Previous 15994 Revisions Next

r9686 Sunday 28th November, 2010 at 19:59:31 UTC by Nathan Woods
More Atari Ace conversions. [Atari Ace]
[src/mess/drivers]a3000.c a310.c a5105.c a51xx.c a6809.c a7150.c abc1600.c ac1.c acrnsys1.c alesis.c amico2k.c apogee.c atm.c basic52.c bbcbc.c ccs2810.c cd2650.c chaos.c chessmst.c clcd.c codata.c d6809.c dectalk.c dm7000.c dms5000.c dms86.c dolphin.c elekscmp.c elektor.c esq1.c et3400.c ex800.c geneve.c h89.c homelab.c horizon.c hp16500.c hx20.c indiana.c instruct.c ipb.c ipc.c ipds.c iq151.c mikrosha.c mits680b.c mk14.c mk85.c mk90.c mmd1.c msbc1.c next.c osborne1.c p112.c p8k.c pcfx.c pcw.c pda600.c pipbug.c pmi80.c prof180x.c qtsbc.c rex6000.c rmnimbus.c rt1715.c rvoice.c sbc6510.c sc1.c sdk85.c sdk86.c selz80.c stopthie.c swtpc.c sys2900.c systec.c ti990_10.c ti990_4.c ti99_4p.c ti99_4x.c ti99_8.c tim011.c tm990189.c uknc.c unior.c unistar.c vk100.c votrpss.c votrtnt.c vt220.c vt240.c vt320.c vt520.c x07.c zsbc3.c
[src/mess/includes]ac1.h homelab.h osborne1.h pc8401a.h pcw.h rmnimbus.h
[src/mess/machine]osborne1.c rmnimbus.c terminal.c
[src/mess/video]pcw.c rmnimbus.c

src/mess/machine/terminal.c
r9685r9686
99typedef struct _terminal_state terminal_state;
1010struct _terminal_state
1111{
12   UINT8 framecnt;
1213   UINT8 buffer[TERMINAL_WIDTH*TERMINAL_HEIGHT];
1314   UINT8 x_pos;
1415   UINT8 y_pos;
r9685r9686
258259   terminal_state *term = get_safe_token(device);
259260   UINT8 options = input_port_read(device->machine, "TERM_CONF");
260261   UINT16 cursor = term->y_pos * TERMINAL_WIDTH + term->x_pos;
261   static UINT8 framecnt=0;
262262   UINT8 y,ra,chr,gfx;
263263   UINT16 sy=0,ma=0,x;
264264
265   framecnt++;
265   term->framecnt++;
266266
267267   for (y = 0; y < TERMINAL_HEIGHT; y++)
268268   {
r9685r9686
279279            {
280280               if ((options & 2) || (ra == 9)) // block, or underline & at bottom line
281281               {
282                  if ((options & 4) && (framecnt & 8)) // want blink & time to blink
282                  if ((options & 4) && (term->framecnt & 8)) // want blink & time to blink
283283                  {
284284                  }
285285                  else
src/mess/machine/osborne1.c
r9685r9686
2828#define RAMMODE      (0x01)
2929
3030
31static struct osborne1
32{
33   UINT8   bank2_enabled;
34   UINT8   bank3_enabled;
35   UINT8   *bank4_ptr;
36   UINT8   *empty_4K;
37   /* IRQ states */
38   int      pia_0_irq_state;
39   int      pia_1_irq_state;
40   /* video related */
41   UINT8   new_start_x;
42   UINT8   new_start_y;
43   emu_timer   *video_timer;
44   UINT8   *charrom;
45   UINT8   charline;
46   UINT8   start_y;
47   /* bankswitch setting */
48   UINT8   bankswitch;
49   UINT8   in_irq_handler;
50   /* beep state */
51   UINT8   beep;
52} osborne1;
53
54
5531WRITE8_HANDLER( osborne1_0000_w )
5632{
33   osborne1_state *state = space->machine->driver_data<osborne1_state>();
5734   /* Check whether regular RAM is enabled */
58   if ( ! osborne1.bank2_enabled || ( osborne1.in_irq_handler && osborne1.bankswitch == RAMMODE ) )
35   if ( ! state->bank2_enabled || ( state->in_irq_handler && state->bankswitch == RAMMODE ) )
5936   {
6037      messram_get_ptr(space->machine->device("messram"))[ offset ] = data;
6138   }
r9685r9686
6441
6542WRITE8_HANDLER( osborne1_1000_w )
6643{
44   osborne1_state *state = space->machine->driver_data<osborne1_state>();
6745   /* Check whether regular RAM is enabled */
68   if ( ! osborne1.bank2_enabled || ( osborne1.in_irq_handler && osborne1.bankswitch == RAMMODE ) )
46   if ( ! state->bank2_enabled || ( state->in_irq_handler && state->bankswitch == RAMMODE ) )
6947   {
7048      messram_get_ptr(space->machine->device("messram"))[ 0x1000 + offset ] = data;
7149   }
r9685r9686
7452
7553READ8_HANDLER( osborne1_2000_r )
7654{
55   osborne1_state *state = space->machine->driver_data<osborne1_state>();
7756   UINT8   data = 0xFF;
7857   running_device *fdc = space->machine->device("mb8877");
7958   running_device *pia_0 = space->machine->device("pia_0" );
8059   running_device *pia_1 = space->machine->device("pia_1" );
8160
8261   /* Check whether regular RAM is enabled */
83   if ( ! osborne1.bank2_enabled )
62   if ( ! state->bank2_enabled )
8463   {
8564      data = messram_get_ptr(space->machine->device("messram"))[ 0x2000 + offset ];
8665   }
r9685r9686
125104
126105WRITE8_HANDLER( osborne1_2000_w )
127106{
107   osborne1_state *state = space->machine->driver_data<osborne1_state>();
128108   running_device *fdc = space->machine->device("mb8877");
129109   running_device *pia_0 = space->machine->device("pia_0" );
130110   running_device *pia_1 = space->machine->device("pia_1" );
131111
132112   /* Check whether regular RAM is enabled */
133   if ( ! osborne1.bank2_enabled )
113   if ( ! state->bank2_enabled )
134114   {
135115      messram_get_ptr(space->machine->device("messram"))[ 0x2000 + offset ] = data;
136116   }
137117   else
138118   {
139      if ( osborne1.in_irq_handler && osborne1.bankswitch == RAMMODE )
119      if ( state->in_irq_handler && state->bankswitch == RAMMODE )
140120      {
141121         messram_get_ptr(space->machine->device("messram"))[ 0x2000 + offset ] = data;
142122      }
r9685r9686
161141
162142WRITE8_HANDLER( osborne1_3000_w )
163143{
144   osborne1_state *state = space->machine->driver_data<osborne1_state>();
164145   /* Check whether regular RAM is enabled */
165   if ( ! osborne1.bank2_enabled || ( osborne1.in_irq_handler && osborne1.bankswitch == RAMMODE ) )
146   if ( ! state->bank2_enabled || ( state->in_irq_handler && state->bankswitch == RAMMODE ) )
166147   {
167148      messram_get_ptr(space->machine->device("messram"))[ 0x3000 + offset ] = data;
168149   }
r9685r9686
171152
172153WRITE8_HANDLER( osborne1_videoram_w )
173154{
155   osborne1_state *state = space->machine->driver_data<osborne1_state>();
174156   /* Check whether the video attribute section is enabled */
175   if ( osborne1.bank3_enabled )
157   if ( state->bank3_enabled )
176158   {
177159      data |= 0x7F;
178160   }
179   osborne1.bank4_ptr[offset] = data;
161   state->bank4_ptr[offset] = data;
180162}
181163
182164
183165WRITE8_HANDLER( osborne1_bankswitch_w )
184166{
167   osborne1_state *state = space->machine->driver_data<osborne1_state>();
185168   switch( offset )
186169   {
187170   case 0x00:
188      osborne1.bank2_enabled = 1;
189      osborne1.bank3_enabled = 0;
171      state->bank2_enabled = 1;
172      state->bank3_enabled = 0;
190173      break;
191174   case 0x01:
192      osborne1.bank2_enabled = 0;
193      osborne1.bank3_enabled = 0;
175      state->bank2_enabled = 0;
176      state->bank3_enabled = 0;
194177      break;
195178   case 0x02:
196      osborne1.bank2_enabled = 1;
197      osborne1.bank3_enabled = 1;
179      state->bank2_enabled = 1;
180      state->bank3_enabled = 1;
198181      break;
199182   case 0x03:
200      osborne1.bank2_enabled = 1;
201      osborne1.bank3_enabled = 0;
183      state->bank2_enabled = 1;
184      state->bank3_enabled = 0;
202185      break;
203186   }
204   if ( osborne1.bank2_enabled )
187   if ( state->bank2_enabled )
205188   {
206189      memory_set_bankptr(space->machine,"bank1", memory_region(space->machine, "maincpu") );
207      memory_set_bankptr(space->machine,"bank2", osborne1.empty_4K );
208      memory_set_bankptr(space->machine,"bank3", osborne1.empty_4K );
190      memory_set_bankptr(space->machine,"bank2", state->empty_4K );
191      memory_set_bankptr(space->machine,"bank3", state->empty_4K );
209192   }
210193   else
211194   {
r9685r9686
213196      memory_set_bankptr(space->machine,"bank2", messram_get_ptr(space->machine->device("messram")) + 0x1000 );
214197      memory_set_bankptr(space->machine,"bank3", messram_get_ptr(space->machine->device("messram")) + 0x3000 );
215198   }
216   osborne1.bank4_ptr = messram_get_ptr(space->machine->device("messram")) + ( ( osborne1.bank3_enabled ) ? 0x10000 : 0xF000 );
217   memory_set_bankptr(space->machine,"bank4", osborne1.bank4_ptr );
218   osborne1.bankswitch = offset;
219   osborne1.in_irq_handler = 0;
199   state->bank4_ptr = messram_get_ptr(space->machine->device("messram")) + ( ( state->bank3_enabled ) ? 0x10000 : 0xF000 );
200   memory_set_bankptr(space->machine,"bank4", state->bank4_ptr );
201   state->bankswitch = offset;
202   state->in_irq_handler = 0;
220203}
221204
222205
223206DIRECT_UPDATE_HANDLER( osborne1_opbase )
224207{
208   osborne1_state *state = machine->driver_data<osborne1_state>();
225209   if ( ( address & 0xF000 ) == 0x2000 )
226210   {
227      if ( ! osborne1.bank2_enabled )
211      if ( ! state->bank2_enabled )
228212      {
229213         direct.explicit_configure(0x2000, 0x2fff, 0x0fff, messram_get_ptr(machine->device("messram")) + 0x2000);
230214         return ~0;
r9685r9686
236220
237221static void osborne1_update_irq_state(running_machine *machine)
238222{
239   //logerror("Changing irq state; pia_0_irq_state = %s, pia_1_irq_state = %s\n", osborne1.pia_0_irq_state ? "SET" : "CLEARED", osborne1.pia_1_irq_state ? "SET" : "CLEARED" );
223   osborne1_state *state = machine->driver_data<osborne1_state>();
224   //logerror("Changing irq state; pia_0_irq_state = %s, pia_1_irq_state = %s\n", state->pia_0_irq_state ? "SET" : "CLEARED", state->pia_1_irq_state ? "SET" : "CLEARED" );
240225
241   if ( osborne1.pia_1_irq_state )
226   if ( state->pia_1_irq_state )
242227   {
243228      cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE );
244229   }
r9685r9686
251236
252237static WRITE_LINE_DEVICE_HANDLER( ieee_pia_irq_a_func )
253238{
254   osborne1.pia_0_irq_state = state;
239   osborne1_state *drvstate = device->machine->driver_data<osborne1_state>();
240   drvstate->pia_0_irq_state = state;
255241   osborne1_update_irq_state(device->machine);
256242}
257243
r9685r9686
280266
281267static WRITE8_DEVICE_HANDLER( video_pia_port_a_w )
282268{
269   osborne1_state *state = device->machine->driver_data<osborne1_state>();
283270   running_device *fdc = device->machine->device("mb8877");
284271
285   osborne1.new_start_x = data >> 1;
272   state->new_start_x = data >> 1;
286273   wd17xx_dden_w(fdc, BIT(data, 0));
287274
288275   //logerror("Video pia port a write: %02X, density set to %s\n", data, data & 1 ? "FM" : "MFM" );
r9685r9686
291278
292279static WRITE8_DEVICE_HANDLER( video_pia_port_b_w )
293280{
281   osborne1_state *state = device->machine->driver_data<osborne1_state>();
294282   running_device *fdc = device->machine->device("mb8877");
295283
296   osborne1.new_start_y = data & 0x1F;
297   osborne1.beep = ( data & 0x20 ) ? 1 : 0;
284   state->new_start_y = data & 0x1F;
285   state->beep = ( data & 0x20 ) ? 1 : 0;
298286   if ( data & 0x40 )
299287   {
300288      wd17xx_set_drive( fdc, 0 );
r9685r9686
309297
310298static WRITE_LINE_DEVICE_HANDLER( video_pia_irq_a_func )
311299{
312   osborne1.pia_1_irq_state = state;
300   osborne1_state *drvstate = device->machine->driver_data<osborne1_state>();
301   drvstate->pia_1_irq_state = state;
313302   osborne1_update_irq_state(device->machine);
314303}
315304
r9685r9686
346335
347336static TIMER_CALLBACK(osborne1_video_callback)
348337{
338   osborne1_state *state = machine->driver_data<osborne1_state>();
349339   address_space* space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
350340   running_device *speaker = space->machine->device("beep");
351341   running_device *pia_1 = space->machine->device("pia_1");
r9685r9686
355345   if ( y == 0 )
356346   {
357347      /* Clear CA1 on video PIA */
358      osborne1.start_y = ( osborne1.new_start_y - 1 ) & 0x1F;
359      osborne1.charline = 0;
348      state->start_y = ( state->new_start_y - 1 ) & 0x1F;
349      state->charline = 0;
360350      pia6821_ca1_w( pia_1, 0 );
361351   }
362352   if ( y == 240 )
r9685r9686
367357   if ( y < 240 )
368358   {
369359      /* Draw a line of the display */
370      UINT16 address = osborne1.start_y * 128 + osborne1.new_start_x + 11;
360      UINT16 address = state->start_y * 128 + state->new_start_x + 11;
371361      UINT16 *p = BITMAP_ADDR16( machine->generic.tmpbitmap, y, 0 );
372362      int x;
373363
r9685r9686
376366         UINT8   character = messram_get_ptr(machine->device("messram"))[ 0xF000 + ( ( address + x ) & 0xFFF ) ];
377367         UINT8   cursor = character & 0x80;
378368         UINT8   dim = messram_get_ptr(machine->device("messram"))[ 0x10000 + ( ( address + x ) & 0xFFF ) ] & 0x80;
379         UINT8   bits = osborne1.charrom[ osborne1.charline * 128 + ( character & 0x7F ) ];
369         UINT8   bits = state->charrom[ state->charline * 128 + ( character & 0x7F ) ];
380370         int      bit;
381371
382         if ( cursor && osborne1.charline == 9 )
372         if ( cursor && state->charline == 9 )
383373         {
384374            bits = 0xFF;
385375         }
r9685r9686
390380         }
391381      }
392382
393      osborne1.charline += 1;
394      if ( osborne1.charline == 10 )
383      state->charline += 1;
384      if ( state->charline == 10 )
395385      {
396         osborne1.start_y += 1;
397         osborne1.charline = 0;
386         state->start_y += 1;
387         state->charline = 0;
398388      }
399389   }
400390
401391   if ( ( y % 10 ) == 2 || ( y % 10 ) == 6 )
402392   {
403      beep_set_state( speaker, osborne1.beep );
393      beep_set_state( speaker, state->beep );
404394   }
405395   else
406396   {
407397      beep_set_state( speaker, 0 );
408398   }
409399
410   timer_adjust_oneshot(osborne1.video_timer, machine->primary_screen->time_until_pos(y + 1, 0 ), 0);
400   timer_adjust_oneshot(state->video_timer, machine->primary_screen->time_until_pos(y + 1, 0 ), 0);
411401}
412402
413403static TIMER_CALLBACK( setup_osborne1 )
r9685r9686
447437
448438MACHINE_RESET( osborne1 )
449439{
440   osborne1_state *state = machine->driver_data<osborne1_state>();
450441   int drive;
451442   address_space* space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
452443   /* Initialize memory configuration */
453444   osborne1_bankswitch_w( space, 0x00, 0 );
454445
455   osborne1.pia_0_irq_state = FALSE;
456   osborne1.pia_1_irq_state = FALSE;
446   state->pia_0_irq_state = FALSE;
447   state->pia_1_irq_state = FALSE;
457448
458   osborne1.pia_1_irq_state = 0;
459   osborne1.in_irq_handler = 0;
449   state->pia_1_irq_state = 0;
450   state->in_irq_handler = 0;
460451
461   osborne1.charrom = memory_region( machine, "gfx1" );
452   state->charrom = memory_region( machine, "gfx1" );
462453
463454   memset( messram_get_ptr(machine->device("messram")) + 0x10000, 0xFF, 0x1000 );
464455
r9685r9686
473464
474465DRIVER_INIT( osborne1 )
475466{
476   memset( &osborne1, 0, sizeof( osborne1 ) );
467   osborne1_state *state = machine->driver_data<osborne1_state>();
477468
478   osborne1.empty_4K = auto_alloc_array(machine, UINT8, 0x1000 );
479   memset( osborne1.empty_4K, 0xFF, 0x1000 );
469   state->empty_4K = auto_alloc_array(machine, UINT8, 0x1000 );
470   memset( state->empty_4K, 0xFF, 0x1000 );
480471
481472   /* Configure the 6850 ACIA */
482473//  acia6850_config( 0, &osborne1_6850_config );
483   osborne1.video_timer = timer_alloc(machine,  osborne1_video_callback , NULL);
484   timer_adjust_oneshot(osborne1.video_timer, machine->primary_screen->time_until_pos(1, 0 ), 0);
474   state->video_timer = timer_alloc(machine,  osborne1_video_callback , NULL);
475   timer_adjust_oneshot(state->video_timer, machine->primary_screen->time_until_pos(1, 0 ), 0);
485476
486477   timer_set(machine,  attotime_zero, NULL, 0, setup_osborne1 );
487478}
r9685r9686
560551
561552int osborne1_daisy_device::z80daisy_irq_state()
562553{
563   return ( osborne1.pia_1_irq_state ? Z80_DAISY_INT : 0 );
554   osborne1_state *state = machine->driver_data<osborne1_state>();
555   return ( state->pia_1_irq_state ? Z80_DAISY_INT : 0 );
564556}
565557
566558
r9685r9686
571563
572564int osborne1_daisy_device::z80daisy_irq_ack()
573565{
566   osborne1_state *state = machine->driver_data<osborne1_state>();
574567   /* Enable ROM and I/O when IRQ is acknowledged */
575   UINT8 old_bankswitch = osborne1.bankswitch;
568   UINT8 old_bankswitch = state->bankswitch;
576569   address_space* space = cputag_get_address_space(device().machine, "maincpu", ADDRESS_SPACE_PROGRAM);
577570
578571   osborne1_bankswitch_w( space, 0, 0 );
579   osborne1.bankswitch = old_bankswitch;
580   osborne1.in_irq_handler = 1;
572   state->bankswitch = old_bankswitch;
573   state->in_irq_handler = 1;
581574   return 0xF8;
582575}
583576
src/mess/machine/rmnimbus.c
r9685r9686
6262
6363/* Debugging */
6464
65#define DEBUG_SET(flags)    ((debug_machine & (flags))==(flags))
66static UINT32 debug_machine;
65#define DEBUG_SET(flags)    ((state->debug_machine & (flags))==(flags))
6766
6867#define DMA_BREAK           0x0000001
6968#define DECODE_BIOS         0x0000002
7069
71/* 80186 internal stuff */
72struct mem_state
73{
74   UINT16       lower;
75   UINT16       upper;
76   UINT16       middle;
77   UINT16       middle_size;
78   UINT16       peripheral;
79};
80
81struct timer_state
82{
83   UINT16       control;
84   UINT16       maxA;
85   UINT16       maxB;
86   UINT16       count;
87   emu_timer   *int_timer;
88   emu_timer   *time_timer;
89   UINT8       time_timer_active;
90   attotime   last_time;
91};
92
93struct dma_state
94{
95   UINT32       source;
96   UINT32       dest;
97   UINT16       count;
98   UINT16       control;
99   UINT8       finished;
100   emu_timer   *finish_timer;
101};
102
103struct intr_state
104{
105   UINT8   pending;
106   UINT16   ack_mask;
107   UINT16   priority_mask;
108   UINT16   in_service;
109   UINT16   request;
110   UINT16   status;
111   UINT16   poll_status;
112   UINT16   timer;
113   UINT16   dma[2];
114   UINT16   ext[4];
115   UINT16  ext_vector[2]; // external vectors, when in cascade mode
116};
117
118static struct i186_state
119{
120   struct timer_state   timer[3];
121   struct dma_state   dma[2];
122   struct intr_state   intr;
123   struct mem_state   mem;
124} i186;
125
126
12770/* Z80 SIO */
12871
12972const z80sio_interface nimbus_sio_intf =
r9685r9686
13679   sio_serial_receive      /* receive handler */
13780};
13881
139static struct keyboard_state
140{
141   UINT8       keyrows[NIMBUS_KEYROWS];
142   emu_timer   *keyscan_timer;
143   UINT8       queue[KEYBOARD_QUEUE_SIZE];
144   UINT8       head;
145   UINT8       tail;
146} keyboard;
147
14882/* Floppy drives WD2793 */
14983
15084static WRITE_LINE_DEVICE_HANDLER( nimbus_fdc_intrq_w );
r9685r9686
15993};
16094
16195
162// Static data related to Floppy and SCSI hard disks
163static struct _nimbus_drives
164{
165    UINT8   reg400;
166    UINT8   reg410_in;
167    UINT8   reg410_out;
168    UINT8   reg418;
169
170    UINT8   drq_ff;
171    UINT8   int_ff;
172} nimbus_drives;
173
174
175/* 8031 Peripheral controler */
176static struct _ipc_interface
177{
178    UINT8   ipc_in;
179    UINT8   ipc_out;
180    UINT8   status_in;
181    UINT8   status_out;
182    UINT8   int_8c_pending;
183    UINT8   int_8e_pending;
184    UINT8   int_8f_pending;
185} ipc_interface;
186
18796static const UINT16 def_config[16] =
18897{
18998    0x0280, 0x017F, 0xE822, 0x8129,
r9685r9686
193102};
194103
195104/* Memory controler */
196static UINT8 mcu_reg080;
197105
198106/* IO Unit */
199static UINT8 iou_reg092;
200107
201108/* Sound */
202static UINT8 last_playmode;
203109
204/* Mouse/Joystick */
205110
206typedef struct
207{
208    UINT8   mouse_px;
209    UINT8   mouse_py;
210
211    UINT8   mouse_x;
212    UINT8   mouse_y;
213    UINT8   mouse_pc;
214    UINT8   mouse_pcx;
215    UINT8   mouse_pcy;
216
217    UINT8   intstate_x;
218    UINT8   intstate_y;
219
220    UINT8   reg0a4;
221
222    emu_timer   *mouse_timer;
223} _mouse_joy_state;
224
225static _mouse_joy_state nimbus_mouse;
226static UINT8 ay8910_a;
227
228111static void drq_callback(running_machine *machine, int which);
229112static void nimbus_recalculate_ints(running_machine *machine);
230113
r9685r9686
259142static void mouse_js_reset(running_machine *machine);
260143static TIMER_CALLBACK(mouse_callback);
261144
262#define num_ioports 0x80
263static UINT16 IOPorts[num_ioports];
264145
265static UINT8 sio_int_state;
266
267146/*************************************
268147 *
269148 *  80186 interrupt controller
r9685r9686
271150 *************************************/
272151static IRQ_CALLBACK(int_callback)
273152{
153   rmnimbus_state *state = device->machine->driver_data<rmnimbus_state>();
274154    UINT8   vector;
275155    UINT16  old;
276156    UINT16  oldreq;
277157
278158   if (LOG_INTERRUPTS)
279      logerror("(%f) **** Acknowledged interrupt vector %02X\n", attotime_to_double(timer_get_time(device->machine)), i186.intr.poll_status & 0x1f);
159      logerror("(%f) **** Acknowledged interrupt vector %02X\n", attotime_to_double(timer_get_time(device->machine)), state->i186.intr.poll_status & 0x1f);
280160
281161   /* clear the interrupt */
282162   cpu_set_input_line(device, 0, CLEAR_LINE);
283   i186.intr.pending = 0;
163   state->i186.intr.pending = 0;
284164
285    oldreq=i186.intr.request;
165   oldreq=state->i186.intr.request;
286166
287167   /* clear the request and set the in-service bit */
288168#if LATCH_INTS
289   i186.intr.request &= ~i186.intr.ack_mask;
169   state->i186.intr.request &= ~state->i186.intr.ack_mask;
290170#else
291   i186.intr.request &= ~(i186.intr.ack_mask & 0x0f);
171   state->i186.intr.request &= ~(state->i186.intr.ack_mask & 0x0f);
292172#endif
293173
294   if((LOG_INTERRUPTS) && (i186.intr.request!=oldreq))
295        logerror("i186.intr.request changed from %02X to %02X\n",oldreq,i186.intr.request);
174   if((LOG_INTERRUPTS) && (state->i186.intr.request!=oldreq))
175      logerror("i186.intr.request changed from %02X to %02X\n",oldreq,state->i186.intr.request);
296176
297    old=i186.intr.in_service;
177   old=state->i186.intr.in_service;
298178
299   i186.intr.in_service |= i186.intr.ack_mask;
179   state->i186.intr.in_service |= state->i186.intr.ack_mask;
300180
301    if((LOG_INTERRUPTS) && (i186.intr.in_service!=old))
302        logerror("i186.intr.in_service changed from %02X to %02X\n",old,i186.intr.in_service);
181   if((LOG_INTERRUPTS) && (state->i186.intr.in_service!=old))
182      logerror("i186.intr.in_service changed from %02X to %02X\n",old,state->i186.intr.in_service);
303183
304    if (i186.intr.ack_mask == 0x0001)
184   if (state->i186.intr.ack_mask == 0x0001)
305185   {
306      switch (i186.intr.poll_status & 0x1f)
186      switch (state->i186.intr.poll_status & 0x1f)
307187      {
308         case 0x08:   i186.intr.status &= ~0x01;   break;
309         case 0x12:   i186.intr.status &= ~0x02;   break;
310         case 0x13:   i186.intr.status &= ~0x04;   break;
188         case 0x08:   state->i186.intr.status &= ~0x01;   break;
189         case 0x12:   state->i186.intr.status &= ~0x02;   break;
190         case 0x13:   state->i186.intr.status &= ~0x04;   break;
311191      }
312192   }
313   i186.intr.ack_mask = 0;
193   state->i186.intr.ack_mask = 0;
314194
315195   /* a request no longer pending */
316   i186.intr.poll_status &= ~0x8000;
196   state->i186.intr.poll_status &= ~0x8000;
317197
318198   /* return the vector */
319    switch(i186.intr.poll_status & 0x1F)
199    switch(state->i186.intr.poll_status & 0x1F)
320200    {
321        case 0x0C   : vector=(i186.intr.ext[0] & EXTINT_CTRL_CASCADE) ? i186.intr.ext_vector[0] : (i186.intr.poll_status & 0x1f); break;
322        case 0x0D   : vector=(i186.intr.ext[1] & EXTINT_CTRL_CASCADE) ? i186.intr.ext_vector[1] : (i186.intr.poll_status & 0x1f); break;
201        case 0x0C   : vector=(state->i186.intr.ext[0] & EXTINT_CTRL_CASCADE) ? state->i186.intr.ext_vector[0] : (state->i186.intr.poll_status & 0x1f); break;
202        case 0x0D   : vector=(state->i186.intr.ext[1] & EXTINT_CTRL_CASCADE) ? state->i186.intr.ext_vector[1] : (state->i186.intr.poll_status & 0x1f); break;
323203        default :
324            vector=i186.intr.poll_status & 0x1f; break;
204            vector=state->i186.intr.poll_status & 0x1f; break;
325205    }
326206
327207    if (LOG_INTERRUPTS)
328   {
329        logerror("i186.intr.ext[0]=%04X i186.intr.ext[1]=%04X\n",i186.intr.ext[0],i186.intr.ext[1]);
330        logerror("Ext vectors : %02X %02X\n",i186.intr.ext_vector[0],i186.intr.ext_vector[1]);
331        logerror("Int %02X Calling vector %02X\n",i186.intr.poll_status,vector);
208    {
209        logerror("i186.intr.ext[0]=%04X i186.intr.ext[1]=%04X\n",state->i186.intr.ext[0],state->i186.intr.ext[1]);
210        logerror("Ext vectors : %02X %02X\n",state->i186.intr.ext_vector[0],state->i186.intr.ext_vector[1]);
211        logerror("Int %02X Calling vector %02X\n",state->i186.intr.poll_status,vector);
332212    }
333213
334214    return vector;
r9685r9686
337217
338218static void update_interrupt_state(running_machine *machine)
339219{
340    int new_vector = 0;
341    int Priority;
342    int IntNo;
220   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
221   int new_vector = 0;
222   int Priority;
223   int IntNo;
343224
344225   if (LOG_INTERRUPTS)
345        logerror("update_interrupt_status: req=%04X stat=%04X serv=%04X priority_mask=%4X\n", i186.intr.request, i186.intr.status, i186.intr.in_service, i186.intr.priority_mask);
226      logerror("update_interrupt_status: req=%04X stat=%04X serv=%04X priority_mask=%4X\n", state->i186.intr.request, state->i186.intr.status, state->i186.intr.in_service, state->i186.intr.priority_mask);
346227
347228   /* loop over priorities */
348   for (Priority = 0; Priority <= i186.intr.priority_mask; Priority++)
229   for (Priority = 0; Priority <= state->i186.intr.priority_mask; Priority++)
349230   {
350231      /* note: by checking 4 bits, we also verify that the mask is off */
351      if ((i186.intr.timer & 0x0F) == Priority)
232      if ((state->i186.intr.timer & 0x0F) == Priority)
352233      {
353234         /* if we're already servicing something at this level, don't generate anything new */
354         if (i186.intr.in_service & 0x01)
235         if (state->i186.intr.in_service & 0x01)
355236            return;
356237
357238         /* if there's something pending, generate an interrupt */
358         if (i186.intr.status & 0x07)
239         if (state->i186.intr.status & 0x07)
359240         {
360            if (i186.intr.status & 1)
241            if (state->i186.intr.status & 1)
361242               new_vector = 0x08;
362            else if (i186.intr.status & 2)
243            else if (state->i186.intr.status & 2)
363244               new_vector = 0x12;
364            else if (i186.intr.status & 4)
245            else if (state->i186.intr.status & 4)
365246               new_vector = 0x13;
366247            else
367248               popmessage("Invalid timer interrupt!");
368249
369250            /* set the clear mask and generate the int */
370            i186.intr.ack_mask = 0x0001;
251            state->i186.intr.ack_mask = 0x0001;
371252            goto generate_int;
372253         }
373254      }
374255
375256      /* check DMA interrupts */
376257      for (IntNo = 0; IntNo < 2; IntNo++)
377         if ((i186.intr.dma[IntNo] & 0x0F) == Priority)
258         if ((state->i186.intr.dma[IntNo] & 0x0F) == Priority)
378259         {
379260            /* if we're already servicing something at this level, don't generate anything new */
380            if (i186.intr.in_service & (0x04 << IntNo))
261            if (state->i186.intr.in_service & (0x04 << IntNo))
381262               return;
382263
383264            /* if there's something pending, generate an interrupt */
384            if (i186.intr.request & (0x04 << IntNo))
265            if (state->i186.intr.request & (0x04 << IntNo))
385266            {
386267               new_vector = 0x0a + IntNo;
387268
388269               /* set the clear mask and generate the int */
389               i186.intr.ack_mask = 0x0004 << IntNo;
270               state->i186.intr.ack_mask = 0x0004 << IntNo;
390271               goto generate_int;
391272            }
392273         }
393274
394        /* check external interrupts */
275      /* check external interrupts */
395276      for (IntNo = 0; IntNo < 4; IntNo++)
396         if ((i186.intr.ext[IntNo] & 0x0F) == Priority)
277         if ((state->i186.intr.ext[IntNo] & 0x0F) == Priority)
397278         {
398                if (LOG_INTERRUPTS)
399                    logerror("Int%d priority=%d\n",IntNo,Priority);
279            if (LOG_INTERRUPTS)
280               logerror("Int%d priority=%d\n",IntNo,Priority);
400281
401                /* if we're already servicing something at this level, don't generate anything new */
402            if (i186.intr.in_service & (0x10 << IntNo))
282            /* if we're already servicing something at this level, don't generate anything new */
283            if (state->i186.intr.in_service & (0x10 << IntNo))
403284               return;
404285
405286            /* if there's something pending, generate an interrupt */
406            if (i186.intr.request & (0x10 << IntNo))
287            if (state->i186.intr.request & (0x10 << IntNo))
407288            {
408289               /* otherwise, generate an interrupt for this request */
409290               new_vector = 0x0c + IntNo;
410291
411292               /* set the clear mask and generate the int */
412               i186.intr.ack_mask = 0x0010 << IntNo;
413                    goto generate_int;
293               state->i186.intr.ack_mask = 0x0010 << IntNo;
294               goto generate_int;
414295            }
415296         }
416297   }
r9685r9686
418299
419300generate_int:
420301   /* generate the appropriate interrupt */
421   i186.intr.poll_status = 0x8000 | new_vector;
422   if (!i186.intr.pending)
302   state->i186.intr.poll_status = 0x8000 | new_vector;
303   if (!state->i186.intr.pending)
423304      cputag_set_input_line(machine, MAINCPU_TAG, 0, ASSERT_LINE);
424   i186.intr.pending = 1;
305   state->i186.intr.pending = 1;
425306   cpuexec_trigger(machine, CPU_RESUME_TRIGGER);
426307   if (LOG_OPTIMIZATION) logerror("  - trigger due to interrupt pending\n");
427308   if (LOG_INTERRUPTS) logerror("(%f) **** Requesting interrupt vector %02X\n", attotime_to_double(timer_get_time(machine)), new_vector);
r9685r9686
430311
431312static void handle_eoi(running_machine *machine,int data)
432313{
433    int Priority;
434    int IntNo;
435    int handled=0;
314   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
315   int Priority;
316   int IntNo;
317   int handled=0;
436318
437319   /* specific case */
438320   if (!(data & 0x8000))
r9685r9686
440322      /* turn off the appropriate in-service bit */
441323      switch (data & 0x1f)
442324      {
443         case 0x08:   i186.intr.in_service &= ~0x01;   break;
444         case 0x12:   i186.intr.in_service &= ~0x01;   break;
445         case 0x13:   i186.intr.in_service &= ~0x01;   break;
446         case 0x0a:   i186.intr.in_service &= ~0x04;   break;
447         case 0x0b:   i186.intr.in_service &= ~0x08;   break;
448         case 0x0c:   i186.intr.in_service &= ~0x10;   break;
449         case 0x0d:   i186.intr.in_service &= ~0x20;   break;
450         case 0x0e:   i186.intr.in_service &= ~0x40;   break;
451         case 0x0f:   i186.intr.in_service &= ~0x80;   break;
325         case 0x08:   state->i186.intr.in_service &= ~0x01;   break;
326         case 0x12:   state->i186.intr.in_service &= ~0x01;   break;
327         case 0x13:   state->i186.intr.in_service &= ~0x01;   break;
328         case 0x0a:   state->i186.intr.in_service &= ~0x04;   break;
329         case 0x0b:   state->i186.intr.in_service &= ~0x08;   break;
330         case 0x0c:   state->i186.intr.in_service &= ~0x10;   break;
331         case 0x0d:   state->i186.intr.in_service &= ~0x20;   break;
332         case 0x0e:   state->i186.intr.in_service &= ~0x40;   break;
333         case 0x0f:   state->i186.intr.in_service &= ~0x80;   break;
452334         default:   logerror("%05X:ERROR - 80186 EOI with unknown vector %02X\n", cpu_get_pc(machine->device(MAINCPU_TAG)), data & 0x1f);
453335      }
454336      if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for vector %02X\n", attotime_to_double(timer_get_time(machine)), data & 0x1f);
r9685r9686
461343      for (Priority = 0; ((Priority <= 7) && !handled); Priority++)
462344      {
463345         /* check for in-service timers */
464         if ((i186.intr.timer & 0x07) == Priority && (i186.intr.in_service & 0x01))
346         if ((state->i186.intr.timer & 0x07) == Priority && (state->i186.intr.in_service & 0x01))
465347         {
466            i186.intr.in_service &= ~0x01;
348            state->i186.intr.in_service &= ~0x01;
467349            if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for timer\n", attotime_to_double(timer_get_time(machine)));
468350            handled=1;
469351         }
470352
471353         /* check for in-service DMA interrupts */
472354         for (IntNo = 0; ((IntNo < 2) && !handled) ; IntNo++)
473            if ((i186.intr.dma[IntNo] & 0x07) == Priority && (i186.intr.in_service & (0x04 << IntNo)))
355            if ((state->i186.intr.dma[IntNo] & 0x07) == Priority && (state->i186.intr.in_service & (0x04 << IntNo)))
474356            {
475               i186.intr.in_service &= ~(0x04 << IntNo);
357               state->i186.intr.in_service &= ~(0x04 << IntNo);
476358               if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for DMA%d\n", attotime_to_double(timer_get_time(machine)), IntNo);
477359               handled=1;
478360            }
479361
480362         /* check external interrupts */
481363         for (IntNo = 0; ((IntNo < 4) && !handled) ; IntNo++)
482            if ((i186.intr.ext[IntNo] & 0x07) == Priority && (i186.intr.in_service & (0x10 << IntNo)))
364            if ((state->i186.intr.ext[IntNo] & 0x07) == Priority && (state->i186.intr.in_service & (0x10 << IntNo)))
483365            {
484               i186.intr.in_service &= ~(0x10 << IntNo);
366               state->i186.intr.in_service &= ~(0x10 << IntNo);
485367               if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for INT%d\n", attotime_to_double(timer_get_time(machine)), IntNo);
486368               handled=1;
487369            }
488370      }
489371   }
490    nimbus_recalculate_ints(machine);
372   nimbus_recalculate_ints(machine);
491373}
492374
493375/* Trigger an external interupt, optionally supplying the vector to take */
494376static void external_int(running_machine *machine, UINT16 intno, UINT8 vector)
495377{
378   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
496379   if (LOG_INTERRUPTS_EXT) logerror("generating external int %02X, vector %02X\n",intno,vector);
497380
498381    // Only 4 external ints
r9685r9686
506389    // int 0 & int 1
507390    if (intno<2)
508391    {
509        if(i186.intr.ext[intno] & EXTINT_CTRL_CASCADE)
510            i186.intr.ext_vector[intno]=vector;
392        if(state->i186.intr.ext[intno] & EXTINT_CTRL_CASCADE)
393            state->i186.intr.ext_vector[intno]=vector;
511394    }
512395
513396    // Turn on the requested request bit and handle interrupt
514    i186.intr.request |= (0x010 << intno);
397    state->i186.intr.request |= (0x010 << intno);
515398    update_interrupt_state(machine);
516399}
517400
518401static void nimbus_recalculate_ints(running_machine *machine)
519402{
520    if((iou_reg092 & DISK_INT_ENABLE) && nimbus_drives.int_ff)
403   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
404    if((state->iou_reg092 & DISK_INT_ENABLE) && state->nimbus_drives.int_ff)
521405    {
522        nimbus_drives.int_ff=0;
406        state->nimbus_drives.int_ff=0;
523407        external_int(machine,0,EXTERNAL_INT_DISK);
524408    }
525409}
r9685r9686
532416
533417static TIMER_CALLBACK(internal_timer_int)
534418{
419   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
535420   int which = param;
536   struct timer_state *t = &i186.timer[which];
421   struct timer_state *t = &state->i186.timer[which];
537422
538423   if (LOG_TIMER) logerror("Hit interrupt callback for timer %d\n", which);
539424
r9685r9686
543428   /* request an interrupt */
544429   if (t->control & 0x2000)
545430   {
546      i186.intr.status |= 0x01 << which;
431      state->i186.intr.status |= 0x01 << which;
547432      update_interrupt_state(machine);
548433      if (LOG_TIMER) logerror("  Generating timer interrupt\n");
549434   }
r9685r9686
560445}
561446
562447
563static void internal_timer_sync(int which)
448static void internal_timer_sync(running_machine *machine, int which)
564449{
565   struct timer_state *t = &i186.timer[which];
450   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
451   struct timer_state *t = &state->i186.timer[which];
566452
567453   /* if we have a timing timer running, adjust the count */
568454   if (t->time_timer_active)
r9685r9686
585471
586472
587473static void internal_timer_update(running_machine *machine,
588                          int which,
474                                  int which,
589475                                  int new_count,
590476                                  int new_maxA,
591477                                  int new_maxB,
592478                                  int new_control)
593479{
594   struct timer_state *t = &i186.timer[which];
480   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
481   struct timer_state *t = &state->i186.timer[which];
595482   int update_int_timer = 0;
596483
597    if (LOG_TIMER)
598        logerror("internal_timer_update: %d, new_count=%d, new_maxA=%d, new_maxB=%d,new_control=%d\n",which,new_count,new_maxA,new_maxB,new_control);
484   if (LOG_TIMER)
485      logerror("internal_timer_update: %d, new_count=%d, new_maxA=%d, new_maxB=%d,new_control=%d\n",which,new_count,new_maxA,new_maxB,new_control);
599486
600487   /* if we have a new count and we're on, update things */
601488   if (new_count != -1)
602489   {
603490      if (t->control & 0x8000)
604491      {
605         internal_timer_sync(which);
492         internal_timer_sync(machine, which);
606493         update_int_timer = 1;
607494      }
608495      t->count = new_count;
r9685r9686
613500   {
614501      if (t->control & 0x8000)
615502      {
616         internal_timer_sync(which);
503         internal_timer_sync(machine, which);
617504         update_int_timer = 1;
618505      }
619506      t->maxA = new_maxA;
r9685r9686
628515   {
629516      if (t->control & 0x8000)
630517      {
631         internal_timer_sync(which);
518         internal_timer_sync(machine, which);
632519         update_int_timer = 1;
633520      }
634521
r9685r9686
657544      /* check for control bits we don't handle */
658545      diff = new_control ^ t->control;
659546      if (diff & 0x001c)
660        logerror("%05X:ERROR! -unsupported timer mode %04X\n",
547         logerror("%05X:ERROR! -unsupported timer mode %04X\n",
661548            cpu_get_pc(machine->device(MAINCPU_TAG)), new_control);
662549
663550      /* if we have real changes, update things */
r9685r9686
668555         if ((diff & 0x8000) && !(new_control & 0x8000))
669556         {
670557            /* compute the final count */
671            internal_timer_sync(which);
558            internal_timer_sync(machine, which);
672559
673560            /* nuke the timer and force the interrupt timer to be recomputed */
674561            timer_adjust_oneshot(t->time_timer, attotime_never, which);
r9685r9686
688575         /* if something about the interrupt timer changed, force an update */
689576         if (!(diff & 0x8000) && (diff & 0x2000))
690577         {
691            internal_timer_sync(which);
578            internal_timer_sync(machine, which);
692579            update_int_timer = 1;
693580         }
694581      }
r9685r9686
700587   /* update the interrupt timer */
701588   if (update_int_timer)
702589   {
703          if ((t->control & 0x8000) && (t->control & 0x2000))
704          {
705              int diff = t->maxA - t->count;
706              if (diff <= 0)
707                 diff += 0x10000;
708              timer_adjust_oneshot(t->int_timer, attotime_mul(ATTOTIME_IN_HZ(2000000), diff), which);
709              if (LOG_TIMER) logerror("Set interrupt timer for %d\n", which);
710          }
711          else
712          {
713              timer_adjust_oneshot(t->int_timer, attotime_never, which);
714          }
590      if ((t->control & 0x8000) && (t->control & 0x2000))
591      {
592         int diff = t->maxA - t->count;
593         if (diff <= 0)
594            diff += 0x10000;
595         timer_adjust_oneshot(t->int_timer, attotime_mul(ATTOTIME_IN_HZ(2000000), diff), which);
596         if (LOG_TIMER) logerror("Set interrupt timer for %d\n", which);
597      }
598      else
599      {
600         timer_adjust_oneshot(t->int_timer, attotime_never, which);
601      }
715602   }
716603}
717604
r9685r9686
725612
726613static TIMER_CALLBACK(dma_timer_callback)
727614{
615   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
728616   int which = param;
729   struct dma_state *d = &i186.dma[which];
617   struct dma_state *d = &state->i186.dma[which];
730618
731619   /* complete the status update */
732620   d->control &= ~0x0002;
r9685r9686
737625   if (d->control & 0x0100)
738626   {
739627      if (LOG_DMA>1) logerror("DMA%d timer callback - requesting interrupt: count = %04X, source = %04X\n", which, d->count, d->source);
740      i186.intr.request |= 0x04 << which;
628      state->i186.intr.request |= 0x04 << which;
741629      update_interrupt_state(machine);
742630   }
743631}
r9685r9686
745633
746634static void update_dma_control(running_machine *machine, int which, int new_control)
747635{
748   struct dma_state *d = &i186.dma[which];
636   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
637   struct dma_state *d = &state->i186.dma[which];
749638   int diff;
750639
751640   /* handle the CHG bit */
752641   if (!(new_control & CHG_NOCHG))
753     new_control = (new_control & ~ST_STOP) | (d->control & ST_STOP);
642      new_control = (new_control & ~ST_STOP) | (d->control & ST_STOP);
754643   new_control &= ~CHG_NOCHG;
755644
756645   /* check for control bits we don't handle */
757646   diff = new_control ^ d->control;
758647   if ((LOG_DMA) && (diff & 0x6811))
759     logerror("%05X:ERROR! - unsupported DMA mode %04X\n",
760         cpu_get_pc(machine->device(MAINCPU_TAG)), new_control);
648      logerror("%05X:ERROR! - unsupported DMA mode %04X\n",
649         cpu_get_pc(machine->device(MAINCPU_TAG)), new_control);
761650
762651   /* if we're going live, set a timer */
763652   if ((diff & 0x0002) && (new_control & 0x0002))
r9685r9686
783672      }
784673   }
785674
786    if (LOG_DMA) logerror("Initiated DMA %d - count = %04X, source = %04X, dest = %04X\n", which, d->count, d->source, d->dest);
787    if (DEBUG_SET(DMA_BREAK))
788        debugger_break(machine);
675   if (LOG_DMA) logerror("Initiated DMA %d - count = %04X, source = %04X, dest = %04X\n", which, d->count, d->source, d->dest);
676   if (DEBUG_SET(DMA_BREAK))
677      debugger_break(machine);
789678
790679   /* set the new control register */
791680   d->control = new_control;
r9685r9686
793682
794683static void drq_callback(running_machine *machine, int which)
795684{
796    struct dma_state *dma = &i186.dma[which];
685   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
686   struct dma_state *dma = &state->i186.dma[which];
797687   address_space *memory_space   = cpu_get_address_space(machine->device(MAINCPU_TAG), ADDRESS_SPACE_PROGRAM);
798    address_space *io_space       = cpu_get_address_space(machine->device(MAINCPU_TAG), ADDRESS_SPACE_IO);
688   address_space *io_space       = cpu_get_address_space(machine->device(MAINCPU_TAG), ADDRESS_SPACE_IO);
799689
800690    address_space *src_space;
801691    address_space *dest_space;
r9685r9686
810700    if(!(dma->control & ST_STOP))
811701    {
812702        logerror("%05X:ERROR! - drq%d with dma channel stopped\n",
813         cpu_get_pc(machine->device(MAINCPU_TAG)), which);
703      cpu_get_pc(machine->device(MAINCPU_TAG)), which);
814704
815705        return;
816706    }
r9685r9686
866756    if((dma->control & INTERRUPT_ON_ZERO) && (dma->count==0))
867757    {
868758      if (LOG_DMA>1) logerror("DMA%d - requesting interrupt: count = %04X, source = %04X\n", which, dma->count, dma->source);
869      i186.intr.request |= 0x04 << which;
759      state->i186.intr.request |= 0x04 << which;
870760      update_interrupt_state(machine);
871761    }
872762}
r9685r9686
877767/*-------------------------------------------------------------------------*/
878768static void nimbus_cpu_init(running_machine *machine)
879769{
770   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
771   logerror("Machine reset\n");
880772
881    logerror("Machine reset\n");
882
883773   /* create timers here so they stick around */
884   i186.timer[0].int_timer = timer_alloc(machine, internal_timer_int, NULL);
885   i186.timer[1].int_timer = timer_alloc(machine, internal_timer_int, NULL);
886   i186.timer[2].int_timer = timer_alloc(machine, internal_timer_int, NULL);
887   i186.timer[0].time_timer = timer_alloc(machine, NULL, NULL);
888   i186.timer[1].time_timer = timer_alloc(machine, NULL, NULL);
889   i186.timer[2].time_timer = timer_alloc(machine, NULL, NULL);
890   i186.dma[0].finish_timer = timer_alloc(machine, dma_timer_callback, NULL);
891   i186.dma[1].finish_timer = timer_alloc(machine, dma_timer_callback, NULL);
774   state->i186.timer[0].int_timer = timer_alloc(machine, internal_timer_int, NULL);
775   state->i186.timer[1].int_timer = timer_alloc(machine, internal_timer_int, NULL);
776   state->i186.timer[2].int_timer = timer_alloc(machine, internal_timer_int, NULL);
777   state->i186.timer[0].time_timer = timer_alloc(machine, NULL, NULL);
778   state->i186.timer[1].time_timer = timer_alloc(machine, NULL, NULL);
779   state->i186.timer[2].time_timer = timer_alloc(machine, NULL, NULL);
780   state->i186.dma[0].finish_timer = timer_alloc(machine, dma_timer_callback, NULL);
781   state->i186.dma[1].finish_timer = timer_alloc(machine, dma_timer_callback, NULL);
892782}
893783
894784static void nimbus_cpu_reset(running_machine *machine)
895785{
786   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
896787   /* reset the interrupt state */
897   i186.intr.priority_mask       = 0x0007;
898   i186.intr.timer          = 0x000f;
899   i186.intr.dma[0]         = 0x000f;
900   i186.intr.dma[1]         = 0x000f;
901   i186.intr.ext[0]         = 0x000f;
902   i186.intr.ext[1]         = 0x000f;
903   i186.intr.ext[2]         = 0x000f;
904   i186.intr.ext[3]         = 0x000f;
905    i186.intr.in_service        = 0x0000;
788   state->i186.intr.priority_mask      = 0x0007;
789   state->i186.intr.timer          = 0x000f;
790   state->i186.intr.dma[0]         = 0x000f;
791   state->i186.intr.dma[1]         = 0x000f;
792   state->i186.intr.ext[0]         = 0x000f;
793   state->i186.intr.ext[1]         = 0x000f;
794   state->i186.intr.ext[2]         = 0x000f;
795   state->i186.intr.ext[3]         = 0x000f;
796   state->i186.intr.in_service      = 0x0000;
906797
907    /* External vectors by default to internal int 0/1 vectors */
908    i186.intr.ext_vector[0]      = 0x000C;
909   i186.intr.ext_vector[1]      = 0x000D;
798   /* External vectors by default to internal int 0/1 vectors */
799   state->i186.intr.ext_vector[0]      = 0x000C;
800   state->i186.intr.ext_vector[1]      = 0x000D;
910801
911    i186.intr.pending           = 0x0000;
912   i186.intr.ack_mask          = 0x0000;
913   i186.intr.request           = 0x0000;
914   i186.intr.status            = 0x0000;
915   i186.intr.poll_status       = 0x0000;
802   state->i186.intr.pending           = 0x0000;
803   state->i186.intr.ack_mask          = 0x0000;
804   state->i186.intr.request           = 0x0000;
805   state->i186.intr.status            = 0x0000;
806   state->i186.intr.poll_status       = 0x0000;
916807
917    logerror("CPU reset done\n");
808   logerror("CPU reset done\n");
918809}
919810
920811READ16_HANDLER( nimbus_i186_internal_port_r )
921812{
813   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
922814   int temp, which;
923815
924816   switch (offset)
r9685r9686
929821
930822      case 0x12:
931823         if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll\n", cpu_get_pc(space->cpu));
932         if (i186.intr.poll_status & 0x8000)
824         if (state->i186.intr.poll_status & 0x8000)
933825            int_callback(space->machine->device(MAINCPU_TAG), 0);
934         return i186.intr.poll_status;
826         return state->i186.intr.poll_status;
935827
936828      case 0x13:
937829         if (LOG_PORTS) logerror("%05X:read 80186 interrupt poll status\n", cpu_get_pc(space->cpu));
938         return i186.intr.poll_status;
830         return state->i186.intr.poll_status;
939831
940832      case 0x14:
941833         if (LOG_PORTS) logerror("%05X:read 80186 interrupt mask\n", cpu_get_pc(space->cpu));
942         temp  = (i186.intr.timer  >> 3) & 0x01;
943         temp |= (i186.intr.dma[0] >> 1) & 0x04;
944         temp |= (i186.intr.dma[1] >> 0) & 0x08;
945         temp |= (i186.intr.ext[0] << 1) & 0x10;
946         temp |= (i186.intr.ext[1] << 2) & 0x20;
947         temp |= (i186.intr.ext[2] << 3) & 0x40;
948         temp |= (i186.intr.ext[3] << 4) & 0x80;
834         temp  = (state->i186.intr.timer  >> 3) & 0x01;
835         temp |= (state->i186.intr.dma[0] >> 1) & 0x04;
836         temp |= (state->i186.intr.dma[1] >> 0) & 0x08;
837         temp |= (state->i186.intr.ext[0] << 1) & 0x10;
838         temp |= (state->i186.intr.ext[1] << 2) & 0x20;
839         temp |= (state->i186.intr.ext[2] << 3) & 0x40;
840         temp |= (state->i186.intr.ext[3] << 4) & 0x80;
949841         return temp;
950842
951843      case 0x15:
952844         if (LOG_PORTS) logerror("%05X:read 80186 interrupt priority mask\n", cpu_get_pc(space->cpu));
953         return i186.intr.priority_mask;
845         return state->i186.intr.priority_mask;
954846
955847      case 0x16:
956848         if (LOG_PORTS) logerror("%05X:read 80186 interrupt in-service\n", cpu_get_pc(space->cpu));
957         return i186.intr.in_service;
849         return state->i186.intr.in_service;
958850
959851      case 0x17:
960852         if (LOG_PORTS) logerror("%05X:read 80186 interrupt request\n", cpu_get_pc(space->cpu));
961         temp = i186.intr.request & ~0x0001;
962         if (i186.intr.status & 0x0007)
853         temp = state->i186.intr.request & ~0x0001;
854         if (state->i186.intr.status & 0x0007)
963855            temp |= 1;
964856         return temp;
965857
966858      case 0x18:
967859         if (LOG_PORTS) logerror("%05X:read 80186 interrupt status\n", cpu_get_pc(space->cpu));
968         return i186.intr.status;
860         return state->i186.intr.status;
969861
970862      case 0x19:
971863         if (LOG_PORTS) logerror("%05X:read 80186 timer interrupt control\n", cpu_get_pc(space->cpu));
972         return i186.intr.timer;
864         return state->i186.intr.timer;
973865
974866      case 0x1a:
975867         if (LOG_PORTS) logerror("%05X:read 80186 DMA 0 interrupt control\n", cpu_get_pc(space->cpu));
976         return i186.intr.dma[0];
868         return state->i186.intr.dma[0];
977869
978870      case 0x1b:
979871         if (LOG_PORTS) logerror("%05X:read 80186 DMA 1 interrupt control\n", cpu_get_pc(space->cpu));
980         return i186.intr.dma[1];
872         return state->i186.intr.dma[1];
981873
982874      case 0x1c:
983875         if (LOG_PORTS) logerror("%05X:read 80186 INT 0 interrupt control\n", cpu_get_pc(space->cpu));
984         return i186.intr.ext[0];
876         return state->i186.intr.ext[0];
985877
986878      case 0x1d:
987879         if (LOG_PORTS) logerror("%05X:read 80186 INT 1 interrupt control\n", cpu_get_pc(space->cpu));
988         return i186.intr.ext[1];
880         return state->i186.intr.ext[1];
989881
990882      case 0x1e:
991883         if (LOG_PORTS) logerror("%05X:read 80186 INT 2 interrupt control\n", cpu_get_pc(space->cpu));
992         return i186.intr.ext[2];
884         return state->i186.intr.ext[2];
993885
994886      case 0x1f:
995887         if (LOG_PORTS) logerror("%05X:read 80186 INT 3 interrupt control\n", cpu_get_pc(space->cpu));
996         return i186.intr.ext[3];
888         return state->i186.intr.ext[3];
997889
998890      case 0x28:
999891      case 0x2c:
r9685r9686
1001893         if (LOG_PORTS) logerror("%05X:read 80186 Timer %d count\n", cpu_get_pc(space->cpu), (offset - 0x28) / 4);
1002894         which = (offset - 0x28) / 4;
1003895         if (!(offset & 1))
1004            internal_timer_sync(which);
1005         return i186.timer[which].count;
896            internal_timer_sync(space->machine, which);
897         return state->i186.timer[which].count;
1006898
1007899      case 0x29:
1008900      case 0x2d:
1009901      case 0x31:
1010902         if (LOG_PORTS) logerror("%05X:read 80186 Timer %d max A\n", cpu_get_pc(space->cpu), (offset - 0x29) / 4);
1011903         which = (offset - 0x29) / 4;
1012         return i186.timer[which].maxA;
904         return state->i186.timer[which].maxA;
1013905
1014906      case 0x2a:
1015907      case 0x2e:
1016908         logerror("%05X:read 80186 Timer %d max B\n", cpu_get_pc(space->cpu), (offset - 0x2a) / 4);
1017909         which = (offset - 0x2a) / 4;
1018         return i186.timer[which].maxB;
910         return state->i186.timer[which].maxB;
1019911
1020912      case 0x2b:
1021913      case 0x2f:
1022914      case 0x33:
1023915         if (LOG_PORTS) logerror("%05X:read 80186 Timer %d control\n", cpu_get_pc(space->cpu), (offset - 0x2b) / 4);
1024916         which = (offset - 0x2b) / 4;
1025         return i186.timer[which].control;
917         return state->i186.timer[which].control;
1026918
1027919      case 0x50:
1028920         if (LOG_PORTS) logerror("%05X:read 80186 upper chip select\n", cpu_get_pc(space->cpu));
1029         return i186.mem.upper;
921         return state->i186.mem.upper;
1030922
1031923      case 0x51:
1032924         if (LOG_PORTS) logerror("%05X:read 80186 lower chip select\n", cpu_get_pc(space->cpu));
1033         return i186.mem.lower;
925         return state->i186.mem.lower;
1034926
1035927      case 0x52:
1036928         if (LOG_PORTS) logerror("%05X:read 80186 peripheral chip select\n", cpu_get_pc(space->cpu));
1037         return i186.mem.peripheral;
929         return state->i186.mem.peripheral;
1038930
1039931      case 0x53:
1040932         if (LOG_PORTS) logerror("%05X:read 80186 middle chip select\n", cpu_get_pc(space->cpu));
1041         return i186.mem.middle;
933         return state->i186.mem.middle;
1042934
1043935      case 0x54:
1044936         if (LOG_PORTS) logerror("%05X:read 80186 middle P chip select\n", cpu_get_pc(space->cpu));
1045         return i186.mem.middle_size;
937         return state->i186.mem.middle_size;
1046938
1047939      case 0x60:
1048940      case 0x68:
1049941         if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower source address\n", cpu_get_pc(space->cpu), (offset - 0x60) / 8);
1050942         which = (offset - 0x60) / 8;
1051         return i186.dma[which].source;
943         return state->i186.dma[which].source;
1052944
1053945      case 0x61:
1054946      case 0x69:
1055947         if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper source address\n", cpu_get_pc(space->cpu), (offset - 0x61) / 8);
1056948         which = (offset - 0x61) / 8;
1057         return i186.dma[which].source >> 16;
949         return state->i186.dma[which].source >> 16;
1058950
1059951      case 0x62:
1060952      case 0x6a:
1061953         if (LOG_PORTS) logerror("%05X:read 80186 DMA%d lower dest address\n", cpu_get_pc(space->cpu), (offset - 0x62) / 8);
1062954         which = (offset - 0x62) / 8;
1063         return i186.dma[which].dest;
955         return state->i186.dma[which].dest;
1064956
1065957      case 0x63:
1066958      case 0x6b:
1067959         if (LOG_PORTS) logerror("%05X:read 80186 DMA%d upper dest address\n", cpu_get_pc(space->cpu), (offset - 0x63) / 8);
1068960         which = (offset - 0x63) / 8;
1069         return i186.dma[which].dest >> 16;
961         return state->i186.dma[which].dest >> 16;
1070962
1071963      case 0x64:
1072964      case 0x6c:
1073965         if (LOG_PORTS) logerror("%05X:read 80186 DMA%d transfer count\n", cpu_get_pc(space->cpu), (offset - 0x64) / 8);
1074966         which = (offset - 0x64) / 8;
1075         return i186.dma[which].count;
967         return state->i186.dma[which].count;
1076968
1077969      case 0x65:
1078970      case 0x6d:
1079971         if (LOG_PORTS) logerror("%05X:read 80186 DMA%d control\n", cpu_get_pc(space->cpu), (offset - 0x65) / 8);
1080972         which = (offset - 0x65) / 8;
1081         return i186.dma[which].control;
973         return state->i186.dma[which].control;
1082974
1083975      default:
1084976         logerror("%05X:read 80186 port %02X\n", cpu_get_pc(space->cpu), offset);
r9685r9686
1095987
1096988WRITE16_HANDLER( nimbus_i186_internal_port_w )
1097989{
990   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
1098991   int temp, which, data16 = data;
1099992
1100993   switch (offset)
r9685r9686
11151008
11161009      case 0x14:
11171010         if (LOG_PORTS) logerror("%05X:80186 interrupt mask = %04X\n", cpu_get_pc(space->cpu), data16);
1118         i186.intr.timer  = (i186.intr.timer  & ~0x08) | ((data16 << 3) & 0x08);
1119         i186.intr.dma[0] = (i186.intr.dma[0] & ~0x08) | ((data16 << 1) & 0x08);
1120         i186.intr.dma[1] = (i186.intr.dma[1] & ~0x08) | ((data16 << 0) & 0x08);
1121         i186.intr.ext[0] = (i186.intr.ext[0] & ~0x08) | ((data16 >> 1) & 0x08);
1122         i186.intr.ext[1] = (i186.intr.ext[1] & ~0x08) | ((data16 >> 2) & 0x08);
1123         i186.intr.ext[2] = (i186.intr.ext[2] & ~0x08) | ((data16 >> 3) & 0x08);
1124         i186.intr.ext[3] = (i186.intr.ext[3] & ~0x08) | ((data16 >> 4) & 0x08);
1011         state->i186.intr.timer  = (state->i186.intr.timer  & ~0x08) | ((data16 << 3) & 0x08);
1012         state->i186.intr.dma[0] = (state->i186.intr.dma[0] & ~0x08) | ((data16 << 1) & 0x08);
1013         state->i186.intr.dma[1] = (state->i186.intr.dma[1] & ~0x08) | ((data16 << 0) & 0x08);
1014         state->i186.intr.ext[0] = (state->i186.intr.ext[0] & ~0x08) | ((data16 >> 1) & 0x08);
1015         state->i186.intr.ext[1] = (state->i186.intr.ext[1] & ~0x08) | ((data16 >> 2) & 0x08);
1016         state->i186.intr.ext[2] = (state->i186.intr.ext[2] & ~0x08) | ((data16 >> 3) & 0x08);
1017         state->i186.intr.ext[3] = (state->i186.intr.ext[3] & ~0x08) | ((data16 >> 4) & 0x08);
11251018         update_interrupt_state(space->machine);
11261019         break;
11271020
11281021      case 0x15:
11291022         if (LOG_PORTS) logerror("%05X:80186 interrupt priority mask = %04X\n", cpu_get_pc(space->cpu), data16);
1130         i186.intr.priority_mask = data16 & 0x0007;
1023         state->i186.intr.priority_mask = data16 & 0x0007;
11311024         update_interrupt_state(space->machine);
11321025         break;
11331026
11341027      case 0x16:
11351028         if (LOG_PORTS) logerror("%05X:80186 interrupt in-service = %04X\n", cpu_get_pc(space->cpu), data16);
1136         i186.intr.in_service = data16 & 0x00ff;
1029         state->i186.intr.in_service = data16 & 0x00ff;
11371030         update_interrupt_state(space->machine);
11381031         break;
11391032
11401033      case 0x17:
11411034         if (LOG_PORTS) logerror("%05X:80186 interrupt request = %04X\n", cpu_get_pc(space->cpu), data16);
1142         i186.intr.request = (i186.intr.request & ~0x00c0) | (data16 & 0x00c0);
1035         state->i186.intr.request = (state->i186.intr.request & ~0x00c0) | (data16 & 0x00c0);
11431036         update_interrupt_state(space->machine);
11441037         break;
11451038
11461039      case 0x18:
11471040         if (LOG_PORTS) logerror("%05X:WARNING - wrote to 80186 interrupt status = %04X\n", cpu_get_pc(space->cpu), data16);
1148         i186.intr.status = (i186.intr.status & ~0x8007) | (data16 & 0x8007);
1041         state->i186.intr.status = (state->i186.intr.status & ~0x8007) | (data16 & 0x8007);
11491042         update_interrupt_state(space->machine);
11501043         break;
11511044
11521045      case 0x19:
11531046         if (LOG_PORTS) logerror("%05X:80186 timer interrupt contol = %04X\n", cpu_get_pc(space->cpu), data16);
1154         i186.intr.timer = data16 & 0x000f;
1047         state->i186.intr.timer = data16 & 0x000f;
11551048         break;
11561049
11571050      case 0x1a:
11581051         if (LOG_PORTS) logerror("%05X:80186 DMA 0 interrupt control = %04X\n", cpu_get_pc(space->cpu), data16);
1159         i186.intr.dma[0] = data16 & 0x000f;
1052         state->i186.intr.dma[0] = data16 & 0x000f;
11601053         break;
11611054
11621055      case 0x1b:
11631056         if (LOG_PORTS) logerror("%05X:80186 DMA 1 interrupt control = %04X\n", cpu_get_pc(space->cpu), data16);
1164         i186.intr.dma[1] = data16 & 0x000f;
1057         state->i186.intr.dma[1] = data16 & 0x000f;
11651058         break;
11661059
11671060      case 0x1c:
11681061         if (LOG_PORTS) logerror("%05X:80186 INT 0 interrupt control = %04X\n", cpu_get_pc(space->cpu), data16);
1169         i186.intr.ext[0] = data16 & 0x007f;
1062         state->i186.intr.ext[0] = data16 & 0x007f;
11701063         break;
11711064
11721065      case 0x1d:
11731066         if (LOG_PORTS) logerror("%05X:80186 INT 1 interrupt control = %04X\n", cpu_get_pc(space->cpu), data16);
1174         i186.intr.ext[1] = data16 & 0x007f;
1067         state->i186.intr.ext[1] = data16 & 0x007f;
11751068         break;
11761069
11771070      case 0x1e:
11781071         if (LOG_PORTS) logerror("%05X:80186 INT 2 interrupt control = %04X\n", cpu_get_pc(space->cpu), data16);
1179         i186.intr.ext[2] = data16 & 0x001f;
1072         state->i186.intr.ext[2] = data16 & 0x001f;
11801073         break;
11811074
11821075      case 0x1f:
11831076         if (LOG_PORTS) logerror("%05X:80186 INT 3 interrupt control = %04X\n", cpu_get_pc(space->cpu), data16);
1184         i186.intr.ext[3] = data16 & 0x001f;
1077         state->i186.intr.ext[3] = data16 & 0x001f;
11851078         break;
11861079
11871080      case 0x28:
r9685r9686
12171110
12181111      case 0x50:
12191112         if (LOG_PORTS) logerror("%05X:80186 upper chip select = %04X\n", cpu_get_pc(space->cpu), data16);
1220         i186.mem.upper = data16 | 0xc038;
1113         state->i186.mem.upper = data16 | 0xc038;
12211114         break;
12221115
12231116      case 0x51:
12241117         if (LOG_PORTS) logerror("%05X:80186 lower chip select = %04X\n", cpu_get_pc(space->cpu), data16);
1225         i186.mem.lower = (data16 & 0x3fff) | 0x0038; printf("%X",i186.mem.lower);
1118         state->i186.mem.lower = (data16 & 0x3fff) | 0x0038; printf("%X",state->i186.mem.lower);
12261119         break;
12271120
12281121      case 0x52:
12291122         if (LOG_PORTS) logerror("%05X:80186 peripheral chip select = %04X\n", cpu_get_pc(space->cpu), data16);
1230         i186.mem.peripheral = data16 | 0x0038;
1123         state->i186.mem.peripheral = data16 | 0x0038;
12311124         break;
12321125
12331126      case 0x53:
12341127         if (LOG_PORTS) logerror("%05X:80186 middle chip select = %04X\n", cpu_get_pc(space->cpu), data16);
1235         i186.mem.middle = data16 | 0x01f8;
1128         state->i186.mem.middle = data16 | 0x01f8;
12361129         break;
12371130
12381131      case 0x54:
12391132         if (LOG_PORTS) logerror("%05X:80186 middle P chip select = %04X\n", cpu_get_pc(space->cpu), data16);
1240         i186.mem.middle_size = data16 | 0x8038;
1133         state->i186.mem.middle_size = data16 | 0x8038;
12411134
12421135         /* we need to do this at a time when the I86 context is swapped in */
12431136         /* this register is generally set once at startup and never again, so it's a good */
r9685r9686
12491142      case 0x68:
12501143         if (LOG_PORTS) logerror("%05X:80186 DMA%d lower source address = %04X\n", cpu_get_pc(space->cpu), (offset - 0x60) / 8, data16);
12511144         which = (offset - 0x60) / 8;
1252         i186.dma[which].source = (i186.dma[which].source & ~0x0ffff) | (data16 & 0x0ffff);
1145         state->i186.dma[which].source = (state->i186.dma[which].source & ~0x0ffff) | (data16 & 0x0ffff);
12531146         break;
12541147
12551148      case 0x61:
12561149      case 0x69:
12571150         if (LOG_PORTS) logerror("%05X:80186 DMA%d upper source address = %04X\n", cpu_get_pc(space->cpu), (offset - 0x61) / 8, data16);
12581151         which = (offset - 0x61) / 8;
1259         i186.dma[which].source = (i186.dma[which].source & ~0xf0000) | ((data16 << 16) & 0xf0000);
1152         state->i186.dma[which].source = (state->i186.dma[which].source & ~0xf0000) | ((data16 << 16) & 0xf0000);
12601153         break;
12611154
12621155      case 0x62:
12631156      case 0x6a:
12641157         if (LOG_PORTS) logerror("%05X:80186 DMA%d lower dest address = %04X\n", cpu_get_pc(space->cpu), (offset - 0x62) / 8, data16);
12651158         which = (offset - 0x62) / 8;
1266         i186.dma[which].dest = (i186.dma[which].dest & ~0x0ffff) | (data16 & 0x0ffff);
1159         state->i186.dma[which].dest = (state->i186.dma[which].dest & ~0x0ffff) | (data16 & 0x0ffff);
12671160         break;
12681161
12691162      case 0x63:
12701163      case 0x6b:
12711164         if (LOG_PORTS) logerror("%05X:80186 DMA%d upper dest address = %04X\n", cpu_get_pc(space->cpu), (offset - 0x63) / 8, data16);
12721165         which = (offset - 0x63) / 8;
1273         i186.dma[which].dest = (i186.dma[which].dest & ~0xf0000) | ((data16 << 16) & 0xf0000);
1166         state->i186.dma[which].dest = (state->i186.dma[which].dest & ~0xf0000) | ((data16 << 16) & 0xf0000);
12741167         break;
12751168
12761169      case 0x64:
12771170      case 0x6c:
12781171         if (LOG_PORTS) logerror("%05X:80186 DMA%d transfer count = %04X\n", cpu_get_pc(space->cpu), (offset - 0x64) / 8, data16);
12791172         which = (offset - 0x64) / 8;
1280         i186.dma[which].count = data16;
1173         state->i186.dma[which].count = data16;
12811174         break;
12821175
12831176      case 0x65:
r9685r9686
13331226
13341227MACHINE_START( nimbus )
13351228{
1336    /* init cpu */
1337    nimbus_cpu_init(machine);
1229   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
1230   /* init cpu */
1231   nimbus_cpu_init(machine);
13381232
1339    keyboard.keyscan_timer=timer_alloc(machine, keyscan_callback, NULL);
1340    nimbus_mouse.mouse_timer=timer_alloc(machine, mouse_callback, NULL);
1233   state->keyboard.keyscan_timer=timer_alloc(machine, keyscan_callback, NULL);
1234   state->nimbus_mouse.mouse_timer=timer_alloc(machine, mouse_callback, NULL);
13411235
13421236   /* setup debug commands */
13431237   if (machine->debug_flags & DEBUG_FLAG_ENABLED)
13441238   {
13451239      debug_console_register_command(machine, "nimbus_irq", CMDFLAG_NONE, 0, 0, 2, execute_debug_irq);
1346        debug_console_register_command(machine, "nimbus_intmasks", CMDFLAG_NONE, 0, 0, 0, execute_debug_intmasks);
1347        debug_console_register_command(machine, "nimbus_debug", CMDFLAG_NONE, 0, 0, 1, nimbus_debug);
1240      debug_console_register_command(machine, "nimbus_intmasks", CMDFLAG_NONE, 0, 0, 0, execute_debug_intmasks);
1241      debug_console_register_command(machine, "nimbus_debug", CMDFLAG_NONE, 0, 0, 1, nimbus_debug);
13481242
1349        /* set up the instruction hook */
1243      /* set up the instruction hook */
13501244      machine->device(MAINCPU_TAG)->debug()->set_instruction_hook(instruction_hook);
1351    }
1245   }
13521246
1353    debug_machine=DECODE_BIOS;
1247   state->debug_machine=DECODE_BIOS;
13541248}
13551249
13561250static void execute_debug_irq(running_machine *machine, int ref, int params, const char *param[])
r9685r9686
13751269
13761270static void execute_debug_intmasks(running_machine *machine, int ref, int params, const char *param[])
13771271{
1272   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
13781273    int IntNo;
13791274
1380    debug_console_printf(machine,"i186.intr.priority_mask=%4X\n",i186.intr.priority_mask);
1275    debug_console_printf(machine,"i186.intr.priority_mask=%4X\n",state->i186.intr.priority_mask);
13811276    for(IntNo=0; IntNo<4; IntNo++)
13821277    {
1383        debug_console_printf(machine,"extInt%d mask=%4X\n",IntNo,i186.intr.ext[IntNo]);
1278        debug_console_printf(machine,"extInt%d mask=%4X\n",IntNo,state->i186.intr.ext[IntNo]);
13841279    }
13851280
1386    debug_console_printf(machine,"i186.intr.request   = %04X\n",i186.intr.request);
1387    debug_console_printf(machine,"i186.intr.ack_mask  = %04X\n",i186.intr.ack_mask);
1388    debug_console_printf(machine,"i186.intr.in_service= %04X\n",i186.intr.in_service);
1281    debug_console_printf(machine,"i186.intr.request   = %04X\n",state->i186.intr.request);
1282    debug_console_printf(machine,"i186.intr.ack_mask  = %04X\n",state->i186.intr.ack_mask);
1283    debug_console_printf(machine,"i186.intr.in_service= %04X\n",state->i186.intr.in_service);
13891284}
13901285
13911286static void nimbus_debug(running_machine *machine, int ref, int params, const char *param[])
13921287{
1288   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
13931289    if(params>0)
13941290    {
1395        sscanf(param[0],"%d",&debug_machine);
1291        sscanf(param[0],"%d",&state->debug_machine);
13961292    }
13971293    else
13981294    {
13991295        debug_console_printf(machine,"Error usage : nimbus_debug <debuglevel>\n");
1400        debug_console_printf(machine,"Current debuglevel=%02X\n",debug_machine);
1296        debug_console_printf(machine,"Current debuglevel=%02X\n",state->debug_machine);
14011297    }
14021298}
14031299
r9685r9686
14071303
14081304static int instruction_hook(device_t &device, offs_t curpc)
14091305{
1306   rmnimbus_state *state = device.machine->driver_data<rmnimbus_state>();
14101307    address_space *space = cpu_get_address_space(&device, ADDRESS_SPACE_PROGRAM);
14111308    UINT8               *addr_ptr;
14121309
r9685r9686
19441841
19451842static void nimbus_bank_memory(running_machine *machine)
19461843{
1844   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
19471845    address_space *space = cputag_get_address_space( machine, MAINCPU_TAG, ADDRESS_SPACE_PROGRAM );
1948   int     ramsize = messram_get_size(machine->device("messram"));
1846    int     ramsize = messram_get_size(machine->device("messram"));
19491847    int     ramblock = 0;
19501848    int     blockno;
19511849    char   bank[10];
r9685r9686
19551853    int     map_blockno;
19561854    int     block_ofs;
19571855
1958    UINT8   ramsel = (mcu_reg080 & 0x1F);
1856    UINT8   ramsel = (state->mcu_reg080 & 0x1F);
19591857
19601858    // Invalid ramsel, return.
19611859    if((ramsel & 0x07)!=0x07)
r9685r9686
19761874    map_blocks[1]  = (ramblocks[ramblock][1].blocksize==0) ? NULL : &ram[ramblocks[ramblock][1].blockbase*1024];
19771875    map_blocks[2]  = (ramblocks[ramblock][2].blocksize==0) ? NULL : &ram[ramblocks[ramblock][2].blockbase*1024];
19781876
1979    //if(LOG_RAM) logerror("\n\nmcu_reg080=%02X, ramblock=%d, map_blocks[0]=%X, map_blocks[1]=%X, map_blocks[2]=%X\n",mcu_reg080,ramblock,(int)map_blocks[0],(int)map_blocks[1],(int)map_blocks[2]);
1877    //if(LOG_RAM) logerror("\n\nmcu_reg080=%02X, ramblock=%d, map_blocks[0]=%X, map_blocks[1]=%X, map_blocks[2]=%X\n",state->mcu_reg080,ramblock,(int)map_blocks[0],(int)map_blocks[1],(int)map_blocks[2]);
19801878
19811879    for(blockno=0;blockno<8;blockno++)
19821880    {
r9685r9686
20141912
20151913READ8_HANDLER( nimbus_mcu_r )
20161914{
2017    return mcu_reg080;
1915   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
1916    return state->mcu_reg080;
20181917}
20191918
20201919WRITE8_HANDLER( nimbus_mcu_w )
20211920{
2022    mcu_reg080=data;
1921   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
1922    state->mcu_reg080=data;
20231923
20241924    nimbus_bank_memory(space->machine);
20251925}
20261926
20271927static void memory_reset(running_machine *machine)
20281928{
2029    mcu_reg080=0x07;
1929   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
1930    state->mcu_reg080=0x07;
20301931    nimbus_bank_memory(machine);
20311932}
20321933
20331934READ16_HANDLER( nimbus_io_r )
20341935{
1936   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
20351937    int pc=cpu_get_pc(space->cpu);
20361938
2037    logerror("Nimbus IOR at pc=%08X from %04X mask=%04X, data=%04X\n",pc,(offset*2)+0x30,mem_mask,IOPorts[offset]);
1939    logerror("Nimbus IOR at pc=%08X from %04X mask=%04X, data=%04X\n",pc,(offset*2)+0x30,mem_mask,state->IOPorts[offset]);
20381940
20391941    switch (offset*2)
20401942    {
2041        default         : return IOPorts[offset];
1943        default         : return state->IOPorts[offset];
20421944    }
20431945    return 0;
20441946}
20451947
20461948WRITE16_HANDLER( nimbus_io_w )
20471949{
1950   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
20481951    int pc=cpu_get_pc(space->cpu);
20491952
20501953    logerror("Nimbus IOW at %08X write of %04X to %04X mask=%04X\n",pc,data,(offset*2)+0x30,mem_mask);
20511954
20521955    switch (offset*2)
20531956    {
2054        default         : COMBINE_DATA(&IOPorts[offset]); break;
1957        default         : COMBINE_DATA(&state->IOPorts[offset]); break;
20551958    }
20561959}
20571960
r9685r9686
20631966
20641967static void keyboard_reset(running_machine *machine)
20651968{
2066    memset(keyboard.keyrows,0xFF,NIMBUS_KEYROWS);
1969   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
1970    memset(state->keyboard.keyrows,0xFF,NIMBUS_KEYROWS);
20671971
2068    // Setup timer to scan keyboard.
2069    timer_adjust_periodic(keyboard.keyscan_timer, attotime_zero, 0, ATTOTIME_IN_HZ(50));
1972    // Setup timer to scan state->keyboard.
1973    timer_adjust_periodic(state->keyboard.keyscan_timer, attotime_zero, 0, ATTOTIME_IN_HZ(50));
20701974}
20711975
2072static void queue_scancode(UINT8 scancode)
1976static void queue_scancode(running_machine *machine, UINT8 scancode)
20731977{
2074   keyboard.queue[keyboard.head] = scancode;
2075   keyboard.head++;
2076   keyboard.head %= ARRAY_LENGTH(keyboard.queue);
1978   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
1979   state->keyboard.queue[state->keyboard.head] = scancode;
1980   state->keyboard.head++;
1981   state->keyboard.head %= ARRAY_LENGTH(state->keyboard.queue);
20771982}
20781983
2079static int keyboard_queue_read(void)
1984static int keyboard_queue_read(running_machine *machine)
20801985{
1986   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
20811987   int data;
2082   if (keyboard.tail == keyboard.head)
1988   if (state->keyboard.tail == state->keyboard.head)
20831989      return -1;
20841990
2085   data = keyboard.queue[keyboard.tail];
1991   data = state->keyboard.queue[state->keyboard.tail];
20861992
20871993   if (LOG_KEYBOARD)
20881994      logerror("keyboard_queue_read(): Keyboard Read 0x%02x\n",data);
20891995
2090   keyboard.tail++;
2091   keyboard.tail %= ARRAY_LENGTH(keyboard.queue);
1996   state->keyboard.tail++;
1997   state->keyboard.tail %= ARRAY_LENGTH(state->keyboard.queue);
20921998   return data;
20931999}
20942000
20952001static void scan_keyboard(running_machine *machine)
20962002
20972003{
2004   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
20982005    UINT8   keyrow;
20992006    UINT8   row;
21002007    UINT8   bitno;
r9685r9686
21112018
21122019        for(mask=0x80, bitno=7;mask>0;mask=mask>>1, bitno-=1)
21132020        {
2114            if(!(keyrow & mask) && (keyboard.keyrows[row] & mask))
2021            if(!(keyrow & mask) && (state->keyboard.keyrows[row] & mask))
21152022            {
21162023                if (LOG_KEYBOARD) logerror("keypress %02X\n",(row<<3)+bitno);
2117                queue_scancode((row<<3)+bitno);
2024                queue_scancode(machine, (row<<3)+bitno);
21182025            }
21192026
2120            if((keyrow & mask) && !(keyboard.keyrows[row] & mask))
2027            if((keyrow & mask) && !(state->keyboard.keyrows[row] & mask))
21212028            {
21222029                if (LOG_KEYBOARD) logerror("keyrelease %02X\n",0x80+(row<<3)+bitno);
2123                queue_scancode(0x80+(row<<3)+bitno);
2030                queue_scancode(machine, 0x80+(row<<3)+bitno);
21242031            }
21252032        }
21262033
2127        keyboard.keyrows[row]=keyrow;
2034        state->keyboard.keyrows[row]=keyrow;
21282035    }
21292036}
21302037
r9685r9686
21432050
21442051static void sio_interrupt(running_device *device, int state)
21452052{
2053   rmnimbus_state *drvstate = device->machine->driver_data<rmnimbus_state>();
21462054    if(LOG_SIO)
21472055        logerror("SIO Interrupt state=%02X\n",state);
21482056
21492057    // Don't re-trigger if already active !
2150    if(state!=sio_int_state)
2058    if(state!=drvstate->sio_int_state)
21512059    {
2152        sio_int_state=state;
2060        drvstate->sio_int_state=state;
21532061
21542062        if(state)
21552063            external_int(device->machine,0,EXTERNAL_INT_Z80SIO);
r9685r9686
21712079
21722080static int sio_serial_receive( running_device *device, int channel )
21732081{
2174   if(channel==0)
2082    if(channel==0)
21752083    {
2176        return keyboard_queue_read();
2084        return keyboard_queue_read(device->machine);
21772085    }
21782086    else
21792087        return -1;
r9685r9686
21832091
21842092static void fdc_reset(running_machine *machine)
21852093{
2186    nimbus_drives.reg400=0;
2187    nimbus_drives.reg410_in=0;
2188    nimbus_drives.reg410_out=0;
2189    nimbus_drives.int_ff=0;
2094   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
2095    state->nimbus_drives.reg400=0;
2096    state->nimbus_drives.reg410_in=0;
2097    state->nimbus_drives.reg410_out=0;
2098    state->nimbus_drives.int_ff=0;
21902099}
21912100
21922101static void set_disk_int(running_machine *machine, int state)
21932102{
2103   rmnimbus_state *drvstate = machine->driver_data<rmnimbus_state>();
21942104    if(LOG_DISK)
21952105        logerror("nimbus_drives_intrq = %d\n",state);
21962106
2197    if(iou_reg092 & DISK_INT_ENABLE)
2107    if(drvstate->iou_reg092 & DISK_INT_ENABLE)
21982108    {
2199        nimbus_drives.int_ff=state;
2109        drvstate->nimbus_drives.int_ff=state;
22002110
22012111        if(state)
22022112            external_int(machine,0,EXTERNAL_INT_DISK);
r9685r9686
22102120
22112121static WRITE_LINE_DEVICE_HANDLER( nimbus_fdc_drq_w )
22122122{
2123   rmnimbus_state *drvstate = device->machine->driver_data<rmnimbus_state>();
22132124
22142125    if(LOG_DISK)
22152126        logerror("nimbus_drives_drq_w(%d)\n", state);
22162127
2217    if(state && FDC_DRQ_ENABLED())
2128    if(state && FDC_DRQ_ENABLED(drvstate))
22182129        drq_callback(device->machine,1);
22192130}
22202131
r9685r9686
22332144
22342145READ8_HANDLER( nimbus_disk_r )
22352146{
2147   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
22362148   int result = 0;
22372149   running_device *fdc = space->machine->device(FDC_TAG);
2238    running_device *hdc = space->machine->device(SCSIBUS_TAG);
2150   running_device *hdc = space->machine->device(SCSIBUS_TAG);
22392151
2240    int pc=cpu_get_pc(space->cpu);
2241    running_device *drive = space->machine->device(nimbus_wd17xx_interface.floppy_drive_tags[FDC_DRIVE()]);
2152   int pc=cpu_get_pc(space->cpu);
2153   running_device *drive = space->machine->device(nimbus_wd17xx_interface.floppy_drive_tags[FDC_DRIVE()]);
22422154
2243    switch(offset*2)
2155   switch(offset*2)
22442156   {
22452157      case 0x08 :
22462158         result = wd17xx_status_r(fdc, 0);
r9685r9686
22552167      case 0x0E :
22562168         result = wd17xx_data_r(fdc, 0);
22572169         break;
2258        case 0x10 :
2259            nimbus_drives.reg410_in &= ~FDC_BITS_410;
2260            nimbus_drives.reg410_in |= (FDC_MOTOR() ? FDC_MOTOR_MASKI : 0x00);
2261            nimbus_drives.reg410_in |= (floppy_drive_get_flag_state(drive, FLOPPY_DRIVE_INDEX) ? 0x00 : FDC_INDEX_MASK);
2262            nimbus_drives.reg410_in |= (floppy_drive_get_flag_state(drive, FLOPPY_DRIVE_READY) ? FDC_READY_MASK : 0x00);
2170      case 0x10 :
2171         state->nimbus_drives.reg410_in &= ~FDC_BITS_410;
2172         state->nimbus_drives.reg410_in |= (FDC_MOTOR() ? FDC_MOTOR_MASKI : 0x00);
2173         state->nimbus_drives.reg410_in |= (floppy_drive_get_flag_state(drive, FLOPPY_DRIVE_INDEX) ? 0x00 : FDC_INDEX_MASK);
2174         state->nimbus_drives.reg410_in |= (floppy_drive_get_flag_state(drive, FLOPPY_DRIVE_READY) ? FDC_READY_MASK : 0x00);
22632175
2264            // Flip inverted bits
2265            result=nimbus_drives.reg410_in ^ INV_BITS_410;
2266            break;
2267        case 0x18 :
2268            result = scsi_data_r(hdc);
2269            hdc_post_rw(space->machine);
2176         // Flip inverted bits
2177         result=state->nimbus_drives.reg410_in ^ INV_BITS_410;
2178         break;
2179      case 0x18 :
2180         result = scsi_data_r(hdc);
2181         hdc_post_rw(space->machine);
22702182      default:
22712183         break;
22722184   }
22732185
2274    if(LOG_DISK_FDD && ((offset*2)<=0x10))
2275        logerror("Nimbus FDCR at pc=%08X from %04X data=%02X\n",pc,(offset*2)+0x400,result);
2186   if(LOG_DISK_FDD && ((offset*2)<=0x10))
2187      logerror("Nimbus FDCR at pc=%08X from %04X data=%02X\n",pc,(offset*2)+0x400,result);
22762188
2277    if((LOG_DISK_HDD) && ((offset*2)>=0x10))
2278        logerror("Nimbus HDCR at pc=%08X from %04X data=%02X\n",pc,(offset*2)+0x400,result);
2189   if((LOG_DISK_HDD) && ((offset*2)>=0x10))
2190      logerror("Nimbus HDCR at pc=%08X from %04X data=%02X\n",pc,(offset*2)+0x400,result);
22792191
2280
22812192   return result;
22822193}
22832194
r9685r9686
23022213
23032214WRITE8_HANDLER( nimbus_disk_w )
23042215{
2216   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
23052217   running_device *fdc = space->machine->device(FDC_TAG);
23062218    running_device *hdc = space->machine->device(SCSIBUS_TAG);
23072219    int                 pc=cpu_get_pc(space->cpu);
2308    UINT8               reg400_old = nimbus_drives.reg400;
2220    UINT8               reg400_old = state->nimbus_drives.reg400;
23092221
23102222    if(LOG_DISK_FDD && ((offset*2)<=0x10))
23112223        logerror("Nimbus FDCW at %05X write of %02X to %04X\n",pc,data,(offset*2)+0x400);
r9685r9686
23162228    switch(offset*2)
23172229   {
23182230        case 0x00 :
2319            nimbus_drives.reg400=data;
2231            state->nimbus_drives.reg400=data;
23202232
23212233            wd17xx_set_drive(fdc,FDC_DRIVE());
23222234            wd17xx_set_side(fdc, FDC_SIDE());
r9685r9686
23542266
23552267static void hdc_reset(running_machine *machine)
23562268{
2269   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
23572270    running_device *hdc = machine->device(SCSIBUS_TAG);
23582271
23592272    init_scsibus(hdc);
23602273
2361    nimbus_drives.reg410_in=0;
2362    nimbus_drives.reg410_in |= (get_scsi_line(hdc,SCSI_LINE_REQ) ? HDC_REQ_MASK : 0);
2363    nimbus_drives.reg410_in |= (get_scsi_line(hdc,SCSI_LINE_CD)  ? HDC_CD_MASK  : 0);
2364    nimbus_drives.reg410_in |= (get_scsi_line(hdc,SCSI_LINE_IO)  ? HDC_IO_MASK  : 0);
2365    nimbus_drives.reg410_in |= (get_scsi_line(hdc,SCSI_LINE_BSY) ? HDC_BSY_MASK : 0);
2366    nimbus_drives.reg410_in |= (get_scsi_line(hdc,SCSI_LINE_MSG) ? HDC_MSG_MASK : 0);
2274    state->nimbus_drives.reg410_in=0;
2275    state->nimbus_drives.reg410_in |= (get_scsi_line(hdc,SCSI_LINE_REQ) ? HDC_REQ_MASK : 0);
2276    state->nimbus_drives.reg410_in |= (get_scsi_line(hdc,SCSI_LINE_CD)  ? HDC_CD_MASK  : 0);
2277    state->nimbus_drives.reg410_in |= (get_scsi_line(hdc,SCSI_LINE_IO)  ? HDC_IO_MASK  : 0);
2278    state->nimbus_drives.reg410_in |= (get_scsi_line(hdc,SCSI_LINE_BSY) ? HDC_BSY_MASK : 0);
2279    state->nimbus_drives.reg410_in |= (get_scsi_line(hdc,SCSI_LINE_MSG) ? HDC_MSG_MASK : 0);
23672280
2368    nimbus_drives.drq_ff=0;
2281    state->nimbus_drives.drq_ff=0;
23692282}
23702283
23712284static void hdc_ctrl_write(running_machine *machine, UINT8 data)
23722285{
2286   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
23732287   running_device *hdc = machine->device(SCSIBUS_TAG);
23742288
23752289    // If we enable the HDC interupt, and an interrupt is pending, go deal with it.
2376    if(((data & HDC_IRQ_MASK) && (~nimbus_drives.reg410_out & HDC_IRQ_MASK)) &&
2377       ((~nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
2290    if(((data & HDC_IRQ_MASK) && (~state->nimbus_drives.reg410_out & HDC_IRQ_MASK)) &&
2291       ((~state->nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
23782292        set_disk_int(machine,1);
23792293
2380    nimbus_drives.reg410_out=data;
2294    state->nimbus_drives.reg410_out=data;
23812295
23822296    set_scsi_line(hdc, SCSI_LINE_RESET, (data & HDC_RESET_MASK) ? 0 : 1);
23832297    set_scsi_line(hdc, SCSI_LINE_SEL, (data & HDC_SEL_MASK) ? 0 : 1);
r9685r9686
23852299
23862300static void hdc_post_rw(running_machine *machine)
23872301{
2302   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
23882303    running_device *hdc = machine->device(SCSIBUS_TAG);
23892304
2390    if((nimbus_drives.reg410_in & HDC_REQ_MASK)==0)
2305    if((state->nimbus_drives.reg410_in & HDC_REQ_MASK)==0)
23912306        set_scsi_line(hdc,SCSI_LINE_ACK,0);
23922307
2393    nimbus_drives.drq_ff=0;
2308    state->nimbus_drives.drq_ff=0;
23942309}
23952310
23962311static void hdc_drq(running_machine *machine)
23972312{
2398    if(HDC_DRQ_ENABLED() && nimbus_drives.drq_ff)
2313   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
2314    if(HDC_DRQ_ENABLED() && state->nimbus_drives.drq_ff)
23992315    {
24002316        drq_callback(machine,1);
24012317    }
r9685r9686
24032319
24042320void nimbus_scsi_linechange(running_device *device, UINT8 line, UINT8 state)
24052321{
2322   rmnimbus_state *drvstate = device->machine->driver_data<rmnimbus_state>();
24062323    UINT8   mask = 0;
24072324    UINT8   last = 0;
24082325
r9685r9686
24152332        case SCSI_LINE_MSG   : mask=HDC_MSG_MASK; break;
24162333    }
24172334
2418    last=nimbus_drives.reg410_in & mask;
2335    last=drvstate->nimbus_drives.reg410_in & mask;
24192336
24202337    if(state)
2421        nimbus_drives.reg410_in|=mask;
2338        drvstate->nimbus_drives.reg410_in|=mask;
24222339    else
2423        nimbus_drives.reg410_in&=~mask;
2340        drvstate->nimbus_drives.reg410_in&=~mask;
24242341
24252342
2426    if(HDC_IRQ_ENABLED() && ((~nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
2343    if(HDC_IRQ_ENABLED(drvstate) && ((~drvstate->nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
24272344        set_disk_int(device->machine,1);
24282345    else
24292346        set_disk_int(device->machine,0);
r9685r9686
24322349    {
24332350        if (state==0)
24342351        {
2435            if(((nimbus_drives.reg410_in & HDC_CD_MASK)==HDC_CD_MASK) && (last!=0))
2352            if(((drvstate->nimbus_drives.reg410_in & HDC_CD_MASK)==HDC_CD_MASK) && (last!=0))
24362353            {
2437                nimbus_drives.drq_ff=1;
2354                drvstate->nimbus_drives.drq_ff=1;
24382355                hdc_drq(device->machine);
24392356            }
24402357        }
r9685r9686
24472364
24482365static void pc8031_reset(running_machine *machine)
24492366{
2367   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
24502368    running_device *er59256 = machine->device(ER59256_TAG);
24512369
24522370    logerror("peripheral controler reset\n");
24532371
2454    memset(&ipc_interface,0,sizeof(ipc_interface));
2372    memset(&state->ipc_interface,0,sizeof(state->ipc_interface));
24552373
24562374    if(!er59256_data_loaded(er59256))
24572375        er59256_preload_rom(er59256,def_config,ARRAY_LENGTH(def_config));
r9685r9686
24612379#if 0
24622380static void ipc_dumpregs()
24632381{
2382   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
24642383    logerror("in_data=%02X, in_status=%02X, out_data=%02X, out_status=%02X\n",
2465              ipc_interface.ipc_in, ipc_interface.status_in,
2466              ipc_interface.ipc_out, ipc_interface.status_out);
2384              state->ipc_interface.ipc_in, state->ipc_interface.status_in,
2385              state->ipc_interface.ipc_out, state->ipc_interface.status_out);
24672386
24682387}
24692388#endif
24702389
24712390READ8_HANDLER( nimbus_pc8031_r )
24722391{
2392   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
24732393   int pc=cpu_get_pc(space->cpu);
24742394    UINT8   result;
24752395
24762396    switch(offset*2)
24772397    {
2478        case 0x00   : result=ipc_interface.ipc_out;
2479                      ipc_interface.status_in   &= ~IPC_IN_READ_PEND;
2480                      ipc_interface.status_out  &= ~IPC_OUT_BYTE_AVAIL;
2398        case 0x00   : result=state->ipc_interface.ipc_out;
2399                      state->ipc_interface.status_in   &= ~IPC_IN_READ_PEND;
2400                      state->ipc_interface.status_out  &= ~IPC_OUT_BYTE_AVAIL;
24812401                      break;
24822402
2483        case 0x02   : result=ipc_interface.status_out;
2403        case 0x02   : result=state->ipc_interface.status_out;
24842404                      break;
24852405
24862406        default : result=0; break;
r9685r9686
24942414
24952415WRITE8_HANDLER( nimbus_pc8031_w )
24962416{
2417   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
24972418   int pc=cpu_get_pc(space->cpu);
24982419
24992420    switch(offset*2)
25002421    {
2501        case 0x00   : ipc_interface.ipc_in=data;
2502                      ipc_interface.status_in   |= IPC_IN_BYTE_AVAIL;
2503                      ipc_interface.status_in   &= ~IPC_IN_ADDR;
2504                      ipc_interface.status_out  |= IPC_OUT_READ_PEND;
2422        case 0x00   : state->ipc_interface.ipc_in=data;
2423                      state->ipc_interface.status_in   |= IPC_IN_BYTE_AVAIL;
2424                      state->ipc_interface.status_in   &= ~IPC_IN_ADDR;
2425                      state->ipc_interface.status_out  |= IPC_OUT_READ_PEND;
25052426                      break;
25062427
2507        case 0x02   : ipc_interface.ipc_in=data;
2508                      ipc_interface.status_in   |= IPC_IN_BYTE_AVAIL;
2509                      ipc_interface.status_in   |= IPC_IN_ADDR;
2510                      ipc_interface.status_out  |= IPC_OUT_READ_PEND;
2428        case 0x02   : state->ipc_interface.ipc_in=data;
2429                      state->ipc_interface.status_in   |= IPC_IN_BYTE_AVAIL;
2430                      state->ipc_interface.status_in   |= IPC_IN_ADDR;
2431                      state->ipc_interface.status_out  |= IPC_OUT_READ_PEND;
25112432                      break;
25122433    }
25132434
r9685r9686
25202441
25212442READ8_HANDLER( nimbus_pc8031_iou_r )
25222443{
2444   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
25232445   int pc=cpu_get_pc(space->cpu);
25242446    UINT8   result = 0;
25252447
25262448    switch (offset & 0x01)
25272449    {
2528        case 0x00   : result=ipc_interface.ipc_in;
2529                      ipc_interface.status_out  &= ~IPC_OUT_READ_PEND;
2530                      ipc_interface.status_in   &= ~IPC_IN_BYTE_AVAIL;
2450        case 0x00   : result=state->ipc_interface.ipc_in;
2451                      state->ipc_interface.status_out  &= ~IPC_OUT_READ_PEND;
2452                      state->ipc_interface.status_in   &= ~IPC_IN_BYTE_AVAIL;
25312453                      break;
25322454
2533        case 0x01   : result=ipc_interface.status_in;
2455        case 0x01   : result=state->ipc_interface.status_in;
25342456                      break;
25352457    }
25362458
2537    if(((offset==2) || (offset==3)) && (iou_reg092 & PC8031_INT_ENABLE))
2459    if(((offset==2) || (offset==3)) && (state->iou_reg092 & PC8031_INT_ENABLE))
25382460        external_int(space->machine,0,EXTERNAL_INT_PC8031_8C);
25392461
25402462    if(LOG_PC8031)
r9685r9686
25452467
25462468WRITE8_HANDLER( nimbus_pc8031_iou_w )
25472469{
2470   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
25482471   int pc=cpu_get_pc(space->cpu);
25492472
25502473    if(LOG_PC8031)
r9685r9686
25522475
25532476    switch(offset & 0x03)
25542477    {
2555        case 0x00   : ipc_interface.ipc_out=data;
2556                      ipc_interface.status_out  |= IPC_OUT_BYTE_AVAIL;
2557                      ipc_interface.status_out  &= ~IPC_OUT_ADDR;
2558                      ipc_interface.status_in   |= IPC_IN_READ_PEND;
2478        case 0x00   : state->ipc_interface.ipc_out=data;
2479                      state->ipc_interface.status_out  |= IPC_OUT_BYTE_AVAIL;
2480                      state->ipc_interface.status_out  &= ~IPC_OUT_ADDR;
2481                      state->ipc_interface.status_in   |= IPC_IN_READ_PEND;
25592482                      break;
25602483
2561        case 0x01   : ipc_interface.ipc_out=data;
2562                      ipc_interface.status_out   |= IPC_OUT_BYTE_AVAIL;
2563                      ipc_interface.status_out   |= IPC_OUT_ADDR;
2564                      ipc_interface.status_in    |= IPC_IN_READ_PEND;
2484        case 0x01   : state->ipc_interface.ipc_out=data;
2485                      state->ipc_interface.status_out   |= IPC_OUT_BYTE_AVAIL;
2486                      state->ipc_interface.status_out   |= IPC_OUT_ADDR;
2487                      state->ipc_interface.status_in    |= IPC_IN_READ_PEND;
25652488                      break;
25662489
2567        case 0x02   : ipc_interface.ipc_out=data;
2568                      ipc_interface.status_out  |= IPC_OUT_BYTE_AVAIL;
2569                      ipc_interface.status_out  &= ~IPC_OUT_ADDR;
2570                      ipc_interface.status_in   |= IPC_IN_READ_PEND;
2571                      if(iou_reg092 & PC8031_INT_ENABLE)
2490        case 0x02   : state->ipc_interface.ipc_out=data;
2491                      state->ipc_interface.status_out  |= IPC_OUT_BYTE_AVAIL;
2492                      state->ipc_interface.status_out  &= ~IPC_OUT_ADDR;
2493                      state->ipc_interface.status_in   |= IPC_IN_READ_PEND;
2494                      if(state->iou_reg092 & PC8031_INT_ENABLE)
25722495                        external_int(space->machine,0,EXTERNAL_INT_PC8031_8F);
25732496                      break;
25742497
2575        case 0x03   : ipc_interface.ipc_out=data;
2576                      //ipc_interface.status_out   |= IPC_OUT_BYTE_AVAIL;
2577                      ipc_interface.status_out   |= IPC_OUT_ADDR;
2578                      ipc_interface.status_in    |= IPC_IN_READ_PEND;
2579                      if(iou_reg092 & PC8031_INT_ENABLE)
2498        case 0x03   : state->ipc_interface.ipc_out=data;
2499                      //state->ipc_interface.status_out   |= IPC_OUT_BYTE_AVAIL;
2500                      state->ipc_interface.status_out   |= IPC_OUT_ADDR;
2501                      state->ipc_interface.status_in    |= IPC_IN_READ_PEND;
2502                      if(state->iou_reg092 & PC8031_INT_ENABLE)
25802503                        external_int(space->machine,0,EXTERNAL_INT_PC8031_8E);
25812504                      break;
25822505    }
r9685r9686
26182541/* IO Unit */
26192542READ8_HANDLER( nimbus_iou_r )
26202543{
2544   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
26212545   int pc=cpu_get_pc(space->cpu);
26222546    UINT8   result=0;
26232547
26242548    if(offset==0)
26252549    {
2626        result=iou_reg092;
2550        result=state->iou_reg092;
26272551    }
26282552
26292553    if(LOG_IOU)
r9685r9686
26342558
26352559WRITE8_HANDLER( nimbus_iou_w )
26362560{
2561   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
26372562   int pc=cpu_get_pc(space->cpu);
26382563    running_device *msm5205 = space->machine->device(MSM5205_TAG);
26392564
r9685r9686
26422567
26432568    if(offset==0)
26442569    {
2645        iou_reg092=data;
2570        state->iou_reg092=data;
26462571        msm5205_reset_w(msm5205, (data & MSM5205_INT_ENABLE) ? 0 : 1);
26472572    }
26482573}
26492574
26502575static void iou_reset(running_machine *machine)
26512576{
2652    iou_reg092=0x00;
2577   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
2578    state->iou_reg092=0x00;
26532579}
26542580
26552581/*
r9685r9686
26682594
26692595static void sound_reset(running_machine *machine)
26702596{
2597   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
26712598    //running_device *ay8910 = machine->device(AY8910_TAG);
26722599    running_device *msm5205 = machine->device(MSM5205_TAG);
26732600
26742601    //ay8910_reset_ym(ay8910);
26752602    msm5205_reset_w(msm5205, 1);
26762603
2677    last_playmode=MSM5205_S48_4B;
2678    msm5205_playmode_w(msm5205,last_playmode);
2604    state->last_playmode=MSM5205_S48_4B;
2605    msm5205_playmode_w(msm5205,state->last_playmode);
26792606
2680    ay8910_a=0;
2607    state->ay8910_a=0;
26812608}
26822609
26832610READ8_HANDLER( nimbus_sound_ay8910_r )
r9685r9686
27092636
27102637WRITE8_HANDLER( nimbus_sound_ay8910_porta_w )
27112638{
2639   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
27122640    running_device *msm5205 = space->machine->device(MSM5205_TAG);
27132641
27142642    msm5205_data_w(msm5205, data);
27152643
27162644    // Mouse code needs a copy of this.
2717    ay8910_a=data;
2645    state->ay8910_a=data;
27182646}
27192647
27202648WRITE8_HANDLER( nimbus_sound_ay8910_portb_w )
27212649{
2650   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
27222651    running_device *msm5205 = space->machine->device(MSM5205_TAG);
27232652
2724    if((data & 0x07)!=last_playmode)
2653    if((data & 0x07)!=state->last_playmode)
27252654    {
2726        last_playmode=(data & 0x07);
2727        msm5205_playmode_w(msm5205, last_playmode);
2655        state->last_playmode=(data & 0x07);
2656        msm5205_playmode_w(msm5205, state->last_playmode);
27282657    }
27292658}
27302659
27312660void nimbus_msm5205_vck(running_device *device)
27322661{
2733    if(iou_reg092 & MSM5205_INT_ENABLE)
2662   rmnimbus_state *state = device->machine->driver_data<rmnimbus_state>();
2663    if(state->iou_reg092 & MSM5205_INT_ENABLE)
27342664        external_int(device->machine,0,EXTERNAL_INT_MSM5205);
27352665}
27362666
r9685r9686
27412671
27422672static void mouse_js_reset(running_machine *machine)
27432673{
2744    _mouse_joy_state *state = &nimbus_mouse;
2674   rmnimbus_state *drvstate = machine->driver_data<rmnimbus_state>();
2675    _mouse_joy_state *state = &drvstate->nimbus_mouse;
27452676
27462677    state->mouse_px=0;
27472678    state->mouse_py=0;
r9685r9686
27552686    state->reg0a4=0xC0;
27562687
27572688    // Setup timer to poll the mouse
2758    timer_adjust_periodic(nimbus_mouse.mouse_timer, attotime_zero, 0, ATTOTIME_IN_HZ(1000));
2689    timer_adjust_periodic(state->mouse_timer, attotime_zero, 0, ATTOTIME_IN_HZ(1000));
27592690}
27602691
27612692static TIMER_CALLBACK(mouse_callback)
27622693{
2694   rmnimbus_state *drvstate = machine->driver_data<rmnimbus_state>();
27632695    UINT8   x = 0;
27642696    UINT8   y = 0;
27652697//  int     pc=cpu_get_pc(machine->device(MAINCPU_TAG));
r9685r9686
27692701    int     xint;
27702702    int     yint;
27712703
2772    _mouse_joy_state *state = &nimbus_mouse;
2704    _mouse_joy_state *state = &drvstate->nimbus_mouse;
27732705
27742706
27752707   state->reg0a4 = input_port_read(machine, MOUSE_BUTTON_TAG) | 0xC0;
r9685r9686
27972729   }
27982730
27992731   if (y == state->mouse_y)
2800    {
2732   {
28012733      state->mouse_py = MOUSE_PHASE_STATIC;
28022734   }
28032735   else if (y > state->mouse_y)
r9685r9686
28262758    state->mouse_pcy &= 0x03;
28272759
28282760//  mxb = MOUSE_XYB[state->mouse_px][state->mouse_pcx]; // XB
2829//    mxa = MOUSE_XYA[state->mouse_px][state->mouse_pcx]; // XA
2761//  mxa = MOUSE_XYA[state->mouse_px][state->mouse_pcx]; // XA
28302762//  mya = MOUSE_XYA[state->mouse_py][state->mouse_pcy]; // YA
28312763//  myb = MOUSE_XYB[state->mouse_py][state->mouse_pcy]; // YB
28322764
r9685r9686
28372769
28382770    if ((state->mouse_py!=MOUSE_PHASE_STATIC) || (state->mouse_px!=MOUSE_PHASE_STATIC))
28392771    {
2840//        logerror("state->mouse_px=%02X, state->mouse_py=%02X, state->mouse_pcx=%02X, state->mouse_pcy=%02X\n",
2772//        logerror("mouse_px=%02X, mouse_py=%02X, mouse_pcx=%02X, mouse_pcy=%02X\n",
28412773//              state->mouse_px,state->mouse_py,state->mouse_pcx,state->mouse_pcy);
28422774
28432775//        logerror("mxb=%02x, mxa=%02X (mxb ^ mxa)=%02X, (ay8910_a & 0xC0)=%02X, (mxb ^ mxa) ^ ((ay8910_a & 0x80) >> 7)=%02X\n",
2844//              mxb,mxa, (mxb ^ mxa) , (ay8910_a & 0xC0), (mxb ^ mxa) ^ ((ay8910_a & 0x40) >> 6));
2776//              mxb,mxa, (mxb ^ mxa) , (state->ay8910_a & 0xC0), (mxb ^ mxa) ^ ((state->ay8910_a & 0x40) >> 6));
28452777    }
28462778
2847    intstate_x = (mxb ^ mxa) ^ ((ay8910_a & 0x40) >> 6);
2848    intstate_y = (myb ^ mya) ^ ((ay8910_a & 0x80) >> 7);
2779    intstate_x = (mxb ^ mxa) ^ ((drvstate->ay8910_a & 0x40) >> 6);
2780    intstate_y = (myb ^ mya) ^ ((drvstate->ay8910_a & 0x80) >> 7);
28492781
2850    if (MOUSE_INT_ENABLED())
2782    if (MOUSE_INT_ENABLED(drvstate))
28512783    {
28522784        if ((intstate_x==1) && (state->intstate_x==0))
28532785//        if (intstate_x!=state->intstate_x)
r9685r9686
28842816    if ((state->mouse_py!=MOUSE_PHASE_STATIC) || (state->mouse_px!=MOUSE_PHASE_STATIC))
28852817    {
28862818//        logerror("pc=%05X, reg0a4=%02X, reg092=%02X, ay_a=%02X, x=%02X, y=%02X, px=%02X, py=%02X, intstate_x=%02X, intstate_y=%02X\n",
2887//                 pc,state->reg0a4,iou_reg092,ay8910_a,state->mouse_x,state->mouse_y,state->mouse_px,state->mouse_py,intstate_x,intstate_y);
2819//                 pc,state->reg0a4,state->iou_reg092,state->ay8910_a,state->mouse_x,state->mouse_y,state->mouse_px,state->mouse_py,intstate_x,intstate_y);
28882820    }
28892821
28902822    state->intstate_x=intstate_x;
r9685r9686
28932825
28942826READ8_HANDLER( nimbus_mouse_js_r )
28952827{
2828   rmnimbus_state *drvstate = space->machine->driver_data<rmnimbus_state>();
28962829   /*
28972830
28982831        bit     description
r9685r9686
29072840        7       ?? always reads 1
29082841
29092842    */
2910   UINT8   result;
2911//  int     pc=cpu_get_pc(space->machine->device(MAINCPU_TAG));
2843   UINT8 result;
2844   //int pc=cpu_get_pc(space->machine->device(MAINCPU_TAG));
29122845
2913   _mouse_joy_state *state = &nimbus_mouse;
2846   _mouse_joy_state *state = &drvstate->nimbus_mouse;
29142847
29152848   if (input_port_read(space->machine, "config") & 0x01)
29162849   {
src/mess/video/pcw.c
r9685r9686
5050***************************************************************************/
5151VIDEO_UPDATE( pcw )
5252{
53   pcw_state *state = screen->machine->driver_data<pcw_state>();
5354   int x,y,b;
5455   unsigned short roller_ram_offs;
5556   unsigned char *roller_ram_ptr;
r9685r9686
5960   pen1 = 1;
6061
6162   /* invert? */
62   if (pcw_vdu_video_control_register & (1<<7))
63   if (state->vdu_video_control_register & (1<<7))
6364   {
6465      /* yes */
6566      pen1^=1;
r9685r9686
6768   }
6869
6970   /* video enable? */
70   if ((pcw_vdu_video_control_register & (1<<6))!=0)
71   if ((state->vdu_video_control_register & (1<<6))!=0)
7172   {
7273      rectangle rect;
7374
r9685r9686
8889      /* yes */
8990
9091      /* offset to start in table */
91      roller_ram_offs = (roller_ram_offset<<1);
92      roller_ram_offs = (state->roller_ram_offset<<1);
9293
9394      for (y=0; y<256; y++)
9495      {
r9685r9686
9899
99100         x = PCW_BORDER_WIDTH;
100101
101         roller_ram_ptr = messram_get_ptr(screen->machine->device("messram")) + roller_ram_addr + roller_ram_offs;
102         roller_ram_ptr = messram_get_ptr(screen->machine->device("messram")) + state->roller_ram_addr + roller_ram_offs;
102103
103104         /* get line address */
104105         /* b16-14 control which bank the line is to be found in, b13-3 the address in the bank (in 16-byte units), and b2-0 the offset. Thus a roller RAM address bbbxxxxxxxxxxxyyy indicates bank bbb, address 00xxxxxxxxxxx0yyy. */
src/mess/video/rmnimbus.c
r9685r9686
3131#include "debug/debugcpu.h"
3232#include "debug/debugcon.h"
3333
34static UINT8 video_mem[SCREEN_WIDTH_PIXELS][SCREEN_HEIGHT_LINES];
3534
3635#define WIDTH_MASK      0x07
3736#define XOR_MASK        0x08
r9685r9686
3938
4039// Offsets of nimbus video registers within register array
4140
42#define NO_VIDREGS      (0x30/2)
4341#define reg000          0x00
4442#define reg002          0x01
4543#define reg004          0x02
r9685r9686
6563#define reg02C          0x16
6664#define reg02E          0x17
6765
68#define FG_COLOUR       (vidregs[reg024]&0x0F)
69#define BG_COLOUR       ((vidregs[reg024]&0xF0)>>4)
66#define FG_COLOUR       (state->vidregs[reg024]&0x0F)
67#define BG_COLOUR       ((state->vidregs[reg024]&0xF0)>>4)
7068
71#define IS_80COL        (vidregs[reg026]&MASK_4080)
72#define IS_XOR          (vidregs[reg022]&XOR_MASK)
69#define IS_80COL        (state->vidregs[reg026]&MASK_4080)
70#define IS_XOR          (state->vidregs[reg022]&XOR_MASK)
7371
7472
75static UINT16 vidregs[NO_VIDREGS];
7673
77static UINT8   bpp;            // Bits / pixel
78static UINT16  pixel_mask;
79static UINT8   hs_count;
8074
8175#define DEBUG_TEXT  0x01
8276#define DEBUG_DB    0x02
8377#define DEBUG_PIXEL 0x04
8478
85#define DEBUG_SET(flags)    ((debug_video & (flags))==(flags))
86static UINT32 debug_video;
79#define DEBUG_SET(flags)    ((state->debug_video & (flags))==(flags))
8780
88static UINT8 get_pixel(UINT16 x, UINT16 y);
89static UINT16 read_pixel_line(UINT16 x, UINT16 y, UINT8 width);
90static UINT16 read_pixel_data(UINT16 x, UINT16 y);
91static UINT16 read_reg_00A(void);
81static UINT8 get_pixel(rmnimbus_state *state, UINT16 x, UINT16 y);
82static UINT16 read_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT8 width);
83static UINT16 read_pixel_data(rmnimbus_state *state, UINT16 x, UINT16 y);
84static UINT16 read_reg_00A(rmnimbus_state *state);
9285
93static void set_pixel(UINT16 x, UINT16 y, UINT8 colour);
94static void write_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width);
95static void write_pixel_data(UINT16 x, UINT16 y, UINT16    data);
96static void move_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width);
97static void write_reg_004(void);
98static void write_reg_006(void);
99static void write_reg_010(void);
100static void write_reg_012(void);
101static void write_reg_014(void);
102static void write_reg_01A(void);
103static void write_reg_01C(void);
104static void write_reg_026(void);
86static void set_pixel(rmnimbus_state *state, UINT16 x, UINT16 y, UINT8 colour);
87static void write_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data, UINT8 width);
88static void write_pixel_data(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data);
89static void move_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data, UINT8 width);
90static void write_reg_004(rmnimbus_state *state);
91static void write_reg_006(rmnimbus_state *state);
92static void write_reg_010(rmnimbus_state *state);
93static void write_reg_012(rmnimbus_state *state);
94static void write_reg_014(rmnimbus_state *state);
95static void write_reg_01A(rmnimbus_state *state);
96static void write_reg_01C(rmnimbus_state *state);
97static void write_reg_026(rmnimbus_state *state);
10598static void change_palette(running_machine *machine, UINT8 bank, UINT16 colours, UINT8 regno);
10699
107100static void video_debug(running_machine *machine, int ref, int params, const char *param[]);
r9685r9686
114107
115108READ16_HANDLER (nimbus_video_io_r)
116109{
110   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
117111    int     pc=cpu_get_pc(space->cpu);
118112    UINT16  result;
119113
120114    switch (offset)
121115    {
122        case    reg000  : result=vidregs[reg000]; break;
123        case    reg002  : result=vidregs[reg002]; break;
124        case    reg004  : result=vidregs[reg004]; break;
125        case    reg006  : result=vidregs[reg006]; break;
126        case    reg008  : result=vidregs[reg008]; break;
127        case    reg00A  : result=read_reg_00A(); break;
128        case    reg00C  : result=vidregs[reg00C]; break;
129        case    reg00E  : result=vidregs[reg00E]; break;
116        case    reg000  : result=state->vidregs[reg000]; break;
117        case    reg002  : result=state->vidregs[reg002]; break;
118        case    reg004  : result=state->vidregs[reg004]; break;
119        case    reg006  : result=state->vidregs[reg006]; break;
120        case    reg008  : result=state->vidregs[reg008]; break;
121        case    reg00A  : result=read_reg_00A(state); break;
122        case    reg00C  : result=state->vidregs[reg00C]; break;
123        case    reg00E  : result=state->vidregs[reg00E]; break;
130124
131        case    reg010  : result=vidregs[reg010]; break;
132        case    reg012  : result=vidregs[reg012]; break;
133        case    reg014  : result=vidregs[reg014]; break;
134        case    reg016  : result=vidregs[reg016]; break;
135        case    reg018  : result=vidregs[reg018]; break;
136        case    reg01A  : result=vidregs[reg01A]; break;
137        case    reg01C  : result=vidregs[reg01C]; break;
138        case    reg01E  : result=vidregs[reg01E]; break;
125        case    reg010  : result=state->vidregs[reg010]; break;
126        case    reg012  : result=state->vidregs[reg012]; break;
127        case    reg014  : result=state->vidregs[reg014]; break;
128        case    reg016  : result=state->vidregs[reg016]; break;
129        case    reg018  : result=state->vidregs[reg018]; break;
130        case    reg01A  : result=state->vidregs[reg01A]; break;
131        case    reg01C  : result=state->vidregs[reg01C]; break;
132        case    reg01E  : result=state->vidregs[reg01E]; break;
139133
140        case    reg020  : result=vidregs[reg020]; break;
141        case    reg022  : result=vidregs[reg022]; break;
142        case    reg024  : result=vidregs[reg024]; break;
143        case    reg026  : result=vidregs[reg026]; break;
144        case    reg028  : result=hs_count; break; //result=vidregs[reg028]; break;
145        case    reg02A  : result=vidregs[reg02A]; break;
146        case    reg02C  : result=vidregs[reg02C]; break;
147        case    reg02E  : result=vidregs[reg02E]; break;
134        case    reg020  : result=state->vidregs[reg020]; break;
135        case    reg022  : result=state->vidregs[reg022]; break;
136        case    reg024  : result=state->vidregs[reg024]; break;
137        case    reg026  : result=state->vidregs[reg026]; break;
138        case    reg028  : result=state->hs_count; break; //result=state->vidregs[reg028]; break;
139        case    reg02A  : result=state->vidregs[reg02A]; break;
140        case    reg02C  : result=state->vidregs[reg02C]; break;
141        case    reg02E  : result=state->vidregs[reg02E]; break;
148142        default         : result=0; break;
149143    }
150144
r9685r9686
154148    return result;
155149}
156150
157static UINT8 get_pixel(UINT16 x, UINT16 y)
151static UINT8 get_pixel(rmnimbus_state *state, UINT16 x, UINT16 y)
158152{
159153    UINT8   result = 0;
160154
161155    if((x<SCREEN_WIDTH_PIXELS) && (y<SCREEN_HEIGHT_LINES))
162156    {
163157        if(IS_80COL)
164            result=video_mem[x][y];
158            result=state->video_mem[x][y];
165159        else
166            result=video_mem[x*2][y];
160            result=state->video_mem[x*2][y];
167161    }
168162
169163    return result;
170164}
171165
172static UINT16 read_pixel_line(UINT16 x, UINT16 y, UINT8 width)
166static UINT16 read_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT8 width)
173167{
174168    UINT16  result = 0;
175169    UINT16  mask;
r9685r9686
178172    UINT8   shifts;
179173
180174    if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
181        logerror("read_pixel_line(x=%04X, y=%04X, width=%02X, bpp=%02X, pixel_mask=%02X)\n",x,y,width,bpp,pixel_mask);
175        logerror("read_pixel_line(x=%04X, y=%04X, width=%02X, bpp=%02X, pixel_mask=%02X)\n",x,y,width,state->bpp,state->pixel_mask);
182176
183    shifts=width-bpp;
177    shifts=width-state->bpp;
184178
185    for(mask=pixel_mask, pixel_x=(x*(width/bpp)); mask>0; mask=(mask>>bpp), pixel_x++)
179    for(mask=state->pixel_mask, pixel_x=(x*(width/state->bpp)); mask>0; mask=(mask>>state->bpp), pixel_x++)
186180    {
187        colour=get_pixel(pixel_x,y);
181        colour=get_pixel(state,pixel_x,y);
188182
189        if(bpp==1)
183        if(state->bpp==1)
190184            colour=((colour==FG_COLOUR) ? 1 : 0) << shifts;
191185        else
192186            colour=colour << shifts;
193187
194188        result=(result & ~mask)  | colour;
195189
196        shifts-=bpp;
190        shifts-=state->bpp;
197191    }
198192
199193    return result;
200194}
201195
202static UINT16 read_pixel_data(UINT16 x, UINT16 y)
196static UINT16 read_pixel_data(rmnimbus_state *state, UINT16 x, UINT16 y)
203197{
204198    UINT16  result=0;
205199
206200    if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
207        logerror("read_pixel_data(x=%04X, y=%04X), reg022=%04X\n",x,y,vidregs[reg022]);
201        logerror("read_pixel_data(x=%04X, y=%04X), reg022=%04X\n",x,y,state->vidregs[reg022]);
208202
209203    if(IS_80COL)
210204    {
211        switch (vidregs[reg022] & WIDTH_MASK)
205        switch (state->vidregs[reg022] & WIDTH_MASK)
212206        {
213207            case 0x00   : break;
214208
r9685r9686
222216
223217            case 0x05   : break;
224218
225            case 0x06   : bpp=2; pixel_mask=0xC000;
226                          result=read_pixel_line(x,y,16);
219            case 0x06   : state->bpp=2; state->pixel_mask=0xC000;
220                          result=read_pixel_line(state,x,y,16);
227221                          break;
228222
229223            case 0x07   : break;
r9685r9686
231225    }
232226    else /* 40 Col */
233227    {
234        switch (vidregs[reg022] & WIDTH_MASK)
228        switch (state->vidregs[reg022] & WIDTH_MASK)
235229        {
236230            case 0x00   : break;
237231
r9685r9686
245239
246240            case 0x05   : break;
247241
248            case 0x06   : bpp=4; pixel_mask=0xF000;
249                          result=read_pixel_line(x,y,16);
242            case 0x06   : state->bpp=4; state->pixel_mask=0xF000;
243                          result=read_pixel_line(state,x,y,16);
250244                          break;
251245
252246            case 0x07   : break;
r9685r9686
256250    return result;
257251}
258252
259static UINT16 read_reg_00A(void)
253static UINT16 read_reg_00A(rmnimbus_state *state)
260254{
261    return read_pixel_data(++vidregs[reg002],vidregs[reg00C]);
255    return read_pixel_data(state, ++state->vidregs[reg002],state->vidregs[reg00C]);
262256}
263257
264258
r9685r9686
274268
275269WRITE16_HANDLER (nimbus_video_io_w)
276270{
271   rmnimbus_state *state = space->machine->driver_data<rmnimbus_state>();
277272    int pc=cpu_get_pc(space->cpu);
278273
279274    if(offset<reg028)
r9685r9686
287282
288283    switch (offset)
289284    {
290        case    reg000  : vidregs[reg000]=data; break;
291        case    reg002  : vidregs[reg002]=data; break;
292        case    reg004  : vidregs[reg004]=data; write_reg_004(); break;
293        case    reg006  : vidregs[reg006]=data; write_reg_006(); break;
294        case    reg008  : vidregs[reg008]=data; break;
295        case    reg00A  : vidregs[reg00A]=data; break;
296        case    reg00C  : vidregs[reg00C]=data; break;
297        case    reg00E  : vidregs[reg00E]=data; break;
285        case    reg000  : state->vidregs[reg000]=data; break;
286        case    reg002  : state->vidregs[reg002]=data; break;
287        case    reg004  : state->vidregs[reg004]=data; write_reg_004(state); break;
288        case    reg006  : state->vidregs[reg006]=data; write_reg_006(state); break;
289        case    reg008  : state->vidregs[reg008]=data; break;
290        case    reg00A  : state->vidregs[reg00A]=data; break;
291        case    reg00C  : state->vidregs[reg00C]=data; break;
292        case    reg00E  : state->vidregs[reg00E]=data; break;
298293
299        case    reg010  : vidregs[reg010]=data; write_reg_010(); break;
300        case    reg012  : vidregs[reg012]=data; write_reg_012(); break;
301        case    reg014  : vidregs[reg014]=data; write_reg_014(); break;
302        case    reg016  : vidregs[reg016]=data; break;
303        case    reg018  : vidregs[reg018]=data; break;
304        case    reg01A  : vidregs[reg01A]=data; write_reg_01A(); break;
305        case    reg01C  : vidregs[reg01C]=data; write_reg_01C();break;
306        case    reg01E  : vidregs[reg01E]=data; break;
294        case    reg010  : state->vidregs[reg010]=data; write_reg_010(state); break;
295        case    reg012  : state->vidregs[reg012]=data; write_reg_012(state); break;
296        case    reg014  : state->vidregs[reg014]=data; write_reg_014(state); break;
297        case    reg016  : state->vidregs[reg016]=data; break;
298        case    reg018  : state->vidregs[reg018]=data; break;
299        case    reg01A  : state->vidregs[reg01A]=data; write_reg_01A(state); break;
300        case    reg01C  : state->vidregs[reg01C]=data; write_reg_01C(state);break;
301        case    reg01E  : state->vidregs[reg01E]=data; break;
307302
308        case    reg020  : vidregs[reg020]=data; break;
309        case    reg022  : vidregs[reg022]=data; break;
310        case    reg024  : vidregs[reg024]=data; break;
311        case    reg026  : vidregs[reg026]=data; write_reg_026(); break;
303        case    reg020  : state->vidregs[reg020]=data; break;
304        case    reg022  : state->vidregs[reg022]=data; break;
305        case    reg024  : state->vidregs[reg024]=data; break;
306        case    reg026  : state->vidregs[reg026]=data; write_reg_026(state); break;
312307        case    reg028  : change_palette(space->machine,0,data,reg028); break;
313308        case    reg02A  : change_palette(space->machine,1,data,reg02A); break;
314309        case    reg02C  : change_palette(space->machine,2,data,reg02C); break;
r9685r9686
318313    }
319314}
320315
321static void set_pixel(UINT16 x, UINT16 y, UINT8 colour)
316static void set_pixel(rmnimbus_state *state, UINT16 x, UINT16 y, UINT8 colour)
322317{
323318    if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
324319        logerror("set_pixel(x=%04X, y=%04X, colour=%04X), IS_XOR=%02X\n",x,y,colour,IS_XOR);
r9685r9686
329324    if((x<SCREEN_WIDTH_PIXELS) && (y<SCREEN_HEIGHT_LINES))
330325    {
331326        if(IS_XOR)
332            video_mem[x][y]^=colour;
327            state->video_mem[x][y]^=colour;
333328        else
334            video_mem[x][y]=colour;
329            state->video_mem[x][y]=colour;
335330    }
336331}
337332
338static void set_pixel40(UINT16 x, UINT16 y, UINT8 colour)
333static void set_pixel40(rmnimbus_state *state, UINT16 x, UINT16 y, UINT8 colour)
339334{
340    set_pixel((x*2),y,colour);
341    set_pixel((x*2)+1,y,colour);
335    set_pixel(state, (x*2),y,colour);
336    set_pixel(state, (x*2)+1,y,colour);
342337}
343338
344static void write_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width)
339static void write_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data, UINT8 width)
345340{
346341    UINT16  mask;
347342    UINT16  pixel_x;
r9685r9686
349344    UINT8   shifts;
350345
351346    if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
352        logerror("write_pixel_line(x=%04X, y=%04X, data=%04X, width=%02X, bpp=%02X, pixel_mask=%02X)\n",x,y,data,width,bpp,pixel_mask);
347        logerror("write_pixel_line(x=%04X, y=%04X, data=%04X, width=%02X, bpp=%02X, pixel_mask=%02X)\n",x,y,data,width,state->bpp,state->pixel_mask);
353348
354    shifts=width-bpp;
349    shifts=width-state->bpp;
355350
356    for(mask=pixel_mask, pixel_x=(x*(width/bpp)); mask>0; mask=(mask>>bpp), pixel_x++)
351    for(mask=state->pixel_mask, pixel_x=(x*(width/state->bpp)); mask>0; mask=(mask>>state->bpp), pixel_x++)
357352    {
358        if(bpp==1)
353        if(state->bpp==1)
359354            colour=(data & mask) ? FG_COLOUR : BG_COLOUR;
360355        else
361356            colour=(data & mask) >> shifts;
362357
363        //logerror("write_pixel_line: data=%04X, mask=%04X, shifts=%02X, bpp=%02X colour=%02X\n",data,mask,shifts,bpp,colour);
358        //logerror("write_pixel_line: data=%04X, mask=%04X, shifts=%02X, bpp=%02X colour=%02X\n",data,mask,shifts,state->bpp,colour);
364359
365360        if(IS_80COL)
366            set_pixel(pixel_x,y,colour);
361            set_pixel(state,pixel_x,y,colour);
367362        else
368            set_pixel40(pixel_x,y,colour);
363            set_pixel40(state,pixel_x,y,colour);
369364
370        shifts-=bpp;
365        shifts-=state->bpp;
371366    }
372367}
373368
374static void move_pixel_line(UINT16 x, UINT16 y, UINT16    data, UINT8 width)
369static void move_pixel_line(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data, UINT8 width)
375370{
376371    UINT16  pixelno;
377372    UINT16  pixelx;
r9685r9686
384379        pixelx=(x*width)+pixelno;
385380        if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
386381            logerror("pixelx=%04X\n",pixelx);
387        video_mem[pixelx][vidregs[reg020]]=video_mem[pixelx][y];
382        state->video_mem[pixelx][state->vidregs[reg020]]=state->video_mem[pixelx][y];
388383    }
389384}
390385
r9685r9686
415410    1   pixels are xor'ed onto the screen
416411*/
417412
418static void write_pixel_data(UINT16 x, UINT16 y, UINT16    data)
413static void write_pixel_data(rmnimbus_state *state, UINT16 x, UINT16 y, UINT16    data)
419414{
420415    if(DEBUG_SET(DEBUG_TEXT | DEBUG_PIXEL))
421        logerror("write_pixel_data(x=%04X, y=%04X, data=%04X), reg022=%04X\n",x,y,data,vidregs[reg022]);
416        logerror("write_pixel_data(x=%04X, y=%04X, data=%04X), reg022=%04X\n",x,y,data,state->vidregs[reg022]);
422417
423418    if(IS_80COL)
424419    {
425        switch (vidregs[reg022] & WIDTH_MASK)
420        switch (state->vidregs[reg022] & WIDTH_MASK)
426421        {
427            case 0x00   : bpp=1; pixel_mask=0x8000;
428                          write_pixel_line(x,y,data,16);
422            case 0x00   : state->bpp=1; state->pixel_mask=0x8000;
423                          write_pixel_line(state,x,y,data,16);
429424                          break;
430425
431            case 0x01   : bpp=1; pixel_mask=0x80;
432                          write_pixel_line(x,y,data,8);
426            case 0x01   : state->bpp=1; state->pixel_mask=0x80;
427                          write_pixel_line(state,x,y,data,8);
433428                          break;
434429
435            case 0x02   : bpp=1; pixel_mask=0x0080;
436                          write_pixel_line(x,y,data,8);
430            case 0x02   : state->bpp=1; state->pixel_mask=0x0080;
431                          write_pixel_line(state,x,y,data,8);
437432                          break;
438433
439            case 0x03   : bpp=1;
440                          set_pixel(x,y,FG_COLOUR);
434            case 0x03   : state->bpp=1;
435                          set_pixel(state,x,y,FG_COLOUR);
441436                          break;
442437
443            case 0x04   : bpp=2; pixel_mask=0xC0;
444                          write_pixel_line(x,y,((data & 0xFF) & ((data & 0xFF00)>>8)),8);
438            case 0x04   : state->bpp=2; state->pixel_mask=0xC0;
439                          write_pixel_line(state,x,y,((data & 0xFF) & ((data & 0xFF00)>>8)),8);
445440                          break;
446441
447            case 0x05   : move_pixel_line(x,y,data,16);
442            case 0x05   : move_pixel_line(state,x,y,data,16);
448443                          break;
449444
450            case 0x06   : bpp=2; pixel_mask=0xC000;
451                          write_pixel_line(x,y,data,16);
445            case 0x06   : state->bpp=2; state->pixel_mask=0xC000;
446                          write_pixel_line(state,x,y,data,16);
452447                          break;
453448
454            case 0x07   : bpp=1;
455                          set_pixel(x,y,FG_COLOUR);
449            case 0x07   : state->bpp=1;
450                          set_pixel(state,x,y,FG_COLOUR);
456451                          break;
457452        }
458453    }
459454    else /* 40 Col */
460455    {
461        switch (vidregs[reg022] & WIDTH_MASK)
456        switch (state->vidregs[reg022] & WIDTH_MASK)
462457        {
463            case 0x00   : bpp=1; pixel_mask=0x0080;
464                          write_pixel_line(x,y,data,8);
458            case 0x00   : state->bpp=1; state->pixel_mask=0x0080;
459                          write_pixel_line(state,x,y,data,8);
465460                          break;
466461
467            case 0x01   : bpp=2; pixel_mask=0xC0;
468                          write_pixel_line(x,y,data,8);
462            case 0x01   : state->bpp=2; state->pixel_mask=0xC0;
463                          write_pixel_line(state,x,y,data,8);
469464                          break;
470465
471            case 0x02   : bpp=1; pixel_mask=0x0080;
472                          set_pixel40(x,y,FG_COLOUR);
466            case 0x02   : state->bpp=1; state->pixel_mask=0x0080;
467                          set_pixel40(state,x,y,FG_COLOUR);
473468                          break;
474469
475            case 0x03   : bpp=1;
476                          set_pixel(x,y,FG_COLOUR);
470            case 0x03   : state->bpp=1;
471                          set_pixel(state,x,y,FG_COLOUR);
477472                          break;
478473
479            case 0x04   : bpp=4; pixel_mask=0xF0;
480                          write_pixel_line(x,y,((data & 0xFF) & ((data & 0xFF00)>>8)),8);
474            case 0x04   : state->bpp=4; state->pixel_mask=0xF0;
475                          write_pixel_line(state,x,y,((data & 0xFF) & ((data & 0xFF00)>>8)),8);
481476                          break;
482477
483            case 0x05   : move_pixel_line(x,y,data,16);
478            case 0x05   : move_pixel_line(state,x,y,data,16);
484479                          break;
485480
486            case 0x06   : bpp=4; pixel_mask=0xF000;
487                          write_pixel_line(x,y,data,16);
481            case 0x06   : state->bpp=4; state->pixel_mask=0xF000;
482                          write_pixel_line(state,x,y,data,16);
488483                          break;
489484
490            case 0x07   : bpp=1;
491                          set_pixel(x,y,FG_COLOUR);
485            case 0x07   : state->bpp=1;
486                          set_pixel(state,x,y,FG_COLOUR);
492487                          break;
493488        }
494489    }
495490}
496491
497static void write_reg_004(void)
492static void write_reg_004(rmnimbus_state *state)
498493{
499    vidregs[reg002]=0;
500    vidregs[reg00C]++;
494    state->vidregs[reg002]=0;
495    state->vidregs[reg00C]++;
501496}
502497
503static void write_reg_006(void)
498static void write_reg_006(rmnimbus_state *state)
504499{
505    vidregs[reg00C]++;
506    vidregs[reg002]=vidregs[reg006];
500    state->vidregs[reg00C]++;
501    state->vidregs[reg002]=state->vidregs[reg006];
507502}
508503
509static void write_reg_010(void)
504static void write_reg_010(rmnimbus_state *state)
510505{
511    write_pixel_data(vidregs[reg002],vidregs[reg00C],vidregs[reg010]);
506    write_pixel_data(state, state->vidregs[reg002],state->vidregs[reg00C],state->vidregs[reg010]);
512507}
513508
514static void write_reg_012(void)
509static void write_reg_012(rmnimbus_state *state)
515510{
516511    // I dunno if this is actually what is happening as the regs seem to be write only....
517512    // doing this however does seem to make some programs (worms from the welcom disk)
518513    // work correctly.
519    vidregs[reg002]=vidregs[reg012];
514    state->vidregs[reg002]=state->vidregs[reg012];
520515
521    write_pixel_data(vidregs[reg012],vidregs[reg00C],FG_COLOUR);
516    write_pixel_data(state, state->vidregs[reg012],state->vidregs[reg00C],FG_COLOUR);
522517}
523518
524static void write_reg_014(void)
519static void write_reg_014(rmnimbus_state *state)
525520{
526    write_pixel_data(vidregs[reg002],vidregs[reg00C]++,vidregs[reg014]);
521    write_pixel_data(state, state->vidregs[reg002],state->vidregs[reg00C]++,state->vidregs[reg014]);
527522}
528523
529static void write_reg_01A(void)
524static void write_reg_01A(rmnimbus_state *state)
530525{
531    write_pixel_data(++vidregs[reg002],vidregs[reg00C],vidregs[reg01A]);
526    write_pixel_data(state, ++state->vidregs[reg002],state->vidregs[reg00C],state->vidregs[reg01A]);
532527}
533528
534static void write_reg_01C(void)
529static void write_reg_01C(rmnimbus_state *state)
535530{
536531    // I dunno if this is actually what is happening as the regs seem to be write only....
537532    // doing this however does seem to make some programs (welcome from the welcom disk,
538533    // and others using the standard RM box menus) work correctly.
539    vidregs[reg00C]=vidregs[reg01C];
534    state->vidregs[reg00C]=state->vidregs[reg01C];
540535
541    write_pixel_data(vidregs[reg002],vidregs[reg01C],FG_COLOUR);
536    write_pixel_data(state, state->vidregs[reg002],state->vidregs[reg01C],FG_COLOUR);
542537}
543538
544539/*
r9685r9686
546541    bit 5 contains the 40/80 column (320/640 pixel) flag.
547542*/
548543
549static void write_reg_026(void)
544static void write_reg_026(rmnimbus_state *state)
550545{
551546    if(DEBUG_SET(DEBUG_TEXT))
552        logerror("reg 026 write, border_colour=%02X\n",vidregs[reg026] & 0x0F);
547        logerror("reg 026 write, border_colour=%02X\n",state->vidregs[reg026] & 0x0F);
553548}
554549
555550static void change_palette(running_machine *machine, UINT8 bank, UINT16 colours, UINT8 regno)
556551{
552   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
557553    UINT8   colourno;
558554    UINT16  mask;
559555    UINT8   shifts;
r9685r9686
562558    UINT8   first;
563559
564560    // for the register's data has changed update it, and then update the pallette, else do nothing.
565    if(vidregs[regno]!=colours)
566        vidregs[regno]=colours;
561    if(state->vidregs[regno]!=colours)
562        state->vidregs[regno]=colours;
567563    else
568564        return;
569565
r9685r9686
589585
590586static void video_debug(running_machine *machine, int ref, int params, const char *param[])
591587{
588   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
592589    if(params>0)
593590    {
594        sscanf(param[0],"%d",&debug_video);
591        sscanf(param[0],"%d",&state->debug_video);
595592    }
596593    else
597594    {
598595        debug_console_printf(machine,"Error usage : nimbus_vid_debug <debuglevel>\n");
599        debug_console_printf(machine,"Current debuglevel=%02X\n",debug_video);
596        debug_console_printf(machine,"Current debuglevel=%02X\n",state->debug_video);
600597    }
601598}
602599
603600static void video_regdump(running_machine *machine, int ref, int params, const char *param[])
604601{
602   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
605603    int regno;
606604
607605    for(regno=0;regno<0x08;regno++)
608606    {
609607        debug_console_printf(machine,"reg%03X=%04X reg%03X=%04X reg%03X=%04X\n",
610                regno*2,vidregs[regno],
611                (regno+0x08)*2,vidregs[regno+0x08],
612                (regno+0x10)*2,vidregs[regno+0x10]);
608                regno*2,state->vidregs[regno],
609                (regno+0x08)*2,state->vidregs[regno+0x08],
610                (regno+0x10)*2,state->vidregs[regno+0x10]);
613611
614612        logerror("reg%03X=%04X reg%03X=%04X reg%03X=%04X\n",
615                regno*2,vidregs[regno],
616                (regno+0x08)*2,vidregs[regno+0x08],
617                (regno+0x10)*2,vidregs[regno+0x10]);
613                regno*2,state->vidregs[regno],
614                (regno+0x08)*2,state->vidregs[regno+0x08],
615                (regno+0x10)*2,state->vidregs[regno+0x10]);
618616    }
619617}
620618
621619VIDEO_START( nimbus )
622620{
623    debug_video=0;
621   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
622    state->debug_video=0;
624623
625624    logerror("VIDEO_START\n");
626625
r9685r9686
633632
634633VIDEO_RESET( nimbus )
635634{
635   rmnimbus_state *state = machine->driver_data<rmnimbus_state>();
636636    // When we reset clear the video registers and video memory.
637    memset(&vidregs,0x00,sizeof(vidregs));
638    memset(&video_mem,0,sizeof(video_mem));
637    memset(&state->vidregs,0x00,sizeof(state->vidregs));
638    memset(&state->video_mem,0,sizeof(state->video_mem));
639639
640    bpp=4;          // bits per pixel
640    state->bpp=4;          // bits per pixel
641641    logerror("Video reset\n");
642642}
643643
r9685r9686
649649
650650VIDEO_UPDATE( nimbus )
651651{
652   rmnimbus_state *state = screen->machine->driver_data<rmnimbus_state>();
652653    int     XCoord;
653654    int     YCoord = screen->vpos();
654655
655656    for(XCoord=0;XCoord<SCREEN_WIDTH_PIXELS;XCoord++)
656657    {
657        *BITMAP_ADDR16(bitmap, YCoord, XCoord)=video_mem[XCoord][YCoord];
658        *BITMAP_ADDR16(bitmap, YCoord, XCoord)=state->video_mem[XCoord][YCoord];
658659    }
659660
660    hs_count++;
661    if((hs_count & 0x000F)>0x0A)
662        hs_count&=0xFFF0;
661    state->hs_count++;
662    if((state->hs_count & 0x000F)>0x0A)
663        state->hs_count&=0xFFF0;
663664
664665    return 0;
665666}
src/mess/includes/homelab.h
r9685r9686
88#define HOMELAB_H_
99
1010
11class homelab_state : public driver_device
12{
13public:
14   homelab_state(running_machine &machine, const driver_device_config_base &config)
15      : driver_device(machine, config) { }
16
17};
18
19
1120/*----------- defined in machine/homelab.c -----------*/
1221
1322extern DRIVER_INIT( homelab );
src/mess/includes/pc8401a.h
r9685r9686
4343   running_device *sed1330;
4444   running_device *mc6845;
4545   running_device *lcd;
46   UINT8 key_latch;
4647};
4748
4849/* ---------- defined in video/pc8401a.c ---------- */
src/mess/includes/ac1.h
r9685r9686
99
1010#include "machine/z80pio.h"
1111
12class ac1_state : public driver_device
13{
14public:
15   ac1_state(running_machine &machine, const driver_device_config_base &config)
16      : driver_device(machine, config) { }
17
18};
19
20
1221/*----------- defined in machine/ac1.c -----------*/
1322
1423DRIVER_INIT( ac1 );
src/mess/includes/pcw.h
r9685r9686
1818#define PCW_SCREEN_HEIGHT   (PCW_DISPLAY_HEIGHT  + (PCW_BORDER_HEIGHT<<1))
1919
2020
21/*----------- defined in drivers/pcw.c -----------*/
21class pcw_state : public driver_device
22{
23public:
24   pcw_state(running_machine &machine, const driver_device_config_base &config)
25      : driver_device(machine, config) { }
2226
23extern unsigned int roller_ram_addr;
24extern unsigned short roller_ram_offset;
25extern unsigned char pcw_vdu_video_control_register;
27   int boot;
28   int system_status;
29   int fdc_interrupt_code;
30   int interrupt_counter;
31   UINT8 banks[4];
32   unsigned char bank_force;
33   UINT8 timer_irq_flag;
34   UINT8 nmi_flag;
35   UINT8 printer_command;
36   UINT8 printer_data;
37   UINT8 printer_status;
38   UINT8 printer_headpos;
39   UINT16 kb_scan_row;
40   UINT8 mcu_keyboard_data[16];
41   UINT8 mcu_transmit_reset_seq;
42   UINT8 mcu_transmit_count;
43   UINT8 mcu_selected;
44   UINT8 mcu_buffer;
45   UINT8 mcu_prev;
46   unsigned int roller_ram_addr;
47   unsigned short roller_ram_offset;
48   unsigned char vdu_video_control_register;
49};
2650
51
2752/*----------- defined in video/pcw.c -----------*/
2853
2954extern VIDEO_START( pcw );
src/mess/includes/osborne1.h
r9685r9686
99
1010#include "machine/6821pia.h"
1111
12class osborne1_state : public driver_device
13{
14public:
15   osborne1_state(running_machine &machine, const driver_device_config_base &config)
16      : driver_device(machine, config) { }
17
18   UINT8   bank2_enabled;
19   UINT8   bank3_enabled;
20   UINT8   *bank4_ptr;
21   UINT8   *empty_4K;
22   /* IRQ states */
23   int      pia_0_irq_state;
24   int      pia_1_irq_state;
25   /* video related */
26   UINT8   new_start_x;
27   UINT8   new_start_y;
28   emu_timer   *video_timer;
29   UINT8   *charrom;
30   UINT8   charline;
31   UINT8   start_y;
32   /* bankswitch setting */
33   UINT8   bankswitch;
34   UINT8   in_irq_handler;
35   /* beep state */
36   UINT8   beep;
37};
38
39
1240/*----------- defined in machine/osborne1.c -----------*/
1341
1442extern const pia6821_interface osborne1_ieee_pia_config;
src/mess/includes/rmnimbus.h
r9685r9686
1313#define MAINCPU_TAG "maincpu"
1414#define IOCPU_TAG   "iocpu"
1515
16#define num_ioports 0x80
17#define NIMBUS_KEYROWS      11
18#define KEYBOARD_QUEUE_SIZE 32
19
1620#define SCREEN_WIDTH_PIXELS     640
1721#define SCREEN_HEIGHT_LINES     250
1822#define SCREEN_NO_COLOURS       16
1923
24#define NO_VIDREGS      (0x30/2)
2025
26/* Nimbus sub-bios structures for debugging */
27
28typedef struct
29{
30   UINT16  ofs_brush;
31   UINT16  seg_brush;
32   UINT16  ofs_data;
33   UINT16  seg_data;
34   UINT16  count;
35} t_area_params;
36
37typedef struct
38{
39   UINT16  ofs_font;
40   UINT16  seg_font;
41   UINT16  ofs_data;
42   UINT16  seg_data;
43   UINT16  x;
44   UINT16  y;
45   UINT16  length;
46} t_plot_string_params;
47
48typedef struct
49{
50   UINT16  style;
51   UINT16  style_index;
52   UINT16  colour1;
53   UINT16  colour2;
54   UINT16  transparency;
55   UINT16  boundary_spec;
56   UINT16  boundary_colour;
57   UINT16  save_colour;
58} t_nimbus_brush;
59
60#define SCREEN_WIDTH_PIXELS     640
61#define SCREEN_HEIGHT_LINES     250
62#define SCREEN_NO_COLOURS       16
63
64
65/* 80186 internal stuff */
66struct mem_state
67{
68   UINT16       lower;
69   UINT16       upper;
70   UINT16       middle;
71   UINT16       middle_size;
72   UINT16       peripheral;
73};
74
75struct timer_state
76{
77   UINT16       control;
78   UINT16       maxA;
79   UINT16       maxB;
80   UINT16       count;
81   emu_timer   *int_timer;
82   emu_timer   *time_timer;
83   UINT8       time_timer_active;
84   attotime   last_time;
85};
86
87struct dma_state
88{
89   UINT32       source;
90   UINT32       dest;
91   UINT16       count;
92   UINT16       control;
93   UINT8       finished;
94   emu_timer   *finish_timer;
95};
96
97struct intr_state
98{
99   UINT8   pending;
100   UINT16   ack_mask;
101   UINT16   priority_mask;
102   UINT16   in_service;
103   UINT16   request;
104   UINT16   status;
105   UINT16   poll_status;
106   UINT16   timer;
107   UINT16   dma[2];
108   UINT16   ext[4];
109   UINT16  ext_vector[2]; // external vectors, when in cascade mode
110};
111
112typedef struct
113{
114   struct timer_state   timer[3];
115   struct dma_state   dma[2];
116   struct intr_state   intr;
117   struct mem_state   mem;
118} i186_state;
119
120typedef struct
121{
122   UINT8       keyrows[NIMBUS_KEYROWS];
123   emu_timer   *keyscan_timer;
124   UINT8       queue[KEYBOARD_QUEUE_SIZE];
125   UINT8       head;
126   UINT8       tail;
127}  keyboard_t;
128
129// Static data related to Floppy and SCSI hard disks
130typedef struct
131{
132   UINT8   reg400;
133   UINT8   reg410_in;
134   UINT8   reg410_out;
135   UINT8   reg418;
136
137   UINT8   drq_ff;
138   UINT8   int_ff;
139} nimbus_drives_t;
140
141/* 8031 Peripheral controler */
142typedef struct
143{
144   UINT8   ipc_in;
145   UINT8   ipc_out;
146   UINT8   status_in;
147   UINT8   status_out;
148   UINT8   int_8c_pending;
149   UINT8   int_8e_pending;
150   UINT8   int_8f_pending;
151} ipc_interface_t;
152
153/* Mouse/Joystick */
154typedef struct
155{
156   UINT8   mouse_px;
157   UINT8   mouse_py;
158
159   UINT8   mouse_x;
160   UINT8   mouse_y;
161   UINT8   mouse_pc;
162   UINT8   mouse_pcx;
163   UINT8   mouse_pcy;
164
165   UINT8   intstate_x;
166   UINT8   intstate_y;
167
168   UINT8   reg0a4;
169
170   emu_timer   *mouse_timer;
171} _mouse_joy_state;
172
173
174class rmnimbus_state : public driver_device
175{
176public:
177   rmnimbus_state(running_machine &machine, const driver_device_config_base &config)
178      : driver_device(machine, config) { }
179
180   UINT32 debug_machine;
181   i186_state i186;
182   keyboard_t keyboard;
183   nimbus_drives_t nimbus_drives;
184   ipc_interface_t ipc_interface;
185   UINT8 mcu_reg080;
186   UINT8 iou_reg092;
187   UINT8 last_playmode;
188   _mouse_joy_state nimbus_mouse;
189   UINT8 ay8910_a;
190   UINT16 IOPorts[num_ioports];
191   UINT8 sio_int_state;
192   UINT8 video_mem[SCREEN_WIDTH_PIXELS][SCREEN_HEIGHT_LINES];
193   UINT16 vidregs[NO_VIDREGS];
194   UINT8 bpp;
195   UINT16 pixel_mask;
196   UINT8 hs_count;
197   UINT32 debug_video;
198};
199
200
21201/*----------- defined in drivers/rmnimbus.c -----------*/
22202
23203extern const unsigned char nimbus_palette[SCREEN_NO_COLOURS][3];
r9685r9686
101281/* Z80 SIO for keyboard */
102282
103283#define Z80SIO_TAG          "z80sio"
104#define NIMBUS_KEYROWS      11
105#define KEYBOARD_QUEUE_SIZE 32
106284
107285extern const z80sio_interface nimbus_sio_intf;
108286
r9685r9686
138316#define FDC_DRQ_MASK    0x80
139317#define FDC_DRIVE_MASK  (FDC_DRIVE0_MASK | FDC_DRIVE1_MASK | FDC_DRIVE2_MASK | FDC_DRIVE3_MASK)
140318
141#define FDC_SIDE()          ((nimbus_drives.reg400 & FDC_SIDE_MASK) >> 4)
142#define FDC_MOTOR()         ((nimbus_drives.reg400 & FDC_MOTOR_MASKO) >> 5)
143#define FDC_DRIVE()         (scsibus_driveno(nimbus_drives.reg400 & FDC_DRIVE_MASK))
144#define HDC_DRQ_ENABLED()   ((nimbus_drives.reg400 & HDC_DRQ_MASK) ? 1 : 0)
145#define FDC_DRQ_ENABLED()   ((nimbus_drives.reg400 & FDC_DRQ_MASK) ? 1 : 0)
319#define FDC_SIDE()          ((state->nimbus_drives.reg400 & FDC_SIDE_MASK) >> 4)
320#define FDC_MOTOR()         ((state->nimbus_drives.reg400 & FDC_MOTOR_MASKO) >> 5)
321#define FDC_DRIVE()         (scsibus_driveno(state->nimbus_drives.reg400 & FDC_DRIVE_MASK))
322#define HDC_DRQ_ENABLED()   ((state->nimbus_drives.reg400 & HDC_DRQ_MASK) ? 1 : 0)
323#define FDC_DRQ_ENABLED(state)   ((state->nimbus_drives.reg400 & FDC_DRQ_MASK) ? 1 : 0)
146324
147325/* Masks for port 0x410 read*/
148326
r9685r9686
166344#define HDC_RESET_MASK  0x01
167345#define HDC_SEL_MASK    0x02
168346#define HDC_IRQ_MASK    0x04
169#define HDC_IRQ_ENABLED()   ((nimbus_drives.reg410_out & HDC_IRQ_MASK) ? 1 : 0)
347#define HDC_IRQ_ENABLED(state)   ((state->nimbus_drives.reg410_out & HDC_IRQ_MASK) ? 1 : 0)
170348
171349
172350#define SCSI_ID_NONE    0x80
r9685r9686
236414READ8_HANDLER( nimbus_mouse_js_r );
237415WRITE8_HANDLER( nimbus_mouse_js_w );
238416
239#define MOUSE_INT_ENABLED()     ((iou_reg092 & MOUSE_INT_ENABLE) ? 1 : 0)
417#define MOUSE_INT_ENABLED(state)     (((state)->iou_reg092 & MOUSE_INT_ENABLE) ? 1 : 0)
240418
241419
242420/*----------- defined in video/rmnimbus.c -----------*/
r9685r9686
255433
256434#define LINEAR_ADDR(seg,ofs)    ((seg<<4)+ofs)
257435
258/* Nimbus sub-bios structures for debugging */
259
260typedef struct
261{
262    UINT16  ofs_brush;
263    UINT16  seg_brush;
264    UINT16  ofs_data;
265    UINT16  seg_data;
266    UINT16  count;
267} t_area_params;
268
269typedef struct
270{
271    UINT16  ofs_font;
272    UINT16  seg_font;
273    UINT16  ofs_data;
274    UINT16  seg_data;
275    UINT16  x;
276    UINT16  y;
277    UINT16  length;
278} t_plot_string_params;
279
280typedef struct
281{
282    UINT16  style;
283    UINT16  style_index;
284    UINT16  colour1;
285    UINT16  colour2;
286    UINT16  transparency;
287    UINT16  boundary_spec;
288    UINT16  boundary_colour;
289    UINT16  save_colour;
290} t_nimbus_brush;
291
292436#define OUTPUT_SEGOFS(mess,seg,ofs)  logerror("%s=%04X:%04X [%08X]\n",mess,seg,ofs,((seg<<4)+ofs))
src/mess/drivers/dectalk.c
r9685r9686
148148#include "machine/terminal.h"
149149
150150
151/* Components */
152
153static struct
151class dectalk_state : public driver_device
154152{
155UINT8 data[8]; // hack to prevent gcc bitching about struct pointers. not used.
156UINT8 x2214_sram[256]; // NVRAM chip's temp sram space
157UINT8 statusLED;
158// input fifo, between m68k and tms32010
159UINT16 infifo[32]; // technically eight 74LS224 4bit*16stage FIFO chips, arranged as a 32 stage, 16-bit wide fifo
160UINT8 infifo_tail_ptr;
161UINT8 infifo_head_ptr;
162// output fifo, between tms32010 and 10khz sample latch for dac
163UINT16 outfifo[16]; // technically three 74LS224 4bit*16stage FIFO chips, arranged as a 16 stage, 12-bit wide fifo
164UINT8 outfifo_tail_ptr;
165UINT8 outfifo_head_ptr;
166UINT8 infifo_semaphore; // latch for status of output fifo, d-latch 74ls74 @ E64 'lower half'
167UINT8 spc_error_latch; // latch for error status of speech dsp, d-latch 74ls74 @ E64 'upper half'
168UINT8 m68k_spcflags_latch; // latch for initializing the speech dsp, d-latch 74ls74 @ E29 'lower half', AND latch for spc irq enable, d-latch 74ls74 @ E29 'upper half'; these are stored in bits 0 and 6 respectively, the rest of the bits stored here MUST be zeroed!
169UINT8 m68k_tlcflags_latch; // latch for telephone interface stuff, d-latches 74ls74 @ E93 'upper half' and @ 103 'upper and lower halves'
170UINT8 simulate_outfifo_error; // simulate an error on the outfifo, which does something unusual to the dsp latches
171UINT8 tlc_tonedetect;
172UINT8 tlc_ringdetect;
173UINT8 tlc_dtmf; // dtmf holding reg
174UINT8 duart_inport; // low 4 bits of duart input
175UINT8 duart_outport; // most recent duart output
176} dectalk={ {0}};
153public:
154   dectalk_state(running_machine &machine, const driver_device_config_base &config)
155      : driver_device(machine, config) { }
177156
157   UINT8 data[8]; // hack to prevent gcc bitching about struct pointers. not used.
158   UINT8 x2214_sram[256]; // NVRAM chip's temp sram space
159   UINT8 statusLED;
160   // input fifo, between m68k and tms32010
161   UINT16 infifo[32]; // technically eight 74LS224 4bit*16stage FIFO chips, arranged as a 32 stage, 16-bit wide fifo
162   UINT8 infifo_tail_ptr;
163   UINT8 infifo_head_ptr;
164   // output fifo, between tms32010 and 10khz sample latch for dac
165   UINT16 outfifo[16]; // technically three 74LS224 4bit*16stage FIFO chips, arranged as a 16 stage, 12-bit wide fifo
166   UINT8 outfifo_tail_ptr;
167   UINT8 outfifo_head_ptr;
168   UINT8 infifo_semaphore; // latch for status of output fifo, d-latch 74ls74 @ E64 'lower half'
169   UINT8 spc_error_latch; // latch for error status of speech dsp, d-latch 74ls74 @ E64 'upper half'
170   UINT8 m68k_spcflags_latch; // latch for initializing the speech dsp, d-latch 74ls74 @ E29 'lower half', AND latch for spc irq enable, d-latch 74ls74 @ E29 'upper half'; these are stored in bits 0 and 6 respectively, the rest of the bits stored here MUST be zeroed!
171   UINT8 m68k_tlcflags_latch; // latch for telephone interface stuff, d-latches 74ls74 @ E93 'upper half' and @ 103 'upper and lower halves'
172   UINT8 simulate_outfifo_error; // simulate an error on the outfifo, which does something unusual to the dsp latches
173   UINT8 tlc_tonedetect;
174   UINT8 tlc_ringdetect;
175   UINT8 tlc_dtmf; // dtmf holding reg
176   UINT8 duart_inport; // low 4 bits of duart input
177   UINT8 duart_outport; // most recent duart output
178   UINT8 hack_self_test; // temp variable for hack below
179};
180
181
178182/* Devices */
179183static void duart_irq_handler(running_device *device, UINT8 vector)
180184{
181      cputag_set_input_line_and_vector(device->machine, "maincpu", M68K_IRQ_6, HOLD_LINE, M68K_INT_ACK_AUTOVECTOR);
182      //cputag_set_input_line_and_vector(device->machine, "maincpu", M68K_IRQ_6, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR);
185   cputag_set_input_line_and_vector(device->machine, "maincpu", M68K_IRQ_6, HOLD_LINE, M68K_INT_ACK_AUTOVECTOR);
186   //cputag_set_input_line_and_vector(device->machine, "maincpu", M68K_IRQ_6, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR);
183187   //cputag_set_input_line_and_vector(device->machine, "maincpu", M68K_IRQ_6, HOLD_LINE, vector);
184188};
185189
186 static UINT8 hack_self_test = 0; // temp variable for hack below
187
188190static UINT8 duart_input(running_device *device)
189191{
192   dectalk_state *state = device->machine->driver_data<dectalk_state>();
190193   UINT8 data = 0;
191   data |= dectalk.duart_inport&0xF;
194   data |= state->duart_inport&0xF;
192195   data |= (input_port_read(device->machine, "duart_in")&0xF0);
193    if ((hack_self_test == 1) && (input_port_read(device->machine, "hacks")&0x01)) data |= 0x10; // hack to prevent hang if selftest disable bit is kept low past the first read; i suppose the proper use of this bit was an incremental switch, or perhaps its expecting an interrupt later from serial in or tone in? added a dipswitch to disable the hack for testing
194    hack_self_test = 1;
196   if ((state->hack_self_test == 1) && (input_port_read(device->machine, "hacks")&0x01)) data |= 0x10; // hack to prevent hang if selftest disable bit is kept low past the first read; i suppose the proper use of this bit was an incremental switch, or perhaps its expecting an interrupt later from serial in or tone in? added a dipswitch to disable the hack for testing
197      state->hack_self_test = 1;
195198   return data;
196199}
197200
198201static void duart_output(running_device *device, UINT8 data)
199202{
200   dectalk.duart_outport = data;
203   dectalk_state *state = device->machine->driver_data<dectalk_state>();
204   state->duart_outport = data;
201205#ifdef SERIAL_TO_STDERR
202206   fprintf(stderr, "RTS: %01X, DTR: %01X\n", data&1, (data&4)>>2);
203207#endif
r9685r9686
220224   duart_output
221225};
222226
223#define SPC_INITIALIZE dectalk.m68k_spcflags_latch&0x1 // speech initialize flag
224#define SPC_IRQ_ENABLED ((dectalk.m68k_spcflags_latch&0x40)>>6) // irq enable flag
227#define SPC_INITIALIZE state->m68k_spcflags_latch&0x1 // speech initialize flag
228#define SPC_IRQ_ENABLED ((state->m68k_spcflags_latch&0x40)>>6) // irq enable flag
225229
226230static void dectalk_outfifo_check (running_machine *machine)
227231{
232   dectalk_state *state = machine->driver_data<dectalk_state>();
228233   // check if output fifo is full; if it isn't, set the int on the dsp
229   if (((dectalk.outfifo_head_ptr-1)&0xF) != dectalk.outfifo_tail_ptr)
234   if (((state->outfifo_head_ptr-1)&0xF) != state->outfifo_tail_ptr)
230235   cputag_set_input_line(machine, "dsp", 0, ASSERT_LINE); // TMS32010 INT
231236   else
232237   cputag_set_input_line(machine, "dsp", 0, CLEAR_LINE); // TMS32010 INT
r9685r9686
234239
235240static void dectalk_clear_all_fifos( running_machine *machine )
236241{
242   dectalk_state *state = machine->driver_data<dectalk_state>();
237243   // clear fifos (TODO: memset would work better here...)
238244   int i;
239   for (i=0; i<16; i++) dectalk.outfifo[i] = 0;
240   for (i=0; i<32; i++) dectalk.infifo[i] = 0;
241   dectalk.outfifo_tail_ptr = dectalk.outfifo_head_ptr = 0;
242   dectalk.infifo_tail_ptr = dectalk.infifo_head_ptr = 0;
245   for (i=0; i<16; i++) state->outfifo[i] = 0;
246   for (i=0; i<32; i++) state->infifo[i] = 0;
247   state->outfifo_tail_ptr = state->outfifo_head_ptr = 0;
248   state->infifo_tail_ptr = state->infifo_head_ptr = 0;
243249   dectalk_outfifo_check(machine);
244250}
245251
246252static void dectalk_x2212_store( running_machine *machine )
247253{
254   dectalk_state *state = machine->driver_data<dectalk_state>();
248255   UINT8 *nvram = memory_region(machine, "nvram");
249256   int i;
250257   for (i = 0; i < 256; i++)
251   nvram[i] = dectalk.x2214_sram[i];
258   nvram[i] = state->x2214_sram[i];
252259#ifdef NVRAM_LOG
253260   logerror("nvram store done\n");
254261#endif
r9685r9686
256263
257264static void dectalk_x2212_recall( running_machine *machine )
258265{
266   dectalk_state *state = machine->driver_data<dectalk_state>();
259267   UINT8 *nvram = memory_region(machine, "nvram");
260268   int i;
261269   for (i = 0; i < 256; i++)
262   dectalk.x2214_sram[i] = nvram[i];
270   state->x2214_sram[i] = nvram[i];
263271#ifdef NVRAM_LOG
264272   logerror("nvram recall done\n");
265273#endif
r9685r9686
268276// helper for dsp infifo_semaphore flag to make dealing with interrupts easier
269277static void dectalk_semaphore_w ( running_machine *machine, UINT16 data )
270278{
271   dectalk.infifo_semaphore = data&1;
272   if ((dectalk.infifo_semaphore == 1) && (dectalk.m68k_spcflags_latch&0x40))
279   dectalk_state *state = machine->driver_data<dectalk_state>();
280   state->infifo_semaphore = data&1;
281   if ((state->infifo_semaphore == 1) && (state->m68k_spcflags_latch&0x40))
273282   {
274283#ifdef VERBOSE
275284      logerror("speech int fired!\n");
r9685r9686
283292// read the output fifo and set the interrupt line active on the dsp
284293static UINT16 dectalk_outfifo_r ( running_machine *machine )
285294{
295   dectalk_state *state = machine->driver_data<dectalk_state>();
286296   UINT16 data = 0xFFFF;
287   data = dectalk.outfifo[dectalk.outfifo_tail_ptr];
297   data = state->outfifo[state->outfifo_tail_ptr];
288298   // if fifo is empty (tail ptr == head ptr), do not increment the tail ptr, otherwise do.
289   //if (dectalk.outfifo_tail_ptr != dectalk.outfifo_head_ptr) dectalk.outfifo_tail_ptr++; // technically correct but doesn't match sn74ls224 sheet
290   if (((dectalk.outfifo_head_ptr-1)&0xF) != dectalk.outfifo_tail_ptr) dectalk.outfifo_tail_ptr++; // matches sn74ls224 sheet
291   dectalk.outfifo_tail_ptr&=0xF;
299   //if (state->outfifo_tail_ptr != state->outfifo_head_ptr) state->outfifo_tail_ptr++; // technically correct but doesn't match sn74ls224 sheet
300   if (((state->outfifo_head_ptr-1)&0xF) != state->outfifo_tail_ptr) state->outfifo_tail_ptr++; // matches sn74ls224 sheet
301   state->outfifo_tail_ptr&=0xF;
292302   dectalk_outfifo_check(machine);
293303   return ((data&0xfff0)^0x8000); // yes this is right, top bit is inverted and bottom 4 are ignored
294304   //return data; // not right but want to get it working first
r9685r9686
297307/* Machine reset and friends: stuff that needs setting up which IS directly affected by reset */
298308static void dectalk_reset(running_device *device)
299309{
310   dectalk_state *state = device->machine->driver_data<dectalk_state>();
300311   const running_device *devconf = device->machine->device("duart68681"); // this is probably an evil disgusting hack, and AaronGiles is gonna throttle me for doing this...
301   hack_self_test = 0; // hack
312   state->hack_self_test = 0; // hack
302313   // stuff that is DIRECTLY affected by the RESET line
303   dectalk.statusLED = 0; // clear status led latch
314   state->statusLED = 0; // clear status led latch
304315   dectalk_x2212_recall(device->machine); // nvram recall
305   dectalk.m68k_spcflags_latch = 1; // initial status is speech reset(d0) active and spc int(d6) disabled
306   dectalk.m68k_tlcflags_latch = 0; // initial status is tone detect int(d6) off, answer phone(d8) off, ring detect int(d14) off
316   state->m68k_spcflags_latch = 1; // initial status is speech reset(d0) active and spc int(d6) disabled
317   state->m68k_tlcflags_latch = 0; // initial status is tone detect int(d6) off, answer phone(d8) off, ring detect int(d14) off
307318   DEVICE_RESET(devconf); // reset the DUART
308319   devconf = devconf; // hack to make gcc shut up about unused variables. the variable IS USED!
309320   //device->machine->device("duart68681")->reset(); // reset the DUART
310321   // stuff that is INDIRECTLY affected by the RESET line
311322   dectalk_clear_all_fifos(device->machine); // speech reset clears the fifos, though we have to do it explicitly here since we're not actually in the m68k_spcflags_w function.
312   dectalk_semaphore_w(device->machine, 0); // on the original dectalk pcb revision, this is a semaphore for the INPUT fifo, later dec hacked on a check for the 3 output fifo chips to see if they're in sync, and set both of these latches if true.
313   dectalk.spc_error_latch = 0; // spc error latch is cleared on /reset
323   dectalk_semaphore_w(device->machine, 0); // on the original state->dectalk pcb revision, this is a semaphore for the INPUT fifo, later dec hacked on a check for the 3 output fifo chips to see if they're in sync, and set both of these latches if true.
324   state->spc_error_latch = 0; // spc error latch is cleared on /reset
314325   cputag_set_input_line(device->machine, "dsp", INPUT_LINE_RESET, ASSERT_LINE); // speech reset forces the CLR line active on the tms32010
315   dectalk.tlc_tonedetect = 0; // TODO, needed for selftest pass
316   dectalk.tlc_ringdetect = 0; // TODO
317   dectalk.tlc_dtmf = 0; // TODO
318   dectalk.duart_inport = 0xF;
319   dectalk.duart_outport = 0;
326   state->tlc_tonedetect = 0; // TODO, needed for selftest pass
327   state->tlc_ringdetect = 0; // TODO
328   state->tlc_dtmf = 0; // TODO
329   state->duart_inport = 0xF;
330   state->duart_outport = 0;
320331}
321332
322333static MACHINE_RESET( dectalk )
r9685r9686
328339/* Begin 68k i/o handlers */
329340static READ8_HANDLER( nvram_read ) // read from x2212 nvram chip and possibly do recall
330341{
342   dectalk_state *state = space->machine->driver_data<dectalk_state>();
331343   UINT8 data = 0xFF;
332   data = dectalk.x2214_sram[offset&0xff]; // TODO: should this be before or after a possible /RECALL? I'm guessing before.
344   data = state->x2214_sram[offset&0xff]; // TODO: should this be before or after a possible /RECALL? I'm guessing before.
333345#ifdef NVRAM_LOG
334346      logerror("m68k: nvram read at %08X: %02X\n", offset, data);
335347#endif
r9685r9686
340352
341353static WRITE8_HANDLER( led_write )
342354{
343   dectalk.statusLED = data&0xFF;
355   dectalk_state *state = space->machine->driver_data<dectalk_state>();
356   state->statusLED = data&0xFF;
344357   popmessage("LED status: %02X\n", data&0xFF);
345358#ifdef VERBOSE
346359   logerror("m68k: LED status: %02X\n", data&0xFF);
r9685r9686
350363
351364static WRITE8_HANDLER( nvram_write ) // write to X2212 NVRAM chip and possibly do store
352365{
366   dectalk_state *state = space->machine->driver_data<dectalk_state>();
353367#ifdef NVRAM_LOG
354368   logerror("m68k: nvram write at %08X: %02X\n", offset, data&0x0f);
355369#endif
356   dectalk.x2214_sram[offset&0xff] = (UINT8)data&0x0f; // TODO: should this be before or after a possible /STORE? I'm guessing before.
370   state->x2214_sram[offset&0xff] = (UINT8)data&0x0f; // TODO: should this be before or after a possible /STORE? I'm guessing before.
357371   if (offset&0x200) // if a9 is set, do a /STORE
358372   dectalk_x2212_store(space->machine);
359373}
360374
361375static WRITE16_HANDLER( m68k_infifo_w ) // 68k write to the speech input fifo
362376{
377   dectalk_state *state = space->machine->driver_data<dectalk_state>();
363378#ifdef USE_LOOSE_TIMING
364379   cpuexec_boost_interleave(space->machine, attotime_zero, ATTOTIME_IN_USEC(25));
365380#endif
366381#ifdef SPC_LOG_68K
367   logerror("m68k: SPC infifo written with data = %04X, fifo head was: %02X; fifo tail: %02X\n",data, dectalk.infifo_head_ptr, dectalk.infifo_tail_ptr);
382   logerror("m68k: SPC infifo written with data = %04X, fifo head was: %02X; fifo tail: %02X\n",data, state->infifo_head_ptr, state->infifo_tail_ptr);
368383#endif
369384   // if fifo is full (head ptr = tail ptr-1), do not increment the head ptr and do not store the data
370   if (((dectalk.infifo_tail_ptr-1)&0x1F) == dectalk.infifo_head_ptr)
385   if (((state->infifo_tail_ptr-1)&0x1F) == state->infifo_head_ptr)
371386   {
372387#ifdef SPC_LOG_68K
373388      logerror("infifo was full, write ignored!\n");
374389#endif
375390      return;
376391   }
377   dectalk.infifo[dectalk.infifo_head_ptr] = data;
378   dectalk.infifo_head_ptr++;
379   dectalk.infifo_head_ptr&=0x1F;
392   state->infifo[state->infifo_head_ptr] = data;
393   state->infifo_head_ptr++;
394   state->infifo_head_ptr&=0x1F;
380395}
381396
382397static READ16_HANDLER( m68k_spcflags_r ) // 68k read from the speech flags
383398{
399   dectalk_state *state = space->machine->driver_data<dectalk_state>();
384400   UINT8 data = 0;
385   data |= dectalk.m68k_spcflags_latch; // bits 0 and 6
386   data |= dectalk.spc_error_latch<<5; // bit 5
387   data |= dectalk.infifo_semaphore<<7; // bit 7
401   data |= state->m68k_spcflags_latch; // bits 0 and 6
402   data |= state->spc_error_latch<<5; // bit 5
403   data |= state->infifo_semaphore<<7; // bit 7
388404#ifdef SPC_LOG_68K
389405   logerror("m68k: SPC flags read, returning data = %04X\n",data);
390406#endif
r9685r9686
393409
394410static WRITE16_HANDLER( m68k_spcflags_w ) // 68k write to the speech flags (only 3 bits do anything)
395411{
412   dectalk_state *state = space->machine->driver_data<dectalk_state>();
396413#ifdef USE_LOOSE_TIMING
397414   cpuexec_boost_interleave(space->machine, attotime_zero, ATTOTIME_IN_USEC(25));
398415#endif
399416#ifdef SPC_LOG_68K
400417   logerror("m68k: SPC flags written with %04X, only storing %04X\n",data, data&0x41);
401418#endif
402   dectalk.m68k_spcflags_latch = data&0x41; // ONLY store bits 6 and 0!
419   state->m68k_spcflags_latch = data&0x41; // ONLY store bits 6 and 0!
403420   // d0: initialize speech flag (reset tms32010 and clear infifo and outfifo if high)
404421   if ((data&0x1) == 0x1) // bit 0
405422   {
r9685r9686
409426      dectalk_clear_all_fifos(space->machine);
410427      cputag_set_input_line(space->machine, "dsp", INPUT_LINE_RESET, ASSERT_LINE); // speech reset forces the CLR line active on the tms32010
411428      // clear the two speech side latches
412      dectalk.spc_error_latch = 0;
429      state->spc_error_latch = 0;
413430      dectalk_semaphore_w(space->machine, 0);
414431   }
415432   else // (data&0x1) == 0
r9685r9686
425442      logerror(" | 0x02: clear error+semaphore latches\n");
426443#endif
427444      // clear the two speech side latches
428      dectalk.spc_error_latch = 0;
445      state->spc_error_latch = 0;
429446      dectalk_semaphore_w(space->machine, 0);
430447   }
431448   if ((data&0x40) == 0x40) // bit 6 - spc irq enable
r9685r9686
433450#ifdef SPC_LOG_68K
434451      logerror(" | 0x40: speech int enabled\n");
435452#endif
436      if ((dectalk.infifo_semaphore == 1))
453      if ((state->infifo_semaphore == 1))
437454      {
438455#ifdef SPC_LOG_68K
439456         logerror("    speech int fired!\n");
r9685r9686
452469
453470static READ16_HANDLER( m68k_tlcflags_r ) // dtmf flags read
454471{
472   dectalk_state *state = space->machine->driver_data<dectalk_state>();
455473   UINT16 data = 0;
456   data |= dectalk.m68k_tlcflags_latch; // bits 6, 8, 14;
457   data |= dectalk.tlc_tonedetect<<7; // bit 7 is tone detect
458   data |= dectalk.tlc_ringdetect<<14; // bit 15 is ring detect
474   data |= state->m68k_tlcflags_latch; // bits 6, 8, 14;
475   data |= state->tlc_tonedetect<<7; // bit 7 is tone detect
476   data |= state->tlc_ringdetect<<14; // bit 15 is ring detect
459477#ifdef TLC_LOG
460478   logerror("m68k: TLC flags read, returning data = %04X\n",data);
461479#endif
r9685r9686
464482
465483static WRITE16_HANDLER( m68k_tlcflags_w ) // dtmf flags write
466484{
485   dectalk_state *state = space->machine->driver_data<dectalk_state>();
467486#ifdef TLC_LOG
468487   logerror("m68k: TLC flags written with %04X, only storing %04X\n",data, data&0x4140);
469488#endif
470   dectalk.m68k_tlcflags_latch = data&0x4140; // ONLY store bits 6 8 and 14!
489   state->m68k_tlcflags_latch = data&0x4140; // ONLY store bits 6 8 and 14!
471490   if ((data&0x40) == 0x40) // bit 6: tone detect interrupt enable
472491   {
473492#ifdef TLC_LOG
474493      logerror(" | 0x40: tone detect int enabled\n");
475494#endif
476      if ((dectalk.tlc_tonedetect == 1))
495      if ((state->tlc_tonedetect == 1))
477496      {
478497#ifdef TLC_LOG
479498         logerror("    TLC int fired!\n");
r9685r9686
486505#ifdef TLC_LOG
487506      logerror(" | 0x40 = 0: tone detect int disabled\n");
488507#endif
489   if (((data&0x4000)!=0x4000) || (dectalk.tlc_ringdetect == 0)) // check to be sure we don't disable int if both ints fired at once
508   if (((data&0x4000)!=0x4000) || (state->tlc_ringdetect == 0)) // check to be sure we don't disable int if both ints fired at once
490509      cputag_set_input_line_and_vector(space->machine, "maincpu", M68K_IRQ_4, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR); // clear int because int is now disabled
491510   }
492511   if ((data&0x100) == 0x100) // bit 8: answer phone relay enable
r9685r9686
506525#ifdef TLC_LOG
507526      logerror(" | 0x4000: ring detect int enabled\n");
508527#endif
509      if ((dectalk.tlc_ringdetect == 1))
528      if ((state->tlc_ringdetect == 1))
510529      {
511530#ifdef TLC_LOG
512531         logerror("    TLC int fired!\n");
r9685r9686
519538#ifdef TLC_LOG
520539      logerror(" | 0x4000 = 0: ring detect int disabled\n");
521540#endif
522   if (((data&0x40)!=0x40) || (dectalk.tlc_tonedetect == 0)) // check to be sure we don't disable int if both ints fired at once
541   if (((data&0x40)!=0x40) || (state->tlc_tonedetect == 0)) // check to be sure we don't disable int if both ints fired at once
523542      cputag_set_input_line_and_vector(space->machine, "maincpu", M68K_IRQ_4, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR); // clear int because int is now disabled
524543   }
525544}
526545
527546static READ16_HANDLER( m68k_tlc_dtmf_r ) // dtmf chip read
528547{
548   dectalk_state *state = space->machine->driver_data<dectalk_state>();
529549   UINT16 data = 0xFFFF;
530   data = dectalk.tlc_dtmf&0xF;
550   data = state->tlc_dtmf&0xF;
531551#ifdef TLC_LOG
532552   logerror("m68k: TLC dtmf detector read, returning data = %02X", data);
533553#endif
r9685r9686
538558/* Begin tms32010 i/o handlers */
539559static WRITE16_HANDLER( spc_latch_outfifo_error_stats ) // latch 74ls74 @ E64 upper and lower halves with d0 and 1 respectively
540560{
561   dectalk_state *state = space->machine->driver_data<dectalk_state>();
541562#ifdef USE_LOOSE_TIMING
542563   cpuexec_boost_interleave(space->machine, attotime_zero, ATTOTIME_IN_USEC(25));
543564#endif
544565#ifdef SPC_LOG_DSP
545566   logerror("dsp: set fifo semaphore and set error status = %01X\n",data&1);
546567#endif
547   dectalk_semaphore_w(space->machine, (~dectalk.simulate_outfifo_error)&1); // always set to 1 here, unless outfifo error.
548   dectalk.spc_error_latch = (data&1);
568   dectalk_semaphore_w(space->machine, (~state->simulate_outfifo_error)&1); // always set to 1 here, unless outfifo error.
569   state->spc_error_latch = (data&1);
549570}
550571
551572static READ16_HANDLER( spc_infifo_data_r )
552573{
574   dectalk_state *state = space->machine->driver_data<dectalk_state>();
553575   UINT16 data = 0xFFFF;
554   data = dectalk.infifo[dectalk.infifo_tail_ptr];
576   data = state->infifo[state->infifo_tail_ptr];
555577#ifdef SPC_LOG_DSP
556   logerror("dsp: SPC infifo read with data = %04X, fifo head: %02X; fifo tail was: %02X\n",data, dectalk.infifo_head_ptr, dectalk.infifo_tail_ptr);
578   logerror("dsp: SPC infifo read with data = %04X, fifo head: %02X; fifo tail was: %02X\n",data, state->infifo_head_ptr, state->infifo_tail_ptr);
557579#endif
558580   // if fifo is empty (tail ptr == head ptr), do not increment the tail ptr, otherwise do.
559   if (dectalk.infifo_tail_ptr != dectalk.infifo_head_ptr) dectalk.infifo_tail_ptr++; // technically correct but doesn't match sn74ls224 sheet
560   //if (((dectalk.infifo_head_ptr-1)&0x1F) != dectalk.infifo_tail_ptr) dectalk.infifo_tail_ptr++; // matches sn74ls224 sheet
561   dectalk.infifo_tail_ptr&=0x1F;
581   if (state->infifo_tail_ptr != state->infifo_head_ptr) state->infifo_tail_ptr++; // technically correct but doesn't match sn74ls224 sheet
582   //if (((state->infifo_head_ptr-1)&0x1F) != state->infifo_tail_ptr) state->infifo_tail_ptr++; // matches sn74ls224 sheet
583   state->infifo_tail_ptr&=0x1F;
562584   return data;
563585}
564586
565587static WRITE16_HANDLER( spc_outfifo_data_w )
566588{
589   dectalk_state *state = space->machine->driver_data<dectalk_state>();
567590   // the low 4 data bits are thrown out on the real unit due to use of a 12 bit dac (and to save use of another 16x4 fifo chip), though technically they're probably valid, and with suitable hacking a dtc-01 could probably output full 16 bit samples at 10khz.
568591#ifdef SPC_LOG_DSP
569   logerror("dsp: SPC outfifo write, data = %04X, fifo head was: %02X; fifo tail: %02X\n", data, dectalk.outfifo_head_ptr, dectalk.outfifo_tail_ptr);
592   logerror("dsp: SPC outfifo write, data = %04X, fifo head was: %02X; fifo tail: %02X\n", data, state->outfifo_head_ptr, state->outfifo_tail_ptr);
570593#endif
571594   cputag_set_input_line(space->machine, "dsp", 0, CLEAR_LINE); //TMS32010 INT (cleared because LDCK inverts the IR line, clearing int on any outfifo write... for a moment at least.)
572595   // if fifo is full (head ptr = tail ptr-1), do not increment the head ptr and do not store the data
573   if (((dectalk.outfifo_tail_ptr-1)&0xF) == dectalk.outfifo_head_ptr)
596   if (((state->outfifo_tail_ptr-1)&0xF) == state->outfifo_head_ptr)
574597   {
575598#ifdef SPC_LOG_DSP
576599      logerror("outfifo was full, write ignored!\n");
577600#endif
578601      return;
579602   }
580   dectalk.outfifo[dectalk.outfifo_head_ptr] = data;
581   dectalk.outfifo_head_ptr++;
582   dectalk.outfifo_head_ptr&=0xF;
603   state->outfifo[state->outfifo_head_ptr] = data;
604   state->outfifo_head_ptr++;
605   state->outfifo_head_ptr&=0xF;
583606   //dectalk_outfifo_check(space->machine); // commented to allow int to clear
584607}
585608
586609static READ16_HANDLER( spc_semaphore_r ) // Return state of d-latch 74ls74 @ E64 'lower half' in d0 which indicates whether infifo is readable
587610{
611   dectalk_state *state = space->machine->driver_data<dectalk_state>();
588612#ifdef SPC_LOG_DSP
589   //logerror("dsp: read infifo semaphore, returned %d\n", dectalk.infifo_semaphore); // commented due to extreme annoyance factor
590   if (!dectalk.infifo_semaphore) logerror("dsp: read infifo semaphore, returned %d\n", dectalk.infifo_semaphore);
613   //logerror("dsp: read infifo semaphore, returned %d\n", state->infifo_semaphore); // commented due to extreme annoyance factor
614   if (!state->infifo_semaphore) logerror("dsp: read infifo semaphore, returned %d\n", state->infifo_semaphore);
591615#endif
592   return dectalk.infifo_semaphore;
616   return state->infifo_semaphore;
593617}
594618/* end tms32010 i/o handlers */
595619
r9685r9686
687711/* Driver init: stuff that needs setting up which isn't directly affected by reset */
688712static DRIVER_INIT( dectalk )
689713{
714   dectalk_state *state = machine->driver_data<dectalk_state>();
690715   dectalk_clear_all_fifos(machine);
691   dectalk.simulate_outfifo_error = 0;
716   state->simulate_outfifo_error = 0;
692717   timer_set(machine, ATTOTIME_IN_HZ(10000), NULL, 0,  outfifo_read_cb);
693718}
694719
r9685r9686
702727   DEVCB_HANDLER(dectalk_kbd_put)
703728};
704729
705static MACHINE_CONFIG_START( dectalk, driver_device )
730static MACHINE_CONFIG_START( dectalk, dectalk_state )
706731    /* basic machine hardware */
707732    MDRV_CPU_ADD("maincpu", M68000, XTAL_20MHz/2) /* E74 20MHz OSC (/2) */
708733    MDRV_CPU_PROGRAM_MAP(m68k_mem)
src/mess/drivers/homelab.c
r9685r9686
148148
149149
150150/* Machine driver */
151static MACHINE_CONFIG_START( homelab, driver_device )
151static MACHINE_CONFIG_START( homelab, homelab_state )
152152   /* basic machine hardware */
153153   MDRV_CPU_ADD("maincpu", Z80, 3000000)
154154   MDRV_CPU_PROGRAM_MAP(homelab2_mem)
src/mess/drivers/vt520.c
r9685r9686
1010#include "devices/messram.h"
1111#include "cpu/mcs51/mcs51.h"
1212
13
14class vt520_state : public driver_device
15{
16public:
17   vt520_state(running_machine &machine, const driver_device_config_base &config)
18      : driver_device(machine, config) { }
19
20};
21
22
1323static ADDRESS_MAP_START(vt520_mem, ADDRESS_SPACE_PROGRAM, 8)
1424   AM_RANGE(0x0000, 0xffff) AM_RAMBANK("bank1")
1525ADDRESS_MAP_END
r9685r9686
5464    return 0;
5565}
5666
57static MACHINE_CONFIG_START( vt520, driver_device )
67static MACHINE_CONFIG_START( vt520, vt520_state )
5868    /* basic machine hardware */
5969    MDRV_CPU_ADD("maincpu",I8032, XTAL_20MHz)
6070    MDRV_CPU_PROGRAM_MAP(vt520_mem)
src/mess/drivers/a3000.c
r9685r9686
1010#include "cpu/m68000/m68000.h"
1111
1212
13class a3000_state : public driver_device
14{
15public:
16   a3000_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
22
1323/***************************************************************************
1424    CONSTANTS
1525***************************************************************************/
r9685r9686
4050    MACHINE DRIVERS
4151***************************************************************************/
4252
43static MACHINE_CONFIG_START( a3000, driver_device )
53static MACHINE_CONFIG_START( a3000, a3000_state )
4454   MDRV_CPU_ADD("maincpu", M68030, XTAL_U104 / 2)
4555   MDRV_CPU_PROGRAM_MAP(a3000_mem)
4656
src/mess/drivers/unistar.c
r9685r9686
99#include "emu.h"
1010#include "cpu/i8085/i8085.h"
1111
12
13class unistar_state : public driver_device
14{
15public:
16   unistar_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(unistar_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x0000, 0x3fff) AM_ROM
r9685r9686
5565   GFXDECODE_ENTRY( "gfx", 0x0000, unistar_charlayout, 0, 1 )
5666GFXDECODE_END
5767
58static MACHINE_CONFIG_START( unistar, driver_device )
68static MACHINE_CONFIG_START( unistar, unistar_state )
5969    /* basic machine hardware */
6070    MDRV_CPU_ADD("maincpu",I8085A, XTAL_2MHz)
6171    MDRV_CPU_PROGRAM_MAP(unistar_mem)
src/mess/drivers/mmd1.c
r9685r9686
1111#include "mmd1.lh"
1212#include "mmd2.lh"
1313
14
15class mmd1_state : public driver_device
16{
17public:
18   mmd1_state(running_machine &machine, const driver_device_config_base &config)
19      : driver_device(machine, config) { }
20
21};
22
23
1424static WRITE8_HANDLER (mmd1_port0_w)
1525{
1626   output_set_value("p0_7", BIT(data,7) ? 0 : 1);
r9685r9686
161171{
162172}
163173
164static MACHINE_CONFIG_START( mmd1, driver_device )
174static MACHINE_CONFIG_START( mmd1, mmd1_state )
165175    /* basic machine hardware */
166176    MDRV_CPU_ADD("maincpu",I8080, 6750000 / 9)
167177    MDRV_CPU_PROGRAM_MAP(mmd1_mem)
r9685r9686
173183   MDRV_DEFAULT_LAYOUT(layout_mmd1)
174184MACHINE_CONFIG_END
175185
176static MACHINE_CONFIG_START( mmd2, driver_device )
186static MACHINE_CONFIG_START( mmd2, mmd1_state )
177187    /* basic machine hardware */
178188    MDRV_CPU_ADD("maincpu",I8080, 6750000 / 9)
179189    MDRV_CPU_PROGRAM_MAP(mmd2_mem)
src/mess/drivers/elekscmp.c
r9685r9686
1010#include "cpu/scmp/scmp.h"
1111#include "elekscmp.lh"
1212
13
14class elekscmp_state : public driver_device
15{
16public:
17   elekscmp_state(running_machine &machine, const driver_device_config_base &config)
18      : driver_device(machine, config) { }
19
20};
21
22
1323static WRITE8_HANDLER(hex_display_w)
1424{
1525   output_set_digit_value(7-offset, data);
r9685r9686
3848{
3949}
4050
41static MACHINE_CONFIG_START( elekscmp, driver_device )
51static MACHINE_CONFIG_START( elekscmp, elekscmp_state )
4252    /* basic machine hardware */
4353    MDRV_CPU_ADD("maincpu",INS8060, XTAL_4MHz)
4454    MDRV_CPU_PROGRAM_MAP(elekscmp_mem)
src/mess/drivers/msbc1.c
r9685r9686
99#include "emu.h"
1010#include "cpu/m68000/m68000.h"
1111
12
13class msbc1_state : public driver_device
14{
15public:
16   msbc1_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(msbc1_mem, ADDRESS_SPACE_PROGRAM, 16)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x00000000, 0x00007fff) AM_ROM AM_REGION("user1",0)
r9685r9686
3343    return 0;
3444}
3545
36static MACHINE_CONFIG_START( msbc1, driver_device )
46static MACHINE_CONFIG_START( msbc1, msbc1_state )
3747    /* basic machine hardware */
3848    MDRV_CPU_ADD("maincpu",M68000, XTAL_8MHz)
3949    MDRV_CPU_PROGRAM_MAP(msbc1_mem)
src/mess/drivers/ti99_8.c
r9685r9686
210210#include "machine/ti99/gromport.h"
211211#include "machine/ti99/mecmouse.h"
212212
213
214class ti99_8_state : public driver_device
215{
216public:
217   ti99_8_state(running_machine &machine, const driver_device_config_base &config)
218      : driver_device(machine, config) { }
219
220};
221
222
213223/*
214224    Memory map - see description above
215225*/
r9685r9686
571581{
572582}
573583
574static MACHINE_CONFIG_START( ti99_8_60hz, driver_device )
584static MACHINE_CONFIG_START( ti99_8_60hz, ti99_8_state )
575585   /* basic machine hardware */
576586   /* TMS9995-MP9537 CPU @ 10.7 MHz */
577587   MDRV_CPU_ADD("maincpu", TMS9995, 10738635)
r9685r9686
616626MACHINE_CONFIG_END
617627
618628
619static MACHINE_CONFIG_START( ti99_8_50hz, driver_device )
629static MACHINE_CONFIG_START( ti99_8_50hz, ti99_8_state )
620630   /* basic machine hardware */
621631   /* TMS9995-MP9537 CPU @ 10.7 MHz */
622632   MDRV_CPU_ADD("maincpu", TMS9995, 10738635)
src/mess/drivers/sc1.c
r9685r9686
99#include "emu.h"
1010#include "cpu/z80/z80.h"
1111
12
13class sc1_state : public driver_device
14{
15public:
16   sc1_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(sc1_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x0fff ) AM_ROM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( sc1, driver_device )
50static MACHINE_CONFIG_START( sc1, sc1_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
4353    MDRV_CPU_PROGRAM_MAP(sc1_mem)
src/mess/drivers/pipbug.c
r9685r9686
99#include "emu.h"
1010#include "cpu/s2650/s2650.h"
1111
12
13class pipbug_state : public driver_device
14{
15public:
16   pipbug_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(pipbug_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x03ff) AM_ROM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( pipbug, driver_device )
50static MACHINE_CONFIG_START( pipbug, pipbug_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",S2650, XTAL_1MHz)
4353    MDRV_CPU_PROGRAM_MAP(pipbug_mem)
src/mess/drivers/chessmst.c
r9685r9686
99#include "emu.h"
1010#include "cpu/z80/z80.h"
1111
12
13class chessmst_state : public driver_device
14{
15public:
16   chessmst_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(chessmst_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x27ff ) AM_ROM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( chessmst, driver_device )
50static MACHINE_CONFIG_START( chessmst, chessmst_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
4353    MDRV_CPU_PROGRAM_MAP(chessmst_mem)
src/mess/drivers/dolphin.c
r9685r9686
99#include "emu.h"
1010#include "cpu/s2650/s2650.h"
1111
12
13class dolphin_state : public driver_device
14{
15public:
16   dolphin_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(dolphin_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x00ff) AM_ROM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( dolphin, driver_device )
50static MACHINE_CONFIG_START( dolphin, dolphin_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",S2650, XTAL_1MHz)
4353    MDRV_CPU_PROGRAM_MAP(dolphin_mem)
src/mess/drivers/a6809.c
r9685r9686
1515#include "video/saa5050.h"
1616#include "video/mc6845.h"
1717
18
19class a6809_state : public driver_device
20{
21public:
22   a6809_state(running_machine &machine, const driver_device_config_base &config)
23      : driver_device(machine, config) { }
24
25};
26
27
1828static ADDRESS_MAP_START(a6809_mem, ADDRESS_SPACE_PROGRAM, 8)
1929   ADDRESS_MAP_UNMAP_HIGH
2030   AM_RANGE(0x0000,0x03ff) AM_RAM
r9685r9686
90100   DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_IRQ0)
91101};
92102
93static MACHINE_CONFIG_START( a6809, driver_device )
103static MACHINE_CONFIG_START( a6809, a6809_state )
94104   /* basic machine hardware */
95105   MDRV_CPU_ADD("maincpu",M6809E, XTAL_4MHz)
96106   MDRV_CPU_PROGRAM_MAP(a6809_mem)
src/mess/drivers/tm990189.c
r9685r9686
7373   device_image_interface *rs232_fp;
7474   UINT8 rs232_rts;
7575   emu_timer *rs232_input_timer;
76   UINT8 bogus_read_save;
7677};
7778
7879
r9685r9686
514515
515516static  READ8_HANDLER(video_vdp_r)
516517{
518   tm990189_state *state = space->machine->driver_data<tm990189_state>();
517519   int reply = 0;
518   static UINT8 bogus_read_save;
519520
520521   /* When the tms9980 reads @>2000 or @>2001, it actually does a word access:
521522    it reads @>2000 first, then @>2001.  According to schematics, both access
r9685r9686
537538      reply = TMS9928A_vram_r(space, 0);
538539
539540   if (!(offset & 1))
540      bogus_read_save = reply;
541      state->bogus_read_save = reply;
541542   else
542      reply = bogus_read_save;
543      reply = state->bogus_read_save;
543544
544545   return reply;
545546}
src/mess/drivers/selz80.c
r9685r9686
1313#include "cpu/z80/z80.h"
1414#include "selz80.lh"
1515
16static UINT8 selz80_digit;
17static UINT8 selz80_segment;
1816
17class selz80_state : public driver_device
18{
19public:
20   selz80_state(running_machine &machine, const driver_device_config_base &config)
21      : driver_device(machine, config) { }
22
23   UINT8 digit;
24   UINT8 segment;
25};
26
27
28
1929static READ8_HANDLER( selz80_00_r )
2030{
2131   return 0xff; // keyboard scan code
r9685r9686
2838
2939static WRITE8_HANDLER( selz80_01_w )
3040{
41   selz80_state *state = space->machine->driver_data<selz80_state>();
3142   if ((data & 0xc0)==0x80)
3243   {
33      selz80_digit = data & 7;
34      output_set_digit_value(selz80_digit, selz80_segment);
44      state->digit = data & 7;
45      output_set_digit_value(state->digit, state->segment);
3546   }
3647}
3748
3849static WRITE8_HANDLER( selz80_00_w )
3950{
40   selz80_segment = BITSWAP8(data, 3, 2, 1, 0, 7, 6, 5, 4);
41   output_set_digit_value(selz80_digit, selz80_segment);
51   selz80_state *state = space->machine->driver_data<selz80_state>();
52   state->segment = BITSWAP8(data, 3, 2, 1, 0, 7, 6, 5, 4);
53   output_set_digit_value(state->digit, state->segment);
4254}
4355
4456static ADDRESS_MAP_START(selz80_mem, ADDRESS_SPACE_PROGRAM, 8)
r9685r9686
7082{
7183}
7284
73static MACHINE_CONFIG_START( selz80, driver_device )
85static MACHINE_CONFIG_START( selz80, selz80_state )
7486   /* basic machine hardware */
7587   MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
7688   MDRV_CPU_PROGRAM_MAP(selz80_mem)
src/mess/drivers/h89.c
r9685r9686
99#include "emu.h"
1010#include "cpu/z80/z80.h"
1111
12
13class h89_state : public driver_device
14{
15public:
16   h89_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(h89_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x0000, 0x0fff) AM_ROM
r9685r9686
3848    return 0;
3949}
4050
41static MACHINE_CONFIG_START( h89, driver_device )
51static MACHINE_CONFIG_START( h89, h89_state )
4252    /* basic machine hardware */
4353    MDRV_CPU_ADD("maincpu",Z80, XTAL_12_288MHz / 6)
4454    MDRV_CPU_PROGRAM_MAP(h89_mem)
src/mess/drivers/zsbc3.c
r9685r9686
1111#include "cpu/z80/z80.h"
1212#include "machine/terminal.h"
1313
14static UINT8 term_data;
1514
15class zsbc3_state : public driver_device
16{
17public:
18   zsbc3_state(running_machine &machine, const driver_device_config_base &config)
19      : driver_device(machine, config) { }
20
21   UINT8 term_data;
22};
23
24
25
1626static WRITE8_HANDLER( zsbc3_28_w )
1727{
1828   running_device *terminal = space->machine->device("terminal");
r9685r9686
2232
2333static READ8_HANDLER( zsbc3_28_r )
2434{
25   UINT8 ret = term_data;
26   term_data = 0;
35   zsbc3_state *state = space->machine->driver_data<zsbc3_state>();
36   UINT8 ret = state->term_data;
37   state->term_data = 0;
2738   return ret;
2839}
2940
3041static READ8_HANDLER( zsbc3_2a_r )
3142{
32   return 4 | ((term_data) ? 1 : 0);
43   zsbc3_state *state = space->machine->driver_data<zsbc3_state>();
44   return 4 | ((state->term_data) ? 1 : 0);
3345}
3446
3547static ADDRESS_MAP_START(zsbc3_mem, ADDRESS_SPACE_PROGRAM, 8)
r9685r9686
5769
5870static WRITE8_DEVICE_HANDLER( zsbc3_kbd_put )
5971{
60   term_data = data;
72   zsbc3_state *state = device->machine->driver_data<zsbc3_state>();
73   state->term_data = data;
6174}
6275
6376static GENERIC_TERMINAL_INTERFACE( zsbc3_terminal_intf )
r9685r9686
6679};
6780
6881
69static MACHINE_CONFIG_START( zsbc3, driver_device )
82static MACHINE_CONFIG_START( zsbc3, zsbc3_state )
7083   /* basic machine hardware */
7184   MDRV_CPU_ADD("maincpu",Z80, XTAL_16MHz /4)
7285   MDRV_CPU_PROGRAM_MAP(zsbc3_mem)
src/mess/drivers/pcw.c
r9685r9686
111111static WRITE_LINE_DEVICE_HANDLER( pcw_fdc_interrupt );
112112
113113// pointer to pcw ram
114unsigned int roller_ram_addr;
115114// flag to indicate if boot-program is enabled/disabled
116static int   pcw_boot;
117static int   pcw_system_status;
118unsigned short roller_ram_offset;
119115// code for CPU int type generated when FDC int is triggered
120static int fdc_interrupt_code;
121unsigned char pcw_vdu_video_control_register;
122static int pcw_interrupt_counter;
123116
124static UINT8 pcw_banks[4];
125static unsigned char pcw_bank_force = 0;
126117
127static UINT8 pcw_timer_irq_flag;
128static UINT8 pcw_nmi_flag;
129118
130static UINT8 pcw_printer_command;
131static UINT8 pcw_printer_data;
132static UINT8 pcw_printer_status;
133static UINT8 pcw_printer_headpos; // non-zero if not at left margin
134119
135static UINT16 pcw_kb_scan_row;
136120
137static UINT8 mcu_keyboard_data[16];
138static UINT8 mcu_transmit_reset_seq;
139static UINT8 mcu_transmit_count;
140121
141static void pcw_update_interrupt_counter(void)
122static void pcw_update_interrupt_counter(pcw_state *state)
142123{
143124   /* never increments past 15! */
144   if (pcw_interrupt_counter==0x0f)
125   if (state->interrupt_counter==0x0f)
145126      return;
146127
147128   /* increment count */
148   pcw_interrupt_counter++;
129   state->interrupt_counter++;
149130}
150131
151132/* PCW uses UPD765 in NON-DMA mode. FDC Ints are connected to /INT or
r9685r9686
162143// set/reset INT and NMI lines
163144static void pcw_update_irqs(running_machine *machine)
164145{
146   pcw_state *state = machine->driver_data<pcw_state>();
165147   // set NMI line, remains set until FDC interrupt type is changed
166   if(pcw_nmi_flag != 0)
148   if(state->nmi_flag != 0)
167149      cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, ASSERT_LINE);
168150   else
169151      cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
170152
171153   // set IRQ line, timer pulses IRQ line, all other devices hold it as necessary
172   if(fdc_interrupt_code == 1 && (pcw_system_status & 0x20))
154   if(state->fdc_interrupt_code == 1 && (state->system_status & 0x20))
173155   {
174156      cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE);
175157      return;
176158   }
177159
178   if(pcw_timer_irq_flag != 0)
160   if(state->timer_irq_flag != 0)
179161   {
180162      cputag_set_input_line(machine, "maincpu", 0, ASSERT_LINE);
181163      return;
r9685r9686
186168
187169static TIMER_CALLBACK(pcw_timer_pulse)
188170{
189   pcw_timer_irq_flag = 0;
171   pcw_state *state = machine->driver_data<pcw_state>();
172   state->timer_irq_flag = 0;
190173   pcw_update_irqs(machine);
191174}
192175
193176/* callback for 1/300ths of a second interrupt */
194177static TIMER_CALLBACK(pcw_timer_interrupt)
195178{
196   pcw_update_interrupt_counter();
179   pcw_state *state = machine->driver_data<pcw_state>();
180   pcw_update_interrupt_counter(state);
197181
198   pcw_timer_irq_flag = 1;
182   state->timer_irq_flag = 1;
199183   pcw_update_irqs(machine);
200184   timer_set(machine,ATTOTIME_IN_USEC(2),NULL,0,pcw_timer_pulse);
201185}
r9685r9686
203187/* fdc interrupt callback. set/clear fdc int */
204188static WRITE_LINE_DEVICE_HANDLER( pcw_fdc_interrupt )
205189{
190   pcw_state *drvstate = device->machine->driver_data<pcw_state>();
206191   if (state == CLEAR_LINE)
207      pcw_system_status &= ~(1<<5);
192      drvstate->system_status &= ~(1<<5);
208193   else
209194   {
210      pcw_system_status |= (1<<5);
211      if(fdc_interrupt_code == 0)  // NMI is held until interrupt type is changed
212         pcw_nmi_flag = 1;
195      drvstate->system_status |= (1<<5);
196      if(drvstate->fdc_interrupt_code == 0)  // NMI is held until interrupt type is changed
197         drvstate->nmi_flag = 1;
213198   }
214199}
215200
r9685r9686
243228
244229static READ8_HANDLER(pcw_keyboard_data_r)
245230{
246   return mcu_keyboard_data[offset];
231   pcw_state *state = space->machine->driver_data<pcw_state>();
232   return state->mcu_keyboard_data[offset];
247233}
248234
249235/* -----------------------------------------------------------------------
r9685r9686
294280
295281static void pcw_update_mem(running_machine *machine, int block, int data)
296282{
283   pcw_state *state = machine->driver_data<pcw_state>();
297284   /* expansion ram select.
298285        if block is 0-7, selects internal ram instead for read/write
299286        */
r9685r9686
341328         break;
342329      }
343330
344      if (pcw_bank_force & mask)
331      if (state->bank_force & mask)
345332      {
346333         read_bank = data & 0x07;
347334      }
r9685r9686
357344   }
358345
359346   /* if boot is active, page in fake ROM */
360/*  if ((pcw_boot) && (block==0))
347/*  if ((state->boot) && (block==0))
361348    {
362349        unsigned char *FakeROM;
363350
r9685r9686
370357/* from Jacob Nevins docs */
371358static int pcw_get_sys_status(running_machine *machine)
372359{
373   return pcw_interrupt_counter | (input_port_read(machine, "EXTRA") & (0x040 | 0x010)) | (pcw_system_status & 0x20);
360   pcw_state *state = machine->driver_data<pcw_state>();
361   return state->interrupt_counter | (input_port_read(machine, "EXTRA") & (0x040 | 0x010)) | (state->system_status & 0x20);
374362}
375363
376364static READ8_HANDLER(pcw_interrupt_counter_r)
377365{
366   pcw_state *state = space->machine->driver_data<pcw_state>();
378367   int data;
379368
380369   /* from Jacob Nevins docs */
r9685r9686
382371   /* get data */
383372   data = pcw_get_sys_status(space->machine);
384373   /* clear int counter */
385   pcw_interrupt_counter = 0;
374   state->interrupt_counter = 0;
386375   /* check interrupts */
387376   pcw_update_irqs(space->machine);
388377   /* return data */
r9685r9686
393382
394383static WRITE8_HANDLER(pcw_bank_select_w)
395384{
385   pcw_state *state = space->machine->driver_data<pcw_state>();
396386   //LOG(("BANK: %2x %x\n",offset, data));
397   pcw_banks[offset] = data;
387   state->banks[offset] = data;
398388
399389   pcw_update_mem(space->machine, offset, data);
400   //popmessage("RAM Banks: %02x %02x %02x %02x",pcw_banks[0],pcw_banks[1],pcw_banks[2],pcw_banks[3]);
390   //popmessage("RAM Banks: %02x %02x %02x %02x",state->banks[0],state->banks[1],state->banks[2],state->banks[3]);
401391}
402392
403393static WRITE8_HANDLER(pcw_bank_force_selection_w)
404394{
405   pcw_bank_force = data;
395   pcw_state *state = space->machine->driver_data<pcw_state>();
396   state->bank_force = data;
406397
407   pcw_update_mem(space->machine, 0, pcw_banks[0]);
408   pcw_update_mem(space->machine, 1, pcw_banks[1]);
409   pcw_update_mem(space->machine, 2, pcw_banks[2]);
410   pcw_update_mem(space->machine, 3, pcw_banks[3]);
398   pcw_update_mem(space->machine, 0, state->banks[0]);
399   pcw_update_mem(space->machine, 1, state->banks[1]);
400   pcw_update_mem(space->machine, 2, state->banks[2]);
401   pcw_update_mem(space->machine, 3, state->banks[3]);
411402}
412403
413404
414405static WRITE8_HANDLER(pcw_roller_ram_addr_w)
415406{
407   pcw_state *state = space->machine->driver_data<pcw_state>();
416408   /*
417409    Address of roller RAM. b7-5: bank (0-7). b4-1: address / 512. */
418410
419   roller_ram_addr = (((data>>5) & 0x07)<<14) |
411   state->roller_ram_addr = (((data>>5) & 0x07)<<14) |
420412                     ((data & 0x01f)<<9);
421   LOG(("Roller-RAM: Address set to 0x%05x\n",roller_ram_addr));
413   LOG(("Roller-RAM: Address set to 0x%05x\n",state->roller_ram_addr));
422414}
423415
424416static WRITE8_HANDLER(pcw_pointer_table_top_scan_w)
425417{
426   roller_ram_offset = data;
427   LOG(("Roller-RAM: offset set to 0x%05x\n",roller_ram_offset));
418   pcw_state *state = space->machine->driver_data<pcw_state>();
419   state->roller_ram_offset = data;
420   LOG(("Roller-RAM: offset set to 0x%05x\n",state->roller_ram_offset));
428421}
429422
430423static WRITE8_HANDLER(pcw_vdu_video_control_register_w)
431424{
432   pcw_vdu_video_control_register = data;
425   pcw_state *state = space->machine->driver_data<pcw_state>();
426   state->vdu_video_control_register = data;
433427   LOG(("Roller-RAM: control reg set to 0x%02x\n",data));
434428}
435429
436430static WRITE8_HANDLER(pcw_system_control_w)
437431{
432   pcw_state *state = space->machine->driver_data<pcw_state>();
438433   running_device *fdc = space->machine->device("upd765");
439434   running_device *speaker = space->machine->device("beep");
440435   LOG(("SYSTEM CONTROL: %d\n",data));
r9685r9686
444439      /* end bootstrap */
445440      case 0:
446441      {
447         pcw_boot = 0;
448         pcw_update_mem(space->machine, 0, pcw_banks[0]);
442         state->boot = 0;
443         pcw_update_mem(space->machine, 0, state->banks[0]);
449444      }
450445      break;
451446
r9685r9686
460455      /* connect fdc interrupt to nmi */
461456      case 2:
462457      {
463         int fdc_previous_interrupt_code = fdc_interrupt_code;
458         int fdc_previous_interrupt_code = state->fdc_interrupt_code;
464459
465         fdc_interrupt_code = 0;
460         state->fdc_interrupt_code = 0;
466461
467462         /* previously connected to INT? */
468463         if (fdc_previous_interrupt_code == 1)
r9685r9686
479474      /* connect fdc interrupt to interrupt */
480475      case 3:
481476      {
482         int fdc_previous_interrupt_code = fdc_interrupt_code;
477         int fdc_previous_interrupt_code = state->fdc_interrupt_code;
483478
484479         /* connect to INT */
485         fdc_interrupt_code = 1;
480         state->fdc_interrupt_code = 1;
486481
487482         /* previously connected to NMI? */
488483         if (fdc_previous_interrupt_code == 0)
r9685r9686
490485            /* yes */
491486
492487            /* clear nmi interrupt */
493            pcw_nmi_flag = 0;
488            state->nmi_flag = 0;
494489         }
495490
496491         /* re-issue interrupt */
r9685r9686
502497      /* connect fdc interrupt to neither */
503498      case 4:
504499      {
505         int fdc_previous_interrupt_code = fdc_interrupt_code;
500         int fdc_previous_interrupt_code = state->fdc_interrupt_code;
506501
507         fdc_interrupt_code = 2;
502         state->fdc_interrupt_code = 2;
508503
509504         /* previously connected to NMI or INT? */
510505         if ((fdc_previous_interrupt_code == 0) || (fdc_previous_interrupt_code == 1))
r9685r9686
512507            /* yes */
513508
514509            /* Clear NMI */
515            pcw_nmi_flag = 0;
510            state->nmi_flag = 0;
516511         }
517512         pcw_update_irqs(space->machine);
518513
r9685r9686
676671/* TODO: Implement the printer for PCW8256, PCW8512,PCW9256*/
677672static WRITE8_HANDLER(pcw_printer_data_w)
678673{
679   pcw_printer_data = data;
674   pcw_state *state = space->machine->driver_data<pcw_state>();
675   state->printer_data = data;
680676   upi41_master_w(space->machine->device("printer_mcu"),0,data);
681677   logerror("PRN [0xFC]: Sent command %02x\n",data);
682678}
683679
684680static WRITE8_HANDLER(pcw_printer_command_w)
685681{
686   pcw_printer_command = data;
682   pcw_state *state = space->machine->driver_data<pcw_state>();
683   state->printer_command = data;
687684   upi41_master_w(space->machine->device("printer_mcu"),1,data);
688685   logerror("PRN [0xFD]: Sent command %02x\n",data);
689686}
r9685r9686
736733
737734static WRITE8_HANDLER(mcu_printer_p2_w)
738735{
736   pcw_state *state = space->machine->driver_data<pcw_state>();
739737//   logerror("PRN: MCU writing %02x to P2\n",data);
740738   if((data & 0x20) == 0)
741      pcw_printer_headpos = 1;  // move head
739      state->printer_headpos = 1;  // move head
742740   if((data & 0x10) == 0)
743      pcw_printer_headpos = 0;
741      state->printer_headpos = 0;
744742}
745743
746744// Paper sensor?
r9685r9686
752750// Print head location? (0 if at left margin, otherwise 1)
753751static READ8_HANDLER(mcu_printer_t0_r)
754752{
755   return pcw_printer_headpos;
753   pcw_state *state = space->machine->driver_data<pcw_state>();
754   return state->printer_headpos;
756755}
757756
758757/*
r9685r9686
762761 *       bit 1: keyboard serial clock
763762 *       bit 0: keyboard serial data
764763 */
765static void mcu_transmit_serial(UINT8 bit)
764static void mcu_transmit_serial(pcw_state *state, UINT8 bit)
766765{
767   static UINT8 selected;
768   static UINT8 buffer;
769766   int seq;
770767
771768   /* Keyboard data is sent in serial from the MCU through the keyboard port, to the ASIC
772769       Sends a string of 12-bit sequences, first 4 bits are the RAM location (from &3ff0),
773770       then 8 bits for the data to be written there. */
774   seq = mcu_transmit_count % 12;
771   seq = state->mcu_transmit_count % 12;
775772   if(seq < 4)
776773   {
777774      if(bit == 0)
778         selected &= ~(8 >> seq);
775         state->mcu_selected &= ~(8 >> seq);
779776      else
780         selected |= (8 >> seq);
777         state->mcu_selected |= (8 >> seq);
781778   }
782779   else
783780   {
784781      seq -= 4;
785782      if(bit == 0)
786         buffer &= ~(128 >> seq);
783         state->mcu_buffer &= ~(128 >> seq);
787784      else
788         buffer |= (128 >> seq);
785         state->mcu_buffer |= (128 >> seq);
789786   }
790   mcu_transmit_count++;
791   if(mcu_transmit_count >= 12)
787   state->mcu_transmit_count++;
788   if(state->mcu_transmit_count >= 12)
792789   {
793      mcu_keyboard_data[selected] = buffer;
794      mcu_transmit_count = 0;
790      state->mcu_keyboard_data[state->mcu_selected] = state->mcu_buffer;
791      state->mcu_transmit_count = 0;
795792   }
796793}
797794
798795static READ8_HANDLER(mcu_kb_scan_r)
799796{
800   return pcw_kb_scan_row & 0xff;
797   pcw_state *state = space->machine->driver_data<pcw_state>();
798   return state->kb_scan_row & 0xff;
801799}
802800
803801static WRITE8_HANDLER(mcu_kb_scan_w)
804802{
805   pcw_kb_scan_row = (pcw_kb_scan_row & 0xff00) | data;
803   pcw_state *state = space->machine->driver_data<pcw_state>();
804   state->kb_scan_row = (state->kb_scan_row & 0xff00) | data;
806805}
807806
808807static READ8_HANDLER(mcu_kb_scan_high_r)
809808{
810   return (pcw_kb_scan_row & 0xff00) >> 8;
809   pcw_state *state = space->machine->driver_data<pcw_state>();
810   return (state->kb_scan_row & 0xff00) >> 8;
811811}
812812
813813static WRITE8_HANDLER(mcu_kb_scan_high_w)
814814{
815   static UINT8 prev;
816
817   if((prev & 0x02) && !(data & 0x02))  // bit is transmitted on high-to-low clock transition
815   pcw_state *state = space->machine->driver_data<pcw_state>();
816   if((state->mcu_prev & 0x02) && !(data & 0x02))  // bit is transmitted on high-to-low clock transition
818817   {
819      mcu_transmit_serial(data & 0x01);
820      mcu_transmit_reset_seq = 0;
818      mcu_transmit_serial(state, data & 0x01);
819      state->mcu_transmit_reset_seq = 0;
821820   }
822821
823   if((prev & 0x01) != (data & 0x01))  // two high->low transitions on the data pin signals the beginning of a new transfer
822   if((state->mcu_prev & 0x01) != (data & 0x01))  // two high->low transitions on the data pin signals the beginning of a new transfer
824823   {
825      mcu_transmit_reset_seq++;
826      if(mcu_transmit_reset_seq > 3)
827         mcu_transmit_count = 0;
824      state->mcu_transmit_reset_seq++;
825      if(state->mcu_transmit_reset_seq > 3)
826         state->mcu_transmit_count = 0;
828827   }
829828
830   pcw_kb_scan_row = (pcw_kb_scan_row & 0x00ff) | ((data & 0xff) << 8);
831   prev = data;
829   state->kb_scan_row = (state->kb_scan_row & 0x00ff) | ((data & 0xff) << 8);
830   state->mcu_prev = data;
832831}
833832
834833static READ8_HANDLER(mcu_kb_data_r)
835834{
836   UINT16 scan_bits = ((pcw_kb_scan_row & 0xf000) >> 4) | (pcw_kb_scan_row & 0xff);
835   pcw_state *state = space->machine->driver_data<pcw_state>();
836   UINT16 scan_bits = ((state->kb_scan_row & 0xf000) >> 4) | (state->kb_scan_row & 0xff);
837837   int x;
838838
839839   for(x=0;x<12;x++)
r9685r9686
930930
931931static MACHINE_START( pcw )
932932{
933   fdc_interrupt_code = 2;
933   pcw_state *state = machine->driver_data<pcw_state>();
934   state->fdc_interrupt_code = 2;
934935}
935936
936937static MACHINE_RESET( pcw )
937938{
939   pcw_state *state = machine->driver_data<pcw_state>();
938940   UINT8* code = memory_region(machine,"printer_mcu");
939941   int x;
940942   /* ram paging is actually undefined at power-on */
941943
942   pcw_bank_force = 0x00;
944   state->bank_force = 0x00;
943945
944   pcw_banks[0] = 0x80;
945   pcw_banks[1] = 0x81;
946   pcw_banks[2] = 0x82;
947   pcw_banks[3] = 0x83;
946   state->banks[0] = 0x80;
947   state->banks[1] = 0x81;
948   state->banks[2] = 0x82;
949   state->banks[3] = 0x83;
948950
949   pcw_update_mem(machine, 0, pcw_banks[0]);
950   pcw_update_mem(machine, 1, pcw_banks[1]);
951   pcw_update_mem(machine, 2, pcw_banks[2]);
952   pcw_update_mem(machine, 3, pcw_banks[3]);
951   pcw_update_mem(machine, 0, state->banks[0]);
952   pcw_update_mem(machine, 1, state->banks[1]);
953   pcw_update_mem(machine, 2, state->banks[2]);
954   pcw_update_mem(machine, 3, state->banks[3]);
953955
954   pcw_boot = 0;   // System starts up in bootstrap mode, disabled until it's possible to emulate it.
956   state->boot = 0;   // System starts up in bootstrap mode, disabled until it's possible to emulate it.
955957
956958   /* copy boot code into RAM - yes, it's skipping a step */
957959   memset(messram_get_ptr(machine->device("messram")),0x00,messram_get_size(machine->device("messram")));
r9685r9686
961963   /* and hack our way past the MCU side of the boot process */
962964   code[0x01] = 0x40;
963965
964   pcw_printer_status = 0xff;
965   pcw_printer_command = 0xff;
966   pcw_printer_data = 0x00;
967   pcw_printer_headpos = 0x00; // bring printer head to left margin
966   state->printer_status = 0xff;
967   state->printer_command = 0xff;
968   state->printer_data = 0x00;
969   state->printer_headpos = 0x00; // bring printer head to left margin
968970}
969971
970972static DRIVER_INIT(pcw)
971973{
974   pcw_state *state = machine->driver_data<pcw_state>();
972975   cpu_set_input_line_vector(machine->device("maincpu"), 0, 0x0ff);
973976
974977   /* lower 4 bits are interrupt counter */
975   pcw_system_status = 0x000;
976   pcw_system_status &= ~((1<<6) | (1<<5) | (1<<4));
978   state->system_status = 0x000;
979   state->system_status &= ~((1<<6) | (1<<5) | (1<<4));
977980
978   pcw_interrupt_counter = 0;
981   state->interrupt_counter = 0;
979982
980   roller_ram_offset = 0;
983   state->roller_ram_offset = 0;
981984
982985   /* timer interrupt */
983986   timer_pulse(machine, ATTOTIME_IN_HZ(300), NULL, 0, pcw_timer_interrupt);
r9685r9686
11911194};
11921195
11931196/* PCW8256, PCW8512, PCW9256 */
1194static MACHINE_CONFIG_START( pcw, driver_device )
1197static MACHINE_CONFIG_START( pcw, pcw_state )
11951198   /* basic machine hardware */
11961199   MDRV_CPU_ADD("maincpu", Z80, 4000000)       /* clock supplied to chip, but in reality it is 3.4 MHz */
11971200   MDRV_CPU_PROGRAM_MAP(pcw_map)
src/mess/drivers/chaos.c
r9685r9686
99#include "emu.h"
1010#include "cpu/s2650/s2650.h"
1111
12
13class chaos_state : public driver_device
14{
15public:
16   chaos_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(chaos_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x2fff) AM_ROM
r9685r9686
3848    return 0;
3949}
4050
41static MACHINE_CONFIG_START( chaos, driver_device )
51static MACHINE_CONFIG_START( chaos, chaos_state )
4252    /* basic machine hardware */
4353    MDRV_CPU_ADD("maincpu",S2650, XTAL_1MHz)
4454    MDRV_CPU_PROGRAM_MAP(chaos_mem)
src/mess/drivers/sdk85.c
r9685r9686
99#include "emu.h"
1010#include "cpu/i8085/i8085.h"
1111
12
13class sdk85_state : public driver_device
14{
15public:
16   sdk85_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(sdk85_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x0000, 0x07ff) AM_ROM // Monitor rom (A14)
r9685r9686
4050    return 0;
4151}
4252
43static MACHINE_CONFIG_START( sdk85, driver_device )
53static MACHINE_CONFIG_START( sdk85, sdk85_state )
4454    /* basic machine hardware */
4555    MDRV_CPU_ADD("maincpu",I8085A, XTAL_2MHz)
4656    MDRV_CPU_PROGRAM_MAP(sdk85_mem)
src/mess/drivers/rt1715.c
r9685r9686
2222#include "video/i8275.h"
2323
2424
25class rt1715_state : public driver_device
26{
27public:
28   rt1715_state(running_machine &machine, const driver_device_config_base &config)
29      : driver_device(machine, config) { }
30
31   int led1_val;
32   int led2_val;
33};
34
35
2536/***************************************************************************
2637    FLOPPY
2738***************************************************************************/
r9685r9686
3950/* si/so led */
4051static READ8_HANDLER( k7658_led1_r )
4152{
42   static int led1_val = 0;
43   led1_val ^= 1;
44   logerror("%s: k7658_led1_r %02x\n", cpuexec_describe_context(space->machine), led1_val);
53   rt1715_state *state = space->machine->driver_data<rt1715_state>();
54   state->led1_val ^= 1;
55   logerror("%s: k7658_led1_r %02x\n", cpuexec_describe_context(space->machine), state->led1_val);
4556   return 0xff;
4657}
4758
4859/* caps led */
4960static READ8_HANDLER( k7658_led2_r )
5061{
51   static int led2_val = 0;
52   led2_val ^= 1;
53   logerror("%s: k7658_led2_r %02x\n", cpuexec_describe_context(space->machine), led2_val);
62   rt1715_state *state = space->machine->driver_data<rt1715_state>();
63   state->led2_val ^= 1;
64   logerror("%s: k7658_led2_r %02x\n", cpuexec_describe_context(space->machine), state->led2_val);
5465   return 0xff;
5566}
5667
r9685r9686
299310   { NULL }
300311};
301312
302static MACHINE_CONFIG_START( rt1715, driver_device )
313static MACHINE_CONFIG_START( rt1715, rt1715_state )
303314   /* basic machine hardware */
304315   MDRV_CPU_ADD("maincpu", Z80, XTAL_2_4576MHz)
305316   MDRV_CPU_PROGRAM_MAP(rt1715_mem)
src/mess/drivers/ex800.c
r9685r9686
132132#include "ex800.lh"
133133
134134
135class ex800_state : public driver_device
136{
137public:
138   ex800_state(running_machine &machine, const driver_device_config_base &config)
139      : driver_device(machine, config) { }
140
141};
142
143
144
135145#define PA0 (data & 0x01)
136146#define PA1 (data & 0x02)
137147#define PA2 (data & 0x04)
r9685r9686
418428******************************************************************************/
419429
420430
421static MACHINE_CONFIG_START( ex800, driver_device )
431static MACHINE_CONFIG_START( ex800, ex800_state )
422432    /* basic machine hardware */
423433    MDRV_CPU_ADD("maincpu", UPD7810, 12000000)  /* 12 MHz? */
424434    MDRV_CPU_CONFIG(ex800_cpu_config)
src/mess/drivers/rex6000.c
r9685r9686
99#include "emu.h"
1010#include "cpu/z80/z80.h"
1111
12
13class rex6000_state : public driver_device
14{
15public:
16   rex6000_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(rex6000_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0xffff ) AM_ROM
r9685r9686
3646    return 0;
3747}
3848
39static MACHINE_CONFIG_START( rex6000, driver_device )
49static MACHINE_CONFIG_START( rex6000, rex6000_state )
4050    /* basic machine hardware */
4151    MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
4252    MDRV_CPU_PROGRAM_MAP(rex6000_mem)
src/mess/drivers/ipb.c
r9685r9686
99#include "emu.h"
1010#include "cpu/i8085/i8085.h"
1111
12
13class ipb_state : public driver_device
14{
15public:
16   ipb_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(ipb_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x0000, 0xdfff) AM_RAM
r9685r9686
3949    return 0;
4050}
4151
42static MACHINE_CONFIG_START( ipb, driver_device )
52static MACHINE_CONFIG_START( ipb, ipb_state )
4353    /* basic machine hardware */
4454    MDRV_CPU_ADD("maincpu",I8080, XTAL_19_6608MHz / 4)
4555    MDRV_CPU_PROGRAM_MAP(ipb_mem)
src/mess/drivers/d6809.c
r9685r9686
99#include "emu.h"
1010#include "cpu/m6809/m6809.h"
1111
12
13class d6809_state : public driver_device
14{
15public:
16   d6809_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(d6809_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x0000,0xdfff) AM_RAM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( d6809, driver_device )
50static MACHINE_CONFIG_START( d6809, d6809_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",M6809E, XTAL_4MHz)
4353    MDRV_CPU_PROGRAM_MAP(d6809_mem)
src/mess/drivers/mk14.c
r9685r9686
1010#include "cpu/scmp/scmp.h"
1111#include "machine/ins8154.h"
1212#include "mk14.lh"
13
14
15class mk14_state : public driver_device
16{
17public:
18   mk14_state(running_machine &machine, const driver_device_config_base &config)
19      : driver_device(machine, config) { }
20
21};
22
1323/*
1424000-1FF  512 byte SCIOS ROM  Decoded by 0xxx
1525200-3FF  ROM Shadow / Expansion RAM
r9685r9686
127137   DEVCB_NULL
128138};
129139
130static MACHINE_CONFIG_START( mk14, driver_device )
140static MACHINE_CONFIG_START( mk14, mk14_state )
131141    /* basic machine hardware */
132142   // IC1 1SP-8A/600 (8060) SC/MP Microprocessor
133143    MDRV_CPU_ADD("maincpu", INS8060, XTAL_4_433619MHz)
src/mess/drivers/mikrosha.c
r9685r9686
1818#include "formats/rk_cas.h"
1919#include "includes/radio86.h"
2020
21
22class mikrosha_state : public driver_device
23{
24public:
25   mikrosha_state(running_machine &machine, const driver_device_config_base &config)
26      : driver_device(machine, config) { }
27
28};
29
30
2131/* Address maps */
2232static ADDRESS_MAP_START(mikrosha_mem, ADDRESS_SPACE_PROGRAM, 8)
2333    AM_RANGE( 0x0000, 0x0fff ) AM_RAMBANK("bank1") // First bank
r9685r9686
184194   GFXDECODE_ENTRY( "gfx1", 0x0000, mikrosha_charlayout, 0, 1 )
185195GFXDECODE_END
186196
187static MACHINE_CONFIG_START( mikrosha, driver_device )
197static MACHINE_CONFIG_START( mikrosha, mikrosha_state )
188198   /* basic machine hardware */
189199   MDRV_CPU_ADD("maincpu", I8080, XTAL_16MHz / 9)
190200   MDRV_CPU_PROGRAM_MAP(mikrosha_mem)
src/mess/drivers/vt220.c
r9685r9686
1010#include "cpu/mcs51/mcs51.h"
1111#include "devices/messram.h"
1212
13
14class vt220_state : public driver_device
15{
16public:
17   vt220_state(running_machine &machine, const driver_device_config_base &config)
18      : driver_device(machine, config) { }
19
20};
21
22
1323static ADDRESS_MAP_START(vt220_mem, ADDRESS_SPACE_PROGRAM, 8)
1424   AM_RANGE(0x0000, 0x7fff) AM_ROM
1525ADDRESS_MAP_END
r9685r9686
3646}
3747
3848
39static MACHINE_CONFIG_START( vt220, driver_device )
49static MACHINE_CONFIG_START( vt220, vt220_state )
4050    /* basic machine hardware */
4151    MDRV_CPU_ADD("maincpu", I8051, XTAL_16MHz)
4252    MDRV_CPU_PROGRAM_MAP(vt220_mem)
src/mess/drivers/ti990_10.c
r9685r9686
7676#include "machine/990_tap.h"
7777#include "video/911_vdt.h"
7878
79
80class ti990_10_state : public driver_device
81{
82public:
83   ti990_10_state(running_machine &machine, const driver_device_config_base &config)
84      : driver_device(machine, config) { }
85
86};
87
88
7989static MACHINE_START( ti990_10 )
8090{
8191   MACHINE_START_CALL( ti990_hdc );
r9685r9686
194204   ti990_set_int9
195205};
196206
197static MACHINE_CONFIG_START( ti990_10, driver_device )
207static MACHINE_CONFIG_START( ti990_10, ti990_10_state )
198208   /* basic machine hardware */
199209   /* TI990/10 CPU @ 4.0(???) MHz */
200210   MDRV_CPU_ADD("maincpu", TI990_10, 4000000)
src/mess/drivers/mk90.c
r9685r9686
99#include "emu.h"
1010#include "cpu/t11/t11.h"
1111
12
13class mk90_state : public driver_device
14{
15public:
16   mk90_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(mk90_mem, ADDRESS_SPACE_PROGRAM, 16)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x3fff ) AM_RAM // RAM
r9685r9686
3949   1 << 13         /* start from 8000 */
4050};
4151
42static MACHINE_CONFIG_START( mk90, driver_device )
52static MACHINE_CONFIG_START( mk90, mk90_state )
4353    /* basic machine hardware */
4454    MDRV_CPU_ADD("maincpu",T11, XTAL_4MHz)
4555    MDRV_CPU_CONFIG(t11_data)
src/mess/drivers/uknc.c
r9685r9686
99#include "emu.h"
1010#include "cpu/t11/t11.h"
1111
12
13class uknc_state : public driver_device
14{
15public:
16   uknc_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(uknc_mem, ADDRESS_SPACE_PROGRAM, 16)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x7fff ) AM_RAM  // RAM
r9685r9686
4555};
4656
4757
48static MACHINE_CONFIG_START( uknc, driver_device )
58static MACHINE_CONFIG_START( uknc, uknc_state )
4959    /* basic machine hardware */
5060    MDRV_CPU_ADD("maincpu", T11, 8000000)
5161   MDRV_CPU_CONFIG(t11_data)
src/mess/drivers/qtsbc.c
r9685r9686
1212#include "cpu/z80/z80.h"
1313#include "machine/terminal.h"
1414
15static UINT8 *qtsbc_ram;
16static UINT8 term_data;
1715
16class qtsbc_state : public driver_device
17{
18public:
19   qtsbc_state(running_machine &machine, const driver_device_config_base &config)
20      : driver_device(machine, config) { }
21
22   UINT8 *ram;
23   UINT8 term_data;
24};
25
26
27
1828static WRITE8_HANDLER( qtsbc_06_w )
1929{
2030   running_device *terminal = space->machine->device("terminal");
r9685r9686
2434
2535static READ8_HANDLER( qtsbc_06_r )
2636{
27   UINT8 ret = term_data;
28   term_data = 0;
37   qtsbc_state *state = space->machine->driver_data<qtsbc_state>();
38   UINT8 ret = state->term_data;
39   state->term_data = 0;
2940   return ret;
3041}
3142
r9685r9686
3647
3748static ADDRESS_MAP_START(qtsbc_mem, ADDRESS_SPACE_PROGRAM, 8)
3849   ADDRESS_MAP_UNMAP_HIGH
39   AM_RANGE( 0x0000, 0xffff ) AM_RAM AM_BASE(&qtsbc_ram) AM_REGION("maincpu",0)
50   AM_RANGE( 0x0000, 0xffff ) AM_RAM AM_BASE_MEMBER(qtsbc_state, ram) AM_REGION("maincpu",0)
4051ADDRESS_MAP_END
4152
4253static ADDRESS_MAP_START( qtsbc_io , ADDRESS_SPACE_IO, 8)
r9685r9686
5465
5566static MACHINE_RESET(qtsbc)
5667{
68   qtsbc_state *state = machine->driver_data<qtsbc_state>();
5769   UINT8* bios = memory_region(machine, "maincpu")+0x10000;
58   memcpy(qtsbc_ram,bios, 0x800);
70   memcpy(state->ram,bios, 0x800);
5971}
6072
6173static WRITE8_DEVICE_HANDLER( qtsbc_kbd_put )
6274{
63   term_data = data;
75   qtsbc_state *state = device->machine->driver_data<qtsbc_state>();
76   state->term_data = data;
6477}
6578
6679static GENERIC_TERMINAL_INTERFACE( qtsbc_terminal_intf )
r9685r9686
6881   DEVCB_HANDLER(qtsbc_kbd_put)
6982};
7083
71static MACHINE_CONFIG_START( qtsbc, driver_device )
84static MACHINE_CONFIG_START( qtsbc, qtsbc_state )
7285   /* basic machine hardware */
7386   MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz) // Mostek MK3880
7487   MDRV_CPU_PROGRAM_MAP(qtsbc_mem)
src/mess/drivers/mits680b.c
r9685r9686
1111#include "machine/6551.h"
1212#include "machine/terminal.h"
1313
14
15class mits680b_state : public driver_device
16{
17public:
18   mits680b_state(running_machine &machine, const driver_device_config_base &config)
19      : driver_device(machine, config) { }
20
21};
22
23
1424static ADDRESS_MAP_START(mits680b_mem, ADDRESS_SPACE_PROGRAM, 8)
1525   ADDRESS_MAP_UNMAP_HIGH
1626   AM_RANGE( 0x0000, 0x03ff ) AM_RAM // 1024 bytes RAM
r9685r9686
3848   DEVCB_HANDLER(mits680b_kbd_put)
3949};
4050
41static MACHINE_CONFIG_START( mits680b, driver_device )
51static MACHINE_CONFIG_START( mits680b, mits680b_state )
4252    /* basic machine hardware */
4353    MDRV_CPU_ADD("maincpu",M6800, XTAL_1MHz / 2)
4454    MDRV_CPU_PROGRAM_MAP(mits680b_mem)
src/mess/drivers/votrpss.c
r9685r9686
6161#include "cpu/z80/z80.h"
6262#include "votrpss.lh"
6363
64
65class votrpss_state : public driver_device
66{
67public:
68   votrpss_state(running_machine &machine, const driver_device_config_base &config)
69      : driver_device(machine, config) { }
70
71};
72
73
6474/* Components */
6575//#include "sound/ay8910.h"
6676//#include "sound/votrax.h"
r9685r9686
132142 Machine Drivers
133143******************************************************************************/
134144
135static MACHINE_CONFIG_START( votrpss, driver_device )
145static MACHINE_CONFIG_START( votrpss, votrpss_state )
136146    /* basic machine hardware */
137147    MDRV_CPU_ADD("maincpu", Z80, XTAL_8MHz/2)  /* 4.000 MHz, verified */
138148    MDRV_CPU_PROGRAM_MAP(z80_mem)
src/mess/drivers/p112.c
r9685r9686
99#include "emu.h"
1010#include "cpu/z180/z180.h"
1111
12
13class p112_state : public driver_device
14{
15public:
16   p112_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(p112_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x00000, 0x07fff) AM_ROM
r9685r9686
3848    return 0;
3949}
4050
41static MACHINE_CONFIG_START( p112, driver_device )
51static MACHINE_CONFIG_START( p112, p112_state )
4252    /* basic machine hardware */
4353    MDRV_CPU_ADD("maincpu",Z180, XTAL_16MHz)
4454    MDRV_CPU_PROGRAM_MAP(p112_mem)
src/mess/drivers/osborne1.c
r9685r9686
238238   GFXDECODE_ENTRY( "gfx1", 0x0000, osborne1_charlayout, 0, 1 )
239239GFXDECODE_END
240240
241static MACHINE_CONFIG_START( osborne1, driver_device )
241static MACHINE_CONFIG_START( osborne1, osborne1_state )
242242   MDRV_CPU_ADD( "maincpu", Z80, MAIN_CLOCK/4 )
243243   MDRV_CPU_PROGRAM_MAP( osborne1_mem)
244244   MDRV_CPU_IO_MAP( osborne1_io)
src/mess/drivers/pda600.c
r9685r9686
5656#include "emu.h"
5757#include "cpu/z180/z180.h"
5858
59
60class pda600_state : public driver_device
61{
62public:
63   pda600_state(running_machine &machine, const driver_device_config_base &config)
64      : driver_device(machine, config) { }
65
66};
67
68
5969static ADDRESS_MAP_START(pda600_mem, ADDRESS_SPACE_PROGRAM, 8)
6070   ADDRESS_MAP_UNMAP_HIGH
6171   AM_RANGE(0x00000, 0x1ffff) AM_ROM
r9685r9686
92102    return 0;
93103}
94104
95static MACHINE_CONFIG_START( pda600, driver_device )
105static MACHINE_CONFIG_START( pda600, pda600_state )
96106    /* basic machine hardware */
97107    MDRV_CPU_ADD("maincpu",Z180, XTAL_14_31818MHz)
98108    MDRV_CPU_PROGRAM_MAP(pda600_mem)
src/mess/drivers/sdk86.c
r9685r9686
1515#include "emu.h"
1616#include "cpu/i86/i86.h"
1717
18
19class sdk86_state : public driver_device
20{
21public:
22   sdk86_state(running_machine &machine, const driver_device_config_base &config)
23      : driver_device(machine, config) { }
24
25};
26
27
1828static ADDRESS_MAP_START(sdk86_mem, ADDRESS_SPACE_PROGRAM, 16)
1929   AM_RANGE(0x00000, 0x03fff) AM_RAM
2030   AM_RANGE(0xfe000, 0xfffff) AM_ROM
r9685r9686
4252    return 0;
4353}
4454
45static MACHINE_CONFIG_START( sdk86, driver_device )
55static MACHINE_CONFIG_START( sdk86, sdk86_state )
4656    /* basic machine hardware */
4757    MDRV_CPU_ADD("maincpu",I8086, XTAL_14_7456MHz/3) /* divided down by i8284 clock generator; jumper selection allows it to be slowed to 2.5MHz, hence changing divider from 3 to 6 */
4858    MDRV_CPU_PROGRAM_MAP(sdk86_mem)
src/mess/drivers/systec.c
r9685r9686
3030#include "emu.h"
3131#include "cpu/z80/z80.h"
3232
33
34class systec_state : public driver_device
35{
36public:
37   systec_state(running_machine &machine, const driver_device_config_base &config)
38      : driver_device(machine, config) { }
39
40};
41
42
3343static ADDRESS_MAP_START(systec_mem, ADDRESS_SPACE_PROGRAM, 8)
3444   ADDRESS_MAP_UNMAP_HIGH
3545   AM_RANGE(0x0000, 0x1fff) AM_ROM
r9685r9686
5767   return 0;
5868}
5969
60static MACHINE_CONFIG_START( systec, driver_device )
70static MACHINE_CONFIG_START( systec, systec_state )
6171    /* basic machine hardware */
6272    MDRV_CPU_ADD("maincpu", Z80, XTAL_16MHz / 4)
6373    MDRV_CPU_PROGRAM_MAP(systec_mem)
src/mess/drivers/ipc.c
r9685r9686
99#include "emu.h"
1010#include "cpu/i8085/i8085.h"
1111
12
13class ipc_state : public driver_device
14{
15public:
16   ipc_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(ipc_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x0000, 0xdfff) AM_RAM
r9685r9686
3848    return 0;
3949}
4050
41static MACHINE_CONFIG_START( ipc, driver_device )
51static MACHINE_CONFIG_START( ipc, ipc_state )
4252    /* basic machine hardware */
4353    MDRV_CPU_ADD("maincpu",I8085A, XTAL_19_6608MHz / 4)
4454    MDRV_CPU_PROGRAM_MAP(ipc_mem)
src/mess/drivers/atm.c
r9685r9686
99#include "machine/beta.h"
1010#include "devices/messram.h"
1111
12
13class atm_state : public driver_device
14{
15public:
16   atm_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222DIRECT_UPDATE_HANDLER( atm_direct )
1323{
1424   spectrum_state *state = machine->driver_data<spectrum_state>();
src/mess/drivers/abc1600.c
r9685r9686
33#include "machine/abc99.h"
44#include "devices/messram.h"
55
6
7class abc1600_state : public driver_device
8{
9public:
10   abc1600_state(running_machine &machine, const driver_device_config_base &config)
11      : driver_device(machine, config) { }
12
13};
14
15
616#define M68008_TAG "m68008"
717
818static ADDRESS_MAP_START( abc1600_mem, ADDRESS_SPACE_PROGRAM, 8 )
r9685r9686
1626   return 0;
1727}
1828
19static MACHINE_CONFIG_START( abc1600, driver_device )
29static MACHINE_CONFIG_START( abc1600, abc1600_state )
2030   /* basic machine hardware */
2131   MDRV_CPU_ADD(M68008_TAG, M68008, 8000000)
2232   MDRV_CPU_PROGRAM_MAP(abc1600_mem)
src/mess/drivers/x07.c
r9685r9686
6868   emu_timer *beep_clear;
6969
7070   /* LCD */
71   UINT8 cursor_blink;
7172   UINT8 lcd_on;
7273   UINT8 lcd_map[32][120];
7374   UINT8 scroll_min;
r9685r9686
856857static VIDEO_UPDATE( x07 )
857858{
858859   t6834_state *state = screen->machine->driver_data<t6834_state>();
859   static UINT8 cursor_blink = 0;
860860
861   cursor_blink++;
861   state->cursor_blink++;
862862
863863   if (state->lcd_on)
864864      for(int y = 0; y < 4; y++)
r9685r9686
867867         for(int x = 0; x < 20; x++)
868868         {
869869            int px = x * 6;
870            if(state->cur_on && (cursor_blink & 0x20) && state->cur_x == x && state->cur_y == y)
870            if(state->cur_on && (state->cursor_blink & 0x20) && state->cur_x == x && state->cur_y == y)
871871            {
872872               for(int l = 0; l < 8; l++)
873873               {
src/mess/drivers/amico2k.c
r9685r9686
2222#include "amico2k.lh"
2323
2424
25class amico2k_state : public driver_device
26{
27public:
28   amico2k_state(running_machine &machine, const driver_device_config_base &config)
29      : driver_device(machine, config) { }
30
31};
32
33
34
2535static READ8_DEVICE_HANDLER( amico2k_i8255a_r )
2636{
2737   return 0xff;
r9685r9686
5969   DEVCB_NULL                     // Port C write
6070};
6171
62static MACHINE_CONFIG_START( amico2k, driver_device )
72static MACHINE_CONFIG_START( amico2k, amico2k_state )
6373   /* basic machine hardware */
6474   MDRV_CPU_ADD("maincpu", M6502, 1000000)   /* 1MHz */
6575   MDRV_CPU_PROGRAM_MAP(amico2k_mem)
src/mess/drivers/a7150.c
r9685r9686
1111#include "emu.h"
1212#include "cpu/i86/i86.h"
1313
14
15class a7150_state : public driver_device
16{
17public:
18   a7150_state(running_machine &machine, const driver_device_config_base &config)
19      : driver_device(machine, config) { }
20
21};
22
23
1424static ADDRESS_MAP_START(a7150_mem, ADDRESS_SPACE_PROGRAM, 16)
1525   ADDRESS_MAP_UNMAP_HIGH
1626   AM_RANGE(0x00000,0xeffff) AM_RAM
r9685r9686
3545   return 0;
3646}
3747
38static MACHINE_CONFIG_START( a7150, driver_device )
48static MACHINE_CONFIG_START( a7150, a7150_state )
3949   /* basic machine hardware */
4050   MDRV_CPU_ADD("maincpu", I8086, 4915000)
4151   MDRV_CPU_PROGRAM_MAP(a7150_mem)
src/mess/drivers/indiana.c
r9685r9686
99#include "emu.h"
1010#include "cpu/m68000/m68000.h"
1111
12
13class indiana_state : public driver_device
14{
15public:
16   indiana_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(indiana_mem, ADDRESS_SPACE_PROGRAM, 32)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x00000000, 0x0000ffff) AM_MIRROR(0x7f800000) AM_ROM AM_REGION("user1",0) // 64Kb of EPROM
r9685r9686
4050    return 0;
4151}
4252
43static MACHINE_CONFIG_START( indiana, driver_device )
53static MACHINE_CONFIG_START( indiana, indiana_state )
4454    /* basic machine hardware */
4555    MDRV_CPU_ADD("maincpu",M68030, XTAL_16MHz)
4656    MDRV_CPU_PROGRAM_MAP(indiana_mem)
src/mess/drivers/esq1.c
r9685r9686
5757#include "sound/es5503.h"
5858#include "machine/68681.h"
5959
60
61class esq1_state : public driver_device
62{
63public:
64   esq1_state(running_machine &machine, const driver_device_config_base &config)
65      : driver_device(machine, config) { }
66
67};
68
69
6070static void esq1_doc_irq(running_device *device, int state)
6171{
6272}
r9685r9686
149159   1000000, 1000000, // IP5, IP6
150160};
151161
152static MACHINE_CONFIG_START( esq1, driver_device )
162static MACHINE_CONFIG_START( esq1, esq1_state )
153163   MDRV_CPU_ADD("maincpu", M6809E, 4000000)   // how fast is it?
154164   MDRV_CPU_PROGRAM_MAP(esq1_map)
155165
src/mess/drivers/vt320.c
r9685r9686
99#include "emu.h"
1010#include "cpu/mcs51/mcs51.h"
1111#include "devices/messram.h"
12
13
14class vt320_state : public driver_device
15{
16public:
17   vt320_state(running_machine &machine, const driver_device_config_base &config)
18      : driver_device(machine, config) { }
19
20};
21
1222/*
1323
1424Partlist :
r9685r9686
6272}
6373
6474
65static MACHINE_CONFIG_START( vt320, driver_device )
75static MACHINE_CONFIG_START( vt320, vt320_state )
6676    /* basic machine hardware */
6777    MDRV_CPU_ADD("maincpu", I8051, XTAL_16MHz)
6878    MDRV_CPU_PROGRAM_MAP(vt320_mem)
src/mess/drivers/votrtnt.c
r9685r9686
1818#include "sound/votrax.h"
1919#include "machine/6850acia.h"
2020
21
22class votrtnt_state : public driver_device
23{
24public:
25   votrtnt_state(running_machine &machine, const driver_device_config_base &config)
26      : driver_device(machine, config) { }
27
28};
29
30
2131/* Devices */
2232
2333
r9685r9686
5868 Machine Drivers
5969******************************************************************************/
6070
61static MACHINE_CONFIG_START( votrtnt, driver_device )
71static MACHINE_CONFIG_START( votrtnt, votrtnt_state )
6272    /* basic machine hardware */
6373    MDRV_CPU_ADD("maincpu", M6802, XTAL_2_4576MHz)  /* 2.4576MHz XTAL, verified; divided by 4 inside the m6802*/
6474    MDRV_CPU_PROGRAM_MAP(6802_mem)
src/mess/drivers/dms5000.c
r9685r9686
99#include "emu.h"
1010#include "cpu/i86/i86.h"
1111
12
13class dms5000_state : public driver_device
14{
15public:
16   dms5000_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(dms5000_mem, ADDRESS_SPACE_PROGRAM, 16)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x00000, 0x1ffff) AM_RAM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( dms5000, driver_device )
50static MACHINE_CONFIG_START( dms5000, dms5000_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",I8086, XTAL_9_8304MHz)
4353    MDRV_CPU_PROGRAM_MAP(dms5000_mem)
src/mess/drivers/a5105.c
r9685r9686
1111#include "emu.h"
1212#include "cpu/z80/z80.h"
1313
14
15class a5105_state : public driver_device
16{
17public:
18   a5105_state(running_machine &machine, const driver_device_config_base &config)
19      : driver_device(machine, config) { }
20
21};
22
23
1424static ADDRESS_MAP_START(a5105_mem, ADDRESS_SPACE_PROGRAM, 8)
1525   ADDRESS_MAP_UNMAP_HIGH
1626ADDRESS_MAP_END
r9685r9686
3747   return 0;
3848}
3949
40static MACHINE_CONFIG_START( a5105, driver_device )
50static MACHINE_CONFIG_START( a5105, a5105_state )
4151   /* basic machine hardware */
4252   MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
4353   MDRV_CPU_PROGRAM_MAP(a5105_mem)
src/mess/drivers/dms86.c
r9685r9686
99#include "emu.h"
1010#include "cpu/i86/i86.h"
1111
12
13class dms86_state : public driver_device
14{
15public:
16   dms86_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(dms86_mem, ADDRESS_SPACE_PROGRAM, 16)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x00000, 0x1ffff) AM_RAM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( dms86, driver_device )
50static MACHINE_CONFIG_START( dms86, dms86_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",I8086, XTAL_9_8304MHz)
4353    MDRV_CPU_PROGRAM_MAP(dms86_mem)
src/mess/drivers/p8k.c
r9685r9686
2929#include "sound/beep.h"
3030
3131
32class p8k_state : public driver_device
33{
34public:
35   p8k_state(running_machine &machine, const driver_device_config_base &config)
36      : driver_device(machine, config) { }
37
38};
39
40
41
3242static ADDRESS_MAP_START(p8k_memmap, ADDRESS_SPACE_PROGRAM, 8)
3343   AM_RANGE(0x0000, 0x1fff) AM_ROM
3444   AM_RANGE(0x2000, 0xffff) AM_RAM
r9685r9686
489499
490500****************************************************************************/
491501
492static MACHINE_CONFIG_START( p8k, driver_device )
502static MACHINE_CONFIG_START( p8k, p8k_state )
493503   /* basic machine hardware */
494504   MDRV_CPU_ADD("maincpu", Z80, XTAL_4MHz )
495505   MDRV_CPU_CONFIG(p8k_daisy_chain)
r9685r9686
531541   MDRV_VIDEO_UPDATE(p8k)
532542MACHINE_CONFIG_END
533543
534static MACHINE_CONFIG_START( p8k_16, driver_device )
544static MACHINE_CONFIG_START( p8k_16, p8k_state )
535545   /* basic machine hardware */
536546   MDRV_CPU_ADD("maincpu", Z8001, XTAL_4MHz )   // actually z8001, appropriate changes pending
537547   MDRV_CPU_CONFIG(p8k_16_daisy_chain)
src/mess/drivers/hp16500.c
r9685r9686
2121#include "cpu/m68000/m68000.h"
2222#include "video/generic.h"
2323
24
25class hp16500_state : public driver_device
26{
27public:
28   hp16500_state(running_machine &machine, const driver_device_config_base &config)
29      : driver_device(machine, config) { }
30
31};
32
33
2434static ADDRESS_MAP_START(hp16500_map, ADDRESS_SPACE_PROGRAM, 32)
2535   AM_RANGE(0x00000000, 0x0001ffff) AM_ROM AM_REGION("bios", 0)
2636   AM_RANGE(0x00600000, 0x0063ffff) AM_RAM
r9685r9686
3646   return 0;
3747}
3848
39static MACHINE_CONFIG_START( hp16500, driver_device )
49static MACHINE_CONFIG_START( hp16500, hp16500_state )
4050   /* basic machine hardware */
4151   MDRV_CPU_ADD("maincpu", M68EC030, 25000000)
4252   MDRV_CPU_PROGRAM_MAP(hp16500_map)
src/mess/drivers/ac1.c
r9685r9686
108108INPUT_PORTS_END
109109
110110/* Machine driver */
111static MACHINE_CONFIG_START( ac1, driver_device )
111static MACHINE_CONFIG_START( ac1, ac1_state )
112112   /* basic machine hardware */
113113   MDRV_CPU_ADD("maincpu", Z80, XTAL_8MHz / 4)
114114   MDRV_CPU_PROGRAM_MAP(ac1_mem)
src/mess/drivers/tim011.c
r9685r9686
99#include "emu.h"
1010#include "cpu/z180/z180.h"
1111
12
13class tim011_state : public driver_device
14{
15public:
16   tim011_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(tim011_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x00000, 0x01fff) AM_ROM
r9685r9686
3949    return 0;
4050}
4151
42static MACHINE_CONFIG_START( tim011,driver_device )
52static MACHINE_CONFIG_START( tim011,tim011_state )
4353    /* basic machine hardware */
4454    MDRV_CPU_ADD("maincpu",Z180, XTAL_12_288MHz / 2)
4555    MDRV_CPU_PROGRAM_MAP(tim011_mem)
src/mess/drivers/et3400.c
r9685r9686
1515#include "et3400.lh"
1616
1717
18class et3400_state : public driver_device
19{
20public:
21   et3400_state(running_machine &machine, const driver_device_config_base &config)
22      : driver_device(machine, config) { }
23
24};
25
26
27
1828static READ8_HANDLER( et3400_keypad_r )
1929{
2030   UINT8 data = 0xff;
r9685r9686
8595INPUT_PORTS_END
8696
8797
88static MACHINE_CONFIG_START( et3400, driver_device )
98static MACHINE_CONFIG_START( et3400, et3400_state )
8999   /* basic machine hardware */
90100   MDRV_CPU_ADD("maincpu", M6800, XTAL_4MHz / 8 )
91101   MDRV_CPU_PROGRAM_MAP(et3400_mem)
src/mess/drivers/ti990_4.c
r9685r9686
4646#endif
4747#include "devices/flopdrv.h"
4848
49
50class ti990_4_state : public driver_device
51{
52public:
53   ti990_4_state(running_machine &machine, const driver_device_config_base &config)
54      : driver_device(machine, config) { }
55
56};
57
58
4959static MACHINE_RESET(ti990_4)
5060{
5161   ti990_hold_load(machine);
r9685r9686
217227   NULL
218228};
219229
220static MACHINE_CONFIG_START( ti990_4, driver_device )
230static MACHINE_CONFIG_START( ti990_4, ti990_4_state )
221231   /* basic machine hardware */
222232   /* TMS9900 CPU @ 3.0(???) MHz */
223233   MDRV_CPU_ADD("maincpu", TMS9900, 3000000)
src/mess/drivers/next.c
r9685r9686
99#include "emu.h"
1010#include "cpu/m68000/m68000.h"
1111
12
13class next_state : public driver_device
14{
15public:
16   next_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(next_mem, ADDRESS_SPACE_PROGRAM, 32)
1323   AM_RANGE(0x00000000, 0x0001ffff) AM_ROM AM_REGION("user1", 0)
1424   AM_RANGE(0x01000000, 0x0101ffff) AM_ROM AM_REGION("user1", 0)
r9685r9686
3444    return 0;
3545}
3646
37static MACHINE_CONFIG_START( next, driver_device )
47static MACHINE_CONFIG_START( next, next_state )
3848    /* basic machine hardware */
3949    MDRV_CPU_ADD("maincpu",M68030, XTAL_25MHz)
4050    MDRV_CPU_PROGRAM_MAP(next_mem)
src/mess/drivers/vt240.c
r9685r9686
1414#include "cpu/t11/t11.h"
1515#include "devices/messram.h"
1616
17
18class vt240_state : public driver_device
19{
20public:
21   vt240_state(running_machine &machine, const driver_device_config_base &config)
22      : driver_device(machine, config) { }
23
24};
25
26
1727static ADDRESS_MAP_START(vt240_mem, ADDRESS_SPACE_PROGRAM, 8)
1828   ADDRESS_MAP_UNMAP_HIGH
1929   AM_RANGE(0x0000, 0x7fff) AM_ROM
r9685r9686
4252   return 0;
4353}
4454
45static MACHINE_CONFIG_START( vt240, driver_device )
55static MACHINE_CONFIG_START( vt240, vt240_state )
4656   /* basic machine hardware */
4757   MDRV_CPU_ADD("maincpu", I8085A, XTAL_16MHz / 4)
4858   MDRV_CPU_PROGRAM_MAP(vt240_mem)
src/mess/drivers/hx20.c
r9685r9686
99#include "emu.h"
1010#include "cpu/m6800/m6800.h"
1111
12
13class hx20_state : public driver_device
14{
15public:
16   hx20_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(ehx20_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   AM_RANGE(0x0000, 0x7fff) AM_RAM // I/O
1424   AM_RANGE(0x8000, 0xffff) AM_ROM
r9685r9686
7888   GFXDECODE_ENTRY( "maincpu", 0xfe20, hx20_3_charlayout, 0, 1 )
7989GFXDECODE_END
8090
81static MACHINE_CONFIG_START( ehx20, driver_device )
91static MACHINE_CONFIG_START( ehx20, hx20_state )
8292    /* basic machine hardware */
8393    MDRV_CPU_ADD("maincpu",HD63701, 614000) // HD6301
8494    MDRV_CPU_PROGRAM_MAP(ehx20_mem)
src/mess/drivers/prof180x.c
r9685r9686
99#include "emu.h"
1010#include "cpu/z80/z80.h"
1111
12
13class prof180x_state : public driver_device
14{
15public:
16   prof180x_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(prof180x_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x1fff ) AM_ROM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( prof180x, driver_device )
50static MACHINE_CONFIG_START( prof180x, prof180x_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz) // HD64180
4353    MDRV_CPU_PROGRAM_MAP(prof180x_mem)
src/mess/drivers/rvoice.c
r9685r9686
1717/* Defines */
1818
1919/* Components */
20/*static UINT8 *main_ram; */
2120
22static struct
21typedef struct
2322{
24UINT8 data[8];
25UINT8 P1DDR;
26UINT8 P2DDR;
27UINT8 PORT1;
28UINT8 PORT2;
29UINT8 P3DDR;
30UINT8 P4DDR;
31UINT8 PORT3;
32UINT8 PORT4;
33UINT8 TCSR1;
34UINT8 FRCH;
35UINT8 FRCL;
36UINT8 OCR1H;
37UINT8 OCR1L;
38UINT8 ICRH;
39UINT8 ICRL;
40UINT8 TCSR2;
41UINT8 RMCR;
42UINT8 TRCSR1;
43UINT8 RDR;
44UINT8 TDR;
45UINT8 RP5CR;
46UINT8 PORT5;
47UINT8 P6DDR;
48UINT8 PORT6;
49UINT8 PORT7;
50UINT8 OCR2H;
51UINT8 OCR2L;
52UINT8 TCSR3;
53UINT8 TCONR;
54UINT8 T2CNT;
55UINT8 TRCSR2;
56UINT8 TSTREG;
57UINT8 P5DDR;
58UINT8 P6CSR;
59} hd63701y0={ {0}};
23   UINT8 data[8];
24   UINT8 P1DDR;
25   UINT8 P2DDR;
26   UINT8 PORT1;
27   UINT8 PORT2;
28   UINT8 P3DDR;
29   UINT8 P4DDR;
30   UINT8 PORT3;
31   UINT8 PORT4;
32   UINT8 TCSR1;
33   UINT8 FRCH;
34   UINT8 FRCL;
35   UINT8 OCR1H;
36   UINT8 OCR1L;
37   UINT8 ICRH;
38   UINT8 ICRL;
39   UINT8 TCSR2;
40   UINT8 RMCR;
41   UINT8 TRCSR1;
42   UINT8 RDR;
43   UINT8 TDR;
44   UINT8 RP5CR;
45   UINT8 PORT5;
46   UINT8 P6DDR;
47   UINT8 PORT6;
48   UINT8 PORT7;
49   UINT8 OCR2H;
50   UINT8 OCR2L;
51   UINT8 TCSR3;
52   UINT8 TCONR;
53   UINT8 T2CNT;
54   UINT8 TRCSR2;
55   UINT8 TSTREG;
56   UINT8 P5DDR;
57   UINT8 P6CSR;
58} hd63701y0_t;
6059
61static struct
60typedef struct
6261{
63UINT8 data[8];
64UINT8 port1;
65UINT8 port2;
66UINT8 port3;
67UINT8 port4;
68UINT8 port5;
69UINT8 port6;
70UINT8 port7;
71} rvoicepc={ {0}};
62   UINT8 data[8];
63   UINT8 port1;
64   UINT8 port2;
65   UINT8 port3;
66   UINT8 port4;
67   UINT8 port5;
68   UINT8 port6;
69   UINT8 port7;
70} rvoicepc_t;
71
72class rvoice_state : public driver_device
73{
74public:
75   rvoice_state(running_machine &machine, const driver_device_config_base &config)
76      : driver_device(machine, config) { }
77
78   hd63701y0_t hd63701y0;
79   rvoicepc_t rvoicepc;
80};
81
82
7283/* Devices */
7384
7485static DRIVER_INIT( rvoicepc )
r9685r9686
7788
7889static MACHINE_RESET( rvoicepc )
7990{
80/* following is from datasheet at http://datasheets.chipdb.org/Hitachi/63701/HD63701Y0.pdf */
81hd63701y0.P1DDR = 0xFE; // port 1 ddr, W
82hd63701y0.P2DDR = 0x00; // port 2 ddr, W
83hd63701y0.PORT1 = 0x00; // port 1, R/W
84hd63701y0.PORT2 = 0x00; // port 2, R/W
85hd63701y0.P3DDR = 0xFE; // port 3 ddr, W
86hd63701y0.P4DDR = 0x00; // port 4 ddr, W
87hd63701y0.PORT3 = 0x00; // port 3, R/W
88hd63701y0.PORT4 = 0x00; // port 4, R/W
89hd63701y0.TCSR1 = 0x00; // timer control/status, R/W
90hd63701y0.FRCH = 0x00;
91hd63701y0.FRCL = 0x00;
92hd63701y0.OCR1H = 0xFF;
93hd63701y0.OCR1L = 0xFF;
94hd63701y0.ICRH = 0x00;
95hd63701y0.ICRL = 0x00;
96hd63701y0.TCSR2 = 0x10;
97hd63701y0.RMCR = 0xC0;
98hd63701y0.TRCSR1 = 0x20;
99hd63701y0.RDR = 0x00; // Recieve Data Reg, R
100hd63701y0.TDR = 0x00; // Transmit Data Reg, W
101hd63701y0.RP5CR = 0x78; // or 0xF8; Ram/Port5 Control Reg, R/W
102hd63701y0.PORT5 = 0x00; // port 5, R/W
103hd63701y0.P6DDR = 0x00; // port 6 ddr, W
104hd63701y0.PORT6 = 0x00; // port 6, R/W
105hd63701y0.PORT7 = 0x00; // port 7, R/W
106hd63701y0.OCR2H = 0xFF;
107hd63701y0.OCR2L = 0xFF;
108hd63701y0.TCSR3 = 0x20;
109hd63701y0.TCONR = 0xFF;
110hd63701y0.T2CNT = 0x00;
111hd63701y0.TRCSR2 = 0x28;
112hd63701y0.TSTREG = 0x00;
113hd63701y0.P5DDR = 0x00; // port 5 ddr, W
114hd63701y0.P6CSR = 0x00;
91   rvoice_state *state = machine->driver_data<rvoice_state>();
92   /* following is from datasheet at http://datasheets.chipdb.org/Hitachi/63701/HD63701Y0.pdf */
93   state->hd63701y0.P1DDR = 0xFE; // port 1 ddr, W
94   state->hd63701y0.P2DDR = 0x00; // port 2 ddr, W
95   state->hd63701y0.PORT1 = 0x00; // port 1, R/W
96   state->hd63701y0.PORT2 = 0x00; // port 2, R/W
97   state->hd63701y0.P3DDR = 0xFE; // port 3 ddr, W
98   state->hd63701y0.P4DDR = 0x00; // port 4 ddr, W
99   state->hd63701y0.PORT3 = 0x00; // port 3, R/W
100   state->hd63701y0.PORT4 = 0x00; // port 4, R/W
101   state->hd63701y0.TCSR1 = 0x00; // timer control/status, R/W
102   state->hd63701y0.FRCH = 0x00;
103   state->hd63701y0.FRCL = 0x00;
104   state->hd63701y0.OCR1H = 0xFF;
105   state->hd63701y0.OCR1L = 0xFF;
106   state->hd63701y0.ICRH = 0x00;
107   state->hd63701y0.ICRL = 0x00;
108   state->hd63701y0.TCSR2 = 0x10;
109   state->hd63701y0.RMCR = 0xC0;
110   state->hd63701y0.TRCSR1 = 0x20;
111   state->hd63701y0.RDR = 0x00; // Recieve Data Reg, R
112   state->hd63701y0.TDR = 0x00; // Transmit Data Reg, W
113   state->hd63701y0.RP5CR = 0x78; // or 0xF8; Ram/Port5 Control Reg, R/W
114   state->hd63701y0.PORT5 = 0x00; // port 5, R/W
115   state->hd63701y0.P6DDR = 0x00; // port 6 ddr, W
116   state->hd63701y0.PORT6 = 0x00; // port 6, R/W
117   state->hd63701y0.PORT7 = 0x00; // port 7, R/W
118   state->hd63701y0.OCR2H = 0xFF;
119   state->hd63701y0.OCR2L = 0xFF;
120   state->hd63701y0.TCSR3 = 0x20;
121   state->hd63701y0.TCONR = 0xFF;
122   state->hd63701y0.T2CNT = 0x00;
123   state->hd63701y0.TRCSR2 = 0x28;
124   state->hd63701y0.TSTREG = 0x00;
125   state->hd63701y0.P5DDR = 0x00; // port 5 ddr, W
126   state->hd63701y0.P6CSR = 0x00;
115127}
116128
117129static READ8_HANDLER( main_hd63701_internal_registers_r )
118130{
131   rvoice_state *state = space->machine->driver_data<rvoice_state>();
119132   UINT8 data = 0;
120133   logerror("main hd637B01Y0: %04x: read from 0x%02X: ", cpu_get_pc(space->cpu), offset);
121134   switch(offset)
r9685r9686
133146         break;
134147      case 0x02: // Port 1
135148         logerror("Port 1\n");
136         data = hd63701y0.PORT1;
149         data = state->hd63701y0.PORT1;
137150         break;
138151      case 0x03: // Port 2
139152         logerror("Port 2\n");
140         data = hd63701y0.PORT1;
153         data = state->hd63701y0.PORT1;
141154         break;
142155      case 0x06: // Port 3
143156         logerror("Port 3\n");
144         data = hd63701y0.PORT3;
157         data = state->hd63701y0.PORT3;
145158         break;
146159      case 0x07: // Port 4
147160         logerror("Port 4\n");
148         data = hd63701y0.PORT4;
161         data = state->hd63701y0.PORT4;
149162         break;
150163      case 0x08: // Timer Control/Status Register 1
151164         logerror("Timer Control/Status Register 1\n");
152         data = hd63701y0.TCSR1;
165         data = state->hd63701y0.TCSR1;
153166         break;
154167      case 0x09: // Free Running Counter (MSB)
155168         logerror("Free Running Counter (MSB)\n");
156         data = hd63701y0.FRCH;
169         data = state->hd63701y0.FRCH;
157170         break;
158171      case 0x0A: // Free Running Counter (LSB)
159172         logerror("Free Running Counter (LSB)\n");
160         data = hd63701y0.FRCL;
173         data = state->hd63701y0.FRCL;
161174         break;
162175      // B C (D E)
163176      case 0x0F: // Timer Control/Status Register 2
164177         logerror("Timer Control/Status Register 2\n");
165         data = hd63701y0.TCSR2;
178         data = state->hd63701y0.TCSR2;
166179         break;
167180      // 10 11 (12)
168181
169182      case 0x14: // RAM/Port 5 Control Register
170183         logerror("RAM/Port 5 Control Register\n");
171         data = hd63701y0.RP5CR;
184         data = state->hd63701y0.RP5CR;
172185         break;
173186      case 0x15: // Port 5
174187         logerror("Port 5\n");
175         data = hd63701y0.PORT5;
188         data = state->hd63701y0.PORT5;
176189         break;
177190      case 0x17: // Port 6
178191         logerror("Port 6\n");
179         data = hd63701y0.PORT6;
192         data = state->hd63701y0.PORT6;
180193         break;
181194      case 0x18: // Port 7
182195         logerror("Port 7\n");
183         data = hd63701y0.PORT7;
196         data = state->hd63701y0.PORT7;
184197         break;
185198      // 19 1a 1b 1c 1d 1e 1f
186199      case 0x21: // Port 6 Control/Status Register
187200         logerror("Port 6 Control/Status Register\n");
188         data = hd63701y0.P6CSR;
201         data = state->hd63701y0.P6CSR;
189202         break;
190203      default:
191204         logerror("\n");
r9685r9686
199212
200213static WRITE8_HANDLER( main_hd63701_internal_registers_w )
201214{
215   rvoice_state *state = space->machine->driver_data<rvoice_state>();
202216   logerror("main hd637B01Y0: %04x: write to 0x%02X: ", cpu_get_pc(space->cpu), offset);
203217   switch(offset)
204218   {
205219      case 0x00: // Port 1 DDR
206220         logerror("Port 1 DDR of %02X\n", data);
207         hd63701y0.P1DDR = data;
208         rvoicepc.port1 = (hd63701y0.PORT1 & hd63701y0.P1DDR);
221         state->hd63701y0.P1DDR = data;
222         state->rvoicepc.port1 = (state->hd63701y0.PORT1 & state->hd63701y0.P1DDR);
209223         break;
210224      case 0x01: // Port 2 DDR
211225         logerror("Port 2 DDR of %02X\n", data);
212         hd63701y0.P2DDR = data;
213         rvoicepc.port2 = (hd63701y0.PORT2 & hd63701y0.P2DDR);
226         state->hd63701y0.P2DDR = data;
227         state->rvoicepc.port2 = (state->hd63701y0.PORT2 & state->hd63701y0.P2DDR);
214228         break;
215229      case 0x02: // Port 1
216230         logerror("Port 1 of %02X\n", data);
217         hd63701y0.PORT1 = data;
218         rvoicepc.port1 = (hd63701y0.PORT1 & hd63701y0.P1DDR);
231         state->hd63701y0.PORT1 = data;
232         state->rvoicepc.port1 = (state->hd63701y0.PORT1 & state->hd63701y0.P1DDR);
219233         break;
220234      case 0x03: // Port 2
221235         logerror("Port 2 of %02X\n", data);
222         hd63701y0.PORT2 = data;
223         rvoicepc.port2 = (hd63701y0.PORT2 & hd63701y0.P2DDR);
236         state->hd63701y0.PORT2 = data;
237         state->rvoicepc.port2 = (state->hd63701y0.PORT2 & state->hd63701y0.P2DDR);
224238         break;
225239      case 0x04: // Port 3 DDR
226240         logerror("Port 3 DDR of %02X\n", data);
227         hd63701y0.P3DDR = data;
228         rvoicepc.port3 = (hd63701y0.PORT3 & hd63701y0.P3DDR);
241         state->hd63701y0.P3DDR = data;
242         state->rvoicepc.port3 = (state->hd63701y0.PORT3 & state->hd63701y0.P3DDR);
229243         break;
230244      case 0x05: // Port 4 DDR
231245         logerror("Port 4 DDR of %02X\n", data);
232         hd63701y0.P4DDR = data;
233         rvoicepc.port4 = (hd63701y0.PORT4 & hd63701y0.P4DDR);
246         state->hd63701y0.P4DDR = data;
247         state->rvoicepc.port4 = (state->hd63701y0.PORT4 & state->hd63701y0.P4DDR);
234248         break;
235249      case 0x06: // Port 3
236250         logerror("Port 3 of %02X\n", data);
237         hd63701y0.PORT3 = data;
238         rvoicepc.port3 = (hd63701y0.PORT3 & hd63701y0.P3DDR);
251         state->hd63701y0.PORT3 = data;
252         state->rvoicepc.port3 = (state->hd63701y0.PORT3 & state->hd63701y0.P3DDR);
239253         break;
240254      case 0x07: // Port 4
241255         logerror("Port 4 of %02X\n", data);
242         hd63701y0.PORT4 = data;
243         rvoicepc.port4 = (hd63701y0.PORT4 & hd63701y0.P4DDR);
256         state->hd63701y0.PORT4 = data;
257         state->rvoicepc.port4 = (state->hd63701y0.PORT4 & state->hd63701y0.P4DDR);
244258         break;
245259      case 0x08: // Timer Control/Status Register 1
246260         logerror("Timer Control/Status Register 1 of %02X\n", data);
247         hd63701y0.TCSR1 = data;
261         state->hd63701y0.TCSR1 = data;
248262         break;
249263      case 0x09: // Free Running Counter (MSB)
250264         logerror("Free Running Counter (MSB) of %02X\n", data);
251         hd63701y0.FRCH = data;
265         state->hd63701y0.FRCH = data;
252266         break;
253267      case 0x0A: // Free Running Counter (LSB)
254268         logerror("Free Running Counter (LSB) of %02X\n", data);
255         hd63701y0.FRCL = data;
269         state->hd63701y0.FRCL = data;
256270         break;
257271      // B C (D E)
258272      case 0x0F: // Timer Control/Status Register 2
259273         logerror("Timer Control/Status Register 2 of %02X\n", data);
260         hd63701y0.TCSR2 = data;
274         state->hd63701y0.TCSR2 = data;
261275         break;
262276      // 10 11 (12)
263277      case 0x13: // TxD Register
264278         logerror("TxD Register of %02X\n", data);
265         hd63701y0.TDR = data;
279         state->hd63701y0.TDR = data;
266280         break;
267281      case 0x14: // RAM/Port 5 Control Register
268282         logerror("RAM/Port 5 Control Register of %02X\n", data);
269         hd63701y0.RP5CR = data;
283         state->hd63701y0.RP5CR = data;
270284         break;
271285      case 0x15: // Port 5
272286         logerror("Port 5 of %02X\n", data);
273         hd63701y0.PORT5 = data;
274         rvoicepc.port5 = (hd63701y0.PORT5 & hd63701y0.P5DDR);
287         state->hd63701y0.PORT5 = data;
288         state->rvoicepc.port5 = (state->hd63701y0.PORT5 & state->hd63701y0.P5DDR);
275289         break;
276290      case 0x16: // Port 6 DDR
277291         logerror("Port 6 DDR of %02X\n", data);
278         hd63701y0.P6DDR = data;
279         rvoicepc.port6 = (hd63701y0.PORT6 & hd63701y0.P6DDR);
292         state->hd63701y0.P6DDR = data;
293         state->rvoicepc.port6 = (state->hd63701y0.PORT6 & state->hd63701y0.P6DDR);
280294         break;
281295      case 0x17: // Port 6
282296         logerror("Port 6 of %02X\n", data);
283         hd63701y0.PORT6 = data;
284         rvoicepc.port6 = (hd63701y0.PORT6 & hd63701y0.P6DDR);
297         state->hd63701y0.PORT6 = data;
298         state->rvoicepc.port6 = (state->hd63701y0.PORT6 & state->hd63701y0.P6DDR);
285299         break;
286300      case 0x18: // Port 7
287301         logerror("Port 7 of %02X\n", data);
288         hd63701y0.PORT7 = data;
289         rvoicepc.port7 = data;
302         state->hd63701y0.PORT7 = data;
303         state->rvoicepc.port7 = data;
290304         break;
291305      // 19 1a 1b 1c 1d 1e 1f
292306      case 0x20: // Port 5 DDR
293307         logerror("Port 5 DDR of %02X\n", data);
294         hd63701y0.P5DDR = data;
295         rvoicepc.port5 = (hd63701y0.PORT5 & hd63701y0.P5DDR);
308         state->hd63701y0.P5DDR = data;
309         state->rvoicepc.port5 = (state->hd63701y0.PORT5 & state->hd63701y0.P5DDR);
296310         break;
297311      case 0x21: // Port 6 Control/Status Register
298312         logerror("Port 6 Control/Status Register of %02X\n", data);
299         hd63701y0.P6CSR = data;
313         state->hd63701y0.P6CSR = data;
300314         break;
301315      default:
302316         logerror("with data of %02X\n", data);
r9685r9686
310324******************************************************************************/
311325
312326static ADDRESS_MAP_START(hd63701_main_mem, ADDRESS_SPACE_PROGRAM, 8)
313    ADDRESS_MAP_UNMAP_HIGH
327   ADDRESS_MAP_UNMAP_HIGH
314328   AM_RANGE(0x0000, 0x0027) AM_READWRITE(main_hd63701_internal_registers_r, main_hd63701_internal_registers_w) // INTERNAL REGS
315329   AM_RANGE(0x0040, 0x013f) AM_RAM // INTERNAL RAM (overlaps acia)
316330   AM_RANGE(0x0060, 0x007f) AM_DEVREADWRITE( "acia65c51", acia_6551_r, acia_6551_w) // ACIA 65C51
317    AM_RANGE(0x2000, 0x7fff) AM_RAM // EXTERNAL SRAM
331   AM_RANGE(0x2000, 0x7fff) AM_RAM // EXTERNAL SRAM
318332   AM_RANGE(0x8000, 0xffff) AM_ROM // 27512 EPROM
319333ADDRESS_MAP_END
320334
r9685r9686
342356   DEVCB_HANDLER(null_kbd_put)
343357};
344358
345static MACHINE_CONFIG_START( rvoicepc, driver_device )
346    /* basic machine hardware */
347    MDRV_CPU_ADD("maincpu", HD63701, XTAL_7_3728MHz)
348    MDRV_CPU_PROGRAM_MAP(hd63701_main_mem)
349    MDRV_CPU_IO_MAP(hd63701_main_io)
359static MACHINE_CONFIG_START( rvoicepc, rvoice_state )
360   /* basic machine hardware */
361   MDRV_CPU_ADD("maincpu", HD63701, XTAL_7_3728MHz)
362   MDRV_CPU_PROGRAM_MAP(hd63701_main_mem)
363   MDRV_CPU_IO_MAP(hd63701_main_io)
350364
351    //MDRV_CPU_ADD("playercpu", HD63701, XTAL_7_3728MHz) // not dumped yet
352    //MDRV_CPU_PROGRAM_MAP(hd63701_slave_mem)
353    //MDRV_CPU_IO_MAP(hd63701_slave_io)
354    MDRV_QUANTUM_TIME(HZ(60))
355    MDRV_MACHINE_RESET(rvoicepc)
365   //MDRV_CPU_ADD("playercpu", HD63701, XTAL_7_3728MHz) // not dumped yet
366   //MDRV_CPU_PROGRAM_MAP(hd63701_slave_mem)
367   //MDRV_CPU_IO_MAP(hd63701_slave_io)
368   MDRV_QUANTUM_TIME(HZ(60))
369   MDRV_MACHINE_RESET(rvoicepc)
356370
357    MDRV_ACIA6551_ADD("acia65c51")
371   MDRV_ACIA6551_ADD("acia65c51")
358372
359    /* video hardware */
360    //MDRV_DEFAULT_LAYOUT(layout_dectalk) // hack to avoid screenless system crash
373   /* video hardware */
374   //MDRV_DEFAULT_LAYOUT(layout_dectalk) // hack to avoid screenless system crash
361375
362    /* sound hardware */
376   /* sound hardware */
363377   MDRV_FRAGMENT_ADD( generic_terminal )
364378   MDRV_GENERIC_TERMINAL_ADD(TERMINAL_TAG,dectalk_terminal_intf)
365379
r9685r9686
373387
374388ROM_START(rvoicepc)
375389
376    ROM_REGION(0x10000, "maincpu", 0)
377    ROM_LOAD("rv_pc.bin", 0x08000, 0x08000, CRC(4001CD5F) SHA1(D973C6E19E493EEDD4F7216BC530DDB0B6C4921E))
378    ROM_CONTINUE(0x8000, 0x8000) // first half of 27c512 rom is blank due to stupid address decoder circuit
390   ROM_REGION(0x10000, "maincpu", 0)
391   ROM_LOAD("rv_pc.bin", 0x08000, 0x08000, CRC(4001CD5F) SHA1(D973C6E19E493EEDD4F7216BC530DDB0B6C4921E))
392   ROM_CONTINUE(0x8000, 0x8000) // first half of 27c512 rom is blank due to stupid address decoder circuit
379393
380394ROM_END
381395
src/mess/drivers/basic52.c
r9685r9686
1111#include "machine/i8255a.h"
1212#include "machine/terminal.h"
1313
14
15class basic52_state : public driver_device
16{
17public:
18   basic52_state(running_machine &machine, const driver_device_config_base &config)
19      : driver_device(machine, config) { }
20
21};
22
23
1424static ADDRESS_MAP_START(basic52_mem, ADDRESS_SPACE_PROGRAM, 8)
1525   ADDRESS_MAP_UNMAP_HIGH
1626   AM_RANGE(0x0000, 0x1fff) AM_ROM
r9685r9686
5969   DEVCB_NULL               /* Port C write */
6070};
6171
62static MACHINE_CONFIG_START( basic31, driver_device )
72static MACHINE_CONFIG_START( basic31, basic52_state )
6373    /* basic machine hardware */
6474    MDRV_CPU_ADD("maincpu", I8031, XTAL_11_0592MHz)
6575    MDRV_CPU_PROGRAM_MAP(basic52_mem)
r9685r9686
7484   MDRV_I8255A_ADD("ppi8255", ppi8255_intf )
7585MACHINE_CONFIG_END
7686
77static MACHINE_CONFIG_START( basic52, driver_device )
87static MACHINE_CONFIG_START( basic52, basic52_state )
7888    /* basic machine hardware */
7989    MDRV_CPU_ADD("maincpu", I8052, XTAL_11_0592MHz)
8090    MDRV_CPU_PROGRAM_MAP(basic52_mem)
src/mess/drivers/sys2900.c
r9685r9686
3636#include "emu.h"
3737#include "cpu/z80/z80.h"
3838
39
40class sys2900_state : public driver_device
41{
42public:
43   sys2900_state(running_machine &machine, const driver_device_config_base &config)
44      : driver_device(machine, config) { }
45
46};
47
48
3949static ADDRESS_MAP_START(sys2900_mem, ADDRESS_SPACE_PROGRAM, 8)
4050   ADDRESS_MAP_UNMAP_HIGH
4151   AM_RANGE( 0x0000, 0xefff ) AM_RAM
r9685r9686
6575    return 0;
6676}
6777
68static MACHINE_CONFIG_START( sys2900, driver_device )
78static MACHINE_CONFIG_START( sys2900, sys2900_state )
6979    /* basic machine hardware */
7080    MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
7181    MDRV_CPU_PROGRAM_MAP(sys2900_mem)
src/mess/drivers/codata.c
r9685r9686
1010#include "cpu/m68000/m68000.h"
1111
1212
13class codata_state : public driver_device
14{
15public:
16   codata_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
22
1323static ADDRESS_MAP_START(codata_mem, ADDRESS_SPACE_PROGRAM, 16)
1424   ADDRESS_MAP_UNMAP_HIGH
1525ADDRESS_MAP_END
r9685r9686
3242    return 0;
3343}
3444
35static MACHINE_CONFIG_START( codata, driver_device )
45static MACHINE_CONFIG_START( codata, codata_state )
3646    /* basic machine hardware */
3747    MDRV_CPU_ADD("maincpu",M68000, XTAL_16MHz / 2)
3848    MDRV_CPU_PROGRAM_MAP(codata_mem)
src/mess/drivers/stopthie.c
r9685r9686
55#include "stopthie.lh"
66
77
8class stopthie_state : public driver_device
9{
10public:
11   stopthie_state(running_machine &machine, const driver_device_config_base &config)
12      : driver_device(machine, config) { }
13
14};
15
16
17
818#define LOG 1
919
1020static INPUT_PORTS_START( stopthie )
r9685r9686
5262};
5363
5464
55static MACHINE_CONFIG_START( stopthie, driver_device )
65static MACHINE_CONFIG_START( stopthie, stopthie_state )
5666   MDRV_CPU_ADD( "maincpu", TMS0980, 5000000 )   /* Clock is wrong */
5767   MDRV_CPU_CONFIG( stopthie_tms0980_config )
5868
src/mess/drivers/a51xx.c
r9685r9686
1212#include "emu.h"
1313#include "cpu/z80/z80.h"
1414
15
16class a51xx_state : public driver_device
17{
18public:
19   a51xx_state(running_machine &machine, const driver_device_config_base &config)
20      : driver_device(machine, config) { }
21
22};
23
24
1525static ADDRESS_MAP_START(a5120_mem, ADDRESS_SPACE_PROGRAM, 8)
1626   ADDRESS_MAP_UNMAP_HIGH
1727   AM_RANGE( 0x0000, 0x03ff ) AM_ROM
r9685r9686
8898   GFXDECODE_ENTRY( "gfx1", 0x0000, a51xx_charlayout, 0, 1 )
8999GFXDECODE_END
90100
91static MACHINE_CONFIG_START( a5120, driver_device )
101static MACHINE_CONFIG_START( a5120, a51xx_state )
92102   /* basic machine hardware */
93103   MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
94104   MDRV_CPU_PROGRAM_MAP(a5120_mem)
r9685r9686
111121   MDRV_VIDEO_UPDATE(a5120)
112122MACHINE_CONFIG_END
113123
114static MACHINE_CONFIG_START( a5130, driver_device )
124static MACHINE_CONFIG_START( a5130, a51xx_state )
115125   /* basic machine hardware */
116126   MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
117127   MDRV_CPU_PROGRAM_MAP(a5130_mem)
src/mess/drivers/geneve.c
r9685r9686
206206#include "sound/sn76496.h"
207207#include "machine/ti99/peribox.h"
208208
209
210class geneve_state : public driver_device
211{
212public:
213   geneve_state(running_machine &machine, const driver_device_config_base &config)
214      : driver_device(machine, config) { }
215
216};
217
218
209219/*
210220    memory map
211221*/
r9685r9686
455465{
456466}
457467
458static MACHINE_CONFIG_START( geneve_60hz, driver_device )
468static MACHINE_CONFIG_START( geneve_60hz, geneve_state )
459469   /* basic machine hardware */
460470   /* TMS9995 CPU @ 12.0 MHz */
461471   MDRV_CPU_ADD("maincpu", TMS9995, 12000000)
src/mess/drivers/instruct.c
r9685r9686
99#include "emu.h"
1010#include "cpu/s2650/s2650.h"
1111
12
13class instruct_state : public driver_device
14{
15public:
16   instruct_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(instruct_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x07ff) AM_ROM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( instruct, driver_device )
50static MACHINE_CONFIG_START( instruct, instruct_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",S2650, XTAL_1MHz)
4353    MDRV_CPU_PROGRAM_MAP(instruct_mem)
src/mess/drivers/alesis.c
r9685r9686
1212#include "emu.h"
1313#include "cpu/mcs51/mcs51.h"
1414
15
16class alesis_state : public driver_device
17{
18public:
19   alesis_state(running_machine &machine, const driver_device_config_base &config)
20      : driver_device(machine, config) { }
21
22};
23
24
1525static ADDRESS_MAP_START(hr16_mem, ADDRESS_SPACE_PROGRAM, 8)
1626   ADDRESS_MAP_UNMAP_HIGH
1727   AM_RANGE(0x0000, 0x7fff) AM_ROM
r9685r9686
4959   return 0;
5060}
5161
52static MACHINE_CONFIG_START( hr16, driver_device )
62static MACHINE_CONFIG_START( hr16, alesis_state )
5363   /* basic machine hardware */
5464   MDRV_CPU_ADD("maincpu",I8031, XTAL_12MHz)
5565   MDRV_CPU_PROGRAM_MAP(hr16_mem)
r9685r9686
7181   MDRV_VIDEO_UPDATE(alesis)
7282MACHINE_CONFIG_END
7383
74static MACHINE_CONFIG_START( sr16, driver_device )
84static MACHINE_CONFIG_START( sr16, alesis_state )
7585   /* basic machine hardware */
7686   MDRV_CPU_ADD("maincpu",I8031, XTAL_12MHz)
7787   MDRV_CPU_PROGRAM_MAP(sr16_mem)
src/mess/drivers/mk85.c
r9685r9686
99#include "emu.h"
1010#include "cpu/t11/t11.h"
1111
12
13class mk85_state : public driver_device
14{
15public:
16   mk85_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(mk85_mem, ADDRESS_SPACE_PROGRAM, 16)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x7fff ) AM_ROM
r9685r9686
3848   5 << 13         /* start from 0000 */
3949};
4050
41static MACHINE_CONFIG_START( mk85, driver_device )
51static MACHINE_CONFIG_START( mk85, mk85_state )
4252    /* basic machine hardware */
4353    MDRV_CPU_ADD("maincpu",T11, XTAL_4MHz)
4454    MDRV_CPU_CONFIG(t11_data)
src/mess/drivers/elektor.c
r9685r9686
99#include "emu.h"
1010#include "cpu/s2650/s2650.h"
1111
12
13class elektor_state : public driver_device
14{
15public:
16   elektor_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(elektor_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x07ff) AM_ROM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( elektor, driver_device )
50static MACHINE_CONFIG_START( elektor, elektor_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",S2650, XTAL_1MHz)
4353    MDRV_CPU_PROGRAM_MAP(elektor_mem)
src/mess/drivers/dm7000.c
r9685r9686
3939#include "emu.h"
4040#include "cpu/powerpc/ppc.h"
4141
42
43class dm7000_state : public driver_device
44{
45public:
46   dm7000_state(running_machine &machine, const driver_device_config_base &config)
47      : driver_device(machine, config) { }
48
49};
50
51
4252/*
4353 Memory map for the IBM "Redwood-4" STB03xxx evaluation board.
4454
r9685r9686
8292    return 0;
8393}
8494
85static MACHINE_CONFIG_START( dm7000, driver_device )
95static MACHINE_CONFIG_START( dm7000, dm7000_state )
8696    /* basic machine hardware */
8797    MDRV_CPU_ADD("maincpu",PPC403GA, 252000000) // Should be PPC405
8898    MDRV_CPU_PROGRAM_MAP(dm7000_mem)
src/mess/drivers/unior.c
r9685r9686
99#include "emu.h"
1010#include "cpu/i8085/i8085.h"
1111
12
13class unior_state : public driver_device
14{
15public:
16   unior_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(unior_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE(0x0000,0xf7ff) AM_RAM
r9685r9686
5565   GFXDECODE_ENTRY( "gfx1", 0x0000, unior_charlayout, 0, 1 )
5666GFXDECODE_END
5767
58static MACHINE_CONFIG_START( unior, driver_device )
68static MACHINE_CONFIG_START( unior, unior_state )
5969    /* basic machine hardware */
6070    MDRV_CPU_ADD("maincpu",I8080, 2222222)
6171    MDRV_CPU_PROGRAM_MAP(unior_mem)
src/mess/drivers/pmi80.c
r9685r9686
99#include "emu.h"
1010#include "cpu/i8085/i8085.h"
1111
12
13class pmi80_state : public driver_device
14{
15public:
16   pmi80_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(pmi80_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x03ff ) AM_ROM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( pmi80, driver_device )
50static MACHINE_CONFIG_START( pmi80, pmi80_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",I8080, XTAL_1MHz)
4353    MDRV_CPU_PROGRAM_MAP(pmi80_mem)
src/mess/drivers/apogee.c
r9685r9686
1717#include "formats/rk_cas.h"
1818#include "includes/radio86.h"
1919
20
21class apogee_state : public driver_device
22{
23public:
24   apogee_state(running_machine &machine, const driver_device_config_base &config)
25      : driver_device(machine, config) { }
26
27};
28
29
2030/* Address maps */
2131static ADDRESS_MAP_START(apogee_mem, ADDRESS_SPACE_PROGRAM, 8)
2232    AM_RANGE( 0x0000, 0x0fff ) AM_RAMBANK("bank1") // First bank
r9685r9686
151161
152162
153163/* Machine driver */
154static MACHINE_CONFIG_START( apogee, driver_device )
164static MACHINE_CONFIG_START( apogee, apogee_state )
155165    /* basic machine hardware */
156166    MDRV_CPU_ADD("maincpu", I8080, XTAL_16MHz / 9)
157167    MDRV_CPU_PROGRAM_MAP(apogee_mem)
src/mess/drivers/vk100.c
r9685r9686
5151#include "emu.h"
5252#include "cpu/i8085/i8085.h"
5353
54
55class vk100_state : public driver_device
56{
57public:
58   vk100_state(running_machine &machine, const driver_device_config_base &config)
59      : driver_device(machine, config) { }
60
61};
62
63
5464static ADDRESS_MAP_START(vk100_mem, ADDRESS_SPACE_PROGRAM, 8)
5565   ADDRESS_MAP_UNMAP_HIGH
5666    AM_RANGE( 0x0000, 0x67ff ) AM_ROM
r9685r9686
113123    return 0;
114124}
115125
116static MACHINE_CONFIG_START( vk100, driver_device )
126static MACHINE_CONFIG_START( vk100, vk100_state )
117127    /* basic machine hardware */
118128    MDRV_CPU_ADD("maincpu", I8085A, XTAL_5_0688MHz)
119129    MDRV_CPU_PROGRAM_MAP(vk100_mem)
src/mess/drivers/acrnsys1.c
r9685r9686
1515#include "acrnsys1.lh"
1616
1717
18class acrnsys1_state : public driver_device
19{
20public:
21   acrnsys1_state(running_machine &machine, const driver_device_config_base &config)
22      : driver_device(machine, config) { }
23
24};
25
26
27
1828/***************************************************************************
1929    KEYBOARD HANDLING
2030***************************************************************************/
r9685r9686
153163   DEVCB_NULL
154164};
155165
156static MACHINE_CONFIG_START( acrnsys1, driver_device )
166static MACHINE_CONFIG_START( acrnsys1, acrnsys1_state )
157167   /* basic machine hardware */
158168   MDRV_CPU_ADD("maincpu", M6502, 1008000)  /* 1.008 MHz */
159169   MDRV_CPU_PROGRAM_MAP(acrnsys1_map)
src/mess/drivers/cd2650.c
r9685r9686
99#include "emu.h"
1010#include "cpu/s2650/s2650.h"
1111
12
13class cd2650_state : public driver_device
14{
15public:
16   cd2650_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(cd2650_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0x03ff) AM_ROM
r9685r9686
3747    return 0;
3848}
3949
40static MACHINE_CONFIG_START( cd2650, driver_device )
50static MACHINE_CONFIG_START( cd2650, cd2650_state )
4151    /* basic machine hardware */
4252    MDRV_CPU_ADD("maincpu",S2650, XTAL_1MHz)
4353    MDRV_CPU_PROGRAM_MAP(cd2650_mem)
src/mess/drivers/horizon.c
r9685r9686
1010#include "cpu/z80/z80.h"
1111#include "machine/terminal.h"
1212
13
14class horizon_state : public driver_device
15{
16public:
17   horizon_state(running_machine &machine, const driver_device_config_base &config)
18      : driver_device(machine, config) { }
19
20};
21
22
1323static ADDRESS_MAP_START(horizon_mem, ADDRESS_SPACE_PROGRAM, 8)
1424   ADDRESS_MAP_UNMAP_HIGH
1525   AM_RANGE(0x0000, 0xe7ff) AM_RAM
r9685r9686
5767   DEVCB_HANDLER(horizon_kbd_put)
5868};
5969
60static MACHINE_CONFIG_START( horizon, driver_device )
70static MACHINE_CONFIG_START( horizon, horizon_state )
6171    /* basic machine hardware */
6272    MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
6373    MDRV_CPU_PROGRAM_MAP(horizon_mem)
src/mess/drivers/rmnimbus.c
r9685r9686
287287}
288288
289289
290static MACHINE_CONFIG_START( nimbus, driver_device )
290static MACHINE_CONFIG_START( nimbus, rmnimbus_state )
291291    /* basic machine hardware */
292292    MDRV_CPU_ADD(MAINCPU_TAG, I80186, 10000000)
293293    MDRV_CPU_PROGRAM_MAP(nimbus_mem)
src/mess/drivers/pcfx.c
r9685r9686
1010#include "cpu/v810/v810.h"
1111#include "video/vdc.h"
1212
13
14class pcfx_state : public driver_device
15{
16public:
17   pcfx_state(running_machine &machine, const driver_device_config_base &config)
18      : driver_device(machine, config) { }
19
20};
21
22
1323static ADDRESS_MAP_START( pcfx_mem, ADDRESS_SPACE_PROGRAM, 32 )
1424   AM_RANGE( 0x00000000, 0x001FFFFF ) AM_RAM   /* RAM */
1525   AM_RANGE( 0x80700000, 0x807FFFFF ) AM_NOP   /* EXTIO */
r9685r9686
4454}
4555
4656
47static MACHINE_CONFIG_START( pcfx, driver_device )
57static MACHINE_CONFIG_START( pcfx, pcfx_state )
4858   MDRV_CPU_ADD( "maincpu", V810, 21477270 )
4959   MDRV_CPU_PROGRAM_MAP( pcfx_mem)
5060   MDRV_CPU_IO_MAP( pcfx_io)
src/mess/drivers/iq151.c
r9685r9686
99#include "emu.h"
1010#include "cpu/z80/z80.h"
1111
12
13class iq151_state : public driver_device
14{
15public:
16   iq151_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(iq151_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   ADDRESS_MAP_UNMAP_HIGH
1424   AM_RANGE( 0x0000, 0xefff ) AM_RAM
r9685r9686
6979   GFXDECODE_ENTRY( "chargen", 0x0400, iq151_64_charlayout, 0, 1 )
7080GFXDECODE_END
7181
72static MACHINE_CONFIG_START( iq151, driver_device )
82static MACHINE_CONFIG_START( iq151, iq151_state )
7383    /* basic machine hardware */
7484    MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
7585    MDRV_CPU_PROGRAM_MAP(iq151_mem)
src/mess/drivers/a310.c
r9685r9686
6464#include "machine/i2cmem.h"
6565#include "devices/messram.h"
6666
67
68class a310_state : public driver_device
69{
70public:
71   a310_state(running_machine &machine, const driver_device_config_base &config)
72      : driver_device(machine, config) { }
73
74};
75
76
6777static WRITE_LINE_DEVICE_HANDLER( a310_wd177x_intrq_w )
6878{
6979   if (state)
r9685r9686
249259   I2CMEM_SLAVE_ADDRESS, 0, 0x100
250260};
251261
252static MACHINE_CONFIG_START( a310, driver_device )
262static MACHINE_CONFIG_START( a310, a310_state )
253263   /* basic machine hardware */
254264   MDRV_CPU_ADD("maincpu", ARM, 8000000)        /* 8 MHz */
255265   MDRV_CPU_PROGRAM_MAP(a310_mem)
src/mess/drivers/ccs2810.c
r9685r9686
1010#include "cpu/z80/z80.h"
1111#include "machine/ins8250.h"
1212
13
14class ccs2810_state : public driver_device
15{
16public:
17   ccs2810_state(running_machine &machine, const driver_device_config_base &config)
18      : driver_device(machine, config) { }
19
20};
21
22
1323static ADDRESS_MAP_START(ccs2810_mem, ADDRESS_SPACE_PROGRAM, 8)
1424   ADDRESS_MAP_UNMAP_HIGH
1525   AM_RANGE(0x0000, 0xefff) AM_RAM
r9685r9686
5060   NULL
5161};
5262
53static MACHINE_CONFIG_START( ccs2810, driver_device )
63static MACHINE_CONFIG_START( ccs2810, ccs2810_state )
5464    /* basic machine hardware */
5565    MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
5666    MDRV_CPU_PROGRAM_MAP(ccs2810_mem)
src/mess/drivers/ipds.c
r9685r9686
1010#include "cpu/i8085/i8085.h"
1111#include "video/i8275.h"
1212
13
14class ipds_state : public driver_device
15{
16public:
17   ipds_state(running_machine &machine, const driver_device_config_base &config)
18      : driver_device(machine, config) { }
19
20};
21
22
1323static ADDRESS_MAP_START(ipds_mem, ADDRESS_SPACE_PROGRAM, 8)
1424   ADDRESS_MAP_UNMAP_HIGH
1525   AM_RANGE(0x0000, 0x07ff) AM_ROM
r9685r9686
8595   GFXDECODE_ENTRY( "gfx1", 0x0000, ipds_charlayout, 0, 1 )
8696GFXDECODE_END
8797
88static MACHINE_CONFIG_START( ipds, driver_device )
98static MACHINE_CONFIG_START( ipds, ipds_state )
8999    /* basic machine hardware */
90100    MDRV_CPU_ADD("maincpu",I8085A, XTAL_19_6608MHz / 4)
91101    MDRV_CPU_PROGRAM_MAP(ipds_mem)
src/mess/drivers/swtpc.c
r9685r9686
1212#include "cpu/m6800/m6800.h"
1313#include "machine/terminal.h"
1414
15
16class swtpc_state : public driver_device
17{
18public:
19   swtpc_state(running_machine &machine, const driver_device_config_base &config)
20      : driver_device(machine, config) { }
21
22};
23
24
1525static WRITE8_HANDLER(swtpc_terminal_w)
1626{
1727   running_device *devconf = space->machine->device("terminal");
r9685r9686
4555   DEVCB_HANDLER(swtpc_kbd_put)
4656};
4757
48static MACHINE_CONFIG_START( swtpc, driver_device )
58static MACHINE_CONFIG_START( swtpc, swtpc_state )
4959    /* basic machine hardware */
5060    MDRV_CPU_ADD("maincpu", M6800, XTAL_1MHz)
5161    MDRV_CPU_PROGRAM_MAP(swtpc_mem)
src/mess/drivers/ti99_4p.c
r9685r9686
6363#include "machine/ti99/sgcpu.h"
6464#include "machine/ti99/peribox.h"
6565
66
67class ti99_4p_state : public driver_device
68{
69public:
70   ti99_4p_state(running_machine &machine, const driver_device_config_base &config)
71      : driver_device(machine, config) { }
72
73};
74
75
6676static ADDRESS_MAP_START(memmap, ADDRESS_SPACE_PROGRAM, 16)
6777   AM_RANGE(0x0000, 0xffff) AM_DEVREADWRITE("sgcpu_board", sgcpu_r, sgcpu_w )
6878ADDRESS_MAP_END
r9685r9686
263273/*
264274    Machine description.
265275*/
266static MACHINE_CONFIG_START( ti99_4p_60hz, driver_device )
276static MACHINE_CONFIG_START( ti99_4p_60hz, ti99_4p_state )
267277   /* basic machine hardware */
268278   /* TMS9900 CPU @ 3.0 MHz */
269279   MDRV_CPU_ADD("maincpu", TMS9900, 3000000)
src/mess/drivers/clcd.c
r9685r9686
99#include "emu.h"
1010#include "cpu/m6502/m6502.h"
1111
12
13class clcd_state : public driver_device
14{
15public:
16   clcd_state(running_machine &machine, const driver_device_config_base &config)
17      : driver_device(machine, config) { }
18
19};
20
21
1222static ADDRESS_MAP_START(clcd_mem, ADDRESS_SPACE_PROGRAM, 8)
1323   AM_RANGE(0x0000, 0x7fff) AM_RAM
1424   AM_RANGE(0x8000, 0xffff) AM_ROM AM_REGION("maincpu", 0)
r9685r9686
3848    return 0;
3949}
4050
41static MACHINE_CONFIG_START( clcd, driver_device )
51static MACHINE_CONFIG_START( clcd, clcd_state )
4252    /* basic machine hardware */
4353    MDRV_CPU_ADD("maincpu",M6502, 2000000) // really M65C102
4454    MDRV_CPU_PROGRAM_MAP(clcd_mem)
src/mess/drivers/ti99_4x.c
r9685r9686
4040#include "machine/ti99/mecmouse.h"
4141#include "machine/ti99/handset.h"
4242
43
44class ti99_4x_state : public driver_device
45{
46public:
47   ti99_4x_state(running_machine &machine, const driver_device_config_base &config)
48      : driver_device(machine, config) { }
49
50};
51
52
4353/*
4454    Memory map
4555*/
r9685r9686
784794{
785795}
786796
787static MACHINE_CONFIG_START( ti99_4_60hz, driver_device )
797static MACHINE_CONFIG_START( ti99_4_60hz, ti99_4x_state )
788798   /* basic machine hardware */
789799   /* TMS9900 CPU @ 3.0 MHz */
790800   MDRV_CPU_ADD("maincpu", TMS9900, 3000000)
r9685r9686
834844   MDRV_HANDSET_ADD( "handset", "tms9901" )
835845MACHINE_CONFIG_END
836846
837static MACHINE_CONFIG_START( ti99_4_50hz, driver_device )
847static MACHINE_CONFIG_START( ti99_4_50hz, ti99_4x_state )
838848   /* basic machine hardware */
839849   /* TMS9900 CPU @ 3.0 MHz */
840850   MDRV_CPU_ADD("maincpu", TMS9900, 3000000)
r9685r9686
880890   MDRV_HANDSET_ADD( "handset", "tms9901" )
881891MACHINE_CONFIG_END
882892
883static MACHINE_CONFIG_START( ti99_4a_60hz, driver_device )
893static MACHINE_CONFIG_START( ti99_4a_60hz, ti99_4x_state )
884894   /* basic machine hardware */
885895   /* TMS9900 CPU @ 3.0 MHz */
886896   MDRV_CPU_ADD("maincpu", TMS9900, 3000000)
r9685r9686
924934   MDRV_MECMOUSE_ADD( "mecmouse" )
925935MACHINE_CONFIG_END
926936
927static MACHINE_CONFIG_START( ti99_4a_50hz, driver_device )
937static MACHINE_CONFIG_START( ti99_4a_50hz, ti99_4x_state )
928938   /* basic machine hardware */
929939   /* TMS9900 CPU @ 3.0 MHz */
930940   MDRV_CPU_ADD("maincpu", TMS9900, 3000000)
r9685r9686
979989   v9938_interrupt(timer.machine, 0);
980990}
981991
982static MACHINE_CONFIG_START( ti99_4ev_60hz, driver_device )
992static MACHINE_CONFIG_START( ti99_4ev_60hz, ti99_4x_state )
983993   /* basic machine hardware */
984994   /* TMS9900 CPU @ 3.0 MHz */
985995   MDRV_CPU_ADD("maincpu", TMS9900, 3000000)
src/mess/drivers/sbc6510.c
r9685r9686
2020#include "machine/6526cia.h"
2121#include "sound/ay8910.h"
2222
23
24class sbc6510_state : public driver_device
25{
26public:
27   sbc6510_state(running_machine &machine, const driver_device_config_base &config)
28      : driver_device(machine, config) { }
29
30};
31
32
2333static ADDRESS_MAP_START(sbc6510_mem, ADDRESS_SPACE_PROGRAM, 8)
2434   ADDRESS_MAP_UNMAP_HIGH
2535   AM_RANGE(0x0000, 0xdfff) AM_RAM
r9685r9686
7282   DEVCB_NULL
7383};
7484
75static MACHINE_CONFIG_START( sbc6510, driver_device )
85static MACHINE_CONFIG_START( sbc6510, sbc6510_state )
7686    /* basic machine hardware */
7787    MDRV_CPU_ADD("maincpu",M6510, XTAL_1MHz)
7888   MDRV_CPU_CONFIG( sbc6510_m6510_interface )
src/mess/drivers/bbcbc.c
r9685r9686
1515#include "cpu/z80/z80daisy.h"
1616#include "devices/cartslot.h"
1717
18
19class bbcbc_state : public driver_device
20{
21public:
22   bbcbc_state(running_machine &machine, const driver_device_config_base &config)
23      : driver_device(machine, config) { }
24
25};
26
27
1828#define MAIN_CLOCK XTAL_4_433619MHz
1929
2030
r9685r9686
161171}
162172
163173
164static MACHINE_CONFIG_START( bbcbc, driver_device )
174static MACHINE_CONFIG_START( bbcbc, bbcbc_state )
165175   MDRV_CPU_ADD( "maincpu", Z80, MAIN_CLOCK / 8 )
166176   MDRV_CPU_PROGRAM_MAP( bbcbc_prg)
167177   MDRV_CPU_IO_MAP( bbcbc_io)

Previous 15994 Revisions Next

© 1998-2018 The MESS Team