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r9685 Sunday 28th November, 2010 at 16:34:39 UTC by Nathan Woods
More Atari Ace stuff. [Atari Ace]

[src/mess/drivers]

m20.c mccpm.c mes.c microdec.c mycom.c nanos.c ob68k1a.c palm.c pc2000.c pce220.c pcm.c pimps.c pk8000.c plan80.c pockstat.c prestige.c pv1000.c pv9234.c pyl601.c rx78.c scv.c spc1000.c ssem.c sun1.c ti99_2.c tk80bs.c tm990189.c tricep.c tutor.c tvc.c vt100.c zrt80.c

src/mess/drivers/plan80.c

r9684	r9685
9	9	#include "emu.h"
10	10	#include "cpu/i8085/i8085.h"
11	11
12		static UINT8* plan80_video_ram;
	12
	13	class plan80_state : public driver_device
	14	{
	15	public:
	16	plan80_state(running_machine &machine, const driver_device_config_base &config)
	17	: driver_device(machine, config) { }
	18
	19	UINT8* video_ram;
	20	};
	21
	22
13	23	static ADDRESS_MAP_START(plan80_mem, ADDRESS_SPACE_PROGRAM, 8)
14	24	ADDRESS_MAP_UNMAP_HIGH
15	25	AM_RANGE(0x0000, 0xefff) AM_RAM
16		AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(&plan80_video_ram)
	26	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE_MEMBER(plan80_state, video_ram)
17	27	AM_RANGE(0xf800, 0xffff) AM_ROM
18	28	ADDRESS_MAP_END
19	29
r9684	r9685
36	46
37	47	static VIDEO_UPDATE( plan80 )
38	48	{
	49	plan80_state *state = screen->machine->driver_data<plan80_state>();
39	50	UINT8 *gfx = memory_region(screen->machine, "gfx");
40	51	int x,y,j,b;
41	52	UINT16 addr;
r9684	r9685
45	56	addr = y*64;
46	57	for(x = 0; x < 48; x++ )
47	58	{
48		UINT8 code = plan80_video_ram[addr + x];
	59	UINT8 code = state->video_ram[addr + x];
49	60	for(j = 0; j < 8; j++ )
50	61	{
51	62	UINT8 val = gfx[code*8 + j];
r9684	r9685
79	90	GFXDECODE_END
80	91
81	92
82		static MACHINE_CONFIG_START( plan80, driver_device )
	93	static MACHINE_CONFIG_START( plan80, plan80_state )
83	94	/* basic machine hardware */
84	95	MDRV_CPU_ADD("maincpu",I8080, 2048000)
85	96	MDRV_CPU_PROGRAM_MAP(plan80_mem)

src/mess/drivers/mycom.c

r9684	r9685
56	56	#include "devices/flopdrv.h"
57	57	#include "formats/basicdsk.h"
58	58
59		static running_device *mc6845;
60		static running_device *mycom_audio;
61		static running_device *mycom_cassette;
62		static running_device *mycom_fdc;
63		static UINT8 *vram;
64		static UINT8 *gfx_rom;
65		static UINT16 vram_addr;
66		static UINT8 keyb_press,keyb_press_flag;
67		static UINT8 mycom_0a,sn_we;
68		static UINT32 upper_sw;
69		static UINT8 *RAM;
70	59
	60	class mycom_state : public driver_device
	61	{
	62	public:
	63	mycom_state(running_machine &machine, const driver_device_config_base &config)
	64	: driver_device(machine, config) { }
	65
	66	running_device *mc6845;
	67	running_device *audio;
	68	running_device *cassette;
	69	running_device *fdc;
	70	UINT8 *vram;
	71	UINT8 *gfx_rom;
	72	UINT16 vram_addr;
	73	UINT8 keyb_press;
	74	UINT8 keyb_press_flag;
	75	UINT8 _0a;
	76	UINT8 sn_we;
	77	UINT32 upper_sw;
	78	UINT8 *RAM;
	79	};
	80
	81
	82
71	83	static VIDEO_START( mycom )
72	84	{
73		mc6845 = machine->device("crtc");
74		vram = memory_region(machine, "vram");
75		gfx_rom = memory_region(machine, "gfx");
	85	mycom_state *state = machine->driver_data<mycom_state>();
	86	state->mc6845 = machine->device("crtc");
	87	state->vram = memory_region(machine, "vram");
	88	state->gfx_rom = memory_region(machine, "gfx");
76	89	}
77	90
78	91	static VIDEO_UPDATE( mycom )
79	92	{
80		mc6845_update(mc6845, bitmap, cliprect);
	93	mycom_state *state = screen->machine->driver_data<mycom_state>();
	94	mc6845_update(state->mc6845, bitmap, cliprect);
81	95	return 0;
82	96	}
83	97
84	98	static MC6845_UPDATE_ROW( mycom_update_row )
85	99	{
	100	mycom_state *state = device->machine->driver_data<mycom_state>();
86	101	UINT8 chr,gfx=0,z;
87	102	UINT16 mem,x;
88	103	UINT16 *p = BITMAP_ADDR16(bitmap, y, 0);
89	104
90		if (mycom_0a & 0x40)
	105	if (state->_0a & 0x40)
91	106	{
92	107	for (x = 0; x < x_count; x++)               // lores pixels
93	108	{
94	109	UINT8 dbit=1;
95	110	if (x == cursor_x) dbit=0;
96	111	mem = (ma + x) & 0x7ff;
97		chr = vram[mem];
	112	chr = state->vram[mem];
98	113	z = ra / 3;
99	114	*p++ = BIT( chr, z ) ? dbit: dbit^1;
100	115	*p++ = BIT( chr, z ) ? dbit: dbit^1;
r9684	r9685
118	133	gfx = inv;   // some blank spacing lines
119	134	else
120	135	{
121		chr = vram[mem];
122		gfx = gfx_rom[(chr<<3) | ra] ^ inv;
	136	chr = state->vram[mem];
	137	gfx = state->gfx_rom[(chr<<3) | ra] ^ inv;
123	138	}
124	139
125	140	/* Display a scanline of a character */
r9684	r9685
137	152
138	153	static WRITE8_HANDLER( mycom_00_w )
139	154	{
	155	mycom_state *state = space->machine->driver_data<mycom_state>();
140	156	switch(data)
141	157	{
142	158	case 0x00: memory_set_bank(space->machine, "boot", 1); break;
143	159	case 0x01: memory_set_bank(space->machine, "boot", 0); break;
144		case 0x02: upper_sw = 0x10000; break;
145		case 0x03: upper_sw = 0x0c000; break;
	160	case 0x02: state->upper_sw = 0x10000; break;
	161	case 0x03: state->upper_sw = 0x0c000; break;
146	162	}
147	163	}
148	164
149	165	static READ8_HANDLER( mycom_upper_r )
150	166	{
151		return RAM[offset | upper_sw];
	167	mycom_state *state = space->machine->driver_data<mycom_state>();
	168	return state->RAM[offset | state->upper_sw];
152	169	}
153	170
154	171	static WRITE8_HANDLER( mycom_upper_w )
155	172	{
156		RAM[offset | 0xc000] = data;
	173	mycom_state *state = space->machine->driver_data<mycom_state>();
	174	state->RAM[offset | 0xc000] = data;
157	175	}
158	176
159	177	static READ8_HANDLER( vram_data_r )
160	178	{
161		return vram[vram_addr];
	179	mycom_state *state = space->machine->driver_data<mycom_state>();
	180	return state->vram[state->vram_addr];
162	181	}
163	182
164	183	static WRITE8_HANDLER( vram_data_w )
165	184	{
166		vram[vram_addr] = data;
	185	mycom_state *state = space->machine->driver_data<mycom_state>();
	186	state->vram[state->vram_addr] = data;
167	187	}
168	188
169	189	static ADDRESS_MAP_START(mycom_map, ADDRESS_SPACE_PROGRAM, 8)
r9684	r9685
312	332
313	333	static WRITE8_DEVICE_HANDLER( mycom_04_w )
314	334	{
315		vram_addr = (vram_addr & 0x700) | data;
	335	mycom_state *state = device->machine->driver_data<mycom_state>();
	336	state->vram_addr = (state->vram_addr & 0x700) | data;
316	337
317		sn_we = data;
	338	state->sn_we = data;
318	339	/* doesn't work? */
319	340	//printf(":%X ",data);
320		//if(sn_we)
321		//sn76496_w(mycom_audio, 0, data);
	341	//if(state->sn_we)
	342	//sn76496_w(state->audio, 0, data);
322	343	}
323	344
324	345	static WRITE8_DEVICE_HANDLER( mycom_06_w )
325	346	{
326		vram_addr = (vram_addr & 0x0ff) | ((data & 0x007) << 8);
	347	mycom_state *state = device->machine->driver_data<mycom_state>();
	348	state->vram_addr = (state->vram_addr & 0x0ff) | ((data & 0x007) << 8);
327	349	}
328	350
329	351	static READ8_DEVICE_HANDLER( mycom_08_r )
330	352	{
	353	mycom_state *state = device->machine->driver_data<mycom_state>();
331	354	/*
332	355	x--- ---- display flag
333	356	---- --x- keyboard shift
r9684	r9685
335	358	*/
336	359	UINT8 data = 0;
337	360
338		data = keyb_press_flag; //~keyb_press_flag & 1;
	361	data = state->keyb_press_flag; //~state->keyb_press_flag & 1;
339	362
340		if (cassette_input(mycom_cassette) > 0.03) // not working
	363	if (cassette_input(state->cassette) > 0.03) // not working
341	364	data+=4;
342	365
343	366	return data;
r9684	r9685
356	379
357	380	static READ8_DEVICE_HANDLER( mycom_05_r )
358	381	{
359		return keyb_press;
	382	mycom_state *state = device->machine->driver_data<mycom_state>();
	383	return state->keyb_press;
360	384	}
361	385
362	386	static WRITE8_DEVICE_HANDLER( mycom_0a_w )
363	387	{
	388	mycom_state *state = device->machine->driver_data<mycom_state>();
364	389	/*
365	390	x--- ---- width 80/40 (0 = 80, 1 = 40)
366	391	-x-- ---- video mode (0= tile, 1 = bitmap)
r9684	r9685
372	397	---- ---x printer strobe
373	398	*/
374	399
375		if ((mycom_0a & 8) != (data & 8))
376		cassette_change_state(mycom_cassette,
	400	if ((state->_0a & 8) != (data & 8))
	401	cassette_change_state(state->cassette,
377	402	(data & 8) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED, CASSETTE_MASK_MOTOR);
378	403
379	404	if (data & 8) // motor on
380		cassette_output(mycom_cassette, (data & 4) ? -1.0 : +1.0);
	405	cassette_output(state->cassette, (data & 4) ? -1.0 : +1.0);
381	406
382		if ((data & 0x80) != (mycom_0a & 0x80))
383		mc6845_set_clock(mc6845, (data & 0x80) ? 1008000 : 2016000);
	407	if ((data & 0x80) != (state->_0a & 0x80))
	408	mc6845_set_clock(state->mc6845, (data & 0x80) ? 1008000 : 2016000);
384	409
385		mycom_0a = data;
	410	state->_0a = data;
386	411
387	412	/* Info about sound
388	413	- uses a SN76489N chip at an unknown clock
r9684	r9685
394	419
395	420	// no sound comes out
396	421	if ((data & 0x30)==0)
397		sn76496_w(mycom_audio, 0, sn_we);
	422	sn76496_w(state->audio, 0, state->sn_we);
398	423	}
399	424
400	425	static I8255A_INTERFACE( ppi8255_intf_0 )
r9684	r9685
441	466
442	467	static TIMER_CALLBACK( mycom_kbd )
443	468	{
	469	mycom_state *state = machine->driver_data<mycom_state>();
444	470	UINT8 x, y, scancode = 0;
445	471	UINT16 pressed[9];
446	472	char kbdrow[2];
447	473	UINT8 modifiers = input_port_read(machine, "XX");
448	474	UINT8 shift_pressed = (modifiers & 2) >> 1;
449		keyb_press_flag = 0;
	475	state->keyb_press_flag = 0;
450	476
451	477	/* see what is pressed */
452	478	for (x = 0; x < 9; x++)
r9684	r9685
466	492	if (BIT(pressed[x], y))
467	493	{
468	494	scancode = ((x + y * 9) << 1) + shift_pressed + 1;
469		keyb_press_flag = 1;
470		keyb_press = mycom_keyval[scancode];
	495	state->keyb_press_flag = 1;
	496	state->keyb_press = mycom_keyval[scancode];
471	497	}
472	498	}
473	499	}
474	500	}
475	501
476		if (keyb_press_flag)
	502	if (state->keyb_press_flag)
477	503	{
478		if (modifiers & 1) keyb_press &= 0xbf;
479		if (modifiers & 4) keyb_press |= 0x80;
	504	if (modifiers & 1) state->keyb_press &= 0xbf;
	505	if (modifiers & 4) state->keyb_press |= 0x80;
480	506	}
481	507	}
482	508
483	509	static MACHINE_START(mycom)
484	510	{
485		mycom_audio = machine->device("sn1");
486		mycom_cassette = machine->device("cassette");
487		mycom_fdc = machine->device("fdc");
488		RAM = memory_region(machine, "maincpu");
	511	mycom_state *state = machine->driver_data<mycom_state>();
	512	state->audio = machine->device("sn1");
	513	state->cassette = machine->device("cassette");
	514	state->fdc = machine->device("fdc");
	515	state->RAM = memory_region(machine, "maincpu");
489	516	timer_pulse(machine, ATTOTIME_IN_HZ(20), NULL, 0, mycom_kbd);
490	517	}
491	518
492	519	static MACHINE_RESET(mycom)
493	520	{
	521	mycom_state *state = machine->driver_data<mycom_state>();
494	522	memory_set_bank(machine, "boot", 1);
495		upper_sw = 0x10000;
496		mycom_0a = 0;
	523	state->upper_sw = 0x10000;
	524	state->_0a = 0;
497	525	}
498	526
499	527	static DRIVER_INIT( mycom )
r9684	r9685
502	530	memory_configure_bank(machine, "boot", 0, 2, &RAM[0x0000], 0x10000);
503	531	}
504	532
505		static MACHINE_CONFIG_START( mycom, driver_device )
	533	static MACHINE_CONFIG_START( mycom, mycom_state )
506	534	/* basic machine hardware */
507	535	MDRV_CPU_ADD("maincpu",Z80, XTAL_10MHz / 4)
508	536	MDRV_CPU_PROGRAM_MAP(mycom_map)

src/mess/drivers/spc1000.c

r9684	r9685
15	15	#include "devices/cassette.h"
16	16	#include "devices/messram.h"
17	17
18		static UINT8 IPLK;
19		static UINT8 *spc1000_video_ram;
20		static UINT8 GMODE;
21	18
	19	class spc1000_state : public driver_device
	20	{
	21	public:
	22	spc1000_state(running_machine &machine, const driver_device_config_base &config)
	23	: driver_device(machine, config) { }
	24
	25	UINT8 IPLK;
	26	UINT8 *video_ram;
	27	UINT8 GMODE;
	28	};
	29
	30
	31
22	32	static ADDRESS_MAP_START(spc1000_mem, ADDRESS_SPACE_PROGRAM, 8)
23	33	ADDRESS_MAP_UNMAP_HIGH
24	34	AM_RANGE( 0x0000, 0x7fff ) AM_READ_BANK("bank1") AM_WRITE_BANK("bank2")
r9684	r9685
27	37
28	38	static WRITE8_HANDLER(spc1000_iplk_w)
29	39	{
30		IPLK = IPLK ? 0 : 1;
31		if (IPLK == 1) {
	40	spc1000_state *state = space->machine->driver_data<spc1000_state>();
	41	state->IPLK = state->IPLK ? 0 : 1;
	42	if (state->IPLK == 1) {
32	43	memory_set_bankptr(space->machine, "bank1", memory_region(space->machine, "maincpu"));
33	44	memory_set_bankptr(space->machine, "bank3", memory_region(space->machine, "maincpu"));
34	45	} else {
r9684	r9685
39	50
40	51	static READ8_HANDLER(spc1000_iplk_r)
41	52	{
42		IPLK = IPLK ? 0 : 1;
43		if (IPLK == 1) {
	53	spc1000_state *state = space->machine->driver_data<spc1000_state>();
	54	state->IPLK = state->IPLK ? 0 : 1;
	55	if (state->IPLK == 1) {
44	56	memory_set_bankptr(space->machine, "bank1", memory_region(space->machine, "maincpu"));
45	57	memory_set_bankptr(space->machine, "bank3", memory_region(space->machine, "maincpu"));
46	58	} else {
r9684	r9685
54	66
55	67	static WRITE8_HANDLER(spc1000_video_ram_w)
56	68	{
57		spc1000_video_ram[offset] = data;
	69	spc1000_state *state = space->machine->driver_data<spc1000_state>();
	70	state->video_ram[offset] = data;
58	71	}
59	72
60	73	static READ8_HANDLER(spc1000_video_ram_r)
61	74	{
62		return spc1000_video_ram[offset];
	75	spc1000_state *state = space->machine->driver_data<spc1000_state>();
	76	return state->video_ram[offset];
63	77	}
64	78
65	79	static READ8_HANDLER(spc1000_keyboard_r) {
r9684	r9685
72	86
73	87	static WRITE8_DEVICE_HANDLER(spc1000_gmode_w)
74	88	{
75		GMODE = data;
	89	spc1000_state *state = device->machine->driver_data<spc1000_state>();
	90	state->GMODE = data;
76	91
77		// GMODE layout: CSS|NA|PS2|PS1|~A/G|GM0|GM1|NA
	92	// state->GMODE layout: CSS|NA|PS2|PS1|~A/G|GM0|GM1|NA
78	93	//  [PS2,PS1] is used to set screen 0/1 pages
79	94	mc6847_gm1_w(device, BIT(data, 1));
80	95	mc6847_gm0_w(device, BIT(data, 2));
r9684	r9685
84	99
85	100	static READ8_DEVICE_HANDLER(spc1000_gmode_r)
86	101	{
87		return GMODE;
	102	spc1000_state *state = device->machine->driver_data<spc1000_state>();
	103	return state->GMODE;
88	104	}
89	105
90	106	static ADDRESS_MAP_START( spc1000_io , ADDRESS_SPACE_IO, 8)
r9684	r9685
194	210
195	211	static MACHINE_RESET(spc1000)
196	212	{
	213	spc1000_state *state = machine->driver_data<spc1000_state>();
197	214	address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
198	215
199	216	memory_install_read_bank(space, 0x0000, 0x7fff, 0, 0, "bank1");
r9684	r9685
207	224	memory_set_bankptr(machine, "bank3", memory_region(machine, "maincpu"));
208	225	memory_set_bankptr(machine, "bank4", messram_get_ptr(machine->device("messram")) + 0x8000);
209	226
210		IPLK = 1;
	227	state->IPLK = 1;
211	228	}
212	229
213	230	static READ8_DEVICE_HANDLER( spc1000_mc6847_videoram_r )
214	231	{
215		// GMODE layout: CSS|NA|PS2|PS1|~A/G|GM0|GM1|NA
	232	spc1000_state *state = device->machine->driver_data<spc1000_state>();
	233	// state->GMODE layout: CSS|NA|PS2|PS1|~A/G|GM0|GM1|NA
216	234	//  [PS2,PS1] is used to set screen 0/1 pages
217		if ( !BIT(GMODE, 3) ) {   // text mode (~A/G set to A)
218		unsigned int page = (BIT(GMODE, 5) << 1) | BIT(GMODE, 4);
219		mc6847_inv_w(device, BIT(spc1000_video_ram[offset+page*0x200+0x800], 0));
220		mc6847_css_w(device, BIT(spc1000_video_ram[offset+page*0x200+0x800], 1));
221		mc6847_as_w(device, BIT(spc1000_video_ram[offset+page*0x200+0x800], 2));
222		mc6847_intext_w(device, BIT(spc1000_video_ram[offset+page*0x200+0x800], 3));
223		return spc1000_video_ram[offset+page*0x200];
	235	if ( !BIT(state->GMODE, 3) ) {   // text mode (~A/G set to A)
	236	unsigned int page = (BIT(state->GMODE, 5) << 1) | BIT(state->GMODE, 4);
	237	mc6847_inv_w(device, BIT(state->video_ram[offset+page*0x200+0x800], 0));
	238	mc6847_css_w(device, BIT(state->video_ram[offset+page*0x200+0x800], 1));
	239	mc6847_as_w(device, BIT(state->video_ram[offset+page*0x200+0x800], 2));
	240	mc6847_intext_w(device, BIT(state->video_ram[offset+page*0x200+0x800], 3));
	241	return state->video_ram[offset+page*0x200];
224	242	} else {   // graphics mode: uses full 6KB of VRAM
225		return spc1000_video_ram[offset];
	243	return state->video_ram[offset];
226	244	}
227	245	}
228	246
229	247
230	248	static UINT8 spc1000_get_char_rom(running_machine *machine, UINT8 ch, int line)
231	249	{
232		return spc1000_video_ram[0x1000+(ch&0x7F)*16+line];
	250	spc1000_state *state = machine->driver_data<spc1000_state>();
	251	return state->video_ram[0x1000+(ch&0x7F)*16+line];
233	252	}
234	253
235	254	static VIDEO_START( spc1000 )
236	255	{
237		spc1000_video_ram = auto_alloc_array(machine, UINT8, 0x2000);
	256	spc1000_state *state = machine->driver_data<spc1000_state>();
	257	state->video_ram = auto_alloc_array(machine, UINT8, 0x2000);
238	258	}
239	259
240	260	static VIDEO_UPDATE( spc1000 )
r9684	r9685
274	294	DEVCB_NULL                           // RS (output)
275	295	};
276	296
277		static MACHINE_CONFIG_START( spc1000, driver_device )
	297	static MACHINE_CONFIG_START( spc1000, spc1000_state )
278	298	/* basic machine hardware */
279	299	MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
280	300	MDRV_CPU_PROGRAM_MAP(spc1000_mem)

src/mess/drivers/palm.c

r9684	r9685
16	16	#include "debugger.h"
17	17	#include "devices/messram.h"
18	18
	19
	20	class palm_state : public driver_device
	21	{
	22	public:
	23	palm_state(running_machine &machine, const driver_device_config_base &config)
	24	: driver_device(machine, config) { }
	25
	26	UINT8 port_f_latch;
	27	UINT16 spim_data;
	28	};
	29
19	30	static offs_t palm_dasm_override(device_t &device, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, int options);
20	31
21		static UINT8 port_f_latch;
22		static UINT16 spim_data;
23	32
24	33	/***************************************************************************
25	34	MACHINE HARDWARE
r9684	r9685
49	58
50	59	static WRITE8_DEVICE_HANDLER( palm_port_f_out )
51	60	{
52		port_f_latch = data;
	61	palm_state *state = device->machine->driver_data<palm_state>();
	62	state->port_f_latch = data;
53	63	}
54	64
55	65	static READ8_DEVICE_HANDLER( palm_port_c_in )
r9684	r9685
59	69
60	70	static READ8_DEVICE_HANDLER( palm_port_f_in )
61	71	{
62		return port_f_latch;
	72	palm_state *state = device->machine->driver_data<palm_state>();
	73	return state->port_f_latch;
63	74	}
64	75
65	76	static WRITE16_DEVICE_HANDLER( palm_spim_out )
66	77	{
67		spim_data = data;
	78	palm_state *state = device->machine->driver_data<palm_state>();
	79	state->spim_data = data;
68	80	}
69	81
70	82	static READ16_DEVICE_HANDLER( palm_spim_in )
71	83	{
72		return spim_data;
	84	palm_state *state = device->machine->driver_data<palm_state>();
	85	return state->spim_data;
73	86	}
74	87
75	88	static void palm_spim_exchange( running_device *device )
76	89	{
	90	palm_state *state = device->machine->driver_data<palm_state>();
77	91	UINT8 x = input_port_read(device->machine, "PENX");
78	92	UINT8 y = input_port_read(device->machine, "PENY");
79	93
80		switch( port_f_latch & 0x0f )
	94	switch( state->port_f_latch & 0x0f )
81	95	{
82	96	case 0x06:
83		spim_data = (0xff - x) * 2;
	97	state->spim_data = (0xff - x) * 2;
84	98	break;
85	99
86	100	case 0x09:
87		spim_data = (0xff - y) * 2;
	101	state->spim_data = (0xff - y) * 2;
88	102	break;
89	103	}
90	104	}
91	105
92	106	static MACHINE_START( palm )
93	107	{
	108	palm_state *state = machine->driver_data<palm_state>();
94	109	address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
95	110	memory_install_read_bank (space, 0x000000, messram_get_size(machine->device("messram")) - 1, messram_get_size(machine->device("messram")) - 1, 0, "bank1");
96	111	memory_install_write_bank(space, 0x000000, messram_get_size(machine->device("messram")) - 1, messram_get_size(machine->device("messram")) - 1, 0, "bank1");
97	112	memory_set_bankptr(machine, "bank1", messram_get_ptr(machine->device("messram")));
98	113
99		state_save_register_global(machine, port_f_latch);
100		state_save_register_global(machine, spim_data);
	114	state_save_register_global(machine, state->port_f_latch);
	115	state_save_register_global(machine, state->spim_data);
101	116	if (machine->device<cpu_device>("maincpu")->debug()) {
102	117	machine->device<cpu_device>("maincpu")->debug()->set_dasm_override(palm_dasm_override);
103	118	}
r9684	r9685
171	186	};
172	187
173	188
174		static MACHINE_CONFIG_START( palm, driver_device )
	189	static MACHINE_CONFIG_START( palm, palm_state )
175	190
176	191	/* basic machine hardware */
177	192	MDRV_CPU_ADD( "maincpu", M68000, 32768*506 )        /* 16.580608 MHz */

src/mess/drivers/tm990189.c

r9684	r9685
47	47	#include "sound/wave.h"
48	48	#include "machine/serial.h"
49	49
50		static int load_state;
51		static int ic_state;
52	50
53		static int digitsel;
54		static int segment;
	51	class tm990189_state : public driver_device
	52	{
	53	public:
	54	tm990189_state(running_machine &machine, const driver_device_config_base &config)
	55	: driver_device(machine, config) { }
55	56
56		static emu_timer *displayena_timer;
	57	int load_state;
	58	int ic_state;
	59	int digitsel;
	60	int segment;
	61	emu_timer *displayena_timer;
	62	UINT8 segment_state[10];
	63	UINT8 old_segment_state[10];
	64	UINT8 LED_state;
	65	emu_timer *joy1x_timer;
	66	emu_timer *joy1y_timer;
	67	emu_timer *joy2x_timer;
	68	emu_timer *joy2y_timer;
	69	int LED_display_window_left;
	70	int LED_display_window_top;
	71	int LED_display_window_width;
	72	int LED_display_window_height;
	73	device_image_interface *rs232_fp;
	74	UINT8 rs232_rts;
	75	emu_timer *rs232_input_timer;
	76	};
	77
	78
	79
	80
57	81	#define displayena_duration ATTOTIME_IN_USEC(4500)   /* Can anyone confirm this? 74LS123 connected to C=0.1uF and R=100kOhm */
58		static UINT8 segment_state[10];
59		static UINT8 old_segment_state[10];
60		static UINT8 LED_state;
61	82
62		static emu_timer *joy1x_timer;
63		static emu_timer *joy1y_timer;
64		static emu_timer *joy2x_timer;
65		static emu_timer *joy2y_timer;
66	83
67	84	enum
68	85	{
r9684	r9685
74	91	0xFF,0x00,0x00   /* red for LEDs */
75	92	};
76	93
77		static int LED_display_window_left;
78		static int LED_display_window_top;
79		static int LED_display_window_width;
80		static int LED_display_window_height;
81	94
82	95	static void hold_load(running_machine *machine);
83	96
84	97
85		static device_image_interface *rs232_fp;
86		static UINT8 rs232_rts;
87		static emu_timer *rs232_input_timer;
88	98
89	99	static MACHINE_RESET( tm990_189 )
90	100	{
r9684	r9685
93	103
94	104	static MACHINE_START( tm990_189 )
95	105	{
96		displayena_timer = timer_alloc(machine, NULL, NULL);
	106	tm990189_state *state = machine->driver_data<tm990189_state>();
	107	state->displayena_timer = timer_alloc(machine, NULL, NULL);
97	108	}
98	109	static const TMS9928a_interface tms9918_interface =
99	110	{
r9684	r9685
105	116
106	117	static MACHINE_START( tm990_189_v )
107	118	{
	119	tm990189_state *state = machine->driver_data<tm990189_state>();
108	120	TMS9928A_configure(&tms9918_interface);
109	121
110		displayena_timer = timer_alloc(machine, NULL, NULL);
	122	state->displayena_timer = timer_alloc(machine, NULL, NULL);
111	123
112		joy1x_timer = timer_alloc(machine, NULL, NULL);
113		joy1y_timer = timer_alloc(machine, NULL, NULL);
114		joy2x_timer = timer_alloc(machine, NULL, NULL);
115		joy2y_timer = timer_alloc(machine, NULL, NULL);
	124	state->joy1x_timer = timer_alloc(machine, NULL, NULL);
	125	state->joy1y_timer = timer_alloc(machine, NULL, NULL);
	126	state->joy2x_timer = timer_alloc(machine, NULL, NULL);
	127	state->joy2y_timer = timer_alloc(machine, NULL, NULL);
116	128	}
117	129
118	130	static MACHINE_RESET( tm990_189_v )
r9684	r9685
141	153
142	154	static VIDEO_EOF( tm990_189 )
143	155	{
	156	tm990189_state *state = machine->driver_data<tm990189_state>();
144	157	int i;
145	158
146	159	for (i=0; i<10; i++)
147		segment_state[i] = 0;
	160	state->segment_state[i] = 0;
148	161	}
149	162
150		INLINE void draw_digit(void)
	163	INLINE void draw_digit(tm990189_state *state)
151	164	{
152		segment_state[digitsel] |= ~segment;
	165	state->segment_state[state->digitsel] |= ~state->segment;
153	166	}
154	167
155		static void update_common(bitmap_t *bitmap,
	168	static void update_common(running_machine *machine, bitmap_t *bitmap,
156	169	int display_x, int display_y,
157	170	int LED14_x, int LED14_y,
158	171	int LED56_x, int LED56_y,
159	172	int LED7_x, int LED7_y,
160	173	pen_t fore_color, pen_t back_color)
161	174	{
	175	tm990189_state *state = machine->driver_data<tm990189_state>();
162	176	int i, j;
163	177	static const struct{ int x, y; int w, h; } bounds[8] =
164	178	{
r9684	r9685
174	188
175	189	for (i=0; i<10; i++)
176	190	{
177		old_segment_state[i] |= segment_state[i];
	191	state->old_segment_state[i] |= state->segment_state[i];
178	192
179	193	for (j=0; j<8; j++)
180	194	plot_box(bitmap, display_x + i*16 + bounds[j].x, display_y + bounds[j].y,
181	195	bounds[j].w, bounds[j].h,
182		(old_segment_state[i] & (1 << j)) ? fore_color : back_color);
	196	(state->old_segment_state[i] & (1 << j)) ? fore_color : back_color);
183	197
184		old_segment_state[i] = segment_state[i];
	198	state->old_segment_state[i] = state->segment_state[i];
185	199	}
186	200
187	201	for (i=0; i<4; i++)
188	202	{
189	203	plot_box(bitmap, LED14_x + 48+4 - i*16, LED14_y + 4, 8, 8,
190		(LED_state & (1 << i)) ? fore_color : back_color);
	204	(state->LED_state & (1 << i)) ? fore_color : back_color);
191	205	}
192	206
193	207	plot_box(bitmap, LED7_x+4, LED7_y+4, 8, 8,
194		(LED_state & 0x10) ? fore_color : back_color);
	208	(state->LED_state & 0x10) ? fore_color : back_color);
195	209
196	210	plot_box(bitmap, LED56_x+16+4, LED56_y+4, 8, 8,
197		(LED_state & 0x20) ? fore_color : back_color);
	211	(state->LED_state & 0x20) ? fore_color : back_color);
198	212
199	213	plot_box(bitmap, LED56_x+4, LED56_y+4, 8, 8,
200		(LED_state & 0x40) ? fore_color : back_color);
	214	(state->LED_state & 0x40) ? fore_color : back_color);
201	215	}
202	216
203	217	static VIDEO_UPDATE( tm990_189 )
204	218	{
205		update_common(bitmap, 580, 150, 110, 508, 387, 456, 507, 478, 1, 0);
	219	update_common(screen->machine, bitmap, 580, 150, 110, 508, 387, 456, 507, 478, 1, 0);
206	220	return 0;
207	221	}
208	222
209	223	static VIDEO_START( tm990_189_v )
210	224	{
	225	tm990189_state *state = machine->driver_data<tm990189_state>();
211	226	screen_device *screen = screen_first(*machine);
212	227	const rectangle &visarea = screen->visible_area();
213	228
214	229	/* NPW 27-Feb-2006 - ewwww gross!!! maybe this can be fixed when
215	230	* multimonitor support is added?*/
216		LED_display_window_left = visarea.min_x;
217		LED_display_window_top = visarea.max_y - 32;
218		LED_display_window_width = visarea.max_x - visarea.min_x;
219		LED_display_window_height = 32;
	231	state->LED_display_window_left = visarea.min_x;
	232	state->LED_display_window_top = visarea.max_y - 32;
	233	state->LED_display_window_width = visarea.max_x - visarea.min_x;
	234	state->LED_display_window_height = 32;
220	235	}
221	236
222	237	static VIDEO_UPDATE( tm990_189_v )
223	238	{
	239	tm990189_state *state = screen->machine->driver_data<tm990189_state>();
224	240	VIDEO_UPDATE_CALL(tms9928a);
225	241
226		plot_box(bitmap, LED_display_window_left, LED_display_window_top, LED_display_window_width, LED_display_window_height, screen->machine->pens[1]);
227		update_common(bitmap,
228		LED_display_window_left, LED_display_window_top,
229		LED_display_window_left, LED_display_window_top+16,
230		LED_display_window_left+80, LED_display_window_top+16,
231		LED_display_window_left+128, LED_display_window_top+16,
	242	plot_box(bitmap, state->LED_display_window_left, state->LED_display_window_top, state->LED_display_window_width, state->LED_display_window_height, screen->machine->pens[1]);
	243	update_common(screen->machine, bitmap,
	244	state->LED_display_window_left, state->LED_display_window_top,
	245	state->LED_display_window_left, state->LED_display_window_top+16,
	246	state->LED_display_window_left+80, state->LED_display_window_top+16,
	247	state->LED_display_window_left+128, state->LED_display_window_top+16,
232	248	6, 1);
233	249	return 0;
234	250	}
r9684	r9685
239	255
240	256	static void field_interrupts(running_machine *machine)
241	257	{
242		if (load_state)
	258	tm990189_state *state = machine->driver_data<tm990189_state>();
	259	if (state->load_state)
243	260	cputag_set_input_line_and_vector(machine, "maincpu", 0, ASSERT_LINE, 2);
244	261	else
245		cputag_set_input_line_and_vector(machine, "maincpu", 0, ASSERT_LINE, ic_state);
	262	cputag_set_input_line_and_vector(machine, "maincpu", 0, ASSERT_LINE, state->ic_state);
246	263	}
247	264
248	265	/*
r9684	r9685
251	268
252	269	static TIMER_CALLBACK(clear_load)
253	270	{
254		load_state = FALSE;
	271	tm990189_state *state = machine->driver_data<tm990189_state>();
	272	state->load_state = FALSE;
255	273	field_interrupts(machine);
256	274	}
257	275
258	276	static void hold_load(running_machine *machine)
259	277	{
260		load_state = TRUE;
	278	tm990189_state *state = machine->driver_data<tm990189_state>();
	279	state->load_state = TRUE;
261	280	field_interrupts(machine);
262	281	timer_set(machine, ATTOTIME_IN_MSEC(100), NULL, 0, clear_load);
263	282	}
r9684	r9685
268	287
269	288	static TMS9901_INT_CALLBACK ( usr9901_interrupt_callback )
270	289	{
271		ic_state = ic & 7;
	290	tm990189_state *state = device->machine->driver_data<tm990189_state>();
	291	state->ic_state = ic & 7;
272	292
273		if (!load_state)
	293	if (!state->load_state)
274	294	field_interrupts(device->machine);
275	295	}
276	296
277	297	static WRITE8_DEVICE_HANDLER( usr9901_led_w )
278	298	{
	299	tm990189_state *state = device->machine->driver_data<tm990189_state>();
279	300	if (data)
280		LED_state |= (1 << offset);
	301	state->LED_state |= (1 << offset);
281	302	else
282		LED_state &= ~(1 << offset);
	303	state->LED_state &= ~(1 << offset);
283	304	}
284	305
285	306	static TMS9901_INT_CALLBACK( sys9901_interrupt_callback )
r9684	r9685
291	312
292	313	static READ8_DEVICE_HANDLER( sys9901_r0 )
293	314	{
	315	tm990189_state *state = device->machine->driver_data<tm990189_state>();
294	316	int reply = 0x00;
295	317	static const char *const keynames[] = { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7", "LINE8" };
296	318
297	319	/* keyboard read */
298		if (digitsel < 9)
299		reply |= input_port_read(device->machine, keynames[digitsel]) << 1;
	320	if (state->digitsel < 9)
	321	reply |= input_port_read(device->machine, keynames[state->digitsel]) << 1;
300	322
301	323	/* tape input */
302	324	if (cassette_input(device->machine->device("cassette")) > 0.0)
r9684	r9685
307	329
308	330	static WRITE8_DEVICE_HANDLER( sys9901_digitsel_w )
309	331	{
	332	tm990189_state *state = device->machine->driver_data<tm990189_state>();
310	333	if (data)
311		digitsel |= 1 << offset;
	334	state->digitsel |= 1 << offset;
312	335	else
313		digitsel &= ~ (1 << offset);
	336	state->digitsel &= ~ (1 << offset);
314	337	}
315	338
316	339	static WRITE8_DEVICE_HANDLER( sys9901_segment_w )
317	340	{
	341	tm990189_state *state = device->machine->driver_data<tm990189_state>();
318	342	if (data)
319		segment |= 1 << (offset-4);
	343	state->segment |= 1 << (offset-4);
320	344	else
321	345	{
322		segment &= ~ (1 << (offset-4));
323		if ((attotime_compare(timer_timeleft(displayena_timer), attotime_zero) > 0) && (digitsel < 10))
324		draw_digit();
	346	state->segment &= ~ (1 << (offset-4));
	347	if ((attotime_compare(timer_timeleft(state->displayena_timer), attotime_zero) > 0) && (state->digitsel < 10))
	348	draw_digit(state);
325	349	}
326	350	}
327	351
328	352	static WRITE8_DEVICE_HANDLER( sys9901_dsplytrgr_w )
329	353	{
330		if ((!data) && (digitsel < 10))
	354	tm990189_state *state = device->machine->driver_data<tm990189_state>();
	355	if ((!data) && (state->digitsel < 10))
331	356	{
332		timer_reset(displayena_timer, displayena_duration);
333		draw_digit();
	357	timer_reset(state->displayena_timer, displayena_duration);
	358	draw_digit(state);
334	359	}
335	360	}
336	361
337	362	static WRITE8_DEVICE_HANDLER( sys9901_shiftlight_w )
338	363	{
	364	tm990189_state *state = device->machine->driver_data<tm990189_state>();
339	365	if (data)
340		LED_state |= 0x10;
	366	state->LED_state |= 0x10;
341	367	else
342		LED_state &= ~0x10;
	368	state->LED_state &= ~0x10;
343	369	}
344	370
345	371	static WRITE8_DEVICE_HANDLER( sys9901_spkrdrive_w )
r9684	r9685
359	385
360	386	static TIMER_CALLBACK(rs232_input_callback)
361	387	{
	388	//tm990189_state *state = machine->driver_data<tm990189_state>();
362	389	UINT8 buf;
363	390	device_image_interface *image = (device_image_interface *)(ptr);
364		if (/*rs232_rts &&*/ /*(mame_ftell(rs232_fp) < mame_fsize(rs232_fp))*/1)
	391	if (/*state->rs232_rts &&*/ /*(mame_ftell(state->rs232_fp) < mame_fsize(state->rs232_fp))*/1)
365	392	{
366	393	if (image->fread(&buf, 1) == 1)
367	394	tms9902_push_data(machine->device("tms9902"), buf);
r9684	r9685
373	400	*/
374	401	static DEVICE_IMAGE_LOAD( tm990_189_rs232 )
375	402	{
	403	tm990189_state *state = image.device().machine->driver_data<tm990189_state>();
376	404	tms9902_set_dsr(image.device().machine->device("tms9902"), 1);
377		rs232_input_timer = timer_alloc(image.device().machine, rs232_input_callback, (void*)image);
378		timer_adjust_periodic(rs232_input_timer, attotime_zero, 0, ATTOTIME_IN_MSEC(10));
	405	state->rs232_input_timer = timer_alloc(image.device().machine, rs232_input_callback, (void*)image);
	406	timer_adjust_periodic(state->rs232_input_timer, attotime_zero, 0, ATTOTIME_IN_MSEC(10));
379	407
380	408	return IMAGE_INIT_PASS;
381	409	}
r9684	r9685
385	413	*/
386	414	static DEVICE_IMAGE_UNLOAD( tm990_189_rs232 )
387	415	{
	416	tm990189_state *state = image.device().machine->driver_data<tm990189_state>();
388	417	tms9902_set_dsr(image.device().machine->device("tms9902"), 0);
389	418
390		timer_reset(rs232_input_timer, attotime_never);   /* FIXME - timers should only be allocated once */
	419	timer_reset(state->rs232_input_timer, attotime_never);   /* FIXME - timers should only be allocated once */
391	420	}
392	421
393	422	DEVICE_GET_INFO( tm990_189_rs232 )
r9684	r9685
414	443
415	444	static TMS9902_RST_CALLBACK( rts_callback )
416	445	{
417		rs232_rts = RTS;
	446	tm990189_state *state = device->machine->driver_data<tm990189_state>();
	447	state->rs232_rts = RTS;
418	448	tms9902_set_cts(device, RTS);
419	449	}
420	450
421	451	static TMS9902_XMIT_CALLBACK( xmit_callback )
422	452	{
	453	tm990189_state *state = device->machine->driver_data<tm990189_state>();
423	454	UINT8 buf = data;
424	455
425		if (rs232_fp)
426		rs232_fp->fwrite(&buf, 1);
	456	if (state->rs232_fp)
	457	state->rs232_fp->fwrite(&buf, 1);
427	458	}
428	459
429	460	/*
r9684	r9685
432	463
433	464	static WRITE8_HANDLER(ext_instr_decode)
434	465	{
	466	tm990189_state *state = space->machine->driver_data<tm990189_state>();
435	467	int ext_op_ID;
436	468
437	469	ext_op_ID = ((offset+0x800) >> 11) & 0x3;
r9684	r9685
446	478	break;
447	479
448	480	case 5: /* CKON: set DECKCONTROL */
449		LED_state |= 0x20;
	481	state->LED_state |= 0x20;
450	482	{
451	483	running_device *img = space->machine->device("cassette");
452	484	cassette_change_state(img, CASSETTE_MOTOR_ENABLED, CASSETTE_MASK_MOTOR);
r9684	r9685
454	486	break;
455	487
456	488	case 6: /* CKOF: clear DECKCONTROL */
457		LED_state &= ~0x20;
	489	state->LED_state &= ~0x20;
458	490	{
459	491	running_device *img = space->machine->device("cassette");
460	492	cassette_change_state(img, CASSETTE_MOTOR_DISABLED, CASSETTE_MASK_MOTOR);
r9684	r9685
469	501
470	502	static void idle_callback(running_device *device, int state)
471	503	{
	504	tm990189_state *drvstate = device->machine->driver_data<tm990189_state>();
472	505	if (state)
473		LED_state |= 0x40;
	506	drvstate->LED_state |= 0x40;
474	507	else
475		LED_state &= ~0x40;
	508	drvstate->LED_state &= ~0x40;
476	509	}
477	510
478	511	/*
r9684	r9685
524	557
525	558	static READ8_HANDLER(video_joy_r)
526	559	{
	560	tm990189_state *state = space->machine->driver_data<tm990189_state>();
527	561	int reply = input_port_read(space->machine, "BUTTONS");
528	562
529	563
530		if (attotime_compare(timer_timeleft(joy1x_timer), attotime_zero) < 0)
	564	if (attotime_compare(timer_timeleft(state->joy1x_timer), attotime_zero) < 0)
531	565	reply |= 0x01;
532	566
533		if (attotime_compare(timer_timeleft(joy1y_timer), attotime_zero) < 0)
	567	if (attotime_compare(timer_timeleft(state->joy1y_timer), attotime_zero) < 0)
534	568	reply |= 0x02;
535	569
536		if (attotime_compare(timer_timeleft(joy2x_timer), attotime_zero) < 0)
	570	if (attotime_compare(timer_timeleft(state->joy2x_timer), attotime_zero) < 0)
537	571	reply |= 0x08;
538	572
539		if (attotime_compare(timer_timeleft(joy2y_timer), attotime_zero) < 0)
	573	if (attotime_compare(timer_timeleft(state->joy2y_timer), attotime_zero) < 0)
540	574	reply |= 0x10;
541	575
542	576	return reply;
r9684	r9685
544	578
545	579	static WRITE8_HANDLER(video_joy_w)
546	580	{
547		timer_reset(joy1x_timer, ATTOTIME_IN_USEC(input_port_read(space->machine, "JOY1_X")*28+28));
548		timer_reset(joy1y_timer, ATTOTIME_IN_USEC(input_port_read(space->machine, "JOY1_Y")*28+28));
549		timer_reset(joy2x_timer, ATTOTIME_IN_USEC(input_port_read(space->machine, "JOY2_X")*28+28));
550		timer_reset(joy2y_timer, ATTOTIME_IN_USEC(input_port_read(space->machine, "JOY2_Y")*28+28));
	581	tm990189_state *state = space->machine->driver_data<tm990189_state>();
	582	timer_reset(state->joy1x_timer, ATTOTIME_IN_USEC(input_port_read(space->machine, "JOY1_X")*28+28));
	583	timer_reset(state->joy1y_timer, ATTOTIME_IN_USEC(input_port_read(space->machine, "JOY1_Y")*28+28));
	584	timer_reset(state->joy2x_timer, ATTOTIME_IN_USEC(input_port_read(space->machine, "JOY2_X")*28+28));
	585	timer_reset(state->joy2y_timer, ATTOTIME_IN_USEC(input_port_read(space->machine, "JOY2_Y")*28+28));
551	586	}
552	587
553	588	/* user tms9901 setup */
r9684	r9685
754	789	idle_callback
755	790	};
756	791
757		static MACHINE_CONFIG_START( tm990_189, driver_device )
	792	static MACHINE_CONFIG_START( tm990_189, tm990189_state )
758	793	/* basic machine hardware */
759	794	/* TMS9980 CPU @ 2.0 MHz */
760	795	MDRV_CPU_ADD("maincpu", TMS9980, 2000000)
r9684	r9685
805	840	#define TOP_BORDER_60HZ      27
806	841	#define BOTTOM_BORDER_60HZ   24
807	842
808		static MACHINE_CONFIG_START( tm990_189_v, driver_device )
	843	static MACHINE_CONFIG_START( tm990_189_v, tm990189_state )
809	844	/* basic machine hardware */
810	845	/* TMS9980 CPU @ 2.0 MHz */
811	846	MDRV_CPU_ADD("maincpu", TMS9980, 2000000)

src/mess/drivers/m20.c

r9684	r9685
19	19	#include "cpu/i86/i86.h"
20	20	#include "video/mc6845.h"
21	21
	22
	23	class m20_state : public driver_device
	24	{
	25	public:
	26	m20_state(running_machine &machine, const driver_device_config_base &config)
	27	: driver_device(machine, config) { }
	28
	29	UINT16 *vram;
	30	};
	31
	32
22	33	#define MAIN_CLOCK 4000000 /* 4 MHz */
23	34	#define PIXEL_CLOCK XTAL_4_433619MHz
24	35
25		static UINT16 *m20_vram;
26	36
27	37	static VIDEO_START( m20 )
28	38	{
r9684	r9685
30	40
31	41	static VIDEO_UPDATE( m20 )
32	42	{
	43	m20_state *state = screen->machine->driver_data<m20_state>();
33	44	int x,y,i;
34	45	UINT8 pen;
35	46	UINT32 count;
r9684	r9685
44	55	{
45	56	for (i = 0; i < 16; i++)
46	57	{
47		pen = (m20_vram[count]) >> (15 - i) & 1;
	58	pen = (state->vram[count]) >> (15 - i) & 1;
48	59
49	60	if ((x + i) <= screen->visible_area().max_x && (y + 0) < screen->visible_area().max_y)
50	61	*BITMAP_ADDR32(bitmap, y, x + i) = screen->machine->pens[pen];
r9684	r9685
61	72	AM_RANGE( 0x00000, 0x01fff ) AM_ROM AM_REGION("maincpu",0x10000)
62	73	AM_RANGE( 0x40000, 0x41fff ) AM_ROM AM_REGION("maincpu",0x10000) //mirror
63	74
64		AM_RANGE( 0x30000, 0x33fff ) AM_RAM AM_BASE(&m20_vram)//base vram
	75	AM_RANGE( 0x30000, 0x33fff ) AM_RAM AM_BASE_MEMBER(m20_state, vram)//base vram
65	76	//  AM_RANGE( 0x34000, 0x37fff ) AM_RAM //extra vram for bitmap mode
66	77	//  AM_RANGE( 0x20000, 0x2???? ) //work RAM?
67	78	//
r9684	r9685
136	147	NULL      /* update address callback */
137	148	};
138	149
139		static MACHINE_CONFIG_START( m20, driver_device )
	150	static MACHINE_CONFIG_START( m20, m20_state )
140	151	/* basic machine hardware */
141	152	MDRV_CPU_ADD("maincpu", Z8001, MAIN_CLOCK)
142	153	MDRV_CPU_PROGRAM_MAP(m20_mem)

src/mess/drivers/ssem.c

r9684	r9685
9	9	#include "devices/cartslot.h"
10	10	#include <stdarg.h>
11	11
12		static UINT8 *store;
13		static UINT8 store_line = 0;
14	12
	13	class ssem_state : public driver_device
	14	{
	15	public:
	16	ssem_state(running_machine &machine, const driver_device_config_base &config)
	17	: driver_device(machine, config) { }
	18
	19	UINT8 *store;
	20	UINT8 store_line;
	21	};
	22
	23
	24
15	25	/****************************************************\
16	26	* General helper functions                           *
17	27	\****************************************************/
r9684	r9685
42	52	\****************************************************/
43	53
44	54	static ADDRESS_MAP_START( ssem_map, ADDRESS_SPACE_PROGRAM, 8 )
45		AM_RANGE(0x00, 0x7f) AM_RAM AM_BASE(&store)// Primary store
	55	AM_RANGE(0x00, 0x7f) AM_RAM AM_BASE_MEMBER(ssem_state, store)// Primary store
46	56	ADDRESS_MAP_END
47	57
48	58	/****************************************************\
r9684	r9685
69	79
70	80	static INPUT_CHANGED( panel_check )
71	81	{
	82	ssem_state *state = field->port->machine->driver_data<ssem_state>();
72	83	UINT8 edit0_state = input_port_read(field->port->machine, "EDIT0");
73	84	UINT8 edit1_state = input_port_read(field->port->machine, "EDIT1");
74	85	UINT8 edit2_state = input_port_read(field->port->machine, "EDIT2");
r9684	r9685
79	90	switch( (int)(FPTR)param )
80	91	{
81	92	case PANEL_BIT0:
82		if(edit0_state & 0x01) store[(store_line << 2) | 0] ^= 0x80;
	93	if(edit0_state & 0x01) state->store[(state->store_line << 2) | 0] ^= 0x80;
83	94	break;
84	95	case PANEL_BIT1:
85		if(edit0_state & 0x02) store[(store_line << 2) | 0] ^= 0x40;
	96	if(edit0_state & 0x02) state->store[(state->store_line << 2) | 0] ^= 0x40;
86	97	break;
87	98	case PANEL_BIT2:
88		if(edit0_state & 0x04) store[(store_line << 2) | 0] ^= 0x20;
	99	if(edit0_state & 0x04) state->store[(state->store_line << 2) | 0] ^= 0x20;
89	100	break;
90	101	case PANEL_BIT3:
91		if(edit0_state & 0x08) store[(store_line << 2) | 0] ^= 0x10;
	102	if(edit0_state & 0x08) state->store[(state->store_line << 2) | 0] ^= 0x10;
92	103	break;
93	104	case PANEL_BIT4:
94		if(edit0_state & 0x10) store[(store_line << 2) | 0] ^= 0x08;
	105	if(edit0_state & 0x10) state->store[(state->store_line << 2) | 0] ^= 0x08;
95	106	break;
96	107	case PANEL_BIT5:
97		if(edit0_state & 0x20) store[(store_line << 2) | 0] ^= 0x04;
	108	if(edit0_state & 0x20) state->store[(state->store_line << 2) | 0] ^= 0x04;
98	109	break;
99	110	case PANEL_BIT6:
100		if(edit0_state & 0x40) store[(store_line << 2) | 0] ^= 0x02;
	111	if(edit0_state & 0x40) state->store[(state->store_line << 2) | 0] ^= 0x02;
101	112	break;
102	113	case PANEL_BIT7:
103		if(edit0_state & 0x80) store[(store_line << 2) | 0] ^= 0x01;
	114	if(edit0_state & 0x80) state->store[(state->store_line << 2) | 0] ^= 0x01;
104	115	break;
105	116	case PANEL_BIT8:
106		if(edit1_state & 0x01) store[(store_line << 2) | 1] ^= 0x80;
	117	if(edit1_state & 0x01) state->store[(state->store_line << 2) | 1] ^= 0x80;
107	118	break;
108	119	case PANEL_BIT9:
109		if(edit1_state & 0x02) store[(store_line << 2) | 1] ^= 0x40;
	120	if(edit1_state & 0x02) state->store[(state->store_line << 2) | 1] ^= 0x40;
110	121	break;
111	122	case PANEL_BIT10:
112		if(edit1_state & 0x04) store[(store_line << 2) | 1] ^= 0x20;
	123	if(edit1_state & 0x04) state->store[(state->store_line << 2) | 1] ^= 0x20;
113	124	break;
114	125	case PANEL_BIT11:
115		if(edit1_state & 0x08) store[(store_line << 2) | 1] ^= 0x10;
	126	if(edit1_state & 0x08) state->store[(state->store_line << 2) | 1] ^= 0x10;
116	127	break;
117	128	case PANEL_BIT12:
118		if(edit1_state & 0x10) store[(store_line << 2) | 1] ^= 0x08;
	129	if(edit1_state & 0x10) state->store[(state->store_line << 2) | 1] ^= 0x08;
119	130	break;
120	131	case PANEL_BIT13:
121		if(edit1_state & 0x20) store[(store_line << 2) | 1] ^= 0x04;
	132	if(edit1_state & 0x20) state->store[(state->store_line << 2) | 1] ^= 0x04;
122	133	break;
123	134	case PANEL_BIT14:
124		if(edit1_state & 0x40) store[(store_line << 2) | 1] ^= 0x02;
	135	if(edit1_state & 0x40) state->store[(state->store_line << 2) | 1] ^= 0x02;
125	136	break;
126	137	case PANEL_BIT15:
127		if(edit1_state & 0x80) store[(store_line << 2) | 1] ^= 0x01;
	138	if(edit1_state & 0x80) state->store[(state->store_line << 2) | 1] ^= 0x01;
128	139	break;
129	140	case PANEL_BIT16:
130		if(edit2_state & 0x01) store[(store_line << 2) | 2] ^= 0x80;
	141	if(edit2_state & 0x01) state->store[(state->store_line << 2) | 2] ^= 0x80;
131	142	break;
132	143	case PANEL_BIT17:
133		if(edit2_state & 0x02) store[(store_line << 2) | 2] ^= 0x40;
	144	if(edit2_state & 0x02) state->store[(state->store_line << 2) | 2] ^= 0x40;
134	145	break;
135	146	case PANEL_BIT18:
136		if(edit2_state & 0x04) store[(store_line << 2) | 2] ^= 0x20;
	147	if(edit2_state & 0x04) state->store[(state->store_line << 2) | 2] ^= 0x20;
137	148	break;
138	149	case PANEL_BIT19:
139		if(edit2_state & 0x08) store[(store_line << 2) | 2] ^= 0x10;
	150	if(edit2_state & 0x08) state->store[(state->store_line << 2) | 2] ^= 0x10;
140	151	break;
141	152	case PANEL_BIT20:
142		if(edit2_state & 0x10) store[(store_line << 2) | 2] ^= 0x08;
	153	if(edit2_state & 0x10) state->store[(state->store_line << 2) | 2] ^= 0x08;
143	154	break;
144	155	case PANEL_BIT21:
145		if(edit2_state & 0x20) store[(store_line << 2) | 2] ^= 0x04;
	156	if(edit2_state & 0x20) state->store[(state->store_line << 2) | 2] ^= 0x04;
146	157	break;
147	158	case PANEL_BIT22:
148		if(edit2_state & 0x40) store[(store_line << 2) | 2] ^= 0x02;
	159	if(edit2_state & 0x40) state->store[(state->store_line << 2) | 2] ^= 0x02;
149	160	break;
150	161	case PANEL_BIT23:
151		if(edit2_state & 0x80) store[(store_line << 2) | 2] ^= 0x01;
	162	if(edit2_state & 0x80) state->store[(state->store_line << 2) | 2] ^= 0x01;
152	163	break;
153	164	case PANEL_BIT24:
154		if(edit3_state & 0x01) store[(store_line << 2) | 3] ^= 0x80;
	165	if(edit3_state & 0x01) state->store[(state->store_line << 2) | 3] ^= 0x80;
155	166	break;
156	167	case PANEL_BIT25:
157		if(edit3_state & 0x02) store[(store_line << 2) | 3] ^= 0x40;
	168	if(edit3_state & 0x02) state->store[(state->store_line << 2) | 3] ^= 0x40;
158	169	break;
159	170	case PANEL_BIT26:
160		if(edit3_state & 0x04) store[(store_line << 2) | 3] ^= 0x20;
	171	if(edit3_state & 0x04) state->store[(state->store_line << 2) | 3] ^= 0x20;
161	172	break;
162	173	case PANEL_BIT27:
163		if(edit3_state & 0x08) store[(store_line << 2) | 3] ^= 0x10;
	174	if(edit3_state & 0x08) state->store[(state->store_line << 2) | 3] ^= 0x10;
164	175	break;
165	176	case PANEL_BIT28:
166		if(edit3_state & 0x10) store[(store_line << 2) | 3] ^= 0x08;
	177	if(edit3_state & 0x10) state->store[(state->store_line << 2) | 3] ^= 0x08;
167	178	break;
168	179	case PANEL_BIT29:
169		if(edit3_state & 0x20) store[(store_line << 2) | 3] ^= 0x04;
	180	if(edit3_state & 0x20) state->store[(state->store_line << 2) | 3] ^= 0x04;
170	181	break;
171	182	case PANEL_BIT30:
172		if(edit3_state & 0x40) store[(store_line << 2) | 3] ^= 0x02;
	183	if(edit3_state & 0x40) state->store[(state->store_line << 2) | 3] ^= 0x02;
173	184	break;
174	185	case PANEL_BIT31:
175		if(edit3_state & 0x80) store[(store_line << 2) | 3] ^= 0x01;
	186	if(edit3_state & 0x80) state->store[(state->store_line << 2) | 3] ^= 0x01;
176	187	break;
177	188	case PANEL_LNUP:
178	189	if(misc_state & 0x01)
179	190	{
180		store_line--;
	191	state->store_line--;
181	192	}
182	193	break;
183	194	case PANEL_LNDN:
184	195	if(misc_state & 0x02)
185	196	{
186		store_line++;
	197	state->store_line++;
187	198	}
188	199	break;
189	200	case PANEL_HALT:
r9684	r9685
430	441
431	442	static VIDEO_UPDATE( ssem )
432	443	{
	444	ssem_state *state = screen->machine->driver_data<ssem_state>();
433	445	UINT32 line = 0;
434	446	running_device *ssem_cpu = screen->machine->device("maincpu");
435	447	UINT32 accum = cpu_get_reg(ssem_cpu, SSEM_A);
r9684	r9685
438	450
439	451	for(line = 0; line < 32; line++)
440	452	{
441		word = (store[(line << 2) | 0] << 24) |
442		(store[(line << 2) | 1] << 16) |
443		(store[(line << 2) | 2] <<  8) |
444		(store[(line << 2) | 3] <<  0);
	453	word = (state->store[(line << 2) | 0] << 24) |
	454	(state->store[(line << 2) | 1] << 16) |
	455	(state->store[(line << 2) | 2] <<  8) |
	456	(state->store[(line << 2) | 3] <<  0);
445	457	for(bit = 0; bit < 32; bit++)
446	458	{
447	459	if(word & (1 << (31 - bit)))
448	460	{
449		glyph_print(screen->machine, bitmap, bit << 3, line << 3, "%c", line == store_line ? 4 : 2);
	461	glyph_print(screen->machine, bitmap, bit << 3, line << 3, "%c", line == state->store_line ? 4 : 2);
450	462	}
451	463	else
452	464	{
453		glyph_print(screen->machine, bitmap, bit << 3, line << 3, "%c", line == store_line ? 3 : 1);
	465	glyph_print(screen->machine, bitmap, bit << 3, line << 3, "%c", line == state->store_line ? 3 : 1);
454	466	}
455	467	}
456	468	}
r9684	r9685
467	479	}
468	480	}
469	481
470		word = reverse((store[(store_line << 2) | 0] << 24) |
471		(store[(store_line << 2) | 1] << 16) |
472		(store[(store_line << 2) | 2] <<  8) |
473		(store[(store_line << 2) | 3] <<  0));
474		glyph_print(screen->machine, bitmap, 0, 272, "LINE:%02d  VALUE:%08x  HALT:%d", store_line, word, cpu_get_reg(ssem_cpu, SSEM_HALT));
	482	word = reverse((state->store[(state->store_line << 2) | 0] << 24) |
	483	(state->store[(state->store_line << 2) | 1] << 16) |
	484	(state->store[(state->store_line << 2) | 2] <<  8) |
	485	(state->store[(state->store_line << 2) | 3] <<  0));
	486	glyph_print(screen->machine, bitmap, 0, 272, "LINE:%02d  VALUE:%08x  HALT:%d", state->store_line, word, cpu_get_reg(ssem_cpu, SSEM_HALT));
475	487	return 0;
476	488	}
477	489
r9684	r9685
500	512
501	513	static DEVICE_IMAGE_LOAD(ssem_store)
502	514	{
	515	ssem_state *state = image.device().machine->driver_data<ssem_state>();
503	516	const char* image_name = image.filename();
504	517	char image_ext[5] = { 0 };
505	518	char image_line[100] = { 0 };
r9684	r9685
540	553	}
541	554	}
542	555
543		store[(line << 2) + 0] = (word >> 24) & 0x000000ff;
544		store[(line << 2) + 1] = (word >> 16) & 0x000000ff;
545		store[(line << 2) + 2] = (word >>  8) & 0x000000ff;
546		store[(line << 2) + 3] = (word >>  0) & 0x000000ff;
	556	state->store[(line << 2) + 0] = (word >> 24) & 0x000000ff;
	557	state->store[(line << 2) + 1] = (word >> 16) & 0x000000ff;
	558	state->store[(line << 2) + 2] = (word >>  8) & 0x000000ff;
	559	state->store[(line << 2) + 3] = (word >>  0) & 0x000000ff;
547	560	}
548	561	else if(strcmp(image_ext, ".asm") == 0)
549	562	{
r9684	r9685
594	607	word = 0x00070000 | unsigned_value;
595	608	}
596	609
597		store[(line << 2) + 0] = (word >> 24) & 0x000000ff;
598		store[(line << 2) + 1] = (word >> 16) & 0x000000ff;
599		store[(line << 2) + 2] = (word >>  8) & 0x000000ff;
600		store[(line << 2) + 3] = (word >>  0) & 0x000000ff;
	610	state->store[(line << 2) + 0] = (word >> 24) & 0x000000ff;
	611	state->store[(line << 2) + 1] = (word >> 16) & 0x000000ff;
	612	state->store[(line << 2) + 2] = (word >>  8) & 0x000000ff;
	613	state->store[(line << 2) + 3] = (word >>  0) & 0x000000ff;
601	614	}
602	615	}
603	616	}
r9684	r9685
611	624
612	625	static MACHINE_RESET( ssem )
613	626	{
614		store_line = 0;
	627	ssem_state *state = machine->driver_data<ssem_state>();
	628	state->store_line = 0;
615	629	}
616	630
617		static MACHINE_CONFIG_START( ssem, driver_device )
	631	static MACHINE_CONFIG_START( ssem, ssem_state )
618	632	/* basic machine hardware */
619	633	MDRV_CPU_ADD("maincpu", SSEM, 700)
620	634	MDRV_CPU_PROGRAM_MAP(ssem_map)

src/mess/drivers/tvc.c

r9684	r9685
11	11	#include "video/mc6845.h"
12	12	#include "devices/messram.h"
13	13
14		static UINT8 tvc_video_mode = 0;
15		static UINT8 tvc_keyline = 0;
16		static UINT8 tvc_flipflop;
17	14
	15	class tvc_state : public driver_device
	16	{
	17	public:
	18	tvc_state(running_machine &machine, const driver_device_config_base &config)
	19	: driver_device(machine, config) { }
	20
	21	UINT8 video_mode;
	22	UINT8 keyline;
	23	UINT8 flipflop;
	24	UINT8 col[4];
	25	};
	26
	27
	28
18	29	static void tvc_set_mem_page(running_machine *machine, UINT8 data)
19	30	{
20	31	address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
r9684	r9685
74	85
75	86	static WRITE8_HANDLER( tvc_video_mode_w )
76	87	{
77		tvc_video_mode = data & 0x03;
	88	tvc_state *state = space->machine->driver_data<tvc_state>();
	89	state->video_mode = data & 0x03;
78	90	}
79	91
80		static UINT8 col[4];
81	92
82	93	static WRITE8_HANDLER( tvc_palette_w )
83	94	{
	95	tvc_state *state = space->machine->driver_data<tvc_state>();
84	96	//  0 I 0 R | 0 G 0 B
85	97	//  0 0 0 0 | I R G B
86	98	int i = ((data&0x40)>>3) | ((data&0x10)>>2) | ((data&0x04)>>1) | (data&0x01);
87	99
88		col[offset] = i;
	100	state->col[offset] = i;
89	101	}
90	102
91	103	static WRITE8_HANDLER( tvc_keyboard_w )
92	104	{
93		tvc_keyline = data;
	105	tvc_state *state = space->machine->driver_data<tvc_state>();
	106	state->keyline = data;
94	107	}
95	108
96	109	static READ8_HANDLER( tvc_keyboard_r )
97	110	{
	111	tvc_state *state = space->machine->driver_data<tvc_state>();
98	112	static const char *const keynames[] = {
99	113	"LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7",
100	114	"LINE8", "LINE9", "LINEA", "LINEB", "LINEC", "LINED", "LINEE", "LINEF"
101	115	};
102		return input_port_read(space->machine, keynames[tvc_keyline & 0x0f]);
	116	return input_port_read(space->machine, keynames[state->keyline & 0x0f]);
103	117	}
104	118
105	119	static READ8_HANDLER( tvc_flipflop_r )
106	120	{
107		return tvc_flipflop;
	121	tvc_state *state = space->machine->driver_data<tvc_state>();
	122	return state->flipflop;
108	123	}
109	124
110	125	static WRITE8_HANDLER( tvc_flipflop_w )
111	126	{
112		tvc_flipflop |= 0x10;
	127	tvc_state *state = space->machine->driver_data<tvc_state>();
	128	state->flipflop |= 0x10;
113	129	}
114	130	static READ8_HANDLER( tvc_port59_r )
115	131	{
r9684	r9685
237	253
238	254	static MACHINE_START(tvc)
239	255	{
	256	tvc_state *state = machine->driver_data<tvc_state>();
240	257	int i;
241	258
242	259	for (i=0; i<4; i++)
243		col[i] = i;
	260	state->col[i] = i;
244	261
245		tvc_flipflop = 0xff;
	262	state->flipflop = 0xff;
246	263	}
247	264
248	265	static MACHINE_RESET(tvc)
249	266	{
	267	tvc_state *state = machine->driver_data<tvc_state>();
250	268	memset(messram_get_ptr(machine->device("messram")),0,(64+14)*1024);
251	269	tvc_set_mem_page(machine, 0);
252		tvc_video_mode = 0;
	270	state->video_mode = 0;
253	271	}
254	272
255	273	static VIDEO_START( tvc )
r9684	r9685
265	283
266	284	static MC6845_UPDATE_ROW( tvc_update_row )
267	285	{
	286	tvc_state *state = device->machine->driver_data<tvc_state>();
268	287	UINT16  *p = BITMAP_ADDR16(bitmap, y, 0);
269	288	int i;
270	289
271		switch(tvc_video_mode) {
	290	switch(state->video_mode) {
272	291	case 0 :
273	292	for ( i = 0; i < x_count; i++ )
274	293	{
275	294	UINT16 offset = i  + (y * 64);
276	295	UINT8 data = messram_get_ptr(device->machine->device("messram"))[ offset + 0x10000];
277		*p = col[(data >> 7)]; p++;
278		*p = col[(data >> 6)]; p++;
279		*p = col[(data >> 5)]; p++;
280		*p = col[(data >> 4)]; p++;
281		*p = col[(data >> 3)]; p++;
282		*p = col[(data >> 2)]; p++;
283		*p = col[(data >> 1)]; p++;
284		*p = col[(data >> 0)]; p++;
	296	*p = state->col[(data >> 7)]; p++;
	297	*p = state->col[(data >> 6)]; p++;
	298	*p = state->col[(data >> 5)]; p++;
	299	*p = state->col[(data >> 4)]; p++;
	300	*p = state->col[(data >> 3)]; p++;
	301	*p = state->col[(data >> 2)]; p++;
	302	*p = state->col[(data >> 1)]; p++;
	303	*p = state->col[(data >> 0)]; p++;
285	304	}
286	305	break;
287	306	case 1 :
r9684	r9685
289	308	{
290	309	UINT16 offset = i  + (y * 64);
291	310	UINT8 data = messram_get_ptr(device->machine->device("messram"))[ offset + 0x10000];
292		*p = col[BIT(data,7)*2 + BIT(data,3)]; p++;
293		*p = col[BIT(data,7)*2 + BIT(data,3)]; p++;
294		*p = col[BIT(data,6)*2 + BIT(data,2)]; p++;
295		*p = col[BIT(data,6)*2 + BIT(data,2)]; p++;
296		*p = col[BIT(data,5)*2 + BIT(data,1)]; p++;
297		*p = col[BIT(data,5)*2 + BIT(data,1)]; p++;
298		*p = col[BIT(data,4)*2 + BIT(data,0)]; p++;
299		*p = col[BIT(data,4)*2 + BIT(data,0)]; p++;
	311	*p = state->col[BIT(data,7)*2 + BIT(data,3)]; p++;
	312	*p = state->col[BIT(data,7)*2 + BIT(data,3)]; p++;
	313	*p = state->col[BIT(data,6)*2 + BIT(data,2)]; p++;
	314	*p = state->col[BIT(data,6)*2 + BIT(data,2)]; p++;
	315	*p = state->col[BIT(data,5)*2 + BIT(data,1)]; p++;
	316	*p = state->col[BIT(data,5)*2 + BIT(data,1)]; p++;
	317	*p = state->col[BIT(data,4)*2 + BIT(data,0)]; p++;
	318	*p = state->col[BIT(data,4)*2 + BIT(data,0)]; p++;
300	319	}
301	320	break;
302	321	default:
r9684	r9685
304	323	{
305	324	UINT16 offset = i  + (y * 64);
306	325	UINT8 data = messram_get_ptr(device->machine->device("messram"))[ offset + 0x10000];
307		*p = col[(data >> 4) & 0xf]; p++;
308		*p = col[(data >> 4) & 0xf]; p++;
309		*p = col[(data >> 4) & 0xf]; p++;
310		*p = col[(data >> 4) & 0xf]; p++;
311		*p = col[(data >> 0) & 0xf]; p++;
312		*p = col[(data >> 0) & 0xf]; p++;
313		*p = col[(data >> 0) & 0xf]; p++;
314		*p = col[(data >> 0) & 0xf]; p++;
	326	*p = state->col[(data >> 4) & 0xf]; p++;
	327	*p = state->col[(data >> 4) & 0xf]; p++;
	328	*p = state->col[(data >> 4) & 0xf]; p++;
	329	*p = state->col[(data >> 4) & 0xf]; p++;
	330	*p = state->col[(data >> 0) & 0xf]; p++;
	331	*p = state->col[(data >> 0) & 0xf]; p++;
	332	*p = state->col[(data >> 0) & 0xf]; p++;
	333	*p = state->col[(data >> 0) & 0xf]; p++;
315	334	}
316	335	break;
317	336
r9684	r9685
361	380
362	381	static INTERRUPT_GEN( tvc_interrupt )
363	382	{
364		tvc_flipflop  &= ~0x10;
	383	tvc_state *state = device->machine->driver_data<tvc_state>();
	384	state->flipflop  &= ~0x10;
365	385	cpu_set_input_line(device, 0, HOLD_LINE);
366	386	}
367	387
368		static MACHINE_CONFIG_START( tvc, driver_device )
	388	static MACHINE_CONFIG_START( tvc, tvc_state )
369	389	/* basic machine hardware */
370	390	MDRV_CPU_ADD("maincpu",Z80, 3125000)
371	391	MDRV_CPU_PROGRAM_MAP(tvc_mem)

src/mess/drivers/tk80bs.c

r9684	r9685
16	16	#include "machine/i8255a.h"
17	17
18	18
	19	class tk80bs_state : public driver_device
	20	{
	21	public:
	22	tk80bs_state(running_machine &machine, const driver_device_config_base &config)
	23	: driver_device(machine, config) { }
19	24
	25	UINT8 *vram;
	26	UINT8 keyb_press;
	27	UINT8 keyb_press_flag;
	28	UINT8 shift_press_flag;
	29	};
	30
	31
	32
	33
20	34	static VIDEO_START( tk80 )
21	35	{
22	36	}
r9684	r9685
46	60	{
47	61	}
48	62
49		static UINT8 *vram;
50		static UINT8 keyb_press,keyb_press_flag,shift_press_flag;
51	63
52	64	static VIDEO_START( tk80bs )
53	65	{
r9684	r9685
55	67
56	68	static VIDEO_UPDATE( tk80bs )
57	69	{
	70	tk80bs_state *state = screen->machine->driver_data<tk80bs_state>();
58	71	int x,y;
59	72	int count;
60	73
r9684	r9685
64	77	{
65	78	for(x=0;x<32;x++)
66	79	{
67		int tile = vram[count];
	80	int tile = state->vram[count];
68	81
69	82	drawgfx_opaque(bitmap, cliprect, screen->machine->gfx[0], tile, 0, 0, 0, x*8, y*8);
70	83
r9684	r9685
78	91	/* FIXME: current i8255 core doesn't seem to like this system at all, so we use custom code here for now */
79	92	static READ8_HANDLER( ppi_custom_r )
80	93	{
	94	tk80bs_state *state = space->machine->driver_data<tk80bs_state>();
81	95	//  printf("%02x\n",offset);
82	96
83	97	switch(offset+0x7dfc)
84	98	{
85		case 0x7dfc: keyb_press_flag = 0; return keyb_press;
	99	case 0x7dfc: state->keyb_press_flag = 0; return state->keyb_press;
86	100	case 0x7dfd: return 0xff;
87		case 0x7dfe: return keyb_press_flag << 5; //keyboard flag
	101	case 0x7dfe: return state->keyb_press_flag << 5; //keyboard flag
88	102	}
89	103
90	104	return 0xff;
r9684	r9685
107	121	AM_RANGE(0x7df8, 0x7df9) AM_NOP // i8251 sio
108	122	//  AM_RANGE(0x7dfc, 0x7dff) AM_DEVREADWRITE("ppi8255_0", i8255a_r, i8255a_w)
109	123	AM_RANGE(0x7dfc, 0x7dff) AM_READWRITE(ppi_custom_r,ppi_custom_w)
110		AM_RANGE(0x7e00, 0x7fff) AM_RAM AM_BASE(&vram) // video ram
	124	AM_RANGE(0x7e00, 0x7fff) AM_RAM AM_BASE_MEMBER(tk80bs_state, vram) // video ram
111	125	AM_RANGE(0x8000, 0xcfff) AM_RAM // RAM
112	126	AM_RANGE(0xd000, 0xefff) AM_ROM // BASIC
113	127	AM_RANGE(0xf000, 0xffff) AM_ROM // BSMON
r9684	r9685
230	244
231	245	static TIMER_CALLBACK( keyboard_callback )
232	246	{
	247	tk80bs_state *state = machine->driver_data<tk80bs_state>();
233	248	const char* portnames[3] = { "key1","key2","key3" };
234	249	int i,port_i,scancode;
235	250	UINT8 keymod = input_port_read(machine,"key_modifiers") & 0x1f;
236	251	scancode = 0;
237	252
238		shift_press_flag = ((keymod & 0x02) >> 1);
	253	state->shift_press_flag = ((keymod & 0x02) >> 1);
239	254
240	255	for(port_i=0;port_i<3;port_i++)
241	256	{
r9684	r9685
247	262	{
248	263	scancode |= 0x80;
249	264	}
250		if(!shift_press_flag)  // shift not pressed
	265	if(!state->shift_press_flag)  // shift not pressed
251	266	{
252	267	//if(scancode >= 0x41 && scancode < 0x5b)
253	268	//  scancode += 0x20;  // lowercase doesn't exist here
r9684	r9685
269	284	if(scancode == 0x3c)
270	285	scancode = 0x3e;
271	286	}
272		keyb_press = scancode;
273		keyb_press_flag = 1;
	287	state->keyb_press = scancode;
	288	state->keyb_press_flag = 1;
274	289	return;
275	290	}
276	291	scancode++;
r9684	r9685
332	347	};
333	348
334	349
335		static MACHINE_CONFIG_START( tk80, driver_device )
	350	static MACHINE_CONFIG_START( tk80, tk80bs_state )
336	351	/* basic machine hardware */
337	352	MDRV_CPU_ADD("maincpu",I8080, XTAL_1MHz)
338	353	MDRV_CPU_PROGRAM_MAP(tk80_mem)
r9684	r9685
356	371	MDRV_VIDEO_UPDATE(tk80)
357	372	MACHINE_CONFIG_END
358	373
359		static MACHINE_CONFIG_START( tk80bs, driver_device )
	374	static MACHINE_CONFIG_START( tk80bs, tk80bs_state )
360	375	/* basic machine hardware */
361	376	MDRV_CPU_ADD("maincpu",I8080, XTAL_1MHz) //unknown clock
362	377	MDRV_CPU_PROGRAM_MAP(tk80bs_mem)

src/mess/drivers/ti99_2.c

r9684	r9685
89	89	: driver_device(machine, config) { }
90	90
91	91	UINT8 *videoram;
	92	int ROM_paged;
	93	int irq_state;
	94	int KeyRow;
92	95	};
93	96
94	97
95		static int ROM_paged;
96		static int irq_state;
97	98
98	99	static DRIVER_INIT( ti99_2_24 )
99	100	{
	101	ti99_2_state *state = machine->driver_data<ti99_2_state>();
100	102	/* no ROM paging */
101		ROM_paged = 0;
	103	state->ROM_paged = 0;
102	104	}
103	105
104	106	static DRIVER_INIT( ti99_2_32 )
105	107	{
	108	ti99_2_state *state = machine->driver_data<ti99_2_state>();
106	109	/* ROM paging enabled */
107		ROM_paged = 1;
	110	state->ROM_paged = 1;
108	111	}
109	112
110	113	#define TI99_2_32_ROMPAGE0 (memory_region(space->machine, "maincpu")+0x4000)
r9684	r9685
112	115
113	116	static MACHINE_RESET( ti99_2 )
114	117	{
115		irq_state = ASSERT_LINE;
116		if (! ROM_paged)
	118	ti99_2_state *state = machine->driver_data<ti99_2_state>();
	119	state->irq_state = ASSERT_LINE;
	120	if (! state->ROM_paged)
117	121	memory_set_bankptr(machine, "bank1", memory_region(machine, "maincpu")+0x4000);
118	122	else
119	123	memory_set_bankptr(machine, "bank1", (memory_region(machine, "maincpu")+0x4000));
r9684	r9685
121	125
122	126	static INTERRUPT_GEN( ti99_2_vblank_interrupt )
123	127	{
124		cpu_set_input_line(device, 1, irq_state);
125		irq_state = (irq_state == ASSERT_LINE) ? CLEAR_LINE : ASSERT_LINE;
	128	ti99_2_state *state = device->machine->driver_data<ti99_2_state>();
	129	cpu_set_input_line(device, 1, state->irq_state);
	130	state->irq_state = (state->irq_state == ASSERT_LINE) ? CLEAR_LINE : ASSERT_LINE;
126	131	}
127	132
128	133
r9684	r9685
210	215	*/
211	216
212	217	/* current keyboard row */
213		static int KeyRow = 0;
214	218
215	219	/* write the current keyboard row */
216	220	static WRITE8_HANDLER ( ti99_2_write_kbd )
217	221	{
	222	ti99_2_state *state = space->machine->driver_data<ti99_2_state>();
218	223	offset &= 0x7;  /* other address lines are not decoded */
219	224
220	225	if (offset <= 2)
221	226	{
222	227	/* this implementation is just a guess */
223	228	if (data)
224		KeyRow |= 1 << offset;
	229	state->KeyRow |= 1 << offset;
225	230	else
226		KeyRow &= ~ (1 << offset);
	231	state->KeyRow &= ~ (1 << offset);
227	232	}
228	233	/* now, we handle ROM paging */
229		if (ROM_paged)
	234	if (state->ROM_paged)
230	235	{   /* if we have paged ROMs, page according to S0 keyboard interface line */
231		memory_set_bankptr(space->machine, "bank1", (KeyRow == 0) ? TI99_2_32_ROMPAGE1 : TI99_2_32_ROMPAGE0);
	236	memory_set_bankptr(space->machine, "bank1", (state->KeyRow == 0) ? TI99_2_32_ROMPAGE1 : TI99_2_32_ROMPAGE0);
232	237	}
233	238	}
234	239
r9684	r9685
262	267	/* read keys in the current row */
263	268	static  READ8_HANDLER ( ti99_2_read_kbd )
264	269	{
	270	ti99_2_state *state = space->machine->driver_data<ti99_2_state>();
265	271	static const char *const keynames[] = { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7" };
266	272
267		return input_port_read(space->machine, keynames[KeyRow]);
	273	return input_port_read(space->machine, keynames[state->KeyRow]);
268	274	}
269	275
270	276	static  READ8_HANDLER ( ti99_2_read_misc_cru )

src/mess/drivers/mes.c

r9684	r9685
9	9	#include "emu.h"
10	10	#include "cpu/z80/z80.h"
11	11
12		static const UINT8 *FNT;
13		static const UINT8 *videoram;
14	12
	13	class mes_state : public driver_device
	14	{
	15	public:
	16	mes_state(running_machine &machine, const driver_device_config_base &config)
	17	: driver_device(machine, config) { }
	18
	19	const UINT8 *FNT;
	20	const UINT8 *videoram;
	21	};
	22
	23
	24
15	25	static ADDRESS_MAP_START(mes_mem, ADDRESS_SPACE_PROGRAM, 8)
16	26	ADDRESS_MAP_UNMAP_HIGH
17	27	AM_RANGE(0x0000, 0x0fff) AM_ROM
r9684	r9685
32	42
33	43	static VIDEO_START( mes )
34	44	{
35		FNT = memory_region(machine, "chargen");
36		videoram = memory_region(machine, "maincpu")+0xf000;
	45	mes_state *state = machine->driver_data<mes_state>();
	46	state->FNT = memory_region(machine, "chargen");
	47	state->videoram = memory_region(machine, "maincpu")+0xf000;
37	48	}
38	49
39	50	/* This system appears to have 2 screens. Not implemented.
40	51	Also the screen dimensions are a guess. */
41	52	static VIDEO_UPDATE( mes )
42		{   //static UINT8 framecnt=0;
	53	{
	54	mes_state *state = screen->machine->driver_data<mes_state>();   //static UINT8 framecnt=0;
43	55	UINT8 y,ra,chr,gfx;
44	56	UINT16 sy=0,ma=0,x,xx;
45	57
r9684	r9685
57	69	gfx = 0;
58	70	if (ra < 9)
59	71	{
60		chr = videoram[xx++];
	72	chr = state->videoram[xx++];
61	73
62	74	//   /* Take care of flashing characters */
63	75	//   if ((chr < 0x80) && (framecnt & 0x08))
r9684	r9685
67	79	x--;
68	80	else
69	81	{
70		gfx = FNT[(chr<<4) | ra ];
	82	gfx = state->FNT[(chr<<4) | ra ];
71	83
72	84	/* Display a scanline of a character */
73	85	*p++ = ( gfx & 0x80 ) ? 1 : 0;
r9684	r9685
87	99	return 0;
88	100	}
89	101
90		static MACHINE_CONFIG_START( mes, driver_device )
	102	static MACHINE_CONFIG_START( mes, mes_state )
91	103	/* basic machine hardware */
92	104	MDRV_CPU_ADD("maincpu", Z80, XTAL_16MHz / 4)
93	105	MDRV_CPU_PROGRAM_MAP(mes_mem)

src/mess/drivers/mccpm.c

r9684	r9685
11	11	#include "cpu/z80/z80.h"
12	12	#include "machine/terminal.h"
13	13
14		static UINT8 *mccpm_ram;
15		static UINT8 term_data;
16	14
	15	class mccpm_state : public driver_device
	16	{
	17	public:
	18	mccpm_state(running_machine &machine, const driver_device_config_base &config)
	19	: driver_device(machine, config) { }
	20
	21	UINT8 *ram;
	22	UINT8 term_data;
	23	};
	24
	25
	26
17	27	static WRITE8_HANDLER( mccpm_f0_w )
18	28	{
19	29	running_device *terminal = space->machine->device("terminal");
r9684	r9685
23	33
24	34	static READ8_HANDLER( mccpm_f0_r )
25	35	{
26		UINT8 ret = term_data;
27		term_data = 0;
	36	mccpm_state *state = space->machine->driver_data<mccpm_state>();
	37	UINT8 ret = state->term_data;
	38	state->term_data = 0;
28	39	return ret;
29	40	}
30	41
31	42	static ADDRESS_MAP_START(mccpm_mem, ADDRESS_SPACE_PROGRAM, 8)
32	43	ADDRESS_MAP_UNMAP_HIGH
33		AM_RANGE(0x0000, 0xffff) AM_RAM AM_BASE(&mccpm_ram)
	44	AM_RANGE(0x0000, 0xffff) AM_RAM AM_BASE_MEMBER(mccpm_state, ram)
34	45	ADDRESS_MAP_END
35	46
36	47	static ADDRESS_MAP_START( mccpm_io , ADDRESS_SPACE_IO, 8)
r9684	r9685
47	58
48	59	static MACHINE_RESET(mccpm)
49	60	{
	61	mccpm_state *state = machine->driver_data<mccpm_state>();
50	62	UINT8* bios = memory_region(machine, "maincpu");
51	63
52		memcpy(mccpm_ram,bios, 0x1000);
	64	memcpy(state->ram,bios, 0x1000);
53	65	}
54	66
55	67	static WRITE8_DEVICE_HANDLER( mccpm_kbd_put )
56	68	{
57		term_data = data;
	69	mccpm_state *state = device->machine->driver_data<mccpm_state>();
	70	state->term_data = data;
58	71	}
59	72
60	73	static GENERIC_TERMINAL_INTERFACE( mccpm_terminal_intf )
r9684	r9685
62	75	DEVCB_HANDLER(mccpm_kbd_put)
63	76	};
64	77
65		static MACHINE_CONFIG_START( mccpm, driver_device )
	78	static MACHINE_CONFIG_START( mccpm, mccpm_state )
66	79	/* basic machine hardware */
67	80	MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
68	81	MDRV_CPU_PROGRAM_MAP(mccpm_mem)

src/mess/drivers/tutor.c

r9684	r9685
167	167	#include "sound/sn76496.h"
168	168	#include "machine/ctronics.h"
169	169
	170
	171	class tutor_state : public driver_device
	172	{
	173	public:
	174	tutor_state(running_machine &machine, const driver_device_config_base &config)
	175	: driver_device(machine, config) { }
	176
	177	char cartridge_enable;
	178	char tape_interrupt_enable;
	179	emu_timer *tape_interrupt_timer;
	180	UINT8 printer_data;
	181	char printer_strobe;
	182	};
	183
	184
170	185	/* mapper state */
171		static char cartridge_enable;
172	186
173	187	/* tape interface state */
174	188	static TIMER_CALLBACK(tape_interrupt_handler);
175	189
176		static char tape_interrupt_enable;
177		static emu_timer *tape_interrupt_timer;
178	190
179	191	/* parallel interface state */
180		static UINT8 printer_data;
181		static char printer_strobe;
182	192
183	193	enum
184	194	{
r9684	r9685
189	199
190	200	static DRIVER_INIT(tutor)
191	201	{
192		tape_interrupt_timer = timer_alloc(machine, tape_interrupt_handler, NULL);
	202	tutor_state *state = machine->driver_data<tutor_state>();
	203	state->tape_interrupt_timer = timer_alloc(machine, tape_interrupt_handler, NULL);
193	204
194	205	memory_configure_bank(machine, "bank1", 0, 1, memory_region(machine, "maincpu") + basic_base, 0);
195	206	memory_configure_bank(machine, "bank1", 1, 1, memory_region(machine, "maincpu") + cartridge_base, 0);
r9684	r9685
219	230
220	231	static MACHINE_RESET(tutor)
221	232	{
222		cartridge_enable = 0;
	233	tutor_state *state = machine->driver_data<tutor_state>();
	234	state->cartridge_enable = 0;
223	235
224		tape_interrupt_enable = 0;
	236	state->tape_interrupt_enable = 0;
225	237
226		printer_data = 0;
227		printer_strobe = 0;
	238	state->printer_data = 0;
	239	state->printer_strobe = 0;
228	240	}
229	241
230	242	static INTERRUPT_GEN( tutor_vblank_interrupt )
r9684	r9685
326	338
327	339	static WRITE8_HANDLER(tutor_mapper_w)
328	340	{
	341	tutor_state *state = space->machine->driver_data<tutor_state>();
329	342	switch (offset)
330	343	{
331	344	case 0x00:
r9684	r9685
334	347
335	348	case 0x08:
336	349	/* disable cartridge ROM, enable BASIC ROM at base >8000 */
337		cartridge_enable = 0;
	350	state->cartridge_enable = 0;
338	351	memory_set_bank(space->machine, "bank1", 0);
339	352	break;
340	353
341	354	case 0x0c:
342	355	/* enable cartridge ROM, disable BASIC ROM at base >8000 */
343		cartridge_enable = 1;
	356	state->cartridge_enable = 1;
344	357	memory_set_bank(space->machine, "bank1", 1);
345	358	break;
346	359
r9684	r9685
372	385
373	386	static TIMER_CALLBACK(tape_interrupt_handler)
374	387	{
375		//assert(tape_interrupt_enable);
	388	//tutor_state *state = machine->driver_data<tutor_state>();
	389	//assert(state->tape_interrupt_enable);
376	390	cputag_set_input_line(machine, "maincpu", 1, (cassette_input(machine->device("cassette")) > 0.0) ? ASSERT_LINE : CLEAR_LINE);
377	391	}
378	392
r9684	r9685
385	399	/* memory handler */
386	400	static WRITE8_HANDLER(tutor_cassette_w)
387	401	{
	402	tutor_state *state = space->machine->driver_data<tutor_state>();
388	403	if (offset & /*0x1f*/0x1e)
389	404	logerror("unknown port in %s %d\n", __FILE__, __LINE__);
390	405
r9684	r9685
401	416	case 1:
402	417	/* interrupt control??? */
403	418	//logerror("ignoring write of %d to cassette port 1\n", data);
404		if (tape_interrupt_enable != ! data)
	419	if (state->tape_interrupt_enable != ! data)
405	420	{
406		tape_interrupt_enable = ! data;
407		if (tape_interrupt_enable)
408		timer_adjust_periodic(tape_interrupt_timer, /*ATTOTIME_IN_HZ(44100)*/attotime_zero, 0, ATTOTIME_IN_HZ(44100));
	421	state->tape_interrupt_enable = ! data;
	422	if (state->tape_interrupt_enable)
	423	timer_adjust_periodic(state->tape_interrupt_timer, /*ATTOTIME_IN_HZ(44100)*/attotime_zero, 0, ATTOTIME_IN_HZ(44100));
409	424	else
410	425	{
411		timer_adjust_oneshot(tape_interrupt_timer, attotime_never, 0);
	426	timer_adjust_oneshot(state->tape_interrupt_timer, attotime_never, 0);
412	427	cputag_set_input_line(space->machine, "maincpu", 1, CLEAR_LINE);
413	428	}
414	429	}
r9684	r9685
669	684	NULL      /* no IDLE callback */
670	685	};
671	686
672		static MACHINE_CONFIG_START( tutor, driver_device )
	687	static MACHINE_CONFIG_START( tutor, tutor_state )
673	688	/* basic machine hardware */
674	689	/* TMS9995 CPU @ 10.7 MHz */
675	690	MDRV_CPU_ADD("maincpu", TMS9995, 10700000)

src/mess/drivers/tricep.c

r9684	r9685
10	10	#include "cpu/m68000/m68000.h"
11	11	#include "machine/terminal.h"
12	12
13		static UINT16* tricep_ram;
14	13
	14	class tricep_state : public driver_device
	15	{
	16	public:
	17	tricep_state(running_machine &machine, const driver_device_config_base &config)
	18	: driver_device(machine, config) { }
	19
	20	UINT16* ram;
	21	};
	22
	23
	24
15	25	static READ16_HANDLER(tricep_terminal_r)
16	26	{
17	27	return 0xffff;
r9684	r9685
25	35
26	36	static ADDRESS_MAP_START(tricep_mem, ADDRESS_SPACE_PROGRAM, 16)
27	37	ADDRESS_MAP_UNMAP_HIGH
28		AM_RANGE(0x00000000, 0x0007ffff) AM_RAM AM_BASE(&tricep_ram)
	38	AM_RANGE(0x00000000, 0x0007ffff) AM_RAM AM_BASE_MEMBER(tricep_state, ram)
29	39	AM_RANGE(0x00fd0000, 0x00fd1fff) AM_ROM AM_REGION("user1",0)
30	40	AM_RANGE(0x00ff0028, 0x00ff0029) AM_READWRITE(tricep_terminal_r,tricep_terminal_w)
31	41	ADDRESS_MAP_END
r9684	r9685
38	48
39	49	static MACHINE_RESET(tricep)
40	50	{
	51	tricep_state *state = machine->driver_data<tricep_state>();
41	52	UINT8* user1 = memory_region(machine, "user1");
42	53
43		memcpy((UINT8*)tricep_ram,user1,0x2000);
	54	memcpy((UINT8*)state->ram,user1,0x2000);
44	55
45	56	machine->device("maincpu")->reset();
46	57	}
r9684	r9685
54	65	DEVCB_HANDLER(tricep_kbd_put)
55	66	};
56	67
57		static MACHINE_CONFIG_START( tricep, driver_device )
	68	static MACHINE_CONFIG_START( tricep, tricep_state )
58	69	/* basic machine hardware */
59	70	MDRV_CPU_ADD("maincpu",M68000, XTAL_8MHz)
60	71	MDRV_CPU_PROGRAM_MAP(tricep_mem)

src/mess/drivers/pockstat.c

r9684	r9685
34	34	#include "devices/cartslot.h"
35	35	#include "sound/dac.h"
36	36
	37	#define MAX_PS_TIMERS   3
	38
	39	typedef struct
	40	{
	41	UINT32 control;
	42	UINT32 stat;
	43	UINT32 valid;
	44	UINT32 wait1;
	45	UINT32 wait2;
	46	UINT32 entry[16];
	47	UINT32 serial;
	48	} ps_ftlb_regs_t;
	49
	50	typedef struct
	51	{
	52	UINT32 hold;
	53	UINT32 status;
	54	UINT32 enable;
	55	UINT32 mask;
	56	} ps_intc_regs_t;
	57
	58	typedef struct
	59	{
	60	UINT32 period;
	61	UINT32 count;
	62	UINT32 control;
	63	emu_timer *timer;
	64	} ps_timer_t;
	65
	66	typedef struct
	67	{
	68	ps_timer_t timer[MAX_PS_TIMERS];
	69	} ps_timer_regs_t;
	70
	71	typedef struct
	72	{
	73	UINT32 mode;
	74	UINT32 control;
	75	} ps_clock_regs_t;
	76
	77	#define PS_CLOCK_STEADY      0x10
	78
	79	typedef struct
	80	{
	81	UINT32 mode;
	82	UINT32 control;
	83	UINT32 time;
	84	UINT32 date;
	85	emu_timer *timer;
	86	} ps_rtc_regs_t;
	87
	88
	89
	90	class pockstat_state : public driver_device
	91	{
	92	public:
	93	pockstat_state(running_machine &machine, const driver_device_config_base &config)
	94	: driver_device(machine, config) { }
	95
	96	UINT32 *lcd_buffer;
	97	ps_ftlb_regs_t ftlb_regs;
	98	ps_intc_regs_t intc_regs;
	99	ps_timer_regs_t timer_regs;
	100	ps_clock_regs_t clock_regs;
	101	ps_rtc_regs_t rtc_regs;
	102	UINT32 lcd_control;
	103	INT32 ps_flash_write_enable_count;
	104	INT32 ps_flash_write_count;
	105	};
	106
	107
37	108	#define DEFAULT_CLOCK   2000000
38	109
39	110	static const int CPU_FREQ[16] =
r9684	r9685
77	148	#define verboselog(x,y,z,...)
78	149	#endif
79	150
80		static UINT32 *lcd_buffer;
81	151
82	152	// Flash TLB
83	153	static READ32_HANDLER( ps_ftlb_r );
r9684	r9685
104	174	static READ32_HANDLER( ps_rtc_r );
105	175	static WRITE32_HANDLER( ps_rtc_w );
106	176
107		typedef struct
108		{
109		UINT32 control;
110		UINT32 stat;
111		UINT32 valid;
112		UINT32 wait1;
113		UINT32 wait2;
114		UINT32 entry[16];
115		UINT32 serial;
116		} ps_ftlb_regs_t;
117
118		typedef struct
119		{
120		UINT32 hold;
121		UINT32 status;
122		UINT32 enable;
123		UINT32 mask;
124		} ps_intc_regs_t;
125
126	177	#define PS_INT_BTN_ACTION      0x00000001 // "Action button"
127	178	#define PS_INT_BTN_RIGHT      0x00000002 // "Right button"
128	179	#define PS_INT_BTN_LEFT         0x00000004 // "Left button"
r9684	r9685
141	192	#define PS_INT_FIQ_MASK         0x00002040
142	193	#define PS_INT_STATUS_MASK      0x0000021f
143	194
144		#define MAX_PS_TIMERS   3
145
146		typedef struct
147		{
148		UINT32 period;
149		UINT32 count;
150		UINT32 control;
151		emu_timer *timer;
152		} ps_timer_t;
153
154		typedef struct
155		{
156		ps_timer_t timer[MAX_PS_TIMERS];
157		} ps_timer_regs_t;
158
159		typedef struct
160		{
161		UINT32 mode;
162		UINT32 control;
163		} ps_clock_regs_t;
164
165		#define PS_CLOCK_STEADY      0x10
166
167		typedef struct
168		{
169		UINT32 mode;
170		UINT32 control;
171		UINT32 time;
172		UINT32 date;
173		emu_timer *timer;
174		} ps_rtc_regs_t;
175
176		static ps_ftlb_regs_t ftlb_regs;
177		static ps_intc_regs_t intc_regs;
178		static ps_timer_regs_t timer_regs;
179		static ps_clock_regs_t clock_regs;
180		static ps_rtc_regs_t rtc_regs;
181
182	195	static READ32_HANDLER( ps_ftlb_r )
183	196	{
	197	pockstat_state *state = space->machine->driver_data<pockstat_state>();
184	198	switch(offset)
185	199	{
186	200	case 0x0000/4:
187		verboselog(space->machine, 0, "ps_ftlb_r: FlashROM TLB Control = %08x & %08x\n", ftlb_regs.control, mem_mask );
188		return ftlb_regs.control | 1; // ???
	201	verboselog(space->machine, 0, "ps_ftlb_r: FlashROM TLB Control = %08x & %08x\n", state->ftlb_regs.control, mem_mask );
	202	return state->ftlb_regs.control | 1; // ???
189	203	case 0x0004/4:
190		verboselog(space->machine, 0, "ps_ftlb_r: Unknown (F_STAT) = %08x & %08x\n", ftlb_regs.stat, mem_mask );
191		return ftlb_regs.stat;
	204	verboselog(space->machine, 0, "ps_ftlb_r: Unknown (F_STAT) = %08x & %08x\n", state->ftlb_regs.stat, mem_mask );
	205	return state->ftlb_regs.stat;
192	206	case 0x0008/4:
193		verboselog(space->machine, 0, "ps_ftlb_r: FlashROM TLB Valid Tag = %08x & %08x\n", ftlb_regs.valid, mem_mask );
194		return ftlb_regs.valid;
	207	verboselog(space->machine, 0, "ps_ftlb_r: FlashROM TLB Valid Tag = %08x & %08x\n", state->ftlb_regs.valid, mem_mask );
	208	return state->ftlb_regs.valid;
195	209	case 0x000c/4:
196		verboselog(space->machine, 0, "ps_ftlb_r: Unknown (F_WAIT1) = %08x & %08x\n", ftlb_regs.wait1, mem_mask );
197		return ftlb_regs.wait1;
	210	verboselog(space->machine, 0, "ps_ftlb_r: Unknown (F_WAIT1) = %08x & %08x\n", state->ftlb_regs.wait1, mem_mask );
	211	return state->ftlb_regs.wait1;
198	212	case 0x0010/4:
199		verboselog(space->machine, 0, "ps_ftlb_r: Unknown (F_WAIT2) = %08x & %08x\n", ftlb_regs.wait2 | 0x04, mem_mask );
200		return ftlb_regs.wait2 | 0x04;
	213	verboselog(space->machine, 0, "ps_ftlb_r: Unknown (F_WAIT2) = %08x & %08x\n", state->ftlb_regs.wait2 | 0x04, mem_mask );
	214	return state->ftlb_regs.wait2 | 0x04;
201	215	case 0x0100/4:
202	216	case 0x0104/4:
203	217	case 0x0108/4:
r9684	r9685
214	228	case 0x0134/4:
215	229	case 0x0138/4:
216	230	case 0x013c/4:
217		verboselog(space->machine, 0, "ps_ftlb_r: FlashROM TLB Entry %d = %08x & %08x\n", offset - 0x100/4, ftlb_regs.entry[offset - 0x100/4], mem_mask );
218		return ftlb_regs.entry[offset - 0x100/4];
	231	verboselog(space->machine, 0, "ps_ftlb_r: FlashROM TLB Entry %d = %08x & %08x\n", offset - 0x100/4, state->ftlb_regs.entry[offset - 0x100/4], mem_mask );
	232	return state->ftlb_regs.entry[offset - 0x100/4];
219	233	case 0x0300/4:
220		verboselog(space->machine, 0, "ps_ftlb_r: Unknown (F_SN) = %08x & %08x\n", ftlb_regs.serial, mem_mask );
221		return ftlb_regs.serial;
	234	verboselog(space->machine, 0, "ps_ftlb_r: Unknown (F_SN) = %08x & %08x\n", state->ftlb_regs.serial, mem_mask );
	235	return state->ftlb_regs.serial;
222	236	default:
223	237	verboselog(space->machine, 0, "ps_ftlb_r: Unknown Register %08x & %08x\n", 0x06000000 + (offset << 2), mem_mask );
224	238	break;
r9684	r9685
228	242
229	243	static WRITE32_HANDLER( ps_ftlb_w )
230	244	{
	245	pockstat_state *state = space->machine->driver_data<pockstat_state>();
231	246	switch(offset)
232	247	{
233	248	case 0x0000/4:
234	249	verboselog(space->machine, 0, "ps_ftlb_w: FlashROM TLB Control = %08x & %08x\n", data, mem_mask );
235		COMBINE_DATA(&ftlb_regs.control);
	250	COMBINE_DATA(&state->ftlb_regs.control);
236	251	break;
237	252	case 0x0004/4:
238	253	verboselog(space->machine, 0, "ps_ftlb_w: Unknown (F_STAT) = %08x & %08x\n", data, mem_mask );
239		COMBINE_DATA(&ftlb_regs.stat);
	254	COMBINE_DATA(&state->ftlb_regs.stat);
240	255	break;
241	256	case 0x0008/4:
242	257	verboselog(space->machine, 0, "ps_ftlb_w: FlashROM TLB Valid Tag = %08x & %08x\n", data, mem_mask );
243		COMBINE_DATA(&ftlb_regs.valid);
	258	COMBINE_DATA(&state->ftlb_regs.valid);
244	259	break;
245	260	case 0x000c/4:
246	261	verboselog(space->machine, 0, "ps_ftlb_w: Unknown (F_WAIT1) = %08x & %08x\n", data, mem_mask );
247		COMBINE_DATA(&ftlb_regs.wait1);
	262	COMBINE_DATA(&state->ftlb_regs.wait1);
248	263	break;
249	264	case 0x0010/4:
250	265	verboselog(space->machine, 0, "ps_ftlb_w: Unknown (F_WAIT2) = %08x & %08x\n", data, mem_mask );
251		COMBINE_DATA(&ftlb_regs.wait2);
	266	COMBINE_DATA(&state->ftlb_regs.wait2);
252	267	break;
253	268	case 0x0100/4:
254	269	case 0x0104/4:
r9684	r9685
267	282	case 0x0138/4:
268	283	case 0x013c/4:
269	284	verboselog(space->machine, 0, "ps_ftlb_w: FlashROM TLB Entry %d = %08x & %08x\n", offset - 0x100/4, data, mem_mask );
270		COMBINE_DATA(&ftlb_regs.entry[offset - 0x100/4]);
	285	COMBINE_DATA(&state->ftlb_regs.entry[offset - 0x100/4]);
271	286	break;
272	287	case 0x0300/4:
273	288	verboselog(space->machine, 0, "ps_ftlb_w: Unknown (F_SN) = %08x & %08x\n", data, mem_mask );
274		COMBINE_DATA(&ftlb_regs.serial);
	289	COMBINE_DATA(&state->ftlb_regs.serial);
275	290	break;
276	291	default:
277	292	verboselog(space->machine, 0, "ps_ftlb_w: Unknown Register %08x = %08x & %08x\n", 0x06000000 + (offset << 2), data, mem_mask );
r9684	r9685
281	296
282	297	static UINT32 ps_intc_get_interrupt_line(running_machine *machine, UINT32 line)
283	298	{
284		return intc_regs.status & line;
	299	pockstat_state *state = machine->driver_data<pockstat_state>();
	300	return state->intc_regs.status & line;
285	301	}
286	302
287	303	static void ps_intc_set_interrupt_line(running_machine *machine, UINT32 line, int state)
288	304	{
289		//printf( "%08x %d %08x %08x %08x\n", line, state, intc_regs.hold, intc_regs.status, intc_regs.enable );
	305	pockstat_state *drvstate = machine->driver_data<pockstat_state>();
	306	//printf( "%08x %d %08x %08x %08x\n", line, state, drvstate->intc_regs.hold, drvstate->intc_regs.status, drvstate->intc_regs.enable );
290	307	if(line)
291	308	{
292	309	if(state)
293	310	{
294		intc_regs.status |= line & PS_INT_STATUS_MASK;
295		intc_regs.hold |= line &~ PS_INT_STATUS_MASK;
296		//printf( " Setting %08x, status = %08x, hold = %08x\n", line, intc_regs.status, intc_regs.hold );
	311	drvstate->intc_regs.status |= line & PS_INT_STATUS_MASK;
	312	drvstate->intc_regs.hold |= line &~ PS_INT_STATUS_MASK;
	313	//printf( " Setting %08x, status = %08x, hold = %08x\n", line, drvstate->intc_regs.status, drvstate->intc_regs.hold );
297	314	}
298	315	else
299	316	{
300		intc_regs.status &= ~line;
301		intc_regs.hold &= ~line;
302		//printf( "Clearing %08x, status = %08x, hold = %08x\n", line, intc_regs.status, intc_regs.hold );
	317	drvstate->intc_regs.status &= ~line;
	318	drvstate->intc_regs.hold &= ~line;
	319	//printf( "Clearing %08x, status = %08x, hold = %08x\n", line, drvstate->intc_regs.status, drvstate->intc_regs.hold );
303	320	}
304	321	}
305		if(intc_regs.hold & intc_regs.enable & PS_INT_IRQ_MASK)
	322	if(drvstate->intc_regs.hold & drvstate->intc_regs.enable & PS_INT_IRQ_MASK)
306	323	{
307	324	cpu_set_input_line(machine->device("maincpu"), ARM7_IRQ_LINE, ASSERT_LINE);
308	325	}
r9684	r9685
310	327	{
311	328	cpu_set_input_line(machine->device("maincpu"), ARM7_IRQ_LINE, CLEAR_LINE);
312	329	}
313		if(intc_regs.hold & intc_regs.enable & PS_INT_FIQ_MASK)
	330	if(drvstate->intc_regs.hold & drvstate->intc_regs.enable & PS_INT_FIQ_MASK)
314	331	{
315	332	cpu_set_input_line(machine->device("maincpu"), ARM7_FIRQ_LINE, ASSERT_LINE);
316	333	}
r9684	r9685
322	339
323	340	static READ32_HANDLER( ps_intc_r )
324	341	{
	342	pockstat_state *state = space->machine->driver_data<pockstat_state>();
325	343	switch(offset)
326	344	{
327	345	case 0x0000/4:
328		verboselog(space->machine, 0, "ps_intc_r: Held Interrupt = %08x & %08x\n", intc_regs.hold, mem_mask );
329		return intc_regs.hold;
	346	verboselog(space->machine, 0, "ps_intc_r: Held Interrupt = %08x & %08x\n", state->intc_regs.hold, mem_mask );
	347	return state->intc_regs.hold;
330	348	case 0x0004/4:
331		verboselog(space->machine, 0, "ps_intc_r: Interrupt Status = %08x & %08x\n", intc_regs.status, mem_mask );
332		return intc_regs.status;
	349	verboselog(space->machine, 0, "ps_intc_r: Interrupt Status = %08x & %08x\n", state->intc_regs.status, mem_mask );
	350	return state->intc_regs.status;
333	351	case 0x0008/4:
334		verboselog(space->machine, 0, "ps_intc_r: Interrupt Enable = %08x & %08x\n", intc_regs.enable, mem_mask );
335		return intc_regs.enable;
	352	verboselog(space->machine, 0, "ps_intc_r: Interrupt Enable = %08x & %08x\n", state->intc_regs.enable, mem_mask );
	353	return state->intc_regs.enable;
336	354	case 0x000c/4:
337	355	verboselog(space->machine, 0, "ps_intc_r: Interrupt Mask (Invalid Read) = %08x & %08x\n", 0, mem_mask );
338	356	return 0;
r9684	r9685
348	366
349	367	static WRITE32_HANDLER( ps_intc_w )
350	368	{
	369	pockstat_state *state = space->machine->driver_data<pockstat_state>();
351	370	switch(offset)
352	371	{
353	372	case 0x0000/4:
r9684	r9685
358	377	break;
359	378	case 0x0008/4:
360	379	verboselog(space->machine, 0, "ps_intc_w: Interrupt Enable = %08x & %08x\n", data, mem_mask );
361		intc_regs.enable |= data;
362		//COMBINE_DATA(&intc_regs.enable);
363		//intc_regs.status &= intc_regs.enable;
364		//intc_regs.hold &= intc_regs.enable;
	380	state->intc_regs.enable |= data;
	381	//COMBINE_DATA(&state->intc_regs.enable);
	382	//state->intc_regs.status &= state->intc_regs.enable;
	383	//state->intc_regs.hold &= state->intc_regs.enable;
365	384	ps_intc_set_interrupt_line(space->machine, 0, 0);
366	385	break;
367	386	case 0x000c/4:
368	387	verboselog(space->machine, 0, "ps_intc_w: Interrupt Mask = %08x & %08x\n", data, mem_mask );
369		intc_regs.enable &= ~data;
370		COMBINE_DATA(&intc_regs.mask);
371		//intc_regs.status &= intc_regs.enable;
372		//intc_regs.hold &= intc_regs.enable;
	388	state->intc_regs.enable &= ~data;
	389	COMBINE_DATA(&state->intc_regs.mask);
	390	//state->intc_regs.status &= state->intc_regs.enable;
	391	//state->intc_regs.hold &= state->intc_regs.enable;
373	392	ps_intc_set_interrupt_line(space->machine, 0, 0);
374	393	break;
375	394	case 0x0010/4:
376	395	verboselog(space->machine, 0, "ps_intc_w: Interrupt Acknowledge = %08x & %08x\n", data, mem_mask );
377		intc_regs.hold &= ~data;
378		intc_regs.status &= ~data;
	396	state->intc_regs.hold &= ~data;
	397	state->intc_regs.status &= ~data;
379	398	ps_intc_set_interrupt_line(space->machine, 0, 0);
380		//COMBINE_DATA(&intc_regs.acknowledge);
	399	//COMBINE_DATA(&state->intc_regs.acknowledge);
381	400	break;
382	401	default:
383	402	verboselog(space->machine, 0, "ps_intc_w: Unknown Register %08x = %08x & %08x\n", 0x0a000000 + (offset << 2), data, mem_mask );
r9684	r9685
387	406
388	407	static TIMER_CALLBACK( timer_tick )
389	408	{
	409	pockstat_state *state = machine->driver_data<pockstat_state>();
390	410	ps_intc_set_interrupt_line(machine, param == 2 ? PS_INT_TIMER2 : (param == 1 ? PS_INT_TIMER1 : PS_INT_TIMER0), 1);
391	411	//printf( "Timer %d is calling back\n", param );
392		timer_regs.timer[param].count = timer_regs.timer[param].period;
	412	state->timer_regs.timer[param].count = state->timer_regs.timer[param].period;
393	413	ps_timer_start(machine, param);
394	414	}
395	415
396	416	static void ps_timer_start(running_machine *machine, int index)
397	417	{
	418	pockstat_state *state = machine->driver_data<pockstat_state>();
398	419	int divisor = 1;
399	420	attotime period;
400		switch(timer_regs.timer[index].control & 3)
	421	switch(state->timer_regs.timer[index].control & 3)
401	422	{
402	423	case 0:
403	424	case 3:
r9684	r9685
410	431	divisor = 256;
411	432	break;
412	433	}
413		period = attotime_mul(ATTOTIME_IN_HZ(CPU_FREQ[clock_regs.mode & 0x0f] / 2), divisor);
414		period = attotime_mul(period, timer_regs.timer[index].count);
415		timer_adjust_oneshot(timer_regs.timer[index].timer, period, index);
	434	period = attotime_mul(ATTOTIME_IN_HZ(CPU_FREQ[state->clock_regs.mode & 0x0f] / 2), divisor);
	435	period = attotime_mul(period, state->timer_regs.timer[index].count);
	436	timer_adjust_oneshot(state->timer_regs.timer[index].timer, period, index);
416	437	}
417	438
418	439	static READ32_HANDLER( ps_timer_r )
419	440	{
	441	pockstat_state *state = space->machine->driver_data<pockstat_state>();
420	442	switch(offset)
421	443	{
422	444	case 0x0000/4:
423	445	case 0x0010/4:
424	446	case 0x0020/4:
425		verboselog(space->machine, 0, "ps_timer_r: Timer %d Period = %08x & %08x\n", offset / (0x10/4), timer_regs.timer[offset / (0x10/4)].period, mem_mask );
426		return timer_regs.timer[offset / (0x10/4)].period;
	447	verboselog(space->machine, 0, "ps_timer_r: Timer %d Period = %08x & %08x\n", offset / (0x10/4), state->timer_regs.timer[offset / (0x10/4)].period, mem_mask );
	448	return state->timer_regs.timer[offset / (0x10/4)].period;
427	449	case 0x0004/4:
428	450	case 0x0014/4:
429	451	case 0x0024/4:
430		verboselog(space->machine, 0, "ps_timer_r: Timer %d Count = %08x & %08x\n", offset / (0x10/4), timer_regs.timer[offset / (0x10/4)].count, mem_mask );
431		if(timer_regs.timer[offset / (0x10/4)].control & 4)
	452	verboselog(space->machine, 0, "ps_timer_r: Timer %d Count = %08x & %08x\n", offset / (0x10/4), state->timer_regs.timer[offset / (0x10/4)].count, mem_mask );
	453	if(state->timer_regs.timer[offset / (0x10/4)].control & 4)
432	454	{
433		timer_regs.timer[offset / (0x10/4)].count--;
434		if(timer_regs.timer[offset / (0x10/4)].count > timer_regs.timer[offset / (0x10/4)].period)
	455	state->timer_regs.timer[offset / (0x10/4)].count--;
	456	if(state->timer_regs.timer[offset / (0x10/4)].count > state->timer_regs.timer[offset / (0x10/4)].period)
435	457	{
436		timer_regs.timer[offset / (0x10/4)].count = timer_regs.timer[offset / (0x10/4)].period;
	458	state->timer_regs.timer[offset / (0x10/4)].count = state->timer_regs.timer[offset / (0x10/4)].period;
437	459	}
438		return --timer_regs.timer[offset / (0x10/4)].count;
	460	return --state->timer_regs.timer[offset / (0x10/4)].count;
439	461	}
440		return timer_regs.timer[offset / (0x10/4)].count;
	462	return state->timer_regs.timer[offset / (0x10/4)].count;
441	463	case 0x0008/4:
442	464	case 0x0018/4:
443	465	case 0x0028/4:
444		verboselog(space->machine, 0, "ps_timer_r: Timer %d Control = %08x & %08x\n", offset / (0x10/4), timer_regs.timer[offset / (0x10/4)].control, mem_mask );
445		return timer_regs.timer[offset / (0x10/4)].control;
	466	verboselog(space->machine, 0, "ps_timer_r: Timer %d Control = %08x & %08x\n", offset / (0x10/4), state->timer_regs.timer[offset / (0x10/4)].control, mem_mask );
	467	return state->timer_regs.timer[offset / (0x10/4)].control;
446	468	default:
447	469	verboselog(space->machine, 0, "ps_timer_r: Unknown Register %08x & %08x\n", 0x0a800000 + (offset << 2), mem_mask );
448	470	break;
r9684	r9685
452	474
453	475	static WRITE32_HANDLER( ps_timer_w )
454	476	{
	477	pockstat_state *state = space->machine->driver_data<pockstat_state>();
455	478	switch(offset)
456	479	{
457	480	case 0x0000/4:
458	481	case 0x0010/4:
459	482	case 0x0020/4:
460	483	verboselog(space->machine, 0, "ps_timer_w: Timer %d Period = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
461		COMBINE_DATA(&timer_regs.timer[offset / (0x10/4)].period);
	484	COMBINE_DATA(&state->timer_regs.timer[offset / (0x10/4)].period);
462	485	break;
463	486	case 0x0004/4:
464	487	case 0x0014/4:
465	488	case 0x0024/4:
466	489	verboselog(space->machine, 0, "ps_timer_w: Timer %d Count = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
467		COMBINE_DATA(&timer_regs.timer[offset / (0x10/4)].count);
	490	COMBINE_DATA(&state->timer_regs.timer[offset / (0x10/4)].count);
468	491	break;
469	492	case 0x0008/4:
470	493	case 0x0018/4:
471	494	case 0x0028/4:
472	495	verboselog(space->machine, 0, "ps_timer_w: Timer %d Control = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
473		COMBINE_DATA(&timer_regs.timer[offset / (0x10/4)].control);
474		if(timer_regs.timer[offset / (0x10/4)].control & 4)
	496	COMBINE_DATA(&state->timer_regs.timer[offset / (0x10/4)].control);
	497	if(state->timer_regs.timer[offset / (0x10/4)].control & 4)
475	498	{
476	499	ps_timer_start(space->machine, offset / (0x10/4));
477	500	}
478	501	else
479	502	{
480		timer_adjust_oneshot(timer_regs.timer[offset / (0x10/4)].timer, attotime_never, offset / (0x10/4));
	503	timer_adjust_oneshot(state->timer_regs.timer[offset / (0x10/4)].timer, attotime_never, offset / (0x10/4));
481	504	}
482	505	break;
483	506	default:
r9684	r9685
488	511
489	512	static READ32_HANDLER( ps_clock_r )
490	513	{
	514	pockstat_state *state = space->machine->driver_data<pockstat_state>();
491	515	switch(offset)
492	516	{
493	517	case 0x0000/4:
494		verboselog(space->machine, 0, "ps_clock_r: Clock Mode = %08x & %08x\n", clock_regs.mode | 0x10, mem_mask );
495		return clock_regs.mode | PS_CLOCK_STEADY;
	518	verboselog(space->machine, 0, "ps_clock_r: Clock Mode = %08x & %08x\n", state->clock_regs.mode | 0x10, mem_mask );
	519	return state->clock_regs.mode | PS_CLOCK_STEADY;
496	520	case 0x0004/4:
497		verboselog(space->machine, 0, "ps_clock_r: Clock Control = %08x & %08x\n", clock_regs.control, mem_mask );
498		return clock_regs.control;
	521	verboselog(space->machine, 0, "ps_clock_r: Clock Control = %08x & %08x\n", state->clock_regs.control, mem_mask );
	522	return state->clock_regs.control;
499	523	default:
500	524	verboselog(space->machine, 0, "ps_clock_r: Unknown Register %08x & %08x\n", 0x0b000000 + (offset << 2), mem_mask );
501	525	break;
r9684	r9685
505	529
506	530	static WRITE32_HANDLER( ps_clock_w )
507	531	{
	532	pockstat_state *state = space->machine->driver_data<pockstat_state>();
508	533	switch(offset)
509	534	{
510	535	case 0x0000/4:
511	536	verboselog(space->machine, 0, "ps_clock_w: Clock Mode = %08x & %08x\n", data, mem_mask );
512		COMBINE_DATA(&clock_regs.mode);
513		cputag_set_clock(space->machine, "maincpu", CPU_FREQ[clock_regs.mode & 0x0f]);
	537	COMBINE_DATA(&state->clock_regs.mode);
	538	cputag_set_clock(space->machine, "maincpu", CPU_FREQ[state->clock_regs.mode & 0x0f]);
514	539	break;
515	540	case 0x0004/4:
516	541	verboselog(space->machine, 0, "ps_clock_w: Clock Control = %08x & %08x\n", data, mem_mask );
517		COMBINE_DATA(&clock_regs.control);
	542	COMBINE_DATA(&state->clock_regs.control);
518	543	break;
519	544	default:
520	545	verboselog(space->machine, 0, "ps_clock_w: Unknown Register %08x = %08x & %08x\n", 0x0b000000 + (offset << 2), data, mem_mask );
r9684	r9685
524	549
525	550	static TIMER_CALLBACK( rtc_tick )
526	551	{
	552	pockstat_state *state = machine->driver_data<pockstat_state>();
527	553	//printf( "RTC is calling back\n" );
528	554	ps_intc_set_interrupt_line(machine, PS_INT_RTC, ps_intc_get_interrupt_line(machine, PS_INT_RTC) ? 0 : 1);
529		if(!(rtc_regs.mode & 1))
	555	if(!(state->rtc_regs.mode & 1))
530	556	{
531		rtc_regs.time++;
532		if((rtc_regs.time & 0x0000000f) == 0x0000000a)
	557	state->rtc_regs.time++;
	558	if((state->rtc_regs.time & 0x0000000f) == 0x0000000a)
533	559	{
534		rtc_regs.time &= 0xfffffff0;
535		rtc_regs.time += 0x00000010;
536		if((rtc_regs.time & 0x000000ff) == 0x00000060)
	560	state->rtc_regs.time &= 0xfffffff0;
	561	state->rtc_regs.time += 0x00000010;
	562	if((state->rtc_regs.time & 0x000000ff) == 0x00000060)
537	563	{
538		rtc_regs.time &= 0xffffff00;
539		rtc_regs.time += 0x00000100;
540		if((rtc_regs.time & 0x00000f00) == 0x00000a00)
	564	state->rtc_regs.time &= 0xffffff00;
	565	state->rtc_regs.time += 0x00000100;
	566	if((state->rtc_regs.time & 0x00000f00) == 0x00000a00)
541	567	{
542		rtc_regs.time &= 0xfffff0ff;
543		rtc_regs.time += 0x00001000;
544		if((rtc_regs.time & 0x0000ff00) == 0x00006000)
	568	state->rtc_regs.time &= 0xfffff0ff;
	569	state->rtc_regs.time += 0x00001000;
	570	if((state->rtc_regs.time & 0x0000ff00) == 0x00006000)
545	571	{
546		rtc_regs.time &= 0xffff00ff;
547		rtc_regs.time += 0x00010000;
548		if((rtc_regs.time & 0x00ff0000) == 0x00240000)
	572	state->rtc_regs.time &= 0xffff00ff;
	573	state->rtc_regs.time += 0x00010000;
	574	if((state->rtc_regs.time & 0x00ff0000) == 0x00240000)
549	575	{
550		rtc_regs.time &= 0xff00ffff;
551		rtc_regs.time += 0x01000000;
552		if((rtc_regs.time & 0x0f000000) == 0x08000000)
	576	state->rtc_regs.time &= 0xff00ffff;
	577	state->rtc_regs.time += 0x01000000;
	578	if((state->rtc_regs.time & 0x0f000000) == 0x08000000)
553	579	{
554		rtc_regs.time &= 0xf0ffffff;
555		rtc_regs.time |= 0x01000000;
	580	state->rtc_regs.time &= 0xf0ffffff;
	581	state->rtc_regs.time |= 0x01000000;
556	582	}
557	583	}
558		else if((rtc_regs.time & 0x000f0000) == 0x000a0000)
	584	else if((state->rtc_regs.time & 0x000f0000) == 0x000a0000)
559	585	{
560		rtc_regs.time &= 0xfff0ffff;
561		rtc_regs.time += 0x00100000;
	586	state->rtc_regs.time &= 0xfff0ffff;
	587	state->rtc_regs.time += 0x00100000;
562	588	}
563	589	}
564	590	}
565	591	}
566	592	}
567	593	}
568		timer_adjust_oneshot(rtc_regs.timer, ATTOTIME_IN_HZ(1), 0);
	594	timer_adjust_oneshot(state->rtc_regs.timer, ATTOTIME_IN_HZ(1), 0);
569	595	}
570	596
571	597	static READ32_HANDLER( ps_rtc_r )
572	598	{
	599	pockstat_state *state = space->machine->driver_data<pockstat_state>();
573	600	switch(offset)
574	601	{
575	602	case 0x0000/4:
576		verboselog(space->machine, 0, "ps_rtc_r: RTC Mode = %08x & %08x\n", rtc_regs.mode, mem_mask );
577		return rtc_regs.mode;
	603	verboselog(space->machine, 0, "ps_rtc_r: RTC Mode = %08x & %08x\n", state->rtc_regs.mode, mem_mask );
	604	return state->rtc_regs.mode;
578	605	case 0x0004/4:
579		verboselog(space->machine, 0, "ps_rtc_r: RTC Control = %08x & %08x\n", rtc_regs.control, mem_mask );
580		return rtc_regs.control;
	606	verboselog(space->machine, 0, "ps_rtc_r: RTC Control = %08x & %08x\n", state->rtc_regs.control, mem_mask );
	607	return state->rtc_regs.control;
581	608	case 0x0008/4:
582		verboselog(space->machine, 0, "ps_rtc_r: RTC Time = %08x & %08x\n", rtc_regs.time, mem_mask );
583		return rtc_regs.time;
	609	verboselog(space->machine, 0, "ps_rtc_r: RTC Time = %08x & %08x\n", state->rtc_regs.time, mem_mask );
	610	return state->rtc_regs.time;
584	611	case 0x000c/4:
585		verboselog(space->machine, 0, "ps_rtc_r: RTC Date = %08x & %08x\n", rtc_regs.date, mem_mask );
586		return rtc_regs.date;
	612	verboselog(space->machine, 0, "ps_rtc_r: RTC Date = %08x & %08x\n", state->rtc_regs.date, mem_mask );
	613	return state->rtc_regs.date;
587	614	default:
588	615	verboselog(space->machine, 0, "ps_rtc_r: Unknown Register %08x & %08x\n", 0x0b800000 + (offset << 2), mem_mask );
589	616	break;
r9684	r9685
593	620
594	621	static WRITE32_HANDLER( ps_rtc_w )
595	622	{
	623	pockstat_state *state = space->machine->driver_data<pockstat_state>();
596	624	switch(offset)
597	625	{
598	626	case 0x0000/4:
599	627	verboselog(space->machine, 0, "ps_rtc_w: RTC Mode = %08x & %08x\n", data, mem_mask );
600		COMBINE_DATA(&rtc_regs.mode);
	628	COMBINE_DATA(&state->rtc_regs.mode);
601	629	break;
602	630	case 0x0004/4:
603	631	verboselog(space->machine, 0, "ps_rtc_w: RTC Control = %08x & %08x\n", data, mem_mask );
604		if(rtc_regs.control == 1 && data == 1)
	632	if(state->rtc_regs.control == 1 && data == 1)
605	633	{
606		switch(rtc_regs.mode >> 1)
	634	switch(state->rtc_regs.mode >> 1)
607	635	{
608	636	case 0: // Seconds
609		rtc_regs.time += 0x00000001;
610		if((rtc_regs.time & 0x0000000f) == 0x0000000a)
	637	state->rtc_regs.time += 0x00000001;
	638	if((state->rtc_regs.time & 0x0000000f) == 0x0000000a)
611	639	{
612		rtc_regs.time &= 0xfffffff0;
613		rtc_regs.time += 0x00000010;
614		if((rtc_regs.time & 0x000000ff) == 0x00000060)
	640	state->rtc_regs.time &= 0xfffffff0;
	641	state->rtc_regs.time += 0x00000010;
	642	if((state->rtc_regs.time & 0x000000ff) == 0x00000060)
615	643	{
616		rtc_regs.time &= 0xffffff00;
	644	state->rtc_regs.time &= 0xffffff00;
617	645	}
618	646	}
619	647	break;
620	648	case 1: // Minutes
621		rtc_regs.time += 0x00000100;
622		if((rtc_regs.time & 0x00000f00) == 0x00000a00)
	649	state->rtc_regs.time += 0x00000100;
	650	if((state->rtc_regs.time & 0x00000f00) == 0x00000a00)
623	651	{
624		rtc_regs.time &= 0xfffff0ff;
625		rtc_regs.time += 0x00001000;
626		if((rtc_regs.time & 0x0000ff00) == 0x00006000)
	652	state->rtc_regs.time &= 0xfffff0ff;
	653	state->rtc_regs.time += 0x00001000;
	654	if((state->rtc_regs.time & 0x0000ff00) == 0x00006000)
627	655	{
628		rtc_regs.time &= 0xffff00ff;
	656	state->rtc_regs.time &= 0xffff00ff;
629	657	}
630	658	}
631	659	break;
632	660	case 2: // Hours
633		rtc_regs.time += 0x00010000;
634		if((rtc_regs.time & 0x00ff0000) == 0x00240000)
	661	state->rtc_regs.time += 0x00010000;
	662	if((state->rtc_regs.time & 0x00ff0000) == 0x00240000)
635	663	{
636		rtc_regs.time &= 0xff00ffff;
	664	state->rtc_regs.time &= 0xff00ffff;
637	665	}
638		else if((rtc_regs.time & 0x000f0000) == 0x000a0000)
	666	else if((state->rtc_regs.time & 0x000f0000) == 0x000a0000)
639	667	{
640		rtc_regs.time &= 0xfff0ffff;
641		rtc_regs.time += 0x00100000;
	668	state->rtc_regs.time &= 0xfff0ffff;
	669	state->rtc_regs.time += 0x00100000;
642	670	}
643	671	break;
644	672	case 3: // Day of the week
645		rtc_regs.time += 0x01000000;
646		if((rtc_regs.time & 0x0f000000) == 0x08000000)
	673	state->rtc_regs.time += 0x01000000;
	674	if((state->rtc_regs.time & 0x0f000000) == 0x08000000)
647	675	{
648		rtc_regs.time &= 0xf0ffffff;
649		rtc_regs.time |= 0x01000000;
	676	state->rtc_regs.time &= 0xf0ffffff;
	677	state->rtc_regs.time |= 0x01000000;
650	678	}
651	679	break;
652	680	case 4: // Day
653		rtc_regs.date += 0x00000001;
654		if((rtc_regs.date & 0x000000ff) == 0x00000032)
	681	state->rtc_regs.date += 0x00000001;
	682	if((state->rtc_regs.date & 0x000000ff) == 0x00000032)
655	683	{
656		rtc_regs.date &= 0xffffff00;
	684	state->rtc_regs.date &= 0xffffff00;
657	685	}
658		else if((rtc_regs.date & 0x0000000f) == 0x0000000a)
	686	else if((state->rtc_regs.date & 0x0000000f) == 0x0000000a)
659	687	{
660		rtc_regs.date &= 0xfffffff0;
661		rtc_regs.date += 0x00000010;
	688	state->rtc_regs.date &= 0xfffffff0;
	689	state->rtc_regs.date += 0x00000010;
662	690	}
663	691	break;
664	692	case 5: // Month
665		rtc_regs.date += 0x00000100;
666		if((rtc_regs.date & 0x0000ff00) == 0x00001300)
	693	state->rtc_regs.date += 0x00000100;
	694	if((state->rtc_regs.date & 0x0000ff00) == 0x00001300)
667	695	{
668		rtc_regs.date &= 0xffffff00;
669		rtc_regs.date |= 0x00000001;
	696	state->rtc_regs.date &= 0xffffff00;
	697	state->rtc_regs.date |= 0x00000001;
670	698	}
671		else if((rtc_regs.date & 0x00000f00) == 0x00000a00)
	699	else if((state->rtc_regs.date & 0x00000f00) == 0x00000a00)
672	700	{
673		rtc_regs.date &= 0xfffff0ff;
674		rtc_regs.date += 0x00001000;
	701	state->rtc_regs.date &= 0xfffff0ff;
	702	state->rtc_regs.date += 0x00001000;
675	703	}
676	704	break;
677	705	case 6: // Year (LSB)
678		rtc_regs.date += 0x00010000;
679		if((rtc_regs.date & 0x000f0000) == 0x000a0000)
	706	state->rtc_regs.date += 0x00010000;
	707	if((state->rtc_regs.date & 0x000f0000) == 0x000a0000)
680	708	{
681		rtc_regs.date &= 0xfff0ffff;
682		rtc_regs.date += 0x00100000;
683		if((rtc_regs.date & 0x00f00000) == 0x00a00000)
	709	state->rtc_regs.date &= 0xfff0ffff;
	710	state->rtc_regs.date += 0x00100000;
	711	if((state->rtc_regs.date & 0x00f00000) == 0x00a00000)
684	712	{
685		rtc_regs.date &= 0xff00ffff;
	713	state->rtc_regs.date &= 0xff00ffff;
686	714	}
687	715	}
688	716	break;
689	717	case 7: // Year (MSB)
690	718	break;
691	719	}
692		rtc_regs.control = 0;
	720	state->rtc_regs.control = 0;
693	721	}
694		else if(rtc_regs.control == 0)
	722	else if(state->rtc_regs.control == 0)
695	723	{
696		COMBINE_DATA(&rtc_regs.control);
	724	COMBINE_DATA(&state->rtc_regs.control);
697	725	}
698	726	break;
699	727	default:
r9684	r9685
702	730	}
703	731	}
704	732
705		static UINT32 lcd_control;
706	733
707	734	static READ32_HANDLER( ps_lcd_r )
708	735	{
	736	pockstat_state *state = space->machine->driver_data<pockstat_state>();
709	737	switch(offset)
710	738	{
711	739	case 0x0000/4:
712		verboselog(space->machine, 0, "ps_lcd_r: LCD Control = %08x & %08x\n", lcd_control | 0x100, mem_mask );
713		return lcd_control;
	740	verboselog(space->machine, 0, "ps_lcd_r: LCD Control = %08x & %08x\n", state->lcd_control | 0x100, mem_mask );
	741	return state->lcd_control;
714	742	default:
715	743	verboselog(space->machine, 0, "ps_lcd_r: Unknown Register %08x & %08x\n", 0x0d000000 + (offset << 2), mem_mask );
716	744	break;
r9684	r9685
720	748
721	749	static WRITE32_HANDLER( ps_lcd_w )
722	750	{
	751	pockstat_state *state = space->machine->driver_data<pockstat_state>();
723	752	switch(offset)
724	753	{
725	754	case 0x0000/4:
726	755	verboselog(space->machine, 0, "ps_lcd_w: LCD Control = %08x & %08x\n", data, mem_mask );
727		COMBINE_DATA(&lcd_control);
	756	COMBINE_DATA(&state->lcd_control);
728	757	break;
729	758	default:
730	759	verboselog(space->machine, 0, "ps_lcd_w: Unknown Register %08x = %08x & %08x\n", 0x0d000000 + (offset << 2), data, mem_mask );
r9684	r9685
745	774
746	775	static READ32_HANDLER(ps_rombank_r)
747	776	{
	777	pockstat_state *state = space->machine->driver_data<pockstat_state>();
748	778	INT32 bank = (offset >> 11) & 0x0f;
749	779	int index = 0;
750	780	for(index = 0; index < 32; index++)
751	781	{
752		if(ftlb_regs.valid & (1 << index))
	782	if(state->ftlb_regs.valid & (1 << index))
753	783	{
754		if(ftlb_regs.entry[index] == bank)
	784	if(state->ftlb_regs.entry[index] == bank)
755	785	{
756	786	//printf( "Address %08x is assigned to %08x in entry %d\n", 0x02000000 + (offset << 2), index * 0x2000 + ((offset << 2) & 0x1fff), index );
757	787	return ((UINT32*)memory_region(space->machine, "flash"))[index * (0x2000/4) + (offset & (0x1fff/4))];
r9684	r9685
761	791	return ((UINT32*)memory_region(space->machine, "flash"))[offset & 0x7fff];
762	792	}
763	793
764		static INT32 ps_flash_write_enable_count;
765		static INT32 ps_flash_write_count;
766	794
767	795	// Horrible hack, probably wrong
768	796	static WRITE32_HANDLER(ps_flash_w)
769	797	{
	798	pockstat_state *state = space->machine->driver_data<pockstat_state>();
770	799	if(offset == (0x55a8/4))
771	800	{
772		ps_flash_write_enable_count++;
	801	state->ps_flash_write_enable_count++;
773	802	return;
774	803	}
775	804	if(offset == (0x2a54/4))
776	805	{
777		ps_flash_write_enable_count++;
	806	state->ps_flash_write_enable_count++;
778	807	return;
779	808	}
780		if(ps_flash_write_enable_count == 3)
	809	if(state->ps_flash_write_enable_count == 3)
781	810	{
782		ps_flash_write_enable_count = 0;
783		ps_flash_write_count = 0x40;
	811	state->ps_flash_write_enable_count = 0;
	812	state->ps_flash_write_count = 0x40;
784	813	return;
785	814	}
786		if(ps_flash_write_count)
	815	if(state->ps_flash_write_count)
787	816	{
788		ps_flash_write_count--;
	817	state->ps_flash_write_count--;
789	818	COMBINE_DATA(&((UINT32*)memory_region(space->machine, "flash"))[offset]);
790	819	}
791	820	}
r9684	r9685
817	846	AM_RANGE(0x0b000000, 0x0b000007) AM_READWRITE(ps_clock_r, ps_clock_w)
818	847	AM_RANGE(0x0b800000, 0x0b80000f) AM_READWRITE(ps_rtc_r, ps_rtc_w)
819	848	AM_RANGE(0x0d000000, 0x0d000003) AM_READWRITE(ps_lcd_r, ps_lcd_w)
820		AM_RANGE(0x0d000100, 0x0d00017f) AM_RAM AM_BASE(&lcd_buffer)
	849	AM_RANGE(0x0d000100, 0x0d00017f) AM_RAM AM_BASE_MEMBER(pockstat_state, lcd_buffer)
821	850	AM_RANGE(0x0d80000c, 0x0d80000f) AM_READWRITE(ps_audio_r, ps_audio_w)
822	851	AM_RANGE(0x0d800014, 0x0d800017) AM_WRITE(ps_dac_w)
823	852	ADDRESS_MAP_END
r9684	r9685
835	864
836	865	static MACHINE_START( pockstat )
837	866	{
	867	pockstat_state *state = machine->driver_data<pockstat_state>();
838	868	int index = 0;
839	869	for(index = 0; index < 3; index++)
840	870	{
841		timer_regs.timer[index].timer = timer_alloc(machine, timer_tick, 0);
842		timer_adjust_oneshot(timer_regs.timer[index].timer, attotime_never, index);
	871	state->timer_regs.timer[index].timer = timer_alloc(machine, timer_tick, 0);
	872	timer_adjust_oneshot(state->timer_regs.timer[index].timer, attotime_never, index);
843	873	}
844	874
845		rtc_regs.time = 0x01000000;
846		rtc_regs.date = 0x19990101;
	875	state->rtc_regs.time = 0x01000000;
	876	state->rtc_regs.date = 0x19990101;
847	877
848		rtc_regs.timer = timer_alloc(machine, rtc_tick, 0);
849		timer_adjust_oneshot(rtc_regs.timer, ATTOTIME_IN_HZ(1), index);
	878	state->rtc_regs.timer = timer_alloc(machine, rtc_tick, 0);
	879	timer_adjust_oneshot(state->rtc_regs.timer, ATTOTIME_IN_HZ(1), index);
850	880
851		state_save_register_global(machine, ftlb_regs.control);
852		state_save_register_global(machine, ftlb_regs.stat);
853		state_save_register_global(machine, ftlb_regs.valid);
854		state_save_register_global(machine, ftlb_regs.wait1);
855		state_save_register_global(machine, ftlb_regs.wait2);
856		state_save_register_global_array(machine, ftlb_regs.entry);
	881	state_save_register_global(machine, state->ftlb_regs.control);
	882	state_save_register_global(machine, state->ftlb_regs.stat);
	883	state_save_register_global(machine, state->ftlb_regs.valid);
	884	state_save_register_global(machine, state->ftlb_regs.wait1);
	885	state_save_register_global(machine, state->ftlb_regs.wait2);
	886	state_save_register_global_array(machine, state->ftlb_regs.entry);
857	887
858		state_save_register_global(machine, intc_regs.hold);
859		state_save_register_global(machine, intc_regs.status);
860		state_save_register_global(machine, intc_regs.enable);
861		state_save_register_global(machine, intc_regs.mask);
	888	state_save_register_global(machine, state->intc_regs.hold);
	889	state_save_register_global(machine, state->intc_regs.status);
	890	state_save_register_global(machine, state->intc_regs.enable);
	891	state_save_register_global(machine, state->intc_regs.mask);
862	892
863		state_save_register_global(machine, timer_regs.timer[0].period);
864		state_save_register_global(machine, timer_regs.timer[0].count);
865		state_save_register_global(machine, timer_regs.timer[0].control);
866		state_save_register_global(machine, timer_regs.timer[1].period);
867		state_save_register_global(machine, timer_regs.timer[1].count);
868		state_save_register_global(machine, timer_regs.timer[1].control);
869		state_save_register_global(machine, timer_regs.timer[2].period);
870		state_save_register_global(machine, timer_regs.timer[2].count);
871		state_save_register_global(machine, timer_regs.timer[2].control);
	893	state_save_register_global(machine, state->timer_regs.timer[0].period);
	894	state_save_register_global(machine, state->timer_regs.timer[0].count);
	895	state_save_register_global(machine, state->timer_regs.timer[0].control);
	896	state_save_register_global(machine, state->timer_regs.timer[1].period);
	897	state_save_register_global(machine, state->timer_regs.timer[1].count);
	898	state_save_register_global(machine, state->timer_regs.timer[1].control);
	899	state_save_register_global(machine, state->timer_regs.timer[2].period);
	900	state_save_register_global(machine, state->timer_regs.timer[2].count);
	901	state_save_register_global(machine, state->timer_regs.timer[2].control);
872	902
873		state_save_register_global(machine, clock_regs.mode);
874		state_save_register_global(machine, clock_regs.control);
	903	state_save_register_global(machine, state->clock_regs.mode);
	904	state_save_register_global(machine, state->clock_regs.control);
875	905
876		state_save_register_global(machine, rtc_regs.mode);
877		state_save_register_global(machine, rtc_regs.control);
878		state_save_register_global(machine, rtc_regs.time);
879		state_save_register_global(machine, rtc_regs.date);
	906	state_save_register_global(machine, state->rtc_regs.mode);
	907	state_save_register_global(machine, state->rtc_regs.control);
	908	state_save_register_global(machine, state->rtc_regs.time);
	909	state_save_register_global(machine, state->rtc_regs.date);
880	910
881		state_save_register_global(machine, ps_flash_write_enable_count);
882		state_save_register_global(machine, ps_flash_write_count);
	911	state_save_register_global(machine, state->ps_flash_write_enable_count);
	912	state_save_register_global(machine, state->ps_flash_write_count);
883	913	}
884	914
885	915	static MACHINE_RESET( pockstat )
886	916	{
	917	pockstat_state *state = machine->driver_data<pockstat_state>();
887	918	cpu_set_reg(machine->device("maincpu"), STATE_GENPC, 0x4000000);
888	919
889		ps_flash_write_enable_count = 0;
890		ps_flash_write_count = 0;
	920	state->ps_flash_write_enable_count = 0;
	921	state->ps_flash_write_count = 0;
891	922	}
892	923
893	924	static VIDEO_UPDATE( pockstat )
894	925	{
	926	pockstat_state *state = screen->machine->driver_data<pockstat_state>();
895	927	int x = 0;
896	928	int y = 0;
897	929	for(y = 0; y < 32; y++)
r9684	r9685
899	931	UINT32 *scanline = BITMAP_ADDR32(bitmap, y, 0);
900	932	for(x = 0; x < 32; x++)
901	933	{
902		if(lcd_control != 0) // Hack
	934	if(state->lcd_control != 0) // Hack
903	935	{
904		if(lcd_buffer[y] & (1 << x))
	936	if(state->lcd_buffer[y] & (1 << x))
905	937	{
906	938	scanline[x] = 0x00000000;
907	939	}
r9684	r9685
945	977	return IMAGE_INIT_PASS;
946	978	}
947	979
948		static MACHINE_CONFIG_START( pockstat, driver_device )
	980	static MACHINE_CONFIG_START( pockstat, pockstat_state )
949	981	/* basic machine hardware */
950	982	MDRV_CPU_ADD("maincpu", ARM7, DEFAULT_CLOCK)
951	983	MDRV_CPU_PROGRAM_MAP(pockstat_mem)

src/mess/drivers/ob68k1a.c

r9684	r9685
9	9	#include "emu.h"
10	10	#include "cpu/m68000/m68000.h"
11	11
12		static UINT16* ob68k1a_ram;
13	12
	13	class ob68k1a_state : public driver_device
	14	{
	15	public:
	16	ob68k1a_state(running_machine &machine, const driver_device_config_base &config)
	17	: driver_device(machine, config) { }
	18
	19	UINT16* ram;
	20	};
	21
	22
	23
14	24	static ADDRESS_MAP_START(ob68k1a_mem, ADDRESS_SPACE_PROGRAM, 16)
15	25	ADDRESS_MAP_UNMAP_HIGH
16		AM_RANGE(0x00000000, 0x00007fff) AM_RAM AM_BASE(&ob68k1a_ram) // 32 KB RAM up to 128K
	26	AM_RANGE(0x00000000, 0x00007fff) AM_RAM AM_BASE_MEMBER(ob68k1a_state, ram) // 32 KB RAM up to 128K
17	27	AM_RANGE(0x00fe0000, 0x00feffff) AM_ROM AM_REGION("user1",0)
18	28	ADDRESS_MAP_END
19	29
r9684	r9685
23	33
24	34
25	35	static MACHINE_RESET(ob68k1a)
26		{
	36	{
	37	ob68k1a_state *state = machine->driver_data<ob68k1a_state>();
27	38	UINT8* user1 = memory_region(machine, "user1");
28	39
29		memcpy((UINT8*)ob68k1a_ram,user1,0x8000);
	40	memcpy((UINT8*)state->ram,user1,0x8000);
30	41
31	42	machine->device("maincpu")->reset();
32	43	}
r9684	r9685
40	51	return 0;
41	52	}
42	53
43		static MACHINE_CONFIG_START( ob68k1a, driver_device )
	54	static MACHINE_CONFIG_START( ob68k1a, ob68k1a_state )
44	55	/* basic machine hardware */
45	56	MDRV_CPU_ADD("maincpu",M68000, XTAL_10MHz)
46	57	MDRV_CPU_PROGRAM_MAP(ob68k1a_mem)

src/mess/drivers/nanos.c

r9684	r9685
17	17	#include "formats/basicdsk.h"
18	18	#include "devices/messram.h"
19	19
20		static const UINT8 *FNT;
21	20
	21	class nanos_state : public driver_device
	22	{
	23	public:
	24	nanos_state(running_machine &machine, const driver_device_config_base &config)
	25	: driver_device(machine, config) { }
	26
	27	const UINT8 *FNT;
	28	UINT8 key_command;
	29	UINT8 last_code;
	30	UINT8 key_pressed;
	31	};
	32
	33
	34
22	35	static ADDRESS_MAP_START(nanos_mem, ADDRESS_SPACE_PROGRAM, 8)
23	36	AM_RANGE( 0x0000, 0x0fff ) AM_READ_BANK("bank1") AM_WRITE_BANK("bank3")
24	37	AM_RANGE( 0x1000, 0xffff ) AM_RAMBANK("bank2")
r9684	r9685
227	240
228	241	static VIDEO_START( nanos )
229	242	{
230		FNT = memory_region(machine, "gfx1");
	243	nanos_state *state = machine->driver_data<nanos_state>();
	244	state->FNT = memory_region(machine, "gfx1");
231	245	}
232	246
233	247	static VIDEO_UPDATE( nanos )
234	248	{
	249	nanos_state *state = screen->machine->driver_data<nanos_state>();
235	250	//  static UINT8 framecnt=0;
236	251	UINT8 y,ra,chr,gfx;
237	252	UINT16 sy=0,ma=0,x;
r9684	r9685
251	266	chr = messram_get_ptr(screen->machine->device("messram"))[0xf800+ x];
252	267
253	268	/* get pattern of pixels for that character scanline */
254		gfx = FNT[(chr<<3) | ra ];
	269	gfx = state->FNT[(chr<<3) | ra ];
255	270	}
256	271	else
257	272	gfx = 0;
r9684	r9685
272	287	return 0;
273	288	}
274	289
275		static UINT8 key_command;
276		static UINT8 last_code = 0;
277		static UINT8 key_pressed;
278	290	static READ8_DEVICE_HANDLER (nanos_port_a_r)
279	291	{
	292	nanos_state *state = device->machine->driver_data<nanos_state>();
280	293	UINT8 retVal;
281		if (key_command==0)  {
282		return key_pressed;
	294	if (state->key_command==0)  {
	295	return state->key_pressed;
283	296	} else {
284		retVal = last_code;
285		last_code = 0;
	297	retVal = state->last_code;
	298	state->last_code = 0;
286	299	return retVal;
287	300	}
288	301	}
r9684	r9685
295	308
296	309	static WRITE8_DEVICE_HANDLER (nanos_port_b_w)
297	310	{
298		key_command = BIT(data,1);
	311	nanos_state *state = device->machine->driver_data<nanos_state>();
	312	state->key_command = BIT(data,1);
299	313	if (BIT(data,7)) {
300	314	memory_set_bankptr(device->machine, "bank1", memory_region(device->machine, "maincpu"));
301	315	} else {
r9684	r9685
316	330
317	331	static TIMER_CALLBACK(keyboard_callback)
318	332	{
	333	nanos_state *state = machine->driver_data<nanos_state>();
319	334	static const char *const keynames[] = { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6" };
320	335
321	336	int i;
r9684	r9685
323	338	UINT8 key_code = 0;
324	339	UINT8 shift = input_port_read(machine, "LINEC") & 0x02 ? 1 : 0;
325	340	UINT8 ctrl =  input_port_read(machine, "LINEC") & 0x01 ? 1 : 0;
326		key_pressed = 0xff;
	341	state->key_pressed = 0xff;
327	342	for(i = 0; i < 7; i++)
328	343	{
329	344
r9684	r9685
389	404	case 7: key_code = 0x0A; break; // LF
390	405	}
391	406	}
392		last_code = key_code;
	407	state->last_code = key_code;
393	408	}
394	409	}
395	410	if (key_code==0){
396		key_pressed = 0xf7;
	411	state->key_pressed = 0xf7;
397	412	}
398	413	}
399	414
400	415	static MACHINE_START(nanos)
401	416	{
402		key_pressed = 0xff;
	417	nanos_state *state = machine->driver_data<nanos_state>();
	418	state->key_pressed = 0xff;
403	419	timer_pulse(machine, ATTOTIME_IN_HZ(24000), NULL, 0, keyboard_callback);
404	420	}
405	421
r9684	r9685
478	494	GFXDECODE_ENTRY( "gfx1", 0x0000, nanos_charlayout, 0, 1 )
479	495	GFXDECODE_END
480	496
481		static MACHINE_CONFIG_START( nanos, driver_device )
	497	static MACHINE_CONFIG_START( nanos, nanos_state )
482	498	/* basic machine hardware */
483	499	MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
484	500	MDRV_CPU_PROGRAM_MAP(nanos_mem)

src/mess/drivers/pv1000.c

r9684	r9685
14	14	DEFINE_LEGACY_SOUND_DEVICE(PV1000,pv1000_sound);
15	15
16	16
17		class d65010_state : public driver_device {
	17	class d65010_state : public driver_device
	18	{
18	19	public:
19	20	d65010_state(running_machine &machine, const driver_device_config_base &config)
20	21	: driver_device(machine, config) { }
r9684	r9685
34	35
35	36	running_device *maincpu;
36	37	screen_device *screen;
	38	UINT8 *ram;
37	39	};
38	40
39	41
40		static UINT8 *pv1000_ram;
41
42
43	42	static WRITE8_HANDLER( pv1000_io_w );
44	43	static READ8_HANDLER( pv1000_io_r );
45	44	static WRITE8_HANDLER( pv1000_gfxram_w );
r9684	r9685
47	46
48	47	static ADDRESS_MAP_START( pv1000, ADDRESS_SPACE_PROGRAM, 8 )
49	48	AM_RANGE( 0x0000, 0x3fff ) AM_MIRROR( 0x4000 ) AM_ROM AM_REGION( "cart", 0 )
50		AM_RANGE( 0xb800, 0xbbff ) AM_RAM AM_BASE( &pv1000_ram )
	49	AM_RANGE( 0xb800, 0xbbff ) AM_RAM AM_BASE_MEMBER( d65010_state, ram )
51	50	AM_RANGE( 0xbc00, 0xbfff ) AM_RAM_WRITE( pv1000_gfxram_w ) AM_REGION( "gfxram", 0 )
52	51	ADDRESS_MAP_END
53	52
r9684	r9685
220	219	{
221	220	for ( x = 0; x < 32; x++ )
222	221	{
223		UINT16 tile = pv1000_ram[ y * 32 + x ];
	222	UINT16 tile = state->ram[ y * 32 + x ];
224	223
225	224	if ( tile < 0xe0 )
226	225	{

src/mess/drivers/prestige.c

r9684	r9685
79	79	#include "devices/messram.h"
80	80	#include "devices/cartslot.h"
81	81
82		static UINT8 bank[6];
83	82
	83	class prestige_state : public driver_device
	84	{
	85	public:
	86	prestige_state(running_machine &machine, const driver_device_config_base &config)
	87	: driver_device(machine, config) { }
	88
	89	UINT8 bank[6];
	90	};
	91
	92
	93
84	94	static READ8_HANDLER( bankswitch_r )
85	95	{
86		return bank[offset];
	96	prestige_state *state = space->machine->driver_data<prestige_state>();
	97	return state->bank[offset];
87	98	}
88	99
89	100	static WRITE8_HANDLER( bankswitch_w )
90	101	{
	102	prestige_state *state = space->machine->driver_data<prestige_state>();
91	103	address_space *program = cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
92	104
93	105	switch (offset)
r9684	r9685
101	113	break;
102	114
103	115	case 2:
104		if (bank[5] == 0x0c)
	116	if (state->bank[5] == 0x0c)
105	117	{
106	118	memory_set_bank(space->machine, "bank3", 0x40 + BIT(data, 7));
107	119	}
r9684	r9685
130	142	}
131	143	}
132	144
133		bank[offset] = data;
	145	state->bank[offset] = data;
134	146	}
135	147
136	148	static ADDRESS_MAP_START(prestige_mem, ADDRESS_SPACE_PROGRAM, 8)
r9684	r9685
210	222	return IMAGE_INIT_FAIL;
211	223	}
212	224
213		static MACHINE_CONFIG_START( prestige, driver_device )
	225	static MACHINE_CONFIG_START( prestige, prestige_state )
214	226	/* basic machine hardware */
215	227	MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
216	228	MDRV_CPU_PROGRAM_MAP(prestige_mem)

src/mess/drivers/pk8000.c

r9684	r9685
17	17	#include "includes/pk8000.h"
18	18	#include "devices/messram.h"
19	19
20		static UINT8 keyboard_line;
21	20
	21	class pk8000_state : public driver_device
	22	{
	23	public:
	24	pk8000_state(running_machine &machine, const driver_device_config_base &config)
	25	: driver_device(machine, config) { }
	26
	27	UINT8 keyboard_line;
	28	};
	29
	30
	31
22	32	static running_device *cassette_device_image(running_machine *machine)
23	33	{
24	34	return machine->device("cassette");
r9684	r9685
89	99
90	100	static READ8_DEVICE_HANDLER(pk8000_80_portb_r)
91	101	{
	102	pk8000_state *state = device->machine->driver_data<pk8000_state>();
92	103	static const char *const keynames[] = { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7", "LINE8", "LINE9" };
93		if(keyboard_line>9) {
	104	if(state->keyboard_line>9) {
94	105	return 0xff;
95	106	}
96		return input_port_read(device->machine,keynames[keyboard_line]);
	107	return input_port_read(device->machine,keynames[state->keyboard_line]);
97	108	}
98	109
99	110	static WRITE8_DEVICE_HANDLER(pk8000_80_portc_w)
100	111	{
101		keyboard_line = data & 0x0f;
	112	pk8000_state *state = device->machine->driver_data<pk8000_state>();
	113	state->keyboard_line = data & 0x0f;
102	114
103	115	speaker_level_w(device->machine->device("speaker"), BIT(data,7));
104	116
r9684	r9685
324	336	NULL
325	337	};
326	338
327		static MACHINE_CONFIG_START( pk8000, driver_device )
	339	static MACHINE_CONFIG_START( pk8000, pk8000_state )
328	340	/* basic machine hardware */
329	341	MDRV_CPU_ADD("maincpu",I8080, 1780000)
330	342	MDRV_CPU_PROGRAM_MAP(pk8000_mem)

src/mess/drivers/pce220.c

r9684	r9685
14	14	#include "cpu/z80/z80.h"
15	15	#include "devices/messram.h"
16	16
17		static UINT8 bank_num;
18		static UINT16 lcd_index_row,lcd_index_col;
19	17
	18	class pce220_state : public driver_device
	19	{
	20	public:
	21	pce220_state(running_machine &machine, const driver_device_config_base &config)
	22	: driver_device(machine, config) { }
	23
	24	UINT8 bank_num;
	25	UINT16 lcd_index_row;
	26	UINT16 lcd_index_col;
	27	UINT8 lcd_timer;
	28	};
	29
	30
	31
20	32	static VIDEO_START( pce220 )
21	33	{
22	34	}
r9684	r9685
58	70
59	71	static WRITE8_HANDLER( lcd_control_w )
60	72	{
	73	pce220_state *state = space->machine->driver_data<pce220_state>();
61	74	if((data & 0xb8) == 0xb8)
62		lcd_index_row = (data & 0x07);
	75	state->lcd_index_row = (data & 0x07);
63	76	if((data & 0x40) == 0x40)
64		lcd_index_col = (data & 0x3f);
	77	state->lcd_index_col = (data & 0x3f);
65	78	}
66	79
67	80	static WRITE8_HANDLER( lcd_data_w )
68	81	{
	82	pce220_state *state = space->machine->driver_data<pce220_state>();
69	83	UINT8 *vram = memory_region(space->machine, "lcd_vram");
70	84
71		vram[lcd_index_row*0x40|lcd_index_col] = data;
	85	vram[state->lcd_index_row*0x40|state->lcd_index_col] = data;
72	86
73		gfx_element_mark_dirty(space->machine->gfx[0], (lcd_index_row*0x40|lcd_index_col)/5);
74		lcd_index_col++;
	87	gfx_element_mark_dirty(space->machine->gfx[0], (state->lcd_index_row*0x40|state->lcd_index_col)/5);
	88	state->lcd_index_col++;
75	89	}
76	90
77	91	static READ8_HANDLER( rom_bank_r )
78	92	{
79		return bank_num;
	93	pce220_state *state = space->machine->driver_data<pce220_state>();
	94	return state->bank_num;
80	95	}
81	96
82	97	static WRITE8_HANDLER( rom_bank_w )
83	98	{
	99	pce220_state *state = space->machine->driver_data<pce220_state>();
84	100	UINT8 bank2 = data & 0x07; // bits 0,1,2
85	101	UINT8 bank1 = (data & 0x70) >> 4; // bits 4,5,6
86	102
87		bank_num = data;
	103	state->bank_num = data;
88	104
89	105	memory_set_bankptr(space->machine, "bank3", memory_region(space->machine, "user1") + 0x4000 * bank1);
90	106	memory_set_bankptr(space->machine, "bank4", memory_region(space->machine, "user1") + 0x4000 * bank2);
r9684	r9685
113	129	}
114	130
115	131	/* TODO */
116		static UINT8 lcd_timer;
117	132
118	133	static READ8_HANDLER( timer_lcd_r )
119	134	{
r9684	r9685
122	137
123	138	static WRITE8_HANDLER( timer_lcd_w )
124	139	{
125		lcd_timer = data & 1;
	140	pce220_state *state = space->machine->driver_data<pce220_state>();
	141	state->lcd_timer = data & 1;
126	142	}
127	143
128	144	static READ8_HANDLER( port15_r )
r9684	r9685
208	224	GFXDECODE_ENTRY( "lcd_vram",   0x00000, test_decode,    0, 1 )
209	225	GFXDECODE_END
210	226
211		static MACHINE_CONFIG_START( pce220, driver_device )
	227	static MACHINE_CONFIG_START( pce220, pce220_state )
212	228	/* basic machine hardware */
213	229	MDRV_CPU_ADD("maincpu",Z80, 3072000 ) // CMOS-SC7852
214	230	MDRV_CPU_PROGRAM_MAP(pce220_mem)

src/mess/drivers/pv9234.c

r9684	r9685
9	9	#include "emu.h"
10	10	#include "cpu/arm7/arm7.h"
11	11
12		static UINT32 *powervu_ram;
13	12
	13	class pv9234_state : public driver_device
	14	{
	15	public:
	16	pv9234_state(running_machine &machine, const driver_device_config_base &config)
	17	: driver_device(machine, config) { }
	18
	19	UINT32 *powervu_ram;
	20	};
	21
	22
	23
14	24	static WRITE32_HANDLER( debug_w )
15	25	{
16	26	printf("%02x %c\n",data,data);
r9684	r9685
18	28
19	29	static ADDRESS_MAP_START(pv9234_map, ADDRESS_SPACE_PROGRAM, 32)
20	30	AM_RANGE(0x000080cc, 0x000080cf) AM_WRITE(debug_w)
21		AM_RANGE(0x0003e000, 0x0003efff) AM_RAM AM_BASE(&powervu_ram)
	31	AM_RANGE(0x0003e000, 0x0003efff) AM_RAM AM_BASE_MEMBER(pv9234_state, powervu_ram)
22	32	AM_RANGE(0x00000000, 0x0007ffff) AM_ROM AM_REGION("maincpu",0) //FLASH ROM!
23	33	AM_RANGE(0x00080000, 0x00087fff) AM_MIRROR(0x78000) AM_RAM AM_SHARE("share1")//mirror is a guess, writes a prg at 0xc0200 then it jumps at b0200 (!)
24	34	AM_RANGE(0xe0000000, 0xe0007fff) AM_MIRROR(0x0fff8000) AM_RAM AM_SHARE("share1")
r9684	r9685
32	42
33	43	static MACHINE_RESET(pv9234)
34	44	{
	45	pv9234_state *state = machine->driver_data<pv9234_state>();
35	46	int i;
36	47
37	48	for(i=0;i<0x1000/4;i++)
38		powervu_ram[i] = 0;
	49	state->powervu_ram[i] = 0;
39	50	}
40	51
41	52	static VIDEO_START( pv9234 )
r9684	r9685
47	58	return 0;
48	59	}
49	60
50		static MACHINE_CONFIG_START( pv9234, driver_device )
	61	static MACHINE_CONFIG_START( pv9234, pv9234_state )
51	62	/* basic machine hardware */
52	63	MDRV_CPU_ADD("maincpu", ARM7, 4915000) //probably a more powerful clone.
53	64	MDRV_CPU_PROGRAM_MAP(pv9234_map)

src/mess/drivers/vt100.c

r9684	r9685
19	19	#include "video/vtvideo.h"
20	20	#include "vt100.lh"
21	21
22		static UINT8 *vt100_ram;
23		static UINT8 vt100_keyboard_int;
24		static UINT8 vt100_receiver_int;
25		static UINT8 vt100_vertical_int;
26	22
27		static double vt100_send_baud_rate;
28		static double vt100_recv_baud_rate;
	23	class vt100_state : public driver_device
	24	{
	25	public:
	26	vt100_state(running_machine &machine, const driver_device_config_base &config)
	27	: driver_device(machine, config) { }
29	28
	29	UINT8 *ram;
	30	UINT8 keyboard_int;
	31	UINT8 receiver_int;
	32	UINT8 vertical_int;
	33	double send_baud_rate;
	34	double recv_baud_rate;
	35	UINT8 key_scan;
	36	};
	37
	38
	39
	40
30	41	static ADDRESS_MAP_START(vt100_mem, ADDRESS_SPACE_PROGRAM, 8)
31	42	ADDRESS_MAP_UNMAP_HIGH
32	43	AM_RANGE( 0x0000, 0x1fff ) AM_ROM  // ROM ( 4 * 2K)
33		AM_RANGE( 0x2000, 0x2bff ) AM_RAM AM_BASE(&vt100_ram) // Screen and scratch RAM
	44	AM_RANGE( 0x2000, 0x2bff ) AM_RAM AM_BASE_MEMBER(vt100_state, ram) // Screen and scratch RAM
34	45	AM_RANGE( 0x2c00, 0x2fff ) AM_RAM  // AVO Screen RAM
35	46	AM_RANGE( 0x3000, 0x3fff ) AM_RAM  // AVO Attribute RAM (4 bits wide)
36	47	// 0x4000, 0x7fff is unassigned
r9684	r9685
49	60	// 7 - Keyboard TBMT H
50	61	static READ8_HANDLER(vt100_flags_r)
51	62	{
	63	vt100_state *state = space->machine->driver_data<vt100_state>();
52	64	UINT8 retVal = 0;
53	65	retVal |= vt_video_lba7_r(space->machine->device("vt100_video"),0) * 0x40;
54		retVal |= vt100_keyboard_int * 0x80;
	66	retVal |= state->keyboard_int * 0x80;
55	67	return retVal;
56	68	}
57	69
58		static UINT8 vt100_key_scan = 0;
59	70
60	71	static TIMER_CALLBACK(keyboard_callback)
61	72	{
	73	vt100_state *state = machine->driver_data<vt100_state>();
62	74	int i;
63	75	static const char *const keynames[] = {
64	76	"LINE0", "LINE1", "LINE2", "LINE3",
r9684	r9685
67	79	"LINEC", "LINED", "LINEE", "LINEF"
68	80	};
69	81	UINT8 code;
70		if (vt100_key_scan == 1) {
	82	if (state->key_scan == 1) {
71	83	for(i = 0; i < 16; i++)
72	84	{
73	85	code =   input_port_read(machine, keynames[i]);
74	86	if (code!=0xff) {
75		vt100_keyboard_int = 1;
	87	state->keyboard_int = 1;
76	88	cputag_set_input_line(machine, "maincpu", 0, HOLD_LINE);
77	89	}
78	90	}
r9684	r9685
82	94
83	95	static WRITE8_HANDLER(vt100_keyboard_w)
84	96	{
	97	vt100_state *state = space->machine->driver_data<vt100_state>();
85	98
86	99	running_device *speaker = space->machine->device("speaker");
87	100
r9684	r9685
92	105	output_set_value("l2_led",     BIT(data,2) ? 0 : 1);
93	106	output_set_value("l3_led",     BIT(data,1) ? 0 : 1);
94	107	output_set_value("l4_led",     BIT(data,0) ? 0 : 1);
95		vt100_key_scan = BIT(data,6);
	108	state->key_scan = BIT(data,6);
96	109	speaker_level_w(speaker, BIT(data,7));
97	110	}
98	111
r9684	r9685
102	115	}
103	116	static WRITE8_HANDLER(vt100_baud_rate_w)
104	117	{
	118	vt100_state *state = space->machine->driver_data<vt100_state>();
105	119	static const double baud_rate[] = {
106	120	50, 75, 110, 134.5, 150, 200, 300, 600, 1200,
107	121	1800, 2000, 2400, 3600, 4800, 9600, 19200
108	122	};
109	123
110		vt100_send_baud_rate = baud_rate[(data >>4) & 0x0f];
111		vt100_recv_baud_rate = baud_rate[data & 0x0f];
	124	state->send_baud_rate = baud_rate[(data >>4) & 0x0f];
	125	state->recv_baud_rate = baud_rate[data & 0x0f];
112	126	}
113	127
114	128	static WRITE8_HANDLER(vt100_nvr_latch_w)
r9684	r9685
274	288	//          all other set to 1
275	289	static IRQ_CALLBACK(vt100_irq_callback)
276	290	{
277		UINT8 retVal = 0xc7 | (0x08 * vt100_keyboard_int) | (0x10 * vt100_receiver_int) | (0x20 * vt100_vertical_int);
278		vt100_receiver_int = 0;
	291	vt100_state *state = device->machine->driver_data<vt100_state>();
	292	UINT8 retVal = 0xc7 | (0x08 * state->keyboard_int) | (0x10 * state->receiver_int) | (0x20 * state->vertical_int);
	293	state->receiver_int = 0;
279	294	return retVal;
280	295	}
281	296
r9684	r9685
286	301
287	302	static MACHINE_RESET(vt100)
288	303	{
289		vt100_keyboard_int = 0;
290		vt100_receiver_int = 0;
291		vt100_vertical_int = 0;
	304	vt100_state *state = machine->driver_data<vt100_state>();
	305	state->keyboard_int = 0;
	306	state->receiver_int = 0;
	307	state->vertical_int = 0;
292	308	output_set_value("online_led",1);
293	309	output_set_value("local_led", 1);
294	310	output_set_value("locked_led",1);
r9684	r9685
297	313	output_set_value("l3_led",     1);
298	314	output_set_value("l4_led",     1);
299	315
300		vt100_key_scan = 0;
	316	state->key_scan = 0;
301	317
302	318	cpu_set_irq_callback(machine->device("maincpu"), vt100_irq_callback);
303	319	}
304	320
305	321	static READ8_DEVICE_HANDLER (vt100_read_video_ram_r )
306	322	{
307		return vt100_ram[offset];
	323	vt100_state *state = device->machine->driver_data<vt100_state>();
	324	return state->ram[offset];
308	325	}
309	326
310	327	static WRITE8_DEVICE_HANDLER (vt100_clear_video_interrupt)
311	328	{
312		vt100_vertical_int = 0;
	329	vt100_state *state = device->machine->driver_data<vt100_state>();
	330	state->vertical_int = 0;
313	331	}
314	332
315	333	static const vt_video_interface vt100_video_interface = {
r9684	r9685
321	339
322	340	static INTERRUPT_GEN( vt100_vertical_interrupt )
323	341	{
324		vt100_vertical_int = 1;
	342	vt100_state *state = device->machine->driver_data<vt100_state>();
	343	state->vertical_int = 1;
325	344	cpu_set_input_line(device, 0, HOLD_LINE);
326	345	}
327	346
r9684	r9685
346	365
347	366	#define XTAL_24_8832MHz    24883200
348	367
349		static MACHINE_CONFIG_START( vt100, driver_device )
	368	static MACHINE_CONFIG_START( vt100, vt100_state )
350	369	/* basic machine hardware */
351	370	MDRV_CPU_ADD("maincpu",I8080, XTAL_24_8832MHz / 9)
352	371	MDRV_CPU_PROGRAM_MAP(vt100_mem)

src/mess/drivers/microdec.c

r9684	r9685
12	12	#include "devices/flopdrv.h"
13	13	#include "machine/terminal.h"
14	14
15		static UINT8 received_char = 0;
16	15
	16	class microdec_state : public driver_device
	17	{
	18	public:
	19	microdec_state(running_machine &machine, const driver_device_config_base &config)
	20	: driver_device(machine, config) { }
	21
	22	UINT8 received_char;
	23	};
	24
	25
	26
17	27	static WRITE8_HANDLER(microdec_terminal_w)
18	28	{
19	29	running_device *devconf = space->machine->device("terminal");
r9684	r9685
22	32
23	33	static READ8_HANDLER(microdec_terminal_status_r)
24	34	{
25		if (received_char!=0) return 3; // char received
	35	microdec_state *state = space->machine->driver_data<microdec_state>();
	36	if (state->received_char!=0) return 3; // char received
26	37	return 1; // ready
27	38	}
28	39
29	40	static READ8_HANDLER(microdec_terminal_r)
30	41	{
31		UINT8 retVal = received_char;
32		received_char = 0;
	42	microdec_state *state = space->machine->driver_data<microdec_state>();
	43	UINT8 retVal = state->received_char;
	44	state->received_char = 0;
33	45	return retVal;
34	46	}
35	47
r9684	r9685
56	68
57	69	static MACHINE_RESET(microdec)
58	70	{
59		received_char = 0;
	71	microdec_state *state = machine->driver_data<microdec_state>();
	72	state->received_char = 0;
60	73	}
61	74
62	75	static WRITE8_DEVICE_HANDLER( microdec_kbd_put )
63	76	{
64		received_char = data;
	77	microdec_state *state = device->machine->driver_data<microdec_state>();
	78	state->received_char = data;
65	79	}
66	80
67	81	static GENERIC_TERMINAL_INTERFACE( microdec_terminal_intf )
r9684	r9685
94	108	NULL
95	109	};
96	110
97		static MACHINE_CONFIG_START( microdec, driver_device )
	111	static MACHINE_CONFIG_START( microdec, microdec_state )
98	112	/* basic machine hardware */
99	113	MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz)
100	114	MDRV_CPU_PROGRAM_MAP(microdec_mem)

src/mess/drivers/pimps.c

r9684	r9685
10	10	#include "cpu/i8085/i8085.h"
11	11	#include "machine/terminal.h"
12	12
	13
	14	class pimps_state : public driver_device
	15	{
	16	public:
	17	pimps_state(running_machine &machine, const driver_device_config_base &config)
	18	: driver_device(machine, config) { }
	19
	20	UINT8 received_char;
	21	};
	22
	23
13	24	// should be 8251 UART
14	25
15		static UINT8 received_char = 0;
16	26
17	27	static READ8_HANDLER(pimps_terminal_status_r)
18	28	{
19		if (received_char!=0) return 3; // char received
	29	pimps_state *state = space->machine->driver_data<pimps_state>();
	30	if (state->received_char!=0) return 3; // char received
20	31	return 1; // ready
21	32	}
22	33
23	34	static READ8_DEVICE_HANDLER(pimps_terminal_r)
24	35	{
25		UINT8 retVal = received_char;
26		received_char = 0;
	36	pimps_state *state = device->machine->driver_data<pimps_state>();
	37	UINT8 retVal = state->received_char;
	38	state->received_char = 0;
27	39	return retVal;
28	40	}
29	41
r9684	r9685
47	59
48	60	static MACHINE_RESET(pimps)
49	61	{
50		received_char = 0;
	62	pimps_state *state = machine->driver_data<pimps_state>();
	63	state->received_char = 0;
51	64	}
52	65
53	66	static WRITE8_DEVICE_HANDLER( pimps_kbd_put )
54	67	{
55		received_char = data;
	68	pimps_state *state = device->machine->driver_data<pimps_state>();
	69	state->received_char = data;
56	70	}
57	71
58	72	static GENERIC_TERMINAL_INTERFACE( pimps_terminal_intf )
r9684	r9685
60	74	DEVCB_HANDLER(pimps_kbd_put)
61	75	};
62	76
63		static MACHINE_CONFIG_START( pimps, driver_device )
	77	static MACHINE_CONFIG_START( pimps, pimps_state )
64	78	/* basic machine hardware */
65	79	MDRV_CPU_ADD("maincpu",I8085A, XTAL_2MHz)
66	80	MDRV_CPU_PROGRAM_MAP(pimps_mem)

src/mess/drivers/pc2000.c

r9684	r9685
9	9	#include "emu.h"
10	10	#include "cpu/z80/z80.h"
11	11
12		static int lcd_vram_index;
13		static UINT8 mux_data;
14		static UINT8 *wram;
15	12
	13	class pc2000_state : public driver_device
	14	{
	15	public:
	16	pc2000_state(running_machine &machine, const driver_device_config_base &config)
	17	: driver_device(machine, config) { }
	18
	19	int lcd_vram_index;
	20	UINT8 mux_data;
	21	UINT8 *wram;
	22	};
	23
	24
	25
16	26	static VIDEO_START( pc2000 )
17	27	{
18	28	}
19	29
20	30	static VIDEO_UPDATE( pc2000 )
21	31	{
	32	pc2000_state *state = screen->machine->driver_data<pc2000_state>();
22	33	int x,y;
23	34	UINT8 *vram = memory_region(screen->machine, "lcd_vram");
24	35
r9684	r9685
32	43	}
33	44	}
34	45
35		popmessage("%c %02x",wram[0xce4],wram[0xce4]); //dce4
	46	popmessage("%c %02x",state->wram[0xce4],state->wram[0xce4]); //dce4
36	47	return 0;
37	48	}
38	49
39	50	static WRITE8_HANDLER( lcd_vram_addr_w )
40	51	{
41		lcd_vram_index = data;
	52	pc2000_state *state = space->machine->driver_data<pc2000_state>();
	53	state->lcd_vram_index = data;
42	54	}
43	55
44	56	static WRITE8_HANDLER( lcd_vram_data_w )
45	57	{
	58	pc2000_state *state = space->machine->driver_data<pc2000_state>();
46	59	UINT8 *vram = memory_region(space->machine, "lcd_vram");
47	60
48		vram[lcd_vram_index] = data;
	61	vram[state->lcd_vram_index] = data;
49	62	}
50	63
51	64
52	65	/* TODO: put a breakpoint at 1625 and test the inputs, writes at dce4 are the scancode values */
53	66	static READ8_HANDLER( key_matrix_10_r )
54	67	{
55		switch(mux_data)
	68	pc2000_state *state = space->machine->driver_data<pc2000_state>();
	69	switch(state->mux_data)
56	70	{
57	71	case 0x01: return input_port_read(space->machine, "IN0");
58	72	case 0x02: return input_port_read(space->machine, "IN1");
r9684	r9685
69	83
70	84	static READ8_HANDLER( key_matrix_11_r )
71	85	{
72		switch(mux_data)
	86	pc2000_state *state = space->machine->driver_data<pc2000_state>();
	87	switch(state->mux_data)
73	88	{
74	89	case 0x01: return input_port_read(space->machine, "IN8");
75	90	case 0x02: return input_port_read(space->machine, "IN9");
r9684	r9685
86	101
87	102	static WRITE8_HANDLER( key_matrix_w )
88	103	{
89		mux_data = data;
	104	pc2000_state *state = space->machine->driver_data<pc2000_state>();
	105	state->mux_data = data;
90	106	}
91	107
92	108	static WRITE8_HANDLER( rombank_w )
r9684	r9685
101	117	AM_RANGE(0x0000, 0x3fff) AM_ROM AM_REGION("bios", 0x00000)
102	118	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
103	119	AM_RANGE(0x8000, 0xbfff) AM_READNOP //  0x8000 - 0xbfff tests a cartridge, header is 0x55 0xaa 0x59 0x45, if it succeeds a jump at 0x8004 occurs
104		AM_RANGE(0xd000, 0xdfff) AM_RAM AM_BASE(&wram)
	120	AM_RANGE(0xd000, 0xdfff) AM_RAM AM_BASE_MEMBER(pc2000_state, wram)
105	121	AM_RANGE(0xf000, 0xffff) AM_ROM AM_REGION("bios", 0x10000) //tied with rom bank at I/O 3
106	122	ADDRESS_MAP_END
107	123
r9684	r9685
469	485	GFXDECODE_END
470	486
471	487
472		static MACHINE_CONFIG_START( pc2000, driver_device )
	488	static MACHINE_CONFIG_START( pc2000, pc2000_state )
473	489	/* basic machine hardware */
474	490	MDRV_CPU_ADD("maincpu",Z80, XTAL_4MHz) /* probably not accurate */
475	491	MDRV_CPU_PROGRAM_MAP(pc2000_mem)

src/mess/drivers/rx78.c

r9684	r9685
48	48	#include "sound/wave.h"
49	49	#include "devices/messram.h"
50	50
	51
	52	class rx78_state : public driver_device
	53	{
	54	public:
	55	rx78_state(running_machine &machine, const driver_device_config_base &config)
	56	: driver_device(machine, config) { }
	57
	58	running_device *cassette;
	59	UINT8 vram_read_bank;
	60	UINT8 vram_write_bank;
	61	UINT8 pal_reg[7];
	62	UINT8 pri_mask;
	63	UINT8 key_mux;
	64	};
	65
	66
51	67	#define MASTER_CLOCK XTAL_28_63636MHz
52	68
53		static running_device *rx78_cassette;
54	69
55	70	static WRITE8_HANDLER( rx78_f0_w )
56	71	{
57		cassette_output(rx78_cassette, (data & 1) ? -1.0 : +1.0);
	72	rx78_state *state = space->machine->driver_data<rx78_state>();
	73	cassette_output(state->cassette, (data & 1) ? -1.0 : +1.0);
58	74	}
59	75
60	76	static READ8_HANDLER( rx78_f0_r )
61	77	{
	78	rx78_state *state = space->machine->driver_data<rx78_state>();
62	79	UINT8 data = 0;
63	80
64		if (cassette_input(rx78_cassette) > 0.03)
	81	if (cassette_input(state->cassette) > 0.03)
65	82	data++;
66	83
67	84	return data;
68	85	}
69	86
70	87
71		static UINT8 vram_read_bank,vram_write_bank,pal_reg[7],pri_mask;
72	88
73	89	static VIDEO_START( rx78 )
74	90	{
r9684	r9685
76	92
77	93	static VIDEO_UPDATE( rx78 )
78	94	{
	95	rx78_state *state = screen->machine->driver_data<rx78_state>();
79	96	UINT8 *vram = memory_region(screen->machine,"vram");
80	97	int x,y,count;
81	98
r9684	r9685
92	109	for (i = 0; i < 8; i++)
93	110	{
94	111	/* bg color */
95		pen[0] = (pri_mask & 0x08) ? (vram[count + 0x6000] >> (i)) : 0x00;
96		pen[1] = (pri_mask & 0x10) ? (vram[count + 0x8000] >> (i)) : 0x00;
97		pen[2] = (pri_mask & 0x20) ? (vram[count + 0xa000] >> (i)) : 0x00;
	112	pen[0] = (state->pri_mask & 0x08) ? (vram[count + 0x6000] >> (i)) : 0x00;
	113	pen[1] = (state->pri_mask & 0x10) ? (vram[count + 0x8000] >> (i)) : 0x00;
	114	pen[2] = (state->pri_mask & 0x20) ? (vram[count + 0xa000] >> (i)) : 0x00;
98	115
99	116	color  = ((pen[0] & 1) << 0);
100	117	color |= ((pen[1] & 1) << 1);
r9684	r9685
104	121	*BITMAP_ADDR16(bitmap, y, x+i) = screen->machine->pens[color];
105	122
106	123	/* fg color */
107		pen[0] = (pri_mask & 0x01) ? (vram[count + 0x0000] >> (i)) : 0x00;
108		pen[1] = (pri_mask & 0x02) ? (vram[count + 0x2000] >> (i)) : 0x00;
109		pen[2] = (pri_mask & 0x04) ? (vram[count + 0x4000] >> (i)) : 0x00;
	124	pen[0] = (state->pri_mask & 0x01) ? (vram[count + 0x0000] >> (i)) : 0x00;
	125	pen[1] = (state->pri_mask & 0x02) ? (vram[count + 0x2000] >> (i)) : 0x00;
	126	pen[2] = (state->pri_mask & 0x04) ? (vram[count + 0x4000] >> (i)) : 0x00;
110	127
111	128	color  = ((pen[0] & 1) << 0);
112	129	color |= ((pen[1] & 1) << 1);
r9684	r9685
122	139	return 0;
123	140	}
124	141
125		static UINT8 key_mux;
126	142
127	143	static READ8_HANDLER( key_r )
128	144	{
	145	rx78_state *state = space->machine->driver_data<rx78_state>();
129	146	static const char *const keynames[] = { "KEY0", "KEY1", "KEY2", "KEY3",
130	147	"KEY4", "KEY5", "KEY6", "KEY7",
131	148	"KEY8", "JOY1P_0","JOY1P_1","JOY1P_2",
132	149	"JOY2P_0", "JOY2P_1", "JOY2P_2", "UNUSED" };
133	150
134		if(key_mux == 0x30) //status read
	151	if(state->key_mux == 0x30) //status read
135	152	{
136	153	int res,i;
137	154
r9684	r9685
142	159	return res;
143	160	}
144	161
145		if(key_mux >= 1 && key_mux <= 15)
146		return input_port_read(space->machine, keynames[key_mux - 1]);
	162	if(state->key_mux >= 1 && state->key_mux <= 15)
	163	return input_port_read(space->machine, keynames[state->key_mux - 1]);
147	164
148	165	return 0;
149	166	}
150	167
151	168	static WRITE8_HANDLER( key_w )
152	169	{
153		key_mux = data;
	170	rx78_state *state = space->machine->driver_data<rx78_state>();
	171	state->key_mux = data;
154	172	}
155	173
156	174	static READ8_HANDLER( rx78_vram_r )
157	175	{
	176	rx78_state *state = space->machine->driver_data<rx78_state>();
158	177	UINT8 *vram = memory_region(space->machine,"vram");
159	178
160		if(vram_read_bank == 0 || vram_read_bank > 6)
	179	if(state->vram_read_bank == 0 || state->vram_read_bank > 6)
161	180	return 0xff;
162	181
163		return vram[offset + ((vram_read_bank - 1) * 0x2000)];
	182	return vram[offset + ((state->vram_read_bank - 1) * 0x2000)];
164	183	}
165	184
166	185	static WRITE8_HANDLER( rx78_vram_w )
167	186	{
	187	rx78_state *state = space->machine->driver_data<rx78_state>();
168	188	UINT8 *vram = memory_region(space->machine,"vram");
169	189
170		if(vram_write_bank & 0x01) { vram[offset + 0 * 0x2000] = data; }
171		if(vram_write_bank & 0x02) { vram[offset + 1 * 0x2000] = data; }
172		if(vram_write_bank & 0x04) { vram[offset + 2 * 0x2000] = data; }
173		if(vram_write_bank & 0x08) { vram[offset + 3 * 0x2000] = data; }
174		if(vram_write_bank & 0x10) { vram[offset + 4 * 0x2000] = data; }
175		if(vram_write_bank & 0x20) { vram[offset + 5 * 0x2000] = data; }
	190	if(state->vram_write_bank & 0x01) { vram[offset + 0 * 0x2000] = data; }
	191	if(state->vram_write_bank & 0x02) { vram[offset + 1 * 0x2000] = data; }
	192	if(state->vram_write_bank & 0x04) { vram[offset + 2 * 0x2000] = data; }
	193	if(state->vram_write_bank & 0x08) { vram[offset + 3 * 0x2000] = data; }
	194	if(state->vram_write_bank & 0x10) { vram[offset + 4 * 0x2000] = data; }
	195	if(state->vram_write_bank & 0x20) { vram[offset + 5 * 0x2000] = data; }
176	196	}
177	197
178	198	static WRITE8_HANDLER( vram_read_bank_w )
179	199	{
180		vram_read_bank = data;
	200	rx78_state *state = space->machine->driver_data<rx78_state>();
	201	state->vram_read_bank = data;
181	202	}
182	203
183	204	static WRITE8_HANDLER( vram_write_bank_w )
184	205	{
185		vram_write_bank = data;
	206	rx78_state *state = space->machine->driver_data<rx78_state>();
	207	state->vram_write_bank = data;
186	208	}
187	209
188	210	static WRITE8_HANDLER( vdp_reg_w )
189	211	{
	212	rx78_state *state = space->machine->driver_data<rx78_state>();
190	213	UINT8 r,g,b,res,i;
191	214
192		pal_reg[offset] = data;
	215	state->pal_reg[offset] = data;
193	216
194	217	for(i=0;i<16;i++)
195	218	{
196		res = ((i & 1) ? pal_reg[0 + (i & 8 ? 3 : 0)] : 0) | ((i & 2) ? pal_reg[1 + (i & 8 ? 3 : 0)] : 0) | ((i & 4) ? pal_reg[2 + (i & 8 ? 3 : 0)] : 0);
197		if(res & pal_reg[6]) //color mask, TODO: check this
198		res &= pal_reg[6];
	219	res = ((i & 1) ? state->pal_reg[0 + (i & 8 ? 3 : 0)] : 0) | ((i & 2) ? state->pal_reg[1 + (i & 8 ? 3 : 0)] : 0) | ((i & 4) ? state->pal_reg[2 + (i & 8 ? 3 : 0)] : 0);
	220	if(res & state->pal_reg[6]) //color mask, TODO: check this
	221	res &= state->pal_reg[6];
199	222
200	223	r = (res & 0x11) == 0x11 ? 0xff : ((res & 0x11) == 0x01 ? 0x7f : 0x00);
201	224	g = (res & 0x22) == 0x22 ? 0xff : ((res & 0x22) == 0x02 ? 0x7f : 0x00);
r9684	r9685
218	241
219	242	static WRITE8_HANDLER( vdp_pri_mask_w )
220	243	{
221		pri_mask = data;
	244	rx78_state *state = space->machine->driver_data<rx78_state>();
	245	state->pri_mask = data;
222	246	}
223	247
224	248
r9684	r9685
375	399
376	400	static MACHINE_RESET(rx78)
377	401	{
378		rx78_cassette = machine->device("cassette");
	402	rx78_state *state = machine->driver_data<rx78_state>();
	403	state->cassette = machine->device("cassette");
379	404	}
380	405
381	406	static DEVICE_IMAGE_LOAD( rx78_cart )
r9684	r9685
426	451	GFXDECODE_ENTRY( "maincpu", 0x1a27, rx78_charlayout, 0, 8 )
427	452	GFXDECODE_END
428	453
429		static MACHINE_CONFIG_START( rx78, driver_device )
	454	static MACHINE_CONFIG_START( rx78, rx78_state )
430	455	/* basic machine hardware */
431	456	MDRV_CPU_ADD("maincpu",Z80, MASTER_CLOCK/7)   // unknown divider
432	457	MDRV_CPU_PROGRAM_MAP(rx78_mem)

src/mess/drivers/sun1.c

r9684	r9685
15	15	#include "machine/upd7201.h"
16	16	#include "machine/terminal.h"
17	17
18		static UINT16* sun1_ram;
19	18
	19	class sun1_state : public driver_device
	20	{
	21	public:
	22	sun1_state(running_machine &machine, const driver_device_config_base &config)
	23	: driver_device(machine, config) { }
	24
	25	UINT16* ram;
	26	};
	27
	28
	29
20	30	// Just hack to show output since upd7201 is not implemented yet
21	31
22	32	static READ16_HANDLER(sun1_upd7201_r)
r9684	r9685
32	42
33	43	static ADDRESS_MAP_START(sun1_mem, ADDRESS_SPACE_PROGRAM, 16)
34	44	ADDRESS_MAP_UNMAP_HIGH
35		AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_BASE(&sun1_ram) // 512 KB RAM / ROM at boot
	45	AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_BASE_MEMBER(sun1_state, ram) // 512 KB RAM / ROM at boot
36	46	AM_RANGE(0x00200000, 0x00203fff) AM_ROM AM_REGION("user1",0)
37	47	AM_RANGE(0x00600000, 0x00600007) AM_READWRITE( sun1_upd7201_r, sun1_upd7201_w )
38	48	ADDRESS_MAP_END
r9684	r9685
45	55
46	56	static MACHINE_RESET(sun1)
47	57	{
	58	sun1_state *state = machine->driver_data<sun1_state>();
48	59	UINT8* user1 = memory_region(machine, "user1");
49	60
50		memcpy((UINT8*)sun1_ram,user1,0x4000);
	61	memcpy((UINT8*)state->ram,user1,0x4000);
51	62
52	63	machine->device("maincpu")->reset();
53	64	}
r9684	r9685
63	74	};
64	75
65	76
66		static MACHINE_CONFIG_START( sun1, driver_device )
	77	static MACHINE_CONFIG_START( sun1, sun1_state )
67	78	/* basic machine hardware */
68	79	MDRV_CPU_ADD("maincpu", M68000, XTAL_10MHz)
69	80	MDRV_CPU_PROGRAM_MAP(sun1_mem)

src/mess/drivers/pyl601.c

r9684	r9685
14	14	#include "machine/upd765.h"
15	15	#include "devices/messram.h"
16	16
17		static UINT8 rom_page;
18		static UINT32 vdisk_addr = 0;
19		static UINT8 key_code;
20		static UINT8 keyboard_clk = 0x00;
21		static UINT8 video_mode = 0x00;
22		static UINT8 tick50_mark = 0x00;
23	17
	18	class pyl601_state : public driver_device
	19	{
	20	public:
	21	pyl601_state(running_machine &machine, const driver_device_config_base &config)
	22	: driver_device(machine, config) { }
	23
	24	UINT8 rom_page;
	25	UINT32 vdisk_addr;
	26	UINT8 key_code;
	27	UINT8 keyboard_clk;
	28	UINT8 video_mode;
	29	UINT8 tick50_mark;
	30	UINT8 floppy_ctrl;
	31	};
	32
	33
	34
24	35	static READ8_HANDLER (rom_page_r)
25	36	{
26		return rom_page;
	37	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	38	return state->rom_page;
27	39	}
28	40
29	41	static WRITE8_HANDLER (rom_page_w)
30	42	{
31		rom_page =data;
	43	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	44	state->rom_page =data;
32	45	if (data & 8)
33	46	{
34	47	int chip = (data >> 4) % 5;
r9684	r9685
44	57
45	58	static WRITE8_HANDLER (vdisk_page_w)
46	59	{
47		vdisk_addr = (vdisk_addr & 0x0ffff) | ((data & 0x0f)<<16);
	60	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	61	state->vdisk_addr = (state->vdisk_addr & 0x0ffff) | ((data & 0x0f)<<16);
48	62	}
49	63
50	64	static WRITE8_HANDLER (vdisk_h_w)
51	65	{
52		vdisk_addr = (vdisk_addr & 0xf00ff) | (data<<8);
	66	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	67	state->vdisk_addr = (state->vdisk_addr & 0xf00ff) | (data<<8);
53	68	}
54	69
55	70	static WRITE8_HANDLER (vdisk_l_w)
56	71	{
57		vdisk_addr = (vdisk_addr & 0xfff00) | data;
	72	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	73	state->vdisk_addr = (state->vdisk_addr & 0xfff00) | data;
58	74	}
59	75
60	76	static WRITE8_HANDLER (vdisk_data_w)
61	77	{
62		messram_get_ptr(space->machine->device("messram"))[0x10000 + (vdisk_addr & 0x7ffff)] = data;
63		vdisk_addr++;
64		vdisk_addr&=0x7ffff;
	78	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	79	messram_get_ptr(space->machine->device("messram"))[0x10000 + (state->vdisk_addr & 0x7ffff)] = data;
	80	state->vdisk_addr++;
	81	state->vdisk_addr&=0x7ffff;
65	82	}
66	83
67	84	static READ8_HANDLER (vdisk_data_r)
68	85	{
69		UINT8 retVal = messram_get_ptr(space->machine->device("messram"))[0x10000 + (vdisk_addr & 0x7ffff)];
70		vdisk_addr++;
71		vdisk_addr &= 0x7ffff;
	86	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	87	UINT8 retVal = messram_get_ptr(space->machine->device("messram"))[0x10000 + (state->vdisk_addr & 0x7ffff)];
	88	state->vdisk_addr++;
	89	state->vdisk_addr &= 0x7ffff;
72	90	return retVal;
73	91	}
74	92
r9684	r9685
87	105
88	106	static READ8_HANDLER ( keyboard_r )
89	107	{
90		return key_code;
	108	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	109	return state->key_code;
91	110	}
92	111
93	112	static READ8_HANDLER ( keycheck_r )
94	113	{
	114	pyl601_state *state = space->machine->driver_data<pyl601_state>();
95	115	UINT8 retVal = 0x3f;
96	116	UINT8 *keyboard = memory_region(space->machine, "keyboard");
97	117	UINT16 row1 = input_port_read(space->machine, "ROW1");
r9684	r9685
111	131	addr |=  ((row2 == 0x00) ? 1 : 0) << 9;
112	132	addr |=  ((row1 == 0x00) ? 1 : 0) << 10;
113	133
114		key_code = keyboard[addr];
115		keyboard_clk = ~keyboard_clk;
	134	state->key_code = keyboard[addr];
	135	state->keyboard_clk = ~state->keyboard_clk;
116	136
117		if (keyboard_clk)
	137	if (state->keyboard_clk)
118	138	retVal |= 0x80;
119	139	}
120	140	return retVal;
r9684	r9685
123	143
124	144	static WRITE8_HANDLER (video_mode_w)
125	145	{
126		video_mode = data;
	146	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	147	state->video_mode = data;
127	148	}
128	149	static READ8_HANDLER (video_mode_r)
129	150	{
130		return video_mode;
	151	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	152	return state->video_mode;
131	153	}
132	154
133	155	static READ8_HANDLER (timer_r)
134	156	{
135		UINT8 retVal= tick50_mark | 0x37;
136		tick50_mark = 0;
	157	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	158	UINT8 retVal= state->tick50_mark | 0x37;
	159	state->tick50_mark = 0;
137	160	return retVal;
138	161	}
139	162
r9684	r9685
155	178	{
156	179	return get_floppy_image(device->machine, (floppy_index & 1)^1);
157	180	}
158		static UINT8 floppy_ctrl = 0;
159	181	static WRITE8_HANDLER( floppy_w )
160	182	{
	183	pyl601_state *state = space->machine->driver_data<pyl601_state>();
161	184	// bit 0 is reset (if zero)
162	185	// bit 1 is TC state
163	186	// bit 2 is drive selected
r9684	r9685
173	196
174	197	upd765_tc_w(floppy, BIT(data,1));
175	198
176		floppy_ctrl = data;
	199	state->floppy_ctrl = data;
177	200	}
178	201	static READ8_HANDLER (floppy_r)
179	202	{
180		return floppy_ctrl;
	203	pyl601_state *state = space->machine->driver_data<pyl601_state>();
	204	return state->floppy_ctrl;
181	205	}
182	206
183	207	static const struct upd765_interface pyldin_upd765_interface =
r9684	r9685
318	342
319	343	static MACHINE_RESET(pyl601)
320	344	{
321		key_code = 0xff;
	345	pyl601_state *state = machine->driver_data<pyl601_state>();
	346	state->key_code = 0xff;
322	347	memory_set_bankptr(machine, "bank1", messram_get_ptr(machine->device("messram")) + 0x0000);
323	348	memory_set_bankptr(machine, "bank2", messram_get_ptr(machine->device("messram")) + 0xc000);
324	349	memory_set_bankptr(machine, "bank3", messram_get_ptr(machine->device("messram")) + 0xe000);
r9684	r9685
342	367
343	368	static MC6845_UPDATE_ROW( pyl601_update_row )
344	369	{
	370	pyl601_state *state = device->machine->driver_data<pyl601_state>();
345	371	UINT8 *charrom = memory_region(device->machine, "gfx1");
346	372
347	373	int column, bit, i;
348	374	UINT8 data;
349		if (BIT(video_mode, 5) == 0)
	375	if (BIT(state->video_mode, 5) == 0)
350	376	{
351	377	for (column = 0; column < x_count; column++)
352	378	{
r9684	r9685
387	413
388	414	static MC6845_UPDATE_ROW( pyl601a_update_row )
389	415	{
	416	pyl601_state *state = device->machine->driver_data<pyl601_state>();
390	417	UINT8 *charrom = memory_region(device->machine, "gfx1");
391	418
392	419	int column, bit, i;
393	420	UINT8 data;
394		if (BIT(video_mode, 5) == 0)
	421	if (BIT(state->video_mode, 5) == 0)
395	422	{
396	423	for (column = 0; column < x_count; column++)
397	424	{
r9684	r9685
463	490
464	491	static INTERRUPT_GEN( pyl601_interrupt )
465	492	{
466		tick50_mark = 0x80;
	493	pyl601_state *state = device->machine->driver_data<pyl601_state>();
	494	state->tick50_mark = 0x80;
467	495	cpu_set_input_line(device, 0, HOLD_LINE);
468	496	}
469	497
r9684	r9685
523	551	GFXDECODE_ENTRY( "gfx1", 0x0000, pyl601a_charlayout, 0, 1 )
524	552	GFXDECODE_END
525	553
526		static MACHINE_CONFIG_START( pyl601, driver_device )
	554	static MACHINE_CONFIG_START( pyl601, pyl601_state )
527	555	/* basic machine hardware */
528	556	MDRV_CPU_ADD("maincpu",M6800, XTAL_1MHz)
529	557	MDRV_CPU_PROGRAM_MAP(pyl601_mem)

src/mess/drivers/scv.c

r9684	r9685
38	38	};
39	39
40	40
41		static UINT8 *scv_vram;
42	41
43	42
44	43	static ADDRESS_MAP_START( scv_mem, ADDRESS_SPACE_PROGRAM, 8 )
45	44	AM_RANGE( 0x0000, 0x0fff ) AM_ROM      /* BIOS */
46	45
47		AM_RANGE( 0x2000, 0x3403 ) AM_RAM AM_BASE( &scv_vram )   /* VRAM + 4 registers */
	46	AM_RANGE( 0x2000, 0x3403 ) AM_RAM AM_BASE_MEMBER(scv_state, vram )   /* VRAM + 4 registers */
48	47
49	48	AM_RANGE( 0x3600, 0x3600 ) AM_DEVWRITE( "upd1771c", upd1771_w )
50	49
r9684	r9685
449	448	}
450	449
451	450
452		INLINE void draw_sprite( bitmap_t *bitmap, UINT8 x, UINT8 y, UINT8 tile_idx, UINT8 col, UINT8 left, UINT8 right, UINT8 top, UINT8 bottom, UINT8 clip_y )
	451	INLINE void draw_sprite( scv_state *state, bitmap_t *bitmap, UINT8 x, UINT8 y, UINT8 tile_idx, UINT8 col, UINT8 left, UINT8 right, UINT8 top, UINT8 bottom, UINT8 clip_y )
453	452	{
454	453	int j;
455	454
456	455	y += clip_y * 2;
457	456	for ( j = clip_y * 4; j < 32; j += 4 )
458	457	{
459		UINT8 pat0 = scv_vram[ tile_idx * 32 + j + 0 ];
460		UINT8 pat1 = scv_vram[ tile_idx * 32 + j + 1 ];
461		UINT8 pat2 = scv_vram[ tile_idx * 32 + j + 2 ];
462		UINT8 pat3 = scv_vram[ tile_idx * 32 + j + 3 ];
	458	UINT8 pat0 = state->vram[ tile_idx * 32 + j + 0 ];
	459	UINT8 pat1 = state->vram[ tile_idx * 32 + j + 1 ];
	460	UINT8 pat2 = state->vram[ tile_idx * 32 + j + 2 ];
	461	UINT8 pat3 = state->vram[ tile_idx * 32 + j + 3 ];
463	462
464	463	if ( ( top && j < 16 ) || ( bottom && j >= 16 ) )
465	464	{
r9684	r9685
561	560
562	561	static VIDEO_UPDATE( scv )
563	562	{
	563	scv_state *state = screen->machine->driver_data<scv_state>();
564	564	int x, y;
565		UINT8 fg = scv_vram[0x1403] >> 4;
566		UINT8 bg = scv_vram[0x1403] & 0x0f;
567		UINT8 gr_fg = scv_vram[0x1401] >> 4;
568		UINT8 gr_bg = scv_vram[0x1401] & 0x0f;
569		int clip_x = ( scv_vram[0x1402] & 0x0f ) * 2;
570		int clip_y = scv_vram[0x1402] >> 4;
	565	UINT8 fg = state->vram[0x1403] >> 4;
	566	UINT8 bg = state->vram[0x1403] & 0x0f;
	567	UINT8 gr_fg = state->vram[0x1401] >> 4;
	568	UINT8 gr_bg = state->vram[0x1401] & 0x0f;
	569	int clip_x = ( state->vram[0x1402] & 0x0f ) * 2;
	570	int clip_y = state->vram[0x1402] >> 4;
571	571
572	572	/* Clear the screen */
573	573	bitmap_fill( bitmap, cliprect, gr_bg );
r9684	r9685
578	578	int text_y = 0;
579	579
580	580	if ( y < clip_y )
581		text_y = ( scv_vram[0x1400] & 0x80 ) ? 0 : 1;
	581	text_y = ( state->vram[0x1400] & 0x80 ) ? 0 : 1;
582	582	else
583		text_y = ( scv_vram[0x1400] & 0x80 ) ? 1 : 0;
	583	text_y = ( state->vram[0x1400] & 0x80 ) ? 1 : 0;
584	584
585	585	for ( x = 0; x < 32; x++ )
586	586	{
587	587	int text_x = 0;
588		UINT8 d = scv_vram[ 0x1000 + y * 32 + x ];
	588	UINT8 d = state->vram[ 0x1000 + y * 32 + x ];
589	589
590	590	if ( x < clip_x )
591		text_x = ( scv_vram[0x1400] & 0x40 ) ? 0 : 1;
	591	text_x = ( state->vram[0x1400] & 0x40 ) ? 0 : 1;
592	592	else
593		text_x = ( scv_vram[0x1400] & 0x40 ) ? 1 : 0;
	593	text_x = ( state->vram[0x1400] & 0x40 ) ? 1 : 0;
594	594
595	595	if ( text_x && text_y )
596	596	{
r9684	r9685
600	600	}
601	601	else
602	602	{
603		switch ( scv_vram[0x1400] & 0x03 )
	603	switch ( state->vram[0x1400] & 0x03 )
604	604	{
605	605	case 0x01:      /* Semi graphics mode */
606	606	draw_semi_graph( bitmap, x * 8    , y * 16     , d & 0x80, gr_fg );
r9684	r9685
624	624	}
625	625
626	626	/* Draw sprites if enabled */
627		if ( scv_vram[0x1400] & 0x10 )
	627	if ( state->vram[0x1400] & 0x10 )
628	628	{
629	629	int i;
630	630
631	631	for ( i = 0; i < 128; i++ )
632	632	{
633		UINT8 spr_y = scv_vram[ 0x1200 + i * 4 ] & 0xfe;
634		UINT8 y_32 = scv_vram[ 0x1200 + i * 4 ] & 0x01;      /* Xx32 sprite */
635		UINT8 clip = scv_vram[ 0x1201 + i * 4 ] >> 4;
636		UINT8 col = scv_vram[ 0x1201 + i * 4 ] & 0x0f;
637		UINT8 spr_x = scv_vram[ 0x1202 + i * 4 ] & 0xfe;
638		UINT8 x_32 = scv_vram[ 0x1202 + i * 4 ] & 0x01;      /* 32xX sprite */
639		UINT8 tile_idx = scv_vram[ 0x1203 + i * 4 ] & 0x7f;
640		UINT8 half = scv_vram[ 0x1203 + i * 4] & 0x80;
	633	UINT8 spr_y = state->vram[ 0x1200 + i * 4 ] & 0xfe;
	634	UINT8 y_32 = state->vram[ 0x1200 + i * 4 ] & 0x01;      /* Xx32 sprite */
	635	UINT8 clip = state->vram[ 0x1201 + i * 4 ] >> 4;
	636	UINT8 col = state->vram[ 0x1201 + i * 4 ] & 0x0f;
	637	UINT8 spr_x = state->vram[ 0x1202 + i * 4 ] & 0xfe;
	638	UINT8 x_32 = state->vram[ 0x1202 + i * 4 ] & 0x01;      /* 32xX sprite */
	639	UINT8 tile_idx = state->vram[ 0x1203 + i * 4 ] & 0x7f;
	640	UINT8 half = state->vram[ 0x1203 + i * 4] & 0x80;
641	641	UINT8 left = 1;
642	642	UINT8 right = 1;
643	643	UINT8 top = 1;
r9684	r9685
681	681	}
682	682
683	683	/* Check if 2 color sprites are enabled */
684		if ( ( scv_vram[0x1400] & 0x20 ) && ( i & 0x20 ) )
	684	if ( ( state->vram[0x1400] & 0x20 ) && ( i & 0x20 ) )
685	685	{
686	686	/* 2 color sprite handling */
687		draw_sprite( bitmap, spr_x, spr_y, tile_idx, col, left, right, top, bottom, clip );
	687	draw_sprite( state, bitmap, spr_x, spr_y, tile_idx, col, left, right, top, bottom, clip );
688	688	if ( x_32 || y_32 )
689	689	{
690	690	static const UINT8 spr_2col_lut0[16] = { 0, 15, 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 1, 1 };
691	691	static const UINT8 spr_2col_lut1[16] = { 0, 1, 8, 11, 2, 3, 10, 9, 4, 5, 12, 13, 6, 7, 14, 15 };
692	692
693		draw_sprite( bitmap, spr_x, spr_y, tile_idx + 8 * x_32 + y_32, ( i & 0x40 ) ? spr_2col_lut1[col] : spr_2col_lut0[col], left, right, top, bottom, clip );
	693	draw_sprite( state, bitmap, spr_x, spr_y, tile_idx + 8 * x_32 + y_32, ( i & 0x40 ) ? spr_2col_lut1[col] : spr_2col_lut0[col], left, right, top, bottom, clip );
694	694	}
695	695	}
696	696	else
697	697	{
698	698	/* regular sprite handling */
699		draw_sprite( bitmap, spr_x, spr_y, tile_idx, col, left, right, top, bottom, clip );
	699	draw_sprite( state, bitmap, spr_x, spr_y, tile_idx, col, left, right, top, bottom, clip );
700	700	if ( x_32 )
701	701	{
702		draw_sprite( bitmap, spr_x + 16, spr_y, tile_idx + 8, col, 1, 1, top, bottom, clip );
	702	draw_sprite( state, bitmap, spr_x + 16, spr_y, tile_idx + 8, col, 1, 1, top, bottom, clip );
703	703	}
704	704	if ( y_32 )
705	705	{
706	706	clip &= 0x07;
707		draw_sprite( bitmap, spr_x, spr_y + 16, tile_idx + 1, col, left, right, 1, 1, clip );
	707	draw_sprite( state, bitmap, spr_x, spr_y + 16, tile_idx + 1, col, left, right, 1, 1, clip );
708	708	if ( x_32 )
709	709	{
710		draw_sprite( bitmap, spr_x + 16, spr_y + 16, tile_idx + 9, col, 1, 1, 1, 1, clip );
	710	draw_sprite( state, bitmap, spr_x + 16, spr_y + 16, tile_idx + 9, col, 1, 1, 1, 1, clip );
711	711	}
712	712	}
713	713	}

src/mess/drivers/zrt80.c

r9684	r9685
11	11	#include "video/mc6845.h"
12	12	#include "machine/ins8250.h"
13	13
14		static UINT8 *video_ram;
15	14
	15	class zrt80_state : public driver_device
	16	{
	17	public:
	18	zrt80_state(running_machine &machine, const driver_device_config_base &config)
	19	: driver_device(machine, config) { }
	20
	21	UINT8 *video_ram;
	22	};
	23
	24
	25
16	26	static ADDRESS_MAP_START(zrt80_mem, ADDRESS_SPACE_PROGRAM, 8)
17	27	ADDRESS_MAP_UNMAP_HIGH
18	28	AM_RANGE(0x0000, 0x0fff) AM_ROM // Z25 - Main firmware
19	29	AM_RANGE(0x1000, 0x1fff) AM_ROM // Z24 - Expansion
20	30	AM_RANGE(0x4000, 0x43ff) AM_RAM   // Board RAM
21	31	// Normaly video RAM is 0x800 but could be expanded up to 8K
22		AM_RANGE(0xc000, 0xdfff) AM_RAM    AM_BASE(&video_ram) // Video RAM
	32	AM_RANGE(0xc000, 0xdfff) AM_RAM    AM_BASE_MEMBER(zrt80_state, video_ram) // Video RAM
23	33
24	34	ADDRESS_MAP_END
25	35
r9684	r9685
133	143
134	144	static MC6845_UPDATE_ROW( zrt80_update_row )
135	145	{
	146	zrt80_state *state = device->machine->driver_data<zrt80_state>();
136	147	UINT8 *charrom = memory_region(device->machine, "chargen");
137	148
138	149	int column, bit;
139	150
140	151	for (column = 0; column < x_count; column++)
141	152	{
142		UINT8 code = video_ram[ma + column] & 0x7f;
	153	UINT8 code = state->video_ram[ma + column] & 0x7f;
143	154	UINT16 addr = code << 4 | (ra & 0x0f);
144	155	UINT8 data = charrom[addr & 0x7ff];
145	156
r9684	r9685
204	215	GFXDECODE_ENTRY( "chargen", 0x0000, zrt80_charlayout, 0, 1 )
205	216	GFXDECODE_END
206	217
207		static MACHINE_CONFIG_START( zrt80, driver_device )
	218	static MACHINE_CONFIG_START( zrt80, zrt80_state )
208	219	/* basic machine hardware */
209	220	MDRV_CPU_ADD("maincpu",Z80, XTAL_2_4576MHz)
210	221	MDRV_CPU_PROGRAM_MAP(zrt80_mem)

src/mess/drivers/pcm.c

r9684	r9685
9	9	#include "emu.h"
10	10	#include "cpu/z80/z80.h"
11	11
12		static UINT8 *pcm_video_ram;
13	12
	13	class pcm_state : public driver_device
	14	{
	15	public:
	16	pcm_state(running_machine &machine, const driver_device_config_base &config)
	17	: driver_device(machine, config) { }
	18
	19	UINT8 *video_ram;
	20	};
	21
	22
	23
14	24	static ADDRESS_MAP_START(pcm_mem, ADDRESS_SPACE_PROGRAM, 8)
15	25	ADDRESS_MAP_UNMAP_HIGH
16	26	AM_RANGE( 0x0000, 0x1fff ) AM_ROM  // ROM
17	27	AM_RANGE( 0x2000, 0xf7ff ) AM_RAM  // RAM
18		AM_RANGE( 0xf800, 0xffff ) AM_RAM AM_BASE(&pcm_video_ram) // Video RAM
	28	AM_RANGE( 0xf800, 0xffff ) AM_RAM AM_BASE_MEMBER(pcm_state, video_ram) // Video RAM
19	29	ADDRESS_MAP_END
20	30
21	31	static ADDRESS_MAP_START( pcm_io , ADDRESS_SPACE_IO, 8)
r9684	r9685
35	45
36	46	static VIDEO_UPDATE( pcm )
37	47	{
	48	pcm_state *state = screen->machine->driver_data<pcm_state>();
38	49	UINT8 code;
39	50	UINT8 line;
40	51	int y, x, j, b;
r9684	r9685
45	56	{
46	57	for (x = 0; x < 64; x++)
47	58	{
48		code = pcm_video_ram[(0x400 + y*64 + x) & 0x7ff];
	59	code = state->video_ram[(0x400 + y*64 + x) & 0x7ff];
49	60	for(j = 0; j < 8; j++ )
50	61	{
51	62	line = gfx[code*8 + j];
r9684	r9685
60	71	}
61	72
62	73
63		static MACHINE_CONFIG_START( pcm, driver_device )
	74	static MACHINE_CONFIG_START( pcm, pcm_state )
64	75	/* basic machine hardware */
65	76	MDRV_CPU_ADD("maincpu",Z80, XTAL_10MHz /4)
66	77	MDRV_CPU_PROGRAM_MAP(pcm_mem)

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