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r14846 Tuesday 3rd April, 2012 at 11:22:43 UTC by Miodrag Milanović
Sync with MAME r15868 (no whatsnew)

[src/emu/machine]	i8155.c i8155.h
[src/emu/sound]	ymf271.c
[src/mame]	mame.lst
[src/mame/audio]	gottlieb.c
[src/mame/drivers]	1945kiii.c 30test.c 39in1.c 5clown.c ace.c acefruit.c acommand.c adp.c albazc.c albazg.c aristmk4.c aristmk5.c aristmk6.c astinvad.c astrocorp.c atarisy4.c attckufo.c atvtrack.c avt.c backfire.c beaminv.c berzerk.c bestleag.c bfcobra.c bfm_sc1.c bfm_sc2.c bfm_sc4.c bfmsys85.c big10.c bingoc.c bingor.c blackt96.c blitz.c blitz68k.c bmcbowl.c bnstars.c boxer.c buster.c bwidow.c cabaret.c calorie.c cardline.c caswin.c cball.c cham24.c chanbara.c chinsan.c clayshoo.c cliffhgr.c cmmb.c cntsteer.c coinmstr.c coinmvga.c coolridr.c corona.c crystal.c cshooter.c csplayh5.c cubeqst.c cultures.c cybertnk.c cyclemb.c d9final.c dacholer.c dai3wksi.c darkhors.c dblewing.c ddayjlc.c ddealer.c deco156.c deco_ld.c deshoros.c destroyr.c dgpix.c discoboy.c diverboy.c dlair.c dmndrby.c dominob.c dorachan.c dotrikun.c dreamwld.c drtomy.c drw80pkr.c dunhuang.c dwarfd.c dynadice.c ecoinf2.c ecoinf3.c egghunt.c embargo.c enigma2.c eolith16.c ertictac.c esh.c ettrivia.c f-32.c famibox.c feversoc.c firefox.c flyball.c gal3.c galaxi.c galgame.c gei.c ggconnie.c ghosteo.c go2000.c goldngam.c goldnpkr.c good.c goodejan.c gottlieb.c gpworld.c gstream.c gticlub.c guab.c gunpey.c halleys.c highvdeo.c hitpoker.c hornet.c hotblock.c hotstuff.c hvyunit.c igs009.c igs011.c igs017.c igs_m027.c igspoker.c imolagp.c intrscti.c istellar.c jackie.c jackpool.c jalmah.c jangou.c jantotsu.c jokrwild.c jollyjgr.c jongkyo.c jpmsys5.c jubilee.c kas89.c kingdrby.c kingpin.c kinst.c koftball.c koikoi.c konamim2.c kongambl.c laserbas.c lastfght.c lgp.c limenko.c littlerb.c looping.c ltcasino.c luckgrln.c m14.c m63.c m79amb.c macs.c magic10.c magicard.c magicfly.c majorpkr.c marinedt.c mastboy.c maxaflex.c maygay1b.c maygayv1.c mayumi.c mazerbla.c meijinsn.c merit.c meritm.c mgolf.c midas.c mil4000.c miniboy7.c mirage.c mirax.c missile.c mjsister.c mlanding.c mogura.c mole.c monzagp.c mpoker.c mpu3.c multfish.c murogem.c mw18w.c mwarr.c namcos2.c namcos23.c neodrvr.c neoprint.c nexus3d.c nightgal.c nmg5.c nmk16.c nsmpoker.c nwk-tr.c nyny.c olibochu.c omegrace.c onetwo.c othello.c pachifev.c panicr.c paranoia.c pasha2.c pengadvb.c peplus.c peyper.c photon2.c pinkiri8.c pipeline.c pkscram.c poker72.c poo.c popobear.c ppmast93.c progolf.c psattack.c pturn.c pzletime.c quantum.c quizo.c quizpun2.c quizshow.c r2dtank.c r2dx_v33.c rabbit.c rbmk.c re900.c rmhaihai.c roul.c royalmah.c safarir.c sangho.c sbowling.c sbrkout.c sbugger.c segald.c sengokmj.c sfbonus.c sfkick.c shanghai.c shougi.c sigmab52.c sigmab98.c skeetsht.c skimaxx.c skyarmy.c skylncr.c sliver.c slotcarn.c sms.c sothello.c spaceg.c speglsht.c splus.c spoker.c spool99.c srmp5.c srmp6.c ssfindo.c sshot.c ssingles.c sstrangr.c statriv2.c sub.c subsino.c subsino2.c summit.c supdrapo.c superdq.c supertnk.c superwng.c suprgolf.c taitopjc.c taitotz.c tapatune.c tempest.c tgtpanic.c thayers.c tickee.c timetrv.c tmaster.c tmmjprd.c tmspoker.c tomcat.c tonton.c toratora.c tourvis.c trvmadns.c ttchamp.c tugboat.c twins.c uapce.c ultrsprt.c umipoker.c unkhorse.c vamphalf.c vcombat.c vegaeo.c videopkr.c vpoker.c vroulet.c wallc.c warpsped.c wheelfir.c wink.c witch.c wldarrow.c xtheball.c zr107.c
[src/mame/includes]	neogeo.h nmk16.h
[src/mame/machine]	cps2crpt.c neocrypt.c neoprot.c
[src/mame/video]	nmk16.c

src/mame/mame.lst

r14845	r14846
7015	7015	kof99p         // 0251 (c) 1999 SNK
7016	7016	ganryu         // 0252 (c) 1999 Visco
7017	7017	garou         // 0253 (c) 1999 SNK
7018		garouo         // 0253 (c) 1999 SNK
	7018	garouh         // 0253 (c) 1999 SNK
7019	7019	garoup         // 0253 (c) 1999 SNK
7020	7020	garoubl         // bootleg
7021	7021	s1945p         // 0254 (c) 1999 Psikyo

src/mame/audio/gottlieb.c

r14845	r14846
161	161	}
162	162
163	163	mame_printf_debug("Votrax played '%s'\n", phonemes);
164		if (strcmp(phonemes, "[0] HEH3LOOW     AH1EH3I3YMTERI2NDAHN") == 0)     /* Q-Bert - Hello, I am turned on */
165		m_samples->start(0, 42);
	164
	165	if (strcmp(phonemes, "[0] HEH3LOOW     AH1EH3I3YMTERI2NDAHN") == 0)     /* Q-Bert & Tylz - Hello, I am turned on */
	166	m_samples->start(0, 42);
166	167	else if (strcmp(phonemes, "[0]BAH1EH1Y") == 0)                       /* Q-Bert - Bye, bye */
167	168	m_samples->start(0, 43);
168	169	else if (strcmp(phonemes, "[0]A2YHT LEH2FTTH") == 0)                 /* Reactor - Eight left */

src/mame/machine/neoprot.c

r14845	r14846
6	6	ssideki, fatfury2, kof98 (some versions), mslugx
7	7
8	8	SMA chip
9		kof99, garou, garouo, mslug3, kof2002
	9	kof99, garou, garouh, mslug3, kof2002
10	10
11	11	custom banking, random number generator
12	12	encryption (see machine/neocrypt.c)
r14845	r14846
257	257	}
258	258
259	259
260		static WRITE16_HANDLER( garouo_bankswitch_w )
	260	static WRITE16_HANDLER( garouh_bankswitch_w )
261	261	{
262	262	/* thanks to Razoola and Mr K for the info */
263	263	int bankaddress;
r14845	r14846
428	428	}
429	429
430	430
431		void garouo_install_protection( running_machine &machine )
	431	void garouh_install_protection( running_machine &machine )
432	432	{
433		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x2fffc0, 0x2fffc1, FUNC(garouo_bankswitch_w));
	433	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x2fffc0, 0x2fffc1, FUNC(garouh_bankswitch_w));
434	434	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x2fe446, 0x2fe447, FUNC(prot_9a37_r));
435	435
436	436	sma_install_random_read_handler(machine, 0x2fffcc, 0x2ffff0);

src/mame/machine/neocrypt.c

r14845	r14846
28	28
29	29	kof98
30	30	- unique early encryption
31		kof99, garou, garouo, mslug3, kof2000
	31	kof99, garou, garouh, mslug3, kof2000
32	32	- complex SMA chip which appears to contain part of the game rom
33	33	internally and decrypts the 68k code on the board.  Also has a
34	34	random number generator and  custom bankswitching
r14845	r14846
1000	1000	}
1001	1001
1002	1002
1003		/* kof99, garou, garouo, mslug3 and kof2000 have and SMA chip which contains program code and decrypts the 68k roms */
	1003	/* kof99, garou, garouh, mslug3 and kof2000 have and SMA chip which contains program code and decrypts the 68k roms */
1004	1004	void kof99_decrypt_68k(running_machine &machine)
1005	1005	{
1006	1006	UINT16 *rom;
r14845	r14846
1067	1067	}
1068	1068
1069	1069
1070		void garouo_decrypt_68k(running_machine &machine)
	1070	void garouh_decrypt_68k(running_machine &machine)
1071	1071	{
1072	1072	UINT16 *rom;
1073	1073	int i,j;

src/mame/machine/cps2crpt.c

r14845	r14846
973	973	{ "mpangj",   { 0x95f741c6,0xe547a21b }, 0x100000 },   // 0C84 347D 89A3  cmpi.l  #$347D89A3,D4
974	974	{ "pzloop2",  { 0xa054f812,0xc40d36b4 }, 0x400000 },   // 0C82 9A73 15F1  cmpi.l  #$9A7315F1,D2
975	975	{ "pzloop2j", { 0xa054f812,0xc40d36b4 }, 0x400000 },   // 0C82 9A73 15F1  cmpi.l  #$9A7315F1,D2
	976	{ "pzloop2jr1",{ 0xa054f812,0xc40d36b4 }, 0x400000 },   // 0C82 9A73 15F1  cmpi.l  #$9A7315F1,D2
976	977	{ "choko",    { 0xd3fb12c6,0x7f8e17b5 }, 0x400000 },   // 0C86 4D17 5B3C  cmpi.l  #$4D175B3C,D6
977	978	{ "dimahoo",  { 0x0ddb8e40,0x2817fd2b }, 0x080000 },   // BE4C B244 B6C5  cmp.w   A4,D7   cmp.w   D4,D1   cmpa.w  D5,A3
978	979	{ "dimahoou", { 0x6575af59,0xb0fea691 }, 0x080000 },   // BE4C B244 B6C5  cmp.w   A4,D7   cmp.w   D4,D1   cmpa.w  D5,A3

src/mame/includes/nmk16.h

r14845	r14846
67	67	WRITE16_HANDLER( manybloc_scroll_w );
68	68
69	69	VIDEO_START( macross );
70		SCREEN_UPDATE_IND16( manybloc );
71	70	VIDEO_START( gunnail );
72	71	VIDEO_START( macross2 );
73	72	VIDEO_START( raphero );
74	73	VIDEO_START( bjtwin );
75	74	VIDEO_START( bioship );
76	75	VIDEO_START( strahl );
77		SCREEN_UPDATE_IND16( bioship );
78		SCREEN_UPDATE_IND16( strahl );
79	76	SCREEN_UPDATE_IND16( macross );
	77	SCREEN_UPDATE_IND16( manybloc );
	78	SCREEN_UPDATE_IND16( tharrier );
	79	SCREEN_UPDATE_IND16( tdragon2 );
80	80	SCREEN_UPDATE_IND16( gunnail );
	81	SCREEN_UPDATE_IND16( bioship );
	82	SCREEN_UPDATE_IND16( strahl );
81	83	SCREEN_UPDATE_IND16( bjtwin );
82		SCREEN_UPDATE_IND16( tharrier );
83		SCREEN_UPDATE_IND16( hachamf );
84		SCREEN_UPDATE_IND16( tdragon );
85	84	SCREEN_VBLANK( nmk );
86	85	SCREEN_VBLANK( strahl );
87	86

src/mame/includes/neogeo.h

r14845	r14846
134	134	void neogeo_sfix_decrypt(running_machine &machine);
135	135	void kof99_decrypt_68k(running_machine &machine);
136	136	void garou_decrypt_68k(running_machine &machine);
137		void garouo_decrypt_68k(running_machine &machine);
	137	void garouh_decrypt_68k(running_machine &machine);
138	138	void mslug3_decrypt_68k(running_machine &machine);
139	139	void kof2000_decrypt_68k(running_machine &machine);
140	140	void kof98_decrypt_68k(running_machine &machine);
r14845	r14846
161	161	void mslugx_install_protection(running_machine &machine);
162	162	void kof99_install_protection(running_machine &machine);
163	163	void garou_install_protection(running_machine &machine);
164		void garouo_install_protection(running_machine &machine);
	164	void garouh_install_protection(running_machine &machine);
165	165	void mslug3_install_protection(running_machine &machine);
166	166	void kof2000_install_protection(running_machine &machine);
167	167	void install_kof98_protection(running_machine &machine);

src/mame/video/nmk16.c

r14845	r14846
521	521	}
522	522	}
523	523
524		static void nmk16_draw_sprites2(running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, int *swaptbl)
	524	static void nmk16_draw_sprites_swap(running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, int *bittbl)
525	525	{
526	526	nmk16_state *state = machine.driver_data<nmk16_state>();
527		int i, l, prio;
	527	int i, prio;
528	528
529		// Priority level (0x10 levels, 4 sub-levels, 0x10 sprites each)
530		for ( i = 0; i < 0x10; i++ )
531		{
532		// Sub-priority level (4 levels)
	529	// Priority level (4 levels, 0x100 sprites)
533	530	for ( prio = 3; prio >= 0; prio-- )
534	531	{
535	532	// Sprite
536		for ( l = 0; l < 0x10; l++ )
	533	for ( i = 0; i < 0x100; i++ )
537	534	{
538		nmk16_draw_sprite(state, machine, bitmap, cliprect, prio, state->m_spriteram_old2 + ((swaptbl[i] + l) * 8));
539		}
	535	int spr = BITSWAP8(i, bittbl[0], bittbl[1], bittbl[2], bittbl[3], bittbl[4], bittbl[5], bittbl[6], bittbl[7]);
	536	nmk16_draw_sprite(state, machine, bitmap, cliprect, prio, state->m_spriteram_old2 + (spr * 8));
540	537	}
541	538	}
542	539	}
543	540
544		static void nmk16_draw_sprites2_flipsupported(running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, int *swaptbl)
	541	static void nmk16_draw_sprites_swap_flipsupported(running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, int *bittbl)
545	542	{
546	543	nmk16_state *state = machine.driver_data<nmk16_state>();
547		int i, l, prio;
	544	int i, prio;
548	545
549		// Priority level (0x10 levels, 4 sub-levels, 0x10 sprites each)
550		for ( i = 0; i < 0x10; i++ )
551		{
552		// Sub-priority level (4 levels)
	546	// Priority level (4 levels, 0x100 sprites)
553	547	for ( prio = 3; prio >= 0; prio-- )
554	548	{
555	549	// Sprite
556		for ( l = 0; l < 0x10; l++ )
	550	for ( i = 0; i < 0x100; i++ )
557	551	{
558		nmk16_draw_sprite_flipsupported(state, machine, bitmap, cliprect, prio, state->m_spriteram_old2 + ((swaptbl[i] + l) * 8));
559		}
	552	int spr = BITSWAP8(i, bittbl[0], bittbl[1], bittbl[2], bittbl[3], bittbl[4], bittbl[5], bittbl[6], bittbl[7]);
	553	nmk16_draw_sprite_flipsupported(state, machine, bitmap, cliprect, prio, state->m_spriteram_old2 + (spr * 16/2));
560	554	}
561	555	}
562	556	}
r14845	r14846
586	580	}
587	581	}
588	582
589		SCREEN_UPDATE_IND16( macross )
	583	/***************************************************************************
	584
	585
	586	Generic Screen Updates
	587
	588
	589	***************************************************************************/
	590
	591	int nmk16_bg_spr_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
590	592	{
591	593	nmk16_state *state = screen.machine().driver_data<nmk16_state>();
592		state->m_tx_tilemap->set_scrollx(0,-state->m_videoshift);
	594	state->m_bg_tilemap0->set_scrollx(0,-state->m_videoshift);
593	595
594	596	state->m_bg_tilemap0->draw(bitmap, cliprect, 0,0);
595	597
596		static int macross_swaptbl[0x10] = {
597		0x00, 0x80, 0x20, 0xA0, 0x40, 0xC0, 0x60, 0xE0,
598		0x10, 0x90, 0x30, 0xB0, 0x50, 0xD0, 0x70, 0xF0,
599		};
600		nmk16_draw_sprites2(screen.machine(), bitmap,cliprect, macross_swaptbl);
601
602		state->m_tx_tilemap->draw(bitmap, cliprect, 0,0);
	598	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,3);
	599	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,2);
	600	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,1);
	601	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,0);
603	602	return 0;
604	603	}
605	604
606		SCREEN_UPDATE_IND16( tdragon )
	605	int nmk16_bg_fg_spr_tx_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
607	606	{
608	607	nmk16_state *state = screen.machine().driver_data<nmk16_state>();
609		//  mcu_run(screen.machine(), 1);
610
611	608	state->m_tx_tilemap->set_scrollx(0,-state->m_videoshift);
612	609
613	610	state->m_bg_tilemap0->draw(bitmap, cliprect, 0,0);
	611	state->m_fg_tilemap->draw(bitmap, cliprect, 0,0);
614	612
615		// TODO: Fix this swap table; it's currently incorrect
616		static int tdragon_swaptbl[0x10] = {
617		0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
618		0x80, 0x90, 0xA0, 0xB0, 0xC0, 0xD0, 0xE0, 0xF0,
619		};
620		nmk16_draw_sprites2(screen.machine(), bitmap,cliprect, tdragon_swaptbl);
	613	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,3);
	614	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,2);
	615	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,1);
	616	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,0);
621	617
622	618	state->m_tx_tilemap->draw(bitmap, cliprect, 0,0);
623	619	return 0;
624	620	}
625	621
626		SCREEN_UPDATE_IND16( hachamf )
	622	int nmk16_bg_spr_tx_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
627	623	{
628	624	nmk16_state *state = screen.machine().driver_data<nmk16_state>();
629		//  mcu_run(screen.machine(), 0);
630
631	625	state->m_tx_tilemap->set_scrollx(0,-state->m_videoshift);
632	626
633	627	state->m_bg_tilemap0->draw(bitmap, cliprect, 0,0);
634	628
635		// TODO: Fix this swap table; it's currently incorrect
636		static int hachamf_swaptbl[0x10] = {
637		0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
638		0x80, 0x90, 0xA0, 0xB0, 0xC0, 0xD0, 0xE0, 0xF0,
639		};
640		nmk16_draw_sprites2(screen.machine(), bitmap,cliprect, hachamf_swaptbl);
641		/*  nmk16_draw_sprites(screen.machine(), bitmap,cliprect,3);
	629	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,3);
642	630	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,2);
643	631	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,1);
644		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,0);*/
	632	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,0);
645	633
646	634	state->m_tx_tilemap->draw(bitmap, cliprect, 0,0);
647	635	return 0;
648	636	}
649	637
650		SCREEN_UPDATE_IND16( manybloc )
	638	int nmk16_bg_sprflip_tx_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
651	639	{
652	640	nmk16_state *state = screen.machine().driver_data<nmk16_state>();
653	641	state->m_tx_tilemap->set_scrollx(0,-state->m_videoshift);
r14845	r14846
663	651	return 0;
664	652	}
665	653
666		SCREEN_UPDATE_IND16( tharrier )
	654	int nmk16_bioshipbg_sprflip_tx_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
667	655	{
668	656	nmk16_state *state = screen.machine().driver_data<nmk16_state>();
669		/* I think the protection device probably copies this to the regs... */
670		UINT16 tharrier_scroll = state->m_mainram[0x9f00/2];
	657	UINT16 *tilerom = (UINT16 *)screen.machine().region("gfx5")->base();
	658	int scrollx=-(state->m_bioship_scroll[1] + state->m_bioship_scroll[0]*256);
	659	int scrolly=-(state->m_bioship_scroll[3] + state->m_bioship_scroll[2]*256);
671	660
672	661	state->m_tx_tilemap->set_scrollx(0,-state->m_videoshift);
673		state->m_bg_tilemap0->set_scrollx(0,tharrier_scroll);
	662
	663	if (state->m_redraw_bitmap)
	664	{
	665	int bank = state->m_bioship_background_bank * 0x2000;
	666	int sx=0, sy=0, offs;
	667	state->m_redraw_bitmap=0;
	668
	669	/* Draw background from tile rom */
	670	for (offs = 0;offs <0x1000;offs++) {
	671	UINT16 data = tilerom[offs+bank];
	672	int numtile = data&0xfff;
	673	int color = (data&0xf000)>>12;
	674
	675	drawgfx_opaque(*state->m_background_bitmap,state->m_background_bitmap->cliprect(),screen.machine().gfx[3],
	676	numtile,
	677	color,
	678	0,0,   /* no flip */
	679	16*sx,16*sy);
	680
	681	data = tilerom[offs+0x1000+bank];
	682	numtile = data&0xfff;
	683	color = (data&0xf000)>>12;
	684	drawgfx_opaque(*state->m_background_bitmap,state->m_background_bitmap->cliprect(),screen.machine().gfx[3],
	685	numtile,
	686	color,
	687	0,0,   /* no flip */
	688	16*sx,(16*sy)+256);
	689
	690	sy++;
	691	if (sy==16) {sy=0; sx++;}
	692	}
	693	}
	694
	695	copyscrollbitmap(bitmap,*state->m_background_bitmap,1,&scrollx,1,&scrolly,cliprect);
674	696	state->m_bg_tilemap0->draw(bitmap, cliprect, 0,0);
675	697
676		// TODO: Fix this swap table; it's currently incorrect
677		static int tharrier_swaptbl[0x10] = {
678		0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
679		0x80, 0x90, 0xA0, 0xB0, 0xC0, 0xD0, 0xE0, 0xF0,
680		};
681		nmk16_draw_sprites2_flipsupported(screen.machine(), bitmap,cliprect, tharrier_swaptbl);
	698	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,3);
	699	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,2);
	700	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,1);
	701	nmk16_draw_sprites(screen.machine(), bitmap,cliprect,0);
682	702
683	703	state->m_tx_tilemap->draw(bitmap, cliprect, 0,0);
684	704	return 0;
685	705	}
686	706
687		SCREEN_UPDATE_IND16( gunnail )
	707	int nmk16_bg_sprswap_tx_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int bittbl[8])
688	708	{
689	709	nmk16_state *state = screen.machine().driver_data<nmk16_state>();
690		int y1;
691		int i=16;
692		rectangle bgclip = cliprect;
	710	state->m_tx_tilemap->set_scrollx(0,-state->m_videoshift);
693	711
	712	state->m_bg_tilemap0->draw(bitmap, cliprect, 0,0);
	713
	714	nmk16_draw_sprites_swap(screen.machine(), bitmap,cliprect, bittbl);
	715
	716	state->m_tx_tilemap->draw(bitmap, cliprect, 0,0);
	717	return 0;
	718	}
	719
	720	int nmk16_bg_sprswapflip_tx_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int bittbl[8])
	721	{
	722	nmk16_state *state = screen.machine().driver_data<nmk16_state>();
	723	state->m_tx_tilemap->set_scrollx(0,-state->m_videoshift);
	724
	725	state->m_bg_tilemap0->draw(bitmap, cliprect, 0,0);
	726
	727	nmk16_draw_sprites_swap_flipsupported(screen.machine(), bitmap,cliprect, bittbl);
	728
	729	state->m_tx_tilemap->draw(bitmap, cliprect, 0,0);
	730	return 0;
	731	}
	732
	733	int nmk16_complexbg_sprswap_tx_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int bittbl[8])
	734	{
	735	nmk16_state *state = screen.machine().driver_data<nmk16_state>();
	736	state->m_tx_tilemap->set_scrollx(0,-state->m_videoshift);
	737
694	738	// the hardware supports per-scanline X *and* Y scroll which isn't
695	739	// supported by tilemaps so we have to draw the tilemap one line at a time
696		y1 = cliprect.min_y;
697
698	740	if (!state->m_simple_scroll)
699	741	{
	742	int i=16;
	743	int y1;
	744	rectangle bgclip = cliprect;
	745	y1 = cliprect.min_y;
700	746	while (y1 <= cliprect.max_y)
701	747	{
702	748	int const yscroll = state->m_gunnail_scrollramy[0] + state->m_gunnail_scrollramy[y1];
r14845	r14846
753	799	bg_tilemap->draw(bitmap, cliprect, 0,0);
754	800	}
755	801
756		static int gunnail_swaptbl[0x10] = {
757		0x00, 0x80, 0x20, 0xA0, 0x40, 0xC0, 0x60, 0xE0,
758		0x10, 0x90, 0x30, 0xB0, 0x50, 0xD0, 0x70, 0xF0,
759		};
760		nmk16_draw_sprites2(screen.machine(), bitmap,cliprect, gunnail_swaptbl);
	802	nmk16_draw_sprites_swap(screen.machine(), bitmap,cliprect, bittbl);
761	803
762		state->m_tx_tilemap->set_scrollx(0,-state->m_videoshift);
763	804	state->m_tx_tilemap->draw(bitmap, cliprect, 0,0);
764	805	return 0;
765	806	}
766	807
767		SCREEN_UPDATE_IND16( bioship )
768		{
769		nmk16_state *state = screen.machine().driver_data<nmk16_state>();
770		UINT16 *tilerom = (UINT16 *)screen.machine().region("gfx5")->base();
771		int scrollx=-(state->m_bioship_scroll[1] + state->m_bioship_scroll[0]*256);
772		int scrolly=-(state->m_bioship_scroll[3] + state->m_bioship_scroll[2]*256);
	808	/***************************************************************************
773	809
774		state->m_tx_tilemap->set_scrollx(0,-state->m_videoshift);
775	810
776		if (state->m_redraw_bitmap)
777		{
778		int bank = state->m_bioship_background_bank * 0x2000;
779		int sx=0, sy=0, offs;
780		state->m_redraw_bitmap=0;
	811	Screen update functions
781	812
782		/* Draw background from tile rom */
783		for (offs = 0;offs <0x1000;offs++) {
784		UINT16 data = tilerom[offs+bank];
785		int numtile = data&0xfff;
786		int color = (data&0xf000)>>12;
787	813
788		drawgfx_opaque(*state->m_background_bitmap,state->m_background_bitmap->cliprect(),screen.machine().gfx[3],
789		numtile,
790		color,
791		0,0,   /* no flip */
792		16*sx,16*sy);
	814	***************************************************************************/
793	815
794		data = tilerom[offs+0x1000+bank];
795		numtile = data&0xfff;
796		color = (data&0xf000)>>12;
797		drawgfx_opaque(*state->m_background_bitmap,state->m_background_bitmap->cliprect(),screen.machine().gfx[3],
798		numtile,
799		color,
800		0,0,   /* no flip */
801		16*sx,(16*sy)+256);
	816	SCREEN_UPDATE_IND16( macross )
	817	{
	818	return nmk16_bg_spr_tx_update(screen, bitmap, cliprect);
	819	}
802	820
803		sy++;
804		if (sy==16) {sy=0; sx++;}
805		}
806		}
	821	SCREEN_UPDATE_IND16( manybloc )
	822	{
	823	return nmk16_bg_sprflip_tx_update(screen, bitmap, cliprect);
	824	}
807	825
808		copyscrollbitmap(bitmap,*state->m_background_bitmap,1,&scrollx,1,&scrolly,cliprect);
809		state->m_bg_tilemap0->draw(bitmap, cliprect, 0,0);
	826	SCREEN_UPDATE_IND16( tharrier )
	827	{
	828	nmk16_state *state = screen.machine().driver_data<nmk16_state>();
	829	/* I think the protection device probably copies this to the regs... */
	830	UINT16 tharrier_scroll = state->m_mainram[0x9f00/2];
810	831
811		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,3);
812		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,2);
813		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,1);
814		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,0);
	832	state->m_bg_tilemap0->set_scrollx(0,tharrier_scroll);
815	833
816		state->m_tx_tilemap->draw(bitmap, cliprect, 0,0);
817		return 0;
	834	return nmk16_bg_sprflip_tx_update(screen, bitmap, cliprect);
818	835	}
819	836
820		SCREEN_UPDATE_IND16( strahl )
	837	SCREEN_UPDATE_IND16( tdragon2 )
821	838	{
822		nmk16_state *state = screen.machine().driver_data<nmk16_state>();
823		state->m_tx_tilemap->set_scrollx(0,-state->m_videoshift);
	839	static int bittbl[8] = {
	840	4, 6, 5, 7, 3, 2, 1, 0
	841	};
824	842
825		state->m_bg_tilemap0->draw(bitmap, cliprect, 0,0);
826		state->m_fg_tilemap->draw(bitmap, cliprect, 0,0);
	843	return nmk16_complexbg_sprswap_tx_update(screen, bitmap, cliprect, bittbl);
	844	}
827	845
828		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,3);
829		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,2);
830		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,1);
831		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,0);
	846	SCREEN_UPDATE_IND16( gunnail )
	847	{
	848	static int bittbl[8] = {
	849	7, 6, 5, 4, 3, 2, 1, 0
	850	};
832	851
833		state->m_tx_tilemap->draw(bitmap, cliprect, 0,0);
834		return 0;
	852	return nmk16_complexbg_sprswap_tx_update(screen, bitmap, cliprect, bittbl);
835	853	}
836	854
837		SCREEN_UPDATE_IND16( bjtwin )
	855	SCREEN_UPDATE_IND16( bioship )
838	856	{
839		nmk16_state *state = screen.machine().driver_data<nmk16_state>();
840		state->m_bg_tilemap0->set_scrollx(0,-state->m_videoshift);
	857	return nmk16_bioshipbg_sprflip_tx_update(screen, bitmap, cliprect);
	858	}
841	859
842		state->m_bg_tilemap0->draw(bitmap, cliprect, 0,0);
	860	SCREEN_UPDATE_IND16( strahl )
	861	{
	862	return nmk16_bg_fg_spr_tx_update(screen, bitmap, cliprect);
	863	}
843	864
844		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,3);
845		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,2);
846		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,1);
847		nmk16_draw_sprites(screen.machine(), bitmap,cliprect,0);
848
849		return 0;
	865	SCREEN_UPDATE_IND16( bjtwin )
	866	{
	867	return nmk16_bg_spr_update(screen, bitmap, cliprect);
850	868	}
851	869
852	870	SCREEN_VBLANK( nmk )

src/mame/drivers/bfcobra.c

r14845	r14846
271	271	struct blitter_t m_blitter;
272	272	struct ramdac_t m_ramdac;
273	273	struct fdc_t m_fdc;
	274	DECLARE_READ8_MEMBER(ramdac_r);
	275	DECLARE_WRITE8_MEMBER(ramdac_w);
	276	DECLARE_READ8_MEMBER(chipset_r);
	277	DECLARE_WRITE8_MEMBER(chipset_w);
	278	DECLARE_WRITE8_MEMBER(rombank_w);
	279	DECLARE_READ8_MEMBER(fdctrl_r);
	280	DECLARE_READ8_MEMBER(fddata_r);
	281	DECLARE_WRITE8_MEMBER(fdctrl_w);
	282	DECLARE_READ8_MEMBER(int_latch_r);
	283	DECLARE_READ8_MEMBER(meter_r);
	284	DECLARE_WRITE8_MEMBER(meter_w);
	285	DECLARE_READ8_MEMBER(latch_r);
	286	DECLARE_WRITE8_MEMBER(latch_w);
274	287	};
275	288
276	289
r14845	r14846
718	731	}
719	732
720	733
721		static READ8_HANDLER( ramdac_r )
	734	READ8_MEMBER(bfcobra_state::ramdac_r)
722	735	{
723		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
724		struct ramdac_t &ramdac = state->m_ramdac;
	736	struct ramdac_t &ramdac = m_ramdac;
725	737	UINT8 val = 0xff;
726	738
727	739	switch (offset & 3)
r14845	r14846
733	745	if (*count == 0)
734	746	{
735	747	rgb_t color;
736		color = palette_get_color(space->machine(), ramdac.addr_r);
	748	color = palette_get_color(machine(), ramdac.addr_r);
737	749
738	750	ramdac.color_r[0] = RGB_RED(color);
739	751	ramdac.color_r[1] = RGB_GREEN(color);
r14845	r14846
754	766	}
755	767	default:
756	768	{
757		mame_printf_debug("Unhandled RAMDAC read (PC:%.4x)\n", cpu_get_previouspc(&space->device()));
	769	mame_printf_debug("Unhandled RAMDAC read (PC:%.4x)\n", cpu_get_previouspc(&space.device()));
758	770	}
759	771	}
760	772
761	773	return val;
762	774	}
763	775
764		static WRITE8_HANDLER( ramdac_w )
	776	WRITE8_MEMBER(bfcobra_state::ramdac_w)
765	777	{
766		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
767		struct ramdac_t &ramdac = state->m_ramdac;
	778	struct ramdac_t &ramdac = m_ramdac;
768	779
769	780	switch (offset & 3)
770	781	{
r14845	r14846
779	790	ramdac.color_w[ramdac.count_w] = pal6bit(data);
780	791	if (++ramdac.count_w == 3)
781	792	{
782		palette_set_color_rgb(space->machine(), ramdac.addr_w, ramdac.color_w[0], ramdac.color_w[1], ramdac.color_w[2]);
	793	palette_set_color_rgb(machine(), ramdac.addr_w, ramdac.color_w[0], ramdac.color_w[1], ramdac.color_w[2]);
783	794	ramdac.count_w = 0;
784	795	ramdac.addr_w++;
785	796	}
r14845	r14846
859	870	}
860	871	}
861	872
862		static READ8_HANDLER( chipset_r )
	873	READ8_MEMBER(bfcobra_state::chipset_r)
863	874	{
864		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
865	875	UINT8 val = 0xff;
866	876
867	877	switch(offset)
r14845	r14846
870	880	case 2:
871	881	case 3:
872	882	{
873		val = state->m_bank_data[offset];
	883	val = m_bank_data[offset];
874	884	break;
875	885	}
876	886	case 6:
877	887	{
878	888	/* TODO */
879		val = state->m_vblank_irq << 4;
	889	val = m_vblank_irq << 4;
880	890	break;
881	891	}
882	892	case 7:
883	893	{
884		state->m_vblank_irq = 0;
	894	m_vblank_irq = 0;
885	895	val = 0x1;
886	896
887	897	/* TODO */
888		update_irqs(space->machine());
	898	update_irqs(machine());
889	899	break;
890	900	}
891	901	case 0x1C:
r14845	r14846
897	907	case 0x20:
898	908	{
899	909	/* Seems correct - used during RLE pic decoding */
900		val = state->m_blitter.dest.addr0;
	910	val = m_blitter.dest.addr0;
901	911	break;
902	912	}
903	913	case 0x22:
904	914	{
905		val = 0x40 | input_port_read(space->machine(), "JOYSTICK");
	915	val = 0x40 | input_port_read(machine(), "JOYSTICK");
906	916	break;
907	917	}
908	918	default:
909	919	{
910		mame_printf_debug("Flare One unknown read: 0x%.2x (PC:0x%.4x)\n", offset, cpu_get_previouspc(&space->device()));
	920	mame_printf_debug("Flare One unknown read: 0x%.2x (PC:0x%.4x)\n", offset, cpu_get_previouspc(&space.device()));
911	921	}
912	922	}
913	923
914	924	return val;
915	925	}
916	926
917		static WRITE8_HANDLER( chipset_w )
	927	WRITE8_MEMBER(bfcobra_state::chipset_w)
918	928	{
919		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
920	929	switch (offset)
921	930	{
922	931	case 0x01:
r14845	r14846
924	933	case 0x03:
925	934	{
926	935	if (data > 0x3f)
927		popmessage("%x: Unusual bank access (%x)\n", cpu_get_previouspc(&space->device()), data);
	936	popmessage("%x: Unusual bank access (%x)\n", cpu_get_previouspc(&space.device()), data);
928	937
929	938	data &= 0x3f;
930		state->m_bank_data[offset] = data;
931		z80_bank(space->machine(), offset, data);
	939	m_bank_data[offset] = data;
	940	z80_bank(machine(), offset, data);
932	941	break;
933	942	}
934	943
935	944	case 0x08:
936	945	{
937		state->m_flip_8 = data;
	946	m_flip_8 = data;
938	947	break;
939	948	}
940	949	case 9:
941		state->m_videomode = data;
	950	m_videomode = data;
942	951	break;
943	952
944	953	case 0x0B:
945	954	{
946		state->m_h_scroll = data;
	955	m_h_scroll = data;
947	956	break;
948	957	}
949	958	case 0x0C:
950	959	{
951		state->m_v_scroll = data;
	960	m_v_scroll = data;
952	961	break;
953	962	}
954	963	case 0x0E:
955	964	{
956		state->m_col4bit[5] = data;
957		state->m_col3bit[5] = data;
958		state->m_col3bit[5 + 8] = data;
	965	m_col4bit[5] = data;
	966	m_col3bit[5] = data;
	967	m_col3bit[5 + 8] = data;
959	968	break;
960	969	}
961	970	case 0x0f:
962	971	{
963		state->m_col4bit[6] = data;
964		state->m_col3bit[6] = data;
965		state->m_col3bit[6 + 8] = data;
	972	m_col4bit[6] = data;
	973	m_col3bit[6] = data;
	974	m_col3bit[6 + 8] = data;
966	975	break;
967	976	}
968	977	case 0x18:
969	978	{
970		state->m_blitter.program.addr0 = data;
	979	m_blitter.program.addr0 = data;
971	980	break;
972	981	}
973	982	case 0x19:
974	983	{
975		state->m_blitter.program.addr1 = data;
	984	m_blitter.program.addr1 = data;
976	985	break;
977	986	}
978	987	case 0x1A:
979	988	{
980		state->m_blitter.program.addr2 = data;
	989	m_blitter.program.addr2 = data;
981	990	break;
982	991	}
983	992	case 0x20:
984	993	{
985		state->m_blitter.command = data;
	994	m_blitter.command = data;
986	995
987	996	if (data & CMD_RUN)
988		RunBlit(space);
	997	RunBlit(&space);
989	998	else
990	999	mame_printf_debug("Blitter stopped by IO.\n");
991	1000
r14845	r14846
993	1002	}
994	1003	case 0x22:
995	1004	{
996		state->m_flip_22 = data;
	1005	m_flip_22 = data;
997	1006	break;
998	1007	}
999	1008	default:
1000	1009	{
1001		mame_printf_debug("Flare One unknown write: 0x%.2x with 0x%.2x (PC:0x%.4x)\n", offset, data, cpu_get_previouspc(&space->device()));
	1010	mame_printf_debug("Flare One unknown write: 0x%.2x with 0x%.2x (PC:0x%.4x)\n", offset, data, cpu_get_previouspc(&space.device()));
1002	1011	}
1003	1012	}
1004	1013	}
r14845	r14846
1024	1033	}
1025	1034	}
1026	1035
1027		static WRITE8_HANDLER( rombank_w )
	1036	WRITE8_MEMBER(bfcobra_state::rombank_w)
1028	1037	{
1029		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
1030		state->m_bank_data[0] = data;
1031		z80_bank(space->machine(), 1, state->m_bank_data[1]);
1032		z80_bank(space->machine(), 2, state->m_bank_data[2]);
1033		z80_bank(space->machine(), 3, state->m_bank_data[3]);
	1038	m_bank_data[0] = data;
	1039	z80_bank(machine(), 1, m_bank_data[1]);
	1040	z80_bank(machine(), 2, m_bank_data[2]);
	1041	z80_bank(machine(), 3, m_bank_data[3]);
1034	1042	}
1035	1043
1036	1044
r14845	r14846
1088	1096	state->m_fdc.phase = COMMAND;
1089	1097	}
1090	1098
1091		static READ8_HANDLER( fdctrl_r )
	1099	READ8_MEMBER(bfcobra_state::fdctrl_r)
1092	1100	{
1093		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
1094	1101	UINT8 val = 0;
1095	1102
1096		val = state->m_fdc.MSR;
	1103	val = m_fdc.MSR;
1097	1104
1098	1105	return val;
1099	1106	}
1100	1107
1101		static READ8_HANDLER( fddata_r )
	1108	READ8_MEMBER(bfcobra_state::fddata_r)
1102	1109	{
1103		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
1104		struct fdc_t &fdc = state->m_fdc;
	1110	struct fdc_t &fdc = m_fdc;
1105	1111	#define   BPS      1024
1106	1112	#define SPT      10
1107	1113	#define BPT      1024*10
r14845	r14846
1130	1136	}
1131	1137
1132	1138	fdc.offset = (BPT * fdc.track*2) + (fdc.side ? BPT : 0) + (BPS * (fdc.sector-1)) + fdc.byte_pos++;
1133		val = *(space->machine().region("user2")->base() + fdc.offset);
	1139	val = *(machine().region("user2")->base() + fdc.offset);
1134	1140
1135	1141	/* Move on to next sector? */
1136	1142	if (fdc.byte_pos == 1024)
r14845	r14846
1172	1178	return val;
1173	1179	}
1174	1180
1175		static WRITE8_HANDLER( fdctrl_w )
	1181	WRITE8_MEMBER(bfcobra_state::fdctrl_w)
1176	1182	{
1177		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
1178		struct fdc_t &fdc = state->m_fdc;
	1183	struct fdc_t &fdc = m_fdc;
1179	1184	switch (fdc.phase)
1180	1185	{
1181	1186	case COMMAND:
r14845	r14846
1334	1339
1335	1340	static ADDRESS_MAP_START( z80_io_map, AS_IO, 8, bfcobra_state )
1336	1341	ADDRESS_MAP_GLOBAL_MASK(0xff)
1337		AM_RANGE(0x00, 0x23) AM_READWRITE_LEGACY(chipset_r, chipset_w)
	1342	AM_RANGE(0x00, 0x23) AM_READWRITE(chipset_r, chipset_w)
1338	1343	AM_RANGE(0x24, 0x24) AM_DEVWRITE("acia6850_0", acia6850_device, control_write)
1339	1344	AM_RANGE(0x25, 0x25) AM_DEVWRITE("acia6850_0", acia6850_device, data_write)
1340	1345	AM_RANGE(0x26, 0x26) AM_DEVREAD("acia6850_0", acia6850_device, status_read)
1341	1346	AM_RANGE(0x27, 0x27) AM_DEVREAD("acia6850_0", acia6850_device, data_read)
1342		AM_RANGE(0x30, 0x30) AM_READ_LEGACY(fdctrl_r)
1343		AM_RANGE(0x31, 0x31) AM_READWRITE_LEGACY(fddata_r, fdctrl_w)
1344		AM_RANGE(0x40, 0x40) AM_WRITE_LEGACY(rombank_w)
1345		AM_RANGE(0x50, 0x53) AM_READWRITE_LEGACY(ramdac_r, ramdac_w)
	1347	AM_RANGE(0x30, 0x30) AM_READ(fdctrl_r)
	1348	AM_RANGE(0x31, 0x31) AM_READWRITE(fddata_r, fdctrl_w)
	1349	AM_RANGE(0x40, 0x40) AM_WRITE(rombank_w)
	1350	AM_RANGE(0x50, 0x53) AM_READWRITE(ramdac_r, ramdac_w)
1346	1351	ADDRESS_MAP_END
1347	1352
1348	1353
r14845	r14846
1368	1373	***************************************************************************/
1369	1374
1370	1375	/* TODO */
1371		static READ8_HANDLER( int_latch_r )
	1376	READ8_MEMBER(bfcobra_state::int_latch_r)
1372	1377	{
1373	1378	return 2 | 1;
1374	1379	}
1375	1380
1376	1381	/* TODO */
1377		static READ8_HANDLER( meter_r )
	1382	READ8_MEMBER(bfcobra_state::meter_r)
1378	1383	{
1379		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
1380		return state->m_meter_latch;
	1384	return m_meter_latch;
1381	1385	}
1382	1386
1383	1387	/* TODO: This is borrowed from Scorpion 1 */
1384		static WRITE8_HANDLER( meter_w )
	1388	WRITE8_MEMBER(bfcobra_state::meter_w)
1385	1389	{
1386		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
1387	1390	int i;
1388		int  changed = state->m_meter_latch ^ data;
	1391	int  changed = m_meter_latch ^ data;
1389	1392
1390		state->m_meter_latch = data;
	1393	m_meter_latch = data;
1391	1394
1392	1395	/*
1393	1396	When a meter is triggered, the current drawn is sensed. If a meter
r14845	r14846
1398	1401	if (changed & (1 << i))
1399	1402	{
1400	1403	MechMtr_update(i, data & (1 << i) );
1401		generic_pulse_irq_line(&space->device(), M6809_FIRQ_LINE, 1);
	1404	generic_pulse_irq_line(&space.device(), M6809_FIRQ_LINE, 1);
1402	1405	}
1403	1406	}
1404	1407	}
1405	1408
1406	1409	/* TODO */
1407		static READ8_HANDLER( latch_r )
	1410	READ8_MEMBER(bfcobra_state::latch_r)
1408	1411	{
1409		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
1410		return state->m_mux_input;
	1412	return m_mux_input;
1411	1413	}
1412	1414
1413		static WRITE8_HANDLER( latch_w )
	1415	WRITE8_MEMBER(bfcobra_state::latch_w)
1414	1416	{
1415		bfcobra_state *state = space->machine().driver_data<bfcobra_state>();
1416	1417	/* TODO: This is borrowed from Scorpion 1 */
1417	1418	switch(offset)
1418	1419	{
1419	1420	case 0:
1420	1421	{
1421		int changed = state->m_mux_outputlatch ^ data;
	1422	int changed = m_mux_outputlatch ^ data;
1422	1423	static const char *const port[] = { "STROBE0", "STROBE1", "STROBE2", "STROBE3", "STROBE4", "STROBE5", "STROBE6", "STROBE7" };
1423	1424
1424		state->m_mux_outputlatch = data;
	1425	m_mux_outputlatch = data;
1425	1426
1426	1427	/* Clock has changed */
1427	1428	if (changed & 0x08)
r14845	r14846
1430	1431
1431	1432	/* Clock is low */
1432	1433	if (!(data & 0x08))
1433		state->m_mux_input = input_port_read(space->machine(), port[input_strobe]);
	1434	m_mux_input = input_port_read(machine(), port[input_strobe]);
1434	1435	}
1435	1436	break;
1436	1437	}
r14845	r14846
1463	1464	AM_RANGE(0x0000, 0x1fff) AM_RAM   AM_SHARE("nvram")
1464	1465	AM_RANGE(0x2000, 0x2000) AM_RAM      // W 'B', 6F
1465	1466	AM_RANGE(0x2200, 0x2200) AM_RAM      // W 'F'
1466		AM_RANGE(0x2600, 0x2600) AM_READWRITE_LEGACY(meter_r, meter_w)
	1467	AM_RANGE(0x2600, 0x2600) AM_READWRITE(meter_r, meter_w)
1467	1468	AM_RANGE(0x2800, 0x2800) AM_RAM      // W
1468		AM_RANGE(0x2A00, 0x2A02) AM_READWRITE_LEGACY(latch_r, latch_w)
1469		AM_RANGE(0x2E00, 0x2E00) AM_READ_LEGACY(int_latch_r)
	1469	AM_RANGE(0x2A00, 0x2A02) AM_READWRITE(latch_r, latch_w)
	1470	AM_RANGE(0x2E00, 0x2E00) AM_READ(int_latch_r)
1470	1471	AM_RANGE(0x3001, 0x3001) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
1471	1472	AM_RANGE(0x3201, 0x3201) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
1472	1473	AM_RANGE(0x3404, 0x3404) AM_DEVREADWRITE("acia6850_1", acia6850_device, status_read, control_write)

src/mame/drivers/sbugger.c

r14845	r14846
99	99
100	100	#include "emu.h"
101	101	#include "cpu/i8085/i8085.h"
	102	#include "machine/i8155.h"
102	103	#include "sound/sn76496.h"
103	104	#include "includes/sbugger.h"
104	105
105		//arbitrary
106		#define NUM_INTS_FRAME 24
107	106
108
109	107	/* memory maps */
110	108
111	109	static ADDRESS_MAP_START( sbugger_map, AS_PROGRAM, 8, sbugger_state )
112	110	AM_RANGE(0x0000, 0x37ff) AM_ROM
113	111	AM_RANGE(0xc800, 0xcbff) AM_RAM_WRITE_LEGACY(sbugger_videoram_attr_w) AM_BASE(m_videoram_attr)
114	112	AM_RANGE(0xcc00, 0xcfff) AM_RAM_WRITE_LEGACY(sbugger_videoram_w) AM_BASE(m_videoram)
115		AM_RANGE(0xe000, 0xe0ff) AM_RAM /* sp is set to e0ff */
	113	AM_RANGE(0xe000, 0xe0ff) AM_DEVREADWRITE("i8156", i8155_device, memory_r, memory_w) /* sp is set to e0ff */
116	114	AM_RANGE(0xf400, 0xffff) AM_RAM
117	115	ADDRESS_MAP_END
118	116
119	117	static ADDRESS_MAP_START( sbugger_io_map, AS_IO, 8, sbugger_state )
120		AM_RANGE(0xe0, 0xe0) AM_WRITENOP            // 8156 command/status reg (write c0 = command START = (start of timer)
121		AM_RANGE(0xe1, 0xe1) AM_READ_PORT("INPUTS")      // 8156 PA
122		AM_RANGE(0xe2, 0xe2) AM_READ_PORT("DSW1")      // 8156 PB
123		AM_RANGE(0xe3, 0xe3) AM_READ_PORT("DSW2")      // 8156 PC = 6 bit ! //2 bits tested af f4c6
124		AM_RANGE(0xe4, 0xe4) AM_WRITENOP            // 8156 timer reg1 (write 7f = CNT length)
125		AM_RANGE(0xe5, 0xe5) AM_WRITENOP            // 8156 timer reg2 (write c0 = timer mode - automatic reload, i.e. single pulse every time TC is reached)
126
	118	AM_RANGE(0xe0, 0xe7) AM_DEVREADWRITE("i8156", i8155_device, io_r, io_w)
127	119	AM_RANGE(0xe8, 0xe8) AM_DEVWRITE_LEGACY("sn76489.1", sn76496_w)
128	120	AM_RANGE(0xe9, 0xe9) AM_DEVWRITE_LEGACY("sn76489.2", sn76496_w)
129	121	ADDRESS_MAP_END
130	122
	123
131	124	/* gfx decode */
132	125
133	126	static const gfx_layout char16layout =
r14845	r14846
147	140	GFXDECODE_ENTRY( "gfx1", 0, char16layout,   0, 1  )
148	141	GFXDECODE_END
149	142
	143
150	144	/* input ports */
151	145
152	146	static INPUT_PORTS_START( sbugger )
r14845	r14846
209	203	PORT_BIT( 0xc0, IP_ACTIVE_HIGH, IPT_UNUSED )
210	204	INPUT_PORTS_END
211	205
	206
212	207	/* machine driver */
213	208
	209	static WRITE_LINE_DEVICE_HANDLER(sbugger_interrupt)
	210	{
	211	cputag_set_input_line(device->machine(), "maincpu", I8085_RST75_LINE, state ? CLEAR_LINE : ASSERT_LINE );
	212	}
	213
	214	static I8156_INTERFACE(i8156_intf)
	215	{
	216	// all ports set to input
	217	DEVCB_INPUT_PORT("INPUTS"),
	218	DEVCB_NULL,
	219	DEVCB_INPUT_PORT("DSW1"),
	220	DEVCB_NULL,
	221	DEVCB_INPUT_PORT("DSW2"),
	222	DEVCB_NULL,
	223	DEVCB_LINE(sbugger_interrupt)
	224	};
	225
214	226	static MACHINE_CONFIG_START( sbugger, sbugger_state )
215	227
216	228	MCFG_CPU_ADD("maincpu", I8085A, 6000000)        /* 3.00 MHz??? */
217	229	MCFG_CPU_PROGRAM_MAP(sbugger_map)
218	230	MCFG_CPU_IO_MAP(sbugger_io_map)
219		MCFG_CPU_PERIODIC_INT(irq3_line_hold,NUM_INTS_FRAME*60)
	231	MCFG_I8156_ADD("i8156", 200000, i8156_intf)      /* freq is an approximation */
220	232
221	233	MCFG_GFXDECODE(sbugger)
222	234
223
224	235	MCFG_SCREEN_ADD("screen", RASTER)
225	236	MCFG_SCREEN_REFRESH_RATE(60)
226	237	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
r14845	r14846
244	255
245	256	MACHINE_CONFIG_END
246	257
	258
247	259	/* rom loading */
248	260
249	261	ROM_START( sbugger )
r14845	r14846
275	287	ROM_LOAD( "spbugger.gfx", 0x0000, 0x1000, CRC(d3f345b5) SHA1(a5082ffc3043352e9b731af95770bdd62fb928bf) )
276	288	ROM_END
277	289
278		GAME( 1981, sbugger,  0,        sbugger,  sbugger,  0, ROT270, "Game-A-Tron", "Space Bugger (set 1)", GAME_NOT_WORKING )
	290	GAME( 1981, sbugger,  0,        sbugger,  sbugger,  0, ROT270, "Game-A-Tron", "Space Bugger (set 1)", GAME_NOT_WORKING | GAME_IMPERFECT_COLORS )
279	291	GAME( 1981, sbuggera, sbugger,  sbugger,  sbugger,  0, ROT270, "Game-A-Tron", "Space Bugger (set 2)", GAME_IMPERFECT_COLORS )

src/mame/drivers/mgolf.c

r14845	r14846
27	27
28	28	/* devices */
29	29	device_t *m_maincpu;
	30	DECLARE_WRITE8_MEMBER(mgolf_vram_w);
	31	DECLARE_READ8_MEMBER(mgolf_wram_r);
	32	DECLARE_READ8_MEMBER(mgolf_dial_r);
	33	DECLARE_READ8_MEMBER(mgolf_misc_r);
	34	DECLARE_WRITE8_MEMBER(mgolf_wram_w);
30	35	};
31	36
32	37
r14845	r14846
39	44	}
40	45
41	46
42		static WRITE8_HANDLER( mgolf_vram_w )
	47	WRITE8_MEMBER(mgolf_state::mgolf_vram_w)
43	48	{
44		mgolf_state *state = space->machine().driver_data<mgolf_state>();
45		state->m_video_ram[offset] = data;
46		state->m_bg_tilemap->mark_tile_dirty(offset);
	49	m_video_ram[offset] = data;
	50	m_bg_tilemap->mark_tile_dirty(offset);
47	51	}
48	52
49	53
r14845	r14846
130	134	}
131	135
132	136
133		static READ8_HANDLER( mgolf_wram_r )
	137	READ8_MEMBER(mgolf_state::mgolf_wram_r)
134	138	{
135		mgolf_state *state = space->machine().driver_data<mgolf_state>();
136		return state->m_video_ram[0x380 + offset];
	139	return m_video_ram[0x380 + offset];
137	140	}
138	141
139	142
140		static READ8_HANDLER( mgolf_dial_r )
	143	READ8_MEMBER(mgolf_state::mgolf_dial_r)
141	144	{
142		UINT8 val = input_port_read(space->machine(), "41");
	145	UINT8 val = input_port_read(machine(), "41");
143	146
144		if ((input_port_read(space->machine(), "DIAL") + 0x00) & 0x20)
	147	if ((input_port_read(machine(), "DIAL") + 0x00) & 0x20)
145	148	{
146	149	val |= 0x01;
147	150	}
148		if ((input_port_read(space->machine(), "DIAL") + 0x10) & 0x20)
	151	if ((input_port_read(machine(), "DIAL") + 0x10) & 0x20)
149	152	{
150	153	val |= 0x02;
151	154	}
r14845	r14846
154	157	}
155	158
156	159
157		static READ8_HANDLER( mgolf_misc_r )
	160	READ8_MEMBER(mgolf_state::mgolf_misc_r)
158	161	{
159		double plunger = calc_plunger_pos(space->machine()); /* see Video Pinball */
	162	double plunger = calc_plunger_pos(machine()); /* see Video Pinball */
160	163
161		UINT8 val = input_port_read(space->machine(), "61");
	164	UINT8 val = input_port_read(machine(), "61");
162	165
163	166	if (plunger >= 0.000 && plunger <= 0.001)
164	167	{
r14845	r14846
173	176	}
174	177
175	178
176		static WRITE8_HANDLER( mgolf_wram_w )
	179	WRITE8_MEMBER(mgolf_state::mgolf_wram_w)
177	180	{
178		mgolf_state *state = space->machine().driver_data<mgolf_state>();
179		state->m_video_ram[0x380 + offset] = data;
	181	m_video_ram[0x380 + offset] = data;
180	182	}
181	183
182	184
r14845	r14846
185	187	ADDRESS_MAP_GLOBAL_MASK(0x3fff)
186	188
187	189	AM_RANGE(0x0040, 0x0040) AM_READ_PORT("40")
188		AM_RANGE(0x0041, 0x0041) AM_READ_LEGACY(mgolf_dial_r)
	190	AM_RANGE(0x0041, 0x0041) AM_READ(mgolf_dial_r)
189	191	AM_RANGE(0x0060, 0x0060) AM_READ_PORT("60")
190		AM_RANGE(0x0061, 0x0061) AM_READ_LEGACY(mgolf_misc_r)
191		AM_RANGE(0x0080, 0x00ff) AM_READ_LEGACY(mgolf_wram_r)
192		AM_RANGE(0x0180, 0x01ff) AM_READ_LEGACY(mgolf_wram_r)
	192	AM_RANGE(0x0061, 0x0061) AM_READ(mgolf_misc_r)
	193	AM_RANGE(0x0080, 0x00ff) AM_READ(mgolf_wram_r)
	194	AM_RANGE(0x0180, 0x01ff) AM_READ(mgolf_wram_r)
193	195	AM_RANGE(0x0800, 0x0bff) AM_READONLY
194	196
195	197	AM_RANGE(0x0000, 0x0009) AM_WRITENOP
r14845	r14846
203	205	AM_RANGE(0x006a, 0x006a) AM_WRITENOP
204	206	AM_RANGE(0x006c, 0x006c) AM_WRITENOP
205	207	AM_RANGE(0x006d, 0x006d) AM_WRITENOP
206		AM_RANGE(0x0080, 0x00ff) AM_WRITE_LEGACY(mgolf_wram_w)
207		AM_RANGE(0x0180, 0x01ff) AM_WRITE_LEGACY(mgolf_wram_w)
208		AM_RANGE(0x0800, 0x0bff) AM_WRITE_LEGACY(mgolf_vram_w) AM_BASE(m_video_ram)
	208	AM_RANGE(0x0080, 0x00ff) AM_WRITE(mgolf_wram_w)
	209	AM_RANGE(0x0180, 0x01ff) AM_WRITE(mgolf_wram_w)
	210	AM_RANGE(0x0800, 0x0bff) AM_WRITE(mgolf_vram_w) AM_BASE(m_video_ram)
209	211
210	212	AM_RANGE(0x2000, 0x3fff) AM_ROM
211	213	ADDRESS_MAP_END

src/mame/drivers/pasha2.c

r14845	r14846
93	93	/* memory */
94	94	UINT16       m_bitmap0[0x40000/2];
95	95	UINT16       m_bitmap1[0x40000/2];
	96	DECLARE_WRITE16_MEMBER(pasha2_misc_w);
	97	DECLARE_WRITE16_MEMBER(pasha2_palette_w);
	98	DECLARE_WRITE16_MEMBER(vbuffer_set_w);
	99	DECLARE_WRITE16_MEMBER(vbuffer_clear_w);
	100	DECLARE_WRITE16_MEMBER(bitmap_0_w);
	101	DECLARE_WRITE16_MEMBER(bitmap_1_w);
	102	DECLARE_WRITE16_MEMBER(pasha2_lamps_w);
	103	DECLARE_READ16_MEMBER(pasha2_speedup_r);
96	104	};
97	105
98	106
99		static WRITE16_HANDLER( pasha2_misc_w )
	107	WRITE16_MEMBER(pasha2_state::pasha2_misc_w)
100	108	{
101		pasha2_state *state = space->machine().driver_data<pasha2_state>();
102	109
103	110	if (offset)
104	111	{
r14845	r14846
106	113	{
107	114	int bank = data & 0xf000;
108	115
109		if (bank != state->m_old_bank)
	116	if (bank != m_old_bank)
110	117	{
111		state->m_old_bank = bank;
	118	m_old_bank = bank;
112	119
113	120	switch (bank)
114	121	{
r14845	r14846
118	125	case 0xb000:
119	126	case 0xc000:
120	127	case 0xd000:
121		memory_set_bankptr(space->machine(), "bank1", space->machine().region("user2")->base() + 0x400 * (bank - 0x8000)); break;
	128	memory_set_bankptr(machine(), "bank1", machine().region("user2")->base() + 0x400 * (bank - 0x8000)); break;
122	129	}
123	130	}
124	131	}
125	132	}
126	133	}
127	134
128		static WRITE16_HANDLER( pasha2_palette_w )
	135	WRITE16_MEMBER(pasha2_state::pasha2_palette_w)
129	136	{
130		pasha2_state *state = space->machine().driver_data<pasha2_state>();
131	137	int color;
132	138
133		COMBINE_DATA(&state->m_paletteram[offset]);
	139	COMBINE_DATA(&m_paletteram[offset]);
134	140
135	141	offset &= 0xff;
136	142
137		color = (state->m_paletteram[offset] >> 8) | (state->m_paletteram[offset + 0x100] & 0xff00);
138		palette_set_color_rgb(space->machine(), offset * 2 + 0, pal5bit(color), pal5bit(color >> 5), pal5bit(color >> 10));
	143	color = (m_paletteram[offset] >> 8) | (m_paletteram[offset + 0x100] & 0xff00);
	144	palette_set_color_rgb(machine(), offset * 2 + 0, pal5bit(color), pal5bit(color >> 5), pal5bit(color >> 10));
139	145
140		color = (state->m_paletteram[offset] & 0xff) | ((state->m_paletteram[offset + 0x100] & 0xff) << 8);
141		palette_set_color_rgb(space->machine(), offset * 2 + 1, pal5bit(color), pal5bit(color >> 5), pal5bit(color >> 10));
	146	color = (m_paletteram[offset] & 0xff) | ((m_paletteram[offset + 0x100] & 0xff) << 8);
	147	palette_set_color_rgb(machine(), offset * 2 + 1, pal5bit(color), pal5bit(color >> 5), pal5bit(color >> 10));
142	148	}
143	149
144		static WRITE16_HANDLER( vbuffer_set_w )
	150	WRITE16_MEMBER(pasha2_state::vbuffer_set_w)
145	151	{
146		pasha2_state *state = space->machine().driver_data<pasha2_state>();
147		state->m_vbuffer = 1;
	152	m_vbuffer = 1;
148	153	}
149	154
150		static WRITE16_HANDLER( vbuffer_clear_w )
	155	WRITE16_MEMBER(pasha2_state::vbuffer_clear_w)
151	156	{
152		pasha2_state *state = space->machine().driver_data<pasha2_state>();
153		state->m_vbuffer = 0;
	157	m_vbuffer = 0;
154	158	}
155	159
156		static WRITE16_HANDLER( bitmap_0_w )
	160	WRITE16_MEMBER(pasha2_state::bitmap_0_w)
157	161	{
158		pasha2_state *state = space->machine().driver_data<pasha2_state>();
159		COMBINE_DATA(&state->m_bitmap0[offset + state->m_vbuffer * 0x20000 / 2]);
	162	COMBINE_DATA(&m_bitmap0[offset + m_vbuffer * 0x20000 / 2]);
160	163	}
161	164
162		static WRITE16_HANDLER( bitmap_1_w )
	165	WRITE16_MEMBER(pasha2_state::bitmap_1_w)
163	166	{
164		pasha2_state *state = space->machine().driver_data<pasha2_state>();
165	167
166	168	// handle overlapping pixels without writing them
167	169	switch (mem_mask)
r14845	r14846
182	184	break;
183	185	}
184	186
185		COMBINE_DATA(&state->m_bitmap1[offset + state->m_vbuffer * 0x20000 / 2]);
	187	COMBINE_DATA(&m_bitmap1[offset + m_vbuffer * 0x20000 / 2]);
186	188	}
187	189
188	190	static WRITE16_DEVICE_HANDLER( oki_bank_w )
r14845	r14846
191	193	downcast<okim6295_device *>(device)->set_bank_base((data & 1) * 0x40000);
192	194	}
193	195
194		static WRITE16_HANDLER( pasha2_lamps_w )
	196	WRITE16_MEMBER(pasha2_state::pasha2_lamps_w)
195	197	{
196	198	if (data)
197	199	popmessage("1P: %c%c%c 2P: %c%c%c 3P: %c%c%c",
r14845	r14846
208	210
209	211	static ADDRESS_MAP_START( pasha2_map, AS_PROGRAM, 16, pasha2_state )
210	212	AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_BASE(m_wram)
211		AM_RANGE(0x40000000, 0x4001ffff) AM_RAM_WRITE_LEGACY(bitmap_0_w)
212		AM_RANGE(0x40020000, 0x4003ffff) AM_RAM_WRITE_LEGACY(bitmap_1_w)
	213	AM_RANGE(0x40000000, 0x4001ffff) AM_RAM_WRITE(bitmap_0_w)
	214	AM_RANGE(0x40020000, 0x4003ffff) AM_RAM_WRITE(bitmap_1_w)
213	215	AM_RANGE(0x40060000, 0x40060001) AM_WRITENOP
214	216	AM_RANGE(0x40064000, 0x40064001) AM_WRITENOP
215	217	AM_RANGE(0x40068000, 0x40068001) AM_WRITENOP
216	218	AM_RANGE(0x4006c000, 0x4006c001) AM_WRITENOP
217		AM_RANGE(0x40070000, 0x40070001) AM_WRITE_LEGACY(vbuffer_clear_w)
218		AM_RANGE(0x40074000, 0x40074001) AM_WRITE_LEGACY(vbuffer_set_w)
	219	AM_RANGE(0x40070000, 0x40070001) AM_WRITE(vbuffer_clear_w)
	220	AM_RANGE(0x40074000, 0x40074001) AM_WRITE(vbuffer_set_w)
219	221	AM_RANGE(0x40078000, 0x40078001) AM_WRITENOP //once at startup -> to disable the eeprom?
220	222	AM_RANGE(0x80000000, 0x803fffff) AM_ROMBANK("bank1")
221		AM_RANGE(0xe0000000, 0xe00003ff) AM_RAM_WRITE_LEGACY(pasha2_palette_w) AM_BASE(m_paletteram) //tilemap? palette?
	223	AM_RANGE(0xe0000000, 0xe00003ff) AM_RAM_WRITE(pasha2_palette_w) AM_BASE(m_paletteram) //tilemap? palette?
222	224	AM_RANGE(0xfff80000, 0xffffffff) AM_ROM AM_REGION("user1",0)
223	225	ADDRESS_MAP_END
224	226
225	227	static ADDRESS_MAP_START( pasha2_io, AS_IO, 16, pasha2_state )
226	228	AM_RANGE(0x08, 0x0b) AM_READNOP //sound status?
227	229	AM_RANGE(0x18, 0x1b) AM_READNOP //sound status?
228		AM_RANGE(0x20, 0x23) AM_WRITE_LEGACY(pasha2_lamps_w)
	230	AM_RANGE(0x20, 0x23) AM_WRITE(pasha2_lamps_w)
229	231	AM_RANGE(0x40, 0x43) AM_READ_PORT("COINS")
230	232	AM_RANGE(0x60, 0x63) AM_READ_PORT("DSW")
231	233	AM_RANGE(0x80, 0x83) AM_READ_PORT("INPUTS")
232	234	AM_RANGE(0xa0, 0xa3) AM_WRITENOP //soundlatch?
233		AM_RANGE(0xc0, 0xc3) AM_WRITE_LEGACY(pasha2_misc_w)
	235	AM_RANGE(0xc0, 0xc3) AM_WRITE(pasha2_misc_w)
234	236	AM_RANGE(0xe2, 0xe3) AM_DEVREADWRITE8("oki1", okim6295_device, read, write, 0x00ff)
235	237	AM_RANGE(0xe6, 0xe7) AM_DEVREADWRITE8("oki2", okim6295_device, read, write, 0x00ff)
236	238	AM_RANGE(0xe8, 0xeb) AM_DEVWRITE_LEGACY("oki1", oki_bank_w)
r14845	r14846
458	460	ROM_LOAD( "pp2.um53",     0x00000, 0x80000, CRC(8a29ad03) SHA1(3e9b0c86d8e3bb0b7691f68ad45431f6f9e8edbd) )
459	461	ROM_END
460	462
461		static READ16_HANDLER( pasha2_speedup_r )
	463	READ16_MEMBER(pasha2_state::pasha2_speedup_r)
462	464	{
463		pasha2_state *state = space->machine().driver_data<pasha2_state>();
464	465
465		if(cpu_get_pc(&space->device()) == 0x8302)
466		device_spin_until_interrupt(&space->device());
	466	if(cpu_get_pc(&space.device()) == 0x8302)
	467	device_spin_until_interrupt(&space.device());
467	468
468		return state->m_wram[(0x95744 / 2) + offset];
	469	return m_wram[(0x95744 / 2) + offset];
469	470	}
470	471
471	472	static DRIVER_INIT( pasha2 )
472	473	{
473		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x95744, 0x95747, FUNC(pasha2_speedup_r) );
	474	pasha2_state *state = machine.driver_data<pasha2_state>();
	475	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x95744, 0x95747, read16_delegate(FUNC(pasha2_state::pasha2_speedup_r), state));
474	476
475	477	memory_set_bankptr(machine, "bank1", machine.region("user2")->base());
476	478	}

src/mame/drivers/coinmstr.c

r14845	r14846
41	41	UINT8 *m_attr_ram3;
42	42	tilemap_t *m_bg_tilemap;
43	43	UINT8 m_question_adr[4];
	44	DECLARE_WRITE8_MEMBER(quizmstr_bg_w);
	45	DECLARE_WRITE8_MEMBER(quizmstr_attr1_w);
	46	DECLARE_WRITE8_MEMBER(quizmstr_attr2_w);
	47	DECLARE_WRITE8_MEMBER(quizmstr_attr3_w);
	48	DECLARE_READ8_MEMBER(question_r);
	49	DECLARE_WRITE8_MEMBER(question_w);
	50	DECLARE_READ8_MEMBER(ff_r);
44	51	};
45	52
46	53
47		static WRITE8_HANDLER( quizmstr_bg_w )
	54	WRITE8_MEMBER(coinmstr_state::quizmstr_bg_w)
48	55	{
49		coinmstr_state *state = space->machine().driver_data<coinmstr_state>();
50		UINT8 *videoram = state->m_videoram;
	56	UINT8 *videoram = m_videoram;
51	57	videoram[offset] = data;
52	58
53	59	if(offset >= 0x0240)
54		state->m_bg_tilemap->mark_tile_dirty(offset - 0x0240);
	60	m_bg_tilemap->mark_tile_dirty(offset - 0x0240);
55	61	}
56	62
57	63
r14845	r14846
88	94	}
89	95
90	96
91		static WRITE8_HANDLER( quizmstr_attr1_w )
	97	WRITE8_MEMBER(coinmstr_state::quizmstr_attr1_w)
92	98	{
93		coinmstr_state *state = space->machine().driver_data<coinmstr_state>();
94		state->m_attr_ram1[offset] = data;
	99	m_attr_ram1[offset] = data;
95	100
96	101	if(offset >= 0x0240)
97	102	{
98	103	// the later games also use attr3 for something..
99		UINT32   paldata = (state->m_attr_ram1[offset] & 0x7f) | ((state->m_attr_ram2[offset] & 0x7f) << 7);
100		state->m_bg_tilemap->mark_tile_dirty(offset - 0x0240);
	104	UINT32   paldata = (m_attr_ram1[offset] & 0x7f) | ((m_attr_ram2[offset] & 0x7f) << 7);
	105	m_bg_tilemap->mark_tile_dirty(offset - 0x0240);
101	106
102		coinmstr_set_pal(space->machine(), paldata, offset - 0x240);
	107	coinmstr_set_pal(machine(), paldata, offset - 0x240);
103	108
104	109	}
105	110	}
106	111
107		static WRITE8_HANDLER( quizmstr_attr2_w )
	112	WRITE8_MEMBER(coinmstr_state::quizmstr_attr2_w)
108	113	{
109		coinmstr_state *state = space->machine().driver_data<coinmstr_state>();
110		state->m_attr_ram2[offset] = data;
	114	m_attr_ram2[offset] = data;
111	115
112	116	if(offset >= 0x0240)
113	117	{
114	118	// the later games also use attr3 for something..
115		UINT32   paldata = (state->m_attr_ram1[offset] & 0x7f) | ((state->m_attr_ram2[offset] & 0x7f) << 7);
116		state->m_bg_tilemap->mark_tile_dirty(offset - 0x0240);
	119	UINT32   paldata = (m_attr_ram1[offset] & 0x7f) | ((m_attr_ram2[offset] & 0x7f) << 7);
	120	m_bg_tilemap->mark_tile_dirty(offset - 0x0240);
117	121
118		coinmstr_set_pal(space->machine(), paldata, offset - 0x240);
	122	coinmstr_set_pal(machine(), paldata, offset - 0x240);
119	123
120	124	}
121	125	}
122	126
123		static WRITE8_HANDLER( quizmstr_attr3_w )
	127	WRITE8_MEMBER(coinmstr_state::quizmstr_attr3_w)
124	128	{
125		coinmstr_state *state = space->machine().driver_data<coinmstr_state>();
126		state->m_attr_ram3[offset] = data;
	129	m_attr_ram3[offset] = data;
127	130
128	131	if(offset >= 0x0240)
129		state->m_bg_tilemap->mark_tile_dirty(offset - 0x0240);
	132	m_bg_tilemap->mark_tile_dirty(offset - 0x0240);
130	133
131	134	}
132	135
133	136
134		static READ8_HANDLER( question_r )
	137	READ8_MEMBER(coinmstr_state::question_r)
135	138	{
136		coinmstr_state *state = space->machine().driver_data<coinmstr_state>();
137	139	int address;
138		UINT8 *questions = space->machine().region("user1")->base();
	140	UINT8 *questions = machine().region("user1")->base();
139	141
140		switch(state->m_question_adr[2])
	142	switch(m_question_adr[2])
141	143	{
142		case 0x38: address = 0x00000; break; // state->m_question_adr[3] == 7
143		case 0x39: address = 0x08000; break; // state->m_question_adr[3] == 7
144		case 0x3a: address = 0x10000; break; // state->m_question_adr[3] == 7
145		case 0x3b: address = 0x18000; break; // state->m_question_adr[3] == 7
146		case 0x3c: address = 0x20000; break; // state->m_question_adr[3] == 7
147		case 0x3d: address = 0x28000; break; // state->m_question_adr[3] == 7
148		case 0x3e: address = 0x30000; break; // state->m_question_adr[3] == 7
149		case 0x07: address = 0x38000; break; // state->m_question_adr[3] == 7
150		case 0x0f: address = 0x40000; break; // state->m_question_adr[3] == 7
151		case 0x17: address = 0x48000; break; // state->m_question_adr[3] == 7
152		case 0x1f: address = 0x50000; break; // state->m_question_adr[3] == 7
153		case 0x27: address = 0x58000; break; // state->m_question_adr[3] == 7
154		case 0x2f: address = 0x60000; break; // state->m_question_adr[3] == 7
155		case 0x37: address = 0x68000; break; // state->m_question_adr[3] == 7
156		case 0x3f: address = 0x70000 + state->m_question_adr[3] * 0x8000; break;
	144	case 0x38: address = 0x00000; break; // m_question_adr[3] == 7
	145	case 0x39: address = 0x08000; break; // m_question_adr[3] == 7
	146	case 0x3a: address = 0x10000; break; // m_question_adr[3] == 7
	147	case 0x3b: address = 0x18000; break; // m_question_adr[3] == 7
	148	case 0x3c: address = 0x20000; break; // m_question_adr[3] == 7
	149	case 0x3d: address = 0x28000; break; // m_question_adr[3] == 7
	150	case 0x3e: address = 0x30000; break; // m_question_adr[3] == 7
	151	case 0x07: address = 0x38000; break; // m_question_adr[3] == 7
	152	case 0x0f: address = 0x40000; break; // m_question_adr[3] == 7
	153	case 0x17: address = 0x48000; break; // m_question_adr[3] == 7
	154	case 0x1f: address = 0x50000; break; // m_question_adr[3] == 7
	155	case 0x27: address = 0x58000; break; // m_question_adr[3] == 7
	156	case 0x2f: address = 0x60000; break; // m_question_adr[3] == 7
	157	case 0x37: address = 0x68000; break; // m_question_adr[3] == 7
	158	case 0x3f: address = 0x70000 + m_question_adr[3] * 0x8000; break;
157	159
158	160	default:
159	161	address = 0;
160		logerror("unknown question rom # = %02X\n",state->m_question_adr[2]);
	162	logerror("unknown question rom # = %02X\n",m_question_adr[2]);
161	163	}
162	164
163		if(state->m_question_adr[3] == 6 || state->m_question_adr[3] > 7)
164		logerror("question_adr[3] = %02X\n",state->m_question_adr[3]);
	165	if(m_question_adr[3] == 6 || m_question_adr[3] > 7)
	166	logerror("question_adr[3] = %02X\n",m_question_adr[3]);
165	167
166	168	/*
167	169	in these offsets they set 0x80... why?
168	170
169		if( (state->m_question_adr[0] & 0x5f) == 0x00 ||
170		(state->m_question_adr[0] & 0x5f) == 0x01 ||
171		(state->m_question_adr[0] & 0x5f) == 0x0f ||
172		(state->m_question_adr[0] & 0x5f) == 0x56 )
	171	if( (m_question_adr[0] & 0x5f) == 0x00 ||
	172	(m_question_adr[0] & 0x5f) == 0x01 ||
	173	(m_question_adr[0] & 0x5f) == 0x0f ||
	174	(m_question_adr[0] & 0x5f) == 0x56 )
173	175	*/
174	176
175	177
176	178	//  don't know...
177		//  address |= ((state->m_question_adr[0] & 0x7f) << 8) | state->m_question_adr[1];
178		address |= (state->m_question_adr[1] << 7) | (state->m_question_adr[0] & 0x7f);
	179	//  address |= ((m_question_adr[0] & 0x7f) << 8) | m_question_adr[1];
	180	address |= (m_question_adr[1] << 7) | (m_question_adr[0] & 0x7f);
179	181
180	182	return questions[address];
181	183	}
182	184
183		static WRITE8_HANDLER( question_w )
	185	WRITE8_MEMBER(coinmstr_state::question_w)
184	186	{
185		coinmstr_state *state = space->machine().driver_data<coinmstr_state>();
186		if(data != state->m_question_adr[offset])
	187	if(data != m_question_adr[offset])
187	188	{
188	189	logerror("offset = %d data = %02X\n",offset,data);
189	190	}
190	191
191		state->m_question_adr[offset] = data;
	192	m_question_adr[offset] = data;
192	193	}
193	194
194		static READ8_HANDLER( ff_r )
	195	READ8_MEMBER(coinmstr_state::ff_r)
195	196	{
196	197	return 0xff;
197	198	}
r14845	r14846
201	202	static ADDRESS_MAP_START( coinmstr_map, AS_PROGRAM, 8, coinmstr_state )
202	203	AM_RANGE(0x0000, 0xbfff) AM_ROM
203	204	AM_RANGE(0xc000, 0xdfff) AM_RAM
204		AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE_LEGACY(quizmstr_bg_w) AM_BASE(m_videoram)
205		AM_RANGE(0xe800, 0xefff) AM_RAM_WRITE_LEGACY(quizmstr_attr1_w) AM_BASE(m_attr_ram1)
206		AM_RANGE(0xf000, 0xf7ff) AM_RAM_WRITE_LEGACY(quizmstr_attr2_w) AM_BASE(m_attr_ram2)
207		AM_RANGE(0xf800, 0xffff) AM_RAM_WRITE_LEGACY(quizmstr_attr3_w) AM_BASE(m_attr_ram3)
	205	AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE(quizmstr_bg_w) AM_BASE(m_videoram)
	206	AM_RANGE(0xe800, 0xefff) AM_RAM_WRITE(quizmstr_attr1_w) AM_BASE(m_attr_ram1)
	207	AM_RANGE(0xf000, 0xf7ff) AM_RAM_WRITE(quizmstr_attr2_w) AM_BASE(m_attr_ram2)
	208	AM_RANGE(0xf800, 0xffff) AM_RAM_WRITE(quizmstr_attr3_w) AM_BASE(m_attr_ram3)
208	209	ADDRESS_MAP_END
209	210
210	211	// Different I/O mappping for every game
r14845	r14846
212	213	static ADDRESS_MAP_START( quizmstr_io_map, AS_IO, 8, coinmstr_state )
213	214	ADDRESS_MAP_UNMAP_HIGH
214	215	ADDRESS_MAP_GLOBAL_MASK(0xff)
215		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(question_r)
216		AM_RANGE(0x00, 0x03) AM_WRITE_LEGACY(question_w)
	216	AM_RANGE(0x00, 0x00) AM_READ(question_r)
	217	AM_RANGE(0x00, 0x03) AM_WRITE(question_w)
217	218	AM_RANGE(0x40, 0x41) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
218	219	AM_RANGE(0x41, 0x41) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
219	220	AM_RANGE(0x48, 0x4b) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
r14845	r14846
228	229
229	230	static ADDRESS_MAP_START( trailblz_io_map, AS_IO, 8, coinmstr_state )
230	231	ADDRESS_MAP_GLOBAL_MASK(0xff)
231		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(question_r)
232		AM_RANGE(0x00, 0x03) AM_WRITE_LEGACY(question_w)
	232	AM_RANGE(0x00, 0x00) AM_READ(question_r)
	233	AM_RANGE(0x00, 0x03) AM_WRITE(question_w)
233	234	AM_RANGE(0x40, 0x40) AM_DEVWRITE("crtc", mc6845_device, address_w)
234	235	AM_RANGE(0x41, 0x41) AM_DEVWRITE("crtc", mc6845_device, register_w)
235	236	AM_RANGE(0x48, 0x49) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
r14845	r14846
243	244	static ADDRESS_MAP_START( supnudg2_io_map, AS_IO, 8, coinmstr_state )
244	245	ADDRESS_MAP_UNMAP_HIGH
245	246	ADDRESS_MAP_GLOBAL_MASK(0xff)
246		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(question_r)
247		AM_RANGE(0x00, 0x03) AM_WRITE_LEGACY(question_w)
	247	AM_RANGE(0x00, 0x00) AM_READ(question_r)
	248	AM_RANGE(0x00, 0x03) AM_WRITE(question_w)
248	249	AM_RANGE(0x40, 0x41) AM_READNOP
249	250	AM_RANGE(0x40, 0x43) AM_WRITENOP
250	251	AM_RANGE(0x43, 0x43) AM_READNOP
r14845	r14846
271	272	AM_RANGE(0x58, 0x5b) AM_DEVREADWRITE("pia0", pia6821_device, read, write) /* confirmed */
272	273	AM_RANGE(0x68, 0x6b) AM_DEVREADWRITE("pia1", pia6821_device, read, write) /* confirmed */
273	274	AM_RANGE(0x78, 0x7b) AM_DEVREADWRITE("pia2", pia6821_device, read, write) /* confirmed */
274		AM_RANGE(0xc0, 0xc1) AM_READ_LEGACY(ff_r)   /* needed to boot */
	275	AM_RANGE(0xc0, 0xc1) AM_READ(ff_r)   /* needed to boot */
275	276	ADDRESS_MAP_END
276	277
277	278

src/mame/drivers/magicard.c

r14845	r14846
184	184	UINT16 *m_scc68070_dma_ch2_regs;
185	185	UINT16 *m_scc68070_mmu_regs;
186	186	struct { int r,g,b,offs,offs_internal; } m_pal;
	187	DECLARE_READ16_MEMBER(test_r);
	188	DECLARE_WRITE16_MEMBER(paletteram_io_w);
	189	DECLARE_READ16_MEMBER(philips_66470_r);
	190	DECLARE_WRITE16_MEMBER(philips_66470_w);
	191	DECLARE_READ16_MEMBER(scc68070_ext_irqc_r);
	192	DECLARE_WRITE16_MEMBER(scc68070_ext_irqc_w);
	193	DECLARE_READ16_MEMBER(scc68070_iic_r);
	194	DECLARE_WRITE16_MEMBER(scc68070_iic_w);
	195	DECLARE_READ16_MEMBER(scc68070_uart_r);
	196	DECLARE_WRITE16_MEMBER(scc68070_uart_w);
	197	DECLARE_READ16_MEMBER(scc68070_timer_r);
	198	DECLARE_WRITE16_MEMBER(scc68070_timer_w);
	199	DECLARE_READ16_MEMBER(scc68070_int_irqc_r);
	200	DECLARE_WRITE16_MEMBER(scc68070_int_irqc_w);
	201	DECLARE_READ16_MEMBER(scc68070_dma_ch1_r);
	202	DECLARE_WRITE16_MEMBER(scc68070_dma_ch1_w);
	203	DECLARE_READ16_MEMBER(scc68070_dma_ch2_r);
	204	DECLARE_WRITE16_MEMBER(scc68070_dma_ch2_w);
	205	DECLARE_READ16_MEMBER(scc68070_mmu_r);
	206	DECLARE_WRITE16_MEMBER(scc68070_mmu_w);
187	207	};
188	208
189	209
r14845	r14846
455	475	*      R/W Handlers      *
456	476	*************************/
457	477
458		static READ16_HANDLER( test_r )
	478	READ16_MEMBER(magicard_state::test_r)
459	479	{
460		return space->machine().rand();
	480	return machine().rand();
461	481	}
462	482
463		static WRITE16_HANDLER( paletteram_io_w )
	483	WRITE16_MEMBER(magicard_state::paletteram_io_w)
464	484	{
465		magicard_state *state = space->machine().driver_data<magicard_state>();
466	485	switch(offset*2)
467	486	{
468	487	case 0:
469		state->m_pal.offs = data;
470		state->m_pal.offs_internal = 0;
	488	m_pal.offs = data;
	489	m_pal.offs_internal = 0;
471	490	break;
472	491	case 4:
473	492	break;
474	493	case 2:
475		switch(state->m_pal.offs_internal)
	494	switch(m_pal.offs_internal)
476	495	{
477	496	case 0:
478		state->m_pal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
479		state->m_pal.offs_internal++;
	497	m_pal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	498	m_pal.offs_internal++;
480	499	break;
481	500	case 1:
482		state->m_pal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
483		state->m_pal.offs_internal++;
	501	m_pal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	502	m_pal.offs_internal++;
484	503	break;
485	504	case 2:
486		state->m_pal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
487		palette_set_color(space->machine(), state->m_pal.offs, MAKE_RGB(state->m_pal.r, state->m_pal.g, state->m_pal.b));
488		state->m_pal.offs_internal = 0;
489		state->m_pal.offs++;
	505	m_pal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	506	palette_set_color(machine(), m_pal.offs, MAKE_RGB(m_pal.r, m_pal.g, m_pal.b));
	507	m_pal.offs_internal = 0;
	508	m_pal.offs++;
490	509	break;
491	510	}
492	511
r14845	r14846
494	513	}
495	514	}
496	515
497		static READ16_HANDLER( philips_66470_r )
	516	READ16_MEMBER(magicard_state::philips_66470_r)
498	517	{
499		magicard_state *state = space->machine().driver_data<magicard_state>();
500	518	switch(offset)
501	519	{
502	520	//      case 0/2:
503		//          return space->machine().rand(); //TODO
	521	//          return machine().rand(); //TODO
504	522	}
505	523
506	524	//printf("[%04x]\n",offset*2);
507	525
508	526
509		return state->m_pcab_vregs[offset];
	527	return m_pcab_vregs[offset];
510	528	}
511	529
512		static WRITE16_HANDLER( philips_66470_w )
	530	WRITE16_MEMBER(magicard_state::philips_66470_w)
513	531	{
514		magicard_state *state = space->machine().driver_data<magicard_state>();
515		COMBINE_DATA(&state->m_pcab_vregs[offset]);
	532	COMBINE_DATA(&m_pcab_vregs[offset]);
516	533
517	534	//  if(offset == 0x10/2)
518	535	//  {
519		//printf("%04x %04x %04x\n",data,state->m_pcab_vregs[0x12/2],state->m_pcab_vregs[0x14/2]);
520		//state->m_pcab_vregs[0x12/2] = state->m_pcab_vregs[0x10/2];
	536	//printf("%04x %04x %04x\n",data,m_pcab_vregs[0x12/2],m_pcab_vregs[0x14/2]);
	537	//m_pcab_vregs[0x12/2] = m_pcab_vregs[0x10/2];
521	538	//  }
522	539	}
523	540
524	541	/* scc68070 specific stuff (to be moved) */
525	542
526		static READ16_HANDLER( scc68070_ext_irqc_r )
	543	READ16_MEMBER(magicard_state::scc68070_ext_irqc_r)
527	544	{
528		magicard_state *state = space->machine().driver_data<magicard_state>();
529		return state->m_scc68070_ext_irqc_regs[offset];
	545	return m_scc68070_ext_irqc_regs[offset];
530	546	}
531	547
532		static WRITE16_HANDLER( scc68070_ext_irqc_w )
	548	WRITE16_MEMBER(magicard_state::scc68070_ext_irqc_w)
533	549	{
534		magicard_state *state = space->machine().driver_data<magicard_state>();
535		state->m_scc68070_ext_irqc_regs[offset] = data;
	550	m_scc68070_ext_irqc_regs[offset] = data;
536	551	}
537	552
538		static READ16_HANDLER( scc68070_iic_r )
	553	READ16_MEMBER(magicard_state::scc68070_iic_r)
539	554	{
540		magicard_state *state = space->machine().driver_data<magicard_state>();
541	555	//printf("%04x\n",offset*2);
542	556
543	557	switch(offset)
544	558	{
545		case 0x04/2: return state->m_scc68070_iic_regs[offset] & 0xef; //iic status register, bit 4 = pending irq
	559	case 0x04/2: return m_scc68070_iic_regs[offset] & 0xef; //iic status register, bit 4 = pending irq
546	560	}
547	561
548		return state->m_scc68070_iic_regs[offset];
	562	return m_scc68070_iic_regs[offset];
549	563	}
550	564
551		static WRITE16_HANDLER( scc68070_iic_w )
	565	WRITE16_MEMBER(magicard_state::scc68070_iic_w)
552	566	{
553		magicard_state *state = space->machine().driver_data<magicard_state>();
554		state->m_scc68070_iic_regs[offset] = data;
	567	m_scc68070_iic_regs[offset] = data;
555	568	}
556	569
557		static READ16_HANDLER( scc68070_uart_r )
	570	READ16_MEMBER(magicard_state::scc68070_uart_r)
558	571	{
559		magicard_state *state = space->machine().driver_data<magicard_state>();
560	572	//printf("%02x\n",offset*2);
561	573
562	574	switch(offset)
563	575	{
564		case 0x02/2: return space->machine().rand(); //uart mode register
	576	case 0x02/2: return machine().rand(); //uart mode register
565	577	}
566	578
567		return state->m_scc68070_uart_regs[offset];
	579	return m_scc68070_uart_regs[offset];
568	580	}
569	581
570		static WRITE16_HANDLER( scc68070_uart_w )
	582	WRITE16_MEMBER(magicard_state::scc68070_uart_w)
571	583	{
572		magicard_state *state = space->machine().driver_data<magicard_state>();
573		state->m_scc68070_uart_regs[offset] = data;
	584	m_scc68070_uart_regs[offset] = data;
574	585	}
575	586
576		static READ16_HANDLER( scc68070_timer_r )
	587	READ16_MEMBER(magicard_state::scc68070_timer_r)
577	588	{
578		magicard_state *state = space->machine().driver_data<magicard_state>();
579		return state->m_scc68070_timer_regs[offset];
	589	return m_scc68070_timer_regs[offset];
580	590	}
581	591
582		static WRITE16_HANDLER( scc68070_timer_w )
	592	WRITE16_MEMBER(magicard_state::scc68070_timer_w)
583	593	{
584		magicard_state *state = space->machine().driver_data<magicard_state>();
585		state->m_scc68070_timer_regs[offset] = data;
	594	m_scc68070_timer_regs[offset] = data;
586	595	}
587	596
588		static READ16_HANDLER( scc68070_int_irqc_r )
	597	READ16_MEMBER(magicard_state::scc68070_int_irqc_r)
589	598	{
590		magicard_state *state = space->machine().driver_data<magicard_state>();
591		return state->m_scc68070_int_irqc_regs[offset];
	599	return m_scc68070_int_irqc_regs[offset];
592	600	}
593	601
594		static WRITE16_HANDLER( scc68070_int_irqc_w )
	602	WRITE16_MEMBER(magicard_state::scc68070_int_irqc_w)
595	603	{
596		magicard_state *state = space->machine().driver_data<magicard_state>();
597		state->m_scc68070_int_irqc_regs[offset] = data;
	604	m_scc68070_int_irqc_regs[offset] = data;
598	605	}
599	606
600		static READ16_HANDLER( scc68070_dma_ch1_r )
	607	READ16_MEMBER(magicard_state::scc68070_dma_ch1_r)
601	608	{
602		magicard_state *state = space->machine().driver_data<magicard_state>();
603		return state->m_scc68070_dma_ch1_regs[offset];
	609	return m_scc68070_dma_ch1_regs[offset];
604	610	}
605	611
606		static WRITE16_HANDLER( scc68070_dma_ch1_w )
	612	WRITE16_MEMBER(magicard_state::scc68070_dma_ch1_w)
607	613	{
608		magicard_state *state = space->machine().driver_data<magicard_state>();
609		state->m_scc68070_dma_ch1_regs[offset] = data;
	614	m_scc68070_dma_ch1_regs[offset] = data;
610	615	}
611	616
612		static READ16_HANDLER( scc68070_dma_ch2_r )
	617	READ16_MEMBER(magicard_state::scc68070_dma_ch2_r)
613	618	{
614		magicard_state *state = space->machine().driver_data<magicard_state>();
615		return state->m_scc68070_dma_ch2_regs[offset];
	619	return m_scc68070_dma_ch2_regs[offset];
616	620	}
617	621
618		static WRITE16_HANDLER( scc68070_dma_ch2_w )
	622	WRITE16_MEMBER(magicard_state::scc68070_dma_ch2_w)
619	623	{
620		magicard_state *state = space->machine().driver_data<magicard_state>();
621		state->m_scc68070_dma_ch2_regs[offset] = data;
	624	m_scc68070_dma_ch2_regs[offset] = data;
622	625	}
623	626
624		static READ16_HANDLER( scc68070_mmu_r )
	627	READ16_MEMBER(magicard_state::scc68070_mmu_r)
625	628	{
626		magicard_state *state = space->machine().driver_data<magicard_state>();
627		return state->m_scc68070_mmu_regs[offset];
	629	return m_scc68070_mmu_regs[offset];
628	630	}
629	631
630		static WRITE16_HANDLER( scc68070_mmu_w )
	632	WRITE16_MEMBER(magicard_state::scc68070_mmu_w)
631	633	{
632		magicard_state *state = space->machine().driver_data<magicard_state>();
633		state->m_scc68070_mmu_regs[offset] = data;
	634	m_scc68070_mmu_regs[offset] = data;
634	635
635	636	switch(offset)
636	637	{
r14845	r14846
651	652	AM_RANGE(0x00000000, 0x0017ffff) AM_MIRROR(0x7fe00000) AM_RAM AM_BASE(m_magicram) /*only 0-7ffff accessed in Magic Card*/
652	653	AM_RANGE(0x00180000, 0x001ffbff) AM_MIRROR(0x7fe00000) AM_RAM AM_REGION("maincpu", 0)
653	654	/* 001ffc00-001ffdff System I/O */
654		AM_RANGE(0x001ffc00, 0x001ffc01) AM_MIRROR(0x7fe00000) AM_READ_LEGACY(test_r)
655		AM_RANGE(0x001ffc40, 0x001ffc41) AM_MIRROR(0x7fe00000) AM_READ_LEGACY(test_r)
656		AM_RANGE(0x001ffd00, 0x001ffd05) AM_MIRROR(0x7fe00000) AM_WRITE_LEGACY(paletteram_io_w) //RAMDAC
	655	AM_RANGE(0x001ffc00, 0x001ffc01) AM_MIRROR(0x7fe00000) AM_READ(test_r)
	656	AM_RANGE(0x001ffc40, 0x001ffc41) AM_MIRROR(0x7fe00000) AM_READ(test_r)
	657	AM_RANGE(0x001ffd00, 0x001ffd05) AM_MIRROR(0x7fe00000) AM_WRITE(paletteram_io_w) //RAMDAC
657	658	/*not the right sound chip,unknown type,it should be an ADPCM with 8 channels.*/
658	659	AM_RANGE(0x001ffd40, 0x001ffd43) AM_MIRROR(0x7fe00000) AM_DEVWRITE8_LEGACY("ymsnd", ym2413_w, 0x00ff)
659		AM_RANGE(0x001ffd80, 0x001ffd81) AM_MIRROR(0x7fe00000) AM_READ_LEGACY(test_r)
	660	AM_RANGE(0x001ffd80, 0x001ffd81) AM_MIRROR(0x7fe00000) AM_READ(test_r)
660	661	AM_RANGE(0x001ffd80, 0x001ffd81) AM_MIRROR(0x7fe00000) AM_WRITENOP //?
661	662	AM_RANGE(0x001fff80, 0x001fffbf) AM_MIRROR(0x7fe00000) AM_RAM //DRAM I/O, not accessed by this game, CD buffer?
662		AM_RANGE(0x001fffe0, 0x001fffff) AM_MIRROR(0x7fe00000) AM_READWRITE_LEGACY(philips_66470_r,philips_66470_w) AM_BASE(m_pcab_vregs) //video registers
663		AM_RANGE(0x80001000, 0x8000100f) AM_READWRITE_LEGACY(scc68070_ext_irqc_r,scc68070_ext_irqc_w) AM_BASE(m_scc68070_ext_irqc_regs) //lir
664		AM_RANGE(0x80002000, 0x8000200f) AM_READWRITE_LEGACY(scc68070_iic_r,scc68070_iic_w) AM_BASE(m_scc68070_iic_regs) //i2c
665		AM_RANGE(0x80002010, 0x8000201f) AM_READWRITE_LEGACY(scc68070_uart_r,scc68070_uart_w) AM_BASE(m_scc68070_uart_regs)
666		AM_RANGE(0x80002020, 0x8000202f) AM_READWRITE_LEGACY(scc68070_timer_r,scc68070_timer_w) AM_BASE(m_scc68070_timer_regs)
667		AM_RANGE(0x80002040, 0x8000204f) AM_READWRITE_LEGACY(scc68070_int_irqc_r,scc68070_int_irqc_w) AM_BASE(m_scc68070_int_irqc_regs)
668		AM_RANGE(0x80004000, 0x8000403f) AM_READWRITE_LEGACY(scc68070_dma_ch1_r,scc68070_dma_ch1_w) AM_BASE(m_scc68070_dma_ch1_regs)
669		AM_RANGE(0x80004040, 0x8000407f) AM_READWRITE_LEGACY(scc68070_dma_ch2_r,scc68070_dma_ch2_w) AM_BASE(m_scc68070_dma_ch2_regs)
670		AM_RANGE(0x80008000, 0x8000807f) AM_READWRITE_LEGACY(scc68070_mmu_r,scc68070_mmu_w) AM_BASE(m_scc68070_mmu_regs)
	663	AM_RANGE(0x001fffe0, 0x001fffff) AM_MIRROR(0x7fe00000) AM_READWRITE(philips_66470_r,philips_66470_w) AM_BASE(m_pcab_vregs) //video registers
	664	AM_RANGE(0x80001000, 0x8000100f) AM_READWRITE(scc68070_ext_irqc_r,scc68070_ext_irqc_w) AM_BASE(m_scc68070_ext_irqc_regs) //lir
	665	AM_RANGE(0x80002000, 0x8000200f) AM_READWRITE(scc68070_iic_r,scc68070_iic_w) AM_BASE(m_scc68070_iic_regs) //i2c
	666	AM_RANGE(0x80002010, 0x8000201f) AM_READWRITE(scc68070_uart_r,scc68070_uart_w) AM_BASE(m_scc68070_uart_regs)
	667	AM_RANGE(0x80002020, 0x8000202f) AM_READWRITE(scc68070_timer_r,scc68070_timer_w) AM_BASE(m_scc68070_timer_regs)
	668	AM_RANGE(0x80002040, 0x8000204f) AM_READWRITE(scc68070_int_irqc_r,scc68070_int_irqc_w) AM_BASE(m_scc68070_int_irqc_regs)
	669	AM_RANGE(0x80004000, 0x8000403f) AM_READWRITE(scc68070_dma_ch1_r,scc68070_dma_ch1_w) AM_BASE(m_scc68070_dma_ch1_regs)
	670	AM_RANGE(0x80004040, 0x8000407f) AM_READWRITE(scc68070_dma_ch2_r,scc68070_dma_ch2_w) AM_BASE(m_scc68070_dma_ch2_regs)
	671	AM_RANGE(0x80008000, 0x8000807f) AM_READWRITE(scc68070_mmu_r,scc68070_mmu_w) AM_BASE(m_scc68070_mmu_regs)
671	672	ADDRESS_MAP_END
672	673
673	674

src/mame/drivers/bfm_sc1.c

r14845	r14846
128	128	UINT8 m_codec_data[256];
129	129
130	130	int m_defaultbank;
	131	DECLARE_WRITE8_MEMBER(bankswitch_w);
	132	DECLARE_READ8_MEMBER(irqlatch_r);
	133	DECLARE_WRITE8_MEMBER(reel12_w);
	134	DECLARE_WRITE8_MEMBER(reel34_w);
	135	DECLARE_WRITE8_MEMBER(reel56_w);
	136	DECLARE_WRITE8_MEMBER(mmtr_w);
	137	DECLARE_READ8_MEMBER(mmtr_r);
	138	DECLARE_READ8_MEMBER(dipcoin_r);
	139	DECLARE_WRITE8_MEMBER(vfd_w);
	140	DECLARE_READ8_MEMBER(mux1latch_r);
	141	DECLARE_READ8_MEMBER(mux1datlo_r);
	142	DECLARE_READ8_MEMBER(mux1dathi_r);
	143	DECLARE_WRITE8_MEMBER(mux1latch_w);
	144	DECLARE_WRITE8_MEMBER(mux1datlo_w);
	145	DECLARE_WRITE8_MEMBER(mux1dathi_w);
	146	DECLARE_READ8_MEMBER(mux2latch_r);
	147	DECLARE_READ8_MEMBER(mux2datlo_r);
	148	DECLARE_READ8_MEMBER(mux2dathi_r);
	149	DECLARE_WRITE8_MEMBER(mux2latch_w);
	150	DECLARE_WRITE8_MEMBER(mux2datlo_w);
	151	DECLARE_WRITE8_MEMBER(mux2dathi_w);
	152	DECLARE_WRITE8_MEMBER(aciactrl_w);
	153	DECLARE_WRITE8_MEMBER(aciadata_w);
	154	DECLARE_READ8_MEMBER(aciastat_r);
	155	DECLARE_READ8_MEMBER(aciadata_r);
	156	DECLARE_WRITE8_MEMBER(triac_w);
	157	DECLARE_READ8_MEMBER(triac_r);
	158	DECLARE_WRITE8_MEMBER(vid_uart_tx_w);
	159	DECLARE_WRITE8_MEMBER(vid_uart_ctrl_w);
	160	DECLARE_READ8_MEMBER(vid_uart_rx_r);
	161	DECLARE_READ8_MEMBER(vid_uart_ctrl_r);
131	162	};
132	163
133	164	#define VFD_RESET  0x20
r14845	r14846
158	189	#endif
159	190	///////////////////////////////////////////////////////////////////////////
160	191
161		static WRITE8_HANDLER( bankswitch_w )
	192	WRITE8_MEMBER(bfm_sc1_state::bankswitch_w)
162	193	{
163	194	//  printf("bankswitch %02x\n", data);
164		memory_set_bank(space->machine(),"bank1",data & 0x03);
	195	memory_set_bank(machine(),"bank1",data & 0x03);
165	196	}
166	197
167	198	///////////////////////////////////////////////////////////////////////////
r14845	r14846
182	213
183	214	///////////////////////////////////////////////////////////////////////////
184	215
185		static READ8_HANDLER( irqlatch_r )
	216	READ8_MEMBER(bfm_sc1_state::irqlatch_r)
186	217	{
187		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
188		int result = state->m_irq_status | 0x02;
	218	int result = m_irq_status | 0x02;
189	219
190		state->m_irq_status = 0;
	220	m_irq_status = 0;
191	221
192	222	return result;
193	223	}
194	224
195	225	///////////////////////////////////////////////////////////////////////////
196	226
197		static WRITE8_HANDLER( reel12_w )
	227	WRITE8_MEMBER(bfm_sc1_state::reel12_w)
198	228	{
199		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
200		if ( state->m_locked & 0x01 )
	229	if ( m_locked & 0x01 )
201	230	{   // hardware is still locked,
202		if ( data == 0x46 ) state->m_locked &= ~0x01;
	231	if ( data == 0x46 ) m_locked &= ~0x01;
203	232	}
204	233	else
205	234	{
206		if ( stepper_update(0, (data>>4)&0x0f) ) state->m_reel_changed |= 0x01;
207		if ( stepper_update(1, data&0x0f   ) ) state->m_reel_changed |= 0x02;
	235	if ( stepper_update(0, (data>>4)&0x0f) ) m_reel_changed |= 0x01;
	236	if ( stepper_update(1, data&0x0f   ) ) m_reel_changed |= 0x02;
208	237
209		if ( stepper_optic_state(0) ) state->m_optic_pattern |=  0x01;
210		else                          state->m_optic_pattern &= ~0x01;
211		if ( stepper_optic_state(1) ) state->m_optic_pattern |=  0x02;
212		else                          state->m_optic_pattern &= ~0x02;
	238	if ( stepper_optic_state(0) ) m_optic_pattern |=  0x01;
	239	else                          m_optic_pattern &= ~0x01;
	240	if ( stepper_optic_state(1) ) m_optic_pattern |=  0x02;
	241	else                          m_optic_pattern &= ~0x02;
213	242	}
214	243	awp_draw_reel(0);
215	244	awp_draw_reel(1);
r14845	r14846
217	246
218	247	///////////////////////////////////////////////////////////////////////////
219	248
220		static WRITE8_HANDLER( reel34_w )
	249	WRITE8_MEMBER(bfm_sc1_state::reel34_w)
221	250	{
222		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
223		if ( state->m_locked & 0x02 )
	251	if ( m_locked & 0x02 )
224	252	{   // hardware is still locked,
225		if ( data == 0x42 ) state->m_locked &= ~0x02;
	253	if ( data == 0x42 ) m_locked &= ~0x02;
226	254	}
227	255	else
228	256	{
229		if ( stepper_update(2, (data>>4)&0x0f) ) state->m_reel_changed |= 0x04;
230		if ( stepper_update(3, data&0x0f   ) ) state->m_reel_changed |= 0x08;
	257	if ( stepper_update(2, (data>>4)&0x0f) ) m_reel_changed |= 0x04;
	258	if ( stepper_update(3, data&0x0f   ) ) m_reel_changed |= 0x08;
231	259
232		if ( stepper_optic_state(2) ) state->m_optic_pattern |=  0x04;
233		else                          state->m_optic_pattern &= ~0x04;
234		if ( stepper_optic_state(3) ) state->m_optic_pattern |=  0x08;
235		else                          state->m_optic_pattern &= ~0x08;
	260	if ( stepper_optic_state(2) ) m_optic_pattern |=  0x04;
	261	else                          m_optic_pattern &= ~0x04;
	262	if ( stepper_optic_state(3) ) m_optic_pattern |=  0x08;
	263	else                          m_optic_pattern &= ~0x08;
236	264	}
237	265	awp_draw_reel(2);
238	266	awp_draw_reel(3);
r14845	r14846
240	268
241	269	///////////////////////////////////////////////////////////////////////////
242	270
243		static WRITE8_HANDLER( reel56_w )
	271	WRITE8_MEMBER(bfm_sc1_state::reel56_w)
244	272	{
245		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
246		if ( stepper_update(4, (data>>4)&0x0f) ) state->m_reel_changed |= 0x10;
247		if ( stepper_update(5, data&0x0f   ) ) state->m_reel_changed |= 0x20;
	273	if ( stepper_update(4, (data>>4)&0x0f) ) m_reel_changed |= 0x10;
	274	if ( stepper_update(5, data&0x0f   ) ) m_reel_changed |= 0x20;
248	275
249		if ( stepper_optic_state(4) ) state->m_optic_pattern |=  0x10;
250		else                          state->m_optic_pattern &= ~0x10;
251		if ( stepper_optic_state(5) ) state->m_optic_pattern |=  0x20;
252		else                          state->m_optic_pattern &= ~0x20;
	276	if ( stepper_optic_state(4) ) m_optic_pattern |=  0x10;
	277	else                          m_optic_pattern &= ~0x10;
	278	if ( stepper_optic_state(5) ) m_optic_pattern |=  0x20;
	279	else                          m_optic_pattern &= ~0x20;
253	280	awp_draw_reel(5);
254	281	awp_draw_reel(6);
255	282	}
r14845	r14846
258	285	// mechanical meters //////////////////////////////////////////////////////
259	286	///////////////////////////////////////////////////////////////////////////
260	287
261		static WRITE8_HANDLER( mmtr_w )
	288	WRITE8_MEMBER(bfm_sc1_state::mmtr_w)
262	289	{
263		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
264	290	int i;
265		if ( state->m_locked & 0x04 )
	291	if ( m_locked & 0x04 )
266	292	{   // hardware is still locked,
267		state->m_locked &= ~0x04;
	293	m_locked &= ~0x04;
268	294	}
269	295	else
270	296	{
271		int  changed = state->m_mmtr_latch ^ data;
	297	int  changed = m_mmtr_latch ^ data;
272	298
273		state->m_mmtr_latch = data;
	299	m_mmtr_latch = data;
274	300
275	301	for (i=0; i<8; i++)
276	302	{
277	303	if ( changed & (1 << i) )
278	304	{
279	305	MechMtr_update(i, data & (1 << i) );
280		generic_pulse_irq_line(space->machine().device("maincpu"), M6809_FIRQ_LINE, 1);
	306	generic_pulse_irq_line(machine().device("maincpu"), M6809_FIRQ_LINE, 1);
281	307	}
282	308	}
283	309	}
r14845	r14846
285	311
286	312	///////////////////////////////////////////////////////////////////////////
287	313
288		static READ8_HANDLER( mmtr_r )
	314	READ8_MEMBER(bfm_sc1_state::mmtr_r)
289	315	{
290		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
291		return state->m_mmtr_latch;
	316	return m_mmtr_latch;
292	317	}
293	318
294	319	///////////////////////////////////////////////////////////////////////////
295	320
296		static READ8_HANDLER( dipcoin_r )
	321	READ8_MEMBER(bfm_sc1_state::dipcoin_r)
297	322	{
298		return input_port_read(space->machine(),"STROBE0") & 0x1F;
	323	return input_port_read(machine(),"STROBE0") & 0x1F;
299	324	}
300	325
301	326	///////////////////////////////////////////////////////////////////////////
r14845	r14846
307	332
308	333	///////////////////////////////////////////////////////////////////////////
309	334
310		static WRITE8_HANDLER( vfd_w )
	335	WRITE8_MEMBER(bfm_sc1_state::vfd_w)
311	336	{
312		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
313		int changed = state->m_vfd_latch ^ data;
	337	int changed = m_vfd_latch ^ data;
314	338
315		state->m_vfd_latch = data;
	339	m_vfd_latch = data;
316	340
317	341	if ( changed )
318	342	{
r14845	r14846
369	393
370	394	/////////////////////////////////////////////////////////////////////////////////////
371	395
372		static READ8_HANDLER( mux1latch_r )
	396	READ8_MEMBER(bfm_sc1_state::mux1latch_r)
373	397	{
374		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
375		return state->m_mux1_input;
	398	return m_mux1_input;
376	399	}
377	400
378	401	/////////////////////////////////////////////////////////////////////////////////////
379	402
380		static READ8_HANDLER( mux1datlo_r )
	403	READ8_MEMBER(bfm_sc1_state::mux1datlo_r)
381	404	{
382	405	return 0;
383	406	}
384	407
385	408	/////////////////////////////////////////////////////////////////////////////////////
386	409
387		static READ8_HANDLER( mux1dathi_r )
	410	READ8_MEMBER(bfm_sc1_state::mux1dathi_r)
388	411	{
389	412	return 0;
390	413	}
391	414
392	415	/////////////////////////////////////////////////////////////////////////////////////
393	416
394		static WRITE8_HANDLER( mux1latch_w )
	417	WRITE8_MEMBER(bfm_sc1_state::mux1latch_w)
395	418	{
396		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
397		int changed = state->m_mux1_outputlatch ^ data;
	419	int changed = m_mux1_outputlatch ^ data;
398	420	static const char *const portnames[] = { "STROBE0", "STROBE1", "STROBE2", "STROBE3", "STROBE4", "STROBE5", "STROBE6", "STROBE7" };
399		state->m_mux1_outputlatch = data;
	421	m_mux1_outputlatch = data;
400	422
401	423	if ( changed & 0x08 )
402	424	{ // clock changed
r14845	r14846
412	434
413	435	for ( i = 0; i < 8; i++ )
414	436	{
415		output_set_lamp_value(BFM_strcnv[offset  ], (state->m_mux1_datalo & pattern?1:0) );
416		output_set_lamp_value(BFM_strcnv[offset+8], (state->m_mux1_datahi & pattern?1:0) );
	437	output_set_lamp_value(BFM_strcnv[offset  ], (m_mux1_datalo & pattern?1:0) );
	438	output_set_lamp_value(BFM_strcnv[offset+8], (m_mux1_datahi & pattern?1:0) );
417	439	pattern<<=1;
418	440	offset++;
419	441	}
r14845	r14846
422	444
423	445	if ( !(data & 0x08) )
424	446	{
425		state->m_sc1_Inputs[ input_strobe ] = input_port_read(space->machine(),portnames[input_strobe]);
	447	m_sc1_Inputs[ input_strobe ] = input_port_read(machine(),portnames[input_strobe]);
426	448
427		state->m_mux1_input = state->m_sc1_Inputs[ input_strobe ];
	449	m_mux1_input = m_sc1_Inputs[ input_strobe ];
428	450	}
429	451	}
430	452	}
431	453
432	454	/////////////////////////////////////////////////////////////////////////////////////
433	455
434		static WRITE8_HANDLER( mux1datlo_w )
	456	WRITE8_MEMBER(bfm_sc1_state::mux1datlo_w)
435	457	{
436		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
437		state->m_mux1_datalo = data;
	458	m_mux1_datalo = data;
438	459	}
439	460
440	461	/////////////////////////////////////////////////////////////////////////////////////
441	462
442		static WRITE8_HANDLER( mux1dathi_w )
	463	WRITE8_MEMBER(bfm_sc1_state::mux1dathi_w)
443	464	{
444		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
445		state->m_mux1_datahi = data;
	465	m_mux1_datahi = data;
446	466	}
447	467
448	468	/////////////////////////////////////////////////////////////////////////////////////
449	469
450		static READ8_HANDLER( mux2latch_r )
	470	READ8_MEMBER(bfm_sc1_state::mux2latch_r)
451	471	{
452		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
453		return state->m_mux2_input;
	472	return m_mux2_input;
454	473	}
455	474
456	475	/////////////////////////////////////////////////////////////////////////////////////
457	476
458		static READ8_HANDLER( mux2datlo_r )
	477	READ8_MEMBER(bfm_sc1_state::mux2datlo_r)
459	478	{
460	479	return 0;
461	480	}
462	481
463	482	/////////////////////////////////////////////////////////////////////////////////////
464	483
465		static READ8_HANDLER( mux2dathi_r )
	484	READ8_MEMBER(bfm_sc1_state::mux2dathi_r)
466	485	{
467	486	return 0;
468	487	}
469	488
470	489	/////////////////////////////////////////////////////////////////////////////////////
471	490
472		static WRITE8_HANDLER( mux2latch_w )
	491	WRITE8_MEMBER(bfm_sc1_state::mux2latch_w)
473	492	{
474		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
475		int changed = state->m_mux2_outputlatch ^ data;
	493	int changed = m_mux2_outputlatch ^ data;
476	494
477		state->m_mux2_outputlatch = data;
	495	m_mux2_outputlatch = data;
478	496
479	497	if ( changed & 0x08 )
480	498	{ // clock changed
r14845	r14846
489	507
490	508	for ( i = 0; i < 8; i++ )
491	509	{
492		output_set_lamp_value(BFM_strcnv[offset  ], (state->m_mux2_datalo & pattern?1:0) );
493		output_set_lamp_value(BFM_strcnv[offset+8], (state->m_mux2_datahi & pattern?1:0) );
	510	output_set_lamp_value(BFM_strcnv[offset  ], (m_mux2_datalo & pattern?1:0) );
	511	output_set_lamp_value(BFM_strcnv[offset+8], (m_mux2_datahi & pattern?1:0) );
494	512	pattern<<=1;
495	513	offset++;
496	514	}
r14845	r14846
498	516
499	517	if ( !(data & 0x08) )
500	518	{
501		state->m_mux2_input = 0x3F ^ state->m_optic_pattern;
	519	m_mux2_input = 0x3F ^ m_optic_pattern;
502	520	}
503	521	}
504	522	}
505	523
506	524	/////////////////////////////////////////////////////////////////////////////////////
507	525
508		static WRITE8_HANDLER( mux2datlo_w )
	526	WRITE8_MEMBER(bfm_sc1_state::mux2datlo_w)
509	527	{
510		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
511		state->m_mux2_datalo = data;
	528	m_mux2_datalo = data;
512	529	}
513	530
514	531	/////////////////////////////////////////////////////////////////////////////////////
515	532
516		static WRITE8_HANDLER( mux2dathi_w )
	533	WRITE8_MEMBER(bfm_sc1_state::mux2dathi_w)
517	534	{
518		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
519		state->m_mux2_datahi = data;
	535	m_mux2_datahi = data;
520	536	}
521	537
522	538	/////////////////////////////////////////////////////////////////////////////////////
523	539	// serial port //////////////////////////////////////////////////////////////////////
524	540	/////////////////////////////////////////////////////////////////////////////////////
525	541
526		static WRITE8_HANDLER( aciactrl_w )
	542	WRITE8_MEMBER(bfm_sc1_state::aciactrl_w)
527	543	{
528	544	}
529	545
530	546	/////////////////////////////////////////////////////////////////////////////////////
531	547
532		static WRITE8_HANDLER( aciadata_w )
	548	WRITE8_MEMBER(bfm_sc1_state::aciadata_w)
533	549	{
534	550	}
535	551
536	552	/////////////////////////////////////////////////////////////////////////////////////
537	553
538		static READ8_HANDLER( aciastat_r )
	554	READ8_MEMBER(bfm_sc1_state::aciastat_r)
539	555	{
540		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
541		return state->m_acia_status;
	556	return m_acia_status;
542	557	}
543	558
544	559	/////////////////////////////////////////////////////////////////////////////////////
545	560
546		static READ8_HANDLER( aciadata_r )
	561	READ8_MEMBER(bfm_sc1_state::aciadata_r)
547	562	{
548	563	return 0;
549	564	}
r14845	r14846
552	567	// payslide triacs //////////////////////////////////////////////////////////////////
553	568	/////////////////////////////////////////////////////////////////////////////////////
554	569
555		static WRITE8_HANDLER( triac_w )
	570	WRITE8_MEMBER(bfm_sc1_state::triac_w)
556	571	{
557		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
558		state->m_triac_latch = data;
	572	m_triac_latch = data;
559	573	}
560	574
561	575	/////////////////////////////////////////////////////////////////////////////////////
562	576
563		static READ8_HANDLER( triac_r )
	577	READ8_MEMBER(bfm_sc1_state::triac_r)
564	578	{
565		bfm_sc1_state *state = space->machine().driver_data<bfm_sc1_state>();
566		return state->m_triac_latch;
	579	return m_triac_latch;
567	580	}
568	581
569	582	/////////////////////////////////////////////////////////////////////////////////////
r14845	r14846
584	597
585	598	/////////////////////////////////////////////////////////////////////////////////////
586	599
587		static WRITE8_HANDLER( vid_uart_tx_w )
	600	WRITE8_MEMBER(bfm_sc1_state::vid_uart_tx_w)
588	601	{
589	602	adder2_send(data);
590		cputag_set_input_line(space->machine(), "adder2", M6809_IRQ_LINE, ASSERT_LINE );//HOLD_LINE);// trigger IRQ
	603	cputag_set_input_line(machine(), "adder2", M6809_IRQ_LINE, ASSERT_LINE );//HOLD_LINE);// trigger IRQ
591	604	}
592	605
593	606	///////////////////////////////////////////////////////////////////////////
594	607
595		static WRITE8_HANDLER( vid_uart_ctrl_w )
	608	WRITE8_MEMBER(bfm_sc1_state::vid_uart_ctrl_w)
596	609	{
597	610	}
598	611
599	612	///////////////////////////////////////////////////////////////////////////
600	613
601		static READ8_HANDLER( vid_uart_rx_r )
	614	READ8_MEMBER(bfm_sc1_state::vid_uart_rx_r)
602	615	{
603	616	return adder2_receive();
604	617	}
605	618
606	619	///////////////////////////////////////////////////////////////////////////
607	620
608		static READ8_HANDLER( vid_uart_ctrl_r )
	621	READ8_MEMBER(bfm_sc1_state::vid_uart_ctrl_r)
609	622	{
610	623	return adder2_status();
611	624	}
r14845	r14846
669	682	static ADDRESS_MAP_START( sc1_base, AS_PROGRAM, 8, bfm_sc1_state )
670	683
671	684	AM_RANGE(0x0000, 0x1FFF) AM_RAM AM_SHARE("nvram") //8k RAM
672		AM_RANGE(0x2000, 0x21FF) AM_WRITE_LEGACY(reel34_w)            // reel 2+3 latch
673		AM_RANGE(0x2200, 0x23FF) AM_WRITE_LEGACY(reel12_w)            // reel 1+2 latch
674		AM_RANGE(0x2400, 0x25FF) AM_WRITE_LEGACY(vfd_w)            // vfd latch
	685	AM_RANGE(0x2000, 0x21FF) AM_WRITE(reel34_w)            // reel 2+3 latch
	686	AM_RANGE(0x2200, 0x23FF) AM_WRITE(reel12_w)            // reel 1+2 latch
	687	AM_RANGE(0x2400, 0x25FF) AM_WRITE(vfd_w)            // vfd latch
675	688
676		AM_RANGE(0x2600, 0x27FF) AM_READWRITE_LEGACY(mmtr_r,mmtr_w)   // mechanical meters
677		AM_RANGE(0x2800, 0x2800) AM_READWRITE_LEGACY(triac_r,triac_w)   // payslide triacs
	689	AM_RANGE(0x2600, 0x27FF) AM_READWRITE(mmtr_r,mmtr_w)   // mechanical meters
	690	AM_RANGE(0x2800, 0x2800) AM_READWRITE(triac_r,triac_w)   // payslide triacs
678	691
679		AM_RANGE(0x2A00, 0x2A00) AM_READWRITE_LEGACY(mux1latch_r,mux1latch_w) // mux1
680		AM_RANGE(0x2A01, 0x2A01) AM_READWRITE_LEGACY(mux1datlo_r,mux1datlo_w)
681		AM_RANGE(0x2A02, 0x2A02) AM_READWRITE_LEGACY(mux1dathi_r,mux1dathi_w)
	692	AM_RANGE(0x2A00, 0x2A00) AM_READWRITE(mux1latch_r,mux1latch_w) // mux1
	693	AM_RANGE(0x2A01, 0x2A01) AM_READWRITE(mux1datlo_r,mux1datlo_w)
	694	AM_RANGE(0x2A02, 0x2A02) AM_READWRITE(mux1dathi_r,mux1dathi_w)
682	695
683		AM_RANGE(0x2E00, 0x2E00) AM_READ_LEGACY(irqlatch_r)         // irq latch
	696	AM_RANGE(0x2E00, 0x2E00) AM_READ(irqlatch_r)         // irq latch
684	697
685	698	AM_RANGE(0x3001, 0x3001) AM_READ_LEGACY(soundlatch_r)
686	699	AM_RANGE(0x3001, 0x3001) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
687	700	AM_RANGE(0x3101, 0x3201) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
688	701
689		AM_RANGE(0x3406, 0x3406) AM_READWRITE_LEGACY(aciastat_r,aciactrl_w)  // MC6850 status register
690		AM_RANGE(0x3407, 0x3407) AM_READWRITE_LEGACY(aciadata_r,aciadata_w)  // MC6850 data register
	702	AM_RANGE(0x3406, 0x3406) AM_READWRITE(aciastat_r,aciactrl_w)  // MC6850 status register
	703	AM_RANGE(0x3407, 0x3407) AM_READWRITE(aciadata_r,aciadata_w)  // MC6850 data register
691	704
692		AM_RANGE(0x3408, 0x3408) AM_READWRITE_LEGACY(mux2latch_r,mux2latch_w) // mux2
693		AM_RANGE(0x3409, 0x3409) AM_READWRITE_LEGACY(mux2datlo_r,mux2datlo_w)
694		AM_RANGE(0x340A, 0x340A) AM_READWRITE_LEGACY(mux2dathi_r,mux2dathi_w)
	705	AM_RANGE(0x3408, 0x3408) AM_READWRITE(mux2latch_r,mux2latch_w) // mux2
	706	AM_RANGE(0x3409, 0x3409) AM_READWRITE(mux2datlo_r,mux2datlo_w)
	707	AM_RANGE(0x340A, 0x340A) AM_READWRITE(mux2dathi_r,mux2dathi_w)
695	708
696		AM_RANGE(0x3600, 0x3600) AM_WRITE_LEGACY(bankswitch_w)       // write bank
697		AM_RANGE(0x3800, 0x39FF) AM_WRITE_LEGACY(reel56_w)            // reel 5+6 latch
	709	AM_RANGE(0x3600, 0x3600) AM_WRITE(bankswitch_w)       // write bank
	710	AM_RANGE(0x3800, 0x39FF) AM_WRITE(reel56_w)            // reel 5+6 latch
698	711
699	712	AM_RANGE(0x4000, 0x5FFF) AM_ROM                     // 8k  ROM
700	713	AM_RANGE(0x6000, 0x7FFF) AM_ROMBANK("bank1")               // 8k  paged ROM (4 pages)
r14845	r14846
709	722	static ADDRESS_MAP_START( sc1_adder2, AS_PROGRAM, 8, bfm_sc1_state )
710	723	AM_IMPORT_FROM( sc1_base )
711	724
712		AM_RANGE(0x3E00, 0x3E00) AM_READWRITE_LEGACY(vid_uart_ctrl_r,vid_uart_ctrl_w)   // video uart control reg read
713		AM_RANGE(0x3E01, 0x3E01) AM_READWRITE_LEGACY(vid_uart_rx_r,vid_uart_tx_w)      // video uart receive  reg
	725	AM_RANGE(0x3E00, 0x3E00) AM_READWRITE(vid_uart_ctrl_r,vid_uart_ctrl_w)   // video uart control reg read
	726	AM_RANGE(0x3E01, 0x3E01) AM_READWRITE(vid_uart_rx_r,vid_uart_tx_w)      // video uart receive  reg
714	727	ADDRESS_MAP_END
715	728
716	729
r14845	r14846
721	734	static ADDRESS_MAP_START( sc1_viper, AS_PROGRAM, 8, bfm_sc1_state )
722	735	AM_IMPORT_FROM( sc1_base )
723	736
724		AM_RANGE(0x3404, 0x3404) AM_READ_LEGACY(dipcoin_r ) // coin input on gamecard
	737	AM_RANGE(0x3404, 0x3404) AM_READ(dipcoin_r ) // coin input on gamecard
725	738	AM_RANGE(0x3801, 0x3801) AM_DEVREAD_LEGACY("upd", nec_r)
726	739	AM_RANGE(0x3800, 0x39FF) AM_DEVWRITE_LEGACY("upd", nec_latch_w)
727	740	ADDRESS_MAP_END

src/mame/drivers/murogem.c

r14845	r14846
117	117	: driver_device(mconfig, type, tag) { }
118	118
119	119	UINT8 *m_videoram;
	120	DECLARE_WRITE8_MEMBER(outport_w);
120	121	};
121	122
122	123
123		static WRITE8_HANDLER( outport_w )
	124	WRITE8_MEMBER(murogem_state::outport_w)
124	125	{
125	126	/*
126	127	It's a Delta-Sigma DAC (1-bit/Bitstream)
r14845	r14846
129	130	7654 3210
130	131	---- x---   Sound DAC.
131	132	*/
132		dac_data_w(space->machine().device("dac"), data & 0x08);
	133	dac_data_w(machine().device("dac"), data & 0x08);
133	134	}
134	135
135	136
r14845	r14846
139	140	AM_RANGE(0x4001, 0x4001) AM_DEVWRITE("crtc", mc6845_device, register_w)
140	141	AM_RANGE(0x5000, 0x5000) AM_READ_PORT("IN0")
141	142	AM_RANGE(0x5800, 0x5800) AM_READ_PORT("IN1")
142		AM_RANGE(0x7000, 0x7000) AM_WRITE_LEGACY(outport_w)   /* output port */
	143	AM_RANGE(0x7000, 0x7000) AM_WRITE(outport_w)   /* output port */
143	144	AM_RANGE(0x8000, 0x87ff) AM_RAM AM_BASE(m_videoram)
144	145	AM_RANGE(0xf000, 0xffff) AM_ROM
145	146	ADDRESS_MAP_END

src/mame/drivers/cntsteer.c

r14845	r14846
62	62	device_t *m_maincpu;
63	63	device_t *m_audiocpu;
64	64	device_t *m_subcpu;
	65	DECLARE_WRITE8_MEMBER(zerotrgt_vregs_w);
	66	DECLARE_WRITE8_MEMBER(cntsteer_vregs_w);
	67	DECLARE_WRITE8_MEMBER(cntsteer_foreground_vram_w);
	68	DECLARE_WRITE8_MEMBER(cntsteer_foreground_attr_w);
	69	DECLARE_WRITE8_MEMBER(cntsteer_background_w);
	70	DECLARE_WRITE8_MEMBER(gekitsui_sub_irq_ack);
	71	DECLARE_WRITE8_MEMBER(cntsteer_sound_w);
	72	DECLARE_WRITE8_MEMBER(zerotrgt_ctrl_w);
	73	DECLARE_WRITE8_MEMBER(cntsteer_sub_irq_w);
	74	DECLARE_WRITE8_MEMBER(cntsteer_sub_nmi_w);
	75	DECLARE_WRITE8_MEMBER(cntsteer_main_irq_w);
	76	DECLARE_READ8_MEMBER(cntsteer_adx_r);
	77	DECLARE_WRITE8_MEMBER(nmimask_w);
65	78	};
66	79
67	80
r14845	r14846
365	378	---- ---x rotation sign (landscape should be turning right (0) == / , turning left (1) == \)
366	379	[4] = xxxx xxxx rotation factor?
367	380	*/
368		static WRITE8_HANDLER(zerotrgt_vregs_w)
	381	WRITE8_MEMBER(cntsteer_state::zerotrgt_vregs_w)
369	382	{
370		cntsteer_state *state = space->machine().driver_data<cntsteer_state>();
371	383	//  static UINT8 test[5];
372	384
373	385	//  test[offset] = data;
r14845	r14846
375	387
376	388	switch (offset)
377	389	{
378		case 0:   state->m_scrolly = data; break;
379		case 1:   state->m_scrollx = data; break;
380		case 2:   state->m_bg_bank = (data & 0x30) << 4;
381		state->m_bg_color_bank = (data & 7);
382		state->m_disable_roz = (data & 0x40);
383		state->m_bg_tilemap->mark_all_dirty();
	390	case 0:   m_scrolly = data; break;
	391	case 1:   m_scrollx = data; break;
	392	case 2:   m_bg_bank = (data & 0x30) << 4;
	393	m_bg_color_bank = (data & 7);
	394	m_disable_roz = (data & 0x40);
	395	m_bg_tilemap->mark_all_dirty();
384	396	break;
385		case 3:   state->m_rotation_sign = (data & 1);
386		flip_screen_set(space->machine(), !(data & 4));
387		state->m_scrolly_hi = (data & 0x30) << 4;
388		state->m_scrollx_hi = (data & 0xc0) << 2;
	397	case 3:   m_rotation_sign = (data & 1);
	398	flip_screen_set(machine(), !(data & 4));
	399	m_scrolly_hi = (data & 0x30) << 4;
	400	m_scrollx_hi = (data & 0xc0) << 2;
389	401	break;
390		case 4:   state->m_rotation_x = data; break;
	402	case 4:   m_rotation_x = data; break;
391	403	}
392	404	}
393	405
394		static WRITE8_HANDLER(cntsteer_vregs_w)
	406	WRITE8_MEMBER(cntsteer_state::cntsteer_vregs_w)
395	407	{
396		cntsteer_state *state = space->machine().driver_data<cntsteer_state>();
397	408	//  static UINT8 test[5];
398	409
399	410	//  test[offset] = data;
r14845	r14846
401	412
402	413	switch(offset)
403	414	{
404		case 0:   state->m_scrolly = data; break;
405		case 1:   state->m_scrollx = data; break;
406		case 2:   state->m_bg_bank = (data & 0x01) << 8;
407		state->m_bg_color_bank = (data & 6) >> 1;
408		state->m_bg_tilemap->mark_all_dirty();
	415	case 0:   m_scrolly = data; break;
	416	case 1:   m_scrollx = data; break;
	417	case 2:   m_bg_bank = (data & 0x01) << 8;
	418	m_bg_color_bank = (data & 6) >> 1;
	419	m_bg_tilemap->mark_all_dirty();
409	420	break;
410		case 3:   state->m_rotation_sign = (data & 7);
411		state->m_disable_roz = (~data & 0x08);
412		state->m_scrolly_hi = (data & 0x30) << 4;
413		state->m_scrollx_hi = (data & 0xc0) << 2;
	421	case 3:   m_rotation_sign = (data & 7);
	422	m_disable_roz = (~data & 0x08);
	423	m_scrolly_hi = (data & 0x30) << 4;
	424	m_scrollx_hi = (data & 0xc0) << 2;
414	425	break;
415		case 4:   state->m_rotation_x = data; break;
	426	case 4:   m_rotation_x = data; break;
416	427	}
417	428	}
418	429
419		static WRITE8_HANDLER( cntsteer_foreground_vram_w )
	430	WRITE8_MEMBER(cntsteer_state::cntsteer_foreground_vram_w)
420	431	{
421		cntsteer_state *state = space->machine().driver_data<cntsteer_state>();
422		state->m_videoram[offset] = data;
423		state->m_fg_tilemap->mark_tile_dirty(offset);
	432	m_videoram[offset] = data;
	433	m_fg_tilemap->mark_tile_dirty(offset);
424	434	}
425	435
426		static WRITE8_HANDLER( cntsteer_foreground_attr_w )
	436	WRITE8_MEMBER(cntsteer_state::cntsteer_foreground_attr_w)
427	437	{
428		cntsteer_state *state = space->machine().driver_data<cntsteer_state>();
429		state->m_colorram[offset] = data;
430		state->m_fg_tilemap->mark_tile_dirty(offset);
	438	m_colorram[offset] = data;
	439	m_fg_tilemap->mark_tile_dirty(offset);
431	440	}
432	441
433		static WRITE8_HANDLER( cntsteer_background_w )
	442	WRITE8_MEMBER(cntsteer_state::cntsteer_background_w)
434	443	{
435		cntsteer_state *state = space->machine().driver_data<cntsteer_state>();
436		state->m_videoram2[offset] = data;
437		state->m_bg_tilemap->mark_tile_dirty(offset);
	444	m_videoram2[offset] = data;
	445	m_bg_tilemap->mark_tile_dirty(offset);
438	446	}
439	447
440	448	/*************************************
r14845	r14846
443	451	*
444	452	*************************************/
445	453
446		static WRITE8_HANDLER( gekitsui_sub_irq_ack )
	454	WRITE8_MEMBER(cntsteer_state::gekitsui_sub_irq_ack)
447	455	{
448		cntsteer_state *state = space->machine().driver_data<cntsteer_state>();
449		device_set_input_line(state->m_subcpu, M6809_IRQ_LINE, CLEAR_LINE);
	456	device_set_input_line(m_subcpu, M6809_IRQ_LINE, CLEAR_LINE);
450	457	}
451	458
452		static WRITE8_HANDLER( cntsteer_sound_w )
	459	WRITE8_MEMBER(cntsteer_state::cntsteer_sound_w)
453	460	{
454		cntsteer_state *state = space->machine().driver_data<cntsteer_state>();
455	461	soundlatch_w(space, 0, data);
456		device_set_input_line(state->m_audiocpu, 0, HOLD_LINE);
	462	device_set_input_line(m_audiocpu, 0, HOLD_LINE);
457	463	}
458	464
459		static WRITE8_HANDLER( zerotrgt_ctrl_w )
	465	WRITE8_MEMBER(cntsteer_state::zerotrgt_ctrl_w)
460	466	{
461		cntsteer_state *state = space->machine().driver_data<cntsteer_state>();
462	467	/*TODO: check this.*/
463		logerror("CTRL: %04x: %04x: %04x\n", cpu_get_pc(&space->device()), offset, data);
464		//  if (offset == 0) device_set_input_line(state->m_subcpu, INPUT_LINE_RESET, ASSERT_LINE);
	468	logerror("CTRL: %04x: %04x: %04x\n", cpu_get_pc(&space.device()), offset, data);
	469	//  if (offset == 0) device_set_input_line(m_subcpu, INPUT_LINE_RESET, ASSERT_LINE);
465	470
466	471	// Wrong - bits 0 & 1 used on this
467		if (offset == 1) device_set_input_line(state->m_subcpu, M6809_IRQ_LINE, ASSERT_LINE);
468		//  if (offset == 2) device_set_input_line(state->m_subcpu, INPUT_LINE_RESET, CLEAR_LINE);
	472	if (offset == 1) device_set_input_line(m_subcpu, M6809_IRQ_LINE, ASSERT_LINE);
	473	//  if (offset == 2) device_set_input_line(m_subcpu, INPUT_LINE_RESET, CLEAR_LINE);
469	474	}
470	475
471		static WRITE8_HANDLER( cntsteer_sub_irq_w )
	476	WRITE8_MEMBER(cntsteer_state::cntsteer_sub_irq_w)
472	477	{
473		cntsteer_state *state = space->machine().driver_data<cntsteer_state>();
474		device_set_input_line(state->m_subcpu, M6809_IRQ_LINE, ASSERT_LINE);
	478	device_set_input_line(m_subcpu, M6809_IRQ_LINE, ASSERT_LINE);
475	479	//  printf("%02x IRQ\n", data);
476	480	}
477	481
478		static WRITE8_HANDLER( cntsteer_sub_nmi_w )
	482	WRITE8_MEMBER(cntsteer_state::cntsteer_sub_nmi_w)
479	483	{
480	484	//  if (data)
481		//  device_set_input_line(state->m_subcpu, INPUT_LINE_NMI, PULSE_LINE);
	485	//  device_set_input_line(m_subcpu, INPUT_LINE_NMI, PULSE_LINE);
482	486	//  popmessage("%02x", data);
483	487	}
484	488
485		static WRITE8_HANDLER( cntsteer_main_irq_w )
	489	WRITE8_MEMBER(cntsteer_state::cntsteer_main_irq_w)
486	490	{
487		cntsteer_state *state = space->machine().driver_data<cntsteer_state>();
488		device_set_input_line(state->m_maincpu, M6809_IRQ_LINE, HOLD_LINE);
	491	device_set_input_line(m_maincpu, M6809_IRQ_LINE, HOLD_LINE);
489	492	}
490	493
491	494	/* Convert weird input handling with MAME standards.*/
492		static READ8_HANDLER( cntsteer_adx_r )
	495	READ8_MEMBER(cntsteer_state::cntsteer_adx_r)
493	496	{
494	497	UINT8 res = 0, adx_val;
495		adx_val = input_port_read(space->machine(), "AN_STEERING");
	498	adx_val = input_port_read(machine(), "AN_STEERING");
496	499
497	500	if (adx_val >= 0x70 && adx_val <= 0x90)
498	501	res = 0xff;
r14845	r14846
528	531	AM_RANGE(0x0000, 0x0fff) AM_RAM AM_SHARE("share1")
529	532	AM_RANGE(0x1000, 0x11ff) AM_RAM AM_BASE(m_spriteram)
530	533	AM_RANGE(0x1200, 0x1fff) AM_RAM
531		AM_RANGE(0x2000, 0x23ff) AM_RAM_WRITE_LEGACY(cntsteer_foreground_vram_w) AM_BASE(m_videoram)
532		AM_RANGE(0x2400, 0x27ff) AM_RAM_WRITE_LEGACY(cntsteer_foreground_attr_w) AM_BASE(m_colorram)
533		AM_RANGE(0x3000, 0x3003) AM_WRITE_LEGACY(zerotrgt_ctrl_w)
	534	AM_RANGE(0x2000, 0x23ff) AM_RAM_WRITE(cntsteer_foreground_vram_w) AM_BASE(m_videoram)
	535	AM_RANGE(0x2400, 0x27ff) AM_RAM_WRITE(cntsteer_foreground_attr_w) AM_BASE(m_colorram)
	536	AM_RANGE(0x3000, 0x3003) AM_WRITE(zerotrgt_ctrl_w)
534	537	AM_RANGE(0x8000, 0xffff) AM_ROM
535	538	ADDRESS_MAP_END
536	539
537	540	static ADDRESS_MAP_START( gekitsui_cpu2_map, AS_PROGRAM, 8, cntsteer_state )
538	541	AM_RANGE(0x0000, 0x0fff) AM_RAM AM_SHARE("share1")
539		AM_RANGE(0x1000, 0x1fff) AM_RAM_WRITE_LEGACY(cntsteer_background_w) AM_BASE(m_videoram2)
	542	AM_RANGE(0x1000, 0x1fff) AM_RAM_WRITE(cntsteer_background_w) AM_BASE(m_videoram2)
540	543	AM_RANGE(0x3000, 0x3000) AM_READ_PORT("DSW0")
541	544	AM_RANGE(0x3001, 0x3001) AM_READ_PORT("P2")
542	545	AM_RANGE(0x3002, 0x3002) AM_READ_PORT("P1")
543	546	AM_RANGE(0x3003, 0x3003) AM_READ_PORT("COINS")
544		AM_RANGE(0x3000, 0x3004) AM_WRITE_LEGACY(zerotrgt_vregs_w)
545		AM_RANGE(0x3005, 0x3005) AM_WRITE_LEGACY(gekitsui_sub_irq_ack)
546		AM_RANGE(0x3007, 0x3007) AM_WRITE_LEGACY(cntsteer_sound_w)
	547	AM_RANGE(0x3000, 0x3004) AM_WRITE(zerotrgt_vregs_w)
	548	AM_RANGE(0x3005, 0x3005) AM_WRITE(gekitsui_sub_irq_ack)
	549	AM_RANGE(0x3007, 0x3007) AM_WRITE(cntsteer_sound_w)
547	550	AM_RANGE(0x4000, 0xffff) AM_ROM
548	551	ADDRESS_MAP_END
549	552
550	553	static ADDRESS_MAP_START( cntsteer_cpu1_map, AS_PROGRAM, 8, cntsteer_state )
551	554	AM_RANGE(0x0000, 0x0fff) AM_RAM AM_SHARE("share1")
552	555	AM_RANGE(0x1000, 0x11ff) AM_RAM AM_BASE(m_spriteram)
553		AM_RANGE(0x2000, 0x23ff) AM_RAM_WRITE_LEGACY(cntsteer_foreground_vram_w) AM_BASE(m_videoram)
554		AM_RANGE(0x2400, 0x27ff) AM_RAM_WRITE_LEGACY(cntsteer_foreground_attr_w) AM_BASE(m_colorram)
555		AM_RANGE(0x3000, 0x3000) AM_WRITE_LEGACY(cntsteer_sub_nmi_w)
556		AM_RANGE(0x3001, 0x3001) AM_WRITE_LEGACY(cntsteer_sub_irq_w)
	556	AM_RANGE(0x2000, 0x23ff) AM_RAM_WRITE(cntsteer_foreground_vram_w) AM_BASE(m_videoram)
	557	AM_RANGE(0x2400, 0x27ff) AM_RAM_WRITE(cntsteer_foreground_attr_w) AM_BASE(m_colorram)
	558	AM_RANGE(0x3000, 0x3000) AM_WRITE(cntsteer_sub_nmi_w)
	559	AM_RANGE(0x3001, 0x3001) AM_WRITE(cntsteer_sub_irq_w)
557	560	AM_RANGE(0x8000, 0xffff) AM_ROM
558	561	ADDRESS_MAP_END
559	562
560	563	static ADDRESS_MAP_START( cntsteer_cpu2_map, AS_PROGRAM, 8, cntsteer_state )
561	564	AM_RANGE(0x0000, 0x0fff) AM_RAM AM_SHARE("share1")
562		AM_RANGE(0x1000, 0x1fff) AM_RAM_WRITE_LEGACY(cntsteer_background_w) AM_BASE(m_videoram2) AM_SHARE("share3")
563		AM_RANGE(0x2000, 0x2fff) AM_RAM_WRITE_LEGACY(cntsteer_background_w) AM_SHARE("share3")
	565	AM_RANGE(0x1000, 0x1fff) AM_RAM_WRITE(cntsteer_background_w) AM_BASE(m_videoram2) AM_SHARE("share3")
	566	AM_RANGE(0x2000, 0x2fff) AM_RAM_WRITE(cntsteer_background_w) AM_SHARE("share3")
564	567	AM_RANGE(0x3000, 0x3000) AM_READ_PORT("DSW0")
565		AM_RANGE(0x3001, 0x3001) AM_READ_LEGACY(cntsteer_adx_r)
	568	AM_RANGE(0x3001, 0x3001) AM_READ(cntsteer_adx_r)
566	569	AM_RANGE(0x3002, 0x3002) AM_READ_PORT("P1")
567	570	AM_RANGE(0x3003, 0x3003) AM_READ_PORT("COINS")
568		AM_RANGE(0x3000, 0x3004) AM_WRITE_LEGACY(cntsteer_vregs_w)
569		AM_RANGE(0x3005, 0x3005) AM_WRITE_LEGACY(gekitsui_sub_irq_ack)
570		AM_RANGE(0x3006, 0x3006) AM_WRITE_LEGACY(cntsteer_main_irq_w)
571		AM_RANGE(0x3007, 0x3007) AM_WRITE_LEGACY(cntsteer_sound_w)
	571	AM_RANGE(0x3000, 0x3004) AM_WRITE(cntsteer_vregs_w)
	572	AM_RANGE(0x3005, 0x3005) AM_WRITE(gekitsui_sub_irq_ack)
	573	AM_RANGE(0x3006, 0x3006) AM_WRITE(cntsteer_main_irq_w)
	574	AM_RANGE(0x3007, 0x3007) AM_WRITE(cntsteer_sound_w)
572	575	AM_RANGE(0x3007, 0x3007) AM_READNOP //m6809 bug.
573	576	AM_RANGE(0x4000, 0xffff) AM_ROM
574	577	ADDRESS_MAP_END
575	578
576	579	/***************************************************************************/
577	580
578		static WRITE8_HANDLER( nmimask_w )
	581	WRITE8_MEMBER(cntsteer_state::nmimask_w)
579	582	{
580		cntsteer_state *state = space->machine().driver_data<cntsteer_state>();
581		state->m_nmimask = data & 0x80;
	583	m_nmimask = data & 0x80;
582	584	}
583	585
584	586	static INTERRUPT_GEN ( sound_interrupt )
r14845	r14846
596	598	AM_RANGE(0x6000, 0x6000) AM_DEVWRITE_LEGACY("ay2", ay8910_data_w)
597	599	AM_RANGE(0x8000, 0x8000) AM_DEVWRITE_LEGACY("ay2", ay8910_address_w)
598	600	AM_RANGE(0xa000, 0xa000) AM_READ_LEGACY(soundlatch_r)
599		AM_RANGE(0xd000, 0xd000) AM_WRITE_LEGACY(nmimask_w)
	601	AM_RANGE(0xd000, 0xd000) AM_WRITE(nmimask_w)
600	602	AM_RANGE(0xe000, 0xffff) AM_ROM
601	603	ADDRESS_MAP_END
602	604

src/mame/drivers/csplayh5.c

r14845	r14846
40	40
41	41	required_device<cpu_device> m_maincpu;
42	42	required_device<v9958_device> m_v9958;
	43	DECLARE_READ16_MEMBER(csplayh5_mux_r);
	44	DECLARE_WRITE16_MEMBER(csplayh5_mux_w);
	45	DECLARE_WRITE16_MEMBER(csplayh5_sound_w);
	46	DECLARE_READ16_MEMBER(test_r);
	47	DECLARE_READ8_MEMBER(csplayh5_sound_r);
	48	DECLARE_WRITE8_MEMBER(csplayh5_soundclr_w);
	49	DECLARE_READ8_MEMBER(tmpz84c011_pio_r);
	50	DECLARE_WRITE8_MEMBER(tmpz84c011_pio_w);
	51	DECLARE_READ8_MEMBER(tmpz84c011_0_pa_r);
	52	DECLARE_READ8_MEMBER(tmpz84c011_0_pb_r);
	53	DECLARE_READ8_MEMBER(tmpz84c011_0_pc_r);
	54	DECLARE_READ8_MEMBER(tmpz84c011_0_pd_r);
	55	DECLARE_READ8_MEMBER(tmpz84c011_0_pe_r);
	56	DECLARE_WRITE8_MEMBER(tmpz84c011_0_pa_w);
	57	DECLARE_WRITE8_MEMBER(tmpz84c011_0_pb_w);
	58	DECLARE_WRITE8_MEMBER(tmpz84c011_0_pc_w);
	59	DECLARE_WRITE8_MEMBER(tmpz84c011_0_pd_w);
	60	DECLARE_WRITE8_MEMBER(tmpz84c011_0_pe_w);
	61	DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pa_r);
	62	DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pb_r);
	63	DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pc_r);
	64	DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pd_r);
	65	DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pe_r);
	66	DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pa_w);
	67	DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pb_w);
	68	DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pc_w);
	69	DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pd_w);
	70	DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pe_w);
43	71	};
44	72
45	73
r14845	r14846
60	88	interrupts seem to be fired quite randomly */
61	89	}
62	90
63		static READ16_HANDLER( csplayh5_mux_r )
	91	READ16_MEMBER(csplayh5_state::csplayh5_mux_r)
64	92	{
65		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
66		switch(state->m_mux_data)
	93	switch(m_mux_data)
67	94	{
68		case 0x01: return input_port_read(space->machine(), "KEY0");
69		case 0x02: return input_port_read(space->machine(), "KEY1");
70		case 0x04: return input_port_read(space->machine(), "KEY2");
71		case 0x08: return input_port_read(space->machine(), "KEY3");
72		case 0x10: return input_port_read(space->machine(), "KEY4");
	95	case 0x01: return input_port_read(machine(), "KEY0");
	96	case 0x02: return input_port_read(machine(), "KEY1");
	97	case 0x04: return input_port_read(machine(), "KEY2");
	98	case 0x08: return input_port_read(machine(), "KEY3");
	99	case 0x10: return input_port_read(machine(), "KEY4");
73	100	}
74	101
75	102	return 0xffff;
76	103	}
77	104
78		static WRITE16_HANDLER( csplayh5_mux_w )
	105	WRITE16_MEMBER(csplayh5_state::csplayh5_mux_w)
79	106	{
80		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
81		state->m_mux_data = (~data & 0x1f);
	107	m_mux_data = (~data & 0x1f);
82	108	}
83	109
84		static WRITE16_HANDLER( csplayh5_sound_w )
	110	WRITE16_MEMBER(csplayh5_state::csplayh5_sound_w)
85	111	{
86	112	soundlatch_w(space, 0, ((data >> 8) & 0xff));
87	113	}
r14845	r14846
90	116	static ADDRESS_MAP_START( csplayh5_map, AS_PROGRAM, 16, csplayh5_state )
91	117	AM_RANGE(0x000000, 0x03ffff) AM_ROM
92	118
93		AM_RANGE(0x200000, 0x200001) AM_READ_PORT("DSW") AM_WRITE_LEGACY(csplayh5_sound_w)
94		AM_RANGE(0x200200, 0x200201) AM_READWRITE_LEGACY(csplayh5_mux_r,csplayh5_mux_w)
	119	AM_RANGE(0x200000, 0x200001) AM_READ_PORT("DSW") AM_WRITE(csplayh5_sound_w)
	120	AM_RANGE(0x200200, 0x200201) AM_READWRITE(csplayh5_mux_r,csplayh5_mux_w)
95	121	AM_RANGE(0x200400, 0x200401) AM_READ_PORT("SYSTEM")
96	122
97	123	AM_RANGE(0x200600, 0x200607) AM_DEVREADWRITE8("v9958", v9958_device, read, write, 0x00ff)
r14845	r14846
104	130	ADDRESS_MAP_END
105	131
106	132	#if USE_H8
107		static READ16_HANDLER( test_r )
	133	READ16_MEMBER(csplayh5_state::test_r)
108	134	{
109		return space->machine().rand();
	135	return machine().rand();
110	136	}
111	137
112	138	static ADDRESS_MAP_START( csplayh5_sub_map, AS_PROGRAM, 16, csplayh5_state )
113	139	AM_RANGE(0x000000, 0x01ffff) AM_ROM
114	140
115		AM_RANGE(0x04002a, 0x04002b) AM_READ_LEGACY(test_r)
116		AM_RANGE(0x040036, 0x040037) AM_READ_LEGACY(test_r)
	141	AM_RANGE(0x04002a, 0x04002b) AM_READ(test_r)
	142	AM_RANGE(0x040036, 0x040037) AM_READ(test_r)
117	143
118	144	AM_RANGE(0x078000, 0x07ffff) AM_RAM AM_SHARE("nvram")
119	145	AM_RANGE(0x080000, 0x0fffff) AM_RAM
r14845	r14846
146	172	memory_set_bankptr(machine, "bank1", &SNDROM[0x08000 + (0x8000 * (data & 0x03))]);
147	173	}
148	174
149		static READ8_HANDLER( csplayh5_sound_r )
	175	READ8_MEMBER(csplayh5_state::csplayh5_sound_r)
150	176	{
151	177	return soundlatch_r(space, 0);
152	178	}
153	179
154		static WRITE8_HANDLER( csplayh5_soundclr_w )
	180	WRITE8_MEMBER(csplayh5_state::csplayh5_soundclr_w)
155	181	{
156	182	soundlatch_clear_w(space, 0, 0);
157	183	}
158	184
159		static READ8_HANDLER( tmpz84c011_pio_r )
	185	READ8_MEMBER(csplayh5_state::tmpz84c011_pio_r)
160	186	{
161	187	int portdata;
162	188
r14845	r14846
179	205	break;
180	206
181	207	default:
182		logerror("%s: TMPZ84C011_PIO Unknown Port Read %02X\n", space->machine().describe_context(), offset);
	208	logerror("%s: TMPZ84C011_PIO Unknown Port Read %02X\n", machine().describe_context(), offset);
183	209	portdata = 0xff;
184	210	break;
185	211	}
r14845	r14846
187	213	return portdata;
188	214	}
189	215
190		static WRITE8_HANDLER( tmpz84c011_pio_w)
	216	WRITE8_MEMBER(csplayh5_state::tmpz84c011_pio_w)
191	217	{
192	218	switch (offset)
193	219	{
194	220	case 0:         /* PA_0 */
195		csplayh5_soundbank_w(space->machine(), data & 0x03);
	221	csplayh5_soundbank_w(machine(), data & 0x03);
196	222	break;
197	223	case 1:         /* PB_0 */
198		DAC_WRITE(space->machine().device("dac2"), 0, data);
	224	DAC_WRITE(machine().device("dac2"), 0, data);
199	225	break;
200	226	case 2:         /* PC_0 */
201		DAC_WRITE(space->machine().device("dac1"), 0, data);
	227	DAC_WRITE(machine().device("dac1"), 0, data);
202	228	break;
203	229	case 3:         /* PD_0 */
204	230	break;
r14845	r14846
207	233	break;
208	234
209	235	default:
210		logerror("%s: TMPZ84C011_PIO Unknown Port Write %02X, %02X\n", space->machine().describe_context(), offset, data);
	236	logerror("%s: TMPZ84C011_PIO Unknown Port Write %02X, %02X\n", machine().describe_context(), offset, data);
211	237	break;
212	238	}
213	239	}
214	240
215	241
216	242	/* CPU interface */
217		static READ8_HANDLER( tmpz84c011_0_pa_r )
	243	READ8_MEMBER(csplayh5_state::tmpz84c011_0_pa_r)
218	244	{
219		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
220		return (tmpz84c011_pio_r(space,0) & ~state->m_pio_dir[0]) | (state->m_pio_latch[0] & state->m_pio_dir[0]);
	245	return (tmpz84c011_pio_r(space,0) & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
221	246	}
222	247
223		static READ8_HANDLER( tmpz84c011_0_pb_r )
	248	READ8_MEMBER(csplayh5_state::tmpz84c011_0_pb_r)
224	249	{
225		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
226		return (tmpz84c011_pio_r(space,1) & ~state->m_pio_dir[1]) | (state->m_pio_latch[1] & state->m_pio_dir[1]);
	250	return (tmpz84c011_pio_r(space,1) & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
227	251	}
228	252
229		static READ8_HANDLER( tmpz84c011_0_pc_r )
	253	READ8_MEMBER(csplayh5_state::tmpz84c011_0_pc_r)
230	254	{
231		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
232		return (tmpz84c011_pio_r(space,2) & ~state->m_pio_dir[2]) | (state->m_pio_latch[2] & state->m_pio_dir[2]);
	255	return (tmpz84c011_pio_r(space,2) & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
233	256	}
234	257
235		static READ8_HANDLER( tmpz84c011_0_pd_r )
	258	READ8_MEMBER(csplayh5_state::tmpz84c011_0_pd_r)
236	259	{
237		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
238		return (tmpz84c011_pio_r(space,3) & ~state->m_pio_dir[3]) | (state->m_pio_latch[3] & state->m_pio_dir[3]);
	260	return (tmpz84c011_pio_r(space,3) & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
239	261	}
240	262
241		static READ8_HANDLER( tmpz84c011_0_pe_r )
	263	READ8_MEMBER(csplayh5_state::tmpz84c011_0_pe_r)
242	264	{
243		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
244		return (tmpz84c011_pio_r(space,4) & ~state->m_pio_dir[4]) | (state->m_pio_latch[4] & state->m_pio_dir[4]);
	265	return (tmpz84c011_pio_r(space,4) & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
245	266	}
246	267
247		static WRITE8_HANDLER( tmpz84c011_0_pa_w )
	268	WRITE8_MEMBER(csplayh5_state::tmpz84c011_0_pa_w)
248	269	{
249		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
250		state->m_pio_latch[0] = data;
	270	m_pio_latch[0] = data;
251	271	tmpz84c011_pio_w(space, 0, data);
252	272	}
253	273
254		static WRITE8_HANDLER( tmpz84c011_0_pb_w )
	274	WRITE8_MEMBER(csplayh5_state::tmpz84c011_0_pb_w)
255	275	{
256		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
257		state->m_pio_latch[1] = data;
	276	m_pio_latch[1] = data;
258	277	tmpz84c011_pio_w(space, 1, data);
259	278	}
260	279
261		static WRITE8_HANDLER( tmpz84c011_0_pc_w )
	280	WRITE8_MEMBER(csplayh5_state::tmpz84c011_0_pc_w)
262	281	{
263		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
264		state->m_pio_latch[2] = data;
	282	m_pio_latch[2] = data;
265	283	tmpz84c011_pio_w(space, 2, data);
266	284	}
267	285
268		static WRITE8_HANDLER( tmpz84c011_0_pd_w )
	286	WRITE8_MEMBER(csplayh5_state::tmpz84c011_0_pd_w)
269	287	{
270		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
271		state->m_pio_latch[3] = data;
	288	m_pio_latch[3] = data;
272	289	tmpz84c011_pio_w(space, 3, data);
273	290	}
274	291
275		static WRITE8_HANDLER( tmpz84c011_0_pe_w )
	292	WRITE8_MEMBER(csplayh5_state::tmpz84c011_0_pe_w)
276	293	{
277		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
278		state->m_pio_latch[4] = data;
	294	m_pio_latch[4] = data;
279	295	tmpz84c011_pio_w(space, 4, data);
280	296	}
281	297
282	298
283		static READ8_HANDLER( tmpz84c011_0_dir_pa_r )
	299	READ8_MEMBER(csplayh5_state::tmpz84c011_0_dir_pa_r)
284	300	{
285		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
286		return state->m_pio_dir[0];
	301	return m_pio_dir[0];
287	302	}
288	303
289		static READ8_HANDLER( tmpz84c011_0_dir_pb_r )
	304	READ8_MEMBER(csplayh5_state::tmpz84c011_0_dir_pb_r)
290	305	{
291		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
292		return state->m_pio_dir[1];
	306	return m_pio_dir[1];
293	307	}
294	308
295		static READ8_HANDLER( tmpz84c011_0_dir_pc_r )
	309	READ8_MEMBER(csplayh5_state::tmpz84c011_0_dir_pc_r)
296	310	{
297		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
298		return state->m_pio_dir[2];
	311	return m_pio_dir[2];
299	312	}
300	313
301		static READ8_HANDLER( tmpz84c011_0_dir_pd_r )
	314	READ8_MEMBER(csplayh5_state::tmpz84c011_0_dir_pd_r)
302	315	{
303		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
304		return state->m_pio_dir[3];
	316	return m_pio_dir[3];
305	317	}
306	318
307		static READ8_HANDLER( tmpz84c011_0_dir_pe_r )
	319	READ8_MEMBER(csplayh5_state::tmpz84c011_0_dir_pe_r)
308	320	{
309		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
310		return state->m_pio_dir[4];
	321	return m_pio_dir[4];
311	322	}
312	323
313	324
314		static WRITE8_HANDLER( tmpz84c011_0_dir_pa_w )
	325	WRITE8_MEMBER(csplayh5_state::tmpz84c011_0_dir_pa_w)
315	326	{
316		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
317		state->m_pio_dir[0] = data;
	327	m_pio_dir[0] = data;
318	328	}
319	329
320		static WRITE8_HANDLER( tmpz84c011_0_dir_pb_w )
	330	WRITE8_MEMBER(csplayh5_state::tmpz84c011_0_dir_pb_w)
321	331	{
322		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
323		state->m_pio_dir[1] = data;
	332	m_pio_dir[1] = data;
324	333	}
325	334
326		static WRITE8_HANDLER( tmpz84c011_0_dir_pc_w )
	335	WRITE8_MEMBER(csplayh5_state::tmpz84c011_0_dir_pc_w)
327	336	{
328		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
329		state->m_pio_dir[2] = data;
	337	m_pio_dir[2] = data;
330	338	}
331	339
332		static WRITE8_HANDLER( tmpz84c011_0_dir_pd_w )
	340	WRITE8_MEMBER(csplayh5_state::tmpz84c011_0_dir_pd_w)
333	341	{
334		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
335		state->m_pio_dir[3] = data;
	342	m_pio_dir[3] = data;
336	343	}
337	344
338		static WRITE8_HANDLER( tmpz84c011_0_dir_pe_w )
	345	WRITE8_MEMBER(csplayh5_state::tmpz84c011_0_dir_pe_w)
339	346	{
340		csplayh5_state *state = space->machine().driver_data<csplayh5_state>();
341		state->m_pio_dir[4] = data;
	347	m_pio_dir[4] = data;
342	348	}
343	349
344	350
r14845	r14846
351	357	static ADDRESS_MAP_START( csplayh5_sound_io_map, AS_IO, 8, csplayh5_state )
352	358	ADDRESS_MAP_GLOBAL_MASK(0xff)
353	359	AM_RANGE(0x10, 0x13) AM_DEVREADWRITE_LEGACY("ctc", z80ctc_r, z80ctc_w)
354		AM_RANGE(0x50, 0x50) AM_READWRITE_LEGACY(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w)
355		AM_RANGE(0x51, 0x51) AM_READWRITE_LEGACY(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w)
356		AM_RANGE(0x52, 0x52) AM_READWRITE_LEGACY(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w)
357		AM_RANGE(0x30, 0x30) AM_READWRITE_LEGACY(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w)
358		AM_RANGE(0x40, 0x40) AM_READWRITE_LEGACY(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w)
359		AM_RANGE(0x54, 0x54) AM_READWRITE_LEGACY(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w)
360		AM_RANGE(0x55, 0x55) AM_READWRITE_LEGACY(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w)
361		AM_RANGE(0x56, 0x56) AM_READWRITE_LEGACY(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w)
362		AM_RANGE(0x34, 0x34) AM_READWRITE_LEGACY(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w)
363		AM_RANGE(0x44, 0x44) AM_READWRITE_LEGACY(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w)
	360	AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w)
	361	AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w)
	362	AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w)
	363	AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w)
	364	AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w)
	365	AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w)
	366	AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w)
	367	AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w)
	368	AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w)
	369	AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w)
364	370	AM_RANGE(0x80, 0x81) AM_DEVWRITE_LEGACY("ymsnd", ym3812_w)
365	371	ADDRESS_MAP_END
366	372
r14845	r14846
576	582	for (i = 0; i < 5; i++)
577	583	{
578	584	state->m_pio_dir[i] = state->m_pio_latch[i] = 0;
579		tmpz84c011_pio_w(space, i, 0);
	585	state->tmpz84c011_pio_w(*space, i, 0);
580	586	}
581	587	}
582	588

src/mame/drivers/nexus3d.c

r14845	r14846
38	38
39	39	UINT8* m_flash_region;
40	40
	41	DECLARE_READ32_MEMBER(nexus3d_unk_r);
	42	//   DECLARE_READ32_MEMBER(nexus3d_unk2_r);
	43	//   DECLARE_READ32_MEMBER(nexus3d_unk3_r);
	44	//   DECLARE_WRITE32_MEMBER(nexus3d_unk2_w);
	45	//   DECLARE_WRITE32_MEMBER(nexus3d_unk3_w);
41	46	};
42	47
43	48
r14845	r14846
120	125
121	126	}
122	127
123		static READ32_HANDLER( nexus3d_unk_r )
	128	READ32_MEMBER(nexus3d_state::nexus3d_unk_r)
124	129	{
125		return space->machine().rand() ^ (space->machine().rand() << 16);
	130	return machine().rand() ^ (machine().rand() << 16);
126	131	}
127	132
128		//static READ32_HANDLER( nexus3d_unk2_r )
	133	//READ32_MEMBER(nexus3d_state::nexus3d_unk2_r)
129	134	//{
130		//  return 0x00000000;//space->machine().rand() ^ (space->machine().rand() << 16);
	135	//  return 0x00000000;//machine().rand() ^ (machine().rand() << 16);
131	136	//}
132	137	//
133		//static READ32_HANDLER( nexus3d_unk3_r )
	138	//READ32_MEMBER(nexus3d_state::nexus3d_unk3_r)
134	139	//{
135		//  return 0x00000000;//space->machine().rand() ^ (space->machine().rand() << 16);
	140	//  return 0x00000000;//machine().rand() ^ (machine().rand() << 16);
136	141	//}
137	142	//
138		//static WRITE32_HANDLER( nexus3d_unk2_w )
	143	//WRITE32_MEMBER(nexus3d_state::nexus3d_unk2_w)
139	144	//{
140	145	//
141	146	//}
142	147	//
143		//static WRITE32_HANDLER( nexus3d_unk3_w )
	148	//WRITE32_MEMBER(nexus3d_state::nexus3d_unk3_w)
144	149	//{
145	150	//
146	151	//}
r14845	r14846
156	161	AM_RANGE(0x9C000018, 0x9C00001b) AM_WRITE8_LEGACY(n3d_flash_addr_w, 0xffffffff)
157	162
158	163	// lots of accesses in this range
159		//  AM_RANGE(0xC0000F44, 0xC0000F47) AM_READWRITE_LEGACY(nexus3d_unk2_r, nexus3d_unk2_w ) // often
160		//  AM_RANGE(0xC0000F4C, 0xC0000F4f) AM_READWRITE_LEGACY(nexus3d_unk3_r, nexus3d_unk3_w ) // often
	164	//  AM_RANGE(0xC0000F44, 0xC0000F47) AM_READWRITE(nexus3d_unk2_r, nexus3d_unk2_w ) // often
	165	//  AM_RANGE(0xC0000F4C, 0xC0000F4f) AM_READWRITE(nexus3d_unk3_r, nexus3d_unk3_w ) // often
161	166
162		AM_RANGE(0xE0000014, 0xE0000017) AM_READ_LEGACY(nexus3d_unk_r ) // sits waiting for this
	167	AM_RANGE(0xE0000014, 0xE0000017) AM_READ(nexus3d_unk_r ) // sits waiting for this
163	168
164	169
165	170	ADDRESS_MAP_END

src/mame/drivers/skeetsht.c

r14845	r14846
30	30	UINT16 m_lastdatar;
31	31	device_t *m_ay;
32	32	device_t *m_tms;
	33	DECLARE_READ16_MEMBER(ramdac_r);
	34	DECLARE_WRITE16_MEMBER(ramdac_w);
	35	DECLARE_WRITE8_MEMBER(tms_w);
	36	DECLARE_READ8_MEMBER(tms_r);
	37	DECLARE_READ8_MEMBER(hc11_porta_r);
	38	DECLARE_WRITE8_MEMBER(hc11_porta_w);
	39	DECLARE_WRITE8_MEMBER(ay8910_w);
33	40	};
34	41
35	42
r14845	r14846
75	82	}
76	83	}
77	84
78		static READ16_HANDLER( ramdac_r )
	85	READ16_MEMBER(skeetsht_state::ramdac_r)
79	86	{
80	87	offset = (offset >> 12) & ~4;
81	88
82	89	if (offset & 8)
83	90	offset = (offset & ~8) | 4;
84	91
85		return tlc34076_r(space->machine().device("tlc34076"), offset);
	92	return tlc34076_r(machine().device("tlc34076"), offset);
86	93	}
87	94
88		static WRITE16_HANDLER( ramdac_w )
	95	WRITE16_MEMBER(skeetsht_state::ramdac_w)
89	96	{
90	97	offset = (offset >> 12) & ~4;
91	98
92	99	if (offset & 8)
93	100	offset = (offset & ~8) | 4;
94	101
95		tlc34076_w(space->machine().device("tlc34076"), offset, data);
	102	tlc34076_w(machine().device("tlc34076"), offset, data);
96	103	}
97	104
98	105
r14845	r14846
108	115	}
109	116
110	117
111		static WRITE8_HANDLER( tms_w )
	118	WRITE8_MEMBER(skeetsht_state::tms_w)
112	119	{
113		skeetsht_state *state = space->machine().driver_data<skeetsht_state>();
114	120
115	121	if ((offset & 1) == 0)
116		state->m_lastdataw = data;
	122	m_lastdataw = data;
117	123	else
118		tms34010_host_w(state->m_tms, offset >> 1, (state->m_lastdataw << 8) | data);
	124	tms34010_host_w(m_tms, offset >> 1, (m_lastdataw << 8) | data);
119	125	}
120	126
121		static READ8_HANDLER( tms_r )
	127	READ8_MEMBER(skeetsht_state::tms_r)
122	128	{
123		skeetsht_state *state = space->machine().driver_data<skeetsht_state>();
124	129
125	130	if ((offset & 1) == 0)
126		state->m_lastdatar = tms34010_host_r(state->m_tms, offset >> 1);
	131	m_lastdatar = tms34010_host_r(m_tms, offset >> 1);
127	132
128		return state->m_lastdatar >> ((offset & 1) ? 0 : 8);
	133	return m_lastdatar >> ((offset & 1) ? 0 : 8);
129	134	}
130	135
131	136
r14845	r14846
135	140	*
136	141	*************************************/
137	142
138		static READ8_HANDLER( hc11_porta_r )
	143	READ8_MEMBER(skeetsht_state::hc11_porta_r)
139	144	{
140		skeetsht_state *state = space->machine().driver_data<skeetsht_state>();
141	145
142		return state->m_porta_latch;
	146	return m_porta_latch;
143	147	}
144	148
145		static WRITE8_HANDLER( hc11_porta_w )
	149	WRITE8_MEMBER(skeetsht_state::hc11_porta_w)
146	150	{
147		skeetsht_state *state = space->machine().driver_data<skeetsht_state>();
148	151
149		if (!(data & 0x8) && (state->m_porta_latch & 8))
150		state->m_ay_sel = state->m_porta_latch & 0x10;
	152	if (!(data & 0x8) && (m_porta_latch & 8))
	153	m_ay_sel = m_porta_latch & 0x10;
151	154
152		state->m_porta_latch = data;
	155	m_porta_latch = data;
153	156	}
154	157
155		static WRITE8_HANDLER( ay8910_w )
	158	WRITE8_MEMBER(skeetsht_state::ay8910_w)
156	159	{
157		skeetsht_state *state = space->machine().driver_data<skeetsht_state>();
158	160
159		if (state->m_ay_sel)
160		ay8910_data_w(state->m_ay, 0, data);
	161	if (m_ay_sel)
	162	ay8910_data_w(m_ay, 0, data);
161	163	else
162		ay8910_address_w(state->m_ay, 0, data);
	164	ay8910_address_w(m_ay, 0, data);
163	165	}
164	166
165	167
r14845	r14846
170	172	*************************************/
171	173
172	174	static ADDRESS_MAP_START( hc11_pgm_map, AS_PROGRAM, 8, skeetsht_state )
173		AM_RANGE(0x2800, 0x2807) AM_READWRITE_LEGACY(tms_r, tms_w)
174		AM_RANGE(0x1800, 0x1800) AM_WRITE_LEGACY(ay8910_w)
	175	AM_RANGE(0x2800, 0x2807) AM_READWRITE(tms_r, tms_w)
	176	AM_RANGE(0x1800, 0x1800) AM_WRITE(ay8910_w)
175	177	AM_RANGE(0xb600, 0xbdff) AM_RAM //internal EEPROM
176	178	AM_RANGE(0x0000, 0xffff) AM_ROM AM_REGION("68hc11", 0)
177	179	ADDRESS_MAP_END
178	180
179	181	static ADDRESS_MAP_START( hc11_io_map, AS_IO, 8, skeetsht_state )
180		AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_READWRITE_LEGACY(hc11_porta_r, hc11_porta_w)
	182	AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_READWRITE(hc11_porta_r, hc11_porta_w)
181	183	ADDRESS_MAP_END
182	184
183	185
r14845	r14846
190	192	static ADDRESS_MAP_START( tms_program_map, AS_PROGRAM, 16, skeetsht_state )
191	193	AM_RANGE(0xc0000000, 0xc00001ff) AM_READWRITE_LEGACY(tms34010_io_register_r, tms34010_io_register_w)
192	194	AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_BASE(m_tms_vram)
193		AM_RANGE(0x00440000, 0x004fffff) AM_READWRITE_LEGACY(ramdac_r, ramdac_w)
	195	AM_RANGE(0x00440000, 0x004fffff) AM_READWRITE(ramdac_r, ramdac_w)
194	196	AM_RANGE(0xff800000, 0xffbfffff) AM_ROM AM_MIRROR(0x00400000) AM_REGION("tms", 0)
195	197	ADDRESS_MAP_END
196	198

src/mame/drivers/dblewing.c

r14845	r14846
75	75	device_t *m_maincpu;
76	76	device_t *m_audiocpu;
77	77	device_t *m_deco_tilegen1;
	78	DECLARE_READ16_MEMBER(dblewing_prot_r);
	79	DECLARE_WRITE16_MEMBER(dblewing_prot_w);
	80	DECLARE_READ8_MEMBER(irq_latch_r);
78	81	};
79	82
80	83	UINT16 dblwings_pri_callback(UINT16 x)
r14845	r14846
120	123	we need to log the PC of each read/write and check to
121	124	see if the code makes any of them move obvious
122	125	*/
123		static READ16_HANDLER ( dblewing_prot_r )
	126	READ16_MEMBER(dblewing_state::dblewing_prot_r)
124	127	{
125		dblewing_state *state = space->machine().driver_data<dblewing_state>();
126	128
127	129	switch (offset * 2)
128	130	{
129		case 0x16a: return state->m_boss_move;          // boss 1 movement
130		case 0x6d6: return state->m_boss_move;          // boss 1 2nd pilot
131		case 0x748: return state->m_boss_move;          // boss 1 3rd pilot
	131	case 0x16a: return m_boss_move;          // boss 1 movement
	132	case 0x6d6: return m_boss_move;          // boss 1 2nd pilot
	133	case 0x748: return m_boss_move;          // boss 1 3rd pilot
132	134
133	135	case 0x566: return 0x0009;           // boss BGM,might be a variable one (read->write to the sound latch)
134		case 0x1ea: return state->m_boss_shoot_type;    // boss 1 shoot type
135		case 0x596: return state->m_boss_3_data;         // boss 3 appearing
136		case 0x692:   return state->m_boss_4_data;
137		case 0x6b0: return state->m_boss_5_data;
138		case 0x51e: return state->m_boss_5sx_data;
139		case 0x784: return state->m_boss_6_data;
	136	case 0x1ea: return m_boss_shoot_type;    // boss 1 shoot type
	137	case 0x596: return m_boss_3_data;         // boss 3 appearing
	138	case 0x692:   return m_boss_4_data;
	139	case 0x6b0: return m_boss_5_data;
	140	case 0x51e: return m_boss_5sx_data;
	141	case 0x784: return m_boss_6_data;
140	142
141	143	case 0x330: return 0; // controls bonuses such as shoot type,bombs etc.
142		case 0x1d4: return state->m_70c_data;  //controls restart points
	144	case 0x1d4: return m_70c_data;  //controls restart points
143	145
144		case 0x0ac: return (input_port_read(space->machine(), "DSW") & 0x40) << 4;//flip screen
145		case 0x4b0: return state->m_608_data;//coinage
	146	case 0x0ac: return (input_port_read(machine(), "DSW") & 0x40) << 4;//flip screen
	147	case 0x4b0: return m_608_data;//coinage
146	148	case 0x068:
147	149	{
148		switch (input_port_read(space->machine(), "DSW") & 0x0300) //I don't know how to relationate this...
	150	switch (input_port_read(machine(), "DSW") & 0x0300) //I don't know how to relationate this...
149	151	{
150	152	case 0x0000: return 0x000;//0
151	153	case 0x0100: return 0x060;//3
r14845	r14846
153	155	case 0x0300: return 0x160;//b
154	156	}
155	157	}
156		case 0x094: return state->m_104_data;// p1 inputs select screen  OK
157		case 0x24c: return state->m_008_data;//read DSW (mirror for coinage/territory)
158		case 0x298: return input_port_read(space->machine(), "SYSTEM");//vblank
159		case 0x476: return input_port_read(space->machine(), "SYSTEM");//mirror for coins
160		case 0x506: return input_port_read(space->machine(), "DSW");
161		case 0x5d8: return state->m_406_data;
162		case 0x2b4: return input_port_read(space->machine(), "P1_P2");
163		case 0x1a8: return (input_port_read(space->machine(), "DSW") & 0x4000) >> 12;//allow continue
164		case 0x3ec: return state->m_70c_data; //score entry
165		case 0x246: return state->m_580_data; // these three controls "perfect bonus" I suppose...
166		case 0x52e: return state->m_580_data;
167		case 0x532: return state->m_580_data;
	158	case 0x094: return m_104_data;// p1 inputs select screen  OK
	159	case 0x24c: return m_008_data;//read DSW (mirror for coinage/territory)
	160	case 0x298: return input_port_read(machine(), "SYSTEM");//vblank
	161	case 0x476: return input_port_read(machine(), "SYSTEM");//mirror for coins
	162	case 0x506: return input_port_read(machine(), "DSW");
	163	case 0x5d8: return m_406_data;
	164	case 0x2b4: return input_port_read(machine(), "P1_P2");
	165	case 0x1a8: return (input_port_read(machine(), "DSW") & 0x4000) >> 12;//allow continue
	166	case 0x3ec: return m_70c_data; //score entry
	167	case 0x246: return m_580_data; // these three controls "perfect bonus" I suppose...
	168	case 0x52e: return m_580_data;
	169	case 0x532: return m_580_data;
168	170	}
169	171
170		//  printf("dblewing prot r %08x, %04x, %04x\n", cpu_get_pc(&space->device()), offset * 2, mem_mask);
	172	//  printf("dblewing prot r %08x, %04x, %04x\n", cpu_get_pc(&space.device()), offset * 2, mem_mask);
171	173
172		if ((offset*2) == 0x0f8) return 0; // state->m_080_data;
	174	if ((offset*2) == 0x0f8) return 0; // m_080_data;
173	175	if ((offset*2) == 0x104) return 0;
174	176	if ((offset*2) == 0x10e) return 0;
175		if ((offset*2) == 0x206) return 0; // state->m_70c_data;
	177	if ((offset*2) == 0x206) return 0; // m_70c_data;
176	178	if ((offset*2) == 0x25c) return 0;
177	179	if ((offset*2) == 0x284) return 0; // 3rd player 2nd boss
178	180	if ((offset*2) == 0x432) return 0; // boss on water level?
179	181	if ((offset*2) == 0x54a) return 0; // 3rd player 2nd boss
180	182	if ((offset*2) == 0x786) return 0;
181	183
182		mame_printf_debug("dblewing prot r %08x, %04x, %04x\n", cpu_get_pc(&space->device()), offset * 2, mem_mask);
	184	mame_printf_debug("dblewing prot r %08x, %04x, %04x\n", cpu_get_pc(&space.device()), offset * 2, mem_mask);
183	185
184		return 0;//space->machine().rand();
	186	return 0;//machine().rand();
185	187	}
186	188
187		static WRITE16_HANDLER( dblewing_prot_w )
	189	WRITE16_MEMBER(dblewing_state::dblewing_prot_w)
188	190	{
189		dblewing_state *state = space->machine().driver_data<dblewing_state>();
190	191
191	192	//  if (offset * 2 != 0x380)
192		//  printf("dblewing prot w %08x, %04x, %04x %04x\n", cpu_get_pc(&space->device()), offset * 2, mem_mask, data);
	193	//  printf("dblewing prot w %08x, %04x, %04x %04x\n", cpu_get_pc(&space.device()), offset * 2, mem_mask, data);
193	194
194	195	switch (offset * 2)
195	196	{
196	197	case 0x088:
197		state->m_088_data = data;
198		if(state->m_088_data == 0)          { state->m_boss_4_data = 0;    }
199		else if(state->m_088_data & 0x8000) { state->m_boss_4_data = 0x50; }
200		else                                { state->m_boss_4_data = 0x40; }
	198	m_088_data = data;
	199	if(m_088_data == 0)          { m_boss_4_data = 0;    }
	200	else if(m_088_data & 0x8000) { m_boss_4_data = 0x50; }
	201	else                                { m_boss_4_data = 0x40; }
201	202
202	203	return;
203	204
204	205	case 0x104:
205		state->m_104_data = data;
	206	m_104_data = data;
206	207	return; // p1 inputs select screen  OK
207	208
208	209	case 0x18a:
209		state->m_18a_data = data;
210		switch (state->m_18a_data)
	210	m_18a_data = data;
	211	switch (m_18a_data)
211	212	{
212		case 0x6b94: state->m_boss_5_data = 0x10; break; //initialize
213		case 0x7c68: state->m_boss_5_data = 0x60; break; //go up
214		case 0xfb1d: state->m_boss_5_data = 0x50; break;
215		case 0x977c: state->m_boss_5_data = 0x50; break;
216		case 0x8a49: state->m_boss_5_data = 0x60; break;
	213	case 0x6b94: m_boss_5_data = 0x10; break; //initialize
	214	case 0x7c68: m_boss_5_data = 0x60; break; //go up
	215	case 0xfb1d: m_boss_5_data = 0x50; break;
	216	case 0x977c: m_boss_5_data = 0x50; break;
	217	case 0x8a49: m_boss_5_data = 0x60; break;
217	218	}
218	219	return;
219	220	case 0x200:
220		state->m_200_data = data;
221		switch (state->m_200_data)
	221	m_200_data = data;
	222	switch (m_200_data)
222	223	{
223		case 0x5a19: state->m_boss_move = 1; break;
224		case 0x3b28: state->m_boss_move = 2; break;
225		case 0x1d4d: state->m_boss_move = 1; break;
	224	case 0x5a19: m_boss_move = 1; break;
	225	case 0x3b28: m_boss_move = 2; break;
	226	case 0x1d4d: m_boss_move = 1; break;
226	227	}
227		//popmessage("%04x",state->m_200_data);
	228	//popmessage("%04x",m_200_data);
228	229	return;
229	230	case 0x280:
230		state->m_280_data = data;
231		switch (state->m_280_data)
	231	m_280_data = data;
	232	switch (m_280_data)
232	233	{
233		case 0x6b94: state->m_boss_5sx_data = 0x10; break;
234		case 0x7519: state->m_boss_5sx_data = 0x60; break;
235		case 0xfc68: state->m_boss_5sx_data = 0x50; break;
236		case 0x02dd: state->m_boss_5sx_data = 0x50; break;
237		case 0x613c: state->m_boss_5sx_data = 0x50; break;
	234	case 0x6b94: m_boss_5sx_data = 0x10; break;
	235	case 0x7519: m_boss_5sx_data = 0x60; break;
	236	case 0xfc68: m_boss_5sx_data = 0x50; break;
	237	case 0x02dd: m_boss_5sx_data = 0x50; break;
	238	case 0x613c: m_boss_5sx_data = 0x50; break;
238	239	}
239		//printf("%04x\n",state->m_280_data);
	240	//printf("%04x\n",m_280_data);
240	241	return;
241	242	case 0x380: // sound write
242	243	soundlatch_w(space, 0, data & 0xff);
243		state->m_sound_irq |= 0x02;
244		device_set_input_line(state->m_audiocpu, 0, (state->m_sound_irq != 0) ? ASSERT_LINE : CLEAR_LINE);
	244	m_sound_irq |= 0x02;
	245	device_set_input_line(m_audiocpu, 0, (m_sound_irq != 0) ? ASSERT_LINE : CLEAR_LINE);
245	246	return;
246	247	case 0x384:
247		state->m_384_data = data;
248		switch(state->m_384_data)
	248	m_384_data = data;
	249	switch(m_384_data)
249	250	{
250		case 0xaa41: state->m_boss_6_data = 1; break;
251		case 0x5a97: state->m_boss_6_data = 2; break;
252		case 0xbac5: state->m_boss_6_data = 3; break;
253		case 0x0afb: state->m_boss_6_data = 4; break;
254		case 0x6a99: state->m_boss_6_data = 5; break;
255		case 0xda8f: state->m_boss_6_data = 6; break;
	251	case 0xaa41: m_boss_6_data = 1; break;
	252	case 0x5a97: m_boss_6_data = 2; break;
	253	case 0xbac5: m_boss_6_data = 3; break;
	254	case 0x0afb: m_boss_6_data = 4; break;
	255	case 0x6a99: m_boss_6_data = 5; break;
	256	case 0xda8f: m_boss_6_data = 6; break;
256	257	}
257	258	return;
258	259	case 0x38e:
259		state->m_38e_data = data;
260		switch(state->m_38e_data)
	260	m_38e_data = data;
	261	switch(m_38e_data)
261	262	{
262		case 0x6c13: state->m_boss_shoot_type = 3; break;
263		case 0xc311: state->m_boss_shoot_type = 0; break;
264		case 0x1593: state->m_boss_shoot_type = 1; break;
265		case 0xf9db: state->m_boss_shoot_type = 2; break;
266		case 0xf742: state->m_boss_shoot_type = 3; break;
	263	case 0x6c13: m_boss_shoot_type = 3; break;
	264	case 0xc311: m_boss_shoot_type = 0; break;
	265	case 0x1593: m_boss_shoot_type = 1; break;
	266	case 0xf9db: m_boss_shoot_type = 2; break;
	267	case 0xf742: m_boss_shoot_type = 3; break;
267	268
268		case 0xeff5: state->m_boss_move = 1; break;
269		case 0xd2f1: state->m_boss_move = 2; break;
270		//default:   printf("%04x\n",state->m_38e_data); break;
271		//case 0xe65a: state->m_boss_shoot_type = 0; break;
	269	case 0xeff5: m_boss_move = 1; break;
	270	case 0xd2f1: m_boss_move = 2; break;
	271	//default:   printf("%04x\n",m_38e_data); break;
	272	//case 0xe65a: m_boss_shoot_type = 0; break;
272	273	}
273	274	return;
274	275	case 0x58c: // 3rd player 1st level
275		state->m_58c_data = data;
276		if(state->m_58c_data == 0)     { state->m_boss_move = 5; }
277		else                           { state->m_boss_move = 2; }
	276	m_58c_data = data;
	277	if(m_58c_data == 0)     { m_boss_move = 5; }
	278	else                           { m_boss_move = 2; }
278	279
279	280	return;
280	281	case 0x60a:
281		state->m_60a_data = data;
282		if(state->m_60a_data & 0x8000) { state->m_boss_3_data = 2; }
283		else                           { state->m_boss_3_data = 9; }
	282	m_60a_data = data;
	283	if(m_60a_data & 0x8000) { m_boss_3_data = 2; }
	284	else                           { m_boss_3_data = 9; }
284	285
285	286	return;
286	287	case 0x580:
287		state->m_580_data = data;
	288	m_580_data = data;
288	289	return;
289	290	case 0x406:
290		state->m_406_data = data;
	291	m_406_data = data;
291	292	return;  // p2 inputs select screen  OK
292	293	}
293	294
294		//  printf("dblewing prot w %08x, %04x, %04x %04x\n", cpu_get_pc(&space->device()), offset * 2, mem_mask, data);
	295	//  printf("dblewing prot w %08x, %04x, %04x %04x\n", cpu_get_pc(&space.device()), offset * 2, mem_mask, data);
295	296
296		if ((offset * 2) == 0x008) { state->m_008_data = data; return; }
297		if ((offset * 2) == 0x080) { state->m_080_data = data; return; } // p3 3rd boss?
298		if ((offset * 2) == 0x28c) { state->m_28c_data = data; return; }
299		if ((offset * 2) == 0x408) { state->m_408_data = data; return; } // 3rd player 1st level?
300		if ((offset * 2) == 0x40e) { state->m_40e_data = data; return; } // 3rd player 2nd level?
301		if ((offset * 2) == 0x608) { state->m_608_data = data; return; }
302		if ((offset * 2) == 0x70c) { state->m_70c_data = data; return; }
303		if ((offset * 2) == 0x78a) { state->m_78a_data = data; return; }
304		if ((offset * 2) == 0x788) { state->m_788_data = data; return; }
	297	if ((offset * 2) == 0x008) { m_008_data = data; return; }
	298	if ((offset * 2) == 0x080) { m_080_data = data; return; } // p3 3rd boss?
	299	if ((offset * 2) == 0x28c) { m_28c_data = data; return; }
	300	if ((offset * 2) == 0x408) { m_408_data = data; return; } // 3rd player 1st level?
	301	if ((offset * 2) == 0x40e) { m_40e_data = data; return; } // 3rd player 2nd level?
	302	if ((offset * 2) == 0x608) { m_608_data = data; return; }
	303	if ((offset * 2) == 0x70c) { m_70c_data = data; return; }
	304	if ((offset * 2) == 0x78a) { m_78a_data = data; return; }
	305	if ((offset * 2) == 0x788) { m_788_data = data; return; }
305	306	}
306	307
307	308	static ADDRESS_MAP_START( dblewing_map, AS_PROGRAM, 16, dblewing_state )
r14845	r14846
321	322	//  AM_RANGE(0x280330, 0x280331) AM_READNOP               // sound?
322	323	//  AM_RANGE(0x280380, 0x280381) AM_WRITENOP              // sound
323	324
324		AM_RANGE(0x280000, 0x2807ff) AM_READWRITE_LEGACY(dblewing_prot_r, dblewing_prot_w)
	325	AM_RANGE(0x280000, 0x2807ff) AM_READWRITE(dblewing_prot_r, dblewing_prot_w)
325	326
326	327
327	328	AM_RANGE(0x284000, 0x284001) AM_RAM
r14845	r14846
332	333	AM_RANGE(0xff0000, 0xff3fff) AM_MIRROR(0xc000) AM_RAM
333	334	ADDRESS_MAP_END
334	335
335		static READ8_HANDLER(irq_latch_r)
	336	READ8_MEMBER(dblewing_state::irq_latch_r)
336	337	{
337		dblewing_state *state = space->machine().driver_data<dblewing_state>();
338	338
339	339	/* bit 1 of dblewing_sound_irq specifies IRQ command writes */
340		state->m_sound_irq &= ~0x02;
341		device_set_input_line(state->m_audiocpu, 0, (state->m_sound_irq != 0) ? ASSERT_LINE : CLEAR_LINE);
342		return state->m_sound_irq;
	340	m_sound_irq &= ~0x02;
	341	device_set_input_line(m_audiocpu, 0, (m_sound_irq != 0) ? ASSERT_LINE : CLEAR_LINE);
	342	return m_sound_irq;
343	343	}
344	344
345	345	static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, dblewing_state )
r14845	r14846
348	348	AM_RANGE(0xa000, 0xa001) AM_DEVREADWRITE_LEGACY("ymsnd", ym2151_status_port_r,ym2151_w)
349	349	AM_RANGE(0xb000, 0xb000) AM_DEVREADWRITE("oki", okim6295_device, read, write)
350	350	AM_RANGE(0xc000, 0xc000) AM_READ_LEGACY(soundlatch_r)
351		AM_RANGE(0xd000, 0xd000) AM_READ_LEGACY(irq_latch_r) //timing? sound latch?
	351	AM_RANGE(0xd000, 0xd000) AM_READ(irq_latch_r) //timing? sound latch?
352	352	AM_RANGE(0xf000, 0xf000) AM_DEVREADWRITE("oki", okim6295_device, read, write)
353	353	ADDRESS_MAP_END
354	354

src/mame/drivers/shougi.c

r14845	r14846
98	98	//UINT8 *m_cpu_sharedram;
99	99	//UINT8 m_cpu_sharedram_control_val;
100	100	int m_r;
	101	DECLARE_WRITE8_MEMBER(cpu_sharedram_sub_w);
	102	DECLARE_WRITE8_MEMBER(cpu_sharedram_main_w);
	103	DECLARE_READ8_MEMBER(cpu_sharedram_r);
	104	DECLARE_WRITE8_MEMBER(cpu_shared_ctrl_sub_w);
	105	DECLARE_WRITE8_MEMBER(cpu_shared_ctrl_main_w);
	106	DECLARE_WRITE8_MEMBER(shougi_watchdog_reset_w);
	107	DECLARE_WRITE8_MEMBER(shougi_mcu_halt_off_w);
	108	DECLARE_WRITE8_MEMBER(shougi_mcu_halt_on_w);
	109	DECLARE_WRITE8_MEMBER(nmi_disable_and_clear_line_w);
	110	DECLARE_WRITE8_MEMBER(nmi_enable_w);
	111	DECLARE_READ8_MEMBER(dummy_r);
101	112	};
102	113
103	114
r14845	r14846
194	205	//to do:
195	206	// add separate sharedram/r/w() for both CPUs and use control value to verify access
196	207
197		static WRITE8_HANDLER ( cpu_sharedram_sub_w )
	208	WRITE8_MEMBER(shougi_state::cpu_sharedram_sub_w)
198	209	{
199	210	if (cpu_sharedram_control_val!=0) logerror("sub CPU access to shared RAM when access set for main cpu\n");
200	211	cpu_sharedram[offset] = data;
201	212	}
202	213
203		static WRITE8_HANDLER ( cpu_sharedram_main_w )
	214	WRITE8_MEMBER(shougi_state::cpu_sharedram_main_w)
204	215	{
205	216	if (cpu_sharedram_control_val!=1) logerror("main CPU access to shared RAM when access set for sub cpu\n");
206	217	cpu_sharedram[offset] = data;
207	218	}
208	219
209		static READ8_HANDLER ( cpu_sharedram_r )
	220	READ8_MEMBER(shougi_state::cpu_sharedram_r)
210	221	{
211	222	return cpu_sharedram[offset];
212	223	}
213	224
214	225	#endif
215	226
216		static WRITE8_HANDLER ( cpu_shared_ctrl_sub_w )
	227	WRITE8_MEMBER(shougi_state::cpu_shared_ctrl_sub_w)
217	228	{
218	229	//cpu_sharedram_control_val = 0;
219	230	//logerror("cpu_sharedram_ctrl=SUB");
220	231	}
221	232
222		static WRITE8_HANDLER ( cpu_shared_ctrl_main_w )
	233	WRITE8_MEMBER(shougi_state::cpu_shared_ctrl_main_w)
223	234	{
224	235	//cpu_sharedram_control_val = 1;
225	236	//logerror("cpu_sharedram_ctrl=MAIN");
226	237	}
227	238
228		static WRITE8_HANDLER( shougi_watchdog_reset_w )
	239	WRITE8_MEMBER(shougi_state::shougi_watchdog_reset_w)
229	240	{
230	241	watchdog_reset_w(space,0,data);
231	242	}
232	243
233		static WRITE8_HANDLER( shougi_mcu_halt_off_w )
	244	WRITE8_MEMBER(shougi_state::shougi_mcu_halt_off_w)
234	245	{
235	246	/* logerror("mcu HALT OFF"); */
236		cputag_set_input_line(space->machine(), "mcu", INPUT_LINE_HALT, CLEAR_LINE);
	247	cputag_set_input_line(machine(), "mcu", INPUT_LINE_HALT, CLEAR_LINE);
237	248	}
238	249
239		static WRITE8_HANDLER( shougi_mcu_halt_on_w )
	250	WRITE8_MEMBER(shougi_state::shougi_mcu_halt_on_w)
240	251	{
241	252	/* logerror("mcu HALT ON"); */
242		cputag_set_input_line(space->machine(), "mcu", INPUT_LINE_HALT,ASSERT_LINE);
	253	cputag_set_input_line(machine(), "mcu", INPUT_LINE_HALT,ASSERT_LINE);
243	254	}
244	255
245	256
246		static WRITE8_HANDLER( nmi_disable_and_clear_line_w )
	257	WRITE8_MEMBER(shougi_state::nmi_disable_and_clear_line_w)
247	258	{
248		shougi_state *state = space->machine().driver_data<shougi_state>();
249	259
250		state->m_nmi_enabled = 0; /* disable NMIs */
	260	m_nmi_enabled = 0; /* disable NMIs */
251	261
252	262	/* NMI lines are tied together on both CPUs and connected to the LS74 /Q output */
253		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
254		cputag_set_input_line(space->machine(), "sub", INPUT_LINE_NMI, CLEAR_LINE);
	263	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
	264	cputag_set_input_line(machine(), "sub", INPUT_LINE_NMI, CLEAR_LINE);
255	265	}
256	266
257		static WRITE8_HANDLER( nmi_enable_w )
	267	WRITE8_MEMBER(shougi_state::nmi_enable_w)
258	268	{
259		shougi_state *state = space->machine().driver_data<shougi_state>();
260	269
261		state->m_nmi_enabled = 1; /* enable NMIs */
	270	m_nmi_enabled = 1; /* enable NMIs */
262	271	}
263	272
264	273	static INTERRUPT_GEN( shougi_vblank_nmi )
r14845	r14846
279	288	AM_RANGE(0x4000, 0x43ff) AM_RAM      /* 2114 x 2 (0x400 x 4bit each) */
280	289
281	290	/* 4800-480f connected to the 74LS259, A3 is data line so 4800-4807 write 0, and 4808-480f write 1 */
282		AM_RANGE(0x4800, 0x4800) AM_READ_PORT("DSW") AM_WRITE_LEGACY(cpu_shared_ctrl_sub_w)
283		AM_RANGE(0x4801, 0x4801) AM_WRITE_LEGACY(nmi_disable_and_clear_line_w)
	291	AM_RANGE(0x4800, 0x4800) AM_READ_PORT("DSW") AM_WRITE(cpu_shared_ctrl_sub_w)
	292	AM_RANGE(0x4801, 0x4801) AM_WRITE(nmi_disable_and_clear_line_w)
284	293	AM_RANGE(0x4802, 0x4802) AM_NOP
285	294	AM_RANGE(0x4803, 0x4803) AM_NOP
286		AM_RANGE(0x4804, 0x4804) AM_WRITE_LEGACY(shougi_mcu_halt_off_w)
	295	AM_RANGE(0x4804, 0x4804) AM_WRITE(shougi_mcu_halt_off_w)
287	296	AM_RANGE(0x4807, 0x4807) AM_WRITENOP   //?????? connected to +5v via resistor
288		AM_RANGE(0x4808, 0x4808) AM_WRITE_LEGACY(cpu_shared_ctrl_main_w)
289		AM_RANGE(0x4809, 0x4809) AM_WRITE_LEGACY(nmi_enable_w)
	297	AM_RANGE(0x4808, 0x4808) AM_WRITE(cpu_shared_ctrl_main_w)
	298	AM_RANGE(0x4809, 0x4809) AM_WRITE(nmi_enable_w)
290	299	AM_RANGE(0x480a, 0x480a) AM_NOP
291	300	AM_RANGE(0x480b, 0x480b) AM_NOP
292		AM_RANGE(0x480c, 0x480c) AM_WRITE_LEGACY(shougi_mcu_halt_on_w)
	301	AM_RANGE(0x480c, 0x480c) AM_WRITE(shougi_mcu_halt_on_w)
293	302	AM_RANGE(0x480f, 0x480f) AM_NOP
294	303
295	304	AM_RANGE(0x5000, 0x5000) AM_READ_PORT("P1")
296		AM_RANGE(0x5800, 0x5800) AM_READ_PORT("P2") AM_WRITE_LEGACY(shougi_watchdog_reset_w)   /* game won't boot if watchdog doesn't work */
	305	AM_RANGE(0x5800, 0x5800) AM_READ_PORT("P2") AM_WRITE(shougi_watchdog_reset_w)   /* game won't boot if watchdog doesn't work */
297	306	AM_RANGE(0x6000, 0x6000) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
298	307	AM_RANGE(0x6800, 0x6800) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
299	308	AM_RANGE(0x7000, 0x73ff) AM_RAM AM_SHARE("share1") /* 2114 x 2 (0x400 x 4bit each) */
r14845	r14846
303	312	ADDRESS_MAP_END
304	313
305	314	/* sub */
306		static READ8_HANDLER ( dummy_r )
	315	READ8_MEMBER(shougi_state::dummy_r)
307	316	{
308		shougi_state *state = space->machine().driver_data<shougi_state>();
309		state->m_r ^= 1;
	317	m_r ^= 1;
310	318
311		if(state->m_r)
	319	if(m_r)
312	320	return 0xff;
313	321	else
314	322	return 0;
r14845	r14846
316	324
317	325	static ADDRESS_MAP_START( readport_sub, AS_IO, 8, shougi_state )
318	326	ADDRESS_MAP_GLOBAL_MASK( 0x00ff )
319		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(dummy_r)
	327	AM_RANGE(0x00, 0x00) AM_READ(dummy_r)
320	328	ADDRESS_MAP_END
321	329
322	330	static ADDRESS_MAP_START( sub_map, AS_PROGRAM, 8, shougi_state )

src/mame/drivers/hornet.c

r14845	r14846
339	339	UINT16 m_gn680_latch;
340	340	UINT16 m_gn680_ret0;
341	341	UINT16 m_gn680_ret1;
	342	DECLARE_READ32_MEMBER(hornet_k037122_sram_r);
	343	DECLARE_WRITE32_MEMBER(hornet_k037122_sram_w);
	344	DECLARE_READ32_MEMBER(hornet_k037122_char_r);
	345	DECLARE_WRITE32_MEMBER(hornet_k037122_char_w);
	346	DECLARE_READ32_MEMBER(hornet_k037122_reg_r);
	347	DECLARE_WRITE32_MEMBER(hornet_k037122_reg_w);
	348	DECLARE_READ8_MEMBER(sysreg_r);
	349	DECLARE_WRITE8_MEMBER(sysreg_w);
	350	DECLARE_WRITE32_MEMBER(comm1_w);
	351	DECLARE_WRITE32_MEMBER(comm_rombank_w);
	352	DECLARE_READ32_MEMBER(comm0_unk_r);
	353	DECLARE_READ32_MEMBER(gun_r);
	354	DECLARE_WRITE32_MEMBER(gun_w);
	355	DECLARE_WRITE16_MEMBER(gn680_sysctrl);
	356	DECLARE_READ16_MEMBER(gn680_latch_r);
	357	DECLARE_WRITE16_MEMBER(gn680_latch_w);
	358	DECLARE_READ32_MEMBER(dsp_dataram0_r);
	359	DECLARE_WRITE32_MEMBER(dsp_dataram0_w);
	360	DECLARE_READ32_MEMBER(dsp_dataram1_r);
	361	DECLARE_WRITE32_MEMBER(dsp_dataram1_w);
342	362	};
343	363
344	364
345	365
346	366
347		static READ32_HANDLER( hornet_k037122_sram_r )
	367	READ32_MEMBER(hornet_state::hornet_k037122_sram_r)
348	368	{
349		device_t *k037122 = space->machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
	369	device_t *k037122 = machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
350	370	return k037122_sram_r(k037122, offset, mem_mask);
351	371	}
352	372
353		static WRITE32_HANDLER( hornet_k037122_sram_w )
	373	WRITE32_MEMBER(hornet_state::hornet_k037122_sram_w)
354	374	{
355		device_t *k037122 = space->machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
	375	device_t *k037122 = machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
356	376	k037122_sram_w(k037122, offset, data, mem_mask);
357	377	}
358	378
359	379
360		static READ32_HANDLER( hornet_k037122_char_r )
	380	READ32_MEMBER(hornet_state::hornet_k037122_char_r)
361	381	{
362		device_t *k037122 = space->machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
	382	device_t *k037122 = machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
363	383	return k037122_char_r(k037122, offset, mem_mask);
364	384	}
365	385
366		static WRITE32_HANDLER( hornet_k037122_char_w )
	386	WRITE32_MEMBER(hornet_state::hornet_k037122_char_w)
367	387	{
368		device_t *k037122 = space->machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
	388	device_t *k037122 = machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
369	389	k037122_char_w(k037122, offset, data, mem_mask);
370	390	}
371	391
372		static READ32_HANDLER( hornet_k037122_reg_r )
	392	READ32_MEMBER(hornet_state::hornet_k037122_reg_r)
373	393	{
374		device_t *k037122 = space->machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
	394	device_t *k037122 = machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
375	395	return k037122_reg_r(k037122, offset, mem_mask);
376	396	}
377	397
378		static WRITE32_HANDLER( hornet_k037122_reg_w )
	398	WRITE32_MEMBER(hornet_state::hornet_k037122_reg_w)
379	399	{
380		device_t *k037122 = space->machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
	400	device_t *k037122 = machine().device(get_cgboard_id() ? "k037122_2" : "k037122_1");
381	401	k037122_reg_w(k037122, offset, data, mem_mask);
382	402	}
383	403
r14845	r14846
435	455
436	456	/*****************************************************************************/
437	457
438		static READ8_HANDLER( sysreg_r )
	458	READ8_MEMBER(hornet_state::sysreg_r)
439	459	{
440	460	UINT8 r = 0;
441	461	static const char *const portnames[] = { "IN0", "IN1", "IN2" };
442		device_t *adc12138 = space->machine().device("adc12138");
443		eeprom_device *eeprom = space->machine().device<eeprom_device>("eeprom");
	462	device_t *adc12138 = machine().device("adc12138");
	463	eeprom_device *eeprom = machine().device<eeprom_device>("eeprom");
444	464
445	465	switch (offset)
446	466	{
447	467	case 0:   /* I/O port 0 */
448	468	case 1:   /* I/O port 1 */
449	469	case 2:   /* I/O port 2 */
450		r = input_port_read(space->machine(), portnames[offset]);
	470	r = input_port_read(machine(), portnames[offset]);
451	471	break;
452	472
453	473	case 3:   /* I/O port 3 */
r14845	r14846
465	485	break;
466	486
467	487	case 4:   /* I/O port 4 - DIP switches */
468		r = input_port_read(space->machine(), "DSW");
	488	r = input_port_read(machine(), "DSW");
469	489	break;
470	490	}
471	491	return r;
472	492	}
473	493
474		static WRITE8_HANDLER( sysreg_w )
	494	WRITE8_MEMBER(hornet_state::sysreg_w)
475	495	{
476		hornet_state *state = space->machine().driver_data<hornet_state>();
477		device_t *adc12138 = space->machine().device("adc12138");
	496	device_t *adc12138 = machine().device("adc12138");
478	497
479	498	switch (offset)
480	499	{
481	500	case 0:   /* LED Register 0 */
482		state->m_led_reg0 = data;
	501	m_led_reg0 = data;
483	502	break;
484	503
485	504	case 1:   /* LED Register 1 */
486		state->m_led_reg1 = data;
	505	m_led_reg1 = data;
487	506	break;
488	507
489	508	case 2: /* Parallel data register */
r14845	r14846
501	520	0x02 = LAMP1
502	521	0x01 = LAMP0
503	522	*/
504		input_port_write(space->machine(), "EEPROMOUT", data, 0xff);
	523	input_port_write(machine(), "EEPROMOUT", data, 0xff);
505	524	mame_printf_debug("System register 0 = %02X\n", data);
506	525	break;
507	526
r14845	r14846
521	540	adc1213x_di_w(adc12138, 0, (data >> 1) & 0x1);
522	541	adc1213x_sclk_w(adc12138, 0, data & 0x1);
523	542
524		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_RESET, (data & 0x80) ? CLEAR_LINE : ASSERT_LINE);
	543	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_RESET, (data & 0x80) ? CLEAR_LINE : ASSERT_LINE);
525	544	mame_printf_debug("System register 1 = %02X\n", data);
526	545	break;
527	546
r14845	r14846
544	563	0x80 = WDTCLK
545	564	*/
546	565	if (data & 0x80)
547		watchdog_reset(space->machine());
	566	watchdog_reset(machine());
548	567	break;
549	568
550	569	case 7:   /* CG Control Register */
r14845	r14846
556	575	0x01 = EXRGB
557	576	*/
558	577	if (data & 0x80)
559		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ1, CLEAR_LINE);
	578	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ1, CLEAR_LINE);
560	579	if (data & 0x40)
561		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
	580	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
562	581	set_cgboard_id((data >> 4) & 3);
563	582	break;
564	583	}
r14845	r14846
566	585
567	586	/*****************************************************************************/
568	587
569		static WRITE32_HANDLER( comm1_w )
	588	WRITE32_MEMBER(hornet_state::comm1_w)
570	589	{
571	590	printf("comm1_w: %08X, %08X, %08X\n", offset, data, mem_mask);
572	591	}
573	592
574		static WRITE32_HANDLER( comm_rombank_w )
	593	WRITE32_MEMBER(hornet_state::comm_rombank_w)
575	594	{
576	595	int bank = data >> 24;
577		UINT8 *usr3 = space->machine().region("user3")->base();
	596	UINT8 *usr3 = machine().region("user3")->base();
578	597	if (usr3 != NULL)
579		memory_set_bank(space->machine(), "bank1", bank & 0x7f);
	598	memory_set_bank(machine(), "bank1", bank & 0x7f);
580	599	}
581	600
582		static READ32_HANDLER( comm0_unk_r )
	601	READ32_MEMBER(hornet_state::comm0_unk_r)
583	602	{
584	603	//  printf("comm0_unk_r: %08X, %08X\n", offset, mem_mask);
585	604	return 0xffffffff;
586	605	}
587	606
588	607
589		static READ32_HANDLER(gun_r)
	608	READ32_MEMBER(hornet_state::gun_r)
590	609	{
591		hornet_state *state = space->machine().driver_data<hornet_state>();
592		return state->m_gn680_ret0<<16 | state->m_gn680_ret1;
	610	return m_gn680_ret0<<16 | m_gn680_ret1;
593	611	}
594	612
595		static WRITE32_HANDLER(gun_w)
	613	WRITE32_MEMBER(hornet_state::gun_w)
596	614	{
597		hornet_state *state = space->machine().driver_data<hornet_state>();
598	615	if (mem_mask == 0xffff0000)
599	616	{
600		state->m_gn680_latch = data>>16;
601		cputag_set_input_line(space->machine(), "gn680", M68K_IRQ_6, HOLD_LINE);
	617	m_gn680_latch = data>>16;
	618	cputag_set_input_line(machine(), "gn680", M68K_IRQ_6, HOLD_LINE);
602	619	}
603	620	}
604	621
r14845	r14846
606	623
607	624	static ADDRESS_MAP_START( hornet_map, AS_PROGRAM, 32, hornet_state )
608	625	AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_BASE(m_workram)      /* Work RAM */
609		AM_RANGE(0x74000000, 0x740000ff) AM_READWRITE_LEGACY(hornet_k037122_reg_r, hornet_k037122_reg_w)
610		AM_RANGE(0x74020000, 0x7403ffff) AM_READWRITE_LEGACY(hornet_k037122_sram_r, hornet_k037122_sram_w)
611		AM_RANGE(0x74040000, 0x7407ffff) AM_READWRITE_LEGACY(hornet_k037122_char_r, hornet_k037122_char_w)
612		AM_RANGE(0x74080000, 0x7408000f) AM_READWRITE_LEGACY(gun_r, gun_w)
	626	AM_RANGE(0x74000000, 0x740000ff) AM_READWRITE(hornet_k037122_reg_r, hornet_k037122_reg_w)
	627	AM_RANGE(0x74020000, 0x7403ffff) AM_READWRITE(hornet_k037122_sram_r, hornet_k037122_sram_w)
	628	AM_RANGE(0x74040000, 0x7407ffff) AM_READWRITE(hornet_k037122_char_r, hornet_k037122_char_w)
	629	AM_RANGE(0x74080000, 0x7408000f) AM_READWRITE(gun_r, gun_w)
613	630	AM_RANGE(0x78000000, 0x7800ffff) AM_READWRITE_LEGACY(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc)
614	631	AM_RANGE(0x780c0000, 0x780c0003) AM_READWRITE_LEGACY(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc)
615		AM_RANGE(0x7d000000, 0x7d00ffff) AM_READ8_LEGACY(sysreg_r, 0xffffffff)
616		AM_RANGE(0x7d010000, 0x7d01ffff) AM_WRITE8_LEGACY(sysreg_w, 0xffffffff)
	632	AM_RANGE(0x7d000000, 0x7d00ffff) AM_READ8(sysreg_r, 0xffffffff)
	633	AM_RANGE(0x7d010000, 0x7d01ffff) AM_WRITE8(sysreg_w, 0xffffffff)
617	634	AM_RANGE(0x7d020000, 0x7d021fff) AM_DEVREADWRITE8_LEGACY("m48t58", timekeeper_r, timekeeper_w, 0xffffffff)   /* M48T58Y RTC/NVRAM */
618	635	AM_RANGE(0x7d030000, 0x7d030007) AM_DEVREADWRITE_LEGACY("k056800", k056800_host_r, k056800_host_w)
619	636	AM_RANGE(0x7d042000, 0x7d043fff) AM_RAM            /* COMM BOARD 0 */
620		AM_RANGE(0x7d044000, 0x7d044007) AM_READ_LEGACY(comm0_unk_r)
621		AM_RANGE(0x7d048000, 0x7d048003) AM_WRITE_LEGACY(comm1_w)
622		AM_RANGE(0x7d04a000, 0x7d04a003) AM_WRITE_LEGACY(comm_rombank_w)
	637	AM_RANGE(0x7d044000, 0x7d044007) AM_READ(comm0_unk_r)
	638	AM_RANGE(0x7d048000, 0x7d048003) AM_WRITE(comm1_w)
	639	AM_RANGE(0x7d04a000, 0x7d04a003) AM_WRITE(comm_rombank_w)
623	640	AM_RANGE(0x7d050000, 0x7d05ffff) AM_ROMBANK("bank1")      /* COMM BOARD 1 */
624	641	AM_RANGE(0x7e000000, 0x7e7fffff) AM_ROM AM_REGION("user2", 0)      /* Data ROM */
625	642	AM_RANGE(0x7f000000, 0x7f3fffff) AM_ROM AM_SHARE("share2")
r14845	r14846
641	658
642	659	/*****************************************************************************/
643	660
644		static WRITE16_HANDLER(gn680_sysctrl)
	661	WRITE16_MEMBER(hornet_state::gn680_sysctrl)
645	662	{
646	663	// bit 15 = watchdog toggle
647	664	// lower 4 bits = LEDs?
648	665	}
649	666
650		static READ16_HANDLER(gn680_latch_r)
	667	READ16_MEMBER(hornet_state::gn680_latch_r)
651	668	{
652		hornet_state *state = space->machine().driver_data<hornet_state>();
653		cputag_set_input_line(space->machine(), "gn680", M68K_IRQ_6, CLEAR_LINE);
	669	cputag_set_input_line(machine(), "gn680", M68K_IRQ_6, CLEAR_LINE);
654	670
655		return state->m_gn680_latch;
	671	return m_gn680_latch;
656	672	}
657	673
658		static WRITE16_HANDLER(gn680_latch_w)
	674	WRITE16_MEMBER(hornet_state::gn680_latch_w)
659	675	{
660		hornet_state *state = space->machine().driver_data<hornet_state>();
661	676	if (offset)
662	677	{
663		state->m_gn680_ret1 = data;
	678	m_gn680_ret1 = data;
664	679	}
665	680	else
666	681	{
667		state->m_gn680_ret0 = data;
	682	m_gn680_ret0 = data;
668	683	}
669	684	}
670	685
r14845	r14846
674	689	static ADDRESS_MAP_START( gn680_memmap, AS_PROGRAM, 16, hornet_state )
675	690	AM_RANGE(0x000000, 0x01ffff) AM_ROM
676	691	AM_RANGE(0x200000, 0x203fff) AM_RAM
677		AM_RANGE(0x300000, 0x300001) AM_WRITE_LEGACY(gn680_sysctrl)
	692	AM_RANGE(0x300000, 0x300001) AM_WRITE(gn680_sysctrl)
678	693	AM_RANGE(0x314000, 0x317fff) AM_RAM
679		AM_RANGE(0x400000, 0x400003) AM_READWRITE_LEGACY(gn680_latch_r, gn680_latch_w)
	694	AM_RANGE(0x400000, 0x400003) AM_READWRITE(gn680_latch_r, gn680_latch_w)
680	695	AM_RANGE(0x400008, 0x400009) AM_WRITENOP   // writes 0001 00fe each time IRQ 6 triggers
681	696	ADDRESS_MAP_END
682	697
683	698	/*****************************************************************************/
684	699
685		static READ32_HANDLER( dsp_dataram0_r )
	700	READ32_MEMBER(hornet_state::dsp_dataram0_r)
686	701	{
687		hornet_state *state = space->machine().driver_data<hornet_state>();
688		return state->m_sharc_dataram[0][offset] & 0xffff;
	702	return m_sharc_dataram[0][offset] & 0xffff;
689	703	}
690	704
691		static WRITE32_HANDLER( dsp_dataram0_w )
	705	WRITE32_MEMBER(hornet_state::dsp_dataram0_w)
692	706	{
693		hornet_state *state = space->machine().driver_data<hornet_state>();
694		state->m_sharc_dataram[0][offset] = data;
	707	m_sharc_dataram[0][offset] = data;
695	708	}
696	709
697		static READ32_HANDLER( dsp_dataram1_r )
	710	READ32_MEMBER(hornet_state::dsp_dataram1_r)
698	711	{
699		hornet_state *state = space->machine().driver_data<hornet_state>();
700		return state->m_sharc_dataram[1][offset] & 0xffff;
	712	return m_sharc_dataram[1][offset] & 0xffff;
701	713	}
702	714
703		static WRITE32_HANDLER( dsp_dataram1_w )
	715	WRITE32_MEMBER(hornet_state::dsp_dataram1_w)
704	716	{
705		hornet_state *state = space->machine().driver_data<hornet_state>();
706		state->m_sharc_dataram[1][offset] = data;
	717	m_sharc_dataram[1][offset] = data;
707	718	}
708	719
709	720	static ADDRESS_MAP_START( sharc0_map, AS_DATA, 32, hornet_state )
710	721	AM_RANGE(0x0400000, 0x041ffff) AM_READWRITE_LEGACY(cgboard_0_shared_sharc_r, cgboard_0_shared_sharc_w)
711		AM_RANGE(0x0500000, 0x05fffff) AM_READWRITE_LEGACY(dsp_dataram0_r, dsp_dataram0_w) AM_BASE(m_sharc_dataram[0])
	722	AM_RANGE(0x0500000, 0x05fffff) AM_READWRITE(dsp_dataram0_r, dsp_dataram0_w) AM_BASE(m_sharc_dataram[0])
712	723	AM_RANGE(0x1400000, 0x14fffff) AM_RAM
713	724	AM_RANGE(0x2400000, 0x27fffff) AM_DEVREADWRITE_LEGACY("voodoo0", voodoo_r, voodoo_w)
714	725	AM_RANGE(0x3400000, 0x34000ff) AM_READWRITE_LEGACY(cgboard_0_comm_sharc_r, cgboard_0_comm_sharc_w)
r14845	r14846
718	729
719	730	static ADDRESS_MAP_START( sharc1_map, AS_DATA, 32, hornet_state )
720	731	AM_RANGE(0x0400000, 0x041ffff) AM_READWRITE_LEGACY(cgboard_1_shared_sharc_r, cgboard_1_shared_sharc_w)
721		AM_RANGE(0x0500000, 0x05fffff) AM_READWRITE_LEGACY(dsp_dataram1_r, dsp_dataram1_w) AM_BASE(m_sharc_dataram[1])
	732	AM_RANGE(0x0500000, 0x05fffff) AM_READWRITE(dsp_dataram1_r, dsp_dataram1_w) AM_BASE(m_sharc_dataram[1])
722	733	AM_RANGE(0x1400000, 0x14fffff) AM_RAM
723	734	AM_RANGE(0x2400000, 0x27fffff) AM_DEVREADWRITE_LEGACY("voodoo1", voodoo_r, voodoo_w)
724	735	AM_RANGE(0x3400000, 0x34000ff) AM_READWRITE_LEGACY(cgboard_1_comm_sharc_r, cgboard_1_comm_sharc_w)

src/mame/drivers/hotstuff.c

r14845	r14846
15	15	{
16	16	UINT8 index;
17	17	}m_ioboard;
	18	DECLARE_READ8_MEMBER(ioboard_status_r);
	19	DECLARE_READ8_MEMBER(ioboard_unk_r);
	20	DECLARE_WRITE8_MEMBER(ioboard_data_w);
	21	DECLARE_WRITE8_MEMBER(ioboard_reg_w);
18	22	};
19	23
20	24
r14845	r14846
67	71	}
68	72
69	73	/* TODO: identify this ... */
70		static READ8_HANDLER( ioboard_status_r )
	74	READ8_MEMBER(hotstuff_state::ioboard_status_r)
71	75	{
72		hotstuff_state *state = space->machine().driver_data<hotstuff_state>();
73	76	UINT8 res;
74	77
75	78	printf("STATUS R\n");
76	79
77		switch(state->m_ioboard.index)
	80	switch(m_ioboard.index)
78	81	{
79	82	case 0x0c: res = 0x80|0x10; break;
80		default: res = 0; break;//space->machine().rand(); break;
	83	default: res = 0; break;//machine().rand(); break;
81	84	}
82	85
83	86	return res;
84	87	}
85	88
86		static READ8_HANDLER( ioboard_unk_r )
	89	READ8_MEMBER(hotstuff_state::ioboard_unk_r)
87	90	{
88	91	printf("UNK R\n");
89	92
90	93	return 0xff;
91	94	}
92	95
93		static WRITE8_HANDLER( ioboard_data_w )
	96	WRITE8_MEMBER(hotstuff_state::ioboard_data_w)
94	97	{
95	98	printf("DATA %02x\n",data);
96	99	}
97	100
98		static WRITE8_HANDLER( ioboard_reg_w )
	101	WRITE8_MEMBER(hotstuff_state::ioboard_reg_w)
99	102	{
100		hotstuff_state *state = space->machine().driver_data<hotstuff_state>();
101	103
102		state->m_ioboard.index = data;
	104	m_ioboard.index = data;
103	105	printf("REG %02x\n",data);
104	106	}
105	107
r14845	r14846
109	111
110	112	AM_RANGE(0x400000, 0x40ffff) AM_RAM
111	113
112		AM_RANGE(0x680000, 0x680001) AM_READWRITE8_LEGACY(ioboard_status_r,ioboard_data_w,0xff00)
113		AM_RANGE(0x680000, 0x680001) AM_READWRITE8_LEGACY(ioboard_unk_r,ioboard_reg_w,0x00ff)
	114	AM_RANGE(0x680000, 0x680001) AM_READWRITE8(ioboard_status_r,ioboard_data_w,0xff00)
	115	AM_RANGE(0x680000, 0x680001) AM_READWRITE8(ioboard_unk_r,ioboard_reg_w,0x00ff)
114	116
115	117	AM_RANGE(0x980000, 0x9bffff) AM_RAM AM_BASE(m_bitmapram)
116	118	ADDRESS_MAP_END

src/mame/drivers/discoboy.c

r14845	r14846
68	68	UINT8    m_ram_3[0x1000];
69	69	UINT8    m_ram_4[0x1000];
70	70	UINT8    m_ram_att[0x800];
	71	DECLARE_WRITE8_MEMBER(rambank_select_w);
	72	DECLARE_WRITE8_MEMBER(discoboy_port_00_w);
	73	DECLARE_WRITE8_MEMBER(discoboy_port_01_w);
	74	DECLARE_WRITE8_MEMBER(discoboy_port_03_w);
	75	DECLARE_WRITE8_MEMBER(discoboy_port_06_w);
	76	DECLARE_WRITE8_MEMBER(rambank_w);
	77	DECLARE_READ8_MEMBER(rambank_r);
	78	DECLARE_READ8_MEMBER(rambank2_r);
	79	DECLARE_WRITE8_MEMBER(rambank2_w);
	80	DECLARE_READ8_MEMBER(discoboy_ram_att_r);
	81	DECLARE_WRITE8_MEMBER(discoboy_ram_att_w);
	82	DECLARE_READ8_MEMBER(discoboy_port_06_r);
	83	DECLARE_WRITE8_MEMBER(yunsung8_adpcm_w);
71	84	};
72	85
73	86
r14845	r14846
192	205	}
193	206	#endif
194	207
195		static WRITE8_HANDLER( rambank_select_w )
	208	WRITE8_MEMBER(discoboy_state::rambank_select_w)
196	209	{
197		discoboy_state *state = space->machine().driver_data<discoboy_state>();
198		state->m_ram_bank = data;
	210	m_ram_bank = data;
199	211	if (data &= 0x83) logerror("rambank_select_w !!!!!");
200	212	}
201	213
202		static WRITE8_HANDLER( discoboy_port_00_w )
	214	WRITE8_MEMBER(discoboy_state::discoboy_port_00_w)
203	215	{
204		discoboy_state *state = space->machine().driver_data<discoboy_state>();
205	216	if (data & 0xfe) logerror("unk discoboy_port_00_w %02x\n",data);
206		state->m_port_00 = data;
	217	m_port_00 = data;
207	218	}
208	219
209		static WRITE8_HANDLER( discoboy_port_01_w )
	220	WRITE8_MEMBER(discoboy_state::discoboy_port_01_w)
210	221	{
211		discoboy_state *state = space->machine().driver_data<discoboy_state>();
212	222
213	223	// 00 10 20 30 during gameplay  1,2,3 other times?? title screen bit 0x40 toggle
214	224	//printf("unk discoboy_port_01_w %02x\n",data);
215	225	// discoboy gfxbank
216		state->m_gfxbank = data & 0xf0;
	226	m_gfxbank = data & 0xf0;
217	227
218		memory_set_bank(space->machine(), "bank1", data & 0x07);
	228	memory_set_bank(machine(), "bank1", data & 0x07);
219	229	}
220	230
221		static WRITE8_HANDLER( discoboy_port_03_w ) // sfx? (to sound cpu)
	231	WRITE8_MEMBER(discoboy_state::discoboy_port_03_w)// sfx? (to sound cpu)
222	232	{
223		discoboy_state *state = space->machine().driver_data<discoboy_state>();
224	233	//  printf("unk discoboy_port_03_w %02x\n", data);
225		//  device_set_input_line(state->m_audiocpu, INPUT_LINE_NMI, HOLD_LINE);
	234	//  device_set_input_line(m_audiocpu, INPUT_LINE_NMI, HOLD_LINE);
226	235	soundlatch_w(space, 0, data);
227		device_set_input_line(state->m_audiocpu, 0, HOLD_LINE);
	236	device_set_input_line(m_audiocpu, 0, HOLD_LINE);
228	237	}
229	238
230		static WRITE8_HANDLER( discoboy_port_06_w )
	239	WRITE8_MEMBER(discoboy_state::discoboy_port_06_w)
231	240	{
232	241	//printf("unk discoboy_port_06_w %02x\n",data);
233	242	if (data != 0) logerror("port 06!!!! %02x\n",data);
234	243	}
235	244
236	245
237		static WRITE8_HANDLER( rambank_w )
	246	WRITE8_MEMBER(discoboy_state::rambank_w)
238	247	{
239		discoboy_state *state = space->machine().driver_data<discoboy_state>();
240	248
241		if (state->m_ram_bank & 0x20)
242		state->m_ram_2[offset] = data;
	249	if (m_ram_bank & 0x20)
	250	m_ram_2[offset] = data;
243	251	else
244		state->m_ram_1[offset] = data;
	252	m_ram_1[offset] = data;
245	253	}
246	254
247		static READ8_HANDLER( rambank_r )
	255	READ8_MEMBER(discoboy_state::rambank_r)
248	256	{
249		discoboy_state *state = space->machine().driver_data<discoboy_state>();
250	257
251		if (state->m_ram_bank & 0x20)
252		return state->m_ram_2[offset];
	258	if (m_ram_bank & 0x20)
	259	return m_ram_2[offset];
253	260	else
254		return state->m_ram_1[offset];
	261	return m_ram_1[offset];
255	262	}
256	263
257		static READ8_HANDLER( rambank2_r )
	264	READ8_MEMBER(discoboy_state::rambank2_r)
258	265	{
259		discoboy_state *state = space->machine().driver_data<discoboy_state>();
260	266
261		if (state->m_port_00 == 0x00)
262		return state->m_ram_3[offset];
263		else if (state->m_port_00 == 0x01)
264		return state->m_ram_4[offset];
	267	if (m_port_00 == 0x00)
	268	return m_ram_3[offset];
	269	else if (m_port_00 == 0x01)
	270	return m_ram_4[offset];
265	271	else
266	272	printf("unk rb2_r\n");
267	273
268		return space->machine().rand();
	274	return machine().rand();
269	275	}
270	276
271		static WRITE8_HANDLER( rambank2_w )
	277	WRITE8_MEMBER(discoboy_state::rambank2_w)
272	278	{
273		discoboy_state *state = space->machine().driver_data<discoboy_state>();
274	279
275		if (state->m_port_00 == 0x00)
276		state->m_ram_3[offset] = data;
277		else if (state->m_port_00 == 0x01)
278		state->m_ram_4[offset] = data;
	280	if (m_port_00 == 0x00)
	281	m_ram_3[offset] = data;
	282	else if (m_port_00 == 0x01)
	283	m_ram_4[offset] = data;
279	284	else
280	285	printf("unk rb2_w\n");
281	286	}
282	287
283		static READ8_HANDLER( discoboy_ram_att_r )
	288	READ8_MEMBER(discoboy_state::discoboy_ram_att_r)
284	289	{
285		discoboy_state *state = space->machine().driver_data<discoboy_state>();
286		return state->m_ram_att[offset];
	290	return m_ram_att[offset];
287	291	}
288	292
289		static WRITE8_HANDLER( discoboy_ram_att_w )
	293	WRITE8_MEMBER(discoboy_state::discoboy_ram_att_w)
290	294	{
291		discoboy_state *state = space->machine().driver_data<discoboy_state>();
292		state->m_ram_att[offset] = data;
	295	m_ram_att[offset] = data;
293	296	}
294	297
295	298	static ADDRESS_MAP_START( discoboy_map, AS_PROGRAM, 8, discoboy_state )
296	299	AM_RANGE(0x0000, 0x7fff) AM_ROM
297	300	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
298		AM_RANGE(0xc000, 0xc7ff) AM_READWRITE_LEGACY(rambank_r, rambank_w)
299		AM_RANGE(0xc800, 0xcfff) AM_READWRITE_LEGACY(discoboy_ram_att_r, discoboy_ram_att_w)
300		AM_RANGE(0xd000, 0xdfff) AM_READWRITE_LEGACY(rambank2_r, rambank2_w)
	301	AM_RANGE(0xc000, 0xc7ff) AM_READWRITE(rambank_r, rambank_w)
	302	AM_RANGE(0xc800, 0xcfff) AM_READWRITE(discoboy_ram_att_r, discoboy_ram_att_w)
	303	AM_RANGE(0xd000, 0xdfff) AM_READWRITE(rambank2_r, rambank2_w)
301	304	AM_RANGE(0xe000, 0xefff) AM_RAM
302	305	AM_RANGE(0xf000, 0xffff) AM_RAM
303	306	ADDRESS_MAP_END
304	307
305	308
306		static READ8_HANDLER( discoboy_port_06_r )
	309	READ8_MEMBER(discoboy_state::discoboy_port_06_r)
307	310	{
308	311	return 0x00;
309	312	}
310	313
311	314	static ADDRESS_MAP_START( io_map, AS_IO, 8, discoboy_state )
312	315	ADDRESS_MAP_GLOBAL_MASK(0xff)
313		AM_RANGE(0x00, 0x00) AM_READ_PORT("DSWA") AM_WRITE_LEGACY(discoboy_port_00_w)
314		AM_RANGE(0x01, 0x01) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(discoboy_port_01_w)
	316	AM_RANGE(0x00, 0x00) AM_READ_PORT("DSWA") AM_WRITE(discoboy_port_00_w)
	317	AM_RANGE(0x01, 0x01) AM_READ_PORT("SYSTEM") AM_WRITE(discoboy_port_01_w)
315	318	AM_RANGE(0x02, 0x02) AM_READ_PORT("P1")
316		AM_RANGE(0x03, 0x03) AM_READ_PORT("P2") AM_WRITE_LEGACY(discoboy_port_03_w)
	319	AM_RANGE(0x03, 0x03) AM_READ_PORT("P2") AM_WRITE(discoboy_port_03_w)
317	320	AM_RANGE(0x04, 0x04) AM_READ_PORT("DSWB")
318		AM_RANGE(0x06, 0x06) AM_READWRITE_LEGACY(discoboy_port_06_r, discoboy_port_06_w) // ???
319		AM_RANGE(0x07, 0x07) AM_WRITE_LEGACY(rambank_select_w) // 0x20 is palette bank bit.. others?
	321	AM_RANGE(0x06, 0x06) AM_READWRITE(discoboy_port_06_r, discoboy_port_06_w) // ???
	322	AM_RANGE(0x07, 0x07) AM_WRITE(rambank_select_w) // 0x20 is palette bank bit.. others?
320	323	ADDRESS_MAP_END
321	324
322	325	/* Sound */
r14845	r14846
332	335	logerror("%s: Bank %02X\n", device->machine().describe_context(), data);
333	336	}
334	337
335		static WRITE8_HANDLER( yunsung8_adpcm_w )
	338	WRITE8_MEMBER(discoboy_state::yunsung8_adpcm_w)
336	339	{
337		discoboy_state *state = space->machine().driver_data<discoboy_state>();
338	340
339	341	/* Swap the nibbles */
340		state->m_adpcm = ((data & 0xf) << 4) | ((data >> 4) & 0xf);
	342	m_adpcm = ((data & 0xf) << 4) | ((data >> 4) & 0xf);
341	343	}
342	344
343	345	static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, discoboy_state )
344	346	AM_RANGE(0x0000, 0x7fff) AM_ROM
345	347	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("sndbank")
346	348	AM_RANGE(0xe000, 0xe000) AM_DEVWRITE_LEGACY("msm",yunsung8_sound_bankswitch_w)
347		AM_RANGE(0xe400, 0xe400) AM_WRITE_LEGACY(yunsung8_adpcm_w)
	349	AM_RANGE(0xe400, 0xe400) AM_WRITE(yunsung8_adpcm_w)
348	350	AM_RANGE(0xec00, 0xec01) AM_DEVWRITE_LEGACY("ymsnd", ym3812_w)
349	351	AM_RANGE(0xf000, 0xf7ff) AM_RAM
350	352	AM_RANGE(0xf800, 0xf800) AM_READ_LEGACY(soundlatch_r)

src/mame/drivers/summit.c

r14845	r14846
27	27
28	28	UINT8 *m_vram;
29	29	UINT8 *m_attr;
	30	DECLARE_WRITE8_MEMBER(out_w);
30	31	};
31	32
32	33
r14845	r14846
56	57	return 0;
57	58	}
58	59
59		static WRITE8_HANDLER( out_w )
	60	WRITE8_MEMBER(summit_state::out_w)
60	61	{
61
62	62	}
63	63
64	64
r14845	r14846
69	69	AM_RANGE(0x2800, 0x2bff) AM_RAM AM_BASE(m_vram)
70	70
71	71	AM_RANGE(0x3800, 0x3800) AM_READ_PORT("IN0")
72		//  AM_RANGE(0x3880, 0x3880) AM_WRITE_LEGACY(out_w)
73		AM_RANGE(0x3900, 0x3900) AM_READ_PORT("IN1") AM_WRITE_LEGACY(out_w) // lamps
74		//  AM_RANGE(0x3980, 0x3980) AM_WRITE_LEGACY(out_w)
75		AM_RANGE(0x3a00, 0x3a00) AM_READ_PORT("IN2") //AM_WRITE_LEGACY(out_w)
	72	//  AM_RANGE(0x3880, 0x3880) AM_WRITE(out_w)
	73	AM_RANGE(0x3900, 0x3900) AM_READ_PORT("IN1") AM_WRITE(out_w) // lamps
	74	//  AM_RANGE(0x3980, 0x3980) AM_WRITE(out_w)
	75	AM_RANGE(0x3a00, 0x3a00) AM_READ_PORT("IN2") //AM_WRITE(out_w)
76	76	AM_RANGE(0x3b00, 0x3b00) AM_READ_PORT("IN3")
77	77
78	78	AM_RANGE(0x7000, 0x71ff) AM_RAM

src/mame/drivers/skimaxx.c

r14845	r14846
58	58	UINT32 m_blitter_src_y;
59	59	UINT32 m_blitter_src_dy;
60	60	UINT32 *m_fpga_ctrl;
	61	DECLARE_WRITE32_MEMBER(skimaxx_blitter_w);
	62	DECLARE_READ32_MEMBER(skimaxx_blitter_r);
	63	DECLARE_WRITE32_MEMBER(m68k_tms_w);
	64	DECLARE_READ32_MEMBER(m68k_tms_r);
	65	DECLARE_WRITE32_MEMBER(skimaxx_fpga_ctrl_w);
	66	DECLARE_READ32_MEMBER(unk_r);
	67	DECLARE_READ32_MEMBER(skimaxx_unk1_r);
	68	DECLARE_WRITE32_MEMBER(skimaxx_unk1_w);
	69	DECLARE_WRITE32_MEMBER(skimaxx_sub_ctrl_w);
	70	DECLARE_READ32_MEMBER(skimaxx_analog_r);
61	71	};
62	72
63	73
r14845	r14846
68	78	*************************************/
69	79
70	80	// Set up blit parameters
71		static WRITE32_HANDLER( skimaxx_blitter_w )
	81	WRITE32_MEMBER(skimaxx_state::skimaxx_blitter_w)
72	82	{
73		skimaxx_state *state = space->machine().driver_data<skimaxx_state>();
74		UINT32 newdata = COMBINE_DATA( &state->m_blitter_regs[offset] );
	83	UINT32 newdata = COMBINE_DATA( &m_blitter_regs[offset] );
75	84
76	85	switch (offset)
77	86	{
78	87	case 0:
79		state->m_blitter_src_dy = (newdata & 0x7fff) - (newdata & 0x8000);
	88	m_blitter_src_dy = (newdata & 0x7fff) - (newdata & 0x8000);
80	89	break;
81	90
82	91	case 1:
83		state->m_blitter_src_x = (newdata & 0x1ff) << 8;
84		state->m_blitter_src_y = (newdata >> 9) << 8;
	92	m_blitter_src_x = (newdata & 0x1ff) << 8;
	93	m_blitter_src_y = (newdata >> 9) << 8;
85	94	break;
86	95
87	96	case 2:
88	97	if (ACCESSING_BITS_16_31)
89		state->m_blitter_src_dx = (newdata >> 16) & 0xffff;
	98	m_blitter_src_dx = (newdata >> 16) & 0xffff;
90	99	if (ACCESSING_BITS_0_15)
91		state->m_blitter_src_dx = newdata & 0xffff;
	100	m_blitter_src_dx = newdata & 0xffff;
92	101
93		state->m_blitter_src_dx = (state->m_blitter_src_dx & 0x7fff) - (state->m_blitter_src_dx & 0x8000);
	102	m_blitter_src_dx = (m_blitter_src_dx & 0x7fff) - (m_blitter_src_dx & 0x8000);
94	103	break;
95	104
96	105	case 3:
r14845	r14846
100	109	}
101	110
102	111	// A read by the 68030 from this area blits one pixel to the back buffer (at the same offset)
103		static READ32_HANDLER( skimaxx_blitter_r )
	112	READ32_MEMBER(skimaxx_state::skimaxx_blitter_r)
104	113	{
105		skimaxx_state *state = space->machine().driver_data<skimaxx_state>();
106		UINT32 penaddr = ((state->m_blitter_src_x >> 8) & 0x1ff) + ((state->m_blitter_src_y >> 8) << 9);
107		UINT16 *src = state->m_blitter_gfx + (penaddr % state->m_blitter_gfx_len);
108		UINT32 *dst = state->m_bg_buffer_back + offset;
	114	UINT32 penaddr = ((m_blitter_src_x >> 8) & 0x1ff) + ((m_blitter_src_y >> 8) << 9);
	115	UINT16 *src = m_blitter_gfx + (penaddr % m_blitter_gfx_len);
	116	UINT32 *dst = m_bg_buffer_back + offset;
109	117
110	118	UINT16 pen = (*src) & 0x7fff;
111	119
r14845	r14846
117	125	*dst = (*dst & 0xffff0000) | pen;
118	126	}
119	127
120		state->m_blitter_src_x = (state->m_blitter_src_x & 0x10000) | ((state->m_blitter_src_x + state->m_blitter_src_dx) & 0xffff);
121		state->m_blitter_src_y = (state->m_blitter_src_y & 0xffff0000) | ((state->m_blitter_src_y + state->m_blitter_src_dy) & 0xffff);
	128	m_blitter_src_x = (m_blitter_src_x & 0x10000) | ((m_blitter_src_x + m_blitter_src_dx) & 0xffff);
	129	m_blitter_src_y = (m_blitter_src_y & 0xffff0000) | ((m_blitter_src_y + m_blitter_src_dy) & 0xffff);
122	130
123	131	return 0;
124	132	}
r14845	r14846
216	224	*
217	225	*************************************/
218	226
219		static WRITE32_HANDLER( m68k_tms_w )
	227	WRITE32_MEMBER(skimaxx_state::m68k_tms_w)
220	228	{
221		tms34010_host_w(space->machine().device("tms"), offset, data);
	229	tms34010_host_w(machine().device("tms"), offset, data);
222	230	}
223	231
224		static READ32_HANDLER( m68k_tms_r )
	232	READ32_MEMBER(skimaxx_state::m68k_tms_r)
225	233	{
226		return tms34010_host_r(space->machine().device("tms"), offset);
	234	return tms34010_host_r(machine().device("tms"), offset);
227	235	}
228	236
229	237
r14845	r14846
242	250	bit 0: bit banging data
243	251	*/
244	252
245		static WRITE32_HANDLER( skimaxx_fpga_ctrl_w )
	253	WRITE32_MEMBER(skimaxx_state::skimaxx_fpga_ctrl_w)
246	254	{
247		skimaxx_state *state = space->machine().driver_data<skimaxx_state>();
248		UINT32 newdata = COMBINE_DATA( state->m_fpga_ctrl );
	255	UINT32 newdata = COMBINE_DATA( m_fpga_ctrl );
249	256
250	257	if (ACCESSING_BITS_0_7)
251	258	{
252	259	// double buffering
253	260	UINT8 bank_bg_buffer = (newdata & 0x40) ? 1 : 0;
254	261
255		state->m_bg_buffer_back  = state->m_bg_buffer + 0x400 * 0x100 * sizeof(UINT16) / sizeof(UINT32) * bank_bg_buffer;
256		state->m_bg_buffer_front = state->m_bg_buffer + 0x400 * 0x100 * sizeof(UINT16) / sizeof(UINT32) * (1 - bank_bg_buffer);
	262	m_bg_buffer_back  = m_bg_buffer + 0x400 * 0x100 * sizeof(UINT16) / sizeof(UINT32) * bank_bg_buffer;
	263	m_bg_buffer_front = m_bg_buffer + 0x400 * 0x100 * sizeof(UINT16) / sizeof(UINT32) * (1 - bank_bg_buffer);
257	264
258		memory_set_bank(space->machine(), "bank1", bank_bg_buffer);
	265	memory_set_bank(machine(), "bank1", bank_bg_buffer);
259	266	}
260	267	}
261	268
262	269	// 0x2000004c: bit 7, bit 0
263		static READ32_HANDLER( unk_r )
	270	READ32_MEMBER(skimaxx_state::unk_r)
264	271	{
265		skimaxx_state *state = space->machine().driver_data<skimaxx_state>();
266		return (*state->m_fpga_ctrl & 0x20) ? 0x80 : 0x00;
	272	return (*m_fpga_ctrl & 0x20) ? 0x80 : 0x00;
267	273	}
268	274
269	275	// 0x20000023
270		static READ32_HANDLER( skimaxx_unk1_r )
	276	READ32_MEMBER(skimaxx_state::skimaxx_unk1_r)
271	277	{
272	278	return 0x80;
273	279	}
274	280
275		static WRITE32_HANDLER( skimaxx_unk1_w )
	281	WRITE32_MEMBER(skimaxx_state::skimaxx_unk1_w)
276	282	{
277	283	}
278	284
279		static WRITE32_HANDLER( skimaxx_sub_ctrl_w )
	285	WRITE32_MEMBER(skimaxx_state::skimaxx_sub_ctrl_w)
280	286	{
281	287	// 7e/7f at the start. 3f/7f, related to reads from 1018xxxx
282	288	if (ACCESSING_BITS_0_7)
283	289	{
284		device_t *subcpu = space->machine().device("subcpu");
	290	device_t *subcpu = machine().device("subcpu");
285	291
286	292	device_set_input_line(subcpu, INPUT_LINE_RESET, (data & 0x01) ? CLEAR_LINE : ASSERT_LINE);
287	293	device_set_input_line(subcpu, INPUT_LINE_HALT,  (data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
r14845	r14846
297	303	..
298	304	1f      left max
299	305	*/
300		static READ32_HANDLER( skimaxx_analog_r )
	306	READ32_MEMBER(skimaxx_state::skimaxx_analog_r)
301	307	{
302		return BITSWAP8(input_port_read(space->machine(), offset ? "Y" : "X"), 0,1,2,3,4,5,6,7);
	308	return BITSWAP8(input_port_read(machine(), offset ? "Y" : "X"), 0,1,2,3,4,5,6,7);
303	309	}
304	310
305	311	/*************************************
r14845	r14846
310	316
311	317	static ADDRESS_MAP_START( 68030_1_map, AS_PROGRAM, 32, skimaxx_state )
312	318	AM_RANGE(0x00000000, 0x001fffff) AM_ROM
313		AM_RANGE(0x10000000, 0x10000003) AM_WRITE_LEGACY(skimaxx_sub_ctrl_w )
314		AM_RANGE(0x10100000, 0x1010000f) AM_READWRITE_LEGACY(m68k_tms_r, m68k_tms_w)//AM_NOP
	319	AM_RANGE(0x10000000, 0x10000003) AM_WRITE(skimaxx_sub_ctrl_w )
	320	AM_RANGE(0x10100000, 0x1010000f) AM_READWRITE(m68k_tms_r, m68k_tms_w)//AM_NOP
315	321	//  AM_RANGE(0x10180000, 0x10187fff) AM_RAM AM_SHARE("share1")
316	322	AM_RANGE(0x10180000, 0x1018ffff) AM_RAM AM_SHARE("share1")   // above 10188000 accessed at level end (game bug?)
317	323	AM_RANGE(0x20000000, 0x20000003) AM_READNOP   // watchdog_r?
r14845	r14846
321	327	AM_RANGE(0x20000018, 0x2000001b) AM_DEVREADWRITE8("oki3", okim6295_device, read, write, 0x00ff)   // right
322	328	AM_RANGE(0x2000001c, 0x2000001f) AM_DEVREADWRITE8("oki4", okim6295_device, read, write, 0x00ff)   // right
323	329
324		AM_RANGE(0x20000020, 0x20000023) AM_READ_LEGACY(skimaxx_unk1_r )   // units linking?
325		AM_RANGE(0x20000024, 0x20000027) AM_WRITE_LEGACY(skimaxx_unk1_w )   // ""
	330	AM_RANGE(0x20000020, 0x20000023) AM_READ(skimaxx_unk1_r )   // units linking?
	331	AM_RANGE(0x20000024, 0x20000027) AM_WRITE(skimaxx_unk1_w )   // ""
326	332
327	333	AM_RANGE(0x20000040, 0x20000043) AM_RAM   // write
328	334	AM_RANGE(0x20000044, 0x20000047) AM_READ_PORT( "DSW" )
329	335	AM_RANGE(0x20000048, 0x2000004b) AM_READ_PORT( "COIN" )
330		AM_RANGE(0x2000004c, 0x2000004f) AM_READ_LEGACY(unk_r)   // bit 7, bit 0
	336	AM_RANGE(0x2000004c, 0x2000004f) AM_READ(unk_r)   // bit 7, bit 0
331	337
332		AM_RANGE(0x20000050, 0x20000057) AM_READ_LEGACY(skimaxx_analog_r ) AM_WRITENOP   // read (0-1f), write motor?
	338	AM_RANGE(0x20000050, 0x20000057) AM_READ(skimaxx_analog_r ) AM_WRITENOP   // read (0-1f), write motor?
333	339
334	340	AM_RANGE(0xfffc0000, 0xffffffff) AM_RAM AM_MIRROR(0x00020000)
335	341	ADDRESS_MAP_END
r14845	r14846
344	350	static ADDRESS_MAP_START( 68030_2_map, AS_PROGRAM, 32, skimaxx_state )
345	351	AM_RANGE(0x00000000, 0x003fffff) AM_ROM
346	352
347		AM_RANGE(0x20000000, 0x2007ffff) AM_READ_LEGACY(skimaxx_blitter_r )   // do blit
348		AM_RANGE(0x30000000, 0x3000000f) AM_WRITE_LEGACY(skimaxx_blitter_w ) AM_BASE(m_blitter_regs )
	353	AM_RANGE(0x20000000, 0x2007ffff) AM_READ(skimaxx_blitter_r )   // do blit
	354	AM_RANGE(0x30000000, 0x3000000f) AM_WRITE(skimaxx_blitter_w ) AM_BASE(m_blitter_regs )
349	355
350		AM_RANGE(0x40000000, 0x40000003) AM_WRITE_LEGACY(skimaxx_fpga_ctrl_w ) AM_BASE(m_fpga_ctrl )
	356	AM_RANGE(0x40000000, 0x40000003) AM_WRITE(skimaxx_fpga_ctrl_w ) AM_BASE(m_fpga_ctrl )
351	357
352	358	AM_RANGE(0x50000000, 0x5007ffff) AM_RAMBANK("bank1")   // background ram allocated here at video_start (skimaxx_bg_buffer_back/front)
353	359	//  AM_RANGE(0xfffc0000, 0xfffc7fff) AM_RAM AM_SHARE("share1")

src/mame/drivers/mwarr.c

r14845	r14846
75	75	int m_which;
76	76
77	77	UINT16 m_sprites_buffer[0x800];
	78	DECLARE_WRITE16_MEMBER(bg_videoram_w);
	79	DECLARE_WRITE16_MEMBER(mlow_videoram_w);
	80	DECLARE_WRITE16_MEMBER(mhigh_videoram_w);
	81	DECLARE_WRITE16_MEMBER(tx_videoram_w);
	82	DECLARE_WRITE16_MEMBER(sprites_commands_w);
	83	DECLARE_WRITE16_MEMBER(mwarr_brightness_w);
78	84	};
79	85
80	86
r14845	r14846
84	90	*
85	91	*************************************/
86	92
87		static WRITE16_HANDLER( bg_videoram_w )
	93	WRITE16_MEMBER(mwarr_state::bg_videoram_w)
88	94	{
89		mwarr_state *state = space->machine().driver_data<mwarr_state>();
90	95
91		COMBINE_DATA(&state->m_bg_videoram[offset]);
92		state->m_bg_tilemap->mark_tile_dirty(offset);
	96	COMBINE_DATA(&m_bg_videoram[offset]);
	97	m_bg_tilemap->mark_tile_dirty(offset);
93	98	}
94	99
95		static WRITE16_HANDLER( mlow_videoram_w )
	100	WRITE16_MEMBER(mwarr_state::mlow_videoram_w)
96	101	{
97		mwarr_state *state = space->machine().driver_data<mwarr_state>();
98	102
99		COMBINE_DATA(&state->m_mlow_videoram[offset]);
100		state->m_mlow_tilemap->mark_tile_dirty(offset);
	103	COMBINE_DATA(&m_mlow_videoram[offset]);
	104	m_mlow_tilemap->mark_tile_dirty(offset);
101	105	}
102	106
103		static WRITE16_HANDLER( mhigh_videoram_w )
	107	WRITE16_MEMBER(mwarr_state::mhigh_videoram_w)
104	108	{
105		mwarr_state *state = space->machine().driver_data<mwarr_state>();
106	109
107		COMBINE_DATA(&state->m_mhigh_videoram[offset]);
108		state->m_mhigh_tilemap->mark_tile_dirty(offset);
	110	COMBINE_DATA(&m_mhigh_videoram[offset]);
	111	m_mhigh_tilemap->mark_tile_dirty(offset);
109	112	}
110	113
111		static WRITE16_HANDLER( tx_videoram_w )
	114	WRITE16_MEMBER(mwarr_state::tx_videoram_w)
112	115	{
113		mwarr_state *state = space->machine().driver_data<mwarr_state>();
114	116
115		COMBINE_DATA(&state->m_tx_videoram[offset]);
116		state->m_tx_tilemap->mark_tile_dirty(offset);
	117	COMBINE_DATA(&m_tx_videoram[offset]);
	118	m_tx_tilemap->mark_tile_dirty(offset);
117	119	}
118	120
119	121	static WRITE16_DEVICE_HANDLER( oki1_bank_w )
r14845	r14846
121	123	downcast<okim6295_device *>(device)->set_bank_base(0x40000 * (data & 3));
122	124	}
123	125
124		static WRITE16_HANDLER( sprites_commands_w )
	126	WRITE16_MEMBER(mwarr_state::sprites_commands_w)
125	127	{
126		mwarr_state *state = space->machine().driver_data<mwarr_state>();
127	128
128		if (state->m_which)
	129	if (m_which)
129	130	{
130	131	int i;
131	132
r14845	r14846
135	136	/* clear sprites on screen */
136	137	for (i = 0; i < 0x800; i++)
137	138	{
138		state->m_sprites_buffer[i] = 0;
	139	m_sprites_buffer[i] = 0;
139	140	}
140		state->m_which = 0;
	141	m_which = 0;
141	142	break;
142	143
143	144	default:
r14845	r14846
146	147	/* refresh sprites on screen */
147	148	for (i = 0; i < 0x800; i++)
148	149	{
149		state->m_sprites_buffer[i] = state->m_spriteram[i];
	150	m_sprites_buffer[i] = m_spriteram[i];
150	151	}
151	152	break;
152	153
r14845	r14846
156	157	}
157	158	}
158	159
159		state->m_which ^= 1;
	160	m_which ^= 1;
160	161	}
161	162
162		static WRITE16_HANDLER( mwarr_brightness_w )
	163	WRITE16_MEMBER(mwarr_state::mwarr_brightness_w)
163	164	{
164		mwarr_state *state = space->machine().driver_data<mwarr_state>();
165	165	int i;
166	166	double brightness;
167	167
168		COMBINE_DATA(&state->m_mwarr_ram[0x14 / 2]);
	168	COMBINE_DATA(&m_mwarr_ram[0x14 / 2]);
169	169
170	170	brightness = (double)(data & 0xff);
171	171	for (i = 0; i < 0x800; i++)
172	172	{
173		palette_set_pen_contrast(space->machine(), i, brightness/255);
	173	palette_set_pen_contrast(machine(), i, brightness/255);
174	174	}
175	175	}
176	176
r14845	r14846
183	183
184	184	static ADDRESS_MAP_START( mwarr_map, AS_PROGRAM, 16, mwarr_state )
185	185	AM_RANGE(0x000000, 0x0fffff) AM_ROM
186		AM_RANGE(0x100000, 0x1007ff) AM_RAM_WRITE_LEGACY(bg_videoram_w) AM_BASE(m_bg_videoram)
187		AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE_LEGACY(mlow_videoram_w) AM_BASE(m_mlow_videoram)
188		AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE_LEGACY(mhigh_videoram_w) AM_BASE(m_mhigh_videoram)
189		AM_RANGE(0x101800, 0x1027ff) AM_RAM_WRITE_LEGACY(tx_videoram_w) AM_BASE(m_tx_videoram)
	186	AM_RANGE(0x100000, 0x1007ff) AM_RAM_WRITE(bg_videoram_w) AM_BASE(m_bg_videoram)
	187	AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(mlow_videoram_w) AM_BASE(m_mlow_videoram)
	188	AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(mhigh_videoram_w) AM_BASE(m_mhigh_videoram)
	189	AM_RANGE(0x101800, 0x1027ff) AM_RAM_WRITE(tx_videoram_w) AM_BASE(m_tx_videoram)
190	190	AM_RANGE(0x103000, 0x1033ff) AM_RAM AM_BASE(m_bg_scrollram)
191	191	AM_RANGE(0x103400, 0x1037ff) AM_RAM AM_BASE(m_mlow_scrollram)
192	192	AM_RANGE(0x103800, 0x103bff) AM_RAM AM_BASE(m_mhigh_scrollram)
r14845	r14846
197	197	AM_RANGE(0x110002, 0x110003) AM_READ_PORT("SYSTEM")
198	198	AM_RANGE(0x110004, 0x110005) AM_READ_PORT("DSW")
199	199	AM_RANGE(0x110010, 0x110011) AM_DEVWRITE_LEGACY("oki2", oki1_bank_w)
200		AM_RANGE(0x110014, 0x110015) AM_WRITE_LEGACY(mwarr_brightness_w)
201		AM_RANGE(0x110016, 0x110017) AM_WRITE_LEGACY(sprites_commands_w)
	200	AM_RANGE(0x110014, 0x110015) AM_WRITE(mwarr_brightness_w)
	201	AM_RANGE(0x110016, 0x110017) AM_WRITE(sprites_commands_w)
202	202	AM_RANGE(0x110000, 0x11ffff) AM_RAM AM_BASE(m_mwarr_ram)
203	203	AM_RANGE(0x180000, 0x180001) AM_DEVREADWRITE8("oki1", okim6295_device, read, write, 0x00ff)
204	204	AM_RANGE(0x190000, 0x190001) AM_DEVREADWRITE8("oki2", okim6295_device, read, write, 0x00ff)

src/mame/drivers/vroulet.c

r14845	r14846
51	51	UINT8 *m_videoram;
52	52	UINT8 *m_colorram;
53	53	tilemap_t *m_bg_tilemap;
	54	DECLARE_WRITE8_MEMBER(vroulet_paletteram_w);
	55	DECLARE_WRITE8_MEMBER(vroulet_videoram_w);
	56	DECLARE_WRITE8_MEMBER(vroulet_colorram_w);
54	57	};
55	58
56	59
57	60	/* video */
58	61
59	62
60		static WRITE8_HANDLER(vroulet_paletteram_w)
	63	WRITE8_MEMBER(vroulet_state::vroulet_paletteram_w)
61	64	{
62	65	/*
63	66	paletteram_xxxxBBBBGGGGRRRR_be_w
r14845	r14846
65	68	*/
66	69
67	70	int i,j,a,b;
68		space->machine().generic.paletteram.u8[offset]=data;
	71	machine().generic.paletteram.u8[offset]=data;
69	72	for(i=0;i<32;i++)
70	73	{
71	74	for(j=0;j<16;j++)
72	75	{
73		a=space->machine().generic.paletteram.u8[((i*8+j)*2)&0xff ];
74		b=space->machine().generic.paletteram.u8[((i*8+j)*2+1)&0xff ];
75		palette_set_color_rgb(space->machine(),i*16+j,pal4bit(b),pal4bit(b>>4),pal4bit(a));
	76	a=machine().generic.paletteram.u8[((i*8+j)*2)&0xff ];
	77	b=machine().generic.paletteram.u8[((i*8+j)*2+1)&0xff ];
	78	palette_set_color_rgb(machine(),i*16+j,pal4bit(b),pal4bit(b>>4),pal4bit(a));
76	79	}
77	80	}
78	81	}
79	82
80		static WRITE8_HANDLER( vroulet_videoram_w )
	83	WRITE8_MEMBER(vroulet_state::vroulet_videoram_w)
81	84	{
82		vroulet_state *state = space->machine().driver_data<vroulet_state>();
83		state->m_videoram[offset] = data;
84		state->m_bg_tilemap->mark_tile_dirty(offset);
	85	m_videoram[offset] = data;
	86	m_bg_tilemap->mark_tile_dirty(offset);
85	87	}
86	88
87		static WRITE8_HANDLER( vroulet_colorram_w )
	89	WRITE8_MEMBER(vroulet_state::vroulet_colorram_w)
88	90	{
89		vroulet_state *state = space->machine().driver_data<vroulet_state>();
90		state->m_colorram[offset] = data;
91		state->m_bg_tilemap->mark_tile_dirty(offset);
	91	m_colorram[offset] = data;
	92	m_bg_tilemap->mark_tile_dirty(offset);
92	93	}
93	94
94	95	static TILE_GET_INFO( get_bg_tile_info )
r14845	r14846
123	124	AM_RANGE(0x0000, 0x5fff) AM_ROM
124	125	AM_RANGE(0x6000, 0x67ff) AM_RAM AM_SHARE("nvram")
125	126	AM_RANGE(0x8000, 0x8000) AM_NOP
126		AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE_LEGACY(vroulet_videoram_w) AM_BASE(m_videoram)
127		AM_RANGE(0x9400, 0x97ff) AM_RAM_WRITE_LEGACY(vroulet_colorram_w) AM_BASE(m_colorram)
	127	AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(vroulet_videoram_w) AM_BASE(m_videoram)
	128	AM_RANGE(0x9400, 0x97ff) AM_RAM_WRITE(vroulet_colorram_w) AM_BASE(m_colorram)
128	129	AM_RANGE(0xa000, 0xa001) AM_RAM AM_BASE(m_ball)
129		AM_RANGE(0xb000, 0xb0ff) AM_WRITE_LEGACY(vroulet_paletteram_w) AM_BASE_GENERIC(paletteram)
	130	AM_RANGE(0xb000, 0xb0ff) AM_WRITE(vroulet_paletteram_w) AM_BASE_GENERIC(paletteram)
130	131	AM_RANGE(0xc000, 0xc000) AM_NOP
131	132	ADDRESS_MAP_END
132	133

src/mame/drivers/coinmvga.c

r14845	r14846
227	227
228	228	UINT16 *m_vram;
229	229	struct { int r,g,b,offs,offs_internal; } m_bgpal, m_fgpal;
	230	DECLARE_WRITE8_MEMBER(debug_w);
	231	DECLARE_WRITE16_MEMBER(ramdac_bg_w);
	232	DECLARE_WRITE16_MEMBER(ramdac_fg_w);
	233	DECLARE_READ16_MEMBER(test_r);
230	234	};
231	235
232	236
r14845	r14846
276	280	*  Read / Write Handlers  *
277	281	**************************/
278	282
279		//static WRITE8_HANDLER( debug_w )
	283	//WRITE8_MEMBER(coinmvga_state::debug_w)
280	284	//{
281	285	//  popmessage("written : %02X", data);
282	286	//}
283	287
284		static WRITE16_HANDLER( ramdac_bg_w )
	288	WRITE16_MEMBER(coinmvga_state::ramdac_bg_w)
285	289	{
286		coinmvga_state *state = space->machine().driver_data<coinmvga_state>();
287	290	if(ACCESSING_BITS_8_15)
288	291	{
289		state->m_bgpal.offs = data >> 8;
290		state->m_bgpal.offs_internal = 0;
	292	m_bgpal.offs = data >> 8;
	293	m_bgpal.offs_internal = 0;
291	294	}
292	295	else //if(mem_mask == 0x00ff)
293	296	{
294		switch(state->m_bgpal.offs_internal)
	297	switch(m_bgpal.offs_internal)
295	298	{
296	299	case 0:
297		state->m_bgpal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
298		state->m_bgpal.offs_internal++;
	300	m_bgpal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	301	m_bgpal.offs_internal++;
299	302	break;
300	303	case 1:
301		state->m_bgpal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
302		state->m_bgpal.offs_internal++;
	304	m_bgpal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	305	m_bgpal.offs_internal++;
303	306	break;
304	307	case 2:
305		state->m_bgpal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
306		palette_set_color(space->machine(), state->m_bgpal.offs, MAKE_RGB(state->m_bgpal.r, state->m_bgpal.g, state->m_bgpal.b));
307		state->m_bgpal.offs_internal = 0;
308		state->m_bgpal.offs++;
	308	m_bgpal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	309	palette_set_color(machine(), m_bgpal.offs, MAKE_RGB(m_bgpal.r, m_bgpal.g, m_bgpal.b));
	310	m_bgpal.offs_internal = 0;
	311	m_bgpal.offs++;
309	312	break;
310	313	}
311	314	}
312	315	}
313	316
314	317
315		static WRITE16_HANDLER( ramdac_fg_w )
	318	WRITE16_MEMBER(coinmvga_state::ramdac_fg_w)
316	319	{
317		coinmvga_state *state = space->machine().driver_data<coinmvga_state>();
318	320	if(ACCESSING_BITS_8_15)
319	321	{
320		state->m_fgpal.offs = data >> 8;
321		state->m_fgpal.offs_internal = 0;
	322	m_fgpal.offs = data >> 8;
	323	m_fgpal.offs_internal = 0;
322	324	}
323	325	else
324	326	{
325		switch(state->m_fgpal.offs_internal)
	327	switch(m_fgpal.offs_internal)
326	328	{
327	329	case 0:
328		state->m_fgpal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
329		state->m_fgpal.offs_internal++;
	330	m_fgpal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	331	m_fgpal.offs_internal++;
330	332	break;
331	333	case 1:
332		state->m_fgpal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
333		state->m_fgpal.offs_internal++;
	334	m_fgpal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	335	m_fgpal.offs_internal++;
334	336	break;
335	337	case 2:
336		state->m_fgpal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
337		palette_set_color(space->machine(), 0x100+state->m_fgpal.offs, MAKE_RGB(state->m_fgpal.r, state->m_fgpal.g, state->m_fgpal.b));
338		state->m_fgpal.offs_internal = 0;
339		state->m_fgpal.offs++;
	338	m_fgpal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	339	palette_set_color(machine(), 0x100+m_fgpal.offs, MAKE_RGB(m_fgpal.r, m_fgpal.g, m_fgpal.b));
	340	m_fgpal.offs_internal = 0;
	341	m_fgpal.offs++;
340	342	break;
341	343	}
342	344	}
343	345	}
344	346
345	347	/*
346		static READ16_HANDLER( test_r )
	348	READ16_MEMBER(coinmvga_state::test_r)
347	349	{
348		return space->machine().rand();
	350	return machine().rand();
349	351	}*/
350	352
351	353	/*************************
r14845	r14846
359	361	//  AM_RANGE(0x0a0000, 0x0fffff) AM_RAM
360	362	//  AM_RANGE(0x100000, 0x1fffff) AM_RAM //colorama
361	363	AM_RANGE(0x210000, 0x21ffff) AM_RAM AM_BASE(m_vram)
362		//  AM_RANGE(0x40746e, 0x40746f) AM_READ_LEGACY(test_r) AM_WRITENOP //touch screen related, colorama
363		//  AM_RANGE(0x403afa, 0x403afb) AM_READ_LEGACY(test_r) AM_WRITENOP //touch screen related, cmrltv75
	364	//  AM_RANGE(0x40746e, 0x40746f) AM_READ(test_r) AM_WRITENOP //touch screen related, colorama
	365	//  AM_RANGE(0x403afa, 0x403afb) AM_READ(test_r) AM_WRITENOP //touch screen related, cmrltv75
364	366	AM_RANGE(0x400000, 0x40ffff) AM_RAM
365	367
366		AM_RANGE(0x600000, 0x600001) AM_WRITE_LEGACY(ramdac_bg_w)
367		AM_RANGE(0x600004, 0x600005) AM_WRITE_LEGACY(ramdac_fg_w)
	368	AM_RANGE(0x600000, 0x600001) AM_WRITE(ramdac_bg_w)
	369	AM_RANGE(0x600004, 0x600005) AM_WRITE(ramdac_fg_w)
368	370	AM_RANGE(0x600008, 0x600009) AM_DEVREADWRITE8_LEGACY("ymz", ymz280b_r, ymz280b_w, 0xffff)
369	371	AM_RANGE(0x610000, 0x61000f) AM_RAM //touch screen i/o
370	372

src/mame/drivers/twins.c

r14845	r14846
62	62	UINT16 *m_videoram;
63	63	UINT16 *m_pal;
64	64	UINT16 m_paloff;
	65	DECLARE_READ16_MEMBER(twins_port4_r);
	66	DECLARE_WRITE16_MEMBER(twins_port4_w);
	67	DECLARE_WRITE16_MEMBER(port6_pal0_w);
	68	DECLARE_WRITE16_MEMBER(porte_paloff0_w);
	69	DECLARE_WRITE16_MEMBER(twinsa_port4_w);
	70	DECLARE_READ16_MEMBER(twinsa_unk_r);
65	71	};
66	72
67	73
68	74
69	75	/* port 4 is eeprom */
70		static READ16_HANDLER( twins_port4_r )
	76	READ16_MEMBER(twins_state::twins_port4_r)
71	77	{
72	78	return 0xffff;
73	79	}
74	80
75		static WRITE16_HANDLER( twins_port4_w )
	81	WRITE16_MEMBER(twins_state::twins_port4_w)
76	82	{
77	83	}
78	84
79		static WRITE16_HANDLER( port6_pal0_w )
	85	WRITE16_MEMBER(twins_state::port6_pal0_w)
80	86	{
81		twins_state *state = space->machine().driver_data<twins_state>();
82		COMBINE_DATA(&state->m_pal[state->m_paloff]);
83		state->m_paloff = (state->m_paloff + 1) & 0xff;
	87	COMBINE_DATA(&m_pal[m_paloff]);
	88	m_paloff = (m_paloff + 1) & 0xff;
84	89	}
85	90
86	91	/* ??? weird ..*/
87		static WRITE16_HANDLER( porte_paloff0_w )
	92	WRITE16_MEMBER(twins_state::porte_paloff0_w)
88	93	{
89		twins_state *state = space->machine().driver_data<twins_state>();
90		state->m_paloff = 0;
	94	m_paloff = 0;
91	95	}
92	96
93	97	static ADDRESS_MAP_START( twins_map, AS_PROGRAM, 16, twins_state )
r14845	r14846
99	103	static ADDRESS_MAP_START( twins_io, AS_IO, 16, twins_state )
100	104	AM_RANGE(0x0000, 0x0003) AM_DEVWRITE8_LEGACY("aysnd", ay8910_address_data_w, 0x00ff)
101	105	AM_RANGE(0x0002, 0x0003) AM_DEVREAD8_LEGACY("aysnd", ay8910_r, 0x00ff)
102		AM_RANGE(0x0004, 0x0005) AM_READWRITE_LEGACY(twins_port4_r, twins_port4_w)
103		AM_RANGE(0x0006, 0x0007) AM_WRITE_LEGACY(port6_pal0_w)
104		AM_RANGE(0x000e, 0x000f) AM_WRITE_LEGACY(porte_paloff0_w)
	106	AM_RANGE(0x0004, 0x0005) AM_READWRITE(twins_port4_r, twins_port4_w)
	107	AM_RANGE(0x0006, 0x0007) AM_WRITE(port6_pal0_w)
	108	AM_RANGE(0x000e, 0x000f) AM_WRITE(porte_paloff0_w)
105	109	ADDRESS_MAP_END
106	110
107	111	static VIDEO_START(twins)
r14845	r14846
247	251	return 0;
248	252	}
249	253
250		static WRITE16_HANDLER( twinsa_port4_w )
	254	WRITE16_MEMBER(twins_state::twinsa_port4_w)
251	255	{
252		twins_state *state = space->machine().driver_data<twins_state>();
253		state->m_pal[state->m_paloff&0xfff] = data;
254		state->m_paloff++;
255		//  printf("paloff %04x\n",state->m_paloff);
	256	m_pal[m_paloff&0xfff] = data;
	257	m_paloff++;
	258	//  printf("paloff %04x\n",m_paloff);
256	259	}
257	260
258		static READ16_HANDLER( twinsa_unk_r )
	261	READ16_MEMBER(twins_state::twinsa_unk_r)
259	262	{
260	263	return 0xffff;
261	264	}
262	265
263	266	static ADDRESS_MAP_START( twinsa_io, AS_IO, 16, twins_state )
264		AM_RANGE(0x0000, 0x0001) AM_READWRITE_LEGACY(twinsa_unk_r, porte_paloff0_w)
265		AM_RANGE(0x0002, 0x0003) AM_WRITE_LEGACY(porte_paloff0_w)
266		AM_RANGE(0x0004, 0x0005) AM_WRITE_LEGACY(twinsa_port4_w) // palette on this set
	267	AM_RANGE(0x0000, 0x0001) AM_READWRITE(twinsa_unk_r, porte_paloff0_w)
	268	AM_RANGE(0x0002, 0x0003) AM_WRITE(porte_paloff0_w)
	269	AM_RANGE(0x0004, 0x0005) AM_WRITE(twinsa_port4_w) // palette on this set
267	270	AM_RANGE(0x0008, 0x0009) AM_DEVWRITE8_LEGACY("aysnd", ay8910_address_w, 0x00ff)
268	271	AM_RANGE(0x0010, 0x0011) AM_DEVREADWRITE8_LEGACY("aysnd", ay8910_r, ay8910_data_w, 0x00ff)
269		AM_RANGE(0x0018, 0x0019) AM_READ_LEGACY(twins_port4_r) AM_WRITE_LEGACY(twins_port4_w)
	272	AM_RANGE(0x0018, 0x0019) AM_READ(twins_port4_r) AM_WRITE(twins_port4_w)
270	273	ADDRESS_MAP_END
271	274
272	275

src/mame/drivers/cultures.c

r14845	r14846
39	39	int      m_bg1_bank;
40	40	int      m_bg2_bank;
41	41	int      m_old_bank;
	42	DECLARE_WRITE8_MEMBER(cpu_bankswitch_w);
	43	DECLARE_WRITE8_MEMBER(bg0_videoram_w);
	44	DECLARE_WRITE8_MEMBER(misc_w);
	45	DECLARE_WRITE8_MEMBER(bg_bank_w);
42	46	};
43	47
44	48
r14845	r14846
115	119	return 0;
116	120	}
117	121
118		static WRITE8_HANDLER( cpu_bankswitch_w )
	122	WRITE8_MEMBER(cultures_state::cpu_bankswitch_w)
119	123	{
120		cultures_state *state = space->machine().driver_data<cultures_state>();
121		memory_set_bank(space->machine(), "bank1", data & 0x0f);
122		state->m_video_bank = ~data & 0x20;
	124	memory_set_bank(machine(), "bank1", data & 0x0f);
	125	m_video_bank = ~data & 0x20;
123	126	}
124	127
125		static WRITE8_HANDLER( bg0_videoram_w )
	128	WRITE8_MEMBER(cultures_state::bg0_videoram_w)
126	129	{
127		cultures_state *state = space->machine().driver_data<cultures_state>();
128		if (state->m_video_bank == 0)
	130	if (m_video_bank == 0)
129	131	{
130	132	int r, g, b, datax;
131		state->m_paletteram[offset] = data;
	133	m_paletteram[offset] = data;
132	134	offset >>= 1;
133		datax = state->m_paletteram[offset * 2] + 256 * state->m_paletteram[offset * 2 + 1];
	135	datax = m_paletteram[offset * 2] + 256 * m_paletteram[offset * 2 + 1];
134	136
135	137	r = ((datax >> 7) & 0x1e) | ((datax & 0x4000) ? 0x1 : 0);
136	138	g = ((datax >> 3) & 0x1e) | ((datax & 0x2000) ? 0x1 : 0);
137	139	b = ((datax << 1) & 0x1e) | ((datax & 0x1000) ? 0x1 : 0);
138	140
139		palette_set_color_rgb(space->machine(), offset, pal5bit(r), pal5bit(g), pal5bit(b));
	141	palette_set_color_rgb(machine(), offset, pal5bit(r), pal5bit(g), pal5bit(b));
140	142	}
141	143	else
142	144	{
143		state->m_bg0_videoram[offset] = data;
144		state->m_bg0_tilemap->mark_tile_dirty(offset >> 1);
	145	m_bg0_videoram[offset] = data;
	146	m_bg0_tilemap->mark_tile_dirty(offset >> 1);
145	147	}
146	148	}
147	149
148		static WRITE8_HANDLER( misc_w )
	150	WRITE8_MEMBER(cultures_state::misc_w)
149	151	{
150		cultures_state *state = space->machine().driver_data<cultures_state>();
151	152	int new_bank = data & 0xf;
152	153
153		if (state->m_old_bank != new_bank)
	154	if (m_old_bank != new_bank)
154	155	{
155	156	// oki banking
156		UINT8 *src = space->machine().region("oki")->base() + 0x40000 + 0x20000 * new_bank;
157		UINT8 *dst = space->machine().region("oki")->base() + 0x20000;
	157	UINT8 *src = machine().region("oki")->base() + 0x40000 + 0x20000 * new_bank;
	158	UINT8 *dst = machine().region("oki")->base() + 0x20000;
158	159	memcpy(dst, src, 0x20000);
159	160
160		state->m_old_bank = new_bank;
	161	m_old_bank = new_bank;
161	162	}
162	163
163		state->m_irq_enable = data & 0x80;
	164	m_irq_enable = data & 0x80;
164	165	}
165	166
166		static WRITE8_HANDLER( bg_bank_w )
	167	WRITE8_MEMBER(cultures_state::bg_bank_w)
167	168	{
168		cultures_state *state = space->machine().driver_data<cultures_state>();
169		if (state->m_bg1_bank != (data & 3))
	169	if (m_bg1_bank != (data & 3))
170	170	{
171		state->m_bg1_bank = data & 3;
172		state->m_bg1_tilemap->mark_all_dirty();
	171	m_bg1_bank = data & 3;
	172	m_bg1_tilemap->mark_all_dirty();
173	173	}
174	174
175		if (state->m_bg2_bank != ((data & 0xc) >> 2))
	175	if (m_bg2_bank != ((data & 0xc) >> 2))
176	176	{
177		state->m_bg2_bank = (data & 0xc) >> 2;
178		state->m_bg2_tilemap->mark_all_dirty();
	177	m_bg2_bank = (data & 0xc) >> 2;
	178	m_bg2_tilemap->mark_all_dirty();
179	179	}
180		coin_counter_w(space->machine(), 0, data & 0x10);
	180	coin_counter_w(machine(), 0, data & 0x10);
181	181	}
182	182
183	183	static ADDRESS_MAP_START( cultures_map, AS_PROGRAM, 8, cultures_state )
184	184	AM_RANGE(0x0000, 0x3fff) AM_ROM
185	185	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
186		AM_RANGE(0x8000, 0xbfff) AM_RAM_WRITE_LEGACY(bg0_videoram_w) AM_BASE(m_bg0_videoram)
	186	AM_RANGE(0x8000, 0xbfff) AM_RAM_WRITE(bg0_videoram_w) AM_BASE(m_bg0_videoram)
187	187	AM_RANGE(0xc000, 0xdfff) AM_RAM
188	188	AM_RANGE(0xf000, 0xffff) AM_RAM
189	189	ADDRESS_MAP_END
r14845	r14846
198	198	AM_RANGE(0x50, 0x53) AM_RAM AM_BASE(m_bg1_regs_y)
199	199	AM_RANGE(0x60, 0x63) AM_RAM AM_BASE(m_bg2_regs_x)
200	200	AM_RANGE(0x70, 0x73) AM_RAM AM_BASE(m_bg2_regs_y)
201		AM_RANGE(0x80, 0x80) AM_WRITE_LEGACY(cpu_bankswitch_w)
202		AM_RANGE(0x90, 0x90) AM_WRITE_LEGACY(misc_w)
203		AM_RANGE(0xa0, 0xa0) AM_WRITE_LEGACY(bg_bank_w)
	201	AM_RANGE(0x80, 0x80) AM_WRITE(cpu_bankswitch_w)
	202	AM_RANGE(0x90, 0x90) AM_WRITE(misc_w)
	203	AM_RANGE(0xa0, 0xa0) AM_WRITE(bg_bank_w)
204	204	AM_RANGE(0xc0, 0xc0) AM_DEVREADWRITE("oki", okim6295_device, read, write)
205	205	AM_RANGE(0xd0, 0xd0) AM_READ_PORT("SW1_A")
206	206	AM_RANGE(0xd1, 0xd1) AM_READ_PORT("SW1_B")

src/mame/drivers/5clown.c

r14845	r14846
466	466	UINT8 *m_colorram;
467	467	tilemap_t *m_bg_tilemap;
468	468	int m_mux_data;
	469	DECLARE_WRITE8_MEMBER(fclown_videoram_w);
	470	DECLARE_WRITE8_MEMBER(fclown_colorram_w);
	471	DECLARE_WRITE8_MEMBER(cpu_c048_w);
	472	DECLARE_WRITE8_MEMBER(cpu_d800_w);
	473	DECLARE_READ8_MEMBER(snd_e06_r);
	474	DECLARE_WRITE8_MEMBER(snd_800_w);
	475	DECLARE_WRITE8_MEMBER(snd_a02_w);
469	476	};
470	477
471	478
r14845	r14846
477	484
478	485
479	486
480		static WRITE8_HANDLER( fclown_videoram_w )
	487	WRITE8_MEMBER(_5clown_state::fclown_videoram_w)
481	488	{
482		_5clown_state *state = space->machine().driver_data<_5clown_state>();
483		state->m_videoram[offset] = data;
484		state->m_bg_tilemap->mark_tile_dirty(offset);
	489	m_videoram[offset] = data;
	490	m_bg_tilemap->mark_tile_dirty(offset);
485	491	}
486	492
487		static WRITE8_HANDLER( fclown_colorram_w )
	493	WRITE8_MEMBER(_5clown_state::fclown_colorram_w)
488	494	{
489		_5clown_state *state = space->machine().driver_data<_5clown_state>();
490		state->m_colorram[offset] = data;
491		state->m_bg_tilemap->mark_tile_dirty(offset);
	495	m_colorram[offset] = data;
	496	m_bg_tilemap->mark_tile_dirty(offset);
492	497	}
493	498
494	499
r14845	r14846
653	658	/**********************************/
654	659
655	660
656		static WRITE8_HANDLER( cpu_c048_w)
	661	WRITE8_MEMBER(_5clown_state::cpu_c048_w)
657	662	{
658	663	logerror("Main: Write to $C048: %02X\n", data);
659	664	}
660	665
661		static WRITE8_HANDLER( cpu_d800_w )
	666	WRITE8_MEMBER(_5clown_state::cpu_d800_w)
662	667	{
663		_5clown_state *state = space->machine().driver_data<_5clown_state>();
664	668	logerror("Main: Write to $D800: %02x\n", data);
665		state->m_main_latch_d800 = data;
	669	m_main_latch_d800 = data;
666	670	}
667	671
668	672
r14845	r14846
681	685	*  SOUND  R/W Handlers        *
682	686	******************************/
683	687
684		static READ8_HANDLER( snd_e06_r )
	688	READ8_MEMBER(_5clown_state::snd_e06_r)
685	689	{
686		_5clown_state *state = space->machine().driver_data<_5clown_state>();
687	690	logerror("Sound: Read from $0E06 \n");
688		return state->m_main_latch_d800;
	691	return m_main_latch_d800;
689	692	}
690	693
691		static WRITE8_HANDLER( snd_800_w )
	694	WRITE8_MEMBER(_5clown_state::snd_800_w)
692	695	{
693		_5clown_state *state = space->machine().driver_data<_5clown_state>();
694		state->m_snd_latch_0800 = data;
	696	m_snd_latch_0800 = data;
695	697
696		if (state->m_snd_latch_0a02 == 0xc0)
	698	if (m_snd_latch_0a02 == 0xc0)
697	699	{
698		state->m_ay8910_addr = state->m_snd_latch_0800;
	700	m_ay8910_addr = m_snd_latch_0800;
699	701	}
700	702
701		if (state->m_snd_latch_0a02 == 0x00)
	703	if (m_snd_latch_0a02 == 0x00)
702	704	{
703		fclown_ay8910_w( state->m_ay8910, state->m_ay8910_addr, state->m_snd_latch_0800);
	705	fclown_ay8910_w( m_ay8910, m_ay8910_addr, m_snd_latch_0800);
704	706	}
705	707	}
706	708
707		static WRITE8_HANDLER( snd_a02_w )
	709	WRITE8_MEMBER(_5clown_state::snd_a02_w)
708	710	{
709		_5clown_state *state = space->machine().driver_data<_5clown_state>();
710		state->m_snd_latch_0a02 = data & 0xff;
711		logerror("Sound: Write to $0A02: %02x\n", state->m_snd_latch_0a02);
	711	m_snd_latch_0a02 = data & 0xff;
	712	logerror("Sound: Write to $0A02: %02x\n", m_snd_latch_0a02);
712	713	}
713	714
714	715
r14845	r14846
722	723	AM_RANGE(0x0801, 0x0801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
723	724	AM_RANGE(0x0844, 0x0847) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
724	725	AM_RANGE(0x0848, 0x084b) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
725		AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE_LEGACY(fclown_videoram_w) AM_BASE(m_videoram)   /* Init'ed at $2042 */
726		AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE_LEGACY(fclown_colorram_w) AM_BASE(m_colorram)   /* Init'ed at $2054 */
	726	AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(fclown_videoram_w) AM_BASE(m_videoram)   /* Init'ed at $2042 */
	727	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(fclown_colorram_w) AM_BASE(m_colorram)   /* Init'ed at $2054 */
727	728	AM_RANGE(0x2000, 0x7fff) AM_ROM               /* ROM space */
728	729
729		AM_RANGE(0xc048, 0xc048) AM_WRITE_LEGACY(cpu_c048_w )
730		AM_RANGE(0xd800, 0xd800) AM_WRITE_LEGACY(cpu_d800_w )
	730	AM_RANGE(0xc048, 0xc048) AM_WRITE(cpu_c048_w )
	731	AM_RANGE(0xd800, 0xd800) AM_WRITE(cpu_d800_w )
731	732
732	733	AM_RANGE(0xc400, 0xc400) AM_READ_PORT("SW1")   /* DIP Switches bank */
733	734	AM_RANGE(0xcc00, 0xcc00) AM_READ_PORT("SW2")   /* DIP Switches bank */
r14845	r14846
793	794
794	795	static ADDRESS_MAP_START( fcaudio_map, AS_PROGRAM, 8, _5clown_state )
795	796	AM_RANGE(0x0000, 0x07ff) AM_RAM
796		AM_RANGE(0x0800, 0x0800) AM_WRITE_LEGACY(snd_800_w)
797		AM_RANGE(0x0a02, 0x0a02) AM_WRITE_LEGACY(snd_a02_w)
	797	AM_RANGE(0x0800, 0x0800) AM_WRITE(snd_800_w)
	798	AM_RANGE(0x0a02, 0x0a02) AM_WRITE(snd_a02_w)
798	799	AM_RANGE(0x0c04, 0x0c04) AM_DEVWRITE("oki6295", okim6295_device, write)
799	800	AM_RANGE(0x0c06, 0x0c06) AM_DEVREAD("oki6295", okim6295_device, read)
800		AM_RANGE(0x0e06, 0x0e06) AM_READ_LEGACY(snd_e06_r)
	801	AM_RANGE(0x0e06, 0x0e06) AM_READ(snd_e06_r)
801	802	AM_RANGE(0xe000, 0xffff) AM_ROM               /* ROM space */
802	803	ADDRESS_MAP_END
803	804

src/mame/drivers/tgtpanic.c

r14845	r14846
21	21
22	22	UINT8 *m_ram;
23	23	UINT8 m_color;
	24	DECLARE_WRITE8_MEMBER(color_w);
24	25	};
25	26
26	27
r14845	r14846
66	67	return 0;
67	68	}
68	69
69		static WRITE8_HANDLER( color_w )
	70	WRITE8_MEMBER(tgtpanic_state::color_w)
70	71	{
71		tgtpanic_state *state = space->machine().driver_data<tgtpanic_state>();
72		space->machine().primary_screen->update_partial(space->machine().primary_screen->vpos());
73		state->m_color = data;
	72	machine().primary_screen->update_partial(machine().primary_screen->vpos());
	73	m_color = data;
74	74	}
75	75
76	76
r14845	r14846
87	87
88	88	static ADDRESS_MAP_START( io_map, AS_IO, 8, tgtpanic_state )
89	89	ADDRESS_MAP_GLOBAL_MASK(0xff)
90		AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0") AM_WRITE_LEGACY(color_w)
	90	AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0") AM_WRITE(color_w)
91	91	AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1")
92	92	ADDRESS_MAP_END
93	93

src/mame/drivers/drw80pkr.c

r14845	r14846
50	50	UINT8 m_pkr_io_ram[0x100];
51	51	UINT16 m_video_ram[0x0400];
52	52	UINT8 m_color_ram[0x0400];
	53	DECLARE_WRITE8_MEMBER(t0_w);
	54	DECLARE_WRITE8_MEMBER(t1_w);
	55	DECLARE_WRITE8_MEMBER(p0_w);
	56	DECLARE_WRITE8_MEMBER(p1_w);
	57	DECLARE_WRITE8_MEMBER(p2_w);
	58	DECLARE_WRITE8_MEMBER(prog_w);
	59	DECLARE_WRITE8_MEMBER(bus_w);
	60	DECLARE_WRITE8_MEMBER(drw80pkr_io_w);
	61	DECLARE_READ8_MEMBER(t0_r);
	62	DECLARE_READ8_MEMBER(t1_r);
	63	DECLARE_READ8_MEMBER(p0_r);
	64	DECLARE_READ8_MEMBER(p1_r);
	65	DECLARE_READ8_MEMBER(p2_r);
	66	DECLARE_READ8_MEMBER(bus_r);
	67	DECLARE_READ8_MEMBER(drw80pkr_io_r);
53	68	};
54	69
55	70
r14845	r14846
67	82	* Write Handlers *
68	83	******************/
69	84
70		static WRITE8_HANDLER( t0_w )
	85	WRITE8_MEMBER(drw80pkr_state::t0_w)
71	86	{
72		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
73		state->m_t0 = data;
	87	m_t0 = data;
74	88	}
75	89
76		static WRITE8_HANDLER( t1_w )
	90	WRITE8_MEMBER(drw80pkr_state::t1_w)
77	91	{
78		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
79		state->m_t1 = data;
	92	m_t1 = data;
80	93	}
81	94
82		static WRITE8_HANDLER( p0_w )
	95	WRITE8_MEMBER(drw80pkr_state::p0_w)
83	96	{
84		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
85		state->m_p0 = data;
	97	m_p0 = data;
86	98	}
87	99
88		static WRITE8_HANDLER( p1_w )
	100	WRITE8_MEMBER(drw80pkr_state::p1_w)
89	101	{
90		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
91		state->m_p1 = data;
	102	m_p1 = data;
92	103	}
93	104
94		static WRITE8_HANDLER( p2_w )
	105	WRITE8_MEMBER(drw80pkr_state::p2_w)
95	106	{
96		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
97		state->m_p2 = data;
	107	m_p2 = data;
98	108	}
99	109
100		static WRITE8_HANDLER( prog_w )
	110	WRITE8_MEMBER(drw80pkr_state::prog_w)
101	111	{
102		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
103		state->m_prog = data;
	112	m_prog = data;
104	113
105	114	// Bankswitch Program Memory
106		if (state->m_prog == 0x01)
	115	if (m_prog == 0x01)
107	116	{
108		state->m_active_bank = state->m_active_bank ^ 0x01;
	117	m_active_bank = m_active_bank ^ 0x01;
109	118
110		memory_set_bank(space->machine(), "bank1", state->m_active_bank);
	119	memory_set_bank(machine(), "bank1", m_active_bank);
111	120	}
112	121	}
113	122
114		static WRITE8_HANDLER( bus_w )
	123	WRITE8_MEMBER(drw80pkr_state::bus_w)
115	124	{
116		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
117		state->m_bus = data;
	125	m_bus = data;
118	126	}
119	127
120		static WRITE8_HANDLER( drw80pkr_io_w )
	128	WRITE8_MEMBER(drw80pkr_state::drw80pkr_io_w)
121	129	{
122		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
123	130	UINT16 n_offs;
124	131
125		if (state->m_p2 == 0x3f || state->m_p2 == 0x7f)
	132	if (m_p2 == 0x3f || m_p2 == 0x7f)
126	133	{
127		n_offs = ((state->m_p1 & 0xc0) << 2 ) + offset;
	134	n_offs = ((m_p1 & 0xc0) << 2 ) + offset;
128	135
129		if (state->m_p2 == 0x3f)
	136	if (m_p2 == 0x3f)
130	137	{
131		state->m_video_ram[n_offs] = data; // low address
	138	m_video_ram[n_offs] = data; // low address
132	139	} else {
133		state->m_color_ram[n_offs] = data & 0x0f; // color palette
134		state->m_video_ram[n_offs] += ((data & 0xf0) << 4 ); // high address
	140	m_color_ram[n_offs] = data & 0x0f; // color palette
	141	m_video_ram[n_offs] += ((data & 0xf0) << 4 ); // high address
135	142	}
136	143
137		state->m_bg_tilemap->mark_tile_dirty(n_offs);
	144	m_bg_tilemap->mark_tile_dirty(n_offs);
138	145	}
139	146
140		if (state->m_p2 == 0xc7)
	147	if (m_p2 == 0xc7)
141	148	{
142	149	// CRTC Register
143	150	// R0 = 0x1f(31)    Horizontal Total
r14845	r14846
161	168	// R13 = 0x00       Display Start Address (Low)
162	169	}
163	170
164		if (state->m_p2 == 0xd7)
	171	if (m_p2 == 0xd7)
165	172	{
166	173	// CRTC Address
167	174	}
168	175
169		if (state->m_p2 == 0xfb) {
170		state->m_pkr_io_ram[offset] = data;
	176	if (m_p2 == 0xfb) {
	177	m_pkr_io_ram[offset] = data;
171	178	}
172	179
173		if (state->m_p2 == 0xff)
	180	if (m_p2 == 0xff)
174	181	{
175		if (state->m_p1 == 0xdf)
	182	if (m_p1 == 0xdf)
176	183	{
177		state->m_attract_mode = data; // Latch this for use in input reads (0x01 = attract mode, 0x00 = game in progress)
	184	m_attract_mode = data; // Latch this for use in input reads (0x01 = attract mode, 0x00 = game in progress)
178	185	}
179	186
180		if (state->m_p1 == 0xdb || state->m_p1 == 0xef || state->m_p1 == 0xf7 || state->m_p1 == 0xfb)
	187	if (m_p1 == 0xdb || m_p1 == 0xef || m_p1 == 0xf7 || m_p1 == 0xfb)
181	188	{
182	189	// unknown, most likely lamps, meters, hopper etc.
183	190	}
184	191
185	192	// ay8910 control port
186		if (state->m_p1 == 0xfc)
187		ay8910_address_w(space->machine().device("aysnd"), 0, data);
	193	if (m_p1 == 0xfc)
	194	ay8910_address_w(machine().device("aysnd"), 0, data);
188	195
189	196	// ay8910_write_port_0_w
190		if (state->m_p1 == 0xfe)
191		ay8910_data_w(space->machine().device("aysnd"), 0, data);
	197	if (m_p1 == 0xfe)
	198	ay8910_data_w(machine().device("aysnd"), 0, data);
192	199	}
193	200	}
194	201
r14845	r14846
196	203	* Read Handlers *
197	204	****************/
198	205
199		static READ8_HANDLER( t0_r )
	206	READ8_MEMBER(drw80pkr_state::t0_r)
200	207	{
201		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
202		return state->m_t0;
	208	return m_t0;
203	209	}
204	210
205		static READ8_HANDLER( t1_r )
	211	READ8_MEMBER(drw80pkr_state::t1_r)
206	212	{
207		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
208		return state->m_t1;
	213	return m_t1;
209	214	}
210	215
211		static READ8_HANDLER( p0_r )
	216	READ8_MEMBER(drw80pkr_state::p0_r)
212	217	{
213		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
214		return state->m_p0;
	218	return m_p0;
215	219	}
216	220
217		static READ8_HANDLER( p1_r )
	221	READ8_MEMBER(drw80pkr_state::p1_r)
218	222	{
219		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
220		return state->m_p1;
	223	return m_p1;
221	224	}
222	225
223		static READ8_HANDLER( p2_r )
	226	READ8_MEMBER(drw80pkr_state::p2_r)
224	227	{
225		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
226		return state->m_p2;
	228	return m_p2;
227	229	}
228	230
229		static READ8_HANDLER( bus_r )
	231	READ8_MEMBER(drw80pkr_state::bus_r)
230	232	{
231		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
232		return state->m_bus;
	233	return m_bus;
233	234	}
234	235
235		static READ8_HANDLER( drw80pkr_io_r )
	236	READ8_MEMBER(drw80pkr_state::drw80pkr_io_r)
236	237	{
237		drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
238	238	UINT8 ret;
239	239	UINT16 kbdin;
240	240
241	241	ret = 0x00;
242	242
243		if (state->m_p2 == 0x3b)
	243	if (m_p2 == 0x3b)
244	244	{
245	245	// unknown
246	246	}
247	247
248		if (state->m_p2 == 0x7b)
	248	if (m_p2 == 0x7b)
249	249	{
250		ret = state->m_pkr_io_ram[offset];
	250	ret = m_pkr_io_ram[offset];
251	251	}
252	252
253		if (state->m_p2 == 0xf7)
	253	if (m_p2 == 0xf7)
254	254	{
255	255	// unknown
256	256	}
257	257
258		if (state->m_p2 == 0xfb)
	258	if (m_p2 == 0xfb)
259	259	{
260		ret = state->m_pkr_io_ram[offset];
	260	ret = m_pkr_io_ram[offset];
261	261	}
262	262
263		if (state->m_p2 == 0xff)
	263	if (m_p2 == 0xff)
264	264	{
265		if (state->m_p1 == 0x5f || state->m_p1 == 0x9f || state->m_p1 == 0xdb)
	265	if (m_p1 == 0x5f || m_p1 == 0x9f || m_p1 == 0xdb)
266	266	{
267	267	// unknown
268	268	}
269	269
270		if (state->m_p1 == 0xfe)
	270	if (m_p1 == 0xfe)
271	271	{
272	272	// Dip switches tied to sound chip
273	273	//
r14845	r14846
280	280	ret = 0x77; // double-up with credit payout
281	281	}
282	282
283		if ((state->m_attract_mode == 0x01 && state->m_p1 == 0xef) || state->m_p1 == 0xf7)
	283	if ((m_attract_mode == 0x01 && m_p1 == 0xef) || m_p1 == 0xf7)
284	284	{
285	285
286	286	// TODO: Get Input Port Values
287		kbdin = ((input_port_read(space->machine(), "IN1") & 0xaf ) << 8) + input_port_read(space->machine(), "IN0");
	287	kbdin = ((input_port_read(machine(), "IN1") & 0xaf ) << 8) + input_port_read(machine(), "IN0");
288	288
289	289	switch (kbdin)
290	290	{
r14845	r14846
417	417	ADDRESS_MAP_END
418	418
419	419	static ADDRESS_MAP_START( drw80pkr_io_map, AS_IO, 8, drw80pkr_state )
420		AM_RANGE(0x00, 0xff) AM_READWRITE_LEGACY(drw80pkr_io_r, drw80pkr_io_w)
421		AM_RANGE(MCS48_PORT_T0,   MCS48_PORT_T0) AM_READWRITE_LEGACY(t0_r, t0_w)
422		AM_RANGE(MCS48_PORT_T1,   MCS48_PORT_T1) AM_READWRITE_LEGACY(t1_r, t1_w)
423		AM_RANGE(MCS48_PORT_P0,   MCS48_PORT_P0) AM_READWRITE_LEGACY(p0_r, p0_w)
424		AM_RANGE(MCS48_PORT_P1,   MCS48_PORT_P1) AM_READWRITE_LEGACY(p1_r, p1_w)
425		AM_RANGE(MCS48_PORT_P2,   MCS48_PORT_P2) AM_READWRITE_LEGACY(p2_r, p2_w)
426		AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_RAM_WRITE_LEGACY(prog_w)
427		AM_RANGE(MCS48_PORT_BUS,  MCS48_PORT_BUS) AM_READWRITE_LEGACY(bus_r, bus_w)
	420	AM_RANGE(0x00, 0xff) AM_READWRITE(drw80pkr_io_r, drw80pkr_io_w)
	421	AM_RANGE(MCS48_PORT_T0,   MCS48_PORT_T0) AM_READWRITE(t0_r, t0_w)
	422	AM_RANGE(MCS48_PORT_T1,   MCS48_PORT_T1) AM_READWRITE(t1_r, t1_w)
	423	AM_RANGE(MCS48_PORT_P0,   MCS48_PORT_P0) AM_READWRITE(p0_r, p0_w)
	424	AM_RANGE(MCS48_PORT_P1,   MCS48_PORT_P1) AM_READWRITE(p1_r, p1_w)
	425	AM_RANGE(MCS48_PORT_P2,   MCS48_PORT_P2) AM_READWRITE(p2_r, p2_w)
	426	AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_RAM_WRITE(prog_w)
	427	AM_RANGE(MCS48_PORT_BUS,  MCS48_PORT_BUS) AM_READWRITE(bus_r, bus_w)
428	428	ADDRESS_MAP_END
429	429
430	430	/*************************

src/mame/drivers/superdq.c

r14845	r14846
41	41	UINT8 *m_videoram;
42	42	tilemap_t *m_tilemap;
43	43	int m_color_bank;
	44	DECLARE_WRITE8_MEMBER(superdq_videoram_w);
	45	DECLARE_WRITE8_MEMBER(superdq_io_w);
	46	DECLARE_READ8_MEMBER(superdq_ld_r);
	47	DECLARE_WRITE8_MEMBER(superdq_ld_w);
44	48	};
45	49
46	50	static TILE_GET_INFO( get_tile_info )
r14845	r14846
139	143	device_set_input_line(device, 0, ASSERT_LINE);
140	144	}
141	145
142		static WRITE8_HANDLER( superdq_videoram_w )
	146	WRITE8_MEMBER(superdq_state::superdq_videoram_w)
143	147	{
144		superdq_state *state = space->machine().driver_data<superdq_state>();
145	148
146		state->m_videoram[offset] = data;
147		state->m_tilemap->mark_tile_dirty(offset);
	149	m_videoram[offset] = data;
	150	m_tilemap->mark_tile_dirty(offset);
148	151	}
149	152
150		static WRITE8_HANDLER( superdq_io_w )
	153	WRITE8_MEMBER(superdq_state::superdq_io_w)
151	154	{
152		superdq_state *state = space->machine().driver_data<superdq_state>();
153	155	int          i;
154	156	static const UINT8 black_color_entries[] = {7,15,16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
155	157
156	158	if ( data & 0x40 ) /* bit 6 = irqack */
157		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
	159	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
158	160
159		coin_counter_w( space->machine(), 0, data & 0x08 );
160		coin_counter_w( space->machine(), 1, data & 0x04 );
	161	coin_counter_w( machine(), 0, data & 0x08 );
	162	coin_counter_w( machine(), 1, data & 0x04 );
161	163
162		state->m_color_bank = ( data & 2 ) ? 1 : 0;
	164	m_color_bank = ( data & 2 ) ? 1 : 0;
163	165
164	166	for( i = 0; i < ARRAY_LENGTH( black_color_entries ); i++ )
165	167	{
166	168	int index = black_color_entries[i];
167	169	if (data & 0x80)
168		palette_set_color(space->machine(), index, palette_get_color(space->machine(), index) & MAKE_ARGB(0,255,255,255));
	170	palette_set_color(machine(), index, palette_get_color(machine(), index) & MAKE_ARGB(0,255,255,255));
169	171	else
170		palette_set_color(space->machine(), index, palette_get_color(space->machine(), index) | MAKE_ARGB(255,0,0,0));
	172	palette_set_color(machine(), index, palette_get_color(machine(), index) | MAKE_ARGB(255,0,0,0));
171	173	}
172	174
173	175	/*
r14845	r14846
177	179	*/
178	180	}
179	181
180		static READ8_HANDLER( superdq_ld_r )
	182	READ8_MEMBER(superdq_state::superdq_ld_r)
181	183	{
182		superdq_state *state = space->machine().driver_data<superdq_state>();
183	184
184		return state->m_ld_in_latch;
	185	return m_ld_in_latch;
185	186	}
186	187
187		static WRITE8_HANDLER( superdq_ld_w )
	188	WRITE8_MEMBER(superdq_state::superdq_ld_w)
188	189	{
189		superdq_state *state = space->machine().driver_data<superdq_state>();
190	190
191		state->m_ld_out_latch = data;
	191	m_ld_out_latch = data;
192	192	}
193	193
194	194
r14845	r14846
202	202	static ADDRESS_MAP_START( superdq_map, AS_PROGRAM, 8, superdq_state )
203	203	AM_RANGE(0x0000, 0x3fff) AM_ROM
204	204	AM_RANGE(0x4000, 0x47ff) AM_RAM
205		AM_RANGE(0x5c00, 0x5fff) AM_RAM_WRITE_LEGACY(superdq_videoram_w) AM_BASE(m_videoram)
	205	AM_RANGE(0x5c00, 0x5fff) AM_RAM_WRITE(superdq_videoram_w) AM_BASE(m_videoram)
206	206	ADDRESS_MAP_END
207	207
208	208	static ADDRESS_MAP_START( superdq_io, AS_IO, 8, superdq_state )
209	209	ADDRESS_MAP_GLOBAL_MASK(0xff)
210		AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0") AM_WRITE_LEGACY(superdq_ld_w)
	210	AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0") AM_WRITE(superdq_ld_w)
211	211	AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1")
212	212	AM_RANGE(0x02, 0x02) AM_READ_PORT("DSW1")
213	213	AM_RANGE(0x03, 0x03) AM_READ_PORT("DSW2")
214		AM_RANGE(0x04, 0x04) AM_READ_LEGACY(superdq_ld_r) AM_DEVWRITE_LEGACY("snsnd", sn76496_w)
215		AM_RANGE(0x08, 0x08) AM_WRITE_LEGACY(superdq_io_w)
	214	AM_RANGE(0x04, 0x04) AM_READ(superdq_ld_r) AM_DEVWRITE_LEGACY("snsnd", sn76496_w)
	215	AM_RANGE(0x08, 0x08) AM_WRITE(superdq_io_w)
216	216	AM_RANGE(0x0c, 0x0d) AM_NOP /* HD46505S */
217	217	ADDRESS_MAP_END
218	218

src/mame/drivers/bestleag.c

r14845	r14846
38	38	tilemap_t *m_fg_tilemap;
39	39	UINT16 *m_spriteram;
40	40	size_t m_spriteram_size;
	41	DECLARE_WRITE16_MEMBER(bestleag_txram_w);
	42	DECLARE_WRITE16_MEMBER(bestleag_bgram_w);
	43	DECLARE_WRITE16_MEMBER(bestleag_fgram_w);
41	44	};
42	45
43	46
r14845	r14846
197	200	return 0;
198	201	}
199	202
200		static WRITE16_HANDLER( bestleag_txram_w )
	203	WRITE16_MEMBER(bestleag_state::bestleag_txram_w)
201	204	{
202		bestleag_state *state = space->machine().driver_data<bestleag_state>();
203		state->m_txram[offset] = data;
204		state->m_tx_tilemap->mark_tile_dirty(offset);
	205	m_txram[offset] = data;
	206	m_tx_tilemap->mark_tile_dirty(offset);
205	207	}
206	208
207		static WRITE16_HANDLER( bestleag_bgram_w )
	209	WRITE16_MEMBER(bestleag_state::bestleag_bgram_w)
208	210	{
209		bestleag_state *state = space->machine().driver_data<bestleag_state>();
210		state->m_bgram[offset] = data;
211		state->m_bg_tilemap->mark_tile_dirty(offset);
	211	m_bgram[offset] = data;
	212	m_bg_tilemap->mark_tile_dirty(offset);
212	213	}
213	214
214		static WRITE16_HANDLER( bestleag_fgram_w )
	215	WRITE16_MEMBER(bestleag_state::bestleag_fgram_w)
215	216	{
216		bestleag_state *state = space->machine().driver_data<bestleag_state>();
217		state->m_fgram[offset] = data;
218		state->m_fg_tilemap->mark_tile_dirty(offset);
	217	m_fgram[offset] = data;
	218	m_fg_tilemap->mark_tile_dirty(offset);
219	219	}
220	220
221	221	static WRITE16_DEVICE_HANDLER( oki_bank_w )
r14845	r14846
230	230	static ADDRESS_MAP_START( bestleag_map, AS_PROGRAM, 16, bestleag_state )
231	231	AM_RANGE(0x000000, 0x03ffff) AM_ROM
232	232	AM_RANGE(0x0d2000, 0x0d3fff) AM_NOP // left over from the original game (only read / written in memory test)
233		AM_RANGE(0x0e0000, 0x0e3fff) AM_RAM_WRITE_LEGACY(bestleag_bgram_w) AM_BASE(m_bgram)
234		AM_RANGE(0x0e8000, 0x0ebfff) AM_RAM_WRITE_LEGACY(bestleag_fgram_w) AM_BASE(m_fgram)
235		AM_RANGE(0x0f0000, 0x0f3fff) AM_RAM_WRITE_LEGACY(bestleag_txram_w) AM_BASE(m_txram)
	233	AM_RANGE(0x0e0000, 0x0e3fff) AM_RAM_WRITE(bestleag_bgram_w) AM_BASE(m_bgram)
	234	AM_RANGE(0x0e8000, 0x0ebfff) AM_RAM_WRITE(bestleag_fgram_w) AM_BASE(m_fgram)
	235	AM_RANGE(0x0f0000, 0x0f3fff) AM_RAM_WRITE(bestleag_txram_w) AM_BASE(m_txram)
236	236	AM_RANGE(0x0f8000, 0x0f800b) AM_RAM AM_BASE(m_vregs)
237	237	AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE_LEGACY(paletteram16_RRRRGGGGBBBBRGBx_word_w) AM_BASE_GENERIC(paletteram)
238	238	AM_RANGE(0x200000, 0x200fff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)

src/mame/drivers/tomcat.c

r14845	r14846
47	47	UINT8 m_nvram[0x800];
48	48	int m_dsp_BIO;
49	49	int m_dsp_idle;
	50	DECLARE_WRITE16_MEMBER(tomcat_adcon_w);
	51	DECLARE_READ16_MEMBER(tomcat_adcread_r);
	52	DECLARE_READ16_MEMBER(tomcat_inputs_r);
	53	DECLARE_WRITE16_MEMBER(tomcat_led1on_w);
	54	DECLARE_WRITE16_MEMBER(tomcat_led2on_w);
	55	DECLARE_WRITE16_MEMBER(tomcat_led2off_w);
	56	DECLARE_WRITE16_MEMBER(tomcat_led1off_w);
	57	DECLARE_WRITE16_MEMBER(tomcat_lnkmodel_w);
	58	DECLARE_WRITE16_MEMBER(tomcat_errl_w);
	59	DECLARE_WRITE16_MEMBER(tomcat_errh_w);
	60	DECLARE_WRITE16_MEMBER(tomcat_ackl_w);
	61	DECLARE_WRITE16_MEMBER(tomcat_ackh_w);
	62	DECLARE_WRITE16_MEMBER(tomcat_lnkmodeh_w);
	63	DECLARE_WRITE16_MEMBER(tomcat_txbuffl_w);
	64	DECLARE_WRITE16_MEMBER(tomcat_txbuffh_w);
	65	DECLARE_WRITE16_MEMBER(tomcat_sndresl_w);
	66	DECLARE_WRITE16_MEMBER(tomcat_sndresh_w);
	67	DECLARE_WRITE16_MEMBER(tomcat_mresl_w);
	68	DECLARE_WRITE16_MEMBER(tomcat_mresh_w);
	69	DECLARE_WRITE16_MEMBER(tomcat_irqclr_w);
	70	DECLARE_READ16_MEMBER(tomcat_inputs2_r);
	71	DECLARE_READ16_MEMBER(tomcat_320bio_r);
	72	DECLARE_READ16_MEMBER(dsp_BIO_r);
	73	DECLARE_READ16_MEMBER(tomcat_shared_ram_r);
	74	DECLARE_WRITE16_MEMBER(tomcat_shared_ram_w);
	75	DECLARE_READ8_MEMBER(tomcat_nvram_r);
	76	DECLARE_WRITE8_MEMBER(tomcat_nvram_w);
	77	DECLARE_WRITE8_MEMBER(soundlatches_w);
50	78	};
51	79
52	80
53	81
54		static WRITE16_HANDLER(tomcat_adcon_w)
	82	WRITE16_MEMBER(tomcat_state::tomcat_adcon_w)
55	83	{
56		tomcat_state *state = space->machine().driver_data<tomcat_state>();
57		state->m_control_num = data;
	84	m_control_num = data;
58	85	}
59	86
60		static READ16_HANDLER(tomcat_adcread_r)
	87	READ16_MEMBER(tomcat_state::tomcat_adcread_r)
61	88	{
62		tomcat_state *state = space->machine().driver_data<tomcat_state>();
63		switch( state->m_control_num )
	89	switch( m_control_num )
64	90	{
65		case 0: return input_port_read(space->machine(), "STICKY");
66		case 1: return input_port_read(space->machine(), "STICKX");
	91	case 0: return input_port_read(machine(), "STICKY");
	92	case 1: return input_port_read(machine(), "STICKX");
67	93	default: return 0x7f7f;
68	94	}
69	95	}
70	96
71		static READ16_HANDLER(tomcat_inputs_r)
	97	READ16_MEMBER(tomcat_state::tomcat_inputs_r)
72	98	{
73	99	UINT16 result = 0;
74	100	if (ACCESSING_BITS_8_15)
75		result |= input_port_read(space->machine(), "IN0") << 8;
	101	result |= input_port_read(machine(), "IN0") << 8;
76	102
77	103	return result;
78	104	}
79	105
80		static WRITE16_HANDLER(tomcat_led1on_w)
	106	WRITE16_MEMBER(tomcat_state::tomcat_led1on_w)
81	107	{
82		set_led_status(space->machine(), 1, 1);
	108	set_led_status(machine(), 1, 1);
83	109	}
84	110
85		static WRITE16_HANDLER(tomcat_led2on_w)
	111	WRITE16_MEMBER(tomcat_state::tomcat_led2on_w)
86	112	{
87		set_led_status(space->machine(), 2, 1);
	113	set_led_status(machine(), 2, 1);
88	114	}
89	115
90		static WRITE16_HANDLER(tomcat_led2off_w)
	116	WRITE16_MEMBER(tomcat_state::tomcat_led2off_w)
91	117	{
92		set_led_status(space->machine(), 2, 0);
	118	set_led_status(machine(), 2, 0);
93	119	}
94	120
95		static WRITE16_HANDLER(tomcat_led1off_w)
	121	WRITE16_MEMBER(tomcat_state::tomcat_led1off_w)
96	122	{
97		set_led_status(space->machine(), 1, 0);
	123	set_led_status(machine(), 1, 0);
98	124	}
99	125
100		static WRITE16_HANDLER(tomcat_lnkmodel_w)
	126	WRITE16_MEMBER(tomcat_state::tomcat_lnkmodel_w)
101	127	{
102	128	// Link Mode Low (address strobe)
103	129	// Master does not respond to Interrupts
104	130	}
105	131
106		static WRITE16_HANDLER(tomcat_errl_w)
	132	WRITE16_MEMBER(tomcat_state::tomcat_errl_w)
107	133	{
108	134	// Link Error Flag Low (address strobe)
109	135	}
110	136
111		static WRITE16_HANDLER(tomcat_errh_w)
	137	WRITE16_MEMBER(tomcat_state::tomcat_errh_w)
112	138	{
113	139	// Link Error Flag High (address strobe)
114	140	}
115	141
116		static WRITE16_HANDLER(tomcat_ackl_w)
	142	WRITE16_MEMBER(tomcat_state::tomcat_ackl_w)
117	143	{
118	144	// Link ACK Flag Low (address strobe)
119	145	}
120	146
121		static WRITE16_HANDLER(tomcat_ackh_w)
	147	WRITE16_MEMBER(tomcat_state::tomcat_ackh_w)
122	148	{
123	149	// Link ACK Flag High (address strobe)
124	150	}
125	151
126		static WRITE16_HANDLER(tomcat_lnkmodeh_w)
	152	WRITE16_MEMBER(tomcat_state::tomcat_lnkmodeh_w)
127	153	{
128	154	// Link Mode high (address strobe)
129	155	}
130	156
131		static WRITE16_HANDLER(tomcat_txbuffl_w)
	157	WRITE16_MEMBER(tomcat_state::tomcat_txbuffl_w)
132	158	{
133	159	// Link Buffer Control (address strobe)
134	160	}
135	161
136		static WRITE16_HANDLER(tomcat_txbuffh_w)
	162	WRITE16_MEMBER(tomcat_state::tomcat_txbuffh_w)
137	163	{
138	164	// Link Buffer Control high (address strobe)
139	165	// Turn off TX (Link) Buffer
140	166	}
141	167
142		static WRITE16_HANDLER(tomcat_sndresl_w)
	168	WRITE16_MEMBER(tomcat_state::tomcat_sndresl_w)
143	169	{
144	170	// Sound Reset Low       (Address Strobe)
145	171	// Reset Sound System
146	172	}
147	173
148		static WRITE16_HANDLER(tomcat_sndresh_w)
	174	WRITE16_MEMBER(tomcat_state::tomcat_sndresh_w)
149	175	{
150	176	// Sound Reset high      (Address Strobe)
151	177	// Release reset of sound system
152	178	}
153	179
154		static WRITE16_HANDLER(tomcat_mresl_w)
	180	WRITE16_MEMBER(tomcat_state::tomcat_mresl_w)
155	181	{
156	182	// 320 Reset Low         (Address Strobe)
157	183	// Reset TMS320
158		device_set_input_line(space->machine().device("dsp"), INPUT_LINE_RESET, ASSERT_LINE);
	184	device_set_input_line(machine().device("dsp"), INPUT_LINE_RESET, ASSERT_LINE);
159	185	}
160	186
161		static WRITE16_HANDLER(tomcat_mresh_w)
	187	WRITE16_MEMBER(tomcat_state::tomcat_mresh_w)
162	188	{
163		tomcat_state *state = space->machine().driver_data<tomcat_state>();
164	189	// 320 Reset high        (Address Strobe)
165	190	// Release reset of TMS320
166		state->m_dsp_BIO = 0;
167		device_set_input_line(space->machine().device("dsp"), INPUT_LINE_RESET, CLEAR_LINE);
	191	m_dsp_BIO = 0;
	192	device_set_input_line(machine().device("dsp"), INPUT_LINE_RESET, CLEAR_LINE);
168	193	}
169	194
170		static WRITE16_HANDLER(tomcat_irqclr_w)
	195	WRITE16_MEMBER(tomcat_state::tomcat_irqclr_w)
171	196	{
172	197	// Clear IRQ Latch          (Address Strobe)
173		cputag_set_input_line(space->machine(), "maincpu", 1, CLEAR_LINE);
	198	cputag_set_input_line(machine(), "maincpu", 1, CLEAR_LINE);
174	199	}
175	200
176		static READ16_HANDLER(tomcat_inputs2_r)
	201	READ16_MEMBER(tomcat_state::tomcat_inputs2_r)
177	202	{
178		tomcat_state *state = space->machine().driver_data<tomcat_state>();
179	203	/*
180	204	*       D15 LNKFLAG     (Game Link)
181	205	*       D14 PC3        "    "
r14845	r14846
186	210	*       D9  /IDLE*      (TMS320 System)
187	211	*       D8
188	212	*/
189		return state->m_dsp_idle ? 0 : (1 << 9);
	213	return m_dsp_idle ? 0 : (1 << 9);
190	214	}
191	215
192		static READ16_HANDLER(tomcat_320bio_r)
	216	READ16_MEMBER(tomcat_state::tomcat_320bio_r)
193	217	{
194		tomcat_state *state = space->machine().driver_data<tomcat_state>();
195		state->m_dsp_BIO = 1;
196		space->machine().device<cpu_device>("maincpu")->suspend(SUSPEND_REASON_SPIN, 1);
	218	m_dsp_BIO = 1;
	219	machine().device<cpu_device>("maincpu")->suspend(SUSPEND_REASON_SPIN, 1);
197	220	return 0;
198	221	}
199	222
200		static READ16_HANDLER(dsp_BIO_r)
	223	READ16_MEMBER(tomcat_state::dsp_BIO_r)
201	224	{
202		tomcat_state *state = space->machine().driver_data<tomcat_state>();
203		if ( cpu_get_pc(&space->device()) == 0x0001 )
	225	if ( cpu_get_pc(&space.device()) == 0x0001 )
204	226	{
205		if ( state->m_dsp_idle == 0 )
	227	if ( m_dsp_idle == 0 )
206	228	{
207		state->m_dsp_idle = 1;
208		state->m_dsp_BIO = 0;
	229	m_dsp_idle = 1;
	230	m_dsp_BIO = 0;
209	231	}
210		return !state->m_dsp_BIO;
	232	return !m_dsp_BIO;
211	233	}
212		else if ( cpu_get_pc(&space->device()) == 0x0003 )
	234	else if ( cpu_get_pc(&space.device()) == 0x0003 )
213	235	{
214		if ( state->m_dsp_BIO == 1 )
	236	if ( m_dsp_BIO == 1 )
215	237	{
216		state->m_dsp_idle = 0;
217		state->m_dsp_BIO = 0;
218		space->machine().device<cpu_device>("maincpu")->resume(SUSPEND_REASON_SPIN );
	238	m_dsp_idle = 0;
	239	m_dsp_BIO = 0;
	240	machine().device<cpu_device>("maincpu")->resume(SUSPEND_REASON_SPIN );
219	241	return 0;
220	242	}
221	243	else
r14845	r14846
226	248	}
227	249	else
228	250	{
229		return !state->m_dsp_BIO;
	251	return !m_dsp_BIO;
230	252	}
231	253	}
232	254
233		static READ16_HANDLER(tomcat_shared_ram_r)
	255	READ16_MEMBER(tomcat_state::tomcat_shared_ram_r)
234	256	{
235		tomcat_state *state = space->machine().driver_data<tomcat_state>();
236		return state->m_shared_ram[offset];
	257	return m_shared_ram[offset];
237	258	}
238	259
239		static WRITE16_HANDLER(tomcat_shared_ram_w)
	260	WRITE16_MEMBER(tomcat_state::tomcat_shared_ram_w)
240	261	{
241		tomcat_state *state = space->machine().driver_data<tomcat_state>();
242		COMBINE_DATA(&state->m_shared_ram[offset]);
	262	COMBINE_DATA(&m_shared_ram[offset]);
243	263	}
244	264
245		static READ8_HANDLER(tomcat_nvram_r)
	265	READ8_MEMBER(tomcat_state::tomcat_nvram_r)
246	266	{
247		tomcat_state *state = space->machine().driver_data<tomcat_state>();
248		return state->m_nvram[offset];
	267	return m_nvram[offset];
249	268	}
250	269
251		static WRITE8_HANDLER(tomcat_nvram_w)
	270	WRITE8_MEMBER(tomcat_state::tomcat_nvram_w)
252	271	{
253		tomcat_state *state = space->machine().driver_data<tomcat_state>();
254		state->m_nvram[offset] = data;
	272	m_nvram[offset] = data;
255	273	}
256	274
257	275	static ADDRESS_MAP_START( tomcat_map, AS_PROGRAM, 16, tomcat_state )
258	276	AM_RANGE(0x000000, 0x00ffff) AM_ROM
259		AM_RANGE(0x402000, 0x402001) AM_READ_LEGACY(tomcat_adcread_r) AM_WRITE_LEGACY(tomcat_adcon_w)
260		AM_RANGE(0x404000, 0x404001) AM_READ_LEGACY(tomcat_inputs_r) AM_WRITE_LEGACY(avgdvg_go_word_w)
	277	AM_RANGE(0x402000, 0x402001) AM_READ(tomcat_adcread_r) AM_WRITE(tomcat_adcon_w)
	278	AM_RANGE(0x404000, 0x404001) AM_READ(tomcat_inputs_r) AM_WRITE_LEGACY(avgdvg_go_word_w)
261	279	AM_RANGE(0x406000, 0x406001) AM_WRITE_LEGACY(avgdvg_reset_word_w)
262		AM_RANGE(0x408000, 0x408001) AM_READWRITE_LEGACY(tomcat_inputs2_r, watchdog_reset16_w)
263		AM_RANGE(0x40a000, 0x40a001) AM_READWRITE_LEGACY(tomcat_320bio_r, tomcat_irqclr_w)
264		AM_RANGE(0x40e000, 0x40e001) AM_WRITE_LEGACY(tomcat_led1on_w)
265		AM_RANGE(0x40e002, 0x40e003) AM_WRITE_LEGACY(tomcat_led2on_w)
266		AM_RANGE(0x40e004, 0x40e005) AM_WRITE_LEGACY(tomcat_mresl_w)
267		AM_RANGE(0x40e006, 0x40e007) AM_WRITE_LEGACY(tomcat_sndresl_w)
268		AM_RANGE(0x40e008, 0x40e009) AM_WRITE_LEGACY(tomcat_lnkmodel_w)
269		AM_RANGE(0x40e00a, 0x40e00b) AM_WRITE_LEGACY(tomcat_errl_w)
270		AM_RANGE(0x40e00c, 0x40e00d) AM_WRITE_LEGACY(tomcat_ackl_w)
271		AM_RANGE(0x40e00e, 0x40e00f) AM_WRITE_LEGACY(tomcat_txbuffl_w)
272		AM_RANGE(0x40e010, 0x40e011) AM_WRITE_LEGACY(tomcat_led1off_w)
273		AM_RANGE(0x40e012, 0x40e013) AM_WRITE_LEGACY(tomcat_led2off_w)
274		AM_RANGE(0x40e014, 0x40e015) AM_WRITE_LEGACY(tomcat_mresh_w)
275		AM_RANGE(0x40e016, 0x40e017) AM_WRITE_LEGACY(tomcat_sndresh_w)
276		AM_RANGE(0x40e018, 0x40e019) AM_WRITE_LEGACY(tomcat_lnkmodeh_w)
277		AM_RANGE(0x40e01a, 0x40e01b) AM_WRITE_LEGACY(tomcat_errh_w)
278		AM_RANGE(0x40e01c, 0x40e01d) AM_WRITE_LEGACY(tomcat_ackh_w)
279		AM_RANGE(0x40e01e, 0x40e01f) AM_WRITE_LEGACY(tomcat_txbuffh_w)
	280	AM_RANGE(0x408000, 0x408001) AM_READWRITE(tomcat_inputs2_r, watchdog_reset16_w)
	281	AM_RANGE(0x40a000, 0x40a001) AM_READWRITE(tomcat_320bio_r, tomcat_irqclr_w)
	282	AM_RANGE(0x40e000, 0x40e001) AM_WRITE(tomcat_led1on_w)
	283	AM_RANGE(0x40e002, 0x40e003) AM_WRITE(tomcat_led2on_w)
	284	AM_RANGE(0x40e004, 0x40e005) AM_WRITE(tomcat_mresl_w)
	285	AM_RANGE(0x40e006, 0x40e007) AM_WRITE(tomcat_sndresl_w)
	286	AM_RANGE(0x40e008, 0x40e009) AM_WRITE(tomcat_lnkmodel_w)
	287	AM_RANGE(0x40e00a, 0x40e00b) AM_WRITE(tomcat_errl_w)
	288	AM_RANGE(0x40e00c, 0x40e00d) AM_WRITE(tomcat_ackl_w)
	289	AM_RANGE(0x40e00e, 0x40e00f) AM_WRITE(tomcat_txbuffl_w)
	290	AM_RANGE(0x40e010, 0x40e011) AM_WRITE(tomcat_led1off_w)
	291	AM_RANGE(0x40e012, 0x40e013) AM_WRITE(tomcat_led2off_w)
	292	AM_RANGE(0x40e014, 0x40e015) AM_WRITE(tomcat_mresh_w)
	293	AM_RANGE(0x40e016, 0x40e017) AM_WRITE(tomcat_sndresh_w)
	294	AM_RANGE(0x40e018, 0x40e019) AM_WRITE(tomcat_lnkmodeh_w)
	295	AM_RANGE(0x40e01a, 0x40e01b) AM_WRITE(tomcat_errh_w)
	296	AM_RANGE(0x40e01c, 0x40e01d) AM_WRITE(tomcat_ackh_w)
	297	AM_RANGE(0x40e01e, 0x40e01f) AM_WRITE(tomcat_txbuffh_w)
280	298	AM_RANGE(0x800000, 0x803fff) AM_RAM AM_BASE_LEGACY((UINT16**)&avgdvg_vectorram) AM_SIZE_LEGACY(&avgdvg_vectorram_size)
281		AM_RANGE(0xffa000, 0xffbfff) AM_READWRITE_LEGACY(tomcat_shared_ram_r, tomcat_shared_ram_w)
	299	AM_RANGE(0xffa000, 0xffbfff) AM_READWRITE(tomcat_shared_ram_r, tomcat_shared_ram_w)
282	300	AM_RANGE(0xffc000, 0xffcfff) AM_RAM
283	301	AM_RANGE(0xffd000, 0xffdfff) AM_DEVREADWRITE8_LEGACY("m48t02", timekeeper_r, timekeeper_w, 0xff00)
284		AM_RANGE(0xffd000, 0xffdfff) AM_READWRITE8_LEGACY(tomcat_nvram_r, tomcat_nvram_w, 0x00ff)
	302	AM_RANGE(0xffd000, 0xffdfff) AM_READWRITE8(tomcat_nvram_r, tomcat_nvram_w, 0x00ff)
285	303	ADDRESS_MAP_END
286	304
287	305	static ADDRESS_MAP_START( dsp_map, AS_PROGRAM, 16, tomcat_state )
r14845	r14846
289	307	ADDRESS_MAP_END
290	308
291	309	static ADDRESS_MAP_START( dsp_io_map, AS_IO, 16, tomcat_state )
292		AM_RANGE(TMS32010_BIO, TMS32010_BIO) AM_READ_LEGACY(dsp_BIO_r)
	310	AM_RANGE(TMS32010_BIO, TMS32010_BIO) AM_READ(dsp_BIO_r)
293	311	ADDRESS_MAP_END
294	312
295		static WRITE8_HANDLER(soundlatches_w)
	313	WRITE8_MEMBER(tomcat_state::soundlatches_w)
296	314	{
297	315	switch(offset)
298	316	{
r14845	r14846
309	327	static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, tomcat_state )
310	328	AM_RANGE(0x0000, 0x1fff) AM_RAM
311	329	AM_RANGE(0x2000, 0x2001) AM_DEVREADWRITE_LEGACY("ymsnd", ym2151_r, ym2151_w)
312		AM_RANGE(0x3000, 0x30df) AM_WRITE_LEGACY(soundlatches_w)
	330	AM_RANGE(0x3000, 0x30df) AM_WRITE(soundlatches_w)
313	331	AM_RANGE(0x30e0, 0x30e0) AM_NOP // COINRD Inputs: D7 = Coin L, D6 = Coin R, D5 = SOUNDFLAG
314	332	AM_RANGE(0x5000, 0x507f) AM_RAM   // 6532 ram
315	333	AM_RANGE(0x5080, 0x509f) AM_DEVREADWRITE_LEGACY("riot", riot6532_r, riot6532_w)

src/mame/drivers/xtheball.c

r14845	r14846
23	23	UINT16 *m_vram_bg;
24	24	UINT16 *m_vram_fg;
25	25	UINT8 m_bitvals[32];
	26	DECLARE_WRITE16_MEMBER(bit_controls_w);
	27	DECLARE_READ16_MEMBER(analogx_r);
	28	DECLARE_READ16_MEMBER(analogy_watchdog_r);
26	29	};
27	30
28	31
r14845	r14846
115	118	*
116	119	*************************************/
117	120
118		static WRITE16_HANDLER( bit_controls_w )
	121	WRITE16_MEMBER(xtheball_state::bit_controls_w)
119	122	{
120		xtheball_state *state = space->machine().driver_data<xtheball_state>();
121		UINT8 *bitvals = state->m_bitvals;
	123	UINT8 *bitvals = m_bitvals;
122	124	if (ACCESSING_BITS_0_7)
123	125	{
124	126	if (bitvals[offset] != (data & 1))
125	127	{
126		logerror("%08x:bit_controls_w(%x,%d)\n", cpu_get_pc(&space->device()), offset, data & 1);
	128	logerror("%08x:bit_controls_w(%x,%d)\n", cpu_get_pc(&space.device()), offset, data & 1);
127	129
128	130	switch (offset)
129	131	{
130	132	case 7:
131		ticket_dispenser_w(space->machine().device("ticket"), 0, data << 7);
	133	ticket_dispenser_w(machine().device("ticket"), 0, data << 7);
132	134	break;
133	135
134	136	case 8:
135		set_led_status(space->machine(), 0, data & 1);
	137	set_led_status(machine(), 0, data & 1);
136	138	break;
137	139	}
138	140	}
r14845	r14846
185	187	*
186	188	*************************************/
187	189
188		static READ16_HANDLER( analogx_r )
	190	READ16_MEMBER(xtheball_state::analogx_r)
189	191	{
190		return (input_port_read(space->machine(), "ANALOGX") << 8) | 0x00ff;
	192	return (input_port_read(machine(), "ANALOGX") << 8) | 0x00ff;
191	193	}
192	194
193	195
194		static READ16_HANDLER( analogy_watchdog_r )
	196	READ16_MEMBER(xtheball_state::analogy_watchdog_r)
195	197	{
196	198	/* doubles as a watchdog address */
197	199	watchdog_reset_w(space,0,0);
198		return (input_port_read(space->machine(), "ANALOGY") << 8) | 0x00ff;
	200	return (input_port_read(machine(), "ANALOGY") << 8) | 0x00ff;
199	201	}
200	202
201	203
r14845	r14846
211	213	AM_RANGE(0x01000000, 0x010fffff) AM_RAM AM_BASE(m_vram_bg)
212	214	AM_RANGE(0x02000000, 0x020fffff) AM_RAM AM_BASE(m_vram_fg)
213	215	AM_RANGE(0x03000000, 0x030000ff) AM_DEVREADWRITE8_LEGACY("tlc34076", tlc34076_r, tlc34076_w, 0x00ff)
214		AM_RANGE(0x03040000, 0x030401ff) AM_WRITE_LEGACY(bit_controls_w)
	216	AM_RANGE(0x03040000, 0x030401ff) AM_WRITE(bit_controls_w)
215	217	AM_RANGE(0x03040080, 0x0304008f) AM_READ_PORT("DSW")
216		AM_RANGE(0x03040100, 0x0304010f) AM_READ_LEGACY(analogx_r)
	218	AM_RANGE(0x03040100, 0x0304010f) AM_READ(analogx_r)
217	219	AM_RANGE(0x03040110, 0x0304011f) AM_READ_PORT("COIN1")
218	220	AM_RANGE(0x03040130, 0x0304013f) AM_READ_PORT("SERVICE2")
219	221	AM_RANGE(0x03040140, 0x0304014f) AM_READ_PORT("COIN3")
220	222	AM_RANGE(0x03040150, 0x0304015f) AM_READ_PORT("BUTTON1")
221	223	AM_RANGE(0x03040160, 0x0304016f) AM_READ_PORT("SERVICE")
222	224	AM_RANGE(0x03040170, 0x0304017f) AM_READ_PORT("SERVICE1")
223		AM_RANGE(0x03040180, 0x0304018f) AM_READ_LEGACY(analogy_watchdog_r)
	225	AM_RANGE(0x03040180, 0x0304018f) AM_READ(analogy_watchdog_r)
224	226	AM_RANGE(0x03060000, 0x0306000f) AM_DEVWRITE8_LEGACY("dac", dac_w, 0xff00)
225	227	AM_RANGE(0x04000000, 0x057fffff) AM_ROM AM_REGION("user2", 0)
226	228	AM_RANGE(0xc0000000, 0xc00001ff) AM_READWRITE_LEGACY(tms34010_io_register_r, tms34010_io_register_w)

src/mame/drivers/maxaflex.c

r14845	r14846
40	40	UINT8 m_tdr;
41	41	UINT8 m_tcr;
42	42	timer_device *m_mcu_timer;
	43	DECLARE_READ8_MEMBER(mcu_portA_r);
	44	DECLARE_WRITE8_MEMBER(mcu_portA_w);
	45	DECLARE_READ8_MEMBER(mcu_portB_r);
	46	DECLARE_WRITE8_MEMBER(mcu_portB_w);
	47	DECLARE_READ8_MEMBER(mcu_portC_r);
	48	DECLARE_WRITE8_MEMBER(mcu_portC_w);
	49	DECLARE_READ8_MEMBER(mcu_ddr_r);
	50	DECLARE_WRITE8_MEMBER(mcu_portA_ddr_w);
	51	DECLARE_WRITE8_MEMBER(mcu_portB_ddr_w);
	52	DECLARE_WRITE8_MEMBER(mcu_portC_ddr_w);
	53	DECLARE_READ8_MEMBER(mcu_tdr_r);
	54	DECLARE_WRITE8_MEMBER(mcu_tdr_w);
	55	DECLARE_READ8_MEMBER(mcu_tcr_r);
	56	DECLARE_WRITE8_MEMBER(mcu_tcr_w);
43	57	};
44	58
45	59
r14845	r14846
58	72	7   (out) AUDIO
59	73	*/
60	74
61		static READ8_HANDLER( mcu_portA_r )
	75	READ8_MEMBER(maxaflex_state::mcu_portA_r)
62	76	{
63		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
64		state->m_portA_in = input_port_read(space->machine(), "dsw") | (input_port_read(space->machine(), "coin") << 4) | (input_port_read(space->machine(), "console") << 5);
65		return (state->m_portA_in & ~state->m_ddrA) | (state->m_portA_out & state->m_ddrA);
	77	m_portA_in = input_port_read(machine(), "dsw") | (input_port_read(machine(), "coin") << 4) | (input_port_read(machine(), "console") << 5);
	78	return (m_portA_in & ~m_ddrA) | (m_portA_out & m_ddrA);
66	79	}
67	80
68		static WRITE8_HANDLER( mcu_portA_w )
	81	WRITE8_MEMBER(maxaflex_state::mcu_portA_w)
69	82	{
70		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
71		state->m_portA_out = data;
72		speaker_level_w(space->machine().device("speaker"), data >> 7);
	83	m_portA_out = data;
	84	speaker_level_w(machine().device("speaker"), data >> 7);
73	85	}
74	86
75	87	/* Port B:
r14845	r14846
83	95	7   (out)   TOFF - enables/disables user controls
84	96	*/
85	97
86		static READ8_HANDLER( mcu_portB_r )
	98	READ8_MEMBER(maxaflex_state::mcu_portB_r)
87	99	{
88		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
89		return (state->m_portB_in & ~state->m_ddrB) | (state->m_portB_out & state->m_ddrB);
	100	return (m_portB_in & ~m_ddrB) | (m_portB_out & m_ddrB);
90	101	}
91	102
92		static WRITE8_HANDLER( mcu_portB_w )
	103	WRITE8_MEMBER(maxaflex_state::mcu_portB_w)
93	104	{
94		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
95		UINT8 diff = data ^ state->m_portB_out;
96		state->m_portB_out = data;
	105	UINT8 diff = data ^ m_portB_out;
	106	m_portB_out = data;
97	107
98	108	/* clear coin interrupt */
99	109	if (data & 0x04)
100		cputag_set_input_line(space->machine(), "mcu", M6805_IRQ_LINE, CLEAR_LINE );
	110	cputag_set_input_line(machine(), "mcu", M6805_IRQ_LINE, CLEAR_LINE );
101	111
102	112	/* AUDMUTE */
103		space->machine().sound().system_enable((data >> 5) & 1);
	113	machine().sound().system_enable((data >> 5) & 1);
104	114
105	115	/* RES600 */
106	116	if (diff & 0x10)
107		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_RESET, (data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
	117	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_RESET, (data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
108	118
109	119	/* latch for lamps */
110	120	if ((diff & 0x40) && !(data & 0x40))
111	121	{
112		output_set_lamp_value(0, (state->m_portC_out >> 0) & 1);
113		output_set_lamp_value(1, (state->m_portC_out >> 1) & 1);
114		output_set_lamp_value(2, (state->m_portC_out >> 2) & 1);
115		output_set_lamp_value(3, (state->m_portC_out >> 3) & 1);
	122	output_set_lamp_value(0, (m_portC_out >> 0) & 1);
	123	output_set_lamp_value(1, (m_portC_out >> 1) & 1);
	124	output_set_lamp_value(2, (m_portC_out >> 2) & 1);
	125	output_set_lamp_value(3, (m_portC_out >> 3) & 1);
116	126	}
117	127	}
118	128
r14845	r14846
122	132	2   (out)   lamp START
123	133	3   (out)   lamp OVER */
124	134
125		static READ8_HANDLER( mcu_portC_r )
	135	READ8_MEMBER(maxaflex_state::mcu_portC_r)
126	136	{
127		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
128		return (state->m_portC_in & ~state->m_ddrC) | (state->m_portC_out & state->m_ddrC);
	137	return (m_portC_in & ~m_ddrC) | (m_portC_out & m_ddrC);
129	138	}
130	139
131		static WRITE8_HANDLER( mcu_portC_w )
	140	WRITE8_MEMBER(maxaflex_state::mcu_portC_w)
132	141	{
133		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
134	142	/* uses a 7447A, which is equivalent to an LS47/48 */
135	143	static const UINT8 ls48_map[16] =
136	144	{ 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7c,0x07,0x7f,0x67,0x58,0x4c,0x62,0x69,0x78,0x00 };
137	145
138		state->m_portC_out = data & 0x0f;
	146	m_portC_out = data & 0x0f;
139	147
140	148	/* displays */
141		switch( state->m_portB_out & 0x3 )
	149	switch( m_portB_out & 0x3 )
142	150	{
143		case 0x0: output_set_digit_value(0, ls48_map[state->m_portC_out]); break;
144		case 0x1: output_set_digit_value(1, ls48_map[state->m_portC_out]); break;
145		case 0x2: output_set_digit_value(2, ls48_map[state->m_portC_out]); break;
	151	case 0x0: output_set_digit_value(0, ls48_map[m_portC_out]); break;
	152	case 0x1: output_set_digit_value(1, ls48_map[m_portC_out]); break;
	153	case 0x2: output_set_digit_value(2, ls48_map[m_portC_out]); break;
146	154	case 0x3: break;
147	155	}
148	156	}
149	157
150		static READ8_HANDLER( mcu_ddr_r )
	158	READ8_MEMBER(maxaflex_state::mcu_ddr_r)
151	159	{
152	160	return 0xff;
153	161	}
154	162
155		static WRITE8_HANDLER( mcu_portA_ddr_w )
	163	WRITE8_MEMBER(maxaflex_state::mcu_portA_ddr_w)
156	164	{
157		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
158		state->m_ddrA = data;
	165	m_ddrA = data;
159	166	}
160	167
161		static WRITE8_HANDLER( mcu_portB_ddr_w )
	168	WRITE8_MEMBER(maxaflex_state::mcu_portB_ddr_w)
162	169	{
163		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
164		state->m_ddrB = data;
	170	m_ddrB = data;
165	171	}
166	172
167		static WRITE8_HANDLER( mcu_portC_ddr_w )
	173	WRITE8_MEMBER(maxaflex_state::mcu_portC_ddr_w)
168	174	{
169		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
170		state->m_ddrC = data;
	175	m_ddrC = data;
171	176	}
172	177
173	178	static TIMER_DEVICE_CALLBACK( mcu_timer_proc )
r14845	r14846
184	189	}
185	190
186	191	/* Timer Data Reg */
187		static READ8_HANDLER( mcu_tdr_r )
	192	READ8_MEMBER(maxaflex_state::mcu_tdr_r)
188	193	{
189		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
190		return state->m_tdr;
	194	return m_tdr;
191	195	}
192	196
193		static WRITE8_HANDLER( mcu_tdr_w )
	197	WRITE8_MEMBER(maxaflex_state::mcu_tdr_w)
194	198	{
195		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
196		state->m_tdr = data;
	199	m_tdr = data;
197	200	}
198	201
199	202	/* Timer control reg */
200		static READ8_HANDLER( mcu_tcr_r )
	203	READ8_MEMBER(maxaflex_state::mcu_tcr_r)
201	204	{
202		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
203		return state->m_tcr & ~0x08;
	205	return m_tcr & ~0x08;
204	206	}
205	207
206		static WRITE8_HANDLER( mcu_tcr_w )
	208	WRITE8_MEMBER(maxaflex_state::mcu_tcr_w)
207	209	{
208		maxaflex_state *state = space->machine().driver_data<maxaflex_state>();
209		state->m_tcr = data;
210		if ( (state->m_tcr & 0x40) == 0 )
	210	m_tcr = data;
	211	if ( (m_tcr & 0x40) == 0 )
211	212	{
212	213	int divider;
213	214	attotime period;
214	215
215		if ( !(state->m_tcr & 0x20) )
	216	if ( !(m_tcr & 0x20) )
216	217	{
217	218	/* internal clock / 4*/
218	219	divider = 4;
r14845	r14846
223	224	divider = 1;
224	225	}
225	226
226		if ( state->m_tcr & 0x07 )
	227	if ( m_tcr & 0x07 )
227	228	{
228	229	/* use prescaler */
229		divider = divider * (1 << (state->m_tcr & 0x7));
	230	divider = divider * (1 << (m_tcr & 0x7));
230	231	}
231	232
232	233	period = attotime::from_hz(3579545) * divider;
233		state->m_mcu_timer->adjust(period, 0, period);
	234	m_mcu_timer->adjust(period, 0, period);
234	235	}
235	236	}
236	237
r14845	r14846
282	283
283	284	static ADDRESS_MAP_START( mcu_mem, AS_PROGRAM, 8, maxaflex_state )
284	285	ADDRESS_MAP_GLOBAL_MASK(0x7ff)
285		AM_RANGE(0x0000, 0x0000) AM_READ_LEGACY(mcu_portA_r ) AM_WRITE_LEGACY(mcu_portA_w )
286		AM_RANGE(0x0001, 0x0001) AM_READ_LEGACY(mcu_portB_r ) AM_WRITE_LEGACY(mcu_portB_w )
287		AM_RANGE(0x0002, 0x0002) AM_READ_LEGACY(mcu_portC_r ) AM_WRITE_LEGACY(mcu_portC_w )
288		AM_RANGE(0x0004, 0x0004) AM_READ_LEGACY(mcu_ddr_r ) AM_WRITE_LEGACY(mcu_portA_ddr_w )
289		AM_RANGE(0x0005, 0x0005) AM_READ_LEGACY(mcu_ddr_r ) AM_WRITE_LEGACY(mcu_portB_ddr_w )
290		AM_RANGE(0x0006, 0x0006) AM_READ_LEGACY(mcu_ddr_r ) AM_WRITE_LEGACY(mcu_portC_ddr_w )
291		AM_RANGE(0x0008, 0x0008) AM_READ_LEGACY(mcu_tdr_r ) AM_WRITE_LEGACY(mcu_tdr_w )
292		AM_RANGE(0x0009, 0x0009) AM_READ_LEGACY(mcu_tcr_r ) AM_WRITE_LEGACY(mcu_tcr_w )
	286	AM_RANGE(0x0000, 0x0000) AM_READ(mcu_portA_r ) AM_WRITE(mcu_portA_w )
	287	AM_RANGE(0x0001, 0x0001) AM_READ(mcu_portB_r ) AM_WRITE(mcu_portB_w )
	288	AM_RANGE(0x0002, 0x0002) AM_READ(mcu_portC_r ) AM_WRITE(mcu_portC_w )
	289	AM_RANGE(0x0004, 0x0004) AM_READ(mcu_ddr_r ) AM_WRITE(mcu_portA_ddr_w )
	290	AM_RANGE(0x0005, 0x0005) AM_READ(mcu_ddr_r ) AM_WRITE(mcu_portB_ddr_w )
	291	AM_RANGE(0x0006, 0x0006) AM_READ(mcu_ddr_r ) AM_WRITE(mcu_portC_ddr_w )
	292	AM_RANGE(0x0008, 0x0008) AM_READ(mcu_tdr_r ) AM_WRITE(mcu_tdr_w )
	293	AM_RANGE(0x0009, 0x0009) AM_READ(mcu_tcr_r ) AM_WRITE(mcu_tcr_w )
293	294	AM_RANGE(0x0010, 0x007f) AM_RAM
294	295	AM_RANGE(0x0080, 0x07ff) AM_ROM
295	296	ADDRESS_MAP_END

src/mame/drivers/atvtrack.c

r14845	r14846
72	72	atvtrack_state(const machine_config &mconfig, device_type type, const char *tag)
73	73	: driver_device(mconfig, type, tag) { }
74	74
	75	DECLARE_READ64_MEMBER(area1_r);
	76	DECLARE_WRITE64_MEMBER(area1_w);
	77	DECLARE_READ64_MEMBER(area2_r);
	78	DECLARE_WRITE64_MEMBER(area2_w);
	79	DECLARE_READ64_MEMBER(area3_r);
	80	DECLARE_WRITE64_MEMBER(area3_w);
	81	DECLARE_READ64_MEMBER(area4_r);
	82	DECLARE_WRITE64_MEMBER(area4_w);
	83	DECLARE_READ64_MEMBER(ioport_r);
	84	DECLARE_WRITE64_MEMBER(ioport_w);
75	85	};
76	86
77	87	static void logbinary(UINT32 data,int high=31,int low=0)
r14845	r14846
104	114	return 0;
105	115	}
106	116
107		static READ64_HANDLER( area1_r )
	117	READ64_MEMBER(atvtrack_state::area1_r)
108	118	{
109	119	UINT32 addr;
110	120
r14845	r14846
117	127	return -1;
118	128	}
119	129
120		static WRITE64_HANDLER( area1_w )
	130	WRITE64_MEMBER(atvtrack_state::area1_w)
121	131	{
122	132	UINT32 addr, dat; //, old;
123	133
r14845	r14846
127	137	area1_data[addr] = dat;
128	138	if (addr == (0x00020000-0x00020000)/4) {
129	139	if (data & 4) {
130		device_execute_interface *exec = dynamic_cast<device_execute_interface *>(space->machine().device("subcpu"));
	140	device_execute_interface *exec = dynamic_cast<device_execute_interface *>(machine().device("subcpu"));
131	141	exec->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
132	142	}
133	143	}
r14845	r14846
136	146	logerror("\n");
137	147	}
138	148
139		static READ64_HANDLER( area2_r )
	149	READ64_MEMBER(atvtrack_state::area2_r)
140	150	{
141	151	UINT32 addr, dat;
142	152	int c;
r14845	r14846
159	169	return 0;
160	170	}
161	171
162		static WRITE64_HANDLER( area2_w )
	172	WRITE64_MEMBER(atvtrack_state::area2_w)
163	173	{
164	174	//  UINT32 addr, dat;
165	175
r14845	r14846
171	181	//      ;
172	182	}
173	183
174		static READ64_HANDLER( area3_r )
	184	READ64_MEMBER(atvtrack_state::area3_r)
175	185	{
176	186	//  UINT32 addr, dat;
177	187
r14845	r14846
184	194	return 0;
185	195	}
186	196
187		static WRITE64_HANDLER( area3_w )
	197	WRITE64_MEMBER(atvtrack_state::area3_w)
188	198	{
189	199	UINT32 addr; //, dat;
190	200	int c;
r14845	r14846
217	227	;
218	228	}
219	229
220		static READ64_HANDLER( area4_r )
	230	READ64_MEMBER(atvtrack_state::area4_r)
221	231	{
222	232	//  UINT32 addr, dat;
223	233
r14845	r14846
230	240	return 0;
231	241	}
232	242
233		static WRITE64_HANDLER( area4_w )
	243	WRITE64_MEMBER(atvtrack_state::area4_w)
234	244	{
235	245	UINT32 addr; //, dat;
236	246	int c;
r14845	r14846
253	263	;
254	264	}
255	265
256		static READ64_HANDLER( ioport_r )
	266	READ64_MEMBER(atvtrack_state::ioport_r)
257	267	{
258	268	if (offset == SH4_IOPORT_16/8) {
259	269	// much simplified way
260		if (strcmp(space->device().tag(), ":maincpu") == 0)
	270	if (strcmp(space.device().tag(), ":maincpu") == 0)
261	271	#ifndef SPECIALMODE
262	272	return -1; // normal
263	273	#else
r14845	r14846
269	279	return 0;
270	280	}
271	281
272		static WRITE64_HANDLER( ioport_w )
	282	WRITE64_MEMBER(atvtrack_state::ioport_w)
273	283	{
274	284	#ifdef SPECIALMODE
275	285	UINT64 d;
r14845	r14846
293	303	else
294	304	d=0x11223344;
295	305	if (cnt == 0)
296		sh4_dma_data(space->cpu,&dm);
	306	sh4_dma_data(cpu,&dm);
297	307	else
298		sh4_dma_data(space->cpu,&dm);
	308	sh4_dma_data(cpu,&dm);
299	309	cnt++;
300	310	}
301	311	#endif
r14845	r14846
343	353
344	354	static ADDRESS_MAP_START( atvtrack_main_map, AS_PROGRAM, 64, atvtrack_state )
345	355	AM_RANGE(0x00000000, 0x000003ff) AM_RAM AM_SHARE("sharedmem")
346		AM_RANGE(0x00020000, 0x00020007) AM_READWRITE_LEGACY(area1_r, area1_w)
347		AM_RANGE(0x14000000, 0x14000007) AM_READWRITE_LEGACY(area2_r, area2_w) // data
348		AM_RANGE(0x14100000, 0x14100007) AM_READWRITE_LEGACY(area3_r, area3_w) // command
349		AM_RANGE(0x14200000, 0x14200007) AM_READWRITE_LEGACY(area4_r, area4_w) // address
	356	AM_RANGE(0x00020000, 0x00020007) AM_READWRITE(area1_r, area1_w)
	357	AM_RANGE(0x14000000, 0x14000007) AM_READWRITE(area2_r, area2_w) // data
	358	AM_RANGE(0x14100000, 0x14100007) AM_READWRITE(area3_r, area3_w) // command
	359	AM_RANGE(0x14200000, 0x14200007) AM_READWRITE(area4_r, area4_w) // address
350	360	AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM
351	361	ADDRESS_MAP_END
352	362
353	363	static ADDRESS_MAP_START( atvtrack_main_port, AS_IO, 64, atvtrack_state )
354		AM_RANGE(0x00, 0x1f) AM_READWRITE_LEGACY(ioport_r, ioport_w)
	364	AM_RANGE(0x00, 0x1f) AM_READWRITE(ioport_r, ioport_w)
355	365	ADDRESS_MAP_END
356	366
357	367	static ADDRESS_MAP_START( atvtrack_sub_map, AS_PROGRAM, 64, atvtrack_state )
r14845	r14846
360	370	ADDRESS_MAP_END
361	371
362	372	static ADDRESS_MAP_START( atvtrack_sub_port, AS_IO, 64, atvtrack_state )
363		/*AM_RANGE(0x00, 0x1f) AM_READWRITE_LEGACY(ioport_r, ioport_w) */
	373	/*AM_RANGE(0x00, 0x1f) AM_READWRITE(ioport_r, ioport_w) */
364	374	ADDRESS_MAP_END
365	375
366	376

src/mame/drivers/cybertnk.c

r14845	r14846
183	183	int m_test_y;
184	184	int m_start_offs;
185	185	int m_color_pen;
	186	DECLARE_WRITE16_MEMBER(tx_vram_w);
	187	DECLARE_READ16_MEMBER(io_r);
	188	DECLARE_WRITE16_MEMBER(io_w);
	189	DECLARE_READ8_MEMBER(soundport_r);
186	190	};
187	191
188	192
189		#define LOG_UNKNOWN_WRITE logerror("unknown io write CPU '%s':%08x  0x%08x 0x%04x & 0x%04x\n", space->device().tag(), cpu_get_pc(&space->device()), offset*2, data, mem_mask);
	193	#define LOG_UNKNOWN_WRITE logerror("unknown io write CPU '%s':%08x  0x%08x 0x%04x & 0x%04x\n", space.device().tag(), cpu_get_pc(&space.device()), offset*2, data, mem_mask);
190	194
191	195	static TILE_GET_INFO( get_tx_tile_info )
192	196	{
r14845	r14846
510	514	static SCREEN_UPDATE_IND16( cybertnk_right ) { return update_screen(screen, bitmap, cliprect, -256); }
511	515
512	516
513		static WRITE16_HANDLER( tx_vram_w )
	517	WRITE16_MEMBER(cybertnk_state::tx_vram_w)
514	518	{
515		cybertnk_state *state = space->machine().driver_data<cybertnk_state>();
516		COMBINE_DATA(&state->m_tx_vram[offset]);
517		state->m_tx_tilemap->mark_tile_dirty(offset);
	519	COMBINE_DATA(&m_tx_vram[offset]);
	520	m_tx_tilemap->mark_tile_dirty(offset);
518	521	}
519	522
520		static READ16_HANDLER( io_r )
	523	READ16_MEMBER(cybertnk_state::io_r)
521	524	{
522		cybertnk_state *state = space->machine().driver_data<cybertnk_state>();
523	525	switch( offset )
524	526	{
525	527	case 2/2:
526		return input_port_read(space->machine(), "DSW1");
	528	return input_port_read(machine(), "DSW1");
527	529
528	530	// 0x00110007 is controller device select
529	531	// 0x001100D5 is controller data
530	532	// 0x00110004 low is controller data ready
531	533	case 4/2:
532		switch( (state->m_io_ram[6/2]) & 0xff )
	534	switch( (m_io_ram[6/2]) & 0xff )
533	535	{
534	536	case 0:
535		state->m_io_ram[0xd4/2] = input_port_read(space->machine(), "TRAVERSE");
	537	m_io_ram[0xd4/2] = input_port_read(machine(), "TRAVERSE");
536	538	break;
537	539
538	540	case 0x20:
539		state->m_io_ram[0xd4/2] = input_port_read(space->machine(), "ELEVATE");
	541	m_io_ram[0xd4/2] = input_port_read(machine(), "ELEVATE");
540	542	break;
541	543
542	544	case 0x40:
543		state->m_io_ram[0xd4/2] = input_port_read(space->machine(), "ACCEL");
	545	m_io_ram[0xd4/2] = input_port_read(machine(), "ACCEL");
544	546	break;
545	547
546	548	case 0x42:
r14845	r14846
548	550	// controller return value is stored in $42(a6)
549	551	// but I don't see it referenced again.
550	552	//popmessage("unknown controller device 0x42");
551		state->m_io_ram[0xd4/2] = 0;
	553	m_io_ram[0xd4/2] = 0;
552	554	break;
553	555
554	556	case 0x60:
555		state->m_io_ram[0xd4/2] = input_port_read(space->machine(), "HANDLE");
	557	m_io_ram[0xd4/2] = input_port_read(machine(), "HANDLE");
556	558	break;
557	559
558	560	//default:
r14845	r14846
561	563	return 0;
562	564
563	565	case 6/2:
564		return input_port_read(space->machine(), "IN0"); // high half
	566	return input_port_read(machine(), "IN0"); // high half
565	567
566	568	case 8/2:
567		return input_port_read(space->machine(), "IN0"); // low half
	569	return input_port_read(machine(), "IN0"); // low half
568	570
569	571	case 0xa/2:
570		return input_port_read(space->machine(), "DSW2");
	572	return input_port_read(machine(), "DSW2");
571	573
572	574	case 0xd4/2:
573		return state->m_io_ram[offset]; // controller data
	575	return m_io_ram[offset]; // controller data
574	576
575	577	default:
576	578	{
577	579	//popmessage("unknown io read 0x%08x", offset);
578		return state->m_io_ram[offset];
	580	return m_io_ram[offset];
579	581	}
580	582	}
581	583	}
582	584
583		static WRITE16_HANDLER( io_w )
	585	WRITE16_MEMBER(cybertnk_state::io_w)
584	586	{
585		cybertnk_state *state = space->machine().driver_data<cybertnk_state>();
586		COMBINE_DATA(&state->m_io_ram[offset]);
	587	COMBINE_DATA(&m_io_ram[offset]);
587	588
588	589	switch( offset )
589	590	{
590	591	case 0/2:
591	592	// sound data
592	593	if (ACCESSING_BITS_0_7)
593		cputag_set_input_line(space->machine(), "audiocpu", 0, HOLD_LINE);
	594	cputag_set_input_line(machine(), "audiocpu", 0, HOLD_LINE);
594	595	else
595	596	LOG_UNKNOWN_WRITE
596	597	break;
r14845	r14846
644	645	case 0x80/2:
645	646	case 0x82/2:
646	647	case 0x84/2:
647		popmessage("%02x %02x %02x %02x %02x %02x %02x",state->m_io_ram[0x40/2],state->m_io_ram[0x42/2],state->m_io_ram[0x44/2],state->m_io_ram[0x46/2],state->m_io_ram[0x48/2],state->m_io_ram[0x4a/2],state->m_io_ram[0x4c/2]);
	648	popmessage("%02x %02x %02x %02x %02x %02x %02x",m_io_ram[0x40/2],m_io_ram[0x42/2],m_io_ram[0x44/2],m_io_ram[0x46/2],m_io_ram[0x48/2],m_io_ram[0x4a/2],m_io_ram[0x4c/2]);
648	649	break;
649	650
650	651	default:
r14845	r14846
653	654	}
654	655	}
655	656
656		static READ8_HANDLER( soundport_r )
	657	READ8_MEMBER(cybertnk_state::soundport_r)
657	658	{
658		cybertnk_state *state = space->machine().driver_data<cybertnk_state>();
659		return state->m_io_ram[0] & 0xff;
	659	return m_io_ram[0] & 0xff;
660	660	}
661	661
662	662	static ADDRESS_MAP_START( master_mem, AS_PROGRAM, 16, cybertnk_state )
663	663	AM_RANGE(0x000000, 0x03ffff) AM_ROM
664	664	AM_RANGE(0x080000, 0x087fff) AM_RAM /*Work RAM*/
665	665	AM_RANGE(0x0a0000, 0x0a0fff) AM_RAM AM_BASE(m_spr_ram) // non-tile based sprite ram
666		AM_RANGE(0x0c0000, 0x0c1fff) AM_RAM_WRITE_LEGACY(tx_vram_w) AM_BASE(m_tx_vram)
	666	AM_RANGE(0x0c0000, 0x0c1fff) AM_RAM_WRITE(tx_vram_w) AM_BASE(m_tx_vram)
667	667	AM_RANGE(0x0c4000, 0x0c5fff) AM_RAM AM_BASE(m_bg_vram)
668	668	AM_RANGE(0x0c8000, 0x0c9fff) AM_RAM AM_BASE(m_fg_vram)
669	669	AM_RANGE(0x0e0000, 0x0e0fff) AM_RAM AM_SHARE("sharedram")
670	670	AM_RANGE(0x100000, 0x107fff) AM_RAM_WRITE_LEGACY(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)
671		AM_RANGE(0x110000, 0x1101ff) AM_READWRITE_LEGACY(io_r,io_w) AM_BASE(m_io_ram)
	671	AM_RANGE(0x110000, 0x1101ff) AM_READWRITE(io_r,io_w) AM_BASE(m_io_ram)
672	672	ADDRESS_MAP_END
673	673
674	674	static ADDRESS_MAP_START( slave_mem, AS_PROGRAM, 16, cybertnk_state )
r14845	r14846
682	682	static ADDRESS_MAP_START( sound_mem, AS_PROGRAM, 8, cybertnk_state )
683	683	AM_RANGE(0x0000, 0x7fff ) AM_ROM
684	684	AM_RANGE(0x8000, 0x9fff ) AM_RAM
685		AM_RANGE(0xa001, 0xa001 ) AM_READ_LEGACY(soundport_r)
	685	AM_RANGE(0xa001, 0xa001 ) AM_READ(soundport_r)
686	686	AM_RANGE(0xa005, 0xa006 ) AM_NOP
687	687	AM_RANGE(0xa000, 0xa001 ) AM_DEVREADWRITE_LEGACY("ym1", y8950_r, y8950_w)
688	688	AM_RANGE(0xc000, 0xc001 ) AM_DEVREADWRITE_LEGACY("ym2", y8950_r, y8950_w)

src/mame/drivers/big10.c

r14845	r14846
72	72
73	73	required_device<v9938_device> m_v9938;
74	74	UINT8 m_mux_data;
	75	DECLARE_READ8_MEMBER(mux_r);
75	76	};
76	77
77	78
r14845	r14846
114	115	state->m_mux_data = ~data;
115	116	}
116	117
117		static READ8_HANDLER( mux_r )
	118	READ8_MEMBER(big10_state::mux_r)
118	119	{
119		big10_state *state = space->machine().driver_data<big10_state>();
120		switch(state->m_mux_data)
	120	switch(m_mux_data)
121	121	{
122		case 1: return input_port_read(space->machine(), "IN1");
123		case 2: return input_port_read(space->machine(), "IN2");
124		case 4: return input_port_read(space->machine(), "IN3");
	122	case 1: return input_port_read(machine(), "IN1");
	123	case 2: return input_port_read(machine(), "IN2");
	124	case 4: return input_port_read(machine(), "IN3");
125	125	}
126	126
127		return state->m_mux_data;
	127	return m_mux_data;
128	128	}
129	129
130	130
r14845	r14846
140	140
141	141	static ADDRESS_MAP_START( main_io, AS_IO, 8, big10_state )
142	142	ADDRESS_MAP_GLOBAL_MASK(0xff)
143		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(mux_r)         /* present in test mode */
	143	AM_RANGE(0x00, 0x00) AM_READ(mux_r)         /* present in test mode */
144	144	AM_RANGE(0x02, 0x02) AM_READ_PORT("SYSTEM")   /* coins and service */
145	145	AM_RANGE(0x98, 0x9b) AM_DEVREADWRITE("v9938", v9938_device, read, write)
146	146	AM_RANGE(0xa0, 0xa1) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)

src/mame/drivers/pipeline.c

r14845	r14846
87	87	UINT8 m_toMCU;
88	88	UINT8 m_fromMCU;
89	89	UINT8 m_ddrA;
	90	DECLARE_WRITE8_MEMBER(vram2_w);
	91	DECLARE_WRITE8_MEMBER(vram1_w);
	92	DECLARE_WRITE8_MEMBER(mcu_portA_w);
	93	DECLARE_READ8_MEMBER(mcu_portA_r);
	94	DECLARE_WRITE8_MEMBER(mcu_ddrA_w);
90	95	};
91	96
92	97
r14845	r14846
139	144	state->m_vidctrl=data;
140	145	}
141	146
142		static WRITE8_HANDLER(vram2_w)
	147	WRITE8_MEMBER(pipeline_state::vram2_w)
143	148	{
144		pipeline_state *state = space->machine().driver_data<pipeline_state>();
145		if(!(state->m_vidctrl&1))
	149	if(!(m_vidctrl&1))
146	150	{
147		state->m_tilemap1->mark_tile_dirty(offset&0x7ff);
148		state->m_vram2[offset]=data;
	151	m_tilemap1->mark_tile_dirty(offset&0x7ff);
	152	m_vram2[offset]=data;
149	153	}
150	154	else
151	155	{
152		state->m_palram[offset]=data;
	156	m_palram[offset]=data;
153	157	if(offset<0x300)
154	158	{
155	159	offset&=0xff;
156		palette_set_color_rgb(space->machine(), offset, pal6bit(state->m_palram[offset]), pal6bit(state->m_palram[offset+0x100]), pal6bit(state->m_palram[offset+0x200]));
	160	palette_set_color_rgb(machine(), offset, pal6bit(m_palram[offset]), pal6bit(m_palram[offset+0x100]), pal6bit(m_palram[offset+0x200]));
157	161	}
158	162	}
159	163	}
160	164
161		static WRITE8_HANDLER(vram1_w)
	165	WRITE8_MEMBER(pipeline_state::vram1_w)
162	166	{
163		pipeline_state *state = space->machine().driver_data<pipeline_state>();
164		state->m_tilemap2->mark_tile_dirty(offset&0x7ff);
165		state->m_vram1[offset]=data;
	167	m_tilemap2->mark_tile_dirty(offset&0x7ff);
	168	m_vram1[offset]=data;
166	169	}
167	170
168	171	static READ8_DEVICE_HANDLER(protection_r)
r14845	r14846
186	189	static ADDRESS_MAP_START( cpu0_mem, AS_PROGRAM, 8, pipeline_state )
187	190	AM_RANGE(0x0000, 0x7fff) AM_ROM
188	191	AM_RANGE(0x8000, 0x87ff) AM_RAM
189		AM_RANGE(0x8800, 0x97ff) AM_RAM_WRITE_LEGACY(vram1_w) AM_BASE(m_vram1)
190		AM_RANGE(0x9800, 0xa7ff) AM_RAM_WRITE_LEGACY(vram2_w) AM_BASE(m_vram2)
	192	AM_RANGE(0x8800, 0x97ff) AM_RAM_WRITE(vram1_w) AM_BASE(m_vram1)
	193	AM_RANGE(0x9800, 0xa7ff) AM_RAM_WRITE(vram2_w) AM_BASE(m_vram2)
191	194	AM_RANGE(0xb800, 0xb803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
192	195	AM_RANGE(0xb810, 0xb813) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
193	196	AM_RANGE(0xb830, 0xb830) AM_NOP
r14845	r14846
206	209	AM_RANGE(0x06, 0x07) AM_NOP
207	210	ADDRESS_MAP_END
208	211
209		static WRITE8_HANDLER(mcu_portA_w)
	212	WRITE8_MEMBER(pipeline_state::mcu_portA_w)
210	213	{
211		pipeline_state *state = space->machine().driver_data<pipeline_state>();
212		state->m_fromMCU=data;
	214	m_fromMCU=data;
213	215	}
214	216
215		static READ8_HANDLER(mcu_portA_r)
	217	READ8_MEMBER(pipeline_state::mcu_portA_r)
216	218	{
217		pipeline_state *state = space->machine().driver_data<pipeline_state>();
218		return (state->m_fromMCU&state->m_ddrA)|(state->m_toMCU& ~state->m_ddrA);
	219	return (m_fromMCU&m_ddrA)|(m_toMCU& ~m_ddrA);
219	220	}
220	221
221		static WRITE8_HANDLER(mcu_ddrA_w)
	222	WRITE8_MEMBER(pipeline_state::mcu_ddrA_w)
222	223	{
223		pipeline_state *state = space->machine().driver_data<pipeline_state>();
224		state->m_ddrA=data;
	224	m_ddrA=data;
225	225	}
226	226
227	227	static ADDRESS_MAP_START( mcu_mem, AS_PROGRAM, 8, pipeline_state )
228		AM_RANGE(0x0000, 0x0000) AM_READ_LEGACY(mcu_portA_r) AM_WRITE_LEGACY(mcu_portA_w)
229		AM_RANGE(0x0004, 0x0004) AM_WRITE_LEGACY(mcu_ddrA_w)
	228	AM_RANGE(0x0000, 0x0000) AM_READ(mcu_portA_r) AM_WRITE(mcu_portA_w)
	229	AM_RANGE(0x0004, 0x0004) AM_WRITE(mcu_ddrA_w)
230	230	AM_RANGE(0x0010, 0x007f) AM_RAM
231	231	AM_RANGE(0x0080, 0x0fff) AM_ROM
232	232	ADDRESS_MAP_END

src/mame/drivers/pinkiri8.c

r14845	r14846
54	54	UINT8 m_prot_read_index;
55	55	UINT8 m_prot_char[6];
56	56	UINT8 m_prot_index;
	57	DECLARE_WRITE8_MEMBER(output_regs_w);
	58	DECLARE_WRITE8_MEMBER(pinkiri8_vram_w);
	59	DECLARE_WRITE8_MEMBER(mux_w);
	60	DECLARE_READ8_MEMBER(mux_p2_r);
	61	DECLARE_READ8_MEMBER(mux_p1_r);
	62	DECLARE_READ8_MEMBER(ronjan_prot_r);
	63	DECLARE_WRITE8_MEMBER(ronjan_prot_w);
	64	DECLARE_READ8_MEMBER(ronjan_prot_status_r);
	65	DECLARE_READ8_MEMBER(ronjan_patched_prot_r);
57	66	};
58	67
59	68
r14845	r14846
381	390	AM_RANGE(0x10000, 0x1ffff) AM_ROM
382	391	ADDRESS_MAP_END
383	392
384		static WRITE8_HANDLER( output_regs_w )
	393	WRITE8_MEMBER(pinkiri8_state::output_regs_w)
385	394	{
386	395	if(data & 0x40)
387		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
	396	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
388	397	//data & 0x80 is probably NMI mask
389	398	}
390	399
391	400
392	401	#define LOG_VRAM 0
393	402
394		static WRITE8_HANDLER( pinkiri8_vram_w )
	403	WRITE8_MEMBER(pinkiri8_state::pinkiri8_vram_w)
395	404	{
396		pinkiri8_state *state = space->machine().driver_data<pinkiri8_state>();
397	405	switch(offset)
398	406	{
399	407	case 0:
400		state->m_vram_addr = (data << 0)  | (state->m_vram_addr&0xffff00);
401		if (LOG_VRAM) printf("\n prev writes was %04x\n\naddress set to %04x -\n", state->m_prev_writes, state->m_vram_addr );
402		state->m_prev_writes = 0;
	408	m_vram_addr = (data << 0)  | (m_vram_addr&0xffff00);
	409	if (LOG_VRAM) printf("\n prev writes was %04x\n\naddress set to %04x -\n", m_prev_writes, m_vram_addr );
	410	m_prev_writes = 0;
403	411	break;
404	412
405	413	case 1:
406		state->m_vram_addr = (data << 8)  | (state->m_vram_addr & 0xff00ff);
407		if (LOG_VRAM)printf("\naddress set to %04x\n", state->m_vram_addr);
	414	m_vram_addr = (data << 8)  | (m_vram_addr & 0xff00ff);
	415	if (LOG_VRAM)printf("\naddress set to %04x\n", m_vram_addr);
408	416	break;
409	417
410	418	case 2:
411		state->m_vram_addr = (data << 16) | (state->m_vram_addr & 0x00ffff);
412		if (LOG_VRAM)printf("\naddress set to %04x\n", state->m_vram_addr);
	419	m_vram_addr = (data << 16) | (m_vram_addr & 0x00ffff);
	420	if (LOG_VRAM)printf("\naddress set to %04x\n", m_vram_addr);
413	421	break;
414	422
415	423	case 3:
416	424
417		address_space *vdp_space = space->machine().device<janshi_vdp_device>("janshivdp")->space();
	425	address_space *vdp_space = machine().device<janshi_vdp_device>("janshivdp")->space();
418	426
419	427	if (LOG_VRAM) printf("%02x ", data);
420		state->m_prev_writes++;
421		state->m_vram_addr++;
	428	m_prev_writes++;
	429	m_vram_addr++;
422	430
423		vdp_space->write_byte(state->m_vram_addr, data);
	431	vdp_space->write_byte(m_vram_addr, data);
424	432	break;
425	433	}
426	434	}
427	435
428	436
429		static WRITE8_HANDLER( mux_w )
	437	WRITE8_MEMBER(pinkiri8_state::mux_w)
430	438	{
431		pinkiri8_state *state = space->machine().driver_data<pinkiri8_state>();
432		state->m_mux_data = data;
	439	m_mux_data = data;
433	440	}
434	441
435		static READ8_HANDLER( mux_p2_r )
	442	READ8_MEMBER(pinkiri8_state::mux_p2_r)
436	443	{
437		pinkiri8_state *state = space->machine().driver_data<pinkiri8_state>();
438		switch(state->m_mux_data)
	444	switch(m_mux_data)
439	445	{
440		case 0x01: return input_port_read(space->machine(), "PL2_01");
441		case 0x02: return input_port_read(space->machine(), "PL2_02");
442		case 0x04: return input_port_read(space->machine(), "PL2_03");
443		case 0x08: return input_port_read(space->machine(), "PL2_04");
444		case 0x10: return input_port_read(space->machine(), "PL2_05");
	446	case 0x01: return input_port_read(machine(), "PL2_01");
	447	case 0x02: return input_port_read(machine(), "PL2_02");
	448	case 0x04: return input_port_read(machine(), "PL2_03");
	449	case 0x08: return input_port_read(machine(), "PL2_04");
	450	case 0x10: return input_port_read(machine(), "PL2_05");
445	451	}
446	452
447	453	return 0xff;
448	454	}
449	455
450		static READ8_HANDLER( mux_p1_r )
	456	READ8_MEMBER(pinkiri8_state::mux_p1_r)
451	457	{
452		pinkiri8_state *state = space->machine().driver_data<pinkiri8_state>();
453		switch(state->m_mux_data)
	458	switch(m_mux_data)
454	459	{
455		case 0x01: return input_port_read(space->machine(), "PL1_01");
456		case 0x02: return input_port_read(space->machine(), "PL1_02");
457		case 0x04: return input_port_read(space->machine(), "PL1_03");
458		case 0x08: return input_port_read(space->machine(), "PL1_04");
459		case 0x10: return input_port_read(space->machine(), "PL1_05");
	460	case 0x01: return input_port_read(machine(), "PL1_01");
	461	case 0x02: return input_port_read(machine(), "PL1_02");
	462	case 0x04: return input_port_read(machine(), "PL1_03");
	463	case 0x08: return input_port_read(machine(), "PL1_04");
	464	case 0x10: return input_port_read(machine(), "PL1_05");
460	465	}
461	466
462	467	return 0xff;
r14845	r14846
465	470	static ADDRESS_MAP_START( pinkiri8_io, AS_IO, 8, pinkiri8_state )
466	471	ADDRESS_MAP_GLOBAL_MASK(0xff)
467	472	AM_RANGE(0x00, 0x3f) AM_RAM //Z180 internal I/O
468		AM_RANGE(0x60, 0x60) AM_WRITE_LEGACY(output_regs_w)
469		AM_RANGE(0x80, 0x83) AM_WRITE_LEGACY(pinkiri8_vram_w)
	473	AM_RANGE(0x60, 0x60) AM_WRITE(output_regs_w)
	474	AM_RANGE(0x80, 0x83) AM_WRITE(pinkiri8_vram_w)
470	475
471	476	AM_RANGE(0xa0, 0xa0) AM_DEVREADWRITE("oki", okim6295_device, read, write) //correct?
472		AM_RANGE(0xb0, 0xb0) AM_WRITE_LEGACY(mux_w) //mux
473		AM_RANGE(0xb0, 0xb0) AM_READ_LEGACY(mux_p2_r) // mux inputs
474		AM_RANGE(0xb1, 0xb1) AM_READ_LEGACY(mux_p1_r) // mux inputs
	477	AM_RANGE(0xb0, 0xb0) AM_WRITE(mux_w) //mux
	478	AM_RANGE(0xb0, 0xb0) AM_READ(mux_p2_r) // mux inputs
	479	AM_RANGE(0xb1, 0xb1) AM_READ(mux_p1_r) // mux inputs
475	480	AM_RANGE(0xb2, 0xb2) AM_READ_PORT("SYSTEM")
476	481	AM_RANGE(0xf8, 0xf8) AM_READ_PORT("DSW1")
477	482	AM_RANGE(0xf9, 0xf9) AM_READ_PORT("DSW2")
r14845	r14846
1173	1178	ROM_END
1174	1179
1175	1180
1176		static READ8_HANDLER( ronjan_prot_r )
	1181	READ8_MEMBER(pinkiri8_state::ronjan_prot_r)
1177	1182	{
1178		pinkiri8_state *state = space->machine().driver_data<pinkiri8_state>();
1179	1183	static const char wing_str[6] = { 'W', 'I', 'N', 'G', '8', '9' };
1180	1184
1181		state->m_prot_read_index++;
	1185	m_prot_read_index++;
1182	1186
1183		if(state->m_prot_read_index & 1)
	1187	if(m_prot_read_index & 1)
1184	1188	return 0xff; //value is discarded
1185	1189
1186		return wing_str[(state->m_prot_read_index >> 1)-1];
	1190	return wing_str[(m_prot_read_index >> 1)-1];
1187	1191	}
1188	1192
1189		static WRITE8_HANDLER( ronjan_prot_w )
	1193	WRITE8_MEMBER(pinkiri8_state::ronjan_prot_w)
1190	1194	{
1191		pinkiri8_state *state = space->machine().driver_data<pinkiri8_state>();
1192	1195
1193	1196	if(data == 0)
1194	1197	{
1195		state->m_prot_index = 0;
	1198	m_prot_index = 0;
1196	1199	}
1197	1200	else
1198	1201	{
1199		state->m_prot_char[state->m_prot_index] = data;
1200		state->m_prot_index++;
	1202	m_prot_char[m_prot_index] = data;
	1203	m_prot_index++;
1201	1204
1202		if(state->m_prot_char[0] == 'E' && state->m_prot_char[1] == 'R' && state->m_prot_char[2] == 'R' && state->m_prot_char[3] == 'O' && state->m_prot_char[4] == 'R')
1203		state->m_prot_read_index = 0;
	1205	if(m_prot_char[0] == 'E' && m_prot_char[1] == 'R' && m_prot_char[2] == 'R' && m_prot_char[3] == 'O' && m_prot_char[4] == 'R')
	1206	m_prot_read_index = 0;
1204	1207	}
1205	1208	}
1206	1209
1207		static READ8_HANDLER( ronjan_prot_status_r )
	1210	READ8_MEMBER(pinkiri8_state::ronjan_prot_status_r)
1208	1211	{
1209	1212	return 0; //bit 0 seems a protection status bit
1210	1213	}
1211	1214
1212		static READ8_HANDLER( ronjan_patched_prot_r )
	1215	READ8_MEMBER(pinkiri8_state::ronjan_patched_prot_r)
1213	1216	{
1214	1217	return 0; //value is read then discarded
1215	1218	}
1216	1219
1217	1220	static DRIVER_INIT( ronjan )
1218	1221	{
1219		machine.device("maincpu")->memory().space(AS_IO)->install_legacy_readwrite_handler(0x90, 0x90, FUNC(ronjan_prot_r), FUNC(ronjan_prot_w));
1220		machine.device("maincpu")->memory().space(AS_IO)->install_legacy_read_handler(0x66, 0x66, FUNC(ronjan_prot_status_r));
1221		machine.device("maincpu")->memory().space(AS_IO)->install_legacy_read_handler(0x9f, 0x9f, FUNC(ronjan_patched_prot_r));
	1222	pinkiri8_state *state = machine.driver_data<pinkiri8_state>();
	1223	machine.device("maincpu")->memory().space(AS_IO)->install_readwrite_handler(0x90, 0x90, read8_delegate(FUNC(pinkiri8_state::ronjan_prot_r), state), write8_delegate(FUNC(pinkiri8_state::ronjan_prot_w), state));
	1224	machine.device("maincpu")->memory().space(AS_IO)->install_read_handler(0x66, 0x66, read8_delegate(FUNC(pinkiri8_state::ronjan_prot_status_r), state));
	1225	machine.device("maincpu")->memory().space(AS_IO)->install_read_handler(0x9f, 0x9f, read8_delegate(FUNC(pinkiri8_state::ronjan_patched_prot_r), state));
1222	1226	}
1223	1227
1224	1228	GAME( 1992,  janshi,    0,   pinkiri8, janshi,    0,      ROT0, "Eagle",         "Janshi",          GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS | GAME_NOT_WORKING )

src/mame/drivers/chanbara.c

r14845	r14846
74	74
75	75	/* devices */
76	76	device_t *m_maincpu;
	77	DECLARE_WRITE8_MEMBER(chanbara_videoram_w);
	78	DECLARE_WRITE8_MEMBER(chanbara_colorram_w);
	79	DECLARE_WRITE8_MEMBER(chanbara_videoram2_w);
	80	DECLARE_WRITE8_MEMBER(chanbara_colorram2_w);
77	81	};
78	82
79	83
r14845	r14846
91	95	}
92	96	}
93	97
94		static WRITE8_HANDLER( chanbara_videoram_w )
	98	WRITE8_MEMBER(chanbara_state::chanbara_videoram_w)
95	99	{
96		chanbara_state *state = space->machine().driver_data<chanbara_state>();
97	100
98		state->m_videoram[offset] = data;
99		state->m_bg_tilemap->mark_tile_dirty(offset);
	101	m_videoram[offset] = data;
	102	m_bg_tilemap->mark_tile_dirty(offset);
100	103	}
101	104
102		static WRITE8_HANDLER( chanbara_colorram_w )
	105	WRITE8_MEMBER(chanbara_state::chanbara_colorram_w)
103	106	{
104		chanbara_state *state = space->machine().driver_data<chanbara_state>();
105	107
106		state->m_colorram[offset] = data;
107		state->m_bg_tilemap->mark_tile_dirty(offset);
	108	m_colorram[offset] = data;
	109	m_bg_tilemap->mark_tile_dirty(offset);
108	110	}
109	111
110		static WRITE8_HANDLER( chanbara_videoram2_w )
	112	WRITE8_MEMBER(chanbara_state::chanbara_videoram2_w)
111	113	{
112		chanbara_state *state = space->machine().driver_data<chanbara_state>();
113	114
114		state->m_videoram2[offset] = data;
115		state->m_bg2_tilemap->mark_tile_dirty(offset);
	115	m_videoram2[offset] = data;
	116	m_bg2_tilemap->mark_tile_dirty(offset);
116	117	}
117	118
118		static WRITE8_HANDLER( chanbara_colorram2_w )
	119	WRITE8_MEMBER(chanbara_state::chanbara_colorram2_w)
119	120	{
120		chanbara_state *state = space->machine().driver_data<chanbara_state>();
121	121
122		state->m_colorram2[offset] = data;
123		state->m_bg2_tilemap->mark_tile_dirty(offset);
	122	m_colorram2[offset] = data;
	123	m_bg2_tilemap->mark_tile_dirty(offset);
124	124	}
125	125
126	126
r14845	r14846
209	209
210	210	static ADDRESS_MAP_START( chanbara_map, AS_PROGRAM, 8, chanbara_state )
211	211	AM_RANGE(0x0000, 0x07ff) AM_RAM
212		AM_RANGE(0x0800, 0x0bff) AM_RAM_WRITE_LEGACY(chanbara_videoram_w) AM_BASE(m_videoram)
213		AM_RANGE(0x0c00, 0x0fff) AM_RAM_WRITE_LEGACY(chanbara_colorram_w) AM_BASE(m_colorram)
	212	AM_RANGE(0x0800, 0x0bff) AM_RAM_WRITE(chanbara_videoram_w) AM_BASE(m_videoram)
	213	AM_RANGE(0x0c00, 0x0fff) AM_RAM_WRITE(chanbara_colorram_w) AM_BASE(m_colorram)
214	214	AM_RANGE(0x1000, 0x10ff) AM_RAM AM_BASE(m_spriteram)
215		AM_RANGE(0x1800, 0x19ff) AM_RAM_WRITE_LEGACY(chanbara_videoram2_w) AM_BASE(m_videoram2)
216		AM_RANGE(0x1a00, 0x1bff) AM_RAM_WRITE_LEGACY(chanbara_colorram2_w) AM_BASE(m_colorram2)
	215	AM_RANGE(0x1800, 0x19ff) AM_RAM_WRITE(chanbara_videoram2_w) AM_BASE(m_videoram2)
	216	AM_RANGE(0x1a00, 0x1bff) AM_RAM_WRITE(chanbara_colorram2_w) AM_BASE(m_colorram2)
217	217	AM_RANGE(0x2000, 0x2000) AM_READ_PORT("DSW1")
218	218	AM_RANGE(0x2001, 0x2001) AM_READ_PORT("SYSTEM")
219	219	AM_RANGE(0x2002, 0x2002) AM_READ_PORT("P2")

src/mame/drivers/m14.c

r14845	r14846
70	70
71	71	/* devices */
72	72	device_t *m_maincpu;
	73	DECLARE_WRITE8_MEMBER(m14_vram_w);
	74	DECLARE_WRITE8_MEMBER(m14_cram_w);
	75	DECLARE_READ8_MEMBER(m14_rng_r);
	76	DECLARE_READ8_MEMBER(input_buttons_r);
	77	DECLARE_WRITE8_MEMBER(test_w);
	78	DECLARE_WRITE8_MEMBER(hopper_w);
73	79	};
74	80
75	81
r14845	r14846
129	135	}
130	136
131	137
132		static WRITE8_HANDLER( m14_vram_w )
	138	WRITE8_MEMBER(m14_state::m14_vram_w)
133	139	{
134		m14_state *state = space->machine().driver_data<m14_state>();
135	140
136		state->m_video_ram[offset] = data;
137		state->m_m14_tilemap->mark_tile_dirty(offset);
	141	m_video_ram[offset] = data;
	142	m_m14_tilemap->mark_tile_dirty(offset);
138	143	}
139	144
140		static WRITE8_HANDLER( m14_cram_w )
	145	WRITE8_MEMBER(m14_state::m14_cram_w)
141	146	{
142		m14_state *state = space->machine().driver_data<m14_state>();
143	147
144		state->m_color_ram[offset] = data;
145		state->m_m14_tilemap->mark_tile_dirty(offset);
	148	m_color_ram[offset] = data;
	149	m_m14_tilemap->mark_tile_dirty(offset);
146	150	}
147	151
148	152	/*************************************
r14845	r14846
151	155	*
152	156	*************************************/
153	157
154		static READ8_HANDLER( m14_rng_r )
	158	READ8_MEMBER(m14_state::m14_rng_r)
155	159	{
156	160	/* graphic artifacts happens if this doesn't return random values. */
157		return (space->machine().rand() & 0x0f) | 0xf0; /* | (input_port_read(space->machine(), "IN1") & 0x80)*/;
	161	return (machine().rand() & 0x0f) | 0xf0; /* | (input_port_read(machine(), "IN1") & 0x80)*/;
158	162	}
159	163
160	164	/* Here routes the hopper & the inputs */
161		static READ8_HANDLER( input_buttons_r )
	165	READ8_MEMBER(m14_state::input_buttons_r)
162	166	{
163		m14_state *state = space->machine().driver_data<m14_state>();
164	167
165		if (state->m_hop_mux)
	168	if (m_hop_mux)
166	169	{
167		state->m_hop_mux = 0;
	170	m_hop_mux = 0;
168	171	return 0; //0x43 status bits
169	172	}
170	173	else
171		return input_port_read(space->machine(), "IN0");
	174	return input_port_read(machine(), "IN0");
172	175	}
173	176
174	177	#if 0
175		static WRITE8_HANDLER( test_w )
	178	WRITE8_MEMBER(m14_state::test_w)
176	179	{
177	180	static UINT8 x[5];
178	181
r14845	r14846
182	185	}
183	186	#endif
184	187
185		static WRITE8_HANDLER( hopper_w )
	188	WRITE8_MEMBER(m14_state::hopper_w)
186	189	{
187		m14_state *state = space->machine().driver_data<m14_state>();
188	190
189	191	/* ---- x--- coin out */
190	192	/* ---- --x- hopper/input mux? */
191		state->m_hop_mux = data & 2;
	193	m_hop_mux = data & 2;
192	194	//popmessage("%02x",data);
193	195	}
194	196
r14845	r14846
201	203	static ADDRESS_MAP_START( m14_map, AS_PROGRAM, 8, m14_state )
202	204	AM_RANGE(0x0000, 0x1fff) AM_ROM
203	205	AM_RANGE(0x2000, 0x23ff) AM_RAM
204		AM_RANGE(0xe000, 0xe3ff) AM_RAM_WRITE_LEGACY(m14_vram_w) AM_BASE(m_video_ram)
205		AM_RANGE(0xe400, 0xe7ff) AM_RAM_WRITE_LEGACY(m14_cram_w) AM_BASE(m_color_ram)
	206	AM_RANGE(0xe000, 0xe3ff) AM_RAM_WRITE(m14_vram_w) AM_BASE(m_video_ram)
	207	AM_RANGE(0xe400, 0xe7ff) AM_RAM_WRITE(m14_cram_w) AM_BASE(m_color_ram)
206	208	ADDRESS_MAP_END
207	209
208	210	static ADDRESS_MAP_START( m14_io_map, AS_IO, 8, m14_state )
209	211	ADDRESS_MAP_GLOBAL_MASK(0xff)
210	212	AM_RANGE(0xf8, 0xf8) AM_READ_PORT("AN_PADDLE") AM_WRITENOP
211		AM_RANGE(0xf9, 0xf9) AM_READ_LEGACY(input_buttons_r) AM_WRITENOP
212		AM_RANGE(0xfa, 0xfa) AM_READ_LEGACY(m14_rng_r) AM_WRITENOP
213		AM_RANGE(0xfb, 0xfb) AM_READ_PORT("DSW") AM_WRITE_LEGACY(hopper_w)
	213	AM_RANGE(0xf9, 0xf9) AM_READ(input_buttons_r) AM_WRITENOP
	214	AM_RANGE(0xfa, 0xfa) AM_READ(m14_rng_r) AM_WRITENOP
	215	AM_RANGE(0xfb, 0xfb) AM_READ_PORT("DSW") AM_WRITE(hopper_w)
214	216	AM_RANGE(0xf8, 0xfc) AM_WRITENOP
215	217	ADDRESS_MAP_END
216	218

src/mame/drivers/jantotsu.c

r14845	r14846
119	119	UINT8    m_col_bank;
120	120	UINT8    m_display_on;
121	121	UINT8    m_bitmap[0x8000];
	122	DECLARE_READ8_MEMBER(jantotsu_bitmap_r);
	123	DECLARE_WRITE8_MEMBER(jantotsu_bitmap_w);
	124	DECLARE_WRITE8_MEMBER(bankaddr_w);
	125	DECLARE_READ8_MEMBER(jantotsu_mux_r);
	126	DECLARE_WRITE8_MEMBER(jantotsu_mux_w);
	127	DECLARE_READ8_MEMBER(jantotsu_dsw2_r);
122	128	};
123	129
124	130
r14845	r14846
170	176	}
171	177
172	178	/* banked vram */
173		static READ8_HANDLER( jantotsu_bitmap_r )
	179	READ8_MEMBER(jantotsu_state::jantotsu_bitmap_r)
174	180	{
175		jantotsu_state *state = space->machine().driver_data<jantotsu_state>();
176		return state->m_bitmap[offset + ((state->m_vram_bank & 3) * 0x2000)];
	181	return m_bitmap[offset + ((m_vram_bank & 3) * 0x2000)];
177	182	}
178	183
179		static WRITE8_HANDLER( jantotsu_bitmap_w )
	184	WRITE8_MEMBER(jantotsu_state::jantotsu_bitmap_w)
180	185	{
181		jantotsu_state *state = space->machine().driver_data<jantotsu_state>();
182		state->m_bitmap[offset + ((state->m_vram_bank & 3) * 0x2000)] = data;
	186	m_bitmap[offset + ((m_vram_bank & 3) * 0x2000)] = data;
183	187	}
184	188
185		static WRITE8_HANDLER( bankaddr_w )
	189	WRITE8_MEMBER(jantotsu_state::bankaddr_w)
186	190	{
187		jantotsu_state *state = space->machine().driver_data<jantotsu_state>();
188	191
189		state->m_vram_bank = ((data & 0xc0) >> 6);
	192	m_vram_bank = ((data & 0xc0) >> 6);
190	193
191		state->m_display_on = (data & 2);
	194	m_display_on = (data & 2);
192	195
193	196	/* bit 0 is unknown */
194	197	if(data & 0x3c)
r14845	r14846
227	230	*************************************/
228	231
229	232	/*Multiplexer is mapped as 6-bits reads,bits 6 & 7 are always connected to the coin mechs.*/
230		static READ8_HANDLER( jantotsu_mux_r )
	233	READ8_MEMBER(jantotsu_state::jantotsu_mux_r)
231	234	{
232		jantotsu_state *state = space->machine().driver_data<jantotsu_state>();
233	235	const char *const portnames[] = { "PL1_1", "PL1_2", "PL1_3", "PL1_4",
234	236	"PL2_1", "PL2_2", "PL2_3", "PL2_4" };
235	237	UINT8 i,res;
236	238
237		//  printf("%02x\n", state->m_mux_data);
238		res = input_port_read(space->machine(), "COINS");
	239	//  printf("%02x\n", m_mux_data);
	240	res = input_port_read(machine(), "COINS");
239	241
240	242	for(i=0;i<8;i++)
241	243	{
242		if((~state->m_mux_data) & (1 << i))
243		res |= input_port_read(space->machine(), portnames[i]);
	244	if((~m_mux_data) & (1 << i))
	245	res |= input_port_read(machine(), portnames[i]);
244	246	}
245	247
246	248	return res;
247	249	}
248	250
249		static WRITE8_HANDLER( jantotsu_mux_w )
	251	WRITE8_MEMBER(jantotsu_state::jantotsu_mux_w)
250	252	{
251		jantotsu_state *state = space->machine().driver_data<jantotsu_state>();
252		state->m_mux_data = data;
	253	m_mux_data = data;
253	254	}
254	255
255	256	/*If bits 6 & 7 doesn't return 0x80,the game hangs until this bit is set,
256	257	so I'm guessing that these bits can't be read by the z80 at all but directly
257	258	hard-wired to the video chip. However I need the schematics / pcb snaps and/or
258	259	a side-by-side test (to know if the background colors really works) to be sure. */
259		static READ8_HANDLER( jantotsu_dsw2_r )
	260	READ8_MEMBER(jantotsu_state::jantotsu_dsw2_r)
260	261	{
261		return (input_port_read(space->machine(), "DSW2") & 0x3f) | 0x80;
	262	return (input_port_read(machine(), "DSW2") & 0x3f) | 0x80;
262	263	}
263	264
264	265	static WRITE8_DEVICE_HANDLER( jan_adpcm_w )
r14845	r14846
322	323	static ADDRESS_MAP_START( jantotsu_map, AS_PROGRAM, 8, jantotsu_state )
323	324	AM_RANGE(0x0000, 0xbfff) AM_ROM
324	325	AM_RANGE(0xc000, 0xc7ff) AM_RAM
325		AM_RANGE(0xe000, 0xffff) AM_READWRITE_LEGACY(jantotsu_bitmap_r, jantotsu_bitmap_w)
	326	AM_RANGE(0xe000, 0xffff) AM_READWRITE(jantotsu_bitmap_r, jantotsu_bitmap_w)
326	327	ADDRESS_MAP_END
327	328
328	329	static ADDRESS_MAP_START( jantotsu_io, AS_IO, 8, jantotsu_state )
329	330	ADDRESS_MAP_GLOBAL_MASK(0xff)
330	331	AM_RANGE(0x00, 0x00) AM_READ_PORT("DSW1") AM_DEVWRITE_LEGACY("sn1", sn76496_w)
331		AM_RANGE(0x01, 0x01) AM_READ_LEGACY(jantotsu_dsw2_r) AM_DEVWRITE_LEGACY("sn2", sn76496_w)
	332	AM_RANGE(0x01, 0x01) AM_READ(jantotsu_dsw2_r) AM_DEVWRITE_LEGACY("sn2", sn76496_w)
332	333	AM_RANGE(0x02, 0x03) AM_DEVWRITE_LEGACY("adpcm", jan_adpcm_w)
333		AM_RANGE(0x04, 0x04) AM_READWRITE_LEGACY(jantotsu_mux_r, jantotsu_mux_w)
334		AM_RANGE(0x07, 0x07) AM_WRITE_LEGACY(bankaddr_w)
	334	AM_RANGE(0x04, 0x04) AM_READWRITE(jantotsu_mux_r, jantotsu_mux_w)
	335	AM_RANGE(0x07, 0x07) AM_WRITE(bankaddr_w)
335	336	ADDRESS_MAP_END
336	337
337	338

src/mame/drivers/photon2.c

r14845	r14846
28	28	UINT8 m_nmi_enable;
29	29
30	30	required_device<cpu_device> m_maincpu;
	31	DECLARE_WRITE8_MEMBER(photon2_membank_w);
	32	DECLARE_READ8_MEMBER(photon2_fe_r);
	33	DECLARE_WRITE8_MEMBER(photon2_fe_w);
	34	DECLARE_WRITE8_MEMBER(photon2_misc_w);
31	35	};
32	36
33	37
r14845	r14846
174	178	*
175	179	*************************************/
176	180
177		static WRITE8_HANDLER(photon2_membank_w)
	181	WRITE8_MEMBER(photon2_state::photon2_membank_w)
178	182	{
179	183	int bank = 0;
180	184	if (data == 0)
r14845	r14846
194	198	logerror( "Unknown banking write: %02X\n", data);
195	199	}
196	200
197		memory_set_bankptr(space->machine(), "bank1", space->machine().region("maincpu")->base() + 0x4000*bank );
	201	memory_set_bankptr(machine(), "bank1", machine().region("maincpu")->base() + 0x4000*bank );
198	202	}
199	203
200		static READ8_HANDLER(photon2_fe_r)
	204	READ8_MEMBER(photon2_state::photon2_fe_r)
201	205	{
202	206	return 0xff;
203	207	}
204	208
205		static WRITE8_HANDLER(photon2_fe_w)
	209	WRITE8_MEMBER(photon2_state::photon2_fe_w)
206	210	{
207		photon2_state *state = space->machine().driver_data<photon2_state>();
208		device_t *speaker = space->machine().device("speaker");
209		state->m_spectrum_port_fe = data;
	211	device_t *speaker = machine().device("speaker");
	212	m_spectrum_port_fe = data;
210	213
211	214	speaker_level_w(speaker, BIT(data,4));
212	215	}
213	216
214		static WRITE8_HANDLER(photon2_misc_w)
	217	WRITE8_MEMBER(photon2_state::photon2_misc_w)
215	218	{
216		photon2_state *state = space->machine().driver_data<photon2_state>();
217		state->m_nmi_enable = !BIT(data,5);
	219	m_nmi_enable = !BIT(data,5);
218	220	}
219	221
220	222	/*************************************
r14845	r14846
232	234	static ADDRESS_MAP_START (spectrum_io, AS_IO, 8, photon2_state )
233	235	ADDRESS_MAP_GLOBAL_MASK(0xff)
234	236	AM_RANGE(0x1f, 0x1f) AM_READ_PORT("JOY")
235		AM_RANGE(0x5b, 0x5b) AM_READ_PORT("COIN") AM_WRITE_LEGACY(photon2_misc_w)
236		AM_RANGE(0x7a, 0x7a) AM_WRITE_LEGACY(photon2_membank_w)
	237	AM_RANGE(0x5b, 0x5b) AM_READ_PORT("COIN") AM_WRITE(photon2_misc_w)
	238	AM_RANGE(0x7a, 0x7a) AM_WRITE(photon2_membank_w)
237	239	AM_RANGE(0x7b, 0x7b) AM_WRITENOP // unknown write
238		AM_RANGE(0x7e, 0x7e) AM_WRITE_LEGACY(photon2_membank_w)
239		AM_RANGE(0xfe, 0xfe) AM_READWRITE_LEGACY(photon2_fe_r, photon2_fe_w)
	240	AM_RANGE(0x7e, 0x7e) AM_WRITE(photon2_membank_w)
	241	AM_RANGE(0xfe, 0xfe) AM_READWRITE(photon2_fe_r, photon2_fe_w)
240	242	ADDRESS_MAP_END
241	243
242	244	/*************************************

src/mame/drivers/highvdeo.c

r14845	r14846
100	100	UINT16 m_vblank_bit;
101	101	UINT16 m_brasil_prot_latch;
102	102	struct { int r,g,b,offs,offs_internal; } m_pal;
	103	DECLARE_READ16_MEMBER(read1_r);
	104	DECLARE_READ16_MEMBER(read2_r);
	105	DECLARE_READ16_MEMBER(read3_r);
	106	DECLARE_WRITE16_MEMBER(tv_vcf_paletteram_w);
	107	DECLARE_WRITE16_MEMBER(tv_vcf_bankselect_w);
	108	DECLARE_WRITE16_MEMBER(write1_w);
	109	DECLARE_READ16_MEMBER(tv_ncf_read2_r);
	110	DECLARE_WRITE16_MEMBER(tv_tcf_paletteram_w);
	111	DECLARE_WRITE16_MEMBER(tv_tcf_bankselect_w);
	112	DECLARE_READ16_MEMBER(newmcard_status_r);
	113	DECLARE_READ16_MEMBER(newmcard_vblank_r);
	114	DECLARE_WRITE16_MEMBER(newmcard_vblank_w);
	115	DECLARE_WRITE16_MEMBER(write2_w);
	116	DECLARE_READ16_MEMBER(brasil_status_r);
	117	DECLARE_WRITE16_MEMBER(brasil_status_w);
	118	DECLARE_READ16_MEMBER(ciclone_status_r);
	119	DECLARE_WRITE16_MEMBER(fashion_output_w);
103	120	};
104	121
105	122
r14845	r14846
174	191
175	192
176	193
177		static READ16_HANDLER( read1_r )
	194	READ16_MEMBER(highvdeo_state::read1_r)
178	195	{
179		return input_port_read(space->machine(), "IN0");
	196	return input_port_read(machine(), "IN0");
180	197	}
181	198
182		static READ16_HANDLER( read2_r )
	199	READ16_MEMBER(highvdeo_state::read2_r)
183	200	{
184		return input_port_read(space->machine(), "IN1");
	201	return input_port_read(machine(), "IN1");
185	202	}
186	203
187		static READ16_HANDLER( read3_r )
	204	READ16_MEMBER(highvdeo_state::read3_r)
188	205	{
189		return input_port_read(space->machine(), "IN2");
	206	return input_port_read(machine(), "IN2");
190	207	}
191	208
192		static WRITE16_HANDLER( tv_vcf_paletteram_w )
	209	WRITE16_MEMBER(highvdeo_state::tv_vcf_paletteram_w)
193	210	{
194		highvdeo_state *state = space->machine().driver_data<highvdeo_state>();
195	211	switch(offset*2)
196	212	{
197	213	case 0:
198		state->m_pal.offs = data;
	214	m_pal.offs = data;
199	215	break;
200	216	case 2:
201		state->m_pal.offs_internal = 0;
	217	m_pal.offs_internal = 0;
202	218	break;
203	219	case 4:
204		switch(state->m_pal.offs_internal)
	220	switch(m_pal.offs_internal)
205	221	{
206	222	case 0:
207		state->m_pal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
208		state->m_pal.offs_internal++;
	223	m_pal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	224	m_pal.offs_internal++;
209	225	break;
210	226	case 1:
211		state->m_pal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
212		state->m_pal.offs_internal++;
	227	m_pal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	228	m_pal.offs_internal++;
213	229	break;
214	230	case 2:
215		state->m_pal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
216		palette_set_color(space->machine(), state->m_pal.offs, MAKE_RGB(state->m_pal.r, state->m_pal.g, state->m_pal.b));
217		state->m_pal.offs_internal = 0;
218		state->m_pal.offs++;
	231	m_pal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	232	palette_set_color(machine(), m_pal.offs, MAKE_RGB(m_pal.r, m_pal.g, m_pal.b));
	233	m_pal.offs_internal = 0;
	234	m_pal.offs++;
219	235	break;
220	236	}
221	237
r14845	r14846
223	239	}
224	240	}
225	241
226		static WRITE16_HANDLER( tv_vcf_bankselect_w )
	242	WRITE16_MEMBER(highvdeo_state::tv_vcf_bankselect_w)
227	243	{
228	244	UINT32 bankaddress;
229		UINT8 *ROM = space->machine().region("user1")->base();
	245	UINT8 *ROM = machine().region("user1")->base();
230	246
231	247	/* bits 0, 1 select the ROM bank */
232	248	bankaddress = (data & 0x03) * 0x40000;
233	249
234		memory_set_bankptr(space->machine(), "bank1", &ROM[bankaddress]);
	250	memory_set_bankptr(machine(), "bank1", &ROM[bankaddress]);
235	251	}
236	252
237	253
r14845	r14846
255	271	return 0xff;
256	272	}
257	273
258		static WRITE16_HANDLER( write1_w )
	274	WRITE16_MEMBER(highvdeo_state::write1_w)
259	275	{
260	276	/*
261	277	- Lbits -
r14845	r14846
287	303	ADDRESS_MAP_END
288	304
289	305	static ADDRESS_MAP_START( tv_vcf_io, AS_IO, 16, highvdeo_state )
290		AM_RANGE(0x0000, 0x0001) AM_WRITE_LEGACY(write1_w ) // lamps
	306	AM_RANGE(0x0000, 0x0001) AM_WRITE(write1_w ) // lamps
291	307	AM_RANGE(0x0006, 0x0007) AM_DEVWRITE_LEGACY("oki", tv_oki6376_w )
292		AM_RANGE(0x0008, 0x0009) AM_READ_LEGACY(read1_r )
293		AM_RANGE(0x000a, 0x000b) AM_READ_LEGACY(read2_r )
294		AM_RANGE(0x000c, 0x000d) AM_READ_LEGACY(read3_r )
295		AM_RANGE(0x0010, 0x0015) AM_WRITE_LEGACY(tv_vcf_paletteram_w )
296		AM_RANGE(0x0030, 0x0031) AM_WRITE_LEGACY(tv_vcf_bankselect_w ) AM_DEVREAD_LEGACY("oki", tv_oki6376_r )
	308	AM_RANGE(0x0008, 0x0009) AM_READ(read1_r )
	309	AM_RANGE(0x000a, 0x000b) AM_READ(read2_r )
	310	AM_RANGE(0x000c, 0x000d) AM_READ(read3_r )
	311	AM_RANGE(0x0010, 0x0015) AM_WRITE(tv_vcf_paletteram_w )
	312	AM_RANGE(0x0030, 0x0031) AM_WRITE(tv_vcf_bankselect_w ) AM_DEVREAD_LEGACY("oki", tv_oki6376_r )
297	313	ADDRESS_MAP_END
298	314
299	315
300		static READ16_HANDLER( tv_ncf_read2_r )
	316	READ16_MEMBER(highvdeo_state::tv_ncf_read2_r)
301	317	{
302	318	static int resetpulse = 0;
303	319
r14845	r14846
305	321	// machine resets itself.
306	322	resetpulse ^= 0x40;
307	323
308		return (input_port_read(space->machine(), "IN1") & 0xbf) | resetpulse;
	324	return (input_port_read(machine(), "IN1") & 0xbf) | resetpulse;
309	325	}
310	326
311	327	static WRITE16_DEVICE_HANDLER( tv_ncf_oki6376_w )
r14845	r14846
334	350	ADDRESS_MAP_END
335	351
336	352	static ADDRESS_MAP_START( tv_ncf_io, AS_IO, 16, highvdeo_state )
337		AM_RANGE(0x0000, 0x0001) AM_WRITE_LEGACY(write1_w ) // lamps
	353	AM_RANGE(0x0000, 0x0001) AM_WRITE(write1_w ) // lamps
338	354	AM_RANGE(0x0008, 0x0009) AM_DEVWRITE_LEGACY("oki", tv_ncf_oki6376_w )
339	355	AM_RANGE(0x000a, 0x000b) AM_DEVWRITE_LEGACY("oki", tv_ncf_oki6376_st_w )
340		AM_RANGE(0x000c, 0x000d) AM_READ_LEGACY(read1_r )
341		AM_RANGE(0x0010, 0x0011) AM_READ_LEGACY(tv_ncf_read2_r )
342		AM_RANGE(0x0012, 0x0013) AM_READ_LEGACY(read3_r )
343		AM_RANGE(0x0030, 0x0035) AM_WRITE_LEGACY(tv_vcf_paletteram_w )
	356	AM_RANGE(0x000c, 0x000d) AM_READ(read1_r )
	357	AM_RANGE(0x0010, 0x0011) AM_READ(tv_ncf_read2_r )
	358	AM_RANGE(0x0012, 0x0013) AM_READ(read3_r )
	359	AM_RANGE(0x0030, 0x0035) AM_WRITE(tv_vcf_paletteram_w )
344	360	ADDRESS_MAP_END
345	361
346	362
347		static WRITE16_HANDLER( tv_tcf_paletteram_w )
	363	WRITE16_MEMBER(highvdeo_state::tv_tcf_paletteram_w)
348	364	{
349	365	int r, g, b, color;
350	366
351		COMBINE_DATA(&space->machine().generic.paletteram.u16[offset]);
	367	COMBINE_DATA(&machine().generic.paletteram.u16[offset]);
352	368
353		color = space->machine().generic.paletteram.u16[offset];
	369	color = machine().generic.paletteram.u16[offset];
354	370	r = (color >> 8) & 0xf8;
355	371	g = (color >> 3) & 0xf8;
356	372	b = (color << 3) & 0xf8;
357	373
358		palette_set_color_rgb(space->machine(), offset, r, g, b);
	374	palette_set_color_rgb(machine(), offset, r, g, b);
359	375	}
360	376
361		static WRITE16_HANDLER( tv_tcf_bankselect_w )
	377	WRITE16_MEMBER(highvdeo_state::tv_tcf_bankselect_w)
362	378	{
363	379	UINT32 bankaddress;
364		UINT8 *ROM = space->machine().region("user1")->base();
	380	UINT8 *ROM = machine().region("user1")->base();
365	381
366	382	/* bits 0, 1, 2 select the ROM bank */
367	383	bankaddress = (data & 0x07) * 0x40000;
368	384
369		memory_set_bankptr(space->machine(), "bank1", &ROM[bankaddress]);
	385	memory_set_bankptr(machine(), "bank1", &ROM[bankaddress]);
370	386	}
371	387
372	388	static ADDRESS_MAP_START( tv_tcf_map, AS_PROGRAM, 16, highvdeo_state )
373	389	AM_RANGE(0x00000, 0x003ff) AM_RAM /*irq vector area*/
374	390	AM_RANGE(0x00400, 0x03fff) AM_RAM AM_SHARE("nvram")
375	391	AM_RANGE(0x40000, 0x5d4bf) AM_RAM AM_BASE(m_blit_ram) /*blitter ram*/
376		AM_RANGE(0x7fe00, 0x7ffff) AM_RAM_WRITE_LEGACY(tv_tcf_paletteram_w ) AM_BASE_GENERIC(paletteram)
	392	AM_RANGE(0x7fe00, 0x7ffff) AM_RAM_WRITE(tv_tcf_paletteram_w ) AM_BASE_GENERIC(paletteram)
377	393	AM_RANGE(0x80000, 0xbffff) AM_ROMBANK("bank1")
378	394	AM_RANGE(0xc0000, 0xfffff) AM_ROM AM_REGION("boot_prg",0)
379	395	ADDRESS_MAP_END
380	396
381	397	static ADDRESS_MAP_START( tv_tcf_io, AS_IO, 16, highvdeo_state )
382		AM_RANGE(0x0000, 0x0001) AM_WRITE_LEGACY(write1_w ) // lamps
	398	AM_RANGE(0x0000, 0x0001) AM_WRITE(write1_w ) // lamps
383	399	AM_RANGE(0x0006, 0x0007) AM_DEVWRITE_LEGACY("oki", tv_oki6376_w )
384		AM_RANGE(0x0008, 0x0009) AM_READ_LEGACY(read1_r )
385		AM_RANGE(0x000a, 0x000b) AM_READ_LEGACY(read2_r )
386		AM_RANGE(0x0030, 0x0031) AM_READ_LEGACY(read3_r ) AM_WRITE_LEGACY(tv_tcf_bankselect_w )
	400	AM_RANGE(0x0008, 0x0009) AM_READ(read1_r )
	401	AM_RANGE(0x000a, 0x000b) AM_READ(read2_r )
	402	AM_RANGE(0x0030, 0x0031) AM_READ(read3_r ) AM_WRITE(tv_tcf_bankselect_w )
387	403	ADDRESS_MAP_END
388	404
389	405	/****************************
r14845	r14846
392	408	*
393	409	****************************/
394	410
395		static READ16_HANDLER( newmcard_status_r )
	411	READ16_MEMBER(highvdeo_state::newmcard_status_r)
396	412	{
397	413	switch(offset*2)
398	414	{
r14845	r14846
403	419	}
404	420
405	421
406		static READ16_HANDLER( newmcard_vblank_r )
	422	READ16_MEMBER(highvdeo_state::newmcard_vblank_r)
407	423	{
408		highvdeo_state *state = space->machine().driver_data<highvdeo_state>();
409		return state->m_vblank_bit; //0x80
	424	return m_vblank_bit; //0x80
410	425	}
411	426
412		static WRITE16_HANDLER( newmcard_vblank_w )
	427	WRITE16_MEMBER(highvdeo_state::newmcard_vblank_w)
413	428	{
414		highvdeo_state *state = space->machine().driver_data<highvdeo_state>();
415		state->m_vblank_bit = data;
	429	m_vblank_bit = data;
416	430	}
417	431
418		static WRITE16_HANDLER( write2_w )
	432	WRITE16_MEMBER(highvdeo_state::write2_w)
419	433	{
420	434	int i;
421	435
r14845	r14846
423	437
424	438	for(i=0;i<4;i++)
425	439	{
426		coin_counter_w(space->machine(), i,data & 0x20);
427		coin_lockout_w(space->machine(), i,~data & 0x08);
	440	coin_counter_w(machine(), i,data & 0x20);
	441	coin_lockout_w(machine(), i,~data & 0x08);
428	442	}
429	443	}
430	444
r14845	r14846
437	451	ADDRESS_MAP_END
438	452
439	453	static ADDRESS_MAP_START( newmcard_io, AS_IO, 16, highvdeo_state )
440		AM_RANGE(0x0030, 0x0033) AM_READ_LEGACY(newmcard_status_r )
441		AM_RANGE(0x0030, 0x0031) AM_WRITE_LEGACY(tv_tcf_bankselect_w )
442		AM_RANGE(0x0000, 0x0001) AM_WRITE_LEGACY(write1_w ) // lamps
443		AM_RANGE(0x0002, 0x0003) AM_WRITE_LEGACY(write2_w ) // coin counter & coin lockout
444		AM_RANGE(0x0004, 0x0005) AM_WRITE_LEGACY(newmcard_vblank_w )
	454	AM_RANGE(0x0030, 0x0033) AM_READ(newmcard_status_r )
	455	AM_RANGE(0x0030, 0x0031) AM_WRITE(tv_tcf_bankselect_w )
	456	AM_RANGE(0x0000, 0x0001) AM_WRITE(write1_w ) // lamps
	457	AM_RANGE(0x0002, 0x0003) AM_WRITE(write2_w ) // coin counter & coin lockout
	458	AM_RANGE(0x0004, 0x0005) AM_WRITE(newmcard_vblank_w )
445	459	AM_RANGE(0x0006, 0x0007) AM_DEVWRITE_LEGACY("oki", tv_oki6376_w )
446		AM_RANGE(0x0008, 0x0009) AM_READ_LEGACY(read1_r )
447		AM_RANGE(0x000a, 0x000b) AM_READ_LEGACY(read2_r )
448		AM_RANGE(0x000c, 0x000d) AM_READ_LEGACY(newmcard_vblank_r )
449		AM_RANGE(0x000e, 0x000f) AM_READ_LEGACY(read3_r )
450		AM_RANGE(0x0010, 0x0015) AM_WRITE_LEGACY(tv_vcf_paletteram_w )
	460	AM_RANGE(0x0008, 0x0009) AM_READ(read1_r )
	461	AM_RANGE(0x000a, 0x000b) AM_READ(read2_r )
	462	AM_RANGE(0x000c, 0x000d) AM_READ(newmcard_vblank_r )
	463	AM_RANGE(0x000e, 0x000f) AM_READ(read3_r )
	464	AM_RANGE(0x0010, 0x0015) AM_WRITE(tv_vcf_paletteram_w )
451	465	ADDRESS_MAP_END
452	466
453	467	/****************************
r14845	r14846
457	471	****************************/
458	472
459	473
460		static READ16_HANDLER( brasil_status_r )
	474	READ16_MEMBER(highvdeo_state::brasil_status_r)
461	475	{
462		highvdeo_state *state = space->machine().driver_data<highvdeo_state>();
463	476	static UINT16 resetpulse;
464	477
465	478	switch(offset*2)
r14845	r14846
468	481	resetpulse^=0x10;
469	482
470	483	return 3 | resetpulse;
471		case 2: return (state->m_brasil_prot_latch & 3); //and 0x3f
	484	case 2: return (m_brasil_prot_latch & 3); //and 0x3f
472	485	}
473	486
474	487	return 0;
r14845	r14846
477	490
478	491
479	492	/*bankaddress might be incorrect.*/
480		static WRITE16_HANDLER( brasil_status_w )
	493	WRITE16_MEMBER(highvdeo_state::brasil_status_w)
481	494	{
482		highvdeo_state *state = space->machine().driver_data<highvdeo_state>();
483	495	UINT32 bankaddress;
484		UINT8 *ROM = space->machine().region("user1")->base();
	496	UINT8 *ROM = machine().region("user1")->base();
485	497
486	498	switch(data & 3) //data & 7?
487	499	{
488		case 0: state->m_brasil_prot_latch = 1; break;
489		case 1: state->m_brasil_prot_latch = 0; break;
490		case 2: state->m_brasil_prot_latch = 2; break;
	500	case 0: m_brasil_prot_latch = 1; break;
	501	case 1: m_brasil_prot_latch = 0; break;
	502	case 2: m_brasil_prot_latch = 2; break;
491	503	}
492	504
493	505	bankaddress = (data & 0x07) * 0x40000;
494	506
495		memory_set_bankptr(space->machine(), "bank1", &ROM[bankaddress]);
	507	memory_set_bankptr(machine(), "bank1", &ROM[bankaddress]);
496	508
497	509	//  popmessage("%04x",data);
498	510	}
r14845	r14846
506	518	ADDRESS_MAP_END
507	519
508	520	static ADDRESS_MAP_START( brasil_io, AS_IO, 16, highvdeo_state )
509		AM_RANGE(0x0030, 0x0033) AM_READ_LEGACY(brasil_status_r )
510		AM_RANGE(0x0030, 0x0031) AM_WRITE_LEGACY(brasil_status_w )
511		AM_RANGE(0x0000, 0x0001) AM_WRITE_LEGACY(write1_w ) // lamps
512		AM_RANGE(0x0002, 0x0003) AM_WRITE_LEGACY(write2_w ) // coin counter & coin lockout
	521	AM_RANGE(0x0030, 0x0033) AM_READ(brasil_status_r )
	522	AM_RANGE(0x0030, 0x0031) AM_WRITE(brasil_status_w )
	523	AM_RANGE(0x0000, 0x0001) AM_WRITE(write1_w ) // lamps
	524	AM_RANGE(0x0002, 0x0003) AM_WRITE(write2_w ) // coin counter & coin lockout
513	525	AM_RANGE(0x0006, 0x0007) AM_DEVWRITE_LEGACY("oki", tv_oki6376_w )
514		AM_RANGE(0x0008, 0x0009) AM_READ_LEGACY(read1_r )
515		AM_RANGE(0x000a, 0x000b) AM_READ_LEGACY(read2_r )
516		AM_RANGE(0x000e, 0x000f) AM_READ_LEGACY(read3_r )
	526	AM_RANGE(0x0008, 0x0009) AM_READ(read1_r )
	527	AM_RANGE(0x000a, 0x000b) AM_READ(read2_r )
	528	AM_RANGE(0x000e, 0x000f) AM_READ(read3_r )
517	529	//  AM_RANGE(0x000e, 0x000f) AM_WRITE
518	530	//  AM_RANGE(0xffa2, 0xffa3) AM_WRITE
519	531	ADDRESS_MAP_END
r14845	r14846
1160	1172	ROM_END
1161	1173
1162	1174	/*Ciclone*/
1163		static READ16_HANDLER( ciclone_status_r )
	1175	READ16_MEMBER(highvdeo_state::ciclone_status_r)
1164	1176	{
1165	1177	static UINT16 resetpulse;
1166	1178	switch(offset*2)
r14845	r14846
1176	1188
1177	1189	static DRIVER_INIT( ciclone )
1178	1190	{
1179		machine.device("maincpu")->memory().space(AS_IO)->install_legacy_read_handler(0x0030, 0x0033, FUNC(ciclone_status_r) );
	1191	highvdeo_state *state = machine.driver_data<highvdeo_state>();
	1192	machine.device("maincpu")->memory().space(AS_IO)->install_read_handler(0x0030, 0x0033, read16_delegate(FUNC(highvdeo_state::ciclone_status_r), state));
1180	1193	}
1181	1194
1182	1195	/*
r14845	r14846
1231	1244	ROM_LOAD( "sound-fashion-v-1-memory4m.u16", 0x00000, 0x80000, CRC(2927c799) SHA1(f11cad096a23fee10bfdff5bf944c96e30f4a8b8) )
1232	1245	ROM_END
1233	1246
1234		static WRITE16_HANDLER( fashion_output_w )
	1247	WRITE16_MEMBER(highvdeo_state::fashion_output_w)
1235	1248	{
1236	1249	int i;
1237	1250
r14845	r14846
1239	1252
1240	1253	for(i=0;i<4;i++)
1241	1254	{
1242		coin_counter_w(space->machine(), i,data & 0x20);
1243		coin_lockout_w(space->machine(), i,~data & 0x01);
	1255	coin_counter_w(machine(), i,data & 0x20);
	1256	coin_lockout_w(machine(), i,~data & 0x01);
1244	1257	}
1245	1258	}
1246	1259
1247	1260	static DRIVER_INIT( fashion )
1248	1261	{
1249		machine.device("maincpu")->memory().space(AS_IO)->install_legacy_write_handler(0x0002, 0x0003, FUNC(fashion_output_w) );
	1262	highvdeo_state *state = machine.driver_data<highvdeo_state>();
	1263	machine.device("maincpu")->memory().space(AS_IO)->install_write_handler(0x0002, 0x0003, write16_delegate(FUNC(highvdeo_state::fashion_output_w), state));
1250	1264	}
1251	1265
1252	1266	GAMEL( 2000, tour4000,  0,      tv_vcf,   tv_vcf,   0,       ROT0,  "High Video", "Tour 4000",         0, layout_fashion )

src/mame/drivers/nsmpoker.c

r14845	r14846
73	73	UINT8 *m_videoram;
74	74	UINT8 *m_colorram;
75	75	tilemap_t *m_bg_tilemap;
	76	DECLARE_WRITE8_MEMBER(nsmpoker_videoram_w);
	77	DECLARE_WRITE8_MEMBER(nsmpoker_colorram_w);
	78	DECLARE_WRITE8_MEMBER(debug_w);
	79	DECLARE_READ8_MEMBER(debug_r);
76	80	};
77	81
78	82
r14845	r14846
81	85	*************************/
82	86
83	87
84		static WRITE8_HANDLER( nsmpoker_videoram_w )
	88	WRITE8_MEMBER(nsmpoker_state::nsmpoker_videoram_w)
85	89	{
86		nsmpoker_state *state = space->machine().driver_data<nsmpoker_state>();
87		state->m_videoram[offset] = data;
88		state->m_bg_tilemap->mark_tile_dirty(offset);
	90	m_videoram[offset] = data;
	91	m_bg_tilemap->mark_tile_dirty(offset);
89	92	}
90	93
91	94
92		static WRITE8_HANDLER( nsmpoker_colorram_w )
	95	WRITE8_MEMBER(nsmpoker_state::nsmpoker_colorram_w)
93	96	{
94		nsmpoker_state *state = space->machine().driver_data<nsmpoker_state>();
95		state->m_colorram[offset] = data;
96		state->m_bg_tilemap->mark_tile_dirty(offset);
	97	m_colorram[offset] = data;
	98	m_bg_tilemap->mark_tile_dirty(offset);
97	99	}
98	100
99	101
r14845	r14846
145	147	device_set_input_line_and_vector(device, 0, ASSERT_LINE, 3);//2=nmi  3,4,5,6
146	148	}
147	149
148		//static WRITE8_HANDLER( debug_w )
	150	//WRITE8_MEMBER(nsmpoker_state::debug_w)
149	151	//{
150	152	//  popmessage("written : %02X", data);
151	153	//}
152	154
153		static READ8_HANDLER( debug_r )
	155	READ8_MEMBER(nsmpoker_state::debug_r)
154	156	{
155		return space->machine().rand() & 0xff;
	157	return machine().rand() & 0xff;
156	158	}
157	159
158	160
r14845	r14846
164	166	AM_RANGE(0x0000, 0x7fff) AM_ROM
165	167	AM_RANGE(0x9000, 0xafff) AM_RAM   // OK... cleared at beginning.
166	168	AM_RANGE(0xb000, 0xcfff) AM_ROM   // WRONG... just to map the last rom somewhere.
167		AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE_LEGACY(nsmpoker_videoram_w) AM_BASE(m_videoram) // WRONG... just a placeholder.
168		AM_RANGE(0xf000, 0xffff) AM_RAM_WRITE_LEGACY(nsmpoker_colorram_w) AM_BASE(m_colorram) // WRONG... just a placeholder.
	169	AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE(nsmpoker_videoram_w) AM_BASE(m_videoram) // WRONG... just a placeholder.
	170	AM_RANGE(0xf000, 0xffff) AM_RAM_WRITE(nsmpoker_colorram_w) AM_BASE(m_colorram) // WRONG... just a placeholder.
169	171	ADDRESS_MAP_END
170	172
171	173	static ADDRESS_MAP_START( nsmpoker_portmap, AS_IO, 8, nsmpoker_state )
172	174	ADDRESS_MAP_GLOBAL_MASK(0xff)
173		AM_RANGE(0xf0, 0xf0) AM_READ_LEGACY(debug_r)   // kind of trap at beginning
	175	AM_RANGE(0xf0, 0xf0) AM_READ(debug_r)   // kind of trap at beginning
174	176	ADDRESS_MAP_END
175	177
176	178	/* I/O byte R/W

src/mame/drivers/othello.c

r14845	r14846
73	73	device_t *m_n7751;
74	74	device_t *m_ay1;
75	75	device_t *m_ay2;
	76	DECLARE_READ8_MEMBER(unk_87_r);
	77	DECLARE_WRITE8_MEMBER(unk_8a_w);
	78	DECLARE_WRITE8_MEMBER(unk_8c_w);
	79	DECLARE_READ8_MEMBER(unk_8c_r);
	80	DECLARE_READ8_MEMBER(sound_ack_r);
	81	DECLARE_WRITE8_MEMBER(unk_8f_w);
	82	DECLARE_WRITE8_MEMBER(tilebank_w);
	83	DECLARE_READ8_MEMBER(latch_r);
	84	DECLARE_WRITE8_MEMBER(ay_select_w);
	85	DECLARE_WRITE8_MEMBER(ack_w);
	86	DECLARE_WRITE8_MEMBER(ay_address_w);
	87	DECLARE_WRITE8_MEMBER(ay_data_w);
	88	DECLARE_READ8_MEMBER(n7751_rom_r);
	89	DECLARE_READ8_MEMBER(n7751_command_r);
	90	DECLARE_READ8_MEMBER(n7751_t1_r);
76	91	};
77	92
78	93
r14845	r14846
124	139	AM_RANGE(0xf000, 0xffff) AM_RAM
125	140	ADDRESS_MAP_END
126	141
127		static READ8_HANDLER( unk_87_r )
	142	READ8_MEMBER(othello_state::unk_87_r)
128	143	{
129	144	/* n7751_status_r ?  bit 7 = ack/status from device connected  to port 8a? */
130		return space->machine().rand();
	145	return machine().rand();
131	146	}
132	147
133		static WRITE8_HANDLER( unk_8a_w )
	148	WRITE8_MEMBER(othello_state::unk_8a_w)
134	149	{
135	150	/*
136		othello_state *state = space->machine().driver_data<othello_state>();
137	151
138		state->m_n7751_command = (data & 0x07);
139		device_set_input_line(state->m_n7751, 0, ((data & 0x08) == 0) ? ASSERT_LINE : CLEAR_LINE);
140		//device_set_input_line(state->m_n7751, 0, (data & 0x02) ? CLEAR_LINE : ASSERT_LINE);
141		space->machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
	152
	153	m_n7751_command = (data & 0x07);
	154	device_set_input_line(m_n7751, 0, ((data & 0x08) == 0) ? ASSERT_LINE : CLEAR_LINE);
	155	//device_set_input_line(m_n7751, 0, (data & 0x02) ? CLEAR_LINE : ASSERT_LINE);
	156	machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100));
142	157	*/
143	158
144	159	logerror("8a -> %x\n", data);
145	160	}
146	161
147		static WRITE8_HANDLER( unk_8c_w )
	162	WRITE8_MEMBER(othello_state::unk_8c_w)
148	163	{
149	164	logerror("8c -> %x\n", data);
150	165	}
151	166
152		static READ8_HANDLER( unk_8c_r )
	167	READ8_MEMBER(othello_state::unk_8c_r)
153	168	{
154		return space->machine().rand();
	169	return machine().rand();
155	170	}
156	171
157		static READ8_HANDLER( sound_ack_r )
	172	READ8_MEMBER(othello_state::sound_ack_r)
158	173	{
159		othello_state *state = space->machine().driver_data<othello_state>();
160		return state->m_ack_data;
	174	return m_ack_data;
161	175	}
162	176
163		static WRITE8_HANDLER( unk_8f_w )
	177	WRITE8_MEMBER(othello_state::unk_8f_w)
164	178	{
165	179	logerror("8f -> %x\n", data);
166	180	}
167	181
168		static WRITE8_HANDLER( tilebank_w )
	182	WRITE8_MEMBER(othello_state::tilebank_w)
169	183	{
170		othello_state *state = space->machine().driver_data<othello_state>();
171		state->m_tile_bank = (data == 0x0f) ? 0x100 : 0x00;
	184	m_tile_bank = (data == 0x0f) ? 0x100 : 0x00;
172	185	logerror("tilebank -> %x\n", data);
173	186	}
174	187
r14845	r14846
179	192	AM_RANGE(0x80, 0x80) AM_READ_PORT("INP")
180	193	AM_RANGE(0x81, 0x81) AM_READ_PORT("SYSTEM")
181	194	AM_RANGE(0x83, 0x83) AM_READ_PORT("DSW")
182		AM_RANGE(0x86, 0x86) AM_WRITE_LEGACY(tilebank_w)
183		AM_RANGE(0x87, 0x87) AM_READ_LEGACY(unk_87_r)
184		AM_RANGE(0x8a, 0x8a) AM_WRITE_LEGACY(unk_8a_w)
185		AM_RANGE(0x8c, 0x8c) AM_READWRITE_LEGACY(unk_8c_r, unk_8c_w)
186		AM_RANGE(0x8d, 0x8d) AM_READWRITE_LEGACY(sound_ack_r, soundlatch_w)
187		AM_RANGE(0x8f, 0x8f) AM_WRITE_LEGACY(unk_8f_w)
	195	AM_RANGE(0x86, 0x86) AM_WRITE(tilebank_w)
	196	AM_RANGE(0x87, 0x87) AM_READ(unk_87_r)
	197	AM_RANGE(0x8a, 0x8a) AM_WRITE(unk_8a_w)
	198	AM_RANGE(0x8c, 0x8c) AM_READWRITE(unk_8c_r, unk_8c_w)
	199	AM_RANGE(0x8d, 0x8d) AM_READWRITE(sound_ack_r, soundlatch_w)
	200	AM_RANGE(0x8f, 0x8f) AM_WRITE(unk_8f_w)
188	201	ADDRESS_MAP_END
189	202
190		static READ8_HANDLER( latch_r )
	203	READ8_MEMBER(othello_state::latch_r)
191	204	{
192	205	int retval = soundlatch_r(space, 0);
193	206	soundlatch_clear_w(space, 0, 0);
194	207	return retval;
195	208	}
196	209
197		static WRITE8_HANDLER( ay_select_w )
	210	WRITE8_MEMBER(othello_state::ay_select_w)
198	211	{
199		othello_state *state = space->machine().driver_data<othello_state>();
200		state->m_ay_select = data;
	212	m_ay_select = data;
201	213	}
202	214
203		static WRITE8_HANDLER( ack_w )
	215	WRITE8_MEMBER(othello_state::ack_w)
204	216	{
205		othello_state *state = space->machine().driver_data<othello_state>();
206		state->m_ack_data = data;
	217	m_ack_data = data;
207	218	}
208	219
209		static WRITE8_HANDLER( ay_address_w )
	220	WRITE8_MEMBER(othello_state::ay_address_w)
210	221	{
211		othello_state *state = space->machine().driver_data<othello_state>();
212	222
213		if (state->m_ay_select & 1) ay8910_address_w(state->m_ay1, 0, data);
214		if (state->m_ay_select & 2) ay8910_address_w(state->m_ay2, 0, data);
	223	if (m_ay_select & 1) ay8910_address_w(m_ay1, 0, data);
	224	if (m_ay_select & 2) ay8910_address_w(m_ay2, 0, data);
215	225	}
216	226
217		static WRITE8_HANDLER( ay_data_w )
	227	WRITE8_MEMBER(othello_state::ay_data_w)
218	228	{
219		othello_state *state = space->machine().driver_data<othello_state>();
220	229
221		if (state->m_ay_select & 1) ay8910_data_w(state->m_ay1, 0, data);
222		if (state->m_ay_select & 2) ay8910_data_w(state->m_ay2, 0, data);
	230	if (m_ay_select & 1) ay8910_data_w(m_ay1, 0, data);
	231	if (m_ay_select & 2) ay8910_data_w(m_ay2, 0, data);
223	232	}
224	233
225	234	static ADDRESS_MAP_START( audio_map, AS_PROGRAM, 8, othello_state )
r14845	r14846
229	238
230	239	static ADDRESS_MAP_START( audio_portmap, AS_IO, 8, othello_state )
231	240	ADDRESS_MAP_GLOBAL_MASK(0xff)
232		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(latch_r)
233		AM_RANGE(0x01, 0x01) AM_WRITE_LEGACY(ay_data_w)
234		AM_RANGE(0x03, 0x03) AM_WRITE_LEGACY(ay_address_w)
235		AM_RANGE(0x04, 0x04) AM_WRITE_LEGACY(ack_w)
236		AM_RANGE(0x08, 0x08) AM_WRITE_LEGACY(ay_select_w)
	241	AM_RANGE(0x00, 0x00) AM_READ(latch_r)
	242	AM_RANGE(0x01, 0x01) AM_WRITE(ay_data_w)
	243	AM_RANGE(0x03, 0x03) AM_WRITE(ay_address_w)
	244	AM_RANGE(0x04, 0x04) AM_WRITE(ack_w)
	245	AM_RANGE(0x08, 0x08) AM_WRITE(ay_select_w)
237	246	ADDRESS_MAP_END
238	247
239	248	static WRITE8_DEVICE_HANDLER( n7751_rom_control_w )
r14845	r14846
271	280	}
272	281	}
273	282
274		static READ8_HANDLER( n7751_rom_r )
	283	READ8_MEMBER(othello_state::n7751_rom_r)
275	284	{
276		othello_state *state = space->machine().driver_data<othello_state>();
277		return space->machine().region("n7751data")->base()[state->m_sound_addr];
	285	return machine().region("n7751data")->base()[m_sound_addr];
278	286	}
279	287
280		static READ8_HANDLER( n7751_command_r )
	288	READ8_MEMBER(othello_state::n7751_command_r)
281	289	{
282		othello_state *state = space->machine().driver_data<othello_state>();
283		return 0x80 | ((state->m_n7751_command & 0x07) << 4);
	290	return 0x80 | ((m_n7751_command & 0x07) << 4);
284	291	}
285	292
286	293	static WRITE8_DEVICE_HANDLER( n7751_p2_w )
r14845	r14846
295	302	state->m_n7751_busy = data;
296	303	}
297	304
298		static READ8_HANDLER( n7751_t1_r )
	305	READ8_MEMBER(othello_state::n7751_t1_r)
299	306	{
300	307	/* T1 - labelled as "TEST", connected to ground */
301	308	return 0;
302	309	}
303	310
304	311	static ADDRESS_MAP_START( n7751_portmap, AS_IO, 8, othello_state )
305		AM_RANGE(MCS48_PORT_T1,   MCS48_PORT_T1) AM_READ_LEGACY(n7751_t1_r)
306		AM_RANGE(MCS48_PORT_P2,   MCS48_PORT_P2) AM_READ_LEGACY(n7751_command_r)
307		AM_RANGE(MCS48_PORT_BUS,  MCS48_PORT_BUS) AM_READ_LEGACY(n7751_rom_r)
	312	AM_RANGE(MCS48_PORT_T1,   MCS48_PORT_T1) AM_READ(n7751_t1_r)
	313	AM_RANGE(MCS48_PORT_P2,   MCS48_PORT_P2) AM_READ(n7751_command_r)
	314	AM_RANGE(MCS48_PORT_BUS,  MCS48_PORT_BUS) AM_READ(n7751_rom_r)
308	315	AM_RANGE(MCS48_PORT_P1,   MCS48_PORT_P1) AM_DEVWRITE_LEGACY("dac", dac_w)
309	316	AM_RANGE(MCS48_PORT_P2,   MCS48_PORT_P2) AM_DEVWRITE_LEGACY("n7751_8243", n7751_p2_w)
310	317	AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE_LEGACY("n7751_8243", i8243_prog_w)

src/mame/drivers/f-32.c

r14845	r14846
27	27	/* memory pointers */
28	28	required_device<e132xn_device>   m_maincpu;
29	29	UINT32 *  m_videoram;
	30	DECLARE_READ32_MEMBER(f32_input_port_1_r);
30	31	};
31	32
32	33
r14845	r14846
59	60	AM_RANGE(0xfff00000, 0xffffffff) AM_ROM AM_REGION("user1",0)
60	61	ADDRESS_MAP_END
61	62
62		static READ32_HANDLER( f32_input_port_1_r )
	63	READ32_MEMBER(mosaicf2_state::f32_input_port_1_r)
63	64	{
64	65	/* burn a bunch of cycles because this is polled frequently during busy loops */
65		mosaicf2_state *state = space->machine().driver_data<mosaicf2_state>();
66		offs_t pc = state->m_maincpu->pc();
	66
	67	offs_t pc = m_maincpu->pc();
67	68	if ((pc == 0x000379de) || (pc == 0x000379cc) )
68		state->m_maincpu->eat_cycles(100);
	69	m_maincpu->eat_cycles(100);
69	70	//else printf("PC %08x\n", pc );
70		return input_port_read(space->machine(), "SYSTEM_P2");
	71	return input_port_read(machine(), "SYSTEM_P2");
71	72	}
72	73
73	74
r14845	r14846
75	76	AM_RANGE(0x4000, 0x4003) AM_DEVREAD8("oki", okim6295_device, read, 0x000000ff)
76	77	AM_RANGE(0x4810, 0x4813) AM_DEVREAD8_LEGACY("ymsnd", ym2151_status_port_r, 0x000000ff)
77	78	AM_RANGE(0x5000, 0x5003) AM_READ_PORT("P1")
78		AM_RANGE(0x5200, 0x5203) AM_READ_LEGACY(f32_input_port_1_r)
	79	AM_RANGE(0x5200, 0x5203) AM_READ(f32_input_port_1_r)
79	80	AM_RANGE(0x5400, 0x5403) AM_READ_PORT("EEPROMIN")
80	81	AM_RANGE(0x6000, 0x6003) AM_DEVWRITE8("oki", okim6295_device, write, 0x000000ff)
81	82	AM_RANGE(0x6800, 0x6803) AM_DEVWRITE8_LEGACY("ymsnd", ym2151_data_port_w, 0x000000ff)

src/mame/drivers/majorpkr.c

r14845	r14846
473	473
474	474	required_device<okim6295_device> oki;
475	475
	476	DECLARE_WRITE8_MEMBER(rom_bank_w);
	477	DECLARE_WRITE8_MEMBER(palette_bank_w);
	478	DECLARE_READ8_MEMBER(paletteram_r);
	479	DECLARE_WRITE8_MEMBER(paletteram_w);
	480	DECLARE_WRITE8_MEMBER(vram_bank_w);
	481	DECLARE_READ8_MEMBER(vram_r);
	482	DECLARE_WRITE8_MEMBER(vram_w);
	483	DECLARE_WRITE8_MEMBER(vidreg_w);
	484	DECLARE_READ8_MEMBER(mux_port_r);
	485	DECLARE_READ8_MEMBER(mux_port2_r);
	486	DECLARE_WRITE8_MEMBER(mux_sel_w);
	487	DECLARE_WRITE8_MEMBER(lamps_a_w);
	488	DECLARE_WRITE8_MEMBER(lamps_b_w);
	489	DECLARE_WRITE8_MEMBER(pulses_w);
476	490	};
477	491
478	492
r14845	r14846
552	566	*         R/W Handlers        *
553	567	******************************/
554	568
555		static WRITE8_HANDLER(rom_bank_w)
	569	WRITE8_MEMBER(majorpkr_state::rom_bank_w)
556	570	{
557		memory_set_bank(space->machine(), "rom_bank", data & 0x3);
	571	memory_set_bank(machine(), "rom_bank", data & 0x3);
558	572	}
559	573
560	574
561		static WRITE8_HANDLER(palette_bank_w)
	575	WRITE8_MEMBER(majorpkr_state::palette_bank_w)
562	576	{
563		majorpkr_state *state = space->machine().driver_data<majorpkr_state>();
564	577
565		state->m_palette_bank=data;
	578	m_palette_bank=data;
566	579	}
567	580
568	581
569		static READ8_HANDLER(paletteram_r)
	582	READ8_MEMBER(majorpkr_state::paletteram_r)
570	583	{
571		majorpkr_state *state = space->machine().driver_data<majorpkr_state>();
572		return state->machine().generic.paletteram.u8[state->m_palette_bank * 0x800 + offset];
	584	return machine().generic.paletteram.u8[m_palette_bank * 0x800 + offset];
573	585	}
574	586
575		static WRITE8_HANDLER(paletteram_w)
	587	WRITE8_MEMBER(majorpkr_state::paletteram_w)
576	588	{
577		majorpkr_state *state = space->machine().driver_data<majorpkr_state>();
578		state->machine().generic.paletteram.u8[state->m_palette_bank * 0x800 + offset] = data;
	589	machine().generic.paletteram.u8[m_palette_bank * 0x800 + offset] = data;
579	590
580	591	offset >>= 1;
581		int color = state->machine().generic.paletteram.u8[state->m_palette_bank * 0x800 + offset * 2] + state->machine().generic.paletteram.u8[state->m_palette_bank * 0x800 + offset * 2 + 1] * 256;
582		palette_set_color(space->machine(), offset + state->m_palette_bank * 256 * 4, MAKE_RGB(pal5bit(color >> 5), pal5bit(color >> 10), pal5bit(color)));
	592	int color = machine().generic.paletteram.u8[m_palette_bank * 0x800 + offset * 2] + machine().generic.paletteram.u8[m_palette_bank * 0x800 + offset * 2 + 1] * 256;
	593	palette_set_color(machine(), offset + m_palette_bank * 256 * 4, MAKE_RGB(pal5bit(color >> 5), pal5bit(color >> 10), pal5bit(color)));
583	594	}
584	595
585	596
586		static WRITE8_HANDLER(vram_bank_w)
	597	WRITE8_MEMBER(majorpkr_state::vram_bank_w)
587	598	{
588		majorpkr_state *state = space->machine().driver_data<majorpkr_state>();
589		state->m_vram_bank = data;
	599	m_vram_bank = data;
590	600	}
591	601
592		static READ8_HANDLER(vram_r)
	602	READ8_MEMBER(majorpkr_state::vram_r)
593	603	{
594		majorpkr_state *state = space->machine().driver_data<majorpkr_state>();
595		return state->m_videoram[state->m_vram_bank * 0x800 + offset];
	604	return m_videoram[m_vram_bank * 0x800 + offset];
596	605	}
597	606
598		static WRITE8_HANDLER(vram_w)
	607	WRITE8_MEMBER(majorpkr_state::vram_w)
599	608	{
600		majorpkr_state *state = space->machine().driver_data<majorpkr_state>();
601		state->m_videoram[state->m_vram_bank * 0x800 + offset] = data;
	609	m_videoram[m_vram_bank * 0x800 + offset] = data;
602	610
603		if (state->m_vram_bank == 0)
	611	if (m_vram_bank == 0)
604	612	{
605		state->m_fg_tilemap->mark_tile_dirty(offset >> 1);
	613	m_fg_tilemap->mark_tile_dirty(offset >> 1);
606	614	}
607	615	else
608	616	{
609		if (state->m_vram_bank == 1)
	617	if (m_vram_bank == 1)
610	618	{
611		state->m_bg_tilemap->mark_tile_dirty(offset >> 1);
	619	m_bg_tilemap->mark_tile_dirty(offset >> 1);
612	620	}
613	621	else
614	622	{
615		//logerror("accessing vram bank %d (offset = %x , data = %x )\n", state->m_vram_bank, offset,data);
	623	//logerror("accessing vram bank %d (offset = %x , data = %x )\n", m_vram_bank, offset,data);
616	624	}
617	625	}
618	626	}
619	627
620		static WRITE8_HANDLER(vidreg_w)
	628	WRITE8_MEMBER(majorpkr_state::vidreg_w)
621	629	{
622		majorpkr_state *state = space->machine().driver_data<majorpkr_state>();
623	630
624	631	/*  If bit6 is active, the screen is drawn upside down.
625	632	(also 0xfc and 0x11 are written to the CRTC registers 0xc0 and 0xd0)
r14845	r14846
628	635	if (data & 0x40)
629	636	{
630	637	/* upside down screen */
631		state->m_flip_state = 1;
	638	m_flip_state = 1;
632	639	}
633	640
634	641	/*  If bit6 is not active, the screen is drawn normally.
r14845	r14846
638	645	else
639	646	{
640	647	/* normal screen */
641		state->m_flip_state = 0;
	648	m_flip_state = 0;
642	649	}
643	650	}
644	651
645	652
646	653	/***** Multiplexed Ports *****/
647	654
648		static READ8_HANDLER( mux_port_r )
	655	READ8_MEMBER(majorpkr_state::mux_port_r)
649	656	{
650		majorpkr_state *state = space->machine().driver_data<majorpkr_state>();
651	657
652		switch( (state->m_mux_data & 0xf0) )      /* 00-10-20-30-0F-1F-2F-3F */
	658	switch( (m_mux_data & 0xf0) )      /* 00-10-20-30-0F-1F-2F-3F */
653	659	{
654		case 0x00: return input_port_read(space->machine(), "DSW1");   /* confirmed */
655		case 0x10: return input_port_read(space->machine(), "DSW2");   /* confirmed */
656		case 0x20: return input_port_read(space->machine(), "DSW3");   /* confirmed */
657		case 0x30: return input_port_read(space->machine(), "DSW4");   /* confirmed */
	660	case 0x00: return input_port_read(machine(), "DSW1");   /* confirmed */
	661	case 0x10: return input_port_read(machine(), "DSW2");   /* confirmed */
	662	case 0x20: return input_port_read(machine(), "DSW3");   /* confirmed */
	663	case 0x30: return input_port_read(machine(), "DSW4");   /* confirmed */
658	664	}
659	665
660	666	return 0xff;
661	667	}
662	668
663		static READ8_HANDLER( mux_port2_r )
	669	READ8_MEMBER(majorpkr_state::mux_port2_r)
664	670	{
665		majorpkr_state *state = space->machine().driver_data<majorpkr_state>();
666	671
667		if ((state->m_mux_data & 0x0f) == 4)
	672	if ((m_mux_data & 0x0f) == 4)
668	673	{
669		return input_port_read(space->machine(), "IN0-1");
	674	return input_port_read(machine(), "IN0-1");
670	675	}
671	676	else
672	677	{
673		return input_port_read(space->machine(), "IN0-0");
	678	return input_port_read(machine(), "IN0-0");
674	679	}
675	680	}
676	681
677		static WRITE8_HANDLER( mux_sel_w )
	682	WRITE8_MEMBER(majorpkr_state::mux_sel_w)
678	683	{
679		majorpkr_state *state = space->machine().driver_data<majorpkr_state>();
680	684
681		state->m_mux_data = data;   /* 00-10-20-30-0F-1F-2F-3F */
	685	m_mux_data = data;   /* 00-10-20-30-0F-1F-2F-3F */
682	686	}
683	687
684	688
r14845	r14846
686	690	*    Lamps and Pulses    *
687	691	*************************/
688	692
689		static WRITE8_HANDLER( lamps_a_w )
	693	WRITE8_MEMBER(majorpkr_state::lamps_a_w)
690	694	{
691	695	/*  Lamps - Array A.
692	696
r14845	r14846
713	717	logerror("Lamps A: Write to 13h: %02x\n", data);
714	718	}
715	719
716		static WRITE8_HANDLER( lamps_b_w )
	720	WRITE8_MEMBER(majorpkr_state::lamps_b_w)
717	721	{
718	722	/*  Lamps - Array B.
719	723
r14845	r14846
738	742	logerror("Lamps B: Write to 14h: %02x\n", data);
739	743	}
740	744
741		static WRITE8_HANDLER( pulses_w )
	745	WRITE8_MEMBER(majorpkr_state::pulses_w)
742	746	{
743	747	/*  Pulses...
744	748
r14845	r14846
751	755	---x ----   Watchdog? (constant writes).
752	756	xxx- ----   Unknown.
753	757	*/
754		coin_counter_w(space->machine(), 3, data & 0x01);      /* Credits Out (all) */
755		coin_counter_w(space->machine(), 2, data & 0x02);      /* Credits 3 */
756		coin_counter_w(space->machine(), 0, data & 0x04);      /* Credits 1 */
757		coin_counter_w(space->machine(), 1, data & 0x08);      /* Credits 2 */
	758	coin_counter_w(machine(), 3, data & 0x01);      /* Credits Out (all) */
	759	coin_counter_w(machine(), 2, data & 0x02);      /* Credits 3 */
	760	coin_counter_w(machine(), 0, data & 0x04);      /* Credits 1 */
	761	coin_counter_w(machine(), 1, data & 0x08);      /* Credits 2 */
758	762
759	763	if (data & 0xe0)
760	764	logerror("Pulse: Write to 10h: %02x\n", data);
r14845	r14846
769	773	AM_RANGE(0x0000, 0xdfff) AM_ROM
770	774	AM_RANGE(0xe000, 0xe7ff) AM_ROM AM_ROMBANK("rom_bank")
771	775	AM_RANGE(0xe800, 0xefff) AM_RAM AM_SHARE("nvram")
772		AM_RANGE(0xf000, 0xf7ff) AM_READWRITE_LEGACY(paletteram_r, paletteram_w)   /* 4*4 palettes - 4 banks? */
773		AM_RANGE(0xf800, 0xffff) AM_READWRITE_LEGACY(vram_r, vram_w)            /* two tilemaps - 2 banks? */
	776	AM_RANGE(0xf000, 0xf7ff) AM_READWRITE(paletteram_r, paletteram_w)   /* 4*4 palettes - 4 banks? */
	777	AM_RANGE(0xf800, 0xffff) AM_READWRITE(vram_r, vram_w)            /* two tilemaps - 2 banks? */
774	778	ADDRESS_MAP_END
775	779
776	780	/*
r14845	r14846
796	800	*/
797	801	static ADDRESS_MAP_START( portmap, AS_IO, 8, majorpkr_state )
798	802	ADDRESS_MAP_GLOBAL_MASK(0xff)
799		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(rom_bank_w)
800		AM_RANGE(0x01, 0x01) AM_WRITE_LEGACY(palette_bank_w)
801		AM_RANGE(0x02, 0x02) AM_WRITE_LEGACY(vram_bank_w)
	803	AM_RANGE(0x00, 0x00) AM_WRITE(rom_bank_w)
	804	AM_RANGE(0x01, 0x01) AM_WRITE(palette_bank_w)
	805	AM_RANGE(0x02, 0x02) AM_WRITE(vram_bank_w)
802	806
803		AM_RANGE(0x10, 0x10) AM_READ_LEGACY(mux_port2_r)   /* muxed set of controls */
804		AM_RANGE(0x10, 0x10) AM_WRITE_LEGACY(pulses_w)      /* kind of watchdog on bit4... mech counters on bits 0-1-2-3 */
	807	AM_RANGE(0x10, 0x10) AM_READ(mux_port2_r)   /* muxed set of controls */
	808	AM_RANGE(0x10, 0x10) AM_WRITE(pulses_w)      /* kind of watchdog on bit4... mech counters on bits 0-1-2-3 */
805	809	AM_RANGE(0x11, 0x11) AM_READ_PORT("IN1")
806		AM_RANGE(0x11, 0x11) AM_WRITE_LEGACY(mux_sel_w)   /* multiplexer selector */
	810	AM_RANGE(0x11, 0x11) AM_WRITE(mux_sel_w)   /* multiplexer selector */
807	811	AM_RANGE(0x12, 0x12) AM_READ_PORT("IN2")
808		AM_RANGE(0x12, 0x12) AM_WRITE_LEGACY(vidreg_w)      /* video registers: normal or up down screen */
809		AM_RANGE(0x13, 0x13) AM_READ_LEGACY(mux_port_r)   /* all 4 DIP switches banks multiplexed */
810		AM_RANGE(0x13, 0x13) AM_WRITE_LEGACY(lamps_a_w)   /* lamps a out */
	812	AM_RANGE(0x12, 0x12) AM_WRITE(vidreg_w)      /* video registers: normal or up down screen */
	813	AM_RANGE(0x13, 0x13) AM_READ(mux_port_r)   /* all 4 DIP switches banks multiplexed */
	814	AM_RANGE(0x13, 0x13) AM_WRITE(lamps_a_w)   /* lamps a out */
811	815	AM_RANGE(0x14, 0x14) AM_READ_PORT("TEST")   /* "freeze" switch */
812		AM_RANGE(0x14, 0x14) AM_WRITE_LEGACY(lamps_b_w)   /* lamps b out */
	816	AM_RANGE(0x14, 0x14) AM_WRITE(lamps_b_w)   /* lamps b out */
813	817
814	818	AM_RANGE(0x30, 0x30) AM_DEVWRITE("crtc", mc6845_device, address_w)
815	819	AM_RANGE(0x31, 0x31) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)

src/mame/drivers/sshot.c

r14845	r14846
167	167
168	168	UINT8      *m_videoram;
169	169	tilemap_t   *m_tilemap;
	170	DECLARE_WRITE8_MEMBER(supershot_vidram_w);
	171	DECLARE_WRITE8_MEMBER(supershot_output0_w);
	172	DECLARE_WRITE8_MEMBER(supershot_output1_w);
170	173	};
171	174
172	175	/*************************************
r14845	r14846
196	199	return 0;
197	200	}
198	201
199		static WRITE8_HANDLER( supershot_vidram_w )
	202	WRITE8_MEMBER(supershot_state::supershot_vidram_w)
200	203	{
201		supershot_state *state = space->machine().driver_data<supershot_state>();
202	204
203		state->m_videoram[offset] = data;
204		state->m_tilemap->mark_tile_dirty(offset);
	205	m_videoram[offset] = data;
	206	m_tilemap->mark_tile_dirty(offset);
205	207	}
206	208
207	209	/*************************************
r14845	r14846
210	212	*
211	213	*************************************/
212	214
213		static WRITE8_HANDLER(supershot_output0_w)
	215	WRITE8_MEMBER(supershot_state::supershot_output0_w)
214	216	{
215	217	/*
216	218	bit     signal      description
r14845	r14846
226	228	*/
227	229	}
228	230
229		static WRITE8_HANDLER(supershot_output1_w)
	231	WRITE8_MEMBER(supershot_state::supershot_output1_w)
230	232	{
231	233	/*
232	234	bit     signal      description
r14845	r14846
250	252
251	253	static ADDRESS_MAP_START( supershot_map, AS_PROGRAM, 8, supershot_state )
252	254	AM_RANGE(0x0000, 0x1fff) AM_ROM
253		AM_RANGE(0x2000, 0x23ff) AM_RAM_WRITE_LEGACY(supershot_vidram_w ) AM_BASE(m_videoram )
	255	AM_RANGE(0x2000, 0x23ff) AM_RAM_WRITE(supershot_vidram_w ) AM_BASE(m_videoram )
254	256	AM_RANGE(0x4100, 0x41ff) AM_RAM
255	257	AM_RANGE(0x4200, 0x4200) AM_READ_PORT("GUNX")
256	258	AM_RANGE(0x4201, 0x4201) AM_READ_PORT("GUNY")
257	259	AM_RANGE(0x4202, 0x4202) AM_READ_PORT("IN0")
258	260	AM_RANGE(0x4203, 0x4203) AM_READ_PORT("DSW")
259		AM_RANGE(0x4206, 0x4206) AM_WRITE_LEGACY(supershot_output0_w)
260		AM_RANGE(0x4207, 0x4207) AM_WRITE_LEGACY(supershot_output1_w)
	261	AM_RANGE(0x4206, 0x4206) AM_WRITE(supershot_output0_w)
	262	AM_RANGE(0x4207, 0x4207) AM_WRITE(supershot_output1_w)
261	263	ADDRESS_MAP_END
262	264
263	265	/*************************************

src/mame/drivers/gstream.c

r14845	r14846
159	159	required_device<e132xt_device> m_maincpu;
160	160	required_device<okim6295_device> m_oki_1;
161	161	required_device<okim6295_device> m_oki_2;
	162	DECLARE_WRITE32_MEMBER(gstream_palette_w);
	163	DECLARE_WRITE32_MEMBER(gstream_vram_w);
	164	DECLARE_WRITE32_MEMBER(gstream_tilemap1_scrollx_w);
	165	DECLARE_WRITE32_MEMBER(gstream_tilemap1_scrolly_w);
	166	DECLARE_WRITE32_MEMBER(gstream_tilemap2_scrollx_w);
	167	DECLARE_WRITE32_MEMBER(gstream_tilemap2_scrolly_w);
	168	DECLARE_WRITE32_MEMBER(gstream_tilemap3_scrollx_w);
	169	DECLARE_WRITE32_MEMBER(gstream_tilemap3_scrolly_w);
	170	DECLARE_WRITE32_MEMBER(gstream_oki_banking_w);
	171	DECLARE_WRITE32_MEMBER(gstream_oki_4040_w);
	172	DECLARE_READ32_MEMBER(gstream_speedup_r);
162	173	};
163	174
164	175
r14845	r14846
192	203	}
193	204
194	205
195		static WRITE32_HANDLER( gstream_palette_w )
	206	WRITE32_MEMBER(gstream_state::gstream_palette_w)
196	207	{
197		gstream_state *state = space->machine().driver_data<gstream_state>();
198		COMBINE_DATA(&state->m_paletteram[offset]);
	208	COMBINE_DATA(&m_paletteram[offset]);
199	209
200		palette_set_color_rgb(space->machine(), offset * 2, pal5bit(state->m_paletteram[offset] >> (0 + 16)),
201		pal5bit(state->m_paletteram[offset] >> (6 + 16)),
202		pal5bit(state->m_paletteram[offset] >> (11 + 16)));
	210	palette_set_color_rgb(machine(), offset * 2, pal5bit(m_paletteram[offset] >> (0 + 16)),
	211	pal5bit(m_paletteram[offset] >> (6 + 16)),
	212	pal5bit(m_paletteram[offset] >> (11 + 16)));
203	213
204	214
205		palette_set_color_rgb(space->machine(),offset * 2 + 1,pal5bit(state->m_paletteram[offset] >> (0)),
206		pal5bit(state->m_paletteram[offset] >> (6)),
207		pal5bit(state->m_paletteram[offset] >> (11)));
	215	palette_set_color_rgb(machine(),offset * 2 + 1,pal5bit(m_paletteram[offset] >> (0)),
	216	pal5bit(m_paletteram[offset] >> (6)),
	217	pal5bit(m_paletteram[offset] >> (11)));
208	218	}
209	219
210		static WRITE32_HANDLER( gstream_vram_w )
	220	WRITE32_MEMBER(gstream_state::gstream_vram_w)
211	221	{
212		gstream_state *state = space->machine().driver_data<gstream_state>();
213		COMBINE_DATA(&state->m_vram[offset]);
	222	COMBINE_DATA(&m_vram[offset]);
214	223
215	224	if (ACCESSING_BITS_24_31)
216	225	{
217	226	if (offset >= 0x000 / 4 && offset < 0x400 / 4)
218	227	{
219		state->m_tilemap1->mark_tile_dirty(offset - (0x000 / 4));
	228	m_tilemap1->mark_tile_dirty(offset - (0x000 / 4));
220	229	}
221	230	else if (offset >= 0x400 / 4 && offset < 0x800 / 4)
222	231	{
223		state->m_tilemap2->mark_tile_dirty(offset - (0x400 / 4));
	232	m_tilemap2->mark_tile_dirty(offset - (0x400 / 4));
224	233	}
225	234	else if (offset >= 0x800 / 4 && offset < 0xc00 / 4)
226	235	{
227		state->m_tilemap3->mark_tile_dirty(offset - (0x800 / 4));
	236	m_tilemap3->mark_tile_dirty(offset - (0x800 / 4));
228	237	}
229	238	}
230	239	}
231	240
232		static WRITE32_HANDLER( gstream_tilemap1_scrollx_w )
	241	WRITE32_MEMBER(gstream_state::gstream_tilemap1_scrollx_w)
233	242	{
234		gstream_state *state = space->machine().driver_data<gstream_state>();
235		state->m_tmap1_scrollx = data;
	243	m_tmap1_scrollx = data;
236	244	}
237	245
238		static WRITE32_HANDLER( gstream_tilemap1_scrolly_w )
	246	WRITE32_MEMBER(gstream_state::gstream_tilemap1_scrolly_w)
239	247	{
240		gstream_state *state = space->machine().driver_data<gstream_state>();
241		state->m_tmap1_scrolly = data;
	248	m_tmap1_scrolly = data;
242	249	}
243	250
244		static WRITE32_HANDLER( gstream_tilemap2_scrollx_w )
	251	WRITE32_MEMBER(gstream_state::gstream_tilemap2_scrollx_w)
245	252	{
246		gstream_state *state = space->machine().driver_data<gstream_state>();
247		state->m_tmap2_scrollx = data;
	253	m_tmap2_scrollx = data;
248	254	}
249	255
250		static WRITE32_HANDLER( gstream_tilemap2_scrolly_w )
	256	WRITE32_MEMBER(gstream_state::gstream_tilemap2_scrolly_w)
251	257	{
252		gstream_state *state = space->machine().driver_data<gstream_state>();
253		state->m_tmap2_scrolly = data;
	258	m_tmap2_scrolly = data;
254	259	}
255	260
256		static WRITE32_HANDLER( gstream_tilemap3_scrollx_w )
	261	WRITE32_MEMBER(gstream_state::gstream_tilemap3_scrollx_w)
257	262	{
258		gstream_state *state = space->machine().driver_data<gstream_state>();
259		state->m_tmap3_scrollx = data;
	263	m_tmap3_scrollx = data;
260	264	}
261	265
262		static WRITE32_HANDLER( gstream_tilemap3_scrolly_w )
	266	WRITE32_MEMBER(gstream_state::gstream_tilemap3_scrolly_w)
263	267	{
264		gstream_state *state = space->machine().driver_data<gstream_state>();
265		state->m_tmap3_scrolly = data;
	268	m_tmap3_scrolly = data;
266	269	}
267	270
268	271	static ADDRESS_MAP_START( gstream_32bit_map, AS_PROGRAM, 32, gstream_state )
269	272	AM_RANGE(0x00000000, 0x003FFFFF) AM_RAM AM_BASE(m_workram) // work ram
270	273	//  AM_RANGE(0x40000000, 0x40FFFFFF) AM_RAM // ?? lots of data gets copied here if present, but game runs without it??
271		AM_RANGE(0x80000000, 0x80003FFF) AM_RAM_WRITE_LEGACY(gstream_vram_w) AM_BASE(m_vram) // video ram
	274	AM_RANGE(0x80000000, 0x80003FFF) AM_RAM_WRITE(gstream_vram_w) AM_BASE(m_vram) // video ram
272	275	AM_RANGE(0x4E000000, 0x4E1FFFFF) AM_ROM AM_REGION("user2",0) // main game rom
273		AM_RANGE(0x4F000000, 0x4F000003) AM_WRITE_LEGACY(gstream_tilemap3_scrollx_w)
274		AM_RANGE(0x4F200000, 0x4F200003) AM_WRITE_LEGACY(gstream_tilemap3_scrolly_w)
275		AM_RANGE(0x4F400000, 0x4F406FFF) AM_RAM_WRITE_LEGACY(gstream_palette_w) AM_BASE(m_paletteram)
276		AM_RANGE(0x4F800000, 0x4F800003) AM_WRITE_LEGACY(gstream_tilemap1_scrollx_w)
277		AM_RANGE(0x4FA00000, 0x4FA00003) AM_WRITE_LEGACY(gstream_tilemap1_scrolly_w)
278		AM_RANGE(0x4FC00000, 0x4FC00003) AM_WRITE_LEGACY(gstream_tilemap2_scrollx_w)
279		AM_RANGE(0x4FE00000, 0x4FE00003) AM_WRITE_LEGACY(gstream_tilemap2_scrolly_w)
	276	AM_RANGE(0x4F000000, 0x4F000003) AM_WRITE(gstream_tilemap3_scrollx_w)
	277	AM_RANGE(0x4F200000, 0x4F200003) AM_WRITE(gstream_tilemap3_scrolly_w)
	278	AM_RANGE(0x4F400000, 0x4F406FFF) AM_RAM_WRITE(gstream_palette_w) AM_BASE(m_paletteram)
	279	AM_RANGE(0x4F800000, 0x4F800003) AM_WRITE(gstream_tilemap1_scrollx_w)
	280	AM_RANGE(0x4FA00000, 0x4FA00003) AM_WRITE(gstream_tilemap1_scrolly_w)
	281	AM_RANGE(0x4FC00000, 0x4FC00003) AM_WRITE(gstream_tilemap2_scrollx_w)
	282	AM_RANGE(0x4FE00000, 0x4FE00003) AM_WRITE(gstream_tilemap2_scrolly_w)
280	283	AM_RANGE(0xFFC00000, 0xFFC01FFF) AM_RAM AM_SHARE("nvram") // Backup RAM
281	284	AM_RANGE(0xFFF80000, 0xFFFFFFFF) AM_ROM AM_REGION("user1",0) // boot rom
282	285	ADDRESS_MAP_END
283	286
284		static WRITE32_HANDLER( gstream_oki_banking_w )
	287	WRITE32_MEMBER(gstream_state::gstream_oki_banking_w)
285	288	{
286	289	/* OKI BANKING  (still far from perfect, based on game behaviour)
287	290
r14845	r14846
314	317
315	318	Musics order is completely guessed but close to what the original PCB game should be */
316	319
317		gstream_state *state = space->machine().driver_data<gstream_state>();
318	320	static const int bank_table_0[16] = { -1, -1, -1, -1, -1, -1, 0, 0, -1, 6, 0, 5, -1, 0, 0, 0 };
319	321	static const int bank_table_1[16] = { -1, -1, -1, -1, -1, -1, 2, 2, -1, 0, 0, 4, -1, 1, 1, 1 };
320	322
321	323	//popmessage("oki_0 banking value = %X\noki_1 banking value = %X\n",data & 0xf,(data >> 4) & 0xf);
322	324
323		state->m_oki_bank_0 = bank_table_0[data & 0xf];
324		state->m_oki_bank_1 = bank_table_1[data & 0xf];      // (data >> 4) & 0xf ??
	325	m_oki_bank_0 = bank_table_0[data & 0xf];
	326	m_oki_bank_1 = bank_table_1[data & 0xf];      // (data >> 4) & 0xf ??
325	327
326	328	/* some values are already used in the table, so we force them manually */
327	329	if ((data == 0x6f) || (data == 0x6e))
328	330	{
329		state->m_oki_bank_0 = 0;   // level 3b-5a samples
330		state->m_oki_bank_1 = 6;      // level 3b-5a music
	331	m_oki_bank_0 = 0;   // level 3b-5a samples
	332	m_oki_bank_1 = 6;      // level 3b-5a music
331	333	}
332	334
333	335	if (data == 0x9b)
334	336	{
335		state->m_oki_bank_0 = 7;      // level 7 music
336		state->m_oki_bank_1 = 0;      // level 7 samples
	337	m_oki_bank_0 = 7;      // level 7 music
	338	m_oki_bank_1 = 0;      // level 7 samples
337	339	}
338	340
339	341	if (data == 0x9f)
340	342	{
341		state->m_oki_bank_0 = 0;      // end sequence samples
342		state->m_oki_bank_1 = 3;      // end sequence music
	343	m_oki_bank_0 = 0;      // end sequence samples
	344	m_oki_bank_1 = 3;      // end sequence music
343	345	}
344	346
345		state->m_oki_1->set_bank_base(state->m_oki_bank_0 * 0x40000);
346		state->m_oki_2->set_bank_base(state->m_oki_bank_1 * 0x40000);
	347	m_oki_1->set_bank_base(m_oki_bank_0 * 0x40000);
	348	m_oki_2->set_bank_base(m_oki_bank_1 * 0x40000);
347	349	}
348	350
349		static WRITE32_HANDLER( gstream_oki_4040_w )
	351	WRITE32_MEMBER(gstream_state::gstream_oki_4040_w)
350	352	{
351	353	// data == 0 or data == 0x81
352	354	}
r14845	r14846
355	357	AM_RANGE(0x4000, 0x4003) AM_READ_PORT("IN0")
356	358	AM_RANGE(0x4010, 0x4013) AM_READ_PORT("IN1")
357	359	AM_RANGE(0x4020, 0x4023) AM_READ_PORT("IN2")   // extra coin switches etc
358		AM_RANGE(0x4030, 0x4033) AM_WRITE_LEGACY(gstream_oki_banking_w)   // oki banking
359		AM_RANGE(0x4040, 0x4043) AM_WRITE_LEGACY(gstream_oki_4040_w)   // ??
	360	AM_RANGE(0x4030, 0x4033) AM_WRITE(gstream_oki_banking_w)   // oki banking
	361	AM_RANGE(0x4040, 0x4043) AM_WRITE(gstream_oki_4040_w)   // ??
360	362	AM_RANGE(0x4050, 0x4053) AM_DEVREADWRITE8("oki2", okim6295_device, read, write, 0x000000ff)   // music and samples
361	363	AM_RANGE(0x4060, 0x4063) AM_DEVREADWRITE8("oki1", okim6295_device, read, write, 0x000000ff)   // music and samples
362	364	ADDRESS_MAP_END
r14845	r14846
627	629	ROM_LOAD( "gstream.nv", 0x000000, 0x2000, CRC(895d724b) SHA1(97941102f94923220d9beb270939f0ad9a40fe0e) )
628	630	ROM_END
629	631
630		static READ32_HANDLER( gstream_speedup_r )
	632	READ32_MEMBER(gstream_state::gstream_speedup_r)
631	633	{
632		gstream_state *state = space->machine().driver_data<gstream_state>();
633		if (state->m_maincpu->state(STATE_GENPC) == 0xc0001592)
	634	if (m_maincpu->state(STATE_GENPC) == 0xc0001592)
634	635	{
635		state->m_maincpu->eat_cycles(50);
	636	m_maincpu->eat_cycles(50);
636	637	}
637	638
638		return state->m_workram[0xd1ee0 / 4];
	639	return m_workram[0xd1ee0 / 4];
639	640	}
640	641
641	642	static DRIVER_INIT( gstream )
642	643	{
643		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xd1ee0, 0xd1ee3, FUNC(gstream_speedup_r) );
	644	gstream_state *state = machine.driver_data<gstream_state>();
	645	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0xd1ee0, 0xd1ee3, read32_delegate(FUNC(gstream_state::gstream_speedup_r), state));
644	646	}
645	647
646	648

src/mame/drivers/igs017.c

r14845	r14846
78	78	UINT8 *m_spriteram;
79	79
80	80	required_device<cpu_device> m_maincpu;
	81	DECLARE_WRITE8_MEMBER(video_disable_w);
	82	DECLARE_WRITE16_MEMBER(video_disable_lsb_w);
	83	DECLARE_WRITE8_MEMBER(fg_w);
	84	DECLARE_WRITE8_MEMBER(bg_w);
	85	DECLARE_READ16_MEMBER(fg_lsb_r);
	86	DECLARE_WRITE16_MEMBER(fg_lsb_w);
	87	DECLARE_READ16_MEMBER(bg_lsb_r);
	88	DECLARE_WRITE16_MEMBER(bg_lsb_w);
	89	DECLARE_READ16_MEMBER(spriteram_lsb_r);
	90	DECLARE_WRITE16_MEMBER(spriteram_lsb_w);
	91	DECLARE_WRITE8_MEMBER(nmi_enable_w);
	92	DECLARE_WRITE8_MEMBER(irq_enable_w);
	93	DECLARE_WRITE8_MEMBER(input_select_w);
	94	DECLARE_READ8_MEMBER(input_r);
	95	DECLARE_WRITE16_MEMBER(mgcs_magic_w);
	96	DECLARE_READ16_MEMBER(mgcs_magic_r);
	97	DECLARE_WRITE16_MEMBER(irq1_enable_w);
	98	DECLARE_WRITE16_MEMBER(irq2_enable_w);
	99	DECLARE_WRITE16_MEMBER(mgcs_paletteram_w);
	100	DECLARE_WRITE16_MEMBER(sdmg2_paletteram_w);
	101	DECLARE_READ8_MEMBER(sdmg2_keys_r);
	102	DECLARE_WRITE16_MEMBER(sdmg2_magic_w);
	103	DECLARE_READ16_MEMBER(sdmg2_magic_r);
	104	DECLARE_READ8_MEMBER(mgdh_keys_r);
	105	DECLARE_WRITE16_MEMBER(mgdha_magic_w);
	106	DECLARE_READ16_MEMBER(mgdha_magic_r);
	107	DECLARE_WRITE8_MEMBER(tjsb_paletteram_w);
	108	DECLARE_WRITE8_MEMBER(tjsb_output_w);
	109	DECLARE_READ8_MEMBER(tjsb_input_r);
81	110	};
82	111
83	112
r14845	r14846
86	115	Video Hardware
87	116	***************************************************************************/
88	117
89		static WRITE8_HANDLER( video_disable_w )
	118	WRITE8_MEMBER(igs017_state::video_disable_w)
90	119	{
91		igs017_state *state = space->machine().driver_data<igs017_state>();
92		state->m_video_disable = data & 1;
	120	m_video_disable = data & 1;
93	121	if (data & (~1))
94		logerror("PC %06X: unknown bits of video_disable written = %02x\n",cpu_get_pc(&space->device()),data);
	122	logerror("PC %06X: unknown bits of video_disable written = %02x\n",cpu_get_pc(&space.device()),data);
95	123	//  popmessage("VIDEO %02X",data);
96	124	}
97		static WRITE16_HANDLER( video_disable_lsb_w )
	125	WRITE16_MEMBER(igs017_state::video_disable_lsb_w)
98	126	{
99	127	if (ACCESSING_BITS_0_7)
100	128	video_disable_w(space,offset,data);
r14845	r14846
124	152	SET_TILE_INFO(0, code, COLOR(attr)+8, TILE_FLIPXY( attr >> 5 ));
125	153	}
126	154
127		static WRITE8_HANDLER( fg_w )
	155	WRITE8_MEMBER(igs017_state::fg_w)
128	156	{
129		igs017_state *state = space->machine().driver_data<igs017_state>();
130		state->m_fg_videoram[offset] = data;
131		state->m_fg_tilemap->mark_tile_dirty(offset/4);
	157	m_fg_videoram[offset] = data;
	158	m_fg_tilemap->mark_tile_dirty(offset/4);
132	159	}
133	160
134		static WRITE8_HANDLER( bg_w )
	161	WRITE8_MEMBER(igs017_state::bg_w)
135	162	{
136		igs017_state *state = space->machine().driver_data<igs017_state>();
137		state->m_bg_videoram[offset] = data;
138		state->m_bg_tilemap->mark_tile_dirty(offset/4);
	163	m_bg_videoram[offset] = data;
	164	m_bg_tilemap->mark_tile_dirty(offset/4);
139	165	}
140	166
141	167	// 16-bit handlers for an 8-bit chip
142	168
143		static READ16_HANDLER( fg_lsb_r )
	169	READ16_MEMBER(igs017_state::fg_lsb_r)
144	170	{
145		igs017_state *state = space->machine().driver_data<igs017_state>();
146		return state->m_fg_videoram[offset];
	171	return m_fg_videoram[offset];
147	172	}
148		static WRITE16_HANDLER( fg_lsb_w )
	173	WRITE16_MEMBER(igs017_state::fg_lsb_w)
149	174	{
150	175	if (ACCESSING_BITS_0_7)
151	176	fg_w(space,offset,data);
152	177	}
153	178
154		static READ16_HANDLER( bg_lsb_r )
	179	READ16_MEMBER(igs017_state::bg_lsb_r)
155	180	{
156		igs017_state *state = space->machine().driver_data<igs017_state>();
157		return state->m_bg_videoram[offset];
	181	return m_bg_videoram[offset];
158	182	}
159		static WRITE16_HANDLER( bg_lsb_w )
	183	WRITE16_MEMBER(igs017_state::bg_lsb_w)
160	184	{
161	185	if (ACCESSING_BITS_0_7)
162	186	bg_w(space,offset,data);
163	187	}
164	188
165		static READ16_HANDLER( spriteram_lsb_r )
	189	READ16_MEMBER(igs017_state::spriteram_lsb_r)
166	190	{
167		igs017_state *state = space->machine().driver_data<igs017_state>();
168		return state->m_spriteram[offset];
	191	return m_spriteram[offset];
169	192	}
170		static WRITE16_HANDLER( spriteram_lsb_w )
	193	WRITE16_MEMBER(igs017_state::spriteram_lsb_w)
171	194	{
172		igs017_state *state = space->machine().driver_data<igs017_state>();
173	195	if (ACCESSING_BITS_0_7)
174		state->m_spriteram[offset] = data;
	196	m_spriteram[offset] = data;
175	197	}
176	198
177	199
r14845	r14846
1099	1121	AM_RANGE( 0x10000, 0x3ffff ) AM_ROM
1100	1122	ADDRESS_MAP_END
1101	1123
1102		static WRITE8_HANDLER( nmi_enable_w )
	1124	WRITE8_MEMBER(igs017_state::nmi_enable_w)
1103	1125	{
1104		igs017_state *state = space->machine().driver_data<igs017_state>();
1105		state->m_nmi_enable = data & 1;
	1126	m_nmi_enable = data & 1;
1106	1127	if (data & (~1))
1107		logerror("PC %06X: nmi_enable = %02x\n",cpu_get_pc(&space->device()),data);
	1128	logerror("PC %06X: nmi_enable = %02x\n",cpu_get_pc(&space.device()),data);
1108	1129	}
1109	1130
1110		static WRITE8_HANDLER( irq_enable_w )
	1131	WRITE8_MEMBER(igs017_state::irq_enable_w)
1111	1132	{
1112		igs017_state *state = space->machine().driver_data<igs017_state>();
1113		state->m_irq_enable = data & 1;
	1133	m_irq_enable = data & 1;
1114	1134	if (data & (~1))
1115		logerror("PC %06X: irq_enable = %02x\n",cpu_get_pc(&space->device()),data);
	1135	logerror("PC %06X: irq_enable = %02x\n",cpu_get_pc(&space.device()),data);
1116	1136	}
1117	1137
1118		static WRITE8_HANDLER( input_select_w )
	1138	WRITE8_MEMBER(igs017_state::input_select_w)
1119	1139	{
1120		igs017_state *state = space->machine().driver_data<igs017_state>();
1121		state->m_input_select = data;
	1140	m_input_select = data;
1122	1141	}
1123	1142
1124		static READ8_HANDLER( input_r )
	1143	READ8_MEMBER(igs017_state::input_r)
1125	1144	{
1126		igs017_state *state = space->machine().driver_data<igs017_state>();
1127		switch (state->m_input_select)
	1145	switch (m_input_select)
1128	1146	{
1129		case 0x00:   return input_port_read(space->machine(), "PLAYER1");
1130		case 0x01:   return input_port_read(space->machine(), "PLAYER2");
1131		case 0x02:   return input_port_read(space->machine(), "COINS");
	1147	case 0x00:   return input_port_read(machine(), "PLAYER1");
	1148	case 0x01:   return input_port_read(machine(), "PLAYER2");
	1149	case 0x02:   return input_port_read(machine(), "COINS");
1132	1150
1133	1151	case 0x03:   return 01;
1134	1152
r14845	r14846
1155	1173	case 0x34:   return 0x32;
1156	1174
1157	1175	default:
1158		logerror("PC %06X: input %02x read\n",cpu_get_pc(&space->device()),state->m_input_select);
	1176	logerror("PC %06X: input %02x read\n",cpu_get_pc(&space.device()),m_input_select);
1159	1177	return 0xff;
1160	1178	}
1161	1179	}
r14845	r14846
1170	1188	//  AM_RANGE(0x200a, 0x200a) AM_WRITENOP
1171	1189
1172	1190	AM_RANGE( 0x2010, 0x2013 ) AM_DEVREAD_LEGACY("ppi8255", ppi8255_r)
1173		AM_RANGE( 0x2012, 0x2012 ) AM_WRITE_LEGACY(video_disable_w )
	1191	AM_RANGE( 0x2012, 0x2012 ) AM_WRITE(video_disable_w )
1174	1192
1175		AM_RANGE( 0x2014, 0x2014 ) AM_WRITE_LEGACY(nmi_enable_w )
1176		AM_RANGE( 0x2015, 0x2015 ) AM_WRITE_LEGACY(irq_enable_w )
	1193	AM_RANGE( 0x2014, 0x2014 ) AM_WRITE(nmi_enable_w )
	1194	AM_RANGE( 0x2015, 0x2015 ) AM_WRITE(irq_enable_w )
1177	1195
1178		AM_RANGE( 0x4000, 0x5fff ) AM_RAM_WRITE_LEGACY(fg_w ) AM_BASE(m_fg_videoram )
1179		AM_RANGE( 0x6000, 0x7fff ) AM_RAM_WRITE_LEGACY(bg_w ) AM_BASE(m_bg_videoram )
	1196	AM_RANGE( 0x4000, 0x5fff ) AM_RAM_WRITE(fg_w ) AM_BASE(m_fg_videoram )
	1197	AM_RANGE( 0x6000, 0x7fff ) AM_RAM_WRITE(bg_w ) AM_BASE(m_bg_videoram )
1180	1198
1181		AM_RANGE( 0x8000, 0x8000 ) AM_WRITE_LEGACY(input_select_w )
1182		AM_RANGE( 0x8001, 0x8001 ) AM_READ_LEGACY(input_r )
	1199	AM_RANGE( 0x8000, 0x8000 ) AM_WRITE(input_select_w )
	1200	AM_RANGE( 0x8001, 0x8001 ) AM_READ(input_r )
1183	1201
1184	1202	AM_RANGE( 0x9000, 0x9000 ) AM_DEVREADWRITE("oki", okim6295_device, read, write)
1185	1203
r14845	r14846
1192	1210	// mgcs
1193	1211
1194	1212
1195		static WRITE16_HANDLER( mgcs_magic_w )
	1213	WRITE16_MEMBER(igs017_state::mgcs_magic_w)
1196	1214	{
1197		igs017_state *state = space->machine().driver_data<igs017_state>();
1198		COMBINE_DATA(&state->m_igs_magic[offset]);
	1215	COMBINE_DATA(&m_igs_magic[offset]);
1199	1216
1200	1217	if (offset == 0)
1201	1218	return;
1202	1219
1203		switch(state->m_igs_magic[0])
	1220	switch(m_igs_magic[0])
1204	1221	{
1205	1222	case 0x00:
1206	1223	if (ACCESSING_BITS_0_7)
1207	1224	{
1208		state->m_input_select = data & 0xff;
	1225	m_input_select = data & 0xff;
1209	1226	}
1210	1227
1211		if ( state->m_input_select & ~0xf8 )
1212		logerror("%06x: warning, unknown bits written in input_select = %02x\n", cpu_get_pc(&space->device()), state->m_input_select);
	1228	if ( m_input_select & ~0xf8 )
	1229	logerror("%06x: warning, unknown bits written in input_select = %02x\n", cpu_get_pc(&space.device()), m_input_select);
1213	1230	break;
1214	1231
1215	1232	case 0x01:
1216	1233	if (ACCESSING_BITS_0_7)
1217	1234	{
1218		state->m_scramble_data = data & 0xff;
	1235	m_scramble_data = data & 0xff;
1219	1236	}
1220	1237	break;
1221	1238
r14845	r14846
1223	1240	// case 0x03: ?
1224	1241
1225	1242	default:
1226		logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[0], data);
	1243	logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[0], data);
1227	1244	}
1228	1245	}
1229	1246
1230		static READ16_HANDLER( mgcs_magic_r )
	1247	READ16_MEMBER(igs017_state::mgcs_magic_r)
1231	1248	{
1232		igs017_state *state = space->machine().driver_data<igs017_state>();
1233		switch(state->m_igs_magic[0])
	1249	switch(m_igs_magic[0])
1234	1250	{
1235	1251	case 0x01:
1236		return BITSWAP8(state->m_scramble_data, 4,5,6,7, 0,1,2,3);
	1252	return BITSWAP8(m_scramble_data, 4,5,6,7, 0,1,2,3);
1237	1253
1238	1254	default:
1239		logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[0]);
	1255	logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[0]);
1240	1256	break;
1241	1257	}
1242	1258
r14845	r14846
1256	1272	return 0xff;
1257	1273	}
1258	1274
1259		static WRITE16_HANDLER( irq1_enable_w )
	1275	WRITE16_MEMBER(igs017_state::irq1_enable_w)
1260	1276	{
1261		igs017_state *state = space->machine().driver_data<igs017_state>();
1262	1277	if (ACCESSING_BITS_0_7)
1263		state->m_irq1_enable = data & 1;
	1278	m_irq1_enable = data & 1;
1264	1279
1265	1280	if (data != 0 && data != 0xff)
1266		logerror("PC %06X: irq1_enable = %04x\n",cpu_get_pc(&space->device()),data);
	1281	logerror("PC %06X: irq1_enable = %04x\n",cpu_get_pc(&space.device()),data);
1267	1282	}
1268	1283
1269		static WRITE16_HANDLER( irq2_enable_w )
	1284	WRITE16_MEMBER(igs017_state::irq2_enable_w)
1270	1285	{
1271		igs017_state *state = space->machine().driver_data<igs017_state>();
1272	1286	if (ACCESSING_BITS_0_7)
1273		state->m_irq2_enable = data & 1;
	1287	m_irq2_enable = data & 1;
1274	1288
1275	1289	if (data != 0 && data != 0xff)
1276		logerror("PC %06X: irq2_enable = %04x\n",cpu_get_pc(&space->device()),data);
	1290	logerror("PC %06X: irq2_enable = %04x\n",cpu_get_pc(&space.device()),data);
1277	1291	}
1278	1292
1279		static WRITE16_HANDLER( mgcs_paletteram_w )
	1293	WRITE16_MEMBER(igs017_state::mgcs_paletteram_w)
1280	1294	{
1281		COMBINE_DATA(&space->machine().generic.paletteram.u16[offset]);
	1295	COMBINE_DATA(&machine().generic.paletteram.u16[offset]);
1282	1296
1283		int bgr = ((space->machine().generic.paletteram.u16[offset/2*2+0] & 0xff) << 8) | (space->machine().generic.paletteram.u16[offset/2*2+1] & 0xff);
	1297	int bgr = ((machine().generic.paletteram.u16[offset/2*2+0] & 0xff) << 8) | (machine().generic.paletteram.u16[offset/2*2+1] & 0xff);
1284	1298
1285	1299	// bitswap
1286	1300	bgr = BITSWAP16(bgr, 7,8,9,2,14,3,13,15,12,11,10,0,1,4,5,6);
1287	1301
1288		palette_set_color_rgb(space->machine(), offset/2, pal5bit(bgr >> 0), pal5bit(bgr >> 5), pal5bit(bgr >> 10));
	1302	palette_set_color_rgb(machine(), offset/2, pal5bit(bgr >> 0), pal5bit(bgr >> 5), pal5bit(bgr >> 10));
1289	1303	}
1290	1304
1291	1305	static ADDRESS_MAP_START( mgcs, AS_PROGRAM, 16, igs017_state )
1292	1306	AM_RANGE( 0x000000, 0x07ffff ) AM_ROM
1293	1307	AM_RANGE( 0x300000, 0x303fff ) AM_RAM
1294		AM_RANGE( 0x49c000, 0x49c003 ) AM_WRITE_LEGACY(mgcs_magic_w )
1295		AM_RANGE( 0x49c002, 0x49c003 ) AM_READ_LEGACY(mgcs_magic_r )
1296		AM_RANGE( 0xa02000, 0xa02fff ) AM_READWRITE_LEGACY(spriteram_lsb_r, spriteram_lsb_w ) AM_BASE(m_spriteram)
1297		AM_RANGE( 0xa03000, 0xa037ff ) AM_RAM_WRITE_LEGACY(mgcs_paletteram_w ) AM_BASE_GENERIC( paletteram )
	1308	AM_RANGE( 0x49c000, 0x49c003 ) AM_WRITE(mgcs_magic_w )
	1309	AM_RANGE( 0x49c002, 0x49c003 ) AM_READ(mgcs_magic_r )
	1310	AM_RANGE( 0xa02000, 0xa02fff ) AM_READWRITE(spriteram_lsb_r, spriteram_lsb_w ) AM_BASE(m_spriteram)
	1311	AM_RANGE( 0xa03000, 0xa037ff ) AM_RAM_WRITE(mgcs_paletteram_w ) AM_BASE_GENERIC( paletteram )
1298	1312	AM_RANGE( 0xa04020, 0xa04027 ) AM_DEVREAD8_LEGACY("ppi8255", ppi8255_r, 0x00ff )
1299		AM_RANGE( 0xa04024, 0xa04025 ) AM_WRITE_LEGACY(video_disable_lsb_w )
1300		AM_RANGE( 0xa04028, 0xa04029 ) AM_WRITE_LEGACY(irq2_enable_w )
1301		AM_RANGE( 0xa0402a, 0xa0402b ) AM_WRITE_LEGACY(irq1_enable_w )
1302		AM_RANGE( 0xa08000, 0xa0bfff ) AM_READWRITE_LEGACY(fg_lsb_r, fg_lsb_w ) AM_BASE(m_fg_videoram )
1303		AM_RANGE( 0xa0c000, 0xa0ffff ) AM_READWRITE_LEGACY(bg_lsb_r, bg_lsb_w ) AM_BASE(m_bg_videoram )
	1313	AM_RANGE( 0xa04024, 0xa04025 ) AM_WRITE(video_disable_lsb_w )
	1314	AM_RANGE( 0xa04028, 0xa04029 ) AM_WRITE(irq2_enable_w )
	1315	AM_RANGE( 0xa0402a, 0xa0402b ) AM_WRITE(irq1_enable_w )
	1316	AM_RANGE( 0xa08000, 0xa0bfff ) AM_READWRITE(fg_lsb_r, fg_lsb_w ) AM_BASE(m_fg_videoram )
	1317	AM_RANGE( 0xa0c000, 0xa0ffff ) AM_READWRITE(bg_lsb_r, bg_lsb_w ) AM_BASE(m_bg_videoram )
1304	1318	AM_RANGE( 0xa12000, 0xa12001 ) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff )
1305	1319	// oki banking through protection (code at $1a350)?
1306	1320	ADDRESS_MAP_END
r14845	r14846
1308	1322
1309	1323	// sdmg2
1310	1324
1311		static WRITE16_HANDLER( sdmg2_paletteram_w )
	1325	WRITE16_MEMBER(igs017_state::sdmg2_paletteram_w)
1312	1326	{
1313		COMBINE_DATA(&space->machine().generic.paletteram.u16[offset]);
	1327	COMBINE_DATA(&machine().generic.paletteram.u16[offset]);
1314	1328
1315		int bgr = ((space->machine().generic.paletteram.u16[offset/2*2+1] & 0xff) << 8) | (space->machine().generic.paletteram.u16[offset/2*2+0] & 0xff);
	1329	int bgr = ((machine().generic.paletteram.u16[offset/2*2+1] & 0xff) << 8) | (machine().generic.paletteram.u16[offset/2*2+0] & 0xff);
1316	1330
1317		palette_set_color_rgb(space->machine(), offset/2, pal5bit(bgr >> 0), pal5bit(bgr >> 5), pal5bit(bgr >> 10));
	1331	palette_set_color_rgb(machine(), offset/2, pal5bit(bgr >> 0), pal5bit(bgr >> 5), pal5bit(bgr >> 10));
1318	1332	}
1319	1333
1320		static READ8_HANDLER( sdmg2_keys_r )
	1334	READ8_MEMBER(igs017_state::sdmg2_keys_r)
1321	1335	{
1322		igs017_state *state = space->machine().driver_data<igs017_state>();
1323		if (~state->m_input_select & 0x01)   return input_port_read(space->machine(), "KEY0");
1324		if (~state->m_input_select & 0x02)   return input_port_read(space->machine(), "KEY1");
1325		if (~state->m_input_select & 0x04)   return input_port_read(space->machine(), "KEY2");
1326		if (~state->m_input_select & 0x08)   return input_port_read(space->machine(), "KEY3");
1327		if (~state->m_input_select & 0x10)   return input_port_read(space->machine(), "KEY4");
	1336	if (~m_input_select & 0x01)   return input_port_read(machine(), "KEY0");
	1337	if (~m_input_select & 0x02)   return input_port_read(machine(), "KEY1");
	1338	if (~m_input_select & 0x04)   return input_port_read(machine(), "KEY2");
	1339	if (~m_input_select & 0x08)   return input_port_read(machine(), "KEY3");
	1340	if (~m_input_select & 0x10)   return input_port_read(machine(), "KEY4");
1328	1341
1329		if (state->m_input_select == 0x1f)   return input_port_read(space->machine(), "KEY0");   // in joystick mode
	1342	if (m_input_select == 0x1f)   return input_port_read(machine(), "KEY0");   // in joystick mode
1330	1343
1331		logerror("%s: warning, reading key with input_select = %02x\n", space->machine().describe_context(), state->m_input_select);
	1344	logerror("%s: warning, reading key with input_select = %02x\n", machine().describe_context(), m_input_select);
1332	1345	return 0xff;
1333	1346	}
1334	1347
1335		static WRITE16_HANDLER( sdmg2_magic_w )
	1348	WRITE16_MEMBER(igs017_state::sdmg2_magic_w)
1336	1349	{
1337		igs017_state *state = space->machine().driver_data<igs017_state>();
1338		COMBINE_DATA(&state->m_igs_magic[offset]);
	1350	COMBINE_DATA(&m_igs_magic[offset]);
1339	1351
1340	1352	if (offset == 0)
1341	1353	return;
1342	1354
1343		switch(state->m_igs_magic[0])
	1355	switch(m_igs_magic[0])
1344	1356	{
1345	1357	// case 0x00: ? 0x80
1346	1358
1347	1359	case 0x01:
1348	1360	if (ACCESSING_BITS_0_7)
1349	1361	{
1350		state->m_input_select   =   data & 0x1f;
1351		coin_counter_w(space->machine(), 0,   data & 0x20);
	1362	m_input_select   =   data & 0x1f;
	1363	coin_counter_w(machine(), 0,   data & 0x20);
1352	1364	//  coin out        data & 0x40
1353		state->m_hopper         =   data & 0x80;
	1365	m_hopper         =   data & 0x80;
1354	1366	}
1355	1367	break;
1356	1368
1357	1369	case 0x02:
1358	1370	if (ACCESSING_BITS_0_7)
1359	1371	{
1360		okim6295_device *oki = space->machine().device<okim6295_device>("oki");
	1372	okim6295_device *oki = machine().device<okim6295_device>("oki");
1361	1373	oki->set_bank_base((data & 0x80) ? 0x40000 : 0);
1362	1374	}
1363	1375	break;
1364	1376
1365	1377	default:
1366		logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[0], data);
	1378	logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[0], data);
1367	1379	}
1368	1380	}
1369	1381
1370		static READ16_HANDLER( sdmg2_magic_r )
	1382	READ16_MEMBER(igs017_state::sdmg2_magic_r)
1371	1383	{
1372		igs017_state *state = space->machine().driver_data<igs017_state>();
1373		switch(state->m_igs_magic[0])
	1384	switch(m_igs_magic[0])
1374	1385	{
1375	1386	case 0x00:
1376	1387	{
1377		UINT16 hopper_bit = (state->m_hopper && ((space->machine().primary_screen->frame_number()/10)&1)) ? 0x0000 : 0x0001;
1378		return input_port_read(space->machine(), "COINS") | hopper_bit;
	1388	UINT16 hopper_bit = (m_hopper && ((machine().primary_screen->frame_number()/10)&1)) ? 0x0000 : 0x0001;
	1389	return input_port_read(machine(), "COINS") | hopper_bit;
1379	1390	}
1380	1391
1381	1392	case 0x02:
1382	1393	return sdmg2_keys_r(space, 0);
1383	1394
1384	1395	default:
1385		logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[0]);
	1396	logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[0]);
1386	1397	break;
1387	1398	}
1388	1399
r14845	r14846
1392	1403	static ADDRESS_MAP_START( sdmg2, AS_PROGRAM, 16, igs017_state )
1393	1404	AM_RANGE(0x000000, 0x07ffff) AM_ROM
1394	1405	AM_RANGE(0x1f0000, 0x1fffff) AM_RAM
1395		AM_RANGE(0x202000, 0x202fff) AM_READWRITE_LEGACY(spriteram_lsb_r, spriteram_lsb_w ) AM_BASE(m_spriteram)
1396		AM_RANGE(0x203000, 0x2037ff) AM_RAM_WRITE_LEGACY(sdmg2_paletteram_w ) AM_BASE_GENERIC( paletteram )
	1406	AM_RANGE(0x202000, 0x202fff) AM_READWRITE(spriteram_lsb_r, spriteram_lsb_w ) AM_BASE(m_spriteram)
	1407	AM_RANGE(0x203000, 0x2037ff) AM_RAM_WRITE(sdmg2_paletteram_w ) AM_BASE_GENERIC( paletteram )
1397	1408	AM_RANGE(0x204020, 0x204027) AM_DEVREAD8_LEGACY("ppi8255", ppi8255_r, 0x00ff )
1398		AM_RANGE(0x204024, 0x204025) AM_WRITE_LEGACY(video_disable_lsb_w )
1399		AM_RANGE(0x204028, 0x204029) AM_WRITE_LEGACY(irq2_enable_w )
1400		AM_RANGE(0x20402a, 0x20402b) AM_WRITE_LEGACY(irq1_enable_w )
1401		AM_RANGE(0x208000, 0x20bfff) AM_READWRITE_LEGACY(fg_lsb_r, fg_lsb_w ) AM_BASE(m_fg_videoram )
1402		AM_RANGE(0x20c000, 0x20ffff) AM_READWRITE_LEGACY(bg_lsb_r, bg_lsb_w ) AM_BASE(m_bg_videoram )
	1409	AM_RANGE(0x204024, 0x204025) AM_WRITE(video_disable_lsb_w )
	1410	AM_RANGE(0x204028, 0x204029) AM_WRITE(irq2_enable_w )
	1411	AM_RANGE(0x20402a, 0x20402b) AM_WRITE(irq1_enable_w )
	1412	AM_RANGE(0x208000, 0x20bfff) AM_READWRITE(fg_lsb_r, fg_lsb_w ) AM_BASE(m_fg_videoram )
	1413	AM_RANGE(0x20c000, 0x20ffff) AM_READWRITE(bg_lsb_r, bg_lsb_w ) AM_BASE(m_bg_videoram )
1403	1414	AM_RANGE(0x210000, 0x210001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff )
1404		AM_RANGE(0x300000, 0x300003) AM_WRITE_LEGACY(sdmg2_magic_w )
1405		AM_RANGE(0x300002, 0x300003) AM_READ_LEGACY(sdmg2_magic_r )
	1415	AM_RANGE(0x300000, 0x300003) AM_WRITE(sdmg2_magic_w )
	1416	AM_RANGE(0x300002, 0x300003) AM_READ(sdmg2_magic_r )
1406	1417	ADDRESS_MAP_END
1407	1418
1408	1419
1409	1420	// mgdh, mgdha
1410	1421
1411		static READ8_HANDLER( mgdh_keys_r )
	1422	READ8_MEMBER(igs017_state::mgdh_keys_r)
1412	1423	{
1413		igs017_state *state = space->machine().driver_data<igs017_state>();
1414		if (~state->m_input_select & 0x04)   return input_port_read(space->machine(), "KEY0");
1415		if (~state->m_input_select & 0x08)   return input_port_read(space->machine(), "KEY1");
1416		if (~state->m_input_select & 0x10)   return input_port_read(space->machine(), "KEY2");
1417		if (~state->m_input_select & 0x20)   return input_port_read(space->machine(), "KEY3");
1418		if (~state->m_input_select & 0x40)   return input_port_read(space->machine(), "KEY4");
	1424	if (~m_input_select & 0x04)   return input_port_read(machine(), "KEY0");
	1425	if (~m_input_select & 0x08)   return input_port_read(machine(), "KEY1");
	1426	if (~m_input_select & 0x10)   return input_port_read(machine(), "KEY2");
	1427	if (~m_input_select & 0x20)   return input_port_read(machine(), "KEY3");
	1428	if (~m_input_select & 0x40)   return input_port_read(machine(), "KEY4");
1419	1429
1420		if ((state->m_input_select & 0xfc) == 0xfc)   return input_port_read(space->machine(), "DSW1");
	1430	if ((m_input_select & 0xfc) == 0xfc)   return input_port_read(machine(), "DSW1");
1421	1431
1422		logerror("%s: warning, reading key with input_select = %02x\n", space->machine().describe_context(), state->m_input_select);
	1432	logerror("%s: warning, reading key with input_select = %02x\n", machine().describe_context(), m_input_select);
1423	1433	return 0xff;
1424	1434	}
1425	1435
1426		static WRITE16_HANDLER( mgdha_magic_w )
	1436	WRITE16_MEMBER(igs017_state::mgdha_magic_w)
1427	1437	{
1428		igs017_state *state = space->machine().driver_data<igs017_state>();
1429		COMBINE_DATA(&state->m_igs_magic[offset]);
	1438	COMBINE_DATA(&m_igs_magic[offset]);
1430	1439
1431	1440	if (offset == 0)
1432	1441	return;
1433	1442
1434		switch(state->m_igs_magic[0])
	1443	switch(m_igs_magic[0])
1435	1444	{
1436	1445	case 0x00:
1437	1446	if (ACCESSING_BITS_0_7)
1438	1447	{
1439	1448	//  coin out     data & 0x40
1440		coin_counter_w(space->machine(), 0, data & 0x80);
	1449	coin_counter_w(machine(), 0, data & 0x80);
1441	1450	}
1442	1451
1443	1452	if ( data & ~0xc0 )
1444		logerror("%06x: warning, unknown bits written to igs_magic 00 = %02x\n", cpu_get_pc(&space->device()), data);
	1453	logerror("%06x: warning, unknown bits written to igs_magic 00 = %02x\n", cpu_get_pc(&space.device()), data);
1445	1454
1446	1455	break;
1447	1456
1448	1457	case 0x01:
1449	1458	if (ACCESSING_BITS_0_7)
1450	1459	{
1451		state->m_input_select = data & 0xff;
1452		state->m_hopper = data & 0x01;
	1460	m_input_select = data & 0xff;
	1461	m_hopper = data & 0x01;
1453	1462	}
1454	1463
1455		if ( state->m_input_select & ~0xfd )
1456		logerror("%06x: warning, unknown bits written in input_select = %02x\n", cpu_get_pc(&space->device()), state->m_input_select);
	1464	if ( m_input_select & ~0xfd )
	1465	logerror("%06x: warning, unknown bits written in input_select = %02x\n", cpu_get_pc(&space.device()), m_input_select);
1457	1466
1458	1467	break;
1459	1468
r14845	r14846
1461	1470	if (ACCESSING_BITS_0_7)
1462	1471	{
1463	1472	// bit 7?
1464		okim6295_device *oki = space->machine().device<okim6295_device>("oki");
	1473	okim6295_device *oki = machine().device<okim6295_device>("oki");
1465	1474	oki->set_bank_base((data & 0x40) ? 0x40000 : 0);
1466	1475	}
1467	1476	break;
r14845	r14846
1478	1487	04ac10: warning, writing to igs_magic 06 = ff
1479	1488	04ac20: warning, writing to igs_magic 07 = 3f
1480	1489	*/
1481		logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[0], data);
	1490	logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[0], data);
1482	1491	}
1483	1492	}
1484	1493
1485		static READ16_HANDLER( mgdha_magic_r )
	1494	READ16_MEMBER(igs017_state::mgdha_magic_r)
1486	1495	{
1487		igs017_state *state = space->machine().driver_data<igs017_state>();
1488		switch(state->m_igs_magic[0])
	1496	switch(m_igs_magic[0])
1489	1497	{
1490	1498	case 0x00:
1491	1499	return mgdh_keys_r(space, 0);
1492	1500
1493	1501	case 0x01:
1494		return input_port_read(space->machine(), "BUTTONS");
	1502	return input_port_read(machine(), "BUTTONS");
1495	1503
1496	1504	case 0x02:
1497		return BITSWAP8(input_port_read(space->machine(), "DSW2"), 0,1,2,3,4,5,6,7);
	1505	return BITSWAP8(input_port_read(machine(), "DSW2"), 0,1,2,3,4,5,6,7);
1498	1506
1499	1507	case 0x03:
1500	1508	{
1501		UINT16 hopper_bit = (state->m_hopper && ((space->machine().primary_screen->frame_number()/10)&1)) ? 0x0000 : 0x0001;
1502		return input_port_read(space->machine(), "COINS") | hopper_bit;
	1509	UINT16 hopper_bit = (m_hopper && ((machine().primary_screen->frame_number()/10)&1)) ? 0x0000 : 0x0001;
	1510	return input_port_read(machine(), "COINS") | hopper_bit;
1503	1511	}
1504	1512
1505	1513	default:
1506		logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[0]);
	1514	logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[0]);
1507	1515	break;
1508	1516	}
1509	1517
r14845	r14846
1513	1521	static ADDRESS_MAP_START( mgdha_map, AS_PROGRAM, 16, igs017_state )
1514	1522	AM_RANGE(0x000000, 0x07ffff) AM_ROM
1515	1523	AM_RANGE(0x600000, 0x603fff) AM_RAM
1516		AM_RANGE(0x876000, 0x876003) AM_WRITE_LEGACY(mgdha_magic_w )
1517		AM_RANGE(0x876002, 0x876003) AM_READ_LEGACY(mgdha_magic_r )
1518		AM_RANGE(0xa02000, 0xa02fff) AM_READWRITE_LEGACY(spriteram_lsb_r, spriteram_lsb_w ) AM_BASE(m_spriteram)
1519		AM_RANGE(0xa03000, 0xa037ff) AM_RAM_WRITE_LEGACY(sdmg2_paletteram_w ) AM_BASE_GENERIC( paletteram )
	1524	AM_RANGE(0x876000, 0x876003) AM_WRITE(mgdha_magic_w )
	1525	AM_RANGE(0x876002, 0x876003) AM_READ(mgdha_magic_r )
	1526	AM_RANGE(0xa02000, 0xa02fff) AM_READWRITE(spriteram_lsb_r, spriteram_lsb_w ) AM_BASE(m_spriteram)
	1527	AM_RANGE(0xa03000, 0xa037ff) AM_RAM_WRITE(sdmg2_paletteram_w ) AM_BASE_GENERIC( paletteram )
1520	1528	//  AM_RANGE(0xa04014, 0xa04015) // written with FF at boot
1521	1529	AM_RANGE(0xa04020, 0xa04027) AM_DEVREAD8_LEGACY("ppi8255", ppi8255_r, 0x00ff )
1522		AM_RANGE(0xa04024, 0xa04025) AM_WRITE_LEGACY(video_disable_lsb_w )
1523		AM_RANGE(0xa04028, 0xa04029) AM_WRITE_LEGACY(irq2_enable_w )
1524		AM_RANGE(0xa0402a, 0xa0402b) AM_WRITE_LEGACY(irq1_enable_w )
1525		AM_RANGE(0xa08000, 0xa0bfff) AM_READWRITE_LEGACY(fg_lsb_r, fg_lsb_w ) AM_BASE(m_fg_videoram )
1526		AM_RANGE(0xa0c000, 0xa0ffff) AM_READWRITE_LEGACY(bg_lsb_r, bg_lsb_w ) AM_BASE(m_bg_videoram )
	1530	AM_RANGE(0xa04024, 0xa04025) AM_WRITE(video_disable_lsb_w )
	1531	AM_RANGE(0xa04028, 0xa04029) AM_WRITE(irq2_enable_w )
	1532	AM_RANGE(0xa0402a, 0xa0402b) AM_WRITE(irq1_enable_w )
	1533	AM_RANGE(0xa08000, 0xa0bfff) AM_READWRITE(fg_lsb_r, fg_lsb_w ) AM_BASE(m_fg_videoram )
	1534	AM_RANGE(0xa0c000, 0xa0ffff) AM_READWRITE(bg_lsb_r, bg_lsb_w ) AM_BASE(m_bg_videoram )
1527	1535	AM_RANGE(0xa10000, 0xa10001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff )
1528	1536	ADDRESS_MAP_END
1529	1537
1530	1538
1531	1539	// tjsb
1532	1540
1533		static WRITE8_HANDLER( tjsb_paletteram_w )
	1541	WRITE8_MEMBER(igs017_state::tjsb_paletteram_w)
1534	1542	{
1535		space->machine().generic.paletteram.u8[offset] = data;
1536		int bgr = (space->machine().generic.paletteram.u8[offset/2*2+1] << 8) | space->machine().generic.paletteram.u8[offset/2*2+0];
	1543	machine().generic.paletteram.u8[offset] = data;
	1544	int bgr = (machine().generic.paletteram.u8[offset/2*2+1] << 8) | machine().generic.paletteram.u8[offset/2*2+0];
1537	1545
1538	1546	// bitswap
1539	1547	bgr = BITSWAP16(bgr, 15, 12,3,6,10,5, 4,2,9,13,8, 7,11,1,0,14);
1540	1548
1541		palette_set_color_rgb(space->machine(), offset/2, pal5bit(bgr >> 0), pal5bit(bgr >> 5), pal5bit(bgr >> 10));
	1549	palette_set_color_rgb(machine(), offset/2, pal5bit(bgr >> 0), pal5bit(bgr >> 5), pal5bit(bgr >> 10));
1542	1550	}
1543	1551
1544		static WRITE8_HANDLER( tjsb_output_w )
	1552	WRITE8_MEMBER(igs017_state::tjsb_output_w)
1545	1553	{
1546		igs017_state *state = space->machine().driver_data<igs017_state>();
1547		switch(state->m_input_select)
	1554	switch(m_input_select)
1548	1555	{
1549	1556	case 0x00:
1550		coin_counter_w(space->machine(), 0,   data & 0x80);   // coin in
	1557	coin_counter_w(machine(), 0,   data & 0x80);   // coin in
1551	1558	if (!(data & ~0x80))
1552	1559	return;
1553	1560	break;
1554	1561
1555	1562	case 0x01:
1556		coin_counter_w(space->machine(), 1,   data & 0x01);   // coin out
	1563	coin_counter_w(machine(), 1,   data & 0x01);   // coin out
1557	1564	if (!(data & ~0x01))
1558	1565	return;
1559	1566	break;
1560	1567
1561	1568	case 0x02:
1562		space->machine().device<okim6295_device>("oki")->set_bank_base((data & 0x10) ? 0x40000 : 0);   // oki bank (0x20/0x30)
	1569	machine().device<okim6295_device>("oki")->set_bank_base((data & 0x10) ? 0x40000 : 0);   // oki bank (0x20/0x30)
1563	1570	if (!(data & ~0x30))
1564	1571	return;
1565	1572	break;
1566	1573
1567	1574	case 0x03:
1568		state->m_hopper = data & 0x40;
	1575	m_hopper = data & 0x40;
1569	1576	if (!(data & ~0x40))
1570	1577	return;
1571	1578	break;
1572	1579	}
1573		logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space->device()), state->m_input_select, data);
	1580	logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space.device()), m_input_select, data);
1574	1581	}
1575	1582
1576		static READ8_HANDLER( tjsb_input_r )
	1583	READ8_MEMBER(igs017_state::tjsb_input_r)
1577	1584	{
1578		igs017_state *state = space->machine().driver_data<igs017_state>();
1579		switch (state->m_input_select)
	1585	switch (m_input_select)
1580	1586	{
1581		case 0x00:   return input_port_read(space->machine(), "PLAYER1");
1582		case 0x01:   return input_port_read(space->machine(), "PLAYER2");
1583		case 0x02:   return input_port_read(space->machine(), "COINS");
	1587	case 0x00:   return input_port_read(machine(), "PLAYER1");
	1588	case 0x01:   return input_port_read(machine(), "PLAYER2");
	1589	case 0x02:   return input_port_read(machine(), "COINS");
1584	1590	case 0x03:
1585	1591	{
1586		UINT8 hopper_bit = (state->m_hopper && ((space->machine().primary_screen->frame_number()/10)&1)) ? 0x00 : 0x20;
1587		return input_port_read(space->machine(), "HOPPER") | hopper_bit;
	1592	UINT8 hopper_bit = (m_hopper && ((machine().primary_screen->frame_number()/10)&1)) ? 0x00 : 0x20;
	1593	return input_port_read(machine(), "HOPPER") | hopper_bit;
1588	1594	}
1589	1595
1590	1596	default:
1591		logerror("PC %06X: input %02x read\n",cpu_get_pc(&space->device()),state->m_input_select);
	1597	logerror("PC %06X: input %02x read\n",cpu_get_pc(&space.device()),m_input_select);
1592	1598	return 0xff;
1593	1599	}
1594	1600	}
1595	1601
1596	1602	static ADDRESS_MAP_START( tjsb_map, AS_PROGRAM, 8, igs017_state )
1597	1603	AM_RANGE( 0x00000, 0x0dfff ) AM_ROM
1598		AM_RANGE( 0x0e000, 0x0e000 ) AM_WRITE_LEGACY(input_select_w )
1599		AM_RANGE( 0x0e001, 0x0e001 ) AM_READWRITE_LEGACY(tjsb_input_r, tjsb_output_w )
	1604	AM_RANGE( 0x0e000, 0x0e000 ) AM_WRITE(input_select_w )
	1605	AM_RANGE( 0x0e001, 0x0e001 ) AM_READWRITE(tjsb_input_r, tjsb_output_w )
1600	1606	AM_RANGE( 0x0e002, 0x0efff ) AM_RAM
1601	1607	AM_RANGE( 0x0f000, 0x0ffff ) AM_RAM
1602	1608	AM_RANGE( 0x10000, 0x3ffff ) AM_ROM
r14845	r14846
1606	1612	AM_RANGE( 0x0000, 0x003f ) AM_RAM // internal regs
1607	1613
1608	1614	AM_RANGE( 0x1000, 0x17ff ) AM_RAM AM_BASE(m_spriteram)
1609		AM_RANGE( 0x1800, 0x1bff ) AM_RAM_WRITE_LEGACY(tjsb_paletteram_w ) AM_BASE_GENERIC(paletteram)
	1615	AM_RANGE( 0x1800, 0x1bff ) AM_RAM_WRITE(tjsb_paletteram_w ) AM_BASE_GENERIC(paletteram)
1610	1616	AM_RANGE( 0x1c00, 0x1fff ) AM_RAM
1611	1617
1612	1618	//  AM_RANGE(0x200a, 0x200a) AM_WRITENOP
1613	1619
1614	1620	AM_RANGE( 0x2010, 0x2013 ) AM_DEVREAD_LEGACY("ppi8255", ppi8255_r)
1615		AM_RANGE( 0x2012, 0x2012 ) AM_WRITE_LEGACY(video_disable_w )
	1621	AM_RANGE( 0x2012, 0x2012 ) AM_WRITE(video_disable_w )
1616	1622
1617		AM_RANGE( 0x2014, 0x2014 ) AM_WRITE_LEGACY(nmi_enable_w )
1618		AM_RANGE( 0x2015, 0x2015 ) AM_WRITE_LEGACY(irq_enable_w )
	1623	AM_RANGE( 0x2014, 0x2014 ) AM_WRITE(nmi_enable_w )
	1624	AM_RANGE( 0x2015, 0x2015 ) AM_WRITE(irq_enable_w )
1619	1625
1620		AM_RANGE( 0x4000, 0x5fff ) AM_RAM_WRITE_LEGACY(fg_w ) AM_BASE(m_fg_videoram )
1621		AM_RANGE( 0x6000, 0x7fff ) AM_RAM_WRITE_LEGACY(bg_w ) AM_BASE(m_bg_videoram )
	1626	AM_RANGE( 0x4000, 0x5fff ) AM_RAM_WRITE(fg_w ) AM_BASE(m_fg_videoram )
	1627	AM_RANGE( 0x6000, 0x7fff ) AM_RAM_WRITE(bg_w ) AM_BASE(m_bg_videoram )
1622	1628
1623	1629	AM_RANGE( 0x9000, 0x9000 ) AM_DEVREADWRITE("oki", okim6295_device, read, write)
1624	1630

src/mame/drivers/monzagp.c

r14845	r14846
47	47	UINT8 *m_vram;
48	48	int m_screenw;
49	49	int m_bank;
	50	DECLARE_READ8_MEMBER(rng_r);
	51	DECLARE_WRITE8_MEMBER(port_w);
	52	DECLARE_WRITE8_MEMBER(port0_w);
	53	DECLARE_WRITE8_MEMBER(port1_w);
	54	DECLARE_WRITE8_MEMBER(port2_w);
	55	DECLARE_WRITE8_MEMBER(port3_w);
50	56	};
51	57
52	58
r14845	r14846
115	121	AM_RANGE(0x0000, 0x0fff) AM_ROM
116	122	ADDRESS_MAP_END
117	123
118		static READ8_HANDLER(rng_r)
	124	READ8_MEMBER(monzagp_state::rng_r)
119	125	{
120		return space->machine().rand();
	126	return machine().rand();
121	127	}
122	128
123		static WRITE8_HANDLER(port_w)
	129	WRITE8_MEMBER(monzagp_state::port_w)
124	130	{
125		monzagp_state *state = space->machine().driver_data<monzagp_state>();
126		state->m_coordx=offset;//-0xc0;
127		//state->m_vram[state->m_coordy*state->m_screenw+state->m_coordx]=data;
	131	m_coordx=offset;//-0xc0;
	132	//m_vram[m_coordy*m_screenw+m_coordx]=data;
128	133	//if(output==0xfe)
129	134	{
130	135	//  if(data>='A' && data <='Z')
131		//      printf("%.2x %.2x %c %c\n",state->m_coordy, offset,data, znaki[data-'A']);
132		//state->m_vram[state->m_coordy*state->m_screenw+state->m_coordx]=data;
133		state->m_vram[(state->m_coordx*256+state->m_coordy)&0x7ff]=data;
	136	//      printf("%.2x %.2x %c %c\n",m_coordy, offset,data, znaki[data-'A']);
	137	//m_vram[m_coordy*m_screenw+m_coordx]=data;
	138	m_vram[(m_coordx*256+m_coordy)&0x7ff]=data;
134	139	}
135	140	}
136	141	/*
r14845	r14846
172	177
173	178
174	179
175		static WRITE8_HANDLER(port0_w)
	180	WRITE8_MEMBER(monzagp_state::port0_w)
176	181	{
177		//  printf("P0 %x = %x\n",cpu_get_pc(&space->device()),data);
	182	//  printf("P0 %x = %x\n",cpu_get_pc(&space.device()),data);
178	183	}
179	184
180		static WRITE8_HANDLER(port1_w)
	185	WRITE8_MEMBER(monzagp_state::port1_w)
181	186	{
182		//  printf("P1 %x = %x\n",cpu_get_pc(&space->device()),data);
	187	//  printf("P1 %x = %x\n",cpu_get_pc(&space.device()),data);
183	188	}
184	189
185		static WRITE8_HANDLER(port2_w)
	190	WRITE8_MEMBER(monzagp_state::port2_w)
186	191	{
187		monzagp_state *state = space->machine().driver_data<monzagp_state>();
188		//  printf("P2 %x = %x\n",cpu_get_pc(&space->device()),data);
189		state->m_coordy=data;
	192	//  printf("P2 %x = %x\n",cpu_get_pc(&space.device()),data);
	193	m_coordy=data;
190	194	}
191	195
192	196	#if 0
193		static WRITE8_HANDLER(port3_w)
	197	WRITE8_MEMBER(monzagp_state::port3_w)
194	198	{
195	199	output=data;
196	200	}
r14845	r14846
212	216	*/
213	217
214	218	static ADDRESS_MAP_START( monzagp_io, AS_IO, 8, monzagp_state )
215		AM_RANGE(0x00, 0xff) AM_READWRITE_LEGACY(rng_r,port_w)
216		AM_RANGE(0x100, 0x100) AM_WRITE_LEGACY(port0_w)
217		AM_RANGE(0x101, 0x101) AM_WRITE_LEGACY(port1_w)
218		AM_RANGE(0x102, 0x102) AM_WRITE_LEGACY(port2_w)
219		AM_RANGE(0x104, 0x104) AM_READ_LEGACY(rng_r)
	219	AM_RANGE(0x00, 0xff) AM_READWRITE(rng_r,port_w)
	220	AM_RANGE(0x100, 0x100) AM_WRITE(port0_w)
	221	AM_RANGE(0x101, 0x101) AM_WRITE(port1_w)
	222	AM_RANGE(0x102, 0x102) AM_WRITE(port2_w)
	223	AM_RANGE(0x104, 0x104) AM_READ(rng_r)
220	224	ADDRESS_MAP_END
221	225
222	226	static INPUT_PORTS_START( monzagp )

src/mame/drivers/shanghai.c

r14845	r14846
34	34	shanghai_state(const machine_config &mconfig, device_type type, const char *tag)
35	35	: driver_device(mconfig, type, tag) { }
36	36
	37	DECLARE_WRITE16_MEMBER(shanghai_coin_w);
	38	DECLARE_READ16_MEMBER(kothello_hd63484_status_r);
37	39	};
38	40
39	41
r14845	r14846
123	125	device_set_input_line_and_vector(device,0,HOLD_LINE,0x80);
124	126	}
125	127
126		static WRITE16_HANDLER( shanghai_coin_w )
	128	WRITE16_MEMBER(shanghai_state::shanghai_coin_w)
127	129	{
128	130	if (ACCESSING_BITS_0_7)
129	131	{
130		coin_counter_w(space->machine(), 0,data & 1);
131		coin_counter_w(space->machine(), 1,data & 2);
	132	coin_counter_w(machine(), 0,data & 1);
	133	coin_counter_w(machine(), 1,data & 2);
132	134	}
133	135	}
134	136
r14845	r14846
152	154	AM_RANGE(0x40, 0x41) AM_READ_PORT("P1")
153	155	AM_RANGE(0x44, 0x45) AM_READ_PORT("P2")
154	156	AM_RANGE(0x48, 0x49) AM_READ_PORT("SYSTEM")
155		AM_RANGE(0x4c, 0x4d) AM_WRITE_LEGACY(shanghai_coin_w)
	157	AM_RANGE(0x4c, 0x4d) AM_WRITE(shanghai_coin_w)
156	158	ADDRESS_MAP_END
157	159
158	160
r14845	r14846
163	165	AM_RANGE(0x30, 0x31) AM_DEVREADWRITE_LEGACY("hd63484", hd63484_status_r, hd63484_address_w)
164	166	AM_RANGE(0x32, 0x33) AM_DEVREADWRITE_LEGACY("hd63484", hd63484_data_r, hd63484_data_w)
165	167	AM_RANGE(0x40, 0x43) AM_DEVREADWRITE8_LEGACY("ymsnd", ym2203_r, ym2203_w, 0x00ff)
166		AM_RANGE(0x50, 0x51) AM_WRITE_LEGACY(shanghai_coin_w)
	168	AM_RANGE(0x50, 0x51) AM_WRITE(shanghai_coin_w)
167	169	ADDRESS_MAP_END
168	170
169		static READ16_HANDLER( kothello_hd63484_status_r )
	171	READ16_MEMBER(shanghai_state::kothello_hd63484_status_r)
170	172	{
171	173	return 0xff22;   /* write FIFO ready + command end + read FIFO ready */
172	174	}
173	175
174	176	static ADDRESS_MAP_START( kothello_map, AS_PROGRAM, 16, shanghai_state )
175	177	AM_RANGE(0x00000, 0x07fff) AM_RAM
176		AM_RANGE(0x08010, 0x08011) AM_READ_LEGACY(kothello_hd63484_status_r) AM_DEVWRITE_LEGACY("hd63484", hd63484_address_w)
	178	AM_RANGE(0x08010, 0x08011) AM_READ(kothello_hd63484_status_r) AM_DEVWRITE_LEGACY("hd63484", hd63484_address_w)
177	179	AM_RANGE(0x08012, 0x08013) AM_DEVREADWRITE_LEGACY("hd63484", hd63484_data_r, hd63484_data_w)
178	180	AM_RANGE(0x09010, 0x09011) AM_READ_PORT("P1")
179	181	AM_RANGE(0x09012, 0x09013) AM_READ_PORT("P2")

src/mame/drivers/avt.c

r14845	r14846
438	438
439	439	required_device<cpu_device> m_maincpu;
440	440	required_device<mc6845_device> m_crtc;
	441	DECLARE_WRITE8_MEMBER(debug_w);
441	442	};
442	443
443	444	#define mc6845_h_char_total    (state->m_crtc_vreg[0])
r14845	r14846
581	582	*            Read / Write Handlers            *
582	583	**********************************************/
583	584
584		//static WRITE8_HANDLER( debug_w )
	585	//WRITE8_MEMBER(avt_state::debug_w)
585	586	//{
586	587	//  popmessage("written : %02X", data);
587	588	//}

src/mame/drivers/mole.c

r14845	r14846
65	65
66	66	/* memory */
67	67	UINT16       m_tileram[0x400];
	68	DECLARE_WRITE8_MEMBER(mole_videoram_w);
	69	DECLARE_WRITE8_MEMBER(mole_tilebank_w);
	70	DECLARE_WRITE8_MEMBER(mole_flipscreen_w);
	71	DECLARE_READ8_MEMBER(mole_protection_r);
68	72	};
69	73
70	74
r14845	r14846
99	103	state->save_item(NAME(state->m_tileram));
100	104	}
101	105
102		static WRITE8_HANDLER( mole_videoram_w )
	106	WRITE8_MEMBER(mole_state::mole_videoram_w)
103	107	{
104		mole_state *state = space->machine().driver_data<mole_state>();
105	108
106		state->m_tileram[offset] = data | (state->m_tile_bank << 8);
107		state->m_bg_tilemap->mark_tile_dirty(offset);
	109	m_tileram[offset] = data | (m_tile_bank << 8);
	110	m_bg_tilemap->mark_tile_dirty(offset);
108	111	}
109	112
110		static WRITE8_HANDLER( mole_tilebank_w )
	113	WRITE8_MEMBER(mole_state::mole_tilebank_w)
111	114	{
112		mole_state *state = space->machine().driver_data<mole_state>();
113	115
114		state->m_tile_bank = data;
115		state->m_bg_tilemap->mark_all_dirty();
	116	m_tile_bank = data;
	117	m_bg_tilemap->mark_all_dirty();
116	118	}
117	119
118		static WRITE8_HANDLER( mole_flipscreen_w )
	120	WRITE8_MEMBER(mole_state::mole_flipscreen_w)
119	121	{
120		flip_screen_set(space->machine(), data & 0x01);
	122	flip_screen_set(machine(), data & 0x01);
121	123	}
122	124
123	125	static SCREEN_UPDATE_IND16( mole )
r14845	r14846
136	138	*
137	139	*************************************/
138	140
139		static READ8_HANDLER( mole_protection_r )
	141	READ8_MEMBER(mole_state::mole_protection_r)
140	142	{
141
142	143	/*  Following are all known examples of Mole Attack
143	144	**  code reading from the protection circuitry:
144	145	**
r14845	r14846
164	165	{
165	166	case 0x08: return 0xb0; /* random mole placement */
166	167	case 0x26:
167		if (cpu_get_pc(&space->device()) == 0x53d7)
	168	if (cpu_get_pc(&space.device()) == 0x53d7)
168	169	{
169	170	return 0x06; /* bonus round */
170	171	}
r14845	r14846
194	195
195	196	static ADDRESS_MAP_START( mole_map, AS_PROGRAM, 8, mole_state )
196	197	AM_RANGE(0x0000, 0x03ff) AM_RAM
197		AM_RANGE(0x0800, 0x08ff) AM_READ_LEGACY(mole_protection_r)
	198	AM_RANGE(0x0800, 0x08ff) AM_READ(mole_protection_r)
198	199	AM_RANGE(0x0800, 0x0800) AM_WRITENOP // ???
199	200	AM_RANGE(0x0820, 0x0820) AM_WRITENOP // ???
200	201	AM_RANGE(0x5000, 0x7fff) AM_MIRROR(0x8000) AM_ROM
201		AM_RANGE(0x8000, 0x83ff) AM_RAM_WRITE_LEGACY(mole_videoram_w)
202		AM_RANGE(0x8400, 0x8400) AM_WRITE_LEGACY(mole_tilebank_w)
	202	AM_RANGE(0x8000, 0x83ff) AM_RAM_WRITE(mole_videoram_w)
	203	AM_RANGE(0x8400, 0x8400) AM_WRITE(mole_tilebank_w)
203	204	AM_RANGE(0x8c00, 0x8c01) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
204	205	AM_RANGE(0x8c40, 0x8c40) AM_WRITENOP // ???
205	206	AM_RANGE(0x8c80, 0x8c80) AM_WRITENOP // ???
r14845	r14846
207	208	AM_RANGE(0x8d00, 0x8d00) AM_READ_PORT("DSW") AM_WRITE_LEGACY(watchdog_reset_w)
208	209	AM_RANGE(0x8d40, 0x8d40) AM_READ_PORT("IN0")
209	210	AM_RANGE(0x8d80, 0x8d80) AM_READ_PORT("IN1")
210		AM_RANGE(0x8dc0, 0x8dc0) AM_READ_PORT("IN2") AM_WRITE_LEGACY(mole_flipscreen_w)
	211	AM_RANGE(0x8dc0, 0x8dc0) AM_READ_PORT("IN2") AM_WRITE(mole_flipscreen_w)
211	212	ADDRESS_MAP_END
212	213
213	214

src/mame/drivers/sigmab52.c

r14845	r14846
140	140
141	141	int m_latch;
142	142	unsigned int m_acrtc_data;
	143	DECLARE_WRITE8_MEMBER(acrtc_w);
	144	DECLARE_READ8_MEMBER(acrtc_r);
	145	DECLARE_READ8_MEMBER(unk_f700_r);
	146	DECLARE_WRITE8_MEMBER(unk_f710_w);
	147	DECLARE_READ8_MEMBER(unk_f721_r);
143	148	};
144	149
145	150
r14845	r14846
234	239	*      ACRTC Access      *
235	240	*************************/
236	241
237		static WRITE8_HANDLER(acrtc_w)
	242	WRITE8_MEMBER(sigmab52_state::acrtc_w)
238	243	{
239		sigmab52_state *state = space->machine().driver_data<sigmab52_state>();
240		device_t *hd63484 = space->machine().device("hd63484");
	244	device_t *hd63484 = machine().device("hd63484");
241	245	if(!offset)
242	246	{
243	247	//address select
244	248	hd63484_address_w(hd63484, 0, data, 0x00ff);
245		state->m_latch = 0;
	249	m_latch = 0;
246	250	}
247	251	else
248	252	{
249		if(!state->m_latch)
	253	if(!m_latch)
250	254	{
251		state->m_acrtc_data = data;
	255	m_acrtc_data = data;
252	256
253	257	}
254	258
255	259	else
256	260	{
257		state->m_acrtc_data <<= 8;
258		state->m_acrtc_data |= data;
	261	m_acrtc_data <<= 8;
	262	m_acrtc_data |= data;
259	263
260		hd63484_data_w(hd63484, 0, state->m_acrtc_data, 0xffff);
	264	hd63484_data_w(hd63484, 0, m_acrtc_data, 0xffff);
261	265	}
262	266
263		state->m_latch ^= 1;
	267	m_latch ^= 1;
264	268	}
265	269	}
266	270
267		static READ8_HANDLER(acrtc_r)
	271	READ8_MEMBER(sigmab52_state::acrtc_r)
268	272	{
269	273	if(offset&1)
270	274	{
271		device_t *hd63484 = space->machine().device("hd63484");
	275	device_t *hd63484 = machine().device("hd63484");
272	276	return hd63484_data_r(hd63484, 0, 0xff);
273	277	}
274	278
275	279	else
276	280	{
277		return 0x7b; //fake status read (instead HD63484_status_r(space, 0, 0xff); )
	281	return 0x7b; //fake status read (instead HD63484_status_r(&space, 0, 0xff); )
278	282	}
279	283	}
280	284
r14845	r14846
283	287	*      Misc Handlers     *
284	288	*************************/
285	289
286		static READ8_HANDLER(unk_f700_r)
	290	READ8_MEMBER(sigmab52_state::unk_f700_r)
287	291	{
288	292	return 0x7f;
289	293	}
290	294
291		static WRITE8_HANDLER(unk_f710_w)
	295	WRITE8_MEMBER(sigmab52_state::unk_f710_w)
292	296	{
293		memory_set_bankptr(space->machine(), "bank1" ,&space->machine().region("maincpu")->base()[0x10000 + ((data&0x80)?0x4000:0x0000)]);
	297	memory_set_bankptr(machine(), "bank1" ,&machine().region("maincpu")->base()[0x10000 + ((data&0x80)?0x4000:0x0000)]);
294	298	}
295	299
296		static READ8_HANDLER(unk_f721_r)
	300	READ8_MEMBER(sigmab52_state::unk_f721_r)
297	301	{
298	302	return 0x04;   // test is stuck. feeding bit3 the error message appear...
299	303	}
r14845	r14846
309	313
310	314	AM_RANGE(0x8000, 0xf6ff) AM_RAMBANK("bank3")
311	315
312		AM_RANGE(0xf700, 0xf700) AM_READ_LEGACY(unk_f700_r)
313		AM_RANGE(0xf710, 0xf710) AM_WRITE_LEGACY(unk_f710_w)
314		AM_RANGE(0xf721, 0xf721) AM_READ_LEGACY(unk_f721_r)
	316	AM_RANGE(0xf700, 0xf700) AM_READ(unk_f700_r)
	317	AM_RANGE(0xf710, 0xf710) AM_WRITE(unk_f710_w)
	318	AM_RANGE(0xf721, 0xf721) AM_READ(unk_f721_r)
315	319
316	320	//AM_RANGE(0x00, 0x01) AM_DEVREADWRITE_LEGACY("hd63484", hd63484_status_r, hd63484_address_w)
317	321	//AM_RANGE(0x02, 0x03) AM_DEVREADWRITE_LEGACY("hd63484", hd63484_data_r, hd63484_data_w)
318	322
319		AM_RANGE(0xf730, 0xf731) AM_READWRITE_LEGACY(acrtc_r, acrtc_w)
	323	AM_RANGE(0xf730, 0xf731) AM_READWRITE(acrtc_r, acrtc_w)
320	324	AM_RANGE(0xf740, 0xf740) AM_READ_PORT("IN0")
321	325	AM_RANGE(0xf741, 0xf741) AM_READ_PORT("IN1")   // random checks to active high to go further with the test.
322	326	AM_RANGE(0xf742, 0xf742) AM_READ_PORT("IN2")

src/mame/drivers/dynadice.c

r14845	r14846
55	55
56	56	/* misc */
57	57	int      m_ay_data;
	58	DECLARE_WRITE8_MEMBER(dynadice_videoram_w);
	59	DECLARE_WRITE8_MEMBER(sound_data_w);
58	60	};
59	61
60	62
61		static WRITE8_HANDLER( dynadice_videoram_w )
	63	WRITE8_MEMBER(dynadice_state::dynadice_videoram_w)
62	64	{
63		dynadice_state *state = space->machine().driver_data<dynadice_state>();
64		state->m_videoram[offset] = data;
65		state->m_bg_tilemap->mark_tile_dirty(offset);
66		state->m_top_tilemap->mark_all_dirty();
	65	m_videoram[offset] = data;
	66	m_bg_tilemap->mark_tile_dirty(offset);
	67	m_top_tilemap->mark_all_dirty();
67	68	}
68	69
69		static WRITE8_HANDLER( sound_data_w )
	70	WRITE8_MEMBER(dynadice_state::sound_data_w)
70	71	{
71		dynadice_state *state = space->machine().driver_data<dynadice_state>();
72		state->m_ay_data = data;
	72	m_ay_data = data;
73	73	}
74	74
75	75	static WRITE8_DEVICE_HANDLER( sound_control_w )
r14845	r14846
94	94
95	95	static ADDRESS_MAP_START( dynadice_map, AS_PROGRAM, 8, dynadice_state )
96	96	AM_RANGE(0x0000, 0x1fff) AM_ROM
97		AM_RANGE(0x2000, 0x23ff) AM_RAM_WRITE_LEGACY(dynadice_videoram_w) AM_BASE(m_videoram)
	97	AM_RANGE(0x2000, 0x23ff) AM_RAM_WRITE(dynadice_videoram_w) AM_BASE(m_videoram)
98	98	AM_RANGE(0x4000, 0x40ff) AM_RAM AM_SHARE("nvram")
99	99	ADDRESS_MAP_END
100	100
r14845	r14846
116	116	ADDRESS_MAP_GLOBAL_MASK(0xff)
117	117	AM_RANGE(0x00, 0x00) AM_READ_LEGACY(soundlatch_r)
118	118	AM_RANGE(0x01, 0x01) AM_WRITE_LEGACY(soundlatch_clear_w)
119		AM_RANGE(0x02, 0x02) AM_WRITE_LEGACY(sound_data_w)
	119	AM_RANGE(0x02, 0x02) AM_WRITE(sound_data_w)
120	120	AM_RANGE(0x03, 0x03) AM_DEVWRITE_LEGACY("aysnd", sound_control_w)
121	121	ADDRESS_MAP_END
122	122

src/mame/drivers/jangou.c

r14845	r14846
64	64	UINT8        m_pen_data[0x10];
65	65	UINT8        m_blit_data[6];
66	66	UINT8        m_blit_buffer[256 * 256];
	67	DECLARE_WRITE8_MEMBER(blitter_process_w);
	68	DECLARE_WRITE8_MEMBER(blit_vregs_w);
	69	DECLARE_WRITE8_MEMBER(mux_w);
	70	DECLARE_WRITE8_MEMBER(output_w);
	71	DECLARE_WRITE8_MEMBER(sound_latch_w);
	72	DECLARE_READ8_MEMBER(sound_latch_r);
	73	DECLARE_WRITE8_MEMBER(cvsd_w);
	74	DECLARE_WRITE8_MEMBER(adpcm_w);
	75	DECLARE_READ8_MEMBER(master_com_r);
	76	DECLARE_WRITE8_MEMBER(master_com_w);
	77	DECLARE_READ8_MEMBER(slave_com_r);
	78	DECLARE_WRITE8_MEMBER(slave_com_w);
	79	DECLARE_READ8_MEMBER(jngolady_rng_r);
67	80	};
68	81
69	82
r14845	r14846
176	189	state->m_blit_buffer[(y * 256) + (x >> 1)] = (state->m_blit_buffer[(y * 256) + (x >> 1)] & 0xf0) | (pix & 0x0f);
177	190	}
178	191
179		static WRITE8_HANDLER( blitter_process_w )
	192	WRITE8_MEMBER(jangou_state::blitter_process_w)
180	193	{
181		jangou_state *state = space->machine().driver_data<jangou_state>();
182	194	int src, x, y, h, w, flipx;
183		state->m_blit_data[offset] = data;
	195	m_blit_data[offset] = data;
184	196
185	197	if (offset == 5)
186	198	{
187	199	int count = 0;
188	200	int xcount, ycount;
189	201
190		/* printf("%02x %02x %02x %02x %02x %02x\n", state->m_blit_data[0], state->m_blit_data[1], state->m_blit_data[2],
191		state->m_blit_data[3], state->m_blit_data[4], state->m_blit_data[5]); */
192		w = (state->m_blit_data[4] & 0xff) + 1;
193		h = (state->m_blit_data[5] & 0xff) + 1;
194		src = ((state->m_blit_data[1] << 8)|(state->m_blit_data[0] << 0));
195		x = (state->m_blit_data[2] & 0xff);
196		y = (state->m_blit_data[3] & 0xff);
	202	/* printf("%02x %02x %02x %02x %02x %02x\n", m_blit_data[0], m_blit_data[1], m_blit_data[2],
	203	m_blit_data[3], m_blit_data[4], m_blit_data[5]); */
	204	w = (m_blit_data[4] & 0xff) + 1;
	205	h = (m_blit_data[5] & 0xff) + 1;
	206	src = ((m_blit_data[1] << 8)|(m_blit_data[0] << 0));
	207	x = (m_blit_data[2] & 0xff);
	208	y = (m_blit_data[3] & 0xff);
197	209
198	210	// lowest bit of src controls flipping / draw direction?
199		flipx = (state->m_blit_data[0] & 1);
	211	flipx = (m_blit_data[0] & 1);
200	212
201	213	if (!flipx)
202	214	src += (w * h) - 1;
r14845	r14846
209	221	{
210	222	int drawx = (x + xcount) & 0xff;
211	223	int drawy = (y + ycount) & 0xff;
212		UINT8 dat = jangou_gfx_nibble(space->machine(), src + count);
213		UINT8 cur_pen_hi = state->m_pen_data[(dat & 0xf0) >> 4];
214		UINT8 cur_pen_lo = state->m_pen_data[(dat & 0x0f) >> 0];
	224	UINT8 dat = jangou_gfx_nibble(machine(), src + count);
	225	UINT8 cur_pen_hi = m_pen_data[(dat & 0xf0) >> 4];
	226	UINT8 cur_pen_lo = m_pen_data[(dat & 0x0f) >> 0];
215	227
216	228	dat = cur_pen_lo | (cur_pen_hi << 4);
217	229
218	230	if ((dat & 0xff) != 0)
219		plot_jangou_gfx_pixel(space->machine(), dat, drawx, drawy);
	231	plot_jangou_gfx_pixel(machine(), dat, drawx, drawy);
220	232
221	233	if (!flipx)
222	234	count--;
r14845	r14846
228	240	}
229	241
230	242	/* What is the bit 5 (0x20) for?*/
231		static WRITE8_HANDLER( blit_vregs_w )
	243	WRITE8_MEMBER(jangou_state::blit_vregs_w)
232	244	{
233		jangou_state *state = space->machine().driver_data<jangou_state>();
234	245
235	246	//  printf("%02x %02x\n", offset, data);
236		state->m_pen_data[offset] = data & 0xf;
	247	m_pen_data[offset] = data & 0xf;
237	248	}
238	249
239	250	/*************************************
r14845	r14846
242	253	*
243	254	*************************************/
244	255
245		static WRITE8_HANDLER( mux_w )
	256	WRITE8_MEMBER(jangou_state::mux_w)
246	257	{
247		jangou_state *state = space->machine().driver_data<jangou_state>();
248		state->m_mux_data = ~data;
	258	m_mux_data = ~data;
249	259	}
250	260
251		static WRITE8_HANDLER( output_w )
	261	WRITE8_MEMBER(jangou_state::output_w)
252	262	{
253	263	/*
254	264	--x- ---- ? (polls between high and low in irq routine,probably signals the vblank routine)
r14845	r14846
256	266	---- ---x coin counter
257	267	*/
258	268	//  printf("%02x\n", data);
259		coin_counter_w(space->machine(), 0, data & 0x01);
	269	coin_counter_w(machine(), 0, data & 0x01);
260	270	//  flip_screen_set(data & 0x04);
261		//  coin_lockout_w(space->machine(), 0, ~data & 0x20);
	271	//  coin_lockout_w(machine(), 0, ~data & 0x20);
262	272	}
263	273
264	274	static READ8_DEVICE_HANDLER( input_mux_r )
r14845	r14846
289	299	*
290	300	*************************************/
291	301
292		static WRITE8_HANDLER( sound_latch_w )
	302	WRITE8_MEMBER(jangou_state::sound_latch_w)
293	303	{
294		jangou_state *state = space->machine().driver_data<jangou_state>();
295	304	soundlatch_w(space, 0, data & 0xff);
296		device_set_input_line(state->m_cpu_1, INPUT_LINE_NMI, ASSERT_LINE);
	305	device_set_input_line(m_cpu_1, INPUT_LINE_NMI, ASSERT_LINE);
297	306	}
298	307
299		static READ8_HANDLER( sound_latch_r )
	308	READ8_MEMBER(jangou_state::sound_latch_r)
300	309	{
301		jangou_state *state = space->machine().driver_data<jangou_state>();
302		device_set_input_line(state->m_cpu_1, INPUT_LINE_NMI, CLEAR_LINE);
	310	device_set_input_line(m_cpu_1, INPUT_LINE_NMI, CLEAR_LINE);
303	311	return soundlatch_r(space, 0);
304	312	}
305	313
306	314	/* Jangou HC-55516 CVSD */
307		static WRITE8_HANDLER( cvsd_w )
	315	WRITE8_MEMBER(jangou_state::cvsd_w)
308	316	{
309		jangou_state *state = space->machine().driver_data<jangou_state>();
310		state->m_cvsd_shiftreg = data;
	317	m_cvsd_shiftreg = data;
311	318	}
312	319
313	320	static TIMER_CALLBACK( cvsd_bit_timer_callback )
r14845	r14846
325	332
326	333
327	334	/* Jangou Lady MSM5218 (MSM5205-compatible) ADPCM */
328		static WRITE8_HANDLER( adpcm_w )
	335	WRITE8_MEMBER(jangou_state::adpcm_w)
329	336	{
330		jangou_state *state = space->machine().driver_data<jangou_state>();
331		state->m_adpcm_byte = data;
	337	m_adpcm_byte = data;
332	338	}
333	339
334	340	static void jngolady_vclk_cb( device_t *device )
r14845	r14846
353	359	*
354	360	*************************************/
355	361
356		static READ8_HANDLER( master_com_r )
	362	READ8_MEMBER(jangou_state::master_com_r)
357	363	{
358		jangou_state *state = space->machine().driver_data<jangou_state>();
359		return state->m_z80_latch;
	364	return m_z80_latch;
360	365	}
361	366
362		static WRITE8_HANDLER( master_com_w )
	367	WRITE8_MEMBER(jangou_state::master_com_w)
363	368	{
364		jangou_state *state = space->machine().driver_data<jangou_state>();
365	369
366		device_set_input_line(state->m_nsc, 0, HOLD_LINE);
367		state->m_nsc_latch = data;
	370	device_set_input_line(m_nsc, 0, HOLD_LINE);
	371	m_nsc_latch = data;
368	372	}
369	373
370		static READ8_HANDLER( slave_com_r )
	374	READ8_MEMBER(jangou_state::slave_com_r)
371	375	{
372		jangou_state *state = space->machine().driver_data<jangou_state>();
373		return state->m_nsc_latch;
	376	return m_nsc_latch;
374	377	}
375	378
376		static WRITE8_HANDLER( slave_com_w )
	379	WRITE8_MEMBER(jangou_state::slave_com_w)
377	380	{
378		jangou_state *state = space->machine().driver_data<jangou_state>();
379		state->m_z80_latch = data;
	381	m_z80_latch = data;
380	382	}
381	383
382	384	/*************************************
r14845	r14846
395	397	AM_RANGE(0x01,0x01) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
396	398	AM_RANGE(0x02,0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
397	399	AM_RANGE(0x10,0x10) AM_READ_PORT("DSW") //dsw + blitter busy flag
398		AM_RANGE(0x10,0x10) AM_WRITE_LEGACY(output_w)
399		AM_RANGE(0x11,0x11) AM_WRITE_LEGACY(mux_w)
400		AM_RANGE(0x12,0x17) AM_WRITE_LEGACY(blitter_process_w)
401		AM_RANGE(0x20,0x2f) AM_WRITE_LEGACY(blit_vregs_w)
	400	AM_RANGE(0x10,0x10) AM_WRITE(output_w)
	401	AM_RANGE(0x11,0x11) AM_WRITE(mux_w)
	402	AM_RANGE(0x12,0x17) AM_WRITE(blitter_process_w)
	403	AM_RANGE(0x20,0x2f) AM_WRITE(blit_vregs_w)
402	404	AM_RANGE(0x30,0x30) AM_WRITENOP //? polls 0x03 continuously
403		AM_RANGE(0x31,0x31) AM_WRITE_LEGACY(sound_latch_w)
	405	AM_RANGE(0x31,0x31) AM_WRITE(sound_latch_w)
404	406	ADDRESS_MAP_END
405	407
406	408
r14845	r14846
410	412
411	413	static ADDRESS_MAP_START( cpu1_io, AS_IO, 8, jangou_state )
412	414	ADDRESS_MAP_GLOBAL_MASK(0xff)
413		AM_RANGE(0x00,0x00) AM_READ_LEGACY(sound_latch_r)
414		AM_RANGE(0x01,0x01) AM_WRITE_LEGACY(cvsd_w)
	415	AM_RANGE(0x00,0x00) AM_READ(sound_latch_r)
	416	AM_RANGE(0x01,0x01) AM_WRITE(cvsd_w)
415	417	AM_RANGE(0x02,0x02) AM_WRITENOP // Echoes sound command - acknowledge?
416	418	ADDRESS_MAP_END
417	419
r14845	r14846
425	427	static ADDRESS_MAP_START( jngolady_cpu0_map, AS_PROGRAM, 8, jangou_state )
426	428	AM_RANGE(0x0000, 0x9fff) AM_ROM
427	429	AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_SHARE("share1")
428		AM_RANGE(0xe000, 0xe000) AM_READWRITE_LEGACY(master_com_r,master_com_w)
	430	AM_RANGE(0xe000, 0xe000) AM_READWRITE(master_com_r,master_com_w)
429	431	ADDRESS_MAP_END
430	432
431	433
r14845	r14846
435	437
436	438	static ADDRESS_MAP_START( jngolady_cpu1_io, AS_IO, 8, jangou_state )
437	439	ADDRESS_MAP_GLOBAL_MASK(0xff)
438		AM_RANGE(0x00,0x00) AM_READ_LEGACY(sound_latch_r)
439		AM_RANGE(0x01,0x01) AM_WRITE_LEGACY(adpcm_w)
	440	AM_RANGE(0x00,0x00) AM_READ(sound_latch_r)
	441	AM_RANGE(0x01,0x01) AM_WRITE(adpcm_w)
440	442	AM_RANGE(0x02,0x02) AM_WRITENOP
441	443	ADDRESS_MAP_END
442	444
r14845	r14846
444	446	static ADDRESS_MAP_START( nsc_map, AS_PROGRAM, 8, jangou_state )
445	447	AM_RANGE(0x0000, 0x007f) AM_RAM //internal ram for irq etc.
446	448	AM_RANGE(0x8000, 0x8000) AM_WRITENOP //write-only,irq related?
447		AM_RANGE(0x9000, 0x9000) AM_READWRITE_LEGACY(slave_com_r,slave_com_w)
	449	AM_RANGE(0x9000, 0x9000) AM_READWRITE(slave_com_r,slave_com_w)
448	450	AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_SHARE("share1")
449	451	AM_RANGE(0xf000, 0xffff) AM_ROM
450	452	ADDRESS_MAP_END
r14845	r14846
466	468	AM_RANGE(0x01,0x01) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
467	469	AM_RANGE(0x02,0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
468	470	AM_RANGE(0x10,0x10) AM_READ_PORT("DSW") //dsw + blitter busy flag
469		AM_RANGE(0x10,0x10) AM_WRITE_LEGACY(output_w)
470		AM_RANGE(0x11,0x11) AM_WRITE_LEGACY(mux_w)
471		AM_RANGE(0x12,0x17) AM_WRITE_LEGACY(blitter_process_w)
472		AM_RANGE(0x20,0x2f) AM_WRITE_LEGACY(blit_vregs_w )
	471	AM_RANGE(0x10,0x10) AM_WRITE(output_w)
	472	AM_RANGE(0x11,0x11) AM_WRITE(mux_w)
	473	AM_RANGE(0x12,0x17) AM_WRITE(blitter_process_w)
	474	AM_RANGE(0x20,0x2f) AM_WRITE(blit_vregs_w )
473	475	AM_RANGE(0x30,0x30) AM_WRITENOP //? polls 0x03 continuously
474		//  AM_RANGE(0x31,0x31) AM_WRITE_LEGACY(sound_latch_w)
	476	//  AM_RANGE(0x31,0x31) AM_WRITE(sound_latch_w)
475	477	ADDRESS_MAP_END
476	478
477	479	/*************************************
r14845	r14846
491	493	AM_RANGE(0x02,0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
492	494	AM_RANGE(0x10,0x10) AM_READ_PORT("DSW")         /* DSW + blitter busy flag */
493	495	AM_RANGE(0x10,0x10) AM_WRITENOP               /* Writes continuosly 0's in attract mode, and 1's in game */
494		AM_RANGE(0x11,0x11) AM_WRITE_LEGACY(mux_w)
	496	AM_RANGE(0x11,0x11) AM_WRITE(mux_w)
495	497	AM_RANGE(0x13,0x13) AM_READNOP               /* Often reads bit7 with unknown purposes */
496		AM_RANGE(0x12,0x17) AM_WRITE_LEGACY(blitter_process_w)
497		AM_RANGE(0x20,0x2f) AM_WRITE_LEGACY(blit_vregs_w)
	498	AM_RANGE(0x12,0x17) AM_WRITE(blitter_process_w)
	499	AM_RANGE(0x20,0x2f) AM_WRITE(blit_vregs_w)
498	500	AM_RANGE(0x30,0x30) AM_WRITENOP               /* Seems to write 0x10 on each sound event */
499	501	ADDRESS_MAP_END
500	502
r14845	r14846
1353	1355	*************************************/
1354	1356
1355	1357	/*Temporary kludge for make the RNG work*/
1356		static READ8_HANDLER( jngolady_rng_r )
	1358	READ8_MEMBER(jangou_state::jngolady_rng_r)
1357	1359	{
1358		return space->machine().rand();
	1360	return machine().rand();
1359	1361	}
1360	1362
1361	1363	static DRIVER_INIT( jngolady )
1362	1364	{
1363		machine.device("nsc")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x08, 0x08, FUNC(jngolady_rng_r) );
	1365	jangou_state *state = machine.driver_data<jangou_state>();
	1366	machine.device("nsc")->memory().space(AS_PROGRAM)->install_read_handler(0x08, 0x08, read8_delegate(FUNC(jangou_state::jngolady_rng_r),state) );
1364	1367	}
1365	1368
1366	1369	static DRIVER_INIT (luckygrl)

src/mame/drivers/pengadvb.c

r14845	r14846
37	37	UINT8 *m_main_mem;
38	38	UINT8 m_mem_map;
39	39	UINT8 m_mem_banks[4];
	40	DECLARE_WRITE8_MEMBER(mem_w);
40	41	};
41	42
42	43
r14845	r14846
122	123	}
123	124	}
124	125
125		static WRITE8_HANDLER(mem_w)
	126	WRITE8_MEMBER(pengadvb_state::mem_w)
126	127	{
127		pengadvb_state *state = space->machine().driver_data<pengadvb_state>();
128	128	if (offset >= 0xc000)
129	129	{
130	130	// write to RAM
131		if ((state->m_mem_map >> 6 & 3) == 3)
132		state->m_main_mem[offset - 0xc000] = data;
	131	if ((m_mem_map >> 6 & 3) == 3)
	132	m_main_mem[offset - 0xc000] = data;
133	133	}
134		else if (offset >= 0x4000 && (state->m_mem_map >> (offset >> 13 & 6) & 3) == 1 && (state->m_mem_banks[(offset - 0x4000) >> 13] != (data & 0xf)))
	134	else if (offset >= 0x4000 && (m_mem_map >> (offset >> 13 & 6) & 3) == 1 && (m_mem_banks[(offset - 0x4000) >> 13] != (data & 0xf)))
135	135	{
136	136	// ROM bankswitch
137		state->m_mem_banks[(offset - 0x4000) >> 13] = data & 0xf;
138		mem_map_banks(space->machine());
	137	m_mem_banks[(offset - 0x4000) >> 13] = data & 0xf;
	138	mem_map_banks(machine());
139	139	}
140	140	}
141	141
r14845	r14846
147	147	AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("bank31")
148	148	AM_RANGE(0xa000, 0xbfff) AM_ROMBANK("bank32")
149	149	AM_RANGE(0xc000, 0xffff) AM_ROMBANK("bank4")
150		AM_RANGE(0x0000, 0xffff) AM_WRITE_LEGACY(mem_w)
	150	AM_RANGE(0x0000, 0xffff) AM_WRITE(mem_w)
151	151	ADDRESS_MAP_END
152	152
153	153	static ADDRESS_MAP_START( io_mem, AS_IO, 8, pengadvb_state )

src/mame/drivers/ssingles.c

r14845	r14846
163	163	pen_t m_pens[NUM_PENS];
164	164
165	165	UINT8 m_atamanot_prot_state;
	166	DECLARE_WRITE8_MEMBER(ssingles_videoram_w);
	167	DECLARE_WRITE8_MEMBER(ssingles_colorram_w);
	168	DECLARE_READ8_MEMBER(c000_r);
	169	DECLARE_READ8_MEMBER(c001_r);
	170	DECLARE_WRITE8_MEMBER(c001_w);
	171	DECLARE_READ8_MEMBER(atamanot_prot_r);
	172	DECLARE_WRITE8_MEMBER(atamanot_prot_w);
166	173	};
167	174
168	175	//fake palette
r14845	r14846
283	290	};
284	291
285	292
286		static WRITE8_HANDLER(ssingles_videoram_w)
	293	WRITE8_MEMBER(ssingles_state::ssingles_videoram_w)
287	294	{
288		ssingles_state *state = space->machine().driver_data<ssingles_state>();
289		UINT8 *vram = space->machine().region("vram")->base();
	295	UINT8 *vram = machine().region("vram")->base();
290	296	vram[offset] = data;
291		state->m_videoram[offset]=data;
	297	m_videoram[offset]=data;
292	298	}
293	299
294		static WRITE8_HANDLER(ssingles_colorram_w)
	300	WRITE8_MEMBER(ssingles_state::ssingles_colorram_w)
295	301	{
296		ssingles_state *state = space->machine().driver_data<ssingles_state>();
297		UINT8 *cram = space->machine().region("cram")->base();
	302	UINT8 *cram = machine().region("cram")->base();
298	303	cram[offset] = data;
299		state->m_colorram[offset]=data;
	304	m_colorram[offset]=data;
300	305	}
301	306
302	307
r14845	r14846
314	319	}
315	320
316	321
317		static READ8_HANDLER(c000_r)
	322	READ8_MEMBER(ssingles_state::c000_r)
318	323	{
319		ssingles_state *state = space->machine().driver_data<ssingles_state>();
320	324
321		return state->m_prot_data;
	325	return m_prot_data;
322	326	}
323	327
324		static READ8_HANDLER(c001_r)
	328	READ8_MEMBER(ssingles_state::c001_r)
325	329	{
326		ssingles_state *state = space->machine().driver_data<ssingles_state>();
327	330
328		state->m_prot_data=0xc4;
	331	m_prot_data=0xc4;
329	332	return 0;
330	333	}
331	334
332		static WRITE8_HANDLER(c001_w)
	335	WRITE8_MEMBER(ssingles_state::c001_w)
333	336	{
334		ssingles_state *state = space->machine().driver_data<ssingles_state>();
335	337
336		state->m_prot_data^=data^0x11;
	338	m_prot_data^=data^0x11;
337	339	}
338	340
339	341	static CUSTOM_INPUT(controls_r)
r14845	r14846
354	356	}
355	357
356	358	static ADDRESS_MAP_START( ssingles_map, AS_PROGRAM, 8, ssingles_state )
357		AM_RANGE(0x0000, 0x00ff) AM_WRITE_LEGACY(ssingles_videoram_w)
358		AM_RANGE(0x0800, 0x08ff) AM_WRITE_LEGACY(ssingles_colorram_w)
	359	AM_RANGE(0x0000, 0x00ff) AM_WRITE(ssingles_videoram_w)
	360	AM_RANGE(0x0800, 0x08ff) AM_WRITE(ssingles_colorram_w)
359	361	AM_RANGE(0x0000, 0x1fff) AM_ROM
360		AM_RANGE(0xc000, 0xc000) AM_READ_LEGACY(c000_r )
361		AM_RANGE(0xc001, 0xc001) AM_READWRITE_LEGACY(c001_r, c001_w )
	362	AM_RANGE(0xc000, 0xc000) AM_READ(c000_r )
	363	AM_RANGE(0xc001, 0xc001) AM_READWRITE(c001_r, c001_w )
362	364	AM_RANGE(0x6000, 0xbfff) AM_ROM
363	365	AM_RANGE(0xf800, 0xffff) AM_RAM
364	366	ADDRESS_MAP_END
365	367
366	368
367		static READ8_HANDLER( atamanot_prot_r )
	369	READ8_MEMBER(ssingles_state::atamanot_prot_r)
368	370	{
369		ssingles_state *state = space->machine().driver_data<ssingles_state>();
370	371	static const char prot_id[] = { "PROGRAM BY KOYAMA" };
371	372
372		logerror("%04x %02x\n",offset,state->m_atamanot_prot_state);
	373	logerror("%04x %02x\n",offset,m_atamanot_prot_state);
373	374
374		switch(state->m_atamanot_prot_state)
	375	switch(m_atamanot_prot_state)
375	376	{
376	377	case 0x20:
377	378	case 0x21:
r14845	r14846
386	387	return 0;
387	388	}
388	389
389		static WRITE8_HANDLER( atamanot_prot_w )
	390	WRITE8_MEMBER(ssingles_state::atamanot_prot_w)
390	391	{
391		ssingles_state *state = space->machine().driver_data<ssingles_state>();
392	392
393		state->m_atamanot_prot_state = data;
	393	m_atamanot_prot_state = data;
394	394	}
395	395
396	396
397	397	static ADDRESS_MAP_START( atamanot_map, AS_PROGRAM, 8, ssingles_state )
398		AM_RANGE(0x0000, 0x00ff) AM_WRITE_LEGACY(ssingles_videoram_w)
399		AM_RANGE(0x0800, 0x08ff) AM_WRITE_LEGACY(ssingles_colorram_w)
	398	AM_RANGE(0x0000, 0x00ff) AM_WRITE(ssingles_videoram_w)
	399	AM_RANGE(0x0800, 0x08ff) AM_WRITE(ssingles_colorram_w)
400	400	AM_RANGE(0x0000, 0x3fff) AM_ROM
401	401	AM_RANGE(0x4000, 0x47ff) AM_RAM
402	402	AM_RANGE(0x6000, 0x60ff) AM_RAM //kanji tilemap?
403	403	//  AM_RANGE(0x6000, 0x7fff) AM_ROM
404		AM_RANGE(0x8000, 0x83ff) AM_READ_LEGACY(atamanot_prot_r)
	404	AM_RANGE(0x8000, 0x83ff) AM_READ(atamanot_prot_r)
405	405	//  AM_RANGE(0x8000, 0x9fff) AM_ROM AM_REGION("question",0x10000)
406		//  AM_RANGE(0xc000, 0xc000) AM_READ_LEGACY(c000_r )
407		//  AM_RANGE(0xc001, 0xc001) AM_READWRITE_LEGACY(c001_r, c001_w )
	406	//  AM_RANGE(0xc000, 0xc000) AM_READ(c000_r )
	407	//  AM_RANGE(0xc001, 0xc001) AM_READWRITE(c001_r, c001_w )
408	408	ADDRESS_MAP_END
409	409
410	410	static ADDRESS_MAP_START( ssingles_io_map, AS_IO, 8, ssingles_state )
r14845	r14846
430	430	AM_RANGE(0x08, 0x08) AM_READNOP
431	431	AM_RANGE(0x0a, 0x0a) AM_DEVWRITE_LEGACY("ay2", ay8910_data_w)
432	432	AM_RANGE(0x16, 0x16) AM_READ_PORT("DSW0")
433		AM_RANGE(0x18, 0x18) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(atamanot_prot_w)
	433	AM_RANGE(0x18, 0x18) AM_READ_PORT("DSW1") AM_WRITE(atamanot_prot_w)
434	434	AM_RANGE(0x1c, 0x1c) AM_READ_PORT("INPUTS")
435	435	//  AM_RANGE(0x1a, 0x1a) AM_WRITENOP //video/crt related
436	436	AM_RANGE(0xfe, 0xfe) AM_DEVWRITE("crtc", mc6845_device, address_w)

src/mame/drivers/kinst.c

r14845	r14846
148	148	UINT32 *m_video_base;
149	149	UINT32 *m_control;
150	150	const UINT8 *m_control_map;
	151	DECLARE_READ32_MEMBER(kinst_control_r);
	152	DECLARE_WRITE32_MEMBER(kinst_control_w);
151	153	};
152	154
153	155
r14845	r14846
320	322	*
321	323	*************************************/
322	324
323		static READ32_HANDLER( kinst_control_r )
	325	READ32_MEMBER(kinst_state::kinst_control_r)
324	326	{
325		kinst_state *state = space->machine().driver_data<kinst_state>();
326	327	UINT32 result;
327	328	static const char *const portnames[] = { "P1", "P2", "VOLUME", "UNUSED", "DSW" };
328	329
329	330	/* apply shuffling */
330		offset = state->m_control_map[offset / 2];
331		result = state->m_control[offset];
	331	offset = m_control_map[offset / 2];
	332	result = m_control[offset];
332	333
333	334	switch (offset)
334	335	{
335	336	case 2:      /* $90 -- sound return */
336		result = input_port_read(space->machine(), portnames[offset]);
	337	result = input_port_read(machine(), portnames[offset]);
337	338	result &= ~0x0002;
338		if (dcs_control_r(space->machine()) & 0x800)
	339	if (dcs_control_r(machine()) & 0x800)
339	340	result |= 0x0002;
340	341	break;
341	342
342	343	case 0:      /* $80 */
343	344	case 1:      /* $88 */
344	345	case 3:      /* $98 */
345		result = input_port_read(space->machine(), portnames[offset]);
	346	result = input_port_read(machine(), portnames[offset]);
346	347	break;
347	348
348	349	case 4:      /* $a0 */
349		result = input_port_read(space->machine(), portnames[offset]);
350		if (cpu_get_pc(&space->device()) == 0x802d428)
351		device_spin_until_interrupt(&space->device());
	350	result = input_port_read(machine(), portnames[offset]);
	351	if (cpu_get_pc(&space.device()) == 0x802d428)
	352	device_spin_until_interrupt(&space.device());
352	353	break;
353	354	}
354	355
r14845	r14846
356	357	}
357	358
358	359
359		static WRITE32_HANDLER( kinst_control_w )
	360	WRITE32_MEMBER(kinst_state::kinst_control_w)
360	361	{
361		kinst_state *state = space->machine().driver_data<kinst_state>();
362	362	UINT32 olddata;
363	363
364	364	/* apply shuffling */
365		offset = state->m_control_map[offset / 2];
366		olddata = state->m_control[offset];
367		COMBINE_DATA(&state->m_control[offset]);
	365	offset = m_control_map[offset / 2];
	366	olddata = m_control[offset];
	367	COMBINE_DATA(&m_control[offset]);
368	368
369	369	switch (offset)
370	370	{
371	371	case 0:      /* $80 - VRAM buffer control */
372	372	if (data & 4)
373		state->m_video_base = &state->m_rambase[0x58000/4];
	373	m_video_base = &m_rambase[0x58000/4];
374	374	else
375		state->m_video_base = &state->m_rambase[0x30000/4];
	375	m_video_base = &m_rambase[0x30000/4];
376	376	break;
377	377
378	378	case 1:      /* $88 - sound reset */
379		dcs_reset_w(space->machine(), ~data & 0x01);
	379	dcs_reset_w(machine(), ~data & 0x01);
380	380	break;
381	381
382	382	case 2:      /* $90 - sound control */
383		if (!(olddata & 0x02) && (state->m_control[offset] & 0x02))
384		dcs_data_w(space->machine(), state->m_control[3]);
	383	if (!(olddata & 0x02) && (m_control[offset] & 0x02))
	384	dcs_data_w(machine(), m_control[3]);
385	385	break;
386	386
387	387	case 3:      /* $98 - sound data */
r14845	r14846
401	401	ADDRESS_MAP_UNMAP_HIGH
402	402	AM_RANGE(0x00000000, 0x0007ffff) AM_RAM AM_BASE(m_rambase)
403	403	AM_RANGE(0x08000000, 0x087fffff) AM_RAM AM_BASE(m_rambase2)
404		AM_RANGE(0x10000080, 0x100000ff) AM_READWRITE_LEGACY(kinst_control_r, kinst_control_w) AM_BASE(m_control)
	404	AM_RANGE(0x10000080, 0x100000ff) AM_READWRITE(kinst_control_r, kinst_control_w) AM_BASE(m_control)
405	405	AM_RANGE(0x10000100, 0x1000013f) AM_DEVREADWRITE_LEGACY("ide", kinst_ide_r, kinst_ide_w)
406	406	AM_RANGE(0x10000170, 0x10000173) AM_DEVREADWRITE_LEGACY("ide", kinst_ide_extra_r, kinst_ide_extra_w)
407	407	AM_RANGE(0x1fc00000, 0x1fc7ffff) AM_ROM AM_REGION("user1", 0) AM_BASE(m_rombase)

src/mame/drivers/sub.c

r14845	r14846
124	124	UINT8* m_spriteram;
125	125	UINT8* m_spriteram2;
126	126	UINT8 m_nmi_en;
	127	DECLARE_WRITE8_MEMBER(subm_to_sound_w);
	128	DECLARE_WRITE8_MEMBER(nmi_mask_w);
127	129	};
128	130
129	131	static VIDEO_START(sub)
r14845	r14846
235	237	AM_RANGE(0xf060, 0xf060) AM_READ_PORT("IN0")
236	238	ADDRESS_MAP_END
237	239
238		static WRITE8_HANDLER( subm_to_sound_w )
	240	WRITE8_MEMBER(sub_state::subm_to_sound_w)
239	241	{
240	242	soundlatch_w(space, 0, data & 0xff);
241		cputag_set_input_line(space->machine(), "soundcpu", 0, HOLD_LINE);
	243	cputag_set_input_line(machine(), "soundcpu", 0, HOLD_LINE);
242	244	}
243	245
244		static WRITE8_HANDLER( nmi_mask_w )
	246	WRITE8_MEMBER(sub_state::nmi_mask_w)
245	247	{
246		sub_state *state = space->machine().driver_data<sub_state>();
247	248
248		state->m_nmi_en = data & 1;
	249	m_nmi_en = data & 1;
249	250	}
250	251
251	252	static ADDRESS_MAP_START( subm_io, AS_IO, 8, sub_state )
252	253	ADDRESS_MAP_GLOBAL_MASK(0xff)
253		AM_RANGE(0x00, 0x00) AM_READWRITE_LEGACY(soundlatch2_r, subm_to_sound_w) // to/from sound CPU
	254	AM_RANGE(0x00, 0x00) AM_READ_LEGACY(soundlatch2_r) AM_WRITE(subm_to_sound_w) // to/from sound CPU
254	255	ADDRESS_MAP_END
255	256
256	257	static ADDRESS_MAP_START( subm_sound_map, AS_PROGRAM, 8, sub_state )
257	258	AM_RANGE(0x0000, 0x3fff) AM_ROM
258	259	AM_RANGE(0x4000, 0x47ff) AM_RAM
259		AM_RANGE(0x6000, 0x6000) AM_WRITE_LEGACY(nmi_mask_w)
	260	AM_RANGE(0x6000, 0x6000) AM_WRITE(nmi_mask_w)
260	261	ADDRESS_MAP_END
261	262
262	263	static ADDRESS_MAP_START( subm_sound_io, AS_IO, 8, sub_state )

src/mame/drivers/mpoker.c

r14845	r14846
183	183	UINT8 m_output[8];
184	184	UINT8* m_video;
185	185	int m_mixdata;
	186	DECLARE_READ8_MEMBER(mixport_r);
	187	DECLARE_WRITE8_MEMBER(muxed_w);
	188	DECLARE_WRITE8_MEMBER(outport0_w);
	189	DECLARE_WRITE8_MEMBER(outport1_w);
	190	DECLARE_WRITE8_MEMBER(outport2_w);
	191	DECLARE_WRITE8_MEMBER(outport3_w);
	192	DECLARE_WRITE8_MEMBER(outport4_w);
	193	DECLARE_WRITE8_MEMBER(outport5_w);
	194	DECLARE_WRITE8_MEMBER(outport6_w);
	195	DECLARE_WRITE8_MEMBER(outport7_w);
	196	DECLARE_WRITE8_MEMBER(sound_w);
186	197	};
187	198
188	199
r14845	r14846
230	241	}
231	242	}
232	243
233		static READ8_HANDLER( mixport_r )
	244	READ8_MEMBER(mpoker_state::mixport_r)
234	245	{
235		mpoker_state *state = space->machine().driver_data<mpoker_state>();
236	246	/*  - bits -
237	247	7654 3210
238	248	---- ---x   Unknown.
r14845	r14846
247	257	If you change the status *every* read, the HW stucks.
248	258	*/
249	259
250		state->m_mixdata = (input_port_read(space->machine(), "SW2") & 0xfd) | (space->machine().rand() & 0x02);
	260	m_mixdata = (input_port_read(machine(), "SW2") & 0xfd) | (machine().rand() & 0x02);
251	261
252		return state->m_mixdata;
	262	return m_mixdata;
253	263	}
254	264
255	265	/***** Port 0158 *****
r14845	r14846
264	274	xxx- ----   Unknown.
265	275	*/
266	276
267		//static WRITE8_HANDLER( muxed_w )
	277	//WRITE8_MEMBER(mpoker_state::muxed_w)
268	278	//{
269	279	//  popmessage("written : %02X %02X %02X %02X %02X %02X %02X %02X", data & 0x01, data & 0x02, data & 0x04, data & 0x08, data & 0x10, data & 0x20, data & 0x40, data & 0x80);
270	280	//}
r14845	r14846
281	291	xxx- ----   Unknown.
282	292	*/
283	293
284		static WRITE8_HANDLER( outport0_w )
	294	WRITE8_MEMBER(mpoker_state::outport0_w)
285	295	{
286		mpoker_state *state = space->machine().driver_data<mpoker_state>();
287	296	output_set_lamp_value(1, (data & 1));         /* Lamp 1 - BET */
288	297	output_set_lamp_value(5, (data >> 1) & 1);      /* Lamp 5 - HOLD 1 */
289	298
290		state->m_output[0] = data;
291		popmessage("outport0 : %02X %02X %02X %02X %02X %02X %02X %02X", state->m_output[0], state->m_output[1], state->m_output[2], state->m_output[3], state->m_output[4], state->m_output[5], state->m_output[6], state->m_output[7]);
	299	m_output[0] = data;
	300	popmessage("outport0 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
292	301	}
293	302
294	303	/***** Port 8001 *****
r14845	r14846
303	312	xxx- ----   Unknown.
304	313	*/
305	314
306		static WRITE8_HANDLER( outport1_w )
	315	WRITE8_MEMBER(mpoker_state::outport1_w)
307	316	{
308		mpoker_state *state = space->machine().driver_data<mpoker_state>();
309	317	output_set_lamp_value(2, (data & 1));         /* Lamp 2 - DEAL */
310	318	output_set_lamp_value(6, (data >> 1) & 1);      /* Lamp 6 - HOLD 2 */
311	319
312		state->m_output[1] = data;
313		popmessage("outport1 : %02X %02X %02X %02X %02X %02X %02X %02X", state->m_output[0], state->m_output[1], state->m_output[2], state->m_output[3], state->m_output[4], state->m_output[5], state->m_output[6], state->m_output[7]);
	320	m_output[1] = data;
	321	popmessage("outport1 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
314	322	}
315	323
316	324	/***** Port 8002 *****
r14845	r14846
325	333	xxx- ----   Unknown.
326	334	*/
327	335
328		static WRITE8_HANDLER( outport2_w )
	336	WRITE8_MEMBER(mpoker_state::outport2_w)
329	337	{
330		mpoker_state *state = space->machine().driver_data<mpoker_state>();
331	338	output_set_lamp_value(3, (data & 1));         /* Lamp 3 - CANCEL */
332	339	output_set_lamp_value(7, (data >> 1) & 1);      /* Lamp 7 - HOLD 3 */
333	340
334		state->m_output[2] = data;
335		popmessage("outport2 : %02X %02X %02X %02X %02X %02X %02X %02X", state->m_output[0], state->m_output[1], state->m_output[2], state->m_output[3], state->m_output[4], state->m_output[5], state->m_output[6], state->m_output[7]);
	341	m_output[2] = data;
	342	popmessage("outport2 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
336	343	}
337	344
338	345	/***** Port 8003 *****
r14845	r14846
347	354	xxx- ----   Unknown.
348	355	*/
349	356
350		static WRITE8_HANDLER( outport3_w )
	357	WRITE8_MEMBER(mpoker_state::outport3_w)
351	358	{
352		mpoker_state *state = space->machine().driver_data<mpoker_state>();
353	359	output_set_lamp_value(4, (data & 1));         /* Lamp 4 - STAND */
354	360	output_set_lamp_value(8, (data >> 1) & 1);      /* Lamp 8 - HOLD 4 */
355	361
356		state->m_output[3] = data;
357		popmessage("outport3 : %02X %02X %02X %02X %02X %02X %02X %02X", state->m_output[0], state->m_output[1], state->m_output[2], state->m_output[3], state->m_output[4], state->m_output[5], state->m_output[6], state->m_output[7]);
	362	m_output[3] = data;
	363	popmessage("outport3 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
358	364	}
359	365
360	366	/***** Port 8004 *****
r14845	r14846
369	375	xxx- ----   Unknown.
370	376	*/
371	377
372		static WRITE8_HANDLER( outport4_w )
	378	WRITE8_MEMBER(mpoker_state::outport4_w)
373	379	{
374		mpoker_state *state = space->machine().driver_data<mpoker_state>();
375	380	output_set_lamp_value(9, (data >> 1) & 1);      /* Lamp 9 - HOLD 5 */
376	381
377		state->m_output[4] = data;
378		popmessage("outport4 : %02X %02X %02X %02X %02X %02X %02X %02X", state->m_output[0], state->m_output[1], state->m_output[2], state->m_output[3], state->m_output[4], state->m_output[5], state->m_output[6], state->m_output[7]);
	382	m_output[4] = data;
	383	popmessage("outport4 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
379	384	}
380	385
381	386	/***** Port 8005 *****
r14845	r14846
390	395	xxx- ----   Unknown.
391	396	*/
392	397
393		static WRITE8_HANDLER( outport5_w )
	398	WRITE8_MEMBER(mpoker_state::outport5_w)
394	399	{
395		mpoker_state *state = space->machine().driver_data<mpoker_state>();
396		state->m_output[5] = data;
397		popmessage("outport5 : %02X %02X %02X %02X %02X %02X %02X %02X", state->m_output[0], state->m_output[1], state->m_output[2], state->m_output[3], state->m_output[4], state->m_output[5], state->m_output[6], state->m_output[7]);
	400	m_output[5] = data;
	401	popmessage("outport5 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
398	402	}
399	403
400	404	/***** Port 8006 *****
r14845	r14846
409	413	xxx- ----   Unknown.
410	414	*/
411	415
412		static WRITE8_HANDLER( outport6_w )
	416	WRITE8_MEMBER(mpoker_state::outport6_w)
413	417	{
414		mpoker_state *state = space->machine().driver_data<mpoker_state>();
415		coin_counter_w(space->machine(), 1, data & 0x02);   /* Payout pulse */
	418	coin_counter_w(machine(), 1, data & 0x02);   /* Payout pulse */
416	419
417		state->m_output[6] = data;
418		popmessage("outport6 : %02X %02X %02X %02X %02X %02X %02X %02X", state->m_output[0], state->m_output[1], state->m_output[2], state->m_output[3], state->m_output[4], state->m_output[5], state->m_output[6], state->m_output[7]);
	420	m_output[6] = data;
	421	popmessage("outport6 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
419	422	}
420	423
421	424	/***** Port 8007 *****
r14845	r14846
430	433	xxx- ----   Unknown.
431	434	*/
432	435
433		static WRITE8_HANDLER( outport7_w )
	436	WRITE8_MEMBER(mpoker_state::outport7_w)
434	437	{
435		mpoker_state *state = space->machine().driver_data<mpoker_state>();
436		coin_counter_w(space->machine(), 0, data & 0x02);   /* Coin pulse */
	438	coin_counter_w(machine(), 0, data & 0x02);   /* Coin pulse */
437	439
438		state->m_output[7] = data;
439		popmessage("outport7 : %02X %02X %02X %02X %02X %02X %02X %02X", state->m_output[0], state->m_output[1], state->m_output[2], state->m_output[3], state->m_output[4], state->m_output[5], state->m_output[6], state->m_output[7]);
	440	m_output[7] = data;
	441	popmessage("outport7 : %02X %02X %02X %02X %02X %02X %02X %02X", m_output[0], m_output[1], m_output[2], m_output[3], m_output[4], m_output[5], m_output[6], m_output[7]);
440	442	}
441	443
442	444
r14845	r14846
462	464	05   | ---- | ---- | ---- | bit2
463	465
464	466
465		//static WRITE8_HANDLER( sound_w )
	467	WRITE8_MEMBER(mpoker_state::sound_w)
466	468	//{
467		//  dac_data_w(space->machine().device("dac"), data);
	469	//  dac_data_w(machine().device("dac"), data);
468	470	//}
469	471	*/
470	472
r14845	r14846
474	476	AM_RANGE(0x3800, 0x38ff) AM_RAM AM_SHARE("nvram")   /* NVRAM = 2x SCM5101E */
475	477	AM_RANGE(0x4000, 0x47ff) AM_RAM AM_BASE(m_video)   /* 4x MM2114N-3 */
476	478	AM_RANGE(0x8000, 0x8000) AM_READ_PORT("SW1")
477		AM_RANGE(0x8001, 0x8001) AM_READ_LEGACY(mixport_r) /* DIP switch bank 2 + a sort of watchdog */
	479	AM_RANGE(0x8001, 0x8001) AM_READ(mixport_r) /* DIP switch bank 2 + a sort of watchdog */
478	480	AM_RANGE(0x8002, 0x8002) AM_READ_PORT("IN1")
479	481	AM_RANGE(0x8003, 0x8003) AM_READ_PORT("IN2")
480		AM_RANGE(0x8000, 0x8000) AM_WRITE_LEGACY(outport0_w)
481		AM_RANGE(0x8001, 0x8001) AM_WRITE_LEGACY(outport1_w)
482		AM_RANGE(0x8002, 0x8002) AM_WRITE_LEGACY(outport2_w)
483		AM_RANGE(0x8003, 0x8003) AM_WRITE_LEGACY(outport3_w)
484		AM_RANGE(0x8004, 0x8004) AM_WRITE_LEGACY(outport4_w)
485		AM_RANGE(0x8005, 0x8005) AM_WRITE_LEGACY(outport5_w)
486		AM_RANGE(0x8006, 0x8006) AM_WRITE_LEGACY(outport6_w)
487		AM_RANGE(0x8007, 0x8007) AM_WRITE_LEGACY(outport7_w)
	482	AM_RANGE(0x8000, 0x8000) AM_WRITE(outport0_w)
	483	AM_RANGE(0x8001, 0x8001) AM_WRITE(outport1_w)
	484	AM_RANGE(0x8002, 0x8002) AM_WRITE(outport2_w)
	485	AM_RANGE(0x8003, 0x8003) AM_WRITE(outport3_w)
	486	AM_RANGE(0x8004, 0x8004) AM_WRITE(outport4_w)
	487	AM_RANGE(0x8005, 0x8005) AM_WRITE(outport5_w)
	488	AM_RANGE(0x8006, 0x8006) AM_WRITE(outport6_w)
	489	AM_RANGE(0x8007, 0x8007) AM_WRITE(outport7_w)
488	490
489	491	ADDRESS_MAP_END
490	492

src/mame/drivers/skyarmy.c

r14845	r14846
41	41	UINT8 *m_scrollram;
42	42	tilemap_t* m_tilemap;
43	43	int m_nmi;
	44	DECLARE_WRITE8_MEMBER(skyarmy_flip_screen_x_w);
	45	DECLARE_WRITE8_MEMBER(skyarmy_flip_screen_y_w);
	46	DECLARE_WRITE8_MEMBER(skyarmy_videoram_w);
	47	DECLARE_WRITE8_MEMBER(skyarmy_colorram_w);
	48	DECLARE_WRITE8_MEMBER(nmi_enable_w);
44	49	};
45	50
46		static WRITE8_HANDLER( skyarmy_flip_screen_x_w )
	51	WRITE8_MEMBER(skyarmy_state::skyarmy_flip_screen_x_w)
47	52	{
48		flip_screen_x_set(space->machine(), data & 0x01);
	53	flip_screen_x_set(machine(), data & 0x01);
49	54	}
50	55
51		static WRITE8_HANDLER( skyarmy_flip_screen_y_w )
	56	WRITE8_MEMBER(skyarmy_state::skyarmy_flip_screen_y_w)
52	57	{
53		flip_screen_y_set(space->machine(), data & 0x01);
	58	flip_screen_y_set(machine(), data & 0x01);
54	59	}
55	60
56	61	static TILE_GET_INFO( get_skyarmy_tile_info )
r14845	r14846
62	67	SET_TILE_INFO( 0, code, attr, 0);
63	68	}
64	69
65		static WRITE8_HANDLER( skyarmy_videoram_w )
	70	WRITE8_MEMBER(skyarmy_state::skyarmy_videoram_w)
66	71	{
67		skyarmy_state *state = space->machine().driver_data<skyarmy_state>();
68	72
69		state->m_videoram[offset] = data;
70		state->m_tilemap->mark_tile_dirty(offset);
	73	m_videoram[offset] = data;
	74	m_tilemap->mark_tile_dirty(offset);
71	75	}
72	76
73		static WRITE8_HANDLER( skyarmy_colorram_w )
	77	WRITE8_MEMBER(skyarmy_state::skyarmy_colorram_w)
74	78	{
75		skyarmy_state *state = space->machine().driver_data<skyarmy_state>();
76	79
77		state->m_colorram[offset] = data;
78		state->m_tilemap->mark_tile_dirty(offset);
	80	m_colorram[offset] = data;
	81	m_tilemap->mark_tile_dirty(offset);
79	82	}
80	83
81	84	static PALETTE_INIT( skyarmy )
r14845	r14846
154	157	}
155	158
156	159
157		static WRITE8_HANDLER( nmi_enable_w )
	160	WRITE8_MEMBER(skyarmy_state::nmi_enable_w)
158	161	{
159		skyarmy_state *state = space->machine().driver_data<skyarmy_state>();
160	162
161		state->m_nmi=data & 1;
	163	m_nmi=data & 1;
162	164	}
163	165
164	166
165	167	static ADDRESS_MAP_START( skyarmy_map, AS_PROGRAM, 8, skyarmy_state )
166	168	AM_RANGE(0x0000, 0x7fff) AM_ROM
167	169	AM_RANGE(0x8000, 0x87ff) AM_RAM
168		AM_RANGE(0x8800, 0x8fff) AM_RAM_WRITE_LEGACY(skyarmy_videoram_w) AM_BASE(m_videoram) /* Video RAM */
169		AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE_LEGACY(skyarmy_colorram_w) AM_BASE(m_colorram) /* Color RAM */
	170	AM_RANGE(0x8800, 0x8fff) AM_RAM_WRITE(skyarmy_videoram_w) AM_BASE(m_videoram) /* Video RAM */
	171	AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(skyarmy_colorram_w) AM_BASE(m_colorram) /* Color RAM */
170	172	AM_RANGE(0x9800, 0x983f) AM_RAM AM_BASE(m_spriteram) /* Sprites */
171	173	AM_RANGE(0x9840, 0x985f) AM_RAM AM_BASE(m_scrollram)  /* Scroll RAM */
172	174	AM_RANGE(0xa000, 0xa000) AM_READ_PORT("DSW")
173	175	AM_RANGE(0xa001, 0xa001) AM_READ_PORT("P1")
174	176	AM_RANGE(0xa002, 0xa002) AM_READ_PORT("P2")
175	177	AM_RANGE(0xa003, 0xa003) AM_READ_PORT("SYSTEM")
176		AM_RANGE(0xa004, 0xa004) AM_WRITE_LEGACY(nmi_enable_w) // ???
177		AM_RANGE(0xa005, 0xa005) AM_WRITE_LEGACY(skyarmy_flip_screen_x_w)
178		AM_RANGE(0xa006, 0xa006) AM_WRITE_LEGACY(skyarmy_flip_screen_y_w)
	178	AM_RANGE(0xa004, 0xa004) AM_WRITE(nmi_enable_w) // ???
	179	AM_RANGE(0xa005, 0xa005) AM_WRITE(skyarmy_flip_screen_x_w)
	180	AM_RANGE(0xa006, 0xa006) AM_WRITE(skyarmy_flip_screen_y_w)
179	181	AM_RANGE(0xa007, 0xa007) AM_WRITENOP
180	182	ADDRESS_MAP_END
181	183

src/mame/drivers/suprgolf.c

r14845	r14846
47	47	UINT8 m_palette_switch;
48	48	UINT8 m_bg_vreg_test;
49	49	UINT8 m_toggle;
	50	DECLARE_READ8_MEMBER(suprgolf_videoram_r);
	51	DECLARE_WRITE8_MEMBER(suprgolf_videoram_w);
	52	DECLARE_READ8_MEMBER(suprgolf_bg_vram_r);
	53	DECLARE_WRITE8_MEMBER(suprgolf_bg_vram_w);
	54	DECLARE_WRITE8_MEMBER(suprgolf_pen_w);
	55	DECLARE_WRITE8_MEMBER(adpcm_data_w);
	56	DECLARE_WRITE8_MEMBER(rom2_bank_select_w);
50	57	};
51	58
52	59	static TILE_GET_INFO( get_tile_info )
r14845	r14846
120	127	return 0;
121	128	}
122	129
123		static READ8_HANDLER( suprgolf_videoram_r )
	130	READ8_MEMBER(suprgolf_state::suprgolf_videoram_r)
124	131	{
125		suprgolf_state *state = space->machine().driver_data<suprgolf_state>();
126	132
127		if (state->m_palette_switch)
128		return state->m_paletteram[offset];
	133	if (m_palette_switch)
	134	return m_paletteram[offset];
129	135	else
130		return state->m_videoram[offset];
	136	return m_videoram[offset];
131	137	}
132	138
133		static WRITE8_HANDLER( suprgolf_videoram_w )
	139	WRITE8_MEMBER(suprgolf_state::suprgolf_videoram_w)
134	140	{
135		suprgolf_state *state = space->machine().driver_data<suprgolf_state>();
136	141
137		if(state->m_palette_switch)
	142	if(m_palette_switch)
138	143	{
139	144	int r,g,b,datax;
140		state->m_paletteram[offset] = data;
	145	m_paletteram[offset] = data;
141	146	offset>>=1;
142		datax = state->m_paletteram[offset*2] + 256*state->m_paletteram[offset*2 + 1];
	147	datax = m_paletteram[offset*2] + 256*m_paletteram[offset*2 + 1];
143	148
144	149	b = (datax & 0x8000) ? 0 : ((datax)&0x001f)>>0;
145	150	g = (datax & 0x8000) ? 0 : ((datax)&0x03e0)>>5;
146	151	r = (datax & 0x8000) ? 0 : ((datax)&0x7c00)>>10;
147	152
148		palette_set_color_rgb(space->machine(), offset, pal5bit(r), pal5bit(g), pal5bit(b));
	153	palette_set_color_rgb(machine(), offset, pal5bit(r), pal5bit(g), pal5bit(b));
149	154	}
150	155	else
151	156	{
152		state->m_videoram[offset] = data;
153		state->m_tilemap->mark_tile_dirty((offset & 0x7fe) >> 1);
	157	m_videoram[offset] = data;
	158	m_tilemap->mark_tile_dirty((offset & 0x7fe) >> 1);
154	159	}
155	160	}
156	161
r14845	r14846
178	183	//  printf("Video regs with data %02x activated\n",data);
179	184	}
180	185
181		static READ8_HANDLER( suprgolf_bg_vram_r )
	186	READ8_MEMBER(suprgolf_state::suprgolf_bg_vram_r)
182	187	{
183		suprgolf_state *state = space->machine().driver_data<suprgolf_state>();
184	188
185		return state->m_bg_vram[offset+state->m_bg_bank*0x2000];
	189	return m_bg_vram[offset+m_bg_bank*0x2000];
186	190	}
187	191
188		static WRITE8_HANDLER( suprgolf_bg_vram_w )
	192	WRITE8_MEMBER(suprgolf_state::suprgolf_bg_vram_w)
189	193	{
190		suprgolf_state *state = space->machine().driver_data<suprgolf_state>();
191	194	UINT8 hi_nibble,lo_nibble;
192	195	UINT8 hi_dirty_dot,lo_dirty_dot; // helpers
193	196
r14845	r14846
198	201
199	202	if(hi_nibble == 0xf0)
200	203	{
201		hi_nibble = state->m_bg_vram[offset+state->m_bg_bank*0x2000] & 0xf0;
202		if(!(state->m_vreg_pen & 0x80) && (!(state->m_bg_bank & 0x10)))
	204	hi_nibble = m_bg_vram[offset+m_bg_bank*0x2000] & 0xf0;
	205	if(!(m_vreg_pen & 0x80) && (!(m_bg_bank & 0x10)))
203	206	hi_dirty_dot = 0;
204	207	}
205	208
206	209	if(lo_nibble == 0x0f)
207	210	{
208		lo_nibble = state->m_bg_vram[offset+state->m_bg_bank*0x2000] & 0x0f;
209		if(!(state->m_vreg_pen & 0x80) && (!(state->m_bg_bank & 0x10)))
	211	lo_nibble = m_bg_vram[offset+m_bg_bank*0x2000] & 0x0f;
	212	if(!(m_vreg_pen & 0x80) && (!(m_bg_bank & 0x10)))
210	213	lo_dirty_dot = 0;
211	214	}
212	215
213		if(state->m_vreg_pen & 0x80 || state->m_bg_bank & 0x10)
214		state->m_bg_vram[offset+state->m_bg_bank*0x2000] = data;
	216	if(m_vreg_pen & 0x80 || m_bg_bank & 0x10)
	217	m_bg_vram[offset+m_bg_bank*0x2000] = data;
215	218	else
216		state->m_bg_vram[offset+state->m_bg_bank*0x2000] = hi_nibble|lo_nibble;
	219	m_bg_vram[offset+m_bg_bank*0x2000] = hi_nibble|lo_nibble;
217	220
218		if(state->m_bg_bank & 0x10)
	221	if(m_bg_bank & 0x10)
219	222	{
220	223	if(hi_dirty_dot)
221		state->m_fg_fb[(offset+(state->m_bg_bank & 0x0f)*0x2000)*2+1] = (state->m_vreg_pen & 0x7f)<<4 | ((state->m_bg_vram[offset+state->m_bg_bank*0x2000] & 0xf0)>>4);
	224	m_fg_fb[(offset+(m_bg_bank & 0x0f)*0x2000)*2+1] = (m_vreg_pen & 0x7f)<<4 | ((m_bg_vram[offset+m_bg_bank*0x2000] & 0xf0)>>4);
222	225	if(lo_dirty_dot)
223		state->m_fg_fb[(offset+(state->m_bg_bank & 0x0f)*0x2000)*2+0] = (state->m_vreg_pen & 0x7f)<<4 | ((state->m_bg_vram[offset+state->m_bg_bank*0x2000] & 0x0f)>>0);
	226	m_fg_fb[(offset+(m_bg_bank & 0x0f)*0x2000)*2+0] = (m_vreg_pen & 0x7f)<<4 | ((m_bg_vram[offset+m_bg_bank*0x2000] & 0x0f)>>0);
224	227	}
225	228	else
226	229	{
227	230	if(hi_dirty_dot)
228		state->m_bg_fb[(offset+(state->m_bg_bank & 0x0f)*0x2000)*2+1] = (state->m_vreg_pen & 0x7f)<<4 | ((state->m_bg_vram[offset+state->m_bg_bank*0x2000] & 0xf0)>>4);
	231	m_bg_fb[(offset+(m_bg_bank & 0x0f)*0x2000)*2+1] = (m_vreg_pen & 0x7f)<<4 | ((m_bg_vram[offset+m_bg_bank*0x2000] & 0xf0)>>4);
229	232	if(lo_dirty_dot)
230		state->m_bg_fb[(offset+(state->m_bg_bank & 0x0f)*0x2000)*2+0] = (state->m_vreg_pen & 0x7f)<<4 | ((state->m_bg_vram[offset+state->m_bg_bank*0x2000] & 0x0f)>>0);
	233	m_bg_fb[(offset+(m_bg_bank & 0x0f)*0x2000)*2+0] = (m_vreg_pen & 0x7f)<<4 | ((m_bg_vram[offset+m_bg_bank*0x2000] & 0x0f)>>0);
231	234	}
232	235	}
233	236
234		static WRITE8_HANDLER( suprgolf_pen_w )
	237	WRITE8_MEMBER(suprgolf_state::suprgolf_pen_w)
235	238	{
236		suprgolf_state *state = space->machine().driver_data<suprgolf_state>();
237	239
238		state->m_vreg_pen = data;
	240	m_vreg_pen = data;
239	241	}
240	242
241		static WRITE8_HANDLER( adpcm_data_w )
	243	WRITE8_MEMBER(suprgolf_state::adpcm_data_w)
242	244	{
243		suprgolf_state *state = space->machine().driver_data<suprgolf_state>();
244	245
245		state->m_msm5205next = data;
	246	m_msm5205next = data;
246	247	}
247	248
248	249	static READ8_DEVICE_HANDLER( rom_bank_select_r )
r14845	r14846
268	269	flip_screen_set(device->machine(), data & 0x80);
269	270	}
270	271
271		static WRITE8_HANDLER( rom2_bank_select_w )
	272	WRITE8_MEMBER(suprgolf_state::rom2_bank_select_w)
272	273	{
273		UINT8 *region_base = space->machine().region("user2")->base();
274		//  mame_printf_debug("ROM_BANK 0x4000 - %X @%X\n",data,cpu_get_previouspc(&space->device()));
	274	UINT8 *region_base = machine().region("user2")->base();
	275	//  mame_printf_debug("ROM_BANK 0x4000 - %X @%X\n",data,cpu_get_previouspc(&space.device()));
275	276
276		memory_set_bankptr(space->machine(), "bank1", region_base + (data&0x0f) * 0x4000);
	277	memory_set_bankptr(machine(), "bank1", region_base + (data&0x0f) * 0x4000);
277	278
278	279	if(data & 0xf0)
279	280	printf("Rom bank select 2 with data %02x activated\n",data);
r14845	r14846
302	303	static ADDRESS_MAP_START( suprgolf_map, AS_PROGRAM, 8, suprgolf_state )
303	304	AM_RANGE(0x0000, 0x3fff) AM_ROM
304	305	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
305		AM_RANGE(0x4000, 0x4000) AM_WRITE_LEGACY(rom2_bank_select_w )
	306	AM_RANGE(0x4000, 0x4000) AM_WRITE(rom2_bank_select_w )
306	307	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank2")
307		AM_RANGE(0xc000, 0xdfff) AM_READWRITE_LEGACY(suprgolf_bg_vram_r, suprgolf_bg_vram_w ) // banked background vram
308		AM_RANGE(0xe000, 0xefff) AM_READWRITE_LEGACY(suprgolf_videoram_r, suprgolf_videoram_w ) AM_BASE(m_videoram) //foreground vram + paletteram
309		AM_RANGE(0xf000, 0xf000) AM_WRITE_LEGACY(suprgolf_pen_w )
	308	AM_RANGE(0xc000, 0xdfff) AM_READWRITE(suprgolf_bg_vram_r, suprgolf_bg_vram_w ) // banked background vram
	309	AM_RANGE(0xe000, 0xefff) AM_READWRITE(suprgolf_videoram_r, suprgolf_videoram_w ) AM_BASE(m_videoram) //foreground vram + paletteram
	310	AM_RANGE(0xf000, 0xf000) AM_WRITE(suprgolf_pen_w )
310	311	AM_RANGE(0xf800, 0xffff) AM_RAM
311	312	ADDRESS_MAP_END
312	313
r14845	r14846
315	316	AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("ppi8255_0", i8255_device, read, write)
316	317	AM_RANGE(0x04, 0x07) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
317	318	AM_RANGE(0x08, 0x09) AM_DEVREADWRITE_LEGACY("ymsnd", ym2203_r, ym2203_w)
318		AM_RANGE(0x0c, 0x0c) AM_WRITE_LEGACY(adpcm_data_w)
	319	AM_RANGE(0x0c, 0x0c) AM_WRITE(adpcm_data_w)
319	320	ADDRESS_MAP_END
320	321
321	322	static INPUT_PORTS_START( suprgolf )

src/mame/drivers/adp.c

r14845	r14846
175	175	/* devices */
176	176	device_t *m_maincpu;
177	177	device_t *m_duart;
	178	DECLARE_READ16_MEMBER(test_r);
	179	DECLARE_WRITE16_MEMBER(wh2_w);
	180	DECLARE_WRITE8_MEMBER(ramdac_io_w);
	181	DECLARE_READ8_MEMBER(h63484_rom_r);
178	182	};
179	183
180	184
r14845	r14846
376	380	}
377	381	}
378	382
379		static READ16_HANDLER( test_r )
	383	READ16_MEMBER(adp_state::test_r)
380	384	{
381		adp_state *state = space->machine().driver_data<adp_state>();
382	385	int value = 0xffff;
383	386
384		switch (state->m_mux_data)
	387	switch (m_mux_data)
385	388	{
386		case 0x00: value = input_port_read(space->machine(), "x0"); break;
387		case 0x01: value = input_port_read(space->machine(), "x1"); break;
388		case 0x02: value = input_port_read(space->machine(), "x2"); break;
389		case 0x03: value = input_port_read(space->machine(), "1P_UP"); break;
390		case 0x04: value = input_port_read(space->machine(), "1P_B1"); break;
391		case 0x05: value = input_port_read(space->machine(), "x5"); break;
392		case 0x06: value = input_port_read(space->machine(), "1P_RIGHT"); break;
393		case 0x07: value = input_port_read(space->machine(), "1P_DOWN"); break;
394		case 0x08: value = input_port_read(space->machine(), "1P_LEFT"); break;
395		case 0x09: value = input_port_read(space->machine(), "x9"); break;
396		case 0x0a: value = input_port_read(space->machine(), "x10"); break;
397		case 0x0b: value = input_port_read(space->machine(), "x11"); break;
398		case 0x0c: value = input_port_read(space->machine(), "x12"); break;
399		case 0x0d: value = input_port_read(space->machine(), "x13"); break;
400		case 0x0e: value = input_port_read(space->machine(), "1P_START"); break;
401		case 0x0f: value = input_port_read(space->machine(), "1P_COIN"); break;
	389	case 0x00: value = input_port_read(machine(), "x0"); break;
	390	case 0x01: value = input_port_read(machine(), "x1"); break;
	391	case 0x02: value = input_port_read(machine(), "x2"); break;
	392	case 0x03: value = input_port_read(machine(), "1P_UP"); break;
	393	case 0x04: value = input_port_read(machine(), "1P_B1"); break;
	394	case 0x05: value = input_port_read(machine(), "x5"); break;
	395	case 0x06: value = input_port_read(machine(), "1P_RIGHT"); break;
	396	case 0x07: value = input_port_read(machine(), "1P_DOWN"); break;
	397	case 0x08: value = input_port_read(machine(), "1P_LEFT"); break;
	398	case 0x09: value = input_port_read(machine(), "x9"); break;
	399	case 0x0a: value = input_port_read(machine(), "x10"); break;
	400	case 0x0b: value = input_port_read(machine(), "x11"); break;
	401	case 0x0c: value = input_port_read(machine(), "x12"); break;
	402	case 0x0d: value = input_port_read(machine(), "x13"); break;
	403	case 0x0e: value = input_port_read(machine(), "1P_START"); break;
	404	case 0x0f: value = input_port_read(machine(), "1P_COIN"); break;
402	405	}
403	406
404		state->m_mux_data++;
405		state->m_mux_data &= 0xf;
	407	m_mux_data++;
	408	m_mux_data &= 0xf;
406	409	/*
407		switch (space->machine().rand() & 3)
	410	switch (machine().rand() & 3)
408	411	{
409	412	case 0:
410	413	return 0;
411	414	case 1:
412	415	return 0xffff;
413	416	default:
414		return space->machine().rand() & 0xffff;
	417	return machine().rand() & 0xffff;
415	418	}
416	419	*/
417		return value | (space->machine().rand() & 0x0000);
	420	return value | (machine().rand() & 0x0000);
418	421	}
419	422
420	423	/*???*/
421		static WRITE16_HANDLER(wh2_w)
	424	WRITE16_MEMBER(adp_state::wh2_w)
422	425	{
423		adp_state *state = space->machine().driver_data<adp_state>();
424		state->m_register_active = data;
	426	m_register_active = data;
425	427	}
426	428
427	429	static READ8_DEVICE_HANDLER(t2_r)
r14845	r14846
447	449	AM_RANGE(0x000000, 0x0fffff) AM_ROM
448	450	AM_RANGE(0x800080, 0x800081) AM_DEVREADWRITE("h63484", h63484_device, status_r, address_w)
449	451	AM_RANGE(0x800082, 0x800083) AM_DEVREADWRITE("h63484", h63484_device, data_r, data_w)
450		AM_RANGE(0x800100, 0x800101) AM_READWRITE_LEGACY(test_r,wh2_w) //related to input
	452	AM_RANGE(0x800100, 0x800101) AM_READWRITE(test_r,wh2_w) //related to input
451	453	AM_RANGE(0x800140, 0x800143) AM_DEVREADWRITE8_LEGACY("aysnd", ay8910_r, ay8910_address_data_w, 0x00ff) //18b too
452	454	AM_RANGE(0x800180, 0x80019f) AM_DEVREADWRITE8_LEGACY("duart68681", duart68681_r, duart68681_w, 0xff )
453	455	AM_RANGE(0xffc000, 0xffffff) AM_RAM
r14845	r14846
472	474	AM_RANGE(0x600006, 0x600007) AM_NOP //(r) is discarded (watchdog?)
473	475	ADDRESS_MAP_END
474	476
475		static WRITE8_HANDLER( ramdac_io_w )
	477	WRITE8_MEMBER(adp_state::ramdac_io_w)
476	478	{
477		adp_state *state = space->machine().driver_data<adp_state>();
478	479	switch(offset)
479	480	{
480	481	case 0:
481		state->m_pal.offs = data;
482		state->m_pal.offs_internal = 0;
	482	m_pal.offs = data;
	483	m_pal.offs_internal = 0;
483	484	break;
484	485	case 2:
485	486	//mask pen reg
486	487	break;
487	488	case 1:
488		switch(state->m_pal.offs_internal)
	489	switch(m_pal.offs_internal)
489	490	{
490	491	case 0:
491		state->m_pal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
492		state->m_pal.offs_internal++;
	492	m_pal.r = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	493	m_pal.offs_internal++;
493	494	break;
494	495	case 1:
495		state->m_pal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
496		state->m_pal.offs_internal++;
	496	m_pal.g = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	497	m_pal.offs_internal++;
497	498	break;
498	499	case 2:
499		state->m_pal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
500		palette_set_color(space->machine(), state->m_pal.offs, MAKE_RGB(state->m_pal.r, state->m_pal.g, state->m_pal.b));
501		state->m_pal.offs_internal = 0;
502		state->m_pal.offs++;
503		state->m_pal.offs&=0xff;
	500	m_pal.b = ((data & 0x3f) << 2) | ((data & 0x30) >> 4);
	501	palette_set_color(machine(), m_pal.offs, MAKE_RGB(m_pal.r, m_pal.g, m_pal.b));
	502	m_pal.offs_internal = 0;
	503	m_pal.offs++;
	504	m_pal.offs&=0xff;
504	505	break;
505	506	}
506	507
r14845	r14846
512	513	AM_RANGE(0x000000, 0x0fffff) AM_ROM
513	514	AM_RANGE(0x800080, 0x800081) AM_DEVREADWRITE("h63484", h63484_device, status_r, address_w)
514	515	AM_RANGE(0x800082, 0x800083) AM_DEVREADWRITE("h63484", h63484_device, data_r, data_w)
515		AM_RANGE(0x800088, 0x80008d) AM_WRITE8_LEGACY(ramdac_io_w, 0x00ff)
	516	AM_RANGE(0x800088, 0x80008d) AM_WRITE8(ramdac_io_w, 0x00ff)
516	517	AM_RANGE(0x800100, 0x800101) AM_RAM //???
517	518	AM_RANGE(0x800140, 0x800143) AM_DEVREADWRITE8_LEGACY("aysnd", ay8910_r, ay8910_address_data_w, 0x00ff) //18b too
518	519	AM_RANGE(0x800180, 0x80019f) AM_DEVREADWRITE8_LEGACY("duart68681", duart68681_r, duart68681_w, 0xff )
r14845	r14846
634	635	DEVCB_NULL
635	636	};
636	637
637		static READ8_HANDLER( h63484_rom_r )
	638	READ8_MEMBER(adp_state::h63484_rom_r)
638	639	{
639		UINT8 *rom = space->machine().region("gfx1")->base();
	640	UINT8 *rom = machine().region("gfx1")->base();
640	641
641	642	return rom[offset];
642	643	}
643	644
644	645	static ADDRESS_MAP_START( adp_h63484_map, AS_0, 8, adp_state )
645	646	AM_RANGE(0x00000, 0x7ffff) AM_DEVREADWRITE("h63484",h63484_device, vram_r,vram_w)
646		AM_RANGE(0x80000, 0xbffff) AM_READ_LEGACY(h63484_rom_r)
	647	AM_RANGE(0x80000, 0xbffff) AM_READ(h63484_rom_r)
647	648	ADDRESS_MAP_END
648	649
649	650	static ADDRESS_MAP_START( fashiong_h63484_map, AS_0, 8, adp_state )

src/mame/drivers/kas89.c

r14845	r14846
218	218	device_t *m_audiocpu;
219	219
220	220	required_device<v9938_device> m_v9938;
	221	DECLARE_WRITE8_MEMBER(mux_w);
	222	DECLARE_READ8_MEMBER(mux_r);
	223	DECLARE_WRITE8_MEMBER(control_w);
	224	DECLARE_WRITE8_MEMBER(sound_comm_w);
	225	DECLARE_WRITE8_MEMBER(int_ack_w);
	226	DECLARE_WRITE8_MEMBER(led_mux_data_w);
	227	DECLARE_WRITE8_MEMBER(led_mux_select_w);
221	228	};
222	229
223	230	#define VDP_MEM             0x40000
r14845	r14846
267	274	*  Input Ports Demux & Common Routines  *
268	275	****************************************/
269	276
270		static WRITE8_HANDLER( mux_w )
	277	WRITE8_MEMBER(kas89_state::mux_w)
271	278	{
272	279	/*  - bits -
273	280	7654 3210
r14845	r14846
275	282
276	283	Writes: 1-2-4-8-10-20-40-3f. Only 80 (for DSW) at very begining...
277	284	*/
278		kas89_state *state = space->machine().driver_data<kas89_state>();
279		state->m_mux_data = data;
	285
	286	m_mux_data = data;
280	287	}
281	288
282		static READ8_HANDLER( mux_r )
	289	READ8_MEMBER(kas89_state::mux_r)
283	290	{
284		kas89_state *state = space->machine().driver_data<kas89_state>();
285		switch(state->m_mux_data)
	291	switch(m_mux_data)
286	292	{
287		case 0x01: return input_port_read(space->machine(), "PL1");
288		case 0x02: return input_port_read(space->machine(), "PL2");
289		case 0x04: return input_port_read(space->machine(), "PL3");
290		case 0x08: return input_port_read(space->machine(), "PL4");
291		case 0x10: return input_port_read(space->machine(), "PL5");
292		case 0x20: return input_port_read(space->machine(), "PL6");
	293	case 0x01: return input_port_read(machine(), "PL1");
	294	case 0x02: return input_port_read(machine(), "PL2");
	295	case 0x04: return input_port_read(machine(), "PL3");
	296	case 0x08: return input_port_read(machine(), "PL4");
	297	case 0x10: return input_port_read(machine(), "PL5");
	298	case 0x20: return input_port_read(machine(), "PL6");
293	299	case 0x40:
294	300	{
295		output_set_lamp_value(37, 1 - ((input_port_read(space->machine(), "SVC") >> 5) & 1));   /* Operator Key LAMP */
296		return input_port_read(space->machine(), "SVC");
	301	output_set_lamp_value(37, 1 - ((input_port_read(machine(), "SVC") >> 5) & 1));   /* Operator Key LAMP */
	302	return input_port_read(machine(), "SVC");
297	303	}
298		case 0x80: return input_port_read(space->machine(), "DSW");   /* Polled at $162a through NMI routine */
299		case 0x3f: return input_port_read(space->machine(), "UNK");
	304	case 0x80: return input_port_read(machine(), "DSW");   /* Polled at $162a through NMI routine */
	305	case 0x3f: return input_port_read(machine(), "UNK");
300	306	}
301	307
302		logerror("Mux_data %02X\n", state->m_mux_data);
303		return state->m_mux_data;
	308	logerror("Mux_data %02X\n", m_mux_data);
	309	return m_mux_data;
304	310	}
305	311
306	312	static TIMER_DEVICE_CALLBACK ( kas89_nmi_cb )
r14845	r14846
319	325	}
320	326
321	327
322		static WRITE8_HANDLER( control_w )
	328	WRITE8_MEMBER(kas89_state::control_w)
323	329	{
324	330	/*  - bits -
325	331	7654 3210
r14845	r14846
329	335	-x-- ----   NMI enable. Active high.
330	336	x-xx x---   Unused.
331	337	*/
332		kas89_state *state = space->machine().driver_data<kas89_state>();
333		state->m_main_nmi_enable = data & 0x40;
334	338
335		coin_counter_w(space->machine(), 0, (data ^ 0xff) & 0x01);   /* Credits In counter */
336		coin_counter_w(space->machine(), 1, (data ^ 0xff) & 0x02);   /* Credits Out counter */
	339	m_main_nmi_enable = data & 0x40;
	340
	341	coin_counter_w(machine(), 0, (data ^ 0xff) & 0x01);   /* Credits In counter */
	342	coin_counter_w(machine(), 1, (data ^ 0xff) & 0x02);   /* Credits Out counter */
337	343	}
338	344
339		static WRITE8_HANDLER( sound_comm_w )
	345	WRITE8_MEMBER(kas89_state::sound_comm_w)
340	346	{
341	347	/*  This port is used mainly for sound latch, but bit6 activates a
342	348	sort of output port (maybe for a sign?)
r14845	r14846
351	357	is written to the outport... (maybe to clear the possible sign).
352	358
353	359	*/
354		kas89_state *state = space->machine().driver_data<kas89_state>();
355	360
	361
356	362	if (data & 0x40)
357	363	{
358		state->m_outdata = (data ^ 0x40);   /* Pure data. Without the activator bit */
	364	m_outdata = (data ^ 0x40);   /* Pure data. Without the activator bit */
359	365
360		if (state->m_outdata == 0x3f)
	366	if (m_outdata == 0x3f)
361	367	{
362	368	UINT8 i;
363	369	for ( i = 0; i < 37; i++ )
r14845	r14846
366	372	}
367	373	}
368	374
369		logerror("Outdata: Write %02x\n", state->m_outdata);
	375	logerror("Outdata: Write %02x\n", m_outdata);
370	376	}
371	377
372	378	else
373	379	{
374	380	soundlatch_w(space, 0, data);
375		device_set_input_line(state->m_audiocpu, 0, ASSERT_LINE );
	381	device_set_input_line(m_audiocpu, 0, ASSERT_LINE );
376	382	}
377	383	}
378	384
379		static WRITE8_HANDLER( int_ack_w )
	385	WRITE8_MEMBER(kas89_state::int_ack_w)
380	386	{
381		kas89_state *state = space->machine().driver_data<kas89_state>();
382		device_set_input_line(state->m_audiocpu, 0, CLEAR_LINE );
	387	device_set_input_line(m_audiocpu, 0, CLEAR_LINE );
383	388	}
384	389
385	390
r14845	r14846
387	392	*   Output Ports Demux & LEDs Support   *
388	393	****************************************/
389	394
390		static WRITE8_HANDLER( led_mux_data_w )
	395	WRITE8_MEMBER(kas89_state::led_mux_data_w)
391	396	{
392	397	/*  - bits -
393	398	7654 3210
394	399	xxxx xxxx   LEDs data.
395	400	*/
396		kas89_state *state = space->machine().driver_data<kas89_state>();
397		state->m_leds_mux_data = data;
	401
	402	m_leds_mux_data = data;
398	403	}
399	404
400		static WRITE8_HANDLER( led_mux_select_w )
	405	WRITE8_MEMBER(kas89_state::led_mux_select_w)
401	406	{
402	407	/*  - bits -
403	408	7654 3210
404	409	---x xxxx   LEDs Set selector.
405	410	*/
406		kas89_state *state = space->machine().driver_data<kas89_state>();
407		state->m_leds_mux_selector = data;
408	411
	412	m_leds_mux_selector = data;
	413
409	414	UINT8 i;
410	415	for ( i = 0; i < 37; i++ )
411	416	{
r14845	r14846
424	429
425	430	case 0x01:
426	431	{
427		output_set_lamp_value(11, (state->m_leds_mux_data >> 0) & 1);   /* Number 11 LED */
428		output_set_lamp_value(36, (state->m_leds_mux_data >> 1) & 1);   /* Number 36 LED */
429		output_set_lamp_value(13, (state->m_leds_mux_data >> 2) & 1);   /* Number 13 LED */
430		output_set_lamp_value(27, (state->m_leds_mux_data >> 3) & 1);   /* Number 27 LED */
431		output_set_lamp_value(06, (state->m_leds_mux_data >> 4) & 1);   /* Number  6 LED */
432		output_set_lamp_value(34, (state->m_leds_mux_data >> 5) & 1);   /* Number 34 LED */
433		output_set_lamp_value(17, (state->m_leds_mux_data >> 6) & 1);   /* Number 17 LED */
434		output_set_lamp_value(25, (state->m_leds_mux_data >> 7) & 1);   /* Number 25 LED */
	432	output_set_lamp_value(11, (m_leds_mux_data >> 0) & 1);   /* Number 11 LED */
	433	output_set_lamp_value(36, (m_leds_mux_data >> 1) & 1);   /* Number 36 LED */
	434	output_set_lamp_value(13, (m_leds_mux_data >> 2) & 1);   /* Number 13 LED */
	435	output_set_lamp_value(27, (m_leds_mux_data >> 3) & 1);   /* Number 27 LED */
	436	output_set_lamp_value(06, (m_leds_mux_data >> 4) & 1);   /* Number  6 LED */
	437	output_set_lamp_value(34, (m_leds_mux_data >> 5) & 1);   /* Number 34 LED */
	438	output_set_lamp_value(17, (m_leds_mux_data >> 6) & 1);   /* Number 17 LED */
	439	output_set_lamp_value(25, (m_leds_mux_data >> 7) & 1);   /* Number 25 LED */
435	440	break;
436	441	}
437	442
438	443	case 0x02:
439	444	{
440		output_set_lamp_value( 2, (state->m_leds_mux_data >> 0) & 1);   /* Number  2 LED */
441		output_set_lamp_value(21, (state->m_leds_mux_data >> 1) & 1);   /* Number 21 LED */
442		output_set_lamp_value( 4, (state->m_leds_mux_data >> 2) & 1);   /* Number  4 LED */
443		output_set_lamp_value(19, (state->m_leds_mux_data >> 3) & 1);   /* Number 19 LED */
444		output_set_lamp_value(15, (state->m_leds_mux_data >> 4) & 1);   /* Number 15 LED */
445		output_set_lamp_value(32, (state->m_leds_mux_data >> 5) & 1);   /* Number 32 LED */
446		output_set_lamp_value( 0, (state->m_leds_mux_data >> 6) & 1);   /* Number  0 LED */
447		output_set_lamp_value(26, (state->m_leds_mux_data >> 7) & 1);   /* Number 26 LED */
	445	output_set_lamp_value( 2, (m_leds_mux_data >> 0) & 1);   /* Number  2 LED */
	446	output_set_lamp_value(21, (m_leds_mux_data >> 1) & 1);   /* Number 21 LED */
	447	output_set_lamp_value( 4, (m_leds_mux_data >> 2) & 1);   /* Number  4 LED */
	448	output_set_lamp_value(19, (m_leds_mux_data >> 3) & 1);   /* Number 19 LED */
	449	output_set_lamp_value(15, (m_leds_mux_data >> 4) & 1);   /* Number 15 LED */
	450	output_set_lamp_value(32, (m_leds_mux_data >> 5) & 1);   /* Number 32 LED */
	451	output_set_lamp_value( 0, (m_leds_mux_data >> 6) & 1);   /* Number  0 LED */
	452	output_set_lamp_value(26, (m_leds_mux_data >> 7) & 1);   /* Number 26 LED */
448	453	break;
449	454	}
450	455
451	456	case 0x04:
452	457	{
453		output_set_lamp_value( 3, (state->m_leds_mux_data >> 0) & 1);   /* Number  3 LED */
454		output_set_lamp_value(35, (state->m_leds_mux_data >> 1) & 1);   /* Number 35 LED */
455		output_set_lamp_value(12, (state->m_leds_mux_data >> 2) & 1);   /* Number 12 LED */
456		output_set_lamp_value(28, (state->m_leds_mux_data >> 3) & 1);   /* Number 28 LED */
457		output_set_lamp_value( 7, (state->m_leds_mux_data >> 4) & 1);   /* Number  7 LED */
458		output_set_lamp_value(29, (state->m_leds_mux_data >> 5) & 1);   /* Number 29 LED */
459		output_set_lamp_value(18, (state->m_leds_mux_data >> 6) & 1);   /* Number 18 LED */
	458	output_set_lamp_value( 3, (m_leds_mux_data >> 0) & 1);   /* Number  3 LED */
	459	output_set_lamp_value(35, (m_leds_mux_data >> 1) & 1);   /* Number 35 LED */
	460	output_set_lamp_value(12, (m_leds_mux_data >> 2) & 1);   /* Number 12 LED */
	461	output_set_lamp_value(28, (m_leds_mux_data >> 3) & 1);   /* Number 28 LED */
	462	output_set_lamp_value( 7, (m_leds_mux_data >> 4) & 1);   /* Number  7 LED */
	463	output_set_lamp_value(29, (m_leds_mux_data >> 5) & 1);   /* Number 29 LED */
	464	output_set_lamp_value(18, (m_leds_mux_data >> 6) & 1);   /* Number 18 LED */
460	465	break;
461	466	}
462	467
463	468	case 0x08:
464	469	{
465		output_set_lamp_value(22, (state->m_leds_mux_data >> 0) & 1);   /* Number 22 LED */
466		output_set_lamp_value( 9, (state->m_leds_mux_data >> 1) & 1);   /* Number  9 LED */
467		output_set_lamp_value(31, (state->m_leds_mux_data >> 2) & 1);   /* Number 31 LED */
468		output_set_lamp_value(14, (state->m_leds_mux_data >> 3) & 1);   /* Number 14 LED */
469		output_set_lamp_value(20, (state->m_leds_mux_data >> 4) & 1);   /* Number 20 LED */
470		output_set_lamp_value( 1, (state->m_leds_mux_data >> 5) & 1);   /* Number  1 LED */
471		output_set_lamp_value(33, (state->m_leds_mux_data >> 6) & 1);   /* Number 33 LED */
	470	output_set_lamp_value(22, (m_leds_mux_data >> 0) & 1);   /* Number 22 LED */
	471	output_set_lamp_value( 9, (m_leds_mux_data >> 1) & 1);   /* Number  9 LED */
	472	output_set_lamp_value(31, (m_leds_mux_data >> 2) & 1);   /* Number 31 LED */
	473	output_set_lamp_value(14, (m_leds_mux_data >> 3) & 1);   /* Number 14 LED */
	474	output_set_lamp_value(20, (m_leds_mux_data >> 4) & 1);   /* Number 20 LED */
	475	output_set_lamp_value( 1, (m_leds_mux_data >> 5) & 1);   /* Number  1 LED */
	476	output_set_lamp_value(33, (m_leds_mux_data >> 6) & 1);   /* Number 33 LED */
472	477	break;
473	478	}
474	479
475	480	case 0x10:
476	481	{
477		output_set_lamp_value(16, (state->m_leds_mux_data >> 0) & 1);   /* Number 16 LED */
478		output_set_lamp_value(24, (state->m_leds_mux_data >> 1) & 1);   /* Number 24 LED */
479		output_set_lamp_value( 5, (state->m_leds_mux_data >> 2) & 1);   /* Number  5 LED */
480		output_set_lamp_value(10, (state->m_leds_mux_data >> 3) & 1);   /* Number 10 LED */
481		output_set_lamp_value(23, (state->m_leds_mux_data >> 4) & 1);   /* Number 23 LED */
482		output_set_lamp_value( 8, (state->m_leds_mux_data >> 5) & 1);   /* Number  8 LED */
483		output_set_lamp_value(30, (state->m_leds_mux_data >> 6) & 1);   /* Number 30 LED */
	482	output_set_lamp_value(16, (m_leds_mux_data >> 0) & 1);   /* Number 16 LED */
	483	output_set_lamp_value(24, (m_leds_mux_data >> 1) & 1);   /* Number 24 LED */
	484	output_set_lamp_value( 5, (m_leds_mux_data >> 2) & 1);   /* Number  5 LED */
	485	output_set_lamp_value(10, (m_leds_mux_data >> 3) & 1);   /* Number 10 LED */
	486	output_set_lamp_value(23, (m_leds_mux_data >> 4) & 1);   /* Number 23 LED */
	487	output_set_lamp_value( 8, (m_leds_mux_data >> 5) & 1);   /* Number  8 LED */
	488	output_set_lamp_value(30, (m_leds_mux_data >> 6) & 1);   /* Number 30 LED */
484	489	break;
485	490	}
486	491
r14845	r14846
517	522	static ADDRESS_MAP_START( kas89_io, AS_IO, 8, kas89_state )
518	523	ADDRESS_MAP_GLOBAL_MASK(0xff)
519	524	AM_RANGE(0x40, 0x43) AM_DEVREADWRITE("v9938", v9938_device, read, write)
520		AM_RANGE(0x80, 0x80) AM_WRITE_LEGACY(mux_w)
521		AM_RANGE(0x81, 0x81) AM_READ_LEGACY(mux_r)
522		AM_RANGE(0x82, 0x82) AM_WRITE_LEGACY(control_w)   /* Bit6 trigger the 138Hz osc. tied to main Z80's NMI.*/
523		AM_RANGE(0x83, 0x83) AM_WRITE_LEGACY(led_mux_data_w)
524		AM_RANGE(0x84, 0x84) AM_WRITE_LEGACY(led_mux_select_w)
525		AM_RANGE(0x85, 0x85) AM_WRITE_LEGACY(sound_comm_w)
	525	AM_RANGE(0x80, 0x80) AM_WRITE(mux_w)
	526	AM_RANGE(0x81, 0x81) AM_READ(mux_r)
	527	AM_RANGE(0x82, 0x82) AM_WRITE(control_w)   /* Bit6 trigger the 138Hz osc. tied to main Z80's NMI.*/
	528	AM_RANGE(0x83, 0x83) AM_WRITE(led_mux_data_w)
	529	AM_RANGE(0x84, 0x84) AM_WRITE(led_mux_select_w)
	530	AM_RANGE(0x85, 0x85) AM_WRITE(sound_comm_w)
526	531	ADDRESS_MAP_END
527	532
528	533	/*
r14845	r14846
570	575
571	576	static ADDRESS_MAP_START( audio_io, AS_IO, 8, kas89_state )
572	577	ADDRESS_MAP_GLOBAL_MASK(0xff)
573		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(int_ack_w)   // comm out (1st Z80). seems to write here the value previously read through soundlatch (port 0x02).
	578	AM_RANGE(0x00, 0x00) AM_WRITE(int_ack_w)   // comm out (1st Z80). seems to write here the value previously read through soundlatch (port 0x02).
574	579	AM_RANGE(0x02, 0x02) AM_READ_LEGACY(soundlatch_r)
575	580	AM_RANGE(0x04, 0x04) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
576	581	AM_RANGE(0x04, 0x05) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)

src/mame/drivers/dmndrby.c

r14845	r14846
70	70	tilemap_t *m_racetrack_tilemap;
71	71	UINT8 m_io_port[8];
72	72	int m_bg;
	73	DECLARE_WRITE8_MEMBER(dderby_sound_w);
	74	DECLARE_READ8_MEMBER(input_r);
	75	DECLARE_WRITE8_MEMBER(output_w);
73	76	};
74	77
75	78
76		static WRITE8_HANDLER( dderby_sound_w )
	79	WRITE8_MEMBER(dmndrby_state::dderby_sound_w)
77	80	{
78	81	soundlatch_w(space,0,data);
79		cputag_set_input_line(space->machine(), "audiocpu", 0, HOLD_LINE);
	82	cputag_set_input_line(machine(), "audiocpu", 0, HOLD_LINE);
80	83	}
81	84
82	85
83		static READ8_HANDLER( input_r )
	86	READ8_MEMBER(dmndrby_state::input_r)
84	87	{
85	88	switch(offset & 7)
86	89	{
87		case 0: return input_port_read(space->machine(), "IN0");
88		case 1: return input_port_read(space->machine(), "IN1");
89		case 2: return input_port_read(space->machine(), "IN2");
90		case 3: return input_port_read(space->machine(), "IN3");
91		case 4: return input_port_read(space->machine(), "IN4");
92		case 5: return input_port_read(space->machine(), "IN5");
93		case 6: return input_port_read(space->machine(), "IN6");
94		case 7: return input_port_read(space->machine(), "IN7");
	90	case 0: return input_port_read(machine(), "IN0");
	91	case 1: return input_port_read(machine(), "IN1");
	92	case 2: return input_port_read(machine(), "IN2");
	93	case 3: return input_port_read(machine(), "IN3");
	94	case 4: return input_port_read(machine(), "IN4");
	95	case 5: return input_port_read(machine(), "IN5");
	96	case 6: return input_port_read(machine(), "IN6");
	97	case 7: return input_port_read(machine(), "IN7");
95	98	}
96	99
97	100	return 0xff;
98	101	}
99	102
100		static WRITE8_HANDLER( output_w )
	103	WRITE8_MEMBER(dmndrby_state::output_w)
101	104	{
102		dmndrby_state *state = space->machine().driver_data<dmndrby_state>();
103	105	/*
104	106	---- x--- refill meter [4]
105	107	---- x--- token out meter [5]
r14845	r14846
111	113	---- --x- coin lockout [0-3]
112	114	---- ---x lamp [0-6]
113	115	*/
114		state->m_io_port[offset] = data;
115		//  popmessage("%02x|%02x|%02x|%02x|%02x|%02x|%02x|%02x|",state->m_io_port[0],state->m_io_port[1],state->m_io_port[2],state->m_io_port[3],state->m_io_port[4],state->m_io_port[5],state->m_io_port[6],state->m_io_port[7]);
	116	m_io_port[offset] = data;
	117	//  popmessage("%02x|%02x|%02x|%02x|%02x|%02x|%02x|%02x|",m_io_port[0],m_io_port[1],m_io_port[2],m_io_port[3],m_io_port[4],m_io_port[5],m_io_port[6],m_io_port[7]);
116	118	}
117	119
118	120	static ADDRESS_MAP_START( memmap, AS_PROGRAM, 8, dmndrby_state )
119	121	AM_RANGE(0x0000, 0x5fff) AM_ROM
120	122	AM_RANGE(0x8000, 0x8fff) AM_RAM AM_SHARE("nvram")
121		AM_RANGE(0xc000, 0xc007) AM_READ_LEGACY(input_r)
122		AM_RANGE(0xc000, 0xc007) AM_WRITE_LEGACY(output_w)
	123	AM_RANGE(0xc000, 0xc007) AM_READ(input_r)
	124	AM_RANGE(0xc000, 0xc007) AM_WRITE(output_w)
123	125	AM_RANGE(0xc802, 0xc802) AM_READ_PORT("DSW1")
124	126	AM_RANGE(0xc803, 0xc803) AM_READ_PORT("DSW2")
125	127	AM_RANGE(0xca00, 0xca00) AM_WRITENOP//(vblank_irq_w) //???
126	128	AM_RANGE(0xca01, 0xca01) AM_WRITENOP //watchdog
127		AM_RANGE(0xca02, 0xca02) AM_RAM_WRITE_LEGACY(dderby_sound_w)
	129	AM_RANGE(0xca02, 0xca02) AM_RAM_WRITE(dderby_sound_w)
128	130	AM_RANGE(0xca03, 0xca03) AM_WRITENOP//(timer_irq_w) //???
129	131	AM_RANGE(0xcc00, 0xcc05) AM_RAM AM_BASE(m_scroll_ram)
130	132	AM_RANGE(0xce08, 0xce1f) AM_RAM AM_BASE(m_sprite_ram) // horse sprites

src/mame/drivers/cmmb.c

r14845	r14846
53	53
54	54	UINT8 *m_videoram;
55	55	UINT8 m_irq_mask;
	56	DECLARE_READ8_MEMBER(cmmb_charram_r);
	57	DECLARE_WRITE8_MEMBER(cmmb_charram_w);
	58	DECLARE_WRITE8_MEMBER(cmmb_paletteram_w);
	59	DECLARE_READ8_MEMBER(cmmb_input_r);
	60	DECLARE_WRITE8_MEMBER(cmmb_output_w);
	61	DECLARE_READ8_MEMBER(kludge_r);
56	62	};
57	63
58	64
r14845	r14846
86	92	return 0;
87	93	}
88	94
89		static READ8_HANDLER( cmmb_charram_r )
	95	READ8_MEMBER(cmmb_state::cmmb_charram_r)
90	96	{
91		UINT8 *GFX = space->machine().region("gfx")->base();
	97	UINT8 *GFX = machine().region("gfx")->base();
92	98
93	99	return GFX[offset];
94	100	}
95	101
96		static WRITE8_HANDLER( cmmb_charram_w )
	102	WRITE8_MEMBER(cmmb_state::cmmb_charram_w)
97	103	{
98		UINT8 *GFX = space->machine().region("gfx")->base();
	104	UINT8 *GFX = machine().region("gfx")->base();
99	105
100	106	GFX[offset] = data;
101	107
102	108	offset&=0xfff;
103	109
104	110	/* dirty char */
105		gfx_element_mark_dirty(space->machine().gfx[0], offset >> 4);
106		gfx_element_mark_dirty(space->machine().gfx[1], offset >> 5);
	111	gfx_element_mark_dirty(machine().gfx[0], offset >> 4);
	112	gfx_element_mark_dirty(machine().gfx[1], offset >> 5);
107	113	}
108	114
109	115
110		static WRITE8_HANDLER( cmmb_paletteram_w )
	116	WRITE8_MEMBER(cmmb_state::cmmb_paletteram_w)
111	117	{
112	118	/* RGB output is inverted */
113	119	paletteram_RRRGGGBB_w(space,offset,~data);
114	120	}
115	121
116		static READ8_HANDLER( cmmb_input_r )
	122	READ8_MEMBER(cmmb_state::cmmb_input_r)
117	123	{
118	124	//printf("%02x R\n",offset);
119	125	switch(offset)
120	126	{
121		case 0x00: return input_port_read(space->machine(), "IN2");
	127	case 0x00: return input_port_read(machine(), "IN2");
122	128	case 0x03: return 4; //eeprom?
123		case 0x0e: return input_port_read(space->machine(), "IN0");
124		case 0x0f: return input_port_read(space->machine(), "IN1");
	129	case 0x0e: return input_port_read(machine(), "IN0");
	130	case 0x0f: return input_port_read(machine(), "IN1");
125	131	}
126	132
127	133	return 0xff;
r14845	r14846
138	144	}
139	145	*/
140	146
141		static WRITE8_HANDLER( cmmb_output_w )
	147	WRITE8_MEMBER(cmmb_state::cmmb_output_w)
142	148	{
143		cmmb_state *state = space->machine().driver_data<cmmb_state>();
144	149	//printf("%02x -> [%02x] W\n",data,offset);
145	150	switch(offset)
146	151	{
147	152	case 0x01:
148	153	{
149		UINT8 *ROM = space->machine().region("maincpu")->base();
	154	UINT8 *ROM = machine().region("maincpu")->base();
150	155	UINT32 bankaddress;
151	156
152	157	bankaddress = 0x1c000 + (0x10000 * (data & 0x03));
153		memory_set_bankptr(space->machine(), "bank1", &ROM[bankaddress]);
	158	memory_set_bankptr(machine(), "bank1", &ROM[bankaddress]);
154	159	}
155	160	break;
156	161	case 0x03:
157		state->m_irq_mask = data & 0x80;
	162	m_irq_mask = data & 0x80;
158	163	break;
159	164	case 0x07:
160	165	break;
161	166	}
162	167	}
163	168
164		static READ8_HANDLER( kludge_r )
	169	READ8_MEMBER(cmmb_state::kludge_r)
165	170	{
166		return space->machine().rand();
	171	return machine().rand();
167	172	}
168	173
169	174	/* overlap empty addresses */
r14845	r14846
172	177	AM_RANGE(0x0000, 0x01ff) AM_RAM /* zero page address */
173	178	//  AM_RANGE(0x13c0, 0x13ff) AM_RAM //spriteram
174	179	AM_RANGE(0x1000, 0x13ff) AM_RAM AM_BASE(m_videoram)
175		AM_RANGE(0x2480, 0x249f) AM_RAM_WRITE_LEGACY(cmmb_paletteram_w) AM_BASE_GENERIC(paletteram)
176		AM_RANGE(0x4000, 0x400f) AM_READWRITE_LEGACY(cmmb_input_r,cmmb_output_w) //i/o
177		AM_RANGE(0x4900, 0x4900) AM_READ_LEGACY(kludge_r)
	180	AM_RANGE(0x2480, 0x249f) AM_RAM_WRITE(cmmb_paletteram_w) AM_BASE_GENERIC(paletteram)
	181	AM_RANGE(0x4000, 0x400f) AM_READWRITE(cmmb_input_r,cmmb_output_w) //i/o
	182	AM_RANGE(0x4900, 0x4900) AM_READ(kludge_r)
178	183	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
179	184	AM_RANGE(0xa000, 0xafff) AM_RAM
180		AM_RANGE(0xb000, 0xbfff) AM_READWRITE_LEGACY(cmmb_charram_r,cmmb_charram_w)
181		AM_RANGE(0xc000, 0xc00f) AM_READWRITE_LEGACY(cmmb_input_r,cmmb_output_w) //i/o
	185	AM_RANGE(0xb000, 0xbfff) AM_READWRITE(cmmb_charram_r,cmmb_charram_w)
	186	AM_RANGE(0xc000, 0xc00f) AM_READWRITE(cmmb_input_r,cmmb_output_w) //i/o
182	187	AM_RANGE(0x8000, 0xffff) AM_ROM
183	188	ADDRESS_MAP_END
184	189

src/mame/drivers/boxer.c

r14845	r14846
36	36
37	37	/* devices */
38	38	device_t *m_maincpu;
	39	DECLARE_READ8_MEMBER(boxer_input_r);
	40	DECLARE_READ8_MEMBER(boxer_misc_r);
	41	DECLARE_WRITE8_MEMBER(boxer_bell_w);
	42	DECLARE_WRITE8_MEMBER(boxer_sound_w);
	43	DECLARE_WRITE8_MEMBER(boxer_pot_w);
	44	DECLARE_WRITE8_MEMBER(boxer_irq_reset_w);
	45	DECLARE_WRITE8_MEMBER(boxer_crowd_w);
	46	DECLARE_WRITE8_MEMBER(boxer_led_w);
39	47	};
40	48
41	49	/*************************************
r14845	r14846
191	199	*
192	200	*************************************/
193	201
194		static READ8_HANDLER( boxer_input_r )
	202	READ8_MEMBER(boxer_state::boxer_input_r)
195	203	{
196		UINT8 val = input_port_read(space->machine(), "IN0");
	204	UINT8 val = input_port_read(machine(), "IN0");
197	205
198		if (input_port_read(space->machine(), "IN3") < space->machine().primary_screen->vpos())
	206	if (input_port_read(machine(), "IN3") < machine().primary_screen->vpos())
199	207	val |= 0x02;
200	208
201	209	return (val << ((offset & 7) ^ 7)) & 0x80;
202	210	}
203	211
204	212
205		static READ8_HANDLER( boxer_misc_r )
	213	READ8_MEMBER(boxer_state::boxer_misc_r)
206	214	{
207		boxer_state *state = space->machine().driver_data<boxer_state>();
208	215	UINT8 val = 0;
209	216
210	217	switch (offset & 3)
211	218	{
212	219	case 0:
213		val = state->m_pot_state & state->m_pot_latch;
	220	val = m_pot_state & m_pot_latch;
214	221	break;
215	222
216	223	case 1:
217		val = space->machine().primary_screen->vpos();
	224	val = machine().primary_screen->vpos();
218	225	break;
219	226
220	227	case 2:
221		val = input_port_read(space->machine(), "IN1");
	228	val = input_port_read(machine(), "IN1");
222	229	break;
223	230
224	231	case 3:
225		val = input_port_read(space->machine(), "IN2");
	232	val = input_port_read(machine(), "IN2");
226	233	break;
227	234	}
228	235
r14845	r14846
232	239
233	240
234	241
235		static WRITE8_HANDLER( boxer_bell_w )
	242	WRITE8_MEMBER(boxer_state::boxer_bell_w)
236	243	{
237	244	}
238	245
239	246
240		static WRITE8_HANDLER( boxer_sound_w )
	247	WRITE8_MEMBER(boxer_state::boxer_sound_w)
241	248	{
242	249	}
243	250
244	251
245		static WRITE8_HANDLER( boxer_pot_w )
	252	WRITE8_MEMBER(boxer_state::boxer_pot_w)
246	253	{
247		boxer_state *state = space->machine().driver_data<boxer_state>();
248	254	/* BIT0 => HPOT1 */
249	255	/* BIT1 => VPOT1 */
250	256	/* BIT2 => RPOT1 */
r14845	r14846
252	258	/* BIT4 => VPOT2 */
253	259	/* BIT5 => RPOT2 */
254	260
255		state->m_pot_latch = data & 0x3f;
	261	m_pot_latch = data & 0x3f;
256	262
257		device_set_input_line(state->m_maincpu, INPUT_LINE_NMI, CLEAR_LINE);
	263	device_set_input_line(m_maincpu, INPUT_LINE_NMI, CLEAR_LINE);
258	264	}
259	265
260	266
261		static WRITE8_HANDLER( boxer_irq_reset_w )
	267	WRITE8_MEMBER(boxer_state::boxer_irq_reset_w)
262	268	{
263		boxer_state *state = space->machine().driver_data<boxer_state>();
264		device_set_input_line(state->m_maincpu, 0, CLEAR_LINE);
	269	device_set_input_line(m_maincpu, 0, CLEAR_LINE);
265	270	}
266	271
267	272
268		static WRITE8_HANDLER( boxer_crowd_w )
	273	WRITE8_MEMBER(boxer_state::boxer_crowd_w)
269	274	{
270	275	/* BIT0 => ATTRACT */
271	276	/* BIT1 => CROWD-1 */
272	277	/* BIT2 => CROWD-2 */
273	278	/* BIT3 => CROWD-3 */
274	279
275		coin_lockout_global_w(space->machine(), data & 1);
	280	coin_lockout_global_w(machine(), data & 1);
276	281	}
277	282
278	283
279		static WRITE8_HANDLER( boxer_led_w )
	284	WRITE8_MEMBER(boxer_state::boxer_led_w)
280	285	{
281		set_led_status(space->machine(), 1, !(data & 1));
282		set_led_status(space->machine(), 0, !(data & 2));
	286	set_led_status(machine(), 1, !(data & 1));
	287	set_led_status(machine(), 0, !(data & 2));
283	288	}
284	289
285	290
r14845	r14846
293	298	ADDRESS_MAP_GLOBAL_MASK(0x3fff)
294	299	AM_RANGE(0x0000, 0x01ff) AM_RAM
295	300	AM_RANGE(0x0200, 0x03ff) AM_RAM AM_BASE(m_tile_ram)
296		AM_RANGE(0x0800, 0x08ff) AM_READ_LEGACY(boxer_input_r)
297		AM_RANGE(0x1000, 0x17ff) AM_READ_LEGACY(boxer_misc_r)
298		AM_RANGE(0x1800, 0x1800) AM_WRITE_LEGACY(boxer_pot_w)
299		AM_RANGE(0x1900, 0x19ff) AM_WRITE_LEGACY(boxer_led_w)
300		AM_RANGE(0x1a00, 0x1aff) AM_WRITE_LEGACY(boxer_sound_w)
301		AM_RANGE(0x1b00, 0x1bff) AM_WRITE_LEGACY(boxer_crowd_w)
302		AM_RANGE(0x1c00, 0x1cff) AM_WRITE_LEGACY(boxer_irq_reset_w)
303		AM_RANGE(0x1d00, 0x1dff) AM_WRITE_LEGACY(boxer_bell_w)
	301	AM_RANGE(0x0800, 0x08ff) AM_READ(boxer_input_r)
	302	AM_RANGE(0x1000, 0x17ff) AM_READ(boxer_misc_r)
	303	AM_RANGE(0x1800, 0x1800) AM_WRITE(boxer_pot_w)
	304	AM_RANGE(0x1900, 0x19ff) AM_WRITE(boxer_led_w)
	305	AM_RANGE(0x1a00, 0x1aff) AM_WRITE(boxer_sound_w)
	306	AM_RANGE(0x1b00, 0x1bff) AM_WRITE(boxer_crowd_w)
	307	AM_RANGE(0x1c00, 0x1cff) AM_WRITE(boxer_irq_reset_w)
	308	AM_RANGE(0x1d00, 0x1dff) AM_WRITE(boxer_bell_w)
304	309	AM_RANGE(0x1e00, 0x1eff) AM_WRITEONLY AM_BASE(m_sprite_ram)
305	310	AM_RANGE(0x1f00, 0x1fff) AM_WRITE_LEGACY(watchdog_reset_w)
306	311	AM_RANGE(0x3000, 0x3fff) AM_ROM

src/mame/drivers/roul.c

r14845	r14846
76	76	UINT8 m_reg[0x10];
77	77	UINT8 *m_videobuf;
78	78	UINT8 m_lamp_old;
	79	DECLARE_READ8_MEMBER(blitter_status_r);
	80	DECLARE_WRITE8_MEMBER(blitter_cmd_w);
	81	DECLARE_WRITE8_MEMBER(sound_latch_w);
	82	DECLARE_WRITE8_MEMBER(ball_w);
79	83	};
80	84
81	85
r14845	r14846
107	111	}
108	112	}
109	113
110		static READ8_HANDLER( blitter_status_r )
	114	READ8_MEMBER(roul_state::blitter_status_r)
111	115	{
112	116	/*
113	117	code check bit 6 and bit 7
r14845	r14846
115	119	bit 6 -> ??? (after unknown blitter command : [80][80][08][02])
116	120	*/
117	121	//  return 0x80; // blitter ready
118		//  logerror("Read unknown port $f5 at %04x\n",cpu_get_pc(&space->device()));
119		return space->machine().rand() & 0x00c0;
	122	//  logerror("Read unknown port $f5 at %04x\n",cpu_get_pc(&space.device()));
	123	return machine().rand() & 0x00c0;
120	124	}
121	125
122		static WRITE8_HANDLER( blitter_cmd_w )
	126	WRITE8_MEMBER(roul_state::blitter_cmd_w)
123	127	{
124		roul_state *state = space->machine().driver_data<roul_state>();
125		state->m_reg[offset] = data;
	128	m_reg[offset] = data;
126	129	if (offset==2)
127	130	{
128	131	int i,j;
129		int width   = state->m_reg[2];
130		int y      = state->m_reg[0];
131		int x      = state->m_reg[1];
132		int color   = state->m_reg[3] & 0x0f;
	132	int width   = m_reg[2];
	133	int y      = m_reg[0];
	134	int x      = m_reg[1];
	135	int color   = m_reg[3] & 0x0f;
133	136	int xdirection = 1, ydirection = 1;
134	137
135		if (state->m_reg[3] & 0x10) ydirection = -1;
136		if (state->m_reg[3] & 0x20) xdirection = -1;
	138	if (m_reg[3] & 0x10) ydirection = -1;
	139	if (m_reg[3] & 0x20) xdirection = -1;
137	140
138	141	if (width == 0x00) width = 0x100;
139	142
140		switch(state->m_reg[3] & 0xc0)
	143	switch(m_reg[3] & 0xc0)
141	144	{
142		case 0x00: // state->m_reg[4] used?
	145	case 0x00: // m_reg[4] used?
143	146	for (i = - width / 2; i < width / 2; i++)
144	147	for (j = - width / 2; j < width / 2; j++)
145		state->m_videobuf[(y + j) * 256 + x + i] = color;
146		logerror("Blitter command 0 : [%02x][%02x][%02x][%02x][%02x]\n",state->m_reg[0],state->m_reg[1],state->m_reg[2],state->m_reg[3],state->m_reg[4]);
	148	m_videobuf[(y + j) * 256 + x + i] = color;
	149	logerror("Blitter command 0 : [%02x][%02x][%02x][%02x][%02x]\n",m_reg[0],m_reg[1],m_reg[2],m_reg[3],m_reg[4]);
147	150	break;
148		case 0x40: // vertical line - state->m_reg[4] not used
	151	case 0x40: // vertical line - m_reg[4] not used
149	152	for (i = 0; i < width; i++ )
150		state->m_videobuf[(y + i * ydirection) * 256 + x] = color;
	153	m_videobuf[(y + i * ydirection) * 256 + x] = color;
151	154	break;
152		case 0x80: // horizontal line - state->m_reg[4] not used
	155	case 0x80: // horizontal line - m_reg[4] not used
153	156	for (i = 0; i < width; i++ )
154		state->m_videobuf[y * 256 + x + i * xdirection] = color;
	157	m_videobuf[y * 256 + x + i * xdirection] = color;
155	158	break;
156		case 0xc0: // diagonal line - state->m_reg[4] not used
	159	case 0xc0: // diagonal line - m_reg[4] not used
157	160	for (i = 0; i < width; i++ )
158		state->m_videobuf[(y + i * ydirection) * 256 + x + i * xdirection] = color;
	161	m_videobuf[(y + i * ydirection) * 256 + x + i * xdirection] = color;
159	162	}
160	163	}
161	164
162	165	}
163	166
164		static WRITE8_HANDLER( sound_latch_w )
	167	WRITE8_MEMBER(roul_state::sound_latch_w)
165	168	{
166	169	soundlatch_w(space, 0, data & 0xff);
167		cputag_set_input_line(space->machine(), "soundcpu", 0, HOLD_LINE);
	170	cputag_set_input_line(machine(), "soundcpu", 0, HOLD_LINE);
168	171	}
169	172
170		static WRITE8_HANDLER( ball_w )
	173	WRITE8_MEMBER(roul_state::ball_w)
171	174	{
172		roul_state *state = space->machine().driver_data<roul_state>();
173	175	int lamp = data;
174	176
175	177	output_set_lamp_value(data, 1);
176		output_set_lamp_value(state->m_lamp_old, 0);
177		state->m_lamp_old = lamp;
	178	output_set_lamp_value(m_lamp_old, 0);
	179	m_lamp_old = lamp;
178	180	}
179	181
180	182	static ADDRESS_MAP_START( roul_map, AS_PROGRAM, 8, roul_state )
r14845	r14846
184	186
185	187	static ADDRESS_MAP_START( roul_cpu_io_map, AS_IO, 8, roul_state )
186	188	ADDRESS_MAP_GLOBAL_MASK(0xff)
187		AM_RANGE(0xf0, 0xf4) AM_WRITE_LEGACY(blitter_cmd_w)
188		AM_RANGE(0xf5, 0xf5) AM_READ_LEGACY(blitter_status_r)
	189	AM_RANGE(0xf0, 0xf4) AM_WRITE(blitter_cmd_w)
	190	AM_RANGE(0xf5, 0xf5) AM_READ(blitter_status_r)
189	191	AM_RANGE(0xf8, 0xf8) AM_READ_PORT("DSW")
190		AM_RANGE(0xf9, 0xf9) AM_WRITE_LEGACY(ball_w)
	192	AM_RANGE(0xf9, 0xf9) AM_WRITE(ball_w)
191	193	AM_RANGE(0xfa, 0xfa) AM_READ_PORT("IN0")
192	194	AM_RANGE(0xfd, 0xfd) AM_READ_PORT("IN1")
193		AM_RANGE(0xfe, 0xfe) AM_WRITE_LEGACY(sound_latch_w)
	195	AM_RANGE(0xfe, 0xfe) AM_WRITE(sound_latch_w)
194	196	ADDRESS_MAP_END
195	197
196	198	static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, roul_state )

src/mame/drivers/speglsht.c

r14845	r14846
121	121	UINT32 m_videoreg;
122	122	bitmap_ind16 *m_bitmap;
123	123	UINT32 *m_cop_ram;
	124	DECLARE_READ32_MEMBER(shared_r);
	125	DECLARE_WRITE32_MEMBER(shared_w);
	126	DECLARE_WRITE32_MEMBER(videoreg_w);
	127	DECLARE_WRITE32_MEMBER(cop_w);
	128	DECLARE_READ32_MEMBER(cop_r);
	129	DECLARE_READ32_MEMBER(irq_ack_clear);
124	130	};
125	131
126	132
r14845	r14846
149	155	AM_RANGE(0xf0, 0xf0) AM_READ_LEGACY(st0016_dma_r)
150	156	ADDRESS_MAP_END
151	157
152		static READ32_HANDLER(shared_r)
	158	READ32_MEMBER(speglsht_state::shared_r)
153	159	{
154		speglsht_state *state = space->machine().driver_data<speglsht_state>();
155		return state->m_shared[offset];
	160	return m_shared[offset];
156	161	}
157	162
158		static WRITE32_HANDLER(shared_w)
	163	WRITE32_MEMBER(speglsht_state::shared_w)
159	164	{
160		speglsht_state *state = space->machine().driver_data<speglsht_state>();
161		state->m_shared[offset]=data&0xff;
	165	m_shared[offset]=data&0xff;
162	166	}
163	167
164		static WRITE32_HANDLER(videoreg_w)
	168	WRITE32_MEMBER(speglsht_state::videoreg_w)
165	169	{
166		speglsht_state *state = space->machine().driver_data<speglsht_state>();
167		COMBINE_DATA(&state->m_videoreg);
	170	COMBINE_DATA(&m_videoreg);
168	171	}
169	172
170	173
171		static WRITE32_HANDLER(cop_w)
	174	WRITE32_MEMBER(speglsht_state::cop_w)
172	175	{
173		speglsht_state *state = space->machine().driver_data<speglsht_state>();
174		COMBINE_DATA(&state->m_cop_ram[offset]);
	176	COMBINE_DATA(&m_cop_ram[offset]);
175	177
176		if(state->m_cop_ram[offset]&0x8000) //fix (sign)
	178	if(m_cop_ram[offset]&0x8000) //fix (sign)
177	179	{
178		state->m_cop_ram[offset]|=0xffff0000;
	180	m_cop_ram[offset]|=0xffff0000;
179	181	}
180	182	}
181	183
182	184	//matrix * vector
183		static READ32_HANDLER(cop_r)
	185	READ32_MEMBER(speglsht_state::cop_r)
184	186	{
185		speglsht_state *state = space->machine().driver_data<speglsht_state>();
186		INT32 *cop=(INT32*)&state->m_cop_ram[0];
	187	INT32 *cop=(INT32*)&m_cop_ram[0];
187	188
188	189	union
189	190	{
r14845	r14846
215	216	return 0;
216	217	}
217	218
218		static READ32_HANDLER(irq_ack_clear)
	219	READ32_MEMBER(speglsht_state::irq_ack_clear)
219	220	{
220		cputag_set_input_line(space->machine(), "sub", R3000_IRQ4, CLEAR_LINE);
	221	cputag_set_input_line(machine(), "sub", R3000_IRQ4, CLEAR_LINE);
221	222	return 0;
222	223	}
223	224
224	225	static ADDRESS_MAP_START( speglsht_mem, AS_PROGRAM, 32, speglsht_state )
225	226	AM_RANGE(0x00000000, 0x000fffff) AM_RAM
226	227	AM_RANGE(0x01000000, 0x01007fff) AM_RAM //tested - STATIC RAM
227		AM_RANGE(0x01600000, 0x0160004f) AM_READWRITE_LEGACY(cop_r, cop_w) AM_BASE(m_cop_ram)
228		AM_RANGE(0x01800200, 0x01800203) AM_WRITE_LEGACY(videoreg_w)
	228	AM_RANGE(0x01600000, 0x0160004f) AM_READWRITE(cop_r, cop_w) AM_BASE(m_cop_ram)
	229	AM_RANGE(0x01800200, 0x01800203) AM_WRITE(videoreg_w)
229	230	AM_RANGE(0x01800300, 0x01800303) AM_READ_PORT("IN0")
230	231	AM_RANGE(0x01800400, 0x01800403) AM_READ_PORT("IN1")
231	232	AM_RANGE(0x01a00000, 0x01afffff) AM_RAM AM_BASE(m_framebuffer)
232	233	AM_RANGE(0x01b00000, 0x01b07fff) AM_RAM //cleared ...  video related ?
233	234	AM_RANGE(0x01c00000, 0x01dfffff) AM_ROM AM_REGION("user2", 0)
234		AM_RANGE(0x0a000000, 0x0a003fff) AM_READWRITE_LEGACY(shared_r, shared_w)
	235	AM_RANGE(0x0a000000, 0x0a003fff) AM_READWRITE(shared_r, shared_w)
235	236	AM_RANGE(0x1eff0000, 0x1eff001f) AM_RAM
236		AM_RANGE(0x1eff003c, 0x1eff003f) AM_READ_LEGACY(irq_ack_clear)
	237	AM_RANGE(0x1eff003c, 0x1eff003f) AM_READ(irq_ack_clear)
237	238	AM_RANGE(0x1fc00000, 0x1fdfffff) AM_ROM AM_REGION("user1", 0)
238	239	AM_RANGE(0x2fc00000, 0x2fdfffff) AM_ROM AM_REGION("user1", 0) // mirror for interrupts
239	240	ADDRESS_MAP_END

src/mame/drivers/magicfly.c

r14845	r14846
427	427	UINT8 *m_colorram;
428	428	tilemap_t *m_bg_tilemap;
429	429	int m_input_selector;
	430	DECLARE_WRITE8_MEMBER(magicfly_videoram_w);
	431	DECLARE_WRITE8_MEMBER(magicfly_colorram_w);
	432	DECLARE_READ8_MEMBER(mux_port_r);
	433	DECLARE_WRITE8_MEMBER(mux_port_w);
430	434	};
431	435
432	436
r14845	r14846
435	439	*************************/
436	440
437	441
438		static WRITE8_HANDLER( magicfly_videoram_w )
	442	WRITE8_MEMBER(magicfly_state::magicfly_videoram_w)
439	443	{
440		magicfly_state *state = space->machine().driver_data<magicfly_state>();
441		state->m_videoram[offset] = data;
442		state->m_bg_tilemap->mark_tile_dirty(offset);
	444	m_videoram[offset] = data;
	445	m_bg_tilemap->mark_tile_dirty(offset);
443	446	}
444	447
445		static WRITE8_HANDLER( magicfly_colorram_w )
	448	WRITE8_MEMBER(magicfly_state::magicfly_colorram_w)
446	449	{
447		magicfly_state *state = space->machine().driver_data<magicfly_state>();
448		state->m_colorram[offset] = data;
449		state->m_bg_tilemap->mark_tile_dirty(offset);
	450	m_colorram[offset] = data;
	451	m_bg_tilemap->mark_tile_dirty(offset);
450	452	}
451	453
452	454	static TILE_GET_INFO( get_magicfly_tile_info )
r14845	r14846
553	555	******************************/
554	556
555	557
556		static READ8_HANDLER( mux_port_r )
	558	READ8_MEMBER(magicfly_state::mux_port_r)
557	559	{
558		magicfly_state *state = space->machine().driver_data<magicfly_state>();
559		switch( state->m_input_selector )
	560	switch( m_input_selector )
560	561	{
561		case 0x01: return input_port_read(space->machine(), "IN0-0");
562		case 0x02: return input_port_read(space->machine(), "IN0-1");
563		case 0x04: return input_port_read(space->machine(), "IN0-2");
564		case 0x08: return input_port_read(space->machine(), "IN0-3");
565		case 0x00: return input_port_read(space->machine(), "DSW0");
	562	case 0x01: return input_port_read(machine(), "IN0-0");
	563	case 0x02: return input_port_read(machine(), "IN0-1");
	564	case 0x04: return input_port_read(machine(), "IN0-2");
	565	case 0x08: return input_port_read(machine(), "IN0-3");
	566	case 0x00: return input_port_read(machine(), "DSW0");
566	567	}
567	568	return 0xff;
568	569	}
569	570
570		static WRITE8_HANDLER( mux_port_w )
	571	WRITE8_MEMBER(magicfly_state::mux_port_w)
571	572	{
572		magicfly_state *state = space->machine().driver_data<magicfly_state>();
573	573	/*  - bits -
574	574	7654 3210
575	575	---- xxxx   Input selector.
r14845	r14846
579	579	x--- ----   Sound DAC.
580	580
581	581	*/
582		state->m_input_selector = data & 0x0f;   /* Input Selector */
	582	m_input_selector = data & 0x0f;   /* Input Selector */
583	583
584		dac_data_w(space->machine().device("dac"), data & 0x80);      /* Sound DAC */
	584	dac_data_w(machine().device("dac"), data & 0x80);      /* Sound DAC */
585	585
586		coin_counter_w(space->machine(), 0, data & 0x40);   /* Coin1 */
587		coin_counter_w(space->machine(), 1, data & 0x10);   /* Coin2 */
588		coin_counter_w(space->machine(), 2, data & 0x20);   /* Payout */
	586	coin_counter_w(machine(), 0, data & 0x40);   /* Coin1 */
	587	coin_counter_w(machine(), 1, data & 0x10);   /* Coin2 */
	588	coin_counter_w(machine(), 2, data & 0x20);   /* Payout */
589	589	}
590	590
591	591
r14845	r14846
597	597	AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("nvram")    /* MK48Z02B NVRAM */
598	598	AM_RANGE(0x0800, 0x0800) AM_DEVWRITE("crtc", mc6845_device, address_w)
599	599	AM_RANGE(0x0801, 0x0801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
600		AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE_LEGACY(magicfly_videoram_w) AM_BASE(m_videoram)   /* HM6116LP #1 (2K x 8) RAM (only 1st half used) */
601		AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE_LEGACY(magicfly_colorram_w) AM_BASE(m_colorram)   /* HM6116LP #2 (2K x 8) RAM (only 1st half used) */
602		AM_RANGE(0x2800, 0x2800) AM_READ_LEGACY(mux_port_r)   /* multiplexed input port */
603		AM_RANGE(0x3000, 0x3000) AM_WRITE_LEGACY(mux_port_w)   /* output port */
	600	AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(magicfly_videoram_w) AM_BASE(m_videoram)   /* HM6116LP #1 (2K x 8) RAM (only 1st half used) */
	601	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(magicfly_colorram_w) AM_BASE(m_colorram)   /* HM6116LP #2 (2K x 8) RAM (only 1st half used) */
	602	AM_RANGE(0x2800, 0x2800) AM_READ(mux_port_r)   /* multiplexed input port */
	603	AM_RANGE(0x3000, 0x3000) AM_WRITE(mux_port_w)   /* output port */
604	604	AM_RANGE(0xc000, 0xffff) AM_ROM               /* ROM space */
605	605	ADDRESS_MAP_END
606	606

src/mame/drivers/gal3.c

r14845	r14846
147	147	UINT16 *m_rsoSharedRAM;
148	148	UINT32 m_led_mst;
149	149	UINT32 m_led_slv;
	150	DECLARE_READ32_MEMBER(led_mst_r);
	151	DECLARE_WRITE32_MEMBER(led_mst_w);
	152	DECLARE_READ32_MEMBER(led_slv_r);
	153	DECLARE_WRITE32_MEMBER(led_slv_w);
	154	DECLARE_READ32_MEMBER(paletteram32_r);
	155	DECLARE_WRITE32_MEMBER(paletteram32_w);
	156	DECLARE_READ32_MEMBER(namcos21_video_enable_r);
	157	DECLARE_WRITE32_MEMBER(namcos21_video_enable_w);
	158	DECLARE_READ32_MEMBER(rso_r);
	159	DECLARE_WRITE32_MEMBER(rso_w);
150	160	};
151	161
152	162
r14845	r14846
270	280
271	281	/***************************************************************************************/
272	282
273		static READ32_HANDLER( led_mst_r )
	283	READ32_MEMBER(gal3_state::led_mst_r)
274	284	{
275		gal3_state *state = space->machine().driver_data<gal3_state>();
276		return state->m_led_mst;
	285	return m_led_mst;
277	286	}
278	287
279		static WRITE32_HANDLER( led_mst_w )
	288	WRITE32_MEMBER(gal3_state::led_mst_w)
280	289	{
281		gal3_state *state = space->machine().driver_data<gal3_state>();
282		COMBINE_DATA(&state->m_led_mst);
	290	COMBINE_DATA(&m_led_mst);
283	291	}
284	292
285		static READ32_HANDLER( led_slv_r )
	293	READ32_MEMBER(gal3_state::led_slv_r)
286	294	{
287		gal3_state *state = space->machine().driver_data<gal3_state>();
288		return state->m_led_slv;
	295	return m_led_slv;
289	296	}
290	297
291		static WRITE32_HANDLER( led_slv_w )
	298	WRITE32_MEMBER(gal3_state::led_slv_w)
292	299	{
293		gal3_state *state = space->machine().driver_data<gal3_state>();
294		COMBINE_DATA(&state->m_led_slv);
	300	COMBINE_DATA(&m_led_slv);
295	301	}
296	302
297	303	/* palette memory handlers */
298	304
299		static READ32_HANDLER( paletteram32_r )
	305	READ32_MEMBER(gal3_state::paletteram32_r)
300	306	{
301	307	offset *= 2;
302		return (space->machine().generic.paletteram.u16[offset]<<16)|space->machine().generic.paletteram.u16[offset+1];
	308	return (machine().generic.paletteram.u16[offset]<<16)|machine().generic.paletteram.u16[offset+1];
303	309	}
304	310
305		static WRITE32_HANDLER( paletteram32_w )
	311	WRITE32_MEMBER(gal3_state::paletteram32_w)
306	312	{
307	313	UINT32 v;
308	314	offset *= 2;
309		v = (space->machine().generic.paletteram.u16[offset]<<16)|space->machine().generic.paletteram.u16[offset+1];
	315	v = (machine().generic.paletteram.u16[offset]<<16)|machine().generic.paletteram.u16[offset+1];
310	316	COMBINE_DATA( &v );
311		space->machine().generic.paletteram.u16[offset+0] = v>>16;
312		space->machine().generic.paletteram.u16[offset+1] = v&0xffff;
	317	machine().generic.paletteram.u16[offset+0] = v>>16;
	318	machine().generic.paletteram.u16[offset+1] = v&0xffff;
313	319	}
314	320
315		static READ32_HANDLER(namcos21_video_enable_r)
	321	READ32_MEMBER(gal3_state::namcos21_video_enable_r)
316	322	{
317		gal3_state *state = space->machine().driver_data<gal3_state>();
318		return state->m_namcos21_video_enable<<16;
	323	return m_namcos21_video_enable<<16;
319	324	}
320	325
321		static WRITE32_HANDLER(namcos21_video_enable_w)
	326	WRITE32_MEMBER(gal3_state::namcos21_video_enable_w)
322	327	{
323		gal3_state *state = space->machine().driver_data<gal3_state>();
324	328	UINT32 v;
325		v = state->m_namcos21_video_enable<<16;
	329	v = m_namcos21_video_enable<<16;
326	330	COMBINE_DATA( &v ); // 0xff53, instead of 0x40 in namcos21
327		state->m_namcos21_video_enable = v>>16;
	331	m_namcos21_video_enable = v>>16;
328	332	}
329	333
330		static READ32_HANDLER(rso_r)
	334	READ32_MEMBER(gal3_state::rso_r)
331	335	{
332		gal3_state *state = space->machine().driver_data<gal3_state>();
333	336	/*store $5555 @$0046, and readback @$0000
334	337	read @$0144 and store at A6_21e & A4_5c
335	338	Check @$009a==1 to start DEMO
336	339	HACK*/
337	340	offset *= 2;
338		return (state->m_rsoSharedRAM[offset]<<16)|state->m_rsoSharedRAM[offset+1];
	341	return (m_rsoSharedRAM[offset]<<16)|m_rsoSharedRAM[offset+1];
339	342	}
340	343
341		static WRITE32_HANDLER(rso_w)
	344	WRITE32_MEMBER(gal3_state::rso_w)
342	345	{
343		gal3_state *state = space->machine().driver_data<gal3_state>();
344	346	UINT32 v;
345	347	offset *= 2;
346		v = (state->m_rsoSharedRAM[offset]<<16)|state->m_rsoSharedRAM[offset+1];
	348	v = (m_rsoSharedRAM[offset]<<16)|m_rsoSharedRAM[offset+1];
347	349	COMBINE_DATA( &v );
348		state->m_rsoSharedRAM[offset+0] = v>>16;
349		state->m_rsoSharedRAM[offset+1] = v&0xffff;
	350	m_rsoSharedRAM[offset+0] = v>>16;
	351	m_rsoSharedRAM[offset+1] = v&0xffff;
350	352	}
351	353
352	354
r14845	r14846
355	357	AM_RANGE(0x20000000, 0x20001fff) AM_RAM AM_BASE(m_nvmem) AM_SIZE(m_nvmem_size)   //NVRAM
356	358	/// AM_RANGE(0x40000000, 0x4000ffff) AM_WRITE_LEGACY() //
357	359	AM_RANGE(0x44000000, 0x44000003) AM_READ_PORT("DSW_CPU_mst"   )
358		AM_RANGE(0x44800000, 0x44800003) AM_READ_LEGACY(led_mst_r) AM_WRITE_LEGACY(led_mst_w)   //LEDs
	360	AM_RANGE(0x44800000, 0x44800003) AM_READ(led_mst_r) AM_WRITE(led_mst_w)   //LEDs
359	361	AM_RANGE(0x48000000, 0x48000003) AM_READNOP   //irq1 v-blank ack
360	362	AM_RANGE(0x4c000000, 0x4c000003) AM_READNOP   //irq3 ack
361	363	AM_RANGE(0x60000000, 0x60007fff) AM_RAM AM_SHARE("share1")   //CRAM
r14845	r14846
364	366	/// AM_RANGE(0xc0000000, 0xc000000b) AM_WRITENOP    //upload?
365	367	AM_RANGE(0xc000000c, 0xc000000f) AM_READNOP   //irq2 ack
366	368	/// AM_RANGE(0xd8000000, 0xd800000f) AM_RAM // protection or 68681?
367		AM_RANGE(0xf2800000, 0xf2800fff) AM_READWRITE_LEGACY(rso_r, rso_w)   //RSO PCB
	369	AM_RANGE(0xf2800000, 0xf2800fff) AM_READWRITE(rso_r, rso_w)   //RSO PCB
368	370	ADDRESS_MAP_END
369	371
370	372	static ADDRESS_MAP_START( cpu_slv_map, AS_PROGRAM, 32, gal3_state )
371	373	AM_RANGE(0x00000000, 0x0007ffff) AM_ROM
372	374	/// AM_RANGE(0x40000000, 0x4000ffff) AM_WRITE_LEGACY() //
373	375	AM_RANGE(0x44000000, 0x44000003) AM_READ_PORT("DSW_CPU_slv"   )
374		AM_RANGE(0x44800000, 0x44800003) AM_READ_LEGACY(led_slv_r) AM_WRITE_LEGACY(led_slv_w)   //LEDs
	376	AM_RANGE(0x44800000, 0x44800003) AM_READ(led_slv_r) AM_WRITE(led_slv_w)   //LEDs
375	377	AM_RANGE(0x48000000, 0x48000003) AM_READNOP   //irq1 ack
376	378	/// AM_RANGE(0x50000000, 0x50000003) AM_READ_LEGACY() AM_WRITE_LEGACY()
377	379	/// AM_RANGE(0x54000000, 0x54000003) AM_READ_LEGACY() AM_WRITE_LEGACY()
r14845	r14846
386	388	/// AM_RANGE(0xf1480000, 0xf14807ff) AM_READWRITE_LEGACY(namcos21_depthcue_r,namcos21_depthcue_w)
387	389	AM_RANGE(0xf1700000, 0xf170ffff) AM_READWRITE_LEGACY(namco_obj32_r,namco_obj32_w)
388	390	AM_RANGE(0xf1720000, 0xf1720007) AM_READWRITE_LEGACY(namco_spritepos32_r,namco_spritepos32_w)
389		AM_RANGE(0xf1740000, 0xf175ffff) AM_READWRITE_LEGACY(paletteram32_r,paletteram32_w) AM_BASE_GENERIC(paletteram)
390		AM_RANGE(0xf1760000, 0xf1760003) AM_READWRITE_LEGACY(namcos21_video_enable_r,namcos21_video_enable_w)
	391	AM_RANGE(0xf1740000, 0xf175ffff) AM_READWRITE(paletteram32_r,paletteram32_w) AM_BASE_GENERIC(paletteram)
	392	AM_RANGE(0xf1760000, 0xf1760003) AM_READWRITE(namcos21_video_enable_r,namcos21_video_enable_w)
391	393
392	394	AM_RANGE(0xf2200000, 0xf220ffff) AM_RAM
393	395	AM_RANGE(0xf2700000, 0xf270ffff) AM_RAM   //AM_READWRITE_LEGACY(namco_obj16_r,namco_obj16_w)
394	396	AM_RANGE(0xf2720000, 0xf2720007) AM_RAM   //AM_READWRITE_LEGACY(namco_spritepos16_r,namco_spritepos16_w)
395	397	AM_RANGE(0xf2740000, 0xf275ffff) AM_RAM   //AM_READWRITE_LEGACY(paletteram16_r,paletteram16_w) AM_BASE_GENERIC(paletteram)
396		AM_RANGE(0xf2760000, 0xf2760003) AM_RAM   //AM_READWRITE_LEGACY(namcos21_video_enable_r,namcos21_video_enable_w)
	398	AM_RANGE(0xf2760000, 0xf2760003) AM_RAM   //AM_READWRITE(namcos21_video_enable_r,namcos21_video_enable_w)
397	399	ADDRESS_MAP_END
398	400
399	401	static ADDRESS_MAP_START( rs_cpu_map, AS_PROGRAM, 16, gal3_state )

src/mame/drivers/nightgal.c

r14845	r14846
52	52
53	53	/* memory */
54	54	UINT8      m_blit_buffer[256*256];
	55	DECLARE_READ8_MEMBER(blitter_status_r);
	56	DECLARE_WRITE8_MEMBER(nsc_true_blitter_w);
	57	DECLARE_WRITE8_MEMBER(sexygal_nsc_true_blitter_w);
	58	DECLARE_WRITE8_MEMBER(nsc_latch_w);
	59	DECLARE_READ8_MEMBER(nsc_latch_r);
	60	DECLARE_WRITE8_MEMBER(z80_latch_w);
	61	DECLARE_READ8_MEMBER(z80_latch_r);
	62	DECLARE_WRITE8_MEMBER(blitter_w);
	63	DECLARE_READ8_MEMBER(nsc_blit_r);
	64	DECLARE_WRITE8_MEMBER(royalqn_blitter_0_w);
	65	DECLARE_WRITE8_MEMBER(royalqn_blitter_1_w);
	66	DECLARE_WRITE8_MEMBER(royalqn_blitter_2_w);
	67	DECLARE_READ8_MEMBER(royalqn_nsc_blit_r);
	68	DECLARE_READ8_MEMBER(royalqn_comm_r);
	69	DECLARE_WRITE8_MEMBER(royalqn_comm_w);
	70	DECLARE_WRITE8_MEMBER(blit_vregs_w);
	71	DECLARE_READ8_MEMBER(blit_vregs_r);
	72	DECLARE_WRITE8_MEMBER(blit_true_vregs_w);
	73	DECLARE_WRITE8_MEMBER(mux_w);
55	74	};
56	75
57	76
58	77
59		static READ8_HANDLER( blitter_status_r )
	78	READ8_MEMBER(nightgal_state::blitter_status_r)
60	79	{
61	80	return 0x80;
62	81	}
r14845	r14846
118	137	state->m_blit_buffer[(y * 256) + (x >> 1)] = (state->m_blit_buffer[(y * 256) + (x >> 1)] & 0xf0) | (pix & 0x0f);
119	138	}
120	139
121		static WRITE8_HANDLER( nsc_true_blitter_w )
	140	WRITE8_MEMBER(nightgal_state::nsc_true_blitter_w)
122	141	{
123		nightgal_state *state = space->machine().driver_data<nightgal_state>();
124	142	int src, x, y, h, w, flipx;
125		state->m_true_blit[offset] = data;
	143	m_true_blit[offset] = data;
126	144
127	145	/*trigger blitter write to ram,might not be correct...*/
128	146	if (offset == 5)
129	147	{
130		//printf("%02x %02x %02x %02x %02x %02x %02x\n", state->m_true_blit[0], state->m_true_blit[1], state->m_true_blit[2], state->m_true_blit[3], state->m_true_blit[4], state->m_true_blit[5], state->m_true_blit[6]);
131		w = (state->m_true_blit[4] & 0xff) + 1;
132		h = (state->m_true_blit[5] & 0xff) + 1;
133		src = ((state->m_true_blit[1] << 8) | (state->m_true_blit[0] << 0));
134		src |= (state->m_true_blit[6] & 3) << 16;
	148	//printf("%02x %02x %02x %02x %02x %02x %02x\n", m_true_blit[0], m_true_blit[1], m_true_blit[2], m_true_blit[3], m_true_blit[4], m_true_blit[5], m_true_blit[6]);
	149	w = (m_true_blit[4] & 0xff) + 1;
	150	h = (m_true_blit[5] & 0xff) + 1;
	151	src = ((m_true_blit[1] << 8) | (m_true_blit[0] << 0));
	152	src |= (m_true_blit[6] & 3) << 16;
135	153
136		x = (state->m_true_blit[2] & 0xff);
137		y = (state->m_true_blit[3] & 0xff);
	154	x = (m_true_blit[2] & 0xff);
	155	y = (m_true_blit[3] & 0xff);
138	156
139	157	// lowest bit of src controls flipping / draw direction?
140		flipx = (state->m_true_blit[0] & 1);
	158	flipx = (m_true_blit[0] & 1);
141	159
142	160	if (!flipx)
143	161	src += (w * h) - 1;
r14845	r14846
153	171	{
154	172	int drawx = (x + xcount) & 0xff;
155	173	int drawy = (y + ycount) & 0xff;
156		UINT8 dat = nightgal_gfx_nibble(space->machine(), src + count);
157		UINT8 cur_pen_hi = state->m_pen_data[(dat & 0xf0) >> 4];
158		UINT8 cur_pen_lo = state->m_pen_data[(dat & 0x0f) >> 0];
	174	UINT8 dat = nightgal_gfx_nibble(machine(), src + count);
	175	UINT8 cur_pen_hi = m_pen_data[(dat & 0xf0) >> 4];
	176	UINT8 cur_pen_lo = m_pen_data[(dat & 0x0f) >> 0];
159	177
160	178	dat = cur_pen_lo | (cur_pen_hi << 4);
161	179
162	180	if ((dat & 0xff) != 0)
163		plot_nightgal_gfx_pixel(space->machine(), dat, drawx, drawy);
	181	plot_nightgal_gfx_pixel(machine(), dat, drawx, drawy);
164	182
165	183	if (!flipx)
166	184	count--;
r14845	r14846
173	191	}
174	192
175	193	/* different register writes (probably a PAL line swapping).*/
176		static WRITE8_HANDLER( sexygal_nsc_true_blitter_w )
	194	WRITE8_MEMBER(nightgal_state::sexygal_nsc_true_blitter_w)
177	195	{
178		nightgal_state *state = space->machine().driver_data<nightgal_state>();
179	196	int src, x, y, h, w, flipx;
180		state->m_true_blit[offset] = data;
	197	m_true_blit[offset] = data;
181	198
182	199	/*trigger blitter write to ram,might not be correct...*/
183	200	if (offset == 6)
184	201	{
185		//printf("%02x %02x %02x %02x %02x %02x %02x\n", state->m_true_blit[0], state->m_true_blit[1], state->m_true_blit[2], state->m_true_blit[3], state->m_true_blit[4], state->m_true_blit[5], state->m_true_blit[6]);
186		w = (state->m_true_blit[5] & 0xff) + 1;
187		h = (state->m_true_blit[6] & 0xff) + 1;
188		src = ((state->m_true_blit[1] << 8) | (state->m_true_blit[0] << 0));
189		src |= (state->m_true_blit[2] & 3) << 16;
	202	//printf("%02x %02x %02x %02x %02x %02x %02x\n", m_true_blit[0], m_true_blit[1], m_true_blit[2], m_true_blit[3], m_true_blit[4], m_true_blit[5], m_true_blit[6]);
	203	w = (m_true_blit[5] & 0xff) + 1;
	204	h = (m_true_blit[6] & 0xff) + 1;
	205	src = ((m_true_blit[1] << 8) | (m_true_blit[0] << 0));
	206	src |= (m_true_blit[2] & 3) << 16;
190	207
191	208
192		x = (state->m_true_blit[3] & 0xff);
193		y = (state->m_true_blit[4] & 0xff);
	209	x = (m_true_blit[3] & 0xff);
	210	y = (m_true_blit[4] & 0xff);
194	211
195	212	// lowest bit of src controls flipping / draw direction?
196		flipx = (state->m_true_blit[0] & 1);
	213	flipx = (m_true_blit[0] & 1);
197	214
198	215	if (!flipx)
199	216	src += (w * h) - 1;
r14845	r14846
209	226	{
210	227	int drawx = (x + xcount) & 0xff;
211	228	int drawy = (y + ycount) & 0xff;
212		UINT8 dat = nightgal_gfx_nibble(space->machine(), src + count);
213		UINT8 cur_pen_hi = state->m_pen_data[(dat & 0xf0) >> 4];
214		UINT8 cur_pen_lo = state->m_pen_data[(dat & 0x0f) >> 0];
	229	UINT8 dat = nightgal_gfx_nibble(machine(), src + count);
	230	UINT8 cur_pen_hi = m_pen_data[(dat & 0xf0) >> 4];
	231	UINT8 cur_pen_lo = m_pen_data[(dat & 0x0f) >> 0];
215	232
216	233	dat = cur_pen_lo | cur_pen_hi << 4;
217	234
218	235	if ((dat & 0xff) != 0)
219		plot_nightgal_gfx_pixel(space->machine(), dat, drawx, drawy);
	236	plot_nightgal_gfx_pixel(machine(), dat, drawx, drawy);
220	237
221	238	if (!flipx)
222	239	count--;
r14845	r14846
224	241	count++;
225	242	}
226	243	}
227		//device_set_input_line(state->m_maincpu, INPUT_LINE_NMI, PULSE_LINE );
	244	//device_set_input_line(m_maincpu, INPUT_LINE_NMI, PULSE_LINE );
228	245	}
229	246	}
230	247	}
r14845	r14846
297	314	//#define SUB_NCS_RUN state->m_ncs_latch = 0x00
298	315	//#define SUB_NCS_HALT state->m_ncs_latch = 0x80
299	316	#ifdef UNUSED_CODE
300		static WRITE8_HANDLER( nsc_latch_w )
	317	WRITE8_MEMBER(nightgal_state::nsc_latch_w)
301	318	{
302		nightgal_state *state = space->machine().driver_data<nightgal_state>();
303		device_set_input_line(state->m_subcpu, 0, HOLD_LINE );
	319	device_set_input_line(m_subcpu, 0, HOLD_LINE );
304	320	}
305	321
306		static READ8_HANDLER( nsc_latch_r )
	322	READ8_MEMBER(nightgal_state::nsc_latch_r)
307	323	{
308		nightgal_state *state = space->machine().driver_data<nightgal_state>();
309	324
310		return state->m_z80_latch;
	325	return m_z80_latch;
311	326	}
312	327
313		static WRITE8_HANDLER( z80_latch_w )
	328	WRITE8_MEMBER(nightgal_state::z80_latch_w)
314	329	{
315		nightgal_state *state = space->machine().driver_data<nightgal_state>();
316		state->m_nsc_latch = data;
	330	m_nsc_latch = data;
317	331	}
318	332
319		static READ8_HANDLER( z80_latch_r )
	333	READ8_MEMBER(nightgal_state::z80_latch_r)
320	334	{
321		nightgal_state *state = space->machine().driver_data<nightgal_state>();
322		return state->m_nsc_latch;
	335	return m_nsc_latch;
323	336	}
324	337
325	338	/*z80 -> MCU video params*/
326		static WRITE8_HANDLER( blitter_w )
	339	WRITE8_MEMBER(nightgal_state::blitter_w)
327	340	{
328		nightgal_state *state = space->machine().driver_data<nightgal_state>();
329		state->m_blit_raw_data[offset] = data;
	341	m_blit_raw_data[offset] = data;
330	342	MAIN_Z80_HALT;
331	343	}
332	344
333		static READ8_HANDLER( nsc_blit_r )
	345	READ8_MEMBER(nightgal_state::nsc_blit_r)
334	346	{
335		nightgal_state *state = space->machine().driver_data<nightgal_state>();
336	347	MAIN_Z80_RUN;
337		return state->m_blit_raw_data[offset];
	348	return m_blit_raw_data[offset];
338	349	}
339	350	#endif
340	351	/* TODO: simplify this (error in the document) */
341	352
342		static WRITE8_HANDLER( royalqn_blitter_0_w )
	353	WRITE8_MEMBER(nightgal_state::royalqn_blitter_0_w)
343	354	{
344		nightgal_state *state = space->machine().driver_data<nightgal_state>();
345		state->m_blit_raw_data[0] = data;
	355	m_blit_raw_data[0] = data;
346	356	}
347	357
348		static WRITE8_HANDLER( royalqn_blitter_1_w )
	358	WRITE8_MEMBER(nightgal_state::royalqn_blitter_1_w)
349	359	{
350		nightgal_state *state = space->machine().driver_data<nightgal_state>();
351		state->m_blit_raw_data[1] = data;
	360	m_blit_raw_data[1] = data;
352	361	}
353	362
354		static WRITE8_HANDLER( royalqn_blitter_2_w )
	363	WRITE8_MEMBER(nightgal_state::royalqn_blitter_2_w)
355	364	{
356		nightgal_state *state = space->machine().driver_data<nightgal_state>();
357		state->m_blit_raw_data[2] = data;
358		device_set_input_line(state->m_subcpu, 0, ASSERT_LINE );
	365	m_blit_raw_data[2] = data;
	366	device_set_input_line(m_subcpu, 0, ASSERT_LINE );
359	367	}
360	368
361		static READ8_HANDLER( royalqn_nsc_blit_r )
	369	READ8_MEMBER(nightgal_state::royalqn_nsc_blit_r)
362	370	{
363		nightgal_state *state = space->machine().driver_data<nightgal_state>();
364	371
365	372	if(offset == 2)
366		device_set_input_line(state->m_subcpu, 0, CLEAR_LINE );
	373	device_set_input_line(m_subcpu, 0, CLEAR_LINE );
367	374
368		return state->m_blit_raw_data[offset];
	375	return m_blit_raw_data[offset];
369	376	}
370	377
371		static READ8_HANDLER( royalqn_comm_r )
	378	READ8_MEMBER(nightgal_state::royalqn_comm_r)
372	379	{
373		nightgal_state *state = space->machine().driver_data<nightgal_state>();
374	380
375		return (state->m_comms_ram[offset] & 0x80) | (0x7f); //bits 6-0 are undefined, presumably open bus
	381	return (m_comms_ram[offset] & 0x80) | (0x7f); //bits 6-0 are undefined, presumably open bus
376	382	}
377	383
378		static WRITE8_HANDLER( royalqn_comm_w )
	384	WRITE8_MEMBER(nightgal_state::royalqn_comm_w)
379	385	{
380		nightgal_state *state = space->machine().driver_data<nightgal_state>();
381	386
382		state->m_comms_ram[offset] = data & 0x80;
	387	m_comms_ram[offset] = data & 0x80;
383	388	}
384	389
385	390	#ifdef UNUSED_CODE
386		static WRITE8_HANDLER( blit_vregs_w )
	391	WRITE8_MEMBER(nightgal_state::blit_vregs_w)
387	392	{
388		nightgal_state *state = space->machine().driver_data<nightgal_state>();
389		state->m_pen_raw_data[offset] = data;
	393	m_pen_raw_data[offset] = data;
390	394	}
391	395
392		static READ8_HANDLER( blit_vregs_r )
	396	READ8_MEMBER(nightgal_state::blit_vregs_r)
393	397	{
394		nightgal_state *state = space->machine().driver_data<nightgal_state>();
395		return state->m_pen_raw_data[offset];
	398	return m_pen_raw_data[offset];
396	399	}
397	400	#endif
398		static WRITE8_HANDLER( blit_true_vregs_w )
	401	WRITE8_MEMBER(nightgal_state::blit_true_vregs_w)
399	402	{
400		nightgal_state *state = space->machine().driver_data<nightgal_state>();
401		state->m_pen_data[offset] = data;
	403	m_pen_data[offset] = data;
402	404	}
403	405
404	406	/********************************************
r14845	r14846
407	409	*
408	410	********************************************/
409	411
410		static WRITE8_HANDLER( mux_w )
	412	WRITE8_MEMBER(nightgal_state::mux_w)
411	413	{
412		nightgal_state *state = space->machine().driver_data<nightgal_state>();
413		state->m_mux_data = ~data;
414		//printf("%02x\n", state->m_mux_data);
	414	m_mux_data = ~data;
	415	//printf("%02x\n", m_mux_data);
415	416	}
416	417
417	418	static READ8_DEVICE_HANDLER( input_1p_r )
r14845	r14846
466	467	#ifdef UNUSED_CODE
467	468	static ADDRESS_MAP_START( nightgal_map, AS_PROGRAM, 8, nightgal_state )
468	469	AM_RANGE(0x0000, 0x7fff) AM_ROM
469		AM_RANGE(0xc100, 0xc100) AM_READ_LEGACY(nsc_latch_r)
470		AM_RANGE(0xc200, 0xc200) AM_WRITE_LEGACY(nsc_latch_w)
471		AM_RANGE(0xc300, 0xc30f) AM_WRITE_LEGACY(blit_vregs_w)
	470	AM_RANGE(0xc100, 0xc100) AM_READ(nsc_latch_r)
	471	AM_RANGE(0xc200, 0xc200) AM_WRITE(nsc_latch_w)
	472	AM_RANGE(0xc300, 0xc30f) AM_WRITE(blit_vregs_w)
472	473	AM_RANGE(0xf000, 0xffff) AM_RAM
473	474	ADDRESS_MAP_END
474	475
r14845	r14846
481	482	AM_RANGE(0x11,0x11) AM_READ_PORT("SYSA")
482	483	AM_RANGE(0x12,0x12) AM_READ_PORT("DSWA")
483	484	AM_RANGE(0x13,0x13) AM_READ_PORT("DSWB")
484		AM_RANGE(0x11,0x11) AM_WRITE_LEGACY(mux_w)
485		AM_RANGE(0x12,0x14) AM_WRITE_LEGACY(blitter_w) //data for the nsc to be processed
	485	AM_RANGE(0x11,0x11) AM_WRITE(mux_w)
	486	AM_RANGE(0x12,0x14) AM_WRITE(blitter_w) //data for the nsc to be processed
486	487	ADDRESS_MAP_END
487	488
488	489	static ADDRESS_MAP_START( nsc_map, AS_PROGRAM, 8, nightgal_state )
489	490	AM_RANGE(0x0000, 0x007f) AM_RAM
490		AM_RANGE(0x0080, 0x0080) AM_READ_LEGACY(blitter_status_r)
491		AM_RANGE(0x0081, 0x0083) AM_READ_LEGACY(nsc_blit_r)
492		AM_RANGE(0x0080, 0x0086) AM_WRITE_LEGACY(nsc_true_blitter_w)
	491	AM_RANGE(0x0080, 0x0080) AM_READ(blitter_status_r)
	492	AM_RANGE(0x0081, 0x0083) AM_READ(nsc_blit_r)
	493	AM_RANGE(0x0080, 0x0086) AM_WRITE(nsc_true_blitter_w)
493	494
494		AM_RANGE(0x00a0, 0x00af) AM_WRITE_LEGACY(blit_true_vregs_w)
	495	AM_RANGE(0x00a0, 0x00af) AM_WRITE(blit_true_vregs_w)
495	496
496		AM_RANGE(0x1100, 0x1100) AM_READWRITE_LEGACY(z80_latch_r,z80_latch_w) //irq control?
	497	AM_RANGE(0x1100, 0x1100) AM_READWRITE(z80_latch_r,z80_latch_w) //irq control?
497	498	AM_RANGE(0x1200, 0x1200) AM_READNOP //flip screen set bit
498		AM_RANGE(0x1300, 0x130f) AM_READ_LEGACY(blit_vregs_r)
	499	AM_RANGE(0x1300, 0x130f) AM_READ(blit_vregs_r)
499	500	//  AM_RANGE(0x1000, 0xdfff) AM_ROM AM_REGION("gfx1", 0 )
500	501	AM_RANGE(0xe000, 0xffff) AM_ROM AM_WRITENOP
501	502	ADDRESS_MAP_END
r14845	r14846
508	509	static ADDRESS_MAP_START( sexygal_map, AS_PROGRAM, 8, nightgal_state )
509	510	AM_RANGE(0x0000, 0x7fff) AM_ROM
510	511	AM_RANGE(0x8000, 0xbfff) AM_RAM //???
511		AM_RANGE(0xe000, 0xefff) AM_READWRITE_LEGACY(royalqn_comm_r, royalqn_comm_w) AM_BASE(m_comms_ram)
	512	AM_RANGE(0xe000, 0xefff) AM_READWRITE(royalqn_comm_r, royalqn_comm_w) AM_BASE(m_comms_ram)
512	513	AM_RANGE(0xf000, 0xffff) AM_RAM
513	514	ADDRESS_MAP_END
514	515
r14845	r14846
517	518	AM_RANGE(0x00,0x01) AM_DEVREADWRITE_LEGACY("ymsnd", ym2203_r, ym2203_w)
518	519	//  AM_RANGE(0x10,0x10) AM_WRITE_LEGACY(output_w)
519	520	AM_RANGE(0x10,0x10) AM_READ_PORT("DSWC")
520		AM_RANGE(0x11,0x11) AM_READ_PORT("SYSA") AM_WRITE_LEGACY(mux_w)
521		AM_RANGE(0x12,0x12) AM_MIRROR(0xe8) AM_READ_PORT("DSWA") AM_WRITE_LEGACY(royalqn_blitter_0_w)
522		AM_RANGE(0x13,0x13) AM_MIRROR(0xe8) AM_READ_PORT("DSWB") AM_WRITE_LEGACY(royalqn_blitter_1_w)
523		AM_RANGE(0x14,0x14) AM_MIRROR(0xe8) AM_READNOP AM_WRITE_LEGACY(royalqn_blitter_2_w)
	521	AM_RANGE(0x11,0x11) AM_READ_PORT("SYSA") AM_WRITE(mux_w)
	522	AM_RANGE(0x12,0x12) AM_MIRROR(0xe8) AM_READ_PORT("DSWA") AM_WRITE(royalqn_blitter_0_w)
	523	AM_RANGE(0x13,0x13) AM_MIRROR(0xe8) AM_READ_PORT("DSWB") AM_WRITE(royalqn_blitter_1_w)
	524	AM_RANGE(0x14,0x14) AM_MIRROR(0xe8) AM_READNOP AM_WRITE(royalqn_blitter_2_w)
524	525	ADDRESS_MAP_END
525	526
526	527	static ADDRESS_MAP_START( sexygal_nsc_map, AS_PROGRAM, 8, nightgal_state )
527	528	AM_RANGE(0x0000, 0x007f) AM_RAM
528		AM_RANGE(0x0080, 0x0080) AM_READ_LEGACY(blitter_status_r)
529		AM_RANGE(0x0081, 0x0083) AM_READ_LEGACY(royalqn_nsc_blit_r)
530		AM_RANGE(0x0080, 0x0086) AM_WRITE_LEGACY(sexygal_nsc_true_blitter_w)
	529	AM_RANGE(0x0080, 0x0080) AM_READ(blitter_status_r)
	530	AM_RANGE(0x0081, 0x0083) AM_READ(royalqn_nsc_blit_r)
	531	AM_RANGE(0x0080, 0x0086) AM_WRITE(sexygal_nsc_true_blitter_w)
531	532
532		AM_RANGE(0x00a0, 0x00af) AM_WRITE_LEGACY(blit_true_vregs_w)
	533	AM_RANGE(0x00a0, 0x00af) AM_WRITE(blit_true_vregs_w)
533	534	AM_RANGE(0x00b0, 0x00b0) AM_WRITENOP // bltflip register
534	535
535		AM_RANGE(0x1000, 0x13ff) AM_MIRROR(0x2c00) AM_READWRITE_LEGACY(royalqn_comm_r, royalqn_comm_w) AM_BASE(m_comms_ram)
	536	AM_RANGE(0x1000, 0x13ff) AM_MIRROR(0x2c00) AM_READWRITE(royalqn_comm_r, royalqn_comm_w) AM_BASE(m_comms_ram)
536	537	AM_RANGE(0xc000, 0xffff) AM_ROM AM_WRITENOP
537	538	ADDRESS_MAP_END
538	539
r14845	r14846
543	544	static ADDRESS_MAP_START( royalqn_map, AS_PROGRAM, 8, nightgal_state )
544	545	AM_RANGE(0x0000, 0x7fff) AM_ROM
545	546	AM_RANGE(0x8000, 0xbfff) AM_NOP
546		AM_RANGE(0xc000, 0xdfff) AM_READWRITE_LEGACY(royalqn_comm_r, royalqn_comm_w) AM_BASE(m_comms_ram)
	547	AM_RANGE(0xc000, 0xdfff) AM_READWRITE(royalqn_comm_r, royalqn_comm_w) AM_BASE(m_comms_ram)
547	548	AM_RANGE(0xe000, 0xffff) AM_RAM
548	549	ADDRESS_MAP_END
549	550
r14845	r14846
552	553	AM_RANGE(0x01,0x01) AM_MIRROR(0xec) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
553	554	AM_RANGE(0x02,0x03) AM_MIRROR(0xec) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
554	555	AM_RANGE(0x10,0x10) AM_MIRROR(0xe8) AM_READ_PORT("DSWC") AM_WRITENOP //AM_WRITE_LEGACY(output_w)
555		AM_RANGE(0x11,0x11) AM_MIRROR(0xe8) AM_READ_PORT("SYSA") AM_WRITE_LEGACY(mux_w)
556		AM_RANGE(0x12,0x12) AM_MIRROR(0xe8) AM_READ_PORT("DSWA") AM_WRITE_LEGACY(royalqn_blitter_0_w)
557		AM_RANGE(0x13,0x13) AM_MIRROR(0xe8) AM_READ_PORT("DSWB") AM_WRITE_LEGACY(royalqn_blitter_1_w)
558		AM_RANGE(0x14,0x14) AM_MIRROR(0xe8) AM_READNOP AM_WRITE_LEGACY(royalqn_blitter_2_w)
	556	AM_RANGE(0x11,0x11) AM_MIRROR(0xe8) AM_READ_PORT("SYSA") AM_WRITE(mux_w)
	557	AM_RANGE(0x12,0x12) AM_MIRROR(0xe8) AM_READ_PORT("DSWA") AM_WRITE(royalqn_blitter_0_w)
	558	AM_RANGE(0x13,0x13) AM_MIRROR(0xe8) AM_READ_PORT("DSWB") AM_WRITE(royalqn_blitter_1_w)
	559	AM_RANGE(0x14,0x14) AM_MIRROR(0xe8) AM_READNOP AM_WRITE(royalqn_blitter_2_w)
559	560	AM_RANGE(0x15,0x15) AM_MIRROR(0xe8) AM_NOP
560	561	AM_RANGE(0x16,0x16) AM_MIRROR(0xe8) AM_NOP
561	562	AM_RANGE(0x17,0x17) AM_MIRROR(0xe8) AM_NOP
r14845	r14846
563	564
564	565	static ADDRESS_MAP_START( royalqn_nsc_map, AS_PROGRAM, 8, nightgal_state )
565	566	AM_RANGE(0x0000, 0x007f) AM_RAM
566		AM_RANGE(0x0080, 0x0080) AM_READ_LEGACY(blitter_status_r)
567		AM_RANGE(0x0081, 0x0083) AM_READ_LEGACY(royalqn_nsc_blit_r)
568		AM_RANGE(0x0080, 0x0086) AM_WRITE_LEGACY(nsc_true_blitter_w)
	567	AM_RANGE(0x0080, 0x0080) AM_READ(blitter_status_r)
	568	AM_RANGE(0x0081, 0x0083) AM_READ(royalqn_nsc_blit_r)
	569	AM_RANGE(0x0080, 0x0086) AM_WRITE(nsc_true_blitter_w)
569	570
570		AM_RANGE(0x00a0, 0x00af) AM_WRITE_LEGACY(blit_true_vregs_w)
	571	AM_RANGE(0x00a0, 0x00af) AM_WRITE(blit_true_vregs_w)
571	572	AM_RANGE(0x00b0, 0x00b0) AM_WRITENOP // bltflip register
572	573
573		AM_RANGE(0x1000, 0x13ff) AM_MIRROR(0x2c00) AM_READWRITE_LEGACY(royalqn_comm_r,royalqn_comm_w)
	574	AM_RANGE(0x1000, 0x13ff) AM_MIRROR(0x2c00) AM_READWRITE(royalqn_comm_r,royalqn_comm_w)
574	575	AM_RANGE(0x4000, 0x4000) AM_NOP
575	576	AM_RANGE(0x8000, 0x8000) AM_NOP //open bus or protection check
576	577	AM_RANGE(0xc000, 0xdfff) AM_MIRROR(0x2000) AM_ROM

src/mame/drivers/maygayv1.c

r14845	r14846
226	226	device_t *m_duart68681;
227	227	i82716_t m_i82716;
228	228	i8279_t m_i8279;
	229	DECLARE_WRITE16_MEMBER(i82716_w);
	230	DECLARE_READ16_MEMBER(i82716_r);
	231	DECLARE_WRITE16_MEMBER(write_odd);
	232	DECLARE_READ16_MEMBER(read_odd);
	233	DECLARE_READ16_MEMBER(maygay_8279_r);
	234	DECLARE_WRITE16_MEMBER(maygay_8279_w);
	235	DECLARE_WRITE16_MEMBER(vsync_int_ctrl);
	236	DECLARE_READ8_MEMBER(mcu_r);
	237	DECLARE_WRITE8_MEMBER(mcu_w);
229	238	};
230	239
231	240
232	241
233	242
234		static WRITE16_HANDLER( i82716_w )
	243	WRITE16_MEMBER(maygayv1_state::i82716_w)
235	244	{
236		maygayv1_state *state = space->machine().driver_data<maygayv1_state>();
237		i82716_t &i82716 = state->m_i82716;
	245	i82716_t &i82716 = m_i82716;
238	246	// Accessing register window?
239	247	if ((VREG(RWBA) & 0xfff0) == (offset & 0xfff0))
240	248	{
r14845	r14846
251	259	}
252	260	}
253	261
254		static READ16_HANDLER( i82716_r )
	262	READ16_MEMBER(maygayv1_state::i82716_r)
255	263	{
256		maygayv1_state *state = space->machine().driver_data<maygayv1_state>();
257		i82716_t &i82716 = state->m_i82716;
	264	i82716_t &i82716 = m_i82716;
258	265	// Accessing register window?
259	266	if ((VREG(RWBA) & ~0xf) == (offset & ~0xf))
260	267	{
r14845	r14846
469	476
470	477
471	478
472		static WRITE16_HANDLER( write_odd )
	479	WRITE16_MEMBER(maygayv1_state::write_odd)
473	480	{
474	481	}
475	482
476	483	//;860008 is a latch of some sort
477		static READ16_HANDLER( read_odd )
	484	READ16_MEMBER(maygayv1_state::read_odd)
478	485	{
479	486	return 0;
480	487	}
r14845	r14846
509	516	}
510	517	}
511	518
512		static READ16_HANDLER( maygay_8279_r )
	519	READ16_MEMBER(maygayv1_state::maygay_8279_r)
513	520	{
514		maygayv1_state *state = space->machine().driver_data<maygayv1_state>();
515		i8279_t &i8279 = state->m_i8279;
	521	i8279_t &i8279 = m_i8279;
516	522	static const char *const portnames[] = { "STROBE1","STROBE2","STROBE3","STROBE4","STROBE5","STROBE6","STROBE7","STROBE8" };
517	523	UINT8 result = 0xff;
518	524	UINT8 addr;
r14845	r14846
526	532	case 0x40:
527	533	addr = i8279.command & 0x07;
528	534
529		result = input_port_read(space->machine(), portnames[addr]);
	535	result = input_port_read(machine(), portnames[addr]);
530	536
531	537	/* handle autoincrement */
532	538	if (i8279.command & 0x10)
r14845	r14846
557	563	}
558	564
559	565
560		static WRITE16_HANDLER( maygay_8279_w )
	566	WRITE16_MEMBER(maygayv1_state::maygay_8279_w)
561	567	{
562		maygayv1_state *state = space->machine().driver_data<maygayv1_state>();
563		i8279_t &i8279 = state->m_i8279;
	568	i8279_t &i8279 = m_i8279;
564	569	UINT8 addr;
565	570
566	571	data >>= 8;
r14845	r14846
660	665
661	666
662	667
663		static WRITE16_HANDLER( vsync_int_ctrl )
	668	WRITE16_MEMBER(maygayv1_state::vsync_int_ctrl)
664	669	{
665		maygayv1_state *state = space->machine().driver_data<maygayv1_state>();
666		state->m_vsync_latch_preset = data & 0x0100;
	670	m_vsync_latch_preset = data & 0x0100;
667	671
668	672	// Active low
669		if (!(state->m_vsync_latch_preset))
670		cputag_set_input_line(space->machine(), "maincpu", 3, CLEAR_LINE);
	673	if (!(m_vsync_latch_preset))
	674	cputag_set_input_line(machine(), "maincpu", 3, CLEAR_LINE);
671	675	}
672	676
673	677	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 16, maygayv1_state )
674	678	AM_RANGE(0x000000, 0x07ffff) AM_ROM
675	679	AM_RANGE(0x080000, 0x083fff) AM_RAM AM_SHARE("nvram")
676	680	AM_RANGE(0x100000, 0x17ffff) AM_ROM AM_REGION("maincpu", 0x80000)
677		AM_RANGE(0x820000, 0x820003) AM_READWRITE_LEGACY(maygay_8279_r, maygay_8279_w)
	681	AM_RANGE(0x820000, 0x820003) AM_READWRITE(maygay_8279_r, maygay_8279_w)
678	682	AM_RANGE(0x800000, 0x800003) AM_DEVWRITE8_LEGACY("ymsnd", ym2413_w, 0xff00 )
679		AM_RANGE(0x860000, 0x86000d) AM_READWRITE_LEGACY(read_odd, write_odd)
680		AM_RANGE(0x86000e, 0x86000f) AM_WRITE_LEGACY(vsync_int_ctrl)
681		AM_RANGE(0x880000, 0x89ffff) AM_READWRITE_LEGACY(i82716_r, i82716_w)
	683	AM_RANGE(0x860000, 0x86000d) AM_READWRITE(read_odd, write_odd)
	684	AM_RANGE(0x86000e, 0x86000f) AM_WRITE(vsync_int_ctrl)
	685	AM_RANGE(0x880000, 0x89ffff) AM_READWRITE(i82716_r, i82716_w)
682	686	AM_RANGE(0x8a0000, 0x8a001f) AM_DEVREADWRITE8_LEGACY("duart68681", duart68681_r, duart68681_w, 0xff)
683	687	AM_RANGE(0x8c0000, 0x8c000f) AM_DEVREADWRITE8("pia", pia6821_device, read, write, 0xff)
684	688	ADDRESS_MAP_END
r14845	r14846
719	723
720	724	*/
721	725
722		static READ8_HANDLER( mcu_r )
	726	READ8_MEMBER(maygayv1_state::mcu_r)
723	727	{
724		maygayv1_state *state = space->machine().driver_data<maygayv1_state>();
725	728	switch (offset)
726	729	{
727	730	case 1:
728	731	{
729		if ( !BIT(state->m_p3, 4) )
730		return (input_port_read(space->machine(), "REEL"));   // Reels???
	732	if ( !BIT(m_p3, 4) )
	733	return (input_port_read(machine(), "REEL"));   // Reels???
731	734	else
732	735	return 0;
733	736	}
r14845	r14846
737	740	return 0;
738	741	}
739	742
740		static WRITE8_HANDLER( mcu_w )
	743	WRITE8_MEMBER(maygayv1_state::mcu_w)
741	744	{
742		maygayv1_state *state = space->machine().driver_data<maygayv1_state>();
743	745	logerror("O %x D %x",offset,data);
744	746
745	747	switch (offset)
746	748	{
747	749	// Bottom nibble = UPD
748	750	case 1:
749		state->m_p1 = data;
	751	m_p1 = data;
750	752	//          upd7759_msg_w(0, data);//?
751	753	break;
752	754	case 3:
753	755	upd7759_reset_w (0, BIT(data, 2));
754	756	upd7759_start_w(0, BIT(data, 6));
755	757
756		//          if ( !BIT(state->m_p3, 7) && BIT(data, 7) )
	758	//          if ( !BIT(m_p3, 7) && BIT(data, 7) )
757	759	// P1 propagates to outputs
758	760
759		state->m_p3 = data;
	761	m_p3 = data;
760	762	break;
761	763	}
762	764	}
r14845	r14846
771	773	ADDRESS_MAP_END
772	774
773	775	static ADDRESS_MAP_START( sound_io, AS_IO, 8, maygayv1_state )
774		AM_RANGE(0x00, 0xff) AM_READWRITE_LEGACY(mcu_r, mcu_w)
	776	AM_RANGE(0x00, 0xff) AM_READWRITE(mcu_r, mcu_w)
775	777	ADDRESS_MAP_END
776	778
777	779

src/mame/drivers/attckufo.c

r14845	r14846
61	61	/* devices */
62	62	required_device<cpu_device> m_maincpu;
63	63	required_device<mos6560_device> m_mos6560;
	64	DECLARE_READ8_MEMBER(attckufo_io_r);
	65	DECLARE_WRITE8_MEMBER(attckufo_io_w);
64	66	};
65	67
66	68
r14845	r14846
95	97	}
96	98
97	99
98		static READ8_HANDLER(attckufo_io_r)
	100	READ8_MEMBER(attckufo_state::attckufo_io_r)
99	101	{
100	102	switch(offset)
101	103	{
102		case 0: return input_port_read(space->machine(), "DSW");
103		case 2: return input_port_read(space->machine(), "INPUT");
	104	case 0: return input_port_read(machine(), "DSW");
	105	case 2: return input_port_read(machine(), "INPUT");
104	106	}
105	107	return 0xff;
106	108	}
107	109
108	110
109		static WRITE8_HANDLER(attckufo_io_w)
	111	WRITE8_MEMBER(attckufo_state::attckufo_io_w)
110	112	{
111	113	/*
112	114	offset, data:
r14845	r14846
121	123	ADDRESS_MAP_GLOBAL_MASK(0x3fff)
122	124	AM_RANGE(0x0000, 0x0fff) AM_RAM AM_BASE(m_mainram)
123	125	AM_RANGE(0x1000, 0x100f) AM_DEVREADWRITE_LEGACY("mos6560", mos6560_port_r, mos6560_port_w)
124		AM_RANGE(0x1400, 0x1403) AM_READWRITE_LEGACY(attckufo_io_r, attckufo_io_w)
	126	AM_RANGE(0x1400, 0x1403) AM_READWRITE(attckufo_io_r, attckufo_io_w)
125	127	AM_RANGE(0x1c00, 0x1fff) AM_RAM AM_BASE(m_tileram)
126	128	AM_RANGE(0x2000, 0x3fff) AM_ROM
127	129	ADDRESS_MAP_END

src/mame/drivers/jongkyo.c

r14845	r14846
45	45	/* memory pointers */
46	46	UINT8 *  m_videoram;
47	47	UINT8    m_videoram2[0x4000];
	48	DECLARE_WRITE8_MEMBER(bank_select_w);
	49	DECLARE_WRITE8_MEMBER(mux_w);
	50	DECLARE_WRITE8_MEMBER(jongkyo_coin_counter_w);
	51	DECLARE_WRITE8_MEMBER(videoram2_w);
	52	DECLARE_WRITE8_MEMBER(unknown_w);
48	53	};
49	54
50	55
r14845	r14846
109	114	*
110	115	*************************************/
111	116
112		static WRITE8_HANDLER( bank_select_w )
	117	WRITE8_MEMBER(jongkyo_state::bank_select_w)
113	118	{
114		jongkyo_state *state = space->machine().driver_data<jongkyo_state>();
115	119	int mask = 1 << (offset >> 1);
116	120
117		state->m_rom_bank &= ~mask;
	121	m_rom_bank &= ~mask;
118	122
119	123	if (offset & 1)
120		state->m_rom_bank |= mask;
	124	m_rom_bank |= mask;
121	125
122		memory_set_bank(space->machine(), "bank1", state->m_rom_bank);
	126	memory_set_bank(machine(), "bank1", m_rom_bank);
123	127	}
124	128
125		static WRITE8_HANDLER( mux_w )
	129	WRITE8_MEMBER(jongkyo_state::mux_w)
126	130	{
127		jongkyo_state *state = space->machine().driver_data<jongkyo_state>();
128		state->m_mux_data = ~data;
129		//  printf("%02x\n", state->m_mux_data);
	131	m_mux_data = ~data;
	132	//  printf("%02x\n", m_mux_data);
130	133	}
131	134
132		static WRITE8_HANDLER( jongkyo_coin_counter_w )
	135	WRITE8_MEMBER(jongkyo_state::jongkyo_coin_counter_w)
133	136	{
134	137	/* bit 1 = coin counter */
135		coin_counter_w(space->machine(), 0, data & 2);
	138	coin_counter_w(machine(), 0, data & 2);
136	139
137	140	/* bit 2 always set? */
138	141	}
r14845	r14846
177	180	input_port_read(device->machine(), "PL2_4") & input_port_read(device->machine(), "PL2_5") & input_port_read(device->machine(), "PL2_6")) | coin_port;
178	181	}
179	182
180		static WRITE8_HANDLER( videoram2_w )
	183	WRITE8_MEMBER(jongkyo_state::videoram2_w)
181	184	{
182		jongkyo_state *state = space->machine().driver_data<jongkyo_state>();
183		state->m_videoram2[offset] = data;
	185	m_videoram2[offset] = data;
184	186	}
185	187
186		static WRITE8_HANDLER( unknown_w )
	188	WRITE8_MEMBER(jongkyo_state::unknown_w)
187	189	{
188	190	switch (offset)
189	191	{
r14845	r14846
218	220	*************************************/
219	221
220	222	static ADDRESS_MAP_START( jongkyo_memmap, AS_PROGRAM, 8, jongkyo_state )
221		AM_RANGE(0x0000, 0x3fff) AM_ROM AM_WRITE_LEGACY(videoram2_w) // wrong, this doesn't seem to be video ram on write..
	223	AM_RANGE(0x0000, 0x3fff) AM_ROM AM_WRITE(videoram2_w) // wrong, this doesn't seem to be video ram on write..
222	224	AM_RANGE(0x4000, 0x6bff) AM_ROM // fixed rom
223	225	AM_RANGE(0x6c00, 0x6fff) AM_ROMBANK("bank1")   // banked (8 banks)
224	226	AM_RANGE(0x7000, 0x77ff) AM_RAM
r14845	r14846
232	234	AM_RANGE(0x01, 0x01) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
233	235	AM_RANGE(0x02, 0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
234	236
235		AM_RANGE(0x10, 0x10) AM_READ_PORT("DSW") AM_WRITE_LEGACY(jongkyo_coin_counter_w)
236		AM_RANGE(0x11, 0x11) AM_READ_PORT("IN0") AM_WRITE_LEGACY(mux_w)
	237	AM_RANGE(0x10, 0x10) AM_READ_PORT("DSW") AM_WRITE(jongkyo_coin_counter_w)
	238	AM_RANGE(0x11, 0x11) AM_READ_PORT("IN0") AM_WRITE(mux_w)
237	239	// W 11 select keyboard row (fe fd fb f7)
238		AM_RANGE(0x40, 0x45) AM_WRITE_LEGACY(bank_select_w)
239		AM_RANGE(0x46, 0x4f) AM_WRITE_LEGACY(unknown_w)
	240	AM_RANGE(0x40, 0x45) AM_WRITE(bank_select_w)
	241	AM_RANGE(0x46, 0x4f) AM_WRITE(unknown_w)
240	242	ADDRESS_MAP_END
241	243
242	244	/*************************************

src/mame/drivers/littlerb.c

r14845	r14846
100	100	required_device<cpu_device> m_maincpu;
101	101	required_device<dac_device> m_dacl;
102	102	required_device<dac_device> m_dacr;
	103	DECLARE_WRITE16_MEMBER(region4_w);
	104	DECLARE_READ16_MEMBER(buffer_status_r);
	105	DECLARE_READ16_MEMBER(littlerb_vdp_r);
	106	DECLARE_WRITE16_MEMBER(littlerb_vdp_w);
	107	DECLARE_WRITE16_MEMBER(littlerb_l_sound_w);
	108	DECLARE_WRITE16_MEMBER(littlerb_r_sound_w);
103	109	};
104	110
105	111
106		static WRITE16_HANDLER( region4_w )
	112	WRITE16_MEMBER(littlerb_state::region4_w)
107	113	{
108		littlerb_state *state = space->machine().driver_data<littlerb_state>();
109		COMBINE_DATA(&state->m_region4[offset]);
	114	COMBINE_DATA(&m_region4[offset]);
110	115	}
111	116
112		static READ16_HANDLER( buffer_status_r )
	117	READ16_MEMBER(littlerb_state::buffer_status_r)
113	118	{
114	119	return 0;
115	120	}
r14845	r14846
125	130	AM_RANGE(0x00800002 ,0x00800003) AM_DEVWRITE8("^ramdac", ramdac_device, pal_w,   0x00ff)
126	131	AM_RANGE(0x00800004 ,0x00800005) AM_DEVWRITE8("^ramdac", ramdac_device, mask_w,  0x00ff)
127	132
128		AM_RANGE(0x1ff80804, 0x1ff80805) AM_READ_LEGACY(buffer_status_r)
	133	AM_RANGE(0x1ff80804, 0x1ff80805) AM_READ(buffer_status_r)
129	134	// most gfx end up here including the sprite list
130		AM_RANGE(0x1ff80000, 0x1fffffff) AM_RAM_WRITE_LEGACY(region4_w)  AM_BASE(m_region4)
	135	AM_RANGE(0x1ff80000, 0x1fffffff) AM_RAM_WRITE(region4_w)  AM_BASE(m_region4)
131	136	ADDRESS_MAP_END
132	137
133	138	static ADDRESS_MAP_START( ramdac_map, AS_0, 8, littlerb_state )
r14845	r14846
223	228	state->m_write_address = state->m_vdp_address_low | state->m_vdp_address_high<<16;
224	229	}
225	230
226		static READ16_HANDLER( littlerb_vdp_r )
	231	READ16_MEMBER(littlerb_state::littlerb_vdp_r)
227	232	{
228		littlerb_state *state = space->machine().driver_data<littlerb_state>();
229		logerror("%06x littlerb_vdp_r offs %04x mask %04x (address %08x)\n", cpu_get_pc(&space->device()), offset, mem_mask, state->m_write_address);
	233	logerror("%06x littlerb_vdp_r offs %04x mask %04x (address %08x)\n", cpu_get_pc(&space.device()), offset, mem_mask, m_write_address);
230	234	UINT16 res;
231	235
232	236	switch (offset & 3)
233	237	{
234		case 0: res = state->m_vdp_address_low; break;
235		case 1: res = state->m_vdp_address_high; break;
236		case 2: res = littlerb_data_read(space->machine(), mem_mask); break;
237		case 3: res = state->m_vdp_writemode; break;
	238	case 0: res = m_vdp_address_low; break;
	239	case 1: res = m_vdp_address_high; break;
	240	case 2: res = littlerb_data_read(machine(), mem_mask); break;
	241	case 3: res = m_vdp_writemode; break;
238	242	}
239	243
240	244	return res;
241	245	}
242	246
243	247	#define LOG_VDP 0
244		static WRITE16_HANDLER( littlerb_vdp_w )
	248	WRITE16_MEMBER(littlerb_state::littlerb_vdp_w)
245	249	{
246		littlerb_state *state = space->machine().driver_data<littlerb_state>();
247	250
248	251	if (offset!=2)
249	252	{
250		if (state->m_type2_writes)
	253	if (m_type2_writes)
251	254	{
252		if (state->m_type2_writes>2)
	255	if (m_type2_writes>2)
253	256	{
254	257	if (LOG_VDP) logerror("******************************* BIG WRITE OCCURRED BEFORE THIS!!! ****************************\n");
255		printf("big write occured with start %08x end %08x\n", state->m_write_address_laststart >> 3, state->m_write_address_lastend >> 3);
	258	printf("big write occured with start %08x end %08x\n", m_write_address_laststart >> 3, m_write_address_lastend >> 3);
256	259	}
257	260
258		if (LOG_VDP) logerror("~%06x previously wrote %08x data bytes\n", state->m_lasttype2pc, state->m_type2_writes*2);
259		state->m_type2_writes = 0;
	261	if (LOG_VDP) logerror("~%06x previously wrote %08x data bytes\n", m_lasttype2pc, m_type2_writes*2);
	262	m_type2_writes = 0;
260	263	}
261	264
262		if (LOG_VDP) logerror("%06x littlerb_vdp_w offs %04x data %04x mask %04x\n", cpu_get_pc(&space->device()), offset, data, mem_mask);
	265	if (LOG_VDP) logerror("%06x littlerb_vdp_w offs %04x data %04x mask %04x\n", cpu_get_pc(&space.device()), offset, data, mem_mask);
263	266	}
264	267	else
265	268	{
266	269	if (mem_mask==0xffff)
267	270	{
268		if (state->m_type2_writes==0)
	271	if (m_type2_writes==0)
269	272	{
270		if (LOG_VDP) logerror("data write started %06x %04x data %04x mask %04x\n", cpu_get_pc(&space->device()), offset, data, mem_mask);
	273	if (LOG_VDP) logerror("data write started %06x %04x data %04x mask %04x\n", cpu_get_pc(&space.device()), offset, data, mem_mask);
271	274	}
272		if (state->m_type2_writes==0) state->m_write_address_laststart = state->m_write_address;
273		state->m_write_address_lastend = state->m_write_address;
274		state->m_type2_writes++;
275		state->m_lasttype2pc = cpu_get_pc(&space->device());
	275	if (m_type2_writes==0) m_write_address_laststart = m_write_address;
	276	m_write_address_lastend = m_write_address;
	277	m_type2_writes++;
	278	m_lasttype2pc = cpu_get_pc(&space.device());
276	279	}
277	280	else
278	281	{
279		if (LOG_VDP) logerror("xxx %06x littlerb_vdp_w offs %04x data %04x mask %04x\n", cpu_get_pc(&space->device()), offset, data, mem_mask);
	282	if (LOG_VDP) logerror("xxx %06x littlerb_vdp_w offs %04x data %04x mask %04x\n", cpu_get_pc(&space.device()), offset, data, mem_mask);
280	283	}
281	284	}
282	285
r14845	r14846
284	287	switch (offset)
285	288	{
286	289	case 0:
287		COMBINE_DATA(&state->m_vdp_address_low);
288		littlerb_recalc_address(space->machine());
	290	COMBINE_DATA(&m_vdp_address_low);
	291	littlerb_recalc_address(machine());
289	292	break;
290	293
291	294	case 1:
292		COMBINE_DATA(&state->m_vdp_address_high);
293		littlerb_recalc_address(space->machine());
	295	COMBINE_DATA(&m_vdp_address_high);
	296	littlerb_recalc_address(machine());
294	297	break;
295	298
296	299
297	300	case 2:
298		littlerb_data_write(space->machine(), data, mem_mask);
	301	littlerb_data_write(machine(), data, mem_mask);
299	302	break;
300	303
301	304	case 3:
302		COMBINE_DATA(&state->m_vdp_writemode);
303		int mode = state->m_vdp_writemode;
	305	COMBINE_DATA(&m_vdp_writemode);
	306	int mode = m_vdp_writemode;
304	307	if ((mode!=0x3800) && (mode !=0x2000)) printf("WRITE MODE CHANGED TO %04x\n",mode);
305	308	break;
306	309
r14845	r14846
315	318	}
316	319
317	320	/* l is SFX, r is BGM (they doesn't seem to share the same data ROM) */
318		static WRITE16_HANDLER( littlerb_l_sound_w )
	321	WRITE16_MEMBER(littlerb_state::littlerb_l_sound_w)
319	322	{
320		littlerb_state *state = space->machine().driver_data<littlerb_state>();
321		state->m_sound_index_l = (data >> sound_data_shift(space->machine())) & 0xff;
322		state->m_sound_pointer_l = 0;
323		//popmessage("%04x %04x",state->m_sound_index_l,state->m_sound_index_r);
	323	m_sound_index_l = (data >> sound_data_shift(machine())) & 0xff;
	324	m_sound_pointer_l = 0;
	325	//popmessage("%04x %04x",m_sound_index_l,m_sound_index_r);
324	326	}
325	327
326		static WRITE16_HANDLER( littlerb_r_sound_w )
	328	WRITE16_MEMBER(littlerb_state::littlerb_r_sound_w)
327	329	{
328		littlerb_state *state = space->machine().driver_data<littlerb_state>();
329		state->m_sound_index_r = (data >> sound_data_shift(space->machine())) & 0xff;
330		state->m_sound_pointer_r = 0;
331		//popmessage("%04x %04x",state->m_sound_index_l,state->m_sound_index_r);
	330	m_sound_index_r = (data >> sound_data_shift(machine())) & 0xff;
	331	m_sound_pointer_r = 0;
	332	//popmessage("%04x %04x",m_sound_index_l,m_sound_index_r);
332	333	}
333	334
334	335	static ADDRESS_MAP_START( littlerb_main, AS_PROGRAM, 16, littlerb_state )
r14845	r14846
338	339	AM_RANGE(0x060004, 0x060007) AM_WRITENOP
339	340	AM_RANGE(0x000000, 0x0fffff) AM_ROM
340	341	AM_RANGE(0x200000, 0x203fff) AM_RAM // main ram?
341		AM_RANGE(0x700000, 0x700007) AM_READ_LEGACY(littlerb_vdp_r) AM_WRITE_LEGACY(littlerb_vdp_w)
342		AM_RANGE(0x740000, 0x740001) AM_WRITE_LEGACY(littlerb_l_sound_w)
343		AM_RANGE(0x760000, 0x760001) AM_WRITE_LEGACY(littlerb_r_sound_w)
	342	AM_RANGE(0x700000, 0x700007) AM_READ(littlerb_vdp_r) AM_WRITE(littlerb_vdp_w)
	343	AM_RANGE(0x740000, 0x740001) AM_WRITE(littlerb_l_sound_w)
	344	AM_RANGE(0x760000, 0x760001) AM_WRITE(littlerb_r_sound_w)
344	345	AM_RANGE(0x780000, 0x780001) AM_WRITENOP // generic outputs
345	346	AM_RANGE(0x7c0000, 0x7c0001) AM_READ_PORT("DSW")
346	347	AM_RANGE(0x7e0000, 0x7e0001) AM_READ_PORT("P1")

src/mame/drivers/namcos23.c

r14845	r14846
1377	1377	UINT8 m_im_rd;
1378	1378	UINT8 m_im_wr;
1379	1379	UINT8 m_s23_tssio_port_4;
	1380	DECLARE_WRITE32_MEMBER(namcos23_textram_w);
	1381	DECLARE_WRITE32_MEMBER(s23_txtchar_w);
	1382	DECLARE_WRITE32_MEMBER(namcos23_paletteram_w);
	1383	DECLARE_READ16_MEMBER(s23_c417_r);
	1384	DECLARE_WRITE16_MEMBER(s23_c417_w);
	1385	DECLARE_READ16_MEMBER(s23_c412_ram_r);
	1386	DECLARE_WRITE16_MEMBER(s23_c412_ram_w);
	1387	DECLARE_READ16_MEMBER(s23_c412_r);
	1388	DECLARE_WRITE16_MEMBER(s23_c412_w);
	1389	DECLARE_READ16_MEMBER(s23_c421_ram_r);
	1390	DECLARE_WRITE16_MEMBER(s23_c421_ram_w);
	1391	DECLARE_READ16_MEMBER(s23_c421_r);
	1392	DECLARE_WRITE16_MEMBER(s23_c421_w);
	1393	DECLARE_WRITE16_MEMBER(s23_ctl_w);
	1394	DECLARE_READ16_MEMBER(s23_ctl_r);
	1395	DECLARE_WRITE16_MEMBER(s23_c361_w);
	1396	DECLARE_READ16_MEMBER(s23_c361_r);
	1397	DECLARE_READ16_MEMBER(s23_c422_r);
	1398	DECLARE_WRITE16_MEMBER(s23_c422_w);
	1399	DECLARE_WRITE32_MEMBER(s23_mcuen_w);
	1400	DECLARE_READ32_MEMBER(gorgon_sharedram_r);
	1401	DECLARE_WRITE32_MEMBER(gorgon_sharedram_w);
	1402	DECLARE_READ32_MEMBER(s23_unk_status_r);
	1403	DECLARE_READ32_MEMBER(p3d_r);
	1404	DECLARE_WRITE32_MEMBER(p3d_w);
	1405	DECLARE_READ32_MEMBER(gmen_trigger_sh2);
	1406	DECLARE_READ32_MEMBER(sh2_shared_r);
	1407	DECLARE_WRITE32_MEMBER(sh2_shared_w);
	1408	DECLARE_WRITE16_MEMBER(sharedram_sub_w);
	1409	DECLARE_READ16_MEMBER(sharedram_sub_r);
	1410	DECLARE_WRITE16_MEMBER(sub_interrupt_main_w);
	1411	DECLARE_READ8_MEMBER(s23_mcu_p8_r);
	1412	DECLARE_READ8_MEMBER(s23_mcu_pa_r);
	1413	DECLARE_WRITE8_MEMBER(s23_mcu_pa_w);
	1414	DECLARE_READ8_MEMBER(s23_mcu_rtc_r);
	1415	DECLARE_READ8_MEMBER(s23_mcu_portB_r);
	1416	DECLARE_WRITE8_MEMBER(s23_mcu_portB_w);
	1417	DECLARE_WRITE8_MEMBER(s23_mcu_settings_w);
	1418	DECLARE_READ8_MEMBER(s23_mcu_iob_r);
	1419	DECLARE_WRITE8_MEMBER(s23_mcu_iob_w);
	1420	DECLARE_READ8_MEMBER(s23_mcu_p6_r);
	1421	DECLARE_WRITE8_MEMBER(s23_mcu_p6_w);
	1422	DECLARE_READ8_MEMBER(s23_iob_mcu_r);
	1423	DECLARE_WRITE8_MEMBER(s23_iob_mcu_w);
	1424	DECLARE_READ8_MEMBER(s23_iob_p4_r);
	1425	DECLARE_WRITE8_MEMBER(s23_iob_p4_w);
	1426	DECLARE_READ8_MEMBER(s23_gun_r);
	1427	DECLARE_READ8_MEMBER(iob_r);
1380	1428	};
1381	1429
1382	1430
r14845	r14846
1400	1448	SET_TILE_INFO( 0, data&0x03ff, data>>12, TILE_FLIPYX((data&0x0c00)>>10) );
1401	1449	} /* TextTilemapGetInfo */
1402	1450
1403		static WRITE32_HANDLER( namcos23_textram_w )
	1451	WRITE32_MEMBER(namcos23_state::namcos23_textram_w)
1404	1452	{
1405		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1406		COMBINE_DATA( &state->m_textram[offset] );
1407		state->m_bgtilemap->mark_tile_dirty(offset*2);
1408		state->m_bgtilemap->mark_tile_dirty((offset*2)+1);
	1453	COMBINE_DATA( &m_textram[offset] );
	1454	m_bgtilemap->mark_tile_dirty(offset*2);
	1455	m_bgtilemap->mark_tile_dirty((offset*2)+1);
1409	1456	}
1410	1457
1411		static WRITE32_HANDLER( s23_txtchar_w )
	1458	WRITE32_MEMBER(namcos23_state::s23_txtchar_w)
1412	1459	{
1413		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1414		COMBINE_DATA(&state->m_charram[offset]);
1415		gfx_element_mark_dirty(space->machine().gfx[0], offset/32);
	1460	COMBINE_DATA(&m_charram[offset]);
	1461	gfx_element_mark_dirty(machine().gfx[0], offset/32);
1416	1462	}
1417	1463
1418	1464	static UINT8 nthbyte( const UINT32 *pSource, int offs )
r14845	r14846
1437	1483
1438	1484	/* each LONGWORD is 2 colors.  each OFFSET is 2 colors */
1439	1485
1440		static WRITE32_HANDLER( namcos23_paletteram_w )
	1486	WRITE32_MEMBER(namcos23_state::namcos23_paletteram_w)
1441	1487	{
1442		COMBINE_DATA( &space->machine().generic.paletteram.u32[offset] );
	1488	COMBINE_DATA( &machine().generic.paletteram.u32[offset] );
1443	1489
1444		UpdatePalette(space->machine(), (offset % (0x10000/4))*2);
	1490	UpdatePalette(machine(), (offset % (0x10000/4))*2);
1445	1491	}
1446	1492
1447		static READ16_HANDLER(s23_c417_r)
	1493	READ16_MEMBER(namcos23_state::s23_c417_r)
1448	1494	{
1449		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1450		c417_t &c417 = state->m_c417;
	1495	c417_t &c417 = m_c417;
1451	1496
1452	1497	switch(offset) {
1453	1498	/* According to timecrs2c, +0 is the status word with bits being:
r14845	r14846
1464	1509	1:  1st c435 busy (inverted)
1465	1510	0:  xcpreq
1466	1511	*/
1467		case 0: return 0x8e | (space->machine().primary_screen->vblank() ? 0x0000 : 0x8000);
	1512	case 0: return 0x8e | (machine().primary_screen->vblank() ? 0x0000 : 0x8000);
1468	1513	case 1: return c417.adr;
1469	1514	case 4:
1470		//      logerror("c417_r %04x = %04x (%08x, %08x)\n", c417.adr, c417.ram[c417.adr], cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1515	//      logerror("c417_r %04x = %04x (%08x, %08x)\n", c417.adr, c417.ram[c417.adr], cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1471	1516	return c417.ram[c417.adr];
1472	1517	case 5:
1473		if(c417.pointrom_adr >= state->m_ptrom_limit)
	1518	if(c417.pointrom_adr >= m_ptrom_limit)
1474	1519	return 0xffff;
1475		return state->m_ptrom[c417.pointrom_adr] >> 16;
	1520	return m_ptrom[c417.pointrom_adr] >> 16;
1476	1521	case 6:
1477		if(c417.pointrom_adr >= state->m_ptrom_limit)
	1522	if(c417.pointrom_adr >= m_ptrom_limit)
1478	1523	return 0xffff;
1479		return state->m_ptrom[c417.pointrom_adr];
	1524	return m_ptrom[c417.pointrom_adr];
1480	1525
1481	1526	}
1482	1527
1483		logerror("c417_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1528	logerror("c417_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1484	1529	return 0;
1485	1530	}
1486	1531
1487		static WRITE16_HANDLER(s23_c417_w)
	1532	WRITE16_MEMBER(namcos23_state::s23_c417_w)
1488	1533	{
1489		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1490		c417_t &c417 = state->m_c417;
	1534	c417_t &c417 = m_c417;
1491	1535
1492	1536	switch(offset) {
1493	1537	case 0:
r14845	r14846
1503	1547	c417.pointrom_adr = 0;
1504	1548	break;
1505	1549	case 4:
1506		//        logerror("c417_w %04x = %04x (%08x, %08x)\n", c417.adr, data, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1550	//        logerror("c417_w %04x = %04x (%08x, %08x)\n", c417.adr, data, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1507	1551	COMBINE_DATA(c417.ram + c417.adr);
1508	1552	break;
1509	1553	case 7:
1510	1554	logerror("c417_w: ack IRQ 2 (%x)\n", data);
1511		cputag_set_input_line(space->machine(), "maincpu", MIPS3_IRQ2, CLEAR_LINE);
	1555	cputag_set_input_line(machine(), "maincpu", MIPS3_IRQ2, CLEAR_LINE);
1512	1556	break;
1513	1557	default:
1514		logerror("c417_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1558	logerror("c417_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1515	1559	break;
1516	1560	}
1517	1561	}
1518	1562
1519		static READ16_HANDLER(s23_c412_ram_r)
	1563	READ16_MEMBER(namcos23_state::s23_c412_ram_r)
1520	1564	{
1521		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1522		c412_t &c412 = state->m_c412;
	1565	c412_t &c412 = m_c412;
1523	1566
1524		//  logerror("c412_ram_r %06x (%08x, %08x)\n", offset, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1567	//  logerror("c412_ram_r %06x (%08x, %08x)\n", offset, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1525	1568	if(offset < 0x100000)
1526	1569	return c412.sdram_a[offset & 0xfffff];
1527	1570	else if(offset < 0x200000)
r14845	r14846
1534	1577	return 0xffff;
1535	1578	}
1536	1579
1537		static WRITE16_HANDLER(s23_c412_ram_w)
	1580	WRITE16_MEMBER(namcos23_state::s23_c412_ram_w)
1538	1581	{
1539		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1540		c412_t &c412 = state->m_c412;
	1582	c412_t &c412 = m_c412;
1541	1583
1542		//  logerror("c412_ram_w %06x = %04x (%08x, %08x)\n", offset, data, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1584	//  logerror("c412_ram_w %06x = %04x (%08x, %08x)\n", offset, data, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1543	1585	if(offset < 0x100000)
1544	1586	COMBINE_DATA(c412.sdram_a + (offset & 0xfffff));
1545	1587	else if(offset < 0x200000)
r14845	r14846
1550	1592	COMBINE_DATA(c412.pczram  + (offset & 0x001ff));
1551	1593	}
1552	1594
1553		static READ16_HANDLER(s23_c412_r)
	1595	READ16_MEMBER(namcos23_state::s23_c412_r)
1554	1596	{
1555		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1556		c412_t &c412 = state->m_c412;
	1597	c412_t &c412 = m_c412;
1557	1598
1558	1599	switch(offset) {
1559	1600	case 3:
r14845	r14846
1564	1605	case 10: return s23_c412_ram_r(space, c412.adr, mem_mask);
1565	1606	}
1566	1607
1567		logerror("c412_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1608	logerror("c412_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1568	1609	return 0;
1569	1610	}
1570	1611
1571		static WRITE16_HANDLER(s23_c412_w)
	1612	WRITE16_MEMBER(namcos23_state::s23_c412_w)
1572	1613	{
1573		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1574		c412_t &c412 = state->m_c412;
	1614	c412_t &c412 = m_c412;
1575	1615
1576	1616	switch(offset) {
1577	1617	case 8: c412.adr = (data & mem_mask) | (c412.adr & (0xffffffff ^ mem_mask)); break;
1578	1618	case 9: c412.adr = ((data & mem_mask) << 16) | (c412.adr & (0xffffffff ^ (mem_mask << 16))); break;
1579	1619	case 10: s23_c412_ram_w(space, c412.adr, data, mem_mask); c412.adr += 2; break;
1580	1620	default:
1581		logerror("c412_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1621	logerror("c412_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1582	1622	break;
1583	1623	}
1584	1624	}
1585	1625
1586		static READ16_HANDLER(s23_c421_ram_r)
	1626	READ16_MEMBER(namcos23_state::s23_c421_ram_r)
1587	1627	{
1588		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1589		c421_t &c421 = state->m_c421;
	1628	c421_t &c421 = m_c421;
1590	1629
1591		//  logerror("c421_ram_r %06x (%08x, %08x)\n", offset, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1630	//  logerror("c421_ram_r %06x (%08x, %08x)\n", offset, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1592	1631	if(offset < 0x40000)
1593	1632	return c421.dram_a[offset & 0x3ffff];
1594	1633	else if(offset < 0x80000)
r14845	r14846
1599	1638	return 0xffff;
1600	1639	}
1601	1640
1602		static WRITE16_HANDLER(s23_c421_ram_w)
	1641	WRITE16_MEMBER(namcos23_state::s23_c421_ram_w)
1603	1642	{
1604		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1605		c421_t &c421 = state->m_c421;
	1643	c421_t &c421 = m_c421;
1606	1644
1607		//  logerror("c421_ram_w %06x = %04x (%08x, %08x)\n", offset, data, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1645	//  logerror("c421_ram_w %06x = %04x (%08x, %08x)\n", offset, data, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1608	1646	if(offset < 0x40000)
1609	1647	COMBINE_DATA(c421.dram_a + (offset & 0x3ffff));
1610	1648	else if(offset < 0x80000)
r14845	r14846
1613	1651	COMBINE_DATA(c421.sram   + (offset & 0x07fff));
1614	1652	}
1615	1653
1616		static READ16_HANDLER(s23_c421_r)
	1654	READ16_MEMBER(namcos23_state::s23_c421_r)
1617	1655	{
1618		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1619		c421_t &c421 = state->m_c421;
	1656	c421_t &c421 = m_c421;
1620	1657
1621	1658	switch(offset) {
1622	1659	case 0: return s23_c421_ram_r(space, c421.adr & 0xfffff, mem_mask);
r14845	r14846
1624	1661	case 3: return c421.adr;
1625	1662	}
1626	1663
1627		logerror("c421_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1664	logerror("c421_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1628	1665	return 0;
1629	1666	}
1630	1667
1631		static WRITE16_HANDLER(s23_c421_w)
	1668	WRITE16_MEMBER(namcos23_state::s23_c421_w)
1632	1669	{
1633		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1634		c421_t &c421 = state->m_c421;
	1670	c421_t &c421 = m_c421;
1635	1671
1636	1672	switch(offset) {
1637	1673	case 0: s23_c421_ram_w(space, c421.adr & 0xfffff, data, mem_mask); c421.adr += 2; break;
1638	1674	case 2: c421.adr = ((data & mem_mask) << 16) | (c421.adr & (0xffffffff ^ (mem_mask << 16))); break;
1639	1675	case 3: c421.adr = (data & mem_mask) | (c421.adr & (0xffffffff ^ mem_mask)); break;
1640	1676	default:
1641		logerror("c421_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1677	logerror("c421_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1642	1678	break;
1643	1679	}
1644	1680	}
1645	1681
1646		static WRITE16_HANDLER(s23_ctl_w)
	1682	WRITE16_MEMBER(namcos23_state::s23_ctl_w)
1647	1683	{
1648		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1649	1684	switch(offset) {
1650	1685	case 0: {
1651		if(state->m_ctl_led != (data & 0xff)) {
1652		state->m_ctl_led = data;
	1686	if(m_ctl_led != (data & 0xff)) {
	1687	m_ctl_led = data;
1653	1688	/*          logerror("LEDS %c%c%c%c%c%c%c%c\n",
1654		state->m_ctl_led & 0x80 ? '.' : '#',
1655		state->m_ctl_led & 0x40 ? '.' : '#',
1656		state->m_ctl_led & 0x20 ? '.' : '#',
1657		state->m_ctl_led & 0x10 ? '.' : '#',
1658		state->m_ctl_led & 0x08 ? '.' : '#',
1659		state->m_ctl_led & 0x04 ? '.' : '#',
1660		state->m_ctl_led & 0x02 ? '.' : '#',
1661		state->m_ctl_led & 0x01 ? '.' : '#');*/
	1689	m_ctl_led & 0x80 ? '.' : '#',
	1690	m_ctl_led & 0x40 ? '.' : '#',
	1691	m_ctl_led & 0x20 ? '.' : '#',
	1692	m_ctl_led & 0x10 ? '.' : '#',
	1693	m_ctl_led & 0x08 ? '.' : '#',
	1694	m_ctl_led & 0x04 ? '.' : '#',
	1695	m_ctl_led & 0x02 ? '.' : '#',
	1696	m_ctl_led & 0x01 ? '.' : '#');*/
1662	1697	}
1663	1698	break;
1664	1699	}
1665	1700
1666	1701	case 2: case 3:
1667	1702	// These may be coming from another CPU, in particular the I/O one
1668		state->m_ctl_inp_buffer[offset-2] = input_port_read(space->machine(), offset == 2 ? "P1" : "P2");
	1703	m_ctl_inp_buffer[offset-2] = input_port_read(machine(), offset == 2 ? "P1" : "P2");
1669	1704	break;
1670	1705	case 5:
1671		if(state->m_ctl_vbl_active) {
1672		state->m_ctl_vbl_active = false;
1673		device_set_input_line(&space->device(), MIPS3_IRQ0, CLEAR_LINE);
	1706	if(m_ctl_vbl_active) {
	1707	m_ctl_vbl_active = false;
	1708	device_set_input_line(&space.device(), MIPS3_IRQ0, CLEAR_LINE);
1674	1709	}
1675	1710	break;
1676	1711
1677	1712	case 6:   // gmen wars spams this heavily with 0 prior to starting the GMEN board test
1678	1713	if (data != 0)
1679		logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1714	logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1680	1715	break;
1681	1716
1682	1717	default:
1683		logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1718	logerror("ctl_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1684	1719	}
1685	1720	}
1686	1721
1687		static READ16_HANDLER(s23_ctl_r)
	1722	READ16_MEMBER(namcos23_state::s23_ctl_r)
1688	1723	{
1689		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1690	1724	switch(offset) {
1691	1725	// 0100 set freezes gorgon (polygon fifo flag)
1692		case 1: return 0x0000 | input_port_read(space->machine(), "DSW");
	1726	case 1: return 0x0000 | input_port_read(machine(), "DSW");
1693	1727	case 2: case 3: {
1694		UINT16 res = state->m_ctl_inp_buffer[offset-2] & 0x800 ? 0xffff : 0x0000;
1695		state->m_ctl_inp_buffer[offset-2] = (state->m_ctl_inp_buffer[offset-2] << 1) | 1;
	1728	UINT16 res = m_ctl_inp_buffer[offset-2] & 0x800 ? 0xffff : 0x0000;
	1729	m_ctl_inp_buffer[offset-2] = (m_ctl_inp_buffer[offset-2] << 1) | 1;
1696	1730	return res;
1697	1731	}
1698	1732	}
1699		logerror("ctl_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1733	logerror("ctl_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1700	1734	return 0xffff;
1701	1735	}
1702	1736
r14845	r14846
1713	1747	}
1714	1748	}
1715	1749
1716		static WRITE16_HANDLER(s23_c361_w)
	1750	WRITE16_MEMBER(namcos23_state::s23_c361_w)
1717	1751	{
1718		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1719		c361_t &c361 = state->m_c361;
	1752	c361_t &c361 = m_c361;
1720	1753
1721	1754	switch(offset) {
1722	1755	case 0:
1723		state->m_bgtilemap->set_scrollx(0, data&0xfff);
	1756	m_bgtilemap->set_scrollx(0, data&0xfff);
1724	1757	break;
1725	1758
1726	1759	case 1:
1727		state->m_bgtilemap->set_scrolly(0, data&0xfff);
	1760	m_bgtilemap->set_scrolly(0, data&0xfff);
1728	1761	break;
1729	1762
1730	1763	case 4:   // interrupt control
1731	1764	c361.scanline = data;
1732	1765	if (data == 0x1ff)
1733	1766	{
1734		cputag_set_input_line(space->machine(), "maincpu", MIPS3_IRQ1, CLEAR_LINE);
	1767	cputag_set_input_line(machine(), "maincpu", MIPS3_IRQ1, CLEAR_LINE);
1735	1768	c361.timer->adjust(attotime::never);
1736	1769	}
1737	1770	else
1738	1771	{
1739		c361.timer->adjust(space->machine().primary_screen->time_until_pos(c361.scanline));
	1772	c361.timer->adjust(machine().primary_screen->time_until_pos(c361.scanline));
1740	1773	}
1741	1774	break;
1742	1775
1743	1776	default:
1744		logerror("c361_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1777	logerror("c361_w %x, %04x @ %04x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1745	1778	}
1746	1779	}
1747	1780
1748		static READ16_HANDLER(s23_c361_r)
	1781	READ16_MEMBER(namcos23_state::s23_c361_r)
1749	1782	{
1750	1783	switch(offset) {
1751		case 5: return space->machine().primary_screen->vpos()*2 | (space->machine().primary_screen->vblank() ? 1 : 0);
1752		case 6: return space->machine().primary_screen->vblank();
	1784	case 5: return machine().primary_screen->vpos()*2 | (machine().primary_screen->vblank() ? 1 : 0);
	1785	case 6: return machine().primary_screen->vblank();
1753	1786	}
1754		logerror("c361_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	1787	logerror("c361_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
1755	1788	return 0xffff;
1756	1789	}
1757	1790
1758		static READ16_HANDLER(s23_c422_r)
	1791	READ16_MEMBER(namcos23_state::s23_c422_r)
1759	1792	{
1760		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1761		c422_t &c422 = state->m_c422;
	1793	c422_t &c422 = m_c422;
1762	1794	return c422.regs[offset];
1763	1795	}
1764	1796
1765		static WRITE16_HANDLER(s23_c422_w)
	1797	WRITE16_MEMBER(namcos23_state::s23_c422_w)
1766	1798	{
1767		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1768		c422_t &c422 = state->m_c422;
	1799	c422_t &c422 = m_c422;
1769	1800	switch (offset)
1770	1801	{
1771	1802	case 1:
1772	1803	if (data == 0xfffb)
1773	1804	{
1774	1805	logerror("c422_w: raise IRQ 3\n");
1775		cputag_set_input_line(space->machine(), "maincpu", MIPS3_IRQ3, ASSERT_LINE);
	1806	cputag_set_input_line(machine(), "maincpu", MIPS3_IRQ3, ASSERT_LINE);
1776	1807	}
1777	1808	else if (data == 0x000f)
1778	1809	{
1779	1810	logerror("c422_w: ack IRQ 3\n");
1780		cputag_set_input_line(space->machine(), "maincpu", MIPS3_IRQ3, CLEAR_LINE);
	1811	cputag_set_input_line(machine(), "maincpu", MIPS3_IRQ3, CLEAR_LINE);
1781	1812	}
1782	1813	break;
1783	1814
r14845	r14846
1791	1822	}
1792	1823
1793	1824	// as with System 22, we need to halt the MCU while checking shared RAM
1794		static WRITE32_HANDLER( s23_mcuen_w )
	1825	WRITE32_MEMBER(namcos23_state::s23_mcuen_w)
1795	1826	{
1796		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1797	1827	logerror("mcuen_w: mask %08x, data %08x\n", mem_mask, data);
1798	1828	if (mem_mask == 0x0000ffff)
1799	1829	{
r14845	r14846
1802	1832	logerror("S23: booting H8/3002\n");
1803	1833
1804	1834	// Panic Park: writing 1 when it's already running means reboot?
1805		if (state->m_s23_subcpu_running)
	1835	if (m_s23_subcpu_running)
1806	1836	{
1807		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_RESET, ASSERT_LINE);
	1837	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_RESET, ASSERT_LINE);
1808	1838	}
1809	1839
1810		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_RESET, CLEAR_LINE);
1811		state->m_s23_subcpu_running = 1;
	1840	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_RESET, CLEAR_LINE);
	1841	m_s23_subcpu_running = 1;
1812	1842	}
1813	1843	else
1814	1844	{
1815	1845	logerror("S23: stopping H8/3002\n");
1816		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_RESET, ASSERT_LINE);
1817		state->m_s23_subcpu_running = 0;
	1846	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_RESET, ASSERT_LINE);
	1847	m_s23_subcpu_running = 0;
1818	1848	}
1819	1849	}
1820	1850	}
r14845	r14846
1825	1855	off into the weeds, so we intercept
1826	1856	*/
1827	1857
1828		static READ32_HANDLER( gorgon_sharedram_r )
	1858	READ32_MEMBER(namcos23_state::gorgon_sharedram_r)
1829	1859	{
1830		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1831		return state->m_shared_ram[offset];
	1860	return m_shared_ram[offset];
1832	1861	}
1833	1862
1834		static WRITE32_HANDLER( gorgon_sharedram_w )
	1863	WRITE32_MEMBER(namcos23_state::gorgon_sharedram_w)
1835	1864	{
1836		namcos23_state *state = space->machine().driver_data<namcos23_state>();
1837		COMBINE_DATA(&state->m_shared_ram[offset]);
	1865	COMBINE_DATA(&m_shared_ram[offset]);
1838	1866
1839	1867	// hack for final furlong
1840	1868	if ((offset == 0x6000/4) && (data == 0) && (mem_mask == 0xff000000))
1841	1869	{
1842	1870	logerror("S23: Final Furlong hack stopping H8/3002\n");
1843		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_RESET, ASSERT_LINE);
	1871	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_RESET, ASSERT_LINE);
1844	1872	}
1845	1873	}
1846	1874
1847	1875	// Panic Park sits in a tight loop waiting for this AND 0002 to be non-zero (at PC=BFC02F00)
1848		static READ32_HANDLER( s23_unk_status_r )
	1876	READ32_MEMBER(namcos23_state::s23_unk_status_r)
1849	1877	{
1850	1878	return 0x00020002;
1851	1879	}
r14845	r14846
2145	2173	}
2146	2174	}
2147	2175
2148		static READ32_HANDLER( p3d_r )
	2176	READ32_MEMBER(namcos23_state::p3d_r)
2149	2177	{
2150	2178	switch(offset) {
2151	2179	case 0xa: return 1; // Busy flag
2152	2180	}
2153	2181
2154		logerror("p3d_r %02x @ %08x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	2182	logerror("p3d_r %02x @ %08x (%08x, %08x)\n", offset, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
2155	2183	return 0;
2156	2184	}
2157	2185
2158		static WRITE32_HANDLER( p3d_w)
	2186	WRITE32_MEMBER(namcos23_state::p3d_w)
2159	2187	{
2160		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2161	2188	switch(offset) {
2162		case 0x7: COMBINE_DATA(&state->m_p3d_address); return;
2163		case 0x8: COMBINE_DATA(&state->m_p3d_size); return;
	2189	case 0x7: COMBINE_DATA(&m_p3d_address); return;
	2190	case 0x8: COMBINE_DATA(&m_p3d_size); return;
2164	2191	case 0x9:
2165	2192	if(data & 1)
2166		p3d_dma(space, state->m_p3d_address, state->m_p3d_size);
	2193	p3d_dma(&space, m_p3d_address, m_p3d_size);
2167	2194	return;
2168	2195	case 0x17:
2169		cputag_set_input_line(space->machine(), "maincpu", MIPS3_IRQ1, CLEAR_LINE);
2170		state->m_c361.timer->adjust(attotime::never);
	2196	cputag_set_input_line(machine(), "maincpu", MIPS3_IRQ1, CLEAR_LINE);
	2197	m_c361.timer->adjust(attotime::never);
2171	2198	return;
2172	2199	}
2173		logerror("p3d_w %02x, %08x @ %08x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space->device()), (unsigned int)cpu_get_reg(&space->device(), MIPS3_R31));
	2200	logerror("p3d_w %02x, %08x @ %08x (%08x, %08x)\n", offset, data, mem_mask, cpu_get_pc(&space.device()), (unsigned int)cpu_get_reg(&space.device(), MIPS3_R31));
2174	2201	}
2175	2202
2176	2203	static void render_apply_transform(INT32 xi, INT32 yi, INT32 zi, const namcos23_render_entry *re, poly_vertex &pv)
r14845	r14846
2422	2449	static ADDRESS_MAP_START( gorgon_map, AS_PROGRAM, 32, namcos23_state )
2423	2450	ADDRESS_MAP_GLOBAL_MASK(0xfffffff)
2424	2451	AM_RANGE(0x00000000, 0x003fffff) AM_RAM
2425		AM_RANGE(0x01000000, 0x010000ff) AM_READWRITE_LEGACY(p3d_r, p3d_w )
2426		AM_RANGE(0x02000000, 0x0200000f) AM_READWRITE16_LEGACY(s23_c417_r, s23_c417_w, 0xffffffff )
2427		AM_RANGE(0x04400000, 0x0440ffff) AM_READWRITE_LEGACY(gorgon_sharedram_r, gorgon_sharedram_w ) AM_BASE(m_shared_ram)
	2452	AM_RANGE(0x01000000, 0x010000ff) AM_READWRITE(p3d_r, p3d_w )
	2453	AM_RANGE(0x02000000, 0x0200000f) AM_READWRITE16(s23_c417_r, s23_c417_w, 0xffffffff )
	2454	AM_RANGE(0x04400000, 0x0440ffff) AM_READWRITE(gorgon_sharedram_r, gorgon_sharedram_w ) AM_BASE(m_shared_ram)
2428	2455
2429		AM_RANGE(0x04c3ff08, 0x04c3ff0b) AM_WRITE_LEGACY(s23_mcuen_w )
	2456	AM_RANGE(0x04c3ff08, 0x04c3ff0b) AM_WRITE(s23_mcuen_w )
2430	2457	AM_RANGE(0x04c3ff0c, 0x04c3ff0f) AM_RAM
2431	2458
2432	2459	AM_RANGE(0x06080000, 0x06081fff) AM_RAM
2433	2460
2434	2461	AM_RANGE(0x06108000, 0x061087ff) AM_RAM      // GAMMA (C404-3S)
2435		AM_RANGE(0x06110000, 0x0613ffff) AM_RAM_WRITE_LEGACY(namcos23_paletteram_w ) AM_BASE_GENERIC(paletteram)
2436		AM_RANGE(0x06400000, 0x06403fff) AM_RAM_WRITE_LEGACY(s23_txtchar_w ) AM_BASE(m_charram)   // text layer characters
	2462	AM_RANGE(0x06110000, 0x0613ffff) AM_RAM_WRITE(namcos23_paletteram_w ) AM_BASE_GENERIC(paletteram)
	2463	AM_RANGE(0x06400000, 0x06403fff) AM_RAM_WRITE(s23_txtchar_w ) AM_BASE(m_charram)   // text layer characters
2437	2464	AM_RANGE(0x06404000, 0x0641dfff) AM_RAM
2438		AM_RANGE(0x0641e000, 0x0641ffff) AM_RAM_WRITE_LEGACY(namcos23_textram_w ) AM_BASE(m_textram)
	2465	AM_RANGE(0x0641e000, 0x0641ffff) AM_RAM_WRITE(namcos23_textram_w ) AM_BASE(m_textram)
2439	2466
2440	2467	AM_RANGE(0x08000000, 0x087fffff) AM_ROM AM_REGION("data", 0)   // data ROMs
2441	2468
2442	2469	AM_RANGE(0x0c000000, 0x0c00ffff) AM_RAM   AM_SHARE("nvram") // BACKUP
2443	2470
2444		AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16_LEGACY(s23_ctl_r, s23_ctl_w, 0xffffffff ) // write for LEDs at d000000, watchdog at d000004
	2471	AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16(s23_ctl_r, s23_ctl_w, 0xffffffff ) // write for LEDs at d000000, watchdog at d000004
2445	2472
2446		AM_RANGE(0x0f000000, 0x0f000003) AM_READ_LEGACY(s23_unk_status_r )
	2473	AM_RANGE(0x0f000000, 0x0f000003) AM_READ(s23_unk_status_r )
2447	2474
2448	2475	AM_RANGE(0x0f200000, 0x0f201fff) AM_RAM
2449	2476
r14845	r14846
2453	2480	static ADDRESS_MAP_START( ss23_map, AS_PROGRAM, 32, namcos23_state )
2454	2481	ADDRESS_MAP_GLOBAL_MASK(0xfffffff)
2455	2482	AM_RANGE(0x00000000, 0x00ffffff) AM_RAM
2456		AM_RANGE(0x01000000, 0x010000ff) AM_READWRITE_LEGACY(p3d_r, p3d_w )
2457		AM_RANGE(0x02000000, 0x0200000f) AM_READWRITE16_LEGACY(s23_c417_r, s23_c417_w, 0xffffffff )
	2483	AM_RANGE(0x01000000, 0x010000ff) AM_READWRITE(p3d_r, p3d_w )
	2484	AM_RANGE(0x02000000, 0x0200000f) AM_READWRITE16(s23_c417_r, s23_c417_w, 0xffffffff )
2458	2485	AM_RANGE(0x04400000, 0x0440ffff) AM_RAM AM_BASE(m_shared_ram)
2459		AM_RANGE(0x04c3ff08, 0x04c3ff0b) AM_WRITE_LEGACY(s23_mcuen_w )
	2486	AM_RANGE(0x04c3ff08, 0x04c3ff0b) AM_WRITE(s23_mcuen_w )
2460	2487	AM_RANGE(0x04c3ff0c, 0x04c3ff0f) AM_RAM
2461	2488	AM_RANGE(0x06000000, 0x0600ffff) AM_RAM AM_SHARE("nvram") // Backup
2462	2489	AM_RANGE(0x06200000, 0x06203fff) AM_RAM                             // C422
2463		AM_RANGE(0x06400000, 0x0640000f) AM_READWRITE16_LEGACY(s23_c422_r, s23_c422_w, 0xffffffff ) // C422 registers
2464		AM_RANGE(0x06800000, 0x06807fff) AM_RAM_WRITE_LEGACY(s23_txtchar_w ) AM_BASE(m_charram) // text layer characters (shown as CGRAM in POST)
	2490	AM_RANGE(0x06400000, 0x0640000f) AM_READWRITE16(s23_c422_r, s23_c422_w, 0xffffffff ) // C422 registers
	2491	AM_RANGE(0x06800000, 0x06807fff) AM_RAM_WRITE(s23_txtchar_w ) AM_BASE(m_charram) // text layer characters (shown as CGRAM in POST)
2465	2492	AM_RANGE(0x06804000, 0x0681dfff) AM_RAM
2466		AM_RANGE(0x0681e000, 0x0681ffff) AM_RAM_WRITE_LEGACY(namcos23_textram_w ) AM_BASE(m_textram)
2467		AM_RANGE(0x06820000, 0x0682000f) AM_READWRITE16_LEGACY(s23_c361_r, s23_c361_w, 0xffffffff ) // C361
	2493	AM_RANGE(0x0681e000, 0x0681ffff) AM_RAM_WRITE(namcos23_textram_w ) AM_BASE(m_textram)
	2494	AM_RANGE(0x06820000, 0x0682000f) AM_READWRITE16(s23_c361_r, s23_c361_w, 0xffffffff ) // C361
2468	2495	AM_RANGE(0x06a08000, 0x06a087ff) AM_RAM // Blending control & GAMMA (C404)
2469		AM_RANGE(0x06a10000, 0x06a3ffff) AM_RAM_WRITE_LEGACY(namcos23_paletteram_w ) AM_BASE_GENERIC(paletteram)
	2496	AM_RANGE(0x06a10000, 0x06a3ffff) AM_RAM_WRITE(namcos23_paletteram_w ) AM_BASE_GENERIC(paletteram)
2470	2497	AM_RANGE(0x08000000, 0x08ffffff) AM_ROM AM_REGION("data", 0x0000000) AM_MIRROR(0x1000000) // data ROMs
2471	2498	AM_RANGE(0x0a000000, 0x0affffff) AM_ROM AM_REGION("data", 0x1000000) AM_MIRROR(0x1000000)
2472		AM_RANGE(0x0c000000, 0x0c00001f) AM_READWRITE16_LEGACY(s23_c412_r, s23_c412_w, 0xffffffff )
2473		AM_RANGE(0x0c400000, 0x0c400007) AM_READWRITE16_LEGACY(s23_c421_r, s23_c421_w, 0xffffffff )
2474		AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16_LEGACY(s23_ctl_r, s23_ctl_w, 0xffffffff )
2475		AM_RANGE(0x0e800000, 0x0e800003) AM_READ_LEGACY(s23_unk_status_r )
	2499	AM_RANGE(0x0c000000, 0x0c00001f) AM_READWRITE16(s23_c412_r, s23_c412_w, 0xffffffff )
	2500	AM_RANGE(0x0c400000, 0x0c400007) AM_READWRITE16(s23_c421_r, s23_c421_w, 0xffffffff )
	2501	AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16(s23_ctl_r, s23_ctl_w, 0xffffffff )
	2502	AM_RANGE(0x0e800000, 0x0e800003) AM_READ(s23_unk_status_r )
2476	2503	AM_RANGE(0x0fc00000, 0x0fffffff) AM_WRITENOP AM_ROM AM_REGION("user1", 0)
2477	2504	ADDRESS_MAP_END
2478	2505
2479		static READ32_HANDLER( gmen_trigger_sh2 )
	2506	READ32_MEMBER(namcos23_state::gmen_trigger_sh2)
2480	2507	{
2481	2508	logerror("gmen_trigger_sh2: booting SH-2\n");
2482		cputag_set_input_line(space->machine(), "gmen", INPUT_LINE_RESET, CLEAR_LINE);
	2509	cputag_set_input_line(machine(), "gmen", INPUT_LINE_RESET, CLEAR_LINE);
2483	2510
2484	2511	return 0;
2485	2512	}
2486	2513
2487		static READ32_HANDLER( sh2_shared_r )
	2514	READ32_MEMBER(namcos23_state::sh2_shared_r)
2488	2515	{
2489		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2490		return state->m_gmen_sh2_shared[offset];
	2516	return m_gmen_sh2_shared[offset];
2491	2517	}
2492	2518
2493		static WRITE32_HANDLER( sh2_shared_w )
	2519	WRITE32_MEMBER(namcos23_state::sh2_shared_w)
2494	2520	{
2495		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2496		COMBINE_DATA(&state->m_gmen_sh2_shared[offset]);
	2521	COMBINE_DATA(&m_gmen_sh2_shared[offset]);
2497	2522	}
2498	2523
2499	2524	static ADDRESS_MAP_START( gmen_mips_map, AS_PROGRAM, 32, namcos23_state )
2500	2525	AM_IMPORT_FROM(ss23_map)
2501		AM_RANGE(0x0e400000, 0x0e400003) AM_READ_LEGACY(gmen_trigger_sh2 )
2502		AM_RANGE(0x0e700000, 0x0e707fff) AM_READWRITE_LEGACY(sh2_shared_r, sh2_shared_w )
	2526	AM_RANGE(0x0e400000, 0x0e400003) AM_READ(gmen_trigger_sh2 )
	2527	AM_RANGE(0x0e700000, 0x0e707fff) AM_READWRITE(sh2_shared_r, sh2_shared_w )
2503	2528	ADDRESS_MAP_END
2504	2529
2505	2530
r14845	r14846
2514	2539	cputag_set_input_line(machine, "gmen", INPUT_LINE_RESET, ASSERT_LINE);
2515	2540	}
2516	2541
2517		static WRITE16_HANDLER( sharedram_sub_w )
	2542	WRITE16_MEMBER(namcos23_state::sharedram_sub_w)
2518	2543	{
2519		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2520		UINT16 *shared16 = (UINT16 *)state->m_shared_ram;
	2544	UINT16 *shared16 = (UINT16 *)m_shared_ram;
2521	2545
2522	2546	// fake that an I/O board is connected for games w/o a dump or that aren't properly communicating with it yet
2523		if (!state->m_has_jvsio)
	2547	if (!m_has_jvsio)
2524	2548	{
2525	2549	if ((offset == 0x4052/2) && (data == 0x78))
2526	2550	{
r14845	r14846
2531	2555	COMBINE_DATA(&shared16[BYTE_XOR_BE(offset)]);
2532	2556	}
2533	2557
2534		static READ16_HANDLER( sharedram_sub_r )
	2558	READ16_MEMBER(namcos23_state::sharedram_sub_r)
2535	2559	{
2536		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2537		UINT16 *shared16 = (UINT16 *)state->m_shared_ram;
	2560	UINT16 *shared16 = (UINT16 *)m_shared_ram;
2538	2561
2539	2562	return shared16[BYTE_XOR_BE(offset)];
2540	2563	}
2541	2564
2542		static WRITE16_HANDLER( sub_interrupt_main_w )
	2565	WRITE16_MEMBER(namcos23_state::sub_interrupt_main_w)
2543	2566	{
2544	2567	if  ((mem_mask == 0xffff) && (data == 0x3170))
2545	2568	{
2546		cputag_set_input_line(space->machine(), "maincpu", MIPS3_IRQ1, ASSERT_LINE);
	2569	cputag_set_input_line(machine(), "maincpu", MIPS3_IRQ1, ASSERT_LINE);
2547	2570	}
2548	2571	else
2549	2572	{
r14845	r14846
2554	2577	/* H8/3002 MCU stuff */
2555	2578	static ADDRESS_MAP_START( s23h8rwmap, AS_PROGRAM, 16, namcos23_state )
2556	2579	AM_RANGE(0x000000, 0x07ffff) AM_ROM
2557		AM_RANGE(0x080000, 0x08ffff) AM_READWRITE_LEGACY(sharedram_sub_r, sharedram_sub_w )
	2580	AM_RANGE(0x080000, 0x08ffff) AM_READWRITE(sharedram_sub_r, sharedram_sub_w )
2558	2581	AM_RANGE(0x280000, 0x287fff) AM_DEVREADWRITE("c352", c352_device, read, write)
2559	2582	AM_RANGE(0x300000, 0x300003) AM_NOP   // seems to be more inputs, maybe false leftover code from System 12?
2560	2583	AM_RANGE(0x300010, 0x300011) AM_NOP
2561		AM_RANGE(0x300020, 0x300021) AM_WRITE_LEGACY(sub_interrupt_main_w )
	2584	AM_RANGE(0x300020, 0x300021) AM_WRITE(sub_interrupt_main_w )
2562	2585	AM_RANGE(0x300030, 0x300031) AM_WRITENOP   // timecrs2 writes this when writing to the sync shared ram location, motoxgo doesn't
2563	2586	ADDRESS_MAP_END
2564	2587
2565		static READ8_HANDLER( s23_mcu_p8_r )
	2588	READ8_MEMBER(namcos23_state::s23_mcu_p8_r)
2566	2589	{
2567	2590	return 0x02;
2568	2591	}
r14845	r14846
2572	2595	// the actual I/O takes place through the H8/3002's serial port B.
2573	2596
2574	2597
2575		static READ8_HANDLER( s23_mcu_pa_r )
	2598	READ8_MEMBER(namcos23_state::s23_mcu_pa_r)
2576	2599	{
2577		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2578		return state->m_s23_porta;
	2600	return m_s23_porta;
2579	2601	}
2580	2602
2581		static WRITE8_HANDLER( s23_mcu_pa_w )
	2603	WRITE8_MEMBER(namcos23_state::s23_mcu_pa_w)
2582	2604	{
2583		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2584	2605	// bit 0 = chip enable for the RTC
2585	2606	// reset the state on the rising edge of the bit
2586		if ((!(state->m_s23_porta & 1)) && (data & 1))
	2607	if ((!(m_s23_porta & 1)) && (data & 1))
2587	2608	{
2588		state->m_s23_rtcstate = 0;
	2609	m_s23_rtcstate = 0;
2589	2610	}
2590	2611
2591		state->m_s23_porta = data;
	2612	m_s23_porta = data;
2592	2613	}
2593	2614
2594	2615	INLINE UINT8 make_bcd(UINT8 data)
r14845	r14846
2596	2617	return ((data / 10) << 4) | (data % 10);
2597	2618	}
2598	2619
2599		static READ8_HANDLER( s23_mcu_rtc_r )
	2620	READ8_MEMBER(namcos23_state::s23_mcu_rtc_r)
2600	2621	{
2601		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2602	2622	UINT8 ret = 0;
2603	2623	system_time systime;
2604	2624	static const int weekday[7] = { 7, 1, 2, 3, 4, 5, 6 };
2605	2625
2606		space->machine().current_datetime(systime);
	2626	machine().current_datetime(systime);
2607	2627
2608		switch (state->m_s23_rtcstate)
	2628	switch (m_s23_rtcstate)
2609	2629	{
2610	2630	case 0:
2611	2631	ret = make_bcd(systime.local_time.second);   // seconds (BCD, 0-59) in bits 0-6, bit 7 = battery low
r14845	r14846
2633	2653	break;
2634	2654	}
2635	2655
2636		state->m_s23_rtcstate++;
	2656	m_s23_rtcstate++;
2637	2657
2638	2658	return ret;
2639	2659	}
2640	2660
2641	2661
2642		static READ8_HANDLER( s23_mcu_portB_r )
	2662	READ8_MEMBER(namcos23_state::s23_mcu_portB_r)
2643	2663	{
2644		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2645		state->m_s23_lastpB ^= 0x80;
2646		return state->m_s23_lastpB;
	2664	m_s23_lastpB ^= 0x80;
	2665	return m_s23_lastpB;
2647	2666	}
2648	2667
2649		static WRITE8_HANDLER( s23_mcu_portB_w )
	2668	WRITE8_MEMBER(namcos23_state::s23_mcu_portB_w)
2650	2669	{
2651		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2652	2670	// bit 7 = chip enable for the video settings controller
2653	2671	if (data & 0x80)
2654	2672	{
2655		state->m_s23_setstate = 0;
	2673	m_s23_setstate = 0;
2656	2674	}
2657	2675
2658		state->m_s23_lastpB = data;
	2676	m_s23_lastpB = data;
2659	2677	}
2660	2678
2661		static WRITE8_HANDLER( s23_mcu_settings_w )
	2679	WRITE8_MEMBER(namcos23_state::s23_mcu_settings_w)
2662	2680	{
2663		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2664		if (state->m_s23_setstate)
	2681	if (m_s23_setstate)
2665	2682	{
2666	2683	// data
2667		state->m_s23_settings[state->m_s23_setnum] = data;
	2684	m_s23_settings[m_s23_setnum] = data;
2668	2685
2669		if (state->m_s23_setnum == 7)
	2686	if (m_s23_setnum == 7)
2670	2687	{
2671	2688	logerror("S23 video settings: Contrast: %02x  R: %02x  G: %02x  B: %02x\n",
2672		BITSWAP8(state->m_s23_settings[0], 0, 1, 2, 3, 4, 5, 6, 7),
2673		BITSWAP8(state->m_s23_settings[1], 0, 1, 2, 3, 4, 5, 6, 7),
2674		BITSWAP8(state->m_s23_settings[2], 0, 1, 2, 3, 4, 5, 6, 7),
2675		BITSWAP8(state->m_s23_settings[3], 0, 1, 2, 3, 4, 5, 6, 7));
	2689	BITSWAP8(m_s23_settings[0], 0, 1, 2, 3, 4, 5, 6, 7),
	2690	BITSWAP8(m_s23_settings[1], 0, 1, 2, 3, 4, 5, 6, 7),
	2691	BITSWAP8(m_s23_settings[2], 0, 1, 2, 3, 4, 5, 6, 7),
	2692	BITSWAP8(m_s23_settings[3], 0, 1, 2, 3, 4, 5, 6, 7));
2676	2693	}
2677	2694	}
2678	2695	else
2679	2696	{   // setting number
2680		state->m_s23_setnum = (data >> 4)-1;
	2697	m_s23_setnum = (data >> 4)-1;
2681	2698	}
2682	2699
2683		state->m_s23_setstate ^= 1;
	2700	m_s23_setstate ^= 1;
2684	2701	}
2685	2702
2686	2703
2687		static READ8_HANDLER( s23_mcu_iob_r )
	2704	READ8_MEMBER(namcos23_state::s23_mcu_iob_r)
2688	2705	{
2689		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2690		UINT8 ret = state->m_iotomain[state->m_im_rd];
	2706	UINT8 ret = m_iotomain[m_im_rd];
2691	2707
2692		state->m_im_rd++;
2693		state->m_im_rd &= 0x7f;
	2708	m_im_rd++;
	2709	m_im_rd &= 0x7f;
2694	2710
2695		if (state->m_im_rd == state->m_im_wr)
	2711	if (m_im_rd == m_im_wr)
2696	2712	{
2697		cputag_set_input_line(space->machine(), "audiocpu", H8_SCI_0_RX, CLEAR_LINE);
	2713	cputag_set_input_line(machine(), "audiocpu", H8_SCI_0_RX, CLEAR_LINE);
2698	2714	}
2699	2715	else
2700	2716	{
2701		cputag_set_input_line(space->machine(), "audiocpu", H8_SCI_0_RX, CLEAR_LINE);
2702		cputag_set_input_line(space->machine(), "audiocpu", H8_SCI_0_RX, ASSERT_LINE);
	2717	cputag_set_input_line(machine(), "audiocpu", H8_SCI_0_RX, CLEAR_LINE);
	2718	cputag_set_input_line(machine(), "audiocpu", H8_SCI_0_RX, ASSERT_LINE);
2703	2719	}
2704	2720
2705	2721	return ret;
2706	2722	}
2707	2723
2708		static WRITE8_HANDLER( s23_mcu_iob_w )
	2724	WRITE8_MEMBER(namcos23_state::s23_mcu_iob_w)
2709	2725	{
2710		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2711		state->m_maintoio[state->m_mi_wr++] = data;
2712		state->m_mi_wr &= 0x7f;
	2726	m_maintoio[m_mi_wr++] = data;
	2727	m_mi_wr &= 0x7f;
2713	2728
2714		cputag_set_input_line(space->machine(), "ioboard", H8_SCI_0_RX, ASSERT_LINE);
	2729	cputag_set_input_line(machine(), "ioboard", H8_SCI_0_RX, ASSERT_LINE);
2715	2730	}
2716	2731
2717	2732	static INPUT_PORTS_START( gorgon )
r14845	r14846
2893	2908	INPUT_PORTS_END
2894	2909
2895	2910
2896		static READ8_HANDLER(s23_mcu_p6_r)
	2911	READ8_MEMBER(namcos23_state::s23_mcu_p6_r)
2897	2912	{
2898		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2899	2913	// bit 1 = JVS cable present sense (1 = I/O board plugged in)
2900		return (state->m_jvssense << 1) | 0xfd;
	2914	return (m_jvssense << 1) | 0xfd;
2901	2915	}
2902	2916
2903		static WRITE8_HANDLER(s23_mcu_p6_w)
	2917	WRITE8_MEMBER(namcos23_state::s23_mcu_p6_w)
2904	2918	{
2905	2919	//  printf("%02x to port 6\n", data);
2906	2920	}
2907	2921
2908	2922	static ADDRESS_MAP_START( s23h8iomap, AS_IO, 8, namcos23_state )
2909		AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE_LEGACY(s23_mcu_p6_r, s23_mcu_p6_w )
	2923	AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE(s23_mcu_p6_r, s23_mcu_p6_w )
2910	2924	AM_RANGE(H8_PORT_7, H8_PORT_7) AM_READ_PORT( "H8PORT" )
2911		AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READ_LEGACY(s23_mcu_p8_r ) AM_WRITENOP
	2925	AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READ(s23_mcu_p8_r ) AM_WRITENOP
2912	2926	AM_RANGE(H8_PORT_9, H8_PORT_9) AM_NOP   // read on Gorgon, purpose unknown
2913		AM_RANGE(H8_PORT_A, H8_PORT_A) AM_READWRITE_LEGACY(s23_mcu_pa_r, s23_mcu_pa_w )
2914		AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE_LEGACY(s23_mcu_portB_r, s23_mcu_portB_w )
2915		AM_RANGE(H8_SERIAL_0, H8_SERIAL_0) AM_READWRITE_LEGACY(s23_mcu_iob_r, s23_mcu_iob_w )
2916		AM_RANGE(H8_SERIAL_1, H8_SERIAL_1) AM_READWRITE_LEGACY(s23_mcu_rtc_r, s23_mcu_settings_w )
	2927	AM_RANGE(H8_PORT_A, H8_PORT_A) AM_READWRITE(s23_mcu_pa_r, s23_mcu_pa_w )
	2928	AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE(s23_mcu_portB_r, s23_mcu_portB_w )
	2929	AM_RANGE(H8_SERIAL_0, H8_SERIAL_0) AM_READWRITE(s23_mcu_iob_r, s23_mcu_iob_w )
	2930	AM_RANGE(H8_SERIAL_1, H8_SERIAL_1) AM_READWRITE(s23_mcu_rtc_r, s23_mcu_settings_w )
2917	2931	AM_RANGE(H8_ADC_0_H, H8_ADC_0_L) AM_NOP
2918	2932	AM_RANGE(H8_ADC_1_H, H8_ADC_1_L) AM_NOP
2919	2933	AM_RANGE(H8_ADC_2_H, H8_ADC_2_L) AM_NOP
r14845	r14846
2922	2936
2923	2937	// version without serial hookup to I/O board for games where the PIC isn't dumped
2924	2938	static ADDRESS_MAP_START( s23h8noiobmap, AS_IO, 8, namcos23_state )
2925		AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE_LEGACY(s23_mcu_p6_r, s23_mcu_p6_w )
	2939	AM_RANGE(H8_PORT_6, H8_PORT_6) AM_READWRITE(s23_mcu_p6_r, s23_mcu_p6_w )
2926	2940	AM_RANGE(H8_PORT_7, H8_PORT_7) AM_READ_PORT( "H8PORT" )
2927		AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READ_LEGACY(s23_mcu_p8_r ) AM_WRITENOP
2928		AM_RANGE(H8_PORT_A, H8_PORT_A) AM_READWRITE_LEGACY(s23_mcu_pa_r, s23_mcu_pa_w )
2929		AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE_LEGACY(s23_mcu_portB_r, s23_mcu_portB_w )
2930		AM_RANGE(H8_SERIAL_1, H8_SERIAL_1) AM_READWRITE_LEGACY(s23_mcu_rtc_r, s23_mcu_settings_w )
	2941	AM_RANGE(H8_PORT_8, H8_PORT_8) AM_READ(s23_mcu_p8_r ) AM_WRITENOP
	2942	AM_RANGE(H8_PORT_A, H8_PORT_A) AM_READWRITE(s23_mcu_pa_r, s23_mcu_pa_w )
	2943	AM_RANGE(H8_PORT_B, H8_PORT_B) AM_READWRITE(s23_mcu_portB_r, s23_mcu_portB_w )
	2944	AM_RANGE(H8_SERIAL_1, H8_SERIAL_1) AM_READWRITE(s23_mcu_rtc_r, s23_mcu_settings_w )
2931	2945	AM_RANGE(H8_ADC_0_H, H8_ADC_0_L) AM_NOP
2932	2946	AM_RANGE(H8_ADC_1_H, H8_ADC_1_L) AM_NOP
2933	2947	AM_RANGE(H8_ADC_2_H, H8_ADC_2_L) AM_NOP
r14845	r14846
2935	2949	ADDRESS_MAP_END
2936	2950
2937	2951
2938		static READ8_HANDLER( s23_iob_mcu_r )
	2952	READ8_MEMBER(namcos23_state::s23_iob_mcu_r)
2939	2953	{
2940		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2941		UINT8 ret = state->m_maintoio[state->m_mi_rd];
	2954	UINT8 ret = m_maintoio[m_mi_rd];
2942	2955
2943		state->m_mi_rd++;
2944		state->m_mi_rd &= 0x7f;
	2956	m_mi_rd++;
	2957	m_mi_rd &= 0x7f;
2945	2958
2946		if (state->m_mi_rd == state->m_mi_wr)
	2959	if (m_mi_rd == m_mi_wr)
2947	2960	{
2948		cputag_set_input_line(space->machine(), "ioboard", H8_SCI_0_RX, CLEAR_LINE);
	2961	cputag_set_input_line(machine(), "ioboard", H8_SCI_0_RX, CLEAR_LINE);
2949	2962	}
2950	2963
2951	2964	return ret;
2952	2965	}
2953	2966
2954		static WRITE8_HANDLER( s23_iob_mcu_w )
	2967	WRITE8_MEMBER(namcos23_state::s23_iob_mcu_w)
2955	2968	{
2956		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2957		state->m_iotomain[state->m_im_wr++] = data;
2958		state->m_im_wr &= 0x7f;
	2969	m_iotomain[m_im_wr++] = data;
	2970	m_im_wr &= 0x7f;
2959	2971
2960		cputag_set_input_line(space->machine(), "audiocpu", H8_SCI_0_RX, ASSERT_LINE);
	2972	cputag_set_input_line(machine(), "audiocpu", H8_SCI_0_RX, ASSERT_LINE);
2961	2973	}
2962	2974
2963	2975
2964		static READ8_HANDLER( s23_iob_p4_r )
	2976	READ8_MEMBER(namcos23_state::s23_iob_p4_r)
2965	2977	{
2966		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2967		return state->m_s23_tssio_port_4;
	2978	return m_s23_tssio_port_4;
2968	2979	}
2969	2980
2970		static WRITE8_HANDLER( s23_iob_p4_w )
	2981	WRITE8_MEMBER(namcos23_state::s23_iob_p4_w)
2971	2982	{
2972		namcos23_state *state = space->machine().driver_data<namcos23_state>();
2973		state->m_s23_tssio_port_4 = data;
	2983	m_s23_tssio_port_4 = data;
2974	2984
2975		state->m_jvssense = (data & 0x04) ? 0 : 1;
	2985	m_jvssense = (data & 0x04) ? 0 : 1;
2976	2986	}
2977	2987
2978		static READ8_HANDLER( s23_gun_r )
	2988	READ8_MEMBER(namcos23_state::s23_gun_r)
2979	2989	{
2980		UINT16 xpos = input_port_read_safe(space->machine(), "LIGHTX", 0) * 640 / 0xff + 0x80;
2981		UINT16 ypos = input_port_read_safe(space->machine(), "LIGHTY", 0) * 240 / 0xff + 0x20;
	2990	UINT16 xpos = input_port_read_safe(machine(), "LIGHTX", 0) * 640 / 0xff + 0x80;
	2991	UINT16 ypos = input_port_read_safe(machine(), "LIGHTY", 0) * 240 / 0xff + 0x20;
2982	2992
2983	2993	// note: will need angle adjustments for accurate aiming at screen sides
2984	2994	switch(offset)
r14845	r14846
2995	3005	return 0;
2996	3006	}
2997	3007
2998		static READ8_HANDLER(iob_r)
	3008	READ8_MEMBER(namcos23_state::iob_r)
2999	3009	{
3000		return space->machine().rand();
	3010	return machine().rand();
3001	3011	}
3002	3012
3003	3013	/* H8/3334 (Namco C78) I/O board MCU */
r14845	r14846
3005	3015	AM_RANGE(0x0000, 0x1fff) AM_ROM AM_REGION("ioboard", 0)
3006	3016	AM_RANGE(0x6000, 0x6000) AM_READ_PORT("TC2P0")     // 0-1 = coin 0-3 = coin connect, 0-5 = test 0-6 = down select, 0-7 = up select, 0-8 = enter
3007	3017	AM_RANGE(0x6001, 0x6001) AM_READ_PORT("TC2P1")     // 1-1 = gun trigger 1-2 = foot pedal
3008		AM_RANGE(0x6002, 0x6003) AM_READ_LEGACY(iob_r )
	3018	AM_RANGE(0x6002, 0x6003) AM_READ(iob_r )
3009	3019	AM_RANGE(0x6004, 0x6005) AM_WRITENOP
3010	3020	AM_RANGE(0x6006, 0x6007) AM_NOP
3011		AM_RANGE(0x7000, 0x700f) AM_READ_LEGACY(iob_r )
	3021	AM_RANGE(0x7000, 0x700f) AM_READ(iob_r )
3012	3022
3013	3023	AM_RANGE(0xc000, 0xf7ff) AM_RAM
3014	3024	ADDRESS_MAP_END
r14845	r14846
3019	3029	AM_RANGE(0x6001, 0x6001) AM_READ_PORT("TC2P1")
3020	3030	AM_RANGE(0x6002, 0x6005) AM_WRITENOP
3021	3031	AM_RANGE(0x6006, 0x6007) AM_NOP
3022		AM_RANGE(0x7000, 0x700f) AM_READ_LEGACY(s23_gun_r )
	3032	AM_RANGE(0x7000, 0x700f) AM_READ(s23_gun_r )
3023	3033
3024	3034	AM_RANGE(0xc000, 0xf7ff) AM_RAM
3025	3035	ADDRESS_MAP_END
r14845	r14846
3032	3042	AM_RANGE(0x6003, 0x6003) AM_READ_PORT("RRP3")     // 1-1 = button?  1-4 = start?
3033	3043	AM_RANGE(0x6004, 0x6005) AM_WRITENOP
3034	3044	AM_RANGE(0x6006, 0x6007) AM_NOP
3035		AM_RANGE(0x7000, 0x700f) AM_READ_LEGACY(iob_r )
	3045	AM_RANGE(0x7000, 0x700f) AM_READ(iob_r )
3036	3046
3037	3047	AM_RANGE(0xc000, 0xf7ff) AM_RAM
3038	3048	ADDRESS_MAP_END
r14845	r14846
3042	3052	port 4 bit 2 = SENSE line back to main (0 = asserted, 1 = dropped)
3043	3053	*/
3044	3054	static ADDRESS_MAP_START( s23iobrdiomap, AS_IO, 8, namcos23_state )
3045		AM_RANGE(H8_PORT_4, H8_PORT_4) AM_READWRITE_LEGACY(s23_iob_p4_r, s23_iob_p4_w )
	3055	AM_RANGE(H8_PORT_4, H8_PORT_4) AM_READWRITE(s23_iob_p4_r, s23_iob_p4_w )
3046	3056	AM_RANGE(H8_PORT_5, H8_PORT_5) AM_NOP   // status LED in bit 2
3047	3057	AM_RANGE(H8_PORT_6, H8_PORT_6) AM_NOP   // unknown
3048	3058	AM_RANGE(H8_PORT_8, H8_PORT_8) AM_NOP   // unknown - used on ASCA-5 only
3049	3059	AM_RANGE(H8_PORT_9, H8_PORT_9) AM_NOP   // unknown - used on ASCA-5 only
3050		AM_RANGE(H8_SERIAL_0, H8_SERIAL_0) AM_READWRITE_LEGACY(s23_iob_mcu_r, s23_iob_mcu_w )
	3060	AM_RANGE(H8_SERIAL_0, H8_SERIAL_0) AM_READWRITE(s23_iob_mcu_r, s23_iob_mcu_w )
3051	3061	AM_RANGE(H8_ADC_0_H, H8_ADC_3_L) AM_NOP
3052	3062	ADDRESS_MAP_END
3053	3063

src/mame/drivers/mjsister.c

r14845	r14846
49	49	/* memory */
50	50	UINT8 m_videoram0[0x8000];
51	51	UINT8 m_videoram1[0x8000];
	52	DECLARE_WRITE8_MEMBER(mjsister_videoram_w);
	53	DECLARE_WRITE8_MEMBER(mjsister_dac_adr_s_w);
	54	DECLARE_WRITE8_MEMBER(mjsister_dac_adr_e_w);
	55	DECLARE_WRITE8_MEMBER(mjsister_banksel1_w);
	56	DECLARE_WRITE8_MEMBER(mjsister_banksel2_w);
	57	DECLARE_WRITE8_MEMBER(mjsister_input_sel1_w);
	58	DECLARE_WRITE8_MEMBER(mjsister_input_sel2_w);
	59	DECLARE_READ8_MEMBER(mjsister_keys_r);
52	60	};
53	61
54	62
r14845	r14846
103	111	state->m_tmpbitmap1->pix16(y, x * 2 + 1) = c2;
104	112	}
105	113
106		static WRITE8_HANDLER( mjsister_videoram_w )
	114	WRITE8_MEMBER(mjsister_state::mjsister_videoram_w)
107	115	{
108		mjsister_state *state = space->machine().driver_data<mjsister_state>();
109		if (state->m_vrambank)
	116	if (m_vrambank)
110	117	{
111		state->m_videoram1[offset] = data;
112		mjsister_plot1(space->machine(), offset, data);
	118	m_videoram1[offset] = data;
	119	mjsister_plot1(machine(), offset, data);
113	120	}
114	121	else
115	122	{
116		state->m_videoram0[offset] = data;
117		mjsister_plot0(space->machine(), offset, data);
	123	m_videoram0[offset] = data;
	124	mjsister_plot0(machine(), offset, data);
118	125	}
119	126	}
120	127
r14845	r14846
169	176	state->m_dac_busy = 0;
170	177	}
171	178
172		static WRITE8_HANDLER( mjsister_dac_adr_s_w )
	179	WRITE8_MEMBER(mjsister_state::mjsister_dac_adr_s_w)
173	180	{
174		mjsister_state *state = space->machine().driver_data<mjsister_state>();
175		state->m_dac_adr_s = data;
	181	m_dac_adr_s = data;
176	182	}
177	183
178		static WRITE8_HANDLER( mjsister_dac_adr_e_w )
	184	WRITE8_MEMBER(mjsister_state::mjsister_dac_adr_e_w)
179	185	{
180		mjsister_state *state = space->machine().driver_data<mjsister_state>();
181		state->m_dac_adr_e = data;
182		state->m_dac_adr = state->m_dac_adr_s << 8;
	186	m_dac_adr_e = data;
	187	m_dac_adr = m_dac_adr_s << 8;
183	188
184		if (state->m_dac_busy == 0)
185		space->machine().scheduler().synchronize(FUNC(dac_callback));
	189	if (m_dac_busy == 0)
	190	machine().scheduler().synchronize(FUNC(dac_callback));
186	191
187		state->m_dac_busy = 1;
	192	m_dac_busy = 1;
188	193	}
189	194
190		static WRITE8_HANDLER( mjsister_banksel1_w )
	195	WRITE8_MEMBER(mjsister_state::mjsister_banksel1_w)
191	196	{
192		mjsister_state *state = space->machine().driver_data<mjsister_state>();
193		int tmp = state->m_colorbank;
	197	int tmp = m_colorbank;
194	198
195	199	switch (data)
196	200	{
197		case 0x0: state->m_rombank0 = 0 ; break;
198		case 0x1: state->m_rombank0 = 1 ; break;
	201	case 0x0: m_rombank0 = 0 ; break;
	202	case 0x1: m_rombank0 = 1 ; break;
199	203
200		case 0x2: state->m_flip_screen = 0 ; break;
201		case 0x3: state->m_flip_screen = 1 ; break;
	204	case 0x2: m_flip_screen = 0 ; break;
	205	case 0x3: m_flip_screen = 1 ; break;
202	206
203		case 0x4: state->m_colorbank &= 0xfe; break;
204		case 0x5: state->m_colorbank |= 0x01; break;
205		case 0x6: state->m_colorbank &= 0xfd; break;
206		case 0x7: state->m_colorbank |= 0x02; break;
207		case 0x8: state->m_colorbank &= 0xfb; break;
208		case 0x9: state->m_colorbank |= 0x04; break;
	207	case 0x4: m_colorbank &= 0xfe; break;
	208	case 0x5: m_colorbank |= 0x01; break;
	209	case 0x6: m_colorbank &= 0xfd; break;
	210	case 0x7: m_colorbank |= 0x02; break;
	211	case 0x8: m_colorbank &= 0xfb; break;
	212	case 0x9: m_colorbank |= 0x04; break;
209	213
210		case 0xa: state->m_video_enable = 0 ; break;
211		case 0xb: state->m_video_enable = 1 ; break;
	214	case 0xa: m_video_enable = 0 ; break;
	215	case 0xb: m_video_enable = 1 ; break;
212	216
213		case 0xe: state->m_vrambank = 0 ; break;
214		case 0xf: state->m_vrambank = 1 ; break;
	217	case 0xe: m_vrambank = 0 ; break;
	218	case 0xf: m_vrambank = 1 ; break;
215	219
216	220	default:
217		logerror("%04x p30_w:%02x\n", cpu_get_pc(&space->device()), data);
	221	logerror("%04x p30_w:%02x\n", cpu_get_pc(&space.device()), data);
218	222	}
219	223
220		if (tmp != state->m_colorbank)
221		state->m_screen_redraw = 1;
	224	if (tmp != m_colorbank)
	225	m_screen_redraw = 1;
222	226
223		memory_set_bank(space->machine(), "bank1", state->m_rombank0 * 2 + state->m_rombank1);
	227	memory_set_bank(machine(), "bank1", m_rombank0 * 2 + m_rombank1);
224	228	}
225	229
226		static WRITE8_HANDLER( mjsister_banksel2_w )
	230	WRITE8_MEMBER(mjsister_state::mjsister_banksel2_w)
227	231	{
228		mjsister_state *state = space->machine().driver_data<mjsister_state>();
229	232
230	233	switch (data)
231	234	{
232		case 0xa: state->m_dac_bank = 0; break;
233		case 0xb: state->m_dac_bank = 1; break;
	235	case 0xa: m_dac_bank = 0; break;
	236	case 0xb: m_dac_bank = 1; break;
234	237
235		case 0xc: state->m_rombank1 = 0; break;
236		case 0xd: state->m_rombank1 = 1; break;
	238	case 0xc: m_rombank1 = 0; break;
	239	case 0xd: m_rombank1 = 1; break;
237	240
238	241	default:
239		logerror("%04x p31_w:%02x\n", cpu_get_pc(&space->device()), data);
	242	logerror("%04x p31_w:%02x\n", cpu_get_pc(&space.device()), data);
240	243	}
241	244
242		memory_set_bank(space->machine(), "bank1", state->m_rombank0 * 2 + state->m_rombank1);
	245	memory_set_bank(machine(), "bank1", m_rombank0 * 2 + m_rombank1);
243	246	}
244	247
245		static WRITE8_HANDLER( mjsister_input_sel1_w )
	248	WRITE8_MEMBER(mjsister_state::mjsister_input_sel1_w)
246	249	{
247		mjsister_state *state = space->machine().driver_data<mjsister_state>();
248		state->m_input_sel1 = data;
	250	m_input_sel1 = data;
249	251	}
250	252
251		static WRITE8_HANDLER( mjsister_input_sel2_w )
	253	WRITE8_MEMBER(mjsister_state::mjsister_input_sel2_w)
252	254	{
253		mjsister_state *state = space->machine().driver_data<mjsister_state>();
254		state->m_input_sel2 = data;
	255	m_input_sel2 = data;
255	256	}
256	257
257		static READ8_HANDLER( mjsister_keys_r )
	258	READ8_MEMBER(mjsister_state::mjsister_keys_r)
258	259	{
259		mjsister_state *state = space->machine().driver_data<mjsister_state>();
260	260	int p, i, ret = 0;
261	261	static const char *const keynames[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4", "KEY5" };
262	262
263		p = state->m_input_sel1 & 0x3f;
264		//  p |= ((state->m_input_sel2 & 8) << 4) | ((state->m_input_sel2 & 0x20) << 1);
	263	p = m_input_sel1 & 0x3f;
	264	//  p |= ((m_input_sel2 & 8) << 4) | ((m_input_sel2 & 0x20) << 1);
265	265
266	266	for (i = 0; i < 6; i++)
267	267	{
268	268	if (BIT(p, i))
269		ret |= input_port_read(space->machine(), keynames[i]);
	269	ret |= input_port_read(machine(), keynames[i]);
270	270	}
271	271
272	272	return ret;
r14845	r14846
281	281	static ADDRESS_MAP_START( mjsister_map, AS_PROGRAM, 8, mjsister_state )
282	282	AM_RANGE(0x0000, 0x77ff) AM_ROM
283	283	AM_RANGE(0x7800, 0x7fff) AM_RAM
284		AM_RANGE(0x8000, 0xffff) AM_ROMBANK("bank1") AM_WRITE_LEGACY(mjsister_videoram_w)
	284	AM_RANGE(0x8000, 0xffff) AM_ROMBANK("bank1") AM_WRITE(mjsister_videoram_w)
285	285	ADDRESS_MAP_END
286	286
287	287	static ADDRESS_MAP_START( mjsister_io_map, AS_IO, 8, mjsister_state )
r14845	r14846
290	290	AM_RANGE(0x10, 0x10) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
291	291	AM_RANGE(0x11, 0x11) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
292	292	AM_RANGE(0x12, 0x12) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
293		AM_RANGE(0x20, 0x20) AM_READ_LEGACY(mjsister_keys_r)
	293	AM_RANGE(0x20, 0x20) AM_READ(mjsister_keys_r)
294	294	AM_RANGE(0x21, 0x21) AM_READ_PORT("IN0")
295		AM_RANGE(0x30, 0x30) AM_WRITE_LEGACY(mjsister_banksel1_w)
296		AM_RANGE(0x31, 0x31) AM_WRITE_LEGACY(mjsister_banksel2_w)
297		AM_RANGE(0x32, 0x32) AM_WRITE_LEGACY(mjsister_input_sel1_w)
298		AM_RANGE(0x33, 0x33) AM_WRITE_LEGACY(mjsister_input_sel2_w)
299		AM_RANGE(0x34, 0x34) AM_WRITE_LEGACY(mjsister_dac_adr_s_w)
300		AM_RANGE(0x35, 0x35) AM_WRITE_LEGACY(mjsister_dac_adr_e_w)
	295	AM_RANGE(0x30, 0x30) AM_WRITE(mjsister_banksel1_w)
	296	AM_RANGE(0x31, 0x31) AM_WRITE(mjsister_banksel2_w)
	297	AM_RANGE(0x32, 0x32) AM_WRITE(mjsister_input_sel1_w)
	298	AM_RANGE(0x33, 0x33) AM_WRITE(mjsister_input_sel2_w)
	299	AM_RANGE(0x34, 0x34) AM_WRITE(mjsister_dac_adr_s_w)
	300	AM_RANGE(0x35, 0x35) AM_WRITE(mjsister_dac_adr_e_w)
301	301	ADDRESS_MAP_END
302	302
303	303

src/mame/drivers/wheelfir.c

r14845	r14846
271	271	}
272	272	return 0;
273	273	}
	274	DECLARE_READ16_MEMBER(wheelfir_status_r);
	275	DECLARE_WRITE16_MEMBER(wheelfir_scanline_cnt_w);
	276	DECLARE_WRITE16_MEMBER(wheelfir_blit_w);
	277	DECLARE_WRITE16_MEMBER(pal_reset_pos_w);
	278	DECLARE_WRITE16_MEMBER(pal_data_w);
	279	DECLARE_WRITE16_MEMBER(wheelfir_7c0000_w);
	280	DECLARE_WRITE16_MEMBER(wheelfir_snd_w);
	281	DECLARE_READ16_MEMBER(wheelfir_snd_r);
	282	DECLARE_WRITE16_MEMBER(coin_cnt_w);
274	283	};
275	284
276	285
277		static READ16_HANDLER( wheelfir_status_r )
	286	READ16_MEMBER(wheelfir_state::wheelfir_status_r)
278	287	{
279	288	/*
280	289	fedcba9876543210
r14845	r14846
284	293	---------------x  ? eeprom
285	294
286	295	*/
287		wheelfir_state *state = space->machine().driver_data<wheelfir_state>();
288		return state->m_toggle_bit| (space->machine().rand()&0x2000);
	296
	297	return m_toggle_bit| (machine().rand()&0x2000);
289	298	}
290	299
291		static WRITE16_HANDLER( wheelfir_scanline_cnt_w )
	300	WRITE16_MEMBER(wheelfir_state::wheelfir_scanline_cnt_w)
292	301	{
293		wheelfir_state *state = space->machine().driver_data<wheelfir_state>();
294		COMBINE_DATA(&state->m_scanline_cnt);
	302	COMBINE_DATA(&m_scanline_cnt);
295	303	}
296	304
297	305
298		static WRITE16_HANDLER(wheelfir_blit_w)
	306	WRITE16_MEMBER(wheelfir_state::wheelfir_blit_w)
299	307	{
300		wheelfir_state *state = space->machine().driver_data<wheelfir_state>();
301	308
302		COMBINE_DATA(&state->m_blitter_data[offset]);
	309	COMBINE_DATA(&m_blitter_data[offset]);
303	310
304	311	if(!ACCESSING_BITS_8_15 && offset==0x6)  //LSB only!
305	312	{
306	313	int x,y;
307	314
308	315
309		int direct_width=state->m_direct_write_x1-state->m_direct_write_x0+1;
310		int direct_height=state->m_direct_write_y1-state->m_direct_write_y0+1;
	316	int direct_width=m_direct_write_x1-m_direct_write_x0+1;
	317	int direct_height=m_direct_write_y1-m_direct_write_y0+1;
311	318
312	319	int sixdat = data&0xff;
313	320
314	321	if(direct_width>0 && direct_height>0)
315	322	{
316		x= state->m_direct_write_idx % direct_width;
317		y = (state->m_direct_write_idx / direct_width) %direct_height;
	323	x= m_direct_write_idx % direct_width;
	324	y = (m_direct_write_idx / direct_width) %direct_height;
318	325
319		x+=state->m_direct_write_x0;
320		y+=state->m_direct_write_y0;
	326	x+=m_direct_write_x0;
	327	y+=m_direct_write_y0;
321	328
322	329	if(x<512 && y <512)
323	330	{
324		state->m_tmp_bitmap[LAYER_BG]->pix16(y, x) = sixdat;
	331	m_tmp_bitmap[LAYER_BG]->pix16(y, x) = sixdat;
325	332	}
326	333	}
327	334
328		++state->m_direct_write_idx;
	335	++m_direct_write_idx;
329	336
330	337	return;
331	338
r14845	r14846
336	343
337	344	if(offset==0x0a && ACCESSING_BITS_0_7)
338	345	{
339		xscroll = (state->m_blitter_data[0xa]&0x00ff) | (state->m_blitter_data[0x8]&0x0040) << 2;
	346	xscroll = (m_blitter_data[0xa]&0x00ff) | (m_blitter_data[0x8]&0x0040) << 2;
340	347	}
341	348
342	349	if(offset==0x0b && ACCESSING_BITS_0_7)
343	350	{
344		yscroll = (state->m_blitter_data[0xb]&0x00ff) | (state->m_blitter_data[0x8]&0x0080) << 1;
	351	yscroll = (m_blitter_data[0xb]&0x00ff) | (m_blitter_data[0x8]&0x0080) << 1;
345	352	}
346	353
347	354	if(offset==0x8 && ACCESSING_BITS_0_7)
348	355	{
349		xscroll = (state->m_blitter_data[0xa]&0x00ff) | (state->m_blitter_data[0x8]&0x0040) << 2;
350		yscroll = (state->m_blitter_data[0xb]&0x00ff) | (state->m_blitter_data[0x8]&0x0080) << 1;
	356	xscroll = (m_blitter_data[0xa]&0x00ff) | (m_blitter_data[0x8]&0x0040) << 2;
	357	yscroll = (m_blitter_data[0xb]&0x00ff) | (m_blitter_data[0x8]&0x0080) << 1;
351	358	}
352	359
353	360	if(xscroll>=0)
354	361	{
355		int scl=state->m_current_scanline>=NUM_SCANLINES?0:state->m_current_scanline;
356		state->m_scanlines[scl].x=xscroll;
357		state->m_scanlines[scl].unkbits=state->m_blitter_data[0x8]&0xff;
	362	int scl=m_current_scanline>=NUM_SCANLINES?0:m_current_scanline;
	363	m_scanlines[scl].x=xscroll;
	364	m_scanlines[scl].unkbits=m_blitter_data[0x8]&0xff;
358	365	}
359	366
360	367	if(yscroll>=0)
361	368	{
362		int scl=state->m_current_scanline>=NUM_SCANLINES?0:state->m_current_scanline;
363		state->m_scanlines[scl].y=yscroll;
364		state->m_scanlines[scl].unkbits=state->m_blitter_data[0x8]&0xff;
	369	int scl=m_current_scanline>=NUM_SCANLINES?0:m_current_scanline;
	370	m_scanlines[scl].y=yscroll;
	371	m_scanlines[scl].unkbits=m_blitter_data[0x8]&0xff;
365	372	}
366	373
367	374
368	375	if(offset==0xf && data==0xffff)
369	376	{
370	377
371		cputag_set_input_line(space->machine(), "maincpu", 1, HOLD_LINE);
	378	cputag_set_input_line(machine(), "maincpu", 1, HOLD_LINE);
372	379
373	380	{
374		UINT8 *rom = space->machine().region("gfx1")->base();
	381	UINT8 *rom = machine().region("gfx1")->base();
375	382
376		int width = space->machine().primary_screen->width();
377		int height = space->machine().primary_screen->height();
	383	int width = machine().primary_screen->width();
	384	int height = machine().primary_screen->height();
378	385
379		int src_x0=(state->m_blitter_data[0]>>8)+((state->m_blitter_data[6]&0x100)?256:0);
380		int src_y0=(state->m_blitter_data[2]>>8)+((state->m_blitter_data[6]&0x200)?256:0);
	386	int src_x0=(m_blitter_data[0]>>8)+((m_blitter_data[6]&0x100)?256:0);
	387	int src_y0=(m_blitter_data[2]>>8)+((m_blitter_data[6]&0x200)?256:0);
381	388
382		int dst_x0=(state->m_blitter_data[0]&0xff)+((state->m_blitter_data[7]&0x40)?256:0);
383		int dst_y0=(state->m_blitter_data[2]&0xff)+((state->m_blitter_data[7]&0x80)?256:0);
	389	int dst_x0=(m_blitter_data[0]&0xff)+((m_blitter_data[7]&0x40)?256:0);
	390	int dst_y0=(m_blitter_data[2]&0xff)+((m_blitter_data[7]&0x80)?256:0);
384	391
385		int dst_x1=(state->m_blitter_data[1]&0xff)+((state->m_blitter_data[9]&4)?256:0);
386		int dst_y1=(state->m_blitter_data[3]&0xff)+((state->m_blitter_data[9]&8)?256:0);
	392	int dst_x1=(m_blitter_data[1]&0xff)+((m_blitter_data[9]&4)?256:0);
	393	int dst_y1=(m_blitter_data[3]&0xff)+((m_blitter_data[9]&8)?256:0);
387	394
388		int x_dst_step=(state->m_blitter_data[7]&0x1)?1:-1;
389		int y_dst_step=(state->m_blitter_data[7]&0x2)?1:-1;
	395	int x_dst_step=(m_blitter_data[7]&0x1)?1:-1;
	396	int y_dst_step=(m_blitter_data[7]&0x2)?1:-1;
390	397
391		int x_src_step=(state->m_blitter_data[8]&0x4000)?1:-1;
392		int y_src_step=(state->m_blitter_data[8]&0x8000)?1:-1;
	398	int x_src_step=(m_blitter_data[8]&0x4000)?1:-1;
	399	int y_src_step=(m_blitter_data[8]&0x8000)?1:-1;
393	400
394		int page=((state->m_blitter_data[6])>>10)*0x40000;
	401	int page=((m_blitter_data[6])>>10)*0x40000;
395	402
396	403
397	404	if(page>=0x400000) /* src set to  unav. page before direct write to the framebuffer */
398	405	{
399	406
400		state->m_direct_write_x0=dst_x0;
401		state->m_direct_write_x1=dst_x1;
402		state->m_direct_write_y0=dst_y0;
403		state->m_direct_write_y1=dst_y1;
404		state->m_direct_write_idx=0;
	407	m_direct_write_x0=dst_x0;
	408	m_direct_write_x1=dst_x1;
	409	m_direct_write_y0=dst_y0;
	410	m_direct_write_y1=dst_y1;
	411	m_direct_write_idx=0;
405	412
406	413	}
407	414
r14845	r14846
447	454
448	455	int d1, d2, hflag, dflag, index;
449	456
450		d1=((state->m_blitter_data[0x0a]&0x1f00)>>8);
	457	d1=((m_blitter_data[0x0a]&0x1f00)>>8);
451	458
452		d2=((state->m_blitter_data[0x0b]&0x1f00)>>8);
	459	d2=((m_blitter_data[0x0b]&0x1f00)>>8);
453	460
454	461
455		d1|=((state->m_blitter_data[0x8]&0x100)>>3);
456		d2|=((state->m_blitter_data[0x8]&0x400)>>5);
457		hflag=(state->m_blitter_data[0x9]&0x1)?1:0;
458		dflag=(state->m_blitter_data[0x8]&0x1000)?1:0;
	462	d1|=((m_blitter_data[0x8]&0x100)>>3);
	463	d2|=((m_blitter_data[0x8]&0x400)>>5);
	464	hflag=(m_blitter_data[0x9]&0x1)?1:0;
	465	dflag=(m_blitter_data[0x8]&0x1000)?1:0;
459	466	index=d1|(d2<<6)|(hflag<<12)|(dflag<<13);
460	467
461	468
462		float scale_x=state->get_scale(index);
	469	float scale_x=get_scale(index);
463	470
464		d1=((state->m_blitter_data[0x0b]&0xc000)>>14) |
465		((state->m_blitter_data[0x0c]&0xc000)>>12) |
466		((state->m_blitter_data[0x0a]&0x4000)>>10);
	471	d1=((m_blitter_data[0x0b]&0xc000)>>14) |
	472	((m_blitter_data[0x0c]&0xc000)>>12) |
	473	((m_blitter_data[0x0a]&0x4000)>>10);
467	474
468		d2=((state->m_blitter_data[0x0c]&0x1f00)>>8);
	475	d2=((m_blitter_data[0x0c]&0x1f00)>>8);
469	476
470	477
471		d1|=((state->m_blitter_data[0x8]&0x200)>>4);
472		d2|=((state->m_blitter_data[0x8]&0x800)>>6);
	478	d1|=((m_blitter_data[0x8]&0x200)>>4);
	479	d2|=((m_blitter_data[0x8]&0x800)>>6);
473	480
474		hflag=(state->m_blitter_data[0x9]&0x2)?1:0;
475		dflag=(state->m_blitter_data[0x8]&0x2000)?1:0;
	481	hflag=(m_blitter_data[0x9]&0x2)?1:0;
	482	dflag=(m_blitter_data[0x8]&0x2000)?1:0;
476	483	index=d1|(d2<<6)|(hflag<<12)|(dflag<<13);
477	484
478	485
479		float scale_y=state->get_scale(index);
	486	float scale_y=get_scale(index);
480	487
481	488
482	489	if(scale_x==0 || scale_y==0) return;
r14845	r14846
491	498	float idx_x,idx_y;
492	499
493	500	int vpage=LAYER_FG;
494		if(state->m_blitter_data[0x7]&0x10)
	501	if(m_blitter_data[0x7]&0x10)
495	502	{
496	503	vpage=LAYER_BG;
497	504	/*
498		printf("bg -> %d %d   %d %d  %d %d @ %x\n",dst_x0,dst_y0, dst_x1,dst_y1, dst_x1-dst_x0, dst_y1-dst_y0,cpu_get_pc(&space->device()));
	505	printf("bg -> %d %d   %d %d  %d %d @ %x\n",dst_x0,dst_y0, dst_x1,dst_y1, dst_x1-dst_x0, dst_y1-dst_y0,cpu_get_pc(&space.device()));
499	506
500	507	for(int i=0;i<16;++i)
501	508	{
502		printf("%x = %.4x\n",i,state->m_blitter_data[i]);
	509	printf("%x = %.4x\n",i,m_blitter_data[i]);
503	510	}
504	511
505	512	printf("\n");
r14845	r14846
509	516	bool endx=false;
510	517	bool endy=false;
511	518
512		if(state->m_blitter_data[0x7]&0x0c)
	519	if(m_blitter_data[0x7]&0x0c)
513	520	{
514	521	//???
515	522	}
r14845	r14846
539	546	//hack for clear
540	547	if(screen_x >0 && screen_y >0 && screen_x < width && screen_y <height)
541	548	{
542		//      state->m_tmp_bitmap[vpage]->pix16(screen_y , screen_x ) =0;
	549	//      m_tmp_bitmap[vpage]->pix16(screen_y , screen_x ) =0;
543	550	}
544	551	}
545	552	else
r14845	r14846
548	555
549	556	if(pix && screen_x >0 && screen_y >0 && screen_x < width && screen_y <height)
550	557	{
551		state->m_tmp_bitmap[vpage]->pix16(screen_y , screen_x ) = pix;
	558	m_tmp_bitmap[vpage]->pix16(screen_y , screen_x ) = pix;
552	559	}
553	560	}
554	561	}
r14845	r14846
606	613	}
607	614
608	615
609		static WRITE16_HANDLER( pal_reset_pos_w )
	616	WRITE16_MEMBER(wheelfir_state::pal_reset_pos_w)
610	617	{
611		wheelfir_state *state = space->machine().driver_data<wheelfir_state>();
612		state->m_palpos = 0;
	618	m_palpos = 0;
613	619	}
614	620
615		static WRITE16_HANDLER( pal_data_w )
	621	WRITE16_MEMBER(wheelfir_state::pal_data_w)
616	622	{
617		wheelfir_state *state = space->machine().driver_data<wheelfir_state>();
618		int color=state->m_palpos/3;
619		state->m_palette[state->m_palpos] = data & 0xff;
620		++state->m_palpos;
	623	int color=m_palpos/3;
	624	m_palette[m_palpos] = data & 0xff;
	625	++m_palpos;
621	626
622		state->m_palpos %=NUM_COLORS*3;
	627	m_palpos %=NUM_COLORS*3;
623	628
624	629	{
625		int r = state->m_palette[color*3];
626		int g = state->m_palette[color*3+1];
627		int b = state->m_palette[color*3+2];
628		palette_set_color(space->machine(), color, MAKE_RGB(r,g,b));
	630	int r = m_palette[color*3];
	631	int g = m_palette[color*3+1];
	632	int b = m_palette[color*3+2];
	633	palette_set_color(machine(), color, MAKE_RGB(r,g,b));
629	634	}
630	635
631	636	}
632	637
633		static WRITE16_HANDLER(wheelfir_7c0000_w)
	638	WRITE16_MEMBER(wheelfir_state::wheelfir_7c0000_w)
634	639	{
635	640	/* seems to be scanline width/2 (used for scanline int timing ? or real width of scanline ?) */
636	641	}
637	642
638		static WRITE16_HANDLER(wheelfir_snd_w)
	643	WRITE16_MEMBER(wheelfir_state::wheelfir_snd_w)
639	644	{
640		wheelfir_state *state = space->machine().driver_data<wheelfir_state>();
641		COMBINE_DATA(&state->m_soundlatch);
642		cputag_set_input_line(space->machine(), "subcpu", 1, HOLD_LINE); /* guess, tested also with periodic interrupts and latch clear*/
643		space->machine().scheduler().synchronize();
	645	COMBINE_DATA(&m_soundlatch);
	646	cputag_set_input_line(machine(), "subcpu", 1, HOLD_LINE); /* guess, tested also with periodic interrupts and latch clear*/
	647	machine().scheduler().synchronize();
644	648	}
645	649
646		static READ16_HANDLER( wheelfir_snd_r )
	650	READ16_MEMBER(wheelfir_state::wheelfir_snd_r)
647	651	{
648		wheelfir_state *state = space->machine().driver_data<wheelfir_state>();
649		return state->m_soundlatch;
	652	return m_soundlatch;
650	653	}
651	654
652		static WRITE16_HANDLER(coin_cnt_w)
	655	WRITE16_MEMBER(wheelfir_state::coin_cnt_w)
653	656	{
654	657	/* bits 0/1 coin counters */
655		coin_counter_w(space->machine(), 0, data & 0x01);
656		coin_counter_w(space->machine(), 1, data & 0x02);
	658	coin_counter_w(machine(), 0, data & 0x01);
	659	coin_counter_w(machine(), 1, data & 0x02);
657	660	}
658	661
659	662
r14845	r14846
661	664	AM_RANGE(0x000000, 0x0fffff) AM_ROM
662	665	AM_RANGE(0x200000, 0x20ffff) AM_RAM
663	666
664		AM_RANGE(0x700000, 0x70001f) AM_WRITE_LEGACY(wheelfir_blit_w)
665		AM_RANGE(0x720000, 0x720001) AM_WRITE_LEGACY(pal_reset_pos_w)
666		AM_RANGE(0x720002, 0x720003) AM_WRITE_LEGACY(pal_data_w)
	667	AM_RANGE(0x700000, 0x70001f) AM_WRITE(wheelfir_blit_w)
	668	AM_RANGE(0x720000, 0x720001) AM_WRITE(pal_reset_pos_w)
	669	AM_RANGE(0x720002, 0x720003) AM_WRITE(pal_data_w)
667	670	AM_RANGE(0x720004, 0x720005) AM_WRITENOP // always ffff?
668		AM_RANGE(0x740000, 0x740001) AM_WRITE_LEGACY(wheelfir_snd_w)
	671	AM_RANGE(0x740000, 0x740001) AM_WRITE(wheelfir_snd_w)
669	672	AM_RANGE(0x780000, 0x78000f) AM_READNOP /* net comms ? */
670		AM_RANGE(0x760000, 0x760001) AM_WRITE_LEGACY(coin_cnt_w)
671		AM_RANGE(0x7a0000, 0x7a0001) AM_WRITE_LEGACY(wheelfir_scanline_cnt_w)
672		AM_RANGE(0x7c0000, 0x7c0001) AM_READWRITE_LEGACY(wheelfir_status_r, wheelfir_7c0000_w)
	673	AM_RANGE(0x760000, 0x760001) AM_WRITE(coin_cnt_w)
	674	AM_RANGE(0x7a0000, 0x7a0001) AM_WRITE(wheelfir_scanline_cnt_w)
	675	AM_RANGE(0x7c0000, 0x7c0001) AM_READWRITE(wheelfir_status_r, wheelfir_7c0000_w)
673	676	AM_RANGE(0x7e0000, 0x7e0001) AM_READ_PORT("P1")
674	677	AM_RANGE(0x7e0002, 0x7e0003) AM_READ_PORT("P2")
675	678
r14845	r14846
681	684	AM_RANGE(0x000000, 0x0fffff) AM_ROM
682	685	AM_RANGE(0x200000, 0x20ffff) AM_RAM
683	686
684		AM_RANGE(0x780000, 0x780001) AM_READ_LEGACY(wheelfir_snd_r)
	687	AM_RANGE(0x780000, 0x780001) AM_READ(wheelfir_snd_r)
685	688
686	689	AM_RANGE(0x700000, 0x700001) AM_DEVWRITE8_LEGACY("dac1", dac_w, 0xff00) //guess for now
687	690	AM_RANGE(0x740000, 0x740001) AM_DEVWRITE8_LEGACY("dac2", dac_w, 0xff00)

src/mame/drivers/onetwo.c

r14845	r14846
63	63	/* devices */
64	64	device_t *m_maincpu;
65	65	device_t *m_audiocpu;
	66	DECLARE_WRITE8_MEMBER(onetwo_fgram_w);
	67	DECLARE_WRITE8_MEMBER(onetwo_cpubank_w);
	68	DECLARE_WRITE8_MEMBER(onetwo_coin_counters_w);
	69	DECLARE_WRITE8_MEMBER(onetwo_soundlatch_w);
	70	DECLARE_WRITE8_MEMBER(palette1_w);
	71	DECLARE_WRITE8_MEMBER(palette2_w);
66	72	};
67	73
68	74
r14845	r14846
103	109	*
104	110	*************************************/
105	111
106		static WRITE8_HANDLER( onetwo_fgram_w )
	112	WRITE8_MEMBER(onetwo_state::onetwo_fgram_w)
107	113	{
108		onetwo_state *state = space->machine().driver_data<onetwo_state>();
109		state->m_fgram[offset] = data;
110		state->m_fg_tilemap->mark_tile_dirty(offset / 2);
	114	m_fgram[offset] = data;
	115	m_fg_tilemap->mark_tile_dirty(offset / 2);
111	116	}
112	117
113		static WRITE8_HANDLER( onetwo_cpubank_w )
	118	WRITE8_MEMBER(onetwo_state::onetwo_cpubank_w)
114	119	{
115		memory_set_bank(space->machine(), "bank1", data);
	120	memory_set_bank(machine(), "bank1", data);
116	121	}
117	122
118		static WRITE8_HANDLER( onetwo_coin_counters_w )
	123	WRITE8_MEMBER(onetwo_state::onetwo_coin_counters_w)
119	124	{
120		watchdog_reset(space->machine());
121		coin_counter_w(space->machine(), 0, BIT(data, 1));
122		coin_counter_w(space->machine(), 1, BIT(data, 2));
	125	watchdog_reset(machine());
	126	coin_counter_w(machine(), 0, BIT(data, 1));
	127	coin_counter_w(machine(), 1, BIT(data, 2));
123	128	}
124	129
125		static WRITE8_HANDLER( onetwo_soundlatch_w )
	130	WRITE8_MEMBER(onetwo_state::onetwo_soundlatch_w)
126	131	{
127		onetwo_state *state = space->machine().driver_data<onetwo_state>();
128	132	soundlatch_w(space, 0, data);
129		device_set_input_line(state->m_audiocpu, INPUT_LINE_NMI, PULSE_LINE);
	133	device_set_input_line(m_audiocpu, INPUT_LINE_NMI, PULSE_LINE);
130	134	}
131	135
132	136	static void set_color(running_machine &machine, int offset)
r14845	r14846
140	144	palette_set_color_rgb(machine, offset, pal5bit(r), pal5bit(g), pal5bit(b));
141	145	}
142	146
143		static WRITE8_HANDLER(palette1_w)
	147	WRITE8_MEMBER(onetwo_state::palette1_w)
144	148	{
145		onetwo_state *state = space->machine().driver_data<onetwo_state>();
146		state->m_paletteram[offset] = data;
147		set_color(space->machine(), offset);
	149	m_paletteram[offset] = data;
	150	set_color(machine(), offset);
148	151	}
149	152
150		static WRITE8_HANDLER(palette2_w)
	153	WRITE8_MEMBER(onetwo_state::palette2_w)
151	154	{
152		onetwo_state *state = space->machine().driver_data<onetwo_state>();
153		state->m_paletteram2[offset] = data;
154		set_color(space->machine(), offset);
	155	m_paletteram2[offset] = data;
	156	set_color(machine(), offset);
155	157	}
156	158
157	159	/*************************************
r14845	r14846
163	165	static ADDRESS_MAP_START( main_cpu, AS_PROGRAM, 8, onetwo_state )
164	166	AM_RANGE(0x0000, 0x7fff) AM_ROM AM_REGION("maincpu", 0x10000)
165	167	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
166		AM_RANGE(0xc800, 0xc87f) AM_RAM_WRITE_LEGACY(palette1_w) AM_BASE(m_paletteram)
167		AM_RANGE(0xc900, 0xc97f) AM_RAM_WRITE_LEGACY(palette2_w) AM_BASE(m_paletteram2)
168		AM_RANGE(0xd000, 0xdfff) AM_RAM_WRITE_LEGACY(onetwo_fgram_w) AM_BASE(m_fgram)
	168	AM_RANGE(0xc800, 0xc87f) AM_RAM_WRITE(palette1_w) AM_BASE(m_paletteram)
	169	AM_RANGE(0xc900, 0xc97f) AM_RAM_WRITE(palette2_w) AM_BASE(m_paletteram2)
	170	AM_RANGE(0xd000, 0xdfff) AM_RAM_WRITE(onetwo_fgram_w) AM_BASE(m_fgram)
169	171	AM_RANGE(0xe000, 0xffff) AM_RAM
170	172	ADDRESS_MAP_END
171	173
172	174	static ADDRESS_MAP_START( main_cpu_io, AS_IO, 8, onetwo_state )
173	175	ADDRESS_MAP_GLOBAL_MASK(0xff)
174		AM_RANGE(0x00, 0x00) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(onetwo_coin_counters_w)
175		AM_RANGE(0x01, 0x01) AM_READ_PORT("DSW2") AM_WRITE_LEGACY(onetwo_soundlatch_w)
176		AM_RANGE(0x02, 0x02) AM_READ_PORT("P1") AM_WRITE_LEGACY(onetwo_cpubank_w)
	176	AM_RANGE(0x00, 0x00) AM_READ_PORT("DSW1") AM_WRITE(onetwo_coin_counters_w)
	177	AM_RANGE(0x01, 0x01) AM_READ_PORT("DSW2") AM_WRITE(onetwo_soundlatch_w)
	178	AM_RANGE(0x02, 0x02) AM_READ_PORT("P1") AM_WRITE(onetwo_cpubank_w)
177	179	AM_RANGE(0x03, 0x03) AM_READ_PORT("P2")
178	180	AM_RANGE(0x04, 0x04) AM_READ_PORT("SYSTEM")
179	181	ADDRESS_MAP_END

src/mame/drivers/vamphalf.c

r14845	r14846
83	83	UINT16 m_finalgdr_backupram_bank;
84	84	UINT8 *m_finalgdr_backupram;
85	85	int m_has_extra_gfx;
	86	DECLARE_WRITE16_MEMBER(flipscreen_w);
	87	DECLARE_WRITE32_MEMBER(flipscreen32_w);
	88	DECLARE_WRITE16_MEMBER(jmpbreak_flipscreen_w);
	89	DECLARE_WRITE32_MEMBER(paletteram32_w);
	90	DECLARE_READ32_MEMBER(wyvernwg_prot_r);
	91	DECLARE_WRITE32_MEMBER(wyvernwg_prot_w);
	92	DECLARE_READ32_MEMBER(finalgdr_prot_r);
	93	DECLARE_WRITE32_MEMBER(finalgdr_prot_w);
	94	DECLARE_WRITE32_MEMBER(finalgdr_backupram_bank_w);
	95	DECLARE_READ32_MEMBER(finalgdr_backupram_r);
	96	DECLARE_WRITE32_MEMBER(finalgdr_backupram_w);
	97	DECLARE_WRITE32_MEMBER(finalgdr_prize_w);
	98	DECLARE_WRITE16_MEMBER(boonggab_prize_w);
	99	DECLARE_WRITE16_MEMBER(boonggab_lamps_w);
	100	DECLARE_READ16_MEMBER(vamphalf_speedup_r);
	101	DECLARE_READ16_MEMBER(vamphafk_speedup_r);
	102	DECLARE_READ16_MEMBER(misncrft_speedup_r);
	103	DECLARE_READ16_MEMBER(coolmini_speedup_r);
	104	DECLARE_READ16_MEMBER(suplup_speedup_r);
	105	DECLARE_READ16_MEMBER(luplup_speedup_r);
	106	DECLARE_READ16_MEMBER(luplup29_speedup_r);
	107	DECLARE_READ16_MEMBER(puzlbang_speedup_r);
	108	DECLARE_READ32_MEMBER(wyvernwg_speedup_r);
	109	DECLARE_READ32_MEMBER(wyvernwga_speedup_r);
	110	DECLARE_READ32_MEMBER(finalgdr_speedup_r);
	111	DECLARE_READ32_MEMBER(mrkicker_speedup_r);
	112	DECLARE_READ16_MEMBER(dquizgo2_speedup_r);
	113	DECLARE_READ32_MEMBER(aoh_speedup_r);
	114	DECLARE_READ16_MEMBER(jmpbreak_speedup_r);
	115	DECLARE_READ16_MEMBER(mrdig_speedup_r);
	116	DECLARE_READ16_MEMBER(dtfamily_speedup_r);
	117	DECLARE_READ16_MEMBER(toyland_speedup_r);
	118	DECLARE_READ16_MEMBER(boonggab_speedup_r);
86	119	};
87	120
88	121	static READ16_DEVICE_HANDLER( eeprom_r )
r14845	r14846
131	164	eeprom->set_clock_line((data & 0x2000) ? ASSERT_LINE : CLEAR_LINE );
132	165	}
133	166
134		static WRITE16_HANDLER( flipscreen_w )
	167	WRITE16_MEMBER(vamphalf_state::flipscreen_w)
135	168	{
136	169	if(offset)
137	170	{
138		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
139		state->m_flipscreen = data & state->m_flip_bit;
	171	m_flipscreen = data & m_flip_bit;
140	172	}
141	173	}
142	174
143		static WRITE32_HANDLER( flipscreen32_w )
	175	WRITE32_MEMBER(vamphalf_state::flipscreen32_w)
144	176	{
145		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
146		state->m_flipscreen = data & state->m_flip_bit;
	177	m_flipscreen = data & m_flip_bit;
147	178	}
148	179
149		static WRITE16_HANDLER( jmpbreak_flipscreen_w )
	180	WRITE16_MEMBER(vamphalf_state::jmpbreak_flipscreen_w)
150	181	{
151		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
152		state->m_flipscreen = data & 0x8000;
	182	m_flipscreen = data & 0x8000;
153	183	}
154	184
155	185
156		static WRITE32_HANDLER( paletteram32_w )
	186	WRITE32_MEMBER(vamphalf_state::paletteram32_w)
157	187	{
158	188	UINT16 paldata;
159	189
160		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
	190	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
161	191
162		paldata = space->machine().generic.paletteram.u32[offset] & 0xffff;
163		palette_set_color_rgb(space->machine(), offset*2 + 1, pal5bit(paldata >> 10), pal5bit(paldata >> 5), pal5bit(paldata >> 0));
	192	paldata = machine().generic.paletteram.u32[offset] & 0xffff;
	193	palette_set_color_rgb(machine(), offset*2 + 1, pal5bit(paldata >> 10), pal5bit(paldata >> 5), pal5bit(paldata >> 0));
164	194
165		paldata = (space->machine().generic.paletteram.u32[offset] >> 16) & 0xffff;
166		palette_set_color_rgb(space->machine(), offset*2 + 0, pal5bit(paldata >> 10), pal5bit(paldata >> 5), pal5bit(paldata >> 0));
	195	paldata = (machine().generic.paletteram.u32[offset] >> 16) & 0xffff;
	196	palette_set_color_rgb(machine(), offset*2 + 0, pal5bit(paldata >> 10), pal5bit(paldata >> 5), pal5bit(paldata >> 0));
167	197	}
168	198
169		static READ32_HANDLER( wyvernwg_prot_r )
	199	READ32_MEMBER(vamphalf_state::wyvernwg_prot_r)
170	200	{
171		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
172		state->m_semicom_prot_idx--;
173		return (state->m_semicom_prot_data[state->m_semicom_prot_which] & (1 << state->m_semicom_prot_idx)) >> state->m_semicom_prot_idx;
	201	m_semicom_prot_idx--;
	202	return (m_semicom_prot_data[m_semicom_prot_which] & (1 << m_semicom_prot_idx)) >> m_semicom_prot_idx;
174	203	}
175	204
176		static WRITE32_HANDLER( wyvernwg_prot_w )
	205	WRITE32_MEMBER(vamphalf_state::wyvernwg_prot_w)
177	206	{
178		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
179		state->m_semicom_prot_which = data & 1;
180		state->m_semicom_prot_idx = 8;
	207	m_semicom_prot_which = data & 1;
	208	m_semicom_prot_idx = 8;
181	209	}
182	210
183		static READ32_HANDLER( finalgdr_prot_r )
	211	READ32_MEMBER(vamphalf_state::finalgdr_prot_r)
184	212	{
185		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
186		state->m_semicom_prot_idx--;
187		return (state->m_semicom_prot_data[state->m_semicom_prot_which] & (1 << state->m_semicom_prot_idx)) ? 0x8000 : 0;
	213	m_semicom_prot_idx--;
	214	return (m_semicom_prot_data[m_semicom_prot_which] & (1 << m_semicom_prot_idx)) ? 0x8000 : 0;
188	215	}
189	216
190		static WRITE32_HANDLER( finalgdr_prot_w )
	217	WRITE32_MEMBER(vamphalf_state::finalgdr_prot_w)
191	218	{
192		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
193	219	/*
194	220	41C6
195	221	967E
r14845	r14846
197	223	F94B
198	224	*/
199	225	if(data == 0x41c6 || data == 0x446b)
200		state->m_semicom_prot_which = 0;
	226	m_semicom_prot_which = 0;
201	227	else
202		state->m_semicom_prot_which =  1;
	228	m_semicom_prot_which =  1;
203	229
204		state->m_semicom_prot_idx = 8;
	230	m_semicom_prot_idx = 8;
205	231	}
206	232
207	233	static WRITE32_DEVICE_HANDLER( finalgdr_oki_bank_w )
r14845	r14846
209	235	downcast<okim6295_device *>(device)->set_bank_base(0x40000 * ((data & 0x300) >> 8));
210	236	}
211	237
212		static WRITE32_HANDLER( finalgdr_backupram_bank_w )
	238	WRITE32_MEMBER(vamphalf_state::finalgdr_backupram_bank_w)
213	239	{
214		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
215		state->m_finalgdr_backupram_bank = (data & 0xff000000) >> 24;
	240	m_finalgdr_backupram_bank = (data & 0xff000000) >> 24;
216	241	}
217	242
218		static READ32_HANDLER( finalgdr_backupram_r )
	243	READ32_MEMBER(vamphalf_state::finalgdr_backupram_r)
219	244	{
220		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
221		return state->m_finalgdr_backupram[offset + state->m_finalgdr_backupram_bank * 0x80] << 24;
	245	return m_finalgdr_backupram[offset + m_finalgdr_backupram_bank * 0x80] << 24;
222	246	}
223	247
224		static WRITE32_HANDLER( finalgdr_backupram_w )
	248	WRITE32_MEMBER(vamphalf_state::finalgdr_backupram_w)
225	249	{
226		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
227		state->m_finalgdr_backupram[offset + state->m_finalgdr_backupram_bank * 0x80] = data >> 24;
	250	m_finalgdr_backupram[offset + m_finalgdr_backupram_bank * 0x80] = data >> 24;
228	251	}
229	252
230		static WRITE32_HANDLER( finalgdr_prize_w )
	253	WRITE32_MEMBER(vamphalf_state::finalgdr_prize_w)
231	254	{
232	255	if(data & 0x1000000)
233	256	{
r14845	r14846
256	279	downcast<okim6295_device *>(device)->set_bank_base(0x40000 * (data & 0x7));
257	280	}
258	281
259		static WRITE16_HANDLER( boonggab_prize_w )
	282	WRITE16_MEMBER(vamphalf_state::boonggab_prize_w)
260	283	{
261	284	if(offset)
262	285	{
r14845	r14846
270	293	}
271	294	}
272	295
273		static WRITE16_HANDLER( boonggab_lamps_w )
	296	WRITE16_MEMBER(vamphalf_state::boonggab_lamps_w)
274	297	{
275	298	if(offset == 1)
276	299	{
r14845	r14846
304	327	static ADDRESS_MAP_START( common_32bit_map, AS_PROGRAM, 32, vamphalf_state )
305	328	AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_BASE(m_wram32)
306	329	AM_RANGE(0x40000000, 0x4003ffff) AM_RAM AM_BASE(m_tiles32)
307		AM_RANGE(0x80000000, 0x8000ffff) AM_RAM_WRITE_LEGACY(paletteram32_w) AM_BASE_GENERIC(paletteram)
	330	AM_RANGE(0x80000000, 0x8000ffff) AM_RAM_WRITE(paletteram32_w) AM_BASE_GENERIC(paletteram)
308	331	AM_RANGE(0xfff00000, 0xffffffff) AM_ROM AM_REGION("user1",0)
309	332	ADDRESS_MAP_END
310	333
r14845	r14846
314	337	AM_RANGE(0x140, 0x143) AM_DEVWRITE8_LEGACY("ymsnd", ym2151_register_port_w, 0x00ff)
315	338	AM_RANGE(0x146, 0x147) AM_DEVREADWRITE8_LEGACY("ymsnd", ym2151_status_port_r, ym2151_data_port_w, 0x00ff)
316	339	AM_RANGE(0x1c0, 0x1c3) AM_DEVREAD_LEGACY("eeprom", eeprom_r)
317		AM_RANGE(0x240, 0x243) AM_WRITE_LEGACY(flipscreen_w)
	340	AM_RANGE(0x240, 0x243) AM_WRITE(flipscreen_w)
318	341	AM_RANGE(0x600, 0x603) AM_READ_PORT("SYSTEM")
319	342	AM_RANGE(0x604, 0x607) AM_READ_PORT("P1_P2")
320	343	AM_RANGE(0x608, 0x60b) AM_DEVWRITE_LEGACY("eeprom", eeprom_w)
321	344	ADDRESS_MAP_END
322	345
323	346	static ADDRESS_MAP_START( misncrft_io, AS_IO, 16, vamphalf_state )
324		AM_RANGE(0x100, 0x103) AM_WRITE_LEGACY(flipscreen_w)
	347	AM_RANGE(0x100, 0x103) AM_WRITE(flipscreen_w)
325	348	AM_RANGE(0x200, 0x203) AM_READ_PORT("P1_P2")
326	349	AM_RANGE(0x240, 0x243) AM_READ_PORT("SYSTEM")
327	350	AM_RANGE(0x3c0, 0x3c3) AM_DEVWRITE_LEGACY("eeprom", eeprom_w)
r14845	r14846
329	352	ADDRESS_MAP_END
330	353
331	354	static ADDRESS_MAP_START( coolmini_io, AS_IO, 16, vamphalf_state )
332		AM_RANGE(0x200, 0x203) AM_WRITE_LEGACY(flipscreen_w)
	355	AM_RANGE(0x200, 0x203) AM_WRITE(flipscreen_w)
333	356	AM_RANGE(0x300, 0x303) AM_READ_PORT("SYSTEM")
334	357	AM_RANGE(0x304, 0x307) AM_READ_PORT("P1_P2")
335	358	AM_RANGE(0x308, 0x30b) AM_DEVWRITE_LEGACY("eeprom", eeprom_w)
r14845	r14846
352	375	ADDRESS_MAP_END
353	376
354	377	static ADDRESS_MAP_START( wyvernwg_io, AS_IO, 32, vamphalf_state )
355		AM_RANGE(0x1800, 0x1803) AM_READWRITE_LEGACY(wyvernwg_prot_r, wyvernwg_prot_w)
356		AM_RANGE(0x2000, 0x2003) AM_WRITE_LEGACY(flipscreen32_w)
	378	AM_RANGE(0x1800, 0x1803) AM_READWRITE(wyvernwg_prot_r, wyvernwg_prot_w)
	379	AM_RANGE(0x2000, 0x2003) AM_WRITE(flipscreen32_w)
357	380	AM_RANGE(0x2800, 0x2803) AM_READ_PORT("P1_P2")
358	381	AM_RANGE(0x3000, 0x3003) AM_READ_PORT("SYSTEM")
359	382	AM_RANGE(0x5400, 0x5403) AM_WRITENOP // soundlatch
r14845	r14846
362	385	ADDRESS_MAP_END
363	386
364	387	static ADDRESS_MAP_START( finalgdr_io, AS_IO, 32, vamphalf_state )
365		AM_RANGE(0x2400, 0x2403) AM_READ_LEGACY(finalgdr_prot_r)
366		AM_RANGE(0x2800, 0x2803) AM_WRITE_LEGACY(finalgdr_backupram_bank_w)
367		AM_RANGE(0x2c00, 0x2dff) AM_READWRITE_LEGACY(finalgdr_backupram_r, finalgdr_backupram_w)
	388	AM_RANGE(0x2400, 0x2403) AM_READ(finalgdr_prot_r)
	389	AM_RANGE(0x2800, 0x2803) AM_WRITE(finalgdr_backupram_bank_w)
	390	AM_RANGE(0x2c00, 0x2dff) AM_READWRITE(finalgdr_backupram_r, finalgdr_backupram_w)
368	391	AM_RANGE(0x3000, 0x3007) AM_DEVREADWRITE8_LEGACY("ymsnd", ym2151_r, ym2151_w, 0x0000ff00)
369	392	AM_RANGE(0x3800, 0x3803) AM_READ_PORT("P1_P2")
370	393	AM_RANGE(0x3400, 0x3403) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x0000ff00)
r14845	r14846
372	395	AM_RANGE(0x4400, 0x4403) AM_DEVREAD_LEGACY("eeprom", eeprom32_r)
373	396	AM_RANGE(0x6000, 0x6003) AM_READNOP //?
374	397	AM_RANGE(0x6000, 0x6003) AM_DEVWRITE_LEGACY("eeprom", finalgdr_eeprom_w)
375		AM_RANGE(0x6040, 0x6043) AM_WRITE_LEGACY(finalgdr_prot_w)
376		//AM_RANGE(0x6080, 0x6083) AM_WRITE_LEGACY(flipscreen32_w) //?
377		AM_RANGE(0x6060, 0x6063) AM_WRITE_LEGACY(finalgdr_prize_w)
	398	AM_RANGE(0x6040, 0x6043) AM_WRITE(finalgdr_prot_w)
	399	//AM_RANGE(0x6080, 0x6083) AM_WRITE(flipscreen32_w) //?
	400	AM_RANGE(0x6060, 0x6063) AM_WRITE(finalgdr_prize_w)
378	401	AM_RANGE(0x60a0, 0x60a3) AM_DEVWRITE_LEGACY("oki", finalgdr_oki_bank_w)
379	402	ADDRESS_MAP_END
380	403
r14845	r14846
382	405	AM_RANGE(0x2400, 0x2403) AM_DEVREAD_LEGACY("eeprom", eeprom32_r)
383	406	AM_RANGE(0x4000, 0x4003) AM_READNOP //?
384	407	AM_RANGE(0x4000, 0x4003) AM_DEVWRITE_LEGACY("eeprom", finalgdr_eeprom_w)
385		AM_RANGE(0x4040, 0x4043) AM_WRITE_LEGACY(finalgdr_prot_w)
	408	AM_RANGE(0x4040, 0x4043) AM_WRITE(finalgdr_prot_w)
386	409	AM_RANGE(0x4084, 0x4087) AM_WRITENOP //?
387	410	AM_RANGE(0x40a0, 0x40a3) AM_DEVWRITE_LEGACY("oki", finalgdr_oki_bank_w)
388		AM_RANGE(0x6400, 0x6403) AM_READ_LEGACY(finalgdr_prot_r)
	411	AM_RANGE(0x6400, 0x6403) AM_READ(finalgdr_prot_r)
389	412	AM_RANGE(0x7000, 0x7007) AM_DEVREADWRITE8_LEGACY("ymsnd", ym2151_r, ym2151_w, 0x0000ff00)
390	413	AM_RANGE(0x7400, 0x7403) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x0000ff00)
391	414	AM_RANGE(0x7800, 0x7803) AM_READ_PORT("P1_P2")
r14845	r14846
419	442	static ADDRESS_MAP_START( aoh_map, AS_PROGRAM, 32, vamphalf_state )
420	443	AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_BASE(m_wram32)
421	444	AM_RANGE(0x40000000, 0x4003ffff) AM_RAM AM_BASE(m_tiles32)
422		AM_RANGE(0x80000000, 0x8000ffff) AM_RAM_WRITE_LEGACY(paletteram32_w) AM_BASE_GENERIC(paletteram)
	445	AM_RANGE(0x80000000, 0x8000ffff) AM_RAM_WRITE(paletteram32_w) AM_BASE_GENERIC(paletteram)
423	446	AM_RANGE(0x80210000, 0x80210003) AM_READ_PORT("SYSTEM")
424	447	AM_RANGE(0x80220000, 0x80220003) AM_READ_PORT("P1_P2")
425	448	AM_RANGE(0xffc00000, 0xffffffff) AM_ROM AM_REGION("user1",0)
r14845	r14846
436	459	static ADDRESS_MAP_START( boonggab_io, AS_IO, 16, vamphalf_state )
437	460	AM_RANGE(0x0c0, 0x0c3) AM_DEVREAD_LEGACY("eeprom", eeprom_r)
438	461	AM_RANGE(0x200, 0x203) AM_NOP // seems unused
439		AM_RANGE(0x300, 0x303) AM_WRITE_LEGACY(flipscreen_w)
	462	AM_RANGE(0x300, 0x303) AM_WRITE(flipscreen_w)
440	463	AM_RANGE(0x400, 0x403) AM_READ_PORT("SYSTEM")
441	464	AM_RANGE(0x404, 0x407) AM_READ_PORT("P1_P2")
442	465	AM_RANGE(0x408, 0x40b) AM_DEVWRITE_LEGACY("eeprom", eeprom_w)
443		AM_RANGE(0x410, 0x413) AM_WRITE_LEGACY(boonggab_prize_w)
444		AM_RANGE(0x414, 0x41b) AM_WRITE_LEGACY(boonggab_lamps_w)
	466	AM_RANGE(0x410, 0x413) AM_WRITE(boonggab_prize_w)
	467	AM_RANGE(0x414, 0x41b) AM_WRITE(boonggab_lamps_w)
445	468	AM_RANGE(0x600, 0x603) AM_DEVWRITE_LEGACY("oki", boonggab_oki_bank_w)
446	469	AM_RANGE(0x700, 0x701) AM_NOP // return 0, when oki chip is read / written
447	470	AM_RANGE(0x702, 0x703) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
r14845	r14846
2050	2073	return 0;
2051	2074	}
2052	2075
2053		static READ16_HANDLER( vamphalf_speedup_r )
	2076	READ16_MEMBER(vamphalf_state::vamphalf_speedup_r)
2054	2077	{
2055		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2056		if(cpu_get_pc(&space->device()) == 0x82de)
	2078	if(cpu_get_pc(&space.device()) == 0x82de)
2057	2079	{
2058		if(irq_active(space))
2059		device_spin_until_interrupt(&space->device());
	2080	if(irq_active(&space))
	2081	device_spin_until_interrupt(&space.device());
2060	2082	else
2061		device_eat_cycles(&space->device(), 50);
	2083	device_eat_cycles(&space.device(), 50);
2062	2084	}
2063	2085
2064		return state->m_wram[(0x4a840/2)+offset];
	2086	return m_wram[(0x4a840/2)+offset];
2065	2087	}
2066	2088
2067		static READ16_HANDLER( vamphafk_speedup_r )
	2089	READ16_MEMBER(vamphalf_state::vamphafk_speedup_r)
2068	2090	{
2069		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2070		if(cpu_get_pc(&space->device()) == 0x82de)
	2091	if(cpu_get_pc(&space.device()) == 0x82de)
2071	2092	{
2072		if(irq_active(space))
2073		device_spin_until_interrupt(&space->device());
	2093	if(irq_active(&space))
	2094	device_spin_until_interrupt(&space.device());
2074	2095	else
2075		device_eat_cycles(&space->device(), 50);
	2096	device_eat_cycles(&space.device(), 50);
2076	2097	}
2077	2098
2078		return state->m_wram[(0x4a6d0/2)+offset];
	2099	return m_wram[(0x4a6d0/2)+offset];
2079	2100	}
2080	2101
2081		static READ16_HANDLER( misncrft_speedup_r )
	2102	READ16_MEMBER(vamphalf_state::misncrft_speedup_r)
2082	2103	{
2083		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2084		if(cpu_get_pc(&space->device()) == 0xecc8)
	2104	if(cpu_get_pc(&space.device()) == 0xecc8)
2085	2105	{
2086		if(irq_active(space))
2087		device_spin_until_interrupt(&space->device());
	2106	if(irq_active(&space))
	2107	device_spin_until_interrupt(&space.device());
2088	2108	else
2089		device_eat_cycles(&space->device(), 50);
	2109	device_eat_cycles(&space.device(), 50);
2090	2110	}
2091	2111
2092		return state->m_wram[(0x72eb4/2)+offset];
	2112	return m_wram[(0x72eb4/2)+offset];
2093	2113	}
2094	2114
2095		static READ16_HANDLER( coolmini_speedup_r )
	2115	READ16_MEMBER(vamphalf_state::coolmini_speedup_r)
2096	2116	{
2097		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2098		if(cpu_get_pc(&space->device()) == 0x75f7a)
	2117	if(cpu_get_pc(&space.device()) == 0x75f7a)
2099	2118	{
2100		if(irq_active(space))
2101		device_spin_until_interrupt(&space->device());
	2119	if(irq_active(&space))
	2120	device_spin_until_interrupt(&space.device());
2102	2121	else
2103		device_eat_cycles(&space->device(), 50);
	2122	device_eat_cycles(&space.device(), 50);
2104	2123	}
2105	2124
2106		return state->m_wram[(0xd2e80/2)+offset];
	2125	return m_wram[(0xd2e80/2)+offset];
2107	2126	}
2108	2127
2109		static READ16_HANDLER( suplup_speedup_r )
	2128	READ16_MEMBER(vamphalf_state::suplup_speedup_r)
2110	2129	{
2111		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2112		if(cpu_get_pc(&space->device()) == 0xaf18a )
	2130	if(cpu_get_pc(&space.device()) == 0xaf18a )
2113	2131	{
2114		if(irq_active(space))
2115		device_spin_until_interrupt(&space->device());
	2132	if(irq_active(&space))
	2133	device_spin_until_interrupt(&space.device());
2116	2134	else
2117		device_eat_cycles(&space->device(), 50);
	2135	device_eat_cycles(&space.device(), 50);
2118	2136	}
2119	2137
2120		return state->m_wram[(0x11605c/2)+offset];
	2138	return m_wram[(0x11605c/2)+offset];
2121	2139	}
2122	2140
2123		static READ16_HANDLER( luplup_speedup_r )
	2141	READ16_MEMBER(vamphalf_state::luplup_speedup_r)
2124	2142	{
2125		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2126		if(cpu_get_pc(&space->device()) == 0xaefac )
	2143	if(cpu_get_pc(&space.device()) == 0xaefac )
2127	2144	{
2128		if(irq_active(space))
2129		device_spin_until_interrupt(&space->device());
	2145	if(irq_active(&space))
	2146	device_spin_until_interrupt(&space.device());
2130	2147	else
2131		device_eat_cycles(&space->device(), 50);
	2148	device_eat_cycles(&space.device(), 50);
2132	2149	}
2133	2150
2134		return state->m_wram[(0x115e84/2)+offset];
	2151	return m_wram[(0x115e84/2)+offset];
2135	2152	}
2136	2153
2137		static READ16_HANDLER( luplup29_speedup_r )
	2154	READ16_MEMBER(vamphalf_state::luplup29_speedup_r)
2138	2155	{
2139		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2140		if(cpu_get_pc(&space->device()) == 0xae6c0 )
	2156	if(cpu_get_pc(&space.device()) == 0xae6c0 )
2141	2157	{
2142		if(irq_active(space))
2143		device_spin_until_interrupt(&space->device());
	2158	if(irq_active(&space))
	2159	device_spin_until_interrupt(&space.device());
2144	2160	else
2145		device_eat_cycles(&space->device(), 50);
	2161	device_eat_cycles(&space.device(), 50);
2146	2162	}
2147	2163
2148		return state->m_wram[(0x113f08/2)+offset];
	2164	return m_wram[(0x113f08/2)+offset];
2149	2165	}
2150	2166
2151		static READ16_HANDLER( puzlbang_speedup_r )
	2167	READ16_MEMBER(vamphalf_state::puzlbang_speedup_r)
2152	2168	{
2153		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2154		if(cpu_get_pc(&space->device()) == 0xae6d2 )
	2169	if(cpu_get_pc(&space.device()) == 0xae6d2 )
2155	2170	{
2156		if(irq_active(space))
2157		device_spin_until_interrupt(&space->device());
	2171	if(irq_active(&space))
	2172	device_spin_until_interrupt(&space.device());
2158	2173	else
2159		device_eat_cycles(&space->device(), 50);
	2174	device_eat_cycles(&space.device(), 50);
2160	2175	}
2161	2176
2162		return state->m_wram[(0x113ecc/2)+offset];
	2177	return m_wram[(0x113ecc/2)+offset];
2163	2178	}
2164	2179
2165		static READ32_HANDLER( wyvernwg_speedup_r )
	2180	READ32_MEMBER(vamphalf_state::wyvernwg_speedup_r)
2166	2181	{
2167		int pc = cpu_get_pc(&space->device());
	2182	int pc = cpu_get_pc(&space.device());
2168	2183
2169		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2170	2184	if(pc == 0x10758)
2171	2185	{
2172		if(irq_active(space))
2173		device_spin_until_interrupt(&space->device());
	2186	if(irq_active(&space))
	2187	device_spin_until_interrupt(&space.device());
2174	2188	else
2175		device_eat_cycles(&space->device(), 50);
	2189	device_eat_cycles(&space.device(), 50);
2176	2190	}
2177	2191
2178		return state->m_wram32[0x00b56fc/4];
	2192	return m_wram32[0x00b56fc/4];
2179	2193	}
2180	2194
2181		static READ32_HANDLER( wyvernwga_speedup_r )
	2195	READ32_MEMBER(vamphalf_state::wyvernwga_speedup_r)
2182	2196	{
2183		int pc = cpu_get_pc(&space->device());
	2197	int pc = cpu_get_pc(&space.device());
2184	2198
2185		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2186	2199	if(pc == 0x10758)
2187	2200	{
2188		if(irq_active(space))
2189		device_spin_until_interrupt(&space->device());
	2201	if(irq_active(&space))
	2202	device_spin_until_interrupt(&space.device());
2190	2203	else
2191		device_eat_cycles(&space->device(), 50);
	2204	device_eat_cycles(&space.device(), 50);
2192	2205	}
2193	2206
2194		return state->m_wram32[0x00b74f8/4];
	2207	return m_wram32[0x00b74f8/4];
2195	2208	}
2196	2209
2197	2210
2198	2211
2199		static READ32_HANDLER( finalgdr_speedup_r )
	2212	READ32_MEMBER(vamphalf_state::finalgdr_speedup_r)
2200	2213	{
2201		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2202		if(cpu_get_pc(&space->device()) == 0x1c212)
	2214	if(cpu_get_pc(&space.device()) == 0x1c212)
2203	2215	{
2204		if(irq_active(space))
2205		device_spin_until_interrupt(&space->device());
	2216	if(irq_active(&space))
	2217	device_spin_until_interrupt(&space.device());
2206	2218	else
2207		device_eat_cycles(&space->device(), 50);
	2219	device_eat_cycles(&space.device(), 50);
2208	2220	}
2209	2221
2210		return state->m_wram32[0x005e874/4];
	2222	return m_wram32[0x005e874/4];
2211	2223	}
2212	2224
2213		static READ32_HANDLER( mrkicker_speedup_r )
	2225	READ32_MEMBER(vamphalf_state::mrkicker_speedup_r)
2214	2226	{
2215		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2216		UINT32 pc = cpu_get_pc(&space->device());
	2227	UINT32 pc = cpu_get_pc(&space.device());
2217	2228	if(pc == 0x469de || pc == 0x46a36)
2218	2229	{
2219		//      if(irq_active(space))
2220		//          device_spin_until_interrupt(&space->device());
	2230	//      if(irq_active(&space))
	2231	//          device_spin_until_interrupt(&space.device());
2221	2232	//      else
2222		device_eat_cycles(&space->device(), 50);
	2233	device_eat_cycles(&space.device(), 50);
2223	2234	}
2224	2235
2225		return state->m_wram32[0x00701a4/4];
	2236	return m_wram32[0x00701a4/4];
2226	2237	}
2227	2238
2228	2239
2229		static READ16_HANDLER( dquizgo2_speedup_r )
	2240	READ16_MEMBER(vamphalf_state::dquizgo2_speedup_r)
2230	2241	{
2231		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2232		if(cpu_get_pc(&space->device()) == 0xaa622)
	2242	if(cpu_get_pc(&space.device()) == 0xaa622)
2233	2243	{
2234		if(irq_active(space))
2235		device_spin_until_interrupt(&space->device());
	2244	if(irq_active(&space))
	2245	device_spin_until_interrupt(&space.device());
2236	2246	else
2237		device_eat_cycles(&space->device(), 50);
	2247	device_eat_cycles(&space.device(), 50);
2238	2248	}
2239	2249
2240		return state->m_wram[(0xcde70/2)+offset];
	2250	return m_wram[(0xcde70/2)+offset];
2241	2251	}
2242	2252
2243		static READ32_HANDLER( aoh_speedup_r )
	2253	READ32_MEMBER(vamphalf_state::aoh_speedup_r)
2244	2254	{
2245		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2246		if(cpu_get_pc(&space->device()) == 0xb994 )
	2255	if(cpu_get_pc(&space.device()) == 0xb994 )
2247	2256	{
2248		device_eat_cycles(&space->device(), 500);
	2257	device_eat_cycles(&space.device(), 500);
2249	2258	}
2250		else if (cpu_get_pc(&space->device()) == 0xba40 )
	2259	else if (cpu_get_pc(&space.device()) == 0xba40 )
2251	2260	{
2252		device_eat_cycles(&space->device(), 500);
	2261	device_eat_cycles(&space.device(), 500);
2253	2262	}
2254	2263
2255	2264
2256		return state->m_wram32[0x28a09c/4];
	2265	return m_wram32[0x28a09c/4];
2257	2266	}
2258	2267
2259		static READ16_HANDLER( jmpbreak_speedup_r )
	2268	READ16_MEMBER(vamphalf_state::jmpbreak_speedup_r)
2260	2269	{
2261		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2262		if(cpu_get_pc(&space->device()) == 0x983c)
	2270	if(cpu_get_pc(&space.device()) == 0x983c)
2263	2271	{
2264		if(irq_active(space))
2265		device_spin_until_interrupt(&space->device());
	2272	if(irq_active(&space))
	2273	device_spin_until_interrupt(&space.device());
2266	2274	else
2267		device_eat_cycles(&space->device(), 50);
	2275	device_eat_cycles(&space.device(), 50);
2268	2276	}
2269	2277
2270		return state->m_wram[(0x00906fc / 2)+offset];
	2278	return m_wram[(0x00906fc / 2)+offset];
2271	2279	}
2272	2280
2273		static READ16_HANDLER( mrdig_speedup_r )
	2281	READ16_MEMBER(vamphalf_state::mrdig_speedup_r)
2274	2282	{
2275		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2276		if(cpu_get_pc(&space->device()) == 0x1710)
	2283	if(cpu_get_pc(&space.device()) == 0x1710)
2277	2284	{
2278		if(irq_active(space))
2279		device_spin_until_interrupt(&space->device());
	2285	if(irq_active(&space))
	2286	device_spin_until_interrupt(&space.device());
2280	2287	else
2281		device_eat_cycles(&space->device(), 50);
	2288	device_eat_cycles(&space.device(), 50);
2282	2289	}
2283	2290
2284		return state->m_wram[(0x00a99c / 2)+offset];
	2291	return m_wram[(0x00a99c / 2)+offset];
2285	2292	}
2286	2293
2287		static READ16_HANDLER( dtfamily_speedup_r )
	2294	READ16_MEMBER(vamphalf_state::dtfamily_speedup_r)
2288	2295	{
2289		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2290	2296
2291		int pc = cpu_get_pc(&space->device());
	2297	int pc = cpu_get_pc(&space.device());
2292	2298
2293	2299	if (pc == 0x12fa6)
2294		device_spin_until_interrupt(&space->device());
	2300	device_spin_until_interrupt(&space.device());
2295	2301
2296		return state->m_wram[0xcc2a8 / 2];
	2302	return m_wram[0xcc2a8 / 2];
2297	2303
2298	2304	}
2299	2305
2300		static READ16_HANDLER( toyland_speedup_r )
	2306	READ16_MEMBER(vamphalf_state::toyland_speedup_r)
2301	2307	{
2302		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2303	2308
2304		if (cpu_get_pc(&space->device()) == 0x130c2)
2305		device_spin_until_interrupt(&space->device());
	2309	if (cpu_get_pc(&space.device()) == 0x130c2)
	2310	device_spin_until_interrupt(&space.device());
2306	2311
2307		return state->m_wram[0x780d8 / 2];
	2312	return m_wram[0x780d8 / 2];
2308	2313
2309	2314	}
2310	2315
2311		static READ16_HANDLER( boonggab_speedup_r )
	2316	READ16_MEMBER(vamphalf_state::boonggab_speedup_r)
2312	2317	{
2313		vamphalf_state *state = space->machine().driver_data<vamphalf_state>();
2314		if(cpu_get_pc(&space->device()) == 0x13198)
	2318	if(cpu_get_pc(&space.device()) == 0x13198)
2315	2319	{
2316		if(irq_active(space))
2317		device_spin_until_interrupt(&space->device());
	2320	if(irq_active(&space))
	2321	device_spin_until_interrupt(&space.device());
2318	2322	}
2319	2323
2320		return state->m_wram[(0xf1b7c / 2)+offset];
	2324	return m_wram[(0xf1b7c / 2)+offset];
2321	2325	}
2322	2326
2323	2327	static DRIVER_INIT( vamphalf )
2324	2328	{
2325	2329	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2326		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x0004a840, 0x0004a843, FUNC(vamphalf_speedup_r) );
	2330	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x0004a840, 0x0004a843, read16_delegate(FUNC(vamphalf_state::vamphalf_speedup_r), state));
2327	2331
2328	2332	state->m_palshift = 0;
2329	2333	state->m_flip_bit = 0x80;
r14845	r14846
2332	2336	static DRIVER_INIT( vamphafk )
2333	2337	{
2334	2338	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2335		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x0004a6d0, 0x0004a6d3, FUNC(vamphafk_speedup_r) );
	2339	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x0004a6d0, 0x0004a6d3, read16_delegate(FUNC(vamphalf_state::vamphafk_speedup_r), state));
2336	2340
2337	2341	state->m_palshift = 0;
2338	2342	state->m_flip_bit = 0x80;
r14845	r14846
2341	2345	static DRIVER_INIT( misncrft )
2342	2346	{
2343	2347	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2344		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00072eb4, 0x00072eb7, FUNC(misncrft_speedup_r) );
	2348	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x00072eb4, 0x00072eb7, read16_delegate(FUNC(vamphalf_state::misncrft_speedup_r), state));
2345	2349
2346	2350	state->m_palshift = 0;
2347	2351	state->m_flip_bit = 1;
r14845	r14846
2350	2354	static DRIVER_INIT( coolmini )
2351	2355	{
2352	2356	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2353		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x000d2e80, 0x000d2e83, FUNC(coolmini_speedup_r) );
	2357	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x000d2e80, 0x000d2e83, read16_delegate(FUNC(vamphalf_state::coolmini_speedup_r), state));
2354	2358
2355	2359	state->m_palshift = 0;
2356	2360	state->m_flip_bit = 1;
r14845	r14846
2359	2363	static DRIVER_INIT( suplup )
2360	2364	{
2361	2365	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2362		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x0011605c, 0x0011605f, FUNC(suplup_speedup_r) );
	2366	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x0011605c, 0x0011605f, read16_delegate(FUNC(vamphalf_state::suplup_speedup_r), state));
2363	2367
2364	2368	state->m_palshift = 8;
2365	2369	/* no flipscreen */
r14845	r14846
2368	2372	static DRIVER_INIT( luplup )
2369	2373	{
2370	2374	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2371		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00115e84, 0x00115e87, FUNC(luplup_speedup_r) );
	2375	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x00115e84, 0x00115e87, read16_delegate(FUNC(vamphalf_state::luplup_speedup_r), state));
2372	2376
2373	2377	state->m_palshift = 8;
2374	2378	/* no flipscreen */
r14845	r14846
2377	2381	static DRIVER_INIT( luplup29 )
2378	2382	{
2379	2383	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2380		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00113f08, 0x00113f0b, FUNC(luplup29_speedup_r) );
	2384	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x00113f08, 0x00113f0b, read16_delegate(FUNC(vamphalf_state::luplup29_speedup_r), state));
2381	2385
2382	2386	state->m_palshift = 8;
2383	2387	/* no flipscreen */
r14845	r14846
2386	2390	static DRIVER_INIT( puzlbang )
2387	2391	{
2388	2392	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2389		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00113ecc, 0x00113ecf, FUNC(puzlbang_speedup_r) );
	2393	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x00113ecc, 0x00113ecf, read16_delegate(FUNC(vamphalf_state::puzlbang_speedup_r), state));
2390	2394
2391	2395	state->m_palshift = 8;
2392	2396	/* no flipscreen */
r14845	r14846
2395	2399	static DRIVER_INIT( wyvernwg )
2396	2400	{
2397	2401	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2398		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00b56fc, 0x00b56ff, FUNC(wyvernwg_speedup_r) );
2399		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00b74f8, 0x00b74fb, FUNC(wyvernwga_speedup_r) );
	2402	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x00b56fc, 0x00b56ff, read32_delegate(FUNC(vamphalf_state::wyvernwg_speedup_r), state));
	2403	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x00b74f8, 0x00b74fb, read32_delegate(FUNC(vamphalf_state::wyvernwga_speedup_r), state));
2400	2404
2401	2405	state->m_palshift = 0;
2402	2406	state->m_flip_bit = 1;
r14845	r14846
2411	2415	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2412	2416	state->m_finalgdr_backupram_bank = 1;
2413	2417	state->m_finalgdr_backupram = auto_alloc_array(machine, UINT8, 0x80*0x100);
2414		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x005e874, 0x005e877, FUNC(finalgdr_speedup_r) );
	2418	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x005e874, 0x005e877, read32_delegate(FUNC(vamphalf_state::finalgdr_speedup_r), state));
2415	2419	machine.device<nvram_device>("nvram")->set_base(state->m_finalgdr_backupram, 0x80*0x100);
2416	2420
2417	2421	state->m_palshift = 0;
r14845	r14846
2428	2432	// backup ram isn't used
2429	2433	state->m_finalgdr_backupram_bank = 1;
2430	2434	state->m_finalgdr_backupram = auto_alloc_array(machine, UINT8, 0x80*0x100);
2431		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00701a4, 0x00701a7, FUNC(mrkicker_speedup_r) );
	2435	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x00701a4, 0x00701a7, read32_delegate(FUNC(vamphalf_state::mrkicker_speedup_r), state));
2432	2436	machine.device<nvram_device>("nvram")->set_base(state->m_finalgdr_backupram, 0x80*0x100);
2433	2437
2434	2438	state->m_palshift = 0;
r14845	r14846
2442	2446	static DRIVER_INIT( dquizgo2 )
2443	2447	{
2444	2448	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2445		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00cde70, 0x00cde73, FUNC(dquizgo2_speedup_r) );
	2449	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x00cde70, 0x00cde73, read16_delegate(FUNC(vamphalf_state::dquizgo2_speedup_r), state));
2446	2450
2447	2451	state->m_palshift = 0;
2448	2452	state->m_flip_bit = 1;
r14845	r14846
2451	2455	static DRIVER_INIT( dtfamily )
2452	2456	{
2453	2457	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2454		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xcc2a8, 0xcc2a9, FUNC(dtfamily_speedup_r) );
	2458	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0xcc2a8, 0xcc2a9, read16_delegate(FUNC(vamphalf_state::dtfamily_speedup_r), state));
2455	2459
2456	2460	state->m_palshift = 0;
2457	2461	state->m_flip_bit = 1;
r14845	r14846
2461	2465	static DRIVER_INIT( toyland )
2462	2466	{
2463	2467	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2464		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x780d8, 0x780d9, FUNC(toyland_speedup_r) );
	2468	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x780d8, 0x780d9, read16_delegate(FUNC(vamphalf_state::toyland_speedup_r), state));
2465	2469
2466	2470	state->m_palshift = 0;
2467	2471	state->m_flip_bit = 1;
r14845	r14846
2470	2474	static DRIVER_INIT( aoh )
2471	2475	{
2472	2476	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2473		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x028a09c, 0x028a09f, FUNC(aoh_speedup_r) );
	2477	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x028a09c, 0x028a09f, read32_delegate(FUNC(vamphalf_state::aoh_speedup_r), state));
2474	2478
2475	2479	state->m_palshift = 0;
2476	2480	/* no flipscreen */
r14845	r14846
2479	2483	static DRIVER_INIT( jmpbreak )
2480	2484	{
2481	2485	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2482		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00906fc, 0x00906ff, FUNC(jmpbreak_speedup_r) );
2483		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xe0000000, 0xe0000003, FUNC(jmpbreak_flipscreen_w) );
	2486	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x00906fc, 0x00906ff, read16_delegate(FUNC(vamphalf_state::jmpbreak_speedup_r), state));
	2487	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0xe0000000, 0xe0000003, write16_delegate(FUNC(vamphalf_state::jmpbreak_flipscreen_w), state));
2484	2488
2485	2489	state->m_palshift = 0;
2486	2490	}
r14845	r14846
2488	2492	static DRIVER_INIT( mrdig )
2489	2493	{
2490	2494	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2491		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x00a99c, 0x00a99f, FUNC(mrdig_speedup_r) );
2492		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xe0000000, 0xe0000003, FUNC(jmpbreak_flipscreen_w) );
	2495	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x00a99c, 0x00a99f, read16_delegate(FUNC(vamphalf_state::mrdig_speedup_r), state));
	2496	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0xe0000000, 0xe0000003, write16_delegate(FUNC(vamphalf_state::jmpbreak_flipscreen_w), state));
2493	2497
2494	2498	state->m_palshift = 0;
2495	2499	}
r14845	r14846
2498	2502	static DRIVER_INIT( boonggab )
2499	2503	{
2500	2504	vamphalf_state *state = machine.driver_data<vamphalf_state>();
2501		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x000f1b7c, 0x000f1b7f, FUNC(boonggab_speedup_r) );
	2505	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x000f1b7c, 0x000f1b7f, read16_delegate(FUNC(vamphalf_state::boonggab_speedup_r), state));
2502	2506
2503	2507	state->m_palshift = 0;
2504	2508	state->m_has_extra_gfx = 1;

src/mame/drivers/mayumi.c

r14845	r14846
30	30	/* misc */
31	31	int m_int_enable;
32	32	int m_input_sel;
	33	DECLARE_WRITE8_MEMBER(mayumi_videoram_w);
	34	DECLARE_WRITE8_MEMBER(bank_sel_w);
	35	DECLARE_WRITE8_MEMBER(input_sel_w);
	36	DECLARE_READ8_MEMBER(key_matrix_r);
33	37	};
34	38
35	39
r14845	r14846
54	58	state->m_tilemap = tilemap_create(machine, get_tile_info, tilemap_scan_rows, 8, 8, 64, 32);
55	59	}
56	60
57		static WRITE8_HANDLER( mayumi_videoram_w )
	61	WRITE8_MEMBER(mayumi_state::mayumi_videoram_w)
58	62	{
59		mayumi_state *state = space->machine().driver_data<mayumi_state>();
60		state->m_videoram[offset] = data;
61		state->m_tilemap->mark_tile_dirty(offset & 0x7ff);
	63	m_videoram[offset] = data;
	64	m_tilemap->mark_tile_dirty(offset & 0x7ff);
62	65	}
63	66
64	67	static SCREEN_UPDATE_IND16( mayumi )
r14845	r14846
88	91	*
89	92	*************************************/
90	93
91		static WRITE8_HANDLER( bank_sel_w )
	94	WRITE8_MEMBER(mayumi_state::bank_sel_w)
92	95	{
93		mayumi_state *state = space->machine().driver_data<mayumi_state>();
94	96	int bank = BIT(data, 7) | (BIT(data, 6) << 1);
95	97
96		memory_set_bank(space->machine(), "bank1", bank);
	98	memory_set_bank(machine(), "bank1", bank);
97	99
98		state->m_int_enable = data & 1;
	100	m_int_enable = data & 1;
99	101
100		flip_screen_set(space->machine(), data & 2);
	102	flip_screen_set(machine(), data & 2);
101	103	}
102	104
103		static WRITE8_HANDLER( input_sel_w )
	105	WRITE8_MEMBER(mayumi_state::input_sel_w)
104	106	{
105		mayumi_state *state = space->machine().driver_data<mayumi_state>();
106		state->m_input_sel = data;
	107	m_input_sel = data;
107	108	}
108	109
109		static READ8_HANDLER( key_matrix_r )
	110	READ8_MEMBER(mayumi_state::key_matrix_r)
110	111	{
111		mayumi_state *state = space->machine().driver_data<mayumi_state>();
112	112	int p, i, ret;
113	113	static const char *const keynames[2][5] =
114	114	{
r14845	r14846
118	118
119	119	ret = 0xff;
120	120
121		p = ~state->m_input_sel & 0x1f;
	121	p = ~m_input_sel & 0x1f;
122	122
123	123	for (i = 0; i < 5; i++)
124	124	{
125	125	if (BIT(p, i))
126		ret &= input_port_read(space->machine(), keynames[offset][i]);
	126	ret &= input_port_read(machine(), keynames[offset][i]);
127	127	}
128	128
129	129	return ret;
r14845	r14846
139	139	AM_RANGE(0x0000, 0x7fff) AM_ROM
140	140	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
141	141	AM_RANGE(0xc000, 0xdfff) AM_RAM AM_SHARE("nvram")
142		AM_RANGE(0xe000, 0xf7ff) AM_RAM_WRITE_LEGACY(mayumi_videoram_w) AM_BASE(m_videoram)
	142	AM_RANGE(0xe000, 0xf7ff) AM_RAM_WRITE(mayumi_videoram_w) AM_BASE(m_videoram)
143	143	ADDRESS_MAP_END
144	144
145	145
146	146	static ADDRESS_MAP_START( mayumi_io_map, AS_IO, 8, mayumi_state )
147	147	ADDRESS_MAP_GLOBAL_MASK(0xff)
148		AM_RANGE(0x30, 0x30) AM_READ_PORT("IN0") AM_WRITE_LEGACY(bank_sel_w)
149		AM_RANGE(0xc0, 0xc0) AM_WRITE_LEGACY(input_sel_w)
150		AM_RANGE(0xc1, 0xc2) AM_READ_LEGACY(key_matrix_r)   // 0xc0-c3 8255ppi
	148	AM_RANGE(0x30, 0x30) AM_READ_PORT("IN0") AM_WRITE(bank_sel_w)
	149	AM_RANGE(0xc0, 0xc0) AM_WRITE(input_sel_w)
	150	AM_RANGE(0xc1, 0xc2) AM_READ(key_matrix_r)   // 0xc0-c3 8255ppi
151	151	AM_RANGE(0xc3, 0xc3) AM_WRITENOP      // 0xc0-c3 8255ppi
152	152	AM_RANGE(0xd0, 0xd1) AM_DEVREADWRITE_LEGACY("ymsnd", ym2203_r, ym2203_w)
153	153	ADDRESS_MAP_END

src/mame/drivers/vegaeo.c

r14845	r14846
26	26
27	27	UINT32 *m_vega_vram;
28	28	UINT8 m_vega_vbuffer;
	29	DECLARE_WRITE32_MEMBER(vega_vram_w);
	30	DECLARE_READ32_MEMBER(vega_vram_r);
	31	DECLARE_WRITE32_MEMBER(vega_palette_w);
	32	DECLARE_WRITE32_MEMBER(vega_misc_w);
	33	DECLARE_READ32_MEMBER(vegaeo_custom_read);
29	34	};
30	35
31	36
32	37
33	38
34		static WRITE32_HANDLER( vega_vram_w )
	39	WRITE32_MEMBER(vegaeo_state::vega_vram_w)
35	40	{
36		vegaeo_state *state = space->machine().driver_data<vegaeo_state>();
37	41	switch(mem_mask)
38	42	{
39	43	case 0xffffffff:
r14845	r14846
59	63	return;
60	64	}
61	65
62		COMBINE_DATA(&state->m_vega_vram[offset + state->m_vega_vbuffer * (0x14000/4)]);
	66	COMBINE_DATA(&m_vega_vram[offset + m_vega_vbuffer * (0x14000/4)]);
63	67	}
64	68
65		static READ32_HANDLER( vega_vram_r )
	69	READ32_MEMBER(vegaeo_state::vega_vram_r)
66	70	{
67		vegaeo_state *state = space->machine().driver_data<vegaeo_state>();
68		return state->m_vega_vram[offset + (0x14000/4) * state->m_vega_vbuffer];
	71	return m_vega_vram[offset + (0x14000/4) * m_vega_vbuffer];
69	72	}
70	73
71		static WRITE32_HANDLER( vega_palette_w )
	74	WRITE32_MEMBER(vegaeo_state::vega_palette_w)
72	75	{
73	76	UINT16 paldata;
74	77
75		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
	78	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
76	79
77		paldata = space->machine().generic.paletteram.u32[offset] & 0x7fff;
78		palette_set_color_rgb(space->machine(), offset, pal5bit(paldata >> 10), pal5bit(paldata >> 5), pal5bit(paldata >> 0));
	80	paldata = machine().generic.paletteram.u32[offset] & 0x7fff;
	81	palette_set_color_rgb(machine(), offset, pal5bit(paldata >> 10), pal5bit(paldata >> 5), pal5bit(paldata >> 0));
79	82	}
80	83
81		static WRITE32_HANDLER( vega_misc_w )
	84	WRITE32_MEMBER(vegaeo_state::vega_misc_w)
82	85	{
83		vegaeo_state *state = space->machine().driver_data<vegaeo_state>();
84	86	// other bits ???
85	87
86		state->m_vega_vbuffer = data & 1;
	88	m_vega_vbuffer = data & 1;
87	89	}
88	90
89	91
90		static READ32_HANDLER( vegaeo_custom_read )
	92	READ32_MEMBER(vegaeo_state::vegaeo_custom_read)
91	93	{
92		eolith_speedup_read(space);
93		return input_port_read(space->machine(), "SYSTEM");
	94	eolith_speedup_read(&space);
	95	return input_port_read(machine(), "SYSTEM");
94	96	}
95	97
96	98	static ADDRESS_MAP_START( vega_map, AS_PROGRAM, 32, vegaeo_state )
97	99	AM_RANGE(0x00000000, 0x001fffff) AM_RAM
98		AM_RANGE(0x80000000, 0x80013fff) AM_READWRITE_LEGACY(vega_vram_r, vega_vram_w)
	100	AM_RANGE(0x80000000, 0x80013fff) AM_READWRITE(vega_vram_r, vega_vram_w)
99	101	AM_RANGE(0xfc000000, 0xfc0000ff) AM_DEVREADWRITE8_LEGACY("at28c16", at28c16_r, at28c16_w, 0x000000ff)
100		AM_RANGE(0xfc200000, 0xfc2003ff) AM_RAM_WRITE_LEGACY(vega_palette_w) AM_BASE_GENERIC(paletteram)
	102	AM_RANGE(0xfc200000, 0xfc2003ff) AM_RAM_WRITE(vega_palette_w) AM_BASE_GENERIC(paletteram)
101	103	AM_RANGE(0xfc400000, 0xfc40005b) AM_WRITENOP // crt registers ?
102	104	AM_RANGE(0xfc600000, 0xfc600003) AM_WRITENOP // soundlatch
103		AM_RANGE(0xfca00000, 0xfca00003) AM_WRITE_LEGACY(vega_misc_w)
104		AM_RANGE(0xfcc00000, 0xfcc00003) AM_READ_LEGACY(vegaeo_custom_read)
	105	AM_RANGE(0xfca00000, 0xfca00003) AM_WRITE(vega_misc_w)
	106	AM_RANGE(0xfcc00000, 0xfcc00003) AM_READ(vegaeo_custom_read)
105	107	AM_RANGE(0xfce00000, 0xfce00003) AM_READ_PORT("P1_P2")
106	108	AM_RANGE(0xfd000000, 0xfeffffff) AM_ROM AM_REGION("user1", 0)
107	109	AM_RANGE(0xfff80000, 0xffffffff) AM_ROM AM_REGION("maincpu", 0)

src/mame/drivers/bnstars.c

r14845	r14846
120	120	int m_ms32_reverse_sprite_order;
121	121	int m_flipscreen;
122	122	UINT16 m_irqreq;
	123	DECLARE_WRITE32_MEMBER(ms32_tx0_ram_w);
	124	DECLARE_WRITE32_MEMBER(ms32_tx1_ram_w);
	125	DECLARE_WRITE32_MEMBER(ms32_bg0_ram_w);
	126	DECLARE_WRITE32_MEMBER(ms32_bg1_ram_w);
	127	DECLARE_WRITE32_MEMBER(ms32_roz0_ram_w);
	128	DECLARE_WRITE32_MEMBER(ms32_roz1_ram_w);
	129	DECLARE_WRITE32_MEMBER(ms32_pal0_ram_w);
	130	DECLARE_WRITE32_MEMBER(ms32_pal1_ram_w);
	131	DECLARE_WRITE32_MEMBER(ms32_spramx_w);
	132	DECLARE_READ32_MEMBER(bnstars1_r);
	133	DECLARE_READ32_MEMBER(bnstars2_r);
	134	DECLARE_READ32_MEMBER(bnstars3_r);
	135	DECLARE_WRITE32_MEMBER(bnstars1_mahjong_select_w);
123	136	};
124	137
125	138
r14845	r14846
146	159	SET_TILE_INFO(7,tileno,colour,0);
147	160	}
148	161
149		static WRITE32_HANDLER( ms32_tx0_ram_w )
	162	WRITE32_MEMBER(bnstars_state::ms32_tx0_ram_w)
150	163	{
151		bnstars_state *state = space->machine().driver_data<bnstars_state>();
152		COMBINE_DATA(&state->m_ms32_tx0_ram[offset]);
153		state->m_ms32_tx_tilemap[0]->mark_tile_dirty(offset/2);
	164	COMBINE_DATA(&m_ms32_tx0_ram[offset]);
	165	m_ms32_tx_tilemap[0]->mark_tile_dirty(offset/2);
154	166	}
155	167
156		static WRITE32_HANDLER( ms32_tx1_ram_w )
	168	WRITE32_MEMBER(bnstars_state::ms32_tx1_ram_w)
157	169	{
158		bnstars_state *state = space->machine().driver_data<bnstars_state>();
159		COMBINE_DATA(&state->m_ms32_tx1_ram[offset]);
160		state->m_ms32_tx_tilemap[1]->mark_tile_dirty(offset/2);
	170	COMBINE_DATA(&m_ms32_tx1_ram[offset]);
	171	m_ms32_tx_tilemap[1]->mark_tile_dirty(offset/2);
161	172	}
162	173
163	174	/* BG Layers */
r14845	r14846
184	195	SET_TILE_INFO(6,tileno,colour,0);
185	196	}
186	197
187		static WRITE32_HANDLER( ms32_bg0_ram_w )
	198	WRITE32_MEMBER(bnstars_state::ms32_bg0_ram_w)
188	199	{
189		bnstars_state *state = space->machine().driver_data<bnstars_state>();
190		COMBINE_DATA(&state->m_ms32_bg0_ram[offset]);
191		state->m_ms32_bg_tilemap[0]->mark_tile_dirty(offset/2);
	200	COMBINE_DATA(&m_ms32_bg0_ram[offset]);
	201	m_ms32_bg_tilemap[0]->mark_tile_dirty(offset/2);
192	202	}
193	203
194		static WRITE32_HANDLER( ms32_bg1_ram_w )
	204	WRITE32_MEMBER(bnstars_state::ms32_bg1_ram_w)
195	205	{
196		bnstars_state *state = space->machine().driver_data<bnstars_state>();
197		COMBINE_DATA(&state->m_ms32_bg1_ram[offset]);
198		state->m_ms32_bg_tilemap[1]->mark_tile_dirty(offset/2);
	206	COMBINE_DATA(&m_ms32_bg1_ram[offset]);
	207	m_ms32_bg_tilemap[1]->mark_tile_dirty(offset/2);
199	208	}
200	209
201	210	/* ROZ Layers */
r14845	r14846
308	317	SET_TILE_INFO(5,tileno,colour,0);
309	318	}
310	319
311		static WRITE32_HANDLER( ms32_roz0_ram_w )
	320	WRITE32_MEMBER(bnstars_state::ms32_roz0_ram_w)
312	321	{
313		bnstars_state *state = space->machine().driver_data<bnstars_state>();
314		COMBINE_DATA(&state->m_ms32_roz0_ram[offset]);
315		state->m_ms32_roz_tilemap[0]->mark_tile_dirty(offset/2);
	322	COMBINE_DATA(&m_ms32_roz0_ram[offset]);
	323	m_ms32_roz_tilemap[0]->mark_tile_dirty(offset/2);
316	324	}
317	325
318		static WRITE32_HANDLER( ms32_roz1_ram_w )
	326	WRITE32_MEMBER(bnstars_state::ms32_roz1_ram_w)
319	327	{
320		bnstars_state *state = space->machine().driver_data<bnstars_state>();
321		COMBINE_DATA(&state->m_ms32_roz1_ram[offset]);
322		state->m_ms32_roz_tilemap[1]->mark_tile_dirty(offset/2);
	328	COMBINE_DATA(&m_ms32_roz1_ram[offset]);
	329	m_ms32_roz_tilemap[1]->mark_tile_dirty(offset/2);
323	330	}
324	331
325	332
r14845	r14846
335	342	palette_set_color(machine,color+screen*0x8000,MAKE_RGB(r,g,b));
336	343	}
337	344
338		static WRITE32_HANDLER( ms32_pal0_ram_w )
	345	WRITE32_MEMBER(bnstars_state::ms32_pal0_ram_w)
339	346	{
340		bnstars_state *state = space->machine().driver_data<bnstars_state>();
341		COMBINE_DATA(&state->m_ms32_pal_ram[0][offset]);
342		update_color(space->machine(), offset/2, 0);
	347	COMBINE_DATA(&m_ms32_pal_ram[0][offset]);
	348	update_color(machine(), offset/2, 0);
343	349	}
344	350
345		static WRITE32_HANDLER( ms32_pal1_ram_w )
	351	WRITE32_MEMBER(bnstars_state::ms32_pal1_ram_w)
346	352	{
347		bnstars_state *state = space->machine().driver_data<bnstars_state>();
348		COMBINE_DATA(&state->m_ms32_pal_ram[1][offset]);
349		update_color(space->machine(), offset/2, 1);
	353	COMBINE_DATA(&m_ms32_pal_ram[1][offset]);
	354	update_color(machine(), offset/2, 1);
350	355	}
351	356
352	357
r14845	r14846
479	484
480	485
481	486
482		static WRITE32_HANDLER( ms32_spramx_w )
	487	WRITE32_MEMBER(bnstars_state::ms32_spramx_w)
483	488	{
484		bnstars_state *state = space->machine().driver_data<bnstars_state>();
485		COMBINE_DATA(&state->m_ms32_spram[offset]);
	489	COMBINE_DATA(&m_ms32_spram[offset]);
486	490	}
487	491
488	492
r14845	r14846
1220	1224
1221	1225	GFXDECODE_END
1222	1226
1223		static READ32_HANDLER( bnstars1_r )
	1227	READ32_MEMBER(bnstars_state::bnstars1_r)
1224	1228	{
1225		bnstars_state *state = space->machine().driver_data<bnstars_state>();
1226		switch (state->m_bnstars1_mahjong_select & 0x2080)
	1229	switch (m_bnstars1_mahjong_select & 0x2080)
1227	1230	{
1228	1231	default:
1229		printf("unk bnstars1_r %08x\n",state->m_bnstars1_mahjong_select);
	1232	printf("unk bnstars1_r %08x\n",m_bnstars1_mahjong_select);
1230	1233	return 0xffffffff;
1231	1234
1232	1235	case 0x0000:
1233		return input_port_read(space->machine(), "IN0");
	1236	return input_port_read(machine(), "IN0");
1234	1237
1235	1238	case 0x0080:
1236		return input_port_read(space->machine(), "IN1");
	1239	return input_port_read(machine(), "IN1");
1237	1240
1238	1241	case 0x2000:
1239		return input_port_read(space->machine(), "IN2");
	1242	return input_port_read(machine(), "IN2");
1240	1243
1241	1244	case 0x2080:
1242		return input_port_read(space->machine(), "IN3");
	1245	return input_port_read(machine(), "IN3");
1243	1246
1244	1247	}
1245	1248	}
1246	1249
1247		static READ32_HANDLER( bnstars2_r )
	1250	READ32_MEMBER(bnstars_state::bnstars2_r)
1248	1251	{
1249		return input_port_read(space->machine(), "IN4");
	1252	return input_port_read(machine(), "IN4");
1250	1253	}
1251	1254
1252		static READ32_HANDLER( bnstars3_r )
	1255	READ32_MEMBER(bnstars_state::bnstars3_r)
1253	1256	{
1254		return input_port_read(space->machine(), "IN5");
	1257	return input_port_read(machine(), "IN5");
1255	1258	}
1256	1259
1257		static WRITE32_HANDLER( bnstars1_mahjong_select_w )
	1260	WRITE32_MEMBER(bnstars_state::bnstars1_mahjong_select_w)
1258	1261	{
1259		bnstars_state *state = space->machine().driver_data<bnstars_state>();
1260		state->m_bnstars1_mahjong_select = data;
1261		//  printf("%08x\n",state->m_bnstars1_mahjong_select);
	1262	m_bnstars1_mahjong_select = data;
	1263	//  printf("%08x\n",m_bnstars1_mahjong_select);
1262	1264	}
1263	1265
1264	1266	static ADDRESS_MAP_START( bnstars_map, AS_PROGRAM, 32, bnstars_state )
1265	1267	AM_RANGE(0x00000000, 0x001fffff) AM_ROM
1266	1268
1267		AM_RANGE(0xfcc00004, 0xfcc00007) AM_READ_LEGACY(bnstars1_r )
1268		AM_RANGE(0xfcc00008, 0xfcc0000b) AM_READ_LEGACY(bnstars2_r )
1269		AM_RANGE(0xfcc00010, 0xfcc00013) AM_READ_LEGACY(bnstars3_r )
	1269	AM_RANGE(0xfcc00004, 0xfcc00007) AM_READ(bnstars1_r )
	1270	AM_RANGE(0xfcc00008, 0xfcc0000b) AM_READ(bnstars2_r )
	1271	AM_RANGE(0xfcc00010, 0xfcc00013) AM_READ(bnstars3_r )
1270	1272
1271	1273	AM_RANGE(0xfce00034, 0xfce00037) AM_WRITENOP
1272	1274
r14845	r14846
1281	1283	AM_RANGE(0xfce00c00, 0xfce00c17) AM_WRITEONLY AM_BASE(m_ms32_tx1_scroll)
1282	1284	AM_RANGE(0xfce00c20, 0xfce00c37) AM_WRITEONLY AM_BASE(m_ms32_bg1_scroll)
1283	1285
1284		AM_RANGE(0xfce00e00, 0xfce00e03) AM_WRITE_LEGACY(bnstars1_mahjong_select_w) // ?
	1286	AM_RANGE(0xfce00e00, 0xfce00e03) AM_WRITE(bnstars1_mahjong_select_w) // ?
1285	1287
1286	1288	/* wrote together */
1287	1289	AM_RANGE(0xfd040000, 0xfd047fff) AM_RAM // priority ram
1288	1290	AM_RANGE(0xfd080000, 0xfd087fff) AM_RAM
1289		AM_RANGE(0xfd200000, 0xfd237fff) AM_RAM_WRITE_LEGACY(ms32_pal1_ram_w) AM_BASE(m_ms32_pal_ram[1])
1290		AM_RANGE(0xfd400000, 0xfd437fff) AM_RAM_WRITE_LEGACY(ms32_pal0_ram_w) AM_BASE(m_ms32_pal_ram[0])
1291		AM_RANGE(0xfe000000, 0xfe01ffff) AM_RAM_WRITE_LEGACY(ms32_roz1_ram_w) AM_BASE(m_ms32_roz1_ram)
1292		AM_RANGE(0xfe400000, 0xfe41ffff) AM_RAM_WRITE_LEGACY(ms32_roz0_ram_w) AM_BASE(m_ms32_roz0_ram)
1293		AM_RANGE(0xfe800000, 0xfe83ffff) AM_RAM_WRITE_LEGACY(ms32_spramx_w) AM_BASE(m_ms32_spram)
1294		AM_RANGE(0xfea00000, 0xfea07fff) AM_RAM_WRITE_LEGACY(ms32_tx1_ram_w) AM_BASE(m_ms32_tx1_ram)
1295		AM_RANGE(0xfea08000, 0xfea0ffff) AM_RAM_WRITE_LEGACY(ms32_bg1_ram_w) AM_BASE(m_ms32_bg1_ram)
1296		AM_RANGE(0xfec00000, 0xfec07fff) AM_RAM_WRITE_LEGACY(ms32_tx0_ram_w) AM_BASE(m_ms32_tx0_ram)
1297		AM_RANGE(0xfec08000, 0xfec0ffff) AM_RAM_WRITE_LEGACY(ms32_bg0_ram_w) AM_BASE(m_ms32_bg0_ram)
	1291	AM_RANGE(0xfd200000, 0xfd237fff) AM_RAM_WRITE(ms32_pal1_ram_w) AM_BASE(m_ms32_pal_ram[1])
	1292	AM_RANGE(0xfd400000, 0xfd437fff) AM_RAM_WRITE(ms32_pal0_ram_w) AM_BASE(m_ms32_pal_ram[0])
	1293	AM_RANGE(0xfe000000, 0xfe01ffff) AM_RAM_WRITE(ms32_roz1_ram_w) AM_BASE(m_ms32_roz1_ram)
	1294	AM_RANGE(0xfe400000, 0xfe41ffff) AM_RAM_WRITE(ms32_roz0_ram_w) AM_BASE(m_ms32_roz0_ram)
	1295	AM_RANGE(0xfe800000, 0xfe83ffff) AM_RAM_WRITE(ms32_spramx_w) AM_BASE(m_ms32_spram)
	1296	AM_RANGE(0xfea00000, 0xfea07fff) AM_RAM_WRITE(ms32_tx1_ram_w) AM_BASE(m_ms32_tx1_ram)
	1297	AM_RANGE(0xfea08000, 0xfea0ffff) AM_RAM_WRITE(ms32_bg1_ram_w) AM_BASE(m_ms32_bg1_ram)
	1298	AM_RANGE(0xfec00000, 0xfec07fff) AM_RAM_WRITE(ms32_tx0_ram_w) AM_BASE(m_ms32_tx0_ram)
	1299	AM_RANGE(0xfec08000, 0xfec0ffff) AM_RAM_WRITE(ms32_bg0_ram_w) AM_BASE(m_ms32_bg0_ram)
1298	1300
1299	1301	AM_RANGE(0xfee00000, 0xfee1ffff) AM_RAM
1300	1302	AM_RANGE(0xffe00000, 0xffffffff) AM_ROMBANK("bank1")

src/mame/drivers/dai3wksi.c

r14845	r14846
62	62	UINT8       m_port_last2;
63	63	int         m_enabled_sound;
64	64	int         m_sound3_counter;
	65	DECLARE_WRITE8_MEMBER(dai3wksi_audio_1_w);
	66	DECLARE_WRITE8_MEMBER(dai3wksi_audio_2_w);
	67	DECLARE_WRITE8_MEMBER(dai3wksi_audio_3_w);
65	68	};
66	69
67	70
r14845	r14846
194	197
195	198
196	199	#if (USE_SAMPLES)
197		static WRITE8_HANDLER( dai3wksi_audio_1_w )
	200	WRITE8_MEMBER(dai3wksi_state::dai3wksi_audio_1_w)
198	201	{
199		dai3wksi_state *state = space->machine().driver_data<dai3wksi_state>();
200		samples_device *samples = space->machine().device<samples_device>("samples");
201		UINT8 rising_bits = data & ~state->m_port_last1;
	202	samples_device *samples = machine().device<samples_device>("samples");
	203	UINT8 rising_bits = data & ~m_port_last1;
202	204
203		state->m_enabled_sound = data & 0x80;
	205	m_enabled_sound = data & 0x80;
204	206
205		if ((rising_bits & 0x20) && state->m_enabled_sound)
	207	if ((rising_bits & 0x20) && m_enabled_sound)
206	208	{
207	209	if (data & 0x04)
208	210	samples->start(CHANNEL_SOUND5, SAMPLE_SOUND5);
209	211	else
210	212	samples->start(CHANNEL_SOUND5, SAMPLE_SOUND5, true);
211	213	}
212		if (!(data & 0x20) && (state->m_port_last1 & 0x20))
	214	if (!(data & 0x20) && (m_port_last1 & 0x20))
213	215	samples->stop(CHANNEL_SOUND5);
214	216
215		state->m_port_last1 = data;
	217	m_port_last1 = data;
216	218	}
217	219
218		static WRITE8_HANDLER( dai3wksi_audio_2_w )
	220	WRITE8_MEMBER(dai3wksi_state::dai3wksi_audio_2_w)
219	221	{
220		dai3wksi_state *state = space->machine().driver_data<dai3wksi_state>();
221		samples_device *samples = space->machine().device<samples_device>("samples");
222		UINT8 rising_bits = data & ~state->m_port_last2;
	222	samples_device *samples = machine().device<samples_device>("samples");
	223	UINT8 rising_bits = data & ~m_port_last2;
223	224
224		state->m_dai3wksi_flipscreen = data & 0x10;
225		state->m_dai3wksi_redscreen  = ~data & 0x20;
226		state->m_dai3wksi_redterop   = data & 0x40;
	225	m_dai3wksi_flipscreen = data & 0x10;
	226	m_dai3wksi_redscreen  = ~data & 0x20;
	227	m_dai3wksi_redterop   = data & 0x40;
227	228
228		if (state->m_enabled_sound)
	229	if (m_enabled_sound)
229	230	{
230	231	if (rising_bits & 0x01) samples->start(CHANNEL_SOUND1, SAMPLE_SOUND1);
231	232	if (rising_bits & 0x02) samples->start(CHANNEL_SOUND2, SAMPLE_SOUND2);
232	233	if (rising_bits & 0x08) samples->start(CHANNEL_SOUND4, SAMPLE_SOUND4);
233	234	if (rising_bits & 0x04)
234	235	{
235		if (!state->m_sound3_counter)
	236	if (!m_sound3_counter)
236	237	samples->start(CHANNEL_SOUND3, SAMPLE_SOUND3_1);
237	238	else
238	239	samples->start(CHANNEL_SOUND3, SAMPLE_SOUND3_2);
239	240
240		state->m_sound3_counter ^= 1;
	241	m_sound3_counter ^= 1;
241	242	}
242	243	}
243	244
244		state->m_port_last2 = data;
	245	m_port_last2 = data;
245	246	}
246	247
247		static WRITE8_HANDLER( dai3wksi_audio_3_w )
	248	WRITE8_MEMBER(dai3wksi_state::dai3wksi_audio_3_w)
248	249	{
249		dai3wksi_state *state = space->machine().driver_data<dai3wksi_state>();
250		samples_device *samples = space->machine().device<samples_device>("samples");
	250	samples_device *samples = machine().device<samples_device>("samples");
251	251
252		if (state->m_enabled_sound)
	252	if (m_enabled_sound)
253	253	{
254	254	if (data & 0x40)
255	255	samples->start(CHANNEL_SOUND6, SAMPLE_SOUND6_1);
r14845	r14846
282	282
283	283	#else
284	284
285		static WRITE8_HANDLER( dai3wksi_audio_1_w )
	285	WRITE8_MEMBER(dai3wksi_state::dai3wksi_audio_1_w)
286	286	{
287		device_t *ic79 = space->machine().device("ic79");
	287	device_t *ic79 = machine().device("ic79");
288	288
289		space->machine().sound().system_enable(data & 0x80);
	289	machine().sound().system_enable(data & 0x80);
290	290
291	291	sn76477_enable_w(ic79, (~data >> 5) & 0x01);      /* invader movement enable */
292	292	sn76477_envelope_1_w(ic79, (~data >> 2) & 0x01);   /* invader movement envelope control*/
293	293	}
294	294
295		static WRITE8_HANDLER( dai3wksi_audio_2_w )
	295	WRITE8_MEMBER(dai3wksi_state::dai3wksi_audio_2_w)
296	296	{
297	297
298		dai3wksi_state *state = space->machine().driver_data<dai3wksi_state>();
299		device_t *ic77 = space->machine().device("ic77");
300		device_t *ic78 = space->machine().device("ic78");
301		device_t *ic80 = space->machine().device("ic80");
	298	device_t *ic77 = machine().device("ic77");
	299	device_t *ic78 = machine().device("ic78");
	300	device_t *ic80 = machine().device("ic80");
302	301
303		state->m_dai3wksi_flipscreen =  data & 0x10;
304		state->m_dai3wksi_redscreen  = ~data & 0x20;
305		state->m_dai3wksi_redterop   =  data & 0x40;
	302	m_dai3wksi_flipscreen =  data & 0x10;
	303	m_dai3wksi_redscreen  = ~data & 0x20;
	304	m_dai3wksi_redterop   =  data & 0x40;
306	305
307	306	sn76477_enable_w(ic77, (~data >> 0) & 0x01);   /* ship movement */
308	307	sn76477_enable_w(ic78, (~data >> 1) & 0x01);   /* danger text */
r14845	r14846
310	309	sn76477_enable_w(ic80, (~data >> 3) & 0x01);   /* planet explosion */
311	310	}
312	311
313		static WRITE8_HANDLER( dai3wksi_audio_3_w )
	312	WRITE8_MEMBER(dai3wksi_state::dai3wksi_audio_3_w)
314	313	{
315		device_t *ic81 = space->machine().device("ic81");
	314	device_t *ic81 = machine().device("ic81");
316	315
317	316	sn76477_enable_w(ic81, (~data >> 2) & 0x01);   /* player shoot enable */
318	317	sn76477_vco_w(ic81, (~data >> 3) & 0x01);      /* player shoot vco control */
r14845	r14846
507	506	AM_RANGE(0x2000, 0x23ff) AM_RAM
508	507	AM_RANGE(0x2400, 0x24ff) AM_MIRROR(0x100) AM_READ_PORT("IN0")
509	508	AM_RANGE(0x2800, 0x28ff) AM_MIRROR(0x100) AM_READ_PORT("IN1")
510		AM_RANGE(0x3000, 0x3000) AM_WRITE_LEGACY(dai3wksi_audio_1_w)
511		AM_RANGE(0x3400, 0x3400) AM_WRITE_LEGACY(dai3wksi_audio_2_w)
512		AM_RANGE(0x3800, 0x3800) AM_WRITE_LEGACY(dai3wksi_audio_3_w)
	509	AM_RANGE(0x3000, 0x3000) AM_WRITE(dai3wksi_audio_1_w)
	510	AM_RANGE(0x3400, 0x3400) AM_WRITE(dai3wksi_audio_2_w)
	511	AM_RANGE(0x3800, 0x3800) AM_WRITE(dai3wksi_audio_3_w)
513	512	AM_RANGE(0x8000, 0xbfff) AM_RAM AM_BASE_SIZE(m_dai3wksi_videoram, m_dai3wksi_videoram_size)
514	513	ADDRESS_MAP_END
515	514

src/mame/drivers/diverboy.c

r14845	r14846
66	66
67	67	/* devices */
68	68	device_t *m_audiocpu;
	69	DECLARE_WRITE16_MEMBER(soundcmd_w);
69	70	};
70	71
71	72
r14845	r14846
117	118	}
118	119
119	120
120		static WRITE16_HANDLER( soundcmd_w )
	121	WRITE16_MEMBER(diverboy_state::soundcmd_w)
121	122	{
122		diverboy_state *state = space->machine().driver_data<diverboy_state>();
123	123
124	124	if (ACCESSING_BITS_0_7)
125	125	{
126	126	soundlatch_w(space, 0, data & 0xff);
127		device_set_input_line(state->m_audiocpu, 0, HOLD_LINE);
	127	device_set_input_line(m_audiocpu, 0, HOLD_LINE);
128	128	}
129	129	}
130	130
r14845	r14846
143	143	AM_RANGE(0x000000, 0x03ffff) AM_ROM
144	144	AM_RANGE(0x040000, 0x04ffff) AM_RAM
145	145	AM_RANGE(0x080000, 0x083fff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
146		AM_RANGE(0x100000, 0x100001) AM_WRITE_LEGACY(soundcmd_w)
	146	AM_RANGE(0x100000, 0x100001) AM_WRITE(soundcmd_w)
147	147	AM_RANGE(0x140000, 0x1407ff) AM_WRITE_LEGACY(paletteram16_xxxxBBBBGGGGRRRR_word_w) AM_BASE_GENERIC(paletteram)
148	148	AM_RANGE(0x180000, 0x180001) AM_READ_PORT("P1_P2")
149	149	AM_RANGE(0x180002, 0x180003) AM_READ_PORT("DSW")

src/mame/drivers/firefox.c

r14845	r14846
57	57	UINT8 m_main_to_sound_flag;
58	58	int m_sprite_bank;
59	59	UINT8 *m_spriteram;
	60	DECLARE_READ8_MEMBER(firefox_disc_status_r);
	61	DECLARE_READ8_MEMBER(firefox_disc_data_r);
	62	DECLARE_WRITE8_MEMBER(firefox_disc_read_w);
	63	DECLARE_WRITE8_MEMBER(firefox_disc_lock_w);
	64	DECLARE_WRITE8_MEMBER(audio_enable_w);
	65	DECLARE_WRITE8_MEMBER(firefox_disc_reset_w);
	66	DECLARE_WRITE8_MEMBER(firefox_disc_write_w);
	67	DECLARE_WRITE8_MEMBER(firefox_disc_data_w);
	68	DECLARE_WRITE8_MEMBER(tileram_w);
	69	DECLARE_WRITE8_MEMBER(tile_palette_w);
	70	DECLARE_WRITE8_MEMBER(sprite_palette_w);
	71	DECLARE_WRITE8_MEMBER(firefox_objram_bank_w);
	72	DECLARE_READ8_MEMBER(sound_to_main_r);
	73	DECLARE_WRITE8_MEMBER(main_to_sound_w);
	74	DECLARE_WRITE8_MEMBER(sound_reset_w);
	75	DECLARE_READ8_MEMBER(main_to_sound_r);
	76	DECLARE_WRITE8_MEMBER(sound_to_main_w);
	77	DECLARE_READ8_MEMBER(adc_r);
	78	DECLARE_WRITE8_MEMBER(adc_select_w);
	79	DECLARE_WRITE8_MEMBER(nvram_w);
	80	DECLARE_READ8_MEMBER(nvram_r);
	81	DECLARE_WRITE8_MEMBER(novram_recall_w);
	82	DECLARE_WRITE8_MEMBER(novram_store_w);
	83	DECLARE_WRITE8_MEMBER(rom_bank_w);
	84	DECLARE_WRITE8_MEMBER(main_irq_clear_w);
	85	DECLARE_WRITE8_MEMBER(main_firq_clear_w);
	86	DECLARE_WRITE8_MEMBER(self_reset_w);
	87	DECLARE_WRITE8_MEMBER(led_w);
	88	DECLARE_WRITE8_MEMBER(firefox_coin_counter_w);
60	89	};
61	90
62	91
r14845	r14846
88	117	40 = DISKFULL - Active low
89	118	80 = DISKDAV - Active low data available
90	119	*/
91		static READ8_HANDLER( firefox_disc_status_r )
	120	READ8_MEMBER(firefox_state::firefox_disc_status_r)
92	121	{
93		firefox_state *state = space->machine().driver_data<firefox_state>();
94	122	UINT8 result = 0xff;
95	123
96	124	result ^= 0x20;
97		if (!state->m_laserdisc->ready_r())
	125	if (!m_laserdisc->ready_r())
98	126	result ^= 0x40;
99		if (state->m_laserdisc->data_available_r())
	127	if (m_laserdisc->data_available_r())
100	128	result ^= 0x80;
101	129
102	130	return result;
r14845	r14846
104	132
105	133	/* 4105 - DREAD */
106	134	/* this reset RDDSK (&DSKRD) */
107		static READ8_HANDLER( firefox_disc_data_r )
	135	READ8_MEMBER(firefox_state::firefox_disc_data_r)
108	136	{
109		firefox_state *state = space->machine().driver_data<firefox_state>();
110		return state->m_n_disc_read_data;
	137	return m_n_disc_read_data;
111	138	}
112	139
113	140	/* DISK READ ENABLE */
114	141	/* 4218 - DSKREAD, set RDDSK */
115		static WRITE8_HANDLER( firefox_disc_read_w )
	142	WRITE8_MEMBER(firefox_state::firefox_disc_read_w)
116	143	{
117		firefox_state *state = space->machine().driver_data<firefox_state>();
118		state->m_n_disc_read_data = state->m_laserdisc->data_r();
	144	m_n_disc_read_data = m_laserdisc->data_r();
119	145	}
120	146
121		static WRITE8_HANDLER( firefox_disc_lock_w )
	147	WRITE8_MEMBER(firefox_state::firefox_disc_lock_w)
122	148	{
123		firefox_state *state = space->machine().driver_data<firefox_state>();
124		state->m_n_disc_lock = data & 0x80;
	149	m_n_disc_lock = data & 0x80;
125	150	}
126	151
127		static WRITE8_HANDLER( audio_enable_w )
	152	WRITE8_MEMBER(firefox_state::audio_enable_w)
128	153	{
129		firefox_state *state = space->machine().driver_data<firefox_state>();
130		state->m_laserdisc->set_output_gain(~offset & 1, (data & 0x80) ? 1.0 : 0.0);
	154	m_laserdisc->set_output_gain(~offset & 1, (data & 0x80) ? 1.0 : 0.0);
131	155	}
132	156
133		static WRITE8_HANDLER( firefox_disc_reset_w )
	157	WRITE8_MEMBER(firefox_state::firefox_disc_reset_w)
134	158	{
135		firefox_state *state = space->machine().driver_data<firefox_state>();
136		state->m_laserdisc->reset_w((data & 0x80) ? CLEAR_LINE : ASSERT_LINE);
	159	m_laserdisc->reset_w((data & 0x80) ? CLEAR_LINE : ASSERT_LINE);
137	160	}
138	161
139	162	/* active low on dbb7 */
140		static WRITE8_HANDLER( firefox_disc_write_w )
	163	WRITE8_MEMBER(firefox_state::firefox_disc_write_w)
141	164	{
142		firefox_state *state = space->machine().driver_data<firefox_state>();
143	165	if ( ( data & 0x80 ) == 0 )
144		state->m_laserdisc->data_w(state->m_n_disc_data);
	166	m_laserdisc->data_w(m_n_disc_data);
145	167	}
146	168
147	169	/* latch the data */
148		static WRITE8_HANDLER( firefox_disc_data_w )
	170	WRITE8_MEMBER(firefox_state::firefox_disc_data_w)
149	171	{
150		firefox_state *state = space->machine().driver_data<firefox_state>();
151		state->m_n_disc_data = data;
	172	m_n_disc_data = data;
152	173	}
153	174
154	175
r14845	r14846
167	188	}
168	189
169	190
170		static WRITE8_HANDLER( tileram_w )
	191	WRITE8_MEMBER(firefox_state::tileram_w)
171	192	{
172		firefox_state *state = space->machine().driver_data<firefox_state>();
173		state->m_tileram[offset] = data;
174		state->m_bgtiles->mark_tile_dirty(offset);
	193	m_tileram[offset] = data;
	194	m_bgtiles->mark_tile_dirty(offset);
175	195	}
176	196
177	197
r14845	r14846
237	257	palette_set_color( machine, start + index, MAKE_ARGB( a, r, g, b ) );
238	258	}
239	259
240		static WRITE8_HANDLER( tile_palette_w )
	260	WRITE8_MEMBER(firefox_state::tile_palette_w)
241	261	{
242		firefox_state *state = space->machine().driver_data<firefox_state>();
243		state->m_tile_palette[ offset ] = data;
244		set_rgba( space->machine(), 0, offset & 0xff, state->m_tile_palette );
	262	m_tile_palette[ offset ] = data;
	263	set_rgba( machine(), 0, offset & 0xff, m_tile_palette );
245	264	}
246	265
247		static WRITE8_HANDLER( sprite_palette_w )
	266	WRITE8_MEMBER(firefox_state::sprite_palette_w)
248	267	{
249		firefox_state *state = space->machine().driver_data<firefox_state>();
250		state->m_sprite_palette[ offset ] = data;
251		set_rgba( space->machine(), 256, offset & 0xff, state->m_sprite_palette );
	268	m_sprite_palette[ offset ] = data;
	269	set_rgba( machine(), 256, offset & 0xff, m_sprite_palette );
252	270	}
253	271
254		static WRITE8_HANDLER( firefox_objram_bank_w )
	272	WRITE8_MEMBER(firefox_state::firefox_objram_bank_w)
255	273	{
256		firefox_state *state = space->machine().driver_data<firefox_state>();
257		state->m_sprite_bank = data & 0x03;
	274	m_sprite_bank = data & 0x03;
258	275	}
259	276
260	277
r14845	r14846
277	294	return state->m_sound_to_main_flag;
278	295	}
279	296
280		static READ8_HANDLER( sound_to_main_r )
	297	READ8_MEMBER(firefox_state::sound_to_main_r)
281	298	{
282		firefox_state *state = space->machine().driver_data<firefox_state>();
283		state->m_sound_to_main_flag = 0;
	299	m_sound_to_main_flag = 0;
284	300	return soundlatch2_r(space, 0);
285	301	}
286	302
287		static WRITE8_HANDLER( main_to_sound_w )
	303	WRITE8_MEMBER(firefox_state::main_to_sound_w)
288	304	{
289		firefox_state *state = space->machine().driver_data<firefox_state>();
290		state->m_main_to_sound_flag = 1;
	305	m_main_to_sound_flag = 1;
291	306	soundlatch_w(space, 0, data);
292		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_NMI, PULSE_LINE);
	307	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_NMI, PULSE_LINE);
293	308	}
294	309
295		static WRITE8_HANDLER( sound_reset_w )
	310	WRITE8_MEMBER(firefox_state::sound_reset_w)
296	311	{
297		firefox_state *state = space->machine().driver_data<firefox_state>();
298		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_RESET, (data & 0x80) ? ASSERT_LINE : CLEAR_LINE);
	312	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_RESET, (data & 0x80) ? ASSERT_LINE : CLEAR_LINE);
299	313	if ((data & 0x80) != 0)
300		state->m_sound_to_main_flag = state->m_main_to_sound_flag = 0;
	314	m_sound_to_main_flag = m_main_to_sound_flag = 0;
301	315	}
302	316
303		static READ8_HANDLER( main_to_sound_r )
	317	READ8_MEMBER(firefox_state::main_to_sound_r)
304	318	{
305		firefox_state *state = space->machine().driver_data<firefox_state>();
306		state->m_main_to_sound_flag = 0;
	319	m_main_to_sound_flag = 0;
307	320	return soundlatch_r(space, 0);
308	321	}
309	322
310		static WRITE8_HANDLER( sound_to_main_w )
	323	WRITE8_MEMBER(firefox_state::sound_to_main_w)
311	324	{
312		firefox_state *state = space->machine().driver_data<firefox_state>();
313		state->m_sound_to_main_flag = 1;
	325	m_sound_to_main_flag = 1;
314	326	soundlatch2_w(space, 0, data);
315	327	}
316	328
r14845	r14846
361	373	*
362	374	*************************************/
363	375
364		static READ8_HANDLER( adc_r )
	376	READ8_MEMBER(firefox_state::adc_r)
365	377	{
366		firefox_state *state = space->machine().driver_data<firefox_state>();
367		if( state->m_control_num == 0 )
	378	if( m_control_num == 0 )
368	379	{
369		return input_port_read( space->machine(), "PITCH" );
	380	return input_port_read( machine(), "PITCH" );
370	381	}
371	382
372		return input_port_read( space->machine(), "YAW" );
	383	return input_port_read( machine(), "YAW" );
373	384	}
374	385
375		static WRITE8_HANDLER( adc_select_w )
	386	WRITE8_MEMBER(firefox_state::adc_select_w)
376	387	{
377		firefox_state *state = space->machine().driver_data<firefox_state>();
378		state->m_control_num = offset;
	388	m_control_num = offset;
379	389	}
380	390
381	391
r14845	r14846
386	396	*
387	397	*************************************/
388	398
389		static WRITE8_HANDLER( nvram_w )
	399	WRITE8_MEMBER(firefox_state::nvram_w)
390	400	{
391		firefox_state *state = space->machine().driver_data<firefox_state>();
392		state->m_nvram_1c->write(*space, offset, data >> 4);
393		state->m_nvram_1d->write(*space, offset, data & 0xf);
	401	m_nvram_1c->write(*&space, offset, data >> 4);
	402	m_nvram_1d->write(*&space, offset, data & 0xf);
394	403	}
395	404
396		static READ8_HANDLER( nvram_r )
	405	READ8_MEMBER(firefox_state::nvram_r)
397	406	{
398		firefox_state *state = space->machine().driver_data<firefox_state>();
399		return (state->m_nvram_1c->read(*space, offset) << 4) | (state->m_nvram_1d->read(*space, offset) & 0x0f);
	407	return (m_nvram_1c->read(*&space, offset) << 4) | (m_nvram_1d->read(*&space, offset) & 0x0f);
400	408	}
401	409
402		static WRITE8_HANDLER( novram_recall_w )
	410	WRITE8_MEMBER(firefox_state::novram_recall_w)
403	411	{
404		firefox_state *state = space->machine().driver_data<firefox_state>();
405		state->m_nvram_1c->recall(data & 0x80);
406		state->m_nvram_1d->recall(data & 0x80);
	412	m_nvram_1c->recall(data & 0x80);
	413	m_nvram_1d->recall(data & 0x80);
407	414	}
408	415
409		static WRITE8_HANDLER( novram_store_w )
	416	WRITE8_MEMBER(firefox_state::novram_store_w)
410	417	{
411		firefox_state *state = space->machine().driver_data<firefox_state>();
412		state->m_nvram_1c->store(data & 0x80);
413		state->m_nvram_1d->store(data & 0x80);
	418	m_nvram_1c->store(data & 0x80);
	419	m_nvram_1d->store(data & 0x80);
414	420	}
415	421
416	422
r14845	r14846
421	427	*
422	428	*************************************/
423	429
424		static WRITE8_HANDLER( rom_bank_w )
	430	WRITE8_MEMBER(firefox_state::rom_bank_w)
425	431	{
426		memory_set_bank(space->machine(), "bank1", data & 0x1f);
	432	memory_set_bank(machine(), "bank1", data & 0x1f);
427	433	}
428	434
429		static WRITE8_HANDLER( main_irq_clear_w )
	435	WRITE8_MEMBER(firefox_state::main_irq_clear_w)
430	436	{
431		cputag_set_input_line( space->machine(), "maincpu", M6809_IRQ_LINE, CLEAR_LINE );
	437	cputag_set_input_line( machine(), "maincpu", M6809_IRQ_LINE, CLEAR_LINE );
432	438	}
433	439
434		static WRITE8_HANDLER( main_firq_clear_w )
	440	WRITE8_MEMBER(firefox_state::main_firq_clear_w)
435	441	{
436		cputag_set_input_line( space->machine(), "maincpu", M6809_FIRQ_LINE, CLEAR_LINE );
	442	cputag_set_input_line( machine(), "maincpu", M6809_FIRQ_LINE, CLEAR_LINE );
437	443	}
438	444
439		static WRITE8_HANDLER( self_reset_w )
	445	WRITE8_MEMBER(firefox_state::self_reset_w)
440	446	{
441		cputag_set_input_line( space->machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE );
	447	cputag_set_input_line( machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE );
442	448	}
443	449
444	450
r14845	r14846
449	455	*
450	456	*************************************/
451	457
452		static WRITE8_HANDLER( led_w )
	458	WRITE8_MEMBER(firefox_state::led_w)
453	459	{
454		set_led_status( space->machine(), offset, ( data & 0x80 ) == 0 );
	460	set_led_status( machine(), offset, ( data & 0x80 ) == 0 );
455	461	}
456	462
457		static WRITE8_HANDLER( firefox_coin_counter_w )
	463	WRITE8_MEMBER(firefox_state::firefox_coin_counter_w)
458	464	{
459		coin_counter_w( space->machine(), offset, data & 0x80 );
	465	coin_counter_w( machine(), offset, data & 0x80 );
460	466	}
461	467
462	468
r14845	r14846
490	496
491	497	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, firefox_state )
492	498	AM_RANGE(0x0000, 0x0fff) AM_RAM
493		AM_RANGE(0x1000, 0x1fff) AM_RAM_WRITE_LEGACY(tileram_w) AM_BASE(m_tileram)
	499	AM_RANGE(0x1000, 0x1fff) AM_RAM_WRITE(tileram_w) AM_BASE(m_tileram)
494	500	AM_RANGE(0x2000, 0x27ff) AM_RAM AM_BASE(m_spriteram)
495		AM_RANGE(0x2800, 0x2aff) AM_RAM_WRITE_LEGACY(sprite_palette_w) AM_BASE(m_sprite_palette)
496		AM_RANGE(0x2b00, 0x2b00) AM_MIRROR(0x04ff) AM_WRITE_LEGACY(firefox_objram_bank_w)
497		AM_RANGE(0x2c00, 0x2eff) AM_RAM_WRITE_LEGACY(tile_palette_w) AM_BASE(m_tile_palette)
	501	AM_RANGE(0x2800, 0x2aff) AM_RAM_WRITE(sprite_palette_w) AM_BASE(m_sprite_palette)
	502	AM_RANGE(0x2b00, 0x2b00) AM_MIRROR(0x04ff) AM_WRITE(firefox_objram_bank_w)
	503	AM_RANGE(0x2c00, 0x2eff) AM_RAM_WRITE(tile_palette_w) AM_BASE(m_tile_palette)
498	504	AM_RANGE(0x3000, 0x3fff) AM_ROMBANK("bank1")
499		AM_RANGE(0x4000, 0x40ff) AM_READWRITE_LEGACY(nvram_r, nvram_w)                  /* NOVRAM */
	505	AM_RANGE(0x4000, 0x40ff) AM_READWRITE(nvram_r, nvram_w)                  /* NOVRAM */
500	506	AM_RANGE(0x4100, 0x4100) AM_MIRROR(0x00f8) AM_READ_PORT("rdin0")         /* RDIN0 */
501	507	AM_RANGE(0x4101, 0x4101) AM_MIRROR(0x00f8) AM_READ_PORT("rdin1")         /* RDIN1 */
502		AM_RANGE(0x4102, 0x4102) AM_MIRROR(0x00f8) AM_READ_LEGACY(firefox_disc_status_r)   /* RDIN2 */
	508	AM_RANGE(0x4102, 0x4102) AM_MIRROR(0x00f8) AM_READ(firefox_disc_status_r)   /* RDIN2 */
503	509	AM_RANGE(0x4103, 0x4103) AM_MIRROR(0x00f8) AM_READ_PORT("opt0")            /* OPT0 */
504	510	AM_RANGE(0x4104, 0x4104) AM_MIRROR(0x00f8) AM_READ_PORT("opt1")            /* OPT1 */
505		AM_RANGE(0x4105, 0x4105) AM_MIRROR(0x00f8) AM_READ_LEGACY(firefox_disc_data_r)      /* DREAD */
506		AM_RANGE(0x4106, 0x4106) AM_MIRROR(0x00f8) AM_READ_LEGACY(sound_to_main_r)         /* RDSOUND */
507		AM_RANGE(0x4107, 0x4107) AM_MIRROR(0x00f8) AM_READ_LEGACY(adc_r)               /* ADC */
508		AM_RANGE(0x4200, 0x4200) AM_MIRROR(0x0047) AM_WRITE_LEGACY(main_irq_clear_w)      /* RSTIRQ */
509		AM_RANGE(0x4208, 0x4208) AM_MIRROR(0x0047) AM_WRITE_LEGACY(main_firq_clear_w)      /* RSTFIRQ */
	511	AM_RANGE(0x4105, 0x4105) AM_MIRROR(0x00f8) AM_READ(firefox_disc_data_r)      /* DREAD */
	512	AM_RANGE(0x4106, 0x4106) AM_MIRROR(0x00f8) AM_READ(sound_to_main_r)         /* RDSOUND */
	513	AM_RANGE(0x4107, 0x4107) AM_MIRROR(0x00f8) AM_READ(adc_r)               /* ADC */
	514	AM_RANGE(0x4200, 0x4200) AM_MIRROR(0x0047) AM_WRITE(main_irq_clear_w)      /* RSTIRQ */
	515	AM_RANGE(0x4208, 0x4208) AM_MIRROR(0x0047) AM_WRITE(main_firq_clear_w)      /* RSTFIRQ */
510	516	AM_RANGE(0x4210, 0x4210) AM_MIRROR(0x0047) AM_WRITE_LEGACY(watchdog_reset_w)      /* WDCLK */
511		AM_RANGE(0x4218, 0x4218) AM_MIRROR(0x0047) AM_WRITE_LEGACY(firefox_disc_read_w)   /* DSKREAD */
512		AM_RANGE(0x4220, 0x4223) AM_MIRROR(0x0044) AM_WRITE_LEGACY(adc_select_w)         /* ADCSTART */
513		AM_RANGE(0x4230, 0x4230) AM_MIRROR(0x0047) AM_WRITE_LEGACY(self_reset_w)         /* AMUCK */
514		AM_RANGE(0x4280, 0x4280) AM_MIRROR(0x0040) AM_WRITE_LEGACY(novram_recall_w)      /* LATCH0 -> NVRECALL */
515		AM_RANGE(0x4281, 0x4281) AM_MIRROR(0x0040) AM_WRITE_LEGACY(sound_reset_w)         /* LATCH0 -> RSTSOUND */
516		AM_RANGE(0x4282, 0x4282) AM_MIRROR(0x0040) AM_WRITE_LEGACY(novram_store_w)         /* LATCH0 -> NVRSTORE */
517		AM_RANGE(0x4283, 0x4283) AM_MIRROR(0x0040) AM_WRITE_LEGACY(firefox_disc_lock_w)   /* LATCH0 -> LOCK */
518		AM_RANGE(0x4284, 0x4285) AM_MIRROR(0x0040) AM_WRITE_LEGACY(audio_enable_w)         /* LATCH0 -> SWDSKR, SWDSKL */
519		AM_RANGE(0x4286, 0x4286) AM_MIRROR(0x0040) AM_WRITE_LEGACY(firefox_disc_reset_w)   /* LATCH0 -> RSTDSK */
520		AM_RANGE(0x4287, 0x4287) AM_MIRROR(0x0040) AM_WRITE_LEGACY(firefox_disc_write_w)   /* LATCH0 -> WRDSK */
521		AM_RANGE(0x4288, 0x4289) AM_MIRROR(0x0040) AM_WRITE_LEGACY(firefox_coin_counter_w)   /* LATCH1 -> COIN COUNTERR, COUNTERL */
522		AM_RANGE(0x428c, 0x428f) AM_MIRROR(0x0040) AM_WRITE_LEGACY(led_w)               /* LATCH1 -> LEDs */
523		AM_RANGE(0x4290, 0x4290) AM_MIRROR(0x0047) AM_WRITE_LEGACY(rom_bank_w)            /* WRTREG */
524		AM_RANGE(0x4298, 0x4298) AM_MIRROR(0x0047) AM_WRITE_LEGACY(main_to_sound_w)      /* WRSOUND */
525		AM_RANGE(0x42a0, 0x42a0) AM_MIRROR(0x0047) AM_WRITE_LEGACY(firefox_disc_data_w)   /* DSKLATCH */
	517	AM_RANGE(0x4218, 0x4218) AM_MIRROR(0x0047) AM_WRITE(firefox_disc_read_w)   /* DSKREAD */
	518	AM_RANGE(0x4220, 0x4223) AM_MIRROR(0x0044) AM_WRITE(adc_select_w)         /* ADCSTART */
	519	AM_RANGE(0x4230, 0x4230) AM_MIRROR(0x0047) AM_WRITE(self_reset_w)         /* AMUCK */
	520	AM_RANGE(0x4280, 0x4280) AM_MIRROR(0x0040) AM_WRITE(novram_recall_w)      /* LATCH0 -> NVRECALL */
	521	AM_RANGE(0x4281, 0x4281) AM_MIRROR(0x0040) AM_WRITE(sound_reset_w)         /* LATCH0 -> RSTSOUND */
	522	AM_RANGE(0x4282, 0x4282) AM_MIRROR(0x0040) AM_WRITE(novram_store_w)         /* LATCH0 -> NVRSTORE */
	523	AM_RANGE(0x4283, 0x4283) AM_MIRROR(0x0040) AM_WRITE(firefox_disc_lock_w)   /* LATCH0 -> LOCK */
	524	AM_RANGE(0x4284, 0x4285) AM_MIRROR(0x0040) AM_WRITE(audio_enable_w)         /* LATCH0 -> SWDSKR, SWDSKL */
	525	AM_RANGE(0x4286, 0x4286) AM_MIRROR(0x0040) AM_WRITE(firefox_disc_reset_w)   /* LATCH0 -> RSTDSK */
	526	AM_RANGE(0x4287, 0x4287) AM_MIRROR(0x0040) AM_WRITE(firefox_disc_write_w)   /* LATCH0 -> WRDSK */
	527	AM_RANGE(0x4288, 0x4289) AM_MIRROR(0x0040) AM_WRITE(firefox_coin_counter_w)   /* LATCH1 -> COIN COUNTERR, COUNTERL */
	528	AM_RANGE(0x428c, 0x428f) AM_MIRROR(0x0040) AM_WRITE(led_w)               /* LATCH1 -> LEDs */
	529	AM_RANGE(0x4290, 0x4290) AM_MIRROR(0x0047) AM_WRITE(rom_bank_w)            /* WRTREG */
	530	AM_RANGE(0x4298, 0x4298) AM_MIRROR(0x0047) AM_WRITE(main_to_sound_w)      /* WRSOUND */
	531	AM_RANGE(0x42a0, 0x42a0) AM_MIRROR(0x0047) AM_WRITE(firefox_disc_data_w)   /* DSKLATCH */
526	532	AM_RANGE(0x4400, 0xffff) AM_ROM
527	533	ADDRESS_MAP_END
528	534
r14845	r14846
538	544	AM_RANGE(0x0000, 0x07ff) AM_RAM
539	545	AM_RANGE(0x0800, 0x087f) AM_MIRROR(0x0700) AM_RAM /* RIOT ram */
540	546	AM_RANGE(0x0880, 0x089f) AM_MIRROR(0x07e0) AM_DEVREADWRITE_LEGACY("riot",riot6532_r, riot6532_w)
541		AM_RANGE(0x1000, 0x1000) AM_READ_LEGACY(main_to_sound_r)
542		AM_RANGE(0x1800, 0x1800) AM_WRITE_LEGACY(sound_to_main_w)
	547	AM_RANGE(0x1000, 0x1000) AM_READ(main_to_sound_r)
	548	AM_RANGE(0x1800, 0x1800) AM_WRITE(sound_to_main_w)
543	549	AM_RANGE(0x2000, 0x200f) AM_DEVREADWRITE_LEGACY("pokey1", pokey_r, pokey_w)
544	550	AM_RANGE(0x2800, 0x280f) AM_DEVREADWRITE_LEGACY("pokey2", pokey_r, pokey_w)
545	551	AM_RANGE(0x3000, 0x300f) AM_DEVREADWRITE_LEGACY("pokey3", pokey_r, pokey_w)

src/mame/drivers/deco156.c

r14845	r14846
41	41	UINT16   m_pf1_rowscroll[0x800/2];
42	42	UINT16   m_pf2_rowscroll[0x800/2];
43	43	UINT16* m_spriteram;
	44	DECLARE_WRITE32_MEMBER(hvysmsh_eeprom_w);
	45	DECLARE_WRITE32_MEMBER(wcvol95_nonbuffered_palette_w);
	46	DECLARE_WRITE32_MEMBER(deco156_nonbuffered_palette_w);
	47	DECLARE_READ32_MEMBER(wcvol95_pf1_rowscroll_r);
	48	DECLARE_READ32_MEMBER(wcvol95_pf2_rowscroll_r);
	49	DECLARE_READ32_MEMBER(wcvol95_spriteram_r);
	50	DECLARE_WRITE32_MEMBER(wcvol95_pf1_rowscroll_w);
	51	DECLARE_WRITE32_MEMBER(wcvol95_pf2_rowscroll_w);
	52	DECLARE_WRITE32_MEMBER(wcvol95_spriteram_w);
44	53	};
45	54
46	55
r14845	r14846
76	85
77	86	/***************************************************************************/
78	87
79		static WRITE32_HANDLER(hvysmsh_eeprom_w)
	88	WRITE32_MEMBER(deco156_state::hvysmsh_eeprom_w)
80	89	{
81		deco156_state *state = space->machine().driver_data<deco156_state>();
82	90	if (ACCESSING_BITS_0_7)
83	91	{
84		state->m_oki2->set_bank_base(0x40000 * (data & 0x7));
85		input_port_write(space->machine(), "EEPROMOUT", data, 0xff);
	92	m_oki2->set_bank_base(0x40000 * (data & 0x7));
	93	input_port_write(machine(), "EEPROMOUT", data, 0xff);
86	94	}
87	95	}
88	96
r14845	r14846
92	100	oki->set_bank_base((data & 1) * 0x40000);
93	101	}
94	102
95		static WRITE32_HANDLER(wcvol95_nonbuffered_palette_w)
	103	WRITE32_MEMBER(deco156_state::wcvol95_nonbuffered_palette_w)
96	104	{
97		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
98		palette_set_color_rgb(space->machine(),offset,pal5bit(space->machine().generic.paletteram.u32[offset] >> 0),pal5bit(space->machine().generic.paletteram.u32[offset] >> 5),pal5bit(space->machine().generic.paletteram.u32[offset] >> 10));
	105	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
	106	palette_set_color_rgb(machine(),offset,pal5bit(machine().generic.paletteram.u32[offset] >> 0),pal5bit(machine().generic.paletteram.u32[offset] >> 5),pal5bit(machine().generic.paletteram.u32[offset] >> 10));
99	107	}
100	108
101	109	/* This is the same as deco32_nonbuffered_palette_w in video/deco32.c */
102		static WRITE32_HANDLER( deco156_nonbuffered_palette_w )
	110	WRITE32_MEMBER(deco156_state::deco156_nonbuffered_palette_w)
103	111	{
104	112	int r,g,b;
105	113
106		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
	114	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
107	115
108		b = (space->machine().generic.paletteram.u32[offset] >>16) & 0xff;
109		g = (space->machine().generic.paletteram.u32[offset] >> 8) & 0xff;
110		r = (space->machine().generic.paletteram.u32[offset] >> 0) & 0xff;
	116	b = (machine().generic.paletteram.u32[offset] >>16) & 0xff;
	117	g = (machine().generic.paletteram.u32[offset] >> 8) & 0xff;
	118	r = (machine().generic.paletteram.u32[offset] >> 0) & 0xff;
111	119
112		palette_set_color(space->machine(),offset,MAKE_RGB(r,g,b));
	120	palette_set_color(machine(),offset,MAKE_RGB(r,g,b));
113	121	}
114	122
115		static READ32_HANDLER( wcvol95_pf1_rowscroll_r ) { deco156_state *state = space->machine().driver_data<deco156_state>(); return state->m_pf1_rowscroll[offset] ^ 0xffff0000; }
116		static READ32_HANDLER( wcvol95_pf2_rowscroll_r ) { deco156_state *state = space->machine().driver_data<deco156_state>();   return state->m_pf2_rowscroll[offset] ^ 0xffff0000; }
117		static READ32_HANDLER( wcvol95_spriteram_r )     { deco156_state *state = space->machine().driver_data<deco156_state>(); return state->m_spriteram[offset] ^ 0xffff0000; }
118		static WRITE32_HANDLER( wcvol95_pf1_rowscroll_w ) { deco156_state *state = space->machine().driver_data<deco156_state>(); data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&state->m_pf1_rowscroll[offset]); }
119		static WRITE32_HANDLER( wcvol95_pf2_rowscroll_w ) { deco156_state *state = space->machine().driver_data<deco156_state>(); data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&state->m_pf2_rowscroll[offset]); }
120		static WRITE32_HANDLER( wcvol95_spriteram_w )    { deco156_state *state = space->machine().driver_data<deco156_state>(); data &= 0x0000ffff; mem_mask &= 0x0000ffff;   COMBINE_DATA(&state->m_spriteram[offset]); }
	123	READ32_MEMBER(deco156_state::wcvol95_pf1_rowscroll_r){ return m_pf1_rowscroll[offset] ^ 0xffff0000; }
	124	READ32_MEMBER(deco156_state::wcvol95_pf2_rowscroll_r){ return m_pf2_rowscroll[offset] ^ 0xffff0000; }
	125	READ32_MEMBER(deco156_state::wcvol95_spriteram_r){ return m_spriteram[offset] ^ 0xffff0000; }
	126	WRITE32_MEMBER(deco156_state::wcvol95_pf1_rowscroll_w){ data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&m_pf1_rowscroll[offset]); }
	127	WRITE32_MEMBER(deco156_state::wcvol95_pf2_rowscroll_w){ data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&m_pf2_rowscroll[offset]); }
	128	WRITE32_MEMBER(deco156_state::wcvol95_spriteram_w){ data &= 0x0000ffff; mem_mask &= 0x0000ffff;   COMBINE_DATA(&m_spriteram[offset]); }
121	129
122	130
123	131	static ADDRESS_MAP_START( hvysmsh_map, AS_PROGRAM, 32, deco156_state )
r14845	r14846
125	133	AM_RANGE(0x100000, 0x107fff) AM_RAM
126	134	AM_RANGE(0x120000, 0x120003) AM_READ_PORT("INPUTS")
127	135	AM_RANGE(0x120000, 0x120003) AM_WRITENOP // Volume control in low byte
128		AM_RANGE(0x120004, 0x120007) AM_WRITE_LEGACY(hvysmsh_eeprom_w)
	136	AM_RANGE(0x120004, 0x120007) AM_WRITE(hvysmsh_eeprom_w)
129	137	AM_RANGE(0x120008, 0x12000b) AM_WRITENOP // IRQ ack?
130	138	AM_RANGE(0x12000c, 0x12000f) AM_DEVWRITE_LEGACY("oki1", hvysmsh_oki_0_bank_w)
131	139	AM_RANGE(0x140000, 0x140003) AM_DEVREADWRITE8("oki1", okim6295_device, read, write, 0x000000ff)
r14845	r14846
133	141	AM_RANGE(0x180000, 0x18001f) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf_control_dword_r, deco16ic_pf_control_dword_w)
134	142	AM_RANGE(0x190000, 0x191fff) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf1_data_dword_r, deco16ic_pf1_data_dword_w)
135	143	AM_RANGE(0x194000, 0x195fff) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf2_data_dword_r, deco16ic_pf2_data_dword_w)
136		AM_RANGE(0x1a0000, 0x1a0fff) AM_READWRITE_LEGACY(wcvol95_pf1_rowscroll_r, wcvol95_pf1_rowscroll_w)
137		AM_RANGE(0x1a4000, 0x1a4fff) AM_READWRITE_LEGACY(wcvol95_pf2_rowscroll_r, wcvol95_pf2_rowscroll_w)
138		AM_RANGE(0x1c0000, 0x1c0fff) AM_RAM_WRITE_LEGACY(deco156_nonbuffered_palette_w) AM_BASE_GENERIC(paletteram)
	144	AM_RANGE(0x1a0000, 0x1a0fff) AM_READWRITE(wcvol95_pf1_rowscroll_r, wcvol95_pf1_rowscroll_w)
	145	AM_RANGE(0x1a4000, 0x1a4fff) AM_READWRITE(wcvol95_pf2_rowscroll_r, wcvol95_pf2_rowscroll_w)
	146	AM_RANGE(0x1c0000, 0x1c0fff) AM_RAM_WRITE(deco156_nonbuffered_palette_w) AM_BASE_GENERIC(paletteram)
139	147	AM_RANGE(0x1d0010, 0x1d002f) AM_READNOP // Check for DMA complete?
140		AM_RANGE(0x1e0000, 0x1e1fff) AM_READWRITE_LEGACY(wcvol95_spriteram_r, wcvol95_spriteram_w)
	148	AM_RANGE(0x1e0000, 0x1e1fff) AM_READWRITE(wcvol95_spriteram_r, wcvol95_spriteram_w)
141	149	ADDRESS_MAP_END
142	150
143	151	static ADDRESS_MAP_START( wcvol95_map, AS_PROGRAM, 32, deco156_state )
r14845	r14846
145	153	AM_RANGE(0x100000, 0x10001f) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf_control_dword_r, deco16ic_pf_control_dword_w)
146	154	AM_RANGE(0x110000, 0x111fff) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf1_data_dword_r, deco16ic_pf1_data_dword_w)
147	155	AM_RANGE(0x114000, 0x115fff) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf2_data_dword_r, deco16ic_pf2_data_dword_w)
148		AM_RANGE(0x120000, 0x120fff) AM_READWRITE_LEGACY(wcvol95_pf1_rowscroll_r, wcvol95_pf1_rowscroll_w)
149		AM_RANGE(0x124000, 0x124fff) AM_READWRITE_LEGACY(wcvol95_pf2_rowscroll_r, wcvol95_pf2_rowscroll_w)
	156	AM_RANGE(0x120000, 0x120fff) AM_READWRITE(wcvol95_pf1_rowscroll_r, wcvol95_pf1_rowscroll_w)
	157	AM_RANGE(0x124000, 0x124fff) AM_READWRITE(wcvol95_pf2_rowscroll_r, wcvol95_pf2_rowscroll_w)
150	158	AM_RANGE(0x130000, 0x137fff) AM_RAM
151	159	AM_RANGE(0x140000, 0x140003) AM_READ_PORT("INPUTS")
152	160	AM_RANGE(0x150000, 0x150003) AM_WRITE_PORT("EEPROMOUT")
153		AM_RANGE(0x160000, 0x161fff) AM_READWRITE_LEGACY(wcvol95_spriteram_r, wcvol95_spriteram_w)
	161	AM_RANGE(0x160000, 0x161fff) AM_READWRITE(wcvol95_spriteram_r, wcvol95_spriteram_w)
154	162	AM_RANGE(0x170000, 0x170003) AM_NOP // Irq ack?
155		AM_RANGE(0x180000, 0x180fff) AM_RAM_WRITE_LEGACY(wcvol95_nonbuffered_palette_w) AM_BASE_GENERIC(paletteram)
	163	AM_RANGE(0x180000, 0x180fff) AM_RAM_WRITE(wcvol95_nonbuffered_palette_w) AM_BASE_GENERIC(paletteram)
156	164	AM_RANGE(0x1a0000, 0x1a0007) AM_DEVREADWRITE8_LEGACY("ymz", ymz280b_r, ymz280b_w, 0x000000ff)
157	165	ADDRESS_MAP_END
158	166

src/mame/drivers/dwarfd.c

r14845	r14846
333	333	UINT8    m_videobuf[0x8000];
334	334
335	335	required_device<cpu_device> m_maincpu;
	336	DECLARE_WRITE8_MEMBER(i8275_preg_w);
	337	DECLARE_READ8_MEMBER(i8275_preg_r);
	338	DECLARE_WRITE8_MEMBER(i8275_creg_w);
	339	DECLARE_READ8_MEMBER(i8275_sreg_r);
	340	DECLARE_READ8_MEMBER(dwarfd_ram_r);
	341	DECLARE_WRITE8_MEMBER(dwarfd_ram_w);
	342	DECLARE_WRITE8_MEMBER(output1_w);
	343	DECLARE_WRITE8_MEMBER(output2_w);
	344	DECLARE_READ8_MEMBER(qc_b8_r);
336	345	};
337	346
338	347
r14845	r14846
373	382	};
374	383
375	384
376		static WRITE8_HANDLER (i8275_preg_w) //param reg
	385	WRITE8_MEMBER(dwarfd_state::i8275_preg_w)//param reg
377	386	{
378		dwarfd_state *state = space->machine().driver_data<dwarfd_state>();
379	387
380		switch (state->m_i8275Command)
	388	switch (m_i8275Command)
381	389	{
382	390	case I8275_COMMAND_RESET:
383	391	{
384		switch (state->m_i8275CommandSeqCnt)
	392	switch (m_i8275CommandSeqCnt)
385	393	{
386	394	case 4:
387	395	{
388	396	//screen byte comp byte 1
389		state->m_i8275SpacedRows = data >> 7;
390		state->m_i8275HorizontalCharactersRow = (data & 0x7f) + 1;
391		if (state->m_i8275HorizontalCharactersRow > 80)
	397	m_i8275SpacedRows = data >> 7;
	398	m_i8275HorizontalCharactersRow = (data & 0x7f) + 1;
	399	if (m_i8275HorizontalCharactersRow > 80)
392	400	{
393		logerror("i8275 Undefined num of characters/Row! = %d\n", state->m_i8275HorizontalCharactersRow);
394		state->m_i8275HorizontalCharactersRow = CHARACTERS_UNDEFINED;
	401	logerror("i8275 Undefined num of characters/Row! = %d\n", m_i8275HorizontalCharactersRow);
	402	m_i8275HorizontalCharactersRow = CHARACTERS_UNDEFINED;
395	403	}
396	404	else
397	405	{
398		logerror("i8275 %d characters/row\n", state->m_i8275HorizontalCharactersRow);
	406	logerror("i8275 %d characters/row\n", m_i8275HorizontalCharactersRow);
399	407	}
400		if (state->m_i8275SpacedRows & 1)
	408	if (m_i8275SpacedRows & 1)
401	409	{
402		logerror("i8275 spaced rows\n");
	410	logerror("i8275 &spaced rows\n");
403	411	}
404	412	else
405	413	{
406	414	logerror("i8275 normal rows\n");
407	415	}
408		state->m_i8275CommandSeqCnt--;
	416	m_i8275CommandSeqCnt--;
409	417	}
410	418	break;
411	419
412	420	case 3:
413	421	{
414	422	//screen byte comp byte 2
415		state->m_i8275VerticalRows = (data & 0x3f) + 1;
416		state->m_i8275VerticalRetraceRows = (data >> 6) + 1;
	423	m_i8275VerticalRows = (data & 0x3f) + 1;
	424	m_i8275VerticalRetraceRows = (data >> 6) + 1;
417	425
418		logerror("i8275 %d rows\n", state->m_i8275VerticalRows);
419		logerror("i8275 %d vertical retrace rows\n", state->m_i8275VerticalRetraceRows);
	426	logerror("i8275 %d rows\n", m_i8275VerticalRows);
	427	logerror("i8275 %d vertical retrace rows\n", m_i8275VerticalRetraceRows);
420	428
421		state->m_i8275CommandSeqCnt--;
	429	m_i8275CommandSeqCnt--;
422	430	}
423	431	break;
424	432
425	433	case 2:
426	434	{
427	435	//screen byte comp byte 3
428		state->m_i8275Underline = (data >> 4) + 1;
429		state->m_i8275Lines = (data & 0xf) + 1;
430		logerror("i8275 underline placement: %d\n", state->m_i8275Underline);
431		logerror("i8275 %d lines/row\n", state->m_i8275Lines);
	436	m_i8275Underline = (data >> 4) + 1;
	437	m_i8275Lines = (data & 0xf) + 1;
	438	logerror("i8275 underline placement: %d\n", m_i8275Underline);
	439	logerror("i8275 %d lines/row\n", m_i8275Lines);
432	440
433		state->m_i8275CommandSeqCnt--;
	441	m_i8275CommandSeqCnt--;
434	442	}
435	443	break;
436	444
437	445	case 1:
438	446	{
439	447	//screen byte comp byte 4
440		state->m_i8275LineCounterMode = data >> 7;
441		state->m_i8275FieldAttributeMode = (data >> 6) & 1;
442		state->m_i8275CursorFormat = (data >> 4) & 3;
443		state->m_i8275HorizontalRetrace = ((data & 0xf) + 1) << 1;
444		logerror("i8275 line counter mode: %d\n", state->m_i8275LineCounterMode);
445		if (state->m_i8275FieldAttributeMode)
	448	m_i8275LineCounterMode = data >> 7;
	449	m_i8275FieldAttributeMode = (data >> 6) & 1;
	450	m_i8275CursorFormat = (data >> 4) & 3;
	451	m_i8275HorizontalRetrace = ((data & 0xf) + 1) << 1;
	452	logerror("i8275 line counter mode: %d\n", m_i8275LineCounterMode);
	453	if (m_i8275FieldAttributeMode)
446	454	{
447	455	logerror("i8275 field attribute mode non-transparent\n");
448	456	}
r14845	r14846
451	459	logerror("i8275 field attribute mode transparent\n");
452	460	}
453	461
454		switch (state->m_i8275CursorFormat)
	462	switch (m_i8275CursorFormat)
455	463	{
456	464	case 0:   {logerror("i8275 cursor format - blinking reverse video block\n");}   break;
457	465	case 1:   {logerror("i8275 cursor format - blinking underline\n");}break;
r14845	r14846
459	467	case 3:   {logerror("i8275 cursor format - nonblinking underline\n");}break;
460	468	}
461	469
462		logerror("i8275 %d chars for horizontal retrace\n",state->m_i8275HorizontalRetrace );
463		state->m_i8275CommandSeqCnt--;
	470	logerror("i8275 %d chars for horizontal retrace\n",m_i8275HorizontalRetrace );
	471	m_i8275CommandSeqCnt--;
464	472	}
465	473	break;
466	474
r14845	r14846
489	497
490	498	}
491	499
492		static READ8_HANDLER (i8275_preg_r) //param reg
	500	READ8_MEMBER(dwarfd_state::i8275_preg_r)//param reg
493	501	{
494	502	return 0;
495	503	}
496	504
497		static WRITE8_HANDLER (i8275_creg_w) //comand reg
	505	WRITE8_MEMBER(dwarfd_state::i8275_creg_w)//comand reg
498	506	{
499		dwarfd_state *state = space->machine().driver_data<dwarfd_state>();
500	507
501	508	switch (data>>5)
502	509	{
503	510	case 0:
504	511	{
505	512	/* reset */
506		state->m_i8275Command = I8275_COMMAND_RESET;
507		state->m_i8275CommandSeqCnt = I8275_COMMAND_RESET_LENGTH;
	513	m_i8275Command = I8275_COMMAND_RESET;
	514	m_i8275CommandSeqCnt = I8275_COMMAND_RESET_LENGTH;
508	515	}
509	516	break;
510	517
511	518	case 5:
512	519	{
513	520	/* enable interrupt */
514		state->m_i8275Command = I8275_COMMAND_EI;
515		state->m_i8275CommandSeqCnt = I8275_COMMAND_EI_LENGTH;
	521	m_i8275Command = I8275_COMMAND_EI;
	522	m_i8275CommandSeqCnt = I8275_COMMAND_EI_LENGTH;
516	523	}
517	524	break;
518	525
519	526	case 6:
520	527	{
521	528	/* disable interrupt */
522		state->m_i8275Command = I8275_COMMAND_DI;
523		state->m_i8275CommandSeqCnt = I8275_COMMAND_DI_LENGTH;
	529	m_i8275Command = I8275_COMMAND_DI;
	530	m_i8275CommandSeqCnt = I8275_COMMAND_DI_LENGTH;
524	531	}
525	532	break;
526	533
527	534	case 7:
528	535	{
529	536	/* preset counters */
530		state->m_i8275CommandSeqCnt = I8275_COMMAND_PRESET_LENGTH;
	537	m_i8275CommandSeqCnt = I8275_COMMAND_PRESET_LENGTH;
531	538
532	539	}
533	540	break;
534	541	}
535	542	}
536	543
537		static READ8_HANDLER (i8275_sreg_r) //status
	544	READ8_MEMBER(dwarfd_state::i8275_sreg_r)//status
538	545	{
539	546	return 0;
540	547	}
541	548
542		static READ8_HANDLER(dwarfd_ram_r)
	549	READ8_MEMBER(dwarfd_state::dwarfd_ram_r)
543	550	{
544		dwarfd_state *state = space->machine().driver_data<dwarfd_state>();
545	551
546		if (state->m_crt_access == 0)
	552	if (m_crt_access == 0)
547	553	{
548		return state->m_dw_ram[offset];
	554	return m_dw_ram[offset];
549	555	}
550	556	else
551	557	{
552		state->m_videobuf[state->m_line * 256 + state->m_idx] = state->m_dw_ram[offset];
553		state->m_idx++;
554		return state->m_dw_ram[offset];
	558	m_videobuf[m_line * 256 + m_idx] = m_dw_ram[offset];
	559	m_idx++;
	560	return m_dw_ram[offset];
555	561	}
556	562	}
557	563
558		static WRITE8_HANDLER(dwarfd_ram_w)
	564	WRITE8_MEMBER(dwarfd_state::dwarfd_ram_w)
559	565	{
560		dwarfd_state *state = space->machine().driver_data<dwarfd_state>();
561		state->m_dw_ram[offset] = data;
	566	m_dw_ram[offset] = data;
562	567	}
563	568
564		static WRITE8_HANDLER(output1_w)
	569	WRITE8_MEMBER(dwarfd_state::output1_w)
565	570	{
566	571	/*
567	572	bits:
r14845	r14846
576	581	*/
577	582	}
578	583
579		static WRITE8_HANDLER(output2_w)
	584	WRITE8_MEMBER(dwarfd_state::output2_w)
580	585	{
581	586	/*
582	587	bits:
r14845	r14846
592	597	}
593	598
594	599
595		static READ8_HANDLER(qc_b8_r)
	600	READ8_MEMBER(dwarfd_state::qc_b8_r)
596	601	{
597		return space->machine().rand();
	602	return machine().rand();
598	603	}
599	604
600	605	static ADDRESS_MAP_START( mem_map, AS_PROGRAM, 8, dwarfd_state )
601	606	AM_RANGE(0x0000, 0x3fff) AM_ROM
602		AM_RANGE(0x4000, 0x4fff) AM_READWRITE_LEGACY(dwarfd_ram_r, dwarfd_ram_w)
	607	AM_RANGE(0x4000, 0x4fff) AM_READWRITE(dwarfd_ram_r, dwarfd_ram_w)
603	608	ADDRESS_MAP_END
604	609
605	610	static ADDRESS_MAP_START( io_map, AS_IO, 8, dwarfd_state )
r14845	r14846
607	612	AM_RANGE(0x01, 0x01) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
608	613	AM_RANGE(0x02, 0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
609	614
610		AM_RANGE(0x20, 0x20) AM_READWRITE_LEGACY(i8275_preg_r, i8275_preg_w)
611		AM_RANGE(0x21, 0x21) AM_READWRITE_LEGACY(i8275_sreg_r, i8275_creg_w)
	615	AM_RANGE(0x20, 0x20) AM_READWRITE(i8275_preg_r, i8275_preg_w)
	616	AM_RANGE(0x21, 0x21) AM_READWRITE(i8275_sreg_r, i8275_creg_w)
612	617	AM_RANGE(0x40, 0x40) AM_WRITENOP // unknown
613		AM_RANGE(0x60, 0x60) AM_WRITE_LEGACY(output1_w)
614		AM_RANGE(0x80, 0x80) AM_WRITE_LEGACY(output2_w)
	618	AM_RANGE(0x60, 0x60) AM_WRITE(output1_w)
	619	AM_RANGE(0x80, 0x80) AM_WRITE(output2_w)
615	620	AM_RANGE(0xc0, 0xc0) AM_READ_PORT("DSW1")
616	621	AM_RANGE(0xc1, 0xc1) AM_READ_PORT("DSW2")
617	622	ADDRESS_MAP_END
618	623
619	624	static ADDRESS_MAP_START( qc_map, AS_PROGRAM, 8, dwarfd_state )
620	625	AM_RANGE(0x0000, 0x7fff) AM_ROM
621		AM_RANGE(0x8000, 0x8fff) AM_READWRITE_LEGACY(dwarfd_ram_r, dwarfd_ram_w)
	626	AM_RANGE(0x8000, 0x8fff) AM_READWRITE(dwarfd_ram_r, dwarfd_ram_w)
622	627	ADDRESS_MAP_END
623	628
624	629	static ADDRESS_MAP_START( qc_io_map, AS_IO, 8, dwarfd_state )
625	630	AM_IMPORT_FROM( io_map )
626	631	ADDRESS_MAP_GLOBAL_MASK(0xff)
627		AM_RANGE(0xb8, 0xb8) AM_READ_LEGACY(qc_b8_r)
	632	AM_RANGE(0xb8, 0xb8) AM_READ(qc_b8_r)
628	633	ADDRESS_MAP_END
629	634
630	635	static INPUT_PORTS_START( dwarfd )

src/mame/drivers/caswin.c

r14845	r14846
56	56	UINT8 *m_sc0_vram;
57	57	UINT8 *m_sc0_attr;
58	58	tilemap_t *m_sc0_tilemap;
	59	DECLARE_WRITE8_MEMBER(sc0_vram_w);
	60	DECLARE_WRITE8_MEMBER(sc0_attr_w);
	61	DECLARE_WRITE8_MEMBER(vvillage_scroll_w);
	62	DECLARE_WRITE8_MEMBER(vvillage_vregs_w);
	63	DECLARE_READ8_MEMBER(vvillage_rng_r);
	64	DECLARE_WRITE8_MEMBER(vvillage_output_w);
	65	DECLARE_WRITE8_MEMBER(vvillage_lamps_w);
59	66	};
60	67
61	68
r14845	r14846
86	93	return 0;
87	94	}
88	95
89		static WRITE8_HANDLER( sc0_vram_w )
	96	WRITE8_MEMBER(caswin_state::sc0_vram_w)
90	97	{
91		caswin_state *state = space->machine().driver_data<caswin_state>();
92		state->m_sc0_vram[offset] = data;
93		state->m_sc0_tilemap->mark_tile_dirty(offset);
	98	m_sc0_vram[offset] = data;
	99	m_sc0_tilemap->mark_tile_dirty(offset);
94	100	}
95	101
96		static WRITE8_HANDLER( sc0_attr_w )
	102	WRITE8_MEMBER(caswin_state::sc0_attr_w)
97	103	{
98		caswin_state *state = space->machine().driver_data<caswin_state>();
99		state->m_sc0_attr[offset] = data;
100		state->m_sc0_tilemap->mark_tile_dirty(offset);
	104	m_sc0_attr[offset] = data;
	105	m_sc0_tilemap->mark_tile_dirty(offset);
101	106	}
102	107
103	108	/*These two are tested during the two cherry sub-games.I really don't know what is supposed to do...*/
104		static WRITE8_HANDLER( vvillage_scroll_w )
	109	WRITE8_MEMBER(caswin_state::vvillage_scroll_w)
105	110	{
106	111	//...
107	112	}
108	113
109	114	/*---- --x- window effect? */
110	115	/*---- ---x flip screen */
111		static WRITE8_HANDLER( vvillage_vregs_w )
	116	WRITE8_MEMBER(caswin_state::vvillage_vregs_w)
112	117	{
113		flip_screen_set(space->machine(), data & 1);
	118	flip_screen_set(machine(), data & 1);
114	119	}
115	120
116	121	/**********************
r14845	r14846
119	124	*
120	125	**********************/
121	126
122		static READ8_HANDLER( vvillage_rng_r )
	127	READ8_MEMBER(caswin_state::vvillage_rng_r)
123	128	{
124		return space->machine().rand();
	129	return machine().rand();
125	130	}
126	131
127		static WRITE8_HANDLER( vvillage_output_w )
	132	WRITE8_MEMBER(caswin_state::vvillage_output_w)
128	133	{
129		coin_counter_w(space->machine(), 0,data & 1);
130		coin_counter_w(space->machine(), 1,data & 1);
	134	coin_counter_w(machine(), 0,data & 1);
	135	coin_counter_w(machine(), 1,data & 1);
131	136	// data & 4 payout counter
132		coin_lockout_w(space->machine(), 0,data & 0x20);
133		coin_lockout_w(space->machine(), 1,data & 0x20);
	137	coin_lockout_w(machine(), 0,data & 0x20);
	138	coin_lockout_w(machine(), 1,data & 0x20);
134	139	}
135	140
136		static WRITE8_HANDLER( vvillage_lamps_w )
	141	WRITE8_MEMBER(caswin_state::vvillage_lamps_w)
137	142	{
138	143	/*
139	144	---x ---- lamp button 5
r14845	r14846
142	147	---- --x- lamp button 2
143	148	---- ---x lamp button 1
144	149	*/
145		set_led_status(space->machine(), 0, data & 0x01);
146		set_led_status(space->machine(), 1, data & 0x02);
147		set_led_status(space->machine(), 2, data & 0x04);
148		set_led_status(space->machine(), 3, data & 0x08);
149		set_led_status(space->machine(), 4, data & 0x10);
	150	set_led_status(machine(), 0, data & 0x01);
	151	set_led_status(machine(), 1, data & 0x02);
	152	set_led_status(machine(), 2, data & 0x04);
	153	set_led_status(machine(), 3, data & 0x08);
	154	set_led_status(machine(), 4, data & 0x10);
150	155	}
151	156
152	157	static ADDRESS_MAP_START( vvillage_mem, AS_PROGRAM, 8, caswin_state )
153	158	AM_RANGE(0x0000, 0x7fff) AM_ROM
154		AM_RANGE(0xa000, 0xa000) AM_READ_LEGACY(vvillage_rng_r) //accessed by caswin only
	159	AM_RANGE(0xa000, 0xa000) AM_READ(vvillage_rng_r) //accessed by caswin only
155	160	AM_RANGE(0xe000, 0xe7ff) AM_RAM AM_SHARE("nvram")
156		AM_RANGE(0xf000, 0xf3ff) AM_RAM_WRITE_LEGACY(sc0_vram_w) AM_BASE(m_sc0_vram)
157		AM_RANGE(0xf800, 0xfbff) AM_RAM_WRITE_LEGACY(sc0_attr_w) AM_BASE(m_sc0_attr)
	161	AM_RANGE(0xf000, 0xf3ff) AM_RAM_WRITE(sc0_vram_w) AM_BASE(m_sc0_vram)
	162	AM_RANGE(0xf800, 0xfbff) AM_RAM_WRITE(sc0_attr_w) AM_BASE(m_sc0_attr)
158	163	ADDRESS_MAP_END
159	164
160	165	static ADDRESS_MAP_START( vvillage_io, AS_IO, 8, caswin_state )
r14845	r14846
163	168	AM_RANGE(0x02,0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
164	169	AM_RANGE(0x10,0x10) AM_READ_PORT("IN0")
165	170	AM_RANGE(0x11,0x11) AM_READ_PORT("IN1")
166		AM_RANGE(0x10,0x10) AM_WRITE_LEGACY(vvillage_scroll_w)
167		AM_RANGE(0x11,0x11) AM_WRITE_LEGACY(vvillage_vregs_w)
168		AM_RANGE(0x12,0x12) AM_WRITE_LEGACY(vvillage_lamps_w)
169		AM_RANGE(0x13,0x13) AM_WRITE_LEGACY(vvillage_output_w)
	171	AM_RANGE(0x10,0x10) AM_WRITE(vvillage_scroll_w)
	172	AM_RANGE(0x11,0x11) AM_WRITE(vvillage_vregs_w)
	173	AM_RANGE(0x12,0x12) AM_WRITE(vvillage_lamps_w)
	174	AM_RANGE(0x13,0x13) AM_WRITE(vvillage_output_w)
170	175	ADDRESS_MAP_END
171	176
172	177

src/mame/drivers/hitpoker.c

r14845	r14846
62	62	UINT8 m_eeprom_data[0x200];
63	63	UINT16 m_eeprom_index;
64	64	UINT8 m_tmp;
	65	DECLARE_READ8_MEMBER(hitpoker_vram_r);
	66	DECLARE_WRITE8_MEMBER(hitpoker_vram_w);
	67	DECLARE_READ8_MEMBER(hitpoker_cram_r);
	68	DECLARE_WRITE8_MEMBER(hitpoker_cram_w);
	69	DECLARE_READ8_MEMBER(hitpoker_paletteram_r);
	70	DECLARE_WRITE8_MEMBER(hitpoker_paletteram_w);
	71	DECLARE_READ8_MEMBER(rtc_r);
	72	DECLARE_WRITE8_MEMBER(eeprom_w);
	73	DECLARE_READ8_MEMBER(eeprom_r);
	74	DECLARE_READ8_MEMBER(hitpoker_pic_r);
	75	DECLARE_WRITE8_MEMBER(hitpoker_pic_w);
	76	DECLARE_READ8_MEMBER(test_r);
65	77	};
66	78
67	79
r14845	r14846
102	114	return 0;
103	115	}
104	116
105		static READ8_HANDLER( hitpoker_vram_r )
	117	READ8_MEMBER(hitpoker_state::hitpoker_vram_r)
106	118	{
107		hitpoker_state *state = space->machine().driver_data<hitpoker_state>();
108		UINT8 *ROM = space->machine().region("maincpu")->base();
	119	UINT8 *ROM = machine().region("maincpu")->base();
109	120
110		if(state->m_pic_data & 0x10)
111		return state->m_videoram[offset];
	121	if(m_pic_data & 0x10)
	122	return m_videoram[offset];
112	123	else
113	124	return ROM[offset+0x8000];
114	125	}
115	126
116		static WRITE8_HANDLER( hitpoker_vram_w )
	127	WRITE8_MEMBER(hitpoker_state::hitpoker_vram_w)
117	128	{
118		hitpoker_state *state = space->machine().driver_data<hitpoker_state>();
119		//  UINT8 *ROM = space->machine().region("maincpu")->base();
	129	//  UINT8 *ROM = machine().region("maincpu")->base();
120	130
121		//  if(state->m_sys_regs[0x00] & 0x10)
122		state->m_videoram[offset] = data;
	131	//  if(m_sys_regs[0x00] & 0x10)
	132	m_videoram[offset] = data;
123	133	}
124	134
125		static READ8_HANDLER( hitpoker_cram_r )
	135	READ8_MEMBER(hitpoker_state::hitpoker_cram_r)
126	136	{
127		hitpoker_state *state = space->machine().driver_data<hitpoker_state>();
128		UINT8 *ROM = space->machine().region("maincpu")->base();
	137	UINT8 *ROM = machine().region("maincpu")->base();
129	138
130		if(state->m_pic_data & 0x10)
131		return state->m_colorram[offset];
	139	if(m_pic_data & 0x10)
	140	return m_colorram[offset];
132	141	else
133	142	return ROM[offset+0xc000];
134	143	}
135	144
136		static WRITE8_HANDLER( hitpoker_cram_w )
	145	WRITE8_MEMBER(hitpoker_state::hitpoker_cram_w)
137	146	{
138		hitpoker_state *state = space->machine().driver_data<hitpoker_state>();
139		state->m_colorram[offset] = data;
	147	m_colorram[offset] = data;
140	148	}
141	149
142		static READ8_HANDLER( hitpoker_paletteram_r )
	150	READ8_MEMBER(hitpoker_state::hitpoker_paletteram_r)
143	151	{
144		hitpoker_state *state = space->machine().driver_data<hitpoker_state>();
145		UINT8 *ROM = space->machine().region("maincpu")->base();
	152	UINT8 *ROM = machine().region("maincpu")->base();
146	153
147		if(state->m_pic_data & 0x10)
148		return state->m_paletteram[offset];
	154	if(m_pic_data & 0x10)
	155	return m_paletteram[offset];
149	156	else
150	157	return ROM[offset+0xe000];
151	158	}
152	159
153		static WRITE8_HANDLER( hitpoker_paletteram_w )
	160	WRITE8_MEMBER(hitpoker_state::hitpoker_paletteram_w)
154	161	{
155		hitpoker_state *state = space->machine().driver_data<hitpoker_state>();
156	162	int r,g,b,datax;
157		state->m_paletteram[offset] = data;
	163	m_paletteram[offset] = data;
158	164	offset>>=1;
159		datax=256*state->m_paletteram[offset*2]+state->m_paletteram[offset*2+1];
	165	datax=256*m_paletteram[offset*2]+m_paletteram[offset*2+1];
160	166
161	167	/* RGB565 */
162	168	b = ((datax)&0xf800)>>11;
163	169	g = ((datax)&0x07e0)>>5;
164	170	r = ((datax)&0x001f)>>0;
165	171
166		palette_set_color_rgb(space->machine(), offset, pal5bit(r), pal6bit(g), pal5bit(b));
	172	palette_set_color_rgb(machine(), offset, pal5bit(r), pal6bit(g), pal5bit(b));
167	173	}
168	174
169		static READ8_HANDLER( rtc_r )
	175	READ8_MEMBER(hitpoker_state::rtc_r)
170	176	{
171	177	return 0x80; //kludge it for now
172	178	}
173	179
174	180
175	181	/* tests 0x180, what EEPROM is this one??? */
176		static WRITE8_HANDLER( eeprom_w )
	182	WRITE8_MEMBER(hitpoker_state::eeprom_w)
177	183	{
178		hitpoker_state *state = space->machine().driver_data<hitpoker_state>();
179	184	if(offset == 0)
180	185	{
181		state->m_eeprom_index = (state->m_eeprom_index & 0x100)|(data & 0xff);
	186	m_eeprom_index = (m_eeprom_index & 0x100)|(data & 0xff);
182	187	//printf("W INDEX %02x\n",data);
183	188	}
184	189	if(offset == 1)
185	190	{
186		state->m_eeprom_index = (state->m_eeprom_index & 0xff)|((data & 0x1)<<8);
	191	m_eeprom_index = (m_eeprom_index & 0xff)|((data & 0x1)<<8);
187	192	//data & 0x4: eeprom clock
188	193	//printf("W CLOCK + INDEX %02x\n",data);
189	194	}
190	195	}
191	196
192		static READ8_HANDLER( eeprom_r )
	197	READ8_MEMBER(hitpoker_state::eeprom_r)
193	198	{
194		hitpoker_state *state = space->machine().driver_data<hitpoker_state>();
195		state->m_tmp = state->m_eeprom_data[state->m_eeprom_index];
196		if((state->m_eeprom_index & 0x1f) == 0x1f)
197		state->m_tmp = 0xaa;
198		//printf("%02x\n",state->m_eeprom_index);
199		state->m_eeprom_index++;
200		//state->m_eeprom_index&=0x1f;
201		return state->m_tmp;
	199	m_tmp = m_eeprom_data[m_eeprom_index];
	200	if((m_eeprom_index & 0x1f) == 0x1f)
	201	m_tmp = 0xaa;
	202	//printf("%02x\n",m_eeprom_index);
	203	m_eeprom_index++;
	204	//m_eeprom_index&=0x1f;
	205	return m_tmp;
202	206	}
203	207
204		static READ8_HANDLER( hitpoker_pic_r )
	208	READ8_MEMBER(hitpoker_state::hitpoker_pic_r)
205	209	{
206		hitpoker_state *state = space->machine().driver_data<hitpoker_state>();
207	210	//  logerror("R\n");
208	211
209	212	if(offset == 0)
210	213	{
211		if(cpu_get_pc(&space->device()) == 0x3143 ||
212		cpu_get_pc(&space->device()) == 0x314e ||
213		cpu_get_pc(&space->device()) == 0x3164 ||
214		cpu_get_pc(&space->device()) == 0x3179)
215		return state->m_pic_data;
	214	if(cpu_get_pc(&space.device()) == 0x3143 ||
	215	cpu_get_pc(&space.device()) == 0x314e ||
	216	cpu_get_pc(&space.device()) == 0x3164 ||
	217	cpu_get_pc(&space.device()) == 0x3179)
	218	return m_pic_data;
216	219
217		return (state->m_pic_data & 0x7f) | (state->m_pic_data & 0x40 ? 0x80 : 0x00);
	220	return (m_pic_data & 0x7f) | (m_pic_data & 0x40 ? 0x80 : 0x00);
218	221	}
219	222
220		return state->m_sys_regs[offset];
	223	return m_sys_regs[offset];
221	224	}
222	225
223		static WRITE8_HANDLER( hitpoker_pic_w )
	226	WRITE8_MEMBER(hitpoker_state::hitpoker_pic_w)
224	227	{
225		hitpoker_state *state = space->machine().driver_data<hitpoker_state>();
226	228	if(offset == 0)
227		state->m_pic_data = (data & 0xff);// | (data & 0x40) ? 0x80 : 0x00;
	229	m_pic_data = (data & 0xff);// | (data & 0x40) ? 0x80 : 0x00;
228	230	//  logerror("%02x W\n",data);
229		state->m_sys_regs[offset] = data;
	231	m_sys_regs[offset] = data;
230	232	}
231	233
232	234	#if 0
233		static READ8_HANDLER( test_r )
	235	READ8_MEMBER(hitpoker_state::test_r)
234	236	{
235		return space->machine().rand();
	237	return machine().rand();
236	238	}
237	239	#endif
238	240
r14845	r14846
240	242	static ADDRESS_MAP_START( hitpoker_map, AS_PROGRAM, 8, hitpoker_state )
241	243	AM_RANGE(0x0000, 0x00ff) AM_RAM // stack ram
242	244	AM_RANGE(0x1000, 0x103f) AM_RAM // internal I/O
243		AM_RANGE(0x8000, 0xb5ff) AM_READWRITE_LEGACY(hitpoker_vram_r,hitpoker_vram_w)
	245	AM_RANGE(0x8000, 0xb5ff) AM_READWRITE(hitpoker_vram_r,hitpoker_vram_w)
244	246	AM_RANGE(0xb600, 0xbdff) AM_RAM
245	247	AM_RANGE(0xbe0a, 0xbe0a) AM_READ_PORT("IN0")
246	248	AM_RANGE(0xbe0c, 0xbe0c) AM_READ_PORT("IN2") //irq ack?
247		AM_RANGE(0xbe0d, 0xbe0d) AM_READ_LEGACY(rtc_r)
	249	AM_RANGE(0xbe0d, 0xbe0d) AM_READ(rtc_r)
248	250	AM_RANGE(0xbe0e, 0xbe0e) AM_READ_PORT("IN1")
249		AM_RANGE(0xbe50, 0xbe51) AM_WRITE_LEGACY(eeprom_w)
250		AM_RANGE(0xbe53, 0xbe53) AM_READ_LEGACY(eeprom_r)
	251	AM_RANGE(0xbe50, 0xbe51) AM_WRITE(eeprom_w)
	252	AM_RANGE(0xbe53, 0xbe53) AM_READ(eeprom_r)
251	253	AM_RANGE(0xbe80, 0xbe80) AM_DEVWRITE("crtc", mc6845_device, address_w)
252	254	AM_RANGE(0xbe81, 0xbe81) AM_DEVWRITE("crtc", mc6845_device, register_w)
253	255	AM_RANGE(0xbe90, 0xbe91) AM_DEVREADWRITE_LEGACY("aysnd", ay8910_r,ay8910_address_data_w)
254	256	AM_RANGE(0xbea0, 0xbea0) AM_READ_PORT("VBLANK") //probably other bits as well
255		//  AM_RANGE(0xbe00, 0xbeff) AM_READ_LEGACY(test_r)
256		AM_RANGE(0xc000, 0xdfff) AM_READWRITE_LEGACY(hitpoker_cram_r,hitpoker_cram_w)
257		AM_RANGE(0xe000, 0xefff) AM_READWRITE_LEGACY(hitpoker_paletteram_r,hitpoker_paletteram_w)
	257	//  AM_RANGE(0xbe00, 0xbeff) AM_READ(test_r)
	258	AM_RANGE(0xc000, 0xdfff) AM_READWRITE(hitpoker_cram_r,hitpoker_cram_w)
	259	AM_RANGE(0xe000, 0xefff) AM_READWRITE(hitpoker_paletteram_r,hitpoker_paletteram_w)
258	260	AM_RANGE(0x0000, 0xbdff) AM_ROM
259	261	AM_RANGE(0xbf00, 0xffff) AM_ROM
260	262	ADDRESS_MAP_END
261	263
262	264	static ADDRESS_MAP_START( hitpoker_io, AS_IO, 8, hitpoker_state )
263		AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_READWRITE_LEGACY(hitpoker_pic_r,hitpoker_pic_w) AM_BASE(m_sys_regs)
	265	AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_READWRITE(hitpoker_pic_r,hitpoker_pic_w) AM_BASE(m_sys_regs)
264	266	ADDRESS_MAP_END
265	267
266	268	static INPUT_PORTS_START( hitpoker )

src/mame/drivers/m79amb.c

r14845	r14846
71	71	/* misc */
72	72	UINT8 m_lut_gun1[0x100];
73	73	UINT8 m_lut_gun2[0x100];
	74	DECLARE_WRITE8_MEMBER(ramtek_videoram_w);
	75	DECLARE_READ8_MEMBER(gray5bit_controller0_r);
	76	DECLARE_READ8_MEMBER(gray5bit_controller1_r);
	77	DECLARE_WRITE8_MEMBER(m79amb_8002_w);
74	78	};
75	79
76	80
77		static WRITE8_HANDLER( ramtek_videoram_w )
	81	WRITE8_MEMBER(m79amb_state::ramtek_videoram_w)
78	82	{
79		m79amb_state *state = space->machine().driver_data<m79amb_state>();
80		state->m_videoram[offset] = data & ~*state->m_mask;
	83	m_videoram[offset] = data & ~*m_mask;
81	84	}
82	85
83	86	static SCREEN_UPDATE_RGB32( ramtek )
r14845	r14846
107	110	}
108	111
109	112
110		static READ8_HANDLER( gray5bit_controller0_r )
	113	READ8_MEMBER(m79amb_state::gray5bit_controller0_r)
111	114	{
112		m79amb_state *state = space->machine().driver_data<m79amb_state>();
113		UINT8 port_data = input_port_read(space->machine(), "8004");
114		UINT8 gun_pos = input_port_read(space->machine(), "GUN1");
	115	UINT8 port_data = input_port_read(machine(), "8004");
	116	UINT8 gun_pos = input_port_read(machine(), "GUN1");
115	117
116		return (port_data & 0xe0) | state->m_lut_gun1[gun_pos];
	118	return (port_data & 0xe0) | m_lut_gun1[gun_pos];
117	119	}
118	120
119		static READ8_HANDLER( gray5bit_controller1_r )
	121	READ8_MEMBER(m79amb_state::gray5bit_controller1_r)
120	122	{
121		m79amb_state *state = space->machine().driver_data<m79amb_state>();
122		UINT8 port_data = input_port_read(space->machine(), "8005");
123		UINT8 gun_pos = input_port_read(space->machine(), "GUN2");
	123	UINT8 port_data = input_port_read(machine(), "8005");
	124	UINT8 gun_pos = input_port_read(machine(), "GUN2");
124	125
125		return (port_data & 0xe0) | state->m_lut_gun2[gun_pos];
	126	return (port_data & 0xe0) | m_lut_gun2[gun_pos];
126	127	}
127	128
128		static WRITE8_HANDLER( m79amb_8002_w )
	129	WRITE8_MEMBER(m79amb_state::m79amb_8002_w)
129	130	{
130	131	/* D1 may also be watchdog reset */
131	132	/* port goes to 0x7f to turn on explosion lamp */
r14845	r14846
134	135
135	136	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, m79amb_state )
136	137	AM_RANGE(0x0000, 0x1fff) AM_ROM
137		AM_RANGE(0x4000, 0x5fff) AM_RAM_WRITE_LEGACY(ramtek_videoram_w) AM_BASE(m_videoram)
	138	AM_RANGE(0x4000, 0x5fff) AM_RAM_WRITE(ramtek_videoram_w) AM_BASE(m_videoram)
138	139	AM_RANGE(0x6000, 0x63ff) AM_RAM               /* ?? */
139	140	AM_RANGE(0x8000, 0x8000) AM_READ_PORT("8000") AM_DEVWRITE_LEGACY("discrete", m79amb_8000_w)
140	141	AM_RANGE(0x8001, 0x8001) AM_WRITEONLY AM_BASE(m_mask)
141		AM_RANGE(0x8002, 0x8002) AM_READ_PORT("8002") AM_WRITE_LEGACY(m79amb_8002_w)
	142	AM_RANGE(0x8002, 0x8002) AM_READ_PORT("8002") AM_WRITE(m79amb_8002_w)
142	143	AM_RANGE(0x8003, 0x8003) AM_DEVWRITE_LEGACY("discrete", m79amb_8003_w)
143		AM_RANGE(0x8004, 0x8004) AM_READ_LEGACY(gray5bit_controller0_r)
144		AM_RANGE(0x8005, 0x8005) AM_READ_LEGACY(gray5bit_controller1_r)
	144	AM_RANGE(0x8004, 0x8004) AM_READ(gray5bit_controller0_r)
	145	AM_RANGE(0x8005, 0x8005) AM_READ(gray5bit_controller1_r)
145	146	AM_RANGE(0xc000, 0xc07f) AM_RAM               /* ?? */
146	147	AM_RANGE(0xc200, 0xc27f) AM_RAM               /* ?? */
147	148	ADDRESS_MAP_END

src/mame/drivers/meritm.c

r14845	r14846
147	147	required_device<v9938_device> m_v9938_0;
148	148	required_device<v9938_device> m_v9938_1;
149	149	required_device<microtouch_device> m_microtouch;
	150	DECLARE_WRITE8_MEMBER(meritm_crt250_bank_w);
	151	DECLARE_WRITE8_MEMBER(meritm_psd_a15_w);
	152	DECLARE_WRITE8_MEMBER(meritm_bank_w);
	153	DECLARE_WRITE8_MEMBER(meritm_crt250_questions_lo_w);
	154	DECLARE_WRITE8_MEMBER(meritm_crt250_questions_hi_w);
	155	DECLARE_WRITE8_MEMBER(meritm_crt250_questions_bank_w);
	156	DECLARE_WRITE8_MEMBER(meritm_ds1644_w);
	157	DECLARE_READ8_MEMBER(meritm_ds1644_r);
150	158	};
151	159
152	160
r14845	r14846
414	422	memory_set_bank(machine, "bank1", rombank );
415	423	};
416	424
417		static WRITE8_HANDLER(meritm_crt250_bank_w)
	425	WRITE8_MEMBER(meritm_state::meritm_crt250_bank_w)
418	426	{
419		meritm_crt250_switch_banks(space->machine());
	427	meritm_crt250_switch_banks(machine());
420	428	};
421	429
422	430	static void meritm_switch_banks( running_machine &machine )
r14845	r14846
434	442	memory_set_bank(machine, "bank3", rambank);
435	443	};
436	444
437		static WRITE8_HANDLER(meritm_psd_a15_w)
	445	WRITE8_MEMBER(meritm_state::meritm_psd_a15_w)
438	446	{
439		meritm_state *state = space->machine().driver_data<meritm_state>();
440		state->m_psd_a15 = data;
441		//logerror( "Writing PSD_A15 with %02x at PC=%04X\n", data, cpu_get_pc(&space->device()) );
442		meritm_switch_banks(space->machine());
	447	m_psd_a15 = data;
	448	//logerror( "Writing PSD_A15 with %02x at PC=%04X\n", data, cpu_get_pc(&space.device()) );
	449	meritm_switch_banks(machine());
443	450	};
444	451
445		static WRITE8_HANDLER(meritm_bank_w)
	452	WRITE8_MEMBER(meritm_state::meritm_bank_w)
446	453	{
447		meritm_switch_banks(space->machine());
	454	meritm_switch_banks(machine());
448	455	};
449	456
450	457	/*************************************
r14845	r14846
454	461	*************************************/
455	462
456	463
457		static WRITE8_HANDLER(meritm_crt250_questions_lo_w)
	464	WRITE8_MEMBER(meritm_state::meritm_crt250_questions_lo_w)
458	465	{
459		meritm_state *state = space->machine().driver_data<meritm_state>();
460		state->m_questions_loword_address &= 0xff00;
461		state->m_questions_loword_address |= data;
	466	m_questions_loword_address &= 0xff00;
	467	m_questions_loword_address |= data;
462	468	};
463	469
464		static WRITE8_HANDLER(meritm_crt250_questions_hi_w)
	470	WRITE8_MEMBER(meritm_state::meritm_crt250_questions_hi_w)
465	471	{
466		meritm_state *state = space->machine().driver_data<meritm_state>();
467		state->m_questions_loword_address &= 0x00ff;
468		state->m_questions_loword_address |= (data << 8);
	472	m_questions_loword_address &= 0x00ff;
	473	m_questions_loword_address |= (data << 8);
469	474	};
470	475
471		static WRITE8_HANDLER(meritm_crt250_questions_bank_w)
	476	WRITE8_MEMBER(meritm_state::meritm_crt250_questions_bank_w)
472	477	{
473		meritm_state *state = space->machine().driver_data<meritm_state>();
474	478	UINT32 questions_address;
475	479	UINT8 *dst;
476	480
477		if ((state->m_bank & 0x07) != 0)
	481	if ((m_bank & 0x07) != 0)
478	482	{
479		logerror("meritm_crt250_questions_bank_w: bank is %d\n", state->m_bank);
	483	logerror("meritm_crt250_questions_bank_w: bank is %d\n", m_bank);
480	484	return;
481	485	}
482	486
483		dst = space->machine().region("maincpu")->base() + 0x70000 + 2;
	487	dst = machine().region("maincpu")->base() + 0x70000 + 2;
484	488
485	489	if (data == 0)
486	490	{
r14845	r14846
508	512	case 0x3f: questions_address = 0xb0000; break;
509	513	default: logerror( "meritm_crt250_questions_bank_w: unknown data = %02x\n", data ); return;
510	514	}
511		logerror( "Reading question byte at %06X\n", questions_address | state->m_questions_loword_address);
512		*dst = space->machine().region("extra")->base()[questions_address | state->m_questions_loword_address];
	515	logerror( "Reading question byte at %06X\n", questions_address | m_questions_loword_address);
	516	*dst = machine().region("extra")->base()[questions_address | m_questions_loword_address];
513	517	}
514	518	};
515	519
r14845	r14846
520	524	*
521	525	*************************************/
522	526
523		static WRITE8_HANDLER(meritm_ds1644_w)
	527	WRITE8_MEMBER(meritm_state::meritm_ds1644_w)
524	528	{
525		meritm_state *state = space->machine().driver_data<meritm_state>();
526		int rambank = (state->m_psd_a15 >> 2) & 0x3;
	529	int rambank = (m_psd_a15 >> 2) & 0x3;
527	530	if (rambank < 3)
528	531	{
529		state->m_ram[rambank*0x2000 + 0x1ff8 + offset] = data;
	532	m_ram[rambank*0x2000 + 0x1ff8 + offset] = data;
530	533	}
531	534	else
532	535	{
533	536	if (offset == 0)
534	537	{
535		state->m_ram[0x7ff8] = data;
	538	m_ram[0x7ff8] = data;
536	539	}
537	540	//logerror( "Writing RTC, reg = %d, data = %x\n", offset, data);
538	541	}
r14845	r14846
545	548	return ((data / 10) << 4) | (data %10);
546	549	}
547	550
548		static READ8_HANDLER(meritm_ds1644_r)
	551	READ8_MEMBER(meritm_state::meritm_ds1644_r)
549	552	{
550		meritm_state *state = space->machine().driver_data<meritm_state>();
551	553	system_time systime;
552		int rambank = (state->m_psd_a15 >> 2) & 0x3;
	554	int rambank = (m_psd_a15 >> 2) & 0x3;
553	555	if (rambank == 3)
554	556	{
555	557	//logerror( "Reading RTC, reg = %x\n", offset);
556	558
557		space->machine().current_datetime(systime);
558		state->m_ram[0x7ff9] = binary_to_BCD(systime.local_time.second);
559		state->m_ram[0x7ffa] = binary_to_BCD(systime.local_time.minute);
560		state->m_ram[0x7ffb] = binary_to_BCD(systime.local_time.hour);
561		state->m_ram[0x7ffc] = binary_to_BCD(systime.local_time.weekday+1);
562		state->m_ram[0x7ffd] = binary_to_BCD(systime.local_time.mday);
563		state->m_ram[0x7ffe] = binary_to_BCD(systime.local_time.month+1);
564		state->m_ram[0x7fff] = binary_to_BCD(systime.local_time.year % 100);
	559	machine().current_datetime(systime);
	560	m_ram[0x7ff9] = binary_to_BCD(systime.local_time.second);
	561	m_ram[0x7ffa] = binary_to_BCD(systime.local_time.minute);
	562	m_ram[0x7ffb] = binary_to_BCD(systime.local_time.hour);
	563	m_ram[0x7ffc] = binary_to_BCD(systime.local_time.weekday+1);
	564	m_ram[0x7ffd] = binary_to_BCD(systime.local_time.mday);
	565	m_ram[0x7ffe] = binary_to_BCD(systime.local_time.month+1);
	566	m_ram[0x7fff] = binary_to_BCD(systime.local_time.year % 100);
565	567	}
566		return state->m_ram[rambank*0x2000 + 0x1ff8 + offset];
	568	return m_ram[rambank*0x2000 + 0x1ff8 + offset];
567	569	};
568	570
569	571	/*************************************
r14845	r14846
579	581
580	582	static ADDRESS_MAP_START( meritm_crt250_questions_map, AS_PROGRAM, 8, meritm_state )
581	583	AM_RANGE(0x0000, 0xdfff) AM_ROMBANK("bank1")
582		AM_RANGE(0x0000, 0x0000) AM_WRITE_LEGACY(meritm_crt250_questions_lo_w)
583		AM_RANGE(0x0001, 0x0001) AM_WRITE_LEGACY(meritm_crt250_questions_hi_w)
584		AM_RANGE(0x0002, 0x0002) AM_WRITE_LEGACY(meritm_crt250_questions_bank_w)
	584	AM_RANGE(0x0000, 0x0000) AM_WRITE(meritm_crt250_questions_lo_w)
	585	AM_RANGE(0x0001, 0x0001) AM_WRITE(meritm_crt250_questions_hi_w)
	586	AM_RANGE(0x0002, 0x0002) AM_WRITE(meritm_crt250_questions_bank_w)
585	587	AM_RANGE(0xe000, 0xffff) AM_RAM AM_SHARE("nvram")
586	588	ADDRESS_MAP_END
587	589
r14845	r14846
594	596	AM_RANGE(0x50, 0x53) AM_DEVREADWRITE_LEGACY("z80pio_1", z80pio_cd_ba_r, z80pio_cd_ba_w)
595	597	AM_RANGE(0x80, 0x80) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
596	598	AM_RANGE(0x80, 0x81) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
597		AM_RANGE(0xff, 0xff) AM_WRITE_LEGACY(meritm_crt250_bank_w)
	599	AM_RANGE(0xff, 0xff) AM_WRITE(meritm_crt250_bank_w)
598	600	ADDRESS_MAP_END
599	601
600	602	static ADDRESS_MAP_START( meritm_crt250_crt258_io_map, AS_IO, 8, meritm_state )
r14845	r14846
607	609	AM_RANGE(0x60, 0x67) AM_READWRITE_LEGACY(pc16552d_0_r,pc16552d_0_w)
608	610	AM_RANGE(0x80, 0x80) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
609	611	AM_RANGE(0x80, 0x81) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
610		AM_RANGE(0xff, 0xff) AM_WRITE_LEGACY(meritm_crt250_bank_w)
	612	AM_RANGE(0xff, 0xff) AM_WRITE(meritm_crt250_bank_w)
611	613	ADDRESS_MAP_END
612	614
613	615	static ADDRESS_MAP_START( meritm_map, AS_PROGRAM, 8, meritm_state )
r14845	r14846
618	620
619	621	static ADDRESS_MAP_START( meritm_io_map, AS_IO, 8, meritm_state )
620	622	ADDRESS_MAP_GLOBAL_MASK(0xff)
621		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(meritm_psd_a15_w)
	623	AM_RANGE(0x00, 0x00) AM_WRITE(meritm_psd_a15_w)
622	624	AM_RANGE(0x01, 0x01) AM_WRITE_LEGACY(watchdog_reset_w)
623	625	AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("v9938_0", v9938_device, read, write)
624	626	AM_RANGE(0x20, 0x23) AM_DEVREADWRITE("v9938_1", v9938_device, read, write)
r14845	r14846
628	630	AM_RANGE(0x60, 0x67) AM_READWRITE_LEGACY(pc16552d_0_r,pc16552d_0_w)
629	631	AM_RANGE(0x80, 0x80) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
630	632	AM_RANGE(0x80, 0x81) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
631		AM_RANGE(0xff, 0xff) AM_WRITE_LEGACY(meritm_bank_w)
	633	AM_RANGE(0xff, 0xff) AM_WRITE(meritm_bank_w)
632	634	ADDRESS_MAP_END
633	635
634	636	/*************************************
r14845	r14846
1876	1878	{ 0x99, 0x53, 0xfc, 0x29, 0x3a, 0x95, 0x8b, 0x58, 0xca, 0xca, 0x00, 0xc2, 0x30, 0x62, 0x0b, 0x96 };
1877	1879
1878	1880	ds1204_init(machine, megat3_ds1204_key, megat3_ds1204_nvram);
	1881
	1882	meritm_state *state = machine.driver_data<meritm_state>();
	1883	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xfff8, 0xffff, read8_delegate(FUNC(meritm_state::meritm_ds1644_r), state), write8_delegate(FUNC(meritm_state::meritm_ds1644_w), state));
1879	1884
1880		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xfff8, 0xffff, FUNC(meritm_ds1644_r), FUNC(meritm_ds1644_w) );
1881
1882	1885	};
1883	1886
1884	1887	static DRIVER_INIT(megat4)
r14845	r14846
1907	1910
1908	1911	ds1204_init(machine, 0, megat4te_ds1204_nvram);
1909	1912
1910		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xfff8, 0xffff, FUNC(meritm_ds1644_r), FUNC(meritm_ds1644_w) );
	1913	meritm_state *state = machine.driver_data<meritm_state>();
	1914	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xfff8, 0xffff, read8_delegate(FUNC(meritm_state::meritm_ds1644_r), state), write8_delegate(FUNC(meritm_state::meritm_ds1644_w), state));
1911	1915
1912	1916	};
1913	1917
r14845	r14846
1918	1922
1919	1923	ds1204_init(machine, 0, megat4te_ds1204_nvram);
1920	1924
1921		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xfff8, 0xffff, FUNC(meritm_ds1644_r), FUNC(meritm_ds1644_w) );
	1925	meritm_state *state = machine.driver_data<meritm_state>();
	1926	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xfff8, 0xffff, read8_delegate(FUNC(meritm_state::meritm_ds1644_r), state), write8_delegate(FUNC(meritm_state::meritm_ds1644_w), state));
1922	1927
1923	1928	};
1924	1929
r14845	r14846
1938	1943
1939	1944	ds1204_init(machine, 0, megat5_ds1204_nvram);
1940	1945
1941		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xfff8, 0xffff, FUNC(meritm_ds1644_r), FUNC(meritm_ds1644_w) );
	1946	meritm_state *state = machine.driver_data<meritm_state>();
	1947	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xfff8, 0xffff, read8_delegate(FUNC(meritm_state::meritm_ds1644_r), state), write8_delegate(FUNC(meritm_state::meritm_ds1644_w), state));
1942	1948
1943	1949	}
1944	1950

src/mame/drivers/koftball.c

r14845	r14846
51	51	UINT16 m_prot_data;
52	52
53	53	required_device<cpu_device> m_maincpu;
	54	DECLARE_WRITE16_MEMBER(bmc_RAMDAC_offset_w);
	55	DECLARE_WRITE16_MEMBER(bmc_RAMDAC_color_w);
	56	DECLARE_READ16_MEMBER(bmc_RAMDAC_color_r);
	57	DECLARE_READ16_MEMBER(random_number_r);
	58	DECLARE_READ16_MEMBER(prot_r);
	59	DECLARE_WRITE16_MEMBER(prot_w);
	60	DECLARE_WRITE16_MEMBER(bmc_1_videoram_w);
	61	DECLARE_WRITE16_MEMBER(bmc_2_videoram_w);
54	62	};
55	63
56	64
r14845	r14846
93	101	return 0;
94	102	}
95	103
96		static WRITE16_HANDLER( bmc_RAMDAC_offset_w )
	104	WRITE16_MEMBER(koftball_state::bmc_RAMDAC_offset_w)
97	105	{
98		koftball_state *state = space->machine().driver_data<koftball_state>();
99		state->m_clr_offset=data*3;
	106	m_clr_offset=data*3;
100	107	}
101	108
102		static WRITE16_HANDLER( bmc_RAMDAC_color_w )
	109	WRITE16_MEMBER(koftball_state::bmc_RAMDAC_color_w)
103	110	{
104		koftball_state *state = space->machine().driver_data<koftball_state>();
105		state->m_bmc_colorram[state->m_clr_offset]=data;
106		palette_set_color_rgb(space->machine(),state->m_clr_offset/3,pal6bit(state->m_bmc_colorram[(state->m_clr_offset/3)*3]),pal6bit(state->m_bmc_colorram[(state->m_clr_offset/3)*3+1]),pal6bit(state->m_bmc_colorram[(state->m_clr_offset/3)*3+2]));
107		state->m_clr_offset=(state->m_clr_offset+1)%768;
	111	m_bmc_colorram[m_clr_offset]=data;
	112	palette_set_color_rgb(machine(),m_clr_offset/3,pal6bit(m_bmc_colorram[(m_clr_offset/3)*3]),pal6bit(m_bmc_colorram[(m_clr_offset/3)*3+1]),pal6bit(m_bmc_colorram[(m_clr_offset/3)*3+2]));
	113	m_clr_offset=(m_clr_offset+1)%768;
108	114	}
109	115
110		static READ16_HANDLER( bmc_RAMDAC_color_r )
	116	READ16_MEMBER(koftball_state::bmc_RAMDAC_color_r)
111	117	{
112		koftball_state *state = space->machine().driver_data<koftball_state>();
113		return state->m_bmc_colorram[state->m_clr_offset];
	118	return m_bmc_colorram[m_clr_offset];
114	119	}
115	120
116		static READ16_HANDLER(random_number_r)
	121	READ16_MEMBER(koftball_state::random_number_r)
117	122	{
118		return space->machine().rand();
	123	return machine().rand();
119	124	}
120	125
121	126
122		static READ16_HANDLER(prot_r)
	127	READ16_MEMBER(koftball_state::prot_r)
123	128	{
124		koftball_state *state = space->machine().driver_data<koftball_state>();
125		switch(state->m_prot_data)
	129	switch(m_prot_data)
126	130	{
127	131	case 0x0000: return 0x0d00;
128	132	case 0xff00: return 0x8d00;
r14845	r14846
130	134	case 0x8000: return 0x0f0f;
131	135	}
132	136
133		logerror("unk prot r %x %x\n",state->m_prot_data,   cpu_get_previouspc(&space->device()));
134		return space->machine().rand();
	137	logerror("unk prot r %x %x\n",m_prot_data,   cpu_get_previouspc(&space.device()));
	138	return machine().rand();
135	139	}
136	140
137		static WRITE16_HANDLER(prot_w)
	141	WRITE16_MEMBER(koftball_state::prot_w)
138	142	{
139		koftball_state *state = space->machine().driver_data<koftball_state>();
140		COMBINE_DATA(&state->m_prot_data);
	143	COMBINE_DATA(&m_prot_data);
141	144	}
142	145
143		static WRITE16_HANDLER(bmc_1_videoram_w)
	146	WRITE16_MEMBER(koftball_state::bmc_1_videoram_w)
144	147	{
145		koftball_state *state = space->machine().driver_data<koftball_state>();
146		COMBINE_DATA(&state->m_bmc_1_videoram[offset]);
147		state->m_tilemap_1->mark_tile_dirty(offset);
	148	COMBINE_DATA(&m_bmc_1_videoram[offset]);
	149	m_tilemap_1->mark_tile_dirty(offset);
148	150	}
149	151
150		static WRITE16_HANDLER(bmc_2_videoram_w)
	152	WRITE16_MEMBER(koftball_state::bmc_2_videoram_w)
151	153	{
152		koftball_state *state = space->machine().driver_data<koftball_state>();
153		COMBINE_DATA(&state->m_bmc_2_videoram[offset]);
154		state->m_tilemap_2->mark_tile_dirty(offset);
	154	COMBINE_DATA(&m_bmc_2_videoram[offset]);
	155	m_tilemap_2->mark_tile_dirty(offset);
155	156	}
156	157
157	158	static ADDRESS_MAP_START( koftball_mem, AS_PROGRAM, 16, koftball_state )
158	159	AM_RANGE(0x000000, 0x01ffff) AM_ROM
159	160	AM_RANGE(0x220000, 0x22ffff) AM_RAM AM_BASE(m_main_ram)
160	161
161		AM_RANGE(0x260000, 0x260fff) AM_WRITE_LEGACY(bmc_1_videoram_w) AM_BASE(m_bmc_1_videoram)
162		AM_RANGE(0x261000, 0x261fff) AM_WRITE_LEGACY(bmc_2_videoram_w) AM_BASE(m_bmc_2_videoram)
	162	AM_RANGE(0x260000, 0x260fff) AM_WRITE(bmc_1_videoram_w) AM_BASE(m_bmc_1_videoram)
	163	AM_RANGE(0x261000, 0x261fff) AM_WRITE(bmc_2_videoram_w) AM_BASE(m_bmc_2_videoram)
163	164	AM_RANGE(0x262000, 0x26ffff) AM_RAM
164	165
165	166	AM_RANGE(0x280000, 0x28ffff) AM_RAM /* unused ? */
166	167	AM_RANGE(0x2a0000, 0x2a001f) AM_WRITENOP
167		AM_RANGE(0x2a0000, 0x2a001f) AM_READ_LEGACY(random_number_r)
168		AM_RANGE(0x2b0000, 0x2b0003) AM_READ_LEGACY(random_number_r)
169		AM_RANGE(0x2d8000, 0x2d8001) AM_READ_LEGACY(random_number_r)
	168	AM_RANGE(0x2a0000, 0x2a001f) AM_READ(random_number_r)
	169	AM_RANGE(0x2b0000, 0x2b0003) AM_READ(random_number_r)
	170	AM_RANGE(0x2d8000, 0x2d8001) AM_READ(random_number_r)
170	171	/*sound chip or mcu comm ? maybe just i/o (offset 0xe=lamps?)*/
171	172	AM_RANGE(0x2da000, 0x2da001) AM_WRITENOP /* offset ? */
172	173	AM_RANGE(0x2da002, 0x2da003) AM_WRITENOP /* data ? */
173	174
174		AM_RANGE(0x2db000, 0x2db001) AM_WRITE_LEGACY(bmc_RAMDAC_offset_w)
175		AM_RANGE(0x2db002, 0x2db003) AM_READWRITE_LEGACY(bmc_RAMDAC_color_r, bmc_RAMDAC_color_w)
	175	AM_RANGE(0x2db000, 0x2db001) AM_WRITE(bmc_RAMDAC_offset_w)
	176	AM_RANGE(0x2db002, 0x2db003) AM_READWRITE(bmc_RAMDAC_color_r, bmc_RAMDAC_color_w)
176	177	AM_RANGE(0x2db004, 0x2db005) AM_WRITENOP
177	178	AM_RANGE(0x2dc000, 0x2dc001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0xff00)
178	179	AM_RANGE(0x2f0000, 0x2f0003) AM_READ_PORT("INPUTS")
179	180	AM_RANGE(0x300000, 0x300001) AM_WRITENOP
180	181	AM_RANGE(0x320000, 0x320001) AM_WRITENOP
181		AM_RANGE(0x340000, 0x340001) AM_READ_LEGACY(prot_r)
182		AM_RANGE(0x360000, 0x360001) AM_WRITE_LEGACY(prot_w)
	182	AM_RANGE(0x340000, 0x340001) AM_READ(prot_r)
	183	AM_RANGE(0x360000, 0x360001) AM_WRITE(prot_w)
183	184	ADDRESS_MAP_END
184	185
185	186

src/mame/drivers/ertictac.c

r14845	r14846
32	32	ertictac_state(const machine_config &mconfig, device_type type, const char *tag)
33	33	: driver_device(mconfig, type, tag) { }
34	34
	35	DECLARE_READ32_MEMBER(ertictac_podule_r);
35	36	};
36	37
37	38
38		static READ32_HANDLER( ertictac_podule_r )
	39	READ32_MEMBER(ertictac_state::ertictac_podule_r)
39	40	{
40	41	ioc_regs[IRQ_STATUS_B] &= ~ARCHIMEDES_IRQB_PODULE_IRQ;
41	42
42	43	switch(offset)
43	44	{
44		case 0x04/4: return input_port_read(space->machine(), "DSW1") & 0xff;
45		case 0x08/4: return input_port_read(space->machine(), "DSW2") & 0xff;
46		case 0x10/4: return input_port_read(space->machine(), "SYSTEM") & 0xff;
47		case 0x14/4: return input_port_read(space->machine(), "P2") & 0xff;
48		case 0x18/4: return input_port_read(space->machine(), "P1") & 0xff;
	45	case 0x04/4: return input_port_read(machine(), "DSW1") & 0xff;
	46	case 0x08/4: return input_port_read(machine(), "DSW2") & 0xff;
	47	case 0x10/4: return input_port_read(machine(), "SYSTEM") & 0xff;
	48	case 0x14/4: return input_port_read(machine(), "P2") & 0xff;
	49	case 0x18/4: return input_port_read(machine(), "P1") & 0xff;
49	50	}
50	51
51	52	return 0;
r14845	r14846
55	56	AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(archimedes_memc_logical_r, archimedes_memc_logical_w)
56	57	AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_BASE_LEGACY(&archimedes_memc_physmem) /* physical RAM - 16 MB for now, should be 512k for the A310 */
57	58
58		AM_RANGE(0x03340000, 0x0334001f) AM_READ_LEGACY(ertictac_podule_r)
59		AM_RANGE(0x033c0000, 0x033c001f) AM_READ_LEGACY(ertictac_podule_r)
	59	AM_RANGE(0x03340000, 0x0334001f) AM_READ(ertictac_podule_r)
	60	AM_RANGE(0x033c0000, 0x033c001f) AM_READ(ertictac_podule_r)
60	61
61	62	AM_RANGE(0x03000000, 0x033fffff) AM_READWRITE_LEGACY(archimedes_ioc_r, archimedes_ioc_w)
62	63	AM_RANGE(0x03400000, 0x035fffff) AM_READWRITE_LEGACY(archimedes_vidc_r, archimedes_vidc_w)

src/mame/drivers/atarisy4.c

r14845	r14846
35	35	UINT16 *m_shared_ram[2];
36	36	UINT16 *m_screen_ram;
37	37	poly_manager *m_poly;
	38	DECLARE_WRITE16_MEMBER(gpu_w);
	39	DECLARE_READ16_MEMBER(gpu_r);
	40	DECLARE_READ16_MEMBER(m68k_shared_0_r);
	41	DECLARE_WRITE16_MEMBER(m68k_shared_0_w);
	42	DECLARE_READ16_MEMBER(m68k_shared_1_r);
	43	DECLARE_WRITE16_MEMBER(m68k_shared_1_w);
	44	DECLARE_READ16_MEMBER(dsp0_status_r);
	45	DECLARE_WRITE16_MEMBER(dsp0_control_w);
	46	DECLARE_READ16_MEMBER(dsp0_bio_r);
	47	DECLARE_WRITE16_MEMBER(dsp0_bank_w);
	48	DECLARE_READ16_MEMBER(dsp1_status_r);
	49	DECLARE_WRITE16_MEMBER(dsp1_control_w);
	50	DECLARE_READ16_MEMBER(dsp1_bio_r);
	51	DECLARE_WRITE16_MEMBER(dsp1_bank_w);
	52	DECLARE_READ16_MEMBER(analog_r);
38	53	};
39	54
40	55
r14845	r14846
112	127	*
113	128	*************************************/
114	129
115		static READ16_HANDLER( analog_r );
	130
116	131	static MACHINE_RESET( atarisy4 );
117	132	static MACHINE_RESET( airrace );
118	133
r14845	r14846
426	441	}
427	442	}
428	443
429		static WRITE16_HANDLER( gpu_w )
	444	WRITE16_MEMBER(atarisy4_state::gpu_w)
430	445	{
431	446	switch (offset)
432	447	{
r14845	r14846
454	469	case 0x17:
455	470	{
456	471	gpu.ecr = data;
457		execute_gpu_command(space->machine());
	472	execute_gpu_command(machine());
458	473	break;
459	474	}
460	475	case 0x1a:   gpu.far = data;      break;
r14845	r14846
463	478	gpu.mcr = data;
464	479
465	480	if (~data & 0x08)
466		cputag_set_input_line(space->machine(), "maincpu", 6, CLEAR_LINE);
	481	cputag_set_input_line(machine(), "maincpu", 6, CLEAR_LINE);
467	482
468	483	break;
469	484	}
r14845	r14846
473	488	}
474	489	}
475	490
476		static READ16_HANDLER( gpu_r )
	491	READ16_MEMBER(atarisy4_state::gpu_r)
477	492	{
478	493	UINT16 res = 0;
479	494
r14845	r14846
508	523	*
509	524	*************************************/
510	525
511		static READ16_HANDLER( m68k_shared_0_r )
	526	READ16_MEMBER(atarisy4_state::m68k_shared_0_r)
512	527	{
513		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
514		if (!BIT(state->m_csr[0], 3))
515		return (state->m_shared_ram[0][offset]);
	528	if (!BIT(m_csr[0], 3))
	529	return (m_shared_ram[0][offset]);
516	530	else
517	531	return 0xffff;
518	532	}
519	533
520		static WRITE16_HANDLER( m68k_shared_0_w )
	534	WRITE16_MEMBER(atarisy4_state::m68k_shared_0_w)
521	535	{
522		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
523		if (!BIT(state->m_csr[0], 3))
524		COMBINE_DATA(&state->m_shared_ram[0][offset]);
	536	if (!BIT(m_csr[0], 3))
	537	COMBINE_DATA(&m_shared_ram[0][offset]);
525	538	}
526	539
527		static READ16_HANDLER( m68k_shared_1_r )
	540	READ16_MEMBER(atarisy4_state::m68k_shared_1_r)
528	541	{
529		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
530		if (!BIT(state->m_csr[1], 3))
531		return (state->m_shared_ram[1][offset]);
	542	if (!BIT(m_csr[1], 3))
	543	return (m_shared_ram[1][offset]);
532	544	else
533	545	return 0xffff;
534	546	}
535	547
536		static WRITE16_HANDLER( m68k_shared_1_w )
	548	WRITE16_MEMBER(atarisy4_state::m68k_shared_1_w)
537	549	{
538		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
539		if (!BIT(state->m_csr[1], 3))
540		COMBINE_DATA(&state->m_shared_ram[1][offset]);
	550	if (!BIT(m_csr[1], 3))
	551	COMBINE_DATA(&m_shared_ram[1][offset]);
541	552	}
542	553
543		static READ16_HANDLER( dsp0_status_r )
	554	READ16_MEMBER(atarisy4_state::dsp0_status_r)
544	555	{
545		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
546		return state->m_csr[0];
	556	return m_csr[0];
547	557	}
548	558
549		static WRITE16_HANDLER( dsp0_control_w )
	559	WRITE16_MEMBER(atarisy4_state::dsp0_control_w)
550	560	{
551		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
552		cputag_set_input_line(space->machine(), "dsp0", INPUT_LINE_RESET, data & 0x01 ? CLEAR_LINE : ASSERT_LINE);
553		cputag_set_input_line(space->machine(), "dsp0", 0, data & 0x02 ? ASSERT_LINE : CLEAR_LINE);
	561	cputag_set_input_line(machine(), "dsp0", INPUT_LINE_RESET, data & 0x01 ? CLEAR_LINE : ASSERT_LINE);
	562	cputag_set_input_line(machine(), "dsp0", 0, data & 0x02 ? ASSERT_LINE : CLEAR_LINE);
554	563
555		state->m_csr[0] = data;
	564	m_csr[0] = data;
556	565	}
557	566
558		static READ16_HANDLER( dsp0_bio_r )
	567	READ16_MEMBER(atarisy4_state::dsp0_bio_r)
559	568	{
560		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
561		return BIT(state->m_csr[0], 2);
	569	return BIT(m_csr[0], 2);
562	570	}
563	571
564		static WRITE16_HANDLER( dsp0_bank_w )
	572	WRITE16_MEMBER(atarisy4_state::dsp0_bank_w)
565	573	{
566		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
567	574	if (data & 0x4000)
568	575	{
569	576	/* Set TIDONE bit */
570		state->m_csr[0] |= 0x10;
	577	m_csr[0] |= 0x10;
571	578
572		if (BIT(state->m_csr[0], 5) == 1)
	579	if (BIT(m_csr[0], 5) == 1)
573	580	fatalerror("68000 interrupt enable was set!");
574	581	}
575	582
576	583	data &= 0x3800;
577		memory_set_bankptr(space->machine(), "dsp0_bank1", &state->m_shared_ram[0][data]);
578		state->m_dsp_bank[0] = data;
	584	memory_set_bankptr(machine(), "dsp0_bank1", &m_shared_ram[0][data]);
	585	m_dsp_bank[0] = data;
579	586	}
580	587
581		static READ16_HANDLER( dsp1_status_r )
	588	READ16_MEMBER(atarisy4_state::dsp1_status_r)
582	589	{
583		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
584		return state->m_csr[1];
	590	return m_csr[1];
585	591	}
586	592
587		static WRITE16_HANDLER( dsp1_control_w )
	593	WRITE16_MEMBER(atarisy4_state::dsp1_control_w)
588	594	{
589		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
590		cputag_set_input_line(space->machine(), "dsp1", INPUT_LINE_RESET, data & 0x01 ? CLEAR_LINE : ASSERT_LINE);
591		cputag_set_input_line(space->machine(), "dsp1", 0, data & 0x02 ? ASSERT_LINE : CLEAR_LINE);
	595	cputag_set_input_line(machine(), "dsp1", INPUT_LINE_RESET, data & 0x01 ? CLEAR_LINE : ASSERT_LINE);
	596	cputag_set_input_line(machine(), "dsp1", 0, data & 0x02 ? ASSERT_LINE : CLEAR_LINE);
592	597
593		state->m_csr[1] = data;
	598	m_csr[1] = data;
594	599	}
595	600
596		static READ16_HANDLER( dsp1_bio_r )
	601	READ16_MEMBER(atarisy4_state::dsp1_bio_r)
597	602	{
598		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
599		return BIT(state->m_csr[1], 2);
	603	return BIT(m_csr[1], 2);
600	604	}
601	605
602		static WRITE16_HANDLER( dsp1_bank_w )
	606	WRITE16_MEMBER(atarisy4_state::dsp1_bank_w)
603	607	{
604		atarisy4_state *state = space->machine().driver_data<atarisy4_state>();
605	608	if (data & 0x4000)
606	609	{
607	610	/* Set TIDONE bit */
608		state->m_csr[1] |= 0x10;
	611	m_csr[1] |= 0x10;
609	612
610		if (BIT(state->m_csr[1], 5) == 1)
	613	if (BIT(m_csr[1], 5) == 1)
611	614	fatalerror("68000 interrupt enable was set!");
612	615	}
613	616
614	617	data &= 0x3800;
615		memory_set_bankptr(space->machine(), "dsp1_bank1", &state->m_shared_ram[1][data]);
616		state->m_dsp_bank[1] = data;
	618	memory_set_bankptr(machine(), "dsp1_bank1", &m_shared_ram[1][data]);
	619	m_dsp_bank[1] = data;
617	620	}
618	621
619	622
r14845	r14846
627	630	AM_RANGE(0x000000, 0x00ffff) AM_RAM AM_BASE(m_m68k_ram)
628	631	AM_RANGE(0x010000, 0x01ffff) AM_RAM
629	632	AM_RANGE(0x580000, 0x580001) AM_READ_PORT("JOYSTICK")
630		AM_RANGE(0x588000, 0x588001) AM_READ_LEGACY(analog_r)
	633	AM_RANGE(0x588000, 0x588001) AM_READ(analog_r)
631	634	AM_RANGE(0x598000, 0x598001) AM_NOP /* Sound board */
632		AM_RANGE(0x7c0000, 0x7c4fff) AM_READWRITE_LEGACY(m68k_shared_1_r, m68k_shared_1_w)
633		AM_RANGE(0x7c6000, 0x7c6001) AM_READWRITE_LEGACY(dsp1_status_r, dsp1_control_w)
634		AM_RANGE(0x7f0000, 0x7f4fff) AM_READWRITE_LEGACY(m68k_shared_0_r, m68k_shared_0_w)
635		AM_RANGE(0x7f6000, 0x7f6001) AM_READWRITE_LEGACY(dsp0_status_r, dsp0_control_w)
	635	AM_RANGE(0x7c0000, 0x7c4fff) AM_READWRITE(m68k_shared_1_r, m68k_shared_1_w)
	636	AM_RANGE(0x7c6000, 0x7c6001) AM_READWRITE(dsp1_status_r, dsp1_control_w)
	637	AM_RANGE(0x7f0000, 0x7f4fff) AM_READWRITE(m68k_shared_0_r, m68k_shared_0_w)
	638	AM_RANGE(0x7f6000, 0x7f6001) AM_READWRITE(dsp0_status_r, dsp0_control_w)
636	639	AM_RANGE(0xa00400, 0xbfffff) AM_RAM AM_BASE(m_screen_ram)
637		AM_RANGE(0xff8000, 0xff8fff) AM_READWRITE_LEGACY(gpu_r, gpu_w)
	640	AM_RANGE(0xff8000, 0xff8fff) AM_READWRITE(gpu_r, gpu_w)
638	641	ADDRESS_MAP_END
639	642
640	643
r14845	r14846
651	654	ADDRESS_MAP_END
652	655
653	656	static ADDRESS_MAP_START( dsp0_io_map, AS_IO, 16, atarisy4_state )
654		AM_RANGE(0x00, 0x01) AM_WRITE_LEGACY(dsp0_bank_w)
655		AM_RANGE(TMS32010_BIO, TMS32010_BIO) AM_READ_LEGACY(dsp0_bio_r)
	657	AM_RANGE(0x00, 0x01) AM_WRITE(dsp0_bank_w)
	658	AM_RANGE(TMS32010_BIO, TMS32010_BIO) AM_READ(dsp0_bio_r)
656	659	ADDRESS_MAP_END
657	660
658	661
r14845	r14846
669	672	ADDRESS_MAP_END
670	673
671	674	static ADDRESS_MAP_START( dsp1_io_map, AS_IO, 16, atarisy4_state )
672		AM_RANGE(0x00, 0x01) AM_WRITE_LEGACY(dsp1_bank_w)
673		AM_RANGE(TMS32010_BIO, TMS32010_BIO) AM_READ_LEGACY(dsp1_bio_r)
	675	AM_RANGE(0x00, 0x01) AM_WRITE(dsp1_bank_w)
	676	AM_RANGE(TMS32010_BIO, TMS32010_BIO) AM_READ(dsp1_bio_r)
674	677	ADDRESS_MAP_END
675	678
676	679
r14845	r14846
680	683	*
681	684	*************************************/
682	685
683		static READ16_HANDLER( analog_r )
	686	READ16_MEMBER(atarisy4_state::analog_r)
684	687	{
685		return (input_port_read(space->machine(), "STICKX") << 8) | input_port_read(space->machine(), "STICKY");
	688	return (input_port_read(machine(), "STICKX") << 8) | input_port_read(machine(), "STICKY");
686	689	}
687	690
688	691	static INPUT_PORTS_START( atarisy4 )

src/mame/drivers/missile.c

r14845	r14846
367	367	UINT8 m_flipscreen;
368	368	UINT8 m_madsel_delay;
369	369	UINT16 m_madsel_lastpc;
	370	DECLARE_WRITE8_MEMBER(missile_w);
	371	DECLARE_READ8_MEMBER(missile_r);
370	372	};
371	373
372	374
r14845	r14846
707	709	*
708	710	*************************************/
709	711
710		static WRITE8_HANDLER( missile_w )
	712	WRITE8_MEMBER(missile_state::missile_w)
711	713	{
712		missile_state *state = space->machine().driver_data<missile_state>();
713		UINT8 *videoram = state->m_videoram;
	714	UINT8 *videoram = m_videoram;
714	715	/* if we're in MADSEL mode, write to video RAM */
715		if (get_madsel(space))
	716	if (get_madsel(&space))
716	717	{
717		write_vram(space, offset, data);
	718	write_vram(&space, offset, data);
718	719	return;
719	720	}
720	721
r14845	r14846
727	728
728	729	/* POKEY */
729	730	else if (offset < 0x4800)
730		pokey_w(space->machine().device("pokey"), offset & 0x0f, data);
	731	pokey_w(machine().device("pokey"), offset & 0x0f, data);
731	732
732	733	/* OUT0 */
733	734	else if (offset < 0x4900)
734	735	{
735		state->m_flipscreen = ~data & 0x40;
736		coin_counter_w(space->machine(), 0, data & 0x20);
737		coin_counter_w(space->machine(), 1, data & 0x10);
738		coin_counter_w(space->machine(), 2, data & 0x08);
739		set_led_status(space->machine(), 1, ~data & 0x04);
740		set_led_status(space->machine(), 0, ~data & 0x02);
741		state->m_ctrld = data & 1;
	736	m_flipscreen = ~data & 0x40;
	737	coin_counter_w(machine(), 0, data & 0x20);
	738	coin_counter_w(machine(), 1, data & 0x10);
	739	coin_counter_w(machine(), 2, data & 0x08);
	740	set_led_status(machine(), 1, ~data & 0x04);
	741	set_led_status(machine(), 0, ~data & 0x02);
	742	m_ctrld = data & 1;
742	743	}
743	744
744	745	/* color RAM */
745	746	else if (offset >= 0x4b00 && offset < 0x4c00)
746		palette_set_color_rgb(space->machine(), offset & 7, pal1bit(~data >> 3), pal1bit(~data >> 2), pal1bit(~data >> 1));
	747	palette_set_color_rgb(machine(), offset & 7, pal1bit(~data >> 3), pal1bit(~data >> 2), pal1bit(~data >> 1));
747	748
748	749	/* watchdog */
749	750	else if (offset >= 0x4c00 && offset < 0x4d00)
750		watchdog_reset(space->machine());
	751	watchdog_reset(machine());
751	752
752	753	/* interrupt ack */
753	754	else if (offset >= 0x4d00 && offset < 0x4e00)
754	755	{
755		if (state->m_irq_state)
	756	if (m_irq_state)
756	757	{
757		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
758		state->m_irq_state = 0;
	758	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
	759	m_irq_state = 0;
759	760	}
760	761	}
761	762
762	763	/* anything else */
763	764	else
764		logerror("%04X:Unknown write to %04X = %02X\n", cpu_get_pc(&space->device()), offset, data);
	765	logerror("%04X:Unknown write to %04X = %02X\n", cpu_get_pc(&space.device()), offset, data);
765	766	}
766	767
767	768
768		static READ8_HANDLER( missile_r )
	769	READ8_MEMBER(missile_state::missile_r)
769	770	{
770		missile_state *state = space->machine().driver_data<missile_state>();
771		UINT8 *videoram = state->m_videoram;
	771	UINT8 *videoram = m_videoram;
772	772	UINT8 result = 0xff;
773	773
774	774	/* if we're in MADSEL mode, read from video RAM */
775		if (get_madsel(space))
776		return read_vram(space, offset);
	775	if (get_madsel(&space))
	776	return read_vram(&space, offset);
777	777
778	778	/* otherwise, strip A15 and handle manually */
779	779	offset &= 0x7fff;
r14845	r14846
784	784
785	785	/* ROM */
786	786	else if (offset >= 0x5000)
787		result = space->machine().region("maincpu")->base()[offset];
	787	result = machine().region("maincpu")->base()[offset];
788	788
789	789	/* POKEY */
790	790	else if (offset < 0x4800)
791		result = pokey_r(space->machine().device("pokey"), offset & 0x0f);
	791	result = pokey_r(machine().device("pokey"), offset & 0x0f);
792	792
793	793	/* IN0 */
794	794	else if (offset < 0x4900)
795	795	{
796		if (state->m_ctrld)   /* trackball */
	796	if (m_ctrld)   /* trackball */
797	797	{
798		if (!state->m_flipscreen)
799		result = ((input_port_read(space->machine(), "TRACK0_Y") << 4) & 0xf0) | (input_port_read(space->machine(), "TRACK0_X") & 0x0f);
	798	if (!m_flipscreen)
	799	result = ((input_port_read(machine(), "TRACK0_Y") << 4) & 0xf0) | (input_port_read(machine(), "TRACK0_X") & 0x0f);
800	800	else
801		result = ((input_port_read(space->machine(), "TRACK1_Y") << 4) & 0xf0) | (input_port_read(space->machine(), "TRACK1_X") & 0x0f);
	801	result = ((input_port_read(machine(), "TRACK1_Y") << 4) & 0xf0) | (input_port_read(machine(), "TRACK1_X") & 0x0f);
802	802	}
803	803	else   /* buttons */
804		result = input_port_read(space->machine(), "IN0");
	804	result = input_port_read(machine(), "IN0");
805	805	}
806	806
807	807	/* IN1 */
808	808	else if (offset < 0x4a00)
809		result = input_port_read(space->machine(), "IN1");
	809	result = input_port_read(machine(), "IN1");
810	810
811	811	/* IN2 */
812	812	else if (offset < 0x4b00)
813		result = input_port_read(space->machine(), "R10");
	813	result = input_port_read(machine(), "R10");
814	814
815	815	/* anything else */
816	816	else
817		logerror("%04X:Unknown read from %04X\n", cpu_get_pc(&space->device()), offset);
	817	logerror("%04X:Unknown read from %04X\n", cpu_get_pc(&space.device()), offset);
818	818	return result;
819	819	}
820	820
r14845	r14846
828	828
829	829	/* complete memory map derived from schematics (implemented above) */
830	830	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, missile_state )
831		AM_RANGE(0x0000, 0xffff) AM_READWRITE_LEGACY(missile_r, missile_w) AM_BASE(m_videoram)
	831	AM_RANGE(0x0000, 0xffff) AM_READWRITE(missile_r, missile_w) AM_BASE(m_videoram)
832	832	ADDRESS_MAP_END
833	833
834	834

src/mame/drivers/go2000.c

r14845	r14846
47	47
48	48	/* devices */
49	49	device_t *m_soundcpu;
	50	DECLARE_WRITE16_MEMBER(sound_cmd_w);
	51	DECLARE_WRITE8_MEMBER(go2000_pcm_1_bankswitch_w);
50	52	};
51	53
52	54
53		static WRITE16_HANDLER( sound_cmd_w )
	55	WRITE16_MEMBER(go2000_state::sound_cmd_w)
54	56	{
55		go2000_state *state = space->machine().driver_data<go2000_state>();
56	57	soundlatch_w(space, offset, data & 0xff);
57		device_set_input_line(state->m_soundcpu, 0, HOLD_LINE);
	58	device_set_input_line(m_soundcpu, 0, HOLD_LINE);
58	59	}
59	60
60	61	static ADDRESS_MAP_START( go2000_map, AS_PROGRAM, 16, go2000_state )
r14845	r14846
65	66	AM_RANGE(0x800000, 0x800fff) AM_RAM_WRITE_LEGACY(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)
66	67	AM_RANGE(0xa00000, 0xa00001) AM_READ_PORT("INPUTS")
67	68	AM_RANGE(0xa00002, 0xa00003) AM_READ_PORT("DSW")
68		AM_RANGE(0x620002, 0x620003) AM_WRITE_LEGACY(sound_cmd_w)
	69	AM_RANGE(0x620002, 0x620003) AM_WRITE(sound_cmd_w)
69	70	//  AM_RANGE(0xe00000, 0xe00001) AM_WRITENOP
70	71	//  AM_RANGE(0xe00010, 0xe00011) AM_WRITENOP
71	72	//  AM_RANGE(0xe00020, 0xe00021) AM_WRITENOP
72	73	ADDRESS_MAP_END
73	74
74		static WRITE8_HANDLER( go2000_pcm_1_bankswitch_w )
	75	WRITE8_MEMBER(go2000_state::go2000_pcm_1_bankswitch_w)
75	76	{
76		memory_set_bank(space->machine(), "bank1", data & 0x07);
	77	memory_set_bank(machine(), "bank1", data & 0x07);
77	78	}
78	79
79	80	static ADDRESS_MAP_START( go2000_sound_map, AS_PROGRAM, 8, go2000_state )
r14845	r14846
85	86	ADDRESS_MAP_GLOBAL_MASK(0xff)
86	87	AM_RANGE(0x00, 0x00) AM_READ_LEGACY(soundlatch_r)
87	88	AM_RANGE(0x00, 0x00) AM_DEVWRITE_LEGACY("dac1", dac_w)
88		AM_RANGE(0x03, 0x03) AM_WRITE_LEGACY(go2000_pcm_1_bankswitch_w)
	89	AM_RANGE(0x03, 0x03) AM_WRITE(go2000_pcm_1_bankswitch_w)
89	90	ADDRESS_MAP_END
90	91
91	92

src/mame/drivers/deshoros.c

r14845	r14846
25	25	UINT8 *m_io_ram;
26	26	char m_led_array[21];
27	27	UINT8 m_bank;
	28	DECLARE_READ8_MEMBER(io_r);
	29	DECLARE_WRITE8_MEMBER(io_w);
	30	void update_led_array(UINT8 new_data);
28	31	};
29	32
30	33
r14845	r14846
47	50	}
48	51
49	52	/*I don't know it this is 100% correct,might be different...*/
50		static void update_led_array(deshoros_state *state, UINT8 new_data)
	53	void deshoros_state::update_led_array(UINT8 new_data)
51	54	{
52	55	UINT8 i;
53	56	/*scroll the data*/
54	57	for(i=0;i<19;i++)
55		state->m_led_array[i] = state->m_led_array[i+1];
	58	m_led_array[i] = m_led_array[i+1];
56	59	/*update the data*/
57		state->m_led_array[19] = new_data;
	60	m_led_array[19] = new_data;
58	61	}
59	62
60	63
r14845	r14846
72	75	}
73	76	}
74	77
75		static READ8_HANDLER( io_r )
	78	READ8_MEMBER(deshoros_state::io_r)
76	79	{
77		deshoros_state *state = space->machine().driver_data<deshoros_state>();
78	80	switch(offset)
79	81	{
80	82	case 0x00: return 0xff; //printer read
81		case 0x03: return input_port_read(space->machine(), "KEY0" );
82		case 0x04: return input_port_read(space->machine(), "KEY1" );
83		case 0x05: return input_port_read(space->machine(), "SYSTEM" );
84		case 0x0a: return state->m_io_ram[offset]; //"buzzer" 0 read
85		case 0x0b: return state->m_io_ram[offset]; //"buzzer" 1 read
	83	case 0x03: return input_port_read(machine(), "KEY0" );
	84	case 0x04: return input_port_read(machine(), "KEY1" );
	85	case 0x05: return input_port_read(machine(), "SYSTEM" );
	86	case 0x0a: return m_io_ram[offset]; //"buzzer" 0 read
	87	case 0x0b: return m_io_ram[offset]; //"buzzer" 1 read
86	88	}
87	89	//  printf("R -> [%02x]\n",offset);
88	90
89		return state->m_io_ram[offset];
	91	return m_io_ram[offset];
90	92	}
91	93
92		static WRITE8_HANDLER( io_w )
	94	WRITE8_MEMBER(deshoros_state::io_w)
93	95	{
94		deshoros_state *state = space->machine().driver_data<deshoros_state>();
95	96	switch(offset)
96	97	{
97	98	case 0x00: /*Printer data*/                  return;
98		case 0x02: update_led_array(state, data);              return;
99		case 0x05: coin_lockout_w(space->machine(), 0,state->m_io_ram[offset] & 1);return;
	99	case 0x02: update_led_array(data);              return;
	100	case 0x05: coin_lockout_w(machine(), 0,m_io_ram[offset] & 1);return;
100	101	case 0x06: /*Printer IRQ enable*/             return;
101	102	//      case 0x0a: "buzzer" 0 write
102	103	//      case 0x0b: "buzzer" 1 write
103		case 0x0c: answer_bankswitch(space->machine(),data&0x03); return; //data & 0x10 enabled too,dunno if it is worth to shift the data...
	104	case 0x0c: answer_bankswitch(machine(),data&0x03); return; //data & 0x10 enabled too,dunno if it is worth to shift the data...
104	105	}
105		state->m_io_ram[offset] = data;
	106	m_io_ram[offset] = data;
106	107	//  printf("%02x -> [%02x]\n",data,offset);
107	108	}
108	109
109	110	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, deshoros_state )
110	111	AM_RANGE(0x0000, 0x5fff) AM_ROMBANK("bank1")
111	112	AM_RANGE(0x8000, 0x87ff) AM_RAM
112		AM_RANGE(0x9000, 0x900f) AM_READWRITE_LEGACY(io_r,io_w) AM_BASE(m_io_ram) //i/o area
	113	AM_RANGE(0x9000, 0x900f) AM_READWRITE(io_r,io_w) AM_BASE(m_io_ram) //i/o area
113	114	AM_RANGE(0xc000, 0xffff) AM_ROM
114	115	ADDRESS_MAP_END
115	116

src/mame/drivers/igs_m027.c

r14845	r14846
33	33	UINT32 *m_igs_palette32;
34	34	tilemap_t *m_igs_tx_tilemap;
35	35	tilemap_t *m_igs_bg_tilemap;
	36	DECLARE_WRITE32_MEMBER(igs_cg_videoram_w);
	37	DECLARE_WRITE32_MEMBER(igs_tx_videoram_w);
	38	DECLARE_WRITE32_MEMBER(igs_bg_videoram_w);
	39	DECLARE_WRITE32_MEMBER(igs_palette32_w);
36	40	};
37	41
38	42
r14845	r14846
52	56
53	57
54	58	/* CGLayer */
55		static WRITE32_HANDLER( igs_cg_videoram_w )
	59	WRITE32_MEMBER(igs_m027_state::igs_cg_videoram_w)
56	60	{
57		igs_m027_state *state = space->machine().driver_data<igs_m027_state>();
58		COMBINE_DATA(&state->m_igs_cg_videoram[offset]);
	61	COMBINE_DATA(&m_igs_cg_videoram[offset]);
59	62	//if(data!=0)
60		logerror("PC(%08X) CG @%x = %x!\n",cpu_get_pc(&space->device()),offset ,state->m_igs_cg_videoram[offset]);
	63	logerror("PC(%08X) CG @%x = %x!\n",cpu_get_pc(&space.device()),offset ,m_igs_cg_videoram[offset]);
61	64
62	65
63	66
r14845	r14846
96	99
97	100
98	101	/* TX Layer */
99		static WRITE32_HANDLER( igs_tx_videoram_w )
	102	WRITE32_MEMBER(igs_m027_state::igs_tx_videoram_w)
100	103	{
101		igs_m027_state *state = space->machine().driver_data<igs_m027_state>();
102		COMBINE_DATA(&state->m_igs_tx_videoram[offset]);
103		state->m_igs_tx_tilemap->mark_tile_dirty(offset);
	104	COMBINE_DATA(&m_igs_tx_videoram[offset]);
	105	m_igs_tx_tilemap->mark_tile_dirty(offset);
104	106	//if(data!=0)
105		//logerror( "TX VIDEO RAM OFFSET %x ,data %x!\n",offset ,state->m_igs_tx_videoram[offset]);
	107	//logerror( "TX VIDEO RAM OFFSET %x ,data %x!\n",offset ,m_igs_tx_videoram[offset]);
106	108	}
107	109
108	110	static TILE_GET_INFO( get_tx_tilemap_tile_info )
r14845	r14846
117	119	}
118	120
119	121	/* BG Layer */
120		static WRITE32_HANDLER( igs_bg_videoram_w )
	122	WRITE32_MEMBER(igs_m027_state::igs_bg_videoram_w)
121	123	{
122		igs_m027_state *state = space->machine().driver_data<igs_m027_state>();
123		COMBINE_DATA(&state->m_igs_bg_videoram[offset]);
124		state->m_igs_bg_tilemap->mark_tile_dirty(offset);
	124	COMBINE_DATA(&m_igs_bg_videoram[offset]);
	125	m_igs_bg_tilemap->mark_tile_dirty(offset);
125	126	//if(data!=0)
126		logerror("BG VIDEO RAM OFFSET %x ,data %x!\n",offset ,state->m_igs_bg_videoram[offset]);
	127	logerror("BG VIDEO RAM OFFSET %x ,data %x!\n",offset ,m_igs_bg_videoram[offset]);
127	128	}
128	129
129	130	static TILE_GET_INFO( get_bg_tilemap_tile_info )
r14845	r14846
139	140
140	141
141	142	/* Palette Layer */
142		static WRITE32_HANDLER( igs_palette32_w )
	143	WRITE32_MEMBER(igs_m027_state::igs_palette32_w)
143	144	{
144		igs_m027_state *state = space->machine().driver_data<igs_m027_state>();
145		space->machine().generic.paletteram.u16=(UINT16 *)state->m_igs_palette32;
146		COMBINE_DATA(&state->m_igs_palette32[offset]);
147		//paletteram16_xGGGGGRRRRRBBBBB_word_w(offset*2,space->machine().generic.paletteram.u16[offset*2],0);
148		//paletteram16_xGGGGGRRRRRBBBBB_word_w(offset*2+1,space->machine().generic.paletteram.u16[offset*2+1],0);
	145	machine().generic.paletteram.u16=(UINT16 *)m_igs_palette32;
	146	COMBINE_DATA(&m_igs_palette32[offset]);
	147	//paletteram16_xGGGGGRRRRRBBBBB_word_w(offset*2,machine().generic.paletteram.u16[offset*2],0);
	148	//paletteram16_xGGGGGRRRRRBBBBB_word_w(offset*2+1,machine().generic.paletteram.u16[offset*2+1],0);
149	149	//if(data!=0)
150		//fprintf(stdout,"PALETTE RAM OFFSET %x ,data %x!\n",offset ,state->m_igs_palette32[offset]);
	150	//fprintf(stdout,"PALETTE RAM OFFSET %x ,data %x!\n",offset ,m_igs_palette32[offset]);
151	151	}
152	152
153	153
r14845	r14846
197	197	AM_RANGE(0x10000000, 0x100003ff) AM_RAM AM_BASE(m_igs_mainram)// main ram for asic?
198	198	AM_RANGE(0x18000000, 0x18007fff) AM_RAM
199	199
200		AM_RANGE(0x38001000, 0x380017ff) AM_RAM_WRITE_LEGACY(igs_cg_videoram_w) AM_BASE(m_igs_cg_videoram)      //0x200 * 1   CG PALETTE?
201		AM_RANGE(0x38001800, 0x38001fff) AM_RAM_WRITE_LEGACY(igs_palette32_w) AM_BASE(m_igs_palette32)      //0x200 * 1
	200	AM_RANGE(0x38001000, 0x380017ff) AM_RAM_WRITE(igs_cg_videoram_w) AM_BASE(m_igs_cg_videoram)      //0x200 * 1   CG PALETTE?
	201	AM_RANGE(0x38001800, 0x38001fff) AM_RAM_WRITE(igs_palette32_w) AM_BASE(m_igs_palette32)      //0x200 * 1
202	202
203		AM_RANGE(0x38004000, 0x38005FFF) AM_RAM_WRITE_LEGACY(igs_tx_videoram_w) AM_BASE(m_igs_tx_videoram) /* Text Layer */
204		AM_RANGE(0x38006000, 0x38007FFF) AM_RAM_WRITE_LEGACY(igs_bg_videoram_w) AM_BASE(m_igs_bg_videoram) /* CG Layer */
	203	AM_RANGE(0x38004000, 0x38005FFF) AM_RAM_WRITE(igs_tx_videoram_w) AM_BASE(m_igs_tx_videoram) /* Text Layer */
	204	AM_RANGE(0x38006000, 0x38007FFF) AM_RAM_WRITE(igs_bg_videoram_w) AM_BASE(m_igs_bg_videoram) /* CG Layer */
205	205
206	206
207	207	AM_RANGE(0x38002010, 0x38002017) AM_RAM      //??????????????

src/mame/drivers/subsino2.c

r14845	r14846
96	96	UINT8 *m_am188em_regs;
97	97	UINT16 m_bishjan_sel;
98	98	UINT16 m_bishjan_input;
	99	DECLARE_WRITE8_MEMBER(ss9601_byte_lo_w);
	100	DECLARE_WRITE8_MEMBER(ss9601_byte_lo2_w);
	101	DECLARE_WRITE8_MEMBER(ss9601_videoram_0_hi_w);
	102	DECLARE_WRITE8_MEMBER(ss9601_videoram_0_lo_w);
	103	DECLARE_WRITE8_MEMBER(ss9601_videoram_0_hi_lo_w);
	104	DECLARE_WRITE8_MEMBER(ss9601_videoram_0_hi_lo2_w);
	105	DECLARE_READ8_MEMBER(ss9601_videoram_0_hi_r);
	106	DECLARE_READ8_MEMBER(ss9601_videoram_0_lo_r);
	107	DECLARE_WRITE8_MEMBER(ss9601_videoram_1_hi_w);
	108	DECLARE_WRITE8_MEMBER(ss9601_videoram_1_lo_w);
	109	DECLARE_WRITE8_MEMBER(ss9601_videoram_1_hi_lo_w);
	110	DECLARE_WRITE8_MEMBER(ss9601_videoram_1_hi_lo2_w);
	111	DECLARE_READ8_MEMBER(ss9601_videoram_1_hi_r);
	112	DECLARE_READ8_MEMBER(ss9601_videoram_1_lo_r);
	113	DECLARE_WRITE8_MEMBER(ss9601_reelram_hi_lo_w);
	114	DECLARE_READ8_MEMBER(ss9601_reelram_hi_r);
	115	DECLARE_READ8_MEMBER(ss9601_reelram_lo_r);
	116	DECLARE_WRITE8_MEMBER(ss9601_scrollctrl_w);
	117	DECLARE_WRITE8_MEMBER(ss9601_tilesize_w);
	118	DECLARE_WRITE8_MEMBER(ss9601_scroll_w);
	119	DECLARE_WRITE8_MEMBER(ss9601_scrollram_0_hi_w);
	120	DECLARE_WRITE8_MEMBER(ss9601_scrollram_0_lo_w);
	121	DECLARE_WRITE8_MEMBER(ss9601_scrollram_0_hi_lo_w);
	122	DECLARE_READ8_MEMBER(ss9601_scrollram_0_hi_r);
	123	DECLARE_READ8_MEMBER(ss9601_scrollram_0_lo_r);
	124	DECLARE_WRITE8_MEMBER(ss9601_scrollram_1_hi_w);
	125	DECLARE_WRITE8_MEMBER(ss9601_scrollram_1_lo_w);
	126	DECLARE_WRITE8_MEMBER(ss9601_scrollram_1_hi_lo_w);
	127	DECLARE_READ8_MEMBER(ss9601_scrollram_1_hi_r);
	128	DECLARE_READ8_MEMBER(ss9601_scrollram_1_lo_r);
	129	DECLARE_WRITE8_MEMBER(ss9601_disable_w);
	130	DECLARE_WRITE8_MEMBER(hm86171_colorram_w);
	131	DECLARE_WRITE8_MEMBER(dsw_mask_w);
	132	DECLARE_READ8_MEMBER(dsw_r);
	133	DECLARE_READ8_MEMBER(vblank_bit2_r);
	134	DECLARE_READ8_MEMBER(vblank_bit6_r);
	135	DECLARE_READ8_MEMBER(am188em_regs_r);
	136	DECLARE_WRITE8_MEMBER(am188em_regs_w);
	137	DECLARE_WRITE16_MEMBER(bishjan_sel_w);
	138	DECLARE_READ16_MEMBER(bishjan_serial_r);
	139	DECLARE_WRITE16_MEMBER(bishjan_input_w);
	140	DECLARE_READ16_MEMBER(bishjan_input_r);
	141	DECLARE_WRITE16_MEMBER(bishjan_outputs_w);
	142	DECLARE_WRITE8_MEMBER(expcard_outputs_w);
	143	DECLARE_WRITE8_MEMBER(mtrain_outputs_w);
	144	DECLARE_WRITE8_MEMBER(mtrain_videoram_w);
	145	DECLARE_WRITE8_MEMBER(mtrain_tilesize_w);
	146	DECLARE_READ8_MEMBER(mtrain_prot_r);
	147	DECLARE_WRITE8_MEMBER(saklove_outputs_w);
	148	DECLARE_WRITE8_MEMBER(xplan_outputs_w);
	149	DECLARE_WRITE8_MEMBER(xtrain_outputs_w);
99	150	};
100	151
101	152
r14845	r14846
133	184	}
134	185
135	186
136		static WRITE8_HANDLER( ss9601_byte_lo_w )
	187	WRITE8_MEMBER(subsino2_state::ss9601_byte_lo_w)
137	188	{
138		subsino2_state *state = space->machine().driver_data<subsino2_state>();
139		state->m_ss9601_byte_lo = data;
	189	m_ss9601_byte_lo = data;
140	190	}
141		static WRITE8_HANDLER( ss9601_byte_lo2_w )
	191	WRITE8_MEMBER(subsino2_state::ss9601_byte_lo2_w)
142	192	{
143		subsino2_state *state = space->machine().driver_data<subsino2_state>();
144		state->m_ss9601_byte_lo2 = data;
	193	m_ss9601_byte_lo2 = data;
145	194	}
146	195
147	196
r14845	r14846
172	221	}
173	222
174	223	// Layer 0
175		static WRITE8_HANDLER( ss9601_videoram_0_hi_w )
	224	WRITE8_MEMBER(subsino2_state::ss9601_videoram_0_hi_w)
176	225	{
177		subsino2_state *state = space->machine().driver_data<subsino2_state>();
178		ss9601_videoram_w(&state->m_layers[0], VRAM_HI, space, offset, data);
	226	ss9601_videoram_w(&m_layers[0], VRAM_HI, &space, offset, data);
179	227	}
180	228
181		static WRITE8_HANDLER( ss9601_videoram_0_lo_w )
	229	WRITE8_MEMBER(subsino2_state::ss9601_videoram_0_lo_w)
182	230	{
183		subsino2_state *state = space->machine().driver_data<subsino2_state>();
184		ss9601_videoram_w(&state->m_layers[0], VRAM_LO, space, offset, data);
	231	ss9601_videoram_w(&m_layers[0], VRAM_LO, &space, offset, data);
185	232	}
186	233
187		static WRITE8_HANDLER( ss9601_videoram_0_hi_lo_w )
	234	WRITE8_MEMBER(subsino2_state::ss9601_videoram_0_hi_lo_w)
188	235	{
189		subsino2_state *state = space->machine().driver_data<subsino2_state>();
190		ss9601_videoram_w(&state->m_layers[0], VRAM_HI, space, offset, data);
191		ss9601_videoram_w(&state->m_layers[0], VRAM_LO, space, offset, state->m_ss9601_byte_lo);
	236	ss9601_videoram_w(&m_layers[0], VRAM_HI, &space, offset, data);
	237	ss9601_videoram_w(&m_layers[0], VRAM_LO, &space, offset, m_ss9601_byte_lo);
192	238	}
193	239
194		static WRITE8_HANDLER( ss9601_videoram_0_hi_lo2_w )
	240	WRITE8_MEMBER(subsino2_state::ss9601_videoram_0_hi_lo2_w)
195	241	{
196		subsino2_state *state = space->machine().driver_data<subsino2_state>();
197		ss9601_videoram_w(&state->m_layers[0], VRAM_HI, space, offset, data);
198		ss9601_videoram_w(&state->m_layers[0], VRAM_LO, space, offset, state->m_ss9601_byte_lo2);
	242	ss9601_videoram_w(&m_layers[0], VRAM_HI, &space, offset, data);
	243	ss9601_videoram_w(&m_layers[0], VRAM_LO, &space, offset, m_ss9601_byte_lo2);
199	244	}
200	245
201		static READ8_HANDLER( ss9601_videoram_0_hi_r )
	246	READ8_MEMBER(subsino2_state::ss9601_videoram_0_hi_r)
202	247	{
203		subsino2_state *state = space->machine().driver_data<subsino2_state>();
204		return state->m_layers[0].videorams[VRAM_HI][offset];
	248	return m_layers[0].videorams[VRAM_HI][offset];
205	249	}
206	250
207		static READ8_HANDLER( ss9601_videoram_0_lo_r )
	251	READ8_MEMBER(subsino2_state::ss9601_videoram_0_lo_r)
208	252	{
209		subsino2_state *state = space->machine().driver_data<subsino2_state>();
210		return state->m_layers[0].videorams[VRAM_LO][offset];
	253	return m_layers[0].videorams[VRAM_LO][offset];
211	254	}
212	255
213	256	// Layer 1
214		static WRITE8_HANDLER( ss9601_videoram_1_hi_w )
	257	WRITE8_MEMBER(subsino2_state::ss9601_videoram_1_hi_w)
215	258	{
216		subsino2_state *state = space->machine().driver_data<subsino2_state>();
217		ss9601_videoram_w(&state->m_layers[1], VRAM_HI, space, offset, data);
	259	ss9601_videoram_w(&m_layers[1], VRAM_HI, &space, offset, data);
218	260	}
219	261
220		static WRITE8_HANDLER( ss9601_videoram_1_lo_w )
	262	WRITE8_MEMBER(subsino2_state::ss9601_videoram_1_lo_w)
221	263	{
222		subsino2_state *state = space->machine().driver_data<subsino2_state>();
223		ss9601_videoram_w(&state->m_layers[1], VRAM_LO, space, offset, data);
	264	ss9601_videoram_w(&m_layers[1], VRAM_LO, &space, offset, data);
224	265	}
225	266
226		static WRITE8_HANDLER( ss9601_videoram_1_hi_lo_w )
	267	WRITE8_MEMBER(subsino2_state::ss9601_videoram_1_hi_lo_w)
227	268	{
228		subsino2_state *state = space->machine().driver_data<subsino2_state>();
229		ss9601_videoram_w(&state->m_layers[1], VRAM_HI, space, offset, data);
230		ss9601_videoram_w(&state->m_layers[1], VRAM_LO, space, offset, state->m_ss9601_byte_lo);
	269	ss9601_videoram_w(&m_layers[1], VRAM_HI, &space, offset, data);
	270	ss9601_videoram_w(&m_layers[1], VRAM_LO, &space, offset, m_ss9601_byte_lo);
231	271	}
232	272
233		static WRITE8_HANDLER( ss9601_videoram_1_hi_lo2_w )
	273	WRITE8_MEMBER(subsino2_state::ss9601_videoram_1_hi_lo2_w)
234	274	{
235		subsino2_state *state = space->machine().driver_data<subsino2_state>();
236		ss9601_videoram_w(&state->m_layers[1], VRAM_HI, space, offset, data);
237		ss9601_videoram_w(&state->m_layers[1], VRAM_LO, space, offset, state->m_ss9601_byte_lo2);
	275	ss9601_videoram_w(&m_layers[1], VRAM_HI, &space, offset, data);
	276	ss9601_videoram_w(&m_layers[1], VRAM_LO, &space, offset, m_ss9601_byte_lo2);
238	277	}
239	278
240		static READ8_HANDLER( ss9601_videoram_1_hi_r )
	279	READ8_MEMBER(subsino2_state::ss9601_videoram_1_hi_r)
241	280	{
242		subsino2_state *state = space->machine().driver_data<subsino2_state>();
243		return state->m_layers[1].videorams[VRAM_HI][offset];
	281	return m_layers[1].videorams[VRAM_HI][offset];
244	282	}
245	283
246		static READ8_HANDLER( ss9601_videoram_1_lo_r )
	284	READ8_MEMBER(subsino2_state::ss9601_videoram_1_lo_r)
247	285	{
248		subsino2_state *state = space->machine().driver_data<subsino2_state>();
249		return state->m_layers[1].videorams[VRAM_LO][offset];
	286	return m_layers[1].videorams[VRAM_LO][offset];
250	287	}
251	288
252	289	// Layer 0 Reels
253	290
254		static WRITE8_HANDLER( ss9601_reelram_hi_lo_w )
	291	WRITE8_MEMBER(subsino2_state::ss9601_reelram_hi_lo_w)
255	292	{
256		subsino2_state *state = space->machine().driver_data<subsino2_state>();
257		state->m_ss9601_reelrams[VRAM_HI][offset] = data;
258		state->m_ss9601_reelrams[VRAM_LO][offset] = state->m_ss9601_byte_lo;
	293	m_ss9601_reelrams[VRAM_HI][offset] = data;
	294	m_ss9601_reelrams[VRAM_LO][offset] = m_ss9601_byte_lo;
259	295	}
260		static READ8_HANDLER( ss9601_reelram_hi_r )
	296	READ8_MEMBER(subsino2_state::ss9601_reelram_hi_r)
261	297	{
262		subsino2_state *state = space->machine().driver_data<subsino2_state>();
263		return state->m_ss9601_reelrams[VRAM_HI][offset];
	298	return m_ss9601_reelrams[VRAM_HI][offset];
264	299	}
265		static READ8_HANDLER( ss9601_reelram_lo_r )
	300	READ8_MEMBER(subsino2_state::ss9601_reelram_lo_r)
266	301	{
267		subsino2_state *state = space->machine().driver_data<subsino2_state>();
268		return state->m_ss9601_reelrams[VRAM_LO][offset];
	302	return m_ss9601_reelrams[VRAM_LO][offset];
269	303	}
270	304
271	305
r14845	r14846
374	408
375	409	// These are written in sequence
376	410
377		static WRITE8_HANDLER( ss9601_scrollctrl_w )
	411	WRITE8_MEMBER(subsino2_state::ss9601_scrollctrl_w)
378	412	{
379		subsino2_state *state = space->machine().driver_data<subsino2_state>();
380		state->m_ss9601_scrollctrl = data;
	413	m_ss9601_scrollctrl = data;
381	414	}
382	415
383		static WRITE8_HANDLER( ss9601_tilesize_w )
	416	WRITE8_MEMBER(subsino2_state::ss9601_tilesize_w)
384	417	{
385		subsino2_state *state = space->machine().driver_data<subsino2_state>();
386		state->m_ss9601_tilesize = data;
	418	m_ss9601_tilesize = data;
387	419
388	420	tilesize_t sizes[2];
389	421	switch (data)
r14845	r14846
407	439	sizes[0] = TILE_8x8;
408	440	sizes[1] = TILE_8x8;
409	441
410		logerror("%s: warning, unknown tilesize = %02x\n", space->machine().describe_context(), data);
	442	logerror("%s: warning, unknown tilesize = %02x\n", machine().describe_context(), data);
411	443	popmessage("UNKNOWN TILESIZE %02X", data);
412	444	break;
413	445	}
414	446
415	447	for (int i = 0; i < 2; i++)
416	448	{
417		layer_t *l = &state->m_layers[i];
	449	layer_t *l = &m_layers[i];
418	450
419	451	if (l->tilesize != sizes[i])
420	452	{
r14845	r14846
428	460	Tilemaps Scroll
429	461	***************************************************************************/
430	462
431		static WRITE8_HANDLER( ss9601_scroll_w )
	463	WRITE8_MEMBER(subsino2_state::ss9601_scroll_w)
432	464	{
433		subsino2_state *state = space->machine().driver_data<subsino2_state>();
434		layer_t *layers = state->m_layers;
	465	layer_t *layers = m_layers;
435	466	switch ( offset )
436	467	{
437	468	// Layer 0
r14845	r14846
449	480	}
450	481
451	482	// Layer 0
452		static WRITE8_HANDLER( ss9601_scrollram_0_hi_w )
	483	WRITE8_MEMBER(subsino2_state::ss9601_scrollram_0_hi_w)
453	484	{
454		subsino2_state *state = space->machine().driver_data<subsino2_state>();
455		state->m_layers[0].scrollrams[VRAM_HI][offset] = data;
	485	m_layers[0].scrollrams[VRAM_HI][offset] = data;
456	486	}
457	487
458		static WRITE8_HANDLER( ss9601_scrollram_0_lo_w )
	488	WRITE8_MEMBER(subsino2_state::ss9601_scrollram_0_lo_w)
459	489	{
460		subsino2_state *state = space->machine().driver_data<subsino2_state>();
461		state->m_layers[0].scrollrams[VRAM_LO][offset] = data;
	490	m_layers[0].scrollrams[VRAM_LO][offset] = data;
462	491	}
463	492
464		static WRITE8_HANDLER( ss9601_scrollram_0_hi_lo_w )
	493	WRITE8_MEMBER(subsino2_state::ss9601_scrollram_0_hi_lo_w)
465	494	{
466		subsino2_state *state = space->machine().driver_data<subsino2_state>();
467		state->m_layers[0].scrollrams[VRAM_HI][offset] = data;
468		state->m_layers[0].scrollrams[VRAM_LO][offset] = state->m_ss9601_byte_lo;
	495	m_layers[0].scrollrams[VRAM_HI][offset] = data;
	496	m_layers[0].scrollrams[VRAM_LO][offset] = m_ss9601_byte_lo;
469	497	}
470	498
471		static READ8_HANDLER ( ss9601_scrollram_0_hi_r )
	499	READ8_MEMBER(subsino2_state::ss9601_scrollram_0_hi_r)
472	500	{
473		subsino2_state *state = space->machine().driver_data<subsino2_state>();
474		return state->m_layers[0].scrollrams[VRAM_HI][offset];
	501	return m_layers[0].scrollrams[VRAM_HI][offset];
475	502	}
476	503
477		static READ8_HANDLER ( ss9601_scrollram_0_lo_r )
	504	READ8_MEMBER(subsino2_state::ss9601_scrollram_0_lo_r)
478	505	{
479		subsino2_state *state = space->machine().driver_data<subsino2_state>();
480		return state->m_layers[0].scrollrams[VRAM_LO][offset];
	506	return m_layers[0].scrollrams[VRAM_LO][offset];
481	507	}
482	508
483	509	// Layer 1
484		static WRITE8_HANDLER( ss9601_scrollram_1_hi_w )
	510	WRITE8_MEMBER(subsino2_state::ss9601_scrollram_1_hi_w)
485	511	{
486		subsino2_state *state = space->machine().driver_data<subsino2_state>();
487		state->m_layers[1].scrollrams[VRAM_HI][offset] = data;
	512	m_layers[1].scrollrams[VRAM_HI][offset] = data;
488	513	}
489	514
490		static WRITE8_HANDLER( ss9601_scrollram_1_lo_w )
	515	WRITE8_MEMBER(subsino2_state::ss9601_scrollram_1_lo_w)
491	516	{
492		subsino2_state *state = space->machine().driver_data<subsino2_state>();
493		state->m_layers[1].scrollrams[VRAM_LO][offset] = data;
	517	m_layers[1].scrollrams[VRAM_LO][offset] = data;
494	518	}
495	519
496		static WRITE8_HANDLER( ss9601_scrollram_1_hi_lo_w )
	520	WRITE8_MEMBER(subsino2_state::ss9601_scrollram_1_hi_lo_w)
497	521	{
498		subsino2_state *state = space->machine().driver_data<subsino2_state>();
499		state->m_layers[1].scrollrams[VRAM_HI][offset] = data;
500		state->m_layers[1].scrollrams[VRAM_LO][offset] = state->m_ss9601_byte_lo;
	522	m_layers[1].scrollrams[VRAM_HI][offset] = data;
	523	m_layers[1].scrollrams[VRAM_LO][offset] = m_ss9601_byte_lo;
501	524	}
502	525
503		static READ8_HANDLER ( ss9601_scrollram_1_hi_r )
	526	READ8_MEMBER(subsino2_state::ss9601_scrollram_1_hi_r)
504	527	{
505		subsino2_state *state = space->machine().driver_data<subsino2_state>();
506		return state->m_layers[1].scrollrams[VRAM_HI][offset];
	528	return m_layers[1].scrollrams[VRAM_HI][offset];
507	529	}
508	530
509		static READ8_HANDLER ( ss9601_scrollram_1_lo_r )
	531	READ8_MEMBER(subsino2_state::ss9601_scrollram_1_lo_r)
510	532	{
511		subsino2_state *state = space->machine().driver_data<subsino2_state>();
512		return state->m_layers[1].scrollrams[VRAM_LO][offset];
	533	return m_layers[1].scrollrams[VRAM_LO][offset];
513	534	}
514	535
515	536
r14845	r14846
517	538	Tilemaps Disable
518	539	***************************************************************************/
519	540
520		static WRITE8_HANDLER( ss9601_disable_w )
	541	WRITE8_MEMBER(subsino2_state::ss9601_disable_w)
521	542	{
522		subsino2_state *state = space->machine().driver_data<subsino2_state>();
523		state->m_ss9601_disable = data;
	543	m_ss9601_disable = data;
524	544	}
525	545
526	546
r14845	r14846
724	744	***************************************************************************/
725	745
726	746
727		static WRITE8_HANDLER( hm86171_colorram_w )
	747	WRITE8_MEMBER(subsino2_state::hm86171_colorram_w)
728	748	{
729		subsino2_state *state = space->machine().driver_data<subsino2_state>();
730	749	switch (offset)
731	750	{
732	751	case 0:
733		state->m_hm86171_offs = data * 3;
	752	m_hm86171_offs = data * 3;
734	753	break;
735	754
736	755	case 1:
737		state->m_hm86171_colorram[state->m_hm86171_offs] = data;
738		palette_set_color_rgb(space->machine(), state->m_hm86171_offs/3,
739		pal6bit(state->m_hm86171_colorram[(state->m_hm86171_offs/3)*3+0]),
740		pal6bit(state->m_hm86171_colorram[(state->m_hm86171_offs/3)*3+1]),
741		pal6bit(state->m_hm86171_colorram[(state->m_hm86171_offs/3)*3+2])
	756	m_hm86171_colorram[m_hm86171_offs] = data;
	757	palette_set_color_rgb(machine(), m_hm86171_offs/3,
	758	pal6bit(m_hm86171_colorram[(m_hm86171_offs/3)*3+0]),
	759	pal6bit(m_hm86171_colorram[(m_hm86171_offs/3)*3+1]),
	760	pal6bit(m_hm86171_colorram[(m_hm86171_offs/3)*3+2])
742	761	);
743		state->m_hm86171_offs = (state->m_hm86171_offs+1) % (256*3);
	762	m_hm86171_offs = (m_hm86171_offs+1) % (256*3);
744	763	break;
745	764
746	765	case 2:
r14845	r14846
757	776	Input / Output
758	777	***************************************************************************/
759	778
760		static WRITE8_HANDLER( dsw_mask_w )
	779	WRITE8_MEMBER(subsino2_state::dsw_mask_w)
761	780	{
762		subsino2_state *state = space->machine().driver_data<subsino2_state>();
763		state->m_dsw_mask = data;
	781	m_dsw_mask = data;
764	782	}
765	783
766		static READ8_HANDLER( dsw_r )
	784	READ8_MEMBER(subsino2_state::dsw_r)
767	785	{
768		subsino2_state *state = space->machine().driver_data<subsino2_state>();
769		return   ( (input_port_read(space->machine(), "DSW1") & state->m_dsw_mask) ? 0x01 : 0 ) |
770		( (input_port_read(space->machine(), "DSW2") & state->m_dsw_mask) ? 0x02 : 0 ) |
771		( (input_port_read(space->machine(), "DSW3") & state->m_dsw_mask) ? 0x04 : 0 ) |
772		( (input_port_read(space->machine(), "DSW4") & state->m_dsw_mask) ? 0x08 : 0 ) ;
	786	return   ( (input_port_read(machine(), "DSW1") & m_dsw_mask) ? 0x01 : 0 ) |
	787	( (input_port_read(machine(), "DSW2") & m_dsw_mask) ? 0x02 : 0 ) |
	788	( (input_port_read(machine(), "DSW3") & m_dsw_mask) ? 0x04 : 0 ) |
	789	( (input_port_read(machine(), "DSW4") & m_dsw_mask) ? 0x08 : 0 ) ;
773	790	}
774	791
775	792
776		static READ8_HANDLER( vblank_bit2_r )
	793	READ8_MEMBER(subsino2_state::vblank_bit2_r)
777	794	{
778		return space->machine().primary_screen->vblank() ? 0x04 : 0x00;
	795	return machine().primary_screen->vblank() ? 0x04 : 0x00;
779	796	}
780		static READ8_HANDLER( vblank_bit6_r )
	797	READ8_MEMBER(subsino2_state::vblank_bit6_r)
781	798	{
782		return space->machine().primary_screen->vblank() ? 0x40 : 0x00;
	799	return machine().primary_screen->vblank() ? 0x40 : 0x00;
783	800	}
784	801
785	802	static WRITE8_DEVICE_HANDLER( oki_bank_bit0_w )
r14845	r14846
810	827	AM188EM_I0CON = 0x38
811	828	};
812	829
813		static READ8_HANDLER( am188em_regs_r )
	830	READ8_MEMBER(subsino2_state::am188em_regs_r)
814	831	{
815		subsino2_state *state = space->machine().driver_data<subsino2_state>();
816		return state->m_am188em_regs[offset];
	832	return m_am188em_regs[offset];
817	833	}
818	834
819		static WRITE8_HANDLER( am188em_regs_w )
	835	WRITE8_MEMBER(subsino2_state::am188em_regs_w)
820	836	{
821		subsino2_state *state = space->machine().driver_data<subsino2_state>();
822		state->m_am188em_regs[offset] = data;
	837	m_am188em_regs[offset] = data;
823	838	}
824	839
825	840	static MACHINE_RESET( am188em )
r14845	r14846
867	882	***************************************************************************/
868	883
869	884
870		static WRITE16_HANDLER( bishjan_sel_w )
	885	WRITE16_MEMBER(subsino2_state::bishjan_sel_w)
871	886	{
872		subsino2_state *state = space->machine().driver_data<subsino2_state>();
873	887	if (ACCESSING_BITS_8_15)
874		state->m_bishjan_sel = data >> 8;
	888	m_bishjan_sel = data >> 8;
875	889	}
876	890
877		static READ16_HANDLER( bishjan_serial_r )
	891	READ16_MEMBER(subsino2_state::bishjan_serial_r)
878	892	{
879		subsino2_state *state = space->machine().driver_data<subsino2_state>();
880	893	return
881		(space->machine().rand() & 0x9800)   |   // bit 7 - serial communication
882		(((state->m_bishjan_sel==0x12) ? 0x40:0x00) << 8) |
	894	(machine().rand() & 0x9800)   |   // bit 7 - serial communication
	895	(((m_bishjan_sel==0x12) ? 0x40:0x00) << 8) |
883	896	//      (machine.rand() & 0xff);
884		//      (((space->machine().primary_screen->frame_number()%60)==0)?0x18:0x00);
	897	//      (((machine().primary_screen->frame_number()%60)==0)?0x18:0x00);
885	898	0x18;
886	899	}
887	900
888		static WRITE16_HANDLER( bishjan_input_w )
	901	WRITE16_MEMBER(subsino2_state::bishjan_input_w)
889	902	{
890		subsino2_state *state = space->machine().driver_data<subsino2_state>();
891	903	if (ACCESSING_BITS_8_15)
892		state->m_bishjan_input = data >> 8;
	904	m_bishjan_input = data >> 8;
893	905	}
894	906
895		static READ16_HANDLER( bishjan_input_r )
	907	READ16_MEMBER(subsino2_state::bishjan_input_r)
896	908	{
897		subsino2_state *state = space->machine().driver_data<subsino2_state>();
898	909	int i;
899	910	UINT16 res = 0xff;
900	911	static const char *const port[] = { "KEYB_0", "KEYB_1", "KEYB_2", "KEYB_3", "KEYB_4" };
901	912
902	913	for (i = 0; i < 5; i++)
903		if (state->m_bishjan_input & (1 << i))
904		res = input_port_read(space->machine(), port[i]);
	914	if (m_bishjan_input & (1 << i))
	915	res = input_port_read(machine(), port[i]);
905	916
906	917	return   (res << 8) |                           // high byte
907		input_port_read(space->machine(), "SYSTEM") |      // low byte
908		(ticket_dispenser_r(space->machine().device("hopper"), 0) ? 0x00 : 0x04)   // bit 2: hopper sensor
	918	input_port_read(machine(), "SYSTEM") |      // low byte
	919	(ticket_dispenser_r(machine().device("hopper"), 0) ? 0x00 : 0x04)   // bit 2: hopper sensor
909	920	;
910	921	}
911	922
912		static WRITE16_HANDLER( bishjan_outputs_w )
	923	WRITE16_MEMBER(subsino2_state::bishjan_outputs_w)
913	924	{
914		subsino2_state *state = space->machine().driver_data<subsino2_state>();
915		state->m_outputs16[offset] = data;
	925	m_outputs16[offset] = data;
916	926
917	927	switch (offset)
918	928	{
r14845	r14846
920	930	if (ACCESSING_BITS_0_7)
921	931	{
922	932	// coin out         data & 0x01;
923		ticket_dispenser_w(space->machine().device("hopper"), 0, (data & 0x0002) ? 0x80 : 0);   // hopper
924		coin_counter_w(space->machine(), 0,   data & 0x0010 );
	933	ticket_dispenser_w(machine().device("hopper"), 0, (data & 0x0002) ? 0x80 : 0);   // hopper
	934	coin_counter_w(machine(), 0,   data & 0x0010 );
925	935	}
926	936	break;
927	937	}
928	938
929		//  popmessage("0: %04x", state->m_outputs16[0]);
	939	//  popmessage("0: %04x", m_outputs16[0]);
930	940	}
931	941
932	942
r14845	r14846
939	949	AM_RANGE( 0x200000, 0x207fff ) AM_RAM AM_SHARE("nvram")   // battery
940	950
941	951	// read lo (L1)   (only half tilemap?)
942		AM_RANGE( 0x412000, 0x412fff ) AM_READ8_LEGACY(ss9601_videoram_1_lo_r, 0xffff )
943		AM_RANGE( 0x413000, 0x4131ff ) AM_READWRITE8_LEGACY(ss9601_scrollram_1_lo_r, ss9601_scrollram_1_lo_w, 0xffff )
	952	AM_RANGE( 0x412000, 0x412fff ) AM_READ8(ss9601_videoram_1_lo_r, 0xffff )
	953	AM_RANGE( 0x413000, 0x4131ff ) AM_READWRITE8(ss9601_scrollram_1_lo_r, ss9601_scrollram_1_lo_w, 0xffff )
944	954	// read lo (REEL)
945		AM_RANGE( 0x416000, 0x416fff ) AM_READ8_LEGACY(ss9601_reelram_lo_r, 0xffff )
946		AM_RANGE( 0x417000, 0x4171ff ) AM_READWRITE8_LEGACY(ss9601_scrollram_0_lo_r, ss9601_scrollram_0_lo_w, 0xffff )
	955	AM_RANGE( 0x416000, 0x416fff ) AM_READ8(ss9601_reelram_lo_r, 0xffff )
	956	AM_RANGE( 0x417000, 0x4171ff ) AM_READWRITE8(ss9601_scrollram_0_lo_r, ss9601_scrollram_0_lo_w, 0xffff )
947	957
948	958	// read hi (L1)
949		AM_RANGE( 0x422000, 0x422fff ) AM_READ8_LEGACY(ss9601_videoram_1_hi_r, 0xffff )
950		AM_RANGE( 0x423000, 0x4231ff ) AM_READWRITE8_LEGACY(ss9601_scrollram_1_hi_r, ss9601_scrollram_1_hi_w, 0xffff )
	959	AM_RANGE( 0x422000, 0x422fff ) AM_READ8(ss9601_videoram_1_hi_r, 0xffff )
	960	AM_RANGE( 0x423000, 0x4231ff ) AM_READWRITE8(ss9601_scrollram_1_hi_r, ss9601_scrollram_1_hi_w, 0xffff )
951	961	// read hi (REEL)
952		AM_RANGE( 0x426000, 0x426fff ) AM_READ8_LEGACY(ss9601_reelram_hi_r, 0xffff )
953		AM_RANGE( 0x427000, 0x4271ff ) AM_READWRITE8_LEGACY(ss9601_scrollram_0_hi_r, ss9601_scrollram_0_hi_w, 0xffff )
	962	AM_RANGE( 0x426000, 0x426fff ) AM_READ8(ss9601_reelram_hi_r, 0xffff )
	963	AM_RANGE( 0x427000, 0x4271ff ) AM_READWRITE8(ss9601_scrollram_0_hi_r, ss9601_scrollram_0_hi_w, 0xffff )
954	964
955	965	// write both (L1)
956		AM_RANGE( 0x430000, 0x431fff ) AM_WRITE8_LEGACY(ss9601_videoram_1_hi_lo_w, 0xffff )
957		AM_RANGE( 0x432000, 0x432fff ) AM_WRITE8_LEGACY(ss9601_videoram_1_hi_lo_w, 0xffff )
958		AM_RANGE( 0x433000, 0x4331ff ) AM_WRITE8_LEGACY(ss9601_scrollram_1_hi_lo_w, 0xffff )
	966	AM_RANGE( 0x430000, 0x431fff ) AM_WRITE8(ss9601_videoram_1_hi_lo_w, 0xffff )
	967	AM_RANGE( 0x432000, 0x432fff ) AM_WRITE8(ss9601_videoram_1_hi_lo_w, 0xffff )
	968	AM_RANGE( 0x433000, 0x4331ff ) AM_WRITE8(ss9601_scrollram_1_hi_lo_w, 0xffff )
959	969	// write both (L0 & REEL)
960		AM_RANGE( 0x434000, 0x435fff ) AM_WRITE8_LEGACY(ss9601_videoram_0_hi_lo_w, 0xffff )
961		AM_RANGE( 0x436000, 0x436fff ) AM_WRITE8_LEGACY(ss9601_reelram_hi_lo_w, 0xffff )
962		AM_RANGE( 0x437000, 0x4371ff ) AM_WRITE8_LEGACY(ss9601_scrollram_0_hi_lo_w, 0xffff )
	970	AM_RANGE( 0x434000, 0x435fff ) AM_WRITE8(ss9601_videoram_0_hi_lo_w, 0xffff )
	971	AM_RANGE( 0x436000, 0x436fff ) AM_WRITE8(ss9601_reelram_hi_lo_w, 0xffff )
	972	AM_RANGE( 0x437000, 0x4371ff ) AM_WRITE8(ss9601_scrollram_0_hi_lo_w, 0xffff )
963	973
964		AM_RANGE( 0x600000, 0x600001 ) AM_READNOP AM_WRITE_LEGACY(bishjan_sel_w )
965		AM_RANGE( 0x600040, 0x600041 ) AM_WRITE8_LEGACY(ss9601_scrollctrl_w, 0xff00 )
966		AM_RANGE( 0x600060, 0x600063 ) AM_WRITE8_LEGACY(hm86171_colorram_w, 0xffff )
967		AM_RANGE( 0x600080, 0x600081 ) AM_WRITE8_LEGACY(ss9601_tilesize_w, 0xff00 )
968		AM_RANGE( 0x6000a0, 0x6000a1 ) AM_WRITE8_LEGACY(ss9601_byte_lo_w, 0xff00 )
	974	AM_RANGE( 0x600000, 0x600001 ) AM_READNOP AM_WRITE(bishjan_sel_w )
	975	AM_RANGE( 0x600040, 0x600041 ) AM_WRITE8(ss9601_scrollctrl_w, 0xff00 )
	976	AM_RANGE( 0x600060, 0x600063 ) AM_WRITE8(hm86171_colorram_w, 0xffff )
	977	AM_RANGE( 0x600080, 0x600081 ) AM_WRITE8(ss9601_tilesize_w, 0xff00 )
	978	AM_RANGE( 0x6000a0, 0x6000a1 ) AM_WRITE8(ss9601_byte_lo_w, 0xff00 )
969	979
970		AM_RANGE( 0xa0001e, 0xa0001f ) AM_WRITE8_LEGACY(ss9601_disable_w, 0x00ff )
	980	AM_RANGE( 0xa0001e, 0xa0001f ) AM_WRITE8(ss9601_disable_w, 0x00ff )
971	981
972		AM_RANGE( 0xa00020, 0xa00025 ) AM_WRITE8_LEGACY(ss9601_scroll_w, 0xffff )
	982	AM_RANGE( 0xa00020, 0xa00025 ) AM_WRITE8(ss9601_scroll_w, 0xffff )
973	983
974	984	AM_RANGE( 0xc00000, 0xc00001 ) AM_READ_PORT("DSW")                        // SW1
975		AM_RANGE( 0xc00002, 0xc00003 ) AM_READ_PORT("JOY") AM_WRITE_LEGACY(bishjan_input_w )   // IN C
976		AM_RANGE( 0xc00004, 0xc00005 ) AM_READ_LEGACY(bishjan_input_r )                  // IN A & B
977		AM_RANGE( 0xc00006, 0xc00007 ) AM_READ_LEGACY(bishjan_serial_r )                  // IN D
978		AM_RANGE( 0xc00008, 0xc00009 ) AM_READ_PORT("RESET") AM_WRITE_LEGACY(bishjan_outputs_w ) AM_BASE(m_outputs16 )
	985	AM_RANGE( 0xc00002, 0xc00003 ) AM_READ_PORT("JOY") AM_WRITE(bishjan_input_w )   // IN C
	986	AM_RANGE( 0xc00004, 0xc00005 ) AM_READ(bishjan_input_r )                  // IN A & B
	987	AM_RANGE( 0xc00006, 0xc00007 ) AM_READ(bishjan_serial_r )                  // IN D
	988	AM_RANGE( 0xc00008, 0xc00009 ) AM_READ_PORT("RESET") AM_WRITE(bishjan_outputs_w ) AM_BASE(m_outputs16 )
979	989	ADDRESS_MAP_END
980	990
981	991	/***************************************************************************
982	992	Express Card / Top Card
983	993	***************************************************************************/
984	994
985		static WRITE8_HANDLER( expcard_outputs_w )
	995	WRITE8_MEMBER(subsino2_state::expcard_outputs_w)
986	996	{
987		subsino2_state *state = space->machine().driver_data<subsino2_state>();
988		state->m_outputs[offset] = data;
	997	m_outputs[offset] = data;
989	998
990	999	switch (offset)
991	1000	{
r14845	r14846
994	1003	break;
995	1004
996	1005	case 1:   // C
997		set_led_status(space->machine(), 0,   data & 0x02);   // raise
	1006	set_led_status(machine(), 0,   data & 0x02);   // raise
998	1007	break;
999	1008
1000	1009	case 2:   // B
1001		set_led_status(space->machine(), 1,   data & 0x04);   // hold 4 / small & hold 5 / big ?
1002		set_led_status(space->machine(), 2,   data & 0x08);   // hold 1 / bet
1003		set_led_status(space->machine(), 3,   data & 0x10);   // hold 2 / take ?
1004		set_led_status(space->machine(), 4,   data & 0x20);   // hold 3 / double up ?
	1010	set_led_status(machine(), 1,   data & 0x04);   // hold 4 / small & hold 5 / big ?
	1011	set_led_status(machine(), 2,   data & 0x08);   // hold 1 / bet
	1012	set_led_status(machine(), 3,   data & 0x10);   // hold 2 / take ?
	1013	set_led_status(machine(), 4,   data & 0x20);   // hold 3 / double up ?
1005	1014	break;
1006	1015
1007	1016	case 3:   // A
1008		coin_counter_w(space->machine(), 0,   data & 0x01 );   // coin in
1009		coin_counter_w(space->machine(), 1,   data & 0x02 );   // key in
	1017	coin_counter_w(machine(), 0,   data & 0x01 );   // coin in
	1018	coin_counter_w(machine(), 1,   data & 0x02 );   // key in
1010	1019
1011		set_led_status(space->machine(), 5,   data & 0x10);   // start
	1020	set_led_status(machine(), 5,   data & 0x10);   // start
1012	1021	break;
1013	1022	}
1014	1023
1015		//  popmessage("0: %02x - 1: %02x - 2: %02x - 3: %02x", state->m_outputs[0], state->m_outputs[1], state->m_outputs[2], state->m_outputs[3]);
	1024	//  popmessage("0: %02x - 1: %02x - 2: %02x - 3: %02x", m_outputs[0], m_outputs[1], m_outputs[2], m_outputs[3]);
1016	1025	}
1017	1026
1018	1027	/***************************************************************************
1019	1028	Magic Train
1020	1029	***************************************************************************/
1021	1030
1022		static WRITE8_HANDLER( mtrain_outputs_w )
	1031	WRITE8_MEMBER(subsino2_state::mtrain_outputs_w)
1023	1032	{
1024		subsino2_state *state = space->machine().driver_data<subsino2_state>();
1025		state->m_outputs[offset] = data;
	1033	m_outputs[offset] = data;
1026	1034
1027	1035	switch (offset)
1028	1036	{
1029	1037	case 0:
1030		coin_counter_w(space->machine(), 0,   data & 0x01 );   // key in
1031		coin_counter_w(space->machine(), 1,   data & 0x02 );   // coin in
1032		coin_counter_w(space->machine(), 2,   data & 0x10 );   // pay out
1033		//          coin_counter_w(space->machine(), 3,   data & 0x20 );  // hopper motor
	1038	coin_counter_w(machine(), 0,   data & 0x01 );   // key in
	1039	coin_counter_w(machine(), 1,   data & 0x02 );   // coin in
	1040	coin_counter_w(machine(), 2,   data & 0x10 );   // pay out
	1041	//          coin_counter_w(machine(), 3,   data & 0x20 );  // hopper motor
1034	1042	break;
1035	1043
1036	1044	case 1:
1037		set_led_status(space->machine(), 0,   data & 0x01);   // stop reel?
1038		set_led_status(space->machine(), 1,   data & 0x02);   // stop reel? (double or take)
1039		set_led_status(space->machine(), 2,   data & 0x04);   // start all
1040		set_led_status(space->machine(), 3,   data & 0x08);   // bet / stop all
1041		set_led_status(space->machine(), 4,   data & 0x20);   // stop reel? (double or take)
	1045	set_led_status(machine(), 0,   data & 0x01);   // stop reel?
	1046	set_led_status(machine(), 1,   data & 0x02);   // stop reel? (double or take)
	1047	set_led_status(machine(), 2,   data & 0x04);   // start all
	1048	set_led_status(machine(), 3,   data & 0x08);   // bet / stop all
	1049	set_led_status(machine(), 4,   data & 0x20);   // stop reel? (double or take)
1042	1050	break;
1043	1051
1044	1052	case 2:
r14845	r14846
1048	1056	break;
1049	1057	}
1050	1058
1051		//  popmessage("0: %02x - 1: %02x - 2: %02x - 3: %02x", state->m_outputs[0], state->m_outputs[1], state->m_outputs[2], state->m_outputs[3]);
	1059	//  popmessage("0: %02x - 1: %02x - 2: %02x - 3: %02x", m_outputs[0], m_outputs[1], m_outputs[2], m_outputs[3]);
1052	1060	}
1053	1061
1054		static WRITE8_HANDLER( mtrain_videoram_w )
	1062	WRITE8_MEMBER(subsino2_state::mtrain_videoram_w)
1055	1063	{
1056		subsino2_state *state = space->machine().driver_data<subsino2_state>();
1057		vram_t vram = (state->m_ss9601_byte_lo & 0x08) ? VRAM_HI : VRAM_LO;
1058		switch (state->m_ss9601_byte_lo & (~0x08))
	1064	vram_t vram = (m_ss9601_byte_lo & 0x08) ? VRAM_HI : VRAM_LO;
	1065	switch (m_ss9601_byte_lo & (~0x08))
1059	1066	{
1060		case 0x00:   ss9601_videoram_w(&state->m_layers[1], vram, space, offset,        data);
1061		ss9601_videoram_w(&state->m_layers[1], vram, space, offset+0x1000, data);   break;
	1067	case 0x00:   ss9601_videoram_w(&m_layers[1], vram, &space, offset,        data);
	1068	ss9601_videoram_w(&m_layers[1], vram, &space, offset+0x1000, data);   break;
1062	1069
1063		case 0x04:   ss9601_videoram_w(&state->m_layers[0], vram, space, offset,        data);
1064		ss9601_videoram_w(&state->m_layers[0], vram, space, offset+0x1000, data);   break;
	1070	case 0x04:   ss9601_videoram_w(&m_layers[0], vram, &space, offset,        data);
	1071	ss9601_videoram_w(&m_layers[0], vram, &space, offset+0x1000, data);   break;
1065	1072
1066		case 0x06:   state->m_ss9601_reelrams[vram][offset] = data;   break;
	1073	case 0x06:   m_ss9601_reelrams[vram][offset] = data;   break;
1067	1074	}
1068	1075	}
1069	1076
1070		static WRITE8_HANDLER( mtrain_tilesize_w )
	1077	WRITE8_MEMBER(subsino2_state::mtrain_tilesize_w)
1071	1078	{
1072		subsino2_state *state = space->machine().driver_data<subsino2_state>();
1073		state->m_ss9601_tilesize = data;
	1079	m_ss9601_tilesize = data;
1074	1080
1075	1081	tilesize_t sizes[2];
1076	1082	switch (data)
r14845	r14846
1089	1095	sizes[0] = TILE_8x8;
1090	1096	sizes[1] = TILE_8x8;
1091	1097
1092		logerror("%s: warning, unknown tilesize = %02x\n", space->machine().describe_context(), data);
	1098	logerror("%s: warning, unknown tilesize = %02x\n", machine().describe_context(), data);
1093	1099	popmessage("UNKNOWN TILESIZE %02X", data);
1094	1100	break;
1095	1101	}
1096	1102
1097	1103	for (int i = 0; i < 2; i++)
1098	1104	{
1099		layer_t *l = &state->m_layers[i];
	1105	layer_t *l = &m_layers[i];
1100	1106
1101	1107	if (l->tilesize != sizes[i])
1102	1108	{
r14845	r14846
1106	1112	}
1107	1113	}
1108	1114
1109		static READ8_HANDLER( mtrain_prot_r )
	1115	READ8_MEMBER(subsino2_state::mtrain_prot_r)
1110	1116	{
1111	1117	return "SUBSION"[offset];
1112	1118	}
r14845	r14846
1116	1122
1117	1123	AM_RANGE( 0x07800, 0x07fff ) AM_RAM AM_SHARE("nvram")   // battery
1118	1124
1119		AM_RANGE( 0x08000, 0x08fff ) AM_WRITE_LEGACY(mtrain_videoram_w )
	1125	AM_RANGE( 0x08000, 0x08fff ) AM_WRITE(mtrain_videoram_w )
1120	1126
1121		AM_RANGE( 0x0911f, 0x0911f ) AM_WRITE_LEGACY(ss9601_disable_w )
1122		AM_RANGE( 0x09120, 0x09125 ) AM_WRITE_LEGACY(ss9601_scroll_w )
	1127	AM_RANGE( 0x0911f, 0x0911f ) AM_WRITE(ss9601_disable_w )
	1128	AM_RANGE( 0x09120, 0x09125 ) AM_WRITE(ss9601_scroll_w )
1123	1129
1124		AM_RANGE( 0x0912f, 0x0912f ) AM_WRITE_LEGACY(ss9601_byte_lo_w )
	1130	AM_RANGE( 0x0912f, 0x0912f ) AM_WRITE(ss9601_byte_lo_w )
1125	1131
1126		AM_RANGE( 0x09140, 0x09142 ) AM_WRITE_LEGACY(mtrain_outputs_w ) AM_BASE(m_outputs )
	1132	AM_RANGE( 0x09140, 0x09142 ) AM_WRITE(mtrain_outputs_w ) AM_BASE(m_outputs )
1127	1133	AM_RANGE( 0x09143, 0x09143 ) AM_READ_PORT( "IN D" )   // (not shown in system test) 0x40 serial out, 0x80 serial in
1128	1134	AM_RANGE( 0x09144, 0x09144 ) AM_READ_PORT( "IN A" )   // A
1129	1135	AM_RANGE( 0x09145, 0x09145 ) AM_READ_PORT( "IN B" )   // B
1130	1136	AM_RANGE( 0x09146, 0x09146 ) AM_READ_PORT( "IN C" )   // C
1131		AM_RANGE( 0x09147, 0x09147 ) AM_READ_LEGACY(dsw_r )
1132		AM_RANGE( 0x09148, 0x09148 ) AM_WRITE_LEGACY(dsw_mask_w )
	1137	AM_RANGE( 0x09147, 0x09147 ) AM_READ(dsw_r )
	1138	AM_RANGE( 0x09148, 0x09148 ) AM_WRITE(dsw_mask_w )
1133	1139
1134		AM_RANGE( 0x09152, 0x09152 ) AM_WRITE_LEGACY(vblank_bit2_r ) AM_DEVWRITE_LEGACY("oki", oki_bank_bit0_w )
	1140	AM_RANGE( 0x09152, 0x09152 ) AM_READ(vblank_bit2_r ) AM_DEVWRITE_LEGACY("oki", oki_bank_bit0_w )
1135	1141
1136		AM_RANGE( 0x09158, 0x0915e ) AM_READ_LEGACY(mtrain_prot_r )
	1142	AM_RANGE( 0x09158, 0x0915e ) AM_READ(mtrain_prot_r )
1137	1143
1138		AM_RANGE( 0x09160, 0x09163 ) AM_WRITE_LEGACY(hm86171_colorram_w )
	1144	AM_RANGE( 0x09160, 0x09163 ) AM_WRITE(hm86171_colorram_w )
1139	1145	AM_RANGE( 0x09164, 0x09164 ) AM_DEVREADWRITE("oki", okim6295_device, read, write)
1140		AM_RANGE( 0x09168, 0x09168 ) AM_WRITE_LEGACY(mtrain_tilesize_w )
	1146	AM_RANGE( 0x09168, 0x09168 ) AM_WRITE(mtrain_tilesize_w )
1141	1147
1142	1148	AM_RANGE( 0x09800, 0x09fff ) AM_RAM
1143	1149
r14845	r14846
1152	1158	Sakura Love - Ying Hua Lian
1153	1159	***************************************************************************/
1154	1160
1155		static WRITE8_HANDLER( saklove_outputs_w )
	1161	WRITE8_MEMBER(subsino2_state::saklove_outputs_w)
1156	1162	{
1157		subsino2_state *state = space->machine().driver_data<subsino2_state>();
1158		state->m_outputs[offset] = data;
	1163	m_outputs[offset] = data;
1159	1164
1160	1165	switch (offset)
1161	1166	{
1162	1167	case 0:
1163		coin_counter_w(space->machine(), 0,   data & 0x01 );   // coin in
1164		coin_counter_w(space->machine(), 1,   data & 0x02 );   // key in
	1168	coin_counter_w(machine(), 0,   data & 0x01 );   // coin in
	1169	coin_counter_w(machine(), 1,   data & 0x02 );   // key in
1165	1170	break;
1166	1171
1167	1172	case 1:
r14845	r14846
1175	1180	break;
1176	1181	}
1177	1182
1178		//  popmessage("0: %02x - 1: %02x - 2: %02x - 3: %02x", state->m_outputs[0], state->m_outputs[1], state->m_outputs[2], state->m_outputs[3]);
	1183	//  popmessage("0: %02x - 1: %02x - 2: %02x - 3: %02x", m_outputs[0], m_outputs[1], m_outputs[2], m_outputs[3]);
1179	1184	}
1180	1185
1181	1186	static ADDRESS_MAP_START( saklove_map, AS_PROGRAM, 8, subsino2_state )
1182	1187	AM_RANGE(0x00000, 0x07fff) AM_RAM AM_SHARE("nvram")   // battery
1183	1188
1184	1189	// read lo (L1)   (only half tilemap?)
1185		AM_RANGE(0x12000, 0x12fff) AM_READWRITE_LEGACY(ss9601_videoram_1_lo_r,  ss9601_videoram_1_lo_w )
1186		AM_RANGE(0x13000, 0x131ff) AM_READWRITE_LEGACY(ss9601_scrollram_1_lo_r, ss9601_scrollram_1_lo_w )
	1190	AM_RANGE(0x12000, 0x12fff) AM_READWRITE(ss9601_videoram_1_lo_r,  ss9601_videoram_1_lo_w )
	1191	AM_RANGE(0x13000, 0x131ff) AM_READWRITE(ss9601_scrollram_1_lo_r, ss9601_scrollram_1_lo_w )
1187	1192	// read lo (L0)
1188		AM_RANGE(0x16000, 0x16fff) AM_READWRITE_LEGACY(ss9601_videoram_0_lo_r,  ss9601_videoram_0_lo_w )
1189		AM_RANGE(0x17000, 0x171ff) AM_READWRITE_LEGACY(ss9601_scrollram_0_lo_r, ss9601_scrollram_0_lo_w )
	1193	AM_RANGE(0x16000, 0x16fff) AM_READWRITE(ss9601_videoram_0_lo_r,  ss9601_videoram_0_lo_w )
	1194	AM_RANGE(0x17000, 0x171ff) AM_READWRITE(ss9601_scrollram_0_lo_r, ss9601_scrollram_0_lo_w )
1190	1195
1191	1196	// read hi (L1)
1192		AM_RANGE(0x22000, 0x22fff) AM_READWRITE_LEGACY(ss9601_videoram_1_hi_r,  ss9601_videoram_1_hi_w )
1193		AM_RANGE(0x23000, 0x231ff) AM_READWRITE_LEGACY(ss9601_scrollram_1_hi_r, ss9601_scrollram_1_hi_w )
	1197	AM_RANGE(0x22000, 0x22fff) AM_READWRITE(ss9601_videoram_1_hi_r,  ss9601_videoram_1_hi_w )
	1198	AM_RANGE(0x23000, 0x231ff) AM_READWRITE(ss9601_scrollram_1_hi_r, ss9601_scrollram_1_hi_w )
1194	1199	// read hi (L0)
1195		AM_RANGE(0x26000, 0x26fff) AM_READWRITE_LEGACY(ss9601_videoram_0_hi_r,  ss9601_videoram_0_hi_w )
1196		AM_RANGE(0x27000, 0x271ff) AM_READWRITE_LEGACY(ss9601_scrollram_0_hi_r, ss9601_scrollram_0_hi_w )
	1200	AM_RANGE(0x26000, 0x26fff) AM_READWRITE(ss9601_videoram_0_hi_r,  ss9601_videoram_0_hi_w )
	1201	AM_RANGE(0x27000, 0x271ff) AM_READWRITE(ss9601_scrollram_0_hi_r, ss9601_scrollram_0_hi_w )
1197	1202
1198	1203	// write both (L1)
1199		AM_RANGE(0x30000, 0x31fff) AM_READWRITE_LEGACY(ss9601_videoram_1_hi_r, ss9601_videoram_1_hi_lo_w )
	1204	AM_RANGE(0x30000, 0x31fff) AM_READWRITE(ss9601_videoram_1_hi_r, ss9601_videoram_1_hi_lo_w )
1200	1205	// write both (L0)
1201		AM_RANGE(0x34000, 0x35fff) AM_READWRITE_LEGACY(ss9601_videoram_0_hi_r, ss9601_videoram_0_hi_lo_w )
	1206	AM_RANGE(0x34000, 0x35fff) AM_READWRITE(ss9601_videoram_0_hi_r, ss9601_videoram_0_hi_lo_w )
1202	1207
1203	1208	AM_RANGE(0xe0000, 0xfffff) AM_ROM AM_REGION("maincpu",0)
1204	1209	ADDRESS_MAP_END
1205	1210
1206	1211	static ADDRESS_MAP_START( saklove_io, AS_IO, 8, subsino2_state )
1207		AM_RANGE(0x0000, 0x0000) AM_WRITE_LEGACY(ss9601_scrollctrl_w )
	1212	AM_RANGE(0x0000, 0x0000) AM_WRITE(ss9601_scrollctrl_w )
1208	1213
1209	1214	AM_RANGE(0x0020, 0x0020) AM_DEVREADWRITE("oki", okim6295_device, read, write)
1210	1215	AM_RANGE(0x0040, 0x0041) AM_DEVWRITE_LEGACY("ymsnd", ym3812_w )
1211	1216
1212		AM_RANGE(0x0060, 0x0063) AM_WRITE_LEGACY(hm86171_colorram_w )
	1217	AM_RANGE(0x0060, 0x0063) AM_WRITE(hm86171_colorram_w )
1213	1218
1214		AM_RANGE(0x0080, 0x0080) AM_WRITE_LEGACY(ss9601_tilesize_w )
1215		AM_RANGE(0x00a0, 0x00a0) AM_WRITE_LEGACY(ss9601_byte_lo_w )
1216		AM_RANGE(0x021f, 0x021f) AM_WRITE_LEGACY(ss9601_disable_w )
1217		AM_RANGE(0x0220, 0x0225) AM_WRITE_LEGACY(ss9601_scroll_w )
	1219	AM_RANGE(0x0080, 0x0080) AM_WRITE(ss9601_tilesize_w )
	1220	AM_RANGE(0x00a0, 0x00a0) AM_WRITE(ss9601_byte_lo_w )
	1221	AM_RANGE(0x021f, 0x021f) AM_WRITE(ss9601_disable_w )
	1222	AM_RANGE(0x0220, 0x0225) AM_WRITE(ss9601_scroll_w )
1218	1223
1219		AM_RANGE(0x0300, 0x0303) AM_WRITE_LEGACY(saklove_outputs_w ) AM_BASE(m_outputs )
	1224	AM_RANGE(0x0300, 0x0303) AM_WRITE(saklove_outputs_w ) AM_BASE(m_outputs )
1220	1225	AM_RANGE(0x0303, 0x0303) AM_READ_PORT( "IN D" )   // 0x40 serial out, 0x80 serial in
1221	1226	AM_RANGE(0x0304, 0x0304) AM_READ_PORT( "IN A" )
1222	1227	AM_RANGE(0x0305, 0x0305) AM_READ_PORT( "IN B" )
1223	1228	AM_RANGE(0x0306, 0x0306) AM_READ_PORT( "IN C" )
1224	1229
1225		AM_RANGE(0x0307, 0x0307) AM_READ_LEGACY(dsw_r )
1226		AM_RANGE(0x0308, 0x0308) AM_WRITE_LEGACY(dsw_mask_w )
	1230	AM_RANGE(0x0307, 0x0307) AM_READ(dsw_r )
	1231	AM_RANGE(0x0308, 0x0308) AM_WRITE(dsw_mask_w )
1227	1232
1228		AM_RANGE(0x0312, 0x0312) AM_READ_LEGACY(vblank_bit2_r ) AM_DEVWRITE_LEGACY("oki", oki_bank_bit0_w )
	1233	AM_RANGE(0x0312, 0x0312) AM_READ(vblank_bit2_r ) AM_DEVWRITE_LEGACY("oki", oki_bank_bit0_w )
1229	1234
1230	1235	// Peripheral Control Block
1231		AM_RANGE(0xff00, 0xffff) AM_READWRITE_LEGACY(am188em_regs_r, am188em_regs_w ) AM_BASE(m_am188em_regs )
	1236	AM_RANGE(0xff00, 0xffff) AM_READWRITE(am188em_regs_r, am188em_regs_w ) AM_BASE(m_am188em_regs )
1232	1237	ADDRESS_MAP_END
1233	1238
1234	1239	/***************************************************************************
1235	1240	X-Plan
1236	1241	***************************************************************************/
1237	1242
1238		static WRITE8_HANDLER( xplan_outputs_w )
	1243	WRITE8_MEMBER(subsino2_state::xplan_outputs_w)
1239	1244	{
1240		subsino2_state *state = space->machine().driver_data<subsino2_state>();
1241		state->m_outputs[offset] = data;
	1245	m_outputs[offset] = data;
1242	1246
1243	1247	switch (offset)
1244	1248	{
r14845	r14846
1247	1251	break;
1248	1252
1249	1253	case 1:
1250		set_led_status(space->machine(), 0,   data & 0x02);   // raise
	1254	set_led_status(machine(), 0,   data & 0x02);   // raise
1251	1255	break;
1252	1256
1253	1257	case 2:   // B
1254		set_led_status(space->machine(), 1,   data & 0x04);   // hold 1 / big ?
1255		set_led_status(space->machine(), 2,   data & 0x08);   // hold 5 / bet
1256		set_led_status(space->machine(), 3,   data & 0x10);   // hold 4 ?
1257		set_led_status(space->machine(), 4,   data & 0x20);   // hold 2 / double up
1258		set_led_status(space->machine(), 5,   data & 0x40);   // hold 3 / small ?
	1258	set_led_status(machine(), 1,   data & 0x04);   // hold 1 / big ?
	1259	set_led_status(machine(), 2,   data & 0x08);   // hold 5 / bet
	1260	set_led_status(machine(), 3,   data & 0x10);   // hold 4 ?
	1261	set_led_status(machine(), 4,   data & 0x20);   // hold 2 / double up
	1262	set_led_status(machine(), 5,   data & 0x40);   // hold 3 / small ?
1259	1263	break;
1260	1264
1261	1265	case 3:   // A
1262		coin_counter_w(space->machine(), 0,   data & 0x01 );
1263		coin_counter_w(space->machine(), 1,   data & 0x02 );
	1266	coin_counter_w(machine(), 0,   data & 0x01 );
	1267	coin_counter_w(machine(), 1,   data & 0x02 );
1264	1268
1265		set_led_status(space->machine(), 6,   data & 0x10);   // start / take
	1269	set_led_status(machine(), 6,   data & 0x10);   // start / take
1266	1270	break;
1267	1271	}
1268	1272
1269		//  popmessage("0: %02x - 1: %02x - 2: %02x - 3: %02x", state->m_outputs[0], state->m_outputs[1], state->m_outputs[2], state->m_outputs[3]);
	1273	//  popmessage("0: %02x - 1: %02x - 2: %02x - 3: %02x", m_outputs[0], m_outputs[1], m_outputs[2], m_outputs[3]);
1270	1274	}
1271	1275
1272	1276	static ADDRESS_MAP_START( xplan_map, AS_PROGRAM, 8, subsino2_state )
1273	1277	AM_RANGE(0x00000, 0x07fff) AM_RAM AM_SHARE("nvram")   // battery
1274	1278
1275	1279	// write both (L1, byte_lo2)
1276		AM_RANGE( 0x10000, 0x11fff ) AM_WRITE_LEGACY(ss9601_videoram_1_hi_lo2_w )
	1280	AM_RANGE( 0x10000, 0x11fff ) AM_WRITE(ss9601_videoram_1_hi_lo2_w )
1277	1281	// read lo (L1)   (only half tilemap?)
1278		AM_RANGE( 0x12000, 0x12fff ) AM_READ_LEGACY(ss9601_videoram_1_lo_r )
1279		AM_RANGE( 0x13000, 0x131ff ) AM_READWRITE_LEGACY(ss9601_scrollram_1_lo_r, ss9601_scrollram_1_lo_w )
	1282	AM_RANGE( 0x12000, 0x12fff ) AM_READ(ss9601_videoram_1_lo_r )
	1283	AM_RANGE( 0x13000, 0x131ff ) AM_READWRITE(ss9601_scrollram_1_lo_r, ss9601_scrollram_1_lo_w )
1280	1284
1281	1285	// write both (L0, byte_lo2)
1282		AM_RANGE( 0x14000, 0x15fff ) AM_WRITE_LEGACY(ss9601_videoram_0_hi_lo2_w )
	1286	AM_RANGE( 0x14000, 0x15fff ) AM_WRITE(ss9601_videoram_0_hi_lo2_w )
1283	1287	// read lo (REEL)
1284		AM_RANGE( 0x16000, 0x16fff ) AM_READ_LEGACY(ss9601_reelram_lo_r )
1285		AM_RANGE( 0x17000, 0x171ff ) AM_READWRITE_LEGACY(ss9601_scrollram_0_lo_r, ss9601_scrollram_0_lo_w )
	1288	AM_RANGE( 0x16000, 0x16fff ) AM_READ(ss9601_reelram_lo_r )
	1289	AM_RANGE( 0x17000, 0x171ff ) AM_READWRITE(ss9601_scrollram_0_lo_r, ss9601_scrollram_0_lo_w )
1286	1290
1287	1291	// read hi (L1)
1288		AM_RANGE( 0x22000, 0x22fff ) AM_READ_LEGACY(ss9601_videoram_1_hi_r )
1289		AM_RANGE( 0x23000, 0x231ff ) AM_READWRITE_LEGACY(ss9601_scrollram_1_hi_r, ss9601_scrollram_1_hi_w )
	1292	AM_RANGE( 0x22000, 0x22fff ) AM_READ(ss9601_videoram_1_hi_r )
	1293	AM_RANGE( 0x23000, 0x231ff ) AM_READWRITE(ss9601_scrollram_1_hi_r, ss9601_scrollram_1_hi_w )
1290	1294	// read hi (REEL)
1291		AM_RANGE( 0x26000, 0x26fff ) AM_READ_LEGACY(ss9601_reelram_hi_r )
1292		AM_RANGE( 0x27000, 0x271ff ) AM_READWRITE_LEGACY(ss9601_scrollram_0_hi_r, ss9601_scrollram_0_hi_w )
	1295	AM_RANGE( 0x26000, 0x26fff ) AM_READ(ss9601_reelram_hi_r )
	1296	AM_RANGE( 0x27000, 0x271ff ) AM_READWRITE(ss9601_scrollram_0_hi_r, ss9601_scrollram_0_hi_w )
1293	1297
1294	1298	// write both (L1, byte_lo)
1295		AM_RANGE( 0x30000, 0x31fff ) AM_WRITE_LEGACY(ss9601_videoram_1_hi_lo_w )
1296		AM_RANGE( 0x32000, 0x32fff ) AM_WRITE_LEGACY(ss9601_videoram_1_hi_lo_w )
1297		AM_RANGE( 0x33000, 0x331ff ) AM_WRITE_LEGACY(ss9601_scrollram_1_hi_lo_w )
	1299	AM_RANGE( 0x30000, 0x31fff ) AM_WRITE(ss9601_videoram_1_hi_lo_w )
	1300	AM_RANGE( 0x32000, 0x32fff ) AM_WRITE(ss9601_videoram_1_hi_lo_w )
	1301	AM_RANGE( 0x33000, 0x331ff ) AM_WRITE(ss9601_scrollram_1_hi_lo_w )
1298	1302	// write both (L0 & REEL, byte_lo)
1299		AM_RANGE( 0x34000, 0x35fff ) AM_WRITE_LEGACY(ss9601_videoram_0_hi_lo_w )
1300		AM_RANGE( 0x36000, 0x36fff ) AM_WRITE_LEGACY(ss9601_reelram_hi_lo_w )
1301		AM_RANGE( 0x37000, 0x371ff ) AM_WRITE_LEGACY(ss9601_scrollram_0_hi_lo_w )
	1303	AM_RANGE( 0x34000, 0x35fff ) AM_WRITE(ss9601_videoram_0_hi_lo_w )
	1304	AM_RANGE( 0x36000, 0x36fff ) AM_WRITE(ss9601_reelram_hi_lo_w )
	1305	AM_RANGE( 0x37000, 0x371ff ) AM_WRITE(ss9601_scrollram_0_hi_lo_w )
1302	1306
1303	1307	AM_RANGE(0xc0000, 0xfffff) AM_ROM AM_REGION("maincpu",0)
1304	1308	ADDRESS_MAP_END
r14845	r14846
1306	1310	static ADDRESS_MAP_START( xplan_io, AS_IO, 8, subsino2_state )
1307	1311	AM_RANGE(0x0000, 0x0000) AM_DEVREADWRITE("oki", okim6295_device, read, write)
1308	1312
1309		AM_RANGE(0x0020, 0x0020) AM_WRITE_LEGACY(ss9601_byte_lo2_w )
	1313	AM_RANGE(0x0020, 0x0020) AM_WRITE(ss9601_byte_lo2_w )
1310	1314
1311		AM_RANGE(0x0040, 0x0040) AM_WRITE_LEGACY(ss9601_scrollctrl_w )
	1315	AM_RANGE(0x0040, 0x0040) AM_WRITE(ss9601_scrollctrl_w )
1312	1316
1313		AM_RANGE(0x0060, 0x0063) AM_WRITE_LEGACY(hm86171_colorram_w )
1314		AM_RANGE(0x0080, 0x0080) AM_WRITE_LEGACY(ss9601_tilesize_w )
1315		AM_RANGE(0x00a0, 0x00a0) AM_WRITE_LEGACY(ss9601_byte_lo_w )
	1317	AM_RANGE(0x0060, 0x0063) AM_WRITE(hm86171_colorram_w )
	1318	AM_RANGE(0x0080, 0x0080) AM_WRITE(ss9601_tilesize_w )
	1319	AM_RANGE(0x00a0, 0x00a0) AM_WRITE(ss9601_byte_lo_w )
1316	1320
1317		AM_RANGE(0x021f, 0x021f) AM_WRITE_LEGACY(ss9601_disable_w )
1318		AM_RANGE(0x0220, 0x0225) AM_WRITE_LEGACY(ss9601_scroll_w )
	1321	AM_RANGE(0x021f, 0x021f) AM_WRITE(ss9601_disable_w )
	1322	AM_RANGE(0x0220, 0x0225) AM_WRITE(ss9601_scroll_w )
1319	1323
1320	1324	AM_RANGE(0x0235, 0x0235) AM_NOP   // INT0 Ack.?
1321	1325
1322		AM_RANGE(0x0300, 0x0300) AM_READ_LEGACY(vblank_bit6_r ) AM_DEVWRITE_LEGACY("oki", oki_bank_bit4_w )
1323		AM_RANGE(0x0301, 0x0301) AM_WRITE_LEGACY(dsw_mask_w )
1324		AM_RANGE(0x0302, 0x0302) AM_READ_LEGACY(dsw_r )
	1326	AM_RANGE(0x0300, 0x0300) AM_READ(vblank_bit6_r ) AM_DEVWRITE_LEGACY("oki", oki_bank_bit4_w )
	1327	AM_RANGE(0x0301, 0x0301) AM_WRITE(dsw_mask_w )
	1328	AM_RANGE(0x0302, 0x0302) AM_READ(dsw_r )
1325	1329	AM_RANGE(0x0303, 0x0303) AM_READ_PORT( "IN C" )
1326	1330	AM_RANGE(0x0304, 0x0304) AM_READ_PORT( "IN B" )
1327	1331	AM_RANGE(0x0305, 0x0305) AM_READ_PORT( "IN A" )
1328	1332	AM_RANGE(0x0306, 0x0306) AM_READ_PORT( "IN D" )   // 0x40 serial out, 0x80 serial in
1329	1333
1330	1334	// 306 = d, 307 = c, 308 = b, 309 = a
1331		AM_RANGE(0x0306, 0x0309) AM_WRITE_LEGACY(xplan_outputs_w ) AM_BASE(m_outputs )
	1335	AM_RANGE(0x0306, 0x0309) AM_WRITE(xplan_outputs_w ) AM_BASE(m_outputs )
1332	1336
1333	1337	// Peripheral Control Block
1334		AM_RANGE(0xff00, 0xffff) AM_READWRITE_LEGACY(am188em_regs_r, am188em_regs_w ) AM_BASE(m_am188em_regs )
	1338	AM_RANGE(0xff00, 0xffff) AM_READWRITE(am188em_regs_r, am188em_regs_w ) AM_BASE(m_am188em_regs )
1335	1339	ADDRESS_MAP_END
1336	1340
1337	1341	/***************************************************************************
1338	1342	X-Train
1339	1343	***************************************************************************/
1340	1344
1341		static WRITE8_HANDLER( xtrain_outputs_w )
	1345	WRITE8_MEMBER(subsino2_state::xtrain_outputs_w)
1342	1346	{
1343		subsino2_state *state = space->machine().driver_data<subsino2_state>();
1344		state->m_outputs[offset] = data;
	1347	m_outputs[offset] = data;
1345	1348
1346	1349	switch (offset)
1347	1350	{
r14845	r14846
1350	1353	break;
1351	1354
1352	1355	case 1:   // C
1353		set_led_status(space->machine(), 0,   data & 0x02);   // re-double
1354		set_led_status(space->machine(), 1,   data & 0x04);   // half double
	1356	set_led_status(machine(), 0,   data & 0x02);   // re-double
	1357	set_led_status(machine(), 1,   data & 0x04);   // half double
1355	1358	break;
1356	1359
1357	1360	case 2:   // B
1358		set_led_status(space->machine(), 2,   data & 0x02);   // hold 3 / small
1359		set_led_status(space->machine(), 3,   data & 0x04);   // hold 2 / big
1360		set_led_status(space->machine(), 4,   data & 0x08);   // bet
1361		set_led_status(space->machine(), 5,   data & 0x10);   // hold1 / take
1362		set_led_status(space->machine(), 6,   data & 0x20);   // double up
	1361	set_led_status(machine(), 2,   data & 0x02);   // hold 3 / small
	1362	set_led_status(machine(), 3,   data & 0x04);   // hold 2 / big
	1363	set_led_status(machine(), 4,   data & 0x08);   // bet
	1364	set_led_status(machine(), 5,   data & 0x10);   // hold1 / take
	1365	set_led_status(machine(), 6,   data & 0x20);   // double up
1363	1366	break;
1364	1367
1365	1368	case 3:   // A
1366		coin_counter_w(space->machine(), 0,   data & 0x01 );   // coin in
1367		coin_counter_w(space->machine(), 1,   data & 0x02 );   // key in
	1369	coin_counter_w(machine(), 0,   data & 0x01 );   // coin in
	1370	coin_counter_w(machine(), 1,   data & 0x02 );   // key in
1368	1371
1369		set_led_status(space->machine(), 7,   data & 0x10);   // start
	1372	set_led_status(machine(), 7,   data & 0x10);   // start
1370	1373	break;
1371	1374	}
1372	1375
1373		//  popmessage("0: %02x - 1: %02x - 2: %02x - 3: %02x", state->m_outputs[0], state->m_outputs[1], state->m_outputs[2], state->m_outputs[3]);
	1376	//  popmessage("0: %02x - 1: %02x - 2: %02x - 3: %02x", m_outputs[0], m_outputs[1], m_outputs[2], m_outputs[3]);
1374	1377	}
1375	1378
1376	1379	static ADDRESS_MAP_START( expcard_io, AS_IO, 8, subsino2_state )
1377	1380	// 306 = d, 307 = c, 308 = b, 309 = a
1378		AM_RANGE(0x0306, 0x0309) AM_WRITE_LEGACY(expcard_outputs_w ) AM_BASE(m_outputs )
	1381	AM_RANGE(0x0306, 0x0309) AM_WRITE(expcard_outputs_w ) AM_BASE(m_outputs )
1379	1382
1380	1383	AM_IMPORT_FROM( xplan_io )
1381	1384	ADDRESS_MAP_END
1382	1385
1383	1386	static ADDRESS_MAP_START( xtrain_io, AS_IO, 8, subsino2_state )
1384	1387	// 306 = d, 307 = c, 308 = b, 309 = a
1385		AM_RANGE(0x0306, 0x0309) AM_WRITE_LEGACY(xtrain_outputs_w ) AM_BASE(m_outputs )
	1388	AM_RANGE(0x0306, 0x0309) AM_WRITE(xtrain_outputs_w ) AM_BASE(m_outputs )
1386	1389
1387	1390	AM_IMPORT_FROM( xplan_io )
1388	1391	ADDRESS_MAP_END

src/mame/drivers/buster.c

r14845	r14846
19	19	: driver_device(mconfig, type, tag) { }
20	20
21	21	UINT8 *m_vram;
	22	DECLARE_READ8_MEMBER(test_r);
22	23	};
23	24
24	25
r14845	r14846
50	51	}
51	52
52	53	#if 0
53		static READ8_HANDLER( test_r )
	54	READ8_MEMBER(buster_state::test_r)
54	55	{
55		return space->machine().rand();
	56	return machine().rand();
56	57	}
57	58	#endif
58	59
r14845	r14846
71	72	AM_RANGE(0x7c8c, 0x7c8c) AM_READ_PORT("IN6")
72	73	AM_RANGE(0x7c8e, 0x7c8e) AM_READ_PORT("IN7")
73	74	AM_RANGE(0x7c00, 0x7cff) AM_RAM // ???
74		AM_RANGE(0x8800, 0x8fff) AM_RAM AM_SHARE("wram")//AM_READ_LEGACY(test_r) // ???
	75	AM_RANGE(0x8800, 0x8fff) AM_RAM AM_SHARE("wram")//AM_READ(test_r) // ???
75	76	AM_RANGE(0xa000, 0xa0ff) AM_RAM // nvram?
76	77	ADDRESS_MAP_END
77	78

src/mame/drivers/m63.c

r14845	r14846
155	155	device_t *m_ay1;
156	156	device_t *m_ay2;
157	157	samples_device *m_samples;
	158	DECLARE_WRITE8_MEMBER(m63_videoram_w);
	159	DECLARE_WRITE8_MEMBER(m63_colorram_w);
	160	DECLARE_WRITE8_MEMBER(m63_videoram2_w);
	161	DECLARE_WRITE8_MEMBER(m63_palbank_w);
	162	DECLARE_WRITE8_MEMBER(m63_flipscreen_w);
	163	DECLARE_WRITE8_MEMBER(fghtbskt_flipscreen_w);
	164	DECLARE_WRITE8_MEMBER(coin_w);
	165	DECLARE_WRITE8_MEMBER(snd_irq_w);
	166	DECLARE_WRITE8_MEMBER(snddata_w);
	167	DECLARE_WRITE8_MEMBER(p1_w);
	168	DECLARE_WRITE8_MEMBER(p2_w);
	169	DECLARE_READ8_MEMBER(snd_status_r);
	170	DECLARE_READ8_MEMBER(irq_r);
	171	DECLARE_READ8_MEMBER(snddata_r);
	172	DECLARE_WRITE8_MEMBER(fghtbskt_samples_w);
	173	DECLARE_WRITE8_MEMBER(nmi_mask_w);
158	174	};
159	175
160	176
r14845	r14846
213	229	}
214	230	}
215	231
216		static WRITE8_HANDLER( m63_videoram_w )
	232	WRITE8_MEMBER(m63_state::m63_videoram_w)
217	233	{
218		m63_state *state = space->machine().driver_data<m63_state>();
219	234
220		state->m_videoram[offset] = data;
221		state->m_bg_tilemap->mark_tile_dirty(offset);
	235	m_videoram[offset] = data;
	236	m_bg_tilemap->mark_tile_dirty(offset);
222	237	}
223	238
224		static WRITE8_HANDLER( m63_colorram_w )
	239	WRITE8_MEMBER(m63_state::m63_colorram_w)
225	240	{
226		m63_state *state = space->machine().driver_data<m63_state>();
227	241
228		state->m_colorram[offset] = data;
229		state->m_bg_tilemap->mark_tile_dirty(offset);
	242	m_colorram[offset] = data;
	243	m_bg_tilemap->mark_tile_dirty(offset);
230	244	}
231	245
232		static WRITE8_HANDLER( m63_videoram2_w )
	246	WRITE8_MEMBER(m63_state::m63_videoram2_w)
233	247	{
234		m63_state *state = space->machine().driver_data<m63_state>();
235	248
236		state->m_videoram2[offset] = data;
237		state->m_fg_tilemap->mark_tile_dirty(offset);
	249	m_videoram2[offset] = data;
	250	m_fg_tilemap->mark_tile_dirty(offset);
238	251	}
239	252
240		static WRITE8_HANDLER( m63_palbank_w )
	253	WRITE8_MEMBER(m63_state::m63_palbank_w)
241	254	{
242		m63_state *state = space->machine().driver_data<m63_state>();
243	255
244		if (state->m_pal_bank != (data & 0x01))
	256	if (m_pal_bank != (data & 0x01))
245	257	{
246		state->m_pal_bank = data & 0x01;
247		state->m_bg_tilemap->mark_all_dirty();
	258	m_pal_bank = data & 0x01;
	259	m_bg_tilemap->mark_all_dirty();
248	260	}
249	261	}
250	262
251		static WRITE8_HANDLER( m63_flipscreen_w )
	263	WRITE8_MEMBER(m63_state::m63_flipscreen_w)
252	264	{
253		if (flip_screen_get(space->machine()) != (~data & 0x01))
	265	if (flip_screen_get(machine()) != (~data & 0x01))
254	266	{
255		flip_screen_set(space->machine(), ~data & 0x01);
256		space->machine().tilemap().mark_all_dirty();
	267	flip_screen_set(machine(), ~data & 0x01);
	268	machine().tilemap().mark_all_dirty();
257	269	}
258	270	}
259	271
260		static WRITE8_HANDLER( fghtbskt_flipscreen_w )
	272	WRITE8_MEMBER(m63_state::fghtbskt_flipscreen_w)
261	273	{
262		m63_state *state = space->machine().driver_data<m63_state>();
263	274
264		flip_screen_set(space->machine(), data);
265		state->m_fg_flag = flip_screen_get(space->machine()) ? TILE_FLIPX : 0;
	275	flip_screen_set(machine(), data);
	276	m_fg_flag = flip_screen_get(machine()) ? TILE_FLIPX : 0;
266	277	}
267	278
268	279
r14845	r14846
354	365	}
355	366
356	367
357		static WRITE8_HANDLER( coin_w )
	368	WRITE8_MEMBER(m63_state::coin_w)
358	369	{
359		coin_counter_w(space->machine(), offset, data & 0x01);
	370	coin_counter_w(machine(), offset, data & 0x01);
360	371	}
361	372
362		static WRITE8_HANDLER( snd_irq_w )
	373	WRITE8_MEMBER(m63_state::snd_irq_w)
363	374	{
364		m63_state *state = space->machine().driver_data<m63_state>();
365		device_set_input_line(state->m_soundcpu, 0, ASSERT_LINE);
366		space->machine().scheduler().synchronize();
	375	device_set_input_line(m_soundcpu, 0, ASSERT_LINE);
	376	machine().scheduler().synchronize();
367	377	}
368	378
369		static WRITE8_HANDLER( snddata_w )
	379	WRITE8_MEMBER(m63_state::snddata_w)
370	380	{
371		m63_state *state = space->machine().driver_data<m63_state>();
372	381
373		if ((state->m_p2 & 0xf0) == 0xe0)
374		ay8910_address_w(state->m_ay1, 0, offset);
375		else if ((state->m_p2 & 0xf0) == 0xa0)
376		ay8910_data_w(state->m_ay1, 0, offset);
377		else if (state->m_ay2 != NULL && (state->m_p1 & 0xe0) == 0x60)
378		ay8910_address_w(state->m_ay2, 0, offset);
379		else if (state->m_ay2 != NULL && (state->m_p1 & 0xe0) == 0x40)
380		ay8910_data_w(state->m_ay2, 0, offset);
381		else if ((state->m_p2 & 0xf0) == 0x70 )
382		state->m_sound_status = offset;
	382	if ((m_p2 & 0xf0) == 0xe0)
	383	ay8910_address_w(m_ay1, 0, offset);
	384	else if ((m_p2 & 0xf0) == 0xa0)
	385	ay8910_data_w(m_ay1, 0, offset);
	386	else if (m_ay2 != NULL && (m_p1 & 0xe0) == 0x60)
	387	ay8910_address_w(m_ay2, 0, offset);
	388	else if (m_ay2 != NULL && (m_p1 & 0xe0) == 0x40)
	389	ay8910_data_w(m_ay2, 0, offset);
	390	else if ((m_p2 & 0xf0) == 0x70 )
	391	m_sound_status = offset;
383	392	}
384	393
385		static WRITE8_HANDLER( p1_w )
	394	WRITE8_MEMBER(m63_state::p1_w)
386	395	{
387		m63_state *state = space->machine().driver_data<m63_state>();
388		state->m_p1 = data;
	396	m_p1 = data;
389	397	}
390	398
391		static WRITE8_HANDLER( p2_w )
	399	WRITE8_MEMBER(m63_state::p2_w)
392	400	{
393		m63_state *state = space->machine().driver_data<m63_state>();
394	401
395		state->m_p2 = data;
396		if((state->m_p2 & 0xf0) == 0x50)
	402	m_p2 = data;
	403	if((m_p2 & 0xf0) == 0x50)
397	404	{
398		device_set_input_line(state->m_soundcpu, 0, CLEAR_LINE);
	405	device_set_input_line(m_soundcpu, 0, CLEAR_LINE);
399	406	}
400	407	}
401	408
402		static READ8_HANDLER( snd_status_r )
	409	READ8_MEMBER(m63_state::snd_status_r)
403	410	{
404		m63_state *state = space->machine().driver_data<m63_state>();
405		return state->m_sound_status;
	411	return m_sound_status;
406	412	}
407	413
408		static READ8_HANDLER( irq_r )
	414	READ8_MEMBER(m63_state::irq_r)
409	415	{
410		m63_state *state = space->machine().driver_data<m63_state>();
411	416
412		if (state->m_sound_irq)
	417	if (m_sound_irq)
413	418	{
414		state->m_sound_irq = 0;
	419	m_sound_irq = 0;
415	420	return 1;
416	421	}
417	422	return 0;
418	423	}
419	424
420		static READ8_HANDLER( snddata_r )
	425	READ8_MEMBER(m63_state::snddata_r)
421	426	{
422		m63_state *state = space->machine().driver_data<m63_state>();
423		switch (state->m_p2 & 0xf0)
	427	switch (m_p2 & 0xf0)
424	428	{
425	429	case 0x60:   return soundlatch_r(space, 0); ;
426		case 0x70:   return space->machine().region("user1")->base()[((state->m_p1 & 0x1f) << 8) | offset];
	430	case 0x70:   return machine().region("user1")->base()[((m_p1 & 0x1f) << 8) | offset];
427	431	}
428	432	return 0xff;
429	433	}
430	434
431		static WRITE8_HANDLER( fghtbskt_samples_w )
	435	WRITE8_MEMBER(m63_state::fghtbskt_samples_w)
432	436	{
433		m63_state *state = space->machine().driver_data<m63_state>();
434	437
435	438	if (data & 1)
436		state->m_samples->start_raw(0, state->m_samplebuf + ((data & 0xf0) << 8), 0x2000, 8000);
	439	m_samples->start_raw(0, m_samplebuf + ((data & 0xf0) << 8), 0x2000, 8000);
437	440	}
438	441
439		static WRITE8_HANDLER( nmi_mask_w )
	442	WRITE8_MEMBER(m63_state::nmi_mask_w)
440	443	{
441		m63_state *state = space->machine().driver_data<m63_state>();
442	444
443		state->m_nmi_mask = data & 1;
	445	m_nmi_mask = data & 1;
444	446	}
445	447
446	448
r14845	r14846
450	452	AM_RANGE(0xe000, 0xe1ff) AM_RAM
451	453	AM_RANGE(0xe200, 0xe2ff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
452	454	AM_RANGE(0xe300, 0xe3ff) AM_RAM AM_BASE(m_scrollram)
453		AM_RANGE(0xe400, 0xe7ff) AM_RAM_WRITE_LEGACY(m63_videoram2_w) AM_BASE(m_videoram2)
454		AM_RANGE(0xe800, 0xebff) AM_RAM_WRITE_LEGACY(m63_videoram_w) AM_BASE(m_videoram)
455		AM_RANGE(0xec00, 0xefff) AM_RAM_WRITE_LEGACY(m63_colorram_w) AM_BASE(m_colorram)
456		AM_RANGE(0xf000, 0xf000) AM_WRITE_LEGACY(nmi_mask_w)
457		AM_RANGE(0xf002, 0xf002) AM_WRITE_LEGACY(m63_flipscreen_w)
458		AM_RANGE(0xf003, 0xf003) AM_WRITE_LEGACY(m63_palbank_w)
459		AM_RANGE(0xf006, 0xf007) AM_WRITE_LEGACY(coin_w)
	455	AM_RANGE(0xe400, 0xe7ff) AM_RAM_WRITE(m63_videoram2_w) AM_BASE(m_videoram2)
	456	AM_RANGE(0xe800, 0xebff) AM_RAM_WRITE(m63_videoram_w) AM_BASE(m_videoram)
	457	AM_RANGE(0xec00, 0xefff) AM_RAM_WRITE(m63_colorram_w) AM_BASE(m_colorram)
	458	AM_RANGE(0xf000, 0xf000) AM_WRITE(nmi_mask_w)
	459	AM_RANGE(0xf002, 0xf002) AM_WRITE(m63_flipscreen_w)
	460	AM_RANGE(0xf003, 0xf003) AM_WRITE(m63_palbank_w)
	461	AM_RANGE(0xf006, 0xf007) AM_WRITE(coin_w)
460	462	AM_RANGE(0xf800, 0xf800) AM_READ_PORT("P1") AM_WRITE_LEGACY(soundlatch_w)
461	463	AM_RANGE(0xf801, 0xf801) AM_READ_PORT("P2") AM_WRITENOP   /* continues game when in stop mode (cleared by NMI handler) */
462	464	AM_RANGE(0xf802, 0xf802) AM_READ_PORT("DSW1")
463		AM_RANGE(0xf803, 0xf803) AM_WRITE_LEGACY(snd_irq_w)
	465	AM_RANGE(0xf803, 0xf803) AM_WRITE(snd_irq_w)
464	466	AM_RANGE(0xf806, 0xf806) AM_READ_PORT("DSW2")
465	467	ADDRESS_MAP_END
466	468
r14845	r14846
471	473	AM_RANGE(0xd000, 0xd1ff) AM_RAM
472	474	AM_RANGE(0xd200, 0xd2ff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
473	475	AM_RANGE(0xd300, 0xd3ff) AM_RAM AM_BASE(m_scrollram)
474		AM_RANGE(0xd400, 0xd7ff) AM_RAM_WRITE_LEGACY(m63_videoram2_w) AM_BASE(m_videoram2)
475		AM_RANGE(0xd800, 0xdbff) AM_RAM_WRITE_LEGACY(m63_videoram_w) AM_BASE(m_videoram)
476		AM_RANGE(0xdc00, 0xdfff) AM_RAM_WRITE_LEGACY(m63_colorram_w) AM_BASE(m_colorram)
477		AM_RANGE(0xf000, 0xf000) AM_READ_LEGACY(snd_status_r)
	476	AM_RANGE(0xd400, 0xd7ff) AM_RAM_WRITE(m63_videoram2_w) AM_BASE(m_videoram2)
	477	AM_RANGE(0xd800, 0xdbff) AM_RAM_WRITE(m63_videoram_w) AM_BASE(m_videoram)
	478	AM_RANGE(0xdc00, 0xdfff) AM_RAM_WRITE(m63_colorram_w) AM_BASE(m_colorram)
	479	AM_RANGE(0xf000, 0xf000) AM_READ(snd_status_r)
478	480	AM_RANGE(0xf001, 0xf001) AM_READ_PORT("P1")
479	481	AM_RANGE(0xf002, 0xf002) AM_READ_PORT("P2")
480	482	AM_RANGE(0xf003, 0xf003) AM_READ_PORT("DSW")
481		AM_RANGE(0xf000, 0xf000) AM_WRITE_LEGACY(snd_irq_w)
	483	AM_RANGE(0xf000, 0xf000) AM_WRITE(snd_irq_w)
482	484	AM_RANGE(0xf001, 0xf001) AM_WRITENOP
483	485	AM_RANGE(0xf002, 0xf002) AM_WRITE_LEGACY(soundlatch_w)
484	486	AM_RANGE(0xf800, 0xf800) AM_WRITENOP
485		AM_RANGE(0xf801, 0xf801) AM_WRITE_LEGACY(nmi_mask_w)
486		AM_RANGE(0xf802, 0xf802) AM_WRITE_LEGACY(fghtbskt_flipscreen_w)
	487	AM_RANGE(0xf801, 0xf801) AM_WRITE(nmi_mask_w)
	488	AM_RANGE(0xf802, 0xf802) AM_WRITE(fghtbskt_flipscreen_w)
487	489	AM_RANGE(0xf803, 0xf803) AM_WRITENOP
488	490	AM_RANGE(0xf804, 0xf804) AM_WRITENOP
489	491	AM_RANGE(0xf805, 0xf805) AM_WRITENOP
490	492	AM_RANGE(0xf806, 0xf806) AM_WRITENOP
491		AM_RANGE(0xf807, 0xf807) AM_WRITE_LEGACY(fghtbskt_samples_w)
	493	AM_RANGE(0xf807, 0xf807) AM_WRITE(fghtbskt_samples_w)
492	494	ADDRESS_MAP_END
493	495
494	496	static ADDRESS_MAP_START( i8039_map, AS_PROGRAM, 8, m63_state )
r14845	r14846
497	499
498	500
499	501	static ADDRESS_MAP_START( i8039_port_map, AS_IO, 8, m63_state )
500		AM_RANGE(0x00, 0xff) AM_READWRITE_LEGACY(snddata_r, snddata_w)
501		AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_WRITE_LEGACY(p1_w)
502		AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_WRITE_LEGACY(p2_w)
503		AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ_LEGACY(irq_r)
	502	AM_RANGE(0x00, 0xff) AM_READWRITE(snddata_r, snddata_w)
	503	AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_WRITE(p1_w)
	504	AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_WRITE(p2_w)
	505	AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ(irq_r)
504	506	ADDRESS_MAP_END
505	507
506	508

src/mame/drivers/ggconnie.c

r14845	r14846
29	29	ggconnie_state(const machine_config &mconfig, device_type type, const char *tag)
30	30	: driver_device(mconfig, type, tag) { }
31	31
	32	DECLARE_WRITE8_MEMBER(lamp_w);
	33	DECLARE_WRITE8_MEMBER(output_w);
32	34	};
33	35
34	36
r14845	r14846
113	115
114	116	INPUT_PORTS_END
115	117
116		static WRITE8_HANDLER(lamp_w)
	118	WRITE8_MEMBER(ggconnie_state::lamp_w)
117	119	{
118	120	output_set_value("lamp", !BIT(data,0));
119	121	}
120	122
121		static WRITE8_HANDLER(output_w)
	123	WRITE8_MEMBER(ggconnie_state::output_w)
122	124	{
123	125	// written in "Output Test" in test mode
124	126	}
r14845	r14846
132	134	AM_RANGE( 0x1f7100, 0x1f7100) AM_READ_PORT("SWB")
133	135	AM_RANGE( 0x1f7200, 0x1f7200) AM_READ_PORT("SWC")
134	136	AM_RANGE( 0x1f7700, 0x1f7700) AM_READ_PORT("IN1")
135		AM_RANGE( 0x1f7800, 0x1f7800) AM_WRITE_LEGACY(output_w)
	137	AM_RANGE( 0x1f7800, 0x1f7800) AM_WRITE(output_w)
136	138	AM_RANGE( 0x1fe000, 0x1fe007) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w) AM_MIRROR(0x03e0)
137	139	AM_RANGE( 0x1fe008, 0x1fe00f) AM_READWRITE_LEGACY(vpc_r, vpc_w) AM_MIRROR(0x03e0)
138	140	AM_RANGE( 0x1fe010, 0x1fe017) AM_READWRITE_LEGACY(vdc_1_r, vdc_1_w) AM_MIRROR(0x03e0)
139	141	AM_RANGE( 0x1fe400, 0x1fe7ff) AM_READWRITE_LEGACY(vce_r, vce_w)
140	142	AM_RANGE( 0x1fe800, 0x1febff) AM_DEVREADWRITE_LEGACY("c6280", c6280_r, c6280_w)
141	143	AM_RANGE( 0x1fec00, 0x1fefff) AM_READWRITE_LEGACY(h6280_timer_r, h6280_timer_w)
142		AM_RANGE( 0x1ff000, 0x1ff000) AM_READ_PORT("IN0") AM_WRITE_LEGACY(lamp_w)
	144	AM_RANGE( 0x1ff000, 0x1ff000) AM_READ_PORT("IN0") AM_WRITE(lamp_w)
143	145	AM_RANGE( 0x1ff400, 0x1ff7ff) AM_READWRITE_LEGACY(h6280_irq_status_r, h6280_irq_status_w )
144	146	ADDRESS_MAP_END
145	147

src/mame/drivers/toratora.c

r14845	r14846
43	43	pia6821_device *m_pia_u1;
44	44	pia6821_device *m_pia_u2;
45	45	pia6821_device *m_pia_u3;
	46	DECLARE_WRITE8_MEMBER(clear_tv_w);
	47	DECLARE_READ8_MEMBER(timer_r);
	48	DECLARE_WRITE8_MEMBER(clear_timer_w);
46	49	};
47	50
48	51
r14845	r14846
98	101	}
99	102
100	103
101		static WRITE8_HANDLER( clear_tv_w )
	104	WRITE8_MEMBER(toratora_state::clear_tv_w)
102	105	{
103		toratora_state *state = space->machine().driver_data<toratora_state>();
104		state->m_clear_tv = 1;
	106	m_clear_tv = 1;
105	107	}
106	108
107	109
r14845	r14846
156	158	state->m_pia_u1->ca2_w(input_port_read(device->machine(), "INPUT") & 0x20);
157	159	}
158	160
159		static READ8_HANDLER( timer_r )
	161	READ8_MEMBER(toratora_state::timer_r)
160	162	{
161		toratora_state *state = space->machine().driver_data<toratora_state>();
162		return state->m_timer;
	163	return m_timer;
163	164	}
164	165
165		static WRITE8_HANDLER( clear_timer_w )
	166	WRITE8_MEMBER(toratora_state::clear_timer_w)
166	167	{
167		toratora_state *state = space->machine().driver_data<toratora_state>();
168		state->m_timer = 0;
	168	m_timer = 0;
169	169	}
170	170
171	171
r14845	r14846
314	314	AM_RANGE(0x8000, 0x9fff) AM_RAM AM_BASE_SIZE(m_videoram, m_videoram_size)
315	315	AM_RANGE(0xa000, 0xf047) AM_NOP
316	316	AM_RANGE(0xf048, 0xf049) AM_NOP
317		AM_RANGE(0xf04a, 0xf04a) AM_WRITE_LEGACY(clear_tv_w)   /* the read is mark *LEDEN, but not used */
318		AM_RANGE(0xf04b, 0xf04b) AM_READWRITE_LEGACY(timer_r, clear_timer_w)
	317	AM_RANGE(0xf04a, 0xf04a) AM_WRITE(clear_tv_w)   /* the read is mark *LEDEN, but not used */
	318	AM_RANGE(0xf04b, 0xf04b) AM_READWRITE(timer_r, clear_timer_w)
319	319	AM_RANGE(0xa04c, 0xf09f) AM_NOP
320	320	AM_RANGE(0xf0a0, 0xf0a3) AM_DEVREADWRITE("pia_u1", pia6821_device, read, write)
321	321	AM_RANGE(0xf0a4, 0xf0a7) AM_DEVREADWRITE("pia_u3", pia6821_device, read, write)

src/mame/drivers/r2dtank.c

r14845	r14846
61	61	UINT32 m_ttl74123_output;
62	62	UINT8 m_AY8910_selected;
63	63	pen_t m_pens[NUM_PENS];
	64	DECLARE_READ8_MEMBER(audio_command_r);
	65	DECLARE_WRITE8_MEMBER(audio_command_w);
	66	DECLARE_READ8_MEMBER(audio_answer_r);
	67	DECLARE_WRITE8_MEMBER(audio_answer_w);
64	68	};
65	69
66	70
r14845	r14846
99	103	*
100	104	*************************************/
101	105
102		static READ8_HANDLER( audio_command_r )
	106	READ8_MEMBER(r2dtank_state::audio_command_r)
103	107	{
104	108	UINT8 ret = soundlatch_r(space, 0);
105	109
106		if (LOG_AUDIO_COMM) logerror("%08X  CPU#1  Audio Command Read: %x\n", cpu_get_pc(&space->device()), ret);
	110	if (LOG_AUDIO_COMM) logerror("%08X  CPU#1  Audio Command Read: %x\n", cpu_get_pc(&space.device()), ret);
107	111
108	112	return ret;
109	113	}
110	114
111	115
112		static WRITE8_HANDLER( audio_command_w )
	116	WRITE8_MEMBER(r2dtank_state::audio_command_w)
113	117	{
114	118	soundlatch_w(space, 0, ~data);
115		cputag_set_input_line(space->machine(), "audiocpu", M6800_IRQ_LINE, HOLD_LINE);
	119	cputag_set_input_line(machine(), "audiocpu", M6800_IRQ_LINE, HOLD_LINE);
116	120
117		if (LOG_AUDIO_COMM) logerror("%08X   CPU#0  Audio Command Write: %x\n", cpu_get_pc(&space->device()), data^0xff);
	121	if (LOG_AUDIO_COMM) logerror("%08X   CPU#0  Audio Command Write: %x\n", cpu_get_pc(&space.device()), data^0xff);
118	122	}
119	123
120	124
121		static READ8_HANDLER( audio_answer_r )
	125	READ8_MEMBER(r2dtank_state::audio_answer_r)
122	126	{
123	127	UINT8 ret = soundlatch2_r(space, 0);
124		if (LOG_AUDIO_COMM) logerror("%08X  CPU#0  Audio Answer Read: %x\n", cpu_get_pc(&space->device()), ret);
	128	if (LOG_AUDIO_COMM) logerror("%08X  CPU#0  Audio Answer Read: %x\n", cpu_get_pc(&space.device()), ret);
125	129
126	130	return ret;
127	131	}
128	132
129	133
130		static WRITE8_HANDLER( audio_answer_w )
	134	WRITE8_MEMBER(r2dtank_state::audio_answer_w)
131	135	{
132	136	/* HACK - prevents lock-up, but causes game to end some in-between sreens prematurely */
133		if (cpu_get_pc(&space->device()) == 0xfb12)
	137	if (cpu_get_pc(&space.device()) == 0xfb12)
134	138	data = 0x00;
135	139
136	140	soundlatch2_w(space, 0, data);
137		cputag_set_input_line(space->machine(), "maincpu", M6809_IRQ_LINE, HOLD_LINE);
	141	cputag_set_input_line(machine(), "maincpu", M6809_IRQ_LINE, HOLD_LINE);
138	142
139		if (LOG_AUDIO_COMM) logerror("%08X  CPU#1  Audio Answer Write: %x\n", cpu_get_pc(&space->device()), data);
	143	if (LOG_AUDIO_COMM) logerror("%08X  CPU#1  Audio Answer Write: %x\n", cpu_get_pc(&space.device()), data);
140	144	}
141	145
142	146
r14845	r14846
416	420	AM_RANGE(0x4000, 0x5fff) AM_RAM AM_BASE(m_colorram)
417	421	AM_RANGE(0x6000, 0x7fff) AM_RAM
418	422	AM_RANGE(0x8000, 0x8003) AM_DEVREAD("pia_main", pia6821_device, read) AM_DEVWRITE_LEGACY("pia_main", pia_comp_w)
419		AM_RANGE(0x8004, 0x8004) AM_READWRITE_LEGACY(audio_answer_r, audio_command_w)
	423	AM_RANGE(0x8004, 0x8004) AM_READWRITE(audio_answer_r, audio_command_w)
420	424	AM_RANGE(0xb000, 0xb000) AM_DEVWRITE("crtc", mc6845_device, address_w)
421	425	AM_RANGE(0xb001, 0xb001) AM_DEVWRITE("crtc", mc6845_device, register_w)
422	426	AM_RANGE(0xc000, 0xc007) AM_RAM AM_SHARE("nvram")
r14845	r14846
427	431	static ADDRESS_MAP_START( r2dtank_audio_map, AS_PROGRAM, 8, r2dtank_state )
428	432	AM_RANGE(0x0000, 0x007f) AM_RAM      /* internal RAM */
429	433	AM_RANGE(0xd000, 0xd003) AM_DEVREADWRITE("pia_audio", pia6821_device, read, write)
430		AM_RANGE(0xf000, 0xf000) AM_READWRITE_LEGACY(audio_command_r, audio_answer_w)
	434	AM_RANGE(0xf000, 0xf000) AM_READWRITE(audio_command_r, audio_answer_w)
431	435	AM_RANGE(0xf800, 0xffff) AM_ROM
432	436	ADDRESS_MAP_END
433	437

src/mame/drivers/mastboy.c

r14845	r14846
459	459	int m_m5205_part;
460	460	int m_m5205_sambit0;
461	461	int m_m5205_sambit1;
	462	DECLARE_READ8_MEMBER(banked_ram_r);
	463	DECLARE_WRITE8_MEMBER(banked_ram_w);
	464	DECLARE_WRITE8_MEMBER(mastboy_bank_w);
	465	DECLARE_READ8_MEMBER(mastboy_backupram_r);
	466	DECLARE_WRITE8_MEMBER(mastboy_backupram_w);
	467	DECLARE_WRITE8_MEMBER(backupram_enable_w);
	468	DECLARE_WRITE8_MEMBER(msm5205_mastboy_m5205_sambit0_w);
	469	DECLARE_WRITE8_MEMBER(msm5205_mastboy_m5205_sambit1_w);
	470	DECLARE_WRITE8_MEMBER(mastboy_msm5205_data_w);
	471	DECLARE_WRITE8_MEMBER(mastboy_irq0_ack_w);
	472	DECLARE_READ8_MEMBER(mastboy_port_38_read);
	473	DECLARE_READ8_MEMBER(mastboy_nmi_read);
462	474	};
463	475
464	476
r14845	r14846
517	529
518	530	/* Access to Banked RAM */
519	531
520		static READ8_HANDLER(banked_ram_r)
	532	READ8_MEMBER(mastboy_state::banked_ram_r)
521	533	{
522		mastboy_state *state = space->machine().driver_data<mastboy_state>();
523		if ((state->m_bank&0x80) == 0x00)
	534	if ((m_bank&0x80) == 0x00)
524	535	{
525	536	int bank;
526		bank = state->m_bank & 0x07;
527		//if (state->m_bank&0xf8) printf("invalid bank bits in vram/vrom read\n");
	537	bank = m_bank & 0x07;
	538	//if (m_bank&0xf8) printf("invalid bank bits in vram/vrom read\n");
528	539
529	540	if (bank>0x3) // ROM access
530	541	{
531		UINT8 *src    = space->machine().region( "gfx1" )->base();
	542	UINT8 *src    = machine().region( "gfx1" )->base();
532	543	bank &=0x3;
533	544	return src[offset+(bank*0x4000)];
534	545	}
r14845	r14846
536	547	{
537	548	bank &=0x3;
538	549	/* we have to invert the data for the GFX decode */
539		return state->m_vram[offset+(bank*0x4000)]^0xff;
	550	return m_vram[offset+(bank*0x4000)]^0xff;
540	551	}
541	552	}
542	553	else
543	554	{
544	555	UINT8 *src;
545	556	int bank;
546		bank = state->m_bank & 0x7f;
547		src = space->machine().region       ( "user1" )->base() + bank * 0x4000;
	557	bank = m_bank & 0x7f;
	558	src = machine().region       ( "user1" )->base() + bank * 0x4000;
548	559	return src[offset];
549	560	}
550	561	}
551	562
552		static WRITE8_HANDLER( banked_ram_w )
	563	WRITE8_MEMBER(mastboy_state::banked_ram_w)
553	564	{
554		mastboy_state *state = space->machine().driver_data<mastboy_state>();
555		if ((state->m_bank&0x80) == 0x00)
	565	if ((m_bank&0x80) == 0x00)
556	566	{
557	567	int bank;
558		bank = state->m_bank & 0x07;
	568	bank = m_bank & 0x07;
559	569	//if (data&0xf8) printf("invalid bank bits in vram/vrom write\n");
560	570
561	571	if (bank>0x3) // ROM access
r14845	r14846
571	581	offs = offset+(bank*0x4000);
572	582
573	583	/* we have to invert the data for the GFX decode */
574		state->m_vram[offs] = data^0xff;
	584	m_vram[offs] = data^0xff;
575	585
576	586	/* Decode the new tile */
577		gfx_element_mark_dirty(space->machine().gfx[0], offs/32);
	587	gfx_element_mark_dirty(machine().gfx[0], offs/32);
578	588	}
579	589	}
580	590	else
r14845	r14846
583	593	}
584	594	}
585	595
586		static WRITE8_HANDLER( mastboy_bank_w )
	596	WRITE8_MEMBER(mastboy_state::mastboy_bank_w)
587	597	{
588		mastboy_state *state = space->machine().driver_data<mastboy_state>();
589	598	// controls access to banked ram / rom
590		state->m_bank = data;
	599	m_bank = data;
591	600	}
592	601
593	602	/* Backup RAM access */
594	603
595		static READ8_HANDLER( mastboy_backupram_r )
	604	READ8_MEMBER(mastboy_state::mastboy_backupram_r)
596	605	{
597		mastboy_state *state = space->machine().driver_data<mastboy_state>();
598		return state->m_nvram[offset];
	606	return m_nvram[offset];
599	607	}
600	608
601		static WRITE8_HANDLER( mastboy_backupram_w )
	609	WRITE8_MEMBER(mastboy_state::mastboy_backupram_w)
602	610	{
603		mastboy_state *state = space->machine().driver_data<mastboy_state>();
604		//  if (state->m_backupram_enabled)
	611	//  if (m_backupram_enabled)
605	612	//  {
606		state->m_nvram[offset] = data;
	613	m_nvram[offset] = data;
607	614	//  }
608	615	//  else
609	616	//  {
r14845	r14846
611	618	//  }
612	619	}
613	620
614		static WRITE8_HANDLER( backupram_enable_w )
	621	WRITE8_MEMBER(mastboy_state::backupram_enable_w)
615	622	{
616		mastboy_state *state = space->machine().driver_data<mastboy_state>();
617	623	/* This is some kind of enable / disable control for backup ram (see Charles's notes) but I'm not
618	624	sure how it works in practice, if we use it then it writes a lot of data with it disabled */
619		state->m_backupram_enabled = data&1;
	625	m_backupram_enabled = data&1;
620	626	}
621	627
622	628	/* MSM5205 Related */
623	629
624		static WRITE8_HANDLER( msm5205_mastboy_m5205_sambit0_w )
	630	WRITE8_MEMBER(mastboy_state::msm5205_mastboy_m5205_sambit0_w)
625	631	{
626		mastboy_state *state = space->machine().driver_data<mastboy_state>();
627		device_t *adpcm = space->machine().device("msm");
	632	device_t *adpcm = machine().device("msm");
628	633
629		state->m_m5205_sambit0 = data & 1;
630		msm5205_playmode_w(adpcm,  (1 << 2) | (state->m_m5205_sambit1 << 1) | (state->m_m5205_sambit0) );
	634	m_m5205_sambit0 = data & 1;
	635	msm5205_playmode_w(adpcm,  (1 << 2) | (m_m5205_sambit1 << 1) | (m_m5205_sambit0) );
631	636
632	637	logerror("msm5205 samplerate bit 0, set to %02x\n",data);
633	638	}
634	639
635		static WRITE8_HANDLER( msm5205_mastboy_m5205_sambit1_w )
	640	WRITE8_MEMBER(mastboy_state::msm5205_mastboy_m5205_sambit1_w)
636	641	{
637		mastboy_state *state = space->machine().driver_data<mastboy_state>();
638		device_t *adpcm = space->machine().device("msm");
	642	device_t *adpcm = machine().device("msm");
639	643
640		state->m_m5205_sambit1 = data & 1;
	644	m_m5205_sambit1 = data & 1;
641	645
642		msm5205_playmode_w(adpcm,  (1 << 2) | (state->m_m5205_sambit1 << 1) | (state->m_m5205_sambit0) );
	646	msm5205_playmode_w(adpcm,  (1 << 2) | (m_m5205_sambit1 << 1) | (m_m5205_sambit0) );
643	647
644	648	logerror("msm5205 samplerate bit 0, set to %02x\n",data);
645	649	}
r14845	r14846
651	655	msm5205_reset_w(device,data&1);
652	656	}
653	657
654		static WRITE8_HANDLER( mastboy_msm5205_data_w )
	658	WRITE8_MEMBER(mastboy_state::mastboy_msm5205_data_w)
655	659	{
656		mastboy_state *state = space->machine().driver_data<mastboy_state>();
657		state->m_m5205_next = data;
	660	m_m5205_next = data;
658	661	}
659	662
660	663	static void mastboy_adpcm_int(device_t *device)
r14845	r14846
677	680
678	681	/* Interrupt Handling */
679	682
680		static WRITE8_HANDLER( mastboy_irq0_ack_w )
	683	WRITE8_MEMBER(mastboy_state::mastboy_irq0_ack_w)
681	684	{
682		mastboy_state *state = space->machine().driver_data<mastboy_state>();
683		state->m_irq0_ack = data;
	685	m_irq0_ack = data;
684	686	if ((data & 1) == 1)
685		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
	687	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
686	688	}
687	689
688	690	static INTERRUPT_GEN( mastboy_interrupt )
r14845	r14846
704	706	AM_RANGE(0x9000, 0x9fff) AM_RAM AM_BASE(m_tileram)// tilemap ram
705	707	AM_RANGE(0xa000, 0xa1ff) AM_RAM AM_BASE(m_colram) AM_MIRROR(0x0e00)  // colour ram
706	708
707		AM_RANGE(0xc000, 0xffff) AM_READWRITE_LEGACY(banked_ram_r,banked_ram_w) // mastboy bank area read / write
	709	AM_RANGE(0xc000, 0xffff) AM_READWRITE(banked_ram_r,banked_ram_w) // mastboy bank area read / write
708	710
709		AM_RANGE(0xff000, 0xff7ff) AM_READWRITE_LEGACY(mastboy_backupram_r,mastboy_backupram_w) AM_SHARE("nvram")
	711	AM_RANGE(0xff000, 0xff7ff) AM_READWRITE(mastboy_backupram_r,mastboy_backupram_w) AM_SHARE("nvram")
710	712
711	713	AM_RANGE(0xff800, 0xff807) AM_READ_PORT("P1")
712	714	AM_RANGE(0xff808, 0xff80f) AM_READ_PORT("P2")
713	715	AM_RANGE(0xff810, 0xff817) AM_READ_PORT("DSW1")
714	716	AM_RANGE(0xff818, 0xff81f) AM_READ_PORT("DSW2")
715	717
716		AM_RANGE(0xff820, 0xff827) AM_WRITE_LEGACY(mastboy_bank_w)
	718	AM_RANGE(0xff820, 0xff827) AM_WRITE(mastboy_bank_w)
717	719	AM_RANGE(0xff828, 0xff828) AM_DEVWRITE_LEGACY("saa", saa1099_data_w)
718	720	AM_RANGE(0xff829, 0xff829) AM_DEVWRITE_LEGACY("saa", saa1099_control_w)
719		AM_RANGE(0xff830, 0xff830) AM_WRITE_LEGACY(mastboy_msm5205_data_w)
720		AM_RANGE(0xff838, 0xff838) AM_WRITE_LEGACY(mastboy_irq0_ack_w)
721		AM_RANGE(0xff839, 0xff839) AM_WRITE_LEGACY(msm5205_mastboy_m5205_sambit0_w)
722		AM_RANGE(0xff83a, 0xff83a) AM_WRITE_LEGACY(msm5205_mastboy_m5205_sambit1_w)
	721	AM_RANGE(0xff830, 0xff830) AM_WRITE(mastboy_msm5205_data_w)
	722	AM_RANGE(0xff838, 0xff838) AM_WRITE(mastboy_irq0_ack_w)
	723	AM_RANGE(0xff839, 0xff839) AM_WRITE(msm5205_mastboy_m5205_sambit0_w)
	724	AM_RANGE(0xff83a, 0xff83a) AM_WRITE(msm5205_mastboy_m5205_sambit1_w)
723	725	AM_RANGE(0xff83b, 0xff83b) AM_DEVWRITE_LEGACY("msm", mastboy_msm5205_reset_w)
724		AM_RANGE(0xff83c, 0xff83c) AM_WRITE_LEGACY(backupram_enable_w)
	726	AM_RANGE(0xff83c, 0xff83c) AM_WRITE(backupram_enable_w)
725	727
726	728	AM_RANGE(0xffc00, 0xfffff) AM_RAM // Internal RAM
727	729	ADDRESS_MAP_END
728	730
729	731	/* Ports */
730	732
731		static READ8_HANDLER( mastboy_port_38_read )
	733	READ8_MEMBER(mastboy_state::mastboy_port_38_read)
732	734	{
733	735	return 0x00;
734	736	}
735	737
736		static READ8_HANDLER( mastboy_nmi_read )
	738	READ8_MEMBER(mastboy_state::mastboy_nmi_read)
737	739	{
738	740	// this is read in the NMI, it's related to the Z180 MMU I think, must return right value or game jumps to 0000
739	741	return 0x00;
740	742	}
741	743
742	744	static ADDRESS_MAP_START( mastboy_io_map, AS_IO, 8, mastboy_state )
743		AM_RANGE(0x38, 0x38) AM_READ_LEGACY(mastboy_port_38_read)
744		AM_RANGE(0x39, 0x39) AM_READ_LEGACY(mastboy_nmi_read)
	745	AM_RANGE(0x38, 0x38) AM_READ(mastboy_port_38_read)
	746	AM_RANGE(0x39, 0x39) AM_READ(mastboy_nmi_read)
745	747	ADDRESS_MAP_END
746	748
747	749	/* Input Ports */

src/mame/drivers/rmhaihai.c

r14845	r14846
45	45	UINT8 *m_colorram;
46	46	tilemap_t *m_bg_tilemap;
47	47	int m_keyboard_cmd;
	48	DECLARE_WRITE8_MEMBER(rmhaihai_videoram_w);
	49	DECLARE_WRITE8_MEMBER(rmhaihai_colorram_w);
	50	DECLARE_READ8_MEMBER(keyboard_r);
	51	DECLARE_WRITE8_MEMBER(keyboard_w);
	52	DECLARE_READ8_MEMBER(samples_r);
	53	DECLARE_WRITE8_MEMBER(ctrl_w);
	54	DECLARE_WRITE8_MEMBER(themj_rombank_w);
48	55	};
49	56
50	57
51	58
52		static WRITE8_HANDLER( rmhaihai_videoram_w )
	59	WRITE8_MEMBER(rmhaihai_state::rmhaihai_videoram_w)
53	60	{
54		rmhaihai_state *state = space->machine().driver_data<rmhaihai_state>();
55		state->m_videoram[offset] = data;
56		state->m_bg_tilemap->mark_tile_dirty(offset);
	61	m_videoram[offset] = data;
	62	m_bg_tilemap->mark_tile_dirty(offset);
57	63	}
58	64
59		static WRITE8_HANDLER( rmhaihai_colorram_w )
	65	WRITE8_MEMBER(rmhaihai_state::rmhaihai_colorram_w)
60	66	{
61		rmhaihai_state *state = space->machine().driver_data<rmhaihai_state>();
62		state->m_colorram[offset] = data;
63		state->m_bg_tilemap->mark_tile_dirty(offset);
	67	m_colorram[offset] = data;
	68	m_bg_tilemap->mark_tile_dirty(offset);
64	69	}
65	70
66	71	static TILE_GET_INFO( get_bg_tile_info )
r14845	r14846
90	95
91	96
92	97
93		static READ8_HANDLER( keyboard_r )
	98	READ8_MEMBER(rmhaihai_state::keyboard_r)
94	99	{
95		rmhaihai_state *state = space->machine().driver_data<rmhaihai_state>();
96	100	static const char *const keynames[] = { "KEY0", "KEY1" };
97	101
98		logerror("%04x: keyboard_r\n",cpu_get_pc(&space->device()));
99		switch(cpu_get_pc(&space->device()))
	102	logerror("%04x: keyboard_r\n",cpu_get_pc(&space.device()));
	103	switch(cpu_get_pc(&space.device()))
100	104	{
101	105	/* read keyboard */
102	106	case 0x0aba:   // rmhaihai, rmhaisei
r14845	r14846
108	112
109	113	for (i = 0; i < 31; i++)
110	114	{
111		if (input_port_read(space->machine(), keynames[i/16]) & (1 << (i & 15))) return i+1;
	115	if (input_port_read(machine(), keynames[i/16]) & (1 << (i & 15))) return i+1;
112	116	}
113		if (input_port_read(space->machine(), "KEY1") & 0x8000) return 0x80;   // coin
	117	if (input_port_read(machine(), "KEY1") & 0x8000) return 0x80;   // coin
114	118	return 0;
115	119	}
116	120	case 0x5c7b:   // rmhaihai, rmhaisei, rmhaijin
r14845	r14846
120	124
121	125
122	126	case 0x13a:   // additional checks done by rmhaijin
123		if (state->m_keyboard_cmd == 0x3b) return 0xdd;
124		if (state->m_keyboard_cmd == 0x85) return 0xdc;
125		if (state->m_keyboard_cmd == 0xf2) return 0xd6;
126		if (state->m_keyboard_cmd == 0xc1) return 0x8f;
127		if (state->m_keyboard_cmd == 0xd0) return 0x08;
	127	if (m_keyboard_cmd == 0x3b) return 0xdd;
	128	if (m_keyboard_cmd == 0x85) return 0xdc;
	129	if (m_keyboard_cmd == 0xf2) return 0xd6;
	130	if (m_keyboard_cmd == 0xc1) return 0x8f;
	131	if (m_keyboard_cmd == 0xd0) return 0x08;
128	132	return 0;
129	133
130	134	case 0x140:   // additional checks done by rmhaisei
131	135	case 0x155:   // additional checks done by themj, but they are patched out!
132		if (state->m_keyboard_cmd == 0x11) return 0x57;
133		if (state->m_keyboard_cmd == 0x3e) return 0xda;
134		if (state->m_keyboard_cmd == 0x48) return 0x74;
135		if (state->m_keyboard_cmd == 0x5d) return 0x46;
136		if (state->m_keyboard_cmd == 0xd0) return 0x08;
	136	if (m_keyboard_cmd == 0x11) return 0x57;
	137	if (m_keyboard_cmd == 0x3e) return 0xda;
	138	if (m_keyboard_cmd == 0x48) return 0x74;
	139	if (m_keyboard_cmd == 0x5d) return 0x46;
	140	if (m_keyboard_cmd == 0xd0) return 0x08;
137	141	return 0;
138	142	}
139	143
r14845	r14846
141	145	return 0;
142	146	}
143	147
144		static WRITE8_HANDLER( keyboard_w )
	148	WRITE8_MEMBER(rmhaihai_state::keyboard_w)
145	149	{
146		rmhaihai_state *state = space->machine().driver_data<rmhaihai_state>();
147		logerror("%04x: keyboard_w %02x\n",cpu_get_pc(&space->device()),data);
148		state->m_keyboard_cmd = data;
	150	logerror("%04x: keyboard_w %02x\n",cpu_get_pc(&space.device()),data);
	151	m_keyboard_cmd = data;
149	152	}
150	153
151		static READ8_HANDLER( samples_r )
	154	READ8_MEMBER(rmhaihai_state::samples_r)
152	155	{
153		return space->machine().region("adpcm")->base()[offset];
	156	return machine().region("adpcm")->base()[offset];
154	157	}
155	158
156	159	static WRITE8_DEVICE_HANDLER( adpcm_w )
r14845	r14846
160	163	msm5205_vclk_w (device,(data>>4)&1); /* bit4     */
161	164	}
162	165
163		static WRITE8_HANDLER( ctrl_w )
	166	WRITE8_MEMBER(rmhaihai_state::ctrl_w)
164	167	{
165		rmhaihai_state *state = space->machine().driver_data<rmhaihai_state>();
166		flip_screen_set(space->machine(), data & 0x01);
	168	flip_screen_set(machine(), data & 0x01);
167	169
168	170	// (data & 0x02) is switched on and off in service mode
169	171
170		coin_lockout_w(space->machine(), 0, ~data & 0x04);
171		coin_counter_w(space->machine(), 0, data & 0x08);
	172	coin_lockout_w(machine(), 0, ~data & 0x04);
	173	coin_counter_w(machine(), 0, data & 0x08);
172	174
173	175	// (data & 0x10) is medal in service mode
174	176
175		state->m_gfxbank = (data & 0x40) >> 6;   /* rmhaisei only */
	177	m_gfxbank = (data & 0x40) >> 6;   /* rmhaisei only */
176	178	}
177	179
178		static WRITE8_HANDLER( themj_rombank_w )
	180	WRITE8_MEMBER(rmhaihai_state::themj_rombank_w)
179	181	{
180		UINT8 *rom = space->machine().region("maincpu")->base() + 0x10000;
	182	UINT8 *rom = machine().region("maincpu")->base() + 0x10000;
181	183	int bank = data & 0x03;
182	184	logerror("banksw %d\n",bank);
183		memory_set_bankptr(space->machine(), "bank1", rom + bank*0x4000);
184		memory_set_bankptr(space->machine(), "bank2", rom + bank*0x4000 + 0x2000);
	185	memory_set_bankptr(machine(), "bank1", rom + bank*0x4000);
	186	memory_set_bankptr(machine(), "bank2", rom + bank*0x4000 + 0x2000);
185	187	}
186	188
187	189	static MACHINE_RESET( themj )
188	190	{
189		themj_rombank_w(machine.device("maincpu")->memory().space(AS_IO), 0, 0);
	191	rmhaihai_state *state = machine.driver_data<rmhaihai_state>();
	192	state->themj_rombank_w(*machine.device("maincpu")->memory().space(AS_IO), 0, 0);
190	193	}
191	194
192	195
r14845	r14846
194	197	static ADDRESS_MAP_START( rmhaihai_map, AS_PROGRAM, 8, rmhaihai_state )
195	198	AM_RANGE(0x0000, 0x9fff) AM_ROM
196	199	AM_RANGE(0xa000, 0xa7ff) AM_RAM
197		AM_RANGE(0xa800, 0xafff) AM_RAM_WRITE_LEGACY(rmhaihai_colorram_w) AM_BASE(m_colorram)
198		AM_RANGE(0xb000, 0xb7ff) AM_RAM_WRITE_LEGACY(rmhaihai_videoram_w) AM_BASE(m_videoram)
	200	AM_RANGE(0xa800, 0xafff) AM_RAM_WRITE(rmhaihai_colorram_w) AM_BASE(m_colorram)
	201	AM_RANGE(0xb000, 0xb7ff) AM_RAM_WRITE(rmhaihai_videoram_w) AM_BASE(m_videoram)
199	202	AM_RANGE(0xb83c, 0xb83c) AM_WRITENOP   // ??
200	203	AM_RANGE(0xbc00, 0xbc00) AM_WRITENOP   // ??
201	204	AM_RANGE(0xc000, 0xdfff) AM_ROM
r14845	r14846
203	206	ADDRESS_MAP_END
204	207
205	208	static ADDRESS_MAP_START( rmhaihai_io_map, AS_IO, 8, rmhaihai_state )
206		AM_RANGE(0x0000, 0x7fff) AM_READ_LEGACY(samples_r)
207		AM_RANGE(0x8000, 0x8000) AM_READ_LEGACY(keyboard_r) AM_WRITENOP   // ??
208		AM_RANGE(0x8001, 0x8001) AM_READNOP AM_WRITE_LEGACY(keyboard_w)   // ??
	209	AM_RANGE(0x0000, 0x7fff) AM_READ(samples_r)
	210	AM_RANGE(0x8000, 0x8000) AM_READ(keyboard_r) AM_WRITENOP   // ??
	211	AM_RANGE(0x8001, 0x8001) AM_READNOP AM_WRITE(keyboard_w)   // ??
209	212	AM_RANGE(0x8020, 0x8020) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
210	213	AM_RANGE(0x8020, 0x8021) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
211	214	AM_RANGE(0x8040, 0x8040) AM_DEVWRITE_LEGACY("msm", adpcm_w)
212		AM_RANGE(0x8060, 0x8060) AM_WRITE_LEGACY(ctrl_w)
	215	AM_RANGE(0x8060, 0x8060) AM_WRITE(ctrl_w)
213	216	AM_RANGE(0x8080, 0x8080) AM_WRITENOP   // ??
214	217	AM_RANGE(0xbc04, 0xbc04) AM_WRITENOP   // ??
215	218	AM_RANGE(0xbc0c, 0xbc0c) AM_WRITENOP   // ??
r14845	r14846
219	222	AM_RANGE(0x0000, 0x7fff) AM_ROM
220	223	AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("bank1")
221	224	AM_RANGE(0xa000, 0xa7ff) AM_RAM
222		AM_RANGE(0xa800, 0xafff) AM_RAM_WRITE_LEGACY(rmhaihai_colorram_w) AM_BASE(m_colorram)
223		AM_RANGE(0xb000, 0xb7ff) AM_RAM_WRITE_LEGACY(rmhaihai_videoram_w) AM_BASE(m_videoram)
	225	AM_RANGE(0xa800, 0xafff) AM_RAM_WRITE(rmhaihai_colorram_w) AM_BASE(m_colorram)
	226	AM_RANGE(0xb000, 0xb7ff) AM_RAM_WRITE(rmhaihai_videoram_w) AM_BASE(m_videoram)
224	227	AM_RANGE(0xc000, 0xdfff) AM_ROMBANK("bank2")
225	228	AM_RANGE(0xe000, 0xffff) AM_ROM
226	229	ADDRESS_MAP_END
227	230
228	231	static ADDRESS_MAP_START( themj_io_map, AS_IO, 8, rmhaihai_state )
229		AM_RANGE(0x0000, 0x7fff) AM_READ_LEGACY(samples_r)
230		AM_RANGE(0x8000, 0x8000) AM_READ_LEGACY(keyboard_r) AM_WRITENOP   // ??
231		AM_RANGE(0x8001, 0x8001) AM_READNOP AM_WRITE_LEGACY(keyboard_w)   // ??
	232	AM_RANGE(0x0000, 0x7fff) AM_READ(samples_r)
	233	AM_RANGE(0x8000, 0x8000) AM_READ(keyboard_r) AM_WRITENOP   // ??
	234	AM_RANGE(0x8001, 0x8001) AM_READNOP AM_WRITE(keyboard_w)   // ??
232	235	AM_RANGE(0x8020, 0x8020) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
233	236	AM_RANGE(0x8020, 0x8021) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
234	237	AM_RANGE(0x8040, 0x8040) AM_DEVWRITE_LEGACY("msm", adpcm_w)
235		AM_RANGE(0x8060, 0x8060) AM_WRITE_LEGACY(ctrl_w)
	238	AM_RANGE(0x8060, 0x8060) AM_WRITE(ctrl_w)
236	239	AM_RANGE(0x8080, 0x8080) AM_WRITENOP   // ??
237		AM_RANGE(0x80a0, 0x80a0) AM_WRITE_LEGACY(themj_rombank_w)
	240	AM_RANGE(0x80a0, 0x80a0) AM_WRITE(themj_rombank_w)
238	241	AM_RANGE(0xbc04, 0xbc04) AM_WRITENOP   // ??
239	242	AM_RANGE(0xbc0c, 0xbc0c) AM_WRITENOP   // ??
240	243	ADDRESS_MAP_END

src/mame/drivers/albazc.c

r14845	r14846
25	25	UINT8 *  m_spriteram2;
26	26	UINT8 *  m_spriteram3;
27	27	UINT8 m_flip_bit;
	28	DECLARE_WRITE8_MEMBER(hanaroku_out_0_w);
	29	DECLARE_WRITE8_MEMBER(hanaroku_out_1_w);
	30	DECLARE_WRITE8_MEMBER(hanaroku_out_2_w);
	31	DECLARE_WRITE8_MEMBER(albazc_vregs_w);
28	32	};
29	33
30	34
r14845	r14846
84	88	return 0;
85	89	}
86	90
87		static WRITE8_HANDLER( hanaroku_out_0_w )
	91	WRITE8_MEMBER(albazc_state::hanaroku_out_0_w)
88	92	{
89	93	/*
90	94	bit     description
r14845	r14846
99	103	7      meter5 (start)
100	104	*/
101	105
102		coin_counter_w(space->machine(), 0, data & 0x01);
103		coin_counter_w(space->machine(), 1, data & 0x02);
104		coin_counter_w(space->machine(), 2, data & 0x04);
105		coin_counter_w(space->machine(), 3, data & 0x08);
106		coin_counter_w(space->machine(), 4, data & 0x80);
	106	coin_counter_w(machine(), 0, data & 0x01);
	107	coin_counter_w(machine(), 1, data & 0x02);
	108	coin_counter_w(machine(), 2, data & 0x04);
	109	coin_counter_w(machine(), 3, data & 0x08);
	110	coin_counter_w(machine(), 4, data & 0x80);
107	111	}
108	112
109		static WRITE8_HANDLER( hanaroku_out_1_w )
	113	WRITE8_MEMBER(albazc_state::hanaroku_out_1_w)
110	114	{
111	115	/*
112	116	bit     description
r14845	r14846
122	126	*/
123	127	}
124	128
125		static WRITE8_HANDLER( hanaroku_out_2_w )
	129	WRITE8_MEMBER(albazc_state::hanaroku_out_2_w)
126	130	{
127	131	// unused
128	132	}
129	133
130		static WRITE8_HANDLER( albazc_vregs_w )
	134	WRITE8_MEMBER(albazc_state::albazc_vregs_w)
131	135	{
132		albazc_state *state = space->machine().driver_data<albazc_state>();
133	136
134	137	#ifdef UNUSED_FUNCTION
135	138	{
r14845	r14846
142	145	if(offset == 0)
143	146	{
144	147	/* core bug with this? */
145		//flip_screen_set(space->machine(), (data & 0x40) >> 6);
146		state->m_flip_bit = (data & 0x40) >> 6;
	148	//flip_screen_set(machine(), (data & 0x40) >> 6);
	149	m_flip_bit = (data & 0x40) >> 6;
147	150	}
148	151	}
149	152
r14845	r14846
155	158	AM_RANGE(0x9000, 0x97ff) AM_RAM AM_BASE(m_spriteram2)
156	159	AM_RANGE(0xa000, 0xa1ff) AM_RAM AM_BASE(m_spriteram3)
157	160	AM_RANGE(0xa200, 0xa2ff) AM_WRITENOP   // ??? written once during P.O.S.T.
158		AM_RANGE(0xa300, 0xa304) AM_WRITE_LEGACY(albazc_vregs_w)   // ???
	161	AM_RANGE(0xa300, 0xa304) AM_WRITE(albazc_vregs_w)   // ???
159	162	AM_RANGE(0xb000, 0xb000) AM_WRITENOP   // ??? always 0x40
160	163	AM_RANGE(0xc000, 0xc3ff) AM_RAM         // main ram
161	164	AM_RANGE(0xc400, 0xc4ff) AM_RAM         // ???
162	165	AM_RANGE(0xd000, 0xd000) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
163	166	AM_RANGE(0xd000, 0xd001) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
164		AM_RANGE(0xe000, 0xe000) AM_READ_PORT("IN0") AM_WRITE_LEGACY(hanaroku_out_0_w)
	167	AM_RANGE(0xe000, 0xe000) AM_READ_PORT("IN0") AM_WRITE(hanaroku_out_0_w)
165	168	AM_RANGE(0xe001, 0xe001) AM_READ_PORT("IN1")
166		AM_RANGE(0xe002, 0xe002) AM_READ_PORT("IN2") AM_WRITE_LEGACY(hanaroku_out_1_w)
167		AM_RANGE(0xe004, 0xe004) AM_READ_PORT("DSW3") AM_WRITE_LEGACY(hanaroku_out_2_w)
	169	AM_RANGE(0xe002, 0xe002) AM_READ_PORT("IN2") AM_WRITE(hanaroku_out_1_w)
	170	AM_RANGE(0xe004, 0xe004) AM_READ_PORT("DSW3") AM_WRITE(hanaroku_out_2_w)
168	171	ADDRESS_MAP_END
169	172
170	173

src/mame/drivers/midas.c

r14845	r14846
66	66	UINT16 *m_gfxram;
67	67	UINT16 *m_gfxregs;
68	68	tilemap_t *m_tmap;
	69	DECLARE_READ16_MEMBER(ret_ffff);
	70	DECLARE_WRITE16_MEMBER(midas_gfxregs_w);
	71	DECLARE_WRITE16_MEMBER(livequiz_coin_w);
	72	DECLARE_READ16_MEMBER(hammer_sensor_r);
	73	DECLARE_WRITE16_MEMBER(hammer_coin_w);
	74	DECLARE_WRITE16_MEMBER(hammer_motor_w);
	75	DECLARE_WRITE16_MEMBER(hammer_led_w);
69	76	};
70	77
71	78
r14845	r14846
214	221	}
215	222	}
216	223
217		static READ16_HANDLER( ret_ffff )
	224	READ16_MEMBER(midas_state::ret_ffff)
218	225	{
219	226	return 0xffff;
220	227	}
221	228
222		static WRITE16_HANDLER( midas_gfxregs_w )
	229	WRITE16_MEMBER(midas_state::midas_gfxregs_w)
223	230	{
224		midas_state *state = space->machine().driver_data<midas_state>();
225		COMBINE_DATA( state->m_gfxregs + offset );
	231	COMBINE_DATA( m_gfxregs + offset );
226	232
227	233	switch( offset )
228	234	{
229	235	case 1:
230	236	{
231		UINT16 addr = state->m_gfxregs[0];
232		state->m_gfxram[addr] = data;
233		state->m_gfxregs[0] += state->m_gfxregs[2];
	237	UINT16 addr = m_gfxregs[0];
	238	m_gfxram[addr] = data;
	239	m_gfxregs[0] += m_gfxregs[2];
234	240
235		if ( addr >= 0x7000 && addr <= 0x7fff )   state->m_tmap->mark_tile_dirty(addr - 0x7000);
	241	if ( addr >= 0x7000 && addr <= 0x7fff )   m_tmap->mark_tile_dirty(addr - 0x7000);
236	242
237	243	break;
238	244	}
r14845	r14846
243	249	Live Quiz Show
244	250	***************************************************************************************/
245	251
246		static WRITE16_HANDLER( livequiz_coin_w )
	252	WRITE16_MEMBER(midas_state::livequiz_coin_w)
247	253	{
248	254	if (ACCESSING_BITS_0_7)
249	255	{
250		coin_counter_w(space->machine(), 0, data & 0x0001);
	256	coin_counter_w(machine(), 0, data & 0x0001);
251	257	}
252	258	#ifdef MAME_DEBUG
253	259	//  popmessage("coin %04X", data);
r14845	r14846
262	268	AM_RANGE(0x940000, 0x940001) AM_READ_PORT("PLAYER2")
263	269	AM_RANGE(0x980000, 0x980001) AM_READ_PORT("START")
264	270
265		AM_RANGE(0x980000, 0x980001) AM_WRITE_LEGACY(livequiz_coin_w )
	271	AM_RANGE(0x980000, 0x980001) AM_WRITE(livequiz_coin_w )
266	272
267	273	AM_RANGE(0x9a0000, 0x9a0001) AM_DEVWRITE_LEGACY("eeprom", midas_eeprom_w )
268	274
269		AM_RANGE(0x9c0000, 0x9c0005) AM_WRITE_LEGACY(midas_gfxregs_w ) AM_BASE(m_gfxregs )
	275	AM_RANGE(0x9c0000, 0x9c0005) AM_WRITE(midas_gfxregs_w ) AM_BASE(m_gfxregs )
270	276
271	277	AM_RANGE(0xa00000, 0xa3ffff) AM_RAM_WRITE_LEGACY(paletteram16_xrgb_word_be_w ) AM_BASE_GENERIC( paletteram )
272	278	AM_RANGE(0xa40000, 0xa7ffff) AM_RAM
273	279
274		AM_RANGE(0xb00000, 0xb00001) AM_READ_LEGACY(ret_ffff )
275		AM_RANGE(0xb20000, 0xb20001) AM_READ_LEGACY(ret_ffff )
276		AM_RANGE(0xb40000, 0xb40001) AM_READ_LEGACY(ret_ffff )
277		AM_RANGE(0xb60000, 0xb60001) AM_READ_LEGACY(ret_ffff )
	280	AM_RANGE(0xb00000, 0xb00001) AM_READ(ret_ffff )
	281	AM_RANGE(0xb20000, 0xb20001) AM_READ(ret_ffff )
	282	AM_RANGE(0xb40000, 0xb40001) AM_READ(ret_ffff )
	283	AM_RANGE(0xb60000, 0xb60001) AM_READ(ret_ffff )
278	284
279	285	AM_RANGE(0xb80008, 0xb8000b) AM_DEVREADWRITE8_LEGACY("ymz", ymz280b_r, ymz280b_w, 0x00ff )
280	286
r14845	r14846
290	296	Hammer
291	297	***************************************************************************************/
292	298
293		static READ16_HANDLER( hammer_sensor_r )
	299	READ16_MEMBER(midas_state::hammer_sensor_r)
294	300	{
295		if (input_port_read(space->machine(), "HAMMER") & 0x80)
	301	if (input_port_read(machine(), "HAMMER") & 0x80)
296	302	return 0xffff;
297	303
298		return (input_port_read(space->machine(), "SENSORY") << 8) | input_port_read(space->machine(), "SENSORX");
	304	return (input_port_read(machine(), "SENSORY") << 8) | input_port_read(machine(), "SENSORX");
299	305	}
300	306
301		static WRITE16_HANDLER( hammer_coin_w )
	307	WRITE16_MEMBER(midas_state::hammer_coin_w)
302	308	{
303	309	if (ACCESSING_BITS_0_7)
304	310	{
305		coin_counter_w(space->machine(), 0, data & 0x0001);
306		coin_counter_w(space->machine(), 1, data & 0x0002);
	311	coin_counter_w(machine(), 0, data & 0x0001);
	312	coin_counter_w(machine(), 1, data & 0x0002);
307	313	}
308	314	#ifdef MAME_DEBUG
309	315	//  popmessage("coin %04X", data);
310	316	#endif
311	317	}
312	318
313		static WRITE16_HANDLER( hammer_motor_w )
	319	WRITE16_MEMBER(midas_state::hammer_motor_w)
314	320	{
315	321	if (ACCESSING_BITS_0_7)
316	322	{
317		ticket_dispenser_w(space->machine().device("prize1"), 0, (data & 0x0001) << 7);
318		ticket_dispenser_w(space->machine().device("prize2"), 0, (data & 0x0002) << 6);
319		ticket_dispenser_w(space->machine().device("ticket"), 0, (data & 0x0010) << 3);
	323	ticket_dispenser_w(machine().device("prize1"), 0, (data & 0x0001) << 7);
	324	ticket_dispenser_w(machine().device("prize2"), 0, (data & 0x0002) << 6);
	325	ticket_dispenser_w(machine().device("ticket"), 0, (data & 0x0010) << 3);
320	326	// data & 0x0080 ?
321	327	}
322	328	#ifdef MAME_DEBUG
r14845	r14846
324	330	#endif
325	331	}
326	332
327		static WRITE16_HANDLER( hammer_led_w )
	333	WRITE16_MEMBER(midas_state::hammer_led_w)
328	334	{
329	335	#ifdef MAME_DEBUG
330	336	//  popmessage("led %04X", data);
r14845	r14846
339	345	AM_RANGE(0x940000, 0x940001) AM_READ_PORT("IN0")
340	346	AM_RANGE(0x980000, 0x980001) AM_READ_PORT("TILT")
341	347
342		AM_RANGE(0x980000, 0x980001) AM_WRITE_LEGACY(hammer_coin_w )
	348	AM_RANGE(0x980000, 0x980001) AM_WRITE(hammer_coin_w )
343	349	AM_RANGE(0x9c000c, 0x9c000d) AM_WRITENOP   // IRQ Ack
344		AM_RANGE(0x9c000e, 0x9c000f) AM_WRITE_LEGACY(hammer_led_w )
	350	AM_RANGE(0x9c000e, 0x9c000f) AM_WRITE(hammer_led_w )
345	351
346	352	AM_RANGE(0x9a0000, 0x9a0001) AM_DEVWRITE_LEGACY("eeprom", midas_eeprom_w )
347	353
348		AM_RANGE(0x9c0000, 0x9c0005) AM_WRITE_LEGACY(midas_gfxregs_w ) AM_BASE(m_gfxregs )
	354	AM_RANGE(0x9c0000, 0x9c0005) AM_WRITE(midas_gfxregs_w ) AM_BASE(m_gfxregs )
349	355
350	356	AM_RANGE(0xa00000, 0xa3ffff) AM_RAM_WRITE_LEGACY(paletteram16_xrgb_word_be_w ) AM_BASE_GENERIC( paletteram )
351	357	AM_RANGE(0xa40000, 0xa7ffff) AM_RAM
352	358
353		AM_RANGE(0xb00000, 0xb00001) AM_READ_LEGACY(ret_ffff )
354		AM_RANGE(0xb20000, 0xb20001) AM_READ_LEGACY(ret_ffff )
355		AM_RANGE(0xb40000, 0xb40001) AM_READ_LEGACY(ret_ffff )
356		AM_RANGE(0xb60000, 0xb60001) AM_READ_LEGACY(ret_ffff )
	359	AM_RANGE(0xb00000, 0xb00001) AM_READ(ret_ffff )
	360	AM_RANGE(0xb20000, 0xb20001) AM_READ(ret_ffff )
	361	AM_RANGE(0xb40000, 0xb40001) AM_READ(ret_ffff )
	362	AM_RANGE(0xb60000, 0xb60001) AM_READ(ret_ffff )
357	363
358	364	AM_RANGE(0xb80008, 0xb8000b) AM_DEVREADWRITE8_LEGACY("ymz", ymz280b_r, ymz280b_w, 0x00ff )
359	365
360	366	AM_RANGE(0xba0000, 0xba0001) AM_READ_PORT("IN1")
361	367	AM_RANGE(0xbc0000, 0xbc0001) AM_READ_PORT("HAMMER")
362	368
363		AM_RANGE(0xbc0002, 0xbc0003) AM_WRITE_LEGACY(hammer_motor_w )
	369	AM_RANGE(0xbc0002, 0xbc0003) AM_WRITE(hammer_motor_w )
364	370
365		AM_RANGE(0xbc0004, 0xbc0005) AM_READ_LEGACY(hammer_sensor_r )
	371	AM_RANGE(0xbc0004, 0xbc0005) AM_READ(hammer_sensor_r )
366	372
367	373	AM_RANGE(0xd00000, 0xd1ffff) AM_RAM   // zoom table?
368	374

src/mame/drivers/aristmk4.c

r14845	r14846
282	282	int m_insnote;
283	283	int m_cashcade_c;
284	284	int m_printer_motor;
	285	DECLARE_READ8_MEMBER(ldsw);
	286	DECLARE_READ8_MEMBER(cgdrr);
	287	DECLARE_WRITE8_MEMBER(cgdrw);
	288	DECLARE_WRITE8_MEMBER(u3_p0);
	289	DECLARE_READ8_MEMBER(u3_p2);
	290	DECLARE_READ8_MEMBER(u3_p3);
	291	DECLARE_READ8_MEMBER(bv_p0);
	292	DECLARE_READ8_MEMBER(bv_p1);
	293	DECLARE_READ8_MEMBER(mkiv_pia_ina);
	294	DECLARE_WRITE8_MEMBER(mkiv_pia_outa);
	295	DECLARE_WRITE8_MEMBER(mlamps);
	296	DECLARE_READ8_MEMBER(cashcade_r);
	297	DECLARE_WRITE8_MEMBER(mk4_printer_w);
	298	DECLARE_READ8_MEMBER(mk4_printer_r);
285	299	};
286	300
287	301	/* Partial Cashcade protocol */
r14845	r14846
362	376	return 0;
363	377	}
364	378
365		static READ8_HANDLER(ldsw)
	379	READ8_MEMBER(aristmk4_state::ldsw)
366	380	{
367		aristmk4_state *state = space->machine().driver_data<aristmk4_state>();
368	381
369		int U3_p2_ret= input_port_read(space->machine(), "5002");
	382	int U3_p2_ret= input_port_read(machine(), "5002");
370	383	if(U3_p2_ret & 0x1)
371	384	{
372	385	return 0;
373	386	}
374		return state->m_cgdrsw = input_port_read(space->machine(), "5005");
	387	return m_cgdrsw = input_port_read(machine(), "5005");
375	388	}
376	389
377		static READ8_HANDLER(cgdrr)
	390	READ8_MEMBER(aristmk4_state::cgdrr)
378	391	{
379		aristmk4_state *state = space->machine().driver_data<aristmk4_state>();
380	392
381		if(state->m_cgdrsw) // is the LC closed
	393	if(m_cgdrsw) // is the LC closed
382	394	{
383		return state->m_ripple; // return a positive value from the ripple counter
	395	return m_ripple; // return a positive value from the ripple counter
384	396	}
385	397	return 0x0; // otherwise the counter outputs are set low.
386	398	}
387	399
388		static WRITE8_HANDLER(cgdrw)
	400	WRITE8_MEMBER(aristmk4_state::cgdrw)
389	401	{
390		aristmk4_state *state = space->machine().driver_data<aristmk4_state>();
391	402
392		state->m_ripple = data;
	403	m_ripple = data;
393	404	}
394	405
395		static WRITE8_HANDLER(u3_p0)
	406	WRITE8_MEMBER(aristmk4_state::u3_p0)
396	407	{
397		aristmk4_state *state = space->machine().driver_data<aristmk4_state>();
398	408
399		state->m_u3_p0_w = data;
	409	m_u3_p0_w = data;
400	410
401	411	if ((data&0x80)==0) //Printer Motor Off
402	412	{
403		state->m_printer_motor = 1; // Set this so the next read of u3_p3 returns PTRHOM as OFF.
	413	m_printer_motor = 1; // Set this so the next read of u3_p3 returns PTRHOM as OFF.
404	414	}
405	415
406		//logerror("u3_p0_w: %02X\n",state->m_u3_p0_w);
	416	//logerror("u3_p0_w: %02X\n",m_u3_p0_w);
407	417	}
408	418
409		static READ8_HANDLER(u3_p2)
	419	READ8_MEMBER(aristmk4_state::u3_p2)
410	420	{
411		aristmk4_state *state = space->machine().driver_data<aristmk4_state>();
412	421
413		int u3_p2_ret= input_port_read(space->machine(), "5002");
414		int u3_p3_ret= input_port_read(space->machine(), "5003");
	422	int u3_p2_ret= input_port_read(machine(), "5002");
	423	int u3_p3_ret= input_port_read(machine(), "5003");
415	424
416	425	output_set_lamp_value(19, (u3_p2_ret >> 4) & 1); //auditkey light
417	426	output_set_lamp_value(20, (u3_p3_ret >> 2) & 1); //jackpotkey light
418	427
419		if (state->m_u3_p0_w&0x20) // DOPTE on
	428	if (m_u3_p0_w&0x20) // DOPTE on
420	429	{
421	430	if (u3_p3_ret&0x02) // door closed
422	431	u3_p2_ret = u3_p2_ret^0x08; // DOPTI on
423	432	}
424	433
425		if (state->m_inscrd==0)
	434	if (m_inscrd==0)
426	435	{
427		state->m_inscrd=input_port_read(space->machine(), "insertcoin");
	436	m_inscrd=input_port_read(machine(), "insertcoin");
428	437	}
429	438
430		if (state->m_inscrd==1)
	439	if (m_inscrd==1)
431	440	u3_p2_ret=u3_p2_ret^0x02;
432	441
433	442	return u3_p2_ret;
434	443	}
435	444
436		static READ8_HANDLER(u3_p3)
	445	READ8_MEMBER(aristmk4_state::u3_p3)
437	446	{
438		aristmk4_state *state = space->machine().driver_data<aristmk4_state>();
439	447
440		int u3_p3_ret= input_port_read(space->machine(), "5003");
	448	int u3_p3_ret= input_port_read(machine(), "5003");
441	449
442		if ((state->m_printer_motor)==1) // Printer Motor Off
	450	if ((m_printer_motor)==1) // Printer Motor Off
443	451
444	452	{
445	453	u3_p3_ret = u3_p3_ret^0x80; // Printer Home Off
446		state->m_printer_motor=0;
	454	m_printer_motor=0;
447	455
448	456	}
449	457
r14845	r14846
457	465	state->m_insnote=0; //reset note input after 150msec
458	466	}
459	467
460		static READ8_HANDLER(bv_p0)
	468	READ8_MEMBER(aristmk4_state::bv_p0)
461	469	{
462		aristmk4_state *state = space->machine().driver_data<aristmk4_state>();
463	470
464	471	int bv_p0_ret=0x00;
465	472
466		switch(state->m_insnote)
	473	switch(m_insnote)
467	474	{
468	475	case 0x01:
469		bv_p0_ret=input_port_read(space->machine(), "NS")+0x81; //check note selector
470		state->m_insnote++;
	476	bv_p0_ret=input_port_read(machine(), "NS")+0x81; //check note selector
	477	m_insnote++;
471	478	break;
472	479	case 0x02:
473	480	bv_p0_ret=0x89;
474		state->m_insnote++;
475		space->machine().scheduler().timer_set(attotime::from_msec(150), FUNC(note_input_reset));
	481	m_insnote++;
	482	machine().scheduler().timer_set(attotime::from_msec(150), FUNC(note_input_reset));
476	483	break;
477	484	default:
478	485	break; //timer will reset the input
r14845	r14846
482	489
483	490	}
484	491
485		static READ8_HANDLER(bv_p1)
	492	READ8_MEMBER(aristmk4_state::bv_p1)
486	493	{
487		aristmk4_state *state = space->machine().driver_data<aristmk4_state>();
488	494
489	495	int bv_p1_ret=0x00;
490	496
491		if (state->m_insnote==0)
492		state->m_insnote=input_port_read(space->machine(), "insertnote");
	497	if (m_insnote==0)
	498	m_insnote=input_port_read(machine(), "insertnote");
493	499
494		if (state->m_insnote==1)
	500	if (m_insnote==1)
495	501	bv_p1_ret=0x08;
496	502
497		if (state->m_insnote==2)
	503	if (m_insnote==2)
498	504	bv_p1_ret=0x08;
499	505
500	506	return bv_p1_ret;
r14845	r14846
516	522	******************************************************************************/
517	523
518	524	//input a
519		static READ8_HANDLER(mkiv_pia_ina)
	525	READ8_MEMBER(aristmk4_state::mkiv_pia_ina)
520	526	{
521	527	/* uncomment this code once RTC is fixed */
522	528
523		//return space->machine().device<mc146818_device>("rtc")->read(*space,1);
	529	//return machine().device<mc146818_device>("rtc")->read(*&space,1);
524	530	return 0;   // OK for now, the aussie version has no RTC on the MB so this is valid.
525	531	}
526	532
527	533	//output a
528		static WRITE8_HANDLER(mkiv_pia_outa)
	534	WRITE8_MEMBER(aristmk4_state::mkiv_pia_outa)
529	535	{
530		aristmk4_state *state = space->machine().driver_data<aristmk4_state>();
531		mc146818_device *mc = space->machine().device<mc146818_device>("rtc");
532		if(state->m_rtc_data_strobe)
	536	mc146818_device *mc = machine().device<mc146818_device>("rtc");
	537	if(m_rtc_data_strobe)
533	538	{
534		mc->write(*space,1,data);
	539	mc->write(*&space,1,data);
535	540	//logerror("rtc protocol write data: %02X\n",data);
536	541	}
537	542	else
538	543	{
539		mc->write(*space,0,data);
	544	mc->write(*&space,0,data);
540	545	//logerror("rtc protocol write address: %02X\n",data);
541	546	}
542	547	}
r14845	r14846
832	837	//logerror("Lights port B: %02X\n",data);
833	838	}
834	839
835		static WRITE8_HANDLER(mlamps)
	840	WRITE8_MEMBER(aristmk4_state::mlamps)
836	841	{
837	842	/* TAKE WIN AND GAMBLE LAMPS */
838	843	output_set_lamp_value(18, (data >> 5) & 1);
r14845	r14846
847	852	}
848	853
849	854
850		static READ8_HANDLER(cashcade_r)
	855	READ8_MEMBER(aristmk4_state::cashcade_r)
851	856	{
852		aristmk4_state *state = space->machine().driver_data<aristmk4_state>();
853	857	/* work around for cashcade games */
854		return cashcade_p[(state->m_cashcade_c++)%15];
	858	return cashcade_p[(m_cashcade_c++)%15];
855	859	}
856	860
857		static WRITE8_HANDLER(mk4_printer_w)
	861	WRITE8_MEMBER(aristmk4_state::mk4_printer_w)
858	862	{
859	863	//logerror("Printer: %c %d\n",data,data);
860	864	}
861	865
862		static READ8_HANDLER(mk4_printer_r)
	866	READ8_MEMBER(aristmk4_state::mk4_printer_r)
863	867	{
864	868	return 0;
865	869	}
r14845	r14846
875	879	AM_RANGE(0x0800, 0x17ff) AM_RAM
876	880	AM_RANGE(0x1800, 0x1800) AM_DEVREADWRITE("crtc", mc6845_device, status_r, address_w)
877	881	AM_RANGE(0x1801, 0x1801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
878		AM_RANGE(0x1c00, 0x1cff) AM_WRITE_LEGACY(mk4_printer_w)
879		AM_RANGE(0x1900, 0x19ff) AM_READ_LEGACY(mk4_printer_r)
	882	AM_RANGE(0x1c00, 0x1cff) AM_WRITE(mk4_printer_w)
	883	AM_RANGE(0x1900, 0x19ff) AM_READ(mk4_printer_r)
880	884	AM_RANGE(0x2000, 0x3fff) AM_ROM  // graphics rom map
881	885	AM_RANGE(0x4000, 0x4fff) AM_RAMBANK("bank1") AM_SHARE("nvram")
882	886
883		AM_RANGE(0x5000, 0x5000) AM_WRITE_LEGACY(u3_p0)
884		AM_RANGE(0x5002, 0x5002) AM_READ_LEGACY(u3_p2)
885		AM_RANGE(0x5003, 0x5003) AM_READ_LEGACY(u3_p3)
886		AM_RANGE(0x5005, 0x5005) AM_READ_LEGACY(ldsw)
	887	AM_RANGE(0x5000, 0x5000) AM_WRITE(u3_p0)
	888	AM_RANGE(0x5002, 0x5002) AM_READ(u3_p2)
	889	AM_RANGE(0x5003, 0x5003) AM_READ(u3_p3)
	890	AM_RANGE(0x5005, 0x5005) AM_READ(ldsw)
887	891	AM_RANGE(0x500d, 0x500d) AM_READ_PORT("500d")
888	892	AM_RANGE(0x500e, 0x500e) AM_READ_PORT("500e")
889	893	AM_RANGE(0x500f, 0x500f) AM_READ_PORT("500f")
890	894	AM_RANGE(0x5010, 0x501f) AM_DEVREADWRITE("via6522_0",via6522_device,read,write)
891		AM_RANGE(0x5200, 0x5200) AM_READ_LEGACY(cashcade_r)
	895	AM_RANGE(0x5200, 0x5200) AM_READ(cashcade_r)
892	896	AM_RANGE(0x5201, 0x5201) AM_READ_PORT("5201")
893		AM_RANGE(0x52c0, 0x52c0) AM_READ_LEGACY(bv_p0)
894		AM_RANGE(0x52c1, 0x52c1) AM_READ_LEGACY(bv_p1)
	897	AM_RANGE(0x52c0, 0x52c0) AM_READ(bv_p0)
	898	AM_RANGE(0x52c1, 0x52c1) AM_READ(bv_p1)
895	899	AM_RANGE(0x527f, 0x5281) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
896	900	AM_RANGE(0x5300, 0x5300) AM_READ_PORT("5300")
897	901	AM_RANGE(0x5380, 0x5383) AM_DEVREADWRITE("pia6821_0", pia6821_device, read, write)  // RTC data - PORT A , mechanical meters - PORTB ??
898		AM_RANGE(0x5440, 0x5440) AM_WRITE_LEGACY(mlamps) // take win and gamble lamps
899		AM_RANGE(0x5468, 0x5468) AM_READWRITE_LEGACY(cgdrr,cgdrw) // 4020 ripple counter outputs
	902	AM_RANGE(0x5440, 0x5440) AM_WRITE(mlamps) // take win and gamble lamps
	903	AM_RANGE(0x5468, 0x5468) AM_READWRITE(cgdrr,cgdrw) // 4020 ripple counter outputs
900	904	AM_RANGE(0x6000, 0xffff) AM_ROM  // game roms
901	905	ADDRESS_MAP_END
902	906
r14845	r14846
919	923	AM_RANGE(0x0800, 0x17ff) AM_RAM
920	924	AM_RANGE(0x1800, 0x1800) AM_DEVREADWRITE("crtc", mc6845_device, status_r, address_w)
921	925	AM_RANGE(0x1801, 0x1801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
922		AM_RANGE(0x1c00, 0x1cff) AM_WRITE_LEGACY(mk4_printer_w)
923		AM_RANGE(0x1900, 0x19ff) AM_READ_LEGACY(mk4_printer_r)
	926	AM_RANGE(0x1c00, 0x1cff) AM_WRITE(mk4_printer_w)
	927	AM_RANGE(0x1900, 0x19ff) AM_READ(mk4_printer_r)
924	928	AM_RANGE(0x4000, 0x4fff) AM_RAMBANK("bank1") AM_SHARE("nvram")
925	929
926		AM_RANGE(0x5000, 0x5000) AM_WRITE_LEGACY(u3_p0)
927		AM_RANGE(0x5002, 0x5002) AM_READ_LEGACY(u3_p2)
	930	AM_RANGE(0x5000, 0x5000) AM_WRITE(u3_p0)
	931	AM_RANGE(0x5002, 0x5002) AM_READ(u3_p2)
928	932	AM_RANGE(0x5003, 0x5003) AM_READ_PORT("5003")
929		AM_RANGE(0x5005, 0x5005) AM_READ_LEGACY(ldsw)
	933	AM_RANGE(0x5005, 0x5005) AM_READ(ldsw)
930	934	AM_RANGE(0x500d, 0x500d) AM_READ_PORT("500d")
931	935	AM_RANGE(0x500e, 0x500e) AM_READ_PORT("500e")
932	936	AM_RANGE(0x500f, 0x500f) AM_READ_PORT("500f")
933	937	AM_RANGE(0x5010, 0x501f) AM_DEVREADWRITE("via6522_0",via6522_device,read,write)
934		AM_RANGE(0x5200, 0x5200) AM_READ_LEGACY(cashcade_r)
	938	AM_RANGE(0x5200, 0x5200) AM_READ(cashcade_r)
935	939	AM_RANGE(0x5201, 0x5201) AM_READ_PORT("5201")
936		AM_RANGE(0x52c0, 0x52c0) AM_READ_LEGACY(bv_p0)
937		AM_RANGE(0x52c1, 0x52c1) AM_READ_LEGACY(bv_p1)
	940	AM_RANGE(0x52c0, 0x52c0) AM_READ(bv_p0)
	941	AM_RANGE(0x52c1, 0x52c1) AM_READ(bv_p1)
938	942	AM_RANGE(0x527f, 0x5281) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
939	943	AM_RANGE(0x5300, 0x5300) AM_READ_PORT("5300")
940	944	AM_RANGE(0x5380, 0x5383) AM_DEVREADWRITE("pia6821_0", pia6821_device, read, write)  // RTC data - PORT A , mechanical meters - PORTB ??
941		AM_RANGE(0x5440, 0x5440) AM_WRITE_LEGACY(mlamps) // take win and gamble lamps
942		AM_RANGE(0x5468, 0x5468) AM_READWRITE_LEGACY(cgdrr,cgdrw) // 4020 ripple counter outputs
	945	AM_RANGE(0x5440, 0x5440) AM_WRITE(mlamps) // take win and gamble lamps
	946	AM_RANGE(0x5468, 0x5468) AM_READWRITE(cgdrr,cgdrw) // 4020 ripple counter outputs
943	947	AM_RANGE(0x6000, 0x7fff) AM_ROM  // graphics rom map
944	948	AM_RANGE(0x8000, 0xffff) AM_ROM  // game roms
945	949	ADDRESS_MAP_END
r14845	r14846
1521	1525
1522	1526	static const pia6821_interface aristmk4_pia1_intf =
1523	1527	{
1524		DEVCB_MEMORY_HANDLER("maincpu",PROGRAM,mkiv_pia_ina),   // port A in
	1528	DEVCB_DRIVER_MEMBER(aristmk4_state, mkiv_pia_ina),   // port A in
1525	1529	DEVCB_NULL,   // port B in
1526	1530	DEVCB_NULL,   // line CA1 in
1527	1531	DEVCB_NULL,   // line CB1 in
1528	1532	DEVCB_NULL,   // line CA2 in
1529	1533	DEVCB_NULL,   // line CB2 in
1530		DEVCB_MEMORY_HANDLER("maincpu",PROGRAM,mkiv_pia_outa),   // port A out
	1534	DEVCB_DRIVER_MEMBER(aristmk4_state, mkiv_pia_outa),   // port A out
1531	1535	DEVCB_HANDLER(mkiv_pia_outb),   // port B out
1532	1536	DEVCB_HANDLER(mkiv_pia_ca2),   // line CA2 out
1533	1537	DEVCB_HANDLER(mkiv_pia_cb2),   // port CB2 out

src/mame/drivers/galaxi.c

r14845	r14846
71	71	int       m_hopper;
72	72	int       m_ticket;
73	73	UINT16    m_out[3];
	74	DECLARE_WRITE16_MEMBER(galaxi_bg1_w);
	75	DECLARE_WRITE16_MEMBER(galaxi_bg2_w);
	76	DECLARE_WRITE16_MEMBER(galaxi_bg3_w);
	77	DECLARE_WRITE16_MEMBER(galaxi_bg4_w);
	78	DECLARE_WRITE16_MEMBER(galaxi_fg_w);
	79	DECLARE_WRITE16_MEMBER(galaxi_500000_w);
	80	DECLARE_WRITE16_MEMBER(galaxi_500002_w);
	81	DECLARE_WRITE16_MEMBER(galaxi_500004_w);
74	82	};
75	83
76	84
r14845	r14846
113	121	SET_TILE_INFO(1, code, 0x20 + (code >> 12), 0);
114	122	}
115	123
116		static WRITE16_HANDLER( galaxi_bg1_w )
	124	WRITE16_MEMBER(galaxi_state::galaxi_bg1_w)
117	125	{
118		galaxi_state *state = space->machine().driver_data<galaxi_state>();
119		COMBINE_DATA(&state->m_bg1_ram[offset]);
120		state->m_bg1_tmap->mark_tile_dirty(offset);
	126	COMBINE_DATA(&m_bg1_ram[offset]);
	127	m_bg1_tmap->mark_tile_dirty(offset);
121	128	}
122	129
123		static WRITE16_HANDLER( galaxi_bg2_w )
	130	WRITE16_MEMBER(galaxi_state::galaxi_bg2_w)
124	131	{
125		galaxi_state *state = space->machine().driver_data<galaxi_state>();
126		COMBINE_DATA(&state->m_bg2_ram[offset]);
127		state->m_bg2_tmap->mark_tile_dirty(offset);
	132	COMBINE_DATA(&m_bg2_ram[offset]);
	133	m_bg2_tmap->mark_tile_dirty(offset);
128	134	}
129	135
130		static WRITE16_HANDLER( galaxi_bg3_w )
	136	WRITE16_MEMBER(galaxi_state::galaxi_bg3_w)
131	137	{
132		galaxi_state *state = space->machine().driver_data<galaxi_state>();
133		COMBINE_DATA(&state->m_bg3_ram[offset]);
134		state->m_bg3_tmap->mark_tile_dirty(offset);
	138	COMBINE_DATA(&m_bg3_ram[offset]);
	139	m_bg3_tmap->mark_tile_dirty(offset);
135	140	}
136	141
137		static WRITE16_HANDLER( galaxi_bg4_w )
	142	WRITE16_MEMBER(galaxi_state::galaxi_bg4_w)
138	143	{
139		galaxi_state *state = space->machine().driver_data<galaxi_state>();
140		COMBINE_DATA(&state->m_bg4_ram[offset]);
141		state->m_bg4_tmap->mark_tile_dirty(offset);
	144	COMBINE_DATA(&m_bg4_ram[offset]);
	145	m_bg4_tmap->mark_tile_dirty(offset);
142	146	}
143	147
144		static WRITE16_HANDLER( galaxi_fg_w )
	148	WRITE16_MEMBER(galaxi_state::galaxi_fg_w)
145	149	{
146		galaxi_state *state = space->machine().driver_data<galaxi_state>();
147		COMBINE_DATA(&state->m_fg_ram[offset]);
148		state->m_fg_tmap->mark_tile_dirty(offset);
	150	COMBINE_DATA(&m_fg_ram[offset]);
	151	m_fg_tmap->mark_tile_dirty(offset);
149	152	}
150	153
151	154	static VIDEO_START(galaxi)
r14845	r14846
208	211	//  popmessage("%04x %04x %04x", state->m_out[0], state->m_out[1], state->m_out[2]);
209	212	}
210	213
211		static WRITE16_HANDLER( galaxi_500000_w )
	214	WRITE16_MEMBER(galaxi_state::galaxi_500000_w)
212	215	{
213		galaxi_state *state = space->machine().driver_data<galaxi_state>();
214		COMBINE_DATA(&state->m_out[0]);
215		show_out(space->machine());
	216	COMBINE_DATA(&m_out[0]);
	217	show_out(machine());
216	218	}
217	219
218		static WRITE16_HANDLER( galaxi_500002_w )
	220	WRITE16_MEMBER(galaxi_state::galaxi_500002_w)
219	221	{
220		galaxi_state *state = space->machine().driver_data<galaxi_state>();
221		COMBINE_DATA(&state->m_out[1]);
222		show_out(space->machine());
	222	COMBINE_DATA(&m_out[1]);
	223	show_out(machine());
223	224	}
224	225
225		static WRITE16_HANDLER( galaxi_500004_w )
	226	WRITE16_MEMBER(galaxi_state::galaxi_500004_w)
226	227	{
227		galaxi_state *state = space->machine().driver_data<galaxi_state>();
228	228
229	229	if (ACCESSING_BITS_0_7)
230	230	{
r14845	r14846
250	250	}
251	251	if (ACCESSING_BITS_8_15)
252	252	{
253		state->m_ticket = data & 0x0100;
254		state->m_hopper = data & 0x1000;
255		coin_counter_w(space->machine(), 0, data & 0x2000);   // coins
	253	m_ticket = data & 0x0100;
	254	m_hopper = data & 0x1000;
	255	coin_counter_w(machine(), 0, data & 0x2000);   // coins
256	256	}
257	257
258		COMBINE_DATA(&state->m_out[2]);
259		show_out(space->machine());
	258	COMBINE_DATA(&m_out[2]);
	259	show_out(machine());
260	260	}
261	261
262	262	static CUSTOM_INPUT( ticket_r )
r14845	r14846
275	275	static ADDRESS_MAP_START( galaxi_map, AS_PROGRAM, 16, galaxi_state )
276	276	AM_RANGE(0x000000, 0x03ffff) AM_ROM
277	277
278		AM_RANGE(0x100000, 0x1003ff) AM_RAM_WRITE_LEGACY(galaxi_bg1_w) AM_BASE(m_bg1_ram)
279		AM_RANGE(0x100400, 0x1007ff) AM_RAM_WRITE_LEGACY(galaxi_bg2_w) AM_BASE(m_bg2_ram)
280		AM_RANGE(0x100800, 0x100bff) AM_RAM_WRITE_LEGACY(galaxi_bg3_w) AM_BASE(m_bg3_ram)
281		AM_RANGE(0x100c00, 0x100fff) AM_RAM_WRITE_LEGACY(galaxi_bg4_w) AM_BASE(m_bg4_ram)
	278	AM_RANGE(0x100000, 0x1003ff) AM_RAM_WRITE(galaxi_bg1_w) AM_BASE(m_bg1_ram)
	279	AM_RANGE(0x100400, 0x1007ff) AM_RAM_WRITE(galaxi_bg2_w) AM_BASE(m_bg2_ram)
	280	AM_RANGE(0x100800, 0x100bff) AM_RAM_WRITE(galaxi_bg3_w) AM_BASE(m_bg3_ram)
	281	AM_RANGE(0x100c00, 0x100fff) AM_RAM_WRITE(galaxi_bg4_w) AM_BASE(m_bg4_ram)
282	282
283		AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE_LEGACY(galaxi_fg_w ) AM_BASE(m_fg_ram)
	283	AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(galaxi_fg_w ) AM_BASE(m_fg_ram)
284	284	AM_RANGE(0x102000, 0x1047ff) AM_READNOP   // unknown
285	285
286	286	AM_RANGE(0x300000, 0x3007ff) AM_RAM_WRITE_LEGACY(paletteram16_xRRRRRGGGGGBBBBB_word_w) AM_BASE_GENERIC(paletteram)
287	287
288	288	AM_RANGE(0x500000, 0x500001) AM_READ_PORT("INPUTS")
289		AM_RANGE(0x500000, 0x500001) AM_WRITE_LEGACY(galaxi_500000_w)
290		AM_RANGE(0x500002, 0x500003) AM_WRITE_LEGACY(galaxi_500002_w)
291		AM_RANGE(0x500004, 0x500005) AM_WRITE_LEGACY(galaxi_500004_w)
	289	AM_RANGE(0x500000, 0x500001) AM_WRITE(galaxi_500000_w)
	290	AM_RANGE(0x500002, 0x500003) AM_WRITE(galaxi_500002_w)
	291	AM_RANGE(0x500004, 0x500005) AM_WRITE(galaxi_500004_w)
292	292
293	293	AM_RANGE(0x700000, 0x700001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
294	294

src/mame/drivers/sothello.c

r14845	r14846
53	53	int m_soundcpu_busy;
54	54	int m_msm_data;
55	55	required_device<v9938_device> m_v9938;
	56	DECLARE_WRITE8_MEMBER(bank_w);
	57	DECLARE_READ8_MEMBER(subcpu_halt_set);
	58	DECLARE_READ8_MEMBER(subcpu_halt_clear);
	59	DECLARE_READ8_MEMBER(subcpu_comm_status);
	60	DECLARE_READ8_MEMBER(soundcpu_status_r);
	61	DECLARE_WRITE8_MEMBER(msm_data_w);
	62	DECLARE_WRITE8_MEMBER(soundcpu_busyflag_set_w);
	63	DECLARE_WRITE8_MEMBER(soundcpu_busyflag_reset_w);
	64	DECLARE_WRITE8_MEMBER(soundcpu_int_clear_w);
	65	DECLARE_WRITE8_MEMBER(subcpu_status_w);
	66	DECLARE_READ8_MEMBER(subcpu_status_r);
56	67	};
57	68
58	69
r14845	r14846
67	78
68	79	/* main Z80 */
69	80
70		static WRITE8_HANDLER(bank_w)
	81	WRITE8_MEMBER(sothello_state::bank_w)
71	82	{
72		UINT8 *RAM = space->machine().region("maincpu")->base();
	83	UINT8 *RAM = machine().region("maincpu")->base();
73	84	int bank=0;
74	85	switch(data^0xff)
75	86	{
r14845	r14846
78	89	case 4: bank=2; break;
79	90	case 8: bank=3; break;
80	91	}
81		memory_set_bankptr(space->machine(),"bank1",&RAM[bank*0x4000+0x10000]);
	92	memory_set_bankptr(machine(),"bank1",&RAM[bank*0x4000+0x10000]);
82	93	}
83	94
84	95	static TIMER_CALLBACK( subcpu_suspend )
r14845	r14846
92	103	cputag_set_input_line(machine, "sub", INPUT_LINE_NMI, PULSE_LINE);
93	104	}
94	105
95		static READ8_HANDLER( subcpu_halt_set )
	106	READ8_MEMBER(sothello_state::subcpu_halt_set)
96	107	{
97		sothello_state *state = space->machine().driver_data<sothello_state>();
98		space->machine().scheduler().synchronize(FUNC(subcpu_suspend));
99		state->m_subcpu_status|=2;
	108	machine().scheduler().synchronize(FUNC(subcpu_suspend));
	109	m_subcpu_status|=2;
100	110	return 0;
101	111	}
102	112
103		static READ8_HANDLER( subcpu_halt_clear )
	113	READ8_MEMBER(sothello_state::subcpu_halt_clear)
104	114	{
105		sothello_state *state = space->machine().driver_data<sothello_state>();
106		space->machine().scheduler().synchronize(FUNC(subcpu_resume));
107		state->m_subcpu_status&=~1;
108		state->m_subcpu_status&=~2;
	115	machine().scheduler().synchronize(FUNC(subcpu_resume));
	116	m_subcpu_status&=~1;
	117	m_subcpu_status&=~2;
109	118	return 0;
110	119	}
111	120
112		static READ8_HANDLER(subcpu_comm_status )
	121	READ8_MEMBER(sothello_state::subcpu_comm_status)
113	122	{
114		sothello_state *state = space->machine().driver_data<sothello_state>();
115		return state->m_subcpu_status;
	123	return m_subcpu_status;
116	124	}
117	125
118		static READ8_HANDLER( soundcpu_status_r )
	126	READ8_MEMBER(sothello_state::soundcpu_status_r)
119	127	{
120		sothello_state *state = space->machine().driver_data<sothello_state>();
121		return state->m_soundcpu_busy;
	128	return m_soundcpu_busy;
122	129	}
123	130
124	131	static ADDRESS_MAP_START( maincpu_mem_map, AS_PROGRAM, 8, sothello_state )
r14845	r14846
133	140	AM_RANGE( 0x00, 0x0f) AM_READ_PORT("INPUT1")
134	141	AM_RANGE( 0x10, 0x1f) AM_READ_PORT("INPUT2")
135	142	AM_RANGE( 0x20, 0x2f) AM_READ_PORT("SYSTEM")
136		AM_RANGE( 0x30, 0x30) AM_READ_LEGACY(subcpu_halt_set)
137		AM_RANGE( 0x31, 0x31) AM_READ_LEGACY(subcpu_halt_clear)
138		AM_RANGE( 0x32, 0x32) AM_READ_LEGACY(subcpu_comm_status)
139		AM_RANGE( 0x33, 0x33) AM_READ_LEGACY(soundcpu_status_r)
	143	AM_RANGE( 0x30, 0x30) AM_READ(subcpu_halt_set)
	144	AM_RANGE( 0x31, 0x31) AM_READ(subcpu_halt_clear)
	145	AM_RANGE( 0x32, 0x32) AM_READ(subcpu_comm_status)
	146	AM_RANGE( 0x33, 0x33) AM_READ(soundcpu_status_r)
140	147	AM_RANGE( 0x40, 0x4f) AM_WRITE_LEGACY(soundlatch_w)
141		AM_RANGE( 0x50, 0x50) AM_WRITE_LEGACY(bank_w)
	148	AM_RANGE( 0x50, 0x50) AM_WRITE(bank_w)
142	149	AM_RANGE( 0x60, 0x61) AM_MIRROR(0x02) AM_DEVREADWRITE_LEGACY("ymsnd", ym2203_r, ym2203_w)
143	150	/* not sure, but the A1 line is ignored, code @ $8b8 */
144	151	AM_RANGE( 0x70, 0x73) AM_DEVREADWRITE( "v9938", v9938_device, read, write )
r14845	r14846
158	165	msm5205_reset_w(device,data&1);
159	166	}
160	167
161		static WRITE8_HANDLER( msm_data_w )
	168	WRITE8_MEMBER(sothello_state::msm_data_w)
162	169	{
163		sothello_state *state = space->machine().driver_data<sothello_state>();
164		state->m_msm_data = data;
	170	m_msm_data = data;
165	171
166	172	}
167	173
168		static WRITE8_HANDLER(soundcpu_busyflag_set_w)
	174	WRITE8_MEMBER(sothello_state::soundcpu_busyflag_set_w)
169	175	{
170		sothello_state *state = space->machine().driver_data<sothello_state>();
171		state->m_soundcpu_busy=1;
	176	m_soundcpu_busy=1;
172	177	}
173	178
174		static WRITE8_HANDLER(soundcpu_busyflag_reset_w)
	179	WRITE8_MEMBER(sothello_state::soundcpu_busyflag_reset_w)
175	180	{
176		sothello_state *state = space->machine().driver_data<sothello_state>();
177		state->m_soundcpu_busy=0;
	181	m_soundcpu_busy=0;
178	182	}
179	183
180		static WRITE8_HANDLER(soundcpu_int_clear_w)
	184	WRITE8_MEMBER(sothello_state::soundcpu_int_clear_w)
181	185	{
182		cputag_set_input_line(space->machine(), "soundcpu", 0, CLEAR_LINE );
	186	cputag_set_input_line(machine(), "soundcpu", 0, CLEAR_LINE );
183	187	}
184	188
185	189	static ADDRESS_MAP_START( soundcpu_mem_map, AS_PROGRAM, 8, sothello_state )
r14845	r14846
190	194	static ADDRESS_MAP_START( soundcpu_io_map, AS_IO, 8, sothello_state )
191	195	ADDRESS_MAP_GLOBAL_MASK(0xff)
192	196	AM_RANGE(0x00, 0x00) AM_READ_LEGACY(soundlatch_r)
193		AM_RANGE(0x01, 0x01) AM_WRITE_LEGACY(msm_data_w)
	197	AM_RANGE(0x01, 0x01) AM_WRITE(msm_data_w)
194	198	AM_RANGE(0x02, 0x02) AM_DEVWRITE_LEGACY("msm", msm_cfg_w)
195		AM_RANGE(0x03, 0x03) AM_WRITE_LEGACY(soundcpu_busyflag_set_w)
196		AM_RANGE(0x04, 0x04) AM_WRITE_LEGACY(soundcpu_busyflag_reset_w)
197		AM_RANGE(0x05, 0x05) AM_WRITE_LEGACY(soundcpu_int_clear_w)
	199	AM_RANGE(0x03, 0x03) AM_WRITE(soundcpu_busyflag_set_w)
	200	AM_RANGE(0x04, 0x04) AM_WRITE(soundcpu_busyflag_reset_w)
	201	AM_RANGE(0x05, 0x05) AM_WRITE(soundcpu_int_clear_w)
198	202	ADDRESS_MAP_END
199	203
200	204	/* sub 6809 */
r14845	r14846
212	216	}
213	217	}
214	218
215		static WRITE8_HANDLER(subcpu_status_w)
	219	WRITE8_MEMBER(sothello_state::subcpu_status_w)
216	220	{
217		unlock_shared_ram(space);
	221	unlock_shared_ram(&space);
218	222	}
219	223
220		static READ8_HANDLER(subcpu_status_r)
	224	READ8_MEMBER(sothello_state::subcpu_status_r)
221	225	{
222		unlock_shared_ram(space);
	226	unlock_shared_ram(&space);
223	227	return 0;
224	228	}
225	229
226	230	static ADDRESS_MAP_START( subcpu_mem_map, AS_PROGRAM, 8, sothello_state )
227		AM_RANGE(0x0000, 0x1fff) AM_READWRITE_LEGACY(subcpu_status_r,subcpu_status_w)
	231	AM_RANGE(0x0000, 0x1fff) AM_READWRITE(subcpu_status_r,subcpu_status_w)
228	232	AM_RANGE(0x2000, 0x77ff) AM_RAM
229	233	AM_RANGE(0x7800, 0x7fff) AM_RAM AM_SHARE("share1")  /* upper 0x800 of 6264 is shared  with main cpu */
230	234	AM_RANGE(0x8000, 0xffff) AM_ROM

src/mame/drivers/taitotz.c

r14845	r14846
99	99	UINT32 video_ram_ptr;
100	100
101	101	bitmap_rgb32 framebuffer;
	102	DECLARE_WRITE64_MEMBER(video_chip_w);
	103	DECLARE_READ64_MEMBER(ppc_common_r);
	104	DECLARE_WRITE64_MEMBER(ppc_common_w);
102	105	};
103	106
104	107
r14845	r14846
234	237	// 0xB1000000, size 0x800000  : texture RAM
235	238
236	239
237		static WRITE64_HANDLER(video_chip_w)
	240	WRITE64_MEMBER(taitotz_state::video_chip_w)
238	241	{
239		taitotz_state *state = space->machine().driver_data<taitotz_state>();
240	242
241		//printf("unk_w: %08X, %08X%08X, %08X%08X at %08X\n", offset, (UINT32)(data >> 32), (UINT32)(data), (UINT32)(mem_mask >> 32), (UINT32)(mem_mask), cpu_get_pc(space->cpu));
	243	//printf("unk_w: %08X, %08X%08X, %08X%08X at %08X\n", offset, (UINT32)(data >> 32), (UINT32)(data), (UINT32)(mem_mask >> 32), (UINT32)(mem_mask), cpu_get_pc(cpu));
242	244
243	245	UINT32 reg = offset * 8;
244	246	UINT32 regdata;
r14845	r14846
257	259	{
258	260	case 0:
259	261	{
260		video_reg_w(space->machine(), state->video_reg, regdata);
	262	video_reg_w(machine(), video_reg, regdata);
261	263	break;
262	264	}
263	265	case 0x8:
264	266	{
265		state->video_reg = regdata;
	267	video_reg = regdata;
266	268
267		if ((state->video_reg & 0xf0000000) == 0xb0000000)
	269	if ((video_reg & 0xf0000000) == 0xb0000000)
268	270	{
269		state->video_ram_ptr = 0;
	271	video_ram_ptr = 0;
270	272
271		switch (state->video_reg & 0x0fffffff)
	273	switch (video_reg & 0x0fffffff)
272	274	{
273		case 0x0980000: state->video_ram = state->video_char_ram; break;
274		case 0x09c0000: state->video_ram = state->video_tile_ram; break;
275		case 0x1800000: state->video_ram = state->video_screen_ram; break;
	275	case 0x0980000: video_ram = video_char_ram; break;
	276	case 0x09c0000: video_ram = video_tile_ram; break;
	277	case 0x1800000: video_ram = video_screen_ram; break;
276	278	default:
277	279	{
278		fatalerror("video_chip_ram sel %08X\n", state->video_reg & 0x0fffffff);
	280	fatalerror("video_chip_ram sel %08X\n", video_reg & 0x0fffffff);
279	281	break;
280	282	}
281	283	}
r14845	r14846
290	292	}
291	293	}
292	294
293		static READ64_HANDLER(ppc_common_r)
	295	READ64_MEMBER(taitotz_state::ppc_common_r)
294	296	{
295	297	if (offset == 0x7ff)
296	298	{
r14845	r14846
303	305	return 0;
304	306	}
305	307
306		static WRITE64_HANDLER(ppc_common_w)
	308	WRITE64_MEMBER(taitotz_state::ppc_common_w)
307	309	{
308	310	if (offset == 0x7ff)
309	311	{
310		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
	312	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
311	313	}
312	314	}
313	315
r14845	r14846
328	330	static ADDRESS_MAP_START( ppc603e_mem, AS_PROGRAM, 64, taitotz_state )
329	331	//AM_RANGE(0x00000000, 0x00000007) AM_RAM   // Register/RAM access port? - Written 128k+256k times on boot
330	332	//AM_RANGE(0x00000008, 0x0000000f) AM_RAM   // Register/RAM address port?
331		AM_RANGE(0x00000000, 0x0000000f) AM_WRITE_LEGACY(video_chip_w)
	333	AM_RANGE(0x00000000, 0x0000000f) AM_WRITE(video_chip_w)
332	334	AM_RANGE(0x40000000, 0x400fffff) AM_RAM   // Work RAM
333		AM_RANGE(0xa8000000, 0xa8003fff) AM_READWRITE_LEGACY(ppc_common_r, ppc_common_w)   // Common RAM (with TLCS-900)
	335	AM_RANGE(0xa8000000, 0xa8003fff) AM_READWRITE(ppc_common_r, ppc_common_w)   // Common RAM (with TLCS-900)
334	336	//AM_RANGE(0xa8003ff8, 0xa8003fff) AM_RAM   // TLCS-900 related?
335	337	AM_RANGE(0xac000000, 0xac0fffff) AM_ROM AM_REGION("user1", 0)
336	338	AM_RANGE(0xfff00000, 0xffffffff) AM_ROM AM_REGION("user1", 0)

src/mame/drivers/cabaret.c

r14845	r14846
40	40	tilemap_t *m_fg_tilemap;
41	41	int m_nmi_enable;
42	42	UINT8 m_out[3];
	43	DECLARE_WRITE8_MEMBER(bg_scroll_w);
	44	DECLARE_WRITE8_MEMBER(bg_tile_w);
	45	DECLARE_WRITE8_MEMBER(fg_tile_w);
	46	DECLARE_WRITE8_MEMBER(fg_color_w);
	47	DECLARE_WRITE8_MEMBER(cabaret_nmi_and_coins_w);
	48	void show_out();
43	49	};
44	50
45	51
r14845	r14846
51	57
52	58
53	59
54		static WRITE8_HANDLER( bg_scroll_w )
	60	WRITE8_MEMBER(cabaret_state::bg_scroll_w)
55	61	{
56		cabaret_state *state = space->machine().driver_data<cabaret_state>();
57		state->m_bg_scroll[offset] = data;
58		state->m_bg_tilemap->set_scrolly(offset,data);
	62	m_bg_scroll[offset] = data;
	63	m_bg_tilemap->set_scrolly(offset,data);
59	64	}
60	65
61		static WRITE8_HANDLER( bg_tile_w )
	66	WRITE8_MEMBER(cabaret_state::bg_tile_w)
62	67	{
63		cabaret_state *state = space->machine().driver_data<cabaret_state>();
64		state->m_bg_tile_ram[offset] = data;
65		state->m_bg_tilemap->mark_tile_dirty(offset);
	68	m_bg_tile_ram[offset] = data;
	69	m_bg_tilemap->mark_tile_dirty(offset);
66	70	}
67	71
68	72	static TILE_GET_INFO( get_bg_tile_info )
r14845	r14846
80	84	SET_TILE_INFO(0, code, tile != 0x1fff ? ((code >> 12) & 0xe) + 1 : 0, 0);
81	85	}
82	86
83		static WRITE8_HANDLER( fg_tile_w )
	87	WRITE8_MEMBER(cabaret_state::fg_tile_w)
84	88	{
85		cabaret_state *state = space->machine().driver_data<cabaret_state>();
86		state->m_fg_tile_ram[offset] = data;
87		state->m_fg_tilemap->mark_tile_dirty(offset);
	89	m_fg_tile_ram[offset] = data;
	90	m_fg_tilemap->mark_tile_dirty(offset);
88	91	}
89	92
90		static WRITE8_HANDLER( fg_color_w )
	93	WRITE8_MEMBER(cabaret_state::fg_color_w)
91	94	{
92		cabaret_state *state = space->machine().driver_data<cabaret_state>();
93		state->m_fg_color_ram[offset] = data;
94		state->m_fg_tilemap->mark_tile_dirty(offset);
	95	m_fg_color_ram[offset] = data;
	96	m_fg_tilemap->mark_tile_dirty(offset);
95	97	}
96	98
97	99	static VIDEO_START(cabaret)
r14845	r14846
122	124
123	125
124	126
125		static void show_out(cabaret_state *state)
	127	void cabaret_state::show_out()
126	128	{
127	129	#ifdef MAME_DEBUG
128		popmessage("%02x %02x %02x", state->m_out[0], state->m_out[1], state->m_out[2]);
	130	popmessage("%02x %02x %02x",m_out[0], m_out[1], m_out[2]);
129	131	#endif
130	132	}
131	133
132		static WRITE8_HANDLER( cabaret_nmi_and_coins_w )
	134	WRITE8_MEMBER(cabaret_state::cabaret_nmi_and_coins_w)
133	135	{
134		cabaret_state *state = space->machine().driver_data<cabaret_state>();
135		if ((state->m_nmi_enable ^ data) & (~0xdd))
	136	if ((m_nmi_enable ^ data) & (~0xdd))
136	137	{
137		logerror("PC %06X: nmi_and_coins = %02x\n",cpu_get_pc(&space->device()),data);
	138	logerror("PC %06X: nmi_and_coins = %02x\n",cpu_get_pc(&space.device()),data);
138	139	//      popmessage("%02x",data);
139	140	}
140	141
141		coin_counter_w(space->machine(), 0,      data & 0x01);   // coin_a
142		coin_counter_w(space->machine(), 1,      data & 0x04);   // coin_c
143		coin_counter_w(space->machine(), 2,      data & 0x08);   // key in
144		coin_counter_w(space->machine(), 3,      data & 0x10);   // coin state->m_out mech
	142	coin_counter_w(machine(), 0,      data & 0x01);   // coin_a
	143	coin_counter_w(machine(), 1,      data & 0x04);   // coin_c
	144	coin_counter_w(machine(), 2,      data & 0x08);   // key in
	145	coin_counter_w(machine(), 3,      data & 0x10);   // coin m_out mech
145	146
146		set_led_status(space->machine(), 6,      data & 0x40);   // led for coin state->m_out / hopper active
	147	set_led_status(machine(), 6,      data & 0x40);   // led for coin m_out / hopper active
147	148
148		state->m_nmi_enable = data;   //  data & 0x80     // nmi enable?
	149	m_nmi_enable = data;   //  data & 0x80     // nmi enable?
149	150
150		state->m_out[0] = data;
151		show_out(state);
	151	m_out[0] = data;
	152	show_out();
152	153	}
153	154
154	155
r14845	r14846
165	166	AM_RANGE( 0x0081, 0x0081 ) AM_READ_PORT( "SERVICE" )
166	167	AM_RANGE( 0x0082, 0x0082 ) AM_READ_PORT( "COINS" )
167	168	AM_RANGE( 0x0090, 0x0090 ) AM_READ_PORT( "BUTTONS1" )
168		AM_RANGE( 0x00a0, 0x00a0 ) AM_WRITE_LEGACY(cabaret_nmi_and_coins_w )
	169	AM_RANGE( 0x00a0, 0x00a0 ) AM_WRITE(cabaret_nmi_and_coins_w )
169	170
170	171	AM_RANGE( 0x00a1, 0x00a1 ) AM_READ_PORT("DSW1")         /* DSW1 */
171	172	AM_RANGE( 0x00a2, 0x00a2 ) AM_READ_PORT("DSW2")         /* DSW2 */
r14845	r14846
173	174
174	175	AM_RANGE( 0x00e0, 0x00e1 ) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w )
175	176
176		AM_RANGE( 0x2000, 0x27ff ) AM_RAM_WRITE_LEGACY(fg_tile_w )  AM_BASE(m_fg_tile_ram )
177		AM_RANGE( 0x2800, 0x2fff ) AM_RAM_WRITE_LEGACY(fg_color_w ) AM_BASE(m_fg_color_ram )
	177	AM_RANGE( 0x2000, 0x27ff ) AM_RAM_WRITE(fg_tile_w )  AM_BASE(m_fg_tile_ram )
	178	AM_RANGE( 0x2800, 0x2fff ) AM_RAM_WRITE(fg_color_w ) AM_BASE(m_fg_color_ram )
178	179
179	180	AM_RANGE( 0x3000, 0x37ff ) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split1_w ) AM_BASE_GENERIC( paletteram )
180	181	AM_RANGE( 0x3800, 0x3fff ) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split2_w ) AM_BASE_GENERIC( paletteram2 )
181	182
182		AM_RANGE( 0x1000, 0x103f ) AM_RAM_WRITE_LEGACY(bg_scroll_w ) AM_BASE(m_bg_scroll )
	183	AM_RANGE( 0x1000, 0x103f ) AM_RAM_WRITE(bg_scroll_w ) AM_BASE(m_bg_scroll )
183	184
184		AM_RANGE( 0x1800, 0x19ff ) AM_RAM_WRITE_LEGACY(bg_tile_w )  AM_BASE(m_bg_tile_ram )
	185	AM_RANGE( 0x1800, 0x19ff ) AM_RAM_WRITE(bg_tile_w )  AM_BASE(m_bg_tile_ram )
185	186	AM_RANGE( 0x8000, 0xffff ) AM_ROM AM_REGION("gfx3", 0)
186	187	ADDRESS_MAP_END
187	188

src/mame/drivers/olibochu.c

r14845	r14846
75	75
76	76	/* misc */
77	77	int m_cmd;
	78	DECLARE_WRITE8_MEMBER(olibochu_videoram_w);
	79	DECLARE_WRITE8_MEMBER(olibochu_colorram_w);
	80	DECLARE_WRITE8_MEMBER(olibochu_flipscreen_w);
	81	DECLARE_WRITE8_MEMBER(sound_command_w);
78	82	};
79	83
80	84
r14845	r14846
116	120	}
117	121	}
118	122
119		static WRITE8_HANDLER( olibochu_videoram_w )
	123	WRITE8_MEMBER(olibochu_state::olibochu_videoram_w)
120	124	{
121		olibochu_state *state = space->machine().driver_data<olibochu_state>();
122		state->m_videoram[offset] = data;
123		state->m_bg_tilemap->mark_tile_dirty(offset);
	125	m_videoram[offset] = data;
	126	m_bg_tilemap->mark_tile_dirty(offset);
124	127	}
125	128
126		static WRITE8_HANDLER( olibochu_colorram_w )
	129	WRITE8_MEMBER(olibochu_state::olibochu_colorram_w)
127	130	{
128		olibochu_state *state = space->machine().driver_data<olibochu_state>();
129		state->m_colorram[offset] = data;
130		state->m_bg_tilemap->mark_tile_dirty(offset);
	131	m_colorram[offset] = data;
	132	m_bg_tilemap->mark_tile_dirty(offset);
131	133	}
132	134
133		static WRITE8_HANDLER( olibochu_flipscreen_w )
	135	WRITE8_MEMBER(olibochu_state::olibochu_flipscreen_w)
134	136	{
135		if (flip_screen_get(space->machine()) != (data & 0x80))
	137	if (flip_screen_get(machine()) != (data & 0x80))
136	138	{
137		flip_screen_set(space->machine(), data & 0x80);
138		space->machine().tilemap().mark_all_dirty();
	139	flip_screen_set(machine(), data & 0x80);
	140	machine().tilemap().mark_all_dirty();
139	141	}
140	142
141	143	/* other bits are used, but unknown */
r14845	r14846
227	229	}
228	230
229	231
230		static WRITE8_HANDLER( sound_command_w )
	232	WRITE8_MEMBER(olibochu_state::sound_command_w)
231	233	{
232		olibochu_state *state = space->machine().driver_data<olibochu_state>();
233	234	int c;
234	235
235	236	if (offset == 0)
236		state->m_cmd = (state->m_cmd & 0x00ff) | (data << 8);
	237	m_cmd = (m_cmd & 0x00ff) | (data << 8);
237	238	else
238		state->m_cmd = (state->m_cmd & 0xff00) | data;
	239	m_cmd = (m_cmd & 0xff00) | data;
239	240
240	241	for (c = 15; c >= 0; c--)
241		if (state->m_cmd & (1 << c)) break;
	242	if (m_cmd & (1 << c)) break;
242	243
243	244	if (c >= 0) soundlatch_w(space, 0, 15 - c);
244	245	}
r14845	r14846
246	247
247	248	static ADDRESS_MAP_START( olibochu_map, AS_PROGRAM, 8, olibochu_state )
248	249	AM_RANGE(0x0000, 0x7fff) AM_ROM
249		AM_RANGE(0x8000, 0x83ff) AM_RAM_WRITE_LEGACY(olibochu_videoram_w) AM_BASE(m_videoram)
250		AM_RANGE(0x8400, 0x87ff) AM_RAM_WRITE_LEGACY(olibochu_colorram_w) AM_BASE(m_colorram)
	250	AM_RANGE(0x8000, 0x83ff) AM_RAM_WRITE(olibochu_videoram_w) AM_BASE(m_videoram)
	251	AM_RANGE(0x8400, 0x87ff) AM_RAM_WRITE(olibochu_colorram_w) AM_BASE(m_colorram)
251	252	AM_RANGE(0x9000, 0x903f) AM_RAM //???
252	253	AM_RANGE(0x9800, 0x983f) AM_RAM //???
253	254	AM_RANGE(0xa000, 0xa000) AM_READ_PORT("IN0")
r14845	r14846
256	257	AM_RANGE(0xa003, 0xa003) AM_READ_PORT("DSW0")
257	258	AM_RANGE(0xa004, 0xa004) AM_READ_PORT("DSW1")
258	259	AM_RANGE(0xa005, 0xa005) AM_READ_PORT("DSW2")
259		AM_RANGE(0xa800, 0xa801) AM_WRITE_LEGACY(sound_command_w)
260		AM_RANGE(0xa802, 0xa802) AM_WRITE_LEGACY(olibochu_flipscreen_w)   /* bit 6 = enable sound? */
	260	AM_RANGE(0xa800, 0xa801) AM_WRITE(sound_command_w)
	261	AM_RANGE(0xa802, 0xa802) AM_WRITE(olibochu_flipscreen_w)   /* bit 6 = enable sound? */
261	262	AM_RANGE(0xf400, 0xf41f) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
262	263	AM_RANGE(0xf440, 0xf47f) AM_RAM AM_BASE_SIZE(m_spriteram2, m_spriteram2_size)
263	264	AM_RANGE(0xf000, 0xffff) AM_RAM

src/mame/drivers/tugboat.c

r14845	r14846
40	40	int m_reg0;
41	41	int m_reg1;
42	42	int m_ctrl;
	43	DECLARE_WRITE8_MEMBER(tugboat_hd46505_0_w);
	44	DECLARE_WRITE8_MEMBER(tugboat_hd46505_1_w);
	45	DECLARE_WRITE8_MEMBER(tugboat_score_w);
43	46	};
44	47
45	48
r14845	r14846
69	72
70	73	/* see mc6845.c. That file is only a placeholder, I process the writes here
71	74	because I need the start_addr register to handle scrolling */
72		static WRITE8_HANDLER( tugboat_hd46505_0_w )
	75	WRITE8_MEMBER(tugboat_state::tugboat_hd46505_0_w)
73	76	{
74		tugboat_state *state = space->machine().driver_data<tugboat_state>();
75		if (offset == 0) state->m_reg0 = data & 0x0f;
76		else if (state->m_reg0 < 18) state->m_hd46505_0_reg[state->m_reg0] = data;
	77	if (offset == 0) m_reg0 = data & 0x0f;
	78	else if (m_reg0 < 18) m_hd46505_0_reg[m_reg0] = data;
77	79	}
78		static WRITE8_HANDLER( tugboat_hd46505_1_w )
	80	WRITE8_MEMBER(tugboat_state::tugboat_hd46505_1_w)
79	81	{
80		tugboat_state *state = space->machine().driver_data<tugboat_state>();
81		if (offset == 0) state->m_reg1 = data & 0x0f;
82		else if (state->m_reg1 < 18) state->m_hd46505_1_reg[state->m_reg1] = data;
	82	if (offset == 0) m_reg1 = data & 0x0f;
	83	else if (m_reg1 < 18) m_hd46505_1_reg[m_reg1] = data;
83	84	}
84	85
85	86
86		static WRITE8_HANDLER( tugboat_score_w )
	87	WRITE8_MEMBER(tugboat_state::tugboat_score_w)
87	88	{
88		tugboat_state *state = space->machine().driver_data<tugboat_state>();
89		if (offset>=0x8) state->m_ram[0x291d + 32*offset + 32*(1-8)] = data ^ 0x0f;
90		if (offset<0x8 ) state->m_ram[0x291d + 32*offset + 32*9] = data ^ 0x0f;
	89	if (offset>=0x8) m_ram[0x291d + 32*offset + 32*(1-8)] = data ^ 0x0f;
	90	if (offset<0x8 ) m_ram[0x291d + 32*offset + 32*9] = data ^ 0x0f;
91	91	}
92	92
93	93	static void draw_tilemap(running_machine &machine, bitmap_ind16 &bitmap,const rectangle &cliprect,
r14845	r14846
213	213	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, tugboat_state )
214	214	AM_RANGE(0x0000, 0x01ff) AM_RAM AM_BASE(m_ram)
215	215	AM_RANGE(0x1060, 0x1061) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
216		AM_RANGE(0x10a0, 0x10a1) AM_WRITE_LEGACY(tugboat_hd46505_0_w)   /* scrolling is performed changing the start_addr register (0C/0D) */
217		AM_RANGE(0x10c0, 0x10c1) AM_WRITE_LEGACY(tugboat_hd46505_1_w)
	216	AM_RANGE(0x10a0, 0x10a1) AM_WRITE(tugboat_hd46505_0_w)   /* scrolling is performed changing the start_addr register (0C/0D) */
	217	AM_RANGE(0x10c0, 0x10c1) AM_WRITE(tugboat_hd46505_1_w)
218	218	AM_RANGE(0x11e4, 0x11e7) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
219	219	AM_RANGE(0x11e8, 0x11eb) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
220	220	//AM_RANGE(0x1700, 0x1fff) AM_RAM
221		AM_RANGE(0x18e0, 0x18ef) AM_WRITE_LEGACY(tugboat_score_w)
	221	AM_RANGE(0x18e0, 0x18ef) AM_WRITE(tugboat_score_w)
222	222	AM_RANGE(0x2000, 0x2fff) AM_RAM   /* tilemap RAM */
223	223	AM_RANGE(0x4000, 0x7fff) AM_ROM
224	224	AM_RANGE(0xfff0, 0xffff) AM_ROM   /* vectors */

src/mame/drivers/kingdrby.c

r14845	r14846
90	90	UINT8 m_p2_hopper;
91	91	UINT8 m_mux_data;
92	92	UINT8 *m_spriteram;
	93	DECLARE_WRITE8_MEMBER(sc0_vram_w);
	94	DECLARE_WRITE8_MEMBER(sc0_attr_w);
	95	DECLARE_WRITE8_MEMBER(led_array_w);
	96	DECLARE_WRITE8_MEMBER(kingdrbb_lamps_w);
93	97	};
94	98
95	99
r14845	r14846
233	237	return 0;
234	238	}
235	239
236		static WRITE8_HANDLER( sc0_vram_w )
	240	WRITE8_MEMBER(kingdrby_state::sc0_vram_w)
237	241	{
238		kingdrby_state *state = space->machine().driver_data<kingdrby_state>();
239		state->m_vram[offset] = data;
240		state->m_sc0_tilemap->mark_tile_dirty(offset);
241		state->m_sc0w_tilemap->mark_tile_dirty(offset);
242		state->m_sc1_tilemap->mark_tile_dirty(offset);
	242	m_vram[offset] = data;
	243	m_sc0_tilemap->mark_tile_dirty(offset);
	244	m_sc0w_tilemap->mark_tile_dirty(offset);
	245	m_sc1_tilemap->mark_tile_dirty(offset);
243	246	}
244	247
245		static WRITE8_HANDLER( sc0_attr_w )
	248	WRITE8_MEMBER(kingdrby_state::sc0_attr_w)
246	249	{
247		kingdrby_state *state = space->machine().driver_data<kingdrby_state>();
248		state->m_attr[offset] = data;
249		state->m_sc0_tilemap->mark_tile_dirty(offset);
250		state->m_sc0w_tilemap->mark_tile_dirty(offset);
251		state->m_sc1_tilemap->mark_tile_dirty(offset);
	250	m_attr[offset] = data;
	251	m_sc0_tilemap->mark_tile_dirty(offset);
	252	m_sc0w_tilemap->mark_tile_dirty(offset);
	253	m_sc1_tilemap->mark_tile_dirty(offset);
252	254	}
253	255
254	256	/*************************************
r14845	r14846
361	363	static const UINT8 led_map[16] =
362	364	{ 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7c,0x07,0x7f,0x67,0x77,0x7c,0x39,0x5e,0x79,0x00 };
363	365
364		static WRITE8_HANDLER( led_array_w )
	366	WRITE8_MEMBER(kingdrby_state::led_array_w)
365	367	{
366	368	/*
367	369	offset = directly tied with the button (i.e. offset 1 = 1-2, offset 2 = 1-3 etc.)
r14845	r14846
384	386	static ADDRESS_MAP_START( master_map, AS_PROGRAM, 8, kingdrby_state )
385	387	AM_RANGE(0x0000, 0x2fff) AM_ROM
386	388	AM_RANGE(0x3000, 0x33ff) AM_RAM AM_MIRROR(0xc00) AM_SHARE("share1")
387		AM_RANGE(0x4000, 0x43ff) AM_RAM_WRITE_LEGACY(sc0_vram_w) AM_BASE(m_vram)
388		AM_RANGE(0x5000, 0x53ff) AM_RAM_WRITE_LEGACY(sc0_attr_w) AM_BASE(m_attr)
	389	AM_RANGE(0x4000, 0x43ff) AM_RAM_WRITE(sc0_vram_w) AM_BASE(m_vram)
	390	AM_RANGE(0x5000, 0x53ff) AM_RAM_WRITE(sc0_attr_w) AM_BASE(m_attr)
389	391	ADDRESS_MAP_END
390	392
391	393	static ADDRESS_MAP_START( master_io_map, AS_IO, 8, kingdrby_state )
r14845	r14846
403	405	AM_RANGE(0x7400, 0x74ff) AM_RAM AM_BASE(m_spriteram)
404	406	AM_RANGE(0x7600, 0x7600) AM_DEVWRITE("crtc", mc6845_device, address_w)
405	407	AM_RANGE(0x7601, 0x7601) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
406		AM_RANGE(0x7801, 0x780f) AM_WRITE_LEGACY(led_array_w)
	408	AM_RANGE(0x7801, 0x780f) AM_WRITE(led_array_w)
407	409	AM_RANGE(0x7a00, 0x7a00) AM_RAM //buffer for the key matrix
408	410	AM_RANGE(0x7c00, 0x7c00) AM_READ_PORT("DSW")
409	411	ADDRESS_MAP_END
410	412
411		static WRITE8_HANDLER( kingdrbb_lamps_w )
	413	WRITE8_MEMBER(kingdrby_state::kingdrbb_lamps_w)
412	414	{
413	415	// (same as the inputs but active high)
414	416	}
r14845	r14846
427	429	AM_RANGE(0x7801, 0x7801) AM_READ_PORT("KEY1")
428	430	AM_RANGE(0x7802, 0x7802) AM_READ_PORT("KEY2")
429	431	AM_RANGE(0x7803, 0x7803) AM_READ_PORT("KEY3")
430		AM_RANGE(0x7800, 0x7803) AM_WRITE_LEGACY(kingdrbb_lamps_w)
	432	AM_RANGE(0x7800, 0x7803) AM_WRITE(kingdrbb_lamps_w)
431	433	AM_RANGE(0x7a00, 0x7a00) AM_READ_PORT("SYSTEM")
432	434	AM_RANGE(0x7c00, 0x7c00) AM_READ_PORT("DSW")
433	435	ADDRESS_MAP_END

src/mame/drivers/r2dx_v33.c

r14845	r14846
32	32	: driver_device(mconfig, type, tag) { }
33	33
34	34	UINT16 *m_spriteram;
	35	DECLARE_WRITE16_MEMBER(rdx_bg_vram_w);
	36	DECLARE_WRITE16_MEMBER(rdx_md_vram_w);
	37	DECLARE_WRITE16_MEMBER(rdx_fg_vram_w);
	38	DECLARE_WRITE16_MEMBER(rdx_tx_vram_w);
	39	DECLARE_READ16_MEMBER(rdx_v33_unknown_r);
	40	DECLARE_WRITE16_MEMBER(mcu_xval_w);
	41	DECLARE_WRITE16_MEMBER(mcu_yval_w);
	42	DECLARE_WRITE16_MEMBER(mcu_table_w);
	43	DECLARE_WRITE16_MEMBER(mcu_table2_w);
	44	DECLARE_READ16_MEMBER(nzerotea_sound_comms_r);
	45	DECLARE_WRITE16_MEMBER(nzerotea_sound_comms_w);
35	46	};
36	47
37	48
r14845	r14846
285	296	mcu_prog_offs = data;
286	297	}
287	298
288		static WRITE16_HANDLER( rdx_bg_vram_w )
	299	WRITE16_MEMBER(r2dx_v33_state::rdx_bg_vram_w)
289	300	{
290	301	COMBINE_DATA(&bg_vram[offset]);
291	302	bg_tilemap->mark_tile_dirty(offset);
292	303	}
293	304
294		static WRITE16_HANDLER( rdx_md_vram_w )
	305	WRITE16_MEMBER(r2dx_v33_state::rdx_md_vram_w)
295	306	{
296	307	COMBINE_DATA(&md_vram[offset]);
297	308	md_tilemap->mark_tile_dirty(offset);
298	309	}
299	310
300		static WRITE16_HANDLER( rdx_fg_vram_w )
	311	WRITE16_MEMBER(r2dx_v33_state::rdx_fg_vram_w)
301	312	{
302	313	COMBINE_DATA(&fg_vram[offset]);
303	314	fg_tilemap->mark_tile_dirty(offset);
304	315	}
305	316
306		static WRITE16_HANDLER( rdx_tx_vram_w )
	317	WRITE16_MEMBER(r2dx_v33_state::rdx_tx_vram_w)
307	318	{
308	319	COMBINE_DATA(&tx_vram[offset]);
309	320	tx_tilemap->mark_tile_dirty(offset);
310	321	}
311	322
312		static READ16_HANDLER( rdx_v33_unknown_r )
	323	READ16_MEMBER(r2dx_v33_state::rdx_v33_unknown_r)
313	324	{
314		return space->machine().rand();
	325	return machine().rand();
315	326	}
316	327
317	328
318	329	static UINT16 mcu_xval,mcu_yval;
319	330
320	331	/* something sent to the MCU for X/Y global screen calculating ... */
321		static WRITE16_HANDLER( mcu_xval_w )
	332	WRITE16_MEMBER(r2dx_v33_state::mcu_xval_w)
322	333	{
323	334	mcu_xval = data;
324	335	//popmessage("%04x %04x",mcu_xval,mcu_yval);
325	336	}
326	337
327		static WRITE16_HANDLER( mcu_yval_w )
	338	WRITE16_MEMBER(r2dx_v33_state::mcu_yval_w)
328	339	{
329	340	mcu_yval = data;
330	341	//popmessage("%04x %04x",mcu_xval,mcu_yval);
r14845	r14846
333	344	static UINT16 mcu_data[9];
334	345
335	346	/* 0x400-0x407 seems some DMA hook-up, 0x420-0x427 looks like some x/y sprite calculation routine */
336		static WRITE16_HANDLER( mcu_table_w )
	347	WRITE16_MEMBER(r2dx_v33_state::mcu_table_w)
337	348	{
338	349	mcu_data[offset] = data;
339	350
340	351	//popmessage("%04x %04x %04x %04x | %04x %04x %04x %04x",mcu_data[0/2],mcu_data[2/2],mcu_data[4/2],mcu_data[6/2],mcu_data[8/2],mcu_data[0xa/2],mcu_data[0xc/2],mcu_data[0xe/2]);
341	352	}
342	353
343		static WRITE16_HANDLER( mcu_table2_w )
	354	WRITE16_MEMBER(r2dx_v33_state::mcu_table2_w)
344	355	{
345	356	mcu_data[offset+4] = data;
346	357
r14845	r14846
351	362	static ADDRESS_MAP_START( rdx_v33_map, AS_PROGRAM, 16, r2dx_v33_state )
352	363	AM_RANGE(0x00000, 0x003ff) AM_RAM // vectors copied here
353	364
354		AM_RANGE(0x00400, 0x00407) AM_WRITE_LEGACY(mcu_table_w)
355		AM_RANGE(0x00420, 0x00429) AM_WRITE_LEGACY(mcu_table2_w)
	365	AM_RANGE(0x00400, 0x00407) AM_WRITE(mcu_table_w)
	366	AM_RANGE(0x00420, 0x00429) AM_WRITE(mcu_table2_w)
356	367
357	368	/* results from cop? */
358		AM_RANGE(0x00430, 0x00431) AM_READ_LEGACY(rdx_v33_unknown_r)
359		AM_RANGE(0x00432, 0x00433) AM_READ_LEGACY(rdx_v33_unknown_r)
360		AM_RANGE(0x00434, 0x00435) AM_READ_LEGACY(rdx_v33_unknown_r)
361		AM_RANGE(0x00436, 0x00437) AM_READ_LEGACY(rdx_v33_unknown_r)
	369	AM_RANGE(0x00430, 0x00431) AM_READ(rdx_v33_unknown_r)
	370	AM_RANGE(0x00432, 0x00433) AM_READ(rdx_v33_unknown_r)
	371	AM_RANGE(0x00434, 0x00435) AM_READ(rdx_v33_unknown_r)
	372	AM_RANGE(0x00436, 0x00437) AM_READ(rdx_v33_unknown_r)
362	373
363	374	AM_RANGE(0x00600, 0x0064f) AM_RAM AM_BASE_LEGACY(&seibu_crtc_regs)
364	375	AM_RANGE(0x00650, 0x0068f) AM_RAM //???
r14845	r14846
370	381	//  AM_RANGE(0x006b6, 0x006b7) AM_WRITENOP
371	382	AM_RANGE(0x006bc, 0x006bd) AM_WRITE_LEGACY(mcu_prog_offs_w)
372	383	AM_RANGE(0x006be, 0x006bf) AM_WRITENOP // MCU program related
373		AM_RANGE(0x006d8, 0x006d9) AM_WRITE_LEGACY(mcu_xval_w)
374		AM_RANGE(0x006da, 0x006db) AM_WRITE_LEGACY(mcu_yval_w)
	384	AM_RANGE(0x006d8, 0x006d9) AM_WRITE(mcu_xval_w)
	385	AM_RANGE(0x006da, 0x006db) AM_WRITE(mcu_yval_w)
375	386	//  AM_RANGE(0x006dc, 0x006dd) AM_READ_LEGACY(rdx_v33_unknown2_r)
376	387	//  AM_RANGE(0x006de, 0x006df) AM_WRITE_LEGACY(mcu_unkaa_w) // mcu command related?
377	388
r14845	r14846
388	399
389	400	AM_RANGE(0x0c000, 0x0c7ff) AM_RAM AM_BASE(m_spriteram)
390	401	AM_RANGE(0x0c800, 0x0cfff) AM_RAM
391		AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE_LEGACY(rdx_bg_vram_w) AM_BASE_LEGACY(&bg_vram)
392		AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE_LEGACY(rdx_md_vram_w) AM_BASE_LEGACY(&md_vram)
393		AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE_LEGACY(rdx_fg_vram_w) AM_BASE_LEGACY(&fg_vram)
394		AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE_LEGACY(rdx_tx_vram_w) AM_BASE_LEGACY(&tx_vram)
	402	AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(rdx_bg_vram_w) AM_BASE_LEGACY(&bg_vram)
	403	AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(rdx_md_vram_w) AM_BASE_LEGACY(&md_vram)
	404	AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(rdx_fg_vram_w) AM_BASE_LEGACY(&fg_vram)
	405	AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(rdx_tx_vram_w) AM_BASE_LEGACY(&tx_vram)
395	406	AM_RANGE(0x0f800, 0x0ffff) AM_RAM /* Stack area */
396	407	AM_RANGE(0x10000, 0x1efff) AM_RAM
397	408	AM_RANGE(0x1f000, 0x1ffff) AM_RAM_WRITE_LEGACY(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)
r14845	r14846
400	411	AM_RANGE(0x40000, 0xfffff) AM_ROM AM_REGION("mainprg", 0x40000 )
401	412	ADDRESS_MAP_END
402	413
403		static READ16_HANDLER( nzerotea_sound_comms_r )
	414	READ16_MEMBER(r2dx_v33_state::nzerotea_sound_comms_r)
404	415	{
405	416	switch(offset+0x780)
406	417	{
407		case (0x788/2):   return seibu_main_word_r(space,2,0xffff);
408		case (0x78c/2):   return seibu_main_word_r(space,3,0xffff);
409		case (0x794/2): return seibu_main_word_r(space,5,0xffff);
	418	case (0x788/2):   return seibu_main_word_r(&space,2,0xffff);
	419	case (0x78c/2):   return seibu_main_word_r(&space,3,0xffff);
	420	case (0x794/2): return seibu_main_word_r(&space,5,0xffff);
410	421	}
411	422
412	423	return 0xffff;
413	424	}
414	425
415	426
416		static WRITE16_HANDLER( nzerotea_sound_comms_w )
	427	WRITE16_MEMBER(r2dx_v33_state::nzerotea_sound_comms_w)
417	428	{
418	429	switch(offset+0x780)
419	430	{
420		case (0x780/2): { seibu_main_word_w(space,0,data,0x00ff); break; }
421		case (0x784/2): { seibu_main_word_w(space,1,data,0x00ff); break; }
422		//case (0x790/2): { seibu_main_word_w(space,4,data,0x00ff); break; }
423		case (0x794/2): { seibu_main_word_w(space,4,data,0x00ff); break; }
424		case (0x798/2): { seibu_main_word_w(space,6,data,0x00ff); break; }
	431	case (0x780/2): { seibu_main_word_w(&space,0,data,0x00ff); break; }
	432	case (0x784/2): { seibu_main_word_w(&space,1,data,0x00ff); break; }
	433	//case (0x790/2): { seibu_main_word_w(&space,4,data,0x00ff); break; }
	434	case (0x794/2): { seibu_main_word_w(&space,4,data,0x00ff); break; }
	435	case (0x798/2): { seibu_main_word_w(&space,6,data,0x00ff); break; }
425	436	}
426	437	}
427	438
r14845	r14846
429	440	AM_RANGE(0x00000, 0x003ff) AM_RAM //stack area
430	441
431	442	/* results from cop? */
432		AM_RANGE(0x00430, 0x00431) AM_READ_LEGACY(rdx_v33_unknown_r)
433		AM_RANGE(0x00432, 0x00433) AM_READ_LEGACY(rdx_v33_unknown_r)
434		AM_RANGE(0x00434, 0x00435) AM_READ_LEGACY(rdx_v33_unknown_r)
435		AM_RANGE(0x00436, 0x00437) AM_READ_LEGACY(rdx_v33_unknown_r)
	443	AM_RANGE(0x00430, 0x00431) AM_READ(rdx_v33_unknown_r)
	444	AM_RANGE(0x00432, 0x00433) AM_READ(rdx_v33_unknown_r)
	445	AM_RANGE(0x00434, 0x00435) AM_READ(rdx_v33_unknown_r)
	446	AM_RANGE(0x00436, 0x00437) AM_READ(rdx_v33_unknown_r)
436	447
437		AM_RANGE(0x00400, 0x00407) AM_WRITE_LEGACY(mcu_table_w)
438		AM_RANGE(0x00420, 0x00427) AM_WRITE_LEGACY(mcu_table2_w)
	448	AM_RANGE(0x00400, 0x00407) AM_WRITE(mcu_table_w)
	449	AM_RANGE(0x00420, 0x00427) AM_WRITE(mcu_table2_w)
439	450
440	451	AM_RANGE(0x00600, 0x0064f) AM_RAM AM_BASE_LEGACY(&seibu_crtc_regs)
441	452
r14845	r14846
454	465	AM_RANGE(0x0074c, 0x0074d) AM_READ_PORT("SYSTEM")
455	466	//  AM_RANGE(0x00762, 0x00763) AM_READ_LEGACY(nzerotea_unknown_r)
456	467
457		AM_RANGE(0x00780, 0x0079f) AM_READWRITE_LEGACY(nzerotea_sound_comms_r,nzerotea_sound_comms_w)
	468	AM_RANGE(0x00780, 0x0079f) AM_READWRITE(nzerotea_sound_comms_r,nzerotea_sound_comms_w)
458	469
459	470	AM_RANGE(0x00800, 0x00fff) AM_RAM
460	471	AM_RANGE(0x01000, 0x0bfff) AM_RAM
461	472
462	473	AM_RANGE(0x0c000, 0x0c7ff) AM_RAM AM_BASE(m_spriteram)
463	474	AM_RANGE(0x0c800, 0x0cfff) AM_RAM
464		AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE_LEGACY(rdx_bg_vram_w) AM_BASE_LEGACY(&bg_vram)
465		AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE_LEGACY(rdx_md_vram_w) AM_BASE_LEGACY(&md_vram)
466		AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE_LEGACY(rdx_fg_vram_w) AM_BASE_LEGACY(&fg_vram)
467		AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE_LEGACY(rdx_tx_vram_w) AM_BASE_LEGACY(&tx_vram)
	475	AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(rdx_bg_vram_w) AM_BASE_LEGACY(&bg_vram)
	476	AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(rdx_md_vram_w) AM_BASE_LEGACY(&md_vram)
	477	AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(rdx_fg_vram_w) AM_BASE_LEGACY(&fg_vram)
	478	AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(rdx_tx_vram_w) AM_BASE_LEGACY(&tx_vram)
468	479	AM_RANGE(0x0f800, 0x0ffff) AM_RAM /* Stack area */
469	480	AM_RANGE(0x10000, 0x1efff) AM_RAM
470	481	AM_RANGE(0x1f000, 0x1ffff) AM_RAM_WRITE_LEGACY(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)

src/mame/drivers/lastfght.c

r14845	r14846
102	102
103	103	/* memory */
104	104	UINT8   m_colorram[256 * 3];
	105	DECLARE_WRITE16_MEMBER(colordac_w);
	106	DECLARE_WRITE16_MEMBER(lastfght_hi_w);
	107	DECLARE_WRITE16_MEMBER(lastfght_x_w);
	108	DECLARE_WRITE16_MEMBER(lastfght_yw_w);
	109	DECLARE_WRITE16_MEMBER(lastfght_h_w);
	110	DECLARE_WRITE16_MEMBER(lastfght_sx_w);
	111	DECLARE_WRITE16_MEMBER(lastfght_sy_w);
	112	DECLARE_WRITE16_MEMBER(lastfght_sr_w);
	113	DECLARE_WRITE16_MEMBER(lastfght_sd_w);
	114	DECLARE_WRITE16_MEMBER(lastfght_blit_w);
	115	DECLARE_WRITE16_MEMBER(lastfght_dest_w);
	116	DECLARE_READ16_MEMBER(lastfght_c00000_r);
	117	DECLARE_READ16_MEMBER(lastfght_c00002_r);
	118	DECLARE_READ16_MEMBER(lastfght_c00004_r);
	119	DECLARE_READ16_MEMBER(lastfght_c00006_r);
	120	DECLARE_WRITE16_MEMBER(lastfght_c00006_w);
	121	DECLARE_READ16_MEMBER(lastfght_sound_r);
	122	DECLARE_WRITE16_MEMBER(lastfght_sound_w);
105	123	};
106	124
107	125
r14845	r14846
165	183
166	184	// Palette: HMC HM86171 VGA 256 colour RAMDAC
167	185
168		static WRITE16_HANDLER( colordac_w )
	186	WRITE16_MEMBER(lastfght_state::colordac_w)
169	187	{
170		lastfght_state *state = space->machine().driver_data<lastfght_state>();
171	188
172	189	if (ACCESSING_BITS_0_7)
173	190	{
174		state->m_colorram[state->m_clr_offset] = data;
175		palette_set_color_rgb(space->machine(), state->m_clr_offset / 3,
176		pal6bit(state->m_colorram[(state->m_clr_offset / 3) * 3 + 0]),
177		pal6bit(state->m_colorram[(state->m_clr_offset / 3) * 3 + 1]),
178		pal6bit(state->m_colorram[(state->m_clr_offset / 3) * 3 + 2])
	191	m_colorram[m_clr_offset] = data;
	192	palette_set_color_rgb(machine(), m_clr_offset / 3,
	193	pal6bit(m_colorram[(m_clr_offset / 3) * 3 + 0]),
	194	pal6bit(m_colorram[(m_clr_offset / 3) * 3 + 1]),
	195	pal6bit(m_colorram[(m_clr_offset / 3) * 3 + 2])
179	196	);
180		state->m_clr_offset = (state->m_clr_offset + 1) % (256 * 3);
	197	m_clr_offset = (m_clr_offset + 1) % (256 * 3);
181	198	}
182	199	if (ACCESSING_BITS_8_15)
183	200	{
184		state->m_clr_offset = (data >> 8) * 3;
	201	m_clr_offset = (data >> 8) * 3;
185	202	}
186	203	}
187	204
188	205	//  Blitter (supports zooming)
189	206
190	207	// high byte of a 16 bit register
191		static WRITE16_HANDLER( lastfght_hi_w )
	208	WRITE16_MEMBER(lastfght_state::lastfght_hi_w)
192	209	{
193		lastfght_state *state = space->machine().driver_data<lastfght_state>();
194	210
195	211	if (ACCESSING_BITS_8_15)
196		logerror("%06x: 600000.b = %02x\n", cpu_get_pc(&space->device()), data >> 8);
	212	logerror("%06x: 600000.b = %02x\n", cpu_get_pc(&space.device()), data >> 8);
197	213	if (ACCESSING_BITS_0_7)
198	214	{
199		state->m_hi = data << 8;
200		//logerror("%06x: lastfght_hi  = %02x\n", cpu_get_pc(&space->device()), data);
	215	m_hi = data << 8;
	216	//logerror("%06x: lastfght_hi  = %02x\n", cpu_get_pc(&space.device()), data);
201	217	}
202	218	}
203	219
204	220	// screen x
205		static WRITE16_HANDLER( lastfght_x_w )
	221	WRITE16_MEMBER(lastfght_state::lastfght_x_w)
206	222	{
207		lastfght_state *state = space->machine().driver_data<lastfght_state>();
208	223
209	224	if (ACCESSING_BITS_8_15)
210		logerror("%06x: 800008.b = %02x\n", cpu_get_pc(&space->device()), data >> 8);
	225	logerror("%06x: 800008.b = %02x\n", cpu_get_pc(&space.device()), data >> 8);
211	226	if (ACCESSING_BITS_0_7)
212	227	{
213		state->m_x = state->m_hi | data;
214		//logerror("%06x: lastfght_x   = %02x\n", cpu_get_pc(&space->device()),data);
	228	m_x = m_hi | data;
	229	//logerror("%06x: lastfght_x   = %02x\n", cpu_get_pc(&space.device()),data);
215	230	}
216	231	}
217	232
218	233	// screen y, screen width - 1
219		static WRITE16_HANDLER( lastfght_yw_w )
	234	WRITE16_MEMBER(lastfght_state::lastfght_yw_w)
220	235	{
221		lastfght_state *state = space->machine().driver_data<lastfght_state>();
222	236
223	237	if (ACCESSING_BITS_8_15)
224	238	{
225		state->m_y = state->m_hi | (data >> 8);
226		//logerror("%06x: lastfght_y   = %02x\n", cpu_get_pc(&space->device()), data >> 8);
	239	m_y = m_hi | (data >> 8);
	240	//logerror("%06x: lastfght_y   = %02x\n", cpu_get_pc(&space.device()), data >> 8);
227	241	}
228	242	if (ACCESSING_BITS_0_7)
229	243	{
230		state->m_w = state->m_hi | data;
231		//logerror("%06x: lastfght_w   = %02x\n", cpu_get_pc(&space->device()), data);
	244	m_w = m_hi | data;
	245	//logerror("%06x: lastfght_w   = %02x\n", cpu_get_pc(&space.device()), data);
232	246	}
233	247	}
234	248
235	249	// screen height - 1
236		static WRITE16_HANDLER( lastfght_h_w )
	250	WRITE16_MEMBER(lastfght_state::lastfght_h_w)
237	251	{
238		lastfght_state *state = space->machine().driver_data<lastfght_state>();
239	252
240	253	if (ACCESSING_BITS_8_15)
241	254	{
242		state->m_h = state->m_hi | (data >> 8);
243		//logerror("%06x: lastfght_h   = %02x\n", cpu_get_pc(&space->device()), data >> 8);
	255	m_h = m_hi | (data >> 8);
	256	//logerror("%06x: lastfght_h   = %02x\n", cpu_get_pc(&space.device()), data >> 8);
244	257	}
245	258	if (ACCESSING_BITS_0_7)
246		logerror("%06x: 80000d.b = %02x\n", cpu_get_pc(&space->device()), data);
	259	logerror("%06x: 80000d.b = %02x\n", cpu_get_pc(&space.device()), data);
247	260	}
248	261
249	262	// source delta x << 6, source x << 6
250		static WRITE16_HANDLER( lastfght_sx_w )
	263	WRITE16_MEMBER(lastfght_state::lastfght_sx_w)
251	264	{
252		lastfght_state *state = space->machine().driver_data<lastfght_state>();
253	265
254	266	if (ACCESSING_BITS_8_15)
255	267	{
256		state->m_dsx = state->m_hi | (data >> 8);
257		//logerror("%06x: lastfght_dsx = %02x\n", cpu_get_pc(&space->device()), data >> 8);
	268	m_dsx = m_hi | (data >> 8);
	269	//logerror("%06x: lastfght_dsx = %02x\n", cpu_get_pc(&space.device()), data >> 8);
258	270	}
259	271	if (ACCESSING_BITS_0_7)
260	272	{
261		state->m_sx = state->m_hi | data;
262		//logerror("%06x: lastfght_sx  = %02x\n", cpu_get_pc(&space->device()), data);
	273	m_sx = m_hi | data;
	274	//logerror("%06x: lastfght_sx  = %02x\n", cpu_get_pc(&space.device()), data);
263	275	}
264	276	}
265	277
266	278	// source y << 6, source y1 << 6
267		static WRITE16_HANDLER( lastfght_sy_w )
	279	WRITE16_MEMBER(lastfght_state::lastfght_sy_w)
268	280	{
269		lastfght_state *state = space->machine().driver_data<lastfght_state>();
270	281
271	282	if (ACCESSING_BITS_8_15)
272	283	{
273		state->m_sy = state->m_hi | (data >> 8);
274		//logerror("%06x: lastfght_sy  = %02x\n", cpu_get_pc(&space->device()), data >> 8);
	284	m_sy = m_hi | (data >> 8);
	285	//logerror("%06x: lastfght_sy  = %02x\n", cpu_get_pc(&space.device()), data >> 8);
275	286	}
276	287	if (ACCESSING_BITS_0_7)
277	288	{
278		state->m_sy1 = state->m_hi | data;
279		//logerror("%06x: lastfght_sy1 = %02x\n", cpu_get_pc(&space->device()), data);
	289	m_sy1 = m_hi | data;
	290	//logerror("%06x: lastfght_sy1 = %02x\n", cpu_get_pc(&space.device()), data);
280	291	}
281	292	}
282	293
283	294	// source rom (0x200000 bytes), source page (512x256 bytes)
284		static WRITE16_HANDLER( lastfght_sr_w )
	295	WRITE16_MEMBER(lastfght_state::lastfght_sr_w)
285	296	{
286		lastfght_state *state = space->machine().driver_data<lastfght_state>();
287	297
288	298	if (ACCESSING_BITS_8_15)
289	299	{
290		state->m_sp = (state->m_hi >> 8) >> 4;
291		//logerror("%06x: lastfght_sp  = %02x\n", cpu_get_pc(&space->device()), data >> 8);
	300	m_sp = (m_hi >> 8) >> 4;
	301	//logerror("%06x: lastfght_sp  = %02x\n", cpu_get_pc(&space.device()), data >> 8);
292	302	}
293	303	if (ACCESSING_BITS_0_7)
294	304	{
295		state->m_sr = data;
296		//logerror("%06x: lastfght_sr  = %02x\n", cpu_get_pc(&space->device()), data);
	305	m_sr = data;
	306	//logerror("%06x: lastfght_sr  = %02x\n", cpu_get_pc(&space.device()), data);
297	307	}
298	308	}
299	309
300	310	// source x1 << 6, source delta y << 6
301		static WRITE16_HANDLER( lastfght_sd_w )
	311	WRITE16_MEMBER(lastfght_state::lastfght_sd_w)
302	312	{
303		lastfght_state *state = space->machine().driver_data<lastfght_state>();
304	313
305	314	if (ACCESSING_BITS_8_15)
306	315	{
307		state->m_sx1 = state->m_hi | (data >> 8);
308		//logerror("%06x: lastfght_sx1 = %02x\n", cpu_get_pc(&space->device()), data >> 8);
	316	m_sx1 = m_hi | (data >> 8);
	317	//logerror("%06x: lastfght_sx1 = %02x\n", cpu_get_pc(&space.device()), data >> 8);
309	318	}
310	319	if (ACCESSING_BITS_0_7)
311	320	{
312		state->m_dsy = state->m_hi | data;
313		//logerror("%06x: lastfght_dsy = %02x\n", cpu_get_pc(&space->device()), data);
	321	m_dsy = m_hi | data;
	322	//logerror("%06x: lastfght_dsy = %02x\n", cpu_get_pc(&space.device()), data);
314	323	}
315	324	}
316	325
317	326	// start blit
318		static WRITE16_HANDLER( lastfght_blit_w )
	327	WRITE16_MEMBER(lastfght_state::lastfght_blit_w)
319	328	{
320		lastfght_state *state = space->machine().driver_data<lastfght_state>();
321	329
322	330	if (ACCESSING_BITS_8_15)
323	331	{
324	332	int x, y, addr;
325		UINT8 *gfxdata = space->machine().region( "gfx1" )->base();
326		bitmap_ind16 &dest = state->m_bitmap[state->m_dest];
	333	UINT8 *gfxdata = machine().region( "gfx1" )->base();
	334	bitmap_ind16 &dest = m_bitmap[m_dest];
327	335
328	336	#if 0
329		logerror("%06x: blit x %03x, y %03x, w %03x, h %03x, sx %03x.%02x, sx1 %03x.%02x, dsx %03x.%02x, sy %03x.%02x, sy1 %03x.%02x, dsy %03x.%02x, sp %02x, sr %02x, data %02x\n", cpu_get_pc(&space->device()),
330		state->m_x, state->m_y, state->m_w + 1, state->m_h + 1,
331		state->m_sx >> 6, state->m_sx & 0x3f, state->m_sx1 >> 6, state->m_dsx & 0x3f, state->m_sx1 >> 6, state->m_sx1 & 0x3f,
332		state->m_sy >> 6, state->m_sy & 0x3f, state->m_sy1 >> 6, state->m_dsy & 0x3f, state->m_sy1 >> 6, state->m_sy1 & 0x3f,
333		state->m_sp, state->m_sr,
	337	logerror("%06x: blit x %03x, y %03x, w %03x, h %03x, sx %03x.%02x, sx1 %03x.%02x, dsx %03x.%02x, sy %03x.%02x, sy1 %03x.%02x, dsy %03x.%02x, sp %02x, sr %02x, data %02x\n", cpu_get_pc(&space.device()),
	338	m_x, m_y, m_w + 1, m_h + 1,
	339	m_sx >> 6, m_sx & 0x3f, m_sx1 >> 6, m_dsx & 0x3f, m_sx1 >> 6, m_sx1 & 0x3f,
	340	m_sy >> 6, m_sy & 0x3f, m_sy1 >> 6, m_dsy & 0x3f, m_sy1 >> 6, m_sy1 & 0x3f,
	341	m_sp, m_sr,
334	342	data >> 8);
335	343	#endif
336	344
337		for (y = 0; y <= state->m_h; y++)
	345	for (y = 0; y <= m_h; y++)
338	346	{
339		for (x = 0; x <= state->m_w; x++)
	347	for (x = 0; x <= m_w; x++)
340	348	{
341		addr = (((state->m_sx + state->m_sx1 + state->m_dsx * x) >> 6) & 0x1ff) +
342		(((state->m_sy + state->m_sy1 + state->m_dsy * y) >> 6) & 0xff) * 0x200 +
343		state->m_sp * 0x200 * 0x100 + state->m_sr * 0x200000;
	349	addr = (((m_sx + m_sx1 + m_dsx * x) >> 6) & 0x1ff) +
	350	(((m_sy + m_sy1 + m_dsy * y) >> 6) & 0xff) * 0x200 +
	351	m_sp * 0x200 * 0x100 + m_sr * 0x200000;
344	352
345	353	data = gfxdata[addr];
346	354
347		if (data && (state->m_x + x >= 0) && (state->m_x + x < 512) && (state->m_y + y >= 0) && (state->m_y + y < 256))
348		dest.pix16(state->m_y + y, state->m_x + x) = data;
	355	if (data && (m_x + x >= 0) && (m_x + x < 512) && (m_y + y >= 0) && (m_y + y < 256))
	356	dest.pix16(m_y + y, m_x + x) = data;
349	357	}
350	358	}
351	359	}
352	360	if (ACCESSING_BITS_0_7)
353		logerror("%06x: 600007.b = %02x\n", cpu_get_pc(&space->device()), data);
	361	logerror("%06x: 600007.b = %02x\n", cpu_get_pc(&space.device()), data);
354	362	}
355	363
356	364	// toggle framebuffer
357		static WRITE16_HANDLER( lastfght_dest_w )
	365	WRITE16_MEMBER(lastfght_state::lastfght_dest_w)
358	366	{
359		lastfght_state *state = space->machine().driver_data<lastfght_state>();
360	367
361	368	if (ACCESSING_BITS_0_7)
362		state->m_dest ^= 1;
	369	m_dest ^= 1;
363	370	}
364	371
365		static READ16_HANDLER( lastfght_c00000_r )
	372	READ16_MEMBER(lastfght_state::lastfght_c00000_r)
366	373	{
367	374	// high byte:
368	375	// bit 7 = blitter busy
r14845	r14846
371	378
372	379	}
373	380
374		static READ16_HANDLER( lastfght_c00002_r )
	381	READ16_MEMBER(lastfght_state::lastfght_c00002_r)
375	382	{
376	383	// high byte:
377	384	// mask 0x1c: from sound?
378		return (space->machine().rand() & 0x1c00) | input_port_read(space->machine(), "IN0");
	385	return (machine().rand() & 0x1c00) | input_port_read(machine(), "IN0");
379	386	}
380	387
381		static READ16_HANDLER( lastfght_c00004_r )
	388	READ16_MEMBER(lastfght_state::lastfght_c00004_r)
382	389	{
383		return input_port_read(space->machine(), "IN1");
	390	return input_port_read(machine(), "IN1");
384	391	}
385	392
386		static READ16_HANDLER( lastfght_c00006_r )
	393	READ16_MEMBER(lastfght_state::lastfght_c00006_r)
387	394	{
388	395	// low byte:
389	396	// bit 7 = protection?
390	397	// bit 5 = blitter?
391		return input_port_read(space->machine(), "IN2");
	398	return input_port_read(machine(), "IN2");
392	399	}
393	400
394		static WRITE16_HANDLER( lastfght_c00006_w )
	401	WRITE16_MEMBER(lastfght_state::lastfght_c00006_w)
395	402	{
396		lastfght_state *state = space->machine().driver_data<lastfght_state>();
397		COMBINE_DATA(&state->m_c00006);
398		//  popmessage("%04x", state->m_c00006);
	403	COMBINE_DATA(&m_c00006);
	404	//  popmessage("%04x", m_c00006);
399	405	}
400	406
401		static READ16_HANDLER( lastfght_sound_r )
	407	READ16_MEMBER(lastfght_state::lastfght_sound_r)
402	408	{
403	409	// low byte:
404	410	// bit 3
405	411	return 8;
406	412	}
407	413
408		static WRITE16_HANDLER( lastfght_sound_w )
	414	WRITE16_MEMBER(lastfght_state::lastfght_sound_w)
409	415	{
410	416	if (ACCESSING_BITS_8_15)
411		logerror("%06x: sound_w msb = %02x\n", cpu_get_pc(&space->device()), data >> 8);
	417	logerror("%06x: sound_w msb = %02x\n", cpu_get_pc(&space.device()), data >> 8);
412	418	if (ACCESSING_BITS_0_7)
413		logerror("%06x: sound_w lsb = %02x\n", cpu_get_pc(&space->device()), data);
	419	logerror("%06x: sound_w lsb = %02x\n", cpu_get_pc(&space.device()), data);
414	420	}
415	421
416	422	/***************************************************************************
r14845	r14846
425	431
426	432	AM_RANGE( 0x200000, 0x20ffff ) AM_RAM AM_SHARE("nvram")   // battery
427	433
428		AM_RANGE( 0x600000, 0x600001 ) AM_WRITE_LEGACY(lastfght_hi_w )
429		AM_RANGE( 0x600002, 0x600003 ) AM_READWRITE_LEGACY(lastfght_sound_r, lastfght_sound_w )
430		AM_RANGE( 0x600006, 0x600007 ) AM_WRITE_LEGACY(lastfght_blit_w )
431		AM_RANGE( 0x600008, 0x600009 ) AM_WRITE_LEGACY(colordac_w )
	434	AM_RANGE( 0x600000, 0x600001 ) AM_WRITE(lastfght_hi_w )
	435	AM_RANGE( 0x600002, 0x600003 ) AM_READWRITE(lastfght_sound_r, lastfght_sound_w )
	436	AM_RANGE( 0x600006, 0x600007 ) AM_WRITE(lastfght_blit_w )
	437	AM_RANGE( 0x600008, 0x600009 ) AM_WRITE(colordac_w )
432	438	AM_RANGE( 0x60000a, 0x60000b ) AM_WRITENOP   // colordac?
433	439
434		AM_RANGE( 0x800000, 0x800001 ) AM_WRITE_LEGACY(lastfght_sx_w )
435		AM_RANGE( 0x800002, 0x800003 ) AM_WRITE_LEGACY(lastfght_sd_w )
436		AM_RANGE( 0x800004, 0x800005 ) AM_WRITE_LEGACY(lastfght_sy_w )
437		AM_RANGE( 0x800006, 0x800007 ) AM_WRITE_LEGACY(lastfght_sr_w )
438		AM_RANGE( 0x800008, 0x800009 ) AM_WRITE_LEGACY(lastfght_x_w )
439		AM_RANGE( 0x80000a, 0x80000b ) AM_WRITE_LEGACY(lastfght_yw_w )
440		AM_RANGE( 0x80000c, 0x80000d ) AM_WRITE_LEGACY(lastfght_h_w )
	440	AM_RANGE( 0x800000, 0x800001 ) AM_WRITE(lastfght_sx_w )
	441	AM_RANGE( 0x800002, 0x800003 ) AM_WRITE(lastfght_sd_w )
	442	AM_RANGE( 0x800004, 0x800005 ) AM_WRITE(lastfght_sy_w )
	443	AM_RANGE( 0x800006, 0x800007 ) AM_WRITE(lastfght_sr_w )
	444	AM_RANGE( 0x800008, 0x800009 ) AM_WRITE(lastfght_x_w )
	445	AM_RANGE( 0x80000a, 0x80000b ) AM_WRITE(lastfght_yw_w )
	446	AM_RANGE( 0x80000c, 0x80000d ) AM_WRITE(lastfght_h_w )
441	447
442		AM_RANGE( 0x800014, 0x800015 ) AM_WRITE_LEGACY(lastfght_dest_w )
	448	AM_RANGE( 0x800014, 0x800015 ) AM_WRITE(lastfght_dest_w )
443	449
444		AM_RANGE( 0xc00000, 0xc00001 ) AM_READ_LEGACY(lastfght_c00000_r )
445		AM_RANGE( 0xc00002, 0xc00003 ) AM_READ_LEGACY(lastfght_c00002_r )
446		AM_RANGE( 0xc00004, 0xc00005 ) AM_READ_LEGACY(lastfght_c00004_r )
447		AM_RANGE( 0xc00006, 0xc00007 ) AM_READWRITE_LEGACY(lastfght_c00006_r, lastfght_c00006_w )
	450	AM_RANGE( 0xc00000, 0xc00001 ) AM_READ(lastfght_c00000_r )
	451	AM_RANGE( 0xc00002, 0xc00003 ) AM_READ(lastfght_c00002_r )
	452	AM_RANGE( 0xc00004, 0xc00005 ) AM_READ(lastfght_c00004_r )
	453	AM_RANGE( 0xc00006, 0xc00007 ) AM_READWRITE(lastfght_c00006_r, lastfght_c00006_w )
448	454
449	455	AM_RANGE( 0xff0000, 0xffffff ) AM_RAM
450	456	ADDRESS_MAP_END

src/mame/drivers/embargo.c

r14845	r14846
22	22	UINT8    m_dial_enable_1;
23	23	UINT8    m_dial_enable_2;
24	24	UINT8    m_input_select;
	25	DECLARE_READ8_MEMBER(input_port_bit_r);
	26	DECLARE_READ8_MEMBER(dial_r);
	27	DECLARE_WRITE8_MEMBER(port_1_w);
	28	DECLARE_WRITE8_MEMBER(port_2_w);
	29	DECLARE_WRITE8_MEMBER(input_select_w);
25	30	};
26	31
27	32
r14845	r14846
65	70	*
66	71	*************************************/
67	72
68		static READ8_HANDLER( input_port_bit_r )
	73	READ8_MEMBER(embargo_state::input_port_bit_r)
69	74	{
70		embargo_state *state = space->machine().driver_data<embargo_state>();
71		return (input_port_read(space->machine(), "IN1") << (7 - state->m_input_select)) & 0x80;
	75	return (input_port_read(machine(), "IN1") << (7 - m_input_select)) & 0x80;
72	76	}
73	77
74	78
75		static READ8_HANDLER( dial_r )
	79	READ8_MEMBER(embargo_state::dial_r)
76	80	{
77		embargo_state *state = space->machine().driver_data<embargo_state>();
78	81
79	82	UINT8 lo = 0;
80	83	UINT8 hi = 0;
r14845	r14846
92	95	0x09, 0x0a, 0x08, 0x09, 0x08, 0x05, 0x07, 0x06
93	96	};
94	97
95		if (state->m_dial_enable_1 && !state->m_dial_enable_2)
	98	if (m_dial_enable_1 && !m_dial_enable_2)
96	99	{
97		lo = input_port_read(space->machine(), "DIAL0");
98		hi = input_port_read(space->machine(), "DIAL1");
	100	lo = input_port_read(machine(), "DIAL0");
	101	hi = input_port_read(machine(), "DIAL1");
99	102	}
100	103
101		if (state->m_dial_enable_2 && !state->m_dial_enable_1)
	104	if (m_dial_enable_2 && !m_dial_enable_1)
102	105	{
103		lo = input_port_read(space->machine(), "DIAL2");
104		hi = input_port_read(space->machine(), "DIAL3");
	106	lo = input_port_read(machine(), "DIAL2");
	107	hi = input_port_read(machine(), "DIAL3");
105	108	}
106	109
107	110	lo = 12 * lo / 256;
r14845	r14846
124	127	}
125	128
126	129
127		static WRITE8_HANDLER( port_1_w )
	130	WRITE8_MEMBER(embargo_state::port_1_w)
128	131	{
129		embargo_state *state = space->machine().driver_data<embargo_state>();
130		state->m_dial_enable_1 = data & 0x01; /* other bits unknown */
	132	m_dial_enable_1 = data & 0x01; /* other bits unknown */
131	133	}
132	134
133	135
134		static WRITE8_HANDLER( port_2_w )
	136	WRITE8_MEMBER(embargo_state::port_2_w)
135	137	{
136		embargo_state *state = space->machine().driver_data<embargo_state>();
137		state->m_dial_enable_2 = data & 0x01; /* other bits unknown */
	138	m_dial_enable_2 = data & 0x01; /* other bits unknown */
138	139	}
139	140
140	141
141		static WRITE8_HANDLER( input_select_w )
	142	WRITE8_MEMBER(embargo_state::input_select_w)
142	143	{
143		embargo_state *state = space->machine().driver_data<embargo_state>();
144		state->m_input_select = data & 0x07;
	144	m_input_select = data & 0x07;
145	145	}
146	146
147	147
r14845	r14846
167	167	*************************************/
168	168
169	169	static ADDRESS_MAP_START( main_io_map, AS_IO, 8, embargo_state )
170		AM_RANGE(0x01, 0x01) AM_READ_PORT("IN0") AM_WRITE_LEGACY(port_1_w)
171		AM_RANGE(0x02, 0x02) AM_READWRITE_LEGACY(dial_r, port_2_w)
	170	AM_RANGE(0x01, 0x01) AM_READ_PORT("IN0") AM_WRITE(port_1_w)
	171	AM_RANGE(0x02, 0x02) AM_READWRITE(dial_r, port_2_w)
172	172	AM_RANGE(0x03, 0x03) AM_WRITENOP /* always 0xFE */
173	173	AM_RANGE(S2650_DATA_PORT, S2650_DATA_PORT) AM_READ_PORT("IN2")
174		AM_RANGE(S2650_CTRL_PORT, S2650_CTRL_PORT) AM_READWRITE_LEGACY(input_port_bit_r, input_select_w)
	174	AM_RANGE(S2650_CTRL_PORT, S2650_CTRL_PORT) AM_READWRITE(input_port_bit_r, input_select_w)
175	175	ADDRESS_MAP_END
176	176
177	177

src/mame/drivers/warpsped.c

r14845	r14846
97	97	tilemap_t   *m_starfield_tilemap;
98	98	UINT8      *m_workram;
99	99	UINT8      m_regs[0x28];
	100	DECLARE_WRITE8_MEMBER(warpspeed_hardware_w);
	101	DECLARE_WRITE8_MEMBER(warpspeed_vidram_w);
100	102	};
101	103
102		static WRITE8_HANDLER( warpspeed_hardware_w )
	104	WRITE8_MEMBER(warpspeed_state::warpspeed_hardware_w)
103	105	{
104		warpspeed_state *state = space->machine().driver_data<warpspeed_state>();
105		state->m_regs[offset] = data;
	106	m_regs[offset] = data;
106	107	}
107	108
108	109	static TILE_GET_INFO( get_warpspeed_text_tile_info )
r14845	r14846
123	124	SET_TILE_INFO(1, code, 0, 0);
124	125	}
125	126
126		static WRITE8_HANDLER( warpspeed_vidram_w )
	127	WRITE8_MEMBER(warpspeed_state::warpspeed_vidram_w)
127	128	{
128		warpspeed_state *state = space->machine().driver_data<warpspeed_state>();
129	129
130		state->m_videoram[offset] = data;
131		state->m_text_tilemap->mark_tile_dirty(offset);
	130	m_videoram[offset] = data;
	131	m_text_tilemap->mark_tile_dirty(offset);
132	132	}
133	133
134	134	static VIDEO_START( warpspeed )
r14845	r14846
215	215
216	216	static ADDRESS_MAP_START( warpspeed_map, AS_PROGRAM, 8, warpspeed_state )
217	217	AM_RANGE(0x0000, 0x0dff) AM_ROM
218		AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE_LEGACY(warpspeed_vidram_w ) AM_BASE(m_videoram)
	218	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(warpspeed_vidram_w ) AM_BASE(m_videoram)
219	219	AM_RANGE(0x1c00, 0x1cff) AM_RAM AM_BASE(m_workram)
220	220	ADDRESS_MAP_END
221	221
r14845	r14846
225	225	AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1")
226	226	AM_RANGE(0x02, 0x02) AM_READ_PORT("DSW")
227	227	AM_RANGE(0x03, 0x03) AM_READ_PORT("IN2")
228		AM_RANGE(0x00, 0x27) AM_WRITE_LEGACY(warpspeed_hardware_w )
	228	AM_RANGE(0x00, 0x27) AM_WRITE(warpspeed_hardware_w )
229	229	ADDRESS_MAP_END
230	230
231	231	static INPUT_PORTS_START( warpspeed )

src/mame/drivers/spaceg.c

r14845	r14846
183	183	UINT8 *  m_colorram;
184	184	UINT8 *  m_io9400;
185	185	UINT8 *  m_io9401;
	186	DECLARE_WRITE8_MEMBER(zvideoram_w);
	187	DECLARE_READ8_MEMBER(spaceg_colorram_r);
186	188	};
187	189
188	190	/*************************************
r14845	r14846
218	220	palette_set_color (machine, 15, MAKE_RGB(0x7f,0x7f,0x7f));//???
219	221	}
220	222
221		static WRITE8_HANDLER( zvideoram_w )
	223	WRITE8_MEMBER(spaceg_state::zvideoram_w)
222	224	{
223		spaceg_state *state = space->machine().driver_data<spaceg_state>();
224		int col = state->m_colorram[0x400];
225		int xoff = *state->m_io9400 >> 5 & 7;
	225	int col = m_colorram[0x400];
	226	int xoff = *m_io9400 >> 5 & 7;
226	227	UINT16 offset2 = (offset + 0x100) & 0x1fff;
227	228	UINT16 sdata = data << (8 - xoff);
228		UINT16 vram_data = state->m_videoram[offset] << 8 | (state->m_videoram[offset2]);
	229	UINT16 vram_data = m_videoram[offset] << 8 | (m_videoram[offset2]);
229	230
230	231	if (col > 0x0f) popmessage("color > 0x0f = %2d", col);
231	232	col &= 0x0f;
232	233
233		switch (*state->m_io9401)
	234	switch (*m_io9401)
234	235	{
235	236	// draw
236	237	case 0:
r14845	r14846
240	241	vram_data |= sdata;
241	242
242	243	// update colorram
243		if (sdata&0xff00) state->m_colorram[offset] = col;
244		if (sdata&0x00ff) state->m_colorram[offset2] = col;
	244	if (sdata&0xff00) m_colorram[offset] = col;
	245	if (sdata&0x00ff) m_colorram[offset2] = col;
245	246	break;
246	247
247	248	// erase
r14845	r14846
250	251	break;
251	252
252	253	default:
253		logerror("mode = %02x pc = %04x\n", *state->m_io9401, cpu_get_pc(&space->device()));
254		popmessage("mode = %02x pc = %04x\n", *state->m_io9401, cpu_get_pc(&space->device()));
	254	logerror("mode = %02x pc = %04x\n", *m_io9401, cpu_get_pc(&space.device()));
	255	popmessage("mode = %02x pc = %04x\n", *m_io9401, cpu_get_pc(&space.device()));
255	256	return;
256	257	}
257	258
258		state->m_videoram[offset]=vram_data>>8;
259		state->m_videoram[offset2]=vram_data&0xff;
	259	m_videoram[offset]=vram_data>>8;
	260	m_videoram[offset2]=vram_data&0xff;
260	261	}
261	262
262	263
263		static READ8_HANDLER(spaceg_colorram_r)
	264	READ8_MEMBER(spaceg_state::spaceg_colorram_r)
264	265	{
265		spaceg_state *state = space->machine().driver_data<spaceg_state>();
266	266	int rgbcolor;
267	267
268	268	if (offset < 0x400)
269	269	{
270		rgbcolor = (state->m_colorram[offset] << 1) | ((offset &0x100) >> 8);
	270	rgbcolor = (m_colorram[offset] << 1) | ((offset &0x100) >> 8);
271	271
272	272	if ((offset >= 0x200) && (offset < 0x220)) /* 0xa200- 0xa21f */
273	273	{
274	274	/* palette 1 */
275	275	int col_ind = offset & 0x1f;
276		palette_set_color_rgb(space->machine(), 0x10 + 0x00 + col_ind, pal3bit(rgbcolor >> 0), pal3bit(rgbcolor >> 6), pal3bit(rgbcolor >> 3));
	276	palette_set_color_rgb(machine(), 0x10 + 0x00 + col_ind, pal3bit(rgbcolor >> 0), pal3bit(rgbcolor >> 6), pal3bit(rgbcolor >> 3));
277	277	}
278	278	else if ((offset >= 0x300) && (offset < 0x320)) /* 0xa300- 0xa31f */
279	279	{
280	280	/* palette 2 */
281	281	int col_ind = offset & 0x1f;
282		palette_set_color_rgb(space->machine(), 0x10 + 0x00 + col_ind, pal3bit(rgbcolor >> 0), pal3bit(rgbcolor >> 6), pal3bit(rgbcolor >> 3));
	282	palette_set_color_rgb(machine(), 0x10 + 0x00 + col_ind, pal3bit(rgbcolor >> 0), pal3bit(rgbcolor >> 6), pal3bit(rgbcolor >> 3));
283	283	}
284	284	else
285	285	logerror("palette? read from colorram offset = %04x\n",offset);
286	286	}
287	287
288		if (*state->m_io9401 != 0x40)
289		logerror("colorram read in mode: 9401 = %02x (offset = %04x)\n", *state->m_io9401, offset);
	288	if (*m_io9401 != 0x40)
	289	logerror("colorram read in mode: 9401 = %02x (offset = %04x)\n", *m_io9401, offset);
290	290
291		return state->m_colorram[offset];
	291	return m_colorram[offset];
292	292	}
293	293
294	294
r14845	r14846
328	328	AM_RANGE(0x3000, 0x3fff) AM_ROM
329	329	AM_RANGE(0x7000, 0x77ff) AM_RAM
330	330
331		AM_RANGE(0xa000, 0xbfff) AM_RAM_READ_LEGACY(spaceg_colorram_r) AM_BASE(m_colorram)
332		AM_RANGE(0xc000, 0xdfff) AM_RAM_WRITE_LEGACY(zvideoram_w) AM_BASE(m_videoram)
	331	AM_RANGE(0xa000, 0xbfff) AM_RAM_READ(spaceg_colorram_r) AM_BASE(m_colorram)
	332	AM_RANGE(0xc000, 0xdfff) AM_RAM_WRITE(zvideoram_w) AM_BASE(m_videoram)
333	333
334	334	AM_RANGE(0x9400, 0x9400) AM_WRITEONLY AM_BASE(m_io9400) /* gfx ctrl */
335	335	AM_RANGE(0x9401, 0x9401) AM_WRITEONLY AM_BASE(m_io9401) /* gfx ctrl */

src/mame/drivers/gei.c

r14845	r14846
92	92	int m_signature_answer;
93	93	int m_signature_pos;
94	94	UINT8 m_nmi_mask;
	95	DECLARE_WRITE8_MEMBER(gei_drawctrl_w);
	96	DECLARE_WRITE8_MEMBER(gei_bitmap_w);
	97	DECLARE_READ8_MEMBER(catchall);
	98	DECLARE_WRITE8_MEMBER(banksel_main_w);
	99	DECLARE_WRITE8_MEMBER(banksel_1_w);
	100	DECLARE_WRITE8_MEMBER(banksel_2_w);
	101	DECLARE_WRITE8_MEMBER(banksel_3_w);
	102	DECLARE_WRITE8_MEMBER(banksel_4_w);
	103	DECLARE_WRITE8_MEMBER(banksel_5_w);
	104	DECLARE_WRITE8_MEMBER(banksel_1_1_w);
	105	DECLARE_WRITE8_MEMBER(banksel_2_1_w);
	106	DECLARE_WRITE8_MEMBER(banksel_3_1_w);
	107	DECLARE_WRITE8_MEMBER(banksel_4_1_w);
	108	DECLARE_WRITE8_MEMBER(banksel_5_1_w);
	109	DECLARE_WRITE8_MEMBER(banksel_1_2_w);
	110	DECLARE_WRITE8_MEMBER(banksel_2_2_w);
	111	DECLARE_WRITE8_MEMBER(banksel_3_2_w);
	112	DECLARE_WRITE8_MEMBER(banksel_4_2_w);
	113	DECLARE_WRITE8_MEMBER(banksel_5_2_w);
	114	DECLARE_WRITE8_MEMBER(geimulti_bank_w);
	115	DECLARE_READ8_MEMBER(banksel_1_r);
	116	DECLARE_READ8_MEMBER(banksel_2_r);
	117	DECLARE_READ8_MEMBER(banksel_3_r);
	118	DECLARE_READ8_MEMBER(banksel_4_r);
	119	DECLARE_READ8_MEMBER(banksel_5_r);
	120	DECLARE_READ8_MEMBER(signature_r);
	121	DECLARE_WRITE8_MEMBER(signature_w);
	122	DECLARE_WRITE8_MEMBER(signature2_w);
95	123	};
96	124
97	125
98		static WRITE8_HANDLER( gei_drawctrl_w )
	126	WRITE8_MEMBER(gei_state::gei_drawctrl_w)
99	127	{
100		gei_state *state = space->machine().driver_data<gei_state>();
101		state->m_drawctrl[offset] = data;
	128	m_drawctrl[offset] = data;
102	129	if (offset == 2)
103	130	{
104	131	int i;
105	132	for (i = 0; i < 8; i++)
106		if (BIT(state->m_drawctrl[1],i)) state->m_color[i] = state->m_drawctrl[0] & 7;
	133	if (BIT(m_drawctrl[1],i)) m_color[i] = m_drawctrl[0] & 7;
107	134	}
108	135	}
109	136
110		static WRITE8_HANDLER( gei_bitmap_w )
	137	WRITE8_MEMBER(gei_state::gei_bitmap_w)
111	138	{
112		gei_state *state = space->machine().driver_data<gei_state>();
113	139	int sx,sy;
114	140	int i;
115	141
116		state->m_yadd = (offset==state->m_prevoffset) ? (state->m_yadd+1):0;
117		state->m_prevoffset = offset;
	142	m_yadd = (offset==m_prevoffset) ? (m_yadd+1):0;
	143	m_prevoffset = offset;
118	144
119	145	sx = 8 * (offset % 64);
120	146	sy = offset / 64;
121		sy = (sy + state->m_yadd) & 0xff;
	147	sy = (sy + m_yadd) & 0xff;
122	148
123	149
124	150	for (i = 0; i < 8; i++)
125		state->m_bitmap.pix16(sy, sx+i) = state->m_color[8-i-1];
	151	m_bitmap.pix16(sy, sx+i) = m_color[8-i-1];
126	152	}
127	153
128	154	static PALETTE_INIT(gei)
r14845	r14846
226	252	state->m_nmi_mask = data & 0x40;
227	253	}
228	254
229		static READ8_HANDLER( catchall )
	255	READ8_MEMBER(gei_state::catchall)
230	256	{
231		int pc = cpu_get_pc(&space->device());
	257	int pc = cpu_get_pc(&space.device());
232	258
233	259	if (pc != 0x3c74 && pc != 0x0364 && pc != 0x036d)   /* weed out spurious blit reads */
234	260	logerror("%04x: unmapped memory read from %04x\n",pc,offset);
r14845	r14846
241	267	return 4;
242	268	}
243	269
244		static WRITE8_HANDLER( banksel_main_w )
	270	WRITE8_MEMBER(gei_state::banksel_main_w)
245	271	{
246		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x8000);
	272	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x8000);
247	273	}
248		static WRITE8_HANDLER( banksel_1_w )
	274	WRITE8_MEMBER(gei_state::banksel_1_w)
249	275	{
250		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x10000);
	276	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x10000);
251	277	}
252		static WRITE8_HANDLER( banksel_2_w )
	278	WRITE8_MEMBER(gei_state::banksel_2_w)
253	279	{
254		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x18000);
	280	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x18000);
255	281	}
256		static WRITE8_HANDLER( banksel_3_w )
	282	WRITE8_MEMBER(gei_state::banksel_3_w)
257	283	{
258		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x20000);
	284	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x20000);
259	285	}
260		static WRITE8_HANDLER( banksel_4_w )
	286	WRITE8_MEMBER(gei_state::banksel_4_w)
261	287	{
262		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x28000);
	288	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x28000);
263	289	}
264		static WRITE8_HANDLER( banksel_5_w )
	290	WRITE8_MEMBER(gei_state::banksel_5_w)
265	291	{
266		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x30000);
	292	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x30000);
267	293	}
268	294
269		static WRITE8_HANDLER( banksel_1_1_w )
	295	WRITE8_MEMBER(gei_state::banksel_1_1_w)
270	296	{
271		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x10000);
	297	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x10000);
272	298	}
273		static WRITE8_HANDLER( banksel_2_1_w )
	299	WRITE8_MEMBER(gei_state::banksel_2_1_w)
274	300	{
275		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x14000);
	301	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x14000);
276	302	}
277		static WRITE8_HANDLER( banksel_3_1_w )
	303	WRITE8_MEMBER(gei_state::banksel_3_1_w)
278	304	{
279		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x18000);
	305	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x18000);
280	306	}
281		static WRITE8_HANDLER( banksel_4_1_w )
	307	WRITE8_MEMBER(gei_state::banksel_4_1_w)
282	308	{
283		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x1c000);
	309	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x1c000);
284	310	}
285		static WRITE8_HANDLER( banksel_5_1_w )
	311	WRITE8_MEMBER(gei_state::banksel_5_1_w)
286	312	{
287		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x20000);
	313	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x20000);
288	314	}
289		static WRITE8_HANDLER( banksel_1_2_w )
	315	WRITE8_MEMBER(gei_state::banksel_1_2_w)
290	316	{
291		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x12000);
	317	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x12000);
292	318	}
293		static WRITE8_HANDLER( banksel_2_2_w )
	319	WRITE8_MEMBER(gei_state::banksel_2_2_w)
294	320	{
295		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x16000);
	321	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x16000);
296	322	}
297		static WRITE8_HANDLER( banksel_3_2_w )
	323	WRITE8_MEMBER(gei_state::banksel_3_2_w)
298	324	{
299		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x1a000);
	325	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x1a000);
300	326	}
301		static WRITE8_HANDLER( banksel_4_2_w )
	327	WRITE8_MEMBER(gei_state::banksel_4_2_w)
302	328	{
303		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x1e000);
	329	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x1e000);
304	330	}
305		static WRITE8_HANDLER( banksel_5_2_w )
	331	WRITE8_MEMBER(gei_state::banksel_5_2_w)
306	332	{
307		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x22000);
	333	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x22000);
308	334	}
309	335
310		static WRITE8_HANDLER(geimulti_bank_w)
	336	WRITE8_MEMBER(gei_state::geimulti_bank_w)
311	337	{
312	338	int bank = -1;
313	339
r14845	r14846
332	358	}
333	359
334	360	if (bank != -1)
335		memory_set_bankptr(space->machine(), "bank1", space->machine().region("bank")->base() + bank*0x8000);
	361	memory_set_bankptr(machine(), "bank1", machine().region("bank")->base() + bank*0x8000);
336	362	}
337	363
338		static READ8_HANDLER(banksel_1_r)
	364	READ8_MEMBER(gei_state::banksel_1_r)
339	365	{
340		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x10000);
	366	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x10000);
341	367	return 0x03;
342	368	};
343	369
344		static READ8_HANDLER(banksel_2_r)
	370	READ8_MEMBER(gei_state::banksel_2_r)
345	371	{
346		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x18000);
	372	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x18000);
347	373	return 0x03;
348	374	}
349	375
350		static READ8_HANDLER(banksel_3_r)
	376	READ8_MEMBER(gei_state::banksel_3_r)
351	377	{
352		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x20000);
	378	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x20000);
353	379	return 0x03;
354	380	}
355	381
356		static READ8_HANDLER(banksel_4_r)
	382	READ8_MEMBER(gei_state::banksel_4_r)
357	383	{
358		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x28000);
	384	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x28000);
359	385	return 0x03;
360	386	}
361	387
362		static READ8_HANDLER(banksel_5_r)
	388	READ8_MEMBER(gei_state::banksel_5_r)
363	389	{
364		memory_set_bankptr(space->machine(), "bank1",space->machine().region("maincpu")->base() + 0x30000);
	390	memory_set_bankptr(machine(), "bank1",machine().region("maincpu")->base() + 0x30000);
365	391	return 0x03;
366	392	}
367	393
368	394	/* This signature is used to validate the ROMs in sportauth. Simple protection check? */
369	395
370		static READ8_HANDLER( signature_r )
	396	READ8_MEMBER(gei_state::signature_r)
371	397	{
372		gei_state *state = space->machine().driver_data<gei_state>();
373		return state->m_signature_answer;
	398	return m_signature_answer;
374	399	}
375	400
376		static WRITE8_HANDLER( signature_w )
	401	WRITE8_MEMBER(gei_state::signature_w)
377	402	{
378		gei_state *state = space->machine().driver_data<gei_state>();
379		if (data == 0) state->m_signature_pos = 0;
	403	if (data == 0) m_signature_pos = 0;
380	404	else
381	405	{
382	406	static const UINT8 signature[8] = { 0xff, 0x01, 0xfd, 0x05, 0xf5, 0x15, 0xd5, 0x55 };
383	407
384		state->m_signature_answer = signature[state->m_signature_pos++];
	408	m_signature_answer = signature[m_signature_pos++];
385	409
386		state->m_signature_pos &= 7;   /* safety; shouldn't happen */
	410	m_signature_pos &= 7;   /* safety; shouldn't happen */
387	411	}
388	412	}
389	413
390		static WRITE8_HANDLER( signature2_w )
	414	WRITE8_MEMBER(gei_state::signature2_w)
391	415	{
392		gei_state *state = space->machine().driver_data<gei_state>();
393		if (data == 0) state->m_signature_pos = 0;
	416	if (data == 0) m_signature_pos = 0;
394	417	else
395	418	{
396	419	static const UINT8 signature[8] = { 0xff, 0x01, 0xf7, 0x11, 0xd7, 0x51, 0x57, 0x51 };
397	420
398		state->m_signature_answer = signature[state->m_signature_pos++];
	421	m_signature_answer = signature[m_signature_pos++];
399	422
400		state->m_signature_pos &= 7;   /* safety; shouldn't happen */
	423	m_signature_pos &= 7;   /* safety; shouldn't happen */
401	424	}
402	425	}
403	426
r14845	r14846
407	430	AM_RANGE(0x4000, 0x47ff) AM_RAM AM_SHARE("nvram")
408	431	AM_RANGE(0x4800, 0x4803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
409	432	AM_RANGE(0x5000, 0x5003) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
410		AM_RANGE(0x600f, 0x600f) AM_WRITE_LEGACY(banksel_5_1_w)
411		AM_RANGE(0x6017, 0x6017) AM_WRITE_LEGACY(banksel_4_1_w)
412		AM_RANGE(0x601b, 0x601b) AM_WRITE_LEGACY(banksel_3_1_w)
413		AM_RANGE(0x601d, 0x601d) AM_WRITE_LEGACY(banksel_2_1_w)
414		AM_RANGE(0x601e, 0x601e) AM_WRITE_LEGACY(banksel_1_1_w)
415		AM_RANGE(0x608f, 0x608f) AM_WRITE_LEGACY(banksel_5_2_w)
416		AM_RANGE(0x6097, 0x6097) AM_WRITE_LEGACY(banksel_4_2_w)
417		AM_RANGE(0x609b, 0x609b) AM_WRITE_LEGACY(banksel_3_2_w)
418		AM_RANGE(0x609d, 0x609d) AM_WRITE_LEGACY(banksel_2_2_w)
419		AM_RANGE(0x609e, 0x609e) AM_WRITE_LEGACY(banksel_1_2_w)
420		AM_RANGE(0x8000, 0x8002) AM_WRITE_LEGACY(gei_drawctrl_w)
	433	AM_RANGE(0x600f, 0x600f) AM_WRITE(banksel_5_1_w)
	434	AM_RANGE(0x6017, 0x6017) AM_WRITE(banksel_4_1_w)
	435	AM_RANGE(0x601b, 0x601b) AM_WRITE(banksel_3_1_w)
	436	AM_RANGE(0x601d, 0x601d) AM_WRITE(banksel_2_1_w)
	437	AM_RANGE(0x601e, 0x601e) AM_WRITE(banksel_1_1_w)
	438	AM_RANGE(0x608f, 0x608f) AM_WRITE(banksel_5_2_w)
	439	AM_RANGE(0x6097, 0x6097) AM_WRITE(banksel_4_2_w)
	440	AM_RANGE(0x609b, 0x609b) AM_WRITE(banksel_3_2_w)
	441	AM_RANGE(0x609d, 0x609d) AM_WRITE(banksel_2_2_w)
	442	AM_RANGE(0x609e, 0x609e) AM_WRITE(banksel_1_2_w)
	443	AM_RANGE(0x8000, 0x8002) AM_WRITE(gei_drawctrl_w)
421	444	AM_RANGE(0x8000, 0x9fff) AM_ROM /* space for diagnostic ROM? */
422	445	AM_RANGE(0xa000, 0xbfff) AM_ROM
423		AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE_LEGACY(gei_bitmap_w)
	446	AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE(gei_bitmap_w)
424	447	ADDRESS_MAP_END
425	448
426	449	static ADDRESS_MAP_START( gselect_map, AS_PROGRAM, 8, gei_state )
427	450	AM_RANGE(0x0000, 0x1fff) AM_ROM
428	451	AM_RANGE(0x2000, 0x3fff) AM_ROMBANK("bank1")
429	452	AM_RANGE(0x4000, 0x40ff) AM_RAM AM_SHARE("nvram")
430		AM_RANGE(0x4400, 0x4400) AM_WRITE_LEGACY(banksel_1_1_w)
431		AM_RANGE(0x4401, 0x4401) AM_WRITE_LEGACY(banksel_1_2_w)
432		AM_RANGE(0x4402, 0x4402) AM_WRITE_LEGACY(banksel_2_1_w)
433		AM_RANGE(0x4403, 0x4403) AM_WRITE_LEGACY(banksel_2_2_w)
	453	AM_RANGE(0x4400, 0x4400) AM_WRITE(banksel_1_1_w)
	454	AM_RANGE(0x4401, 0x4401) AM_WRITE(banksel_1_2_w)
	455	AM_RANGE(0x4402, 0x4402) AM_WRITE(banksel_2_1_w)
	456	AM_RANGE(0x4403, 0x4403) AM_WRITE(banksel_2_2_w)
434	457	AM_RANGE(0x4800, 0x4803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
435	458	AM_RANGE(0x5000, 0x5003) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
436		AM_RANGE(0x8000, 0x8002) AM_WRITE_LEGACY(gei_drawctrl_w)
437		AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE_LEGACY(gei_bitmap_w)
	459	AM_RANGE(0x8000, 0x8002) AM_WRITE(gei_drawctrl_w)
	460	AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE(gei_bitmap_w)
438	461	ADDRESS_MAP_END
439	462
440	463	// TODO: where are mapped the lower 0x2000 bytes of the banks?
r14845	r14846
444	467	AM_RANGE(0x4000, 0x47ff) AM_RAM AM_SHARE("nvram")
445	468	AM_RANGE(0x4800, 0x4803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
446	469	AM_RANGE(0x5000, 0x5003) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
447		AM_RANGE(0x606f, 0x606f) AM_WRITE_LEGACY(banksel_5_1_w)
448		AM_RANGE(0x6077, 0x6077) AM_WRITE_LEGACY(banksel_4_1_w)
449		AM_RANGE(0x607b, 0x607b) AM_WRITE_LEGACY(banksel_3_1_w)
450		AM_RANGE(0x607d, 0x607d) AM_WRITE_LEGACY(banksel_2_1_w)
451		AM_RANGE(0x607e, 0x607e) AM_WRITE_LEGACY(banksel_1_1_w)
452		AM_RANGE(0x8000, 0x8002) AM_WRITE_LEGACY(gei_drawctrl_w)
	470	AM_RANGE(0x606f, 0x606f) AM_WRITE(banksel_5_1_w)
	471	AM_RANGE(0x6077, 0x6077) AM_WRITE(banksel_4_1_w)
	472	AM_RANGE(0x607b, 0x607b) AM_WRITE(banksel_3_1_w)
	473	AM_RANGE(0x607d, 0x607d) AM_WRITE(banksel_2_1_w)
	474	AM_RANGE(0x607e, 0x607e) AM_WRITE(banksel_1_1_w)
	475	AM_RANGE(0x8000, 0x8002) AM_WRITE(gei_drawctrl_w)
453	476	AM_RANGE(0x8000, 0xbfff) AM_ROM
454		AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE_LEGACY(gei_bitmap_w)
	477	AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE(gei_bitmap_w)
455	478	ADDRESS_MAP_END
456	479
457	480	static ADDRESS_MAP_START( gepoker_map, AS_PROGRAM, 8, gei_state )
r14845	r14846
460	483	AM_RANGE(0x4000, 0x47ff) AM_RAM AM_SHARE("nvram")
461	484	AM_RANGE(0x4800, 0x4803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
462	485	AM_RANGE(0x5000, 0x5003) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
463		AM_RANGE(0x60ef, 0x60ef) AM_WRITE_LEGACY(banksel_3_1_w)
464		AM_RANGE(0x60f7, 0x60f7) AM_WRITE_LEGACY(banksel_2_2_w)
465		AM_RANGE(0x60fb, 0x60fb) AM_WRITE_LEGACY(banksel_2_1_w)
466		AM_RANGE(0x60fd, 0x60fd) AM_WRITE_LEGACY(banksel_1_2_w)
467		AM_RANGE(0x60fe, 0x60fe) AM_WRITE_LEGACY(banksel_1_1_w)
468		AM_RANGE(0x8000, 0x8002) AM_WRITE_LEGACY(gei_drawctrl_w)
	486	AM_RANGE(0x60ef, 0x60ef) AM_WRITE(banksel_3_1_w)
	487	AM_RANGE(0x60f7, 0x60f7) AM_WRITE(banksel_2_2_w)
	488	AM_RANGE(0x60fb, 0x60fb) AM_WRITE(banksel_2_1_w)
	489	AM_RANGE(0x60fd, 0x60fd) AM_WRITE(banksel_1_2_w)
	490	AM_RANGE(0x60fe, 0x60fe) AM_WRITE(banksel_1_1_w)
	491	AM_RANGE(0x8000, 0x8002) AM_WRITE(gei_drawctrl_w)
469	492	AM_RANGE(0x8000, 0xbfff) AM_ROM /* space for diagnostic ROM? */
470	493	AM_RANGE(0xe000, 0xffff) AM_ROM
471		AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE_LEGACY(gei_bitmap_w)
	494	AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE(gei_bitmap_w)
472	495	ADDRESS_MAP_END
473	496
474	497	static ADDRESS_MAP_START( amuse1_map, AS_PROGRAM, 8, gei_state )
475	498	AM_RANGE(0x0000, 0x1fff) AM_ROM
476	499	AM_RANGE(0x2000, 0x3fff) AM_ROMBANK("bank1")
477	500	AM_RANGE(0x4000, 0x43ff) AM_RAM AM_SHARE("nvram")
478		AM_RANGE(0x4400, 0x4400) AM_WRITE_LEGACY(banksel_1_1_w)
479		AM_RANGE(0x4401, 0x4401) AM_WRITE_LEGACY(banksel_2_1_w)
480		AM_RANGE(0x4402, 0x4402) AM_WRITE_LEGACY(banksel_3_1_w)
481		AM_RANGE(0x4403, 0x4403) AM_WRITE_LEGACY(banksel_4_1_w)
	501	AM_RANGE(0x4400, 0x4400) AM_WRITE(banksel_1_1_w)
	502	AM_RANGE(0x4401, 0x4401) AM_WRITE(banksel_2_1_w)
	503	AM_RANGE(0x4402, 0x4402) AM_WRITE(banksel_3_1_w)
	504	AM_RANGE(0x4403, 0x4403) AM_WRITE(banksel_4_1_w)
482	505	AM_RANGE(0x4800, 0x4803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
483	506	AM_RANGE(0x5000, 0x5003) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
484	507	AM_RANGE(0x5800, 0x5fff) AM_ROM
485		AM_RANGE(0x8000, 0x8002) AM_WRITE_LEGACY(gei_drawctrl_w)
	508	AM_RANGE(0x8000, 0x8002) AM_WRITE(gei_drawctrl_w)
486	509	AM_RANGE(0x8000, 0xbfff) AM_ROM /* space for diagnostic ROM? */
487	510	AM_RANGE(0xe000, 0xffff) AM_ROM
488		AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE_LEGACY(gei_bitmap_w)
	511	AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE(gei_bitmap_w)
489	512	ADDRESS_MAP_END
490	513
491	514	static ADDRESS_MAP_START( findout_map, AS_PROGRAM, 8, gei_state )
r14845	r14846
494	517	AM_RANGE(0x4800, 0x4803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r,ppi8255_w)
495	518	AM_RANGE(0x5000, 0x5003) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r,ppi8255_w)
496	519	/* banked ROMs are enabled by low 6 bits of the address */
497		AM_RANGE(0x601f, 0x601f) AM_WRITE_LEGACY(banksel_main_w)
498		AM_RANGE(0x602f, 0x602f) AM_WRITE_LEGACY(banksel_5_w)
499		AM_RANGE(0x6037, 0x6037) AM_WRITE_LEGACY(banksel_4_w)
500		AM_RANGE(0x603b, 0x603b) AM_WRITE_LEGACY(banksel_3_w)
501		AM_RANGE(0x603d, 0x603d) AM_WRITE_LEGACY(banksel_2_w)
502		AM_RANGE(0x603e, 0x603e) AM_WRITE_LEGACY(banksel_1_w)
503		AM_RANGE(0x6200, 0x6200) AM_WRITE_LEGACY(signature_w)
504		AM_RANGE(0x6400, 0x6400) AM_READ_LEGACY(signature_r)
	520	AM_RANGE(0x601f, 0x601f) AM_WRITE(banksel_main_w)
	521	AM_RANGE(0x602f, 0x602f) AM_WRITE(banksel_5_w)
	522	AM_RANGE(0x6037, 0x6037) AM_WRITE(banksel_4_w)
	523	AM_RANGE(0x603b, 0x603b) AM_WRITE(banksel_3_w)
	524	AM_RANGE(0x603d, 0x603d) AM_WRITE(banksel_2_w)
	525	AM_RANGE(0x603e, 0x603e) AM_WRITE(banksel_1_w)
	526	AM_RANGE(0x6200, 0x6200) AM_WRITE(signature_w)
	527	AM_RANGE(0x6400, 0x6400) AM_READ(signature_r)
505	528	AM_RANGE(0x7800, 0x7fff) AM_ROM /*space for diagnostic ROM?*/
506	529	AM_RANGE(0x8000, 0xffff) AM_ROMBANK("bank1")
507		AM_RANGE(0x8000, 0x8002) AM_WRITE_LEGACY(gei_drawctrl_w)
508		AM_RANGE(0xc000, 0xffff) AM_WRITE_LEGACY(gei_bitmap_w)
509		AM_RANGE(0x0000, 0xffff) AM_READ_LEGACY(catchall)
	530	AM_RANGE(0x8000, 0x8002) AM_WRITE(gei_drawctrl_w)
	531	AM_RANGE(0xc000, 0xffff) AM_WRITE(gei_bitmap_w)
	532	AM_RANGE(0x0000, 0xffff) AM_READ(catchall)
510	533	ADDRESS_MAP_END
511	534
512	535	static ADDRESS_MAP_START( quizvid_map, AS_PROGRAM, 8, gei_state )
r14845	r14846
515	538	AM_RANGE(0x4800, 0x4803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r,ppi8255_w)
516	539	AM_RANGE(0x5000, 0x5003) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r,ppi8255_w)
517	540	/* banked ROMs are enabled by low 6 bits of the address */
518		AM_RANGE(0x602f, 0x602f) AM_READ_LEGACY(banksel_5_r)
519		AM_RANGE(0x6037, 0x6037) AM_READ_LEGACY(banksel_4_r)
520		AM_RANGE(0x603b, 0x603b) AM_READ_LEGACY(banksel_3_r)
521		AM_RANGE(0x603d, 0x603d) AM_READ_LEGACY(banksel_2_r)
522		AM_RANGE(0x603e, 0x603e) AM_READ_LEGACY(banksel_1_r)
	541	AM_RANGE(0x602f, 0x602f) AM_READ(banksel_5_r)
	542	AM_RANGE(0x6037, 0x6037) AM_READ(banksel_4_r)
	543	AM_RANGE(0x603b, 0x603b) AM_READ(banksel_3_r)
	544	AM_RANGE(0x603d, 0x603d) AM_READ(banksel_2_r)
	545	AM_RANGE(0x603e, 0x603e) AM_READ(banksel_1_r)
523	546	AM_RANGE(0x7800, 0x7fff) AM_ROM /*space for diagnostic ROM?*/
524	547	AM_RANGE(0x8000, 0xffff) AM_ROMBANK("bank1")
525		AM_RANGE(0x8000, 0x8002) AM_WRITE_LEGACY(gei_drawctrl_w)
526		AM_RANGE(0xc000, 0xffff) AM_WRITE_LEGACY(gei_bitmap_w)
527		AM_RANGE(0x0000, 0xffff) AM_READ_LEGACY(catchall)
	548	AM_RANGE(0x8000, 0x8002) AM_WRITE(gei_drawctrl_w)
	549	AM_RANGE(0xc000, 0xffff) AM_WRITE(gei_bitmap_w)
	550	AM_RANGE(0x0000, 0xffff) AM_READ(catchall)
528	551	ADDRESS_MAP_END
529	552
530	553	static ADDRESS_MAP_START( suprpokr_map, AS_PROGRAM, 8, gei_state )
r14845	r14846
532	555	AM_RANGE(0x4000, 0x47ff) AM_RAM AM_SHARE("nvram")
533	556	AM_RANGE(0x4800, 0x4803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
534	557	AM_RANGE(0x5000, 0x5003) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
535		AM_RANGE(0x6200, 0x6200) AM_WRITE_LEGACY(signature2_w)
536		AM_RANGE(0x6400, 0x6400) AM_READ_LEGACY(signature_r)
537		AM_RANGE(0x8000, 0x8002) AM_WRITE_LEGACY(gei_drawctrl_w)
538		AM_RANGE(0xc000, 0xffff) AM_WRITE_LEGACY(gei_bitmap_w)
	558	AM_RANGE(0x6200, 0x6200) AM_WRITE(signature2_w)
	559	AM_RANGE(0x6400, 0x6400) AM_READ(signature_r)
	560	AM_RANGE(0x8000, 0x8002) AM_WRITE(gei_drawctrl_w)
	561	AM_RANGE(0xc000, 0xffff) AM_WRITE(gei_bitmap_w)
539	562	AM_RANGE(0x8000, 0xffff) AM_ROM
540	563	ADDRESS_MAP_END
541	564
r14845	r14846
545	568	AM_RANGE(0x4800, 0x4803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
546	569	AM_RANGE(0x5000, 0x5003) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
547	570	AM_RANGE(0x5800, 0x5fff) AM_ROM
548		AM_RANGE(0x5a00, 0x5cff) AM_WRITE_LEGACY(geimulti_bank_w)
	571	AM_RANGE(0x5a00, 0x5cff) AM_WRITE(geimulti_bank_w)
549	572	AM_RANGE(0x6000, 0x7fff) AM_ROM
550		AM_RANGE(0x8000, 0x8002) AM_WRITE_LEGACY(gei_drawctrl_w)
	573	AM_RANGE(0x8000, 0x8002) AM_WRITE(gei_drawctrl_w)
551	574	AM_RANGE(0x8000, 0xffff) AM_ROMBANK("bank1")
552		AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE_LEGACY(gei_bitmap_w)
	575	AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE(gei_bitmap_w)
553	576	ADDRESS_MAP_END
554	577
555	578	static ADDRESS_MAP_START( sprtauth_map, AS_PROGRAM, 8, gei_state )
r14845	r14846
557	580	AM_RANGE(0x4000, 0x47ff) AM_RAM AM_SHARE("nvram")
558	581	AM_RANGE(0x4800, 0x4803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
559	582	AM_RANGE(0x5000, 0x5003) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
560		AM_RANGE(0x5600, 0x5600) AM_READ_LEGACY(signature_r)
561		AM_RANGE(0x5800, 0x5800) AM_WRITE_LEGACY(signature_w)
562		AM_RANGE(0x5a00, 0x5cff) AM_WRITE_LEGACY(geimulti_bank_w)
	583	AM_RANGE(0x5600, 0x5600) AM_READ(signature_r)
	584	AM_RANGE(0x5800, 0x5800) AM_WRITE(signature_w)
	585	AM_RANGE(0x5a00, 0x5cff) AM_WRITE(geimulti_bank_w)
563	586	AM_RANGE(0x6000, 0x7fff) AM_ROM
564		AM_RANGE(0x8000, 0x8002) AM_WRITE_LEGACY(gei_drawctrl_w)
	587	AM_RANGE(0x8000, 0x8002) AM_WRITE(gei_drawctrl_w)
565	588	AM_RANGE(0x8000, 0xffff) AM_ROMBANK("bank1")
566		AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE_LEGACY(gei_bitmap_w)
	589	AM_RANGE(0xc000, 0xffff) AM_RAM_WRITE(gei_bitmap_w)
567	590	ADDRESS_MAP_END
568	591
569	592	static INPUT_PORTS_START(reelfun_standard)

src/mame/drivers/looping.c

r14845	r14846
113	113	UINT8      m_sound[8];
114	114
115	115	int      m_last;
	116	DECLARE_WRITE8_MEMBER(flip_screen_x_w);
	117	DECLARE_WRITE8_MEMBER(flip_screen_y_w);
	118	DECLARE_WRITE8_MEMBER(looping_videoram_w);
	119	DECLARE_WRITE8_MEMBER(looping_colorram_w);
	120	DECLARE_WRITE8_MEMBER(level2_irq_set);
	121	DECLARE_WRITE8_MEMBER(main_irq_ack_w);
	122	DECLARE_WRITE8_MEMBER(looping_souint_clr);
	123	DECLARE_WRITE8_MEMBER(looping_soundlatch_w);
	124	DECLARE_WRITE8_MEMBER(ballon_enable_w);
	125	DECLARE_WRITE8_MEMBER(out_0_w);
	126	DECLARE_WRITE8_MEMBER(out_2_w);
	127	DECLARE_READ8_MEMBER(adc_r);
	128	DECLARE_WRITE8_MEMBER(adc_w);
	129	DECLARE_WRITE8_MEMBER(plr2_w);
	130	DECLARE_READ8_MEMBER(cop_io_r);
	131	DECLARE_WRITE8_MEMBER(cop_io_w);
	132	DECLARE_READ8_MEMBER(protection_r);
116	133	};
117	134
118	135
r14845	r14846
195	212	*
196	213	*************************************/
197	214
198		static WRITE8_HANDLER( flip_screen_x_w )
	215	WRITE8_MEMBER(looping_state::flip_screen_x_w)
199	216	{
200		looping_state *state = space->machine().driver_data<looping_state>();
201		flip_screen_x_set(space->machine(), ~data & 0x01);
202		state->m_bg_tilemap->set_scrollx(0, flip_screen_get(space->machine()) ? 128 : 0);
	217	flip_screen_x_set(machine(), ~data & 0x01);
	218	m_bg_tilemap->set_scrollx(0, flip_screen_get(machine()) ? 128 : 0);
203	219	}
204	220
205	221
206		static WRITE8_HANDLER( flip_screen_y_w )
	222	WRITE8_MEMBER(looping_state::flip_screen_y_w)
207	223	{
208		looping_state *state = space->machine().driver_data<looping_state>();
209		flip_screen_y_set(space->machine(), ~data & 0x01);
210		state->m_bg_tilemap->set_scrollx(0, flip_screen_get(space->machine()) ? 128 : 0);
	224	flip_screen_y_set(machine(), ~data & 0x01);
	225	m_bg_tilemap->set_scrollx(0, flip_screen_get(machine()) ? 128 : 0);
211	226	}
212	227
213	228
214		static WRITE8_HANDLER( looping_videoram_w )
	229	WRITE8_MEMBER(looping_state::looping_videoram_w)
215	230	{
216		looping_state *state = space->machine().driver_data<looping_state>();
217		state->m_videoram[offset] = data;
218		state->m_bg_tilemap->mark_tile_dirty(offset);
	231	m_videoram[offset] = data;
	232	m_bg_tilemap->mark_tile_dirty(offset);
219	233	}
220	234
221	235
222		static WRITE8_HANDLER( looping_colorram_w )
	236	WRITE8_MEMBER(looping_state::looping_colorram_w)
223	237	{
224		looping_state *state = space->machine().driver_data<looping_state>();
225	238	int i;
226	239
227		state->m_colorram[offset] = data;
	240	m_colorram[offset] = data;
228	241
229	242	/* odd bytes are column color attribute */
230	243	if (offset & 1)
r14845	r14846
232	245	/* mark the whole column dirty */
233	246	offs_t offs = (offset/2);
234	247	for (i = 0; i < 0x20; i++)
235		state->m_bg_tilemap->mark_tile_dirty(i * 0x20 + offs);
	248	m_bg_tilemap->mark_tile_dirty(i * 0x20 + offs);
236	249	}
237	250
238	251	/* even bytes are column scroll */
239	252	else
240		state->m_bg_tilemap->set_scrolly(offset/2, data);
	253	m_bg_tilemap->set_scrolly(offset/2, data);
241	254	}
242	255
243	256
r14845	r14846
316	329	}
317	330
318	331
319		static WRITE8_HANDLER( level2_irq_set )
	332	WRITE8_MEMBER(looping_state::level2_irq_set)
320	333	{
321	334	if (!(data & 1))
322		cputag_set_input_line_and_vector(space->machine(), "maincpu", 0, ASSERT_LINE, 4);
	335	cputag_set_input_line_and_vector(machine(), "maincpu", 0, ASSERT_LINE, 4);
323	336	}
324	337
325	338
326		static WRITE8_HANDLER( main_irq_ack_w )
	339	WRITE8_MEMBER(looping_state::main_irq_ack_w)
327	340	{
328	341	if (data == 0)
329		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
	342	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
330	343	}
331	344
332	345
333		static WRITE8_HANDLER( looping_souint_clr )
	346	WRITE8_MEMBER(looping_state::looping_souint_clr)
334	347	{
335	348	if (data == 0)
336		cputag_set_input_line(space->machine(), "audiocpu", 0, CLEAR_LINE);
	349	cputag_set_input_line(machine(), "audiocpu", 0, CLEAR_LINE);
337	350	}
338	351
339	352
r14845	r14846
343	356	}
344	357
345	358
346		static WRITE8_HANDLER( looping_soundlatch_w )
	359	WRITE8_MEMBER(looping_state::looping_soundlatch_w)
347	360	{
348	361	soundlatch_w(space, offset, data);
349		cputag_set_input_line_and_vector(space->machine(), "audiocpu", 0, ASSERT_LINE, 4);
	362	cputag_set_input_line_and_vector(machine(), "audiocpu", 0, ASSERT_LINE, 4);
350	363	}
351	364
352	365
r14845	r14846
402	415	}
403	416
404	417
405		static WRITE8_HANDLER( ballon_enable_w )
	418	WRITE8_MEMBER(looping_state::ballon_enable_w)
406	419	{
407		looping_state *state = space->machine().driver_data<looping_state>();
408		if (state->m_last != data)
	420	if (m_last != data)
409	421	mame_printf_debug("ballon_enable_w = %d\n", data);
410		state->m_last = data;
	422	m_last = data;
411	423	}
412	424
413	425
r14845	r14846
418	430	*
419	431	*************************************/
420	432
421		static WRITE8_HANDLER( out_0_w ) { mame_printf_debug("out0 = %02X\n", data); }
422		static WRITE8_HANDLER( out_2_w ) { mame_printf_debug("out2 = %02X\n", data); }
	433	WRITE8_MEMBER(looping_state::out_0_w){ mame_printf_debug("out0 = %02X\n", data); }
	434	WRITE8_MEMBER(looping_state::out_2_w){ mame_printf_debug("out2 = %02X\n", data); }
423	435
424		static READ8_HANDLER( adc_r )  { mame_printf_debug("%04X:ADC read\n", cpu_get_pc(&space->device())); return 0xff; }
425		static WRITE8_HANDLER( adc_w ) { mame_printf_debug("%04X:ADC write = %02X\n", cpu_get_pc(&space->device()), data); }
	436	READ8_MEMBER(looping_state::adc_r){ mame_printf_debug("%04X:ADC read\n", cpu_get_pc(&space.device())); return 0xff; }
	437	WRITE8_MEMBER(looping_state::adc_w){ mame_printf_debug("%04X:ADC write = %02X\n", cpu_get_pc(&space.device()), data); }
426	438
427		static WRITE8_HANDLER( plr2_w )
	439	WRITE8_MEMBER(looping_state::plr2_w)
428	440	{
429	441	/* set to 1 after IDLE, cleared to 0 during processing */
430	442	/* is this an LED on the PCB? */
r14845	r14846
438	450	*
439	451	*************************************/
440	452
441		static READ8_HANDLER( cop_io_r )
	453	READ8_MEMBER(looping_state::cop_io_r)
442	454	{
443		//looping_state *state = space->machine().driver_data<looping_state>();
444		// if (offset == 1) return space->machine().rand() & 0x01;
445		return 1; // state->m_cop_io[offset];
	455	// if (offset == 1) return machine().rand() & 0x01;
	456	return 1; // m_cop_io[offset];
446	457	}
447	458
448		static WRITE8_HANDLER( cop_io_w )
	459	WRITE8_MEMBER(looping_state::cop_io_w)
449	460	{
450		looping_state *state = space->machine().driver_data<looping_state>();
451		state->m_cop_io[offset] = data;
	461	m_cop_io[offset] = data;
452	462	if (offset == 0) logerror("%02x  ",data);
453	463	}
454	464
455		static READ8_HANDLER( protection_r )
	465	READ8_MEMBER(looping_state::protection_r)
456	466	{
457		looping_state *state = space->machine().driver_data<looping_state>();
458	467	//        The code reads ($7002) ($7004) alternately
459	468	//        The result must change at least once every 10 reads
460	469	//        A read from ($34b0 + result) must == $01
r14845	r14846
473	482	//        cop write randomly fc (unfortunatly) but 61,67,b7,bf,db,e1,f3,fd,ff too and only these values
474	483
475	484	// missing something
476		if(state->m_cop_io[0] != 0xfc) return state->m_cop_io[0];
	485	if(m_cop_io[0] != 0xfc) return m_cop_io[0];
477	486	return 0xff;
478	487	}
479	488
r14845	r14846
487	496	static ADDRESS_MAP_START( looping_map, AS_PROGRAM, 8, looping_state )
488	497	AM_RANGE(0x0000, 0x7fff) AM_ROM
489	498
490		AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE_LEGACY(looping_videoram_w) AM_BASE(m_videoram)
	499	AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(looping_videoram_w) AM_BASE(m_videoram)
491	500
492		AM_RANGE(0x9800, 0x983f) AM_MIRROR(0x0700) AM_RAM_WRITE_LEGACY(looping_colorram_w) AM_BASE(m_colorram)
	501	AM_RANGE(0x9800, 0x983f) AM_MIRROR(0x0700) AM_RAM_WRITE(looping_colorram_w) AM_BASE(m_colorram)
493	502	AM_RANGE(0x9840, 0x987f) AM_MIRROR(0x0700) AM_RAM AM_BASE(m_spriteram)
494	503	AM_RANGE(0x9880, 0x98ff) AM_MIRROR(0x0700) AM_RAM
495	504
496		AM_RANGE(0xb001, 0xb001) AM_MIRROR(0x07f8) AM_WRITE_LEGACY(level2_irq_set)
497		AM_RANGE(0xb006, 0xb006) AM_MIRROR(0x07f8) AM_WRITE_LEGACY(flip_screen_x_w)
498		AM_RANGE(0xb007, 0xb007) AM_MIRROR(0x07f8) AM_WRITE_LEGACY(flip_screen_y_w)
	505	AM_RANGE(0xb001, 0xb001) AM_MIRROR(0x07f8) AM_WRITE(level2_irq_set)
	506	AM_RANGE(0xb006, 0xb006) AM_MIRROR(0x07f8) AM_WRITE(flip_screen_x_w)
	507	AM_RANGE(0xb007, 0xb007) AM_MIRROR(0x07f8) AM_WRITE(flip_screen_y_w)
499	508
500	509	AM_RANGE(0xe000, 0xefff) AM_RAM
501		AM_RANGE(0xf800, 0xf800) AM_MIRROR(0x03fc) AM_READ_PORT("P1") AM_WRITE_LEGACY(out_0_w)               /* /OUT0 */
502		AM_RANGE(0xf801, 0xf801) AM_MIRROR(0x03fc) AM_READ_PORT("P2") AM_WRITE_LEGACY(looping_soundlatch_w)   /* /OUT1 */
503		AM_RANGE(0xf802, 0xf802) AM_MIRROR(0x03fc) AM_READ_PORT("DSW") AM_WRITE_LEGACY(out_2_w)            /* /OUT2 */
504		AM_RANGE(0xf803, 0xf803) AM_MIRROR(0x03fc) AM_READWRITE_LEGACY(adc_r, adc_w)
	510	AM_RANGE(0xf800, 0xf800) AM_MIRROR(0x03fc) AM_READ_PORT("P1") AM_WRITE(out_0_w)               /* /OUT0 */
	511	AM_RANGE(0xf801, 0xf801) AM_MIRROR(0x03fc) AM_READ_PORT("P2") AM_WRITE(looping_soundlatch_w)   /* /OUT1 */
	512	AM_RANGE(0xf802, 0xf802) AM_MIRROR(0x03fc) AM_READ_PORT("DSW") AM_WRITE(out_2_w)            /* /OUT2 */
	513	AM_RANGE(0xf803, 0xf803) AM_MIRROR(0x03fc) AM_READWRITE(adc_r, adc_w)
505	514	ADDRESS_MAP_END
506	515
507	516	static ADDRESS_MAP_START( looping_io_map, AS_IO, 8, looping_state )
508	517	/* 400 = A16 */
509	518	/* 401 = A17 */
510	519	/* 402 = COLOR 9 */
511		AM_RANGE(0x403, 0x403) AM_WRITE_LEGACY(plr2_w)
	520	AM_RANGE(0x403, 0x403) AM_WRITE(plr2_w)
512	521	/* 404 = C0 */
513	522	/* 405 = C1 */
514		AM_RANGE(0x406, 0x406) AM_WRITE_LEGACY(main_irq_ack_w)
	523	AM_RANGE(0x406, 0x406) AM_WRITE(main_irq_ack_w)
515	524	AM_RANGE(0x407, 0x407) AM_WRITE_LEGACY(watchdog_reset_w)
516	525
517	526	AM_RANGE(0x10000, 0x10000) AM_NOP      /* external IDLE signal -- we can ignore it */
r14845	r14846
532	541	ADDRESS_MAP_END
533	542
534	543	static ADDRESS_MAP_START( looping_sound_io_map, AS_IO, 8, looping_state )
535		AM_RANGE(0x000, 0x000) AM_WRITE_LEGACY(looping_souint_clr)
	544	AM_RANGE(0x000, 0x000) AM_WRITE(looping_souint_clr)
536	545	AM_RANGE(0x001, 0x007) AM_DEVWRITE_LEGACY("dac", looping_sound_sw)
537	546	AM_RANGE(0x008, 0x008) AM_DEVWRITE_LEGACY("aysnd", ay_enable_w)
538	547	AM_RANGE(0x009, 0x009) AM_DEVWRITE_LEGACY("tms", speech_enable_w)
539		AM_RANGE(0x00a, 0x00a) AM_WRITE_LEGACY(ballon_enable_w)
	548	AM_RANGE(0x00a, 0x00a) AM_WRITE(ballon_enable_w)
540	549	AM_RANGE(0x00b, 0x00f) AM_NOP
541	550	ADDRESS_MAP_END
542	551
r14845	r14846
551	560	ADDRESS_MAP_END
552	561
553	562	static ADDRESS_MAP_START( looping_cop_io_map, AS_IO, 8, looping_state )
554		AM_RANGE(0x0100, 0x0107) AM_READWRITE_LEGACY(cop_io_r, cop_io_w)
	563	AM_RANGE(0x0100, 0x0107) AM_READWRITE(cop_io_r, cop_io_w)
555	564	ADDRESS_MAP_END
556	565
557	566
r14845	r14846
898	907	rom[i] = BITSWAP8(rom[i], 0,1,2,3,4,5,6,7);
899	908
900	909	/* install protection handlers */
901		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x7000, 0x7007, FUNC(protection_r));
	910	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x7000, 0x7007, read8_delegate(FUNC(looping_state::protection_r), state));
902	911	}
903	912
904	913

src/mame/drivers/1945kiii.c

r14845	r14846
67	67	/* devices */
68	68	required_device<okim6295_device> m_oki1;
69	69	required_device<okim6295_device> m_oki2;
	70	DECLARE_WRITE16_MEMBER(k3_bgram_w);
	71	DECLARE_WRITE16_MEMBER(k3_scrollx_w);
	72	DECLARE_WRITE16_MEMBER(k3_scrolly_w);
	73	DECLARE_WRITE16_MEMBER(k3_soundbanks_w);
70	74	};
71	75
72	76
73		static WRITE16_HANDLER( k3_bgram_w )
	77	WRITE16_MEMBER(k3_state::k3_bgram_w)
74	78	{
75		k3_state *state = space->machine().driver_data<k3_state>();
76		COMBINE_DATA(&state->m_bgram[offset]);
77		state->m_bg_tilemap->mark_tile_dirty(offset);
	79	COMBINE_DATA(&m_bgram[offset]);
	80	m_bg_tilemap->mark_tile_dirty(offset);
78	81	}
79	82
80	83	static TILE_GET_INFO( get_k3_bg_tile_info )
r14845	r14846
125	128	}
126	129
127	130
128		static WRITE16_HANDLER( k3_scrollx_w )
	131	WRITE16_MEMBER(k3_state::k3_scrollx_w)
129	132	{
130		k3_state *state = space->machine().driver_data<k3_state>();
131		state->m_bg_tilemap->set_scrollx(0, data);
	133	m_bg_tilemap->set_scrollx(0, data);
132	134	}
133	135
134		static WRITE16_HANDLER( k3_scrolly_w )
	136	WRITE16_MEMBER(k3_state::k3_scrolly_w)
135	137	{
136		k3_state *state = space->machine().driver_data<k3_state>();
137		state->m_bg_tilemap->set_scrolly(0, data);
	138	m_bg_tilemap->set_scrolly(0, data);
138	139	}
139	140
140		static WRITE16_HANDLER( k3_soundbanks_w )
	141	WRITE16_MEMBER(k3_state::k3_soundbanks_w)
141	142	{
142		k3_state *state = space->machine().driver_data<k3_state>();
143		state->m_oki1->set_bank_base((data & 4) ? 0x40000 : 0);
144		state->m_oki2->set_bank_base((data & 2) ? 0x40000 : 0);
	143	m_oki1->set_bank_base((data & 4) ? 0x40000 : 0);
	144	m_oki2->set_bank_base((data & 2) ? 0x40000 : 0);
145	145	}
146	146
147	147	static ADDRESS_MAP_START( k3_map, AS_PROGRAM, 16, k3_state )
r14845	r14846
153	153	AM_RANGE(0x200000, 0x200fff) AM_RAM_WRITE_LEGACY(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)   // palette
154	154	AM_RANGE(0x240000, 0x240fff) AM_RAM AM_BASE(m_spriteram_1)
155	155	AM_RANGE(0x280000, 0x280fff) AM_RAM AM_BASE(m_spriteram_2)
156		AM_RANGE(0x2c0000, 0x2c0fff) AM_RAM_WRITE_LEGACY(k3_bgram_w) AM_BASE(m_bgram)
157		AM_RANGE(0x340000, 0x340001) AM_WRITE_LEGACY(k3_scrollx_w)
158		AM_RANGE(0x380000, 0x380001) AM_WRITE_LEGACY(k3_scrolly_w)
159		AM_RANGE(0x3c0000, 0x3c0001) AM_WRITE_LEGACY(k3_soundbanks_w)
	156	AM_RANGE(0x2c0000, 0x2c0fff) AM_RAM_WRITE(k3_bgram_w) AM_BASE(m_bgram)
	157	AM_RANGE(0x340000, 0x340001) AM_WRITE(k3_scrollx_w)
	158	AM_RANGE(0x380000, 0x380001) AM_WRITE(k3_scrolly_w)
	159	AM_RANGE(0x3c0000, 0x3c0001) AM_WRITE(k3_soundbanks_w)
160	160	AM_RANGE(0x400000, 0x400001) AM_READ_PORT("INPUTS")
161	161	AM_RANGE(0x440000, 0x440001) AM_READ_PORT("SYSTEM")
162	162	AM_RANGE(0x480000, 0x480001) AM_READ_PORT("DSW")

src/mame/drivers/astinvad.c

r14845	r14846
62	62	device_t *m_ppi8255_0;
63	63	device_t *m_ppi8255_1;
64	64	samples_device *m_samples;
	65	DECLARE_WRITE8_MEMBER(color_latch_w);
	66	DECLARE_WRITE8_MEMBER(spaceint_videoram_w);
	67	DECLARE_READ8_MEMBER(kamikaze_ppi_r);
	68	DECLARE_WRITE8_MEMBER(kamikaze_ppi_w);
	69	DECLARE_WRITE8_MEMBER(spaceint_sound1_w);
	70	DECLARE_WRITE8_MEMBER(spaceint_sound2_w);
65	71	};
66	72
67	73
r14845	r14846
112	118	}
113	119
114	120
115		static WRITE8_HANDLER( color_latch_w )
	121	WRITE8_MEMBER(astinvad_state::color_latch_w)
116	122	{
117		astinvad_state *state = space->machine().driver_data<astinvad_state>();
118		state->m_color_latch = data & 0x0f;
	123	m_color_latch = data & 0x0f;
119	124	}
120	125
121	126
122		static WRITE8_HANDLER( spaceint_videoram_w )
	127	WRITE8_MEMBER(astinvad_state::spaceint_videoram_w)
123	128	{
124		astinvad_state *state = space->machine().driver_data<astinvad_state>();
125		state->m_videoram[offset] = data;
126		state->m_colorram[offset] = state->m_color_latch;
	129	m_videoram[offset] = data;
	130	m_colorram[offset] = m_color_latch;
127	131	}
128	132
129	133
r14845	r14846
288	292	*
289	293	*************************************/
290	294
291		static READ8_HANDLER( kamikaze_ppi_r )
	295	READ8_MEMBER(astinvad_state::kamikaze_ppi_r)
292	296	{
293		astinvad_state *state = space->machine().driver_data<astinvad_state>();
294	297	UINT8 result = 0xff;
295	298
296	299	/* the address lines are used for /CS; yes, they can overlap! */
297	300	if (!(offset & 4))
298		result &= ppi8255_r(state->m_ppi8255_0, offset);
	301	result &= ppi8255_r(m_ppi8255_0, offset);
299	302	if (!(offset & 8))
300		result &= ppi8255_r(state->m_ppi8255_1, offset);
	303	result &= ppi8255_r(m_ppi8255_1, offset);
301	304	return result;
302	305	}
303	306
304	307
305		static WRITE8_HANDLER( kamikaze_ppi_w )
	308	WRITE8_MEMBER(astinvad_state::kamikaze_ppi_w)
306	309	{
307		astinvad_state *state = space->machine().driver_data<astinvad_state>();
308	310
309	311	/* the address lines are used for /CS; yes, they can overlap! */
310	312	if (!(offset & 4))
311		ppi8255_w(state->m_ppi8255_0, offset, data);
	313	ppi8255_w(m_ppi8255_0, offset, data);
312	314	if (!(offset & 8))
313		ppi8255_w(state->m_ppi8255_1, offset, data);
	315	ppi8255_w(m_ppi8255_1, offset, data);
314	316	}
315	317
316	318
r14845	r14846
354	356	}
355	357
356	358
357		static WRITE8_HANDLER( spaceint_sound1_w )
	359	WRITE8_MEMBER(astinvad_state::spaceint_sound1_w)
358	360	{
359		astinvad_state *state = space->machine().driver_data<astinvad_state>();
360		int bits_gone_hi = data & ~state->m_sound_state[0];
361		state->m_sound_state[0] = data;
	361	int bits_gone_hi = data & ~m_sound_state[0];
	362	m_sound_state[0] = data;
362	363
363		if (bits_gone_hi & 0x01) state->m_samples->start(1, SND_SHOT);
364		if (bits_gone_hi & 0x02) state->m_samples->start(2, SND_BASEHIT);
365		if (bits_gone_hi & 0x04) state->m_samples->start(4, SND_UFOHIT);
366		if (bits_gone_hi & 0x08) state->m_samples->start(0, SND_UFO, true);
367		if (!(data & 0x08))      state->m_samples->stop(0);
	364	if (bits_gone_hi & 0x01) m_samples->start(1, SND_SHOT);
	365	if (bits_gone_hi & 0x02) m_samples->start(2, SND_BASEHIT);
	366	if (bits_gone_hi & 0x04) m_samples->start(4, SND_UFOHIT);
	367	if (bits_gone_hi & 0x08) m_samples->start(0, SND_UFO, true);
	368	if (!(data & 0x08))      m_samples->stop(0);
368	369
369		if (bits_gone_hi & 0x10) state->m_samples->start(5, SND_FLEET1);
370		if (bits_gone_hi & 0x20) state->m_samples->start(5, SND_FLEET2);
371		if (bits_gone_hi & 0x40) state->m_samples->start(5, SND_FLEET3);
372		if (bits_gone_hi & 0x80) state->m_samples->start(5, SND_FLEET4);
	370	if (bits_gone_hi & 0x10) m_samples->start(5, SND_FLEET1);
	371	if (bits_gone_hi & 0x20) m_samples->start(5, SND_FLEET2);
	372	if (bits_gone_hi & 0x40) m_samples->start(5, SND_FLEET3);
	373	if (bits_gone_hi & 0x80) m_samples->start(5, SND_FLEET4);
373	374	}
374	375
375	376
376		static WRITE8_HANDLER( spaceint_sound2_w )
	377	WRITE8_MEMBER(astinvad_state::spaceint_sound2_w)
377	378	{
378		astinvad_state *state = space->machine().driver_data<astinvad_state>();
379		int bits_gone_hi = data & ~state->m_sound_state[1];
380		state->m_sound_state[1] = data;
	379	int bits_gone_hi = data & ~m_sound_state[1];
	380	m_sound_state[1] = data;
381	381
382		space->machine().sound().system_enable(data & 0x02);
	382	machine().sound().system_enable(data & 0x02);
383	383
384		if (bits_gone_hi & 0x04) state->m_samples->start(3, SND_INVADERHIT);
	384	if (bits_gone_hi & 0x04) m_samples->start(3, SND_INVADERHIT);
385	385
386		state->m_screen_flip = (input_port_read(space->machine(), "CABINET") & data & 0x80) ? 0xff : 0x00;
	386	m_screen_flip = (input_port_read(machine(), "CABINET") & data & 0x80) ? 0xff : 0x00;
387	387	}
388	388
389	389
r14845	r14846
405	405	static ADDRESS_MAP_START( spaceint_map, AS_PROGRAM, 8, astinvad_state )
406	406	AM_RANGE(0x0000, 0x1fff) AM_ROM
407	407	AM_RANGE(0x2000, 0x23ff) AM_RAM
408		AM_RANGE(0x4000, 0x5fff) AM_RAM_WRITE_LEGACY(spaceint_videoram_w) AM_BASE_SIZE(m_videoram, m_videoram_size)
	408	AM_RANGE(0x4000, 0x5fff) AM_RAM_WRITE(spaceint_videoram_w) AM_BASE_SIZE(m_videoram, m_videoram_size)
409	409	ADDRESS_MAP_END
410	410
411	411
412	412	static ADDRESS_MAP_START( kamikaze_portmap, AS_IO, 8, astinvad_state )
413	413	ADDRESS_MAP_GLOBAL_MASK(0xff)
414		AM_RANGE(0x00, 0xff) AM_READWRITE_LEGACY(kamikaze_ppi_r, kamikaze_ppi_w)
	414	AM_RANGE(0x00, 0xff) AM_READWRITE(kamikaze_ppi_r, kamikaze_ppi_w)
415	415	ADDRESS_MAP_END
416	416
417	417
r14845	r14846
419	419	ADDRESS_MAP_GLOBAL_MASK(0xff)
420	420	AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0")
421	421	AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1")
422		AM_RANGE(0x02, 0x02) AM_WRITE_LEGACY(spaceint_sound1_w)
423		AM_RANGE(0x03, 0x03) AM_WRITE_LEGACY(color_latch_w)
424		AM_RANGE(0x04, 0x04) AM_WRITE_LEGACY(spaceint_sound2_w)
	422	AM_RANGE(0x02, 0x02) AM_WRITE(spaceint_sound1_w)
	423	AM_RANGE(0x03, 0x03) AM_WRITE(color_latch_w)
	424	AM_RANGE(0x04, 0x04) AM_WRITE(spaceint_sound2_w)
425	425	ADDRESS_MAP_END
426	426
427	427

src/mame/drivers/supertnk.c

r14845	r14846
115	115	UINT8 m_rom_bank;
116	116	UINT8 m_bitplane_select;
117	117	pen_t m_pens[NUM_PENS];
	118	DECLARE_WRITE8_MEMBER(supertnk_bankswitch_0_w);
	119	DECLARE_WRITE8_MEMBER(supertnk_bankswitch_1_w);
	120	DECLARE_WRITE8_MEMBER(supertnk_interrupt_ack_w);
	121	DECLARE_WRITE8_MEMBER(supertnk_videoram_w);
	122	DECLARE_READ8_MEMBER(supertnk_videoram_r);
	123	DECLARE_WRITE8_MEMBER(supertnk_bitplane_select_0_w);
	124	DECLARE_WRITE8_MEMBER(supertnk_bitplane_select_1_w);
118	125	};
119	126
120	127
r14845	r14846
125	132	*
126	133	*************************************/
127	134
128		static WRITE8_HANDLER( supertnk_bankswitch_0_w )
	135	WRITE8_MEMBER(supertnk_state::supertnk_bankswitch_0_w)
129	136	{
130		supertnk_state *state = space->machine().driver_data<supertnk_state>();
131	137	offs_t bank_address;
132	138
133		state->m_rom_bank = (state->m_rom_bank & 0x02) | ((data << 0) & 0x01);
	139	m_rom_bank = (m_rom_bank & 0x02) | ((data << 0) & 0x01);
134	140
135		bank_address = 0x10000 + (state->m_rom_bank * 0x1000);
	141	bank_address = 0x10000 + (m_rom_bank * 0x1000);
136	142
137		memory_set_bankptr(space->machine(), "bank1", &space->machine().region("maincpu")->base()[bank_address]);
	143	memory_set_bankptr(machine(), "bank1", &machine().region("maincpu")->base()[bank_address]);
138	144	}
139	145
140	146
141		static WRITE8_HANDLER( supertnk_bankswitch_1_w )
	147	WRITE8_MEMBER(supertnk_state::supertnk_bankswitch_1_w)
142	148	{
143		supertnk_state *state = space->machine().driver_data<supertnk_state>();
144	149	offs_t bank_address;
145	150
146		state->m_rom_bank = (state->m_rom_bank & 0x01) | ((data << 1) & 0x02);
	151	m_rom_bank = (m_rom_bank & 0x01) | ((data << 1) & 0x02);
147	152
148		bank_address = 0x10000 + (state->m_rom_bank * 0x1000);
	153	bank_address = 0x10000 + (m_rom_bank * 0x1000);
149	154
150		memory_set_bankptr(space->machine(), "bank1", &space->machine().region("maincpu")->base()[bank_address]);
	155	memory_set_bankptr(machine(), "bank1", &machine().region("maincpu")->base()[bank_address]);
151	156	}
152	157
153	158
r14845	r14846
165	170	}
166	171
167	172
168		static WRITE8_HANDLER( supertnk_interrupt_ack_w )
	173	WRITE8_MEMBER(supertnk_state::supertnk_interrupt_ack_w)
169	174	{
170		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
	175	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
171	176	}
172	177
173	178
r14845	r14846
197	202	}
198	203
199	204
200		static WRITE8_HANDLER( supertnk_videoram_w )
	205	WRITE8_MEMBER(supertnk_state::supertnk_videoram_w)
201	206	{
202		supertnk_state *state = space->machine().driver_data<supertnk_state>();
203	207
204		if (state->m_bitplane_select > 2)
	208	if (m_bitplane_select > 2)
205	209	{
206		state->m_videoram[0][offset] = 0;
207		state->m_videoram[1][offset] = 0;
208		state->m_videoram[2][offset] = 0;
	210	m_videoram[0][offset] = 0;
	211	m_videoram[1][offset] = 0;
	212	m_videoram[2][offset] = 0;
209	213	}
210	214	else
211	215	{
212		state->m_videoram[state->m_bitplane_select][offset] = data;
	216	m_videoram[m_bitplane_select][offset] = data;
213	217	}
214	218	}
215	219
216	220
217		static READ8_HANDLER( supertnk_videoram_r )
	221	READ8_MEMBER(supertnk_state::supertnk_videoram_r)
218	222	{
219		supertnk_state *state = space->machine().driver_data<supertnk_state>();
220	223	UINT8 ret = 0x00;
221	224
222		if (state->m_bitplane_select < 3)
223		ret = state->m_videoram[state->m_bitplane_select][offset];
	225	if (m_bitplane_select < 3)
	226	ret = m_videoram[m_bitplane_select][offset];
224	227
225	228	return ret;
226	229	}
227	230
228	231
229		static WRITE8_HANDLER( supertnk_bitplane_select_0_w )
	232	WRITE8_MEMBER(supertnk_state::supertnk_bitplane_select_0_w)
230	233	{
231		supertnk_state *state = space->machine().driver_data<supertnk_state>();
232	234
233		state->m_bitplane_select = (state->m_bitplane_select & 0x02) | ((data << 0) & 0x01);
	235	m_bitplane_select = (m_bitplane_select & 0x02) | ((data << 0) & 0x01);
234	236	}
235	237
236	238
237		static WRITE8_HANDLER( supertnk_bitplane_select_1_w )
	239	WRITE8_MEMBER(supertnk_state::supertnk_bitplane_select_1_w)
238	240	{
239		supertnk_state *state = space->machine().driver_data<supertnk_state>();
240	241
241		state->m_bitplane_select = (state->m_bitplane_select & 0x01) | ((data << 1) & 0x02);
	242	m_bitplane_select = (m_bitplane_select & 0x01) | ((data << 1) & 0x02);
242	243	}
243	244
244	245
r14845	r14846
284	285
285	286	static MACHINE_RESET( supertnk )
286	287	{
	288	supertnk_state *state = machine.driver_data<supertnk_state>();
287	289	address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
288		supertnk_bankswitch_0_w(space, 0, 0);
289		supertnk_bankswitch_1_w(space, 0, 0);
	290	state->supertnk_bankswitch_0_w(*space, 0, 0);
	291	state->supertnk_bankswitch_1_w(*space, 0, 0);
290	292
291		supertnk_bitplane_select_0_w(space, 0, 0);
292		supertnk_bitplane_select_1_w(space, 0, 0);
	293	state->supertnk_bitplane_select_0_w(*space, 0, 0);
	294	state->supertnk_bitplane_select_1_w(*space, 0, 0);
293	295	}
294	296
295	297
r14845	r14846
309	311	AM_RANGE(0x1efe, 0x1eff) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
310	312	AM_RANGE(0x1efe, 0x1efe) AM_READ_PORT("DSW")
311	313	AM_RANGE(0x1eff, 0x1eff) AM_READ_PORT("UNK")
312		AM_RANGE(0x2000, 0x3fff) AM_READWRITE_LEGACY(supertnk_videoram_r, supertnk_videoram_w)
	314	AM_RANGE(0x2000, 0x3fff) AM_READWRITE(supertnk_videoram_r, supertnk_videoram_w)
313	315	ADDRESS_MAP_END
314	316
315	317
r14845	r14846
322	324
323	325	static ADDRESS_MAP_START( supertnk_io_map, AS_IO, 8, supertnk_state )
324	326	AM_RANGE(0x0000, 0x0000) AM_WRITENOP
325		AM_RANGE(0x0400, 0x0400) AM_WRITE_LEGACY(supertnk_bitplane_select_0_w)
326		AM_RANGE(0x0401, 0x0401) AM_WRITE_LEGACY(supertnk_bitplane_select_1_w)
327		AM_RANGE(0x0402, 0x0402) AM_WRITE_LEGACY(supertnk_bankswitch_0_w)
328		AM_RANGE(0x0404, 0x0404) AM_WRITE_LEGACY(supertnk_bankswitch_1_w)
329		AM_RANGE(0x0406, 0x0406) AM_WRITE_LEGACY(supertnk_interrupt_ack_w)
	327	AM_RANGE(0x0400, 0x0400) AM_WRITE(supertnk_bitplane_select_0_w)
	328	AM_RANGE(0x0401, 0x0401) AM_WRITE(supertnk_bitplane_select_1_w)
	329	AM_RANGE(0x0402, 0x0402) AM_WRITE(supertnk_bankswitch_0_w)
	330	AM_RANGE(0x0404, 0x0404) AM_WRITE(supertnk_bankswitch_1_w)
	331	AM_RANGE(0x0406, 0x0406) AM_WRITE(supertnk_interrupt_ack_w)
330	332	AM_RANGE(0x0407, 0x0407) AM_WRITE_LEGACY(watchdog_reset_w)
331	333	ADDRESS_MAP_END
332	334

src/mame/drivers/neodrvr.c

r14845	r14846
500	500	. NEO-AEG PROG4096 B
501	501	. NEO-AEG PROGGS
502	502	. NEO-AEG PROGTOP2
	503	. NEO-AEG PROGEOP (1999.4.2)
503	504	. NEO-AEG PROGLBA (1999.7.6)
504	505	. NEO-AEG PROGRK
505	506	. NEO-AEG PROGRKB
r14845	r14846
5774	5775	. NGM-2410
5775	5776	NEO-MVS PROGBK1 / NEO-MVS CHA512Y
5776	5777	. NGH-2410
	5778	NEO-AEG PROGBK1Y / NEO-AEG CHA512Y
5777	5779	****************************************/
5778	5780
5779		ROM_START( mslug2 )
	5781	ROM_START( mslug2 ) /* MVS AND AES VERSION */
5780	5782	ROM_REGION( 0x300000, "maincpu", 0 )
5781	5783	ROM_LOAD16_WORD_SWAP( "241-p1.p1",  0x000000, 0x100000, CRC(2a53c5da) SHA1(5a6aba482cac588a6c2c51179c95b487c6e11899) ) /* TC538200 */
5782	5784	ROM_LOAD16_WORD_SWAP( "241-p2.sp2", 0x100000, 0x200000, CRC(38883f44) SHA1(fcf34b8c6e37774741542393b963635412484a27) ) /* TC5316200 */
r14845	r14846
6126	6128	/****************************************
6127	6129	ID-0250
6128	6130	. NGM-2500
6129		NEO-MVS PROGEOP / NEO-MVS CHA512Y
	6131	NEO-MVS PROGEOP (1999.2.2) / NEO-MVS CHA512Y
6130	6132	. NGH-2500
	6133	NEO-AEG PROGEOP (1999.4.2) / NEO-AEG CHA512Y
6131	6134	****************************************/
6132	6135
6133		ROM_START( mslugx )
	6136	ROM_START( mslugx ) /* MVS AND AES VERSION */
6134	6137	ROM_REGION( 0x500000, "maincpu", 0 )
6135	6138	ROM_LOAD16_WORD_SWAP( "250-p1.p1",  0x000000, 0x100000, CRC(81f1f60b) SHA1(4c19f2e9824e606178ac1c9d4b0516fbaa625035) ) /* TC538200 */
6136	6139	ROM_LOAD16_WORD_SWAP( "250-p2.ep1", 0x100000, 0x400000, CRC(1fda2e12) SHA1(18aaa7a3ba8da99f78c430e9be69ccde04bc04d9) ) /* TC5332205 */
r14845	r14846
6380	6383	. NGM-2530
6381	6384	NEO-MVS PROGLBA (NEO-SMA) (LBA-SUB) / NEO-MVS CHAFIO (1999.6.14) (NEO-CMC 7042)
6382	6385	. NGH-2530
	6386	NEO-AEG PROGLBA (NEO-SMA) / NEO-AEG CHAFIO (1999.8.10) (NEO-CMC 7042)
6383	6387	****************************************/
6384	6388
6385		ROM_START( garou ) /* Original Version - Encrypted GFX */ /* later revision */
	6389	ROM_START( garou ) /* Original Version - Encrypted GFX */ /* MVS VERSION - later revision */
6386	6390	ROM_REGION( 0x900000, "maincpu", 0 )
6387	6391	ROM_LOAD16_WORD_SWAP( "kf.neo-sma", 0x0c0000, 0x040000, CRC(98bc93dc) SHA1(01fe3d18b50f770e131e8d8eeff4c630ba8c9551) )   /* stored in the custom chip */
6388	6392	ROM_LOAD16_WORD_SWAP( "253-ep1.p1", 0x100000, 0x200000, CRC(ea3171a4) SHA1(bbda40f652baa0dc5fc6a006c001a1bdb0df43f6) ) /* M27C160 */
r14845	r14846
6420	6424	ROM_LOAD16_BYTE( "253-c8.c8", 0x3000001, 0x800000, CRC(21a11303) SHA1(fd61221ad257c185ef5c1f9694bd6b840b591af3) ) /* Plane 2,3 */ /* TC5364205 */
6421	6425	ROM_END
6422	6426
6423		ROM_START( garouo ) /* Original Version - Encrypted GFX */ /* earlier revision */
	6427	ROM_START( garouh ) /* Original Version - Encrypted GFX */ /* MVS AND AES VERSION - earlier revision */
6424	6428	ROM_REGION( 0x900000, "maincpu", 0 )
6425	6429	ROM_LOAD16_WORD_SWAP( "ke.neo-sma", 0x0c0000, 0x040000, CRC(96c72233) SHA1(29e19effd40fdf7e5144332396857f4ad0eff13e) )   /* stored in the custom chip */
6426	6430	ROM_LOAD16_WORD_SWAP( "253-p1.p1",  0x100000, 0x400000, CRC(18ae5d7e) SHA1(bdb58ec9137d8653979b47132f2d10e1cc6aaa24) ) /* mask rom TC5332205 */
r14845	r14846
7681	7685	ROM_END
7682	7686
7683	7687
	7688	/* Vektorlogic games, unlicensed */
	7689
	7690
	7691	/****************************************
	7692	NSBP ??
	7693	PROGRAM CART REVISION 2.0 (C) VEKTORLOGIC 2004 / GRAPHICS CART REVISION 1.2 (C) VEKTORLOGIC 2004
	7694	****************************************/
	7695
	7696	// this doesn't boot, protection like kof98?
	7697	// you can force it to boot with a simple debugger trick, but then it resets when starting a game
	7698	ROM_START( sbp ) /* Unlicensed, no official game ID # */ /* MVS ONLY VERSION */
	7699	ROM_REGION( 0x100000, "maincpu", 0 )
	7700	ROM_LOAD16_WORD_SWAP( "001-003-02a.u2", 0x000000, 0x080000, CRC(d054d264) SHA1(d1b4bc626d000e0679def0545940fa75035921ab) ) /* HN27C4096HG */
	7701
	7702	ROM_REGION( 0x20000, "fixed", 0 )
	7703	ROM_LOAD( "001-003-02b.u2", 0x000000, 0x20000, CRC(2fd04b2a) SHA1(1acb446704ab56d0a33df7c48855aa8d00fd5a3c) ) /* M27C4001 */
	7704	ROM_IGNORE(0x20000)
	7705	ROM_IGNORE(0x20000)
	7706	ROM_IGNORE(0x20000)
	7707
	7708	ROM_REGION( 0x20000, "fixedbios", 0 )
	7709	ROM_LOAD( "sfix.sfix", 0x000000, 0x20000, CRC(c2ea0cfd) SHA1(fd4a618cdcdbf849374f0a50dd8efe9dbab706c3) )
	7710	ROM_Y_ZOOM
	7711
	7712	NEO_BIOS_AUDIO_512K( "001-003-01b.u1", CRC(7b1f86f7) SHA1(15b6af7f9fbd0f1f6a1ecd912200ca8d0af2da2a) ) /* M27C4001 */
	7713
	7714	ROM_REGION( 0x800000, "ymsnd", 0 )
	7715	ROM_LOAD( "001-003-12a.u12", 0x000000, 0x400000, CRC(c96723b9) SHA1(52eec88550781d45f84efbf9b905d7e7912e96fa) ) /* M27C322 */
	7716	ROM_LOAD( "001-003-13a.u13", 0x400000, 0x400000, CRC(08c339a5) SHA1(badc9510ae243ef2a7877977eb36efa81b1489fe) ) /* M27C322 */
	7717
	7718	NO_DELTAT_REGION
	7719
	7720	ROM_REGION( 0x400000, "sprites", 0 )
	7721	ROM_LOAD16_BYTE( "001-003-03b.u3", 0x000000, 0x200000, CRC(44791317) SHA1(9e773eb9aae5ee767213bd17348ff8a312e9cb16) ) /* Plane 0,1 */ /* M27C160 */
	7722	ROM_LOAD16_BYTE( "001-003-04b.u4", 0x000001, 0x200000, CRC(a3a1c0df) SHA1(3b1e5be673f7cbb04199a805b0e0de93dad8cb8c) ) /* Plane 2,3 */ /* M27C160 */
	7723	ROM_END
	7724
	7725
7684	7726	/* Jamma PCB sets */
7685	7727
7686	7728
r14845	r14846
8873	8915	ROM_LOAD16_BYTE( "dig-c2.bin", 0x000001, 0x080000, CRC(3e632161) SHA1(83711c4286fb1d9f3f91414ac6e5fed36618033e) ) /* Plane 2,3 */
8874	8916	ROM_END
8875	8917
8876		// this doesn't boot, protection like kof98?
8877		// you can force it to boot with a simple debugger trick, but then it resets when starting a game
8878		ROM_START( sbp ) /* Unlicensed, no official game ID # */
8879		ROM_REGION( 0x100000, "maincpu", 0 )
8880		ROM_LOAD16_WORD_SWAP( "2a.bin", 0x000000, 0x080000, CRC(d054d264) SHA1(d1b4bc626d000e0679def0545940fa75035921ab) )
8881	8918
8882		ROM_REGION( 0x20000, "fixed", 0 )
8883		ROM_LOAD( "2b.bin",       0x000000, 0x20000, CRC(2fd04b2a) SHA1(1acb446704ab56d0a33df7c48855aa8d00fd5a3c) )
8884		ROM_IGNORE(0x20000)
8885		ROM_IGNORE(0x20000)
8886		ROM_IGNORE(0x20000)
8887
8888		ROM_REGION( 0x20000, "fixedbios", 0 )
8889		ROM_LOAD( "sfix.sfix", 0x000000, 0x20000, CRC(c2ea0cfd) SHA1(fd4a618cdcdbf849374f0a50dd8efe9dbab706c3) )
8890		ROM_Y_ZOOM
8891
8892		NEO_BIOS_AUDIO_512K( "1b.bin", CRC(7b1f86f7) SHA1(15b6af7f9fbd0f1f6a1ecd912200ca8d0af2da2a) )
8893
8894		ROM_REGION( 0x800000, "ymsnd", 0 )
8895		ROM_LOAD( "12a.bin", 0x000000, 0x400000, CRC(c96723b9) SHA1(52eec88550781d45f84efbf9b905d7e7912e96fa) )
8896		ROM_LOAD( "13a.bin", 0x400000, 0x400000, CRC(08c339a5) SHA1(badc9510ae243ef2a7877977eb36efa81b1489fe) )
8897
8898		NO_DELTAT_REGION
8899
8900		ROM_REGION( 0x400000, "sprites", 0 )
8901		ROM_LOAD16_BYTE( "3b.bin", 0x000000, 0x200000, CRC(44791317) SHA1(9e773eb9aae5ee767213bd17348ff8a312e9cb16) ) /* Plane 0,1 */
8902		ROM_LOAD16_BYTE( "4b.bin", 0x000001, 0x200000, CRC(a3a1c0df) SHA1(3b1e5be673f7cbb04199a805b0e0de93dad8cb8c) ) /* Plane 2,3 */
8903		ROM_END
8904
8905
8906	8919	/****************************************************************************/
8907	8920
8908	8921	/* Game specific input definitions */
r14845	r14846
9252	9265	garou_install_protection(machine);
9253	9266	}
9254	9267
9255		static DRIVER_INIT( garouo )
	9268	static DRIVER_INIT( garouh )
9256	9269	{
9257	9270	neogeo_state *state = machine.driver_data<neogeo_state>();
9258	9271	DRIVER_INIT_CALL(neogeo);
9259		garouo_decrypt_68k(machine);
	9272	garouh_decrypt_68k(machine);
9260	9273	state->m_fixed_layer_bank_type = 1;
9261	9274	kof99_neogeo_gfx_decrypt(machine, 0x06);
9262		garouo_install_protection(machine);
	9275	garouh_install_protection(machine);
9263	9276	}
9264	9277
9265	9278	static DRIVER_INIT( garoubl )
r14845	r14846
9901	9914	else if(strcmp(crypt_feature,"kof99_prot") == 0)   { neo_gameinit = driver_init_kof99; }
9902	9915	else if(strcmp(crypt_feature,"kof99k_prot") == 0)   { neo_gameinit = driver_init_kof99k; }
9903	9916	else if(strcmp(crypt_feature,"garou_prot") == 0)   { neo_gameinit = driver_init_garou; }
9904		else if(strcmp(crypt_feature,"garouo_prot") == 0)   { neo_gameinit = driver_init_garouo; }
	9917	else if(strcmp(crypt_feature,"garouh_prot") == 0)   { neo_gameinit = driver_init_garouh; }
9905	9918	else if(strcmp(crypt_feature,"garoubl_prot") == 0)   { neo_gameinit = driver_init_garoubl; }
9906	9919	else if(strcmp(crypt_feature,"mslug3_prot") == 0)   { neo_gameinit = driver_init_mslug3; }
9907	9920	else if(strcmp(crypt_feature,"mslug3h_prot") == 0)   { neo_gameinit = driver_init_mslug3h; }
r14845	r14846
10053	10066	GAME( 1998, rbff2,     neogeo,   neogeo,   neogeo,   neogeo,   ROT0, "SNK", "Real Bout Fatal Fury 2 - The Newcomers / Real Bout Garou Densetsu 2 - the newcomers (NGM-2400)", GAME_SUPPORTS_SAVE )
10054	10067	GAME( 1998, rbff2h,    rbff2,    neogeo,   neogeo,   neogeo,   ROT0, "SNK", "Real Bout Fatal Fury 2 - The Newcomers / Real Bout Garou Densetsu 2 - the newcomers (NGH-2400)", GAME_SUPPORTS_SAVE )
10055	10068	GAME( 1998, rbff2k,    rbff2,    neogeo,   neogeo,   neogeo,   ROT0, "SNK", "Real Bout Fatal Fury 2 - The Newcomers (Korean release)", GAME_SUPPORTS_SAVE ) // no Japanese title / mode
10056		GAME( 1998, mslug2,    neogeo,   neogeo,   neogeo,   neogeo,   ROT0, "SNK", "Metal Slug 2 - Super Vehicle-001/II", GAME_SUPPORTS_SAVE )
	10069	GAME( 1998, mslug2,    neogeo,   neogeo,   neogeo,   neogeo,   ROT0, "SNK", "Metal Slug 2 - Super Vehicle-001/II (NGM-2410)(NGH-2410)", GAME_SUPPORTS_SAVE )
10057	10070	GAME( 1998, kof98,     neogeo,   neogeo,   neogeo,   kof98,    ROT0, "SNK", "The King of Fighters '98 - The Slugfest / King of Fighters '98 - dream match never ends (NGM-2420)", GAME_SUPPORTS_SAVE )
10058	10071	GAME( 1998, kof98k,    kof98,    neogeo,   neogeo,   kof98,    ROT0, "SNK", "The King of Fighters '98 - The Slugfest / King of Fighters '98 - dream match never ends (Korean board)", GAME_SUPPORTS_SAVE )
10059	10072	GAME( 1998, kof98ka,   kof98,    neogeo,   neogeo,   kof98,    ROT0, "SNK", "The King of Fighters '98 - The Slugfest / King of Fighters '98 - dream match never ends (Korean board 2)", GAME_SUPPORTS_SAVE )
10060	10073	GAME( 1998, kof98h,    kof98,    neogeo,   neogeo,   neogeo,   ROT0, "SNK", "The King of Fighters '98 - The Slugfest / King of Fighters '98 - dream match never ends (NGH-2420)", GAME_SUPPORTS_SAVE )
10061	10074	GAME( 1998, lastbld2,  neogeo,   neogeo,   neogeo,   neogeo,   ROT0, "SNK", "The Last Blade 2 / Bakumatsu Roman - Dai Ni Maku Gekka no Kenshi (NGM-2430)(NGH-2430)", GAME_SUPPORTS_SAVE )
10062	10075	GAME( 1998, neocup98,  neogeo,   neogeo,   neogeo,   neogeo,   ROT0, "SNK", "Neo-Geo Cup '98 - The Road to the Victory", GAME_SUPPORTS_SAVE )
10063		GAME( 1999, mslugx,    neogeo,   neogeo,   neogeo,   mslugx,   ROT0, "SNK", "Metal Slug X - Super Vehicle-001", GAME_SUPPORTS_SAVE )
10064		GAME( 1999, kof99,     neogeo,   neogeo,   neogeo,   kof99,    ROT0, "SNK", "The King of Fighters '99 - Millennium Battle (set 1)" , GAME_SUPPORTS_SAVE ) /* Encrypted Code & GFX */
10065		GAME( 1999, kof99h,    kof99,    neogeo,   neogeo,   kof99,    ROT0, "SNK", "The King of Fighters '99 - Millennium Battle (set 2)" , GAME_SUPPORTS_SAVE ) /* Encrypted Code & GFX, crashes going into attract demo */
	10076	GAME( 1999, mslugx,    neogeo,   neogeo,   neogeo,   mslugx,   ROT0, "SNK", "Metal Slug X - Super Vehicle-001 (NGM-2500)(NGH-2500)", GAME_SUPPORTS_SAVE )
	10077	GAME( 1999, kof99,     neogeo,   neogeo,   neogeo,   kof99,    ROT0, "SNK", "The King of Fighters '99 - Millennium Battle (NGM-2510)" , GAME_SUPPORTS_SAVE ) /* Encrypted Code & GFX */
	10078	GAME( 1999, kof99h,    kof99,    neogeo,   neogeo,   kof99,    ROT0, "SNK", "The King of Fighters '99 - Millennium Battle (NGH-2510)" , GAME_SUPPORTS_SAVE ) /* Encrypted Code & GFX, crashes going into attract demo */
10066	10079	GAME( 1999, kof99e,    kof99,    neogeo,   neogeo,   kof99,    ROT0, "SNK", "The King of Fighters '99 - Millennium Battle (earlier)" , GAME_SUPPORTS_SAVE ) /* Encrypted Code & GFX */
10067	10080	GAME( 1999, kof99k,    kof99,    neogeo,   neogeo,   kof99k,   ROT0, "SNK", "The King of Fighters '99 - Millennium Battle (Korean release)" , GAME_SUPPORTS_SAVE )   /* Encrypted GFX */
10068	10081	GAME( 1999, kof99p,    kof99,    neogeo,   neogeo,   neogeo,   ROT0, "SNK", "The King of Fighters '99 - Millennium Battle (prototype)", GAME_SUPPORTS_SAVE )
10069		GAME( 1999, garou,     neogeo,   neogeo,   neogeo,   garou,    ROT0, "SNK", "Garou - Mark of the Wolves (set 1)" , GAME_SUPPORTS_SAVE ) /* Encrypted Code & GFX */
10070		GAME( 1999, garouo,    garou,    neogeo,   neogeo,   garouo,   ROT0, "SNK", "Garou - Mark of the Wolves (set 2)" , GAME_SUPPORTS_SAVE ) /* Encrypted Code & GFX */
	10082	GAME( 1999, garou,     neogeo,   neogeo,   neogeo,   garou,    ROT0, "SNK", "Garou - Mark of the Wolves (NGM-2530)" , GAME_SUPPORTS_SAVE ) /* Encrypted Code & GFX */
	10083	GAME( 1999, garouh,    garou,    neogeo,   neogeo,   garouh,   ROT0, "SNK", "Garou - Mark of the Wolves (NGM-2530)(NGH-2530)" , GAME_SUPPORTS_SAVE ) /* Encrypted Code & GFX */
10071	10084	GAME( 1999, garoup,    garou,    neogeo,   neogeo,   neogeo,   ROT0, "SNK", "Garou - Mark of the Wolves (prototype)", GAME_SUPPORTS_SAVE )
10072	10085	GAME( 1999, garoubl,   garou,    neogeo,   neogeo,   garoubl,  ROT0, "bootleg", "Garou - Mark of the Wolves (bootleg)", GAME_SUPPORTS_SAVE ) /* Bootleg of garoup */
10073	10086	GAME( 2000, mslug3,    neogeo,   neogeo,   neogeo,   mslug3,   ROT0, "SNK", "Metal Slug 3 (NGM-2560)" , GAME_SUPPORTS_SAVE ) /* Encrypted Code & GFX */

src/mame/drivers/esh.c

r14845	r14846
39	39	UINT8 *m_tile_ram;
40	40	UINT8 *m_tile_control_ram;
41	41	UINT8 m_ld_video_visible;
	42	DECLARE_READ8_MEMBER(ldp_read);
	43	DECLARE_WRITE8_MEMBER(ldp_write);
	44	DECLARE_WRITE8_MEMBER(misc_write);
	45	DECLARE_WRITE8_MEMBER(led_writes);
	46	DECLARE_WRITE8_MEMBER(nmi_line_w);
42	47	};
43	48
44	49
r14845	r14846
81	86
82	87
83	88	/* MEMORY HANDLERS */
84		static READ8_HANDLER(ldp_read)
	89	READ8_MEMBER(esh_state::ldp_read)
85	90	{
86		esh_state *state = space->machine().driver_data<esh_state>();
87		return state->m_laserdisc->status_r();
	91	return m_laserdisc->status_r();
88	92	}
89	93
90		static WRITE8_HANDLER(ldp_write)
	94	WRITE8_MEMBER(esh_state::ldp_write)
91	95	{
92		esh_state *state = space->machine().driver_data<esh_state>();
93		state->m_laserdisc->data_w(data);
	96	m_laserdisc->data_w(data);
94	97	}
95	98
96		static WRITE8_HANDLER(misc_write)
	99	WRITE8_MEMBER(esh_state::misc_write)
97	100	{
98		esh_state *state = space->machine().driver_data<esh_state>();
99	101	/* Bit 0 unknown */
100	102
101	103	if (data & 0x02)
102	104	logerror("BEEP!\n");
103	105
104	106	/* Bit 2 unknown */
105		state->m_ld_video_visible = !((data & 0x08) >> 3);
	107	m_ld_video_visible = !((data & 0x08) >> 3);
106	108
107	109	/* Bits 4-7 unknown */
108	110	/* They cycle through a repeating pattern though */
109	111	}
110	112
111		static WRITE8_HANDLER(led_writes)
	113	WRITE8_MEMBER(esh_state::led_writes)
112	114	{
113	115	switch(offset)
114	116	{
r14845	r14846
139	141	}
140	142	}
141	143
142		static WRITE8_HANDLER(nmi_line_w)
	144	WRITE8_MEMBER(esh_state::nmi_line_w)
143	145	{
144	146	if (data == 0x00)
145		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_NMI, ASSERT_LINE);
	147	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_NMI, ASSERT_LINE);
146	148	if (data == 0x01)
147		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
	149	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
148	150
149	151	if (data != 0x00 && data != 0x01)
150	152	logerror("NMI line got a weird value!\n");
r14845	r14846
167	169	AM_RANGE(0xf1,0xf1) AM_READ_PORT("IN1")
168	170	AM_RANGE(0xf2,0xf2) AM_READ_PORT("IN2")
169	171	AM_RANGE(0xf3,0xf3) AM_READ_PORT("IN3")
170		AM_RANGE(0xf4,0xf4) AM_READWRITE_LEGACY(ldp_read,ldp_write)
171		AM_RANGE(0xf5,0xf5) AM_WRITE_LEGACY(misc_write)   /* Continuously writes repeating patterns */
172		AM_RANGE(0xf8,0xfd) AM_WRITE_LEGACY(led_writes)
173		AM_RANGE(0xfe,0xfe) AM_WRITE_LEGACY(nmi_line_w)   /* Both 0xfe and 0xff flip quickly between 0 and 1 */
	172	AM_RANGE(0xf4,0xf4) AM_READWRITE(ldp_read,ldp_write)
	173	AM_RANGE(0xf5,0xf5) AM_WRITE(misc_write)   /* Continuously writes repeating patterns */
	174	AM_RANGE(0xf8,0xfd) AM_WRITE(led_writes)
	175	AM_RANGE(0xfe,0xfe) AM_WRITE(nmi_line_w)   /* Both 0xfe and 0xff flip quickly between 0 and 1 */
174	176	AM_RANGE(0xff,0xff) AM_NOP               /*   (they're probably not NMI enables - likely LED's like their neighbors :) */
175	177	ADDRESS_MAP_END                           /*   (someday 0xf8-0xff will probably be a single handler) */
176	178

src/mame/drivers/ecoinf2.c

r14845	r14846
16	16	public:
17	17	ecoinf2_state(const machine_config &mconfig, device_type type, const char *tag)
18	18	: driver_device(mconfig, type, tag) { }
	19	DECLARE_WRITE8_MEMBER(ox_port5c_out_w);
19	20	};
20	21
21	22
22		static WRITE8_HANDLER( ox_port5c_out_w )
	23	WRITE8_MEMBER(ecoinf2_state::ox_port5c_out_w)
23	24	{
24	25	// Watchdog?
25	26	}
r14845	r14846
31	32
32	33	static ADDRESS_MAP_START( oxo_portmap, AS_IO, 8, ecoinf2_state )
33	34	ADDRESS_MAP_GLOBAL_MASK(0xff)
34		AM_RANGE(0x5c, 0x5c) AM_WRITE_LEGACY(ox_port5c_out_w)
	35	AM_RANGE(0x5c, 0x5c) AM_WRITE(ox_port5c_out_w)
35	36	ADDRESS_MAP_END
36	37
37	38

src/mame/drivers/halleys.c

r14845	r14846
243	243	emu_timer *m_blitter_reset_timer;
244	244	offs_t m_collision_detection;
245	245	int m_latch_delay;
	246	DECLARE_WRITE8_MEMBER(bgtile_w);
	247	DECLARE_READ8_MEMBER(blitter_status_r);
	248	DECLARE_READ8_MEMBER(blitter_r);
	249	DECLARE_WRITE8_MEMBER(blitter_w);
	250	DECLARE_READ8_MEMBER(collision_id_r);
	251	DECLARE_WRITE8_MEMBER(halleys_paletteram_IIRRGGBB_w);
	252	DECLARE_READ8_MEMBER(zero_r);
	253	DECLARE_READ8_MEMBER(debug_r);
	254	DECLARE_READ8_MEMBER(vector_r);
	255	DECLARE_WRITE8_MEMBER(firq_ack_w);
	256	DECLARE_WRITE8_MEMBER(soundcommand_w);
	257	DECLARE_READ8_MEMBER(coin_lockout_r);
	258	DECLARE_READ8_MEMBER(io_mirror_r);
	259	void blit(int offset);
246	260	};
247	261
248	262
r14845	r14846
250	264	//**************************************************************************
251	265	// MB1551x Blitter Functions
252	266
253		static void blit(halleys_state *state, int offset)
	267	void halleys_state::blit(int offset)
254	268	{
255	269	/*
256	270	The render layers can be converted to standard MAME bitmaps but
r14845	r14846
334	348	UINT16 ax; UINT8 al, ah;      // partial regs
335	349
336	350
337		param = state->m_blitter_ram + offset;
	351	param = m_blitter_ram + offset;
338	352
339	353
340	354	#if HALLEYS_DEBUG
r14845	r14846
356	370	// update sprite status
357	371	layer = (code>>3 & 2) | (code>>7 & 1);
358	372	offset >>= 4;
359		status = (stptr) ? state->m_cpu1_base[stptr] : ACTIVE;
	373	status = (stptr) ? m_cpu1_base[stptr] : ACTIVE;
360	374	flags = mode;
361	375	group = mode & GROUP;
362	376	command = code & COMMAND;
363		if (state->m_game_id == GAME_HALLEYS)
	377	if (m_game_id == GAME_HALLEYS)
364	378	{
365	379	if (!layer) flags |= PPCD_ON;
366	380	if (offset >= HALLEYS_SPLIT) flags |= AD_HIGH; else
r14845	r14846
388	402	src1 &= 0x3fff;
389	403	src2 &= 0x3fff;
390	404	bank = ((code & BANKBIT0) | (color & BANKBIT1)) << 8;
391		pal_ptr = state->m_internal_palette;
	405	pal_ptr = m_internal_palette;
392	406
393	407
394	408	// the crossroad of fate
r14845	r14846
435	449
436	450
437	451	// calculate entry points and loop constants
438		src1_ptr = state->m_gfx_plane02 + ((bank + src1)<<3) + eax;
439		src2_ptr = state->m_gfx_plane13 + ((bank + src2)<<3) + eax;
	452	src1_ptr = m_gfx_plane02 + ((bank + src1)<<3) + eax;
	453	src2_ptr = m_gfx_plane13 + ((bank + src2)<<3) + eax;
440	454
441	455	if (!(flags & (S1_IDLE | S2_IDLE)))
442	456	{
r14845	r14846
446	460	}
447	461	else src_dy = src_dx = 0;
448	462
449		dst_ptr = state->m_render_layer[layer] + dst_skip;
	463	dst_ptr = m_render_layer[layer] + dst_skip;
450	464
451	465
452	466	// look up pen values and set rendering flags
r14845	r14846
556	570	// update collision list if object collided with the other group
557	571	if (status & ACTIVE && ax & SP_COLLD)
558	572	{
559		state->m_collision_list[state->m_collision_count & (MAX_SPRITES-1)] = offset;
560		state->m_collision_count++;
	573	m_collision_list[m_collision_count & (MAX_SPRITES-1)] = offset;
	574	m_collision_count++;
561	575
562	576	#if HALLEYS_DEBUG
563		popmessage("ID:%02x CC:%3d", offset, state->m_collision_count);
	577	popmessage("ID:%02x CC:%3d", offset, m_collision_count);
564	578	#endif
565	579	}
566	580
r14845	r14846
705	719	if (flags & S1_IDLE) src_dx = 0; else src_dx = 1;
706	720	if (flags & S1_REV ) src_dx = -src_dx;
707	721
708		src_base = state->m_gfx1_base + bank;
	722	src_base = m_gfx1_base + bank;
709	723
710	724	if (command == STARPASS1 || command == STARPASS2) layer = (layer & 1) + 4;
711		dst_base = state->m_render_layer[layer];
	725	dst_base = m_render_layer[layer];
712	726
713	727
714	728	//--------------------------------------------------------------------------
r14845	r14846
732	746	if (!command && y == 0xff && h == 1)
733	747	{
734	748	y = 0; h = SCREEN_HEIGHT;
735		dst_base = state->m_render_layer[(layer&1)+4];
	749	dst_base = m_render_layer[(layer&1)+4];
736	750	WARP_WIPE_COMMON
737	751
738		state->m_stars_enabled = ~layer & 1;
	752	m_stars_enabled = ~layer & 1;
739	753	}
740	754
741	755	// wipe background and chain-wipe corresponding sprite layer when the command is zero
742	756	else
743	757	{
744	758	WARP_WIPE_COMMON
745		if (!command) { dst_base = state->m_render_layer[layer&1]; WARP_WIPE_COMMON }
	759	if (!command) { dst_base = m_render_layer[layer&1]; WARP_WIPE_COMMON }
746	760	}
747	761
748	762	} else
r14845	r14846
794	808	}
795	809	}
796	810
797		state->m_stars_enabled = layer & 1;
	811	m_stars_enabled = layer & 1;
798	812
799	813	#undef RORB
800	814	#undef C2S
r14845	r14846
862	876	if (flags & IGNORE_0) { w=8; h=8; WARP_WIPE_COMMON }
863	877
864	878	src1_ptr = src_base + src1;
865		dst_ptr = state->m_render_layer[2] + (y << SCREEN_WIDTH_L2);
	879	dst_ptr = m_render_layer[2] + (y << SCREEN_WIDTH_L2);
866	880
867	881	src1_ptr += 8;
868	882	edx = -8;
r14845	r14846
974	988
975	989
976	990	// draws Ben Bero Beh's color backdrop(verification required)
977		static WRITE8_HANDLER( bgtile_w )
	991	WRITE8_MEMBER(halleys_state::bgtile_w)
978	992	{
979		halleys_state *state = space->machine().driver_data<halleys_state>();
980	993	int yskip, xskip, ecx;
981	994	UINT16 *edi;
982	995	UINT16 ax;
983	996
984		state->m_cpu1_base[0x1f00+offset] = data;
	997	m_cpu1_base[0x1f00+offset] = data;
985	998	offset -= 0x18;
986	999
987	1000	if (offset >= 191) return;
r14845	r14846
992	1005	yskip = yskip * 48 + 24;
993	1006	xskip = xskip * 5 + 2;
994	1007
995		edi = state->m_render_layer[2] + (yskip<<SCREEN_WIDTH_L2) + xskip + (48<<SCREEN_WIDTH_L2);
	1008	edi = m_render_layer[2] + (yskip<<SCREEN_WIDTH_L2) + xskip + (48<<SCREEN_WIDTH_L2);
996	1009	ecx = -(48<<SCREEN_WIDTH_L2);
997	1010	ax = (UINT16)data | BG_RGB;
998	1011
r14845	r14846
1000	1013	}
1001	1014
1002	1015
1003		static READ8_HANDLER( blitter_status_r )
	1016	READ8_MEMBER(halleys_state::blitter_status_r)
1004	1017	{
1005		halleys_state *state = space->machine().driver_data<halleys_state>();
1006		if (state->m_game_id==GAME_HALLEYS && cpu_get_pc(&space->device())==0x8017) return(0x55); // HACK: trick SRAM test on startup
	1018	if (m_game_id==GAME_HALLEYS && cpu_get_pc(&space.device())==0x8017) return(0x55); // HACK: trick SRAM test on startup
1007	1019
1008	1020	return(0);
1009	1021	}
1010	1022
1011	1023
1012		static READ8_HANDLER( blitter_r )
	1024	READ8_MEMBER(halleys_state::blitter_r)
1013	1025	{
1014		halleys_state *state = space->machine().driver_data<halleys_state>();
1015	1026	int i = offset & 0xf;
1016	1027
1017	1028	if (i==0 || i==4) return(1);
1018	1029
1019		return(state->m_blitter_ram[offset]);
	1030	return(m_blitter_ram[offset]);
1020	1031	}
1021	1032
1022	1033
r14845	r14846
1027	1038	}
1028	1039
1029	1040
1030		static WRITE8_HANDLER( blitter_w )
	1041	WRITE8_MEMBER(halleys_state::blitter_w)
1031	1042	{
1032		halleys_state *state = space->machine().driver_data<halleys_state>();
1033	1043	int i = offset & 0xf;
1034	1044
1035		state->m_blitter_ram[offset] = data;
	1045	m_blitter_ram[offset] = data;
1036	1046
1037		if (i==0) blit(state, offset);
	1047	if (i==0) blit(offset);
1038	1048
1039		if (state->m_game_id == GAME_BENBEROB)
	1049	if (m_game_id == GAME_BENBEROB)
1040	1050	{
1041	1051	if (i==0 || (i==4 && !data))
1042	1052	{
1043		state->m_blitter_busy = 0;
1044		if (state->m_firq_level) cputag_set_input_line(space->machine(), "maincpu", M6809_FIRQ_LINE, ASSERT_LINE); // make up delayed FIRQ's
	1053	m_blitter_busy = 0;
	1054	if (m_firq_level) cputag_set_input_line(machine(), "maincpu", M6809_FIRQ_LINE, ASSERT_LINE); // make up delayed FIRQ's
1045	1055	}
1046	1056	else
1047	1057	{
1048		state->m_blitter_busy = 1;
1049		state->m_blitter_reset_timer->adjust(downcast<cpu_device *>(&space->device())->cycles_to_attotime(100)); // free blitter if no updates in 100 cycles
	1058	m_blitter_busy = 1;
	1059	m_blitter_reset_timer->adjust(downcast<cpu_device *>(&space.device())->cycles_to_attotime(100)); // free blitter if no updates in 100 cycles
1050	1060	}
1051	1061	}
1052	1062	}
1053	1063
1054	1064
1055		static READ8_HANDLER( collision_id_r )
	1065	READ8_MEMBER(halleys_state::collision_id_r)
1056	1066	{
1057		halleys_state *state = space->machine().driver_data<halleys_state>();
1058	1067	/*
1059	1068	Collision detection abstract:
1060	1069
r14845	r14846
1077	1086	UPDATE: re-implemented pixel collision to accompany the hack method.
1078	1087	*/
1079	1088
1080		if (state->m_game_id==GAME_HALLEYS && cpu_get_pc(&space->device())==state->m_collision_detection) // HACK: collision detection bypass
	1089	if (m_game_id==GAME_HALLEYS && cpu_get_pc(&space.device())==m_collision_detection) // HACK: collision detection bypass
1081	1090	{
1082		if (state->m_collision_count) { state->m_collision_count--; return(state->m_collision_list[state->m_collision_count]); }
	1091	if (m_collision_count) { m_collision_count--; return(m_collision_list[m_collision_count]); }
1083	1092
1084	1093	return(0);
1085	1094	}
1086	1095
1087		return(state->m_io_ram[0x66]);
	1096	return(m_io_ram[0x66]);
1088	1097	}
1089	1098
1090	1099
r14845	r14846
1185	1194	*b = prom_6330[0x40 + (bit0|bit1|bit2|bit3|bit4)];
1186	1195	}
1187	1196
1188		static WRITE8_HANDLER( halleys_paletteram_IIRRGGBB_w )
	1197	WRITE8_MEMBER(halleys_state::halleys_paletteram_IIRRGGBB_w)
1189	1198	{
1190		halleys_state *state = space->machine().driver_data<halleys_state>();
1191	1199	UINT32 d, r, g, b, i, j;
1192		UINT32 *pal_ptr = state->m_internal_palette;
	1200	UINT32 *pal_ptr = m_internal_palette;
1193	1201
1194		space->machine().generic.paletteram.u8[offset] = data;
	1202	machine().generic.paletteram.u8[offset] = data;
1195	1203	d = (UINT32)data;
1196	1204	j = d | BG_RGB;
1197	1205	pal_ptr[offset] = j;
r14845	r14846
1205	1213	g = d    & 0x0c; g |= i;  g = g<<4 | g;
1206	1214	b = d<<2 & 0x0c; b |= i;  b = b<<4 | b;
1207	1215
1208		palette_set_color(space->machine(), offset, MAKE_RGB(r, g, b));
1209		palette_set_color(space->machine(), offset+SP_2BACK, MAKE_RGB(r, g, b));
1210		palette_set_color(space->machine(), offset+SP_ALPHA, MAKE_RGB(r, g, b));
1211		palette_set_color(space->machine(), offset+SP_COLLD, MAKE_RGB(r, g, b));
	1216	palette_set_color(machine(), offset, MAKE_RGB(r, g, b));
	1217	palette_set_color(machine(), offset+SP_2BACK, MAKE_RGB(r, g, b));
	1218	palette_set_color(machine(), offset+SP_ALPHA, MAKE_RGB(r, g, b));
	1219	palette_set_color(machine(), offset+SP_COLLD, MAKE_RGB(r, g, b));
1212	1220
1213		halleys_decode_rgb(space->machine(), &r, &g, &b, offset, 0);
1214		palette_set_color(space->machine(), offset+0x20, MAKE_RGB(r, g, b));
	1221	halleys_decode_rgb(machine(), &r, &g, &b, offset, 0);
	1222	palette_set_color(machine(), offset+0x20, MAKE_RGB(r, g, b));
1215	1223	}
1216	1224
1217	1225
r14845	r14846
1513	1521
1514	1522	#if HALLEYS_DEBUG
1515	1523
1516		static READ8_HANDLER( zero_r ) { return(0); }
	1524	READ8_MEMBER(halleys_state::zero_r){ return(0); }
1517	1525
1518		static READ8_HANDLER( debug_r )
	1526	READ8_MEMBER(halleys_state::debug_r)
1519	1527	{
1520		halleys_state *state = space->machine().driver_data<halleys_state>();
1521		return(state->m_io_ram[offset]);
	1528	return(m_io_ram[offset]);
1522	1529	}
1523	1530
1524	1531	#endif
r14845	r14846
1582	1589	}
1583	1590
1584	1591
1585		static READ8_HANDLER( vector_r )
	1592	READ8_MEMBER(halleys_state::vector_r)
1586	1593	{
1587		halleys_state *state = space->machine().driver_data<halleys_state>();
1588		return(state->m_cpu1_base[0xffe0 + (offset^(state->m_mVectorType<<4))]);
	1594	return(m_cpu1_base[0xffe0 + (offset^(m_mVectorType<<4))]);
1589	1595	}
1590	1596
1591	1597
1592		static WRITE8_HANDLER( firq_ack_w )
	1598	WRITE8_MEMBER(halleys_state::firq_ack_w)
1593	1599	{
1594		halleys_state *state = space->machine().driver_data<halleys_state>();
1595		state->m_io_ram[0x9c] = data;
	1600	m_io_ram[0x9c] = data;
1596	1601
1597		if (state->m_firq_level) state->m_firq_level--;
1598		cputag_set_input_line(space->machine(), "maincpu", M6809_FIRQ_LINE, CLEAR_LINE);
	1602	if (m_firq_level) m_firq_level--;
	1603	cputag_set_input_line(machine(), "maincpu", M6809_FIRQ_LINE, CLEAR_LINE);
1599	1604	}
1600	1605
1601	1606
r14845	r14846
1606	1611	}
1607	1612
1608	1613
1609		static WRITE8_HANDLER( soundcommand_w )
	1614	WRITE8_MEMBER(halleys_state::soundcommand_w)
1610	1615	{
1611		halleys_state *state = space->machine().driver_data<halleys_state>();
1612	1616
1613		state->m_io_ram[0x8a] = data;
	1617	m_io_ram[0x8a] = data;
1614	1618	soundlatch_w(space,offset,data);
1615		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_NMI, PULSE_LINE);
	1619	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_NMI, PULSE_LINE);
1616	1620	}
1617	1621
1618	1622
1619		static READ8_HANDLER( coin_lockout_r )
	1623	READ8_MEMBER(halleys_state::coin_lockout_r)
1620	1624	{
1621	1625	// This is a hack, but it lets you coin up when COIN1 or COIN2 are signaled.
1622	1626	// See NMI for the twisted logic that is involved in handling coin input :
1623	1627	//   0x8599 : 'benberob'
1624	1628	//   0x83e2 : 'halleys', 'halleysc', 'halleycj'
1625	1629	//   0x83df : 'halley87'
1626		int inp = input_port_read(space->machine(), "IN0");
1627		int result = ((input_port_read(space->machine(), "DSW4")) & 0x20) >> 5;
	1630	int inp = input_port_read(machine(), "IN0");
	1631	int result = ((input_port_read(machine(), "DSW4")) & 0x20) >> 5;
1628	1632
1629	1633	if (inp & 0x80) result |= 0x02;
1630	1634	if (inp & 0x40) result |= 0x04;
r14845	r14846
1633	1637	}
1634	1638
1635	1639
1636		static READ8_HANDLER( io_mirror_r )
	1640	READ8_MEMBER(halleys_state::io_mirror_r)
1637	1641	{
1638	1642	static const char *const portnames[] = { "IN0", "IN1", "IN2", "IN3" };
1639	1643
1640		return input_port_read(space->machine(), portnames[offset]);
	1644	return input_port_read(machine(), portnames[offset]);
1641	1645	}
1642	1646
1643	1647
r14845	r14846
1645	1649	// Memory Maps
1646	1650
1647	1651	static ADDRESS_MAP_START( halleys_map, AS_PROGRAM, 8, halleys_state )
1648		AM_RANGE(0x0000, 0x0fff) AM_READWRITE_LEGACY(blitter_r, blitter_w) AM_BASE(m_blitter_ram) AM_SIZE(m_blitter_ramsize)
1649		AM_RANGE(0x1f00, 0x1fff) AM_WRITE_LEGACY(bgtile_w)      // background tiles?(Ben Bero Beh only)
	1652	AM_RANGE(0x0000, 0x0fff) AM_READWRITE(blitter_r, blitter_w) AM_BASE(m_blitter_ram) AM_SIZE(m_blitter_ramsize)
	1653	AM_RANGE(0x1f00, 0x1fff) AM_WRITE(bgtile_w)      // background tiles?(Ben Bero Beh only)
1650	1654	AM_RANGE(0x1000, 0xefff) AM_ROM
1651	1655	AM_RANGE(0xf000, 0xfeff) AM_RAM               // work ram
1652	1656
1653		AM_RANGE(0xff66, 0xff66) AM_READ_LEGACY(collision_id_r) // HACK: collision detection bypass(Halley's Comet only)
1654		AM_RANGE(0xff71, 0xff71) AM_READ_LEGACY(blitter_status_r)
1655		AM_RANGE(0xff80, 0xff83) AM_READ_LEGACY(io_mirror_r)
1656		AM_RANGE(0xff8a, 0xff8a) AM_WRITE_LEGACY(soundcommand_w)
	1657	AM_RANGE(0xff66, 0xff66) AM_READ(collision_id_r) // HACK: collision detection bypass(Halley's Comet only)
	1658	AM_RANGE(0xff71, 0xff71) AM_READ(blitter_status_r)
	1659	AM_RANGE(0xff80, 0xff83) AM_READ(io_mirror_r)
	1660	AM_RANGE(0xff8a, 0xff8a) AM_WRITE(soundcommand_w)
1657	1661	AM_RANGE(0xff90, 0xff90) AM_READ_PORT("IN0")   // coin/start
1658	1662	AM_RANGE(0xff91, 0xff91) AM_READ_PORT("IN1")   // player 1
1659	1663	AM_RANGE(0xff92, 0xff92) AM_READ_PORT("IN2")   // player 2
1660	1664	AM_RANGE(0xff93, 0xff93) AM_READ_PORT("IN3")   // unused?
1661		AM_RANGE(0xff94, 0xff94) AM_READ_LEGACY(coin_lockout_r)
	1665	AM_RANGE(0xff94, 0xff94) AM_READ(coin_lockout_r)
1662	1666	AM_RANGE(0xff95, 0xff95) AM_READ_PORT("DSW1")   // dipswitch 4
1663	1667	AM_RANGE(0xff96, 0xff96) AM_READ_PORT("DSW2")   // dipswitch 3
1664	1668	AM_RANGE(0xff97, 0xff97) AM_READ_PORT("DSW3")   // dipswitch 2
1665		AM_RANGE(0xff9c, 0xff9c) AM_WRITE_LEGACY(firq_ack_w)
	1669	AM_RANGE(0xff9c, 0xff9c) AM_WRITE(firq_ack_w)
1666	1670	AM_RANGE(0xff00, 0xffbf) AM_RAM AM_BASE(m_io_ram) AM_SIZE(m_io_ramsize)   // I/O write fall-through
1667	1671
1668		AM_RANGE(0xffc0, 0xffdf) AM_RAM_WRITE_LEGACY(halleys_paletteram_IIRRGGBB_w) AM_BASE_GENERIC(paletteram)
1669		AM_RANGE(0xffe0, 0xffff) AM_READ_LEGACY(vector_r)
	1672	AM_RANGE(0xffc0, 0xffdf) AM_RAM_WRITE(halleys_paletteram_IIRRGGBB_w) AM_BASE_GENERIC(paletteram)
	1673	AM_RANGE(0xffe0, 0xffff) AM_READ(vector_r)
1670	1674	ADDRESS_MAP_END
1671	1675
1672	1676

src/mame/drivers/statriv2.c

r14845	r14846
90	90	UINT8 m_question_offset_high;
91	91	UINT8 m_latched_coin;
92	92	UINT8 m_last_coin;
	93	DECLARE_WRITE8_MEMBER(statriv2_videoram_w);
	94	DECLARE_READ8_MEMBER(question_data_r);
	95	DECLARE_READ8_MEMBER(laserdisc_io_r);
	96	DECLARE_WRITE8_MEMBER(laserdisc_io_w);
93	97	};
94	98
95	99
r14845	r14846
161	165	*
162	166	*************************************/
163	167
164		static WRITE8_HANDLER( statriv2_videoram_w )
	168	WRITE8_MEMBER(statriv2_state::statriv2_videoram_w)
165	169	{
166		statriv2_state *state = space->machine().driver_data<statriv2_state>();
167		UINT8 *videoram = state->m_videoram;
	170	UINT8 *videoram = m_videoram;
168	171	videoram[offset] = data;
169		state->m_tilemap->mark_tile_dirty(offset & 0x3ff);
	172	m_tilemap->mark_tile_dirty(offset & 0x3ff);
170	173	}
171	174
172	175
r14845	r14846
216	219	*
217	220	*************************************/
218	221
219		static READ8_HANDLER( question_data_r )
	222	READ8_MEMBER(statriv2_state::question_data_r)
220	223	{
221		statriv2_state *state = space->machine().driver_data<statriv2_state>();
222		const UINT8 *qrom = space->machine().region("questions")->base();
223		UINT32 qromsize = space->machine().region("questions")->bytes();
	224	const UINT8 *qrom = machine().region("questions")->base();
	225	UINT32 qromsize = machine().region("questions")->bytes();
224	226	UINT32 address;
225	227
226		if (state->m_question_offset_high == 0xff)
227		state->m_question_offset[state->m_question_offset_low]++;
	228	if (m_question_offset_high == 0xff)
	229	m_question_offset[m_question_offset_low]++;
228	230
229		address = state->m_question_offset[state->m_question_offset_low];
230		address |= state->m_question_offset[state->m_question_offset_mid] << 8;
231		if (state->m_question_offset_high != 0xff)
232		address |= state->m_question_offset[state->m_question_offset_high] << 16;
	231	address = m_question_offset[m_question_offset_low];
	232	address |= m_question_offset[m_question_offset_mid] << 8;
	233	if (m_question_offset_high != 0xff)
	234	address |= m_question_offset[m_question_offset_high] << 16;
233	235
234	236	return (address < qromsize) ? qrom[address] : 0xff;
235	237	}
r14845	r14846
292	294	AM_RANGE(0x0000, 0x3fff) AM_ROM
293	295	AM_RANGE(0x4000, 0x43ff) AM_RAM
294	296	AM_RANGE(0x4800, 0x48ff) AM_RAM AM_SHARE("nvram")
295		AM_RANGE(0xc800, 0xcfff) AM_RAM_WRITE_LEGACY(statriv2_videoram_w) AM_BASE(m_videoram)
	297	AM_RANGE(0xc800, 0xcfff) AM_RAM_WRITE(statriv2_videoram_w) AM_BASE(m_videoram)
296	298	ADDRESS_MAP_END
297	299
298	300	static ADDRESS_MAP_START( statriv2_io_map, AS_IO, 8, statriv2_state )
299	301	AM_RANGE(0x20, 0x23) AM_DEVREADWRITE_LEGACY("ppi", ppi8255_r, ppi8255_w)
300		AM_RANGE(0x28, 0x2b) AM_READ_LEGACY(question_data_r) AM_WRITEONLY AM_BASE(m_question_offset)
	302	AM_RANGE(0x28, 0x2b) AM_READ(question_data_r) AM_WRITEONLY AM_BASE(m_question_offset)
301	303	AM_RANGE(0xb0, 0xb1) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
302	304	AM_RANGE(0xb1, 0xb1) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
303	305	AM_RANGE(0xc0, 0xcf) AM_DEVREADWRITE_LEGACY("tms", tms9927_r, tms9927_w)
r14845	r14846
1109	1111	}
1110	1112
1111	1113
1112		static READ8_HANDLER( laserdisc_io_r )
	1114	READ8_MEMBER(statriv2_state::laserdisc_io_r)
1113	1115	{
1114	1116	UINT8 result = 0x00;
1115	1117	if (offset == 1)
1116	1118	result = 0x18;
1117		mame_printf_debug("%s:ld read ($%02X) = %02X\n", space->machine().describe_context(), 0x28 + offset, result);
	1119	mame_printf_debug("%s:ld read ($%02X) = %02X\n", machine().describe_context(), 0x28 + offset, result);
1118	1120	return result;
1119	1121	}
1120	1122
1121		static WRITE8_HANDLER( laserdisc_io_w )
	1123	WRITE8_MEMBER(statriv2_state::laserdisc_io_w)
1122	1124	{
1123		mame_printf_debug("%s:ld write ($%02X) = %02X\n", space->machine().describe_context(), 0x28 + offset, data);
	1125	mame_printf_debug("%s:ld write ($%02X) = %02X\n", machine().describe_context(), 0x28 + offset, data);
1124	1126	}
1125	1127
1126	1128	static DRIVER_INIT( laserdisc )
1127	1129	{
1128	1130	address_space *iospace = machine.device("maincpu")->memory().space(AS_IO);
1129		iospace->install_legacy_readwrite_handler(0x28, 0x2b, FUNC(laserdisc_io_r), FUNC(laserdisc_io_w));
	1131	statriv2_state *state = machine.driver_data<statriv2_state>();
	1132	iospace->install_readwrite_handler(0x28, 0x2b, read8_delegate(FUNC(statriv2_state::laserdisc_io_r), state), write8_delegate(FUNC(statriv2_state::laserdisc_io_w), state));
1130	1133	}
1131	1134
1132	1135

src/mame/drivers/d9final.c

r14845	r14846
34	34	UINT8 *m_hi_vram;
35	35	UINT8 *m_cram;
36	36	tilemap_t *m_sc0_tilemap;
	37	DECLARE_WRITE8_MEMBER(sc0_lovram);
	38	DECLARE_WRITE8_MEMBER(sc0_hivram);
	39	DECLARE_WRITE8_MEMBER(sc0_cram);
	40	DECLARE_WRITE8_MEMBER(d9final_bank_w);
	41	DECLARE_READ8_MEMBER(prot_latch_r);
37	42	};
38	43
39	44
r14845	r14846
64	69	return 0;
65	70	}
66	71
67		static WRITE8_HANDLER( sc0_lovram )
	72	WRITE8_MEMBER(d9final_state::sc0_lovram)
68	73	{
69		d9final_state *state = space->machine().driver_data<d9final_state>();
70		state->m_lo_vram[offset] = data;
71		state->m_sc0_tilemap->mark_tile_dirty(offset);
	74	m_lo_vram[offset] = data;
	75	m_sc0_tilemap->mark_tile_dirty(offset);
72	76	}
73	77
74		static WRITE8_HANDLER( sc0_hivram )
	78	WRITE8_MEMBER(d9final_state::sc0_hivram)
75	79	{
76		d9final_state *state = space->machine().driver_data<d9final_state>();
77		state->m_hi_vram[offset] = data;
78		state->m_sc0_tilemap->mark_tile_dirty(offset);
	80	m_hi_vram[offset] = data;
	81	m_sc0_tilemap->mark_tile_dirty(offset);
79	82	}
80	83
81		static WRITE8_HANDLER( sc0_cram )
	84	WRITE8_MEMBER(d9final_state::sc0_cram)
82	85	{
83		d9final_state *state = space->machine().driver_data<d9final_state>();
84		state->m_cram[offset] = data;
85		state->m_sc0_tilemap->mark_tile_dirty(offset);
	86	m_cram[offset] = data;
	87	m_sc0_tilemap->mark_tile_dirty(offset);
86	88	}
87	89
88		static WRITE8_HANDLER( d9final_bank_w )
	90	WRITE8_MEMBER(d9final_state::d9final_bank_w)
89	91	{
90		UINT8 *ROM = space->machine().region("maincpu")->base();
	92	UINT8 *ROM = machine().region("maincpu")->base();
91	93	UINT32 bankaddress;
92	94
93	95	bankaddress = 0x10000+(0x4000 * (data & 0x7));
94		memory_set_bankptr(space->machine(), "bank1", &ROM[bankaddress]);
	96	memory_set_bankptr(machine(), "bank1", &ROM[bankaddress]);
95	97	}
96	98
97	99	/* game checks this after three attract cycles, otherwise coin inputs stop to work. */
98		static READ8_HANDLER( prot_latch_r )
	100	READ8_MEMBER(d9final_state::prot_latch_r)
99	101	{
100		//  printf("PC=%06x\n",cpu_get_pc(&space->device()));
	102	//  printf("PC=%06x\n",cpu_get_pc(&space.device()));
101	103
102	104	return 0x04;
103	105	}
r14845	r14846
109	111	AM_RANGE(0xc000, 0xc7ff) AM_RAM
110	112	AM_RANGE(0xc800, 0xcbff) AM_RAM_WRITE_LEGACY(paletteram_xxxxBBBBRRRRGGGG_split1_w) AM_BASE_GENERIC(paletteram)
111	113	AM_RANGE(0xcc00, 0xcfff) AM_RAM_WRITE_LEGACY(paletteram_xxxxBBBBRRRRGGGG_split2_w) AM_BASE_GENERIC(paletteram2)
112		AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE_LEGACY(sc0_lovram) AM_BASE(m_lo_vram)
113		AM_RANGE(0xd800, 0xdfff) AM_RAM_WRITE_LEGACY(sc0_hivram) AM_BASE(m_hi_vram)
114		AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE_LEGACY(sc0_cram) AM_BASE(m_cram)
115		AM_RANGE(0xf000, 0xf000) AM_READ_LEGACY(prot_latch_r)
	114	AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE(sc0_lovram) AM_BASE(m_lo_vram)
	115	AM_RANGE(0xd800, 0xdfff) AM_RAM_WRITE(sc0_hivram) AM_BASE(m_hi_vram)
	116	AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE(sc0_cram) AM_BASE(m_cram)
	117	AM_RANGE(0xf000, 0xf000) AM_READ(prot_latch_r)
116	118	ADDRESS_MAP_END
117	119
118	120	static ADDRESS_MAP_START( d9final_io, AS_IO, 8, d9final_state )
r14845	r14846
124	126	AM_RANGE(0x40, 0x41) AM_DEVWRITE_LEGACY("ymsnd",ym2413_w)
125	127	AM_RANGE(0x60, 0x60) AM_READ_PORT("DSWD")
126	128	AM_RANGE(0x80, 0x80) AM_READ_PORT("IN0")
127		AM_RANGE(0xa0, 0xa0) AM_READ_PORT("IN1") AM_WRITE_LEGACY(d9final_bank_w)
	129	AM_RANGE(0xa0, 0xa0) AM_READ_PORT("IN1") AM_WRITE(d9final_bank_w)
128	130	AM_RANGE(0xe0, 0xe0) AM_READ_PORT("IN2")
129	131	ADDRESS_MAP_END
130	132

src/mame/drivers/ttchamp.c

r14845	r14846
53	53
54	54	UINT16 *m_peno_vram;
55	55	UINT16 m_paloff;
	56	DECLARE_WRITE16_MEMBER(paloff_w);
	57	DECLARE_WRITE16_MEMBER(pcup_prgbank_w);
	58	DECLARE_WRITE16_MEMBER(paldat_w);
	59	DECLARE_READ16_MEMBER(peno_rand);
	60	DECLARE_READ16_MEMBER(peno_rand2);
56	61	};
57	62
58	63
r14845	r14846
93	98	}
94	99
95	100
96		static WRITE16_HANDLER( paloff_w )
	101	WRITE16_MEMBER(ttchamp_state::paloff_w)
97	102	{
98		ttchamp_state *state = space->machine().driver_data<ttchamp_state>();
99		COMBINE_DATA(&state->m_paloff);
	103	COMBINE_DATA(&m_paloff);
100	104	}
101	105
102	106	#ifdef UNUSED_FUNCTION
103		static WRITE16_HANDLER( pcup_prgbank_w )
	107	WRITE16_MEMBER(ttchamp_state::pcup_prgbank_w)
104	108	{
105	109	int bank;
106		UINT8 *ROM1 = space->machine().region("user1")->base();
	110	UINT8 *ROM1 = machine().region("user1")->base();
107	111
108	112	if (ACCESSING_BITS_0_7)
109	113	{
110	114	bank = (data>>4) &0x07;
111		memory_set_bankptr(space->machine(), "bank2",&ROM1[0x80000*(bank)]);
	115	memory_set_bankptr(machine(), "bank2",&ROM1[0x80000*(bank)]);
112	116	}
113	117	}
114	118	#endif
115	119
116		static WRITE16_HANDLER( paldat_w )
	120	WRITE16_MEMBER(ttchamp_state::paldat_w)
117	121	{
118		ttchamp_state *state = space->machine().driver_data<ttchamp_state>();
119		palette_set_color_rgb(space->machine(),state->m_paloff & 0x7fff,pal5bit(data>>0),pal5bit(data>>5),pal5bit(data>>10));
	122	palette_set_color_rgb(machine(),m_paloff & 0x7fff,pal5bit(data>>0),pal5bit(data>>5),pal5bit(data>>10));
120	123	}
121	124
122		static READ16_HANDLER( peno_rand )
	125	READ16_MEMBER(ttchamp_state::peno_rand)
123	126	{
124		return 0xffff;// space->machine().rand();
	127	return 0xffff;// machine().rand();
125	128	}
126	129
127	130	#ifdef UNUSED_FUNCTION
128		static READ16_HANDLER( peno_rand2 )
	131	READ16_MEMBER(ttchamp_state::peno_rand2)
129	132	{
130		return space->machine().rand();
	133	return machine().rand();
131	134	}
132	135	#endif
133	136
r14845	r14846
144	147	AM_RANGE(0x0002, 0x0003) AM_READ_PORT("SYSTEM")
145	148	AM_RANGE(0x0004, 0x0005) AM_READ_PORT("P1_P2")
146	149
147		//  AM_RANGE(0x0018, 0x0019) AM_READ_LEGACY(peno_rand2)
148		//  AM_RANGE(0x001e, 0x001f) AM_READ_LEGACY(peno_rand2)
	150	//  AM_RANGE(0x0018, 0x0019) AM_READ(peno_rand2)
	151	//  AM_RANGE(0x001e, 0x001f) AM_READ(peno_rand2)
149	152
150		AM_RANGE(0x0008, 0x0009) AM_WRITE_LEGACY(paldat_w)
151		AM_RANGE(0x000a, 0x000b) AM_WRITE_LEGACY(paloff_w)
	153	AM_RANGE(0x0008, 0x0009) AM_WRITE(paldat_w)
	154	AM_RANGE(0x000a, 0x000b) AM_WRITE(paloff_w)
152	155
153		//  AM_RANGE(0x0010, 0x0010) AM_WRITE_LEGACY(pcup_prgbank_w)
	156	//  AM_RANGE(0x0010, 0x0010) AM_WRITE(pcup_prgbank_w)
154	157	AM_RANGE(0x0010, 0x0011) AM_WRITENOP
155	158
156	159	AM_RANGE(0x0020, 0x0021) AM_WRITENOP
157	160
158		AM_RANGE(0x0034, 0x0035) AM_READ_LEGACY(peno_rand) AM_WRITENOP
	161	AM_RANGE(0x0034, 0x0035) AM_READ(peno_rand) AM_WRITENOP
159	162	ADDRESS_MAP_END
160	163
161	164

src/mame/drivers/aristmk6.c

r14845	r14846
20	20
21	21	UINT32 m_test_x,m_test_y,m_start_offs;
22	22	UINT8 m_type;
	23	DECLARE_READ64_MEMBER(test_r);
23	24	};
24	25
25	26
r14845	r14846
108	109	return 0;
109	110	}
110	111
111		static READ64_HANDLER( test_r )
	112	READ64_MEMBER(aristmk6_state::test_r)
112	113	{
113	114	// bit 1 read in various places, status for something ...
114	115	return -1;
r14845	r14846
117	118	static ADDRESS_MAP_START( aristmk6_map, AS_PROGRAM, 64, aristmk6_state )
118	119	AM_RANGE(0x00000000, 0x003fffff) AM_ROM AM_REGION("maincpu", 0)
119	120	AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM // work ram
120		AM_RANGE(0x13800000, 0x13800007) AM_READ_LEGACY(test_r)
	121	AM_RANGE(0x13800000, 0x13800007) AM_READ(test_r)
121	122	ADDRESS_MAP_END
122	123
123	124	static ADDRESS_MAP_START( aristmk6_port, AS_IO, 64, aristmk6_state )

src/mame/drivers/gottlieb.c

r14845	r14846
1750	1750	MACHINE_CONFIG_END
1751	1751
1752	1752
1753		static MACHINE_CONFIG_DERIVED( gottlieb1_votrax, gottlieb_core )
1754		MCFG_GOTTLIEB_SOUND_R1_ADD_VOTRAX("r1sound")
1755		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1756		MACHINE_CONFIG_END
1757
1758
1759	1753	static MACHINE_CONFIG_DERIVED( gottlieb2, gottlieb_core )
1760	1754	MCFG_GOTTLIEB_SOUND_R2_ADD("r2sound")
1761	1755	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
r14845	r14846
1802	1796	MCFG_FRAGMENT_ADD(qbert_samples)
1803	1797	MACHINE_CONFIG_END
1804	1798
	1799
	1800	static MACHINE_CONFIG_DERIVED( tylz, gottlieb1 )
	1801	MCFG_FRAGMENT_ADD(qbert_samples)
	1802	MACHINE_CONFIG_END
	1803
	1804
1805	1805	#else
1806	1806
	1807
	1808	static MACHINE_CONFIG_DERIVED( gottlieb1_votrax, gottlieb_core )
	1809	MCFG_GOTTLIEB_SOUND_R1_ADD_VOTRAX("r1sound")
	1810	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	1811	MACHINE_CONFIG_END
	1812
	1813
1807	1814	static MACHINE_CONFIG_DERIVED( reactor, gottlieb1_votrax )
1808	1815
1809	1816	/* basic machine hardware */
r14845	r14846
1817	1824	static MACHINE_CONFIG_DERIVED( qbert, gottlieb1_votrax )
1818	1825	MACHINE_CONFIG_END
1819	1826
	1827
	1828	static MACHINE_CONFIG_DERIVED( tylz, gottlieb1_votrax )
	1829	MACHINE_CONFIG_END
	1830
	1831
1820	1832	#endif
1821	1833
1822	1834
r14845	r14846
2492	2504	GAME( 1982, qberttst,  qbert,    qbert,          qbert,    romtiles, ROT270, "Gottlieb", "Q*bert (early test version)", GAME_IMPERFECT_SOUND )
2493	2505	GAME( 1982, qbtrktst,  qbert,    qbert,          qbert,    romtiles, ROT270, "Gottlieb", "Q*bert Board Input Test Rom", GAME_IMPERFECT_SOUND )
2494	2506	GAME( 1982, insector,  0,        gottlieb1,       insector, romtiles, ROT0,   "Gottlieb", "Insector (prototype)", 0 )
2495		GAME( 1982, tylz,      0,        gottlieb1_votrax,   tylz,     romtiles, ROT0,   "Mylstar",  "Tylz (prototype)", GAME_IMPERFECT_SOUND ) // modified sound hw?
	2507	GAME( 1982, tylz,      0,        tylz,   tylz,     romtiles, ROT0,   "Mylstar",  "Tylz (prototype)", GAME_IMPERFECT_SOUND ) // modified sound hw?
2496	2508	GAME( 1984, argusg,    0,        gottlieb1,       argusg,   ramtiles, ROT0,   "Gottlieb", "Argus (Gottlieb, prototype)" , 0) // aka Guardian / Protector?
2497	2509	GAME( 1983, mplanets,  0,        gottlieb1,       mplanets, romtiles, ROT270, "Gottlieb", "Mad Planets", 0 )
2498	2510	GAME( 1983, mplanetsuk,mplanets, gottlieb1,       mplanets, romtiles, ROT270, "Gottlieb (Taitel license)", "Mad Planets (UK)", 0 )

src/mame/drivers/psattack.c

r14845	r14846
85	85	psattack_state(const machine_config &mconfig, device_type type, const char *tag)
86	86	: driver_device(mconfig, type, tag) { }
87	87
	88	DECLARE_READ32_MEMBER(psattack_unk_r);
88	89	};
89	90
90	91
91		static READ32_HANDLER( psattack_unk_r )
	92	READ32_MEMBER(psattack_state::psattack_unk_r)
92	93	{
93	94	return 0xffffffff;
94	95	}
95	96
96	97	static ADDRESS_MAP_START( psattack_mem, AS_PROGRAM, 32, psattack_state )
97	98	AM_RANGE(0x00000000, 0x001fffff) AM_ROM
98		AM_RANGE(0x01402204, 0x01402207) AM_READ_LEGACY(psattack_unk_r)
99		AM_RANGE(0x01402804, 0x01402807) AM_READ_LEGACY(psattack_unk_r)
	99	AM_RANGE(0x01402204, 0x01402207) AM_READ(psattack_unk_r)
	100	AM_RANGE(0x01402804, 0x01402807) AM_READ(psattack_unk_r)
100	101
101	102
102	103	AM_RANGE(0x02000000, 0x027fffff) AM_RAM

src/mame/drivers/acommand.c

r14845	r14846
78	78	UINT16 m_ufo_sw2;
79	79	UINT16 *m_spriteram;
80	80	size_t m_spriteram_size;
	81	DECLARE_WRITE16_MEMBER(ac_bgvram_w);
	82	DECLARE_WRITE16_MEMBER(ac_txvram_w);
	83	DECLARE_WRITE16_MEMBER(ac_bgscroll_w);
	84	DECLARE_WRITE16_MEMBER(ac_txscroll_w);
	85	DECLARE_READ16_MEMBER(ac_devices_r);
	86	DECLARE_WRITE16_MEMBER(ac_devices_w);
	87	DECLARE_WRITE16_MEMBER(ac_unk2_w);
81	88	};
82	89
83	90
r14845	r14846
257	264	}
258	265
259	266
260		static WRITE16_HANDLER( ac_bgvram_w )
	267	WRITE16_MEMBER(acommand_state::ac_bgvram_w)
261	268	{
262		acommand_state *state = space->machine().driver_data<acommand_state>();
263		COMBINE_DATA(&state->m_ac_bgvram[offset]);
264		state->m_bg_tilemap->mark_tile_dirty(offset);
	269	COMBINE_DATA(&m_ac_bgvram[offset]);
	270	m_bg_tilemap->mark_tile_dirty(offset);
265	271	}
266	272
267		static WRITE16_HANDLER( ac_txvram_w )
	273	WRITE16_MEMBER(acommand_state::ac_txvram_w)
268	274	{
269		acommand_state *state = space->machine().driver_data<acommand_state>();
270		COMBINE_DATA(&state->m_ac_txvram[offset]);
271		state->m_tx_tilemap->mark_tile_dirty(offset);
	275	COMBINE_DATA(&m_ac_txvram[offset]);
	276	m_tx_tilemap->mark_tile_dirty(offset);
272	277	}
273	278
274		static WRITE16_HANDLER(ac_bgscroll_w)
	279	WRITE16_MEMBER(acommand_state::ac_bgscroll_w)
275	280	{
276		acommand_state *state = space->machine().driver_data<acommand_state>();
277	281	switch(offset)
278	282	{
279		case 0: state->m_bg_tilemap->set_scrollx(0,data); break;
280		case 1: state->m_bg_tilemap->set_scrolly(0,data); break;
	283	case 0: m_bg_tilemap->set_scrollx(0,data); break;
	284	case 1: m_bg_tilemap->set_scrolly(0,data); break;
281	285	case 2: /*BG_TILEMAP priority?*/ break;
282	286	}
283	287	}
284	288
285		static WRITE16_HANDLER(ac_txscroll_w)
	289	WRITE16_MEMBER(acommand_state::ac_txscroll_w)
286	290	{
287		acommand_state *state = space->machine().driver_data<acommand_state>();
288	291	switch(offset)
289	292	{
290		case 0: state->m_tx_tilemap->set_scrollx(0,data); break;
291		case 1: state->m_tx_tilemap->set_scrolly(0,data); break;
	293	case 0: m_tx_tilemap->set_scrollx(0,data); break;
	294	case 1: m_tx_tilemap->set_scrolly(0,data); break;
292	295	case 2: /*TX_TILEMAP priority?*/ break;
293	296	}
294	297	}
r14845	r14846
296	299	/******************************************************************************************/
297	300
298	301
299		static READ16_HANDLER(ac_devices_r)
	302	READ16_MEMBER(acommand_state::ac_devices_r)
300	303	{
301		acommand_state *state = space->machine().driver_data<acommand_state>();
302		logerror("(PC=%06x) read at %04x\n",cpu_get_pc(&space->device()),offset*2);
	304	logerror("(PC=%06x) read at %04x\n",cpu_get_pc(&space.device()),offset*2);
303	305
304	306	switch(offset)
305	307	{
r14845	r14846
316	318	---- ---- ---- --x- (Activate Test)
317	319	---- ---- ---- ---x (Advance through Tests)
318	320	*/
319		return input_port_read(space->machine(), "IN0");
	321	return input_port_read(machine(), "IN0");
320	322	case 0x0014/2:
321	323	case 0x0016/2:
322		return space->machine().device<okim6295_device>("oki1")->read(*space,0);
	324	return machine().device<okim6295_device>("oki1")->read(*&space,0);
323	325	case 0x0018/2:
324	326	case 0x001a/2:
325		return space->machine().device<okim6295_device>("oki2")->read(*space,0);
	327	return machine().device<okim6295_device>("oki2")->read(*&space,0);
326	328	case 0x0040/2:
327	329	/*
328	330	"Upper switch / Under Switch"
r14845	r14846
340	342	*/
341	343	//22dc8
342	344	{
343		state->m_ufo_sw1 = state->m_ac_devram[offset] & 3;
344		if(state->m_ac_devram[offset] & 0x10)
345		state->m_ufo_sw1|= 0x10;
346		if(state->m_ac_devram[offset] & 0x40)
347		state->m_ufo_sw1|= 0x20;
348		if(state->m_ac_devram[offset] & 0x100)
349		state->m_ufo_sw1|=0x100;
350		if(state->m_ac_devram[offset] & 0x400)
351		state->m_ufo_sw1|=0x200;
352		if(state->m_ac_devram[offset] & 0x1000)
353		state->m_ufo_sw1|=0x1000;
354		if(state->m_ac_devram[offset] & 0x4000)
355		state->m_ufo_sw1|=0x2000;
356		//          if(state->m_ac_devram[0x0048/2] & 0x0001)
357		//              state->m_ufo_sw1|=0x0040;
358		//          if(state->m_ac_devram[0x0048/2] & 0x0004)
359		//              state->m_ufo_sw1|=0x0400;
360		//          if(state->m_ac_devram[0x0048/2] & 0x0100)
361		//              state->m_ufo_sw1|=0x4000;
362		return state->m_ufo_sw1;
	345	m_ufo_sw1 = m_ac_devram[offset] & 3;
	346	if(m_ac_devram[offset] & 0x10)
	347	m_ufo_sw1|= 0x10;
	348	if(m_ac_devram[offset] & 0x40)
	349	m_ufo_sw1|= 0x20;
	350	if(m_ac_devram[offset] & 0x100)
	351	m_ufo_sw1|=0x100;
	352	if(m_ac_devram[offset] & 0x400)
	353	m_ufo_sw1|=0x200;
	354	if(m_ac_devram[offset] & 0x1000)
	355	m_ufo_sw1|=0x1000;
	356	if(m_ac_devram[offset] & 0x4000)
	357	m_ufo_sw1|=0x2000;
	358	//          if(m_ac_devram[0x0048/2] & 0x0001)
	359	//              m_ufo_sw1|=0x0040;
	360	//          if(m_ac_devram[0x0048/2] & 0x0004)
	361	//              m_ufo_sw1|=0x0400;
	362	//          if(m_ac_devram[0x0048/2] & 0x0100)
	363	//              m_ufo_sw1|=0x4000;
	364	return m_ufo_sw1;
363	365	}
364	366	case 0x0044/2:
365	367	/*
r14845	r14846
369	371	---- ---- ---- ---x Upper Switch - 4 (active low)
370	372	*/
371	373	{
372		state->m_ufo_sw2 = 0;
373		if(state->m_ac_devram[offset] & 0x01)
374		state->m_ufo_sw2|= 1;
375		if(state->m_ac_devram[offset] & 0x04)
376		state->m_ufo_sw2|= 2;
377		if(state->m_ac_devram[offset] & 0x10)
378		state->m_ufo_sw2|=0x10;
379		if(state->m_ac_devram[offset] & 0x40)
380		state->m_ufo_sw2|=0x20;
381		return state->m_ufo_sw2;
	374	m_ufo_sw2 = 0;
	375	if(m_ac_devram[offset] & 0x01)
	376	m_ufo_sw2|= 1;
	377	if(m_ac_devram[offset] & 0x04)
	378	m_ufo_sw2|= 2;
	379	if(m_ac_devram[offset] & 0x10)
	380	m_ufo_sw2|=0x10;
	381	if(m_ac_devram[offset] & 0x40)
	382	m_ufo_sw2|=0x20;
	383	return m_ufo_sw2;
382	384	}
383	385	case 0x0048/2:
384		return state->m_ac_devram[offset];
	386	return m_ac_devram[offset];
385	387	case 0x005c/2:
386	388	/*
387	389	xxxx xxxx ---- ---- DIPSW4
388	390	---- ---- xxxx xxxx DIPSW3
389	391	*/
390		return input_port_read(space->machine(), "IN1");
	392	return input_port_read(machine(), "IN1");
391	393	}
392		return state->m_ac_devram[offset];
	394	return m_ac_devram[offset];
393	395	}
394	396
395		static WRITE16_HANDLER(ac_devices_w)
	397	WRITE16_MEMBER(acommand_state::ac_devices_w)
396	398	{
397		acommand_state *state = space->machine().driver_data<acommand_state>();
398		COMBINE_DATA(&state->m_ac_devram[offset]);
	399	COMBINE_DATA(&m_ac_devram[offset]);
399	400	switch(offset)
400	401	{
401	402	case 0x00/2:
402	403	if (ACCESSING_BITS_0_7)
403	404	{
404		okim6295_device *oki1 = space->machine().device<okim6295_device>("oki1");
405		okim6295_device *oki2 = space->machine().device<okim6295_device>("oki2");
	405	okim6295_device *oki1 = machine().device<okim6295_device>("oki1");
	406	okim6295_device *oki2 = machine().device<okim6295_device>("oki2");
406	407	oki1->set_bank_base(0x40000 * (data & 0x3));
407	408	oki2->set_bank_base(0x40000 * (data & 0x30) >> 4);
408	409	}
r14845	r14846
411	412	case 0x16/2:
412	413	if(ACCESSING_BITS_0_7)
413	414	{
414		okim6295_device *oki1 = space->machine().device<okim6295_device>("oki1");
415		oki1->write(*space,0,data);
	415	okim6295_device *oki1 = machine().device<okim6295_device>("oki1");
	416	oki1->write(*&space,0,data);
416	417	}
417	418	break;
418	419	case 0x18/2:
419	420	case 0x1a/2:
420	421	if(ACCESSING_BITS_0_7)
421	422	{
422		okim6295_device *oki2 = space->machine().device<okim6295_device>("oki2");
423		oki2->write(*space,0,data);
	423	okim6295_device *oki2 = machine().device<okim6295_device>("oki2");
	424	oki2->write(*&space,0,data);
424	425	}
425	426	break;
426	427	case 0x1c/2:
r14845	r14846
433	434	case 0x48/2:
434	435	break;
435	436	case 0x50/2:
436		state->m_led0 = state->m_ac_devram[offset];
437		//popmessage("%04x",state->m_led0);
	437	m_led0 = m_ac_devram[offset];
	438	//popmessage("%04x",m_led0);
438	439	break;
439	440	case 0x54/2:
440		state->m_led1 = state->m_ac_devram[offset];
441		//popmessage("%04x",state->m_led0);
	441	m_led1 = m_ac_devram[offset];
	442	//popmessage("%04x",m_led0);
442	443	break;
443	444	}
444	445	}
445	446
446	447	/*This is always zero ATM*/
447		static WRITE16_HANDLER(ac_unk2_w)
	448	WRITE16_MEMBER(acommand_state::ac_unk2_w)
448	449	{
449	450	if(data)
450	451	popmessage("UNK-2 enabled %04x",data);
r14845	r14846
452	453
453	454	static ADDRESS_MAP_START( acommand_map, AS_PROGRAM, 16, acommand_state )
454	455	AM_RANGE(0x000000, 0x03ffff) AM_ROM
455		AM_RANGE(0x082000, 0x082005) AM_WRITE_LEGACY(ac_bgscroll_w)
456		AM_RANGE(0x082100, 0x082105) AM_WRITE_LEGACY(ac_txscroll_w)
457		AM_RANGE(0x082208, 0x082209) AM_WRITE_LEGACY(ac_unk2_w)
458		AM_RANGE(0x0a0000, 0x0a3fff) AM_RAM_WRITE_LEGACY(ac_bgvram_w) AM_BASE(m_ac_bgvram)
459		AM_RANGE(0x0b0000, 0x0b3fff) AM_RAM_WRITE_LEGACY(ac_txvram_w) AM_BASE(m_ac_txvram)
	456	AM_RANGE(0x082000, 0x082005) AM_WRITE(ac_bgscroll_w)
	457	AM_RANGE(0x082100, 0x082105) AM_WRITE(ac_txscroll_w)
	458	AM_RANGE(0x082208, 0x082209) AM_WRITE(ac_unk2_w)
	459	AM_RANGE(0x0a0000, 0x0a3fff) AM_RAM_WRITE(ac_bgvram_w) AM_BASE(m_ac_bgvram)
	460	AM_RANGE(0x0b0000, 0x0b3fff) AM_RAM_WRITE(ac_txvram_w) AM_BASE(m_ac_txvram)
460	461	AM_RANGE(0x0b8000, 0x0bffff) AM_RAM_WRITE_LEGACY(paletteram16_RRRRGGGGBBBBRGBx_word_w) AM_BASE_GENERIC(paletteram)
461	462	AM_RANGE(0x0f0000, 0x0f7fff) AM_RAM
462	463	AM_RANGE(0x0f8000, 0x0f8fff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
463	464	AM_RANGE(0x0f9000, 0x0fffff) AM_RAM
464		AM_RANGE(0x100000, 0x1000ff) AM_READ_LEGACY(ac_devices_r) AM_WRITE_LEGACY(ac_devices_w) AM_BASE(m_ac_devram)
	465	AM_RANGE(0x100000, 0x1000ff) AM_READ(ac_devices_r) AM_WRITE(ac_devices_w) AM_BASE(m_ac_devram)
465	466	ADDRESS_MAP_END
466	467
467	468	static INPUT_PORTS_START( acommand )

src/mame/drivers/goldnpkr.c

r14845	r14846
966	966	tilemap_t *m_bg_tilemap;
967	967	UINT8 m_mux_data;
968	968	UINT8 m_pia0_PA_data;
	969	DECLARE_WRITE8_MEMBER(goldnpkr_videoram_w);
	970	DECLARE_WRITE8_MEMBER(goldnpkr_colorram_w);
969	971	};
970	972
971	973
r14845	r14846
974	976	*********************************************/
975	977
976	978
977		static WRITE8_HANDLER( goldnpkr_videoram_w )
	979	WRITE8_MEMBER(goldnpkr_state::goldnpkr_videoram_w)
978	980	{
979		goldnpkr_state *state = space->machine().driver_data<goldnpkr_state>();
980		state->m_videoram[offset] = data;
981		state->m_bg_tilemap->mark_tile_dirty(offset);
	981	m_videoram[offset] = data;
	982	m_bg_tilemap->mark_tile_dirty(offset);
982	983	}
983	984
984		static WRITE8_HANDLER( goldnpkr_colorram_w )
	985	WRITE8_MEMBER(goldnpkr_state::goldnpkr_colorram_w)
985	986	{
986		goldnpkr_state *state = space->machine().driver_data<goldnpkr_state>();
987		state->m_colorram[offset] = data;
988		state->m_bg_tilemap->mark_tile_dirty(offset);
	987	m_colorram[offset] = data;
	988	m_bg_tilemap->mark_tile_dirty(offset);
989	989	}
990	990
991	991	static TILE_GET_INFO( get_bg_tile_info )
r14845	r14846
1345	1345	AM_RANGE(0x0801, 0x0801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
1346	1346	AM_RANGE(0x0844, 0x0847) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
1347	1347	AM_RANGE(0x0848, 0x084b) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
1348		AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE_LEGACY(goldnpkr_videoram_w) AM_BASE(m_videoram)
1349		AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE_LEGACY(goldnpkr_colorram_w) AM_BASE(m_colorram)
	1348	AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(goldnpkr_videoram_w) AM_BASE(m_videoram)
	1349	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(goldnpkr_colorram_w) AM_BASE(m_colorram)
1350	1350	AM_RANGE(0x2000, 0x7fff) AM_ROM /* superdbl uses 0x2000..0x3fff address space */
1351	1351	ADDRESS_MAP_END
1352	1352
r14845	r14846
1357	1357	AM_RANGE(0x0801, 0x0801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
1358	1358	AM_RANGE(0x0844, 0x0847) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
1359	1359	AM_RANGE(0x0848, 0x084b) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
1360		AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE_LEGACY(goldnpkr_videoram_w) AM_BASE(m_videoram)
1361		AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE_LEGACY(goldnpkr_colorram_w) AM_BASE(m_colorram)
	1360	AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(goldnpkr_videoram_w) AM_BASE(m_videoram)
	1361	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(goldnpkr_colorram_w) AM_BASE(m_colorram)
1362	1362	AM_RANGE(0x2000, 0x3fff) AM_ROM
1363	1363	ADDRESS_MAP_END
1364	1364
r14845	r14846
1369	1369	AM_RANGE(0x0801, 0x0801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
1370	1370	AM_RANGE(0x0844, 0x0847) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
1371	1371	AM_RANGE(0x0848, 0x084b) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
1372		AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE_LEGACY(goldnpkr_videoram_w) AM_BASE(m_videoram)
1373		AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE_LEGACY(goldnpkr_colorram_w) AM_BASE(m_colorram)
	1372	AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(goldnpkr_videoram_w) AM_BASE(m_videoram)
	1373	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(goldnpkr_colorram_w) AM_BASE(m_colorram)
1374	1374	AM_RANGE(0x2000, 0x2000) AM_READ_PORT("SW2")
1375	1375	//  AM_RANGE(0x2108, 0x210b) AM_NOP /* unknown 40-pin device */
1376	1376	AM_RANGE(0x2800, 0x2fff) AM_RAM
r14845	r14846
1394	1394	AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("nvram")   /* battery backed RAM */
1395	1395	AM_RANGE(0x0844, 0x0847) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
1396	1396	AM_RANGE(0x0848, 0x084b) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
1397		AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE_LEGACY(goldnpkr_videoram_w) AM_BASE(m_videoram)
1398		AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE_LEGACY(goldnpkr_colorram_w) AM_BASE(m_colorram)
	1397	AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(goldnpkr_videoram_w) AM_BASE(m_videoram)
	1398	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(goldnpkr_colorram_w) AM_BASE(m_colorram)
1399	1399	AM_RANGE(0x2000, 0x2000) AM_READ_PORT("SW2")
1400	1400	AM_RANGE(0x2100, 0x2100) AM_DEVWRITE("crtc", mc6845_device, address_w)
1401	1401	AM_RANGE(0x2101, 0x2101) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
r14845	r14846
1409	1409	AM_RANGE(0x0801, 0x0801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
1410	1410	AM_RANGE(0x0844, 0x0847) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
1411	1411	AM_RANGE(0x0848, 0x084b) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
1412		AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE_LEGACY(goldnpkr_videoram_w) AM_BASE(m_videoram)
1413		AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE_LEGACY(goldnpkr_colorram_w) AM_BASE(m_colorram)
	1412	AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(goldnpkr_videoram_w) AM_BASE(m_videoram)
	1413	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(goldnpkr_colorram_w) AM_BASE(m_colorram)
1414	1414	AM_RANGE(0x2000, 0x2000) AM_READ_PORT("SW2")
1415	1415	AM_RANGE(0x2200, 0x27ff) AM_ROM   /* for VK set */
1416	1416	AM_RANGE(0x2800, 0x2fff) AM_RAM   /* for VK set */
r14845	r14846
1430	1430	AM_RANGE(0x0801, 0x0801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
1431	1431	AM_RANGE(0x0844, 0x0847) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
1432	1432	AM_RANGE(0x0848, 0x084b) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
1433		AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE_LEGACY(goldnpkr_videoram_w) AM_BASE(m_videoram)
1434		AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE_LEGACY(goldnpkr_colorram_w) AM_BASE(m_colorram)
	1433	AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(goldnpkr_videoram_w) AM_BASE(m_videoram)
	1434	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(goldnpkr_colorram_w) AM_BASE(m_colorram)
1435	1435	AM_RANGE(0x2000, 0x2000) AM_READ_PORT("SW2")
1436	1436	AM_RANGE(0x2200, 0x27ff) AM_ROM   /* for VK hardware */
1437	1437	AM_RANGE(0x2800, 0x2fff) AM_RAM   AM_SHARE("nvram")   /* Dallas ds1210 + battery backed RAM */
r14845	r14846
1449	1449	AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("nvram")   /* battery backed RAM */
1450	1450	AM_RANGE(0x0844, 0x0847) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
1451	1451	AM_RANGE(0x0848, 0x084b) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
1452		AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE_LEGACY(goldnpkr_videoram_w) AM_BASE(m_videoram)
1453		AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE_LEGACY(goldnpkr_colorram_w) AM_BASE(m_colorram)
	1452	AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(goldnpkr_videoram_w) AM_BASE(m_videoram)
	1453	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(goldnpkr_colorram_w) AM_BASE(m_colorram)
1454	1454	AM_RANGE(0x2000, 0x2000) AM_READ_PORT("SW2")
1455	1455	AM_RANGE(0x2100, 0x2100) AM_DEVWRITE("crtc", mc6845_device, address_w)
1456	1456	AM_RANGE(0x2101, 0x2101) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
r14845	r14846
1484	1484	AM_RANGE(0x0801, 0x0801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
1485	1485	AM_RANGE(0x0844, 0x0847) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
1486	1486	AM_RANGE(0x0848, 0x084b) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
1487		AM_RANGE(0x1000, 0x17ff) AM_RAM_WRITE_LEGACY(goldnpkr_videoram_w) AM_BASE(m_videoram)
1488		AM_RANGE(0x1800, 0x1fff) AM_RAM_WRITE_LEGACY(goldnpkr_colorram_w) AM_BASE(m_colorram)
	1487	AM_RANGE(0x1000, 0x17ff) AM_RAM_WRITE(goldnpkr_videoram_w) AM_BASE(m_videoram)
	1488	AM_RANGE(0x1800, 0x1fff) AM_RAM_WRITE(goldnpkr_colorram_w) AM_BASE(m_colorram)
1489	1489	AM_RANGE(0x2000, 0x3fff) AM_ROM
1490	1490	ADDRESS_MAP_END
1491	1491

src/mame/drivers/ppmast93.c

r14845	r14846
146	146	tilemap_t *m_bg_tilemap;
147	147	UINT8 *m_fgram;
148	148	UINT8 *m_bgram;
	149	DECLARE_WRITE8_MEMBER(ppmast93_fgram_w);
	150	DECLARE_WRITE8_MEMBER(ppmast93_bgram_w);
	151	DECLARE_WRITE8_MEMBER(ppmast93_port4_w);
	152	DECLARE_WRITE8_MEMBER(ppmast_sound_w);
149	153	};
150	154
151	155
152	156
153	157
154		static WRITE8_HANDLER( ppmast93_fgram_w )
	158	WRITE8_MEMBER(ppmast93_state::ppmast93_fgram_w)
155	159	{
156		ppmast93_state *state = space->machine().driver_data<ppmast93_state>();
157		state->m_fgram[offset] = data;
158		state->m_fg_tilemap->mark_tile_dirty(offset/2);
	160	m_fgram[offset] = data;
	161	m_fg_tilemap->mark_tile_dirty(offset/2);
159	162	}
160	163
161		static WRITE8_HANDLER( ppmast93_bgram_w )
	164	WRITE8_MEMBER(ppmast93_state::ppmast93_bgram_w)
162	165	{
163		ppmast93_state *state = space->machine().driver_data<ppmast93_state>();
164		state->m_bgram[offset] = data;
165		state->m_bg_tilemap->mark_tile_dirty(offset/2);
	166	m_bgram[offset] = data;
	167	m_bg_tilemap->mark_tile_dirty(offset/2);
166	168	}
167	169
168		static WRITE8_HANDLER( ppmast93_port4_w )
	170	WRITE8_MEMBER(ppmast93_state::ppmast93_port4_w)
169	171	{
170		UINT8 *rom = space->machine().region("maincpu")->base();
	172	UINT8 *rom = machine().region("maincpu")->base();
171	173	int bank;
172	174
173		coin_counter_w(space->machine(), 0, data & 0x08);
174		coin_counter_w(space->machine(), 1, data & 0x10);
	175	coin_counter_w(machine(), 0, data & 0x08);
	176	coin_counter_w(machine(), 1, data & 0x10);
175	177
176	178	bank = data & 0x07;
177		memory_set_bankptr(space->machine(), "bank1",&rom[0x10000+(bank*0x4000)]);
	179	memory_set_bankptr(machine(), "bank1",&rom[0x10000+(bank*0x4000)]);
178	180	}
179	181
180	182	static ADDRESS_MAP_START( ppmast93_cpu1_map, AS_PROGRAM, 8, ppmast93_state )
181	183	AM_RANGE(0x0000, 0x7fff) AM_ROM AM_WRITENOP AM_REGION("maincpu", 0x10000)
182	184	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
183		AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE_LEGACY(ppmast93_bgram_w) AM_BASE(m_bgram) AM_SHARE("share1")
	185	AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE(ppmast93_bgram_w) AM_BASE(m_bgram) AM_SHARE("share1")
184	186	AM_RANGE(0xd800, 0xdfff) AM_WRITENOP
185		AM_RANGE(0xf000, 0xf7ff) AM_RAM_WRITE_LEGACY(ppmast93_fgram_w) AM_BASE(m_fgram) AM_SHARE("share2")
	187	AM_RANGE(0xf000, 0xf7ff) AM_RAM_WRITE(ppmast93_fgram_w) AM_BASE(m_fgram) AM_SHARE("share2")
186	188	AM_RANGE(0xf800, 0xffff) AM_RAM
187	189	ADDRESS_MAP_END
188	190
r14845	r14846
195	197	AM_RANGE(0x08, 0x08) AM_READ_PORT("DSW2")
196	198
197	199	AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(soundlatch_w)
198		AM_RANGE(0x04, 0x04) AM_WRITE_LEGACY(ppmast93_port4_w)
	200	AM_RANGE(0x04, 0x04) AM_WRITE(ppmast93_port4_w)
199	201	ADDRESS_MAP_END
200	202
201	203	static ADDRESS_MAP_START( ppmast93_cpu2_map, AS_PROGRAM, 8, ppmast93_state )
r14845	r14846
205	207	ADDRESS_MAP_END
206	208
207	209
208		static WRITE8_HANDLER(ppmast_sound_w)
	210	WRITE8_MEMBER(ppmast93_state::ppmast_sound_w)
209	211	{
210	212	switch(offset&0xff)
211	213	{
212	214	case 0:
213		case 1: ym2413_w(space->machine().device("ymsnd"),offset,data); break;
214		case 2: dac_data_w(space->machine().device("dac"),data);break;
215		default: logerror("%x %x - %x\n",offset,data,cpu_get_previouspc(&space->device()));
	215	case 1: ym2413_w(machine().device("ymsnd"),offset,data); break;
	216	case 2: dac_data_w(machine().device("dac"),data);break;
	217	default: logerror("%x %x - %x\n",offset,data,cpu_get_previouspc(&space.device()));
216	218	}
217	219	}
218	220
219	221	static ADDRESS_MAP_START( ppmast93_cpu2_io, AS_IO, 8, ppmast93_state )
220		AM_RANGE(0x0000, 0xffff) AM_ROM AM_WRITE_LEGACY(ppmast_sound_w) AM_REGION("sub", 0x20000)
	222	AM_RANGE(0x0000, 0xffff) AM_ROM AM_WRITE(ppmast_sound_w) AM_REGION("sub", 0x20000)
221	223	ADDRESS_MAP_END
222	224
223	225	static INPUT_PORTS_START( ppmast93 )

src/mame/drivers/eolith16.c

r14845	r14846
24	24
25	25	UINT16 *m_vram;
26	26	int m_vbuffer;
	27	DECLARE_WRITE16_MEMBER(eeprom_w);
	28	DECLARE_READ16_MEMBER(eolith16_custom_r);
	29	DECLARE_WRITE16_MEMBER(vram_w);
	30	DECLARE_READ16_MEMBER(vram_r);
27	31	};
28	32
29	33
r14845	r14846
40	44	"*10011xxxxxx"   // unlock       100 11xxxxxxx
41	45	};
42	46
43		static WRITE16_HANDLER( eeprom_w )
	47	WRITE16_MEMBER(eolith16_state::eeprom_w)
44	48	{
45		eolith16_state *state = space->machine().driver_data<eolith16_state>();
46		state->m_vbuffer = (data & 0x80) >> 7;
47		coin_counter_w(space->machine(), 0, data & 1);
	49	m_vbuffer = (data & 0x80) >> 7;
	50	coin_counter_w(machine(), 0, data & 1);
48	51
49		input_port_write(space->machine(), "EEPROMOUT", data, 0xff);
	52	input_port_write(machine(), "EEPROMOUT", data, 0xff);
50	53
51	54	//data & 0x100 and data & 0x004 always set
52	55	}
53	56
54		static READ16_HANDLER( eolith16_custom_r )
	57	READ16_MEMBER(eolith16_state::eolith16_custom_r)
55	58	{
56		eolith_speedup_read(space);
57		return input_port_read(space->machine(), "SPECIAL");
	59	eolith_speedup_read(&space);
	60	return input_port_read(machine(), "SPECIAL");
58	61	}
59	62
60	63
61	64
62		static WRITE16_HANDLER( vram_w )
	65	WRITE16_MEMBER(eolith16_state::vram_w)
63	66	{
64		eolith16_state *state = space->machine().driver_data<eolith16_state>();
65		COMBINE_DATA(&state->m_vram[offset + (0x10000/2) * state->m_vbuffer]);
	67	COMBINE_DATA(&m_vram[offset + (0x10000/2) * m_vbuffer]);
66	68	}
67	69
68		static READ16_HANDLER( vram_r )
	70	READ16_MEMBER(eolith16_state::vram_r)
69	71	{
70		eolith16_state *state = space->machine().driver_data<eolith16_state>();
71		return state->m_vram[offset + (0x10000/2) * state->m_vbuffer];
	72	return m_vram[offset + (0x10000/2) * m_vbuffer];
72	73	}
73	74
74	75	static ADDRESS_MAP_START( eolith16_map, AS_PROGRAM, 16, eolith16_state )
75	76	AM_RANGE(0x00000000, 0x001fffff) AM_RAM
76		AM_RANGE(0x50000000, 0x5000ffff) AM_READWRITE_LEGACY(vram_r, vram_w)
	77	AM_RANGE(0x50000000, 0x5000ffff) AM_READWRITE(vram_r, vram_w)
77	78	AM_RANGE(0x90000000, 0x9000002f) AM_WRITENOP //?
78	79	AM_RANGE(0xff000000, 0xff1fffff) AM_ROM AM_REGION("user2", 0)
79	80	AM_RANGE(0xffe40000, 0xffe40001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
80		AM_RANGE(0xffe80000, 0xffe80001) AM_WRITE_LEGACY(eeprom_w)
81		AM_RANGE(0xffea0000, 0xffea0001) AM_READ_LEGACY(eolith16_custom_r)
	81	AM_RANGE(0xffe80000, 0xffe80001) AM_WRITE(eeprom_w)
	82	AM_RANGE(0xffea0000, 0xffea0001) AM_READ(eolith16_custom_r)
82	83	AM_RANGE(0xffea0002, 0xffea0003) AM_READ_PORT("SYSTEM")
83	84	AM_RANGE(0xffec0000, 0xffec0001) AM_READNOP // not used?
84	85	AM_RANGE(0xffec0002, 0xffec0003) AM_READ_PORT("INPUTS")

src/mame/drivers/segald.c

r14845	r14846
42	42	UINT8 m_ldv1000_input_latch;
43	43	UINT8 m_ldv1000_output_latch;
44	44
	45	DECLARE_READ8_MEMBER(astron_DISC_read);
	46	DECLARE_READ8_MEMBER(astron_OUT_read);
	47	DECLARE_READ8_MEMBER(astron_OBJ_read);
	48	DECLARE_READ8_MEMBER(astron_COLOR_read);
	49	DECLARE_WRITE8_MEMBER(astron_DISC_write);
	50	DECLARE_WRITE8_MEMBER(astron_OUT_write);
	51	DECLARE_WRITE8_MEMBER(astron_OBJ_write);
	52	DECLARE_WRITE8_MEMBER(astron_COLOR_write);
	53	DECLARE_WRITE8_MEMBER(astron_FIX_write);
	54	DECLARE_WRITE8_MEMBER(astron_io_bankswitch_w);
45	55	};
46	56
47	57	/* VIDEO GOODS */
r14845	r14846
104	114
105	115	/* MEMORY HANDLERS */
106	116	/* READS */
107		static READ8_HANDLER( astron_DISC_read )
	117	READ8_MEMBER(segald_state::astron_DISC_read)
108	118	{
109		segald_state *state = space->machine().driver_data<segald_state>();
110	119
111		if (state->m_nmi_enable)
112		state->m_ldv1000_input_latch = state->m_laserdisc->status_r();
	120	if (m_nmi_enable)
	121	m_ldv1000_input_latch = m_laserdisc->status_r();
113	122
114		logerror("DISC read   (0x%04x) @ 0x%04x [0x%x]\n", state->m_ldv1000_input_latch, offset, cpu_get_pc(&space->device()));
	123	logerror("DISC read   (0x%04x) @ 0x%04x [0x%x]\n", m_ldv1000_input_latch, offset, cpu_get_pc(&space.device()));
115	124
116		return state->m_ldv1000_input_latch;
	125	return m_ldv1000_input_latch;
117	126	}
118	127
119		static READ8_HANDLER( astron_OUT_read )
	128	READ8_MEMBER(segald_state::astron_OUT_read)
120	129	{
121		segald_state *state = space->machine().driver_data<segald_state>();
122	130
123		logerror("OUT read   (0x%04x) @ 0x%04x [0x%x]\n", state->m_out_RAM[offset], offset, cpu_get_pc(&space->device()));
124		return state->m_out_RAM[offset];
	131	logerror("OUT read   (0x%04x) @ 0x%04x [0x%x]\n", m_out_RAM[offset], offset, cpu_get_pc(&space.device()));
	132	return m_out_RAM[offset];
125	133	}
126	134
127		static READ8_HANDLER( astron_OBJ_read )
	135	READ8_MEMBER(segald_state::astron_OBJ_read)
128	136	{
129		segald_state *state = space->machine().driver_data<segald_state>();
130	137
131		logerror("OBJ read   (0x%04x) @ 0x%04x [0x%x]\n", state->m_obj_RAM[offset], offset, cpu_get_pc(&space->device()));
132		return state->m_obj_RAM[offset];
	138	logerror("OBJ read   (0x%04x) @ 0x%04x [0x%x]\n", m_obj_RAM[offset], offset, cpu_get_pc(&space.device()));
	139	return m_obj_RAM[offset];
133	140	}
134	141
135		static READ8_HANDLER( astron_COLOR_read )
	142	READ8_MEMBER(segald_state::astron_COLOR_read)
136	143	{
137		segald_state *state = space->machine().driver_data<segald_state>();
138	144
139		logerror("COLOR read   (0x%04x) @ 0x%04x [0x%x]\n", state->m_color_RAM[offset], offset, cpu_get_pc(&space->device()));
140		return state->m_color_RAM[offset];
	145	logerror("COLOR read   (0x%04x) @ 0x%04x [0x%x]\n", m_color_RAM[offset], offset, cpu_get_pc(&space.device()));
	146	return m_color_RAM[offset];
141	147	}
142	148
143	149
144	150	/* WRITES */
145		static WRITE8_HANDLER( astron_DISC_write )
	151	WRITE8_MEMBER(segald_state::astron_DISC_write)
146	152	{
147		segald_state *state = space->machine().driver_data<segald_state>();
148	153
149		logerror("DISC write : 0x%04x @  0x%04x [0x%x]\n", data, offset, cpu_get_pc(&space->device()));
	154	logerror("DISC write : 0x%04x @  0x%04x [0x%x]\n", data, offset, cpu_get_pc(&space.device()));
150	155
151		state->m_ldv1000_output_latch = data;
	156	m_ldv1000_output_latch = data;
152	157
153		if (state->m_nmi_enable)
154		state->m_laserdisc->data_w(state->m_ldv1000_output_latch);
	158	if (m_nmi_enable)
	159	m_laserdisc->data_w(m_ldv1000_output_latch);
155	160	}
156	161
157		static WRITE8_HANDLER( astron_OUT_write )
	162	WRITE8_MEMBER(segald_state::astron_OUT_write)
158	163	{
159		segald_state *state = space->machine().driver_data<segald_state>();
160	164
161		logerror("OUT write : 0x%04x @  0x%04x [0x%x]\n", data, offset, cpu_get_pc(&space->device()));
	165	logerror("OUT write : 0x%04x @  0x%04x [0x%x]\n", data, offset, cpu_get_pc(&space.device()));
162	166
163	167	switch(offset)
164	168	{
r14845	r14846
176	180	/* data & 0x10 = Continue Lamp */
177	181
178	182	/* data & 0x20 = CHC           */
179		state->m_nmi_enable = data & 0x40;      /* NMIE */
	183	m_nmi_enable = data & 0x40;      /* NMIE */
180	184	/* data & 0x80 = CN0 Pin 19    */
181	185	break;
182	186
r14845	r14846
189	193	break;
190	194	}
191	195
192		state->m_out_RAM[offset] = data;
	196	m_out_RAM[offset] = data;
193	197	}
194	198
195		static WRITE8_HANDLER( astron_OBJ_write )
	199	WRITE8_MEMBER(segald_state::astron_OBJ_write)
196	200	{
197		segald_state *state = space->machine().driver_data<segald_state>();
198	201
199		state->m_obj_RAM[offset] = data;
200		logerror("OBJ write : 0x%04x @ 0x%04x [0x%x]\n", data, offset, cpu_get_pc(&space->device()));
	202	m_obj_RAM[offset] = data;
	203	logerror("OBJ write : 0x%04x @ 0x%04x [0x%x]\n", data, offset, cpu_get_pc(&space.device()));
201	204	}
202	205
203		static WRITE8_HANDLER( astron_COLOR_write )
	206	WRITE8_MEMBER(segald_state::astron_COLOR_write)
204	207	{
205		segald_state *state = space->machine().driver_data<segald_state>();
206	208	UINT8 r, g, b, a;
207	209	UINT8 highBits, lowBits;
208	210	const UINT8 palIndex = offset >> 1;
209	211
210	212	/* Combine */
211		state->m_color_RAM[offset] = data;
	213	m_color_RAM[offset] = data;
212	214
213	215	/* Easy access */
214		highBits = state->m_color_RAM[(palIndex<<1)+1] & 0x0f;
215		lowBits  = state->m_color_RAM[(palIndex<<1)];
	216	highBits = m_color_RAM[(palIndex<<1)+1] & 0x0f;
	217	lowBits  = m_color_RAM[(palIndex<<1)];
216	218
217	219	/* 4-bit RGB */
218	220	r = (lowBits  & 0x0f);
r14845	r14846
220	222	b = (highBits & 0x0f);
221	223	a = (highBits & 0x80) ? 0 : 255;
222	224
223		palette_set_color(space->machine(), palIndex, MAKE_ARGB(a, r, g, b));
224		logerror("COLOR write : 0x%04x @   0x%04x [0x%x]\n", data, offset, cpu_get_pc(&space->device()));
	225	palette_set_color(machine(), palIndex, MAKE_ARGB(a, r, g, b));
	226	logerror("COLOR write : 0x%04x @   0x%04x [0x%x]\n", data, offset, cpu_get_pc(&space.device()));
225	227	}
226	228
227		static WRITE8_HANDLER( astron_FIX_write )
	229	WRITE8_MEMBER(segald_state::astron_FIX_write)
228	230	{
229		segald_state *state = space->machine().driver_data<segald_state>();
230	231
231		state->m_fix_RAM[offset] = data;
232		/* logerror("FIX write : 0x%04x @ 0x%04x [0x%x]\n", data, offset, cpu_get_pc(&space->device())); */
	232	m_fix_RAM[offset] = data;
	233	/* logerror("FIX write : 0x%04x @ 0x%04x [0x%x]\n", data, offset, cpu_get_pc(&space.device())); */
233	234	}
234	235
235		static WRITE8_HANDLER( astron_io_bankswitch_w )
	236	WRITE8_MEMBER(segald_state::astron_io_bankswitch_w)
236	237	{
237	238	logerror("Banking 0x%x\n", data);
238		memory_set_bank(space->machine(), "bank1", data & 0xff);
	239	memory_set_bank(machine(), "bank1", data & 0xff);
239	240	}
240	241
241	242
r14845	r14846
246	247	AM_RANGE(0x0000, 0x7fff) AM_ROM
247	248	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
248	249
249		AM_RANGE(0xc000, 0xc7ff) AM_READWRITE_LEGACY(astron_OBJ_read, astron_OBJ_write) AM_BASE(m_obj_RAM)   /* OBJ according to the schematics (sprite) */
250		AM_RANGE(0xc800, 0xcfff) AM_READWRITE_LEGACY(astron_DISC_read, astron_DISC_write)               /* DISC interface according to schematics */
	250	AM_RANGE(0xc000, 0xc7ff) AM_READWRITE(astron_OBJ_read, astron_OBJ_write) AM_BASE(m_obj_RAM)   /* OBJ according to the schematics (sprite) */
	251	AM_RANGE(0xc800, 0xcfff) AM_READWRITE(astron_DISC_read, astron_DISC_write)               /* DISC interface according to schematics */
251	252	AM_RANGE(0xd000, 0xd000) AM_READ_PORT("DSWA")                        /* SW bank 2 (DIPs) */
252	253	AM_RANGE(0xd001, 0xd001) AM_READ_PORT("DSWB")                        /* SW bank 3 (DIPs) */
253	254	AM_RANGE(0xd002, 0xd002) AM_READ_PORT("IN0")                        /* SW bank 0 (IO) */
254	255	AM_RANGE(0xd003, 0xd003) AM_READ_PORT("IN1")                        /* SW bank 1 (IO) */
255		AM_RANGE(0xd800, 0xd803) AM_READWRITE_LEGACY(astron_OUT_read, astron_OUT_write) AM_BASE(m_out_RAM)   /* OUT according to schematics (output port) */
256		AM_RANGE(0xe000, 0xe1ff) AM_READWRITE_LEGACY(astron_COLOR_read, astron_COLOR_write) AM_BASE(m_color_RAM) /* COLOR according to the schematics */
257		AM_RANGE(0xf000, 0xf7ff) AM_WRITE_LEGACY(astron_FIX_write) AM_BASE(m_fix_RAM)                  /* FIX according to schematics (characters) */
	256	AM_RANGE(0xd800, 0xd803) AM_READWRITE(astron_OUT_read, astron_OUT_write) AM_BASE(m_out_RAM)   /* OUT according to schematics (output port) */
	257	AM_RANGE(0xe000, 0xe1ff) AM_READWRITE(astron_COLOR_read, astron_COLOR_write) AM_BASE(m_color_RAM) /* COLOR according to the schematics */
	258	AM_RANGE(0xf000, 0xf7ff) AM_WRITE(astron_FIX_write) AM_BASE(m_fix_RAM)                  /* FIX according to schematics (characters) */
258	259	AM_RANGE(0xf800, 0xffff) AM_RAM                                                /* RAM according to schematics */
259	260	ADDRESS_MAP_END
260	261
r14845	r14846
262	263	/* I/O MAP */
263	264	static ADDRESS_MAP_START( mainport, AS_IO, 8, segald_state )
264	265	ADDRESS_MAP_GLOBAL_MASK(0xff)
265		AM_RANGE(0x00, 0x01) AM_WRITE_LEGACY(astron_io_bankswitch_w)
	266	AM_RANGE(0x00, 0x01) AM_WRITE(astron_io_bankswitch_w)
266	267	ADDRESS_MAP_END
267	268
268	269

src/mame/drivers/tickee.c

r14845	r14846
42	42	int m_beamyadd;
43	43	int m_palette_bank;
44	44	UINT8 m_gunx[2];
	45	DECLARE_WRITE16_MEMBER(rapidfir_transparent_w);
	46	DECLARE_READ16_MEMBER(rapidfir_transparent_r);
	47	DECLARE_WRITE16_MEMBER(tickee_control_w);
	48	DECLARE_READ16_MEMBER(ffff_r);
	49	DECLARE_READ16_MEMBER(rapidfir_gun1_r);
	50	DECLARE_READ16_MEMBER(rapidfir_gun2_r);
	51	DECLARE_READ16_MEMBER(ff7f_r);
	52	DECLARE_WRITE16_MEMBER(ff7f_w);
	53	DECLARE_WRITE16_MEMBER(rapidfir_control_w);
45	54	};
46	55
47	56
r14845	r14846
225	234	*
226	235	*************************************/
227	236
228		static WRITE16_HANDLER( rapidfir_transparent_w )
	237	WRITE16_MEMBER(tickee_state::rapidfir_transparent_w)
229	238	{
230		tickee_state *state = space->machine().driver_data<tickee_state>();
231	239	if (!(data & 0xff00)) mem_mask &= 0x00ff;
232	240	if (!(data & 0x00ff)) mem_mask &= 0xff00;
233		COMBINE_DATA(&state->m_vram[offset]);
	241	COMBINE_DATA(&m_vram[offset]);
234	242	}
235	243
236	244
237		static READ16_HANDLER( rapidfir_transparent_r )
	245	READ16_MEMBER(tickee_state::rapidfir_transparent_r)
238	246	{
239		tickee_state *state = space->machine().driver_data<tickee_state>();
240		return state->m_vram[offset];
	247	return m_vram[offset];
241	248	}
242	249
243	250
r14845	r14846
264	271	*
265	272	*************************************/
266	273
267		static WRITE16_HANDLER( tickee_control_w )
	274	WRITE16_MEMBER(tickee_state::tickee_control_w)
268	275	{
269		tickee_state *state = space->machine().driver_data<tickee_state>();
270		UINT16 olddata = state->m_control[offset];
	276	UINT16 olddata = m_control[offset];
271	277
272	278	/* offsets:
273	279
r14845	r14846
276	282	6 = lamps? (changing all the time)
277	283	*/
278	284
279		COMBINE_DATA(&state->m_control[offset]);
	285	COMBINE_DATA(&m_control[offset]);
280	286
281	287	if (offset == 3)
282	288	{
283		ticket_dispenser_w(space->machine().device("ticket1"), 0, (data & 8) << 4);
284		ticket_dispenser_w(space->machine().device("ticket2"), 0, (data & 4) << 5);
	289	ticket_dispenser_w(machine().device("ticket1"), 0, (data & 8) << 4);
	290	ticket_dispenser_w(machine().device("ticket2"), 0, (data & 4) << 5);
285	291	}
286	292
287		if (olddata != state->m_control[offset])
288		logerror("%08X:tickee_control_w(%d) = %04X (was %04X)\n", cpu_get_pc(&space->device()), offset, state->m_control[offset], olddata);
	293	if (olddata != m_control[offset])
	294	logerror("%08X:tickee_control_w(%d) = %04X (was %04X)\n", cpu_get_pc(&space.device()), offset, m_control[offset], olddata);
289	295	}
290	296
291	297
r14845	r14846
296	302	*
297	303	*************************************/
298	304
299		static READ16_HANDLER( ffff_r )
	305	READ16_MEMBER(tickee_state::ffff_r)
300	306	{
301	307	return 0xffff;
302	308	}
303	309
304	310
305		static READ16_HANDLER( rapidfir_gun1_r )
	311	READ16_MEMBER(tickee_state::rapidfir_gun1_r)
306	312	{
307		tickee_state *state = space->machine().driver_data<tickee_state>();
308		return state->m_gunx[0];
	313	return m_gunx[0];
309	314	}
310	315
311	316
312		static READ16_HANDLER( rapidfir_gun2_r )
	317	READ16_MEMBER(tickee_state::rapidfir_gun2_r)
313	318	{
314		tickee_state *state = space->machine().driver_data<tickee_state>();
315		return state->m_gunx[1];
	319	return m_gunx[1];
316	320	}
317	321
318	322
319		static READ16_HANDLER( ff7f_r )
	323	READ16_MEMBER(tickee_state::ff7f_r)
320	324	{
321	325	/* Ticket dispenser status? */
322	326	return 0xff7f;
323	327	}
324	328
325		static WRITE16_HANDLER( ff7f_w )
	329	WRITE16_MEMBER(tickee_state::ff7f_w)
326	330	{
327	331	/* Ticket dispenser output? */
328	332	}
329	333
330		static WRITE16_HANDLER( rapidfir_control_w )
	334	WRITE16_MEMBER(tickee_state::rapidfir_control_w)
331	335	{
332		tickee_state *state = space->machine().driver_data<tickee_state>();
333	336	/* other bits like control on tickee? */
334	337	if (ACCESSING_BITS_0_7)
335		state->m_palette_bank = data & 1;
	338	m_palette_bank = data & 1;
336	339	}
337	340
338	341
r14845	r14846
386	389	AM_RANGE(0x04200000, 0x0420001f) AM_DEVWRITE8_LEGACY("ym1", ay8910_address_data_w, 0x00ff)
387	390	AM_RANGE(0x04200100, 0x0420010f) AM_DEVREAD8_LEGACY("ym2", ay8910_r, 0x00ff)
388	391	AM_RANGE(0x04200100, 0x0420011f) AM_DEVWRITE8_LEGACY("ym2", ay8910_address_data_w, 0x00ff)
389		AM_RANGE(0x04400000, 0x0440007f) AM_WRITE_LEGACY(tickee_control_w) AM_BASE(m_control)
	392	AM_RANGE(0x04400000, 0x0440007f) AM_WRITE(tickee_control_w) AM_BASE(m_control)
390	393	AM_RANGE(0x04400040, 0x0440004f) AM_READ_PORT("IN2")
391	394	AM_RANGE(0xc0000000, 0xc00001ff) AM_READWRITE_LEGACY(tms34010_io_register_r, tms34010_io_register_w)
392	395	AM_RANGE(0xc0000240, 0xc000025f) AM_WRITENOP      /* seems to be a bug in their code */
r14845	r14846
404	407	AM_RANGE(0x04300000, 0x0430001f) AM_DEVWRITE8_LEGACY("ym1", ay8910_address_data_w, 0x00ff)
405	408	AM_RANGE(0x04300100, 0x0430010f) AM_DEVREAD8_LEGACY("ym2", ay8910_r, 0x00ff)
406	409	AM_RANGE(0x04300100, 0x0430011f) AM_DEVWRITE8_LEGACY("ym2", ay8910_address_data_w, 0x00ff)
407		AM_RANGE(0x04500000, 0x0450007f) AM_WRITE_LEGACY(tickee_control_w) AM_BASE(m_control)
	410	AM_RANGE(0x04500000, 0x0450007f) AM_WRITE(tickee_control_w) AM_BASE(m_control)
408	411	AM_RANGE(0xc0000000, 0xc00001ff) AM_READWRITE_LEGACY(tms34010_io_register_r, tms34010_io_register_w)
409	412	AM_RANGE(0xc0000240, 0xc000025f) AM_WRITENOP      /* seems to be a bug in their code */
410	413	AM_RANGE(0xff000000, 0xffffffff) AM_ROM AM_REGION("user1", 0)
r14845	r14846
419	422	AM_RANGE(0x04200000, 0x0420000f) AM_DEVREAD8_LEGACY("ym", ay8910_r, 0x00ff)
420	423	AM_RANGE(0x04200000, 0x0420000f) AM_DEVWRITE8_LEGACY("ym", ay8910_address_data_w, 0x00ff)
421	424	AM_RANGE(0x04200100, 0x0420010f) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
422		AM_RANGE(0x04400000, 0x0440007f) AM_WRITE_LEGACY(tickee_control_w) AM_BASE(m_control)
	425	AM_RANGE(0x04400000, 0x0440007f) AM_WRITE(tickee_control_w) AM_BASE(m_control)
423	426	AM_RANGE(0x04400040, 0x0440004f) AM_READ_PORT("IN2") // ?
424	427	AM_RANGE(0xc0000000, 0xc00001ff) AM_READWRITE_LEGACY(tms34010_io_register_r, tms34010_io_register_w)
425	428	AM_RANGE(0xc0000240, 0xc000025f) AM_WRITENOP      /* seems to be a bug in their code */
r14845	r14846
430	433	/* newer hardware */
431	434	static ADDRESS_MAP_START( rapidfir_map, AS_PROGRAM, 16, tickee_state )
432	435	AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_BASE(m_vram)
433		AM_RANGE(0x02000000, 0x027fffff) AM_READWRITE_LEGACY(rapidfir_transparent_r, rapidfir_transparent_w)
	436	AM_RANGE(0x02000000, 0x027fffff) AM_READWRITE(rapidfir_transparent_r, rapidfir_transparent_w)
434	437	AM_RANGE(0xc0000000, 0xc00001ff) AM_READWRITE_LEGACY(tms34010_io_register_r, tms34010_io_register_w)
435		AM_RANGE(0xfc000000, 0xfc00000f) AM_READ_LEGACY(rapidfir_gun1_r)
436		AM_RANGE(0xfc000100, 0xfc00010f) AM_READ_LEGACY(rapidfir_gun2_r)
437		AM_RANGE(0xfc000400, 0xfc00040f) AM_READ_LEGACY(ffff_r)
	438	AM_RANGE(0xfc000000, 0xfc00000f) AM_READ(rapidfir_gun1_r)
	439	AM_RANGE(0xfc000100, 0xfc00010f) AM_READ(rapidfir_gun2_r)
	440	AM_RANGE(0xfc000400, 0xfc00040f) AM_READ(ffff_r)
438	441	AM_RANGE(0xfc000500, 0xfc00050f) AM_NOP
439		AM_RANGE(0xfc000600, 0xfc00060f) AM_WRITE_LEGACY(rapidfir_control_w)
	442	AM_RANGE(0xfc000600, 0xfc00060f) AM_WRITE(rapidfir_control_w)
440	443	AM_RANGE(0xfc000700, 0xfc00070f) AM_DEVWRITE_LEGACY("oki", sound_bank_w)
441	444	AM_RANGE(0xfc000800, 0xfc00080f) AM_READ_PORT("IN0")
442	445	AM_RANGE(0xfc000900, 0xfc00090f) AM_READ_PORT("IN1")
r14845	r14846
447	450	AM_RANGE(0xfc100000, 0xfc1000ff) AM_MIRROR(0x80000) AM_DEVREADWRITE8_LEGACY("tlc34076", tlc34076_r, tlc34076_w, 0x00ff)
448	451	AM_RANGE(0xfc200000, 0xfc207fff) AM_RAM AM_SHARE("nvram")
449	452	AM_RANGE(0xfc300000, 0xfc30000f) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
450		AM_RANGE(0xfc400010, 0xfc40001f) AM_READWRITE_LEGACY(ff7f_r, ff7f_w)
	453	AM_RANGE(0xfc400010, 0xfc40001f) AM_READWRITE(ff7f_r, ff7f_w)
451	454	AM_RANGE(0xfe000000, 0xffffffff) AM_ROM AM_REGION("user1", 0)
452	455	ADDRESS_MAP_END
453	456

src/mame/drivers/srmp5.c

r14845	r14846
82	82	#ifdef DEBUG_CHAR
83	83	UINT8 m_tileduty[0x2000];
84	84	#endif
	85	DECLARE_READ32_MEMBER(srmp5_palette_r);
	86	DECLARE_WRITE32_MEMBER(srmp5_palette_w);
	87	DECLARE_WRITE32_MEMBER(bank_w);
	88	DECLARE_READ32_MEMBER(tileram_r);
	89	DECLARE_WRITE32_MEMBER(tileram_w);
	90	DECLARE_READ32_MEMBER(spr_r);
	91	DECLARE_WRITE32_MEMBER(spr_w);
	92	DECLARE_READ32_MEMBER(data_r);
	93	DECLARE_WRITE32_MEMBER(input_select_w);
	94	DECLARE_READ32_MEMBER(srmp5_inputs_r);
	95	DECLARE_WRITE32_MEMBER(cmd1_w);
	96	DECLARE_WRITE32_MEMBER(cmd2_w);
	97	DECLARE_READ32_MEMBER(cmd_stat32_r);
	98	DECLARE_READ32_MEMBER(srmp5_vidregs_r);
	99	DECLARE_WRITE32_MEMBER(srmp5_vidregs_w);
	100	DECLARE_READ32_MEMBER(irq_ack_clear);
	101	DECLARE_READ8_MEMBER(cmd1_r);
	102	DECLARE_READ8_MEMBER(cmd2_r);
	103	DECLARE_READ8_MEMBER(cmd_stat8_r);
85	104	};
86	105
87	106
r14845	r14846
201	220	return 0;
202	221	}
203	222
204		static READ32_HANDLER(srmp5_palette_r)
	223	READ32_MEMBER(srmp5_state::srmp5_palette_r)
205	224	{
206		srmp5_state *state = space->machine().driver_data<srmp5_state>();
207	225
208		return state->m_palram[offset];
	226	return m_palram[offset];
209	227	}
210	228
211		static WRITE32_HANDLER(srmp5_palette_w)
	229	WRITE32_MEMBER(srmp5_state::srmp5_palette_w)
212	230	{
213		srmp5_state *state = space->machine().driver_data<srmp5_state>();
214	231
215		COMBINE_DATA(&state->m_palram[offset]);
216		palette_set_color(space->machine(), offset, MAKE_RGB(data << 3 & 0xFF, data >> 2 & 0xFF, data >> 7 & 0xFF));
	232	COMBINE_DATA(&m_palram[offset]);
	233	palette_set_color(machine(), offset, MAKE_RGB(data << 3 & 0xFF, data >> 2 & 0xFF, data >> 7 & 0xFF));
217	234	}
218		static WRITE32_HANDLER(bank_w)
	235	WRITE32_MEMBER(srmp5_state::bank_w)
219	236	{
220		srmp5_state *state = space->machine().driver_data<srmp5_state>();
221	237
222		COMBINE_DATA(&state->m_databank);
	238	COMBINE_DATA(&m_databank);
223	239	}
224	240
225		static READ32_HANDLER(tileram_r)
	241	READ32_MEMBER(srmp5_state::tileram_r)
226	242	{
227		srmp5_state *state = space->machine().driver_data<srmp5_state>();
228	243
229		return state->m_tileram[offset];
	244	return m_tileram[offset];
230	245	}
231	246
232		static WRITE32_HANDLER(tileram_w)
	247	WRITE32_MEMBER(srmp5_state::tileram_w)
233	248	{
234		srmp5_state *state = space->machine().driver_data<srmp5_state>();
235	249
236		state->m_tileram[offset] = data & 0xFFFF; //lower 16bit only
	250	m_tileram[offset] = data & 0xFFFF; //lower 16bit only
237	251	#ifdef DEBUG_CHAR
238		state->m_tileduty[offset >> 6] = 1;
	252	m_tileduty[offset >> 6] = 1;
239	253	#endif
240	254	}
241	255
242		static READ32_HANDLER(spr_r)
	256	READ32_MEMBER(srmp5_state::spr_r)
243	257	{
244		srmp5_state *state = space->machine().driver_data<srmp5_state>();
245	258
246		return state->m_sprram[offset];
	259	return m_sprram[offset];
247	260	}
248	261
249		static WRITE32_HANDLER(spr_w)
	262	WRITE32_MEMBER(srmp5_state::spr_w)
250	263	{
251		srmp5_state *state = space->machine().driver_data<srmp5_state>();
252	264
253		state->m_sprram[offset] = data & 0xFFFF; //lower 16bit only
	265	m_sprram[offset] = data & 0xFFFF; //lower 16bit only
254	266	}
255	267
256		static READ32_HANDLER(data_r)
	268	READ32_MEMBER(srmp5_state::data_r)
257	269	{
258		srmp5_state *state = space->machine().driver_data<srmp5_state>();
259	270	UINT32 data;
260		const UINT8 *usr = space->machine().region("user2")->base();
	271	const UINT8 *usr = machine().region("user2")->base();
261	272
262		data=((state->m_databank>>4)&0xf)*0x100000; //guess
	273	data=((m_databank>>4)&0xf)*0x100000; //guess
263	274	data=usr[data+offset*2]+usr[data+offset*2+1]*256;
264	275	return data|(data<<16);
265	276	}
266	277
267		static WRITE32_HANDLER(input_select_w)
	278	WRITE32_MEMBER(srmp5_state::input_select_w)
268	279	{
269		srmp5_state *state = space->machine().driver_data<srmp5_state>();
270	280
271		state->m_input_select = data & 0x0F;
	281	m_input_select = data & 0x0F;
272	282	}
273	283
274		static READ32_HANDLER(srmp5_inputs_r)
	284	READ32_MEMBER(srmp5_state::srmp5_inputs_r)
275	285	{
276		srmp5_state *state = space->machine().driver_data<srmp5_state>();
277	286	UINT32 ret = 0;
278	287
279		switch (state->m_input_select)
	288	switch (m_input_select)
280	289	{
281	290	case 0x01:
282		ret = input_port_read(space->machine(), "IN0");
	291	ret = input_port_read(machine(), "IN0");
283	292	break;
284	293	case 0x02:
285		ret = input_port_read(space->machine(), "IN1");
	294	ret = input_port_read(machine(), "IN1");
286	295	break;
287	296	case 0x04:
288		ret = input_port_read(space->machine(), "IN2");
	297	ret = input_port_read(machine(), "IN2");
289	298	break;
290	299	case 0x00:
291	300	case 0x08:
292		ret = input_port_read(space->machine(), "IN3");
	301	ret = input_port_read(machine(), "IN3");
293	302	break;
294	303	}
295	304	return ret;
296	305	}
297	306
298	307	//almost all cmds are sound related
299		static WRITE32_HANDLER(cmd1_w)
	308	WRITE32_MEMBER(srmp5_state::cmd1_w)
300	309	{
301		srmp5_state *state = space->machine().driver_data<srmp5_state>();
302	310
303		state->m_cmd1 = data & 0xFF;
	311	m_cmd1 = data & 0xFF;
304	312	logerror("cmd1_w %08X\n", data);
305	313	}
306	314
307		static WRITE32_HANDLER(cmd2_w)
	315	WRITE32_MEMBER(srmp5_state::cmd2_w)
308	316	{
309		srmp5_state *state = space->machine().driver_data<srmp5_state>();
310	317
311		state->m_cmd2 = data & 0xFF;
312		state->m_cmd_stat = 5;
	318	m_cmd2 = data & 0xFF;
	319	m_cmd_stat = 5;
313	320	logerror("cmd2_w %08X\n", data);
314	321	}
315	322
316		static READ32_HANDLER(cmd_stat32_r)
	323	READ32_MEMBER(srmp5_state::cmd_stat32_r)
317	324	{
318		srmp5_state *state = space->machine().driver_data<srmp5_state>();
319	325
320		return state->m_cmd_stat;
	326	return m_cmd_stat;
321	327	}
322	328
323		static READ32_HANDLER(srmp5_vidregs_r)
	329	READ32_MEMBER(srmp5_state::srmp5_vidregs_r)
324	330	{
325		srmp5_state *state = space->machine().driver_data<srmp5_state>();
326	331
327		logerror("vidregs read  %08X %08X\n", offset << 2, state->m_vidregs[offset]);
328		return state->m_vidregs[offset];
	332	logerror("vidregs read  %08X %08X\n", offset << 2, m_vidregs[offset]);
	333	return m_vidregs[offset];
329	334	}
330	335
331		static WRITE32_HANDLER(srmp5_vidregs_w)
	336	WRITE32_MEMBER(srmp5_state::srmp5_vidregs_w)
332	337	{
333		srmp5_state *state = space->machine().driver_data<srmp5_state>();
334	338
335		COMBINE_DATA(&state->m_vidregs[offset]);
	339	COMBINE_DATA(&m_vidregs[offset]);
336	340	if(offset != 0x10C / 4)
337		logerror("vidregs write %08X %08X\n", offset << 2, state->m_vidregs[offset]);
	341	logerror("vidregs write %08X %08X\n", offset << 2, m_vidregs[offset]);
338	342	}
339	343
340		static READ32_HANDLER(irq_ack_clear)
	344	READ32_MEMBER(srmp5_state::irq_ack_clear)
341	345	{
342		cputag_set_input_line(space->machine(), "sub", R3000_IRQ4, CLEAR_LINE);
	346	cputag_set_input_line(machine(), "sub", R3000_IRQ4, CLEAR_LINE);
343	347	return 0;
344	348	}
345	349
r14845	r14846
350	354	AM_RANGE(0x01800000, 0x01800003) AM_RAM //?1
351	355	AM_RANGE(0x01800004, 0x01800007) AM_READ_PORT("DSW1")
352	356	AM_RANGE(0x01800008, 0x0180000b) AM_READ_PORT("DSW2")
353		AM_RANGE(0x0180000c, 0x0180000f) AM_WRITE_LEGACY(bank_w)
354		AM_RANGE(0x01800010, 0x01800013) AM_READ_LEGACY(srmp5_inputs_r) //multiplexed controls (selected by writes to 1c)
	357	AM_RANGE(0x0180000c, 0x0180000f) AM_WRITE(bank_w)
	358	AM_RANGE(0x01800010, 0x01800013) AM_READ(srmp5_inputs_r) //multiplexed controls (selected by writes to 1c)
355	359	AM_RANGE(0x01800014, 0x01800017) AM_READ_PORT("TEST")
356		AM_RANGE(0x0180001c, 0x0180001f) AM_WRITE_LEGACY(input_select_w)//c1 c2 c4 c8 => mahjong inputs (at $10) - bits 0-3
	360	AM_RANGE(0x0180001c, 0x0180001f) AM_WRITE(input_select_w)//c1 c2 c4 c8 => mahjong inputs (at $10) - bits 0-3
357	361	AM_RANGE(0x01800200, 0x01800203) AM_RAM  //sound related ? only few writes after boot
358		AM_RANGE(0x01802000, 0x01802003) AM_WRITE_LEGACY(cmd1_w)
359		AM_RANGE(0x01802004, 0x01802007) AM_WRITE_LEGACY(cmd2_w)
360		AM_RANGE(0x01802008, 0x0180200b) AM_READ_LEGACY(cmd_stat32_r)
361		AM_RANGE(0x01a00000, 0x01bfffff) AM_READ_LEGACY(data_r)
	362	AM_RANGE(0x01802000, 0x01802003) AM_WRITE(cmd1_w)
	363	AM_RANGE(0x01802004, 0x01802007) AM_WRITE(cmd2_w)
	364	AM_RANGE(0x01802008, 0x0180200b) AM_READ(cmd_stat32_r)
	365	AM_RANGE(0x01a00000, 0x01bfffff) AM_READ(data_r)
362	366	AM_RANGE(0x01c00000, 0x01c00003) AM_READNOP // debug? 'Toru'
363	367
364		AM_RANGE(0x0a000000, 0x0a0fffff) AM_READWRITE_LEGACY(spr_r, spr_w)
365		AM_RANGE(0x0a100000, 0x0a17ffff) AM_READWRITE_LEGACY(srmp5_palette_r, srmp5_palette_w)
	368	AM_RANGE(0x0a000000, 0x0a0fffff) AM_READWRITE(spr_r, spr_w)
	369	AM_RANGE(0x0a100000, 0x0a17ffff) AM_READWRITE(srmp5_palette_r, srmp5_palette_w)
366	370	//0?N???A?????????i??????????
367	371	AM_RANGE(0x0a180000, 0x0a180003) AM_READNOP // write 0x00000400
368		AM_RANGE(0x0a180000, 0x0a18011f) AM_READWRITE_LEGACY(srmp5_vidregs_r, srmp5_vidregs_w)
369		AM_RANGE(0x0a200000, 0x0a3fffff) AM_READWRITE_LEGACY(tileram_r, tileram_w)
	372	AM_RANGE(0x0a180000, 0x0a18011f) AM_READWRITE(srmp5_vidregs_r, srmp5_vidregs_w)
	373	AM_RANGE(0x0a200000, 0x0a3fffff) AM_READWRITE(tileram_r, tileram_w)
370	374
371	375	AM_RANGE(0x1eff0000, 0x1eff001f) AM_WRITEONLY
372		AM_RANGE(0x1eff003c, 0x1eff003f) AM_READ_LEGACY(irq_ack_clear)
	376	AM_RANGE(0x1eff003c, 0x1eff003f) AM_READ(irq_ack_clear)
373	377	AM_RANGE(0x1fc00000, 0x1fdfffff) AM_ROM AM_REGION("user1", 0)
374	378	AM_RANGE(0x2fc00000, 0x2fdfffff) AM_ROM AM_REGION("user1", 0)
375	379	ADDRESS_MAP_END
r14845	r14846
382	386	AM_RANGE(0xf000, 0xffff) AM_RAM
383	387	ADDRESS_MAP_END
384	388
385		static READ8_HANDLER(cmd1_r)
	389	READ8_MEMBER(srmp5_state::cmd1_r)
386	390	{
387		srmp5_state *state = space->machine().driver_data<srmp5_state>();
388	391
389		state->m_cmd_stat = 0;
390		return state->m_cmd1;
	392	m_cmd_stat = 0;
	393	return m_cmd1;
391	394	}
392	395
393		static READ8_HANDLER(cmd2_r)
	396	READ8_MEMBER(srmp5_state::cmd2_r)
394	397	{
395		srmp5_state *state = space->machine().driver_data<srmp5_state>();
396	398
397		return state->m_cmd2;
	399	return m_cmd2;
398	400	}
399	401
400		static READ8_HANDLER(cmd_stat8_r)
	402	READ8_MEMBER(srmp5_state::cmd_stat8_r)
401	403	{
402		srmp5_state *state = space->machine().driver_data<srmp5_state>();
403	404
404		return state->m_cmd_stat;
	405	return m_cmd_stat;
405	406	}
406	407
407	408	static ADDRESS_MAP_START( st0016_io, AS_IO, 8, srmp5_state )
408	409	ADDRESS_MAP_GLOBAL_MASK(0xff)
409	410	AM_RANGE(0x00, 0xbf) AM_READ_LEGACY(st0016_vregs_r) AM_WRITE_LEGACY(st0016_vregs_w)
410		AM_RANGE(0xc0, 0xc0) AM_READ_LEGACY(cmd1_r)
411		AM_RANGE(0xc1, 0xc1) AM_READ_LEGACY(cmd2_r)
412		AM_RANGE(0xc2, 0xc2) AM_READ_LEGACY(cmd_stat8_r)
	411	AM_RANGE(0xc0, 0xc0) AM_READ(cmd1_r)
	412	AM_RANGE(0xc1, 0xc1) AM_READ(cmd2_r)
	413	AM_RANGE(0xc2, 0xc2) AM_READ(cmd_stat8_r)
413	414	AM_RANGE(0xe1, 0xe1) AM_WRITE_LEGACY(st0016_rom_bank_w)
414	415	AM_RANGE(0xe7, 0xe7) AM_WRITE_LEGACY(st0016_rom_bank_w)
415	416	AM_RANGE(0xf0, 0xf0) AM_READ_LEGACY(st0016_dma_r)

src/mame/drivers/destroyr.c

r14845	r14846
39	39
40	40	/* devices */
41	41	device_t *m_maincpu;
	42	DECLARE_WRITE8_MEMBER(destroyr_misc_w);
	43	DECLARE_WRITE8_MEMBER(destroyr_cursor_load_w);
	44	DECLARE_WRITE8_MEMBER(destroyr_interrupt_ack_w);
	45	DECLARE_WRITE8_MEMBER(destroyr_output_w);
	46	DECLARE_READ8_MEMBER(destroyr_input_r);
	47	DECLARE_READ8_MEMBER(destroyr_scanline_r);
42	48	};
43	49
44	50
r14845	r14846
160	166	}
161	167
162	168
163		static WRITE8_HANDLER( destroyr_misc_w )
	169	WRITE8_MEMBER(destroyr_state::destroyr_misc_w)
164	170	{
165		destroyr_state *state = space->machine().driver_data<destroyr_state>();
166	171
167	172	/* bits 0 to 2 connect to the sound circuits */
168		state->m_attract = data & 0x01;
169		state->m_noise = data & 0x02;
170		state->m_motor_speed = data & 0x04;
171		state->m_potmask[0] = data & 0x08;
172		state->m_wavemod = data & 0x10;
173		state->m_potmask[1] = data & 0x20;
	173	m_attract = data & 0x01;
	174	m_noise = data & 0x02;
	175	m_motor_speed = data & 0x04;
	176	m_potmask[0] = data & 0x08;
	177	m_wavemod = data & 0x10;
	178	m_potmask[1] = data & 0x20;
174	179
175		coin_lockout_w(space->machine(), 0, !state->m_attract);
176		coin_lockout_w(space->machine(), 1, !state->m_attract);
	180	coin_lockout_w(machine(), 0, !m_attract);
	181	coin_lockout_w(machine(), 1, !m_attract);
177	182	}
178	183
179	184
180		static WRITE8_HANDLER( destroyr_cursor_load_w )
	185	WRITE8_MEMBER(destroyr_state::destroyr_cursor_load_w)
181	186	{
182		destroyr_state *state = space->machine().driver_data<destroyr_state>();
183		state->m_cursor = data;
	187	m_cursor = data;
184	188	watchdog_reset_w(space, offset, data);
185	189	}
186	190
187	191
188		static WRITE8_HANDLER( destroyr_interrupt_ack_w )
	192	WRITE8_MEMBER(destroyr_state::destroyr_interrupt_ack_w)
189	193	{
190		destroyr_state *state = space->machine().driver_data<destroyr_state>();
191		device_set_input_line(state->m_maincpu, 0, CLEAR_LINE);
	194	device_set_input_line(m_maincpu, 0, CLEAR_LINE);
192	195	}
193	196
194	197
195		static WRITE8_HANDLER( destroyr_output_w )
	198	WRITE8_MEMBER(destroyr_state::destroyr_output_w)
196	199	{
197	200	if (offset & 8) destroyr_misc_w(space, 8, data);
198	201
199	202	else switch (offset & 7)
200	203	{
201	204	case 0:
202		set_led_status(space->machine(), 0, data & 1);
	205	set_led_status(machine(), 0, data & 1);
203	206	break;
204	207	case 1:
205		set_led_status(space->machine(), 1, data & 1); /* no second LED present on cab */
	208	set_led_status(machine(), 1, data & 1); /* no second LED present on cab */
206	209	break;
207	210	case 2:
208	211	/* bit 0 => songate */
r14845	r14846
226	229	}
227	230
228	231
229		static READ8_HANDLER( destroyr_input_r )
	232	READ8_MEMBER(destroyr_state::destroyr_input_r)
230	233	{
231		destroyr_state *state = space->machine().driver_data<destroyr_state>();
232	234
233	235	if (offset & 1)
234	236	{
235		return input_port_read(space->machine(), "IN1");
	237	return input_port_read(machine(), "IN1");
236	238	}
237	239
238	240	else
239	241	{
240		UINT8 ret = input_port_read(space->machine(), "IN0");
	242	UINT8 ret = input_port_read(machine(), "IN0");
241	243
242		if (state->m_potsense[0] && state->m_potmask[0])
	244	if (m_potsense[0] && m_potmask[0])
243	245	ret |= 4;
244		if (state->m_potsense[1] && state->m_potmask[1])
	246	if (m_potsense[1] && m_potmask[1])
245	247	ret |= 8;
246	248
247	249	return ret;
r14845	r14846
249	251	}
250	252
251	253
252		static READ8_HANDLER( destroyr_scanline_r )
	254	READ8_MEMBER(destroyr_state::destroyr_scanline_r)
253	255	{
254		return space->machine().primary_screen->vpos();
	256	return machine().primary_screen->vpos();
255	257	}
256	258
257	259
258	260	static ADDRESS_MAP_START( destroyr_map, AS_PROGRAM, 8, destroyr_state )
259	261	ADDRESS_MAP_GLOBAL_MASK(0x7fff)
260	262	AM_RANGE(0x0000, 0x00ff) AM_MIRROR(0xf00) AM_RAM
261		AM_RANGE(0x1000, 0x1fff) AM_READWRITE_LEGACY(destroyr_input_r, destroyr_output_w)
	263	AM_RANGE(0x1000, 0x1fff) AM_READWRITE(destroyr_input_r, destroyr_output_w)
262	264	AM_RANGE(0x2000, 0x2fff) AM_READ_PORT("IN2")
263	265	AM_RANGE(0x3000, 0x30ff) AM_MIRROR(0xf00) AM_WRITEONLY AM_BASE(m_alpha_num_ram)
264	266	AM_RANGE(0x4000, 0x401f) AM_MIRROR(0xfe0) AM_WRITEONLY AM_BASE(m_major_obj_ram)
265		AM_RANGE(0x5000, 0x5000) AM_MIRROR(0xff8) AM_WRITE_LEGACY(destroyr_cursor_load_w)
266		AM_RANGE(0x5001, 0x5001) AM_MIRROR(0xff8) AM_WRITE_LEGACY(destroyr_interrupt_ack_w)
	267	AM_RANGE(0x5000, 0x5000) AM_MIRROR(0xff8) AM_WRITE(destroyr_cursor_load_w)
	268	AM_RANGE(0x5001, 0x5001) AM_MIRROR(0xff8) AM_WRITE(destroyr_interrupt_ack_w)
267	269	AM_RANGE(0x5002, 0x5007) AM_MIRROR(0xff8) AM_WRITEONLY AM_BASE(m_minor_obj_ram)
268		AM_RANGE(0x6000, 0x6fff) AM_READ_LEGACY(destroyr_scanline_r)
	270	AM_RANGE(0x6000, 0x6fff) AM_READ(destroyr_scanline_r)
269	271	AM_RANGE(0x7000, 0x7fff) AM_ROM
270	272	ADDRESS_MAP_END
271	273

src/mame/drivers/feversoc.c

r14845	r14846
72	72
73	73	UINT16 m_x;
74	74	UINT32 *m_spriteram;
	75	DECLARE_WRITE32_MEMBER(fs_paletteram_w);
	76	DECLARE_READ32_MEMBER(in0_r);
	77	DECLARE_WRITE32_MEMBER(output_w);
75	78	};
76	79
77	80
r14845	r14846
112	115	return 0;
113	116	}
114	117
115		static WRITE32_HANDLER( fs_paletteram_w )
	118	WRITE32_MEMBER(feversoc_state::fs_paletteram_w)
116	119	{
117	120	int r,g,b;
118		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
	121	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
119	122
120		r = ((space->machine().generic.paletteram.u32[offset] & 0x001f0000)>>16) << 3;
121		g = ((space->machine().generic.paletteram.u32[offset] & 0x03e00000)>>16) >> 2;
122		b = ((space->machine().generic.paletteram.u32[offset] & 0x7c000000)>>16) >> 7;
	123	r = ((machine().generic.paletteram.u32[offset] & 0x001f0000)>>16) << 3;
	124	g = ((machine().generic.paletteram.u32[offset] & 0x03e00000)>>16) >> 2;
	125	b = ((machine().generic.paletteram.u32[offset] & 0x7c000000)>>16) >> 7;
123	126
124		palette_set_color(space->machine(),offset*2+0,MAKE_RGB(r,g,b));
	127	palette_set_color(machine(),offset*2+0,MAKE_RGB(r,g,b));
125	128
126		r = (space->machine().generic.paletteram.u32[offset] & 0x001f) << 3;
127		g = (space->machine().generic.paletteram.u32[offset] & 0x03e0) >> 2;
128		b = (space->machine().generic.paletteram.u32[offset] & 0x7c00) >> 7;
	129	r = (machine().generic.paletteram.u32[offset] & 0x001f) << 3;
	130	g = (machine().generic.paletteram.u32[offset] & 0x03e0) >> 2;
	131	b = (machine().generic.paletteram.u32[offset] & 0x7c00) >> 7;
129	132
130		palette_set_color(space->machine(),offset*2+1,MAKE_RGB(r,g,b));
	133	palette_set_color(machine(),offset*2+1,MAKE_RGB(r,g,b));
131	134	}
132	135
133		static READ32_HANDLER( in0_r )
	136	READ32_MEMBER(feversoc_state::in0_r)
134	137	{
135		feversoc_state *state = space->machine().driver_data<feversoc_state>();
136	138
137		state->m_x^=0x40; //vblank? eeprom read bit?
138		return (input_port_read(space->machine(), "IN0") | state->m_x) | (input_port_read(space->machine(), "IN1")<<16);
	139	m_x^=0x40; //vblank? eeprom read bit?
	140	return (input_port_read(machine(), "IN0") | m_x) | (input_port_read(machine(), "IN1")<<16);
139	141	}
140	142
141		static WRITE32_HANDLER( output_w )
	143	WRITE32_MEMBER(feversoc_state::output_w)
142	144	{
143	145	if(ACCESSING_BITS_16_31)
144	146	{
145	147	/* probably eeprom stuff too */
146		coin_lockout_w(space->machine(), 0,~data>>16 & 0x40);
147		coin_lockout_w(space->machine(), 1,~data>>16 & 0x40);
148		coin_counter_w(space->machine(), 0,data>>16 & 1);
	148	coin_lockout_w(machine(), 0,~data>>16 & 0x40);
	149	coin_lockout_w(machine(), 1,~data>>16 & 0x40);
	150	coin_counter_w(machine(), 0,data>>16 & 1);
149	151	//data>>16 & 2 coin out
150		coin_counter_w(space->machine(), 1,data>>16 & 4);
	152	coin_counter_w(machine(), 1,data>>16 & 4);
151	153	//data>>16 & 8 coin hopper
152		okim6295_device *oki = space->machine().device<okim6295_device>("oki");
	154	okim6295_device *oki = machine().device<okim6295_device>("oki");
153	155	oki->set_bank_base(0x40000 * (((data>>16) & 0x20)>>5));
154	156	}
155	157	if(ACCESSING_BITS_0_15)
156	158	{
157	159	/* -xxx xxxx lamps*/
158		coin_counter_w(space->machine(), 2,data & 0x2000); //key in
	160	coin_counter_w(machine(), 2,data & 0x2000); //key in
159	161	//data & 0x4000 key out
160	162	}
161	163	}
r14845	r14846
164	166	AM_RANGE(0x00000000, 0x0003ffff) AM_ROM
165	167	AM_RANGE(0x02000000, 0x0203dfff) AM_RAM //work ram
166	168	AM_RANGE(0x0203e000, 0x0203ffff) AM_RAM AM_BASE(m_spriteram)
167		AM_RANGE(0x06000000, 0x06000003) AM_WRITE_LEGACY(output_w)
	169	AM_RANGE(0x06000000, 0x06000003) AM_WRITE(output_w)
168	170	AM_RANGE(0x06000004, 0x06000007) AM_WRITENOP //???
169		AM_RANGE(0x06000008, 0x0600000b) AM_READ_LEGACY(in0_r)
	171	AM_RANGE(0x06000008, 0x0600000b) AM_READ(in0_r)
170	172	AM_RANGE(0x0600000c, 0x0600000f) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff0000)
171	173	//  AM_RANGE(0x06010000, 0x06017fff) AM_RAM //contains RISE11 keys and other related stuff.
172		AM_RANGE(0x06018000, 0x06019fff) AM_RAM_WRITE_LEGACY(fs_paletteram_w) AM_BASE_GENERIC(paletteram)
	174	AM_RANGE(0x06018000, 0x06019fff) AM_RAM_WRITE(fs_paletteram_w) AM_BASE_GENERIC(paletteram)
173	175	ADDRESS_MAP_END
174	176
175	177	static const gfx_layout spi_spritelayout =

src/mame/drivers/vcombat.c

r14845	r14846
102	102	UINT16* m_vid_0_shared_RAM;
103	103	UINT16* m_vid_1_shared_RAM;
104	104	int m_crtc_select;
	105	DECLARE_WRITE16_MEMBER(main_video_write);
	106	DECLARE_READ16_MEMBER(control_1_r);
	107	DECLARE_READ16_MEMBER(control_2_r);
	108	DECLARE_READ16_MEMBER(control_3_r);
	109	DECLARE_WRITE16_MEMBER(wiggle_i860p0_pins_w);
	110	DECLARE_WRITE16_MEMBER(wiggle_i860p1_pins_w);
	111	DECLARE_READ16_MEMBER(main_irqiack_r);
	112	DECLARE_READ16_MEMBER(sound_resetmain_r);
	113	DECLARE_WRITE64_MEMBER(v0_fb_w);
	114	DECLARE_WRITE64_MEMBER(v1_fb_w);
	115	DECLARE_WRITE16_MEMBER(crtc_w);
105	116	};
106	117
107	118	static UINT32 update_screen(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect, int index)
r14845	r14846
157	168	static SCREEN_UPDATE_RGB32( vcombat_aux ) { return update_screen(screen, bitmap, cliprect, 1); }
158	169
159	170
160		static WRITE16_HANDLER( main_video_write )
	171	WRITE16_MEMBER(vcombat_state::main_video_write)
161	172	{
162		vcombat_state *state = space->machine().driver_data<vcombat_state>();
163		int fb = (*state->m_framebuffer_ctrl & 0x20) ? 0 : 1;
164		UINT16 old_data = state->m_m68k_framebuffer[fb][offset];
	173	int fb = (*m_framebuffer_ctrl & 0x20) ? 0 : 1;
	174	UINT16 old_data = m_m68k_framebuffer[fb][offset];
165	175
166	176	/* Transparency mode? */
167		if (*state->m_framebuffer_ctrl & 0x40)
	177	if (*m_framebuffer_ctrl & 0x40)
168	178	{
169	179	if (data == 0x0000)
170	180	return;
r14845	r14846
174	184	if ((data & 0xff00) == 0)
175	185	data = (data & 0x00ff) | (old_data & 0xff00);
176	186
177		COMBINE_DATA(&state->m_m68k_framebuffer[fb][offset]);
	187	COMBINE_DATA(&m_m68k_framebuffer[fb][offset]);
178	188	}
179	189	else
180	190	{
181		COMBINE_DATA(&state->m_m68k_framebuffer[fb][offset]);
	191	COMBINE_DATA(&m_m68k_framebuffer[fb][offset]);
182	192	}
183	193	}
184	194
185		static READ16_HANDLER( control_1_r )
	195	READ16_MEMBER(vcombat_state::control_1_r)
186	196	{
187		return (input_port_read(space->machine(), "IN0") << 8);
	197	return (input_port_read(machine(), "IN0") << 8);
188	198	}
189	199
190		static READ16_HANDLER( control_2_r )
	200	READ16_MEMBER(vcombat_state::control_2_r)
191	201	{
192		return (input_port_read(space->machine(), "IN1") << 8);
	202	return (input_port_read(machine(), "IN1") << 8);
193	203	}
194	204
195		static READ16_HANDLER( control_3_r )
	205	READ16_MEMBER(vcombat_state::control_3_r)
196	206	{
197		return (input_port_read(space->machine(), "IN2") << 8);
	207	return (input_port_read(machine(), "IN2") << 8);
198	208	}
199	209
200	210	static void wiggle_i860_common(device_t *device, UINT16 data)
r14845	r14846
224	234	i860_set_pin(device, DEC_PIN_RESET, 0);
225	235	}
226	236
227		static WRITE16_HANDLER( wiggle_i860p0_pins_w )
	237	WRITE16_MEMBER(vcombat_state::wiggle_i860p0_pins_w)
228	238	{
229		wiggle_i860_common(space->machine().device("vid_0"), data);
	239	wiggle_i860_common(machine().device("vid_0"), data);
230	240	}
231	241
232		static WRITE16_HANDLER( wiggle_i860p1_pins_w )
	242	WRITE16_MEMBER(vcombat_state::wiggle_i860p1_pins_w)
233	243	{
234		wiggle_i860_common(space->machine().device("vid_1"), data);
	244	wiggle_i860_common(machine().device("vid_1"), data);
235	245	}
236	246
237		static READ16_HANDLER( main_irqiack_r )
	247	READ16_MEMBER(vcombat_state::main_irqiack_r)
238	248	{
239	249	//fprintf(stderr, "M0: irq iack\n");
240		device_set_input_line(space->machine().device("maincpu"), M68K_IRQ_1, CLEAR_LINE);
241		//device_set_input_line(space->machine().device("maincpu"), INPUT_LINE_RESET, CLEAR_LINE);
	250	device_set_input_line(machine().device("maincpu"), M68K_IRQ_1, CLEAR_LINE);
	251	//device_set_input_line(machine().device("maincpu"), INPUT_LINE_RESET, CLEAR_LINE);
242	252	return 0;
243	253	}
244	254
245		static READ16_HANDLER( sound_resetmain_r )
	255	READ16_MEMBER(vcombat_state::sound_resetmain_r)
246	256	{
247	257	//fprintf(stderr, "M1: reset line to M0\n");
248		//device_set_input_line(space->machine().device("maincpu"), INPUT_LINE_RESET, PULSE_LINE);
	258	//device_set_input_line(machine().device("maincpu"), INPUT_LINE_RESET, PULSE_LINE);
249	259	return 0;
250	260	}
251	261
252		static WRITE64_HANDLER( v0_fb_w )
	262	WRITE64_MEMBER(vcombat_state::v0_fb_w)
253	263	{
254		vcombat_state *state = space->machine().driver_data<vcombat_state>();
255	264	/* The frame buffer seems to sit on a 32-bit data bus, while the
256	265	i860 uses a 64-bit data bus.  Adjust accordingly.  */
257		char *p = (char *)(state->m_i860_framebuffer[0][0]);
	266	char *p = (char *)(m_i860_framebuffer[0][0]);
258	267	int m = mem_mask;
259	268	int o = (offset << 2);
260	269	if (m & 0xff000000) {
r14845	r14846
273	282
274	283	/* This is just temporary so we can see what each i860 is doing to the
275	284	framebuffer.  */
276		static WRITE64_HANDLER( v1_fb_w )
	285	WRITE64_MEMBER(vcombat_state::v1_fb_w)
277	286	{
278		vcombat_state *state = space->machine().driver_data<vcombat_state>();
279	287	/* The frame buffer seems to sit on a 32-bit data bus, while the
280	288	i860 uses a 64-bit data bus.  Adjust accordingly.  */
281		char *p = (char *)(state->m_i860_framebuffer[1][0]);
	289	char *p = (char *)(m_i860_framebuffer[1][0]);
282	290	int m = mem_mask;
283	291	int o = (offset << 2);
284	292	if (m & 0xff000000) {
r14845	r14846
295	303	}
296	304	}
297	305
298		static WRITE16_HANDLER( crtc_w )
	306	WRITE16_MEMBER(vcombat_state::crtc_w)
299	307	{
300		vcombat_state *state = space->machine().driver_data<vcombat_state>();
301		mc6845_device *crtc = space->machine().device<mc6845_device>("crtc");
	308	mc6845_device *crtc = machine().device<mc6845_device>("crtc");
302	309
303	310	if (crtc == NULL)
304	311	return;
305	312
306		if (state->m_crtc_select == 0)
307		crtc->address_w(*space, 0, data >> 8);
	313	if (m_crtc_select == 0)
	314	crtc->address_w(*&space, 0, data >> 8);
308	315	else
309		crtc->register_w(*space, 0, data >> 8);
	316	crtc->register_w(*&space, 0, data >> 8);
310	317
311		state->m_crtc_select ^= 1;
	318	m_crtc_select ^= 1;
312	319	}
313	320
314	321	static WRITE16_DEVICE_HANDLER( vcombat_dac_w )
r14845	r14846
320	327	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 16, vcombat_state )
321	328	AM_RANGE(0x000000, 0x0fffff) AM_ROM
322	329	AM_RANGE(0x200000, 0x20ffff) AM_RAM
323		AM_RANGE(0x300000, 0x30ffff) AM_WRITE_LEGACY(main_video_write)
	330	AM_RANGE(0x300000, 0x30ffff) AM_WRITE(main_video_write)
324	331
325	332	AM_RANGE(0x400000, 0x43ffff) AM_RAM AM_BASE(m_vid_0_shared_RAM) AM_SHARE("share2")   /* First i860 shared RAM */
326	333	AM_RANGE(0x440000, 0x440003) AM_RAM AM_SHARE("share6")      /* M0->P0 i860 #1 com 1 */
327	334	AM_RANGE(0x480000, 0x480003) AM_RAM AM_SHARE("share7")      /* M0<-P0 i860 #1 com 2 */
328		AM_RANGE(0x4c0000, 0x4c0003) AM_WRITE_LEGACY(wiggle_i860p0_pins_w)   /* i860 #1 stop/start/reset */
	335	AM_RANGE(0x4c0000, 0x4c0003) AM_WRITE(wiggle_i860p0_pins_w)   /* i860 #1 stop/start/reset */
329	336
330	337	AM_RANGE(0x500000, 0x53ffff) AM_RAM AM_BASE(m_vid_1_shared_RAM) AM_SHARE("share3")   /* Second i860 shared RAM */
331	338	AM_RANGE(0x540000, 0x540003) AM_RAM AM_SHARE("share8")      /* M0->P1 i860 #2 com 1 */
332	339	AM_RANGE(0x580000, 0x580003) AM_RAM AM_SHARE("share9")      /* M0<-P1 i860 #2 com 2 */
333		AM_RANGE(0x5c0000, 0x5c0003) AM_WRITE_LEGACY(wiggle_i860p1_pins_w)   /* i860 #2 stop/start/reset */
	340	AM_RANGE(0x5c0000, 0x5c0003) AM_WRITE(wiggle_i860p1_pins_w)   /* i860 #2 stop/start/reset */
334	341
335		AM_RANGE(0x600000, 0x600001) AM_READ_LEGACY(control_1_r)   /* IN0 port */
	342	AM_RANGE(0x600000, 0x600001) AM_READ(control_1_r)   /* IN0 port */
336	343	AM_RANGE(0x600004, 0x600005) AM_RAM AM_SHARE("share5")      /* M0<-M1 */
337		AM_RANGE(0x600008, 0x600009) AM_READ_LEGACY(control_2_r)   /* IN1 port */
	344	AM_RANGE(0x600008, 0x600009) AM_READ(control_2_r)   /* IN1 port */
338	345	AM_RANGE(0x60001c, 0x60001d) AM_NOP
339	346
340		AM_RANGE(0x60000c, 0x60000d) AM_WRITE_LEGACY(crtc_w)
	347	AM_RANGE(0x60000c, 0x60000d) AM_WRITE(crtc_w)
341	348	AM_RANGE(0x600010, 0x600011) AM_RAM AM_BASE(m_framebuffer_ctrl)
342	349	AM_RANGE(0x700000, 0x7007ff) AM_RAM AM_SHARE("nvram")
343		AM_RANGE(0x701000, 0x701001) AM_READ_LEGACY(main_irqiack_r)
344		AM_RANGE(0x702000, 0x702001) AM_READ_LEGACY(control_3_r)
	350	AM_RANGE(0x701000, 0x701001) AM_READ(main_irqiack_r)
	351	AM_RANGE(0x702000, 0x702001) AM_READ(control_3_r)
345	352	AM_RANGE(0x705000, 0x705001) AM_RAM AM_SHARE("share4")      /* M1->M0 */
346	353
347	354	//AM_RANGE(0x703000, 0x703001)      /* Headset rotation axis? */
r14845	r14846
353	360
354	361	/* The first i860 - middle board */
355	362	static ADDRESS_MAP_START( vid_0_map, AS_PROGRAM, 64, vcombat_state )
356		AM_RANGE(0x00000000, 0x0001ffff) AM_RAM_WRITE_LEGACY(v0_fb_w)      /* Shared framebuffer - half of the bits lost to 32-bit bus */
	363	AM_RANGE(0x00000000, 0x0001ffff) AM_RAM_WRITE(v0_fb_w)      /* Shared framebuffer - half of the bits lost to 32-bit bus */
357	364	AM_RANGE(0x20000000, 0x20000007) AM_RAM AM_SHARE("share6")      /* M0<-P0 com 1 (0x440000 in 68k-land) */
358	365	AM_RANGE(0x40000000, 0x401fffff) AM_ROM AM_REGION("gfx", 0)
359	366	AM_RANGE(0x80000000, 0x80000007) AM_RAM AM_SHARE("share7")      /* M0->P0 com 2 (0x480000 in 68k-land) */
r14845	r14846
364	371
365	372	/* The second i860 - top board */
366	373	static ADDRESS_MAP_START( vid_1_map, AS_PROGRAM, 64, vcombat_state )
367		AM_RANGE(0x00000000, 0x0001ffff) AM_RAM_WRITE_LEGACY(v1_fb_w)      /* Half of the bits lost to 32-bit bus */
	374	AM_RANGE(0x00000000, 0x0001ffff) AM_RAM_WRITE(v1_fb_w)      /* Half of the bits lost to 32-bit bus */
368	375	AM_RANGE(0x20000000, 0x20000007) AM_RAM AM_SHARE("share8")      /* M0->P1 com 1 (0x540000 in 68k-land) */
369	376	AM_RANGE(0x40000000, 0x401fffff) AM_ROM AM_REGION("gfx", 0)
370	377	AM_RANGE(0x80000000, 0x80000007) AM_RAM AM_SHARE("share9")         /* M0<-P1 com 2      (0x580000 in 68k-land) */
r14845	r14846
378	385	AM_RANGE(0x000000, 0x03ffff) AM_ROM
379	386	AM_RANGE(0x080000, 0x08ffff) AM_RAM
380	387	AM_RANGE(0x0c0000, 0x0c0001) AM_DEVWRITE_LEGACY("dac", vcombat_dac_w)
381		AM_RANGE(0x140000, 0x140001) AM_READ_LEGACY(sound_resetmain_r)   /* Ping M0's reset line */
	388	AM_RANGE(0x140000, 0x140001) AM_READ(sound_resetmain_r)   /* Ping M0's reset line */
382	389	AM_RANGE(0x180000, 0x180001) AM_RAM AM_SHARE("share4")   /* M1<-M0 */
383	390	AM_RANGE(0x1c0000, 0x1c0001) AM_RAM AM_SHARE("share5")   /* M1->M0 */
384	391	AM_RANGE(0x200000, 0x37ffff) AM_ROM AM_REGION("samples", 0)

src/mame/drivers/pkscram.c

r14845	r14846
31	31	tilemap_t *m_fg_tilemap;
32	32	tilemap_t *m_md_tilemap;
33	33	tilemap_t *m_bg_tilemap;
	34	DECLARE_WRITE16_MEMBER(pkscramble_fgtilemap_w);
	35	DECLARE_WRITE16_MEMBER(pkscramble_mdtilemap_w);
	36	DECLARE_WRITE16_MEMBER(pkscramble_bgtilemap_w);
	37	DECLARE_WRITE16_MEMBER(pkscramble_output_w);
34	38	};
35	39
36	40
37	41	enum { interrupt_scanline=192 };
38	42
39	43
40		static WRITE16_HANDLER( pkscramble_fgtilemap_w )
	44	WRITE16_MEMBER(pkscram_state::pkscramble_fgtilemap_w)
41	45	{
42		pkscram_state *state = space->machine().driver_data<pkscram_state>();
43		COMBINE_DATA(&state->m_pkscramble_fgtilemap_ram[offset]);
44		state->m_fg_tilemap->mark_tile_dirty(offset >> 1);
	46	COMBINE_DATA(&m_pkscramble_fgtilemap_ram[offset]);
	47	m_fg_tilemap->mark_tile_dirty(offset >> 1);
45	48	}
46	49
47		static WRITE16_HANDLER( pkscramble_mdtilemap_w )
	50	WRITE16_MEMBER(pkscram_state::pkscramble_mdtilemap_w)
48	51	{
49		pkscram_state *state = space->machine().driver_data<pkscram_state>();
50		COMBINE_DATA(&state->m_pkscramble_mdtilemap_ram[offset]);
51		state->m_md_tilemap->mark_tile_dirty(offset >> 1);
	52	COMBINE_DATA(&m_pkscramble_mdtilemap_ram[offset]);
	53	m_md_tilemap->mark_tile_dirty(offset >> 1);
52	54	}
53	55
54		static WRITE16_HANDLER( pkscramble_bgtilemap_w )
	56	WRITE16_MEMBER(pkscram_state::pkscramble_bgtilemap_w)
55	57	{
56		pkscram_state *state = space->machine().driver_data<pkscram_state>();
57		COMBINE_DATA(&state->m_pkscramble_bgtilemap_ram[offset]);
58		state->m_bg_tilemap->mark_tile_dirty(offset >> 1);
	58	COMBINE_DATA(&m_pkscramble_bgtilemap_ram[offset]);
	59	m_bg_tilemap->mark_tile_dirty(offset >> 1);
59	60	}
60	61
61	62	// input bit 0x20 in port1 should stay low until bit 0x20 is written here, then
62	63	// it should stay high for some time (currently we cheat keeping the input always active)
63		static WRITE16_HANDLER( pkscramble_output_w )
	64	WRITE16_MEMBER(pkscram_state::pkscramble_output_w)
64	65	{
65		pkscram_state *state = space->machine().driver_data<pkscram_state>();
66	66	// OUTPUT
67	67	// BIT
68	68	// 0x0001 -> STL
r14845	r14846
83	83	// 0x2000 -> vblank interrupt enable
84	84	// 0x4000 -> set on every second frame - not used
85	85
86		state->m_out = data;
	86	m_out = data;
87	87
88		if (!(state->m_out & 0x2000) && state->m_interrupt_line_active)
	88	if (!(m_out & 0x2000) && m_interrupt_line_active)
89	89	{
90		cputag_set_input_line(space->machine(), "maincpu", 1, CLEAR_LINE);
91		state->m_interrupt_line_active = 0;
	90	cputag_set_input_line(machine(), "maincpu", 1, CLEAR_LINE);
	91	m_interrupt_line_active = 0;
92	92	}
93	93
94		coin_counter_w(space->machine(), 0, data & 0x80);
	94	coin_counter_w(machine(), 0, data & 0x80);
95	95	}
96	96
97	97	static ADDRESS_MAP_START( pkscramble_map, AS_PROGRAM, 16, pkscram_state )
r14845	r14846
99	99	AM_RANGE(0x000000, 0x01ffff) AM_ROM
100	100	AM_RANGE(0x040000, 0x0400ff) AM_RAM AM_SHARE("nvram")
101	101	AM_RANGE(0x041000, 0x043fff) AM_RAM // main ram
102		AM_RANGE(0x044000, 0x044fff) AM_RAM_WRITE_LEGACY(pkscramble_fgtilemap_w) AM_BASE(m_pkscramble_fgtilemap_ram) // fg tilemap
103		AM_RANGE(0x045000, 0x045fff) AM_RAM_WRITE_LEGACY(pkscramble_mdtilemap_w) AM_BASE(m_pkscramble_mdtilemap_ram) // md tilemap (just a copy of fg?)
104		AM_RANGE(0x046000, 0x046fff) AM_RAM_WRITE_LEGACY(pkscramble_bgtilemap_w) AM_BASE(m_pkscramble_bgtilemap_ram) // bg tilemap
	102	AM_RANGE(0x044000, 0x044fff) AM_RAM_WRITE(pkscramble_fgtilemap_w) AM_BASE(m_pkscramble_fgtilemap_ram) // fg tilemap
	103	AM_RANGE(0x045000, 0x045fff) AM_RAM_WRITE(pkscramble_mdtilemap_w) AM_BASE(m_pkscramble_mdtilemap_ram) // md tilemap (just a copy of fg?)
	104	AM_RANGE(0x046000, 0x046fff) AM_RAM_WRITE(pkscramble_bgtilemap_w) AM_BASE(m_pkscramble_bgtilemap_ram) // bg tilemap
105	105	AM_RANGE(0x047000, 0x047fff) AM_RAM // unused
106	106	AM_RANGE(0x048000, 0x048fff) AM_RAM_WRITE_LEGACY(paletteram16_xRRRRRGGGGGBBBBB_word_w) AM_BASE_GENERIC(paletteram)
107	107	AM_RANGE(0x049000, 0x049001) AM_READ_PORT("DSW")
108	108	AM_RANGE(0x049004, 0x049005) AM_READ_PORT("INPUTS")
109		AM_RANGE(0x049008, 0x049009) AM_WRITE_LEGACY(pkscramble_output_w)
	109	AM_RANGE(0x049008, 0x049009) AM_WRITE(pkscramble_output_w)
110	110	AM_RANGE(0x049010, 0x049011) AM_WRITENOP
111	111	AM_RANGE(0x049014, 0x049015) AM_WRITENOP
112	112	AM_RANGE(0x049018, 0x049019) AM_WRITENOP

src/mame/drivers/39in1.c

r14845	r14846
54	54	//FILE* audio_dump;
55	55	UINT32 m_words[0x800];
56	56	INT16 m_samples[0x1000];
	57	DECLARE_READ32_MEMBER(pxa255_i2s_r);
	58	DECLARE_WRITE32_MEMBER(pxa255_i2s_w);
	59	DECLARE_READ32_MEMBER(pxa255_dma_r);
	60	DECLARE_WRITE32_MEMBER(pxa255_dma_w);
	61	DECLARE_READ32_MEMBER(pxa255_ostimer_r);
	62	DECLARE_WRITE32_MEMBER(pxa255_ostimer_w);
	63	DECLARE_READ32_MEMBER(pxa255_intc_r);
	64	DECLARE_WRITE32_MEMBER(pxa255_intc_w);
	65	DECLARE_READ32_MEMBER(pxa255_gpio_r);
	66	DECLARE_WRITE32_MEMBER(pxa255_gpio_w);
	67	DECLARE_READ32_MEMBER(pxa255_lcd_r);
	68	DECLARE_WRITE32_MEMBER(pxa255_lcd_w);
	69	DECLARE_READ32_MEMBER(return_zero);
	70	DECLARE_READ32_MEMBER(unknown_r);
	71	DECLARE_READ32_MEMBER(cpld_r);
	72	DECLARE_WRITE32_MEMBER(cpld_w);
	73	DECLARE_READ32_MEMBER(prot_cheater_r);
57	74	};
58	75
59	76
60	77	static void pxa255_dma_irq_check(running_machine& machine);
61		static READ32_HANDLER( pxa255_dma_r );
62		static WRITE32_HANDLER( pxa255_dma_w );
63	78
64		static READ32_HANDLER( pxa255_i2s_r );
65		static WRITE32_HANDLER( pxa255_i2s_w );
66	79
	80
	81
	82
	83
67	84	static void pxa255_ostimer_irq_check(running_machine& machine);
68	85	static TIMER_CALLBACK( pxa255_ostimer_match );
69		static READ32_HANDLER( pxa255_ostimer_r );
70		static WRITE32_HANDLER( pxa255_ostimer_w );
71	86
	87
	88
72	89	static void pxa255_update_interrupts(running_machine& machine);
73	90	static void pxa255_set_irq_line(running_machine& machine, UINT32 line, int state);
74		static READ32_HANDLER( pxa255_intc_r );
75		static WRITE32_HANDLER( pxa255_intc_w );
76	91
77		static READ32_HANDLER( pxa255_gpio_r );
78		static WRITE32_HANDLER( pxa255_gpio_w );
79	92
	93
	94
	95
	96
80	97	static void pxa255_lcd_load_dma_descriptor(address_space* space, UINT32 address, int channel);
81	98	static void pxa255_lcd_irq_check(running_machine& machine);
82	99	static void pxa255_lcd_dma_kickoff(running_machine& machine, int channel);
83	100	static void pxa255_lcd_check_load_next_branch(running_machine& machine, int channel);
84		static READ32_HANDLER( pxa255_lcd_r );
85		static WRITE32_HANDLER( pxa255_lcd_w );
86	101
	102
	103
87	104	#define VERBOSE_LEVEL ( 3 )
88	105
89	106	INLINE void ATTR_PRINTF(3,4) verboselog( running_machine& machine, int n_level, const char* s_fmt, ... )
r14845	r14846
108	125
109	126	*/
110	127
111		static READ32_HANDLER( pxa255_i2s_r )
	128	READ32_MEMBER(_39in1_state::pxa255_i2s_r)
112	129	{
113		_39in1_state *state = space->machine().driver_data<_39in1_state>();
114		PXA255_I2S_Regs *i2s_regs = &state->m_i2s_regs;
	130	PXA255_I2S_Regs *i2s_regs = &m_i2s_regs;
115	131
116	132	switch(PXA255_I2S_BASE_ADDR | (offset << 2))
117	133	{
118	134	case PXA255_SACR0:
119		verboselog( space->machine(), 3, "pxa255_i2s_r: Serial Audio Controller Global Control Register: %08x & %08x\n", i2s_regs->sacr0, mem_mask );
	135	verboselog( machine(), 3, "pxa255_i2s_r: Serial Audio Controller Global Control Register: %08x & %08x\n", i2s_regs->sacr0, mem_mask );
120	136	return i2s_regs->sacr0;
121	137	case PXA255_SACR1:
122		verboselog( space->machine(), 3, "pxa255_i2s_r: Serial Audio Controller I2S/MSB-Justified Control Register: %08x & %08x\n", i2s_regs->sacr1, mem_mask );
	138	verboselog( machine(), 3, "pxa255_i2s_r: Serial Audio Controller I2S/MSB-Justified Control Register: %08x & %08x\n", i2s_regs->sacr1, mem_mask );
123	139	return i2s_regs->sacr1;
124	140	case PXA255_SASR0:
125		verboselog( space->machine(), 3, "pxa255_i2s_r: Serial Audio Controller I2S/MSB-Justified Status Register: %08x & %08x\n", i2s_regs->sasr0, mem_mask );
	141	verboselog( machine(), 3, "pxa255_i2s_r: Serial Audio Controller I2S/MSB-Justified Status Register: %08x & %08x\n", i2s_regs->sasr0, mem_mask );
126	142	return i2s_regs->sasr0;
127	143	case PXA255_SAIMR:
128		verboselog( space->machine(), 3, "pxa255_i2s_r: Serial Audio Interrupt Mask Register: %08x & %08x\n", i2s_regs->saimr, mem_mask );
	144	verboselog( machine(), 3, "pxa255_i2s_r: Serial Audio Interrupt Mask Register: %08x & %08x\n", i2s_regs->saimr, mem_mask );
129	145	return i2s_regs->saimr;
130	146	case PXA255_SAICR:
131		verboselog( space->machine(), 3, "pxa255_i2s_r: Serial Audio Interrupt Clear Register: %08x & %08x\n", i2s_regs->saicr, mem_mask );
	147	verboselog( machine(), 3, "pxa255_i2s_r: Serial Audio Interrupt Clear Register: %08x & %08x\n", i2s_regs->saicr, mem_mask );
132	148	return i2s_regs->saicr;
133	149	case PXA255_SADIV:
134		verboselog( space->machine(), 3, "pxa255_i2s_r: Serial Audio Clock Divider Register: %08x & %08x\n", i2s_regs->sadiv, mem_mask );
	150	verboselog( machine(), 3, "pxa255_i2s_r: Serial Audio Clock Divider Register: %08x & %08x\n", i2s_regs->sadiv, mem_mask );
135	151	return i2s_regs->sadiv;
136	152	case PXA255_SADR:
137		verboselog( space->machine(), 5, "pxa255_i2s_r: Serial Audio Data Register: %08x & %08x\n", i2s_regs->sadr, mem_mask );
	153	verboselog( machine(), 5, "pxa255_i2s_r: Serial Audio Data Register: %08x & %08x\n", i2s_regs->sadr, mem_mask );
138	154	return i2s_regs->sadr;
139	155	default:
140		verboselog( space->machine(), 0, "pxa255_i2s_r: Unknown address: %08x\n", PXA255_I2S_BASE_ADDR | (offset << 2));
	156	verboselog( machine(), 0, "pxa255_i2s_r: Unknown address: %08x\n", PXA255_I2S_BASE_ADDR | (offset << 2));
141	157	break;
142	158	}
143	159	return 0;
144	160	}
145	161
146		static WRITE32_HANDLER( pxa255_i2s_w )
	162	WRITE32_MEMBER(_39in1_state::pxa255_i2s_w)
147	163	{
148		_39in1_state *state = space->machine().driver_data<_39in1_state>();
149		PXA255_I2S_Regs *i2s_regs = &state->m_i2s_regs;
	164	PXA255_I2S_Regs *i2s_regs = &m_i2s_regs;
150	165
151	166	#if 0
152	167	if(!audio_dump)
r14845	r14846
166	181	switch(PXA255_I2S_BASE_ADDR | (offset << 2))
167	182	{
168	183	case PXA255_SACR0:
169		verboselog( space->machine(), 3, "pxa255_i2s_w: Serial Audio Controller Global Control Register: %08x & %08x\n", data, mem_mask );
	184	verboselog( machine(), 3, "pxa255_i2s_w: Serial Audio Controller Global Control Register: %08x & %08x\n", data, mem_mask );
170	185	i2s_regs->sacr0 = data & 0x0000ff3d;
171	186	break;
172	187	case PXA255_SACR1:
173		verboselog( space->machine(), 3, "pxa255_i2s_w: Serial Audio Controller I2S/MSB-Justified Control Register: %08x & %08x\n", data, mem_mask );
	188	verboselog( machine(), 3, "pxa255_i2s_w: Serial Audio Controller I2S/MSB-Justified Control Register: %08x & %08x\n", data, mem_mask );
174	189	i2s_regs->sacr1 = data & 0x00000039;
175	190	break;
176	191	case PXA255_SASR0:
177		verboselog( space->machine(), 3, "pxa255_i2s_w: Serial Audio Controller I2S/MSB-Justified Status Register: %08x & %08x\n", data, mem_mask );
	192	verboselog( machine(), 3, "pxa255_i2s_w: Serial Audio Controller I2S/MSB-Justified Status Register: %08x & %08x\n", data, mem_mask );
178	193	i2s_regs->sasr0 = data & 0x0000ff7f;
179	194	break;
180	195	case PXA255_SAIMR:
181		verboselog( space->machine(), 3, "pxa255_i2s_w: Serial Audio Interrupt Mask Register: %08x & %08x\n", data, mem_mask );
	196	verboselog( machine(), 3, "pxa255_i2s_w: Serial Audio Interrupt Mask Register: %08x & %08x\n", data, mem_mask );
182	197	i2s_regs->saimr = data & 0x00000078;
183	198	break;
184	199	case PXA255_SAICR:
185		verboselog( space->machine(), 3, "pxa255_i2s_w: Serial Audio Interrupt Clear Register: %08x & %08x\n", data, mem_mask );
	200	verboselog( machine(), 3, "pxa255_i2s_w: Serial Audio Interrupt Clear Register: %08x & %08x\n", data, mem_mask );
186	201	if(i2s_regs->saicr & PXA255_SAICR_ROR)
187	202	{
188	203	i2s_regs->sasr0 &= ~PXA255_SASR0_ROR;
r14845	r14846
193	208	}
194	209	break;
195	210	case PXA255_SADIV:
196		verboselog( space->machine(), 3, "pxa255_i2s_w: Serial Audio Clock Divider Register: %08x & %08x\n", data, mem_mask );
	211	verboselog( machine(), 3, "pxa255_i2s_w: Serial Audio Clock Divider Register: %08x & %08x\n", data, mem_mask );
197	212	i2s_regs->sadiv = data & 0x0000007f;
198		dmadac_set_frequency(&state->m_dmadac[0], 2, ((double)147600000 / (double)i2s_regs->sadiv) / 256.0);
199		dmadac_enable(&state->m_dmadac[0], 2, 1);
	213	dmadac_set_frequency(&m_dmadac[0], 2, ((double)147600000 / (double)i2s_regs->sadiv) / 256.0);
	214	dmadac_enable(&m_dmadac[0], 2, 1);
200	215	break;
201	216	case PXA255_SADR:
202		verboselog( space->machine(), 4, "pxa255_i2s_w: Serial Audio Data Register: %08x & %08x\n", data, mem_mask );
	217	verboselog( machine(), 4, "pxa255_i2s_w: Serial Audio Data Register: %08x & %08x\n", data, mem_mask );
203	218	i2s_regs->sadr = data;
204	219	#if 0
205	220	if(audio_dump)
r14845	r14846
209	224	#endif
210	225	break;
211	226	default:
212		verboselog( space->machine(), 0, "pxa255_i2s_w: Unknown address: %08x = %08x & %08x\n", PXA255_I2S_BASE_ADDR | (offset << 2), data, mem_mask);
	227	verboselog( machine(), 0, "pxa255_i2s_w: Unknown address: %08x = %08x & %08x\n", PXA255_I2S_BASE_ADDR | (offset << 2), data, mem_mask);
213	228	break;
214	229	}
215	230	}
r14845	r14846
399	414	pxa255_dma_irq_check(machine);
400	415	}
401	416
402		static READ32_HANDLER( pxa255_dma_r )
	417	READ32_MEMBER(_39in1_state::pxa255_dma_r)
403	418	{
404		_39in1_state *state = space->machine().driver_data<_39in1_state>();
405		PXA255_DMA_Regs *dma_regs = &state->m_dma_regs;
	419	PXA255_DMA_Regs *dma_regs = &m_dma_regs;
406	420
407	421	switch(PXA255_DMA_BASE_ADDR | (offset << 2))
408	422	{
r14845	r14846
410	424	case PXA255_DCSR4:      case PXA255_DCSR5:      case PXA255_DCSR6:      case PXA255_DCSR7:
411	425	case PXA255_DCSR8:      case PXA255_DCSR9:      case PXA255_DCSR10:      case PXA255_DCSR11:
412	426	case PXA255_DCSR12:      case PXA255_DCSR13:      case PXA255_DCSR14:      case PXA255_DCSR15:
413		verboselog( space->machine(), 4, "pxa255_dma_r: DMA Channel Control/Status Register %d: %08x & %08x\n", offset, dma_regs->dcsr[offset], mem_mask );
	427	verboselog( machine(), 4, "pxa255_dma_r: DMA Channel Control/Status Register %d: %08x & %08x\n", offset, dma_regs->dcsr[offset], mem_mask );
414	428	return dma_regs->dcsr[offset];
415	429	case PXA255_DINT:
416		if (0) verboselog( space->machine(), 3, "pxa255_dma_r: DMA Interrupt Register: %08x & %08x\n", dma_regs->dint, mem_mask );
	430	if (0) verboselog( machine(), 3, "pxa255_dma_r: DMA Interrupt Register: %08x & %08x\n", dma_regs->dint, mem_mask );
417	431	return dma_regs->dint;
418	432	case PXA255_DRCMR0:      case PXA255_DRCMR1:      case PXA255_DRCMR2:      case PXA255_DRCMR3:
419	433	case PXA255_DRCMR4:      case PXA255_DRCMR5:      case PXA255_DRCMR6:      case PXA255_DRCMR7:
r14845	r14846
425	439	case PXA255_DRCMR28:   case PXA255_DRCMR29:   case PXA255_DRCMR30:   case PXA255_DRCMR31:
426	440	case PXA255_DRCMR32:   case PXA255_DRCMR33:   case PXA255_DRCMR34:   case PXA255_DRCMR35:
427	441	case PXA255_DRCMR36:   case PXA255_DRCMR37:   case PXA255_DRCMR38:   case PXA255_DRCMR39:
428		verboselog( space->machine(), 3, "pxa255_dma_r: DMA Request to Channel Map Register %d: %08x & %08x\n", offset - (0x100 >> 2), 0, mem_mask );
	442	verboselog( machine(), 3, "pxa255_dma_r: DMA Request to Channel Map Register %d: %08x & %08x\n", offset - (0x100 >> 2), 0, mem_mask );
429	443	return dma_regs->drcmr[offset - (0x100 >> 2)];
430	444	case PXA255_DDADR0:      case PXA255_DDADR1:      case PXA255_DDADR2:      case PXA255_DDADR3:
431	445	case PXA255_DDADR4:      case PXA255_DDADR5:      case PXA255_DDADR6:      case PXA255_DDADR7:
432	446	case PXA255_DDADR8:      case PXA255_DDADR9:      case PXA255_DDADR10:   case PXA255_DDADR11:
433	447	case PXA255_DDADR12:   case PXA255_DDADR13:   case PXA255_DDADR14:   case PXA255_DDADR15:
434		verboselog( space->machine(), 3, "pxa255_dma_r: DMA Descriptor Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask );
	448	verboselog( machine(), 3, "pxa255_dma_r: DMA Descriptor Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask );
435	449	return dma_regs->ddadr[(offset - (0x200 >> 2)) >> 2];
436	450	case PXA255_DSADR0:      case PXA255_DSADR1:      case PXA255_DSADR2:      case PXA255_DSADR3:
437	451	case PXA255_DSADR4:      case PXA255_DSADR5:      case PXA255_DSADR6:      case PXA255_DSADR7:
438	452	case PXA255_DSADR8:      case PXA255_DSADR9:      case PXA255_DSADR10:   case PXA255_DSADR11:
439	453	case PXA255_DSADR12:   case PXA255_DSADR13:   case PXA255_DSADR14:   case PXA255_DSADR15:
440		verboselog( space->machine(), 3, "pxa255_dma_r: DMA Source Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask );
	454	verboselog( machine(), 3, "pxa255_dma_r: DMA Source Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask );
441	455	return dma_regs->dsadr[(offset - (0x200 >> 2)) >> 2];
442	456	case PXA255_DTADR0:      case PXA255_DTADR1:      case PXA255_DTADR2:      case PXA255_DTADR3:
443	457	case PXA255_DTADR4:      case PXA255_DTADR5:      case PXA255_DTADR6:      case PXA255_DTADR7:
444	458	case PXA255_DTADR8:      case PXA255_DTADR9:      case PXA255_DTADR10:   case PXA255_DTADR11:
445	459	case PXA255_DTADR12:   case PXA255_DTADR13:   case PXA255_DTADR14:   case PXA255_DTADR15:
446		verboselog( space->machine(), 3, "pxa255_dma_r: DMA Target Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask );
	460	verboselog( machine(), 3, "pxa255_dma_r: DMA Target Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask );
447	461	return dma_regs->dtadr[(offset - (0x200 >> 2)) >> 2];
448	462	case PXA255_DCMD0:      case PXA255_DCMD1:      case PXA255_DCMD2:      case PXA255_DCMD3:
449	463	case PXA255_DCMD4:      case PXA255_DCMD5:      case PXA255_DCMD6:      case PXA255_DCMD7:
450	464	case PXA255_DCMD8:      case PXA255_DCMD9:      case PXA255_DCMD10:      case PXA255_DCMD11:
451	465	case PXA255_DCMD12:      case PXA255_DCMD13:      case PXA255_DCMD14:      case PXA255_DCMD15:
452		verboselog( space->machine(), 3, "pxa255_dma_r: DMA Command Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask );
	466	verboselog( machine(), 3, "pxa255_dma_r: DMA Command Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, 0, mem_mask );
453	467	return dma_regs->dcmd[(offset - (0x200 >> 2)) >> 2];
454	468	default:
455		verboselog( space->machine(), 0, "pxa255_dma_r: Unknown address: %08x\n", PXA255_DMA_BASE_ADDR | (offset << 2));
	469	verboselog( machine(), 0, "pxa255_dma_r: Unknown address: %08x\n", PXA255_DMA_BASE_ADDR | (offset << 2));
456	470	break;
457	471	}
458	472	return 0;
459	473	}
460	474
461		static WRITE32_HANDLER( pxa255_dma_w )
	475	WRITE32_MEMBER(_39in1_state::pxa255_dma_w)
462	476	{
463		_39in1_state *state = space->machine().driver_data<_39in1_state>();
464		PXA255_DMA_Regs *dma_regs = &state->m_dma_regs;
	477	PXA255_DMA_Regs *dma_regs = &m_dma_regs;
465	478
466	479	switch(PXA255_DMA_BASE_ADDR | (offset << 2))
467	480	{
r14845	r14846
469	482	case PXA255_DCSR4:      case PXA255_DCSR5:      case PXA255_DCSR6:      case PXA255_DCSR7:
470	483	case PXA255_DCSR8:      case PXA255_DCSR9:      case PXA255_DCSR10:      case PXA255_DCSR11:
471	484	case PXA255_DCSR12:      case PXA255_DCSR13:      case PXA255_DCSR14:      case PXA255_DCSR15:
472		if (0) verboselog( space->machine(), 3, "pxa255_dma_w: DMA Channel Control/Status Register %d: %08x & %08x\n", offset, data, mem_mask );
	485	if (0) verboselog( machine(), 3, "pxa255_dma_w: DMA Channel Control/Status Register %d: %08x & %08x\n", offset, data, mem_mask );
473	486	dma_regs->dcsr[offset] &= ~(data & 0x00000007);
474	487	dma_regs->dcsr[offset] &= ~0x60000000;
475	488	dma_regs->dcsr[offset] |= data & 0x60000000;
r14845	r14846
478	491	dma_regs->dcsr[offset] |= PXA255_DCSR_RUN;
479	492	if(data & PXA255_DCSR_NODESCFETCH)
480	493	{
481		verboselog( space->machine(), 0, "              No-Descriptor-Fetch mode is not supported.\n" );
	494	verboselog( machine(), 0, "              No-Descriptor-Fetch mode is not supported.\n" );
482	495	break;
483	496	}
484	497
485		pxa255_dma_load_descriptor_and_start(space->machine(), offset);
	498	pxa255_dma_load_descriptor_and_start(machine(), offset);
486	499	}
487	500	else if(!(data & PXA255_DCSR_RUN))
488	501	{
489	502	dma_regs->dcsr[offset] &= ~PXA255_DCSR_RUN;
490	503	}
491	504
492		pxa255_dma_irq_check(space->machine());
	505	pxa255_dma_irq_check(machine());
493	506	break;
494	507	case PXA255_DINT:
495		verboselog( space->machine(), 3, "pxa255_dma_w: DMA Interrupt Register: %08x & %08x\n", data, mem_mask );
	508	verboselog( machine(), 3, "pxa255_dma_w: DMA Interrupt Register: %08x & %08x\n", data, mem_mask );
496	509	dma_regs->dint &= ~data;
497	510	break;
498	511	case PXA255_DRCMR0:      case PXA255_DRCMR1:      case PXA255_DRCMR2:      case PXA255_DRCMR3:
r14845	r14846
505	518	case PXA255_DRCMR28:   case PXA255_DRCMR29:   case PXA255_DRCMR30:   case PXA255_DRCMR31:
506	519	case PXA255_DRCMR32:   case PXA255_DRCMR33:   case PXA255_DRCMR34:   case PXA255_DRCMR35:
507	520	case PXA255_DRCMR36:   case PXA255_DRCMR37:   case PXA255_DRCMR38:   case PXA255_DRCMR39:
508		verboselog( space->machine(), 3, "pxa255_dma_w: DMA Request to Channel Map Register %d: %08x & %08x\n", offset - (0x100 >> 2), data, mem_mask );
	521	verboselog( machine(), 3, "pxa255_dma_w: DMA Request to Channel Map Register %d: %08x & %08x\n", offset - (0x100 >> 2), data, mem_mask );
509	522	dma_regs->drcmr[offset - (0x100 >> 2)] = data & 0x0000008f;
510	523	break;
511	524	case PXA255_DDADR0:      case PXA255_DDADR1:      case PXA255_DDADR2:      case PXA255_DDADR3:
512	525	case PXA255_DDADR4:      case PXA255_DDADR5:      case PXA255_DDADR6:      case PXA255_DDADR7:
513	526	case PXA255_DDADR8:      case PXA255_DDADR9:      case PXA255_DDADR10:   case PXA255_DDADR11:
514	527	case PXA255_DDADR12:   case PXA255_DDADR13:   case PXA255_DDADR14:   case PXA255_DDADR15:
515		verboselog( space->machine(), 3, "pxa255_dma_w: DMA Descriptor Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask );
	528	verboselog( machine(), 3, "pxa255_dma_w: DMA Descriptor Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask );
516	529	dma_regs->ddadr[(offset - (0x200 >> 2)) >> 2] = data & 0xfffffff1;
517	530	break;
518	531	case PXA255_DSADR0:      case PXA255_DSADR1:      case PXA255_DSADR2:      case PXA255_DSADR3:
519	532	case PXA255_DSADR4:      case PXA255_DSADR5:      case PXA255_DSADR6:      case PXA255_DSADR7:
520	533	case PXA255_DSADR8:      case PXA255_DSADR9:      case PXA255_DSADR10:   case PXA255_DSADR11:
521	534	case PXA255_DSADR12:   case PXA255_DSADR13:   case PXA255_DSADR14:   case PXA255_DSADR15:
522		verboselog( space->machine(), 3, "pxa255_dma_w: DMA Source Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask );
	535	verboselog( machine(), 3, "pxa255_dma_w: DMA Source Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask );
523	536	dma_regs->dsadr[(offset - (0x200 >> 2)) >> 2] = data & 0xfffffffc;
524	537	break;
525	538	case PXA255_DTADR0:      case PXA255_DTADR1:      case PXA255_DTADR2:      case PXA255_DTADR3:
526	539	case PXA255_DTADR4:      case PXA255_DTADR5:      case PXA255_DTADR6:      case PXA255_DTADR7:
527	540	case PXA255_DTADR8:      case PXA255_DTADR9:      case PXA255_DTADR10:   case PXA255_DTADR11:
528	541	case PXA255_DTADR12:   case PXA255_DTADR13:   case PXA255_DTADR14:   case PXA255_DTADR15:
529		verboselog( space->machine(), 3, "pxa255_dma_w: DMA Target Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask );
	542	verboselog( machine(), 3, "pxa255_dma_w: DMA Target Address Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask );
530	543	dma_regs->dtadr[(offset - (0x200 >> 2)) >> 2] = data & 0xfffffffc;
531	544	break;
532	545	case PXA255_DCMD0:      case PXA255_DCMD1:      case PXA255_DCMD2:      case PXA255_DCMD3:
533	546	case PXA255_DCMD4:      case PXA255_DCMD5:      case PXA255_DCMD6:      case PXA255_DCMD7:
534	547	case PXA255_DCMD8:      case PXA255_DCMD9:      case PXA255_DCMD10:      case PXA255_DCMD11:
535	548	case PXA255_DCMD12:      case PXA255_DCMD13:      case PXA255_DCMD14:      case PXA255_DCMD15:
536		verboselog( space->machine(), 3, "pxa255_dma_w: DMA Command Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask );
	549	verboselog( machine(), 3, "pxa255_dma_w: DMA Command Register %d: %08x & %08x\n", (offset - (0x200 >> 2)) >> 2, data, mem_mask );
537	550	dma_regs->dcmd[(offset - (0x200 >> 2)) >> 2] = data & 0xf067dfff;
538	551	break;
539	552	default:
540		verboselog( space->machine(), 0, "pxa255_dma_w: Unknown address: %08x = %08x & %08x\n", PXA255_DMA_BASE_ADDR | (offset << 2), data, mem_mask);
	553	verboselog( machine(), 0, "pxa255_dma_w: Unknown address: %08x = %08x & %08x\n", PXA255_DMA_BASE_ADDR | (offset << 2), data, mem_mask);
541	554	break;
542	555	}
543	556	}
r14845	r14846
572	585	pxa255_ostimer_irq_check(machine);
573	586	}
574	587
575		static READ32_HANDLER( pxa255_ostimer_r )
	588	READ32_MEMBER(_39in1_state::pxa255_ostimer_r)
576	589	{
577		_39in1_state *state = space->machine().driver_data<_39in1_state>();
578		PXA255_OSTMR_Regs *ostimer_regs = &state->m_ostimer_regs;
	590	PXA255_OSTMR_Regs *ostimer_regs = &m_ostimer_regs;
579	591
580	592	switch(PXA255_OSTMR_BASE_ADDR | (offset << 2))
581	593	{
582	594	case PXA255_OSMR0:
583		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_r: OS Timer Match Register 0: %08x & %08x\n", ostimer_regs->osmr[0], mem_mask );
	595	if (0) verboselog( machine(), 3, "pxa255_ostimer_r: OS Timer Match Register 0: %08x & %08x\n", ostimer_regs->osmr[0], mem_mask );
584	596	return ostimer_regs->osmr[0];
585	597	case PXA255_OSMR1:
586		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_r: OS Timer Match Register 1: %08x & %08x\n", ostimer_regs->osmr[1], mem_mask );
	598	if (0) verboselog( machine(), 3, "pxa255_ostimer_r: OS Timer Match Register 1: %08x & %08x\n", ostimer_regs->osmr[1], mem_mask );
587	599	return ostimer_regs->osmr[1];
588	600	case PXA255_OSMR2:
589		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_r: OS Timer Match Register 2: %08x & %08x\n", ostimer_regs->osmr[2], mem_mask );
	601	if (0) verboselog( machine(), 3, "pxa255_ostimer_r: OS Timer Match Register 2: %08x & %08x\n", ostimer_regs->osmr[2], mem_mask );
590	602	return ostimer_regs->osmr[2];
591	603	case PXA255_OSMR3:
592		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_r: OS Timer Match Register 3: %08x & %08x\n", ostimer_regs->osmr[3], mem_mask );
	604	if (0) verboselog( machine(), 3, "pxa255_ostimer_r: OS Timer Match Register 3: %08x & %08x\n", ostimer_regs->osmr[3], mem_mask );
593	605	return ostimer_regs->osmr[3];
594	606	case PXA255_OSCR:
595		if (0) verboselog( space->machine(), 4, "pxa255_ostimer_r: OS Timer Count Register: %08x & %08x\n", ostimer_regs->oscr, mem_mask );
	607	if (0) verboselog( machine(), 4, "pxa255_ostimer_r: OS Timer Count Register: %08x & %08x\n", ostimer_regs->oscr, mem_mask );
596	608	// free-running 3.something MHz counter.  this is a complete hack.
597	609	ostimer_regs->oscr += 0x300;
598	610	return ostimer_regs->oscr;
599	611	case PXA255_OSSR:
600		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_r: OS Timer Status Register: %08x & %08x\n", ostimer_regs->ossr, mem_mask );
	612	if (0) verboselog( machine(), 3, "pxa255_ostimer_r: OS Timer Status Register: %08x & %08x\n", ostimer_regs->ossr, mem_mask );
601	613	return ostimer_regs->ossr;
602	614	case PXA255_OWER:
603		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_r: OS Timer Watchdog Match Enable Register: %08x & %08x\n", ostimer_regs->ower, mem_mask );
	615	if (0) verboselog( machine(), 3, "pxa255_ostimer_r: OS Timer Watchdog Match Enable Register: %08x & %08x\n", ostimer_regs->ower, mem_mask );
604	616	return ostimer_regs->ower;
605	617	case PXA255_OIER:
606		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_r: OS Timer Interrupt Enable Register: %08x & %08x\n", ostimer_regs->oier, mem_mask );
	618	if (0) verboselog( machine(), 3, "pxa255_ostimer_r: OS Timer Interrupt Enable Register: %08x & %08x\n", ostimer_regs->oier, mem_mask );
607	619	return ostimer_regs->oier;
608	620	default:
609		if (0) verboselog( space->machine(), 0, "pxa255_ostimer_r: Unknown address: %08x\n", PXA255_OSTMR_BASE_ADDR | (offset << 2));
	621	if (0) verboselog( machine(), 0, "pxa255_ostimer_r: Unknown address: %08x\n", PXA255_OSTMR_BASE_ADDR | (offset << 2));
610	622	break;
611	623	}
612	624	return 0;
613	625	}
614	626
615		static WRITE32_HANDLER( pxa255_ostimer_w )
	627	WRITE32_MEMBER(_39in1_state::pxa255_ostimer_w)
616	628	{
617		_39in1_state *state = space->machine().driver_data<_39in1_state>();
618		PXA255_OSTMR_Regs *ostimer_regs = &state->m_ostimer_regs;
	629	PXA255_OSTMR_Regs *ostimer_regs = &m_ostimer_regs;
619	630
620	631	switch(PXA255_OSTMR_BASE_ADDR | (offset << 2))
621	632	{
622	633	case PXA255_OSMR0:
623		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_w: OS Timer Match Register 0: %08x & %08x\n", data, mem_mask );
	634	if (0) verboselog( machine(), 3, "pxa255_ostimer_w: OS Timer Match Register 0: %08x & %08x\n", data, mem_mask );
624	635	ostimer_regs->osmr[0] = data;
625	636	if(ostimer_regs->oier & PXA255_OIER_E0)
626	637	{
r14845	r14846
631	642	}
632	643	break;
633	644	case PXA255_OSMR1:
634		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_w: OS Timer Match Register 1: %08x & %08x\n", data, mem_mask );
	645	if (0) verboselog( machine(), 3, "pxa255_ostimer_w: OS Timer Match Register 1: %08x & %08x\n", data, mem_mask );
635	646	ostimer_regs->osmr[1] = data;
636	647	if(ostimer_regs->oier & PXA255_OIER_E1)
637	648	{
r14845	r14846
641	652	}
642	653	break;
643	654	case PXA255_OSMR2:
644		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_w: OS Timer Match Register 2: %08x & %08x\n", data, mem_mask );
	655	if (0) verboselog( machine(), 3, "pxa255_ostimer_w: OS Timer Match Register 2: %08x & %08x\n", data, mem_mask );
645	656	ostimer_regs->osmr[2] = data;
646	657	if(ostimer_regs->oier & PXA255_OIER_E2)
647	658	{
r14845	r14846
651	662	}
652	663	break;
653	664	case PXA255_OSMR3:
654		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_w: OS Timer Match Register 3: %08x & %08x\n", data, mem_mask );
	665	if (0) verboselog( machine(), 3, "pxa255_ostimer_w: OS Timer Match Register 3: %08x & %08x\n", data, mem_mask );
655	666	ostimer_regs->osmr[3] = data;
656	667	if(ostimer_regs->oier & PXA255_OIER_E3)
657	668	{
r14845	r14846
661	672	}
662	673	break;
663	674	case PXA255_OSCR:
664		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_w: OS Timer Count Register: %08x & %08x\n", data, mem_mask );
	675	if (0) verboselog( machine(), 3, "pxa255_ostimer_w: OS Timer Count Register: %08x & %08x\n", data, mem_mask );
665	676	ostimer_regs->oscr = data;
666	677	break;
667	678	case PXA255_OSSR:
668		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_w: OS Timer Status Register: %08x & %08x\n", data, mem_mask );
	679	if (0) verboselog( machine(), 3, "pxa255_ostimer_w: OS Timer Status Register: %08x & %08x\n", data, mem_mask );
669	680	ostimer_regs->ossr &= ~data;
670		pxa255_ostimer_irq_check(space->machine());
	681	pxa255_ostimer_irq_check(machine());
671	682	break;
672	683	case PXA255_OWER:
673		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_w: OS Timer Watchdog Enable Register: %08x & %08x\n", data, mem_mask );
	684	if (0) verboselog( machine(), 3, "pxa255_ostimer_w: OS Timer Watchdog Enable Register: %08x & %08x\n", data, mem_mask );
674	685	ostimer_regs->ower = data & 0x00000001;
675	686	break;
676	687	case PXA255_OIER:
677	688	{
678	689	int index = 0;
679		if (0) verboselog( space->machine(), 3, "pxa255_ostimer_w: OS Timer Interrupt Enable Register: %08x & %08x\n", data, mem_mask );
	690	if (0) verboselog( machine(), 3, "pxa255_ostimer_w: OS Timer Interrupt Enable Register: %08x & %08x\n", data, mem_mask );
680	691	ostimer_regs->oier = data & 0x0000000f;
681	692	for(index = 0; index < 4; index++)
682	693	{
r14845	r14846
691	702	break;
692	703	}
693	704	default:
694		verboselog( space->machine(), 0, "pxa255_ostimer_w: Unknown address: %08x = %08x & %08x\n", PXA255_OSTMR_BASE_ADDR | (offset << 2), data, mem_mask);
	705	verboselog( machine(), 0, "pxa255_ostimer_w: Unknown address: %08x = %08x & %08x\n", PXA255_OSTMR_BASE_ADDR | (offset << 2), data, mem_mask);
695	706	break;
696	707	}
697	708	}
r14845	r14846
726	737	pxa255_update_interrupts(machine);
727	738	}
728	739
729		static READ32_HANDLER( pxa255_intc_r )
	740	READ32_MEMBER(_39in1_state::pxa255_intc_r)
730	741	{
731		_39in1_state *state = space->machine().driver_data<_39in1_state>();
732		PXA255_INTC_Regs *intc_regs = &state->m_intc_regs;
	742	PXA255_INTC_Regs *intc_regs = &m_intc_regs;
733	743
734	744	switch(PXA255_INTC_BASE_ADDR | (offset << 2))
735	745	{
736	746	case PXA255_ICIP:
737		if (0) verboselog( space->machine(), 3, "pxa255_intc_r: Interrupt Controller IRQ Pending Register: %08x & %08x\n", intc_regs->icip, mem_mask );
	747	if (0) verboselog( machine(), 3, "pxa255_intc_r: Interrupt Controller IRQ Pending Register: %08x & %08x\n", intc_regs->icip, mem_mask );
738	748	return intc_regs->icip;
739	749	case PXA255_ICMR:
740		if (0) verboselog( space->machine(), 3, "pxa255_intc_r: Interrupt Controller Mask Register: %08x & %08x\n", intc_regs->icmr, mem_mask );
	750	if (0) verboselog( machine(), 3, "pxa255_intc_r: Interrupt Controller Mask Register: %08x & %08x\n", intc_regs->icmr, mem_mask );
741	751	return intc_regs->icmr;
742	752	case PXA255_ICLR:
743		if (0) verboselog( space->machine(), 3, "pxa255_intc_r: Interrupt Controller Level Register: %08x & %08x\n", intc_regs->iclr, mem_mask );
	753	if (0) verboselog( machine(), 3, "pxa255_intc_r: Interrupt Controller Level Register: %08x & %08x\n", intc_regs->iclr, mem_mask );
744	754	return intc_regs->iclr;
745	755	case PXA255_ICFP:
746		if (0) verboselog( space->machine(), 3, "pxa255_intc_r: Interrupt Controller FIQ Pending Register: %08x & %08x\n", intc_regs->icfp, mem_mask );
	756	if (0) verboselog( machine(), 3, "pxa255_intc_r: Interrupt Controller FIQ Pending Register: %08x & %08x\n", intc_regs->icfp, mem_mask );
747	757	return intc_regs->icfp;
748	758	case PXA255_ICPR:
749		if (0) verboselog( space->machine(), 3, "pxa255_intc_r: Interrupt Controller Pending Register: %08x & %08x\n", intc_regs->icpr, mem_mask );
	759	if (0) verboselog( machine(), 3, "pxa255_intc_r: Interrupt Controller Pending Register: %08x & %08x\n", intc_regs->icpr, mem_mask );
750	760	return intc_regs->icpr;
751	761	case PXA255_ICCR:
752		if (0) verboselog( space->machine(), 3, "pxa255_intc_r: Interrupt Controller Control Register: %08x & %08x\n", intc_regs->iccr, mem_mask );
	762	if (0) verboselog( machine(), 3, "pxa255_intc_r: Interrupt Controller Control Register: %08x & %08x\n", intc_regs->iccr, mem_mask );
753	763	return intc_regs->iccr;
754	764	default:
755		verboselog( space->machine(), 0, "pxa255_intc_r: Unknown address: %08x\n", PXA255_INTC_BASE_ADDR | (offset << 2));
	765	verboselog( machine(), 0, "pxa255_intc_r: Unknown address: %08x\n", PXA255_INTC_BASE_ADDR | (offset << 2));
756	766	break;
757	767	}
758	768	return 0;
759	769	}
760	770
761		static WRITE32_HANDLER( pxa255_intc_w )
	771	WRITE32_MEMBER(_39in1_state::pxa255_intc_w)
762	772	{
763		_39in1_state *state = space->machine().driver_data<_39in1_state>();
764		PXA255_INTC_Regs *intc_regs = &state->m_intc_regs;
	773	PXA255_INTC_Regs *intc_regs = &m_intc_regs;
765	774
766	775	switch(PXA255_INTC_BASE_ADDR | (offset << 2))
767	776	{
768	777	case PXA255_ICIP:
769		verboselog( space->machine(), 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller IRQ Pending Register: %08x & %08x\n", data, mem_mask );
	778	verboselog( machine(), 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller IRQ Pending Register: %08x & %08x\n", data, mem_mask );
770	779	break;
771	780	case PXA255_ICMR:
772		if (0) verboselog( space->machine(), 3, "pxa255_intc_w: Interrupt Controller Mask Register: %08x & %08x\n", data, mem_mask );
	781	if (0) verboselog( machine(), 3, "pxa255_intc_w: Interrupt Controller Mask Register: %08x & %08x\n", data, mem_mask );
773	782	intc_regs->icmr = data & 0xfffe7f00;
774	783	break;
775	784	case PXA255_ICLR:
776		if (0) verboselog( space->machine(), 3, "pxa255_intc_w: Interrupt Controller Level Register: %08x & %08x\n", data, mem_mask );
	785	if (0) verboselog( machine(), 3, "pxa255_intc_w: Interrupt Controller Level Register: %08x & %08x\n", data, mem_mask );
777	786	intc_regs->iclr = data & 0xfffe7f00;
778	787	break;
779	788	case PXA255_ICFP:
780		if (0) verboselog( space->machine(), 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller FIQ Pending Register: %08x & %08x\n", data, mem_mask );
	789	if (0) verboselog( machine(), 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller FIQ Pending Register: %08x & %08x\n", data, mem_mask );
781	790	break;
782	791	case PXA255_ICPR:
783		if (0) verboselog( space->machine(), 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller Pending Register: %08x & %08x\n", data, mem_mask );
	792	if (0) verboselog( machine(), 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller Pending Register: %08x & %08x\n", data, mem_mask );
784	793	break;
785	794	case PXA255_ICCR:
786		if (0) verboselog( space->machine(), 3, "pxa255_intc_w: Interrupt Controller Control Register: %08x & %08x\n", data, mem_mask );
	795	if (0) verboselog( machine(), 3, "pxa255_intc_w: Interrupt Controller Control Register: %08x & %08x\n", data, mem_mask );
787	796	intc_regs->iccr = data & 0x00000001;
788	797	break;
789	798	default:
790		verboselog( space->machine(), 0, "pxa255_intc_w: Unknown address: %08x = %08x & %08x\n", PXA255_INTC_BASE_ADDR | (offset << 2), data, mem_mask);
	799	verboselog( machine(), 0, "pxa255_intc_w: Unknown address: %08x = %08x & %08x\n", PXA255_INTC_BASE_ADDR | (offset << 2), data, mem_mask);
791	800	break;
792	801	}
793	802	}
r14845	r14846
800	809
801	810	*/
802	811
803		static READ32_HANDLER( pxa255_gpio_r )
	812	READ32_MEMBER(_39in1_state::pxa255_gpio_r)
804	813	{
805		_39in1_state *state = space->machine().driver_data<_39in1_state>();
806		PXA255_GPIO_Regs *gpio_regs = &state->m_gpio_regs;
	814	PXA255_GPIO_Regs *gpio_regs = &m_gpio_regs;
807	815
808	816	switch(PXA255_GPIO_BASE_ADDR | (offset << 2))
809	817	{
810	818	case PXA255_GPLR0:
811		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Pin-Level Register 0: %08x & %08x\n", gpio_regs->gplr0 | (1 << 1), mem_mask );
812		return gpio_regs->gplr0 | (1 << 1) | (state->m_eeprom->read_bit() << 5); // Must be on.  Probably a DIP switch.
	819	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Pin-Level Register 0: %08x & %08x\n", gpio_regs->gplr0 | (1 << 1), mem_mask );
	820	return gpio_regs->gplr0 | (1 << 1) | (m_eeprom->read_bit() << 5); // Must be on.  Probably a DIP switch.
813	821	case PXA255_GPLR1:
814		verboselog( space->machine(), 3, "pxa255_gpio_r: *Not Yet Implemented* GPIO Pin-Level Register 1: %08x & %08x\n", gpio_regs->gplr1, mem_mask );
	822	verboselog( machine(), 3, "pxa255_gpio_r: *Not Yet Implemented* GPIO Pin-Level Register 1: %08x & %08x\n", gpio_regs->gplr1, mem_mask );
815	823	return 0xff9fffff;
816	824	/*
817	825	0x200000 = flip screen
818	826	*/
819	827	case PXA255_GPLR2:
820		verboselog( space->machine(), 3, "pxa255_gpio_r: *Not Yet Implemented* GPIO Pin-Level Register 2: %08x & %08x\n", gpio_regs->gplr2, mem_mask );
	828	verboselog( machine(), 3, "pxa255_gpio_r: *Not Yet Implemented* GPIO Pin-Level Register 2: %08x & %08x\n", gpio_regs->gplr2, mem_mask );
821	829	return gpio_regs->gplr2;
822	830	case PXA255_GPDR0:
823		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Pin Direction Register 0: %08x & %08x\n", gpio_regs->gpdr0, mem_mask );
	831	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Pin Direction Register 0: %08x & %08x\n", gpio_regs->gpdr0, mem_mask );
824	832	return gpio_regs->gpdr0;
825	833	case PXA255_GPDR1:
826		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Pin Direction Register 1: %08x & %08x\n", gpio_regs->gpdr1, mem_mask );
	834	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Pin Direction Register 1: %08x & %08x\n", gpio_regs->gpdr1, mem_mask );
827	835	return gpio_regs->gpdr1;
828	836	case PXA255_GPDR2:
829		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Pin Direction Register 2: %08x & %08x\n", gpio_regs->gpdr2, mem_mask );
	837	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Pin Direction Register 2: %08x & %08x\n", gpio_regs->gpdr2, mem_mask );
830	838	return gpio_regs->gpdr2;
831	839	case PXA255_GPSR0:
832		verboselog( space->machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Set Register 0: %08x & %08x\n", space->machine().rand(), mem_mask );
833		return space->machine().rand();
	840	verboselog( machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Set Register 0: %08x & %08x\n", machine().rand(), mem_mask );
	841	return machine().rand();
834	842	case PXA255_GPSR1:
835		verboselog( space->machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Set Register 1: %08x & %08x\n", space->machine().rand(), mem_mask );
836		return space->machine().rand();
	843	verboselog( machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Set Register 1: %08x & %08x\n", machine().rand(), mem_mask );
	844	return machine().rand();
837	845	case PXA255_GPSR2:
838		verboselog( space->machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Set Register 2: %08x & %08x\n", space->machine().rand(), mem_mask );
839		return space->machine().rand();
	846	verboselog( machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Set Register 2: %08x & %08x\n", machine().rand(), mem_mask );
	847	return machine().rand();
840	848	case PXA255_GPCR0:
841		verboselog( space->machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Clear Register 0: %08x & %08x\n", space->machine().rand(), mem_mask );
842		return space->machine().rand();
	849	verboselog( machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Clear Register 0: %08x & %08x\n", machine().rand(), mem_mask );
	850	return machine().rand();
843	851	case PXA255_GPCR1:
844		verboselog( space->machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Clear Register 1: %08x & %08x\n", space->machine().rand(), mem_mask );
845		return space->machine().rand();
	852	verboselog( machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Clear Register 1: %08x & %08x\n", machine().rand(), mem_mask );
	853	return machine().rand();
846	854	case PXA255_GPCR2:
847		verboselog( space->machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Clear Register 2: %08x & %08x\n", space->machine().rand(), mem_mask );
848		return space->machine().rand();
	855	verboselog( machine(), 3, "pxa255_gpio_r: (Invalid Read) GPIO Pin Output Clear Register 2: %08x & %08x\n", machine().rand(), mem_mask );
	856	return machine().rand();
849	857	case PXA255_GRER0:
850		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 0: %08x & %08x\n", gpio_regs->grer0, mem_mask );
	858	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 0: %08x & %08x\n", gpio_regs->grer0, mem_mask );
851	859	return gpio_regs->grer0;
852	860	case PXA255_GRER1:
853		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 1: %08x & %08x\n", gpio_regs->grer1, mem_mask );
	861	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 1: %08x & %08x\n", gpio_regs->grer1, mem_mask );
854	862	return gpio_regs->grer1;
855	863	case PXA255_GRER2:
856		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 2: %08x & %08x\n", gpio_regs->grer2, mem_mask );
	864	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Rising Edge Detect Enable Register 2: %08x & %08x\n", gpio_regs->grer2, mem_mask );
857	865	return gpio_regs->grer2;
858	866	case PXA255_GFER0:
859		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 0: %08x & %08x\n", gpio_regs->gfer0, mem_mask );
	867	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 0: %08x & %08x\n", gpio_regs->gfer0, mem_mask );
860	868	return gpio_regs->gfer0;
861	869	case PXA255_GFER1:
862		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 1: %08x & %08x\n", gpio_regs->gfer1, mem_mask );
	870	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 1: %08x & %08x\n", gpio_regs->gfer1, mem_mask );
863	871	return gpio_regs->gfer1;
864	872	case PXA255_GFER2:
865		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 2: %08x & %08x\n", gpio_regs->gfer2, mem_mask );
	873	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Falling Edge Detect Enable Register 2: %08x & %08x\n", gpio_regs->gfer2, mem_mask );
866	874	return gpio_regs->gfer2;
867	875	case PXA255_GEDR0:
868		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 0: %08x & %08x\n", gpio_regs->gedr0, mem_mask );
	876	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 0: %08x & %08x\n", gpio_regs->gedr0, mem_mask );
869	877	return gpio_regs->gedr0;
870	878	case PXA255_GEDR1:
871		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 1: %08x & %08x\n", gpio_regs->gedr1, mem_mask );
	879	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 1: %08x & %08x\n", gpio_regs->gedr1, mem_mask );
872	880	return gpio_regs->gedr1;
873	881	case PXA255_GEDR2:
874		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 2: %08x & %08x\n", gpio_regs->gedr2, mem_mask );
	882	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Edge Detect Status Register 2: %08x & %08x\n", gpio_regs->gedr2, mem_mask );
875	883	return gpio_regs->gedr2;
876	884	case PXA255_GAFR0_L:
877		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 0 Lower: %08x & %08x\n", gpio_regs->gafr0l, mem_mask );
	885	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 0 Lower: %08x & %08x\n", gpio_regs->gafr0l, mem_mask );
878	886	return gpio_regs->gafr0l;
879	887	case PXA255_GAFR0_U:
880		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 0 Upper: %08x & %08x\n", gpio_regs->gafr0u, mem_mask );
	888	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 0 Upper: %08x & %08x\n", gpio_regs->gafr0u, mem_mask );
881	889	return gpio_regs->gafr0u;
882	890	case PXA255_GAFR1_L:
883		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 1 Lower: %08x & %08x\n", gpio_regs->gafr1l, mem_mask );
	891	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 1 Lower: %08x & %08x\n", gpio_regs->gafr1l, mem_mask );
884	892	return gpio_regs->gafr1l;
885	893	case PXA255_GAFR1_U:
886		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 1 Upper: %08x & %08x\n", gpio_regs->gafr1u, mem_mask );
	894	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 1 Upper: %08x & %08x\n", gpio_regs->gafr1u, mem_mask );
887	895	return gpio_regs->gafr1u;
888	896	case PXA255_GAFR2_L:
889		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 2 Lower: %08x & %08x\n", gpio_regs->gafr2l, mem_mask );
	897	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 2 Lower: %08x & %08x\n", gpio_regs->gafr2l, mem_mask );
890	898	return gpio_regs->gafr2l;
891	899	case PXA255_GAFR2_U:
892		verboselog( space->machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 2 Upper: %08x & %08x\n", gpio_regs->gafr2u, mem_mask );
	900	verboselog( machine(), 3, "pxa255_gpio_r: GPIO Alternate Function Register 2 Upper: %08x & %08x\n", gpio_regs->gafr2u, mem_mask );
893	901	return gpio_regs->gafr2u;
894	902	default:
895		verboselog( space->machine(), 0, "pxa255_gpio_r: Unknown address: %08x\n", PXA255_GPIO_BASE_ADDR | (offset << 2));
	903	verboselog( machine(), 0, "pxa255_gpio_r: Unknown address: %08x\n", PXA255_GPIO_BASE_ADDR | (offset << 2));
896	904	break;
897	905	}
898	906	return 0;
899	907	}
900	908
901		static WRITE32_HANDLER( pxa255_gpio_w )
	909	WRITE32_MEMBER(_39in1_state::pxa255_gpio_w)
902	910	{
903		_39in1_state *state = space->machine().driver_data<_39in1_state>();
904		PXA255_GPIO_Regs *gpio_regs = &state->m_gpio_regs;
	911	PXA255_GPIO_Regs *gpio_regs = &m_gpio_regs;
905	912
906	913	switch(PXA255_GPIO_BASE_ADDR | (offset << 2))
907	914	{
908	915	case PXA255_GPLR0:
909		verboselog( space->machine(), 3, "pxa255_gpio_w: (Invalid Write) GPIO Pin-Level Register 0: %08x & %08x\n", data, mem_mask );
	916	verboselog( machine(), 3, "pxa255_gpio_w: (Invalid Write) GPIO Pin-Level Register 0: %08x & %08x\n", data, mem_mask );
910	917	break;
911	918	case PXA255_GPLR1:
912		verboselog( space->machine(), 3, "pxa255_gpio_w: (Invalid Write) GPIO Pin-Level Register 1: %08x & %08x\n", data, mem_mask );
	919	verboselog( machine(), 3, "pxa255_gpio_w: (Invalid Write) GPIO Pin-Level Register 1: %08x & %08x\n", data, mem_mask );
913	920	break;
914	921	case PXA255_GPLR2:
915		verboselog( space->machine(), 3, "pxa255_gpio_w: (Invalid Write) GPIO Pin-Level Register 2: %08x & %08x\n", data, mem_mask );
	922	verboselog( machine(), 3, "pxa255_gpio_w: (Invalid Write) GPIO Pin-Level Register 2: %08x & %08x\n", data, mem_mask );
916	923	break;
917	924	case PXA255_GPDR0:
918		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Pin Direction Register 0: %08x & %08x\n", data, mem_mask );
	925	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Pin Direction Register 0: %08x & %08x\n", data, mem_mask );
919	926	gpio_regs->gpdr0 = data;
920	927	break;
921	928	case PXA255_GPDR1:
922		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Pin Direction Register 1: %08x & %08x\n", data, mem_mask );
	929	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Pin Direction Register 1: %08x & %08x\n", data, mem_mask );
923	930	gpio_regs->gpdr1 = data;
924	931	break;
925	932	case PXA255_GPDR2:
926		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Pin Direction Register 2: %08x & %08x\n", data, mem_mask );
	933	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Pin Direction Register 2: %08x & %08x\n", data, mem_mask );
927	934	gpio_regs->gpdr2 = data;
928	935	break;
929	936	case PXA255_GPSR0:
930		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Pin Output Set Register 0: %08x & %08x\n", data, mem_mask );
	937	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Pin Output Set Register 0: %08x & %08x\n", data, mem_mask );
931	938	gpio_regs->gpsr0 |= data & gpio_regs->gpdr0;
932	939	if(data & 0x00000004)
933	940	{
934		state->m_eeprom->set_cs_line(CLEAR_LINE);
	941	m_eeprom->set_cs_line(CLEAR_LINE);
935	942	}
936	943	if(data & 0x00000008)
937	944	{
938		state->m_eeprom->set_clock_line(ASSERT_LINE);
	945	m_eeprom->set_clock_line(ASSERT_LINE);
939	946	}
940	947	if(data & 0x00000010)
941	948	{
942		state->m_eeprom->write_bit(1);
	949	m_eeprom->write_bit(1);
943	950	}
944	951	break;
945	952	case PXA255_GPSR1:
946		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Pin Output Set Register 1: %08x & %08x\n", data, mem_mask );
	953	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Pin Output Set Register 1: %08x & %08x\n", data, mem_mask );
947	954	gpio_regs->gpsr1 |= data & gpio_regs->gpdr1;
948	955	break;
949	956	case PXA255_GPSR2:
950		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Pin Output Set Register 2: %08x & %08x\n", data, mem_mask );
	957	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Pin Output Set Register 2: %08x & %08x\n", data, mem_mask );
951	958	gpio_regs->gpsr2 |= data & gpio_regs->gpdr2;
952	959	break;
953	960	case PXA255_GPCR0:
954		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Pin Output Clear Register 0: %08x & %08x\n", data, mem_mask );
	961	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Pin Output Clear Register 0: %08x & %08x\n", data, mem_mask );
955	962	gpio_regs->gpsr0 &= ~(data & gpio_regs->gpdr0);
956	963	if(data & 0x00000004)
957	964	{
958		state->m_eeprom->set_cs_line(ASSERT_LINE);
	965	m_eeprom->set_cs_line(ASSERT_LINE);
959	966	}
960	967	if(data & 0x00000008)
961	968	{
962		state->m_eeprom->set_clock_line(CLEAR_LINE);
	969	m_eeprom->set_clock_line(CLEAR_LINE);
963	970	}
964	971	if(data & 0x00000010)
965	972	{
966		state->m_eeprom->write_bit(0);
	973	m_eeprom->write_bit(0);
967	974	}
968	975	break;
969	976	case PXA255_GPCR1:
970		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Pin Output Clear Register 1: %08x & %08x\n", data, mem_mask );
	977	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Pin Output Clear Register 1: %08x & %08x\n", data, mem_mask );
971	978	gpio_regs->gpsr1 &= ~(data & gpio_regs->gpdr1);
972	979	break;
973	980	case PXA255_GPCR2:
974		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Pin Output Clear Register 2: %08x & %08x\n", data, mem_mask );
	981	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Pin Output Clear Register 2: %08x & %08x\n", data, mem_mask );
975	982	gpio_regs->gpsr2 &= ~(data & gpio_regs->gpdr2);
976	983	break;
977	984	case PXA255_GRER0:
978		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Rising Edge Detect Enable Register 0: %08x & %08x\n", data, mem_mask );
	985	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Rising Edge Detect Enable Register 0: %08x & %08x\n", data, mem_mask );
979	986	gpio_regs->grer0 = data;
980	987	break;
981	988	case PXA255_GRER1:
982		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Rising Edge Detect Enable Register 1: %08x & %08x\n", data, mem_mask );
	989	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Rising Edge Detect Enable Register 1: %08x & %08x\n", data, mem_mask );
983	990	gpio_regs->grer1 = data;
984	991	break;
985	992	case PXA255_GRER2:
986		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Rising Edge Detect Enable Register 2: %08x & %08x\n", data, mem_mask );
	993	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Rising Edge Detect Enable Register 2: %08x & %08x\n", data, mem_mask );
987	994	gpio_regs->grer2 = data;
988	995	break;
989	996	case PXA255_GFER0:
990		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Falling Edge Detect Enable Register 0: %08x & %08x\n", data, mem_mask );
	997	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Falling Edge Detect Enable Register 0: %08x & %08x\n", data, mem_mask );
991	998	gpio_regs->gfer0 = data;
992	999	break;
993	1000	case PXA255_GFER1:
994		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Falling Edge Detect Enable Register 1: %08x & %08x\n", data, mem_mask );
	1001	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Falling Edge Detect Enable Register 1: %08x & %08x\n", data, mem_mask );
995	1002	gpio_regs->gfer1 = data;
996	1003	break;
997	1004	case PXA255_GFER2:
998		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Falling Edge Detect Enable Register 2: %08x & %08x\n", data, mem_mask );
	1005	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Falling Edge Detect Enable Register 2: %08x & %08x\n", data, mem_mask );
999	1006	gpio_regs->gfer2 = data;
1000	1007	break;
1001	1008	case PXA255_GEDR0:
1002		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 0: %08x & %08x\n", gpio_regs->gedr0, mem_mask );
	1009	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 0: %08x & %08x\n", gpio_regs->gedr0, mem_mask );
1003	1010	gpio_regs->gedr0 &= ~data;
1004	1011	break;
1005	1012	case PXA255_GEDR1:
1006		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 1: %08x & %08x\n", gpio_regs->gedr1, mem_mask );
	1013	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 1: %08x & %08x\n", gpio_regs->gedr1, mem_mask );
1007	1014	gpio_regs->gedr1 &= ~data;
1008	1015	break;
1009	1016	case PXA255_GEDR2:
1010		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 2: %08x & %08x\n", gpio_regs->gedr2, mem_mask );
	1017	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Edge Detect Status Register 2: %08x & %08x\n", gpio_regs->gedr2, mem_mask );
1011	1018	gpio_regs->gedr2 &= ~data;
1012	1019	break;
1013	1020	case PXA255_GAFR0_L:
1014		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 0 Lower: %08x & %08x\n", gpio_regs->gafr0l, mem_mask );
	1021	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 0 Lower: %08x & %08x\n", gpio_regs->gafr0l, mem_mask );
1015	1022	gpio_regs->gafr0l = data;
1016	1023	break;
1017	1024	case PXA255_GAFR0_U:
1018		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 0 Upper: %08x & %08x\n", gpio_regs->gafr0u, mem_mask );
	1025	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 0 Upper: %08x & %08x\n", gpio_regs->gafr0u, mem_mask );
1019	1026	gpio_regs->gafr0u = data;
1020	1027	break;
1021	1028	case PXA255_GAFR1_L:
1022		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 1 Lower: %08x & %08x\n", gpio_regs->gafr1l, mem_mask );
	1029	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 1 Lower: %08x & %08x\n", gpio_regs->gafr1l, mem_mask );
1023	1030	gpio_regs->gafr1l = data;
1024	1031	break;
1025	1032	case PXA255_GAFR1_U:
1026		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 1 Upper: %08x & %08x\n", gpio_regs->gafr1u, mem_mask );
	1033	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 1 Upper: %08x & %08x\n", gpio_regs->gafr1u, mem_mask );
1027	1034	gpio_regs->gafr1u = data;
1028	1035	break;
1029	1036	case PXA255_GAFR2_L:
1030		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 2 Lower: %08x & %08x\n", gpio_regs->gafr2l, mem_mask );
	1037	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 2 Lower: %08x & %08x\n", gpio_regs->gafr2l, mem_mask );
1031	1038	gpio_regs->gafr2l = data;
1032	1039	break;
1033	1040	case PXA255_GAFR2_U:
1034		verboselog( space->machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 2 Upper: %08x & %08x\n", gpio_regs->gafr2u, mem_mask );
	1041	verboselog( machine(), 3, "pxa255_gpio_w: GPIO Alternate Function Register 2 Upper: %08x & %08x\n", gpio_regs->gafr2u, mem_mask );
1035	1042	gpio_regs->gafr2u = data;
1036	1043	break;
1037	1044	default:
1038		verboselog( space->machine(), 0, "pxa255_gpio_w: Unknown address: %08x = %08x & %08x\n", PXA255_GPIO_BASE_ADDR | (offset << 2), data, mem_mask);
	1045	verboselog( machine(), 0, "pxa255_gpio_w: Unknown address: %08x = %08x & %08x\n", PXA255_GPIO_BASE_ADDR | (offset << 2), data, mem_mask);
1039	1046	break;
1040	1047	}
1041	1048	}
r14845	r14846
1169	1176	pxa255_lcd_irq_check(machine);
1170	1177	}
1171	1178
1172		static READ32_HANDLER( pxa255_lcd_r )
	1179	READ32_MEMBER(_39in1_state::pxa255_lcd_r)
1173	1180	{
1174		_39in1_state *state = space->machine().driver_data<_39in1_state>();
1175		PXA255_LCD_Regs *lcd_regs = &state->m_lcd_regs;
	1181	PXA255_LCD_Regs *lcd_regs = &m_lcd_regs;
1176	1182
1177	1183	switch(PXA255_LCD_BASE_ADDR | (offset << 2))
1178	1184	{
1179	1185	case PXA255_LCCR0:      // 0x44000000
1180		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD Control 0: %08x & %08x\n", lcd_regs->lccr0, mem_mask );
	1186	verboselog( machine(), 3, "pxa255_lcd_r: LCD Control 0: %08x & %08x\n", lcd_regs->lccr0, mem_mask );
1181	1187	return lcd_regs->lccr0;
1182	1188	case PXA255_LCCR1:      // 0x44000004
1183		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD Control 1: %08x & %08x\n", lcd_regs->lccr1, mem_mask );
	1189	verboselog( machine(), 3, "pxa255_lcd_r: LCD Control 1: %08x & %08x\n", lcd_regs->lccr1, mem_mask );
1184	1190	return lcd_regs->lccr1;
1185	1191	case PXA255_LCCR2:      // 0x44000008
1186		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD Control 2: %08x & %08x\n", lcd_regs->lccr2, mem_mask );
	1192	verboselog( machine(), 3, "pxa255_lcd_r: LCD Control 2: %08x & %08x\n", lcd_regs->lccr2, mem_mask );
1187	1193	return lcd_regs->lccr2;
1188	1194	case PXA255_LCCR3:      // 0x4400000c
1189		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD Control 3: %08x & %08x\n", lcd_regs->lccr3, mem_mask );
	1195	verboselog( machine(), 3, "pxa255_lcd_r: LCD Control 3: %08x & %08x\n", lcd_regs->lccr3, mem_mask );
1190	1196	return lcd_regs->lccr3;
1191	1197	case PXA255_FBR0:      // 0x44000020
1192		verboselog( space->machine(), 4, "pxa255_lcd_r: LCD Frame Branch Register 0: %08x & %08x\n", lcd_regs->fbr[0], mem_mask );
	1198	verboselog( machine(), 4, "pxa255_lcd_r: LCD Frame Branch Register 0: %08x & %08x\n", lcd_regs->fbr[0], mem_mask );
1193	1199	return lcd_regs->fbr[0];
1194	1200	case PXA255_FBR1:      // 0x44000024
1195		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD Frame Branch Register 1: %08x & %08x\n", lcd_regs->fbr[1], mem_mask );
	1201	verboselog( machine(), 3, "pxa255_lcd_r: LCD Frame Branch Register 1: %08x & %08x\n", lcd_regs->fbr[1], mem_mask );
1196	1202	return lcd_regs->fbr[1];
1197	1203	case PXA255_LCSR:      // 0x44000038
1198		verboselog( space->machine(), 4, "pxa255_lcd_r: LCD Status Register: %08x & %08x\n", lcd_regs->lcsr, mem_mask );
	1204	verboselog( machine(), 4, "pxa255_lcd_r: LCD Status Register: %08x & %08x\n", lcd_regs->lcsr, mem_mask );
1199	1205	return lcd_regs->lcsr;
1200	1206	case PXA255_LIIDR:      // 0x4400003c
1201		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD Interrupt ID Register: %08x & %08x\n", lcd_regs->liidr, mem_mask );
	1207	verboselog( machine(), 3, "pxa255_lcd_r: LCD Interrupt ID Register: %08x & %08x\n", lcd_regs->liidr, mem_mask );
1202	1208	return lcd_regs->liidr;
1203	1209	case PXA255_TRGBR:      // 0x44000040
1204		verboselog( space->machine(), 3, "pxa255_lcd_r: TMED RGB Seed Register: %08x & %08x\n", lcd_regs->trgbr, mem_mask );
	1210	verboselog( machine(), 3, "pxa255_lcd_r: TMED RGB Seed Register: %08x & %08x\n", lcd_regs->trgbr, mem_mask );
1205	1211	return lcd_regs->trgbr;
1206	1212	case PXA255_TCR:      // 0x44000044
1207		verboselog( space->machine(), 3, "pxa255_lcd_r: TMED RGB Seed Register: %08x & %08x\n", lcd_regs->tcr, mem_mask );
	1213	verboselog( machine(), 3, "pxa255_lcd_r: TMED RGB Seed Register: %08x & %08x\n", lcd_regs->tcr, mem_mask );
1208	1214	return lcd_regs->tcr;
1209	1215	case PXA255_FDADR0:      // 0x44000200
1210		if (0) verboselog( space->machine(), 3, "pxa255_lcd_r: LCD DMA Frame Descriptor Address Register 0: %08x & %08x\n", lcd_regs->dma[0].fdadr, mem_mask );
	1216	if (0) verboselog( machine(), 3, "pxa255_lcd_r: LCD DMA Frame Descriptor Address Register 0: %08x & %08x\n", lcd_regs->dma[0].fdadr, mem_mask );
1211	1217	return lcd_regs->dma[0].fdadr;
1212	1218	case PXA255_FSADR0:      // 0x44000204
1213		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD DMA Frame Source Address Register 0: %08x & %08x\n", lcd_regs->dma[0].fsadr, mem_mask );
	1219	verboselog( machine(), 3, "pxa255_lcd_r: LCD DMA Frame Source Address Register 0: %08x & %08x\n", lcd_regs->dma[0].fsadr, mem_mask );
1214	1220	return lcd_regs->dma[0].fsadr;
1215	1221	case PXA255_FIDR0:      // 0x44000208
1216		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD DMA Frame ID Register 0: %08x & %08x\n", lcd_regs->dma[0].fidr, mem_mask );
	1222	verboselog( machine(), 3, "pxa255_lcd_r: LCD DMA Frame ID Register 0: %08x & %08x\n", lcd_regs->dma[0].fidr, mem_mask );
1217	1223	return lcd_regs->dma[0].fidr;
1218	1224	case PXA255_LDCMD0:      // 0x4400020c
1219		if (0) verboselog( space->machine(), 3, "pxa255_lcd_r: LCD DMA Command Register 0: %08x & %08x\n", lcd_regs->dma[0].ldcmd & 0xfff00000, mem_mask );
	1225	if (0) verboselog( machine(), 3, "pxa255_lcd_r: LCD DMA Command Register 0: %08x & %08x\n", lcd_regs->dma[0].ldcmd & 0xfff00000, mem_mask );
1220	1226	return lcd_regs->dma[0].ldcmd & 0xfff00000;
1221	1227	case PXA255_FDADR1:      // 0x44000210
1222		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD DMA Frame Descriptor Address Register 1: %08x & %08x\n", lcd_regs->dma[1].fdadr, mem_mask );
	1228	verboselog( machine(), 3, "pxa255_lcd_r: LCD DMA Frame Descriptor Address Register 1: %08x & %08x\n", lcd_regs->dma[1].fdadr, mem_mask );
1223	1229	return lcd_regs->dma[1].fdadr;
1224	1230	case PXA255_FSADR1:      // 0x44000214
1225		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD DMA Frame Source Address Register 1: %08x & %08x\n", lcd_regs->dma[1].fsadr, mem_mask );
	1231	verboselog( machine(), 3, "pxa255_lcd_r: LCD DMA Frame Source Address Register 1: %08x & %08x\n", lcd_regs->dma[1].fsadr, mem_mask );
1226	1232	return lcd_regs->dma[1].fsadr;
1227	1233	case PXA255_FIDR1:      // 0x44000218
1228		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD DMA Frame ID Register 1: %08x & %08x\n", lcd_regs->dma[1].fidr, mem_mask );
	1234	verboselog( machine(), 3, "pxa255_lcd_r: LCD DMA Frame ID Register 1: %08x & %08x\n", lcd_regs->dma[1].fidr, mem_mask );
1229	1235	return lcd_regs->dma[1].fidr;
1230	1236	case PXA255_LDCMD1:      // 0x4400021c
1231		verboselog( space->machine(), 3, "pxa255_lcd_r: LCD DMA Command Register 1: %08x & %08x\n", lcd_regs->dma[1].ldcmd & 0xfff00000, mem_mask );
	1237	verboselog( machine(), 3, "pxa255_lcd_r: LCD DMA Command Register 1: %08x & %08x\n", lcd_regs->dma[1].ldcmd & 0xfff00000, mem_mask );
1232	1238	return lcd_regs->dma[1].ldcmd & 0xfff00000;
1233	1239	default:
1234		verboselog( space->machine(), 0, "pxa255_lcd_r: Unknown address: %08x\n", PXA255_LCD_BASE_ADDR | (offset << 2));
	1240	verboselog( machine(), 0, "pxa255_lcd_r: Unknown address: %08x\n", PXA255_LCD_BASE_ADDR | (offset << 2));
1235	1241	break;
1236	1242	}
1237	1243	return 0;
1238	1244	}
1239	1245
1240		static WRITE32_HANDLER( pxa255_lcd_w )
	1246	WRITE32_MEMBER(_39in1_state::pxa255_lcd_w)
1241	1247	{
1242		_39in1_state *state = space->machine().driver_data<_39in1_state>();
1243		PXA255_LCD_Regs *lcd_regs = &state->m_lcd_regs;
	1248	PXA255_LCD_Regs *lcd_regs = &m_lcd_regs;
1244	1249
1245	1250	switch(PXA255_LCD_BASE_ADDR | (offset << 2))
1246	1251	{
1247	1252	case PXA255_LCCR0:      // 0x44000000
1248		verboselog( space->machine(), 3, "pxa255_lcd_w: LCD Control 0: %08x & %08x\n", data, mem_mask );
	1253	verboselog( machine(), 3, "pxa255_lcd_w: LCD Control 0: %08x & %08x\n", data, mem_mask );
1249	1254	lcd_regs->lccr0 = data & 0x00fffeff;
1250	1255	break;
1251	1256	case PXA255_LCCR1:      // 0x44000004
1252		verboselog( space->machine(), 3, "pxa255_lcd_w: LCD Control 1: %08x & %08x\n", data, mem_mask );
	1257	verboselog( machine(), 3, "pxa255_lcd_w: LCD Control 1: %08x & %08x\n", data, mem_mask );
1253	1258	lcd_regs->lccr1 = data;
1254	1259	break;
1255	1260	case PXA255_LCCR2:      // 0x44000008
1256		verboselog( space->machine(), 3, "pxa255_lcd_w: LCD Control 2: %08x & %08x\n", data, mem_mask );
	1261	verboselog( machine(), 3, "pxa255_lcd_w: LCD Control 2: %08x & %08x\n", data, mem_mask );
1257	1262	lcd_regs->lccr2 = data;
1258	1263	break;
1259	1264	case PXA255_LCCR3:      // 0x4400000c
1260		verboselog( space->machine(), 3, "pxa255_lcd_w: LCD Control 3: %08x & %08x\n", data, mem_mask );
	1265	verboselog( machine(), 3, "pxa255_lcd_w: LCD Control 3: %08x & %08x\n", data, mem_mask );
1261	1266	lcd_regs->lccr3 = data;
1262	1267	break;
1263	1268	case PXA255_FBR0:      // 0x44000020
1264		verboselog( space->machine(), 4l, "pxa255_lcd_w: LCD Frame Branch Register 0: %08x & %08x\n", data, mem_mask );
	1269	verboselog( machine(), 4l, "pxa255_lcd_w: LCD Frame Branch Register 0: %08x & %08x\n", data, mem_mask );
1265	1270	lcd_regs->fbr[0] = data & 0xfffffff3;
1266	1271	if(!lcd_regs->dma[0].eof->enabled())
1267	1272	{
1268		if (0) verboselog( space->machine(), 3, "ch0 EOF timer is not enabled, taking branch now\n" );
1269		pxa255_lcd_check_load_next_branch(space->machine(), 0);
1270		pxa255_lcd_irq_check(space->machine());
	1273	if (0) verboselog( machine(), 3, "ch0 EOF timer is not enabled, taking branch now\n" );
	1274	pxa255_lcd_check_load_next_branch(machine(), 0);
	1275	pxa255_lcd_irq_check(machine());
1271	1276	}
1272	1277	break;
1273	1278	case PXA255_FBR1:      // 0x44000024
1274		verboselog( space->machine(), 3, "pxa255_lcd_w: LCD Frame Branch Register 1: %08x & %08x\n", data, mem_mask );
	1279	verboselog( machine(), 3, "pxa255_lcd_w: LCD Frame Branch Register 1: %08x & %08x\n", data, mem_mask );
1275	1280	lcd_regs->fbr[1] = data & 0xfffffff3;
1276	1281	if(!lcd_regs->dma[1].eof->enabled())
1277	1282	{
1278		verboselog( space->machine(), 3, "ch1 EOF timer is not enabled, taking branch now\n" );
1279		pxa255_lcd_check_load_next_branch(space->machine(), 1);
1280		pxa255_lcd_irq_check(space->machine());
	1283	verboselog( machine(), 3, "ch1 EOF timer is not enabled, taking branch now\n" );
	1284	pxa255_lcd_check_load_next_branch(machine(), 1);
	1285	pxa255_lcd_irq_check(machine());
1281	1286	}
1282	1287	break;
1283	1288	case PXA255_LCSR:      // 0x44000038
1284		verboselog( space->machine(), 4, "pxa255_lcd_w: LCD Controller Status Register: %08x & %08x\n", data, mem_mask );
	1289	verboselog( machine(), 4, "pxa255_lcd_w: LCD Controller Status Register: %08x & %08x\n", data, mem_mask );
1285	1290	lcd_regs->lcsr &= ~data;
1286		pxa255_lcd_irq_check(space->machine());
	1291	pxa255_lcd_irq_check(machine());
1287	1292	break;
1288	1293	case PXA255_LIIDR:      // 0x4400003c
1289		verboselog( space->machine(), 3, "pxa255_lcd_w: LCD Controller Interrupt ID Register: %08x & %08x\n", data, mem_mask );
	1294	verboselog( machine(), 3, "pxa255_lcd_w: LCD Controller Interrupt ID Register: %08x & %08x\n", data, mem_mask );
1290	1295	break;
1291	1296	case PXA255_TRGBR:      // 0x44000040
1292		verboselog( space->machine(), 3, "pxa255_lcd_w: TMED RGB Seed Register: %08x & %08x\n", data, mem_mask );
	1297	verboselog( machine(), 3, "pxa255_lcd_w: TMED RGB Seed Register: %08x & %08x\n", data, mem_mask );
1293	1298	lcd_regs->trgbr = data & 0x00ffffff;
1294	1299	break;
1295	1300	case PXA255_TCR:      // 0x44000044
1296		verboselog( space->machine(), 3, "pxa255_lcd_w: TMED Control Register: %08x & %08x\n", data, mem_mask );
	1301	verboselog( machine(), 3, "pxa255_lcd_w: TMED Control Register: %08x & %08x\n", data, mem_mask );
1297	1302	lcd_regs->tcr = data & 0x00004fff;
1298	1303	break;
1299	1304	case PXA255_FDADR0:      // 0x44000200
1300		verboselog( space->machine(), 4, "pxa255_lcd_w: LCD DMA Frame Descriptor Address Register 0: %08x & %08x\n", data, mem_mask );
	1305	verboselog( machine(), 4, "pxa255_lcd_w: LCD DMA Frame Descriptor Address Register 0: %08x & %08x\n", data, mem_mask );
1301	1306	if(!lcd_regs->dma[0].eof->enabled())
1302	1307	{
1303		pxa255_lcd_load_dma_descriptor(space, data & 0xfffffff0, 0);
	1308	pxa255_lcd_load_dma_descriptor(&space, data & 0xfffffff0, 0);
1304	1309	}
1305	1310	else
1306	1311	{
r14845	r14846
1309	1314	}
1310	1315	break;
1311	1316	case PXA255_FSADR0:      // 0x44000204
1312		verboselog( space->machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Frame Source Address Register 0: %08x & %08x\n", data, mem_mask );
	1317	verboselog( machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Frame Source Address Register 0: %08x & %08x\n", data, mem_mask );
1313	1318	break;
1314	1319	case PXA255_FIDR0:      // 0x44000208
1315		verboselog( space->machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Frame ID Register 0: %08x & %08x\n", data, mem_mask );
	1320	verboselog( machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Frame ID Register 0: %08x & %08x\n", data, mem_mask );
1316	1321	break;
1317	1322	case PXA255_LDCMD0:      // 0x4400020c
1318		verboselog( space->machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Command Register 0: %08x & %08x\n", data, mem_mask );
	1323	verboselog( machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Command Register 0: %08x & %08x\n", data, mem_mask );
1319	1324	break;
1320	1325	case PXA255_FDADR1:      // 0x44000210
1321		verboselog( space->machine(), 4, "pxa255_lcd_w: LCD DMA Frame Descriptor Address Register 1: %08x & %08x\n", data, mem_mask );
	1326	verboselog( machine(), 4, "pxa255_lcd_w: LCD DMA Frame Descriptor Address Register 1: %08x & %08x\n", data, mem_mask );
1322	1327	if(!lcd_regs->dma[1].eof->enabled())
1323	1328	{
1324		pxa255_lcd_load_dma_descriptor(space, data & 0xfffffff0, 1);
	1329	pxa255_lcd_load_dma_descriptor(&space, data & 0xfffffff0, 1);
1325	1330	}
1326	1331	else
1327	1332	{
r14845	r14846
1330	1335	}
1331	1336	break;
1332	1337	case PXA255_FSADR1:      // 0x44000214
1333		verboselog( space->machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Frame Source Address Register 1: %08x & %08x\n", data, mem_mask );
	1338	verboselog( machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Frame Source Address Register 1: %08x & %08x\n", data, mem_mask );
1334	1339	break;
1335	1340	case PXA255_FIDR1:      // 0x44000218
1336		verboselog( space->machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Frame ID Register 1: %08x & %08x\n", data, mem_mask );
	1341	verboselog( machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Frame ID Register 1: %08x & %08x\n", data, mem_mask );
1337	1342	break;
1338	1343	case PXA255_LDCMD1:      // 0x4400021c
1339		verboselog( space->machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Command Register 1: %08x & %08x\n", data, mem_mask );
	1344	verboselog( machine(), 4, "pxa255_lcd_w: (Invalid Write) LCD DMA Command Register 1: %08x & %08x\n", data, mem_mask );
1340	1345	break;
1341	1346	default:
1342		verboselog( space->machine(), 0, "pxa255_lcd_w: Unknown address: %08x = %08x & %08x\n", PXA255_LCD_BASE_ADDR | (offset << 2), data, mem_mask);
	1347	verboselog( machine(), 0, "pxa255_lcd_w: Unknown address: %08x = %08x & %08x\n", PXA255_LCD_BASE_ADDR | (offset << 2), data, mem_mask);
1343	1348	break;
1344	1349	}
1345	1350	}
r14845	r14846
1349	1354	}
1350	1355
1351	1356	#ifdef UNUSED_FUNCTION
1352		static READ32_HANDLER( return_zero )
	1357	READ32_MEMBER(_39in1_state::return_zero)
1353	1358	{
1354	1359	return 0;
1355	1360	}
1356	1361
1357		static READ32_HANDLER( unknown_r )
	1362	READ32_MEMBER(_39in1_state::unknown_r)
1358	1363	{
1359	1364	return 0x00008000;
1360	1365	}
1361	1366	#endif
1362	1367
1363		static READ32_HANDLER( cpld_r )
	1368	READ32_MEMBER(_39in1_state::cpld_r)
1364	1369	{
1365		_39in1_state *state = space->machine().driver_data<_39in1_state>();
1366	1370
1367		//if (cpu_get_pc(&space->device()) != 0xe3af4) printf("CPLD read @ %x (PC %x state %d)\n", offset, cpu_get_pc(&space->device()), state);
	1371	//if (cpu_get_pc(&space.device()) != 0xe3af4) printf("CPLD read @ %x (PC %x state %d)\n", offset, cpu_get_pc(&space.device()), state);
1368	1372
1369		if (cpu_get_pc(&space->device()) == 0x3f04)
	1373	if (cpu_get_pc(&space.device()) == 0x3f04)
1370	1374	{
1371	1375	return 0xf0;     // any non-zero value works here
1372	1376	}
1373		else if (cpu_get_pc(&space->device()) == 0xe3af4)
	1377	else if (cpu_get_pc(&space.device()) == 0xe3af4)
1374	1378	{
1375		return input_port_read(space->machine(), "MCUIPT");
	1379	return input_port_read(machine(), "MCUIPT");
1376	1380	}
1377	1381	else
1378	1382	{
1379		if (state->m_state == 0)
	1383	if (m_state == 0)
1380	1384	{
1381	1385	return 0;
1382	1386	}
1383		else if (state->m_state == 1)
	1387	else if (m_state == 1)
1384	1388	{
1385	1389	switch (offset & ~1)
1386	1390	{
r14845	r14846
1395	1399	default: printf("State 1 unknown offset %x\n", offset); break;
1396	1400	}
1397	1401	}
1398		else if (state->m_state == 2)                  // 29c0: 53 ac 0c 2b a2 07 e6 be 31
	1402	else if (m_state == 2)                  // 29c0: 53 ac 0c 2b a2 07 e6 be 31
1399	1403	{
1400		UINT32 seed = state->m_seed;
1401		UINT32 magic = state->m_magic;
	1404	UINT32 seed = m_seed;
	1405	UINT32 magic = m_magic;
1402	1406
1403	1407	magic = ( (((~(seed >> 16))       ^ (magic >> 1))        & 0x01) |
1404	1408	(((~((seed >> 19) << 1))        ^ ((magic >> 5) << 1)) & 0x02) |
r14845	r14846
1409	1413	(((~(((seed >> 16) >> 1) << 6)) ^ ((magic >> 7) << 6)) & 0x40) |
1410	1414	(((~(((seed >> 16) >> 5) << 7)) ^  (magic << 7))       & 0x80));
1411	1415
1412		state->m_magic = magic;
	1416	m_magic = magic;
1413	1417	return magic;
1414	1418	}
1415	1419	}
r14845	r14846
1417	1421	return 0;
1418	1422	}
1419	1423
1420		static WRITE32_HANDLER( cpld_w )
	1424	WRITE32_MEMBER(_39in1_state::cpld_w)
1421	1425	{
1422		_39in1_state *state = space->machine().driver_data<_39in1_state>();
1423	1426
1424	1427	if (mem_mask == 0xffff)
1425	1428	{
1426		state->m_seed = data<<16;
	1429	m_seed = data<<16;
1427	1430	}
1428	1431
1429		if (cpu_get_pc(&space->device()) == 0x280c)
	1432	if (cpu_get_pc(&space.device()) == 0x280c)
1430	1433	{
1431		state->m_state = 1;
	1434	m_state = 1;
1432	1435	}
1433		if (cpu_get_pc(&space->device()) == 0x2874)
	1436	if (cpu_get_pc(&space.device()) == 0x2874)
1434	1437	{
1435		state->m_state = 2;
1436		state->m_magic = space->read_byte(0xa02d4ff0);
	1438	m_state = 2;
	1439	m_magic = space.read_byte(0xa02d4ff0);
1437	1440	}
1438	1441	else if (offset == 0xa)
1439	1442	{
r14845	r14846
1441	1444	#if 0
1442	1445	else
1443	1446	{
1444		printf("%08x: CPLD_W: %08x = %08x & %08x\n", cpu_get_pc(&space->device()), offset, data, mem_mask);
	1447	printf("%08x: CPLD_W: %08x = %08x & %08x\n", cpu_get_pc(&space.device()), offset, data, mem_mask);
1445	1448	}
1446	1449	#endif
1447	1450	}
1448	1451
1449		static READ32_HANDLER( prot_cheater_r )
	1452	READ32_MEMBER(_39in1_state::prot_cheater_r)
1450	1453	{
1451	1454	return 0x37;
1452	1455	}
r14845	r14846
1460	1463	state->m_eeprom = machine.device<eeprom_device>("eeprom");
1461	1464
1462	1465	address_space *space = machine.device<pxa255_device>("maincpu")->space(AS_PROGRAM);
1463		space->install_legacy_read_handler (0xa0151648, 0xa015164b, FUNC(prot_cheater_r));
	1466	space->install_read_handler (0xa0151648, 0xa015164b, read32_delegate(FUNC(_39in1_state::prot_cheater_r), state));
1464	1467	}
1465	1468
1466	1469	static ADDRESS_MAP_START( 39in1_map, AS_PROGRAM, 32, _39in1_state )
1467	1470	AM_RANGE(0x00000000, 0x0007ffff) AM_ROM
1468	1471	AM_RANGE(0x00400000, 0x005fffff) AM_ROM AM_REGION("data", 0)
1469		AM_RANGE(0x04000000, 0x047fffff) AM_READWRITE_LEGACY(cpld_r, cpld_w )
1470		AM_RANGE(0x40000000, 0x400002ff) AM_READWRITE_LEGACY(pxa255_dma_r, pxa255_dma_w )
1471		AM_RANGE(0x40400000, 0x40400083) AM_READWRITE_LEGACY(pxa255_i2s_r, pxa255_i2s_w )
1472		AM_RANGE(0x40a00000, 0x40a0001f) AM_READWRITE_LEGACY(pxa255_ostimer_r, pxa255_ostimer_w )
1473		AM_RANGE(0x40d00000, 0x40d00017) AM_READWRITE_LEGACY(pxa255_intc_r, pxa255_intc_w )
1474		AM_RANGE(0x40e00000, 0x40e0006b) AM_READWRITE_LEGACY(pxa255_gpio_r, pxa255_gpio_w )
1475		AM_RANGE(0x44000000, 0x4400021f) AM_READWRITE_LEGACY(pxa255_lcd_r,  pxa255_lcd_w )
	1472	AM_RANGE(0x04000000, 0x047fffff) AM_READWRITE(cpld_r, cpld_w )
	1473	AM_RANGE(0x40000000, 0x400002ff) AM_READWRITE(pxa255_dma_r, pxa255_dma_w )
	1474	AM_RANGE(0x40400000, 0x40400083) AM_READWRITE(pxa255_i2s_r, pxa255_i2s_w )
	1475	AM_RANGE(0x40a00000, 0x40a0001f) AM_READWRITE(pxa255_ostimer_r, pxa255_ostimer_w )
	1476	AM_RANGE(0x40d00000, 0x40d00017) AM_READWRITE(pxa255_intc_r, pxa255_intc_w )
	1477	AM_RANGE(0x40e00000, 0x40e0006b) AM_READWRITE(pxa255_gpio_r, pxa255_gpio_w )
	1478	AM_RANGE(0x44000000, 0x4400021f) AM_READWRITE(pxa255_lcd_r,  pxa255_lcd_w )
1476	1479	AM_RANGE(0xa0000000, 0xa07fffff) AM_RAM AM_BASE(m_ram)
1477	1480	ADDRESS_MAP_END
1478	1481

src/mame/drivers/gunpey.c

r14845	r14846
59	59
60	60	UINT16 *m_blit_buffer;
61	61	UINT16 m_blit_ram[0x10];
	62	DECLARE_WRITE8_MEMBER(gunpey_status_w);
	63	DECLARE_READ8_MEMBER(gunpey_status_r);
	64	DECLARE_READ8_MEMBER(gunpey_inputs_r);
	65	DECLARE_WRITE8_MEMBER(gunpey_blitter_w);
62	66	};
63	67
64	68
r14845	r14846
100	104	return 0;
101	105	}
102	106
103		static WRITE8_HANDLER( gunpey_status_w )
	107	WRITE8_MEMBER(gunpey_state::gunpey_status_w)
104	108	{
105	109	}
106	110
107		static READ8_HANDLER( gunpey_status_r )
	111	READ8_MEMBER(gunpey_state::gunpey_status_r)
108	112	{
109	113	if(offset == 1)
110	114	return 0x54;
r14845	r14846
112	116	return 0x00;
113	117	}
114	118
115		static READ8_HANDLER( gunpey_inputs_r )
	119	READ8_MEMBER(gunpey_state::gunpey_inputs_r)
116	120	{
117	121	switch(offset+0x7f40)
118	122	{
119		case 0x7f40: return input_port_read(space->machine(), "DSW1");
120		case 0x7f41: return input_port_read(space->machine(), "DSW2");
121		case 0x7f42: return input_port_read(space->machine(), "P1");
122		case 0x7f43: return input_port_read(space->machine(), "P2");
123		case 0x7f44: return input_port_read(space->machine(), "SYSTEM");
	123	case 0x7f40: return input_port_read(machine(), "DSW1");
	124	case 0x7f41: return input_port_read(machine(), "DSW2");
	125	case 0x7f42: return input_port_read(machine(), "P1");
	126	case 0x7f43: return input_port_read(machine(), "P2");
	127	case 0x7f44: return input_port_read(machine(), "SYSTEM");
124	128	}
125	129
126	130	return 0xff;
127	131	}
128	132
129		static WRITE8_HANDLER( gunpey_blitter_w )
	133	WRITE8_MEMBER(gunpey_state::gunpey_blitter_w)
130	134	{
131		gunpey_state *state = space->machine().driver_data<gunpey_state>();
132		UINT16 *blit_buffer = state->m_blit_buffer;
133		UINT16 *blit_ram = state->m_blit_ram;
134		UINT8 *blit_rom = space->machine().region("blit_data")->base();
	135	UINT16 *blit_buffer = m_blit_buffer;
	136	UINT16 *blit_ram = m_blit_ram;
	137	UINT8 *blit_rom = machine().region("blit_data")->base();
135	138	int x,y;
136	139
137	140	blit_ram[offset] = data;
r14845	r14846
189	192	ADDRESS_MAP_END
190	193
191	194	static ADDRESS_MAP_START( io_map, AS_IO, 16, gunpey_state )
192		AM_RANGE(0x7f40, 0x7f45) AM_READ8_LEGACY(gunpey_inputs_r,0xffff)
	195	AM_RANGE(0x7f40, 0x7f45) AM_READ8(gunpey_inputs_r,0xffff)
193	196
194	197	//  AM_RANGE(0x7f48, 0x7f48) AM_WRITE_LEGACY(output_w)
195	198	AM_RANGE(0x7f80, 0x7f81) AM_DEVREADWRITE8_LEGACY("ymz", ymz280b_r, ymz280b_w, 0xffff)
196	199
197	200	AM_RANGE(0x7f88, 0x7f89) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0xff00)
198	201
199		AM_RANGE(0x7fc8, 0x7fc9) AM_READWRITE8_LEGACY(gunpey_status_r,  gunpey_status_w, 0xffff )
200		AM_RANGE(0x7fd0, 0x7fdf) AM_WRITE8_LEGACY(gunpey_blitter_w, 0xffff )
	202	AM_RANGE(0x7fc8, 0x7fc9) AM_READWRITE8(gunpey_status_r,  gunpey_status_w, 0xffff )
	203	AM_RANGE(0x7fd0, 0x7fdf) AM_WRITE8(gunpey_blitter_w, 0xffff )
201	204	ADDRESS_MAP_END
202	205
203	206

src/mame/drivers/superwng.c

r14845	r14846
50	50	tilemap_t *   m_bg_tilemap;
51	51	tilemap_t *   m_fg_tilemap;
52	52
	53	DECLARE_WRITE8_MEMBER(superwng_nmi_enable_w);
	54	DECLARE_WRITE8_MEMBER(superwng_sound_interrupt_w);
	55	DECLARE_WRITE8_MEMBER(superwng_sound_nmi_clear_w);
	56	DECLARE_WRITE8_MEMBER(superwng_bg_vram_w);
	57	DECLARE_WRITE8_MEMBER(superwng_bg_cram_w);
	58	DECLARE_WRITE8_MEMBER(superwng_fg_vram_w);
	59	DECLARE_WRITE8_MEMBER(superwng_fg_cram_w);
	60	DECLARE_WRITE8_MEMBER(superwng_tilebank_w);
	61	DECLARE_WRITE8_MEMBER(superwng_flip_screen_w);
	62	DECLARE_WRITE8_MEMBER(superwng_cointcnt1_w);
	63	DECLARE_WRITE8_MEMBER(superwng_cointcnt2_w);
53	64	};
54	65
55	66	static TILE_GET_INFO( get_bg_tile_info )
r14845	r14846
189	200	}
190	201	}
191	202
192		static WRITE8_HANDLER( superwng_nmi_enable_w )
	203	WRITE8_MEMBER(superwng_state::superwng_nmi_enable_w)
193	204	{
194		superwng_state *state = space->machine().driver_data<superwng_state>();
195		state->m_nmi_enable = data;
	205	m_nmi_enable = data;
196	206	}
197	207
198	208	static INTERRUPT_GEN( superwng_nmi_interrupt )
r14845	r14846
203	213	nmi_line_pulse(device);
204	214	}
205	215
206		static WRITE8_HANDLER( superwng_sound_interrupt_w )
	216	WRITE8_MEMBER(superwng_state::superwng_sound_interrupt_w)
207	217	{
208		superwng_state *state = space->machine().driver_data<superwng_state>();
209		state->m_sound_byte = data;
210		device_set_input_line(state->m_audiocpu, 0, ASSERT_LINE);
	218	m_sound_byte = data;
	219	device_set_input_line(m_audiocpu, 0, ASSERT_LINE);
211	220	}
212	221
213	222	static READ8_DEVICE_HANDLER( superwng_sound_byte_r )
r14845	r14846
217	226	return state->m_sound_byte;
218	227	}
219	228
220		static WRITE8_HANDLER( superwng_sound_nmi_clear_w )
	229	WRITE8_MEMBER(superwng_state::superwng_sound_nmi_clear_w)
221	230	{
222		superwng_state *state = space->machine().driver_data<superwng_state>();
223		device_set_input_line(state->m_audiocpu, INPUT_LINE_NMI, CLEAR_LINE);
	231	device_set_input_line(m_audiocpu, INPUT_LINE_NMI, CLEAR_LINE);
224	232	}
225	233
226	234	static INTERRUPT_GEN( superwng_sound_nmi_assert )
r14845	r14846
230	238	device_set_input_line(device, INPUT_LINE_NMI, ASSERT_LINE);
231	239	}
232	240
233		static WRITE8_HANDLER(superwng_bg_vram_w)
	241	WRITE8_MEMBER(superwng_state::superwng_bg_vram_w)
234	242	{
235		superwng_state *state = space->machine().driver_data<superwng_state>();
236		state->m_videoram_bg[offset] = data;
237		state->m_bg_tilemap->mark_tile_dirty(offset);
	243	m_videoram_bg[offset] = data;
	244	m_bg_tilemap->mark_tile_dirty(offset);
238	245	}
239	246
240		static WRITE8_HANDLER(superwng_bg_cram_w)
	247	WRITE8_MEMBER(superwng_state::superwng_bg_cram_w)
241	248	{
242		superwng_state *state = space->machine().driver_data<superwng_state>();
243		state->m_colorram_bg[offset] = data;
244		state->m_bg_tilemap->mark_tile_dirty(offset);
	249	m_colorram_bg[offset] = data;
	250	m_bg_tilemap->mark_tile_dirty(offset);
245	251	}
246	252
247		static WRITE8_HANDLER(superwng_fg_vram_w)
	253	WRITE8_MEMBER(superwng_state::superwng_fg_vram_w)
248	254	{
249		superwng_state *state = space->machine().driver_data<superwng_state>();
250		state->m_videoram_fg[offset] = data;
251		state->m_fg_tilemap->mark_tile_dirty(offset);
	255	m_videoram_fg[offset] = data;
	256	m_fg_tilemap->mark_tile_dirty(offset);
252	257	}
253	258
254		static WRITE8_HANDLER(superwng_fg_cram_w)
	259	WRITE8_MEMBER(superwng_state::superwng_fg_cram_w)
255	260	{
256		superwng_state *state = space->machine().driver_data<superwng_state>();
257		state->m_colorram_fg[offset] = data;
258		state->m_fg_tilemap->mark_tile_dirty(offset);
	261	m_colorram_fg[offset] = data;
	262	m_fg_tilemap->mark_tile_dirty(offset);
259	263	}
260	264
261		static WRITE8_HANDLER(superwng_tilebank_w)
	265	WRITE8_MEMBER(superwng_state::superwng_tilebank_w)
262	266	{
263		superwng_state *state = space->machine().driver_data<superwng_state>();
264		state->m_tile_bank = data;
265		state->m_bg_tilemap->mark_all_dirty();
266		state->m_fg_tilemap->mark_all_dirty();
	267	m_tile_bank = data;
	268	m_bg_tilemap->mark_all_dirty();
	269	m_fg_tilemap->mark_all_dirty();
267	270	}
268	271
269		static WRITE8_HANDLER( superwng_flip_screen_w )
	272	WRITE8_MEMBER(superwng_state::superwng_flip_screen_w)
270	273	{
271		superwng_state *state = space->machine().driver_data<superwng_state>();
272		flip_screen_set(space->machine(), ~data & 0x01);
273		state->m_bg_tilemap->mark_all_dirty();
274		state->m_fg_tilemap->mark_all_dirty();
	274	flip_screen_set(machine(), ~data & 0x01);
	275	m_bg_tilemap->mark_all_dirty();
	276	m_fg_tilemap->mark_all_dirty();
275	277	}
276	278
277		static WRITE8_HANDLER(superwng_cointcnt1_w)
	279	WRITE8_MEMBER(superwng_state::superwng_cointcnt1_w)
278	280	{
279		coin_counter_w(space->machine(), 0, data);
	281	coin_counter_w(machine(), 0, data);
280	282	}
281	283
282		static WRITE8_HANDLER(superwng_cointcnt2_w)
	284	WRITE8_MEMBER(superwng_state::superwng_cointcnt2_w)
283	285	{
284		coin_counter_w(space->machine(), 1, data);
	286	coin_counter_w(machine(), 1, data);
285	287	}
286	288
287	289	static ADDRESS_MAP_START( superwng_map, AS_PROGRAM, 8, superwng_state )
288	290	AM_RANGE(0x0000, 0x6fff) AM_ROM
289	291	AM_RANGE(0x7000, 0x7fff) AM_RAM
290		AM_RANGE(0x8000, 0x83ff) AM_RAM_WRITE_LEGACY(superwng_bg_vram_w) AM_BASE(m_videoram_bg)
291		AM_RANGE(0x8400, 0x87ff) AM_RAM_WRITE_LEGACY(superwng_fg_vram_w) AM_BASE(m_videoram_fg)
292		AM_RANGE(0x8800, 0x8bff) AM_RAM_WRITE_LEGACY(superwng_bg_cram_w) AM_BASE(m_colorram_bg)
293		AM_RANGE(0x8c00, 0x8fff) AM_RAM_WRITE_LEGACY(superwng_fg_cram_w) AM_BASE(m_colorram_fg)
	292	AM_RANGE(0x8000, 0x83ff) AM_RAM_WRITE(superwng_bg_vram_w) AM_BASE(m_videoram_bg)
	293	AM_RANGE(0x8400, 0x87ff) AM_RAM_WRITE(superwng_fg_vram_w) AM_BASE(m_videoram_fg)
	294	AM_RANGE(0x8800, 0x8bff) AM_RAM_WRITE(superwng_bg_cram_w) AM_BASE(m_colorram_bg)
	295	AM_RANGE(0x8c00, 0x8fff) AM_RAM_WRITE(superwng_fg_cram_w) AM_BASE(m_colorram_fg)
294	296	AM_RANGE(0x9800, 0x99ff) AM_RAM  //collision map
295	297	AM_RANGE(0xa000, 0xa000) AM_READ_PORT("P1")
296	298	AM_RANGE(0xa000, 0xa000) AM_WRITENOP //unknown
297	299	AM_RANGE(0xa080, 0xa080) AM_READ_PORT("P2")
298	300	AM_RANGE(0xa100, 0xa100) AM_READ_PORT("DSW1")
299		AM_RANGE(0xa100, 0xa100) AM_WRITE_LEGACY(superwng_sound_interrupt_w)
	301	AM_RANGE(0xa100, 0xa100) AM_WRITE(superwng_sound_interrupt_w)
300	302	AM_RANGE(0xa180, 0xa180) AM_READ_PORT("DSW2")
301	303	AM_RANGE(0xa180, 0xa180) AM_WRITENOP //watchdog ? int ack ?
302		AM_RANGE(0xa181, 0xa181) AM_WRITE_LEGACY(superwng_nmi_enable_w)
303		AM_RANGE(0xa182, 0xa182) AM_WRITE_LEGACY(superwng_tilebank_w)
304		AM_RANGE(0xa183, 0xa183) AM_WRITE_LEGACY(superwng_flip_screen_w)
305		AM_RANGE(0xa184, 0xa184) AM_WRITE_LEGACY(superwng_cointcnt1_w)
	304	AM_RANGE(0xa181, 0xa181) AM_WRITE(superwng_nmi_enable_w)
	305	AM_RANGE(0xa182, 0xa182) AM_WRITE(superwng_tilebank_w)
	306	AM_RANGE(0xa183, 0xa183) AM_WRITE(superwng_flip_screen_w)
	307	AM_RANGE(0xa184, 0xa184) AM_WRITE(superwng_cointcnt1_w)
306	308	AM_RANGE(0xa185, 0xa185) AM_WRITENOP //unknown , always(?) 0
307		AM_RANGE(0xa186, 0xa186) AM_WRITE_LEGACY(superwng_cointcnt2_w)
	309	AM_RANGE(0xa186, 0xa186) AM_WRITE(superwng_cointcnt2_w)
308	310	AM_RANGE(0xa187, 0xa187) AM_WRITENOP //unknown , always(?) 0
309	311	ADDRESS_MAP_END
310	312
311	313	static ADDRESS_MAP_START( superwng_sound_map, AS_PROGRAM, 8, superwng_state )
312	314	AM_RANGE(0x0000, 0x1fff) AM_ROM
313	315	AM_RANGE(0x2000, 0x23ff) AM_RAM
314		AM_RANGE(0x3000, 0x3000) AM_WRITE_LEGACY(superwng_sound_nmi_clear_w)
	316	AM_RANGE(0x3000, 0x3000) AM_WRITE(superwng_sound_nmi_clear_w)
315	317	AM_RANGE(0x4000, 0x4000) AM_DEVREADWRITE_LEGACY("ay1", ay8910_r, ay8910_data_w)
316	318	AM_RANGE(0x5000, 0x5000) AM_DEVWRITE_LEGACY("ay1", ay8910_address_w)
317	319	AM_RANGE(0x6000, 0x6000) AM_DEVREADWRITE_LEGACY("ay2", ay8910_r, ay8910_data_w)

src/mame/drivers/guab.c

r14845	r14846
81	81	struct ef9369 m_pal;
82	82	emu_timer *m_fdc_timer;
83	83	struct wd1770 m_fdc;
	84	DECLARE_WRITE16_MEMBER(guab_tms34061_w);
	85	DECLARE_READ16_MEMBER(guab_tms34061_r);
	86	DECLARE_WRITE16_MEMBER(ef9369_w);
	87	DECLARE_READ16_MEMBER(ef9369_r);
	88	DECLARE_WRITE16_MEMBER(wd1770_w);
	89	DECLARE_READ16_MEMBER(wd1770_r);
	90	DECLARE_READ16_MEMBER(io_r);
	91	DECLARE_WRITE16_MEMBER(io_w);
84	92	};
85	93
86	94
r14845	r14846
128	136	};
129	137
130	138
131		static WRITE16_HANDLER( guab_tms34061_w )
	139	WRITE16_MEMBER(guab_state::guab_tms34061_w)
132	140	{
133	141	int func = (offset >> 19) & 3;
134	142	int row = (offset >> 7) & 0xff;
r14845	r14846
140	148	col = offset <<= 1;
141	149
142	150	if (ACCESSING_BITS_8_15)
143		tms34061_w(space, col, row, func, data >> 8);
	151	tms34061_w(&space, col, row, func, data >> 8);
144	152
145	153	if (ACCESSING_BITS_0_7)
146		tms34061_w(space, col | 1, row, func, data & 0xff);
	154	tms34061_w(&space, col | 1, row, func, data & 0xff);
147	155	}
148	156
149	157
150		static READ16_HANDLER( guab_tms34061_r )
	158	READ16_MEMBER(guab_state::guab_tms34061_r)
151	159	{
152	160	UINT16 data = 0;
153	161	int func = (offset >> 19) & 3;
r14845	r14846
160	168	col = offset <<= 1;
161	169
162	170	if (ACCESSING_BITS_8_15)
163		data |= tms34061_r(space, col, row, func) << 8;
	171	data |= tms34061_r(&space, col, row, func) << 8;
164	172
165	173	if (ACCESSING_BITS_0_7)
166		data |= tms34061_r(space, col | 1, row, func);
	174	data |= tms34061_r(&space, col | 1, row, func);
167	175
168	176	return data;
169	177	}
r14845	r14846
175	183	****************************/
176	184
177	185	/* Non-multiplexed mode */
178		static WRITE16_HANDLER( ef9369_w )
	186	WRITE16_MEMBER(guab_state::ef9369_w)
179	187	{
180		guab_state *state = space->machine().driver_data<guab_state>();
181		struct ef9369 &pal = state->m_pal;
	188	struct ef9369 &pal = m_pal;
182	189	data &= 0x00ff;
183	190
184	191	/* Address register */
r14845	r14846
207	214	col = pal.clut[entry] & 0xfff;
208	215
209	216	/* Update the MAME palette */
210		palette_set_color_rgb(space->machine(), entry, pal4bit(col >> 0), pal4bit(col >> 4), pal4bit(col >> 8));
	217	palette_set_color_rgb(machine(), entry, pal4bit(col >> 0), pal4bit(col >> 4), pal4bit(col >> 8));
211	218	}
212	219
213	220	/* Address register auto-increment */
r14845	r14846
216	223	}
217	224	}
218	225
219		static READ16_HANDLER( ef9369_r )
	226	READ16_MEMBER(guab_state::ef9369_r)
220	227	{
221		guab_state *state = space->machine().driver_data<guab_state>();
222		struct ef9369 &pal = state->m_pal;
	228	struct ef9369 &pal = m_pal;
223	229	if ((offset & 1) == 0)
224	230	{
225	231	UINT16 col = pal.clut[pal.addr >> 1];
r14845	r14846
372	378	}
373	379
374	380
375		static WRITE16_HANDLER( wd1770_w )
	381	WRITE16_MEMBER(guab_state::wd1770_w)
376	382	{
377		guab_state *state = space->machine().driver_data<guab_state>();
378		struct wd1770 &fdc = state->m_fdc;
	383	struct wd1770 &fdc = m_fdc;
379	384	data &= 0xff;
380	385
381	386	switch (offset)
r14845	r14846
445	450	fdc.sector));
446	451
447	452	/* Set the data read timer */
448		state->m_fdc_timer->adjust(attotime::from_usec(USEC_DELAY));
	453	m_fdc_timer->adjust(attotime::from_usec(USEC_DELAY));
449	454
450	455	break;
451	456	}
r14845	r14846
464	469	fdc.sector));
465	470
466	471	/* Trigger a DRQ interrupt on the CPU */
467		cputag_set_input_line(space->machine(), "maincpu", INT_FLOPPYCTRL, ASSERT_LINE);
	472	cputag_set_input_line(machine(), "maincpu", INT_FLOPPYCTRL, ASSERT_LINE);
468	473	fdc.status |= DATA_REQUEST;
469	474	break;
470	475	}
r14845	r14846
482	487	case 13:
483	488	{
484	489	/* Stop any operation in progress */
485		state->m_fdc_timer->reset();
	490	m_fdc_timer->reset();
486	491	fdc.status &= ~BUSY;
487	492	FDC_LOG(("Force Interrupt\n"));
488	493	break;
r14845	r14846
509	514	fdc.data = data;
510	515
511	516	/* Clear the DRQ */
512		cputag_set_input_line(space->machine(), "maincpu", INT_FLOPPYCTRL, CLEAR_LINE);
	517	cputag_set_input_line(machine(), "maincpu", INT_FLOPPYCTRL, CLEAR_LINE);
513	518
514	519	/* Queue an event to write the data if write command was specified */
515	520	if (fdc.cmd & 0x20)
516		state->m_fdc_timer->adjust(attotime::from_usec(USEC_DELAY));
	521	m_fdc_timer->adjust(attotime::from_usec(USEC_DELAY));
517	522
518	523	break;
519	524	}
520	525	}
521	526	}
522	527
523		static READ16_HANDLER( wd1770_r )
	528	READ16_MEMBER(guab_state::wd1770_r)
524	529	{
525		guab_state *state = space->machine().driver_data<guab_state>();
526		struct wd1770 &fdc = state->m_fdc;
	530	struct wd1770 &fdc = m_fdc;
527	531	UINT16 retval = 0;
528	532
529	533	switch (offset)
r14845	r14846
548	552	retval = fdc.data;
549	553
550	554	/* Clear the DRQ */
551		cputag_set_input_line(space->machine(), "maincpu", INT_FLOPPYCTRL, CLEAR_LINE);
	555	cputag_set_input_line(machine(), "maincpu", INT_FLOPPYCTRL, CLEAR_LINE);
552	556	fdc.status &= ~DATA_REQUEST;
553	557	break;
554	558	}
r14845	r14846
564	568	*
565	569	****************************************/
566	570
567		static READ16_HANDLER( io_r )
	571	READ16_MEMBER(guab_state::io_r)
568	572	{
569	573	static const char *const portnames[] = { "IN0", "IN1", "IN2" };
570	574
r14845	r14846
574	578	case 0x01:
575	579	case 0x02:
576	580	{
577		return input_port_read(space->machine(), portnames[offset]);
	581	return input_port_read(machine(), portnames[offset]);
578	582	}
579	583	case 0x30:
580	584	{
r14845	r14846
608	612	*
609	613	****************************************/
610	614
611		static WRITE16_HANDLER( io_w )
	615	WRITE16_MEMBER(guab_state::io_w)
612	616	{
613		guab_state *state = space->machine().driver_data<guab_state>();
614		struct wd1770 &fdc = state->m_fdc;
	617	struct wd1770 &fdc = m_fdc;
615	618	switch (offset)
616	619	{
617	620	case 0x10:
r14845	r14846
646	649	}
647	650	case 0x30:
648	651	{
649		sn76496_w(space->machine().device("snsnd"), 0, data & 0xff);
	652	sn76496_w(machine().device("snsnd"), 0, data & 0xff);
650	653	break;
651	654	}
652	655	case 0x31:
r14845	r14846
682	685	static ADDRESS_MAP_START( guab_map, AS_PROGRAM, 16, guab_state )
683	686	AM_RANGE(0x000000, 0x00ffff) AM_ROM
684	687	AM_RANGE(0x040000, 0x04ffff) AM_ROM AM_REGION("maincpu", 0x10000)
685		AM_RANGE(0x0c0000, 0x0c007f) AM_READWRITE_LEGACY(io_r, io_w)
	688	AM_RANGE(0x0c0000, 0x0c007f) AM_READWRITE(io_r, io_w)
686	689	AM_RANGE(0x0c0080, 0x0c0083) AM_NOP /* ACIA 1 */
687	690	AM_RANGE(0x0c00a0, 0x0c00a3) AM_NOP /* ACIA 2 */
688	691	AM_RANGE(0x0c00c0, 0x0c00cf) AM_DEVREADWRITE8("6840ptm", ptm6840_device, read, write, 0xff)
689		AM_RANGE(0x0c00e0, 0x0c00e7) AM_READWRITE_LEGACY(wd1770_r, wd1770_w)
	692	AM_RANGE(0x0c00e0, 0x0c00e7) AM_READWRITE(wd1770_r, wd1770_w)
690	693	AM_RANGE(0x080000, 0x080fff) AM_RAM
691		AM_RANGE(0x100000, 0x100003) AM_READWRITE_LEGACY(ef9369_r, ef9369_w)
692		AM_RANGE(0x800000, 0xb0ffff) AM_READWRITE_LEGACY(guab_tms34061_r, guab_tms34061_w)
	694	AM_RANGE(0x100000, 0x100003) AM_READWRITE(ef9369_r, ef9369_w)
	695	AM_RANGE(0x800000, 0xb0ffff) AM_READWRITE(guab_tms34061_r, guab_tms34061_w)
693	696	AM_RANGE(0xb10000, 0xb1ffff) AM_RAM
694	697	AM_RANGE(0xb80000, 0xb8ffff) AM_RAM
695	698	AM_RANGE(0xb90000, 0xb9ffff) AM_RAM

src/mame/drivers/cyclemb.c

r14845	r14846
86	86	UINT8 *m_obj1_ram;
87	87	UINT8 *m_obj2_ram;
88	88	UINT8 *m_obj3_ram;
	89	DECLARE_WRITE8_MEMBER(cyclemb_bankswitch_w);
	90	DECLARE_READ8_MEMBER(mcu_status_r);
	91	DECLARE_WRITE8_MEMBER(sound_cmd_w);
	92	DECLARE_WRITE8_MEMBER(cyclemb_flip_w);
89	93	};
90	94
91	95
r14845	r14846
215	219	return 0;
216	220	}
217	221
218		static WRITE8_HANDLER( cyclemb_bankswitch_w )
	222	WRITE8_MEMBER(cyclemb_state::cyclemb_bankswitch_w)
219	223	{
220		memory_set_bank(space->machine(), "bank1", data & 3);
	224	memory_set_bank(machine(), "bank1", data & 3);
221	225	}
222	226
223	227	#if 0
224		static WRITE8_HANDLER( sound_cmd_w )
	228	WRITE8_MEMBER(cyclemb_state::sound_cmd_w)
225	229	{
226	230	soundlatch_w(space, 0, data & 0xff);
227		cputag_set_input_line(space->machine(), "audiocpu", 0, HOLD_LINE);
	231	cputag_set_input_line(machine(), "audiocpu", 0, HOLD_LINE);
228	232	}
229	233	#endif
230	234
231	235	#if 0
232		static READ8_HANDLER( mcu_status_r )
	236	READ8_MEMBER(cyclemb_state::mcu_status_r)
233	237	{
234	238	return 1;
235	239	}
236	240
237	241
238		static WRITE8_HANDLER( sound_cmd_w ) //actually ciom
	242	WRITE8_MEMBER(cyclemb_state::sound_cmd_w)//actually ciom
239	243	{
240	244	soundlatch_w(space, 0, data & 0xff);
241		cputag_set_input_line(space->machine(), "audiocpu", 0, HOLD_LINE);
	245	cputag_set_input_line(machine(), "audiocpu", 0, HOLD_LINE);
242	246	}
243	247	#endif
244	248
245		static WRITE8_HANDLER( cyclemb_flip_w )
	249	WRITE8_MEMBER(cyclemb_state::cyclemb_flip_w)
246	250	{
247		flip_screen_set(space->machine(), data & 1);
	251	flip_screen_set(machine(), data & 1);
248	252
249	253	// a bunch of other things are setted here
250	254	}
r14845	r14846
262	266
263	267	static ADDRESS_MAP_START( cyclemb_io, AS_IO, 8, cyclemb_state )
264	268	//  ADDRESS_MAP_GLOBAL_MASK(0xff)
265		AM_RANGE(0xc000, 0xc000) AM_WRITE_LEGACY(cyclemb_bankswitch_w)
	269	AM_RANGE(0xc000, 0xc000) AM_WRITE(cyclemb_bankswitch_w)
266	270	AM_RANGE(0xc09e, 0xc09f) AM_READWRITE_LEGACY(cyclemb_8741_0_r, cyclemb_8741_0_w)
267		AM_RANGE(0xc0bf, 0xc0bf) AM_WRITE_LEGACY(cyclemb_flip_w) //flip screen
	271	AM_RANGE(0xc0bf, 0xc0bf) AM_WRITE(cyclemb_flip_w) //flip screen
268	272	ADDRESS_MAP_END
269	273
270	274	static ADDRESS_MAP_START( cyclemb_sound_map, AS_PROGRAM, 8, cyclemb_state )

src/mame/drivers/bingor.c

r14845	r14846
450	450	: driver_device(mconfig, type, tag) { }
451	451
452	452	UINT16 *m_blit_ram;
	453	DECLARE_READ16_MEMBER(test_r);
	454	DECLARE_READ8_MEMBER(test8_r);
453	455	};
454	456
455	457
r14845	r14846
500	502	}
501	503
502	504	#if 0
503		static READ16_HANDLER( test_r )
	505	READ16_MEMBER(bingor_state::test_r)
504	506	{
505		return space->machine().rand();
	507	return machine().rand();
506	508	}
507	509	#endif
508	510
r14845	r14846
515	517	ADDRESS_MAP_END
516	518
517	519	static ADDRESS_MAP_START( bingor_io, AS_IO, 16, bingor_state )
518		//  AM_RANGE(0x0000, 0x00ff) AM_READ_LEGACY(test_r )
	520	//  AM_RANGE(0x0000, 0x00ff) AM_READ(test_r )
519	521	AM_RANGE(0x0100, 0x0101) AM_DEVWRITE8_LEGACY("saa", saa1099_data_w, 0x00ff)
520	522	AM_RANGE(0x0102, 0x0103) AM_DEVWRITE8_LEGACY("saa", saa1099_control_w, 0x00ff)
521		//  AM_RANGE(0x0200, 0x0201) AM_READ_LEGACY(test_r )
	523	//  AM_RANGE(0x0200, 0x0201) AM_READ(test_r )
522	524	ADDRESS_MAP_END
523	525
524		static READ8_HANDLER( test8_r )
	526	READ8_MEMBER(bingor_state::test8_r)
525	527	{
526		return space->machine().rand();
	528	return machine().rand();
527	529	}
528	530
529	531	static ADDRESS_MAP_START( pic_io_map, AS_IO, 8, bingor_state )
530		AM_RANGE(0x02, 0x02) AM_READ_LEGACY(test8_r)
	532	AM_RANGE(0x02, 0x02) AM_READ(test8_r)
531	533	AM_RANGE(0x10, 0x10) AM_READNOP
532	534	ADDRESS_MAP_END
533	535

src/mame/drivers/beaminv.c

r14845	r14846
74	74
75	75	/* devices */
76	76	device_t *m_maincpu;
	77	DECLARE_READ8_MEMBER(v128_r);
	78	DECLARE_WRITE8_MEMBER(controller_select_w);
	79	DECLARE_READ8_MEMBER(controller_r);
77	80	};
78	81
79	82
r14845	r14846
192	195	}
193	196
194	197
195		static READ8_HANDLER( v128_r )
	198	READ8_MEMBER(beaminv_state::v128_r)
196	199	{
197		return (space->machine().primary_screen->vpos() >> 7) & 0x01;
	200	return (machine().primary_screen->vpos() >> 7) & 0x01;
198	201	}
199	202
200	203
r14845	r14846
209	212	#define P2_CONTROL_PORT_TAG   ("CONTP2")
210	213
211	214
212		static WRITE8_HANDLER( controller_select_w )
	215	WRITE8_MEMBER(beaminv_state::controller_select_w)
213	216	{
214		beaminv_state *state = space->machine().driver_data<beaminv_state>();
215	217	/* 0x01 (player 1) or 0x02 (player 2) */
216		state->m_controller_select = data;
	218	m_controller_select = data;
217	219	}
218	220
219	221
220		static READ8_HANDLER( controller_r )
	222	READ8_MEMBER(beaminv_state::controller_r)
221	223	{
222		beaminv_state *state = space->machine().driver_data<beaminv_state>();
223		return input_port_read(space->machine(), (state->m_controller_select == 1) ? P1_CONTROL_PORT_TAG : P2_CONTROL_PORT_TAG);
	224	return input_port_read(machine(), (m_controller_select == 1) ? P1_CONTROL_PORT_TAG : P2_CONTROL_PORT_TAG);
224	225	}
225	226
226	227
r14845	r14846
236	237	AM_RANGE(0x1800, 0x1fff) AM_RAM
237	238	AM_RANGE(0x2400, 0x2400) AM_MIRROR(0x03ff) AM_READ_PORT("DSW")
238	239	AM_RANGE(0x2800, 0x2800) AM_MIRROR(0x03ff) AM_READ_PORT("INPUTS")
239		AM_RANGE(0x3400, 0x3400) AM_MIRROR(0x03ff) AM_READ_LEGACY(controller_r)
240		AM_RANGE(0x3800, 0x3800) AM_MIRROR(0x03ff) AM_READ_LEGACY(v128_r)
	240	AM_RANGE(0x3400, 0x3400) AM_MIRROR(0x03ff) AM_READ(controller_r)
	241	AM_RANGE(0x3800, 0x3800) AM_MIRROR(0x03ff) AM_READ(v128_r)
241	242	AM_RANGE(0x4000, 0x5fff) AM_RAM AM_BASE_SIZE(m_videoram, m_videoram_size)
242	243	ADDRESS_MAP_END
243	244
r14845	r14846
251	252
252	253	static ADDRESS_MAP_START( main_io_map, AS_IO, 8, beaminv_state )
253	254	ADDRESS_MAP_GLOBAL_MASK(0xff)
254		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(controller_select_w) /* to be confirmed */
	255	AM_RANGE(0x00, 0x00) AM_WRITE(controller_select_w) /* to be confirmed */
255	256	ADDRESS_MAP_END
256	257
257	258

src/mame/drivers/sengokmj.c

r14845	r14846
67	67
68	68	UINT16 m_sengokumj_mux_data;
69	69	UINT8 m_hopper_io;
	70	DECLARE_READ16_MEMBER(mahjong_panel_r);
	71	DECLARE_WRITE16_MEMBER(mahjong_panel_w);
	72	DECLARE_WRITE16_MEMBER(sengokmj_out_w);
	73	DECLARE_READ16_MEMBER(sengokmj_system_r);
70	74	};
71	75
72	76
73	77
74	78	/* Multiplexer device for the mahjong panel */
75		static READ16_HANDLER( mahjong_panel_r )
	79	READ16_MEMBER(sengokmj_state::mahjong_panel_r)
76	80	{
77		sengokmj_state *state = space->machine().driver_data<sengokmj_state>();
78		switch(state->m_sengokumj_mux_data)
	81	switch(m_sengokumj_mux_data)
79	82	{
80		case 0x0100: return input_port_read(space->machine(), "KEY0");
81		case 0x0200: return input_port_read(space->machine(), "KEY1");
82		case 0x0400: return input_port_read(space->machine(), "KEY2");
83		case 0x0800: return input_port_read(space->machine(), "KEY3");
84		case 0x1000: return input_port_read(space->machine(), "KEY4");
85		case 0x2000: return input_port_read(space->machine(), "UNUSED");
	83	case 0x0100: return input_port_read(machine(), "KEY0");
	84	case 0x0200: return input_port_read(machine(), "KEY1");
	85	case 0x0400: return input_port_read(machine(), "KEY2");
	86	case 0x0800: return input_port_read(machine(), "KEY3");
	87	case 0x1000: return input_port_read(machine(), "KEY4");
	88	case 0x2000: return input_port_read(machine(), "UNUSED");
86	89	}
87	90
88	91	return 0xffff;
89	92	}
90	93
91		static WRITE16_HANDLER( mahjong_panel_w )
	94	WRITE16_MEMBER(sengokmj_state::mahjong_panel_w)
92	95	{
93		sengokmj_state *state = space->machine().driver_data<sengokmj_state>();
94		state->m_sengokumj_mux_data = data;
	96	m_sengokumj_mux_data = data;
95	97	}
96	98
97		static WRITE16_HANDLER( sengokmj_out_w )
	99	WRITE16_MEMBER(sengokmj_state::sengokmj_out_w)
98	100	{
99		sengokmj_state *state = space->machine().driver_data<sengokmj_state>();
100	101	/* ---- ---- ---x ---- J.P. Signal (?)*/
101	102	/* ---- ---- ---- -x-- Coin counter (done AFTER that you press start)*/
102	103	/* ---- ---- ---- --x- Cash enable (lockout)*/
103	104	/* ---- ---- ---- ---x Hopper 10 */
104		coin_lockout_w(space->machine(), 0,~data & 2);
105		coin_lockout_w(space->machine(), 1,~data & 2);
106		coin_counter_w(space->machine(), 0,data & 4);
107		state->m_hopper_io = ((data & 1)<<6);
108		//  popmessage("%02x",state->m_hopper_io);
	105	coin_lockout_w(machine(), 0,~data & 2);
	106	coin_lockout_w(machine(), 1,~data & 2);
	107	coin_counter_w(machine(), 0,data & 4);
	108	m_hopper_io = ((data & 1)<<6);
	109	//  popmessage("%02x",m_hopper_io);
109	110	}
110	111
111		static READ16_HANDLER( sengokmj_system_r )
	112	READ16_MEMBER(sengokmj_state::sengokmj_system_r)
112	113	{
113		sengokmj_state *state = space->machine().driver_data<sengokmj_state>();
114		return (input_port_read(space->machine(), "SYSTEM") & 0xffbf) | state->m_hopper_io;
	114	return (input_port_read(machine(), "SYSTEM") & 0xffbf) | m_hopper_io;
115	115	}
116	116
117	117	static ADDRESS_MAP_START( sengokmj_map, AS_PROGRAM, 16, sengokmj_state )
r14845	r14846
134	134	//  AM_RANGE(0x8080, 0x8081) CRTC extra register?
135	135	//  AM_RANGE(0x80c0, 0x80c1) CRTC extra register?
136	136	//  AM_RANGE(0x8100, 0x8101) AM_WRITENOP // always 0
137		AM_RANGE(0x8180, 0x8181) AM_WRITE_LEGACY(sengokmj_out_w)
138		AM_RANGE(0x8140, 0x8141) AM_WRITE_LEGACY(mahjong_panel_w)
	137	AM_RANGE(0x8180, 0x8181) AM_WRITE(sengokmj_out_w)
	138	AM_RANGE(0x8140, 0x8141) AM_WRITE(mahjong_panel_w)
139	139	AM_RANGE(0xc000, 0xc001) AM_READ_PORT("DSW1")
140		AM_RANGE(0xc002, 0xc003) AM_READ_LEGACY(mahjong_panel_r)
141		AM_RANGE(0xc004, 0xc005) AM_READ_LEGACY(sengokmj_system_r) //switches
	140	AM_RANGE(0xc002, 0xc003) AM_READ(mahjong_panel_r)
	141	AM_RANGE(0xc004, 0xc005) AM_READ(sengokmj_system_r) //switches
142	142	ADDRESS_MAP_END
143	143
144	144

src/mame/drivers/cham24.c

r14845	r14846
73	73	UINT32 m_in_1;
74	74	UINT32 m_in_0_shift;
75	75	UINT32 m_in_1_shift;
	76	DECLARE_WRITE8_MEMBER(nt_w);
	77	DECLARE_READ8_MEMBER(nt_r);
	78	DECLARE_WRITE8_MEMBER(sprite_dma_w);
	79	DECLARE_READ8_MEMBER(cham24_IN0_r);
	80	DECLARE_WRITE8_MEMBER(cham24_IN0_w);
	81	DECLARE_READ8_MEMBER(cham24_IN1_r);
	82	DECLARE_WRITE8_MEMBER(cham24_mapper_w);
76	83	};
77	84
78	85
r14845	r14846
110	117	}
111	118	}
112	119
113		static WRITE8_HANDLER( nt_w )
	120	WRITE8_MEMBER(cham24_state::nt_w)
114	121	{
115		cham24_state *state = space->machine().driver_data<cham24_state>();
116	122	int page = ((offset & 0xc00) >> 10);
117		state->m_nt_page[page][offset & 0x3ff] = data;
	123	m_nt_page[page][offset & 0x3ff] = data;
118	124	}
119	125
120		static READ8_HANDLER( nt_r )
	126	READ8_MEMBER(cham24_state::nt_r)
121	127	{
122		cham24_state *state = space->machine().driver_data<cham24_state>();
123	128	int page = ((offset & 0xc00) >> 10);
124		return state->m_nt_page[page][offset & 0x3ff];
	129	return m_nt_page[page][offset & 0x3ff];
125	130
126	131	}
127	132
128		static WRITE8_HANDLER( sprite_dma_w )
	133	WRITE8_MEMBER(cham24_state::sprite_dma_w)
129	134	{
130	135	int source = (data & 7);
131		ppu2c0x_device *ppu = space->machine().device<ppu2c0x_device>("ppu");
132		ppu->spriteram_dma(space, source);
	136	ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
	137	ppu->spriteram_dma(&space, source);
133	138	}
134	139
135	140	static READ8_DEVICE_HANDLER( psg_4015_r )
r14845	r14846
148	153	}
149	154
150	155
151		static READ8_HANDLER( cham24_IN0_r )
	156	READ8_MEMBER(cham24_state::cham24_IN0_r)
152	157	{
153		cham24_state *state = space->machine().driver_data<cham24_state>();
154		return ((state->m_in_0 >> state->m_in_0_shift++) & 0x01) | 0x40;
	158	return ((m_in_0 >> m_in_0_shift++) & 0x01) | 0x40;
155	159	}
156	160
157		static WRITE8_HANDLER( cham24_IN0_w )
	161	WRITE8_MEMBER(cham24_state::cham24_IN0_w)
158	162	{
159		cham24_state *state = space->machine().driver_data<cham24_state>();
160	163	if (data & 0xfe)
161	164	{
162	165	//logerror("Unhandled cham24_IN0_w write: data = %02X\n", data);
r14845	r14846
167	170	return;
168	171	}
169	172
170		state->m_in_0_shift = 0;
171		state->m_in_1_shift = 0;
	173	m_in_0_shift = 0;
	174	m_in_1_shift = 0;
172	175
173		state->m_in_0 = input_port_read(space->machine(), "P1");
174		state->m_in_1 = input_port_read(space->machine(), "P2");
	176	m_in_0 = input_port_read(machine(), "P1");
	177	m_in_1 = input_port_read(machine(), "P2");
175	178
176	179	}
177	180
178		static READ8_HANDLER( cham24_IN1_r )
	181	READ8_MEMBER(cham24_state::cham24_IN1_r)
179	182	{
180		cham24_state *state = space->machine().driver_data<cham24_state>();
181		return ((state->m_in_1 >> state->m_in_1_shift++) & 0x01) | 0x40;
	183	return ((m_in_1 >> m_in_1_shift++) & 0x01) | 0x40;
182	184	}
183	185
184		static WRITE8_HANDLER( cham24_mapper_w )
	186	WRITE8_MEMBER(cham24_state::cham24_mapper_w)
185	187	{
186	188	UINT32 gfx_bank = offset & 0x3f;
187	189	UINT32 prg_16k_bank_page = (offset >> 6) & 0x01;
r14845	r14846
189	191	UINT32 prg_bank_page_size = (offset >> 12) & 0x01;
190	192	UINT32 gfx_mirroring = (offset >> 13) & 0x01;
191	193
192		UINT8* dst = space->machine().region("maincpu")->base();
193		UINT8* src = space->machine().region("user1")->base();
	194	UINT8* dst = machine().region("maincpu")->base();
	195	UINT8* src = machine().region("user1")->base();
194	196
195	197	// switch PPU VROM bank
196		memory_set_bankptr(space->machine(), "bank1", space->machine().region("gfx1")->base() + (0x2000 * gfx_bank));
	198	memory_set_bankptr(machine(), "bank1", machine().region("gfx1")->base() + (0x2000 * gfx_bank));
197	199
198	200	// set gfx mirroring
199		cham24_set_mirroring(space->machine(), gfx_mirroring != 0 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	201	cham24_set_mirroring(machine(), gfx_mirroring != 0 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
200	202
201	203	// switch PRG bank
202	204	if (prg_bank_page_size == 0)
r14845	r14846
225	227	AM_RANGE(0x0000, 0x07ff) AM_RAM   /* NES RAM */
226	228	AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu", ppu2c0x_device, read, write)
227	229	AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes", nes_psg_r, nes_psg_w)         /* PSG primary registers */
228		AM_RANGE(0x4014, 0x4014) AM_WRITE_LEGACY(sprite_dma_w)
	230	AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_w)
229	231	AM_RANGE(0x4015, 0x4015) AM_DEVREADWRITE_LEGACY("nes", psg_4015_r, psg_4015_w)         /* PSG status / first control register */
230		AM_RANGE(0x4016, 0x4016) AM_READWRITE_LEGACY(cham24_IN0_r,        cham24_IN0_w)         /* IN0 - input port 1 */
231		AM_RANGE(0x4017, 0x4017) AM_READ_LEGACY(cham24_IN1_r) AM_DEVWRITE_LEGACY("nes", psg_4017_w)      /* IN1 - input port 2 / PSG second control register */
232		AM_RANGE(0x8000, 0xffff) AM_ROM AM_WRITE_LEGACY(cham24_mapper_w)
	232	AM_RANGE(0x4016, 0x4016) AM_READWRITE(cham24_IN0_r,        cham24_IN0_w)         /* IN0 - input port 1 */
	233	AM_RANGE(0x4017, 0x4017) AM_READ(cham24_IN1_r) AM_DEVWRITE_LEGACY("nes", psg_4017_w)      /* IN1 - input port 2 / PSG second control register */
	234	AM_RANGE(0x8000, 0xffff) AM_ROM AM_WRITE(cham24_mapper_w)
233	235	ADDRESS_MAP_END
234	236
235	237	static INPUT_PORTS_START( cham24 )
r14845	r14846
320	322	state->m_nt_page[3] = state->m_nt_ram + 0xc00;
321	323
322	324	/* and read/write handlers */
323		machine.device("ppu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0x2000, 0x3eff, FUNC(nt_r), FUNC(nt_w));
	325	machine.device("ppu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x2000, 0x3eff,read8_delegate(FUNC(cham24_state::nt_r), state), write8_delegate(FUNC(cham24_state::nt_w), state));
324	326	}
325	327
326	328	static DRIVER_INIT( cham24 )

src/mame/drivers/rbmk.c

r14845	r14846
67	67	UINT16 *m_gms_vidram2;
68	68	UINT16 m_tilebank;
69	69	UINT8 m_mux_data;
	70	DECLARE_READ16_MEMBER(gms_read);
	71	DECLARE_WRITE16_MEMBER(gms_write1);
	72	DECLARE_WRITE16_MEMBER(gms_write2);
	73	DECLARE_WRITE16_MEMBER(gms_write3);
	74	DECLARE_READ8_MEMBER(rbmk_mcu_io_r);
	75	DECLARE_WRITE8_MEMBER(rbmk_mcu_io_w);
	76	DECLARE_WRITE8_MEMBER(mcu_io_mux_w);
70	77	};
71	78
72	79
73		static READ16_HANDLER( gms_read )
	80	READ16_MEMBER(rbmk_state::gms_read)
74	81	{
75		return space->machine().rand();
	82	return machine().rand();
76	83	}
77	84
78	85
79		static WRITE16_HANDLER( gms_write1 )
	86	WRITE16_MEMBER(rbmk_state::gms_write1)
80	87	{
81
82	88	}
83	89
84		static WRITE16_HANDLER( gms_write2 )
	90	WRITE16_MEMBER(rbmk_state::gms_write2)
85	91	{
86		rbmk_state *state = space->machine().driver_data<rbmk_state>();
87		state->m_tilebank=data;
	92	m_tilebank=data;
88	93	}
89	94
90		static WRITE16_HANDLER( gms_write3 )
	95	WRITE16_MEMBER(rbmk_state::gms_write3)
91	96	{
92
93	97	}
94	98
95	99	static WRITE16_DEVICE_HANDLER( eeprom_w )
r14845	r14846
115	119	AM_RANGE(0x900000, 0x900fff) AM_RAM_WRITE_LEGACY(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)
116	120	AM_RANGE(0x9c0000, 0x9c0fff) AM_RAM AM_BASE(m_gms_vidram)
117	121	AM_RANGE(0xb00000, 0xb00001) AM_DEVWRITE_LEGACY("eeprom", eeprom_w)
118		AM_RANGE(0xC00000, 0xC00001) AM_READ_PORT("IN0") AM_WRITE_LEGACY(gms_write1)
119		AM_RANGE(0xC08000, 0xC08001) AM_READ_PORT("IN1") AM_WRITE_LEGACY(gms_write2)
	122	AM_RANGE(0xC00000, 0xC00001) AM_READ_PORT("IN0") AM_WRITE(gms_write1)
	123	AM_RANGE(0xC08000, 0xC08001) AM_READ_PORT("IN1") AM_WRITE(gms_write2)
120	124	AM_RANGE(0xC10000, 0xC10001) AM_READ_PORT("IN3")
121		AM_RANGE(0xC18080, 0xC18081) AM_READ_LEGACY(gms_read)
	125	AM_RANGE(0xC18080, 0xC18081) AM_READ(gms_read)
122	126	AM_RANGE(0xC20000, 0xC20001) AM_READ_PORT("IN2")
123		AM_RANGE(0xC28000, 0xC28001) AM_WRITE_LEGACY(gms_write3)
	127	AM_RANGE(0xC28000, 0xC28001) AM_WRITE(gms_write3)
124	128	ADDRESS_MAP_END
125	129
126	130
r14845	r14846
128	132	//  AM_RANGE(0x0000, 0x0fff) AM_ROM
129	133	ADDRESS_MAP_END
130	134
131		static READ8_HANDLER( rbmk_mcu_io_r )
	135	READ8_MEMBER(rbmk_state::rbmk_mcu_io_r)
132	136	{
133		rbmk_state *state = space->machine().driver_data<rbmk_state>();
134		if(state->m_mux_data & 8)
	137	if(m_mux_data & 8)
135	138	{
136		return ym2151_r(space->machine().device("ymsnd"), offset & 1);
	139	return ym2151_r(machine().device("ymsnd"), offset & 1);
137	140	}
138		else if(state->m_mux_data & 4)
	141	else if(m_mux_data & 4)
139	142	{
140	143	//printf("%02x R\n",offset);
141	144	// ...
142	145	return 0xff;
143	146	}
144	147	else
145		printf("Warning: mux data R = %02x",state->m_mux_data);
	148	printf("Warning: mux data R = %02x",m_mux_data);
146	149
147	150	return 0xff;
148	151	}
149	152
150		static WRITE8_HANDLER( rbmk_mcu_io_w )
	153	WRITE8_MEMBER(rbmk_state::rbmk_mcu_io_w)
151	154	{
152		rbmk_state *state = space->machine().driver_data<rbmk_state>();
153		if(state->m_mux_data & 8) { ym2151_w(space->machine().device("ymsnd"), offset & 1, data); }
154		else if(state->m_mux_data & 4)
	155	if(m_mux_data & 8) { ym2151_w(machine().device("ymsnd"), offset & 1, data); }
	156	else if(m_mux_data & 4)
155	157	{
156	158	//printf("%02x %02x W\n",offset,data);
157	159	// ...
158	160	}
159	161	else
160		printf("Warning: mux data W = %02x",state->m_mux_data);
	162	printf("Warning: mux data W = %02x",m_mux_data);
161	163	}
162	164
163		static WRITE8_HANDLER( mcu_io_mux_w )
	165	WRITE8_MEMBER(rbmk_state::mcu_io_mux_w)
164	166	{
165		rbmk_state *state = space->machine().driver_data<rbmk_state>();
166		state->m_mux_data = ~data;
	167	m_mux_data = ~data;
167	168	}
168	169
169	170	static ADDRESS_MAP_START( rbmk_mcu_io, AS_IO, 8, rbmk_state )
170		AM_RANGE(0x0ff00, 0x0ffff) AM_READWRITE_LEGACY(rbmk_mcu_io_r, rbmk_mcu_io_w )
	171	AM_RANGE(0x0ff00, 0x0ffff) AM_READWRITE(rbmk_mcu_io_r, rbmk_mcu_io_w )
171	172
172		AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_WRITE_LEGACY(mcu_io_mux_w )
	173	AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_WRITE(mcu_io_mux_w )
173	174	ADDRESS_MAP_END
174	175
175	176	static INPUT_PORTS_START( rbmk )

src/mame/drivers/trvmadns.c

r14845	r14846
75	75	UINT8 *m_gfxram;
76	76	UINT8 *m_tileram;
77	77	int m_old_data;
	78	DECLARE_WRITE8_MEMBER(trvmadns_banking_w);
	79	DECLARE_WRITE8_MEMBER(trvmadns_gfxram_w);
	80	DECLARE_WRITE8_MEMBER(trvmadns_palette_w);
	81	DECLARE_WRITE8_MEMBER(w2);
	82	DECLARE_WRITE8_MEMBER(w3);
	83	DECLARE_WRITE8_MEMBER(trvmadns_tileram_w);
78	84	};
79	85
80	86
81		static WRITE8_HANDLER( trvmadns_banking_w )
	87	WRITE8_MEMBER(trvmadns_state::trvmadns_banking_w)
82	88	{
83		trvmadns_state *state = space->machine().driver_data<trvmadns_state>();
84	89
85	90	UINT8 *rom;
86	91	int address = 0;
r14845	r14846
91	96	}
92	97	else if((data & 0xf0) == 0x80 || (data & 0xf0) == 0x90)
93	98	{
94		rom = space->machine().region("user2")->base();
	99	rom = machine().region("user2")->base();
95	100
96	101	switch(data & 0xf)
97	102	{
r14845	r14846
107	112
108	113	address |= (data & 0x10) ? 0x10000 : 0;
109	114
110		memory_set_bankptr(space->machine(), "bank1", &rom[address]);
111		memory_set_bankptr(space->machine(), "bank2", &rom[address + 0x1000]);
	115	memory_set_bankptr(machine(), "bank1", &rom[address]);
	116	memory_set_bankptr(machine(), "bank2", &rom[address + 0x1000]);
112	117	}
113	118	else
114	119	{
115		if(data != state->m_old_data)
	120	if(data != m_old_data)
116	121	{
117		state->m_old_data = data;
	122	m_old_data = data;
118	123	logerror("port80 = %02X\n",data);
119	124	//logerror("port80 = %02X\n",data);
120	125	}
121	126
122		rom = space->machine().region("user1")->base();
	127	rom = machine().region("user1")->base();
123	128
124	129	/*
125	130	7
r14845	r14846
147	152
148	153	//      logerror("add = %X\n",address);
149	154
150		memory_set_bankptr(space->machine(), "bank1", &rom[address]);
	155	memory_set_bankptr(machine(), "bank1", &rom[address]);
151	156	}
152	157	}
153	158
154		static WRITE8_HANDLER( trvmadns_gfxram_w )
	159	WRITE8_MEMBER(trvmadns_state::trvmadns_gfxram_w)
155	160	{
156		trvmadns_state *state = space->machine().driver_data<trvmadns_state>();
157		state->m_gfxram[offset] = data;
158		gfx_element_mark_dirty(space->machine().gfx[0], offset/16);
	161	m_gfxram[offset] = data;
	162	gfx_element_mark_dirty(machine().gfx[0], offset/16);
159	163	}
160	164
161		static WRITE8_HANDLER( trvmadns_palette_w )
	165	WRITE8_MEMBER(trvmadns_state::trvmadns_palette_w)
162	166	{
163	167	int r,g,b,datax;
164		space->machine().generic.paletteram.u8[offset] = data;
	168	machine().generic.paletteram.u8[offset] = data;
165	169	offset>>=1;
166		datax=space->machine().generic.paletteram.u8[offset*2+1]+256*space->machine().generic.paletteram.u8[offset*2];
	170	datax=machine().generic.paletteram.u8[offset*2+1]+256*machine().generic.paletteram.u8[offset*2];
167	171
168	172	b = (((datax & 0x0007)>>0) | ((datax & 0x0200)>>6)) ^ 0xf;
169	173	r = (((datax & 0x0038)>>3) | ((datax & 0x0400)>>7)) ^ 0xf;
170	174	g = (((datax & 0x01c0)>>6) | ((datax & 0x0800)>>8)) ^ 0xf;
171	175
172		palette_set_color_rgb(space->machine(), offset, pal4bit(r), pal4bit(g), pal4bit(b));
	176	palette_set_color_rgb(machine(), offset, pal4bit(r), pal4bit(g), pal4bit(b));
173	177	}
174	178
175	179
176		static WRITE8_HANDLER( w2 )
	180	WRITE8_MEMBER(trvmadns_state::w2)
177	181	{
178	182	/*  static int old = -1;
179	183	if(data!=old)
r14845	r14846
181	185	*/
182	186	}
183	187
184		static WRITE8_HANDLER( w3 )
	188	WRITE8_MEMBER(trvmadns_state::w3)
185	189	{
186	190	/*  static int old = -1;
187	191	if(data!=old)
r14845	r14846
189	193	*/
190	194	}
191	195
192		static WRITE8_HANDLER( trvmadns_tileram_w )
	196	WRITE8_MEMBER(trvmadns_state::trvmadns_tileram_w)
193	197	{
194		trvmadns_state *state = space->machine().driver_data<trvmadns_state>();
195	198	if(offset==0)
196	199	{
197		if(cpu_get_previouspc(&space->device())==0x29e9)// || cpu_get_previouspc(&space->device())==0x1b3f) //29f5
	200	if(cpu_get_previouspc(&space.device())==0x29e9)// || cpu_get_previouspc(&space.device())==0x1b3f) //29f5
198	201	{
199		cputag_set_input_line(space->machine(), "maincpu", 0, HOLD_LINE);
	202	cputag_set_input_line(machine(), "maincpu", 0, HOLD_LINE);
200	203	}
201	204	//      else
202		//          logerror("%x \n", cpu_get_previouspc(&space->device()));
	205	//          logerror("%x \n", cpu_get_previouspc(&space.device()));
203	206
204	207	}
205	208
206		state->m_tileram[offset] = data;
207		state->m_bg_tilemap->mark_tile_dirty(offset >> 1);
	209	m_tileram[offset] = data;
	210	m_bg_tilemap->mark_tile_dirty(offset >> 1);
208	211	}
209	212
210	213
r14845	r14846
212	215	AM_RANGE(0x0000, 0x5fff) AM_ROM
213	216	AM_RANGE(0x6000, 0x6fff) AM_ROMBANK("bank1")
214	217	AM_RANGE(0x7000, 0x7fff) AM_ROMBANK("bank2")
215		AM_RANGE(0x6000, 0x7fff) AM_WRITE_LEGACY(trvmadns_gfxram_w) AM_BASE(m_gfxram)
	218	AM_RANGE(0x6000, 0x7fff) AM_WRITE(trvmadns_gfxram_w) AM_BASE(m_gfxram)
216	219	AM_RANGE(0x8000, 0x87ff) AM_RAM
217		AM_RANGE(0xa000, 0xa7ff) AM_RAM_WRITE_LEGACY(trvmadns_tileram_w) AM_BASE(m_tileram)
218		AM_RANGE(0xc000, 0xc01f) AM_RAM_WRITE_LEGACY(trvmadns_palette_w) AM_BASE_GENERIC(paletteram)
219		AM_RANGE(0xe000, 0xe000) AM_WRITE_LEGACY(w2)//NOP
220		AM_RANGE(0xe004, 0xe004) AM_WRITE_LEGACY(w3)//NOP
	220	AM_RANGE(0xa000, 0xa7ff) AM_RAM_WRITE(trvmadns_tileram_w) AM_BASE(m_tileram)
	221	AM_RANGE(0xc000, 0xc01f) AM_RAM_WRITE(trvmadns_palette_w) AM_BASE_GENERIC(paletteram)
	222	AM_RANGE(0xe000, 0xe000) AM_WRITE(w2)//NOP
	223	AM_RANGE(0xe004, 0xe004) AM_WRITE(w3)//NOP
221	224	ADDRESS_MAP_END
222	225
223	226	static ADDRESS_MAP_START( io_map, AS_IO, 8, trvmadns_state )
224	227	ADDRESS_MAP_GLOBAL_MASK(0xff)
225	228	AM_RANGE(0x00, 0x01) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
226	229	AM_RANGE(0x02, 0x02) AM_READ_PORT("IN0")
227		AM_RANGE(0x80, 0x80) AM_WRITE_LEGACY(trvmadns_banking_w)
	230	AM_RANGE(0x80, 0x80) AM_WRITE(trvmadns_banking_w)
228	231	ADDRESS_MAP_END
229	232
230	233	static INPUT_PORTS_START( trvmadns )

src/mame/drivers/albazg.c

r14845	r14846
61	61	UINT8 m_mux_data;
62	62	int m_bank;
63	63	UINT8 m_prot_lock;
	64	DECLARE_WRITE8_MEMBER(yumefuda_vram_w);
	65	DECLARE_WRITE8_MEMBER(yumefuda_cram_w);
	66	DECLARE_READ8_MEMBER(custom_ram_r);
	67	DECLARE_WRITE8_MEMBER(custom_ram_w);
	68	DECLARE_WRITE8_MEMBER(prot_lock_w);
64	69	};
65	70
66	71	static TILE_GET_INFO( y_get_bg_tile_info )
r14845	r14846
108	113	GFXDECODE_END
109	114
110	115
111		static WRITE8_HANDLER( yumefuda_vram_w )
	116	WRITE8_MEMBER(albazg_state::yumefuda_vram_w)
112	117	{
113		albazg_state *state = space->machine().driver_data<albazg_state>();
114		state->m_videoram[offset] = data;
115		state->m_bg_tilemap->mark_tile_dirty(offset);
	118	m_videoram[offset] = data;
	119	m_bg_tilemap->mark_tile_dirty(offset);
116	120	}
117	121
118		static WRITE8_HANDLER( yumefuda_cram_w )
	122	WRITE8_MEMBER(albazg_state::yumefuda_cram_w)
119	123	{
120		albazg_state *state = space->machine().driver_data<albazg_state>();
121		state->m_colorram[offset] = data;
122		state->m_bg_tilemap->mark_tile_dirty(offset);
	124	m_colorram[offset] = data;
	125	m_bg_tilemap->mark_tile_dirty(offset);
123	126	}
124	127
125	128	/*Custom RAM (Thrash Protection)*/
126		static READ8_HANDLER( custom_ram_r )
	129	READ8_MEMBER(albazg_state::custom_ram_r)
127	130	{
128		albazg_state *state = space->machine().driver_data<albazg_state>();
129		//  logerror("Custom RAM read at %02x PC = %x\n", offset + 0xaf80, cpu_get_pc(&space->device()));
130		return state->m_cus_ram[offset];// ^ 0x55;
	131	//  logerror("Custom RAM read at %02x PC = %x\n", offset + 0xaf80, cpu_get_pc(&space.device()));
	132	return m_cus_ram[offset];// ^ 0x55;
131	133	}
132	134
133		static WRITE8_HANDLER( custom_ram_w )
	135	WRITE8_MEMBER(albazg_state::custom_ram_w)
134	136	{
135		albazg_state *state = space->machine().driver_data<albazg_state>();
136		//  logerror("Custom RAM write at %02x : %02x PC = %x\n", offset + 0xaf80, data, cpu_get_pc(&space->device()));
137		if(state->m_prot_lock)
138		state->m_cus_ram[offset] = data;
	137	//  logerror("Custom RAM write at %02x : %02x PC = %x\n", offset + 0xaf80, data, cpu_get_pc(&space.device()));
	138	if(m_prot_lock)
	139	m_cus_ram[offset] = data;
139	140	}
140	141
141	142	/*this might be used as NVRAM commands btw*/
142		static WRITE8_HANDLER( prot_lock_w )
	143	WRITE8_MEMBER(albazg_state::prot_lock_w)
143	144	{
144		albazg_state *state = space->machine().driver_data<albazg_state>();
145		//  logerror("PC %04x Prot lock value written %02x\n", cpu_get_pc(&space->device()), data);
146		state->m_prot_lock = data;
	145	//  logerror("PC %04x Prot lock value written %02x\n", cpu_get_pc(&space.device()), data);
	146	m_prot_lock = data;
147	147	}
148	148
149	149	static READ8_DEVICE_HANDLER( mux_r )
r14845	r14846
230	230	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, albazg_state )
231	231	AM_RANGE(0x0000, 0x7fff) AM_ROM
232	232	AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("bank1")
233		AM_RANGE(0xa7fc, 0xa7fc) AM_WRITE_LEGACY(prot_lock_w)
	233	AM_RANGE(0xa7fc, 0xa7fc) AM_WRITE(prot_lock_w)
234	234	AM_RANGE(0xa7ff, 0xa7ff) AM_WRITE_PORT("EEPROMOUT")
235		AM_RANGE(0xaf80, 0xafff) AM_READWRITE_LEGACY(custom_ram_r, custom_ram_w) AM_BASE(m_cus_ram)
	235	AM_RANGE(0xaf80, 0xafff) AM_READWRITE(custom_ram_r, custom_ram_w) AM_BASE(m_cus_ram)
236	236	AM_RANGE(0xb000, 0xb07f) AM_RAM_WRITE_LEGACY(paletteram_xRRRRRGGGGGBBBBB_split1_w) AM_BASE_GENERIC(paletteram)
237	237	AM_RANGE(0xb080, 0xb0ff) AM_RAM_WRITE_LEGACY(paletteram_xRRRRRGGGGGBBBBB_split2_w) AM_BASE_GENERIC(paletteram2)
238		AM_RANGE(0xc000, 0xc3ff) AM_RAM_WRITE_LEGACY(yumefuda_vram_w) AM_BASE(m_videoram)
239		AM_RANGE(0xd000, 0xd3ff) AM_RAM_WRITE_LEGACY(yumefuda_cram_w) AM_BASE(m_colorram)
	238	AM_RANGE(0xc000, 0xc3ff) AM_RAM_WRITE(yumefuda_vram_w) AM_BASE(m_videoram)
	239	AM_RANGE(0xd000, 0xd3ff) AM_RAM_WRITE(yumefuda_cram_w) AM_BASE(m_colorram)
240	240	AM_RANGE(0xe000, 0xffff) AM_RAM
241	241	ADDRESS_MAP_END
242	242

src/mame/drivers/bingoc.c

r14845	r14846
41	41	: driver_device(mconfig, type, tag) { }
42	42
43	43	UINT8 m_x;
	44	DECLARE_READ16_MEMBER(bingoc_rand_r);
	45	DECLARE_READ8_MEMBER(sound_test_r);
	46	DECLARE_WRITE16_MEMBER(main_sound_latch_w);
44	47	};
45	48
46	49
r14845	r14846
56	59	return 0;
57	60	}
58	61
59		static READ16_HANDLER( bingoc_rand_r )
	62	READ16_MEMBER(bingoc_state::bingoc_rand_r)
60	63	{
61	64	return 0xffff;
62	65	}
r14845	r14846
68	71	0x80-0x85 ym2151 bgm
69	72	0x90-0x9b ym2151 sfx
70	73	*/
71		static READ8_HANDLER( sound_test_r )
	74	READ8_MEMBER(bingoc_state::sound_test_r)
72	75	{
73		bingoc_state *state = space->machine().driver_data<bingoc_state>();
74	76
75		if(space->machine().input().code_pressed_once(KEYCODE_Z))
76		state->m_x++;
	77	if(machine().input().code_pressed_once(KEYCODE_Z))
	78	m_x++;
77	79
78		if(space->machine().input().code_pressed_once(KEYCODE_X))
79		state->m_x--;
	80	if(machine().input().code_pressed_once(KEYCODE_X))
	81	m_x--;
80	82
81		if(space->machine().input().code_pressed_once(KEYCODE_A))
	83	if(machine().input().code_pressed_once(KEYCODE_A))
82	84	return 0xff;
83	85
84		popmessage("%02x",state->m_x);
85		return state->m_x;
	86	popmessage("%02x",m_x);
	87	return m_x;
86	88	}
87	89	#else
88		static WRITE16_HANDLER( main_sound_latch_w )
	90	WRITE16_MEMBER(bingoc_state::main_sound_latch_w)
89	91	{
90	92	soundlatch_w(space,0,data&0xff);
91		cputag_set_input_line(space->machine(), "soundcpu", INPUT_LINE_NMI, PULSE_LINE);
	93	cputag_set_input_line(machine(), "soundcpu", INPUT_LINE_NMI, PULSE_LINE);
92	94	}
93	95	#endif
94	96
r14845	r14846
106	108
107	109	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 16, bingoc_state )
108	110	AM_RANGE(0x000000, 0x03ffff) AM_ROM
109		AM_RANGE(0x100000, 0x10007f) AM_READ_LEGACY(bingoc_rand_r) //comms? lamps?
110		AM_RANGE(0x180000, 0x18007f) AM_READ_LEGACY(bingoc_rand_r) //comms? lamps?
	111	AM_RANGE(0x100000, 0x10007f) AM_READ(bingoc_rand_r) //comms? lamps?
	112	AM_RANGE(0x180000, 0x18007f) AM_READ(bingoc_rand_r) //comms? lamps?
111	113	#if !SOUND_TEST
112		AM_RANGE(0x180010, 0x180011) AM_WRITE_LEGACY(main_sound_latch_w) //WRONG there...
	114	AM_RANGE(0x180010, 0x180011) AM_WRITE(main_sound_latch_w) //WRONG there...
113	115	#endif
114	116	AM_RANGE(0xff8000, 0xffffff) AM_RAM
115	117	ADDRESS_MAP_END
r14845	r14846
127	129	#if !SOUND_TEST
128	130	AM_RANGE(0xc0, 0xc0) AM_READ_LEGACY(soundlatch_r) //soundlatch
129	131	#else
130		AM_RANGE(0xc0, 0xc0) AM_READ_LEGACY(sound_test_r)
	132	AM_RANGE(0xc0, 0xc0) AM_READ(sound_test_r)
131	133	#endif
132	134	ADDRESS_MAP_END
133	135

src/mame/drivers/sstrangr.c

r14845	r14846
22	22	UINT8 *m_ram;
23	23	UINT8 m_flip_screen;
24	24	UINT8 *m_proms;
	25	DECLARE_WRITE8_MEMBER(port_w);
25	26	};
26	27
27	28
r14845	r14846
129	130	}
130	131
131	132
132		static WRITE8_HANDLER( port_w )
	133	WRITE8_MEMBER(sstrangr_state::port_w)
133	134	{
134		sstrangr_state *state = space->machine().driver_data<sstrangr_state>();
135	135
136		state->m_flip_screen = data & 0x20;
	136	m_flip_screen = data & 0x20;
137	137	}
138	138
139	139
r14845	r14846
149	149	static ADDRESS_MAP_START( sstrangr_io_map, AS_IO, 8, sstrangr_state )
150	150	AM_RANGE(0x41, 0x41) AM_READ_PORT("DSW")
151	151	AM_RANGE(0x42, 0x42) AM_READ_PORT("INPUTS")
152		AM_RANGE(0x44, 0x44) AM_READ_PORT("EXT") AM_WRITE_LEGACY(port_w)
	152	AM_RANGE(0x44, 0x44) AM_READ_PORT("EXT") AM_WRITE(port_w)
153	153	ADDRESS_MAP_END
154	154
155	155

src/mame/drivers/backfire.c

r14845	r14846
52	52	UINT16    m_pf2_rowscroll[0x0800/2];
53	53	UINT16    m_pf3_rowscroll[0x0800/2];
54	54	UINT16    m_pf4_rowscroll[0x0800/2];
	55	DECLARE_READ32_MEMBER(backfire_control2_r);
	56	DECLARE_READ32_MEMBER(backfire_control3_r);
	57	DECLARE_WRITE32_MEMBER(backfire_nonbuffered_palette_w);
	58	DECLARE_READ32_MEMBER(backfire_pf1_rowscroll_r);
	59	DECLARE_READ32_MEMBER(backfire_pf2_rowscroll_r);
	60	DECLARE_READ32_MEMBER(backfire_pf3_rowscroll_r);
	61	DECLARE_READ32_MEMBER(backfire_pf4_rowscroll_r);
	62	DECLARE_WRITE32_MEMBER(backfire_pf1_rowscroll_w);
	63	DECLARE_WRITE32_MEMBER(backfire_pf2_rowscroll_w);
	64	DECLARE_WRITE32_MEMBER(backfire_pf3_rowscroll_w);
	65	DECLARE_WRITE32_MEMBER(backfire_pf4_rowscroll_w);
	66	DECLARE_READ32_MEMBER(backfire_spriteram1_r);
	67	DECLARE_WRITE32_MEMBER(backfire_spriteram1_w);
	68	DECLARE_READ32_MEMBER(backfire_spriteram2_r);
	69	DECLARE_WRITE32_MEMBER(backfire_spriteram2_w);
	70	DECLARE_READ32_MEMBER(backfire_speedup_r);
55	71	};
56	72
57	73	//UINT32 *backfire_180010, *backfire_188010;
r14845	r14846
160	176	| ((input_port_read(device->machine(), "IN3") & 0x40) << 16)) ^ (backfire_screen << 26) ;
161	177	}
162	178
163		static READ32_HANDLER( backfire_control2_r )
	179	READ32_MEMBER(backfire_state::backfire_control2_r)
164	180	{
165		backfire_state *state = space->machine().driver_data<backfire_state>();
166	181
167		//  logerror("%08x:Read eprom %08x (%08x)\n", cpu_get_pc(&space->device()), offset << 1, mem_mask);
168		return (state->m_eeprom->read_bit() << 24) | input_port_read(space->machine(), "IN1") | (input_port_read(space->machine(), "IN1") << 16);
	182	//  logerror("%08x:Read eprom %08x (%08x)\n", cpu_get_pc(&space.device()), offset << 1, mem_mask);
	183	return (m_eeprom->read_bit() << 24) | input_port_read(machine(), "IN1") | (input_port_read(machine(), "IN1") << 16);
169	184	}
170	185
171	186	#ifdef UNUSED_FUNCTION
172		static READ32_HANDLER(backfire_control3_r)
	187	READ32_MEMBER(backfire_state::backfire_control3_r)
173	188	{
174		backfire_state *state = space->machine().driver_data<backfire_state>();
175	189
176		//  logerror("%08x:Read eprom %08x (%08x)\n", cpu_get_pc(&space->device()), offset << 1, mem_mask);
177		return (state->m_eeprom->read_bit() << 24) | input_port_read(space->machine(), "IN2") | (input_port_read(space->machine(), "IN2") << 16);
	190	//  logerror("%08x:Read eprom %08x (%08x)\n", cpu_get_pc(&space.device()), offset << 1, mem_mask);
	191	return (m_eeprom->read_bit() << 24) | input_port_read(machine(), "IN2") | (input_port_read(machine(), "IN2") << 16);
178	192	}
179	193	#endif
180	194
r14845	r14846
192	206	}
193	207
194	208
195		static WRITE32_HANDLER(backfire_nonbuffered_palette_w)
	209	WRITE32_MEMBER(backfire_state::backfire_nonbuffered_palette_w)
196	210	{
197		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
198		palette_set_color_rgb(space->machine(),offset,pal5bit(space->machine().generic.paletteram.u32[offset] >> 0),pal5bit(space->machine().generic.paletteram.u32[offset] >> 5),pal5bit(space->machine().generic.paletteram.u32[offset] >> 10));
	211	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
	212	palette_set_color_rgb(machine(),offset,pal5bit(machine().generic.paletteram.u32[offset] >> 0),pal5bit(machine().generic.paletteram.u32[offset] >> 5),pal5bit(machine().generic.paletteram.u32[offset] >> 10));
199	213	}
200	214
201	215	/* map 32-bit writes to 16-bit */
202	216
203		static READ32_HANDLER( backfire_pf1_rowscroll_r ) { backfire_state *state = space->machine().driver_data<backfire_state>(); return state->m_pf1_rowscroll[offset] ^ 0xffff0000; }
204		static READ32_HANDLER( backfire_pf2_rowscroll_r ) { backfire_state *state = space->machine().driver_data<backfire_state>(); return state->m_pf2_rowscroll[offset] ^ 0xffff0000; }
205		static READ32_HANDLER( backfire_pf3_rowscroll_r ) { backfire_state *state = space->machine().driver_data<backfire_state>(); return state->m_pf3_rowscroll[offset] ^ 0xffff0000; }
206		static READ32_HANDLER( backfire_pf4_rowscroll_r ) { backfire_state *state = space->machine().driver_data<backfire_state>(); return state->m_pf4_rowscroll[offset] ^ 0xffff0000; }
207		static WRITE32_HANDLER( backfire_pf1_rowscroll_w ) { backfire_state *state = space->machine().driver_data<backfire_state>(); data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&state->m_pf1_rowscroll[offset]); }
208		static WRITE32_HANDLER( backfire_pf2_rowscroll_w ) { backfire_state *state = space->machine().driver_data<backfire_state>(); data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&state->m_pf2_rowscroll[offset]); }
209		static WRITE32_HANDLER( backfire_pf3_rowscroll_w ) { backfire_state *state = space->machine().driver_data<backfire_state>(); data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&state->m_pf3_rowscroll[offset]); }
210		static WRITE32_HANDLER( backfire_pf4_rowscroll_w ) { backfire_state *state = space->machine().driver_data<backfire_state>(); data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&state->m_pf4_rowscroll[offset]); }
	217	READ32_MEMBER(backfire_state::backfire_pf1_rowscroll_r){ return m_pf1_rowscroll[offset] ^ 0xffff0000; }
	218	READ32_MEMBER(backfire_state::backfire_pf2_rowscroll_r){ return m_pf2_rowscroll[offset] ^ 0xffff0000; }
	219	READ32_MEMBER(backfire_state::backfire_pf3_rowscroll_r){ return m_pf3_rowscroll[offset] ^ 0xffff0000; }
	220	READ32_MEMBER(backfire_state::backfire_pf4_rowscroll_r){ return m_pf4_rowscroll[offset] ^ 0xffff0000; }
	221	WRITE32_MEMBER(backfire_state::backfire_pf1_rowscroll_w){ data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&m_pf1_rowscroll[offset]); }
	222	WRITE32_MEMBER(backfire_state::backfire_pf2_rowscroll_w){ data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&m_pf2_rowscroll[offset]); }
	223	WRITE32_MEMBER(backfire_state::backfire_pf3_rowscroll_w){ data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&m_pf3_rowscroll[offset]); }
	224	WRITE32_MEMBER(backfire_state::backfire_pf4_rowscroll_w){ data &= 0x0000ffff; mem_mask &= 0x0000ffff; COMBINE_DATA(&m_pf4_rowscroll[offset]); }
211	225
212	226
213	227	#ifdef UNUSED_FUNCTION
r14845	r14846
228	242	#endif
229	243
230	244
231		static READ32_HANDLER( backfire_spriteram1_r )
	245	READ32_MEMBER(backfire_state::backfire_spriteram1_r)
232	246	{
233		backfire_state *state = space->machine().driver_data<backfire_state>();
234		return state->m_spriteram_1[offset] ^ 0xffff0000;
	247	return m_spriteram_1[offset] ^ 0xffff0000;
235	248	}
236	249
237		static WRITE32_HANDLER( backfire_spriteram1_w )
	250	WRITE32_MEMBER(backfire_state::backfire_spriteram1_w)
238	251	{
239		backfire_state *state = space->machine().driver_data<backfire_state>();
240	252	data &= 0x0000ffff;
241	253	mem_mask &= 0x0000ffff;
242	254
243		COMBINE_DATA(&state->m_spriteram_1[offset]);
	255	COMBINE_DATA(&m_spriteram_1[offset]);
244	256	}
245	257
246		static READ32_HANDLER( backfire_spriteram2_r )
	258	READ32_MEMBER(backfire_state::backfire_spriteram2_r)
247	259	{
248		backfire_state *state = space->machine().driver_data<backfire_state>();
249		return state->m_spriteram_2[offset] ^ 0xffff0000;
	260	return m_spriteram_2[offset] ^ 0xffff0000;
250	261	}
251	262
252		static WRITE32_HANDLER( backfire_spriteram2_w )
	263	WRITE32_MEMBER(backfire_state::backfire_spriteram2_w)
253	264	{
254		backfire_state *state = space->machine().driver_data<backfire_state>();
255	265	data &= 0x0000ffff;
256	266	mem_mask &= 0x0000ffff;
257	267
258		COMBINE_DATA(&state->m_spriteram_2[offset]);
	268	COMBINE_DATA(&m_spriteram_2[offset]);
259	269	}
260	270
261	271
r14845	r14846
265	275	AM_RANGE(0x100000, 0x10001f) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf_control_dword_r, deco16ic_pf_control_dword_w)
266	276	AM_RANGE(0x110000, 0x111fff) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf1_data_dword_r, deco16ic_pf1_data_dword_w)
267	277	AM_RANGE(0x114000, 0x115fff) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf2_data_dword_r, deco16ic_pf2_data_dword_w)
268		AM_RANGE(0x120000, 0x120fff) AM_READWRITE_LEGACY(backfire_pf1_rowscroll_r, backfire_pf1_rowscroll_w)
269		AM_RANGE(0x124000, 0x124fff) AM_READWRITE_LEGACY(backfire_pf2_rowscroll_r, backfire_pf2_rowscroll_w)
	278	AM_RANGE(0x120000, 0x120fff) AM_READWRITE(backfire_pf1_rowscroll_r, backfire_pf1_rowscroll_w)
	279	AM_RANGE(0x124000, 0x124fff) AM_READWRITE(backfire_pf2_rowscroll_r, backfire_pf2_rowscroll_w)
270	280	AM_RANGE(0x130000, 0x13001f) AM_DEVREADWRITE_LEGACY("tilegen2", deco16ic_pf_control_dword_r, deco16ic_pf_control_dword_w)
271	281	AM_RANGE(0x140000, 0x141fff) AM_DEVREADWRITE_LEGACY("tilegen2", deco16ic_pf1_data_dword_r, deco16ic_pf1_data_dword_w)
272	282	AM_RANGE(0x144000, 0x145fff) AM_DEVREADWRITE_LEGACY("tilegen2", deco16ic_pf2_data_dword_r, deco16ic_pf2_data_dword_w)
273		AM_RANGE(0x150000, 0x150fff) AM_READWRITE_LEGACY(backfire_pf3_rowscroll_r, backfire_pf3_rowscroll_w)
274		AM_RANGE(0x154000, 0x154fff) AM_READWRITE_LEGACY(backfire_pf4_rowscroll_r, backfire_pf4_rowscroll_w)
275		AM_RANGE(0x160000, 0x161fff) AM_WRITE_LEGACY(backfire_nonbuffered_palette_w) AM_BASE_GENERIC(paletteram)
	283	AM_RANGE(0x150000, 0x150fff) AM_READWRITE(backfire_pf3_rowscroll_r, backfire_pf3_rowscroll_w)
	284	AM_RANGE(0x154000, 0x154fff) AM_READWRITE(backfire_pf4_rowscroll_r, backfire_pf4_rowscroll_w)
	285	AM_RANGE(0x160000, 0x161fff) AM_WRITE(backfire_nonbuffered_palette_w) AM_BASE_GENERIC(paletteram)
276	286	AM_RANGE(0x170000, 0x177fff) AM_RAM AM_BASE(m_mainram)// main ram
277	287
278	288	//  AM_RANGE(0x180010, 0x180013) AM_RAM AM_BASE_LEGACY(&backfire_180010) // always 180010 ?
279	289	//  AM_RANGE(0x188010, 0x188013) AM_RAM AM_BASE_LEGACY(&backfire_188010) // always 188010 ?
280	290
281		AM_RANGE(0x184000, 0x185fff) AM_READWRITE_LEGACY(backfire_spriteram1_r, backfire_spriteram1_w)
282		AM_RANGE(0x18c000, 0x18dfff) AM_READWRITE_LEGACY(backfire_spriteram2_r, backfire_spriteram2_w)
	291	AM_RANGE(0x184000, 0x185fff) AM_READWRITE(backfire_spriteram1_r, backfire_spriteram1_w)
	292	AM_RANGE(0x18c000, 0x18dfff) AM_READWRITE(backfire_spriteram2_r, backfire_spriteram2_w)
283	293	AM_RANGE(0x190000, 0x190003) AM_DEVREAD_LEGACY("eeprom", backfire_eeprom_r)
284		AM_RANGE(0x194000, 0x194003) AM_READ_LEGACY(backfire_control2_r)
	294	AM_RANGE(0x194000, 0x194003) AM_READ(backfire_control2_r)
285	295	AM_RANGE(0x1a4000, 0x1a4003) AM_DEVWRITE_LEGACY("eeprom", backfire_eeprom_w)
286	296
287	297	AM_RANGE(0x1a8000, 0x1a8003) AM_RAM AM_BASE(m_left_priority)
r14845	r14846
675	685	auto_free(machine, buf1);
676	686	}
677	687
678		static READ32_HANDLER( backfire_speedup_r )
	688	READ32_MEMBER(backfire_state::backfire_speedup_r)
679	689	{
680		backfire_state *state = space->machine().driver_data<backfire_state>();
681	690
682		//mame_printf_debug( "%08x\n",cpu_get_pc(&space->device()));
	691	//mame_printf_debug( "%08x\n",cpu_get_pc(&space.device()));
683	692
684		if (cpu_get_pc(&space->device() )== 0xce44)  device_spin_until_time(&space->device(), attotime::from_usec(400)); // backfire
685		if (cpu_get_pc(&space->device()) == 0xcee4)  device_spin_until_time(&space->device(), attotime::from_usec(400)); // backfirea
	693	if (cpu_get_pc(&space.device() )== 0xce44)  device_spin_until_time(&space.device(), attotime::from_usec(400)); // backfire
	694	if (cpu_get_pc(&space.device()) == 0xcee4)  device_spin_until_time(&space.device(), attotime::from_usec(400)); // backfirea
686	695
687		return state->m_mainram[0x18/4];
	696	return m_mainram[0x18/4];
688	697	}
689	698
690	699
r14845	r14846
695	704	deco156_decrypt(machine);
696	705	machine.device("maincpu")->set_clock_scale(4.0f); /* core timings aren't accurate */
697	706	descramble_sound(machine);
698		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x0170018, 0x017001b, FUNC(backfire_speedup_r) );
	707	backfire_state *state = machine.driver_data<backfire_state>();
	708	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x0170018, 0x017001b, read32_delegate(FUNC(backfire_state::backfire_speedup_r), state));
699	709	}
700	710
701	711	GAME( 1995, backfire,  0,        backfire,   backfire, backfire, ROT0, "Data East Corporation", "Backfire! (set 1)", GAME_SUPPORTS_SAVE )

src/mame/drivers/cubeqst.c

r14845	r14846
38	38	UINT8 m_reset_latch;
39	39	required_device<simutrek_special_device> m_laserdisc;
40	40	rgb_t *m_colormap;
	41	DECLARE_WRITE16_MEMBER(palette_w);
	42	DECLARE_READ16_MEMBER(line_r);
	43	DECLARE_WRITE16_MEMBER(laserdisc_w);
	44	DECLARE_READ16_MEMBER(laserdisc_r);
	45	DECLARE_WRITE16_MEMBER(ldaud_w);
	46	DECLARE_WRITE16_MEMBER(control_w);
	47	DECLARE_WRITE16_MEMBER(reset_w);
	48	DECLARE_WRITE16_MEMBER(io_w);
	49	DECLARE_READ16_MEMBER(io_r);
	50	DECLARE_READ16_MEMBER(chop_r);
	51	DECLARE_READ16_MEMBER(read_rotram);
	52	DECLARE_WRITE16_MEMBER(write_rotram);
	53	DECLARE_READ16_MEMBER(read_sndram);
	54	DECLARE_WRITE16_MEMBER(write_sndram);
41	55	};
42	56
43	57
r14845	r14846
87	101	}
88	102	}
89	103
90		static WRITE16_HANDLER( palette_w )
	104	WRITE16_MEMBER(cubeqst_state::palette_w)
91	105	{
92		space->machine().primary_screen->update_now();
93		COMBINE_DATA(&space->machine().generic.paletteram.u16[offset]);
	106	machine().primary_screen->update_now();
	107	COMBINE_DATA(&machine().generic.paletteram.u16[offset]);
94	108	}
95	109
96	110	/* TODO: This is a simplified version of what actually happens */
r14845	r14846
170	184	return 0;
171	185	}
172	186
173		static READ16_HANDLER( line_r )
	187	READ16_MEMBER(cubeqst_state::line_r)
174	188	{
175	189	/* I think this is unusued */
176		return space->machine().primary_screen->vpos();
	190	return machine().primary_screen->vpos();
177	191	}
178	192
179	193	static INTERRUPT_GEN( vblank )
r14845	r14846
194	208	*
195	209	*************************************/
196	210
197		static WRITE16_HANDLER( laserdisc_w )
	211	WRITE16_MEMBER(cubeqst_state::laserdisc_w)
198	212	{
199		cubeqst_state *state = space->machine().driver_data<cubeqst_state>();
200		state->m_laserdisc->data_w(data & 0xff);
	213	m_laserdisc->data_w(data & 0xff);
201	214	}
202	215
203	216	/*
204	217	D0: Command acknowledge
205	218	D1: Seek status (0 = searching, 1 = ready)
206	219	*/
207		static READ16_HANDLER( laserdisc_r )
	220	READ16_MEMBER(cubeqst_state::laserdisc_r)
208	221	{
209		cubeqst_state *state = space->machine().driver_data<cubeqst_state>();
210		int ldp_command_flag = (state->m_laserdisc->ready_r() == ASSERT_LINE) ? 0 : 1;
211		int ldp_seek_status = (state->m_laserdisc->status_r() == ASSERT_LINE) ? 1 : 0;
	222	int ldp_command_flag = (m_laserdisc->ready_r() == ASSERT_LINE) ? 0 : 1;
	223	int ldp_seek_status = (m_laserdisc->status_r() == ASSERT_LINE) ? 1 : 0;
212	224
213	225	return (ldp_seek_status << 1) | ldp_command_flag;
214	226	}
215	227
216	228
217	229	/* LDP audio squelch control */
218		static WRITE16_HANDLER( ldaud_w )
	230	WRITE16_MEMBER(cubeqst_state::ldaud_w)
219	231	{
220		cubeqst_state *state = space->machine().driver_data<cubeqst_state>();
221		state->m_laserdisc->set_external_audio_squelch(data & 1 ? ASSERT_LINE : CLEAR_LINE);
	232	m_laserdisc->set_external_audio_squelch(data & 1 ? ASSERT_LINE : CLEAR_LINE);
222	233	}
223	234
224	235	/*
r14845	r14846
231	242
232	243	Note: Can only be written during VBLANK (as with palette RAM)
233	244	*/
234		static WRITE16_HANDLER( control_w )
	245	WRITE16_MEMBER(cubeqst_state::control_w)
235	246	{
236		cubeqst_state *state = space->machine().driver_data<cubeqst_state>();
237		state->m_laserdisc->video_enable(data & 1);
	247	m_laserdisc->video_enable(data & 1);
238	248	}
239	249
240	250
r14845	r14846
268	278	D1: /Sound
269	279	D2: /Disk
270	280	*/
271		static WRITE16_HANDLER( reset_w )
	281	WRITE16_MEMBER(cubeqst_state::reset_w)
272	282	{
273		cubeqst_state *state = space->machine().driver_data<cubeqst_state>();
274		cputag_set_input_line(space->machine(), "rotate_cpu", INPUT_LINE_RESET, data & 1 ? CLEAR_LINE : ASSERT_LINE);
275		cputag_set_input_line(space->machine(), "line_cpu", INPUT_LINE_RESET, data & 1 ? CLEAR_LINE : ASSERT_LINE);
276		cputag_set_input_line(space->machine(), "sound_cpu", INPUT_LINE_RESET, data & 2 ? CLEAR_LINE : ASSERT_LINE);
	283	cputag_set_input_line(machine(), "rotate_cpu", INPUT_LINE_RESET, data & 1 ? CLEAR_LINE : ASSERT_LINE);
	284	cputag_set_input_line(machine(), "line_cpu", INPUT_LINE_RESET, data & 1 ? CLEAR_LINE : ASSERT_LINE);
	285	cputag_set_input_line(machine(), "sound_cpu", INPUT_LINE_RESET, data & 2 ? CLEAR_LINE : ASSERT_LINE);
277	286
278	287	/* Swap stack and pointer RAM banks on rising edge of display reset */
279		if (!BIT(state->m_reset_latch, 0) && BIT(data, 0))
280		swap_linecpu_banks(space->machine());
	288	if (!BIT(m_reset_latch, 0) && BIT(data, 0))
	289	swap_linecpu_banks(machine());
281	290
282	291	if (!BIT(data, 2))
283		state->m_laserdisc->reset();
	292	m_laserdisc->reset();
284	293
285		state->m_reset_latch = data & 0xff;
	294	m_reset_latch = data & 0xff;
286	295	}
287	296
288	297
r14845	r14846
292	301	*
293	302	*************************************/
294	303
295		static WRITE16_HANDLER( io_w )
	304	WRITE16_MEMBER(cubeqst_state::io_w)
296	305	{
297		cubeqst_state *state = space->machine().driver_data<cubeqst_state>();
298	306	/*
299	307	0: Spare lamp
300	308	1: Spare driver
r14845	r14846
307	315	*/
308	316
309	317	/* TODO: On rising edge of Q7, status LED latch is written */
310		if ( !BIT(state->m_io_latch, 7) && BIT(data, 7) )
	318	if ( !BIT(m_io_latch, 7) && BIT(data, 7) )
311	319	{
312	320	/*
313	321	0: Battery failure
r14845	r14846
316	324	*/
317	325	}
318	326
319		state->m_io_latch = data;
	327	m_io_latch = data;
320	328	}
321	329
322		static READ16_HANDLER( io_r )
	330	READ16_MEMBER(cubeqst_state::io_r)
323	331	{
324		cubeqst_state *state = space->machine().driver_data<cubeqst_state>();
325		UINT16 port_data = input_port_read(space->machine(), "IO");
	332	UINT16 port_data = input_port_read(machine(), "IO");
326	333
327	334	/*
328	335	Certain bits depend on Q7 of the IO latch:
r14845	r14846
333	340	10: Spare  / Trackball V data
334	341	*/
335	342
336		if ( !BIT(state->m_io_latch, 7) )
	343	if ( !BIT(m_io_latch, 7) )
337	344	return port_data;
338	345	else
339	346	/* Return zeroes for the trackball signals for now */
r14845	r14846
341	348	}
342	349
343	350	/* Trackball ('CHOP') */
344		static READ16_HANDLER( chop_r )
	351	READ16_MEMBER(cubeqst_state::chop_r)
345	352	{
346		return (input_port_read(space->machine(), "TRACK_X") << 8) | input_port_read(space->machine(), "TRACK_Y");
	353	return (input_port_read(machine(), "TRACK_X") << 8) | input_port_read(machine(), "TRACK_Y");
347	354	}
348	355
349	356
r14845	r14846
382	389	*
383	390	*************************************/
384	391
385		static READ16_HANDLER( read_rotram )
	392	READ16_MEMBER(cubeqst_state::read_rotram)
386	393	{
387		return cubeqcpu_rotram_r(space->machine().device("rotate_cpu"), offset, mem_mask);
	394	return cubeqcpu_rotram_r(machine().device("rotate_cpu"), offset, mem_mask);
388	395	}
389	396
390		static WRITE16_HANDLER( write_rotram )
	397	WRITE16_MEMBER(cubeqst_state::write_rotram)
391	398	{
392		cubeqcpu_rotram_w(space->machine().device("rotate_cpu"), offset, data, mem_mask);
	399	cubeqcpu_rotram_w(machine().device("rotate_cpu"), offset, data, mem_mask);
393	400	}
394	401
395		static READ16_HANDLER( read_sndram )
	402	READ16_MEMBER(cubeqst_state::read_sndram)
396	403	{
397		return cubeqcpu_sndram_r(space->machine().device("sound_cpu"), offset, mem_mask);
	404	return cubeqcpu_sndram_r(machine().device("sound_cpu"), offset, mem_mask);
398	405	}
399	406
400		static WRITE16_HANDLER( write_sndram )
	407	WRITE16_MEMBER(cubeqst_state::write_sndram)
401	408	{
402		cubeqcpu_sndram_w(space->machine().device("sound_cpu"), offset, data, mem_mask);
	409	cubeqcpu_sndram_w(machine().device("sound_cpu"), offset, data, mem_mask);
403	410	}
404	411
405	412	static ADDRESS_MAP_START( m68k_program_map, AS_PROGRAM, 16, cubeqst_state )
406	413	ADDRESS_MAP_GLOBAL_MASK(0x03ffff)
407	414	AM_RANGE(0x000000, 0x01ffff) AM_ROM
408		AM_RANGE(0x020000, 0x027fff) AM_READWRITE_LEGACY(read_rotram, write_rotram)
409		AM_RANGE(0x028000, 0x028fff) AM_READWRITE_LEGACY(read_sndram, write_sndram)
410		AM_RANGE(0x038000, 0x038001) AM_READWRITE_LEGACY(io_r, io_w)
411		AM_RANGE(0x038002, 0x038003) AM_READWRITE_LEGACY(chop_r, ldaud_w)
412		AM_RANGE(0x038008, 0x038009) AM_READWRITE_LEGACY(line_r, reset_w)
413		AM_RANGE(0x03800e, 0x03800f) AM_READWRITE_LEGACY(laserdisc_r, laserdisc_w)
414		AM_RANGE(0x03c800, 0x03c9ff) AM_RAM_WRITE_LEGACY(palette_w) AM_BASE_GENERIC(paletteram)
415		AM_RANGE(0x03cc00, 0x03cc01) AM_WRITE_LEGACY(control_w)
	415	AM_RANGE(0x020000, 0x027fff) AM_READWRITE(read_rotram, write_rotram)
	416	AM_RANGE(0x028000, 0x028fff) AM_READWRITE(read_sndram, write_sndram)
	417	AM_RANGE(0x038000, 0x038001) AM_READWRITE(io_r, io_w)
	418	AM_RANGE(0x038002, 0x038003) AM_READWRITE(chop_r, ldaud_w)
	419	AM_RANGE(0x038008, 0x038009) AM_READWRITE(line_r, reset_w)
	420	AM_RANGE(0x03800e, 0x03800f) AM_READWRITE(laserdisc_r, laserdisc_w)
	421	AM_RANGE(0x03c800, 0x03c9ff) AM_RAM_WRITE(palette_w) AM_BASE_GENERIC(paletteram)
	422	AM_RANGE(0x03cc00, 0x03cc01) AM_WRITE(control_w)
416	423	AM_RANGE(0x03e000, 0x03efff) AM_RAM AM_SHARE("nvram")
417	424	AM_RANGE(0x03f000, 0x03ffff) AM_RAM
418	425	ADDRESS_MAP_END

src/mame/drivers/astrocorp.c

r14845	r14846
51	51	bitmap_ind16 m_bitmap;
52	52	UINT16     m_screen_enable;
53	53	UINT16     m_draw_sprites;
	54	DECLARE_WRITE16_MEMBER(astrocorp_draw_sprites_w);
	55	DECLARE_WRITE16_MEMBER(astrocorp_eeprom_w);
	56	DECLARE_WRITE16_MEMBER(showhand_outputs_w);
	57	DECLARE_WRITE16_MEMBER(skilldrp_outputs_w);
	58	DECLARE_WRITE16_MEMBER(astrocorp_screen_enable_w);
	59	DECLARE_READ16_MEMBER(astrocorp_unk_r);
	60	DECLARE_WRITE16_MEMBER(astrocorp_palette_w);
54	61	};
55	62
56	63	/***************************************************************************
r14845	r14846
155	162	Memory Maps
156	163	***************************************************************************/
157	164
158		static WRITE16_HANDLER( astrocorp_draw_sprites_w )
	165	WRITE16_MEMBER(astrocorp_state::astrocorp_draw_sprites_w)
159	166	{
160		astrocorp_state *state = space->machine().driver_data<astrocorp_state>();
161	167
162		UINT16 old = state->m_draw_sprites;
163		UINT16 now = COMBINE_DATA(&state->m_draw_sprites);
	168	UINT16 old = m_draw_sprites;
	169	UINT16 now = COMBINE_DATA(&m_draw_sprites);
164	170
165	171	if (!old && now)
166		draw_sprites(space->machine(), state->m_bitmap, space->machine().primary_screen->visible_area());
	172	draw_sprites(machine(), m_bitmap, machine().primary_screen->visible_area());
167	173	}
168	174
169		static WRITE16_HANDLER( astrocorp_eeprom_w )
	175	WRITE16_MEMBER(astrocorp_state::astrocorp_eeprom_w)
170	176	{
171	177	if (ACCESSING_BITS_0_7)
172	178	{
173		input_port_write(space->machine(), "EEPROMOUT", data, 0xff);
	179	input_port_write(machine(), "EEPROMOUT", data, 0xff);
174	180	}
175	181	}
176	182
r14845	r14846
194	200	}
195	201	}
196	202
197		static WRITE16_HANDLER( showhand_outputs_w )
	203	WRITE16_MEMBER(astrocorp_state::showhand_outputs_w)
198	204	{
199	205	if (ACCESSING_BITS_0_7)
200	206	{
201		coin_counter_w(space->machine(), 0,   (data & 0x0004));   // coin counter
202		set_led_status(space->machine(), 0,   (data & 0x0008));   // you win
203		if ((data & 0x0010)) increment_dispensed_tickets(space->machine(), 1); // coin out
204		set_led_status(space->machine(), 1,   (data & 0x0020));   // coin/hopper jam
	207	coin_counter_w(machine(), 0,   (data & 0x0004));   // coin counter
	208	set_led_status(machine(), 0,   (data & 0x0008));   // you win
	209	if ((data & 0x0010)) increment_dispensed_tickets(machine(), 1); // coin out
	210	set_led_status(machine(), 1,   (data & 0x0020));   // coin/hopper jam
205	211	}
206	212	if (ACCESSING_BITS_8_15)
207	213	{
208		set_led_status(space->machine(), 2,   (data & 0x0100));   // bet
209		set_led_status(space->machine(), 3,   (data & 0x0800));   // start
210		set_led_status(space->machine(), 4,   (data & 0x1000));   // ? select/choose
211		set_led_status(space->machine(), 5,   (data & 0x2000));   // ? select/choose
212		set_led_status(space->machine(), 6,   (data & 0x4000));   // look
	214	set_led_status(machine(), 2,   (data & 0x0100));   // bet
	215	set_led_status(machine(), 3,   (data & 0x0800));   // start
	216	set_led_status(machine(), 4,   (data & 0x1000));   // ? select/choose
	217	set_led_status(machine(), 5,   (data & 0x2000));   // ? select/choose
	218	set_led_status(machine(), 6,   (data & 0x4000));   // look
213	219	}
214	220	//  popmessage("%04X",data);
215	221	}
216	222
217		static WRITE16_HANDLER( skilldrp_outputs_w )
	223	WRITE16_MEMBER(astrocorp_state::skilldrp_outputs_w)
218	224	{
219	225	// key in          (0001)
220	226	// coin in         (0002)
r14845	r14846
234	240
235	241	if (ACCESSING_BITS_0_7)
236	242	{
237		coin_counter_w(space->machine(), 0,   (data & 0x0001));   // key in  |
238		coin_counter_w(space->machine(), 0,   (data & 0x0002));   // coin in |- manual shows 1 in- and 1 out- counter
239		coin_counter_w(space->machine(), 1,   (data & 0x0004));   // key out |
240		ticket_dispenser_w(space->machine().device("hopper"), 0, (data & 0x0008)<<4);   // hopper motor?
	243	coin_counter_w(machine(), 0,   (data & 0x0001));   // key in  |
	244	coin_counter_w(machine(), 0,   (data & 0x0002));   // coin in |- manual shows 1 in- and 1 out- counter
	245	coin_counter_w(machine(), 1,   (data & 0x0004));   // key out |
	246	ticket_dispenser_w(machine().device("hopper"), 0, (data & 0x0008)<<4);   // hopper motor?
241	247	//                                  (data & 0x0010)     // hopper?
242		set_led_status(space->machine(), 0,   (data & 0x0020));   // error lamp (coin/hopper jam: "call attendant")
243		ticket_dispenser_w(space->machine().device("ticket"), 0, data & 0x0080);   // ticket motor?
	248	set_led_status(machine(), 0,   (data & 0x0020));   // error lamp (coin/hopper jam: "call attendant")
	249	ticket_dispenser_w(machine().device("ticket"), 0, data & 0x0080);   // ticket motor?
244	250	}
245	251	if (ACCESSING_BITS_8_15)
246	252	{
247	253	// lamps:
248		set_led_status(space->machine(), 1,   (data & 0x0100));   // select
249		set_led_status(space->machine(), 2,   (data & 0x0400));   // take
250		set_led_status(space->machine(), 3,   (data & 0x0800));   // bet
251		set_led_status(space->machine(), 4,   (data & 0x1000));   // start
252		set_led_status(space->machine(), 5,   (data & 0x4000));   // win / test
253		set_led_status(space->machine(), 6,   (data & 0x8000));   // ticket?
	254	set_led_status(machine(), 1,   (data & 0x0100));   // select
	255	set_led_status(machine(), 2,   (data & 0x0400));   // take
	256	set_led_status(machine(), 3,   (data & 0x0800));   // bet
	257	set_led_status(machine(), 4,   (data & 0x1000));   // start
	258	set_led_status(machine(), 5,   (data & 0x4000));   // win / test
	259	set_led_status(machine(), 6,   (data & 0x8000));   // ticket?
254	260	}
255	261
256	262	//  popmessage("%04X",data);
257	263	}
258	264
259		static WRITE16_HANDLER( astrocorp_screen_enable_w )
	265	WRITE16_MEMBER(astrocorp_state::astrocorp_screen_enable_w)
260	266	{
261		astrocorp_state *state = space->machine().driver_data<astrocorp_state>();
262		COMBINE_DATA(&state->m_screen_enable);
	267	COMBINE_DATA(&m_screen_enable);
263	268	//  popmessage("%04X",data);
264		if (state->m_screen_enable & (~1))
265		logerror("CPU #0 PC %06X: screen enable = %04X\n", cpu_get_pc(&space->device()), state->m_screen_enable);
	269	if (m_screen_enable & (~1))
	270	logerror("CPU #0 PC %06X: screen enable = %04X\n", cpu_get_pc(&space.device()), m_screen_enable);
266	271	}
267	272
268		static READ16_HANDLER( astrocorp_unk_r )
	273	READ16_MEMBER(astrocorp_state::astrocorp_unk_r)
269	274	{
270	275	return 0xffff;   // bit 3?
271	276	}
272	277
273	278	// 5-6-5 Palette: BBBBB-GGGGGG-RRRRR
274		static WRITE16_HANDLER( astrocorp_palette_w )
	279	WRITE16_MEMBER(astrocorp_state::astrocorp_palette_w)
275	280	{
276		astrocorp_state *state = space->machine().driver_data<astrocorp_state>();
277		COMBINE_DATA(&state->m_paletteram[offset]);
278		palette_set_color_rgb(space->machine(), offset,
279		pal5bit((state->m_paletteram[offset] >>  0) & 0x1f),
280		pal6bit((state->m_paletteram[offset] >>  5) & 0x3f),
281		pal5bit((state->m_paletteram[offset] >> 11) & 0x1f)
	281	COMBINE_DATA(&m_paletteram[offset]);
	282	palette_set_color_rgb(machine(), offset,
	283	pal5bit((m_paletteram[offset] >>  0) & 0x1f),
	284	pal6bit((m_paletteram[offset] >>  5) & 0x3f),
	285	pal5bit((m_paletteram[offset] >> 11) & 0x1f)
282	286	);
283	287	}
284	288
285	289	static ADDRESS_MAP_START( showhand_map, AS_PROGRAM, 16, astrocorp_state )
286	290	AM_RANGE( 0x000000, 0x01ffff ) AM_ROM
287	291	AM_RANGE( 0x050000, 0x050fff ) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
288		AM_RANGE( 0x052000, 0x052001 ) AM_WRITE_LEGACY(astrocorp_draw_sprites_w)
	292	AM_RANGE( 0x052000, 0x052001 ) AM_WRITE(astrocorp_draw_sprites_w)
289	293	AM_RANGE( 0x054000, 0x054001 ) AM_READ_PORT("INPUTS")
290		AM_RANGE( 0x058000, 0x058001 ) AM_WRITE_LEGACY(astrocorp_eeprom_w)
291		AM_RANGE( 0x05a000, 0x05a001 ) AM_WRITE_LEGACY(showhand_outputs_w)
	294	AM_RANGE( 0x058000, 0x058001 ) AM_WRITE(astrocorp_eeprom_w)
	295	AM_RANGE( 0x05a000, 0x05a001 ) AM_WRITE(showhand_outputs_w)
292	296	AM_RANGE( 0x05e000, 0x05e001 ) AM_READ_PORT("EEPROMIN")
293		AM_RANGE( 0x060000, 0x0601ff ) AM_RAM_WRITE_LEGACY(astrocorp_palette_w) AM_BASE(m_paletteram)
	297	AM_RANGE( 0x060000, 0x0601ff ) AM_RAM_WRITE(astrocorp_palette_w) AM_BASE(m_paletteram)
294	298	AM_RANGE( 0x070000, 0x073fff ) AM_RAM AM_SHARE("nvram")   // battery
295	299	AM_RANGE( 0x080000, 0x080001 ) AM_DEVWRITE_LEGACY("oki", astrocorp_sound_bank_w)
296		AM_RANGE( 0x0a0000, 0x0a0001 ) AM_WRITE_LEGACY(astrocorp_screen_enable_w)
297		AM_RANGE( 0x0d0000, 0x0d0001 ) AM_READ_LEGACY(astrocorp_unk_r) AM_DEVWRITE8("oki", okim6295_device, write, 0xff00)
	300	AM_RANGE( 0x0a0000, 0x0a0001 ) AM_WRITE(astrocorp_screen_enable_w)
	301	AM_RANGE( 0x0d0000, 0x0d0001 ) AM_READ(astrocorp_unk_r) AM_DEVWRITE8("oki", okim6295_device, write, 0xff00)
298	302	ADDRESS_MAP_END
299	303
300	304	static ADDRESS_MAP_START( showhanc_map, AS_PROGRAM, 16, astrocorp_state )
301	305	AM_RANGE( 0x000000, 0x01ffff ) AM_ROM
302		AM_RANGE( 0x060000, 0x0601ff ) AM_RAM_WRITE_LEGACY(astrocorp_palette_w) AM_BASE(m_paletteram)
	306	AM_RANGE( 0x060000, 0x0601ff ) AM_RAM_WRITE(astrocorp_palette_w) AM_BASE(m_paletteram)
303	307	AM_RANGE( 0x070000, 0x070001 ) AM_DEVWRITE_LEGACY("oki", astrocorp_sound_bank_w)
304	308	AM_RANGE( 0x080000, 0x080fff ) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
305		AM_RANGE( 0x082000, 0x082001 ) AM_WRITE_LEGACY(astrocorp_draw_sprites_w)
	309	AM_RANGE( 0x082000, 0x082001 ) AM_WRITE(astrocorp_draw_sprites_w)
306	310	AM_RANGE( 0x084000, 0x084001 ) AM_READ_PORT("INPUTS")
307		AM_RANGE( 0x088000, 0x088001 ) AM_WRITE_LEGACY(astrocorp_eeprom_w)
308		AM_RANGE( 0x08a000, 0x08a001 ) AM_WRITE_LEGACY(showhand_outputs_w)
	311	AM_RANGE( 0x088000, 0x088001 ) AM_WRITE(astrocorp_eeprom_w)
	312	AM_RANGE( 0x08a000, 0x08a001 ) AM_WRITE(showhand_outputs_w)
309	313	AM_RANGE( 0x08e000, 0x08e001 ) AM_READ_PORT("EEPROMIN")
310	314	AM_RANGE( 0x090000, 0x093fff ) AM_RAM AM_SHARE("nvram")   // battery
311		AM_RANGE( 0x0a0000, 0x0a0001 ) AM_WRITE_LEGACY(astrocorp_screen_enable_w)
312		AM_RANGE( 0x0e0000, 0x0e0001 ) AM_READ_LEGACY(astrocorp_unk_r) AM_DEVWRITE8("oki", okim6295_device, write, 0xff00)
	315	AM_RANGE( 0x0a0000, 0x0a0001 ) AM_WRITE(astrocorp_screen_enable_w)
	316	AM_RANGE( 0x0e0000, 0x0e0001 ) AM_READ(astrocorp_unk_r) AM_DEVWRITE8("oki", okim6295_device, write, 0xff00)
313	317	ADDRESS_MAP_END
314	318
315	319	static ADDRESS_MAP_START( skilldrp_map, AS_PROGRAM, 16, astrocorp_state )
316	320	AM_RANGE( 0x000000, 0x03ffff ) AM_ROM
317	321	AM_RANGE( 0x200000, 0x200fff ) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
318		AM_RANGE( 0x202000, 0x202001 ) AM_WRITE_LEGACY(astrocorp_draw_sprites_w)
	322	AM_RANGE( 0x202000, 0x202001 ) AM_WRITE(astrocorp_draw_sprites_w)
319	323	AM_RANGE( 0x204000, 0x204001 ) AM_READ_PORT("INPUTS")
320		AM_RANGE( 0x208000, 0x208001 ) AM_WRITE_LEGACY(astrocorp_eeprom_w)
321		AM_RANGE( 0x20a000, 0x20a001 ) AM_WRITE_LEGACY(skilldrp_outputs_w)
	324	AM_RANGE( 0x208000, 0x208001 ) AM_WRITE(astrocorp_eeprom_w)
	325	AM_RANGE( 0x20a000, 0x20a001 ) AM_WRITE(skilldrp_outputs_w)
322	326	AM_RANGE( 0x20e000, 0x20e001 ) AM_READ_PORT("EEPROMIN")
323		AM_RANGE( 0x380000, 0x3801ff ) AM_RAM_WRITE_LEGACY(astrocorp_palette_w) AM_BASE(m_paletteram)
324		AM_RANGE( 0x400000, 0x400001 ) AM_WRITE_LEGACY(astrocorp_screen_enable_w)
	327	AM_RANGE( 0x380000, 0x3801ff ) AM_RAM_WRITE(astrocorp_palette_w) AM_BASE(m_paletteram)
	328	AM_RANGE( 0x400000, 0x400001 ) AM_WRITE(astrocorp_screen_enable_w)
325	329	AM_RANGE( 0x500000, 0x507fff ) AM_RAM AM_SHARE("nvram")   // battery
326	330	AM_RANGE( 0x580000, 0x580001 ) AM_DEVWRITE_LEGACY("oki", skilldrp_sound_bank_w)
327	331	AM_RANGE( 0x600000, 0x600001 ) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
r14845	r14846
331	335	AM_RANGE( 0x000000, 0x01ffff ) AM_ROM
332	336	AM_RANGE( 0x280000, 0x283fff ) AM_RAM AM_SHARE("nvram")   // battery
333	337	AM_RANGE( 0x380000, 0x380fff ) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
334		AM_RANGE( 0x382000, 0x382001 ) AM_WRITE_LEGACY(astrocorp_draw_sprites_w)
	338	AM_RANGE( 0x382000, 0x382001 ) AM_WRITE(astrocorp_draw_sprites_w)
335	339	AM_RANGE( 0x384000, 0x384001 ) AM_READ_PORT("INPUTS")
336		AM_RANGE( 0x388000, 0x388001 ) AM_WRITE_LEGACY(astrocorp_eeprom_w)
337		AM_RANGE( 0x38a000, 0x38a001 ) AM_WRITE_LEGACY(skilldrp_outputs_w)
	340	AM_RANGE( 0x388000, 0x388001 ) AM_WRITE(astrocorp_eeprom_w)
	341	AM_RANGE( 0x38a000, 0x38a001 ) AM_WRITE(skilldrp_outputs_w)
338	342	AM_RANGE( 0x38e000, 0x38e001 ) AM_READ_PORT("EEPROMIN")
339		AM_RANGE( 0x480000, 0x4801ff ) AM_RAM_WRITE_LEGACY(astrocorp_palette_w) AM_BASE(m_paletteram)
340		AM_RANGE( 0x500000, 0x500001 ) AM_WRITE_LEGACY(astrocorp_screen_enable_w)
	343	AM_RANGE( 0x480000, 0x4801ff ) AM_RAM_WRITE(astrocorp_palette_w) AM_BASE(m_paletteram)
	344	AM_RANGE( 0x500000, 0x500001 ) AM_WRITE(astrocorp_screen_enable_w)
341	345	AM_RANGE( 0x580000, 0x580001 ) AM_DEVWRITE_LEGACY("oki", skilldrp_sound_bank_w)
342	346	AM_RANGE( 0x600000, 0x600001 ) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
343	347	ADDRESS_MAP_END

src/mame/drivers/ltcasino.c

r14845	r14846
27	27	UINT8 *m_tile_num_ram;
28	28	UINT8 *m_tile_atr_ram;
29	29	tilemap_t *m_tilemap;
	30	DECLARE_WRITE8_MEMBER(ltcasino_tile_num_w);
	31	DECLARE_WRITE8_MEMBER(ltcasino_tile_atr_w);
30	32	};
31	33
32	34
r14845	r14846
52	54	}
53	55
54	56
55		static WRITE8_HANDLER( ltcasino_tile_num_w )
	57	WRITE8_MEMBER(ltcasino_state::ltcasino_tile_num_w)
56	58	{
57		ltcasino_state *state = space->machine().driver_data<ltcasino_state>();
58		state->m_tile_num_ram[offset] = data;
59		state->m_tilemap->mark_tile_dirty(offset);
	59	m_tile_num_ram[offset] = data;
	60	m_tilemap->mark_tile_dirty(offset);
60	61	}
61	62
62		static WRITE8_HANDLER( ltcasino_tile_atr_w )
	63	WRITE8_MEMBER(ltcasino_state::ltcasino_tile_atr_w)
63	64	{
64		ltcasino_state *state = space->machine().driver_data<ltcasino_state>();
65		state->m_tile_atr_ram[offset] = data;
66		state->m_tilemap->mark_tile_dirty(offset);
	65	m_tile_atr_ram[offset] = data;
	66	m_tilemap->mark_tile_dirty(offset);
67	67	}
68	68
69	69
70	70	static ADDRESS_MAP_START( ltcasino_map, AS_PROGRAM, 8, ltcasino_state )
71	71	AM_RANGE(0x0000, 0x7fff) AM_RAM
72	72	AM_RANGE(0x8000, 0xcfff) AM_ROM
73		AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE_LEGACY(ltcasino_tile_num_w) AM_BASE(m_tile_num_ram)
	73	AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE(ltcasino_tile_num_w) AM_BASE(m_tile_num_ram)
74	74	AM_RANGE(0xd800, 0xdfff) AM_RAM
75		AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE_LEGACY(ltcasino_tile_atr_w) AM_BASE(m_tile_atr_ram)
	75	AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE(ltcasino_tile_atr_w) AM_BASE(m_tile_atr_ram)
76	76	AM_RANGE(0xe800, 0xebff) AM_RAM
77	77
78	78	AM_RANGE(0xec00, 0xec00) AM_READ_PORT("IN0")

src/mame/drivers/meijinsn.c

r14845	r14846
89	89	int m_mcu_latch;
90	90
91	91	required_device<cpu_device> m_maincpu;
	92	DECLARE_WRITE16_MEMBER(sound_w);
	93	DECLARE_READ16_MEMBER(alpha_mcu_r);
92	94	};
93	95
94	96
95	97
96		static WRITE16_HANDLER( sound_w )
	98	WRITE16_MEMBER(meijinsn_state::sound_w)
97	99	{
98	100	if (ACCESSING_BITS_0_7)
99	101	soundlatch_w(space, 0, data & 0xff);
100	102	}
101	103
102		static READ16_HANDLER( alpha_mcu_r )
	104	READ16_MEMBER(meijinsn_state::alpha_mcu_r)
103	105	{
104		meijinsn_state *state = space->machine().driver_data<meijinsn_state>();
105	106	static const UINT8 coinage1[2][2] = {{1,1}, {1,2}};
106	107	static const UINT8 coinage2[2][2] = {{1,5}, {2,1}};
107	108
108		int source = state->m_shared_ram[offset];
	109	int source = m_shared_ram[offset];
109	110
110	111	switch (offset)
111	112	{
112	113	case 0: /* Dipswitch 2 */
113		state->m_shared_ram[0] = (source & 0xff00) | input_port_read(space->machine(), "DSW");
	114	m_shared_ram[0] = (source & 0xff00) | input_port_read(machine(), "DSW");
114	115	return 0;
115	116
116	117	case 0x22: /* Coin value */
117		state->m_shared_ram[0x22] = (source & 0xff00) | (state->m_credits & 0x00ff);
	118	m_shared_ram[0x22] = (source & 0xff00) | (m_credits & 0x00ff);
118	119	return 0;
119	120
120	121	case 0x29: /* Query microcontroller for coin insert */
121	122
122		state->m_credits = 0;
	123	m_credits = 0;
123	124
124		if ((input_port_read(space->machine(), "COINS") & 0x3) == 3)
125		state->m_mcu_latch = 0;
	125	if ((input_port_read(machine(), "COINS") & 0x3) == 3)
	126	m_mcu_latch = 0;
126	127
127		if ((input_port_read(space->machine(), "COINS") & 0x1) == 0 && !state->m_mcu_latch)
	128	if ((input_port_read(machine(), "COINS") & 0x1) == 0 && !m_mcu_latch)
128	129	{
129		state->m_shared_ram[0x29] = (source & 0xff00) | 0x22;   // coinA
130		state->m_shared_ram[0x22] = (source & 0xff00) | 0x00;
131		state->m_mcu_latch = 1;
	130	m_shared_ram[0x29] = (source & 0xff00) | 0x22;   // coinA
	131	m_shared_ram[0x22] = (source & 0xff00) | 0x00;
	132	m_mcu_latch = 1;
132	133
133		state->m_coinvalue = (~input_port_read(space->machine(), "DSW")>>3) & 1;
	134	m_coinvalue = (~input_port_read(machine(), "DSW")>>3) & 1;
134	135
135		state->m_deposits1++;
136		if (state->m_deposits1 == coinage1[state->m_coinvalue][0])
	136	m_deposits1++;
	137	if (m_deposits1 == coinage1[m_coinvalue][0])
137	138	{
138		state->m_credits = coinage1[state->m_coinvalue][1];
139		state->m_deposits1 = 0;
	139	m_credits = coinage1[m_coinvalue][1];
	140	m_deposits1 = 0;
140	141	}
141	142	else
142		state->m_credits = 0;
	143	m_credits = 0;
143	144	}
144		else if ((input_port_read(space->machine(), "COINS") & 0x2) == 0 && !state->m_mcu_latch)
	145	else if ((input_port_read(machine(), "COINS") & 0x2) == 0 && !m_mcu_latch)
145	146	{
146		state->m_shared_ram[0x29] = (source & 0xff00) | 0x22;   // coinA
147		state->m_shared_ram[0x22] = (source & 0xff00) | 0x00;
148		state->m_mcu_latch = 1;
	147	m_shared_ram[0x29] = (source & 0xff00) | 0x22;   // coinA
	148	m_shared_ram[0x22] = (source & 0xff00) | 0x00;
	149	m_mcu_latch = 1;
149	150
150		state->m_coinvalue = (~input_port_read(space->machine(), "DSW") >> 3) & 1;
	151	m_coinvalue = (~input_port_read(machine(), "DSW") >> 3) & 1;
151	152
152		state->m_deposits2++;
153		if (state->m_deposits2 == coinage2[state->m_coinvalue][0])
	153	m_deposits2++;
	154	if (m_deposits2 == coinage2[m_coinvalue][0])
154	155	{
155		state->m_credits = coinage2[state->m_coinvalue][1];
156		state->m_deposits2 = 0;
	156	m_credits = coinage2[m_coinvalue][1];
	157	m_deposits2 = 0;
157	158	}
158	159	else
159		state->m_credits = 0;
	160	m_credits = 0;
160	161	}
161	162	else
162	163	{
163		state->m_shared_ram[0x29] = (source & 0xff00) | 0x22;
	164	m_shared_ram[0x29] = (source & 0xff00) | 0x22;
164	165	}
165	166	return 0;
166	167	}
r14845	r14846
171	172
172	173	static ADDRESS_MAP_START( meijinsn_map, AS_PROGRAM, 16, meijinsn_state )
173	174	AM_RANGE(0x000000, 0x03ffff) AM_ROM
174		AM_RANGE(0x080e00, 0x080fff) AM_READ_LEGACY(alpha_mcu_r) AM_WRITENOP
	175	AM_RANGE(0x080e00, 0x080fff) AM_READ(alpha_mcu_r) AM_WRITENOP
175	176	AM_RANGE(0x100000, 0x107fff) AM_RAM AM_BASE(m_videoram)
176	177	AM_RANGE(0x180000, 0x180dff) AM_RAM
177	178	AM_RANGE(0x180e00, 0x180fff) AM_RAM AM_BASE(m_shared_ram)
178	179	AM_RANGE(0x181000, 0x181fff) AM_RAM
179	180	AM_RANGE(0x1c0000, 0x1c0001) AM_READ_PORT("P2")
180		AM_RANGE(0x1a0000, 0x1a0001) AM_READ_PORT("P1") AM_WRITE_LEGACY(sound_w)
	181	AM_RANGE(0x1a0000, 0x1a0001) AM_READ_PORT("P1") AM_WRITE(sound_w)
181	182	ADDRESS_MAP_END
182	183
183	184	static ADDRESS_MAP_START( meijinsn_sound_map, AS_PROGRAM, 8, meijinsn_state )

src/mame/drivers/coolridr.c

r14845	r14846
297	297	required_device<cpu_device> m_maincpu;
298	298	required_device<cpu_device> m_subcpu;
299	299	required_device<cpu_device> m_soundcpu;
	300	DECLARE_READ32_MEMBER(sysh1_unk_r);
	301	DECLARE_WRITE32_MEMBER(sysh1_unk_w);
	302	DECLARE_READ32_MEMBER(sysh1_ioga_r);
	303	DECLARE_WRITE32_MEMBER(sysh1_ioga_w);
	304	DECLARE_WRITE32_MEMBER(sysh1_txt_blit_w);
	305	DECLARE_WRITE32_MEMBER(sysh1_pal_w);
	306	DECLARE_WRITE32_MEMBER(sysh1_dma_w);
	307	DECLARE_WRITE32_MEMBER(sysh1_char_w);
	308	DECLARE_READ32_MEMBER(coolridr_hack1_r);
	309	DECLARE_READ32_MEMBER(coolridr_hack2_r);
300	310	};
301	311
302	312
r14845	r14846
376	386	/* end video */
377	387
378	388	/* unknown purpose */
379		static READ32_HANDLER(sysh1_unk_r)
	389	READ32_MEMBER(coolridr_state::sysh1_unk_r)
380	390	{
381		coolridr_state *state = space->machine().driver_data<coolridr_state>();
382	391	switch(offset)
383	392	{
384	393	case 0x08/4:
385	394	{
386	395
387		state->m_vblank^=1;
	396	m_vblank^=1;
388	397
389		return (state->m_h1_unk[offset] & 0xfdffffff) | (state->m_vblank<<25);
	398	return (m_h1_unk[offset] & 0xfdffffff) | (m_vblank<<25);
390	399	}
391	400	case 0x14/4:
392		return state->m_h1_unk[offset];
	401	return m_h1_unk[offset];
393	402	//case 0x20/4:
394	403	}
395	404
396		return 0xffffffff;//state->m_h1_unk[offset];
	405	return 0xffffffff;//m_h1_unk[offset];
397	406	}
398	407
399		static WRITE32_HANDLER(sysh1_unk_w)
	408	WRITE32_MEMBER(coolridr_state::sysh1_unk_w)
400	409	{
401		coolridr_state *state = space->machine().driver_data<coolridr_state>();
402		COMBINE_DATA(&state->m_h1_unk[offset]);
	410	COMBINE_DATA(&m_h1_unk[offset]);
403	411	}
404	412
405	413	/* According to Guru, this is actually the same I/O chip of Sega Model 2 HW */
406	414	#if 0
407		static READ32_HANDLER(sysh1_ioga_r)
	415	READ32_MEMBER(coolridr_state::sysh1_ioga_r)
408	416	{
409		//return space->machine().rand();//h1_ioga[offset];
	417	//return machine().rand();//h1_ioga[offset];
410	418	return h1_ioga[offset];
411	419	}
412	420
413		static WRITE32_HANDLER(sysh1_ioga_w)
	421	WRITE32_MEMBER(coolridr_state::sysh1_ioga_w)
414	422	{
415	423	COMBINE_DATA(&h1_ioga[offset]);
416	424	}
r14845	r14846
418	426
419	427
420	428	/* This is a RLE-based sprite blitter (US Patent #6,141,122), very unusual from Sega... */
421		static WRITE32_HANDLER( sysh1_txt_blit_w )
	429	WRITE32_MEMBER(coolridr_state::sysh1_txt_blit_w)
422	430	{
423		coolridr_state *state = space->machine().driver_data<coolridr_state>();
424	431
425		COMBINE_DATA(&state->m_sysh1_txt_blit[offset]);
	432	COMBINE_DATA(&m_sysh1_txt_blit[offset]);
426	433
427	434	switch(offset)
428	435	{
429	436	// The mode register
430	437	case 0x04:
431	438	{
432		state->m_blitterMode = (data & 0x00ff0000) >> 16;
	439	m_blitterMode = (data & 0x00ff0000) >> 16;
433	440
434		if (state->m_blitterMode == 0xf4)
	441	if (m_blitterMode == 0xf4)
435	442	{
436	443	// Some sort of addressing state.
437	444	// In the case of text, simply writes 4 characters per 32-bit word.
438	445	// These values may be loaded into RAM somewhere as they are written.
439	446	// The number of characters is determined by the upper-most 8 bits.
440		state->m_textBytesToWrite = (data & 0xff000000) >> 24;
441		state->m_textOffset = (data & 0x0000ffff);
442		state->m_blitterSerialCount = 0;
	447	m_textBytesToWrite = (data & 0xff000000) >> 24;
	448	m_textOffset = (data & 0x0000ffff);
	449	m_blitterSerialCount = 0;
443	450	}
444		else if (state->m_blitterMode == 0x30 || state->m_blitterMode == 0x90)
	451	else if (m_blitterMode == 0x30 || m_blitterMode == 0x90)
445	452	{
446	453	// The blitter function(s).
447	454	// After this is set a fixed count of 11 32-bit words are sent to the data register.
448	455	// The lower word always seems to be 0x0001 and the upper byte always 0xac.
449		state->m_blitterSerialCount = 0;
	456	m_blitterSerialCount = 0;
450	457	}
451		else if (state->m_blitterMode == 0x10)
	458	else if (m_blitterMode == 0x10)
452	459	{
453	460	// Could be a full clear of VRAM?
454	461	for(UINT32 vramAddr = 0x3f40000; vramAddr < 0x3f4ffff; vramAddr+=4)
455		space->write_dword(vramAddr, 0x00000000);
	462	space.write_dword(vramAddr, 0x00000000);
456	463	}
457	464	break;
458	465	}
r14845	r14846
460	467	// The data register
461	468	case 0x05:
462	469	{
463		if (state->m_blitterMode == 0xf4)
	470	if (m_blitterMode == 0xf4)
464	471	{
465	472	// Uploads a series of bytes that index into the encoded sprite table
466		const size_t memOffset = 0x03f40000 + state->m_textOffset + state->m_blitterSerialCount;
467		space->write_dword(memOffset, data);
468		state->m_blitterSerialCount += 0x04;
	473	const size_t memOffset = 0x03f40000 + m_textOffset + m_blitterSerialCount;
	474	space.write_dword(memOffset, data);
	475	m_blitterSerialCount += 0x04;
469	476
470	477	// DEBUG: Uncomment to see the ASCII strings as they are being blitted
471		//if (state->m_blitterSerialCount >= state->m_textBytesToWrite)
	478	//if (m_blitterSerialCount >= m_textBytesToWrite)
472	479	//{
473		//  for (int i = 0; i < state->m_textBytesToWrite+1; i++)
474		//      printf("%c", space->read_byte(0x03f40000 + state->m_textOffset + i));
	480	//  for (int i = 0; i < m_textBytesToWrite+1; i++)
	481	//      printf("%c", read_byte(0x03f40000 + m_textOffset + i));
475	482	//  printf("\n");
476	483	//}
477	484	}
478		else if (state->m_blitterMode == 0x30 || state->m_blitterMode == 0x90)
	485	else if (m_blitterMode == 0x30 || m_blitterMode == 0x90)
479	486	{
480	487	// Serialized 32-bit words in order of appearance:
481	488	//  0: 00000000 - totally unknown : always seems to be zero
r14845	r14846
495	502	//                (See ifdef'ed out code below for a closer examination)
496	503
497	504	// Serialized counts
498		if (state->m_blitterSerialCount == 1)
	505	if (m_blitterSerialCount == 1)
499	506	{
500		state->m_colorNumber = (data & 0x000000ff);   // Probably more bits
	507	m_colorNumber = (data & 0x000000ff);   // Probably more bits
501	508	}
502		else if (state->m_blitterSerialCount == 6)
	509	else if (m_blitterSerialCount == 6)
503	510	{
504		state->m_vCellCount = (data & 0xffff0000) >> 16;
505		state->m_hCellCount = (data & 0x0000ffff);
	511	m_vCellCount = (data & 0xffff0000) >> 16;
	512	m_hCellCount = (data & 0x0000ffff);
506	513	}
507		else if (state->m_blitterSerialCount == 9)
	514	else if (m_blitterSerialCount == 9)
508	515	{
509		state->m_vPosition = (data & 0xffff0000) >> 16;
510		state->m_hPosition = (data & 0x0000ffff);
	516	m_vPosition = (data & 0xffff0000) >> 16;
	517	m_hPosition = (data & 0x0000ffff);
511	518	}
512		else if (state->m_blitterSerialCount == 11)
	519	else if (m_blitterSerialCount == 11)
513	520	{
514	521	const UINT32 memOffset = data;
515	522
516	523	// Splat some sprites
517		for (int h = 0; h < state->m_hCellCount; h++)
	524	for (int h = 0; h < m_hCellCount; h++)
518	525	{
519		for (int v = 0; v < state->m_vCellCount; v++)
	526	for (int v = 0; v < m_vCellCount; v++)
520	527	{
521		const int pixelOffsetX = state->m_hPosition + (h*16);
522		const int pixelOffsetY = state->m_vPosition + (v*16);
	528	const int pixelOffsetX = m_hPosition + (h*16);
	529	const int pixelOffsetY = m_vPosition + (v*16);
523	530
524	531	// It's unknown if it's row-major or column-major
525	532	// TODO: Study the CRT test and "Cool Riders" logo for clues.
526		UINT8 spriteNumber = space->read_byte(memOffset + h + (v*h));
	533	UINT8 spriteNumber = space.read_byte(memOffset + h + (v*h));
527	534
528		// DEBUG: For demo purposes, skip spaces and NULL characters
	535	// DEBUG: For demo purposes, skip &spaces and NULL characters
529	536	if (spriteNumber == 0x20 || spriteNumber == 0x00)
530	537	continue;
531	538
r14845	r14846
535	542	for (int y = 1; y < 15; y++)
536	543	{
537	544	UINT32 color;
538		if (state->m_colorNumber == 0x5b)
	545	if (m_colorNumber == 0x5b)
539	546	color = 0xffff0000;
540		else if (state->m_colorNumber == 0x5d)
	547	else if (m_colorNumber == 0x5d)
541	548	color = 0xff00ff00;
542		else if (state->m_colorNumber == 0x5e)
	549	else if (m_colorNumber == 0x5e)
543	550	color = 0xff0000ff;
544	551	else
545	552	color = 0xff00ffff;
546		state->m_temp_bitmap_sprites.pix32(pixelOffsetY+y, pixelOffsetX+x) = color;
	553	m_temp_bitmap_sprites.pix32(pixelOffsetY+y, pixelOffsetX+x) = color;
547	554	}
548	555	}
549	556	}
550	557	}
551	558	}
552	559
553		state->m_blitterSerialCount++;
	560	m_blitterSerialCount++;
554	561	}
555	562	break;
556	563	}
r14845	r14846
558	565	}
559	566
560	567
561		static WRITE32_HANDLER( sysh1_pal_w )
	568	WRITE32_MEMBER(coolridr_state::sysh1_pal_w)
562	569	{
563	570	int r,g,b;
564		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
	571	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
565	572
566		r = ((space->machine().generic.paletteram.u32[offset] & 0x00007c00) >> 10);
567		g = ((space->machine().generic.paletteram.u32[offset] & 0x000003e0) >> 5);
568		b = ((space->machine().generic.paletteram.u32[offset] & 0x0000001f) >> 0);
569		palette_set_color_rgb(space->machine(),(offset*2)+1,pal5bit(r),pal5bit(g),pal5bit(b));
570		r = ((space->machine().generic.paletteram.u32[offset] & 0x7c000000) >> 26);
571		g = ((space->machine().generic.paletteram.u32[offset] & 0x03e00000) >> 21);
572		b = ((space->machine().generic.paletteram.u32[offset] & 0x001f0000) >> 16);
573		palette_set_color_rgb(space->machine(),offset*2,pal5bit(r),pal5bit(g),pal5bit(b));
	573	r = ((machine().generic.paletteram.u32[offset] & 0x00007c00) >> 10);
	574	g = ((machine().generic.paletteram.u32[offset] & 0x000003e0) >> 5);
	575	b = ((machine().generic.paletteram.u32[offset] & 0x0000001f) >> 0);
	576	palette_set_color_rgb(machine(),(offset*2)+1,pal5bit(r),pal5bit(g),pal5bit(b));
	577	r = ((machine().generic.paletteram.u32[offset] & 0x7c000000) >> 26);
	578	g = ((machine().generic.paletteram.u32[offset] & 0x03e00000) >> 21);
	579	b = ((machine().generic.paletteram.u32[offset] & 0x001f0000) >> 16);
	580	palette_set_color_rgb(machine(),offset*2,pal5bit(r),pal5bit(g),pal5bit(b));
574	581	}
575	582
576	583
r14845	r14846
651	658	}while(!end_dma_mark );
652	659	}
653	660
654		static WRITE32_HANDLER( sysh1_dma_w )
	661	WRITE32_MEMBER(coolridr_state::sysh1_dma_w)
655	662	{
656		coolridr_state *state = space->machine().driver_data<coolridr_state>();
657		COMBINE_DATA(&state->m_framebuffer_vram[offset]);
	663	COMBINE_DATA(&m_framebuffer_vram[offset]);
658	664
659	665	if(offset*4 == 0x000)
660	666	{
661		if((state->m_framebuffer_vram[offset] & 0xff00000) == 0xfe00000)
662		sysh1_dma_transfer(space, state->m_framebuffer_vram[offset] & 0xffff);
	667	if((m_framebuffer_vram[offset] & 0xff00000) == 0xfe00000)
	668	sysh1_dma_transfer(&space, m_framebuffer_vram[offset] & 0xffff);
663	669	}
664	670	}
665	671
666		static WRITE32_HANDLER( sysh1_char_w )
	672	WRITE32_MEMBER(coolridr_state::sysh1_char_w)
667	673	{
668		coolridr_state *state = space->machine().driver_data<coolridr_state>();
669		COMBINE_DATA(&state->m_h1_charram[offset]);
	674	COMBINE_DATA(&m_h1_charram[offset]);
670	675
671	676	{
672		UINT8 *gfx = space->machine().region("ram_gfx")->base();
	677	UINT8 *gfx = machine().region("ram_gfx")->base();
673	678
674		gfx[offset*4+0] = (state->m_h1_charram[offset] & 0xff000000) >> 24;
675		gfx[offset*4+1] = (state->m_h1_charram[offset] & 0x00ff0000) >> 16;
676		gfx[offset*4+2] = (state->m_h1_charram[offset] & 0x0000ff00) >> 8;
677		gfx[offset*4+3] = (state->m_h1_charram[offset] & 0x000000ff) >> 0;
	679	gfx[offset*4+0] = (m_h1_charram[offset] & 0xff000000) >> 24;
	680	gfx[offset*4+1] = (m_h1_charram[offset] & 0x00ff0000) >> 16;
	681	gfx[offset*4+2] = (m_h1_charram[offset] & 0x0000ff00) >> 8;
	682	gfx[offset*4+3] = (m_h1_charram[offset] & 0x000000ff) >> 0;
678	683
679		gfx_element_mark_dirty(space->machine().gfx[2], offset/64); //*4/256
	684	gfx_element_mark_dirty(machine().gfx[2], offset/64); //*4/256
680	685	}
681	686	}
682	687
r14845	r14846
685	690	AM_RANGE(0x01000000, 0x01ffffff) AM_ROM AM_REGION("gfx_data",0x0000000)
686	691
687	692	AM_RANGE(0x03000000, 0x030fffff) AM_RAM AM_BASE(m_h1_vram)//bg vram
688		AM_RANGE(0x03c00000, 0x03c0ffff) AM_RAM_WRITE_LEGACY(sysh1_pal_w) AM_BASE_GENERIC(paletteram)
689		AM_RANGE(0x03d00000, 0x03dfffff) AM_RAM_WRITE_LEGACY(sysh1_char_w) AM_BASE(m_h1_charram) //FIXME: half size
690		AM_RANGE(0x03e00000, 0x03efffff) AM_RAM_WRITE_LEGACY(sysh1_dma_w) AM_BASE(m_framebuffer_vram) //FIXME: not all of it
	693	AM_RANGE(0x03c00000, 0x03c0ffff) AM_RAM_WRITE(sysh1_pal_w) AM_BASE_GENERIC(paletteram)
	694	AM_RANGE(0x03d00000, 0x03dfffff) AM_RAM_WRITE(sysh1_char_w) AM_BASE(m_h1_charram) //FIXME: half size
	695	AM_RANGE(0x03e00000, 0x03efffff) AM_RAM_WRITE(sysh1_dma_w) AM_BASE(m_framebuffer_vram) //FIXME: not all of it
691	696
692	697	AM_RANGE(0x03f00000, 0x03f0ffff) AM_RAM AM_SHARE("share3") /*Communication area RAM*/
693	698	AM_RANGE(0x03f40000, 0x03f4ffff) AM_RAM AM_BASE(m_txt_vram)//text tilemap + "lineram"
694		AM_RANGE(0x04000000, 0x0400003f) AM_RAM_WRITE_LEGACY(sysh1_txt_blit_w) AM_BASE(m_sysh1_txt_blit)
	699	AM_RANGE(0x04000000, 0x0400003f) AM_RAM_WRITE(sysh1_txt_blit_w) AM_BASE(m_sysh1_txt_blit)
695	700	AM_RANGE(0x06000000, 0x060fffff) AM_RAM AM_BASE(m_sysh1_workram_h)
696	701	AM_RANGE(0x20000000, 0x201fffff) AM_ROM AM_SHARE("share1")
697	702
r14845	r14846
710	715	AM_RANGE(0x03208900, 0x03208903) AM_RAM /*???*/
711	716	AM_RANGE(0x03300400, 0x03300403) AM_RAM /*irq enable?*/
712	717
713		AM_RANGE(0x04000000, 0x0400003f) AM_READWRITE_LEGACY(sysh1_unk_r,sysh1_unk_w) AM_BASE(m_h1_unk)
	718	AM_RANGE(0x04000000, 0x0400003f) AM_READWRITE(sysh1_unk_r,sysh1_unk_w) AM_BASE(m_h1_unk)
714	719	AM_RANGE(0x04200000, 0x0420003f) AM_RAM /*???*/
715	720
716	721	AM_RANGE(0x05000000, 0x05000fff) AM_RAM
r14845	r14846
1215	1220	ROM_END
1216	1221
1217	1222	#if 0
1218		static READ32_HANDLER( coolridr_hack1_r )
	1223	READ32_MEMBER(coolridr_state::coolridr_hack1_r)
1219	1224	{
1220		coolridr_state *state = space->machine().driver_data<coolridr_state>();
1221		offs_t pc = downcast<cpu_device *>(&space->device())->pc();
	1225	offs_t pc = downcast<cpu_device *>(&space.device())->pc();
1222	1226	if(pc == 0x6012374 || pc == 0x6012392)
1223	1227	return 0;
1224	1228
1225		return state->m_sysh1_workram_h[0xd88a4/4];
	1229	return m_sysh1_workram_h[0xd88a4/4];
1226	1230	}
1227	1231	#endif
1228	1232
1229	1233	/*TODO: there must be an irq line with custom vector located somewhere that writes to here...*/
1230		static READ32_HANDLER( coolridr_hack2_r )
	1234	READ32_MEMBER(coolridr_state::coolridr_hack2_r)
1231	1235	{
1232		coolridr_state *state = space->machine().driver_data<coolridr_state>();
1233		offs_t pc = downcast<cpu_device *>(&space->device())->pc();
	1236	offs_t pc = downcast<cpu_device *>(&space.device())->pc();
1234	1237	if(pc == 0x6002cba || pc == 0x6002d42)
1235	1238	return 0;
1236	1239
1237		return state->m_sysh1_workram_h[0xd8894/4];
	1240	return m_sysh1_workram_h[0xd8894/4];
1238	1241	}
1239	1242
1240	1243	static DRIVER_INIT( coolridr )
1241	1244	{
	1245	coolridr_state *state = machine.driver_data<coolridr_state>();
1242	1246	//  machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x60d88a4, 0x060d88a7, FUNC(coolridr_hack1_r) );
1243		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x60d8894, 0x060d8897, FUNC(coolridr_hack2_r) );
	1247	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x60d8894, 0x060d8897, read32_delegate(FUNC(coolridr_state::coolridr_hack2_r), state));
1244	1248	}
1245	1249
1246	1250	GAME( 1995, coolridr,    0, coolridr,    coolridr,    coolridr, ROT0,  "Sega", "Cool Riders (US)",GAME_NOT_WORKING|GAME_NO_SOUND )

src/mame/drivers/blitz.c

r14845	r14846
302	302	UINT8 *m_colorram;
303	303	tilemap_t *m_bg_tilemap;
304	304	int m_mux_data;
	305	DECLARE_WRITE8_MEMBER(megadpkr_videoram_w);
	306	DECLARE_WRITE8_MEMBER(megadpkr_colorram_w);
305	307	};
306	308
307	309
r14845	r14846
311	313	*********************************************/
312	314
313	315
314		static WRITE8_HANDLER( megadpkr_videoram_w )
	316	WRITE8_MEMBER(blitz_state::megadpkr_videoram_w)
315	317	{
316		blitz_state *state = space->machine().driver_data<blitz_state>();
317		state->m_videoram[offset] = data;
318		state->m_bg_tilemap->mark_tile_dirty(offset);
	318	m_videoram[offset] = data;
	319	m_bg_tilemap->mark_tile_dirty(offset);
319	320	}
320	321
321		static WRITE8_HANDLER( megadpkr_colorram_w )
	322	WRITE8_MEMBER(blitz_state::megadpkr_colorram_w)
322	323	{
323		blitz_state *state = space->machine().driver_data<blitz_state>();
324		state->m_colorram[offset] = data;
325		state->m_bg_tilemap->mark_tile_dirty(offset);
	324	m_colorram[offset] = data;
	325	m_bg_tilemap->mark_tile_dirty(offset);
326	326	}
327	327
328	328
r14845	r14846
485	485	AM_RANGE(0x10f8, 0x10fb) AM_DEVREADWRITE("pia1", pia6821_device, read, write)
486	486	*/
487	487
488		AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE_LEGACY(megadpkr_videoram_w) AM_BASE(m_videoram)
489		AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE_LEGACY(megadpkr_colorram_w) AM_BASE(m_colorram)
	488	AM_RANGE(0x1000, 0x13ff) AM_RAM_WRITE(megadpkr_videoram_w) AM_BASE(m_videoram)
	489	AM_RANGE(0x1800, 0x1bff) AM_RAM_WRITE(megadpkr_colorram_w) AM_BASE(m_colorram)
490	490
491	491	AM_RANGE(0xc000, 0xffff) AM_ROM
492	492	ADDRESS_MAP_END

src/mame/drivers/intrscti.c

r14845	r14846
22	22	: driver_device(mconfig, type, tag) { }
23	23
24	24	UINT8 *m_ram;
	25	DECLARE_READ8_MEMBER(unk_r);
25	26	};
26	27
27	28
28		static READ8_HANDLER( unk_r )
	29	READ8_MEMBER(intrscti_state::unk_r)
29	30	{
30		return space->machine().rand();
	31	return machine().rand();
31	32	}
32	33
33	34	static ADDRESS_MAP_START( intrscti_map, AS_PROGRAM, 8, intrscti_state )
r14845	r14846
39	40
40	41	static ADDRESS_MAP_START( readport, AS_IO, 8, intrscti_state )
41	42	ADDRESS_MAP_GLOBAL_MASK(0xff)
42		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(unk_r )
43		AM_RANGE(0x01, 0x01) AM_READ_LEGACY(unk_r )
	43	AM_RANGE(0x00, 0x00) AM_READ(unk_r )
	44	AM_RANGE(0x01, 0x01) AM_READ(unk_r )
44	45	ADDRESS_MAP_END
45	46
46	47

src/mame/drivers/sfbonus.c

r14845	r14846
301	301	UINT8* m_3000_regs;
302	302	UINT8* m_2801_regs;
303	303	UINT8* m_2c01_regs;
	304	DECLARE_WRITE8_MEMBER(sfbonus_videoram_w);
	305	DECLARE_WRITE8_MEMBER(sfbonus_bank_w);
	306	DECLARE_READ8_MEMBER(sfbonus_2800_r);
	307	DECLARE_READ8_MEMBER(sfbonus_2801_r);
	308	DECLARE_READ8_MEMBER(sfbonus_2c00_r);
	309	DECLARE_READ8_MEMBER(sfbonus_2c01_r);
	310	DECLARE_READ8_MEMBER(sfbonus_3800_r);
	311	DECLARE_WRITE8_MEMBER(sfbonus_1800_w);
	312	DECLARE_WRITE8_MEMBER(sfbonus_3800_w);
	313	DECLARE_WRITE8_MEMBER(sfbonus_3000_w);
	314	DECLARE_WRITE8_MEMBER(sfbonus_2801_w);
	315	DECLARE_WRITE8_MEMBER(sfbonus_2c01_w);
304	316	};
305	317
306	318
r14845	r14846
702	714	}
703	715
704	716
705		static WRITE8_HANDLER( sfbonus_videoram_w )
	717	WRITE8_MEMBER(sfbonus_state::sfbonus_videoram_w)
706	718	{
707		sfbonus_state *state = space->machine().driver_data<sfbonus_state>();
708	719	if (offset<0x4000) /* 0x0000 - 0x3fff */
709	720	{
710		state->m_tilemap_ram[offset] = data;
711		state->m_tilemap->mark_tile_dirty(offset/2);
	721	m_tilemap_ram[offset] = data;
	722	m_tilemap->mark_tile_dirty(offset/2);
712	723	}
713	724	else if (offset<0x4800) /* 0x4000 - 0x47ff */
714	725	{
715	726	offset-=0x4000;
716	727
717		state->m_reel_ram[offset] = data;
718		state->m_reel_tilemap->mark_tile_dirty(offset/2);
	728	m_reel_ram[offset] = data;
	729	m_reel_tilemap->mark_tile_dirty(offset/2);
719	730	}
720	731	else if (offset<0x5000)  /* 0x4800 - 0x4fff */
721	732	{
722	733	offset-=0x4800;
723	734
724		state->m_reel2_ram[offset] = data;
725		state->m_reel2_tilemap->mark_tile_dirty(offset/2);
	735	m_reel2_ram[offset] = data;
	736	m_reel2_tilemap->mark_tile_dirty(offset/2);
726	737	}
727	738	else if (offset<0x5800) /* 0x5000 - 0x57ff */
728	739	{
729	740	offset-=0x5000;
730	741
731		state->m_reel3_ram[offset] = data;
732		state->m_reel3_tilemap->mark_tile_dirty(offset/2);
	742	m_reel3_ram[offset] = data;
	743	m_reel3_tilemap->mark_tile_dirty(offset/2);
733	744	}
734	745	else if (offset<0x6000) /* 0x5800 - 0x5fff */
735	746	{
736	747	offset-=0x5800;
737	748
738		state->m_reel4_ram[offset] = data;
739		state->m_reel4_tilemap->mark_tile_dirty(offset/2);
	749	m_reel4_ram[offset] = data;
	750	m_reel4_tilemap->mark_tile_dirty(offset/2);
740	751	}
741	752	else if (offset<0x8000)
742	753	{
743	754	offset -=0x6000;
744	755	// scroll regs etc.
745	756	//logerror("access vram at [%04x] <- %02x\n",offset,data);
746		state->m_videoram[offset] = data;
	757	m_videoram[offset] = data;
747	758	}
748	759	else
749	760	{
r14845	r14846
1057	1068
1058	1069
1059	1070	static ADDRESS_MAP_START( sfbonus_map, AS_PROGRAM, 8, sfbonus_state )
1060		AM_RANGE(0x0000, 0xefff) AM_ROMBANK("bank1") AM_WRITE_LEGACY(sfbonus_videoram_w)
	1071	AM_RANGE(0x0000, 0xefff) AM_ROMBANK("bank1") AM_WRITE(sfbonus_videoram_w)
1061	1072	AM_RANGE(0xf000, 0xffff) AM_RAM AM_BASE(m_nvram) AM_SIZE(m_nvram_size)
1062	1073	ADDRESS_MAP_END
1063	1074
1064		static WRITE8_HANDLER( sfbonus_bank_w )
	1075	WRITE8_MEMBER(sfbonus_state::sfbonus_bank_w)
1065	1076	{
1066		UINT8 *ROM = space->machine().region("maincpu")->base();
	1077	UINT8 *ROM = machine().region("maincpu")->base();
1067	1078	UINT8 bank;
1068	1079
1069	1080	bank = data & 7;
1070	1081
1071		memory_set_bankptr(space->machine(), "bank1", &ROM[bank * 0x10000]);
	1082	memory_set_bankptr(machine(), "bank1", &ROM[bank * 0x10000]);
1072	1083	}
1073	1084
1074	1085
1075	1086
1076		static READ8_HANDLER( sfbonus_2800_r )
	1087	READ8_MEMBER(sfbonus_state::sfbonus_2800_r)
1077	1088	{
1078		return space->machine().rand();
	1089	return machine().rand();
1079	1090	}
1080	1091
1081		static READ8_HANDLER( sfbonus_2801_r )
	1092	READ8_MEMBER(sfbonus_state::sfbonus_2801_r)
1082	1093	{
1083		return space->machine().rand();
	1094	return machine().rand();
1084	1095	}
1085	1096
1086		static READ8_HANDLER( sfbonus_2c00_r )
	1097	READ8_MEMBER(sfbonus_state::sfbonus_2c00_r)
1087	1098	{
1088		return space->machine().rand();
	1099	return machine().rand();
1089	1100	}
1090	1101
1091		static READ8_HANDLER( sfbonus_2c01_r )
	1102	READ8_MEMBER(sfbonus_state::sfbonus_2c01_r)
1092	1103	{
1093		return space->machine().rand();
	1104	return machine().rand();
1094	1105	}
1095	1106
1096		static READ8_HANDLER( sfbonus_3800_r )
	1107	READ8_MEMBER(sfbonus_state::sfbonus_3800_r)
1097	1108	{
1098	1109	return 0xff;
1099	1110	}
1100	1111
1101	1112
1102	1113	// lamps and coin counters
1103		static WRITE8_HANDLER( sfbonus_1800_w )
	1114	WRITE8_MEMBER(sfbonus_state::sfbonus_1800_w)
1104	1115	{
1105		sfbonus_state *state = space->machine().driver_data<sfbonus_state>();
1106		state->m_1800_regs[offset] = data;
	1116	m_1800_regs[offset] = data;
1107	1117	}
1108	1118
1109		static WRITE8_HANDLER( sfbonus_3800_w )
	1119	WRITE8_MEMBER(sfbonus_state::sfbonus_3800_w)
1110	1120	{
1111		sfbonus_state *state = space->machine().driver_data<sfbonus_state>();
1112		state->m_3800_regs[offset] = data;
	1121	m_3800_regs[offset] = data;
1113	1122	}
1114	1123
1115		static WRITE8_HANDLER( sfbonus_3000_w )
	1124	WRITE8_MEMBER(sfbonus_state::sfbonus_3000_w)
1116	1125	{
1117		sfbonus_state *state = space->machine().driver_data<sfbonus_state>();
1118		state->m_3000_regs[offset] = data;
	1126	m_3000_regs[offset] = data;
1119	1127	}
1120	1128
1121		static WRITE8_HANDLER( sfbonus_2801_w )
	1129	WRITE8_MEMBER(sfbonus_state::sfbonus_2801_w)
1122	1130	{
1123		sfbonus_state *state = space->machine().driver_data<sfbonus_state>();
1124		state->m_2801_regs[offset] = data;
	1131	m_2801_regs[offset] = data;
1125	1132	}
1126	1133
1127		static WRITE8_HANDLER( sfbonus_2c01_w )
	1134	WRITE8_MEMBER(sfbonus_state::sfbonus_2c01_w)
1128	1135	{
1129		sfbonus_state *state = space->machine().driver_data<sfbonus_state>();
1130		state->m_2c01_regs[offset] = data;
	1136	m_2c01_regs[offset] = data;
1131	1137	}
1132	1138
1133	1139
r14845	r14846
1148	1154	AM_RANGE(0x0c01, 0x0c01) AM_DEVWRITE("ramdac", ramdac_device, pal_w)
1149	1155	AM_RANGE(0x0c02, 0x0c02) AM_DEVWRITE("ramdac", ramdac_device, mask_w)
1150	1156
1151		AM_RANGE(0x1800, 0x1807) AM_WRITE_LEGACY(sfbonus_1800_w) AM_BASE(m_1800_regs) // lamps and coin counters
	1157	AM_RANGE(0x1800, 0x1807) AM_WRITE(sfbonus_1800_w) AM_BASE(m_1800_regs) // lamps and coin counters
1152	1158
1153	1159	AM_RANGE(0x2400, 0x241f) AM_RAM AM_BASE(m_vregs)
1154	1160
1155		AM_RANGE(0x2800, 0x2800) AM_READ_LEGACY(sfbonus_2800_r)
1156		AM_RANGE(0x2801, 0x2801) AM_READ_LEGACY(sfbonus_2801_r) AM_WRITE_LEGACY(sfbonus_2801_w) AM_BASE(m_2801_regs)
	1161	AM_RANGE(0x2800, 0x2800) AM_READ(sfbonus_2800_r)
	1162	AM_RANGE(0x2801, 0x2801) AM_READ(sfbonus_2801_r) AM_WRITE(sfbonus_2801_w) AM_BASE(m_2801_regs)
1157	1163
1158		AM_RANGE(0x2c00, 0x2c00) AM_READ_LEGACY(sfbonus_2c00_r)
1159		AM_RANGE(0x2c01, 0x2c01) AM_READ_LEGACY(sfbonus_2c01_r) AM_WRITE_LEGACY(sfbonus_2c01_w) AM_BASE(m_2c01_regs)
	1164	AM_RANGE(0x2c00, 0x2c00) AM_READ(sfbonus_2c00_r)
	1165	AM_RANGE(0x2c01, 0x2c01) AM_READ(sfbonus_2c01_r) AM_WRITE(sfbonus_2c01_w) AM_BASE(m_2c01_regs)
1160	1166
1161		AM_RANGE(0x3000, 0x3000) AM_WRITE_LEGACY(sfbonus_3000_w) AM_BASE(m_3000_regs)
1162		AM_RANGE(0x3400, 0x3400) AM_WRITE_LEGACY(sfbonus_bank_w)
1163		AM_RANGE(0x3800, 0x3800) AM_READ_LEGACY(sfbonus_3800_r)
	1167	AM_RANGE(0x3000, 0x3000) AM_WRITE(sfbonus_3000_w) AM_BASE(m_3000_regs)
	1168	AM_RANGE(0x3400, 0x3400) AM_WRITE(sfbonus_bank_w)
	1169	AM_RANGE(0x3800, 0x3800) AM_READ(sfbonus_3800_r)
1164	1170
1165		AM_RANGE(0x3800, 0x3807) AM_WRITE_LEGACY(sfbonus_3800_w) AM_BASE(m_3800_regs)
	1171	AM_RANGE(0x3800, 0x3807) AM_WRITE(sfbonus_3800_w) AM_BASE(m_3800_regs)
1166	1172	ADDRESS_MAP_END
1167	1173
1168	1174

src/mame/drivers/tempest.c

r14845	r14846
289	289	: driver_device(mconfig, type, tag) { }
290	290
291	291	UINT8 m_player_select;
	292	DECLARE_WRITE8_MEMBER(wdclr_w);
	293	DECLARE_WRITE8_MEMBER(tempest_led_w);
	294	DECLARE_WRITE8_MEMBER(tempest_coin_w);
292	295	};
293	296
294	297
r14845	r14846
314	317	*
315	318	*************************************/
316	319
317		static WRITE8_HANDLER( wdclr_w )
	320	WRITE8_MEMBER(tempest_state::wdclr_w)
318	321	{
319		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
320		watchdog_reset(space->machine());
	322	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
	323	watchdog_reset(machine());
321	324	}
322	325
323	326	/*************************************
r14845	r14846
367	370	*
368	371	*************************************/
369	372
370		static WRITE8_HANDLER( tempest_led_w )
	373	WRITE8_MEMBER(tempest_state::tempest_led_w)
371	374	{
372		tempest_state *state = space->machine().driver_data<tempest_state>();
373		set_led_status(space->machine(), 0, ~data & 0x02);
374		set_led_status(space->machine(), 1, ~data & 0x01);
	375	set_led_status(machine(), 0, ~data & 0x02);
	376	set_led_status(machine(), 1, ~data & 0x01);
375	377	/* FLIP is bit 0x04 */
376		state->m_player_select = data & 0x04;
	378	m_player_select = data & 0x04;
377	379	}
378	380
379	381
380		static WRITE8_HANDLER( tempest_coin_w )
	382	WRITE8_MEMBER(tempest_state::tempest_coin_w)
381	383	{
382		coin_counter_w(space->machine(), 0, (data & 0x01));
383		coin_counter_w(space->machine(), 1, (data & 0x02));
384		coin_counter_w(space->machine(), 2, (data & 0x04));
	384	coin_counter_w(machine(), 0, (data & 0x01));
	385	coin_counter_w(machine(), 1, (data & 0x02));
	386	coin_counter_w(machine(), 2, (data & 0x04));
385	387	avg_set_flip_x(data & 0x08);
386	388	avg_set_flip_y(data & 0x10);
387	389	}
r14845	r14846
402	404	AM_RANGE(0x0e00, 0x0e00) AM_READ_PORT("DSW2")
403	405	AM_RANGE(0x2000, 0x2fff) AM_RAM AM_BASE_LEGACY(&avgdvg_vectorram) AM_SIZE_LEGACY(&avgdvg_vectorram_size) AM_REGION("maincpu", 0x2000)
404	406	AM_RANGE(0x3000, 0x3fff) AM_ROM
405		AM_RANGE(0x4000, 0x4000) AM_WRITE_LEGACY(tempest_coin_w)
	407	AM_RANGE(0x4000, 0x4000) AM_WRITE(tempest_coin_w)
406	408	AM_RANGE(0x4800, 0x4800) AM_WRITE_LEGACY(avgdvg_go_w)
407		AM_RANGE(0x5000, 0x5000) AM_WRITE_LEGACY(wdclr_w)
	409	AM_RANGE(0x5000, 0x5000) AM_WRITE(wdclr_w)
408	410	AM_RANGE(0x5800, 0x5800) AM_WRITE_LEGACY(avgdvg_reset_w)
409	411	AM_RANGE(0x6000, 0x603f) AM_DEVWRITE("earom", atari_vg_earom_device, write)
410	412	AM_RANGE(0x6040, 0x6040) AM_DEVREAD_LEGACY("mathbox", mathbox_status_r) AM_DEVWRITE("earom", atari_vg_earom_device, ctrl_w)
r14845	r14846
414	416	AM_RANGE(0x6080, 0x609f) AM_DEVWRITE_LEGACY("mathbox", mathbox_go_w)
415	417	AM_RANGE(0x60c0, 0x60cf) AM_DEVREADWRITE_LEGACY("pokey1", pokey_r, pokey_w)
416	418	AM_RANGE(0x60d0, 0x60df) AM_DEVREADWRITE_LEGACY("pokey2", pokey_r, pokey_w)
417		AM_RANGE(0x60e0, 0x60e0) AM_WRITE_LEGACY(tempest_led_w)
	419	AM_RANGE(0x60e0, 0x60e0) AM_WRITE(tempest_led_w)
418	420	AM_RANGE(0x9000, 0xdfff) AM_ROM
419	421	AM_RANGE(0xf000, 0xffff) AM_ROM   /* for the reset / interrupt vectors */
420	422	ADDRESS_MAP_END

src/mame/drivers/crystal.c

r14845	r14846
157	157	device_t *m_maincpu;
158	158	device_t *m_ds1302;
159	159	device_t *m_vr0video;
	160	DECLARE_READ32_MEMBER(FlipCount_r);
	161	DECLARE_WRITE32_MEMBER(FlipCount_w);
	162	DECLARE_READ32_MEMBER(Input_r);
	163	DECLARE_WRITE32_MEMBER(IntAck_w);
	164	DECLARE_WRITE32_MEMBER(Banksw_w);
	165	DECLARE_WRITE32_MEMBER(Timer0_w);
	166	DECLARE_READ32_MEMBER(Timer0_r);
	167	DECLARE_WRITE32_MEMBER(Timer1_w);
	168	DECLARE_READ32_MEMBER(Timer1_r);
	169	DECLARE_WRITE32_MEMBER(Timer2_w);
	170	DECLARE_READ32_MEMBER(Timer2_r);
	171	DECLARE_WRITE32_MEMBER(Timer3_w);
	172	DECLARE_READ32_MEMBER(Timer3_r);
	173	DECLARE_READ32_MEMBER(FlashCmd_r);
	174	DECLARE_WRITE32_MEMBER(FlashCmd_w);
	175	DECLARE_READ32_MEMBER(PIO_r);
	176	DECLARE_WRITE32_MEMBER(PIO_w);
	177	DECLARE_READ32_MEMBER(DMA0_r);
	178	DECLARE_WRITE32_MEMBER(DMA0_w);
	179	DECLARE_READ32_MEMBER(DMA1_r);
	180	DECLARE_WRITE32_MEMBER(DMA1_w);
160	181	};
161	182
162	183	static void IntReq( running_machine &machine, int num )
r14845	r14846
177	198	#endif
178	199	}
179	200
180		static READ32_HANDLER( FlipCount_r )
	201	READ32_MEMBER(crystal_state::FlipCount_r)
181	202	{
182		crystal_state *state = space->machine().driver_data<crystal_state>();
183	203
184	204	#ifdef IDLE_LOOP_SPEEDUP
185		UINT32 IntPend = space->read_dword(0x01800c0c);
186		state->m_FlipCntRead++;
187		if (state->m_FlipCntRead >= 16 && !IntPend && state->m_FlipCount != 0)
188		device_suspend(state->m_maincpu, SUSPEND_REASON_SPIN, 1);
	205	UINT32 IntPend = space.read_dword(0x01800c0c);
	206	m_FlipCntRead++;
	207	if (m_FlipCntRead >= 16 && !IntPend && m_FlipCount != 0)
	208	device_suspend(m_maincpu, SUSPEND_REASON_SPIN, 1);
189	209	#endif
190		return ((UINT32) state->m_FlipCount) << 16;
	210	return ((UINT32) m_FlipCount) << 16;
191	211	}
192	212
193		static WRITE32_HANDLER( FlipCount_w )
	213	WRITE32_MEMBER(crystal_state::FlipCount_w)
194	214	{
195		crystal_state *state = space->machine().driver_data<crystal_state>();
196	215
197	216	if (mem_mask & 0x00ff0000)
198	217	{
199	218	int fc = (data >> 16) & 0xff;
200	219	if (fc == 1)
201		state->m_FlipCount++;
	220	m_FlipCount++;
202	221	else if (fc == 0)
203		state->m_FlipCount = 0;
	222	m_FlipCount = 0;
204	223	}
205	224	}
206	225
207		static READ32_HANDLER( Input_r )
	226	READ32_MEMBER(crystal_state::Input_r)
208	227	{
209		crystal_state *state = space->machine().driver_data<crystal_state>();
210	228
211	229	if (offset == 0)
212		return input_port_read(space->machine(), "P1_P2");
	230	return input_port_read(machine(), "P1_P2");
213	231	else if (offset == 1)
214		return input_port_read(space->machine(), "P3_P4");
	232	return input_port_read(machine(), "P3_P4");
215	233	else if( offset == 2)
216	234	{
217		UINT8 Port4 = input_port_read(space->machine(), "SYSTEM");
218		if (!(Port4 & 0x10) && ((state->m_OldPort4 ^ Port4) & 0x10))   //coin buttons trigger IRQs
219		IntReq(space->machine(), 12);
220		if (!(Port4 & 0x20) && ((state->m_OldPort4 ^ Port4) & 0x20))
221		IntReq(space->machine(), 19);
222		state->m_OldPort4 = Port4;
223		return /*dips*/input_port_read(space->machine(), "DSW") | (Port4 << 16);
	235	UINT8 Port4 = input_port_read(machine(), "SYSTEM");
	236	if (!(Port4 & 0x10) && ((m_OldPort4 ^ Port4) & 0x10))   //coin buttons trigger IRQs
	237	IntReq(machine(), 12);
	238	if (!(Port4 & 0x20) && ((m_OldPort4 ^ Port4) & 0x20))
	239	IntReq(machine(), 19);
	240	m_OldPort4 = Port4;
	241	return /*dips*/input_port_read(machine(), "DSW") | (Port4 << 16);
224	242	}
225	243	return 0;
226	244	}
227	245
228		static WRITE32_HANDLER( IntAck_w )
	246	WRITE32_MEMBER(crystal_state::IntAck_w)
229	247	{
230		crystal_state *state = space->machine().driver_data<crystal_state>();
231		UINT32 IntPend = space->read_dword(0x01800c0c);
	248	UINT32 IntPend = space.read_dword(0x01800c0c);
232	249
233	250	if (mem_mask & 0xff)
234	251	{
235	252	IntPend &= ~(1 << (data & 0x1f));
236		space->write_dword(0x01800c0c, IntPend);
	253	space.write_dword(0x01800c0c, IntPend);
237	254	if (!IntPend)
238		device_set_input_line(state->m_maincpu, SE3208_INT, CLEAR_LINE);
	255	device_set_input_line(m_maincpu, SE3208_INT, CLEAR_LINE);
239	256	}
240	257	if (mem_mask & 0xff00)
241		state->m_IntHigh = (data >> 8) & 7;
	258	m_IntHigh = (data >> 8) & 7;
242	259	}
243	260
244	261	static IRQ_CALLBACK( icallback )
r14845	r14846
258	275	return 0;      //This should never happen
259	276	}
260	277
261		static WRITE32_HANDLER( Banksw_w )
	278	WRITE32_MEMBER(crystal_state::Banksw_w)
262	279	{
263		crystal_state *state = space->machine().driver_data<crystal_state>();
264	280
265		state->m_Bank = (data >> 1) & 7;
266		if (state->m_Bank <= 2)
267		memory_set_bankptr(space->machine(), "bank1", space->machine().region("user1")->base() + state->m_Bank * 0x1000000);
	281	m_Bank = (data >> 1) & 7;
	282	if (m_Bank <= 2)
	283	memory_set_bankptr(machine(), "bank1", machine().region("user1")->base() + m_Bank * 0x1000000);
268	284	else
269		memory_set_bankptr(space->machine(), "bank1", space->machine().region("user2")->base());
	285	memory_set_bankptr(machine(), "bank1", machine().region("user2")->base());
270	286	}
271	287
272	288	static TIMER_CALLBACK( Timercb )
r14845	r14846
299	315	COMBINE_DATA(&state->m_Timerctrl[which]);
300	316	}
301	317
302		static WRITE32_HANDLER( Timer0_w )
	318	WRITE32_MEMBER(crystal_state::Timer0_w)
303	319	{
304		Timer_w(space, 0, data, mem_mask);
	320	Timer_w(&space, 0, data, mem_mask);
305	321	}
306	322
307		static READ32_HANDLER( Timer0_r )
	323	READ32_MEMBER(crystal_state::Timer0_r)
308	324	{
309		crystal_state *state = space->machine().driver_data<crystal_state>();
310		return state->m_Timerctrl[0];
	325	return m_Timerctrl[0];
311	326	}
312	327
313		static WRITE32_HANDLER( Timer1_w )
	328	WRITE32_MEMBER(crystal_state::Timer1_w)
314	329	{
315		Timer_w(space, 1, data, mem_mask);
	330	Timer_w(&space, 1, data, mem_mask);
316	331	}
317	332
318		static READ32_HANDLER( Timer1_r )
	333	READ32_MEMBER(crystal_state::Timer1_r)
319	334	{
320		crystal_state *state = space->machine().driver_data<crystal_state>();
321		return state->m_Timerctrl[1];
	335	return m_Timerctrl[1];
322	336	}
323	337
324		static WRITE32_HANDLER( Timer2_w )
	338	WRITE32_MEMBER(crystal_state::Timer2_w)
325	339	{
326		Timer_w(space, 2, data, mem_mask);
	340	Timer_w(&space, 2, data, mem_mask);
327	341	}
328	342
329		static READ32_HANDLER( Timer2_r )
	343	READ32_MEMBER(crystal_state::Timer2_r)
330	344	{
331		crystal_state *state = space->machine().driver_data<crystal_state>();
332		return state->m_Timerctrl[2];
	345	return m_Timerctrl[2];
333	346	}
334	347
335		static WRITE32_HANDLER( Timer3_w )
	348	WRITE32_MEMBER(crystal_state::Timer3_w)
336	349	{
337		Timer_w(space, 3, data, mem_mask);
	350	Timer_w(&space, 3, data, mem_mask);
338	351	}
339	352
340		static READ32_HANDLER( Timer3_r )
	353	READ32_MEMBER(crystal_state::Timer3_r)
341	354	{
342		crystal_state *state = space->machine().driver_data<crystal_state>();
343		return state->m_Timerctrl[3];
	355	return m_Timerctrl[3];
344	356	}
345	357
346		static READ32_HANDLER( FlashCmd_r )
	358	READ32_MEMBER(crystal_state::FlashCmd_r)
347	359	{
348		crystal_state *state = space->machine().driver_data<crystal_state>();
349	360
350		if ((state->m_FlashCmd & 0xff) == 0xff)
	361	if ((m_FlashCmd & 0xff) == 0xff)
351	362	{
352		if (state->m_Bank <= 2)
	363	if (m_Bank <= 2)
353	364	{
354		UINT32 *ptr = (UINT32*)(space->machine().region("user1")->base() + state->m_Bank * 0x1000000);
	365	UINT32 *ptr = (UINT32*)(machine().region("user1")->base() + m_Bank * 0x1000000);
355	366	return ptr[0];
356	367	}
357	368	else
358	369	return 0xffffffff;
359	370	}
360		if ((state->m_FlashCmd & 0xff) == 0x90)
	371	if ((m_FlashCmd & 0xff) == 0x90)
361	372	{
362		if (state->m_Bank <= 2)
	373	if (m_Bank <= 2)
363	374	return 0x00180089;   //Intel 128MBit
364	375	else
365	376	return 0xffffffff;
r14845	r14846
367	378	return 0;
368	379	}
369	380
370		static WRITE32_HANDLER( FlashCmd_w )
	381	WRITE32_MEMBER(crystal_state::FlashCmd_w)
371	382	{
372		crystal_state *state = space->machine().driver_data<crystal_state>();
373		state->m_FlashCmd = data;
	383	m_FlashCmd = data;
374	384	}
375	385
376		static READ32_HANDLER( PIO_r )
	386	READ32_MEMBER(crystal_state::PIO_r)
377	387	{
378		crystal_state *state = space->machine().driver_data<crystal_state>();
379		return state->m_PIO;
	388	return m_PIO;
380	389	}
381	390
382		static WRITE32_HANDLER( PIO_w )
	391	WRITE32_MEMBER(crystal_state::PIO_w)
383	392	{
384		crystal_state *state = space->machine().driver_data<crystal_state>();
385	393	UINT32 RST = data & 0x01000000;
386	394	UINT32 CLK = data & 0x02000000;
387	395	UINT32 DAT = data & 0x10000000;
388	396
389	397	if (!RST)
390		state->m_ds1302->reset();
	398	m_ds1302->reset();
391	399
392		ds1302_dat_w(state->m_ds1302, 0, DAT ? 1 : 0);
393		ds1302_clk_w(state->m_ds1302, 0, CLK ? 1 : 0);
	400	ds1302_dat_w(m_ds1302, 0, DAT ? 1 : 0);
	401	ds1302_clk_w(m_ds1302, 0, CLK ? 1 : 0);
394	402
395		if (ds1302_read(state->m_ds1302, 0))
396		space->write_dword(0x01802008, space->read_dword(0x01802008) | 0x10000000);
	403	if (ds1302_read(m_ds1302, 0))
	404	space.write_dword(0x01802008, space.read_dword(0x01802008) | 0x10000000);
397	405	else
398		space->write_dword(0x01802008, space->read_dword(0x01802008) & (~0x10000000));
	406	space.write_dword(0x01802008, space.read_dword(0x01802008) & (~0x10000000));
399	407
400		COMBINE_DATA(&state->m_PIO);
	408	COMBINE_DATA(&m_PIO);
401	409	}
402	410
403	411	INLINE void DMA_w( address_space *space, int which, UINT32 data, UINT32 mem_mask )
r14845	r14846
443	451	COMBINE_DATA(&state->m_DMActrl[which]);
444	452	}
445	453
446		static READ32_HANDLER( DMA0_r )
	454	READ32_MEMBER(crystal_state::DMA0_r)
447	455	{
448		crystal_state *state = space->machine().driver_data<crystal_state>();
449		return state->m_DMActrl[0];
	456	return m_DMActrl[0];
450	457	}
451	458
452		static WRITE32_HANDLER( DMA0_w )
	459	WRITE32_MEMBER(crystal_state::DMA0_w)
453	460	{
454		DMA_w(space, 0, data, mem_mask);
	461	DMA_w(&space, 0, data, mem_mask);
455	462	}
456	463
457		static READ32_HANDLER( DMA1_r )
	464	READ32_MEMBER(crystal_state::DMA1_r)
458	465	{
459		crystal_state *state = space->machine().driver_data<crystal_state>();
460		return state->m_DMActrl[1];
	466	return m_DMActrl[1];
461	467	}
462	468
463		static WRITE32_HANDLER( DMA1_w )
	469	WRITE32_MEMBER(crystal_state::DMA1_w)
464	470	{
465		DMA_w(space, 1, data, mem_mask);
	471	DMA_w(&space, 1, data, mem_mask);
466	472	}
467	473
468	474
469	475	static ADDRESS_MAP_START( crystal_mem, AS_PROGRAM, 32, crystal_state )
470	476	AM_RANGE(0x00000000, 0x0001ffff) AM_ROM AM_WRITENOP
471	477
472		AM_RANGE(0x01200000, 0x0120000f) AM_READ_LEGACY(Input_r)
473		AM_RANGE(0x01280000, 0x01280003) AM_WRITE_LEGACY(Banksw_w)
	478	AM_RANGE(0x01200000, 0x0120000f) AM_READ(Input_r)
	479	AM_RANGE(0x01280000, 0x01280003) AM_WRITE(Banksw_w)
474	480	AM_RANGE(0x01400000, 0x0140ffff) AM_RAM AM_SHARE("nvram")
475	481
476		AM_RANGE(0x01801400, 0x01801403) AM_READWRITE_LEGACY(Timer0_r, Timer0_w)
477		AM_RANGE(0x01801408, 0x0180140b) AM_READWRITE_LEGACY(Timer1_r, Timer1_w)
478		AM_RANGE(0x01801410, 0x01801413) AM_READWRITE_LEGACY(Timer2_r, Timer2_w)
479		AM_RANGE(0x01801418, 0x0180141b) AM_READWRITE_LEGACY(Timer3_r, Timer3_w)
480		AM_RANGE(0x01802004, 0x01802007) AM_READWRITE_LEGACY(PIO_r, PIO_w)
	482	AM_RANGE(0x01801400, 0x01801403) AM_READWRITE(Timer0_r, Timer0_w)
	483	AM_RANGE(0x01801408, 0x0180140b) AM_READWRITE(Timer1_r, Timer1_w)
	484	AM_RANGE(0x01801410, 0x01801413) AM_READWRITE(Timer2_r, Timer2_w)
	485	AM_RANGE(0x01801418, 0x0180141b) AM_READWRITE(Timer3_r, Timer3_w)
	486	AM_RANGE(0x01802004, 0x01802007) AM_READWRITE(PIO_r, PIO_w)
481	487
482		AM_RANGE(0x01800800, 0x01800803) AM_READWRITE_LEGACY(DMA0_r, DMA0_w)
483		AM_RANGE(0x01800810, 0x01800813) AM_READWRITE_LEGACY(DMA1_r, DMA1_w)
	488	AM_RANGE(0x01800800, 0x01800803) AM_READWRITE(DMA0_r, DMA0_w)
	489	AM_RANGE(0x01800810, 0x01800813) AM_READWRITE(DMA1_r, DMA1_w)
484	490
485		AM_RANGE(0x01800c04, 0x01800c07) AM_WRITE_LEGACY(IntAck_w)
	491	AM_RANGE(0x01800c04, 0x01800c07) AM_WRITE(IntAck_w)
486	492	AM_RANGE(0x01800000, 0x0180ffff) AM_RAM AM_BASE(m_sysregs)
487	493	AM_RANGE(0x02000000, 0x027fffff) AM_RAM AM_BASE(m_workram)
488	494
489		AM_RANGE(0x030000a4, 0x030000a7) AM_READWRITE_LEGACY(FlipCount_r, FlipCount_w)
	495	AM_RANGE(0x030000a4, 0x030000a7) AM_READWRITE(FlipCount_r, FlipCount_w)
490	496
491	497	AM_RANGE(0x03000000, 0x0300ffff) AM_RAM AM_BASE(m_vidregs)
492	498	AM_RANGE(0x03800000, 0x03ffffff) AM_RAM AM_BASE(m_textureram)
493	499	AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_BASE(m_frameram)
494	500	AM_RANGE(0x04800000, 0x04800fff) AM_DEVREADWRITE_LEGACY("vrender", vr0_snd_read, vr0_snd_write)
495	501
496		AM_RANGE(0x05000000, 0x05000003) AM_READWRITE_LEGACY(FlashCmd_r, FlashCmd_w)
	502	AM_RANGE(0x05000000, 0x05000003) AM_READWRITE(FlashCmd_r, FlashCmd_w)
497	503	AM_RANGE(0x05000000, 0x05ffffff) AM_ROMBANK("bank1")
498	504
499	505	AM_RANGE(0x44414F4C, 0x44414F7F) AM_RAM AM_BASE(m_ResetPatch)

src/mame/drivers/chinsan.c

r14845	r14846
62	62	UINT8    m_adpcm_idle;
63	63	UINT8    m_adpcm_data;
64	64	UINT8    m_trigger;
	65	DECLARE_WRITE8_MEMBER(ctrl_w);
	66	DECLARE_WRITE8_MEMBER(chinsan_port00_w);
	67	DECLARE_READ8_MEMBER(chinsan_input_port_0_r);
	68	DECLARE_READ8_MEMBER(chinsan_input_port_1_r);
65	69	};
66	70
67	71
r14845	r14846
112	116	*
113	117	*************************************/
114	118
115		static WRITE8_HANDLER( ctrl_w )
	119	WRITE8_MEMBER(chinsan_state::ctrl_w)
116	120	{
117		memory_set_bank(space->machine(), "bank1", data >> 6);
	121	memory_set_bank(machine(), "bank1", data >> 6);
118	122	}
119	123
120	124	static WRITE8_DEVICE_HANDLER( ym_port_w1 )
r14845	r14846
141	145	},
142	146	};
143	147
144		static WRITE8_HANDLER( chinsan_port00_w )
	148	WRITE8_MEMBER(chinsan_state::chinsan_port00_w)
145	149	{
146		chinsan_state *state = space->machine().driver_data<chinsan_state>();
147	150
148		state->m_port_select = data;
	151	m_port_select = data;
149	152
150	153	if (
151	154	(data != 0x40) &&
r14845	r14846
159	162
160	163	}
161	164
162		static READ8_HANDLER( chinsan_input_port_0_r )
	165	READ8_MEMBER(chinsan_state::chinsan_input_port_0_r)
163	166	{
164		chinsan_state *state = space->machine().driver_data<chinsan_state>();
165	167
166	168	//return 0xff; // the inputs don't seem to work, so just return ff for now
167	169
168		switch (state->m_port_select)
	170	switch (m_port_select)
169	171	{
170	172	/* i doubt these are both really the same.. */
171	173	case 0x40:
172	174	case 0x4f:
173		return input_port_read(space->machine(), "MAHJONG_P2_1");
	175	return input_port_read(machine(), "MAHJONG_P2_1");
174	176
175	177	case 0x53:
176		return input_port_read(space->machine(), "MAHJONG_P2_2");
	178	return input_port_read(machine(), "MAHJONG_P2_2");
177	179
178	180	case 0x57:
179		return input_port_read(space->machine(), "MAHJONG_P2_3");
	181	return input_port_read(machine(), "MAHJONG_P2_3");
180	182
181	183	case 0x5b:
182		return input_port_read(space->machine(), "MAHJONG_P2_4");
	184	return input_port_read(machine(), "MAHJONG_P2_4");
183	185
184	186	case 0x5d:
185		return input_port_read(space->machine(), "MAHJONG_P2_5");
	187	return input_port_read(machine(), "MAHJONG_P2_5");
186	188
187	189	case 0x5e:
188		return input_port_read(space->machine(), "MAHJONG_P2_6");
	190	return input_port_read(machine(), "MAHJONG_P2_6");
189	191	}
190	192
191		printf("chinsan_input_port_0_r unk_r %02x\n", state->m_port_select);
192		return space->machine().rand();
	193	printf("chinsan_input_port_0_r unk_r %02x\n", m_port_select);
	194	return machine().rand();
193	195	}
194	196
195		static READ8_HANDLER( chinsan_input_port_1_r )
	197	READ8_MEMBER(chinsan_state::chinsan_input_port_1_r)
196	198	{
197		chinsan_state *state = space->machine().driver_data<chinsan_state>();
198	199
199		switch (state->m_port_select)
	200	switch (m_port_select)
200	201	{
201	202	/* i doubt these are both really the same.. */
202	203	case 0x40:
203	204	case 0x4f:
204		return input_port_read(space->machine(), "MAHJONG_P1_1");
	205	return input_port_read(machine(), "MAHJONG_P1_1");
205	206
206	207	case 0x53:
207		return input_port_read(space->machine(), "MAHJONG_P1_2");
	208	return input_port_read(machine(), "MAHJONG_P1_2");
208	209
209	210	case 0x57:
210		return input_port_read(space->machine(), "MAHJONG_P1_3");
	211	return input_port_read(machine(), "MAHJONG_P1_3");
211	212
212	213	case 0x5b:
213		return input_port_read(space->machine(), "MAHJONG_P1_4");
	214	return input_port_read(machine(), "MAHJONG_P1_4");
214	215
215	216	case 0x5d:
216		return input_port_read(space->machine(), "MAHJONG_P1_5");
	217	return input_port_read(machine(), "MAHJONG_P1_5");
217	218
218	219	case 0x5e:
219		return input_port_read(space->machine(), "MAHJONG_P1_6");
	220	return input_port_read(machine(), "MAHJONG_P1_6");
220	221	}
221	222
222		printf("chinsan_input_port_1_r unk_r %02x\n", state->m_port_select);
223		return space->machine().rand();
	223	printf("chinsan_input_port_1_r unk_r %02x\n", m_port_select);
	224	return machine().rand();
224	225	}
225	226
226	227	static WRITE8_DEVICE_HANDLER( chin_adpcm_w )
r14845	r14846
246	247
247	248	static ADDRESS_MAP_START( chinsan_io, AS_IO, 8, chinsan_state )
248	249	ADDRESS_MAP_GLOBAL_MASK(0xff)
249		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(chinsan_port00_w)
250		AM_RANGE(0x01, 0x01) AM_READ_LEGACY(chinsan_input_port_0_r)
251		AM_RANGE(0x02, 0x02) AM_READ_LEGACY(chinsan_input_port_1_r)
	250	AM_RANGE(0x00, 0x00) AM_WRITE(chinsan_port00_w)
	251	AM_RANGE(0x01, 0x01) AM_READ(chinsan_input_port_0_r)
	252	AM_RANGE(0x02, 0x02) AM_READ(chinsan_input_port_1_r)
252	253	AM_RANGE(0x10, 0x11) AM_DEVREADWRITE_LEGACY("ymsnd", ym2203_r, ym2203_w)
253	254	AM_RANGE(0x20, 0x20) AM_DEVWRITE_LEGACY("adpcm", chin_adpcm_w)
254		AM_RANGE(0x30, 0x30) AM_WRITE_LEGACY(ctrl_w)   // ROM bank + unknown stuff (input mutliplex?)
	255	AM_RANGE(0x30, 0x30) AM_WRITE(ctrl_w)   // ROM bank + unknown stuff (input mutliplex?)
255	256	ADDRESS_MAP_END
256	257
257	258

src/mame/drivers/famibox.c

r14845	r14846
91	91	emu_timer*   m_gameplay_timer;
92	92	UINT8      m_money_reg;
93	93
	94	DECLARE_WRITE8_MEMBER(famibox_nt_w);
	95	DECLARE_READ8_MEMBER(famibox_nt_r);
	96	DECLARE_WRITE8_MEMBER(sprite_dma_w);
	97	DECLARE_READ8_MEMBER(famibox_IN0_r);
	98	DECLARE_WRITE8_MEMBER(famibox_IN0_w);
	99	DECLARE_READ8_MEMBER(famibox_IN1_r);
	100	DECLARE_READ8_MEMBER(famibox_system_r);
	101	DECLARE_WRITE8_MEMBER(famibox_system_w);
94	102	};
95	103
96	104	/******************************************************
r14845	r14846
133	141	}
134	142	#endif
135	143
136		static WRITE8_HANDLER (famibox_nt_w)
	144	WRITE8_MEMBER(famibox_state::famibox_nt_w)
137	145	{
138		famibox_state *state = space->machine().driver_data<famibox_state>();
139	146	int page = ((offset & 0xc00) >> 10);
140		state->m_nt_page[page][offset & 0x3ff] = data;
	147	m_nt_page[page][offset & 0x3ff] = data;
141	148	}
142	149
143	150
144		static READ8_HANDLER (famibox_nt_r)
	151	READ8_MEMBER(famibox_state::famibox_nt_r)
145	152	{
146		famibox_state *state = space->machine().driver_data<famibox_state>();
147	153	int page = ((offset & 0xc00) >> 10);
148		return state->m_nt_page[page][offset & 0x3ff];
	154	return m_nt_page[page][offset & 0x3ff];
149	155	}
150	156
151	157	/******************************************************
r14845	r14846
154	160
155	161	*******************************************************/
156	162
157		static WRITE8_HANDLER( sprite_dma_w )
	163	WRITE8_MEMBER(famibox_state::sprite_dma_w)
158	164	{
159		ppu2c0x_device *ppu = space->machine().device<ppu2c0x_device>("ppu");
	165	ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
160	166	int source = (data & 7);
161		ppu->spriteram_dma(space, source);
	167	ppu->spriteram_dma(&space, source);
162	168	}
163	169
164	170	static READ8_DEVICE_HANDLER( psg_4015_r )
r14845	r14846
183	189	*******************************************************/
184	190
185	191
186		static READ8_HANDLER( famibox_IN0_r )
	192	READ8_MEMBER(famibox_state::famibox_IN0_r)
187	193	{
188		famibox_state *state = space->machine().driver_data<famibox_state>();
189		return ((state->m_in_0 >> state->m_in_0_shift++) & 0x01) | 0x40;
	194	return ((m_in_0 >> m_in_0_shift++) & 0x01) | 0x40;
190	195	}
191	196
192		static WRITE8_HANDLER( famibox_IN0_w )
	197	WRITE8_MEMBER(famibox_state::famibox_IN0_w)
193	198	{
194		famibox_state *state = space->machine().driver_data<famibox_state>();
195	199	if (data & 0x01)
196	200	{
197	201	return;
198	202	}
199	203
200		state->m_in_0_shift = 0;
201		state->m_in_1_shift = 0;
	204	m_in_0_shift = 0;
	205	m_in_1_shift = 0;
202	206
203		state->m_in_0 = input_port_read(space->machine(), "P1");
204		state->m_in_1 = input_port_read(space->machine(), "P2");
	207	m_in_0 = input_port_read(machine(), "P1");
	208	m_in_1 = input_port_read(machine(), "P2");
205	209	}
206	210
207		static READ8_HANDLER( famibox_IN1_r )
	211	READ8_MEMBER(famibox_state::famibox_IN1_r)
208	212	{
209		famibox_state *state = space->machine().driver_data<famibox_state>();
210		return ((state->m_in_1 >> state->m_in_1_shift++) & 0x01) | 0x40;
	213	return ((m_in_1 >> m_in_1_shift++) & 0x01) | 0x40;
211	214	}
212	215
213	216	/******************************************************
r14845	r14846
295	298	}
296	299	}
297	300
298		static READ8_HANDLER( famibox_system_r )
	301	READ8_MEMBER(famibox_state::famibox_system_r)
299	302	{
300		famibox_state *state = space->machine().driver_data<famibox_state>();
301	303	switch( offset & 0x07 )
302	304	{
303	305	case 0: /* device which caused exception */
304	306	{
305		UINT8 ret = state->m_exception_cause;
306		state->m_exception_cause = 0xff;
	307	UINT8 ret = m_exception_cause;
	308	m_exception_cause = 0xff;
307	309	return ret;
308	310	}
309	311	case 2:
310		return input_port_read(space->machine(), "DSW");
	312	return input_port_read(machine(), "DSW");
311	313	case 3:
312		return input_port_read(space->machine(), "KEYSWITCH");
	314	return input_port_read(machine(), "KEYSWITCH");
313	315	case 7:
314	316	return 0x02;
315	317	default:
316		logerror("%s: Unhandled famibox_system_r(%x)\n", space->machine().describe_context(), offset );
	318	logerror("%s: Unhandled famibox_system_r(%x)\n", machine().describe_context(), offset );
317	319	return 0;
318	320	}
319	321	}
320	322
321		static WRITE8_HANDLER( famibox_system_w )
	323	WRITE8_MEMBER(famibox_state::famibox_system_w)
322	324	{
323		famibox_state *state = space->machine().driver_data<famibox_state>();
324	325	switch( offset & 0x07 )
325	326	{
326	327	case 0:
327		logerror("%s: Interrupt enable\n", space->machine().describe_context());
	328	logerror("%s: Interrupt enable\n", machine().describe_context());
328	329	logerror("6.82Hz interrupt source (0 = enable): %d\n", BIT(data,0));
329	330	logerror("8 bit timer expiration @ 5003W (1 = enable): %d\n", BIT(data,1));
330	331	logerror("controller reads (1 = enable): %d\n", BIT(data,2));
r14845	r14846
332	333	logerror("money insertion (1 = enable): %d\n", BIT(data,4));
333	334	logerror("reset button (1 = enable): %d\n", BIT(data,5));
334	335	logerror("\"CATV connector\" pin 4 detection (1 = enable): %d\n", BIT(data,7));
335		state->m_exception_mask = data;
336		if ( BIT(state->m_exception_mask,1) && ( state->m_attract_timer_period != 0 ) )
	336	m_exception_mask = data;
	337	if ( BIT(m_exception_mask,1) && ( m_attract_timer_period != 0 ) )
337	338	{
338		if (state->m_attract_timer->start() != attotime::never)
	339	if (m_attract_timer->start() != attotime::never)
339	340	{
340		state->m_attract_timer->adjust(attotime::from_seconds((INT32)((double)1.0/6.8274*state->m_attract_timer_period)), 0, attotime::never);
	341	m_attract_timer->adjust(attotime::from_seconds((INT32)((double)1.0/6.8274*m_attract_timer_period)), 0, attotime::never);
341	342	}
342	343	}
343	344	break;
344	345	case 1:
345		state->m_money_reg = data;
346		logerror("%s: Money handling register: %02x\n", space->machine().describe_context(), data);
	346	m_money_reg = data;
	347	logerror("%s: Money handling register: %02x\n", machine().describe_context(), data);
347	348	break;
348	349	case 2:
349		logerror("%s: LED & memory protect register: %02x\n", space->machine().describe_context(), data);
	350	logerror("%s: LED & memory protect register: %02x\n", machine().describe_context(), data);
350	351	break;
351	352	case 3:
352		logerror("%s: 8 bit down counter, for attract mode timing: %02x\n", space->machine().describe_context(), data);
353		state->m_attract_timer_period = data;
354		if ( BIT(state->m_exception_mask,1) && ( data != 0 ) )
	353	logerror("%s: 8 bit down counter, for attract mode timing: %02x\n", machine().describe_context(), data);
	354	m_attract_timer_period = data;
	355	if ( BIT(m_exception_mask,1) && ( data != 0 ) )
355	356	{
356		state->m_attract_timer->adjust(attotime::from_hz(6.8274/state->m_attract_timer_period), 0, attotime::never);
	357	m_attract_timer->adjust(attotime::from_hz(6.8274/m_attract_timer_period), 0, attotime::never);
357	358	}
358	359	break;
359	360	case 4:
360		logerror("%s: bankswitch %x\n", space->machine().describe_context(), data );
361		famicombox_bankswitch(space->machine(), data & 0x3f);
	361	logerror("%s: bankswitch %x\n", machine().describe_context(), data );
	362	famicombox_bankswitch(machine(), data & 0x3f);
362	363	break;
363	364	default:
364		logerror("%s: Unhandled famibox_system_w(%x,%02x)\n", space->machine().describe_context(), offset, data );
	365	logerror("%s: Unhandled famibox_system_w(%x,%02x)\n", machine().describe_context(), offset, data );
365	366	}
366	367	}
367	368
r14845	r14846
376	377	AM_RANGE(0x0000, 0x1fff) AM_RAM
377	378	AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu", ppu2c0x_device, read, write)
378	379	AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes", nes_psg_r, nes_psg_w)         /* PSG primary registers */
379		AM_RANGE(0x4014, 0x4014) AM_WRITE_LEGACY(sprite_dma_w)
	380	AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_w)
380	381	AM_RANGE(0x4015, 0x4015) AM_DEVREADWRITE_LEGACY("nes", psg_4015_r, psg_4015_w)         /* PSG status / first control register */
381		AM_RANGE(0x4016, 0x4016) AM_READWRITE_LEGACY(famibox_IN0_r, famibox_IN0_w)   /* IN0 - input port 1 */
382		AM_RANGE(0x4017, 0x4017) AM_READ_LEGACY(famibox_IN1_r) AM_DEVWRITE_LEGACY("nes", psg_4017_w)      /* IN1 - input port 2 / PSG second control register */
383		AM_RANGE(0x5000, 0x5fff) AM_READWRITE_LEGACY(famibox_system_r, famibox_system_w)
	382	AM_RANGE(0x4016, 0x4016) AM_READWRITE(famibox_IN0_r, famibox_IN0_w)   /* IN0 - input port 1 */
	383	AM_RANGE(0x4017, 0x4017) AM_READ(famibox_IN1_r) AM_DEVWRITE_LEGACY("nes", psg_4017_w)      /* IN1 - input port 2 / PSG second control register */
	384	AM_RANGE(0x5000, 0x5fff) AM_READWRITE(famibox_system_r, famibox_system_w)
384	385	AM_RANGE(0x6000, 0x7fff) AM_RAM
385	386	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("cpubank1")
386	387	AM_RANGE(0xc000, 0xffff) AM_ROMBANK("cpubank2")
r14845	r14846
553	554	state->m_nt_page[2] = state->m_nt_ram + 0x800;
554	555	state->m_nt_page[3] = state->m_nt_ram + 0xc00;
555	556
556		machine.device("ppu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0x2000, 0x3eff, FUNC(famibox_nt_r), FUNC(famibox_nt_w));
	557	machine.device("ppu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(famibox_state::famibox_nt_r), state), write8_delegate(FUNC(famibox_state::famibox_nt_w), state));
557	558	machine.device("ppu")->memory().space(AS_PROGRAM)->install_read_bank(0x0000, 0x1fff, "ppubank1");
558	559
559	560	famicombox_bankswitch(machine, 0);

src/mame/drivers/cshooter.c

r14845	r14846
101	101	int m_counter;
102	102	UINT8 *m_spriteram;
103	103	size_t m_spriteram_size;
	104	DECLARE_WRITE8_MEMBER(cshooter_txram_w);
	105	DECLARE_READ8_MEMBER(cshooter_coin_r);
	106	DECLARE_WRITE8_MEMBER(cshooter_c500_w);
	107	DECLARE_WRITE8_MEMBER(cshooter_c700_w);
	108	DECLARE_WRITE8_MEMBER(bank_w);
	109	DECLARE_WRITE8_MEMBER(pal_w);
	110	DECLARE_WRITE8_MEMBER(pal2_w);
	111	DECLARE_READ8_MEMBER(pal_r);
	112	DECLARE_READ8_MEMBER(seibu_sound_comms_r);
	113	DECLARE_WRITE8_MEMBER(seibu_sound_comms_w);
104	114	};
105	115
106	116
r14845	r14846
121	131	0);
122	132	}
123	133
124		static WRITE8_HANDLER(cshooter_txram_w)
	134	WRITE8_MEMBER(cshooter_state::cshooter_txram_w)
125	135	{
126		cshooter_state *state = space->machine().driver_data<cshooter_state>();
127		state->m_txram[offset] = data;
128		state->m_txtilemap->mark_tile_dirty(offset/2);
	136	m_txram[offset] = data;
	137	m_txtilemap->mark_tile_dirty(offset/2);
129	138	}
130	139
131	140	static VIDEO_START(cshooter)
r14845	r14846
210	219	MACHINE_RESET_CALL(seibu_sound);
211	220	}
212	221
213		static READ8_HANDLER ( cshooter_coin_r )
	222	READ8_MEMBER(cshooter_state::cshooter_coin_r)
214	223	{
215		cshooter_state *state = space->machine().driver_data<cshooter_state>();
216	224	/* Even reads must return 0xff - Odd reads must return the contents of input port 5.
217	225	Code at 0x5061 is executed once during P.O.S.T. where there is one read.
218	226	Code at 0x50b4 is then executed each frame (not sure) where there are 2 reads. */
219		return ( (state->m_counter++ & 1) ? 0xff : input_port_read(space->machine(), "COIN") );
	227	return ( (m_counter++ & 1) ? 0xff : input_port_read(machine(), "COIN") );
220	228	}
221	229
222		static WRITE8_HANDLER ( cshooter_c500_w )
	230	WRITE8_MEMBER(cshooter_state::cshooter_c500_w)
223	231	{
224	232	}
225	233
226		static WRITE8_HANDLER ( cshooter_c700_w )
	234	WRITE8_MEMBER(cshooter_state::cshooter_c700_w)
227	235	{
228	236	}
229	237
230		static WRITE8_HANDLER ( bank_w )
	238	WRITE8_MEMBER(cshooter_state::bank_w)
231	239	{
232		memory_set_bankptr(space->machine(), "bank1",&space->machine().region("user1")->base()[0x4000*((data>>4)&3)]);
	240	memory_set_bankptr(machine(), "bank1",&machine().region("user1")->base()[0x4000*((data>>4)&3)]);
233	241	}
234	242
235	243
236		static WRITE8_HANDLER(pal_w)
	244	WRITE8_MEMBER(cshooter_state::pal_w)
237	245	{
238		space->machine().generic.paletteram.u8[offset]=data;
	246	machine().generic.paletteram.u8[offset]=data;
239	247	offset&=0xff;
240		palette_set_color_rgb(space->machine(), offset, pal4bit(space->machine().generic.paletteram.u8[offset] >> 4), pal4bit(space->machine().generic.paletteram.u8[offset]), pal4bit(space->machine().generic.paletteram.u8[offset+0x100]));
	248	palette_set_color_rgb(machine(), offset, pal4bit(machine().generic.paletteram.u8[offset] >> 4), pal4bit(machine().generic.paletteram.u8[offset]), pal4bit(machine().generic.paletteram.u8[offset+0x100]));
241	249	}
242	250
243		static WRITE8_HANDLER(pal2_w)
	251	WRITE8_MEMBER(cshooter_state::pal2_w)
244	252	{
245		space->machine().generic.paletteram.u8[offset]=data;
	253	machine().generic.paletteram.u8[offset]=data;
246	254	offset&=0x1ff;
247		palette_set_color_rgb(space->machine(), offset, pal4bit(space->machine().generic.paletteram.u8[offset] >> 4), pal4bit(space->machine().generic.paletteram.u8[offset]), pal4bit(space->machine().generic.paletteram.u8[offset+0x200]));
	255	palette_set_color_rgb(machine(), offset, pal4bit(machine().generic.paletteram.u8[offset] >> 4), pal4bit(machine().generic.paletteram.u8[offset]), pal4bit(machine().generic.paletteram.u8[offset+0x200]));
248	256	}
249	257
250		static READ8_HANDLER(pal_r)
	258	READ8_MEMBER(cshooter_state::pal_r)
251	259	{
252		return space->machine().generic.paletteram.u8[offset];
	260	return machine().generic.paletteram.u8[offset];
253	261	}
254	262
255	263	static ADDRESS_MAP_START( cshooter_map, AS_PROGRAM, 8, cshooter_state )
256	264	AM_RANGE(0x0000, 0x7fff) AM_ROM
257	265	AM_RANGE(0x8000, 0xafff) AM_READ_BANK("bank1") AM_WRITEONLY
258	266	AM_RANGE(0xb000, 0xb0ff) AM_READONLY         // sound related ?
259		AM_RANGE(0xc000, 0xc1ff) AM_WRITE_LEGACY(pal_w) AM_READ_LEGACY(pal_r) AM_BASE_GENERIC(paletteram)
	267	AM_RANGE(0xc000, 0xc1ff) AM_WRITE(pal_w) AM_READ(pal_r) AM_BASE_GENERIC(paletteram)
260	268	AM_RANGE(0xc200, 0xc200) AM_READ_PORT("IN0")
261	269	AM_RANGE(0xc201, 0xc201) AM_READ_PORT("IN1")
262	270	AM_RANGE(0xc202, 0xc202) AM_READ_PORT("IN2")
263	271	AM_RANGE(0xc203, 0xc203) AM_READ_PORT("DSW2")
264	272	AM_RANGE(0xc204, 0xc204) AM_READ_PORT("DSW1")
265		AM_RANGE(0xc205, 0xc205) AM_READ_LEGACY(cshooter_coin_r)   // hack until I understand
266		AM_RANGE(0xc500, 0xc500) AM_WRITE_LEGACY(cshooter_c500_w)
	273	AM_RANGE(0xc205, 0xc205) AM_READ(cshooter_coin_r)   // hack until I understand
	274	AM_RANGE(0xc500, 0xc500) AM_WRITE(cshooter_c500_w)
267	275	AM_RANGE(0xc600, 0xc600) AM_WRITENOP         // see notes
268		AM_RANGE(0xc700, 0xc700) AM_WRITE_LEGACY(cshooter_c700_w)
	276	AM_RANGE(0xc700, 0xc700) AM_WRITE(cshooter_c700_w)
269	277	AM_RANGE(0xc801, 0xc801) AM_WRITENOP         // see notes
270		AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE_LEGACY(cshooter_txram_w) AM_BASE(m_txram)
	278	AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE(cshooter_txram_w) AM_BASE(m_txram)
271	279	AM_RANGE(0xd800, 0xdfff) AM_RAM
272	280	AM_RANGE(0xe000, 0xffff) AM_RAM
273	281	ADDRESS_MAP_END
274	282
275		static READ8_HANDLER( seibu_sound_comms_r )
	283	READ8_MEMBER(cshooter_state::seibu_sound_comms_r)
276	284	{
277		return seibu_main_word_r(space,offset,0x00ff);
	285	return seibu_main_word_r(&space,offset,0x00ff);
278	286	}
279	287
280		static WRITE8_HANDLER( seibu_sound_comms_w )
	288	WRITE8_MEMBER(cshooter_state::seibu_sound_comms_w)
281	289	{
282		seibu_main_word_w(space,offset,data,0x00ff);
	290	seibu_main_word_w(&space,offset,data,0x00ff);
283	291	}
284	292
285	293	static ADDRESS_MAP_START( airraid_map, AS_PROGRAM, 8, cshooter_state )
r14845	r14846
292	300	AM_RANGE(0xc002, 0xc002) AM_READ_PORT("IN2")
293	301	AM_RANGE(0xc003, 0xc003) AM_READ_PORT("DSW2")
294	302	AM_RANGE(0xc004, 0xc004) AM_READ_PORT("DSW1")
295		AM_RANGE(0xc500, 0xc500) AM_WRITE_LEGACY(cshooter_c500_w)
	303	AM_RANGE(0xc500, 0xc500) AM_WRITE(cshooter_c500_w)
296	304	AM_RANGE(0xc600, 0xc600) AM_WRITENOP         // see notes
297		AM_RANGE(0xc700, 0xc700) AM_WRITE_LEGACY(cshooter_c700_w)
	305	AM_RANGE(0xc700, 0xc700) AM_WRITE(cshooter_c700_w)
298	306	AM_RANGE(0xc801, 0xc801) AM_WRITENOP         // see notes
299		AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE_LEGACY(cshooter_txram_w) AM_BASE(m_txram)
300		AM_RANGE(0xd800, 0xdbff) AM_WRITE_LEGACY(pal2_w) AM_READ_LEGACY(pal_r) AM_BASE_GENERIC(paletteram)
301		AM_RANGE(0xdc11, 0xdc11) AM_WRITE_LEGACY(bank_w)
	307	AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE(cshooter_txram_w) AM_BASE(m_txram)
	308	AM_RANGE(0xd800, 0xdbff) AM_WRITE(pal2_w) AM_READ(pal_r) AM_BASE_GENERIC(paletteram)
	309	AM_RANGE(0xdc11, 0xdc11) AM_WRITE(bank_w)
302	310	AM_RANGE(0xdc00, 0xdc1f) AM_RAM //video registers
303		AM_RANGE(0xde00, 0xde0f) AM_READWRITE_LEGACY(seibu_sound_comms_r,seibu_sound_comms_w)
	311	AM_RANGE(0xde00, 0xde0f) AM_READWRITE(seibu_sound_comms_r,seibu_sound_comms_w)
304	312	AM_RANGE(0xe000, 0xfdff) AM_RAM AM_BASE(m_mainram)
305	313	AM_RANGE(0xfe00, 0xffff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
306	314	ADDRESS_MAP_END

src/mame/drivers/ultrsprt.c

r14845	r14846
25	25
26	26	UINT32 *m_vram;
27	27	UINT32 *m_workram;
	28	DECLARE_WRITE32_MEMBER(palette_w);
	29	DECLARE_READ32_MEMBER(eeprom_r);
	30	DECLARE_WRITE32_MEMBER(eeprom_w);
	31	DECLARE_WRITE32_MEMBER(int_ack_w);
	32	DECLARE_READ16_MEMBER(K056800_68k_r);
	33	DECLARE_WRITE16_MEMBER(K056800_68k_w);
28	34	};
29	35
30	36
r14845	r14846
55	61	return 0;
56	62	}
57	63
58		static WRITE32_HANDLER( palette_w )
	64	WRITE32_MEMBER(ultrsprt_state::palette_w)
59	65	{
60		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
61		data = space->machine().generic.paletteram.u32[offset];
	66	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
	67	data = machine().generic.paletteram.u32[offset];
62	68
63		palette_set_color(space->machine(), (offset*2)+0, MAKE_RGB(pal5bit(data >> 26), pal5bit(data >> 21), pal5bit(data >> 16)));
64		palette_set_color(space->machine(), (offset*2)+1, MAKE_RGB(pal5bit(data >> 10), pal5bit(data >>  5), pal5bit(data >>  0)));
	69	palette_set_color(machine(), (offset*2)+0, MAKE_RGB(pal5bit(data >> 26), pal5bit(data >> 21), pal5bit(data >> 16)));
	70	palette_set_color(machine(), (offset*2)+1, MAKE_RGB(pal5bit(data >> 10), pal5bit(data >>  5), pal5bit(data >>  0)));
65	71	}
66	72
67		static READ32_HANDLER( eeprom_r )
	73	READ32_MEMBER(ultrsprt_state::eeprom_r)
68	74	{
69	75	UINT32 r = 0;
70	76
71	77	if (ACCESSING_BITS_24_31)
72		r |= input_port_read(space->machine(), "SERVICE");
	78	r |= input_port_read(machine(), "SERVICE");
73	79
74	80	return r;
75	81	}
76	82
77		static WRITE32_HANDLER( eeprom_w )
	83	WRITE32_MEMBER(ultrsprt_state::eeprom_w)
78	84	{
79	85	if (ACCESSING_BITS_24_31)
80		input_port_write(space->machine(), "EEPROMOUT", data, 0xffffffff);
	86	input_port_write(machine(), "EEPROMOUT", data, 0xffffffff);
81	87	}
82	88
83	89	static CUSTOM_INPUT( analog_ctrl_r )
r14845	r14846
86	92	return input_port_read(field.machine(), tag) & 0xfff;
87	93	}
88	94
89		static WRITE32_HANDLER( int_ack_w )
	95	WRITE32_MEMBER(ultrsprt_state::int_ack_w)
90	96	{
91		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ1, CLEAR_LINE);
	97	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ1, CLEAR_LINE);
92	98	}
93	99
94	100	static MACHINE_START( ultrsprt )
r14845	r14846
106	112
107	113	static ADDRESS_MAP_START( ultrsprt_map, AS_PROGRAM, 32, ultrsprt_state )
108	114	AM_RANGE(0x00000000, 0x0007ffff) AM_RAM AM_BASE(m_vram)
109		AM_RANGE(0x70000000, 0x70000003) AM_READWRITE_LEGACY(eeprom_r, eeprom_w)
	115	AM_RANGE(0x70000000, 0x70000003) AM_READWRITE(eeprom_r, eeprom_w)
110	116	AM_RANGE(0x70000020, 0x70000023) AM_READ_PORT("P1")
111	117	AM_RANGE(0x70000040, 0x70000043) AM_READ_PORT("P2")
112	118	AM_RANGE(0x70000080, 0x70000087) AM_DEVWRITE_LEGACY("k056800", k056800_host_w)
113	119	AM_RANGE(0x70000088, 0x7000008f) AM_DEVREAD_LEGACY("k056800", k056800_host_r)
114		AM_RANGE(0x700000e0, 0x700000e3) AM_WRITE_LEGACY(int_ack_w)
	120	AM_RANGE(0x700000e0, 0x700000e3) AM_WRITE(int_ack_w)
115	121	AM_RANGE(0x7f000000, 0x7f01ffff) AM_RAM AM_BASE(m_workram)
116		AM_RANGE(0x7f700000, 0x7f703fff) AM_RAM_WRITE_LEGACY(palette_w) AM_BASE_GENERIC(paletteram)
	122	AM_RANGE(0x7f700000, 0x7f703fff) AM_RAM_WRITE(palette_w) AM_BASE_GENERIC(paletteram)
117	123	AM_RANGE(0x7f800000, 0x7f9fffff) AM_MIRROR(0x00600000) AM_ROM AM_REGION("user1", 0)
118	124	ADDRESS_MAP_END
119	125
r14845	r14846
121	127	/*****************************************************************************/
122	128
123	129
124		static READ16_HANDLER( K056800_68k_r )
	130	READ16_MEMBER(ultrsprt_state::K056800_68k_r)
125	131	{
126		device_t *k056800 = space->machine().device("k056800");
	132	device_t *k056800 = machine().device("k056800");
127	133	UINT16 r = 0;
128	134
129	135	if (ACCESSING_BITS_8_15)
r14845	r14846
135	141	return r;
136	142	}
137	143
138		static WRITE16_HANDLER( K056800_68k_w )
	144	WRITE16_MEMBER(ultrsprt_state::K056800_68k_w)
139	145	{
140		device_t *k056800 = space->machine().device("k056800");
	146	device_t *k056800 = machine().device("k056800");
141	147
142	148	if (ACCESSING_BITS_8_15)
143	149	k056800_sound_w(k056800, (offset*2)+0, (data >> 8) & 0xff, 0x00ff);
r14845	r14846
149	155	static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 16, ultrsprt_state )
150	156	AM_RANGE(0x00000000, 0x0001ffff) AM_ROM
151	157	AM_RANGE(0x00100000, 0x00101fff) AM_RAM
152		AM_RANGE(0x00200000, 0x00200007) AM_WRITE_LEGACY(K056800_68k_w)
153		AM_RANGE(0x00200008, 0x0020000f) AM_READ_LEGACY(K056800_68k_r)
	158	AM_RANGE(0x00200000, 0x00200007) AM_WRITE(K056800_68k_w)
	159	AM_RANGE(0x00200008, 0x0020000f) AM_READ(K056800_68k_r)
154	160	AM_RANGE(0x00400000, 0x004002ff) AM_DEVREADWRITE8("konami", k054539_device, read, write, 0xffff)
155	161	ADDRESS_MAP_END
156	162

src/mame/drivers/maygay1b.c

r14845	r14846
125	125	int m_optic_pattern;
126	126	device_t *m_duart68681;
127	127	i8279_state m_i8279[2];
	128	DECLARE_READ8_MEMBER(m1_8279_r);
	129	DECLARE_WRITE8_MEMBER(m1_8279_w);
	130	DECLARE_READ8_MEMBER(m1_8279_2_r);
	131	DECLARE_WRITE8_MEMBER(m1_8279_2_w);
	132	DECLARE_WRITE8_MEMBER(reel12_w);
	133	DECLARE_WRITE8_MEMBER(reel34_w);
	134	DECLARE_WRITE8_MEMBER(reel56_w);
	135	DECLARE_WRITE8_MEMBER(m1_latch_w);
	136	DECLARE_WRITE8_MEMBER(latch_ch2_w);
	137	DECLARE_READ8_MEMBER(latch_st_hi);
	138	DECLARE_READ8_MEMBER(latch_st_lo);
	139	DECLARE_WRITE8_MEMBER(m1ab_no_oki_w);
	140	void m1_draw_lamps(int data,int strobe, int col);
128	141	};
129	142
130	143
131		static void m1_draw_lamps(maygay1b_state *state, int data,int strobe, int col)
	144	void maygay1b_state::m1_draw_lamps(int data,int strobe, int col)
132	145	{
133	146	int i;
134	147	int scramble[8] = { 0x10, 0x20, 0x40, 0x80, 0x01, 0x02, 0x04, 0x08 };
135	148
136		state->m_lamppos = strobe + col * 8;
	149	m_lamppos = strobe + col * 8;
137	150
138	151	for ( i = 0; i < 8; i++ )
139	152	{
140		state->m_Lamps[state->m_lamppos] = ( data & scramble[i] );
141		output_set_lamp_value(state->m_lamppos, state->m_Lamps[state->m_lamppos]);
	153	m_Lamps[m_lamppos] = ( data & scramble[i] );
	154	output_set_lamp_value(m_lamppos, m_Lamps[m_lamppos]);
142	155	}
143		state->m_lamppos++;
	156	m_lamppos++;
144	157	}
145	158
146	159
r14845	r14846
174	187	}
175	188	}
176	189
177		static READ8_HANDLER( m1_8279_r )
	190	READ8_MEMBER(maygay1b_state::m1_8279_r)
178	191	{
179		maygay1b_state *state = space->machine().driver_data<maygay1b_state>();
180		i8279_state *chip = state->m_i8279 + 0;
	192	i8279_state *chip = m_i8279 + 0;
181	193	static const char *const portnames[] = { "SW1","STROBE5","STROBE7","STROBE3","SW2","STROBE4","STROBE6","STROBE2" };
182	194	UINT8 result = 0xff;
183	195	UINT8 addr;
r14845	r14846
190	202	/* read sensor RAM */
191	203	case 0x40:
192	204	addr = chip->command & 0x07;
193		result = input_port_read(space->machine(),"SW1");
	205	result = input_port_read(machine(),"SW1");
194	206	/* handle autoincrement */
195	207	if (chip->command & 0x10)
196	208	chip->command = (chip->command & 0xf0) | ((addr + 1) & 0x0f);
r14845	r14846
217	229	{
218	230	if ( chip->read_sensor )
219	231	{
220		result = input_port_read(space->machine(),portnames[chip->sense_address]);
	232	result = input_port_read(machine(),portnames[chip->sense_address]);
221	233	//          break
222	234	}
223	235	if ( chip->sense_auto_inc )
r14845	r14846
234	246	return result;
235	247	}
236	248
237		static WRITE8_HANDLER( m1_8279_w )
	249	WRITE8_MEMBER(maygay1b_state::m1_8279_w)
238	250	{
239		maygay1b_state *state = space->machine().driver_data<maygay1b_state>();
240		i8279_state *chip = state->m_i8279 + 0;
	251	i8279_state *chip = m_i8279 + 0;
241	252	UINT8 addr;
242	253
243	254	/* write data */
r14845	r14846
345	356	{  // Data
346	357	if ( chip->ram[chip->disp_address] != data )
347	358	{
348		m1_draw_lamps(state,chip->ram[chip->disp_address],chip->disp_address, 0);
	359	m1_draw_lamps(chip->ram[chip->disp_address],chip->disp_address, 0);
349	360	}
350	361	chip->ram[chip->disp_address] = data;
351	362	if ( chip->disp_auto_inc )
r14845	r14846
353	364	}
354	365	}
355	366
356		static READ8_HANDLER( m1_8279_2_r )
	367	READ8_MEMBER(maygay1b_state::m1_8279_2_r)
357	368	{
358		maygay1b_state *state = space->machine().driver_data<maygay1b_state>();
359		i8279_state *chip = state->m_i8279 + 1;
	369	i8279_state *chip = m_i8279 + 1;
360	370	UINT8 result = 0xff;
361	371	UINT8 addr;
362	372
r14845	r14846
394	404	}
395	405
396	406
397		static WRITE8_HANDLER( m1_8279_2_w )
	407	WRITE8_MEMBER(maygay1b_state::m1_8279_2_w)
398	408	{
399		maygay1b_state *state = space->machine().driver_data<maygay1b_state>();
400		i8279_state *chip = state->m_i8279 + 1;
	409	i8279_state *chip = m_i8279 + 1;
401	410	UINT8 addr;
402	411
403	412	/* write data */
r14845	r14846
497	506	{  // Data
498	507	if ( chip->ram[chip->disp_address] != data )
499	508	{
500		m1_draw_lamps(state,chip->ram[chip->disp_address],chip->disp_address, 128);
	509	m1_draw_lamps(chip->ram[chip->disp_address],chip->disp_address, 128);
501	510	}
502	511	chip->ram[chip->disp_address] = data;
503	512	if ( chip->disp_auto_inc )
r14845	r14846
727	736	// setup the standard oki MSC1937 display ///////////////////////////////
728	737	ROC10937_init(0, MSC1937,0);
729	738	}
730		static WRITE8_HANDLER( reel12_w )
	739	WRITE8_MEMBER(maygay1b_state::reel12_w)
731	740	{
732		maygay1b_state *state = space->machine().driver_data<maygay1b_state>();
733	741	stepper_update(0, data & 0x0F );
734	742	stepper_update(1, (data>>4) & 0x0F );
735	743
736		if ( stepper_optic_state(0) ) state->m_optic_pattern |=  0x01;
737		else                          state->m_optic_pattern &= ~0x01;
738		if ( stepper_optic_state(1) ) state->m_optic_pattern |=  0x02;
739		else                          state->m_optic_pattern &= ~0x02;
	744	if ( stepper_optic_state(0) ) m_optic_pattern |=  0x01;
	745	else                          m_optic_pattern &= ~0x01;
	746	if ( stepper_optic_state(1) ) m_optic_pattern |=  0x02;
	747	else                          m_optic_pattern &= ~0x02;
740	748
741	749	awp_draw_reel(0);
742	750	awp_draw_reel(1);
743	751	}
744	752
745		static WRITE8_HANDLER( reel34_w )
	753	WRITE8_MEMBER(maygay1b_state::reel34_w)
746	754	{
747		maygay1b_state *state = space->machine().driver_data<maygay1b_state>();
748	755	stepper_update(2, data & 0x0F );
749	756	stepper_update(3, (data>>4) & 0x0F );
750	757
751		if ( stepper_optic_state(2) ) state->m_optic_pattern |=  0x04;
752		else                          state->m_optic_pattern &= ~0x04;
753		if ( stepper_optic_state(3) ) state->m_optic_pattern |=  0x08;
754		else                          state->m_optic_pattern &= ~0x08;
	758	if ( stepper_optic_state(2) ) m_optic_pattern |=  0x04;
	759	else                          m_optic_pattern &= ~0x04;
	760	if ( stepper_optic_state(3) ) m_optic_pattern |=  0x08;
	761	else                          m_optic_pattern &= ~0x08;
755	762
756	763	awp_draw_reel(2);
757	764	awp_draw_reel(3);
758	765	}
759	766
760		static WRITE8_HANDLER( reel56_w )
	767	WRITE8_MEMBER(maygay1b_state::reel56_w)
761	768	{
762		maygay1b_state *state = space->machine().driver_data<maygay1b_state>();
763	769	stepper_update(4, data & 0x0F );
764	770	stepper_update(5, (data>>4) & 0x0F );
765	771
766		if ( stepper_optic_state(4) ) state->m_optic_pattern |=  0x10;
767		else                          state->m_optic_pattern &= ~0x10;
768		if ( stepper_optic_state(5) ) state->m_optic_pattern |=  0x20;
769		else                          state->m_optic_pattern &= ~0x20;
	772	if ( stepper_optic_state(4) ) m_optic_pattern |=  0x10;
	773	else                          m_optic_pattern &= ~0x10;
	774	if ( stepper_optic_state(5) ) m_optic_pattern |=  0x20;
	775	else                          m_optic_pattern &= ~0x20;
770	776
771	777	awp_draw_reel(4);
772	778	awp_draw_reel(5);
r14845	r14846
786	792	if ( data & (1 << i) )   MechMtr_update(i, data & (1 << i) );
787	793	}
788	794
789		static WRITE8_HANDLER( m1_latch_w )
	795	WRITE8_MEMBER(maygay1b_state::m1_latch_w)
790	796	{
791		maygay1b_state *state = space->machine().driver_data<maygay1b_state>();
792	797	switch ( offset )
793	798	{
794		case 0: // state->m_RAMEN
795		state->m_RAMEN = (data & 1);
	799	case 0: // m_RAMEN
	800	m_RAMEN = (data & 1);
796	801	break;
797	802	case 1: // AlarmEn
798		state->m_ALARMEN = (data & 1);
	803	m_ALARMEN = (data & 1);
799	804	break;
800	805	case 2: // Enable
801		cpu0_nmi(space->machine(),1);
802		cpu0_nmi(space->machine(),0);
	806	cpu0_nmi(machine(),1);
	807	cpu0_nmi(machine(),0);
803	808
804	809	//        if ( m1_enable == 0 && ( data & 1 ) && Vmm )
805	810	//      {
r14845	r14846
812	817	}
813	818	break;
814	819	case 4: // PSURelay
815		state->m_PSUrelay = (data & 1);
	820	m_PSUrelay = (data & 1);
816	821	break;
817	822	case 5: // WDog
818		state->m_WDOG = (data & 1);
	823	m_WDOG = (data & 1);
819	824	break;
820	825	case 6: // Srsel
821		state->m_SRSEL = (data & 1);
	826	m_SRSEL = (data & 1);
822	827	break;
823	828	}
824	829	}
825	830
826		static WRITE8_HANDLER( latch_ch2_w )
	831	WRITE8_MEMBER(maygay1b_state::latch_ch2_w)
827	832	{
828		device_t *msm6376 = space->machine().device("msm6376");
	833	device_t *msm6376 = machine().device("msm6376");
829	834	okim6376_w(msm6376, 0, data&0x7f);
830	835	okim6376_ch2_w(msm6376,data&0x80);
831	836	}
832	837
833	838	//A strange setup this, the address lines are used to move st to the right level
834		static READ8_HANDLER( latch_st_hi )
	839	READ8_MEMBER(maygay1b_state::latch_st_hi)
835	840	{
836		device_t *msm6376 = space->machine().device("msm6376");
	841	device_t *msm6376 = machine().device("msm6376");
837	842	okim6376_st_w(msm6376,1);
838	843	return 0;
839	844	}
840	845
841		static READ8_HANDLER( latch_st_lo )
	846	READ8_MEMBER(maygay1b_state::latch_st_lo)
842	847	{
843		device_t *msm6376 = space->machine().device("msm6376");
	848	device_t *msm6376 = machine().device("msm6376");
844	849	okim6376_st_w(msm6376,0);
845	850	return 0;
846	851	}
r14845	r14846
848	853	static ADDRESS_MAP_START( m1_memmap, AS_PROGRAM, 8, maygay1b_state )
849	854	AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("nvram")
850	855
851		AM_RANGE(0x2000, 0x2000) AM_WRITE_LEGACY(reel12_w)
852		AM_RANGE(0x2010, 0x2010) AM_WRITE_LEGACY(reel34_w)
853		AM_RANGE(0x2020, 0x2020) AM_WRITE_LEGACY(reel56_w)
	856	AM_RANGE(0x2000, 0x2000) AM_WRITE(reel12_w)
	857	AM_RANGE(0x2010, 0x2010) AM_WRITE(reel34_w)
	858	AM_RANGE(0x2020, 0x2020) AM_WRITE(reel56_w)
854	859
855		AM_RANGE(0x2030, 0x2031) AM_READWRITE_LEGACY(m1_8279_r,m1_8279_w)
856		AM_RANGE(0x2040, 0x2041) AM_READWRITE_LEGACY(m1_8279_2_r,m1_8279_2_w)
	860	AM_RANGE(0x2030, 0x2031) AM_READWRITE(m1_8279_r,m1_8279_w)
	861	AM_RANGE(0x2040, 0x2041) AM_READWRITE(m1_8279_2_r,m1_8279_2_w)
857	862	AM_RANGE(0x2050, 0x2050)// SCAN on M1B
858	863
859	864	AM_RANGE(0x2070, 0x207f) AM_DEVREADWRITE_LEGACY("duart68681", duart68681_r, duart68681_w )
r14845	r14846
864	869	AM_RANGE(0x20A0, 0x20A3) AM_DEVWRITE("pia", pia6821_device, write)
865	870	AM_RANGE(0x20A0, 0x20A3) AM_DEVREAD("pia", pia6821_device, read)
866	871
867		AM_RANGE(0x20C0, 0x20C7) AM_WRITE_LEGACY(m1_latch_w)
	872	AM_RANGE(0x20C0, 0x20C7) AM_WRITE(m1_latch_w)
868	873
869	874	AM_RANGE(0x2400, 0x2401) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w )
870		AM_RANGE(0x2404, 0x2405) AM_READ_LEGACY(latch_st_lo)
871		AM_RANGE(0x2406, 0x2407) AM_READ_LEGACY(latch_st_hi)
	875	AM_RANGE(0x2404, 0x2405) AM_READ(latch_st_lo)
	876	AM_RANGE(0x2406, 0x2407) AM_READ(latch_st_hi)
872	877
873		AM_RANGE(0x2420, 0x2421) AM_WRITE_LEGACY(latch_ch2_w ) // oki
	878	AM_RANGE(0x2420, 0x2421) AM_WRITE(latch_ch2_w ) // oki
874	879
875	880	AM_RANGE(0x2800, 0xffff) AM_ROM
876	881	ADDRESS_MAP_END
r14845	r14846
4404	4409	ROM_REGION( 0x100000, "msm6376", ROMREGION_ERASE00 )
4405	4410	ROM_END
4406	4411
4407		static WRITE8_HANDLER( m1ab_no_oki_w )
	4412	WRITE8_MEMBER(maygay1b_state::m1ab_no_oki_w)
4408	4413	{
4409	4414	popmessage("write to OKI, but no OKI rom");
4410	4415	}
r14845	r14846
4412	4417	static DRIVER_INIT( m1 )
4413	4418	{
4414	4419
4415		//AM_RANGE(0x2420, 0x2421) AM_WRITE_LEGACY(latch_ch2_w ) // oki
	4420	//AM_RANGE(0x2420, 0x2421) AM_WRITE(latch_ch2_w ) // oki
4416	4421	// if there is no OKI region disable writes here, the rom might be missing, so alert user
4417	4422
4418	4423	UINT8 *okirom = machine.region( "oki" )->base();
4419	4424
4420		if (!okirom)
4421		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x2420, 0x2421, FUNC(m1ab_no_oki_w));
4422
	4425	if (!okirom) {
	4426	maygay1b_state *state = machine.driver_data<maygay1b_state>();
	4427	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0x2420, 0x2421, write8_delegate(FUNC(maygay1b_state::m1ab_no_oki_w), state));
	4428	}
4423	4429	// print out the rom id / header info to give us some hints
4424	4430	// note this isn't always correct, alley cat has 'Calpsyo' still in the ident string?
4425	4431	{

src/mame/drivers/spool99.c

r14845	r14846
104	104	tilemap_t *m_sc0_tilemap;
105	105	UINT8 *m_cram;
106	106	UINT8 *m_vram;
	107	DECLARE_WRITE8_MEMBER(spool99_vram_w);
	108	DECLARE_WRITE8_MEMBER(spool99_cram_w);
	109	DECLARE_READ8_MEMBER(spool99_io_r);
	110	DECLARE_READ8_MEMBER(vcarn_io_r);
107	111	};
108	112
109	113	static TILE_GET_INFO( get_spool99_tile_info )
r14845	r14846
134	138	return 0;
135	139	}
136	140
137		static WRITE8_HANDLER( spool99_vram_w )
	141	WRITE8_MEMBER(spool99_state::spool99_vram_w)
138	142	{
139		spool99_state *state = space->machine().driver_data<spool99_state>();
140	143
141		state->m_vram[offset] = data;
142		state->m_sc0_tilemap->mark_tile_dirty(offset/2);
	144	m_vram[offset] = data;
	145	m_sc0_tilemap->mark_tile_dirty(offset/2);
143	146	}
144	147
145		static WRITE8_HANDLER( spool99_cram_w )
	148	WRITE8_MEMBER(spool99_state::spool99_cram_w)
146	149	{
147		spool99_state *state = space->machine().driver_data<spool99_state>();
148	150
149		state->m_cram[offset] = data;
150		state->m_sc0_tilemap->mark_tile_dirty(offset/2);
	151	m_cram[offset] = data;
	152	m_sc0_tilemap->mark_tile_dirty(offset/2);
151	153	}
152	154
153	155
154	156
155		static READ8_HANDLER( spool99_io_r )
	157	READ8_MEMBER(spool99_state::spool99_io_r)
156	158	{
157		UINT8 *ROM = space->machine().region("maincpu")->base();
	159	UINT8 *ROM = machine().region("maincpu")->base();
158	160
159	161	//  if(!(io_switch))
160	162	{
161	163	switch(offset+0xaf00)
162	164	{
163		case 0xafd8: return input_port_read(space->machine(),"COIN1");
	165	case 0xafd8: return input_port_read(machine(),"COIN1");
164	166	//          case 0xafd9: return 1;
165		case 0xafda: return input_port_read(space->machine(),"COIN2");
	167	case 0xafda: return input_port_read(machine(),"COIN2");
166	168	case 0xafdb: return 1;
167		case 0xafdc: return input_port_read(space->machine(),"SERVICE1");//attract mode
168		case 0xafdd: return input_port_read(space->machine(),"HOLD3");
169		case 0xafde: return input_port_read(space->machine(),"HOLD4");
170		case 0xafdf: return input_port_read(space->machine(),"HOLD2");
171		case 0xafe0: return input_port_read(space->machine(),"HOLD1");
172		case 0xafe1: return input_port_read(space->machine(),"HOLD5");
173		case 0xafe2: return input_port_read(space->machine(),"START");
174		case 0xafe3: return input_port_read(space->machine(),"BET");//system 2
175		case 0xafe4: return input_port_read(space->machine(),"SERVICE2");//attract mode
	169	case 0xafdc: return input_port_read(machine(),"SERVICE1");//attract mode
	170	case 0xafdd: return input_port_read(machine(),"HOLD3");
	171	case 0xafde: return input_port_read(machine(),"HOLD4");
	172	case 0xafdf: return input_port_read(machine(),"HOLD2");
	173	case 0xafe0: return input_port_read(machine(),"HOLD1");
	174	case 0xafe1: return input_port_read(machine(),"HOLD5");
	175	case 0xafe2: return input_port_read(machine(),"START");
	176	case 0xafe3: return input_port_read(machine(),"BET");//system 2
	177	case 0xafe4: return input_port_read(machine(),"SERVICE2");//attract mode
176	178	//          case 0xafe5: return 1;
177	179	//          case 0xafe6: return 1;
178		case 0xafe7: return space->machine().device<eeprom_device>("eeprom")->read_bit();
179		case 0xaff8: return space->machine().device<okim6295_device>("oki")->read(*space,0);
	180	case 0xafe7: return machine().device<eeprom_device>("eeprom")->read_bit();
	181	case 0xaff8: return machine().device<okim6295_device>("oki")->read(*&space,0);
180	182	}
181	183	}
182	184	//  printf("%04x %d\n",offset+0xaf00,io_switch);
r14845	r14846
209	211	static ADDRESS_MAP_START( spool99_map, AS_PROGRAM, 8, spool99_state )
210	212	AM_RANGE(0x0000, 0x00ff) AM_RAM AM_BASE(m_main)
211	213	AM_RANGE(0x0100, 0xaeff) AM_ROM AM_REGION("maincpu", 0x100) AM_WRITENOP
212		AM_RANGE(0xaf00, 0xafff) AM_READ_LEGACY(spool99_io_r)
	214	AM_RANGE(0xaf00, 0xafff) AM_READ(spool99_io_r)
213	215	AM_RANGE(0xafed, 0xafed) AM_DEVWRITE_LEGACY("eeprom", eeprom_resetline_w )
214	216	AM_RANGE(0xafee, 0xafee) AM_DEVWRITE_LEGACY("eeprom", eeprom_clockline_w )
215	217	AM_RANGE(0xafef, 0xafef) AM_DEVWRITE_LEGACY("eeprom", eeprom_dataline_w )
r14845	r14846
218	220	AM_RANGE(0xb000, 0xb3ff) AM_RAM_WRITE_LEGACY(paletteram_xxxxBBBBGGGGRRRR_le_w) AM_BASE_GENERIC(paletteram)
219	221
220	222	AM_RANGE(0xb800, 0xdfff) AM_RAM
221		AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE_LEGACY(spool99_vram_w) AM_BASE(m_vram)
222		AM_RANGE(0xf000, 0xffff) AM_RAM_WRITE_LEGACY(spool99_cram_w) AM_BASE(m_cram)
	223	AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE(spool99_vram_w) AM_BASE(m_vram)
	224	AM_RANGE(0xf000, 0xffff) AM_RAM_WRITE(spool99_cram_w) AM_BASE(m_cram)
223	225	ADDRESS_MAP_END
224	226
225		static READ8_HANDLER( vcarn_io_r )
	227	READ8_MEMBER(spool99_state::vcarn_io_r)
226	228	{
227		UINT8 *ROM = space->machine().region("maincpu")->base();
	229	UINT8 *ROM = machine().region("maincpu")->base();
228	230
229	231	//  if(!(io_switch))
230	232	{
231	233	switch(offset+0xa700)
232	234	{
233		case 0xa720: return input_port_read(space->machine(),"SERVICE1");//attract mode
234		case 0xa722: return input_port_read(space->machine(),"COIN1");
235		case 0xa723: return input_port_read(space->machine(),"COIN2");
236		case 0xa724: return input_port_read(space->machine(),"SERVICE2");//attract mode
237		case 0xa725: return input_port_read(space->machine(),"HOLD3");
238		case 0xa726: return input_port_read(space->machine(),"HOLD4");
239		case 0xa727: return input_port_read(space->machine(),"HOLD2");
240		case 0xa780: return space->machine().device<okim6295_device>("oki")->read(*space,0);
241		case 0xa7a0: return input_port_read(space->machine(),"HOLD1");
242		case 0xa7a1: return input_port_read(space->machine(),"HOLD5");
243		case 0xa7a2: return input_port_read(space->machine(),"START");
244		case 0xa7a3: return input_port_read(space->machine(),"BET");//system 2
	235	case 0xa720: return input_port_read(machine(),"SERVICE1");//attract mode
	236	case 0xa722: return input_port_read(machine(),"COIN1");
	237	case 0xa723: return input_port_read(machine(),"COIN2");
	238	case 0xa724: return input_port_read(machine(),"SERVICE2");//attract mode
	239	case 0xa725: return input_port_read(machine(),"HOLD3");
	240	case 0xa726: return input_port_read(machine(),"HOLD4");
	241	case 0xa727: return input_port_read(machine(),"HOLD2");
	242	case 0xa780: return machine().device<okim6295_device>("oki")->read(*&space,0);
	243	case 0xa7a0: return input_port_read(machine(),"HOLD1");
	244	case 0xa7a1: return input_port_read(machine(),"HOLD5");
	245	case 0xa7a2: return input_port_read(machine(),"START");
	246	case 0xa7a3: return input_port_read(machine(),"BET");//system 2
245	247
246		case 0xa7a7: return space->machine().device<eeprom_device>("eeprom")->read_bit();
	248	case 0xa7a7: return machine().device<eeprom_device>("eeprom")->read_bit();
247	249
248	250	}
249	251	}
r14845	r14846
255	257	static ADDRESS_MAP_START( vcarn_map, AS_PROGRAM, 8, spool99_state )
256	258	AM_RANGE(0x0000, 0x00ff) AM_RAM AM_BASE(m_main)
257	259	AM_RANGE(0x0100, 0xa6ff) AM_ROM AM_REGION("maincpu", 0x100) AM_WRITENOP
258		AM_RANGE(0xa700, 0xa7ff) AM_READ_LEGACY(vcarn_io_r)
	260	AM_RANGE(0xa700, 0xa7ff) AM_READ(vcarn_io_r)
259	261	AM_RANGE(0xa745, 0xa745) AM_DEVWRITE_LEGACY("eeprom", eeprom_resetline_w )
260	262	AM_RANGE(0xa746, 0xa746) AM_DEVWRITE_LEGACY("eeprom", eeprom_clockline_w )
261	263	AM_RANGE(0xa747, 0xa747) AM_DEVWRITE_LEGACY("eeprom", eeprom_dataline_w )
r14845	r14846
264	266	AM_RANGE(0xa800, 0xabff) AM_RAM_WRITE_LEGACY(paletteram_xxxxBBBBGGGGRRRR_le_w) AM_BASE_GENERIC(paletteram)
265	267
266	268	AM_RANGE(0xb000, 0xdfff) AM_RAM
267		//  AM_RANGE(0xdf00, 0xdfff) AM_READWRITE_LEGACY(vcarn_io_r,vcarn_io_w) AM_BASE_LEGACY(&vcarn_io)
268		AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE_LEGACY(spool99_vram_w) AM_BASE(m_vram)
269		AM_RANGE(0xf000, 0xffff) AM_RAM_WRITE_LEGACY(spool99_cram_w) AM_BASE(m_cram)
	269	//  AM_RANGE(0xdf00, 0xdfff) AM_READWRITE(vcarn_io_r,vcarn_io_w) AM_BASE_LEGACY(&vcarn_io)
	270	AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE(spool99_vram_w) AM_BASE(m_vram)
	271	AM_RANGE(0xf000, 0xffff) AM_RAM_WRITE(spool99_cram_w) AM_BASE(m_cram)
270	272	ADDRESS_MAP_END
271	273
272	274

src/mame/drivers/30test.c

r14845	r14846
56	56
57	57	UINT8 m_mux_data;
58	58	UINT8 m_oki_bank;
	59	DECLARE_WRITE8_MEMBER(namco_30test_led_w);
	60	DECLARE_WRITE8_MEMBER(namco_30test_led_rank_w);
	61	DECLARE_WRITE8_MEMBER(namco_30test_lamps_w);
	62	DECLARE_READ8_MEMBER(namco_30test_mux_r);
	63	DECLARE_READ8_MEMBER(hc11_mux_r);
	64	DECLARE_WRITE8_MEMBER(hc11_mux_w);
59	65	};
60	66
61	67
62	68	static const UINT8 led_map[16] =
63	69	{ 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7c,0x07,0x7f,0x67,0x77,0x7c,0x39,0x5e,0x79,0x00 };
64	70
65		static WRITE8_HANDLER( namco_30test_led_w )
	71	WRITE8_MEMBER(namco_30test_state::namco_30test_led_w)
66	72	{
67	73	output_set_digit_value(0 + offset * 2, led_map[(data & 0xf0) >> 4]);
68	74	output_set_digit_value(1 + offset * 2, led_map[(data & 0x0f) >> 0]);
69	75	}
70	76
71		static WRITE8_HANDLER( namco_30test_led_rank_w )
	77	WRITE8_MEMBER(namco_30test_state::namco_30test_led_rank_w)
72	78	{
73	79	output_set_digit_value(64 + offset * 2, led_map[(data & 0xf0) >> 4]);
74	80	output_set_digit_value(65 + offset * 2, led_map[(data & 0x0f) >> 0]);
75	81	}
76	82
77		static WRITE8_HANDLER( namco_30test_lamps_w )
	83	WRITE8_MEMBER(namco_30test_state::namco_30test_lamps_w)
78	84	{
79	85	// d0-d5: ranking, d6: game over, d7: assume marquee lamp
80	86	for (int i = 0; i < 8; i++)
81	87	output_set_lamp_value(i, data >> i & 1);
82	88	}
83	89
84		static READ8_HANDLER(namco_30test_mux_r)
	90	READ8_MEMBER(namco_30test_state::namco_30test_mux_r)
85	91	{
86		namco_30test_state *state = space->machine().driver_data<namco_30test_state>();
87	92	UINT8 res = 0xff;
88	93
89		switch(state->m_mux_data)
	94	switch(m_mux_data)
90	95	{
91		case 0x01: res = input_port_read(space->machine(), "IN0"); break;
92		case 0x02: res = input_port_read(space->machine(), "IN1"); break;
93		case 0x04: res = input_port_read(space->machine(), "IN2"); break;
94		case 0x08: res = input_port_read(space->machine(), "IN3"); break;
	96	case 0x01: res = input_port_read(machine(), "IN0"); break;
	97	case 0x02: res = input_port_read(machine(), "IN1"); break;
	98	case 0x04: res = input_port_read(machine(), "IN2"); break;
	99	case 0x08: res = input_port_read(machine(), "IN3"); break;
95	100	}
96	101
97	102	return res;
98	103	}
99	104
100		static READ8_HANDLER(hc11_mux_r)
	105	READ8_MEMBER(namco_30test_state::hc11_mux_r)
101	106	{
102		namco_30test_state *state = space->machine().driver_data<namco_30test_state>();
103		return state->m_mux_data;
	107	return m_mux_data;
104	108	}
105	109
106		static WRITE8_HANDLER(hc11_mux_w)
	110	WRITE8_MEMBER(namco_30test_state::hc11_mux_w)
107	111	{
108		namco_30test_state *state = space->machine().driver_data<namco_30test_state>();
109		state->m_mux_data = data;
	112	m_mux_data = data;
110	113	}
111	114
112	115	static READ8_DEVICE_HANDLER( hc11_okibank_r )
r14845	r14846
127	130
128	131	static ADDRESS_MAP_START( namco_30test_map, AS_PROGRAM, 8, namco_30test_state )
129	132	AM_RANGE(0x0000, 0x003f) AM_RAM // internal I/O
130		AM_RANGE(0x007c, 0x007c) AM_READWRITE_LEGACY(hc11_mux_r,hc11_mux_w)
	133	AM_RANGE(0x007c, 0x007c) AM_READWRITE(hc11_mux_r,hc11_mux_w)
131	134	AM_RANGE(0x007e, 0x007e) AM_DEVREADWRITE_LEGACY("oki",hc11_okibank_r,hc11_okibank_w)
132	135	AM_RANGE(0x0040, 0x007f) AM_RAM // more internal I/O, HC11 change pending
133	136	AM_RANGE(0x0080, 0x037f) AM_RAM // internal RAM
134	137	AM_RANGE(0x0d80, 0x0dbf) AM_RAM   // EEPROM read-back data goes there
135	138	AM_RANGE(0x2000, 0x2000) AM_DEVREADWRITE("oki", okim6295_device, read, write)
136	139	/* 0x401e-0x401f: time */
137		AM_RANGE(0x4000, 0x401f) AM_WRITE_LEGACY(namco_30test_led_w) // 7-seg leds
	140	AM_RANGE(0x4000, 0x401f) AM_WRITE(namco_30test_led_w) // 7-seg leds
138	141	/* 0x6000: 1st place 7-seg led */
139	142	/* 0x6001: 2nd place 7-seg led */
140	143	/* 0x6002: 3rd place 7-seg led */
141	144	/* 0x6003: current / last play score */
142	145	/* 0x6004: lamps */
143		AM_RANGE(0x6000, 0x6003) AM_WRITE_LEGACY(namco_30test_led_rank_w)
144		AM_RANGE(0x6004, 0x6004) AM_WRITE_LEGACY(namco_30test_lamps_w)
	146	AM_RANGE(0x6000, 0x6003) AM_WRITE(namco_30test_led_rank_w)
	147	AM_RANGE(0x6004, 0x6004) AM_WRITE(namco_30test_lamps_w)
145	148	AM_RANGE(0x8000, 0xffff) AM_ROM
146	149	ADDRESS_MAP_END
147	150
148	151	static ADDRESS_MAP_START( namco_30test_io, AS_IO, 8, namco_30test_state )
149		AM_RANGE(MC68HC11_IO_PORTA,MC68HC11_IO_PORTA) AM_READ_LEGACY(namco_30test_mux_r)
	152	AM_RANGE(MC68HC11_IO_PORTA,MC68HC11_IO_PORTA) AM_READ(namco_30test_mux_r)
150	153	//  AM_RANGE(MC68HC11_IO_PORTD,MC68HC11_IO_PORTD) AM_RAM
151	154	AM_RANGE(MC68HC11_IO_PORTE,MC68HC11_IO_PORTE) AM_READ_PORT("SYSTEM")
152	155	ADDRESS_MAP_END

src/mame/drivers/lgp.c

r14845	r14846
80	80	UINT8 *m_tile_ram;
81	81	UINT8 *m_tile_control_ram;
82	82	emu_timer *m_irq_timer;
	83	DECLARE_READ8_MEMBER(ldp_read);
	84	DECLARE_WRITE8_MEMBER(ldp_write);
83	85	};
84	86
85	87
r14845	r14846
122	124
123	125	/* MEMORY HANDLERS */
124	126	/* Main Z80 R/W */
125		static READ8_HANDLER(ldp_read)
	127	READ8_MEMBER(lgp_state::ldp_read)
126	128	{
127		lgp_state *state = space->machine().driver_data<lgp_state>();
128		return state->m_laserdisc->status_r();
	129	return m_laserdisc->status_r();
129	130	}
130	131
131		static WRITE8_HANDLER(ldp_write)
	132	WRITE8_MEMBER(lgp_state::ldp_write)
132	133	{
133		lgp_state *state = space->machine().driver_data<lgp_state>();
134		state->m_laserdisc->data_w(data);
	134	m_laserdisc->data_w(data);
135	135	}
136	136
137	137
r14845	r14846
145	145	AM_RANGE(0xe400,0xe7ff) AM_RAM AM_BASE(m_tile_control_ram)
146	146
147	147	//  AM_RANGE(0xef00,0xef00) AM_READ_PORT("IN_TEST")
148		AM_RANGE(0xef80,0xef80) AM_READWRITE_LEGACY(ldp_read,ldp_write)
149		AM_RANGE(0xefb8,0xefb8) AM_READ_LEGACY(ldp_read)      /* Likely not right, calms it down though */
	148	AM_RANGE(0xef80,0xef80) AM_READWRITE(ldp_read,ldp_write)
	149	AM_RANGE(0xefb8,0xefb8) AM_READ(ldp_read)      /* Likely not right, calms it down though */
150	150	AM_RANGE(0xefc0,0xefc0) AM_READ_PORT("DSWA")   /* Not tested */
151	151	AM_RANGE(0xefc8,0xefc8) AM_READ_PORT("DSWB")
152	152	AM_RANGE(0xefd0,0xefd0) AM_READ_PORT("DSWC")

src/mame/drivers/cliffhgr.c

r14845	r14846
99	99	UINT32 m_phillips_code;
100	100
101	101	emu_timer *m_irq_timer;
	102	DECLARE_WRITE8_MEMBER(cliff_test_led_w);
	103	DECLARE_WRITE8_MEMBER(cliff_port_bank_w);
	104	DECLARE_READ8_MEMBER(cliff_port_r);
	105	DECLARE_READ8_MEMBER(cliff_phillips_code_r);
	106	DECLARE_WRITE8_MEMBER(cliff_phillips_clear_w);
	107	DECLARE_WRITE8_MEMBER(cliff_coin_counter_w);
	108	DECLARE_READ8_MEMBER(cliff_irq_ack_r);
	109	DECLARE_WRITE8_MEMBER(cliff_ldwire_w);
102	110	};
103	111
104	112
105	113	/********************************************************/
106	114
107		static WRITE8_HANDLER( cliff_test_led_w )
	115	WRITE8_MEMBER(cliffhgr_state::cliff_test_led_w)
108	116	{
109		set_led_status(space->machine(), 0, offset ^ 1);
	117	set_led_status(machine(), 0, offset ^ 1);
110	118	}
111	119
112		static WRITE8_HANDLER( cliff_port_bank_w )
	120	WRITE8_MEMBER(cliffhgr_state::cliff_port_bank_w)
113	121	{
114		cliffhgr_state *state = space->machine().driver_data<cliffhgr_state>();
115	122
116	123	/* writing 0x0f clears the LS174 flip flop */
117	124	if (data == 0x0f)
118		state->m_port_bank = 0;
	125	m_port_bank = 0;
119	126	else
120		state->m_port_bank = data & 0x0f; /* only D3-D0 are connected */
	127	m_port_bank = data & 0x0f; /* only D3-D0 are connected */
121	128	}
122	129
123		static READ8_HANDLER( cliff_port_r )
	130	READ8_MEMBER(cliffhgr_state::cliff_port_r)
124	131	{
125	132	static const char *const banknames[] = { "BANK0", "BANK1", "BANK2", "BANK3", "BANK4", "BANK5", "BANK6" };
126	133
127		cliffhgr_state *state = space->machine().driver_data<cliffhgr_state>();
128	134
129		if (state->m_port_bank < 7)
130		return input_port_read(space->machine(),  banknames[state->m_port_bank]);
131	135
	136	if (m_port_bank < 7)
	137	return input_port_read(machine(),  banknames[m_port_bank]);
	138
132	139	/* output is pulled up for non-mapped ports */
133	140	return 0xff;
134	141	}
135	142
136		static READ8_HANDLER( cliff_phillips_code_r )
	143	READ8_MEMBER(cliffhgr_state::cliff_phillips_code_r)
137	144	{
138		cliffhgr_state *state = space->machine().driver_data<cliffhgr_state>();
139		return (state->m_phillips_code >> (8 * offset)) & 0xff;
	145	return (m_phillips_code >> (8 * offset)) & 0xff;
140	146	}
141	147
142		static WRITE8_HANDLER( cliff_phillips_clear_w )
	148	WRITE8_MEMBER(cliffhgr_state::cliff_phillips_clear_w)
143	149	{
144	150	/* reset serial to parallel converters */
145	151	}
146	152
147		static WRITE8_HANDLER( cliff_coin_counter_w )
	153	WRITE8_MEMBER(cliffhgr_state::cliff_coin_counter_w)
148	154	{
149		coin_counter_w(space->machine(), 0, (data & 0x40) ? 1 : 0 );
	155	coin_counter_w(machine(), 0, (data & 0x40) ? 1 : 0 );
150	156	}
151	157
152		static READ8_HANDLER( cliff_irq_ack_r )
	158	READ8_MEMBER(cliffhgr_state::cliff_irq_ack_r)
153	159	{
154	160	/* deassert IRQ on the CPU */
155		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
	161	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
156	162
157	163	return 0x00;
158	164	}
r14845	r14846
166	172	// bit 4 (data & 0x10) is overlay related?
167	173	}
168	174
169		static WRITE8_HANDLER( cliff_ldwire_w )
	175	WRITE8_MEMBER(cliffhgr_state::cliff_ldwire_w)
170	176	{
171		cliffhgr_state *state = space->machine().driver_data<cliffhgr_state>();
172		state->m_laserdisc->control_w((data & 1) ? ASSERT_LINE : CLEAR_LINE);
	177	m_laserdisc->control_w((data & 1) ? ASSERT_LINE : CLEAR_LINE);
173	178	}
174	179
175	180
r14845	r14846
237	242	AM_RANGE(0x44, 0x44) AM_DEVWRITE("tms9928a", tms9928a_device, vram_write)
238	243	AM_RANGE(0x45, 0x45) AM_DEVREAD("tms9928a", tms9928a_device, vram_read)
239	244	AM_RANGE(0x46, 0x46) AM_DEVWRITE_LEGACY("discrete", cliff_sound_overlay_w)
240		AM_RANGE(0x50, 0x52) AM_READ_LEGACY(cliff_phillips_code_r)
241		AM_RANGE(0x53, 0x53) AM_READ_LEGACY(cliff_irq_ack_r)
	245	AM_RANGE(0x50, 0x52) AM_READ(cliff_phillips_code_r)
	246	AM_RANGE(0x53, 0x53) AM_READ(cliff_irq_ack_r)
242	247	AM_RANGE(0x54, 0x54) AM_DEVWRITE("tms9928a", tms9928a_device, register_write)
243	248	AM_RANGE(0x55, 0x55) AM_DEVREAD("tms9928a", tms9928a_device, register_read)
244		AM_RANGE(0x57, 0x57) AM_WRITE_LEGACY(cliff_phillips_clear_w)
245		AM_RANGE(0x60, 0x60) AM_WRITE_LEGACY(cliff_port_bank_w)
246		AM_RANGE(0x62, 0x62) AM_READ_LEGACY(cliff_port_r)
	249	AM_RANGE(0x57, 0x57) AM_WRITE(cliff_phillips_clear_w)
	250	AM_RANGE(0x60, 0x60) AM_WRITE(cliff_port_bank_w)
	251	AM_RANGE(0x62, 0x62) AM_READ(cliff_port_r)
247	252	AM_RANGE(0x64, 0x64) AM_WRITENOP /* unused in schematics, may be used as timing delay for IR interface */
248		AM_RANGE(0x66, 0x66) AM_WRITE_LEGACY(cliff_ldwire_w)
249		AM_RANGE(0x68, 0x68) AM_WRITE_LEGACY(cliff_coin_counter_w)
	253	AM_RANGE(0x66, 0x66) AM_WRITE(cliff_ldwire_w)
	254	AM_RANGE(0x68, 0x68) AM_WRITE(cliff_coin_counter_w)
250	255	AM_RANGE(0x6a, 0x6a) AM_WRITENOP /* /LAMP0 (Infrared?) */
251		AM_RANGE(0x6e, 0x6f) AM_WRITE_LEGACY(cliff_test_led_w)
	256	AM_RANGE(0x6e, 0x6f) AM_WRITE(cliff_test_led_w)
252	257	ADDRESS_MAP_END
253	258
254	259

src/mame/drivers/multfish.c

r14845	r14846
197	197	UINT8 m_hopper;
198	198
199	199	UINT8 m_vid[multfish_VIDRAM_SIZE];
	200	DECLARE_WRITE8_MEMBER(multfish_vid_w);
	201	DECLARE_WRITE8_MEMBER(multfish_bank_w);
	202	DECLARE_READ8_MEMBER(bankedram_r);
	203	DECLARE_WRITE8_MEMBER(bankedram_w);
	204	DECLARE_WRITE8_MEMBER(multfish_rambank_w);
	205	DECLARE_READ8_MEMBER(ray_r);
	206	DECLARE_WRITE8_MEMBER(multfish_hopper_w);
	207	DECLARE_WRITE8_MEMBER(rollfr_hopper_w);
	208	DECLARE_WRITE8_MEMBER(multfish_lamps1_w);
	209	DECLARE_WRITE8_MEMBER(multfish_lamps2_w);
	210	DECLARE_WRITE8_MEMBER(multfish_lamps3_w);
	211	DECLARE_WRITE8_MEMBER(multfish_counters_w);
	212	DECLARE_WRITE8_MEMBER(multfish_f3_w);
	213	DECLARE_WRITE8_MEMBER(multfish_dispenable_w);
200	214	};
201	215
202	216	static TILE_GET_INFO( get_multfish_tile_info )
r14845	r14846
267	281	return 0;
268	282	}
269	283
270		static WRITE8_HANDLER( multfish_vid_w )
	284	WRITE8_MEMBER(multfish_state::multfish_vid_w)
271	285	{
272		multfish_state *state = space->machine().driver_data<multfish_state>();
273	286
274		state->m_vid[offset]=data;
	287	m_vid[offset]=data;
275	288
276	289	// 0x0000 - 0x1fff is normal tilemap
277	290	if (offset < 0x2000)
278	291	{
279		state->m_tilemap->mark_tile_dirty((offset&0xfff)/2);
	292	m_tilemap->mark_tile_dirty((offset&0xfff)/2);
280	293
281	294	}
282	295	// 0x2000 - 0x2fff is for the reels
283	296	else if (offset < 0x4000)
284	297	{
285		state->m_reel_tilemap->mark_tile_dirty((offset&0x1fff)/2);
	298	m_reel_tilemap->mark_tile_dirty((offset&0x1fff)/2);
286	299	}
287	300	else if (offset < 0x6000)
288	301	{
289	302	int r,g,b;
290	303	int coldat;
291	304
292		coldat = state->m_vid[(offset&0xfffe)] | (state->m_vid[(offset&0xfffe)^1] << 8);
	305	coldat = m_vid[(offset&0xfffe)] | (m_vid[(offset&0xfffe)^1] << 8);
293	306
294	307	/* xor and bitswap palette */
295		switch (state->m_xor_paltype) {
	308	switch (m_xor_paltype) {
296	309	case 1:
297		coldat ^= state->m_xor_palette;
	310	coldat ^= m_xor_palette;
298	311	coldat ^= ((coldat&0x2) >>1) | ((coldat&0x80) >>3) ;
299	312	coldat = BITSWAP16(coldat,10,15,5,13,8,12,11,2,0,4,7,14,9,3,1,6);
300	313	break;
301	314	case 2:
302		coldat ^= state->m_xor_palette;
	315	coldat ^= m_xor_palette;
303	316	coldat ^= ((coldat&0x0001) <<1) ^ ((coldat&0x0010) <<1) ^ ((coldat&0x0010) <<2) ^ ((coldat&0x0020) <<1) ^ ((coldat&0x0080) >>1);
304	317	coldat = BITSWAP16(coldat,4,10,13,14,8,11,15,12,2,6,5,0,7,3,1,9);
305	318	break;
r14845	r14846
309	322	b = ( (coldat &0x00e0)>> (5));
310	323	b|= ( (coldat &0xe000)>> (8+5-3));
311	324
312		palette_set_color_rgb(space->machine(), (offset-0x4000)/2, r<<3, g<<3, b<<2);
	325	palette_set_color_rgb(machine(), (offset-0x4000)/2, r<<3, g<<3, b<<2);
313	326	}
314	327	else
315	328	{
r14845	r14846
317	330	}
318	331	}
319	332
320		static WRITE8_HANDLER( multfish_bank_w )
	333	WRITE8_MEMBER(multfish_state::multfish_bank_w)
321	334	{
322		memory_set_bank(space->machine(), "bank1", data & 0x0f);
	335	memory_set_bank(machine(), "bank1", data & 0x0f);
323	336	}
324	337
325	338	static READ8_DEVICE_HANDLER( multfish_timekeeper_r )
r14845	r14846
332	345	timekeeper_w(device, offset + 0x6000, data);
333	346	}
334	347
335		static READ8_HANDLER( bankedram_r )
	348	READ8_MEMBER(multfish_state::bankedram_r)
336	349	{
337		multfish_state *state = space->machine().driver_data<multfish_state>();
338	350
339		if ((state->m_rambk & 0x80) == 0x00)
	351	if ((m_rambk & 0x80) == 0x00)
340	352	{
341		return timekeeper_r(space->machine().device("m48t35"), offset + 0x2000*(state->m_rambk & 0x03));
	353	return timekeeper_r(machine().device("m48t35"), offset + 0x2000*(m_rambk & 0x03));
342	354	}
343	355	else
344	356	{
345		return state->m_vid[offset+0x2000*(state->m_rambk & 0x03)];
	357	return m_vid[offset+0x2000*(m_rambk & 0x03)];
346	358	}
347	359
348	360	}
349	361
350		static WRITE8_HANDLER( bankedram_w )
	362	WRITE8_MEMBER(multfish_state::bankedram_w)
351	363	{
352		multfish_state *state = space->machine().driver_data<multfish_state>();
353	364
354		if ((state->m_rambk & 0x80) == 0x00)
	365	if ((m_rambk & 0x80) == 0x00)
355	366	{
356		timekeeper_w(space->machine().device("m48t35"), offset + 0x2000*(state->m_rambk & 0x03), data);
	367	timekeeper_w(machine().device("m48t35"), offset + 0x2000*(m_rambk & 0x03), data);
357	368	}
358	369	else
359	370	{
360		multfish_vid_w(space, offset+0x2000*(state->m_rambk & 0x03), data);
	371	multfish_vid_w(space, offset+0x2000*(m_rambk & 0x03), data);
361	372	}
362	373	}
363	374
364		static WRITE8_HANDLER( multfish_rambank_w )
	375	WRITE8_MEMBER(multfish_state::multfish_rambank_w)
365	376	{
366		multfish_state *state = space->machine().driver_data<multfish_state>();
367	377
368		state->m_rambk = data;
	378	m_rambk = data;
369	379	}
370	380
371	381
372		static READ8_HANDLER( ray_r )
	382	READ8_MEMBER(multfish_state::ray_r)
373	383	{
374	384	// the games read the raster beam position as part of the hardware checks..
375	385	// with a 6mhz clock and 640x480 resolution this seems to give the right results.
376		return space->machine().primary_screen->vpos();
	386	return machine().primary_screen->vpos();
377	387	}
378	388
379	389	static CUSTOM_INPUT( multfish_hopper_r )
r14845	r14846
391	401	}
392	402	}
393	403
394		static WRITE8_HANDLER( multfish_hopper_w )
	404	WRITE8_MEMBER(multfish_state::multfish_hopper_w)
395	405	{
396	406	/*  Port 0x33
397	407
r14845	r14846
400	410	---- -X-- Bill Acceptor Lock 24B
401	411	---X ---- Hopper Motor 33B
402	412	*/
403		multfish_state *state = space->machine().driver_data<multfish_state>();
404	413
405		state->m_hopper_motor = data & 0x10;
406		coin_lockout_w(space->machine(), 0, data & 0x01);
407		coin_lockout_w(space->machine(), 1, data & 0x01);
408		coin_lockout_w(space->machine(), 2, data & 0x01);
409		coin_lockout_w(space->machine(), 3, data & 0x01);
410		coin_lockout_w(space->machine(), 4, data & 0x04);
411		coin_lockout_w(space->machine(), 5, data & 0x04);
412		coin_lockout_w(space->machine(), 6, data & 0x04);
413		coin_lockout_w(space->machine(), 7, data & 0x04);
	414
	415	m_hopper_motor = data & 0x10;
	416	coin_lockout_w(machine(), 0, data & 0x01);
	417	coin_lockout_w(machine(), 1, data & 0x01);
	418	coin_lockout_w(machine(), 2, data & 0x01);
	419	coin_lockout_w(machine(), 3, data & 0x01);
	420	coin_lockout_w(machine(), 4, data & 0x04);
	421	coin_lockout_w(machine(), 5, data & 0x04);
	422	coin_lockout_w(machine(), 6, data & 0x04);
	423	coin_lockout_w(machine(), 7, data & 0x04);
414	424	}
415	425
416		static WRITE8_HANDLER( rollfr_hopper_w )
	426	WRITE8_MEMBER(multfish_state::rollfr_hopper_w)
417	427	{
418	428	/*
419	429	By default RollFruit use inverted coinlock bit.
420	430	*/
421		multfish_state *state = space->machine().driver_data<multfish_state>();
422	431
423		state->m_hopper_motor = data & 0x10;
424		coin_lockout_w(space->machine(), 0, !data & 0x01);
425		coin_lockout_w(space->machine(), 1, !data & 0x01);
426		coin_lockout_w(space->machine(), 2, !data & 0x01);
427		coin_lockout_w(space->machine(), 3, !data & 0x01);
428		coin_lockout_w(space->machine(), 4, data & 0x04);
429		coin_lockout_w(space->machine(), 5, data & 0x04);
430		coin_lockout_w(space->machine(), 6, data & 0x04);
431		coin_lockout_w(space->machine(), 7, data & 0x04);
	432
	433	m_hopper_motor = data & 0x10;
	434	coin_lockout_w(machine(), 0, !data & 0x01);
	435	coin_lockout_w(machine(), 1, !data & 0x01);
	436	coin_lockout_w(machine(), 2, !data & 0x01);
	437	coin_lockout_w(machine(), 3, !data & 0x01);
	438	coin_lockout_w(machine(), 4, data & 0x04);
	439	coin_lockout_w(machine(), 5, data & 0x04);
	440	coin_lockout_w(machine(), 6, data & 0x04);
	441	coin_lockout_w(machine(), 7, data & 0x04);
432	442	}
433	443
434	444	DRIVER_INIT( customl )
r14845	r14846
669	679	}
670	680
671	681	static ADDRESS_MAP_START( multfish_map, AS_PROGRAM, 8, multfish_state )
672		AM_RANGE(0x0000, 0x7fff) AM_ROM AM_WRITE_LEGACY(multfish_vid_w)
	682	AM_RANGE(0x0000, 0x7fff) AM_ROM AM_WRITE(multfish_vid_w)
673	683	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
674	684	AM_RANGE(0xc000, 0xdfff) AM_DEVREADWRITE_LEGACY("m48t35", multfish_timekeeper_r, multfish_timekeeper_w)
675		AM_RANGE(0xe000, 0xffff) AM_READWRITE_LEGACY(bankedram_r, bankedram_w)
	685	AM_RANGE(0xe000, 0xffff) AM_READWRITE(bankedram_r, bankedram_w)
676	686	ADDRESS_MAP_END
677	687
678	688	// According to control panel the user buttons are arranged as
r14845	r14846
820	830	INPUT_PORTS_END
821	831
822	832
823		static WRITE8_HANDLER( multfish_lamps1_w )
	833	WRITE8_MEMBER(multfish_state::multfish_lamps1_w)
824	834	{
825	835	/*  Port 0x30
826	836
r14845	r14846
844	854	output_set_lamp_value(0, ((data >> 7) & 1)); /* Bet/Double Lamp */
845	855	}
846	856
847		static WRITE8_HANDLER( multfish_lamps2_w )
	857	WRITE8_MEMBER(multfish_state::multfish_lamps2_w)
848	858	{
849	859	/*  Port 0x34
850	860
r14845	r14846
860	870	output_set_lamp_value(10, ((data >> 4) & 1)); /* Upper Lamp Green */
861	871	}
862	872
863		static WRITE8_HANDLER( multfish_lamps3_w )
	873	WRITE8_MEMBER(multfish_state::multfish_lamps3_w)
864	874	{
865	875	/*  Port 0x35
866	876
r14845	r14846
870	880	output_set_lamp_value(11, ((data >> 1) & 1)); /* Upper Lamp Red */
871	881	}
872	882
873		static WRITE8_HANDLER( multfish_counters_w )
	883	WRITE8_MEMBER(multfish_state::multfish_counters_w)
874	884	{
875	885	/*  Port 0x31
876	886
r14845	r14846
882	892	-X-- ---- Key Out Counter 27A
883	893	X--- ---- Total Bet Counter 28B
884	894	*/
885		coin_counter_w(space->machine(), 0, data & 0x01);
886		coin_counter_w(space->machine(), 1, data & 0x02);
887		coin_counter_w(space->machine(), 2, data & 0x04);
888		coin_counter_w(space->machine(), 3, data & 0x10);
889		coin_counter_w(space->machine(), 4, data & 0x40);
890		coin_counter_w(space->machine(), 5, data & 0x80);
	895	coin_counter_w(machine(), 0, data & 0x01);
	896	coin_counter_w(machine(), 1, data & 0x02);
	897	coin_counter_w(machine(), 2, data & 0x04);
	898	coin_counter_w(machine(), 3, data & 0x10);
	899	coin_counter_w(machine(), 4, data & 0x40);
	900	coin_counter_w(machine(), 5, data & 0x80);
891	901	}
892	902
893		static WRITE8_HANDLER( multfish_f3_w )
	903	WRITE8_MEMBER(multfish_state::multfish_f3_w)
894	904	{
895	905	//popmessage("multfish_f3_w %02x",data);
896	906	}
897	907
898		static WRITE8_HANDLER( multfish_dispenable_w )
	908	WRITE8_MEMBER(multfish_state::multfish_dispenable_w)
899	909	{
900		multfish_state *state = space->machine().driver_data<multfish_state>();
901	910	//popmessage("multfish_f4_w %02x",data); // display enable?
902		state->m_disp_enable = data;
	911	m_disp_enable = data;
903	912	}
904	913
905	914	static ADDRESS_MAP_START( multfish_portmap, AS_IO, 8, multfish_state )
r14845	r14846
914	923	AM_RANGE(0x17, 0x17) AM_READ_PORT("IN7")
915	924
916	925	/* Write ports not hooked up yet */
917		AM_RANGE(0x30, 0x30) AM_WRITE_LEGACY(multfish_lamps1_w)
918		AM_RANGE(0x31, 0x31) AM_WRITE_LEGACY(multfish_counters_w)
	926	AM_RANGE(0x30, 0x30) AM_WRITE(multfish_lamps1_w)
	927	AM_RANGE(0x31, 0x31) AM_WRITE(multfish_counters_w)
919	928	//  AM_RANGE(0x32, 0x32) AM_WRITE_LEGACY(multfish_port32_w)
920		AM_RANGE(0x33, 0x33) AM_WRITE_LEGACY(multfish_hopper_w)
921		AM_RANGE(0x34, 0x34) AM_WRITE_LEGACY(multfish_lamps2_w)
922		AM_RANGE(0x35, 0x35) AM_WRITE_LEGACY(multfish_lamps3_w)
	929	AM_RANGE(0x33, 0x33) AM_WRITE(multfish_hopper_w)
	930	AM_RANGE(0x34, 0x34) AM_WRITE(multfish_lamps2_w)
	931	AM_RANGE(0x35, 0x35) AM_WRITE(multfish_lamps3_w)
923	932	//  AM_RANGE(0x36, 0x36) AM_WRITE_LEGACY(multfish_port36_w)
924	933	AM_RANGE(0x37, 0x37) AM_WRITE_LEGACY(watchdog_reset_w)
925	934	AM_RANGE(0x38, 0x38) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
926	935	AM_RANGE(0x39, 0x39) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
927	936	AM_RANGE(0x3a, 0x3a) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
928	937
929		AM_RANGE(0x60, 0x60) AM_WRITE_LEGACY(multfish_dispenable_w) // display enable mirror for lottery sets
	938	AM_RANGE(0x60, 0x60) AM_WRITE(multfish_dispenable_w) // display enable mirror for lottery sets
930	939
931		AM_RANGE(0x90, 0x90) AM_READ_LEGACY(ray_r)
	940	AM_RANGE(0x90, 0x90) AM_READ(ray_r)
932	941
933		AM_RANGE(0xa0, 0xa0)  AM_WRITE_LEGACY(multfish_bank_w) // Crazy Monkey 2 banking
934		AM_RANGE(0xb0, 0xb0)  AM_WRITE_LEGACY(multfish_bank_w) // Fruit Cocktail 2 lottery banking
935		AM_RANGE(0xb1, 0xb1)  AM_WRITE_LEGACY(multfish_bank_w) // Crazy Monkey Ent banking
936		AM_RANGE(0xb2, 0xb2)  AM_WRITE_LEGACY(multfish_bank_w) // Lacky Haunter Ent banking
937		AM_RANGE(0xb6, 0xb6)  AM_WRITE_LEGACY(multfish_bank_w) // Resident Ent banking
938		AM_RANGE(0xbf, 0xbf)  AM_WRITE_LEGACY(multfish_bank_w) // Gnome Ent banking
939		AM_RANGE(0xc7, 0xc7)  AM_WRITE_LEGACY(multfish_bank_w) // Resident lottery banking
940		AM_RANGE(0xca, 0xca)  AM_WRITE_LEGACY(multfish_bank_w) // Gnome lottery banking
941		AM_RANGE(0xcb, 0xcb)  AM_WRITE_LEGACY(multfish_bank_w) // Keks lottery banking
942		AM_RANGE(0xcc, 0xcc)  AM_WRITE_LEGACY(multfish_bank_w) // Sweet Life 2 lottery banking
943		AM_RANGE(0xcd, 0xcd)  AM_WRITE_LEGACY(multfish_bank_w) // Island 2 lottery banking
944		AM_RANGE(0xce, 0xce)  AM_WRITE_LEGACY(multfish_bank_w) // Pirate 2 lottery banking
945		AM_RANGE(0xd0, 0xd0)  AM_WRITE_LEGACY(multfish_bank_w) // rollfr_4 banking
946		AM_RANGE(0xe1, 0xe1)  AM_WRITE_LEGACY(multfish_bank_w) // Island 2 banking
947		AM_RANGE(0xe5, 0xe5)  AM_WRITE_LEGACY(multfish_bank_w) // Gnome banking
948		AM_RANGE(0xe8, 0xe8)  AM_WRITE_LEGACY(multfish_bank_w) // Sweet Life 2 banking
949		AM_RANGE(0xea, 0xea)  AM_WRITE_LEGACY(multfish_bank_w) // Fruit Cocktail 2 banking
950		AM_RANGE(0xec, 0xec)  AM_WRITE_LEGACY(multfish_bank_w) // Crazy Monkey lottery banking
	942	AM_RANGE(0xa0, 0xa0)  AM_WRITE(multfish_bank_w) // Crazy Monkey 2 banking
	943	AM_RANGE(0xb0, 0xb0)  AM_WRITE(multfish_bank_w) // Fruit Cocktail 2 lottery banking
	944	AM_RANGE(0xb1, 0xb1)  AM_WRITE(multfish_bank_w) // Crazy Monkey Ent banking
	945	AM_RANGE(0xb2, 0xb2)  AM_WRITE(multfish_bank_w) // Lacky Haunter Ent banking
	946	AM_RANGE(0xb6, 0xb6)  AM_WRITE(multfish_bank_w) // Resident Ent banking
	947	AM_RANGE(0xbf, 0xbf)  AM_WRITE(multfish_bank_w) // Gnome Ent banking
	948	AM_RANGE(0xc7, 0xc7)  AM_WRITE(multfish_bank_w) // Resident lottery banking
	949	AM_RANGE(0xca, 0xca)  AM_WRITE(multfish_bank_w) // Gnome lottery banking
	950	AM_RANGE(0xcb, 0xcb)  AM_WRITE(multfish_bank_w) // Keks lottery banking
	951	AM_RANGE(0xcc, 0xcc)  AM_WRITE(multfish_bank_w) // Sweet Life 2 lottery banking
	952	AM_RANGE(0xcd, 0xcd)  AM_WRITE(multfish_bank_w) // Island 2 lottery banking
	953	AM_RANGE(0xce, 0xce)  AM_WRITE(multfish_bank_w) // Pirate 2 lottery banking
	954	AM_RANGE(0xd0, 0xd0)  AM_WRITE(multfish_bank_w) // rollfr_4 banking
	955	AM_RANGE(0xe1, 0xe1)  AM_WRITE(multfish_bank_w) // Island 2 banking
	956	AM_RANGE(0xe5, 0xe5)  AM_WRITE(multfish_bank_w) // Gnome banking
	957	AM_RANGE(0xe8, 0xe8)  AM_WRITE(multfish_bank_w) // Sweet Life 2 banking
	958	AM_RANGE(0xea, 0xea)  AM_WRITE(multfish_bank_w) // Fruit Cocktail 2 banking
	959	AM_RANGE(0xec, 0xec)  AM_WRITE(multfish_bank_w) // Crazy Monkey lottery banking
951	960
952		AM_RANGE(0xf0, 0xf0)  AM_WRITE_LEGACY(multfish_bank_w) // Gold Fish banking
953		AM_RANGE(0xf1, 0xf1)  AM_WRITE_LEGACY(multfish_rambank_w)
954		AM_RANGE(0xf3, 0xf3)  AM_WRITE_LEGACY(multfish_f3_w) // from 00->01 at startup, irq enable maybe?
955		AM_RANGE(0xf4, 0xf4)  AM_WRITE_LEGACY(multfish_dispenable_w) // display enable
	961	AM_RANGE(0xf0, 0xf0)  AM_WRITE(multfish_bank_w) // Gold Fish banking
	962	AM_RANGE(0xf1, 0xf1)  AM_WRITE(multfish_rambank_w)
	963	AM_RANGE(0xf3, 0xf3)  AM_WRITE(multfish_f3_w) // from 00->01 at startup, irq enable maybe?
	964	AM_RANGE(0xf4, 0xf4)  AM_WRITE(multfish_dispenable_w) // display enable
956	965
957	966	/* mirrors of the rom banking */
958		AM_RANGE(0xf8, 0xfd)  AM_WRITE_LEGACY(multfish_bank_w)
	967	AM_RANGE(0xf8, 0xfd)  AM_WRITE(multfish_bank_w)
959	968	ADDRESS_MAP_END
960	969
961	970	static ADDRESS_MAP_START( rollfr_portmap, AS_IO, 8, multfish_state )
962		AM_RANGE(0x33, 0x33) AM_WRITE_LEGACY(rollfr_hopper_w)
	971	AM_RANGE(0x33, 0x33) AM_WRITE(rollfr_hopper_w)
963	972	AM_IMPORT_FROM(multfish_portmap)
964	973	ADDRESS_MAP_END
965	974

src/mame/drivers/timetrv.c

r14845	r14846
35	35
36	36	UINT8 *m_led_vram_lo;
37	37	UINT8 *m_led_vram_hi;
	38	DECLARE_READ8_MEMBER(test1_r);
	39	DECLARE_READ8_MEMBER(test2_r);
	40	DECLARE_READ8_MEMBER(in_r);
	41	DECLARE_READ8_MEMBER(ld_r);
38	42	};
39	43
40	44
r14845	r14846
51	55	return 0;
52	56	}
53	57
54		static READ8_HANDLER( test1_r )
	58	READ8_MEMBER(timetrv_state::test1_r)
55	59	{
56		return input_port_read(space->machine(), "IN0");//space->machine().rand();
	60	return input_port_read(machine(), "IN0");//machine().rand();
57	61	}
58	62
59		static READ8_HANDLER( test2_r )
	63	READ8_MEMBER(timetrv_state::test2_r)
60	64	{
61	65	/*bit 7,eeprom read bit*/
62		return (input_port_read(space->machine(), "IN1") & 0x7f);//space->machine().rand();
	66	return (input_port_read(machine(), "IN1") & 0x7f);//machine().rand();
63	67	}
64	68
65	69
66		static READ8_HANDLER( in_r )
	70	READ8_MEMBER(timetrv_state::in_r)
67	71	{
68	72	return 0xff;
69	73	}
70	74
71		static READ8_HANDLER( ld_r )
	75	READ8_MEMBER(timetrv_state::ld_r)
72	76	{
73		return space->machine().rand();
	77	return machine().rand();
74	78	}
75	79
76	80	static ADDRESS_MAP_START( timetrv_map, AS_PROGRAM, 8, timetrv_state )
r14845	r14846
81	85
82	86	static ADDRESS_MAP_START( timetrv_io, AS_IO, 8, timetrv_state )
83	87	AM_RANGE(0x0122, 0x0123) AM_WRITENOP //eeprom write bits
84		AM_RANGE(0x1000, 0x1000) AM_READ_LEGACY(test1_r) //inputs
85		AM_RANGE(0x1001, 0x1001) AM_READ_LEGACY(test2_r) //eeprom read bit + inputs
	88	AM_RANGE(0x1000, 0x1000) AM_READ(test1_r) //inputs
	89	AM_RANGE(0x1001, 0x1001) AM_READ(test2_r) //eeprom read bit + inputs
86	90
87		AM_RANGE(0x1080, 0x1082) AM_READ_LEGACY(in_r) //dsw
	91	AM_RANGE(0x1080, 0x1082) AM_READ(in_r) //dsw
88	92	AM_RANGE(0x1100, 0x1105) AM_WRITENOP //laserdisc write area
89		AM_RANGE(0x1100, 0x1105) AM_READ_LEGACY(ld_r) //5 -> laserdisc read status
	93	AM_RANGE(0x1100, 0x1105) AM_READ(ld_r) //5 -> laserdisc read status
90	94	AM_RANGE(0x1180, 0x1187) AM_RAM AM_BASE(m_led_vram_lo)//led string,part 1
91	95	AM_RANGE(0x1200, 0x1207) AM_RAM AM_BASE(m_led_vram_hi)//led string,part 2
92	96	AM_RANGE(0xff80, 0xffff) AM_RAM //am80188-em-like cpu internal regs?

src/mame/drivers/quizo.c

r14845	r14846
37	37	UINT8 *m_videoram;
38	38	UINT8 m_port60;
39	39	UINT8 m_port70;
	40	DECLARE_WRITE8_MEMBER(vram_w);
	41	DECLARE_WRITE8_MEMBER(port70_w);
	42	DECLARE_WRITE8_MEMBER(port60_w);
40	43	};
41	44
42	45
r14845	r14846
105	108	return 0;
106	109	}
107	110
108		static WRITE8_HANDLER(vram_w)
	111	WRITE8_MEMBER(quizo_state::vram_w)
109	112	{
110		quizo_state *state = space->machine().driver_data<quizo_state>();
111		UINT8 *videoram = state->m_videoram;
112		int bank=(state->m_port70&8)?1:0;
	113	UINT8 *videoram = m_videoram;
	114	int bank=(m_port70&8)?1:0;
113	115	videoram[offset+bank*0x4000]=data;
114	116	}
115	117
116		static WRITE8_HANDLER(port70_w)
	118	WRITE8_MEMBER(quizo_state::port70_w)
117	119	{
118		quizo_state *state = space->machine().driver_data<quizo_state>();
119		state->m_port70=data;
	120	m_port70=data;
120	121	}
121	122
122		static WRITE8_HANDLER(port60_w)
	123	WRITE8_MEMBER(quizo_state::port60_w)
123	124	{
124		quizo_state *state = space->machine().driver_data<quizo_state>();
125	125	if(data>9)
126	126	{
127		logerror("ROMBANK %x @ %x\n", data, cpu_get_pc(&space->device()));
	127	logerror("ROMBANK %x @ %x\n", data, cpu_get_pc(&space.device()));
128	128	data=0;
129	129	}
130		state->m_port60=data;
131		memory_set_bankptr(space->machine(),  "bank1", &space->machine().region("user1")->base()[rombankLookup[data]*0x4000] );
	130	m_port60=data;
	131	memory_set_bankptr(machine(),  "bank1", &machine().region("user1")->base()[rombankLookup[data]*0x4000] );
132	132	}
133	133
134	134	static ADDRESS_MAP_START( memmap, AS_PROGRAM, 8, quizo_state )
135	135	AM_RANGE(0x0000, 0x3fff) AM_ROM
136	136	AM_RANGE(0x4000, 0x47ff) AM_RAM
137	137	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
138		AM_RANGE(0xc000, 0xffff) AM_WRITE_LEGACY(vram_w)
	138	AM_RANGE(0xc000, 0xffff) AM_WRITE(vram_w)
139	139
140	140	ADDRESS_MAP_END
141	141
r14845	r14846
145	145	AM_RANGE(0x10, 0x10) AM_READ_PORT("IN1")
146	146	AM_RANGE(0x40, 0x40) AM_READ_PORT("IN2")
147	147	AM_RANGE(0x50, 0x51) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
148		AM_RANGE(0x60, 0x60) AM_WRITE_LEGACY(port60_w)
149		AM_RANGE(0x70, 0x70) AM_WRITE_LEGACY(port70_w)
	148	AM_RANGE(0x60, 0x60) AM_WRITE(port60_w)
	149	AM_RANGE(0x70, 0x70) AM_WRITE(port70_w)
150	150	ADDRESS_MAP_END
151	151
152	152	static INPUT_PORTS_START( quizo )

src/mame/drivers/bfm_sc2.c

r14845	r14846
228	228	int m_e2dummywrite;
229	229	int m_e2data_to_read;
230	230	UINT8 m_codec_data[256];
	231	DECLARE_WRITE8_MEMBER(bankswitch_w);
	232	DECLARE_WRITE8_MEMBER(reel12_vid_w);
	233	DECLARE_WRITE8_MEMBER(reel12_w);
	234	DECLARE_WRITE8_MEMBER(reel34_w);
	235	DECLARE_WRITE8_MEMBER(reel56_w);
	236	DECLARE_WRITE8_MEMBER(mmtr_w);
	237	DECLARE_WRITE8_MEMBER(mux_output_w);
	238	DECLARE_READ8_MEMBER(mux_input_r);
	239	DECLARE_WRITE8_MEMBER(unlock_w);
	240	DECLARE_WRITE8_MEMBER(dimas_w);
	241	DECLARE_WRITE8_MEMBER(dimcnt_w);
	242	DECLARE_WRITE8_MEMBER(unknown_w);
	243	DECLARE_WRITE8_MEMBER(volume_override_w);
	244	DECLARE_READ8_MEMBER(vfd_status_hop_r);
	245	DECLARE_WRITE8_MEMBER(expansion_latch_w);
	246	DECLARE_READ8_MEMBER(expansion_latch_r);
	247	DECLARE_WRITE8_MEMBER(muxena_w);
	248	DECLARE_WRITE8_MEMBER(timerirq_w);
	249	DECLARE_READ8_MEMBER(timerirqclr_r);
	250	DECLARE_READ8_MEMBER(irqstatus_r);
	251	DECLARE_WRITE8_MEMBER(coininhib_w);
	252	DECLARE_READ8_MEMBER(coin_input_r);
	253	DECLARE_WRITE8_MEMBER(payout_latch_w);
	254	DECLARE_WRITE8_MEMBER(payout_triac_w);
	255	DECLARE_WRITE8_MEMBER(payout_select_w);
	256	DECLARE_WRITE8_MEMBER(vfd2_data_w);
	257	DECLARE_WRITE8_MEMBER(vfd_reset_w);
	258	DECLARE_READ8_MEMBER(uart1stat_r);
	259	DECLARE_READ8_MEMBER(uart1data_r);
	260	DECLARE_WRITE8_MEMBER(uart1ctrl_w);
	261	DECLARE_WRITE8_MEMBER(uart1data_w);
	262	DECLARE_READ8_MEMBER(uart2stat_r);
	263	DECLARE_READ8_MEMBER(uart2data_r);
	264	DECLARE_WRITE8_MEMBER(uart2ctrl_w);
	265	DECLARE_WRITE8_MEMBER(uart2data_w);
	266	DECLARE_WRITE8_MEMBER(vid_uart_tx_w);
	267	DECLARE_WRITE8_MEMBER(vid_uart_ctrl_w);
	268	DECLARE_READ8_MEMBER(vid_uart_rx_r);
	269	DECLARE_READ8_MEMBER(vid_uart_ctrl_r);
	270	DECLARE_READ8_MEMBER(key_r);
	271	DECLARE_READ8_MEMBER(vfd_status_r);
	272	DECLARE_WRITE8_MEMBER(vfd1_data_w);
	273	DECLARE_WRITE8_MEMBER(e2ram_w);
	274	DECLARE_READ8_MEMBER(direct_input_r);
	275	DECLARE_READ8_MEMBER(sc3_expansion_r);
	276	DECLARE_WRITE8_MEMBER(sc3_expansion_w);
	277	int recdata(int changed, int data);
231	278	};
232	279
233	280
r14845	r14846
427	474
428	475	///////////////////////////////////////////////////////////////////////////
429	476
430		static WRITE8_HANDLER( bankswitch_w )
	477	WRITE8_MEMBER(bfm_sc2_state::bankswitch_w)
431	478	{
432		memory_set_bank(space->machine(), "bank1",data & 0x03);
	479	memory_set_bank(machine(), "bank1",data & 0x03);
433	480	}
434	481
435	482	///////////////////////////////////////////////////////////////////////////
r14845	r14846
450	497
451	498	///////////////////////////////////////////////////////////////////////////
452	499
453		static WRITE8_HANDLER( reel12_vid_w )  // in a video cabinet this is used to drive a hopper
	500	WRITE8_MEMBER(bfm_sc2_state::reel12_vid_w)// in a video cabinet this is used to drive a hopper
454	501	{
455		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
456		state->m_reel12_latch = data;
	502	m_reel12_latch = data;
457	503
458		if ( state->m_has_hopper )
	504	if ( m_has_hopper )
459	505	{
460		int oldhop = state->m_hopper_running;
	506	int oldhop = m_hopper_running;
461	507
462	508	if ( data & 0x01 )
463	509	{ // hopper power
464	510	if ( data & 0x02 )
465	511	{
466		state->m_hopper_running    = 1;
	512	m_hopper_running    = 1;
467	513	}
468	514	else
469	515	{
470		state->m_hopper_running    = 0;
	516	m_hopper_running    = 0;
471	517	}
472	518	}
473	519	else
474	520	{
475		//state->m_hopper_coin_sense = 0;
476		state->m_hopper_running    = 0;
	521	//m_hopper_coin_sense = 0;
	522	m_hopper_running    = 0;
477	523	}
478	524
479		if ( oldhop != state->m_hopper_running )
	525	if ( oldhop != m_hopper_running )
480	526	{
481		state->m_hopper_coin_sense = 0;
482		oldhop = state->m_hopper_running;
	527	m_hopper_coin_sense = 0;
	528	oldhop = m_hopper_running;
483	529	}
484	530	}
485	531	}
486	532
487	533
488	534	/* Reels 1 and 2 */
489		static WRITE8_HANDLER( reel12_w )
	535	WRITE8_MEMBER(bfm_sc2_state::reel12_w)
490	536	{
491		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
492		state->m_reel12_latch = data;
	537	m_reel12_latch = data;
493	538
494		if ( stepper_update(0, data&0x0f   ) ) state->m_reel_changed |= 0x01;
495		if ( stepper_update(1, (data>>4))&0x0f ) state->m_reel_changed |= 0x02;
	539	if ( stepper_update(0, data&0x0f   ) ) m_reel_changed |= 0x01;
	540	if ( stepper_update(1, (data>>4))&0x0f ) m_reel_changed |= 0x02;
496	541
497		if ( stepper_optic_state(0) ) state->m_optic_pattern |=  0x01;
498		else                          state->m_optic_pattern &= ~0x01;
499		if ( stepper_optic_state(1) ) state->m_optic_pattern |=  0x02;
500		else                          state->m_optic_pattern &= ~0x02;
	542	if ( stepper_optic_state(0) ) m_optic_pattern |=  0x01;
	543	else                          m_optic_pattern &= ~0x01;
	544	if ( stepper_optic_state(1) ) m_optic_pattern |=  0x02;
	545	else                          m_optic_pattern &= ~0x02;
501	546
502	547	awp_draw_reel(0);
503	548	awp_draw_reel(1);
504	549	}
505	550
506		static WRITE8_HANDLER( reel34_w )
	551	WRITE8_MEMBER(bfm_sc2_state::reel34_w)
507	552	{
508		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
509		state->m_reel34_latch = data;
	553	m_reel34_latch = data;
510	554
511		if ( stepper_update(2, data&0x0f ) ) state->m_reel_changed |= 0x04;
512		if ( stepper_update(3, (data>>4)&0x0f) ) state->m_reel_changed |= 0x08;
	555	if ( stepper_update(2, data&0x0f ) ) m_reel_changed |= 0x04;
	556	if ( stepper_update(3, (data>>4)&0x0f) ) m_reel_changed |= 0x08;
513	557
514		if ( stepper_optic_state(2) ) state->m_optic_pattern |=  0x04;
515		else                          state->m_optic_pattern &= ~0x04;
516		if ( stepper_optic_state(3) ) state->m_optic_pattern |=  0x08;
517		else                          state->m_optic_pattern &= ~0x08;
	558	if ( stepper_optic_state(2) ) m_optic_pattern |=  0x04;
	559	else                          m_optic_pattern &= ~0x04;
	560	if ( stepper_optic_state(3) ) m_optic_pattern |=  0x08;
	561	else                          m_optic_pattern &= ~0x08;
518	562
519	563	awp_draw_reel(2);
520	564	awp_draw_reel(3);
r14845	r14846
522	566
523	567	///////////////////////////////////////////////////////////////////////////
524	568
525		static WRITE8_HANDLER( reel56_w )
	569	WRITE8_MEMBER(bfm_sc2_state::reel56_w)
526	570	{
527		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
528		state->m_reel56_latch = data;
	571	m_reel56_latch = data;
529	572
530		if ( stepper_update(4, data&0x0f   ) ) state->m_reel_changed |= 0x10;
531		if ( stepper_update(5, (data>>4)&0x0f) ) state->m_reel_changed |= 0x20;
	573	if ( stepper_update(4, data&0x0f   ) ) m_reel_changed |= 0x10;
	574	if ( stepper_update(5, (data>>4)&0x0f) ) m_reel_changed |= 0x20;
532	575
533		if ( stepper_optic_state(4) ) state->m_optic_pattern |=  0x10;
534		else                          state->m_optic_pattern &= ~0x10;
535		if ( stepper_optic_state(5) ) state->m_optic_pattern |=  0x20;
536		else                          state->m_optic_pattern &= ~0x20;
	576	if ( stepper_optic_state(4) ) m_optic_pattern |=  0x10;
	577	else                          m_optic_pattern &= ~0x10;
	578	if ( stepper_optic_state(5) ) m_optic_pattern |=  0x20;
	579	else                          m_optic_pattern &= ~0x20;
537	580
538	581	awp_draw_reel(4);
539	582	awp_draw_reel(5);
r14845	r14846
545	588	// mechanical meters //////////////////////////////////////////////////////
546	589	///////////////////////////////////////////////////////////////////////////
547	590
548		static WRITE8_HANDLER( mmtr_w )
	591	WRITE8_MEMBER(bfm_sc2_state::mmtr_w)
549	592	{
550		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
551	593	int i;
552		int  changed = state->m_mmtr_latch ^ data;
	594	int  changed = m_mmtr_latch ^ data;
553	595
554		state->m_mmtr_latch = data;
	596	m_mmtr_latch = data;
555	597
556	598	for (i = 0; i<8; i++)
557	599	{
r14845	r14846
560	602	MechMtr_update(i, data & (1 << i) );
561	603	}
562	604	}
563		if ( data & 0x1F ) cputag_set_input_line(space->machine(), "maincpu", M6809_FIRQ_LINE, ASSERT_LINE );
	605	if ( data & 0x1F ) cputag_set_input_line(machine(), "maincpu", M6809_FIRQ_LINE, ASSERT_LINE );
564	606	}
565	607
566	608	///////////////////////////////////////////////////////////////////////////
567	609
568		static WRITE8_HANDLER( mux_output_w )
	610	WRITE8_MEMBER(bfm_sc2_state::mux_output_w)
569	611	{
570	612	int i;
571	613	int off = offset<<3;
r14845	r14846
577	619
578	620	///////////////////////////////////////////////////////////////////////////
579	621
580		static READ8_HANDLER( mux_input_r )
	622	READ8_MEMBER(bfm_sc2_state::mux_input_r)
581	623	{
582		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
583	624	int result = 0xFF,t1,t2;
584	625	static const char *const port[] = { "STROBE0", "STROBE1", "STROBE2", "STROBE3", "STROBE4", "STROBE5", "STROBE6", "STROBE7", "STROBE8", "STROBE9", "STROBE10", "STROBE11" };
585	626
586	627	if (offset < 8)
587	628	{
588	629	int idx = (offset & 4) ? 4 : 8;
589		t1 = state->m_input_override[offset];   // strobe 0-7 data 0-4
590		t2 = state->m_input_override[offset+idx];   // strobe 8-B data 0-4
	630	t1 = m_input_override[offset];   // strobe 0-7 data 0-4
	631	t2 = m_input_override[offset+idx];   // strobe 8-B data 0-4
591	632
592		t1 = (state->m_sc2_Inputs[offset]   & t1) | ( ( input_port_read(space->machine(), port[offset])   & ~t1) & 0x1F);
	633	t1 = (m_sc2_Inputs[offset]   & t1) | ( ( input_port_read(machine(), port[offset])   & ~t1) & 0x1F);
593	634	if (idx == 8)
594		t2 = (state->m_sc2_Inputs[offset+8] & t2) | ( ( input_port_read(space->machine(), port[offset+8]) & ~t2) << 5);
	635	t2 = (m_sc2_Inputs[offset+8] & t2) | ( ( input_port_read(machine(), port[offset+8]) & ~t2) << 5);
595	636	else
596		t2 =  (state->m_sc2_Inputs[offset+4] & t2) | ( ( ( input_port_read(space->machine(), port[offset+4]) & ~t2) << 2) & 0x60);
	637	t2 =  (m_sc2_Inputs[offset+4] & t2) | ( ( ( input_port_read(machine(), port[offset+4]) & ~t2) << 2) & 0x60);
597	638
598		state->m_sc2_Inputs[offset]   = (state->m_sc2_Inputs[offset]   & ~0x1F) | t1;
599		state->m_sc2_Inputs[offset+idx] = (state->m_sc2_Inputs[offset+idx] & ~0x60) | t2;
	639	m_sc2_Inputs[offset]   = (m_sc2_Inputs[offset]   & ~0x1F) | t1;
	640	m_sc2_Inputs[offset+idx] = (m_sc2_Inputs[offset+idx] & ~0x60) | t2;
600	641	result = t1 | t2;
601	642	}
602	643
r14845	r14846
605	646
606	647	///////////////////////////////////////////////////////////////////////////
607	648
608		static WRITE8_HANDLER( unlock_w )
	649	WRITE8_MEMBER(bfm_sc2_state::unlock_w)
609	650	{
610	651	}
611	652
612	653	///////////////////////////////////////////////////////////////////////////
613	654
614		static WRITE8_HANDLER( dimas_w )
	655	WRITE8_MEMBER(bfm_sc2_state::dimas_w)
615	656	{
616	657	}
617	658
618	659	///////////////////////////////////////////////////////////////////////////
619	660
620		static WRITE8_HANDLER( dimcnt_w )
	661	WRITE8_MEMBER(bfm_sc2_state::dimcnt_w)
621	662	{
622	663	}
623	664
624	665	///////////////////////////////////////////////////////////////////////////
625	666
626		static WRITE8_HANDLER( unknown_w )
	667	WRITE8_MEMBER(bfm_sc2_state::unknown_w)
627	668	{
628	669	}
629	670
630	671	///////////////////////////////////////////////////////////////////////////
631	672
632		static WRITE8_HANDLER( volume_override_w )
	673	WRITE8_MEMBER(bfm_sc2_state::volume_override_w)
633	674	{
634		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
635		int old = state->m_volume_override;
	675	int old = m_volume_override;
636	676
637		state->m_volume_override = data?1:0;
	677	m_volume_override = data?1:0;
638	678
639		if ( old != state->m_volume_override )
	679	if ( old != m_volume_override )
640	680	{
641		ym2413_device *ym = space->machine().device<ym2413_device>("ymsnd");
642		upd7759_device *upd = space->machine().device<upd7759_device>("upd");
643		float percent = state->m_volume_override? 1.0f : (32-state->m_global_volume)/32.0f;
	681	ym2413_device *ym = machine().device<ym2413_device>("ymsnd");
	682	upd7759_device *upd = machine().device<upd7759_device>("upd");
	683	float percent = m_volume_override? 1.0f : (32-m_global_volume)/32.0f;
644	684
645	685	ym->set_output_gain(0, percent);
646	686	ym->set_output_gain(1, percent);
r14845	r14846
675	715
676	716	///////////////////////////////////////////////////////////////////////////
677	717
678		static READ8_HANDLER( vfd_status_hop_r )   // on video games, hopper inputs are connected to this
	718	READ8_MEMBER(bfm_sc2_state::vfd_status_hop_r)// on video games, hopper inputs are connected to this
679	719	{
680		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
681	720	// b7 = NEC busy
682	721	// b6 = alpha busy (also matrix board)
683	722	// b5 - b0 = reel optics
684	723
685	724	int result = 0;
686	725
687		if ( state->m_has_hopper )
	726	if ( m_has_hopper )
688	727	{
689	728	result |= 0x04; // hopper high level
690	729	result |= 0x08; // hopper low  level
691	730
692	731	result |= 0x01|0x02;
693	732
694		if ( state->m_hopper_running )
	733	if ( m_hopper_running )
695	734	{
696	735	result &= ~0x01;                          // set motor running input
697	736
698		if ( state->m_timercnt & 0x04 ) state->m_hopper_coin_sense ^= 1;     // toggle coin seen
	737	if ( m_timercnt & 0x04 ) m_hopper_coin_sense ^= 1;     // toggle coin seen
699	738
700		if ( state->m_hopper_coin_sense ) result &= ~0x02;        // update coin seen input
	739	if ( m_hopper_coin_sense ) result &= ~0x02;        // update coin seen input
701	740	}
702	741	}
703	742
704		if ( !upd7759_busy_r(space->machine().device("upd")) ) result |= 0x80;           // update sound busy input
	743	if ( !upd7759_busy_r(machine().device("upd")) ) result |= 0x80;           // update sound busy input
705	744
706	745	return result;
707	746	}
708	747
709	748	///////////////////////////////////////////////////////////////////////////
710	749
711		static WRITE8_HANDLER( expansion_latch_w )
	750	WRITE8_MEMBER(bfm_sc2_state::expansion_latch_w)
712	751	{
713		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
714		int changed = state->m_expansion_latch^data;
	752	int changed = m_expansion_latch^data;
715	753
716		state->m_expansion_latch = data;
	754	m_expansion_latch = data;
717	755
718	756	// bit0,  1 = lamp mux disabled, 0 = lamp mux enabled
719	757	// bit1,  ? used in Del's millions
r14845	r14846
730	768	{ // changed from high to low,
731	769	if ( !(data & 0x08) )
732	770	{
733		if ( state->m_global_volume < 31 ) state->m_global_volume++; //0-31 expressed as 1-32
	771	if ( m_global_volume < 31 ) m_global_volume++; //0-31 expressed as 1-32
734	772	}
735	773	else
736	774	{
737		if ( state->m_global_volume > 0  ) state->m_global_volume--;
	775	if ( m_global_volume > 0  ) m_global_volume--;
738	776	}
739	777
740	778	{
741		ym2413_device *ym = space->machine().device<ym2413_device>("ymsnd");
742		upd7759_device *upd = space->machine().device<upd7759_device>("upd");
743		float percent = state->m_volume_override ? 1.0f : (32-state->m_global_volume)/32.0f;
	779	ym2413_device *ym = machine().device<ym2413_device>("ymsnd");
	780	upd7759_device *upd = machine().device<upd7759_device>("upd");
	781	float percent = m_volume_override ? 1.0f : (32-m_global_volume)/32.0f;
744	782
745	783	ym->set_output_gain(0, percent);
746	784	ym->set_output_gain(1, percent);
r14845	r14846
752	790
753	791	///////////////////////////////////////////////////////////////////////////
754	792
755		static READ8_HANDLER( expansion_latch_r )
	793	READ8_MEMBER(bfm_sc2_state::expansion_latch_r)
756	794	{
757	795	return 0;
758	796	}
759	797
760	798	///////////////////////////////////////////////////////////////////////////
761	799
762		static WRITE8_HANDLER( muxena_w )
	800	WRITE8_MEMBER(bfm_sc2_state::muxena_w)
763	801	{
764	802	}
765	803
766	804	///////////////////////////////////////////////////////////////////////////
767	805
768		static WRITE8_HANDLER( timerirq_w )
	806	WRITE8_MEMBER(bfm_sc2_state::timerirq_w)
769	807	{
770		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
771		state->m_is_timer_enabled = data & 1;
	808	m_is_timer_enabled = data & 1;
772	809	}
773	810
774	811	///////////////////////////////////////////////////////////////////////////
775	812
776		static READ8_HANDLER( timerirqclr_r )
	813	READ8_MEMBER(bfm_sc2_state::timerirqclr_r)
777	814	{
778		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
779		state->m_irq_timer_stat = 0;
780		state->m_irq_status     = 0;
	815	m_irq_timer_stat = 0;
	816	m_irq_status     = 0;
781	817
782	818	return 0;
783	819	}
784	820
785	821	///////////////////////////////////////////////////////////////////////////
786	822
787		static READ8_HANDLER( irqstatus_r )
	823	READ8_MEMBER(bfm_sc2_state::irqstatus_r)
788	824	{
789		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
790		int result = state->m_irq_status | state->m_irq_timer_stat | 0x80;   // 0x80 = ~MUXERROR
	825	int result = m_irq_status | m_irq_timer_stat | 0x80;   // 0x80 = ~MUXERROR
791	826
792		state->m_irq_timer_stat = 0;
	827	m_irq_timer_stat = 0;
793	828
794	829	return result;
795	830	}
796	831
797	832	///////////////////////////////////////////////////////////////////////////
798	833
799		static WRITE8_HANDLER( coininhib_w )
	834	WRITE8_MEMBER(bfm_sc2_state::coininhib_w)
800	835	{
801		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
802		int changed = state->m_coin_inhibits^data,i,p;
	836	int changed = m_coin_inhibits^data,i,p;
803	837
804		state->m_coin_inhibits = data;
	838	m_coin_inhibits = data;
805	839
806	840	p = 0x01;
807	841	i = 0;
r14845	r14846
810	844	{
811	845	if ( changed & p )
812	846	{ // this inhibit line has changed
813		coin_lockout_w(space->machine(), i, (~data & p) ); // update lockouts
	847	coin_lockout_w(machine(), i, (~data & p) ); // update lockouts
814	848	changed &= ~p;
815	849	}
816	850
r14845	r14846
821	855
822	856	///////////////////////////////////////////////////////////////////////////
823	857
824		static READ8_HANDLER( coin_input_r )
	858	READ8_MEMBER(bfm_sc2_state::coin_input_r)
825	859	{
826		return input_port_read(space->machine(), "COINS");
	860	return input_port_read(machine(), "COINS");
827	861	}
828	862
829	863	///////////////////////////////////////////////////////////////////////////
830	864
831		static WRITE8_HANDLER( payout_latch_w )
	865	WRITE8_MEMBER(bfm_sc2_state::payout_latch_w)
832	866	{
833		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
834		state->m_pay_latch = data;
	867	m_pay_latch = data;
835	868	}
836	869
837	870	///////////////////////////////////////////////////////////////////////////
838	871
839		static WRITE8_HANDLER( payout_triac_w )
	872	WRITE8_MEMBER(bfm_sc2_state::payout_triac_w)
840	873	{
841		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
842		if ( state->m_triac_select == 0x57 )
	874	if ( m_triac_select == 0x57 )
843	875	{
844	876	int slide = 0;
845	877
846		switch ( state->m_pay_latch )
	878	switch ( m_pay_latch )
847	879	{
848	880	case 0x01: slide = 1;
849	881	break;
r14845	r14846
868	900	{
869	901	if ( data == 0x4D )
870	902	{
871		if ( !state->m_slide_states[slide] )
	903	if ( !m_slide_states[slide] )
872	904	{
873		if ( state->m_slide_pay_sensor[slide] )
	905	if ( m_slide_pay_sensor[slide] )
874	906	{
875		int strobe = state->m_slide_pay_sensor[slide]>>4, data = state->m_slide_pay_sensor[slide]&0x0F;
	907	int strobe = m_slide_pay_sensor[slide]>>4, data = m_slide_pay_sensor[slide]&0x0F;
876	908
877		Scorpion2_SetSwitchState(space->machine(), strobe, data, 0);
	909	Scorpion2_SetSwitchState(machine(), strobe, data, 0);
878	910	}
879		state->m_slide_states[slide] = 1;
	911	m_slide_states[slide] = 1;
880	912	}
881	913	}
882	914	else
883	915	{
884		if ( state->m_slide_states[slide] )
	916	if ( m_slide_states[slide] )
885	917	{
886		if ( state->m_slide_pay_sensor[slide] )
	918	if ( m_slide_pay_sensor[slide] )
887	919	{
888		int strobe = state->m_slide_pay_sensor[slide]>>4, data = state->m_slide_pay_sensor[slide]&0x0F;
	920	int strobe = m_slide_pay_sensor[slide]>>4, data = m_slide_pay_sensor[slide]&0x0F;
889	921
890		Scorpion2_SetSwitchState(space->machine(), strobe, data, 1);
	922	Scorpion2_SetSwitchState(machine(), strobe, data, 1);
891	923	}
892		state->m_slide_states[slide] = 0;
	924	m_slide_states[slide] = 0;
893	925	}
894	926	}
895	927	}
r14845	r14846
898	930
899	931	///////////////////////////////////////////////////////////////////////////
900	932
901		static WRITE8_HANDLER( payout_select_w )
	933	WRITE8_MEMBER(bfm_sc2_state::payout_select_w)
902	934	{
903		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
904		state->m_triac_select = data;
	935	m_triac_select = data;
905	936	}
906	937
907	938
908	939
909	940	///////////////////////////////////////////////////////////////////////////
910	941
911		static WRITE8_HANDLER( vfd2_data_w )
	942	WRITE8_MEMBER(bfm_sc2_state::vfd2_data_w)
912	943	{
913		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
914		state->m_vfd2_latch = data;
	944	m_vfd2_latch = data;
915	945	BFM_BD1_newdata(1, data);
916	946	BFM_BD1_draw(1);
917	947	}
918	948
919	949	///////////////////////////////////////////////////////////////////////////
920	950
921		static WRITE8_HANDLER( vfd_reset_w )
	951	WRITE8_MEMBER(bfm_sc2_state::vfd_reset_w)
922	952	{
923	953	BFM_BD1_reset(0);     // reset both VFD's
924	954	BFM_BD1_reset(1);
r14845	r14846
930	960	// serial port ////////////////////////////////////////////////////////////
931	961	///////////////////////////////////////////////////////////////////////////
932	962
933		static READ8_HANDLER( uart1stat_r )
	963	READ8_MEMBER(bfm_sc2_state::uart1stat_r)
934	964	{
935		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
936	965	int status = 0x06;
937	966
938		if ( state->m_data_to_uart1  ) status |= 0x01;
939		if ( !state->m_data_to_uart2 ) status |= 0x02;
	967	if ( m_data_to_uart1  ) status |= 0x01;
	968	if ( !m_data_to_uart2 ) status |= 0x02;
940	969
941	970	return status;
942	971	}
943	972	///////////////////////////////////////////////////////////////////////////
944	973
945		static READ8_HANDLER( uart1data_r )
	974	READ8_MEMBER(bfm_sc2_state::uart1data_r)
946	975	{
947		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
948		return state->m_uart1_data;
	976	return m_uart1_data;
949	977	}
950	978
951	979	//////////////////////////////////////////////////////////////////////////
952	980
953		static WRITE8_HANDLER( uart1ctrl_w )
	981	WRITE8_MEMBER(bfm_sc2_state::uart1ctrl_w)
954	982	{
955	983	UART_LOG(("uart1ctrl:%x\n", data));
956	984	}
957	985	///////////////////////////////////////////////////////////////////////////
958	986
959		static WRITE8_HANDLER( uart1data_w )
	987	WRITE8_MEMBER(bfm_sc2_state::uart1data_w)
960	988	{
961		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
962		state->m_data_to_uart2 = 1;
963		state->m_uart1_data    = data;
	989	m_data_to_uart2 = 1;
	990	m_uart1_data    = data;
964	991	UART_LOG(("uart1:%x\n", data));
965	992	}
966	993	///////////////////////////////////////////////////////////////////////////
967	994
968		static READ8_HANDLER( uart2stat_r )
	995	READ8_MEMBER(bfm_sc2_state::uart2stat_r)
969	996	{
970		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
971	997	int status = 0x06;
972	998
973		if ( state->m_data_to_uart2  ) status |= 0x01;
974		if ( !state->m_data_to_uart1 ) status |= 0x02;
	999	if ( m_data_to_uart2  ) status |= 0x01;
	1000	if ( !m_data_to_uart1 ) status |= 0x02;
975	1001
976	1002	return status;
977	1003	}
978	1004	///////////////////////////////////////////////////////////////////////////
979	1005
980		static READ8_HANDLER( uart2data_r )
	1006	READ8_MEMBER(bfm_sc2_state::uart2data_r)
981	1007	{
982		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
983		return state->m_uart2_data;
	1008	return m_uart2_data;
984	1009	}
985	1010
986	1011	///////////////////////////////////////////////////////////////////////////
987	1012
988		static WRITE8_HANDLER( uart2ctrl_w )
	1013	WRITE8_MEMBER(bfm_sc2_state::uart2ctrl_w)
989	1014	{
990	1015	UART_LOG(("uart2ctrl:%x\n", data));
991	1016	}
992	1017
993	1018	///////////////////////////////////////////////////////////////////////////
994	1019
995		static WRITE8_HANDLER( uart2data_w )
	1020	WRITE8_MEMBER(bfm_sc2_state::uart2data_w)
996	1021	{
997		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
998		state->m_data_to_uart1 = 1;
999		state->m_uart2_data    = data;
	1022	m_data_to_uart1 = 1;
	1023	m_uart2_data    = data;
1000	1024	UART_LOG(("uart2:%x\n", data));
1001	1025	}
1002	1026
1003	1027	///////////////////////////////////////////////////////////////////////////
1004	1028
1005		static WRITE8_HANDLER( vid_uart_tx_w )
	1029	WRITE8_MEMBER(bfm_sc2_state::vid_uart_tx_w)
1006	1030	{
1007	1031	adder2_send(data);
1008		cputag_set_input_line(space->machine(), "adder2", M6809_IRQ_LINE, HOLD_LINE );
	1032	cputag_set_input_line(machine(), "adder2", M6809_IRQ_LINE, HOLD_LINE );
1009	1033
1010	1034	LOG_SERIAL(("sadder  %02X  (%c)\n",data, data ));
1011	1035	}
1012	1036
1013	1037	///////////////////////////////////////////////////////////////////////////
1014	1038
1015		static WRITE8_HANDLER( vid_uart_ctrl_w )
	1039	WRITE8_MEMBER(bfm_sc2_state::vid_uart_ctrl_w)
1016	1040	{
1017	1041	}
1018	1042
1019	1043	///////////////////////////////////////////////////////////////////////////
1020	1044
1021		static READ8_HANDLER( vid_uart_rx_r )
	1045	READ8_MEMBER(bfm_sc2_state::vid_uart_rx_r)
1022	1046	{
1023	1047	int data = adder2_receive();
1024	1048
r14845	r14846
1029	1053
1030	1054	///////////////////////////////////////////////////////////////////////////
1031	1055
1032		static READ8_HANDLER( vid_uart_ctrl_r )
	1056	READ8_MEMBER(bfm_sc2_state::vid_uart_ctrl_r)
1033	1057	{
1034	1058	return adder2_status();
1035	1059	}
1036	1060
1037	1061	///////////////////////////////////////////////////////////////////////////
1038	1062
1039		static READ8_HANDLER( key_r )
	1063	READ8_MEMBER(bfm_sc2_state::key_r)
1040	1064	{
1041		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
1042		int result = state->m_key[ offset ];
	1065	int result = m_key[ offset ];
1043	1066
1044	1067	if ( offset == 7 )
1045	1068	{
1046		result = (result & 0xFE) | read_e2ram(space->machine());
	1069	result = (result & 0xFE) | read_e2ram(machine());
1047	1070	}
1048	1071
1049	1072	return result;
r14845	r14846
1079	1102	state->m_e2data_to_read = 0;
1080	1103	}
1081	1104
1082		static int recdata(bfm_sc2_state *state, int changed, int data)
	1105	int bfm_sc2_state::recdata(int changed, int data)
1083	1106	{
1084	1107	int res = 1;
1085	1108
1086		if ( state->m_e2cnt < 8 )
	1109	if ( m_e2cnt < 8 )
1087	1110	{
1088	1111	res = 0;
1089	1112
1090	1113	if ( (changed & SCL) && (data & SCL) )
1091	1114	{ // clocked in new data
1092		int pattern = 1 << (7-state->m_e2cnt);
	1115	int pattern = 1 << (7-m_e2cnt);
1093	1116
1094		if ( data & SDA ) state->m_e2data |=  pattern;
1095		else              state->m_e2data &= ~pattern;
	1117	if ( data & SDA ) m_e2data |=  pattern;
	1118	else              m_e2data &= ~pattern;
1096	1119
1097		state->m_e2data_pin = state->m_e2data_to_read & 0x80 ? 1 : 0;
	1120	m_e2data_pin = m_e2data_to_read & 0x80 ? 1 : 0;
1098	1121
1099		state->m_e2data_to_read <<= 1;
	1122	m_e2data_to_read <<= 1;
1100	1123
1101		LOG(("e2d pin= %d\n", state->m_e2data_pin));
	1124	LOG(("e2d pin= %d\n", m_e2data_pin));
1102	1125
1103		state->m_e2cnt++;
1104		if ( state->m_e2cnt >= 8 )
	1126	m_e2cnt++;
	1127	if ( m_e2cnt >= 8 )
1105	1128	{
1106	1129	res++;
1107	1130	}
r14845	r14846
1133	1156
1134	1157
1135	1158	/* VFD Status */
1136		static READ8_HANDLER( vfd_status_r )
	1159	READ8_MEMBER(bfm_sc2_state::vfd_status_r)
1137	1160	{
1138		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
1139	1161	/* b7 = NEC busy */
1140	1162	/* b6 = alpha busy (also matrix board) */
1141	1163	/* b5 - b0 = reel optics */
1142	1164
1143		int result = state->m_optic_pattern;
	1165	int result = m_optic_pattern;
1144	1166
1145		if ( !upd7759_busy_r(space->machine().device("upd")) ) result |= 0x80;
	1167	if ( !upd7759_busy_r(machine().device("upd")) ) result |= 0x80;
1146	1168
1147		if (space->machine().device("matrix"))
	1169	if (machine().device("matrix"))
1148	1170	if ( BFM_dm01_busy() ) result |= 0x40;
1149	1171
1150	1172	return result;
1151	1173	}
1152	1174
1153		static WRITE8_HANDLER( vfd1_data_w )
	1175	WRITE8_MEMBER(bfm_sc2_state::vfd1_data_w)
1154	1176	{
1155		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>();
1156		state->m_vfd1_latch = data;
	1177	m_vfd1_latch = data;
1157	1178
1158		if (space->machine().device("matrix"))
	1179	if (machine().device("matrix"))
1159	1180	{
1160		BFM_dm01_writedata(space->machine(),data);
	1181	BFM_dm01_writedata(machine(),data);
1161	1182	}
1162	1183	else
1163	1184	{
r14845	r14846
1168	1189
1169	1190
1170	1191	//
1171		static WRITE8_HANDLER( e2ram_w )
	1192	WRITE8_MEMBER(bfm_sc2_state::e2ram_w)
1172	1193	{
1173		bfm_sc2_state *state = space->machine().driver_data<bfm_sc2_state>(); // b0 = clock b1 = data
1174	1194
1175	1195	int changed, ack;
1176	1196
1177	1197	data ^= (SDA|SCL);  // invert signals
1178	1198
1179		changed  = (state->m_e2reg^data) & 0x03;
	1199	changed  = (m_e2reg^data) & 0x03;
1180	1200
1181		state->m_e2reg = data;
	1201	m_e2reg = data;
1182	1202
1183	1203	if ( changed )
1184	1204	{
r14845	r14846
1188	1208	( !(changed & SCL) && (data & SCL) )    // SCL=1 and not changed
1189	1209	)
1190	1210	{   // X24C08 Start condition (1->0 on SDA while SCL=1)
1191		state->m_e2dummywrite = ( state->m_e2state == 5 );
	1211	m_e2dummywrite = ( m_e2state == 5 );
1192	1212
1193		LOG(("e2ram:   c:%d d:%d Start condition dummywrite=%d\n", (data & SCL)?1:0, (data&SDA)?1:0, state->m_e2dummywrite ));
	1213	LOG(("e2ram:   c:%d d:%d Start condition dummywrite=%d\n", (data & SCL)?1:0, (data&SDA)?1:0, m_e2dummywrite ));
1194	1214
1195		state->m_e2state = 1; // ready for commands
1196		state->m_e2cnt   = 0;
1197		state->m_e2data  = 0;
	1215	m_e2state = 1; // ready for commands
	1216	m_e2cnt   = 0;
	1217	m_e2data  = 0;
1198	1218	break;
1199	1219	}
1200	1220
r14845	r14846
1203	1223	)
1204	1224	{   // X24C08 Stop condition (0->1 on SDA while SCL=1)
1205	1225	LOG(("e2ram:   c:%d d:%d Stop condition\n", (data & SCL)?1:0, (data&SDA)?1:0 ));
1206		state->m_e2state = 0;
1207		state->m_e2data  = 0;
	1226	m_e2state = 0;
	1227	m_e2data  = 0;
1208	1228	break;
1209	1229	}
1210	1230
1211		switch ( state->m_e2state )
	1231	switch ( m_e2state )
1212	1232	{
1213	1233	case 1: // Receiving address + R/W bit
1214	1234
1215		if ( recdata(state, changed, data) )
	1235	if ( recdata(changed, data) )
1216	1236	{
1217		state->m_e2address = (state->m_e2address & 0x00FF) | ((state->m_e2data>>1) & 0x03) << 8;
1218		state->m_e2cnt   = 0;
1219		state->m_e2rw    = state->m_e2data & 1;
	1237	m_e2address = (m_e2address & 0x00FF) | ((m_e2data>>1) & 0x03) << 8;
	1238	m_e2cnt   = 0;
	1239	m_e2rw    = m_e2data & 1;
1220	1240
1221	1241	LOG(("e2ram: Slave address received !!  device id=%01X device adr=%01d high order adr %0X RW=%d) %02X\n",
1222		state->m_e2data>>4, (state->m_e2data & 0x08)?1:0, (state->m_e2data>>1) & 0x03, state->m_e2rw , state->m_e2data ));
	1242	m_e2data>>4, (m_e2data & 0x08)?1:0, (m_e2data>>1) & 0x03, m_e2rw , m_e2data ));
1223	1243
1224		state->m_e2state = 2;
	1244	m_e2state = 2;
1225	1245	}
1226	1246	break;
1227	1247
r14845	r14846
1230	1250	ack = recAck(changed,data);
1231	1251	if ( ack )
1232	1252	{
1233		state->m_e2data_pin = 0;
	1253	m_e2data_pin = 0;
1234	1254
1235	1255	if ( ack < 0 )
1236	1256	{
1237	1257	LOG(("ACK = 0\n"));
1238		state->m_e2state = 0;
	1258	m_e2state = 0;
1239	1259	}
1240	1260	else
1241	1261	{
1242	1262	LOG(("ACK = 1\n"));
1243		if ( state->m_e2dummywrite )
	1263	if ( m_e2dummywrite )
1244	1264	{
1245		state->m_e2dummywrite = 0;
	1265	m_e2dummywrite = 0;
1246	1266
1247		state->m_e2data_to_read = state->m_e2ram[state->m_e2address];
	1267	m_e2data_to_read = m_e2ram[m_e2address];
1248	1268
1249		if ( state->m_e2rw & 1 ) state->m_e2state = 7; // read data
1250		else        state->m_e2state = 0; //?not sure
	1269	if ( m_e2rw & 1 ) m_e2state = 7; // read data
	1270	else        m_e2state = 0; //?not sure
1251	1271	}
1252	1272	else
1253	1273	{
1254		if ( state->m_e2rw & 1 ) state->m_e2state = 7; // reading
1255		else            state->m_e2state = 3; // writing
	1274	if ( m_e2rw & 1 ) m_e2state = 7; // reading
	1275	else            m_e2state = 3; // writing
1256	1276	}
1257		switch ( state->m_e2state )
	1277	switch ( m_e2state )
1258	1278	{
1259	1279	case 7:
1260		LOG(("read address %04X\n",state->m_e2address));
1261		state->m_e2data_to_read = state->m_e2ram[state->m_e2address];
	1280	LOG(("read address %04X\n",m_e2address));
	1281	m_e2data_to_read = m_e2ram[m_e2address];
1262	1282	break;
1263	1283	case 3:
1264	1284	LOG(("write, awaiting address\n"));
1265	1285	break;
1266	1286	default:
1267		LOG(("?unknow action %04X\n",state->m_e2address));
	1287	LOG(("?unknow action %04X\n",m_e2address));
1268	1288	break;
1269	1289	}
1270	1290	}
1271		state->m_e2data = 0;
	1291	m_e2data = 0;
1272	1292	}
1273	1293	break;
1274	1294
1275	1295	case 3: // writing data, receiving address
1276	1296
1277		if ( recdata(state, changed, data) )
	1297	if ( recdata(changed, data) )
1278	1298	{
1279		state->m_e2data_pin = 0;
1280		state->m_e2address = (state->m_e2address & 0xFF00) | state->m_e2data;
	1299	m_e2data_pin = 0;
	1300	m_e2address = (m_e2address & 0xFF00) | m_e2data;
1281	1301
1282		LOG(("write address = %04X waiting for ACK\n", state->m_e2address));
1283		state->m_e2state = 4;
1284		state->m_e2cnt   = 0;
1285		state->m_e2data  = 0;
	1302	LOG(("write address = %04X waiting for ACK\n", m_e2address));
	1303	m_e2state = 4;
	1304	m_e2cnt   = 0;
	1305	m_e2data  = 0;
1286	1306	}
1287	1307	break;
1288	1308
r14845	r14846
1291	1311	ack = recAck(changed,data);
1292	1312	if ( ack )
1293	1313	{
1294		state->m_e2data_pin = 0;   // pin=0, no error !!
	1314	m_e2data_pin = 0;   // pin=0, no error !!
1295	1315
1296	1316	if ( ack < 0 )
1297	1317	{
1298		state->m_e2state = 0;
	1318	m_e2state = 0;
1299	1319	LOG(("ACK = 0, cancel write\n" ));
1300	1320	}
1301	1321	else
1302	1322	{
1303		state->m_e2state = 5;
	1323	m_e2state = 5;
1304	1324	LOG(("ACK = 1, awaiting data to write\n" ));
1305	1325	}
1306	1326	}
1307	1327	break;
1308	1328
1309	1329	case 5: // receive data to write
1310		if ( recdata(state, changed, data) )
	1330	if ( recdata(changed, data) )
1311	1331	{
1312		LOG(("write data = %02X received, awaiting ACK\n", state->m_e2data));
1313		state->m_e2cnt   = 0;
1314		state->m_e2state = 6;  // wait ack
	1332	LOG(("write data = %02X received, awaiting ACK\n", m_e2data));
	1333	m_e2cnt   = 0;
	1334	m_e2state = 6;  // wait ack
1315	1335	}
1316	1336	break;
1317	1337
r14845	r14846
1322	1342	{
1323	1343	if ( ack < 0 )
1324	1344	{
1325		state->m_e2state = 0;
	1345	m_e2state = 0;
1326	1346	LOG(("ACK=0, write canceled\n"));
1327	1347	}
1328	1348	else
1329	1349	{
1330		LOG(("ACK=1, writing %02X to %04X\n", state->m_e2data, state->m_e2address));
	1350	LOG(("ACK=1, writing %02X to %04X\n", m_e2data, m_e2address));
1331	1351
1332		state->m_e2ram[state->m_e2address] = state->m_e2data;
	1352	m_e2ram[m_e2address] = m_e2data;
1333	1353
1334		state->m_e2address = (state->m_e2address & ~0x000F) | ((state->m_e2address+1)&0x0F);
	1354	m_e2address = (m_e2address & ~0x000F) | ((m_e2address+1)&0x0F);
1335	1355
1336		state->m_e2state = 5; // write next address
	1356	m_e2state = 5; // write next address
1337	1357	}
1338	1358	}
1339	1359	break;
1340	1360
1341	1361	case 7: // receive address from read
1342	1362
1343		if ( recdata(state, changed, data) )
	1363	if ( recdata(changed, data) )
1344	1364	{
1345		//state->m_e2data_pin = 0;
	1365	//m_e2data_pin = 0;
1346	1366
1347		LOG(("address read, data = %02X waiting for ACK\n", state->m_e2data ));
	1367	LOG(("address read, data = %02X waiting for ACK\n", m_e2data ));
1348	1368
1349		state->m_e2state = 8;
	1369	m_e2state = 8;
1350	1370	}
1351	1371	break;
1352	1372
r14845	r14846
1354	1374
1355	1375	if ( recAck(changed, data) )
1356	1376	{
1357		state->m_e2state = 7;
	1377	m_e2state = 7;
1358	1378
1359		state->m_e2address = (state->m_e2address & ~0x0F) | ((state->m_e2address+1)&0x0F); // lower 4 bits wrap around
	1379	m_e2address = (m_e2address & ~0x0F) | ((m_e2address+1)&0x0F); // lower 4 bits wrap around
1360	1380
1361		state->m_e2data_to_read = state->m_e2ram[state->m_e2address];
	1381	m_e2data_to_read = m_e2ram[m_e2address];
1362	1382
1363		LOG(("ready for next address %04X\n", state->m_e2address));
	1383	LOG(("ready for next address %04X\n", m_e2address));
1364	1384
1365		state->m_e2cnt   = 0;
1366		state->m_e2data  = 0;
	1385	m_e2cnt   = 0;
	1386	m_e2data  = 0;
1367	1387	}
1368	1388	break;
1369	1389
r14845	r14846
1413	1433	}
1414	1434
1415	1435
1416		static READ8_HANDLER( direct_input_r )
	1436	READ8_MEMBER(bfm_sc2_state::direct_input_r)
1417	1437	{
1418	1438	return 0;
1419	1439	}
r14845	r14846
1423	1443
1424	1444	static ADDRESS_MAP_START( sc2_basemap, AS_PROGRAM, 8, bfm_sc2_state )
1425	1445	AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("nvram") //8k
1426		AM_RANGE(0x2000, 0x2000) AM_READ_LEGACY(vfd_status_r)
1427		AM_RANGE(0x2000, 0x20FF) AM_WRITE_LEGACY(reel12_w)
1428		AM_RANGE(0x2100, 0x21FF) AM_WRITE_LEGACY(reel34_w)
1429		AM_RANGE(0x2200, 0x22FF) AM_WRITE_LEGACY(reel56_w)
	1446	AM_RANGE(0x2000, 0x2000) AM_READ(vfd_status_r)
	1447	AM_RANGE(0x2000, 0x20FF) AM_WRITE(reel12_w)
	1448	AM_RANGE(0x2100, 0x21FF) AM_WRITE(reel34_w)
	1449	AM_RANGE(0x2200, 0x22FF) AM_WRITE(reel56_w)
1430	1450
1431		AM_RANGE(0x2300, 0x230B) AM_READ_LEGACY(mux_input_r)
1432		AM_RANGE(0x2300, 0x231F) AM_WRITE_LEGACY(mux_output_w)
1433		AM_RANGE(0x2320, 0x2323) AM_WRITE_LEGACY(dimas_w)            /* ?unknown dim related */
	1451	AM_RANGE(0x2300, 0x230B) AM_READ(mux_input_r)
	1452	AM_RANGE(0x2300, 0x231F) AM_WRITE(mux_output_w)
	1453	AM_RANGE(0x2320, 0x2323) AM_WRITE(dimas_w)            /* ?unknown dim related */
1434	1454
1435		AM_RANGE(0x2324, 0x2324) AM_READWRITE_LEGACY(expansion_latch_r, expansion_latch_w)
1436		AM_RANGE(0x2325, 0x2327) AM_WRITE_LEGACY(unknown_w)
1437		AM_RANGE(0x2328, 0x2328) AM_WRITE_LEGACY(muxena_w)
1438		AM_RANGE(0x2329, 0x2329) AM_READWRITE_LEGACY(timerirqclr_r, timerirq_w)
1439		AM_RANGE(0x232A, 0x232D) AM_WRITE_LEGACY(unknown_w)
1440		AM_RANGE(0x232E, 0x232E) AM_READ_LEGACY(irqstatus_r)
	1455	AM_RANGE(0x2324, 0x2324) AM_READWRITE(expansion_latch_r, expansion_latch_w)
	1456	AM_RANGE(0x2325, 0x2327) AM_WRITE(unknown_w)
	1457	AM_RANGE(0x2328, 0x2328) AM_WRITE(muxena_w)
	1458	AM_RANGE(0x2329, 0x2329) AM_READWRITE(timerirqclr_r, timerirq_w)
	1459	AM_RANGE(0x232A, 0x232D) AM_WRITE(unknown_w)
	1460	AM_RANGE(0x232E, 0x232E) AM_READ(irqstatus_r)
1441	1461
1442		AM_RANGE(0x232F, 0x232F) AM_WRITE_LEGACY(coininhib_w)
1443		AM_RANGE(0x2330, 0x2330) AM_WRITE_LEGACY(payout_latch_w)
1444		AM_RANGE(0x2331, 0x2331) AM_WRITE_LEGACY(payout_triac_w)
	1462	AM_RANGE(0x232F, 0x232F) AM_WRITE(coininhib_w)
	1463	AM_RANGE(0x2330, 0x2330) AM_WRITE(payout_latch_w)
	1464	AM_RANGE(0x2331, 0x2331) AM_WRITE(payout_triac_w)
1445	1465	AM_RANGE(0x2332, 0x2332) AM_WRITE_LEGACY(watchdog_reset_w)
1446		AM_RANGE(0x2333, 0x2333) AM_WRITE_LEGACY(mmtr_w)
1447		AM_RANGE(0x2334, 0x2335) AM_WRITE_LEGACY(unknown_w)
1448		AM_RANGE(0x2336, 0x2336) AM_WRITE_LEGACY(dimcnt_w)
1449		AM_RANGE(0x2337, 0x2337) AM_WRITE_LEGACY(volume_override_w)
1450		AM_RANGE(0x2338, 0x2338) AM_WRITE_LEGACY(payout_select_w)
1451		AM_RANGE(0x2339, 0x2339) AM_WRITE_LEGACY(unknown_w)
1452		AM_RANGE(0x2400, 0x2400) AM_READWRITE_LEGACY(uart1stat_r, uart1ctrl_w)   /* mc6850 compatible uart */
1453		AM_RANGE(0x2500, 0x2500) AM_READWRITE_LEGACY(uart1data_r, uart1data_w)
1454		AM_RANGE(0x2600, 0x2600) AM_READWRITE_LEGACY(uart2stat_r, uart2ctrl_w)   /* mc6850 compatible uart */
1455		AM_RANGE(0x2700, 0x2700) AM_READWRITE_LEGACY(uart2data_r, uart2data_w)
1456		AM_RANGE(0x2800, 0x2800) AM_WRITE_LEGACY(vfd1_data_w)               /* vfd1 data */
1457		AM_RANGE(0x2900, 0x2900) AM_WRITE_LEGACY(vfd_reset_w)               /* vfd1+vfd2 reset line */
	1466	AM_RANGE(0x2333, 0x2333) AM_WRITE(mmtr_w)
	1467	AM_RANGE(0x2334, 0x2335) AM_WRITE(unknown_w)
	1468	AM_RANGE(0x2336, 0x2336) AM_WRITE(dimcnt_w)
	1469	AM_RANGE(0x2337, 0x2337) AM_WRITE(volume_override_w)
	1470	AM_RANGE(0x2338, 0x2338) AM_WRITE(payout_select_w)
	1471	AM_RANGE(0x2339, 0x2339) AM_WRITE(unknown_w)
	1472	AM_RANGE(0x2400, 0x2400) AM_READWRITE(uart1stat_r, uart1ctrl_w)   /* mc6850 compatible uart */
	1473	AM_RANGE(0x2500, 0x2500) AM_READWRITE(uart1data_r, uart1data_w)
	1474	AM_RANGE(0x2600, 0x2600) AM_READWRITE(uart2stat_r, uart2ctrl_w)   /* mc6850 compatible uart */
	1475	AM_RANGE(0x2700, 0x2700) AM_READWRITE(uart2data_r, uart2data_w)
	1476	AM_RANGE(0x2800, 0x2800) AM_WRITE(vfd1_data_w)               /* vfd1 data */
	1477	AM_RANGE(0x2900, 0x2900) AM_WRITE(vfd_reset_w)               /* vfd1+vfd2 reset line */
1458	1478	AM_RANGE(0x2A00, 0x2AFF) AM_DEVWRITE_LEGACY("upd", nec_latch_w)
1459	1479	AM_RANGE(0x2B00, 0x2BFF) AM_DEVWRITE_LEGACY("upd", nec_reset_w)
1460		AM_RANGE(0x2C00, 0x2C00) AM_WRITE_LEGACY(unlock_w)                  /* custom chip unlock */
	1480	AM_RANGE(0x2C00, 0x2C00) AM_WRITE(unlock_w)                  /* custom chip unlock */
1461	1481	AM_RANGE(0x2D00, 0x2D01) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w)
1462		AM_RANGE(0x2E00, 0x2E00) AM_WRITE_LEGACY(bankswitch_w)               /* write bank (rom page select for 0x6000 - 0x7fff ) */
1463		AM_RANGE(0x2F00, 0x2F00) AM_WRITE_LEGACY(vfd2_data_w)               /* vfd2 data */
	1482	AM_RANGE(0x2E00, 0x2E00) AM_WRITE(bankswitch_w)               /* write bank (rom page select for 0x6000 - 0x7fff ) */
	1483	AM_RANGE(0x2F00, 0x2F00) AM_WRITE(vfd2_data_w)               /* vfd2 data */
1464	1484
1465		AM_RANGE(0x3FFE, 0x3FFE) AM_READ_LEGACY(direct_input_r )
1466		AM_RANGE(0x3FFF, 0x3FFF) AM_READ_LEGACY(coin_input_r)
	1485	AM_RANGE(0x3FFE, 0x3FFE) AM_READ(direct_input_r )
	1486	AM_RANGE(0x3FFF, 0x3FFF) AM_READ(coin_input_r)
1467	1487	AM_RANGE(0x4000, 0x5FFF) AM_ROM
1468		AM_RANGE(0x4000, 0xFFFF) AM_WRITE_LEGACY(unknown_w)         // contains unknown I/O registers
	1488	AM_RANGE(0x4000, 0xFFFF) AM_WRITE(unknown_w)         // contains unknown I/O registers
1469	1489	AM_RANGE(0x6000, 0x7FFF) AM_ROMBANK("bank1")
1470	1490	AM_RANGE(0x8000, 0xFFFF) AM_ROM
1471	1491	ADDRESS_MAP_END
r14845	r14846
1475	1495	static ADDRESS_MAP_START( memmap_vid, AS_PROGRAM, 8, bfm_sc2_state )
1476	1496	AM_IMPORT_FROM( sc2_basemap )
1477	1497
1478		AM_RANGE(0x2000, 0x2000) AM_READ_LEGACY(vfd_status_hop_r)      // vfd status register
1479		AM_RANGE(0x2000, 0x20FF) AM_WRITE_LEGACY(reel12_vid_w)
	1498	AM_RANGE(0x2000, 0x2000) AM_READ(vfd_status_hop_r)      // vfd status register
	1499	AM_RANGE(0x2000, 0x20FF) AM_WRITE(reel12_vid_w)
1480	1500	AM_RANGE(0x2100, 0x21FF) AM_WRITENOP
1481	1501	AM_RANGE(0x2200, 0x22FF) AM_WRITENOP
1482	1502
1483		AM_RANGE(0x3C00, 0x3C07) AM_READ_LEGACY(key_r   )
1484		AM_RANGE(0x3C80, 0x3C80) AM_WRITE_LEGACY(e2ram_w )
	1503	AM_RANGE(0x3C00, 0x3C07) AM_READ(key_r   )
	1504	AM_RANGE(0x3C80, 0x3C80) AM_WRITE(e2ram_w )
1485	1505
1486		AM_RANGE(0x3E00, 0x3E00) AM_READWRITE_LEGACY(vid_uart_ctrl_r, vid_uart_ctrl_w)      // video uart control reg
1487		AM_RANGE(0x3E01, 0x3E01) AM_READWRITE_LEGACY(vid_uart_rx_r, vid_uart_tx_w)         // video uart data  reg
	1506	AM_RANGE(0x3E00, 0x3E00) AM_READWRITE(vid_uart_ctrl_r, vid_uart_ctrl_w)      // video uart control reg
	1507	AM_RANGE(0x3E01, 0x3E01) AM_READWRITE(vid_uart_rx_r, vid_uart_tx_w)         // video uart data  reg
1488	1508	ADDRESS_MAP_END
1489	1509
1490	1510	// input ports for pyramid ////////////////////////////////////////
r14845	r14846
2546	2566
2547	2567	#ifdef UNUSED_FUNCTION
2548	2568	/* Scorpion 3 expansion */
2549		static READ8_HANDLER( sc3_expansion_r )
	2569	READ8_MEMBER(bfm_sc2_state::sc3_expansion_r)
2550	2570	{
2551	2571	int result = 0;
2552	2572
r14845	r14846
2561	2581	}
2562	2582
2563	2583
2564		static WRITE8_HANDLER( sc3_expansion_w )
	2584	WRITE8_MEMBER(bfm_sc2_state::sc3_expansion_w)
2565	2585	{
2566	2586	switch ( offset )
2567	2587	{

src/mame/drivers/tmmjprd.c

r14845	r14846
49	49	UINT8 m_system_in;
50	50	double m_old_brt1;
51	51	double m_old_brt2;
	52	DECLARE_WRITE32_MEMBER(tmmjprd_tilemap0_w);
	53	DECLARE_WRITE32_MEMBER(tmmjprd_tilemap1_w);
	54	DECLARE_WRITE32_MEMBER(tmmjprd_tilemap2_w);
	55	DECLARE_WRITE32_MEMBER(tmmjprd_tilemap3_w);
	56	DECLARE_READ32_MEMBER(tmmjprd_tilemap0_r);
	57	DECLARE_READ32_MEMBER(tmmjprd_tilemap1_r);
	58	DECLARE_READ32_MEMBER(tmmjprd_tilemap2_r);
	59	DECLARE_READ32_MEMBER(tmmjprd_tilemap3_r);
	60	DECLARE_READ32_MEMBER(randomtmmjprds);
	61	DECLARE_WRITE32_MEMBER(tmmjprd_blitter_w);
	62	DECLARE_READ32_MEMBER(tmmjprd_mux_r);
	63	DECLARE_WRITE32_MEMBER(tmmjprd_paletteram_dword_w);
	64	DECLARE_WRITE32_MEMBER(tmmjprd_brt_1_w);
	65	DECLARE_WRITE32_MEMBER(tmmjprd_brt_2_w);
52	66	};
53	67
54	68
55		static WRITE32_HANDLER( tmmjprd_tilemap0_w )
	69	WRITE32_MEMBER(tmmjprd_state::tmmjprd_tilemap0_w)
56	70	{
57		tmmjprd_state *state = space->machine().driver_data<tmmjprd_state>();
58		COMBINE_DATA(&state->m_tilemap_ram[0][offset]);
	71	COMBINE_DATA(&m_tilemap_ram[0][offset]);
59	72	}
60	73
61	74
62	75
63		static WRITE32_HANDLER( tmmjprd_tilemap1_w )
	76	WRITE32_MEMBER(tmmjprd_state::tmmjprd_tilemap1_w)
64	77	{
65		tmmjprd_state *state = space->machine().driver_data<tmmjprd_state>();
66		COMBINE_DATA(&state->m_tilemap_ram[1][offset]);
	78	COMBINE_DATA(&m_tilemap_ram[1][offset]);
67	79	}
68	80
69		static WRITE32_HANDLER( tmmjprd_tilemap2_w )
	81	WRITE32_MEMBER(tmmjprd_state::tmmjprd_tilemap2_w)
70	82	{
71		tmmjprd_state *state = space->machine().driver_data<tmmjprd_state>();
72		COMBINE_DATA(&state->m_tilemap_ram[2][offset]);
	83	COMBINE_DATA(&m_tilemap_ram[2][offset]);
73	84	}
74	85
75		static WRITE32_HANDLER( tmmjprd_tilemap3_w )
	86	WRITE32_MEMBER(tmmjprd_state::tmmjprd_tilemap3_w)
76	87	{
77		tmmjprd_state *state = space->machine().driver_data<tmmjprd_state>();
78		COMBINE_DATA(&state->m_tilemap_ram[3][offset]);
	88	COMBINE_DATA(&m_tilemap_ram[3][offset]);
79	89	}
80	90
81	91	static void draw_sprites(running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect, int screen)
r14845	r14846
335	345	state->m_tilemap_ram[3] = auto_alloc_array_clear(machine, UINT32, 0x8000);
336	346	}
337	347
338		static READ32_HANDLER( tmmjprd_tilemap0_r )
	348	READ32_MEMBER(tmmjprd_state::tmmjprd_tilemap0_r)
339	349	{
340		tmmjprd_state *state = space->machine().driver_data<tmmjprd_state>();
341		return state->m_tilemap_ram[0][offset];
	350	return m_tilemap_ram[0][offset];
342	351	}
343	352
344		static READ32_HANDLER( tmmjprd_tilemap1_r )
	353	READ32_MEMBER(tmmjprd_state::tmmjprd_tilemap1_r)
345	354	{
346		tmmjprd_state *state = space->machine().driver_data<tmmjprd_state>();
347		return state->m_tilemap_ram[1][offset];
	355	return m_tilemap_ram[1][offset];
348	356	}
349	357
350		static READ32_HANDLER( tmmjprd_tilemap2_r )
	358	READ32_MEMBER(tmmjprd_state::tmmjprd_tilemap2_r)
351	359	{
352		tmmjprd_state *state = space->machine().driver_data<tmmjprd_state>();
353		return state->m_tilemap_ram[2][offset];
	360	return m_tilemap_ram[2][offset];
354	361	}
355	362
356		static READ32_HANDLER( tmmjprd_tilemap3_r )
	363	READ32_MEMBER(tmmjprd_state::tmmjprd_tilemap3_r)
357	364	{
358		tmmjprd_state *state = space->machine().driver_data<tmmjprd_state>();
359		return state->m_tilemap_ram[3][offset];
	365	return m_tilemap_ram[3][offset];
360	366	}
361	367
362		static READ32_HANDLER( randomtmmjprds )
	368	READ32_MEMBER(tmmjprd_state::randomtmmjprds)
363	369	{
364		return 0x0000;//space->machine().rand();
	370	return 0x0000;//machine().rand();
365	371	}
366	372
367	373
r14845	r14846
470	476
471	477
472	478
473		static WRITE32_HANDLER( tmmjprd_blitter_w )
	479	WRITE32_MEMBER(tmmjprd_state::tmmjprd_blitter_w)
474	480	{
475	481	COMBINE_DATA(&tmmjprd_blitterregs[offset]);
476	482
477	483	if (offset == 0x0c/4)
478	484	{
479		tmmjprd_do_blit(space->machine());
	485	tmmjprd_do_blit(machine());
480	486	}
481	487	}
482	488	#endif
r14845	r14846
504	510	}
505	511	}
506	512
507		static READ32_HANDLER( tmmjprd_mux_r )
	513	READ32_MEMBER(tmmjprd_state::tmmjprd_mux_r)
508	514	{
509		tmmjprd_state *state = space->machine().driver_data<tmmjprd_state>();
510	515
511		state->m_system_in = input_port_read(space->machine(), "SYSTEM");
	516	m_system_in = input_port_read(machine(), "SYSTEM");
512	517
513		switch(state->m_mux_data)
	518	switch(m_mux_data)
514	519	{
515		case 0x01: return (state->m_system_in & 0xff) | (input_port_read(space->machine(), "PL1_1")<<8) | (input_port_read(space->machine(), "PL2_1")<<16) | 0xff000000;
516		case 0x02: return (state->m_system_in & 0xff) | (input_port_read(space->machine(), "PL1_2")<<8) | (input_port_read(space->machine(), "PL2_2")<<16) | 0xff000000;
517		case 0x04: return (state->m_system_in & 0xff) | (input_port_read(space->machine(), "PL1_3")<<8) | (input_port_read(space->machine(), "PL2_3")<<16) | 0xff000000;
518		case 0x08: return (state->m_system_in & 0xff) | (input_port_read(space->machine(), "PL1_4")<<8) | (input_port_read(space->machine(), "PL2_4")<<16) | 0xff000000;
519		case 0x10: return (state->m_system_in & 0xff) | (input_port_read(space->machine(), "PL1_5")<<8) | (input_port_read(space->machine(), "PL2_5")<<16) | 0xff000000;
	520	case 0x01: return (m_system_in & 0xff) | (input_port_read(machine(), "PL1_1")<<8) | (input_port_read(machine(), "PL2_1")<<16) | 0xff000000;
	521	case 0x02: return (m_system_in & 0xff) | (input_port_read(machine(), "PL1_2")<<8) | (input_port_read(machine(), "PL2_2")<<16) | 0xff000000;
	522	case 0x04: return (m_system_in & 0xff) | (input_port_read(machine(), "PL1_3")<<8) | (input_port_read(machine(), "PL2_3")<<16) | 0xff000000;
	523	case 0x08: return (m_system_in & 0xff) | (input_port_read(machine(), "PL1_4")<<8) | (input_port_read(machine(), "PL2_4")<<16) | 0xff000000;
	524	case 0x10: return (m_system_in & 0xff) | (input_port_read(machine(), "PL1_5")<<8) | (input_port_read(machine(), "PL2_5")<<16) | 0xff000000;
520	525	}
521	526
522		return (state->m_system_in & 0xff) | 0xffffff00;
	527	return (m_system_in & 0xff) | 0xffffff00;
523	528	}
524	529
525	530	static INPUT_PORTS_START( tmmjprd )
r14845	r14846
609	614	INPUT_PORTS_END
610	615
611	616
612		static WRITE32_HANDLER( tmmjprd_paletteram_dword_w )
	617	WRITE32_MEMBER(tmmjprd_state::tmmjprd_paletteram_dword_w)
613	618	{
614	619	int r,g,b;
615		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
	620	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
616	621
617		b = ((space->machine().generic.paletteram.u32[offset] & 0x000000ff) >>0);
618		r = ((space->machine().generic.paletteram.u32[offset] & 0x0000ff00) >>8);
619		g = ((space->machine().generic.paletteram.u32[offset] & 0x00ff0000) >>16);
	622	b = ((machine().generic.paletteram.u32[offset] & 0x000000ff) >>0);
	623	r = ((machine().generic.paletteram.u32[offset] & 0x0000ff00) >>8);
	624	g = ((machine().generic.paletteram.u32[offset] & 0x00ff0000) >>16);
620	625
621		palette_set_color(space->machine(),offset,MAKE_RGB(r,g,b));
	626	palette_set_color(machine(),offset,MAKE_RGB(r,g,b));
622	627	}
623	628
624	629
625	630	/* notice that data & 0x4 is always cleared on brt_1 and set on brt_2.        *
626	631	* My wild guess is that bits 0,1 and 2 controls what palette entries to dim. */
627		static WRITE32_HANDLER( tmmjprd_brt_1_w )
	632	WRITE32_MEMBER(tmmjprd_state::tmmjprd_brt_1_w)
628	633	{
629		tmmjprd_state *state = space->machine().driver_data<tmmjprd_state>();
630	634	int i;
631	635	double brt;
632	636	int bank;
r14845	r14846
635	639	brt = ((data & 0x78)>>3) / 15.0;
636	640	bank = data & 0x4 ? 0x800 : 0; //guess
637	641
638		if(data & 0x80 && state->m_old_brt1 != brt)
	642	if(data & 0x80 && m_old_brt1 != brt)
639	643	{
640		state->m_old_brt1 = brt;
	644	m_old_brt1 = brt;
641	645	for (i = bank; i < 0x800+bank; i++)
642		palette_set_pen_contrast(space->machine(), i, brt);
	646	palette_set_pen_contrast(machine(), i, brt);
643	647	}
644	648	}
645	649
646		static WRITE32_HANDLER( tmmjprd_brt_2_w )
	650	WRITE32_MEMBER(tmmjprd_state::tmmjprd_brt_2_w)
647	651	{
648		tmmjprd_state *state = space->machine().driver_data<tmmjprd_state>();
649	652	int i;
650	653	double brt;
651	654	int bank;
r14845	r14846
654	657	brt = ((data & 0x78)>>3) / 15.0;
655	658	bank = data & 0x4 ? 0x800 : 0; //guess
656	659
657		if(data & 0x80 && state->m_old_brt2 != brt)
	660	if(data & 0x80 && m_old_brt2 != brt)
658	661	{
659		state->m_old_brt2 = brt;
	662	m_old_brt2 = brt;
660	663	for (i = bank; i < 0x800+bank; i++)
661		palette_set_pen_contrast(space->machine(), i, brt);
	664	palette_set_pen_contrast(machine(), i, brt);
662	665	}
663	666	}
664	667
665	668	static ADDRESS_MAP_START( tmmjprd_map, AS_PROGRAM, 32, tmmjprd_state )
666	669	AM_RANGE(0x000000, 0x1fffff) AM_ROM
667		AM_RANGE(0x200010, 0x200013) AM_READ_LEGACY(randomtmmjprds) // gfx chip status?
668		AM_RANGE(0x200980, 0x200983) AM_READ_LEGACY(randomtmmjprds) // sound chip status?
669		AM_RANGE(0x200984, 0x200987) AM_READ_LEGACY(randomtmmjprds) // sound chip status?
	670	AM_RANGE(0x200010, 0x200013) AM_READ(randomtmmjprds) // gfx chip status?
	671	AM_RANGE(0x200980, 0x200983) AM_READ(randomtmmjprds) // sound chip status?
	672	AM_RANGE(0x200984, 0x200987) AM_READ(randomtmmjprds) // sound chip status?
670	673	/* check these are used .. */
671	674	//  AM_RANGE(0x200010, 0x200013) AM_WRITEONLY AM_BASE_LEGACY(&tmmjprd_viewregs0 )
672	675	AM_RANGE(0x200100, 0x200117) AM_WRITEONLY AM_BASE(m_tilemap_regs[0] ) // tilemap regs1
r14845	r14846
675	678	AM_RANGE(0x200160, 0x200177) AM_WRITEONLY AM_BASE(m_tilemap_regs[3] ) // tilemap regs4
676	679	AM_RANGE(0x200200, 0x20021b) AM_WRITEONLY AM_BASE(m_spriteregs ) // sprregs?
677	680	//  AM_RANGE(0x200300, 0x200303) AM_WRITE_LEGACY(tmmjprd_rombank_w) // used during rom testing, rombank/area select + something else?
678		AM_RANGE(0x20040c, 0x20040f) AM_WRITE_LEGACY(tmmjprd_brt_1_w)
679		AM_RANGE(0x200410, 0x200413) AM_WRITE_LEGACY(tmmjprd_brt_2_w)
	681	AM_RANGE(0x20040c, 0x20040f) AM_WRITE(tmmjprd_brt_1_w)
	682	AM_RANGE(0x200410, 0x200413) AM_WRITE(tmmjprd_brt_2_w)
680	683	//  AM_RANGE(0x200500, 0x200503) AM_WRITEONLY AM_BASE_LEGACY(&tmmjprd_viewregs7 )
681		//  AM_RANGE(0x200700, 0x20070f) AM_WRITE_LEGACY(tmmjprd_blitter_w) AM_BASE_LEGACY(&tmmjprd_blitterregs )
	684	//  AM_RANGE(0x200700, 0x20070f) AM_WRITE(tmmjprd_blitter_w) AM_BASE_LEGACY(&tmmjprd_blitterregs )
682	685	//  AM_RANGE(0x200800, 0x20080f) AM_WRITEONLY AM_BASE_LEGACY(&tmmjprd_viewregs9 ) // never changes?
683	686	//  AM_RANGE(0x200900, 0x20098f) AM_WRITE_LEGACY(tmmjprd_audio_w)
684	687	/* hmm */
685	688	//  AM_RANGE(0x279700, 0x279713) AM_WRITEONLY AM_BASE_LEGACY(&tmmjprd_viewregs10 )
686	689	/* tilemaps */
687		AM_RANGE(0x280000, 0x283fff) AM_READWRITE_LEGACY(tmmjprd_tilemap0_r,tmmjprd_tilemap0_w)
688		AM_RANGE(0x284000, 0x287fff) AM_READWRITE_LEGACY(tmmjprd_tilemap1_r,tmmjprd_tilemap1_w)
689		AM_RANGE(0x288000, 0x28bfff) AM_READWRITE_LEGACY(tmmjprd_tilemap2_r,tmmjprd_tilemap2_w)
690		AM_RANGE(0x28c000, 0x28ffff) AM_READWRITE_LEGACY(tmmjprd_tilemap3_r,tmmjprd_tilemap3_w)
	690	AM_RANGE(0x280000, 0x283fff) AM_READWRITE(tmmjprd_tilemap0_r,tmmjprd_tilemap0_w)
	691	AM_RANGE(0x284000, 0x287fff) AM_READWRITE(tmmjprd_tilemap1_r,tmmjprd_tilemap1_w)
	692	AM_RANGE(0x288000, 0x28bfff) AM_READWRITE(tmmjprd_tilemap2_r,tmmjprd_tilemap2_w)
	693	AM_RANGE(0x28c000, 0x28ffff) AM_READWRITE(tmmjprd_tilemap3_r,tmmjprd_tilemap3_w)
691	694	/* ?? is palette ram shared with sprites in this case or just a different map */
692	695	AM_RANGE(0x290000, 0x29bfff) AM_RAM AM_BASE(m_spriteram)
693		AM_RANGE(0x29c000, 0x29ffff) AM_RAM_WRITE_LEGACY(tmmjprd_paletteram_dword_w) AM_BASE_GENERIC(paletteram)
	696	AM_RANGE(0x29c000, 0x29ffff) AM_RAM_WRITE(tmmjprd_paletteram_dword_w) AM_BASE_GENERIC(paletteram)
694	697
695		AM_RANGE(0x400000, 0x400003) AM_READ_LEGACY(tmmjprd_mux_r) AM_DEVWRITE_LEGACY("eeprom", tmmjprd_eeprom_write)
	698	AM_RANGE(0x400000, 0x400003) AM_READ(tmmjprd_mux_r) AM_DEVWRITE_LEGACY("eeprom", tmmjprd_eeprom_write)
696	699	AM_RANGE(0xf00000, 0xffffff) AM_RAM
697	700	ADDRESS_MAP_END
698	701

src/mame/drivers/witch.c

r14845	r14846
214	214	int m_scrolly;
215	215	UINT8 m_reg_a002;
216	216	int m_bank;
	217	DECLARE_WRITE8_MEMBER(gfx0_vram_w);
	218	DECLARE_WRITE8_MEMBER(gfx0_cram_w);
	219	DECLARE_READ8_MEMBER(gfx0_vram_r);
	220	DECLARE_READ8_MEMBER(gfx0_cram_r);
	221	DECLARE_WRITE8_MEMBER(gfx1_vram_w);
	222	DECLARE_WRITE8_MEMBER(gfx1_cram_w);
	223	DECLARE_READ8_MEMBER(gfx1_vram_r);
	224	DECLARE_READ8_MEMBER(gfx1_cram_r);
	225	DECLARE_READ8_MEMBER(read_a00x);
	226	DECLARE_WRITE8_MEMBER(write_a00x);
	227	DECLARE_READ8_MEMBER(prot_read_700x);
217	228	};
218	229
219	230
r14845	r14846
273	284	0);
274	285	}
275	286
276		static WRITE8_HANDLER( gfx0_vram_w )
	287	WRITE8_MEMBER(witch_state::gfx0_vram_w)
277	288	{
278		witch_state *state = space->machine().driver_data<witch_state>();
279		state->m_gfx0_vram[offset] = data;
280		state->m_gfx0a_tilemap->mark_tile_dirty(offset);
281		state->m_gfx0b_tilemap->mark_tile_dirty(offset);
	289	m_gfx0_vram[offset] = data;
	290	m_gfx0a_tilemap->mark_tile_dirty(offset);
	291	m_gfx0b_tilemap->mark_tile_dirty(offset);
282	292	}
283	293
284		static WRITE8_HANDLER( gfx0_cram_w )
	294	WRITE8_MEMBER(witch_state::gfx0_cram_w)
285	295	{
286		witch_state *state = space->machine().driver_data<witch_state>();
287		state->m_gfx0_cram[offset] = data;
288		state->m_gfx0a_tilemap->mark_tile_dirty(offset);
289		state->m_gfx0b_tilemap->mark_tile_dirty(offset);
	296	m_gfx0_cram[offset] = data;
	297	m_gfx0a_tilemap->mark_tile_dirty(offset);
	298	m_gfx0b_tilemap->mark_tile_dirty(offset);
290	299	}
291		static READ8_HANDLER( gfx0_vram_r )
	300	READ8_MEMBER(witch_state::gfx0_vram_r)
292	301	{
293		witch_state *state = space->machine().driver_data<witch_state>();
294		return state->m_gfx0_vram[offset];
	302	return m_gfx0_vram[offset];
295	303	}
296	304
297		static READ8_HANDLER( gfx0_cram_r )
	305	READ8_MEMBER(witch_state::gfx0_cram_r)
298	306	{
299		witch_state *state = space->machine().driver_data<witch_state>();
300		return state->m_gfx0_cram[offset];
	307	return m_gfx0_cram[offset];
301	308	}
302	309
303	310	#define FIX_OFFSET() do { \
304		offset=(((offset + ((state->m_scrolly & 0xf8) << 2) ) & 0x3e0)+((offset + (state->m_scrollx >> 3) ) & 0x1f)+32)&0x3ff; } while(0)
	311	offset=(((offset + ((m_scrolly & 0xf8) << 2) ) & 0x3e0)+((offset + (m_scrollx >> 3) ) & 0x1f)+32)&0x3ff; } while(0)
305	312
306		static WRITE8_HANDLER( gfx1_vram_w )
	313	WRITE8_MEMBER(witch_state::gfx1_vram_w)
307	314	{
308		witch_state *state = space->machine().driver_data<witch_state>();
309	315	FIX_OFFSET();
310		state->m_gfx1_vram[offset] = data;
311		state->m_gfx1_tilemap->mark_tile_dirty(offset);
	316	m_gfx1_vram[offset] = data;
	317	m_gfx1_tilemap->mark_tile_dirty(offset);
312	318	}
313	319
314		static WRITE8_HANDLER( gfx1_cram_w )
	320	WRITE8_MEMBER(witch_state::gfx1_cram_w)
315	321	{
316		witch_state *state = space->machine().driver_data<witch_state>();
317	322	FIX_OFFSET();
318		state->m_gfx1_cram[offset] = data;
319		state->m_gfx1_tilemap->mark_tile_dirty(offset);
	323	m_gfx1_cram[offset] = data;
	324	m_gfx1_tilemap->mark_tile_dirty(offset);
320	325	}
321		static READ8_HANDLER( gfx1_vram_r )
	326	READ8_MEMBER(witch_state::gfx1_vram_r)
322	327	{
323		witch_state *state = space->machine().driver_data<witch_state>();
324	328	FIX_OFFSET();
325		return state->m_gfx1_vram[offset];
	329	return m_gfx1_vram[offset];
326	330	}
327	331
328		static READ8_HANDLER( gfx1_cram_r )
	332	READ8_MEMBER(witch_state::gfx1_cram_r)
329	333	{
330		witch_state *state = space->machine().driver_data<witch_state>();
331	334	FIX_OFFSET();
332		return state->m_gfx1_cram[offset];
	335	return m_gfx1_cram[offset];
333	336	}
334	337
335		static READ8_HANDLER(read_a00x)
	338	READ8_MEMBER(witch_state::read_a00x)
336	339	{
337		witch_state *state = space->machine().driver_data<witch_state>();
338	340	switch(offset)
339	341	{
340		case 0x02: return state->m_reg_a002;
341		case 0x04: return input_port_read(space->machine(), "A004");
342		case 0x05: return input_port_read(space->machine(), "A005");
343		case 0x0c: return input_port_read(space->machine(), "SERVICE");   // stats / reset
344		case 0x0e: return input_port_read(space->machine(), "A00E");      // coin/reset
	342	case 0x02: return m_reg_a002;
	343	case 0x04: return input_port_read(machine(), "A004");
	344	case 0x05: return input_port_read(machine(), "A005");
	345	case 0x0c: return input_port_read(machine(), "SERVICE");   // stats / reset
	346	case 0x0e: return input_port_read(machine(), "A00E");      // coin/reset
345	347	}
346	348
347	349	if(offset == 0x00) //muxed with A002?
348	350	{
349		switch(state->m_reg_a002 & 0x3f)
	351	switch(m_reg_a002 & 0x3f)
350	352	{
351	353	case 0x3b:
352		return input_port_read(space->machine(), "UNK");   //bet10 / pay out
	354	return input_port_read(machine(), "UNK");   //bet10 / pay out
353	355	case 0x3e:
354		return input_port_read(space->machine(), "INPUTS");   //TODO : trace f564
	356	return input_port_read(machine(), "INPUTS");   //TODO : trace f564
355	357	case 0x3d:
356		return input_port_read(space->machine(), "A005");
	358	return input_port_read(machine(), "A005");
357	359	default:
358		logerror("A000 read with mux=0x%02x\n", state->m_reg_a002 & 0x3f);
	360	logerror("A000 read with mux=0x%02x\n", m_reg_a002 & 0x3f);
359	361	}
360	362	}
361	363	return 0xff;
362	364	}
363	365
364		static WRITE8_HANDLER(write_a00x)
	366	WRITE8_MEMBER(witch_state::write_a00x)
365	367	{
366		witch_state *state = space->machine().driver_data<witch_state>();
367	368	switch(offset)
368	369	{
369		case 0x02: //A002 bit 7&6 = state->m_bank ????
	370	case 0x02: //A002 bit 7&6 = m_bank ????
370	371	{
371	372	int newbank;
372		state->m_reg_a002 = data;
	373	m_reg_a002 = data;
373	374	newbank = (data>>6)&3;
374	375
375		if(newbank != state->m_bank)
	376	if(newbank != m_bank)
376	377	{
377		UINT8 *ROM = space->machine().region("maincpu")->base();
378		state->m_bank = newbank;
	378	UINT8 *ROM = machine().region("maincpu")->base();
	379	m_bank = newbank;
379	380	ROM = &ROM[0x10000+0x8000 * newbank + UNBANKED_SIZE];
380		memory_set_bankptr(space->machine(), "bank1",ROM);
	381	memory_set_bankptr(machine(), "bank1",ROM);
381	382	}
382	383	}
383	384	break;
r14845	r14846
386	387	break;
387	388
388	389	case 0x08: //A008
389		device_set_input_line(&space->device(),0,CLEAR_LINE);
	390	device_set_input_line(&space.device(),0,CLEAR_LINE);
390	391	break;
391	392	}
392	393	}
393	394
394		static READ8_HANDLER(prot_read_700x)
	395	READ8_MEMBER(witch_state::prot_read_700x)
395	396	{
396	397	/*
397	398	Code @$21a looks like simple protection check.
r14845	r14846
403	404	Otherwise later in game some I/O (controls) reads are skipped.
404	405	*/
405	406
406		switch(cpu_get_pc(&space->device()))
	407	switch(cpu_get_pc(&space.device()))
407	408	{
408	409	case 0x23f:
409	410	case 0x246:
r14845	r14846
413	414	case 0x25e:
414	415	return offset;//enough to pass...
415	416	}
416		return space->machine().region("sub")->base()[0x7000+offset];
	417	return machine().region("sub")->base()[0x7000+offset];
417	418	}
418	419
419	420	/*
r14845	r14846
464	465	AM_RANGE(UNBANKED_SIZE, 0x7fff) AM_ROMBANK("bank1")
465	466	AM_RANGE(0x8000, 0x8001) AM_DEVREADWRITE_LEGACY("ym1", ym2203_r, ym2203_w)
466	467	AM_RANGE(0x8008, 0x8009) AM_DEVREADWRITE_LEGACY("ym2", ym2203_r, ym2203_w)
467		AM_RANGE(0xa000, 0xa00f) AM_READWRITE_LEGACY(read_a00x, write_a00x)
468		AM_RANGE(0xc000, 0xc3ff) AM_READWRITE_LEGACY(gfx0_vram_r, gfx0_vram_w) AM_BASE(m_gfx0_vram)
469		AM_RANGE(0xc400, 0xc7ff) AM_READWRITE_LEGACY(gfx0_cram_r, gfx0_cram_w) AM_BASE(m_gfx0_cram)
470		AM_RANGE(0xc800, 0xcbff) AM_READWRITE_LEGACY(gfx1_vram_r, gfx1_vram_w) AM_BASE(m_gfx1_vram)
471		AM_RANGE(0xcc00, 0xcfff) AM_READWRITE_LEGACY(gfx1_cram_r, gfx1_cram_w) AM_BASE(m_gfx1_cram)
	468	AM_RANGE(0xa000, 0xa00f) AM_READWRITE(read_a00x, write_a00x)
	469	AM_RANGE(0xc000, 0xc3ff) AM_READWRITE(gfx0_vram_r, gfx0_vram_w) AM_BASE(m_gfx0_vram)
	470	AM_RANGE(0xc400, 0xc7ff) AM_READWRITE(gfx0_cram_r, gfx0_cram_w) AM_BASE(m_gfx0_cram)
	471	AM_RANGE(0xc800, 0xcbff) AM_READWRITE(gfx1_vram_r, gfx1_vram_w) AM_BASE(m_gfx1_vram)
	472	AM_RANGE(0xcc00, 0xcfff) AM_READWRITE(gfx1_cram_r, gfx1_cram_w) AM_BASE(m_gfx1_cram)
472	473	AM_RANGE(0xd000, 0xdfff) AM_RAM AM_BASE(m_sprite_ram)
473	474	AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split1_w) AM_BASE_GENERIC(paletteram)
474	475	AM_RANGE(0xe800, 0xefff) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split2_w) AM_BASE_GENERIC(paletteram2)
r14845	r14846
483	484	AM_RANGE(0x8000, 0x8001) AM_DEVREADWRITE_LEGACY("ym1", ym2203_r, ym2203_w)
484	485	AM_RANGE(0x8008, 0x8009) AM_DEVREADWRITE_LEGACY("ym2", ym2203_r, ym2203_w)
485	486	AM_RANGE(0x8010, 0x8016) AM_DEVREADWRITE_LEGACY("essnd", read_8010, es8712_w)
486		AM_RANGE(0xa000, 0xa00f) AM_READWRITE_LEGACY(read_a00x, write_a00x)
	487	AM_RANGE(0xa000, 0xa00f) AM_READWRITE(read_a00x, write_a00x)
487	488	AM_RANGE(0xf000, 0xf0ff) AM_RAM AM_SHARE("share1")
488	489	AM_RANGE(0xf180, 0xffff) AM_RAM AM_SHARE("share2")
489	490	ADDRESS_MAP_END
r14845	r14846
867	868	UINT8 *ROM = (UINT8 *)machine.region("maincpu")->base();
868	869	memory_set_bankptr(machine, "bank1", &ROM[0x10000+UNBANKED_SIZE]);
869	870
870		machine.device("sub")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x7000, 0x700f, FUNC(prot_read_700x));
	871	machine.device("sub")->memory().space(AS_PROGRAM)->install_read_handler(0x7000, 0x700f, read8_delegate(FUNC(witch_state::prot_read_700x), state));
871	872	state->m_bank = -1;
872	873	}
873	874

src/mame/drivers/luckgrln.c

r14845	r14846
111	111	UINT8* m_reel4_attr;
112	112	int m_palette_count;
113	113	UINT8 m_palette_ram[0x10000];
	114	DECLARE_WRITE8_MEMBER(luckgrln_reel1_ram_w);
	115	DECLARE_WRITE8_MEMBER(luckgrln_reel1_attr_w);
	116	DECLARE_WRITE8_MEMBER(luckgrln_reel2_ram_w);
	117	DECLARE_WRITE8_MEMBER(luckgrln_reel2_attr_w);
	118	DECLARE_WRITE8_MEMBER(luckgrln_reel3_ram_w);
	119	DECLARE_WRITE8_MEMBER(luckgrln_reel3_attr_w);
	120	DECLARE_WRITE8_MEMBER(luckgrln_reel4_ram_w);
	121	DECLARE_WRITE8_MEMBER(luckgrln_reel4_attr_w);
	122	DECLARE_WRITE8_MEMBER(output_w);
	123	DECLARE_WRITE8_MEMBER(palette_offset_low_w);
	124	DECLARE_WRITE8_MEMBER(palette_offset_high_w);
	125	DECLARE_WRITE8_MEMBER(palette_w);
	126	DECLARE_READ8_MEMBER(rtc_r);
	127	DECLARE_WRITE8_MEMBER(lamps_a_w);
	128	DECLARE_WRITE8_MEMBER(lamps_b_w);
	129	DECLARE_WRITE8_MEMBER(counters_w);
	130	DECLARE_READ8_MEMBER(test_r);
114	131	};
115	132
116	133
117		static WRITE8_HANDLER( luckgrln_reel1_ram_w )
	134	WRITE8_MEMBER(luckgrln_state::luckgrln_reel1_ram_w)
118	135	{
119		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
120		state->m_reel1_ram[offset] = data;
121		state->m_reel1_tilemap->mark_tile_dirty(offset);
	136	m_reel1_ram[offset] = data;
	137	m_reel1_tilemap->mark_tile_dirty(offset);
122	138	}
123	139
124		static WRITE8_HANDLER( luckgrln_reel1_attr_w )
	140	WRITE8_MEMBER(luckgrln_state::luckgrln_reel1_attr_w)
125	141	{
126		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
127		state->m_reel1_attr[offset] = data;
128		state->m_reel1_tilemap->mark_tile_dirty(offset);
	142	m_reel1_attr[offset] = data;
	143	m_reel1_tilemap->mark_tile_dirty(offset);
129	144	}
130	145
131	146
r14845	r14846
148	163	}
149	164
150	165
151		static WRITE8_HANDLER( luckgrln_reel2_ram_w )
	166	WRITE8_MEMBER(luckgrln_state::luckgrln_reel2_ram_w)
152	167	{
153		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
154		state->m_reel2_ram[offset] = data;
155		state->m_reel2_tilemap->mark_tile_dirty(offset);
	168	m_reel2_ram[offset] = data;
	169	m_reel2_tilemap->mark_tile_dirty(offset);
156	170	}
157	171
158		static WRITE8_HANDLER( luckgrln_reel2_attr_w )
	172	WRITE8_MEMBER(luckgrln_state::luckgrln_reel2_attr_w)
159	173	{
160		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
161		state->m_reel2_attr[offset] = data;
162		state->m_reel2_tilemap->mark_tile_dirty(offset);
	174	m_reel2_attr[offset] = data;
	175	m_reel2_tilemap->mark_tile_dirty(offset);
163	176	}
164	177
165	178
r14845	r14846
180	193	0);
181	194	}
182	195
183		static WRITE8_HANDLER( luckgrln_reel3_ram_w )
	196	WRITE8_MEMBER(luckgrln_state::luckgrln_reel3_ram_w)
184	197	{
185		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
186		state->m_reel3_ram[offset] = data;
187		state->m_reel3_tilemap->mark_tile_dirty(offset);
	198	m_reel3_ram[offset] = data;
	199	m_reel3_tilemap->mark_tile_dirty(offset);
188	200	}
189	201
190		static WRITE8_HANDLER( luckgrln_reel3_attr_w )
	202	WRITE8_MEMBER(luckgrln_state::luckgrln_reel3_attr_w)
191	203	{
192		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
193		state->m_reel3_attr[offset] = data;
194		state->m_reel3_tilemap->mark_tile_dirty(offset);
	204	m_reel3_attr[offset] = data;
	205	m_reel3_tilemap->mark_tile_dirty(offset);
195	206	}
196	207
197	208
r14845	r14846
211	222	0);
212	223	}
213	224
214		static WRITE8_HANDLER( luckgrln_reel4_ram_w )
	225	WRITE8_MEMBER(luckgrln_state::luckgrln_reel4_ram_w)
215	226	{
216		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
217		state->m_reel4_ram[offset] = data;
218		state->m_reel4_tilemap->mark_tile_dirty(offset);
	227	m_reel4_ram[offset] = data;
	228	m_reel4_tilemap->mark_tile_dirty(offset);
219	229	}
220	230
221		static WRITE8_HANDLER( luckgrln_reel4_attr_w )
	231	WRITE8_MEMBER(luckgrln_state::luckgrln_reel4_attr_w)
222	232	{
223		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
224		state->m_reel4_attr[offset] = data;
225		state->m_reel4_tilemap->mark_tile_dirty(offset);
	233	m_reel4_attr[offset] = data;
	234	m_reel4_tilemap->mark_tile_dirty(offset);
226	235	}
227	236
228	237
r14845	r14846
363	372	AM_RANGE(0x10000, 0x1ffff) AM_ROM AM_REGION("rom_data",0x10000)
364	373	AM_RANGE(0x20000, 0x2ffff) AM_ROM AM_REGION("rom_data",0x00000)
365	374
366		AM_RANGE(0x0c000, 0x0c1ff) AM_RAM_WRITE_LEGACY(luckgrln_reel1_ram_w)  AM_BASE(m_reel1_ram) // only written to half way
367		AM_RANGE(0x0c800, 0x0c9ff) AM_RAM_WRITE_LEGACY(luckgrln_reel1_attr_w) AM_BASE(m_reel1_attr)
	375	AM_RANGE(0x0c000, 0x0c1ff) AM_RAM_WRITE(luckgrln_reel1_ram_w)  AM_BASE(m_reel1_ram) // only written to half way
	376	AM_RANGE(0x0c800, 0x0c9ff) AM_RAM_WRITE(luckgrln_reel1_attr_w) AM_BASE(m_reel1_attr)
368	377	AM_RANGE(0x0d000, 0x0d03f) AM_RAM AM_BASE(m_reel1_scroll) AM_MIRROR(0x000c0)
369	378
370		AM_RANGE(0x0c200, 0x0c3ff) AM_RAM_WRITE_LEGACY(luckgrln_reel2_ram_w)  AM_BASE(m_reel2_ram)
371		AM_RANGE(0x0ca00, 0x0cbff) AM_RAM_WRITE_LEGACY(luckgrln_reel2_attr_w) AM_BASE(m_reel2_attr)
	379	AM_RANGE(0x0c200, 0x0c3ff) AM_RAM_WRITE(luckgrln_reel2_ram_w)  AM_BASE(m_reel2_ram)
	380	AM_RANGE(0x0ca00, 0x0cbff) AM_RAM_WRITE(luckgrln_reel2_attr_w) AM_BASE(m_reel2_attr)
372	381	AM_RANGE(0x0d200, 0x0d23f) AM_RAM AM_BASE(m_reel2_scroll) AM_MIRROR(0x000c0)
373	382
374		AM_RANGE(0x0c400, 0x0c5ff) AM_RAM_WRITE_LEGACY(luckgrln_reel3_ram_w ) AM_BASE(m_reel3_ram)
375		AM_RANGE(0x0cc00, 0x0cdff) AM_RAM_WRITE_LEGACY(luckgrln_reel3_attr_w) AM_BASE(m_reel3_attr)
	383	AM_RANGE(0x0c400, 0x0c5ff) AM_RAM_WRITE(luckgrln_reel3_ram_w ) AM_BASE(m_reel3_ram)
	384	AM_RANGE(0x0cc00, 0x0cdff) AM_RAM_WRITE(luckgrln_reel3_attr_w) AM_BASE(m_reel3_attr)
376	385	AM_RANGE(0x0d400, 0x0d43f) AM_RAM AM_BASE(m_reel3_scroll) AM_MIRROR(0x000c0)
377	386
378		AM_RANGE(0x0c600, 0x0c7ff) AM_RAM_WRITE_LEGACY(luckgrln_reel4_ram_w ) AM_BASE(m_reel4_ram)
379		AM_RANGE(0x0ce00, 0x0cfff) AM_RAM_WRITE_LEGACY(luckgrln_reel4_attr_w) AM_BASE(m_reel4_attr)
	387	AM_RANGE(0x0c600, 0x0c7ff) AM_RAM_WRITE(luckgrln_reel4_ram_w ) AM_BASE(m_reel4_ram)
	388	AM_RANGE(0x0ce00, 0x0cfff) AM_RAM_WRITE(luckgrln_reel4_attr_w) AM_BASE(m_reel4_attr)
380	389	AM_RANGE(0x0d600, 0x0d63f) AM_RAM AM_BASE(m_reel4_scroll)
381	390
382	391	//  AM_RANGE(0x0d200, 0x0d2ff) AM_RAM
r14845	r14846
400	409	AM_RANGE(0xf0000, 0xfffff) AM_UNMAP
401	410	ADDRESS_MAP_END
402	411
403		static WRITE8_HANDLER( output_w )
	412	WRITE8_MEMBER(luckgrln_state::output_w)
404	413	{
405		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
406	414	/* correct? */
407	415	if (data==0x84)
408		state->m_nmi_enable = 0;
	416	m_nmi_enable = 0;
409	417	else if (data==0x85)
410		state->m_nmi_enable = 1;
	418	m_nmi_enable = 1;
411	419	else
412	420	printf("output_w unk data %02x\n",data);
413	421	}
414	422
415	423
416	424
417		static WRITE8_HANDLER( palette_offset_low_w )
	425	WRITE8_MEMBER(luckgrln_state::palette_offset_low_w)
418	426	{
419		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
420		state->m_palette_count = data<<1;
	427	m_palette_count = data<<1;
421	428	}
422		static WRITE8_HANDLER( palette_offset_high_w )
	429	WRITE8_MEMBER(luckgrln_state::palette_offset_high_w)
423	430	{
424		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
425		state->m_palette_count = state->m_palette_count | data<<9;
	431	m_palette_count = m_palette_count | data<<9;
426	432	}
427	433
428	434
429		static WRITE8_HANDLER( palette_w )
	435	WRITE8_MEMBER(luckgrln_state::palette_w)
430	436	{
431		luckgrln_state *state = space->machine().driver_data<luckgrln_state>();
432		state->m_palette_ram[state->m_palette_count] = data;
	437	m_palette_ram[m_palette_count] = data;
433	438
434	439
435	440	{
436	441	int r,g,b;
437	442	int offs;
438	443	UINT16 dat;
439		offs = state->m_palette_count&~0x1;
440		dat = state->m_palette_ram[offs] | state->m_palette_ram[offs+1]<<8;
	444	offs = m_palette_count&~0x1;
	445	dat = m_palette_ram[offs] | m_palette_ram[offs+1]<<8;
441	446
442	447	r = (dat >> 0) & 0x1f;
443	448	g = (dat >> 5) & 0x1f;
444	449	b = (dat >> 10) & 0x1f;
445	450
446		palette_set_color_rgb(space->machine(), offs/2, pal5bit(r), pal5bit(g), pal5bit(b));
	451	palette_set_color_rgb(machine(), offs/2, pal5bit(r), pal5bit(g), pal5bit(b));
447	452
448	453	}
449	454
450		state->m_palette_count++;
	455	m_palette_count++;
451	456
452	457	}
453	458
454	459	// Oki M62X428 is a 4-bit RTC, doesn't seem to be millennium bug proof ...
455		static READ8_HANDLER( rtc_r )
	460	READ8_MEMBER(luckgrln_state::rtc_r)
456	461	{
457	462	system_time systime;
458		space->machine().base_datetime(systime);
	463	machine().base_datetime(systime);
459	464
460	465	switch(offset)
461	466	{
r14845	r14846
479	484	}
480	485
481	486	/* Analizing the lamps, the game should has a 12-buttons control layout */
482		static WRITE8_HANDLER(lamps_a_w)
	487	WRITE8_MEMBER(luckgrln_state::lamps_a_w)
483	488	{
484	489	/*  LAMPS A:
485	490
r14845	r14846
504	509	output_set_lamp_value(7, (data >> 7) & 1);      /* TAKE */
505	510	}
506	511
507		static WRITE8_HANDLER(lamps_b_w)
	512	WRITE8_MEMBER(luckgrln_state::lamps_b_w)
508	513	{
509	514	/*  LAMPS B:
510	515
r14845	r14846
523	528	output_set_lamp_value(11, (data >> 3) & 1);      /* CANCEL */
524	529	}
525	530
526		static WRITE8_HANDLER(counters_w)
	531	WRITE8_MEMBER(luckgrln_state::counters_w)
527	532	{
528	533	/*  COUNTERS:
529	534
r14845	r14846
535	540	xxxx ----  unused
536	541
537	542	*/
538		coin_counter_w(space->machine(), 0, data & 0x01);   /* COIN 1 */
539		coin_counter_w(space->machine(), 1, data & 0x04);   /* COIN 2 */
540		coin_counter_w(space->machine(), 2, data & 0x08);   /* COIN 3 */
541		coin_counter_w(space->machine(), 3, data & 0x02);   /* KEY IN */
	543	coin_counter_w(machine(), 0, data & 0x01);   /* COIN 1 */
	544	coin_counter_w(machine(), 1, data & 0x04);   /* COIN 2 */
	545	coin_counter_w(machine(), 2, data & 0x08);   /* COIN 3 */
	546	coin_counter_w(machine(), 3, data & 0x02);   /* KEY IN */
542	547	}
543	548
544	549
r14845	r14846
546	551	static ADDRESS_MAP_START( portmap, AS_IO, 8, luckgrln_state )
547	552	ADDRESS_MAP_GLOBAL_MASK(0xff)
548	553	AM_RANGE(0x0000, 0x003f) AM_RAM // Z180 internal regs
549		AM_RANGE(0x0060, 0x0060) AM_WRITE_LEGACY(output_w)
	554	AM_RANGE(0x0060, 0x0060) AM_WRITE(output_w)
550	555
551		AM_RANGE(0x0090, 0x009f) AM_READ_LEGACY(rtc_r) //AM_WRITENOP
	556	AM_RANGE(0x0090, 0x009f) AM_READ(rtc_r) //AM_WRITENOP
552	557
553		AM_RANGE(0x00a0, 0x00a0) AM_WRITE_LEGACY(palette_offset_low_w)
554		AM_RANGE(0x00a1, 0x00a1) AM_WRITE_LEGACY(palette_offset_high_w)
555		AM_RANGE(0x00a2, 0x00a2) AM_WRITE_LEGACY(palette_w)
	558	AM_RANGE(0x00a0, 0x00a0) AM_WRITE(palette_offset_low_w)
	559	AM_RANGE(0x00a1, 0x00a1) AM_WRITE(palette_offset_high_w)
	560	AM_RANGE(0x00a2, 0x00a2) AM_WRITE(palette_w)
556	561
557	562	AM_RANGE(0x00b0, 0x00b0) AM_DEVWRITE("crtc", mc6845_device, address_w)
558	563	AM_RANGE(0x00b1, 0x00b1) AM_DEVWRITE("crtc", mc6845_device, register_w)
559	564
560	565	AM_RANGE(0x00b8, 0x00b8) AM_READ_PORT("IN0")
561		AM_RANGE(0x00b9, 0x00b9) AM_READ_PORT("IN1") AM_WRITE_LEGACY(counters_w)
562		AM_RANGE(0x00ba, 0x00ba) AM_READ_PORT("IN2") AM_WRITE_LEGACY(lamps_a_w)
563		AM_RANGE(0x00bb, 0x00bb) AM_READ_PORT("IN3") AM_WRITE_LEGACY(lamps_b_w)
	566	AM_RANGE(0x00b9, 0x00b9) AM_READ_PORT("IN1") AM_WRITE(counters_w)
	567	AM_RANGE(0x00ba, 0x00ba) AM_READ_PORT("IN2") AM_WRITE(lamps_a_w)
	568	AM_RANGE(0x00bb, 0x00bb) AM_READ_PORT("IN3") AM_WRITE(lamps_b_w)
564	569	AM_RANGE(0x00bc, 0x00bc) AM_READ_PORT("DSW1")
565	570
566	571	AM_RANGE(0x00c0, 0x00c3) AM_WRITENOP
r14845	r14846
598	603	ADDRESS_MAP_END
599	604
600	605	/* reads a bit 1 status there after every round played */
601		static READ8_HANDLER( test_r )
	606	READ8_MEMBER(luckgrln_state::test_r)
602	607	{
603	608	return 0xff;
604	609	}
605	610
606	611	static ADDRESS_MAP_START( _7smash_io, AS_IO, 8, luckgrln_state )
607		AM_RANGE(0x66, 0x66) AM_READ_LEGACY(test_r)
	612	AM_RANGE(0x66, 0x66) AM_READ(test_r)
608	613	AM_IMPORT_FROM( portmap )
609	614	ADDRESS_MAP_END
610	615

src/mame/drivers/sigmab98.c

r14845	r14846
122	122	UINT8 m_vblank_vector;
123	123	UINT8 m_timer0_vector;
124	124	UINT8 m_timer1_vector;
	125	DECLARE_WRITE8_MEMBER(regs_w);
	126	DECLARE_READ8_MEMBER(regs_r);
	127	DECLARE_WRITE8_MEMBER(regs2_w);
	128	DECLARE_READ8_MEMBER(regs2_r);
	129	DECLARE_WRITE8_MEMBER(c4_w);
	130	DECLARE_WRITE8_MEMBER(c6_w);
	131	DECLARE_WRITE8_MEMBER(c8_w);
	132	DECLARE_WRITE8_MEMBER(animalc_rombank_w);
	133	DECLARE_READ8_MEMBER(animalc_rombank_r);
	134	DECLARE_WRITE8_MEMBER(animalc_rambank_w);
	135	DECLARE_READ8_MEMBER(animalc_rambank_r);
	136	DECLARE_READ8_MEMBER(unk_34_r);
	137	DECLARE_READ8_MEMBER(vblank_r);
	138	DECLARE_WRITE8_MEMBER(vblank_w);
	139	DECLARE_WRITE8_MEMBER(sammymdl_coin_w);
	140	DECLARE_WRITE8_MEMBER(sammymdl_leds_w);
	141	DECLARE_WRITE8_MEMBER(sammymdl_hopper_w);
	142	DECLARE_READ8_MEMBER(sammymdl_coin_hopper_r);
	143	DECLARE_WRITE8_MEMBER(haekaka_rombank_w);
	144	DECLARE_READ8_MEMBER(haekaka_rombank_r);
	145	DECLARE_WRITE8_MEMBER(haekaka_rambank_w);
	146	DECLARE_READ8_MEMBER(haekaka_rambank_r);
	147	DECLARE_READ8_MEMBER(haekaka_vblank_r);
	148	DECLARE_READ8_MEMBER(haekaka_b000_r);
	149	DECLARE_WRITE8_MEMBER(haekaka_b000_w);
	150	DECLARE_WRITE8_MEMBER(haekaka_leds_w);
	151	DECLARE_WRITE8_MEMBER(haekaka_coin_w);
	152	DECLARE_WRITE8_MEMBER(itazuram_rombank_w);
	153	DECLARE_READ8_MEMBER(itazuram_rombank_r);
	154	DECLARE_WRITE8_MEMBER(itazuram_rambank_w);
	155	DECLARE_READ8_MEMBER(itazuram_rambank_r);
	156	DECLARE_WRITE8_MEMBER(itazuram_nvram_palette_w);
	157	DECLARE_WRITE8_MEMBER(itazuram_palette_w);
	158	DECLARE_READ8_MEMBER(itazuram_palette_r);
	159	DECLARE_WRITE8_MEMBER(tdoboon_rombank_w);
	160	DECLARE_READ8_MEMBER(tdoboon_rombank_r);
	161	DECLARE_WRITE8_MEMBER(tdoboon_rambank_w);
	162	DECLARE_READ8_MEMBER(tdoboon_rambank_r);
	163	DECLARE_READ8_MEMBER(tdoboon_c000_r);
	164	DECLARE_WRITE8_MEMBER(tdoboon_c000_w);
	165	void show_outputs();
	166	void show_3_outputs();
125	167	};
126	168
127	169
r14845	r14846
289	331	***************************************************************************/
290	332
291	333	// rombank
292		static WRITE8_HANDLER( regs_w )
	334	WRITE8_MEMBER(sigmab98_state::regs_w)
293	335	{
294		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
295	336	if (offset == 0)
296	337	{
297		state->m_reg = data;
	338	m_reg = data;
298	339	return;
299	340	}
300	341
301		switch ( state->m_reg )
	342	switch ( m_reg )
302	343	{
303	344	case 0x1f:
304		state->m_rombank = data;
	345	m_rombank = data;
305	346	if (data >= 0x18)
306		logerror("%s: unknown rom bank = %02x\n", space->machine().describe_context(), data);
	347	logerror("%s: unknown rom bank = %02x\n", machine().describe_context(), data);
307	348	else
308		memory_set_bank(space->machine(), "rombank", data);
	349	memory_set_bank(machine(), "rombank", data);
309	350	break;
310	351
311	352	default:
312		logerror("%s: unknown reg written: %02x = %02x\n", space->machine().describe_context(), state->m_reg, data);
	353	logerror("%s: unknown reg written: %02x = %02x\n", machine().describe_context(), m_reg, data);
313	354	}
314	355	}
315		static READ8_HANDLER( regs_r )
	356	READ8_MEMBER(sigmab98_state::regs_r)
316	357	{
317		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
318	358	if (offset == 0)
319		return state->m_reg;
	359	return m_reg;
320	360
321		switch ( state->m_reg )
	361	switch ( m_reg )
322	362	{
323	363	case 0x1f:
324		return state->m_rombank;
	364	return m_rombank;
325	365
326	366	default:
327		logerror("%s: unknown reg read: %02x\n", space->machine().describe_context(), state->m_reg);
	367	logerror("%s: unknown reg read: %02x\n", machine().describe_context(), m_reg);
328	368	return 0x00;
329	369	}
330	370	}
331	371
332	372	// rambank
333		static WRITE8_HANDLER( regs2_w )
	373	WRITE8_MEMBER(sigmab98_state::regs2_w)
334	374	{
335		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
336	375	if (offset == 0)
337	376	{
338		state->m_reg2 = data;
	377	m_reg2 = data;
339	378	return;
340	379	}
341	380
342		switch ( state->m_reg2 )
	381	switch ( m_reg2 )
343	382	{
344	383	case 0xb5:
345		state->m_rambank = data;
	384	m_rambank = data;
346	385	switch (data)
347	386	{
348	387	case 0x32:
349		memory_set_bank(space->machine(), "rambank", 0);
	388	memory_set_bank(machine(), "rambank", 0);
350	389	break;
351	390	case 0x36:
352		memory_set_bank(space->machine(), "rambank", 1);
	391	memory_set_bank(machine(), "rambank", 1);
353	392	break;
354	393	default:
355		logerror("%s: unknown ram bank = %02x\n", space->machine().describe_context(), data);
	394	logerror("%s: unknown ram bank = %02x\n", machine().describe_context(), data);
356	395	}
357	396	break;
358	397
359	398	default:
360		logerror("%s: unknown reg2 written: %02x = %02x\n", space->machine().describe_context(), state->m_reg2, data);
	399	logerror("%s: unknown reg2 written: %02x = %02x\n", machine().describe_context(), m_reg2, data);
361	400	}
362	401	}
363		static READ8_HANDLER( regs2_r )
	402	READ8_MEMBER(sigmab98_state::regs2_r)
364	403	{
365		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
366	404	if (offset == 0)
367		return state->m_reg2;
	405	return m_reg2;
368	406
369		switch ( state->m_reg2 )
	407	switch ( m_reg2 )
370	408	{
371	409	case 0xb5:
372		return state->m_rambank;
	410	return m_rambank;
373	411
374	412	default:
375		logerror("%s: unknown reg2 read: %02x\n", space->machine().describe_context(), state->m_reg2);
	413	logerror("%s: unknown reg2 read: %02x\n", machine().describe_context(), m_reg2);
376	414	return 0x00;
377	415	}
378	416	}
r14845	r14846
380	418
381	419	// Outputs
382	420
383		static void show_outputs(sigmab98_state *state)
	421	void sigmab98_state::show_outputs()
384	422	{
385	423	#ifdef MAME_DEBUG
386		//  popmessage("0: %02X  4: %02X  6: %02X  8: %02X",state->m_c0,state->m_c4,state->m_c6,state->m_c8);
	424	//  popmessage("0: %02X  4: %02X  6: %02X  8: %02X",m_c0,m_c4,m_c6,m_c8);
387	425	#endif
388	426	}
389	427
r14845	r14846
403	441	eeprom->set_clock_line((data & 0x10) ? ASSERT_LINE : CLEAR_LINE);
404	442
405	443	state->m_c0 = data;
406		show_outputs(state);
	444	//show_outputs(state);
407	445	}
408	446
409	447	// Port c4
410	448	// 10 led?
411		static WRITE8_HANDLER( c4_w )
	449	WRITE8_MEMBER(sigmab98_state::c4_w)
412	450	{
413		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
414		set_led_status(space->machine(), 0, (data & 0x10));
	451	set_led_status(machine(), 0, (data & 0x10));
415	452
416		state->m_c4 = data;
417		show_outputs(state);
	453	m_c4 = data;
	454	show_outputs();
418	455	}
419	456
420	457	// Port c6
r14845	r14846
423	460	// 08 always blinks
424	461	// 10 led?
425	462	// 20 blinks after coin up
426		static WRITE8_HANDLER( c6_w )
	463	WRITE8_MEMBER(sigmab98_state::c6_w)
427	464	{
428		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
429		coin_lockout_w(space->machine(), 0, (~data) & 0x02);
	465	coin_lockout_w(machine(), 0, (~data) & 0x02);
430	466
431		coin_counter_w(space->machine(), 0,   data  & 0x04);
	467	coin_counter_w(machine(), 0,   data  & 0x04);
432	468
433		set_led_status(space->machine(), 1,   data  & 0x08);
434		set_led_status(space->machine(), 2,   data  & 0x10);
435		set_led_status(space->machine(), 3,   data  & 0x20);   //
	469	set_led_status(machine(), 1,   data  & 0x08);
	470	set_led_status(machine(), 2,   data  & 0x10);
	471	set_led_status(machine(), 3,   data  & 0x20);   //
436	472
437		state->m_c6 = data;
438		show_outputs(state);
	473	m_c6 = data;
	474	show_outputs();
439	475	}
440	476
441	477	// Port c8
442	478	// 01 hopper enable?
443	479	// 02 hopper motor on (active low)?
444		static WRITE8_HANDLER( c8_w )
	480	WRITE8_MEMBER(sigmab98_state::c8_w)
445	481	{
446		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
447		ticket_dispenser_w(space->machine().device("hopper"), 0, (!(data & 0x02) && (data & 0x01)) ? 0x00 : 0x80);
	482	ticket_dispenser_w(machine().device("hopper"), 0, (!(data & 0x02) && (data & 0x01)) ? 0x00 : 0x80);
448	483
449		state->m_c8 = data;
450		show_outputs(state);
	484	m_c8 = data;
	485	show_outputs();
451	486	}
452	487
453	488	static ADDRESS_MAP_START( gegege_mem_map, AS_PROGRAM, 8, sigmab98_state )
r14845	r14846
473	508
474	509	AM_RANGE( 0x00, 0x01 ) AM_DEVWRITE_LEGACY("ymz", ymz280b_w )
475	510
476		AM_RANGE( 0xa0, 0xa1 ) AM_READWRITE_LEGACY(regs_r,  regs_w )
	511	AM_RANGE( 0xa0, 0xa1 ) AM_READWRITE(regs_r,  regs_w )
477	512	//  AM_RANGE( 0xa2, 0xa3 )
478		AM_RANGE( 0xa4, 0xa5 ) AM_READWRITE_LEGACY(regs2_r, regs2_w )
	513	AM_RANGE( 0xa4, 0xa5 ) AM_READWRITE(regs2_r, regs2_w )
479	514
480	515	AM_RANGE( 0xc0, 0xc0 ) AM_READ_PORT( "EEPROM" )
481	516	AM_RANGE( 0xc0, 0xc0 ) AM_DEVWRITE_LEGACY("eeprom", eeprom_w)
r14845	r14846
483	518	AM_RANGE( 0xc2, 0xc2 ) AM_READ_PORT( "IN1" )
484	519
485	520	AM_RANGE( 0xc4, 0xc4 ) AM_READ_PORT( "IN2" )
486		AM_RANGE( 0xc4, 0xc4 ) AM_WRITE_LEGACY(c4_w )
	521	AM_RANGE( 0xc4, 0xc4 ) AM_WRITE(c4_w )
487	522
488		AM_RANGE( 0xc6, 0xc6 ) AM_WRITE_LEGACY(c6_w )
	523	AM_RANGE( 0xc6, 0xc6 ) AM_WRITE(c6_w )
489	524
490		AM_RANGE( 0xc8, 0xc8 ) AM_WRITE_LEGACY(c8_w )
	525	AM_RANGE( 0xc8, 0xc8 ) AM_WRITE(c8_w )
491	526
492	527	AM_RANGE( 0xe5, 0xe5 ) AM_READNOP   // during irq
493	528	ADDRESS_MAP_END
r14845	r14846
498	533	***************************************************************************/
499	534
500	535	// rombank
501		static WRITE8_HANDLER( animalc_rombank_w )
	536	WRITE8_MEMBER(sigmab98_state::animalc_rombank_w)
502	537	{
503		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
504	538	if (offset == 0)
505	539	{
506		state->m_reg = data;
	540	m_reg = data;
507	541	return;
508	542	}
509	543
510		UINT8 *rom = space->machine().region("maincpu")->base();
511		switch ( state->m_reg )
	544	UINT8 *rom = machine().region("maincpu")->base();
	545	switch ( m_reg )
512	546	{
513	547	case 0x0f:
514		state->m_rombank = data;
	548	m_rombank = data;
515	549	switch (data)
516	550	{
517		case 0x10:   memory_set_bankptr(space->machine(), "rombank", rom + 0x400 + 0x4000);   break;
518		case 0x14:   memory_set_bankptr(space->machine(), "rombank", rom + 0x400 + 0x8000);   break;
519		case 0x18:   memory_set_bankptr(space->machine(), "rombank", rom + 0x400 + 0xc000);   break;
	551	case 0x10:   memory_set_bankptr(machine(), "rombank", rom + 0x400 + 0x4000);   break;
	552	case 0x14:   memory_set_bankptr(machine(), "rombank", rom + 0x400 + 0x8000);   break;
	553	case 0x18:   memory_set_bankptr(machine(), "rombank", rom + 0x400 + 0xc000);   break;
520	554	default:
521		logerror("%s: unknown rom bank = %02x, reg = %02x\n", space->machine().describe_context(), data, state->m_reg);
	555	logerror("%s: unknown rom bank = %02x, reg = %02x\n", machine().describe_context(), data, m_reg);
522	556	}
523	557	break;
524	558
525	559	default:
526		logerror("%s: unknown reg written: %02x = %02x\n", space->machine().describe_context(), state->m_reg, data);
	560	logerror("%s: unknown reg written: %02x = %02x\n", machine().describe_context(), m_reg, data);
527	561	}
528	562	}
529		static READ8_HANDLER( animalc_rombank_r )
	563	READ8_MEMBER(sigmab98_state::animalc_rombank_r)
530	564	{
531		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
532	565	if (offset == 0)
533		return state->m_reg;
	566	return m_reg;
534	567
535		switch ( state->m_reg )
	568	switch ( m_reg )
536	569	{
537	570	case 0x0f:
538		return state->m_rombank;
	571	return m_rombank;
539	572
540	573	default:
541		logerror("%s: unknown reg read: %02x\n", space->machine().describe_context(), state->m_reg);
	574	logerror("%s: unknown reg read: %02x\n", machine().describe_context(), m_reg);
542	575	return 0x00;
543	576	}
544	577	}
545	578
546	579	// rambank
547		static WRITE8_HANDLER( animalc_rambank_w )
	580	WRITE8_MEMBER(sigmab98_state::animalc_rambank_w)
548	581	{
549		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
550	582	if (offset == 0)
551	583	{
552		state->m_reg2 = data;
	584	m_reg2 = data;
553	585	return;
554	586	}
555	587
556	588	int bank = 0;
557		switch ( state->m_reg2 )
	589	switch ( m_reg2 )
558	590	{
559	591	case 0x1f:
560		state->m_rambank = data;
	592	m_rambank = data;
561	593	switch (data)
562	594	{
563	595	case 0x58:   bank = 0;   break;
r14845	r14846
566	598	case 0x64:   bank = 3;   break;
567	599	case 0x65:   bank = 4;   break;
568	600	default:
569		logerror("%s: unknown ram bank = %02x, reg2 = %02x\n", space->machine().describe_context(), data, state->m_reg2);
	601	logerror("%s: unknown ram bank = %02x, reg2 = %02x\n", machine().describe_context(), data, m_reg2);
570	602	return;
571	603	}
572		memory_set_bank(space->machine(), "rambank", bank);
	604	memory_set_bank(machine(), "rambank", bank);
573	605	if ( (bank == 1) || (bank == 2) || (bank == 3) )
574		memory_set_bank(space->machine(), "sprbank", bank-1);
	606	memory_set_bank(machine(), "sprbank", bank-1);
575	607	break;
576	608
577	609	default:
578		logerror("%s: unknown reg2 written: %02x = %02x\n", space->machine().describe_context(), state->m_reg2, data);
	610	logerror("%s: unknown reg2 written: %02x = %02x\n", machine().describe_context(), m_reg2, data);
579	611	}
580	612	}
581		static READ8_HANDLER( animalc_rambank_r )
	613	READ8_MEMBER(sigmab98_state::animalc_rambank_r)
582	614	{
583		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
584	615	if (offset == 0)
585		return state->m_reg2;
	616	return m_reg2;
586	617
587		switch ( state->m_reg2 )
	618	switch ( m_reg2 )
588	619	{
589	620	case 0x1f:
590		return state->m_rambank;
	621	return m_rambank;
591	622
592	623	default:
593		logerror("%s: unknown reg2 read: %02x\n", space->machine().describe_context(), state->m_reg2);
	624	logerror("%s: unknown reg2 read: %02x\n", machine().describe_context(), m_reg2);
594	625	return 0x00;
595	626	}
596	627	}
r14845	r14846
618	649	logerror("%s: unknown eeeprom bits written %02x\n", device->machine().describe_context(), data);
619	650	}
620	651
621		static READ8_HANDLER( unk_34_r )
	652	READ8_MEMBER(sigmab98_state::unk_34_r)
622	653	{
623	654	// mask 0x01?
624	655	return 0x01;
625	656	}
626	657
627		static READ8_HANDLER( vblank_r )
	658	READ8_MEMBER(sigmab98_state::vblank_r)
628	659	{
629		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
630	660	// mask 0x04 must be set before writing sprite list
631	661	// mask 0x10 must be set or irq/00 hangs?
632		return   state->m_vblank | 0x14;
	662	return   m_vblank | 0x14;
633	663	}
634	664
635		static WRITE8_HANDLER( vblank_w )
	665	WRITE8_MEMBER(sigmab98_state::vblank_w)
636	666	{
637		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
638		state->m_vblank = (state->m_vblank & ~0x03) | (data & 0x03);
	667	m_vblank = (m_vblank & ~0x03) | (data & 0x03);
639	668	}
640	669
641	670	static SCREEN_VBLANK( sammymdl )
r14845	r14846
648	677	}
649	678	}
650	679
651		static void show_3_outputs(sigmab98_state *state)
	680	void sigmab98_state::show_3_outputs()
652	681	{
653	682	#ifdef MAME_DEBUG
654		//  popmessage("COIN: %02X  LED: %02X  HOP: %02X", state->m_out[0], state->m_out[1], state->m_out[2]);
	683	//  popmessage("COIN: %02X  LED: %02X  HOP: %02X", m_out[0], m_out[1], m_out[2]);
655	684	#endif
656	685	}
657	686	// Port 31
658		static WRITE8_HANDLER( sammymdl_coin_w )
	687	WRITE8_MEMBER(sigmab98_state::sammymdl_coin_w)
659	688	{
660		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
661		coin_counter_w(space->machine(), 0,   data  & 0x01 );   // coin1 in
662		coin_counter_w(space->machine(), 1,   data  & 0x02 );   // coin2 in
663		coin_counter_w(space->machine(), 2,   data  & 0x04 );   // medal in
	689	coin_counter_w(machine(), 0,   data  & 0x01 );   // coin1 in
	690	coin_counter_w(machine(), 1,   data  & 0x02 );   // coin2 in
	691	coin_counter_w(machine(), 2,   data  & 0x04 );   // medal in
664	692
665		//  coin_lockout_w(space->machine(), 1, (~data) & 0x08 ); // coin2 lockout?
666		//  coin_lockout_w(space->machine(), 0, (~data) & 0x10 ); // coin1 lockout
667		//  coin_lockout_w(space->machine(), 2, (~data) & 0x20 ); // medal lockout?
	693	//  coin_lockout_w(machine(), 1, (~data) & 0x08 ); // coin2 lockout?
	694	//  coin_lockout_w(machine(), 0, (~data) & 0x10 ); // coin1 lockout
	695	//  coin_lockout_w(machine(), 2, (~data) & 0x20 ); // medal lockout?
668	696
669		state->m_out[0] = data;
670		show_3_outputs(state);
	697	m_out[0] = data;
	698	show_3_outputs();
671	699	}
672	700
673	701	// Port 32
674		static WRITE8_HANDLER( sammymdl_leds_w )
	702	WRITE8_MEMBER(sigmab98_state::sammymdl_leds_w)
675	703	{
676		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
677		set_led_status(space->machine(), 0,   data & 0x01);   // button
	704	set_led_status(machine(), 0,   data & 0x01);   // button
678	705
679		state->m_out[1] = data;
680		show_3_outputs(state);
	706	m_out[1] = data;
	707	show_3_outputs();
681	708	}
682	709
683	710	// Port b0
684	711	// 02 hopper enable?
685	712	// 01 hopper motor on (active low)?
686		static WRITE8_HANDLER( sammymdl_hopper_w )
	713	WRITE8_MEMBER(sigmab98_state::sammymdl_hopper_w)
687	714	{
688		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
689		ticket_dispenser_w(space->machine().device("hopper"), 0, (!(data & 0x01) && (data & 0x02)) ? 0x00 : 0x80);
	715	ticket_dispenser_w(machine().device("hopper"), 0, (!(data & 0x01) && (data & 0x02)) ? 0x00 : 0x80);
690	716
691		state->m_out[2] = data;
692		show_3_outputs(state);
	717	m_out[2] = data;
	718	show_3_outputs();
693	719	}
694	720
695		static READ8_HANDLER( sammymdl_coin_hopper_r )
	721	READ8_MEMBER(sigmab98_state::sammymdl_coin_hopper_r)
696	722	{
697		UINT8 ret = input_port_read(space->machine(), "COIN");
	723	UINT8 ret = input_port_read(machine(), "COIN");
698	724
699		//  if ( !ticket_dispenser_r(space->machine().device("hopper"), 0) )
	725	//  if ( !ticket_dispenser_r(machine().device("hopper"), 0) )
700	726	//      ret &= ~0x01;
701	727
702	728	return ret;
r14845	r14846
715	741	AM_RANGE( 0xd800, 0xd87f ) AM_RAM   // table?
716	742
717	743	AM_RANGE( 0xe011, 0xe011 ) AM_WRITENOP   // IRQ Enable? Screen disable?
718		AM_RANGE( 0xe013, 0xe013 ) AM_READWRITE_LEGACY(vblank_r, vblank_w )   // IRQ Ack?
	744	AM_RANGE( 0xe013, 0xe013 ) AM_READWRITE(vblank_r, vblank_w )   // IRQ Ack?
719	745
720	746	AM_RANGE( 0xfe00, 0xffff ) AM_RAM   // High speed internal RAM
721	747	ADDRESS_MAP_END
722	748
723	749	static ADDRESS_MAP_START( animalc_io, AS_IO, 8, sigmab98_state )
724	750	ADDRESS_MAP_GLOBAL_MASK(0xff)
725		AM_RANGE( 0x02, 0x03 ) AM_READWRITE_LEGACY(animalc_rombank_r, animalc_rombank_w )
726		AM_RANGE( 0x04, 0x05 ) AM_READWRITE_LEGACY(animalc_rambank_r, animalc_rambank_w )
	751	AM_RANGE( 0x02, 0x03 ) AM_READWRITE(animalc_rombank_r, animalc_rombank_w )
	752	AM_RANGE( 0x04, 0x05 ) AM_READWRITE(animalc_rambank_r, animalc_rambank_w )
727	753
728	754	AM_RANGE( 0x2c, 0x2c ) AM_DEVREADWRITE_LEGACY("eeprom", sammymdl_eeprom_r, sammymdl_eeprom_w )
729		AM_RANGE( 0x2e, 0x2e ) AM_READ_LEGACY(sammymdl_coin_hopper_r )
	755	AM_RANGE( 0x2e, 0x2e ) AM_READ(sammymdl_coin_hopper_r )
730	756	AM_RANGE( 0x30, 0x30 ) AM_READ_PORT( "BUTTON" )
731		AM_RANGE( 0x31, 0x31 ) AM_WRITE_LEGACY(sammymdl_coin_w )
732		AM_RANGE( 0x32, 0x32 ) AM_WRITE_LEGACY(sammymdl_leds_w )
733		AM_RANGE( 0x34, 0x34 ) AM_READ_LEGACY(unk_34_r )
	757	AM_RANGE( 0x31, 0x31 ) AM_WRITE(sammymdl_coin_w )
	758	AM_RANGE( 0x32, 0x32 ) AM_WRITE(sammymdl_leds_w )
	759	AM_RANGE( 0x34, 0x34 ) AM_READ(unk_34_r )
734	760	AM_RANGE( 0x90, 0x90 ) AM_DEVWRITE("oki", okim9810_device, write )
735	761	AM_RANGE( 0x91, 0x91 ) AM_DEVWRITE("oki", okim9810_device, write_TMP_register )
736	762	AM_RANGE( 0x92, 0x92 ) AM_DEVREAD("oki", okim9810_device, read )
737		AM_RANGE( 0xb0, 0xb0 ) AM_WRITE_LEGACY(sammymdl_hopper_w )
	763	AM_RANGE( 0xb0, 0xb0 ) AM_WRITE(sammymdl_hopper_w )
738	764	AM_RANGE( 0xc0, 0xc0 ) AM_WRITE_LEGACY(watchdog_reset_w )   // 1
739	765	ADDRESS_MAP_END
740	766
r14845	r14846
743	769	***************************************************************************/
744	770
745	771	// rombank
746		static WRITE8_HANDLER( haekaka_rombank_w )
	772	WRITE8_MEMBER(sigmab98_state::haekaka_rombank_w)
747	773	{
748		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
749	774	if (offset == 0)
750	775	{
751		state->m_reg = data;
	776	m_reg = data;
752	777	return;
753	778	}
754	779
755		switch ( state->m_reg )
	780	switch ( m_reg )
756	781	{
757	782	case 0x2b:
758		state->m_rombank = data;
	783	m_rombank = data;
759	784	switch (data)
760	785	{
761	786	case 0x10:   // ROM
r14845	r14846
780	805	break;
781	806
782	807	default:
783		logerror("%s: unknown rom bank = %02x, reg = %02x\n", space->machine().describe_context(), data, state->m_reg);
	808	logerror("%s: unknown rom bank = %02x, reg = %02x\n", machine().describe_context(), data, m_reg);
784	809	}
785	810	break;
786	811
787	812	default:
788		logerror("%s: unknown reg written: %02x = %02x\n", space->machine().describe_context(), state->m_reg, data);
	813	logerror("%s: unknown reg written: %02x = %02x\n", machine().describe_context(), m_reg, data);
789	814	}
790	815	}
791		static READ8_HANDLER( haekaka_rombank_r )
	816	READ8_MEMBER(sigmab98_state::haekaka_rombank_r)
792	817	{
793		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
794	818	if (offset == 0)
795		return state->m_reg;
	819	return m_reg;
796	820
797		switch ( state->m_reg )
	821	switch ( m_reg )
798	822	{
799	823	case 0x2b:
800		return state->m_rombank;
	824	return m_rombank;
801	825
802	826	default:
803		logerror("%s: unknown reg read: %02x\n", space->machine().describe_context(), state->m_reg);
	827	logerror("%s: unknown reg read: %02x\n", machine().describe_context(), m_reg);
804	828	return 0x00;
805	829	}
806	830	}
807	831
808	832	// rambank
809		static WRITE8_HANDLER( haekaka_rambank_w )
	833	WRITE8_MEMBER(sigmab98_state::haekaka_rambank_w)
810	834	{
811		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
812	835	if (offset == 0)
813	836	{
814		state->m_reg2 = data;
	837	m_reg2 = data;
815	838	return;
816	839	}
817	840
818		switch ( state->m_reg2 )
	841	switch ( m_reg2 )
819	842	{
820	843	case 0x33:
821		state->m_rambank = data;
	844	m_rambank = data;
822	845	switch (data)
823	846	{
824	847	case 0x53:
825	848	break;
826	849
827	850	default:
828		logerror("%s: unknown ram bank = %02x, reg2 = %02x\n", space->machine().describe_context(), data, state->m_reg2);
	851	logerror("%s: unknown ram bank = %02x, reg2 = %02x\n", machine().describe_context(), data, m_reg2);
829	852	}
830	853	break;
831	854
832	855	default:
833		logerror("%s: unknown reg2 written: %02x = %02x\n", space->machine().describe_context(), state->m_reg2, data);
	856	logerror("%s: unknown reg2 written: %02x = %02x\n", machine().describe_context(), m_reg2, data);
834	857	}
835	858	}
836		static READ8_HANDLER( haekaka_rambank_r )
	859	READ8_MEMBER(sigmab98_state::haekaka_rambank_r)
837	860	{
838		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
839	861	if (offset == 0)
840		return state->m_reg2;
	862	return m_reg2;
841	863
842		switch ( state->m_reg2 )
	864	switch ( m_reg2 )
843	865	{
844	866	case 0x33:
845		return state->m_rambank;
	867	return m_rambank;
846	868
847	869	default:
848		logerror("%s: unknown reg2 read: %02x\n", space->machine().describe_context(), state->m_reg2);
	870	logerror("%s: unknown reg2 read: %02x\n", machine().describe_context(), m_reg2);
849	871	return 0x00;
850	872	}
851	873	}
852	874
853		static READ8_HANDLER( haekaka_vblank_r )
	875	READ8_MEMBER(sigmab98_state::haekaka_vblank_r)
854	876	{
855		return space->machine().primary_screen->vblank() ? 0 : 0x1c;
	877	return machine().primary_screen->vblank() ? 0 : 0x1c;
856	878	}
857	879
858		static READ8_HANDLER( haekaka_b000_r )
	880	READ8_MEMBER(sigmab98_state::haekaka_b000_r)
859	881	{
860		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
861		switch (state->m_rombank)
	882	switch (m_rombank)
862	883	{
863	884	case 0x10:   // ROM
864	885	case 0x11:
r14845	r14846
876	897	case 0x1d:
877	898	case 0x1e:
878	899	case 0x1f:
879		return space->machine().region("maincpu")->base()[offset + 0xb400 + 0x1000 * (state->m_rombank-0x10)];
	900	return machine().region("maincpu")->base()[offset + 0xb400 + 0x1000 * (m_rombank-0x10)];
880	901
881	902	case 0x65:   // SPRITERAM
882	903	if (offset < 0x1000)
883		return state->m_spriteram[offset];
	904	return m_spriteram[offset];
884	905
885	906	case 0x67:   // PALETTERAM + TABLE? + REGS
886	907	if (offset < 0x200)
887		return space->machine().generic.paletteram.u8[offset];
	908	return machine().generic.paletteram.u8[offset];
888	909	else if (offset == (0xc013-0xb000))
889	910	return haekaka_vblank_r(space, offset);
890	911	break;
891	912	}
892	913
893		logerror("%s: unknown read from %02x with rombank = %02x\n", space->machine().describe_context(), offset+0xb000, state->m_rombank);
	914	logerror("%s: unknown read from %02x with rombank = %02x\n", machine().describe_context(), offset+0xb000, m_rombank);
894	915	return 0x00;
895	916	}
896	917
897		static WRITE8_HANDLER( haekaka_b000_w )
	918	WRITE8_MEMBER(sigmab98_state::haekaka_b000_w)
898	919	{
899		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
900		switch (state->m_rombank)
	920	switch (m_rombank)
901	921	{
902	922	case 0x65:   // SPRITERAM
903	923	if (offset < 0x1000)
904	924	{
905		state->m_spriteram[offset] = data;
	925	m_spriteram[offset] = data;
906	926	return;
907	927	}
908	928	break;
r14845	r14846
911	931	if (offset < 0x200)
912	932	{
913	933	paletteram_xRRRRRGGGGGBBBBB_be_w(space, offset, data);
914		//              space->machine().generic.paletteram.u8[offset] = data;
	934	//              machine().generic.paletteram.u8[offset] = data;
915	935	return;
916	936	}
917	937	else if ((offset >= 0x800) && (offset < 0x880))
r14845	r14846
922	942	break;
923	943	}
924	944
925		logerror("%s: unknown write to %02x = %02x with rombank = %02x\n", space->machine().describe_context(), offset+0xb000, data, state->m_rombank);
	945	logerror("%s: unknown write to %02x = %02x with rombank = %02x\n", machine().describe_context(), offset+0xb000, data, m_rombank);
926	946	}
927	947
928		static WRITE8_HANDLER( haekaka_leds_w )
	948	WRITE8_MEMBER(sigmab98_state::haekaka_leds_w)
929	949	{
930		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
931	950	// All used
932		set_led_status(space->machine(), 0,   data & 0x01);
933		set_led_status(space->machine(), 1,   data & 0x02);
934		set_led_status(space->machine(), 2,   data & 0x04);
935		set_led_status(space->machine(), 3,   data & 0x08);
936		set_led_status(space->machine(), 4,   data & 0x10);
937		set_led_status(space->machine(), 5,   data & 0x20);
938		set_led_status(space->machine(), 6,   data & 0x40);
939		set_led_status(space->machine(), 7,   data & 0x80);
	951	set_led_status(machine(), 0,   data & 0x01);
	952	set_led_status(machine(), 1,   data & 0x02);
	953	set_led_status(machine(), 2,   data & 0x04);
	954	set_led_status(machine(), 3,   data & 0x08);
	955	set_led_status(machine(), 4,   data & 0x10);
	956	set_led_status(machine(), 5,   data & 0x20);
	957	set_led_status(machine(), 6,   data & 0x40);
	958	set_led_status(machine(), 7,   data & 0x80);
940	959
941		state->m_out[1] = data;
942		show_3_outputs(state);
	960	m_out[1] = data;
	961	show_3_outputs();
943	962	}
944	963
945		static WRITE8_HANDLER( haekaka_coin_w )
	964	WRITE8_MEMBER(sigmab98_state::haekaka_coin_w)
946	965	{
947		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
948		coin_counter_w(space->machine(), 0,   data & 0x01 );   // medal out
	966	coin_counter_w(machine(), 0,   data & 0x01 );   // medal out
949	967	//                                      data & 0x02 ?
950	968	//                                      data & 0x04 ?
951	969	//                                      data & 0x10 ?
952	970
953		state->m_out[0] = data;
954		show_3_outputs(state);
	971	m_out[0] = data;
	972	show_3_outputs();
955	973	}
956	974
957	975	static ADDRESS_MAP_START( haekaka_map, AS_PROGRAM, 8, sigmab98_state )
958	976	AM_RANGE( 0x0000, 0x7fff ) AM_ROM
959		AM_RANGE( 0xb000, 0xcfff ) AM_READWRITE_LEGACY(haekaka_b000_r, haekaka_b000_w )
	977	AM_RANGE( 0xb000, 0xcfff ) AM_READWRITE(haekaka_b000_r, haekaka_b000_w )
960	978	AM_RANGE( 0xd000, 0xefff ) AM_RAM AM_SHARE( "nvram" ) AM_BASE(m_nvram )
961	979	AM_RANGE( 0xfe00, 0xffff ) AM_RAM   // High speed internal RAM
962	980	ADDRESS_MAP_END
963	981
964	982	static ADDRESS_MAP_START( haekaka_io, AS_IO, 8, sigmab98_state )
965	983	ADDRESS_MAP_GLOBAL_MASK(0xff)
966		AM_RANGE( 0x02, 0x03 ) AM_READWRITE_LEGACY(haekaka_rombank_r, haekaka_rombank_w )
967		AM_RANGE( 0x04, 0x05 ) AM_READWRITE_LEGACY(haekaka_rambank_r, haekaka_rambank_w )
	984	AM_RANGE( 0x02, 0x03 ) AM_READWRITE(haekaka_rombank_r, haekaka_rombank_w )
	985	AM_RANGE( 0x04, 0x05 ) AM_READWRITE(haekaka_rambank_r, haekaka_rambank_w )
968	986
969	987	AM_RANGE( 0x2c, 0x2c ) AM_DEVREADWRITE_LEGACY("eeprom", sammymdl_eeprom_r, sammymdl_eeprom_w )
970		AM_RANGE( 0x2e, 0x2e ) AM_READ_LEGACY(sammymdl_coin_hopper_r )
	988	AM_RANGE( 0x2e, 0x2e ) AM_READ(sammymdl_coin_hopper_r )
971	989	AM_RANGE( 0x30, 0x30 ) AM_READ_PORT( "BUTTON" )
972		AM_RANGE( 0x31, 0x31 ) AM_WRITE_LEGACY(haekaka_coin_w )
973		AM_RANGE( 0x32, 0x32 ) AM_WRITE_LEGACY(haekaka_leds_w )
	990	AM_RANGE( 0x31, 0x31 ) AM_WRITE(haekaka_coin_w )
	991	AM_RANGE( 0x32, 0x32 ) AM_WRITE(haekaka_leds_w )
974	992	AM_RANGE( 0x90, 0x90 ) AM_DEVWRITE("oki", okim9810_device, write )
975	993	AM_RANGE( 0x91, 0x91 ) AM_DEVWRITE("oki", okim9810_device, write_TMP_register )
976	994	AM_RANGE( 0x92, 0x92 ) AM_DEVREAD("oki", okim9810_device, read )
977		AM_RANGE( 0xb0, 0xb0 ) AM_WRITE_LEGACY(sammymdl_hopper_w )
	995	AM_RANGE( 0xb0, 0xb0 ) AM_WRITE(sammymdl_hopper_w )
978	996	AM_RANGE( 0xc0, 0xc0 ) AM_WRITE_LEGACY(watchdog_reset_w )   // 1
979	997	ADDRESS_MAP_END
980	998
r14845	r14846
983	1001	***************************************************************************/
984	1002
985	1003	// rombank
986		static WRITE8_HANDLER( itazuram_rombank_w )
	1004	WRITE8_MEMBER(sigmab98_state::itazuram_rombank_w)
987	1005	{
988		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
989	1006	if (offset == 0)
990	1007	{
991		state->m_reg = data;
	1008	m_reg = data;
992	1009	return;
993	1010	}
994	1011
995		UINT8 *rom = space->machine().region("maincpu")->base();
996		switch ( state->m_reg )
	1012	UINT8 *rom = machine().region("maincpu")->base();
	1013	switch ( m_reg )
997	1014	{
998	1015	case 0x0d:
999		state->m_rombank = data;
	1016	m_rombank = data;
1000	1017	switch (data)
1001	1018	{
1002	1019	case 0x11:   // 3800 IS ROM
1003		memory_set_bankptr(space->machine(), "rombank0", rom + 0x4c00);
1004		memory_set_bankptr(space->machine(), "rombank1", rom + 0x5c00);
1005		memory_set_bankptr(space->machine(), "sprbank0", state->m_spriteram + 0x1000*4);   // scratch
1006		memory_set_bankptr(space->machine(), "sprbank1", state->m_spriteram + 0x1000*4);   // scratch
	1020	memory_set_bankptr(machine(), "rombank0", rom + 0x4c00);
	1021	memory_set_bankptr(machine(), "rombank1", rom + 0x5c00);
	1022	memory_set_bankptr(machine(), "sprbank0", m_spriteram + 0x1000*4);   // scratch
	1023	memory_set_bankptr(machine(), "sprbank1", m_spriteram + 0x1000*4);   // scratch
1007	1024	break;
1008	1025
1009	1026	default:
1010		logerror("%s: unknown rom bank = %02x, reg = %02x\n", space->machine().describe_context(), data, state->m_reg);
	1027	logerror("%s: unknown rom bank = %02x, reg = %02x\n", machine().describe_context(), data, m_reg);
1011	1028	}
1012	1029	break;
1013	1030
1014	1031	case 0x4d:
1015		state->m_rombank = data;
	1032	m_rombank = data;
1016	1033	switch (data)
1017	1034	{
1018	1035	case 0x14:   // 3800 IS ROM
1019		memory_set_bankptr(space->machine(), "rombank0", rom + 0x8000);
1020		memory_set_bankptr(space->machine(), "rombank1", rom + 0x9000);
1021		memory_set_bankptr(space->machine(), "sprbank0", state->m_spriteram + 0x1000*4);   // scratch
1022		memory_set_bankptr(space->machine(), "sprbank1", state->m_spriteram + 0x1000*4);   // scratch
	1036	memory_set_bankptr(machine(), "rombank0", rom + 0x8000);
	1037	memory_set_bankptr(machine(), "rombank1", rom + 0x9000);
	1038	memory_set_bankptr(machine(), "sprbank0", m_spriteram + 0x1000*4);   // scratch
	1039	memory_set_bankptr(machine(), "sprbank1", m_spriteram + 0x1000*4);   // scratch
1023	1040	break;
1024	1041
1025	1042	default:
1026		logerror("%s: unknown rom bank = %02x, reg = %02x\n", space->machine().describe_context(), data, state->m_reg);
	1043	logerror("%s: unknown rom bank = %02x, reg = %02x\n", machine().describe_context(), data, m_reg);
1027	1044	}
1028	1045	break;
1029	1046
1030	1047	case 0x8d:
1031		state->m_rombank = data;
	1048	m_rombank = data;
1032	1049	switch (data)
1033	1050	{
1034	1051	case 0x0f:   // 3800 IS ROM
1035		memory_set_bankptr(space->machine(), "rombank0", rom + 0x3400);
1036		memory_set_bankptr(space->machine(), "rombank1", rom + 0x4400);
1037		memory_set_bankptr(space->machine(), "sprbank0", state->m_spriteram + 0x1000*4);   // scratch
1038		memory_set_bankptr(space->machine(), "sprbank1", state->m_spriteram + 0x1000*4);   // scratch
	1052	memory_set_bankptr(machine(), "rombank0", rom + 0x3400);
	1053	memory_set_bankptr(machine(), "rombank1", rom + 0x4400);
	1054	memory_set_bankptr(machine(), "sprbank0", m_spriteram + 0x1000*4);   // scratch
	1055	memory_set_bankptr(machine(), "sprbank1", m_spriteram + 0x1000*4);   // scratch
1039	1056	break;
1040	1057
1041	1058	case 0x12:   // 3800 IS ROM
1042		memory_set_bankptr(space->machine(), "rombank0", rom + 0x6400);
1043		memory_set_bankptr(space->machine(), "rombank1", rom + 0x7400);
1044		memory_set_bankptr(space->machine(), "sprbank0", state->m_spriteram + 0x1000*4);   // scratch
1045		memory_set_bankptr(space->machine(), "sprbank1", state->m_spriteram + 0x1000*4);   // scratch
	1059	memory_set_bankptr(machine(), "rombank0", rom + 0x6400);
	1060	memory_set_bankptr(machine(), "rombank1", rom + 0x7400);
	1061	memory_set_bankptr(machine(), "sprbank0", m_spriteram + 0x1000*4);   // scratch
	1062	memory_set_bankptr(machine(), "sprbank1", m_spriteram + 0x1000*4);   // scratch
1046	1063	break;
1047	1064
1048	1065	// used in test mode:
1049		//              case 0x5c:  memory_set_bankptr(space->machine(), "rombank", rom + 0x400 + 0x0000);    break;  // 3800 IS RAM! (8000 bytes)
	1066	//              case 0x5c:  memory_set_bankptr(machine(), "rombank", rom + 0x400 + 0x0000);    break;  // 3800 IS RAM! (8000 bytes)
1050	1067
1051	1068	case 0x5e:   // 3800 IS RAM! (1404 bytes)
1052		memory_set_bankptr(space->machine(), "rombank0", state->m_spriteram + 0x1000*1);
1053		memory_set_bankptr(space->machine(), "sprbank0", state->m_spriteram + 0x1000*1);
1054		memory_set_bankptr(space->machine(), "rombank1", state->m_spriteram + 0x1000*2);
1055		memory_set_bankptr(space->machine(), "sprbank1", state->m_spriteram + 0x1000*2);
	1069	memory_set_bankptr(machine(), "rombank0", m_spriteram + 0x1000*1);
	1070	memory_set_bankptr(machine(), "sprbank0", m_spriteram + 0x1000*1);
	1071	memory_set_bankptr(machine(), "rombank1", m_spriteram + 0x1000*2);
	1072	memory_set_bankptr(machine(), "sprbank1", m_spriteram + 0x1000*2);
1056	1073	break;
1057	1074
1058	1075	case 0x6c:   // 3800 IS RAM! (1000 bytes) - SPRITERAM
1059		memory_set_bankptr(space->machine(), "rombank0", state->m_spriteram);
1060		memory_set_bankptr(space->machine(), "sprbank0", state->m_spriteram);
1061		//                  memory_set_bankptr(space->machine(), "sprbank1", state->m_spriteram + 0x1000*4);    // scratch
	1076	memory_set_bankptr(machine(), "rombank0", m_spriteram);
	1077	memory_set_bankptr(machine(), "sprbank0", m_spriteram);
	1078	//                  memory_set_bankptr(machine(), "sprbank1", m_spriteram + 0x1000*4);    // scratch
1062	1079	break;
1063	1080
1064	1081	default:
1065		logerror("%s: unknown rom bank = %02x, reg = %02x\n", space->machine().describe_context(), data, state->m_reg);
	1082	logerror("%s: unknown rom bank = %02x, reg = %02x\n", machine().describe_context(), data, m_reg);
1066	1083	}
1067	1084	break;
1068	1085
1069	1086	case 0xcd:
1070		state->m_rombank = data;
	1087	m_rombank = data;
1071	1088	switch (data)
1072	1089	{
1073	1090	case 0x14:   // 3800 IS ROM
1074		memory_set_bankptr(space->machine(), "rombank0", rom + 0x8800);
1075		memory_set_bankptr(space->machine(), "rombank1", rom + 0x9800);
1076		memory_set_bankptr(space->machine(), "sprbank0", state->m_spriteram + 0x1000*4);   // scratch
1077		memory_set_bankptr(space->machine(), "sprbank1", state->m_spriteram + 0x1000*4);   // scratch
	1091	memory_set_bankptr(machine(), "rombank0", rom + 0x8800);
	1092	memory_set_bankptr(machine(), "rombank1", rom + 0x9800);
	1093	memory_set_bankptr(machine(), "sprbank0", m_spriteram + 0x1000*4);   // scratch
	1094	memory_set_bankptr(machine(), "sprbank1", m_spriteram + 0x1000*4);   // scratch
1078	1095	break;
1079	1096
1080	1097	default:
1081		logerror("%s: unknown rom bank = %02x, reg = %02x\n", space->machine().describe_context(), data, state->m_reg);
	1098	logerror("%s: unknown rom bank = %02x, reg = %02x\n", machine().describe_context(), data, m_reg);
1082	1099	}
1083	1100	break;
1084	1101
1085	1102	default:
1086		logerror("%s: unknown reg written: %02x = %02x\n", space->machine().describe_context(), state->m_reg, data);
	1103	logerror("%s: unknown reg written: %02x = %02x\n", machine().describe_context(), m_reg, data);
1087	1104	}
1088	1105	}
1089		static READ8_HANDLER( itazuram_rombank_r )
	1106	READ8_MEMBER(sigmab98_state::itazuram_rombank_r)
1090	1107	{
1091		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
1092	1108	if (offset == 0)
1093		return state->m_reg;
	1109	return m_reg;
1094	1110
1095		switch ( state->m_reg )
	1111	switch ( m_reg )
1096	1112	{
1097	1113	// FIXME different registers
1098	1114	case 0x0d:
1099	1115	case 0x4d:
1100	1116	case 0x8d:
1101	1117	case 0xcd:
1102		return state->m_rombank;
	1118	return m_rombank;
1103	1119
1104	1120	default:
1105		logerror("%s: unknown reg read: %02x\n", space->machine().describe_context(), state->m_reg);
	1121	logerror("%s: unknown reg read: %02x\n", machine().describe_context(), m_reg);
1106	1122	return 0x00;
1107	1123	}
1108	1124	}
1109	1125
1110	1126	// rambank
1111		static WRITE8_HANDLER( itazuram_rambank_w )
	1127	WRITE8_MEMBER(sigmab98_state::itazuram_rambank_w)
1112	1128	{
1113		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
1114	1129	if (offset == 0)
1115	1130	{
1116		state->m_reg2 = data;
	1131	m_reg2 = data;
1117	1132	return;
1118	1133	}
1119	1134
1120		switch ( state->m_reg2 )
	1135	switch ( m_reg2 )
1121	1136	{
1122	1137	case 0x76:
1123		state->m_rambank = data;
	1138	m_rambank = data;
1124	1139	switch (data)
1125	1140	{
1126		case 0x52:   memory_set_bankptr(space->machine(), "palbank", state->m_nvram);                           break;
1127		case 0x64:   memory_set_bankptr(space->machine(), "palbank", space->machine().generic.paletteram.u8);   break;
	1141	case 0x52:   memory_set_bankptr(machine(), "palbank", m_nvram);                           break;
	1142	case 0x64:   memory_set_bankptr(machine(), "palbank", machine().generic.paletteram.u8);   break;
1128	1143	default:
1129		logerror("%s: unknown ram bank = %02x, reg2 = %02x\n", space->machine().describe_context(), data, state->m_reg2);
	1144	logerror("%s: unknown ram bank = %02x, reg2 = %02x\n", machine().describe_context(), data, m_reg2);
1130	1145	return;
1131	1146	}
1132	1147	break;
1133	1148
1134	1149	default:
1135		logerror("%s: unknown reg2 written: %02x = %02x\n", space->machine().describe_context(), state->m_reg2, data);
	1150	logerror("%s: unknown reg2 written: %02x = %02x\n", machine().describe_context(), m_reg2, data);
1136	1151	}
1137	1152	}
1138	1153
1139		static READ8_HANDLER( itazuram_rambank_r )
	1154	READ8_MEMBER(sigmab98_state::itazuram_rambank_r)
1140	1155	{
1141		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
1142	1156	if (offset == 0)
1143		return state->m_reg2;
	1157	return m_reg2;
1144	1158
1145		switch ( state->m_reg2 )
	1159	switch ( m_reg2 )
1146	1160	{
1147	1161	case 0x76:
1148		return state->m_rambank;
	1162	return m_rambank;
1149	1163
1150	1164	default:
1151		logerror("%s: unknown reg2 read: %02x\n", space->machine().describe_context(), state->m_reg2);
	1165	logerror("%s: unknown reg2 read: %02x\n", machine().describe_context(), m_reg2);
1152	1166	return 0x00;
1153	1167	}
1154	1168	}
1155	1169
1156		static WRITE8_HANDLER( itazuram_nvram_palette_w )
	1170	WRITE8_MEMBER(sigmab98_state::itazuram_nvram_palette_w)
1157	1171	{
1158		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
1159		if (state->m_rambank == 0x64)
	1172	if (m_rambank == 0x64)
1160	1173	{
1161	1174	paletteram_xRRRRRGGGGGBBBBB_be_w(space, offset, data);
1162		//      space->machine().generic.paletteram.u8[offset] = data;
	1175	//      machine().generic.paletteram.u8[offset] = data;
1163	1176	}
1164		else if (state->m_rambank == 0x52)
	1177	else if (m_rambank == 0x52)
1165	1178	{
1166		state->m_nvram[offset] = data;
	1179	m_nvram[offset] = data;
1167	1180	}
1168	1181	else
1169	1182	{
1170		logerror("%s: itazuram_nvram_palette_w offset = %03x with unknown bank = %02x\n", space->machine().describe_context(), offset, state->m_rambank);
	1183	logerror("%s: itazuram_nvram_palette_w offset = %03x with unknown bank = %02x\n", machine().describe_context(), offset, m_rambank);
1171	1184	}
1172	1185	}
1173	1186
1174		static WRITE8_HANDLER( itazuram_palette_w )
	1187	WRITE8_MEMBER(sigmab98_state::itazuram_palette_w)
1175	1188	{
1176		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
1177		if (state->m_rombank == 0x6c)
	1189	if (m_rombank == 0x6c)
1178	1190	{
1179	1191	if (offset < 0x200)
1180	1192	paletteram_xRRRRRGGGGGBBBBB_be_w(space, offset, data);
1181		//          space->machine().generic.paletteram.u8[offset] = data;
	1193	//          machine().generic.paletteram.u8[offset] = data;
1182	1194	}
1183	1195	else
1184	1196	{
1185		logerror("%s: itazuram_palette_w offset = %03x with unknown bank = %02x\n", space->machine().describe_context(), offset, state->m_rombank);
	1197	logerror("%s: itazuram_palette_w offset = %03x with unknown bank = %02x\n", machine().describe_context(), offset, m_rombank);
1186	1198	}
1187	1199	}
1188		static READ8_HANDLER( itazuram_palette_r )
	1200	READ8_MEMBER(sigmab98_state::itazuram_palette_r)
1189	1201	{
1190		return space->machine().generic.paletteram.u8[offset];
	1202	return machine().generic.paletteram.u8[offset];
1191	1203	}
1192	1204
1193	1205	static ADDRESS_MAP_START( itazuram_map, AS_PROGRAM, 8, sigmab98_state )
r14845	r14846
1195	1207	AM_RANGE( 0x3800, 0x47ff ) AM_READ_BANK( "rombank0" ) AM_WRITE_BANK( "sprbank0" )
1196	1208	AM_RANGE( 0x4800, 0x57ff ) AM_READ_BANK( "rombank1" ) AM_WRITE_BANK( "sprbank1" )
1197	1209
1198		AM_RANGE( 0x5800, 0x59ff ) AM_READWRITE_LEGACY(itazuram_palette_r, itazuram_palette_w )
	1210	AM_RANGE( 0x5800, 0x59ff ) AM_READWRITE(itazuram_palette_r, itazuram_palette_w )
1199	1211	AM_RANGE( 0x6000, 0x607f ) AM_RAM   // table?
1200	1212
1201	1213	AM_RANGE( 0x6811, 0x6811 ) AM_WRITENOP   // IRQ Enable? Screen disable?
1202	1214	AM_RANGE( 0x6813, 0x6813 ) AM_WRITENOP   // IRQ Ack?
1203		AM_RANGE( 0xdc00, 0xfdff ) AM_READ_BANK( "palbank" ) AM_WRITE_LEGACY(itazuram_nvram_palette_w ) AM_SHARE( "nvram" ) AM_BASE(m_nvram )   // nvram | paletteram
	1215	AM_RANGE( 0xdc00, 0xfdff ) AM_READ_BANK( "palbank" ) AM_WRITE(itazuram_nvram_palette_w ) AM_SHARE( "nvram" ) AM_BASE(m_nvram )   // nvram | paletteram
1204	1216
1205	1217	AM_RANGE( 0xfe00, 0xffff ) AM_RAM   // High speed internal RAM
1206	1218	ADDRESS_MAP_END
1207	1219
1208	1220	static ADDRESS_MAP_START( itazuram_io, AS_IO, 8, sigmab98_state )
1209	1221	ADDRESS_MAP_GLOBAL_MASK(0xff)
1210		AM_RANGE( 0x02, 0x03 ) AM_READWRITE_LEGACY(itazuram_rombank_r, itazuram_rombank_w )
1211		AM_RANGE( 0x04, 0x05 ) AM_READWRITE_LEGACY(itazuram_rambank_r, itazuram_rambank_w )
	1222	AM_RANGE( 0x02, 0x03 ) AM_READWRITE(itazuram_rombank_r, itazuram_rombank_w )
	1223	AM_RANGE( 0x04, 0x05 ) AM_READWRITE(itazuram_rambank_r, itazuram_rambank_w )
1212	1224
1213	1225	AM_RANGE( 0x2c, 0x2c ) AM_DEVREADWRITE_LEGACY("eeprom", sammymdl_eeprom_r, sammymdl_eeprom_w )
1214		AM_RANGE( 0x2e, 0x2e ) AM_READ_LEGACY(sammymdl_coin_hopper_r )
	1226	AM_RANGE( 0x2e, 0x2e ) AM_READ(sammymdl_coin_hopper_r )
1215	1227	AM_RANGE( 0x30, 0x30 ) AM_READ_PORT( "BUTTON" )
1216		AM_RANGE( 0x31, 0x31 ) AM_WRITE_LEGACY(sammymdl_coin_w )
1217		AM_RANGE( 0x32, 0x32 ) AM_WRITE_LEGACY(sammymdl_leds_w )
	1228	AM_RANGE( 0x31, 0x31 ) AM_WRITE(sammymdl_coin_w )
	1229	AM_RANGE( 0x32, 0x32 ) AM_WRITE(sammymdl_leds_w )
1218	1230	AM_RANGE( 0x90, 0x90 ) AM_DEVWRITE("oki", okim9810_device, write )
1219	1231	AM_RANGE( 0x91, 0x91 ) AM_DEVWRITE("oki", okim9810_device, write_TMP_register )
1220	1232	AM_RANGE( 0x92, 0x92 ) AM_DEVREAD("oki", okim9810_device, read )
1221		AM_RANGE( 0xb0, 0xb0 ) AM_WRITE_LEGACY(sammymdl_hopper_w )
	1233	AM_RANGE( 0xb0, 0xb0 ) AM_WRITE(sammymdl_hopper_w )
1222	1234	AM_RANGE( 0xc0, 0xc0 ) AM_WRITE_LEGACY(watchdog_reset_w )   // 1
1223	1235	ADDRESS_MAP_END
1224	1236
r14845	r14846
1227	1239	***************************************************************************/
1228	1240
1229	1241	static ADDRESS_MAP_START( pyenaget_io, AS_IO, 8, sigmab98_state )
1230		AM_RANGE( 0x31, 0x31 ) AM_WRITE_LEGACY(sammymdl_coin_w )
	1242	AM_RANGE( 0x31, 0x31 ) AM_WRITE(sammymdl_coin_w )
1231	1243	AM_IMPORT_FROM( haekaka_io )
1232	1244	ADDRESS_MAP_END
1233	1245
r14845	r14846
1236	1248	***************************************************************************/
1237	1249
1238	1250	// rombank
1239		static WRITE8_HANDLER( tdoboon_rombank_w )
	1251	WRITE8_MEMBER(sigmab98_state::tdoboon_rombank_w)
1240	1252	{
1241		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
1242	1253	if (offset == 0)
1243	1254	{
1244		state->m_reg = data;
	1255	m_reg = data;
1245	1256	return;
1246	1257	}
1247	1258
1248		switch ( state->m_reg )
	1259	switch ( m_reg )
1249	1260	{
1250	1261	case 0x2f:
1251		state->m_rombank = data;
	1262	m_rombank = data;
1252	1263	switch (data)
1253	1264	{
1254	1265	case 0x10:   // ROM
r14845	r14846
1274	1285	break;
1275	1286
1276	1287	default:
1277		logerror("%s: unknown rom bank = %02x, reg = %02x\n", space->machine().describe_context(), data, state->m_reg);
	1288	logerror("%s: unknown rom bank = %02x, reg = %02x\n", machine().describe_context(), data, m_reg);
1278	1289	}
1279	1290	break;
1280	1291
1281	1292	default:
1282		logerror("%s: unknown reg written: %02x = %02x\n", space->machine().describe_context(), state->m_reg, data);
	1293	logerror("%s: unknown reg written: %02x = %02x\n", machine().describe_context(), m_reg, data);
1283	1294	}
1284	1295	}
1285		static READ8_HANDLER( tdoboon_rombank_r )
	1296	READ8_MEMBER(sigmab98_state::tdoboon_rombank_r)
1286	1297	{
1287		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
1288	1298	if (offset == 0)
1289		return state->m_reg;
	1299	return m_reg;
1290	1300
1291		switch ( state->m_reg )
	1301	switch ( m_reg )
1292	1302	{
1293	1303	case 0x2f:
1294		return state->m_rombank;
	1304	return m_rombank;
1295	1305
1296	1306	default:
1297		logerror("%s: unknown reg read: %02x\n", space->machine().describe_context(), state->m_reg);
	1307	logerror("%s: unknown reg read: %02x\n", machine().describe_context(), m_reg);
1298	1308	return 0x00;
1299	1309	}
1300	1310	}
1301	1311
1302	1312	// rambank
1303		static WRITE8_HANDLER( tdoboon_rambank_w )
	1313	WRITE8_MEMBER(sigmab98_state::tdoboon_rambank_w)
1304	1314	{
1305		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
1306	1315	if (offset == 0)
1307	1316	{
1308		state->m_reg2 = data;
	1317	m_reg2 = data;
1309	1318	return;
1310	1319	}
1311	1320
1312		switch ( state->m_reg2 )
	1321	switch ( m_reg2 )
1313	1322	{
1314	1323	case 0x33:
1315		state->m_rambank = data;
	1324	m_rambank = data;
1316	1325	switch (data)
1317	1326	{
1318	1327	case 0x53:
1319	1328	break;
1320	1329
1321	1330	default:
1322		logerror("%s: unknown ram bank = %02x, reg2 = %02x\n", space->machine().describe_context(), data, state->m_reg2);
	1331	logerror("%s: unknown ram bank = %02x, reg2 = %02x\n", machine().describe_context(), data, m_reg2);
1323	1332	}
1324	1333	break;
1325	1334
1326	1335	default:
1327		logerror("%s: unknown reg2 written: %02x = %02x\n", space->machine().describe_context(), state->m_reg2, data);
	1336	logerror("%s: unknown reg2 written: %02x = %02x\n", machine().describe_context(), m_reg2, data);
1328	1337	}
1329	1338	}
1330		static READ8_HANDLER( tdoboon_rambank_r )
	1339	READ8_MEMBER(sigmab98_state::tdoboon_rambank_r)
1331	1340	{
1332		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
1333	1341	if (offset == 0)
1334		return state->m_reg2;
	1342	return m_reg2;
1335	1343
1336		switch ( state->m_reg2 )
	1344	switch ( m_reg2 )
1337	1345	{
1338	1346	case 0x33:
1339		return state->m_rambank;
	1347	return m_rambank;
1340	1348
1341	1349	default:
1342		logerror("%s: unknown reg2 read: %02x\n", space->machine().describe_context(), state->m_reg2);
	1350	logerror("%s: unknown reg2 read: %02x\n", machine().describe_context(), m_reg2);
1343	1351	return 0x00;
1344	1352	}
1345	1353	}
1346	1354
1347		static READ8_HANDLER( tdoboon_c000_r )
	1355	READ8_MEMBER(sigmab98_state::tdoboon_c000_r)
1348	1356	{
1349		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
1350		switch (state->m_rombank)
	1357	switch (m_rombank)
1351	1358	{
1352	1359	case 0x10:   // ROM
1353	1360	case 0x11:
r14845	r14846
1365	1372	case 0x1d:
1366	1373	case 0x1e:
1367	1374	case 0x1f:
1368		return space->machine().region("maincpu")->base()[offset + 0xc400 + 0x1000 * (state->m_rombank-0x10)];
	1375	return machine().region("maincpu")->base()[offset + 0xc400 + 0x1000 * (m_rombank-0x10)];
1369	1376
1370	1377	case 0x64:   // SPRITERAM
1371	1378	if (offset < 0x1000)
1372		return state->m_spriteram[offset];
	1379	return m_spriteram[offset];
1373	1380	break;
1374	1381
1375	1382	case 0x66:   // PALETTERAM + TABLE?
1376	1383	if (offset < 0x200)
1377		return space->machine().generic.paletteram.u8[offset];
	1384	return machine().generic.paletteram.u8[offset];
1378	1385	break;
1379	1386
1380	1387	case 0x67:   // REGS
r14845	r14846
1383	1390	break;
1384	1391	}
1385	1392
1386		logerror("%s: unknown read from %02x with rombank = %02x\n", space->machine().describe_context(), offset+0xc000, state->m_rombank);
	1393	logerror("%s: unknown read from %02x with rombank = %02x\n", machine().describe_context(), offset+0xc000, m_rombank);
1387	1394	return 0x00;
1388	1395	}
1389	1396
1390		static WRITE8_HANDLER( tdoboon_c000_w )
	1397	WRITE8_MEMBER(sigmab98_state::tdoboon_c000_w)
1391	1398	{
1392		sigmab98_state *state = space->machine().driver_data<sigmab98_state>();
1393		switch (state->m_rombank)
	1399	switch (m_rombank)
1394	1400	{
1395	1401	case 0x64:   // SPRITERAM
1396	1402	if (offset < 0x1000)
1397	1403	{
1398		state->m_spriteram[offset] = data;
	1404	m_spriteram[offset] = data;
1399	1405	return;
1400	1406	}
1401	1407	break;
r14845	r14846
1404	1410	if (offset < 0x200)
1405	1411	{
1406	1412	paletteram_xRRRRRGGGGGBBBBB_be_w(space, offset, data);
1407		//              space->machine().generic.paletteram.u8[offset] = data;
	1413	//              machine().generic.paletteram.u8[offset] = data;
1408	1414	return;
1409	1415	}
1410	1416	else if ((offset >= 0x800) && (offset < 0x880))
r14845	r14846
1415	1421	break;
1416	1422	}
1417	1423
1418		logerror("%s: unknown write to %02x = %02x with rombank = %02x\n", space->machine().describe_context(), offset+0xc000, data, state->m_rombank);
	1424	logerror("%s: unknown write to %02x = %02x with rombank = %02x\n", machine().describe_context(), offset+0xc000, data, m_rombank);
1419	1425	}
1420	1426
1421	1427	static ADDRESS_MAP_START( tdoboon_map, AS_PROGRAM, 8, sigmab98_state )
1422	1428	AM_RANGE( 0x0000, 0xbfff ) AM_ROM
1423		AM_RANGE( 0xc000, 0xcfff ) AM_READWRITE_LEGACY(tdoboon_c000_r, tdoboon_c000_w )
	1429	AM_RANGE( 0xc000, 0xcfff ) AM_READWRITE(tdoboon_c000_r, tdoboon_c000_w )
1424	1430	AM_RANGE( 0xd000, 0xefff ) AM_RAM AM_SHARE( "nvram" ) AM_BASE(m_nvram )
1425	1431	AM_RANGE( 0xfe00, 0xffff ) AM_RAM   // High speed internal RAM
1426	1432	ADDRESS_MAP_END
1427	1433
1428	1434	static ADDRESS_MAP_START( tdoboon_io, AS_IO, 8, sigmab98_state )
1429	1435	ADDRESS_MAP_GLOBAL_MASK(0xff)
1430		AM_RANGE( 0x02, 0x03 ) AM_READWRITE_LEGACY(tdoboon_rombank_r, tdoboon_rombank_w )
1431		AM_RANGE( 0x04, 0x05 ) AM_READWRITE_LEGACY(tdoboon_rambank_r, tdoboon_rambank_w )
	1436	AM_RANGE( 0x02, 0x03 ) AM_READWRITE(tdoboon_rombank_r, tdoboon_rombank_w )
	1437	AM_RANGE( 0x04, 0x05 ) AM_READWRITE(tdoboon_rambank_r, tdoboon_rambank_w )
1432	1438
1433	1439	AM_RANGE( 0x2c, 0x2c ) AM_DEVREADWRITE_LEGACY("eeprom", sammymdl_eeprom_r, sammymdl_eeprom_w )
1434		AM_RANGE( 0x2e, 0x2e ) AM_READ_LEGACY(sammymdl_coin_hopper_r )
	1440	AM_RANGE( 0x2e, 0x2e ) AM_READ(sammymdl_coin_hopper_r )
1435	1441	AM_RANGE( 0x30, 0x30 ) AM_READ_PORT( "BUTTON" )
1436		AM_RANGE( 0x31, 0x31 ) AM_WRITE_LEGACY(sammymdl_coin_w )
1437		AM_RANGE( 0x32, 0x32 ) AM_WRITE_LEGACY(sammymdl_leds_w )
	1442	AM_RANGE( 0x31, 0x31 ) AM_WRITE(sammymdl_coin_w )
	1443	AM_RANGE( 0x32, 0x32 ) AM_WRITE(sammymdl_leds_w )
1438	1444	AM_RANGE( 0x90, 0x90 ) AM_DEVWRITE("oki", okim9810_device, write )
1439	1445	AM_RANGE( 0x91, 0x91 ) AM_DEVWRITE("oki", okim9810_device, write_TMP_register )
1440	1446	AM_RANGE( 0x92, 0x92 ) AM_DEVREAD("oki", okim9810_device, read )
1441		AM_RANGE( 0xb0, 0xb0 ) AM_WRITE_LEGACY(sammymdl_hopper_w )
	1447	AM_RANGE( 0xb0, 0xb0 ) AM_WRITE(sammymdl_hopper_w )
1442	1448	AM_RANGE( 0xc0, 0xc0 ) AM_WRITE_LEGACY(watchdog_reset_w )   // 1
1443	1449	ADDRESS_MAP_END
1444	1450

src/mame/drivers/popobear.c

r14845	r14846
90	90	UINT16 *m_vram;
91	91	UINT16 *m_spr;
92	92	required_device<cpu_device> m_maincpu;
	93	DECLARE_READ8_MEMBER(popo_620000_r);
	94	DECLARE_WRITE8_MEMBER(popobear_irq_ack_w);
93	95	};
94	96
95	97	VIDEO_START(popobear)
r14845	r14846
267	269	}
268	270
269	271	/* ??? */
270		static READ8_HANDLER( popo_620000_r )
	272	READ8_MEMBER(popobear_state::popo_620000_r)
271	273	{
272	274	return 9;
273	275	}
274	276
275		static WRITE8_HANDLER( popobear_irq_ack_w )
	277	WRITE8_MEMBER(popobear_state::popobear_irq_ack_w)
276	278	{
277		popobear_state *state = space->machine().driver_data<popobear_state>();
278	279	int i;
279	280
280	281	for(i=0;i<8;i++)
281	282	{
282	283	if(data & 1 << i)
283		device_set_input_line(state->m_maincpu, i, CLEAR_LINE);
	284	device_set_input_line(m_maincpu, i, CLEAR_LINE);
284	285	}
285	286	}
286	287
r14845	r14846
298	299	//  AM_RANGE(0x480020, 0x480021) AM_NOP //AM_READ_LEGACY(popo_480020_r) AM_WRITE_LEGACY(popo_480020_w)
299	300	//  AM_RANGE(0x480028, 0x480029) AM_NOP //AM_WRITE_LEGACY(popo_480028_w)
300	301	//  AM_RANGE(0x48002c, 0x48002d) AM_NOP //AM_WRITE_LEGACY(popo_48002c_w)
301		AM_RANGE(0x480030, 0x480031) AM_WRITE8_LEGACY(popobear_irq_ack_w, 0x00ff)
	302	AM_RANGE(0x480030, 0x480031) AM_WRITE8(popobear_irq_ack_w, 0x00ff)
302	303	AM_RANGE(0x480034, 0x480035) AM_RAM // coin counter or coin lockout
303	304	AM_RANGE(0x48003a, 0x48003b) AM_RAM //AM_READ_LEGACY(popo_48003a_r) AM_WRITE_LEGACY(popo_48003a_w)
304	305
r14845	r14846
310	311	AM_RANGE(0x550000, 0x550003) AM_DEVWRITE8_LEGACY("ymsnd", ym2413_w, 0x00ff )
311	312
312	313	AM_RANGE(0x600000, 0x600001) AM_WRITENOP
313		AM_RANGE(0x620000, 0x620001) AM_READ8_LEGACY(popo_620000_r,0xff00) AM_WRITENOP
	314	AM_RANGE(0x620000, 0x620001) AM_READ8(popo_620000_r,0xff00) AM_WRITENOP
314	315	AM_RANGE(0x800000, 0x9fffff) AM_ROM AM_REGION("gfx1", 0) // u5 & u6
315	316	AM_RANGE(0xa00000, 0xbfffff) AM_ROM AM_REGION("gfx2", 0) // u7 & u8
316	317	ADDRESS_MAP_END

src/mame/drivers/mpu3.c

r14845	r14846
152	152	int m_optic_pattern;
153	153
154	154	emu_timer *m_ic21_timer;
	155	DECLARE_WRITE8_MEMBER(characteriser_w);
	156	DECLARE_READ8_MEMBER(characteriser_r);
	157	DECLARE_WRITE8_MEMBER(mpu3ptm_w);
	158	DECLARE_READ8_MEMBER(mpu3ptm_r);
155	159	};
156	160
157	161	#define DISPLAY_PORT 0
r14845	r14846
790	794	address of the PAL in memory varies between games. Once found, the memory location of the data table is easily found from the X register of the CPU.
791	795	*/
792	796
793		static WRITE8_HANDLER( characteriser_w )
	797	WRITE8_MEMBER(mpu3_state::characteriser_w)
794	798	{
795		mpu3_state *state = space->machine().driver_data<mpu3_state>();
796	799	int x;
797	800	int call=data;
798		if (!state->m_current_chr_table)
799		fatalerror("No Characteriser Table @ %04x\n", cpu_get_previouspc(&space->device()));
	801	if (!m_current_chr_table)
	802	fatalerror("No Characteriser Table @ %04x\n", cpu_get_previouspc(&space.device()));
800	803
801	804	if (offset == 0)
802	805	{
803	806	{
804	807	if (call == 0)
805	808	{
806		state->m_prot_col = 0;
	809	m_prot_col = 0;
807	810	}
808	811	else
809	812	{
810		for (x = state->m_prot_col; x < 64; x++)
	813	for (x = m_prot_col; x < 64; x++)
811	814	{
812		if   (state->m_current_chr_table[(x)].call == call)
	815	if   (m_current_chr_table[(x)].call == call)
813	816	{
814		state->m_prot_col = x;
	817	m_prot_col = x;
815	818	break;
816	819	}
817	820	}
r14845	r14846
821	824	}
822	825
823	826
824		static READ8_HANDLER( characteriser_r )
	827	READ8_MEMBER(mpu3_state::characteriser_r)
825	828	{
826		mpu3_state *state = space->machine().driver_data<mpu3_state>();
827		if (!state->m_current_chr_table)
828		fatalerror("No Characteriser Table @ %04x\n", cpu_get_previouspc(&space->device()));
	829	if (!m_current_chr_table)
	830	fatalerror("No Characteriser Table @ %04x\n", cpu_get_previouspc(&space.device()));
829	831
830	832	if (offset == 0)
831	833	{
832		return state->m_current_chr_table[state->m_prot_col].response;
	834	return m_current_chr_table[m_prot_col].response;
833	835	}
834	836	return 0;
835	837	}
r14845	r14846
857	859	timer.machine().device<pia6821_device>("pia_ic4")->ca1_w(state->m_ic10_output);
858	860
859	861	}
860		static WRITE8_HANDLER( mpu3ptm_w )
	862	WRITE8_MEMBER(mpu3_state::mpu3ptm_w)
861	863	{
862		ptm6840_device *ptm2 = space->machine().device<ptm6840_device>("ptm_ic2");
	864	ptm6840_device *ptm2 = machine().device<ptm6840_device>("ptm_ic2");
863	865
864	866	ptm2->write(offset >>2,data);//((offset & 0x1f) >>2),data);
865	867	}
866	868
867		static READ8_HANDLER( mpu3ptm_r )
	869	READ8_MEMBER(mpu3_state::mpu3ptm_r)
868	870	{
869		ptm6840_device *ptm2 = space->machine().device<ptm6840_device>("ptm_ic2");
	871	ptm6840_device *ptm2 = machine().device<ptm6840_device>("ptm_ic2");
870	872
871	873	return ptm2->read(offset >>2);
872	874	}
873	875
874	876	static ADDRESS_MAP_START( mpu3_basemap, AS_PROGRAM, 8, mpu3_state )
875	877	AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("nvram")
876		AM_RANGE(0x8800, 0x881f) AM_READWRITE_LEGACY(mpu3ptm_r, mpu3ptm_w)/* PTM6840 IC2 */
	878	AM_RANGE(0x8800, 0x881f) AM_READWRITE(mpu3ptm_r, mpu3ptm_w)/* PTM6840 IC2 */
877	879	AM_RANGE(0x9000, 0x9003) AM_DEVREADWRITE("pia_ic3", pia6821_device, read, write)      /* PIA6821 IC3 */
878	880	AM_RANGE(0x9800, 0x9803) AM_DEVREADWRITE("pia_ic4", pia6821_device, read, write)      /* PIA6821 IC4 */
879	881	AM_RANGE(0xa000, 0xa003) AM_DEVREADWRITE("pia_ic5", pia6821_device, read, write)      /* PIA6821 IC5 */
r14845	r14846
923	925
924	926	state->m_disp_func=METER_PORT;
925	927	state->m_current_chr_table = hprvpr_data;
926		space->install_legacy_readwrite_handler(0xc000, 0xc000 , FUNC(characteriser_r),FUNC(characteriser_w));
	928	space->install_readwrite_handler(0xc000, 0xc000 , read8_delegate(FUNC(mpu3_state::characteriser_r), state),write8_delegate(FUNC(mpu3_state::characteriser_w), state));
927	929
928	930	}
929	931

src/mame/drivers/goodejan.c

r14845	r14846
64	64	: driver_device(mconfig, type, tag) { }
65	65
66	66	UINT16 m_mux_data;
	67	DECLARE_WRITE16_MEMBER(goodejan_gfxbank_w);
	68	DECLARE_READ16_MEMBER(mahjong_panel_r);
	69	DECLARE_WRITE16_MEMBER(mahjong_panel_w);
67	70	};
68	71
69	72
r14845	r14846
72	75	#define GOODEJAN_MHZ3 12000000
73	76
74	77
75		static WRITE16_HANDLER( goodejan_gfxbank_w )
	78	WRITE16_MEMBER(goodejan_state::goodejan_gfxbank_w)
76	79	{
77	80	seibucrtc_sc0bank_w((data & 0x100)>>8);// = (data & 0x100)>>8;
78	81	}
79	82
80	83	/* Multiplexer device for the mahjong panel */
81		static READ16_HANDLER( mahjong_panel_r )
	84	READ16_MEMBER(goodejan_state::mahjong_panel_r)
82	85	{
83		goodejan_state *state = space->machine().driver_data<goodejan_state>();
84	86	UINT16 ret;
85	87	ret = 0xffff;
86	88
87		switch(state->m_mux_data)
	89	switch(m_mux_data)
88	90	{
89		case 1:    ret = input_port_read(space->machine(), "KEY0"); break;
90		case 2:    ret = input_port_read(space->machine(), "KEY1"); break;
91		case 4:    ret = input_port_read(space->machine(), "KEY2"); break;
92		case 8:    ret = input_port_read(space->machine(), "KEY3"); break;
93		case 0x10: ret = input_port_read(space->machine(), "KEY4"); break;
	91	case 1:    ret = input_port_read(machine(), "KEY0"); break;
	92	case 2:    ret = input_port_read(machine(), "KEY1"); break;
	93	case 4:    ret = input_port_read(machine(), "KEY2"); break;
	94	case 8:    ret = input_port_read(machine(), "KEY3"); break;
	95	case 0x10: ret = input_port_read(machine(), "KEY4"); break;
94	96	}
95	97
96	98	return ret;
97	99	}
98	100
99		static WRITE16_HANDLER( mahjong_panel_w )
	101	WRITE16_MEMBER(goodejan_state::mahjong_panel_w)
100	102	{
101		goodejan_state *state = space->machine().driver_data<goodejan_state>();
102		state->m_mux_data = data;
	103	m_mux_data = data;
103	104	}
104	105
105	106	static ADDRESS_MAP_START( goodejan_map, AS_PROGRAM, 16, goodejan_state )
r14845	r14846
116	117
117	118	/*totmejan CRT is at 8000-804f,goodejan is at 8040-807f(808f but not tested)*/
118	119	static ADDRESS_MAP_START( common_io_map, AS_IO, 16, goodejan_state )
119		AM_RANGE(0x9000, 0x9001) AM_WRITE_LEGACY(goodejan_gfxbank_w)
	120	AM_RANGE(0x9000, 0x9001) AM_WRITE(goodejan_gfxbank_w)
120	121	AM_RANGE(0xb000, 0xb003) AM_WRITENOP
121		AM_RANGE(0xb004, 0xb005) AM_WRITE_LEGACY(mahjong_panel_w)
	122	AM_RANGE(0xb004, 0xb005) AM_WRITE(mahjong_panel_w)
122	123
123	124	AM_RANGE(0xc000, 0xc001) AM_READ_PORT("DSW1")
124		AM_RANGE(0xc002, 0xc003) AM_READ_LEGACY(mahjong_panel_r)
	125	AM_RANGE(0xc002, 0xc003) AM_READ(mahjong_panel_r)
125	126	AM_RANGE(0xc004, 0xc005) AM_READ_PORT("DSW2") // switches
126	127	AM_RANGE(0xd000, 0xd00f) AM_READWRITE_LEGACY(seibu_main_word_r, seibu_main_word_w)
127	128	ADDRESS_MAP_END

src/mame/drivers/quizshow.c

r14845	r14846
45	45	int m_blink_state;
46	46	int m_category_enable;
47	47	int m_tape_head_pos;
	48	DECLARE_WRITE8_MEMBER(quizshow_lamps1_w);
	49	DECLARE_WRITE8_MEMBER(quizshow_lamps2_w);
	50	DECLARE_WRITE8_MEMBER(quizshow_lamps3_w);
	51	DECLARE_WRITE8_MEMBER(quizshow_tape_control_w);
	52	DECLARE_WRITE8_MEMBER(quizshow_audio_w);
	53	DECLARE_WRITE8_MEMBER(quizshow_video_disable_w);
	54	DECLARE_READ8_MEMBER(quizshow_timing_r);
	55	DECLARE_READ8_MEMBER(quizshow_tape_signal_r);
	56	DECLARE_WRITE8_MEMBER(quizshow_main_ram_w);
48	57	};
49	58
50	59
r14845	r14846
104	113
105	114	***************************************************************************/
106	115
107		static WRITE8_HANDLER(quizshow_lamps1_w)
	116	WRITE8_MEMBER(quizshow_state::quizshow_lamps1_w)
108	117	{
109	118	// d0-d3: P1 answer button lamps
110	119	for (int i = 0; i < 4; i++)
r14845	r14846
113	122	// d4-d7: N/C
114	123	}
115	124
116		static WRITE8_HANDLER(quizshow_lamps2_w)
	125	WRITE8_MEMBER(quizshow_state::quizshow_lamps2_w)
117	126	{
118	127	// d0-d3: P2 answer button lamps
119	128	for (int i = 0; i < 4; i++)
r14845	r14846
122	131	// d4-d7: N/C
123	132	}
124	133
125		static WRITE8_HANDLER(quizshow_lamps3_w)
	134	WRITE8_MEMBER(quizshow_state::quizshow_lamps3_w)
126	135	{
127	136	// d0-d1: start button lamps
128	137	output_set_lamp_value(8, data >> 0 & 1);
r14845	r14846
132	141	// d4-d7: N/C
133	142	}
134	143
135		static WRITE8_HANDLER(quizshow_tape_control_w)
	144	WRITE8_MEMBER(quizshow_state::quizshow_tape_control_w)
136	145	{
137		quizshow_state *state = space->machine().driver_data<quizshow_state>();
138	146
139	147	// d2: enable user category select (changes tape head position)
140	148	output_set_lamp_value(10, data >> 2 & 1);
141		state->m_category_enable = (data & 0xc) == 0xc;
	149	m_category_enable = (data & 0xc) == 0xc;
142	150
143	151	// d3: tape motor
144	152	// TODO
r14845	r14846
147	155	// d4-d7: N/C
148	156	}
149	157
150		static WRITE8_HANDLER(quizshow_audio_w)
	158	WRITE8_MEMBER(quizshow_state::quizshow_audio_w)
151	159	{
152	160	// d1: audio beep on/off
153	161	// TODO
r14845	r14846
155	163	// d0, d2-d7: N/C
156	164	}
157	165
158		static WRITE8_HANDLER(quizshow_video_disable_w)
	166	WRITE8_MEMBER(quizshow_state::quizshow_video_disable_w)
159	167	{
160	168	// d0: video disable (looked glitchy when I implemented it, maybe there's more to it)
161	169	// d1-d7: N/C
162	170	}
163	171
164		static READ8_HANDLER(quizshow_timing_r)
	172	READ8_MEMBER(quizshow_state::quizshow_timing_r)
165	173	{
166		quizshow_state *state = space->machine().driver_data<quizshow_state>();
167	174	UINT8 ret = 0x80;
168	175
169	176	// d0-d3: 1R-8R (16-line counter)
170		ret |= state->m_clocks >> 1 & 0xf;
	177	ret |= m_clocks >> 1 & 0xf;
171	178
172	179	// d4: 8VAC?, use 8V instead
173		ret |= state->m_clocks << 4 & 0x10;
	180	ret |= m_clocks << 4 & 0x10;
174	181
175	182	// d5-d6: 4F-8F
176		ret |= state->m_clocks >> 2 & 0x60;
	183	ret |= m_clocks >> 2 & 0x60;
177	184
178	185	// d7: display busy/idle, during in-between tilerows(?) and blanking
179		if (space->machine().primary_screen->vpos() >= VBSTART || (space->machine().primary_screen->vpos() + 4) & 8)
	186	if (machine().primary_screen->vpos() >= VBSTART || (machine().primary_screen->vpos() + 4) & 8)
180	187	ret &= 0x7f;
181	188
182	189	return ret;
183	190	}
184	191
185		static READ8_HANDLER(quizshow_tape_signal_r)
	192	READ8_MEMBER(quizshow_state::quizshow_tape_signal_r)
186	193	{
187	194	// TODO (for now, hold INS to fastforward and it'll show garbage questions where D is always(?) the right answer)
188		return space->machine().rand() & 0x80;
	195	return machine().rand() & 0x80;
189	196	}
190	197
191		static WRITE8_HANDLER(quizshow_main_ram_w)
	198	WRITE8_MEMBER(quizshow_state::quizshow_main_ram_w)
192	199	{
193		quizshow_state *state = space->machine().driver_data<quizshow_state>();
194		state->m_main_ram[offset]=data;
195		state->m_tilemap->mark_tile_dirty(offset);
	200	m_main_ram[offset]=data;
	201	m_tilemap->mark_tile_dirty(offset);
196	202	}
197	203
198	204
199	205	static ADDRESS_MAP_START( quizshow_mem_map, AS_PROGRAM, 8, quizshow_state )
200	206	ADDRESS_MAP_GLOBAL_MASK(0x7fff)
201	207	AM_RANGE(0x0000, 0x0bff) AM_ROM
202		AM_RANGE(0x1802, 0x1802) AM_WRITE_LEGACY(quizshow_audio_w)
203		AM_RANGE(0x1804, 0x1804) AM_WRITE_LEGACY(quizshow_lamps1_w)
204		AM_RANGE(0x1808, 0x1808) AM_WRITE_LEGACY(quizshow_lamps2_w)
205		AM_RANGE(0x1810, 0x1810) AM_WRITE_LEGACY(quizshow_lamps3_w)
206		AM_RANGE(0x1820, 0x1820) AM_WRITE_LEGACY(quizshow_tape_control_w)
207		AM_RANGE(0x1840, 0x1840) AM_WRITE_LEGACY(quizshow_video_disable_w)
	208	AM_RANGE(0x1802, 0x1802) AM_WRITE(quizshow_audio_w)
	209	AM_RANGE(0x1804, 0x1804) AM_WRITE(quizshow_lamps1_w)
	210	AM_RANGE(0x1808, 0x1808) AM_WRITE(quizshow_lamps2_w)
	211	AM_RANGE(0x1810, 0x1810) AM_WRITE(quizshow_lamps3_w)
	212	AM_RANGE(0x1820, 0x1820) AM_WRITE(quizshow_tape_control_w)
	213	AM_RANGE(0x1840, 0x1840) AM_WRITE(quizshow_video_disable_w)
208	214	AM_RANGE(0x1881, 0x1881) AM_READ_PORT("IN0")
209	215	AM_RANGE(0x1882, 0x1882) AM_READ_PORT("IN1")
210	216	AM_RANGE(0x1884, 0x1884) AM_READ_PORT("IN2")
211	217	AM_RANGE(0x1888, 0x1888) AM_READ_PORT("IN3")
212		AM_RANGE(0x1900, 0x1900) AM_READ_LEGACY(quizshow_timing_r)
213		AM_RANGE(0x1e00, 0x1fff) AM_RAM_WRITE_LEGACY(quizshow_main_ram_w) AM_BASE(m_main_ram)
	218	AM_RANGE(0x1900, 0x1900) AM_READ(quizshow_timing_r)
	219	AM_RANGE(0x1e00, 0x1fff) AM_RAM_WRITE(quizshow_main_ram_w) AM_BASE(m_main_ram)
214	220	ADDRESS_MAP_END
215	221
216	222	static ADDRESS_MAP_START( quizshow_io_map, AS_IO, 8, quizshow_state )
217	223	ADDRESS_MAP_UNMAP_HIGH
218	224	//   AM_RANGE(S2650_CTRL_PORT, S2650_CTRL_PORT) AM_NOP // unused
219	225	//   AM_RANGE(S2650_DATA_PORT, S2650_DATA_PORT) AM_NOP // unused
220		AM_RANGE(S2650_SENSE_PORT, S2650_SENSE_PORT) AM_READ_LEGACY(quizshow_tape_signal_r)
	226	AM_RANGE(S2650_SENSE_PORT, S2650_SENSE_PORT) AM_READ(quizshow_tape_signal_r)
221	227	AM_RANGE(S2650_FO_PORT, S2650_FO_PORT) AM_RAM AM_BASE(m_fo_state)
222	228	ADDRESS_MAP_END
223	229

src/mame/drivers/peyper.c

r14845	r14846
12	12
13	13	UINT8 display_block;
14	14	UINT8 display[16];
	15	DECLARE_READ8_MEMBER(sw_r);
	16	DECLARE_WRITE8_MEMBER(col_w);
	17	DECLARE_WRITE8_MEMBER(disp_w);
	18	DECLARE_WRITE8_MEMBER(lamp_w);
	19	DECLARE_WRITE8_MEMBER(lamp7_w);
	20	DECLARE_WRITE8_MEMBER(sol_w);
15	21	};
16	22
17	23
18		static READ8_HANDLER(sw_r)
	24	READ8_MEMBER(peyper_state::sw_r)
19	25	{
20	26	return 0xff;
21	27	}
22	28
23		static WRITE8_HANDLER(col_w)
	29	WRITE8_MEMBER(peyper_state::col_w)
24	30	{
25		peyper_state *state = space->machine().driver_data<peyper_state>();
26	31
27		if (data==0x90) state->display_block = 0;
	32	if (data==0x90) display_block = 0;
28	33	}
29	34
30	35	static const UINT8 hex_to_7seg[16] =
r14845	r14846
34	39	0x00, 0x00, 0x00, 0x00 };
35	40
36	41	/* seems to only work correctly for 'solarwap', 'poleposn' and 'sonstwar' (look at how high-scores are displayed for example) - or shall layout be changed ? */
37		static WRITE8_HANDLER(disp_w)
	42	WRITE8_MEMBER(peyper_state::disp_w)
38	43	{
39		peyper_state *state = space->machine().driver_data<peyper_state>();
40		state->display[state->display_block] = data;
	44	display[display_block] = data;
41	45
42	46	UINT8 a = data & 0x0f;
43	47	UINT8 b = data >> 4;
r14845	r14846
53	57	6 -> DPL19,DPL1
54	58	7 -> DPL30,DPL33
55	59	*/
56		switch(state->display_block) {
	60	switch(display_block) {
57	61	case 0 :
58	62	output_set_indexed_value("dpl_",25,hex_a);
59	63	output_set_indexed_value("dpl_",27,hex_b);
r14845	r14846
141	145	break;
142	146	}
143	147
144		state->display_block++;
145		state->display_block&=0x0f;
	148	display_block++;
	149	display_block&=0x0f;
146	150	}
147	151
148		static WRITE8_HANDLER(lamp_w)
	152	WRITE8_MEMBER(peyper_state::lamp_w)
149	153	{
150	154	//logerror("lamp_w %02x\n",data);
151	155	//logerror("[%d]= %02x\n",4+offset/4,data);
152	156	}
153	157
154		static WRITE8_HANDLER(lamp7_w)
	158	WRITE8_MEMBER(peyper_state::lamp7_w)
155	159	{
156	160	//logerror("[7]= %02x\n",data);
157	161	}
158	162
159		static WRITE8_HANDLER(sol_w)
	163	WRITE8_MEMBER(peyper_state::sol_w)
160	164	{
161	165	//logerror("sol_w %02x\n",data);
162	166	}
r14845	r14846
190	194	//  AM_RANGE(0x0000, 0xffff) AM_NOP
191	195	ADDRESS_MAP_UNMAP_HIGH
192	196	ADDRESS_MAP_GLOBAL_MASK(0xff)
193		AM_RANGE(0x00, 0x00) AM_READWRITE_LEGACY(sw_r,disp_w)
194		AM_RANGE(0x01, 0x01) AM_WRITE_LEGACY(col_w)
	197	AM_RANGE(0x00, 0x00) AM_READWRITE(sw_r,disp_w)
	198	AM_RANGE(0x01, 0x01) AM_WRITE(col_w)
195	199	//  AM_RANGE(0x04, 0x04) AM_DEVWRITE_LEGACY("ay8910_0", ay8910_address_w)
196	200	//  AM_RANGE(0x06, 0x06) AM_DEVWRITE_LEGACY("ay8910_0", ay8910_data_w)
197	201	//  AM_RANGE(0x08, 0x08) AM_DEVWRITE_LEGACY("ay8910_1", ay8910_address_w)
198	202	//  AM_RANGE(0x0a, 0x0a) AM_DEVWRITE_LEGACY("ay8910_1", ay8910_data_w)
199		AM_RANGE(0x0c, 0x0c) AM_WRITE_LEGACY(sol_w)
200		AM_RANGE(0x10, 0x18) AM_WRITE_LEGACY(lamp_w)
	203	AM_RANGE(0x0c, 0x0c) AM_WRITE(sol_w)
	204	AM_RANGE(0x10, 0x18) AM_WRITE(lamp_w)
201	205	AM_RANGE(0x20, 0x20) AM_READ_PORT("DSW0")
202	206	AM_RANGE(0x24, 0x24) AM_READ_PORT("DSW1")
203	207	AM_RANGE(0x28, 0x28) AM_READ_PORT("SYSTEM")
204		AM_RANGE(0x2c, 0x2c) AM_WRITE_LEGACY(lamp7_w)
	208	AM_RANGE(0x2c, 0x2c) AM_WRITE(lamp7_w)
205	209	ADDRESS_MAP_END
206	210
207	211	static INPUT_PORTS_START( pbsonic_generic )

src/mame/drivers/tourvis.c

r14845	r14846
193	193	tourvision_state(const machine_config &mconfig, device_type type, const char *tag)
194	194	: driver_device(mconfig, type, tag) { }
195	195
	196	DECLARE_WRITE8_MEMBER(tourvision_8085_d000_w);
196	197	};
197	198
198	199
r14845	r14846
287	288	AM_RANGE( 0x00, 0x03) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w )
288	289	ADDRESS_MAP_END
289	290
290		static WRITE8_HANDLER( tourvision_8085_d000_w )
	291	WRITE8_MEMBER(tourvision_state::tourvision_8085_d000_w)
291	292	{
292	293	//logerror( "D000 (8085) write %02x\n", data );
293	294	}
r14845	r14846
300	301	AM_RANGE(0xa000, 0xa000) AM_READ_PORT("DSW2")
301	302	AM_RANGE(0xb000, 0xb000) AM_READNOP // unknown (must NOT be == 0x03 ? code at 0x1154)
302	303	AM_RANGE(0xc000, 0xc000) AM_READ_PORT("SYSTEM")
303		AM_RANGE(0xd000, 0xd000) AM_WRITE_LEGACY(tourvision_8085_d000_w )
	304	AM_RANGE(0xd000, 0xd000) AM_WRITE(tourvision_8085_d000_w )
304	305	AM_RANGE(0xe000, 0xe1ff) AM_RAM
305	306	AM_RANGE(0xf000, 0xf000) AM_READNOP // protection or internal counter ? there is sometimes some data in BIOS0 which is replaced by 0xff in BIOS1
306	307	ADDRESS_MAP_END

src/mame/drivers/enigma2.c

r14845	r14846
78	78	/* devices */
79	79	device_t *m_maincpu;
80	80	device_t *m_audiocpu;
	81	DECLARE_READ8_MEMBER(dip_switch_r);
	82	DECLARE_WRITE8_MEMBER(sound_data_w);
	83	DECLARE_WRITE8_MEMBER(enigma2_flip_screen_w);
81	84	};
82	85
83	86
r14845	r14846
346	349
347	350
348	351
349		static READ8_HANDLER( dip_switch_r )
	352	READ8_MEMBER(enigma2_state::dip_switch_r)
350	353	{
351		enigma2_state *state = space->machine().driver_data<enigma2_state>();
352	354	UINT8 ret = 0x00;
353	355
354		if (LOG_PROT) logerror("DIP SW Read: %x at %x (prot data %x)\n", offset, cpu_get_pc(&space->device()), state->m_protection_data);
	356	if (LOG_PROT) logerror("DIP SW Read: %x at %x (prot data %x)\n", offset, cpu_get_pc(&space.device()), m_protection_data);
355	357	switch (offset)
356	358	{
357	359	case 0x01:
358	360	/* For the DIP switches to be read, protection_data must be
359	361	0xff on reset. The AY8910 reset ensures this. */
360		if (state->m_protection_data != 0xff)
361		ret = state->m_protection_data ^ 0x88;
	362	if (m_protection_data != 0xff)
	363	ret = m_protection_data ^ 0x88;
362	364	else
363		ret = input_port_read(space->machine(), "DSW");
	365	ret = input_port_read(machine(), "DSW");
364	366	break;
365	367
366	368	case 0x02:
367		if (cpu_get_pc(&space->device()) == 0x07e5)
	369	if (cpu_get_pc(&space.device()) == 0x07e5)
368	370	ret = 0xaa;
369	371	else
370	372	ret = 0xf4;
r14845	r14846
379	381	}
380	382
381	383
382		static WRITE8_HANDLER( sound_data_w )
	384	WRITE8_MEMBER(enigma2_state::sound_data_w)
383	385	{
384		enigma2_state *state = space->machine().driver_data<enigma2_state>();
385	386	/* clock sound latch shift register on rising edge of D2 */
386		if (!(data & 0x04) && (state->m_last_sound_data & 0x04))
387		state->m_sound_latch = (state->m_sound_latch << 1) | (~data & 0x01);
	387	if (!(data & 0x04) && (m_last_sound_data & 0x04))
	388	m_sound_latch = (m_sound_latch << 1) | (~data & 0x01);
388	389
389		device_set_input_line(state->m_audiocpu, INPUT_LINE_NMI, (data & 0x02) ? ASSERT_LINE : CLEAR_LINE);
	390	device_set_input_line(m_audiocpu, INPUT_LINE_NMI, (data & 0x02) ? ASSERT_LINE : CLEAR_LINE);
390	391
391		state->m_last_sound_data = data;
	392	m_last_sound_data = data;
392	393	}
393	394
394	395
r14845	r14846
407	408	}
408	409
409	410
410		static WRITE8_HANDLER( enigma2_flip_screen_w )
	411	WRITE8_MEMBER(enigma2_state::enigma2_flip_screen_w)
411	412	{
412		enigma2_state *state = space->machine().driver_data<enigma2_state>();
413		state->m_flip_screen = ((data >> 5) & 0x01) && ((input_port_read(space->machine(), "DSW") & 0x20) == 0x20);
	413	m_flip_screen = ((data >> 5) & 0x01) && ((input_port_read(machine(), "DSW") & 0x20) == 0x20);
414	414	}
415	415
416	416
r14845	r14846
448	448	AM_RANGE(0x0000, 0x1fff) AM_ROM AM_WRITENOP
449	449	AM_RANGE(0x2000, 0x3fff) AM_MIRROR(0x4000) AM_RAM AM_BASE(m_videoram)
450	450	AM_RANGE(0x4000, 0x4fff) AM_ROM AM_WRITENOP
451		AM_RANGE(0x5000, 0x57ff) AM_READ_LEGACY(dip_switch_r) AM_WRITENOP
	451	AM_RANGE(0x5000, 0x57ff) AM_READ(dip_switch_r) AM_WRITENOP
452	452	AM_RANGE(0x5800, 0x5800) AM_MIRROR(0x07f8) AM_NOP
453	453	AM_RANGE(0x5801, 0x5801) AM_MIRROR(0x07f8) AM_READ_PORT("IN0") AM_WRITENOP
454	454	AM_RANGE(0x5802, 0x5802) AM_MIRROR(0x07f8) AM_READ_PORT("IN1") AM_WRITENOP
455		AM_RANGE(0x5803, 0x5803) AM_MIRROR(0x07f8) AM_READNOP AM_WRITE_LEGACY(sound_data_w)
	455	AM_RANGE(0x5803, 0x5803) AM_MIRROR(0x07f8) AM_READNOP AM_WRITE(sound_data_w)
456	456	AM_RANGE(0x5804, 0x5804) AM_MIRROR(0x07f8) AM_NOP
457		AM_RANGE(0x5805, 0x5805) AM_MIRROR(0x07f8) AM_READNOP AM_WRITE_LEGACY(enigma2_flip_screen_w)
	457	AM_RANGE(0x5805, 0x5805) AM_MIRROR(0x07f8) AM_READNOP AM_WRITE(enigma2_flip_screen_w)
458	458	AM_RANGE(0x5806, 0x5807) AM_MIRROR(0x07f8) AM_NOP
459	459	ADDRESS_MAP_END
460	460
r14845	r14846
463	463	AM_RANGE(0x0000, 0x1fff) AM_ROM AM_WRITENOP
464	464	AM_RANGE(0x2000, 0x3fff) AM_MIRROR(0x4000) AM_RAM AM_BASE(m_videoram)
465	465	AM_RANGE(0x4000, 0x4fff) AM_ROM AM_WRITENOP
466		AM_RANGE(0x5000, 0x57ff) AM_READ_LEGACY(dip_switch_r) AM_WRITENOP
	466	AM_RANGE(0x5000, 0x57ff) AM_READ(dip_switch_r) AM_WRITENOP
467	467	AM_RANGE(0x5800, 0x5fff) AM_NOP
468	468	ADDRESS_MAP_END
469	469
r14845	r14846
473	473	AM_RANGE(0x00, 0x00) AM_NOP
474	474	AM_RANGE(0x01, 0x01) AM_READ_PORT("IN0") AM_WRITENOP
475	475	AM_RANGE(0x02, 0x02) AM_READ_PORT("IN1") AM_WRITENOP
476		AM_RANGE(0x03, 0x03) AM_READNOP AM_WRITE_LEGACY(sound_data_w)
	476	AM_RANGE(0x03, 0x03) AM_READNOP AM_WRITE(sound_data_w)
477	477	AM_RANGE(0x04, 0x04) AM_NOP
478		AM_RANGE(0x05, 0x05) AM_READNOP AM_WRITE_LEGACY(enigma2_flip_screen_w)
	478	AM_RANGE(0x05, 0x05) AM_READNOP AM_WRITE(enigma2_flip_screen_w)
479	479	AM_RANGE(0x06, 0x07) AM_NOP
480	480	ADDRESS_MAP_END
481	481

src/mame/drivers/videopkr.c

r14845	r14846
336	336	UINT8 m_sbp2;
337	337	UINT8 m_sbp3;
338	338	tilemap_t *m_bg_tilemap;
	339	DECLARE_READ8_MEMBER(videopkr_io_r);
	340	DECLARE_WRITE8_MEMBER(videopkr_io_w);
	341	DECLARE_READ8_MEMBER(videopkr_p1_data_r);
	342	DECLARE_READ8_MEMBER(videopkr_p2_data_r);
	343	DECLARE_WRITE8_MEMBER(videopkr_p1_data_w);
	344	DECLARE_WRITE8_MEMBER(videopkr_p2_data_w);
	345	DECLARE_READ8_MEMBER(videopkr_t0_latch);
	346	DECLARE_WRITE8_MEMBER(prog_w);
	347	DECLARE_READ8_MEMBER(sound_io_r);
	348	DECLARE_WRITE8_MEMBER(sound_io_w);
	349	DECLARE_READ8_MEMBER(sound_p2_r);
	350	DECLARE_WRITE8_MEMBER(sound_p2_w);
	351	DECLARE_READ8_MEMBER(baby_sound_p0_r);
	352	DECLARE_WRITE8_MEMBER(baby_sound_p0_w);
	353	DECLARE_READ8_MEMBER(baby_sound_p1_r);
	354	DECLARE_WRITE8_MEMBER(baby_sound_p1_w);
	355	DECLARE_READ8_MEMBER(baby_sound_p2_r);
339	356	};
340	357
341	358
r14845	r14846
506	523	*      R/W Handlers      *
507	524	*************************/
508	525
509		static READ8_HANDLER( videopkr_io_r )
	526	READ8_MEMBER(videopkr_state::videopkr_io_r)
510	527	{
511		videopkr_state *state = space->machine().driver_data<videopkr_state>();
512	528	UINT8 valor = 0, hf, co;
513	529
514	530	UINT16 kbdin;
515	531
516		switch (state->m_p2)
	532	switch (m_p2)
517	533	{
518	534	case 0xef:   /* inputs are multiplexed through a diode matrix */
519	535	{
520		hf = ((input_port_read(space->machine(), "IN1") & 0x10 ) >> 4) & 1;         /* Hopper full detection */
521		co = 0x10 * ((input_port_read(space->machine(), "IN1") & 0x20 ) >> 5);      /* Coin Out detection */
522		kbdin = ((input_port_read(space->machine(), "IN1") & 0xaf ) << 8) + input_port_read(space->machine(), "IN0");
	536	hf = ((input_port_read(machine(), "IN1") & 0x10 ) >> 4) & 1;         /* Hopper full detection */
	537	co = 0x10 * ((input_port_read(machine(), "IN1") & 0x20 ) >> 5);      /* Coin Out detection */
	538	kbdin = ((input_port_read(machine(), "IN1") & 0xaf ) << 8) + input_port_read(machine(), "IN0");
523	539
524	540	switch (kbdin)
525	541	{
r14845	r14846
551	567
552	568	case 0xdf:
553	569	{
554		state->m_n_offs = ((state->m_p1 & 0xc0) << 2 ) + offset;
555		valor = state->m_data_ram[offset];
	570	m_n_offs = ((m_p1 & 0xc0) << 2 ) + offset;
	571	valor = m_data_ram[offset];
556	572	break;
557	573	}
558	574
559	575	case 0x5f:
560	576	{
561		state->m_n_offs = ((state->m_p1 & 0xc0) << 2 ) + offset;
562		valor = state->m_data_ram[offset];
	577	m_n_offs = ((m_p1 & 0xc0) << 2 ) + offset;
	578	valor = m_data_ram[offset];
563	579	break;
564	580	}
565	581
r14845	r14846
568	584	case 0x7e:
569	585	case 0x7f:
570	586	{
571		state->m_n_offs = ((state->m_p1 & 0xc0) << 2 ) + offset;
572		valor = state->m_color_ram[state->m_n_offs];
	587	m_n_offs = ((m_p1 & 0xc0) << 2 ) + offset;
	588	valor = m_color_ram[m_n_offs];
573	589	break;
574	590	}
575	591
r14845	r14846
578	594	case 0xbe:
579	595	case 0xbf:
580	596	{
581		state->m_n_offs = ((state->m_p1 & 0xc0) << 2 ) + offset;
582		valor = state->m_video_ram[state->m_n_offs];
	597	m_n_offs = ((m_p1 & 0xc0) << 2 ) + offset;
	598	valor = m_video_ram[m_n_offs];
583	599	break;
584	600	}
585	601	}
r14845	r14846
587	603	return valor;
588	604	}
589	605
590		static WRITE8_HANDLER( videopkr_io_w )
	606	WRITE8_MEMBER(videopkr_state::videopkr_io_w)
591	607	{
592		videopkr_state *state = space->machine().driver_data<videopkr_state>();
593		switch (state->m_p2)
	608	switch (m_p2)
594	609	{
595	610	case 0x3c:
596	611	case 0x3d:
597	612	case 0x3e:
598	613	case 0x3f:
599	614	{
600		state->m_n_offs = ((state->m_p1 & 0xc0) << 2 ) + offset;
601		state->m_color_ram[state->m_n_offs] = data & 0x0f;
602		state->m_video_ram[state->m_n_offs] = data;
603		state->m_bg_tilemap->mark_tile_dirty(state->m_n_offs);
	615	m_n_offs = ((m_p1 & 0xc0) << 2 ) + offset;
	616	m_color_ram[m_n_offs] = data & 0x0f;
	617	m_video_ram[m_n_offs] = data;
	618	m_bg_tilemap->mark_tile_dirty(m_n_offs);
604	619	break;
605	620	}
606	621
607	622	case 0xdf:
608	623	{
609		state->m_data_ram[offset] = (data & 0x0f) + 0xf0;
	624	m_data_ram[offset] = (data & 0x0f) + 0xf0;
610	625	break;
611	626	}
612	627
r14845	r14846
615	630	case 0x7e:
616	631	case 0x7f:
617	632	{
618		state->m_n_offs = ((state->m_p1 & 0xc0) << 2 ) + offset;
619		state->m_color_ram[state->m_n_offs] = data & 0x0f;
620		state->m_bg_tilemap->mark_tile_dirty(state->m_n_offs);
	633	m_n_offs = ((m_p1 & 0xc0) << 2 ) + offset;
	634	m_color_ram[m_n_offs] = data & 0x0f;
	635	m_bg_tilemap->mark_tile_dirty(m_n_offs);
621	636	break;
622	637	}
623	638
r14845	r14846
626	641	case 0xbe:
627	642	case 0xbf:
628	643	{
629		state->m_n_offs = ((state->m_p1 & 0xc0) << 2 ) + offset;
630		state->m_video_ram[state->m_n_offs] = data;
631		state->m_bg_tilemap->mark_tile_dirty(state->m_n_offs);
	644	m_n_offs = ((m_p1 & 0xc0) << 2 ) + offset;
	645	m_video_ram[m_n_offs] = data;
	646	m_bg_tilemap->mark_tile_dirty(m_n_offs);
632	647	break;
633	648	}
634	649
r14845	r14846
642	657	output_set_lamp_value(5, ((data >> 5) & 1));   /* Hopper_1 */
643	658	output_set_lamp_value(6, ((data >> 6) & 1));   /* Hopper_2 */
644	659	output_set_lamp_value(7, ((data >> 7) & 1));   /* Diverter */
645		state->m_p24_data = data;
646		state->m_hp_1 = (~state->m_p24_data >> 6) & 1;
647		state->m_hp_2 = (~state->m_p24_data >> 5) & 1;
648		state->m_dvrt = (~state->m_p24_data >> 7) & 1;
	660	m_p24_data = data;
	661	m_hp_1 = (~m_p24_data >> 6) & 1;
	662	m_hp_2 = (~m_p24_data >> 5) & 1;
	663	m_dvrt = (~m_p24_data >> 7) & 1;
649	664	break;
650	665	}
651	666
652	667	case 0xff:
653	668	{
654		state->m_t0_latch = state->m_t0_latch ^ 0x01;      /* fix the bookkeeping mode */
	669	m_t0_latch = m_t0_latch ^ 0x01;      /* fix the bookkeeping mode */
655	670	break;
656	671	}
657	672	}
658	673	}
659	674
660		static READ8_HANDLER( videopkr_p1_data_r )
	675	READ8_MEMBER(videopkr_state::videopkr_p1_data_r)
661	676	{
662		videopkr_state *state = space->machine().driver_data<videopkr_state>();
663		return state->m_p1;
	677	return m_p1;
664	678	}
665	679
666		static READ8_HANDLER( videopkr_p2_data_r )
	680	READ8_MEMBER(videopkr_state::videopkr_p2_data_r)
667	681	{
668		videopkr_state *state = space->machine().driver_data<videopkr_state>();
669		return state->m_p2;
	682	return m_p2;
670	683	}
671	684
672		static WRITE8_HANDLER( videopkr_p1_data_w )
	685	WRITE8_MEMBER(videopkr_state::videopkr_p1_data_w)
673	686	{
674		videopkr_state *state = space->machine().driver_data<videopkr_state>();
675		state->m_p1 = data;
	687	m_p1 = data;
676	688
677	689	output_set_lamp_value(8, (data & 1));         /* Aux_0 - Jackpot mech. counter (Baby Games)*/
678	690	output_set_lamp_value(9, ((data >> 1) & 1));   /* Aux_1 - */
r14845	r14846
681	693	output_set_lamp_value(12, ((data >> 4) & 1));   /* Aux_4 - Bell */
682	694	output_set_lamp_value(13, ((data >> 5) & 1));   /* Aux_5 - /CIO */
683	695
684		state->m_jckp = state->m_p1 & 1;
	696	m_jckp = m_p1 & 1;
685	697
686		if ((~state->m_c_io & 1) & state->m_ant_cio & state->m_hp_1 & state->m_hp_2)
	698	if ((~m_c_io & 1) & m_ant_cio & m_hp_1 & m_hp_2)
687	699	{
688		++state->m_count1;   /* Decoded Coin In Mech. Counter*/
	700	++m_count1;   /* Decoded Coin In Mech. Counter*/
689	701	}
690	702
691		if ((~state->m_c_io & 1) & state->m_ant_cio & (~state->m_hp_1 & 1) & (~state->m_hp_2 & 1))
	703	if ((~m_c_io & 1) & m_ant_cio & (~m_hp_1 & 1) & (~m_hp_2 & 1))
692	704	{
693		++state->m_count2;   /* Decoded Coind Out Mech. Counter */
	705	++m_count2;   /* Decoded Coind Out Mech. Counter */
694	706	}
695	707
696		if (~state->m_c_io & state->m_ant_cio & state->m_hp_1 & state->m_hp_2 & ~state->m_dvrt)
	708	if (~m_c_io & m_ant_cio & m_hp_1 & m_hp_2 & ~m_dvrt)
697	709	{
698		++state->m_count3;   /* Decoded Coin to Drop Mech. Counter */
	710	++m_count3;   /* Decoded Coin to Drop Mech. Counter */
699	711	}
700	712
701		if (~state->m_jckp & state->m_ant_jckp)
	713	if (~m_jckp & m_ant_jckp)
702	714	{
703		++state->m_count4;   /* Decoded Jackpot Mech. Counter */
	715	++m_count4;   /* Decoded Jackpot Mech. Counter */
704	716	}
705	717
706		count_7dig(state->m_count1, 0);
707		count_7dig(state->m_count2, 7);
708		count_7dig(state->m_count3, 14);
709		count_7dig(state->m_count4, 21);
	718	count_7dig(m_count1, 0);
	719	count_7dig(m_count2, 7);
	720	count_7dig(m_count3, 14);
	721	count_7dig(m_count4, 21);
710	722
711		state->m_ant_cio = state->m_c_io;
712		state->m_ant_jckp = state->m_jckp;
	723	m_ant_cio = m_c_io;
	724	m_ant_jckp = m_jckp;
713	725	}
714	726
715		static WRITE8_HANDLER( videopkr_p2_data_w )
	727	WRITE8_MEMBER(videopkr_state::videopkr_p2_data_w)
716	728	{
717		videopkr_state *state = space->machine().driver_data<videopkr_state>();
718		state->m_p2 = data;
	729	m_p2 = data;
719	730	}
720	731
721		static READ8_HANDLER( videopkr_t0_latch )
	732	READ8_MEMBER(videopkr_state::videopkr_t0_latch)
722	733	{
723		videopkr_state *state = space->machine().driver_data<videopkr_state>();
724		return state->m_t0_latch;
	734	return m_t0_latch;
725	735	}
726	736
727		static WRITE8_HANDLER( prog_w )
	737	WRITE8_MEMBER(videopkr_state::prog_w)
728	738	{
729	739	if (!data)
730		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);   /* clear interrupt FF */
	740	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);   /* clear interrupt FF */
731	741	}
732	742
733	743	/*************************
r14845	r14846
766	776
767	777	*/
768	778
769		static READ8_HANDLER(sound_io_r)
	779	READ8_MEMBER(videopkr_state::sound_io_r)
770	780	{
771		videopkr_state *state = space->machine().driver_data<videopkr_state>();
772		switch (state->m_vp_sound_p2)
	781	switch (m_vp_sound_p2)
773	782	{
774	783	case 0xbf:
775	784	{
776		state->m_c_io = (state->m_p1 >> 5) & 1;
777		state->m_hp_1 = (~state->m_p24_data >> 6) & 1;
778		state->m_hp_2 = (~state->m_p24_data >> 5) & 1;
779		state->m_bell = (state->m_p1 >> 4) & 1;
780		state->m_aux3 = (state->m_p1 >> 3) & 1;
781		state->m_dvrt = (~state->m_p24_data >> 7) & 1;
782		state->m_sound_ant = state->m_sound_latch;
783		state->m_sound_latch = state->m_c_io + (state->m_hp_1 << 1) + (state->m_hp_2 << 2) + (state->m_bell << 3) + 0xf0;
	785	m_c_io = (m_p1 >> 5) & 1;
	786	m_hp_1 = (~m_p24_data >> 6) & 1;
	787	m_hp_2 = (~m_p24_data >> 5) & 1;
	788	m_bell = (m_p1 >> 4) & 1;
	789	m_aux3 = (m_p1 >> 3) & 1;
	790	m_dvrt = (~m_p24_data >> 7) & 1;
	791	m_sound_ant = m_sound_latch;
	792	m_sound_latch = m_c_io + (m_hp_1 << 1) + (m_hp_2 << 2) + (m_bell << 3) + 0xf0;
784	793
785	794	break;
786	795	}
787	796	}
788	797
789		return state->m_sound_latch;
	798	return m_sound_latch;
790	799	}
791	800
792		static WRITE8_HANDLER(sound_io_w)
	801	WRITE8_MEMBER(videopkr_state::sound_io_w)
793	802	{
794		videopkr_state *state = space->machine().driver_data<videopkr_state>();
795		if (state->m_vp_sound_p2 == 0x5f || state->m_vp_sound_p2 == 0xdf)
	803	if (m_vp_sound_p2 == 0x5f || m_vp_sound_p2 == 0xdf)
796	804	{
797		state->m_dc_40103 = data;
798		state->m_dc_4020 = 0;
	805	m_dc_40103 = data;
	806	m_dc_4020 = 0;
799	807	}
800	808	}
801	809
802		static READ8_HANDLER(sound_p2_r)
	810	READ8_MEMBER(videopkr_state::sound_p2_r)
803	811	{
804		videopkr_state *state = space->machine().driver_data<videopkr_state>();
805		return state->m_vp_sound_p2;
	812	return m_vp_sound_p2;
806	813	}
807	814
808		static WRITE8_HANDLER(sound_p2_w)
	815	WRITE8_MEMBER(videopkr_state::sound_p2_w)
809	816	{
810		videopkr_state *state = space->machine().driver_data<videopkr_state>();
811		state->m_vp_sound_p2 = data;
	817	m_vp_sound_p2 = data;
812	818
813	819	switch (data)
814	820	{
815	821	case 0x5f:
816	822	{
817		state->m_te_40103 = 0;   /* p2.7 LOW */
818		state->m_ld_40103 = 0;   /* p2.5 LOW */
	823	m_te_40103 = 0;   /* p2.7 LOW */
	824	m_ld_40103 = 0;   /* p2.5 LOW */
819	825	break;
820	826	}
821	827
822	828	case 0x7f:
823	829	{
824		state->m_te_40103 = 0;
825		state->m_ld_40103 = 1;
	830	m_te_40103 = 0;
	831	m_ld_40103 = 1;
826	832	break;
827	833	}
828	834
829	835	case 0xff:
830	836	{
831		state->m_te_40103 = 1;
832		state->m_ld_40103 = 1;
	837	m_te_40103 = 1;
	838	m_ld_40103 = 1;
833	839	break;
834	840	}
835	841	}
r14845	r14846
838	844
839	845	/* Baby Sound Handlers */
840	846
841		static READ8_HANDLER(baby_sound_p0_r)
	847	READ8_MEMBER(videopkr_state::baby_sound_p0_r)
842	848	{
843		videopkr_state *state = space->machine().driver_data<videopkr_state>();
844		return state->m_sbp0;
	849	return m_sbp0;
845	850	}
846	851
847		static WRITE8_HANDLER(baby_sound_p0_w)
	852	WRITE8_MEMBER(videopkr_state::baby_sound_p0_w)
848	853	{
849		videopkr_state *state = space->machine().driver_data<videopkr_state>();
850		state->m_sbp0 = data;
	854	m_sbp0 = data;
851	855	}
852	856
853		static READ8_HANDLER(baby_sound_p1_r)
	857	READ8_MEMBER(videopkr_state::baby_sound_p1_r)
854	858	{
855		videopkr_state *state = space->machine().driver_data<videopkr_state>();
856		state->m_c_io = (state->m_p1 >> 5) & 1;
857		state->m_hp_1 = (~state->m_p24_data >> 6) & 1;
858		state->m_hp_2 = (~state->m_p24_data >> 5) & 1;
859		state->m_bell = (state->m_p1 >> 4) & 1;
860		state->m_aux3 = (state->m_p1 >> 3) & 1;
861		state->m_baby_latch = state->m_c_io + (state->m_hp_1 << 1) + (state->m_hp_2 << 2) + (state->m_bell << 3) + (state->m_aux3 << 4) + 0xe0;
862		return state->m_baby_latch;
	859	m_c_io = (m_p1 >> 5) & 1;
	860	m_hp_1 = (~m_p24_data >> 6) & 1;
	861	m_hp_2 = (~m_p24_data >> 5) & 1;
	862	m_bell = (m_p1 >> 4) & 1;
	863	m_aux3 = (m_p1 >> 3) & 1;
	864	m_baby_latch = m_c_io + (m_hp_1 << 1) + (m_hp_2 << 2) + (m_bell << 3) + (m_aux3 << 4) + 0xe0;
	865	return m_baby_latch;
863	866	}
864	867
865		static WRITE8_HANDLER(baby_sound_p1_w)
	868	WRITE8_MEMBER(videopkr_state::baby_sound_p1_w)
866	869	{
867		videopkr_state *state = space->machine().driver_data<videopkr_state>();
868		state->m_baby_latch = state->m_baby_latch | data;
	870	m_baby_latch = m_baby_latch | data;
869	871	}
870	872
871		static READ8_HANDLER(baby_sound_p2_r)
	873	READ8_MEMBER(videopkr_state::baby_sound_p2_r)
872	874	{
873		videopkr_state *state = space->machine().driver_data<videopkr_state>();
874		return state->m_sbp2;
	875	return m_sbp2;
875	876	}
876	877
877	878	static WRITE8_DEVICE_HANDLER(baby_sound_p2_w)
r14845	r14846
943	944	ADDRESS_MAP_END
944	945
945	946	static ADDRESS_MAP_START( i8039_io_port, AS_IO, 8, videopkr_state )
946		AM_RANGE(0x00,            0xff           ) AM_READWRITE_LEGACY(videopkr_io_r, videopkr_io_w)
947		AM_RANGE(MCS48_PORT_P1,   MCS48_PORT_P1  ) AM_READWRITE_LEGACY(videopkr_p1_data_r, videopkr_p1_data_w)
948		AM_RANGE(MCS48_PORT_P2,   MCS48_PORT_P2  ) AM_READWRITE_LEGACY(videopkr_p2_data_r, videopkr_p2_data_w)
949		AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_WRITE_LEGACY(prog_w)
950		AM_RANGE(MCS48_PORT_T0,   MCS48_PORT_T0  ) AM_READ_LEGACY(videopkr_t0_latch)
	947	AM_RANGE(0x00,            0xff           ) AM_READWRITE(videopkr_io_r, videopkr_io_w)
	948	AM_RANGE(MCS48_PORT_P1,   MCS48_PORT_P1  ) AM_READWRITE(videopkr_p1_data_r, videopkr_p1_data_w)
	949	AM_RANGE(MCS48_PORT_P2,   MCS48_PORT_P2  ) AM_READWRITE(videopkr_p2_data_r, videopkr_p2_data_w)
	950	AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_WRITE(prog_w)
	951	AM_RANGE(MCS48_PORT_T0,   MCS48_PORT_T0  ) AM_READ(videopkr_t0_latch)
951	952	ADDRESS_MAP_END
952	953
953	954	static ADDRESS_MAP_START( i8039_sound_mem, AS_PROGRAM, 8, videopkr_state )
r14845	r14846
955	956	ADDRESS_MAP_END
956	957
957	958	static ADDRESS_MAP_START( i8039_sound_port, AS_IO, 8, videopkr_state )
958		AM_RANGE(0x00         , 0xff         ) AM_READWRITE_LEGACY(sound_io_r, sound_io_w)
	959	AM_RANGE(0x00         , 0xff         ) AM_READWRITE(sound_io_r, sound_io_w)
959	960	AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_DEVWRITE_LEGACY("dac", dac_w)
960		AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_READWRITE_LEGACY(sound_p2_r, sound_p2_w)
	961	AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_READWRITE(sound_p2_r, sound_p2_w)
961	962	ADDRESS_MAP_END
962	963
963	964
r14845	r14846
968	969	static ADDRESS_MAP_START( i8051_sound_port, AS_IO, 8, videopkr_state )
969	970	AM_RANGE(0x0000, 0x1ff) AM_RAM
970	971	/* ports */
971		AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_READWRITE_LEGACY(baby_sound_p0_r, baby_sound_p0_w)
972		AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE_LEGACY(baby_sound_p1_r, baby_sound_p1_w)
973		AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READ_LEGACY(baby_sound_p2_r) AM_DEVWRITE_LEGACY("dac", baby_sound_p2_w)
	972	AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_READWRITE(baby_sound_p0_r, baby_sound_p0_w)
	973	AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(baby_sound_p1_r, baby_sound_p1_w)
	974	AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READ(baby_sound_p2_r) AM_DEVWRITE_LEGACY("dac", baby_sound_p2_w)
974	975	AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_DEVREADWRITE_LEGACY("aysnd", baby_sound_p3_r, baby_sound_p3_w)
975	976	ADDRESS_MAP_END
976	977

src/mame/drivers/igspoker.c

r14845	r14846
91	91	size_t m_protection_res;
92	92
93	93	required_device<cpu_device> m_maincpu;
	94	DECLARE_READ8_MEMBER(igs_irqack_r);
	95	DECLARE_WRITE8_MEMBER(igs_irqack_w);
	96	DECLARE_WRITE8_MEMBER(bg_tile_w);
	97	DECLARE_WRITE8_MEMBER(fg_tile_w);
	98	DECLARE_WRITE8_MEMBER(fg_color_w);
	99	DECLARE_WRITE8_MEMBER(igs_nmi_and_coins_w);
	100	DECLARE_WRITE8_MEMBER(igs_lamps_w);
	101	DECLARE_READ8_MEMBER(custom_io_r);
	102	DECLARE_WRITE8_MEMBER(custom_io_w);
	103	DECLARE_READ8_MEMBER(exp_rom_r);
	104	void show_out();
94	105	};
95	106
96	107
r14845	r14846
119	130	}
120	131
121	132
122		static READ8_HANDLER( igs_irqack_r )
	133	READ8_MEMBER(igspoker_state::igs_irqack_r)
123	134	{
124		igspoker_state *state = space->machine().driver_data<igspoker_state>();
125		device_set_input_line(state->m_maincpu, 0, CLEAR_LINE);
	135	device_set_input_line(m_maincpu, 0, CLEAR_LINE);
126	136	return 0;
127	137	}
128	138
129		static WRITE8_HANDLER( igs_irqack_w )
	139	WRITE8_MEMBER(igspoker_state::igs_irqack_w)
130	140	{
131		//  cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
	141	//  cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
132	142	}
133	143
134	144
r14845	r14846
147	157	SET_TILE_INFO(0, code, tile != 0x1fff ? ((code >> 12) & 0xe) + 1 : 0, 0);
148	158	}
149	159
150		static WRITE8_HANDLER( bg_tile_w )
	160	WRITE8_MEMBER(igspoker_state::bg_tile_w)
151	161	{
152		igspoker_state *state = space->machine().driver_data<igspoker_state>();
153		state->m_bg_tile_ram[offset] = data;
154		state->m_bg_tilemap->mark_tile_dirty(offset);
	162	m_bg_tile_ram[offset] = data;
	163	m_bg_tilemap->mark_tile_dirty(offset);
155	164	}
156	165
157		static WRITE8_HANDLER( fg_tile_w )
	166	WRITE8_MEMBER(igspoker_state::fg_tile_w)
158	167	{
159		igspoker_state *state = space->machine().driver_data<igspoker_state>();
160		state->m_fg_tile_ram[offset] = data;
161		state->m_fg_tilemap->mark_tile_dirty(offset);
	168	m_fg_tile_ram[offset] = data;
	169	m_fg_tilemap->mark_tile_dirty(offset);
162	170	}
163	171
164		static WRITE8_HANDLER( fg_color_w )
	172	WRITE8_MEMBER(igspoker_state::fg_color_w)
165	173	{
166		igspoker_state *state = space->machine().driver_data<igspoker_state>();
167		state->m_fg_color_ram[offset] = data;
168		state->m_fg_tilemap->mark_tile_dirty(offset);
	174	m_fg_color_ram[offset] = data;
	175	m_fg_tilemap->mark_tile_dirty(offset);
169	176	}
170	177
171	178	static VIDEO_START(igs_video)
r14845	r14846
205	212	}
206	213
207	214
208		static void show_out(igspoker_state *state)
	215	void igspoker_state::show_out()
209	216	{
210	217	#ifdef MAME_DEBUG
211		popmessage("%02x %02x", state->m_out[0], state->m_out[1]);
	218	popmessage("%02x %02x", m_out[0], m_out[1]);
212	219	#endif
213	220	}
214	221
215		static WRITE8_HANDLER( igs_nmi_and_coins_w )
	222	WRITE8_MEMBER(igspoker_state::igs_nmi_and_coins_w)
216	223	{
217		igspoker_state *state = space->machine().driver_data<igspoker_state>();
218		coin_counter_w(space->machine(), 0,      data & 0x01);   // coin_a
219		coin_counter_w(space->machine(), 1,      data & 0x04);   // coin_c
220		coin_counter_w(space->machine(), 2,      data & 0x08);   // key in
221		coin_counter_w(space->machine(), 3,      data & 0x10);   // coin state->m_out mech
	224	coin_counter_w(machine(), 0,      data & 0x01);   // coin_a
	225	coin_counter_w(machine(), 1,      data & 0x04);   // coin_c
	226	coin_counter_w(machine(), 2,      data & 0x08);   // key in
	227	coin_counter_w(machine(), 3,      data & 0x10);   // coin m_out mech
222	228
223		set_led_status(space->machine(), 6,      data & 0x20);   // led for coin state->m_out / state->m_hopper active
	229	set_led_status(machine(), 6,      data & 0x20);   // led for coin m_out / m_hopper active
224	230
225		state->m_nmi_enable = data & 0x80;     // nmi enable?
	231	m_nmi_enable = data & 0x80;     // nmi enable?
226	232	#ifdef VERBOSE
227		logerror("PC %06X: NMI change %02x\n",cpu_get_pc(&space->device()),state->m_nmi_enable);
	233	logerror("PC %06X: NMI change %02x\n",cpu_get_pc(&space.device()),m_nmi_enable);
228	234	#endif
229	235
230		state->m_out[0] = data;
231		show_out(state);
	236	m_out[0] = data;
	237	show_out();
232	238	}
233	239
234		static WRITE8_HANDLER( igs_lamps_w )
	240	WRITE8_MEMBER(igspoker_state::igs_lamps_w)
235	241	{
236		igspoker_state *state = space->machine().driver_data<igspoker_state>();
237	242	/*
238	243	- Lbits -
239	244	7654 3210
r14845	r14846
266	271	output_set_lamp_value(5, (data >> 2) & 1);      /* Lamp 5 - HOLD 5 */
267	272	output_set_lamp_value(6, (data & 1));         /* Lamp 6 - START */
268	273
269		state->m_hopper         =   (~data)& 0x80;
	274	m_hopper         =   (~data)& 0x80;
270	275
271		state->m_out[1] = data;
272		show_out(state);
	276	m_out[1] = data;
	277	show_out();
273	278	}
274	279
275	280
276	281
277		static READ8_HANDLER( custom_io_r )
	282	READ8_MEMBER(igspoker_state::custom_io_r)
278	283	{
279		igspoker_state *state = space->machine().driver_data<igspoker_state>();
280	284	#ifdef VERBOSE
281		logerror("PC %06X: Protection read %02x\n",cpu_get_pc(&space->device()), (int) state->m_protection_res);
	285	logerror("PC %06X: Protection read %02x\n",cpu_get_pc(&space.device()), (int) m_protection_res);
282	286	#endif
283		return state->m_protection_res;
	287	return m_protection_res;
284	288	}
285	289
286		static WRITE8_HANDLER( custom_io_w )
	290	WRITE8_MEMBER(igspoker_state::custom_io_w)
287	291	{
288		igspoker_state *state = space->machine().driver_data<igspoker_state>();
289	292	#ifdef VERBOSE
290		logerror("PC %06X: Protection write %02x\n",cpu_get_pc(&space->device()),data);
	293	logerror("PC %06X: Protection write %02x\n",cpu_get_pc(&space.device()),data);
291	294	#endif
292	295
293	296	switch (data)
294	297	{
295		case 0x00: state->m_protection_res = input_port_read(space->machine(), "BUTTONS1"); break;
	298	case 0x00: m_protection_res = input_port_read(machine(), "BUTTONS1"); break;
296	299	// CSK227
297		case 0x20: state->m_protection_res = 0x49; break;
298		case 0x21: state->m_protection_res = 0x47; break;
299		case 0x22: state->m_protection_res = 0x53; break;
300		case 0x24: state->m_protection_res = 0x41; break;
301		case 0x25: state->m_protection_res = 0x41; break;
302		case 0x26: state->m_protection_res = 0x7f; break;
303		case 0x27: state->m_protection_res = 0x41; break;
304		case 0x28: state->m_protection_res = 0x41; break;
305		case 0x2a: state->m_protection_res = 0x3e; break;
306		case 0x2b: state->m_protection_res = 0x41; break;
	300	case 0x20: m_protection_res = 0x49; break;
	301	case 0x21: m_protection_res = 0x47; break;
	302	case 0x22: m_protection_res = 0x53; break;
	303	case 0x24: m_protection_res = 0x41; break;
	304	case 0x25: m_protection_res = 0x41; break;
	305	case 0x26: m_protection_res = 0x7f; break;
	306	case 0x27: m_protection_res = 0x41; break;
	307	case 0x28: m_protection_res = 0x41; break;
	308	case 0x2a: m_protection_res = 0x3e; break;
	309	case 0x2b: m_protection_res = 0x41; break;
307	310	// CSK227 and NUMBER10
308		case 0x2c: state->m_protection_res = 0x49; break;
309		case 0x2d: state->m_protection_res = 0xf9; break;
310		case 0x2e: state->m_protection_res = 0x0a; break;
311		case 0x30: state->m_protection_res = 0x26; break;
312		case 0x31: state->m_protection_res = 0x49; break;
313		case 0x32: state->m_protection_res = 0x49; break;
314		case 0x33: state->m_protection_res = 0x49; break;
315		case 0x34: state->m_protection_res = 0x32; break;
	311	case 0x2c: m_protection_res = 0x49; break;
	312	case 0x2d: m_protection_res = 0xf9; break;
	313	case 0x2e: m_protection_res = 0x0a; break;
	314	case 0x30: m_protection_res = 0x26; break;
	315	case 0x31: m_protection_res = 0x49; break;
	316	case 0x32: m_protection_res = 0x49; break;
	317	case 0x33: m_protection_res = 0x49; break;
	318	case 0x34: m_protection_res = 0x32; break;
316	319	// NUMBER10
317		case 0x60: state->m_protection_res = 0x30; break;
318		case 0x61: state->m_protection_res = 0x31; break;
319		case 0x62: state->m_protection_res = 0x3e; break;
320		case 0x64: state->m_protection_res = 0x3c; break;
321		case 0x65: state->m_protection_res = 0x31; break;
322		case 0x66: state->m_protection_res = 0x39; break;
323		case 0x67: state->m_protection_res = 0x33; break;
324		case 0x68: state->m_protection_res = 0x35; break;
325		case 0x6a: state->m_protection_res = 0x40; break;
326		case 0x6b: state->m_protection_res = 0x43; break;
	320	case 0x60: m_protection_res = 0x30; break;
	321	case 0x61: m_protection_res = 0x31; break;
	322	case 0x62: m_protection_res = 0x3e; break;
	323	case 0x64: m_protection_res = 0x3c; break;
	324	case 0x65: m_protection_res = 0x31; break;
	325	case 0x66: m_protection_res = 0x39; break;
	326	case 0x67: m_protection_res = 0x33; break;
	327	case 0x68: m_protection_res = 0x35; break;
	328	case 0x6a: m_protection_res = 0x40; break;
	329	case 0x6b: m_protection_res = 0x43; break;
327	330	default:
328		state->m_protection_res = data;
	331	m_protection_res = data;
329	332	}
330	333	}
331	334
r14845	r14846
336	339	return field.machine().input().code_pressed(KEYCODE_H);
337	340	}
338	341
339		static READ8_HANDLER( exp_rom_r )
	342	READ8_MEMBER(igspoker_state::exp_rom_r)
340	343	{
341		UINT8 *rom = space->machine().region("maincpu")->base();
	344	UINT8 *rom = machine().region("maincpu")->base();
342	345	return rom[offset+0x10000];
343	346	}
344	347
r14845	r14846
355	358	AM_RANGE(0x4002, 0x4002) AM_READ_PORT("DSW3")         /* DSW3 */
356	359	AM_RANGE(0x4003, 0x4003) AM_READ_PORT("DSW4")         /* DSW4 */
357	360	AM_RANGE(0x4004, 0x4004) AM_READ_PORT("DSW5")         /* DSW5 */
358		AM_RANGE(0x5080, 0x5080) AM_WRITE_LEGACY(igs_nmi_and_coins_w)
	361	AM_RANGE(0x5080, 0x5080) AM_WRITE(igs_nmi_and_coins_w)
359	362	AM_RANGE(0x5081, 0x5081) AM_READ_PORT("SERVICE")         /* Services */
360	363	AM_RANGE(0x5082, 0x5082) AM_READ_PORT("COINS")         /* Coing & Kbd */
361		AM_RANGE(0x5090, 0x5090) AM_WRITE_LEGACY(custom_io_w)
362		AM_RANGE(0x5091, 0x5091) AM_READ_LEGACY(custom_io_r) AM_WRITE_LEGACY(igs_lamps_w )         /* Keyboard */
	364	AM_RANGE(0x5090, 0x5090) AM_WRITE(custom_io_w)
	365	AM_RANGE(0x5091, 0x5091) AM_READ(custom_io_r) AM_WRITE(igs_lamps_w )         /* Keyboard */
363	366	AM_RANGE(0x50a0, 0x50a0) AM_READ_PORT("BUTTONS2")         /* Not connected */
364	367	AM_RANGE(0x50b0, 0x50b1) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w)
365		AM_RANGE(0x50c0, 0x50c0) AM_READ_LEGACY(igs_irqack_r) AM_WRITE_LEGACY(igs_irqack_w)
366		AM_RANGE(0x6800, 0x6fff) AM_RAM_WRITE_LEGACY(bg_tile_w )  AM_BASE(m_bg_tile_ram )
367		AM_RANGE(0x7000, 0x77ff) AM_RAM_WRITE_LEGACY(fg_tile_w )  AM_BASE(m_fg_tile_ram )
368		AM_RANGE(0x7800, 0x7fff) AM_RAM_WRITE_LEGACY(fg_color_w ) AM_BASE(m_fg_color_ram )
369		AM_RANGE(0x0000, 0xffff) AM_READ_LEGACY(exp_rom_r )
	368	AM_RANGE(0x50c0, 0x50c0) AM_READ(igs_irqack_r) AM_WRITE(igs_irqack_w)
	369	AM_RANGE(0x6800, 0x6fff) AM_RAM_WRITE(bg_tile_w )  AM_BASE(m_bg_tile_ram )
	370	AM_RANGE(0x7000, 0x77ff) AM_RAM_WRITE(fg_tile_w )  AM_BASE(m_fg_tile_ram )
	371	AM_RANGE(0x7800, 0x7fff) AM_RAM_WRITE(fg_color_w ) AM_BASE(m_fg_color_ram )
	372	AM_RANGE(0x0000, 0xffff) AM_READ(exp_rom_r )
370	373	ADDRESS_MAP_END
371	374
372	375
r14845	r14846
1111	1114	AM_RANGE(0x4004, 0x4004) AM_READ_PORT("DSW5")         /* DSW5 */
1112	1115	AM_RANGE(0x4006, 0x4006) AM_READ_PORT("DSW6")
1113	1116	AM_RANGE(0x4007, 0x4007) AM_READ_PORT("DSW7")
1114		AM_RANGE(0x50f0, 0x50f0) AM_WRITE_LEGACY(igs_nmi_and_coins_w)
	1117	AM_RANGE(0x50f0, 0x50f0) AM_WRITE(igs_nmi_and_coins_w)
1115	1118	AM_RANGE(0x5080, 0x5080) AM_READ_PORT("SERVICE")         /* Services */
1116		AM_RANGE(0x5090, 0x5090) AM_WRITE_LEGACY(custom_io_w)
1117		AM_RANGE(0x5091, 0x5091) AM_READ_LEGACY(custom_io_r) AM_WRITE_LEGACY(igs_lamps_w )         /* Keyboard */
	1119	AM_RANGE(0x5090, 0x5090) AM_WRITE(custom_io_w)
	1120	AM_RANGE(0x5091, 0x5091) AM_READ(custom_io_r) AM_WRITE(igs_lamps_w )         /* Keyboard */
1118	1121	AM_RANGE(0x50a0, 0x50a0) AM_READ_PORT("BUTTONS2")
1119	1122	/* Sound synthesys has been patched out, replaced by ADPCM samples */
1120	1123	AM_RANGE(0x50b0, 0x50b0) AM_DEVREADWRITE("oki", okim6295_device, read, write)
1121		AM_RANGE(0x50c0, 0x50c0) AM_READ_LEGACY(igs_irqack_r) AM_WRITE_LEGACY(igs_irqack_w)
1122		AM_RANGE(0x7000, 0x77ff) AM_RAM_WRITE_LEGACY(fg_tile_w )  AM_BASE(m_fg_tile_ram )
1123		AM_RANGE(0x7800, 0x7fff) AM_RAM_WRITE_LEGACY(fg_color_w ) AM_BASE(m_fg_color_ram )
1124		AM_RANGE(0x0000, 0xffff) AM_READ_LEGACY(exp_rom_r )
	1124	AM_RANGE(0x50c0, 0x50c0) AM_READ(igs_irqack_r) AM_WRITE(igs_irqack_w)
	1125	AM_RANGE(0x7000, 0x77ff) AM_RAM_WRITE(fg_tile_w )  AM_BASE(m_fg_tile_ram )
	1126	AM_RANGE(0x7800, 0x7fff) AM_RAM_WRITE(fg_color_w ) AM_BASE(m_fg_color_ram )
	1127	AM_RANGE(0x0000, 0xffff) AM_READ(exp_rom_r )
1125	1128	ADDRESS_MAP_END
1126	1129
1127	1130	static ADDRESS_MAP_START( cpokerpk_io_map, AS_IO, 8, igspoker_state )
r14845	r14846
1132	1135	AM_RANGE(0x4002, 0x4002) AM_READ_PORT("DSW3")         /* DSW3 */
1133	1136	AM_RANGE(0x4003, 0x4003) AM_READ_PORT("DSW4")         /* DSW4 */
1134	1137	AM_RANGE(0x4004, 0x4004) AM_READ_PORT("DSW5")         /* DSW5 */
1135		AM_RANGE(0x50f0, 0x50f0) AM_WRITE_LEGACY(igs_nmi_and_coins_w)
	1138	AM_RANGE(0x50f0, 0x50f0) AM_WRITE(igs_nmi_and_coins_w)
1136	1139	AM_RANGE(0x5081, 0x5081) AM_READ_PORT("SERVICE")         /* Services */
1137	1140	AM_RANGE(0x5082, 0x5082) AM_READ_PORT("COINS")         /* Coing & Kbd */
1138		AM_RANGE(0x5090, 0x5090) AM_WRITE_LEGACY(custom_io_w)
1139		AM_RANGE(0x5091, 0x5091) AM_READ_LEGACY(custom_io_r) AM_WRITE_LEGACY(igs_lamps_w )         /* Keyboard */
	1141	AM_RANGE(0x5090, 0x5090) AM_WRITE(custom_io_w)
	1142	AM_RANGE(0x5091, 0x5091) AM_READ(custom_io_r) AM_WRITE(igs_lamps_w )         /* Keyboard */
1140	1143	AM_RANGE(0x50a0, 0x50a0) AM_READ_PORT("BUTTONS2")
1141	1144	/* Sound synthesys has been patched out, replaced by ADPCM samples */
1142	1145	AM_RANGE(0x50b0, 0x50b0) AM_DEVREADWRITE("oki", okim6295_device, read, write)
1143		AM_RANGE(0x50c0, 0x50c0) AM_READ_LEGACY(igs_irqack_r) AM_WRITE_LEGACY(igs_irqack_w)
1144		AM_RANGE(0x7000, 0x77ff) AM_RAM_WRITE_LEGACY(fg_tile_w )  AM_BASE(m_fg_tile_ram )
1145		AM_RANGE(0x7800, 0x7fff) AM_RAM_WRITE_LEGACY(fg_color_w ) AM_BASE(m_fg_color_ram )
1146		AM_RANGE(0x0000, 0xffff) AM_READ_LEGACY(exp_rom_r )
	1146	AM_RANGE(0x50c0, 0x50c0) AM_READ(igs_irqack_r) AM_WRITE(igs_irqack_w)
	1147	AM_RANGE(0x7000, 0x77ff) AM_RAM_WRITE(fg_tile_w )  AM_BASE(m_fg_tile_ram )
	1148	AM_RANGE(0x7800, 0x7fff) AM_RAM_WRITE(fg_color_w ) AM_BASE(m_fg_color_ram )
	1149	AM_RANGE(0x0000, 0xffff) AM_READ(exp_rom_r )
1147	1150	ADDRESS_MAP_END
1148	1151
1149	1152	static INPUT_PORTS_START( number10 )

src/mame/drivers/koikoi.c

r14845	r14846
62	62	int m_inputval;
63	63	int m_inputlen;
64	64	int m_ioram[8];
	65	DECLARE_WRITE8_MEMBER(vram_w);
	66	DECLARE_READ8_MEMBER(io_r);
	67	DECLARE_WRITE8_MEMBER(io_w);
65	68	};
66	69
67	70
r14845	r14846
145	148	*
146	149	*************************************/
147	150
148		static WRITE8_HANDLER( vram_w )
	151	WRITE8_MEMBER(koikoi_state::vram_w)
149	152	{
150		koikoi_state *state = space->machine().driver_data<koikoi_state>();
151		state->m_videoram[offset] = data;
152		state->m_tmap->mark_tile_dirty(offset & 0x3ff);
	153	m_videoram[offset] = data;
	154	m_tmap->mark_tile_dirty(offset & 0x3ff);
153	155	}
154	156
155	157	static READ8_DEVICE_HANDLER( input_r )
r14845	r14846
195	197	//xor'ed mux select, player 1 = 1,2,4,8, player 2 = 0x10, 0x20, 0x40, 0x80
196	198	}
197	199
198		static READ8_HANDLER( io_r )
	200	READ8_MEMBER(koikoi_state::io_r)
199	201	{
200		koikoi_state *state = space->machine().driver_data<koikoi_state>();
201	202	if (!offset)
202		return input_port_read(space->machine(), "IN0") ^ state->m_ioram[4]; //coin
	203	return input_port_read(machine(), "IN0") ^ m_ioram[4]; //coin
203	204
204	205	return 0;
205	206	}
206	207
207		static WRITE8_HANDLER( io_w )
	208	WRITE8_MEMBER(koikoi_state::io_w)
208	209	{
209		koikoi_state *state = space->machine().driver_data<koikoi_state>();
210	210	if (offset == 7 && data == 0)
211		state->m_inputcnt = 0; //reset read cycle counter
	211	m_inputcnt = 0; //reset read cycle counter
212	212
213		state->m_ioram[offset] = data;
	213	m_ioram[offset] = data;
214	214	}
215	215
216	216	/*************************************
r14845	r14846
222	222	static ADDRESS_MAP_START( koikoi_map, AS_PROGRAM, 8, koikoi_state )
223	223	AM_RANGE(0x0000, 0x2fff) AM_ROM
224	224	AM_RANGE(0x6000, 0x67ff) AM_RAM
225		AM_RANGE(0x7000, 0x77ff) AM_RAM_WRITE_LEGACY(vram_w) AM_BASE(m_videoram)
	225	AM_RANGE(0x7000, 0x77ff) AM_RAM_WRITE(vram_w) AM_BASE(m_videoram)
226	226	AM_RANGE(0x8000, 0x8000) AM_READ_PORT("DSW")
227		AM_RANGE(0x9000, 0x9007) AM_READWRITE_LEGACY(io_r, io_w)
	227	AM_RANGE(0x9000, 0x9007) AM_READWRITE(io_r, io_w)
228	228	ADDRESS_MAP_END
229	229
230	230	static ADDRESS_MAP_START( koikoi_io_map, AS_IO, 8, koikoi_state )

src/mame/drivers/mil4000.c

r14845	r14846
107	107	tilemap_t *m_sc3_tilemap;
108	108	UINT16 m_vblank;
109	109	UINT16 m_hblank;
	110	DECLARE_READ16_MEMBER(hvretrace_r);
	111	DECLARE_WRITE16_MEMBER(sc0_vram_w);
	112	DECLARE_WRITE16_MEMBER(sc1_vram_w);
	113	DECLARE_WRITE16_MEMBER(sc2_vram_w);
	114	DECLARE_WRITE16_MEMBER(sc3_vram_w);
	115	DECLARE_WRITE16_MEMBER(output_w);
110	116	};
111	117
112	118
r14845	r14846
190	196	}
191	197
192	198	/*TODO*/
193		static READ16_HANDLER( hvretrace_r )
	199	READ16_MEMBER(mil4000_state::hvretrace_r)
194	200	{
195		mil4000_state *state = space->machine().driver_data<mil4000_state>();
196	201	UINT16 res;
197	202
198	203	res = 0;
199	204
200		state->m_vblank^=1;
201		state->m_hblank^=1;
	205	m_vblank^=1;
	206	m_hblank^=1;
202	207
203	208	/*V-Blank*/
204		if (state->m_vblank)
	209	if (m_vblank)
205	210	res|= 0x80;
206	211
207	212	/*H-Blank*/
208		if (state->m_hblank)
	213	if (m_hblank)
209	214	res|= 0x40;
210	215
211	216	return res;
212	217	}
213	218
214	219
215		static WRITE16_HANDLER( sc0_vram_w )
	220	WRITE16_MEMBER(mil4000_state::sc0_vram_w)
216	221	{
217		mil4000_state *state = space->machine().driver_data<mil4000_state>();
218		state->m_sc0_vram[offset] = data;
219		state->m_sc0_tilemap->mark_tile_dirty(offset/2);
	222	m_sc0_vram[offset] = data;
	223	m_sc0_tilemap->mark_tile_dirty(offset/2);
220	224	}
221	225
222		static WRITE16_HANDLER( sc1_vram_w )
	226	WRITE16_MEMBER(mil4000_state::sc1_vram_w)
223	227	{
224		mil4000_state *state = space->machine().driver_data<mil4000_state>();
225		state->m_sc1_vram[offset] = data;
226		state->m_sc1_tilemap->mark_tile_dirty(offset/2);
	228	m_sc1_vram[offset] = data;
	229	m_sc1_tilemap->mark_tile_dirty(offset/2);
227	230	}
228	231
229		static WRITE16_HANDLER( sc2_vram_w )
	232	WRITE16_MEMBER(mil4000_state::sc2_vram_w)
230	233	{
231		mil4000_state *state = space->machine().driver_data<mil4000_state>();
232		state->m_sc2_vram[offset] = data;
233		state->m_sc2_tilemap->mark_tile_dirty(offset/2);
	234	m_sc2_vram[offset] = data;
	235	m_sc2_tilemap->mark_tile_dirty(offset/2);
234	236	}
235	237
236		static WRITE16_HANDLER( sc3_vram_w )
	238	WRITE16_MEMBER(mil4000_state::sc3_vram_w)
237	239	{
238		mil4000_state *state = space->machine().driver_data<mil4000_state>();
239		state->m_sc3_vram[offset] = data;
240		state->m_sc3_tilemap->mark_tile_dirty(offset/2);
	240	m_sc3_vram[offset] = data;
	241	m_sc3_tilemap->mark_tile_dirty(offset/2);
241	242	}
242	243
243	244	/*end of video stuff*/
r14845	r14846
252	253	---- ---- ---- --x- Hold 2
253	254	---- ---- ---- ---x Hold 1
254	255	*/
255		static WRITE16_HANDLER( output_w )
	256	WRITE16_MEMBER(mil4000_state::output_w)
256	257	{
257	258	int i;
258	259
259	260	for(i=0;i<3;i++)
260		coin_counter_w(space->machine(), i, data & 0x2000);
	261	coin_counter_w(machine(), i, data & 0x2000);
261	262
262	263	output_set_lamp_value(0, (data) & 1);      /* HOLD1 */
263	264	output_set_lamp_value(1, (data >> 1) & 1);   /* HOLD2 */
r14845	r14846
272	273
273	274	static ADDRESS_MAP_START( mil4000_map, AS_PROGRAM, 16, mil4000_state )
274	275	AM_RANGE(0x000000, 0x03ffff) AM_ROM
275		AM_RANGE(0x500000, 0x503fff) AM_RAM_WRITE_LEGACY(sc0_vram_w) AM_BASE(m_sc0_vram)   // CY62256L-70, U77
276		AM_RANGE(0x504000, 0x507fff) AM_RAM_WRITE_LEGACY(sc1_vram_w) AM_BASE(m_sc1_vram)   // CY62256L-70, U77
277		AM_RANGE(0x508000, 0x50bfff) AM_RAM_WRITE_LEGACY(sc2_vram_w) AM_BASE(m_sc2_vram)   // CY62256L-70, U78
278		AM_RANGE(0x50c000, 0x50ffff) AM_RAM_WRITE_LEGACY(sc3_vram_w) AM_BASE(m_sc3_vram)   // CY62256L-70, U78
	276	AM_RANGE(0x500000, 0x503fff) AM_RAM_WRITE(sc0_vram_w) AM_BASE(m_sc0_vram)   // CY62256L-70, U77
	277	AM_RANGE(0x504000, 0x507fff) AM_RAM_WRITE(sc1_vram_w) AM_BASE(m_sc1_vram)   // CY62256L-70, U77
	278	AM_RANGE(0x508000, 0x50bfff) AM_RAM_WRITE(sc2_vram_w) AM_BASE(m_sc2_vram)   // CY62256L-70, U78
	279	AM_RANGE(0x50c000, 0x50ffff) AM_RAM_WRITE(sc3_vram_w) AM_BASE(m_sc3_vram)   // CY62256L-70, U78
279	280
280	281	AM_RANGE(0x708000, 0x708001) AM_READ_PORT("IN0")
281	282	AM_RANGE(0x708002, 0x708003) AM_READ_PORT("IN1")
282		AM_RANGE(0x708004, 0x708005) AM_READ_LEGACY(hvretrace_r)
	283	AM_RANGE(0x708004, 0x708005) AM_READ(hvretrace_r)
283	284	AM_RANGE(0x708006, 0x708007) AM_READ_PORT("IN2")
284		AM_RANGE(0x708008, 0x708009) AM_WRITE_LEGACY(output_w)
	285	AM_RANGE(0x708008, 0x708009) AM_WRITE(output_w)
285	286	AM_RANGE(0x708010, 0x708011) AM_NOP //touch screen
286	287	AM_RANGE(0x70801e, 0x70801f) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
287	288

src/mame/drivers/gticlub.c

r14845	r14846
244	244	UINT32 *m_work_ram;
245	245	UINT32 *m_sharc_dataram_0;
246	246	UINT32 *m_sharc_dataram_1;
	247	DECLARE_WRITE32_MEMBER(paletteram32_w);
	248	DECLARE_READ32_MEMBER(gticlub_k001604_tile_r);
	249	DECLARE_WRITE32_MEMBER(gticlub_k001604_tile_w);
	250	DECLARE_READ32_MEMBER(gticlub_k001604_char_r);
	251	DECLARE_WRITE32_MEMBER(gticlub_k001604_char_w);
	252	DECLARE_READ32_MEMBER(gticlub_k001604_reg_r);
	253	DECLARE_WRITE32_MEMBER(gticlub_k001604_reg_w);
	254	DECLARE_READ8_MEMBER(sysreg_r);
	255	DECLARE_WRITE8_MEMBER(sysreg_w);
	256	DECLARE_READ32_MEMBER(dsp_dataram0_r);
	257	DECLARE_WRITE32_MEMBER(dsp_dataram0_w);
	258	DECLARE_READ32_MEMBER(dsp_dataram1_r);
	259	DECLARE_WRITE32_MEMBER(dsp_dataram1_w);
247	260	};
248	261
249	262
250		static WRITE32_HANDLER( paletteram32_w )
	263	WRITE32_MEMBER(gticlub_state::paletteram32_w)
251	264	{
252		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
253		data = space->machine().generic.paletteram.u32[offset];
254		palette_set_color_rgb(space->machine(), offset, pal5bit(data >> 10), pal5bit(data >> 5), pal5bit(data >> 0));
	265	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
	266	data = machine().generic.paletteram.u32[offset];
	267	palette_set_color_rgb(machine(), offset, pal5bit(data >> 10), pal5bit(data >> 5), pal5bit(data >> 0));
255	268	}
256	269
257	270	static void voodoo_vblank_0(device_t *device, int param)
r14845	r14846
264	277	cputag_set_input_line(device->machine(), "maincpu", INPUT_LINE_IRQ1, param ? ASSERT_LINE : CLEAR_LINE);
265	278	}
266	279
267		static READ32_HANDLER( gticlub_k001604_tile_r )
	280	READ32_MEMBER(gticlub_state::gticlub_k001604_tile_r)
268	281	{
269		device_t *k001604 = space->machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
	282	device_t *k001604 = machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
270	283	return k001604_tile_r(k001604, offset, mem_mask);
271	284	}
272	285
273		static WRITE32_HANDLER( gticlub_k001604_tile_w )
	286	WRITE32_MEMBER(gticlub_state::gticlub_k001604_tile_w)
274	287	{
275		device_t *k001604 = space->machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
	288	device_t *k001604 = machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
276	289	k001604_tile_w(k001604, offset, data, mem_mask);
277	290	}
278	291
279	292
280		static READ32_HANDLER( gticlub_k001604_char_r )
	293	READ32_MEMBER(gticlub_state::gticlub_k001604_char_r)
281	294	{
282		device_t *k001604 = space->machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
	295	device_t *k001604 = machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
283	296	return k001604_char_r(k001604, offset, mem_mask);
284	297	}
285	298
286		static WRITE32_HANDLER( gticlub_k001604_char_w )
	299	WRITE32_MEMBER(gticlub_state::gticlub_k001604_char_w)
287	300	{
288		device_t *k001604 = space->machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
	301	device_t *k001604 = machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
289	302	k001604_char_w(k001604, offset, data, mem_mask);
290	303	}
291	304
292		static READ32_HANDLER( gticlub_k001604_reg_r )
	305	READ32_MEMBER(gticlub_state::gticlub_k001604_reg_r)
293	306	{
294		device_t *k001604 = space->machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
	307	device_t *k001604 = machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
295	308	return k001604_reg_r(k001604, offset, mem_mask);
296	309	}
297	310
298		static WRITE32_HANDLER( gticlub_k001604_reg_w )
	311	WRITE32_MEMBER(gticlub_state::gticlub_k001604_reg_w)
299	312	{
300		device_t *k001604 = space->machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
	313	device_t *k001604 = machine().device(get_cgboard_id() ? "k001604_2" : "k001604_1");
301	314	k001604_reg_w(k001604, offset, data, mem_mask);
302	315	}
303	316
r14845	r14846
318	331	0            /* reset_delay */
319	332	};
320	333
321		static READ8_HANDLER( sysreg_r )
	334	READ8_MEMBER(gticlub_state::sysreg_r)
322	335	{
323	336	static const char *const portnames[] = { "IN0", "IN1", "IN2", "IN3" };
324		device_t *adc1038 = space->machine().device("adc1038");
325		eeprom_device *eeprom = space->machine().device<eeprom_device>("eeprom");
	337	device_t *adc1038 = machine().device("adc1038");
	338	eeprom_device *eeprom = machine().device<eeprom_device>("eeprom");
326	339
327	340	switch (offset)
328	341	{
329	342	case 0:
330	343	case 1:
331	344	case 3:
332		return input_port_read(space->machine(), portnames[offset]);
	345	return input_port_read(machine(), portnames[offset]);
333	346
334	347	case 2:
335	348	return adc1038_sars_read(adc1038) << 7;
r14845	r14846
354	367	return 0;
355	368	}
356	369
357		static WRITE8_HANDLER( sysreg_w )
	370	WRITE8_MEMBER(gticlub_state::sysreg_w)
358	371	{
359		device_t *adc1038 = space->machine().device("adc1038");
360		eeprom_device *eeprom = space->machine().device<eeprom_device>("eeprom");
	372	device_t *adc1038 = machine().device("adc1038");
	373	eeprom_device *eeprom = machine().device<eeprom_device>("eeprom");
361	374
362	375	switch (offset)
363	376	{
r14845	r14846
374	387
375	388	case 4:
376	389	if (data & 0x80)   /* CG Board 1 IRQ Ack */
377		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ1, CLEAR_LINE);
	390	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ1, CLEAR_LINE);
378	391
379	392	if (data & 0x40)   /* CG Board 0 IRQ Ack */
380		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
	393	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
381	394
382	395	adc1038_di_write(adc1038, (data >> 0) & 1);
383	396	adc1038_clk_write(adc1038, (data >> 1) & 1);
r14845	r14846
402	415
403	416	static ADDRESS_MAP_START( gticlub_map, AS_PROGRAM, 32, gticlub_state )
404	417	AM_RANGE(0x00000000, 0x000fffff) AM_RAM AM_BASE(m_work_ram)      /* Work RAM */
405		AM_RANGE(0x74000000, 0x740000ff) AM_READWRITE_LEGACY(gticlub_k001604_reg_r, gticlub_k001604_reg_w)
406		AM_RANGE(0x74010000, 0x7401ffff) AM_RAM_WRITE_LEGACY(paletteram32_w) AM_BASE_GENERIC(paletteram)
407		AM_RANGE(0x74020000, 0x7403ffff) AM_READWRITE_LEGACY(gticlub_k001604_tile_r, gticlub_k001604_tile_w)
408		AM_RANGE(0x74040000, 0x7407ffff) AM_READWRITE_LEGACY(gticlub_k001604_char_r, gticlub_k001604_char_w)
	418	AM_RANGE(0x74000000, 0x740000ff) AM_READWRITE(gticlub_k001604_reg_r, gticlub_k001604_reg_w)
	419	AM_RANGE(0x74010000, 0x7401ffff) AM_RAM_WRITE(paletteram32_w) AM_BASE_GENERIC(paletteram)
	420	AM_RANGE(0x74020000, 0x7403ffff) AM_READWRITE(gticlub_k001604_tile_r, gticlub_k001604_tile_w)
	421	AM_RANGE(0x74040000, 0x7407ffff) AM_READWRITE(gticlub_k001604_char_r, gticlub_k001604_char_w)
409	422	AM_RANGE(0x78000000, 0x7800ffff) AM_READWRITE_LEGACY(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc)
410	423	AM_RANGE(0x78040000, 0x7804000f) AM_READWRITE_LEGACY(K001006_0_r, K001006_0_w)
411	424	AM_RANGE(0x78080000, 0x7808000f) AM_READWRITE_LEGACY(K001006_1_r, K001006_1_w)
412	425	AM_RANGE(0x780c0000, 0x780c0003) AM_READWRITE_LEGACY(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc)
413		AM_RANGE(0x7e000000, 0x7e003fff) AM_READWRITE8_LEGACY(sysreg_r, sysreg_w, 0xffffffff)
	426	AM_RANGE(0x7e000000, 0x7e003fff) AM_READWRITE8(sysreg_r, sysreg_w, 0xffffffff)
414	427	AM_RANGE(0x7e008000, 0x7e009fff) AM_DEVREADWRITE8_LEGACY("k056230", k056230_r, k056230_w, 0xffffffff)
415	428	AM_RANGE(0x7e00a000, 0x7e00bfff) AM_DEVREADWRITE_LEGACY("k056230", lanc_ram_r, lanc_ram_w)
416	429	AM_RANGE(0x7e00c000, 0x7e00c007) AM_DEVWRITE_LEGACY("k056800", k056800_host_w)
r14845	r14846
434	447
435	448	/*****************************************************************************/
436	449
437		static READ32_HANDLER( dsp_dataram0_r )
	450	READ32_MEMBER(gticlub_state::dsp_dataram0_r)
438	451	{
439		gticlub_state *state = space->machine().driver_data<gticlub_state>();
440		return state->m_sharc_dataram_0[offset] & 0xffff;
	452	return m_sharc_dataram_0[offset] & 0xffff;
441	453	}
442	454
443		static WRITE32_HANDLER( dsp_dataram0_w )
	455	WRITE32_MEMBER(gticlub_state::dsp_dataram0_w)
444	456	{
445		gticlub_state *state = space->machine().driver_data<gticlub_state>();
446		state->m_sharc_dataram_0[offset] = data;
	457	m_sharc_dataram_0[offset] = data;
447	458	}
448	459
449		static READ32_HANDLER( dsp_dataram1_r )
	460	READ32_MEMBER(gticlub_state::dsp_dataram1_r)
450	461	{
451		gticlub_state *state = space->machine().driver_data<gticlub_state>();
452		return state->m_sharc_dataram_1[offset] & 0xffff;
	462	return m_sharc_dataram_1[offset] & 0xffff;
453	463	}
454	464
455		static WRITE32_HANDLER( dsp_dataram1_w )
	465	WRITE32_MEMBER(gticlub_state::dsp_dataram1_w)
456	466	{
457		gticlub_state *state = space->machine().driver_data<gticlub_state>();
458		state->m_sharc_dataram_1[offset] = data;
	467	m_sharc_dataram_1[offset] = data;
459	468	}
460	469
461	470	static ADDRESS_MAP_START( sharc_map, AS_DATA, 32, gticlub_state )
462	471	AM_RANGE(0x400000, 0x41ffff) AM_READWRITE_LEGACY(cgboard_0_shared_sharc_r, cgboard_0_shared_sharc_w)
463		AM_RANGE(0x500000, 0x5fffff) AM_READWRITE_LEGACY(dsp_dataram0_r, dsp_dataram0_w)
	472	AM_RANGE(0x500000, 0x5fffff) AM_READWRITE(dsp_dataram0_r, dsp_dataram0_w)
464	473	AM_RANGE(0x600000, 0x6fffff) AM_READWRITE_LEGACY(K001005_r, K001005_w)
465	474	AM_RANGE(0x700000, 0x7000ff) AM_READWRITE_LEGACY(cgboard_0_comm_sharc_r, cgboard_0_comm_sharc_w)
466	475	ADDRESS_MAP_END
467	476
468	477	static ADDRESS_MAP_START( hangplt_sharc0_map, AS_DATA, 32, gticlub_state )
469	478	AM_RANGE(0x0400000, 0x041ffff) AM_READWRITE_LEGACY(cgboard_0_shared_sharc_r, cgboard_0_shared_sharc_w)
470		AM_RANGE(0x0500000, 0x05fffff) AM_READWRITE_LEGACY(dsp_dataram0_r, dsp_dataram0_w)
	479	AM_RANGE(0x0500000, 0x05fffff) AM_READWRITE(dsp_dataram0_r, dsp_dataram0_w)
471	480	AM_RANGE(0x1400000, 0x14fffff) AM_RAM
472	481	AM_RANGE(0x2400000, 0x27fffff) AM_DEVREADWRITE_LEGACY("voodoo0", nwk_voodoo_0_r, voodoo_w)
473	482	AM_RANGE(0x3400000, 0x34000ff) AM_READWRITE_LEGACY(cgboard_0_comm_sharc_r, cgboard_0_comm_sharc_w)
r14845	r14846
478	487
479	488	static ADDRESS_MAP_START( hangplt_sharc1_map, AS_DATA, 32, gticlub_state )
480	489	AM_RANGE(0x0400000, 0x041ffff) AM_READWRITE_LEGACY(cgboard_1_shared_sharc_r, cgboard_1_shared_sharc_w)
481		AM_RANGE(0x0500000, 0x05fffff) AM_READWRITE_LEGACY(dsp_dataram1_r, dsp_dataram1_w)
	490	AM_RANGE(0x0500000, 0x05fffff) AM_READWRITE(dsp_dataram1_r, dsp_dataram1_w)
482	491	AM_RANGE(0x1400000, 0x14fffff) AM_RAM
483	492	AM_RANGE(0x2400000, 0x27fffff) AM_DEVREADWRITE_LEGACY("voodoo1", nwk_voodoo_1_r, voodoo_w)
484	493	AM_RANGE(0x3400000, 0x34000ff) AM_READWRITE_LEGACY(cgboard_1_comm_sharc_r, cgboard_1_comm_sharc_w)

src/mame/drivers/mazerbla.c

r14845	r14846
109	109
110	110	int m_planes_enabled[4];
111	111	#endif
	112	DECLARE_WRITE8_MEMBER(cfb_backgnd_color_w);
	113	DECLARE_WRITE8_MEMBER(cfb_vbank_w);
	114	DECLARE_WRITE8_MEMBER(cfb_rom_bank_sel_w);
	115	DECLARE_WRITE8_MEMBER(cfb_rom_bank_sel_w_gg);
	116	DECLARE_READ8_MEMBER(cfb_port_02_r);
	117	DECLARE_WRITE8_MEMBER(vcu_video_reg_w);
	118	DECLARE_READ8_MEMBER(vcu_set_cmd_param_r);
	119	DECLARE_READ8_MEMBER(vcu_set_gfx_addr_r);
	120	DECLARE_READ8_MEMBER(vcu_set_clr_addr_r);
	121	DECLARE_WRITE8_MEMBER(cfb_zpu_int_req_set_w);
	122	DECLARE_READ8_MEMBER(cfb_zpu_int_req_clr);
	123	DECLARE_READ8_MEMBER(ls670_0_r);
	124	DECLARE_WRITE8_MEMBER(ls670_0_w);
	125	DECLARE_READ8_MEMBER(ls670_1_r);
	126	DECLARE_WRITE8_MEMBER(ls670_1_w);
	127	DECLARE_WRITE8_MEMBER(zpu_bcd_decoder_w);
	128	DECLARE_READ8_MEMBER(zpu_inputs_r);
	129	DECLARE_WRITE8_MEMBER(zpu_led_w);
	130	DECLARE_WRITE8_MEMBER(zpu_lamps_w);
	131	DECLARE_WRITE8_MEMBER(zpu_coin_counter_w);
	132	DECLARE_WRITE8_MEMBER(cfb_led_w);
	133	DECLARE_WRITE8_MEMBER(vsb_ls273_audio_control_w);
	134	DECLARE_WRITE8_MEMBER(main_sound_w);
	135	DECLARE_WRITE8_MEMBER(sound_int_clear_w);
	136	DECLARE_WRITE8_MEMBER(sound_nmi_clear_w);
112	137	};
113	138
114	139
r14845	r14846
291	316	}
292	317
293	318
294		static WRITE8_HANDLER( cfb_backgnd_color_w )
	319	WRITE8_MEMBER(mazerbla_state::cfb_backgnd_color_w)
295	320	{
296		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
297	321
298		if (state->m_bknd_col != data)
	322	if (m_bknd_col != data)
299	323	{
300	324	int r, g, b, bit0, bit1, bit2;
301	325
302		state->m_bknd_col = data;
	326	m_bknd_col = data;
303	327
304	328	/* red component */
305	329	bit1 = BIT(data, 7);
306	330	bit0 = BIT(data, 6);
307		r = combine_2_weights(state->m_weights_r, bit0, bit1);
	331	r = combine_2_weights(m_weights_r, bit0, bit1);
308	332
309	333	/* green component */
310	334	bit2 = BIT(data, 5);
311	335	bit1 = BIT(data, 4);
312	336	bit0 = BIT(data, 3);
313		g = combine_3_weights(state->m_weights_g, bit0, bit1, bit2);
	337	g = combine_3_weights(m_weights_g, bit0, bit1, bit2);
314	338
315	339	/* blue component */
316	340	bit2 = BIT(data, 2);
317	341	bit1 = BIT(data, 1);
318	342	bit0 = BIT(data, 0);
319		b = combine_3_weights(state->m_weights_b, bit0, bit1, bit2);
	343	b = combine_3_weights(m_weights_b, bit0, bit1, bit2);
320	344
321		palette_set_color(space->machine(), 255, MAKE_RGB(r, g, b));
	345	palette_set_color(machine(), 255, MAKE_RGB(r, g, b));
322	346	//logerror("background color (port 01) write=%02x\n",data);
323	347	}
324	348	}
325	349
326	350
327		static WRITE8_HANDLER( cfb_vbank_w )
	351	WRITE8_MEMBER(mazerbla_state::cfb_vbank_w)
328	352	{
329		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
330	353
331	354	/* only bit 6 connected */
332		state->m_vbank = BIT(data, 6);
	355	m_vbank = BIT(data, 6);
333	356	}
334	357
335	358
336		static WRITE8_HANDLER( cfb_rom_bank_sel_w )   /* mazer blazer */
	359	WRITE8_MEMBER(mazerbla_state::cfb_rom_bank_sel_w)/* mazer blazer */
337	360	{
338		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
339		state->m_gfx_rom_bank = data;
	361	m_gfx_rom_bank = data;
340	362
341		memory_set_bankptr(space->machine(),  "bank1", space->machine().region("sub2")->base() + (state->m_gfx_rom_bank * 0x2000) + 0x10000);
	363	memory_set_bankptr(machine(),  "bank1", machine().region("sub2")->base() + (m_gfx_rom_bank * 0x2000) + 0x10000);
342	364	}
343	365
344		static WRITE8_HANDLER( cfb_rom_bank_sel_w_gg )   /* great guns */
	366	WRITE8_MEMBER(mazerbla_state::cfb_rom_bank_sel_w_gg)/* great guns */
345	367	{
346		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
347		state->m_gfx_rom_bank = data >> 1;
	368	m_gfx_rom_bank = data >> 1;
348	369
349		memory_set_bankptr(space->machine(),  "bank1", space->machine().region("sub2")->base() + (state->m_gfx_rom_bank * 0x2000) + 0x10000);
	370	memory_set_bankptr(machine(),  "bank1", machine().region("sub2")->base() + (m_gfx_rom_bank * 0x2000) + 0x10000);
350	371	}
351	372
352	373
353	374	/* VCU status? */
354		static READ8_HANDLER( cfb_port_02_r )
	375	READ8_MEMBER(mazerbla_state::cfb_port_02_r)
355	376	{
356		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
357		state->m_port02_status ^= 0xff;
358		return state->m_port02_status;
	377	m_port02_status ^= 0xff;
	378	return m_port02_status;
359	379	}
360	380
361	381
362		static WRITE8_HANDLER( vcu_video_reg_w )
	382	WRITE8_MEMBER(mazerbla_state::vcu_video_reg_w)
363	383	{
364		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
365		if (state->m_vcu_video_reg[offset] != data)
	384	if (m_vcu_video_reg[offset] != data)
366	385	{
367		state->m_vcu_video_reg[offset] = data;
368		//popmessage("video_reg= %02x %02x %02x %02x", state->m_vcu_video_reg[0], state->m_vcu_video_reg[1], state->m_vcu_video_reg[2], state->m_vcu_video_reg[3]);
369		//logerror("video_reg= %02x %02x %02x %02x\n", state->m_vcu_video_reg[0], state->m_vcu_video_reg[1], state->m_vcu_video_reg[2], state->m_vcu_video_reg[3]);
	386	m_vcu_video_reg[offset] = data;
	387	//popmessage("video_reg= %02x %02x %02x %02x", m_vcu_video_reg[0], m_vcu_video_reg[1], m_vcu_video_reg[2], m_vcu_video_reg[3]);
	388	//logerror("video_reg= %02x %02x %02x %02x\n", m_vcu_video_reg[0], m_vcu_video_reg[1], m_vcu_video_reg[2], m_vcu_video_reg[3]);
370	389	}
371	390	}
372	391
373		static READ8_HANDLER( vcu_set_cmd_param_r )
	392	READ8_MEMBER(mazerbla_state::vcu_set_cmd_param_r)
374	393	{
375		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
376		state->m_vcu_gfx_param_addr = offset;
	394	m_vcu_gfx_param_addr = offset;
377	395
378	396	/* offset  = 0 is not known */
379		state->m_xpos      = state->m_cfb_ram[state->m_vcu_gfx_param_addr + 1] | (state->m_cfb_ram[state->m_vcu_gfx_param_addr + 2]<<8);
380		state->m_ypos      = state->m_cfb_ram[state->m_vcu_gfx_param_addr + 3] | (state->m_cfb_ram[state->m_vcu_gfx_param_addr + 4]<<8);
381		state->m_color1    = state->m_cfb_ram[state->m_vcu_gfx_param_addr + 5];
382		state->m_color2    = state->m_cfb_ram[state->m_vcu_gfx_param_addr + 6];
383		state->m_mode      = state->m_cfb_ram[state->m_vcu_gfx_param_addr + 7];
384		state->m_pix_xsize = state->m_cfb_ram[state->m_vcu_gfx_param_addr + 8];
385		state->m_pix_ysize = state->m_cfb_ram[state->m_vcu_gfx_param_addr + 9];
	397	m_xpos      = m_cfb_ram[m_vcu_gfx_param_addr + 1] | (m_cfb_ram[m_vcu_gfx_param_addr + 2]<<8);
	398	m_ypos      = m_cfb_ram[m_vcu_gfx_param_addr + 3] | (m_cfb_ram[m_vcu_gfx_param_addr + 4]<<8);
	399	m_color1    = m_cfb_ram[m_vcu_gfx_param_addr + 5];
	400	m_color2    = m_cfb_ram[m_vcu_gfx_param_addr + 6];
	401	m_mode      = m_cfb_ram[m_vcu_gfx_param_addr + 7];
	402	m_pix_xsize = m_cfb_ram[m_vcu_gfx_param_addr + 8];
	403	m_pix_ysize = m_cfb_ram[m_vcu_gfx_param_addr + 9];
386	404
387		state->m_plane = state->m_mode & 3;
	405	m_plane = m_mode & 3;
388	406
389	407	return 0;
390	408	}
391	409
392	410
393		static READ8_HANDLER( vcu_set_gfx_addr_r )
	411	READ8_MEMBER(mazerbla_state::vcu_set_gfx_addr_r)
394	412	{
395		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
396		UINT8 * rom = space->machine().region("sub2")->base() + (state->m_gfx_rom_bank * 0x2000) + 0x10000;
	413	UINT8 * rom = machine().region("sub2")->base() + (m_gfx_rom_bank * 0x2000) + 0x10000;
397	414	int offs;
398	415	int x, y;
399	416	int bits = 0;
400	417	UINT8 color_base = 0;
401	418
402		if (state->m_game_id == MAZERBLA)
	419	if (m_game_id == MAZERBLA)
403	420	color_base = 0x80;   /* 0x80 - good for Mazer Blazer: (only in game, CRT test mode is bad) */
404	421
405		if (state->m_game_id == GREATGUN)
	422	if (m_game_id == GREATGUN)
406	423	color_base = 0x00;   /* 0x00 - good for Great Guns: (both in game and CRT test mode) */
407	424	/*
408	425	if ((mode <= 0x07) || (mode >= 0x10))
409	426	{
410	427	logerror("paradr=");
411		logerror("%3x ", state->m_vcu_gfx_param_addr );
	428	logerror("%3x ", m_vcu_gfx_param_addr );
412	429
413		logerror("%02x ", state->m_cfb_ram[vcu_gfx_param_addr + 0] );
414		logerror("x=%04x ", state->m_xpos );                 //1,2
415		logerror("y=%04x ", state->m_ypos );                 //3,4
416		logerror("color1=%02x ", state->m_color1);             //5
417		logerror("color2=%02x ", state->m_color2);           //6
418		logerror("mode=%02x ", state->m_mode );              //7
419		logerror("xpix=%02x ", state->m_pix_xsize );         //8
420		logerror("ypix=%02x ", state->m_pix_ysize );         //9
	430	logerror("%02x ", m_cfb_ram[vcu_gfx_param_addr + 0] );
	431	logerror("x=%04x ", m_xpos );                 //1,2
	432	logerror("y=%04x ", m_ypos );                 //3,4
	433	logerror("color1=%02x ", m_color1);             //5
	434	logerror("color2=%02x ", m_color2);           //6
	435	logerror("mode=%02x ", m_mode );              //7
	436	logerror("xpix=%02x ", m_pix_xsize );         //8
	437	logerror("ypix=%02x ", m_pix_ysize );         //9
421	438
422		logerror("addr=%4i bank=%1i\n", offset, state->m_gfx_rom_bank);
	439	logerror("addr=%4i bank=%1i\n", offset, m_gfx_rom_bank);
423	440	}
424	441	*/
425	442
426		state->m_vcu_gfx_addr = offset;
	443	m_vcu_gfx_addr = offset;
427	444
428	445	/* draw */
429		offs = state->m_vcu_gfx_addr;
	446	offs = m_vcu_gfx_addr;
430	447
431		switch(state->m_mode)
	448	switch(m_mode)
432	449	{
433	450	/* 2 bits per pixel */
434	451	case 0x0f:
435	452	case 0x0e:
436	453	case 0x0d:
437	454	case 0x0c:
438		//      if (state->m_dbg_gfx_e)
	455	//      if (m_dbg_gfx_e)
439	456	//      {
440		//          if (state->m_vbank == state->m_dbg_vbank)
	457	//          if (m_vbank == m_dbg_vbank)
441	458	{
442		for (y = 0; y <= state->m_pix_ysize; y++)
	459	for (y = 0; y <= m_pix_ysize; y++)
443	460	{
444		for (x = 0; x <= state->m_pix_xsize; x++)
	461	for (x = 0; x <= m_pix_xsize; x++)
445	462	{
446	463	UINT8 pixeldata = rom[(offs + (bits >> 3)) % 0x2000];
447	464	UINT8 data = (pixeldata >> (6 - (bits & 7))) & 3;
r14845	r14846
450	467	switch(data)
451	468	{
452	469	case 0:
453		col = color_base | ((state->m_color1 & 0x0f));      //background PEN
	470	col = color_base | ((m_color1 & 0x0f));      //background PEN
454	471	break;
455	472	case 1:
456		col = color_base | ((state->m_color1 & 0xf0) >> 4);   //foreground PEN
	473	col = color_base | ((m_color1 & 0xf0) >> 4);   //foreground PEN
457	474	break;
458	475	case 2:
459		col = color_base | ((state->m_color2 & 0x0f));   //background PEN2
	476	col = color_base | ((m_color2 & 0x0f));   //background PEN2
460	477	break;
461	478	case 3:
462		col = color_base | ((state->m_color2 & 0xf0) >> 4);   //foreground PEN2
	479	col = color_base | ((m_color2 & 0xf0) >> 4);   //foreground PEN2
463	480	break;
464	481	}
465	482
466		if (((state->m_xpos + x) < 256) && ((state->m_ypos + y) < 256) )
467		state->m_tmpbitmaps[state->m_plane].pix16(state->m_ypos + y, state->m_xpos + x) = col;
	483	if (((m_xpos + x) < 256) && ((m_ypos + y) < 256) )
	484	m_tmpbitmaps[m_plane].pix16(m_ypos + y, m_xpos + x) = col;
468	485
469	486	bits += 2;
470	487	}
r14845	r14846
478	495	case 0x0a:/* verified - 1bpp */
479	496	case 0x09:/* verified - 1bpp: gun crosshair */
480	497	case 0x08:/* */
481		//      if (state->m_dbg_gfx_e)
	498	//      if (m_dbg_gfx_e)
482	499	//      {
483		//          if (state->m_vbank == state->m_dbg_vbank)
	500	//          if (m_vbank == m_dbg_vbank)
484	501	{
485	502
486		for (y = 0; y <= state->m_pix_ysize; y++)
	503	for (y = 0; y <= m_pix_ysize; y++)
487	504	{
488		for (x = 0; x <= state->m_pix_xsize; x++)
	505	for (x = 0; x <= m_pix_xsize; x++)
489	506	{
490	507	UINT8 pixeldata = rom[(offs + (bits >> 3)) % 0x2000];
491	508	UINT8 data = (pixeldata >> (7 - (bits & 7))) & 1;
492	509
493	510	/* color = 4 MSB = front PEN, 4 LSB = background PEN */
494	511
495		if (((state->m_xpos + x) < 256) && ((state->m_ypos + y) < 256))
496		state->m_tmpbitmaps[state->m_plane].pix16(state->m_ypos + y, state->m_xpos + x) = data ? color_base | ((state->m_color1 & 0xf0) >> 4): color_base | ((state->m_color1 & 0x0f));
	512	if (((m_xpos + x) < 256) && ((m_ypos + y) < 256))
	513	m_tmpbitmaps[m_plane].pix16(m_ypos + y, m_xpos + x) = data ? color_base | ((m_color1 & 0xf0) >> 4): color_base | ((m_color1 & 0x0f));
497	514
498	515	bits += 1;
499	516	}
r14845	r14846
506	523	case 0x03:
507	524	case 0x01:
508	525	case 0x00:
509		//      if (state->m_dbg_gfx_e)
	526	//      if (m_dbg_gfx_e)
510	527	//      {
511		//          if (state->m_vbank == state->m_dbg_vbank)
	528	//          if (m_vbank == m_dbg_vbank)
512	529	{
513		for (y = 0; y <= state->m_pix_ysize; y++)
	530	for (y = 0; y <= m_pix_ysize; y++)
514	531	{
515		for (x = 0; x <= state->m_pix_xsize; x++)
	532	for (x = 0; x <= m_pix_xsize; x++)
516	533	{
517	534	UINT8 pixeldata = rom[(offs + (bits >> 3)) % 0x2000];
518	535	UINT8 data = (pixeldata >> (4 - (bits & 7))) & 15;
r14845	r14846
520	537
521	538	col = color_base | data;
522	539
523		if (((state->m_xpos + x) < 256) && ((state->m_ypos + y) < 256))
524		state->m_tmpbitmaps[state->m_plane].pix16(state->m_ypos + y, state->m_xpos + x) = col;
	540	if (((m_xpos + x) < 256) && ((m_ypos + y) < 256))
	541	m_tmpbitmaps[m_plane].pix16(m_ypos + y, m_xpos + x) = col;
525	542
526	543	bits += 4;
527	544	}
r14845	r14846
530	547	//      }
531	548	break;
532	549	default:
533		popmessage("not supported VCU drawing mode=%2x", state->m_mode);
	550	popmessage("not supported VCU drawing mode=%2x", m_mode);
534	551	break;
535	552	}
536	553
537	554	return 0;
538	555	}
539	556
540		static READ8_HANDLER( vcu_set_clr_addr_r )
	557	READ8_MEMBER(mazerbla_state::vcu_set_clr_addr_r)
541	558	{
542		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
543		UINT8 * rom = space->machine().region("sub2")->base() + (state->m_gfx_rom_bank * 0x2000) + 0x10000;
	559	UINT8 * rom = machine().region("sub2")->base() + (m_gfx_rom_bank * 0x2000) + 0x10000;
544	560	int offs;
545	561	int x, y;
546	562	int bits = 0;
r14845	r14846
552	568	//if (0) //(mode != 0x07)
553	569	{
554	570	logerror("paladr=");
555		logerror("%3x ", state->m_vcu_gfx_param_addr );
	571	logerror("%3x ", m_vcu_gfx_param_addr );
556	572
557		logerror("%02x ", state->m_cfb_ram[state->m_vcu_gfx_param_addr + 0] );
558		logerror("x=%04x ", state->m_xpos );                 //1,2
559		logerror("y=%04x ", state->m_ypos );                 //3,4
560		logerror("color1=%02x ", state->m_color1);             //5
561		logerror("color2=%02x ", state->m_color2 );          //6
562		logerror("mode=%02x ", state->m_mode );              //7
563		logerror("xpix=%02x ", state->m_pix_xsize );         //8
564		logerror("ypix=%02x ", state->m_pix_ysize );         //9
	573	logerror("%02x ", m_cfb_ram[m_vcu_gfx_param_addr + 0] );
	574	logerror("x=%04x ", m_xpos );                 //1,2
	575	logerror("y=%04x ", m_ypos );                 //3,4
	576	logerror("color1=%02x ", m_color1);             //5
	577	logerror("color2=%02x ", m_color2 );          //6
	578	logerror("mode=%02x ", m_mode );              //7
	579	logerror("xpix=%02x ", m_pix_xsize );         //8
	580	logerror("ypix=%02x ", m_pix_ysize );         //9
565	581
566		logerror("addr=%4i bank=%1i\n", offset, state->m_gfx_rom_bank);
	582	logerror("addr=%4i bank=%1i\n", offset, m_gfx_rom_bank);
567	583
568	584	for (y = 0; y < 16; y++)
569	585	{
570	586	logerror("%04x: ", offset + y * 16);
571	587	for (x = 0; x < 16; x++)
572	588	{
573		logerror("%02x ", state->m_cfb_ram[offset + x + y * 16]);
	589	logerror("%02x ", m_cfb_ram[offset + x + y * 16]);
574	590	}
575	591	logerror("\n");
576	592	}
r14845	r14846
581	597	/* copy palette / CLUT(???) */
582	598
583	599
584		switch (state->m_mode)
	600	switch (m_mode)
585	601	{
586	602	case 0x13: /* draws sprites?? in mazer blazer and ... wrong sprite in place of targeting-cross and UFO laser */
587	603	case 0x03:
588	604	/* ... this may proove that there is really only one area and that
589	605	the draw command/palette selector is done via the 'mode' only ... */
590		//if (state->m_dbg_clr_e)
	606	//if (m_dbg_clr_e)
591	607	{
592		offs = state->m_vcu_gfx_addr;
	608	offs = m_vcu_gfx_addr;
593	609
594		if (state->m_game_id == MAZERBLA)
	610	if (m_game_id == MAZERBLA)
595	611	color_base = 0x80;   /* 0x80 constant: matches Mazer Blazer movie */
596	612
597		if (state->m_game_id == GREATGUN)
	613	if (m_game_id == GREATGUN)
598	614	color_base = 0x00;
599	615
600		for (y = 0; y <= state->m_pix_ysize; y++)
	616	for (y = 0; y <= m_pix_ysize; y++)
601	617	{
602		for (x = 0; x <= state->m_pix_xsize; x++)
	618	for (x = 0; x <= m_pix_xsize; x++)
603	619	{
604	620	UINT8 pixeldata = rom[(offs + (bits >> 3)) % 0x2000];
605	621	UINT8 data = (pixeldata >> (6 - (bits & 7))) & 3;
r14845	r14846
608	624	switch(data)
609	625	{
610	626	case 0:
611		col = color_base | ((state->m_color1 & 0x0f));      //background PEN
	627	col = color_base | ((m_color1 & 0x0f));      //background PEN
612	628	break;
613	629	case 1:
614		col = color_base | ((state->m_color1 & 0xf0) >> 4);   //foreground PEN
	630	col = color_base | ((m_color1 & 0xf0) >> 4);   //foreground PEN
615	631	break;
616	632	case 2:
617		col = color_base | ((state->m_color2 & 0x0f));   //background PEN2
	633	col = color_base | ((m_color2 & 0x0f));   //background PEN2
618	634	break;
619	635	case 3:
620		col = color_base | ((state->m_color2 & 0xf0) >> 4);   //foreground PEN2
	636	col = color_base | ((m_color2 & 0xf0) >> 4);   //foreground PEN2
621	637	break;
622	638	}
623	639
624		if (((state->m_xpos + x) < 256) && ((state->m_ypos + y) < 256))
625		state->m_tmpbitmaps[state->m_plane].pix16(state->m_ypos + y, state->m_xpos + x) = col;
	640	if (((m_xpos + x) < 256) && ((m_ypos + y) < 256))
	641	m_tmpbitmaps[m_plane].pix16(m_ypos + y, m_xpos + x) = col;
626	642
627	643	bits += 2;
628	644	}
r14845	r14846
634	650	case 0x07:
635	651	offs = offset;
636	652
637		switch(state->m_ypos)
	653	switch(m_ypos)
638	654	{
639	655	case 6: //seems to encode palette write
640	656	{
641	657	int r, g, b, bit0, bit1, bit2;
642	658
643	659	//pix_xsize and pix_ysize seem to be related to palette length ? (divide by 2)
644		int lookup_offs = (state->m_ypos >> 1) * 256; //=3*256
	660	int lookup_offs = (m_ypos >> 1) * 256; //=3*256
645	661
646	662	for (y = 0; y < 16; y++)
647	663	{
648	664	for (x = 0; x < 16; x++)
649	665	{
650		UINT8 colour = state->m_cfb_ram[offs + x + y * 16];
	666	UINT8 colour = m_cfb_ram[offs + x + y * 16];
651	667
652	668	/* red component */
653	669	bit1 = (colour >> 7) & 0x01;
654	670	bit0 = (colour >> 6) & 0x01;
655		r = combine_2_weights(state->m_weights_r, bit0, bit1);
	671	r = combine_2_weights(m_weights_r, bit0, bit1);
656	672
657	673	/* green component */
658	674	bit2 = (colour >> 5) & 0x01;
659	675	bit1 = (colour >> 4) & 0x01;
660	676	bit0 = (colour >> 3) & 0x01;
661		g = combine_3_weights(state->m_weights_g, bit0, bit1, bit2);
	677	g = combine_3_weights(m_weights_g, bit0, bit1, bit2);
662	678
663	679	/* blue component */
664	680	bit2 = (colour >> 2) & 0x01;
665	681	bit1 = (colour >> 1) & 0x01;
666	682	bit0 = (colour >> 0) & 0x01;
667		b = combine_3_weights(state->m_weights_b, bit0, bit1, bit2);
	683	b = combine_3_weights(m_weights_b, bit0, bit1, bit2);
668	684
669	685	if ((x + y * 16) < 255)//keep color 255 free for use as background color
670		palette_set_color(space->machine(), x + y * 16, MAKE_RGB(r, g, b));
	686	palette_set_color(machine(), x + y * 16, MAKE_RGB(r, g, b));
671	687
672		state->m_lookup_ram[lookup_offs + x + y * 16] = colour;
	688	m_lookup_ram[lookup_offs + x + y * 16] = colour;
673	689	}
674	690	}
675	691	}
676	692	break;
677	693	case 4: //seems to encode lookup???? table write
678	694	{
679		int lookup_offs = (state->m_ypos >> 1) * 256; //=2*256
	695	int lookup_offs = (m_ypos >> 1) * 256; //=2*256
680	696
681	697	for (y = 0; y < 16; y++)
682	698	{
683	699	for (x = 0; x < 16; x++)
684	700	{
685		UINT8 dat = state->m_cfb_ram[offs + x + y * 16];
686		state->m_lookup_ram[lookup_offs + x + y * 16] = dat;
	701	UINT8 dat = m_cfb_ram[offs + x + y * 16];
	702	m_lookup_ram[lookup_offs + x + y * 16] = dat;
687	703	}
688	704	}
689	705	}
690	706	break;
691	707	case 2: //seems to encode lookup???? table write
692	708	{
693		int lookup_offs = (state->m_ypos >> 1) * 256; //=1*256
	709	int lookup_offs = (m_ypos >> 1) * 256; //=1*256
694	710
695	711	for (y = 0; y < 16; y++)
696	712	{
697	713	for (x = 0; x < 16; x++)
698	714	{
699		UINT8 dat = state->m_cfb_ram[offs + x + y * 16];
700		state->m_lookup_ram[lookup_offs + x + y * 16] = dat;
	715	UINT8 dat = m_cfb_ram[offs + x + y * 16];
	716	m_lookup_ram[lookup_offs + x + y * 16] = dat;
701	717	}
702	718	}
703	719	}
704	720	break;
705	721	case 0: //seems to encode lookup???? table write
706	722	{
707		int lookup_offs = (state->m_ypos >> 1) * 256; //=0*256
	723	int lookup_offs = (m_ypos >> 1) * 256; //=0*256
708	724
709	725	for (y = 0; y < 16; y++)
710	726	{
711	727	for (x = 0; x < 16; x++)
712	728	{
713		UINT8 dat = state->m_cfb_ram[offs + x + y * 16];
714		state->m_lookup_ram[lookup_offs + x + y * 16] = dat;
	729	UINT8 dat = m_cfb_ram[offs + x + y * 16];
	730	m_lookup_ram[lookup_offs + x + y * 16] = dat;
715	731	}
716	732	}
717	733	}
718	734	break;
719	735
720	736	default:
721		popmessage("not supported lookup/color write mode=%2x", state->m_ypos);
	737	popmessage("not supported lookup/color write mode=%2x", m_ypos);
722	738	break;
723	739	}
724	740	break;
725	741
726	742	default:
727		popmessage("not supported VCU color mode=%2x", state->m_mode);
	743	popmessage("not supported VCU color mode=%2x", m_mode);
728	744	break;
729	745	}
730	746
r14845	r14846
737	753	*
738	754	*************************************/
739	755
740		static WRITE8_HANDLER( cfb_zpu_int_req_set_w )
	756	WRITE8_MEMBER(mazerbla_state::cfb_zpu_int_req_set_w)
741	757	{
742		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
743	758
744		state->m_zpu_int_vector &= ~2;   /* clear D1 on INTA (interrupt acknowledge) */
	759	m_zpu_int_vector &= ~2;   /* clear D1 on INTA (interrupt acknowledge) */
745	760
746		device_set_input_line(state->m_maincpu, 0, ASSERT_LINE);   /* main cpu interrupt (comes from CFB (generated at the start of INT routine on CFB) - vblank?) */
	761	device_set_input_line(m_maincpu, 0, ASSERT_LINE);   /* main cpu interrupt (comes from CFB (generated at the start of INT routine on CFB) - vblank?) */
747	762	}
748	763
749		static READ8_HANDLER( cfb_zpu_int_req_clr )
	764	READ8_MEMBER(mazerbla_state::cfb_zpu_int_req_clr)
750	765	{
751		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
752	766
753		state->m_zpu_int_vector |= 2;
	767	m_zpu_int_vector |= 2;
754	768
755	769	/* clear the INT line when there are no more interrupt requests */
756		if (state->m_zpu_int_vector == 0xff)
757		device_set_input_line(state->m_maincpu, 0, CLEAR_LINE);
	770	if (m_zpu_int_vector == 0xff)
	771	device_set_input_line(m_maincpu, 0, CLEAR_LINE);
758	772
759	773	return 0;
760	774	}
761	775
762		static READ8_HANDLER( ls670_0_r )
	776	READ8_MEMBER(mazerbla_state::ls670_0_r)
763	777	{
764		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
765	778
766	779	/* set a timer to force synchronization after the read */
767		space->machine().scheduler().synchronize();
	780	machine().scheduler().synchronize();
768	781
769		return state->m_ls670_0[offset];
	782	return m_ls670_0[offset];
770	783	}
771	784
772	785	static TIMER_CALLBACK( deferred_ls670_0_w )
r14845	r14846
778	791	state->m_ls670_0[offset] = data;
779	792	}
780	793
781		static WRITE8_HANDLER( ls670_0_w )
	794	WRITE8_MEMBER(mazerbla_state::ls670_0_w)
782	795	{
783	796	/* do this on a timer to let the CPUs synchronize */
784		space->machine().scheduler().synchronize(FUNC(deferred_ls670_0_w), (offset << 8) | data);
	797	machine().scheduler().synchronize(FUNC(deferred_ls670_0_w), (offset << 8) | data);
785	798	}
786	799
787		static READ8_HANDLER( ls670_1_r )
	800	READ8_MEMBER(mazerbla_state::ls670_1_r)
788	801	{
789		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
790	802
791	803	/* set a timer to force synchronization after the read */
792		space->machine().scheduler().synchronize();
	804	machine().scheduler().synchronize();
793	805
794		return state->m_ls670_1[offset];
	806	return m_ls670_1[offset];
795	807	}
796	808
797	809	static TIMER_CALLBACK( deferred_ls670_1_w )
r14845	r14846
803	815	state->m_ls670_1[offset] = data;
804	816	}
805	817
806		static WRITE8_HANDLER( ls670_1_w )
	818	WRITE8_MEMBER(mazerbla_state::ls670_1_w)
807	819	{
808	820	/* do this on a timer to let the CPUs synchronize */
809		space->machine().scheduler().synchronize(FUNC(deferred_ls670_1_w), (offset << 8) | data);
	821	machine().scheduler().synchronize(FUNC(deferred_ls670_1_w), (offset << 8) | data);
810	822	}
811	823
812	824
r14845	r14846
862	874
863	875	*/
864	876
865		static WRITE8_HANDLER( zpu_bcd_decoder_w )
	877	WRITE8_MEMBER(mazerbla_state::zpu_bcd_decoder_w)
866	878	{
867		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
868	879
869	880	/* bcd decoder used a input select (a mux) for reads from port 0x62 */
870		state->m_bcd_7445 = data & 0xf;
	881	m_bcd_7445 = data & 0xf;
871	882	}
872	883
873		static READ8_HANDLER( zpu_inputs_r )
	884	READ8_MEMBER(mazerbla_state::zpu_inputs_r)
874	885	{
875		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
876	886	static const char *const strobenames[] = { "ZPU", "DSW0", "DSW1", "DSW2", "DSW3", "BUTTONS", "STICK0_X", "STICK0_Y",
877	887	"STICK1_X", "STICK1_Y", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED", "UNUSED" };
878	888
879	889	UINT8 ret = 0;
880	890
881		ret = input_port_read(space->machine(), strobenames[state->m_bcd_7445]);
	891	ret = input_port_read(machine(), strobenames[m_bcd_7445]);
882	892
883	893	return ret;
884	894	}
885	895
886		static WRITE8_HANDLER( zpu_led_w )
	896	WRITE8_MEMBER(mazerbla_state::zpu_led_w)
887	897	{
888	898	/* 0x6e - reset (offset = 0)*/
889	899	/* 0x6f - set */
890		set_led_status(space->machine(), 0, offset & 1);
	900	set_led_status(machine(), 0, offset & 1);
891	901	}
892	902
893		static WRITE8_HANDLER( zpu_lamps_w)
	903	WRITE8_MEMBER(mazerbla_state::zpu_lamps_w)
894	904	{
895	905	/* bit 4 = /LAMP0 */
896	906	/* bit 5 = /LAMP1 */
897	907
898		/*set_led_status(space->machine(), 0, (data & 0x10) >> 4);*/
899		/*set_led_status(space->machine(), 1, (data & 0x20) >> 4);*/
	908	/*set_led_status(machine(), 0, (data & 0x10) >> 4);*/
	909	/*set_led_status(machine(), 1, (data & 0x20) >> 4);*/
900	910	}
901	911
902		static WRITE8_HANDLER( zpu_coin_counter_w )
	912	WRITE8_MEMBER(mazerbla_state::zpu_coin_counter_w)
903	913	{
904	914	/* bit 6 = coin counter */
905		coin_counter_w(space->machine(), offset, BIT(data, 6));
	915	coin_counter_w(machine(), offset, BIT(data, 6));
906	916	}
907	917
908		static WRITE8_HANDLER(cfb_led_w)
	918	WRITE8_MEMBER(mazerbla_state::cfb_led_w)
909	919	{
910	920	/* bit 7 - led on */
911		set_led_status(space->machine(), 2, BIT(data, 7));
	921	set_led_status(machine(), 2, BIT(data, 7));
912	922	}
913	923
914	924	static WRITE8_DEVICE_HANDLER( gg_led_ctrl_w )
r14845	r14846
924	934	*
925	935	*************************************/
926	936
927		static WRITE8_HANDLER( vsb_ls273_audio_control_w )
	937	WRITE8_MEMBER(mazerbla_state::vsb_ls273_audio_control_w)
928	938	{
929		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
930		state->m_vsb_ls273 = data;
	939	m_vsb_ls273 = data;
931	940
932	941	/* bit 5 - led on */
933		set_led_status(space->machine(), 1, BIT(data, 5));
	942	set_led_status(machine(), 1, BIT(data, 5));
934	943	}
935	944
936	945	static READ8_DEVICE_HANDLER( soundcommand_r )
r14845	r14846
948	957	device_set_input_line(state->m_subcpu, INPUT_LINE_NMI, ASSERT_LINE);
949	958	}
950	959
951		static WRITE8_HANDLER( main_sound_w )
	960	WRITE8_MEMBER(mazerbla_state::main_sound_w)
952	961	{
953		space->machine().scheduler().synchronize(FUNC(delayed_sound_w), data & 0xff);
	962	machine().scheduler().synchronize(FUNC(delayed_sound_w), data & 0xff);
954	963	}
955	964
956		static WRITE8_HANDLER( sound_int_clear_w )
	965	WRITE8_MEMBER(mazerbla_state::sound_int_clear_w)
957	966	{
958		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
959		device_set_input_line(state->m_subcpu, 0, CLEAR_LINE);
	967	device_set_input_line(m_subcpu, 0, CLEAR_LINE);
960	968	}
961	969
962		static WRITE8_HANDLER( sound_nmi_clear_w )
	970	WRITE8_MEMBER(mazerbla_state::sound_nmi_clear_w)
963	971	{
964		mazerbla_state *state = space->machine().driver_data<mazerbla_state>();
965		device_set_input_line(state->m_subcpu, INPUT_LINE_NMI, CLEAR_LINE);
	972	device_set_input_line(m_subcpu, INPUT_LINE_NMI, CLEAR_LINE);
966	973	}
967	974
968	975
r14845	r14846
975	982	static ADDRESS_MAP_START( mazerbla_map, AS_PROGRAM, 8, mazerbla_state )
976	983	AM_RANGE(0x0000, 0x7fff) AM_ROM
977	984	AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_SHARE("share1")
978		AM_RANGE(0xd800, 0xd800) AM_READ_LEGACY(cfb_zpu_int_req_clr)
	985	AM_RANGE(0xd800, 0xd800) AM_READ(cfb_zpu_int_req_clr)
979	986	AM_RANGE(0xe000, 0xe7ff) AM_RAM AM_BASE_SIZE(m_videoram, m_videoram_size)
980	987	AM_RANGE(0xe800, 0xefff) AM_RAM
981	988	ADDRESS_MAP_END
982	989
983	990	static ADDRESS_MAP_START( mazerbla_io_map, AS_IO, 8, mazerbla_state )
984	991	ADDRESS_MAP_GLOBAL_MASK(0xff)
985		AM_RANGE(0x4c, 0x4f) AM_READWRITE_LEGACY(ls670_1_r, ls670_0_w)
986		AM_RANGE(0x60, 0x60) AM_WRITE_LEGACY(zpu_bcd_decoder_w)
987		AM_RANGE(0x62, 0x62) AM_READ_LEGACY(zpu_inputs_r)
988		AM_RANGE(0x68, 0x68) AM_WRITE_LEGACY(zpu_coin_counter_w)
989		AM_RANGE(0x6a, 0x6a) AM_WRITE_LEGACY(zpu_lamps_w)
990		AM_RANGE(0x6e, 0x6f) AM_WRITE_LEGACY(zpu_led_w)
	992	AM_RANGE(0x4c, 0x4f) AM_READWRITE(ls670_1_r, ls670_0_w)
	993	AM_RANGE(0x60, 0x60) AM_WRITE(zpu_bcd_decoder_w)
	994	AM_RANGE(0x62, 0x62) AM_READ(zpu_inputs_r)
	995	AM_RANGE(0x68, 0x68) AM_WRITE(zpu_coin_counter_w)
	996	AM_RANGE(0x6a, 0x6a) AM_WRITE(zpu_lamps_w)
	997	AM_RANGE(0x6e, 0x6f) AM_WRITE(zpu_led_w)
991	998	ADDRESS_MAP_END
992	999
993	1000	static ADDRESS_MAP_START( mazerbla_cpu2_map, AS_PROGRAM, 8, mazerbla_state )
r14845	r14846
998	1005
999	1006	static ADDRESS_MAP_START( mazerbla_cpu2_io_map, AS_IO, 8, mazerbla_state )
1000	1007	ADDRESS_MAP_GLOBAL_MASK(0xff)
1001		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(vsb_ls273_audio_control_w)
1002		AM_RANGE(0x80, 0x83) AM_READWRITE_LEGACY(ls670_0_r, ls670_1_w)
	1008	AM_RANGE(0x00, 0x00) AM_WRITE(vsb_ls273_audio_control_w)
	1009	AM_RANGE(0x80, 0x83) AM_READWRITE(ls670_0_r, ls670_1_w)
1003	1010	ADDRESS_MAP_END
1004	1011
1005	1012	static ADDRESS_MAP_START( mazerbla_cpu3_map, AS_PROGRAM, 8, mazerbla_state )
1006	1013	AM_RANGE(0x0000, 0x37ff) AM_ROM
1007	1014	AM_RANGE(0x3800, 0x3fff) AM_RAM AM_SHARE("share1")
1008	1015	AM_RANGE(0x4000, 0x5fff) AM_ROMBANK("bank1")               /* GFX roms */
1009		AM_RANGE(0x4000, 0x4003) AM_WRITE_LEGACY(vcu_video_reg_w)
	1016	AM_RANGE(0x4000, 0x4003) AM_WRITE(vcu_video_reg_w)
1010	1017	AM_RANGE(0x6000, 0x67ff) AM_RAM AM_BASE(m_cfb_ram)      /* Color Frame Buffer PCB, a.k.a. RAM for VCU commands and parameters */
1011		AM_RANGE(0xa000, 0xa7ff) AM_READ_LEGACY(vcu_set_cmd_param_r)   /* VCU command and parameters LOAD */
1012		AM_RANGE(0xc000, 0xdfff) AM_READ_LEGACY(vcu_set_gfx_addr_r)   /* gfx LOAD (blit) */
1013		AM_RANGE(0xe000, 0xffff) AM_READ_LEGACY(vcu_set_clr_addr_r)   /* palette? LOAD */
	1018	AM_RANGE(0xa000, 0xa7ff) AM_READ(vcu_set_cmd_param_r)   /* VCU command and parameters LOAD */
	1019	AM_RANGE(0xc000, 0xdfff) AM_READ(vcu_set_gfx_addr_r)   /* gfx LOAD (blit) */
	1020	AM_RANGE(0xe000, 0xffff) AM_READ(vcu_set_clr_addr_r)   /* palette? LOAD */
1014	1021	ADDRESS_MAP_END
1015	1022
1016	1023	static ADDRESS_MAP_START( mazerbla_cpu3_io_map, AS_IO, 8, mazerbla_state )
1017	1024	ADDRESS_MAP_GLOBAL_MASK(0xff)
1018		AM_RANGE(0x01, 0x01) AM_WRITE_LEGACY(cfb_backgnd_color_w)
1019		AM_RANGE(0x02, 0x02) AM_READWRITE_LEGACY(cfb_port_02_r, cfb_led_w)   /* Read = VCU status ? */
1020		AM_RANGE(0x03, 0x03) AM_WRITE_LEGACY(cfb_zpu_int_req_set_w)
1021		AM_RANGE(0x04, 0x04) AM_WRITE_LEGACY(cfb_rom_bank_sel_w)
1022		AM_RANGE(0x05, 0x05) AM_WRITE_LEGACY(cfb_vbank_w)   //visible/writable videopage select?
	1025	AM_RANGE(0x01, 0x01) AM_WRITE(cfb_backgnd_color_w)
	1026	AM_RANGE(0x02, 0x02) AM_READWRITE(cfb_port_02_r, cfb_led_w)   /* Read = VCU status ? */
	1027	AM_RANGE(0x03, 0x03) AM_WRITE(cfb_zpu_int_req_set_w)
	1028	AM_RANGE(0x04, 0x04) AM_WRITE(cfb_rom_bank_sel_w)
	1029	AM_RANGE(0x05, 0x05) AM_WRITE(cfb_vbank_w)   //visible/writable videopage select?
1023	1030	ADDRESS_MAP_END
1024	1031
1025	1032
r14845	r14846
1031	1038
1032	1039	static ADDRESS_MAP_START( greatgun_io_map, AS_IO, 8, mazerbla_state )
1033	1040	ADDRESS_MAP_GLOBAL_MASK(0xff)
1034		AM_RANGE(0x4c, 0x4c) AM_WRITE_LEGACY(main_sound_w)
1035		AM_RANGE(0x60, 0x60) AM_WRITE_LEGACY(zpu_bcd_decoder_w)
1036		AM_RANGE(0x62, 0x62) AM_READ_LEGACY(zpu_inputs_r)
	1041	AM_RANGE(0x4c, 0x4c) AM_WRITE(main_sound_w)
	1042	AM_RANGE(0x60, 0x60) AM_WRITE(zpu_bcd_decoder_w)
	1043	AM_RANGE(0x62, 0x62) AM_READ(zpu_inputs_r)
1037	1044	AM_RANGE(0x66, 0x66) AM_WRITENOP
1038	1045	AM_RANGE(0x68, 0x68) AM_WRITENOP
1039		AM_RANGE(0x6e, 0x6f) AM_WRITE_LEGACY(zpu_led_w)
	1046	AM_RANGE(0x6e, 0x6f) AM_WRITE(zpu_led_w)
1040	1047	ADDRESS_MAP_END
1041	1048
1042	1049	/* Great Guns has a little different banking layout */
1043	1050	static ADDRESS_MAP_START( greatgun_cpu3_io_map, AS_IO, 8, mazerbla_state )
1044	1051	ADDRESS_MAP_GLOBAL_MASK(0xff)
1045	1052	AM_RANGE(0x00, 0x00) AM_WRITENOP
1046		AM_RANGE(0x01, 0x01) AM_WRITE_LEGACY(cfb_backgnd_color_w)
1047		AM_RANGE(0x02, 0x02) AM_READWRITE_LEGACY(cfb_port_02_r, cfb_led_w)   /* Read = VCU status ? */
1048		AM_RANGE(0x03, 0x03) AM_WRITE_LEGACY(cfb_zpu_int_req_set_w)
1049		AM_RANGE(0x04, 0x04) AM_WRITE_LEGACY(cfb_rom_bank_sel_w_gg)
1050		AM_RANGE(0x05, 0x05) AM_WRITE_LEGACY(cfb_vbank_w)   //visible/writable videopage select?
	1053	AM_RANGE(0x01, 0x01) AM_WRITE(cfb_backgnd_color_w)
	1054	AM_RANGE(0x02, 0x02) AM_READWRITE(cfb_port_02_r, cfb_led_w)   /* Read = VCU status ? */
	1055	AM_RANGE(0x03, 0x03) AM_WRITE(cfb_zpu_int_req_set_w)
	1056	AM_RANGE(0x04, 0x04) AM_WRITE(cfb_rom_bank_sel_w_gg)
	1057	AM_RANGE(0x05, 0x05) AM_WRITE(cfb_vbank_w)   //visible/writable videopage select?
1051	1058	ADDRESS_MAP_END
1052	1059
1053	1060	static ADDRESS_MAP_START( greatgun_sound_map, AS_PROGRAM, 8, mazerbla_state )
r14845	r14846
1056	1063	AM_RANGE(0x4000, 0x4000) AM_DEVREAD_LEGACY("ay1", ay8910_r)
1057	1064	AM_RANGE(0x4000, 0x4001) AM_DEVWRITE_LEGACY("ay1", ay8910_address_data_w)
1058	1065	AM_RANGE(0x6000, 0x6001) AM_DEVWRITE_LEGACY("ay2", ay8910_address_data_w)
1059		AM_RANGE(0x8000, 0x8000) AM_WRITE_LEGACY(sound_int_clear_w)
1060		AM_RANGE(0xa000, 0xa000) AM_WRITE_LEGACY(sound_nmi_clear_w)
	1066	AM_RANGE(0x8000, 0x8000) AM_WRITE(sound_int_clear_w)
	1067	AM_RANGE(0xa000, 0xa000) AM_WRITE(sound_nmi_clear_w)
1061	1068	ADDRESS_MAP_END
1062	1069
1063	1070

src/mame/drivers/acefruit.c

r14845	r14846
25	25	UINT8 *m_colorram;
26	26	UINT8 *m_videoram;
27	27	emu_timer *m_refresh_timer;
	28	DECLARE_WRITE8_MEMBER(acefruit_colorram_w);
	29	DECLARE_WRITE8_MEMBER(acefruit_coin_w);
	30	DECLARE_WRITE8_MEMBER(acefruit_sound_w);
	31	DECLARE_WRITE8_MEMBER(acefruit_lamp_w);
	32	DECLARE_WRITE8_MEMBER(acefruit_solenoid_w);
28	33	};
29	34
30	35
r14845	r14846
215	220	}
216	221	}
217	222
218		static WRITE8_HANDLER( acefruit_colorram_w )
	223	WRITE8_MEMBER(acefruit_state::acefruit_colorram_w)
219	224	{
220		acefruit_state *state = space->machine().driver_data<acefruit_state>();
221		state->m_colorram[ offset ] = data & 0xf;
	225	m_colorram[ offset ] = data & 0xf;
222	226	}
223	227
224		static WRITE8_HANDLER( acefruit_coin_w )
	228	WRITE8_MEMBER(acefruit_state::acefruit_coin_w)
225	229	{
226	230	/* TODO: ? */
227	231	}
228	232
229		static WRITE8_HANDLER( acefruit_sound_w )
	233	WRITE8_MEMBER(acefruit_state::acefruit_sound_w)
230	234	{
231	235	/* TODO: ? */
232	236	}
233	237
234		static WRITE8_HANDLER( acefruit_lamp_w )
	238	WRITE8_MEMBER(acefruit_state::acefruit_lamp_w)
235	239	{
236	240	int i;
237	241
r14845	r14846
241	245	}
242	246	}
243	247
244		static WRITE8_HANDLER( acefruit_solenoid_w )
	248	WRITE8_MEMBER(acefruit_state::acefruit_solenoid_w)
245	249	{
246	250	int i;
247	251
r14845	r14846
278	282	AM_RANGE(0x0000, 0x1fff) AM_ROM
279	283	AM_RANGE(0x2000, 0x20ff) AM_RAM AM_SHARE("nvram")
280	284	AM_RANGE(0x4000, 0x43ff) AM_RAM AM_BASE(m_videoram)
281		AM_RANGE(0x4400, 0x47ff) AM_RAM_WRITE_LEGACY(acefruit_colorram_w) AM_BASE(m_colorram)
	285	AM_RANGE(0x4400, 0x47ff) AM_RAM_WRITE(acefruit_colorram_w) AM_BASE(m_colorram)
282	286	AM_RANGE(0x8000, 0x8000) AM_READ_PORT("IN0")
283	287	AM_RANGE(0x8001, 0x8001) AM_READ_PORT("IN1")
284	288	AM_RANGE(0x8002, 0x8002) AM_READ_PORT("IN2")
r14845	r14846
288	292	AM_RANGE(0x8006, 0x8006) AM_READ_PORT("IN6")
289	293	AM_RANGE(0x8007, 0x8007) AM_READ_PORT("IN7")
290	294	AM_RANGE(0x6000, 0x6005) AM_RAM AM_BASE(m_spriteram)
291		AM_RANGE(0xa000, 0xa001) AM_WRITE_LEGACY(acefruit_lamp_w)
292		AM_RANGE(0xa002, 0xa003) AM_WRITE_LEGACY(acefruit_coin_w)
293		AM_RANGE(0xa004, 0xa004) AM_WRITE_LEGACY(acefruit_solenoid_w)
294		AM_RANGE(0xa005, 0xa006) AM_WRITE_LEGACY(acefruit_sound_w)
	295	AM_RANGE(0xa000, 0xa001) AM_WRITE(acefruit_lamp_w)
	296	AM_RANGE(0xa002, 0xa003) AM_WRITE(acefruit_coin_w)
	297	AM_RANGE(0xa004, 0xa004) AM_WRITE(acefruit_solenoid_w)
	298	AM_RANGE(0xa005, 0xa006) AM_WRITE(acefruit_sound_w)
295	299	AM_RANGE(0xc000, 0xc000) AM_WRITE_LEGACY(watchdog_reset_w)
296	300	AM_RANGE(0xe000, 0xffff) AM_ROM
297	301	ADDRESS_MAP_END

src/mame/drivers/skylncr.c

r14845	r14846
67	67	UINT8 m_nmi_enable;
68	68	int m_color;
69	69	int m_color2;
	70	DECLARE_WRITE8_MEMBER(skylncr_videoram_w);
	71	DECLARE_WRITE8_MEMBER(skylncr_colorram_w);
	72	DECLARE_WRITE8_MEMBER(reeltiles_1_w);
	73	DECLARE_WRITE8_MEMBER(reeltiles_2_w);
	74	DECLARE_WRITE8_MEMBER(reeltiles_3_w);
	75	DECLARE_WRITE8_MEMBER(reeltiles_4_w);
	76	DECLARE_WRITE8_MEMBER(reeltileshigh_1_w);
	77	DECLARE_WRITE8_MEMBER(reeltileshigh_2_w);
	78	DECLARE_WRITE8_MEMBER(reeltileshigh_3_w);
	79	DECLARE_WRITE8_MEMBER(reeltileshigh_4_w);
	80	DECLARE_WRITE8_MEMBER(skylncr_paletteram_w);
	81	DECLARE_WRITE8_MEMBER(skylncr_paletteram2_w);
	82	DECLARE_WRITE8_MEMBER(reelscroll1_w);
	83	DECLARE_WRITE8_MEMBER(reelscroll2_w);
	84	DECLARE_WRITE8_MEMBER(reelscroll3_w);
	85	DECLARE_WRITE8_MEMBER(reelscroll4_w);
	86	DECLARE_WRITE8_MEMBER(skylncr_coin_w);
	87	DECLARE_READ8_MEMBER(ret_ff);
	88	DECLARE_READ8_MEMBER(ret_00);
	89	DECLARE_WRITE8_MEMBER(skylncr_nmi_enable_w);
70	90	};
71	91
72	92
r14845	r14846
74	94	*           Video Hardware            *
75	95	**************************************/
76	96
77		static WRITE8_HANDLER( skylncr_videoram_w )
	97	WRITE8_MEMBER(skylncr_state::skylncr_videoram_w)
78	98	{
79		skylncr_state *state = space->machine().driver_data<skylncr_state>();
80		state->m_videoram[offset] = data;
81		state->m_tmap->mark_tile_dirty(offset);
	99	m_videoram[offset] = data;
	100	m_tmap->mark_tile_dirty(offset);
82	101	}
83	102
84		static WRITE8_HANDLER( skylncr_colorram_w )
	103	WRITE8_MEMBER(skylncr_state::skylncr_colorram_w)
85	104	{
86		skylncr_state *state = space->machine().driver_data<skylncr_state>();
87		state->m_colorram[offset] = data;
88		state->m_tmap->mark_tile_dirty(offset);
	105	m_colorram[offset] = data;
	106	m_tmap->mark_tile_dirty(offset);
89	107	}
90	108
91	109
r14845	r14846
178	196	return 0;
179	197	}
180	198
181		static WRITE8_HANDLER( reeltiles_1_w )
	199	WRITE8_MEMBER(skylncr_state::reeltiles_1_w)
182	200	{
183		skylncr_state *state = space->machine().driver_data<skylncr_state>();
184		state->m_reeltiles_1_ram[offset] = data;
185		state->m_reel_1_tilemap->mark_tile_dirty(offset);
	201	m_reeltiles_1_ram[offset] = data;
	202	m_reel_1_tilemap->mark_tile_dirty(offset);
186	203	}
187	204
188		static WRITE8_HANDLER( reeltiles_2_w )
	205	WRITE8_MEMBER(skylncr_state::reeltiles_2_w)
189	206	{
190		skylncr_state *state = space->machine().driver_data<skylncr_state>();
191		state->m_reeltiles_2_ram[offset] = data;
192		state->m_reel_2_tilemap->mark_tile_dirty(offset);
	207	m_reeltiles_2_ram[offset] = data;
	208	m_reel_2_tilemap->mark_tile_dirty(offset);
193	209	}
194	210
195		static WRITE8_HANDLER( reeltiles_3_w )
	211	WRITE8_MEMBER(skylncr_state::reeltiles_3_w)
196	212	{
197		skylncr_state *state = space->machine().driver_data<skylncr_state>();
198		state->m_reeltiles_3_ram[offset] = data;
199		state->m_reel_3_tilemap->mark_tile_dirty(offset);
	213	m_reeltiles_3_ram[offset] = data;
	214	m_reel_3_tilemap->mark_tile_dirty(offset);
200	215	}
201	216
202		static WRITE8_HANDLER( reeltiles_4_w )
	217	WRITE8_MEMBER(skylncr_state::reeltiles_4_w)
203	218	{
204		skylncr_state *state = space->machine().driver_data<skylncr_state>();
205		state->m_reeltiles_4_ram[offset] = data;
206		state->m_reel_4_tilemap->mark_tile_dirty(offset);
	219	m_reeltiles_4_ram[offset] = data;
	220	m_reel_4_tilemap->mark_tile_dirty(offset);
207	221	}
208	222
209		static WRITE8_HANDLER( reeltileshigh_1_w )
	223	WRITE8_MEMBER(skylncr_state::reeltileshigh_1_w)
210	224	{
211		skylncr_state *state = space->machine().driver_data<skylncr_state>();
212		state->m_reeltileshigh_1_ram[offset] = data;
213		state->m_reel_1_tilemap->mark_tile_dirty(offset);
	225	m_reeltileshigh_1_ram[offset] = data;
	226	m_reel_1_tilemap->mark_tile_dirty(offset);
214	227	}
215	228
216		static WRITE8_HANDLER( reeltileshigh_2_w )
	229	WRITE8_MEMBER(skylncr_state::reeltileshigh_2_w)
217	230	{
218		skylncr_state *state = space->machine().driver_data<skylncr_state>();
219		state->m_reeltileshigh_2_ram[offset] = data;
220		state->m_reel_2_tilemap->mark_tile_dirty(offset);
	231	m_reeltileshigh_2_ram[offset] = data;
	232	m_reel_2_tilemap->mark_tile_dirty(offset);
221	233	}
222	234
223		static WRITE8_HANDLER( reeltileshigh_3_w )
	235	WRITE8_MEMBER(skylncr_state::reeltileshigh_3_w)
224	236	{
225		skylncr_state *state = space->machine().driver_data<skylncr_state>();
226		state->m_reeltileshigh_3_ram[offset] = data;
227		state->m_reel_3_tilemap->mark_tile_dirty(offset);
	237	m_reeltileshigh_3_ram[offset] = data;
	238	m_reel_3_tilemap->mark_tile_dirty(offset);
228	239	}
229	240
230		static WRITE8_HANDLER( reeltileshigh_4_w )
	241	WRITE8_MEMBER(skylncr_state::reeltileshigh_4_w)
231	242	{
232		skylncr_state *state = space->machine().driver_data<skylncr_state>();
233		state->m_reeltileshigh_4_ram[offset] = data;
234		state->m_reel_4_tilemap->mark_tile_dirty(offset);
	243	m_reeltileshigh_4_ram[offset] = data;
	244	m_reel_4_tilemap->mark_tile_dirty(offset);
235	245	}
236	246
237	247
238		static WRITE8_HANDLER( skylncr_paletteram_w )
	248	WRITE8_MEMBER(skylncr_state::skylncr_paletteram_w)
239	249	{
240		skylncr_state *state = space->machine().driver_data<skylncr_state>();
241	250
242	251	if (offset == 0)
243	252	{
244		state->m_color = data;
	253	m_color = data;
245	254	}
246	255	else
247	256	{
248	257	int r,g,b;
249		space->machine().generic.paletteram.u8[state->m_color] = data;
	258	machine().generic.paletteram.u8[m_color] = data;
250	259
251		r = space->machine().generic.paletteram.u8[(state->m_color/3 * 3) + 0];
252		g = space->machine().generic.paletteram.u8[(state->m_color/3 * 3) + 1];
253		b = space->machine().generic.paletteram.u8[(state->m_color/3 * 3) + 2];
	260	r = machine().generic.paletteram.u8[(m_color/3 * 3) + 0];
	261	g = machine().generic.paletteram.u8[(m_color/3 * 3) + 1];
	262	b = machine().generic.paletteram.u8[(m_color/3 * 3) + 2];
254	263	r = (r << 2) | (r >> 4);
255	264	g = (g << 2) | (g >> 4);
256	265	b = (b << 2) | (b >> 4);
257	266
258		palette_set_color(space->machine(), state->m_color / 3, MAKE_RGB(r, g, b));
259		state->m_color = (state->m_color + 1) % (0x100 * 3);
	267	palette_set_color(machine(), m_color / 3, MAKE_RGB(r, g, b));
	268	m_color = (m_color + 1) % (0x100 * 3);
260	269	}
261	270	}
262	271
263		static WRITE8_HANDLER( skylncr_paletteram2_w )
	272	WRITE8_MEMBER(skylncr_state::skylncr_paletteram2_w)
264	273	{
265		skylncr_state *state = space->machine().driver_data<skylncr_state>();
266	274
267	275	if (offset == 0)
268	276	{
269		state->m_color2 = data;
	277	m_color2 = data;
270	278	}
271	279	else
272	280	{
273	281	int r,g,b;
274		space->machine().generic.paletteram2.u8[state->m_color2] = data;
	282	machine().generic.paletteram2.u8[m_color2] = data;
275	283
276		r = space->machine().generic.paletteram2.u8[(state->m_color2/3 * 3) + 0];
277		g = space->machine().generic.paletteram2.u8[(state->m_color2/3 * 3) + 1];
278		b = space->machine().generic.paletteram2.u8[(state->m_color2/3 * 3) + 2];
	284	r = machine().generic.paletteram2.u8[(m_color2/3 * 3) + 0];
	285	g = machine().generic.paletteram2.u8[(m_color2/3 * 3) + 1];
	286	b = machine().generic.paletteram2.u8[(m_color2/3 * 3) + 2];
279	287	r = (r << 2) | (r >> 4);
280	288	g = (g << 2) | (g >> 4);
281	289	b = (b << 2) | (b >> 4);
282	290
283		palette_set_color(space->machine(), 0x100 + state->m_color2 / 3, MAKE_RGB(r, g, b));
284		state->m_color2 = (state->m_color2 + 1) % (0x100 * 3);
	291	palette_set_color(machine(), 0x100 + m_color2 / 3, MAKE_RGB(r, g, b));
	292	m_color2 = (m_color2 + 1) % (0x100 * 3);
285	293	}
286	294	}
287	295
288		static WRITE8_HANDLER( reelscroll1_w )
	296	WRITE8_MEMBER(skylncr_state::reelscroll1_w)
289	297	{
290		skylncr_state *state = space->machine().driver_data<skylncr_state>();
291		state->m_reelscroll1[offset] = data;
	298	m_reelscroll1[offset] = data;
292	299	}
293	300
294		static WRITE8_HANDLER( reelscroll2_w )
	301	WRITE8_MEMBER(skylncr_state::reelscroll2_w)
295	302	{
296		skylncr_state *state = space->machine().driver_data<skylncr_state>();
297		state->m_reelscroll2[offset] = data;
	303	m_reelscroll2[offset] = data;
298	304	}
299	305
300		static WRITE8_HANDLER( reelscroll3_w )
	306	WRITE8_MEMBER(skylncr_state::reelscroll3_w)
301	307	{
302		skylncr_state *state = space->machine().driver_data<skylncr_state>();
303		state->m_reelscroll3[offset] = data;
	308	m_reelscroll3[offset] = data;
304	309	}
305	310
306		static WRITE8_HANDLER( reelscroll4_w )
	311	WRITE8_MEMBER(skylncr_state::reelscroll4_w)
307	312	{
308		skylncr_state *state = space->machine().driver_data<skylncr_state>();
309		state->m_reelscroll4[offset] = data;
	313	m_reelscroll4[offset] = data;
310	314	}
311	315
312	316
r14845	r14846
314	318	*         Other Handlers            *
315	319	************************************/
316	320
317		static WRITE8_HANDLER( skylncr_coin_w )
	321	WRITE8_MEMBER(skylncr_state::skylncr_coin_w)
318	322	{
319		coin_counter_w( space->machine(), 0, data & 0x04 );
	323	coin_counter_w( machine(), 0, data & 0x04 );
320	324	}
321	325
322		static READ8_HANDLER( ret_ff )
	326	READ8_MEMBER(skylncr_state::ret_ff)
323	327	{
324	328	return 0xff;
325	329	}
326	330
327	331	#ifdef UNUSED_FUNCTION
328		static READ8_HANDLER( ret_00 )
	332	READ8_MEMBER(skylncr_state::ret_00)
329	333	{
330	334	return 0x00;
331	335	}
332	336	#endif
333	337
334		static WRITE8_HANDLER( skylncr_nmi_enable_w )
	338	WRITE8_MEMBER(skylncr_state::skylncr_nmi_enable_w)
335	339	{
336		skylncr_state *state = space->machine().driver_data<skylncr_state>();
337		state->m_nmi_enable = data & 0x10;
	340	m_nmi_enable = data & 0x10;
338	341	}
339	342
340	343
r14845	r14846
346	349	AM_RANGE(0x0000, 0x7fff) AM_ROM
347	350	AM_RANGE(0x8000, 0x87ff) AM_RAM AM_SHARE("nvram")
348	351
349		AM_RANGE(0x8800, 0x8fff) AM_RAM_WRITE_LEGACY(skylncr_videoram_w ) AM_BASE(m_videoram )
350		AM_RANGE(0x9000, 0x97ff) AM_RAM_WRITE_LEGACY(skylncr_colorram_w ) AM_BASE(m_colorram )
	352	AM_RANGE(0x8800, 0x8fff) AM_RAM_WRITE(skylncr_videoram_w ) AM_BASE(m_videoram )
	353	AM_RANGE(0x9000, 0x97ff) AM_RAM_WRITE(skylncr_colorram_w ) AM_BASE(m_colorram )
351	354
352		AM_RANGE(0x9800, 0x99ff) AM_RAM_WRITE_LEGACY(reeltiles_1_w ) AM_BASE(m_reeltiles_1_ram )
353		AM_RANGE(0x9a00, 0x9bff) AM_RAM_WRITE_LEGACY(reeltiles_2_w ) AM_BASE(m_reeltiles_2_ram )
354		AM_RANGE(0x9c00, 0x9dff) AM_RAM_WRITE_LEGACY(reeltiles_3_w ) AM_BASE(m_reeltiles_3_ram )
355		AM_RANGE(0x9e00, 0x9fff) AM_RAM_WRITE_LEGACY(reeltiles_4_w ) AM_BASE(m_reeltiles_4_ram )
356		AM_RANGE(0xa000, 0xa1ff) AM_RAM_WRITE_LEGACY(reeltileshigh_1_w ) AM_BASE(m_reeltileshigh_1_ram )
357		AM_RANGE(0xa200, 0xa3ff) AM_RAM_WRITE_LEGACY(reeltileshigh_2_w ) AM_BASE(m_reeltileshigh_2_ram )
358		AM_RANGE(0xa400, 0xa5ff) AM_RAM_WRITE_LEGACY(reeltileshigh_3_w ) AM_BASE(m_reeltileshigh_3_ram )
359		AM_RANGE(0xa600, 0xa7ff) AM_RAM_WRITE_LEGACY(reeltileshigh_4_w ) AM_BASE(m_reeltileshigh_4_ram )
	355	AM_RANGE(0x9800, 0x99ff) AM_RAM_WRITE(reeltiles_1_w ) AM_BASE(m_reeltiles_1_ram )
	356	AM_RANGE(0x9a00, 0x9bff) AM_RAM_WRITE(reeltiles_2_w ) AM_BASE(m_reeltiles_2_ram )
	357	AM_RANGE(0x9c00, 0x9dff) AM_RAM_WRITE(reeltiles_3_w ) AM_BASE(m_reeltiles_3_ram )
	358	AM_RANGE(0x9e00, 0x9fff) AM_RAM_WRITE(reeltiles_4_w ) AM_BASE(m_reeltiles_4_ram )
	359	AM_RANGE(0xa000, 0xa1ff) AM_RAM_WRITE(reeltileshigh_1_w ) AM_BASE(m_reeltileshigh_1_ram )
	360	AM_RANGE(0xa200, 0xa3ff) AM_RAM_WRITE(reeltileshigh_2_w ) AM_BASE(m_reeltileshigh_2_ram )
	361	AM_RANGE(0xa400, 0xa5ff) AM_RAM_WRITE(reeltileshigh_3_w ) AM_BASE(m_reeltileshigh_3_ram )
	362	AM_RANGE(0xa600, 0xa7ff) AM_RAM_WRITE(reeltileshigh_4_w ) AM_BASE(m_reeltileshigh_4_ram )
360	363
361		AM_RANGE(0xaa55, 0xaa55) AM_READ_LEGACY(ret_ff )
	364	AM_RANGE(0xaa55, 0xaa55) AM_READ(ret_ff )
362	365
363		AM_RANGE(0xb000, 0xb03f) AM_RAM_WRITE_LEGACY(reelscroll1_w) AM_BASE(m_reelscroll1)
364		AM_RANGE(0xb040, 0xb07f) AM_RAM_WRITE_LEGACY(reelscroll1_w)
365		AM_RANGE(0xb080, 0xb0bf) AM_RAM_WRITE_LEGACY(reelscroll1_w)
366		AM_RANGE(0xb0c0, 0xb0ff) AM_RAM_WRITE_LEGACY(reelscroll1_w)
367		AM_RANGE(0xb100, 0xb13f) AM_RAM_WRITE_LEGACY(reelscroll1_w)
368		AM_RANGE(0xb140, 0xb17f) AM_RAM_WRITE_LEGACY(reelscroll1_w)
369		AM_RANGE(0xb180, 0xb1bf) AM_RAM_WRITE_LEGACY(reelscroll1_w)
370		AM_RANGE(0xb1c0, 0xb1ff) AM_RAM_WRITE_LEGACY(reelscroll1_w)
	366	AM_RANGE(0xb000, 0xb03f) AM_RAM_WRITE(reelscroll1_w) AM_BASE(m_reelscroll1)
	367	AM_RANGE(0xb040, 0xb07f) AM_RAM_WRITE(reelscroll1_w)
	368	AM_RANGE(0xb080, 0xb0bf) AM_RAM_WRITE(reelscroll1_w)
	369	AM_RANGE(0xb0c0, 0xb0ff) AM_RAM_WRITE(reelscroll1_w)
	370	AM_RANGE(0xb100, 0xb13f) AM_RAM_WRITE(reelscroll1_w)
	371	AM_RANGE(0xb140, 0xb17f) AM_RAM_WRITE(reelscroll1_w)
	372	AM_RANGE(0xb180, 0xb1bf) AM_RAM_WRITE(reelscroll1_w)
	373	AM_RANGE(0xb1c0, 0xb1ff) AM_RAM_WRITE(reelscroll1_w)
371	374
372		AM_RANGE(0xb200, 0xb23f) AM_RAM_WRITE_LEGACY(reelscroll2_w) AM_BASE(m_reelscroll2)
373		AM_RANGE(0xb240, 0xb27f) AM_RAM_WRITE_LEGACY(reelscroll2_w)
374		AM_RANGE(0xb280, 0xb2bf) AM_RAM_WRITE_LEGACY(reelscroll2_w)
375		AM_RANGE(0xb2c0, 0xb2ff) AM_RAM_WRITE_LEGACY(reelscroll2_w)
376		AM_RANGE(0xb300, 0xb33f) AM_RAM_WRITE_LEGACY(reelscroll2_w)
377		AM_RANGE(0xb340, 0xb37f) AM_RAM_WRITE_LEGACY(reelscroll2_w)
378		AM_RANGE(0xb380, 0xb3bf) AM_RAM_WRITE_LEGACY(reelscroll2_w)
379		AM_RANGE(0xb3c0, 0xb3ff) AM_RAM_WRITE_LEGACY(reelscroll2_w)
	375	AM_RANGE(0xb200, 0xb23f) AM_RAM_WRITE(reelscroll2_w) AM_BASE(m_reelscroll2)
	376	AM_RANGE(0xb240, 0xb27f) AM_RAM_WRITE(reelscroll2_w)
	377	AM_RANGE(0xb280, 0xb2bf) AM_RAM_WRITE(reelscroll2_w)
	378	AM_RANGE(0xb2c0, 0xb2ff) AM_RAM_WRITE(reelscroll2_w)
	379	AM_RANGE(0xb300, 0xb33f) AM_RAM_WRITE(reelscroll2_w)
	380	AM_RANGE(0xb340, 0xb37f) AM_RAM_WRITE(reelscroll2_w)
	381	AM_RANGE(0xb380, 0xb3bf) AM_RAM_WRITE(reelscroll2_w)
	382	AM_RANGE(0xb3c0, 0xb3ff) AM_RAM_WRITE(reelscroll2_w)
380	383
381		AM_RANGE(0xb400, 0xb43f) AM_RAM_WRITE_LEGACY(reelscroll3_w) AM_BASE(m_reelscroll3)
382		AM_RANGE(0xb440, 0xb47f) AM_RAM_WRITE_LEGACY(reelscroll3_w)
383		AM_RANGE(0xb480, 0xb4bf) AM_RAM_WRITE_LEGACY(reelscroll3_w)
384		AM_RANGE(0xb4c0, 0xb4ff) AM_RAM_WRITE_LEGACY(reelscroll3_w)
385		AM_RANGE(0xb500, 0xb53f) AM_RAM_WRITE_LEGACY(reelscroll3_w)
386		AM_RANGE(0xb540, 0xb57f) AM_RAM_WRITE_LEGACY(reelscroll3_w)
387		AM_RANGE(0xb580, 0xb5bf) AM_RAM_WRITE_LEGACY(reelscroll3_w)
388		AM_RANGE(0xb5c0, 0xb5ff) AM_RAM_WRITE_LEGACY(reelscroll3_w)
	384	AM_RANGE(0xb400, 0xb43f) AM_RAM_WRITE(reelscroll3_w) AM_BASE(m_reelscroll3)
	385	AM_RANGE(0xb440, 0xb47f) AM_RAM_WRITE(reelscroll3_w)
	386	AM_RANGE(0xb480, 0xb4bf) AM_RAM_WRITE(reelscroll3_w)
	387	AM_RANGE(0xb4c0, 0xb4ff) AM_RAM_WRITE(reelscroll3_w)
	388	AM_RANGE(0xb500, 0xb53f) AM_RAM_WRITE(reelscroll3_w)
	389	AM_RANGE(0xb540, 0xb57f) AM_RAM_WRITE(reelscroll3_w)
	390	AM_RANGE(0xb580, 0xb5bf) AM_RAM_WRITE(reelscroll3_w)
	391	AM_RANGE(0xb5c0, 0xb5ff) AM_RAM_WRITE(reelscroll3_w)
389	392
390		AM_RANGE(0xb600, 0xb63f) AM_RAM_WRITE_LEGACY(reelscroll4_w) AM_BASE(m_reelscroll4)
391		AM_RANGE(0xb640, 0xb67f) AM_RAM_WRITE_LEGACY(reelscroll4_w)
392		AM_RANGE(0xb680, 0xb6bf) AM_RAM_WRITE_LEGACY(reelscroll4_w)
393		AM_RANGE(0xb6c0, 0xb6ff) AM_RAM_WRITE_LEGACY(reelscroll4_w)
394		AM_RANGE(0xb700, 0xb73f) AM_RAM_WRITE_LEGACY(reelscroll4_w)
395		AM_RANGE(0xb740, 0xb77f) AM_RAM_WRITE_LEGACY(reelscroll4_w)
396		AM_RANGE(0xb780, 0xb7bf) AM_RAM_WRITE_LEGACY(reelscroll4_w)
397		AM_RANGE(0xb7c0, 0xb7ff) AM_RAM_WRITE_LEGACY(reelscroll4_w)
	393	AM_RANGE(0xb600, 0xb63f) AM_RAM_WRITE(reelscroll4_w) AM_BASE(m_reelscroll4)
	394	AM_RANGE(0xb640, 0xb67f) AM_RAM_WRITE(reelscroll4_w)
	395	AM_RANGE(0xb680, 0xb6bf) AM_RAM_WRITE(reelscroll4_w)
	396	AM_RANGE(0xb6c0, 0xb6ff) AM_RAM_WRITE(reelscroll4_w)
	397	AM_RANGE(0xb700, 0xb73f) AM_RAM_WRITE(reelscroll4_w)
	398	AM_RANGE(0xb740, 0xb77f) AM_RAM_WRITE(reelscroll4_w)
	399	AM_RANGE(0xb780, 0xb7bf) AM_RAM_WRITE(reelscroll4_w)
	400	AM_RANGE(0xb7c0, 0xb7ff) AM_RAM_WRITE(reelscroll4_w)
398	401
399	402	AM_RANGE(0xc000, 0xffff) AM_ROM
400	403	ADDRESS_MAP_END
r14845	r14846
406	409	AM_RANGE(0x00, 0x03) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)   /* Input Ports */
407	410	AM_RANGE(0x10, 0x13) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)   /* Input Ports */
408	411
409		AM_RANGE(0x20, 0x20) AM_WRITE_LEGACY(skylncr_coin_w )
	412	AM_RANGE(0x20, 0x20) AM_WRITE(skylncr_coin_w )
410	413
411	414	AM_RANGE(0x30, 0x31) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w )
412	415	AM_RANGE(0x31, 0x31) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
413	416
414		AM_RANGE(0x40, 0x41) AM_WRITE_LEGACY(skylncr_paletteram_w )
415		AM_RANGE(0x50, 0x51) AM_WRITE_LEGACY(skylncr_paletteram2_w )
	417	AM_RANGE(0x40, 0x41) AM_WRITE(skylncr_paletteram_w )
	418	AM_RANGE(0x50, 0x51) AM_WRITE(skylncr_paletteram2_w )
416	419
417		AM_RANGE(0x70, 0x70) AM_WRITE_LEGACY(skylncr_nmi_enable_w )
	420	AM_RANGE(0x70, 0x70) AM_WRITE(skylncr_nmi_enable_w )
418	421	ADDRESS_MAP_END
419	422
420	423

src/mame/drivers/nyny.c

r14845	r14846
111	111	pia6821_device *m_pia1;
112	112	pia6821_device *m_pia2;
113	113	pen_t m_pens[NUM_PENS];
	114	DECLARE_WRITE8_MEMBER(audio_1_command_w);
	115	DECLARE_WRITE8_MEMBER(audio_1_answer_w);
	116	DECLARE_WRITE8_MEMBER(audio_2_command_w);
	117	DECLARE_READ8_MEMBER(nyny_pia_1_2_r);
	118	DECLARE_WRITE8_MEMBER(nyny_pia_1_2_w);
114	119	};
115	120
116	121
r14845	r14846
121	126	*************************************/
122	127
123	128	static WRITE_LINE_DEVICE_HANDLER( flipscreen_w );
124		static WRITE8_HANDLER( audio_2_command_w );
125	129
126	130
	131
127	132	/*************************************
128	133	*
129	134	*  Interrupt generation
r14845	r14846
214	219	state->m_star_enable = data & 0x10;
215	220
216	221	/* bits 5-7 go to the music board connector */
217		audio_2_command_w(state->m_maincpu->memory().space(AS_PROGRAM), 0, data & 0xe0);
	222	state->audio_2_command_w(*state->m_maincpu->memory().space(AS_PROGRAM), 0, data & 0xe0);
218	223	}
219	224
220	225
r14845	r14846
434	439	*
435	440	*************************************/
436	441
437		static WRITE8_HANDLER( audio_1_command_w )
	442	WRITE8_MEMBER(nyny_state::audio_1_command_w)
438	443	{
439		nyny_state *state = space->machine().driver_data<nyny_state>();
440	444
441	445	soundlatch_w(space, 0, data);
442		device_set_input_line(state->m_audiocpu, M6800_IRQ_LINE, HOLD_LINE);
	446	device_set_input_line(m_audiocpu, M6800_IRQ_LINE, HOLD_LINE);
443	447	}
444	448
445	449
446		static WRITE8_HANDLER( audio_1_answer_w )
	450	WRITE8_MEMBER(nyny_state::audio_1_answer_w)
447	451	{
448		nyny_state *state = space->machine().driver_data<nyny_state>();
449	452
450	453	soundlatch3_w(space, 0, data);
451		device_set_input_line(state->m_maincpu, M6809_IRQ_LINE, HOLD_LINE);
	454	device_set_input_line(m_maincpu, M6809_IRQ_LINE, HOLD_LINE);
452	455	}
453	456
454	457
r14845	r14846
489	492	*
490	493	*************************************/
491	494
492		static WRITE8_HANDLER( audio_2_command_w )
	495	WRITE8_MEMBER(nyny_state::audio_2_command_w)
493	496	{
494		nyny_state *state = space->machine().driver_data<nyny_state>();
495	497
496	498	soundlatch2_w(space, 0, (data & 0x60) >> 5);
497		device_set_input_line(state->m_audiocpu2, M6800_IRQ_LINE, BIT(data, 7) ? CLEAR_LINE : ASSERT_LINE);
	499	device_set_input_line(m_audiocpu2, M6800_IRQ_LINE, BIT(data, 7) ? CLEAR_LINE : ASSERT_LINE);
498	500	}
499	501
500	502
r14845	r14846
505	507	*
506	508	*************************************/
507	509
508		static READ8_HANDLER( nyny_pia_1_2_r )
	510	READ8_MEMBER(nyny_state::nyny_pia_1_2_r)
509	511	{
510		nyny_state *state = space->machine().driver_data<nyny_state>();
511	512	UINT8 ret = 0;
512	513
513	514	/* the address bits are directly connected to the chip selects */
514		if (BIT(offset, 2))  ret = state->m_pia1->read(*memory_nonspecific_space(space->machine()), offset & 0x03);
515		if (BIT(offset, 3))  ret = state->m_pia2->read_alt(*memory_nonspecific_space(space->machine()), offset & 0x03);
	515	if (BIT(offset, 2))  ret = m_pia1->read(space, offset & 0x03);
	516	if (BIT(offset, 3))  ret = m_pia2->read_alt(space, offset & 0x03);
516	517
517	518	return ret;
518	519	}
519	520
520	521
521		static WRITE8_HANDLER( nyny_pia_1_2_w )
	522	WRITE8_MEMBER(nyny_state::nyny_pia_1_2_w)
522	523	{
523		nyny_state *state = space->machine().driver_data<nyny_state>();
524	524
525	525	/* the address bits are directly connected to the chip selects */
526		if (BIT(offset, 2))  state->m_pia1->write(*memory_nonspecific_space(space->machine()), offset & 0x03, data);
527		if (BIT(offset, 3))  state->m_pia2->write_alt(*memory_nonspecific_space(space->machine()), offset & 0x03, data);
	526	if (BIT(offset, 2))  m_pia1->write(space, offset & 0x03, data);
	527	if (BIT(offset, 3))  m_pia2->write_alt(space, offset & 0x03, data);
528	528	}
529	529
530	530
r14845	r14846
537	537	AM_RANGE(0xa000, 0xa0ff) AM_RAM AM_SHARE("nvram") /* SRAM (coin counter, shown when holding F2) */
538	538	AM_RANGE(0xa100, 0xa100) AM_MIRROR(0x00fe) AM_DEVWRITE("crtc", mc6845_device, address_w)
539	539	AM_RANGE(0xa101, 0xa101) AM_MIRROR(0x00fe) AM_DEVWRITE("crtc", mc6845_device, register_w)
540		AM_RANGE(0xa200, 0xa20f) AM_MIRROR(0x00f0) AM_READWRITE_LEGACY(nyny_pia_1_2_r, nyny_pia_1_2_w)
541		AM_RANGE(0xa300, 0xa300) AM_MIRROR(0x00ff) AM_READWRITE_LEGACY(soundlatch3_r, audio_1_command_w)
	540	AM_RANGE(0xa200, 0xa20f) AM_MIRROR(0x00f0) AM_READWRITE(nyny_pia_1_2_r, nyny_pia_1_2_w)
	541	AM_RANGE(0xa300, 0xa300) AM_MIRROR(0x00ff) AM_READ_LEGACY(soundlatch3_r) AM_WRITE(audio_1_command_w)
542	542	AM_RANGE(0xa400, 0xa7ff) AM_NOP
543	543	AM_RANGE(0xa800, 0xbfff) AM_ROM
544	544	AM_RANGE(0xc000, 0xdfff) AM_RAM
r14845	r14846
550	550	ADDRESS_MAP_GLOBAL_MASK(0x7fff)
551	551	AM_RANGE(0x0000, 0x007f) AM_RAM      /* internal RAM */
552	552	AM_RANGE(0x0080, 0x0fff) AM_NOP
553		AM_RANGE(0x1000, 0x1000) AM_MIRROR(0x0fff) AM_READWRITE_LEGACY(soundlatch_r, audio_1_answer_w)
	553	AM_RANGE(0x1000, 0x1000) AM_MIRROR(0x0fff) AM_READ_LEGACY(soundlatch_r) AM_WRITE(audio_1_answer_w)
554	554	AM_RANGE(0x2000, 0x2000) AM_MIRROR(0x0fff) AM_READ_PORT("SW3")
555	555	AM_RANGE(0x3000, 0x3000) AM_MIRROR(0x0ffc) AM_DEVREAD_LEGACY("ay1", ay8910_r)
556	556	AM_RANGE(0x3000, 0x3001) AM_MIRROR(0x0ffc) AM_DEVWRITE_LEGACY("ay1", ay8910_data_address_w)

src/mame/drivers/limenko.c

r14845	r14846
52	52	bitmap_ind8 m_sprites_bitmap_pri;
53	53	int m_prev_sprites_count;
54	54	UINT8 m_spotty_sound_cmd;
	55	DECLARE_WRITE32_MEMBER(limenko_coincounter_w);
	56	DECLARE_WRITE32_MEMBER(limenko_paletteram_w);
	57	DECLARE_WRITE32_MEMBER(bg_videoram_w);
	58	DECLARE_WRITE32_MEMBER(md_videoram_w);
	59	DECLARE_WRITE32_MEMBER(fg_videoram_w);
	60	DECLARE_WRITE32_MEMBER(spotty_soundlatch_w);
	61	DECLARE_WRITE32_MEMBER(spriteram_buffer_w);
	62	DECLARE_WRITE8_MEMBER(spotty_sound_cmd_w);
	63	DECLARE_READ8_MEMBER(spotty_sound_cmd_r);
	64	DECLARE_READ8_MEMBER(spotty_sound_r);
	65	DECLARE_READ32_MEMBER(dynabomb_speedup_r);
	66	DECLARE_READ32_MEMBER(legendoh_speedup_r);
	67	DECLARE_READ32_MEMBER(sb2003_speedup_r);
	68	DECLARE_READ32_MEMBER(spotty_speedup_r);
55	69	};
56	70
57	71
r14845	r14846
61	75	MISC FUNCTIONS
62	76	*****************************************************************************************************/
63	77
64		static WRITE32_HANDLER( limenko_coincounter_w )
	78	WRITE32_MEMBER(limenko_state::limenko_coincounter_w)
65	79	{
66		coin_counter_w(space->machine(),0,data & 0x10000);
	80	coin_counter_w(machine(),0,data & 0x10000);
67	81	}
68	82
69		static WRITE32_HANDLER( limenko_paletteram_w )
	83	WRITE32_MEMBER(limenko_state::limenko_paletteram_w)
70	84	{
71	85	UINT16 paldata;
72		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
	86	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
73	87
74	88	if(ACCESSING_BITS_0_15)
75	89	{
76		paldata = space->machine().generic.paletteram.u32[offset] & 0x7fff;
77		palette_set_color_rgb(space->machine(), offset * 2 + 1, pal5bit(paldata >> 0), pal5bit(paldata >> 5), pal5bit(paldata >> 10));
	90	paldata = machine().generic.paletteram.u32[offset] & 0x7fff;
	91	palette_set_color_rgb(machine(), offset * 2 + 1, pal5bit(paldata >> 0), pal5bit(paldata >> 5), pal5bit(paldata >> 10));
78	92	}
79	93
80	94	if(ACCESSING_BITS_16_31)
81	95	{
82		paldata = (space->machine().generic.paletteram.u32[offset] >> 16) & 0x7fff;
83		palette_set_color_rgb(space->machine(), offset * 2 + 0, pal5bit(paldata >> 0), pal5bit(paldata >> 5), pal5bit(paldata >> 10));
	96	paldata = (machine().generic.paletteram.u32[offset] >> 16) & 0x7fff;
	97	palette_set_color_rgb(machine(), offset * 2 + 0, pal5bit(paldata >> 0), pal5bit(paldata >> 5), pal5bit(paldata >> 10));
84	98	}
85	99	}
86	100
87		static WRITE32_HANDLER( bg_videoram_w )
	101	WRITE32_MEMBER(limenko_state::bg_videoram_w)
88	102	{
89		limenko_state *state = space->machine().driver_data<limenko_state>();
90		COMBINE_DATA(&state->m_bg_videoram[offset]);
91		state->m_bg_tilemap->mark_tile_dirty(offset);
	103	COMBINE_DATA(&m_bg_videoram[offset]);
	104	m_bg_tilemap->mark_tile_dirty(offset);
92	105	}
93	106
94		static WRITE32_HANDLER( md_videoram_w )
	107	WRITE32_MEMBER(limenko_state::md_videoram_w)
95	108	{
96		limenko_state *state = space->machine().driver_data<limenko_state>();
97		COMBINE_DATA(&state->m_md_videoram[offset]);
98		state->m_md_tilemap->mark_tile_dirty(offset);
	109	COMBINE_DATA(&m_md_videoram[offset]);
	110	m_md_tilemap->mark_tile_dirty(offset);
99	111	}
100	112
101		static WRITE32_HANDLER( fg_videoram_w )
	113	WRITE32_MEMBER(limenko_state::fg_videoram_w)
102	114	{
103		limenko_state *state = space->machine().driver_data<limenko_state>();
104		COMBINE_DATA(&state->m_fg_videoram[offset]);
105		state->m_fg_tilemap->mark_tile_dirty(offset);
	115	COMBINE_DATA(&m_fg_videoram[offset]);
	116	m_fg_tilemap->mark_tile_dirty(offset);
106	117	}
107	118
108		static WRITE32_HANDLER( spotty_soundlatch_w )
	119	WRITE32_MEMBER(limenko_state::spotty_soundlatch_w)
109	120	{
110	121	soundlatch_w(space, 0, (data >> 16) & 0xff);
111	122	}
r14845	r14846
116	127	return state->m_spriteram_bit;
117	128	}
118	129
119		static WRITE32_HANDLER( spriteram_buffer_w )
	130	WRITE32_MEMBER(limenko_state::spriteram_buffer_w)
120	131	{
121		limenko_state *state = space->machine().driver_data<limenko_state>();
122	132	rectangle clip(0, 383, 0, 239);
123	133
124		state->m_sprites_bitmap_pri.fill(0, clip);
125		state->m_sprites_bitmap.fill(0, clip);
	134	m_sprites_bitmap_pri.fill(0, clip);
	135	m_sprites_bitmap.fill(0, clip);
126	136
127	137	// toggle spriterams location in the memory map
128		state->m_spriteram_bit ^= 1;
	138	m_spriteram_bit ^= 1;
129	139
130		if(state->m_spriteram_bit)
	140	if(m_spriteram_bit)
131	141	{
132	142	// draw the sprites to the frame buffer
133		draw_sprites(space->machine(),state->m_spriteram2,clip,state->m_prev_sprites_count);
	143	draw_sprites(machine(),m_spriteram2,clip,m_prev_sprites_count);
134	144	}
135	145	else
136	146	{
137	147	// draw the sprites to the frame buffer
138		draw_sprites(space->machine(),state->m_spriteram,clip,state->m_prev_sprites_count);
	148	draw_sprites(machine(),m_spriteram,clip,m_prev_sprites_count);
139	149	}
140	150
141	151	// buffer the next number of sprites to draw
142		state->m_prev_sprites_count = (state->m_videoreg[0] & 0x1ff0000) >> 16;
	152	m_prev_sprites_count = (m_videoreg[0] & 0x1ff0000) >> 16;
143	153	}
144	154
145	155	/*****************************************************************************************************
r14845	r14846
149	159	static ADDRESS_MAP_START( limenko_map, AS_PROGRAM, 32, limenko_state )
150	160	AM_RANGE(0x00000000, 0x001fffff) AM_RAM   AM_BASE(m_mainram)
151	161	AM_RANGE(0x40000000, 0x403fffff) AM_ROM AM_REGION("user2",0)
152		AM_RANGE(0x80000000, 0x80007fff) AM_RAM_WRITE_LEGACY(fg_videoram_w) AM_BASE(m_fg_videoram)
153		AM_RANGE(0x80008000, 0x8000ffff) AM_RAM_WRITE_LEGACY(md_videoram_w) AM_BASE(m_md_videoram)
154		AM_RANGE(0x80010000, 0x80017fff) AM_RAM_WRITE_LEGACY(bg_videoram_w) AM_BASE(m_bg_videoram)
	162	AM_RANGE(0x80000000, 0x80007fff) AM_RAM_WRITE(fg_videoram_w) AM_BASE(m_fg_videoram)
	163	AM_RANGE(0x80008000, 0x8000ffff) AM_RAM_WRITE(md_videoram_w) AM_BASE(m_md_videoram)
	164	AM_RANGE(0x80010000, 0x80017fff) AM_RAM_WRITE(bg_videoram_w) AM_BASE(m_bg_videoram)
155	165	AM_RANGE(0x80018000, 0x80018fff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
156	166	AM_RANGE(0x80019000, 0x80019fff) AM_RAM AM_BASE(m_spriteram2)
157		AM_RANGE(0x8001c000, 0x8001dfff) AM_RAM_WRITE_LEGACY(limenko_paletteram_w) AM_BASE_GENERIC(paletteram)
	167	AM_RANGE(0x8001c000, 0x8001dfff) AM_RAM_WRITE(limenko_paletteram_w) AM_BASE_GENERIC(paletteram)
158	168	AM_RANGE(0x8001e000, 0x8001ebff) AM_RAM // ? not used
159	169	AM_RANGE(0x8001ffec, 0x8001ffff) AM_RAM AM_BASE(m_videoreg)
160		AM_RANGE(0x8003e000, 0x8003e003) AM_WRITE_LEGACY(spriteram_buffer_w)
	170	AM_RANGE(0x8003e000, 0x8003e003) AM_WRITE(spriteram_buffer_w)
161	171	AM_RANGE(0xffe00000, 0xffffffff) AM_ROM AM_REGION("user1",0)
162	172	ADDRESS_MAP_END
163	173
r14845	r14846
165	175	AM_RANGE(0x0000, 0x0003) AM_READ_PORT("IN0")
166	176	AM_RANGE(0x0800, 0x0803) AM_READ_PORT("IN1")
167	177	AM_RANGE(0x1000, 0x1003) AM_READ_PORT("IN2")
168		AM_RANGE(0x4000, 0x4003) AM_WRITE_LEGACY(limenko_coincounter_w)
	178	AM_RANGE(0x4000, 0x4003) AM_WRITE(limenko_coincounter_w)
169	179	AM_RANGE(0x4800, 0x4803) AM_WRITE_PORT("EEPROMOUT")
170	180	AM_RANGE(0x5000, 0x5003) AM_WRITENOP // sound latch
171	181	ADDRESS_MAP_END
r14845	r14846
176	186	static ADDRESS_MAP_START( spotty_map, AS_PROGRAM, 32, limenko_state )
177	187	AM_RANGE(0x00000000, 0x001fffff) AM_RAM   AM_BASE(m_mainram)
178	188	AM_RANGE(0x40002000, 0x400024d3) AM_RAM //?
179		AM_RANGE(0x80000000, 0x80007fff) AM_RAM_WRITE_LEGACY(fg_videoram_w) AM_BASE(m_fg_videoram)
180		AM_RANGE(0x80008000, 0x8000ffff) AM_RAM_WRITE_LEGACY(md_videoram_w) AM_BASE(m_md_videoram)
181		AM_RANGE(0x80010000, 0x80017fff) AM_RAM_WRITE_LEGACY(bg_videoram_w) AM_BASE(m_bg_videoram)
	189	AM_RANGE(0x80000000, 0x80007fff) AM_RAM_WRITE(fg_videoram_w) AM_BASE(m_fg_videoram)
	190	AM_RANGE(0x80008000, 0x8000ffff) AM_RAM_WRITE(md_videoram_w) AM_BASE(m_md_videoram)
	191	AM_RANGE(0x80010000, 0x80017fff) AM_RAM_WRITE(bg_videoram_w) AM_BASE(m_bg_videoram)
182	192	AM_RANGE(0x80018000, 0x80018fff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
183	193	AM_RANGE(0x80019000, 0x80019fff) AM_RAM AM_BASE(m_spriteram2)
184		AM_RANGE(0x8001c000, 0x8001dfff) AM_RAM_WRITE_LEGACY(limenko_paletteram_w) AM_BASE_GENERIC(paletteram)
	194	AM_RANGE(0x8001c000, 0x8001dfff) AM_RAM_WRITE(limenko_paletteram_w) AM_BASE_GENERIC(paletteram)
185	195	AM_RANGE(0x8001e000, 0x8001ebff) AM_RAM // ? not used
186	196	AM_RANGE(0x8001ffec, 0x8001ffff) AM_RAM AM_BASE(m_videoreg)
187		AM_RANGE(0x8003e000, 0x8003e003) AM_WRITE_LEGACY(spriteram_buffer_w)
	197	AM_RANGE(0x8003e000, 0x8003e003) AM_WRITE(spriteram_buffer_w)
188	198	AM_RANGE(0xfff00000, 0xffffffff) AM_ROM AM_REGION("user1",0)
189	199	ADDRESS_MAP_END
190	200
r14845	r14846
194	204	AM_RANGE(0x0800, 0x0803) AM_WRITENOP // hopper related
195	205	AM_RANGE(0x1000, 0x1003) AM_READ_PORT("IN2")
196	206	AM_RANGE(0x4800, 0x4803) AM_WRITE_PORT("EEPROMOUT")
197		AM_RANGE(0x5000, 0x5003) AM_WRITE_LEGACY(spotty_soundlatch_w)
	207	AM_RANGE(0x5000, 0x5003) AM_WRITE(spotty_soundlatch_w)
198	208	ADDRESS_MAP_END
199	209
200		static WRITE8_HANDLER( spotty_sound_cmd_w )
	210	WRITE8_MEMBER(limenko_state::spotty_sound_cmd_w)
201	211	{
202		limenko_state *state = space->machine().driver_data<limenko_state>();
203		state->m_spotty_sound_cmd = data;
	212	m_spotty_sound_cmd = data;
204	213	}
205	214
206		static READ8_HANDLER( spotty_sound_cmd_r )
	215	READ8_MEMBER(limenko_state::spotty_sound_cmd_r)
207	216	{
208	217	return 0; //??? some status bit? if set it executes a jump in the code
209	218	}
210	219
211		static READ8_HANDLER( spotty_sound_r )
	220	READ8_MEMBER(limenko_state::spotty_sound_r)
212	221	{
213		limenko_state *state = space->machine().driver_data<limenko_state>();
214		// check state->m_spotty_sound_cmd bits...
	222	// check m_spotty_sound_cmd bits...
215	223
216		if(state->m_spotty_sound_cmd == 0xf7)
	224	if(m_spotty_sound_cmd == 0xf7)
217	225	return soundlatch_r(space,0);
218	226	else
219		return space->machine().device<okim6295_device>("oki")->read(*space,0);
	227	return machine().device<okim6295_device>("oki")->read(*&space,0);
220	228	}
221	229
222	230	static ADDRESS_MAP_START( spotty_sound_io_map, AS_IO, 8, limenko_state )
223		AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READ_LEGACY(spotty_sound_r) AM_DEVWRITE("oki", okim6295_device, write) //? sound latch and ?
224		AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE_LEGACY(spotty_sound_cmd_r, spotty_sound_cmd_w) //not sure about anything...
	231	AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READ(spotty_sound_r) AM_DEVWRITE("oki", okim6295_device, write) //? sound latch and ?
	232	AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(spotty_sound_cmd_r, spotty_sound_cmd_w) //not sure about anything...
225	233	ADDRESS_MAP_END
226	234
227	235	/*****************************************************************************************************
r14845	r14846
985	993
986	994
987	995
988		static READ32_HANDLER( dynabomb_speedup_r )
	996	READ32_MEMBER(limenko_state::dynabomb_speedup_r)
989	997	{
990		limenko_state *state = space->machine().driver_data<limenko_state>();
991		if(space->machine().firstcpu->pc() == 0xc25b8)
	998	if(machine().firstcpu->pc() == 0xc25b8)
992	999	{
993		space->machine().firstcpu->eat_cycles(50);
	1000	machine().firstcpu->eat_cycles(50);
994	1001	}
995	1002
996		return state->m_mainram[0xe2784/4];
	1003	return m_mainram[0xe2784/4];
997	1004	}
998	1005
999		static READ32_HANDLER( legendoh_speedup_r )
	1006	READ32_MEMBER(limenko_state::legendoh_speedup_r)
1000	1007	{
1001		limenko_state *state = space->machine().driver_data<limenko_state>();
1002		if(space->machine().firstcpu->pc() == 0x23e32)
	1008	if(machine().firstcpu->pc() == 0x23e32)
1003	1009	{
1004		space->machine().firstcpu->eat_cycles(50);
	1010	machine().firstcpu->eat_cycles(50);
1005	1011	}
1006	1012
1007		return state->m_mainram[0x32ab0/4];
	1013	return m_mainram[0x32ab0/4];
1008	1014	}
1009	1015
1010		static READ32_HANDLER( sb2003_speedup_r )
	1016	READ32_MEMBER(limenko_state::sb2003_speedup_r)
1011	1017	{
1012		limenko_state *state = space->machine().driver_data<limenko_state>();
1013		if(space->machine().firstcpu->pc() == 0x26da4)
	1018	if(machine().firstcpu->pc() == 0x26da4)
1014	1019	{
1015		space->machine().firstcpu->eat_cycles(50);
	1020	machine().firstcpu->eat_cycles(50);
1016	1021	}
1017	1022
1018		return state->m_mainram[0x135800/4];
	1023	return m_mainram[0x135800/4];
1019	1024	}
1020	1025
1021		static READ32_HANDLER( spotty_speedup_r )
	1026	READ32_MEMBER(limenko_state::spotty_speedup_r)
1022	1027	{
1023		limenko_state *state = space->machine().driver_data<limenko_state>();
1024		if(space->machine().firstcpu->pc() == 0x8560)
	1028	if(machine().firstcpu->pc() == 0x8560)
1025	1029	{
1026		space->machine().firstcpu->eat_cycles(50);
	1030	machine().firstcpu->eat_cycles(50);
1027	1031	}
1028	1032
1029		return state->m_mainram[0x6626c/4];
	1033	return m_mainram[0x6626c/4];
1030	1034	}
1031	1035
1032	1036	static DRIVER_INIT( dynabomb )
1033	1037	{
1034	1038	limenko_state *state = machine.driver_data<limenko_state>();
1035		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xe2784, 0xe2787, FUNC(dynabomb_speedup_r) );
	1039	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0xe2784, 0xe2787, read32_delegate(FUNC(limenko_state::dynabomb_speedup_r), state));
1036	1040
1037	1041	state->m_spriteram_bit = 1;
1038	1042	}
r14845	r14846
1040	1044	static DRIVER_INIT( legendoh )
1041	1045	{
1042	1046	limenko_state *state = machine.driver_data<limenko_state>();
1043		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x32ab0, 0x32ab3, FUNC(legendoh_speedup_r) );
	1047	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x32ab0, 0x32ab3, read32_delegate(FUNC(limenko_state::legendoh_speedup_r), state));
1044	1048
1045	1049	state->m_spriteram_bit = 1;
1046	1050	}
r14845	r14846
1048	1052	static DRIVER_INIT( sb2003 )
1049	1053	{
1050	1054	limenko_state *state = machine.driver_data<limenko_state>();
1051		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x135800, 0x135803, FUNC(sb2003_speedup_r) );
	1055	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x135800, 0x135803, read32_delegate(FUNC(limenko_state::sb2003_speedup_r), state));
1052	1056
1053	1057	state->m_spriteram_bit = 1;
1054	1058	}
r14845	r14846
1069	1073	dst[x+2] = (src[x+1]&0x0f) >> 0;
1070	1074	}
1071	1075
1072		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x6626c, 0x6626f, FUNC(spotty_speedup_r) );
	1076	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x6626c, 0x6626f, read32_delegate(FUNC(limenko_state::spotty_speedup_r), state));
1073	1077
1074	1078	state->m_spriteram_bit = 1;
1075	1079	}

src/mame/drivers/bfm_sc4.c

r14845	r14846
65	65	UINT16* m_mainram;
66	66	// devices
67	67	required_device<cpu_device> m_maincpu;
	68	DECLARE_READ16_MEMBER(sc4_mem_r);
	69	DECLARE_WRITE16_MEMBER(sc4_mem_w);
68	70	};
69	71
70	72	class sc4_adder4_state : public sc4_state
r14845	r14846
79	81	required_device<cpu_device> m_adder4cpu;
80	82	};
81	83
82		static READ16_HANDLER( sc4_mem_r )
	84	READ16_MEMBER(sc4_state::sc4_mem_r)
83	85	{
84		sc4_state *state = space->machine().driver_data<sc4_state>();
85		int pc = cpu_get_pc(&space->device());
86		int cs = m68307_get_cs(state->m_maincpu, offset * 2);
	86	int pc = cpu_get_pc(&space.device());
	87	int cs = m68307_get_cs(m_maincpu, offset * 2);
87	88	int base = 0, end = 0;
88		//   if (!(space->debugger_access())) printf("cs is %d\n", cs);
	89	//   if (!(debugger_access())) printf("cs is %d\n", cs);
89	90
90	91	switch ( cs )
91	92	{
92	93	case 1:
93	94	if (offset<0x100000/2)
94		return state->m_cpuregion[offset];
	95	return m_cpuregion[offset];
95	96	else
96	97	logerror("%08x maincpu read access offset %08x mem_mask %04x cs %d\n", pc, offset*2, mem_mask, cs);
97	98	break;
r14845	r14846
103	104	if ((offset>=base) && (offset<end))
104	105	{
105	106	offset-=base;
106		return(state->m_mainram[offset]);
	107	return(m_mainram[offset]);
107	108	}
108	109	else
109	110	{
r14845	r14846
129	130	return 0x0000;
130	131	}
131	132
132		static WRITE16_HANDLER( sc4_mem_w )
	133	WRITE16_MEMBER(sc4_state::sc4_mem_w)
133	134	{
134		sc4_state *state = space->machine().driver_data<sc4_state>();
135		int pc = cpu_get_pc(&space->device());
136		int cs = m68307_get_cs(state->m_maincpu, offset * 2);
	135	int pc = cpu_get_pc(&space.device());
	136	int cs = m68307_get_cs(m_maincpu, offset * 2);
137	137	int base = 0, end = 0;
138	138
139	139	switch ( cs )
r14845	r14846
153	153	if ((offset>=base) && (offset<end))
154	154	{
155	155	offset-=base;
156		COMBINE_DATA(&state->m_mainram[offset]);
	156	COMBINE_DATA(&m_mainram[offset]);
157	157	}
158	158	else
159	159	{
r14845	r14846
174	174	}
175	175	}
176	176
177		static ADDRESS_MAP_START( sc4_map, AS_PROGRAM, 16, sc4_adder4_state )
178		AM_RANGE(0x000000000, 0xffffffff) AM_READWRITE_LEGACY(sc4_mem_r, sc4_mem_w)
	177	static ADDRESS_MAP_START( sc4_map, AS_PROGRAM, 16, sc4_state )
	178	AM_RANGE(0x000000000, 0xffffffff) AM_READWRITE(sc4_mem_r, sc4_mem_w)
179	179	ADDRESS_MAP_END
180	180
181	181	static ADDRESS_MAP_START( sc4_adder4_map, AS_PROGRAM, 32, sc4_adder4_state )

src/mame/drivers/paranoia.c

r14845	r14846
36	36	#include "emu.h"
37	37	#include "cpu/z80/z80.h"
38	38	#include "cpu/i8085/i8085.h"
	39	#include "machine/i8155.h"
39	40	#include "machine/pcecommn.h"
40	41	#include "video/vdc.h"
41	42	#include "cpu/h6280/h6280.h"
r14845	r14846
48	49	paranoia_state(const machine_config &mconfig, device_type type, const char *tag)
49	50	: driver_device(mconfig, type, tag) { }
50	51
	52	DECLARE_WRITE8_MEMBER(paranoia_8085_d000_w);
	53	DECLARE_READ8_MEMBER(paranoia_z80_io_01_r);
	54	DECLARE_READ8_MEMBER(paranoia_z80_io_02_r);
	55	DECLARE_WRITE8_MEMBER(paranoia_z80_io_17_w);
	56	DECLARE_WRITE8_MEMBER(paranoia_z80_io_37_w);
51	57	};
52	58
53	59
r14845	r14846
78	84	AM_RANGE( 0x00, 0x03) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w )
79	85	ADDRESS_MAP_END
80	86
81		static WRITE8_HANDLER( paranoia_8085_d000_w )
	87	WRITE8_MEMBER(paranoia_state::paranoia_8085_d000_w)
82	88	{
83	89	//logerror( "D000 (8085) write %02x\n", data );
84	90	}
85	91
86		static WRITE8_HANDLER( paranoia_8085_8155_w )
87		{
88		switch( offset )
89		{
90		case 0: logerror( "8155 Command register write %x, timer command = %x, interrupt enable = %x, ports = %x\n", data, (data >> 6) & 3, (data >> 4) & 3, data & 0xf ); break;
91		case 1: logerror( "8155 I/O Port A write %x\n", data ); break;
92		case 2: logerror( "8155 I/O Port B write %x\n", data ); break;
93		case 3: logerror( "8155 I/O Port C (or control) write %x\n", data ); break;
94		case 4: logerror( "8155 Timer low 8 bits write %x\n", data ); break;
95		case 5: logerror( "8155 Timer high 6 bits write %x, timer mode %x\n", data & 0x3f, (data >> 6) & 3); break;
96		}
97		}
98
99	92	static ADDRESS_MAP_START(paranoia_8085_map, AS_PROGRAM, 8, paranoia_state )
100	93	AM_RANGE( 0x0000, 0x7fff) AM_ROM
101		AM_RANGE( 0x8000, 0x80ff) AM_RAM
102		AM_RANGE( 0x8100, 0x8105) AM_WRITE_LEGACY(paranoia_8085_8155_w )
103		AM_RANGE( 0xd000, 0xd000) AM_WRITE_LEGACY(paranoia_8085_d000_w )
	94	AM_RANGE( 0x8000, 0x80ff) AM_DEVREADWRITE("i8155", i8155_device, memory_r, memory_w)
	95	AM_RANGE( 0x8100, 0x8107) AM_DEVREADWRITE("i8155", i8155_device, io_r, io_w)
	96	AM_RANGE( 0xd000, 0xd000) AM_WRITE(paranoia_8085_d000_w )
104	97	AM_RANGE( 0xe000, 0xe1ff) AM_RAM
105	98	ADDRESS_MAP_END
106	99
r14845	r14846
113	106	AM_RANGE( 0x7000, 0x73ff) AM_RAM
114	107	ADDRESS_MAP_END
115	108
116		static READ8_HANDLER(paranoia_z80_io_01_r)
	109	READ8_MEMBER(paranoia_state::paranoia_z80_io_01_r)
117	110	{
118	111	return 0;
119	112	}
120	113
121		static READ8_HANDLER(paranoia_z80_io_02_r)
	114	READ8_MEMBER(paranoia_state::paranoia_z80_io_02_r)
122	115	{
123	116	return 0;
124	117	}
125	118
126		static WRITE8_HANDLER(paranoia_z80_io_17_w)
	119	WRITE8_MEMBER(paranoia_state::paranoia_z80_io_17_w)
127	120	{
128	121	}
129	122
130		static WRITE8_HANDLER(paranoia_z80_io_37_w)
	123	WRITE8_MEMBER(paranoia_state::paranoia_z80_io_37_w)
131	124	{
132	125	}
133	126
134	127	static ADDRESS_MAP_START(paranoia_z80_io_map, AS_IO, 8, paranoia_state )
135	128	ADDRESS_MAP_GLOBAL_MASK(0xff)
136		AM_RANGE( 0x01, 0x01 ) AM_READ_LEGACY(paranoia_z80_io_01_r )
137		AM_RANGE( 0x02, 0x02 ) AM_READ_LEGACY(paranoia_z80_io_02_r )
138		AM_RANGE( 0x17, 0x17 ) AM_WRITE_LEGACY(paranoia_z80_io_17_w )
139		AM_RANGE( 0x37, 0x37 ) AM_WRITE_LEGACY(paranoia_z80_io_37_w )
	129	AM_RANGE( 0x01, 0x01 ) AM_READ(paranoia_z80_io_01_r )
	130	AM_RANGE( 0x02, 0x02 ) AM_READ(paranoia_z80_io_02_r )
	131	AM_RANGE( 0x17, 0x17 ) AM_WRITE(paranoia_z80_io_17_w )
	132	AM_RANGE( 0x37, 0x37 ) AM_WRITE(paranoia_z80_io_37_w )
140	133	ADDRESS_MAP_END
141	134
	135	static WRITE8_DEVICE_HANDLER(paranoia_i8155_a_w)
	136	{
	137	//logerror("i8155 Port A: %02X\n", data);
	138	}
	139
	140	static WRITE8_DEVICE_HANDLER(paranoia_i8155_b_w)
	141	{
	142	//logerror("i8155 Port B: %02X\n", data);
	143	}
	144
	145	static WRITE8_DEVICE_HANDLER(paranoia_i8155_c_w)
	146	{
	147	//logerror("i8155 Port C: %02X\n", data);
	148	}
	149
	150	static WRITE_LINE_DEVICE_HANDLER(paranoia_i8155_timer_out)
	151	{
	152	//cputag_set_input_line(device->machine(), "sub", I8085_RST55_LINE, state ? CLEAR_LINE : ASSERT_LINE );
	153	//logerror("Timer out %d\n", state);
	154	}
	155
	156	static I8155_INTERFACE(i8155_intf)
	157	{
	158	// all ports set to output
	159	DEVCB_NULL,
	160	DEVCB_HANDLER(paranoia_i8155_a_w),
	161	DEVCB_NULL,
	162	DEVCB_HANDLER(paranoia_i8155_b_w),
	163	DEVCB_NULL,
	164	DEVCB_HANDLER(paranoia_i8155_c_w),
	165	DEVCB_LINE(paranoia_i8155_timer_out)
	166	};
	167
142	168	static const c6280_interface c6280_config =
143	169	{
144	170	"maincpu"
r14845	r14846
161	187	MCFG_CPU_PROGRAM_MAP(paranoia_z80_map)
162	188	MCFG_CPU_IO_MAP(paranoia_z80_io_map)
163	189
	190	MCFG_I8155_ADD("i8155", 1000000 /*?*/, i8155_intf)
	191
164	192	/* video hardware */
165	193
166	194	MCFG_SCREEN_ADD("screen", RASTER)

src/mame/drivers/galgame.c

r14845	r14846
37	37	int m_point_work_list_index;
38	38	int m_point_display_list_index;
39	39	int m_interrupt;
	40	DECLARE_READ16_MEMBER(ke_r);
	41	DECLARE_WRITE16_MEMBER(ke_w);
	42	DECLARE_READ16_MEMBER(x_r);
	43	DECLARE_WRITE16_MEMBER(x_w);
	44	DECLARE_READ16_MEMBER(y_r);
	45	DECLARE_WRITE16_MEMBER(y_w);
	46	DECLARE_WRITE16_MEMBER(clk_w);
40	47	};
41	48
42	49	/*************************************
r14845	r14846
45	52	*
46	53	*************************************/
47	54
48		static READ16_HANDLER(ke_r)
	55	READ16_MEMBER(galaxygame_state::ke_r)
49	56	{
50		galaxygame_state *state = space->machine().driver_data<galaxygame_state>();
51	57
52	58	UINT16 ret;
53	59
r14845	r14846
57	63	ret = 0;
58	64	break;
59	65	case 1: // AC
60		ret = state->m_ac;
	66	ret = m_ac;
61	67	break;
62	68	case 2: // MQ
63		ret = state->m_mq;
	69	ret = m_mq;
64	70	break;
65	71	case 7: // ASH
66	72	ret = 0;
r14845	r14846
73	79	return ret;
74	80	}
75	81
76		static WRITE16_HANDLER(ke_w)
	82	WRITE16_MEMBER(galaxygame_state::ke_w)
77	83	{
78		galaxygame_state *state = space->machine().driver_data<galaxygame_state>();
79	84
80	85	switch( offset )
81	86	{
r14845	r14846
83	88	{
84	89	if ( data != 0 )
85	90	{
86		INT32 dividend = (INT32)((UINT32)((UINT16)state->m_ac << 16) | (UINT16)(state->m_mq));
87		state->m_mq = dividend / (INT16)data;
88		state->m_ac = dividend % (INT16)data;
	91	INT32 dividend = (INT32)((UINT32)((UINT16)m_ac << 16) | (UINT16)(m_mq));
	92	m_mq = dividend / (INT16)data;
	93	m_ac = dividend % (INT16)data;
89	94	}
90	95	else
91	96	{
92		state->m_mq = 0;
93		state->m_ac = 0;
	97	m_mq = 0;
	98	m_ac = 0;
94	99	}
95	100	}
96	101	break;
97	102	case 1: // AC
98		state->m_ac = (INT16)data;
	103	m_ac = (INT16)data;
99	104	break;
100	105	case 2: // MQ
101		state->m_mq = (INT16)data;
102		if (state->m_mq < 0)
	106	m_mq = (INT16)data;
	107	if (m_mq < 0)
103	108	{
104		state->m_ac = -1;
	109	m_ac = -1;
105	110	}
106	111	else
107	112	{
108		state->m_ac = 0;
	113	m_ac = 0;
109	114	}
110	115	break;
111	116	case 3: // X
112	117	{
113		INT32 mulres = (INT32)state->m_mq*(INT32)(INT16)data;
114		state->m_ac = mulres >> 16;
115		state->m_mq = mulres & 0xffff;
	118	INT32 mulres = (INT32)m_mq*(INT32)(INT16)data;
	119	m_ac = mulres >> 16;
	120	m_mq = mulres & 0xffff;
116	121	}
117	122	break;
118	123	case 6: // LSH
119	124	{
120	125	data &= 63;
121		INT32 val = (INT32)((UINT32)((UINT16)state->m_ac << 16) | (UINT16)(state->m_mq));
	126	INT32 val = (INT32)((UINT32)((UINT16)m_ac << 16) | (UINT16)(m_mq));
122	127	if ( data < 32 )
123	128	{
124	129	val = val << data;
r14845	r14846
127	132	{
128	133	val = val >> (64 - data);
129	134	}
130		state->m_mq = val & 0xffff;
131		state->m_ac = (val >> 16) & 0xffff;
	135	m_mq = val & 0xffff;
	136	m_ac = (val >> 16) & 0xffff;
132	137	}
133	138	break;
134	139	case 7: // ASH
135	140	{
136	141	data &= 63;
137		INT32 val = (INT32)((UINT32)((UINT16)state->m_ac << 16) | (UINT16)(state->m_mq));
	142	INT32 val = (INT32)((UINT32)((UINT16)m_ac << 16) | (UINT16)(m_mq));
138	143	if ( data < 32 )
139	144	{
140	145	val = val << data;
r14845	r14846
143	148	{
144	149	val = val >> (64 - data);
145	150	}
146		state->m_mq = val & 0xffff;
147		state->m_ac = (val >> 16) & 0xffff;
	151	m_mq = val & 0xffff;
	152	m_ac = (val >> 16) & 0xffff;
148	153	}
149	154	break;
150	155	default:
r14845	r14846
171	176	return 0;
172	177	}
173	178
174		static READ16_HANDLER(x_r)
	179	READ16_MEMBER(galaxygame_state::x_r)
175	180	{
176		galaxygame_state *state = space->machine().driver_data<galaxygame_state>();
177		return state->m_x;
	181	return m_x;
178	182	}
179	183
180		static WRITE16_HANDLER(x_w)
	184	WRITE16_MEMBER(galaxygame_state::x_w)
181	185	{
182		galaxygame_state *state = space->machine().driver_data<galaxygame_state>();
183		state->m_x = data;
	186	m_x = data;
184	187	}
185	188
186		static READ16_HANDLER(y_r)
	189	READ16_MEMBER(galaxygame_state::y_r)
187	190	{
188		galaxygame_state *state = space->machine().driver_data<galaxygame_state>();
189		return state->m_y;
	191	return m_y;
190	192	}
191	193
192		static WRITE16_HANDLER(y_w)
	194	WRITE16_MEMBER(galaxygame_state::y_w)
193	195	{
194		galaxygame_state *state = space->machine().driver_data<galaxygame_state>();
195		state->m_y = data;
	196	m_y = data;
196	197	if ( data == 0x0101 )
197	198	{
198	199	// send points list to display device
199	200	// seems to happen on first 0x0101 write after interrupt
200		if ( state->m_interrupt )
	201	if ( m_interrupt )
201	202	{
202		for ( int i = 0; i < state->m_point_work_list_index ; i++ )
	203	for ( int i = 0; i < m_point_work_list_index ; i++ )
203	204	{
204		state->m_point_display_list[i].x = state->m_point_work_list[i].x;
205		state->m_point_display_list[i].y = state->m_point_work_list[i].y;
	205	m_point_display_list[i].x = m_point_work_list[i].x;
	206	m_point_display_list[i].y = m_point_work_list[i].y;
206	207	}
207		state->m_point_display_list_index = state->m_point_work_list_index;
208		state->m_point_work_list_index = 0;
209		state->m_interrupt = 0;
	208	m_point_display_list_index = m_point_work_list_index;
	209	m_point_work_list_index = 0;
	210	m_interrupt = 0;
210	211	}
211	212	}
212	213	else
213	214	{
214		if ( state->m_point_work_list_index >= MAX_POINTS )
	215	if ( m_point_work_list_index >= MAX_POINTS )
215	216	{
216	217	logerror("Work list overflow\n");
217	218	}
218	219	else
219	220	{
220		state->m_point_work_list[state->m_point_work_list_index].x = state->m_x;
221		state->m_point_work_list[state->m_point_work_list_index].y = state->m_y;
222		state->m_point_work_list_index++;
	221	m_point_work_list[m_point_work_list_index].x = m_x;
	222	m_point_work_list[m_point_work_list_index].y = m_y;
	223	m_point_work_list_index++;
223	224	}
224	225	}
225	226	}
r14845	r14846
269	270	*
270	271	*************************************/
271	272
272		static WRITE16_HANDLER(clk_w)
	273	WRITE16_MEMBER(galaxygame_state::clk_w)
273	274	{
274		galaxygame_state *state = space->machine().driver_data<galaxygame_state>();
275		state->m_clk = data;
	275	m_clk = data;
276	276	}
277	277
278	278	static ADDRESS_MAP_START( galaxygame_map, AS_PROGRAM, 16, galaxygame_state )
279	279	AM_RANGE(0x0000, 0x1fff) AM_RAM
280		AM_RANGE(0xfec0, 0xfecf) AM_READWRITE_LEGACY(ke_r, ke_w)
281		AM_RANGE(0xff52, 0xff53) AM_READWRITE_LEGACY(y_r, y_w) // 177522 Y
	280	AM_RANGE(0xfec0, 0xfecf) AM_READWRITE(ke_r, ke_w)
	281	AM_RANGE(0xff52, 0xff53) AM_READWRITE(y_r, y_w) // 177522 Y
282	282	AM_RANGE(0xff54, 0xff55) AM_READ_PORT("COINAC") // 177524 COINAC
283		AM_RANGE(0xff5a, 0xff5b) AM_READWRITE_LEGACY(x_r, x_w)   // 177532 X
	283	AM_RANGE(0xff5a, 0xff5b) AM_READWRITE(x_r, x_w)   // 177532 X
284	284	AM_RANGE(0xff5c, 0xff5d) AM_READ_PORT("SR")      // 177534 SR
285		AM_RANGE(0xff66, 0xff67) AM_WRITE_LEGACY(clk_w)      // 177546 KW11 line frequency clock
	285	AM_RANGE(0xff66, 0xff67) AM_WRITE(clk_w)      // 177546 KW11 line frequency clock
286	286	ADDRESS_MAP_END
287	287
288	288

src/mame/drivers/poo.c

r14845	r14846
56	56	UINT8 *m_scrolly;
57	57	UINT8 *m_sprites;
58	58	UINT8 m_vram_colbank;
	59	DECLARE_READ8_MEMBER(unk_inp_r);
	60	DECLARE_READ8_MEMBER(unk_inp2_r);
	61	DECLARE_READ8_MEMBER(unk_inp3_r);
	62	DECLARE_WRITE8_MEMBER(unk_w);
	63	DECLARE_WRITE8_MEMBER(sound_cmd_w);
	64	DECLARE_WRITE8_MEMBER(poo_vregs_w);
	65	DECLARE_READ8_MEMBER(timer_r);
59	66	};
60	67
61	68
r14845	r14846
106	113	return 0;
107	114	}
108	115
109		static READ8_HANDLER( unk_inp_r )
	116	READ8_MEMBER(poo_state::unk_inp_r)
110	117	{
111		return 0x00;//space->machine().rand();
	118	return 0x00;//machine().rand();
112	119	}
113	120
114	121	#if 0
115	122
116		static READ8_HANDLER( unk_inp2_r )
	123	READ8_MEMBER(poo_state::unk_inp2_r)
117	124	{
118	125	return 0xff;
119	126	}
120	127
121		static READ8_HANDLER( unk_inp3_r )
	128	READ8_MEMBER(poo_state::unk_inp3_r)
122	129	{
123		return space->machine().rand();
	130	return machine().rand();
124	131	}
125	132	#endif
126	133
127	134
128	135	#if 0
129		static WRITE8_HANDLER( unk_w )
	136	WRITE8_MEMBER(poo_state::unk_w)
130	137	{
131	138	printf("%02x %02x\n",data,offset);
132	139	}
133	140	#endif
134	141
135	142	/* soundlatch write */
136		static WRITE8_HANDLER( sound_cmd_w )
	143	WRITE8_MEMBER(poo_state::sound_cmd_w)
137	144	{
138	145	soundlatch_w(space, 0, (data & 0xff));
139		cputag_set_input_line(space->machine(), "subcpu", 0, HOLD_LINE);
	146	cputag_set_input_line(machine(), "subcpu", 0, HOLD_LINE);
140	147	}
141	148
142		static WRITE8_HANDLER( poo_vregs_w )
	149	WRITE8_MEMBER(poo_state::poo_vregs_w)
143	150	{
144		poo_state *state = space->machine().driver_data<poo_state>();
145	151	// bit 2 used, unknown purpose
146		state->m_vram_colbank = data & 0x18;
	152	m_vram_colbank = data & 0x18;
147	153	}
148	154
149	155	static ADDRESS_MAP_START( unclepoo_main_map, AS_PROGRAM, 8, poo_state )
150	156	AM_RANGE(0x0000, 0x7fff) AM_ROM AM_WRITENOP
151	157	AM_RANGE(0x8000, 0x8fff) AM_RAM
152	158	AM_RANGE(0x9000, 0x97ff) AM_RAM
153		AM_RANGE(0x9800, 0x9801) AM_READ_LEGACY(unk_inp_r) //AM_WRITE_LEGACY(unk_w )
	159	AM_RANGE(0x9800, 0x9801) AM_READ(unk_inp_r) //AM_WRITE(unk_w )
154	160
155	161	AM_RANGE(0xb000, 0xb07f) AM_RAM AM_BASE(m_sprites)
156	162	AM_RANGE(0xb080, 0xb0ff) AM_RAM AM_BASE(m_scrolly)
157	163
158		AM_RANGE(0xb400, 0xb400) AM_WRITE_LEGACY(sound_cmd_w)
	164	AM_RANGE(0xb400, 0xb400) AM_WRITE(sound_cmd_w)
159	165
160	166	AM_RANGE(0xb500, 0xb500) AM_READ_PORT("DSW1")
161	167	AM_RANGE(0xb501, 0xb501) AM_READ_PORT("DSW2")
r14845	r14846
163	169	AM_RANGE(0xb503, 0xb503) AM_READ_PORT("P2")
164	170	AM_RANGE(0xb504, 0xb504) AM_READ_PORT("SYSTEM")
165	171
166		AM_RANGE(0xb700, 0xb700) AM_WRITE_LEGACY(poo_vregs_w)
	172	AM_RANGE(0xb700, 0xb700) AM_WRITE(poo_vregs_w)
167	173
168	174	AM_RANGE(0xb800, 0xbfff) AM_RAM AM_BASE(m_vram)
169	175
r14845	r14846
306	312	}
307	313	}
308	314
309		static READ8_HANDLER( timer_r )
	315	READ8_MEMBER(poo_state::timer_r)
310	316	{
311		return downcast<cpu_device *>(&space->device())->total_cycles() / 16;
	317	return downcast<cpu_device *>(&space.device())->total_cycles() / 16;
312	318	}
313	319
314	320
r14845	r14846
317	323	AY8910_LEGACY_OUTPUT,
318	324	AY8910_DEFAULT_LOADS,
319	325	DEVCB_MEMORY_HANDLER("subcpu", PROGRAM, soundlatch_r),
320		DEVCB_MEMORY_HANDLER("subcpu", PROGRAM, timer_r),
	326	DEVCB_DRIVER_MEMBER(poo_state, timer_r),
321	327	DEVCB_NULL,
322	328	DEVCB_NULL
323	329	};

src/mame/drivers/drtomy.c

r14845	r14846
29	29
30	30	/* misc */
31	31	int       m_oki_bank;
	32	DECLARE_WRITE16_MEMBER(drtomy_vram_fg_w);
	33	DECLARE_WRITE16_MEMBER(drtomy_vram_bg_w);
32	34	};
33	35
34	36
r14845	r14846
133	135	return 0;
134	136	}
135	137
136		static WRITE16_HANDLER( drtomy_vram_fg_w )
	138	WRITE16_MEMBER(drtomy_state::drtomy_vram_fg_w)
137	139	{
138		drtomy_state *state = space->machine().driver_data<drtomy_state>();
139		COMBINE_DATA(&state->m_videoram_fg[offset]);
140		state->m_tilemap_fg->mark_tile_dirty(offset);
	140	COMBINE_DATA(&m_videoram_fg[offset]);
	141	m_tilemap_fg->mark_tile_dirty(offset);
141	142	}
142	143
143		static WRITE16_HANDLER( drtomy_vram_bg_w )
	144	WRITE16_MEMBER(drtomy_state::drtomy_vram_bg_w)
144	145	{
145		drtomy_state *state = space->machine().driver_data<drtomy_state>();
146		COMBINE_DATA(&state->m_videoram_bg[offset]);
147		state->m_tilemap_bg->mark_tile_dirty(offset);
	146	COMBINE_DATA(&m_videoram_bg[offset]);
	147	m_tilemap_bg->mark_tile_dirty(offset);
148	148	}
149	149
150	150	static WRITE16_DEVICE_HANDLER( drtomy_okibank_w )
r14845	r14846
162	162
163	163	static ADDRESS_MAP_START( drtomy_map, AS_PROGRAM, 16, drtomy_state )
164	164	AM_RANGE(0x000000, 0x03ffff) AM_ROM   /* ROM */
165		AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE_LEGACY(drtomy_vram_fg_w) AM_BASE(m_videoram_fg)   /* Video RAM FG */
166		AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE_LEGACY(drtomy_vram_bg_w) AM_BASE(m_videoram_bg) /* Video RAM BG */
	165	AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(drtomy_vram_fg_w) AM_BASE(m_videoram_fg)   /* Video RAM FG */
	166	AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(drtomy_vram_bg_w) AM_BASE(m_videoram_bg) /* Video RAM BG */
167	167	AM_RANGE(0x200000, 0x2007ff) AM_RAM_WRITE_LEGACY(paletteram16_xRRRRRGGGGGBBBBB_word_w) AM_BASE_GENERIC(paletteram) /* Palette */
168	168	AM_RANGE(0x440000, 0x440fff) AM_RAM AM_BASE(m_spriteram) /* Sprite RAM */
169	169	AM_RANGE(0x700000, 0x700001) AM_READ_PORT("DSW1")

src/mame/drivers/calorie.c

r14845	r14846
98	98	tilemap_t  *m_bg_tilemap;
99	99	tilemap_t  *m_fg_tilemap;
100	100	UINT8    m_bg_bank;
	101	DECLARE_WRITE8_MEMBER(fg_ram_w);
	102	DECLARE_WRITE8_MEMBER(bg_bank_w);
	103	DECLARE_WRITE8_MEMBER(calorie_flipscreen_w);
	104	DECLARE_READ8_MEMBER(calorie_soundlatch_r);
	105	DECLARE_WRITE8_MEMBER(bogus_w);
101	106	};
102	107
103	108
r14845	r14846
198	203	*
199	204	*************************************/
200	205
201		static WRITE8_HANDLER( fg_ram_w )
	206	WRITE8_MEMBER(calorie_state::fg_ram_w)
202	207	{
203		calorie_state *state = space->machine().driver_data<calorie_state>();
204		state->m_fg_ram[offset] = data;
205		state->m_fg_tilemap->mark_tile_dirty(offset & 0x3ff);
	208	m_fg_ram[offset] = data;
	209	m_fg_tilemap->mark_tile_dirty(offset & 0x3ff);
206	210	}
207	211
208		static WRITE8_HANDLER( bg_bank_w )
	212	WRITE8_MEMBER(calorie_state::bg_bank_w)
209	213	{
210		calorie_state *state = space->machine().driver_data<calorie_state>();
211		if((state->m_bg_bank & ~0x10) != (data & ~0x10))
212		state->m_bg_tilemap->mark_all_dirty();
	214	if((m_bg_bank & ~0x10) != (data & ~0x10))
	215	m_bg_tilemap->mark_all_dirty();
213	216
214		state->m_bg_bank = data;
	217	m_bg_bank = data;
215	218	}
216	219
217		static WRITE8_HANDLER( calorie_flipscreen_w )
	220	WRITE8_MEMBER(calorie_state::calorie_flipscreen_w)
218	221	{
219		flip_screen_set(space->machine(), data & 1);
	222	flip_screen_set(machine(), data & 1);
220	223	}
221	224
222		static READ8_HANDLER( calorie_soundlatch_r )
	225	READ8_MEMBER(calorie_state::calorie_soundlatch_r)
223	226	{
224	227	UINT8 latch = soundlatch_r(space, 0);
225	228	soundlatch_clear_w(space, 0, 0);
226	229	return latch;
227	230	}
228	231
229		static WRITE8_HANDLER( bogus_w )
	232	WRITE8_MEMBER(calorie_state::bogus_w)
230	233	{
231	234	popmessage("written to 3rd sound chip: data = %02X port = %02X", data, offset);
232	235	}
r14845	r14846
241	244	AM_RANGE(0x0000, 0x7fff) AM_ROM
242	245	AM_RANGE(0x8000, 0xbfff) AM_ROM
243	246	AM_RANGE(0xc000, 0xcfff) AM_RAM
244		AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE_LEGACY(fg_ram_w) AM_BASE(m_fg_ram)
	247	AM_RANGE(0xd000, 0xd7ff) AM_RAM_WRITE(fg_ram_w) AM_BASE(m_fg_ram)
245	248	AM_RANGE(0xd800, 0xdbff) AM_RAM AM_BASE(m_sprites)
246	249	AM_RANGE(0xdc00, 0xdcff) AM_RAM_WRITE_LEGACY(paletteram_xxxxBBBBGGGGRRRR_le_w) AM_BASE_GENERIC(paletteram)
247		AM_RANGE(0xde00, 0xde00) AM_WRITE_LEGACY(bg_bank_w)
	250	AM_RANGE(0xde00, 0xde00) AM_WRITE(bg_bank_w)
248	251	AM_RANGE(0xf000, 0xf000) AM_READ_PORT("P1")
249	252	AM_RANGE(0xf001, 0xf001) AM_READ_PORT("P2")
250	253	AM_RANGE(0xf002, 0xf002) AM_READ_PORT("SYSTEM")
251		AM_RANGE(0xf004, 0xf004) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(calorie_flipscreen_w)
	254	AM_RANGE(0xf004, 0xf004) AM_READ_PORT("DSW1") AM_WRITE(calorie_flipscreen_w)
252	255	AM_RANGE(0xf005, 0xf005) AM_READ_PORT("DSW2")
253	256	AM_RANGE(0xf800, 0xf800) AM_WRITE_LEGACY(soundlatch_w)
254	257	ADDRESS_MAP_END
r14845	r14846
257	260	static ADDRESS_MAP_START( calorie_sound_map, AS_PROGRAM, 8, calorie_state )
258	261	AM_RANGE(0x0000, 0x3fff) AM_ROM
259	262	AM_RANGE(0x8000, 0x87ff) AM_RAM
260		AM_RANGE(0xc000, 0xc000) AM_READ_LEGACY(calorie_soundlatch_r)
	263	AM_RANGE(0xc000, 0xc000) AM_READ(calorie_soundlatch_r)
261	264	ADDRESS_MAP_END
262	265
263	266	static ADDRESS_MAP_START( calorie_sound_io_map, AS_IO, 8, calorie_state )
r14845	r14846
267	270	AM_RANGE(0x10, 0x11) AM_DEVWRITE_LEGACY("ay2", ay8910_address_data_w)
268	271	AM_RANGE(0x11, 0x11) AM_DEVREAD_LEGACY("ay2", ay8910_r)
269	272	// 3rd ?
270		AM_RANGE(0x00, 0xff) AM_WRITE_LEGACY(bogus_w)
	273	AM_RANGE(0x00, 0xff) AM_WRITE(bogus_w)
271	274	ADDRESS_MAP_END
272	275
273	276

src/mame/drivers/sfkick.c

r14845	r14846
70	70	int m_bank[8];
71	71	int m_input_mux;
72	72	required_device<v9938_device> m_v9938;
	73	DECLARE_WRITE8_MEMBER(page0_w);
	74	DECLARE_WRITE8_MEMBER(page1_w);
	75	DECLARE_WRITE8_MEMBER(page2_w);
	76	DECLARE_WRITE8_MEMBER(page3_w);
73	77	};
74	78
75	79
r14845	r14846
241	245	sfkick_remap_banks(machine);
242	246	}
243	247
244		static WRITE8_HANDLER(page0_w)
	248	WRITE8_MEMBER(sfkick_state::page0_w)
245	249	{
246		sfkick_state *state = space->machine().driver_data<sfkick_state>();
247		if((state->m_bank_cfg&3)==2)
	250	if((m_bank_cfg&3)==2)
248	251	{
249	252	if(offset<0x2000)
250	253	{
251		sfkick_bank_set(space->machine(),0,data);
	254	sfkick_bank_set(machine(),0,data);
252	255	}
253	256	else
254	257	{
255		sfkick_bank_set(space->machine(),1,data);
	258	sfkick_bank_set(machine(),1,data);
256	259	}
257	260	}
258	261	}
259	262
260		static WRITE8_HANDLER(page1_w)
	263	WRITE8_MEMBER(sfkick_state::page1_w)
261	264	{
262		sfkick_state *state = space->machine().driver_data<sfkick_state>();
263		if(((state->m_bank_cfg>>2)&3)==2)
	265	if(((m_bank_cfg>>2)&3)==2)
264	266	{
265	267	if(offset<0x2000)
266	268	{
267		sfkick_bank_set(space->machine(),2,data);
	269	sfkick_bank_set(machine(),2,data);
268	270	}
269	271	else
270	272	{
271		sfkick_bank_set(space->machine(),3,data);
	273	sfkick_bank_set(machine(),3,data);
272	274	}
273	275	}
274	276	}
275	277
276		static WRITE8_HANDLER(page2_w)
	278	WRITE8_MEMBER(sfkick_state::page2_w)
277	279	{
278		sfkick_state *state = space->machine().driver_data<sfkick_state>();
279		if(((state->m_bank_cfg>>4)&3)==2)
	280	if(((m_bank_cfg>>4)&3)==2)
280	281	{
281	282	if(offset<0x2000)
282	283	{
283		sfkick_bank_set(space->machine(),4,data);
	284	sfkick_bank_set(machine(),4,data);
284	285	}
285	286	else
286	287	{
287		sfkick_bank_set(space->machine(),5,data);
	288	sfkick_bank_set(machine(),5,data);
288	289	}
289	290	}
290	291	}
291	292
292		static WRITE8_HANDLER(page3_w)
	293	WRITE8_MEMBER(sfkick_state::page3_w)
293	294	{
294		sfkick_state *state = space->machine().driver_data<sfkick_state>();
295		if(((state->m_bank_cfg>>6)&3)==2)
	295	if(((m_bank_cfg>>6)&3)==2)
296	296	{
297	297	if(offset<0x2000)
298	298	{
299		sfkick_bank_set(space->machine(),6,data);
	299	sfkick_bank_set(machine(),6,data);
300	300	}
301	301	else
302	302	{
303		sfkick_bank_set(space->machine(),7,data);
	303	sfkick_bank_set(machine(),7,data);
304	304	}
305	305	}
306	306	else
307	307	{
308		if(((state->m_bank_cfg>>6)&3)==3)
	308	if(((m_bank_cfg>>6)&3)==3)
309	309	{
310		state->m_main_mem[offset]=data;
	310	m_main_mem[offset]=data;
311	311	}
312	312	}
313	313	}
r14845	r14846
323	323	AM_RANGE( 0xa000, 0xbfff) AM_ROMBANK("bank6")
324	324	AM_RANGE( 0xc000, 0xdfff) AM_ROMBANK("bank7")
325	325	AM_RANGE( 0xe000, 0xffff) AM_ROMBANK("bank8")
326		AM_RANGE( 0x0000, 0x3fff) AM_WRITE_LEGACY(page0_w )
327		AM_RANGE( 0x4000, 0x7fff) AM_WRITE_LEGACY(page1_w )
328		AM_RANGE( 0x8000, 0xbfff) AM_WRITE_LEGACY(page2_w )
329		AM_RANGE( 0xc000, 0xffff) AM_WRITE_LEGACY(page3_w )
	326	AM_RANGE( 0x0000, 0x3fff) AM_WRITE(page0_w )
	327	AM_RANGE( 0x4000, 0x7fff) AM_WRITE(page1_w )
	328	AM_RANGE( 0x8000, 0xbfff) AM_WRITE(page2_w )
	329	AM_RANGE( 0xc000, 0xffff) AM_WRITE(page3_w )
330	330	ADDRESS_MAP_END
331	331
332	332	static ADDRESS_MAP_START( sfkick_io_map, AS_IO, 8, sfkick_state )

src/mame/drivers/dgpix.c

r14845	r14846
65	65	int m_old_vbuf;
66	66	UINT32 m_flash_cmd;
67	67	INT32 m_first_offset;
	68	DECLARE_READ32_MEMBER(flash_r);
	69	DECLARE_WRITE32_MEMBER(flash_w);
	70	DECLARE_WRITE32_MEMBER(vram_w);
	71	DECLARE_READ32_MEMBER(vram_r);
	72	DECLARE_WRITE32_MEMBER(vbuffer_w);
	73	DECLARE_WRITE32_MEMBER(coin_w);
	74	DECLARE_READ32_MEMBER(vblank_r);
68	75	};
69	76
70	77
71		static READ32_HANDLER( flash_r )
	78	READ32_MEMBER(dgpix_state::flash_r)
72	79	{
73		dgpix_state *state = space->machine().driver_data<dgpix_state>();
74		UINT32 *ROM = (UINT32 *)space->machine().region("user1")->base();
	80	UINT32 *ROM = (UINT32 *)machine().region("user1")->base();
75	81
76		if(offset >= (0x2000000 - state->m_flash_roms * 0x400000) / 4)
	82	if(offset >= (0x2000000 - m_flash_roms * 0x400000) / 4)
77	83	{
78		if(state->m_flash_cmd == 0x90900000)
	84	if(m_flash_cmd == 0x90900000)
79	85	{
80	86	//read maker ID and chip ID
81	87	return 0x00890014;
82	88	}
83		else if(state->m_flash_cmd == 0x00700000)
	89	else if(m_flash_cmd == 0x00700000)
84	90	{
85	91	//read status
86	92	return 0x80<<16;
87	93	}
88		else if(state->m_flash_cmd == 0x70700000)
	94	else if(m_flash_cmd == 0x70700000)
89	95	{
90	96	//read status and ?
91	97	return 0x82<<16;
92	98	}
93		else if(state->m_flash_cmd == 0xe8e80000)
	99	else if(m_flash_cmd == 0xe8e80000)
94	100	{
95	101	//read status ?
96	102	return 0x80<<16;
r14845	r14846
100	106	return ROM[offset];
101	107	}
102	108
103		static WRITE32_HANDLER( flash_w )
	109	WRITE32_MEMBER(dgpix_state::flash_w)
104	110	{
105		dgpix_state *state = space->machine().driver_data<dgpix_state>();
106		if(state->m_flash_cmd == 0x20200000)
	111	if(m_flash_cmd == 0x20200000)
107	112	{
108	113	// erase game settings
109	114	if(data == 0xd0d00000)
110	115	{
111	116	// point to game settings
112		UINT8 *rom = (UINT8 *)space->machine().region("user1")->base() + offset*4;
	117	UINT8 *rom = (UINT8 *)machine().region("user1")->base() + offset*4;
113	118
114	119	// erase one block
115	120	memset(rom, 0xff, 0x10000);
116	121
117		state->m_flash_cmd = 0;
	122	m_flash_cmd = 0;
118	123	}
119	124	}
120		else if(state->m_flash_cmd == 0x0f0f0000)
	125	else if(m_flash_cmd == 0x0f0f0000)
121	126	{
122		if(data == 0xd0d00000 && offset == state->m_first_offset)
	127	if(data == 0xd0d00000 && offset == m_first_offset)
123	128	{
124	129	// finished
125		state->m_flash_cmd = 0;
126		state->m_first_offset = -1;
	130	m_flash_cmd = 0;
	131	m_first_offset = -1;
127	132	}
128	133	else
129	134	{
130		UINT16 *rom = (UINT16 *)space->machine().region("user1")->base();
	135	UINT16 *rom = (UINT16 *)machine().region("user1")->base();
131	136
132	137	// write game settings
133	138
r14845	r14846
139	144	}
140	145	else
141	146	{
142		state->m_flash_cmd = data;
	147	m_flash_cmd = data;
143	148
144		if(state->m_flash_cmd == 0x0f0f0000 && state->m_first_offset == -1)
	149	if(m_flash_cmd == 0x0f0f0000 && m_first_offset == -1)
145	150	{
146		state->m_first_offset = offset;
	151	m_first_offset = offset;
147	152	}
148	153	}
149	154	}
150	155
151		static WRITE32_HANDLER( vram_w )
	156	WRITE32_MEMBER(dgpix_state::vram_w)
152	157	{
153		dgpix_state *state = space->machine().driver_data<dgpix_state>();
154		UINT32 *dest = &state->m_vram[offset+(0x40000/4)*state->m_vbuffer];
	158	UINT32 *dest = &m_vram[offset+(0x40000/4)*m_vbuffer];
155	159
156	160	if (mem_mask == 0xffffffff)
157	161	{
r14845	r14846
166	170	COMBINE_DATA(dest);
167	171	}
168	172
169		static READ32_HANDLER( vram_r )
	173	READ32_MEMBER(dgpix_state::vram_r)
170	174	{
171		dgpix_state *state = space->machine().driver_data<dgpix_state>();
172		return state->m_vram[offset+(0x40000/4)*state->m_vbuffer];
	175	return m_vram[offset+(0x40000/4)*m_vbuffer];
173	176	}
174	177
175		static WRITE32_HANDLER( vbuffer_w )
	178	WRITE32_MEMBER(dgpix_state::vbuffer_w)
176	179	{
177		dgpix_state *state = space->machine().driver_data<dgpix_state>();
178		if(state->m_old_vbuf == 3 && (data & 3) == 2)
	180	if(m_old_vbuf == 3 && (data & 3) == 2)
179	181	{
180		state->m_vbuffer ^= 1;
	182	m_vbuffer ^= 1;
181	183	}
182	184
183		state->m_old_vbuf = data & 3;
	185	m_old_vbuf = data & 3;
184	186	}
185	187
186		static WRITE32_HANDLER( coin_w )
	188	WRITE32_MEMBER(dgpix_state::coin_w)
187	189	{
188		coin_counter_w(space->machine(), 0, data & 1);
189		coin_counter_w(space->machine(), 1, data & 2);
	190	coin_counter_w(machine(), 0, data & 1);
	191	coin_counter_w(machine(), 1, data & 2);
190	192	}
191	193
192		static READ32_HANDLER( vblank_r )
	194	READ32_MEMBER(dgpix_state::vblank_r)
193	195	{
194	196	/* burn a bunch of cycles because this is polled frequently during busy loops */
195		device_eat_cycles(&space->device(), 100);
196		return input_port_read(space->machine(), "VBLANK");
	197	device_eat_cycles(&space.device(), 100);
	198	return input_port_read(machine(), "VBLANK");
197	199	}
198	200
199	201	static ADDRESS_MAP_START( cpu_map, AS_PROGRAM, 32, dgpix_state )
200	202	AM_RANGE(0x00000000, 0x007fffff) AM_RAM
201		AM_RANGE(0x40000000, 0x4003ffff) AM_READWRITE_LEGACY(vram_r, vram_w)
202		AM_RANGE(0xe0000000, 0xe1ffffff) AM_READWRITE_LEGACY(flash_r, flash_w)
203		AM_RANGE(0xe2000000, 0xe3ffffff) AM_READWRITE_LEGACY(flash_r, flash_w)
	203	AM_RANGE(0x40000000, 0x4003ffff) AM_READWRITE(vram_r, vram_w)
	204	AM_RANGE(0xe0000000, 0xe1ffffff) AM_READWRITE(flash_r, flash_w)
	205	AM_RANGE(0xe2000000, 0xe3ffffff) AM_READWRITE(flash_r, flash_w)
204	206	AM_RANGE(0xffc00000, 0xffffffff) AM_ROM AM_REGION("user1", 0x1c00000)
205	207	ADDRESS_MAP_END
206	208
207	209	static ADDRESS_MAP_START( io_map, AS_IO, 32, dgpix_state )
208	210	AM_RANGE(0x0200, 0x0203) AM_READNOP // used to sync with the protecion PIC? tested bits 0 and 1
209		AM_RANGE(0x0400, 0x0403) AM_READWRITE_LEGACY(vblank_r, vbuffer_w)
	211	AM_RANGE(0x0400, 0x0403) AM_READWRITE(vblank_r, vbuffer_w)
210	212	AM_RANGE(0x0a10, 0x0a13) AM_READ_PORT("INPUTS")
211		AM_RANGE(0x0200, 0x0203) AM_WRITE_LEGACY(coin_w)
	213	AM_RANGE(0x0200, 0x0203) AM_WRITE(coin_w)
212	214	AM_RANGE(0x0c00, 0x0c03) AM_WRITENOP // writes only: 1, 0, 1 at startup
213	215	AM_RANGE(0x0c80, 0x0c83) AM_WRITENOP // sound commands / latches
214	216	AM_RANGE(0x0c80, 0x0c83) AM_READNOP //read at startup -> cmp 0xFE

src/mame/drivers/sangho.c

r14845	r14846
54	54	UINT8 m_pzlestar_mem_bank;
55	55	UINT8 m_pzlestar_rom_bank;
56	56	required_device<v9938_device> m_v9938;
	57	DECLARE_WRITE8_MEMBER(pzlestar_bank_w);
	58	DECLARE_WRITE8_MEMBER(pzlestar_mem_bank_w);
	59	DECLARE_READ8_MEMBER(pzlestar_mem_bank_r);
	60	DECLARE_WRITE8_MEMBER(sexyboom_bank_w);
57	61	};
58	62
59	63
r14845	r14846
152	156
153	157	}
154	158
155		static WRITE8_HANDLER(pzlestar_bank_w)
	159	WRITE8_MEMBER(sangho_state::pzlestar_bank_w)
156	160	{
157		sangho_state *state = space->machine().driver_data<sangho_state>();
158	161	logerror("rom bank %02x\n", data);
159		state->m_pzlestar_rom_bank = data;
160		pzlestar_map_banks(space->machine());
	162	m_pzlestar_rom_bank = data;
	163	pzlestar_map_banks(machine());
161	164	}
162	165
163		static WRITE8_HANDLER(pzlestar_mem_bank_w)
	166	WRITE8_MEMBER(sangho_state::pzlestar_mem_bank_w)
164	167	{
165		sangho_state *state = space->machine().driver_data<sangho_state>();
166	168	logerror("mem bank %02x\n", data);
167		state->m_pzlestar_mem_bank = data;
168		pzlestar_map_banks(space->machine());
	169	m_pzlestar_mem_bank = data;
	170	pzlestar_map_banks(machine());
169	171	}
170	172
171		static READ8_HANDLER(pzlestar_mem_bank_r)
	173	READ8_MEMBER(sangho_state::pzlestar_mem_bank_r)
172	174	{
173		sangho_state *state = space->machine().driver_data<sangho_state>();
174		return state->m_pzlestar_mem_bank;
	175	return m_pzlestar_mem_bank;
175	176	}
176	177
177	178	static void sexyboom_map_bank(running_machine &machine, int bank)
r14845	r14846
217	218	}
218	219	}
219	220
220		static WRITE8_HANDLER(sexyboom_bank_w)
	221	WRITE8_MEMBER(sangho_state::sexyboom_bank_w)
221	222	{
222		sangho_state *state = space->machine().driver_data<sangho_state>();
223		state->m_sexyboom_bank[offset] = data;
224		sexyboom_map_bank(space->machine(), offset>>1);
	223	m_sexyboom_bank[offset] = data;
	224	sexyboom_map_bank(machine(), offset>>1);
225	225	}
226	226
227	227	static ADDRESS_MAP_START( sangho_map, AS_PROGRAM, 8, sangho_state )
r14845	r14846
236	236	static ADDRESS_MAP_START( pzlestar_io_map, AS_IO, 8, sangho_state )
237	237	ADDRESS_MAP_GLOBAL_MASK(0xff)
238	238	AM_RANGE( 0x7c, 0x7d) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w )
239		AM_RANGE( 0x91, 0x91) AM_WRITE_LEGACY(pzlestar_bank_w )
	239	AM_RANGE( 0x91, 0x91) AM_WRITE(pzlestar_bank_w )
240	240	AM_RANGE( 0x98, 0x9b) AM_DEVREADWRITE("v9938", v9938_device, read, write )
241	241	AM_RANGE( 0xa0, 0xa0) AM_READ_PORT("P1")
242	242	AM_RANGE( 0xa1, 0xa1) AM_READ_PORT("P2")
243		AM_RANGE( 0xa8, 0xa8) AM_READWRITE_LEGACY(pzlestar_mem_bank_r, pzlestar_mem_bank_w )
	243	AM_RANGE( 0xa8, 0xa8) AM_READWRITE(pzlestar_mem_bank_r, pzlestar_mem_bank_w )
244	244	AM_RANGE( 0xf7, 0xf7) AM_READ_PORT("DSW")
245	245	ADDRESS_MAP_END
246	246
r14845	r14846
253	253	AM_RANGE( 0xa1, 0xa1) AM_READ_PORT("P2")
254	254	AM_RANGE( 0xf0, 0xf3) AM_DEVREADWRITE("v9938", v9938_device, read, write )
255	255	AM_RANGE( 0xf7, 0xf7) AM_READ_PORT("DSW")
256		AM_RANGE( 0xf8, 0xff) AM_WRITE_LEGACY(sexyboom_bank_w )
	256	AM_RANGE( 0xf8, 0xff) AM_WRITE(sexyboom_bank_w )
257	257	ADDRESS_MAP_END
258	258
259	259

src/mame/drivers/bmcbowl.c

r14845	r14846
120	120	size_t m_stats_ram_size;
121	121	int m_clr_offset;
122	122	int m_bmc_input;
	123	DECLARE_READ16_MEMBER(bmc_random_read);
	124	DECLARE_READ16_MEMBER(bmc_protection_r);
	125	DECLARE_WRITE16_MEMBER(bmc_RAMDAC_offset_w);
	126	DECLARE_WRITE16_MEMBER(bmc_RAMDAC_color_w);
	127	DECLARE_WRITE16_MEMBER(scroll_w);
123	128	};
124	129
125	130
r14845	r14846
181	186	return 0;
182	187	}
183	188
184		static READ16_HANDLER( bmc_random_read )
	189	READ16_MEMBER(bmcbowl_state::bmc_random_read)
185	190	{
186		return space->machine().rand();
	191	return machine().rand();
187	192	}
188	193
189		static READ16_HANDLER( bmc_protection_r )
	194	READ16_MEMBER(bmcbowl_state::bmc_protection_r)
190	195	{
191		switch(cpu_get_previouspc(&space->device()))
	196	switch(cpu_get_previouspc(&space.device()))
192	197	{
193	198	case 0xca68:
194		switch(cpu_get_reg(&space->device(), M68K_D2))
	199	switch(cpu_get_reg(&space.device(), M68K_D2))
195	200	{
196	201	case 0:        return 0x37<<8;
197	202	case 0x1013: return 0;
r14845	r14846
199	204	}
200	205	break;
201	206	}
202		logerror("Protection read @ %X\n",cpu_get_previouspc(&space->device()));
203		return space->machine().rand();
	207	logerror("Protection read @ %X\n",cpu_get_previouspc(&space.device()));
	208	return machine().rand();
204	209	}
205	210
206		static WRITE16_HANDLER( bmc_RAMDAC_offset_w )
	211	WRITE16_MEMBER(bmcbowl_state::bmc_RAMDAC_offset_w)
207	212	{
208		bmcbowl_state *state = space->machine().driver_data<bmcbowl_state>();
209		state->m_clr_offset=data*3;
	213	m_clr_offset=data*3;
210	214	}
211	215
212		static WRITE16_HANDLER( bmc_RAMDAC_color_w )
	216	WRITE16_MEMBER(bmcbowl_state::bmc_RAMDAC_color_w)
213	217	{
214		bmcbowl_state *state = space->machine().driver_data<bmcbowl_state>();
215		state->m_bmc_colorram[state->m_clr_offset]=data;
216		palette_set_color_rgb(space->machine(),state->m_clr_offset/3,pal6bit(state->m_bmc_colorram[(state->m_clr_offset/3)*3]),pal6bit(state->m_bmc_colorram[(state->m_clr_offset/3)*3+1]),pal6bit(state->m_bmc_colorram[(state->m_clr_offset/3)*3+2]));
217		state->m_clr_offset=(state->m_clr_offset+1)%768;
	218	m_bmc_colorram[m_clr_offset]=data;
	219	palette_set_color_rgb(machine(),m_clr_offset/3,pal6bit(m_bmc_colorram[(m_clr_offset/3)*3]),pal6bit(m_bmc_colorram[(m_clr_offset/3)*3+1]),pal6bit(m_bmc_colorram[(m_clr_offset/3)*3+2]));
	220	m_clr_offset=(m_clr_offset+1)%768;
218	221	}
219	222
220		static WRITE16_HANDLER( scroll_w )
	223	WRITE16_MEMBER(bmcbowl_state::scroll_w)
221	224	{
222	225	//TODO - scroll
223	226	}
r14845	r14846
326	329	static ADDRESS_MAP_START( bmcbowl_mem, AS_PROGRAM, 16, bmcbowl_state )
327	330	AM_RANGE(0x000000, 0x01ffff) AM_ROM
328	331
329		AM_RANGE(0x090000, 0x090001) AM_WRITE_LEGACY(bmc_RAMDAC_offset_w)
330		AM_RANGE(0x090002, 0x090003) AM_WRITE_LEGACY(bmc_RAMDAC_color_w)
	332	AM_RANGE(0x090000, 0x090001) AM_WRITE(bmc_RAMDAC_offset_w)
	333	AM_RANGE(0x090002, 0x090003) AM_WRITE(bmc_RAMDAC_color_w)
331	334	AM_RANGE(0x090004, 0x090005) AM_WRITENOP//RAMDAC
332	335
333	336	AM_RANGE(0x090800, 0x090803) AM_WRITENOP
334	337	AM_RANGE(0x091000, 0x091001) AM_WRITENOP
335		AM_RANGE(0x091800, 0x091801) AM_WRITE_LEGACY(scroll_w)
	338	AM_RANGE(0x091800, 0x091801) AM_WRITE(scroll_w)
336	339
337	340	AM_RANGE(0x092000, 0x09201f) AM_DEVREADWRITE8("via6522_0", via6522_device, read, write, 0x00ff)
338	341
r14845	r14846
354	357	AM_RANGE(0x30c040, 0x30c041) AM_WRITENOP
355	358	AM_RANGE(0x30c080, 0x30c081) AM_WRITENOP
356	359	AM_RANGE(0x30c0c0, 0x30c0c1) AM_WRITENOP
357		AM_RANGE(0x30c100, 0x30c101) AM_READ_LEGACY(bmc_protection_r)
	360	AM_RANGE(0x30c100, 0x30c101) AM_READ(bmc_protection_r)
358	361	AM_RANGE(0x30c140, 0x30c141) AM_WRITENOP
359		AM_RANGE(0x30ca00, 0x30ca01) AM_READ_LEGACY(bmc_random_read) AM_WRITENOP
	362	AM_RANGE(0x30ca00, 0x30ca01) AM_READ(bmc_random_read) AM_WRITENOP
360	363	ADDRESS_MAP_END
361	364
362	365

src/mame/drivers/pachifev.c

r14845	r14846
103	103	UINT8 m_adpcm_idle;
104	104	UINT8 m_trigger;
105	105	UINT8 m_adpcm_data;
	106	DECLARE_WRITE8_MEMBER(controls_w);
	107	DECLARE_READ8_MEMBER(controls_r);
106	108	};
107	109
108		static WRITE8_HANDLER(controls_w)
	110	WRITE8_MEMBER(pachifev_state::controls_w)
109	111	{
110	112	if(!data)
111	113	{
112		pachifev_state *state = space->machine().driver_data<pachifev_state>();
113	114
	115
114	116	/*end of input read*/
115		state->m_power=0;
116		state->m_max_power=state->m_input_power;
117		if(--state->m_cnt <= 0) /* why to do it N times? no idea.. someone should fix it */
	117	m_power=0;
	118	m_max_power=m_input_power;
	119	if(--m_cnt <= 0) /* why to do it N times? no idea.. someone should fix it */
118	120	{
119		state->m_cnt=0;
120		state->m_input_power=0;
	121	m_cnt=0;
	122	m_input_power=0;
121	123	}
122	124	}
123	125	}
124	126
125		static READ8_HANDLER(controls_r)
	127	READ8_MEMBER(pachifev_state::controls_r)
126	128	{
127		pachifev_state *state = space->machine().driver_data<pachifev_state>();
128		int output_bit=(state->m_power < state->m_max_power)?0:1;
129		++state->m_power;
	129	int output_bit=(m_power < m_max_power)?0:1;
	130	++m_power;
130	131	return output_bit;
131	132	}
132	133
r14845	r14846
144	145	AM_RANGE(0xff12, 0xff12) AM_DEVREADWRITE("tms9928a", tms9928a_device, register_read, register_write)
145	146	AM_RANGE(0xff20, 0xff20) AM_DEVWRITE_LEGACY("sn76_1", sn76496_w)
146	147	AM_RANGE(0xff30, 0xff30) AM_DEVWRITE_LEGACY("sn76_2", sn76496_w)
147		AM_RANGE(0xff40, 0xff40) AM_WRITE_LEGACY(controls_w)
	148	AM_RANGE(0xff40, 0xff40) AM_WRITE(controls_w)
148	149	AM_RANGE(0xff50, 0xff50) AM_WRITENOP /* unknown */
149	150	AM_RANGE(0xfffa, 0xfffb) AM_NOP /* decrementer */
150	151	AM_RANGE(0xfffc, 0xffff) AM_NOP /* nmi */
151	152	ADDRESS_MAP_END
152	153
153	154	static ADDRESS_MAP_START( pachifev_cru, AS_IO, 8, pachifev_state )
154		AM_RANGE(0x000, 0x000) AM_READ_LEGACY(controls_r)
	155	AM_RANGE(0x000, 0x000) AM_READ(controls_r)
155	156	ADDRESS_MAP_END
156	157
157	158

src/mame/drivers/magic10.c

r14845	r14846
100	100	int m_layer2_offset[2];
101	101	UINT16 *m_vregs;
102	102	UINT16 m_magic102_ret;
	103	DECLARE_WRITE16_MEMBER(layer0_videoram_w);
	104	DECLARE_WRITE16_MEMBER(layer1_videoram_w);
	105	DECLARE_WRITE16_MEMBER(layer2_videoram_w);
	106	DECLARE_WRITE16_MEMBER(paletteram_w);
	107	DECLARE_READ16_MEMBER(magic102_r);
	108	DECLARE_READ16_MEMBER(hotslot_copro_r);
	109	DECLARE_WRITE16_MEMBER(hotslot_copro_w);
	110	DECLARE_WRITE16_MEMBER(magic10_out_w);
103	111	};
104	112
105	113
r14845	r14846
107	115	*      Video Hardware      *
108	116	***************************/
109	117
110		static WRITE16_HANDLER( layer0_videoram_w )
	118	WRITE16_MEMBER(magic10_state::layer0_videoram_w)
111	119	{
112		magic10_state *state = space->machine().driver_data<magic10_state>();
113		COMBINE_DATA(&state->m_layer0_videoram[offset]);
114		state->m_layer0_tilemap->mark_tile_dirty(offset >> 1);
	120	COMBINE_DATA(&m_layer0_videoram[offset]);
	121	m_layer0_tilemap->mark_tile_dirty(offset >> 1);
115	122	}
116	123
117		static WRITE16_HANDLER( layer1_videoram_w )
	124	WRITE16_MEMBER(magic10_state::layer1_videoram_w)
118	125	{
119		magic10_state *state = space->machine().driver_data<magic10_state>();
120		COMBINE_DATA(&state->m_layer1_videoram[offset]);
121		state->m_layer1_tilemap->mark_tile_dirty(offset >> 1);
	126	COMBINE_DATA(&m_layer1_videoram[offset]);
	127	m_layer1_tilemap->mark_tile_dirty(offset >> 1);
122	128	}
123	129
124		static WRITE16_HANDLER( layer2_videoram_w )
	130	WRITE16_MEMBER(magic10_state::layer2_videoram_w)
125	131	{
126		magic10_state *state = space->machine().driver_data<magic10_state>();
127		COMBINE_DATA(&state->m_layer2_videoram[offset]);
128		state->m_layer2_tilemap->mark_tile_dirty(offset >> 1);
	132	COMBINE_DATA(&m_layer2_videoram[offset]);
	133	m_layer2_tilemap->mark_tile_dirty(offset >> 1);
129	134	}
130	135
131		static WRITE16_HANDLER( paletteram_w )
	136	WRITE16_MEMBER(magic10_state::paletteram_w)
132	137	{
133		data = COMBINE_DATA(&space->machine().generic.paletteram.u16[offset]);
134		palette_set_color_rgb( space->machine(), offset, pal4bit(data >> 4), pal4bit(data >> 0), pal4bit(data >> 8));
	138	data = COMBINE_DATA(&machine().generic.paletteram.u16[offset]);
	139	palette_set_color_rgb( machine(), offset, pal4bit(data >> 4), pal4bit(data >> 0), pal4bit(data >> 8));
135	140	}
136	141
137	142
r14845	r14846
209	214	*       R/W Handlers       *
210	215	***************************/
211	216
212		static READ16_HANDLER( magic102_r )
	217	READ16_MEMBER(magic10_state::magic102_r)
213	218	{
214		magic10_state *state = space->machine().driver_data<magic10_state>();
215		state->m_magic102_ret ^= 0x20;
216		return state->m_magic102_ret;
	219	m_magic102_ret ^= 0x20;
	220	return m_magic102_ret;
217	221	}
218	222
219		static READ16_HANDLER( hotslot_copro_r )
	223	READ16_MEMBER(magic10_state::hotslot_copro_r)
220	224	{
221	225	return 0x80;
222	226	}
223	227
224		static WRITE16_HANDLER( hotslot_copro_w )
	228	WRITE16_MEMBER(magic10_state::hotslot_copro_w)
225	229	{
226	230	logerror("Writing to copro: %d \n", data);
227	231	}
228	232
229		static WRITE16_HANDLER( magic10_out_w )
	233	WRITE16_MEMBER(magic10_state::magic10_out_w)
230	234	{
231	235	/*
232	236	----------------------------------------------
r14845	r14846
275	279	output_set_lamp_value(7, (data >> 6) & 1);      /* Lamp 7 - PLAY (BET/TAKE/CANCEL) */
276	280	output_set_lamp_value(8, (data >> 8) & 1);      /* Lamp 8 - PAYOUT/SUPERGAME */
277	281
278		coin_counter_w(space->machine(), 0, data & 0x400);
	282	coin_counter_w(machine(), 0, data & 0x400);
279	283	}
280	284
281	285	/***************************
r14845	r14846
284	288
285	289	static ADDRESS_MAP_START( magic10_map, AS_PROGRAM, 16, magic10_state )
286	290	AM_RANGE(0x000000, 0x03ffff) AM_ROM
287		AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE_LEGACY(layer1_videoram_w) AM_BASE(m_layer1_videoram)
288		AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE_LEGACY(layer0_videoram_w) AM_BASE(m_layer0_videoram)
289		AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE_LEGACY(layer2_videoram_w) AM_BASE(m_layer2_videoram)
	291	AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_BASE(m_layer1_videoram)
	292	AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_BASE(m_layer0_videoram)
	293	AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_BASE(m_layer2_videoram)
290	294	AM_RANGE(0x200000, 0x2007ff) AM_RAM AM_SHARE("nvram")
291		AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE_LEGACY(paletteram_w) AM_BASE_GENERIC(paletteram)
	295	AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE(paletteram_w) AM_BASE_GENERIC(paletteram)
292	296	AM_RANGE(0x400000, 0x400001) AM_READ_PORT("INPUTS")
293	297	AM_RANGE(0x400002, 0x400003) AM_READ_PORT("DSW")
294		AM_RANGE(0x400008, 0x400009) AM_WRITE_LEGACY(magic10_out_w)
	298	AM_RANGE(0x400008, 0x400009) AM_WRITE(magic10_out_w)
295	299	AM_RANGE(0x40000a, 0x40000b) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
296	300	AM_RANGE(0x40000e, 0x40000f) AM_WRITENOP
297	301	AM_RANGE(0x400080, 0x400087) AM_RAM AM_BASE(m_vregs)
r14845	r14846
300	304
301	305	static ADDRESS_MAP_START( magic10a_map, AS_PROGRAM, 16, magic10_state )
302	306	AM_RANGE(0x000000, 0x03ffff) AM_ROM
303		AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE_LEGACY(layer1_videoram_w) AM_BASE(m_layer1_videoram)
304		AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE_LEGACY(layer0_videoram_w) AM_BASE(m_layer0_videoram)
305		AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE_LEGACY(layer2_videoram_w) AM_BASE(m_layer2_videoram)
	307	AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_BASE(m_layer1_videoram)
	308	AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_BASE(m_layer0_videoram)
	309	AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_BASE(m_layer2_videoram)
306	310	AM_RANGE(0x200000, 0x2007ff) AM_RAM AM_SHARE("nvram")
307		AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE_LEGACY(paletteram_w) AM_BASE_GENERIC(paletteram)
	311	AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE(paletteram_w) AM_BASE_GENERIC(paletteram)
308	312	AM_RANGE(0x500000, 0x500001) AM_READ_PORT("INPUTS")
309	313	AM_RANGE(0x500002, 0x500003) AM_READ_PORT("DSW")
310		AM_RANGE(0x500008, 0x500009) AM_WRITE_LEGACY(magic10_out_w)
	314	AM_RANGE(0x500008, 0x500009) AM_WRITE(magic10_out_w)
311	315	AM_RANGE(0x50000a, 0x50000b) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
312	316	AM_RANGE(0x50000e, 0x50000f) AM_WRITENOP
313	317	AM_RANGE(0x500080, 0x500087) AM_RAM AM_BASE(m_vregs)   // video registers?
r14845	r14846
316	320
317	321	static ADDRESS_MAP_START( magic102_map, AS_PROGRAM, 16, magic10_state )
318	322	AM_RANGE(0x000000, 0x03ffff) AM_ROM
319		AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE_LEGACY(layer1_videoram_w) AM_BASE(m_layer1_videoram)
320		AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE_LEGACY(layer0_videoram_w) AM_BASE(m_layer0_videoram)
321		AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE_LEGACY(layer2_videoram_w) AM_BASE(m_layer2_videoram)
	323	AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_BASE(m_layer1_videoram)
	324	AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_BASE(m_layer0_videoram)
	325	AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_BASE(m_layer2_videoram)
322	326	AM_RANGE(0x200000, 0x2007ff) AM_RAM AM_SHARE("nvram")
323		AM_RANGE(0x400000, 0x4001ff) AM_RAM_WRITE_LEGACY(paletteram_w) AM_BASE_GENERIC(paletteram)
324		AM_RANGE(0x500000, 0x500001) AM_READ_LEGACY(magic102_r)
	327	AM_RANGE(0x400000, 0x4001ff) AM_RAM_WRITE(paletteram_w) AM_BASE_GENERIC(paletteram)
	328	AM_RANGE(0x500000, 0x500001) AM_READ(magic102_r)
325	329	AM_RANGE(0x500004, 0x500005) AM_READNOP // gives credits
326	330	AM_RANGE(0x500006, 0x500007) AM_READNOP // gives credits
327	331	AM_RANGE(0x50001a, 0x50001b) AM_READ_PORT("IN0")
r14845	r14846
335	339
336	340	static ADDRESS_MAP_START( hotslot_map, AS_PROGRAM, 16, magic10_state )
337	341	AM_RANGE(0x000000, 0x03ffff) AM_ROM
338		AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE_LEGACY(layer1_videoram_w) AM_BASE(m_layer1_videoram)
339		AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE_LEGACY(layer0_videoram_w) AM_BASE(m_layer0_videoram)
340		AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE_LEGACY(layer2_videoram_w) AM_BASE(m_layer2_videoram)
	342	AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_BASE(m_layer1_videoram)
	343	AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_BASE(m_layer0_videoram)
	344	AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_BASE(m_layer2_videoram)
341	345	AM_RANGE(0x200000, 0x2007ff) AM_RAM AM_SHARE("nvram")
342		AM_RANGE(0x400000, 0x4001ff) AM_RAM_WRITE_LEGACY(paletteram_w) AM_BASE_GENERIC(paletteram)
343		AM_RANGE(0x500004, 0x500005) AM_READWRITE_LEGACY(hotslot_copro_r, hotslot_copro_w)   // copro comm
	346	AM_RANGE(0x400000, 0x4001ff) AM_RAM_WRITE(paletteram_w) AM_BASE_GENERIC(paletteram)
	347	AM_RANGE(0x500004, 0x500005) AM_READWRITE(hotslot_copro_r, hotslot_copro_w)   // copro comm
344	348	AM_RANGE(0x500006, 0x500011) AM_RAM
345	349	AM_RANGE(0x500012, 0x500013) AM_READ_PORT("IN0")
346	350	AM_RANGE(0x500014, 0x500015) AM_READ_PORT("IN1")
r14845	r14846
354	358
355	359	static ADDRESS_MAP_START( sgsafari_map, AS_PROGRAM, 16, magic10_state )
356	360	AM_RANGE(0x000000, 0x03ffff) AM_ROM
357		AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE_LEGACY(layer1_videoram_w) AM_BASE(m_layer1_videoram)
358		AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE_LEGACY(layer0_videoram_w) AM_BASE(m_layer0_videoram)
359		AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE_LEGACY(layer2_videoram_w) AM_BASE(m_layer2_videoram)
	361	AM_RANGE(0x100000, 0x100fff) AM_RAM_WRITE(layer1_videoram_w) AM_BASE(m_layer1_videoram)
	362	AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(layer0_videoram_w) AM_BASE(m_layer0_videoram)
	363	AM_RANGE(0x102000, 0x103fff) AM_RAM_WRITE(layer2_videoram_w) AM_BASE(m_layer2_videoram)
360	364	AM_RANGE(0x200000, 0x203fff) AM_RAM AM_SHARE("nvram")
361		AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE_LEGACY(paletteram_w) AM_BASE_GENERIC(paletteram)
	365	AM_RANGE(0x300000, 0x3001ff) AM_RAM_WRITE(paletteram_w) AM_BASE_GENERIC(paletteram)
362	366	AM_RANGE(0x500002, 0x500003) AM_READ_PORT("DSW1")
363		AM_RANGE(0x500008, 0x500009) AM_WRITE_LEGACY(magic10_out_w)
	367	AM_RANGE(0x500008, 0x500009) AM_WRITE(magic10_out_w)
364	368	AM_RANGE(0x50000a, 0x50000b) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
365	369	AM_RANGE(0x50000e, 0x50000f) AM_READ_PORT("IN0")
366	370	AM_RANGE(0x500080, 0x500087) AM_RAM AM_BASE(m_vregs)   // video registers?

src/mame/drivers/kongambl.c

r14845	r14846
25	25	kongambl_state(const machine_config &mconfig, device_type type, const char *tag)
26	26	: driver_device(mconfig, type, tag) { }
27	27
	28	DECLARE_READ32_MEMBER(eeprom_r);
	29	DECLARE_WRITE32_MEMBER(eeprom_w);
28	30	};
29	31
30	32
r14845	r14846
53	55	return 0;
54	56	}
55	57
56		static READ32_HANDLER( eeprom_r )
	58	READ32_MEMBER(kongambl_state::eeprom_r)
57	59	{
58	60	if (ACCESSING_BITS_0_7)
59	61	{
60		UINT32 rv = input_port_read(space->machine(), "SYSTEM") & ~0x1;
	62	UINT32 rv = input_port_read(machine(), "SYSTEM") & ~0x1;
61	63
62	64	return rv;   // bit 0 freezes the game if 1
63	65	}
r14845	r14846
65	67	return 0;
66	68	}
67	69
68		static WRITE32_HANDLER( eeprom_w )
	70	WRITE32_MEMBER(kongambl_state::eeprom_w)
69	71	{
70	72	if (ACCESSING_BITS_8_15)
71	73	{
72		input_port_write(space->machine(), "EEPROMOUT", (data>>8)&0xf, 0xff);
	74	input_port_write(machine(), "EEPROMOUT", (data>>8)&0xf, 0xff);
73	75	}
74	76	}
75	77
r14845	r14846
87	89
88	90	AM_RANGE(0x480000, 0x48003f) AM_DEVWRITE_LEGACY("k056832", k056832_long_w)
89	91
90		AM_RANGE(0x700000, 0x700003) AM_READ_LEGACY(eeprom_r )
91		AM_RANGE(0x780000, 0x780003) AM_WRITE_LEGACY(eeprom_w )
	92	AM_RANGE(0x700000, 0x700003) AM_READ(eeprom_r )
	93	AM_RANGE(0x780000, 0x780003) AM_WRITE(eeprom_w )
92	94	ADDRESS_MAP_END
93	95
94	96

src/mame/drivers/mogura.c

r14845	r14846
22	22	device_t *m_maincpu;
23	23	device_t *m_dac1;
24	24	device_t *m_dac2;
	25	DECLARE_WRITE8_MEMBER(mogura_tileram_w);
	26	DECLARE_WRITE8_MEMBER(mogura_dac_w);
	27	DECLARE_WRITE8_MEMBER(mogura_gfxram_w);
25	28	};
26	29
27	30
r14845	r14846
97	100	return 0;
98	101	}
99	102
100		static WRITE8_HANDLER( mogura_tileram_w )
	103	WRITE8_MEMBER(mogura_state::mogura_tileram_w)
101	104	{
102		mogura_state *state = space->machine().driver_data<mogura_state>();
103		state->m_tileram[offset] = data;
104		state->m_tilemap->mark_tile_dirty(offset & 0x7ff);
	105	m_tileram[offset] = data;
	106	m_tilemap->mark_tile_dirty(offset & 0x7ff);
105	107	}
106	108
107		static WRITE8_HANDLER(mogura_dac_w)
	109	WRITE8_MEMBER(mogura_state::mogura_dac_w)
108	110	{
109		mogura_state *state = space->machine().driver_data<mogura_state>();
110		dac_data_w(state->m_dac1, data & 0xf0);   /* left */
111		dac_data_w(state->m_dac2, (data & 0x0f) << 4);   /* right */
	111	dac_data_w(m_dac1, data & 0xf0);   /* left */
	112	dac_data_w(m_dac2, (data & 0x0f) << 4);   /* right */
112	113	}
113	114
114	115
115		static WRITE8_HANDLER ( mogura_gfxram_w )
	116	WRITE8_MEMBER(mogura_state::mogura_gfxram_w)
116	117	{
117		mogura_state *state = space->machine().driver_data<mogura_state>();
118		state->m_gfxram[offset] = data ;
	118	m_gfxram[offset] = data ;
119	119
120		gfx_element_mark_dirty(space->machine().gfx[0], offset / 16);
	120	gfx_element_mark_dirty(machine().gfx[0], offset / 16);
121	121	}
122	122
123	123
124	124	static ADDRESS_MAP_START( mogura_map, AS_PROGRAM, 8, mogura_state )
125	125	AM_RANGE(0x0000, 0x7fff) AM_ROM
126	126	AM_RANGE(0xc000, 0xdfff) AM_RAM // main ram
127		AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE_LEGACY(mogura_gfxram_w) AM_BASE(m_gfxram) // ram based characters
128		AM_RANGE(0xf000, 0xffff) AM_RAM_WRITE_LEGACY(mogura_tileram_w) AM_BASE(m_tileram) // tilemap
	127	AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE(mogura_gfxram_w) AM_BASE(m_gfxram) // ram based characters
	128	AM_RANGE(0xf000, 0xffff) AM_RAM_WRITE(mogura_tileram_w) AM_BASE(m_tileram) // tilemap
129	129	ADDRESS_MAP_END
130	130
131	131	static ADDRESS_MAP_START( mogura_io_map, AS_IO, 8, mogura_state )
r14845	r14846
137	137	AM_RANGE(0x0e, 0x0e) AM_READ_PORT("P3")
138	138	AM_RANGE(0x0f, 0x0f) AM_READ_PORT("P4")
139	139	AM_RANGE(0x10, 0x10) AM_READ_PORT("SERVICE")
140		AM_RANGE(0x14, 0x14) AM_WRITE_LEGACY(mogura_dac_w)   /* 4 bit DAC x 2. MSB = left, LSB = right */
	140	AM_RANGE(0x14, 0x14) AM_WRITE(mogura_dac_w)   /* 4 bit DAC x 2. MSB = left, LSB = right */
141	141	ADDRESS_MAP_END
142	142
143	143	static INPUT_PORTS_START( mogura )

src/mame/drivers/ddealer.c

r14845	r14846
138	138	/* misc */
139	139	UINT8    m_input_pressed;
140	140	UINT16   m_coin_input;
	141	DECLARE_WRITE16_MEMBER(ddealer_flipscreen_w);
	142	DECLARE_WRITE16_MEMBER(back_vram_w);
	143	DECLARE_WRITE16_MEMBER(ddealer_vregs_w);
	144	DECLARE_WRITE16_MEMBER(ddealer_mcu_shared_w);
	145	DECLARE_READ16_MEMBER(ddealer_mcu_r);
141	146	};
142	147
143	148
144	149
145		static WRITE16_HANDLER( ddealer_flipscreen_w )
	150	WRITE16_MEMBER(ddealer_state::ddealer_flipscreen_w)
146	151	{
147		ddealer_state *state = space->machine().driver_data<ddealer_state>();
148		state->m_flipscreen = data & 0x01;
	152	m_flipscreen = data & 0x01;
149	153	}
150	154
151	155	static TILE_GET_INFO( get_back_tile_info )
r14845	r14846
358	362
359	363
360	364
361		static WRITE16_HANDLER( back_vram_w )
	365	WRITE16_MEMBER(ddealer_state::back_vram_w)
362	366	{
363		ddealer_state *state = space->machine().driver_data<ddealer_state>();
364		COMBINE_DATA(&state->m_back_vram[offset]);
365		state->m_back_tilemap->mark_tile_dirty(offset);
	367	COMBINE_DATA(&m_back_vram[offset]);
	368	m_back_tilemap->mark_tile_dirty(offset);
366	369	}
367	370
368	371
369		static WRITE16_HANDLER( ddealer_vregs_w )
	372	WRITE16_MEMBER(ddealer_state::ddealer_vregs_w)
370	373	{
371		ddealer_state *state = space->machine().driver_data<ddealer_state>();
372		COMBINE_DATA(&state->m_vregs[offset]);
	374	COMBINE_DATA(&m_vregs[offset]);
373	375	}
374	376
375	377	/******************************************************************************************************
r14845	r14846
379	381	******************************************************************************************************/
380	382
381	383	#define PROT_JSR(_offs_,_protvalue_,_pc_) \
382		if(state->m_mcu_shared_ram[(_offs_)/2] == _protvalue_) \
	384	if(m_mcu_shared_ram[(_offs_)/2] == _protvalue_) \
383	385	{ \
384		state->m_mcu_shared_ram[(_offs_)/2] = 0xffff;  /*(MCU job done)*/ \
385		state->m_mcu_shared_ram[(_offs_+2-0x10)/2] = 0x4ef9;/*JMP*/\
386		state->m_mcu_shared_ram[(_offs_+4-0x10)/2] = 0x0000;/*HI-DWORD*/\
387		state->m_mcu_shared_ram[(_offs_+6-0x10)/2] = _pc_;  /*LO-DWORD*/\
	386	m_mcu_shared_ram[(_offs_)/2] = 0xffff;  /*(MCU job done)*/ \
	387	m_mcu_shared_ram[(_offs_+2-0x10)/2] = 0x4ef9;/*JMP*/\
	388	m_mcu_shared_ram[(_offs_+4-0x10)/2] = 0x0000;/*HI-DWORD*/\
	389	m_mcu_shared_ram[(_offs_+6-0x10)/2] = _pc_;  /*LO-DWORD*/\
388	390	} \
389	391
390	392	#define PROT_INPUT(_offs_,_protvalue_,_protinput_,_input_) \
391		if(state->m_mcu_shared_ram[_offs_] == _protvalue_) \
	393	if(m_mcu_shared_ram[_offs_] == _protvalue_) \
392	394	{\
393		state->m_mcu_shared_ram[_protinput_] = ((_input_ & 0xffff0000)>>16);\
394		state->m_mcu_shared_ram[_protinput_+1] = (_input_ & 0x0000ffff);\
	395	m_mcu_shared_ram[_protinput_] = ((_input_ & 0xffff0000)>>16);\
	396	m_mcu_shared_ram[_protinput_+1] = (_input_ & 0x0000ffff);\
395	397	}
396	398
397		static WRITE16_HANDLER( ddealer_mcu_shared_w )
	399	WRITE16_MEMBER(ddealer_state::ddealer_mcu_shared_w)
398	400	{
399		ddealer_state *state = space->machine().driver_data<ddealer_state>();
400		COMBINE_DATA(&state->m_mcu_shared_ram[offset]);
	401	COMBINE_DATA(&m_mcu_shared_ram[offset]);
401	402
402	403	switch(offset)
403	404	{
r14845	r14846
429	430	case 0x4fe/2: PROT_JSR(0x4fe,0x8018,0x9818); break;
430	431	/*Start-up vector,I think that only the first ram address can be written by the main CPU,or it is a whole sequence.*/
431	432	case 0x000/2:
432		if (state->m_mcu_shared_ram[0x000 / 2] == 0x60fe)
	433	if (m_mcu_shared_ram[0x000 / 2] == 0x60fe)
433	434	{
434		state->m_mcu_shared_ram[0x000 / 2] = 0x0000;//coin counter
435		state->m_mcu_shared_ram[0x002 / 2] = 0x0000;//coin counter "decimal point"
436		state->m_mcu_shared_ram[0x004 / 2] = 0x4ef9;
	435	m_mcu_shared_ram[0x000 / 2] = 0x0000;//coin counter
	436	m_mcu_shared_ram[0x002 / 2] = 0x0000;//coin counter "decimal point"
	437	m_mcu_shared_ram[0x004 / 2] = 0x4ef9;
437	438	}
438	439	break;
439	440	case 0x002/2:
440	441	case 0x004/2:
441		if (state->m_mcu_shared_ram[0x002 / 2] == 0x0000 && state->m_mcu_shared_ram[0x004 / 2] == 0x0214)
442		state->m_mcu_shared_ram[0x004 / 2] = 0x4ef9;
	442	if (m_mcu_shared_ram[0x002 / 2] == 0x0000 && m_mcu_shared_ram[0x004 / 2] == 0x0214)
	443	m_mcu_shared_ram[0x004 / 2] = 0x4ef9;
443	444	break;
444	445	case 0x008/2:
445		if (state->m_mcu_shared_ram[0x008 / 2] == 0x000f)
446		state->m_mcu_shared_ram[0x008 / 2] = 0x0604;
	446	if (m_mcu_shared_ram[0x008 / 2] == 0x000f)
	447	m_mcu_shared_ram[0x008 / 2] = 0x0604;
447	448	break;
448	449	case 0x00c/2:
449		if (state->m_mcu_shared_ram[0x00c / 2] == 0x000f)
450		state->m_mcu_shared_ram[0x00c / 2] = 0x0000;
	450	if (m_mcu_shared_ram[0x00c / 2] == 0x000f)
	451	m_mcu_shared_ram[0x00c / 2] = 0x0000;
451	452	break;
452	453	}
453	454	}
r14845	r14846
460	461	AM_RANGE(0x08000a, 0x08000b) AM_READ_PORT("UNK")
461	462	AM_RANGE(0x084000, 0x084003) AM_DEVWRITE8_LEGACY("ymsnd", ym2203_w, 0x00ff) // ym ?
462	463	AM_RANGE(0x088000, 0x0887ff) AM_RAM_WRITE_LEGACY(paletteram16_RRRRGGGGBBBBRGBx_word_w) AM_BASE_GENERIC(paletteram) // palette ram
463		AM_RANGE(0x08c000, 0x08cfff) AM_RAM_WRITE_LEGACY(ddealer_vregs_w) AM_BASE(m_vregs) // palette ram
	464	AM_RANGE(0x08c000, 0x08cfff) AM_RAM_WRITE(ddealer_vregs_w) AM_BASE(m_vregs) // palette ram
464	465
465	466	/* this might actually be 1 tilemap with some funky rowscroll / columnscroll enabled, I'm not sure */
466	467	AM_RANGE(0x090000, 0x090fff) AM_RAM AM_BASE(m_left_fg_vram_top)
r14845	r14846
468	469	AM_RANGE(0x092000, 0x092fff) AM_RAM AM_BASE(m_left_fg_vram_bottom)
469	470	AM_RANGE(0x093000, 0x093fff) AM_RAM AM_BASE(m_right_fg_vram_bottom)
470	471	//AM_RANGE(0x094000, 0x094001) AM_NOP // always 0?
471		AM_RANGE(0x098000, 0x098001) AM_WRITE_LEGACY(ddealer_flipscreen_w)
472		AM_RANGE(0x09c000, 0x09cfff) AM_RAM_WRITE_LEGACY(back_vram_w) AM_BASE(m_back_vram) // bg tilemap
	472	AM_RANGE(0x098000, 0x098001) AM_WRITE(ddealer_flipscreen_w)
	473	AM_RANGE(0x09c000, 0x09cfff) AM_RAM_WRITE(back_vram_w) AM_BASE(m_back_vram) // bg tilemap
473	474	AM_RANGE(0x0f0000, 0x0fdfff) AM_RAM AM_BASE(m_work_ram)
474		AM_RANGE(0x0fe000, 0x0fefff) AM_RAM_WRITE_LEGACY(ddealer_mcu_shared_w) AM_BASE(m_mcu_shared_ram)
	475	AM_RANGE(0x0fe000, 0x0fefff) AM_RAM_WRITE(ddealer_mcu_shared_w) AM_BASE(m_mcu_shared_ram)
475	476	AM_RANGE(0x0ff000, 0x0fffff) AM_RAM
476	477	ADDRESS_MAP_END
477	478
r14845	r14846
647	648
648	649
649	650
650		static READ16_HANDLER( ddealer_mcu_r )
	651	READ16_MEMBER(ddealer_state::ddealer_mcu_r)
651	652	{
652		ddealer_state *state = space->machine().driver_data<ddealer_state>();
653	653	static const int resp[] =
654	654	{
655	655	0x93, 0xc7, 0x00, 0x8000,
r14845	r14846
661	661
662	662	int res;
663	663
664		res = resp[state->m_respcount++];
665		if (resp[state->m_respcount] < 0)
666		state->m_respcount = 0;
	664	res = resp[m_respcount++];
	665	if (resp[m_respcount] < 0)
	666	m_respcount = 0;
667	667
668	668	return res;
669	669	}
670	670
671	671	static DRIVER_INIT( ddealer )
672	672	{
673		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xfe01c, 0xfe01d, FUNC(ddealer_mcu_r) );
	673	ddealer_state *state = machine.driver_data<ddealer_state>();
	674	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0xfe01c, 0xfe01d, read16_delegate(FUNC(ddealer_state::ddealer_mcu_r), state));
674	675	}
675	676
676	677	ROM_START( ddealer )

src/mame/drivers/berzerk.c

r14845	r14846
37	37	int m_p1_direction;
38	38	int m_p2_counter_74ls161;
39	39	int m_p2_direction;
	40	DECLARE_READ8_MEMBER(led_on_r);
	41	DECLARE_WRITE8_MEMBER(led_on_w);
	42	DECLARE_READ8_MEMBER(led_off_r);
	43	DECLARE_WRITE8_MEMBER(led_off_w);
	44	DECLARE_WRITE8_MEMBER(irq_enable_w);
	45	DECLARE_WRITE8_MEMBER(nmi_enable_w);
	46	DECLARE_WRITE8_MEMBER(nmi_disable_w);
	47	DECLARE_READ8_MEMBER(nmi_enable_r);
	48	DECLARE_READ8_MEMBER(nmi_disable_r);
	49	DECLARE_WRITE8_MEMBER(magicram_w);
	50	DECLARE_WRITE8_MEMBER(magicram_control_w);
	51	DECLARE_READ8_MEMBER(intercept_v256_r);
	52	DECLARE_WRITE8_MEMBER(berzerk_audio_w);
	53	DECLARE_READ8_MEMBER(berzerk_audio_r);
	54	DECLARE_READ8_MEMBER(moonwarp_p1_r);
	55	DECLARE_READ8_MEMBER(moonwarp_p2_r);
40	56	};
41	57
42	58
r14845	r14846
70	86	*
71	87	*************************************/
72	88
73		static READ8_HANDLER( led_on_r )
	89	READ8_MEMBER(berzerk_state::led_on_r)
74	90	{
75		set_led_status(space->machine(), 0, 1);
	91	set_led_status(machine(), 0, 1);
76	92
77	93	return 0;
78	94	}
79	95
80	96
81		static WRITE8_HANDLER( led_on_w )
	97	WRITE8_MEMBER(berzerk_state::led_on_w)
82	98	{
83		set_led_status(space->machine(), 0, 1);
	99	set_led_status(machine(), 0, 1);
84	100	}
85	101
86	102
87		static READ8_HANDLER( led_off_r )
	103	READ8_MEMBER(berzerk_state::led_off_r)
88	104	{
89		set_led_status(space->machine(), 0, 0);
	105	set_led_status(machine(), 0, 0);
90	106
91	107	return 0;
92	108	}
93	109
94	110
95		static WRITE8_HANDLER( led_off_w )
	111	WRITE8_MEMBER(berzerk_state::led_off_w)
96	112	{
97		set_led_status(space->machine(), 0, 0);
	113	set_led_status(machine(), 0, 0);
98	114	}
99	115
100	116
r14845	r14846
153	169	*
154	170	*************************************/
155	171
156		static WRITE8_HANDLER( irq_enable_w )
	172	WRITE8_MEMBER(berzerk_state::irq_enable_w)
157	173	{
158		berzerk_state *state = space->machine().driver_data<berzerk_state>();
159		state->m_irq_enabled = data & 0x01;
	174	m_irq_enabled = data & 0x01;
160	175	}
161	176
162	177
r14845	r14846
212	227	*
213	228	*************************************/
214	229
215		static WRITE8_HANDLER( nmi_enable_w )
	230	WRITE8_MEMBER(berzerk_state::nmi_enable_w)
216	231	{
217		berzerk_state *state = space->machine().driver_data<berzerk_state>();
218		state->m_nmi_enabled = 1;
	232	m_nmi_enabled = 1;
219	233	}
220	234
221	235
222		static WRITE8_HANDLER( nmi_disable_w )
	236	WRITE8_MEMBER(berzerk_state::nmi_disable_w)
223	237	{
224		berzerk_state *state = space->machine().driver_data<berzerk_state>();
225		state->m_nmi_enabled = 0;
	238	m_nmi_enabled = 0;
226	239	}
227	240
228	241
229		static READ8_HANDLER( nmi_enable_r )
	242	READ8_MEMBER(berzerk_state::nmi_enable_r)
230	243	{
231		berzerk_state *state = space->machine().driver_data<berzerk_state>();
232		state->m_nmi_enabled = 1;
	244	m_nmi_enabled = 1;
233	245
234	246	return 0;
235	247	}
236	248
237	249
238		static READ8_HANDLER( nmi_disable_r )
	250	READ8_MEMBER(berzerk_state::nmi_disable_r)
239	251	{
240		berzerk_state *state = space->machine().driver_data<berzerk_state>();
241		state->m_nmi_enabled = 0;
	252	m_nmi_enabled = 0;
242	253
243	254	return 0;
244	255	}
r14845	r14846
347	358	}
348	359
349	360
350		static WRITE8_HANDLER( magicram_w )
	361	WRITE8_MEMBER(berzerk_state::magicram_w)
351	362	{
352		berzerk_state *state = space->machine().driver_data<berzerk_state>();
353	363	UINT8 alu_output;
354	364
355		UINT8 current_video_data = state->m_videoram[offset];
	365	UINT8 current_video_data = m_videoram[offset];
356	366
357	367	/* shift data towards LSB.  MSB bits are filled by data from last_shift_data.
358	368	The shifter consists of 5 74153 devices @ 7A, 8A, 9A, 10A and 11A,
359	369	followed by 4 more 153's at 11B, 10B, 9B and 8B, which optionally
360	370	reverse the order of the resulting bits */
361		UINT8 shift_flop_output = (((UINT16)state->m_last_shift_data << 8) | data) >> (state->m_magicram_control & 0x07);
	371	UINT8 shift_flop_output = (((UINT16)m_last_shift_data << 8) | data) >> (m_magicram_control & 0x07);
362	372
363		if (state->m_magicram_control & 0x08)
	373	if (m_magicram_control & 0x08)
364	374	shift_flop_output = BITSWAP8(shift_flop_output, 0, 1, 2, 3, 4, 5, 6, 7);
365	375
366	376	/* collision detection - AND gate output goes to the K pin of the flip-flop,
367	377	while J is LO, therefore, it only resets, never sets */
368	378	if (shift_flop_output & current_video_data)
369		state->m_intercept = 0;
	379	m_intercept = 0;
370	380
371	381	/* perform ALU step */
372	382	TTL74181_write(LS181_12C, TTL74181_INPUT_A0, 4, shift_flop_output & 0x0f);
373	383	TTL74181_write(LS181_10C, TTL74181_INPUT_A0, 4, shift_flop_output >> 4);
374	384	TTL74181_write(LS181_12C, TTL74181_INPUT_B0, 4, current_video_data & 0x0f);
375	385	TTL74181_write(LS181_10C, TTL74181_INPUT_B0, 4, current_video_data >> 4);
376		TTL74181_write(LS181_12C, TTL74181_INPUT_S0, 4, state->m_magicram_control >> 4);
377		TTL74181_write(LS181_10C, TTL74181_INPUT_S0, 4, state->m_magicram_control >> 4);
	386	TTL74181_write(LS181_12C, TTL74181_INPUT_S0, 4, m_magicram_control >> 4);
	387	TTL74181_write(LS181_10C, TTL74181_INPUT_S0, 4, m_magicram_control >> 4);
378	388
379	389	alu_output = (TTL74181_read(LS181_10C, TTL74181_OUTPUT_F0, 4) << 4) |
380	390	(TTL74181_read(LS181_12C, TTL74181_OUTPUT_F0, 4) << 0);
381	391
382		state->m_videoram[offset] = alu_output ^ 0xff;
	392	m_videoram[offset] = alu_output ^ 0xff;
383	393
384	394	/* save data for next time */
385		state->m_last_shift_data = data & 0x7f;
	395	m_last_shift_data = data & 0x7f;
386	396	}
387	397
388	398
389		static WRITE8_HANDLER( magicram_control_w )
	399	WRITE8_MEMBER(berzerk_state::magicram_control_w)
390	400	{
391		berzerk_state *state = space->machine().driver_data<berzerk_state>();
392	401	/* save the control byte, clear the shift data latch,
393	402	and set the intercept flip-flop */
394		state->m_magicram_control = data;
395		state->m_last_shift_data = 0;
396		state->m_intercept = 1;
	403	m_magicram_control = data;
	404	m_last_shift_data = 0;
	405	m_intercept = 1;
397	406	}
398	407
399	408
400		static READ8_HANDLER( intercept_v256_r )
	409	READ8_MEMBER(berzerk_state::intercept_v256_r)
401	410	{
402		berzerk_state *state = space->machine().driver_data<berzerk_state>();
403	411	UINT8 counter;
404	412	UINT8 v256;
405	413
406		vpos_to_vsync_chain_counter(space->machine().primary_screen->vpos(), &counter, &v256);
	414	vpos_to_vsync_chain_counter(machine().primary_screen->vpos(), &counter, &v256);
407	415
408		return (!state->m_intercept << 7) | v256;
	416	return (!m_intercept << 7) | v256;
409	417	}
410	418
411	419
r14845	r14846
492	500	*
493	501	*************************************/
494	502
495		static WRITE8_HANDLER( berzerk_audio_w )
	503	WRITE8_MEMBER(berzerk_state::berzerk_audio_w)
496	504	{
497	505	device_t *device;
498	506	int clock_divisor;
r14845	r14846
501	509	{
502	510	/* offset 4 writes to the S14001A */
503	511	case 4:
504		device = space->machine().device("speech");
	512	device = machine().device("speech");
505	513	switch (data >> 6)
506	514	{
507	515	/* write data to the S14001 */
r14845	r14846
519	527	break;
520	528
521	529	case 1:
522		device = space->machine().device("speech");
	530	device = machine().device("speech");
523	531	/* volume */
524	532	s14001a_set_volume(device, ((data & 0x38) >> 3) + 1);
525	533
r14845	r14846
537	545
538	546	/* offset 6 writes to the sfxcontrol latch */
539	547	case 6:
540		exidy_sfxctrl_w(space->machine().device("exidy"), data >> 6, data);
	548	exidy_sfxctrl_w(machine().device("exidy"), data >> 6, data);
541	549	break;
542	550
543	551	/* everything else writes to the 6840 */
544	552	default:
545		exidy_sh6840_w(space->machine().device("exidy"), offset, data);
	553	exidy_sh6840_w(machine().device("exidy"), offset, data);
546	554	break;
547	555
548	556	}
549	557	}
550	558
551	559
552		static READ8_HANDLER( berzerk_audio_r )
	560	READ8_MEMBER(berzerk_state::berzerk_audio_r)
553	561	{
554		device_t *device = space->machine().device("speech");
	562	device_t *device = machine().device("speech");
555	563	switch (offset)
556	564	{
557	565	/* offset 4 reads from the S14001A */
r14845	r14846
563	571	return 0;
564	572	/* everything else reads from the 6840 */
565	573	default:
566		return exidy_sh6840_r(space->machine().device("exidy"), offset);
	574	return exidy_sh6840_r(machine().device("exidy"), offset);
567	575	}
568	576	}
569	577
r14845	r14846
572	580	static SOUND_RESET(berzerk)
573	581	{
574	582	address_space *space = machine.device("maincpu")->memory().space(AS_IO);
	583	berzerk_state *state = machine.driver_data<berzerk_state>();
575	584	/* clears the flip-flop controlling the volume and freq on the speech chip */
576		berzerk_audio_w(space, 4, 0x40);
	585	state->berzerk_audio_w(*space, 4, 0x40);
577	586	}
578	587
579	588
r14845	r14846
589	598	AM_RANGE(0x0800, 0x0bff) AM_MIRROR(0x0400) AM_RAM AM_SHARE("nvram")
590	599	AM_RANGE(0x1000, 0x3fff) AM_ROM
591	600	AM_RANGE(0x4000, 0x5fff) AM_RAM AM_BASE(m_videoram) AM_SIZE(m_videoram_size) AM_SHARE("share1")
592		AM_RANGE(0x6000, 0x7fff) AM_RAM_WRITE_LEGACY(magicram_w) AM_SHARE("share1")
	601	AM_RANGE(0x6000, 0x7fff) AM_RAM_WRITE(magicram_w) AM_SHARE("share1")
593	602	AM_RANGE(0x8000, 0x87ff) AM_MIRROR(0x3800) AM_RAM AM_BASE(m_colorram)
594	603	AM_RANGE(0xc000, 0xffff) AM_NOP
595	604	ADDRESS_MAP_END
r14845	r14846
598	607	static ADDRESS_MAP_START( frenzy_map, AS_PROGRAM, 8, berzerk_state )
599	608	AM_RANGE(0x0000, 0x3fff) AM_ROM
600	609	AM_RANGE(0x4000, 0x5fff) AM_RAM AM_BASE(m_videoram) AM_SIZE(m_videoram_size) AM_SHARE("share1")
601		AM_RANGE(0x6000, 0x7fff) AM_RAM_WRITE_LEGACY(magicram_w) AM_SHARE("share1")
	610	AM_RANGE(0x6000, 0x7fff) AM_RAM_WRITE(magicram_w) AM_SHARE("share1")
602	611	AM_RANGE(0x8000, 0x87ff) AM_MIRROR(0x3800) AM_RAM AM_BASE(m_colorram)
603	612	AM_RANGE(0xc000, 0xcfff) AM_ROM
604	613	AM_RANGE(0xf800, 0xfbff) AM_MIRROR(0x0400) AM_RAM AM_SHARE("nvram")
r14845	r14846
615	624	static ADDRESS_MAP_START( berzerk_io_map, AS_IO, 8, berzerk_state )
616	625	ADDRESS_MAP_GLOBAL_MASK(0xff)
617	626	AM_RANGE(0x00, 0x3f) AM_NOP
618		AM_RANGE(0x40, 0x47) AM_READWRITE_LEGACY(berzerk_audio_r, berzerk_audio_w)
	627	AM_RANGE(0x40, 0x47) AM_READWRITE(berzerk_audio_r, berzerk_audio_w)
619	628	AM_RANGE(0x48, 0x48) AM_READ_PORT("P1") AM_WRITENOP
620	629	AM_RANGE(0x49, 0x49) AM_READ_PORT("SYSTEM") AM_WRITENOP
621	630	AM_RANGE(0x4a, 0x4a) AM_READ_PORT("P2") AM_WRITENOP
622		AM_RANGE(0x4b, 0x4b) AM_READNOP AM_WRITE_LEGACY(magicram_control_w)
623		AM_RANGE(0x4c, 0x4c) AM_READWRITE_LEGACY(nmi_enable_r, nmi_enable_w)
624		AM_RANGE(0x4d, 0x4d) AM_READWRITE_LEGACY(nmi_disable_r, nmi_disable_w)
625		AM_RANGE(0x4e, 0x4e) AM_READ_LEGACY(intercept_v256_r) AM_WRITENOP // note reading from here should clear pending frame interrupts, see zfb-1.tiff 74ls74 at 3D pin 13 /CLR
626		AM_RANGE(0x4f, 0x4f) AM_READNOP AM_WRITE_LEGACY(irq_enable_w)
	631	AM_RANGE(0x4b, 0x4b) AM_READNOP AM_WRITE(magicram_control_w)
	632	AM_RANGE(0x4c, 0x4c) AM_READWRITE(nmi_enable_r, nmi_enable_w)
	633	AM_RANGE(0x4d, 0x4d) AM_READWRITE(nmi_disable_r, nmi_disable_w)
	634	AM_RANGE(0x4e, 0x4e) AM_READ(intercept_v256_r) AM_WRITENOP // note reading from here should clear pending frame interrupts, see zfb-1.tiff 74ls74 at 3D pin 13 /CLR
	635	AM_RANGE(0x4f, 0x4f) AM_READNOP AM_WRITE(irq_enable_w)
627	636	AM_RANGE(0x50, 0x57) AM_NOP /* second sound board, initialized but not used */
628	637	AM_RANGE(0x58, 0x5f) AM_NOP
629	638	AM_RANGE(0x60, 0x60) AM_MIRROR(0x18) AM_READ_PORT("F3") AM_WRITENOP
r14845	r14846
632	641	AM_RANGE(0x63, 0x63) AM_MIRROR(0x18) AM_READ_PORT("F5") AM_WRITENOP
633	642	AM_RANGE(0x64, 0x64) AM_MIRROR(0x18) AM_READ_PORT("F4") AM_WRITENOP
634	643	AM_RANGE(0x65, 0x65) AM_MIRROR(0x18) AM_READ_PORT("SW2") AM_WRITENOP
635		AM_RANGE(0x66, 0x66) AM_MIRROR(0x18) AM_READWRITE_LEGACY(led_off_r, led_off_w)
636		AM_RANGE(0x67, 0x67) AM_MIRROR(0x18) AM_READWRITE_LEGACY(led_on_r, led_on_w)
	644	AM_RANGE(0x66, 0x66) AM_MIRROR(0x18) AM_READWRITE(led_off_r, led_off_w)
	645	AM_RANGE(0x67, 0x67) AM_MIRROR(0x18) AM_READWRITE(led_on_r, led_on_w)
637	646	AM_RANGE(0x80, 0xff) AM_NOP
638	647	ADDRESS_MAP_END
639	648
r14845	r14846
885	894	PORT_DIPSETTING(    0xff, "255" )
886	895	INPUT_PORTS_END
887	896
888		static READ8_HANDLER( moonwarp_p1_r )
	897	READ8_MEMBER(berzerk_state::moonwarp_p1_r)
889	898	{
890		berzerk_state *state = space->machine().driver_data<berzerk_state>();
891	899	// This seems to be the same type of dial as the later 'moon war 2' set uses
892	900	// see http://www.cityofberwyn.com/schematics/stern/MoonWar_opto.tiff for schematic
893	901	// I.e. a 74ls161 counts from 0 to 15 which is the absolute number of bars passed on the quadrature
894	902	// one difference is it lacks the strobe input (does it?), which if not active causes
895	903	// the dial input to go open bus. This is used in moon war 2 to switch between player 1
896	904	// and player 2 dials, which share a single port. moonwarp uses separate ports for the dials.
897		signed char dialread = input_port_read(space->machine(),"P1_DIAL");
	905	signed char dialread = input_port_read(machine(),"P1_DIAL");
898	906	UINT8 ret;
899		UINT8 buttons = (input_port_read(space->machine(),"P1")&0xe0);
900		if (dialread < 0) state->m_p1_direction = 0;
901		else if (dialread > 0) state->m_p1_direction = 0x10;
902		state->m_p1_counter_74ls161 += abs(dialread);
903		state->m_p1_counter_74ls161 &= 0xf;
904		ret = state->m_p1_counter_74ls161 | state->m_p1_direction | buttons;
905		//fprintf(stderr, "dialread1: %02x, p1_counter_74ls161: %02x, spinner ret is %02x\n", dialread, state->m_p1_counter_74ls161, ret);
	907	UINT8 buttons = (input_port_read(machine(),"P1")&0xe0);
	908	if (dialread < 0) m_p1_direction = 0;
	909	else if (dialread > 0) m_p1_direction = 0x10;
	910	m_p1_counter_74ls161 += abs(dialread);
	911	m_p1_counter_74ls161 &= 0xf;
	912	ret = m_p1_counter_74ls161 | m_p1_direction | buttons;
	913	//fprintf(stderr, "dialread1: %02x, p1_counter_74ls161: %02x, spinner ret is %02x\n", dialread, m_p1_counter_74ls161, ret);
906	914	return ret;
907	915	}
908	916
909		static READ8_HANDLER( moonwarp_p2_r )
	917	READ8_MEMBER(berzerk_state::moonwarp_p2_r)
910	918	{
911		berzerk_state *state = space->machine().driver_data<berzerk_state>();
912	919	// same as above, but for player 2 in cocktail mode
913		signed char dialread = input_port_read(space->machine(),"P2_DIAL");
	920	signed char dialread = input_port_read(machine(),"P2_DIAL");
914	921	UINT8 ret;
915		UINT8 buttons = (input_port_read(space->machine(),"P2")&0xe0);
916		if (dialread < 0) state->m_p2_direction = 0;
917		else if (dialread > 0) state->m_p2_direction = 0x10;
918		state->m_p2_counter_74ls161 += abs(dialread);
919		state->m_p2_counter_74ls161 &= 0xf;
920		ret = state->m_p2_counter_74ls161 | state->m_p2_direction | buttons;
921		//fprintf(stderr, "dialread2: %02x, p2_counter_74ls161: %02x, spinner ret is %02x\n", dialread, state->m_p2_counter_74ls161, ret);
	922	UINT8 buttons = (input_port_read(machine(),"P2")&0xe0);
	923	if (dialread < 0) m_p2_direction = 0;
	924	else if (dialread > 0) m_p2_direction = 0x10;
	925	m_p2_counter_74ls161 += abs(dialread);
	926	m_p2_counter_74ls161 &= 0xf;
	927	ret = m_p2_counter_74ls161 | m_p2_direction | buttons;
	928	//fprintf(stderr, "dialread2: %02x, p2_counter_74ls161: %02x, spinner ret is %02x\n", dialread, m_p2_counter_74ls161, ret);
922	929	return ret;
923	930	}
924	931
r14845	r14846
1228	1235	static DRIVER_INIT( moonwarp )
1229	1236	{
1230	1237	address_space *io = machine.device("maincpu")->memory().space(AS_IO);
1231		io->install_legacy_read_handler (0x48, 0x48, FUNC(moonwarp_p1_r));
1232		io->install_legacy_read_handler (0x4a, 0x4a, FUNC(moonwarp_p2_r));
	1238	berzerk_state *state = machine.driver_data<berzerk_state>();
	1239	io->install_read_handler (0x48, 0x48, read8_delegate(FUNC(berzerk_state::moonwarp_p1_r), state));
	1240	io->install_read_handler (0x4a, 0x4a, read8_delegate(FUNC(berzerk_state::moonwarp_p2_r), state));
1233	1241	}
1234	1242
1235	1243	/*************************************

src/mame/drivers/vpoker.c

r14845	r14846
120	120
121	121	UINT8 *m_videoram;
122	122	UINT8 m_blit_ram[8];
	123	DECLARE_READ8_MEMBER(blitter_r);
	124	DECLARE_WRITE8_MEMBER(blitter_w);
123	125	};
124	126
125	127
r14845	r14846
153	155	return 0;
154	156	}
155	157
156		static READ8_HANDLER( blitter_r )
	158	READ8_MEMBER(vpoker_state::blitter_r)
157	159	{
158	160	if(offset == 6)
159		return input_port_read(space->machine(), "IN0");
	161	return input_port_read(machine(), "IN0");
160	162
161	163	return 0;
162	164	}
163	165
164		static WRITE8_HANDLER( blitter_w )
	166	WRITE8_MEMBER(vpoker_state::blitter_w)
165	167	{
166		vpoker_state *state = space->machine().driver_data<vpoker_state>();
167		UINT8 *videoram = state->m_videoram;
	168	UINT8 *videoram = m_videoram;
168	169
169		state->m_blit_ram[offset] = data;
	170	m_blit_ram[offset] = data;
170	171
171	172	if(offset == 2)
172	173	{
173	174	int blit_offs;
174	175
175		blit_offs = (state->m_blit_ram[1] & 0x01)<<8|(state->m_blit_ram[2] & 0xff);
	176	blit_offs = (m_blit_ram[1] & 0x01)<<8|(m_blit_ram[2] & 0xff);
176	177
177		videoram[blit_offs] = state->m_blit_ram[0];
178		//      printf("%02x %02x %02x %02x %02x %02x %02x %02x\n",state->m_blit_ram[0],state->m_blit_ram[1],state->m_blit_ram[2],state->m_blit_ram[3],state->m_blit_ram[4],state->m_blit_ram[5],state->m_blit_ram[6],state->m_blit_ram[7]);
	178	videoram[blit_offs] = m_blit_ram[0];
	179	//      printf("%02x %02x %02x %02x %02x %02x %02x %02x\n",m_blit_ram[0],m_blit_ram[1],m_blit_ram[2],m_blit_ram[3],m_blit_ram[4],m_blit_ram[5],m_blit_ram[6],m_blit_ram[7]);
179	180	}
180	181	}
181	182
r14845	r14846
183	184	ADDRESS_MAP_GLOBAL_MASK(0x3fff)
184	185	AM_RANGE(0x0000, 0x01ff) AM_RAM      /* vpoker has 0x100, 5acespkr has 0x200 */
185	186	AM_RANGE(0x0400, 0x0407) AM_DEVREADWRITE("6840ptm", ptm6840_device, read, write)
186		AM_RANGE(0x0800, 0x0807) AM_READ_LEGACY(blitter_r) AM_WRITE_LEGACY(blitter_w)
	187	AM_RANGE(0x0800, 0x0807) AM_READ(blitter_r) AM_WRITE(blitter_w)
187	188	AM_RANGE(0x2000, 0x3fff) AM_ROM
188	189	ADDRESS_MAP_END
189	190

src/mame/drivers/igs009.c

r14845	r14846
47	47	int m_hopper;
48	48	UINT8 m_out[3];
49	49	UINT8 m_igs_magic[2];
	50	DECLARE_WRITE8_MEMBER(gp98_reel1_ram_w);
	51	DECLARE_WRITE8_MEMBER(gp98_reel2_ram_w);
	52	DECLARE_WRITE8_MEMBER(gp98_reel3_ram_w);
	53	DECLARE_WRITE8_MEMBER(gp98_reel4_ram_w);
	54	DECLARE_WRITE8_MEMBER(bg_scroll_w);
	55	DECLARE_WRITE8_MEMBER(fg_tile_w);
	56	DECLARE_WRITE8_MEMBER(fg_color_w);
	57	DECLARE_WRITE8_MEMBER(jingbell_nmi_and_coins_w);
	58	DECLARE_WRITE8_MEMBER(jingbell_video_and_leds_w);
	59	DECLARE_WRITE8_MEMBER(jingbell_leds_w);
	60	DECLARE_WRITE8_MEMBER(jingbell_magic_w);
	61	DECLARE_READ8_MEMBER(jingbell_magic_r);
	62	void show_out();
50	63	};
51	64
52	65
r14845	r14846
56	69
57	70
58	71
59		static WRITE8_HANDLER( gp98_reel1_ram_w )
	72	WRITE8_MEMBER(igs009_state::gp98_reel1_ram_w)
60	73	{
61		igs009_state *state = space->machine().driver_data<igs009_state>();
62		state->m_gp98_reel1_ram[offset] = data;
63		state->m_gp98_reel1_tilemap->mark_tile_dirty(offset);
	74	m_gp98_reel1_ram[offset] = data;
	75	m_gp98_reel1_tilemap->mark_tile_dirty(offset);
64	76	}
65	77
66	78	static TILE_GET_INFO( get_jingbell_reel1_tile_info )
r14845	r14846
89	101	}
90	102
91	103
92		static WRITE8_HANDLER( gp98_reel2_ram_w )
	104	WRITE8_MEMBER(igs009_state::gp98_reel2_ram_w)
93	105	{
94		igs009_state *state = space->machine().driver_data<igs009_state>();
95		state->m_gp98_reel2_ram[offset] = data;
96		state->m_gp98_reel2_tilemap->mark_tile_dirty(offset);
	106	m_gp98_reel2_ram[offset] = data;
	107	m_gp98_reel2_tilemap->mark_tile_dirty(offset);
97	108	}
98	109
99	110	static TILE_GET_INFO( get_jingbell_reel2_tile_info )
r14845	r14846
122	133
123	134
124	135
125		static WRITE8_HANDLER( gp98_reel3_ram_w )
	136	WRITE8_MEMBER(igs009_state::gp98_reel3_ram_w)
126	137	{
127		igs009_state *state = space->machine().driver_data<igs009_state>();
128		state->m_gp98_reel3_ram[offset] = data;
129		state->m_gp98_reel3_tilemap->mark_tile_dirty(offset);
	138	m_gp98_reel3_ram[offset] = data;
	139	m_gp98_reel3_tilemap->mark_tile_dirty(offset);
130	140	}
131	141
132	142	static TILE_GET_INFO( get_jingbell_reel3_tile_info )
r14845	r14846
155	165
156	166
157	167
158		static WRITE8_HANDLER( gp98_reel4_ram_w )
	168	WRITE8_MEMBER(igs009_state::gp98_reel4_ram_w)
159	169	{
160		igs009_state *state = space->machine().driver_data<igs009_state>();
161		state->m_gp98_reel4_ram[offset] = data;
162		state->m_gp98_reel4_tilemap->mark_tile_dirty(offset);
	170	m_gp98_reel4_ram[offset] = data;
	171	m_gp98_reel4_tilemap->mark_tile_dirty(offset);
163	172	}
164	173
165	174	static TILE_GET_INFO( get_jingbell_reel4_tile_info )
r14845	r14846
192	201
193	202
194	203
195		static WRITE8_HANDLER( bg_scroll_w )
	204	WRITE8_MEMBER(igs009_state::bg_scroll_w)
196	205	{
197		igs009_state *state = space->machine().driver_data<igs009_state>();
198		state->m_bg_scroll[offset] = data;
	206	m_bg_scroll[offset] = data;
199	207	//  bg_tilemap->set_scrolly(offset,data);
200	208	}
201	209
r14845	r14846
207	215	SET_TILE_INFO(1, code, (4*(code >> 14)+3), 0);
208	216	}
209	217
210		static WRITE8_HANDLER( fg_tile_w )
	218	WRITE8_MEMBER(igs009_state::fg_tile_w)
211	219	{
212		igs009_state *state = space->machine().driver_data<igs009_state>();
213		state->m_fg_tile_ram[offset] = data;
214		state->m_fg_tilemap->mark_tile_dirty(offset);
	220	m_fg_tile_ram[offset] = data;
	221	m_fg_tilemap->mark_tile_dirty(offset);
215	222	}
216	223
217		static WRITE8_HANDLER( fg_color_w )
	224	WRITE8_MEMBER(igs009_state::fg_color_w)
218	225	{
219		igs009_state *state = space->machine().driver_data<igs009_state>();
220		state->m_fg_color_ram[offset] = data;
221		state->m_fg_tilemap->mark_tile_dirty(offset);
	226	m_fg_color_ram[offset] = data;
	227	m_fg_tilemap->mark_tile_dirty(offset);
222	228	}
223	229
224	230	static VIDEO_START(jingbell)
r14845	r14846
344	350	}
345	351
346	352
347		static void show_out(igs009_state *state)
	353	void igs009_state::show_out()
348	354	{
349	355	#ifdef MAME_DEBUG
350		popmessage("%02x %02x %02x", state->m_out[0], state->m_out[1], state->m_out[2]);
	356	popmessage("%02x %02x %02x", m_out[0], m_out[1], m_out[2]);
351	357	#endif
352	358	}
353	359
354		static WRITE8_HANDLER( jingbell_nmi_and_coins_w )
	360	WRITE8_MEMBER(igs009_state::jingbell_nmi_and_coins_w)
355	361	{
356		igs009_state *state = space->machine().driver_data<igs009_state>();
357		if ((state->m_nmi_enable ^ data) & (~0xdd))
	362	if ((m_nmi_enable ^ data) & (~0xdd))
358	363	{
359		logerror("PC %06X: nmi_and_coins = %02x\n",cpu_get_pc(&space->device()),data);
	364	logerror("PC %06X: nmi_and_coins = %02x\n",cpu_get_pc(&space.device()),data);
360	365	//      popmessage("%02x",data);
361	366	}
362	367
363		coin_counter_w(space->machine(), 0,      data & 0x01);   // coin_a
364		coin_counter_w(space->machine(), 1,      data & 0x04);   // coin_c
365		coin_counter_w(space->machine(), 2,      data & 0x08);   // key in
366		coin_counter_w(space->machine(), 3,      data & 0x10);   // coin state->m_out mech
	368	coin_counter_w(machine(), 0,      data & 0x01);   // coin_a
	369	coin_counter_w(machine(), 1,      data & 0x04);   // coin_c
	370	coin_counter_w(machine(), 2,      data & 0x08);   // key in
	371	coin_counter_w(machine(), 3,      data & 0x10);   // coin m_out mech
367	372
368		set_led_status(space->machine(), 6,      data & 0x40);   // led for coin state->m_out / state->m_hopper active
	373	set_led_status(machine(), 6,      data & 0x40);   // led for coin m_out / m_hopper active
369	374
370		state->m_nmi_enable = data;   //  data & 0x80     // nmi enable?
	375	m_nmi_enable = data;   //  data & 0x80     // nmi enable?
371	376
372		state->m_out[0] = data;
373		show_out(state);
	377	m_out[0] = data;
	378	show_out();
374	379	}
375	380
376		static WRITE8_HANDLER( jingbell_video_and_leds_w )
	381	WRITE8_MEMBER(igs009_state::jingbell_video_and_leds_w)
377	382	{
378		igs009_state *state = space->machine().driver_data<igs009_state>();
379		set_led_status(space->machine(), 4,     data & 0x01);   // start?
380		set_led_status(space->machine(), 5,     data & 0x04);   // l_bet?
	383	set_led_status(machine(), 4,     data & 0x01);   // start?
	384	set_led_status(machine(), 5,     data & 0x04);   // l_bet?
381	385
382		state->m_video_enable   =     data & 0x40;
383		state->m_hopper         =   (~data)& 0x80;
	386	m_video_enable   =     data & 0x40;
	387	m_hopper         =   (~data)& 0x80;
384	388
385		state->m_out[1] = data;
386		show_out(state);
	389	m_out[1] = data;
	390	show_out();
387	391	}
388	392
389		static WRITE8_HANDLER( jingbell_leds_w )
	393	WRITE8_MEMBER(igs009_state::jingbell_leds_w)
390	394	{
391		igs009_state *state = space->machine().driver_data<igs009_state>();
392		set_led_status(space->machine(), 0, data & 0x01);   // stop_1
393		set_led_status(space->machine(), 1, data & 0x02);   // stop_2
394		set_led_status(space->machine(), 2, data & 0x04);   // stop_3
395		set_led_status(space->machine(), 3, data & 0x08);   // stop
	395	set_led_status(machine(), 0, data & 0x01);   // stop_1
	396	set_led_status(machine(), 1, data & 0x02);   // stop_2
	397	set_led_status(machine(), 2, data & 0x04);   // stop_3
	398	set_led_status(machine(), 3, data & 0x08);   // stop
396	399	// data & 0x10?
397	400
398		state->m_out[2] = data;
399		show_out(state);
	401	m_out[2] = data;
	402	show_out();
400	403	}
401	404
402	405
403		static WRITE8_HANDLER( jingbell_magic_w )
	406	WRITE8_MEMBER(igs009_state::jingbell_magic_w)
404	407	{
405		igs009_state *state = space->machine().driver_data<igs009_state>();
406		state->m_igs_magic[offset] = data;
	408	m_igs_magic[offset] = data;
407	409
408	410	if (offset == 0)
409	411	return;
410	412
411		switch(state->m_igs_magic[0])
	413	switch(m_igs_magic[0])
412	414	{
413	415	case 0x01:
414	416	break;
415	417
416	418	default:
417		//          popmessage("magic %x <- %04x",state->m_igs_magic[0],data);
418		logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[0], data);
	419	//          popmessage("magic %x <- %04x",m_igs_magic[0],data);
	420	logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[0], data);
419	421	}
420	422	}
421	423
422		static READ8_HANDLER( jingbell_magic_r )
	424	READ8_MEMBER(igs009_state::jingbell_magic_r)
423	425	{
424		igs009_state *state = space->machine().driver_data<igs009_state>();
425		switch(state->m_igs_magic[0])
	426	switch(m_igs_magic[0])
426	427	{
427	428	case 0x00:
428		if ( !(state->m_igs_magic[1] & 0x01) )   return input_port_read(space->machine(), "DSW1");
429		if ( !(state->m_igs_magic[1] & 0x02) )   return input_port_read(space->machine(), "DSW2");
430		if ( !(state->m_igs_magic[1] & 0x04) )   return input_port_read(space->machine(), "DSW3");
431		if ( !(state->m_igs_magic[1] & 0x08) )   return input_port_read(space->machine(), "DSW4");
432		if ( !(state->m_igs_magic[1] & 0x10) )   return input_port_read(space->machine(), "DSW5");
433		logerror("%06x: warning, reading dsw with igs_magic[1] = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[1]);
	429	if ( !(m_igs_magic[1] & 0x01) )   return input_port_read(machine(), "DSW1");
	430	if ( !(m_igs_magic[1] & 0x02) )   return input_port_read(machine(), "DSW2");
	431	if ( !(m_igs_magic[1] & 0x04) )   return input_port_read(machine(), "DSW3");
	432	if ( !(m_igs_magic[1] & 0x08) )   return input_port_read(machine(), "DSW4");
	433	if ( !(m_igs_magic[1] & 0x10) )   return input_port_read(machine(), "DSW5");
	434	logerror("%06x: warning, reading dsw with igs_magic[1] = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[1]);
434	435	break;
435	436
436	437	default:
437		logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[0]);
	438	logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[0]);
438	439	}
439	440
440	441	return 0;
r14845	r14846
451	452	static ADDRESS_MAP_START( jingbell_portmap, AS_IO, 8, igs009_state )
452	453	AM_RANGE( 0x0000, 0x003f ) AM_RAM // Z180 internal regs
453	454
454		AM_RANGE( 0x1000, 0x11ff ) AM_RAM_WRITE_LEGACY(bg_scroll_w ) AM_BASE(m_bg_scroll )
	455	AM_RANGE( 0x1000, 0x11ff ) AM_RAM_WRITE(bg_scroll_w ) AM_BASE(m_bg_scroll )
455	456
456	457	AM_RANGE( 0x2000, 0x23ff ) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split1_w ) AM_BASE_GENERIC( paletteram )
457	458	AM_RANGE( 0x2400, 0x27ff ) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split2_w ) AM_BASE_GENERIC( paletteram2 )
458	459
459		AM_RANGE( 0x3000, 0x33ff ) AM_RAM_WRITE_LEGACY(gp98_reel1_ram_w )  AM_BASE(m_gp98_reel1_ram )
460		AM_RANGE( 0x3400, 0x37ff ) AM_RAM_WRITE_LEGACY(gp98_reel2_ram_w )  AM_BASE(m_gp98_reel2_ram )
461		AM_RANGE( 0x3800, 0x3bff ) AM_RAM_WRITE_LEGACY(gp98_reel3_ram_w )  AM_BASE(m_gp98_reel3_ram )
462		AM_RANGE( 0x3c00, 0x3fff ) AM_RAM_WRITE_LEGACY(gp98_reel4_ram_w )  AM_BASE(m_gp98_reel4_ram )
	460	AM_RANGE( 0x3000, 0x33ff ) AM_RAM_WRITE(gp98_reel1_ram_w )  AM_BASE(m_gp98_reel1_ram )
	461	AM_RANGE( 0x3400, 0x37ff ) AM_RAM_WRITE(gp98_reel2_ram_w )  AM_BASE(m_gp98_reel2_ram )
	462	AM_RANGE( 0x3800, 0x3bff ) AM_RAM_WRITE(gp98_reel3_ram_w )  AM_BASE(m_gp98_reel3_ram )
	463	AM_RANGE( 0x3c00, 0x3fff ) AM_RAM_WRITE(gp98_reel4_ram_w )  AM_BASE(m_gp98_reel4_ram )
463	464
464	465	AM_RANGE( 0x4000, 0x407f ) AM_RAM AM_BASE(m_bg_scroll2 )
465	466
466		AM_RANGE( 0x5000, 0x5fff ) AM_RAM_WRITE_LEGACY(fg_tile_w )  AM_BASE(m_fg_tile_ram )
	467	AM_RANGE( 0x5000, 0x5fff ) AM_RAM_WRITE(fg_tile_w )  AM_BASE(m_fg_tile_ram )
467	468
468		AM_RANGE( 0x6480, 0x6480 ) AM_WRITE_LEGACY(jingbell_nmi_and_coins_w )
	469	AM_RANGE( 0x6480, 0x6480 ) AM_WRITE(jingbell_nmi_and_coins_w )
469	470
470	471	AM_RANGE( 0x6481, 0x6481 ) AM_READ_PORT( "SERVICE" )
471	472	AM_RANGE( 0x6482, 0x6482 ) AM_READ_PORT( "COINS" )
472	473	AM_RANGE( 0x6490, 0x6490 ) AM_READ_PORT( "BUTTONS1" )
473		AM_RANGE( 0x6491, 0x6491 ) AM_WRITE_LEGACY(jingbell_video_and_leds_w )
474		AM_RANGE( 0x6492, 0x6492 ) AM_WRITE_LEGACY(jingbell_leds_w )
	474	AM_RANGE( 0x6491, 0x6491 ) AM_WRITE(jingbell_video_and_leds_w )
	475	AM_RANGE( 0x6492, 0x6492 ) AM_WRITE(jingbell_leds_w )
475	476	AM_RANGE( 0x64a0, 0x64a0 ) AM_READ_PORT( "BUTTONS2" )
476	477
477	478	AM_RANGE( 0x64b0, 0x64b1 ) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w )
478	479
479	480	AM_RANGE( 0x64c0, 0x64c0 ) AM_DEVREADWRITE("oki", okim6295_device, read, write)
480	481
481		AM_RANGE( 0x64d0, 0x64d1 ) AM_READWRITE_LEGACY(jingbell_magic_r, jingbell_magic_w )   // DSW1-5
	482	AM_RANGE( 0x64d0, 0x64d1 ) AM_READWRITE(jingbell_magic_r, jingbell_magic_w )   // DSW1-5
482	483
483		AM_RANGE( 0x7000, 0x7fff ) AM_RAM_WRITE_LEGACY(fg_color_w ) AM_BASE(m_fg_color_ram )
	484	AM_RANGE( 0x7000, 0x7fff ) AM_RAM_WRITE(fg_color_w ) AM_BASE(m_fg_color_ram )
484	485
485	486	AM_RANGE( 0x8000, 0xffff ) AM_ROM AM_REGION("data", 0)
486	487	ADDRESS_MAP_END

src/mame/drivers/blitz68k.c

r14845	r14846
56	56	UINT16 *m_blit_vregs;
57	57	UINT16 *m_blit_transpen;
58	58	UINT16 *m_leds[3];
	59	DECLARE_WRITE16_MEMBER(blit_copy_w);
	60	DECLARE_READ8_MEMBER(blit_status_r);
	61	DECLARE_WRITE8_MEMBER(blit_x_w);
	62	DECLARE_WRITE8_MEMBER(blit_y_w);
	63	DECLARE_WRITE8_MEMBER(blit_xy_w);
	64	DECLARE_WRITE8_MEMBER(blit_w_w);
	65	DECLARE_WRITE8_MEMBER(blit_h_w);
	66	DECLARE_WRITE8_MEMBER(blit_wh_w);
	67	DECLARE_WRITE8_MEMBER(blit_addr0_w);
	68	DECLARE_WRITE8_MEMBER(blit_addr1_w);
	69	DECLARE_WRITE8_MEMBER(blit_addr01_w);
	70	DECLARE_WRITE8_MEMBER(blit_addr2_w);
	71	DECLARE_WRITE8_MEMBER(blit_pens_w);
	72	DECLARE_WRITE8_MEMBER(blit_pen0_w);
	73	DECLARE_WRITE8_MEMBER(blit_pen1_w);
	74	DECLARE_WRITE8_MEMBER(blit_pen2_w);
	75	DECLARE_WRITE8_MEMBER(blit_pen3_w);
	76	DECLARE_WRITE8_MEMBER(blit_flag0_w);
	77	DECLARE_WRITE8_MEMBER(blit_flag1_w);
	78	DECLARE_WRITE8_MEMBER(blit_flipx_w);
	79	DECLARE_WRITE8_MEMBER(blit_flipy_w);
	80	DECLARE_WRITE8_MEMBER(blit_solid_w);
	81	DECLARE_WRITE8_MEMBER(blit_trans_w);
	82	DECLARE_WRITE8_MEMBER(blit_flag6_w);
	83	DECLARE_WRITE8_MEMBER(blit_flag7_w);
	84	DECLARE_WRITE8_MEMBER(blit_flags_w);
	85	DECLARE_WRITE8_MEMBER(blit_draw_w);
	86	DECLARE_WRITE8_MEMBER(blit_hwyxa_draw_w);
	87	DECLARE_READ16_MEMBER(blitter_status_r);
	88	DECLARE_WRITE16_MEMBER(lamps_w);
	89	DECLARE_READ16_MEMBER(test_r);
	90	DECLARE_WRITE16_MEMBER(irq_callback_w);
	91	DECLARE_WRITE16_MEMBER(sound_write_w);
	92	DECLARE_READ8_MEMBER(bankrob_mcu1_r);
	93	DECLARE_READ8_MEMBER(bankrob_mcu2_r);
	94	DECLARE_READ8_MEMBER(bankrob_mcu_status_read_r);
	95	DECLARE_READ8_MEMBER(bankrob_mcu_status_write_r);
	96	DECLARE_WRITE8_MEMBER(bankrob_mcu1_w);
	97	DECLARE_WRITE8_MEMBER(bankrob_mcu2_w);
	98	DECLARE_READ8_MEMBER(bankroba_mcu1_r);
	99	DECLARE_READ8_MEMBER(bankroba_mcu2_r);
	100	DECLARE_READ8_MEMBER(bankroba_mcu1_status_write_r);
	101	DECLARE_READ8_MEMBER(bankroba_mcu2_status_write_r);
	102	DECLARE_WRITE8_MEMBER(bankroba_mcu1_w);
	103	DECLARE_WRITE8_MEMBER(bankroba_mcu2_w);
	104	DECLARE_WRITE16_MEMBER(cjffruit_leds1_w);
	105	DECLARE_WRITE16_MEMBER(cjffruit_leds2_w);
	106	DECLARE_WRITE16_MEMBER(cjffruit_leds3_w);
	107	DECLARE_READ8_MEMBER(crtc_r);
	108	DECLARE_WRITE8_MEMBER(crtc_w);
	109	DECLARE_READ16_MEMBER(cjffruit_mcu_r);
	110	DECLARE_WRITE16_MEMBER(cjffruit_mcu_w);
	111	DECLARE_READ16_MEMBER(deucesw2_mcu_r);
	112	DECLARE_WRITE16_MEMBER(deucesw2_mcu_w);
	113	DECLARE_WRITE16_MEMBER(deucesw2_leds1_w);
	114	DECLARE_WRITE16_MEMBER(deucesw2_leds2_w);
	115	DECLARE_WRITE16_MEMBER(deucesw2_leds3_w);
	116	DECLARE_READ8_MEMBER(dualgame_mcu1_r);
	117	DECLARE_READ8_MEMBER(dualgame_mcu2_r);
	118	DECLARE_READ8_MEMBER(dualgame_mcu_status_read_r);
	119	DECLARE_READ8_MEMBER(dualgame_mcu_status_write_r);
	120	DECLARE_WRITE8_MEMBER(dualgame_mcu1_w);
	121	DECLARE_WRITE8_MEMBER(dualgame_mcu2_w);
	122	DECLARE_READ16_MEMBER(hermit_mcu_r);
	123	DECLARE_WRITE16_MEMBER(hermit_mcu_w);
	124	DECLARE_WRITE16_MEMBER(hermit_leds1_w);
	125	DECLARE_WRITE16_MEMBER(hermit_leds2_w);
	126	DECLARE_READ16_MEMBER(hermit_track_r);
	127	DECLARE_READ8_MEMBER(maxidbl_mcu1_r);
	128	DECLARE_READ8_MEMBER(maxidbl_mcu2_r);
	129	DECLARE_READ8_MEMBER(maxidbl_mcu_status_read_r);
	130	DECLARE_READ8_MEMBER(maxidbl_mcu_status_write_r);
	131	DECLARE_WRITE8_MEMBER(maxidbl_mcu1_w);
	132	DECLARE_WRITE8_MEMBER(maxidbl_mcu2_w);
	133	void show_leds123();
	134	void show_leds12();
59	135	};
60	136
61	137	/*************************************************************************************************************
r14845	r14846
151	227	*************************************************************************************************************/
152	228
153	229
154		static WRITE16_HANDLER( blit_copy_w )
	230	WRITE16_MEMBER(blitz68k_state::blit_copy_w)
155	231	{
156		blitz68k_state *state = space->machine().driver_data<blitz68k_state>();
157		UINT8 *blit_rom = space->machine().region("blitter")->base();
	232	UINT8 *blit_rom = machine().region("blitter")->base();
158	233	UINT32 blit_dst_xpos;
159	234	UINT32 blit_dst_ypos;
160	235	int x,y,x_size,y_size;
161	236	UINT32 src;
162	237
163		logerror("blit copy %04x %04x %04x %04x %04x\n", state->m_blit_romaddr[0], state->m_blit_attr1_ram[0], state->m_blit_dst_ram_loword[0], state->m_blit_attr2_ram[0], state->m_blit_dst_ram_hiword[0] );
164		logerror("blit vregs %04x %04x %04x %04x\n",state->m_blit_vregs[0/2],state->m_blit_vregs[2/2],state->m_blit_vregs[4/2],state->m_blit_vregs[6/2]);
165		logerror("blit transpen %04x %04x %04x %04x %04x %04x %04x %04x\n",state->m_blit_transpen[0/2],state->m_blit_transpen[2/2],state->m_blit_transpen[4/2],state->m_blit_transpen[6/2],
166		state->m_blit_transpen[8/2],state->m_blit_transpen[10/2],state->m_blit_transpen[12/2],state->m_blit_transpen[14/2]);
	238	logerror("blit copy %04x %04x %04x %04x %04x\n", m_blit_romaddr[0], m_blit_attr1_ram[0], m_blit_dst_ram_loword[0], m_blit_attr2_ram[0], m_blit_dst_ram_hiword[0] );
	239	logerror("blit vregs %04x %04x %04x %04x\n",m_blit_vregs[0/2],m_blit_vregs[2/2],m_blit_vregs[4/2],m_blit_vregs[6/2]);
	240	logerror("blit transpen %04x %04x %04x %04x %04x %04x %04x %04x\n",m_blit_transpen[0/2],m_blit_transpen[2/2],m_blit_transpen[4/2],m_blit_transpen[6/2],
	241	m_blit_transpen[8/2],m_blit_transpen[10/2],m_blit_transpen[12/2],m_blit_transpen[14/2]);
167	242
168		blit_dst_xpos = (state->m_blit_dst_ram_loword[0] & 0x00ff)*2;
169		blit_dst_ypos = ((state->m_blit_dst_ram_loword[0] & 0xff00)>>8);
	243	blit_dst_xpos = (m_blit_dst_ram_loword[0] & 0x00ff)*2;
	244	blit_dst_ypos = ((m_blit_dst_ram_loword[0] & 0xff00)>>8);
170	245
171		y_size = (0x100-((state->m_blit_attr2_ram[0] & 0xff00)>>8));
172		x_size = (state->m_blit_attr2_ram[0] & 0x00ff)*2;
	246	y_size = (0x100-((m_blit_attr2_ram[0] & 0xff00)>>8));
	247	x_size = (m_blit_attr2_ram[0] & 0x00ff)*2;
173	248
174	249	/* rounding around for 0 size */
175	250	if(x_size == 0) { x_size = 0x200; }
r14845	r14846
177	252	/* TODO: used by steaser "Game Over" msg on attract mode*/
178	253	//  if(y_size == 1) { y_size = 32; }
179	254
180		src = state->m_blit_romaddr[0] | (state->m_blit_attr1_ram[0] & 0x1f00)<<8;
181		//  src|= (state->m_blit_transpen[0xc/2] & 0x0100)<<12;
	255	src = m_blit_romaddr[0] | (m_blit_attr1_ram[0] & 0x1f00)<<8;
	256	//  src|= (m_blit_transpen[0xc/2] & 0x0100)<<12;
182	257
183	258	for(y=0;y<y_size;y++)
184	259	{
r14845	r14846
186	261	{
187	262	int drawx = (blit_dst_xpos+x)&0x1ff;
188	263	int drawy = (blit_dst_ypos+y)&0x0ff;
189		if(state->m_blit_transpen[0x8/2] & 0x100)
190		state->m_blit_buffer[drawy*512+drawx] = ((state->m_blit_vregs[0] & 0xf00)>>8);
	264	if(m_blit_transpen[0x8/2] & 0x100)
	265	m_blit_buffer[drawy*512+drawx] = ((m_blit_vregs[0] & 0xf00)>>8);
191	266	else
192	267	{
193	268	UINT8 pen_helper;
194	269
195	270	pen_helper = blit_rom[src] & 0xff;
196		if(state->m_blit_transpen[0xa/2] & 0x100) //pen is opaque register
	271	if(m_blit_transpen[0xa/2] & 0x100) //pen is opaque register
197	272	{
198	273	if(pen_helper)
199		state->m_blit_buffer[drawy*512+drawx] = ((pen_helper & 0xff) <= 3) ? ((state->m_blit_vregs[pen_helper] & 0xf00)>>8) : blit_rom[src];
	274	m_blit_buffer[drawy*512+drawx] = ((pen_helper & 0xff) <= 3) ? ((m_blit_vregs[pen_helper] & 0xf00)>>8) : blit_rom[src];
200	275	}
201	276	else
202		state->m_blit_buffer[drawy*512+drawx] = ((pen_helper & 0xff) <= 3) ? ((state->m_blit_vregs[pen_helper] & 0xf00)>>8) : blit_rom[src];
	277	m_blit_buffer[drawy*512+drawx] = ((pen_helper & 0xff) <= 3) ? ((m_blit_vregs[pen_helper] & 0xf00)>>8) : blit_rom[src];
203	278	}
204	279
205	280	src++;
r14845	r14846
214	289
215	290	*************************************************************************************************************/
216	291
217		static READ8_HANDLER( blit_status_r )
	292	READ8_MEMBER(blitz68k_state::blit_status_r)
218	293	{
219	294	return 0;   // bit 0 = blitter busy
220	295	}
221	296
222		static WRITE8_HANDLER( blit_x_w )
	297	WRITE8_MEMBER(blitz68k_state::blit_x_w)
223	298	{
224	299	blit.x = data;
225	300	}
226		static WRITE8_HANDLER( blit_y_w )
	301	WRITE8_MEMBER(blitz68k_state::blit_y_w)
227	302	{
228	303	blit.y = data;
229	304	}
230		static WRITE8_HANDLER( blit_xy_w )
	305	WRITE8_MEMBER(blitz68k_state::blit_xy_w)
231	306	{
232	307	if (offset)
233	308	blit_x_w(space, offset, data);
r14845	r14846
236	311	}
237	312
238	313
239		static WRITE8_HANDLER( blit_w_w )
	314	WRITE8_MEMBER(blitz68k_state::blit_w_w)
240	315	{
241	316	blit.w = data;
242	317	}
243		static WRITE8_HANDLER( blit_h_w )
	318	WRITE8_MEMBER(blitz68k_state::blit_h_w)
244	319	{
245	320	blit.h = data;
246	321	}
247		static WRITE8_HANDLER( blit_wh_w )
	322	WRITE8_MEMBER(blitz68k_state::blit_wh_w)
248	323	{
249	324	if (offset)
250	325	blit_w_w(space, offset, data-1);
r14845	r14846
253	328	}
254	329
255	330
256		static WRITE8_HANDLER( blit_addr0_w )
	331	WRITE8_MEMBER(blitz68k_state::blit_addr0_w)
257	332	{
258	333	blit.addr[0] = data;
259	334	}
260		static WRITE8_HANDLER( blit_addr1_w )
	335	WRITE8_MEMBER(blitz68k_state::blit_addr1_w)
261	336	{
262	337	blit.addr[1] = data;
263	338	}
264		static WRITE8_HANDLER( blit_addr01_w )
	339	WRITE8_MEMBER(blitz68k_state::blit_addr01_w)
265	340	{
266	341	if (offset)
267	342	blit_addr0_w(space, offset, data);
268	343	else
269	344	blit_addr1_w(space, offset, data);
270	345	}
271		static WRITE8_HANDLER( blit_addr2_w )
	346	WRITE8_MEMBER(blitz68k_state::blit_addr2_w)
272	347	{
273	348	blit.addr[2] = data;
274	349	}
275	350
276	351
277		static WRITE8_HANDLER( blit_pens_w )
	352	WRITE8_MEMBER(blitz68k_state::blit_pens_w)
278	353	{
279	354	blit.pen[offset] = data;
280	355	}
281		static WRITE8_HANDLER( blit_pen0_w )
	356	WRITE8_MEMBER(blitz68k_state::blit_pen0_w)
282	357	{
283	358	blit.pen[0] = data;
284	359	}
285		static WRITE8_HANDLER( blit_pen1_w )
	360	WRITE8_MEMBER(blitz68k_state::blit_pen1_w)
286	361	{
287	362	blit.pen[1] = data;
288	363	}
289		static WRITE8_HANDLER( blit_pen2_w )
	364	WRITE8_MEMBER(blitz68k_state::blit_pen2_w)
290	365	{
291	366	blit.pen[2] = data;
292	367	}
293		static WRITE8_HANDLER( blit_pen3_w )
	368	WRITE8_MEMBER(blitz68k_state::blit_pen3_w)
294	369	{
295	370	blit.pen[3] = data;
296	371	}
297	372
298	373
299		static WRITE8_HANDLER( blit_flag0_w )
	374	WRITE8_MEMBER(blitz68k_state::blit_flag0_w)
300	375	{
301	376	blit.flag[0] = data;
302	377	}
303		static WRITE8_HANDLER( blit_flag1_w )
	378	WRITE8_MEMBER(blitz68k_state::blit_flag1_w)
304	379	{
305	380	blit.flag[1] = data;
306	381	}
307		static WRITE8_HANDLER( blit_flipx_w )
	382	WRITE8_MEMBER(blitz68k_state::blit_flipx_w)
308	383	{
309	384	blit.flipx = data;
310	385	}
311		static WRITE8_HANDLER( blit_flipy_w )
	386	WRITE8_MEMBER(blitz68k_state::blit_flipy_w)
312	387	{
313	388	blit.flipy = data;
314	389	}
315		static WRITE8_HANDLER( blit_solid_w )
	390	WRITE8_MEMBER(blitz68k_state::blit_solid_w)
316	391	{
317	392	blit.solid = data;
318	393	}
319		static WRITE8_HANDLER( blit_trans_w )
	394	WRITE8_MEMBER(blitz68k_state::blit_trans_w)
320	395	{
321	396	blit.trans = data;
322	397	}
323		static WRITE8_HANDLER( blit_flag6_w )
	398	WRITE8_MEMBER(blitz68k_state::blit_flag6_w)
324	399	{
325	400	blit.flag[6] = data;
326	401	}
327		static WRITE8_HANDLER( blit_flag7_w )
	402	WRITE8_MEMBER(blitz68k_state::blit_flag7_w)
328	403	{
329	404	blit.flag[7] = data;
330	405	}
331	406
332		static WRITE8_HANDLER( blit_flags_w )
	407	WRITE8_MEMBER(blitz68k_state::blit_flags_w)
333	408	{
334	409	switch(offset)
335	410	{
r14845	r14846
340	415	}
341	416	}
342	417
343		static WRITE8_HANDLER( blit_draw_w )
	418	WRITE8_MEMBER(blitz68k_state::blit_draw_w)
344	419	{
345		blitz68k_state *state = space->machine().driver_data<blitz68k_state>();
346		UINT8 *blit_rom  = space->machine().region("blitter")->base();
347		int blit_romsize = space->machine().region("blitter")->bytes();
	420	UINT8 *blit_rom  = machine().region("blitter")->base();
	421	int blit_romsize = machine().region("blitter")->bytes();
348	422	UINT32 blit_dst_xpos;
349	423	UINT32 blit_dst_ypos;
350	424	int x, y, x_size, y_size;
351	425	UINT32 src;
352	426
353		logerror("%s: blit x=%02x y=%02x w=%02x h=%02x addr=%02x%02x%02x pens=%02x %02x %02x %02x flag=%02x %02x %02x %02x - %02x %02x %02x %02x\n", space->machine().describe_context(),
	427	logerror("%s: blit x=%02x y=%02x w=%02x h=%02x addr=%02x%02x%02x pens=%02x %02x %02x %02x flag=%02x %02x %02x %02x - %02x %02x %02x %02x\n", machine().describe_context(),
354	428	blit.x,  blit.y, blit.w, blit.h,
355	429	blit.addr[2], blit.addr[1], blit.addr[0],
356	430	blit.pen[0], blit.pen[1], blit.pen[2], blit.pen[3],
r14845	r14846
397	471	if (pen <= 3)
398	472	pen = blit.pen[pen] & 0xf;
399	473
400		state->m_blit_buffer[drawy * 512 + drawx] = pen;
	474	m_blit_buffer[drawy * 512 + drawx] = pen;
401	475	}
402	476	}
403	477	}
r14845	r14846
409	483	blit.y = blit_dst_ypos;
410	484	}
411	485
412		static WRITE8_HANDLER( blit_hwyxa_draw_w )
	486	WRITE8_MEMBER(blitz68k_state::blit_hwyxa_draw_w)
413	487	{
414	488	switch (offset)
415	489	{
r14845	r14846
428	502	Outputs
429	503	*************************************************************************************************************/
430	504
431		static void show_leds123(blitz68k_state *state)
	505	void blitz68k_state::show_leds123()
432	506	{
433	507	#ifdef MAME_DEBUG
434		popmessage("led %02x %02x %02x", state->m_leds[0][0]>>8, state->m_leds[1][0]>>8, state->m_leds[2][0]>>8);
	508	popmessage("led %02x %02x %02x", m_leds[0][0]>>8, m_leds[1][0]>>8, m_leds[2][0]>>8);
435	509	#endif
436	510	}
437		static void show_leds12(blitz68k_state *state)
	511	void blitz68k_state::show_leds12()
438	512	{
439	513	#ifdef MAME_DEBUG
440		popmessage("led %02x %02x", state->m_leds[0][0]>>8, state->m_leds[1][0]>>8);
	514	popmessage("led %02x %02x", m_leds[0][0]>>8, m_leds[1][0]>>8);
441	515	#endif
442	516	}
443	517
r14845	r14846
448	522	*************************************************************************************************************/
449	523
450	524	/*bit 0 is the blitter busy flag*/
451		static READ16_HANDLER( blitter_status_r )
	525	READ16_MEMBER(blitz68k_state::blitter_status_r)
452	526	{
453	527	return 0;
454	528	}
455	529
456	530	/*TODO*/
457		static WRITE16_HANDLER( lamps_w )
	531	WRITE16_MEMBER(blitz68k_state::lamps_w)
458	532	{
459	533	//  popmessage("%02x",data);
460	534	}
461	535
462		static READ16_HANDLER( test_r )
	536	READ16_MEMBER(blitz68k_state::test_r)
463	537	{
464		return 0xffff;//space->machine().rand();
	538	return 0xffff;//machine().rand();
465	539	}
466	540
467	541	#if 0
468		static WRITE16_HANDLER( irq_callback_w )
	542	WRITE16_MEMBER(blitz68k_state::irq_callback_w)
469	543	{
470	544	//  popmessage("%02x",data);
471		cputag_set_input_line(space->machine(), "maincpu", 3, HOLD_LINE );
	545	cputag_set_input_line(machine(), "maincpu", 3, HOLD_LINE );
472	546	}
473	547
474		static WRITE16_HANDLER( sound_write_w )
	548	WRITE16_MEMBER(blitz68k_state::sound_write_w)
475	549	{
476	550	popmessage("%02x",data);
477	551	dac_data_w(0, data & 0x0f);      /* Sound DAC? */
r14845	r14846
483	557	AM_RANGE(0x100000, 0x1fffff) AM_ROM AM_REGION("blitter", 0)
484	558	AM_RANGE(0x200000, 0x20ffff) AM_RAM AM_SHARE("nvram")
485	559
486		//  AM_RANGE(0x800000, 0x800001) AM_READ_LEGACY(test_r)
487		//  AM_RANGE(0x880000, 0x880001) AM_READ_LEGACY(test_r)
	560	//  AM_RANGE(0x800000, 0x800001) AM_READ(test_r)
	561	//  AM_RANGE(0x880000, 0x880001) AM_READ(test_r)
488	562
489	563	AM_RANGE(0x900000, 0x900001) AM_DEVWRITE8("ramdac",ramdac_device, index_w, 0xff00 )
490	564	AM_RANGE(0x900002, 0x900003) AM_DEVWRITE8("ramdac",ramdac_device, pal_w, 0xff00 )
r14845	r14846
495	569	AM_RANGE(0x9a0000, 0x9a0001) AM_RAM AM_BASE(m_blit_attr1_ram)
496	570	AM_RANGE(0x9a8000, 0x9a8001) AM_RAM AM_BASE(m_blit_dst_ram_loword)
497	571	AM_RANGE(0x9b0000, 0x9b0001) AM_RAM AM_BASE(m_blit_attr2_ram)
498		AM_RANGE(0x9b8000, 0x9b8001) AM_RAM_WRITE_LEGACY(blit_copy_w ) AM_BASE(m_blit_dst_ram_hiword)
499		AM_RANGE(0x9e0000, 0x9e0001) AM_READ_LEGACY(blitter_status_r)
	572	AM_RANGE(0x9b8000, 0x9b8001) AM_RAM_WRITE(blit_copy_w ) AM_BASE(m_blit_dst_ram_hiword)
	573	AM_RANGE(0x9e0000, 0x9e0001) AM_READ(blitter_status_r)
500	574
501		AM_RANGE(0xc00000, 0xc00001) AM_WRITE_LEGACY(lamps_w)
	575	AM_RANGE(0xc00000, 0xc00001) AM_WRITE(lamps_w)
502	576	AM_RANGE(0xc00180, 0xc00181) AM_READ_PORT("IN2")
503		//  AM_RANGE(0xc00200, 0xc00201) AM_WRITE_LEGACY(sound_write_w)
	577	//  AM_RANGE(0xc00200, 0xc00201) AM_WRITE(sound_write_w)
504	578	AM_RANGE(0xc00380, 0xc00381) AM_READ_PORT("IN3")
505		//  AM_RANGE(0xc00300, 0xc00301) AM_WRITE_LEGACY(irq_callback_w)
	579	//  AM_RANGE(0xc00300, 0xc00301) AM_WRITE(irq_callback_w)
506	580	ADDRESS_MAP_END
507	581
508	582	static ADDRESS_MAP_START( steaser_map, AS_PROGRAM, 16, blitz68k_state )
r14845	r14846
510	584	AM_RANGE(0x100000, 0x1fffff) AM_ROM AM_REGION("blitter", 0)
511	585	AM_RANGE(0x200000, 0x20ffff) AM_RAM AM_SHARE("nvram")
512	586
513		AM_RANGE(0x800000, 0x800001) AM_READ_LEGACY(test_r)
514		//  AM_RANGE(0x840000, 0x840001) AM_WRITE_LEGACY(sound_write_w)
515		AM_RANGE(0x880000, 0x880001) AM_READ_LEGACY(test_r)
516		//  AM_RANGE(0x8c0000, 0x8c0001) AM_WRITE_LEGACY(sound_write_w)
	587	AM_RANGE(0x800000, 0x800001) AM_READ(test_r)
	588	//  AM_RANGE(0x840000, 0x840001) AM_WRITE(sound_write_w)
	589	AM_RANGE(0x880000, 0x880001) AM_READ(test_r)
	590	//  AM_RANGE(0x8c0000, 0x8c0001) AM_WRITE(sound_write_w)
517	591
518	592	AM_RANGE(0x900000, 0x900001) AM_DEVWRITE8("ramdac",ramdac_device, index_w, 0xff00 )
519	593	AM_RANGE(0x900002, 0x900003) AM_DEVWRITE8("ramdac",ramdac_device, pal_w, 0xff00 )
r14845	r14846
525	599	AM_RANGE(0x9a0000, 0x9a0001) AM_RAM AM_BASE(m_blit_attr1_ram)
526	600	AM_RANGE(0x9a8000, 0x9a8001) AM_RAM AM_BASE(m_blit_dst_ram_loword)
527	601	AM_RANGE(0x9b0000, 0x9b0001) AM_RAM AM_BASE(m_blit_attr2_ram)
528		AM_RANGE(0x9b8000, 0x9b8001) AM_RAM_WRITE_LEGACY(blit_copy_w ) AM_BASE(m_blit_dst_ram_hiword)
	602	AM_RANGE(0x9b8000, 0x9b8001) AM_RAM_WRITE(blit_copy_w ) AM_BASE(m_blit_dst_ram_hiword)
529	603	AM_RANGE(0x9c0002, 0x9c0003) AM_READNOP //pen control?
530	604	AM_RANGE(0x9d0000, 0x9d0001) AM_READNOP //?
531		AM_RANGE(0x9e0000, 0x9e0001) AM_READ_LEGACY(blitter_status_r)
	605	AM_RANGE(0x9e0000, 0x9e0001) AM_READ(blitter_status_r)
532	606	AM_RANGE(0x9f0000, 0x9f0001) AM_WRITENOP //???
533	607
534		//  AM_RANGE(0xc00000, 0xc00001) AM_WRITE_LEGACY(lamps_w)
535		AM_RANGE(0xbd0000, 0xbd0001) AM_READ_LEGACY(test_r)
536		//  AM_RANGE(0xc00200, 0xc00201) AM_WRITE_LEGACY(sound_write_w)
	608	//  AM_RANGE(0xc00000, 0xc00001) AM_WRITE(lamps_w)
	609	AM_RANGE(0xbd0000, 0xbd0001) AM_READ(test_r)
	610	//  AM_RANGE(0xc00200, 0xc00201) AM_WRITE(sound_write_w)
537	611	//  AM_RANGE(0xc00380, 0xc00381) AM_READ_PORT("IN3")
538		//  AM_RANGE(0xc00300, 0xc00301) AM_WRITE_LEGACY(irq_callback_w)
	612	//  AM_RANGE(0xc00300, 0xc00301) AM_WRITE(irq_callback_w)
539	613	ADDRESS_MAP_END
540	614
541	615	/*************************************************************************************************************
r14845	r14846
543	617	*************************************************************************************************************/
544	618
545	619	// MCU simulation (to be done)
546		static READ8_HANDLER( bankrob_mcu1_r )
	620	READ8_MEMBER(blitz68k_state::bankrob_mcu1_r)
547	621	{
548		UINT8 ret = 0;   // space->machine().rand() gives "interesting" results
549		logerror("%s: mcu1 reads %02x\n", space->machine().describe_context(), ret);
	622	UINT8 ret = 0;   // machine().rand() gives "interesting" results
	623	logerror("%s: mcu1 reads %02x\n", machine().describe_context(), ret);
550	624	return ret;
551	625	}
552		static READ8_HANDLER( bankrob_mcu2_r )
	626	READ8_MEMBER(blitz68k_state::bankrob_mcu2_r)
553	627	{
554		UINT8 ret = 0;   // space->machine().rand() gives "interesting" results
555		logerror("%s: mcu2 reads %02x\n", space->machine().describe_context(), ret);
	628	UINT8 ret = 0;   // machine().rand() gives "interesting" results
	629	logerror("%s: mcu2 reads %02x\n", machine().describe_context(), ret);
556	630	return ret;
557	631	}
558	632
559		static READ8_HANDLER( bankrob_mcu_status_read_r )
	633	READ8_MEMBER(blitz68k_state::bankrob_mcu_status_read_r)
560	634	{
561	635	return 0x03;   // bit 0 = MCU1, bit 1 = MCU2. Active high.
562	636	}
563	637
564		static READ8_HANDLER( bankrob_mcu_status_write_r )
	638	READ8_MEMBER(blitz68k_state::bankrob_mcu_status_write_r)
565	639	{
566	640	return 0x03;   // bit 0 = MCU1, bit 1 = MCU2. Active high.
567	641	}
568	642
569		static WRITE8_HANDLER( bankrob_mcu1_w )
	643	WRITE8_MEMBER(blitz68k_state::bankrob_mcu1_w)
570	644	{
571		logerror("%s: mcu1 written with %02x\n", space->machine().describe_context(), data);
	645	logerror("%s: mcu1 written with %02x\n", machine().describe_context(), data);
572	646	}
573		static WRITE8_HANDLER( bankrob_mcu2_w )
	647	WRITE8_MEMBER(blitz68k_state::bankrob_mcu2_w)
574	648	{
575		logerror("%s: mcu2 written with %02x\n", space->machine().describe_context(), data);
	649	logerror("%s: mcu2 written with %02x\n", machine().describe_context(), data);
576	650	}
577	651
578	652	static ADDRESS_MAP_START( bankrob_map, AS_PROGRAM, 16, blitz68k_state )
r14845	r14846
582	656	AM_RANGE(0x220000, 0x220001) AM_DEVREAD8("ramdac",ramdac_device, index_r, 0xff00 )
583	657	AM_RANGE(0x220002, 0x220003) AM_DEVREAD8("ramdac",ramdac_device, pal_r, 0xff00 )
584	658
585		AM_RANGE(0x240000, 0x240001) AM_WRITE8_LEGACY(blit_addr0_w, 0xff00)
586		AM_RANGE(0x240002, 0x240003) AM_WRITE8_LEGACY(blit_addr1_w, 0xff00)
587		AM_RANGE(0x240004, 0x240005) AM_WRITE8_LEGACY(blit_addr2_w, 0xff00)
	659	AM_RANGE(0x240000, 0x240001) AM_WRITE8(blit_addr0_w, 0xff00)
	660	AM_RANGE(0x240002, 0x240003) AM_WRITE8(blit_addr1_w, 0xff00)
	661	AM_RANGE(0x240004, 0x240005) AM_WRITE8(blit_addr2_w, 0xff00)
588	662
589		AM_RANGE(0x240006, 0x240007) AM_WRITE8_LEGACY(blit_x_w, 0xff00)
590		AM_RANGE(0x240008, 0x240009) AM_WRITE8_LEGACY(blit_y_w, 0xff00)
	663	AM_RANGE(0x240006, 0x240007) AM_WRITE8(blit_x_w, 0xff00)
	664	AM_RANGE(0x240008, 0x240009) AM_WRITE8(blit_y_w, 0xff00)
591	665
592		AM_RANGE(0x24000a, 0x24000b) AM_WRITE8_LEGACY(blit_w_w, 0xff00)
593		AM_RANGE(0x24000c, 0x24000d) AM_WRITE8_LEGACY(blit_h_w, 0xff00)
	666	AM_RANGE(0x24000a, 0x24000b) AM_WRITE8(blit_w_w, 0xff00)
	667	AM_RANGE(0x24000c, 0x24000d) AM_WRITE8(blit_h_w, 0xff00)
594	668
595		AM_RANGE(0x24000e, 0x24000f) AM_WRITE8_LEGACY(blit_draw_w, 0xff00)
	669	AM_RANGE(0x24000e, 0x24000f) AM_WRITE8(blit_draw_w, 0xff00)
596	670
597		AM_RANGE(0x260000, 0x260001) AM_WRITE8_LEGACY(blit_pen0_w, 0xff00)
598		AM_RANGE(0x260002, 0x260003) AM_WRITE8_LEGACY(blit_pen1_w, 0xff00)
599		AM_RANGE(0x260004, 0x260005) AM_WRITE8_LEGACY(blit_pen2_w, 0xff00)
600		AM_RANGE(0x260006, 0x260007) AM_WRITE8_LEGACY(blit_pen3_w, 0xff00)
	671	AM_RANGE(0x260000, 0x260001) AM_WRITE8(blit_pen0_w, 0xff00)
	672	AM_RANGE(0x260002, 0x260003) AM_WRITE8(blit_pen1_w, 0xff00)
	673	AM_RANGE(0x260004, 0x260005) AM_WRITE8(blit_pen2_w, 0xff00)
	674	AM_RANGE(0x260006, 0x260007) AM_WRITE8(blit_pen3_w, 0xff00)
601	675
602		AM_RANGE(0x280000, 0x280001) AM_READ_LEGACY(blitter_status_r)
	676	AM_RANGE(0x280000, 0x280001) AM_READ(blitter_status_r)
603	677
604	678	AM_RANGE(0x2c0000, 0x2c0001) AM_WRITENOP   // 1->0
605	679
606		AM_RANGE(0x2e0000, 0x2e0001) AM_WRITE8_LEGACY(blit_flag0_w, 0xff00)
607		AM_RANGE(0x2e0002, 0x2e0003) AM_WRITE8_LEGACY(blit_flag1_w, 0xff00)
608		AM_RANGE(0x2e0004, 0x2e0005) AM_WRITE8_LEGACY(blit_flipx_w, 0xff00)
609		AM_RANGE(0x2e0006, 0x2e0007) AM_WRITE8_LEGACY(blit_flipy_w, 0xff00)
610		AM_RANGE(0x2e0008, 0x2e0009) AM_WRITE8_LEGACY(blit_solid_w, 0xff00)
611		AM_RANGE(0x2e000a, 0x2e000b) AM_WRITE8_LEGACY(blit_trans_w, 0xff00)
612		AM_RANGE(0x2e000c, 0x2e000d) AM_WRITE8_LEGACY(blit_flag6_w, 0xff00)
613		AM_RANGE(0x2e000e, 0x2e000f) AM_WRITE8_LEGACY(blit_flag7_w, 0xff00)
	680	AM_RANGE(0x2e0000, 0x2e0001) AM_WRITE8(blit_flag0_w, 0xff00)
	681	AM_RANGE(0x2e0002, 0x2e0003) AM_WRITE8(blit_flag1_w, 0xff00)
	682	AM_RANGE(0x2e0004, 0x2e0005) AM_WRITE8(blit_flipx_w, 0xff00)
	683	AM_RANGE(0x2e0006, 0x2e0007) AM_WRITE8(blit_flipy_w, 0xff00)
	684	AM_RANGE(0x2e0008, 0x2e0009) AM_WRITE8(blit_solid_w, 0xff00)
	685	AM_RANGE(0x2e000a, 0x2e000b) AM_WRITE8(blit_trans_w, 0xff00)
	686	AM_RANGE(0x2e000c, 0x2e000d) AM_WRITE8(blit_flag6_w, 0xff00)
	687	AM_RANGE(0x2e000e, 0x2e000f) AM_WRITE8(blit_flag7_w, 0xff00)
614	688
615	689	AM_RANGE(0x300000, 0x300001) AM_DEVWRITE8("ramdac",ramdac_device, index_w, 0xff00 )
616	690	AM_RANGE(0x300002, 0x300003) AM_DEVWRITE8("ramdac",ramdac_device, pal_w, 0xff00 )
617	691	AM_RANGE(0x300004, 0x300005) AM_DEVWRITE8("ramdac",ramdac_device, mask_w, 0xff00 )
618	692
619		AM_RANGE(0x400000, 0x400001) AM_READ8_LEGACY(bankrob_mcu_status_write_r, 0x00ff)
620		AM_RANGE(0x400002, 0x400003) AM_READ8_LEGACY(bankrob_mcu_status_read_r,  0x00ff)
	693	AM_RANGE(0x400000, 0x400001) AM_READ8(bankrob_mcu_status_write_r, 0x00ff)
	694	AM_RANGE(0x400002, 0x400003) AM_READ8(bankrob_mcu_status_read_r,  0x00ff)
621	695
622		AM_RANGE(0x400004, 0x400005) AM_READWRITE8_LEGACY(bankrob_mcu1_r, bankrob_mcu1_w, 0x00ff)
623		AM_RANGE(0x400006, 0x400007) AM_READWRITE8_LEGACY(bankrob_mcu2_r, bankrob_mcu2_w, 0xff00)
	696	AM_RANGE(0x400004, 0x400005) AM_READWRITE8(bankrob_mcu1_r, bankrob_mcu1_w, 0x00ff)
	697	AM_RANGE(0x400006, 0x400007) AM_READWRITE8(bankrob_mcu2_r, bankrob_mcu2_w, 0xff00)
624	698
625	699	AM_RANGE(0x800000, 0x800001) AM_DEVREADWRITE8("crtc", mc6845_device, status_r,   address_w,  0xff00)   // triggered by MCU?
626	700	AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("crtc", mc6845_device, register_r, register_w, 0xff00)
r14845	r14846
629	703	// bankroba:
630	704
631	705	// MCU simulation (to be done)
632		static READ8_HANDLER( bankroba_mcu1_r )
	706	READ8_MEMBER(blitz68k_state::bankroba_mcu1_r)
633	707	{
634		UINT8 ret = space->machine().rand();   // space->machine().rand() gives "interesting" results
635		logerror("%s: mcu1 reads %02x\n", space->machine().describe_context(), ret);
	708	UINT8 ret = machine().rand();   // machine().rand() gives "interesting" results
	709	logerror("%s: mcu1 reads %02x\n", machine().describe_context(), ret);
636	710	return ret;
637	711	}
638		static READ8_HANDLER( bankroba_mcu2_r )
	712	READ8_MEMBER(blitz68k_state::bankroba_mcu2_r)
639	713	{
640		UINT8 ret = space->machine().rand();   // space->machine().rand() gives "interesting" results
641		logerror("%s: mcu2 reads %02x\n", space->machine().describe_context(), ret);
	714	UINT8 ret = machine().rand();   // machine().rand() gives "interesting" results
	715	logerror("%s: mcu2 reads %02x\n", machine().describe_context(), ret);
642	716	return ret;
643	717	}
644	718
645		static READ8_HANDLER( bankroba_mcu1_status_write_r )
	719	READ8_MEMBER(blitz68k_state::bankroba_mcu1_status_write_r)
646	720	{
647	721	return 0x00;   // bit 0 = MCU1. Active low.
648	722	}
649		static READ8_HANDLER( bankroba_mcu2_status_write_r )
	723	READ8_MEMBER(blitz68k_state::bankroba_mcu2_status_write_r)
650	724	{
651	725	return 0x01;   // bit 0 = MCU2. Active high.
652	726	}
653	727
654		static WRITE8_HANDLER( bankroba_mcu1_w )
	728	WRITE8_MEMBER(blitz68k_state::bankroba_mcu1_w)
655	729	{
656		logerror("%s: mcu1 written with %02x\n", space->machine().describe_context(), data);
	730	logerror("%s: mcu1 written with %02x\n", machine().describe_context(), data);
657	731	}
658		static WRITE8_HANDLER( bankroba_mcu2_w )
	732	WRITE8_MEMBER(blitz68k_state::bankroba_mcu2_w)
659	733	{
660		logerror("%s: mcu2 written with %02x\n", space->machine().describe_context(), data);
	734	logerror("%s: mcu2 written with %02x\n", machine().describe_context(), data);
661	735	}
662	736
663	737	static ADDRESS_MAP_START( bankroba_map, AS_PROGRAM, 16, blitz68k_state )
664	738	AM_RANGE(0x000000, 0x03ffff) AM_ROM
665	739	AM_RANGE(0x200000, 0x20ffff) AM_RAM
666	740
667		AM_RANGE(0x800000, 0x800001) AM_WRITE8_LEGACY(bankroba_mcu1_r, 0x00ff)   // lev 4
668		AM_RANGE(0x840000, 0x840001) AM_WRITE8_LEGACY(bankroba_mcu1_w, 0x00ff)
	741	AM_RANGE(0x800000, 0x800001) AM_READ8(bankroba_mcu1_r, 0x00ff)   // lev 4
	742	AM_RANGE(0x840000, 0x840001) AM_WRITE8(bankroba_mcu1_w, 0x00ff)
669	743
670		AM_RANGE(0x880000, 0x880001) AM_WRITE8_LEGACY(bankroba_mcu2_r, 0x00ff)   // lev 3
671		AM_RANGE(0x8c0000, 0x8c0001) AM_WRITE8_LEGACY(bankroba_mcu2_w, 0x00ff)
	744	AM_RANGE(0x880000, 0x880001) AM_READ8(bankroba_mcu2_r, 0x00ff)   // lev 3
	745	AM_RANGE(0x8c0000, 0x8c0001) AM_WRITE8(bankroba_mcu2_w, 0x00ff)
672	746
673	747	AM_RANGE(0x900000, 0x900001) AM_DEVWRITE8("ramdac",ramdac_device, index_w, 0xff00 )
674	748	AM_RANGE(0x900002, 0x900003) AM_DEVWRITE8("ramdac",ramdac_device, pal_w, 0xff00 )
r14845	r14846
676	750
677	751	//  AM_RANGE(0x940000, 0x940001) AM_WRITE   // lev 6
678	752
679		AM_RANGE(0x980000, 0x980001) AM_WRITE8_LEGACY(blit_flag0_w, 0xff00)
680		AM_RANGE(0x980002, 0x980003) AM_WRITE8_LEGACY(blit_flag1_w, 0xff00)
681		AM_RANGE(0x980004, 0x980005) AM_WRITE8_LEGACY(blit_flipx_w, 0xff00)
682		AM_RANGE(0x980006, 0x980007) AM_WRITE8_LEGACY(blit_flipy_w, 0xff00)
683		AM_RANGE(0x980008, 0x980009) AM_WRITE8_LEGACY(blit_solid_w, 0xff00)
684		AM_RANGE(0x98000a, 0x98000b) AM_WRITE8_LEGACY(blit_trans_w, 0xff00)
685		AM_RANGE(0x98000c, 0x98000d) AM_WRITE8_LEGACY(blit_flag6_w, 0xff00)
686		AM_RANGE(0x98000e, 0x98000f) AM_WRITE8_LEGACY(blit_flag7_w, 0xff00)
	753	AM_RANGE(0x980000, 0x980001) AM_WRITE8(blit_flag0_w, 0xff00)
	754	AM_RANGE(0x980002, 0x980003) AM_WRITE8(blit_flag1_w, 0xff00)
	755	AM_RANGE(0x980004, 0x980005) AM_WRITE8(blit_flipx_w, 0xff00)
	756	AM_RANGE(0x980006, 0x980007) AM_WRITE8(blit_flipy_w, 0xff00)
	757	AM_RANGE(0x980008, 0x980009) AM_WRITE8(blit_solid_w, 0xff00)
	758	AM_RANGE(0x98000a, 0x98000b) AM_WRITE8(blit_trans_w, 0xff00)
	759	AM_RANGE(0x98000c, 0x98000d) AM_WRITE8(blit_flag6_w, 0xff00)
	760	AM_RANGE(0x98000e, 0x98000f) AM_WRITE8(blit_flag7_w, 0xff00)
687	761
688		AM_RANGE(0x990000, 0x990001) AM_WRITE8_LEGACY(blit_pen0_w, 0xff00)
689		AM_RANGE(0x990002, 0x990003) AM_WRITE8_LEGACY(blit_pen1_w, 0xff00)
690		AM_RANGE(0x990004, 0x990005) AM_WRITE8_LEGACY(blit_pen2_w, 0xff00)
691		AM_RANGE(0x990006, 0x990007) AM_WRITE8_LEGACY(blit_pen3_w, 0xff00)
	762	AM_RANGE(0x990000, 0x990001) AM_WRITE8(blit_pen0_w, 0xff00)
	763	AM_RANGE(0x990002, 0x990003) AM_WRITE8(blit_pen1_w, 0xff00)
	764	AM_RANGE(0x990004, 0x990005) AM_WRITE8(blit_pen2_w, 0xff00)
	765	AM_RANGE(0x990006, 0x990007) AM_WRITE8(blit_pen3_w, 0xff00)
692	766
693		AM_RANGE(0x998000, 0x998001) AM_WRITE8_LEGACY(blit_addr01_w, 0xffff)
694		AM_RANGE(0x9a0000, 0x9a0001) AM_WRITE8_LEGACY(blit_addr2_w,  0xff00)
	767	AM_RANGE(0x998000, 0x998001) AM_WRITE8(blit_addr01_w, 0xffff)
	768	AM_RANGE(0x9a0000, 0x9a0001) AM_WRITE8(blit_addr2_w,  0xff00)
695	769
696		AM_RANGE(0x9a8000, 0x9a8001) AM_WRITE8_LEGACY(blit_xy_w, 0xffff)
	770	AM_RANGE(0x9a8000, 0x9a8001) AM_WRITE8(blit_xy_w, 0xffff)
697	771
698		AM_RANGE(0x9b0000, 0x9b0001) AM_WRITE8_LEGACY(blit_wh_w, 0xffff)
	772	AM_RANGE(0x9b0000, 0x9b0001) AM_WRITE8(blit_wh_w, 0xffff)
699	773
700		AM_RANGE(0x9b8000, 0x9b8001) AM_WRITE8_LEGACY(blit_draw_w, 0x00ff)
	774	AM_RANGE(0x9b8000, 0x9b8001) AM_WRITE8(blit_draw_w, 0x00ff)
701	775
702	776	AM_RANGE(0x9c0000, 0x9c0001) AM_DEVREAD8("ramdac",ramdac_device, index_r, 0xff00 )
703	777	AM_RANGE(0x9c0002, 0x9c0003) AM_DEVREAD8("ramdac",ramdac_device, pal_r, 0xff00 )
704	778
705		AM_RANGE(0x9d0000, 0x9d0001) AM_READ8_LEGACY(bankroba_mcu1_status_write_r, 0xff00)
	779	AM_RANGE(0x9d0000, 0x9d0001) AM_READ8(bankroba_mcu1_status_write_r, 0xff00)
706	780
707		AM_RANGE(0x9e0000, 0x9e0001) AM_READ_LEGACY(blitter_status_r)
	781	AM_RANGE(0x9e0000, 0x9e0001) AM_READ(blitter_status_r)
708	782
709	783	AM_RANGE(0x9f0000, 0x9f0001) AM_WRITENOP // 1
710	784
711		AM_RANGE(0xbd0000, 0xbd0001) AM_READ8_LEGACY(bankroba_mcu2_status_write_r, 0xff00)
	785	AM_RANGE(0xbd0000, 0xbd0001) AM_READ8(bankroba_mcu2_status_write_r, 0xff00)
712	786
713	787	// CRTC connected to MCU?
714	788	ADDRESS_MAP_END
r14845	r14846
717	791	Funny Fruit
718	792	*************************************************************************************************************/
719	793
720		static WRITE16_HANDLER( cjffruit_leds1_w )
	794	WRITE16_MEMBER(blitz68k_state::cjffruit_leds1_w)
721	795	{
722		blitz68k_state *state = space->machine().driver_data<blitz68k_state>();
723		data = COMBINE_DATA(state->m_leds[0]);
	796	data = COMBINE_DATA(m_leds[0]);
724	797	if (ACCESSING_BITS_8_15)
725	798	{
726		coin_counter_w(space->machine(), 0, data & 0x0100);   // coin in
727		set_led_status(space->machine(), 0, data & 0x0200);   // win???
	799	coin_counter_w(machine(), 0, data & 0x0100);   // coin in
	800	set_led_status(machine(), 0, data & 0x0200);   // win???
728	801	//                                     1  data & 0x0400     // win???
729		set_led_status(space->machine(), 2, data & 0x0800);   // small
730		set_led_status(space->machine(), 3, data & 0x1000);   // big
731		set_led_status(space->machine(), 4, data & 0x2000);   // take
732		set_led_status(space->machine(), 5, data & 0x4000);   // double up
733		set_led_status(space->machine(), 6, data & 0x8000);   // cancel
734		show_leds123(state);
	802	set_led_status(machine(), 2, data & 0x0800);   // small
	803	set_led_status(machine(), 3, data & 0x1000);   // big
	804	set_led_status(machine(), 4, data & 0x2000);   // take
	805	set_led_status(machine(), 5, data & 0x4000);   // double up
	806	set_led_status(machine(), 6, data & 0x8000);   // cancel
	807	show_leds123();
735	808	}
736	809	}
737	810
738		static WRITE16_HANDLER( cjffruit_leds2_w )
	811	WRITE16_MEMBER(blitz68k_state::cjffruit_leds2_w)
739	812	{
740		blitz68k_state *state = space->machine().driver_data<blitz68k_state>();
741		data = COMBINE_DATA(state->m_leds[1]);
	813	data = COMBINE_DATA(m_leds[1]);
742	814	if (ACCESSING_BITS_8_15)
743	815	{
744		set_led_status(space->machine(),  7, data & 0x0100);   // start
745		set_led_status(space->machine(),  8, data & 0x0200);   // bet
746		set_led_status(space->machine(),  9, data & 0x0400);   // hold 5
747		set_led_status(space->machine(), 10, data & 0x0800);   // hold 4
748		set_led_status(space->machine(), 11, data & 0x1000);   // hold 3
749		set_led_status(space->machine(), 12, data & 0x2000);   // hold 2
750		set_led_status(space->machine(), 13, data & 0x4000);   // collect
751		set_led_status(space->machine(), 14, data & 0x8000);   // call attendant
752		show_leds123(state);
	816	set_led_status(machine(),  7, data & 0x0100);   // start
	817	set_led_status(machine(),  8, data & 0x0200);   // bet
	818	set_led_status(machine(),  9, data & 0x0400);   // hold 5
	819	set_led_status(machine(), 10, data & 0x0800);   // hold 4
	820	set_led_status(machine(), 11, data & 0x1000);   // hold 3
	821	set_led_status(machine(), 12, data & 0x2000);   // hold 2
	822	set_led_status(machine(), 13, data & 0x4000);   // collect
	823	set_led_status(machine(), 14, data & 0x8000);   // call attendant
	824	show_leds123();
753	825	}
754	826	}
755	827
756		static WRITE16_HANDLER( cjffruit_leds3_w )
	828	WRITE16_MEMBER(blitz68k_state::cjffruit_leds3_w)
757	829	{
758		blitz68k_state *state = space->machine().driver_data<blitz68k_state>();
759		data = COMBINE_DATA(state->m_leds[2]);
	830	data = COMBINE_DATA(m_leds[2]);
760	831	if (ACCESSING_BITS_8_15)
761	832	{
762		set_led_status(space->machine(), 15, data & 0x0100);   // hopper coins?
763		set_led_status(space->machine(), 16, data & 0x0400);   // coin out?
764		show_leds123(state);
	833	set_led_status(machine(), 15, data & 0x0100);   // hopper coins?
	834	set_led_status(machine(), 16, data & 0x0400);   // coin out?
	835	show_leds123();
765	836	}
766	837	}
767	838
768	839	// CRTC
769		static READ8_HANDLER( crtc_r )
	840	READ8_MEMBER(blitz68k_state::crtc_r)
770	841	{
771		mc6845_device *mc6845 = space->machine().device<mc6845_device>("crtc");
	842	mc6845_device *mc6845 = machine().device<mc6845_device>("crtc");
772	843	if (offset)
773		return mc6845->register_r(*space, 0);
	844	return mc6845->register_r(*&space, 0);
774	845	else
775		return mc6845->status_r(*space, 0);
	846	return mc6845->status_r(*&space, 0);
776	847	}
777	848
778		static WRITE8_HANDLER( crtc_w )
	849	WRITE8_MEMBER(blitz68k_state::crtc_w)
779	850	{
780		mc6845_device *mc6845 = space->machine().device<mc6845_device>("crtc");
	851	mc6845_device *mc6845 = machine().device<mc6845_device>("crtc");
781	852	if (offset)
782		mc6845->register_w(*space, 0, data);
	853	mc6845->register_w(*&space, 0, data);
783	854	else
784		mc6845->address_w(*space, 0, data);
	855	mc6845->address_w(*&space, 0, data);
785	856	}
786	857
787	858	static WRITE16_DEVICE_HANDLER( crtc_lpen_w )
r14845	r14846
793	864	}
794	865
795	866	// MCU simulation (to be done)
796		static READ16_HANDLER( cjffruit_mcu_r )
	867	READ16_MEMBER(blitz68k_state::cjffruit_mcu_r)
797	868	{
798		UINT8 ret = 0x00;   // space->machine().rand() gives "interesting" results
799		logerror("%s: mcu reads %02x\n", space->machine().describe_context(), ret);
	869	UINT8 ret = 0x00;   // machine().rand() gives "interesting" results
	870	logerror("%s: mcu reads %02x\n", machine().describe_context(), ret);
800	871	return ret << 8;
801	872	}
802	873
803		static WRITE16_HANDLER( cjffruit_mcu_w )
	874	WRITE16_MEMBER(blitz68k_state::cjffruit_mcu_w)
804	875	{
805		logerror("%s: mcu written with %02x\n", space->machine().describe_context(),data >> 8);
	876	logerror("%s: mcu written with %02x\n", machine().describe_context(),data >> 8);
806	877	}
807	878
808	879	static ADDRESS_MAP_START( cjffruit_map, AS_PROGRAM, 16, blitz68k_state )
r14845	r14846
810	881	AM_RANGE(0x400000, 0x41ffff) AM_RAM AM_SHARE("nvram")
811	882	AM_RANGE(0x480000, 0x4807ff) AM_RAM
812	883
813		AM_RANGE(0x820000, 0x820007) AM_WRITE8_LEGACY(blit_hwyxa_draw_w, 0xffff)
	884	AM_RANGE(0x820000, 0x820007) AM_WRITE8(blit_hwyxa_draw_w, 0xffff)
814	885
815		AM_RANGE(0x850000, 0x850001) AM_READ_LEGACY(cjffruit_mcu_r )
	886	AM_RANGE(0x850000, 0x850001) AM_READ(cjffruit_mcu_r )
816	887
817	888	AM_RANGE(0x870000, 0x870001) AM_READ_PORT("IN0")
818	889	AM_RANGE(0x872000, 0x872001) AM_READ_PORT("IN1")
r14845	r14846
825	896	AM_RANGE(0x880000, 0x880001) AM_DEVREAD8("ramdac",ramdac_device, index_r, 0xff00 )
826	897	AM_RANGE(0x880000, 0x880001) AM_DEVREAD8("ramdac",ramdac_device, pal_r, 0x00ff )
827	898
828		AM_RANGE(0x8a0000, 0x8a0007) AM_WRITE8_LEGACY(blit_hwyxa_draw_w, 0xffff)
	899	AM_RANGE(0x8a0000, 0x8a0007) AM_WRITE8(blit_hwyxa_draw_w, 0xffff)
829	900
830		AM_RANGE(0x8b0000, 0x8b0003) AM_WRITE8_LEGACY(blit_pens_w, 0xffff)
	901	AM_RANGE(0x8b0000, 0x8b0003) AM_WRITE8(blit_pens_w, 0xffff)
831	902
832		AM_RANGE(0x8e0000, 0x8e0001) AM_WRITE_LEGACY(cjffruit_mcu_w )
	903	AM_RANGE(0x8e0000, 0x8e0001) AM_WRITE(cjffruit_mcu_w )
833	904
834		AM_RANGE(0x8f8000, 0x8f8001) AM_WRITE_LEGACY(cjffruit_leds1_w) AM_BASE(m_leds[0])
835		AM_RANGE(0x8fa000, 0x8fa001) AM_WRITE_LEGACY(cjffruit_leds2_w) AM_BASE(m_leds[1])
836		AM_RANGE(0x8fc000, 0x8fc001) AM_WRITE_LEGACY(cjffruit_leds3_w) AM_BASE(m_leds[2])
	905	AM_RANGE(0x8f8000, 0x8f8001) AM_WRITE(cjffruit_leds1_w) AM_BASE(m_leds[0])
	906	AM_RANGE(0x8fa000, 0x8fa001) AM_WRITE(cjffruit_leds2_w) AM_BASE(m_leds[1])
	907	AM_RANGE(0x8fc000, 0x8fc001) AM_WRITE(cjffruit_leds3_w) AM_BASE(m_leds[2])
837	908
838		AM_RANGE(0x8fe000, 0x8fe003) AM_WRITE8_LEGACY(blit_flags_w, 0xffff)   // flipx,y,solid,trans
	909	AM_RANGE(0x8fe000, 0x8fe003) AM_WRITE8(blit_flags_w, 0xffff)   // flipx,y,solid,trans
839	910	AM_RANGE(0x8fe004, 0x8fe005) AM_WRITEONLY
840	911	AM_RANGE(0x8fe006, 0x8fe007) AM_DEVWRITE_LEGACY("crtc", crtc_lpen_w)   // 0x8fe006: 0->1, 0x8fe007: 1->0
841	912
842		AM_RANGE(0xc40000, 0xc40001) AM_READWRITE8_LEGACY(crtc_r, crtc_w, 0xffff)
	913	AM_RANGE(0xc40000, 0xc40001) AM_READWRITE8(crtc_r, crtc_w, 0xffff)
843	914	ADDRESS_MAP_END
844	915
845	916	/*************************************************************************************************************
r14845	r14846
847	918	*************************************************************************************************************/
848	919
849	920	// MCU simulation (to be done)
850		static READ16_HANDLER( deucesw2_mcu_r )
	921	READ16_MEMBER(blitz68k_state::deucesw2_mcu_r)
851	922	{
852		UINT8 ret = 0x00;   // space->machine().rand() gives "interesting" results
853		logerror("%s: mcu reads %02x\n", space->machine().describe_context(), ret);
	923	UINT8 ret = 0x00;   // machine().rand() gives "interesting" results
	924	logerror("%s: mcu reads %02x\n", machine().describe_context(), ret);
854	925	return ret << 8;
855	926	}
856	927
857		static WRITE16_HANDLER( deucesw2_mcu_w )
	928	WRITE16_MEMBER(blitz68k_state::deucesw2_mcu_w)
858	929	{
859		logerror("%s: mcu written with %02x\n", space->machine().describe_context(),data >> 8);
	930	logerror("%s: mcu written with %02x\n", machine().describe_context(),data >> 8);
860	931	}
861	932
862		static WRITE16_HANDLER( deucesw2_leds1_w )
	933	WRITE16_MEMBER(blitz68k_state::deucesw2_leds1_w)
863	934	{
864		blitz68k_state *state = space->machine().driver_data<blitz68k_state>();
865		data = COMBINE_DATA(state->m_leds[0]);
	935	data = COMBINE_DATA(m_leds[0]);
866	936	if (ACCESSING_BITS_8_15)
867	937	{
868		coin_counter_w(space->machine(), 0, data & 0x0100);   // coin in
869		set_led_status(space->machine(), 0, data & 0x0200);   // win???
	938	coin_counter_w(machine(), 0, data & 0x0100);   // coin in
	939	set_led_status(machine(), 0, data & 0x0200);   // win???
870	940	//                                     1  data & 0x0400     // win???
871		set_led_status(space->machine(), 2, data & 0x0800);   // small
872		set_led_status(space->machine(), 3, data & 0x1000);   // big
873		set_led_status(space->machine(), 4, data & 0x2000);   // take
874		set_led_status(space->machine(), 5, data & 0x4000);   // double up
875		set_led_status(space->machine(), 6, data & 0x8000);   // cancel
876		show_leds123(state);
	941	set_led_status(machine(), 2, data & 0x0800);   // small
	942	set_led_status(machine(), 3, data & 0x1000);   // big
	943	set_led_status(machine(), 4, data & 0x2000);   // take
	944	set_led_status(machine(), 5, data & 0x4000);   // double up
	945	set_led_status(machine(), 6, data & 0x8000);   // cancel
	946	show_leds123();
877	947	}
878	948	}
879	949
880		static WRITE16_HANDLER( deucesw2_leds2_w )
	950	WRITE16_MEMBER(blitz68k_state::deucesw2_leds2_w)
881	951	{
882		blitz68k_state *state = space->machine().driver_data<blitz68k_state>();
883		data = COMBINE_DATA(state->m_leds[1]);
	952	data = COMBINE_DATA(m_leds[1]);
884	953	if (ACCESSING_BITS_8_15)
885	954	{
886		set_led_status(space->machine(),  7, data & 0x0100);   // start
887		set_led_status(space->machine(),  8, data & 0x0200);   // bet
888		set_led_status(space->machine(),  9, data & 0x0400);   // hold 5
889		set_led_status(space->machine(), 10, data & 0x0800);   // hold 4
890		set_led_status(space->machine(), 11, data & 0x1000);   // hold 3
891		set_led_status(space->machine(), 12, data & 0x2000);   // hold 2
892		set_led_status(space->machine(), 13, data & 0x4000);   // hold 1
893		set_led_status(space->machine(), 14, data & 0x8000);   // call attendant
894		show_leds123(state);
	955	set_led_status(machine(),  7, data & 0x0100);   // start
	956	set_led_status(machine(),  8, data & 0x0200);   // bet
	957	set_led_status(machine(),  9, data & 0x0400);   // hold 5
	958	set_led_status(machine(), 10, data & 0x0800);   // hold 4
	959	set_led_status(machine(), 11, data & 0x1000);   // hold 3
	960	set_led_status(machine(), 12, data & 0x2000);   // hold 2
	961	set_led_status(machine(), 13, data & 0x4000);   // hold 1
	962	set_led_status(machine(), 14, data & 0x8000);   // call attendant
	963	show_leds123();
895	964	}
896	965	}
897	966
898		static WRITE16_HANDLER( deucesw2_leds3_w )
	967	WRITE16_MEMBER(blitz68k_state::deucesw2_leds3_w)
899	968	{
900		blitz68k_state *state = space->machine().driver_data<blitz68k_state>();
901		data = COMBINE_DATA(state->m_leds[2]);
	969	data = COMBINE_DATA(m_leds[2]);
902	970	if (ACCESSING_BITS_8_15)
903	971	{
904		set_led_status(space->machine(), 15, data & 0x0100);   // hopper coins?
905		set_led_status(space->machine(), 16, data & 0x0400);   // coin out?
906		show_leds123(state);
	972	set_led_status(machine(), 15, data & 0x0100);   // hopper coins?
	973	set_led_status(machine(), 16, data & 0x0400);   // coin out?
	974	show_leds123();
907	975	}
908	976	}
909	977
r14845	r14846
911	979	AM_RANGE(0x000000, 0x03ffff) AM_ROM
912	980	AM_RANGE(0x400000, 0x41ffff) AM_RAM
913	981
914		AM_RANGE(0x800000, 0x800007) AM_WRITE8_LEGACY(blit_hwyxa_draw_w, 0xffff)
	982	AM_RANGE(0x800000, 0x800007) AM_WRITE8(blit_hwyxa_draw_w, 0xffff)
915	983
916	984	AM_RANGE(0x812000, 0x812001) AM_DEVREAD8("ramdac",ramdac_device, index_r, 0xff00 )
917	985	AM_RANGE(0x812000, 0x812001) AM_DEVREAD8("ramdac",ramdac_device, pal_r, 0x00ff )
918	986
919		AM_RANGE(0x830000, 0x830001) AM_READ_LEGACY(deucesw2_mcu_r )
	987	AM_RANGE(0x830000, 0x830001) AM_READ(deucesw2_mcu_r )
920	988
921	989	AM_RANGE(0x840000, 0x840001) AM_READ_PORT("IN0")
922	990	AM_RANGE(0x850000, 0x850001) AM_READ_PORT("IN1")
923	991	AM_RANGE(0x860000, 0x860001) AM_READ_PORT("IN2")
924	992	AM_RANGE(0x870000, 0x870001) AM_READ_PORT("DSW")
925	993
926		AM_RANGE(0x880000, 0x880007) AM_WRITE8_LEGACY(blit_hwyxa_draw_w, 0xffff)
	994	AM_RANGE(0x880000, 0x880007) AM_WRITE8(blit_hwyxa_draw_w, 0xffff)
927	995
928	996	AM_RANGE(0x890000, 0x890001) AM_DEVWRITE8("ramdac",ramdac_device, index_w, 0xff00 )
929	997	AM_RANGE(0x890000, 0x890001) AM_DEVWRITE8("ramdac",ramdac_device, pal_w, 0x00ff )
930	998	AM_RANGE(0x890002, 0x890003) AM_DEVWRITE8("ramdac",ramdac_device, mask_w, 0xff00 )
931	999
932		AM_RANGE(0x894000, 0x894003) AM_WRITE8_LEGACY(blit_pens_w, 0xffff)
	1000	AM_RANGE(0x894000, 0x894003) AM_WRITE8(blit_pens_w, 0xffff)
933	1001
934		AM_RANGE(0x896000, 0x896001) AM_WRITE_LEGACY(deucesw2_mcu_w )
	1002	AM_RANGE(0x896000, 0x896001) AM_WRITE(deucesw2_mcu_w )
935	1003
936		AM_RANGE(0x898000, 0x898001) AM_WRITE_LEGACY(deucesw2_leds1_w) AM_BASE(m_leds[0])
937		AM_RANGE(0x89a000, 0x89a001) AM_WRITE_LEGACY(deucesw2_leds2_w) AM_BASE(m_leds[1])
938		AM_RANGE(0x89c000, 0x89c001) AM_WRITE_LEGACY(deucesw2_leds3_w) AM_BASE(m_leds[2])
	1004	AM_RANGE(0x898000, 0x898001) AM_WRITE(deucesw2_leds1_w) AM_BASE(m_leds[0])
	1005	AM_RANGE(0x89a000, 0x89a001) AM_WRITE(deucesw2_leds2_w) AM_BASE(m_leds[1])
	1006	AM_RANGE(0x89c000, 0x89c001) AM_WRITE(deucesw2_leds3_w) AM_BASE(m_leds[2])
939	1007
940		AM_RANGE(0x89e000, 0x89e003) AM_WRITE8_LEGACY(blit_flags_w, 0xffff)   // flipx,y,solid,trans
	1008	AM_RANGE(0x89e000, 0x89e003) AM_WRITE8(blit_flags_w, 0xffff)   // flipx,y,solid,trans
941	1009	AM_RANGE(0x89e004, 0x89e005) AM_WRITEONLY
942	1010	AM_RANGE(0x89e006, 0x89e007) AM_DEVWRITE_LEGACY("crtc", crtc_lpen_w)   // 0x89e006: 0->1, 0x89e007: 1->0
943	1011
944		AM_RANGE(0xc00000, 0xc00001) AM_READWRITE8_LEGACY(crtc_r, crtc_w, 0xffff)
	1012	AM_RANGE(0xc00000, 0xc00001) AM_READWRITE8(crtc_r, crtc_w, 0xffff)
945	1013	ADDRESS_MAP_END
946	1014
947	1015	/*************************************************************************************************************
r14845	r14846
949	1017	*************************************************************************************************************/
950	1018
951	1019	// MCU simulation (to be done)
952		static READ8_HANDLER( dualgame_mcu1_r )
	1020	READ8_MEMBER(blitz68k_state::dualgame_mcu1_r)
953	1021	{
954		UINT8 ret = 0;   // space->machine().rand() gives "interesting" results
955		logerror("%s: mcu1 reads %02x\n", space->machine().describe_context(), ret);
	1022	UINT8 ret = 0;   // machine().rand() gives "interesting" results
	1023	logerror("%s: mcu1 reads %02x\n", machine().describe_context(), ret);
956	1024	return ret;
957	1025	}
958		static READ8_HANDLER( dualgame_mcu2_r )
	1026	READ8_MEMBER(blitz68k_state::dualgame_mcu2_r)
959	1027	{
960		UINT8 ret = 0;   // space->machine().rand() gives "interesting" results
961		logerror("%s: mcu2 reads %02x\n", space->machine().describe_context(), ret);
	1028	UINT8 ret = 0;   // machine().rand() gives "interesting" results
	1029	logerror("%s: mcu2 reads %02x\n", machine().describe_context(), ret);
962	1030	return ret;
963	1031	}
964	1032
965		static READ8_HANDLER( dualgame_mcu_status_read_r )
	1033	READ8_MEMBER(blitz68k_state::dualgame_mcu_status_read_r)
966	1034	{
967	1035	return 0x03;   // bit 0 = MCU1, bit 1 = MCU2. Active high.
968	1036	}
969	1037
970		static READ8_HANDLER( dualgame_mcu_status_write_r )
	1038	READ8_MEMBER(blitz68k_state::dualgame_mcu_status_write_r)
971	1039	{
972	1040	return 0x03;   // bit 0 = MCU1, bit 1 = MCU2. Active high.
973	1041	}
974	1042
975		static WRITE8_HANDLER( dualgame_mcu1_w )
	1043	WRITE8_MEMBER(blitz68k_state::dualgame_mcu1_w)
976	1044	{
977		logerror("%s: mcu1 written with %02x\n", space->machine().describe_context(), data);
	1045	logerror("%s: mcu1 written with %02x\n", machine().describe_context(), data);
978	1046	}
979		static WRITE8_HANDLER( dualgame_mcu2_w )
	1047	WRITE8_MEMBER(blitz68k_state::dualgame_mcu2_w)
980	1048	{
981		logerror("%s: mcu2 written with %02x\n", space->machine().describe_context(), data);
	1049	logerror("%s: mcu2 written with %02x\n", machine().describe_context(), data);
982	1050	}
983	1051
984	1052	static ADDRESS_MAP_START( dualgame_map, AS_PROGRAM, 16, blitz68k_state )
r14845	r14846
988	1056	AM_RANGE(0x220002, 0x220003) AM_DEVREAD8("ramdac",ramdac_device, index_r, 0xff00 )
989	1057	AM_RANGE(0x220002, 0x220003) AM_DEVREAD8("ramdac",ramdac_device, pal_r, 0x00ff )
990	1058
991		AM_RANGE(0x240000, 0x240001) AM_WRITE8_LEGACY(blit_addr0_w, 0xff00)
992		AM_RANGE(0x240002, 0x240003) AM_WRITE8_LEGACY(blit_addr1_w, 0xff00)
993		AM_RANGE(0x240004, 0x240005) AM_WRITE8_LEGACY(blit_addr2_w, 0xff00)
	1059	AM_RANGE(0x240000, 0x240001) AM_WRITE8(blit_addr0_w, 0xff00)
	1060	AM_RANGE(0x240002, 0x240003) AM_WRITE8(blit_addr1_w, 0xff00)
	1061	AM_RANGE(0x240004, 0x240005) AM_WRITE8(blit_addr2_w, 0xff00)
994	1062
995		AM_RANGE(0x240006, 0x240007) AM_WRITE8_LEGACY(blit_x_w, 0xff00)
996		AM_RANGE(0x240008, 0x240009) AM_WRITE8_LEGACY(blit_y_w, 0xff00)
	1063	AM_RANGE(0x240006, 0x240007) AM_WRITE8(blit_x_w, 0xff00)
	1064	AM_RANGE(0x240008, 0x240009) AM_WRITE8(blit_y_w, 0xff00)
997	1065
998		AM_RANGE(0x24000a, 0x24000b) AM_WRITE8_LEGACY(blit_w_w, 0xff00)
999		AM_RANGE(0x24000c, 0x24000d) AM_WRITE8_LEGACY(blit_h_w, 0xff00)
	1066	AM_RANGE(0x24000a, 0x24000b) AM_WRITE8(blit_w_w, 0xff00)
	1067	AM_RANGE(0x24000c, 0x24000d) AM_WRITE8(blit_h_w, 0xff00)
1000	1068
1001		AM_RANGE(0x24000e, 0x24000f) AM_WRITE8_LEGACY(blit_draw_w, 0xff00)
	1069	AM_RANGE(0x24000e, 0x24000f) AM_WRITE8(blit_draw_w, 0xff00)
1002	1070
1003		AM_RANGE(0x260000, 0x260001) AM_WRITE8_LEGACY(blit_pen0_w, 0xff00)
1004		AM_RANGE(0x260002, 0x260003) AM_WRITE8_LEGACY(blit_pen1_w, 0xff00)
1005		AM_RANGE(0x260004, 0x260005) AM_WRITE8_LEGACY(blit_pen2_w, 0xff00)
1006		AM_RANGE(0x260006, 0x260007) AM_WRITE8_LEGACY(blit_pen3_w, 0xff00)
	1071	AM_RANGE(0x260000, 0x260001) AM_WRITE8(blit_pen0_w, 0xff00)
	1072	AM_RANGE(0x260002, 0x260003) AM_WRITE8(blit_pen1_w, 0xff00)
	1073	AM_RANGE(0x260004, 0x260005) AM_WRITE8(blit_pen2_w, 0xff00)
	1074	AM_RANGE(0x260006, 0x260007) AM_WRITE8(blit_pen3_w, 0xff00)
1007	1075
1008		AM_RANGE(0x280000, 0x280001) AM_READ8_LEGACY(blit_status_r, 0xff00)
	1076	AM_RANGE(0x280000, 0x280001) AM_READ8(blit_status_r, 0xff00)
1009	1077
1010	1078	AM_RANGE(0x2a0000, 0x2a0001) AM_DEVWRITE_LEGACY("crtc", crtc_lpen_w)
1011	1079	AM_RANGE(0x2a0000, 0x2a0001) AM_READNOP
1012	1080
1013	1081	AM_RANGE(0x2c0000, 0x2c0001) AM_WRITENOP   // 1->0 (MCU related?)
1014	1082
1015		AM_RANGE(0x2e0000, 0x2e0001) AM_WRITE8_LEGACY(blit_flag0_w, 0xff00)
1016		AM_RANGE(0x2e0002, 0x2e0003) AM_WRITE8_LEGACY(blit_flag1_w, 0xff00)
1017		AM_RANGE(0x2e0004, 0x2e0005) AM_WRITE8_LEGACY(blit_flipx_w, 0xff00)   // flipx
1018		AM_RANGE(0x2e0006, 0x2e0007) AM_WRITE8_LEGACY(blit_flipy_w, 0xff00)   // flipy
1019		AM_RANGE(0x2e0008, 0x2e0009) AM_WRITE8_LEGACY(blit_solid_w, 0xff00)   // solid
1020		AM_RANGE(0x2e000a, 0x2e000b) AM_WRITE8_LEGACY(blit_trans_w, 0xff00)   // transparency
1021		AM_RANGE(0x2e000c, 0x2e000d) AM_WRITE8_LEGACY(blit_flag6_w, 0xff00)
1022		AM_RANGE(0x2e000e, 0x2e000f) AM_WRITE8_LEGACY(blit_flag7_w, 0xff00)
	1083	AM_RANGE(0x2e0000, 0x2e0001) AM_WRITE8(blit_flag0_w, 0xff00)
	1084	AM_RANGE(0x2e0002, 0x2e0003) AM_WRITE8(blit_flag1_w, 0xff00)
	1085	AM_RANGE(0x2e0004, 0x2e0005) AM_WRITE8(blit_flipx_w, 0xff00)   // flipx
	1086	AM_RANGE(0x2e0006, 0x2e0007) AM_WRITE8(blit_flipy_w, 0xff00)   // flipy
	1087	AM_RANGE(0x2e0008, 0x2e0009) AM_WRITE8(blit_solid_w, 0xff00)   // solid
	1088	AM_RANGE(0x2e000a, 0x2e000b) AM_WRITE8(blit_trans_w, 0xff00)   // transparency
	1089	AM_RANGE(0x2e000c, 0x2e000d) AM_WRITE8(blit_flag6_w, 0xff00)
	1090	AM_RANGE(0x2e000e, 0x2e000f) AM_WRITE8(blit_flag7_w, 0xff00)
1023	1091
1024	1092	AM_RANGE(0x300000, 0x300001) AM_DEVWRITE8("ramdac",ramdac_device, index_w, 0xff00 )
1025	1093	AM_RANGE(0x300002, 0x300003) AM_DEVWRITE8("ramdac",ramdac_device, pal_w, 0xff00 )
1026	1094	AM_RANGE(0x300004, 0x300005) AM_DEVWRITE8("ramdac",ramdac_device, mask_w, 0xff00 )
1027	1095
1028		AM_RANGE(0x400000, 0x400001) AM_READ8_LEGACY(dualgame_mcu_status_write_r, 0x00ff)
1029		AM_RANGE(0x400002, 0x400003) AM_READ8_LEGACY(dualgame_mcu_status_read_r,  0x00ff)
	1096	AM_RANGE(0x400000, 0x400001) AM_READ8(dualgame_mcu_status_write_r, 0x00ff)
	1097	AM_RANGE(0x400002, 0x400003) AM_READ8(dualgame_mcu_status_read_r,  0x00ff)
1030	1098
1031		AM_RANGE(0x400004, 0x400005) AM_READWRITE8_LEGACY(dualgame_mcu1_r, dualgame_mcu1_w, 0x00ff)
1032		AM_RANGE(0x400006, 0x400007) AM_READWRITE8_LEGACY(dualgame_mcu2_r, dualgame_mcu2_w, 0xff00)
	1099	AM_RANGE(0x400004, 0x400005) AM_READWRITE8(dualgame_mcu1_r, dualgame_mcu1_w, 0x00ff)
	1100	AM_RANGE(0x400006, 0x400007) AM_READWRITE8(dualgame_mcu2_r, dualgame_mcu2_w, 0xff00)
1033	1101
1034	1102	AM_RANGE(0x800000, 0x800001) AM_DEVREADWRITE8("crtc", mc6845_device, status_r,   address_w,  0xff00)
1035	1103	AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("crtc", mc6845_device, register_r, register_w, 0xff00)
r14845	r14846
1040	1108	*************************************************************************************************************/
1041	1109
1042	1110	// MCU simulation (to be done)
1043		static READ16_HANDLER( hermit_mcu_r )
	1111	READ16_MEMBER(blitz68k_state::hermit_mcu_r)
1044	1112	{
1045		UINT8 ret = 0x00;   // space->machine().rand() gives "interesting" results
1046		logerror("%s: mcu reads %02x\n", space->machine().describe_context(), ret);
	1113	UINT8 ret = 0x00;   // machine().rand() gives "interesting" results
	1114	logerror("%s: mcu reads %02x\n", machine().describe_context(), ret);
1047	1115	return ret << 8;
1048	1116	}
1049	1117
1050		static WRITE16_HANDLER( hermit_mcu_w )
	1118	WRITE16_MEMBER(blitz68k_state::hermit_mcu_w)
1051	1119	{
1052		logerror("%s: mcu written with %02x\n", space->machine().describe_context(),data >> 8);
	1120	logerror("%s: mcu written with %02x\n", machine().describe_context(),data >> 8);
1053	1121	}
1054	1122
1055		static WRITE16_HANDLER( hermit_leds1_w )
	1123	WRITE16_MEMBER(blitz68k_state::hermit_leds1_w)
1056	1124	{
1057		blitz68k_state *state = space->machine().driver_data<blitz68k_state>();
1058		data = COMBINE_DATA(state->m_leds[0]);
	1125	data = COMBINE_DATA(m_leds[0]);
1059	1126	if (ACCESSING_BITS_8_15)
1060	1127	{
1061		coin_counter_w(space->machine(), 0, data & 0x0100);   // coin in
1062		show_leds12(state);
	1128	coin_counter_w(machine(), 0, data & 0x0100);   // coin in
	1129	show_leds12();
1063	1130	}
1064	1131	}
1065	1132
1066		static WRITE16_HANDLER( hermit_leds2_w )
	1133	WRITE16_MEMBER(blitz68k_state::hermit_leds2_w)
1067	1134	{
1068		blitz68k_state *state = space->machine().driver_data<blitz68k_state>();
1069		data = COMBINE_DATA(state->m_leds[1]);
	1135	data = COMBINE_DATA(m_leds[1]);
1070	1136	if (ACCESSING_BITS_8_15)
1071	1137	{
1072		set_led_status(space->machine(),  7, data & 0x0100);   // button
1073		show_leds12(state);
	1138	set_led_status(machine(),  7, data & 0x0100);   // button
	1139	show_leds12();
1074	1140	}
1075	1141	}
1076	1142
1077		static READ16_HANDLER( hermit_track_r )
	1143	READ16_MEMBER(blitz68k_state::hermit_track_r)
1078	1144	{
1079	1145	#ifdef MAME_DEBUG
1080		//  popmessage("track %02x %02x", input_port_read(space->machine(), "TRACK_X"), input_port_read(space->machine(), "TRACK_Y"));
	1146	//  popmessage("track %02x %02x", input_port_read(machine(), "TRACK_X"), input_port_read(machine(), "TRACK_Y"));
1081	1147	#endif
1082	1148
1083	1149	return
1084		((0xf - ((input_port_read(space->machine(), "TRACK_Y") + 0x7) & 0xf)) << 12) |
1085		((0xf - ((input_port_read(space->machine(), "TRACK_X") + 0x7) & 0xf)) << 8)  ;
	1150	((0xf - ((input_port_read(machine(), "TRACK_Y") + 0x7) & 0xf)) << 12) |
	1151	((0xf - ((input_port_read(machine(), "TRACK_X") + 0x7) & 0xf)) << 8)  ;
1086	1152	}
1087	1153
1088	1154	static ADDRESS_MAP_START( hermit_map, AS_PROGRAM, 16, blitz68k_state )
r14845	r14846
1100	1166	AM_RANGE(0x840000, 0x840001) AM_DEVREAD8("ramdac",ramdac_device, pal_r, 0x00ff )
1101	1167
1102	1168
1103		AM_RANGE(0x8c0000, 0x8c0003) AM_WRITE8_LEGACY(blit_pens_w, 0xffff )
	1169	AM_RANGE(0x8c0000, 0x8c0003) AM_WRITE8(blit_pens_w, 0xffff )
1104	1170
1105		AM_RANGE(0x940000, 0x940001) AM_READ_LEGACY(hermit_mcu_r )
1106		AM_RANGE(0x980000, 0x980001) AM_WRITE_LEGACY(hermit_mcu_w )
	1171	AM_RANGE(0x940000, 0x940001) AM_READ(hermit_mcu_r )
	1172	AM_RANGE(0x980000, 0x980001) AM_WRITE(hermit_mcu_w )
1107	1173
1108	1174	AM_RANGE(0x9c0000, 0x9c0001) AM_READ_PORT("IN0")
1109		AM_RANGE(0x9c8000, 0x9c8001) AM_READ_LEGACY(hermit_track_r )
	1175	AM_RANGE(0x9c8000, 0x9c8001) AM_READ(hermit_track_r )
1110	1176	AM_RANGE(0x9d0000, 0x9d0001) AM_READ_PORT("IN2")
1111	1177	AM_RANGE(0x9d8000, 0x9d8001) AM_READ_PORT("DSW")
1112	1178
1113		AM_RANGE(0x9e0000, 0x9e0001) AM_WRITE_LEGACY(hermit_leds1_w) AM_BASE(m_leds[0])
1114		AM_RANGE(0x9e8000, 0x9e8001) AM_WRITE_LEGACY(hermit_leds2_w) AM_BASE(m_leds[1])
	1179	AM_RANGE(0x9e0000, 0x9e0001) AM_WRITE(hermit_leds1_w) AM_BASE(m_leds[0])
	1180	AM_RANGE(0x9e8000, 0x9e8001) AM_WRITE(hermit_leds2_w) AM_BASE(m_leds[1])
1115	1181
1116		AM_RANGE(0x9f0000, 0x9f0003) AM_WRITE8_LEGACY(blit_flags_w, 0xffff)   // flipx,y,solid,trans
	1182	AM_RANGE(0x9f0000, 0x9f0003) AM_WRITE8(blit_flags_w, 0xffff)   // flipx,y,solid,trans
1117	1183	AM_RANGE(0x9f0004, 0x9f0005) AM_WRITEONLY
1118	1184	AM_RANGE(0x9f0006, 0x9f0007) AM_DEVWRITE_LEGACY("crtc", crtc_lpen_w)   // 0x9f0006: 0->1, 0x9f0007: 1->0
1119	1185
1120		AM_RANGE(0xb00000, 0xb00001) AM_READWRITE8_LEGACY(crtc_r, crtc_w, 0xffff)   // triggered by MCU?
	1186	AM_RANGE(0xb00000, 0xb00001) AM_READWRITE8(crtc_r, crtc_w, 0xffff)   // triggered by MCU?
1121	1187
1122		AM_RANGE(0xc80000, 0xc80007) AM_WRITE8_LEGACY(blit_hwyxa_draw_w, 0xffff)
	1188	AM_RANGE(0xc80000, 0xc80007) AM_WRITE8(blit_hwyxa_draw_w, 0xffff)
1123	1189	ADDRESS_MAP_END
1124	1190
1125	1191	/*************************************************************************************************************
r14845	r14846
1127	1193	*************************************************************************************************************/
1128	1194
1129	1195	// MCU simulation (to be done)
1130		static READ8_HANDLER( maxidbl_mcu1_r )
	1196	READ8_MEMBER(blitz68k_state::maxidbl_mcu1_r)
1131	1197	{
1132		UINT8 ret = 0;   // space->machine().rand() gives "interesting" results
1133		logerror("%s: mcu1 reads %02x\n", space->machine().describe_context(), ret);
	1198	UINT8 ret = 0;   // machine().rand() gives "interesting" results
	1199	logerror("%s: mcu1 reads %02x\n", machine().describe_context(), ret);
1134	1200	return ret;
1135	1201	}
1136		static READ8_HANDLER( maxidbl_mcu2_r )
	1202	READ8_MEMBER(blitz68k_state::maxidbl_mcu2_r)
1137	1203	{
1138		UINT8 ret = 0;   // space->machine().rand() gives "interesting" results
1139		logerror("%s: mcu2 reads %02x\n", space->machine().describe_context(), ret);
	1204	UINT8 ret = 0;   // machine().rand() gives "interesting" results
	1205	logerror("%s: mcu2 reads %02x\n", machine().describe_context(), ret);
1140	1206	return ret;
1141	1207	}
1142	1208
1143		static READ8_HANDLER( maxidbl_mcu_status_read_r )
	1209	READ8_MEMBER(blitz68k_state::maxidbl_mcu_status_read_r)
1144	1210	{
1145	1211	return 0x03;   // bit 0 = MCU1, bit 1 = MCU2. Active high.
1146	1212	}
1147	1213
1148		static READ8_HANDLER( maxidbl_mcu_status_write_r )
	1214	READ8_MEMBER(blitz68k_state::maxidbl_mcu_status_write_r)
1149	1215	{
1150	1216	return 0x03;   // bit 0 = MCU1, bit 1 = MCU2. Active high.
1151	1217	}
1152	1218
1153		static WRITE8_HANDLER( maxidbl_mcu1_w )
	1219	WRITE8_MEMBER(blitz68k_state::maxidbl_mcu1_w)
1154	1220	{
1155		logerror("%s: mcu1 written with %02x\n", space->machine().describe_context(), data);
	1221	logerror("%s: mcu1 written with %02x\n", machine().describe_context(), data);
1156	1222	}
1157		static WRITE8_HANDLER( maxidbl_mcu2_w )
	1223	WRITE8_MEMBER(blitz68k_state::maxidbl_mcu2_w)
1158	1224	{
1159		logerror("%s: mcu2 written with %02x\n", space->machine().describe_context(), data);
	1225	logerror("%s: mcu2 written with %02x\n", machine().describe_context(), data);
1160	1226	}
1161	1227
1162	1228	static ADDRESS_MAP_START( maxidbl_map, AS_PROGRAM, 16, blitz68k_state )
r14845	r14846
1168	1234	AM_RANGE(0x30000c, 0x30000d) AM_WRITENOP   // 0->1 (IRQ3 ack.?)
1169	1235	AM_RANGE(0x30000e, 0x30000f) AM_WRITENOP   // 1->0 (MCU related?)
1170	1236
1171		AM_RANGE(0x500000, 0x500001) AM_READ8_LEGACY(maxidbl_mcu_status_write_r, 0x00ff)
1172		AM_RANGE(0x500002, 0x500003) AM_READ8_LEGACY(maxidbl_mcu_status_read_r,  0x00ff)
	1237	AM_RANGE(0x500000, 0x500001) AM_READ8(maxidbl_mcu_status_write_r, 0x00ff)
	1238	AM_RANGE(0x500002, 0x500003) AM_READ8(maxidbl_mcu_status_read_r,  0x00ff)
1173	1239
1174		AM_RANGE(0x500004, 0x500005) AM_READWRITE8_LEGACY(maxidbl_mcu1_r, maxidbl_mcu1_w, 0x00ff)
1175		AM_RANGE(0x500006, 0x500007) AM_READWRITE8_LEGACY(maxidbl_mcu2_r, maxidbl_mcu2_w, 0xff00)
	1240	AM_RANGE(0x500004, 0x500005) AM_READWRITE8(maxidbl_mcu1_r, maxidbl_mcu1_w, 0x00ff)
	1241	AM_RANGE(0x500006, 0x500007) AM_READWRITE8(maxidbl_mcu2_r, maxidbl_mcu2_w, 0xff00)
1176	1242
1177	1243	AM_RANGE(0x600000, 0x600001) AM_DEVREADWRITE8("crtc", mc6845_device, status_r,   address_w,  0xff00)   // triggered by MCU?
1178	1244	AM_RANGE(0x600002, 0x600003) AM_DEVREADWRITE8("crtc", mc6845_device, register_r, register_w, 0xff00)

src/mame/drivers/tapatune.c

r14845	r14846
55	55	UINT8   m_68k_to_z80_data;
56	56
57	57	UINT16   m_bsmt_data;
	58	DECLARE_WRITE16_MEMBER(palette_w);
	59	DECLARE_READ16_MEMBER(read_from_z80);
	60	DECLARE_WRITE16_MEMBER(write_to_z80);
	61	DECLARE_READ16_MEMBER(irq_ack_r);
	62	DECLARE_READ8_MEMBER(sound_irq_clear);
	63	DECLARE_WRITE8_MEMBER(controls_mux);
	64	DECLARE_READ8_MEMBER(controls_r);
	65	DECLARE_WRITE8_MEMBER(write_index_to_68k);
	66	DECLARE_WRITE8_MEMBER(write_data_to_68k);
	67	DECLARE_READ8_MEMBER(read_index_from_68k);
	68	DECLARE_READ8_MEMBER(read_data_from_68k);
	69	DECLARE_READ8_MEMBER(bsmt_status_r);
	70	DECLARE_WRITE8_MEMBER(bsmt_data_lo_w);
	71	DECLARE_WRITE8_MEMBER(bsmt_data_hi_w);
	72	DECLARE_WRITE8_MEMBER(bsmt_reg_w);
58	73	};
59	74
60		static WRITE16_HANDLER(palette_w)
	75	WRITE16_MEMBER(tapatune_state::palette_w)
61	76	{
62		tapatune_state *state = space->machine().driver_data<tapatune_state>();
63	77
64	78	//logerror("Palette write: offset = %02x, data = %04x, mask = %04x\n", offset, data, mem_mask );
65	79	switch(offset)
66	80	{
67	81	case 0: // address register
68		state->m_palette_write_address = ((data >> 8) & 0xff) * 3;
	82	m_palette_write_address = ((data >> 8) & 0xff) * 3;
69	83	break;
70	84	case 1: // palette data
71		state->m_paletteram[state->m_palette_write_address++] = (data >> 8) & 0xff;
	85	m_paletteram[m_palette_write_address++] = (data >> 8) & 0xff;
72	86	break;
73	87	case 2: // unknown?
74	88	break;
75	89	}
76	90	}
77	91
78		static READ16_HANDLER(read_from_z80)
	92	READ16_MEMBER(tapatune_state::read_from_z80)
79	93	{
80		tapatune_state *state = space->machine().driver_data<tapatune_state>();
81	94
82		//logerror("Reading data from Z80: index = %02x, data = %02x\n", state->m_z80_to_68k_index, state->m_z80_to_68k_data );
	95	//logerror("Reading data from Z80: index = %02x, data = %02x\n", m_z80_to_68k_index, m_z80_to_68k_data );
83	96
84	97	switch( offset )
85	98	{
86	99	case 0:
87		return ((UINT16)state->m_z80_to_68k_data << 8) | (state->m_z80_to_68k_index);
	100	return ((UINT16)m_z80_to_68k_data << 8) | (m_z80_to_68k_index);
88	101	default:
89	102	return 0;
90	103	}
91	104	}
92	105
93		static WRITE16_HANDLER(write_to_z80)
	106	WRITE16_MEMBER(tapatune_state::write_to_z80)
94	107	{
95		tapatune_state *state = space->machine().driver_data<tapatune_state>();
96	108
97	109	switch( offset )
98	110	{
99	111	case 0:
100	112	//if ( (data >> 8) & 0xff )
101	113	//  logerror("Command to Z80: %04x\n", data);
102		state->m_68k_to_z80_index = data & 0xff;
103		state->m_68k_to_z80_data = (data >> 8) & 0xff;
104		cputag_set_input_line(space->machine(), "maincpu", 3, CLEAR_LINE);
	114	m_68k_to_z80_index = data & 0xff;
	115	m_68k_to_z80_data = (data >> 8) & 0xff;
	116	cputag_set_input_line(machine(), "maincpu", 3, CLEAR_LINE);
105	117	break;
106	118	case 1:
107	119	break;
108	120	}
109	121	}
110	122
111		static READ16_HANDLER(irq_ack_r)
	123	READ16_MEMBER(tapatune_state::irq_ack_r)
112	124	{
113		cputag_set_input_line(space->machine(), "maincpu", 2, CLEAR_LINE);
	125	cputag_set_input_line(machine(), "maincpu", 2, CLEAR_LINE);
114	126	return 0;
115	127	}
116	128
r14845	r14846
121	133	AM_RANGE(0x328000, 0x32ffff) AM_RAM
122	134	AM_RANGE(0x330000, 0x337fff) AM_RAM // ram used as system video buffer
123	135	AM_RANGE(0x338000, 0x33ffff) AM_RAM
124		AM_RANGE(0x400000, 0x400003) AM_READWRITE_LEGACY(read_from_z80, write_to_z80)
125		AM_RANGE(0x400010, 0x400011) AM_READ_LEGACY(irq_ack_r)
126		AM_RANGE(0x600000, 0x600005) AM_WRITE_LEGACY(palette_w)
	136	AM_RANGE(0x400000, 0x400003) AM_READWRITE(read_from_z80, write_to_z80)
	137	AM_RANGE(0x400010, 0x400011) AM_READ(irq_ack_r)
	138	AM_RANGE(0x600000, 0x600005) AM_WRITE(palette_w)
127	139	AM_RANGE(0x800000, 0x800001) AM_DEVWRITE8("crtc", mc6845_device, address_w, 0xff00)
128	140	AM_RANGE(0x800002, 0x800003) AM_DEVREADWRITE8("crtc", mc6845_device, register_r, register_w, 0xff00)
129	141	ADDRESS_MAP_END
130	142
131		static READ8_HANDLER(sound_irq_clear)
	143	READ8_MEMBER(tapatune_state::sound_irq_clear)
132	144	{
133		cputag_set_input_line(space->machine(), "soundcpu", 0, CLEAR_LINE);
	145	cputag_set_input_line(machine(), "soundcpu", 0, CLEAR_LINE);
134	146	return 0;
135	147	}
136	148
137		static WRITE8_HANDLER(controls_mux)
	149	WRITE8_MEMBER(tapatune_state::controls_mux)
138	150	{
139		tapatune_state *state = space->machine().driver_data<tapatune_state>();
140	151	//logerror("Controls mux written with %02x\n", data);
141		state->m_controls_mux = data;
	152	m_controls_mux = data;
142	153	}
143	154
144		static READ8_HANDLER(controls_r)
	155	READ8_MEMBER(tapatune_state::controls_r)
145	156	{
146		tapatune_state *state = space->machine().driver_data<tapatune_state>();
147		switch( state->m_controls_mux )
	157	switch( m_controls_mux )
148	158	{
149		case 0x07: return input_port_read(space->machine(), "DSW1");
150		case 0x08: return input_port_read(space->machine(), "DSW2");
151		case 0x09: return input_port_read(space->machine(), "IN0");
	159	case 0x07: return input_port_read(machine(), "DSW1");
	160	case 0x08: return input_port_read(machine(), "DSW2");
	161	case 0x09: return input_port_read(machine(), "IN0");
152	162	default: return 0xff;
153	163	}
154	164	}
155	165
156		static WRITE8_HANDLER(write_index_to_68k)
	166	WRITE8_MEMBER(tapatune_state::write_index_to_68k)
157	167	{
158		tapatune_state *state = space->machine().driver_data<tapatune_state>();
159		state->m_z80_to_68k_index = data;
	168	m_z80_to_68k_index = data;
160	169	}
161	170
162		static WRITE8_HANDLER(write_data_to_68k)
	171	WRITE8_MEMBER(tapatune_state::write_data_to_68k)
163	172	{
164		tapatune_state *state = space->machine().driver_data<tapatune_state>();
165		state->m_z80_to_68k_data = data;
166		//logerror("Writing data from Z80: index = %02x, data = %02x\n", state->m_z80_to_68k_index, state->m_z80_to_68k_data );
167		cputag_set_input_line(space->machine(), "maincpu", 3, ASSERT_LINE);
	173	m_z80_to_68k_data = data;
	174	//logerror("Writing data from Z80: index = %02x, data = %02x\n", m_z80_to_68k_index, m_z80_to_68k_data );
	175	cputag_set_input_line(machine(), "maincpu", 3, ASSERT_LINE);
168	176	}
169	177
170		static READ8_HANDLER(read_index_from_68k)
	178	READ8_MEMBER(tapatune_state::read_index_from_68k)
171	179	{
172		tapatune_state *state = space->machine().driver_data<tapatune_state>();
173		return state->m_68k_to_z80_index;
	180	return m_68k_to_z80_index;
174	181	}
175	182
176		static READ8_HANDLER(read_data_from_68k)
	183	READ8_MEMBER(tapatune_state::read_data_from_68k)
177	184	{
178		tapatune_state *state = space->machine().driver_data<tapatune_state>();
179		//if ( state->m_68k_to_z80_data != 0 )
180		//  logerror("Load command from 68K: %02x %02x\n", state->m_68k_to_z80_index, state->m_68k_to_z80_data);
181		return state->m_68k_to_z80_data;
	185	//if ( m_68k_to_z80_data != 0 )
	186	//  logerror("Load command from 68K: %02x %02x\n", m_68k_to_z80_index, m_68k_to_z80_data);
	187	return m_68k_to_z80_data;
182	188	}
183	189
184		static READ8_HANDLER(bsmt_status_r)
	190	READ8_MEMBER(tapatune_state::bsmt_status_r)
185	191	{
186		bsmt2000_device *bsmt = space->machine().device<bsmt2000_device>("bsmt");
	192	bsmt2000_device *bsmt = machine().device<bsmt2000_device>("bsmt");
187	193	return (bsmt->read_status() << 7) ^ 0x80;
188	194	}
189	195
190		static WRITE8_HANDLER(bsmt_data_lo_w)
	196	WRITE8_MEMBER(tapatune_state::bsmt_data_lo_w)
191	197	{
192		tapatune_state *state = space->machine().driver_data<tapatune_state>();
193		state->m_bsmt_data = (state->m_bsmt_data & 0xff00) | data;
	198	m_bsmt_data = (m_bsmt_data & 0xff00) | data;
194	199	}
195	200
196		static WRITE8_HANDLER(bsmt_data_hi_w)
	201	WRITE8_MEMBER(tapatune_state::bsmt_data_hi_w)
197	202	{
198		tapatune_state *state = space->machine().driver_data<tapatune_state>();
199		state->m_bsmt_data = (state->m_bsmt_data & 0x00ff) | (data << 8);
	203	m_bsmt_data = (m_bsmt_data & 0x00ff) | (data << 8);
200	204	}
201	205
202		static WRITE8_HANDLER(bsmt_reg_w)
	206	WRITE8_MEMBER(tapatune_state::bsmt_reg_w)
203	207	{
204		bsmt2000_device *bsmt = space->machine().device<bsmt2000_device>("bsmt");
205		tapatune_state *state = space->machine().driver_data<tapatune_state>();
	208	bsmt2000_device *bsmt = machine().device<bsmt2000_device>("bsmt");
206	209
207		//logerror("Writing BSMT reg: %02X data: %04X\n", data, state->m_bsmt_data);
	210
	211	//logerror("Writing BSMT reg: %02X data: %04X\n", data, m_bsmt_data);
208	212	bsmt->write_reg(data);
209		bsmt->write_data(state->m_bsmt_data);
	213	bsmt->write_data(m_bsmt_data);
210	214	}
211	215
212	216	static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, tapatune_state )
r14845	r14846
217	221
218	222	static ADDRESS_MAP_START ( sound_io_map, AS_IO, 8, tapatune_state )
219	223	ADDRESS_MAP_GLOBAL_MASK(0xff)
220		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(bsmt_data_lo_w)
221		AM_RANGE(0x08, 0x08) AM_WRITE_LEGACY(bsmt_data_hi_w)
222		AM_RANGE(0x10, 0x10) AM_WRITE_LEGACY(bsmt_reg_w)
223		AM_RANGE(0x18, 0x18) AM_WRITE_LEGACY(controls_mux)
224		AM_RANGE(0x20, 0x20) AM_READ_LEGACY(sound_irq_clear)
225		AM_RANGE(0x28, 0x28) AM_READ_LEGACY(bsmt_status_r)
226		AM_RANGE(0x30, 0x30) AM_READ_LEGACY(controls_r)
	224	AM_RANGE(0x00, 0x00) AM_WRITE(bsmt_data_lo_w)
	225	AM_RANGE(0x08, 0x08) AM_WRITE(bsmt_data_hi_w)
	226	AM_RANGE(0x10, 0x10) AM_WRITE(bsmt_reg_w)
	227	AM_RANGE(0x18, 0x18) AM_WRITE(controls_mux)
	228	AM_RANGE(0x20, 0x20) AM_READ(sound_irq_clear)
	229	AM_RANGE(0x28, 0x28) AM_READ(bsmt_status_r)
	230	AM_RANGE(0x30, 0x30) AM_READ(controls_r)
227	231	AM_RANGE(0x38, 0x38) AM_READ_PORT("COINS")
228		AM_RANGE(0x60, 0x60) AM_WRITE_LEGACY(write_index_to_68k)
229		AM_RANGE(0x61, 0x61) AM_WRITE_LEGACY(write_data_to_68k)
	232	AM_RANGE(0x60, 0x60) AM_WRITE(write_index_to_68k)
	233	AM_RANGE(0x61, 0x61) AM_WRITE(write_data_to_68k)
230	234	AM_RANGE(0x63, 0x63) AM_WRITENOP // leds? lamps?
231		AM_RANGE(0x68, 0x68) AM_READ_LEGACY(read_index_from_68k)
232		AM_RANGE(0x69, 0x69) AM_READ_LEGACY(read_data_from_68k)
	235	AM_RANGE(0x68, 0x68) AM_READ(read_index_from_68k)
	236	AM_RANGE(0x69, 0x69) AM_READ(read_data_from_68k)
233	237	AM_RANGE(0x6b, 0x6b) AM_READ_PORT("BUTTONS")
234	238	ADDRESS_MAP_END
235	239

src/mame/drivers/dacholer.c

r14845	r14846
69	69	/* devices */
70	70	required_device<cpu_device> m_maincpu;
71	71	required_device<cpu_device> m_audiocpu;
	72	DECLARE_WRITE8_MEMBER(bg_scroll_x_w);
	73	DECLARE_WRITE8_MEMBER(bg_scroll_y_w);
	74	DECLARE_WRITE8_MEMBER(background_w);
	75	DECLARE_WRITE8_MEMBER(foreground_w);
	76	DECLARE_WRITE8_MEMBER(bg_bank_w);
	77	DECLARE_WRITE8_MEMBER(coins_w);
	78	DECLARE_WRITE8_MEMBER(snd_w);
	79	DECLARE_WRITE8_MEMBER(main_irq_ack_w);
	80	DECLARE_WRITE8_MEMBER(adpcm_w);
	81	DECLARE_WRITE8_MEMBER(snd_ack_w);
	82	DECLARE_WRITE8_MEMBER(snd_irq_w);
	83	DECLARE_WRITE8_MEMBER(music_irq_w);
72	84	};
73	85
74	86	static TILE_GET_INFO( get_bg_tile_info )
r14845	r14846
92	104	state->m_fg_tilemap->set_transparent_pen(0);
93	105	}
94	106
95		static WRITE8_HANDLER( bg_scroll_x_w )
	107	WRITE8_MEMBER(dacholer_state::bg_scroll_x_w)
96	108	{
97		dacholer_state *state = space->machine().driver_data<dacholer_state>();
98		state->m_scroll_x = data;
	109	m_scroll_x = data;
99	110	}
100	111
101		static WRITE8_HANDLER( bg_scroll_y_w )
	112	WRITE8_MEMBER(dacholer_state::bg_scroll_y_w)
102	113	{
103		dacholer_state *state = space->machine().driver_data<dacholer_state>();
104		state->m_scroll_y = data;
	114	m_scroll_y = data;
105	115	}
106	116
107	117	static void draw_sprites( running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect )
r14845	r14846
157	167	return 0;
158	168	}
159	169
160		static WRITE8_HANDLER( background_w )
	170	WRITE8_MEMBER(dacholer_state::background_w)
161	171	{
162		dacholer_state *state = space->machine().driver_data<dacholer_state>();
163		state->m_bgvideoram[offset] = data;
164		state->m_bg_tilemap->mark_tile_dirty(offset);
	172	m_bgvideoram[offset] = data;
	173	m_bg_tilemap->mark_tile_dirty(offset);
165	174	}
166	175
167		static WRITE8_HANDLER( foreground_w )
	176	WRITE8_MEMBER(dacholer_state::foreground_w)
168	177	{
169		dacholer_state *state = space->machine().driver_data<dacholer_state>();
170		state->m_fgvideoram[offset] = data;
171		state->m_fg_tilemap->mark_tile_dirty(offset);
	178	m_fgvideoram[offset] = data;
	179	m_fg_tilemap->mark_tile_dirty(offset);
172	180	}
173	181
174		static WRITE8_HANDLER( bg_bank_w )
	182	WRITE8_MEMBER(dacholer_state::bg_bank_w)
175	183	{
176		dacholer_state *state = space->machine().driver_data<dacholer_state>();
177		if ((data & 3) != state->m_bg_bank)
	184	if ((data & 3) != m_bg_bank)
178	185	{
179		state->m_bg_bank = data & 3;
180		state->m_bg_tilemap->mark_all_dirty();
	186	m_bg_bank = data & 3;
	187	m_bg_tilemap->mark_all_dirty();
181	188	}
182	189
183		flip_screen_set(space->machine(), data & 0xc); // probably one bit for flipx and one for flipy
	190	flip_screen_set(machine(), data & 0xc); // probably one bit for flipx and one for flipy
184	191
185	192	}
186	193
187		static WRITE8_HANDLER( coins_w )
	194	WRITE8_MEMBER(dacholer_state::coins_w)
188	195	{
189		coin_counter_w(space->machine(), 0, data & 1);
190		coin_counter_w(space->machine(), 1, data & 2);
	196	coin_counter_w(machine(), 0, data & 1);
	197	coin_counter_w(machine(), 1, data & 2);
191	198
192		set_led_status(space->machine(), 0, data & 4);
193		set_led_status(space->machine(), 1, data & 8);
	199	set_led_status(machine(), 0, data & 4);
	200	set_led_status(machine(), 1, data & 8);
194	201	}
195	202
196		static WRITE8_HANDLER(snd_w)
	203	WRITE8_MEMBER(dacholer_state::snd_w)
197	204	{
198		dacholer_state *state = space->machine().driver_data<dacholer_state>();
199	205	soundlatch_w(space, offset, data);
200		device_set_input_line(state->m_audiocpu, INPUT_LINE_NMI, PULSE_LINE);
	206	device_set_input_line(m_audiocpu, INPUT_LINE_NMI, PULSE_LINE);
201	207	}
202	208
203		static WRITE8_HANDLER( main_irq_ack_w )
	209	WRITE8_MEMBER(dacholer_state::main_irq_ack_w)
204	210	{
205		dacholer_state *state = space->machine().driver_data<dacholer_state>();
206		device_set_input_line(state->m_maincpu, 0, CLEAR_LINE);
	211	device_set_input_line(m_maincpu, 0, CLEAR_LINE);
207	212	}
208	213
209	214
210	215	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, dacholer_state )
211	216	AM_RANGE(0x0000, 0x7fff) AM_ROM
212	217	AM_RANGE(0x8800, 0x97ff) AM_RAM
213		AM_RANGE(0xc000, 0xc3ff) AM_MIRROR(0x400) AM_RAM_WRITE_LEGACY(background_w) AM_BASE(m_bgvideoram)
214		AM_RANGE(0xd000, 0xd3ff) AM_RAM_WRITE_LEGACY(foreground_w) AM_BASE(m_fgvideoram)
	218	AM_RANGE(0xc000, 0xc3ff) AM_MIRROR(0x400) AM_RAM_WRITE(background_w) AM_BASE(m_bgvideoram)
	219	AM_RANGE(0xd000, 0xd3ff) AM_RAM_WRITE(foreground_w) AM_BASE(m_fgvideoram)
215	220	AM_RANGE(0xe000, 0xe0ff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
216	221	ADDRESS_MAP_END
217	222
r14845	r14846
229	234	AM_RANGE(0x03, 0x03) AM_READ_PORT("DSWA")
230	235	AM_RANGE(0x04, 0x04) AM_READ_PORT("DSWB")
231	236	AM_RANGE(0x05, 0x05) AM_READNOP // watchdog in itaten
232		AM_RANGE(0x20, 0x20) AM_WRITE_LEGACY(coins_w)
233		AM_RANGE(0x21, 0x21) AM_WRITE_LEGACY(bg_bank_w)
234		AM_RANGE(0x22, 0x22) AM_WRITE_LEGACY(bg_scroll_x_w)
235		AM_RANGE(0x23, 0x23) AM_WRITE_LEGACY(bg_scroll_y_w)
236		AM_RANGE(0x24, 0x24) AM_WRITE_LEGACY(main_irq_ack_w)
237		AM_RANGE(0x27, 0x27) AM_WRITE_LEGACY(snd_w)
	237	AM_RANGE(0x20, 0x20) AM_WRITE(coins_w)
	238	AM_RANGE(0x21, 0x21) AM_WRITE(bg_bank_w)
	239	AM_RANGE(0x22, 0x22) AM_WRITE(bg_scroll_x_w)
	240	AM_RANGE(0x23, 0x23) AM_WRITE(bg_scroll_y_w)
	241	AM_RANGE(0x24, 0x24) AM_WRITE(main_irq_ack_w)
	242	AM_RANGE(0x27, 0x27) AM_WRITE(snd_w)
238	243	ADDRESS_MAP_END
239	244
240	245
r14845	r14846
250	255	ADDRESS_MAP_END
251	256
252	257
253		static WRITE8_HANDLER( adpcm_w )
	258	WRITE8_MEMBER(dacholer_state::adpcm_w)
254	259	{
255		dacholer_state *state = space->machine().driver_data<dacholer_state>();
256		state->m_msm_data = data;
257		state->m_msm_toggle = 0;
	260	m_msm_data = data;
	261	m_msm_toggle = 0;
258	262	}
259	263
260		static WRITE8_HANDLER( snd_ack_w )
	264	WRITE8_MEMBER(dacholer_state::snd_ack_w)
261	265	{
262		dacholer_state *state = space->machine().driver_data<dacholer_state>();
263		state->m_snd_ack = data;
	266	m_snd_ack = data;
264	267	}
265	268
266	269	static CUSTOM_INPUT( snd_ack_r )
r14845	r14846
269	272	return state->m_snd_ack;      //guess ...
270	273	}
271	274
272		static WRITE8_HANDLER( snd_irq_w )
	275	WRITE8_MEMBER(dacholer_state::snd_irq_w)
273	276	{
274		dacholer_state *state = space->machine().driver_data<dacholer_state>();
275		state->m_snd_interrupt_enable = data;
	277	m_snd_interrupt_enable = data;
276	278	}
277	279
278		static WRITE8_HANDLER( music_irq_w )
	280	WRITE8_MEMBER(dacholer_state::music_irq_w)
279	281	{
280		dacholer_state *state = space->machine().driver_data<dacholer_state>();
281		state->m_music_interrupt_enable = data;
	282	m_music_interrupt_enable = data;
282	283	}
283	284
284	285	static ADDRESS_MAP_START( snd_io_map, AS_IO, 8, dacholer_state )
285	286	ADDRESS_MAP_GLOBAL_MASK(0xff)
286	287	AM_RANGE(0x00, 0x00) AM_READWRITE_LEGACY(soundlatch_r, soundlatch_clear_w )
287		AM_RANGE(0x04, 0x04) AM_WRITE_LEGACY(music_irq_w)
288		AM_RANGE(0x08, 0x08) AM_WRITE_LEGACY(snd_irq_w)
289		AM_RANGE(0x0c, 0x0c) AM_WRITE_LEGACY(snd_ack_w)
290		AM_RANGE(0x80, 0x80) AM_WRITE_LEGACY(adpcm_w)
	288	AM_RANGE(0x04, 0x04) AM_WRITE(music_irq_w)
	289	AM_RANGE(0x08, 0x08) AM_WRITE(snd_irq_w)
	290	AM_RANGE(0x0c, 0x0c) AM_WRITE(snd_ack_w)
	291	AM_RANGE(0x80, 0x80) AM_WRITE(adpcm_w)
291	292	AM_RANGE(0x86, 0x87) AM_DEVWRITE_LEGACY("ay1", ay8910_data_address_w)
292	293	AM_RANGE(0x8a, 0x8b) AM_DEVWRITE_LEGACY("ay2", ay8910_data_address_w)
293	294	AM_RANGE(0x8e, 0x8f) AM_DEVWRITE_LEGACY("ay3", ay8910_data_address_w)

src/mame/drivers/wallc.c

r14845	r14846
61	61
62	62	UINT8 *m_videoram;
63	63	tilemap_t *m_bg_tilemap;
	64	DECLARE_WRITE8_MEMBER(wallc_videoram_w);
	65	DECLARE_WRITE8_MEMBER(wallc_coin_counter_w);
64	66	};
65	67
66	68
r14845	r14846
126	128	}
127	129	}
128	130
129		static WRITE8_HANDLER( wallc_videoram_w )
	131	WRITE8_MEMBER(wallc_state::wallc_videoram_w)
130	132	{
131		wallc_state *state = space->machine().driver_data<wallc_state>();
132		UINT8 *videoram = state->m_videoram;
	133	UINT8 *videoram = m_videoram;
133	134	videoram[offset] = data;
134		state->m_bg_tilemap->mark_tile_dirty(offset);
	135	m_bg_tilemap->mark_tile_dirty(offset);
135	136	}
136	137
137	138	static TILE_GET_INFO( get_bg_tile_info )
r14845	r14846
154	155	return 0;
155	156	}
156	157
157		static WRITE8_HANDLER( wallc_coin_counter_w )
	158	WRITE8_MEMBER(wallc_state::wallc_coin_counter_w)
158	159	{
159		coin_counter_w(space->machine(), 0,data & 2);
	160	coin_counter_w(machine(), 0,data & 2);
160	161	}
161	162
162	163	static ADDRESS_MAP_START( wallc_map, AS_PROGRAM, 8, wallc_state )
163	164	AM_RANGE(0x0000, 0x7fff) AM_ROM
164		AM_RANGE(0x8000, 0x83ff) AM_RAM_WRITE_LEGACY(wallc_videoram_w) AM_MIRROR(0xc00) AM_BASE(m_videoram)   /* 2114, 2114 */
	165	AM_RANGE(0x8000, 0x83ff) AM_RAM_WRITE(wallc_videoram_w) AM_MIRROR(0xc00) AM_BASE(m_videoram)   /* 2114, 2114 */
165	166	AM_RANGE(0xa000, 0xa3ff) AM_RAM      /* 2114, 2114 */
166	167
167	168	AM_RANGE(0xb000, 0xb000) AM_READ_PORT("DSW1")
r14845	r14846
170	171	AM_RANGE(0xb600, 0xb600) AM_READ_PORT("DSW2")
171	172
172	173	AM_RANGE(0xb000, 0xb000) AM_WRITENOP
173		AM_RANGE(0xb100, 0xb100) AM_WRITE_LEGACY(wallc_coin_counter_w)
	174	AM_RANGE(0xb100, 0xb100) AM_WRITE(wallc_coin_counter_w)
174	175	AM_RANGE(0xb200, 0xb200) AM_WRITENOP
175	176	AM_RANGE(0xb500, 0xb500) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
176	177	AM_RANGE(0xb600, 0xb600) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)

src/mame/drivers/marinedt.c

r14845	r14846
130	130	UINT8 m_cxh;
131	131	UINT8 m_cyrh;
132	132	UINT8 m_cyqh;
	133	DECLARE_WRITE8_MEMBER(tx_tileram_w);
	134	DECLARE_READ8_MEMBER(marinedt_port1_r);
	135	DECLARE_READ8_MEMBER(marinedt_coll_r);
	136	DECLARE_READ8_MEMBER(marinedt_obj1_x_r);
	137	DECLARE_READ8_MEMBER(marinedt_obj1_yr_r);
	138	DECLARE_READ8_MEMBER(marinedt_obj1_yq_r);
	139	DECLARE_WRITE8_MEMBER(marinedt_obj1_a_w);
	140	DECLARE_WRITE8_MEMBER(marinedt_obj1_x_w);
	141	DECLARE_WRITE8_MEMBER(marinedt_obj1_y_w);
	142	DECLARE_WRITE8_MEMBER(marinedt_obj2_a_w);
	143	DECLARE_WRITE8_MEMBER(marinedt_obj2_x_w);
	144	DECLARE_WRITE8_MEMBER(marinedt_obj2_y_w);
	145	DECLARE_WRITE8_MEMBER(marinedt_music_w);
	146	DECLARE_WRITE8_MEMBER(marinedt_sound_w);
	147	DECLARE_WRITE8_MEMBER(marinedt_pd_w);
	148	DECLARE_WRITE8_MEMBER(marinedt_pf_w);
133	149	};
134	150
135	151
136		static WRITE8_HANDLER( tx_tileram_w )
	152	WRITE8_MEMBER(marinedt_state::tx_tileram_w)
137	153	{
138		marinedt_state *state = space->machine().driver_data<marinedt_state>();
139	154
140		state->m_tx_tileram[offset] = data;
141		state->m_tx_tilemap->mark_tile_dirty(offset);
	155	m_tx_tileram[offset] = data;
	156	m_tx_tilemap->mark_tile_dirty(offset);
142	157	}
143	158
144		static READ8_HANDLER( marinedt_port1_r )
	159	READ8_MEMBER(marinedt_state::marinedt_port1_r)
145	160	{
146		marinedt_state *state = space->machine().driver_data<marinedt_state>();
147	161
148	162	//might need to be reversed for cocktail stuff
149	163
150	164	/* x/y multiplexed */
151		return input_port_read(space->machine(), ((state->m_pf & 0x08) >> 3) ? "TRACKY" : "TRACKX");
	165	return input_port_read(machine(), ((m_pf & 0x08) >> 3) ? "TRACKY" : "TRACKX");
152	166	}
153	167
154		static READ8_HANDLER( marinedt_coll_r )
	168	READ8_MEMBER(marinedt_state::marinedt_coll_r)
155	169	{
156	170	//76543210
157	171	//x------- obj1 to obj2 collision
r14845	r14846
159	173	//----x--- obj1 to playfield collision
160	174	//-----xxx unused
161	175
162		marinedt_state *state = space->machine().driver_data<marinedt_state>();
163		return state->m_coll | state->m_collh;
	176	return m_coll | m_collh;
164	177	}
165	178
166	179	//are these returning only during a collision?
167	180	//id imagine they are returning the pf char where the collission took place?
168	181	//what about where there is lots of colls?
169	182	//maybe the first on a scanline basis
170		static READ8_HANDLER( marinedt_obj1_x_r )
	183	READ8_MEMBER(marinedt_state::marinedt_obj1_x_r)
171	184	{
172	185	//76543210
173	186	//xxxx---- unknown
174	187	//----xxxx x pos in tile ram
175	188
176		marinedt_state *state = space->machine().driver_data<marinedt_state>();
177		UINT8 *RAM = space->machine().region("maincpu")->base();
	189	UINT8 *RAM = machine().region("maincpu")->base();
178	190
179	191	if (RAM[0x430e])
180		--state->m_cx;
	192	--m_cx;
181	193	else
182		++state->m_cx;
	194	++m_cx;
183	195
184	196	//figure out why inc/dec based on 430e?
185		return state->m_cx | (state->m_cxh << 4);
	197	return m_cx | (m_cxh << 4);
186	198	}
187	199
188		static READ8_HANDLER( marinedt_obj1_yr_r )
	200	READ8_MEMBER(marinedt_state::marinedt_obj1_yr_r)
189	201	{
190	202	//76543210
191	203	//xxxx---- unknown
192	204	//----xxxx row in current screen quarter
193	205
194		marinedt_state *state = space->machine().driver_data<marinedt_state>();
195	206
196	207	//has to be +1 if cx went over?
197		if (state->m_cx == 0x10)
198		state->m_cyr++;
	208	if (m_cx == 0x10)
	209	m_cyr++;
199	210
200		return state->m_cyr | (state->m_cyrh << 4);
	211	return m_cyr | (m_cyrh << 4);
201	212	}
202	213
203		static READ8_HANDLER( marinedt_obj1_yq_r )
	214	READ8_MEMBER(marinedt_state::marinedt_obj1_yq_r)
204	215	{
205	216	//76543210
206	217	//xx------ unknown
r14845	r14846
208	219	//----xx-- unknown
209	220	//------xx screen quarter
210	221
211		marinedt_state *state = space->machine().driver_data<marinedt_state>();
212		return state->m_cyq | (state->m_cyqh << 4);
	222	return m_cyq | (m_cyqh << 4);
213	223	}
214	224
215		static WRITE8_HANDLER( marinedt_obj1_a_w ) { marinedt_state *state = space->machine().driver_data<marinedt_state>();    state->m_obj1_a = data; }
216		static WRITE8_HANDLER( marinedt_obj1_x_w ) { marinedt_state *state = space->machine().driver_data<marinedt_state>();    state->m_obj1_x = data; }
217		static WRITE8_HANDLER( marinedt_obj1_y_w ) { marinedt_state *state = space->machine().driver_data<marinedt_state>();    state->m_obj1_y = data; }
218		static WRITE8_HANDLER( marinedt_obj2_a_w ) { marinedt_state *state = space->machine().driver_data<marinedt_state>();    state->m_obj2_a = data; }
219		static WRITE8_HANDLER( marinedt_obj2_x_w ) { marinedt_state *state = space->machine().driver_data<marinedt_state>();    state->m_obj2_x = data; }
220		static WRITE8_HANDLER( marinedt_obj2_y_w ) { marinedt_state *state = space->machine().driver_data<marinedt_state>();    state->m_obj2_y = data; }
	225	WRITE8_MEMBER(marinedt_state::marinedt_obj1_a_w){ m_obj1_a = data; }
	226	WRITE8_MEMBER(marinedt_state::marinedt_obj1_x_w){ m_obj1_x = data; }
	227	WRITE8_MEMBER(marinedt_state::marinedt_obj1_y_w){ m_obj1_y = data; }
	228	WRITE8_MEMBER(marinedt_state::marinedt_obj2_a_w){ m_obj2_a = data; }
	229	WRITE8_MEMBER(marinedt_state::marinedt_obj2_x_w){ m_obj2_x = data; }
	230	WRITE8_MEMBER(marinedt_state::marinedt_obj2_y_w){ m_obj2_y = data; }
221	231
222		static WRITE8_HANDLER( marinedt_music_w ){ marinedt_state *state = space->machine().driver_data<marinedt_state>();    state->m_music = data; }
	232	WRITE8_MEMBER(marinedt_state::marinedt_music_w){ m_music = data; }
223	233
224		static WRITE8_HANDLER( marinedt_sound_w )
	234	WRITE8_MEMBER(marinedt_state::marinedt_sound_w)
225	235	{
226	236	//76543210
227	237	//xx------ ??
r14845	r14846
232	242	//------x- dots hit
233	243	//-------x ??
234	244
235		marinedt_state *state = space->machine().driver_data<marinedt_state>();
236		state->m_sound = data;
	245	m_sound = data;
237	246	}
238	247
239		static WRITE8_HANDLER( marinedt_pd_w )
	248	WRITE8_MEMBER(marinedt_state::marinedt_pd_w)
240	249	{
241	250	//76543210
242	251	//xxx----- ?? unused
r14845	r14846
246	255	//------x- obj2 enable
247	256	//-------x obj1 enable
248	257
249		marinedt_state *state = space->machine().driver_data<marinedt_state>();
250		state->m_pd = data;
	258	m_pd = data;
251	259	}
252	260
253	261	/*
r14845	r14846
265	273	marinedt_pf_w: 07   // cocktail
266	274	marinedt_pf_w: 03   // non-flip sprite?
267	275	*/
268		static WRITE8_HANDLER( marinedt_pf_w )
	276	WRITE8_MEMBER(marinedt_state::marinedt_pf_w)
269	277	{
270	278	//76543210
271	279	//xxxx---- ?? unused (will need to understand table of written values)
r14845	r14846
274	282	//------x- ?? upright/cocktail
275	283	//-------x ?? service mode (coin lockout??)
276	284
277		marinedt_state *state = space->machine().driver_data<marinedt_state>();
278	285
279		//if ((state->m_pf & 0x07) != (data & 0x07))
	286	//if ((m_pf & 0x07) != (data & 0x07))
280	287	//  mame_printf_debug("marinedt_pf_w: %02x\n", data & 0x07);
281	288
282		if ((state->m_pf & 0x02) != (data & 0x02))
	289	if ((m_pf & 0x02) != (data & 0x02))
283	290	{
284	291	if (data & 0x02)
285	292	mame_printf_debug("tile flip\n");
r14845	r14846
287	294	mame_printf_debug("tile non-flip\n");
288	295
289	296	if (data & 0x02)
290		state->m_tx_tilemap->set_flip(TILEMAP_FLIPX | TILEMAP_FLIPY);
	297	m_tx_tilemap->set_flip(TILEMAP_FLIPX | TILEMAP_FLIPY);
291	298	else
292		state->m_tx_tilemap->set_flip(0);
	299	m_tx_tilemap->set_flip(0);
293	300	}
294	301
295		state->m_pf = data;
	302	m_pf = data;
296	303
297	304	//if (data & 0xf0)
298		//    logerror("pf:%02x %d\n", state->m_pf);
299		//logerror("pd:%02x %d\n", state->m_pd, space->machine().primary_screen->frame_number());
	305	//    logerror("pf:%02x %d\n", m_pf);
	306	//logerror("pd:%02x %d\n", m_pd, machine().primary_screen->frame_number());
300	307
301	308	}
302	309
r14845	r14846
304	311	AM_RANGE(0x0000, 0x37ff) AM_ROM
305	312	AM_RANGE(0x4000, 0x43ff) AM_RAM
306	313	AM_RANGE(0x4400, 0x47ff) AM_RAM            //unused, vram mirror?
307		AM_RANGE(0x4800, 0x4bff) AM_RAM_WRITE_LEGACY(tx_tileram_w) AM_BASE(m_tx_tileram)
	314	AM_RANGE(0x4800, 0x4bff) AM_RAM_WRITE(tx_tileram_w) AM_BASE(m_tx_tileram)
308	315	AM_RANGE(0x4c00, 0x4c00) AM_WRITENOP   //?? maybe off by one error
309	316	ADDRESS_MAP_END
310	317
311	318	static ADDRESS_MAP_START( marinedt_io_map, AS_IO, 8, marinedt_state )
312	319	ADDRESS_MAP_GLOBAL_MASK(0xff)
313	320	AM_RANGE(0x00, 0x00) AM_READ_PORT("DSW0")      //dips coinage
314		AM_RANGE(0x01, 0x01) AM_READ_LEGACY(marinedt_port1_r)   //trackball xy muxed
315		AM_RANGE(0x02, 0x02) AM_READWRITE_LEGACY(marinedt_obj1_x_r, marinedt_obj1_a_w)
316		AM_RANGE(0x03, 0x03) AM_READ_PORT("IN0") AM_WRITE_LEGACY(marinedt_obj1_x_w)
317		AM_RANGE(0x04, 0x04) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(marinedt_obj1_y_w)
318		AM_RANGE(0x05, 0x05) AM_WRITE_LEGACY(marinedt_music_w)
319		AM_RANGE(0x06, 0x06) AM_READWRITE_LEGACY(marinedt_obj1_yr_r, marinedt_sound_w)
320		AM_RANGE(0x08, 0x08) AM_WRITE_LEGACY(marinedt_obj2_a_w)
321		AM_RANGE(0x09, 0x09) AM_WRITE_LEGACY(marinedt_obj2_x_w)
322		AM_RANGE(0x0a, 0x0a) AM_READWRITE_LEGACY(marinedt_obj1_yq_r, marinedt_obj2_y_w)
323		AM_RANGE(0x0d, 0x0d) AM_WRITE_LEGACY(marinedt_pd_w)
324		AM_RANGE(0x0e, 0x0e) AM_READWRITE_LEGACY(marinedt_coll_r, watchdog_reset_w)
325		AM_RANGE(0x0f, 0x0f) AM_WRITE_LEGACY(marinedt_pf_w)
	321	AM_RANGE(0x01, 0x01) AM_READ(marinedt_port1_r)   //trackball xy muxed
	322	AM_RANGE(0x02, 0x02) AM_READWRITE(marinedt_obj1_x_r, marinedt_obj1_a_w)
	323	AM_RANGE(0x03, 0x03) AM_READ_PORT("IN0") AM_WRITE(marinedt_obj1_x_w)
	324	AM_RANGE(0x04, 0x04) AM_READ_PORT("DSW1") AM_WRITE(marinedt_obj1_y_w)
	325	AM_RANGE(0x05, 0x05) AM_WRITE(marinedt_music_w)
	326	AM_RANGE(0x06, 0x06) AM_READWRITE(marinedt_obj1_yr_r, marinedt_sound_w)
	327	AM_RANGE(0x08, 0x08) AM_WRITE(marinedt_obj2_a_w)
	328	AM_RANGE(0x09, 0x09) AM_WRITE(marinedt_obj2_x_w)
	329	AM_RANGE(0x0a, 0x0a) AM_READWRITE(marinedt_obj1_yq_r, marinedt_obj2_y_w)
	330	AM_RANGE(0x0d, 0x0d) AM_WRITE(marinedt_pd_w)
	331	AM_RANGE(0x0e, 0x0e) AM_READWRITE(marinedt_coll_r, watchdog_reset_w)
	332	AM_RANGE(0x0f, 0x0f) AM_WRITE(marinedt_pf_w)
326	333	ADDRESS_MAP_END
327	334
328	335

src/mame/drivers/sliver.c

r14845	r14846
103	103	UINT16 m_tempbuf[8];
104	104
105	105	required_device<cpu_device> m_maincpu;
	106	DECLARE_WRITE16_MEMBER(fifo_data_w);
	107	DECLARE_WRITE16_MEMBER(fifo_clear_w);
	108	DECLARE_WRITE16_MEMBER(fifo_flush_w);
	109	DECLARE_WRITE16_MEMBER(jpeg1_w);
	110	DECLARE_WRITE16_MEMBER(jpeg2_w);
	111	DECLARE_WRITE16_MEMBER(io_offset_w);
	112	DECLARE_WRITE16_MEMBER(io_data_w);
	113	DECLARE_WRITE16_MEMBER(sound_w);
	114	DECLARE_WRITE8_MEMBER(oki_setbank);
106	115	};
107	116
108	117	static void plot_pixel_rgb(sliver_state *state, int x, int y, UINT32 r, UINT32 g, UINT32 b)
r14845	r14846
130	139	state->m_bitmap_fg.pix32(y, x) = r | (g<<8) | (b<<16);
131	140	}
132	141
133		static WRITE16_HANDLER( fifo_data_w )
	142	WRITE16_MEMBER(sliver_state::fifo_data_w)
134	143	{
135		sliver_state *state = space->machine().driver_data<sliver_state>();
136	144
137		if (state->m_tmp_counter < 8)
	145	if (m_tmp_counter < 8)
138	146	{
139		COMBINE_DATA(&state->m_tempbuf[state->m_tmp_counter]);
140		state->m_tmp_counter++;
141		if (state->m_tmp_counter == 8) // copy 8 bytes to fifo,  every byte should be copied directly, but it's easier to copy whole commands
	147	COMBINE_DATA(&m_tempbuf[m_tmp_counter]);
	148	m_tmp_counter++;
	149	if (m_tmp_counter == 8) // copy 8 bytes to fifo,  every byte should be copied directly, but it's easier to copy whole commands
142	150	{
143	151	do
144	152	{
145		state->m_fifo[state->m_fptr++]=state->m_tempbuf[8-state->m_tmp_counter];
146		if (state->m_fptr > (FIFO_SIZE - 1))
	153	m_fifo[m_fptr++]=m_tempbuf[8-m_tmp_counter];
	154	if (m_fptr > (FIFO_SIZE - 1))
147	155	{
148		state->m_fptr=FIFO_SIZE-1;
	156	m_fptr=FIFO_SIZE-1;
149	157	}
150	158	}
151		while (--state->m_tmp_counter > 0);
	159	while (--m_tmp_counter > 0);
152	160	}
153	161	}
154	162	}
r14845	r14846
187	195	}
188	196	}
189	197
190		static WRITE16_HANDLER( fifo_clear_w )
	198	WRITE16_MEMBER(sliver_state::fifo_clear_w)
191	199	{
192		sliver_state *state = space->machine().driver_data<sliver_state>();
193	200
194		state->m_bitmap_fg.fill(0);
195		state->m_fptr=0;
196		state->m_tmp_counter=0;
	201	m_bitmap_fg.fill(0);
	202	m_fptr=0;
	203	m_tmp_counter=0;
197	204	}
198	205
199		static WRITE16_HANDLER( fifo_flush_w )
	206	WRITE16_MEMBER(sliver_state::fifo_flush_w)
200	207	{
201		blit_gfx(space->machine());
	208	blit_gfx(machine());
202	209	}
203	210
204	211
205		static WRITE16_HANDLER( jpeg1_w )
	212	WRITE16_MEMBER(sliver_state::jpeg1_w)
206	213	{
207		sliver_state *state = space->machine().driver_data<sliver_state>();
208	214
209		COMBINE_DATA(&state->m_jpeg1);
	215	COMBINE_DATA(&m_jpeg1);
210	216	}
211	217
212	218	static void render_jpeg(running_machine &machine)
r14845	r14846
266	272
267	273	}
268	274
269		static WRITE16_HANDLER( jpeg2_w )
	275	WRITE16_MEMBER(sliver_state::jpeg2_w)
270	276	{
271		sliver_state *state = space->machine().driver_data<sliver_state>();
272	277
273		COMBINE_DATA(&state->m_jpeg2);
	278	COMBINE_DATA(&m_jpeg2);
274	279
275		render_jpeg(space->machine());
	280	render_jpeg(machine());
276	281
277	282	}
278	283
279		static WRITE16_HANDLER(io_offset_w)
	284	WRITE16_MEMBER(sliver_state::io_offset_w)
280	285	{
281		sliver_state *state = space->machine().driver_data<sliver_state>();
282	286
283		COMBINE_DATA(&state->m_io_offset);
	287	COMBINE_DATA(&m_io_offset);
284	288	}
285	289
286		static WRITE16_HANDLER(io_data_w)
	290	WRITE16_MEMBER(sliver_state::io_data_w)
287	291	{
288		sliver_state *state = space->machine().driver_data<sliver_state>();
289	292
290		if (state->m_io_offset < IO_SIZE)
	293	if (m_io_offset < IO_SIZE)
291	294	{
292	295	int tmpx, tmpy;
293		COMBINE_DATA(&state->m_io_reg[state->m_io_offset]);
	296	COMBINE_DATA(&m_io_reg[m_io_offset]);
294	297
295		tmpy = state->m_io_reg[0x1a] + (state->m_io_reg[0x1b] << 8) - state->m_io_reg[0x20]; //0x20  ???
296		tmpx = state->m_io_reg[0x1e] + (state->m_io_reg[0x1f] << 8);
	298	tmpy = m_io_reg[0x1a] + (m_io_reg[0x1b] << 8) - m_io_reg[0x20]; //0x20  ???
	299	tmpx = m_io_reg[0x1e] + (m_io_reg[0x1f] << 8);
297	300
298		if (tmpy != state->m_jpeg_y || tmpx != state->m_jpeg_x)
	301	if (tmpy != m_jpeg_y || tmpx != m_jpeg_x)
299	302	{
300		state->m_jpeg_x = tmpx;
301		state->m_jpeg_y = tmpy;
302		render_jpeg(space->machine());
	303	m_jpeg_x = tmpx;
	304	m_jpeg_y = tmpy;
	305	render_jpeg(machine());
303	306	}
304	307	}
305	308	else
306	309	{
307		logerror("I/O access out of range: %x\n", state->m_io_offset);
	310	logerror("I/O access out of range: %x\n", m_io_offset);
308	311	}
309	312	}
310	313
311		static WRITE16_HANDLER(sound_w)
	314	WRITE16_MEMBER(sliver_state::sound_w)
312	315	{
313	316	soundlatch_w(space, 0, data & 0xff);
314		cputag_set_input_line(space->machine(), "audiocpu", MCS51_INT0_LINE, HOLD_LINE);
	317	cputag_set_input_line(machine(), "audiocpu", MCS51_INT0_LINE, HOLD_LINE);
315	318	}
316	319
317	320	static ADDRESS_MAP_START( sliver_map, AS_PROGRAM, 16, sliver_state )
r14845	r14846
323	326
324	327	AM_RANGE(0x300002, 0x300003) AM_NOP // bit 0 tested, writes 0xe0 and 0xc0 - both r and w at the end of interrupt code
325	328
326		AM_RANGE(0x300004, 0x300005) AM_WRITE_LEGACY(io_offset_w) //unknown i/o device
327		AM_RANGE(0x300006, 0x300007) AM_WRITE_LEGACY(io_data_w)
	329	AM_RANGE(0x300004, 0x300005) AM_WRITE(io_offset_w) //unknown i/o device
	330	AM_RANGE(0x300006, 0x300007) AM_WRITE(io_data_w)
328	331
329	332	AM_RANGE(0x400000, 0x400001) AM_READ_PORT("P1_P2")
330	333	AM_RANGE(0x400002, 0x400003) AM_READ_PORT("SYSTEM")
331	334	AM_RANGE(0x400004, 0x400005) AM_READ_PORT("DSW")
332		AM_RANGE(0x400006, 0x400007) AM_WRITE_LEGACY(fifo_data_w)
333		AM_RANGE(0x400008, 0x400009) AM_WRITE_LEGACY(fifo_clear_w)
334		AM_RANGE(0x40000a, 0x40000b) AM_WRITE_LEGACY(fifo_flush_w)
335		AM_RANGE(0x40000c, 0x40000d) AM_WRITE_LEGACY(jpeg1_w)
336		AM_RANGE(0x40000e, 0x40000f) AM_WRITE_LEGACY(jpeg2_w)
	335	AM_RANGE(0x400006, 0x400007) AM_WRITE(fifo_data_w)
	336	AM_RANGE(0x400008, 0x400009) AM_WRITE(fifo_clear_w)
	337	AM_RANGE(0x40000a, 0x40000b) AM_WRITE(fifo_flush_w)
	338	AM_RANGE(0x40000c, 0x40000d) AM_WRITE(jpeg1_w)
	339	AM_RANGE(0x40000e, 0x40000f) AM_WRITE(jpeg2_w)
337	340
338	341	AM_RANGE(0x400010, 0x400015) AM_WRITENOP //unknown
339		AM_RANGE(0x400016, 0x400017) AM_WRITE_LEGACY(sound_w)
	342	AM_RANGE(0x400016, 0x400017) AM_WRITE(sound_w)
340	343	AM_RANGE(0x400018, 0x400019) AM_WRITENOP //unknown
341	344
342	345	AM_RANGE(0xff0000, 0xffffff) AM_RAM
r14845	r14846
344	347
345	348	// Sound CPU
346	349
347		static WRITE8_HANDLER(oki_setbank)
	350	WRITE8_MEMBER(sliver_state::oki_setbank)
348	351	{
349		UINT8 *sound = space->machine().region("oki")->base();
	352	UINT8 *sound = machine().region("oki")->base();
350	353	int bank=(data^0xff)&3; //xor or not ?
351	354	memcpy(sound+0x20000, sound+0x100000+0x20000*bank, 0x20000);
352	355	}
r14845	r14846
359	362	AM_RANGE(0x0100, 0x0100) AM_DEVREADWRITE("oki", okim6295_device, read, write)
360	363	AM_RANGE(0x0101, 0x0101) AM_READ_LEGACY(soundlatch_r)
361	364	/* ports */
362		AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE_LEGACY(oki_setbank )
	365	AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(oki_setbank )
363	366	ADDRESS_MAP_END
364	367
365	368	static VIDEO_START(sliver)

src/mame/drivers/tonton.c

r14845	r14846
38	38	m_v9938(*this, "v9938") { }
39	39
40	40	required_device<v9938_device> m_v9938;
	41	DECLARE_WRITE8_MEMBER(tonton_outport_w);
41	42	};
42	43
43	44	#define MAIN_CLOCK XTAL_21_4772MHz
r14845	r14846
66	67	*          Multi-Purpose Output Port             *
67	68	*************************************************/
68	69
69		static WRITE8_HANDLER( tonton_outport_w )
	70	WRITE8_MEMBER(tonton_state::tonton_outport_w)
70	71	{
71	72	/* lockout perhaps? */
72		coin_counter_w(space->machine(), offset, data & 0x01);
	73	coin_counter_w(machine(), offset, data & 0x01);
73	74
74	75	// data & 2 is hopper related
75	76
r14845	r14846
92	93	ADDRESS_MAP_GLOBAL_MASK(0xff)
93	94	AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0")
94	95	AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1")
95		AM_RANGE(0x00, 0x01) AM_WRITE_LEGACY(tonton_outport_w)
	96	AM_RANGE(0x00, 0x01) AM_WRITE(tonton_outport_w)
96	97	AM_RANGE(0x02, 0x02) AM_READ_PORT("DSW1")
97	98	AM_RANGE(0x03, 0x03) AM_READ_PORT("DSW2")
98	99	AM_RANGE(0x88, 0x8b) AM_DEVREADWRITE( "v9938", v9938_device, read, write )

src/mame/drivers/subsino.c

r14845	r14846
257	257	int m_colordac_offs;
258	258	UINT8* m_stisub_colorram;
259	259	UINT8 m_stisub_outc;
	260	DECLARE_WRITE8_MEMBER(subsino_tiles_offset_w);
	261	DECLARE_WRITE8_MEMBER(subsino_videoram_w);
	262	DECLARE_WRITE8_MEMBER(subsino_colorram_w);
	263	DECLARE_WRITE8_MEMBER(subsino_reel1_ram_w);
	264	DECLARE_WRITE8_MEMBER(subsino_reel2_ram_w);
	265	DECLARE_WRITE8_MEMBER(subsino_reel3_ram_w);
	266	DECLARE_WRITE8_MEMBER(subsino_out_a_w);
	267	DECLARE_WRITE8_MEMBER(subsino_out_b_w);
	268	DECLARE_READ8_MEMBER(flash_r);
	269	DECLARE_WRITE8_MEMBER(flash_w);
	270	DECLARE_READ8_MEMBER(hwcheck_r);
	271	DECLARE_WRITE8_MEMBER(subsino_out_c_w);
	272	DECLARE_WRITE8_MEMBER(colordac_w);
	273	DECLARE_WRITE8_MEMBER(stisub_out_c_w);
	274	DECLARE_WRITE8_MEMBER(reel_scrollattr_w);
	275	DECLARE_READ8_MEMBER(reel_scrollattr_r);
260	276	};
261	277
262	278
r14845	r14846
266	282	***************************************************************************/
267	283
268	284
269		static WRITE8_HANDLER( subsino_tiles_offset_w )
	285	WRITE8_MEMBER(subsino_state::subsino_tiles_offset_w)
270	286	{
271		subsino_state *state = space->machine().driver_data<subsino_state>();
272		state->m_tiles_offset = (data & 1) ? 0x1000: 0;
273		state->m_tmap->mark_tile_dirty(offset);
	287	m_tiles_offset = (data & 1) ? 0x1000: 0;
	288	m_tmap->mark_tile_dirty(offset);
274	289	//  popmessage("gfx %02x",data);
275	290	}
276	291
277		static WRITE8_HANDLER( subsino_videoram_w )
	292	WRITE8_MEMBER(subsino_state::subsino_videoram_w)
278	293	{
279		subsino_state *state = space->machine().driver_data<subsino_state>();
280		state->m_videoram[offset] = data;
281		state->m_tmap->mark_tile_dirty(offset);
	294	m_videoram[offset] = data;
	295	m_tmap->mark_tile_dirty(offset);
282	296	}
283	297
284		static WRITE8_HANDLER( subsino_colorram_w )
	298	WRITE8_MEMBER(subsino_state::subsino_colorram_w)
285	299	{
286		subsino_state *state = space->machine().driver_data<subsino_state>();
287		state->m_colorram[offset] = data;
288		state->m_tmap->mark_tile_dirty(offset);
	300	m_colorram[offset] = data;
	301	m_tmap->mark_tile_dirty(offset);
289	302	}
290	303
291	304	static TILE_GET_INFO( get_tile_info )
r14845	r14846
317	330
318	331
319	332
320		static WRITE8_HANDLER( subsino_reel1_ram_w )
	333	WRITE8_MEMBER(subsino_state::subsino_reel1_ram_w)
321	334	{
322		subsino_state *state = space->machine().driver_data<subsino_state>();
323		state->m_reel1_ram[offset] = data;
324		state->m_reel1_tilemap->mark_tile_dirty(offset);
	335	m_reel1_ram[offset] = data;
	336	m_reel1_tilemap->mark_tile_dirty(offset);
325	337	}
326	338
327	339	static TILE_GET_INFO( get_subsino_reel1_tile_info )
r14845	r14846
351	363	}
352	364
353	365
354		static WRITE8_HANDLER( subsino_reel2_ram_w )
	366	WRITE8_MEMBER(subsino_state::subsino_reel2_ram_w)
355	367	{
356		subsino_state *state = space->machine().driver_data<subsino_state>();
357		state->m_reel2_ram[offset] = data;
358		state->m_reel2_tilemap->mark_tile_dirty(offset);
	368	m_reel2_ram[offset] = data;
	369	m_reel2_tilemap->mark_tile_dirty(offset);
359	370	}
360	371
361	372	static TILE_GET_INFO( get_subsino_reel2_tile_info )
r14845	r14846
384	395	0);
385	396	}
386	397
387		static WRITE8_HANDLER( subsino_reel3_ram_w )
	398	WRITE8_MEMBER(subsino_state::subsino_reel3_ram_w)
388	399	{
389		subsino_state *state = space->machine().driver_data<subsino_state>();
390		state->m_reel3_ram[offset] = data;
391		state->m_reel3_tilemap->mark_tile_dirty(offset);
	400	m_reel3_ram[offset] = data;
	401	m_reel3_tilemap->mark_tile_dirty(offset);
392	402	}
393	403
394	404	static TILE_GET_INFO( get_subsino_reel3_tile_info )
r14845	r14846
584	594	*                          Lamps & other outputs.                          *
585	595	***************************************************************************/
586	596
587		static WRITE8_HANDLER( subsino_out_a_w )
	597	WRITE8_MEMBER(subsino_state::subsino_out_a_w)
588	598	{
589
590	599	/***** COIN PULSE: *****
591	600
592	601
r14845	r14846
625	634	output_set_lamp_value(14, (data >> 6) & 1);   /* Lamp 14 */
626	635	output_set_lamp_value(15, (data >> 7) & 1);   /* Lamp 15 */
627	636
628		coin_counter_w( space->machine(), 0, data & 0x01 );   /* coin / keyin */
629		coin_counter_w( space->machine(), 1, data & 0x02 );   /* keyin / coin */
630		coin_counter_w( space->machine(), 2, data & 0x10 );   /* keyout */
631		coin_counter_w( space->machine(), 3, data & 0x20 );   /* payout */
	637	coin_counter_w( machine(), 0, data & 0x01 );   /* coin / keyin */
	638	coin_counter_w( machine(), 1, data & 0x02 );   /* keyin / coin */
	639	coin_counter_w( machine(), 2, data & 0x10 );   /* keyout */
	640	coin_counter_w( machine(), 3, data & 0x20 );   /* payout */
632	641
633	642	//  popmessage("Out A %02x",data);
634	643
635	644	}
636	645
637		static WRITE8_HANDLER( subsino_out_b_w )
	646	WRITE8_MEMBER(subsino_state::subsino_out_b_w)
638	647	{
639	648	/***** LAMPS: *****
640	649
r14845	r14846
787	796	AM_RANGE( 0x0d005, 0x0d005 ) AM_READ_PORT( "INA" )
788	797	AM_RANGE( 0x0d006, 0x0d006 ) AM_READ_PORT( "INB" )
789	798
790		AM_RANGE( 0x0d009, 0x0d009 ) AM_WRITE_LEGACY(subsino_out_b_w )
791		AM_RANGE( 0x0d00a, 0x0d00a ) AM_WRITE_LEGACY(subsino_out_a_w )
	799	AM_RANGE( 0x0d009, 0x0d009 ) AM_WRITE(subsino_out_b_w )
	800	AM_RANGE( 0x0d00a, 0x0d00a ) AM_WRITE(subsino_out_a_w )
792	801
793	802	AM_RANGE( 0x0d00c, 0x0d00c ) AM_READ_PORT( "INC" )
794	803
r14845	r14846
796	805
797	806	AM_RANGE( 0x0d018, 0x0d018 ) AM_DEVWRITE("oki", okim6295_device, write)
798	807
799		AM_RANGE( 0x0d01b, 0x0d01b ) AM_WRITE_LEGACY(subsino_tiles_offset_w )
	808	AM_RANGE( 0x0d01b, 0x0d01b ) AM_WRITE(subsino_tiles_offset_w )
800	809
801		AM_RANGE( 0x0e000, 0x0e7ff ) AM_RAM_WRITE_LEGACY(subsino_colorram_w ) AM_BASE(m_colorram )
802		AM_RANGE( 0x0e800, 0x0efff ) AM_RAM_WRITE_LEGACY(subsino_videoram_w ) AM_BASE(m_videoram )
	810	AM_RANGE( 0x0e000, 0x0e7ff ) AM_RAM_WRITE(subsino_colorram_w ) AM_BASE(m_colorram )
	811	AM_RANGE( 0x0e800, 0x0efff ) AM_RAM_WRITE(subsino_videoram_w ) AM_BASE(m_videoram )
803	812	ADDRESS_MAP_END
804	813
805	814
r14845	r14846
814	823	AM_RANGE( 0x09005, 0x09005 ) AM_READ_PORT( "INA" )
815	824	AM_RANGE( 0x09006, 0x09006 ) AM_READ_PORT( "INB" )
816	825
817		AM_RANGE( 0x09009, 0x09009 ) AM_WRITE_LEGACY(subsino_out_b_w )
818		AM_RANGE( 0x0900a, 0x0900a ) AM_WRITE_LEGACY(subsino_out_a_w )
	826	AM_RANGE( 0x09009, 0x09009 ) AM_WRITE(subsino_out_b_w )
	827	AM_RANGE( 0x0900a, 0x0900a ) AM_WRITE(subsino_out_a_w )
819	828
820	829	AM_RANGE( 0x0900c, 0x0900c ) AM_READ_PORT( "INC" )
821	830
r14845	r14846
823	832
824	833	AM_RANGE( 0x09018, 0x09018 ) AM_DEVWRITE("oki", okim6295_device, write)
825	834
826		AM_RANGE( 0x0901b, 0x0901b ) AM_WRITE_LEGACY(subsino_tiles_offset_w )
	835	AM_RANGE( 0x0901b, 0x0901b ) AM_WRITE(subsino_tiles_offset_w )
827	836
828	837	AM_RANGE( 0x07800, 0x07fff ) AM_RAM
829		AM_RANGE( 0x08000, 0x087ff ) AM_RAM_WRITE_LEGACY(subsino_colorram_w ) AM_BASE(m_colorram )
830		AM_RANGE( 0x08800, 0x08fff ) AM_RAM_WRITE_LEGACY(subsino_videoram_w ) AM_BASE(m_videoram )
	838	AM_RANGE( 0x08000, 0x087ff ) AM_RAM_WRITE(subsino_colorram_w ) AM_BASE(m_colorram )
	839	AM_RANGE( 0x08800, 0x08fff ) AM_RAM_WRITE(subsino_videoram_w ) AM_BASE(m_videoram )
831	840
832	841	AM_RANGE( 0x00000, 0x13fff ) AM_ROM //overlap unmapped regions
833	842	ADDRESS_MAP_END
r14845	r14846
841	850	static ADDRESS_MAP_START( victor21_map, AS_PROGRAM, 8, subsino_state )
842	851	AM_RANGE( 0x09800, 0x09fff ) AM_RAM
843	852
844		AM_RANGE( 0x09000, 0x09000 ) AM_WRITE_LEGACY(subsino_out_a_w )
845		AM_RANGE( 0x09001, 0x09001 ) AM_WRITE_LEGACY(subsino_out_b_w )
	853	AM_RANGE( 0x09000, 0x09000 ) AM_WRITE(subsino_out_a_w )
	854	AM_RANGE( 0x09001, 0x09001 ) AM_WRITE(subsino_out_b_w )
846	855	AM_RANGE( 0x09002, 0x09002 ) AM_READ_PORT( "INC" )
847	856	AM_RANGE( 0x09004, 0x09004 ) AM_READ_PORT( "INA" )
848	857	AM_RANGE( 0x09005, 0x09005 ) AM_READ_PORT( "INB" )
r14845	r14846
857	866
858	867	AM_RANGE( 0x0900e, 0x0900f ) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w )
859	868
860		AM_RANGE( 0x0900d, 0x0900d ) AM_WRITE_LEGACY(subsino_tiles_offset_w )
	869	AM_RANGE( 0x0900d, 0x0900d ) AM_WRITE(subsino_tiles_offset_w )
861	870
862	871	AM_RANGE( 0x07800, 0x07fff ) AM_RAM
863		AM_RANGE( 0x08000, 0x087ff ) AM_RAM_WRITE_LEGACY(subsino_videoram_w ) AM_BASE(m_videoram )
864		AM_RANGE( 0x08800, 0x08fff ) AM_RAM_WRITE_LEGACY(subsino_colorram_w ) AM_BASE(m_colorram )
	872	AM_RANGE( 0x08000, 0x087ff ) AM_RAM_WRITE(subsino_videoram_w ) AM_BASE(m_videoram )
	873	AM_RANGE( 0x08800, 0x08fff ) AM_RAM_WRITE(subsino_colorram_w ) AM_BASE(m_colorram )
865	874
866	875	AM_RANGE( 0x00000, 0x08fff ) AM_ROM //overlap unmapped regions
867	876	AM_RANGE( 0x10000, 0x13fff ) AM_ROM
r14845	r14846
886	895	*/
887	896
888	897
889		static READ8_HANDLER( flash_r )
	898	READ8_MEMBER(subsino_state::flash_r)
890	899	{
891		subsino_state *state = space->machine().driver_data<subsino_state>();
892		//  printf("R %02x\n",state->m_flash_val);
	900	//  printf("R %02x\n",m_flash_val);
893	901
894		if(state->m_flash_val == 0xff)
	902	if(m_flash_val == 0xff)
895	903	return 0xd9;
896		else if(state->m_flash_val <= 0xa)
897		return state->m_flash_val;
898		else if(state->m_flash_val == 0x92)
	904	else if(m_flash_val <= 0xa)
	905	return m_flash_val;
	906	else if(m_flash_val == 0x92)
899	907	return 0xeb; //protected GFXs in Cross Bingo
900	908	else
901	909	return 0xd9;
902	910	}
903	911
904		static WRITE8_HANDLER( flash_w )
	912	WRITE8_MEMBER(subsino_state::flash_w)
905	913	{
906		subsino_state *state = space->machine().driver_data<subsino_state>();
907		switch(state->m_flash_packet_start)
	914	switch(m_flash_packet_start)
908	915	{
909	916	case 0:
910		state->m_flash_packet = data;
911		if((state->m_flash_packet & 0xf8) == 0xd0)
912		state->m_flash_packet_start = 1; //start of packet
	917	m_flash_packet = data;
	918	if((m_flash_packet & 0xf8) == 0xd0)
	919	m_flash_packet_start = 1; //start of packet
913	920	break;
914	921	case 1:
915		state->m_flash_packet = data;
916		if((state->m_flash_packet & 0xf8) == 0xe0)
917		state->m_flash_packet_start = 0; //end of packet
	922	m_flash_packet = data;
	923	if((m_flash_packet & 0xf8) == 0xe0)
	924	m_flash_packet_start = 0; //end of packet
918	925	else
919		state->m_flash_val = data;
	926	m_flash_val = data;
920	927	break;
921	928	}
922	929	}
923	930
924	931	static ADDRESS_MAP_START( victor5_map, AS_PROGRAM, 8, subsino_state )
925	932	AM_IMPORT_FROM( victor21_map )
926		AM_RANGE( 0x0900a, 0x0900a ) AM_READWRITE_LEGACY(flash_r, flash_w )
	933	AM_RANGE( 0x0900a, 0x0900a ) AM_READWRITE(flash_r, flash_w )
927	934	AM_RANGE( 0x0900b, 0x0900b ) AM_READNOP //"flash" status, bit 0
928	935	ADDRESS_MAP_END
929	936
930	937
931		static READ8_HANDLER( hwcheck_r )
	938	READ8_MEMBER(subsino_state::hwcheck_r)
932	939	{
933	940	/* Wants this at POST otherwise an "Hardware Error" occurs. */
934	941	return 0x55;
r14845	r14846
942	949	AM_RANGE( 0x09002, 0x09002 ) AM_READ_PORT( "INA" )
943	950	AM_RANGE( 0x09003, 0x09003 ) AM_READ_PORT( "INB" )
944	951	AM_RANGE( 0x09004, 0x09004 ) AM_READ_PORT( "INC" )
945		AM_RANGE( 0x09005, 0x09005 ) AM_WRITE_LEGACY(subsino_out_a_w )
	952	AM_RANGE( 0x09005, 0x09005 ) AM_WRITE(subsino_out_a_w )
946	953
947	954	AM_RANGE( 0x09008, 0x09008 ) AM_READ_PORT( "SW4" )
948		AM_RANGE( 0x09009, 0x09009 ) AM_READ_PORT( "SW3" )   // AM_WRITE_LEGACY(subsino_out_a_w )
949		AM_RANGE( 0x0900a, 0x0900a ) AM_READWRITE_LEGACY(hwcheck_r, subsino_out_b_w )
	955	AM_RANGE( 0x09009, 0x09009 ) AM_READ_PORT( "SW3" )   // AM_WRITE(subsino_out_a_w )
	956	AM_RANGE( 0x0900a, 0x0900a ) AM_READWRITE(hwcheck_r, subsino_out_b_w )
950	957
951		AM_RANGE( 0x09010, 0x09010 ) AM_READWRITE_LEGACY(flash_r, flash_w )
	958	AM_RANGE( 0x09010, 0x09010 ) AM_READWRITE(flash_r, flash_w )
952	959	//  AM_RANGE( 0x09011, 0x09011 ) //"flash" status, bit 0
953	960	//  AM_RANGE( 0x0900c, 0x0900c ) AM_READ_PORT( "INC" )
954	961	AM_RANGE( 0x0900c, 0x0900d ) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w )
955	962
956	963	//  AM_RANGE( 0x09018, 0x09018 ) AM_DEVWRITE("oki", okim6295_device, write)
957	964
958		//  AM_RANGE( 0x0900d, 0x0900d ) AM_WRITE_LEGACY(subsino_tiles_offset_w )
	965	//  AM_RANGE( 0x0900d, 0x0900d ) AM_WRITE(subsino_tiles_offset_w )
959	966
960	967	AM_RANGE( 0x07800, 0x07fff ) AM_RAM
961		AM_RANGE( 0x08000, 0x087ff ) AM_RAM_WRITE_LEGACY(subsino_videoram_w ) AM_BASE(m_videoram )
962		AM_RANGE( 0x08800, 0x08fff ) AM_RAM_WRITE_LEGACY(subsino_colorram_w ) AM_BASE(m_colorram )
	968	AM_RANGE( 0x08000, 0x087ff ) AM_RAM_WRITE(subsino_videoram_w ) AM_BASE(m_videoram )
	969	AM_RANGE( 0x08800, 0x08fff ) AM_RAM_WRITE(subsino_colorram_w ) AM_BASE(m_colorram )
963	970
964	971	AM_RANGE( 0x00000, 0x8fff ) AM_ROM //overlap unmapped regions
965	972
r14845	r14846
967	974
968	975	ADDRESS_MAP_END
969	976
970		static WRITE8_HANDLER( subsino_out_c_w )
	977	WRITE8_MEMBER(subsino_state::subsino_out_c_w)
971	978	{
972		subsino_state *state = space->machine().driver_data<subsino_state>();
973	979	// not 100% sure on this
974	980
975	981	// ???? eccc
976	982	// e = enable reels?
977	983	// c = reel colour bank?
978		state->m_out_c = data;
	984	m_out_c = data;
979	985
980		state->m_reel1_tilemap->mark_all_dirty();
981		state->m_reel2_tilemap->mark_all_dirty();
982		state->m_reel3_tilemap->mark_all_dirty();
	986	m_reel1_tilemap->mark_all_dirty();
	987	m_reel2_tilemap->mark_all_dirty();
	988	m_reel3_tilemap->mark_all_dirty();
983	989	//  popmessage("data %02x\n",data);
984	990	}
985	991
r14845	r14846
995	1001	AM_RANGE( 0x09006, 0x09006 ) AM_READ_PORT( "INB" )
996	1002
997	1003	/* 0x09008: is marked as OUTPUT C in the test mode. */
998		AM_RANGE( 0x09008, 0x09008 ) AM_WRITE_LEGACY(subsino_out_c_w )
999		AM_RANGE( 0x09009, 0x09009 ) AM_WRITE_LEGACY(subsino_out_b_w )
1000		AM_RANGE( 0x0900a, 0x0900a ) AM_WRITE_LEGACY(subsino_out_a_w )
	1004	AM_RANGE( 0x09008, 0x09008 ) AM_WRITE(subsino_out_c_w )
	1005	AM_RANGE( 0x09009, 0x09009 ) AM_WRITE(subsino_out_b_w )
	1006	AM_RANGE( 0x0900a, 0x0900a ) AM_WRITE(subsino_out_a_w )
1001	1007
1002	1008	AM_RANGE( 0x0900c, 0x0900c ) AM_READ_PORT( "INC" )
1003	1009
r14845	r14846
1005	1011
1006	1012	//  AM_RANGE( 0x0900c, 0x0900c ) AM_DEVWRITE("oki", okim6295_device, write)
1007	1013
1008		AM_RANGE( 0x0901b, 0x0901b ) AM_WRITE_LEGACY(subsino_tiles_offset_w )
	1014	AM_RANGE( 0x0901b, 0x0901b ) AM_WRITE(subsino_tiles_offset_w )
1009	1015
1010	1016	AM_RANGE( 0x07800, 0x07fff ) AM_RAM
1011		AM_RANGE( 0x08800, 0x08fff ) AM_RAM_WRITE_LEGACY(subsino_videoram_w ) AM_BASE(m_videoram )
1012		AM_RANGE( 0x08000, 0x087ff ) AM_RAM_WRITE_LEGACY(subsino_colorram_w ) AM_BASE(m_colorram )
	1017	AM_RANGE( 0x08800, 0x08fff ) AM_RAM_WRITE(subsino_videoram_w ) AM_BASE(m_videoram )
	1018	AM_RANGE( 0x08000, 0x087ff ) AM_RAM_WRITE(subsino_colorram_w ) AM_BASE(m_colorram )
1013	1019
1014	1020	AM_RANGE( 0x00000, 0x0bfff ) AM_ROM // overlap unmapped regions
1015	1021	AM_RANGE( 0x10000, 0x13fff ) AM_ROM
r14845	r14846
1019	1025	AM_RANGE( 0x15140, 0x1517f ) AM_RAM AM_BASE(m_reel2_scroll)
1020	1026	AM_RANGE( 0x15180, 0x151bf ) AM_RAM AM_BASE(m_reel1_scroll)
1021	1027
1022		AM_RANGE( 0x15800, 0x159ff ) AM_RAM_WRITE_LEGACY(subsino_reel1_ram_w) AM_BASE(m_reel1_ram)
1023		AM_RANGE( 0x15a00, 0x15bff ) AM_RAM_WRITE_LEGACY(subsino_reel2_ram_w) AM_BASE(m_reel2_ram)
1024		AM_RANGE( 0x15c00, 0x15dff ) AM_RAM_WRITE_LEGACY(subsino_reel3_ram_w) AM_BASE(m_reel3_ram)
	1028	AM_RANGE( 0x15800, 0x159ff ) AM_RAM_WRITE(subsino_reel1_ram_w) AM_BASE(m_reel1_ram)
	1029	AM_RANGE( 0x15a00, 0x15bff ) AM_RAM_WRITE(subsino_reel2_ram_w) AM_BASE(m_reel2_ram)
	1030	AM_RANGE( 0x15c00, 0x15dff ) AM_RAM_WRITE(subsino_reel3_ram_w) AM_BASE(m_reel3_ram)
1025	1031	ADDRESS_MAP_END
1026	1032
1027	1033
1028		static WRITE8_HANDLER(colordac_w)
	1034	WRITE8_MEMBER(subsino_state::colordac_w)
1029	1035	{
1030		subsino_state *state = space->machine().driver_data<subsino_state>();
1031	1036	switch ( offset )
1032	1037	{
1033	1038	case 0:
1034		state->m_colordac_offs = data * 3;
	1039	m_colordac_offs = data * 3;
1035	1040	break;
1036	1041
1037	1042	case 1:
1038		state->m_stisub_colorram[state->m_colordac_offs] = data;
1039		palette_set_color_rgb(space->machine(), state->m_colordac_offs/3,
1040		pal6bit(state->m_stisub_colorram[(state->m_colordac_offs/3)*3+0]),
1041		pal6bit(state->m_stisub_colorram[(state->m_colordac_offs/3)*3+1]),
1042		pal6bit(state->m_stisub_colorram[(state->m_colordac_offs/3)*3+2])
	1043	m_stisub_colorram[m_colordac_offs] = data;
	1044	palette_set_color_rgb(machine(), m_colordac_offs/3,
	1045	pal6bit(m_stisub_colorram[(m_colordac_offs/3)*3+0]),
	1046	pal6bit(m_stisub_colorram[(m_colordac_offs/3)*3+1]),
	1047	pal6bit(m_stisub_colorram[(m_colordac_offs/3)*3+2])
1043	1048	);
1044		state->m_colordac_offs = (state->m_colordac_offs+1) % (256*3);
	1049	m_colordac_offs = (m_colordac_offs+1) % (256*3);
1045	1050	break;
1046	1051
1047	1052	case 2:
r14845	r14846
1054	1059	}
1055	1060
1056	1061
1057		static WRITE8_HANDLER( stisub_out_c_w )
	1062	WRITE8_MEMBER(subsino_state::stisub_out_c_w)
1058	1063	{
1059		subsino_state *state = space->machine().driver_data<subsino_state>();
1060		state->m_stisub_outc = data;
	1064	m_stisub_outc = data;
1061	1065
1062	1066	}
1063	1067
1064	1068	// this stuff is banked..
1065	1069	// not 100% sure on the bank bits.. other bits are also set
1066		static WRITE8_HANDLER( reel_scrollattr_w )
	1070	WRITE8_MEMBER(subsino_state::reel_scrollattr_w)
1067	1071	{
1068		subsino_state *state = space->machine().driver_data<subsino_state>();
1069		if (state->m_stisub_outc&0x20)
	1072	if (m_stisub_outc&0x20)
1070	1073	{
1071	1074	if (offset<0x200)
1072	1075	{
1073		state->m_reel1_attr[offset&0x1ff] = data;
	1076	m_reel1_attr[offset&0x1ff] = data;
1074	1077	}
1075	1078	else if (offset<0x400)
1076	1079	{
1077		state->m_reel2_attr[offset&0x1ff] = data;
	1080	m_reel2_attr[offset&0x1ff] = data;
1078	1081	}
1079	1082	else if (offset<0x600)
1080	1083	{
1081		state->m_reel3_attr[offset&0x1ff] = data;
	1084	m_reel3_attr[offset&0x1ff] = data;
1082	1085	}
1083	1086	else
1084	1087	{
r14845	r14846
1095	1098	}
1096	1099	else if (offset<0x80)
1097	1100	{
1098		state->m_reel2_scroll[offset&0x3f] = data;
	1101	m_reel2_scroll[offset&0x3f] = data;
1099	1102	}
1100	1103	else if (offset<0xc0)
1101	1104	{
1102		state->m_reel1_scroll[offset&0x3f] = data;
	1105	m_reel1_scroll[offset&0x3f] = data;
1103	1106	}
1104	1107	else
1105	1108	{
1106		state->m_reel3_scroll[offset&0x3f] = data;
	1109	m_reel3_scroll[offset&0x3f] = data;
1107	1110	}
1108	1111	}
1109	1112	}
1110	1113
1111		static READ8_HANDLER( reel_scrollattr_r )
	1114	READ8_MEMBER(subsino_state::reel_scrollattr_r)
1112	1115	{
1113		subsino_state *state = space->machine().driver_data<subsino_state>();
1114		return state->m_reel1_attr[offset];
	1116	return m_reel1_attr[offset];
1115	1117	}
1116	1118
1117	1119	static ADDRESS_MAP_START( stisub_map, AS_PROGRAM, 8, subsino_state )
r14845	r14846
1127	1129	AM_RANGE( 0x0d005, 0x0d005 ) AM_READ_PORT( "INB" )
1128	1130	AM_RANGE( 0x0d006, 0x0d006 ) AM_READ_PORT( "INA" )
1129	1131
1130		AM_RANGE( 0x0d008, 0x0d008 ) AM_WRITE_LEGACY(stisub_out_c_w )
	1132	AM_RANGE( 0x0d008, 0x0d008 ) AM_WRITE(stisub_out_c_w )
1131	1133
1132		AM_RANGE( 0x0d009, 0x0d009 ) AM_WRITE_LEGACY(subsino_out_b_w )
1133		AM_RANGE( 0x0d00a, 0x0d00a ) AM_WRITE_LEGACY(subsino_out_a_w )
	1134	AM_RANGE( 0x0d009, 0x0d009 ) AM_WRITE(subsino_out_b_w )
	1135	AM_RANGE( 0x0d00a, 0x0d00a ) AM_WRITE(subsino_out_a_w )
1134	1136
1135	1137	AM_RANGE( 0x0d00c, 0x0d00c ) AM_READ_PORT( "INC" )
1136	1138
1137		AM_RANGE( 0x0d010, 0x0d013 ) AM_WRITE_LEGACY(colordac_w)
	1139	AM_RANGE( 0x0d010, 0x0d013 ) AM_WRITE(colordac_w)
1138	1140
1139	1141	AM_RANGE( 0x0d016, 0x0d017 ) AM_DEVWRITE_LEGACY("ymsnd", ym3812_w )
1140	1142
1141		//  AM_RANGE( 0x0d01b, 0x0d01b ) AM_WRITE_LEGACY(subsino_tiles_offset_w )
	1143	//  AM_RANGE( 0x0d01b, 0x0d01b ) AM_WRITE(subsino_tiles_offset_w )
1142	1144
1143		AM_RANGE( 0x0e000, 0x0e7ff ) AM_RAM_WRITE_LEGACY(subsino_colorram_w ) AM_BASE(m_colorram )
1144		AM_RANGE( 0x0e800, 0x0efff ) AM_RAM_WRITE_LEGACY(subsino_videoram_w ) AM_BASE(m_videoram )
	1145	AM_RANGE( 0x0e000, 0x0e7ff ) AM_RAM_WRITE(subsino_colorram_w ) AM_BASE(m_colorram )
	1146	AM_RANGE( 0x0e800, 0x0efff ) AM_RAM_WRITE(subsino_videoram_w ) AM_BASE(m_videoram )
1145	1147
1146		AM_RANGE( 0xf000, 0xf7ff ) AM_READWRITE_LEGACY(reel_scrollattr_r, reel_scrollattr_w)
	1148	AM_RANGE( 0xf000, 0xf7ff ) AM_READWRITE(reel_scrollattr_r, reel_scrollattr_w)
1147	1149
1148		AM_RANGE( 0xf800, 0xf9ff ) AM_RAM_WRITE_LEGACY(subsino_reel1_ram_w) AM_BASE(m_reel1_ram)
1149		AM_RANGE( 0xfa00, 0xfbff ) AM_RAM_WRITE_LEGACY(subsino_reel2_ram_w) AM_BASE(m_reel2_ram)
1150		AM_RANGE( 0xfc00, 0xfdff ) AM_RAM_WRITE_LEGACY(subsino_reel3_ram_w) AM_BASE(m_reel3_ram)
	1150	AM_RANGE( 0xf800, 0xf9ff ) AM_RAM_WRITE(subsino_reel1_ram_w) AM_BASE(m_reel1_ram)
	1151	AM_RANGE( 0xfa00, 0xfbff ) AM_RAM_WRITE(subsino_reel2_ram_w) AM_BASE(m_reel2_ram)
	1152	AM_RANGE( 0xfc00, 0xfdff ) AM_RAM_WRITE(subsino_reel3_ram_w) AM_BASE(m_reel3_ram)
1151	1153	ADDRESS_MAP_END
1152	1154
1153	1155
r14845	r14846
1173	1175	//  AM_RANGE( 0x0d00b, 0x0d00b ) AM_WRITE
1174	1176	AM_RANGE( 0x0d00c, 0x0d00c ) AM_READ_PORT( "INC" )
1175	1177
1176		AM_RANGE( 0x0d010, 0x0d013 ) AM_WRITE_LEGACY(colordac_w)
	1178	AM_RANGE( 0x0d010, 0x0d013 ) AM_WRITE(colordac_w)
1177	1179
1178	1180	//  AM_RANGE( 0x0d012, 0x0d012 ) AM_WRITE
1179	1181
r14845	r14846
1181	1183
1182	1184	//  AM_RANGE( 0x0d018, 0x0d018 ) AM_DEVREADWRITE("oki", okim6295_device, read, write)
1183	1185
1184		AM_RANGE( 0x0e000, 0x0e7ff ) AM_RAM_WRITE_LEGACY(subsino_colorram_w ) AM_BASE(m_colorram )
1185		AM_RANGE( 0x0e800, 0x0efff ) AM_RAM_WRITE_LEGACY(subsino_videoram_w ) AM_BASE(m_videoram )
	1186	AM_RANGE( 0x0e000, 0x0e7ff ) AM_RAM_WRITE(subsino_colorram_w ) AM_BASE(m_colorram )
	1187	AM_RANGE( 0x0e800, 0x0efff ) AM_RAM_WRITE(subsino_videoram_w ) AM_BASE(m_videoram )
1186	1188
1187		AM_RANGE( 0xf000, 0xf7ff ) AM_READWRITE_LEGACY(reel_scrollattr_r, reel_scrollattr_w)
	1189	AM_RANGE( 0xf000, 0xf7ff ) AM_READWRITE(reel_scrollattr_r, reel_scrollattr_w)
1188	1190
1189		AM_RANGE( 0xf800, 0xf9ff ) AM_RAM_WRITE_LEGACY(subsino_reel1_ram_w) AM_BASE(m_reel1_ram)
1190		AM_RANGE( 0xfa00, 0xfbff ) AM_RAM_WRITE_LEGACY(subsino_reel2_ram_w) AM_BASE(m_reel2_ram)
1191		AM_RANGE( 0xfc00, 0xfdff ) AM_RAM_WRITE_LEGACY(subsino_reel3_ram_w) AM_BASE(m_reel3_ram)
	1191	AM_RANGE( 0xf800, 0xf9ff ) AM_RAM_WRITE(subsino_reel1_ram_w) AM_BASE(m_reel1_ram)
	1192	AM_RANGE( 0xfa00, 0xfbff ) AM_RAM_WRITE(subsino_reel2_ram_w) AM_BASE(m_reel2_ram)
	1193	AM_RANGE( 0xfc00, 0xfdff ) AM_RAM_WRITE(subsino_reel3_ram_w) AM_BASE(m_reel3_ram)
1192	1194	ADDRESS_MAP_END
1193	1195
1194	1196

src/mame/drivers/mlanding.c

r14845	r14846
46	46	UINT16 m_dsp_HOLD_signal;
47	47	UINT8 *m_mecha_ram;
48	48	UINT8 m_trigger;
	49	DECLARE_WRITE16_MEMBER(ml_tileram_w);
	50	DECLARE_READ16_MEMBER(ml_tileram_r);
	51	DECLARE_READ16_MEMBER(io1_r);
	52	DECLARE_WRITE16_MEMBER(ml_output_w);
	53	DECLARE_WRITE16_MEMBER(ml_sub_reset_w);
	54	DECLARE_WRITE16_MEMBER(ml_to_sound_w);
	55	DECLARE_WRITE8_MEMBER(ml_sound_to_main_w);
	56	DECLARE_READ16_MEMBER(ml_analog1_lsb_r);
	57	DECLARE_READ16_MEMBER(ml_analog2_lsb_r);
	58	DECLARE_READ16_MEMBER(ml_analog3_lsb_r);
	59	DECLARE_READ16_MEMBER(ml_analog1_msb_r);
	60	DECLARE_READ16_MEMBER(ml_analog2_msb_r);
	61	DECLARE_READ16_MEMBER(ml_analog3_msb_r);
	62	DECLARE_WRITE16_MEMBER(ml_nmi_to_sound_w);
	63	DECLARE_READ16_MEMBER(ml_mecha_ram_r);
	64	DECLARE_WRITE16_MEMBER(ml_mecha_ram_w);
	65	DECLARE_WRITE8_MEMBER(ml_msm_start_msb_w);
	66	DECLARE_READ16_MEMBER(ml_dotram_r);
	67	DECLARE_WRITE16_MEMBER(ml_dotram_w);
	68	DECLARE_READ16_MEMBER(dsp_HOLD_signal_r);
	69	DECLARE_READ8_MEMBER(test_r);
49	70	};
50	71
51	72
r14845	r14846
200	221	return 1;
201	222	}
202	223
203		static WRITE16_HANDLER(ml_tileram_w)
	224	WRITE16_MEMBER(mlanding_state::ml_tileram_w)
204	225	{
205		mlanding_state *state = space->machine().driver_data<mlanding_state>();
206		COMBINE_DATA(&state->m_ml_tileram[offset]);
	226	COMBINE_DATA(&m_ml_tileram[offset]);
207	227	}
208	228
209		static READ16_HANDLER(ml_tileram_r)
	229	READ16_MEMBER(mlanding_state::ml_tileram_r)
210	230	{
211		mlanding_state *state = space->machine().driver_data<mlanding_state>();
212		return state->m_ml_tileram[offset];
	231	return m_ml_tileram[offset];
213	232	}
214	233
215	234
216		static READ16_HANDLER( io1_r ) //240006
	235	READ16_MEMBER(mlanding_state::io1_r)//240006
217	236	{
218		mlanding_state *state = space->machine().driver_data<mlanding_state>();
219	237	/*
220	238	fedcba9876543210
221	239	x  - mecha driver status
r14845	r14846
227	245	*/
228	246	// multiplexed? or just overriden?
229	247
230		int retval = (state->m_dma_active << 15) | (input_port_read(space->machine(), "DSW") & 0x7fff);
	248	int retval = (m_dma_active << 15) | (input_port_read(machine(), "DSW") & 0x7fff);
231	249	return retval;
232	250	}
233	251
234	252	/* output */
235		static WRITE16_HANDLER(ml_output_w)
	253	WRITE16_MEMBER(mlanding_state::ml_output_w)
236	254	{
237		mlanding_state *state = space->machine().driver_data<mlanding_state>();
238	255	/*
239	256	x--- ---- palette fg bankswitch
240	257	---x ---- coin lockout?
r14845	r14846
243	260	*/
244	261	//  popmessage("%04x",data);
245	262
246		state->m_pal_fg_bank = (data & 0x80)>>7;
	263	m_pal_fg_bank = (data & 0x80)>>7;
247	264	}
248	265
249	266	static WRITE8_DEVICE_HANDLER( sound_bankswitch_w )
r14845	r14846
292	309	}
293	310
294	311	/* TODO: this uses many bits */
295		static WRITE16_HANDLER( ml_sub_reset_w )
	312	WRITE16_MEMBER(mlanding_state::ml_sub_reset_w)
296	313	{
297		mlanding_state *state = space->machine().driver_data<mlanding_state>();
298	314	int pixels;
299	315
300	316	// Return the number of pixels drawn?
301		pixels = start_dma(space->machine());
	317	pixels = start_dma(machine());
302	318
303	319	if (pixels)
304	320	{
305		state->m_dma_active = 1;
306		space->machine().scheduler().timer_set(attotime::from_msec(20), FUNC(dma_complete));
	321	m_dma_active = 1;
	322	machine().scheduler().timer_set(attotime::from_msec(20), FUNC(dma_complete));
307	323	}
308	324
309	325	if(!(data & 0x40)) // unknown line used
310		cputag_set_input_line(space->machine(), "sub", INPUT_LINE_RESET, CLEAR_LINE);
	326	cputag_set_input_line(machine(), "sub", INPUT_LINE_RESET, CLEAR_LINE);
311	327
312	328	//data & 0x20 sound cpu?
313	329
314	330	if(!(data & 0x80)) // unknown line used
315	331	{
316		cputag_set_input_line(space->machine(), "dsp", INPUT_LINE_RESET, CLEAR_LINE);
317		state->m_dsp_HOLD_signal = data & 0x80;
	332	cputag_set_input_line(machine(), "dsp", INPUT_LINE_RESET, CLEAR_LINE);
	333	m_dsp_HOLD_signal = data & 0x80;
318	334	}
319	335	}
320	336
321		static WRITE16_HANDLER( ml_to_sound_w )
	337	WRITE16_MEMBER(mlanding_state::ml_to_sound_w)
322	338	{
323		device_t *tc0140syt = space->machine().device("tc0140syt");
	339	device_t *tc0140syt = machine().device("tc0140syt");
324	340	if (offset == 0)
325	341	tc0140syt_port_w(tc0140syt, 0, data & 0xff);
326	342	else if (offset == 1)
327	343	{
328		//cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_NMI, ASSERT_LINE);
	344	//cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_NMI, ASSERT_LINE);
329	345	tc0140syt_comm_w(tc0140syt, 0, data & 0xff);
330	346	}
331	347	}
332	348
333		static WRITE8_HANDLER( ml_sound_to_main_w )
	349	WRITE8_MEMBER(mlanding_state::ml_sound_to_main_w)
334	350	{
335		device_t *tc0140syt = space->machine().device("tc0140syt");
	351	device_t *tc0140syt = machine().device("tc0140syt");
336	352	if (offset == 0)
337	353	tc0140syt_slave_port_w(tc0140syt, 0, data & 0xff);
338	354	else if (offset == 1)
339	355	{
340		//cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_NMI, CLEAR_LINE);
	356	//cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_NMI, CLEAR_LINE);
341	357	tc0140syt_slave_comm_w(tc0140syt, 0, data & 0xff);
342	358	}
343	359	}
344	360
345		static READ16_HANDLER( ml_analog1_lsb_r )
	361	READ16_MEMBER(mlanding_state::ml_analog1_lsb_r)
346	362	{
347		return input_port_read(space->machine(), "STICKX") & 0xff;
	363	return input_port_read(machine(), "STICKX") & 0xff;
348	364	}
349	365
350		static READ16_HANDLER( ml_analog2_lsb_r )
	366	READ16_MEMBER(mlanding_state::ml_analog2_lsb_r)
351	367	{
352		return input_port_read(space->machine(), "STICKY") & 0xff;
	368	return input_port_read(machine(), "STICKY") & 0xff;
353	369	}
354	370
355		static READ16_HANDLER( ml_analog3_lsb_r )
	371	READ16_MEMBER(mlanding_state::ml_analog3_lsb_r)
356	372	{
357		return (input_port_read(space->machine(), "STICKZ") & 0xff);
	373	return (input_port_read(machine(), "STICKZ") & 0xff);
358	374	}
359	375
360	376	/*
r14845	r14846
378	394	*/
379	395
380	396	/* high bits of analog inputs + "limiters"/ADC converters. */
381		static READ16_HANDLER( ml_analog1_msb_r )
	397	READ16_MEMBER(mlanding_state::ml_analog1_msb_r)
382	398	{
383		return ((input_port_read(space->machine(), "STICKY") & 0xf00)>>8) | (input_port_read(space->machine(), "IN2") & 0xf0);
	399	return ((input_port_read(machine(), "STICKY") & 0xf00)>>8) | (input_port_read(machine(), "IN2") & 0xf0);
384	400	}
385	401
386		static READ16_HANDLER( ml_analog2_msb_r )
	402	READ16_MEMBER(mlanding_state::ml_analog2_msb_r)
387	403	{
388	404	UINT8 res;
389	405	UINT16 y_adc,x_adc;
390	406
391		y_adc = input_port_read(space->machine(), "STICKY");
392		x_adc = input_port_read(space->machine(), "STICKZ");
	407	y_adc = input_port_read(machine(), "STICKY");
	408	x_adc = input_port_read(machine(), "STICKZ");
393	409
394	410	res = 0;
395	411
r14845	r14846
405	421
406	422	//  popmessage("%04x %04x",x_adc,y_adc);
407	423
408		return ((input_port_read(space->machine(), "STICKZ") & 0xf00)>>8) | res;
	424	return ((input_port_read(machine(), "STICKZ") & 0xf00)>>8) | res;
409	425	}
410	426
411		static READ16_HANDLER( ml_analog3_msb_r )
	427	READ16_MEMBER(mlanding_state::ml_analog3_msb_r)
412	428	{
413	429	UINT8 z_adc,res;
414	430	UINT16 x_adc;
415	431
416		z_adc = input_port_read(space->machine(), "STICKX");
417		x_adc = input_port_read(space->machine(), "STICKZ");
	432	z_adc = input_port_read(machine(), "STICKX");
	433	x_adc = input_port_read(machine(), "STICKZ");
418	434
419	435	res = 0;
420	436
r14845	r14846
428	444	if(x_adc & 0x800 || x_adc == 0)
429	445	res|= 0x10;
430	446
431		return ((input_port_read(space->machine(), "STICKX") & 0xf00)>>8) | res;
	447	return ((input_port_read(machine(), "STICKX") & 0xf00)>>8) | res;
432	448	}
433	449
434		static WRITE16_HANDLER( ml_nmi_to_sound_w )
	450	WRITE16_MEMBER(mlanding_state::ml_nmi_to_sound_w)
435	451	{
436		//  cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_RESET, CLEAR_LINE);
	452	//  cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_RESET, CLEAR_LINE);
437	453	}
438	454
439		static READ16_HANDLER( ml_mecha_ram_r )
	455	READ16_MEMBER(mlanding_state::ml_mecha_ram_r)
440	456	{
441		mlanding_state *state = space->machine().driver_data<mlanding_state>();
442		return (state->m_mecha_ram[offset*2]<<8)|state->m_mecha_ram[offset*2+1];
	457	return (m_mecha_ram[offset*2]<<8)|m_mecha_ram[offset*2+1];
443	458	}
444	459
445		static WRITE16_HANDLER( ml_mecha_ram_w )
	460	WRITE16_MEMBER(mlanding_state::ml_mecha_ram_w)
446	461	{
447		mlanding_state *state = space->machine().driver_data<mlanding_state>();
448		COMBINE_DATA(state->m_mecha_ram+offset*2+1);
	462	COMBINE_DATA(m_mecha_ram+offset*2+1);
449	463	data >>= 8;
450	464	mem_mask >>= 8;
451		COMBINE_DATA(state->m_mecha_ram+offset*2);
	465	COMBINE_DATA(m_mecha_ram+offset*2);
452	466	}
453	467
454	468	static ADDRESS_MAP_START( mlanding_mem, AS_PROGRAM, 16, mlanding_state )
r14845	r14846
456	470	AM_RANGE(0x080000, 0x08ffff) AM_RAM
457	471
458	472	AM_RANGE(0x100000, 0x17ffff) AM_RAM AM_BASE(m_g_ram)// 512kB G RAM - enough here for double buffered 512x400x8 frame
459		AM_RANGE(0x180000, 0x1bffff) AM_READWRITE_LEGACY(ml_tileram_r, ml_tileram_w) AM_BASE(m_ml_tileram)
	473	AM_RANGE(0x180000, 0x1bffff) AM_READWRITE(ml_tileram_r, ml_tileram_w) AM_BASE(m_ml_tileram)
460	474	AM_RANGE(0x1c0000, 0x1c3fff) AM_RAM AM_SHARE("share2") AM_BASE(m_dma_ram)
461	475	AM_RANGE(0x1c4000, 0x1cffff) AM_RAM AM_SHARE("share1")
462	476
463		AM_RANGE(0x1d0000, 0x1d0001) AM_WRITE_LEGACY(ml_sub_reset_w)
464		AM_RANGE(0x1d0002, 0x1d0003) AM_WRITE_LEGACY(ml_nmi_to_sound_w) //sound reset ??
	477	AM_RANGE(0x1d0000, 0x1d0001) AM_WRITE(ml_sub_reset_w)
	478	AM_RANGE(0x1d0002, 0x1d0003) AM_WRITE(ml_nmi_to_sound_w) //sound reset ??
465	479
466		AM_RANGE(0x2d0000, 0x2d0003) AM_WRITE_LEGACY(ml_to_sound_w)
	480	AM_RANGE(0x2d0000, 0x2d0003) AM_WRITE(ml_to_sound_w)
467	481	AM_RANGE(0x2d0000, 0x2d0001) AM_READNOP
468	482	AM_RANGE(0x2d0002, 0x2d0003) AM_DEVREAD8_LEGACY("tc0140syt", tc0140syt_comm_r, 0x00ff)
469	483
470	484	AM_RANGE(0x200000, 0x20ffff) AM_RAM_WRITE_LEGACY(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)
471		AM_RANGE(0x280000, 0x2807ff) AM_READWRITE_LEGACY(ml_mecha_ram_r,ml_mecha_ram_w)
	485	AM_RANGE(0x280000, 0x2807ff) AM_READWRITE(ml_mecha_ram_r,ml_mecha_ram_w)
472	486
473	487	AM_RANGE(0x290000, 0x290001) AM_READ_PORT("IN1")
474	488	AM_RANGE(0x290002, 0x290003) AM_READ_PORT("IN0")
475	489
476	490	AM_RANGE(0x240004, 0x240005) AM_NOP //watchdog ??
477		AM_RANGE(0x240006, 0x240007) AM_READ_LEGACY(io1_r) // vblank ?
478		AM_RANGE(0x2a0000, 0x2a0001) AM_WRITE_LEGACY(ml_output_w)
	491	AM_RANGE(0x240006, 0x240007) AM_READ(io1_r) // vblank ?
	492	AM_RANGE(0x2a0000, 0x2a0001) AM_WRITE(ml_output_w)
479	493
480	494	/*  */
481		AM_RANGE(0x2b0000, 0x2b0001) AM_READ_LEGACY(ml_analog1_lsb_r)      //-40 .. 40 analog controls ?
482		AM_RANGE(0x2b0004, 0x2b0005) AM_READ_LEGACY(ml_analog2_lsb_r)      //-40 .. 40 analog controls ?
483		AM_RANGE(0x2b0006, 0x2b0007) AM_READ_LEGACY(ml_analog1_msb_r) // tested in service mode, dips?
484		AM_RANGE(0x2c0000, 0x2c0001) AM_READ_LEGACY(ml_analog3_lsb_r)      //-60 .. 60 analog controls ?
485		AM_RANGE(0x2c0002, 0x2c0003) AM_READ_LEGACY(ml_analog2_msb_r)
486		AM_RANGE(0x2b0002, 0x2b0003) AM_READ_LEGACY(ml_analog3_msb_r)      // IN2/IN3 could be switched
	495	AM_RANGE(0x2b0000, 0x2b0001) AM_READ(ml_analog1_lsb_r)      //-40 .. 40 analog controls ?
	496	AM_RANGE(0x2b0004, 0x2b0005) AM_READ(ml_analog2_lsb_r)      //-40 .. 40 analog controls ?
	497	AM_RANGE(0x2b0006, 0x2b0007) AM_READ(ml_analog1_msb_r) // tested in service mode, dips?
	498	AM_RANGE(0x2c0000, 0x2c0001) AM_READ(ml_analog3_lsb_r)      //-60 .. 60 analog controls ?
	499	AM_RANGE(0x2c0002, 0x2c0003) AM_READ(ml_analog2_msb_r)
	500	AM_RANGE(0x2b0002, 0x2b0003) AM_READ(ml_analog3_msb_r)      // IN2/IN3 could be switched
487	501	ADDRESS_MAP_END
488	502
489	503
r14845	r14846
507	521	state->m_adpcm_end = (state->m_adpcm_pos+0x800);
508	522	}
509	523
510		static WRITE8_HANDLER( ml_msm_start_msb_w )
	524	WRITE8_MEMBER(mlanding_state::ml_msm_start_msb_w)
511	525	{
512		mlanding_state *state = space->machine().driver_data<mlanding_state>();
513		state->m_adpcm_pos = (state->m_adpcm_pos & 0x00ff00) | ((data & 0x0f)<<16) | 0x20;
	526	m_adpcm_pos = (m_adpcm_pos & 0x00ff00) | ((data & 0x0f)<<16) | 0x20;
514	527	}
515	528
516	529	static ADDRESS_MAP_START( mlanding_z80_mem, AS_PROGRAM, 8, mlanding_state )
r14845	r14846
518	531	AM_RANGE(0x4000, 0x7fff) AM_ROMBANK("bank1")
519	532	AM_RANGE(0x8000, 0x8fff) AM_RAM
520	533	AM_RANGE(0x9000, 0x9001) AM_MIRROR(0x00fe) AM_DEVREADWRITE_LEGACY("ymsnd", ym2151_r, ym2151_w)
521		AM_RANGE(0xa000, 0xa001) AM_WRITE_LEGACY(ml_sound_to_main_w)
	534	AM_RANGE(0xa000, 0xa001) AM_WRITE(ml_sound_to_main_w)
522	535	AM_RANGE(0xa001, 0xa001) AM_DEVREAD_LEGACY("tc0140syt", tc0140syt_slave_comm_r)
523	536
524	537	//  AM_RANGE(0xb000, 0xb000) AM_WRITE_LEGACY(ml_msm5205_address_w) //guess
r14845	r14846
526	539	//  AM_RANGE(0xd000, 0xd000) AM_DEVWRITE_LEGACY("msm", ml_msm5205_stop_w)
527	540
528	541	AM_RANGE(0xf000, 0xf000) AM_DEVWRITE_LEGACY("msm",ml_msm_start_lsb_w)
529		AM_RANGE(0xf200, 0xf200) AM_WRITE_LEGACY(ml_msm_start_msb_w)
	542	AM_RANGE(0xf200, 0xf200) AM_WRITE(ml_msm_start_msb_w)
530	543	ADDRESS_MAP_END
531	544
532		static READ16_HANDLER( ml_dotram_r )
	545	READ16_MEMBER(mlanding_state::ml_dotram_r)
533	546	{
534		mlanding_state *state = space->machine().driver_data<mlanding_state>();
535		return state->m_ml_dotram[offset];
	547	return m_ml_dotram[offset];
536	548	}
537	549
538		static WRITE16_HANDLER( ml_dotram_w )
	550	WRITE16_MEMBER(mlanding_state::ml_dotram_w)
539	551	{
540		mlanding_state *state = space->machine().driver_data<mlanding_state>();
541		state->m_ml_dotram[offset] = data;
	552	m_ml_dotram[offset] = data;
542	553	}
543	554
544		static READ16_HANDLER( dsp_HOLD_signal_r )
	555	READ16_MEMBER(mlanding_state::dsp_HOLD_signal_r)
545	556	{
546		mlanding_state *state = space->machine().driver_data<mlanding_state>();
547		return state->m_dsp_HOLD_signal;
	557	return m_dsp_HOLD_signal;
548	558	}
549	559
550	560
551		static READ8_HANDLER( test_r )
	561	READ8_MEMBER(mlanding_state::test_r)
552	562	{
553		return space->machine().rand();
	563	return machine().rand();
554	564	}
555	565
556	566	//mecha driver ?
r14845	r14846
559	569	AM_RANGE(0x8000, 0x87ff) AM_RAM AM_BASE(m_mecha_ram)
560	570	AM_RANGE(0x8800, 0x8fff) AM_RAM
561	571
562		AM_RANGE(0x9000, 0x9001) AM_READ_LEGACY(test_r)
563		AM_RANGE(0x9800, 0x9803) AM_READ_LEGACY(test_r)
	572	AM_RANGE(0x9000, 0x9001) AM_READ(test_r)
	573	AM_RANGE(0x9800, 0x9803) AM_READ(test_r)
564	574	ADDRESS_MAP_END
565	575
566	576	static ADDRESS_MAP_START( DSP_map_program, AS_PROGRAM, 16, mlanding_state )
r14845	r14846
568	578	ADDRESS_MAP_END
569	579
570	580	static ADDRESS_MAP_START( DSP_map_data, AS_DATA, 16, mlanding_state )
571		AM_RANGE(0x0000, 0x1fff) AM_READWRITE_LEGACY(ml_dotram_r,ml_dotram_w)
	581	AM_RANGE(0x0000, 0x1fff) AM_READWRITE(ml_dotram_r,ml_dotram_w)
572	582	ADDRESS_MAP_END
573	583
574	584	static ADDRESS_MAP_START( DSP_map_io, AS_IO, 16, mlanding_state )
575		AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ_LEGACY(dsp_HOLD_signal_r)
	585	AM_RANGE(TMS32025_HOLD, TMS32025_HOLD) AM_READ(dsp_HOLD_signal_r)
576	586	//  AM_RANGE(TMS32025_HOLDA, TMS32025_HOLDA) AM_WRITE_LEGACY(dsp_HOLDA_signal_w)
577	587	ADDRESS_MAP_END
578	588

src/mame/drivers/neoprint.c

r14845	r14846
37	37	UINT8 m_audio_result;
38	38	UINT8 m_bank_val;
39	39	UINT8 m_vblank;
	40	DECLARE_READ16_MEMBER(neoprint_calendar_r);
	41	DECLARE_WRITE16_MEMBER(neoprint_calendar_w);
	42	DECLARE_READ8_MEMBER(neoprint_unk_r);
	43	DECLARE_READ16_MEMBER(neoprint_audio_result_r);
	44	DECLARE_WRITE8_MEMBER(audio_cpu_clear_nmi_w);
	45	DECLARE_WRITE16_MEMBER(audio_command_w);
	46	DECLARE_READ8_MEMBER(audio_command_r);
	47	DECLARE_WRITE8_MEMBER(audio_result_w);
	48	DECLARE_WRITE16_MEMBER(nprsp_palette_w);
	49	DECLARE_WRITE8_MEMBER(nprsp_bank_w);
	50	DECLARE_READ16_MEMBER(rom_window_r);
40	51	};
41	52
42	53
r14845	r14846
113	124	}
114	125
115	126
116		static READ16_HANDLER( neoprint_calendar_r )
	127	READ16_MEMBER(neoprint_state::neoprint_calendar_r)
117	128	{
118		//if(cpu_get_pc(&space->device()) != 0x4b38 )//&& cpu_get_pc(&space->device()) != 0x5f86 && cpu_get_pc(&space->device()) != 0x5f90)
119		//  printf("%08x\n",cpu_get_pc(&space->device()));
	129	//if(cpu_get_pc(&space.device()) != 0x4b38 )//&& cpu_get_pc(&space.device()) != 0x5f86 && cpu_get_pc(&space.device()) != 0x5f90)
	130	//  printf("%08x\n",cpu_get_pc(&space.device()));
120	131
121		return (upd4990a_databit_r(space->machine().device("upd4990a"), 0) << 15);
	132	return (upd4990a_databit_r(machine().device("upd4990a"), 0) << 15);
122	133	}
123	134
124		static WRITE16_HANDLER( neoprint_calendar_w )
	135	WRITE16_MEMBER(neoprint_state::neoprint_calendar_w)
125	136	{
126		upd4990a_control_16_w(space->machine().device("upd4990a"), 0, ((data >> 8) & 7), mem_mask);
	137	upd4990a_control_16_w(machine().device("upd4990a"), 0, ((data >> 8) & 7), mem_mask);
127	138	}
128	139
129		static READ8_HANDLER( neoprint_unk_r )
	140	READ8_MEMBER(neoprint_state::neoprint_unk_r)
130	141	{
131		neoprint_state *state = space->machine().driver_data<neoprint_state>();
132	142
133	143	/* ---x ---- tested in irq routine, odd/even field number? */
134	144	/* ---- xx-- one of these two must be high */
135	145	/* ---- --xx checked right before entering into attract mode, presumably printer/camera related */
136	146
137		state->m_vblank = (space->machine().primary_screen->frame_number() & 0x1) ? 0x10 : 0x00;
	147	m_vblank = (machine().primary_screen->frame_number() & 0x1) ? 0x10 : 0x00;
138	148
139		//if(cpu_get_pc(&space->device()) != 0x1504 && cpu_get_pc(&space->device()) != 0x5f86 && cpu_get_pc(&space->device()) != 0x5f90)
140		//  printf("%08x\n",cpu_get_pc(&space->device()));
	149	//if(cpu_get_pc(&space.device()) != 0x1504 && cpu_get_pc(&space.device()) != 0x5f86 && cpu_get_pc(&space.device()) != 0x5f90)
	150	//  printf("%08x\n",cpu_get_pc(&space.device()));
141	151
142		return state->m_vblank| 4 | 3;
	152	return m_vblank| 4 | 3;
143	153	}
144	154
145		static READ16_HANDLER( neoprint_audio_result_r )
	155	READ16_MEMBER(neoprint_state::neoprint_audio_result_r)
146	156	{
147		neoprint_state *state = space->machine().driver_data<neoprint_state>();
148		return (state->m_audio_result << 8) | 0x00;
	157	return (m_audio_result << 8) | 0x00;
149	158	}
150	159
151	160	static void audio_cpu_assert_nmi(running_machine &machine)
r14845	r14846
154	163	}
155	164
156	165
157		static WRITE8_HANDLER( audio_cpu_clear_nmi_w )
	166	WRITE8_MEMBER(neoprint_state::audio_cpu_clear_nmi_w)
158	167	{
159		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_NMI, CLEAR_LINE);
	168	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_NMI, CLEAR_LINE);
160	169	}
161	170
162		static WRITE16_HANDLER( audio_command_w )
	171	WRITE16_MEMBER(neoprint_state::audio_command_w)
163	172	{
164	173	/* accessing the LSB only is not mapped */
165	174	if (mem_mask != 0x00ff)
166	175	{
167	176	soundlatch_w(space, 0, data >> 8);
168	177
169		audio_cpu_assert_nmi(space->machine());
	178	audio_cpu_assert_nmi(machine());
170	179
171	180	/* boost the interleave to let the audio CPU read the command */
172		space->machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(50));
	181	machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(50));
173	182
174		//if (LOG_CPU_COMM) logerror("MAIN CPU PC %06x: audio_command_w %04x - %04x\n", cpu_get_pc(&space->device()), data, mem_mask);
	183	//if (LOG_CPU_COMM) logerror("MAIN CPU PC %06x: audio_command_w %04x - %04x\n", cpu_get_pc(&space.device()), data, mem_mask);
175	184	}
176	185	}
177	186
178	187
179		static READ8_HANDLER( audio_command_r )
	188	READ8_MEMBER(neoprint_state::audio_command_r)
180	189	{
181	190	UINT8 ret = soundlatch_r(space, 0);
182	191
183		//if (LOG_CPU_COMM) logerror(" AUD CPU PC   %04x: audio_command_r %02x\n", cpu_get_pc(&space->device()), ret);
	192	//if (LOG_CPU_COMM) logerror(" AUD CPU PC   %04x: audio_command_r %02x\n", cpu_get_pc(&space.device()), ret);
184	193
185	194	/* this is a guess */
186	195	audio_cpu_clear_nmi_w(space, 0, 0);
r14845	r14846
190	199
191	200
192	201
193		static WRITE8_HANDLER( audio_result_w )
	202	WRITE8_MEMBER(neoprint_state::audio_result_w)
194	203	{
195		neoprint_state *state = space->machine().driver_data<neoprint_state>();
196		//neogeo_state *state = space->machine().driver_data<neogeo_state>();
197	204
198		//if (LOG_CPU_COMM && (state->m_audio_result != data)) logerror(" AUD CPU PC   %04x: audio_result_w %02x\n", cpu_get_pc(&space->device()), data);
199	205
200		state->m_audio_result = data;
	206	//if (LOG_CPU_COMM && (m_audio_result != data)) logerror(" AUD CPU PC   %04x: audio_result_w %02x\n", cpu_get_pc(&space.device()), data);
	207
	208	m_audio_result = data;
201	209	}
202	210
203	211	static ADDRESS_MAP_START( neoprint_map, AS_PROGRAM, 16, neoprint_state )
r14845	r14846
207	215	AM_RANGE(0x300000, 0x30ffff) AM_RAM AM_SHARE("nvram")
208	216	AM_RANGE(0x400000, 0x43ffff) AM_RAM AM_BASE(m_npvidram)
209	217	AM_RANGE(0x500000, 0x51ffff) AM_RAM_WRITE_LEGACY(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)
210		AM_RANGE(0x600000, 0x600001) AM_READWRITE_LEGACY(neoprint_audio_result_r,audio_command_w)
211		AM_RANGE(0x600002, 0x600003) AM_READWRITE_LEGACY(neoprint_calendar_r,neoprint_calendar_w)
	218	AM_RANGE(0x600000, 0x600001) AM_READWRITE(neoprint_audio_result_r,audio_command_w)
	219	AM_RANGE(0x600002, 0x600003) AM_READWRITE(neoprint_calendar_r,neoprint_calendar_w)
212	220	AM_RANGE(0x600004, 0x600005) AM_READ_PORT("SYSTEM") AM_WRITENOP
213	221	AM_RANGE(0x600006, 0x600007) AM_READ_PORT("IN") AM_WRITENOP
214	222	AM_RANGE(0x600008, 0x600009) AM_READ_PORT("DSW1")
215		AM_RANGE(0x60000a, 0x60000b) AM_READ8_LEGACY(neoprint_unk_r,0xff00)
	223	AM_RANGE(0x60000a, 0x60000b) AM_READ8(neoprint_unk_r,0xff00)
216	224	AM_RANGE(0x60000c, 0x60000d) AM_READ_PORT("DSW2")
217	225	AM_RANGE(0x60000e, 0x60000f) AM_WRITENOP
218	226
r14845	r14846
221	229	AM_RANGE(0x70001e, 0x70001f) AM_WRITENOP //watchdog
222	230	ADDRESS_MAP_END
223	231
224		static WRITE16_HANDLER( nprsp_palette_w )
	232	WRITE16_MEMBER(neoprint_state::nprsp_palette_w)
225	233	{
226	234	UINT8 r,g,b,i;
227	235
228		COMBINE_DATA(&space->machine().generic.paletteram.u16[offset]);
	236	COMBINE_DATA(&machine().generic.paletteram.u16[offset]);
229	237
230		g = (space->machine().generic.paletteram.u16[offset & ~1] & 0xf800) >> 8;
231		r = (space->machine().generic.paletteram.u16[offset & ~1] & 0x00f8) >> 0;
232		i = (space->machine().generic.paletteram.u16[offset | 1] & 0x1c00) >> 10;
233		b = (space->machine().generic.paletteram.u16[offset | 1] & 0x00f8) >> 0;
	238	g = (machine().generic.paletteram.u16[offset & ~1] & 0xf800) >> 8;
	239	r = (machine().generic.paletteram.u16[offset & ~1] & 0x00f8) >> 0;
	240	i = (machine().generic.paletteram.u16[offset | 1] & 0x1c00) >> 10;
	241	b = (machine().generic.paletteram.u16[offset | 1] & 0x00f8) >> 0;
234	242	r |= i;
235	243	g |= i;
236	244	b |= i;
r14845	r14846
244	252
245	253	pal_entry = ((offset & 0xfffe) >> 1) + ((offset & 0x20000) ? 0x8000 : 0);
246	254
247		palette_set_color(space->machine(), pal_entry, MAKE_RGB(r,g,b));
	255	palette_set_color(machine(), pal_entry, MAKE_RGB(r,g,b));
248	256	}
249	257	}
250	258
251		static WRITE8_HANDLER( nprsp_bank_w )
	259	WRITE8_MEMBER(neoprint_state::nprsp_bank_w)
252	260	{
253		neoprint_state *state = space->machine().driver_data<neoprint_state>();
254	261	/* this register seems flip-flop based ... */
255	262
256	263	if((data & 0xf0) == 0x20)
257	264	{
258	265	if((data & 0xf) == 0x1)
259		state->m_bank_val = 1;
	266	m_bank_val = 1;
260	267	if((data & 0xf) == 0x2)
261		state->m_bank_val = 0;
	268	m_bank_val = 0;
262	269	}
263	270	}
264	271
265		static READ16_HANDLER( rom_window_r )
	272	READ16_MEMBER(neoprint_state::rom_window_r)
266	273	{
267		neoprint_state *state = space->machine().driver_data<neoprint_state>();
268		UINT16 *rom = (UINT16 *)space->machine().region("maincpu")->base();
	274	UINT16 *rom = (UINT16 *)machine().region("maincpu")->base();
269	275
270		return rom[offset | 0x80000/2 | state->m_bank_val*0x40000/2];
	276	return rom[offset | 0x80000/2 | m_bank_val*0x40000/2];
271	277	}
272	278
273	279	static ADDRESS_MAP_START( nprsp_map, AS_PROGRAM, 16, neoprint_state )
274	280	AM_RANGE(0x000000, 0x07ffff) AM_ROM
275		AM_RANGE(0x080000, 0x0fffff) AM_READ_LEGACY(rom_window_r)
276		AM_RANGE(0x200000, 0x200001) AM_READWRITE_LEGACY(neoprint_audio_result_r,audio_command_w)
277		AM_RANGE(0x200002, 0x200003) AM_READWRITE_LEGACY(neoprint_calendar_r,neoprint_calendar_w)
	281	AM_RANGE(0x080000, 0x0fffff) AM_READ(rom_window_r)
	282	AM_RANGE(0x200000, 0x200001) AM_READWRITE(neoprint_audio_result_r,audio_command_w)
	283	AM_RANGE(0x200002, 0x200003) AM_READWRITE(neoprint_calendar_r,neoprint_calendar_w)
278	284	AM_RANGE(0x200004, 0x200005) AM_READ_PORT("SYSTEM") AM_WRITENOP
279	285	AM_RANGE(0x200006, 0x200007) AM_READ_PORT("IN") AM_WRITENOP
280		AM_RANGE(0x200008, 0x200009) AM_READ_PORT("DSW1") AM_WRITE8_LEGACY(nprsp_bank_w,0xff00)
281		AM_RANGE(0x20000a, 0x20000b) AM_READ8_LEGACY(neoprint_unk_r,0xff00)
	286	AM_RANGE(0x200008, 0x200009) AM_READ_PORT("DSW1") AM_WRITE8(nprsp_bank_w,0xff00)
	287	AM_RANGE(0x20000a, 0x20000b) AM_READ8(neoprint_unk_r,0xff00)
282	288	AM_RANGE(0x20000c, 0x20000d) AM_READ_PORT("DSW2")
283	289	AM_RANGE(0x20000e, 0x20000f) AM_WRITENOP
284	290
r14845	r14846
288	294	AM_RANGE(0x300000, 0x33ffff) AM_RAM AM_SHARE("nvram")
289	295	AM_RANGE(0x380000, 0x38ffff) AM_RAM
290	296	AM_RANGE(0x400000, 0x43ffff) AM_RAM AM_BASE(m_npvidram)
291		AM_RANGE(0x500000, 0x57ffff) AM_RAM_WRITE_LEGACY(nprsp_palette_w) AM_BASE_GENERIC(paletteram)
	297	AM_RANGE(0x500000, 0x57ffff) AM_RAM_WRITE(nprsp_palette_w) AM_BASE_GENERIC(paletteram)
292	298	ADDRESS_MAP_END
293	299
294	300	/*************************************
r14845	r14846
315	321	*************************************/
316	322
317	323	static ADDRESS_MAP_START( neoprint_audio_io_map, AS_IO, 8, neoprint_state )
318		/*AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READWRITE_LEGACY(audio_command_r, audio_cpu_clear_nmi_w);*/  /* may not and NMI clear */
319		AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READ_LEGACY(audio_command_r) AM_WRITENOP
	324	/*AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READWRITE(audio_command_r, audio_cpu_clear_nmi_w);*/  /* may not and NMI clear */
	325	AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READ(audio_command_r) AM_WRITENOP
320	326	AM_RANGE(0x04, 0x07) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY("ymsnd", ym2610_r, ym2610_w)
321	327	//  AM_RANGE(0x08, 0x08) AM_MIRROR(0xff00) /* write - NMI enable / acknowledge? (the data written doesn't matter) */
322	328	//  AM_RANGE(0x08, 0x08) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ_LEGACY(audio_cpu_bank_select_f000_f7ff_r)
323	329	//  AM_RANGE(0x09, 0x09) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ_LEGACY(audio_cpu_bank_select_e000_efff_r)
324	330	//  AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ_LEGACY(audio_cpu_bank_select_c000_dfff_r)
325	331	//  AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ_LEGACY(audio_cpu_bank_select_8000_bfff_r)
326		AM_RANGE(0x0c, 0x0c) AM_MIRROR(0xff00) AM_WRITE_LEGACY(audio_result_w)
	332	AM_RANGE(0x0c, 0x0c) AM_MIRROR(0xff00) AM_WRITE(audio_result_w)
327	333	//  AM_RANGE(0x18, 0x18) AM_MIRROR(0xff00) /* write - NMI disable? (the data written doesn't matter) */
328	334	ADDRESS_MAP_END
329	335

src/mame/drivers/tmaster.c

r14845	r14846
145	145
146	146	required_device<cpu_device> m_maincpu;
147	147	optional_device<microtouch_device> m_microtouch;
	148	DECLARE_READ16_MEMBER(rtc_r);
	149	DECLARE_WRITE16_MEMBER(rtc_w);
	150	DECLARE_WRITE16_MEMBER(tmaster_color_w);
	151	DECLARE_WRITE16_MEMBER(tmaster_addr_w);
	152	DECLARE_WRITE16_MEMBER(tmaster_blitter_w);
	153	DECLARE_READ16_MEMBER(tmaster_blitter_r);
	154	DECLARE_READ16_MEMBER(tmaster_coins_r);
	155	DECLARE_READ16_MEMBER(galgames_eeprom_r);
	156	DECLARE_WRITE16_MEMBER(galgames_eeprom_w);
	157	DECLARE_WRITE16_MEMBER(galgames_palette_offset_w);
	158	DECLARE_WRITE16_MEMBER(galgames_palette_data_w);
	159	DECLARE_READ16_MEMBER(galgames_okiram_r);
	160	DECLARE_WRITE16_MEMBER(galgames_okiram_w);
	161	DECLARE_WRITE16_MEMBER(galgames_cart_sel_w);
	162	DECLARE_READ16_MEMBER(galgames_cart_clock_r);
	163	DECLARE_WRITE16_MEMBER(galgames_cart_clock_w);
	164	DECLARE_READ16_MEMBER(galgames_cart_data_r);
	165	DECLARE_WRITE16_MEMBER(galgames_cart_data_w);
	166	DECLARE_READ16_MEMBER(dummy_read_01);
148	167	};
149	168
150	169
r14845	r14846
215	234	return ((data / 10) << 4) | (data %10);
216	235	}
217	236
218		static READ16_HANDLER(rtc_r)
	237	READ16_MEMBER(tmaster_state::rtc_r)
219	238	{
220		tmaster_state *state = space->machine().driver_data<tmaster_state>();
221	239	system_time systime;
222	240
223		space->machine().current_datetime(systime);
224		state->m_rtc_ram[0x1] = binary_to_BCD(systime.local_time.second);
225		state->m_rtc_ram[0x2] = binary_to_BCD(systime.local_time.minute);
226		state->m_rtc_ram[0x3] = binary_to_BCD(systime.local_time.hour);
227		state->m_rtc_ram[0x4] = binary_to_BCD(systime.local_time.weekday);
228		state->m_rtc_ram[0x5] = binary_to_BCD(systime.local_time.mday);
229		state->m_rtc_ram[0x6] = binary_to_BCD(systime.local_time.month+1);
230		state->m_rtc_ram[0x7] = binary_to_BCD(systime.local_time.year % 100);
	241	machine().current_datetime(systime);
	242	m_rtc_ram[0x1] = binary_to_BCD(systime.local_time.second);
	243	m_rtc_ram[0x2] = binary_to_BCD(systime.local_time.minute);
	244	m_rtc_ram[0x3] = binary_to_BCD(systime.local_time.hour);
	245	m_rtc_ram[0x4] = binary_to_BCD(systime.local_time.weekday);
	246	m_rtc_ram[0x5] = binary_to_BCD(systime.local_time.mday);
	247	m_rtc_ram[0x6] = binary_to_BCD(systime.local_time.month+1);
	248	m_rtc_ram[0x7] = binary_to_BCD(systime.local_time.year % 100);
231	249
232		return state->m_rtc_ram[offset];
	250	return m_rtc_ram[offset];
233	251	}
234	252
235		static WRITE16_HANDLER(rtc_w)
	253	WRITE16_MEMBER(tmaster_state::rtc_w)
236	254	{
237		tmaster_state *state = space->machine().driver_data<tmaster_state>();
238	255	if ( offset == 0 )
239	256	{
240		state->m_rtc_ram[0x0] = data & 0xff;
	257	m_rtc_ram[0x0] = data & 0xff;
241	258	}
242	259	}
243	260
r14845	r14846
347	364	return 0;
348	365	}
349	366
350		static WRITE16_HANDLER( tmaster_color_w )
	367	WRITE16_MEMBER(tmaster_state::tmaster_color_w)
351	368	{
352		tmaster_state *state = space->machine().driver_data<tmaster_state>();
353		COMBINE_DATA( &state->m_color );
	369	COMBINE_DATA( &m_color );
354	370	}
355	371
356		static WRITE16_HANDLER( tmaster_addr_w )
	372	WRITE16_MEMBER(tmaster_state::tmaster_addr_w)
357	373	{
358		tmaster_state *state = space->machine().driver_data<tmaster_state>();
359		COMBINE_DATA( &state->m_addr );
	374	COMBINE_DATA( &m_addr );
360	375	}
361	376
362	377	static void tmaster_draw(running_machine &machine)
r14845	r14846
472	487	}
473	488	}
474	489
475		static WRITE16_HANDLER( tmaster_blitter_w )
	490	WRITE16_MEMBER(tmaster_state::tmaster_blitter_w)
476	491	{
477		tmaster_state *state = space->machine().driver_data<tmaster_state>();
478		COMBINE_DATA( state->m_regs + offset );
	492	COMBINE_DATA( m_regs + offset );
479	493	switch (offset*2)
480	494	{
481	495	case 0x0e:
482		tmaster_draw(space->machine());
483		cputag_set_input_line(space->machine(), "maincpu", 2, HOLD_LINE);
	496	tmaster_draw(machine());
	497	cputag_set_input_line(machine(), "maincpu", 2, HOLD_LINE);
484	498	break;
485	499	}
486	500	}
487	501
488		static READ16_HANDLER( tmaster_blitter_r )
	502	READ16_MEMBER(tmaster_state::tmaster_blitter_r)
489	503	{
490	504	return 0x0000;   // bit 7 = 1 -> blitter busy
491	505	}
r14845	r14846
500	514	Touch Master
501	515	***************************************************************************/
502	516
503		static READ16_HANDLER( tmaster_coins_r )
	517	READ16_MEMBER(tmaster_state::tmaster_coins_r)
504	518	{
505		return input_port_read(space->machine(), "COIN")|(space->machine().rand()&0x0800);
	519	return input_port_read(machine(), "COIN")|(machine().rand()&0x0800);
506	520	}
507	521
508	522	static ADDRESS_MAP_START( tmaster_map, AS_PROGRAM, 16, tmaster_state )
509	523	AM_RANGE( 0x000000, 0x1fffff ) AM_ROM
510	524	AM_RANGE( 0x200000, 0x27ffff ) AM_RAM
511	525	AM_RANGE( 0x280000, 0x28ffef ) AM_RAM AM_SHARE("nvram")
512		AM_RANGE( 0x28fff0, 0x28ffff ) AM_READWRITE_LEGACY(rtc_r, rtc_w )
	526	AM_RANGE( 0x28fff0, 0x28ffff ) AM_READWRITE(rtc_r, rtc_w )
513	527
514		AM_RANGE( 0x300010, 0x300011 ) AM_READ_LEGACY(tmaster_coins_r )
	528	AM_RANGE( 0x300010, 0x300011 ) AM_READ(tmaster_coins_r )
515	529
516	530	AM_RANGE( 0x300020, 0x30003f ) AM_DEVREADWRITE8_LEGACY("duart68681", duart68681_r, duart68681_w, 0xff )
517	531
518	532	AM_RANGE( 0x300040, 0x300041 ) AM_DEVWRITE_LEGACY("oki", tmaster_oki_bank_w )
519	533
520		AM_RANGE( 0x300070, 0x300071 ) AM_WRITE_LEGACY(tmaster_addr_w )
	534	AM_RANGE( 0x300070, 0x300071 ) AM_WRITE(tmaster_addr_w )
521	535
522		AM_RANGE( 0x500000, 0x500011 ) AM_WRITE_LEGACY(tmaster_blitter_w ) AM_BASE(m_regs )
523		AM_RANGE( 0x500010, 0x500011 ) AM_READ_LEGACY(tmaster_blitter_r )
	536	AM_RANGE( 0x500000, 0x500011 ) AM_WRITE(tmaster_blitter_w ) AM_BASE(m_regs )
	537	AM_RANGE( 0x500010, 0x500011 ) AM_READ(tmaster_blitter_r )
524	538
525	539	AM_RANGE( 0x580000, 0x580001 ) AM_WRITENOP // often
526	540
r14845	r14846
528	542
529	543	AM_RANGE( 0x800000, 0x800001 ) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff )
530	544
531		AM_RANGE( 0x800010, 0x800011 ) AM_WRITE_LEGACY(tmaster_color_w )
	545	AM_RANGE( 0x800010, 0x800011 ) AM_WRITE(tmaster_color_w )
532	546	ADDRESS_MAP_END
533	547
534	548
r14845	r14846
574	588
575	589	static const char *const galgames_eeprom_names[5] = { GALGAMES_EEPROM_BIOS, GALGAMES_EEPROM_CART1, GALGAMES_EEPROM_CART2, GALGAMES_EEPROM_CART3, GALGAMES_EEPROM_CART4 };
576	590
577		static READ16_HANDLER( galgames_eeprom_r )
	591	READ16_MEMBER(tmaster_state::galgames_eeprom_r)
578	592	{
579		tmaster_state *state = space->machine().driver_data<tmaster_state>();
580		eeprom_device *eeprom = space->machine().device<eeprom_device>(galgames_eeprom_names[state->m_galgames_cart]);
	593	eeprom_device *eeprom = machine().device<eeprom_device>(galgames_eeprom_names[m_galgames_cart]);
581	594
582	595	return eeprom->read_bit() ? 0x80 : 0x00;
583	596	}
584	597
585		static WRITE16_HANDLER( galgames_eeprom_w )
	598	WRITE16_MEMBER(tmaster_state::galgames_eeprom_w)
586	599	{
587		tmaster_state *state = space->machine().driver_data<tmaster_state>();
588	600	if (data & ~0x0003)
589		logerror("CPU #0 PC: %06X - Unknown EEPROM bit written %04X\n",cpu_get_pc(&space->device()),data);
	601	logerror("CPU #0 PC: %06X - Unknown EEPROM bit written %04X\n",cpu_get_pc(&space.device()),data);
590	602
591	603	if ( ACCESSING_BITS_0_7 )
592	604	{
593		eeprom_device *eeprom = space->machine().device<eeprom_device>(galgames_eeprom_names[state->m_galgames_cart]);
	605	eeprom_device *eeprom = machine().device<eeprom_device>(galgames_eeprom_names[m_galgames_cart]);
594	606
595	607	// latch the bit
596	608	eeprom->write_bit(data & 0x0001);
r14845	r14846
602	614
603	615	// BT481A Palette RAMDAC
604	616
605		static WRITE16_HANDLER( galgames_palette_offset_w )
	617	WRITE16_MEMBER(tmaster_state::galgames_palette_offset_w)
606	618	{
607		tmaster_state *state = space->machine().driver_data<tmaster_state>();
608	619	if (ACCESSING_BITS_0_7)
609	620	{
610		state->m_palette_offset = data & 0xff;
611		state->m_palette_index = 0;
	621	m_palette_offset = data & 0xff;
	622	m_palette_index = 0;
612	623	}
613	624	}
614		static WRITE16_HANDLER( galgames_palette_data_w )
	625	WRITE16_MEMBER(tmaster_state::galgames_palette_data_w)
615	626	{
616		tmaster_state *state = space->machine().driver_data<tmaster_state>();
617	627	if (ACCESSING_BITS_0_7)
618	628	{
619		state->m_palette_data[state->m_palette_index] = data & 0xff;
620		if (++state->m_palette_index == 3)
	629	m_palette_data[m_palette_index] = data & 0xff;
	630	if (++m_palette_index == 3)
621	631	{
622	632	int palette_base;
623	633	for (palette_base = 0; palette_base < 0x1000; palette_base += 0x100)
624		palette_set_color(space->machine(), state->m_palette_offset + palette_base, MAKE_RGB(state->m_palette_data[0], state->m_palette_data[1], state->m_palette_data[2]));
625		state->m_palette_index = 0;
626		state->m_palette_offset++;
	634	palette_set_color(machine(), m_palette_offset + palette_base, MAKE_RGB(m_palette_data[0], m_palette_data[1], m_palette_data[2]));
	635	m_palette_index = 0;
	636	m_palette_offset++;
627	637	}
628	638	}
629	639	}
630	640
631	641	// Sound
632		static READ16_HANDLER( galgames_okiram_r )
	642	READ16_MEMBER(tmaster_state::galgames_okiram_r)
633	643	{
634		return space->machine().region("oki")->base()[offset] | 0xff00;
	644	return machine().region("oki")->base()[offset] | 0xff00;
635	645	}
636		static WRITE16_HANDLER( galgames_okiram_w )
	646	WRITE16_MEMBER(tmaster_state::galgames_okiram_w)
637	647	{
638	648	if (ACCESSING_BITS_0_7)
639		space->machine().region("oki")->base()[offset] = data & 0xff;
	649	machine().region("oki")->base()[offset] = data & 0xff;
640	650	}
641	651
642	652	// Carts (preliminary, PIC communication is not implemented)
r14845	r14846
654	664	memory_set_bank(machine, GALGAMES_BANK_240000_R, GALGAMES_ROM0 + state->m_galgames_cart);   // rom
655	665	}
656	666
657		static WRITE16_HANDLER( galgames_cart_sel_w )
	667	WRITE16_MEMBER(tmaster_state::galgames_cart_sel_w)
658	668	{
659	669	// cart selection (0 1 2 3 4 7)
660	670
r14845	r14846
666	676	{
667	677	case 0x07:      // 7 resets the eeprom
668	678	for (i = 0; i < 5; i++)
669		space->machine().device<eeprom_device>(galgames_eeprom_names[i])->set_cs_line(ASSERT_LINE);
	679	machine().device<eeprom_device>(galgames_eeprom_names[i])->set_cs_line(ASSERT_LINE);
670	680	break;
671	681
672	682	case 0x00:
r14845	r14846
674	684	case 0x02:
675	685	case 0x03:
676	686	case 0x04:
677		space->machine().device<eeprom_device>(galgames_eeprom_names[data & 0xff])->set_cs_line(CLEAR_LINE);
678		galgames_update_rombank(space->machine(), data & 0xff);
	687	machine().device<eeprom_device>(galgames_eeprom_names[data & 0xff])->set_cs_line(CLEAR_LINE);
	688	galgames_update_rombank(machine(), data & 0xff);
679	689	break;
680	690
681	691	default:
682		space->machine().device<eeprom_device>(galgames_eeprom_names[0])->set_cs_line(CLEAR_LINE);
683		galgames_update_rombank(space->machine(), 0);
684		logerror("%06x: unknown cart sel = %04x\n", cpu_get_pc(&space->device()), data);
	692	machine().device<eeprom_device>(galgames_eeprom_names[0])->set_cs_line(CLEAR_LINE);
	693	galgames_update_rombank(machine(), 0);
	694	logerror("%06x: unknown cart sel = %04x\n", cpu_get_pc(&space.device()), data);
685	695	break;
686	696	}
687	697	}
688	698	}
689	699
690		static READ16_HANDLER( galgames_cart_clock_r )
	700	READ16_MEMBER(tmaster_state::galgames_cart_clock_r)
691	701	{
692	702	return 0x0080;
693	703	}
694	704
695		static WRITE16_HANDLER( galgames_cart_clock_w )
	705	WRITE16_MEMBER(tmaster_state::galgames_cart_clock_w)
696	706	{
697		tmaster_state *state = space->machine().driver_data<tmaster_state>();
698	707	if (ACCESSING_BITS_0_7)
699	708	{
700	709	// bit 3 = clock
r14845	r14846
702	711	// ROM/RAM banking
703	712	if ((data & 0xf7) == 0x05)
704	713	{
705		memory_set_bank(space->machine(), GALGAMES_BANK_000000_R, GALGAMES_RAM);   // ram
706		galgames_update_rombank(space->machine(), state->m_galgames_cart);
707		logerror("%06x: romram bank = %04x\n", cpu_get_pc(&space->device()), data);
	714	memory_set_bank(machine(), GALGAMES_BANK_000000_R, GALGAMES_RAM);   // ram
	715	galgames_update_rombank(machine(), m_galgames_cart);
	716	logerror("%06x: romram bank = %04x\n", cpu_get_pc(&space.device()), data);
708	717	}
709	718	else
710	719	{
711		memory_set_bank(space->machine(), GALGAMES_BANK_000000_R, GALGAMES_ROM0);   // rom
712		memory_set_bank(space->machine(), GALGAMES_BANK_200000_R, GALGAMES_RAM);   // ram
713		logerror("%06x: unknown romram bank = %04x\n", cpu_get_pc(&space->device()), data);
	720	memory_set_bank(machine(), GALGAMES_BANK_000000_R, GALGAMES_ROM0);   // rom
	721	memory_set_bank(machine(), GALGAMES_BANK_200000_R, GALGAMES_RAM);   // ram
	722	logerror("%06x: unknown romram bank = %04x\n", cpu_get_pc(&space.device()), data);
714	723	}
715	724	}
716	725	}
717	726
718		static READ16_HANDLER( galgames_cart_data_r )
	727	READ16_MEMBER(tmaster_state::galgames_cart_data_r)
719	728	{
720	729	return 0;
721	730	}
722		static WRITE16_HANDLER( galgames_cart_data_w )
	731	WRITE16_MEMBER(tmaster_state::galgames_cart_data_w)
723	732	{
724	733	}
725	734
726	735
727		static READ16_HANDLER( dummy_read_01 )
	736	READ16_MEMBER(tmaster_state::dummy_read_01)
728	737	{
729	738	return 0x3;   // Pass the check at PC = 0xfae & a later one
730	739	}
r14845	r14846
736	745	AM_RANGE( 0x200000, 0x23ffff ) AM_READ_BANK(GALGAMES_BANK_200000_R) AM_WRITE_BANK(GALGAMES_BANK_200000_W)
737	746	AM_RANGE( 0x240000, 0x3fffff ) AM_READ_BANK(GALGAMES_BANK_240000_R)
738	747
739		AM_RANGE( 0x400000, 0x400011 ) AM_WRITE_LEGACY(tmaster_blitter_w ) AM_BASE(m_regs )
740		AM_RANGE( 0x400012, 0x400013 ) AM_WRITE_LEGACY(tmaster_addr_w )
741		AM_RANGE( 0x400014, 0x400015 ) AM_WRITE_LEGACY(tmaster_color_w )
742		AM_RANGE( 0x400020, 0x400021 ) AM_READ_LEGACY(tmaster_blitter_r )
	748	AM_RANGE( 0x400000, 0x400011 ) AM_WRITE(tmaster_blitter_w ) AM_BASE(m_regs )
	749	AM_RANGE( 0x400012, 0x400013 ) AM_WRITE(tmaster_addr_w )
	750	AM_RANGE( 0x400014, 0x400015 ) AM_WRITE(tmaster_color_w )
	751	AM_RANGE( 0x400020, 0x400021 ) AM_READ(tmaster_blitter_r )
743	752
744		AM_RANGE( 0x600000, 0x600001 ) AM_READ_LEGACY(dummy_read_01 ) AM_WRITENOP
745		AM_RANGE( 0x700000, 0x700001 ) AM_READ_LEGACY(dummy_read_01 ) AM_WRITENOP
	753	AM_RANGE( 0x600000, 0x600001 ) AM_READ(dummy_read_01 ) AM_WRITENOP
	754	AM_RANGE( 0x700000, 0x700001 ) AM_READ(dummy_read_01 ) AM_WRITENOP
746	755	AM_RANGE( 0x800020, 0x80003f ) AM_NOP   // ?
747	756	AM_RANGE( 0x900000, 0x900001 ) AM_WRITE_LEGACY(watchdog_reset16_w )
748	757
749	758	AM_RANGE( 0xa00000, 0xa00001 ) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff )
750		AM_RANGE( 0xb00000, 0xb7ffff ) AM_READWRITE_LEGACY(galgames_okiram_r, galgames_okiram_w ) // (only low bytes tested) 4x N341024SJ-15
	759	AM_RANGE( 0xb00000, 0xb7ffff ) AM_READWRITE(galgames_okiram_r, galgames_okiram_w ) // (only low bytes tested) 4x N341024SJ-15
751	760
752		AM_RANGE( 0xc00000, 0xc00001 ) AM_WRITE_LEGACY(galgames_palette_offset_w )
753		AM_RANGE( 0xc00002, 0xc00003 ) AM_WRITE_LEGACY(galgames_palette_data_w )
	761	AM_RANGE( 0xc00000, 0xc00001 ) AM_WRITE(galgames_palette_offset_w )
	762	AM_RANGE( 0xc00002, 0xc00003 ) AM_WRITE(galgames_palette_data_w )
754	763
755	764	AM_RANGE( 0xd00000, 0xd00001 ) AM_READ_PORT("TRACKBALL_1_X")
756	765	AM_RANGE( 0xd00000, 0xd00001 ) AM_WRITENOP
r14845	r14846
761	770	AM_RANGE( 0xd0000a, 0xd0000b ) AM_READ_PORT("P2")
762	771	AM_RANGE( 0xd0000c, 0xd0000d ) AM_READ_PORT("SYSTEM") AM_WRITENOP
763	772
764		AM_RANGE( 0xd0000e, 0xd0000f ) AM_WRITE_LEGACY(galgames_cart_sel_w )
765		AM_RANGE( 0xd00010, 0xd00011 ) AM_READWRITE_LEGACY(galgames_eeprom_r, galgames_eeprom_w )
766		AM_RANGE( 0xd00012, 0xd00013 ) AM_READWRITE_LEGACY(galgames_cart_data_r, galgames_cart_data_w )
767		AM_RANGE( 0xd00014, 0xd00015 ) AM_READWRITE_LEGACY(galgames_cart_clock_r, galgames_cart_clock_w )
	773	AM_RANGE( 0xd0000e, 0xd0000f ) AM_WRITE(galgames_cart_sel_w )
	774	AM_RANGE( 0xd00010, 0xd00011 ) AM_READWRITE(galgames_eeprom_r, galgames_eeprom_w )
	775	AM_RANGE( 0xd00012, 0xd00013 ) AM_READWRITE(galgames_cart_data_r, galgames_cart_data_w )
	776	AM_RANGE( 0xd00014, 0xd00015 ) AM_READWRITE(galgames_cart_clock_r, galgames_cart_clock_w )
768	777
769	778	ADDRESS_MAP_END
770	779

src/mame/drivers/flyball.c

r14845	r14846
42	42
43	43	/* devices */
44	44	device_t *m_maincpu;
	45	DECLARE_READ8_MEMBER(flyball_input_r);
	46	DECLARE_READ8_MEMBER(flyball_scanline_r);
	47	DECLARE_READ8_MEMBER(flyball_potsense_r);
	48	DECLARE_WRITE8_MEMBER(flyball_potmask_w);
	49	DECLARE_WRITE8_MEMBER(flyball_pitcher_pic_w);
	50	DECLARE_WRITE8_MEMBER(flyball_ball_vert_w);
	51	DECLARE_WRITE8_MEMBER(flyball_ball_horz_w);
	52	DECLARE_WRITE8_MEMBER(flyball_pitcher_vert_w);
	53	DECLARE_WRITE8_MEMBER(flyball_pitcher_horz_w);
	54	DECLARE_WRITE8_MEMBER(flyball_misc_w);
45	55	};
46	56
47	57
r14845	r14846
159	169	*************************************/
160	170
161	171	/* two physical buttons (start game and stop runner) share the same port bit */
162		static READ8_HANDLER( flyball_input_r )
	172	READ8_MEMBER(flyball_state::flyball_input_r)
163	173	{
164		return input_port_read(space->machine(), "IN0") & input_port_read(space->machine(), "IN1");
	174	return input_port_read(machine(), "IN0") & input_port_read(machine(), "IN1");
165	175	}
166	176
167		static READ8_HANDLER( flyball_scanline_r )
	177	READ8_MEMBER(flyball_state::flyball_scanline_r)
168	178	{
169		return space->machine().primary_screen->vpos() & 0x3f;
	179	return machine().primary_screen->vpos() & 0x3f;
170	180	}
171	181
172		static READ8_HANDLER( flyball_potsense_r )
	182	READ8_MEMBER(flyball_state::flyball_potsense_r)
173	183	{
174		flyball_state *state = space->machine().driver_data<flyball_state>();
175		return state->m_potsense & ~state->m_potmask;
	184	return m_potsense & ~m_potmask;
176	185	}
177	186
178		static WRITE8_HANDLER( flyball_potmask_w )
	187	WRITE8_MEMBER(flyball_state::flyball_potmask_w)
179	188	{
180		flyball_state *state = space->machine().driver_data<flyball_state>();
181		state->m_potmask |= data & 0xf;
	189	m_potmask |= data & 0xf;
182	190	}
183	191
184		static WRITE8_HANDLER( flyball_pitcher_pic_w )
	192	WRITE8_MEMBER(flyball_state::flyball_pitcher_pic_w)
185	193	{
186		flyball_state *state = space->machine().driver_data<flyball_state>();
187		state->m_pitcher_pic = data & 0xf;
	194	m_pitcher_pic = data & 0xf;
188	195	}
189	196
190		static WRITE8_HANDLER( flyball_ball_vert_w )
	197	WRITE8_MEMBER(flyball_state::flyball_ball_vert_w)
191	198	{
192		flyball_state *state = space->machine().driver_data<flyball_state>();
193		state->m_ball_vert = data;
	199	m_ball_vert = data;
194	200	}
195	201
196		static WRITE8_HANDLER( flyball_ball_horz_w )
	202	WRITE8_MEMBER(flyball_state::flyball_ball_horz_w)
197	203	{
198		flyball_state *state = space->machine().driver_data<flyball_state>();
199		state->m_ball_horz = data;
	204	m_ball_horz = data;
200	205	}
201	206
202		static WRITE8_HANDLER( flyball_pitcher_vert_w )
	207	WRITE8_MEMBER(flyball_state::flyball_pitcher_vert_w)
203	208	{
204		flyball_state *state = space->machine().driver_data<flyball_state>();
205		state->m_pitcher_vert = data;
	209	m_pitcher_vert = data;
206	210	}
207	211
208		static WRITE8_HANDLER( flyball_pitcher_horz_w )
	212	WRITE8_MEMBER(flyball_state::flyball_pitcher_horz_w)
209	213	{
210		flyball_state *state = space->machine().driver_data<flyball_state>();
211		state->m_pitcher_horz = data;
	214	m_pitcher_horz = data;
212	215	}
213	216
214		static WRITE8_HANDLER( flyball_misc_w )
	217	WRITE8_MEMBER(flyball_state::flyball_misc_w)
215	218	{
216	219	int bit = ~data & 1;
217	220
218	221	switch (offset)
219	222	{
220	223	case 0:
221		set_led_status(space->machine(), 0, bit);
	224	set_led_status(machine(), 0, bit);
222	225	break;
223	226	case 1:
224	227	/* crowd very loud */
r14845	r14846
249	252	ADDRESS_MAP_GLOBAL_MASK(0x1fff)
250	253	AM_RANGE(0x0000, 0x00ff) AM_MIRROR(0x100) AM_RAM
251	254	AM_RANGE(0x0800, 0x0800) AM_NOP
252		AM_RANGE(0x0801, 0x0801) AM_WRITE_LEGACY(flyball_pitcher_pic_w)
253		AM_RANGE(0x0802, 0x0802) AM_READ_LEGACY(flyball_scanline_r)
254		AM_RANGE(0x0803, 0x0803) AM_READ_LEGACY(flyball_potsense_r)
255		AM_RANGE(0x0804, 0x0804) AM_WRITE_LEGACY(flyball_ball_vert_w)
256		AM_RANGE(0x0805, 0x0805) AM_WRITE_LEGACY(flyball_ball_horz_w)
257		AM_RANGE(0x0806, 0x0806) AM_WRITE_LEGACY(flyball_pitcher_vert_w)
258		AM_RANGE(0x0807, 0x0807) AM_WRITE_LEGACY(flyball_pitcher_horz_w)
259		AM_RANGE(0x0900, 0x0900) AM_WRITE_LEGACY(flyball_potmask_w)
260		AM_RANGE(0x0a00, 0x0a07) AM_WRITE_LEGACY(flyball_misc_w)
261		AM_RANGE(0x0b00, 0x0b00) AM_READ_LEGACY(flyball_input_r)
	255	AM_RANGE(0x0801, 0x0801) AM_WRITE(flyball_pitcher_pic_w)
	256	AM_RANGE(0x0802, 0x0802) AM_READ(flyball_scanline_r)
	257	AM_RANGE(0x0803, 0x0803) AM_READ(flyball_potsense_r)
	258	AM_RANGE(0x0804, 0x0804) AM_WRITE(flyball_ball_vert_w)
	259	AM_RANGE(0x0805, 0x0805) AM_WRITE(flyball_ball_horz_w)
	260	AM_RANGE(0x0806, 0x0806) AM_WRITE(flyball_pitcher_vert_w)
	261	AM_RANGE(0x0807, 0x0807) AM_WRITE(flyball_pitcher_horz_w)
	262	AM_RANGE(0x0900, 0x0900) AM_WRITE(flyball_potmask_w)
	263	AM_RANGE(0x0a00, 0x0a07) AM_WRITE(flyball_misc_w)
	264	AM_RANGE(0x0b00, 0x0b00) AM_READ(flyball_input_r)
262	265	AM_RANGE(0x0d00, 0x0eff) AM_WRITEONLY AM_BASE(m_playfield_ram)
263	266	AM_RANGE(0x1000, 0x1fff) AM_ROM AM_BASE(m_rombase) /* program */
264	267	ADDRESS_MAP_END

src/mame/drivers/unkhorse.c

r14845	r14846
4	4	probably early 80s, manufacturer unknown
5	5
6	6	from a broken PCB, labeled EFI TG-007
7		8085A CPU + 8155 (for I/O, and maybe sound)
	7	8085A CPU + 8155 (for I/O and sound)
8	8	8KB RAM mainly for bitmap video, and 512x4 RAM for color map
9	9
10	10	TODO:
11	11	- identify game!
12		- sound
13		- improve inputs
14		- confirm colors
	12	- improve I/O:
	13	* more buttons/sensors?
	14	* horse_output_w bits
	15	* 6-pos dipswitch on the pcb, only 4 are known at the moment
	16	- confirm colors and sound pitch
15	17
16	18	***************************************************************************/
17	19
18	20	#include "emu.h"
19	21	#include "cpu/i8085/i8085.h"
20	22	#include "machine/i8155.h"
	23	#include "sound/dac.h"
21	24
22	25
23	26	class horse_state : public driver_device
r14845	r14846
40	43
41	44	PALETTE_INIT( horse )
42	45	{
43		// palette is simply 1bpp
	46	// palette is simply 3bpp
44	47	for (int i = 0; i < 8; i++)
45	48	palette_set_color_rgb(machine, i, pal1bit(i >> 2), pal1bit(i >> 1), pal1bit(i >> 0));
46	49	}
r14845	r14846
87	90	static READ8_DEVICE_HANDLER(horse_input_r)
88	91	{
89	92	horse_state *state = device->machine().driver_data<horse_state>();
90		UINT8 ret = 0xff;
91	93
92		if (state->m_output & 0x80)
93		ret &= input_port_read(device->machine(), "IN0");
	94	switch (state->m_output >> 6 & 3)
	95	{
	96	case 0: return input_port_read(device->machine(), "IN0");
	97	case 1: return input_port_read(device->machine(), "IN1");
	98	case 2: return input_port_read(device->machine(), "IN2");
	99	default: break;
	100	}
94	101
95		if (state->m_output & 0x40)
96		ret &= input_port_read(device->machine(), "IN1");
97
98		return ret;
	102	return 0xff;
99	103	}
100	104
101	105	static WRITE8_DEVICE_HANDLER(horse_output_w)
r14845	r14846
104	108	state->m_output = data;
105	109
106	110	// d4: payout related
107		// d6-d7: input select
	111	// d6-d7: input mux
108	112	// other bits: ?
109	113	}
110	114
111	115	static WRITE_LINE_DEVICE_HANDLER(horse_timer_out)
112	116	{
113		// sound?
114		// TODO
	117	dac_signed_w(device->machine().device("dac"), 0, state ? 0x7f : 0);
115	118	}
116	119
117	120	static I8155_INTERFACE(i8155_intf)
r14845	r14846
135	138
136	139	static INPUT_PORTS_START( horse )
137	140	PORT_START("IN0")
138		PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
	141	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )   PORT_DIPLOCATION("SW:1,2,3")
139	142	PORT_DIPSETTING( 0x01, DEF_STR( 1C_1C ) )
140	143	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
141	144	PORT_DIPSETTING( 0x03, DEF_STR( 1C_3C ) )
r14845	r14846
144	147	PORT_DIPSETTING( 0x06, DEF_STR( 1C_6C ) )
145	148	PORT_DIPSETTING( 0x07, DEF_STR( 1C_7C ) )
146	149	PORT_DIPSETTING( 0x00, "1 Coin/10 Credits" )
147		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
148		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
149		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT )
150		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_TILT )
151		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
	150	PORT_DIPNAME( 0x08, 0x08, "UNK04" )            PORT_DIPLOCATION("SW:4")
	151	PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
	152	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	153	PORT_DIPNAME( 0x10, 0x10, "UNK05" )            PORT_DIPLOCATION("SW:5")
	154	PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
	155	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	156	PORT_DIPNAME( 0x20, 0x20, "Maximum Bet" )      PORT_DIPLOCATION("SW:6")
	157	PORT_DIPSETTING(    0x20, "20" )
	158	PORT_DIPSETTING(    0x00, "50" )
	159	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	160	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
152	161
153	162	PORT_START("IN1")
154		PORT_DIPNAME( 0x01, 0x01, "UNK1" )
155		PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
156		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
157		PORT_DIPNAME( 0x02, 0x02, "UNK2" )
158		PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
159		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
160		PORT_DIPNAME( 0x04, 0x04, "UNK3" )
161		PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
162		PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	163	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
	164	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	165	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
163	166	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
164	167	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
165	168	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
166	169	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
167	170	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	171
	172	PORT_START("IN2")
	173	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
	174	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	175	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	176	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	177	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	178	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT )
	179	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_TILT )
	180	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 )
168	181	INPUT_PORTS_END
169	182
170	183
r14845	r14846
187	200	MCFG_CPU_IO_MAP(horse_io_map)
188	201	MCFG_CPU_VBLANK_INT("screen", horse_interrupt)
189	202
190		MCFG_I8155_ADD("i8155", XTAL_12MHz / 2, i8155_intf) // divider guessed
	203	MCFG_I8155_ADD("i8155", XTAL_12MHz / 2, i8155_intf)
191	204
192	205	/* video hardware */
193	206	MCFG_SCREEN_ADD("screen", RASTER)
r14845	r14846
202	215	MCFG_PALETTE_INIT(horse)
203	216
204	217	/* sound hardware */
205		// ..
	218	MCFG_SPEAKER_STANDARD_MONO("mono")
	219
	220	MCFG_SOUND_ADD("dac", DAC, 0)
	221	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
206	222	MACHINE_CONFIG_END
207	223
208	224
r14845	r14846
224	240	ROM_END
225	241
226	242
227		GAME( 19??, unkhorse, 0, horse, horse, 0, ROT270, "<unknown>", "unknown Japanese horse gambling game", GAME_NO_SOUND | GAME_IMPERFECT_COLORS )
	243	GAME( 19??, unkhorse, 0, horse, horse, 0, ROT270, "<unknown>", "unknown Japanese horse gambling game", 0 )

src/mame/drivers/pturn.c

r14845	r14846
97	97	int m_nmi_sub;
98	98	UINT8 *m_spriteram;
99	99	size_t m_spriteram_size;
	100	DECLARE_WRITE8_MEMBER(pturn_videoram_w);
	101	DECLARE_WRITE8_MEMBER(nmi_main_enable_w);
	102	DECLARE_WRITE8_MEMBER(nmi_sub_enable_w);
	103	DECLARE_WRITE8_MEMBER(sound_w);
	104	DECLARE_WRITE8_MEMBER(bgcolor_w);
	105	DECLARE_WRITE8_MEMBER(bg_scrollx_w);
	106	DECLARE_WRITE8_MEMBER(fgpalette_w);
	107	DECLARE_WRITE8_MEMBER(bg_scrolly_w);
	108	DECLARE_WRITE8_MEMBER(fgbank_w);
	109	DECLARE_WRITE8_MEMBER(bgbank_w);
	110	DECLARE_WRITE8_MEMBER(flip_w);
	111	DECLARE_READ8_MEMBER(pturn_custom_r);
100	112	};
101	113
102	114
r14845	r14846
202	214	}
203	215	#endif
204	216
205		static WRITE8_HANDLER( pturn_videoram_w )
	217	WRITE8_MEMBER(pturn_state::pturn_videoram_w)
206	218	{
207		pturn_state *state = space->machine().driver_data<pturn_state>();
208		UINT8 *videoram = state->m_videoram;
	219	UINT8 *videoram = m_videoram;
209	220	videoram[offset]=data;
210		state->m_fgmap->mark_tile_dirty(offset);
	221	m_fgmap->mark_tile_dirty(offset);
211	222	}
212	223
213	224
214		static WRITE8_HANDLER( nmi_main_enable_w )
	225	WRITE8_MEMBER(pturn_state::nmi_main_enable_w)
215	226	{
216		pturn_state *state = space->machine().driver_data<pturn_state>();
217		state->m_nmi_main = data;
	227	m_nmi_main = data;
218	228	}
219	229
220		static WRITE8_HANDLER( nmi_sub_enable_w )
	230	WRITE8_MEMBER(pturn_state::nmi_sub_enable_w)
221	231	{
222		pturn_state *state = space->machine().driver_data<pturn_state>();
223		state->m_nmi_sub = data;
	232	m_nmi_sub = data;
224	233	}
225	234
226		static WRITE8_HANDLER(sound_w)
	235	WRITE8_MEMBER(pturn_state::sound_w)
227	236	{
228	237	soundlatch_w(space,0,data);
229	238	}
230	239
231	240
232		static WRITE8_HANDLER(bgcolor_w)
	241	WRITE8_MEMBER(pturn_state::bgcolor_w)
233	242	{
234		pturn_state *state = space->machine().driver_data<pturn_state>();
235		state->m_bgcolor=data;
	243	m_bgcolor=data;
236	244	}
237	245
238		static WRITE8_HANDLER(bg_scrollx_w)
	246	WRITE8_MEMBER(pturn_state::bg_scrollx_w)
239	247	{
240		pturn_state *state = space->machine().driver_data<pturn_state>();
241		state->m_bgmap->set_scrolly(0, (data>>5)*32*8);
242		state->m_bgpalette=data&0x1f;
243		state->m_bgmap->mark_all_dirty();
	248	m_bgmap->set_scrolly(0, (data>>5)*32*8);
	249	m_bgpalette=data&0x1f;
	250	m_bgmap->mark_all_dirty();
244	251	}
245	252
246		static WRITE8_HANDLER(fgpalette_w)
	253	WRITE8_MEMBER(pturn_state::fgpalette_w)
247	254	{
248		pturn_state *state = space->machine().driver_data<pturn_state>();
249		state->m_fgpalette=data&0x1f;
250		state->m_fgmap->mark_all_dirty();
	255	m_fgpalette=data&0x1f;
	256	m_fgmap->mark_all_dirty();
251	257	}
252	258
253		static WRITE8_HANDLER(bg_scrolly_w)
	259	WRITE8_MEMBER(pturn_state::bg_scrolly_w)
254	260	{
255		pturn_state *state = space->machine().driver_data<pturn_state>();
256		state->m_bgmap->set_scrollx(0, data);
	261	m_bgmap->set_scrollx(0, data);
257	262	}
258	263
259		static WRITE8_HANDLER(fgbank_w)
	264	WRITE8_MEMBER(pturn_state::fgbank_w)
260	265	{
261		pturn_state *state = space->machine().driver_data<pturn_state>();
262		state->m_fgbank=data&1;
263		state->m_fgmap->mark_all_dirty();
	266	m_fgbank=data&1;
	267	m_fgmap->mark_all_dirty();
264	268	}
265	269
266		static WRITE8_HANDLER(bgbank_w)
	270	WRITE8_MEMBER(pturn_state::bgbank_w)
267	271	{
268		pturn_state *state = space->machine().driver_data<pturn_state>();
269		state->m_bgbank=data&1;
270		state->m_bgmap->mark_all_dirty();
	272	m_bgbank=data&1;
	273	m_bgmap->mark_all_dirty();
271	274	}
272	275
273		static WRITE8_HANDLER(flip_w)
	276	WRITE8_MEMBER(pturn_state::flip_w)
274	277	{
275		flip_screen_set(space->machine(), data);
	278	flip_screen_set(machine(), data);
276	279	}
277	280
278	281
279		static READ8_HANDLER (pturn_custom_r)
	282	READ8_MEMBER(pturn_state::pturn_custom_r)
280	283	{
281	284	int addr = (int)offset + 0xc800;
282	285
r14845	r14846
305	308	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, pturn_state )
306	309	AM_RANGE(0x0000, 0x7fff) AM_ROM
307	310	AM_RANGE(0xc000, 0xc7ff) AM_RAM
308		AM_RANGE(0xc800, 0xcfff) AM_WRITENOP AM_READ_LEGACY(pturn_custom_r)
	311	AM_RANGE(0xc800, 0xcfff) AM_WRITENOP AM_READ(pturn_custom_r)
309	312
310	313	AM_RANGE(0xdfe0, 0xdfe0) AM_NOP
311	314
312		AM_RANGE(0xe000, 0xe3ff) AM_RAM_WRITE_LEGACY(pturn_videoram_w) AM_BASE(m_videoram)
313		AM_RANGE(0xe400, 0xe400) AM_WRITE_LEGACY(fgpalette_w)
314		AM_RANGE(0xe800, 0xe800) AM_WRITE_LEGACY(sound_w)
	315	AM_RANGE(0xe000, 0xe3ff) AM_RAM_WRITE(pturn_videoram_w) AM_BASE(m_videoram)
	316	AM_RANGE(0xe400, 0xe400) AM_WRITE(fgpalette_w)
	317	AM_RANGE(0xe800, 0xe800) AM_WRITE(sound_w)
315	318
316	319	AM_RANGE(0xf000, 0xf0ff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
317	320
318		AM_RANGE(0xf400, 0xf400) AM_WRITE_LEGACY(bg_scrollx_w)
	321	AM_RANGE(0xf400, 0xf400) AM_WRITE(bg_scrollx_w)
319	322
320	323	AM_RANGE(0xf800, 0xf800) AM_READ_PORT("P1") AM_WRITENOP
321		AM_RANGE(0xf801, 0xf801) AM_READ_PORT("P2") AM_WRITE_LEGACY(bgcolor_w)
	324	AM_RANGE(0xf801, 0xf801) AM_READ_PORT("P2") AM_WRITE(bgcolor_w)
322	325	AM_RANGE(0xf802, 0xf802) AM_READ_PORT("SYSTEM")
323		AM_RANGE(0xf803, 0xf803) AM_WRITE_LEGACY(bg_scrolly_w)
	326	AM_RANGE(0xf803, 0xf803) AM_WRITE(bg_scrolly_w)
324	327	AM_RANGE(0xf804, 0xf804) AM_READ_PORT("DSW2")
325	328	AM_RANGE(0xf805, 0xf805) AM_READ_PORT("DSW1")
326	329	AM_RANGE(0xf806, 0xf806) AM_READNOP /* Protection related, ((val&3)==2) -> jump to 0 */
327	330
328		AM_RANGE(0xfc00, 0xfc00) AM_WRITE_LEGACY(flip_w)
329		AM_RANGE(0xfc01, 0xfc01) AM_WRITE_LEGACY(nmi_main_enable_w)
	331	AM_RANGE(0xfc00, 0xfc00) AM_WRITE(flip_w)
	332	AM_RANGE(0xfc01, 0xfc01) AM_WRITE(nmi_main_enable_w)
330	333	AM_RANGE(0xfc02, 0xfc02) AM_WRITENOP /* Unknown */
331	334	AM_RANGE(0xfc03, 0xfc03) AM_WRITENOP /* Unknown */
332		AM_RANGE(0xfc04, 0xfc04) AM_WRITE_LEGACY(bgbank_w)
333		AM_RANGE(0xfc05, 0xfc05) AM_WRITE_LEGACY(fgbank_w)
	335	AM_RANGE(0xfc04, 0xfc04) AM_WRITE(bgbank_w)
	336	AM_RANGE(0xfc05, 0xfc05) AM_WRITE(fgbank_w)
334	337	AM_RANGE(0xfc06, 0xfc06) AM_WRITENOP /* Unknown */
335	338	AM_RANGE(0xfc07, 0xfc07) AM_WRITENOP /* Unknown */
336	339
r14845	r14846
339	342	static ADDRESS_MAP_START( sub_map, AS_PROGRAM, 8, pturn_state )
340	343	AM_RANGE(0x0000, 0x0fff) AM_ROM
341	344	AM_RANGE(0x2000, 0x23ff) AM_RAM
342		AM_RANGE(0x3000, 0x3000) AM_READ_LEGACY(soundlatch_r) AM_WRITE_LEGACY(nmi_sub_enable_w)
	345	AM_RANGE(0x3000, 0x3000) AM_READ_LEGACY(soundlatch_r) AM_WRITE(nmi_sub_enable_w)
343	346	AM_RANGE(0x4000, 0x4000) AM_RAM
344	347	AM_RANGE(0x5000, 0x5001) AM_DEVWRITE_LEGACY("ay1", ay8910_address_data_w)
345	348	AM_RANGE(0x6000, 0x6001) AM_DEVWRITE_LEGACY("ay2", ay8910_address_data_w)

src/mame/drivers/jubilee.c

r14845	r14846
98	98
99	99	UINT8 *m_videoram;
100	100	tilemap_t *m_bg_tilemap;
	101	DECLARE_WRITE8_MEMBER(jubileep_videoram_w);
	102	DECLARE_READ8_MEMBER(unk_r);
101	103	};
102	104
103	105
r14845	r14846
106	108	*************************/
107	109
108	110
109		static WRITE8_HANDLER( jubileep_videoram_w )
	111	WRITE8_MEMBER(jubilee_state::jubileep_videoram_w)
110	112	{
111		jubilee_state *state = space->machine().driver_data<jubilee_state>();
112		state->m_videoram[offset] = data;
113		state->m_bg_tilemap->mark_tile_dirty(offset);
	113	m_videoram[offset] = data;
	114	m_bg_tilemap->mark_tile_dirty(offset);
114	115	}
115	116
116	117
r14845	r14846
163	164	static ADDRESS_MAP_START( jubileep_map, AS_PROGRAM, 8, jubilee_state )
164	165	ADDRESS_MAP_GLOBAL_MASK(0x3fff)
165	166	AM_RANGE(0x0000, 0x2fff) AM_ROM
166		AM_RANGE(0x3000, 0x30ff) AM_WRITE_LEGACY(jubileep_videoram_w) AM_BASE(m_videoram)   /* wrong... just placed somewhere */
	167	AM_RANGE(0x3000, 0x30ff) AM_WRITE(jubileep_videoram_w) AM_BASE(m_videoram)   /* wrong... just placed somewhere */
167	168	AM_RANGE(0x3100, 0x3fff) AM_RAM
168	169	ADDRESS_MAP_END
169	170
r14845	r14846
177	178	*/
178	179
179	180
180		static READ8_HANDLER(unk_r)
	181	READ8_MEMBER(jubilee_state::unk_r)
181	182	{
182		return (space->machine().rand() & 0xff);
	183	return (machine().rand() & 0xff);
183	184	}
184	185
185	186	static ADDRESS_MAP_START( jubileep_cru_map, AS_IO, 8, jubilee_state )
186		//  AM_RANGE(0x0000, 0xffff) AM_READ_LEGACY(unk_r)
	187	//  AM_RANGE(0x0000, 0xffff) AM_READ(unk_r)
187	188	//  AM_RANGE(0x00, 0x00) AM_DEVREADWRITE_LEGACY("crtc",  mc6845_status_r, mc6845_address_w)
188	189	//  AM_RANGE(0x01, 0x01) AM_DEVREADWRITE_LEGACY("crtc", mc6845_register_r, mc6845_register_w)
189		AM_RANGE(0xc8, 0xc8) AM_READ_LEGACY(unk_r)
	190	AM_RANGE(0xc8, 0xc8) AM_READ(unk_r)
190	191	ADDRESS_MAP_END
191	192
192	193	/* I/O byte R/W

src/mame/drivers/goldngam.c

r14845	r14846
244	244	: driver_device(mconfig, type, tag) { }
245	245
246	246	UINT16 *m_videoram;
	247	DECLARE_READ16_MEMBER(unk_r);
247	248	};
248	249
249	250
r14845	r14846
289	290	* Memory Map Information *
290	291	*************************/
291	292
292		static READ16_HANDLER(unk_r)
	293	READ16_MEMBER(goldngam_state::unk_r)
293	294	{
294		int test1 = (space->machine().rand() & 0xae00);
	295	int test1 = (machine().rand() & 0xae00);
295	296	//  popmessage("VAL = %02x", test1);
296	297
297	298	return test1;
r14845	r14846
301	302	AM_RANGE(0x000000, 0x03ffff) AM_ROM
302	303	AM_RANGE(0x200000, 0x20ffff) AM_RAM
303	304	AM_RANGE(0x400002, 0x400003) AM_NOP // hopper status read ?
304		AM_RANGE(0x40000c, 0x40000d) AM_READ_LEGACY(unk_r)
	305	AM_RANGE(0x40000c, 0x40000d) AM_READ(unk_r)
305	306	AM_RANGE(0x40000e, 0x40000f) AM_READ_PORT("DSW2")   // not sure...
306	307	AM_RANGE(0x402000, 0x402001) AM_DEVREAD8_LEGACY("aysnd", ay8910_r, 0x00ff)
307	308	AM_RANGE(0x402000, 0x402003) AM_DEVWRITE8_LEGACY("aysnd", ay8910_address_data_w, 0x00ff) //wrong

src/mame/drivers/laserbas.c

r14845	r14846
49	49	UINT8    m_vram1[0x8000];
50	50	UINT8    m_vram2[0x8000];
51	51	UINT8    *m_protram;
	52	DECLARE_READ8_MEMBER(vram_r);
	53	DECLARE_WRITE8_MEMBER(vram_w);
	54	DECLARE_READ8_MEMBER(read_unk);
	55	DECLARE_WRITE8_MEMBER(vrambank_w);
	56	DECLARE_READ8_MEMBER(protram_r);
	57	DECLARE_WRITE8_MEMBER(protram_w);
52	58	};
53	59
54	60
r14845	r14846
81	87	return 0;
82	88	}
83	89
84		static READ8_HANDLER(vram_r)
	90	READ8_MEMBER(laserbas_state::vram_r)
85	91	{
86		laserbas_state *state = space->machine().driver_data<laserbas_state>();
87	92
88		if(!state->m_vrambank)
89		return state->m_vram1[offset];
	93	if(!m_vrambank)
	94	return m_vram1[offset];
90	95	else
91		return state->m_vram2[offset];
	96	return m_vram2[offset];
92	97	}
93	98
94		static WRITE8_HANDLER(vram_w)
	99	WRITE8_MEMBER(laserbas_state::vram_w)
95	100	{
96		laserbas_state *state = space->machine().driver_data<laserbas_state>();
97	101
98		if(!state->m_vrambank)
99		state->m_vram1[offset] = data;
	102	if(!m_vrambank)
	103	m_vram1[offset] = data;
100	104	else
101		state->m_vram2[offset] = data;
	105	m_vram2[offset] = data;
102	106	}
103	107
104	108	#if 0
105		static READ8_HANDLER( read_unk )
	109	READ8_MEMBER(laserbas_state::read_unk)
106	110	{
107		laserbas_state *state = space->machine().driver_data<laserbas_state>();
108	111
109		state->m_count ^= 0x80;
110		return state->m_count | 0x7f;
	112	m_count ^= 0x80;
	113	return m_count | 0x7f;
111	114	}
112	115	#endif
113	116
114		static WRITE8_HANDLER(vrambank_w)
	117	WRITE8_MEMBER(laserbas_state::vrambank_w)
115	118	{
116		laserbas_state *state = space->machine().driver_data<laserbas_state>();
117	119
118	120	/* either bit 2 or 3 controls flip screen */
119	121
120		state->m_vrambank = data & 0x40;
	122	m_vrambank = data & 0x40;
121	123	}
122	124
123		static READ8_HANDLER( protram_r )
	125	READ8_MEMBER(laserbas_state::protram_r)
124	126	{
125		laserbas_state *state = space->machine().driver_data<laserbas_state>();
126	127
127		return state->m_protram[offset];
	128	return m_protram[offset];
128	129	}
129	130
130		static WRITE8_HANDLER( protram_w )
	131	WRITE8_MEMBER(laserbas_state::protram_w)
131	132	{
132		laserbas_state *state = space->machine().driver_data<laserbas_state>();
133	133
134		state->m_protram[offset] = data;
	134	m_protram[offset] = data;
135	135	}
136	136
137	137	static ADDRESS_MAP_START( laserbas_memory, AS_PROGRAM, 8, laserbas_state )
138	138	//ADDRESS_MAP_UNMAP_HIGH
139	139	AM_RANGE(0x0000, 0x3fff) AM_ROM
140		AM_RANGE(0x4000, 0xbfff) AM_READWRITE_LEGACY(vram_r, vram_w)
	140	AM_RANGE(0x4000, 0xbfff) AM_READWRITE(vram_r, vram_w)
141	141	AM_RANGE(0xc000, 0xf7ff) AM_ROM
142		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(protram_r, protram_w) AM_BASE(m_protram) /* protection device */
	142	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(protram_r, protram_w) AM_BASE(m_protram) /* protection device */
143	143	AM_RANGE(0xfc00, 0xffff) AM_RAM
144	144	ADDRESS_MAP_END
145	145
r14845	r14846
147	147	ADDRESS_MAP_GLOBAL_MASK(0xff)
148	148	AM_RANGE(0x00, 0x00) AM_DEVWRITE("crtc", mc6845_device, address_w)
149	149	AM_RANGE(0x01, 0x01) AM_DEVWRITE("crtc", mc6845_device, register_w)
150		AM_RANGE(0x10, 0x10) AM_WRITE_LEGACY(vrambank_w)
	150	AM_RANGE(0x10, 0x10) AM_WRITE(vrambank_w)
151	151	AM_RANGE(0x20, 0x20) AM_READ_PORT("IN1") // DSW + something else?
152	152	AM_RANGE(0x21, 0x21) AM_READ_PORT("IN0")
153	153	AM_RANGE(0x22, 0x22) AM_READ_PORT("IN2")

src/mame/drivers/kingpin.c

r14845	r14846
33	33	: driver_device(mconfig, type, tag) { }
34	34
35	35	UINT8 *m_code_base;
	36	DECLARE_READ8_MEMBER(io_read_missing_dips);
36	37	};
37	38
38	39
39		static READ8_HANDLER( io_read_missing_dips )
	40	READ8_MEMBER(kingpin_state::io_read_missing_dips)
40	41	{
41	42	return 0x00;
42	43	}
r14845	r14846
106	107
107	108	static ADDRESS_MAP_START( kingpin_io_map, AS_IO, 8, kingpin_state )
108	109	ADDRESS_MAP_GLOBAL_MASK(0xff)
109		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(io_read_missing_dips)
	110	AM_RANGE(0x00, 0x00) AM_READ(io_read_missing_dips)
110	111	AM_RANGE(0x01, 0x01) AM_READ_PORT("DSW")
111		/*  AM_RANGE(0x02, 0x02) AM_READ_LEGACY(io_read_missing_dips) */
	112	/*  AM_RANGE(0x02, 0x02) AM_READ(io_read_missing_dips) */
112	113	/*  AM_RANGE(0x02, 0x02) AM_WRITE_LEGACY(NO IDEA) */
113	114	AM_RANGE(0x10, 0x10) AM_READ_PORT("IN0")
114	115	AM_RANGE(0x11, 0x11) AM_READ_PORT("IN1")

src/mame/drivers/taitopjc.c

r14845	r14846
71	71	taitopjc_state(const machine_config &mconfig, device_type type, const char *tag)
72	72	: driver_device(mconfig, type, tag)
73	73	{ }
	74	DECLARE_READ64_MEMBER(video_r);
	75	DECLARE_WRITE64_MEMBER(video_w);
	76	DECLARE_READ64_MEMBER(ppc_common_r);
	77	DECLARE_READ64_MEMBER(dsp_r);
	78	DECLARE_WRITE64_MEMBER(dsp_w);
	79	DECLARE_READ8_MEMBER(tlcs_common_r);
	80	DECLARE_WRITE8_MEMBER(tlcs_common_w);
	81	DECLARE_READ8_MEMBER(tlcs_sound_r);
	82	DECLARE_WRITE8_MEMBER(tlcs_sound_w);
74	83	};
75	84
76	85	static VIDEO_START( taitopjc )
r14845	r14846
157	166	}
158	167	}
159	168
160		static READ64_HANDLER(video_r)
	169	READ64_MEMBER(taitopjc_state::video_r)
161	170	{
162	171	UINT64 r = 0;
163	172
r14845	r14846
165	174	{
166	175	if (ACCESSING_BITS_32_63)
167	176	{
168		r |= (UINT64)(videochip_r(space, video_address)) << 32;
	177	r |= (UINT64)(videochip_r(&space, video_address)) << 32;
169	178	}
170	179	}
171	180
172	181	return r;
173	182	}
174	183
175		static WRITE64_HANDLER(video_w)
	184	WRITE64_MEMBER(taitopjc_state::video_w)
176	185	{
177	186	if (offset == 0)
178	187	{
179	188	if (ACCESSING_BITS_32_63)
180	189	{
181	190	//printf("Address %08X = %08X\n", video_address, (UINT32)(data >> 32));
182		videochip_w(space, video_address, (UINT32)(data >> 32));
	191	videochip_w(&space, video_address, (UINT32)(data >> 32));
183	192	}
184	193	}
185	194	if (offset == 1)
r14845	r14846
205	214	};
206	215	*/
207	216
208		static READ64_HANDLER(ppc_common_r)
	217	READ64_MEMBER(taitopjc_state::ppc_common_r)
209	218	{
210	219	UINT64 r = 0;
211	220	UINT32 address;
r14845	r14846
247	256
248	257	static UINT16 dsp_ram[0x1000];
249	258
250		static READ64_HANDLER(dsp_r)
	259	READ64_MEMBER(taitopjc_state::dsp_r)
251	260	{
252	261	UINT64 r = 0;
253	262
r14845	r14846
262	271	return r;
263	272	}
264	273
265		static WRITE64_HANDLER(dsp_w)
	274	WRITE64_MEMBER(taitopjc_state::dsp_w)
266	275	{
267	276	logerror("dsp_w: %08X, %08X%08X, %08X%08X\n", offset, (UINT32)(data >> 32), (UINT32)(data), (UINT32)(mem_mask >> 32), (UINT32)(mem_mask));
268	277
r14845	r14846
311	320
312	321	static ADDRESS_MAP_START( ppc603e_mem, AS_PROGRAM, 64, taitopjc_state )
313	322	AM_RANGE(0x00000000, 0x003fffff) AM_RAM // Work RAM
314		AM_RANGE(0x40000000, 0x4000000f) AM_READWRITE_LEGACY(video_r, video_w)
315		AM_RANGE(0x80000000, 0x80003fff) AM_READWRITE_LEGACY(dsp_r, dsp_w)
316		AM_RANGE(0xc0000000, 0xc000ffff) AM_READ_LEGACY(ppc_common_r)
	323	AM_RANGE(0x40000000, 0x4000000f) AM_READWRITE(video_r, video_w)
	324	AM_RANGE(0x80000000, 0x80003fff) AM_READWRITE(dsp_r, dsp_w)
	325	AM_RANGE(0xc0000000, 0xc000ffff) AM_READ(ppc_common_r)
317	326	AM_RANGE(0xff000000, 0xff01ffff) AM_ROM AM_REGION("user2", 0)
318	327	AM_RANGE(0xffe00000, 0xffffffff) AM_ROM AM_REGION("user1", 0)
319	328	ADDRESS_MAP_END
r14845	r14846
321	330
322	331
323	332
324		static READ8_HANDLER(tlcs_common_r)
	333	READ8_MEMBER(taitopjc_state::tlcs_common_r)
325	334	{
326	335	return common_ram[offset];
327	336	}
328	337
329		static WRITE8_HANDLER(tlcs_common_w)
	338	WRITE8_MEMBER(taitopjc_state::tlcs_common_w)
330	339	{
331	340	//  printf("tlcs_common_w: %08X, %02X\n", offset, data);
332	341
333	342	common_ram[offset] = data;
334	343	}
335	344
336		static READ8_HANDLER(tlcs_sound_r)
	345	READ8_MEMBER(taitopjc_state::tlcs_sound_r)
337	346	{
338	347	if (offset == 0x17)
339	348	{
r14845	r14846
343	352	return 0;
344	353	}
345	354
346		static WRITE8_HANDLER(tlcs_sound_w)
	355	WRITE8_MEMBER(taitopjc_state::tlcs_sound_w)
347	356	{
348	357	//  printf("tlcs_sound_w: %08X, %02X\n", offset, data);
349	358	}
r14845	r14846
367	376
368	377	static ADDRESS_MAP_START( tlcs900h_mem, AS_PROGRAM, 8, taitopjc_state )
369	378	AM_RANGE(0x010000, 0x02ffff) AM_RAM      // Work RAM
370		AM_RANGE(0x040000, 0x0400ff) AM_READWRITE_LEGACY(tlcs_sound_r, tlcs_sound_w)
371		AM_RANGE(0x060000, 0x061fff) AM_READWRITE_LEGACY(tlcs_common_r, tlcs_common_w)
	379	AM_RANGE(0x040000, 0x0400ff) AM_READWRITE(tlcs_sound_r, tlcs_sound_w)
	380	AM_RANGE(0x060000, 0x061fff) AM_READWRITE(tlcs_common_r, tlcs_common_w)
372	381	AM_RANGE(0xfc0000, 0xffffff) AM_ROM AM_REGION("io_cpu", 0)
373	382	ADDRESS_MAP_END
374	383

src/mame/drivers/clayshoo.c

r14845	r14846
31	31	emu_timer *m_analog_timer_1, *m_analog_timer_2;
32	32	UINT8 m_input_port_select;
33	33	UINT8 m_analog_port_val;
	34	DECLARE_WRITE8_MEMBER(analog_reset_w);
	35	DECLARE_READ8_MEMBER(analog_r);
34	36	};
35	37
36	38
r14845	r14846
107	109	}
108	110
109	111
110		static WRITE8_HANDLER( analog_reset_w )
	112	WRITE8_MEMBER(clayshoo_state::analog_reset_w)
111	113	{
112		clayshoo_state *state = space->machine().driver_data<clayshoo_state>();
113	114
114	115	/* reset the analog value, and start the two times that will fire
115	116	off in a short period proportional to the position of the
116	117	analog control and set the appropriate bit. */
117	118
118		state->m_analog_port_val = 0xff;
	119	m_analog_port_val = 0xff;
119	120
120		state->m_analog_timer_1->adjust(compute_duration(&space->device(), input_port_read(space->machine(), "AN1")), 0x02);
121		state->m_analog_timer_2->adjust(compute_duration(&space->device(), input_port_read(space->machine(), "AN2")), 0x01);
	121	m_analog_timer_1->adjust(compute_duration(&space.device(), input_port_read(machine(), "AN1")), 0x02);
	122	m_analog_timer_2->adjust(compute_duration(&space.device(), input_port_read(machine(), "AN2")), 0x01);
122	123	}
123	124
124	125
125		static READ8_HANDLER( analog_r )
	126	READ8_MEMBER(clayshoo_state::analog_r)
126	127	{
127		clayshoo_state *state = space->machine().driver_data<clayshoo_state>();
128		return state->m_analog_port_val;
	128	return m_analog_port_val;
129	129	}
130	130
131	131
r14845	r14846
222	222	AM_RANGE(0x4000, 0x47ff) AM_ROM
223	223	AM_RANGE(0x8000, 0x97ff) AM_RAM AM_BASE_SIZE(m_videoram, m_videoram_size)   /* 6k of video ram according to readme */
224	224	AM_RANGE(0x9800, 0xa800) AM_WRITENOP     /* not really mapped, but cleared */
225		AM_RANGE(0xc800, 0xc800) AM_READWRITE_LEGACY(analog_r, analog_reset_w)
	225	AM_RANGE(0xc800, 0xc800) AM_READWRITE(analog_r, analog_reset_w)
226	226	ADDRESS_MAP_END
227	227
228	228

src/mame/drivers/ghosteo.c

r14845	r14846
84	84	int m_security_count;
85	85	UINT32 m_bballoon_port[20];
86	86	struct nand_t m_nand;
	87	DECLARE_WRITE32_MEMBER(sound_w);
	88	DECLARE_READ32_MEMBER(bballoon_speedup_r);
87	89	};
88	90
89	91
r14845	r14846
329	331	i2cmem_sda_write( i2cmem, state);
330	332	}
331	333
332		static WRITE32_HANDLER( sound_w )
	334	WRITE32_MEMBER(ghosteo_state::sound_w)
333	335	{
334	336	if ((data >= 0x20) && (data <= 0x7F))
335	337	{
r14845	r14846
349	351	AM_RANGE(0x10000000, 0x10000003) AM_READ_PORT("10000000")
350	352	AM_RANGE(0x10100000, 0x10100003) AM_READ_PORT("10100000")
351	353	AM_RANGE(0x10200000, 0x10200003) AM_READ_PORT("10200000")
352		AM_RANGE(0x10300000, 0x10300003) AM_WRITE_LEGACY(sound_w)
	354	AM_RANGE(0x10300000, 0x10300003) AM_WRITE(sound_w)
353	355	AM_RANGE(0x30000000, 0x31ffffff) AM_RAM AM_BASE(m_system_memory) AM_MIRROR(0x02000000)
354	356	ADDRESS_MAP_END
355	357
r14845	r14846
435	437
436	438	device_t* s3c2410;
437	439
438		static READ32_HANDLER( bballoon_speedup_r )
	440	READ32_MEMBER(ghosteo_state::bballoon_speedup_r)
439	441	{
440	442	UINT32 ret = s3c2410_lcd_r(s3c2410, offset+0x10/4, mem_mask);
441	443
442	444
443		int pc = cpu_get_pc(&space->device());
	445	int pc = cpu_get_pc(&space.device());
444	446
445	447	// these are vblank waits
446	448	if (pc == 0x3001c0e4 || pc == 0x3001c0d8)
447	449	{
448	450	// BnB Arcade
449		device_spin_until_time(&space->device(), attotime::from_usec(20));
	451	device_spin_until_time(&space.device(), attotime::from_usec(20));
450	452	}
451	453	else if (pc == 0x3002b580 || pc == 0x3002b550)
452	454	{
453	455	// Happy Tour
454		device_spin_until_time(&space->device(), attotime::from_usec(20));
	456	device_spin_until_time(&space.device(), attotime::from_usec(20));
455	457	}
456	458	//else
457	459	//  printf("speedup %08x %08x\n", pc, ret);
r14845	r14846
461	463
462	464	static MACHINE_RESET( bballoon )
463	465	{
464		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x4d000010, 0x4d000013, FUNC(bballoon_speedup_r));
	466	ghosteo_state *state = machine.driver_data<ghosteo_state>();
	467	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x4d000010, 0x4d000013,read32_delegate(FUNC(ghosteo_state::bballoon_speedup_r), state));
465	468	s3c2410 = machine.device("s3c2410");
466	469	}
467	470

src/mame/drivers/dunhuang.c

r14845	r14846
93	93	UINT8          m_colorram[0x40 * 0x20];
94	94	UINT8          m_colorram2[0x40 * 0x8];
95	95	UINT8          m_paldata[3 * 256];
	96	DECLARE_WRITE8_MEMBER(dunhuang_pos_x_w);
	97	DECLARE_WRITE8_MEMBER(dunhuang_pos_y_w);
	98	DECLARE_WRITE8_MEMBER(dunhuang_tile_w);
	99	DECLARE_WRITE8_MEMBER(dunhuang_tile2_w);
	100	DECLARE_WRITE8_MEMBER(dunhuang_clear_y_w);
	101	DECLARE_WRITE8_MEMBER(dunhuang_horiz_clear_w);
	102	DECLARE_WRITE8_MEMBER(dunhuang_vert_clear_w);
	103	DECLARE_WRITE8_MEMBER(dunhuang_block_dest_w);
	104	DECLARE_WRITE8_MEMBER(dunhuang_block_x_w);
	105	DECLARE_WRITE8_MEMBER(dunhuang_block_y_w);
	106	DECLARE_WRITE8_MEMBER(dunhuang_block_w_w);
	107	DECLARE_WRITE8_MEMBER(dunhuang_block_c_w);
	108	DECLARE_WRITE8_MEMBER(dunhuang_block_addr_lo_w);
	109	DECLARE_WRITE8_MEMBER(dunhuang_block_addr_hi_w);
	110	DECLARE_WRITE8_MEMBER(dunhuang_block_h_w);
	111	DECLARE_WRITE8_MEMBER(dunhuang_paloffs_w);
	112	DECLARE_WRITE8_MEMBER(dunhuang_paldata_w);
	113	DECLARE_WRITE8_MEMBER(dunhuang_layers_w);
	114	DECLARE_WRITE8_MEMBER(dunhuang_input_w);
	115	DECLARE_READ8_MEMBER(dunhuang_service_r);
	116	DECLARE_READ8_MEMBER(dunhuang_input_r);
	117	DECLARE_WRITE8_MEMBER(dunhuang_rombank_w);
	118	DECLARE_WRITE8_MEMBER(dunhuang_82_w);
96	119	};
97	120
98	121
r14845	r14846
170	193
171	194	// Tilemaps access
172	195
173		static WRITE8_HANDLER( dunhuang_pos_x_w )
	196	WRITE8_MEMBER(dunhuang_state::dunhuang_pos_x_w)
174	197	{
175		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
176		state->m_pos_x = data & 0x3f;
177		state->m_written = 0;
178		state->m_written2 = 0;
	198	m_pos_x = data & 0x3f;
	199	m_written = 0;
	200	m_written2 = 0;
179	201	}
180	202
181		static WRITE8_HANDLER( dunhuang_pos_y_w )
	203	WRITE8_MEMBER(dunhuang_state::dunhuang_pos_y_w)
182	204	{
183		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
184		state->m_pos_y = data;
185		state->m_written = 0;
186		state->m_written2 = 0;
	205	m_pos_y = data;
	206	m_written = 0;
	207	m_written2 = 0;
187	208	}
188	209
189		static WRITE8_HANDLER( dunhuang_tile_w )
	210	WRITE8_MEMBER(dunhuang_state::dunhuang_tile_w)
190	211	{
191		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
192	212	int addr;
193	213
194		if (state->m_written & (1 << offset))
	214	if (m_written & (1 << offset))
195	215	{
196		state->m_written = 0;
197		state->m_pos_x++;
198		if (state->m_pos_x == 0x40)
	216	m_written = 0;
	217	m_pos_x++;
	218	if (m_pos_x == 0x40)
199	219	{
200		state->m_pos_x = 0;
201		state->m_pos_y++;
	220	m_pos_x = 0;
	221	m_pos_y++;
202	222	}
203	223	}
204		state->m_written |= 1 << offset;
	224	m_written |= 1 << offset;
205	225
206		addr = (state->m_pos_x & 0x3f) + (state->m_pos_y & 0x1f) * 0x40;
	226	addr = (m_pos_x & 0x3f) + (m_pos_y & 0x1f) * 0x40;
207	227	switch (offset)
208	228	{
209		case 0:   state->m_videoram[addr] = (state->m_videoram[addr] & 0xff00) | data;      break;
210		case 1:   state->m_videoram[addr] = (state->m_videoram[addr] & 0x00ff) | (data<<8);   break;
211		case 2:   state->m_colorram[addr] = data;                                    break;
	229	case 0:   m_videoram[addr] = (m_videoram[addr] & 0xff00) | data;      break;
	230	case 1:   m_videoram[addr] = (m_videoram[addr] & 0x00ff) | (data<<8);   break;
	231	case 2:   m_colorram[addr] = data;                                    break;
212	232	}
213		state->m_tmap->mark_tile_dirty(addr);
	233	m_tmap->mark_tile_dirty(addr);
214	234	}
215	235
216		static WRITE8_HANDLER( dunhuang_tile2_w )
	236	WRITE8_MEMBER(dunhuang_state::dunhuang_tile2_w)
217	237	{
218		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
219	238	int addr;
220	239
221		if (state->m_written2 & (1 << offset))
	240	if (m_written2 & (1 << offset))
222	241	{
223		state->m_written2 = 0;
224		state->m_pos_x++;
225		if (state->m_pos_x == 0x40)
	242	m_written2 = 0;
	243	m_pos_x++;
	244	if (m_pos_x == 0x40)
226	245	{
227		state->m_pos_x = 0;
228		state->m_pos_y++;
	246	m_pos_x = 0;
	247	m_pos_y++;
229	248	}
230	249	}
231		state->m_written2 |= 1 << offset;
	250	m_written2 |= 1 << offset;
232	251
233		addr = (state->m_pos_x & 0x3f) + (state->m_pos_y & 0x07) * 0x40;
	252	addr = (m_pos_x & 0x3f) + (m_pos_y & 0x07) * 0x40;
234	253	switch (offset)
235	254	{
236		case 0:   state->m_videoram2[addr] = (state->m_videoram2[addr] & 0xff00) | data;      break;
237		case 1:   state->m_videoram2[addr] = (state->m_videoram2[addr] & 0x00ff) | (data<<8);   break;
238		case 2:   state->m_colorram2[addr] = data;                                 break;
	255	case 0:   m_videoram2[addr] = (m_videoram2[addr] & 0xff00) | data;      break;
	256	case 1:   m_videoram2[addr] = (m_videoram2[addr] & 0x00ff) | (data<<8);   break;
	257	case 2:   m_colorram2[addr] = data;                                 break;
239	258	}
240		state->m_tmap2->mark_tile_dirty(addr);
	259	m_tmap2->mark_tile_dirty(addr);
241	260	}
242	261
243	262	// Clear a row of tiles (videoram)
244	263
245		static WRITE8_HANDLER( dunhuang_clear_y_w )
	264	WRITE8_MEMBER(dunhuang_state::dunhuang_clear_y_w)
246	265	{
247		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
248		state->m_clear_y = data;
	266	m_clear_y = data;
249	267	}
250		static WRITE8_HANDLER( dunhuang_horiz_clear_w )
	268	WRITE8_MEMBER(dunhuang_state::dunhuang_horiz_clear_w)
251	269	{
252		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
253	270	int i;
254		//  logerror("%06x: horiz clear, y = %02x, data = %02d\n", cpu_get_pc(&space->device()), state->m_clear_y,data);
	271	//  logerror("%06x: horiz clear, y = %02x, data = %02d\n", cpu_get_pc(&space.device()), m_clear_y,data);
255	272	for (i = 0; i < 0x40; i++)
256	273	{
257		int addr = state->m_clear_y * 0x40 + i;
	274	int addr = m_clear_y * 0x40 + i;
258	275
259		state->m_videoram[addr] = 0;
260		state->m_colorram[addr] = 0;
261		state->m_tmap->mark_tile_dirty(addr);
	276	m_videoram[addr] = 0;
	277	m_colorram[addr] = 0;
	278	m_tmap->mark_tile_dirty(addr);
262	279	}
263	280	}
264	281
265	282	// Clear a column of tiles (videoram2)
266	283
267		static WRITE8_HANDLER( dunhuang_vert_clear_w )
	284	WRITE8_MEMBER(dunhuang_state::dunhuang_vert_clear_w)
268	285	{
269		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
270	286	int i;
271		//  logerror("%06x: vert clear, x = %02x, y = %02x, data = %02x\n", cpu_get_pc(&space->device()), state->m_pos_x,state->m_pos_y,data);
	287	//  logerror("%06x: vert clear, x = %02x, y = %02x, data = %02x\n", cpu_get_pc(&space.device()), m_pos_x,m_pos_y,data);
272	288	for (i = 0; i < 0x08; i++)
273	289	{
274		int addr = (state->m_pos_x & 0x3f) + (i & 0x07) * 0x40;
	290	int addr = (m_pos_x & 0x3f) + (i & 0x07) * 0x40;
275	291
276		state->m_videoram2[addr] = 1;
277		state->m_colorram2[addr] = 0;
278		state->m_tmap2->mark_tile_dirty(addr);
	292	m_videoram2[addr] = 1;
	293	m_colorram2[addr] = 0;
	294	m_tmap2->mark_tile_dirty(addr);
279	295	}
280	296	}
281	297
r14845	r14846
285	301	// The tiles codes are read from the graphics roms too!
286	302	//
287	303
288		static WRITE8_HANDLER( dunhuang_block_dest_w )
	304	WRITE8_MEMBER(dunhuang_state::dunhuang_block_dest_w)
289	305	{
290		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
291		state->m_block_dest = data;
	306	m_block_dest = data;
292	307	}
293	308
294		static WRITE8_HANDLER( dunhuang_block_x_w )
	309	WRITE8_MEMBER(dunhuang_state::dunhuang_block_x_w)
295	310	{
296		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
297		state->m_block_x = data;
	311	m_block_x = data;
298	312	}
299	313
300		static WRITE8_HANDLER( dunhuang_block_y_w )
	314	WRITE8_MEMBER(dunhuang_state::dunhuang_block_y_w)
301	315	{
302		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
303		state->m_block_y = data;
	316	m_block_y = data;
304	317	}
305	318
306		static WRITE8_HANDLER( dunhuang_block_w_w )
	319	WRITE8_MEMBER(dunhuang_state::dunhuang_block_w_w)
307	320	{
308		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
309		state->m_block_w = data;
	321	m_block_w = data;
310	322	}
311	323
312		static WRITE8_HANDLER( dunhuang_block_c_w )
	324	WRITE8_MEMBER(dunhuang_state::dunhuang_block_c_w)
313	325	{
314		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
315		state->m_block_c = data;
	326	m_block_c = data;
316	327	}
317	328
318		static WRITE8_HANDLER( dunhuang_block_addr_lo_w )
	329	WRITE8_MEMBER(dunhuang_state::dunhuang_block_addr_lo_w)
319	330	{
320		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
321		state->m_block_addr_lo = data;
	331	m_block_addr_lo = data;
322	332	}
323	333
324		static WRITE8_HANDLER( dunhuang_block_addr_hi_w )
	334	WRITE8_MEMBER(dunhuang_state::dunhuang_block_addr_hi_w)
325	335	{
326		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
327		state->m_block_addr_hi = data;
	336	m_block_addr_hi = data;
328	337	}
329	338
330	339
331		static WRITE8_HANDLER( dunhuang_block_h_w )
	340	WRITE8_MEMBER(dunhuang_state::dunhuang_block_h_w)
332	341	{
333		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
334	342	int i,j, addr;
335	343	UINT8 *tile_addr;
336	344
337		//  logerror("%06x: block dst %x, src %x, xy %x %x, wh %x %x, clr %x\n", cpu_get_pc(&space->device()), state->m_block_dest, (state->m_block_addr_hi << 8) + state->m_block_addr_lo, state->m_block_x,state->m_block_y,state->m_block_w+1,state->m_block_h+1,state->m_block_c);
	345	//  logerror("%06x: block dst %x, src %x, xy %x %x, wh %x %x, clr %x\n", cpu_get_pc(&space.device()), m_block_dest, (m_block_addr_hi << 8) + m_block_addr_lo, m_block_x,m_block_y,m_block_w+1,m_block_h+1,m_block_c);
338	346
339		state->m_block_h = data;
	347	m_block_h = data;
340	348
341		tile_addr = space->machine().region("gfx2")->base() + ((state->m_block_addr_hi << 8) + state->m_block_addr_lo) * 4;
	349	tile_addr = machine().region("gfx2")->base() + ((m_block_addr_hi << 8) + m_block_addr_lo) * 4;
342	350
343		switch (state->m_block_dest)
	351	switch (m_block_dest)
344	352	{
345	353	case 0x04:   // write to videoram
346		for (j = 0; j <= state->m_block_h; j++)
	354	for (j = 0; j <= m_block_h; j++)
347	355	{
348		for (i = 0; i <= state->m_block_w; i++)
	356	for (i = 0; i <= m_block_w; i++)
349	357	{
350		addr = ((state->m_block_x + i)& 0x3f) + ((state->m_block_y + j) & 0x1f) * 0x40;
	358	addr = ((m_block_x + i)& 0x3f) + ((m_block_y + j) & 0x1f) * 0x40;
351	359
352		state->m_videoram[addr] = (tile_addr[1] << 8) | tile_addr[0];
353		state->m_colorram[addr] = state->m_block_c;
354		state->m_tmap->mark_tile_dirty(addr);
	360	m_videoram[addr] = (tile_addr[1] << 8) | tile_addr[0];
	361	m_colorram[addr] = m_block_c;
	362	m_tmap->mark_tile_dirty(addr);
355	363	tile_addr += 4;
356	364	}
357	365	}
358	366	break;
359	367
360	368	case 0x08:   // write to videoram2
361		for (j = 0; j <= state->m_block_h; j++)
	369	for (j = 0; j <= m_block_h; j++)
362	370	{
363		for (i = 0; i <= state->m_block_w; i++)
	371	for (i = 0; i <= m_block_w; i++)
364	372	{
365		addr = ((state->m_block_x + i)& 0x3f) + ((state->m_block_y + j) & 0x7) * 0x40;
	373	addr = ((m_block_x + i)& 0x3f) + ((m_block_y + j) & 0x7) * 0x40;
366	374
367		state->m_videoram2[addr] = (tile_addr[1] << 8) | tile_addr[0];
368		state->m_colorram2[addr] = state->m_block_c;
369		state->m_tmap2->mark_tile_dirty(addr);
	375	m_videoram2[addr] = (tile_addr[1] << 8) | tile_addr[0];
	376	m_colorram2[addr] = m_block_c;
	377	m_tmap2->mark_tile_dirty(addr);
370	378	tile_addr += 4;
371	379	}
372	380	}
373	381	break;
374	382
375	383	default:
376		popmessage("%06x: block dst=%x", cpu_get_pc(&space->device()), state->m_block_dest);
	384	popmessage("%06x: block dst=%x", cpu_get_pc(&space.device()), m_block_dest);
377	385	}
378	386	}
379	387
380	388	// Palette: HMC HM86171 VGA 256 colour RAMDAC
381	389
382		static WRITE8_HANDLER( dunhuang_paloffs_w )
	390	WRITE8_MEMBER(dunhuang_state::dunhuang_paloffs_w)
383	391	{
384		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
385		state->m_paloffs = data * 3;
	392	m_paloffs = data * 3;
386	393	}
387	394
388		static WRITE8_HANDLER( dunhuang_paldata_w )
	395	WRITE8_MEMBER(dunhuang_state::dunhuang_paldata_w)
389	396	{
390		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
391		state->m_paldata[state->m_paloffs] = data;
	397	m_paldata[m_paloffs] = data;
392	398
393		palette_set_color_rgb( space->machine(), state->m_paloffs/3,
394		pal6bit(state->m_paldata[(state->m_paloffs/3)*3+0]),
395		pal6bit(state->m_paldata[(state->m_paloffs/3)*3+1]),
396		pal6bit(state->m_paldata[(state->m_paloffs/3)*3+2])
	399	palette_set_color_rgb( machine(), m_paloffs/3,
	400	pal6bit(m_paldata[(m_paloffs/3)*3+0]),
	401	pal6bit(m_paldata[(m_paloffs/3)*3+1]),
	402	pal6bit(m_paldata[(m_paloffs/3)*3+2])
397	403	);
398	404
399		state->m_paloffs = (state->m_paloffs + 1) % (3*256);
	405	m_paloffs = (m_paloffs + 1) % (3*256);
400	406	}
401	407
402	408	// Layers control (not understood)
403	409
404		static WRITE8_HANDLER( dunhuang_layers_w )
	410	WRITE8_MEMBER(dunhuang_state::dunhuang_layers_w)
405	411	{
406		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
407	412	//  popmessage("layers %02x",data);
408		state->m_layers = data;
	413	m_layers = data;
409	414	}
410	415
411	416	/***************************************************************************
r14845	r14846
420	425
421	426	// Inputs
422	427
423		static WRITE8_HANDLER( dunhuang_input_w )
	428	WRITE8_MEMBER(dunhuang_state::dunhuang_input_w)
424	429	{
425		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
426		state->m_input = data;
	430	m_input = data;
427	431	}
428	432
429		static READ8_HANDLER( dunhuang_service_r )
	433	READ8_MEMBER(dunhuang_state::dunhuang_service_r)
430	434	{
431		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
432		return input_port_read(space->machine(), "SERVICE")
433		| ((state->m_hopper && !(space->machine().primary_screen->frame_number() % 10)) ? 0x00 : 0x08)   // bit 3: hopper sensor
	435	return input_port_read(machine(), "SERVICE")
	436	| ((m_hopper && !(machine().primary_screen->frame_number() % 10)) ? 0x00 : 0x08)   // bit 3: hopper sensor
434	437	| 0x80                                                // bit 7 low -> tiles block transferrer busy
435	438	;
436	439	}
r14845	r14846
446	449	logerror("%s: warning, unknown dsw bits read, input = %02x\n", device->machine().describe_context(), state->m_input);
447	450	return 0xff;
448	451	}
449		static READ8_HANDLER( dunhuang_input_r )
	452	READ8_MEMBER(dunhuang_state::dunhuang_input_r)
450	453	{
451		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
452		if (!(state->m_input & 0x01))   return input_port_read(space->machine(), "IN0");
453		if (!(state->m_input & 0x02))   return input_port_read(space->machine(), "IN1");
454		if (!(state->m_input & 0x04))   return input_port_read(space->machine(), "IN2");
455		if (!(state->m_input & 0x08))   return input_port_read(space->machine(), "IN3");
456		if (!(state->m_input & 0x10))   return input_port_read(space->machine(), "IN4");
457		logerror("%s: warning, unknown input bits read, input = %02x\n", space->machine().describe_context(), state->m_input);
	454	if (!(m_input & 0x01))   return input_port_read(machine(), "IN0");
	455	if (!(m_input & 0x02))   return input_port_read(machine(), "IN1");
	456	if (!(m_input & 0x04))   return input_port_read(machine(), "IN2");
	457	if (!(m_input & 0x08))   return input_port_read(machine(), "IN3");
	458	if (!(m_input & 0x10))   return input_port_read(machine(), "IN4");
	459	logerror("%s: warning, unknown input bits read, input = %02x\n", machine().describe_context(), m_input);
458	460	return 0xff;
459	461	}
460	462
461		static WRITE8_HANDLER( dunhuang_rombank_w )
	463	WRITE8_MEMBER(dunhuang_state::dunhuang_rombank_w)
462	464	{
463		dunhuang_state *state = space->machine().driver_data<dunhuang_state>();
464	465
465	466	// ?                data & 0x01
466	467	// ?                data & 0x02
467	468
468		memory_set_bank(space->machine(), "bank1", ((data >> 2) & 0x7));
	469	memory_set_bank(machine(), "bank1", ((data >> 2) & 0x7));
469	470
470	471	// COIN OUT:        data & 0x20
471		coin_counter_w(space->machine(), 0,   data & 0x40);
472		state->m_hopper = data & 0x80;
	472	coin_counter_w(machine(), 0,   data & 0x40);
	473	m_hopper = data & 0x80;
473	474	}
474	475
475	476
476	477	#ifdef UNUSED_FUNCTION
477		static WRITE8_HANDLER( dunhuang_82_w )
	478	WRITE8_MEMBER(dunhuang_state::dunhuang_82_w)
478	479	{
479	480	//  popmessage("82 = %02x",dunhuang_82);
480	481	}
481	482	#endif
482	483
483	484	static ADDRESS_MAP_START( dunhuang_io_map, AS_IO, 8, dunhuang_state )
484		AM_RANGE( 0x0000, 0x0000 ) AM_WRITE_LEGACY(dunhuang_pos_x_w )
485		AM_RANGE( 0x0001, 0x0001 ) AM_WRITE_LEGACY(dunhuang_pos_y_w )
486		AM_RANGE( 0x0002, 0x0004 ) AM_WRITE_LEGACY(dunhuang_tile_w )
487		AM_RANGE( 0x0005, 0x0007 ) AM_WRITE_LEGACY(dunhuang_tile2_w )
	485	AM_RANGE( 0x0000, 0x0000 ) AM_WRITE(dunhuang_pos_x_w )
	486	AM_RANGE( 0x0001, 0x0001 ) AM_WRITE(dunhuang_pos_y_w )
	487	AM_RANGE( 0x0002, 0x0004 ) AM_WRITE(dunhuang_tile_w )
	488	AM_RANGE( 0x0005, 0x0007 ) AM_WRITE(dunhuang_tile2_w )
488	489
489		AM_RANGE( 0x0008, 0x0008 ) AM_WRITE_LEGACY(dunhuang_vert_clear_w )
	490	AM_RANGE( 0x0008, 0x0008 ) AM_WRITE(dunhuang_vert_clear_w )
490	491
491	492	AM_RANGE( 0x000c, 0x000c ) AM_READ_LEGACY(watchdog_reset_r )
492	493
493		AM_RANGE( 0x000f, 0x000f ) AM_WRITE_LEGACY(dunhuang_block_addr_lo_w )
494		AM_RANGE( 0x0010, 0x0010 ) AM_WRITE_LEGACY(dunhuang_block_addr_hi_w )
	494	AM_RANGE( 0x000f, 0x000f ) AM_WRITE(dunhuang_block_addr_lo_w )
	495	AM_RANGE( 0x0010, 0x0010 ) AM_WRITE(dunhuang_block_addr_hi_w )
495	496	//  AM_RANGE( 0x0011, 0x0011 ) ?
496		AM_RANGE( 0x0012, 0x0012 ) AM_WRITE_LEGACY(dunhuang_block_c_w )
497		AM_RANGE( 0x0015, 0x0015 ) AM_WRITE_LEGACY(dunhuang_block_x_w )
498		AM_RANGE( 0x0016, 0x0016 ) AM_WRITE_LEGACY(dunhuang_block_y_w )
499		AM_RANGE( 0x0017, 0x0017 ) AM_WRITE_LEGACY(dunhuang_block_w_w )
500		AM_RANGE( 0x0018, 0x0018 ) AM_WRITE_LEGACY(dunhuang_block_h_w )
	497	AM_RANGE( 0x0012, 0x0012 ) AM_WRITE(dunhuang_block_c_w )
	498	AM_RANGE( 0x0015, 0x0015 ) AM_WRITE(dunhuang_block_x_w )
	499	AM_RANGE( 0x0016, 0x0016 ) AM_WRITE(dunhuang_block_y_w )
	500	AM_RANGE( 0x0017, 0x0017 ) AM_WRITE(dunhuang_block_w_w )
	501	AM_RANGE( 0x0018, 0x0018 ) AM_WRITE(dunhuang_block_h_w )
501	502
502		AM_RANGE( 0x0019, 0x0019 ) AM_WRITE_LEGACY(dunhuang_clear_y_w )
503		AM_RANGE( 0x001a, 0x001a ) AM_WRITE_LEGACY(dunhuang_horiz_clear_w )
	503	AM_RANGE( 0x0019, 0x0019 ) AM_WRITE(dunhuang_clear_y_w )
	504	AM_RANGE( 0x001a, 0x001a ) AM_WRITE(dunhuang_horiz_clear_w )
504	505
505		AM_RANGE( 0x001b, 0x001b ) AM_WRITE_LEGACY(dunhuang_block_dest_w )
	506	AM_RANGE( 0x001b, 0x001b ) AM_WRITE(dunhuang_block_dest_w )
506	507
507	508	AM_RANGE( 0x0081, 0x0081 ) AM_DEVWRITE_LEGACY("ymsnd", ym2413_register_port_w   )
508	509	AM_RANGE( 0x0089, 0x0089 ) AM_DEVWRITE_LEGACY("ymsnd", ym2413_data_port_w      )
509	510
510		//  AM_RANGE( 0x0082, 0x0082 ) AM_WRITE_LEGACY(dunhuang_82_w )
	511	//  AM_RANGE( 0x0082, 0x0082 ) AM_WRITE(dunhuang_82_w )
511	512
512		AM_RANGE( 0x0083, 0x0083 ) AM_WRITE_LEGACY(dunhuang_paloffs_w )
513		AM_RANGE( 0x008b, 0x008b ) AM_WRITE_LEGACY(dunhuang_paldata_w )
	513	AM_RANGE( 0x0083, 0x0083 ) AM_WRITE(dunhuang_paloffs_w )
	514	AM_RANGE( 0x008b, 0x008b ) AM_WRITE(dunhuang_paldata_w )
514	515
515		AM_RANGE( 0x0084, 0x0084 ) AM_READ_LEGACY(dunhuang_service_r )
516		AM_RANGE( 0x0085, 0x0085 ) AM_READ_LEGACY(dunhuang_input_r )
	516	AM_RANGE( 0x0084, 0x0084 ) AM_READ(dunhuang_service_r )
	517	AM_RANGE( 0x0085, 0x0085 ) AM_READ(dunhuang_input_r )
517	518
518		AM_RANGE( 0x0086, 0x0086 ) AM_WRITE_LEGACY(dunhuang_rombank_w )
519		AM_RANGE( 0x0087, 0x0087 ) AM_WRITE_LEGACY(dunhuang_layers_w )
	519	AM_RANGE( 0x0086, 0x0086 ) AM_WRITE(dunhuang_rombank_w )
	520	AM_RANGE( 0x0087, 0x0087 ) AM_WRITE(dunhuang_layers_w )
520	521
521	522	AM_RANGE( 0x0088, 0x0088 ) AM_DEVREAD_LEGACY("ay8910", ay8910_r )
522	523	AM_RANGE( 0x0090, 0x0090 ) AM_DEVWRITE_LEGACY("ay8910", ay8910_data_w )
r14845	r14846
757	758	AY8910_DEFAULT_LOADS,
758	759	//  A                   B
759	760	DEVCB_NULL,                     DEVCB_HANDLER(dunhuang_dsw_r),   // R
760		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, dunhuang_input_w),   DEVCB_NULL                  // W
	761	DEVCB_DRIVER_MEMBER(dunhuang_state, dunhuang_input_w),   DEVCB_NULL                  // W
761	762	};
762	763
763	764

src/mame/drivers/deco_ld.c

r14845	r14846
119	119	required_device<pioneer_ldv1000_device> m_laserdisc;
120	120	UINT8 m_laserdisc_data;
121	121	int m_nmimask;
	122	DECLARE_WRITE8_MEMBER(rblaster_sound_w);
	123	DECLARE_WRITE8_MEMBER(rblaster_vram_bank_w);
	124	DECLARE_READ8_MEMBER(laserdisc_r);
	125	DECLARE_WRITE8_MEMBER(laserdisc_w);
	126	DECLARE_READ8_MEMBER(test_r);
	127	DECLARE_WRITE8_MEMBER(nmimask_w);
122	128	};
123	129
124	130
r14845	r14846
148	154	}
149	155
150	156	#if 0
151		static WRITE8_HANDLER( rblaster_sound_w )
	157	WRITE8_MEMBER(deco_ld_state::rblaster_sound_w)
152	158	{
153	159	soundlatch_w(space,0,data);
154		device_set_input_line(space->machine().cpu[1], 0, HOLD_LINE);
	160	device_set_input_line(machine().cpu[1], 0, HOLD_LINE);
155	161	}
156	162	#endif
157	163
158		static WRITE8_HANDLER( rblaster_vram_bank_w )
	164	WRITE8_MEMBER(deco_ld_state::rblaster_vram_bank_w)
159	165	{
160		deco_ld_state *state = space->machine().driver_data<deco_ld_state>();
161		state->m_vram_bank = data;
	166	m_vram_bank = data;
162	167	}
163	168
164		static READ8_HANDLER( laserdisc_r )
	169	READ8_MEMBER(deco_ld_state::laserdisc_r)
165	170	{
166		deco_ld_state *state = space->machine().driver_data<deco_ld_state>();
167		UINT8 result = state->m_laserdisc->status_r();
	171	UINT8 result = m_laserdisc->status_r();
168	172	//  mame_printf_debug("laserdisc_r = %02X\n", result);
169	173	return result;
170	174	}
171	175
172	176
173		static WRITE8_HANDLER( laserdisc_w )
	177	WRITE8_MEMBER(deco_ld_state::laserdisc_w)
174	178	{
175		deco_ld_state *state = space->machine().driver_data<deco_ld_state>();
176		state->m_laserdisc_data = data;
	179	m_laserdisc_data = data;
177	180	}
178	181
179		static READ8_HANDLER( test_r )
	182	READ8_MEMBER(deco_ld_state::test_r)
180	183	{
181		return space->machine().rand();
	184	return machine().rand();
182	185	}
183	186
184	187	static ADDRESS_MAP_START( begas_map, AS_PROGRAM, 8, deco_ld_state )
185	188	AM_RANGE(0x0000, 0x0fff) AM_RAM
186	189	//  AM_RANGE(0x1000, 0x1007) AM_NOP
187		AM_RANGE(0x1000, 0x1000) AM_READ_LEGACY(test_r)
188		AM_RANGE(0x1001, 0x1001) AM_READ_LEGACY(test_r)
189		AM_RANGE(0x1002, 0x1002) AM_READ_LEGACY(test_r)
190		AM_RANGE(0x1003, 0x1003) AM_READ_LEGACY(test_r)
	190	AM_RANGE(0x1000, 0x1000) AM_READ(test_r)
	191	AM_RANGE(0x1001, 0x1001) AM_READ(test_r)
	192	AM_RANGE(0x1002, 0x1002) AM_READ(test_r)
	193	AM_RANGE(0x1003, 0x1003) AM_READ(test_r)
191	194	AM_RANGE(0x1001, 0x1001) AM_WRITENOP //???
192	195	//  AM_RANGE(0x1003, 0x1003) AM_READ_PORT("IN0")
193		AM_RANGE(0x1003, 0x1003) AM_WRITE_LEGACY(rblaster_vram_bank_w) //might be 1001
	196	AM_RANGE(0x1003, 0x1003) AM_WRITE(rblaster_vram_bank_w) //might be 1001
194	197	AM_RANGE(0x1006, 0x1006) AM_NOP //ld status / command
195		AM_RANGE(0x1007, 0x1007) AM_READWRITE_LEGACY(laserdisc_r,laserdisc_w) // ld data
	198	AM_RANGE(0x1007, 0x1007) AM_READWRITE(laserdisc_r,laserdisc_w) // ld data
196	199	AM_RANGE(0x1800, 0x1fff) AM_RAM_WRITE_LEGACY(paletteram_RRRGGGBB_w) AM_BASE_GENERIC(paletteram)
197	200	AM_RANGE(0x2000, 0x27ff) AM_RAM
198	201	AM_RANGE(0x2800, 0x2fff) AM_RAM AM_BASE(m_videoram)
r14845	r14846
203	206	static ADDRESS_MAP_START( cobra_map, AS_PROGRAM, 8, deco_ld_state )
204	207	AM_RANGE(0x0000, 0x0fff) AM_RAM
205	208	AM_RANGE(0x1000, 0x1000) AM_READ_PORT("IN1")
206		AM_RANGE(0x1001, 0x1001) AM_READ_LEGACY(test_r)//_PORT("IN2")
207		AM_RANGE(0x1002, 0x1002) AM_READ_LEGACY(test_r)//_PORT("IN3")
208		AM_RANGE(0x1003, 0x1003) AM_READ_LEGACY(test_r)//AM_READ_PORT("IN0")
209		//  AM_RANGE(0x1004, 0x1004) AM_READ_LEGACY(test_r)//_PORT("IN4")
210		//  AM_RANGE(0x1005, 0x1005) AM_READ_LEGACY(test_r)//_PORT("IN5")
211		AM_RANGE(0x1004, 0x1004) AM_WRITE_LEGACY(rblaster_vram_bank_w) //might be 1001
	209	AM_RANGE(0x1001, 0x1001) AM_READ(test_r)//_PORT("IN2")
	210	AM_RANGE(0x1002, 0x1002) AM_READ(test_r)//_PORT("IN3")
	211	AM_RANGE(0x1003, 0x1003) AM_READ(test_r)//AM_READ_PORT("IN0")
	212	//  AM_RANGE(0x1004, 0x1004) AM_READ(test_r)//_PORT("IN4")
	213	//  AM_RANGE(0x1005, 0x1005) AM_READ(test_r)//_PORT("IN5")
	214	AM_RANGE(0x1004, 0x1004) AM_WRITE(rblaster_vram_bank_w) //might be 1001
212	215	AM_RANGE(0x1006, 0x1006) AM_NOP //ld status / command
213		AM_RANGE(0x1007, 0x1007) AM_READWRITE_LEGACY(laserdisc_r,laserdisc_w) // ld data
	216	AM_RANGE(0x1007, 0x1007) AM_READWRITE(laserdisc_r,laserdisc_w) // ld data
214	217	AM_RANGE(0x1800, 0x1fff) AM_RAM_WRITE_LEGACY(paletteram_RRRGGGBB_w) AM_BASE_GENERIC(paletteram)
215	218	AM_RANGE(0x2000, 0x2fff) AM_RAM
216	219	AM_RANGE(0x3000, 0x37ff) AM_RAM //vram attr?
r14845	r14846
224	227	//  AM_RANGE(0x1000, 0x1007) AM_NOP
225	228	AM_RANGE(0x1001, 0x1001) AM_WRITENOP //???
226	229	AM_RANGE(0x1003, 0x1003) AM_READ_PORT("IN0")
227		AM_RANGE(0x1003, 0x1003) AM_WRITE_LEGACY(rblaster_vram_bank_w) //might be 1001
	230	AM_RANGE(0x1003, 0x1003) AM_WRITE(rblaster_vram_bank_w) //might be 1001
228	231	AM_RANGE(0x1006, 0x1006) AM_NOP //ld status / command
229		AM_RANGE(0x1007, 0x1007) AM_READWRITE_LEGACY(laserdisc_r,laserdisc_w) // ld data
	232	AM_RANGE(0x1007, 0x1007) AM_READWRITE(laserdisc_r,laserdisc_w) // ld data
230	233	AM_RANGE(0x1800, 0x1fff) AM_RAM_WRITE_LEGACY(paletteram_RRRGGGBB_w) AM_BASE_GENERIC(paletteram)
231	234	AM_RANGE(0x2800, 0x2fff) AM_RAM AM_BASE(m_videoram)
232	235	AM_RANGE(0x3000, 0x3fff) AM_RAM
r14845	r14846
236	239	/* sound arrangement is pratically identical to Zero Target. */
237	240
238	241	#ifdef UNUSED_FUNCTION
239		static WRITE8_HANDLER( nmimask_w )
	242	WRITE8_MEMBER(deco_ld_state::nmimask_w)
240	243	{
241		deco_ld_state *state = space->machine().driver_data<deco_ld_state>();
242		state->m_nmimask = data & 0x80;
	244	m_nmimask = data & 0x80;
243	245	}
244	246	#endif
245	247

src/mame/drivers/progolf.c

r14845	r14846
71	71	UINT8 m_scrollx_lo;
72	72	UINT8 m_gfx_switch;
73	73	UINT8 m_sound_cmd;
	74	DECLARE_WRITE8_MEMBER(progolf_charram_w);
	75	DECLARE_WRITE8_MEMBER(progolf_char_vregs_w);
	76	DECLARE_WRITE8_MEMBER(progolf_scrollx_lo_w);
	77	DECLARE_WRITE8_MEMBER(progolf_scrollx_hi_w);
	78	DECLARE_WRITE8_MEMBER(progolf_flip_screen_w);
	79	DECLARE_WRITE8_MEMBER(audio_command_w);
	80	DECLARE_READ8_MEMBER(audio_command_r);
	81	DECLARE_READ8_MEMBER(progolf_videoram_r);
	82	DECLARE_WRITE8_MEMBER(progolf_videoram_w);
74	83	};
75	84
76	85
r14845	r14846
140	149	return 0;
141	150	}
142	151
143		static WRITE8_HANDLER( progolf_charram_w )
	152	WRITE8_MEMBER(progolf_state::progolf_charram_w)
144	153	{
145		progolf_state *state = space->machine().driver_data<progolf_state>();
146	154	int i;
147		state->m_fbram[offset] = data;
	155	m_fbram[offset] = data;
148	156
149		if(state->m_char_pen == 7)
	157	if(m_char_pen == 7)
150	158	{
151	159	for(i=0;i<8;i++)
152		state->m_fg_fb[offset*8+i] = 0;
	160	m_fg_fb[offset*8+i] = 0;
153	161	}
154	162	else
155	163	{
156	164	for(i=0;i<8;i++)
157	165	{
158		if(state->m_fg_fb[offset*8+i] == state->m_char_pen)
159		state->m_fg_fb[offset*8+i] = data & (1<<(7-i)) ? state->m_char_pen : 0;
	166	if(m_fg_fb[offset*8+i] == m_char_pen)
	167	m_fg_fb[offset*8+i] = data & (1<<(7-i)) ? m_char_pen : 0;
160	168	else
161		state->m_fg_fb[offset*8+i] = data & (1<<(7-i)) ? state->m_fg_fb[offset*8+i]|state->m_char_pen : state->m_fg_fb[offset*8+i];
	169	m_fg_fb[offset*8+i] = data & (1<<(7-i)) ? m_fg_fb[offset*8+i]|m_char_pen : m_fg_fb[offset*8+i];
162	170	}
163	171	}
164	172	}
165	173
166		static WRITE8_HANDLER( progolf_char_vregs_w )
	174	WRITE8_MEMBER(progolf_state::progolf_char_vregs_w)
167	175	{
168		progolf_state *state = space->machine().driver_data<progolf_state>();
169		state->m_char_pen = data & 0x07;
170		state->m_gfx_switch = data & 0xf0;
171		state->m_char_pen_vreg = data & 0x30;
	176	m_char_pen = data & 0x07;
	177	m_gfx_switch = data & 0xf0;
	178	m_char_pen_vreg = data & 0x30;
172	179	}
173	180
174		static WRITE8_HANDLER( progolf_scrollx_lo_w )
	181	WRITE8_MEMBER(progolf_state::progolf_scrollx_lo_w)
175	182	{
176		progolf_state *state = space->machine().driver_data<progolf_state>();
177		state->m_scrollx_lo = data;
	183	m_scrollx_lo = data;
178	184	}
179	185
180		static WRITE8_HANDLER( progolf_scrollx_hi_w )
	186	WRITE8_MEMBER(progolf_state::progolf_scrollx_hi_w)
181	187	{
182		progolf_state *state = space->machine().driver_data<progolf_state>();
183		state->m_scrollx_hi = data;
	188	m_scrollx_hi = data;
184	189	}
185	190
186		static WRITE8_HANDLER( progolf_flip_screen_w )
	191	WRITE8_MEMBER(progolf_state::progolf_flip_screen_w)
187	192	{
188		flip_screen_set(space->machine(), data & 1);
	193	flip_screen_set(machine(), data & 1);
189	194	if(data & 0xfe)
190	195	printf("$9600 with data = %02x used\n",data);
191	196	}
192	197
193		static WRITE8_HANDLER( audio_command_w )
	198	WRITE8_MEMBER(progolf_state::audio_command_w)
194	199	{
195		progolf_state *state = space->machine().driver_data<progolf_state>();
196		state->m_sound_cmd = data;
197		cputag_set_input_line(space->machine(), "audiocpu", 0, ASSERT_LINE);
	200	m_sound_cmd = data;
	201	cputag_set_input_line(machine(), "audiocpu", 0, ASSERT_LINE);
198	202	}
199	203
200		static READ8_HANDLER( audio_command_r )
	204	READ8_MEMBER(progolf_state::audio_command_r)
201	205	{
202		progolf_state *state = space->machine().driver_data<progolf_state>();
203		cputag_set_input_line(space->machine(), "audiocpu", 0, CLEAR_LINE);
204		return state->m_sound_cmd;
	206	cputag_set_input_line(machine(), "audiocpu", 0, CLEAR_LINE);
	207	return m_sound_cmd;
205	208	}
206	209
207		static READ8_HANDLER( progolf_videoram_r )
	210	READ8_MEMBER(progolf_state::progolf_videoram_r)
208	211	{
209		progolf_state *state = space->machine().driver_data<progolf_state>();
210		UINT8 *videoram = state->m_videoram;
211		UINT8 *gfx_rom = space->machine().region("gfx1")->base();
	212	UINT8 *videoram = m_videoram;
	213	UINT8 *gfx_rom = machine().region("gfx1")->base();
212	214
213	215	if (offset >= 0x0800)
214	216	{
215		if      (state->m_gfx_switch == 0x50)
	217	if      (m_gfx_switch == 0x50)
216	218	return gfx_rom[offset];
217		else if (state->m_gfx_switch == 0x60)
	219	else if (m_gfx_switch == 0x60)
218	220	return gfx_rom[offset + 0x1000];
219		else if (state->m_gfx_switch == 0x70)
	221	else if (m_gfx_switch == 0x70)
220	222	return gfx_rom[offset + 0x2000];
221	223	else
222	224	return videoram[offset];
223	225	} else {
224		if      (state->m_gfx_switch == 0x10)
	226	if      (m_gfx_switch == 0x10)
225	227	return gfx_rom[offset];
226		else if (state->m_gfx_switch == 0x20)
	228	else if (m_gfx_switch == 0x20)
227	229	return gfx_rom[offset + 0x1000];
228		else if (state->m_gfx_switch == 0x30)
	230	else if (m_gfx_switch == 0x30)
229	231	return gfx_rom[offset + 0x2000];
230	232	else
231	233	return videoram[offset];
232	234	}
233	235	}
234	236
235		static WRITE8_HANDLER( progolf_videoram_w )
	237	WRITE8_MEMBER(progolf_state::progolf_videoram_w)
236	238	{
237		progolf_state *state = space->machine().driver_data<progolf_state>();
238		UINT8 *videoram = state->m_videoram;
239		//if(state->m_gfx_switch & 0x40)
	239	UINT8 *videoram = m_videoram;
	240	//if(m_gfx_switch & 0x40)
240	241	videoram[offset] = data;
241	242	}
242	243
243	244	static ADDRESS_MAP_START( main_cpu, AS_PROGRAM, 8, progolf_state )
244	245	AM_RANGE(0x0000, 0x5fff) AM_RAM
245		AM_RANGE(0x6000, 0x7fff) AM_RAM_WRITE_LEGACY(progolf_charram_w) AM_BASE(m_fbram)
246		AM_RANGE(0x8000, 0x8fff) AM_READWRITE_LEGACY(progolf_videoram_r,progolf_videoram_w)
247		AM_RANGE(0x9000, 0x9000) AM_READ_PORT("IN2") AM_WRITE_LEGACY(progolf_char_vregs_w)
248		AM_RANGE(0x9200, 0x9200) AM_READ_PORT("P1") AM_WRITE_LEGACY(progolf_scrollx_hi_w) //p1 inputs
249		AM_RANGE(0x9400, 0x9400) AM_READ_PORT("P2") AM_WRITE_LEGACY(progolf_scrollx_lo_w) //p2 inputs
250		AM_RANGE(0x9600, 0x9600) AM_READ_PORT("IN0") AM_WRITE_LEGACY(progolf_flip_screen_w)   /* VBLANK */
	246	AM_RANGE(0x6000, 0x7fff) AM_RAM_WRITE(progolf_charram_w) AM_BASE(m_fbram)
	247	AM_RANGE(0x8000, 0x8fff) AM_READWRITE(progolf_videoram_r,progolf_videoram_w)
	248	AM_RANGE(0x9000, 0x9000) AM_READ_PORT("IN2") AM_WRITE(progolf_char_vregs_w)
	249	AM_RANGE(0x9200, 0x9200) AM_READ_PORT("P1") AM_WRITE(progolf_scrollx_hi_w) //p1 inputs
	250	AM_RANGE(0x9400, 0x9400) AM_READ_PORT("P2") AM_WRITE(progolf_scrollx_lo_w) //p2 inputs
	251	AM_RANGE(0x9600, 0x9600) AM_READ_PORT("IN0") AM_WRITE(progolf_flip_screen_w)   /* VBLANK */
251	252	AM_RANGE(0x9800, 0x9800) AM_READ_PORT("DSW1")
252	253	AM_RANGE(0x9800, 0x9800) AM_DEVWRITE("crtc", mc6845_device, address_w)
253	254	AM_RANGE(0x9801, 0x9801) AM_DEVWRITE("crtc", mc6845_device, register_w)
254		AM_RANGE(0x9a00, 0x9a00) AM_READ_PORT("DSW2") AM_WRITE_LEGACY(audio_command_w)
	255	AM_RANGE(0x9a00, 0x9a00) AM_READ_PORT("DSW2") AM_WRITE(audio_command_w)
255	256	//  AM_RANGE(0x9e00, 0x9e00) AM_WRITENOP
256	257	AM_RANGE(0xb000, 0xffff) AM_ROM
257	258	ADDRESS_MAP_END
r14845	r14846
262	263	AM_RANGE(0x5000, 0x5fff) AM_DEVWRITE_LEGACY("ay1", ay8910_address_w)
263	264	AM_RANGE(0x6000, 0x6fff) AM_DEVREADWRITE_LEGACY("ay2", ay8910_r, ay8910_data_w)
264	265	AM_RANGE(0x7000, 0x7fff) AM_DEVWRITE_LEGACY("ay2", ay8910_address_w)
265		AM_RANGE(0x8000, 0x8fff) AM_READ_LEGACY(audio_command_r) AM_WRITENOP //volume control?
	266	AM_RANGE(0x8000, 0x8fff) AM_READ(audio_command_r) AM_WRITENOP //volume control?
266	267	AM_RANGE(0xf000, 0xffff) AM_ROM
267	268	ADDRESS_MAP_END
268	269

src/mame/drivers/jackie.c

r14845	r14846
76	76	UINT16 m_unk_reg[3][5];
77	77
78	78	required_device<cpu_device> m_maincpu;
	79	DECLARE_WRITE8_MEMBER(fg_tile_w);
	80	DECLARE_WRITE8_MEMBER(fg_color_w);
	81	DECLARE_WRITE8_MEMBER(bg_scroll_w);
	82	DECLARE_WRITE8_MEMBER(jackie_reel1_ram_w);
	83	DECLARE_WRITE8_MEMBER(jackie_reel2_ram_w);
	84	DECLARE_WRITE8_MEMBER(jackie_reel3_ram_w);
	85	DECLARE_WRITE8_MEMBER(jackie_unk_reg1_lo_w);
	86	DECLARE_WRITE8_MEMBER(jackie_unk_reg2_lo_w);
	87	DECLARE_WRITE8_MEMBER(jackie_unk_reg3_lo_w);
	88	DECLARE_WRITE8_MEMBER(jackie_unk_reg1_hi_w);
	89	DECLARE_WRITE8_MEMBER(jackie_unk_reg2_hi_w);
	90	DECLARE_WRITE8_MEMBER(jackie_unk_reg3_hi_w);
	91	DECLARE_WRITE8_MEMBER(jackie_nmi_and_coins_w);
	92	DECLARE_WRITE8_MEMBER(jackie_lamps_w);
	93	DECLARE_READ8_MEMBER(igs_irqack_r);
	94	DECLARE_WRITE8_MEMBER(igs_irqack_w);
	95	DECLARE_READ8_MEMBER(expram_r);
	96	void jackie_unk_reg_lo_w( int offset, UINT8 data, int reg );
	97	void jackie_unk_reg_hi_w( int offset, UINT8 data, int reg );
	98	void show_out();
79	99	};
80	100
81	101
r14845	r14846
89	109	SET_TILE_INFO(0, code, tile != 0x1fff ? ((code >> 12) & 0xe) + 1 : 0, 0);
90	110	}
91	111
92		static WRITE8_HANDLER( fg_tile_w )
	112	WRITE8_MEMBER(jackie_state::fg_tile_w)
93	113	{
94		jackie_state *state = space->machine().driver_data<jackie_state>();
95		state->m_fg_tile_ram[offset] = data;
96		state->m_fg_tilemap->mark_tile_dirty(offset);
	114	m_fg_tile_ram[offset] = data;
	115	m_fg_tilemap->mark_tile_dirty(offset);
97	116	}
98	117
99		static WRITE8_HANDLER( fg_color_w )
	118	WRITE8_MEMBER(jackie_state::fg_color_w)
100	119	{
101		jackie_state *state = space->machine().driver_data<jackie_state>();
102		state->m_fg_color_ram[offset] = data;
103		state->m_fg_tilemap->mark_tile_dirty(offset);
	120	m_fg_color_ram[offset] = data;
	121	m_fg_tilemap->mark_tile_dirty(offset);
104	122	}
105	123
106	124
107	125
108	126
109		static WRITE8_HANDLER( bg_scroll_w )
	127	WRITE8_MEMBER(jackie_state::bg_scroll_w)
110	128	{
111		jackie_state *state = space->machine().driver_data<jackie_state>();
112		state->m_bg_scroll[offset] = data;
	129	m_bg_scroll[offset] = data;
113	130	}
114	131
115	132
116		static WRITE8_HANDLER( jackie_reel1_ram_w )
	133	WRITE8_MEMBER(jackie_state::jackie_reel1_ram_w)
117	134	{
118		jackie_state *state = space->machine().driver_data<jackie_state>();
119		state->m_reel1_ram[offset] = data;
120		state->m_reel1_tilemap->mark_tile_dirty(offset);
	135	m_reel1_ram[offset] = data;
	136	m_reel1_tilemap->mark_tile_dirty(offset);
121	137	}
122	138
123	139	static TILE_GET_INFO( get_jackie_reel1_tile_info )
r14845	r14846
129	145
130	146
131	147
132		static WRITE8_HANDLER( jackie_reel2_ram_w )
	148	WRITE8_MEMBER(jackie_state::jackie_reel2_ram_w)
133	149	{
134		jackie_state *state = space->machine().driver_data<jackie_state>();
135		state->m_reel2_ram[offset] = data;
136		state->m_reel2_tilemap->mark_tile_dirty(offset);
	150	m_reel2_ram[offset] = data;
	151	m_reel2_tilemap->mark_tile_dirty(offset);
137	152	}
138	153
139	154	static TILE_GET_INFO( get_jackie_reel2_tile_info )
r14845	r14846
144	159	}
145	160
146	161
147		static WRITE8_HANDLER( jackie_reel3_ram_w )
	162	WRITE8_MEMBER(jackie_state::jackie_reel3_ram_w)
148	163	{
149		jackie_state *state = space->machine().driver_data<jackie_state>();
150		state->m_reel3_ram[offset] = data;
151		state->m_reel3_tilemap->mark_tile_dirty(offset);
	164	m_reel3_ram[offset] = data;
	165	m_reel3_tilemap->mark_tile_dirty(offset);
152	166	}
153	167
154	168	static TILE_GET_INFO( get_jackie_reel3_tile_info )
r14845	r14846
234	248	}
235	249
236	250
237		static void show_out(jackie_state *state)
	251	void jackie_state::show_out()
238	252	{
239	253	#ifdef MAME_DEBUG
240	254	//  popmessage("%02x %02x %02x", state->m_out[0], state->m_out[1], state->m_out[2]);
241	255	popmessage("520: %04x %04x %04x %04x %04x\n560: %04x %04x %04x %04x %04x\n5A0: %04x %04x %04x %04x %04x",
242		state->m_unk_reg[0][0],state->m_unk_reg[0][1],state->m_unk_reg[0][2],state->m_unk_reg[0][3],state->m_unk_reg[0][4],
243		state->m_unk_reg[1][0],state->m_unk_reg[1][1],state->m_unk_reg[1][2],state->m_unk_reg[1][3],state->m_unk_reg[1][4],
244		state->m_unk_reg[2][0],state->m_unk_reg[2][1],state->m_unk_reg[2][2],state->m_unk_reg[2][3],state->m_unk_reg[2][4]
	256	m_unk_reg[0][0],m_unk_reg[0][1],m_unk_reg[0][2],m_unk_reg[0][3],m_unk_reg[0][4],
	257	m_unk_reg[1][0],m_unk_reg[1][1],m_unk_reg[1][2],m_unk_reg[1][3],m_unk_reg[1][4],
	258	m_unk_reg[2][0],m_unk_reg[2][1],m_unk_reg[2][2],m_unk_reg[2][3],m_unk_reg[2][4]
245	259	);
246	260	#endif
247	261	}
248	262
249		static void jackie_unk_reg_lo_w( address_space *space, int offset, UINT8 data, int reg )
	263	void jackie_state::jackie_unk_reg_lo_w( int offset, UINT8 data, int reg )
250	264	{
251		jackie_state *state = space->machine().driver_data<jackie_state>();
252		state->m_unk_reg[reg][offset] &= 0xff00;
253		state->m_unk_reg[reg][offset] |= data;
254		show_out(state);
	265	m_unk_reg[reg][offset] &= 0xff00;
	266	m_unk_reg[reg][offset] |= data;
	267	show_out();
255	268	}
256	269
257		static WRITE8_HANDLER( jackie_unk_reg1_lo_w ) { jackie_unk_reg_lo_w( space, offset, data, 0 ); }
258		static WRITE8_HANDLER( jackie_unk_reg2_lo_w ) { jackie_unk_reg_lo_w( space, offset, data, 1 ); }
259		static WRITE8_HANDLER( jackie_unk_reg3_lo_w ) { jackie_unk_reg_lo_w( space, offset, data, 2 ); }
	270	WRITE8_MEMBER(jackie_state::jackie_unk_reg1_lo_w){ jackie_unk_reg_lo_w( offset, data, 0 ); }
	271	WRITE8_MEMBER(jackie_state::jackie_unk_reg2_lo_w){ jackie_unk_reg_lo_w( offset, data, 1 ); }
	272	WRITE8_MEMBER(jackie_state::jackie_unk_reg3_lo_w){ jackie_unk_reg_lo_w( offset, data, 2 ); }
260	273
261		static void jackie_unk_reg_hi_w( address_space *space, int offset, UINT8 data, int reg )
	274	void jackie_state::jackie_unk_reg_hi_w( int offset, UINT8 data, int reg )
262	275	{
263		jackie_state *state = space->machine().driver_data<jackie_state>();
264		state->m_unk_reg[reg][offset] &= 0xff;
265		state->m_unk_reg[reg][offset] |= data << 8;
266		show_out(state);
	276	m_unk_reg[reg][offset] &= 0xff;
	277	m_unk_reg[reg][offset] |= data << 8;
	278	show_out();
267	279	}
268	280
269		static WRITE8_HANDLER( jackie_unk_reg1_hi_w ) { jackie_unk_reg_hi_w( space, offset, data, 0 ); }
270		static WRITE8_HANDLER( jackie_unk_reg2_hi_w ) { jackie_unk_reg_hi_w( space, offset, data, 1 ); }
271		static WRITE8_HANDLER( jackie_unk_reg3_hi_w ) { jackie_unk_reg_hi_w( space, offset, data, 2 ); }
	281	WRITE8_MEMBER(jackie_state::jackie_unk_reg1_hi_w){ jackie_unk_reg_hi_w( offset, data, 0 ); }
	282	WRITE8_MEMBER(jackie_state::jackie_unk_reg2_hi_w){ jackie_unk_reg_hi_w( offset, data, 1 ); }
	283	WRITE8_MEMBER(jackie_state::jackie_unk_reg3_hi_w){ jackie_unk_reg_hi_w( offset, data, 2 ); }
272	284
273		static WRITE8_HANDLER( jackie_nmi_and_coins_w )
	285	WRITE8_MEMBER(jackie_state::jackie_nmi_and_coins_w)
274	286	{
275		jackie_state *state = space->machine().driver_data<jackie_state>();
276		coin_counter_w(space->machine(), 0,      data & 0x01);   // coin_a
277		coin_counter_w(space->machine(), 1,      data & 0x04);   // coin_c
278		coin_counter_w(space->machine(), 2,      data & 0x08);   // key in
279		coin_counter_w(space->machine(), 3,      data & 0x10);   // coin state->m_out mech
	287	coin_counter_w(machine(), 0,      data & 0x01);   // coin_a
	288	coin_counter_w(machine(), 1,      data & 0x04);   // coin_c
	289	coin_counter_w(machine(), 2,      data & 0x08);   // key in
	290	coin_counter_w(machine(), 3,      data & 0x10);   // coin m_out mech
280	291
281		set_led_status(space->machine(), 6,      data & 0x20);   // led for coin state->m_out / state->m_hopper active
	292	set_led_status(machine(), 6,      data & 0x20);   // led for coin m_out / m_hopper active
282	293
283		state->m_exp_bank   = (data & 0x02) ? 1 : 0;      // expram bank number
284		state->m_nmi_enable = data & 0x80;     // nmi enable?
	294	m_exp_bank   = (data & 0x02) ? 1 : 0;      // expram bank number
	295	m_nmi_enable = data & 0x80;     // nmi enable?
285	296
286		state->m_out[0] = data;
287		show_out(state);
	297	m_out[0] = data;
	298	show_out();
288	299	}
289	300
290		static WRITE8_HANDLER( jackie_lamps_w )
	301	WRITE8_MEMBER(jackie_state::jackie_lamps_w)
291	302	{
292		jackie_state *state = space->machine().driver_data<jackie_state>();
293	303	/*
294	304	- Lbits -
295	305	7654 3210
r14845	r14846
308	318	output_set_lamp_value(5, (data >> 2) & 1);      /* Lamp 5 - HOLD 5 */
309	319	output_set_lamp_value(6, (data & 1));         /* Lamp 6 - START */
310	320
311		state->m_hopper         =   (~data)& 0x80;
	321	m_hopper         =   (~data)& 0x80;
312	322
313		state->m_out[1] = data;
314		show_out(state);
	323	m_out[1] = data;
	324	show_out();
315	325	}
316	326
317		static READ8_HANDLER( igs_irqack_r )
	327	READ8_MEMBER(jackie_state::igs_irqack_r)
318	328	{
319		jackie_state *state = space->machine().driver_data<jackie_state>();
320		state->m_irq_enable = 1;
	329	m_irq_enable = 1;
321	330	return 0;
322	331	}
323	332
324		static WRITE8_HANDLER( igs_irqack_w )
	333	WRITE8_MEMBER(jackie_state::igs_irqack_w)
325	334	{
326		jackie_state *state = space->machine().driver_data<jackie_state>();
327		//  cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
328		state->m_out[2] = data;
329		show_out(state);
	335	//  cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
	336	m_out[2] = data;
	337	show_out();
330	338	}
331	339
332		static READ8_HANDLER( expram_r )
	340	READ8_MEMBER(jackie_state::expram_r)
333	341	{
334		jackie_state *state = space->machine().driver_data<jackie_state>();
335		UINT8 *rom = space->machine().region("gfx3")->base();
	342	UINT8 *rom = machine().region("gfx3")->base();
336	343
337		offset += state->m_exp_bank * 0x8000;
338		//  logerror("PC %06X: %04x = %02x\n",cpu_get_pc(&space->device()),offset,rom[offset]);
	344	offset += m_exp_bank * 0x8000;
	345	//  logerror("PC %06X: %04x = %02x\n",cpu_get_pc(&space.device()),offset,rom[offset]);
339	346	return rom[offset];
340	347	}
341	348
r14845	r14846
346	353	ADDRESS_MAP_END
347	354
348	355	static ADDRESS_MAP_START( jackie_io_map, AS_IO, 8, jackie_state )
349		AM_RANGE(0x0520, 0x0524) AM_WRITE_LEGACY(jackie_unk_reg1_lo_w)
350		AM_RANGE(0x0d20, 0x0d24) AM_WRITE_LEGACY(jackie_unk_reg1_hi_w)
351		AM_RANGE(0x0560, 0x0564) AM_WRITE_LEGACY(jackie_unk_reg2_lo_w)
352		AM_RANGE(0x0d60, 0x0d64) AM_WRITE_LEGACY(jackie_unk_reg2_hi_w)
353		AM_RANGE(0x05a0, 0x05a4) AM_WRITE_LEGACY(jackie_unk_reg3_lo_w)
354		AM_RANGE(0x0da0, 0x0da4) AM_WRITE_LEGACY(jackie_unk_reg3_hi_w)
	356	AM_RANGE(0x0520, 0x0524) AM_WRITE(jackie_unk_reg1_lo_w)
	357	AM_RANGE(0x0d20, 0x0d24) AM_WRITE(jackie_unk_reg1_hi_w)
	358	AM_RANGE(0x0560, 0x0564) AM_WRITE(jackie_unk_reg2_lo_w)
	359	AM_RANGE(0x0d60, 0x0d64) AM_WRITE(jackie_unk_reg2_hi_w)
	360	AM_RANGE(0x05a0, 0x05a4) AM_WRITE(jackie_unk_reg3_lo_w)
	361	AM_RANGE(0x0da0, 0x0da4) AM_WRITE(jackie_unk_reg3_hi_w)
355	362	AM_RANGE(0x1000, 0x1107) AM_RAM AM_BASE(m_bg_scroll2 )
356	363	AM_RANGE(0x2000, 0x27ff) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split1_w ) AM_BASE_GENERIC( paletteram )
357	364	AM_RANGE(0x2800, 0x2fff) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split2_w ) AM_BASE_GENERIC( paletteram2 )
r14845	r14846
360	367	AM_RANGE(0x4002, 0x4002) AM_READ_PORT("DSW3")         /* DSW3 */
361	368	AM_RANGE(0x4003, 0x4003) AM_READ_PORT("DSW4")         /* DSW4 */
362	369	AM_RANGE(0x4004, 0x4004) AM_READ_PORT("DSW5")         /* DSW5 */
363		AM_RANGE(0x5080, 0x5080) AM_WRITE_LEGACY(jackie_nmi_and_coins_w)
	370	AM_RANGE(0x5080, 0x5080) AM_WRITE(jackie_nmi_and_coins_w)
364	371	AM_RANGE(0x5081, 0x5081) AM_READ_PORT("SERVICE")
365	372	AM_RANGE(0x5082, 0x5082) AM_READ_PORT("COINS")
366	373	AM_RANGE(0x5090, 0x5090) AM_READ_PORT("BUTTONS1")
367		AM_RANGE(0x5091, 0x5091) AM_WRITE_LEGACY(jackie_lamps_w )
	374	AM_RANGE(0x5091, 0x5091) AM_WRITE(jackie_lamps_w )
368	375	AM_RANGE(0x50a0, 0x50a0) AM_READ_PORT("BUTTONS2")
369	376	AM_RANGE(0x50b0, 0x50b1) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w)
370		AM_RANGE(0x50c0, 0x50c0) AM_READ_LEGACY(igs_irqack_r) AM_WRITE_LEGACY(igs_irqack_w)
371		AM_RANGE(0x6000, 0x60ff) AM_RAM_WRITE_LEGACY(bg_scroll_w ) AM_BASE(m_bg_scroll )
372		AM_RANGE(0x6800, 0x69ff) AM_RAM_WRITE_LEGACY(jackie_reel1_ram_w )  AM_BASE(m_reel1_ram )
373		AM_RANGE(0x6a00, 0x6bff) AM_RAM_WRITE_LEGACY(jackie_reel2_ram_w )  AM_BASE(m_reel2_ram )
374		AM_RANGE(0x6c00, 0x6dff) AM_RAM_WRITE_LEGACY(jackie_reel3_ram_w )  AM_BASE(m_reel3_ram )
375		AM_RANGE(0x7000, 0x77ff) AM_RAM_WRITE_LEGACY(fg_tile_w )  AM_BASE(m_fg_tile_ram )
376		AM_RANGE(0x7800, 0x7fff) AM_RAM_WRITE_LEGACY(fg_color_w ) AM_BASE(m_fg_color_ram )
377		AM_RANGE(0x8000, 0xffff) AM_READ_LEGACY(expram_r)
	377	AM_RANGE(0x50c0, 0x50c0) AM_READ(igs_irqack_r) AM_WRITE(igs_irqack_w)
	378	AM_RANGE(0x6000, 0x60ff) AM_RAM_WRITE(bg_scroll_w ) AM_BASE(m_bg_scroll )
	379	AM_RANGE(0x6800, 0x69ff) AM_RAM_WRITE(jackie_reel1_ram_w )  AM_BASE(m_reel1_ram )
	380	AM_RANGE(0x6a00, 0x6bff) AM_RAM_WRITE(jackie_reel2_ram_w )  AM_BASE(m_reel2_ram )
	381	AM_RANGE(0x6c00, 0x6dff) AM_RAM_WRITE(jackie_reel3_ram_w )  AM_BASE(m_reel3_ram )
	382	AM_RANGE(0x7000, 0x77ff) AM_RAM_WRITE(fg_tile_w )  AM_BASE(m_fg_tile_ram )
	383	AM_RANGE(0x7800, 0x7fff) AM_RAM_WRITE(fg_color_w ) AM_BASE(m_fg_color_ram )
	384	AM_RANGE(0x8000, 0xffff) AM_READ(expram_r)
378	385	ADDRESS_MAP_END
379	386
380	387	static CUSTOM_INPUT( hopper_r )

src/mame/drivers/blackt96.c

r14845	r14846
61	61
62	62	UINT16* m_tilemapram;
63	63	UINT16* m_tilemapram2;
	64	DECLARE_WRITE16_MEMBER(blackt96_c0000_w);
	65	DECLARE_WRITE16_MEMBER(blackt96_80000_w);
	66	DECLARE_READ8_MEMBER(PIC16C5X_T0_clk_r);
	67	DECLARE_WRITE8_MEMBER(blackt96_soundio_port00_w);
	68	DECLARE_READ8_MEMBER(blackt96_soundio_port01_r);
	69	DECLARE_WRITE8_MEMBER(blackt96_soundio_port01_w);
	70	DECLARE_READ8_MEMBER(blackt96_soundio_port02_r);
	71	DECLARE_WRITE8_MEMBER(blackt96_soundio_port02_w);
64	72	};
65	73
66	74
r14845	r14846
156	164	}
157	165
158	166
159		static WRITE16_HANDLER( blackt96_c0000_w )
	167	WRITE16_MEMBER(blackt96_state::blackt96_c0000_w)
160	168	{
161	169	printf("blackt96_c0000_w %04x %04x\n",data,mem_mask);
162	170	}
163	171
164		static WRITE16_HANDLER( blackt96_80000_w )
	172	WRITE16_MEMBER(blackt96_state::blackt96_80000_w)
165	173	{
166	174	// TO sound MCU?
167	175	printf("blackt96_80000_w %04x %04x\n",data,mem_mask);
r14845	r14846
170	178
171	179	static ADDRESS_MAP_START( blackt96_map, AS_PROGRAM, 16, blackt96_state )
172	180	AM_RANGE(0x000000, 0x07ffff) AM_ROM
173		AM_RANGE(0x080000, 0x080001) AM_READ_PORT("P1_P2") AM_WRITE_LEGACY(blackt96_80000_w)
174		AM_RANGE(0x0c0000, 0x0c0001) AM_READ_PORT("IN1") AM_WRITE_LEGACY(blackt96_c0000_w) // COIN INPUT
	181	AM_RANGE(0x080000, 0x080001) AM_READ_PORT("P1_P2") AM_WRITE(blackt96_80000_w)
	182	AM_RANGE(0x0c0000, 0x0c0001) AM_READ_PORT("IN1") AM_WRITE(blackt96_c0000_w) // COIN INPUT
175	183	AM_RANGE(0x0e0000, 0x0e0001) AM_READ_PORT("IN2")
176	184	AM_RANGE(0x0e8000, 0x0e8001) AM_READ_PORT("IN3")
177	185	AM_RANGE(0x0f0000, 0x0f0001) AM_READ_PORT("DSW1")
r14845	r14846
443	451	GFXDECODE_END
444	452
445	453
446		static READ8_HANDLER( PIC16C5X_T0_clk_r )
	454	READ8_MEMBER(blackt96_state::PIC16C5X_T0_clk_r)
447	455	{
448	456	return 0;
449	457	}
450	458
451		static WRITE8_HANDLER( blackt96_soundio_port00_w )
	459	WRITE8_MEMBER(blackt96_state::blackt96_soundio_port00_w)
452	460	{
453
454	461	}
455	462
456		static READ8_HANDLER( blackt96_soundio_port01_r )
	463	READ8_MEMBER(blackt96_state::blackt96_soundio_port01_r)
457	464	{
458		return space->machine().rand();
	465	return machine().rand();
459	466	}
460	467
461		static WRITE8_HANDLER( blackt96_soundio_port01_w )
	468	WRITE8_MEMBER(blackt96_state::blackt96_soundio_port01_w)
462	469	{
463
464	470	}
465	471
466		static READ8_HANDLER( blackt96_soundio_port02_r )
	472	READ8_MEMBER(blackt96_state::blackt96_soundio_port02_r)
467	473	{
468		return space->machine().rand();
	474	return machine().rand();
469	475	}
470	476
471		static WRITE8_HANDLER( blackt96_soundio_port02_w )
	477	WRITE8_MEMBER(blackt96_state::blackt96_soundio_port02_w)
472	478	{
473
474	479	}
475	480
476	481	static ADDRESS_MAP_START( sound_io_map, AS_IO, 8, blackt96_state )
477		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(blackt96_soundio_port00_w )
478		AM_RANGE(0x01, 0x01) AM_READWRITE_LEGACY(blackt96_soundio_port01_r, blackt96_soundio_port01_w )
479		AM_RANGE(0x02, 0x02) AM_READWRITE_LEGACY(blackt96_soundio_port02_r, blackt96_soundio_port02_w )
480		AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ_LEGACY(PIC16C5X_T0_clk_r)
	482	AM_RANGE(0x00, 0x00) AM_WRITE(blackt96_soundio_port00_w )
	483	AM_RANGE(0x01, 0x01) AM_READWRITE(blackt96_soundio_port01_r, blackt96_soundio_port01_w )
	484	AM_RANGE(0x02, 0x02) AM_READWRITE(blackt96_soundio_port02_r, blackt96_soundio_port02_w )
	485	AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
481	486	ADDRESS_MAP_END
482	487
483	488

src/mame/drivers/ace.c

r14845	r14846
56	56
57	57	/* input-related */
58	58	int m_objpos[8];
	59	DECLARE_WRITE8_MEMBER(ace_objpos_w);
	60	DECLARE_READ8_MEMBER(ace_objpos_r);
	61	DECLARE_WRITE8_MEMBER(ace_characterram_w);
	62	DECLARE_WRITE8_MEMBER(ace_scoreram_w);
	63	DECLARE_READ8_MEMBER(unk_r);
59	64	};
60	65
61	66
62		static WRITE8_HANDLER( ace_objpos_w )
	67	WRITE8_MEMBER(aceal_state::ace_objpos_w)
63	68	{
64		aceal_state *state = space->machine().driver_data<aceal_state>();
65		state->m_objpos[offset] = data;
	69	m_objpos[offset] = data;
66	70	}
67	71
68	72	#if 0
69		static READ8_HANDLER( ace_objpos_r )
	73	READ8_MEMBER(aceal_state::ace_objpos_r)
70	74	{
71		aceal_state *state = space->machine().driver_data<aceal_state>();
72		return state->m_objpos[offset];
	75	return m_objpos[offset];
73	76	}
74	77	#endif
75	78
r14845	r14846
128	131	}
129	132
130	133
131		static WRITE8_HANDLER( ace_characterram_w )
	134	WRITE8_MEMBER(aceal_state::ace_characterram_w)
132	135	{
133		aceal_state *state = space->machine().driver_data<aceal_state>();
134		if (state->m_characterram[offset] != data)
	136	if (m_characterram[offset] != data)
135	137	{
136	138	if (data & ~0x07)
137	139	{
138	140	logerror("write to %04x data = %02x\n", 0x8000 + offset, data);
139	141	popmessage("write to %04x data = %02x\n", 0x8000 + offset, data);
140	142	}
141		state->m_characterram[offset] = data;
142		gfx_element_mark_dirty(space->machine().gfx[1], 0);
143		gfx_element_mark_dirty(space->machine().gfx[2], 0);
144		gfx_element_mark_dirty(space->machine().gfx[3], 0);
	143	m_characterram[offset] = data;
	144	gfx_element_mark_dirty(machine().gfx[1], 0);
	145	gfx_element_mark_dirty(machine().gfx[2], 0);
	146	gfx_element_mark_dirty(machine().gfx[3], 0);
145	147	}
146	148	}
147	149
148		static WRITE8_HANDLER( ace_scoreram_w )
	150	WRITE8_MEMBER(aceal_state::ace_scoreram_w)
149	151	{
150		aceal_state *state = space->machine().driver_data<aceal_state>();
151		state->m_scoreram[offset] = data;
152		gfx_element_mark_dirty(space->machine().gfx[4], offset / 32);
	152	m_scoreram[offset] = data;
	153	gfx_element_mark_dirty(machine().gfx[4], offset / 32);
153	154	}
154	155
155		static READ8_HANDLER( unk_r )
	156	READ8_MEMBER(aceal_state::unk_r)
156	157	{
157		return space->machine().rand() & 0xff;
	158	return machine().rand() & 0xff;
158	159	}
159	160
160	161
r14845	r14846
166	167
167	168	AM_RANGE(0x0000, 0x09ff) AM_ROM
168	169
169		AM_RANGE(0x2000, 0x20ff) AM_RAM_WRITE_LEGACY(ace_scoreram_w) AM_BASE(m_scoreram)   /* 2x2101 */
	170	AM_RANGE(0x2000, 0x20ff) AM_RAM_WRITE(ace_scoreram_w) AM_BASE(m_scoreram)   /* 2x2101 */
170	171	AM_RANGE(0x8300, 0x83ff) AM_RAM AM_BASE(m_ram2)   /* 2x2101 */
171		AM_RANGE(0x8000, 0x80ff) AM_RAM_WRITE_LEGACY(ace_characterram_w) AM_BASE(m_characterram)   /* 3x3101 (3bits: 0, 1, 2) */
	172	AM_RANGE(0x8000, 0x80ff) AM_RAM_WRITE(ace_characterram_w) AM_BASE(m_characterram)   /* 3x3101 (3bits: 0, 1, 2) */
172	173
173		AM_RANGE(0xc000, 0xc005) AM_WRITE_LEGACY(ace_objpos_w)
	174	AM_RANGE(0xc000, 0xc005) AM_WRITE(ace_objpos_w)
174	175
175	176	/* players inputs */
176	177	AM_RANGE(0xc008, 0xc008) AM_READ_PORT("c008")
r14845	r14846
184	185	AM_RANGE(0xc010, 0xc010) AM_READ_PORT("c010")
185	186	AM_RANGE(0xc011, 0xc011) AM_READ_PORT("c011")
186	187
187		AM_RANGE(0xc012, 0xc012) AM_READ_LEGACY(unk_r)
	188	AM_RANGE(0xc012, 0xc012) AM_READ(unk_r)
188	189
189	190	/* vblank */
190	191	AM_RANGE(0xc014, 0xc014) AM_READ_PORT("c014")
r14845	r14846
195	196	/* start (must read 1 at least once to make the game run) */
196	197	AM_RANGE(0xc016, 0xc016) AM_READ_PORT("c016")
197	198
198		AM_RANGE(0xc017, 0xc017) AM_READ_LEGACY(unk_r)
199		AM_RANGE(0xc018, 0xc018) AM_READ_LEGACY(unk_r)
200		AM_RANGE(0xc019, 0xc019) AM_READ_LEGACY(unk_r)
	199	AM_RANGE(0xc017, 0xc017) AM_READ(unk_r)
	200	AM_RANGE(0xc018, 0xc018) AM_READ(unk_r)
	201	AM_RANGE(0xc019, 0xc019) AM_READ(unk_r)
201	202
202		AM_RANGE(0xc020, 0xc020) AM_READ_LEGACY(unk_r)
203		AM_RANGE(0xc021, 0xc021) AM_READ_LEGACY(unk_r)
204		AM_RANGE(0xc022, 0xc022) AM_READ_LEGACY(unk_r)
205		AM_RANGE(0xc023, 0xc023) AM_READ_LEGACY(unk_r)
206		AM_RANGE(0xc024, 0xc024) AM_READ_LEGACY(unk_r)
207		AM_RANGE(0xc025, 0xc025) AM_READ_LEGACY(unk_r)
208		AM_RANGE(0xc026, 0xc026) AM_READ_LEGACY(unk_r)
	203	AM_RANGE(0xc020, 0xc020) AM_READ(unk_r)
	204	AM_RANGE(0xc021, 0xc021) AM_READ(unk_r)
	205	AM_RANGE(0xc022, 0xc022) AM_READ(unk_r)
	206	AM_RANGE(0xc023, 0xc023) AM_READ(unk_r)
	207	AM_RANGE(0xc024, 0xc024) AM_READ(unk_r)
	208	AM_RANGE(0xc025, 0xc025) AM_READ(unk_r)
	209	AM_RANGE(0xc026, 0xc026) AM_READ(unk_r)
209	210
210	211	ADDRESS_MAP_END
211	212

src/mame/drivers/dreamwld.c

r14845	r14846
146	146
147	147	/* misc */
148	148	int      m_protindex;
	149	DECLARE_WRITE32_MEMBER(dreamwld_bg_videoram_w);
	150	DECLARE_WRITE32_MEMBER(dreamwld_bg2_videoram_w);
	151	DECLARE_READ32_MEMBER(dreamwld_protdata_r);
	152	DECLARE_WRITE32_MEMBER(dreamwld_6295_0_bank_w);
	153	DECLARE_WRITE32_MEMBER(dreamwld_6295_1_bank_w);
	154	DECLARE_WRITE32_MEMBER(dreamwld_palette_w);
149	155	};
150	156
151	157
r14845	r14846
215	221	}
216	222
217	223
218		static WRITE32_HANDLER( dreamwld_bg_videoram_w )
	224	WRITE32_MEMBER(dreamwld_state::dreamwld_bg_videoram_w)
219	225	{
220		dreamwld_state *state = space->machine().driver_data<dreamwld_state>();
221		COMBINE_DATA(&state->m_bg_videoram[offset]);
222		state->m_bg_tilemap->mark_tile_dirty(offset * 2);
223		state->m_bg_tilemap->mark_tile_dirty(offset * 2 + 1);
	226	COMBINE_DATA(&m_bg_videoram[offset]);
	227	m_bg_tilemap->mark_tile_dirty(offset * 2);
	228	m_bg_tilemap->mark_tile_dirty(offset * 2 + 1);
224	229	}
225	230
226	231	static TILE_GET_INFO( get_dreamwld_bg_tile_info )
r14845	r14846
234	239	}
235	240
236	241
237		static WRITE32_HANDLER( dreamwld_bg2_videoram_w )
	242	WRITE32_MEMBER(dreamwld_state::dreamwld_bg2_videoram_w)
238	243	{
239		dreamwld_state *state = space->machine().driver_data<dreamwld_state>();
240		COMBINE_DATA(&state->m_bg2_videoram[offset]);
241		state->m_bg2_tilemap->mark_tile_dirty(offset * 2);
242		state->m_bg2_tilemap->mark_tile_dirty(offset * 2 + 1);
	244	COMBINE_DATA(&m_bg2_videoram[offset]);
	245	m_bg2_tilemap->mark_tile_dirty(offset * 2);
	246	m_bg2_tilemap->mark_tile_dirty(offset * 2 + 1);
243	247	}
244	248
245	249	static TILE_GET_INFO( get_dreamwld_bg2_tile_info )
r14845	r14846
389	393
390	394
391	395
392		static READ32_HANDLER( dreamwld_protdata_r )
	396	READ32_MEMBER(dreamwld_state::dreamwld_protdata_r)
393	397	{
394	398	//static int count = 0;
395		dreamwld_state *state = space->machine().driver_data<dreamwld_state>();
396	399
	400
397	401	//printf("protection read %04x\n", count);
398	402	//count++;
399	403
400		UINT8 *protdata = space->machine().region("user1")->base();
401		size_t protsize = space->machine().region("user1")->bytes();
402		UINT8 dat = protdata[(state->m_protindex++) % protsize];
	404	UINT8 *protdata = machine().region("user1")->base();
	405	size_t protsize = machine().region("user1")->bytes();
	406	UINT8 dat = protdata[(m_protindex++) % protsize];
403	407
404	408	// real hw returns 00 after end of data, I haven't checked if it's possible to overflow the read counter
405	409	// and read out the internal rom.
r14845	r14846
408	412	}
409	413
410	414
411		static WRITE32_HANDLER( dreamwld_6295_0_bank_w )
	415	WRITE32_MEMBER(dreamwld_state::dreamwld_6295_0_bank_w)
412	416	{
413		UINT8 *sound = space->machine().region("oki1")->base();
	417	UINT8 *sound = machine().region("oki1")->base();
414	418
415	419	if (ACCESSING_BITS_0_7)
416	420	memcpy(sound + 0x30000, sound + 0xb0000 + 0x10000 * (data&0x3), 0x10000);
r14845	r14846
418	422	logerror("OKI0: unk bank write %x mem_mask %8x\n", data, mem_mask);
419	423	}
420	424
421		static WRITE32_HANDLER( dreamwld_6295_1_bank_w )
	425	WRITE32_MEMBER(dreamwld_state::dreamwld_6295_1_bank_w)
422	426	{
423		UINT8 *sound = space->machine().region("oki2")->base();
	427	UINT8 *sound = machine().region("oki2")->base();
424	428
425	429	if (ACCESSING_BITS_0_7)
426	430	memcpy(sound + 0x30000, sound + 0xb0000 + 0x10000 * (data&0x3), 0x10000);
r14845	r14846
430	434
431	435	// why doesn't using paletteram16_xRRRRRGGGGGBBBBB_word_w with a 16-bit handler work? colours are
432	436	// severely corrupt on dream world's semicom screen + many sprites, seems palette values get duplicated.
433		static WRITE32_HANDLER( dreamwld_palette_w )
	437	WRITE32_MEMBER(dreamwld_state::dreamwld_palette_w)
434	438	{
435		dreamwld_state *state = space->machine().driver_data<dreamwld_state>();
436	439	UINT16 dat;
437	440	int color;
438	441
439		COMBINE_DATA(&state->m_paletteram[offset]);
	442	COMBINE_DATA(&m_paletteram[offset]);
440	443	color = offset * 2;
441	444
442		dat = state->m_paletteram[offset] & 0x7fff;
443		palette_set_color_rgb(space->machine(), color+1, pal5bit(dat >> 10), pal5bit(dat >> 5), pal5bit(dat >> 0));
	445	dat = m_paletteram[offset] & 0x7fff;
	446	palette_set_color_rgb(machine(), color+1, pal5bit(dat >> 10), pal5bit(dat >> 5), pal5bit(dat >> 0));
444	447
445		dat = (state->m_paletteram[offset] >> 16) & 0x7fff;
446		palette_set_color_rgb(space->machine(), color, pal5bit(dat >> 10), pal5bit(dat >> 5), pal5bit(dat >> 0));
	448	dat = (m_paletteram[offset] >> 16) & 0x7fff;
	449	palette_set_color_rgb(machine(), color, pal5bit(dat >> 10), pal5bit(dat >> 5), pal5bit(dat >> 0));
447	450	}
448	451
449	452
r14845	r14846
452	455	AM_RANGE(0x000000, 0x0fffff) AM_ROM  AM_WRITENOP
453	456
454	457	AM_RANGE(0x400000, 0x401fff) AM_RAM AM_BASE(m_spriteram)
455		AM_RANGE(0x600000, 0x601fff) AM_RAM AM_WRITE_LEGACY(dreamwld_palette_w) AM_BASE(m_paletteram)
456		AM_RANGE(0x800000, 0x801fff) AM_RAM_WRITE_LEGACY(dreamwld_bg_videoram_w ) AM_BASE(m_bg_videoram)
457		AM_RANGE(0x802000, 0x803fff) AM_RAM_WRITE_LEGACY(dreamwld_bg2_videoram_w ) AM_BASE(m_bg2_videoram)
	458	AM_RANGE(0x600000, 0x601fff) AM_RAM AM_WRITE(dreamwld_palette_w) AM_BASE(m_paletteram)
	459	AM_RANGE(0x800000, 0x801fff) AM_RAM_WRITE(dreamwld_bg_videoram_w ) AM_BASE(m_bg_videoram)
	460	AM_RANGE(0x802000, 0x803fff) AM_RAM_WRITE(dreamwld_bg2_videoram_w ) AM_BASE(m_bg2_videoram)
458	461	AM_RANGE(0x804000, 0x805fff) AM_RAM AM_BASE(m_vregs)  // scroll regs etc.
459	462
460	463	AM_RANGE(0xc00000, 0xc00003) AM_READ_PORT("INPUTS")
461	464	AM_RANGE(0xc00004, 0xc00007) AM_READ_PORT("c00004")
462	465
463		AM_RANGE(0xc0000c, 0xc0000f) AM_WRITE_LEGACY(dreamwld_6295_0_bank_w) // sfx
	466	AM_RANGE(0xc0000c, 0xc0000f) AM_WRITE(dreamwld_6295_0_bank_w) // sfx
464	467	AM_RANGE(0xc00018, 0xc0001b) AM_DEVREADWRITE8("oki1", okim6295_device, read, write, 0xff000000) // sfx
465	468
466		AM_RANGE(0xc00030, 0xc00033) AM_READ_LEGACY(dreamwld_protdata_r) // it reads protection data (irq code) from here and puts it at ffd000
	469	AM_RANGE(0xc00030, 0xc00033) AM_READ(dreamwld_protdata_r) // it reads protection data (irq code) from here and puts it at ffd000
467	470
468	471	AM_RANGE(0xfe0000, 0xffffff) AM_RAM AM_BASE(m_workram) // work ram
469	472	ADDRESS_MAP_END
r14845	r14846
471	474	static ADDRESS_MAP_START( dreamwld_map, AS_PROGRAM, 32, dreamwld_state )
472	475	AM_IMPORT_FROM( baryon_map )
473	476
474		AM_RANGE(0xc0002c, 0xc0002f) AM_WRITE_LEGACY(dreamwld_6295_1_bank_w) // sfx
	477	AM_RANGE(0xc0002c, 0xc0002f) AM_WRITE(dreamwld_6295_1_bank_w) // sfx
475	478	AM_RANGE(0xc00028, 0xc0002b) AM_DEVREADWRITE8("oki2", okim6295_device, read, write, 0xff000000) // sfx
476	479	ADDRESS_MAP_END
477	480

src/mame/drivers/panicr.c

r14845	r14846
77	77	UINT8 *m_scrollram;
78	78	UINT8 *m_mainram;
79	79	UINT8 *m_spriteram;
	80	DECLARE_READ8_MEMBER(t5182shared_r);
	81	DECLARE_WRITE8_MEMBER(t5182shared_w);
80	82	};
81	83
82	84
r14845	r14846
171	173	0);
172	174	}
173	175
174		static READ8_HANDLER(t5182shared_r)
	176	READ8_MEMBER(panicr_state::t5182shared_r)
175	177	{
176	178	if ((offset & 1) == 0)
177		return t5182_sharedram_r(space, offset/2);
	179	return t5182_sharedram_r(&space, offset/2);
178	180	else
179	181	return 0;
180	182	}
181	183
182		static WRITE8_HANDLER(t5182shared_w)
	184	WRITE8_MEMBER(panicr_state::t5182shared_w)
183	185	{
184	186	if ((offset & 1) == 0)
185		t5182_sharedram_w(space, offset/2, data);
	187	t5182_sharedram_w(&space, offset/2, data);
186	188	}
187	189
188	190
r14845	r14846
196	198	AM_RANGE(0x0d002, 0x0d002) AM_READ_LEGACY(t5182_sharedram_semaphore_snd_r)
197	199	AM_RANGE(0x0d004, 0x0d004) AM_WRITE_LEGACY(t5182_sharedram_semaphore_main_acquire_w)
198	200	AM_RANGE(0x0d006, 0x0d006) AM_WRITE_LEGACY(t5182_sharedram_semaphore_main_release_w)
199		AM_RANGE(0x0d200, 0x0d2ff) AM_READWRITE_LEGACY(t5182shared_r, t5182shared_w)
	201	AM_RANGE(0x0d200, 0x0d2ff) AM_READWRITE(t5182shared_r, t5182shared_w)
200	202	AM_RANGE(0x0d400, 0x0d400) AM_READ_PORT("P1")
201	203	AM_RANGE(0x0d402, 0x0d402) AM_READ_PORT("P2")
202	204	AM_RANGE(0x0d404, 0x0d404) AM_READ_PORT("START")

src/mame/drivers/istellar.c

r14845	r14846
39	39	UINT8 m_ldp_latch1;
40	40	UINT8 m_ldp_latch2;
41	41	UINT8 m_z80_2_nmi_enable;
	42	DECLARE_READ8_MEMBER(z80_0_latch1_read);
	43	DECLARE_WRITE8_MEMBER(z80_0_latch2_write);
	44	DECLARE_READ8_MEMBER(z80_2_ldp_read);
	45	DECLARE_READ8_MEMBER(z80_2_latch2_read);
	46	DECLARE_READ8_MEMBER(z80_2_nmienable);
	47	DECLARE_READ8_MEMBER(z80_2_unknown_read);
	48	DECLARE_WRITE8_MEMBER(z80_2_latch1_write);
	49	DECLARE_WRITE8_MEMBER(z80_2_ldp_write);
42	50	};
43	51
44	52
r14845	r14846
93	101
94	102	/* MEMORY HANDLERS */
95	103	/* Z80 0 R/W */
96		static READ8_HANDLER(z80_0_latch1_read)
	104	READ8_MEMBER(istellar_state::z80_0_latch1_read)
97	105	{
98		istellar_state *state = space->machine().driver_data<istellar_state>();
99		/*logerror("CPU0 : reading LDP status latch (%x)\n", state->m_ldp_latch1);*/
100		return state->m_ldp_latch1;
	106	/*logerror("CPU0 : reading LDP status latch (%x)\n", m_ldp_latch1);*/
	107	return m_ldp_latch1;
101	108	}
102	109
103		static WRITE8_HANDLER(z80_0_latch2_write)
	110	WRITE8_MEMBER(istellar_state::z80_0_latch2_write)
104	111	{
105		istellar_state *state = space->machine().driver_data<istellar_state>();
106	112	/*logerror("CPU0 : writing cpu_latch2 (%x).  Potentially followed by an IRQ.\n", data);*/
107		state->m_ldp_latch2 = data;
	113	m_ldp_latch2 = data;
108	114
109	115	/* A CPU2 NMI */
110		if (state->m_z80_2_nmi_enable)
	116	if (m_z80_2_nmi_enable)
111	117	{
112	118	logerror("Executing an NMI on CPU2\n");
113		cputag_set_input_line(space->machine(), "sub", INPUT_LINE_NMI, PULSE_LINE);      /* Maybe this is a ASSERT_LINE, CLEAR_LINE combo? */
114		state->m_z80_2_nmi_enable = 0;
	119	cputag_set_input_line(machine(), "sub", INPUT_LINE_NMI, PULSE_LINE);      /* Maybe this is a ASSERT_LINE, CLEAR_LINE combo? */
	120	m_z80_2_nmi_enable = 0;
115	121	}
116	122	}
117	123
r14845	r14846
120	126
121	127
122	128	/* Z80 2 R/W */
123		static READ8_HANDLER(z80_2_ldp_read)
	129	READ8_MEMBER(istellar_state::z80_2_ldp_read)
124	130	{
125		istellar_state *state = space->machine().driver_data<istellar_state>();
126		UINT8 readResult = state->m_laserdisc->status_r();
	131	UINT8 readResult = m_laserdisc->status_r();
127	132	logerror("CPU2 : reading LDP : %x\n", readResult);
128	133	return readResult;
129	134	}
130	135
131		static READ8_HANDLER(z80_2_latch2_read)
	136	READ8_MEMBER(istellar_state::z80_2_latch2_read)
132	137	{
133		istellar_state *state = space->machine().driver_data<istellar_state>();
134		logerror("CPU2 : reading latch2 (%x)\n", state->m_ldp_latch2);
135		return state->m_ldp_latch2;
	138	logerror("CPU2 : reading latch2 (%x)\n", m_ldp_latch2);
	139	return m_ldp_latch2;
136	140	}
137	141
138		static READ8_HANDLER(z80_2_nmienable)
	142	READ8_MEMBER(istellar_state::z80_2_nmienable)
139	143	{
140		istellar_state *state = space->machine().driver_data<istellar_state>();
141	144	logerror("CPU2 : ENABLING NMI\n");
142		state->m_z80_2_nmi_enable = 1;
	145	m_z80_2_nmi_enable = 1;
143	146	return 0x00;
144	147	}
145	148
146		static READ8_HANDLER(z80_2_unknown_read)
	149	READ8_MEMBER(istellar_state::z80_2_unknown_read)
147	150	{
148	151	logerror("CPU2 : c000!\n");
149	152	return 0x00;
150	153	}
151	154
152		static WRITE8_HANDLER(z80_2_latch1_write)
	155	WRITE8_MEMBER(istellar_state::z80_2_latch1_write)
153	156	{
154		istellar_state *state = space->machine().driver_data<istellar_state>();
155	157	logerror("CPU2 : writing latch1 (%x)\n", data);
156		state->m_ldp_latch1 = data;
	158	m_ldp_latch1 = data;
157	159	}
158	160
159		static WRITE8_HANDLER(z80_2_ldp_write)
	161	WRITE8_MEMBER(istellar_state::z80_2_ldp_write)
160	162	{
161		istellar_state *state = space->machine().driver_data<istellar_state>();
162	163	logerror("CPU2 : writing LDP : 0x%x\n", data);
163		state->m_laserdisc->data_w(data);
	164	m_laserdisc->data_w(data);
164	165	}
165	166
166	167
r14845	r14846
182	183	static ADDRESS_MAP_START( z80_2_mem, AS_PROGRAM, 8, istellar_state )
183	184	AM_RANGE(0x0000,0x17ff) AM_ROM
184	185	AM_RANGE(0x1800,0x1fff) AM_RAM
185		AM_RANGE(0xc000,0xc000) AM_READ_LEGACY(z80_2_unknown_read)      /* Seems to be thrown away every time it's read - maybe interrupt related? */
	186	AM_RANGE(0xc000,0xc000) AM_READ(z80_2_unknown_read)      /* Seems to be thrown away every time it's read - maybe interrupt related? */
186	187	ADDRESS_MAP_END
187	188
188	189
r14845	r14846
193	194	AM_RANGE(0x02,0x02) AM_READ_PORT("DSW1")
194	195	AM_RANGE(0x03,0x03) AM_READ_PORT("DSW2")
195	196	/*AM_RANGE(0x04,0x04) AM_WRITE_LEGACY(volatile_palette_write)*/
196		AM_RANGE(0x05,0x05) AM_READWRITE_LEGACY(z80_0_latch1_read,z80_0_latch2_write)
	197	AM_RANGE(0x05,0x05) AM_READWRITE(z80_0_latch1_read,z80_0_latch2_write)
197	198	ADDRESS_MAP_END
198	199
199	200	static ADDRESS_MAP_START( z80_1_io, AS_IO, 8, istellar_state )
r14845	r14846
205	206
206	207	static ADDRESS_MAP_START( z80_2_io, AS_IO, 8, istellar_state )
207	208	ADDRESS_MAP_GLOBAL_MASK(0xff)
208		AM_RANGE(0x00,0x00) AM_READWRITE_LEGACY(z80_2_ldp_read,z80_2_ldp_write)
209		AM_RANGE(0x01,0x01) AM_READWRITE_LEGACY(z80_2_latch2_read,z80_2_latch1_write)
210		AM_RANGE(0x02,0x02) AM_READ_LEGACY(z80_2_nmienable)
	209	AM_RANGE(0x00,0x00) AM_READWRITE(z80_2_ldp_read,z80_2_ldp_write)
	210	AM_RANGE(0x01,0x01) AM_READWRITE(z80_2_latch2_read,z80_2_latch1_write)
	211	AM_RANGE(0x02,0x02) AM_READ(z80_2_nmienable)
211	212	/*  AM_RANGE(0x03,0x03) AM_WRITE_LEGACY(z80_2_ldtrans_write)*/
212	213	ADDRESS_MAP_END
213	214

src/mame/drivers/macs.c

r14845	r14846
71	71	UINT8 m_rev;
72	72	UINT8 *m_ram1;
73	73	UINT8 *m_ram2;
	74	DECLARE_WRITE8_MEMBER(rambank_w);
	75	DECLARE_READ8_MEMBER(macs_input_r);
	76	DECLARE_WRITE8_MEMBER(macs_rom_bank_w);
	77	DECLARE_WRITE8_MEMBER(macs_output_w);
74	78	};
75	79
76	80
r14845	r14846
91	95	AM_RANGE(0xf800, 0xffff) AM_RAMBANK("bank2") /* common /backup ram ?*/
92	96	ADDRESS_MAP_END
93	97
94		static WRITE8_HANDLER(rambank_w)
	98	WRITE8_MEMBER(macs_state::rambank_w)
95	99	{
96		macs_state *state = space->machine().driver_data<macs_state>();
97		memory_set_bankptr(space->machine(),  "bank3", &state->m_ram1[0x10000+(data&1)*0x800] );
	100	memory_set_bankptr(machine(),  "bank3", &m_ram1[0x10000+(data&1)*0x800] );
98	101	}
99	102
100		static READ8_HANDLER( macs_input_r )
	103	READ8_MEMBER(macs_state::macs_input_r)
101	104	{
102		macs_state *state = space->machine().driver_data<macs_state>();
103	105	switch(offset)
104	106	{
105	107	case 0:
106	108	{
107	109	/*It's bit-wise*/
108		switch(state->m_mux_data&0x0f)
	110	switch(m_mux_data&0x0f)
109	111	{
110		case 0x00: return input_port_read(space->machine(), "IN0");
111		case 0x01: return input_port_read(space->machine(), "IN1");
112		case 0x02: return input_port_read(space->machine(), "IN2");
113		case 0x04: return input_port_read(space->machine(), "IN3");
114		case 0x08: return input_port_read(space->machine(), "IN4");
	112	case 0x00: return input_port_read(machine(), "IN0");
	113	case 0x01: return input_port_read(machine(), "IN1");
	114	case 0x02: return input_port_read(machine(), "IN2");
	115	case 0x04: return input_port_read(machine(), "IN3");
	116	case 0x08: return input_port_read(machine(), "IN4");
115	117	default:
116		logerror("Unmapped mahjong panel mux data %02x\n",state->m_mux_data);
	118	logerror("Unmapped mahjong panel mux data %02x\n",m_mux_data);
117	119	return 0xff;
118	120	}
119	121	}
120		case 1: return input_port_read(space->machine(), "SYS0");
121		case 2: return input_port_read(space->machine(), "DSW0");
122		case 3: return input_port_read(space->machine(), "DSW1");
123		case 4: return input_port_read(space->machine(), "DSW2");
124		case 5: return input_port_read(space->machine(), "DSW3");
125		case 6: return input_port_read(space->machine(), "DSW4");
126		case 7: return input_port_read(space->machine(), "SYS1");
127		default:   popmessage("Unmapped I/O read at PC = %06x offset = %02x",cpu_get_pc(&space->device()),offset+0xc0);
	122	case 1: return input_port_read(machine(), "SYS0");
	123	case 2: return input_port_read(machine(), "DSW0");
	124	case 3: return input_port_read(machine(), "DSW1");
	125	case 4: return input_port_read(machine(), "DSW2");
	126	case 5: return input_port_read(machine(), "DSW3");
	127	case 6: return input_port_read(machine(), "DSW4");
	128	case 7: return input_port_read(machine(), "SYS1");
	129	default:   popmessage("Unmapped I/O read at PC = %06x offset = %02x",cpu_get_pc(&space.device()),offset+0xc0);
128	130	}
129	131
130	132	return 0xff;
131	133	}
132	134
133	135
134		static WRITE8_HANDLER( macs_rom_bank_w )
	136	WRITE8_MEMBER(macs_state::macs_rom_bank_w)
135	137	{
136		memory_set_bankptr(space->machine(),  "bank1", space->machine().region("maincpu")->base() + (data* 0x4000) + 0x10000 + macs_cart_slot*0x400000 );
	138	memory_set_bankptr(machine(),  "bank1", machine().region("maincpu")->base() + (data* 0x4000) + 0x10000 + macs_cart_slot*0x400000 );
137	139
138	140	st0016_rom_bank=data;
139	141	}
140	142
141		static WRITE8_HANDLER( macs_output_w )
	143	WRITE8_MEMBER(macs_state::macs_output_w)
142	144	{
143		macs_state *state = space->machine().driver_data<macs_state>();
144		UINT8 *ROM = space->machine().region("maincpu")->base();
	145	UINT8 *ROM = machine().region("maincpu")->base();
145	146
146	147	switch(offset)
147	148	{
r14845	r14846
152	153	---- --x- Cassette A slot
153	154	*/
154	155
155		if(state->m_rev == 1)
	156	if(m_rev == 1)
156	157	{
157	158	/* FIXME: dunno if this RAM bank is right, DASM tracking made on the POST screens indicates that there's just one RAM bank,
158	159	but then MACS2 games locks up. */
159		memory_set_bankptr(space->machine(),  "bank3", &state->m_ram1[((data&0x20)>>5)*0x1000+0x000] );
	160	memory_set_bankptr(machine(),  "bank3", &m_ram1[((data&0x20)>>5)*0x1000+0x000] );
160	161
161	162	macs_cart_slot = (data & 0xc) >> 2;
162	163
163		memory_set_bankptr(space->machine(),  "bank4", &ROM[macs_cart_slot*0x400000+0x10000] );
	164	memory_set_bankptr(machine(),  "bank4", &ROM[macs_cart_slot*0x400000+0x10000] );
164	165	}
165	166
166		memory_set_bankptr(space->machine(),  "bank2", &state->m_ram1[((data&0x20)>>5)*0x1000+0x800] );
	167	memory_set_bankptr(machine(),  "bank2", &m_ram1[((data&0x20)>>5)*0x1000+0x800] );
167	168	break;
168		case 2: state->m_mux_data = data; break;
	169	case 2: m_mux_data = data; break;
169	170
170	171	}
171	172	}
r14845	r14846
173	174	static ADDRESS_MAP_START( macs_io, AS_IO, 8, macs_state )
174	175	ADDRESS_MAP_GLOBAL_MASK(0xff)
175	176	AM_RANGE(0x00, 0xbf) AM_READ_LEGACY(st0016_vregs_r) AM_WRITE_LEGACY(st0016_vregs_w) /* video/crt regs ? */
176		AM_RANGE(0xc0, 0xc7) AM_READWRITE_LEGACY(macs_input_r,macs_output_w)
	177	AM_RANGE(0xc0, 0xc7) AM_READWRITE(macs_input_r,macs_output_w)
177	178	AM_RANGE(0xe0, 0xe0) AM_WRITENOP /* renju = $40, neratte = 0 */
178		AM_RANGE(0xe1, 0xe1) AM_WRITE_LEGACY(macs_rom_bank_w)
	179	AM_RANGE(0xe1, 0xe1) AM_WRITE(macs_rom_bank_w)
179	180	AM_RANGE(0xe2, 0xe2) AM_WRITE_LEGACY(st0016_sprite_bank_w)
180	181	AM_RANGE(0xe3, 0xe4) AM_WRITE_LEGACY(st0016_character_bank_w)
181	182	AM_RANGE(0xe5, 0xe5) AM_WRITE_LEGACY(st0016_palette_bank_w)
182		AM_RANGE(0xe6, 0xe6) AM_WRITE_LEGACY(rambank_w) /* banking ? ram bank ? shared rambank ? */
	183	AM_RANGE(0xe6, 0xe6) AM_WRITE(rambank_w) /* banking ? ram bank ? shared rambank ? */
183	184	AM_RANGE(0xe7, 0xe7) AM_WRITENOP /* watchdog */
184	185	AM_RANGE(0xf0, 0xf0) AM_READ_LEGACY(st0016_dma_r)
185	186	ADDRESS_MAP_END

src/mame/drivers/sbowling.c

r14845	r14846
63	63	UINT8 m_pix[2];
64	64
65	65	required_device<cpu_device> m_maincpu;
	66	DECLARE_WRITE8_MEMBER(sbw_videoram_w);
	67	DECLARE_WRITE8_MEMBER(pix_shift_w);
	68	DECLARE_WRITE8_MEMBER(pix_data_w);
	69	DECLARE_READ8_MEMBER(pix_data_r);
	70	DECLARE_WRITE8_MEMBER(system_w);
	71	DECLARE_WRITE8_MEMBER(graph_control_w);
	72	DECLARE_READ8_MEMBER(controls_r);
66	73	};
67	74
68	75	static TILE_GET_INFO( get_sb_tile_info )
r14845	r14846
84	91	tmpbitmap->pix16(y, x) = col;
85	92	}
86	93
87		static WRITE8_HANDLER( sbw_videoram_w )
	94	WRITE8_MEMBER(sbowling_state::sbw_videoram_w)
88	95	{
89		sbowling_state *state = space->machine().driver_data<sbowling_state>();
90		int flip = flip_screen_get(space->machine());
	96	int flip = flip_screen_get(machine());
91	97	int x,y,i,v1,v2;
92	98
93		state->m_videoram[offset] = data;
	99	m_videoram[offset] = data;
94	100
95	101	offset &= 0x1fff;
96	102
97	103	y = offset / 32;
98	104	x = (offset % 32) * 8;
99	105
100		v1 = state->m_videoram[offset];
101		v2 = state->m_videoram[offset+0x2000];
	106	v1 = m_videoram[offset];
	107	v2 = m_videoram[offset+0x2000];
102	108
103	109	for (i = 0; i < 8; i++)
104	110	{
105		plot_pixel_sbw(state->m_tmpbitmap, x++, y, state->m_color_prom_address | ( ((v1&1)*0x20) | ((v2&1)*0x40) ), flip);
	111	plot_pixel_sbw(m_tmpbitmap, x++, y, m_color_prom_address | ( ((v1&1)*0x20) | ((v2&1)*0x40) ), flip);
106	112	v1 >>= 1;
107	113	v2 >>= 1;
108	114	}
r14845	r14846
126	132	state->m_sb_tilemap = tilemap_create(machine, get_sb_tile_info, tilemap_scan_rows, 8, 8, 32, 32);
127	133	}
128	134
129		static WRITE8_HANDLER( pix_shift_w )
	135	WRITE8_MEMBER(sbowling_state::pix_shift_w)
130	136	{
131		sbowling_state *state = space->machine().driver_data<sbowling_state>();
132	137
133		state->m_pix_sh = data;
	138	m_pix_sh = data;
134	139	}
135		static WRITE8_HANDLER( pix_data_w )
	140	WRITE8_MEMBER(sbowling_state::pix_data_w)
136	141	{
137		sbowling_state *state = space->machine().driver_data<sbowling_state>();
138	142
139		state->m_pix[0] = state->m_pix[1];
140		state->m_pix[1] = data;
	143	m_pix[0] = m_pix[1];
	144	m_pix[1] = data;
141	145	}
142		static READ8_HANDLER( pix_data_r )
	146	READ8_MEMBER(sbowling_state::pix_data_r)
143	147	{
144		sbowling_state *state = space->machine().driver_data<sbowling_state>();
145	148	UINT32 p1, p0;
146	149	int res;
147		int sh = state->m_pix_sh & 7;
	150	int sh = m_pix_sh & 7;
148	151
149		p1 = state->m_pix[1];
150		p0 = state->m_pix[0];
	152	p1 = m_pix[1];
	153	p0 = m_pix[0];
151	154
152	155	res = (((p1 << (sh+8)) | (p0 << sh)) & 0xff00) >> 8;
153	156
r14845	r14846
169	172
170	173	}
171	174
172		static WRITE8_HANDLER (system_w)
	175	WRITE8_MEMBER(sbowling_state::system_w)
173	176	{
174	177	/*
175	178	76543210
r14845	r14846
178	181	-----x-- 1 ?
179	182	----x--- flip screen/controls
180	183	*/
181		sbowling_state *state = space->machine().driver_data<sbowling_state>();
182	184
183		flip_screen_set(space->machine(), data&1);
184	185
185		if ((state->m_sbw_system^data)&1)
	186	flip_screen_set(machine(), data&1);
	187
	188	if ((m_sbw_system^data)&1)
186	189	{
187	190	int offs;
188	191	for (offs = 0;offs < 0x4000; offs++)
189		sbw_videoram_w(space, offs, state->m_videoram[offs]);
	192	sbw_videoram_w(space, offs, m_videoram[offs]);
190	193	}
191		state->m_sbw_system = data;
	194	m_sbw_system = data;
192	195	}
193	196
194		static WRITE8_HANDLER(graph_control_w)
	197	WRITE8_MEMBER(sbowling_state::graph_control_w)
195	198	{
196	199	/*
197	200	76543210
r14845	r14846
201	204	xx------ color PROM address lines A4,A3
202	205	*/
203	206
204		sbowling_state *state = space->machine().driver_data<sbowling_state>();
205	207
206		state->m_color_prom_address = ((data&0x07)<<7) | ((data&0xc0)>>3);
207	208
208		state->m_bgmap = ((data>>4)^3) & 0x3;
209		state->m_sb_tilemap->mark_all_dirty();
	209	m_color_prom_address = ((data&0x07)<<7) | ((data&0xc0)>>3);
	210
	211	m_bgmap = ((data>>4)^3) & 0x3;
	212	m_sb_tilemap->mark_all_dirty();
210	213	}
211	214
212		static READ8_HANDLER (controls_r)
	215	READ8_MEMBER(sbowling_state::controls_r)
213	216	{
214		sbowling_state *state = space->machine().driver_data<sbowling_state>();
215	217
216		if (state->m_sbw_system & 2)
217		return input_port_read(space->machine(), "TRACKY");
	218	if (m_sbw_system & 2)
	219	return input_port_read(machine(), "TRACKY");
218	220	else
219		return input_port_read(space->machine(), "TRACKX");
	221	return input_port_read(machine(), "TRACKX");
220	222	}
221	223
222	224	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, sbowling_state )
223	225	AM_RANGE(0x0000, 0x2fff) AM_ROM
224		AM_RANGE(0x8000, 0xbfff) AM_RAM_WRITE_LEGACY(sbw_videoram_w) AM_BASE(m_videoram)
	226	AM_RANGE(0x8000, 0xbfff) AM_RAM_WRITE(sbw_videoram_w) AM_BASE(m_videoram)
225	227	AM_RANGE(0xf800, 0xf801) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
226	228	AM_RANGE(0xf801, 0xf801) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
227	229	AM_RANGE(0xfc00, 0xffff) AM_RAM
r14845	r14846
230	232
231	233	static ADDRESS_MAP_START( port_map, AS_IO, 8, sbowling_state )
232	234	AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0") AM_WRITE_LEGACY(watchdog_reset_w)
233		AM_RANGE(0x01, 0x01) AM_READWRITE_LEGACY(controls_r, pix_data_w)
234		AM_RANGE(0x02, 0x02) AM_READWRITE_LEGACY(pix_data_r, pix_shift_w)
	235	AM_RANGE(0x01, 0x01) AM_READWRITE(controls_r, pix_data_w)
	236	AM_RANGE(0x02, 0x02) AM_READWRITE(pix_data_r, pix_shift_w)
235	237	AM_RANGE(0x03, 0x03) AM_READ_PORT("IN1") AM_WRITENOP
236		AM_RANGE(0x04, 0x04) AM_READ_PORT("DSW0") AM_WRITE_LEGACY(system_w)
237		AM_RANGE(0x05, 0x05) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(graph_control_w)
	238	AM_RANGE(0x04, 0x04) AM_READ_PORT("DSW0") AM_WRITE(system_w)
	239	AM_RANGE(0x05, 0x05) AM_READ_PORT("DSW1") AM_WRITE(graph_control_w)
238	240	ADDRESS_MAP_END
239	241
240	242

src/mame/drivers/good.c

r14845	r14846
50	50	/* video-related */
51	51	tilemap_t  *m_bg_tilemap;
52	52	tilemap_t  *m_fg_tilemap;
	53	DECLARE_WRITE16_MEMBER(fg_tilemapram_w);
	54	DECLARE_WRITE16_MEMBER(bg_tilemapram_w);
53	55	};
54	56
55	57
56		static WRITE16_HANDLER( fg_tilemapram_w )
	58	WRITE16_MEMBER(good_state::fg_tilemapram_w)
57	59	{
58		good_state *state = space->machine().driver_data<good_state>();
59		COMBINE_DATA(&state->m_fg_tilemapram[offset]);
60		state->m_fg_tilemap->mark_tile_dirty(offset / 2);
	60	COMBINE_DATA(&m_fg_tilemapram[offset]);
	61	m_fg_tilemap->mark_tile_dirty(offset / 2);
61	62	}
62	63
63	64	static TILE_GET_INFO( get_fg_tile_info )
r14845	r14846
68	69	SET_TILE_INFO(0, tileno, attr, 0);
69	70	}
70	71
71		static WRITE16_HANDLER( bg_tilemapram_w )
	72	WRITE16_MEMBER(good_state::bg_tilemapram_w)
72	73	{
73		good_state *state = space->machine().driver_data<good_state>();
74		COMBINE_DATA(&state->m_bg_tilemapram[offset]);
75		state->m_bg_tilemap->mark_tile_dirty(offset / 2);
	74	COMBINE_DATA(&m_bg_tilemapram[offset]);
	75	m_bg_tilemap->mark_tile_dirty(offset / 2);
76	76	}
77	77
78	78	static TILE_GET_INFO( get_bg_tile_info )
r14845	r14846
113	113
114	114	AM_RANGE(0x800000, 0x8007ff) AM_RAM_WRITE_LEGACY(paletteram16_xRRRRRGGGGGBBBBB_word_w) AM_BASE_GENERIC(paletteram)
115	115
116		AM_RANGE(0x820000, 0x820fff) AM_RAM_WRITE_LEGACY(fg_tilemapram_w) AM_BASE(m_fg_tilemapram)
117		AM_RANGE(0x822000, 0x822fff) AM_RAM_WRITE_LEGACY(bg_tilemapram_w) AM_BASE(m_bg_tilemapram)
	116	AM_RANGE(0x820000, 0x820fff) AM_RAM_WRITE(fg_tilemapram_w) AM_BASE(m_fg_tilemapram)
	117	AM_RANGE(0x822000, 0x822fff) AM_RAM_WRITE(bg_tilemapram_w) AM_BASE(m_bg_tilemapram)
118	118
119	119	AM_RANGE(0xff0000, 0xffefff) AM_RAM
120	120	ADDRESS_MAP_END

src/mame/drivers/mirage.c

r14845	r14846
67	67	required_device<okim6295_device> m_oki_sfx;
68	68	required_device<okim6295_device> m_oki_bgm;
69	69	required_device<buffered_spriteram16_device> m_spriteram;
	70	DECLARE_WRITE16_MEMBER(mirage_mux_w);
	71	DECLARE_READ16_MEMBER(mirage_input_r);
	72	DECLARE_WRITE16_MEMBER(okim1_rombank_w);
	73	DECLARE_WRITE16_MEMBER(okim0_rombank_w);
70	74	};
71	75
72	76	static VIDEO_START( mirage )
r14845	r14846
96	100	}
97	101
98	102
99		static WRITE16_HANDLER( mirage_mux_w )
	103	WRITE16_MEMBER(miragemi_state::mirage_mux_w)
100	104	{
101		miragemi_state *state = space->machine().driver_data<miragemi_state>();
102		state->m_mux_data = data & 0x1f;
	105	m_mux_data = data & 0x1f;
103	106	}
104	107
105		static READ16_HANDLER( mirage_input_r )
	108	READ16_MEMBER(miragemi_state::mirage_input_r)
106	109	{
107		miragemi_state *state = space->machine().driver_data<miragemi_state>();
108		switch (state->m_mux_data & 0x1f)
	110	switch (m_mux_data & 0x1f)
109	111	{
110		case 0x01: return input_port_read(space->machine(), "KEY0");
111		case 0x02: return input_port_read(space->machine(), "KEY1");
112		case 0x04: return input_port_read(space->machine(), "KEY2");
113		case 0x08: return input_port_read(space->machine(), "KEY3");
114		case 0x10: return input_port_read(space->machine(), "KEY4");
	112	case 0x01: return input_port_read(machine(), "KEY0");
	113	case 0x02: return input_port_read(machine(), "KEY1");
	114	case 0x04: return input_port_read(machine(), "KEY2");
	115	case 0x08: return input_port_read(machine(), "KEY3");
	116	case 0x10: return input_port_read(machine(), "KEY4");
115	117	}
116	118
117	119	return 0xffff;
118	120	}
119	121
120		static WRITE16_HANDLER( okim1_rombank_w )
	122	WRITE16_MEMBER(miragemi_state::okim1_rombank_w)
121	123	{
122		miragemi_state *state = space->machine().driver_data<miragemi_state>();
123		state->m_oki_sfx->set_bank_base(0x40000 * (data & 0x3));
	124	m_oki_sfx->set_bank_base(0x40000 * (data & 0x3));
124	125	}
125	126
126		static WRITE16_HANDLER( okim0_rombank_w )
	127	WRITE16_MEMBER(miragemi_state::okim0_rombank_w)
127	128	{
128		miragemi_state *state = space->machine().driver_data<miragemi_state>();
129	129
130	130	/*bits 4-6 used on POST? */
131		state->m_oki_bgm->set_bank_base(0x40000 * (data & 0x7));
	131	m_oki_bgm->set_bank_base(0x40000 * (data & 0x7));
132	132	}
133	133
134	134	static ADDRESS_MAP_START( mirage_map, AS_PROGRAM, 16, miragemi_state )
r14845	r14846
148	148	AM_RANGE(0x160000, 0x160001) AM_WRITENOP
149	149	AM_RANGE(0x168000, 0x16800f) AM_DEVWRITE_LEGACY("tilegen1", deco16ic_pf_control_w)
150	150	AM_RANGE(0x16a000, 0x16a001) AM_WRITENOP
151		AM_RANGE(0x16c000, 0x16c001) AM_WRITE_LEGACY(okim1_rombank_w)
152		AM_RANGE(0x16c002, 0x16c003) AM_WRITE_LEGACY(okim0_rombank_w)
153		AM_RANGE(0x16c004, 0x16c005) AM_WRITE_LEGACY(mirage_mux_w)
154		AM_RANGE(0x16c006, 0x16c007) AM_READ_LEGACY(mirage_input_r)
	151	AM_RANGE(0x16c000, 0x16c001) AM_WRITE(okim1_rombank_w)
	152	AM_RANGE(0x16c002, 0x16c003) AM_WRITE(okim0_rombank_w)
	153	AM_RANGE(0x16c004, 0x16c005) AM_WRITE(mirage_mux_w)
	154	AM_RANGE(0x16c006, 0x16c007) AM_READ(mirage_input_r)
155	155	AM_RANGE(0x16e000, 0x16e001) AM_WRITENOP
156	156	AM_RANGE(0x16e002, 0x16e003) AM_READ_PORT("SYSTEM_IN")
157	157	AM_RANGE(0x170000, 0x173fff) AM_RAM

src/mame/drivers/bfmsys85.c

r14845	r14846
90	90	UINT8 m_codec_data[256];
91	91	UINT8 m_sys85_data_line_r;
92	92	UINT8 m_sys85_data_line_t;
	93	DECLARE_WRITE8_MEMBER(watchdog_w);
	94	DECLARE_READ8_MEMBER(irqlatch_r);
	95	DECLARE_WRITE8_MEMBER(reel12_w);
	96	DECLARE_WRITE8_MEMBER(reel34_w);
	97	DECLARE_WRITE8_MEMBER(mmtr_w);
	98	DECLARE_READ8_MEMBER(mmtr_r);
	99	DECLARE_WRITE8_MEMBER(vfd_w);
	100	DECLARE_WRITE8_MEMBER(mux_ctrl_w);
	101	DECLARE_READ8_MEMBER(mux_ctrl_r);
	102	DECLARE_WRITE8_MEMBER(mux_data_w);
	103	DECLARE_READ8_MEMBER(mux_data_r);
	104	DECLARE_WRITE8_MEMBER(mux_enable_w);
	105	DECLARE_WRITE8_MEMBER(triac_w);
	106	DECLARE_READ8_MEMBER(triac_r);
93	107	};
94	108
95	109
r14845	r14846
160	174
161	175	///////////////////////////////////////////////////////////////////////////
162	176
163		static WRITE8_HANDLER( watchdog_w )
	177	WRITE8_MEMBER(bfmsys85_state::watchdog_w)
164	178	{
165	179	}
166	180
r14845	r14846
178	192
179	193	///////////////////////////////////////////////////////////////////////////
180	194
181		static READ8_HANDLER( irqlatch_r )
	195	READ8_MEMBER(bfmsys85_state::irqlatch_r)
182	196	{
183		bfmsys85_state *state = space->machine().driver_data<bfmsys85_state>();
184		int result = state->m_irq_status | 0x02;
	197	int result = m_irq_status | 0x02;
185	198
186		state->m_irq_status = 0;
	199	m_irq_status = 0;
187	200
188	201	return result;
189	202	}
190	203
191	204	///////////////////////////////////////////////////////////////////////////
192	205
193		static WRITE8_HANDLER( reel12_w )
	206	WRITE8_MEMBER(bfmsys85_state::reel12_w)
194	207	{
195		bfmsys85_state *state = space->machine().driver_data<bfmsys85_state>();
196		if ( stepper_update(0, (data>>4)&0x0f) ) state->m_reel_changed |= 0x01;
197		if ( stepper_update(1, data&0x0f   ) ) state->m_reel_changed |= 0x02;
	208	if ( stepper_update(0, (data>>4)&0x0f) ) m_reel_changed |= 0x01;
	209	if ( stepper_update(1, data&0x0f   ) ) m_reel_changed |= 0x02;
198	210
199		if ( stepper_optic_state(0) ) state->m_optic_pattern |=  0x01;
200		else                          state->m_optic_pattern &= ~0x01;
201		if ( stepper_optic_state(1) ) state->m_optic_pattern |=  0x02;
202		else                          state->m_optic_pattern &= ~0x02;
	211	if ( stepper_optic_state(0) ) m_optic_pattern |=  0x01;
	212	else                          m_optic_pattern &= ~0x01;
	213	if ( stepper_optic_state(1) ) m_optic_pattern |=  0x02;
	214	else                          m_optic_pattern &= ~0x02;
203	215	awp_draw_reel(0);
204	216	awp_draw_reel(1);
205	217	}
206	218
207	219	///////////////////////////////////////////////////////////////////////////
208	220
209		static WRITE8_HANDLER( reel34_w )
	221	WRITE8_MEMBER(bfmsys85_state::reel34_w)
210	222	{
211		bfmsys85_state *state = space->machine().driver_data<bfmsys85_state>();
212		if ( stepper_update(2, (data>>4)&0x0f) ) state->m_reel_changed |= 0x04;
213		if ( stepper_update(3, data&0x0f   ) ) state->m_reel_changed |= 0x08;
	223	if ( stepper_update(2, (data>>4)&0x0f) ) m_reel_changed |= 0x04;
	224	if ( stepper_update(3, data&0x0f   ) ) m_reel_changed |= 0x08;
214	225
215		if ( stepper_optic_state(2) ) state->m_optic_pattern |=  0x04;
216		else                          state->m_optic_pattern &= ~0x04;
217		if ( stepper_optic_state(3) ) state->m_optic_pattern |=  0x08;
218		else                          state->m_optic_pattern &= ~0x08;
	226	if ( stepper_optic_state(2) ) m_optic_pattern |=  0x04;
	227	else                          m_optic_pattern &= ~0x04;
	228	if ( stepper_optic_state(3) ) m_optic_pattern |=  0x08;
	229	else                          m_optic_pattern &= ~0x08;
219	230	awp_draw_reel(2);
220	231	awp_draw_reel(3);
221	232	}
r14845	r14846
224	235	// mechanical meters //////////////////////////////////////////////////////
225	236	///////////////////////////////////////////////////////////////////////////
226	237
227		static WRITE8_HANDLER( mmtr_w )
	238	WRITE8_MEMBER(bfmsys85_state::mmtr_w)
228	239	{
229		bfmsys85_state *state = space->machine().driver_data<bfmsys85_state>();
230	240	int i;
231		int  changed = state->m_mmtr_latch ^ data;
	241	int  changed = m_mmtr_latch ^ data;
232	242
233		state->m_mmtr_latch = data;
	243	m_mmtr_latch = data;
234	244
235	245	for (i=0; i<8; i++)
236	246	if ( changed & (1 << i) )   MechMtr_update(i, data & (1 << i) );
237	247
238		if ( data ) generic_pulse_irq_line(space->machine().device("maincpu"), M6809_FIRQ_LINE, 1);
	248	if ( data ) generic_pulse_irq_line(machine().device("maincpu"), M6809_FIRQ_LINE, 1);
239	249	}
240	250	///////////////////////////////////////////////////////////////////////////
241	251
242		static READ8_HANDLER( mmtr_r )
	252	READ8_MEMBER(bfmsys85_state::mmtr_r)
243	253	{
244		bfmsys85_state *state = space->machine().driver_data<bfmsys85_state>();
245		return state->m_mmtr_latch;
	254	return m_mmtr_latch;
246	255	}
247	256	///////////////////////////////////////////////////////////////////////////
248	257
249		static WRITE8_HANDLER( vfd_w )
	258	WRITE8_MEMBER(bfmsys85_state::vfd_w)
250	259	{
251		bfmsys85_state *state = space->machine().driver_data<bfmsys85_state>();
252		int changed = state->m_vfd_latch ^ data;
	260	int changed = m_vfd_latch ^ data;
253	261
254		state->m_vfd_latch = data;
	262	m_vfd_latch = data;
255	263
256	264	if ( changed )
257	265	{
r14845	r14846
280	288	// input / output multiplexers ///////////////////////////////////////////////////
281	289	//////////////////////////////////////////////////////////////////////////////////
282	290
283		static WRITE8_HANDLER( mux_ctrl_w )
	291	WRITE8_MEMBER(bfmsys85_state::mux_ctrl_w)
284	292	{
285		bfmsys85_state *state = space->machine().driver_data<bfmsys85_state>();
286	293	switch ( data & 0xF0 )
287	294	{
288	295	case 0x10:
r14845	r14846
295	302
296	303	case 0x40:
297	304	//logerror(" sys85 mux: read strobe");
298		state->m_mux_input_strobe = data & 0x07;
	305	m_mux_input_strobe = data & 0x07;
299	306
300		if ( state->m_mux_input_strobe == 5 ) state->m_Inputs[5] = 0xFF ^ state->m_optic_pattern;
	307	if ( m_mux_input_strobe == 5 ) m_Inputs[5] = 0xFF ^ m_optic_pattern;
301	308
302		state->m_mux_input = ~state->m_Inputs[state->m_mux_input_strobe];
	309	m_mux_input = ~m_Inputs[m_mux_input_strobe];
303	310	break;
304	311
305	312	case 0x80:
306		state->m_mux_output_strobe = data & 0x0F;
	313	m_mux_output_strobe = data & 0x0F;
307	314	break;
308	315
309	316	case 0xC0:
r14845	r14846
316	323	}
317	324	}
318	325
319		static READ8_HANDLER( mux_ctrl_r )
	326	READ8_MEMBER(bfmsys85_state::mux_ctrl_r)
320	327	{
321	328	// software waits for bit7 to become low
322	329
323	330	return 0;
324	331	}
325	332
326		static WRITE8_HANDLER( mux_data_w )
	333	WRITE8_MEMBER(bfmsys85_state::mux_data_w)
327	334	{
328		bfmsys85_state *state = space->machine().driver_data<bfmsys85_state>();
329	335	int pattern = 0x01, i,
330		off = state->m_mux_output_strobe<<4;
	336	off = m_mux_output_strobe<<4;
331	337
332	338	for ( i = 0; i < 8; i++ )
333	339	{
r14845	r14846
337	343	}
338	344	}
339	345
340		static READ8_HANDLER( mux_data_r )
	346	READ8_MEMBER(bfmsys85_state::mux_data_r)
341	347	{
342		bfmsys85_state *state = space->machine().driver_data<bfmsys85_state>();
343		return state->m_mux_input;
	348	return m_mux_input;
344	349	}
345	350
346	351	///////////////////////////////////////////////////////////////////////////
347	352
348		static WRITE8_HANDLER( mux_enable_w )
	353	WRITE8_MEMBER(bfmsys85_state::mux_enable_w)
349	354	{
350	355	}
351	356
r14845	r14846
353	358	// payslide triacs ////////////////////////////////////////////////////////
354	359	///////////////////////////////////////////////////////////////////////////
355	360
356		static WRITE8_HANDLER( triac_w )
	361	WRITE8_MEMBER(bfmsys85_state::triac_w)
357	362	{
358		bfmsys85_state *state = space->machine().driver_data<bfmsys85_state>();
359		state->m_triac_latch = data;
	363	m_triac_latch = data;
360	364	}
361	365
362	366	///////////////////////////////////////////////////////////////////////////
363	367
364		static READ8_HANDLER( triac_r )
	368	READ8_MEMBER(bfmsys85_state::triac_r)
365	369	{
366		bfmsys85_state *state = space->machine().driver_data<bfmsys85_state>();
367		return state->m_triac_latch;
	370	return m_triac_latch;
368	371	}
369	372
370	373	// machine start (called only once) ////////////////////////////////////////
r14845	r14846
387	390	static ADDRESS_MAP_START( memmap, AS_PROGRAM, 8, bfmsys85_state )
388	391
389	392	AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("nvram") //8k RAM
390		AM_RANGE(0x2000, 0x21FF) AM_WRITE_LEGACY(reel34_w)         // reel 3+4 latch
391		AM_RANGE(0x2200, 0x23FF) AM_WRITE_LEGACY(reel12_w)         // reel 1+2 latch
392		AM_RANGE(0x2400, 0x25FF) AM_WRITE_LEGACY(vfd_w)         // vfd latch
	393	AM_RANGE(0x2000, 0x21FF) AM_WRITE(reel34_w)         // reel 3+4 latch
	394	AM_RANGE(0x2200, 0x23FF) AM_WRITE(reel12_w)         // reel 1+2 latch
	395	AM_RANGE(0x2400, 0x25FF) AM_WRITE(vfd_w)         // vfd latch
393	396
394		AM_RANGE(0x2600, 0x27FF) AM_READWRITE_LEGACY(mmtr_r,mmtr_w)// mechanical meter latch
395		AM_RANGE(0x2800, 0x2800) AM_READ_LEGACY(triac_r)         // payslide triacs
396		AM_RANGE(0x2800, 0x29FF) AM_WRITE_LEGACY(triac_w)         // triacs
	397	AM_RANGE(0x2600, 0x27FF) AM_READWRITE(mmtr_r,mmtr_w)// mechanical meter latch
	398	AM_RANGE(0x2800, 0x2800) AM_READ(triac_r)         // payslide triacs
	399	AM_RANGE(0x2800, 0x29FF) AM_WRITE(triac_w)         // triacs
397	400
398		AM_RANGE(0x2A00, 0x2A00) AM_READWRITE_LEGACY(mux_data_r,mux_data_w)// mux
399		AM_RANGE(0x2A01, 0x2A01) AM_READWRITE_LEGACY(mux_ctrl_r,mux_ctrl_w)// mux status register
400		AM_RANGE(0x2E00, 0x2E00) AM_READ_LEGACY(irqlatch_r)      // irq latch ( MC6850 / timer )
	401	AM_RANGE(0x2A00, 0x2A00) AM_READWRITE(mux_data_r,mux_data_w)// mux
	402	AM_RANGE(0x2A01, 0x2A01) AM_READWRITE(mux_ctrl_r,mux_ctrl_w)// mux status register
	403	AM_RANGE(0x2E00, 0x2E00) AM_READ(irqlatch_r)      // irq latch ( MC6850 / timer )
401	404
402	405	AM_RANGE(0x3000, 0x3000) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
403	406	AM_RANGE(0x3001, 0x3001) AM_READNOP //sound latch
r14845	r14846
409	412	AM_RANGE(0x3406, 0x3406) AM_DEVREAD("acia6850_0", acia6850_device, status_read)
410	413	AM_RANGE(0x3407, 0x3407) AM_DEVREAD("acia6850_0", acia6850_device, data_read)
411	414
412		AM_RANGE(0x3600, 0x3600) AM_WRITE_LEGACY(mux_enable_w)      // mux enable
	415	AM_RANGE(0x3600, 0x3600) AM_WRITE(mux_enable_w)      // mux enable
413	416
414	417	AM_RANGE(0x4000, 0xffff) AM_ROM                  // 48K ROM
415		AM_RANGE(0x8000, 0xFFFF) AM_WRITE_LEGACY(watchdog_w)      // kick watchdog
	418	AM_RANGE(0x8000, 0xFFFF) AM_WRITE(watchdog_w)      // kick watchdog
416	419
417	420	ADDRESS_MAP_END
418	421

src/mame/drivers/ettrivia.c

r14845	r14846
47	47	UINT8 *m_fg_videoram;
48	48	tilemap_t *m_bg_tilemap;
49	49	tilemap_t *m_fg_tilemap;
	50	DECLARE_WRITE8_MEMBER(ettrivia_fg_w);
	51	DECLARE_WRITE8_MEMBER(ettrivia_bg_w);
	52	DECLARE_WRITE8_MEMBER(ettrivia_control_w);
	53	DECLARE_READ8_MEMBER(ettrivia_question_r);
	54	DECLARE_WRITE8_MEMBER(b000_w);
	55	DECLARE_READ8_MEMBER(b000_r);
	56	DECLARE_WRITE8_MEMBER(b800_w);
50	57	};
51	58
52	59
53		static WRITE8_HANDLER( ettrivia_fg_w )
	60	WRITE8_MEMBER(ettrivia_state::ettrivia_fg_w)
54	61	{
55		ettrivia_state *state = space->machine().driver_data<ettrivia_state>();
56		state->m_fg_videoram[offset] = data;
57		state->m_fg_tilemap->mark_tile_dirty(offset);
	62	m_fg_videoram[offset] = data;
	63	m_fg_tilemap->mark_tile_dirty(offset);
58	64	}
59	65
60		static WRITE8_HANDLER( ettrivia_bg_w )
	66	WRITE8_MEMBER(ettrivia_state::ettrivia_bg_w)
61	67	{
62		ettrivia_state *state = space->machine().driver_data<ettrivia_state>();
63		state->m_bg_videoram[offset] = data;
64		state->m_bg_tilemap->mark_tile_dirty(offset);
	68	m_bg_videoram[offset] = data;
	69	m_bg_tilemap->mark_tile_dirty(offset);
65	70	}
66	71
67		static WRITE8_HANDLER( ettrivia_control_w )
	72	WRITE8_MEMBER(ettrivia_state::ettrivia_control_w)
68	73	{
69		ettrivia_state *state = space->machine().driver_data<ettrivia_state>();
70		space->machine().tilemap().mark_all_dirty();
	74	machine().tilemap().mark_all_dirty();
71	75
72		state->m_palreg  = (data >> 1) & 3;
73		state->m_gfx_bank = (data >> 2) & 1;
	76	m_palreg  = (data >> 1) & 3;
	77	m_gfx_bank = (data >> 2) & 1;
74	78
75		state->m_question_bank = (data >> 3) & 3;
	79	m_question_bank = (data >> 3) & 3;
76	80
77		coin_counter_w(space->machine(), 0, data & 0x80);
	81	coin_counter_w(machine(), 0, data & 0x80);
78	82
79		flip_screen_set(space->machine(), data & 1);
	83	flip_screen_set(machine(), data & 1);
80	84	}
81	85
82		static READ8_HANDLER( ettrivia_question_r )
	86	READ8_MEMBER(ettrivia_state::ettrivia_question_r)
83	87	{
84		ettrivia_state *state = space->machine().driver_data<ettrivia_state>();
85		UINT8 *QUESTIONS = space->machine().region("user1")->base();
86		return QUESTIONS[offset + 0x10000 * state->m_question_bank];
	88	UINT8 *QUESTIONS = machine().region("user1")->base();
	89	return QUESTIONS[offset + 0x10000 * m_question_bank];
87	90	}
88	91
89		static WRITE8_HANDLER( b000_w )
	92	WRITE8_MEMBER(ettrivia_state::b000_w)
90	93	{
91		ettrivia_state *state = space->machine().driver_data<ettrivia_state>();
92		state->m_b000_val = data;
	94	m_b000_val = data;
93	95	}
94	96
95		static READ8_HANDLER( b000_r )
	97	READ8_MEMBER(ettrivia_state::b000_r)
96	98	{
97		ettrivia_state *state = space->machine().driver_data<ettrivia_state>();
98		if(state->m_b800_prev)
99		return state->m_b000_ret;
	99	if(m_b800_prev)
	100	return m_b000_ret;
100	101	else
101		return state->m_b000_val;
	102	return m_b000_val;
102	103	}
103	104
104		static WRITE8_HANDLER( b800_w )
	105	WRITE8_MEMBER(ettrivia_state::b800_w)
105	106	{
106		ettrivia_state *state = space->machine().driver_data<ettrivia_state>();
107	107	switch(data)
108	108	{
109	109	/* special case to return the value written to 0xb000 */
110	110	/* does it reset the chips too ? */
111	111	case 0:   break;
112		case 0xc4: state->m_b000_ret = ay8910_r(space->machine().device("ay1"), 0);   break;
113		case 0x94: state->m_b000_ret = ay8910_r(space->machine().device("ay2"), 0);   break;
114		case 0x86: state->m_b000_ret = ay8910_r(space->machine().device("ay3"), 0);   break;
	112	case 0xc4: m_b000_ret = ay8910_r(machine().device("ay1"), 0);   break;
	113	case 0x94: m_b000_ret = ay8910_r(machine().device("ay2"), 0);   break;
	114	case 0x86: m_b000_ret = ay8910_r(machine().device("ay3"), 0);   break;
115	115
116	116	case 0x80:
117		switch(state->m_b800_prev)
	117	switch(m_b800_prev)
118	118	{
119		case 0xe0: ay8910_address_w(space->machine().device("ay1"),0,state->m_b000_val);   break;
120		case 0x98: ay8910_address_w(space->machine().device("ay2"),0,state->m_b000_val);   break;
121		case 0x83: ay8910_address_w(space->machine().device("ay3"),0,state->m_b000_val);   break;
	119	case 0xe0: ay8910_address_w(machine().device("ay1"),0,m_b000_val);   break;
	120	case 0x98: ay8910_address_w(machine().device("ay2"),0,m_b000_val);   break;
	121	case 0x83: ay8910_address_w(machine().device("ay3"),0,m_b000_val);   break;
122	122
123		case 0xa0: ay8910_data_w(space->machine().device("ay1"),0,state->m_b000_val);   break;
124		case 0x88: ay8910_data_w(space->machine().device("ay2"),0,state->m_b000_val);   break;
125		case 0x81: ay8910_data_w(space->machine().device("ay3"),0,state->m_b000_val);   break;
	123	case 0xa0: ay8910_data_w(machine().device("ay1"),0,m_b000_val);   break;
	124	case 0x88: ay8910_data_w(machine().device("ay2"),0,m_b000_val);   break;
	125	case 0x81: ay8910_data_w(machine().device("ay3"),0,m_b000_val);   break;
126	126
127	127	}
128	128	break;
129	129	}
130	130
131		state->m_b800_prev = data;
	131	m_b800_prev = data;
132	132	}
133	133
134	134	static ADDRESS_MAP_START( cpu_map, AS_PROGRAM, 8, ettrivia_state )
135	135	AM_RANGE(0x0000, 0x7fff) AM_ROM
136	136	AM_RANGE(0x8000, 0x87ff) AM_RAM AM_SHARE("nvram")
137		AM_RANGE(0x9000, 0x9000) AM_WRITE_LEGACY(ettrivia_control_w)
	137	AM_RANGE(0x9000, 0x9000) AM_WRITE(ettrivia_control_w)
138	138	AM_RANGE(0x9800, 0x9800) AM_WRITENOP
139	139	AM_RANGE(0xa000, 0xa000) AM_WRITENOP
140		AM_RANGE(0xb000, 0xb000) AM_READ_LEGACY(b000_r) AM_WRITE_LEGACY(b000_w)
141		AM_RANGE(0xb800, 0xb800) AM_WRITE_LEGACY(b800_w)
142		AM_RANGE(0xc000, 0xc7ff) AM_RAM_WRITE_LEGACY(ettrivia_fg_w) AM_BASE(m_fg_videoram)
143		AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE_LEGACY(ettrivia_bg_w) AM_BASE(m_bg_videoram)
	140	AM_RANGE(0xb000, 0xb000) AM_READ(b000_r) AM_WRITE(b000_w)
	141	AM_RANGE(0xb800, 0xb800) AM_WRITE(b800_w)
	142	AM_RANGE(0xc000, 0xc7ff) AM_RAM_WRITE(ettrivia_fg_w) AM_BASE(m_fg_videoram)
	143	AM_RANGE(0xe000, 0xe7ff) AM_RAM_WRITE(ettrivia_bg_w) AM_BASE(m_bg_videoram)
144	144	ADDRESS_MAP_END
145	145
146	146	static ADDRESS_MAP_START( io_map, AS_IO, 8, ettrivia_state )
147		AM_RANGE(0x0000, 0xffff) AM_READ_LEGACY(ettrivia_question_r)
	147	AM_RANGE(0x0000, 0xffff) AM_READ(ettrivia_question_r)
148	148	ADDRESS_MAP_END
149	149
150	150	static INPUT_PORTS_START( ettrivia )

src/mame/drivers/jalmah.c

r14845	r14846
157	157	UINT8 m_oki_rom;
158	158	UINT8 m_oki_bank;
159	159	UINT8 m_oki_za;
	160	DECLARE_WRITE16_MEMBER(sc0_vram_w);
	161	DECLARE_WRITE16_MEMBER(sc3_vram_w);
	162	DECLARE_WRITE16_MEMBER(sc1_vram_w);
	163	DECLARE_WRITE16_MEMBER(sc2_vram_w);
	164	DECLARE_WRITE16_MEMBER(jalmah_tilebank_w);
	165	DECLARE_WRITE16_MEMBER(jalmah_scroll_w);
	166	DECLARE_WRITE16_MEMBER(urashima_bank_w);
	167	DECLARE_WRITE16_MEMBER(urashima_sc0_vram_w);
	168	DECLARE_WRITE16_MEMBER(urashima_sc3_vram_w);
	169	DECLARE_WRITE16_MEMBER(urashima_vregs_w);
	170	DECLARE_WRITE16_MEMBER(urashima_dma_w);
	171	DECLARE_WRITE16_MEMBER(jalmah_okirom_w);
	172	DECLARE_WRITE16_MEMBER(jalmah_okibank_w);
	173	DECLARE_WRITE16_MEMBER(jalmah_flip_screen_w);
	174	DECLARE_READ16_MEMBER(urashima_mcu_r);
	175	DECLARE_WRITE16_MEMBER(urashima_mcu_w);
	176	DECLARE_READ16_MEMBER(daireika_mcu_r);
	177	DECLARE_WRITE16_MEMBER(daireika_mcu_w);
	178	DECLARE_READ16_MEMBER(mjzoomin_mcu_r);
	179	DECLARE_WRITE16_MEMBER(mjzoomin_mcu_w);
	180	DECLARE_READ16_MEMBER(kakumei_mcu_r);
	181	DECLARE_READ16_MEMBER(suchipi_mcu_r);
160	182	};
161	183
162	184
r14845	r14846
472	494	return 0;
473	495	}
474	496
475		static WRITE16_HANDLER( sc0_vram_w )
	497	WRITE16_MEMBER(jalmah_state::sc0_vram_w)
476	498	{
477		jalmah_state *state = space->machine().driver_data<jalmah_state>();
478		COMBINE_DATA(&state->m_sc0_vram[offset]);
	499	COMBINE_DATA(&m_sc0_vram[offset]);
479	500	/*2048x256 tilemap*/
480		state->m_sc0_tilemap_0->mark_tile_dirty(offset);
	501	m_sc0_tilemap_0->mark_tile_dirty(offset);
481	502	/*1024x512 tilemap*/
482		state->m_sc0_tilemap_1->mark_tile_dirty(offset);
	503	m_sc0_tilemap_1->mark_tile_dirty(offset);
483	504	/*512x1024 tilemap*/
484		state->m_sc0_tilemap_2->mark_tile_dirty(offset);
	505	m_sc0_tilemap_2->mark_tile_dirty(offset);
485	506	/*256x2048 tilemap*/
486		state->m_sc0_tilemap_3->mark_tile_dirty(offset);
	507	m_sc0_tilemap_3->mark_tile_dirty(offset);
487	508	}
488	509
489		static WRITE16_HANDLER( sc3_vram_w )
	510	WRITE16_MEMBER(jalmah_state::sc3_vram_w)
490	511	{
491		jalmah_state *state = space->machine().driver_data<jalmah_state>();
492		COMBINE_DATA(&state->m_sc3_vram[offset]);
	512	COMBINE_DATA(&m_sc3_vram[offset]);
493	513	/*2048x256 tilemap*/
494		state->m_sc3_tilemap_0->mark_tile_dirty(offset);
	514	m_sc3_tilemap_0->mark_tile_dirty(offset);
495	515	/*1024x512 tilemap*/
496		state->m_sc3_tilemap_2->mark_tile_dirty(offset);
	516	m_sc3_tilemap_2->mark_tile_dirty(offset);
497	517	/*512x1024 tilemap*/
498		state->m_sc3_tilemap_3->mark_tile_dirty(offset);
	518	m_sc3_tilemap_3->mark_tile_dirty(offset);
499	519	}
500	520
501		static WRITE16_HANDLER( sc1_vram_w )
	521	WRITE16_MEMBER(jalmah_state::sc1_vram_w)
502	522	{
503		jalmah_state *state = space->machine().driver_data<jalmah_state>();
504		COMBINE_DATA(&state->m_sc1_vram[offset]);
	523	COMBINE_DATA(&m_sc1_vram[offset]);
505	524	/*2048x256 tilemap*/
506		state->m_sc1_tilemap_0->mark_tile_dirty(offset);
	525	m_sc1_tilemap_0->mark_tile_dirty(offset);
507	526	/*1024x512 tilemap*/
508		state->m_sc1_tilemap_1->mark_tile_dirty(offset);
	527	m_sc1_tilemap_1->mark_tile_dirty(offset);
509	528	/*512x1024 tilemap*/
510		state->m_sc1_tilemap_2->mark_tile_dirty(offset);
	529	m_sc1_tilemap_2->mark_tile_dirty(offset);
511	530	/*256x2048 tilemap*/
512		state->m_sc1_tilemap_3->mark_tile_dirty(offset);
	531	m_sc1_tilemap_3->mark_tile_dirty(offset);
513	532	}
514	533
515		static WRITE16_HANDLER( sc2_vram_w )
	534	WRITE16_MEMBER(jalmah_state::sc2_vram_w)
516	535	{
517		jalmah_state *state = space->machine().driver_data<jalmah_state>();
518		COMBINE_DATA(&state->m_sc2_vram[offset]);
	536	COMBINE_DATA(&m_sc2_vram[offset]);
519	537	/*2048x256 tilemap*/
520		state->m_sc2_tilemap_0->mark_tile_dirty(offset);
	538	m_sc2_tilemap_0->mark_tile_dirty(offset);
521	539	/*1024x512 tilemap*/
522		state->m_sc2_tilemap_1->mark_tile_dirty(offset);
	540	m_sc2_tilemap_1->mark_tile_dirty(offset);
523	541	/*512x1024 tilemap*/
524		state->m_sc2_tilemap_2->mark_tile_dirty(offset);
	542	m_sc2_tilemap_2->mark_tile_dirty(offset);
525	543	/*256x2048 tilemap*/
526		state->m_sc2_tilemap_3->mark_tile_dirty(offset);
	544	m_sc2_tilemap_3->mark_tile_dirty(offset);
527	545	}
528	546
529		static WRITE16_HANDLER( jalmah_tilebank_w )
	547	WRITE16_MEMBER(jalmah_state::jalmah_tilebank_w)
530	548	{
531		jalmah_state *state = space->machine().driver_data<jalmah_state>();
532	549	/*
533	550	xxxx ---- fg bank (used by suchipi)
534	551	---- xxxx Priority number (trusted,see mjzoomin)
r14845	r14846
536	553	//popmessage("Write to tilebank %02x",data);
537	554	if (ACCESSING_BITS_0_7)
538	555	{
539		if (state->m_sc0bank != ((data & 0xf0) >> 4))
	556	if (m_sc0bank != ((data & 0xf0) >> 4))
540	557	{
541		state->m_sc0bank = (data & 0xf0) >> 4;
542		state->m_sc0_tilemap_0->mark_all_dirty();
543		state->m_sc0_tilemap_1->mark_all_dirty();
544		state->m_sc0_tilemap_2->mark_all_dirty();
545		state->m_sc0_tilemap_3->mark_all_dirty();
	558	m_sc0bank = (data & 0xf0) >> 4;
	559	m_sc0_tilemap_0->mark_all_dirty();
	560	m_sc0_tilemap_1->mark_all_dirty();
	561	m_sc0_tilemap_2->mark_all_dirty();
	562	m_sc0_tilemap_3->mark_all_dirty();
546	563	}
547		if (state->m_pri != (data & 0x0f))
548		state->m_pri = data & 0x0f;
	564	if (m_pri != (data & 0x0f))
	565	m_pri = data & 0x0f;
549	566	}
550	567	}
551	568
552		static WRITE16_HANDLER( jalmah_scroll_w )
	569	WRITE16_MEMBER(jalmah_state::jalmah_scroll_w)
553	570	{
554		jalmah_state *state = space->machine().driver_data<jalmah_state>();
555		UINT16 *jm_scrollram = state->m_jm_scrollram;
556		UINT16 *jm_vregs = state->m_jm_vregs;
	571	UINT16 *jm_scrollram = m_jm_scrollram;
	572	UINT16 *jm_vregs = m_jm_vregs;
557	573	//logerror("[%04x]<-%04x\n",(offset+0x10)*2,data);
558	574	switch(offset+(0x10))
559	575	{
r14845	r14846
579	595	}
580	596	}
581	597
582		static WRITE16_HANDLER( urashima_bank_w )
	598	WRITE16_MEMBER(jalmah_state::urashima_bank_w)
583	599	{
584		jalmah_state *state = space->machine().driver_data<jalmah_state>();
585	600	if (ACCESSING_BITS_0_7)
586	601	{
587		if (state->m_sc0bank != (data & 0x0f))
	602	if (m_sc0bank != (data & 0x0f))
588	603	{
589		state->m_sc0bank = (data & 0x0f);
590		state->m_sc0_tilemap_0->mark_all_dirty();
591		//state->m_sc0_tilemap_2->mark_all_dirty();
592		//state->m_sc0_tilemap_3->mark_all_dirty();
	604	m_sc0bank = (data & 0x0f);
	605	m_sc0_tilemap_0->mark_all_dirty();
	606	//m_sc0_tilemap_2->mark_all_dirty();
	607	//m_sc0_tilemap_3->mark_all_dirty();
593	608	}
594	609	}
595	610	}
596	611
597		static WRITE16_HANDLER( urashima_sc0_vram_w )
	612	WRITE16_MEMBER(jalmah_state::urashima_sc0_vram_w)
598	613	{
599		jalmah_state *state = space->machine().driver_data<jalmah_state>();
600		COMBINE_DATA(&state->m_sc0_vram[offset]);
601		state->m_sc0_tilemap_0->mark_tile_dirty(offset);
	614	COMBINE_DATA(&m_sc0_vram[offset]);
	615	m_sc0_tilemap_0->mark_tile_dirty(offset);
602	616	}
603	617
604		static WRITE16_HANDLER( urashima_sc3_vram_w )
	618	WRITE16_MEMBER(jalmah_state::urashima_sc3_vram_w)
605	619	{
606		jalmah_state *state = space->machine().driver_data<jalmah_state>();
607		COMBINE_DATA(&state->m_sc3_vram[offset]);
608		state->m_sc3_tilemap_0->mark_tile_dirty(offset);
	620	COMBINE_DATA(&m_sc3_vram[offset]);
	621	m_sc3_tilemap_0->mark_tile_dirty(offset);
609	622	}
610	623
611	624	/*Urashima Mahjong uses a bigger (and mostly unused/wasted) video register ram.*/
612		static WRITE16_HANDLER( urashima_vregs_w )
	625	WRITE16_MEMBER(jalmah_state::urashima_vregs_w)
613	626	{
614		jalmah_state *state = space->machine().driver_data<jalmah_state>();
615		UINT16 *jm_scrollram = state->m_jm_scrollram;
616		UINT16 *jm_vregs = state->m_jm_vregs;
	627	UINT16 *jm_scrollram = m_jm_scrollram;
	628	UINT16 *jm_vregs = m_jm_vregs;
617	629	//logerror("[%04x]<-%04x\n",(offset)*2,data);
618	630	switch(offset)
619	631	{
r14845	r14846
685	697	/*Funky "DMA" / protection thing*/
686	698	/*---- -x-- "DMA" execute.*/
687	699	/*---- ---x used too very often,I don't have any clue of what it is,it might just be the source or the destination address.*/
688		static WRITE16_HANDLER( urashima_dma_w )
	700	WRITE16_MEMBER(jalmah_state::urashima_dma_w)
689	701	{
690	702	if(data & 4)
691	703	{
692	704	UINT32 i;
693	705	for(i = 0; i < 0x200; i += 2)
694		space->write_word(0x88200 + i, space->read_word(0x88400 + i));
	706	space.write_word(0x88200 + i, space.read_word(0x88400 + i));
695	707	}
696	708	}
697	709
r14845	r14846
928	940	******************************************************************************************/
929	941
930	942
931		static WRITE16_HANDLER( jalmah_okirom_w )
	943	WRITE16_MEMBER(jalmah_state::jalmah_okirom_w)
932	944	{
933		jalmah_state *state = space->machine().driver_data<jalmah_state>();
934	945	if(ACCESSING_BITS_0_7)
935	946	{
936		UINT8 *oki = space->machine().region("oki")->base();
	947	UINT8 *oki = machine().region("oki")->base();
937	948
938		state->m_oki_rom = data & 1;
	949	m_oki_rom = data & 1;
939	950
940	951	/* ZA appears to be related to the banking, or maybe kakumei2 uses PAL shuffling and this is for something else? */
941		state->m_oki_za = (data & 2) ? 1 : 0;
	952	m_oki_za = (data & 2) ? 1 : 0;
942	953
943		memcpy(&oki[0x20000], &oki[(state->m_oki_rom * 0x80000) + ((state->m_oki_bank+state->m_oki_za) * 0x20000) + 0x40000], 0x20000);
	954	memcpy(&oki[0x20000], &oki[(m_oki_rom * 0x80000) + ((m_oki_bank+m_oki_za) * 0x20000) + 0x40000], 0x20000);
944	955	}
945	956
946		//popmessage("PC=%06x %02x %02x %02x %08x",cpu_get_pc(&space->device()),state->m_oki_rom,state->m_oki_za,state->m_oki_bank,(state->m_oki_rom * 0x80000) + ((state->m_oki_bank+state->m_oki_za) * 0x20000) + 0x40000);
	957	//popmessage("PC=%06x %02x %02x %02x %08x",cpu_get_pc(&space.device()),m_oki_rom,m_oki_za,m_oki_bank,(m_oki_rom * 0x80000) + ((m_oki_bank+m_oki_za) * 0x20000) + 0x40000);
947	958	}
948	959
949		static WRITE16_HANDLER( jalmah_okibank_w )
	960	WRITE16_MEMBER(jalmah_state::jalmah_okibank_w)
950	961	{
951		jalmah_state *state = space->machine().driver_data<jalmah_state>();
952	962	if(ACCESSING_BITS_0_7)
953	963	{
954		UINT8 *oki = space->machine().region("oki")->base();
	964	UINT8 *oki = machine().region("oki")->base();
955	965
956		state->m_oki_bank = data & 3;
	966	m_oki_bank = data & 3;
957	967
958		memcpy(&oki[0x20000], &oki[(state->m_oki_rom * 0x80000) + ((state->m_oki_bank+state->m_oki_za) * 0x20000) + 0x40000], 0x20000);
	968	memcpy(&oki[0x20000], &oki[(m_oki_rom * 0x80000) + ((m_oki_bank+m_oki_za) * 0x20000) + 0x40000], 0x20000);
959	969	}
960	970
961		//popmessage("PC=%06x %02x %02x %02x %08x",cpu_get_pc(&space->device()),state->m_oki_rom,state->m_oki_za,state->m_oki_bank,(state->m_oki_rom * 0x80000) + ((state->m_oki_bank+state->m_oki_za) * 0x20000) + 0x40000);
	971	//popmessage("PC=%06x %02x %02x %02x %08x",cpu_get_pc(&space.device()),m_oki_rom,m_oki_za,m_oki_bank,(m_oki_rom * 0x80000) + ((m_oki_bank+m_oki_za) * 0x20000) + 0x40000);
962	972	}
963	973
964		static WRITE16_HANDLER( jalmah_flip_screen_w )
	974	WRITE16_MEMBER(jalmah_state::jalmah_flip_screen_w)
965	975	{
966	976	/*---- ----x flip screen*/
967		flip_screen_set(space->machine(), data & 1);
	977	flip_screen_set(machine(), data & 1);
968	978
969	979	//  popmessage("%04x",data);
970	980	}
r14845	r14846
974	984	AM_RANGE(0x080000, 0x080001) AM_READ_PORT("SYSTEM")
975	985	AM_RANGE(0x080002, 0x080003) AM_READ_PORT("DSW")
976	986	//       0x080004, 0x080005  MCU read,different for each game
977		AM_RANGE(0x080010, 0x080011) AM_WRITE_LEGACY(jalmah_flip_screen_w)
	987	AM_RANGE(0x080010, 0x080011) AM_WRITE(jalmah_flip_screen_w)
978	988	//       0x080012, 0x080013  MCU write related,same for each game
979	989	//       0x080014, 0x080015  MCU write related,same for each game
980		/**/AM_RANGE(0x080016, 0x080017) AM_RAM_WRITE_LEGACY(jalmah_tilebank_w)
981		AM_RANGE(0x080018, 0x080019) AM_WRITE_LEGACY(jalmah_okibank_w)
982		AM_RANGE(0x08001a, 0x08001b) AM_WRITE_LEGACY(jalmah_okirom_w)
983		/**/AM_RANGE(0x080020, 0x08003f) AM_RAM_WRITE_LEGACY(jalmah_scroll_w)
	990	/**/AM_RANGE(0x080016, 0x080017) AM_RAM_WRITE(jalmah_tilebank_w)
	991	AM_RANGE(0x080018, 0x080019) AM_WRITE(jalmah_okibank_w)
	992	AM_RANGE(0x08001a, 0x08001b) AM_WRITE(jalmah_okirom_w)
	993	/**/AM_RANGE(0x080020, 0x08003f) AM_RAM_WRITE(jalmah_scroll_w)
984	994	AM_RANGE(0x080040, 0x080041) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
985	995	//       0x084000, 0x084001  ?
986	996	AM_RANGE(0x088000, 0x0887ff) AM_RAM_WRITE_LEGACY(paletteram16_RRRRGGGGBBBBRGBx_word_w) AM_BASE_GENERIC(paletteram) /* Palette RAM */
987		AM_RANGE(0x090000, 0x093fff) AM_RAM_WRITE_LEGACY(sc0_vram_w) AM_BASE(m_sc0_vram)
988		AM_RANGE(0x094000, 0x097fff) AM_RAM_WRITE_LEGACY(sc1_vram_w) AM_BASE(m_sc1_vram)
989		AM_RANGE(0x098000, 0x09bfff) AM_RAM_WRITE_LEGACY(sc2_vram_w) AM_BASE(m_sc2_vram)
990		AM_RANGE(0x09c000, 0x09ffff) AM_RAM_WRITE_LEGACY(sc3_vram_w) AM_BASE(m_sc3_vram)
	997	AM_RANGE(0x090000, 0x093fff) AM_RAM_WRITE(sc0_vram_w) AM_BASE(m_sc0_vram)
	998	AM_RANGE(0x094000, 0x097fff) AM_RAM_WRITE(sc1_vram_w) AM_BASE(m_sc1_vram)
	999	AM_RANGE(0x098000, 0x09bfff) AM_RAM_WRITE(sc2_vram_w) AM_BASE(m_sc2_vram)
	1000	AM_RANGE(0x09c000, 0x09ffff) AM_RAM_WRITE(sc3_vram_w) AM_BASE(m_sc3_vram)
991	1001	AM_RANGE(0x0f0000, 0x0f0fff) AM_RAM AM_BASE(m_jm_shared_ram)/*shared with MCU*/
992	1002	AM_RANGE(0x0f1000, 0x0fffff) AM_RAM /*Work Ram*/
993	1003	AM_RANGE(0x100000, 0x10ffff) AM_RAM AM_BASE(m_jm_mcu_code)/*extra RAM for MCU code prg (NOT ON REAL HW!!!)*/
r14845	r14846
998	1008	AM_RANGE(0x080000, 0x080001) AM_READ_PORT("SYSTEM")
999	1009	AM_RANGE(0x080002, 0x080003) AM_READ_PORT("DSW")
1000	1010	//       0x080004, 0x080005  MCU read,different for each game
1001		AM_RANGE(0x080010, 0x080011) AM_WRITE_LEGACY(jalmah_flip_screen_w)
	1011	AM_RANGE(0x080010, 0x080011) AM_WRITE(jalmah_flip_screen_w)
1002	1012	//       0x080012, 0x080013  MCU write related,same for each game
1003	1013	//       0x080014, 0x080015  MCU write related,same for each game
1004		/**/AM_RANGE(0x080016, 0x080017) AM_RAM_WRITE_LEGACY(urashima_dma_w)
1005		AM_RANGE(0x080018, 0x080019) AM_WRITE_LEGACY(jalmah_okibank_w)
1006		AM_RANGE(0x08001a, 0x08001b) AM_WRITE_LEGACY(jalmah_okirom_w)
1007		/**/AM_RANGE(0x08001c, 0x08001d) AM_RAM_WRITE_LEGACY(urashima_bank_w)
	1014	/**/AM_RANGE(0x080016, 0x080017) AM_RAM_WRITE(urashima_dma_w)
	1015	AM_RANGE(0x080018, 0x080019) AM_WRITE(jalmah_okibank_w)
	1016	AM_RANGE(0x08001a, 0x08001b) AM_WRITE(jalmah_okirom_w)
	1017	/**/AM_RANGE(0x08001c, 0x08001d) AM_RAM_WRITE(urashima_bank_w)
1008	1018	AM_RANGE(0x080040, 0x080041) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
1009	1019	//       0x084000, 0x084001  ?
1010	1020	AM_RANGE(0x088000, 0x0887ff) AM_RAM_WRITE_LEGACY(paletteram16_RRRRGGGGBBBBRGBx_word_w) AM_BASE_GENERIC(paletteram) /* Palette RAM */
1011		AM_RANGE(0x090000, 0x093fff) AM_RAM_WRITE_LEGACY(urashima_sc0_vram_w) AM_BASE(m_sc0_vram)
1012		AM_RANGE(0x094000, 0x097fff) AM_RAM_WRITE_LEGACY(urashima_sc0_vram_w)
1013		AM_RANGE(0x098000, 0x09bfff) AM_RAM_WRITE_LEGACY(urashima_sc0_vram_w)
	1021	AM_RANGE(0x090000, 0x093fff) AM_RAM_WRITE(urashima_sc0_vram_w) AM_BASE(m_sc0_vram)
	1022	AM_RANGE(0x094000, 0x097fff) AM_RAM_WRITE(urashima_sc0_vram_w)
	1023	AM_RANGE(0x098000, 0x09bfff) AM_RAM_WRITE(urashima_sc0_vram_w)
1014	1024	//  AM_RANGE(0x094000, 0x097fff) AM_RAM_WRITE_LEGACY(urashima_sc1_vram_w) AM_BASE(m_sc1_vram)/*unused*/
1015	1025	//  AM_RANGE(0x098000, 0x09bfff) AM_RAM_WRITE_LEGACY(urashima_sc2_vram_w) AM_BASE(m_sc2_vram)/*unused*/
1016	1026	/*$9c000-$9cfff Video Registers*/
1017		/**/AM_RANGE(0x09c000, 0x09dfff) AM_WRITE_LEGACY(urashima_vregs_w)
	1027	/**/AM_RANGE(0x09c000, 0x09dfff) AM_WRITE(urashima_vregs_w)
1018	1028	/**///AM_RANGE(0x09c480, 0x09c49f) AM_RAM_WRITE_LEGACY(urashima_sc2vregs_w)
1019		AM_RANGE(0x09e000, 0x0a1fff) AM_RAM_WRITE_LEGACY(urashima_sc3_vram_w) AM_BASE(m_sc3_vram)
	1029	AM_RANGE(0x09e000, 0x0a1fff) AM_RAM_WRITE(urashima_sc3_vram_w) AM_BASE(m_sc3_vram)
1020	1030	AM_RANGE(0x0f0000, 0x0f0fff) AM_RAM AM_BASE(m_jm_shared_ram)/*shared with MCU*/
1021	1031	AM_RANGE(0x0f1000, 0x0fffff) AM_RAM /*Work Ram*/
1022	1032	AM_RANGE(0x100000, 0x10ffff) AM_RAM AM_BASE(m_jm_mcu_code)/*extra RAM for MCU code prg (NOT ON REAL HW!!!)*/
r14845	r14846
1716	1726
1717	1727	******************************************************************************************/
1718	1728
1719		static READ16_HANDLER( urashima_mcu_r )
	1729	READ16_MEMBER(jalmah_state::urashima_mcu_r)
1720	1730	{
1721		jalmah_state *state = space->machine().driver_data<jalmah_state>();
1722	1731	static const int resp[] = {   0x99, 0xd8, 0x00,
1723	1732	0x2a, 0x6a, 0x00,
1724	1733	0x9c, 0xd8, 0x00,
r14845	r14846
1731	1740	0x21, 0x61, 0x00 };
1732	1741	int res;
1733	1742
1734		res = resp[state->m_respcount++];
1735		if (state->m_respcount >= sizeof(resp)/sizeof(resp[0])) state->m_respcount = 0;
	1743	res = resp[m_respcount++];
	1744	if (m_respcount >= sizeof(resp)/sizeof(resp[0])) m_respcount = 0;
1736	1745
1737		//  logerror("%04x: mcu_r %02x\n",cpu_get_pc(&space->device()),res);
	1746	//  logerror("%04x: mcu_r %02x\n",cpu_get_pc(&space.device()),res);
1738	1747
1739	1748	return res;
1740	1749	}
r14845	r14846
1742	1751	/*
1743	1752	data value is REQ under mjzoomin video test menu.It is related to the MCU?
1744	1753	*/
1745		static WRITE16_HANDLER( urashima_mcu_w )
	1754	WRITE16_MEMBER(jalmah_state::urashima_mcu_w)
1746	1755	{
1747		jalmah_state *state = space->machine().driver_data<jalmah_state>();
1748		UINT16 *jm_shared_ram = state->m_jm_shared_ram;
1749		UINT16 *jm_mcu_code = state->m_jm_mcu_code;
	1756	UINT16 *jm_shared_ram = m_jm_shared_ram;
	1757	UINT16 *jm_mcu_code = m_jm_mcu_code;
1750	1758	if(ACCESSING_BITS_0_7 && data)
1751	1759	{
1752	1760	/*******************************************************
r14845	r14846
1936	1944	}
1937	1945	}
1938	1946
1939		static READ16_HANDLER( daireika_mcu_r )
	1947	READ16_MEMBER(jalmah_state::daireika_mcu_r)
1940	1948	{
1941		jalmah_state *state = space->machine().driver_data<jalmah_state>();
1942	1949	static const int resp[] = {   0x99, 0xd8, 0x00,
1943	1950	0x2a, 0x6a, 0x00,
1944	1951	0x9c, 0xd8, 0x00,
r14845	r14846
1951	1958	0x21, 0x61, 0x00 };
1952	1959	int res;
1953	1960
1954		res = resp[state->m_respcount++];
1955		if (state->m_respcount >= sizeof(resp)/sizeof(resp[0])) state->m_respcount = 0;
	1961	res = resp[m_respcount++];
	1962	if (m_respcount >= sizeof(resp)/sizeof(resp[0])) m_respcount = 0;
1956	1963
1957		//  logerror("%04x: mcu_r %02x\n",cpu_get_pc(&space->device()),res);
	1964	//  logerror("%04x: mcu_r %02x\n",cpu_get_pc(&space.device()),res);
1958	1965
1959	1966	return res;
1960	1967	}
r14845	r14846
1965	1972	static const UINT16 dai_mcu_code[0x11] = { 0x33c5, 0x0010, 0x07fe, 0x3a39,0x000f,0x000c,0xda86,0x0245,
1966	1973	0x003f, 0x33c5, 0x000f, 0x000c,0x3a39,0x0010,0x07fe,0x4e75    };
1967	1974
1968		static WRITE16_HANDLER( daireika_mcu_w )
	1975	WRITE16_MEMBER(jalmah_state::daireika_mcu_w)
1969	1976	{
1970		jalmah_state *state = space->machine().driver_data<jalmah_state>();
1971		UINT16 *jm_shared_ram = state->m_jm_shared_ram;
1972		UINT16 *jm_mcu_code = state->m_jm_mcu_code;
	1977	UINT16 *jm_shared_ram = m_jm_shared_ram;
	1978	UINT16 *jm_mcu_code = m_jm_mcu_code;
1973	1979	UINT16 i;
1974	1980
1975	1981	if(ACCESSING_BITS_0_7 && data)
r14845	r14846
2113	2119	jm_shared_ram[0x0128/2] = 0x0010;
2114	2120	jm_shared_ram[0x012a/2] = 0x8980;
2115	2121
2116		//state->m_pri $f0590
	2122	//m_pri $f0590
2117	2123	jm_mcu_code[0x8980/2] = 0x33fc;
2118	2124	jm_mcu_code[0x8982/2] = 0x0006;
2119	2125	jm_mcu_code[0x8984/2] = 0x000f;
2120		jm_mcu_code[0x8986/2] = 0x0590; //move.w #$6,$f0590 (state->m_pri n)
	2126	jm_mcu_code[0x8986/2] = 0x0590; //move.w #$6,$f0590 (m_pri n)
2121	2127	jm_mcu_code[0x8988/2] = 0x4df9;
2122	2128	jm_mcu_code[0x898a/2] = 0x0009;
2123	2129	jm_mcu_code[0x898c/2] = 0xc000; //lea.w #9c000,A6
r14845	r14846
2218	2224	}
2219	2225	}
2220	2226
2221		static READ16_HANDLER( mjzoomin_mcu_r )
	2227	READ16_MEMBER(jalmah_state::mjzoomin_mcu_r)
2222	2228	{
2223		jalmah_state *state = space->machine().driver_data<jalmah_state>();
2224	2229	static const int resp[] = {   0x9c, 0xd8, 0x00,
2225	2230	0x2a, 0x6a, 0x00,
2226	2231	0x99, 0xd8, 0x00,
r14845	r14846
2232	2237	0x21, 0x61, 0x00 };
2233	2238	int res;
2234	2239
2235		res = resp[state->m_respcount++];
2236		if (state->m_respcount >= sizeof(resp)/sizeof(resp[0])) state->m_respcount = 0;
	2240	res = resp[m_respcount++];
	2241	if (m_respcount >= sizeof(resp)/sizeof(resp[0])) m_respcount = 0;
2237	2242
2238		//  logerror("%04x: mcu_r %02x\n",cpu_get_pc(&space->device()),res);
	2243	//  logerror("%04x: mcu_r %02x\n",cpu_get_pc(&space.device()),res);
2239	2244
2240	2245	return res;
2241	2246	}
r14845	r14846
2243	2248	/*
2244	2249	data value is REQ under mjzoomin video test menu.It is related to the MCU?
2245	2250	*/
2246		static WRITE16_HANDLER( mjzoomin_mcu_w )
	2251	WRITE16_MEMBER(jalmah_state::mjzoomin_mcu_w)
2247	2252	{
2248		jalmah_state *state = space->machine().driver_data<jalmah_state>();
2249		UINT16 *jm_shared_ram = state->m_jm_shared_ram;
2250		UINT16 *jm_mcu_code = state->m_jm_mcu_code;
	2253	UINT16 *jm_shared_ram = m_jm_shared_ram;
	2254	UINT16 *jm_mcu_code = m_jm_mcu_code;
2251	2255	if(ACCESSING_BITS_0_7 && data)
2252	2256	{
2253	2257	/******************************************************
r14845	r14846
2357	2361	}
2358	2362	}
2359	2363
2360		static READ16_HANDLER( kakumei_mcu_r )
	2364	READ16_MEMBER(jalmah_state::kakumei_mcu_r)
2361	2365	{
2362		jalmah_state *state = space->machine().driver_data<jalmah_state>();
2363	2366	static const int resp[] = {   0x8a, 0xd8, 0x00,
2364	2367	0x3c, 0x7c, 0x00,
2365	2368	0x99, 0xd8, 0x00,
r14845	r14846
2371	2374	0x3e, 0x7e, 0x00 };
2372	2375	int res;
2373	2376
2374		res = resp[state->m_respcount++];
2375		if (state->m_respcount >= sizeof(resp)/sizeof(resp[0])) state->m_respcount = 0;
	2377	res = resp[m_respcount++];
	2378	if (m_respcount >= sizeof(resp)/sizeof(resp[0])) m_respcount = 0;
2376	2379
2377		//  popmessage("%04x: mcu_r %02x",cpu_get_pc(&space->device()),res);
	2380	//  popmessage("%04x: mcu_r %02x",cpu_get_pc(&space.device()),res);
2378	2381
2379	2382	return res;
2380	2383	}
2381	2384
2382		static READ16_HANDLER( suchipi_mcu_r )
	2385	READ16_MEMBER(jalmah_state::suchipi_mcu_r)
2383	2386	{
2384		jalmah_state *state = space->machine().driver_data<jalmah_state>();
2385	2387	static const int resp[] = {   0x8a, 0xd8, 0x00,
2386	2388	0x3c, 0x7c, 0x00,
2387	2389	0x99, 0xd8, 0x00,
r14845	r14846
2393	2395	0x3e, 0x7e, 0x00 };
2394	2396	int res;
2395	2397
2396		res = resp[state->m_respcount++];
2397		if (state->m_respcount >= sizeof(resp)/sizeof(resp[0])) state->m_respcount = 0;
	2398	res = resp[m_respcount++];
	2399	if (m_respcount >= sizeof(resp)/sizeof(resp[0])) m_respcount = 0;
2398	2400
2399		//  popmessage("%04x: mcu_r %02x",cpu_get_pc(&space->device()),res);
	2401	//  popmessage("%04x: mcu_r %02x",cpu_get_pc(&space.device()),res);
2400	2402
2401	2403	return res;
2402	2404	}
r14845	r14846
2404	2406	static DRIVER_INIT( urashima )
2405	2407	{
2406	2408	jalmah_state *state = machine.driver_data<jalmah_state>();
2407		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x80004, 0x80005, FUNC(urashima_mcu_r) );
2408		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x80012, 0x80013, FUNC(urashima_mcu_w) );
	2409	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x80004, 0x80005, read16_delegate(FUNC(jalmah_state::urashima_mcu_r), state));
	2410	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0x80012, 0x80013, write16_delegate(FUNC(jalmah_state::urashima_mcu_w), state));
2409	2411
2410	2412	state->m_mcu_prg = 0x12;
2411	2413	}
r14845	r14846
2413	2415	static DRIVER_INIT( daireika )
2414	2416	{
2415	2417	jalmah_state *state = machine.driver_data<jalmah_state>();
2416		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x80004, 0x80005, FUNC(daireika_mcu_r) );
2417		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x80012, 0x80013, FUNC(daireika_mcu_w) );
	2418	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x80004, 0x80005, read16_delegate(FUNC(jalmah_state::daireika_mcu_r), state));
	2419	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0x80012, 0x80013, write16_delegate(FUNC(jalmah_state::daireika_mcu_w), state));
2418	2420
2419	2421	state->m_mcu_prg = 0x11;
2420	2422	}
r14845	r14846
2422	2424	static DRIVER_INIT( mjzoomin )
2423	2425	{
2424	2426	jalmah_state *state = machine.driver_data<jalmah_state>();
2425		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x80004, 0x80005, FUNC(mjzoomin_mcu_r) );
2426		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0x80012, 0x80013, FUNC(mjzoomin_mcu_w) );
	2427	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x80004, 0x80005, read16_delegate(FUNC(jalmah_state::mjzoomin_mcu_r), state));
	2428	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0x80012, 0x80013, write16_delegate(FUNC(jalmah_state::mjzoomin_mcu_w), state));
2427	2429
2428	2430	state->m_mcu_prg = 0x13;
2429	2431	}
r14845	r14846
2431	2433	static DRIVER_INIT( kakumei )
2432	2434	{
2433	2435	jalmah_state *state = machine.driver_data<jalmah_state>();
2434		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x80004, 0x80005, FUNC(kakumei_mcu_r) );
2435
	2436	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x80004, 0x80005, read16_delegate(FUNC(jalmah_state::kakumei_mcu_r), state));
2436	2437	state->m_mcu_prg = 0x21;
2437	2438	}
2438	2439
2439	2440	static DRIVER_INIT( kakumei2 )
2440	2441	{
2441	2442	jalmah_state *state = machine.driver_data<jalmah_state>();
2442		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x80004, 0x80005, FUNC(kakumei_mcu_r) );
	2443	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x80004, 0x80005, read16_delegate(FUNC(jalmah_state::kakumei_mcu_r), state));
2443	2444
2444	2445	state->m_mcu_prg = 0x22;
2445	2446	}
r14845	r14846
2447	2448	static DRIVER_INIT( suchipi )
2448	2449	{
2449	2450	jalmah_state *state = machine.driver_data<jalmah_state>();
2450		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x80004, 0x80005, FUNC(suchipi_mcu_r) );
	2451	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x80004, 0x80005, read16_delegate(FUNC(jalmah_state::suchipi_mcu_r), state));
2451	2452
2452	2453	state->m_mcu_prg = 0x23;
2453	2454	}

src/mame/drivers/supdrapo.c

r14845	r14846
75	75	UINT8 *m_col_line;
76	76	UINT8 *m_videoram;
77	77	UINT8 m_wdog;
	78	DECLARE_READ8_MEMBER(sdpoker_rng_r);
	79	DECLARE_WRITE8_MEMBER(wdog8000_w);
	80	DECLARE_WRITE8_MEMBER(debug8004_w);
	81	DECLARE_WRITE8_MEMBER(debug7c00_w);
	82	DECLARE_WRITE8_MEMBER(coinin_w);
	83	DECLARE_WRITE8_MEMBER(payout_w);
78	84	};
79	85
80	86
r14845	r14846
147	153	R/W Handlers
148	154	**********************************************************************/
149	155
150		static READ8_HANDLER( sdpoker_rng_r )
	156	READ8_MEMBER(supdrapo_state::sdpoker_rng_r)
151	157	{
152		return space->machine().rand();
	158	return machine().rand();
153	159	}
154	160
155		static WRITE8_HANDLER( wdog8000_w )
	161	WRITE8_MEMBER(supdrapo_state::wdog8000_w)
156	162	{
157	163	/*  Kind of state watchdog alternating 0x00 & 0x01 writes.
158	164	Used when exit the test mode (writes 2 consecutive 0's).
r14845	r14846
179	185	Watchdog: 00
180	186
181	187	*/
182		supdrapo_state *state = space->machine().driver_data<supdrapo_state>();
183	188
184		if (state->m_wdog == data)
	189
	190	if (m_wdog == data)
185	191	{
186	192	watchdog_reset_w(space, 0, 0);   /* Reset */
187	193	}
188	194
189		state->m_wdog = data;
	195	m_wdog = data;
190	196	//  logerror("Watchdog: %02X\n", data);
191	197	}
192	198
193	199
194		static WRITE8_HANDLER( debug8004_w )
	200	WRITE8_MEMBER(supdrapo_state::debug8004_w)
195	201	{
196	202	/*  Writes 0x00 each time the machine is initialized */
197	203
r14845	r14846
199	205	//  popmessage("written : %02X", data);
200	206	}
201	207
202		static WRITE8_HANDLER( debug7c00_w )
	208	WRITE8_MEMBER(supdrapo_state::debug7c00_w)
203	209	{
204	210	/*  This one write 0's constantly when the input test mode is running */
205	211	logerror("debug7c00: %02X\n", data);
r14845	r14846
210	216	Coin I/O Counters
211	217	**********************************************************************/
212	218
213		static WRITE8_HANDLER( coinin_w )
	219	WRITE8_MEMBER(supdrapo_state::coinin_w)
214	220	{
215		coin_counter_w(space->machine(), 0, data & 0x01);   /* Coin In */
	221	coin_counter_w(machine(), 0, data & 0x01);   /* Coin In */
216	222	}
217	223
218		static WRITE8_HANDLER( payout_w )
	224	WRITE8_MEMBER(supdrapo_state::payout_w)
219	225	{
220		coin_counter_w(space->machine(), 1, data & 0x01);   /* Payout */
	226	coin_counter_w(machine(), 1, data & 0x01);   /* Payout */
221	227	}
222	228
223	229
r14845	r14846
250	256	AM_RANGE(0x6800, 0x6bff) AM_RAM AM_BASE(m_videoram)
251	257	AM_RANGE(0x6c00, 0x6fff) AM_RAM AM_BASE(m_char_bank)
252	258	AM_RANGE(0x7000, 0x7bff) AM_RAM //$7600 seems watchdog
253		AM_RANGE(0x7c00, 0x7c00) AM_WRITE_LEGACY(debug7c00_w)
254		AM_RANGE(0x8000, 0x8000) AM_READ_PORT("IN4") AM_WRITE_LEGACY(wdog8000_w)
	259	AM_RANGE(0x7c00, 0x7c00) AM_WRITE(debug7c00_w)
	260	AM_RANGE(0x8000, 0x8000) AM_READ_PORT("IN4") AM_WRITE(wdog8000_w)
255	261	AM_RANGE(0x8001, 0x8001) AM_READ_PORT("IN0")
256		AM_RANGE(0x8002, 0x8002) AM_READ_PORT("IN1") AM_WRITE_LEGACY(payout_w)
257		AM_RANGE(0x8003, 0x8003) AM_READ_PORT("IN2") AM_WRITE_LEGACY(coinin_w)
258		AM_RANGE(0x8004, 0x8004) AM_READ_PORT("IN3") AM_WRITE_LEGACY(debug8004_w)
	262	AM_RANGE(0x8002, 0x8002) AM_READ_PORT("IN1") AM_WRITE(payout_w)
	263	AM_RANGE(0x8003, 0x8003) AM_READ_PORT("IN2") AM_WRITE(coinin_w)
	264	AM_RANGE(0x8004, 0x8004) AM_READ_PORT("IN3") AM_WRITE(debug8004_w)
259	265	AM_RANGE(0x8005, 0x8005) AM_READ_PORT("SW1")
260	266	AM_RANGE(0x8006, 0x8006) AM_READ_PORT("SW2")
261	267	AM_RANGE(0x9000, 0x90ff) AM_RAM AM_SHARE("nvram")
262		AM_RANGE(0x9400, 0x9400) AM_READ_LEGACY(sdpoker_rng_r)
	268	AM_RANGE(0x9400, 0x9400) AM_READ(sdpoker_rng_r)
263	269	AM_RANGE(0x9800, 0x9801) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
264	270	ADDRESS_MAP_END
265	271

src/mame/drivers/namcos2.c

r14845	r14846
473	473	namcos2_state(const machine_config &mconfig, device_type type, const char *tag)
474	474	: driver_device(mconfig, type, tag)
475	475	{ }
	476	DECLARE_READ16_MEMBER(namcos2_68k_dpram_word_r);
	477	DECLARE_WRITE16_MEMBER(namcos2_68k_dpram_word_w);
	478	DECLARE_READ8_MEMBER(namcos2_dpram_byte_r);
	479	DECLARE_WRITE8_MEMBER(namcos2_dpram_byte_w);
476	480	};
477	481
478	482	static UINT8 *namcos2_dpram;   /* 2Kx8 */
r14845	r14846
536	540	}
537	541	}
538	542
539		static READ16_HANDLER( namcos2_68k_dpram_word_r )
	543	READ16_MEMBER(namcos2_state::namcos2_68k_dpram_word_r)
540	544	{
541	545	return namcos2_dpram[offset];
542	546	}
543	547
544		static WRITE16_HANDLER( namcos2_68k_dpram_word_w )
	548	WRITE16_MEMBER(namcos2_state::namcos2_68k_dpram_word_w)
545	549	{
546	550	if( ACCESSING_BITS_0_7 )
547	551	{
r14845	r14846
570	574	}
571	575
572	576
573		static READ8_HANDLER( namcos2_dpram_byte_r )
	577	READ8_MEMBER(namcos2_state::namcos2_dpram_byte_r)
574	578	{
575	579	return namcos2_dpram[offset];
576	580	}
577	581
578		static WRITE8_HANDLER( namcos2_dpram_byte_w )
	582	WRITE8_MEMBER(namcos2_state::namcos2_dpram_byte_w)
579	583	{
580	584	namcos2_dpram[offset] = data;
581	585	}
r14845	r14846
601	605	AM_RANGE(0x400000, 0x41ffff) AM_READWRITE_LEGACY(namco_tilemapvideoram16_r,namco_tilemapvideoram16_w)
602	606	AM_RANGE(0x420000, 0x42003f) AM_READWRITE_LEGACY(namco_tilemapcontrol16_r,namco_tilemapcontrol16_w)
603	607	AM_RANGE(0x440000, 0x44ffff) AM_READWRITE_LEGACY(namcos2_68k_video_palette_r,namcos2_68k_video_palette_w) AM_BASE_LEGACY(&namcos2_68k_palette_ram) AM_SIZE_LEGACY(&namcos2_68k_palette_size)
604		AM_RANGE(0x460000, 0x460fff) AM_READWRITE_LEGACY(namcos2_68k_dpram_word_r,namcos2_68k_dpram_word_w)
605		AM_RANGE(0x468000, 0x468fff) AM_READWRITE_LEGACY(namcos2_68k_dpram_word_r,namcos2_68k_dpram_word_w) /* mirror */
	608	AM_RANGE(0x460000, 0x460fff) AM_READWRITE(namcos2_68k_dpram_word_r,namcos2_68k_dpram_word_w)
	609	AM_RANGE(0x468000, 0x468fff) AM_READWRITE(namcos2_68k_dpram_word_r,namcos2_68k_dpram_word_w) /* mirror */
606	610	AM_RANGE(0x480000, 0x483fff) AM_READWRITE_LEGACY(namcos2_68k_serial_comms_ram_r,namcos2_68k_serial_comms_ram_w) AM_BASE_LEGACY(&namcos2_68k_serial_comms_ram)
607	611	AM_RANGE(0x4a0000, 0x4a000f) AM_READWRITE_LEGACY(namcos2_68k_serial_comms_ctrl_r,namcos2_68k_serial_comms_ctrl_w)
608	612	ADDRESS_MAP_END
r14845	r14846
747	751	AM_RANGE(0x0000, 0x3fff) AM_ROMBANK("bank6") /* banked */
748	752	AM_RANGE(0x4000, 0x4001) AM_DEVREADWRITE_LEGACY("ymsnd", ym2151_r,ym2151_w)
749	753	AM_RANGE(0x5000, 0x6fff) AM_DEVREADWRITE_LEGACY("c140", c140_r,c140_w)
750		AM_RANGE(0x7000, 0x77ff) AM_READWRITE_LEGACY(namcos2_dpram_byte_r,namcos2_dpram_byte_w) AM_BASE_LEGACY(&namcos2_dpram)
751		AM_RANGE(0x7800, 0x7fff) AM_READWRITE_LEGACY(namcos2_dpram_byte_r,namcos2_dpram_byte_w) /* mirror */
	754	AM_RANGE(0x7000, 0x77ff) AM_READWRITE(namcos2_dpram_byte_r,namcos2_dpram_byte_w) AM_BASE_LEGACY(&namcos2_dpram)
	755	AM_RANGE(0x7800, 0x7fff) AM_READWRITE(namcos2_dpram_byte_r,namcos2_dpram_byte_w) /* mirror */
752	756	AM_RANGE(0x8000, 0x9fff) AM_RAM
753	757	AM_RANGE(0xa000, 0xbfff) AM_WRITENOP /* Amplifier enable on 1st write */
754	758	AM_RANGE(0xc000, 0xc001) AM_WRITE_LEGACY(namcos2_sound_bankselect_w)
r14845	r14846
779	783	AM_RANGE(0x3001, 0x3001) AM_READ_PORT("MCUDI1")
780	784	AM_RANGE(0x3002, 0x3002) AM_READ_PORT("MCUDI2")
781	785	AM_RANGE(0x3003, 0x3003) AM_READ_PORT("MCUDI3")
782		AM_RANGE(0x5000, 0x57ff) AM_READWRITE_LEGACY(namcos2_dpram_byte_r,namcos2_dpram_byte_w) AM_BASE_LEGACY(&namcos2_dpram)
	786	AM_RANGE(0x5000, 0x57ff) AM_READWRITE(namcos2_dpram_byte_r,namcos2_dpram_byte_w) AM_BASE_LEGACY(&namcos2_dpram)
783	787	AM_RANGE(0x6000, 0x6fff) AM_READNOP /* watchdog */
784	788	AM_RANGE(0x8000, 0xffff) AM_ROM
785	789	ADDRESS_MAP_END

src/mame/drivers/thayers.c

r14845	r14846
55	55	int m_cart_present;
56	56	int m_pr7820_enter;
57	57	struct ssi263_t m_ssi263;
	58	DECLARE_WRITE8_MEMBER(intrq_w);
	59	DECLARE_READ8_MEMBER(irqstate_r);
	60	DECLARE_WRITE8_MEMBER(timer_int_ack_w);
	61	DECLARE_WRITE8_MEMBER(data_rdy_int_ack_w);
	62	DECLARE_WRITE8_MEMBER(cop_d_w);
	63	DECLARE_READ8_MEMBER(cop_data_r);
	64	DECLARE_WRITE8_MEMBER(cop_data_w);
	65	DECLARE_READ8_MEMBER(cop_l_r);
	66	DECLARE_WRITE8_MEMBER(cop_l_w);
	67	DECLARE_READ8_MEMBER(cop_g_r);
	68	DECLARE_WRITE8_MEMBER(control_w);
	69	DECLARE_WRITE8_MEMBER(cop_g_w);
	70	DECLARE_READ8_MEMBER(cop_si_r);
	71	DECLARE_WRITE8_MEMBER(cop_so_w);
	72	DECLARE_WRITE8_MEMBER(control2_w);
	73	DECLARE_READ8_MEMBER(dsw_b_r);
	74	DECLARE_READ8_MEMBER(laserdsc_data_r);
	75	DECLARE_WRITE8_MEMBER(laserdsc_data_w);
	76	DECLARE_WRITE8_MEMBER(laserdsc_control_w);
	77	DECLARE_WRITE8_MEMBER(den1_w);
	78	DECLARE_WRITE8_MEMBER(den2_w);
	79	DECLARE_WRITE8_MEMBER(ssi263_register_w);
	80	DECLARE_READ8_MEMBER(ssi263_register_r);
58	81	};
59	82
60	83
r14845	r14846
84	107	cputag_set_input_line(machine, "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
85	108	}
86	109
87		static WRITE8_HANDLER( intrq_w )
	110	WRITE8_MEMBER(thayers_state::intrq_w)
88	111	{
89	112	// T = 1.1 * R30 * C53 = 1.1 * 750K * 0.01uF = 8.25 ms
90	113
91		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ0, HOLD_LINE);
	114	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ0, HOLD_LINE);
92	115
93		space->machine().scheduler().timer_set(attotime::from_usec(8250), FUNC(intrq_tick));
	116	machine().scheduler().timer_set(attotime::from_usec(8250), FUNC(intrq_tick));
94	117	}
95	118
96		static READ8_HANDLER( irqstate_r )
	119	READ8_MEMBER(thayers_state::irqstate_r)
97	120	{
98		thayers_state *state = space->machine().driver_data<thayers_state>();
99	121	/*
100	122
101	123	bit     description
r14845	r14846
111	133
112	134	*/
113	135
114		return (state->m_data_rdy_int << 5) | (state->m_timer_int << 4) | 0x08 | (state->m_ssi_data_request << 2);
	136	return (m_data_rdy_int << 5) | (m_timer_int << 4) | 0x08 | (m_ssi_data_request << 2);
115	137	}
116	138
117		static WRITE8_HANDLER( timer_int_ack_w )
	139	WRITE8_MEMBER(thayers_state::timer_int_ack_w)
118	140	{
119		thayers_state *state = space->machine().driver_data<thayers_state>();
120		state->m_timer_int = 1;
	141	m_timer_int = 1;
121	142
122		check_interrupt(space->machine());
	143	check_interrupt(machine());
123	144	}
124	145
125		static WRITE8_HANDLER( data_rdy_int_ack_w )
	146	WRITE8_MEMBER(thayers_state::data_rdy_int_ack_w)
126	147	{
127		thayers_state *state = space->machine().driver_data<thayers_state>();
128		state->m_data_rdy_int = 1;
	148	m_data_rdy_int = 1;
129	149
130		check_interrupt(space->machine());
	150	check_interrupt(machine());
131	151	}
132	152
133		static WRITE8_HANDLER( cop_d_w )
	153	WRITE8_MEMBER(thayers_state::cop_d_w)
134	154	{
135		thayers_state *state = space->machine().driver_data<thayers_state>();
136	155	/*
137	156
138	157	bit     description
r14845	r14846
146	165
147	166	if (!BIT(data, 0))
148	167	{
149		state->m_timer_int = 0;
	168	m_timer_int = 0;
150	169	}
151	170
152	171	if (!BIT(data, 1))
153	172	{
154		state->m_data_rdy_int = 0;
	173	m_data_rdy_int = 0;
155	174	}
156	175
157		check_interrupt(space->machine());
	176	check_interrupt(machine());
158	177	}
159	178
160	179	/* COP Communication */
161	180
162		static READ8_HANDLER( cop_data_r )
	181	READ8_MEMBER(thayers_state::cop_data_r)
163	182	{
164		thayers_state *state = space->machine().driver_data<thayers_state>();
165		if (!state->m_cop_data_latch_enable)
	183	if (!m_cop_data_latch_enable)
166	184	{
167		return state->m_cop_data_latch;
	185	return m_cop_data_latch;
168	186	}
169	187	else
170	188	{
171		return state->m_cop_l;
	189	return m_cop_l;
172	190	}
173	191	}
174	192
175		static WRITE8_HANDLER( cop_data_w )
	193	WRITE8_MEMBER(thayers_state::cop_data_w)
176	194	{
177		thayers_state *state = space->machine().driver_data<thayers_state>();
178		state->m_cop_data_latch = data;
	195	m_cop_data_latch = data;
179	196	}
180	197
181		static READ8_HANDLER( cop_l_r )
	198	READ8_MEMBER(thayers_state::cop_l_r)
182	199	{
183		thayers_state *state = space->machine().driver_data<thayers_state>();
184		if (!state->m_cop_data_latch_enable)
	200	if (!m_cop_data_latch_enable)
185	201	{
186		return state->m_cop_data_latch;
	202	return m_cop_data_latch;
187	203	}
188	204	else
189	205	{
r14845	r14846
191	207	}
192	208	}
193	209
194		static WRITE8_HANDLER( cop_l_w )
	210	WRITE8_MEMBER(thayers_state::cop_l_w)
195	211	{
196		thayers_state *state = space->machine().driver_data<thayers_state>();
197		state->m_cop_l = data;
	212	m_cop_l = data;
198	213	}
199	214
200		static READ8_HANDLER( cop_g_r )
	215	READ8_MEMBER(thayers_state::cop_g_r)
201	216	{
202		thayers_state *state = space->machine().driver_data<thayers_state>();
203	217	/*
204	218
205	219	bit     description
r14845	r14846
211	225
212	226	*/
213	227
214		return state->m_cop_cmd_latch;
	228	return m_cop_cmd_latch;
215	229	}
216	230
217		static WRITE8_HANDLER( control_w )
	231	WRITE8_MEMBER(thayers_state::control_w)
218	232	{
219		thayers_state *state = space->machine().driver_data<thayers_state>();
220	233	/*
221	234
222	235	bit     description
r14845	r14846
232	245
233	246	*/
234	247
235		state->m_cop_cmd_latch = (data >> 5) & 0x07;
	248	m_cop_cmd_latch = (data >> 5) & 0x07;
236	249	}
237	250
238		static WRITE8_HANDLER( cop_g_w )
	251	WRITE8_MEMBER(thayers_state::cop_g_w)
239	252	{
240		thayers_state *state = space->machine().driver_data<thayers_state>();
241	253	/*
242	254
243	255	bit     description
r14845	r14846
249	261
250	262	*/
251	263
252		state->m_cop_data_latch_enable = BIT(data, 3);
	264	m_cop_data_latch_enable = BIT(data, 3);
253	265	}
254	266
255	267	/* Keyboard */
256	268
257		static READ8_HANDLER(cop_si_r)
	269	READ8_MEMBER(thayers_state::cop_si_r)
258	270	{
259		thayers_state *state = space->machine().driver_data<thayers_state>();
260	271	/* keyboard data */
261	272
262	273	/*
r14845	r14846
267	278
268	279	*/
269	280
270		switch (state->m_rx_bit)
	281	switch (m_rx_bit)
271	282	{
272	283	case 0:
273	284	case 1:
r14845	r14846
275	286	return 1;
276	287
277	288	case 4:
278		return (state->m_keylatch == 9);
	289	return (m_keylatch == 9);
279	290
280	291	case 5:
281	292	case 6:
r14845	r14846
285	296	UINT8 data;
286	297	char port[4];
287	298
288		sprintf(port, "R%d", state->m_keylatch);
	299	sprintf(port, "R%d", m_keylatch);
289	300
290		data = BIT(input_port_read(space->machine(), port), state->m_rx_bit - 5);
	301	data = BIT(input_port_read(machine(), port), m_rx_bit - 5);
291	302
292	303	return data;
293	304	}
r14845	r14846
297	308	}
298	309	}
299	310
300		static WRITE8_HANDLER( cop_so_w )
	311	WRITE8_MEMBER(thayers_state::cop_so_w)
301	312	{
302		thayers_state *state = space->machine().driver_data<thayers_state>();
303	313	/* keyboard clock */
304	314
305	315	if (data)
306	316	{
307		state->m_rx_bit++;
	317	m_rx_bit++;
308	318
309		if (state->m_rx_bit == 10)
	319	if (m_rx_bit == 10)
310	320	{
311		state->m_rx_bit = 0;
	321	m_rx_bit = 0;
312	322
313		state->m_keylatch++;
	323	m_keylatch++;
314	324
315		if (state->m_keylatch == 10)
	325	if (m_keylatch == 10)
316	326	{
317		state->m_keylatch = 0;
	327	m_keylatch = 0;
318	328	}
319	329	}
320	330	}
r14845	r14846
322	332
323	333	/* I/O Board */
324	334
325		static WRITE8_HANDLER( control2_w )
	335	WRITE8_MEMBER(thayers_state::control2_w)
326	336	{
327		thayers_state *state = space->machine().driver_data<thayers_state>();
328	337	/*
329	338
330	339	bit     description
r14845	r14846
340	349
341	350	*/
342	351
343		if ((!BIT(data, 2)) & state->m_cart_present)
	352	if ((!BIT(data, 2)) & m_cart_present)
344	353	{
345		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_NMI, HOLD_LINE);
	354	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_NMI, HOLD_LINE);
346	355	}
347	356	}
348	357
349		static READ8_HANDLER( dsw_b_r )
	358	READ8_MEMBER(thayers_state::dsw_b_r)
350	359	{
351		return (input_port_read(space->machine(), "COIN") & 0xf0) | (input_port_read(space->machine(), "DSWB") & 0x0f);
	360	return (input_port_read(machine(), "COIN") & 0xf0) | (input_port_read(machine(), "DSWB") & 0x0f);
352	361	}
353	362
354		static READ8_HANDLER( laserdsc_data_r )
	363	READ8_MEMBER(thayers_state::laserdsc_data_r)
355	364	{
356		thayers_state *state = space->machine().driver_data<thayers_state>();
357		if (state->m_ldv1000 != NULL) return state->m_ldv1000->status_r();
358		if (state->m_pr7820 != NULL) return state->m_pr7820->data_r();
	365	if (m_ldv1000 != NULL) return m_ldv1000->status_r();
	366	if (m_pr7820 != NULL) return m_pr7820->data_r();
359	367	return 0;
360	368	}
361	369
362		static WRITE8_HANDLER( laserdsc_data_w )
	370	WRITE8_MEMBER(thayers_state::laserdsc_data_w)
363	371	{
364		thayers_state *state = space->machine().driver_data<thayers_state>();
365		state->m_laserdisc_data = data;
	372	m_laserdisc_data = data;
366	373	}
367	374
368		static WRITE8_HANDLER( laserdsc_control_w )
	375	WRITE8_MEMBER(thayers_state::laserdsc_control_w)
369	376	{
370		thayers_state *state = space->machine().driver_data<thayers_state>();
371	377	/*
372	378
373	379	bit     description
r14845	r14846
383	389
384	390	*/
385	391
386		coin_counter_w(space->machine(), 0, BIT(data, 4));
	392	coin_counter_w(machine(), 0, BIT(data, 4));
387	393
388	394	if (BIT(data, 5))
389	395	{
390		if (state->m_ldv1000 != NULL)
	396	if (m_ldv1000 != NULL)
391	397	{
392		state->m_ldv1000->data_w(state->m_laserdisc_data);
393		state->m_ldv1000->enter_w(BIT(data, 7) ? CLEAR_LINE : ASSERT_LINE);
	398	m_ldv1000->data_w(m_laserdisc_data);
	399	m_ldv1000->enter_w(BIT(data, 7) ? CLEAR_LINE : ASSERT_LINE);
394	400	}
395		if (state->m_pr7820 != NULL)
	401	if (m_pr7820 != NULL)
396	402	{
397		state->m_pr7820->data_w(state->m_laserdisc_data);
398		state->m_pr7820_enter = BIT(data, 6) ? CLEAR_LINE : ASSERT_LINE;
399		state->m_pr7820->enter_w(state->m_pr7820_enter);
	403	m_pr7820->data_w(m_laserdisc_data);
	404	m_pr7820_enter = BIT(data, 6) ? CLEAR_LINE : ASSERT_LINE;
	405	m_pr7820->enter_w(m_pr7820_enter);
400	406	// BIT(data, 7) is INT/_EXT, but there is no such input line in laserdsc.h
401	407	}
402	408	}
403	409	}
404	410
405		static WRITE8_HANDLER( den1_w )
	411	WRITE8_MEMBER(thayers_state::den1_w)
406	412	{
407	413	/*
408	414
r14845	r14846
422	428	output_set_digit_value(data >> 4, led_map[data & 0x0f]);
423	429	}
424	430
425		static WRITE8_HANDLER( den2_w )
	431	WRITE8_MEMBER(thayers_state::den2_w)
426	432	{
427	433	/*
428	434
r14845	r14846
467	473	check_interrupt(machine);
468	474	}
469	475
470		static WRITE8_HANDLER( ssi263_register_w )
	476	WRITE8_MEMBER(thayers_state::ssi263_register_w)
471	477	{
472		thayers_state *state = space->machine().driver_data<thayers_state>();
473		struct ssi263_t &ssi263 = state->m_ssi263;
	478	struct ssi263_t &ssi263 = m_ssi263;
474	479	switch (offset)
475	480	{
476	481	case 0:
r14845	r14846
482	487	ssi263.dr = (data >> 5) & 0x03;
483	488	ssi263.p = data & 0x3f;
484	489
485		state->m_ssi_data_request = 1;
486		check_interrupt(space->machine());
	490	m_ssi_data_request = 1;
	491	check_interrupt(machine());
487	492
488	493	switch (ssi263.mode)
489	494	{
490	495	case 0:
491	496	case 1:
492	497	// phoneme timing response
493		space->machine().scheduler().timer_set(attotime::from_usec(phoneme_time), FUNC(ssi263_phoneme_tick));
	498	machine().scheduler().timer_set(attotime::from_usec(phoneme_time), FUNC(ssi263_phoneme_tick));
494	499	break;
495	500	case 2:
496	501	// frame timing response
497		space->machine().scheduler().timer_set(attotime::from_usec(frame_time), FUNC(ssi263_phoneme_tick));
	502	machine().scheduler().timer_set(attotime::from_usec(frame_time), FUNC(ssi263_phoneme_tick));
498	503	break;
499	504	case 3:
500	505	// disable A/_R output
r14845	r14846
570	575	}
571	576	}
572	577
573		static READ8_HANDLER( ssi263_register_r )
	578	READ8_MEMBER(thayers_state::ssi263_register_r)
574	579	{
575		thayers_state *state = space->machine().driver_data<thayers_state>();
576	580	// D7 becomes an output, as the inverted state of A/_R. The register address bits are ignored.
577	581
578		return !state->m_ssi_data_request << 7;
	582	return !m_ssi_data_request << 7;
579	583	}
580	584
581	585	/* Memory Maps */
r14845	r14846
588	592
589	593	static ADDRESS_MAP_START( thayers_io_map, AS_IO, 8, thayers_state )
590	594	ADDRESS_MAP_GLOBAL_MASK(0xff)
591		AM_RANGE(0x00, 0x07) AM_READWRITE_LEGACY(ssi263_register_r, ssi263_register_w)
592		AM_RANGE(0x20, 0x20) AM_WRITE_LEGACY(control_w)
593		AM_RANGE(0x40, 0x40) AM_READWRITE_LEGACY(irqstate_r, control2_w)
594		AM_RANGE(0x80, 0x80) AM_READWRITE_LEGACY(cop_data_r, cop_data_w)
595		AM_RANGE(0xa0, 0xa0) AM_WRITE_LEGACY(timer_int_ack_w)
596		AM_RANGE(0xc0, 0xc0) AM_WRITE_LEGACY(data_rdy_int_ack_w)
597		AM_RANGE(0xf0, 0xf0) AM_READ_LEGACY(laserdsc_data_r)
598		AM_RANGE(0xf1, 0xf1) AM_READ_LEGACY(dsw_b_r)
	595	AM_RANGE(0x00, 0x07) AM_READWRITE(ssi263_register_r, ssi263_register_w)
	596	AM_RANGE(0x20, 0x20) AM_WRITE(control_w)
	597	AM_RANGE(0x40, 0x40) AM_READWRITE(irqstate_r, control2_w)
	598	AM_RANGE(0x80, 0x80) AM_READWRITE(cop_data_r, cop_data_w)
	599	AM_RANGE(0xa0, 0xa0) AM_WRITE(timer_int_ack_w)
	600	AM_RANGE(0xc0, 0xc0) AM_WRITE(data_rdy_int_ack_w)
	601	AM_RANGE(0xf0, 0xf0) AM_READ(laserdsc_data_r)
	602	AM_RANGE(0xf1, 0xf1) AM_READ(dsw_b_r)
599	603	AM_RANGE(0xf2, 0xf2) AM_READ_PORT("DSWA")
600		AM_RANGE(0xf3, 0xf3) AM_WRITE_LEGACY(intrq_w)
601		AM_RANGE(0xf4, 0xf4) AM_WRITE_LEGACY(laserdsc_data_w)
602		AM_RANGE(0xf5, 0xf5) AM_WRITE_LEGACY(laserdsc_control_w)
603		AM_RANGE(0xf6, 0xf6) AM_WRITE_LEGACY(den1_w)
604		AM_RANGE(0xf7, 0xf7) AM_WRITE_LEGACY(den2_w)
	604	AM_RANGE(0xf3, 0xf3) AM_WRITE(intrq_w)
	605	AM_RANGE(0xf4, 0xf4) AM_WRITE(laserdsc_data_w)
	606	AM_RANGE(0xf5, 0xf5) AM_WRITE(laserdsc_control_w)
	607	AM_RANGE(0xf6, 0xf6) AM_WRITE(den1_w)
	608	AM_RANGE(0xf7, 0xf7) AM_WRITE(den2_w)
605	609	ADDRESS_MAP_END
606	610
607	611	static ADDRESS_MAP_START( thayers_cop_io_map, AS_IO, 8, thayers_state )
608		AM_RANGE(COP400_PORT_L, COP400_PORT_L) AM_READWRITE_LEGACY(cop_l_r, cop_l_w)
609		AM_RANGE(COP400_PORT_G, COP400_PORT_G) AM_READWRITE_LEGACY(cop_g_r, cop_g_w)
610		AM_RANGE(COP400_PORT_D, COP400_PORT_D) AM_WRITE_LEGACY(cop_d_w)
	612	AM_RANGE(COP400_PORT_L, COP400_PORT_L) AM_READWRITE(cop_l_r, cop_l_w)
	613	AM_RANGE(COP400_PORT_G, COP400_PORT_G) AM_READWRITE(cop_g_r, cop_g_w)
	614	AM_RANGE(COP400_PORT_D, COP400_PORT_D) AM_WRITE(cop_d_w)
611	615	AM_RANGE(COP400_PORT_SK, COP400_PORT_SK) AM_WRITENOP
612		AM_RANGE(COP400_PORT_SIO, COP400_PORT_SIO) AM_READ_LEGACY(cop_si_r) AM_WRITE_LEGACY(cop_so_w)
	616	AM_RANGE(COP400_PORT_SIO, COP400_PORT_SIO) AM_READ(cop_si_r) AM_WRITE(cop_so_w)
613	617	ADDRESS_MAP_END
614	618
615	619	/* Input Ports */

src/mame/drivers/merit.c

r14845	r14846
70	70	int m_question_address;
71	71	int m_decryption_key;
72	72	UINT8 *m_backup_ram;
	73	DECLARE_READ8_MEMBER(questions_r);
	74	DECLARE_WRITE8_MEMBER(low_offset_w);
	75	DECLARE_WRITE8_MEMBER(med_offset_w);
	76	DECLARE_WRITE8_MEMBER(high_offset_w);
	77	DECLARE_READ8_MEMBER(palette_r);
	78	DECLARE_WRITE8_MEMBER(palette_w);
	79	DECLARE_WRITE8_MEMBER(casino5_bank_w);
73	80	};
74	81
75	82
r14845	r14846
87	94	}
88	95
89	96
90		static READ8_HANDLER( questions_r )
	97	READ8_MEMBER(merit_state::questions_r)
91	98	{
92		merit_state *state = space->machine().driver_data<merit_state>();
93		UINT8 *questions = space->machine().region("user1")->base();
	99	UINT8 *questions = machine().region("user1")->base();
94	100	int address;
95	101
96		switch(state->m_question_address >> 16)
	102	switch(m_question_address >> 16)
97	103	{
98	104	case 0x30: address = 0x00000;
99	105	break;
r14845	r14846
131	137	*          break;
132	138	*/
133	139
134		default: logerror("read unknown question rom: %02X\n",state->m_question_address >> 16);
	140	default: logerror("read unknown question rom: %02X\n",m_question_address >> 16);
135	141	return 0xff;
136	142	}
137	143
138		address |= state->m_question_address & 0xffff;
	144	address |= m_question_address & 0xffff;
139	145
140	146	return questions[address];
141	147	}
142	148
143		static WRITE8_HANDLER( low_offset_w )
	149	WRITE8_MEMBER(merit_state::low_offset_w)
144	150	{
145		merit_state *state = space->machine().driver_data<merit_state>();
146		offset = (offset & 0xf0) | ((offset - state->m_decryption_key) & 0x0f);
	151	offset = (offset & 0xf0) | ((offset - m_decryption_key) & 0x0f);
147	152	offset = BITSWAP8(offset,7,6,5,4,0,1,2,3);
148		state->m_question_address = (state->m_question_address & 0xffff00) | offset;
	153	m_question_address = (m_question_address & 0xffff00) | offset;
149	154	}
150	155
151		static WRITE8_HANDLER( med_offset_w )
	156	WRITE8_MEMBER(merit_state::med_offset_w)
152	157	{
153		merit_state *state = space->machine().driver_data<merit_state>();
154		offset = (offset & 0xf0) | ((offset - state->m_decryption_key) & 0x0f);
	158	offset = (offset & 0xf0) | ((offset - m_decryption_key) & 0x0f);
155	159	offset = BITSWAP8(offset,7,6,5,4,0,1,2,3);
156		state->m_question_address = (state->m_question_address & 0xff00ff) | (offset << 8);
	160	m_question_address = (m_question_address & 0xff00ff) | (offset << 8);
157	161	}
158	162
159		static WRITE8_HANDLER( high_offset_w )
	163	WRITE8_MEMBER(merit_state::high_offset_w)
160	164	{
161		merit_state *state = space->machine().driver_data<merit_state>();
162	165	offset = BITSWAP8(offset,7,6,5,4,0,1,2,3);
163		state->m_question_address = (state->m_question_address & 0x00ffff) | (offset << 16);
	166	m_question_address = (m_question_address & 0x00ffff) | (offset << 16);
164	167	}
165	168
166		static READ8_HANDLER( palette_r )
	169	READ8_MEMBER(merit_state::palette_r)
167	170	{
168		merit_state *state = space->machine().driver_data<merit_state>();
169	171	int co;
170	172
171		co = ((state->m_ram_attr[offset] & 0x7F) << 3) | (offset & 0x07);
172		return state->m_ram_palette[co];
	173	co = ((m_ram_attr[offset] & 0x7F) << 3) | (offset & 0x07);
	174	return m_ram_palette[co];
173	175	}
174	176
175		static WRITE8_HANDLER( palette_w )
	177	WRITE8_MEMBER(merit_state::palette_w)
176	178	{
177		merit_state *state = space->machine().driver_data<merit_state>();
178	179	int co;
179	180
180		space->machine().primary_screen->update_now();
	181	machine().primary_screen->update_now();
181	182	data &= 0x0f;
182	183
183		co = ((state->m_ram_attr[offset] & 0x7F) << 3) | (offset & 0x07);
184		state->m_ram_palette[co] = data;
	184	co = ((m_ram_attr[offset] & 0x7F) << 3) | (offset & 0x07);
	185	m_ram_palette[co] = data;
185	186
186	187	}
187	188
r14845	r14846
326	327	state->m_backup_ram[0x1011] = 0xc9; //ret
327	328	}
328	329
329		static WRITE8_HANDLER(casino5_bank_w)
	330	WRITE8_MEMBER(merit_state::casino5_bank_w)
330	331	{
331	332	if ( data == 0 )
332	333	{
333		memory_set_bank(space->machine(), "bank1", 1);
334		memory_set_bank(space->machine(), "bank2", 1);
	334	memory_set_bank(machine(), "bank1", 1);
	335	memory_set_bank(machine(), "bank2", 1);
335	336	}
336	337	else if ( data == 0xff )
337	338	{
338		memory_set_bank(space->machine(), "bank1", 0);
339		memory_set_bank(space->machine(), "bank2", 0);
	339	memory_set_bank(machine(), "bank1", 0);
	340	memory_set_bank(machine(), "bank2", 0);
340	341	}
341	342	else
342	343	{
r14845	r14846
358	359	AM_RANGE(0xe001, 0xe001) AM_DEVWRITE("crtc", mc6845_device, register_w)
359	360	AM_RANGE(0xe800, 0xefff) AM_RAM AM_BASE(m_ram_attr)
360	361	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(m_ram_video)
361		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(palette_r, palette_w)
	362	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(palette_r, palette_w)
362	363	ADDRESS_MAP_END
363	364
364	365	static ADDRESS_MAP_START( casino5_map, AS_PROGRAM, 8, merit_state )
r14845	r14846
366	367	AM_RANGE(0x2000, 0x3fff) AM_ROMBANK("bank1")
367	368	AM_RANGE(0x4000, 0x5fff) AM_ROMBANK("bank2")
368	369	AM_RANGE(0x6000, 0x6fff) AM_RAM AM_SHARE("nvram")
369		AM_RANGE(0x7000, 0x7000) AM_WRITE_LEGACY(casino5_bank_w)
	370	AM_RANGE(0x7000, 0x7000) AM_WRITE(casino5_bank_w)
370	371	AM_RANGE(0x7001, 0x7fff) AM_RAM
371	372	AM_RANGE(0xa000, 0xa003) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
372	373	AM_RANGE(0xc000, 0xc003) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
r14845	r14846
374	375	AM_RANGE(0xe001, 0xe001) AM_DEVWRITE("crtc", mc6845_device, register_w)
375	376	AM_RANGE(0xe800, 0xefff) AM_RAM AM_BASE(m_ram_attr)
376	377	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(m_ram_video)
377		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(palette_r, palette_w)
	378	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(palette_r, palette_w)
378	379	ADDRESS_MAP_END
379	380
380	381	static ADDRESS_MAP_START( bigappg_map, AS_PROGRAM, 8, merit_state )
r14845	r14846
386	387	AM_RANGE(0xe001, 0xe001) AM_DEVWRITE("crtc", mc6845_device, register_w)
387	388	AM_RANGE(0xe800, 0xefff) AM_RAM AM_BASE(m_ram_attr)
388	389	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(m_ram_video)
389		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(palette_r, palette_w)
	390	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(palette_r, palette_w)
390	391	ADDRESS_MAP_END
391	392
392	393	static ADDRESS_MAP_START( dodge_map, AS_PROGRAM, 8, merit_state )
r14845	r14846
398	399	AM_RANGE(0xe001, 0xe001) AM_DEVWRITE("crtc", mc6845_device, register_w)
399	400	AM_RANGE(0xe800, 0xefff) AM_RAM AM_BASE(m_ram_attr)
400	401	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(m_ram_video)
401		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(palette_r, palette_w)
	402	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(palette_r, palette_w)
402	403	ADDRESS_MAP_END
403	404
404	405	/* Address decoding is done by prom u13 on crt200a hardware. It decodes
r14845	r14846
408	409
409	410	static ADDRESS_MAP_START( trvwhiz_map, AS_PROGRAM, 8, merit_state )
410	411	AM_RANGE(0x0000, 0x3fff) AM_ROM
411		AM_RANGE(0x4c00, 0x4cff) AM_READWRITE_LEGACY(questions_r, high_offset_w)
412		AM_RANGE(0x5400, 0x54ff) AM_WRITE_LEGACY(low_offset_w)
413		AM_RANGE(0x5800, 0x58ff) AM_WRITE_LEGACY(med_offset_w)
	412	AM_RANGE(0x4c00, 0x4cff) AM_READWRITE(questions_r, high_offset_w)
	413	AM_RANGE(0x5400, 0x54ff) AM_WRITE(low_offset_w)
	414	AM_RANGE(0x5800, 0x58ff) AM_WRITE(med_offset_w)
414	415	AM_RANGE(0x6000, 0x67ff) AM_RAM
415	416	AM_RANGE(0xa000, 0xa003) AM_MIRROR(0x1df0) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
416	417	AM_RANGE(0xc000, 0xc003) AM_MIRROR(0x1df0) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
r14845	r14846
418	419	AM_RANGE(0xe001, 0xe001) AM_MIRROR(0x05f0) AM_DEVWRITE("crtc", mc6845_device, register_w)
419	420	AM_RANGE(0xe800, 0xefff) AM_RAM AM_BASE(m_ram_attr)
420	421	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(m_ram_video)
421		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(palette_r, palette_w)
	422	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(palette_r, palette_w)
422	423	ADDRESS_MAP_END
423	424
424	425	static ADDRESS_MAP_START( trvwhiz_io_map, AS_IO, 8, merit_state )
r14845	r14846
432	433	AM_RANGE(0xa000, 0xbfff) AM_RAM
433	434	AM_RANGE(0xc008, 0xc00b) AM_MIRROR(0x1df0) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
434	435	AM_RANGE(0xc00c, 0xc00f) AM_MIRROR(0x1df0) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
435		AM_RANGE(0xce00, 0xceff) AM_READWRITE_LEGACY(questions_r, high_offset_w)
436		AM_RANGE(0xd600, 0xd6ff) AM_WRITE_LEGACY(low_offset_w)
437		AM_RANGE(0xda00, 0xdaff) AM_WRITE_LEGACY(med_offset_w)
	436	AM_RANGE(0xce00, 0xceff) AM_READWRITE(questions_r, high_offset_w)
	437	AM_RANGE(0xd600, 0xd6ff) AM_WRITE(low_offset_w)
	438	AM_RANGE(0xda00, 0xdaff) AM_WRITE(med_offset_w)
438	439	AM_RANGE(0xe000, 0xe000) AM_MIRROR(0x05f0) AM_DEVWRITE("crtc", mc6845_device, address_w)
439	440	AM_RANGE(0xe001, 0xe001) AM_MIRROR(0x05f0) AM_DEVWRITE("crtc", mc6845_device, register_w)
440	441	AM_RANGE(0xe800, 0xefff) AM_RAM AM_BASE(m_ram_attr)
441	442	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(m_ram_video)
442		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(palette_r, palette_w)
	443	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(palette_r, palette_w)
443	444	ADDRESS_MAP_END
444	445
445	446	static ADDRESS_MAP_START( phrcraze_io_map, AS_IO, 8, merit_state )
r14845	r14846
453	454	AM_RANGE(0x8000, 0x9fff) AM_RAM
454	455	AM_RANGE(0xc004, 0xc007) AM_MIRROR(0x1df0) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
455	456	AM_RANGE(0xc008, 0xc00b) AM_MIRROR(0x1df0) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
456		AM_RANGE(0xce00, 0xceff) AM_READWRITE_LEGACY(questions_r, high_offset_w)
457		AM_RANGE(0xd600, 0xd6ff) AM_WRITE_LEGACY(low_offset_w)
458		AM_RANGE(0xda00, 0xdaff) AM_WRITE_LEGACY(med_offset_w)
	457	AM_RANGE(0xce00, 0xceff) AM_READWRITE(questions_r, high_offset_w)
	458	AM_RANGE(0xd600, 0xd6ff) AM_WRITE(low_offset_w)
	459	AM_RANGE(0xda00, 0xdaff) AM_WRITE(med_offset_w)
459	460	AM_RANGE(0xe000, 0xe000) AM_MIRROR(0x05f0) AM_DEVWRITE("crtc", mc6845_device, address_w)
460	461	AM_RANGE(0xe001, 0xe001) AM_MIRROR(0x05f0) AM_DEVWRITE("crtc", mc6845_device, register_w)
461	462	AM_RANGE(0xe800, 0xefff) AM_RAM AM_BASE(m_ram_attr)
462	463	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(m_ram_video)
463		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(palette_r, palette_w)
	464	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(palette_r, palette_w)
464	465	ADDRESS_MAP_END
465	466
466	467	static ADDRESS_MAP_START( tictac_io_map, AS_IO, 8, merit_state )
r14845	r14846
474	475	AM_RANGE(0xa000, 0xbfff) AM_RAM
475	476	AM_RANGE(0xc004, 0xc007) AM_MIRROR(0x1df0) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
476	477	AM_RANGE(0xc008, 0xc00b) AM_MIRROR(0x1df0) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
477		AM_RANGE(0xce00, 0xceff) AM_READWRITE_LEGACY(questions_r, high_offset_w)
478		AM_RANGE(0xd600, 0xd6ff) AM_WRITE_LEGACY(low_offset_w)
479		AM_RANGE(0xda00, 0xdaff) AM_WRITE_LEGACY(med_offset_w)
	478	AM_RANGE(0xce00, 0xceff) AM_READWRITE(questions_r, high_offset_w)
	479	AM_RANGE(0xd600, 0xd6ff) AM_WRITE(low_offset_w)
	480	AM_RANGE(0xda00, 0xdaff) AM_WRITE(med_offset_w)
480	481	AM_RANGE(0xe000, 0xe000) AM_MIRROR(0x05f0) AM_DEVWRITE("crtc", mc6845_device, address_w)
481	482	AM_RANGE(0xe001, 0xe001) AM_MIRROR(0x05f0) AM_DEVWRITE("crtc", mc6845_device, register_w)
482	483	AM_RANGE(0xe800, 0xefff) AM_RAM AM_BASE(m_ram_attr)
483	484	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(m_ram_video)
484		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(palette_r, palette_w)
	485	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(palette_r, palette_w)
485	486	ADDRESS_MAP_END
486	487
487	488	static ADDRESS_MAP_START( dtrvwz5_map, AS_PROGRAM, 8, merit_state )
r14845	r14846
490	491	AM_RANGE(0xb000, 0xb0ff) AM_ROM /* protection? code jumps here */
491	492	AM_RANGE(0xc004, 0xc007) AM_MIRROR(0x1df0) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
492	493	AM_RANGE(0xc008, 0xc00b) AM_MIRROR(0x1df0) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
493		AM_RANGE(0xce00, 0xceff) AM_READWRITE_LEGACY(questions_r, high_offset_w)
494		AM_RANGE(0xd600, 0xd6ff) AM_WRITE_LEGACY(low_offset_w)
495		AM_RANGE(0xda00, 0xdaff) AM_WRITE_LEGACY(med_offset_w)
	494	AM_RANGE(0xce00, 0xceff) AM_READWRITE(questions_r, high_offset_w)
	495	AM_RANGE(0xd600, 0xd6ff) AM_WRITE(low_offset_w)
	496	AM_RANGE(0xda00, 0xdaff) AM_WRITE(med_offset_w)
496	497	AM_RANGE(0xe000, 0xe000) AM_MIRROR(0x05f0) AM_DEVWRITE("crtc", mc6845_device, address_w)
497	498	AM_RANGE(0xe001, 0xe001) AM_MIRROR(0x05f0) AM_DEVWRITE("crtc", mc6845_device, register_w)
498	499	AM_RANGE(0xe800, 0xefff) AM_RAM AM_BASE(m_ram_attr)
499	500	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(m_ram_video)
500		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(palette_r, palette_w)
	501	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(palette_r, palette_w)
501	502	ADDRESS_MAP_END
502	503
503	504	static ADDRESS_MAP_START( couple_map, AS_PROGRAM, 8, merit_state )
r14845	r14846
510	511	AM_RANGE(0xe001, 0xe001) AM_DEVWRITE("crtc", mc6845_device, register_w)
511	512	AM_RANGE(0xe800, 0xefff) AM_RAM AM_BASE(m_ram_attr)
512	513	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(m_ram_video)
513		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(palette_r, palette_w)
	514	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(palette_r, palette_w)
514	515	ADDRESS_MAP_END
515	516
516	517

src/mame/drivers/dotrikun.c

r14845	r14846
35	35
36	36	/* video-related */
37	37	UINT8          m_color;
	38	DECLARE_WRITE8_MEMBER(dotrikun_color_w);
38	39	};
39	40
40	41
r14845	r14846
44	45	*
45	46	*************************************/
46	47
47		static WRITE8_HANDLER( dotrikun_color_w )
	48	WRITE8_MEMBER(dotrikun_state::dotrikun_color_w)
48	49	{
49		dotrikun_state *state = space->machine().driver_data<dotrikun_state>();
50	50	/*
51	51	x--- ---- screen color swap?
52	52	---- -x-- B
r14845	r14846
54	54	---- ---x R
55	55	*/
56	56
57		state->m_color = data;
58		space->machine().primary_screen->update_partial(space->machine().primary_screen->vpos());
	57	m_color = data;
	58	machine().primary_screen->update_partial(machine().primary_screen->vpos());
59	59	}
60	60
61	61
r14845	r14846
104	104
105	105	static ADDRESS_MAP_START( io_map, AS_IO, 8, dotrikun_state )
106	106	ADDRESS_MAP_GLOBAL_MASK(0xff)
107		AM_RANGE(0x00, 0x00) AM_READ_PORT("INPUTS") AM_WRITE_LEGACY(dotrikun_color_w)
	107	AM_RANGE(0x00, 0x00) AM_READ_PORT("INPUTS") AM_WRITE(dotrikun_color_w)
108	108	ADDRESS_MAP_END
109	109
110	110

src/mame/drivers/sms.c

r14845	r14846
230	230	UINT8 m_communication_port_status;
231	231	bitmap_ind16 m_bitmap;
232	232	UINT8 m_vid_regs[7];
	233	DECLARE_WRITE8_MEMBER(bankswitch_w);
	234	DECLARE_READ8_MEMBER(link_r);
	235	DECLARE_WRITE8_MEMBER(link_w);
	236	DECLARE_READ8_MEMBER(z80_8088_r);
	237	DECLARE_READ8_MEMBER(p03_r);
	238	DECLARE_WRITE8_MEMBER(p03_w);
	239	DECLARE_WRITE8_MEMBER(video_w);
233	240	};
234	241
235	242
r14845	r14846
239	246	*
240	247	*************************************/
241	248
242		static WRITE8_HANDLER(bankswitch_w)
	249	WRITE8_MEMBER(smsmfg_state::bankswitch_w)
243	250	{
244		memory_set_bank(space->machine(), "bank1", data);
	251	memory_set_bank(machine(), "bank1", data);
245	252	}
246	253
247	254	/*************************************
r14845	r14846
250	257	*
251	258	*************************************/
252	259
253		static READ8_HANDLER(link_r)
	260	READ8_MEMBER(smsmfg_state::link_r)
254	261	{
255		smsmfg_state *state = space->machine().driver_data<smsmfg_state>();
256	262	switch(offset)
257	263	{
258	264	case 0:
259		state->m_communication_port_status &= ~0x01;
260		return state->m_communication_port[0];
	265	m_communication_port_status &= ~0x01;
	266	return m_communication_port[0];
261	267	case 1:
262		state->m_communication_port_status &= ~0x02;
263		return state->m_communication_port[1];
	268	m_communication_port_status &= ~0x02;
	269	return m_communication_port[1];
264	270	case 2:
265		return state->m_communication_port_status;
	271	return m_communication_port_status;
266	272	}
267	273	return 0;
268	274	};
269	275
270		static WRITE8_HANDLER(link_w)
	276	WRITE8_MEMBER(smsmfg_state::link_w)
271	277	{
272		smsmfg_state *state = space->machine().driver_data<smsmfg_state>();
273	278	switch(offset)
274	279	{
275	280	case 0:
276		state->m_communication_port_status |= 0x08;
277		state->m_communication_port[3] = data;
	281	m_communication_port_status |= 0x08;
	282	m_communication_port[3] = data;
278	283	break;
279	284	case 1:
280		state->m_communication_port_status |= 0x04;
281		state->m_communication_port[2] = data;
	285	m_communication_port_status |= 0x04;
	286	m_communication_port[2] = data;
282	287	break;
283	288	}
284	289	}
285	290
286		static READ8_HANDLER(z80_8088_r)
	291	READ8_MEMBER(smsmfg_state::z80_8088_r)
287	292	{
288		smsmfg_state *state = space->machine().driver_data<smsmfg_state>();
289		return state->m_communication_port_status;
	293	return m_communication_port_status;
290	294	}
291	295
292		static READ8_HANDLER(p03_r)
	296	READ8_MEMBER(smsmfg_state::p03_r)
293	297	{
294		smsmfg_state *state = space->machine().driver_data<smsmfg_state>();
295	298	switch(offset)
296	299	{
297	300	case 0:
298		state->m_communication_port_status &= ~0x08;
299		return state->m_communication_port[3];
	301	m_communication_port_status &= ~0x08;
	302	return m_communication_port[3];
300	303	case 1:
301		state->m_communication_port_status &= ~0x04;
302		return state->m_communication_port[2];
	304	m_communication_port_status &= ~0x04;
	305	return m_communication_port[2];
303	306	}
304	307	return 0;
305	308	}
306	309
307		static WRITE8_HANDLER(p03_w)
	310	WRITE8_MEMBER(smsmfg_state::p03_w)
308	311	{
309		smsmfg_state *state = space->machine().driver_data<smsmfg_state>();
310	312	switch(offset)
311	313	{
312	314	case 0:
313		state->m_communication_port_status |= 0x01;
314		state->m_communication_port[0] = data;
	315	m_communication_port_status |= 0x01;
	316	m_communication_port[0] = data;
315	317	break;
316	318	case 1:
317		state->m_communication_port_status |= 0x02;
318		state->m_communication_port[1] = data;
	319	m_communication_port_status |= 0x02;
	320	m_communication_port[1] = data;
319	321	break;
320	322	}
321	323	}
r14845	r14846
432	434	*
433	435	*************************************/
434	436
435		static WRITE8_HANDLER(video_w)
	437	WRITE8_MEMBER(smsmfg_state::video_w)
436	438	{
437		smsmfg_state *state = space->machine().driver_data<smsmfg_state>();
438		state->m_vid_regs[offset] = data;
	439	m_vid_regs[offset] = data;
439	440	if ( offset == 5 )
440	441	{
441	442	int x,y;
442		int xstart = state->m_vid_regs[0] + state->m_vid_regs[1]*256;
443		int width = state->m_vid_regs[2];
444		int ystart = state->m_vid_regs[3];
445		int height = state->m_vid_regs[4];
446		int color = state->m_vid_regs[5];
	443	int xstart = m_vid_regs[0] + m_vid_regs[1]*256;
	444	int width = m_vid_regs[2];
	445	int ystart = m_vid_regs[3];
	446	int height = m_vid_regs[4];
	447	int color = m_vid_regs[5];
447	448
448	449	if ( height == 0 )
449	450	height = 256;
r14845	r14846
456	457	for ( x = xstart; x < xstart + width; x++ )
457	458	{
458	459	if ( y < 256 )
459		state->m_bitmap.pix16(y, x) = color;
	460	m_bitmap.pix16(y, x) = color;
460	461	}
461	462	}
462	463	}
r14845	r14846
497	498	static ADDRESS_MAP_START( sms_map, AS_PROGRAM, 8, smsmfg_state )
498	499	AM_RANGE(0x00000, 0x007ff) AM_RAM AM_SHARE("nvram")
499	500	AM_RANGE(0x00800, 0x00803) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
500		AM_RANGE(0x01000, 0x01007) AM_WRITE_LEGACY(video_w)
501		AM_RANGE(0x01800, 0x01803) AM_READWRITE_LEGACY(link_r, link_w)
	501	AM_RANGE(0x01000, 0x01007) AM_WRITE(video_w)
	502	AM_RANGE(0x01800, 0x01803) AM_READWRITE(link_r, link_w)
502	503	AM_RANGE(0x04000, 0x07fff) AM_ROMBANK("bank1")
503		AM_RANGE(0x04000, 0x04000) AM_WRITE_LEGACY(bankswitch_w)
	504	AM_RANGE(0x04000, 0x04000) AM_WRITE(bankswitch_w)
504	505	AM_RANGE(0x08000, 0x0ffff) AM_ROM
505	506	AM_RANGE(0xf8000, 0xfffff) AM_ROM // mirror for vectors
506	507	ADDRESS_MAP_END
507	508
508	509	static ADDRESS_MAP_START( sureshot_map, AS_PROGRAM, 8, smsmfg_state )
509	510	AM_RANGE(0x00000, 0x007ff) AM_RAM AM_SHARE("nvram")
510		AM_RANGE(0x02000, 0x02007) AM_WRITE_LEGACY(video_w)
	511	AM_RANGE(0x02000, 0x02007) AM_WRITE(video_w)
511	512	AM_RANGE(0x03000, 0x03003) AM_DEVREADWRITE_LEGACY("ppi8255_0", ppi8255_r, ppi8255_w)
512		AM_RANGE(0x03800, 0x03803) AM_READWRITE_LEGACY(link_r, link_w)
	513	AM_RANGE(0x03800, 0x03803) AM_READWRITE(link_r, link_w)
513	514	AM_RANGE(0x08000, 0x0ffff) AM_ROM
514	515	AM_RANGE(0xf8000, 0xfffff) AM_ROM // mirror for vectors
515	516	ADDRESS_MAP_END
r14845	r14846
519	520	AM_RANGE(0x2000, 0x27ff) AM_RAM
520	521	AM_RANGE(0x3100, 0x3103) AM_DEVREADWRITE_LEGACY("ppi8255_1", ppi8255_r, ppi8255_w)
521	522	AM_RANGE(0x3381, 0x3382) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
522		AM_RANGE(0x3400, 0x3400) AM_READ_LEGACY(z80_8088_r)
523		AM_RANGE(0x3500, 0x3501) AM_READWRITE_LEGACY(p03_r, p03_w)
	523	AM_RANGE(0x3400, 0x3400) AM_READ(z80_8088_r)
	524	AM_RANGE(0x3500, 0x3501) AM_READWRITE(p03_r, p03_w)
524	525	ADDRESS_MAP_END
525	526
526	527	/*************************************

src/mame/drivers/spoker.c

r14845	r14846
40	40	int m_hopper;
41	41	UINT8 m_igs_magic[2];
42	42	UINT8 m_out[3];
	43	DECLARE_WRITE8_MEMBER(bg_tile_w);
	44	DECLARE_WRITE8_MEMBER(fg_tile_w);
	45	DECLARE_WRITE8_MEMBER(fg_color_w);
	46	DECLARE_WRITE8_MEMBER(spoker_nmi_and_coins_w);
	47	DECLARE_WRITE8_MEMBER(spoker_video_and_leds_w);
	48	DECLARE_WRITE8_MEMBER(spoker_leds_w);
	49	DECLARE_WRITE8_MEMBER(spoker_magic_w);
	50	DECLARE_READ8_MEMBER(spoker_magic_r);
43	51	};
44	52
45		static WRITE8_HANDLER( bg_tile_w )
	53	WRITE8_MEMBER(spoker_state::bg_tile_w)
46	54	{
47		spoker_state *state = space->machine().driver_data<spoker_state>();
48	55
49		state->m_bg_tile_ram[offset] = data;
50		state->m_bg_tilemap->mark_tile_dirty(offset);
	56	m_bg_tile_ram[offset] = data;
	57	m_bg_tilemap->mark_tile_dirty(offset);
51	58	}
52	59
53	60	static TILE_GET_INFO( get_bg_tile_info )
r14845	r14846
64	71	SET_TILE_INFO(0, code, (4*(code >> 14)+3), 0);
65	72	}
66	73
67		static WRITE8_HANDLER( fg_tile_w )
	74	WRITE8_MEMBER(spoker_state::fg_tile_w)
68	75	{
69		spoker_state *state = space->machine().driver_data<spoker_state>();
70	76
71		state->m_fg_tile_ram[offset] = data;
72		state->m_fg_tilemap->mark_tile_dirty(offset);
	77	m_fg_tile_ram[offset] = data;
	78	m_fg_tilemap->mark_tile_dirty(offset);
73	79	}
74	80
75		static WRITE8_HANDLER( fg_color_w )
	81	WRITE8_MEMBER(spoker_state::fg_color_w)
76	82	{
77		spoker_state *state = space->machine().driver_data<spoker_state>();
78	83
79		state->m_fg_color_ram[offset] = data;
80		state->m_fg_tilemap->mark_tile_dirty(offset);
	84	m_fg_color_ram[offset] = data;
	85	m_fg_tilemap->mark_tile_dirty(offset);
81	86	}
82	87
83	88	static VIDEO_START(spoker)
r14845	r14846
119	124	#endif
120	125	}
121	126
122		static WRITE8_HANDLER( spoker_nmi_and_coins_w )
	127	WRITE8_MEMBER(spoker_state::spoker_nmi_and_coins_w)
123	128	{
124		spoker_state *state = space->machine().driver_data<spoker_state>();
125	129
126	130	if ((data) & (0x22))
127	131	{
128		logerror("PC %06X: nmi_and_coins = %02x\n",cpu_get_pc(&space->device()),data);
	132	logerror("PC %06X: nmi_and_coins = %02x\n",cpu_get_pc(&space.device()),data);
129	133	//      popmessage("%02x",data);
130	134	}
131	135
132		coin_counter_w(space->machine(), 0,      data & 0x01);   // coin_a
133		coin_counter_w(space->machine(), 1,      data & 0x04);   // coin_c
134		coin_counter_w(space->machine(), 2,      data & 0x08);   // key in
135		coin_counter_w(space->machine(), 3,      data & 0x10);   // coin out mech
	136	coin_counter_w(machine(), 0,      data & 0x01);   // coin_a
	137	coin_counter_w(machine(), 1,      data & 0x04);   // coin_c
	138	coin_counter_w(machine(), 2,      data & 0x08);   // key in
	139	coin_counter_w(machine(), 3,      data & 0x10);   // coin out mech
136	140
137		set_led_status(space->machine(), 6,      data & 0x40);   // led for coin out / hopper active
	141	set_led_status(machine(), 6,      data & 0x40);   // led for coin out / hopper active
138	142
139		if(((state->m_nmi_ack & 0x80) == 0) && data & 0x80)
140		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
	143	if(((m_nmi_ack & 0x80) == 0) && data & 0x80)
	144	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_NMI, CLEAR_LINE);
141	145
142		state->m_nmi_ack = data & 0x80;     // nmi acknowledge, 0 -> 1
	146	m_nmi_ack = data & 0x80;     // nmi acknowledge, 0 -> 1
143	147
144		state->m_out[0] = data;
145		show_out(state->m_out);
	148	m_out[0] = data;
	149	show_out(m_out);
146	150	}
147	151
148		static WRITE8_HANDLER( spoker_video_and_leds_w )
	152	WRITE8_MEMBER(spoker_state::spoker_video_and_leds_w)
149	153	{
150		spoker_state *state = space->machine().driver_data<spoker_state>();
151	154
152		set_led_status(space->machine(), 4,     data & 0x01);   // start?
153		set_led_status(space->machine(), 5,     data & 0x04);   // l_bet?
	155	set_led_status(machine(), 4,     data & 0x01);   // start?
	156	set_led_status(machine(), 5,     data & 0x04);   // l_bet?
154	157
155		state->m_video_enable   =     data & 0x40;
156		state->m_hopper         =   (~data)& 0x80;
	158	m_video_enable   =     data & 0x40;
	159	m_hopper         =   (~data)& 0x80;
157	160
158		state->m_out[1] = data;
159		show_out(state->m_out);
	161	m_out[1] = data;
	162	show_out(m_out);
160	163	}
161	164
162		static WRITE8_HANDLER( spoker_leds_w )
	165	WRITE8_MEMBER(spoker_state::spoker_leds_w)
163	166	{
164		spoker_state *state = space->machine().driver_data<spoker_state>();
165	167
166		set_led_status(space->machine(), 0, data & 0x01);   // stop_1
167		set_led_status(space->machine(), 1, data & 0x02);   // stop_2
168		set_led_status(space->machine(), 2, data & 0x04);   // stop_3
169		set_led_status(space->machine(), 3, data & 0x08);   // stop
	168	set_led_status(machine(), 0, data & 0x01);   // stop_1
	169	set_led_status(machine(), 1, data & 0x02);   // stop_2
	170	set_led_status(machine(), 2, data & 0x04);   // stop_3
	171	set_led_status(machine(), 3, data & 0x08);   // stop
170	172	// data & 0x10?
171	173
172		state->m_out[2] = data;
173		show_out(state->m_out);
	174	m_out[2] = data;
	175	show_out(m_out);
174	176	}
175	177
176		static WRITE8_HANDLER( spoker_magic_w )
	178	WRITE8_MEMBER(spoker_state::spoker_magic_w)
177	179	{
178		spoker_state *state = space->machine().driver_data<spoker_state>();
179	180
180		state->m_igs_magic[offset] = data;
	181	m_igs_magic[offset] = data;
181	182
182	183	if (offset == 0)
183	184	return;
184	185
185		switch(state->m_igs_magic[0])
	186	switch(m_igs_magic[0])
186	187	{
187	188	case 0x01:
188	189	break;
189	190
190	191	default:
191	192	//          popmessage("magic %x <- %04x",igs_magic[0],data);
192		logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[0], data);
	193	logerror("%06x: warning, writing to igs_magic %02x = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[0], data);
193	194	}
194	195	}
195	196
196		static READ8_HANDLER( spoker_magic_r )
	197	READ8_MEMBER(spoker_state::spoker_magic_r)
197	198	{
198		spoker_state *state = space->machine().driver_data<spoker_state>();
199	199
200		switch(state->m_igs_magic[0])
	200	switch(m_igs_magic[0])
201	201	{
202	202	case 0x00:
203		if ( !(state->m_igs_magic[1] & 0x01) )   return input_port_read(space->machine(), "DSW1");
204		if ( !(state->m_igs_magic[1] & 0x02) )   return input_port_read(space->machine(), "DSW2");
205		if ( !(state->m_igs_magic[1] & 0x04) )   return input_port_read(space->machine(), "DSW3");
206		if ( !(state->m_igs_magic[1] & 0x08) )   return input_port_read(space->machine(), "DSW4");
207		if ( !(state->m_igs_magic[1] & 0x10) )   return input_port_read(space->machine(), "DSW5");
208		logerror("%06x: warning, reading dsw with igs_magic[1] = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[1]);
	203	if ( !(m_igs_magic[1] & 0x01) )   return input_port_read(machine(), "DSW1");
	204	if ( !(m_igs_magic[1] & 0x02) )   return input_port_read(machine(), "DSW2");
	205	if ( !(m_igs_magic[1] & 0x04) )   return input_port_read(machine(), "DSW3");
	206	if ( !(m_igs_magic[1] & 0x08) )   return input_port_read(machine(), "DSW4");
	207	if ( !(m_igs_magic[1] & 0x10) )   return input_port_read(machine(), "DSW5");
	208	logerror("%06x: warning, reading dsw with igs_magic[1] = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[1]);
209	209	break;
210	210
211	211	default:
212		logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(&space->device()), state->m_igs_magic[0]);
	212	logerror("%06x: warning, reading with igs_magic = %02x\n", cpu_get_pc(&space.device()), m_igs_magic[0]);
213	213	}
214	214
215	215	return 0;
r14845	r14846
229	229	AM_RANGE( 0x2000, 0x23ff ) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split1_w ) AM_BASE_GENERIC( paletteram )
230	230	AM_RANGE( 0x2400, 0x27ff ) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split2_w ) AM_BASE_GENERIC( paletteram2 )
231	231
232		AM_RANGE( 0x3000, 0x33ff ) AM_RAM_WRITE_LEGACY(bg_tile_w ) AM_BASE(m_bg_tile_ram )
	232	AM_RANGE( 0x3000, 0x33ff ) AM_RAM_WRITE(bg_tile_w ) AM_BASE(m_bg_tile_ram )
233	233
234		AM_RANGE( 0x5000, 0x5fff ) AM_RAM_WRITE_LEGACY(fg_tile_w )  AM_BASE(m_fg_tile_ram )
	234	AM_RANGE( 0x5000, 0x5fff ) AM_RAM_WRITE(fg_tile_w )  AM_BASE(m_fg_tile_ram )
235	235
236	236	/* TODO: ppi #1 */
237		AM_RANGE( 0x6480, 0x6480 ) AM_WRITE_LEGACY(spoker_nmi_and_coins_w )
	237	AM_RANGE( 0x6480, 0x6480 ) AM_WRITE(spoker_nmi_and_coins_w )
238	238	AM_RANGE( 0x6481, 0x6481 ) AM_READ_PORT( "SERVICE" )
239	239	AM_RANGE( 0x6482, 0x6482 ) AM_READ_PORT( "COINS" )
240	240
241	241	/* TODO: ppi #2 */
242	242	AM_RANGE( 0x6490, 0x6490 ) AM_READ_PORT( "BUTTONS1" )
243		AM_RANGE( 0x6491, 0x6491 ) AM_WRITE_LEGACY(spoker_video_and_leds_w )
244		AM_RANGE( 0x6492, 0x6492 ) AM_WRITE_LEGACY(spoker_leds_w )
	243	AM_RANGE( 0x6491, 0x6491 ) AM_WRITE(spoker_video_and_leds_w )
	244	AM_RANGE( 0x6492, 0x6492 ) AM_WRITE(spoker_leds_w )
245	245
246	246	AM_RANGE( 0x64a0, 0x64a0 ) AM_READ_PORT( "BUTTONS2" )
247	247
r14845	r14846
249	249
250	250	AM_RANGE( 0x64c0, 0x64c0 ) AM_DEVREADWRITE("oki", okim6295_device, read, write)
251	251
252		AM_RANGE( 0x64d0, 0x64d1 ) AM_READWRITE_LEGACY(spoker_magic_r, spoker_magic_w )   // DSW1-5
	252	AM_RANGE( 0x64d0, 0x64d1 ) AM_READWRITE(spoker_magic_r, spoker_magic_w )   // DSW1-5
253	253
254		AM_RANGE( 0x7000, 0x7fff ) AM_RAM_WRITE_LEGACY(fg_color_w ) AM_BASE(m_fg_color_ram )
	254	AM_RANGE( 0x7000, 0x7fff ) AM_RAM_WRITE(fg_color_w ) AM_BASE(m_fg_color_ram )
255	255	ADDRESS_MAP_END
256	256
257	257	static ADDRESS_MAP_START( 3super8_portmap, AS_IO, 8, spoker_state )
r14845	r14846
260	260	AM_RANGE( 0x2000, 0x27ff ) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split1_w ) AM_BASE_GENERIC( paletteram )
261	261	AM_RANGE( 0x2800, 0x2fff ) AM_RAM_WRITE_LEGACY(paletteram_xBBBBBGGGGGRRRRR_split2_w ) AM_BASE_GENERIC( paletteram2 )
262	262
263		AM_RANGE( 0x3000, 0x33ff ) AM_RAM_WRITE_LEGACY(bg_tile_w ) AM_BASE(m_bg_tile_ram )
	263	AM_RANGE( 0x3000, 0x33ff ) AM_RAM_WRITE(bg_tile_w ) AM_BASE(m_bg_tile_ram )
264	264
265	265	AM_RANGE( 0x4000, 0x4000 ) AM_READ_PORT( "DSW1" )
266	266	AM_RANGE( 0x4001, 0x4001 ) AM_READ_PORT( "DSW2" )
r14845	r14846
270	270
271	271	//  AM_RANGE( 0x4000, 0x40ff ) AM_WRITENOP
272	272
273		AM_RANGE( 0x5000, 0x5fff ) AM_RAM_WRITE_LEGACY(fg_tile_w )  AM_BASE(m_fg_tile_ram )
	273	AM_RANGE( 0x5000, 0x5fff ) AM_RAM_WRITE(fg_tile_w )  AM_BASE(m_fg_tile_ram )
274	274
275	275	AM_RANGE( 0x6480, 0x6480 ) AM_READ_PORT( "IN0" )
276	276	AM_RANGE( 0x6490, 0x6490 ) AM_READ_PORT( "IN1" )
277	277	AM_RANGE( 0x6491, 0x6491 ) AM_DEVREADWRITE("oki", okim6295_device, read, write)
278	278	AM_RANGE( 0x64a0, 0x64a0 ) AM_READ_PORT( "IN2" )
279		AM_RANGE( 0x64b0, 0x64b0 ) AM_WRITE_LEGACY(spoker_leds_w )
	279	AM_RANGE( 0x64b0, 0x64b0 ) AM_WRITE(spoker_leds_w )
280	280	AM_RANGE( 0x64c0, 0x64c0 ) AM_READNOP //irq ack?
281	281
282		AM_RANGE( 0x64f0, 0x64f0 ) AM_WRITE_LEGACY(spoker_nmi_and_coins_w )
	282	AM_RANGE( 0x64f0, 0x64f0 ) AM_WRITE(spoker_nmi_and_coins_w )
283	283
284		AM_RANGE( 0x7000, 0x7fff ) AM_RAM_WRITE_LEGACY(fg_color_w ) AM_BASE(m_fg_color_ram )
	284	AM_RANGE( 0x7000, 0x7fff ) AM_RAM_WRITE(fg_color_w ) AM_BASE(m_fg_color_ram )
285	285	ADDRESS_MAP_END
286	286
287	287

src/mame/drivers/zr107.c

r14845	r14846
189	189	int m_ccu_vctl;
190	190	UINT32 *m_workram;
191	191	UINT32 *m_sharc_dataram;
	192	DECLARE_WRITE32_MEMBER(paletteram32_w);
	193	DECLARE_READ8_MEMBER(sysreg_r);
	194	DECLARE_WRITE8_MEMBER(sysreg_w);
	195	DECLARE_READ32_MEMBER(ccu_r);
	196	DECLARE_WRITE32_MEMBER(ccu_w);
	197	DECLARE_WRITE32_MEMBER(jetwave_palette_w);
	198	DECLARE_READ32_MEMBER(dsp_dataram_r);
	199	DECLARE_WRITE32_MEMBER(dsp_dataram_w);
192	200	};
193	201
194	202
r14845	r14846
223	231
224	232	/*****************************************************************************/
225	233
226		static WRITE32_HANDLER( paletteram32_w )
	234	WRITE32_MEMBER(zr107_state::paletteram32_w)
227	235	{
228		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
229		data = space->machine().generic.paletteram.u32[offset];
230		palette_set_color_rgb(space->machine(), (offset * 2) + 0, pal5bit(data >> 26), pal5bit(data >> 21), pal5bit(data >> 16));
231		palette_set_color_rgb(space->machine(), (offset * 2) + 1, pal5bit(data >> 10), pal5bit(data >> 5), pal5bit(data >> 0));
	236	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
	237	data = machine().generic.paletteram.u32[offset];
	238	palette_set_color_rgb(machine(), (offset * 2) + 0, pal5bit(data >> 26), pal5bit(data >> 21), pal5bit(data >> 16));
	239	palette_set_color_rgb(machine(), (offset * 2) + 1, pal5bit(data >> 10), pal5bit(data >> 5), pal5bit(data >> 0));
232	240	}
233	241
234	242	#define NUM_LAYERS   2
r14845	r14846
274	282
275	283	/******************************************************************/
276	284
277		static READ8_HANDLER( sysreg_r )
	285	READ8_MEMBER(zr107_state::sysreg_r)
278	286	{
279	287	UINT32 r = 0;
280	288	static const char *const portnames[] = { "IN0", "IN1", "IN2", "IN3", "IN4" };
r14845	r14846
286	294	case 2:   /* I/O port 2 */
287	295	case 3:   /* System Port 0 */
288	296	case 4:   /* System Port 1 */
289		r = input_port_read(space->machine(), portnames[offset]);
	297	r = input_port_read(machine(), portnames[offset]);
290	298	break;
291	299
292	300	case 5:   /* Parallel data port */
r14845	r14846
295	303	return r;
296	304	}
297	305
298		static WRITE8_HANDLER( sysreg_w )
	306	WRITE8_MEMBER(zr107_state::sysreg_w)
299	307	{
300		zr107_state *state = space->machine().driver_data<zr107_state>();
301	308	switch (offset)
302	309	{
303	310	case 0:   /* LED Register 0 */
304		state->m_led_reg0 = data;
	311	m_led_reg0 = data;
305	312	break;
306	313
307	314	case 1:   /* LED Register 1 */
308		state->m_led_reg1 = data;
	315	m_led_reg1 = data;
309	316	break;
310	317
311	318	case 2: /* Parallel data register */
r14845	r14846
323	330	0x02 = EEPCLK
324	331	0x01 = EEPDI
325	332	*/
326		input_port_write(space->machine(), "EEPROMOUT", data & 0x07, 0xff);
327		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_RESET, (data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
	333	input_port_write(machine(), "EEPROMOUT", data & 0x07, 0xff);
	334	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_RESET, (data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
328	335	mame_printf_debug("System register 0 = %02X\n", data);
329	336	break;
330	337
r14845	r14846
340	347	0x01 = ADDSCLK (ADC SCLK)
341	348	*/
342	349	if (data & 0x80)   /* CG Board 1 IRQ Ack */
343		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ1, CLEAR_LINE);
	350	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ1, CLEAR_LINE);
344	351	if (data & 0x40)   /* CG Board 0 IRQ Ack */
345		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
	352	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
346	353	set_cgboard_id((data >> 4) & 3);
347		input_port_write(space->machine(), "OUT4", data, 0xff);
	354	input_port_write(machine(), "OUT4", data, 0xff);
348	355	mame_printf_debug("System register 1 = %02X\n", data);
349	356	break;
350	357
r14845	r14846
353	360	0x01 = AFE
354	361	*/
355	362	if (data & 0x01)
356		watchdog_reset(space->machine());
	363	watchdog_reset(machine());
357	364	break;
358	365
359	366	}
360	367	}
361	368
362		static READ32_HANDLER( ccu_r )
	369	READ32_MEMBER(zr107_state::ccu_r)
363	370	{
364		zr107_state *state = space->machine().driver_data<zr107_state>();
365	371	UINT32 r = 0;
366	372	switch (offset)
367	373	{
r14845	r14846
370	376	// Midnight Run polls the vertical counter in vblank
371	377	if (ACCESSING_BITS_24_31)
372	378	{
373		state->m_ccu_vcth ^= 0xff;
374		r |= state->m_ccu_vcth << 24;
	379	m_ccu_vcth ^= 0xff;
	380	r |= m_ccu_vcth << 24;
375	381	}
376	382	if (ACCESSING_BITS_8_15)
377	383	{
378		state->m_ccu_vctl++;
379		state->m_ccu_vctl &= 0x1ff;
380		r |= (state->m_ccu_vctl >> 2) << 8;
	384	m_ccu_vctl++;
	385	m_ccu_vctl &= 0x1ff;
	386	r |= (m_ccu_vctl >> 2) << 8;
381	387	}
382	388	}
383	389	}
r14845	r14846
385	391	return r;
386	392	}
387	393
388		static WRITE32_HANDLER( ccu_w )
	394	WRITE32_MEMBER(zr107_state::ccu_w)
389	395	{
390
391	396	}
392	397
393	398	/******************************************************************/
r14845	r14846
406	411	AM_RANGE(0x00000000, 0x000fffff) AM_RAM   AM_BASE(m_workram)   /* Work RAM */
407	412	AM_RANGE(0x74000000, 0x74003fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_long_r, k056832_ram_long_w)
408	413	AM_RANGE(0x74020000, 0x7402003f) AM_DEVREADWRITE_LEGACY("k056832", k056832_long_r, k056832_long_w)
409		AM_RANGE(0x74060000, 0x7406003f) AM_READWRITE_LEGACY(ccu_r, ccu_w)
410		AM_RANGE(0x74080000, 0x74081fff) AM_RAM_WRITE_LEGACY(paletteram32_w) AM_BASE_GENERIC(paletteram)
	414	AM_RANGE(0x74060000, 0x7406003f) AM_READWRITE(ccu_r, ccu_w)
	415	AM_RANGE(0x74080000, 0x74081fff) AM_RAM_WRITE(paletteram32_w) AM_BASE_GENERIC(paletteram)
411	416	AM_RANGE(0x740a0000, 0x740a3fff) AM_DEVREAD_LEGACY("k056832", k056832_rom_long_r)
412	417	AM_RANGE(0x78000000, 0x7800ffff) AM_READWRITE_LEGACY(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc)      /* 21N 21K 23N 23K */
413	418	AM_RANGE(0x78010000, 0x7801ffff) AM_WRITE_LEGACY(cgboard_dsp_shared_w_ppc)
414	419	AM_RANGE(0x78040000, 0x7804000f) AM_READWRITE_LEGACY(K001006_0_r, K001006_0_w)
415	420	AM_RANGE(0x780c0000, 0x780c0007) AM_READWRITE_LEGACY(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc)
416		AM_RANGE(0x7e000000, 0x7e003fff) AM_READWRITE8_LEGACY(sysreg_r, sysreg_w, 0xffffffff)
	421	AM_RANGE(0x7e000000, 0x7e003fff) AM_READWRITE8(sysreg_r, sysreg_w, 0xffffffff)
417	422	AM_RANGE(0x7e008000, 0x7e009fff) AM_DEVREADWRITE8_LEGACY("k056230", k056230_r, k056230_w, 0xffffffff)            /* LANC registers */
418	423	AM_RANGE(0x7e00a000, 0x7e00bfff) AM_DEVREADWRITE_LEGACY("k056230", lanc_ram_r, lanc_ram_w)      /* LANC Buffer RAM (27E) */
419	424	AM_RANGE(0x7e00c000, 0x7e00c007) AM_DEVWRITE_LEGACY("k056800", k056800_host_w)
r14845	r14846
423	428	ADDRESS_MAP_END
424	429
425	430
426		static WRITE32_HANDLER( jetwave_palette_w )
	431	WRITE32_MEMBER(zr107_state::jetwave_palette_w)
427	432	{
428		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
429		data = space->machine().generic.paletteram.u32[offset];
430		palette_set_color_rgb(space->machine(), offset, pal5bit(data >> 10), pal5bit(data >> 5), pal5bit(data >> 0));
	433	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
	434	data = machine().generic.paletteram.u32[offset];
	435	palette_set_color_rgb(machine(), offset, pal5bit(data >> 10), pal5bit(data >> 5), pal5bit(data >> 0));
431	436	}
432	437
433	438	static ADDRESS_MAP_START( jetwave_map, AS_PROGRAM, 32, zr107_state )
434	439	AM_RANGE(0x00000000, 0x000fffff) AM_MIRROR(0x80000000) AM_RAM      /* Work RAM */
435	440	AM_RANGE(0x74000000, 0x740000ff) AM_MIRROR(0x80000000) AM_DEVREADWRITE_LEGACY("k001604", k001604_reg_r, k001604_reg_w)
436		AM_RANGE(0x74010000, 0x7401ffff) AM_MIRROR(0x80000000) AM_RAM_WRITE_LEGACY(jetwave_palette_w) AM_BASE_GENERIC(paletteram)
	441	AM_RANGE(0x74010000, 0x7401ffff) AM_MIRROR(0x80000000) AM_RAM_WRITE(jetwave_palette_w) AM_BASE_GENERIC(paletteram)
437	442	AM_RANGE(0x74020000, 0x7403ffff) AM_MIRROR(0x80000000) AM_DEVREADWRITE_LEGACY("k001604", k001604_tile_r, k001604_tile_w)
438	443	AM_RANGE(0x74040000, 0x7407ffff) AM_MIRROR(0x80000000) AM_DEVREADWRITE_LEGACY("k001604", k001604_char_r, k001604_char_w)
439	444	AM_RANGE(0x78000000, 0x7800ffff) AM_MIRROR(0x80000000) AM_READWRITE_LEGACY(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc)      /* 21N 21K 23N 23K */
r14845	r14846
441	446	AM_RANGE(0x78040000, 0x7804000f) AM_MIRROR(0x80000000) AM_READWRITE_LEGACY(K001006_0_r, K001006_0_w)
442	447	AM_RANGE(0x78080000, 0x7808000f) AM_MIRROR(0x80000000) AM_READWRITE_LEGACY(K001006_1_r, K001006_1_w)
443	448	AM_RANGE(0x780c0000, 0x780c0007) AM_MIRROR(0x80000000) AM_READWRITE_LEGACY(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc)
444		AM_RANGE(0x7e000000, 0x7e003fff) AM_MIRROR(0x80000000) AM_READWRITE8_LEGACY(sysreg_r, sysreg_w, 0xffffffff)
	449	AM_RANGE(0x7e000000, 0x7e003fff) AM_MIRROR(0x80000000) AM_READWRITE8(sysreg_r, sysreg_w, 0xffffffff)
445	450	AM_RANGE(0x7e008000, 0x7e009fff) AM_MIRROR(0x80000000) AM_DEVREADWRITE8_LEGACY("k056230", k056230_r, k056230_w, 0xffffffff)            /* LANC registers */
446	451	AM_RANGE(0x7e00a000, 0x7e00bfff) AM_MIRROR(0x80000000) AM_DEVREADWRITE_LEGACY("k056230", lanc_ram_r, lanc_ram_w)   /* LANC Buffer RAM (27E) */
447	452	AM_RANGE(0x7e00c000, 0x7e00c007) AM_MIRROR(0x80000000) AM_DEVWRITE_LEGACY("k056800", k056800_host_w)
r14845	r14846
473	478	/*****************************************************************************/
474	479
475	480
476		static READ32_HANDLER( dsp_dataram_r )
	481	READ32_MEMBER(zr107_state::dsp_dataram_r)
477	482	{
478		zr107_state *state = space->machine().driver_data<zr107_state>();
479		return state->m_sharc_dataram[offset] & 0xffff;
	483	return m_sharc_dataram[offset] & 0xffff;
480	484	}
481	485
482		static WRITE32_HANDLER( dsp_dataram_w )
	486	WRITE32_MEMBER(zr107_state::dsp_dataram_w)
483	487	{
484		zr107_state *state = space->machine().driver_data<zr107_state>();
485		state->m_sharc_dataram[offset] = data;
	488	m_sharc_dataram[offset] = data;
486	489	}
487	490
488	491	static ADDRESS_MAP_START( sharc_map, AS_DATA, 32, zr107_state )
489	492	AM_RANGE(0x400000, 0x41ffff) AM_READWRITE_LEGACY(cgboard_0_shared_sharc_r, cgboard_0_shared_sharc_w)
490		AM_RANGE(0x500000, 0x5fffff) AM_READWRITE_LEGACY(dsp_dataram_r, dsp_dataram_w)
	493	AM_RANGE(0x500000, 0x5fffff) AM_READWRITE(dsp_dataram_r, dsp_dataram_w)
491	494	AM_RANGE(0x600000, 0x6fffff) AM_READWRITE_LEGACY(K001005_r, K001005_w)
492	495	AM_RANGE(0x700000, 0x7000ff) AM_READWRITE_LEGACY(cgboard_0_comm_sharc_r, cgboard_0_comm_sharc_w)
493	496	ADDRESS_MAP_END

src/mame/drivers/dominob.c

r14845	r14846
80	80	/* input-related */
81	81	//UINT8 m_paddle_select;
82	82	//UINT8 m_paddle_value;
	83	DECLARE_WRITE8_MEMBER(dominob_d008_w);
	84	DECLARE_READ8_MEMBER(dominob_unk_port02_r);
83	85	};
84	86
85	87	static VIDEO_START( dominob )
r14845	r14846
159	161	}
160	162
161	163
162		static WRITE8_HANDLER( dominob_d008_w )
	164	WRITE8_MEMBER(dominob_state::dominob_d008_w)
163	165	{
164	166	/* is there a purpose on this ? always set to 0x00 (read from 0xc47b in RAM) */
165	167	}
r14845	r14846
170	172
171	173	AM_RANGE(0xd000, 0xd001) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
172	174	AM_RANGE(0xd001, 0xd001) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
173		AM_RANGE(0xd008, 0xd008) AM_WRITE_LEGACY(dominob_d008_w)
	175	AM_RANGE(0xd008, 0xd008) AM_WRITE(dominob_d008_w)
174	176	AM_RANGE(0xd00c, 0xd00c) AM_READ_PORT("IN0")
175	177	AM_RANGE(0xd010, 0xd010) AM_READ_PORT("IN1") AM_WRITENOP
176	178	AM_RANGE(0xd018, 0xd018) AM_READ_PORT("IN2") AM_WRITENOP
r14845	r14846
185	187	ADDRESS_MAP_END
186	188
187	189	/* I don't know if this has a purpose - also read in 'arkatayt' but not handled */
188		static READ8_HANDLER( dominob_unk_port02_r )
	190	READ8_MEMBER(dominob_state::dominob_unk_port02_r)
189	191	{
190	192	return 0xff;
191	193	}
192	194
193	195	static ADDRESS_MAP_START( portmap, AS_IO, 8, dominob_state )
194	196	ADDRESS_MAP_GLOBAL_MASK(0xff)
195		AM_RANGE(0x02, 0x02) AM_READ_LEGACY(dominob_unk_port02_r)
	197	AM_RANGE(0x02, 0x02) AM_READ(dominob_unk_port02_r)
196	198	ADDRESS_MAP_END
197	199
198	200

src/mame/drivers/sbrkout.c

r14845	r14846
50	50	UINT8 m_sync2_value;
51	51	UINT8 m_pot_mask[2];
52	52	UINT8 m_pot_trigger[2];
	53	DECLARE_WRITE8_MEMBER(irq_ack_w);
	54	DECLARE_READ8_MEMBER(switches_r);
	55	DECLARE_WRITE8_MEMBER(pot_mask1_w);
	56	DECLARE_WRITE8_MEMBER(pot_mask2_w);
	57	DECLARE_WRITE8_MEMBER(start_1_led_w);
	58	DECLARE_WRITE8_MEMBER(start_2_led_w);
	59	DECLARE_WRITE8_MEMBER(serve_led_w);
	60	DECLARE_WRITE8_MEMBER(coincount_w);
	61	DECLARE_READ8_MEMBER(sync_r);
	62	DECLARE_READ8_MEMBER(sync2_r);
	63	DECLARE_WRITE8_MEMBER(sbrkout_videoram_w);
53	64	};
54	65
55	66
r14845	r14846
142	153	}
143	154
144	155
145		static WRITE8_HANDLER( irq_ack_w )
	156	WRITE8_MEMBER(sbrkout_state::irq_ack_w)
146	157	{
147		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
	158	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
148	159	}
149	160
150	161
r14845	r14846
155	166	*
156	167	*************************************/
157	168
158		static READ8_HANDLER( switches_r )
	169	READ8_MEMBER(sbrkout_state::switches_r)
159	170	{
160		sbrkout_state *state = space->machine().driver_data<sbrkout_state>();
161	171	UINT8 result = 0xff;
162	172
163	173	/* DIP switches are selected by ADR0+ADR1 if ADR3 == 0 */
164	174	if ((offset & 0x0b) == 0x00)
165		result &= (input_port_read(space->machine(), "DIPS") << 6) | 0x3f;
	175	result &= (input_port_read(machine(), "DIPS") << 6) | 0x3f;
166	176	if ((offset & 0x0b) == 0x01)
167		result &= (input_port_read(space->machine(), "DIPS") << 4) | 0x3f;
	177	result &= (input_port_read(machine(), "DIPS") << 4) | 0x3f;
168	178	if ((offset & 0x0b) == 0x02)
169		result &= (input_port_read(space->machine(), "DIPS") << 0) | 0x3f;
	179	result &= (input_port_read(machine(), "DIPS") << 0) | 0x3f;
170	180	if ((offset & 0x0b) == 0x03)
171		result &= (input_port_read(space->machine(), "DIPS") << 2) | 0x3f;
	181	result &= (input_port_read(machine(), "DIPS") << 2) | 0x3f;
172	182
173	183	/* other switches are selected by ADR0+ADR1+ADR2 if ADR4 == 0 */
174	184	if ((offset & 0x17) == 0x00)
175		result &= (input_port_read(space->machine(), "SELECT") << 7) | 0x7f;
	185	result &= (input_port_read(machine(), "SELECT") << 7) | 0x7f;
176	186	if ((offset & 0x17) == 0x04)
177		result &= ((state->m_pot_trigger[0] & ~state->m_pot_mask[0]) << 7) | 0x7f;
	187	result &= ((m_pot_trigger[0] & ~m_pot_mask[0]) << 7) | 0x7f;
178	188	if ((offset & 0x17) == 0x05)
179		result &= ((state->m_pot_trigger[1] & ~state->m_pot_mask[1]) << 7) | 0x7f;
	189	result &= ((m_pot_trigger[1] & ~m_pot_mask[1]) << 7) | 0x7f;
180	190	if ((offset & 0x17) == 0x06)
181		result &= input_port_read(space->machine(), "SERVE");
	191	result &= input_port_read(machine(), "SERVE");
182	192	if ((offset & 0x17) == 0x07)
183		result &= (input_port_read(space->machine(), "SELECT") << 6) | 0x7f;
	193	result &= (input_port_read(machine(), "SELECT") << 6) | 0x7f;
184	194
185	195	return result;
186	196	}
r14845	r14846
204	214	}
205	215
206	216
207		static WRITE8_HANDLER( pot_mask1_w )
	217	WRITE8_MEMBER(sbrkout_state::pot_mask1_w)
208	218	{
209		sbrkout_state *state = space->machine().driver_data<sbrkout_state>();
210		state->m_pot_mask[0] = ~offset & 1;
211		state->m_pot_trigger[0] = 0;
212		update_nmi_state(space->machine());
	219	m_pot_mask[0] = ~offset & 1;
	220	m_pot_trigger[0] = 0;
	221	update_nmi_state(machine());
213	222	}
214	223
215	224
216		static WRITE8_HANDLER( pot_mask2_w )
	225	WRITE8_MEMBER(sbrkout_state::pot_mask2_w)
217	226	{
218		sbrkout_state *state = space->machine().driver_data<sbrkout_state>();
219		state->m_pot_mask[1] = ~offset & 1;
220		state->m_pot_trigger[1] = 0;
221		update_nmi_state(space->machine());
	227	m_pot_mask[1] = ~offset & 1;
	228	m_pot_trigger[1] = 0;
	229	update_nmi_state(machine());
222	230	}
223	231
224	232
r14845	r14846
235	243	reversed for the Serve LED, which has a NOT on the signal.
236	244	*/
237	245
238		static WRITE8_HANDLER( start_1_led_w )
	246	WRITE8_MEMBER(sbrkout_state::start_1_led_w)
239	247	{
240	248	output_set_led_value(0, offset & 1);
241	249	}
242	250
243	251
244		static WRITE8_HANDLER( start_2_led_w )
	252	WRITE8_MEMBER(sbrkout_state::start_2_led_w)
245	253	{
246	254	output_set_led_value(1, offset & 1);
247	255	}
248	256
249	257
250		static WRITE8_HANDLER( serve_led_w )
	258	WRITE8_MEMBER(sbrkout_state::serve_led_w)
251	259	{
252	260	output_set_led_value(0, ~offset & 1);
253	261	}
254	262
255	263
256		static WRITE8_HANDLER( coincount_w )
	264	WRITE8_MEMBER(sbrkout_state::coincount_w)
257	265	{
258		coin_counter_w(space->machine(), 0, offset & 1);
	266	coin_counter_w(machine(), 0, offset & 1);
259	267	}
260	268
261	269
r14845	r14846
266	274	*
267	275	*************************************/
268	276
269		static READ8_HANDLER( sync_r )
	277	READ8_MEMBER(sbrkout_state::sync_r)
270	278	{
271		sbrkout_state *state = space->machine().driver_data<sbrkout_state>();
272		int hpos = space->machine().primary_screen->hpos();
273		state->m_sync2_value = (hpos >= 128 && hpos <= space->machine().primary_screen->visible_area().max_x);
274		return space->machine().primary_screen->vpos();
	279	int hpos = machine().primary_screen->hpos();
	280	m_sync2_value = (hpos >= 128 && hpos <= machine().primary_screen->visible_area().max_x);
	281	return machine().primary_screen->vpos();
275	282	}
276	283
277	284
278		static READ8_HANDLER( sync2_r )
	285	READ8_MEMBER(sbrkout_state::sync2_r)
279	286	{
280		sbrkout_state *state = space->machine().driver_data<sbrkout_state>();
281		return (state->m_sync2_value << 7) | 0x7f;
	287	return (m_sync2_value << 7) | 0x7f;
282	288	}
283	289
284	290
r14845	r14846
305	311	}
306	312
307	313
308		static WRITE8_HANDLER( sbrkout_videoram_w )
	314	WRITE8_MEMBER(sbrkout_state::sbrkout_videoram_w)
309	315	{
310		sbrkout_state *state = space->machine().driver_data<sbrkout_state>();
311		UINT8 *videoram = state->m_videoram;
	316	UINT8 *videoram = m_videoram;
312	317	videoram[offset] = data;
313		state->m_bg_tilemap->mark_tile_dirty(offset);
	318	m_bg_tilemap->mark_tile_dirty(offset);
314	319	}
315	320
316	321
r14845	r14846
352	357	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, sbrkout_state )
353	358	ADDRESS_MAP_GLOBAL_MASK(0x3fff)
354	359	AM_RANGE(0x0000, 0x007f) AM_MIRROR(0x380) AM_RAMBANK("bank1")
355		AM_RANGE(0x0400, 0x07ff) AM_RAM_WRITE_LEGACY(sbrkout_videoram_w) AM_BASE(m_videoram)
356		AM_RANGE(0x0800, 0x083f) AM_READ_LEGACY(switches_r)
	360	AM_RANGE(0x0400, 0x07ff) AM_RAM_WRITE(sbrkout_videoram_w) AM_BASE(m_videoram)
	361	AM_RANGE(0x0800, 0x083f) AM_READ(switches_r)
357	362	AM_RANGE(0x0840, 0x0840) AM_MIRROR(0x003f) AM_READ_PORT("COIN")
358	363	AM_RANGE(0x0880, 0x0880) AM_MIRROR(0x003f) AM_READ_PORT("START")
359	364	AM_RANGE(0x08c0, 0x08c0) AM_MIRROR(0x003f) AM_READ_PORT("SERVICE")
360		AM_RANGE(0x0c00, 0x0c00) AM_MIRROR(0x03ff) AM_READ_LEGACY(sync_r)
361		AM_RANGE(0x0c10, 0x0c11) AM_MIRROR(0x000e) AM_WRITE_LEGACY(serve_led_w)
362		AM_RANGE(0x0c30, 0x0c31) AM_MIRROR(0x000e) AM_WRITE_LEGACY(start_1_led_w)
363		AM_RANGE(0x0c40, 0x0c41) AM_MIRROR(0x000e) AM_WRITE_LEGACY(start_2_led_w)
364		AM_RANGE(0x0c50, 0x0c51) AM_MIRROR(0x000e) AM_WRITE_LEGACY(pot_mask1_w)
365		AM_RANGE(0x0c60, 0x0c61) AM_MIRROR(0x000e) AM_WRITE_LEGACY(pot_mask2_w)
366		AM_RANGE(0x0c70, 0x0c71) AM_MIRROR(0x000e) AM_WRITE_LEGACY(coincount_w)
	365	AM_RANGE(0x0c00, 0x0c00) AM_MIRROR(0x03ff) AM_READ(sync_r)
	366	AM_RANGE(0x0c10, 0x0c11) AM_MIRROR(0x000e) AM_WRITE(serve_led_w)
	367	AM_RANGE(0x0c30, 0x0c31) AM_MIRROR(0x000e) AM_WRITE(start_1_led_w)
	368	AM_RANGE(0x0c40, 0x0c41) AM_MIRROR(0x000e) AM_WRITE(start_2_led_w)
	369	AM_RANGE(0x0c50, 0x0c51) AM_MIRROR(0x000e) AM_WRITE(pot_mask1_w)
	370	AM_RANGE(0x0c60, 0x0c61) AM_MIRROR(0x000e) AM_WRITE(pot_mask2_w)
	371	AM_RANGE(0x0c70, 0x0c71) AM_MIRROR(0x000e) AM_WRITE(coincount_w)
367	372	AM_RANGE(0x0c80, 0x0c80) AM_MIRROR(0x007f) AM_WRITE_LEGACY(watchdog_reset_w)
368		AM_RANGE(0x0e00, 0x0e00) AM_MIRROR(0x007f) AM_WRITE_LEGACY(irq_ack_w)
369		AM_RANGE(0x1000, 0x1000) AM_MIRROR(0x03ff) AM_READ_LEGACY(sync2_r)
	373	AM_RANGE(0x0e00, 0x0e00) AM_MIRROR(0x007f) AM_WRITE(irq_ack_w)
	374	AM_RANGE(0x1000, 0x1000) AM_MIRROR(0x03ff) AM_READ(sync2_r)
370	375	AM_RANGE(0x2800, 0x3fff) AM_ROM
371	376	ADDRESS_MAP_END
372	377

src/mame/drivers/bwidow.c

r14845	r14846
231	231	: driver_device(mconfig, type, tag) { }
232	232
233	233	int m_lastdata;
	234	DECLARE_READ8_MEMBER(spacduel_IN3_r);
	235	DECLARE_WRITE8_MEMBER(bwidow_misc_w);
	236	DECLARE_WRITE8_MEMBER(irq_ack_w);
234	237	};
235	238
236	239
r14845	r14846
263	266
264	267	*/
265	268
266		static READ8_HANDLER( spacduel_IN3_r )
	269	READ8_MEMBER(bwidow_state::spacduel_IN3_r)
267	270	{
268	271	int res;
269	272	int res1;
270	273	int res2;
271	274	int res3;
272	275
273		res1 = input_port_read(space->machine(), "IN3");
274		res2 = input_port_read(space->machine(), "IN4");
275		res3 = input_port_read_safe(space->machine(), "DSW2", 0);
	276	res1 = input_port_read(machine(), "IN3");
	277	res2 = input_port_read(machine(), "IN4");
	278	res3 = input_port_read_safe(machine(), "DSW2", 0);
276	279	res = 0x00;
277	280
278	281	switch (offset & 0x07)
r14845	r14846
326	329	*
327	330	*************************************/
328	331
329		static WRITE8_HANDLER( bwidow_misc_w )
	332	WRITE8_MEMBER(bwidow_state::bwidow_misc_w)
330	333	{
331		bwidow_state *state = space->machine().driver_data<bwidow_state>();
332	334	/*
333	335	0x10 = p1 led
334	336	0x20 = p2 led
r14845	r14846
336	338	0x02 = coin counter 2
337	339	*/
338	340
339		if (data == state->m_lastdata) return;
340		set_led_status(space->machine(), 0,~data & 0x10);
341		set_led_status(space->machine(), 1,~data & 0x20);
342		coin_counter_w(space->machine(), 0, data & 0x01);
343		coin_counter_w(space->machine(), 1, data & 0x02);
344		state->m_lastdata = data;
	341	if (data == m_lastdata) return;
	342	set_led_status(machine(), 0,~data & 0x10);
	343	set_led_status(machine(), 1,~data & 0x20);
	344	coin_counter_w(machine(), 0, data & 0x01);
	345	coin_counter_w(machine(), 1, data & 0x02);
	346	m_lastdata = data;
345	347	}
346	348
347	349	/*************************************
r14845	r14846
350	352	*
351	353	*************************************/
352	354
353		static WRITE8_HANDLER( irq_ack_w )
	355	WRITE8_MEMBER(bwidow_state::irq_ack_w)
354	356	{
355		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
	357	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
356	358	}
357	359
358	360
r14845	r14846
372	374	AM_RANGE(0x7800, 0x7800) AM_READ_PORT("IN0")
373	375	AM_RANGE(0x8000, 0x8000) AM_READ_PORT("IN3")
374	376	AM_RANGE(0x8800, 0x8800) AM_READ_PORT("IN4")
375		AM_RANGE(0x8800, 0x8800) AM_WRITE_LEGACY(bwidow_misc_w) /* coin counters, leds */
	377	AM_RANGE(0x8800, 0x8800) AM_WRITE(bwidow_misc_w) /* coin counters, leds */
376	378	AM_RANGE(0x8840, 0x8840) AM_WRITE_LEGACY(avgdvg_go_w)
377	379	AM_RANGE(0x8880, 0x8880) AM_WRITE_LEGACY(avgdvg_reset_w)
378		AM_RANGE(0x88c0, 0x88c0) AM_WRITE_LEGACY(irq_ack_w) /* interrupt acknowledge */
	380	AM_RANGE(0x88c0, 0x88c0) AM_WRITE(irq_ack_w) /* interrupt acknowledge */
379	381	AM_RANGE(0x8900, 0x8900) AM_DEVWRITE("earom", atari_vg_earom_device, ctrl_w)
380	382	AM_RANGE(0x8940, 0x897f) AM_DEVWRITE("earom", atari_vg_earom_device, write)
381	383	AM_RANGE(0x8980, 0x89ed) AM_WRITENOP /* watchdog clear */
r14845	r14846
386	388	static ADDRESS_MAP_START( spacduel_map, AS_PROGRAM, 8, bwidow_state )
387	389	AM_RANGE(0x0000, 0x03ff) AM_RAM
388	390	AM_RANGE(0x0800, 0x0800) AM_READ_PORT("IN0")
389		AM_RANGE(0x0900, 0x0907) AM_READ_LEGACY(spacduel_IN3_r)   /* IN1 */
	391	AM_RANGE(0x0900, 0x0907) AM_READ(spacduel_IN3_r)   /* IN1 */
390	392	AM_RANGE(0x0905, 0x0906) AM_WRITENOP /* ignore? */
391	393	AM_RANGE(0x0a00, 0x0a00) AM_DEVREAD("earom", atari_vg_earom_device, read)
392	394	//  AM_RANGE(0x0c00, 0x0c00) AM_WRITE_LEGACY(coin_counter_w) /* coin out */
393	395	AM_RANGE(0x0c80, 0x0c80) AM_WRITE_LEGACY(avgdvg_go_w)
394	396	AM_RANGE(0x0d00, 0x0d00) AM_WRITENOP /* watchdog clear */
395	397	AM_RANGE(0x0d80, 0x0d80) AM_WRITE_LEGACY(avgdvg_reset_w)
396		AM_RANGE(0x0e00, 0x0e00) AM_WRITE_LEGACY(irq_ack_w) /* interrupt acknowledge */
	398	AM_RANGE(0x0e00, 0x0e00) AM_WRITE(irq_ack_w) /* interrupt acknowledge */
397	399	AM_RANGE(0x0e80, 0x0e80) AM_DEVWRITE("earom", atari_vg_earom_device, ctrl_w)
398	400	AM_RANGE(0x0f00, 0x0f3f) AM_DEVWRITE("earom", atari_vg_earom_device, write)
399	401	AM_RANGE(0x1000, 0x100f) AM_DEVREADWRITE_LEGACY("pokey1", pokey_r, pokey_w)

src/mame/drivers/re900.c

r14845	r14846
95	95	UINT8 m_ledant;
96	96	UINT8 m_player;
97	97	UINT8 m_stat_a;
	98	DECLARE_READ8_MEMBER(rom_r);
	99	DECLARE_WRITE8_MEMBER(cpu_port_0_w);
	100	DECLARE_WRITE8_MEMBER(re900_watchdog_reset_w);
98	101	};
99	102
100	103
r14845	r14846
168	171	return retval;
169	172	}
170	173
171		static READ8_HANDLER (rom_r)
	174	READ8_MEMBER(re900_state::rom_r)
172	175	{
173		re900_state *state = space->machine().driver_data<re900_state>();
174		return state->m_rom[offset];
	176	return m_rom[offset];
175	177	}
176	178
177	179
r14845	r14846
205	207	}
206	208	}
207	209
208		static WRITE8_HANDLER (cpu_port_0_w)
	210	WRITE8_MEMBER(re900_state::cpu_port_0_w)
209	211	{
210	212	//  output_set_lamp_value(7,1 ^ ( (data >> 4) & 1)); /* Cont. Sal */
211	213	//  output_set_lamp_value(8,1 ^ ( (data >> 5) & 1)); /* Cont. Ent */
212	214	}
213	215
214		static WRITE8_HANDLER(re900_watchdog_reset_w)
	216	WRITE8_MEMBER(re900_state::re900_watchdog_reset_w)
215	217	{
216	218	//watchdog_reset_w(space,0,0); /* To do! */
217	219	}
r14845	r14846
226	228	ADDRESS_MAP_END
227	229
228	230	static ADDRESS_MAP_START( mem_io, AS_IO, 8, re900_state )
229		AM_RANGE(0x0000, 0xbfff) AM_READ_LEGACY(rom_r)
	231	AM_RANGE(0x0000, 0xbfff) AM_READ(rom_r)
230	232	AM_RANGE(0xc000, 0xdfff) AM_RAM AM_SHARE("nvram")
231	233	AM_RANGE(0xe000, 0xe000) AM_DEVWRITE("tms9128", tms9928a_device, vram_write)
232	234	AM_RANGE(0xe001, 0xe001) AM_DEVWRITE("tms9128", tms9928a_device, register_write)
233	235	AM_RANGE(0xe800, 0xe801) AM_DEVWRITE_LEGACY("ay_re900", ay8910_address_data_w)
234	236	AM_RANGE(0xe802, 0xe802) AM_DEVREAD_LEGACY("ay_re900", ay8910_r)
235		AM_RANGE(0xe000, 0xefff) AM_WRITE_LEGACY(re900_watchdog_reset_w)
236		AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_WRITE_LEGACY(cpu_port_0_w)
	237	AM_RANGE(0xe000, 0xefff) AM_WRITE(re900_watchdog_reset_w)
	238	AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_WRITE(cpu_port_0_w)
237	239	AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_NOP
238	240	AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_NOP
239	241	ADDRESS_MAP_END

src/mame/drivers/jackpool.c

r14845	r14846
30	30	UINT16 *m_vram;
31	31	UINT8 m_map_vreg;
32	32	UINT16 *m_io;
	33	DECLARE_READ16_MEMBER(jackpool_ff_r);
	34	DECLARE_READ16_MEMBER(jackpool_io_r);
	35	DECLARE_WRITE16_MEMBER(jackpool_io_w);
33	36	};
34	37
35	38
r14845	r14846
83	86	}
84	87
85	88	/*Communication ram*/
86		static READ16_HANDLER( jackpool_ff_r )
	89	READ16_MEMBER(jackpool_state::jackpool_ff_r)
87	90	{
88	91	return 0xffff;
89	92	}
90	93
91		static READ16_HANDLER( jackpool_io_r )
	94	READ16_MEMBER(jackpool_state::jackpool_io_r)
92	95	{
93		jackpool_state *state = space->machine().driver_data<jackpool_state>();
94	96	switch(offset*2)
95	97	{
96		case 0x00: return input_port_read(space->machine(),"COIN1");
97		case 0x04: return input_port_read(space->machine(),"UNK1");
98		case 0x06: return input_port_read(space->machine(),"UNK2");
99		case 0x08: return input_port_read(space->machine(),"SERVICE1");
100		case 0x0a: return input_port_read(space->machine(),"SERVICE2");//probably not a button, remote?
101		case 0x0c: return input_port_read(space->machine(),"PAYOUT");
102		case 0x0e: return input_port_read(space->machine(),"START2");
103		case 0x10: return input_port_read(space->machine(),"HOLD3");
104		case 0x12: return input_port_read(space->machine(),"HOLD4");
105		case 0x14: return input_port_read(space->machine(),"HOLD2");
106		case 0x16: return input_port_read(space->machine(),"HOLD1");
107		case 0x18: return input_port_read(space->machine(),"HOLD5");
108		case 0x1a: return input_port_read(space->machine(),"START1");
109		case 0x1c: return input_port_read(space->machine(),"BET");
	98	case 0x00: return input_port_read(machine(),"COIN1");
	99	case 0x04: return input_port_read(machine(),"UNK1");
	100	case 0x06: return input_port_read(machine(),"UNK2");
	101	case 0x08: return input_port_read(machine(),"SERVICE1");
	102	case 0x0a: return input_port_read(machine(),"SERVICE2");//probably not a button, remote?
	103	case 0x0c: return input_port_read(machine(),"PAYOUT");
	104	case 0x0e: return input_port_read(machine(),"START2");
	105	case 0x10: return input_port_read(machine(),"HOLD3");
	106	case 0x12: return input_port_read(machine(),"HOLD4");
	107	case 0x14: return input_port_read(machine(),"HOLD2");
	108	case 0x16: return input_port_read(machine(),"HOLD1");
	109	case 0x18: return input_port_read(machine(),"HOLD5");
	110	case 0x1a: return input_port_read(machine(),"START1");
	111	case 0x1c: return input_port_read(machine(),"BET");
110	112	case 0x1e: return 0xff; //ticket motor
111	113	case 0x20: return 0xff; //hopper motor
112		case 0x2c: return space->machine().device<eeprom_device>("eeprom")->read_bit();
113		case 0x2e: return space->machine().device<eeprom_device>("eeprom")->read_bit();
	114	case 0x2c: return machine().device<eeprom_device>("eeprom")->read_bit();
	115	case 0x2e: return machine().device<eeprom_device>("eeprom")->read_bit();
114	116	//      default: printf("R %02x\n",offset*2); break;
115	117	}
116	118
117	119	//  printf("R %02x\n",offset*2);
118		return state->m_io[offset];
	120	return m_io[offset];
119	121	}
120	122
121		static WRITE16_HANDLER( jackpool_io_w )
	123	WRITE16_MEMBER(jackpool_state::jackpool_io_w)
122	124	{
123		jackpool_state *state = space->machine().driver_data<jackpool_state>();
124		COMBINE_DATA(&state->m_io[offset]);
	125	COMBINE_DATA(&m_io[offset]);
125	126
126	127	switch(offset*2)
127	128	{
r14845	r14846
137	138	case 0x46: /* ---- ---x coin counter */break;
138	139	case 0x4a: /* ---- ---x Ticket motor */break;
139	140	case 0x4c: /* ---- ---x Hopper motor */break;
140		case 0x4e: state->m_map_vreg = data & 1;        break;
141		case 0x50: space->machine().device<eeprom_device>("eeprom")->set_cs_line((data & 1) ? CLEAR_LINE : ASSERT_LINE ); break;
142		case 0x52: space->machine().device<eeprom_device>("eeprom")->set_clock_line((data & 1) ? ASSERT_LINE : CLEAR_LINE ); break;
143		case 0x54: space->machine().device<eeprom_device>("eeprom")->write_bit(data & 1); break;
144		//      case 0x5a: space->machine().device<eeprom_device>("eeprom")->set_cs_line((data & 1) ? CLEAR_LINE : ASSERT_LINE ); break;
145		//      case 0x5c: space->machine().device<eeprom_device>("eeprom")->set_cs_line((data & 1) ? CLEAR_LINE : ASSERT_LINE ); break;
	141	case 0x4e: m_map_vreg = data & 1;        break;
	142	case 0x50: machine().device<eeprom_device>("eeprom")->set_cs_line((data & 1) ? CLEAR_LINE : ASSERT_LINE ); break;
	143	case 0x52: machine().device<eeprom_device>("eeprom")->set_clock_line((data & 1) ? ASSERT_LINE : CLEAR_LINE ); break;
	144	case 0x54: machine().device<eeprom_device>("eeprom")->write_bit(data & 1); break;
	145	//      case 0x5a: machine().device<eeprom_device>("eeprom")->set_cs_line((data & 1) ? CLEAR_LINE : ASSERT_LINE ); break;
	146	//      case 0x5c: machine().device<eeprom_device>("eeprom")->set_cs_line((data & 1) ? CLEAR_LINE : ASSERT_LINE ); break;
146	147	case 0x60: break;
147	148	//      default: printf("[%02x] <- %02x W\n",offset*2,data);      break;
148	149	}
r14845	r14846
151	152	if(offset*2 == 0x54)
152	153	{
153	154	printf("Write bit %02x\n",data);
154		space->machine().device<eeprom_device>("eeprom")->write_bit(data & 1);
	155	machine().device<eeprom_device>("eeprom")->write_bit(data & 1);
155	156	}
156	157	if(offset*2 == 0x52)
157	158	{
158	159	printf("Clock bit %02x\n",data);
159		space->machine().device<eeprom_device>("eeprom")->set_clock_line((data & 1) ? ASSERT_LINE : CLEAR_LINE );
	160	machine().device<eeprom_device>("eeprom")->set_clock_line((data & 1) ? ASSERT_LINE : CLEAR_LINE );
160	161	}
161	162	if(offset*2 == 0x50)
162	163	{
163	164	printf("chip select bit %02x\n",data);
164		space->machine().device<eeprom_device>("eeprom")->set_cs_line((data & 1) ? CLEAR_LINE : ASSERT_LINE );
	165	machine().device<eeprom_device>("eeprom")->set_cs_line((data & 1) ? CLEAR_LINE : ASSERT_LINE );
165	166	}
166	167	#endif
167	168	}
r14845	r14846
174	175	AM_RANGE(0x348000, 0x34ffff) AM_RAM //<- vram banks 2 & 3?
175	176
176	177	AM_RANGE(0x360000, 0x3603ff) AM_RAM_WRITE_LEGACY(paletteram16_xxxxBBBBGGGGRRRR_word_w) AM_BASE_GENERIC(paletteram)
177		AM_RANGE(0x380000, 0x380061) AM_READWRITE_LEGACY(jackpool_io_r,jackpool_io_w) AM_BASE(m_io)//AM_READ_LEGACY(jackpool_io_r)
	178	AM_RANGE(0x380000, 0x380061) AM_READWRITE(jackpool_io_r,jackpool_io_w) AM_BASE(m_io)//AM_READ(jackpool_io_r)
178	179
179		AM_RANGE(0x800000, 0x80000f) AM_READ_LEGACY(jackpool_ff_r) AM_WRITENOP //UART
	180	AM_RANGE(0x800000, 0x80000f) AM_READ(jackpool_ff_r) AM_WRITENOP //UART
180	181	AM_RANGE(0xa00000, 0xa00001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
181	182	ADDRESS_MAP_END
182	183

src/mame/drivers/nmg5.c

r14845	r14846
254	254	/* devices */
255	255	device_t *m_maincpu;
256	256	device_t *m_soundcpu;
	257	DECLARE_WRITE16_MEMBER(fg_videoram_w);
	258	DECLARE_WRITE16_MEMBER(bg_videoram_w);
	259	DECLARE_WRITE16_MEMBER(nmg5_soundlatch_w);
	260	DECLARE_READ16_MEMBER(prot_r);
	261	DECLARE_WRITE16_MEMBER(prot_w);
	262	DECLARE_WRITE16_MEMBER(gfx_bank_w);
	263	DECLARE_WRITE16_MEMBER(priority_reg_w);
257	264	};
258	265
259	266
260	267
261		static WRITE16_HANDLER( fg_videoram_w )
	268	WRITE16_MEMBER(nmg5_state::fg_videoram_w)
262	269	{
263		nmg5_state *state = space->machine().driver_data<nmg5_state>();
264		COMBINE_DATA(&state->m_fg_videoram[offset]);
265		state->m_fg_tilemap->mark_tile_dirty(offset);
	270	COMBINE_DATA(&m_fg_videoram[offset]);
	271	m_fg_tilemap->mark_tile_dirty(offset);
266	272	}
267	273
268		static WRITE16_HANDLER( bg_videoram_w )
	274	WRITE16_MEMBER(nmg5_state::bg_videoram_w)
269	275	{
270		nmg5_state *state = space->machine().driver_data<nmg5_state>();
271		COMBINE_DATA(&state->m_bg_videoram[offset]);
272		state->m_bg_tilemap->mark_tile_dirty(offset);
	276	COMBINE_DATA(&m_bg_videoram[offset]);
	277	m_bg_tilemap->mark_tile_dirty(offset);
273	278	}
274	279
275		static WRITE16_HANDLER( nmg5_soundlatch_w )
	280	WRITE16_MEMBER(nmg5_state::nmg5_soundlatch_w)
276	281	{
277		nmg5_state *state = space->machine().driver_data<nmg5_state>();
278	282
279	283	if (ACCESSING_BITS_0_7)
280	284	{
281	285	soundlatch_w(space, 0, data & 0xff);
282		device_set_input_line(state->m_soundcpu, INPUT_LINE_NMI, PULSE_LINE);
	286	device_set_input_line(m_soundcpu, INPUT_LINE_NMI, PULSE_LINE);
283	287	}
284	288	}
285	289
286		static READ16_HANDLER( prot_r )
	290	READ16_MEMBER(nmg5_state::prot_r)
287	291	{
288		nmg5_state *state = space->machine().driver_data<nmg5_state>();
289		return state->m_prot_val | state->m_input_data;
	292	return m_prot_val | m_input_data;
290	293	}
291	294
292		static WRITE16_HANDLER( prot_w )
	295	WRITE16_MEMBER(nmg5_state::prot_w)
293	296	{
294		nmg5_state *state = space->machine().driver_data<nmg5_state>();
295		state->m_input_data = data & 0x0f;
	297	m_input_data = data & 0x0f;
296	298	}
297	299
298		static WRITE16_HANDLER( gfx_bank_w )
	300	WRITE16_MEMBER(nmg5_state::gfx_bank_w)
299	301	{
300		nmg5_state *state = space->machine().driver_data<nmg5_state>();
301	302
302		if (state->m_gfx_bank != (data & 3))
	303	if (m_gfx_bank != (data & 3))
303	304	{
304		state->m_gfx_bank = data & 3;
305		space->machine().tilemap().mark_all_dirty();
	305	m_gfx_bank = data & 3;
	306	machine().tilemap().mark_all_dirty();
306	307	}
307	308	}
308	309
309		static WRITE16_HANDLER( priority_reg_w )
	310	WRITE16_MEMBER(nmg5_state::priority_reg_w)
310	311	{
311		nmg5_state *state = space->machine().driver_data<nmg5_state>();
312	312
313		state->m_priority_reg = data & 7;
	313	m_priority_reg = data & 7;
314	314
315		if (state->m_priority_reg == 4 || state->m_priority_reg == 5 || state->m_priority_reg == 6)
316		popmessage("unknown priority_reg value = %d\n", state->m_priority_reg);
	315	if (m_priority_reg == 4 || m_priority_reg == 5 || m_priority_reg == 6)
	316	popmessage("unknown priority_reg value = %d\n", m_priority_reg);
317	317	}
318	318
319	319	static WRITE8_DEVICE_HANDLER( oki_banking_w )
r14845	r14846
332	332	AM_RANGE(0x120000, 0x12ffff) AM_RAM
333	333	AM_RANGE(0x140000, 0x1407ff) AM_RAM_WRITE_LEGACY(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)
334	334	AM_RANGE(0x160000, 0x1607ff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
335		AM_RANGE(0x180000, 0x180001) AM_WRITE_LEGACY(nmg5_soundlatch_w)
	335	AM_RANGE(0x180000, 0x180001) AM_WRITE(nmg5_soundlatch_w)
336	336	AM_RANGE(0x180002, 0x180003) AM_WRITENOP
337		AM_RANGE(0x180004, 0x180005) AM_READWRITE_LEGACY(prot_r, prot_w)
338		AM_RANGE(0x180006, 0x180007) AM_WRITE_LEGACY(gfx_bank_w)
	337	AM_RANGE(0x180004, 0x180005) AM_READWRITE(prot_r, prot_w)
	338	AM_RANGE(0x180006, 0x180007) AM_WRITE(gfx_bank_w)
339	339	AM_RANGE(0x180008, 0x180009) AM_READ_PORT("DSW")
340	340	AM_RANGE(0x18000a, 0x18000b) AM_READ_PORT("SYSTEM")
341	341	AM_RANGE(0x18000c, 0x18000d) AM_READ_PORT("INPUTS")
342		AM_RANGE(0x18000e, 0x18000f) AM_WRITE_LEGACY(priority_reg_w)
	342	AM_RANGE(0x18000e, 0x18000f) AM_WRITE(priority_reg_w)
343	343	AM_RANGE(0x300002, 0x300009) AM_WRITEONLY AM_BASE(m_scroll_ram)
344	344	AM_RANGE(0x30000a, 0x30000f) AM_WRITENOP
345		AM_RANGE(0x320000, 0x321fff) AM_RAM_WRITE_LEGACY(bg_videoram_w) AM_BASE(m_bg_videoram)
346		AM_RANGE(0x322000, 0x323fff) AM_RAM_WRITE_LEGACY(fg_videoram_w) AM_BASE(m_fg_videoram)
	345	AM_RANGE(0x320000, 0x321fff) AM_RAM_WRITE(bg_videoram_w) AM_BASE(m_bg_videoram)
	346	AM_RANGE(0x322000, 0x323fff) AM_RAM_WRITE(fg_videoram_w) AM_BASE(m_fg_videoram)
347	347	AM_RANGE(0x800000, 0x80ffff) AM_RAM AM_BASE(m_bitmap)
348	348	ADDRESS_MAP_END
349	349
r14845	r14846
352	352	AM_RANGE(0x200000, 0x20ffff) AM_RAM
353	353	AM_RANGE(0x440000, 0x4407ff) AM_RAM_WRITE_LEGACY(paletteram16_xBBBBBGGGGGRRRRR_word_w) AM_BASE_GENERIC(paletteram)
354	354	AM_RANGE(0x460000, 0x4607ff) AM_RAM AM_BASE_SIZE(m_spriteram, m_spriteram_size)
355		AM_RANGE(0x480000, 0x480001) AM_WRITE_LEGACY(nmg5_soundlatch_w)
	355	AM_RANGE(0x480000, 0x480001) AM_WRITE(nmg5_soundlatch_w)
356	356	AM_RANGE(0x480002, 0x480003) AM_WRITENOP
357		AM_RANGE(0x480004, 0x480005) AM_READWRITE_LEGACY(prot_r, prot_w)
358		AM_RANGE(0x480006, 0x480007) AM_WRITE_LEGACY(gfx_bank_w)
	357	AM_RANGE(0x480004, 0x480005) AM_READWRITE(prot_r, prot_w)
	358	AM_RANGE(0x480006, 0x480007) AM_WRITE(gfx_bank_w)
359	359	AM_RANGE(0x480008, 0x480009) AM_READ_PORT("DSW")
360	360	AM_RANGE(0x48000a, 0x48000b) AM_READ_PORT("SYSTEM")
361	361	AM_RANGE(0x48000c, 0x48000d) AM_READ_PORT("INPUTS")
362		AM_RANGE(0x48000e, 0x48000f) AM_WRITE_LEGACY(priority_reg_w)
	362	AM_RANGE(0x48000e, 0x48000f) AM_WRITE(priority_reg_w)
363	363	AM_RANGE(0x500002, 0x500009) AM_WRITEONLY AM_BASE(m_scroll_ram)
364		AM_RANGE(0x520000, 0x521fff) AM_RAM_WRITE_LEGACY(bg_videoram_w) AM_BASE(m_bg_videoram)
365		AM_RANGE(0x522000, 0x523fff) AM_RAM_WRITE_LEGACY(fg_videoram_w) AM_BASE(m_fg_videoram)
	364	AM_RANGE(0x520000, 0x521fff) AM_RAM_WRITE(bg_videoram_w) AM_BASE(m_bg_videoram)
	365	AM_RANGE(0x522000, 0x523fff) AM_RAM_WRITE(fg_videoram_w) AM_BASE(m_fg_videoram)
366	366	AM_RANGE(0x800000, 0x80ffff) AM_RAM AM_BASE(m_bitmap)
367	367	ADDRESS_MAP_END
368	368

src/mame/drivers/wink.c

r14845	r14846
27	27	tilemap_t *m_bg_tilemap;
28	28	UINT8 m_sound_flag;
29	29	UINT8 m_tile_bank;
	30	DECLARE_WRITE8_MEMBER(bgram_w);
	31	DECLARE_WRITE8_MEMBER(player_mux_w);
	32	DECLARE_WRITE8_MEMBER(tile_banking_w);
	33	DECLARE_WRITE8_MEMBER(wink_coin_counter_w);
	34	DECLARE_READ8_MEMBER(analog_port_r);
	35	DECLARE_READ8_MEMBER(player_inputs_r);
	36	DECLARE_WRITE8_MEMBER(sound_irq_w);
	37	DECLARE_READ8_MEMBER(prot_r);
	38	DECLARE_WRITE8_MEMBER(prot_w);
30	39	};
31	40
32	41
r14845	r14846
59	68	return 0;
60	69	}
61	70
62		static WRITE8_HANDLER( bgram_w )
	71	WRITE8_MEMBER(wink_state::bgram_w)
63	72	{
64		wink_state *state = space->machine().driver_data<wink_state>();
65		UINT8 *videoram = state->m_videoram;
	73	UINT8 *videoram = m_videoram;
66	74	videoram[offset] = data;
67		state->m_bg_tilemap->mark_tile_dirty(offset);
	75	m_bg_tilemap->mark_tile_dirty(offset);
68	76	}
69	77
70		static WRITE8_HANDLER( player_mux_w )
	78	WRITE8_MEMBER(wink_state::player_mux_w)
71	79	{
72	80	//player_mux = data & 1;
73	81	//no mux / cocktail mode in the real pcb? strange...
74	82	}
75	83
76		static WRITE8_HANDLER( tile_banking_w )
	84	WRITE8_MEMBER(wink_state::tile_banking_w)
77	85	{
78		wink_state *state = space->machine().driver_data<wink_state>();
79		state->m_tile_bank = data & 1;
80		state->m_bg_tilemap->mark_all_dirty();
	86	m_tile_bank = data & 1;
	87	m_bg_tilemap->mark_all_dirty();
81	88	}
82	89
83		static WRITE8_HANDLER( wink_coin_counter_w )
	90	WRITE8_MEMBER(wink_state::wink_coin_counter_w)
84	91	{
85		coin_counter_w(space->machine(), offset,data & 1);
	92	coin_counter_w(machine(), offset,data & 1);
86	93	}
87	94
88		static READ8_HANDLER( analog_port_r )
	95	READ8_MEMBER(wink_state::analog_port_r)
89	96	{
90		return input_port_read(space->machine(), /* player_mux ? "DIAL2" : */ "DIAL1");
	97	return input_port_read(machine(), /* player_mux ? "DIAL2" : */ "DIAL1");
91	98	}
92	99
93		static READ8_HANDLER( player_inputs_r )
	100	READ8_MEMBER(wink_state::player_inputs_r)
94	101	{
95		return input_port_read(space->machine(), /* player_mux ? "INPUTS2" : */ "INPUTS1");
	102	return input_port_read(machine(), /* player_mux ? "INPUTS2" : */ "INPUTS1");
96	103	}
97	104
98		static WRITE8_HANDLER( sound_irq_w )
	105	WRITE8_MEMBER(wink_state::sound_irq_w)
99	106	{
100		cputag_set_input_line(space->machine(), "audiocpu", 0, HOLD_LINE);
	107	cputag_set_input_line(machine(), "audiocpu", 0, HOLD_LINE);
101	108	//sync with sound cpu (but it still loses some soundlatches...)
102		//space->machine().scheduler().synchronize();
	109	//machine().scheduler().synchronize();
103	110	}
104	111
105	112	static ADDRESS_MAP_START( wink_map, AS_PROGRAM, 8, wink_state )
106	113	AM_RANGE(0x0000, 0x7fff) AM_ROM
107	114	AM_RANGE(0x8000, 0x87ff) AM_RAM
108	115	AM_RANGE(0x9000, 0x97ff) AM_RAM   AM_SHARE("nvram")
109		AM_RANGE(0xa000, 0xa3ff) AM_RAM_WRITE_LEGACY(bgram_w) AM_BASE(m_videoram)
	116	AM_RANGE(0xa000, 0xa3ff) AM_RAM_WRITE(bgram_w) AM_BASE(m_videoram)
110	117	ADDRESS_MAP_END
111	118
112	119
113		static READ8_HANDLER( prot_r )
	120	READ8_MEMBER(wink_state::prot_r)
114	121	{
115	122	//take a0-a7 and do some math using the variable created from the upper address-lines,
116	123	//put the result onto the databus.
r14845	r14846
130	137	return 0x20; //hack to pass the jump calculated using this value
131	138	}
132	139
133		static WRITE8_HANDLER( prot_w )
	140	WRITE8_MEMBER(wink_state::prot_w)
134	141	{
135	142	//take a9-a15 and stuff them in a variable for later use.
136	143	}
r14845	r14846
139	146	ADDRESS_MAP_GLOBAL_MASK(0xff)
140	147	AM_RANGE(0x00, 0x1f) AM_RAM_WRITE_LEGACY(paletteram_xxxxBBBBRRRRGGGG_le_w) AM_BASE_GENERIC(paletteram) //0x10-0x1f is likely to be something else
141	148	//  AM_RANGE(0x20, 0x20) AM_WRITENOP                //??? seems unused..
142		AM_RANGE(0x21, 0x21) AM_WRITE_LEGACY(player_mux_w)      //??? no mux on the pcb.
143		AM_RANGE(0x22, 0x22) AM_WRITE_LEGACY(tile_banking_w)
	149	AM_RANGE(0x21, 0x21) AM_WRITE(player_mux_w)      //??? no mux on the pcb.
	150	AM_RANGE(0x22, 0x22) AM_WRITE(tile_banking_w)
144	151	//  AM_RANGE(0x23, 0x23) AM_WRITENOP                //?
145	152	//  AM_RANGE(0x24, 0x24) AM_WRITENOP                //cab Knocker like in q-bert!
146		AM_RANGE(0x25, 0x27) AM_WRITE_LEGACY(wink_coin_counter_w)
	153	AM_RANGE(0x25, 0x27) AM_WRITE(wink_coin_counter_w)
147	154	AM_RANGE(0x40, 0x40) AM_WRITE_LEGACY(soundlatch_w)
148		AM_RANGE(0x60, 0x60) AM_WRITE_LEGACY(sound_irq_w)
149		AM_RANGE(0x80, 0x80) AM_READ_LEGACY(analog_port_r)
150		AM_RANGE(0xa0, 0xa0) AM_READ_LEGACY(player_inputs_r)
	155	AM_RANGE(0x60, 0x60) AM_WRITE(sound_irq_w)
	156	AM_RANGE(0x80, 0x80) AM_READ(analog_port_r)
	157	AM_RANGE(0xa0, 0xa0) AM_READ(player_inputs_r)
151	158	AM_RANGE(0xa4, 0xa4) AM_READ_PORT("DSW1")   //dipswitch bank2
152	159	AM_RANGE(0xa8, 0xa8) AM_READ_PORT("DSW2")   //dipswitch bank1
153	160	//  AM_RANGE(0xac, 0xac) AM_WRITENOP            //protection - loads video xor unit (written only once at startup)
154	161	AM_RANGE(0xb0, 0xb0) AM_READ_PORT("DSW3")   //unused inputs
155	162	AM_RANGE(0xb4, 0xb4) AM_READ_PORT("DSW4")   //dipswitch bank3
156		AM_RANGE(0xc0, 0xdf) AM_WRITE_LEGACY(prot_w)      //load load protection-buffer from upper address bus
	163	AM_RANGE(0xc0, 0xdf) AM_WRITE(prot_w)      //load load protection-buffer from upper address bus
157	164	AM_RANGE(0xc3, 0xc3) AM_READNOP            //watchdog?
158		AM_RANGE(0xe0, 0xff) AM_READ_LEGACY(prot_r)      //load math unit from buffer & lower address-bus
	165	AM_RANGE(0xe0, 0xff) AM_READ(prot_r)      //load math unit from buffer & lower address-bus
159	166	ADDRESS_MAP_END
160	167
161	168	static ADDRESS_MAP_START( wink_sound_map, AS_PROGRAM, 8, wink_state )

src/mame/drivers/corona.c

r14845	r14846
331	331	UINT8 m_lamp;
332	332	UINT8 m_lamp_old;
333	333	int m_input_selector;
	334	DECLARE_WRITE8_MEMBER(blitter_y_w);
	335	DECLARE_WRITE8_MEMBER(blitter_unk_w);
	336	DECLARE_WRITE8_MEMBER(blitter_x_w);
	337	DECLARE_WRITE8_MEMBER(blitter_aux_w);
	338	DECLARE_READ8_MEMBER(blitter_status_r);
	339	DECLARE_WRITE8_MEMBER(blitter_trig_wdht_w);
	340	DECLARE_WRITE8_MEMBER(sound_latch_w);
	341	DECLARE_READ8_MEMBER(sound_latch_r);
	342	DECLARE_WRITE8_MEMBER(ball_w);
	343	DECLARE_READ8_MEMBER(mux_port_r);
	344	DECLARE_WRITE8_MEMBER(mux_port_w);
	345	DECLARE_WRITE8_MEMBER(wc_meters_w);
	346	void blitter_execute(int x, int y, int color, int width, int flag);
334	347	};
335	348
336	349
r14845	r14846
365	378	}
366	379	}
367	380
368		static WRITE8_HANDLER( blitter_y_w )
	381	WRITE8_MEMBER(corona_state::blitter_y_w)
369	382	{
370		corona_state *state = space->machine().driver_data<corona_state>();
371		state->m_blitter_y_reg = data;
	383	m_blitter_y_reg = data;
372	384	}
373	385
374		static WRITE8_HANDLER( blitter_unk_w )
	386	WRITE8_MEMBER(corona_state::blitter_unk_w)
375	387	{
376		corona_state *state = space->machine().driver_data<corona_state>();
377		state->m_blitter_unk_reg = data;
	388	m_blitter_unk_reg = data;
378	389	}
379	390
380		static WRITE8_HANDLER( blitter_x_w )
	391	WRITE8_MEMBER(corona_state::blitter_x_w)
381	392	{
382		corona_state *state = space->machine().driver_data<corona_state>();
383		state->m_blitter_x_reg = data;
	393	m_blitter_x_reg = data;
384	394	}
385	395
386		static WRITE8_HANDLER( blitter_aux_w )
	396	WRITE8_MEMBER(corona_state::blitter_aux_w)
387	397	{
388		corona_state *state = space->machine().driver_data<corona_state>();
389		state->m_blitter_aux_reg = data;
	398	m_blitter_aux_reg = data;
390	399	}
391	400
392		static READ8_HANDLER( blitter_status_r )
	401	READ8_MEMBER(corona_state::blitter_status_r)
393	402	{
394	403	/* code checks bit 6 and/or bit 7 */
395		//return space->machine().rand() & 0xc0;
	404	//return machine().rand() & 0xc0;
396	405	/*
397	406	x--- ---- blitter busy
398	407	-x-- ---- vblank
399	408	*/
400	409
401		return 0x80 | ((space->machine().primary_screen->vblank() & 1) << 6);
	410	return 0x80 | ((machine().primary_screen->vblank() & 1) << 6);
402	411	}
403	412
404		static void blitter_execute(corona_state *state, int x, int y, int color, int width, int flag)
	413	void corona_state::blitter_execute(int x, int y, int color, int width, int flag)
405	414	{
406	415	int i;
407	416	int xdir = (flag & 0x10)    ? -1 : 1;
r14845	r14846
419	428
420	429	for(yp = 0; yp < 0x100; yp++)
421	430	for(xp = 0; xp < 0x100; xp++)
422		state->m_videobuf[(yp & 0x1ff) * 512 + (xp & 0x1ff)] = color;
	431	m_videobuf[(yp & 0x1ff) * 512 + (xp & 0x1ff)] = color;
423	432	}
424	433	else /* line shape */
425	434	{
r14845	r14846
427	436
428	437	for(i = 0; i < width; i++)
429	438	{
430		state->m_videobuf[(y & 0x1ff) * 512 + (x & 0x1ff)] = color;
	439	m_videobuf[(y & 0x1ff) * 512 + (x & 0x1ff)] = color;
431	440
432	441	if(flag & 0x40) { x+=xdir; }
433	442	if(flag & 0x80) { y+=ydir; }
r14845	r14846
435	444	}
436	445	}
437	446
438		static WRITE8_HANDLER( blitter_trig_wdht_w)
	447	WRITE8_MEMBER(corona_state::blitter_trig_wdht_w)
439	448	{
440		corona_state *state = space->machine().driver_data<corona_state>();
441		blitter_execute(state, state->m_blitter_x_reg, 0x100 - state->m_blitter_y_reg, state->m_blitter_aux_reg & 0xf, data, state->m_blitter_aux_reg & 0xf0);
	449	blitter_execute(m_blitter_x_reg, 0x100 - m_blitter_y_reg, m_blitter_aux_reg & 0xf, data, m_blitter_aux_reg & 0xf0);
442	450	}
443	451
444	452	static VIDEO_START(winner)
r14845	r14846
476	484	*           Read & Write Handlers          *
477	485	*******************************************/
478	486
479		static WRITE8_HANDLER( sound_latch_w )
	487	WRITE8_MEMBER(corona_state::sound_latch_w)
480	488	{
481	489	soundlatch_w(space, 0, data & 0xff);
482		cputag_set_input_line(space->machine(), "soundcpu", 0, ASSERT_LINE);
	490	cputag_set_input_line(machine(), "soundcpu", 0, ASSERT_LINE);
483	491	}
484	492
485		static READ8_HANDLER( sound_latch_r )
	493	READ8_MEMBER(corona_state::sound_latch_r)
486	494	{
487		cputag_set_input_line(space->machine(), "soundcpu", 0, CLEAR_LINE);
	495	cputag_set_input_line(machine(), "soundcpu", 0, CLEAR_LINE);
488	496	return soundlatch_r(space, 0);
489	497	}
490	498
491	499
492		static WRITE8_HANDLER( ball_w )
	500	WRITE8_MEMBER(corona_state::ball_w)
493	501	{
494		corona_state *state = space->machine().driver_data<corona_state>();
495		state->m_lamp = data;
	502	m_lamp = data;
496	503
497	504	output_set_lamp_value(data, 1);
498		output_set_lamp_value(state->m_lamp_old, 0);
499		state->m_lamp_old = state->m_lamp;
	505	output_set_lamp_value(m_lamp_old, 0);
	506	m_lamp_old = m_lamp;
500	507	}
501	508
502	509
503	510	/********  Multiplexed Inputs  ********/
504	511
505	512
506		static READ8_HANDLER( mux_port_r )
	513	READ8_MEMBER(corona_state::mux_port_r)
507	514	{
508		corona_state *state = space->machine().driver_data<corona_state>();
509		switch( state->m_input_selector )
	515	switch( m_input_selector )
510	516	{
511		case 0x01: return input_port_read(space->machine(), "IN0-1");
512		case 0x02: return input_port_read(space->machine(), "IN0-2");
513		case 0x04: return input_port_read(space->machine(), "IN0-3");
514		case 0x08: return input_port_read(space->machine(), "IN0-4");
515		case 0x10: return input_port_read(space->machine(), "IN0-5");
516		case 0x20: return input_port_read(space->machine(), "IN0-6");
	517	case 0x01: return input_port_read(machine(), "IN0-1");
	518	case 0x02: return input_port_read(machine(), "IN0-2");
	519	case 0x04: return input_port_read(machine(), "IN0-3");
	520	case 0x08: return input_port_read(machine(), "IN0-4");
	521	case 0x10: return input_port_read(machine(), "IN0-5");
	522	case 0x20: return input_port_read(machine(), "IN0-6");
517	523	}
518	524
519	525	return 0xff;
520	526	}
521	527
522		static WRITE8_HANDLER( mux_port_w )
	528	WRITE8_MEMBER(corona_state::mux_port_w)
523	529	{
524		corona_state *state = space->machine().driver_data<corona_state>();
525	530	/*  - bits -
526	531	7654 3210
527	532	--xx xxxx   Input selector.
r14845	r14846
531	536	Data is written inverted.
532	537
533	538	*/
534		state->m_input_selector = (data ^ 0xff) & 0x3f;   /* Input Selector,  */
	539	m_input_selector = (data ^ 0xff) & 0x3f;   /* Input Selector,  */
535	540
536		coin_counter_w(space->machine(), 0, (data ^ 0xff) & 0x40);   /* Credits In (mechanical meters) */
537		coin_counter_w(space->machine(), 1, (data ^ 0xff) & 0x80);   /* Credits Out (mechanical meters) */
	541	coin_counter_w(machine(), 0, (data ^ 0xff) & 0x40);   /* Credits In (mechanical meters) */
	542	coin_counter_w(machine(), 1, (data ^ 0xff) & 0x80);   /* Credits Out (mechanical meters) */
538	543
539		//  logerror("muxsel: %02x \n", state->m_input_selector);
	544	//  logerror("muxsel: %02x \n", m_input_selector);
540	545	}
541	546
542		static WRITE8_HANDLER( wc_meters_w )
	547	WRITE8_MEMBER(corona_state::wc_meters_w)
543	548	{
544	549	/*  - bits -
545	550	7654 3210
r14845	r14846
552	557	Data is written inverted.
553	558
554	559	*/
555		coin_counter_w(space->machine(), 0, (data ^ 0xff) & 0x01);   /* Credits In */
556		coin_counter_w(space->machine(), 1, (data ^ 0xff) & 0x02);   /* Credits In (through Coin 3) */
557		coin_counter_w(space->machine(), 2, (data ^ 0xff) & 0x04);   /* Credits Out */
	560	coin_counter_w(machine(), 0, (data ^ 0xff) & 0x01);   /* Credits In */
	561	coin_counter_w(machine(), 1, (data ^ 0xff) & 0x02);   /* Credits In (through Coin 3) */
	562	coin_counter_w(machine(), 2, (data ^ 0xff) & 0x04);   /* Credits Out */
558	563
559	564	//  popmessage("meters: %02x", (data ^ 0xff));
560	565	}
r14845	r14846
605	610
606	611	static ADDRESS_MAP_START( winner81_cpu_io_map, AS_IO, 8, corona_state )
607	612	ADDRESS_MAP_GLOBAL_MASK(0xff)
608		AM_RANGE(0x70, 0x70) AM_WRITE_LEGACY(blitter_x_w)
609		AM_RANGE(0x71, 0x71) AM_WRITE_LEGACY(blitter_unk_w)
610		AM_RANGE(0x72, 0x72) AM_WRITE_LEGACY(blitter_trig_wdht_w)
611		AM_RANGE(0x74, 0x74) AM_WRITE_LEGACY(blitter_y_w)
612		AM_RANGE(0x75, 0x75) AM_READ_LEGACY(blitter_status_r)
613		AM_RANGE(0x76, 0x76) AM_WRITE_LEGACY(blitter_aux_w)
	613	AM_RANGE(0x70, 0x70) AM_WRITE(blitter_x_w)
	614	AM_RANGE(0x71, 0x71) AM_WRITE(blitter_unk_w)
	615	AM_RANGE(0x72, 0x72) AM_WRITE(blitter_trig_wdht_w)
	616	AM_RANGE(0x74, 0x74) AM_WRITE(blitter_y_w)
	617	AM_RANGE(0x75, 0x75) AM_READ(blitter_status_r)
	618	AM_RANGE(0x76, 0x76) AM_WRITE(blitter_aux_w)
614	619
615	620	AM_RANGE(0xd8, 0xd8) AM_WRITENOP         /* dunno, but is writing 0's very often */
616		AM_RANGE(0xdf, 0xdf) AM_WRITE_LEGACY(sound_latch_w)
	621	AM_RANGE(0xdf, 0xdf) AM_WRITE(sound_latch_w)
617	622
618	623	AM_RANGE(0xe8, 0xe8) AM_READ_PORT("IN0")   /* credits for players A, B, C, D */
619	624	AM_RANGE(0xe9, 0xe9) AM_READ_PORT("IN3")
r14845	r14846
622	627	AM_RANGE(0xec, 0xec) AM_READ_PORT("IN4")
623	628	AM_RANGE(0xed, 0xed) AM_READ_PORT("DSW1")   /* DIP switches bank 1 */
624	629	AM_RANGE(0xee, 0xee) AM_READ_PORT("DSW2")
625		AM_RANGE(0xef, 0xef) AM_WRITE_LEGACY(wc_meters_w)   /* meters: coin1 = bit0, coin2 = bit1, coinout = bit2 */
	630	AM_RANGE(0xef, 0xef) AM_WRITE(wc_meters_w)   /* meters: coin1 = bit0, coin2 = bit1, coinout = bit2 */
626	631	ADDRESS_MAP_END
627	632
628	633	static ADDRESS_MAP_START(  winner81_sound_map, AS_PROGRAM, 8, corona_state )
r14845	r14846
632	637
633	638	static ADDRESS_MAP_START(  winner81_sound_cpu_io_map, AS_IO, 8, corona_state )
634	639	ADDRESS_MAP_GLOBAL_MASK(0xff)
635		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(sound_latch_r)
	640	AM_RANGE(0x00, 0x00) AM_READ(sound_latch_r)
636	641	AM_RANGE(0x00, 0x01) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
637	642	ADDRESS_MAP_END
638	643
r14845	r14846
662	667
663	668	static ADDRESS_MAP_START( winner82_cpu_io_map, AS_IO, 8, corona_state )
664	669	ADDRESS_MAP_GLOBAL_MASK(0xff)
665		AM_RANGE(0xf0, 0xf0) AM_WRITE_LEGACY(blitter_x_w)
666		AM_RANGE(0xf1, 0xf1) AM_WRITE_LEGACY(blitter_y_w)
667		AM_RANGE(0xf2, 0xf2) AM_WRITE_LEGACY(blitter_trig_wdht_w)
668		AM_RANGE(0xf3, 0xf3) AM_WRITE_LEGACY(blitter_aux_w)
669		AM_RANGE(0xf4, 0xf4) AM_WRITE_LEGACY(blitter_unk_w)
670		AM_RANGE(0xf5, 0xf5) AM_READ_LEGACY(blitter_status_r)
	670	AM_RANGE(0xf0, 0xf0) AM_WRITE(blitter_x_w)
	671	AM_RANGE(0xf1, 0xf1) AM_WRITE(blitter_y_w)
	672	AM_RANGE(0xf2, 0xf2) AM_WRITE(blitter_trig_wdht_w)
	673	AM_RANGE(0xf3, 0xf3) AM_WRITE(blitter_aux_w)
	674	AM_RANGE(0xf4, 0xf4) AM_WRITE(blitter_unk_w)
	675	AM_RANGE(0xf5, 0xf5) AM_READ(blitter_status_r)
671	676
672	677	AM_RANGE(0xf8, 0xf8) AM_READ_PORT("DSW1")   /* coinage DIP SW */
673	678	AM_RANGE(0xf9, 0xf9) AM_READ_PORT("IN0")   /* controls for players A & B */
674	679	AM_RANGE(0xfa, 0xfa) AM_READ_PORT("IN1")   /* credits for players A, B, C, D */
675	680	AM_RANGE(0xfb, 0xfb) AM_READ_PORT("IN3")   /* single credits for players A, B, C, D, + fix bits 3, 4, 5, 6 in meters */
676		AM_RANGE(0xfc, 0xfc) AM_WRITE_LEGACY(wc_meters_w)
	681	AM_RANGE(0xfc, 0xfc) AM_WRITE(wc_meters_w)
677	682	AM_RANGE(0xfd, 0xfd) AM_READ_PORT("IN2")   /* controls for players C & D */
678		AM_RANGE(0xfe, 0xfe) AM_WRITE_LEGACY(sound_latch_w)
	683	AM_RANGE(0xfe, 0xfe) AM_WRITE(sound_latch_w)
679	684	AM_RANGE(0xff, 0xff) AM_READ_PORT("DSW2")   /* no idea */
680	685	ADDRESS_MAP_END
681	686
r14845	r14846
686	691
687	692	static ADDRESS_MAP_START( winner82_sound_cpu_io_map, AS_IO, 8, corona_state )
688	693	ADDRESS_MAP_GLOBAL_MASK(0xff)
689		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(sound_latch_r)
	694	AM_RANGE(0x00, 0x00) AM_READ(sound_latch_r)
690	695	AM_RANGE(0x00, 0x01) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
691	696	AM_RANGE(0x02, 0x03) AM_WRITENOP   /* socket for another ay, inited but never played */
692	697	ADDRESS_MAP_END
r14845	r14846
726	731
727	732	static ADDRESS_MAP_START( re800_cpu_io_map, AS_IO, 8, corona_state )
728	733	ADDRESS_MAP_GLOBAL_MASK(0xff)
729		AM_RANGE(0xf0, 0xf0) AM_WRITE_LEGACY(blitter_x_w)
730		AM_RANGE(0xf1, 0xf1) AM_WRITE_LEGACY(blitter_y_w)
731		AM_RANGE(0xf2, 0xf2) AM_WRITE_LEGACY(blitter_trig_wdht_w)
732		AM_RANGE(0xf3, 0xf3) AM_WRITE_LEGACY(blitter_aux_w)
733		AM_RANGE(0xf4, 0xf4) AM_WRITE_LEGACY(blitter_unk_w)
734		AM_RANGE(0xf5, 0xf5) AM_READ_LEGACY(blitter_status_r)
	734	AM_RANGE(0xf0, 0xf0) AM_WRITE(blitter_x_w)
	735	AM_RANGE(0xf1, 0xf1) AM_WRITE(blitter_y_w)
	736	AM_RANGE(0xf2, 0xf2) AM_WRITE(blitter_trig_wdht_w)
	737	AM_RANGE(0xf3, 0xf3) AM_WRITE(blitter_aux_w)
	738	AM_RANGE(0xf4, 0xf4) AM_WRITE(blitter_unk_w)
	739	AM_RANGE(0xf5, 0xf5) AM_READ(blitter_status_r)
735	740	AM_RANGE(0xf8, 0xf8) AM_READ_PORT("IN1")
736	741	AM_RANGE(0xf9, 0xf9) AM_READ_PORT("DSW1")
737		AM_RANGE(0xfc, 0xfc) AM_WRITE_LEGACY(mux_port_w)
738		AM_RANGE(0xfd, 0xfd) AM_READ_LEGACY(mux_port_r)
739		AM_RANGE(0xfe, 0xfe) AM_WRITE_LEGACY(sound_latch_w)
740		AM_RANGE(0xff, 0xff) AM_WRITE_LEGACY(ball_w)
	742	AM_RANGE(0xfc, 0xfc) AM_WRITE(mux_port_w)
	743	AM_RANGE(0xfd, 0xfd) AM_READ(mux_port_r)
	744	AM_RANGE(0xfe, 0xfe) AM_WRITE(sound_latch_w)
	745	AM_RANGE(0xff, 0xff) AM_WRITE(ball_w)
741	746	ADDRESS_MAP_END
742	747
743	748	static ADDRESS_MAP_START( re800_sound_map, AS_PROGRAM, 8, corona_state )
r14845	r14846
747	752
748	753	static ADDRESS_MAP_START( re800_sound_cpu_io_map, AS_IO, 8, corona_state )
749	754	ADDRESS_MAP_GLOBAL_MASK(0xff)
750		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(sound_latch_r)
	755	AM_RANGE(0x00, 0x00) AM_READ(sound_latch_r)
751	756	AM_RANGE(0x00, 0x01) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
752	757	ADDRESS_MAP_END
753	758
r14845	r14846
785	790
786	791	static ADDRESS_MAP_START( luckyrlt_cpu_io_map, AS_IO, 8, corona_state )
787	792	ADDRESS_MAP_GLOBAL_MASK(0xff)
788		AM_RANGE(0xf0, 0xf0) AM_WRITE_LEGACY(blitter_x_w)
789		AM_RANGE(0xf1, 0xf1) AM_WRITE_LEGACY(blitter_y_w)
790		AM_RANGE(0xf2, 0xf2) AM_WRITE_LEGACY(blitter_trig_wdht_w)
791		AM_RANGE(0xf3, 0xf3) AM_WRITE_LEGACY(blitter_aux_w)
792		AM_RANGE(0xf4, 0xf4) AM_WRITE_LEGACY(blitter_unk_w)
793		AM_RANGE(0xf5, 0xf5) AM_READ_LEGACY(blitter_status_r)
	793	AM_RANGE(0xf0, 0xf0) AM_WRITE(blitter_x_w)
	794	AM_RANGE(0xf1, 0xf1) AM_WRITE(blitter_y_w)
	795	AM_RANGE(0xf2, 0xf2) AM_WRITE(blitter_trig_wdht_w)
	796	AM_RANGE(0xf3, 0xf3) AM_WRITE(blitter_aux_w)
	797	AM_RANGE(0xf4, 0xf4) AM_WRITE(blitter_unk_w)
	798	AM_RANGE(0xf5, 0xf5) AM_READ(blitter_status_r)
794	799
795	800	AM_RANGE(0xf8, 0xf8) AM_READ_PORT("DSW2")
796		AM_RANGE(0xf9, 0xf9) AM_WRITE_LEGACY(ball_w)
	801	AM_RANGE(0xf9, 0xf9) AM_WRITE(ball_w)
797	802	AM_RANGE(0xfa, 0xfa) AM_READ_PORT("DSW1")
798		AM_RANGE(0xfc, 0xfc) AM_WRITE_LEGACY(mux_port_w)
799		AM_RANGE(0xfd, 0xfd) AM_READ_LEGACY(mux_port_r)
800		AM_RANGE(0xfe, 0xfe) AM_WRITE_LEGACY(sound_latch_w)
	803	AM_RANGE(0xfc, 0xfc) AM_WRITE(mux_port_w)
	804	AM_RANGE(0xfd, 0xfd) AM_READ(mux_port_r)
	805	AM_RANGE(0xfe, 0xfe) AM_WRITE(sound_latch_w)
801	806	ADDRESS_MAP_END
802	807
803	808	static ADDRESS_MAP_START( luckyrlt_sound_map, AS_PROGRAM, 8, corona_state )
r14845	r14846
807	812
808	813	static ADDRESS_MAP_START( luckyrlt_sound_cpu_io_map, AS_IO, 8, corona_state )
809	814	ADDRESS_MAP_GLOBAL_MASK(0xff)
810		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(sound_latch_r)
	815	AM_RANGE(0x00, 0x00) AM_READ(sound_latch_r)
811	816	AM_RANGE(0x00, 0x01) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
812	817	ADDRESS_MAP_END
813	818

src/mame/drivers/safarir.c

r14845	r14846
67	67	UINT8 m_port_last;
68	68	UINT8 m_port_last2;
69	69	samples_device *m_samples;
	70	DECLARE_WRITE8_MEMBER(ram_w);
	71	DECLARE_READ8_MEMBER(ram_r);
	72	DECLARE_WRITE8_MEMBER(ram_bank_w);
	73	DECLARE_WRITE8_MEMBER(safarir_audio_w);
70	74	};
71	75
72	76
r14845	r14846
76	80	*
77	81	*************************************/
78	82
79		static WRITE8_HANDLER( ram_w )
	83	WRITE8_MEMBER(safarir_state::ram_w)
80	84	{
81		safarir_state *state = space->machine().driver_data<safarir_state>();
82	85
83		if (state->m_ram_bank)
84		state->m_ram_2[offset] = data;
	86	if (m_ram_bank)
	87	m_ram_2[offset] = data;
85	88	else
86		state->m_ram_1[offset] = data;
	89	m_ram_1[offset] = data;
87	90
88		((offset & 0x0400) ? state->m_bg_tilemap : state->m_fg_tilemap)->mark_tile_dirty(offset & 0x03ff);
	91	((offset & 0x0400) ? m_bg_tilemap : m_fg_tilemap)->mark_tile_dirty(offset & 0x03ff);
89	92	}
90	93
91	94
92		static READ8_HANDLER( ram_r )
	95	READ8_MEMBER(safarir_state::ram_r)
93	96	{
94		safarir_state *state = space->machine().driver_data<safarir_state>();
95	97
96		return state->m_ram_bank ? state->m_ram_2[offset] : state->m_ram_1[offset];
	98	return m_ram_bank ? m_ram_2[offset] : m_ram_1[offset];
97	99	}
98	100
99	101
100		static WRITE8_HANDLER( ram_bank_w )
	102	WRITE8_MEMBER(safarir_state::ram_bank_w)
101	103	{
102		safarir_state *state = space->machine().driver_data<safarir_state>();
103	104
104		state->m_ram_bank = data & 0x01;
	105	m_ram_bank = data & 0x01;
105	106
106		space->machine().tilemap().mark_all_dirty();
	107	machine().tilemap().mark_all_dirty();
107	108	}
108	109
109	110
r14845	r14846
147	148	{
148	149	int color;
149	150	address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
150		UINT8 code = ram_r(space,tile_index | 0x400);
	151	safarir_state *state = machine.driver_data<safarir_state>();
	152	UINT8 code = state->ram_r(*space,tile_index | 0x400);
151	153
152	154	if (code & 0x80)
153	155	color = 6;   /* yellow */
r14845	r14846
169	171	{
170	172	int color, flags;
171	173	address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
	174	safarir_state *state = machine.driver_data<safarir_state>();
	175	UINT8 code = state->ram_r(*space,tile_index);
172	176
173		UINT8 code = ram_r(space,tile_index);
174
175	177	if (code & 0x80)
176	178	color = 7;   /* white */
177	179	else
r14845	r14846
232	234	#define CHANNEL_SOUND6      5
233	235
234	236
235		static WRITE8_HANDLER( safarir_audio_w )
	237	WRITE8_MEMBER(safarir_state::safarir_audio_w)
236	238	{
237		safarir_state *state = space->machine().driver_data<safarir_state>();
238		samples_device *samples = state->m_samples;
239		UINT8 rising_bits = data & ~state->m_port_last;
	239	samples_device *samples = m_samples;
	240	UINT8 rising_bits = data & ~m_port_last;
240	241
241	242	if (rising_bits == 0x12) samples->start(CHANNEL_SOUND1, SAMPLE_SOUND1_1);
242	243	if (rising_bits == 0x02) samples->start(CHANNEL_SOUND1, SAMPLE_SOUND1_2);
r14845	r14846
249	250
250	251	if (data == 0x13)
251	252	{
252		if ((rising_bits == 0x13 && state->m_port_last != 0x04) || (rising_bits == 0x01 && state->m_port_last == 0x12))
	253	if ((rising_bits == 0x13 && m_port_last != 0x04) || (rising_bits == 0x01 && m_port_last == 0x12))
253	254	{
254	255	samples->start(CHANNEL_SOUND4, SAMPLE_SOUND7);
255	256	}
256		else if (rising_bits == 0x03 && state->m_port_last2 == 0x15 && !samples->playing(CHANNEL_SOUND4))
	257	else if (rising_bits == 0x03 && m_port_last2 == 0x15 && !samples->playing(CHANNEL_SOUND4))
257	258	{
258	259	samples->start(CHANNEL_SOUND4, SAMPLE_SOUND4_1);
259	260	}
260	261	}
261		if (data == 0x53 && state->m_port_last == 0x55) samples->start(CHANNEL_SOUND4, SAMPLE_SOUND4_2);
	262	if (data == 0x53 && m_port_last == 0x55) samples->start(CHANNEL_SOUND4, SAMPLE_SOUND4_2);
262	263
263	264	if (data == 0x1f && rising_bits == 0x1f) samples->start(CHANNEL_SOUND5, SAMPLE_SOUND5_1);
264	265	if (data == 0x14 && (rising_bits == 0x14 || rising_bits == 0x04)) samples->start(CHANNEL_SOUND5, SAMPLE_SOUND5_2);
r14845	r14846
266	267	if (data == 0x07 && rising_bits == 0x07 && !samples->playing(CHANNEL_SOUND6))
267	268	samples->start(CHANNEL_SOUND6, SAMPLE_SOUND8);
268	269
269		state->m_port_last2 = state->m_port_last;
270		state->m_port_last = data;
	270	m_port_last2 = m_port_last;
	271	m_port_last = data;
271	272	}
272	273
273	274
r14845	r14846
338	339
339	340	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, safarir_state )
340	341	AM_RANGE(0x0000, 0x17ff) AM_ROM
341		AM_RANGE(0x2000, 0x27ff) AM_READWRITE_LEGACY(ram_r, ram_w) AM_SIZE(m_ram_size)
342		AM_RANGE(0x2800, 0x2800) AM_MIRROR(0x03ff) AM_READNOP AM_WRITE_LEGACY(ram_bank_w)
	342	AM_RANGE(0x2000, 0x27ff) AM_READWRITE(ram_r, ram_w) AM_SIZE(m_ram_size)
	343	AM_RANGE(0x2800, 0x2800) AM_MIRROR(0x03ff) AM_READNOP AM_WRITE(ram_bank_w)
343	344	AM_RANGE(0x2c00, 0x2cff) AM_MIRROR(0x03ff) AM_READNOP AM_WRITEONLY AM_BASE(m_bg_scroll)
344		AM_RANGE(0x3000, 0x30ff) AM_MIRROR(0x03ff) AM_WRITE_LEGACY(safarir_audio_w)   /* goes to SN76477 */
	345	AM_RANGE(0x3000, 0x30ff) AM_MIRROR(0x03ff) AM_WRITE(safarir_audio_w)   /* goes to SN76477 */
345	346	AM_RANGE(0x3400, 0x3400) AM_MIRROR(0x03ff) AM_WRITENOP   /* cleared at the beginning */
346	347	AM_RANGE(0x3800, 0x38ff) AM_MIRROR(0x03ff) AM_READ_PORT("INPUTS") AM_WRITENOP
347	348	AM_RANGE(0x3c00, 0x3cff) AM_MIRROR(0x03ff) AM_READ_PORT("DSW") AM_WRITENOP

src/mame/drivers/pzletime.c

r14845	r14846
40	40
41	41	/* misc */
42	42	int            m_ticket;
	43	DECLARE_WRITE16_MEMBER(mid_videoram_w);
	44	DECLARE_WRITE16_MEMBER(txt_videoram_w);
	45	DECLARE_WRITE16_MEMBER(ticket_w);
	46	DECLARE_WRITE16_MEMBER(video_regs_w);
43	47	};
44	48
45	49
r14845	r14846
134	138	return 0;
135	139	}
136	140
137		static WRITE16_HANDLER( mid_videoram_w )
	141	WRITE16_MEMBER(pzletime_state::mid_videoram_w)
138	142	{
139		pzletime_state *state = space->machine().driver_data<pzletime_state>();
140		COMBINE_DATA(&state->m_mid_videoram[offset]);
141		state->m_mid_tilemap->mark_tile_dirty(offset);
	143	COMBINE_DATA(&m_mid_videoram[offset]);
	144	m_mid_tilemap->mark_tile_dirty(offset);
142	145	}
143	146
144		static WRITE16_HANDLER( txt_videoram_w )
	147	WRITE16_MEMBER(pzletime_state::txt_videoram_w)
145	148	{
146		pzletime_state *state = space->machine().driver_data<pzletime_state>();
147		COMBINE_DATA(&state->m_txt_videoram[offset]);
148		state->m_txt_tilemap->mark_tile_dirty(offset);
	149	COMBINE_DATA(&m_txt_videoram[offset]);
	150	m_txt_tilemap->mark_tile_dirty(offset);
149	151	}
150	152
151	153	static WRITE16_DEVICE_HANDLER( eeprom_w )
r14845	r14846
159	161	}
160	162	}
161	163
162		static WRITE16_HANDLER( ticket_w )
	164	WRITE16_MEMBER(pzletime_state::ticket_w)
163	165	{
164		pzletime_state *state = space->machine().driver_data<pzletime_state>();
165	166
166	167	if (ACCESSING_BITS_0_7)
167		state->m_ticket = data & 1;
	168	m_ticket = data & 1;
168	169	}
169	170
170		static WRITE16_HANDLER( video_regs_w )
	171	WRITE16_MEMBER(pzletime_state::video_regs_w)
171	172	{
172		pzletime_state *state = space->machine().driver_data<pzletime_state>();
173	173	int i;
174	174
175		COMBINE_DATA(&state->m_video_regs[offset]);
	175	COMBINE_DATA(&m_video_regs[offset]);
176	176
177	177	if (offset == 0)
178	178	{
179		if (state->m_video_regs[0] > 0)
	179	if (m_video_regs[0] > 0)
180	180	{
181	181	for (i = 0; i < 0x300; i++)
182	182	{
183		palette_set_pen_contrast(space->machine(), i, (double)0x8000/(double)state->m_video_regs[0]);
	183	palette_set_pen_contrast(machine(), i, (double)0x8000/(double)m_video_regs[0]);
184	184	}
185	185	}
186	186	}
187	187	else if (offset == 1)
188	188	{
189		if (state->m_video_regs[1] > 0)
	189	if (m_video_regs[1] > 0)
190	190	{
191	191	for (i = 0x300; i < 32768 + 0x300; i++)
192	192	{
193		palette_set_pen_contrast(space->machine(), i, (double)0x8000/(double)state->m_video_regs[1]);
	193	palette_set_pen_contrast(machine(), i, (double)0x8000/(double)m_video_regs[1]);
194	194	}
195	195	}
196	196	}
r14845	r14846
209	209
210	210	static ADDRESS_MAP_START( pzletime_map, AS_PROGRAM, 16, pzletime_state )
211	211	AM_RANGE(0x000000, 0x3fffff) AM_ROM
212		AM_RANGE(0x700000, 0x700005) AM_RAM_WRITE_LEGACY(video_regs_w) AM_BASE(m_video_regs)
	212	AM_RANGE(0x700000, 0x700005) AM_RAM_WRITE(video_regs_w) AM_BASE(m_video_regs)
213	213	AM_RANGE(0x800000, 0x800001) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff)
214	214	AM_RANGE(0x900000, 0x9005ff) AM_RAM_WRITE_LEGACY(paletteram16_xRRRRRGGGGGBBBBB_word_w) AM_BASE_GENERIC(paletteram)
215	215	AM_RANGE(0xa00000, 0xa00007) AM_RAM AM_BASE(m_tilemap_regs)
216	216	AM_RANGE(0xb00000, 0xb3ffff) AM_RAM AM_BASE(m_bg_videoram)
217		AM_RANGE(0xc00000, 0xc00fff) AM_RAM_WRITE_LEGACY(mid_videoram_w) AM_BASE(m_mid_videoram)
218		AM_RANGE(0xc01000, 0xc01fff) AM_RAM_WRITE_LEGACY(txt_videoram_w) AM_BASE(m_txt_videoram)
	217	AM_RANGE(0xc00000, 0xc00fff) AM_RAM_WRITE(mid_videoram_w) AM_BASE(m_mid_videoram)
	218	AM_RANGE(0xc01000, 0xc01fff) AM_RAM_WRITE(txt_videoram_w) AM_BASE(m_txt_videoram)
219	219	AM_RANGE(0xd00000, 0xd01fff) AM_RAM AM_BASE(m_spriteram)
220	220	AM_RANGE(0xe00000, 0xe00001) AM_READ_PORT("INPUT") AM_DEVWRITE_LEGACY("eeprom", eeprom_w)
221		AM_RANGE(0xe00002, 0xe00003) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(ticket_w)
	221	AM_RANGE(0xe00002, 0xe00003) AM_READ_PORT("SYSTEM") AM_WRITE(ticket_w)
222	222	AM_RANGE(0xe00004, 0xe00005) AM_DEVWRITE_LEGACY("oki", oki_bank_w)
223	223	AM_RANGE(0xf00000, 0xf0ffff) AM_RAM
224	224	ADDRESS_MAP_END

src/mame/drivers/uapce.c

r14845	r14846
106	106	: driver_device(mconfig, type, tag) { }
107	107
108	108	UINT8 m_jamma_if_control_latch;
	109	DECLARE_WRITE8_MEMBER(jamma_if_control_latch_w);
	110	DECLARE_READ8_MEMBER(jamma_if_control_latch_r);
	111	DECLARE_READ8_MEMBER(jamma_if_read_dsw);
109	112	};
110	113
111	114	#define UAPCE_SOUND_EN   NODE_10
r14845	r14846
118	121	DISCRETE_SOUND_END
119	122
120	123
121		static WRITE8_HANDLER( jamma_if_control_latch_w )
	124	WRITE8_MEMBER(uapce_state::jamma_if_control_latch_w)
122	125	{
123		uapce_state *state = space->machine().driver_data<uapce_state>();
124		UINT8 diff = data ^ state->m_jamma_if_control_latch;
125		state->m_jamma_if_control_latch = data;
	126	UINT8 diff = data ^ m_jamma_if_control_latch;
	127	m_jamma_if_control_latch = data;
126	128
127	129	/*  D7 : Controls relay which connects the PCE R-AUDIO output to the common audio path.
128	130	(1= Relay closed, 0= Relay open) */
129		space->machine().sound().system_enable( (data >> 7) & 1 );
	131	machine().sound().system_enable( (data >> 7) & 1 );
130	132
131	133	/* D6 : Output to JAMMA connector KEY pin. Connected to /RESET on the PCE backplane connector.
132	134	(1= /RESET not asserted, 0= /RESET asserted) */
133	135
134	136	if ( diff & 0x40 )
135	137	{
136		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_RESET, (data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
	138	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_RESET, (data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
137	139	}
138	140
139	141	/* D5 : Connected to a TIP31 which may control the coin meter:
r14845	r14846
143	145
144	146	Pin 'z' is a normally ground connection, but on this board it is isolated from ground.
145	147	The wiring harness also has the corresponding wire separate from the others. */
146		coin_counter_w(space->machine(), 0, BIT(data,5));
	148	coin_counter_w(machine(), 0, BIT(data,5));
147	149
148	150	/* D4 : Connects the START1 switch input from the JAMMA connector to the
149	151	"RUN" key input of the control pad multiplexer.
r14845	r14846
153	155	752 Hz (D-3) square wave to be output on the common audio path.
154	156	(1= Tone output ON, 0= Tone output OFF) */
155	157
156		discrete_sound_w(space->machine().device("discrete"), UAPCE_SOUND_EN, BIT(data,3));
	158	discrete_sound_w(machine().device("discrete"), UAPCE_SOUND_EN, BIT(data,3));
157	159
158	160	/* D2 : Not latched, though software writes to this bit like it is. */
159	161
r14845	r14846
162	164	/* D0 : Not latched. */
163	165	}
164	166
165		static READ8_HANDLER( jamma_if_control_latch_r )
	167	READ8_MEMBER(uapce_state::jamma_if_control_latch_r)
166	168	{
167		uapce_state *state = space->machine().driver_data<uapce_state>();
168		return state->m_jamma_if_control_latch & 0x08;
	169	return m_jamma_if_control_latch & 0x08;
169	170	}
170	171
171		static READ8_HANDLER( jamma_if_read_dsw )
	172	READ8_MEMBER(uapce_state::jamma_if_read_dsw)
172	173	{
173	174	UINT8 dsw_val;
174	175
175		dsw_val = input_port_read(space->machine(),  "DSW" );
	176	dsw_val = input_port_read(machine(),  "DSW" );
176	177
177	178	if ( BIT( offset, 7 ) == 0 )
178	179	{
r14845	r14846
233	234	static ADDRESS_MAP_START( z80_map, AS_PROGRAM, 8, uapce_state )
234	235	AM_RANGE( 0x0000, 0x07FF) AM_ROM
235	236	AM_RANGE( 0x0800, 0x0FFF) AM_RAM
236		AM_RANGE( 0x1000, 0x17FF) AM_WRITE_LEGACY(jamma_if_control_latch_w )
237		AM_RANGE( 0x1800, 0x1FFF) AM_READ_LEGACY(jamma_if_read_dsw )
	237	AM_RANGE( 0x1000, 0x17FF) AM_WRITE(jamma_if_control_latch_w )
	238	AM_RANGE( 0x1800, 0x1FFF) AM_READ(jamma_if_read_dsw )
238	239	AM_RANGE( 0x2000, 0x27FF) AM_READ_PORT( "COIN" )
239		AM_RANGE( 0x2800, 0x2FFF) AM_READ_LEGACY(jamma_if_control_latch_r )
	240	AM_RANGE( 0x2800, 0x2FFF) AM_READ(jamma_if_control_latch_r )
240	241	ADDRESS_MAP_END
241	242
242	243

src/mame/drivers/aristmk5.c

r14845	r14846
74	74	emu_timer *m_mk5_VSYNC_timer;
75	75	UINT8 m_ext_latch;
76	76	UINT8 m_flyback;
	77	DECLARE_WRITE32_MEMBER(Ns5w48);
	78	DECLARE_READ32_MEMBER(Ns5x58);
	79	DECLARE_READ32_MEMBER(mk5_ioc_r);
	80	DECLARE_WRITE32_MEMBER(mk5_ioc_w);
	81	DECLARE_READ32_MEMBER(Ns5r50);
	82	DECLARE_WRITE32_MEMBER(sram_banksel_w);
77	83	};
78	84
79	85
r14845	r14846
84	90	state->m_mk5_VSYNC_timer->adjust(attotime::never);
85	91	}
86	92
87		static WRITE32_HANDLER(Ns5w48)
	93	WRITE32_MEMBER(aristmk5_state::Ns5w48)
88	94	{
89	95
90
91	96	/*
92	97	There is one writeable register which is written with the Ns5w48 strobe. It contains four bits which are
93	98	taken from bits 16 to 19 of the word being written. The register is cleared whenever the chip is reset. The
r14845	r14846
122	127	ROM:03400968                 TST     R1, #8          ; test vsync
123	128	*/
124	129
125		aristmk5_state *state = space->machine().driver_data<aristmk5_state>();
	130
126	131	ioc_regs[IRQ_STATUS_A] &= ~0x08;
127	132
128	133	/*          bit 1              bit 0 */
129	134	if((data &~(0x02)) && (data & (0x01))) // external video crystal is enabled. 25 mhz
130	135	{
131		state->m_mk5_VSYNC_timer->adjust(attotime::from_hz(50000)); // not sure but see above
	136	m_mk5_VSYNC_timer->adjust(attotime::from_hz(50000)); // not sure but see above
132	137	}
133	138	if((data &~(0x02)) && (data &~(0x01))) // video clock is enabled. 24 mhz
134	139	{
135		state->m_mk5_VSYNC_timer->adjust(attotime::from_hz(50000)); // not sure
	140	m_mk5_VSYNC_timer->adjust(attotime::from_hz(50000)); // not sure
136	141	}
137	142	if((data & (0x02)) && (data &~(0x01))) // video clock is enabled. 36 mhz
138	143	{
139		state->m_mk5_VSYNC_timer->adjust(attotime::from_hz(50000)); // not sure
	144	m_mk5_VSYNC_timer->adjust(attotime::from_hz(50000)); // not sure
140	145	}
141	146	if((data &(0x02)) && (data &(0x01))) // video clock is enabled. 24 mhz
142	147	{
143		state->m_mk5_VSYNC_timer->adjust(attotime::from_hz(50000)); // not sure
	148	m_mk5_VSYNC_timer->adjust(attotime::from_hz(50000)); // not sure
144	149	}
145	150	}
146	151
r14845	r14846
152	157
153	158	}
154	159
155		static READ32_HANDLER(Ns5x58)
	160	READ32_MEMBER(aristmk5_state::Ns5x58)
156	161	{
157	162	/*
158	163	1953.125 Hz for the operating system timer interrupt
r14845	r14846
172	177	`-------'                `-------------'
173	178	*/
174	179
175		aristmk5_state *state = space->machine().driver_data<aristmk5_state>();
	180
176	181	// reset 2KHz timer
177		state->m_mk5_2KHz_timer->adjust(attotime::from_hz(1953.125));
	182	m_mk5_2KHz_timer->adjust(attotime::from_hz(1953.125));
178	183	ioc_regs[IRQ_STATUS_A] &= ~0x01;
179		cputag_set_input_line(space->machine(), "maincpu", ARM_IRQ_LINE, CLEAR_LINE);
	184	cputag_set_input_line(machine(), "maincpu", ARM_IRQ_LINE, CLEAR_LINE);
180	185	return 0xffffffff;
181	186	}
182	187
183	188	/* same as plain AA but with the I2C unconnected */
184		static READ32_HANDLER( mk5_ioc_r )
	189	READ32_MEMBER(aristmk5_state::mk5_ioc_r)
185	190	{
186		aristmk5_state *state = space->machine().driver_data<aristmk5_state>();
187	191	UINT32 ioc_addr;
188	192
189	193	ioc_addr = offset*4;
r14845	r14846
194	198	{
195	199	int vert_pos;
196	200
197		vert_pos = space->machine().primary_screen->vpos();
198		state->m_flyback = (vert_pos <= vidc_regs[VIDC_VDSR] || vert_pos >= vidc_regs[VIDC_VDER]) ? 0x80 : 0x00;
	201	vert_pos = machine().primary_screen->vpos();
	202	m_flyback = (vert_pos <= vidc_regs[VIDC_VDSR] || vert_pos >= vidc_regs[VIDC_VDER]) ? 0x80 : 0x00;
199	203
200		//i2c_data = (i2cmem_sda_read(space->machine().device("i2cmem")) & 1);
	204	//i2c_data = (i2cmem_sda_read(machine().device("i2cmem")) & 1);
201	205
202		return (state->m_flyback) | (ioc_regs[CONTROL] & 0x7c) | (1<<1) | 1;
	206	return (m_flyback) | (ioc_regs[CONTROL] & 0x7c) | (1<<1) | 1;
203	207	}
204	208
205		return archimedes_ioc_r(space,offset,mem_mask);
	209	return archimedes_ioc_r(&space,offset,mem_mask);
206	210	}
207	211
208		static WRITE32_HANDLER( mk5_ioc_w )
	212	WRITE32_MEMBER(aristmk5_state::mk5_ioc_w)
209	213	{
210		aristmk5_state *state = space->machine().driver_data<aristmk5_state>();
211	214	UINT32 ioc_addr;
212	215
213	216	ioc_addr = offset*4;
214	217	ioc_addr >>= 16;
215	218	ioc_addr &= 0x37;
216	219
217		if(!state->m_ext_latch)
	220	if(!m_ext_latch)
218	221	{
219	222	if(((ioc_addr == 0x20) || (ioc_addr == 0x30)) && (offset & 0x1f) == 0)
220	223	{
r14845	r14846
222	225	return;
223	226	}
224	227	else
225		archimedes_ioc_w(space,offset,data,mem_mask);
	228	archimedes_ioc_w(&space,offset,data,mem_mask);
226	229	}
227	230	}
228	231
229		static READ32_HANDLER( Ns5r50 )
	232	READ32_MEMBER(aristmk5_state::Ns5r50)
230	233	{
231	234	return 0xf5; // checked inside the CPU check, unknown meaning
232	235	}
233	236
234		static WRITE32_HANDLER( sram_banksel_w )
	237	WRITE32_MEMBER(aristmk5_state::sram_banksel_w)
235	238	{
236	239	/*
237	240
r14845	r14846
245	248	checked against the other to verify that the stored data is correct.
246	249	Each chip is mapped to the same address, and the chip selected depends on the bank
247	250	select register. Access is mutually exclusive, increasing security with only one chip
248		visible in the CPU address space at a time. If the CPU crashes and overwrites
	251	visible in the CPU address &space at a time. If the CPU crashes and overwrites
249	252	memory only one of the three devices can be corrupted. On reset the bank select
250	253	register selects bank 0, which does not exist. The SRAMs are at banks 1,2,3.
251	254	Each of the SRAM chips may be powered from a separate battery, further reducing
r14845	r14846
286	289
287	290	4 pages of 32k for each sram chip.
288	291	*/
289		memory_set_bank(space->machine(),"sram_bank", (data & 0xc0) >> 6);
290		memory_set_bank(space->machine(),"sram_bank_nz", (data & 0xc0) >> 6);
	292	memory_set_bank(machine(),"sram_bank", (data & 0xc0) >> 6);
	293	memory_set_bank(machine(),"sram_bank_nz", (data & 0xc0) >> 6);
291	294	}
292	295
293	296	/* U.S games have no dram emulator enabled */
r14845	r14846
296	299	AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_BASE_LEGACY(&archimedes_memc_physmem) /* physical RAM - 16 MB for now, should be 512k for the A310 */
297	300
298	301	/* MK-5 overrides */
299		AM_RANGE(0x03010420, 0x03010423) AM_WRITE_LEGACY(sram_banksel_w) // SRAM bank select write
	302	AM_RANGE(0x03010420, 0x03010423) AM_WRITE(sram_banksel_w) // SRAM bank select write
300	303
301	304	//  AM_RANGE(0x0301049c, 0x0301051f) AM_DEVREADWRITE_LEGACY("eeprom", eeprom_r, eeprom_w) // eeprom ???
302	305
r14845	r14846
305	308	AM_RANGE(0x03220000, 0x0323ffff) AM_RAMBANK("sram_bank") //AM_BASE_SIZE_GENERIC(nvram) // nvram 32kbytes x 3
306	309
307	310	// bank5 slow
308		AM_RANGE(0x03250048, 0x0325004b) AM_WRITE_LEGACY(Ns5w48) //IOEB control register
309		AM_RANGE(0x03250050, 0x03250053) AM_READ_LEGACY(Ns5r50)  //IOEB ID register
310		AM_RANGE(0x03250058, 0x0325005b) AM_READ_LEGACY(Ns5x58)  //IOEB interrupt Latch
	311	AM_RANGE(0x03250048, 0x0325004b) AM_WRITE(Ns5w48) //IOEB control register
	312	AM_RANGE(0x03250050, 0x03250053) AM_READ(Ns5r50)  //IOEB ID register
	313	AM_RANGE(0x03250058, 0x0325005b) AM_READ(Ns5x58)  //IOEB interrupt Latch
311	314
312		AM_RANGE(0x03000000, 0x0331ffff) AM_READWRITE_LEGACY(mk5_ioc_r, mk5_ioc_w)
	315	AM_RANGE(0x03000000, 0x0331ffff) AM_READWRITE(mk5_ioc_r, mk5_ioc_w)
313	316	AM_RANGE(0x03320000, 0x0333ffff) AM_RAMBANK("sram_bank_nz") // AM_BASE_SIZE_GENERIC(nvram) // nvram 32kbytes x 3 NZ
314	317	AM_RANGE(0x03400000, 0x035fffff) AM_ROM AM_REGION("maincpu", 0) AM_WRITE_LEGACY(archimedes_vidc_w)
315	318	AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE_LEGACY(archimedes_memc_r, archimedes_memc_w)
r14845	r14846
322	325	AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_BASE_LEGACY(&archimedes_memc_physmem) /* physical RAM - 16 MB for now, should be 512k for the A310 */
323	326
324	327	/* MK-5 overrides */
325		AM_RANGE(0x03010420, 0x03010423) AM_WRITE_LEGACY(sram_banksel_w) // SRAM bank select write
	328	AM_RANGE(0x03010420, 0x03010423) AM_WRITE(sram_banksel_w) // SRAM bank select write
326	329
327	330	//  AM_RANGE(0x0301049c, 0x0301051f) AM_DEVREADWRITE_LEGACY("eeprom", eeprom_r, eeprom_w) // eeprom ???
328	331
r14845	r14846
331	334	AM_RANGE(0x03220000, 0x0323ffff) AM_RAMBANK("sram_bank") //AM_BASE_SIZE_GENERIC(nvram) // nvram 32kbytes x 3
332	335
333	336	// bank5 slow
334		AM_RANGE(0x03250048, 0x0325004b) AM_WRITE_LEGACY(Ns5w48) //IOEB control register
335		AM_RANGE(0x03250050, 0x03250053) AM_READ_LEGACY(Ns5r50)  //IOEB ID register
336		AM_RANGE(0x03250058, 0x0325005b) AM_READ_LEGACY(Ns5x58)  //IOEB interrupt Latch
	337	AM_RANGE(0x03250048, 0x0325004b) AM_WRITE(Ns5w48) //IOEB control register
	338	AM_RANGE(0x03250050, 0x03250053) AM_READ(Ns5r50)  //IOEB ID register
	339	AM_RANGE(0x03250058, 0x0325005b) AM_READ(Ns5x58)  //IOEB interrupt Latch
337	340
338	341
339		AM_RANGE(0x03000000, 0x0331ffff) AM_READWRITE_LEGACY(mk5_ioc_r, mk5_ioc_w)
	342	AM_RANGE(0x03000000, 0x0331ffff) AM_READWRITE(mk5_ioc_r, mk5_ioc_w)
340	343	AM_RANGE(0x03320000, 0x0333ffff) AM_RAMBANK("sram_bank_nz") // AM_BASE_SIZE_GENERIC(nvram) // nvram 32kbytes x 3 NZ
341	344	AM_RANGE(0x03400000, 0x035fffff) AM_ROM AM_REGION("maincpu", 0) AM_WRITE_LEGACY(archimedes_vidc_w)
342	345	AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE_LEGACY(archimedes_memc_r, archimedes_memc_w)

src/mame/drivers/tmspoker.c

r14845	r14846
222	222
223	223	UINT8 *m_videoram;
224	224	tilemap_t *m_bg_tilemap;
	225	DECLARE_WRITE8_MEMBER(tmspoker_videoram_w);
	226	//DECLARE_WRITE8_MEMBER(debug_w);
	227	DECLARE_READ8_MEMBER(unk_r);
225	228	};
226	229
227	230
r14845	r14846
229	232	*     Video Hardware     *
230	233	*************************/
231	234
232		static WRITE8_HANDLER( tmspoker_videoram_w )
	235	WRITE8_MEMBER(tmspoker_state::tmspoker_videoram_w)
233	236	{
234		tmspoker_state *state = space->machine().driver_data<tmspoker_state>();
235		state->m_videoram[offset] = data;
236		state->m_bg_tilemap->mark_tile_dirty(offset);
	237	m_videoram[offset] = data;
	238	m_bg_tilemap->mark_tile_dirty(offset);
237	239	}
238	240
239	241
r14845	r14846
273	275	*  Read / Write Handlers  *
274	276	**************************/
275	277
276		//static WRITE8_HANDLER( debug_w )
	278	//WRITE8_MEMBER(tmspoker_state::debug_w)
277	279	//{
278	280	//  popmessage("written : %02X", data);
279	281	//}
r14845	r14846
314	316	AM_RANGE(0x0000, 0x0fff) AM_ROMBANK("bank1")
315	317	AM_RANGE(0x2800, 0x2800) AM_DEVWRITE("crtc", mc6845_device, address_w)
316	318	AM_RANGE(0x2801, 0x2801) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
317		AM_RANGE(0x3000, 0x33ff) AM_WRITE_LEGACY(tmspoker_videoram_w) AM_BASE(m_videoram)
	319	AM_RANGE(0x3000, 0x33ff) AM_WRITE(tmspoker_videoram_w) AM_BASE(m_videoram)
318	320	AM_RANGE(0x3800, 0x3fff) AM_RAM //NVRAM?
319	321	AM_RANGE(0x2000, 0x20ff) AM_RAM //color RAM?
320	322	ADDRESS_MAP_END
321	323
322	324
323		static READ8_HANDLER(unk_r)
	325	READ8_MEMBER(tmspoker_state::unk_r)
324	326	{
325	327	printf("%x\n",offset);
326		return 0;//0xff;//mame_rand(space->machine);
	328	return 0;//0xff;//mame_rand(machine);
327	329	}
328	330
329	331	static ADDRESS_MAP_START( tmspoker_cru_map, AS_IO, 8, tmspoker_state )
330		AM_RANGE(0x0000, 0xffff) AM_READ_LEGACY(unk_r)
	332	AM_RANGE(0x0000, 0xffff) AM_READ(unk_r)
331	333	ADDRESS_MAP_END
332	334
333	335	/* I/O byte R/W

src/mame/drivers/darkhors.c

r14845	r14846
83	83	UINT32 *m_spriteram;
84	84
85	85	required_device<cpu_device> m_maincpu;
	86	DECLARE_WRITE32_MEMBER(darkhors_tmapram_w);
	87	DECLARE_WRITE32_MEMBER(darkhors_tmapram2_w);
	88	DECLARE_WRITE32_MEMBER(paletteram32_xBBBBBGGGGGRRRRR_dword_w);
	89	DECLARE_WRITE32_MEMBER(darkhors_input_sel_w);
	90	DECLARE_READ32_MEMBER(darkhors_input_sel_r);
	91	DECLARE_WRITE32_MEMBER(darkhors_unk1_w);
	92	DECLARE_WRITE32_MEMBER(jclub2_tileram_w);
86	93	};
87	94
88	95
r14845	r14846
116	123	SET_TILE_INFO(0, tile/2, (color & 0x200) ? (color & 0x1ff) : ((color & 0x0ff) * 4) , 0);
117	124	}
118	125
119		static WRITE32_HANDLER( darkhors_tmapram_w )
	126	WRITE32_MEMBER(darkhors_state::darkhors_tmapram_w)
120	127	{
121		darkhors_state *state = space->machine().driver_data<darkhors_state>();
122		COMBINE_DATA(&state->m_tmapram[offset]);
123		state->m_tmap->mark_tile_dirty(offset);
	128	COMBINE_DATA(&m_tmapram[offset]);
	129	m_tmap->mark_tile_dirty(offset);
124	130	}
125		static WRITE32_HANDLER( darkhors_tmapram2_w )
	131	WRITE32_MEMBER(darkhors_state::darkhors_tmapram2_w)
126	132	{
127		darkhors_state *state = space->machine().driver_data<darkhors_state>();
128		COMBINE_DATA(&state->m_tmapram2[offset]);
129		state->m_tmap2->mark_tile_dirty(offset);
	133	COMBINE_DATA(&m_tmapram2[offset]);
	134	m_tmap2->mark_tile_dirty(offset);
130	135	}
131	136
132	137	static void draw_sprites(running_machine &machine, bitmap_ind16 &bitmap, const rectangle &cliprect)
r14845	r14846
263	268	}
264	269	}
265	270
266		static WRITE32_HANDLER( paletteram32_xBBBBBGGGGGRRRRR_dword_w )
	271	WRITE32_MEMBER(darkhors_state::paletteram32_xBBBBBGGGGGRRRRR_dword_w)
267	272	{
268	273	if (ACCESSING_BITS_16_31)   paletteram16_xBBBBBGGGGGRRRRR_word_w(space, offset*2, data >> 16, mem_mask >> 16);
269	274	if (ACCESSING_BITS_0_15)   paletteram16_xBBBBBGGGGGRRRRR_word_w(space, offset*2+1, data, mem_mask);
270	275	}
271	276
272		static WRITE32_HANDLER( darkhors_input_sel_w )
	277	WRITE32_MEMBER(darkhors_state::darkhors_input_sel_w)
273	278	{
274		darkhors_state *state = space->machine().driver_data<darkhors_state>();
275		COMBINE_DATA(&state->m_input_sel);
	279	COMBINE_DATA(&m_input_sel);
276	280	//  if (ACCESSING_BITS_16_31)    popmessage("%04X",data >> 16);
277	281	}
278	282
r14845	r14846
292	296	}
293	297	}
294	298
295		static READ32_HANDLER( darkhors_input_sel_r )
	299	READ32_MEMBER(darkhors_state::darkhors_input_sel_r)
296	300	{
297		darkhors_state *state = space->machine().driver_data<darkhors_state>();
298	301	// from bit mask to bit number
299		int bit_p1 = mask_to_bit((state->m_input_sel & 0x00ff0000) >> 16);
300		int bit_p2 = mask_to_bit((state->m_input_sel & 0xff000000) >> 24);
	302	int bit_p1 = mask_to_bit((m_input_sel & 0x00ff0000) >> 16);
	303	int bit_p2 = mask_to_bit((m_input_sel & 0xff000000) >> 24);
301	304	static const char *const portnames[] = { "IN0", "IN1", "IN2", "IN3", "IN4", "IN5", "IN6", "IN7" };
302	305
303		return   (input_port_read(space->machine(), portnames[bit_p1]) & 0x00ffffff) |
304		(input_port_read(space->machine(), portnames[bit_p2]) & 0xff000000) ;
	306	return   (input_port_read(machine(), portnames[bit_p1]) & 0x00ffffff) |
	307	(input_port_read(machine(), portnames[bit_p2]) & 0xff000000) ;
305	308	}
306	309
307		static WRITE32_HANDLER( darkhors_unk1_w )
	310	WRITE32_MEMBER(darkhors_state::darkhors_unk1_w)
308	311	{
309	312	// 0x1000 lockout
310	313	//  if (ACCESSING_BITS_16_31)    popmessage("%04X",data >> 16);
r14845	r14846
315	318	AM_RANGE(0x400000, 0x41ffff) AM_RAM
316	319
317	320	AM_RANGE(0x490040, 0x490043) AM_DEVWRITE_LEGACY("eeprom", darkhors_eeprom_w)
318		AM_RANGE(0x4e0080, 0x4e0083) AM_READ_PORT("4e0080") AM_WRITE_LEGACY(darkhors_unk1_w)
	321	AM_RANGE(0x4e0080, 0x4e0083) AM_READ_PORT("4e0080") AM_WRITE(darkhors_unk1_w)
319	322
320	323	AM_RANGE(0x580000, 0x580003) AM_READ_PORT("580000")
321	324	AM_RANGE(0x580004, 0x580007) AM_READ_PORT("580004")
322		AM_RANGE(0x580008, 0x58000b) AM_READ_LEGACY(darkhors_input_sel_r)
323		AM_RANGE(0x58000c, 0x58000f) AM_WRITE_LEGACY(darkhors_input_sel_w)
	325	AM_RANGE(0x580008, 0x58000b) AM_READ(darkhors_input_sel_r)
	326	AM_RANGE(0x58000c, 0x58000f) AM_WRITE(darkhors_input_sel_w)
324	327	AM_RANGE(0x580084, 0x580087) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0xff000000)
325	328	AM_RANGE(0x580200, 0x580203) AM_READNOP
326	329	AM_RANGE(0x580400, 0x580403) AM_READ_PORT("580400")
327	330	AM_RANGE(0x580420, 0x580423) AM_READ_PORT("580420")
328	331
329	332	AM_RANGE(0x800000, 0x86bfff) AM_RAM
330		AM_RANGE(0x86c000, 0x86ffff) AM_RAM_WRITE_LEGACY(darkhors_tmapram_w) AM_BASE(m_tmapram)
331		AM_RANGE(0x870000, 0x873fff) AM_RAM_WRITE_LEGACY(darkhors_tmapram2_w) AM_BASE(m_tmapram2)
	333	AM_RANGE(0x86c000, 0x86ffff) AM_RAM_WRITE(darkhors_tmapram_w) AM_BASE(m_tmapram)
	334	AM_RANGE(0x870000, 0x873fff) AM_RAM_WRITE(darkhors_tmapram2_w) AM_BASE(m_tmapram2)
332	335	AM_RANGE(0x874000, 0x87dfff) AM_RAM
333	336	AM_RANGE(0x87e000, 0x87ffff) AM_RAM AM_BASE(m_spriteram)
334		AM_RANGE(0x880000, 0x89ffff) AM_WRITE_LEGACY(paletteram32_xBBBBBGGGGGRRRRR_dword_w) AM_BASE_GENERIC(paletteram)
	337	AM_RANGE(0x880000, 0x89ffff) AM_WRITE(paletteram32_xBBBBBGGGGGRRRRR_dword_w) AM_BASE_GENERIC(paletteram)
335	338	AM_RANGE(0x8a0000, 0x8bffff) AM_WRITEONLY   // this should still be palette ram!
336	339	AM_RANGE(0x8c0120, 0x8c012f) AM_WRITEONLY AM_BASE(m_tmapscroll)
337	340	AM_RANGE(0x8c0130, 0x8c013f) AM_WRITEONLY AM_BASE(m_tmapscroll2)
338	341	ADDRESS_MAP_END
339	342
340	343
341		static WRITE32_HANDLER( jclub2_tileram_w )
	344	WRITE32_MEMBER(darkhors_state::jclub2_tileram_w)
342	345	{
343		darkhors_state *state = space->machine().driver_data<darkhors_state>();
344		COMBINE_DATA(&state->m_jclub2_tileram[offset]);
345		gfx_element_mark_dirty(space->machine().gfx[state->m_jclub2_gfx_index], offset/(256/4));
	346	COMBINE_DATA(&m_jclub2_tileram[offset]);
	347	gfx_element_mark_dirty(machine().gfx[m_jclub2_gfx_index], offset/(256/4));
346	348
347	349	}
348	350
r14845	r14846
351	353	AM_RANGE(0x400000, 0x41ffff) AM_RAM
352	354
353	355	AM_RANGE(0x490040, 0x490043) AM_DEVWRITE_LEGACY("eeprom", darkhors_eeprom_w)
354		AM_RANGE(0x4e0080, 0x4e0083) AM_READ_PORT("4e0080") AM_WRITE_LEGACY(darkhors_unk1_w)
	356	AM_RANGE(0x4e0080, 0x4e0083) AM_READ_PORT("4e0080") AM_WRITE(darkhors_unk1_w)
355	357
356	358	AM_RANGE(0x580000, 0x580003) AM_READ_PORT("580000")
357	359	AM_RANGE(0x580004, 0x580007) AM_READ_PORT("580004")
358		AM_RANGE(0x580008, 0x58000b) AM_READ_LEGACY(darkhors_input_sel_r)
359		AM_RANGE(0x58000c, 0x58000f) AM_WRITE_LEGACY(darkhors_input_sel_w)
	360	AM_RANGE(0x580008, 0x58000b) AM_READ(darkhors_input_sel_r)
	361	AM_RANGE(0x58000c, 0x58000f) AM_WRITE(darkhors_input_sel_w)
360	362	AM_RANGE(0x580200, 0x580203) AM_READNOP
361	363	AM_RANGE(0x580400, 0x580403) AM_READ_PORT("580400")
362	364	AM_RANGE(0x580420, 0x580423) AM_READ_PORT("580420")
363	365
364	366	AM_RANGE(0x800000, 0x87ffff) AM_RAM AM_BASE(m_spriteram)
365	367
366		AM_RANGE(0x880000, 0x89ffff) AM_WRITE_LEGACY(paletteram32_xBBBBBGGGGGRRRRR_dword_w) AM_BASE_GENERIC(paletteram)
	368	AM_RANGE(0x880000, 0x89ffff) AM_WRITE(paletteram32_xBBBBBGGGGGRRRRR_dword_w) AM_BASE_GENERIC(paletteram)
367	369	AM_RANGE(0x8a0000, 0x8bffff) AM_WRITEONLY   // this should still be palette ram!
368	370
369	371	AM_RANGE(0x8C0000, 0x8C01ff) AM_RAM
370	372	AM_RANGE(0x8E0000, 0x8E01ff) AM_RAM
371	373
372		AM_RANGE(0x900000, 0x90ffff) AM_RAM_WRITE_LEGACY(jclub2_tileram_w) AM_BASE(m_jclub2_tileram) // tile data gets decompressed here by main cpu?
	374	AM_RANGE(0x900000, 0x90ffff) AM_RAM_WRITE(jclub2_tileram_w) AM_BASE(m_jclub2_tileram) // tile data gets decompressed here by main cpu?
373	375	ADDRESS_MAP_END
374	376
375	377

src/mame/drivers/mirax.c

r14845	r14846
83	83	UINT8 m_nmi_mask;
84	84	UINT8 *m_videoram;
85	85	UINT8 *m_colorram;
	86	DECLARE_WRITE8_MEMBER(audio_w);
	87	DECLARE_READ8_MEMBER(unk_r);
	88	DECLARE_WRITE8_MEMBER(nmi_mask_w);
	89	DECLARE_WRITE8_MEMBER(mirax_sound_cmd_w);
	90	DECLARE_WRITE8_MEMBER(coin_lockout_w);
86	91	};
87	92
88	93
r14845	r14846
177	182	state->m_nAyCtrl = 0x00;
178	183	}
179	184
180		static WRITE8_HANDLER(audio_w)
	185	WRITE8_MEMBER(mirax_state::audio_w)
181	186	{
182		mirax_state *state = space->machine().driver_data<mirax_state>();
183	187
184		state->m_nAyCtrl=offset;
	188	m_nAyCtrl=offset;
185	189	}
186	190
187	191	static WRITE8_DEVICE_HANDLER(ay_sel)
r14845	r14846
194	198	}
195	199	}
196	200
197		static READ8_HANDLER( unk_r )
	201	READ8_MEMBER(mirax_state::unk_r)
198	202	{
199	203	return 0xff;
200	204	}
201	205
202		static WRITE8_HANDLER( nmi_mask_w )
	206	WRITE8_MEMBER(mirax_state::nmi_mask_w)
203	207	{
204		mirax_state *state = space->machine().driver_data<mirax_state>();
205		state->m_nmi_mask = data & 1;
	208	m_nmi_mask = data & 1;
206	209	if(data & 0xfe)
207	210	printf("Warning: %02x written at $f501\n",data);
208	211	}
209	212
210		static WRITE8_HANDLER( mirax_sound_cmd_w )
	213	WRITE8_MEMBER(mirax_state::mirax_sound_cmd_w)
211	214	{
212	215	soundlatch_w(space, 0, data & 0xff);
213		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_NMI, PULSE_LINE);
	216	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_NMI, PULSE_LINE);
214	217	}
215	218
216	219	/* might be coin counter instead */
217		static WRITE8_HANDLER( coin_lockout_w )
	220	WRITE8_MEMBER(mirax_state::coin_lockout_w)
218	221	{
219		coin_lockout_w(space->machine(), 0,data & 1);
220		coin_lockout_w(space->machine(), 1,data & 1);
	222	coin_lockout_w(space, 0,data & 1);
	223	coin_lockout_w(space, 1,data & 1);
221	224	}
222	225
223	226	static ADDRESS_MAP_START( mirax_main_map, AS_PROGRAM, 8, mirax_state )
r14845	r14846
229	232	AM_RANGE(0xf000, 0xf000) AM_READ_PORT("P1")
230	233	AM_RANGE(0xf100, 0xf100) AM_READ_PORT("P2")
231	234	AM_RANGE(0xf200, 0xf200) AM_READ_PORT("DSW1")
232		AM_RANGE(0xf300, 0xf300) AM_READ_LEGACY(unk_r) //watchdog? value is always read then discarded
	235	AM_RANGE(0xf300, 0xf300) AM_READ(unk_r) //watchdog? value is always read then discarded
233	236	AM_RANGE(0xf400, 0xf400) AM_READ_PORT("DSW2")
234		AM_RANGE(0xf500, 0xf500) AM_WRITE_LEGACY(coin_lockout_w)
235		AM_RANGE(0xf501, 0xf501) AM_WRITE_LEGACY(nmi_mask_w)
	237	AM_RANGE(0xf500, 0xf500) AM_WRITE(coin_lockout_w)
	238	AM_RANGE(0xf501, 0xf501) AM_WRITE(nmi_mask_w)
236	239	//  AM_RANGE(0xf506, 0xf506)
237	240	//  AM_RANGE(0xf507, 0xf507)
238		AM_RANGE(0xf800, 0xf800) AM_WRITE_LEGACY(mirax_sound_cmd_w)
	241	AM_RANGE(0xf800, 0xf800) AM_WRITE(mirax_sound_cmd_w)
239	242	//  AM_RANGE(0xf900, 0xf900) //sound cmd mirror? ack?
240	243	ADDRESS_MAP_END
241	244
r14845	r14846
252	255	AM_RANGE(0xe401, 0xe401) AM_WRITENOP
253	256	AM_RANGE(0xe403, 0xe403) AM_DEVWRITE_LEGACY("ay2", ay_sel) //2nd ay ?
254	257
255		AM_RANGE(0xf900, 0xf9ff) AM_WRITE_LEGACY(audio_w)
	258	AM_RANGE(0xf900, 0xf9ff) AM_WRITE(audio_w)
256	259	ADDRESS_MAP_END
257	260
258	261	static const gfx_layout layout16 =

src/mame/drivers/cardline.c

r14845	r14846
33	33	UINT8 *m_videoram;
34	34	UINT8 *m_colorram;
35	35	int m_var;
	36	DECLARE_WRITE8_MEMBER(vram_w);
	37	DECLARE_WRITE8_MEMBER(attr_w);
	38	DECLARE_WRITE8_MEMBER(video_w);
	39	DECLARE_READ8_MEMBER(unk_r);
	40	DECLARE_WRITE8_MEMBER(lamps_w);
36	41	};
37	42
38	43
r14845	r14846
70	75	return 0;
71	76	}
72	77
73		static WRITE8_HANDLER(vram_w)
	78	WRITE8_MEMBER(cardline_state::vram_w)
74	79	{
75		cardline_state *state = space->machine().driver_data<cardline_state>();
76		offset+=0x1000*((state->m_video&2)>>1);
77		state->m_videoram[offset]=data;
	80	offset+=0x1000*((m_video&2)>>1);
	81	m_videoram[offset]=data;
78	82	}
79	83
80		static WRITE8_HANDLER(attr_w)
	84	WRITE8_MEMBER(cardline_state::attr_w)
81	85	{
82		cardline_state *state = space->machine().driver_data<cardline_state>();
83		offset+=0x1000*((state->m_video&2)>>1);
84		state->m_colorram[offset]=data;
	86	offset+=0x1000*((m_video&2)>>1);
	87	m_colorram[offset]=data;
85	88	}
86	89
87		static WRITE8_HANDLER(video_w)
	90	WRITE8_MEMBER(cardline_state::video_w)
88	91	{
89		cardline_state *state = space->machine().driver_data<cardline_state>();
90		state->m_video=data;
	92	m_video=data;
91	93	}
92	94
93		static READ8_HANDLER(unk_r)
	95	READ8_MEMBER(cardline_state::unk_r)
94	96	{
95		cardline_state *state = space->machine().driver_data<cardline_state>();
96		state->m_var^=0x10;
97		//printf("var %d\n",state->m_var);
98		return state->m_var;
	97	m_var^=0x10;
	98	//printf("var %d\n",m_var);
	99	return m_var;
99	100	}
100	101
101		static WRITE8_HANDLER(lamps_w)
	102	WRITE8_MEMBER(cardline_state::lamps_w)
102	103	{
103	104	/* button lamps 1-8 (collect, card 1-5, bet, start) */
104	105	output_set_lamp_value(5,(data >> 0) & 1);
r14845	r14846
120	121	AM_RANGE(0x2003, 0x2003) AM_READ_PORT("IN0")
121	122	AM_RANGE(0x2005, 0x2005) AM_READ_PORT("IN1")
122	123	AM_RANGE(0x2006, 0x2006) AM_READ_PORT("DSW")
123		AM_RANGE(0x2007, 0x2007) AM_WRITE_LEGACY(lamps_w)
	124	AM_RANGE(0x2007, 0x2007) AM_WRITE(lamps_w)
124	125	AM_RANGE(0x2008, 0x2008) AM_NOP
125	126	AM_RANGE(0x2080, 0x213f) AM_NOP
126	127	AM_RANGE(0x2400, 0x2400) AM_DEVREADWRITE("oki", okim6295_device, read, write)
r14845	r14846
128	129	AM_RANGE(0x2840, 0x2840) AM_NOP
129	130	AM_RANGE(0x2880, 0x2880) AM_NOP
130	131	AM_RANGE(0x3003, 0x3003) AM_NOP
131		AM_RANGE(0xc000, 0xdfff) AM_WRITE_LEGACY(vram_w) AM_BASE(m_videoram)
132		AM_RANGE(0xe000, 0xffff) AM_WRITE_LEGACY(attr_w) AM_BASE(m_colorram)
	132	AM_RANGE(0xc000, 0xdfff) AM_WRITE(vram_w) AM_BASE(m_videoram)
	133	AM_RANGE(0xe000, 0xffff) AM_WRITE(attr_w) AM_BASE(m_colorram)
133	134	/* Ports */
134		AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE_LEGACY(unk_r, video_w)
	135	AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(unk_r, video_w)
135	136	ADDRESS_MAP_END
136	137
137	138

src/mame/drivers/omegrace.c

r14845	r14846
229	229	omegrace_state(const machine_config &mconfig, device_type type, const char *tag)
230	230	: driver_device(mconfig, type, tag) { }
231	231
	232	DECLARE_READ8_MEMBER(omegrace_vg_go_r);
	233	DECLARE_READ8_MEMBER(omegrace_spinner1_r);
	234	DECLARE_WRITE8_MEMBER(omegrace_leds_w);
	235	DECLARE_WRITE8_MEMBER(omegrace_soundlatch_w);
232	236	};
233	237
234	238
r14845	r14846
253	257	*
254	258	*************************************/
255	259
256		static READ8_HANDLER( omegrace_vg_go_r )
	260	READ8_MEMBER(omegrace_state::omegrace_vg_go_r)
257	261	{
258		avgdvg_go_w(space,0,0);
	262	avgdvg_go_w(&space,0,0);
259	263	return 0;
260	264	}
261	265
r14845	r14846
291	295	};
292	296
293	297
294		static READ8_HANDLER( omegrace_spinner1_r )
	298	READ8_MEMBER(omegrace_state::omegrace_spinner1_r)
295	299	{
296		return (spinnerTable[input_port_read(space->machine(), "SPIN0") & 0x3f]);
	300	return (spinnerTable[input_port_read(machine(), "SPIN0") & 0x3f]);
297	301	}
298	302
299	303
r14845	r14846
304	308	*
305	309	*************************************/
306	310
307		static WRITE8_HANDLER( omegrace_leds_w )
	311	WRITE8_MEMBER(omegrace_state::omegrace_leds_w)
308	312	{
309	313	/* bits 0 and 1 are coin counters */
310		coin_counter_w(space->machine(), 0,data & 0x01);
311		coin_counter_w(space->machine(), 1,data & 0x02);
	314	coin_counter_w(machine(), 0,data & 0x01);
	315	coin_counter_w(machine(), 1,data & 0x02);
312	316
313	317	/* bits 2 to 5 are the start leds (4 and 5 cocktail only) */
314		set_led_status(space->machine(), 0,~data & 0x04);
315		set_led_status(space->machine(), 1,~data & 0x08);
316		set_led_status(space->machine(), 2,~data & 0x10);
317		set_led_status(space->machine(), 3,~data & 0x20);
	318	set_led_status(machine(), 0,~data & 0x04);
	319	set_led_status(machine(), 1,~data & 0x08);
	320	set_led_status(machine(), 2,~data & 0x10);
	321	set_led_status(machine(), 3,~data & 0x20);
318	322
319	323	/* bit 6 flips screen (not supported) */
320	324	}
321	325
322	326
323		static WRITE8_HANDLER( omegrace_soundlatch_w )
	327	WRITE8_MEMBER(omegrace_state::omegrace_soundlatch_w)
324	328	{
325	329	soundlatch_w (space, offset, data);
326		cputag_set_input_line(space->machine(), "audiocpu", 0, HOLD_LINE);
	330	cputag_set_input_line(machine(), "audiocpu", 0, HOLD_LINE);
327	331	}
328	332
329	333
r14845	r14846
345	349
346	350	static ADDRESS_MAP_START( port_map, AS_IO, 8, omegrace_state )
347	351	ADDRESS_MAP_GLOBAL_MASK(0xff)
348		AM_RANGE(0x08, 0x08) AM_READ_LEGACY(omegrace_vg_go_r)
	352	AM_RANGE(0x08, 0x08) AM_READ(omegrace_vg_go_r)
349	353	AM_RANGE(0x09, 0x09) AM_READ_LEGACY(watchdog_reset_r)
350	354	AM_RANGE(0x0a, 0x0a) AM_WRITE_LEGACY(avgdvg_reset_w)
351	355	AM_RANGE(0x0b, 0x0b) AM_READ_PORT("AVGDVG")            /* vg_halt */
r14845	r14846
353	357	AM_RANGE(0x17, 0x17) AM_READ_PORT("DSW2")            /* DIP SW C6 */
354	358	AM_RANGE(0x11, 0x11) AM_READ_PORT("IN0")            /* Player 1 input */
355	359	AM_RANGE(0x12, 0x12) AM_READ_PORT("IN1")            /* Player 2 input */
356		AM_RANGE(0x13, 0x13) AM_WRITE_LEGACY(omegrace_leds_w)         /* coin counters, leds, flip screen */
357		AM_RANGE(0x14, 0x14) AM_WRITE_LEGACY(omegrace_soundlatch_w)   /* Sound command */
358		AM_RANGE(0x15, 0x15) AM_READ_LEGACY(omegrace_spinner1_r)      /* 1st controller */
	360	AM_RANGE(0x13, 0x13) AM_WRITE(omegrace_leds_w)         /* coin counters, leds, flip screen */
	361	AM_RANGE(0x14, 0x14) AM_WRITE(omegrace_soundlatch_w)   /* Sound command */
	362	AM_RANGE(0x15, 0x15) AM_READ(omegrace_spinner1_r)      /* 1st controller */
359	363	AM_RANGE(0x16, 0x16) AM_READ_PORT("SPIN1")            /* 2nd controller (cocktail) */
360	364	ADDRESS_MAP_END
361	365

src/mame/drivers/dlair.c

r14845	r14846
99	99	optional_device<phillips_22vp932_device> m_22vp932;
100	100	UINT8 m_last_misc;
101	101	UINT8 m_laserdisc_data;
	102	DECLARE_WRITE8_MEMBER(misc_w);
	103	DECLARE_WRITE8_MEMBER(dleuro_misc_w);
	104	DECLARE_WRITE8_MEMBER(led_den1_w);
	105	DECLARE_WRITE8_MEMBER(led_den2_w);
	106	DECLARE_READ8_MEMBER(laserdisc_r);
	107	DECLARE_WRITE8_MEMBER(laserdisc_w);
102	108	};
103	109
104	110
r14845	r14846
285	291	*
286	292	*************************************/
287	293
288		static WRITE8_HANDLER( misc_w )
	294	WRITE8_MEMBER(dlair_state::misc_w)
289	295	{
290		dlair_state *state = space->machine().driver_data<dlair_state>();
291	296	/*
292	297	D0-D3 = B0-B3
293	298	D4 = coin counter
r14845	r14846
295	300	D6 = ENTER
296	301	D7 = INT/EXT
297	302	*/
298		UINT8 diff = data ^ state->m_last_misc;
299		state->m_last_misc = data;
	303	UINT8 diff = data ^ m_last_misc;
	304	m_last_misc = data;
300	305
301		coin_counter_w(space->machine(), 0, (~data >> 4) & 1);
	306	coin_counter_w(machine(), 0, (~data >> 4) & 1);
302	307
303	308	/* on bit 5 going low, push the data out to the laserdisc player */
304	309	if ((diff & 0x20) && !(data & 0x20))
305		state->laserdisc_data_w(state->m_laserdisc_data);
	310	laserdisc_data_w(m_laserdisc_data);
306	311
307	312	/* on bit 6 going low, we need to signal enter */
308		state->laserdisc_enter_w((data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
	313	laserdisc_enter_w((data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
309	314	}
310	315
311	316
312		static WRITE8_HANDLER( dleuro_misc_w )
	317	WRITE8_MEMBER(dlair_state::dleuro_misc_w)
313	318	{
314		dlair_state *state = space->machine().driver_data<dlair_state>();
315	319	/*
316	320	D0 = CHAR GEN ON+
317	321	D1 = KILL VIDEO+
r14845	r14846
322	326	D6 = ENTER
323	327	D7 = INT/EXT
324	328	*/
325		UINT8 diff = data ^ state->m_last_misc;
326		state->m_last_misc = data;
	329	UINT8 diff = data ^ m_last_misc;
	330	m_last_misc = data;
327	331
328		coin_counter_w(space->machine(), 1, (~data >> 3) & 1);
329		coin_counter_w(space->machine(), 0, (~data >> 4) & 1);
	332	coin_counter_w(machine(), 1, (~data >> 3) & 1);
	333	coin_counter_w(machine(), 0, (~data >> 4) & 1);
330	334
331	335	/* on bit 5 going low, push the data out to the laserdisc player */
332	336	if ((diff & 0x20) && !(data & 0x20))
333		state->laserdisc_data_w(state->m_laserdisc_data);
	337	laserdisc_data_w(m_laserdisc_data);
334	338
335	339	/* on bit 6 going low, we need to signal enter */
336		state->laserdisc_enter_w((data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
	340	laserdisc_enter_w((data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
337	341	}
338	342
339	343
340		static WRITE8_HANDLER( led_den1_w )
	344	WRITE8_MEMBER(dlair_state::led_den1_w)
341	345	{
342	346	output_set_digit_value(0 + (offset & 7), led_map[data & 0x0f]);
343	347	}
344	348
345	349
346		static WRITE8_HANDLER( led_den2_w )
	350	WRITE8_MEMBER(dlair_state::led_den2_w)
347	351	{
348	352	output_set_digit_value(8 + (offset & 7), led_map[data & 0x0f]);
349	353	}
r14845	r14846
370	374	}
371	375
372	376
373		static READ8_HANDLER( laserdisc_r )
	377	READ8_MEMBER(dlair_state::laserdisc_r)
374	378	{
375		dlair_state *state = space->machine().driver_data<dlair_state>();
376		UINT8 result = state->laserdisc_data_r();
	379	UINT8 result = laserdisc_data_r();
377	380	mame_printf_debug("laserdisc_r = %02X\n", result);
378	381	return result;
379	382	}
380	383
381	384
382		static WRITE8_HANDLER( laserdisc_w )
	385	WRITE8_MEMBER(dlair_state::laserdisc_w)
383	386	{
384		dlair_state *state = space->machine().driver_data<dlair_state>();
385		state->m_laserdisc_data = data;
	387	m_laserdisc_data = data;
386	388	}
387	389
388	390
r14845	r14846
400	402	AM_RANGE(0xc000, 0xc000) AM_MIRROR(0x1fc7) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
401	403	AM_RANGE(0xc008, 0xc008) AM_MIRROR(0x1fc7) AM_READ_PORT("CONTROLS")
402	404	AM_RANGE(0xc010, 0xc010) AM_MIRROR(0x1fc7) AM_READ_PORT("SERVICE")
403		AM_RANGE(0xc020, 0xc020) AM_MIRROR(0x1fc7) AM_READ_LEGACY(laserdisc_r)
	405	AM_RANGE(0xc020, 0xc020) AM_MIRROR(0x1fc7) AM_READ(laserdisc_r)
404	406	AM_RANGE(0xe000, 0xe000) AM_MIRROR(0x1fc7) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
405		AM_RANGE(0xe008, 0xe008) AM_MIRROR(0x1fc7) AM_WRITE_LEGACY(misc_w)
	407	AM_RANGE(0xe008, 0xe008) AM_MIRROR(0x1fc7) AM_WRITE(misc_w)
406	408	AM_RANGE(0xe010, 0xe010) AM_MIRROR(0x1fc7) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
407		AM_RANGE(0xe020, 0xe020) AM_MIRROR(0x1fc7) AM_WRITE_LEGACY(laserdisc_w)
408		AM_RANGE(0xe030, 0xe037) AM_MIRROR(0x1fc0) AM_WRITE_LEGACY(led_den2_w)
409		AM_RANGE(0xe038, 0xe03f) AM_MIRROR(0x1fc0) AM_WRITE_LEGACY(led_den1_w)
	409	AM_RANGE(0xe020, 0xe020) AM_MIRROR(0x1fc7) AM_WRITE(laserdisc_w)
	410	AM_RANGE(0xe030, 0xe037) AM_MIRROR(0x1fc0) AM_WRITE(led_den2_w)
	411	AM_RANGE(0xe038, 0xe03f) AM_MIRROR(0x1fc0) AM_WRITE(led_den1_w)
410	412	ADDRESS_MAP_END
411	413
412	414
r14845	r14846
424	426	AM_RANGE(0xc000, 0xc7ff) AM_MIRROR(0x1800) AM_RAM AM_BASE(m_videoram)
425	427	AM_RANGE(0xe000, 0xe000) AM_MIRROR(0x1f47) // WT LED 1
426	428	AM_RANGE(0xe008, 0xe008) AM_MIRROR(0x1f47) // WT LED 2
427		AM_RANGE(0xe010, 0xe010) AM_MIRROR(0x1f47) AM_WRITE_LEGACY(led_den1_w)         // WT EXT LED 1
428		AM_RANGE(0xe018, 0xe018) AM_MIRROR(0x1f47) AM_WRITE_LEGACY(led_den2_w)         // WT EXT LED 2
429		AM_RANGE(0xe020, 0xe020) AM_MIRROR(0x1f47) AM_WRITE_LEGACY(laserdisc_w)      // DISC WT
430		AM_RANGE(0xe028, 0xe028) AM_MIRROR(0x1f47) AM_WRITE_LEGACY(dleuro_misc_w)      // WT MISC
	429	AM_RANGE(0xe010, 0xe010) AM_MIRROR(0x1f47) AM_WRITE(led_den1_w)         // WT EXT LED 1
	430	AM_RANGE(0xe018, 0xe018) AM_MIRROR(0x1f47) AM_WRITE(led_den2_w)         // WT EXT LED 2
	431	AM_RANGE(0xe020, 0xe020) AM_MIRROR(0x1f47) AM_WRITE(laserdisc_w)      // DISC WT
	432	AM_RANGE(0xe028, 0xe028) AM_MIRROR(0x1f47) AM_WRITE(dleuro_misc_w)      // WT MISC
431	433	AM_RANGE(0xe030, 0xe030) AM_MIRROR(0x1f47) AM_WRITE_LEGACY(watchdog_reset_w)   // CLR WDOG
432	434	AM_RANGE(0xe080, 0xe080) AM_MIRROR(0x1f47) AM_READ_PORT("P1")         // CP A
433	435	AM_RANGE(0xe088, 0xe088) AM_MIRROR(0x1f47) AM_READ_PORT("SYSTEM")      // CP B
434	436	AM_RANGE(0xe090, 0xe090) AM_MIRROR(0x1f47) AM_READ_PORT("DSW1")         // OPT SW A
435	437	AM_RANGE(0xe098, 0xe098) AM_MIRROR(0x1f47) AM_READ_PORT("DSW2")         // OPT SW B
436		AM_RANGE(0xe0a0, 0xe0a0) AM_MIRROR(0x1f47) AM_READ_LEGACY(laserdisc_r)         // RD DISC DATA
	438	AM_RANGE(0xe0a0, 0xe0a0) AM_MIRROR(0x1f47) AM_READ(laserdisc_r)         // RD DISC DATA
437	439	ADDRESS_MAP_END
438	440
439	441

src/mame/drivers/jollyjgr.c

r14845	r14846
125	125	UINT8      m_bitmap_disable;
126	126	UINT8      m_tilemap_bank;
127	127	UINT8      m_pri;
	128	DECLARE_WRITE8_MEMBER(jollyjgr_videoram_w);
	129	DECLARE_WRITE8_MEMBER(jollyjgr_attrram_w);
	130	DECLARE_WRITE8_MEMBER(jollyjgr_misc_w);
	131	DECLARE_WRITE8_MEMBER(jollyjgr_coin_lookout_w);
128	132	};
129	133
130	134
r14845	r14846
134	138	*
135	139	*************************************/
136	140
137		static WRITE8_HANDLER( jollyjgr_videoram_w )
	141	WRITE8_MEMBER(jollyjgr_state::jollyjgr_videoram_w)
138	142	{
139		jollyjgr_state *state = space->machine().driver_data<jollyjgr_state>();
140		state->m_videoram[offset] = data;
141		state->m_bg_tilemap->mark_tile_dirty(offset);
	143	m_videoram[offset] = data;
	144	m_bg_tilemap->mark_tile_dirty(offset);
142	145	}
143	146
144		static WRITE8_HANDLER( jollyjgr_attrram_w )
	147	WRITE8_MEMBER(jollyjgr_state::jollyjgr_attrram_w)
145	148	{
146		jollyjgr_state *state = space->machine().driver_data<jollyjgr_state>();
147	149
148	150	if (offset & 1)
149	151	{
r14845	r14846
151	153	int i;
152	154
153	155	for (i = offset >> 1; i < 0x0400; i += 32)
154		state->m_bg_tilemap->mark_tile_dirty(i);
	156	m_bg_tilemap->mark_tile_dirty(i);
155	157	}
156	158	else
157	159	{
158		state->m_bg_tilemap->set_scrolly(offset >> 1, data);
	160	m_bg_tilemap->set_scrolly(offset >> 1, data);
159	161	}
160	162
161		state->m_colorram[offset] = data;
	163	m_colorram[offset] = data;
162	164	}
163	165
164		static WRITE8_HANDLER( jollyjgr_misc_w )
	166	WRITE8_MEMBER(jollyjgr_state::jollyjgr_misc_w)
165	167	{
166		jollyjgr_state *state = space->machine().driver_data<jollyjgr_state>();
167	168
168	169	// they could be swapped, because it always set "data & 3"
169		state->m_flip_x = data & 1;
170		state->m_flip_y = data & 2;
	170	m_flip_x = data & 1;
	171	m_flip_y = data & 2;
171	172
172	173	// same for these two (used by Frog & Spiders)
173		state->m_bitmap_disable = data & 0x40;
174		state->m_tilemap_bank = data & 0x20;
	174	m_bitmap_disable = data & 0x40;
	175	m_tilemap_bank = data & 0x20;
175	176
176		state->m_pri = data & 4;
	177	m_pri = data & 4;
177	178
178		state->m_bg_tilemap->set_flip((state->m_flip_x ? TILEMAP_FLIPX : 0) | (state->m_flip_y ? TILEMAP_FLIPY : 0));
	179	m_bg_tilemap->set_flip((m_flip_x ? TILEMAP_FLIPX : 0) | (m_flip_y ? TILEMAP_FLIPY : 0));
179	180
180		state->m_nmi_enable = data & 0x80;
	181	m_nmi_enable = data & 0x80;
181	182	}
182	183
183		static WRITE8_HANDLER( jollyjgr_coin_lookout_w )
	184	WRITE8_MEMBER(jollyjgr_state::jollyjgr_coin_lookout_w)
184	185	{
185		coin_lockout_global_w(space->machine(), data & 1);
	186	coin_lockout_global_w(machine(), data & 1);
186	187
187	188	/* bits 4, 5, 6 and 7 are used too */
188	189	}
r14845	r14846
200	201	AM_RANGE(0x8ff9, 0x8ff9) AM_READ_PORT("INPUTS")
201	202	AM_RANGE(0x8ff8, 0x8ff8) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
202	203	AM_RANGE(0x8ffa, 0x8ffa) AM_READ_PORT("SYSTEM") AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
203		AM_RANGE(0x8ffc, 0x8ffc) AM_WRITE_LEGACY(jollyjgr_misc_w)
204		AM_RANGE(0x8ffd, 0x8ffd) AM_WRITE_LEGACY(jollyjgr_coin_lookout_w)
	204	AM_RANGE(0x8ffc, 0x8ffc) AM_WRITE(jollyjgr_misc_w)
	205	AM_RANGE(0x8ffd, 0x8ffd) AM_WRITE(jollyjgr_coin_lookout_w)
205	206	AM_RANGE(0x8fff, 0x8fff) AM_READ_PORT("DSW2")
206		AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE_LEGACY(jollyjgr_videoram_w) AM_BASE(m_videoram)
207		AM_RANGE(0x9800, 0x983f) AM_RAM_WRITE_LEGACY(jollyjgr_attrram_w) AM_BASE(m_colorram)
	207	AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(jollyjgr_videoram_w) AM_BASE(m_videoram)
	208	AM_RANGE(0x9800, 0x983f) AM_RAM_WRITE(jollyjgr_attrram_w) AM_BASE(m_colorram)
208	209	AM_RANGE(0x9840, 0x987f) AM_RAM AM_BASE(m_spriteram)
209	210	AM_RANGE(0x9880, 0x9bff) AM_RAM
210	211	AM_RANGE(0xa000, 0xffff) AM_RAM AM_BASE(m_bitmap)
r14845	r14846
217	218	AM_RANGE(0x8ff9, 0x8ff9) AM_READ_PORT("INPUTS")
218	219	AM_RANGE(0x8ff8, 0x8ff8) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
219	220	AM_RANGE(0x8ffa, 0x8ffa) AM_READ_PORT("SYSTEM") AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
220		AM_RANGE(0x8ffc, 0x8ffc) AM_WRITE_LEGACY(jollyjgr_misc_w)
221		AM_RANGE(0x8ffd, 0x8ffd) AM_WRITE_LEGACY(jollyjgr_coin_lookout_w)
	221	AM_RANGE(0x8ffc, 0x8ffc) AM_WRITE(jollyjgr_misc_w)
	222	AM_RANGE(0x8ffd, 0x8ffd) AM_WRITE(jollyjgr_coin_lookout_w)
222	223	AM_RANGE(0x8fff, 0x8fff) AM_READ_PORT("DSW2")
223		AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE_LEGACY(jollyjgr_videoram_w) AM_BASE(m_videoram)
224		AM_RANGE(0x9800, 0x983f) AM_RAM_WRITE_LEGACY(jollyjgr_attrram_w) AM_BASE(m_colorram)
	224	AM_RANGE(0x9000, 0x93ff) AM_RAM_WRITE(jollyjgr_videoram_w) AM_BASE(m_videoram)
	225	AM_RANGE(0x9800, 0x983f) AM_RAM_WRITE(jollyjgr_attrram_w) AM_BASE(m_colorram)
225	226	AM_RANGE(0x9840, 0x987f) AM_RAM AM_BASE(m_spriteram)
226	227	AM_RANGE(0x9880, 0x989f) AM_RAM // ?
227	228	AM_RANGE(0x98a0, 0x98af) AM_RAM AM_BASE(m_bulletram)

src/mame/drivers/ssfindo.c

r14845	r14846
229	229	emu_timer *m_PS7500timer0;
230	230	emu_timer *m_PS7500timer1;
231	231	int m_iocr_hack;
	232	DECLARE_WRITE32_MEMBER(FIFO_w);
	233	DECLARE_READ32_MEMBER(PS7500_IO_r);
	234	DECLARE_WRITE32_MEMBER(PS7500_IO_w);
	235	DECLARE_READ32_MEMBER(io_r);
	236	DECLARE_WRITE32_MEMBER(io_w);
	237	DECLARE_WRITE32_MEMBER(debug_w);
	238	DECLARE_READ32_MEMBER(ff4_r);
	239	DECLARE_READ32_MEMBER(SIMPLEIO_r);
	240	DECLARE_READ32_MEMBER(randomized_r);
	241	DECLARE_READ32_MEMBER(tetfight_unk_r);
	242	DECLARE_WRITE32_MEMBER(tetfight_unk_w);
232	243	};
233	244
234	245
r14845	r14846
262	273	return 0;
263	274	}
264	275
265		static WRITE32_HANDLER(FIFO_w)
	276	WRITE32_MEMBER(ssfindo_state::FIFO_w)
266	277	{
267		ssfindo_state *state = space->machine().driver_data<ssfindo_state>();
268		state->m_PS7500_FIFO[data>>28]=data;
	278	m_PS7500_FIFO[data>>28]=data;
269	279
270	280	if(!(data>>28))
271	281	{
272		palette_set_color_rgb(space->machine(), state->m_PS7500_FIFO[1]&0xff, data&0xff,(data>>8)&0xff,(data>>16)&0xff);
273		state->m_PS7500_FIFO[1]++; //autoinc
	282	palette_set_color_rgb(machine(), m_PS7500_FIFO[1]&0xff, data&0xff,(data>>8)&0xff,(data>>16)&0xff);
	283	m_PS7500_FIFO[1]++; //autoinc
274	284	}
275	285	}
276	286	static TIMER_CALLBACK( PS7500_Timer0_callback )
r14845	r14846
354	364	}
355	365
356	366
357		static READ32_HANDLER(PS7500_IO_r)
	367	READ32_MEMBER(ssfindo_state::PS7500_IO_r)
358	368	{
359		ssfindo_state *state = space->machine().driver_data<ssfindo_state>();
360	369	switch(offset)
361	370	{
362	371	case MSECR:
363		return space->machine().rand();
	372	return machine().rand();
364	373
365	374	case IOLINES: //TODO: eeprom  24c01
366	375	#if 0
367		mame_printf_debug("IOLINESR %i @%x\n", offset, cpu_get_pc(&space->device()));
	376	mame_printf_debug("IOLINESR %i @%x\n", offset, cpu_get_pc(&space.device()));
368	377	#endif
369	378
370		if(state->m_flashType == 1)
	379	if(m_flashType == 1)
371	380	return 0;
372	381	else
373		return space->machine().rand();
	382	return machine().rand();
374	383
375	384	case IRQSTA:
376		return (state->m_PS7500_IO[offset] & (~2)) | 0x80;
	385	return (m_PS7500_IO[offset] & (~2)) | 0x80;
377	386
378	387	case IRQRQA:
379		return (state->m_PS7500_IO[IRQSTA] & state->m_PS7500_IO[IRQMSKA]) | 0x80;
	388	return (m_PS7500_IO[IRQSTA] & m_PS7500_IO[IRQMSKA]) | 0x80;
380	389
381	390	case IOCR: //TODO: nINT1, OD[n] p.81
382		if (ssfindo_speedup) ssfindo_speedup(space);
	391	if (ssfindo_speedup) ssfindo_speedup(&space);
383	392
384		if( state->m_iocr_hack)
	393	if( m_iocr_hack)
385	394	{
386		return (input_port_read(space->machine(), "PS7500") & 0x80) | 0x34 | (space->machine().rand()&3); //eeprom read ?
	395	return (input_port_read(machine(), "PS7500") & 0x80) | 0x34 | (machine().rand()&3); //eeprom read ?
387	396	}
388	397
389		return (input_port_read(space->machine(), "PS7500") & 0x80) | 0x37;
	398	return (input_port_read(machine(), "PS7500") & 0x80) | 0x37;
390	399
391	400	case VIDCR:
392		return (state->m_PS7500_IO[offset] | 0x50) & 0xfffffff0;
	401	return (m_PS7500_IO[offset] | 0x50) & 0xfffffff0;
393	402
394	403	case T1low:
395	404	case T0low:
r14845	r14846
400	409	case VIDSTART:
401	410	case VIDINITA: //TODO: bits 29 ("equal") and 30 (last bit)  p.105
402	411
403		return state->m_PS7500_IO[offset];
	412	return m_PS7500_IO[offset];
404	413
405	414
406	415	}
407		return space->machine().rand();//state->m_PS7500_IO[offset];
	416	return machine().rand();//m_PS7500_IO[offset];
408	417	}
409	418
410		static WRITE32_HANDLER(PS7500_IO_w)
	419	WRITE32_MEMBER(ssfindo_state::PS7500_IO_w)
411	420	{
412		ssfindo_state *state = space->machine().driver_data<ssfindo_state>();
413		UINT32 temp=state->m_PS7500_IO[offset];
	421	UINT32 temp=m_PS7500_IO[offset];
414	422
415	423	COMBINE_DATA(&temp);
416	424
417	425	switch(offset)
418	426	{
419	427	case IOLINES: //TODO: eeprom  24c01
420		state->m_PS7500_IO[offset]=data;
	428	m_PS7500_IO[offset]=data;
421	429	if(data&0xc0)
422		state->m_adrLatch=0;
	430	m_adrLatch=0;
423	431
424		if(cpu_get_pc(&space->device()) == 0xbac0 && state->m_flashType == 1)
	432	if(cpu_get_pc(&space.device()) == 0xbac0 && m_flashType == 1)
425	433	{
426		state->m_flashN=data&1;
	434	m_flashN=data&1;
427	435	}
428	436
429	437	#if 0
430		logerror("IOLINESW %i = %x  @%x\n",offset,data,cpu_get_pc(&space->device()));
	438	logerror("IOLINESW %i = %x  @%x\n",offset,data,cpu_get_pc(&space.device()));
431	439	#endif
432	440	break;
433	441
434	442	case IRQRQA:
435		state->m_PS7500_IO[IRQSTA]&=~temp;
	443	m_PS7500_IO[IRQSTA]&=~temp;
436	444	break;
437	445
438	446	case IRQMSKA:
439		state->m_PS7500_IO[IRQMSKA]=(temp&(~2))|0x80;
	447	m_PS7500_IO[IRQMSKA]=(temp&(~2))|0x80;
440	448	break;
441	449
442	450	case T1GO:
443		PS7500_startTimer1(space->machine());
	451	PS7500_startTimer1(machine());
444	452	break;
445	453
446	454	case T0GO:
447		PS7500_startTimer0(space->machine());
	455	PS7500_startTimer0(machine());
448	456	break;
449	457
450	458	case VIDEND:
451	459	case VIDSTART:
452		COMBINE_DATA(&state->m_PS7500_IO[offset]);
453		state->m_PS7500_IO[offset]&=0xfffffff0; // qword align
	460	COMBINE_DATA(&m_PS7500_IO[offset]);
	461	m_PS7500_IO[offset]&=0xfffffff0; // qword align
454	462	break;
455	463
456	464	case IOCR:
r14845	r14846
466	474	case T0high:
467	475	case VIDCR:
468	476	case VIDINITA: //TODO: bit 30 (last bit) p.105
469		COMBINE_DATA(&state->m_PS7500_IO[offset]);
	477	COMBINE_DATA(&m_PS7500_IO[offset]);
470	478	break;
471	479
472	480
r14845	r14846
474	482	}
475	483	}
476	484
477		static READ32_HANDLER(io_r)
	485	READ32_MEMBER(ssfindo_state::io_r)
478	486	{
479		ssfindo_state *state = space->machine().driver_data<ssfindo_state>();
480		UINT16 *FLASH = (UINT16 *)space->machine().region("user2")->base(); //16 bit - WORD access
	487	UINT16 *FLASH = (UINT16 *)machine().region("user2")->base(); //16 bit - WORD access
481	488
482		int adr=state->m_flashAdr*0x200+(state->m_flashOffset);
	489	int adr=m_flashAdr*0x200+(m_flashOffset);
483	490
484	491
485		switch(state->m_flashType)
	492	switch(m_flashType)
486	493	{
487	494	case 0:
488		if(state->m_PS7500_IO[IOLINES]&1) //bit 0 of IOLINES  = flash select ( 5/6 or 3/2 )
	495	if(m_PS7500_IO[IOLINES]&1) //bit 0 of IOLINES  = flash select ( 5/6 or 3/2 )
489	496	adr+=0x400000;
490	497	break;
491	498
492	499	case 1:
493		adr+=0x400000*state->m_flashN;
	500	adr+=0x400000*m_flashN;
494	501	break;
495	502	}
496	503
497	504	if(adr<0x400000*2)
498	505	{
499		state->m_flashOffset++;
	506	m_flashOffset++;
500	507	return FLASH[adr];
501	508	}
502	509	return 0;
503	510	}
504	511
505		static WRITE32_HANDLER(io_w)
	512	WRITE32_MEMBER(ssfindo_state::io_w)
506	513	{
507		ssfindo_state *state = space->machine().driver_data<ssfindo_state>();
508	514	UINT32 temp = 0;
509	515	COMBINE_DATA(&temp);
510	516
511	517	#if 0
512		logerror("[io_w] = %x @%x [latch=%x]\n",data,cpu_get_pc(&space->device()),state->m_adrLatch);
	518	logerror("[io_w] = %x @%x [latch=%x]\n",data,cpu_get_pc(&space.device()),m_adrLatch);
513	519	#endif
514	520
515		if(state->m_adrLatch==1)
516		state->m_flashAdr=(temp>>16)&0xff;
517		if(state->m_adrLatch==2)
	521	if(m_adrLatch==1)
	522	m_flashAdr=(temp>>16)&0xff;
	523	if(m_adrLatch==2)
518	524	{
519		state->m_flashAdr|=(temp>>16)&0xff00;
520		state->m_flashOffset=0;
	525	m_flashAdr|=(temp>>16)&0xff00;
	526	m_flashOffset=0;
521	527	}
522		state->m_adrLatch=(state->m_adrLatch+1)%3;
	528	m_adrLatch=(m_adrLatch+1)%3;
523	529	}
524	530
525		static WRITE32_HANDLER(debug_w)
	531	WRITE32_MEMBER(ssfindo_state::debug_w)
526	532	{
527	533	#if 0
528	534	mame_printf_debug("%c",data&0xff); //debug texts - malloc (ie "64 KBytes allocated, elapsed : 378 KBytes, free : 2231 KBytes")
529	535	#endif
530	536	}
531	537
532		static READ32_HANDLER(ff4_r)
	538	READ32_MEMBER(ssfindo_state::ff4_r)
533	539	{
534		return space->machine().rand()&0x20;
	540	return machine().rand()&0x20;
535	541	}
536	542
537		static READ32_HANDLER(SIMPLEIO_r)
	543	READ32_MEMBER(ssfindo_state::SIMPLEIO_r)
538	544	{
539		return space->machine().rand()&1;
	545	return machine().rand()&1;
540	546	}
541	547
542		static READ32_HANDLER(randomized_r)
	548	READ32_MEMBER(ssfindo_state::randomized_r)
543	549	{
544		return space->machine().rand();
	550	return machine().rand();
545	551	}
546	552
547	553	static ADDRESS_MAP_START( ssfindo_map, AS_PROGRAM, 32, ssfindo_state )
548	554	AM_RANGE(0x00000000, 0x000fffff) AM_ROM AM_REGION("user1", 0)
549		AM_RANGE(0x03200000, 0x032001ff) AM_READWRITE_LEGACY(PS7500_IO_r,PS7500_IO_w)
	555	AM_RANGE(0x03200000, 0x032001ff) AM_READWRITE(PS7500_IO_r,PS7500_IO_w)
550	556	AM_RANGE(0x03012e60, 0x03012e67) AM_NOP
551		AM_RANGE(0x03012fe0, 0x03012fe3) AM_WRITE_LEGACY(debug_w)
	557	AM_RANGE(0x03012fe0, 0x03012fe3) AM_WRITE(debug_w)
552	558	AM_RANGE(0x03012ff0, 0x03012ff3) AM_NOP
553		AM_RANGE(0x03012ff4, 0x03012ff7) AM_WRITENOP AM_READ_LEGACY(ff4_r) //status flag ?
	559	AM_RANGE(0x03012ff4, 0x03012ff7) AM_WRITENOP AM_READ(ff4_r) //status flag ?
554	560	AM_RANGE(0x03012ff8, 0x03012fff) AM_NOP
555	561	AM_RANGE(0x03240000, 0x03240003) AM_READ_PORT("IN0") AM_WRITENOP
556	562	AM_RANGE(0x03241000, 0x03241003) AM_READ_PORT("IN1") AM_WRITENOP
557		AM_RANGE(0x03242000, 0x03242003) AM_READ_LEGACY(io_r) AM_WRITE_LEGACY(io_w)
	563	AM_RANGE(0x03242000, 0x03242003) AM_READ(io_r) AM_WRITE(io_w)
558	564	AM_RANGE(0x03243000, 0x03243003) AM_READ_PORT("DSW") AM_WRITENOP
559		AM_RANGE(0x0324f000, 0x0324f003) AM_READ_LEGACY(SIMPLEIO_r)
	565	AM_RANGE(0x0324f000, 0x0324f003) AM_READ(SIMPLEIO_r)
560	566	AM_RANGE(0x03245000, 0x03245003) AM_WRITENOP /* sound ? */
561		AM_RANGE(0x03400000, 0x03400003) AM_WRITE_LEGACY(FIFO_w)
	567	AM_RANGE(0x03400000, 0x03400003) AM_WRITE(FIFO_w)
562	568	AM_RANGE(0x10000000, 0x11ffffff) AM_RAM AM_BASE(m_vram)
563	569	ADDRESS_MAP_END
564	570
565	571	static ADDRESS_MAP_START( ppcar_map, AS_PROGRAM, 32, ssfindo_state )
566	572	AM_RANGE(0x00000000, 0x000fffff) AM_ROM AM_REGION("user1", 0)
567		AM_RANGE(0x03200000, 0x032001ff) AM_READWRITE_LEGACY(PS7500_IO_r,PS7500_IO_w)
568		AM_RANGE(0x03012b00, 0x03012bff) AM_READ_LEGACY(randomized_r) AM_WRITENOP
	573	AM_RANGE(0x03200000, 0x032001ff) AM_READWRITE(PS7500_IO_r,PS7500_IO_w)
	574	AM_RANGE(0x03012b00, 0x03012bff) AM_READ(randomized_r) AM_WRITENOP
569	575	AM_RANGE(0x03012e60, 0x03012e67) AM_WRITENOP
570	576	AM_RANGE(0x03012ff8, 0x03012ffb) AM_READ_PORT("IN0") AM_WRITENOP
571	577	AM_RANGE(0x032c0000, 0x032c0003) AM_READ_PORT("IN1") AM_WRITENOP
572	578	AM_RANGE(0x03340000, 0x03340007) AM_WRITENOP
573	579	AM_RANGE(0x03341000, 0x0334101f) AM_WRITENOP
574		AM_RANGE(0x033c0000, 0x033c0003) AM_READ_LEGACY(io_r) AM_WRITE_LEGACY(io_w)
575		AM_RANGE(0x03400000, 0x03400003) AM_WRITE_LEGACY(FIFO_w)
	580	AM_RANGE(0x033c0000, 0x033c0003) AM_READ(io_r) AM_WRITE(io_w)
	581	AM_RANGE(0x03400000, 0x03400003) AM_WRITE(FIFO_w)
576	582	AM_RANGE(0x08000000, 0x08ffffff) AM_RAM
577	583	AM_RANGE(0x10000000, 0x10ffffff) AM_RAM AM_BASE(m_vram)
578	584	ADDRESS_MAP_END
579	585
580		static READ32_HANDLER(tetfight_unk_r)
	586	READ32_MEMBER(ssfindo_state::tetfight_unk_r)
581	587	{
582	588	//sound status ?
583		return space->machine().rand();
	589	return machine().rand();
584	590	}
585	591
586		static WRITE32_HANDLER(tetfight_unk_w)
	592	WRITE32_MEMBER(ssfindo_state::tetfight_unk_w)
587	593	{
588	594	//sound latch ?
589	595	}
590	596
591	597	static ADDRESS_MAP_START( tetfight_map, AS_PROGRAM, 32, ssfindo_state )
592	598	AM_RANGE(0x00000000, 0x001fffff) AM_ROM AM_REGION("user1", 0)
593		AM_RANGE(0x03200000, 0x032001ff) AM_READWRITE_LEGACY(PS7500_IO_r,PS7500_IO_w)
594		AM_RANGE(0x03400000, 0x03400003) AM_WRITE_LEGACY(FIFO_w)
	599	AM_RANGE(0x03200000, 0x032001ff) AM_READWRITE(PS7500_IO_r,PS7500_IO_w)
	600	AM_RANGE(0x03400000, 0x03400003) AM_WRITE(FIFO_w)
595	601	AM_RANGE(0x03240000, 0x03240003) AM_READ_PORT("DSW")
596	602	AM_RANGE(0x03240004, 0x03240007) AM_READ_PORT("IN0")
597	603	AM_RANGE(0x03240008, 0x0324000b) AM_READ_PORT("DSW2")
598		AM_RANGE(0x03240020, 0x03240023) AM_READWRITE_LEGACY(tetfight_unk_r, tetfight_unk_w)
	604	AM_RANGE(0x03240020, 0x03240023) AM_READWRITE(tetfight_unk_r, tetfight_unk_w)
599	605	AM_RANGE(0x10000000, 0x14ffffff) AM_RAM AM_BASE(m_vram)
600	606	ADDRESS_MAP_END
601	607

src/mame/drivers/peplus.c

r14845	r14846
206	206	UINT64 m_last_coin_out;
207	207	UINT8 m_coin_out_state;
208	208	int m_sda_dir;
	209	DECLARE_WRITE8_MEMBER(peplus_bgcolor_w);
	210	DECLARE_WRITE8_MEMBER(peplus_crtc_display_w);
	211	DECLARE_WRITE8_MEMBER(peplus_io_w);
	212	DECLARE_WRITE8_MEMBER(peplus_duart_w);
	213	DECLARE_WRITE8_MEMBER(peplus_cmos_w);
	214	DECLARE_WRITE8_MEMBER(peplus_s3000_w);
	215	DECLARE_WRITE8_MEMBER(peplus_s5000_w);
	216	DECLARE_WRITE8_MEMBER(peplus_s7000_w);
	217	DECLARE_WRITE8_MEMBER(peplus_sb000_w);
	218	DECLARE_WRITE8_MEMBER(peplus_sd000_w);
	219	DECLARE_WRITE8_MEMBER(peplus_sf000_w);
	220	DECLARE_WRITE8_MEMBER(peplus_output_bank_a_w);
	221	DECLARE_WRITE8_MEMBER(peplus_output_bank_b_w);
	222	DECLARE_WRITE8_MEMBER(peplus_output_bank_c_w);
	223	DECLARE_READ8_MEMBER(peplus_io_r);
	224	DECLARE_READ8_MEMBER(peplus_duart_r);
	225	DECLARE_READ8_MEMBER(peplus_cmos_r);
	226	DECLARE_READ8_MEMBER(peplus_s3000_r);
	227	DECLARE_READ8_MEMBER(peplus_s5000_r);
	228	DECLARE_READ8_MEMBER(peplus_s7000_r);
	229	DECLARE_READ8_MEMBER(peplus_sb000_r);
	230	DECLARE_READ8_MEMBER(peplus_sd000_r);
	231	DECLARE_READ8_MEMBER(peplus_sf000_r);
	232	DECLARE_READ8_MEMBER(peplus_bgcolor_r);
	233	DECLARE_READ8_MEMBER(peplus_dropdoor_r);
	234	DECLARE_READ8_MEMBER(peplus_watchdog_r);
209	235	};
210	236
211	237
r14845	r14846
265	291	* Write Handlers *
266	292	******************/
267	293
268		static WRITE8_HANDLER( peplus_bgcolor_w )
	294	WRITE8_MEMBER(peplus_state::peplus_bgcolor_w)
269	295	{
270	296	int i;
271	297
272		for (i = 0; i < space->machine().total_colors(); i++)
	298	for (i = 0; i < machine().total_colors(); i++)
273	299	{
274	300	int bit0, bit1, bit2, r, g, b;
275	301
r14845	r14846
291	317	bit2 = 0;
292	318	b = 0x21 * bit2 + 0x47 * bit1 + 0x97 * bit0;
293	319
294		palette_set_color(space->machine(), (15 + (i*16)), MAKE_RGB(r, g, b));
	320	palette_set_color(machine(), (15 + (i*16)), MAKE_RGB(r, g, b));
295	321	}
296	322	}
297	323
r14845	r14846
333	359	handle_lightpen(device);
334	360	}
335	361
336		static WRITE8_HANDLER( peplus_crtc_display_w )
	362	WRITE8_MEMBER(peplus_state::peplus_crtc_display_w)
337	363	{
338		peplus_state *state = space->machine().driver_data<peplus_state>();
339		UINT8 *videoram = state->m_videoram;
340		videoram[state->m_vid_address] = data;
341		state->m_palette_ram[state->m_vid_address] = state->m_io_port[1];
342		state->m_palette_ram2[state->m_vid_address] = state->m_io_port[3];
	364	UINT8 *videoram = m_videoram;
	365	videoram[m_vid_address] = data;
	366	m_palette_ram[m_vid_address] = m_io_port[1];
	367	m_palette_ram2[m_vid_address] = m_io_port[3];
343	368
344		state->m_bg_tilemap->mark_tile_dirty(state->m_vid_address);
	369	m_bg_tilemap->mark_tile_dirty(m_vid_address);
345	370
346	371	/* An access here triggers a device read !*/
347		space->machine().device<mc6845_device>("crtc")->register_r(*space, 0);
	372	machine().device<mc6845_device>("crtc")->register_r(*&space, 0);
348	373	}
349	374
350		static WRITE8_HANDLER( peplus_io_w )
	375	WRITE8_MEMBER(peplus_state::peplus_io_w)
351	376	{
352		peplus_state *state = space->machine().driver_data<peplus_state>();
353		state->m_io_port[offset] = data;
	377	m_io_port[offset] = data;
354	378	}
355	379
356		static WRITE8_HANDLER( peplus_duart_w )
	380	WRITE8_MEMBER(peplus_state::peplus_duart_w)
357	381	{
358	382	// Used for Slot Accounting System Communication
359	383	}
360	384
361		static WRITE8_HANDLER( peplus_cmos_w )
	385	WRITE8_MEMBER(peplus_state::peplus_cmos_w)
362	386	{
363		peplus_state *state = space->machine().driver_data<peplus_state>();
364	387	char bank_name[6];
365	388
366	389	/* Test for Wingboard PAL Trigger Condition */
367		if (offset == 0x1fff && state->m_wingboard && data < 5)
	390	if (offset == 0x1fff && m_wingboard && data < 5)
368	391	{
369	392	sprintf(bank_name, "user%d", data + 1);
370		peplus_load_superdata(space->machine(), bank_name);
	393	peplus_load_superdata(machine(), bank_name);
371	394	}
372	395
373		state->m_cmos_ram[offset] = data;
	396	m_cmos_ram[offset] = data;
374	397	}
375	398
376		static WRITE8_HANDLER( peplus_s3000_w )
	399	WRITE8_MEMBER(peplus_state::peplus_s3000_w)
377	400	{
378		peplus_state *state = space->machine().driver_data<peplus_state>();
379		state->m_s3000_ram[offset] = data;
	401	m_s3000_ram[offset] = data;
380	402	}
381	403
382		static WRITE8_HANDLER( peplus_s5000_w )
	404	WRITE8_MEMBER(peplus_state::peplus_s5000_w)
383	405	{
384		peplus_state *state = space->machine().driver_data<peplus_state>();
385		state->m_s5000_ram[offset] = data;
	406	m_s5000_ram[offset] = data;
386	407	}
387	408
388		static WRITE8_HANDLER( peplus_s7000_w )
	409	WRITE8_MEMBER(peplus_state::peplus_s7000_w)
389	410	{
390		peplus_state *state = space->machine().driver_data<peplus_state>();
391		state->m_s7000_ram[offset] = data;
	411	m_s7000_ram[offset] = data;
392	412	}
393	413
394		static WRITE8_HANDLER( peplus_sb000_w )
	414	WRITE8_MEMBER(peplus_state::peplus_sb000_w)
395	415	{
396		peplus_state *state = space->machine().driver_data<peplus_state>();
397		state->m_sb000_ram[offset] = data;
	416	m_sb000_ram[offset] = data;
398	417	}
399	418
400		static WRITE8_HANDLER( peplus_sd000_w )
	419	WRITE8_MEMBER(peplus_state::peplus_sd000_w)
401	420	{
402		peplus_state *state = space->machine().driver_data<peplus_state>();
403		state->m_sd000_ram[offset] = data;
	421	m_sd000_ram[offset] = data;
404	422	}
405	423
406		static WRITE8_HANDLER( peplus_sf000_w )
	424	WRITE8_MEMBER(peplus_state::peplus_sf000_w)
407	425	{
408		peplus_state *state = space->machine().driver_data<peplus_state>();
409		state->m_sf000_ram[offset] = data;
	426	m_sf000_ram[offset] = data;
410	427	}
411	428
412		static WRITE8_HANDLER( peplus_output_bank_a_w )
	429	WRITE8_MEMBER(peplus_state::peplus_output_bank_a_w)
413	430	{
414		peplus_state *state = space->machine().driver_data<peplus_state>();
415	431	output_set_value("pe_bnka0",(data >> 0) & 1); /* Coin Lockout */
416	432	output_set_value("pe_bnka1",(data >> 1) & 1); /* Diverter */
417	433	output_set_value("pe_bnka2",(data >> 2) & 1); /* Bell */
r14845	r14846
421	437	output_set_value("pe_bnka6",(data >> 6) & 1); /* specific to a kind of machine */
422	438	output_set_value("pe_bnka7",(data >> 7) & 1); /* specific to a kind of machine */
423	439
424		state->m_coin_out_state = 0;
	440	m_coin_out_state = 0;
425	441	if(((data >> 4) & 1) || ((data >> 5) & 1))
426		state->m_coin_out_state = 3;
	442	m_coin_out_state = 3;
427	443	}
428	444
429		static WRITE8_HANDLER( peplus_output_bank_b_w )
	445	WRITE8_MEMBER(peplus_state::peplus_output_bank_b_w)
430	446	{
431	447	output_set_value("pe_bnkb0",(data >> 0) & 1); /* specific to a kind of machine */
432	448	output_set_value("pe_bnkb1",(data >> 1) & 1); /* Deal Spin Start */
r14845	r14846
438	454	output_set_value("pe_bnkb7",(data >> 7) & 1); /* specific to a kind of machine */
439	455	}
440	456
441		static WRITE8_HANDLER( peplus_output_bank_c_w )
	457	WRITE8_MEMBER(peplus_state::peplus_output_bank_c_w)
442	458	{
443	459	output_set_value("pe_bnkc0",(data >> 0) & 1); /* Coin In Meter */
444	460	output_set_value("pe_bnkc1",(data >> 1) & 1); /* Coin Out Meter */
r14845	r14846
463	479	* Read Handlers *
464	480	****************/
465	481
466		static READ8_HANDLER( peplus_io_r )
	482	READ8_MEMBER(peplus_state::peplus_io_r)
467	483	{
468		peplus_state *state = space->machine().driver_data<peplus_state>();
469		return state->m_io_port[offset];
	484	return m_io_port[offset];
470	485	}
471	486
472		static READ8_HANDLER( peplus_duart_r )
	487	READ8_MEMBER(peplus_state::peplus_duart_r)
473	488	{
474	489	// Used for Slot Accounting System Communication
475	490	return 0x00;
476	491	}
477	492
478		static READ8_HANDLER( peplus_cmos_r )
	493	READ8_MEMBER(peplus_state::peplus_cmos_r)
479	494	{
480		peplus_state *state = space->machine().driver_data<peplus_state>();
481		return state->m_cmos_ram[offset];
	495	return m_cmos_ram[offset];
482	496	}
483	497
484		static READ8_HANDLER( peplus_s3000_r )
	498	READ8_MEMBER(peplus_state::peplus_s3000_r)
485	499	{
486		peplus_state *state = space->machine().driver_data<peplus_state>();
487		return state->m_s3000_ram[offset];
	500	return m_s3000_ram[offset];
488	501	}
489	502
490		static READ8_HANDLER( peplus_s5000_r )
	503	READ8_MEMBER(peplus_state::peplus_s5000_r)
491	504	{
492		peplus_state *state = space->machine().driver_data<peplus_state>();
493		return state->m_s5000_ram[offset];
	505	return m_s5000_ram[offset];
494	506	}
495	507
496		static READ8_HANDLER( peplus_s7000_r )
	508	READ8_MEMBER(peplus_state::peplus_s7000_r)
497	509	{
498		peplus_state *state = space->machine().driver_data<peplus_state>();
499		return state->m_s7000_ram[offset];
	510	return m_s7000_ram[offset];
500	511	}
501	512
502		static READ8_HANDLER( peplus_sb000_r )
	513	READ8_MEMBER(peplus_state::peplus_sb000_r)
503	514	{
504		peplus_state *state = space->machine().driver_data<peplus_state>();
505		return state->m_sb000_ram[offset];
	515	return m_sb000_ram[offset];
506	516	}
507	517
508		static READ8_HANDLER( peplus_sd000_r )
	518	READ8_MEMBER(peplus_state::peplus_sd000_r)
509	519	{
510		peplus_state *state = space->machine().driver_data<peplus_state>();
511		return state->m_sd000_ram[offset];
	520	return m_sd000_ram[offset];
512	521	}
513	522
514		static READ8_HANDLER( peplus_sf000_r )
	523	READ8_MEMBER(peplus_state::peplus_sf000_r)
515	524	{
516		peplus_state *state = space->machine().driver_data<peplus_state>();
517		return state->m_sf000_ram[offset];
	525	return m_sf000_ram[offset];
518	526	}
519	527
520	528	/* Last Color in Every Palette is bgcolor */
521		static READ8_HANDLER( peplus_bgcolor_r )
	529	READ8_MEMBER(peplus_state::peplus_bgcolor_r)
522	530	{
523		return palette_get_color(space->machine(), 15); // Return bgcolor from First Palette
	531	return palette_get_color(machine(), 15); // Return bgcolor from First Palette
524	532	}
525	533
526		static READ8_HANDLER( peplus_dropdoor_r )
	534	READ8_MEMBER(peplus_state::peplus_dropdoor_r)
527	535	{
528	536	return 0x00; // Drop Door 0x00=Closed 0x02=Open
529	537	}
530	538
531		static READ8_HANDLER( peplus_watchdog_r )
	539	READ8_MEMBER(peplus_state::peplus_watchdog_r)
532	540	{
533	541	return 0x00; // Watchdog
534	542	}
r14845	r14846
736	744
737	745	static ADDRESS_MAP_START( peplus_iomap, AS_IO, 8, peplus_state )
738	746	// Battery-backed RAM (0x1000-0x01fff Extended RAM for Superboards Only)
739		AM_RANGE(0x0000, 0x1fff) AM_READWRITE_LEGACY(peplus_cmos_r, peplus_cmos_w) AM_SHARE("cmos")
	747	AM_RANGE(0x0000, 0x1fff) AM_READWRITE(peplus_cmos_r, peplus_cmos_w) AM_SHARE("cmos")
740	748
741	749	// CRT Controller
742	750	AM_RANGE(0x2008, 0x2008) AM_DEVWRITE_LEGACY("crtc", peplus_crtc_mode_w)
743	751	AM_RANGE(0x2080, 0x2080) AM_DEVREADWRITE("crtc", mc6845_device, status_r, address_w)
744	752	AM_RANGE(0x2081, 0x2081) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
745		AM_RANGE(0x2083, 0x2083) AM_DEVREAD("crtc", mc6845_device, register_r) AM_WRITE_LEGACY(peplus_crtc_display_w)
	753	AM_RANGE(0x2083, 0x2083) AM_DEVREAD("crtc", mc6845_device, register_r) AM_WRITE(peplus_crtc_display_w)
746	754
747	755	// Superboard Data
748		AM_RANGE(0x3000, 0x3fff) AM_READWRITE_LEGACY(peplus_s3000_r, peplus_s3000_w) AM_BASE(m_s3000_ram)
	756	AM_RANGE(0x3000, 0x3fff) AM_READWRITE(peplus_s3000_r, peplus_s3000_w) AM_BASE(m_s3000_ram)
749	757
750	758	// Sound and Dipswitches
751	759	AM_RANGE(0x4000, 0x4000) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
752	760	AM_RANGE(0x4004, 0x4004) AM_READ_PORT("SW1")/* likely ay8910 input port, not direct */ AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
753	761
754	762	// Superboard Data
755		AM_RANGE(0x5000, 0x5fff) AM_READWRITE_LEGACY(peplus_s5000_r, peplus_s5000_w) AM_BASE(m_s5000_ram)
	763	AM_RANGE(0x5000, 0x5fff) AM_READWRITE(peplus_s5000_r, peplus_s5000_w) AM_BASE(m_s5000_ram)
756	764
757	765	// Background Color Latch
758		AM_RANGE(0x6000, 0x6000) AM_READ_LEGACY(peplus_bgcolor_r) AM_WRITE_LEGACY(peplus_bgcolor_w)
	766	AM_RANGE(0x6000, 0x6000) AM_READ(peplus_bgcolor_r) AM_WRITE(peplus_bgcolor_w)
759	767
760	768	// Bogus Location for Video RAM
761	769	AM_RANGE(0x06001, 0x06400) AM_RAM AM_BASE(m_videoram)
762	770
763	771	// Superboard Data
764		AM_RANGE(0x7000, 0x7fff) AM_READWRITE_LEGACY(peplus_s7000_r, peplus_s7000_w) AM_BASE(m_s7000_ram)
	772	AM_RANGE(0x7000, 0x7fff) AM_READWRITE(peplus_s7000_r, peplus_s7000_w) AM_BASE(m_s7000_ram)
765	773
766	774	// Input Bank A, Output Bank C
767		AM_RANGE(0x8000, 0x8000) AM_DEVREAD_LEGACY("i2cmem",peplus_input_bank_a_r) AM_WRITE_LEGACY(peplus_output_bank_c_w)
	775	AM_RANGE(0x8000, 0x8000) AM_DEVREAD_LEGACY("i2cmem",peplus_input_bank_a_r) AM_WRITE(peplus_output_bank_c_w)
768	776
769	777	// Drop Door, I2C EEPROM Writes
770		AM_RANGE(0x9000, 0x9000) AM_READ_LEGACY(peplus_dropdoor_r) AM_DEVWRITE_LEGACY("i2cmem",i2c_nvram_w)
	778	AM_RANGE(0x9000, 0x9000) AM_READ(peplus_dropdoor_r) AM_DEVWRITE_LEGACY("i2cmem",i2c_nvram_w)
771	779
772	780	// Input Banks B & C, Output Bank B
773		AM_RANGE(0xa000, 0xa000) AM_READ_PORT("IN0") AM_WRITE_LEGACY(peplus_output_bank_b_w)
	781	AM_RANGE(0xa000, 0xa000) AM_READ_PORT("IN0") AM_WRITE(peplus_output_bank_b_w)
774	782
775	783	// Superboard Data
776		AM_RANGE(0xb000, 0xbfff) AM_READWRITE_LEGACY(peplus_sb000_r, peplus_sb000_w) AM_BASE(m_sb000_ram)
	784	AM_RANGE(0xb000, 0xbfff) AM_READWRITE(peplus_sb000_r, peplus_sb000_w) AM_BASE(m_sb000_ram)
777	785
778	786	// Output Bank A
779		AM_RANGE(0xc000, 0xc000) AM_READ_LEGACY(peplus_watchdog_r) AM_WRITE_LEGACY(peplus_output_bank_a_w)
	787	AM_RANGE(0xc000, 0xc000) AM_READ(peplus_watchdog_r) AM_WRITE(peplus_output_bank_a_w)
780	788
781	789	// Superboard Data
782		AM_RANGE(0xd000, 0xdfff) AM_READWRITE_LEGACY(peplus_sd000_r, peplus_sd000_w) AM_BASE(m_sd000_ram)
	790	AM_RANGE(0xd000, 0xdfff) AM_READWRITE(peplus_sd000_r, peplus_sd000_w) AM_BASE(m_sd000_ram)
783	791
784	792	// DUART
785		AM_RANGE(0xe000, 0xe00f) AM_READWRITE_LEGACY(peplus_duart_r, peplus_duart_w)
	793	AM_RANGE(0xe000, 0xe00f) AM_READWRITE(peplus_duart_r, peplus_duart_w)
786	794
787	795	// Superboard Data
788		AM_RANGE(0xf000, 0xffff) AM_READWRITE_LEGACY(peplus_sf000_r, peplus_sf000_w) AM_BASE(m_sf000_ram)
	796	AM_RANGE(0xf000, 0xffff) AM_READWRITE(peplus_sf000_r, peplus_sf000_w) AM_BASE(m_sf000_ram)
789	797
790	798	/* Ports start here */
791		AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READ_LEGACY(peplus_io_r) AM_WRITE_LEGACY(peplus_io_w) AM_BASE(m_io_port)
	799	AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READ(peplus_io_r) AM_WRITE(peplus_io_w) AM_BASE(m_io_port)
792	800	ADDRESS_MAP_END
793	801
794	802

src/mame/drivers/ddayjlc.c

r14845	r14846
82	82
83	83	/* devices */
84	84	device_t *m_audiocpu;
	85	DECLARE_WRITE8_MEMBER(prot_w);
	86	DECLARE_WRITE8_MEMBER(char_bank_w);
	87	DECLARE_WRITE8_MEMBER(ddayjlc_bgram_w);
	88	DECLARE_WRITE8_MEMBER(ddayjlc_videoram_w);
	89	DECLARE_WRITE8_MEMBER(sound_nmi_w);
	90	DECLARE_WRITE8_MEMBER(main_nmi_w);
	91	DECLARE_WRITE8_MEMBER(bg0_w);
	92	DECLARE_WRITE8_MEMBER(bg1_w);
	93	DECLARE_WRITE8_MEMBER(bg2_w);
	94	DECLARE_WRITE8_MEMBER(sound_w);
	95	DECLARE_WRITE8_MEMBER(i8257_CH0_w);
	96	DECLARE_WRITE8_MEMBER(i8257_LMSR_w);
85	97	};
86	98
87	99
r14845	r14846
134	146	return prot_data[state->m_prot_addr];
135	147	}
136	148
137		static WRITE8_HANDLER( prot_w )
	149	WRITE8_MEMBER(ddayjlc_state::prot_w)
138	150	{
139		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
140		state->m_prot_addr = (state->m_prot_addr & (~(1 << offset))) | ((data & 1) << offset);
	151	m_prot_addr = (m_prot_addr & (~(1 << offset))) | ((data & 1) << offset);
141	152	}
142	153
143		static WRITE8_HANDLER( char_bank_w )
	154	WRITE8_MEMBER(ddayjlc_state::char_bank_w)
144	155	{
145		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
146		state->m_char_bank = data;
	156	m_char_bank = data;
147	157	}
148	158
149		static WRITE8_HANDLER( ddayjlc_bgram_w )
	159	WRITE8_MEMBER(ddayjlc_state::ddayjlc_bgram_w)
150	160	{
151		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
152	161
153	162	if (!offset)
154		state->m_bg_tilemap->set_scrollx(0, data + 8);
	163	m_bg_tilemap->set_scrollx(0, data + 8);
155	164
156		state->m_bgram[offset] = data;
157		state->m_bg_tilemap->mark_tile_dirty(offset & 0x3ff);
	165	m_bgram[offset] = data;
	166	m_bg_tilemap->mark_tile_dirty(offset & 0x3ff);
158	167	}
159	168
160		static WRITE8_HANDLER( ddayjlc_videoram_w )
	169	WRITE8_MEMBER(ddayjlc_state::ddayjlc_videoram_w)
161	170	{
162		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
163		state->m_videoram[offset] = data;
	171	m_videoram[offset] = data;
164	172	}
165	173
166	174
167		static WRITE8_HANDLER(sound_nmi_w)
	175	WRITE8_MEMBER(ddayjlc_state::sound_nmi_w)
168	176	{
169		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
170		state->m_sound_nmi_enable = data;
	177	m_sound_nmi_enable = data;
171	178	}
172	179
173		static WRITE8_HANDLER(main_nmi_w)
	180	WRITE8_MEMBER(ddayjlc_state::main_nmi_w)
174	181	{
175		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
176		state->m_main_nmi_enable = data;
	182	m_main_nmi_enable = data;
177	183	}
178	184
179		static WRITE8_HANDLER( bg0_w )
	185	WRITE8_MEMBER(ddayjlc_state::bg0_w)
180	186	{
181		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
182		state->m_bgadr = (state->m_bgadr & 0xfe) | (data & 1);
	187	m_bgadr = (m_bgadr & 0xfe) | (data & 1);
183	188	}
184	189
185		static WRITE8_HANDLER( bg1_w )
	190	WRITE8_MEMBER(ddayjlc_state::bg1_w)
186	191	{
187		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
188		state->m_bgadr = (state->m_bgadr & 0xfd) | ((data & 1) << 1);
	192	m_bgadr = (m_bgadr & 0xfd) | ((data & 1) << 1);
189	193	}
190	194
191		static WRITE8_HANDLER( bg2_w )
	195	WRITE8_MEMBER(ddayjlc_state::bg2_w)
192	196	{
193		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
194	197
195		state->m_bgadr = (state->m_bgadr & 0xfb) | ((data & 1) << 2);
196		if (state->m_bgadr > 2)
197		state->m_bgadr = 0;
	198	m_bgadr = (m_bgadr & 0xfb) | ((data & 1) << 2);
	199	if (m_bgadr > 2)
	200	m_bgadr = 0;
198	201
199		memory_set_bank(space->machine(), "bank1", state->m_bgadr);
	202	memory_set_bank(machine(), "bank1", m_bgadr);
200	203	}
201	204
202		static WRITE8_HANDLER( sound_w )
	205	WRITE8_MEMBER(ddayjlc_state::sound_w)
203	206	{
204		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
205	207
206	208	soundlatch_w(space, offset, data);
207		device_set_input_line_and_vector(state->m_audiocpu, 0, HOLD_LINE, 0xff);
	209	device_set_input_line_and_vector(m_audiocpu, 0, HOLD_LINE, 0xff);
208	210	}
209	211
210		static WRITE8_HANDLER( i8257_CH0_w )
	212	WRITE8_MEMBER(ddayjlc_state::i8257_CH0_w)
211	213	{
212		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
213	214
214		state->m_e00x_d[offset][state->m_e00x_l[offset]] = data;
215		state->m_e00x_l[offset] ^= 1;
	215	m_e00x_d[offset][m_e00x_l[offset]] = data;
	216	m_e00x_l[offset] ^= 1;
216	217	}
217	218
218		static WRITE8_HANDLER( i8257_LMSR_w )
	219	WRITE8_MEMBER(ddayjlc_state::i8257_LMSR_w)
219	220	{
220		ddayjlc_state *state = space->machine().driver_data<ddayjlc_state>();
221	221
222	222	if (!data)
223	223	{
224		INT32 src = state->m_e00x_d[0][1] * 256 + state->m_e00x_d[0][0];
225		INT32 dst = state->m_e00x_d[2][1] * 256 + state->m_e00x_d[2][0];
226		INT32 size = (state->m_e00x_d[1][1] * 256 + state->m_e00x_d[1][0]) & 0x3ff;
	224	INT32 src = m_e00x_d[0][1] * 256 + m_e00x_d[0][0];
	225	INT32 dst = m_e00x_d[2][1] * 256 + m_e00x_d[2][0];
	226	INT32 size = (m_e00x_d[1][1] * 256 + m_e00x_d[1][0]) & 0x3ff;
227	227	INT32 i;
228	228
229	229	size++; //??
230	230
231	231	for(i = 0; i < size; i++)
232	232	{
233		space->write_byte(dst++, space->read_byte(src++));
	233	space.write_byte(dst++, space.read_byte(src++));
234	234	}
235	235
236		state->m_e00x_l[0] = 0;
237		state->m_e00x_l[1] = 0;
238		state->m_e00x_l[2] = 0;
239		state->m_e00x_l[3] = 0;
	236	m_e00x_l[0] = 0;
	237	m_e00x_l[1] = 0;
	238	m_e00x_l[2] = 0;
	239	m_e00x_l[3] = 0;
240	240	}
241	241	}
242	242
r14845	r14846
244	244	AM_RANGE(0x0000, 0x7fff) AM_ROM
245	245	AM_RANGE(0x8000, 0x8fff) AM_RAM AM_BASE(m_mainram)
246	246	AM_RANGE(0x9000, 0x93ff) AM_RAM AM_BASE(m_spriteram)
247		AM_RANGE(0x9400, 0x97ff) AM_RAM_WRITE_LEGACY(ddayjlc_videoram_w) AM_BASE(m_videoram)
248		AM_RANGE(0x9800, 0x9fff) AM_RAM_WRITE_LEGACY(ddayjlc_bgram_w) AM_BASE(m_bgram) /* 9800-981f - videoregs */
	247	AM_RANGE(0x9400, 0x97ff) AM_RAM_WRITE(ddayjlc_videoram_w) AM_BASE(m_videoram)
	248	AM_RANGE(0x9800, 0x9fff) AM_RAM_WRITE(ddayjlc_bgram_w) AM_BASE(m_bgram) /* 9800-981f - videoregs */
249	249	AM_RANGE(0xa000, 0xdfff) AM_ROMBANK("bank1") AM_WRITENOP
250		AM_RANGE(0xe000, 0xe003) AM_WRITE_LEGACY(i8257_CH0_w)
	250	AM_RANGE(0xe000, 0xe003) AM_WRITE(i8257_CH0_w)
251	251	AM_RANGE(0xe008, 0xe008) AM_WRITENOP
252		AM_RANGE(0xf000, 0xf000) AM_WRITE_LEGACY(sound_w)
	252	AM_RANGE(0xf000, 0xf000) AM_WRITE(sound_w)
253	253	AM_RANGE(0xf100, 0xf100) AM_WRITENOP
254		AM_RANGE(0xf080, 0xf080) AM_WRITE_LEGACY(char_bank_w)
	254	AM_RANGE(0xf080, 0xf080) AM_WRITE(char_bank_w)
255	255	AM_RANGE(0xf081, 0xf081) AM_WRITENOP
256		AM_RANGE(0xf083, 0xf083) AM_WRITE_LEGACY(i8257_LMSR_w)
257		AM_RANGE(0xf084, 0xf084) AM_WRITE_LEGACY(bg0_w)
258		AM_RANGE(0xf085, 0xf085) AM_WRITE_LEGACY(bg1_w)
259		AM_RANGE(0xf086, 0xf086) AM_WRITE_LEGACY(bg2_w)
260		AM_RANGE(0xf101, 0xf101) AM_WRITE_LEGACY(main_nmi_w)
261		AM_RANGE(0xf102, 0xf105) AM_WRITE_LEGACY(prot_w)
	256	AM_RANGE(0xf083, 0xf083) AM_WRITE(i8257_LMSR_w)
	257	AM_RANGE(0xf084, 0xf084) AM_WRITE(bg0_w)
	258	AM_RANGE(0xf085, 0xf085) AM_WRITE(bg1_w)
	259	AM_RANGE(0xf086, 0xf086) AM_WRITE(bg2_w)
	260	AM_RANGE(0xf101, 0xf101) AM_WRITE(main_nmi_w)
	261	AM_RANGE(0xf102, 0xf105) AM_WRITE(prot_w)
262	262	AM_RANGE(0xf000, 0xf000) AM_READ_PORT("INPUTS")
263	263	AM_RANGE(0xf100, 0xf100) AM_READ_PORT("SYSTEM")
264	264	AM_RANGE(0xf180, 0xf180) AM_READ_PORT("DSW1")
r14845	r14846
273	273	AM_RANGE(0x4000, 0x4000) AM_DEVWRITE_LEGACY("ay1", ay8910_address_w)
274	274	AM_RANGE(0x5000, 0x5000) AM_DEVREADWRITE_LEGACY("ay2", ay8910_r, ay8910_data_w)
275	275	AM_RANGE(0x6000, 0x6000) AM_DEVWRITE_LEGACY("ay2", ay8910_address_w)
276		AM_RANGE(0x7000, 0x7000) AM_WRITE_LEGACY(sound_nmi_w)
	276	AM_RANGE(0x7000, 0x7000) AM_WRITE(sound_nmi_w)
277	277	ADDRESS_MAP_END
278	278
279	279	static INPUT_PORTS_START( ddayjlc )

src/mame/drivers/dorachan.c

r14845	r14846
30	30
31	31	/* devices */
32	32	device_t *m_main_cpu;
	33	DECLARE_WRITE8_MEMBER(dorachan_ctrl_w);
33	34	};
34	35
35	36
r14845	r14846
120	121	}
121	122
122	123
123		static WRITE8_HANDLER(dorachan_ctrl_w)
	124	WRITE8_MEMBER(dorachan_state::dorachan_ctrl_w)
124	125	{
125		dorachan_state *state = space->machine().driver_data<dorachan_state>();
126		state->m_flip_screen = (data >> 6) & 0x01;
	126	m_flip_screen = (data >> 6) & 0x01;
127	127	}
128	128
129	129
r14845	r14846
167	167	ADDRESS_MAP_GLOBAL_MASK(0xff)
168	168	AM_RANGE(0x01, 0x01) AM_WRITENOP
169	169	AM_RANGE(0x02, 0x02) AM_WRITENOP
170		AM_RANGE(0x03, 0x03) AM_WRITE_LEGACY(dorachan_ctrl_w)
	170	AM_RANGE(0x03, 0x03) AM_WRITE(dorachan_ctrl_w)
171	171	ADDRESS_MAP_END
172	172
173	173

src/mame/drivers/quantum.c

r14845	r14846
57	57	quantum_state(const machine_config &mconfig, device_type type, const char *tag)
58	58	: driver_device(mconfig, type, tag) { }
59	59
	60	DECLARE_READ16_MEMBER(trackball_r);
	61	DECLARE_WRITE16_MEMBER(led_w);
60	62	};
61	63
62	64
r14845	r14846
70	72	*
71	73	*************************************/
72	74
73		static READ16_HANDLER( trackball_r )
	75	READ16_MEMBER(quantum_state::trackball_r)
74	76	{
75		return (input_port_read(space->machine(), "TRACKY") << 4) | input_port_read(space->machine(), "TRACKX");
	77	return (input_port_read(machine(), "TRACKY") << 4) | input_port_read(machine(), "TRACKX");
76	78	}
77	79
78	80
r14845	r14846
95	97	*
96	98	*************************************/
97	99
98		static WRITE16_HANDLER( led_w )
	100	WRITE16_MEMBER(quantum_state::led_w)
99	101	{
100	102	if (ACCESSING_BITS_0_7)
101	103	{
102	104	/* bits 0 and 1 are coin counters */
103		coin_counter_w(space->machine(), 0, data & 2);
104		coin_counter_w(space->machine(), 1, data & 1);
	105	coin_counter_w(machine(), 0, data & 2);
	106	coin_counter_w(machine(), 1, data & 1);
105	107
106	108	/* bit 3 = select second trackball for cocktail mode? */
107	109
108	110	/* bits 4 and 5 are LED controls */
109		set_led_status(space->machine(), 0, data & 0x10);
110		set_led_status(space->machine(), 1, data & 0x20);
	111	set_led_status(machine(), 0, data & 0x10);
	112	set_led_status(machine(), 1, data & 0x20);
111	113
112	114	/* bits 6 and 7 flip screen */
113	115	avg_set_flip_x (data & 0x40);
r14845	r14846
130	132	AM_RANGE(0x840000, 0x84001f) AM_DEVREADWRITE8_LEGACY("pokey1", pokey_r, pokey_w, 0x00ff)
131	133	AM_RANGE(0x840020, 0x84003f) AM_DEVREADWRITE8_LEGACY("pokey2", pokey_r, pokey_w, 0x00ff)
132	134	AM_RANGE(0x900000, 0x9001ff) AM_RAM AM_SHARE("nvram")
133		AM_RANGE(0x940000, 0x940001) AM_READ_LEGACY(trackball_r) /* trackball */
	135	AM_RANGE(0x940000, 0x940001) AM_READ(trackball_r) /* trackball */
134	136	AM_RANGE(0x948000, 0x948001) AM_READ_PORT("SYSTEM")
135	137	AM_RANGE(0x950000, 0x95001f) AM_WRITEONLY AM_BASE_LEGACY((UINT16**)&avgdvg_colorram)
136		AM_RANGE(0x958000, 0x958001) AM_WRITE_LEGACY(led_w)
	138	AM_RANGE(0x958000, 0x958001) AM_WRITE(led_w)
137	139	AM_RANGE(0x960000, 0x960001) AM_WRITENOP
138	140	AM_RANGE(0x968000, 0x968001) AM_WRITE_LEGACY(avgdvg_reset_word_w)
139	141	AM_RANGE(0x970000, 0x970001) AM_WRITE_LEGACY(avgdvg_go_word_w)

src/mame/drivers/quizpun2.c

r14845	r14846
99	99	UINT8 *m_fg_ram;
100	100	tilemap_t *m_bg_tmap;
101	101	tilemap_t *m_fg_tmap;
	102	DECLARE_WRITE8_MEMBER(bg_ram_w);
	103	DECLARE_WRITE8_MEMBER(fg_ram_w);
	104	DECLARE_READ8_MEMBER(quizpun2_protection_r);
	105	DECLARE_WRITE8_MEMBER(quizpun2_protection_w);
	106	DECLARE_WRITE8_MEMBER(quizpun2_rombank_w);
	107	DECLARE_WRITE8_MEMBER(quizpun2_irq_ack);
	108	DECLARE_WRITE8_MEMBER(quizpun2_soundlatch_w);
102	109	};
103	110
104	111
r14845	r14846
123	130	SET_TILE_INFO(1, code, color & 0x0f, 0);
124	131	}
125	132
126		static WRITE8_HANDLER( bg_ram_w )
	133	WRITE8_MEMBER(quizpun2_state::bg_ram_w)
127	134	{
128		quizpun2_state *state = space->machine().driver_data<quizpun2_state>();
129		state->m_bg_ram[offset] = data;
130		state->m_bg_tmap->mark_tile_dirty(offset/2);
	135	m_bg_ram[offset] = data;
	136	m_bg_tmap->mark_tile_dirty(offset/2);
131	137	}
132	138
133		static WRITE8_HANDLER( fg_ram_w )
	139	WRITE8_MEMBER(quizpun2_state::fg_ram_w)
134	140	{
135		quizpun2_state *state = space->machine().driver_data<quizpun2_state>();
136		state->m_fg_ram[offset] = data;
137		state->m_fg_tmap->mark_tile_dirty(offset/4);
	141	m_fg_ram[offset] = data;
	142	m_fg_tmap->mark_tile_dirty(offset/4);
138	143	}
139	144
140	145	static VIDEO_START(quizpun2)
r14845	r14846
206	211	);
207	212	}
208	213
209		static READ8_HANDLER( quizpun2_protection_r )
	214	READ8_MEMBER(quizpun2_state::quizpun2_protection_r)
210	215	{
211		quizpun2_state *state = space->machine().driver_data<quizpun2_state>();
212		struct prot_t &prot = state->m_prot;
	216	struct prot_t &prot = m_prot;
213	217	UINT8 ret;
214	218
215	219	switch ( prot.state )
r14845	r14846
236	240	break;
237	241
238	242	default:
239		log_protection(space, "unknown address");
	243	log_protection(&space, "unknown address");
240	244	ret = 0x2e59 >> ((prot.addr & 1) ? 0 : 8);   // return the address of: XOR A, RET
241	245	}
242	246	break;
243	247
244	248	case STATE_EEPROM_R:      // EEPROM read
245	249	{
246		UINT8 *eeprom = space->machine().region("eeprom")->base();
	250	UINT8 *eeprom = machine().region("eeprom")->base();
247	251	ret = eeprom[prot.addr];
248	252	break;
249	253	}
250	254
251	255	default:
252		log_protection(space, "unknown read");
	256	log_protection(&space, "unknown read");
253	257	ret = 0x00;
254	258	}
255	259
256	260	#if VERBOSE_PROTECTION_LOG
257		log_protection(space, "info READ");
	261	log_protection(&space, "info READ");
258	262	#endif
259	263
260	264	prot.addr++;
r14845	r14846
262	266	return ret;
263	267	}
264	268
265		static WRITE8_HANDLER( quizpun2_protection_w )
	269	WRITE8_MEMBER(quizpun2_state::quizpun2_protection_w)
266	270	{
267		quizpun2_state *state = space->machine().driver_data<quizpun2_state>();
268		struct prot_t &prot = state->m_prot;
	271	struct prot_t &prot = m_prot;
269	272
270	273	switch ( prot.state )
271	274	{
272	275	case STATE_EEPROM_W:
273	276	{
274		UINT8 *eeprom = space->machine().region("eeprom")->base();
	277	UINT8 *eeprom = machine().region("eeprom")->base();
275	278	eeprom[prot.addr] = data;
276	279	prot.addr++;
277	280	if ((prot.addr % 8) == 0)
r14845	r14846
300	303	prot.addr = 0;
301	304	}
302	305	else
303		log_protection(space, "unknown command");
	306	log_protection(&space, "unknown command");
304	307	}
305	308	else if (prot.cmd >= 0x00 && prot.cmd <= 0x0f )
306	309	{
r14845	r14846
315	318	else
316	319	{
317	320	prot.state = STATE_IDLE;
318		log_protection(space, "unknown command");
	321	log_protection(&space, "unknown command");
319	322	}
320	323	}
321	324	else
r14845	r14846
327	330	}
328	331
329	332	#if VERBOSE_PROTECTION_LOG
330		log_protection(space, "info WRITE");
	333	log_protection(&space, "info WRITE");
331	334	#endif
332	335	}
333	336
r14845	r14846
336	339	Memory Maps - Main CPU
337	340	***************************************************************************/
338	341
339		static WRITE8_HANDLER( quizpun2_rombank_w )
	342	WRITE8_MEMBER(quizpun2_state::quizpun2_rombank_w)
340	343	{
341		UINT8 *ROM = space->machine().region("maincpu")->base();
342		memory_set_bankptr(space->machine(),  "bank1", &ROM[ 0x10000 + 0x2000 * (data & 0x1f) ] );
	344	UINT8 *ROM = machine().region("maincpu")->base();
	345	memory_set_bankptr(machine(),  "bank1", &ROM[ 0x10000 + 0x2000 * (data & 0x1f) ] );
343	346	}
344	347
345		static WRITE8_HANDLER( quizpun2_irq_ack )
	348	WRITE8_MEMBER(quizpun2_state::quizpun2_irq_ack)
346	349	{
347		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
	350	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
348	351	}
349	352
350		static WRITE8_HANDLER( quizpun2_soundlatch_w )
	353	WRITE8_MEMBER(quizpun2_state::quizpun2_soundlatch_w)
351	354	{
352	355	soundlatch_w(space, 0, data);
353		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_NMI, PULSE_LINE);
	356	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_NMI, PULSE_LINE);
354	357	}
355	358
356	359	static ADDRESS_MAP_START( quizpun2_map, AS_PROGRAM, 8, quizpun2_state )
357	360	AM_RANGE( 0x0000, 0x7fff ) AM_ROM
358	361	AM_RANGE( 0x8000, 0x9fff ) AM_ROMBANK("bank1")
359	362
360		AM_RANGE( 0xa000, 0xbfff ) AM_RAM_WRITE_LEGACY(fg_ram_w ) AM_BASE(m_fg_ram )   // 4 * 800
361		AM_RANGE( 0xc000, 0xc7ff ) AM_RAM_WRITE_LEGACY(bg_ram_w ) AM_BASE(m_bg_ram )   // 4 * 400
	363	AM_RANGE( 0xa000, 0xbfff ) AM_RAM_WRITE(fg_ram_w ) AM_BASE(m_fg_ram )   // 4 * 800
	364	AM_RANGE( 0xc000, 0xc7ff ) AM_RAM_WRITE(bg_ram_w ) AM_BASE(m_bg_ram )   // 4 * 400
362	365	AM_RANGE( 0xc800, 0xcfff ) AM_RAM                              //
363	366
364	367	AM_RANGE( 0xd000, 0xd3ff ) AM_RAM_WRITE_LEGACY(paletteram_xRRRRRGGGGGBBBBB_le_w )  AM_BASE_GENERIC( paletteram )
r14845	r14846
367	370
368	371	static ADDRESS_MAP_START( quizpun2_io_map, AS_IO, 8, quizpun2_state )
369	372	ADDRESS_MAP_GLOBAL_MASK(0xff)
370		AM_RANGE( 0x40, 0x40 ) AM_WRITE_LEGACY(quizpun2_irq_ack )
371		AM_RANGE( 0x50, 0x50 ) AM_WRITE_LEGACY(quizpun2_soundlatch_w )
372		AM_RANGE( 0x60, 0x60 ) AM_WRITE_LEGACY(quizpun2_rombank_w )
	373	AM_RANGE( 0x40, 0x40 ) AM_WRITE(quizpun2_irq_ack )
	374	AM_RANGE( 0x50, 0x50 ) AM_WRITE(quizpun2_soundlatch_w )
	375	AM_RANGE( 0x60, 0x60 ) AM_WRITE(quizpun2_rombank_w )
373	376	AM_RANGE( 0x80, 0x80 ) AM_READ_PORT( "DSW" )
374	377	AM_RANGE( 0x90, 0x90 ) AM_READ_PORT( "IN0" )
375	378	AM_RANGE( 0xa0, 0xa0 ) AM_READ_PORT( "IN1" )
376		AM_RANGE( 0xe0, 0xe0 ) AM_READWRITE_LEGACY(quizpun2_protection_r, quizpun2_protection_w )
	379	AM_RANGE( 0xe0, 0xe0 ) AM_READWRITE(quizpun2_protection_r, quizpun2_protection_w )
377	380	ADDRESS_MAP_END
378	381
379	382

src/mame/drivers/egghunt.c

r14845	r14846
66	66	UINT8 *   m_atram;
67	67	UINT8     m_bgram[0x1000];
68	68	UINT8     m_spram[0x1000];
	69	DECLARE_READ8_MEMBER(egghunt_bgram_r);
	70	DECLARE_WRITE8_MEMBER(egghunt_bgram_w);
	71	DECLARE_WRITE8_MEMBER(egghunt_atram_w);
	72	DECLARE_WRITE8_MEMBER(egghunt_gfx_banking_w);
	73	DECLARE_WRITE8_MEMBER(egghunt_vidram_bank_w);
	74	DECLARE_WRITE8_MEMBER(egghunt_soundlatch_w);
69	75	};
70	76
71	77
r14845	r14846
127	133	SET_TILE_INFO(0, code, colour, 0);
128	134	}
129	135
130		static READ8_HANDLER( egghunt_bgram_r )
	136	READ8_MEMBER(egghunt_state::egghunt_bgram_r)
131	137	{
132		egghunt_state *state = space->machine().driver_data<egghunt_state>();
133		if (state->m_vidram_bank)
	138	if (m_vidram_bank)
134	139	{
135		return state->m_spram[offset];
	140	return m_spram[offset];
136	141	}
137	142	else
138	143	{
139		return state->m_bgram[offset];
	144	return m_bgram[offset];
140	145	}
141	146	}
142	147
143		static WRITE8_HANDLER( egghunt_bgram_w )
	148	WRITE8_MEMBER(egghunt_state::egghunt_bgram_w)
144	149	{
145		egghunt_state *state = space->machine().driver_data<egghunt_state>();
146		if (state->m_vidram_bank)
	150	if (m_vidram_bank)
147	151	{
148		state->m_spram[offset] = data;
	152	m_spram[offset] = data;
149	153	}
150	154	else
151	155	{
152		state->m_bgram[offset] = data;
153		state->m_bg_tilemap->mark_tile_dirty(offset / 2);
	156	m_bgram[offset] = data;
	157	m_bg_tilemap->mark_tile_dirty(offset / 2);
154	158	}
155	159	}
156	160
157		static WRITE8_HANDLER( egghunt_atram_w )
	161	WRITE8_MEMBER(egghunt_state::egghunt_atram_w)
158	162	{
159		egghunt_state *state = space->machine().driver_data<egghunt_state>();
160		state->m_atram[offset] = data;
161		state->m_bg_tilemap->mark_tile_dirty(offset);
	163	m_atram[offset] = data;
	164	m_bg_tilemap->mark_tile_dirty(offset);
162	165	}
163	166
164	167
r14845	r14846
180	183	return 0;
181	184	}
182	185
183		static WRITE8_HANDLER( egghunt_gfx_banking_w )
	186	WRITE8_MEMBER(egghunt_state::egghunt_gfx_banking_w)
184	187	{
185		egghunt_state *state = space->machine().driver_data<egghunt_state>();
186	188	// data & 0x03 is used for tile banking
187	189	// data & 0x30 is used for sprites banking
188		state->m_gfx_banking = data & 0x33;
	190	m_gfx_banking = data & 0x33;
189	191
190		state->m_bg_tilemap->mark_all_dirty();
	192	m_bg_tilemap->mark_all_dirty();
191	193	}
192	194
193		static WRITE8_HANDLER( egghunt_vidram_bank_w )
	195	WRITE8_MEMBER(egghunt_state::egghunt_vidram_bank_w)
194	196	{
195		egghunt_state *state = space->machine().driver_data<egghunt_state>();
196		state->m_vidram_bank = data & 1;
	197	m_vidram_bank = data & 1;
197	198	}
198	199
199		static WRITE8_HANDLER( egghunt_soundlatch_w )
	200	WRITE8_MEMBER(egghunt_state::egghunt_soundlatch_w)
200	201	{
201		egghunt_state *state = space->machine().driver_data<egghunt_state>();
202	202	soundlatch_w(space, 0, data);
203		device_set_input_line(state->m_audiocpu, 0, HOLD_LINE);
	203	device_set_input_line(m_audiocpu, 0, HOLD_LINE);
204	204	}
205	205
206	206	static READ8_DEVICE_HANDLER( egghunt_okibanking_r )
r14845	r14846
220	220	static ADDRESS_MAP_START( egghunt_map, AS_PROGRAM, 8, egghunt_state )
221	221	AM_RANGE(0x0000, 0x7fff) AM_ROM
222	222	AM_RANGE(0xc000, 0xc7ff) AM_RAM_WRITE_LEGACY(paletteram_xRRRRRGGGGGBBBBB_le_w) AM_BASE_GENERIC(paletteram)
223		AM_RANGE(0xc800, 0xcfff) AM_RAM_WRITE_LEGACY(egghunt_atram_w) AM_BASE(m_atram)
224		AM_RANGE(0xd000, 0xdfff) AM_READWRITE_LEGACY(egghunt_bgram_r, egghunt_bgram_w)
	223	AM_RANGE(0xc800, 0xcfff) AM_RAM_WRITE(egghunt_atram_w) AM_BASE(m_atram)
	224	AM_RANGE(0xd000, 0xdfff) AM_READWRITE(egghunt_bgram_r, egghunt_bgram_w)
225	225	AM_RANGE(0xe000, 0xffff) AM_RAM
226	226	ADDRESS_MAP_END
227	227
228	228
229	229	static ADDRESS_MAP_START( io_map, AS_IO, 8, egghunt_state )
230	230	ADDRESS_MAP_GLOBAL_MASK(0xff)
231		AM_RANGE(0x00, 0x00) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(egghunt_vidram_bank_w)
232		AM_RANGE(0x01, 0x01) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(egghunt_gfx_banking_w)
	231	AM_RANGE(0x00, 0x00) AM_READ_PORT("DSW1") AM_WRITE(egghunt_vidram_bank_w)
	232	AM_RANGE(0x01, 0x01) AM_READ_PORT("SYSTEM") AM_WRITE(egghunt_gfx_banking_w)
233	233	AM_RANGE(0x02, 0x02) AM_READ_PORT("P1")
234		AM_RANGE(0x03, 0x03) AM_READ_PORT("P2") AM_WRITE_LEGACY(egghunt_soundlatch_w)
	234	AM_RANGE(0x03, 0x03) AM_READ_PORT("P2") AM_WRITE(egghunt_soundlatch_w)
235	235	AM_RANGE(0x04, 0x04) AM_READ_PORT("DSW2")
236	236	AM_RANGE(0x06, 0x06) AM_READ_PORT("UNK") AM_WRITENOP
237	237	AM_RANGE(0x07, 0x07) AM_WRITENOP

src/mame/drivers/splus.c

r14845	r14846
84	84	INT16 m_stepper_pos[5];
85	85	UINT8 m_stop_pos[5];
86	86
	87	DECLARE_WRITE8_MEMBER(splus_io_w);
	88	DECLARE_WRITE8_MEMBER(splus_load_pulse_w);
	89	DECLARE_WRITE8_MEMBER(splus_serial_w);
	90	DECLARE_WRITE8_MEMBER(splus_7seg_w);
	91	DECLARE_WRITE8_MEMBER(splus_duart_w);
	92	DECLARE_READ8_MEMBER(splus_serial_r);
	93	DECLARE_READ8_MEMBER(splus_m_reel_ram_r);
	94	DECLARE_READ8_MEMBER(splus_io_r);
	95	DECLARE_READ8_MEMBER(splus_duart_r);
	96	DECLARE_READ8_MEMBER(splus_watchdog_r);
	97	DECLARE_READ8_MEMBER(splus_registers_r);
87	98	};
88	99
89	100	/* Static Variables */
r14845	r14846
120	131	* Write Handlers *
121	132	******************/
122	133
123		static WRITE8_HANDLER( splus_io_w )
	134	WRITE8_MEMBER(splus_state::splus_io_w)
124	135	{
125		splus_state *state = space->machine().driver_data<splus_state>();
126	136
127	137	// P1.0 = Reel 1 Controller
128	138	// P1.1 = Reel 2 Controller
r14845	r14846
138	148	if (offset == 1 && ((data & 0x1f) != 0x00)) {
139	149
140	150	// Unknown Bit 7
141		state->m_p1_unknown = (~data & 0x80);
	151	m_p1_unknown = (~data & 0x80);
142	152
143	153	// Stepper Motor Engaged
144		if (((state->m_bank40 >> 0) & 1) == 0x01) {
	154	if (((m_bank40 >> 0) & 1) == 0x01) {
145	155	// Reel Controllers Only
146		state->m_p1_reels = (data & 0x1f);
	156	m_p1_reels = (data & 0x1f);
147	157
148	158	// Loop through Reel Controllers
149	159	for (x = 0; x < 5; x++) {
150	160	// Test Reel Controller
151		if (((state->m_p1_reels >> x) & 1) == 0x01) {
	161	if (((m_p1_reels >> x) & 1) == 0x01) {
152	162	// Forward Direction
153		if (((state->m_bank10 >> 5) & 1) == 0x01) {
154		state->m_stepper_pos[x]++;
155		if (state->m_stepper_pos[x] == MAX_STEPPER)
156		state->m_stepper_pos[x] = 0;
	163	if (((m_bank10 >> 5) & 1) == 0x01) {
	164	m_stepper_pos[x]++;
	165	if (m_stepper_pos[x] == MAX_STEPPER)
	166	m_stepper_pos[x] = 0;
157	167	} else {
158		state->m_stepper_pos[x]--;
159		if (state->m_stepper_pos[x] < 0)
160		state->m_stepper_pos[x] = MAX_STEPPER - 1;
	168	m_stepper_pos[x]--;
	169	if (m_stepper_pos[x] < 0)
	170	m_stepper_pos[x] = MAX_STEPPER - 1;
161	171	}
162		state->m_stop_pos[x] = (int)(state->m_stepper_pos[x] / STEPPER_DIVISOR);
	172	m_stop_pos[x] = (int)(m_stepper_pos[x] / STEPPER_DIVISOR);
163	173	}
164	174	}
165	175	}
166	176	#if DEBUG_OUTPUT
167	177	if ((data & 0x1f) == 0x01)
168		mame_printf_info("Steppers %02X-%02X-%02X-%02X-%02X Motor=%02X Dir=%02X reels=%02X unk=%02X\n", state->m_stop_pos[0],state->m_stop_pos[1],state->m_stop_pos[2],state->m_stop_pos[3],state->m_stop_pos[4],((state->m_bank40 >> 0) & 1),((state->m_bank10 >> 5) & 1),(data & 0x1f), state->m_p1_unknown);
	178	mame_printf_info("Steppers %02X-%02X-%02X-%02X-%02X Motor=%02X Dir=%02X reels=%02X unk=%02X\n", m_stop_pos[0],m_stop_pos[1],m_stop_pos[2],m_stop_pos[3],m_stop_pos[4],((m_bank40 >> 0) & 1),((m_bank10 >> 5) & 1),(data & 0x1f), m_p1_unknown);
169	179	#endif
170	180	}
171	181
172		state->m_io_port[offset] = data;
	182	m_io_port[offset] = data;
173	183	}
174	184
175		static WRITE8_HANDLER( splus_load_pulse_w )
	185	WRITE8_MEMBER(splus_state::splus_load_pulse_w)
176	186	{
177		//  splus_state *state = space->machine().driver_data<splus_state>();
178	187
179	188	//  UINT8 out = 0;
180		//    out = ((~state->m_io_port[1] & 0xf0)>>4); // Output Bank
	189	//    out = ((~m_io_port[1] & 0xf0)>>4); // Output Bank
181	190	}
182	191
183		static WRITE8_HANDLER( splus_serial_w )
	192	WRITE8_MEMBER(splus_state::splus_serial_w)
184	193	{
185		splus_state *state = space->machine().driver_data<splus_state>();
186	194
187	195	UINT8 out = 0;
188		out = ((~state->m_io_port[1] & 0xe0)>>5); // Output Bank
	196	out = ((~m_io_port[1] & 0xe0)>>5); // Output Bank
189	197
190	198	switch (out)
191	199	{
192	200	case 0x00: // Bank 10
193		if (((state->m_bank10 >> 0) & 1) != ((data >> 0) & 1)) {
	201	if (((m_bank10 >> 0) & 1) != ((data >> 0) & 1)) {
194	202	#if DEBUG_OUTPUT
195	203	mame_printf_info("Coin Drop Meter =%02X\n",(data >> 0) & 1);
196	204	#endif
197	205	}
198		if (((state->m_bank10 >> 1) & 1) != ((data >> 1) & 1)) {
	206	if (((m_bank10 >> 1) & 1) != ((data >> 1) & 1)) {
199	207	#if DEBUG_OUTPUT
200	208	mame_printf_info("Coin Out Meter =%02X\n",(data >> 1) & 1);
201	209	#endif
202	210	}
203		if (((state->m_bank10 >> 2) & 1) != ((data >> 2) & 1)) {
	211	if (((m_bank10 >> 2) & 1) != ((data >> 2) & 1)) {
204	212	#if DEBUG_OUTPUT
205	213	mame_printf_info("Coin In Meter =%02X\n",(data >> 2) & 1);
206	214	#endif
207	215	}
208		if (((state->m_bank10 >> 3) & 1) != ((data >> 3) & 1)) {
	216	if (((m_bank10 >> 3) & 1) != ((data >> 3) & 1)) {
209	217	//mame_printf_info("B Switch for SDS =%02X\n",(data >> 3) & 1);
210	218	}
211		if (((state->m_bank10 >> 4) & 1) != ((data >> 4) & 1)) {
	219	if (((m_bank10 >> 4) & 1) != ((data >> 4) & 1)) {
212	220	#if DEBUG_OUTPUT
213	221	mame_printf_info("Hopper Drive 2 =%02X\n",(data >> 4) & 1);
214	222	#endif
215	223	}
216		if (((state->m_bank10 >> 5) & 1) != ((data >> 5) & 1)) {
	224	if (((m_bank10 >> 5) & 1) != ((data >> 5) & 1)) {
217	225	#if DEBUG_OUTPUT
218	226	mame_printf_info("Stepper Motor Direction =%02X\n",(data >> 5) & 1);
219	227	#endif
220	228	}
221		if (((state->m_bank10 >> 6) & 1) != ((data >> 6) & 1)) {
	229	if (((m_bank10 >> 6) & 1) != ((data >> 6) & 1)) {
222	230	#if DEBUG_OUTPUT
223	231	mame_printf_info("Mechanical Bell =%02X\n",(data >> 6) & 1);
224	232	#endif
225	233	}
226		if (((state->m_bank10 >> 7) & 1) != ((data >> 7) & 1)) {
	234	if (((m_bank10 >> 7) & 1) != ((data >> 7) & 1)) {
227	235	#if DEBUG_OUTPUT
228	236	mame_printf_info("Cancelled Credits Meter =%02X\n",(data >> 7) & 1);
229	237	#endif
230	238	}
231		state->m_bank10 = data;
	239	m_bank10 = data;
232	240
233	241	output_set_value("s_bnk10",(data >> 0) & 1); // Coin Drop Meter
234	242	output_set_value("s_bnk11",(data >> 1) & 1); // Coin Out Meter
r14845	r14846
240	248	output_set_value("s_bnk17",(data >> 7) & 1); // Cancelled Credits Meter
241	249	break;
242	250	case 0x01: // Bank 20
243		if (((state->m_bank20 >> 5) & 1) != ((data >> 5) & 1)) {
	251	if (((m_bank20 >> 5) & 1) != ((data >> 5) & 1)) {
244	252	#if DEBUG_OUTPUT
245	253	mame_printf_info("Games Played Meter =%02X\n",(data >> 5) & 1);
246	254	#endif
247	255	}
248		if (((state->m_bank20 >> 6) & 1) != ((data >> 6) & 1)) {
	256	if (((m_bank20 >> 6) & 1) != ((data >> 6) & 1)) {
249	257	#if DEBUG_OUTPUT
250	258	mame_printf_info("Bill Acceptor Enable =%02X\n",(data >> 6) & 1);
251	259	#endif
252	260	}
253		if (((state->m_bank20 >> 7) & 1) != ((data >> 7) & 1)) {
	261	if (((m_bank20 >> 7) & 1) != ((data >> 7) & 1)) {
254	262	#if DEBUG_OUTPUT
255	263	mame_printf_info("Jackpots Meter =%02X\n",(data >> 7) & 1);
256	264	#endif
257	265	}
258		state->m_bank20 = data;
	266	m_bank20 = data;
259	267
260	268	output_set_value("s_bnk20",(data >> 0) & 1); // Payline Lamp 3
261	269	output_set_value("s_bnk21",(data >> 1) & 1); // Payline Lamp 4
r14845	r14846
267	275	output_set_value("s_bnk27",(data >> 7) & 1); // Jackpots Meter
268	276	break;
269	277	case 0x02: // Bank 30
270		if (((state->m_bank30 >> 2) & 1) != ((data >> 2) & 1)) {
	278	if (((m_bank30 >> 2) & 1) != ((data >> 2) & 1)) {
271	279	#if DEBUG_OUTPUT
272	280	mame_printf_info("Handle Release =%02X\n",(data >> 2) & 1);
273	281	#endif
274	282	}
275		if (((state->m_bank30 >> 3) & 1) != ((data >> 3) & 1)) {
	283	if (((m_bank30 >> 3) & 1) != ((data >> 3) & 1)) {
276	284	#if DEBUG_OUTPUT
277	285	mame_printf_info("Diverter =%02X\n",(data >> 3) & 1);
278	286	#endif
279	287	}
280		if (((state->m_bank30 >> 4) & 1) != ((data >> 4) & 1)) {
	288	if (((m_bank30 >> 4) & 1) != ((data >> 4) & 1)) {
281	289	#if DEBUG_OUTPUT
282	290	mame_printf_info("Coin Lockout =%02X\n",(data >> 4) & 1);
283	291	#endif
284	292	}
285		if (((state->m_bank30 >> 5) & 1) != ((data >> 5) & 1)) {
	293	if (((m_bank30 >> 5) & 1) != ((data >> 5) & 1)) {
286	294	#if DEBUG_OUTPUT
287	295	mame_printf_info("Hopper Drive 1 =%02X\n",(data >> 5) & 1);
288	296	#endif
289	297	}
290		state->m_bank30 = data;
	298	m_bank30 = data;
291	299
292	300	output_set_value("s_bnk30",(data >> 0) & 1); // Change Candle Lamp Bottom
293	301	output_set_value("s_bnk31",(data >> 1) & 1); // Change Candle Lamp Top
r14845	r14846
299	307	output_set_value("s_bnk37",(data >> 7) & 1); // Payline Lamp 2
300	308	break;
301	309	case 0x04: // Bank 40
302		if (((state->m_bank40 >> 0) & 1) != ((data >> 0) & 1)) {
	310	if (((m_bank40 >> 0) & 1) != ((data >> 0) & 1)) {
303	311	#if DEBUG_OUTPUT
304	312	mame_printf_info("Stepper Motor Power Supply =%02X\n",(data >> 0) & 1);
305	313	#endif
306	314	}
307		if (((state->m_bank40 >> 3) & 1) != ((data >> 3) & 1)) {
	315	if (((m_bank40 >> 3) & 1) != ((data >> 3) & 1)) {
308	316	#if DEBUG_OUTPUT
309	317	mame_printf_info("Jackpot/Hand Pay Lamp =%02X\n",(data >> 3) & 1);
310	318	#endif
311	319	}
312		state->m_bank40 = data;
	320	m_bank40 = data;
313	321
314	322	output_set_value("s_bnk40",(data >> 0) & 1); // Stepper Motor Power Supply
315	323	output_set_value("s_bnk41",(data >> 1) & 1); // Insert Coin Lamp
r14845	r14846
323	331	}
324	332	}
325	333
326		static WRITE8_HANDLER( splus_7seg_w )
	334	WRITE8_MEMBER(splus_state::splus_7seg_w)
327	335	{
328		splus_state *state = space->machine().driver_data<splus_state>();
329	336
330	337	static const UINT8 ls48_map[16] = { 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7c,0x07,0x7f,0x67,0x58,0x4c,0x62,0x69,0x78,0x00 };
331	338
r14845	r14846
335	342	seg = ((~data & 0xf0)>>4); // Segment Number
336	343	val = (~data & 0x0f); // Digit Value
337	344
338		// Need to add ~state->m_io_port[1]-1 to seg value
339		if (seg < 0x0a && (state->m_io_port[1] & 0xe0) == 0xe0)
	345	// Need to add ~m_io_port[1]-1 to seg value
	346	if (seg < 0x0a && (m_io_port[1] & 0xe0) == 0xe0)
340	347	output_set_digit_value(seg, ls48_map[val]);
341	348	}
342	349
343		static WRITE8_HANDLER( splus_duart_w )
	350	WRITE8_MEMBER(splus_state::splus_duart_w)
344	351	{
345	352	// Used for Slot Accounting System Communication
346	353	}
r14845	r14846
357	364	* Read Handlers *
358	365	****************/
359	366
360		static READ8_HANDLER( splus_serial_r )
	367	READ8_MEMBER(splus_state::splus_serial_r)
361	368	{
362		splus_state *state = space->machine().driver_data<splus_state>();
363	369
364	370	UINT8 coin_out = 0x00;
365	371	UINT8 coin_optics = 0x00;
366	372	UINT8 door_optics = 0x00;
367		UINT32 curr_cycles = space->machine().firstcpu->total_cycles();
	373	UINT32 curr_cycles = machine().firstcpu->total_cycles();
368	374
369	375	UINT8 in = 0x00;
370	376	UINT8 val = 0x00;
371		in = ((~state->m_io_port[1] & 0xe0)>>5); // Input Bank
	377	in = ((~m_io_port[1] & 0xe0)>>5); // Input Bank
372	378
373	379	switch (in)
374	380	{
r14845	r14846
385	391	break;
386	392	case 0x01: // Bank 10
387	393	// Test for Coin-In
388		if ((input_port_read_safe(space->machine(),"SENSOR",0x00) & 0x01) == 0x01 && state->m_coin_state == 0) {
389		state->m_coin_state = 1; // Start Coin Cycle
390		state->m_last_cycles = space->machine().firstcpu->total_cycles();
	394	if ((input_port_read_safe(machine(),"SENSOR",0x00) & 0x01) == 0x01 && m_coin_state == 0) {
	395	m_coin_state = 1; // Start Coin Cycle
	396	m_last_cycles = machine().firstcpu->total_cycles();
391	397	#if DEBUG_OUTPUT
392		mame_printf_info("coin=%02X\n", state->m_coin_state);
	398	mame_printf_info("coin=%02X\n", m_coin_state);
393	399	#endif
394	400	} else {
395	401	/* Process Next Coin Optic State */
396		if (curr_cycles - state->m_last_cycles > 10000 && state->m_coin_state != 0) {
397		state->m_coin_state++;
398		if (state->m_coin_state > 5)
399		state->m_coin_state = 0;
400		state->m_last_cycles = space->machine().firstcpu->total_cycles();
	402	if (curr_cycles - m_last_cycles > 10000 && m_coin_state != 0) {
	403	m_coin_state++;
	404	if (m_coin_state > 5)
	405	m_coin_state = 0;
	406	m_last_cycles = machine().firstcpu->total_cycles();
401	407	#if DEBUG_OUTPUT
402		mame_printf_info("coin=%02X\n", state->m_coin_state);
	408	mame_printf_info("coin=%02X\n", m_coin_state);
403	409	#endif
404	410	}
405	411	}
406	412
407	413	// Set Coin State
408		switch (state->m_coin_state)
	414	switch (m_coin_state)
409	415	{
410	416	case 0x00: // No Coin
411	417	coin_optics = 0x00;
r14845	r14846
428	434	}
429	435
430	436	// Determine Door Optics
431		if ((input_port_read_safe(space->machine(),"I10",0x08) & 0x08) == 0x08)
	437	if ((input_port_read_safe(machine(),"I10",0x08) & 0x08) == 0x08)
432	438	door_optics = 0x08;
433	439	else
434		door_optics = (((state->m_bank20 >> 4) & 1) << 3); // Use Door Optics Transmitter
	440	door_optics = (((m_bank20 >> 4) & 1) << 3); // Use Door Optics Transmitter
435	441
436	442	// Test if Hopper 1 and Hopper 2 Motors On
437		if (((state->m_bank10 >> 4) & 1) || ((state->m_bank30 >> 5) & 1)) {
438		if (state->m_coin_out_state == 0)
439		state->m_coin_out_state = 3;
	443	if (((m_bank10 >> 4) & 1) || ((m_bank30 >> 5) & 1)) {
	444	if (m_coin_out_state == 0)
	445	m_coin_out_state = 3;
440	446	} else {
441		state->m_coin_out_state = 0;
	447	m_coin_out_state = 0;
442	448	}
443	449
444	450	// Process Coin Out
445		if (curr_cycles - state->m_last_coin_out > 700000 && state->m_coin_out_state != 0) {
446		if (state->m_coin_out_state != 2) {
447		state->m_coin_out_state = 2; // Coin-Out Off
	451	if (curr_cycles - m_last_coin_out > 700000 && m_coin_out_state != 0) {
	452	if (m_coin_out_state != 2) {
	453	m_coin_out_state = 2; // Coin-Out Off
448	454	} else {
449		state->m_coin_out_state = 3; // Coin-Out On
	455	m_coin_out_state = 3; // Coin-Out On
450	456	}
451	457
452		state->m_last_coin_out = space->machine().firstcpu->total_cycles();
	458	m_last_coin_out = machine().firstcpu->total_cycles();
453	459	}
454	460
455	461	// Set Coin Out State
456		switch (state->m_coin_out_state)
	462	switch (m_coin_out_state)
457	463	{
458	464	case 0x00: // No Coin-Out
459	465	coin_out = 0x00;
r14845	r14846
473	479	val = val | door_optics; // Door Optics Receiver
474	480	val = val | coin_out; // Hopper Coin OutR
475	481	val = val | 0x00; // Hopper Full
476		val = val | (input_port_read_safe(space->machine(),"I10",0x40) & 0x40); // Handle/Spin Button
477		val = val | (input_port_read_safe(space->machine(),"I10",0x80) & 0x80); // Jackpot Reset Key
	482	val = val | (input_port_read_safe(machine(),"I10",0x40) & 0x40); // Handle/Spin Button
	483	val = val | (input_port_read_safe(machine(),"I10",0x80) & 0x80); // Jackpot Reset Key
478	484	break;
479	485	case 0x02: // Bank 20
480		val = val | (input_port_read_safe(space->machine(),"I20",0x01) & 0x01); // Bet One Credit
481		val = val | (input_port_read_safe(space->machine(),"I20",0x02) & 0x02); // Play Max Credits
482		val = val | (input_port_read_safe(space->machine(),"I20",0x04) & 0x04); // Cash Out
483		val = val | (input_port_read_safe(space->machine(),"I20",0x08) & 0x08); // Change Request
	486	val = val | (input_port_read_safe(machine(),"I20",0x01) & 0x01); // Bet One Credit
	487	val = val | (input_port_read_safe(machine(),"I20",0x02) & 0x02); // Play Max Credits
	488	val = val | (input_port_read_safe(machine(),"I20",0x04) & 0x04); // Cash Out
	489	val = val | (input_port_read_safe(machine(),"I20",0x08) & 0x08); // Change Request
484	490	val = val | 0x00; // Reel Mechanism
485		val = val | (input_port_read_safe(space->machine(),"I20",0x20) & 0x20); // Self Test Button
	491	val = val | (input_port_read_safe(machine(),"I20",0x20) & 0x20); // Self Test Button
486	492	val = val | 0x40; // Card Cage
487	493	val = val | 0x80; // Bill Acceptor
488	494	break;
489	495	case 0x04: // Bank 30
490	496	// Reserved
491		val = val | (input_port_read_safe(space->machine(),"I30",0x02) & 0x02); // Drop Door
	497	val = val | (input_port_read_safe(machine(),"I30",0x02) & 0x02); // Drop Door
492	498	// Jackpot to Credit Key
493	499	// Reserved
494	500	// Reserved
r14845	r14846
500	506	return val;
501	507	}
502	508
503		static READ8_HANDLER( splus_m_reel_ram_r )
	509	READ8_MEMBER(splus_state::splus_m_reel_ram_r)
504	510	{
505		splus_state *state = space->machine().driver_data<splus_state>();
506		return state->m_reel_ram[offset];
	511	return m_reel_ram[offset];
507	512	}
508	513
509		static READ8_HANDLER( splus_io_r )
	514	READ8_MEMBER(splus_state::splus_io_r)
510	515	{
511		splus_state *state = space->machine().driver_data<splus_state>();
512	516
513	517	if (offset == 3)
514		return state->m_io_port[offset] & 0xf3; // Ignore Int0 and Int1, or machine will loop forever waiting
	518	return m_io_port[offset] & 0xf3; // Ignore Int0 and Int1, or machine will loop forever waiting
515	519	else
516		return state->m_io_port[offset];
	520	return m_io_port[offset];
517	521	}
518	522
519		static READ8_HANDLER( splus_duart_r )
	523	READ8_MEMBER(splus_state::splus_duart_r)
520	524	{
521	525	// Used for Slot Accounting System Communication
522	526	return 0x00;
523	527	}
524	528
525		static READ8_HANDLER( splus_watchdog_r )
	529	READ8_MEMBER(splus_state::splus_watchdog_r)
526	530	{
527	531	return 0x00; // Watchdog
528	532	}
529	533
530		static READ8_HANDLER( splus_registers_r )
	534	READ8_MEMBER(splus_state::splus_registers_r)
531	535	{
532	536	return 0xff; // Reset Registers in Real Time Clock
533	537	}
r14845	r14846
587	591
588	592	static ADDRESS_MAP_START( splus_iomap, AS_IO, 8, splus_state )
589	593	// Serial I/O
590		AM_RANGE(0x0000, 0x0000) AM_READ_LEGACY(splus_serial_r) AM_WRITE_LEGACY(splus_serial_w)
	594	AM_RANGE(0x0000, 0x0000) AM_READ(splus_serial_r) AM_WRITE(splus_serial_w)
591	595
592	596	// Battery-backed RAM (Lower 4K) 0x1500-0x16ff eeprom staging area
593	597	AM_RANGE(0x1000, 0x1fff) AM_RAM AM_SHARE("cmosl")
594	598
595	599	// Watchdog, 7-segment Display
596		AM_RANGE(0x2000, 0x2000) AM_READWRITE_LEGACY(splus_watchdog_r, splus_7seg_w)
	600	AM_RANGE(0x2000, 0x2000) AM_READWRITE(splus_watchdog_r, splus_7seg_w)
597	601
598	602	// DUART
599		AM_RANGE(0x3000, 0x300f) AM_READWRITE_LEGACY(splus_duart_r, splus_duart_w)
	603	AM_RANGE(0x3000, 0x300f) AM_READWRITE(splus_duart_r, splus_duart_w)
600	604
601	605	// Dip Switches, Sound
602	606	AM_RANGE(0x4000, 0x4000) AM_READ_PORT("SW1") AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
r14845	r14846
606	610	AM_RANGE(0x5000, 0x5000) AM_DEVREAD_LEGACY("i2cmem", splus_reel_optics_r) AM_DEVWRITE_LEGACY("i2cmem", i2c_nvram_w)
607	611
608	612	// Reset Registers in Realtime Clock, Serial I/O Load Pulse
609		AM_RANGE(0x6000, 0x6000) AM_READWRITE_LEGACY(splus_registers_r, splus_load_pulse_w)
	613	AM_RANGE(0x6000, 0x6000) AM_READWRITE(splus_registers_r, splus_load_pulse_w)
610	614
611	615	// Battery-backed RAM (Upper 4K)
612	616	AM_RANGE(0x7000, 0x7fff) AM_RAM AM_SHARE("cmosh")
613	617
614	618	// SSxxxx Reel Chip
615		AM_RANGE(0x8000, 0x9fff) AM_READ_LEGACY(splus_m_reel_ram_r) AM_BASE(m_reel_ram)
	619	AM_RANGE(0x8000, 0x9fff) AM_READ(splus_m_reel_ram_r) AM_BASE(m_reel_ram)
616	620
617	621	// Ports start here
618		AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READ_LEGACY(splus_io_r) AM_WRITE_LEGACY(splus_io_w) AM_BASE(m_io_port)
	622	AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READ(splus_io_r) AM_WRITE(splus_io_w) AM_BASE(m_io_port)
619	623	ADDRESS_MAP_END
620	624
621	625	/*************************

src/mame/drivers/gpworld.c

r14845	r14846
60	60	UINT8* m_sprite_RAM;
61	61	UINT8* m_palette_RAM;
62	62	required_device<pioneer_ldv1000_device> m_laserdisc;
	63	DECLARE_READ8_MEMBER(ldp_read);
	64	DECLARE_READ8_MEMBER(pedal_in);
	65	DECLARE_WRITE8_MEMBER(ldp_write);
	66	DECLARE_WRITE8_MEMBER(misc_io_write);
	67	DECLARE_WRITE8_MEMBER(brake_gas_write);
	68	DECLARE_WRITE8_MEMBER(palette_write);
63	69	};
64	70
65	71
r14845	r14846
230	236
231	237	/* MEMORY HANDLERS */
232	238	/* READS */
233		static READ8_HANDLER( ldp_read )
	239	READ8_MEMBER(gpworld_state::ldp_read)
234	240	{
235		gpworld_state *state = space->machine().driver_data<gpworld_state>();
236		return state->m_ldp_read_latch;
	241	return m_ldp_read_latch;
237	242	}
238	243
239		static READ8_HANDLER( pedal_in )
	244	READ8_MEMBER(gpworld_state::pedal_in)
240	245	{
241		gpworld_state *state = space->machine().driver_data<gpworld_state>();
242		if (state->m_brake_gas)
243		return   input_port_read(space->machine(), "INACCEL");
	246	if (m_brake_gas)
	247	return   input_port_read(machine(), "INACCEL");
244	248
245		return   input_port_read(space->machine(), "INBRAKE");
	249	return   input_port_read(machine(), "INBRAKE");
246	250
247	251	}
248	252
249	253	/* WRITES */
250		static WRITE8_HANDLER( ldp_write )
	254	WRITE8_MEMBER(gpworld_state::ldp_write)
251	255	{
252		gpworld_state *state = space->machine().driver_data<gpworld_state>();
253		state->m_ldp_write_latch = data;
	256	m_ldp_write_latch = data;
254	257	}
255	258
256		static WRITE8_HANDLER( misc_io_write )
	259	WRITE8_MEMBER(gpworld_state::misc_io_write)
257	260	{
258		gpworld_state *state = space->machine().driver_data<gpworld_state>();
259		state->m_start_lamp = (data & 0x04) >> 1;
260		state->m_nmi_enable = (data & 0x40) >> 6;
	261	m_start_lamp = (data & 0x04) >> 1;
	262	m_nmi_enable = (data & 0x40) >> 6;
261	263	/*  dunno      = (data & 0x80) >> 7; */ //coin counter???
262	264
263		logerror("NMI : %x (0x%x)\n", state->m_nmi_enable, data);
	265	logerror("NMI : %x (0x%x)\n", m_nmi_enable, data);
264	266	}
265	267
266		static WRITE8_HANDLER( brake_gas_write )
	268	WRITE8_MEMBER(gpworld_state::brake_gas_write)
267	269	{
268		gpworld_state *state = space->machine().driver_data<gpworld_state>();
269		state->m_brake_gas = data & 0x01;
	270	m_brake_gas = data & 0x01;
270	271	}
271	272
272		static WRITE8_HANDLER( palette_write )
	273	WRITE8_MEMBER(gpworld_state::palette_write)
273	274	{
274		gpworld_state *state = space->machine().driver_data<gpworld_state>();
275	275	/* This is all just a (bad) guess */
276	276	int pal_index, r, g, b, a;
277	277
278		state->m_palette_RAM[offset] = data;
	278	m_palette_RAM[offset] = data;
279	279
280	280	/* "Round down" to the nearest palette entry */
281	281	pal_index = offset & 0xffe;
282	282
283		g = (state->m_palette_RAM[pal_index]   & 0xf0) << 0;
284		b = (state->m_palette_RAM[pal_index]   & 0x0f) << 4;
285		r = (state->m_palette_RAM[pal_index+1] & 0x0f) << 4;
286		a = (state->m_palette_RAM[pal_index+1] & 0x80) ? 0 : 255;   /* guess */
	283	g = (m_palette_RAM[pal_index]   & 0xf0) << 0;
	284	b = (m_palette_RAM[pal_index]   & 0x0f) << 4;
	285	r = (m_palette_RAM[pal_index+1] & 0x0f) << 4;
	286	a = (m_palette_RAM[pal_index+1] & 0x80) ? 0 : 255;   /* guess */
287	287
288	288	/* logerror("PAL WRITE index : %x  rgb : %d %d %d (real %x) at %x\n", pal_index, r,g,b, data, offset); */
289	289
290		palette_set_color(space->machine(), (pal_index & 0xffe) >> 1, MAKE_ARGB(a, r, g, b));
	290	palette_set_color(machine(), (pal_index & 0xffe) >> 1, MAKE_ARGB(a, r, g, b));
291	291	}
292	292
293	293	/* PROGRAM MAP */
294	294	static ADDRESS_MAP_START( mainmem, AS_PROGRAM, 8, gpworld_state )
295	295	AM_RANGE(0x0000,0xbfff) AM_ROM
296	296	AM_RANGE(0xc000,0xc7ff) AM_RAM AM_BASE(m_sprite_RAM)
297		AM_RANGE(0xc800,0xcfff) AM_WRITE_LEGACY(palette_write) AM_BASE(m_palette_RAM)   /* The memory test reads at 0xc800 */
	297	AM_RANGE(0xc800,0xcfff) AM_WRITE(palette_write) AM_BASE(m_palette_RAM)   /* The memory test reads at 0xc800 */
298	298	AM_RANGE(0xd000,0xd7ff) AM_RAM AM_BASE(m_tile_RAM)
299		AM_RANGE(0xd800,0xd800) AM_READWRITE_LEGACY(ldp_read,ldp_write)
	299	AM_RANGE(0xd800,0xd800) AM_READWRITE(ldp_read,ldp_write)
300	300	/*  AM_RANGE(0xd801,0xd801) AM_READ_LEGACY(???) */
301	301	AM_RANGE(0xda00,0xda00) AM_READ_PORT("INWHEEL")   //8255 here....
302	302	/*  AM_RANGE(0xda01,0xda01) AM_WRITE_LEGACY(???) */               /* These inputs are interesting - there are writes and reads all over these addr's */
303		AM_RANGE(0xda02,0xda02) AM_WRITE_LEGACY(brake_gas_write)            /*bit 0 select gas/brake input */
304		AM_RANGE(0xda20,0xda20) AM_READ_LEGACY(pedal_in)
	303	AM_RANGE(0xda02,0xda02) AM_WRITE(brake_gas_write)            /*bit 0 select gas/brake input */
	304	AM_RANGE(0xda20,0xda20) AM_READ(pedal_in)
305	305
306	306	AM_RANGE(0xe000,0xffff) AM_RAM                        /* Potentially not all work RAM? */
307	307	ADDRESS_MAP_END
r14845	r14846
310	310	/* I/O MAP */
311	311	static ADDRESS_MAP_START( mainport, AS_IO, 8, gpworld_state )
312	312	ADDRESS_MAP_GLOBAL_MASK(0xff)
313		AM_RANGE(0x01,0x01) AM_WRITE_LEGACY(misc_io_write)
	313	AM_RANGE(0x01,0x01) AM_WRITE(misc_io_write)
314	314	AM_RANGE(0x80,0x80) AM_READ_PORT("IN0")
315	315	AM_RANGE(0x81,0x81) AM_READ_PORT("IN1")
316	316	AM_RANGE(0x82,0x82) AM_READ_PORT("DSW1")

src/mame/drivers/mw18w.c

r14845	r14846
25	25	mw18w_state(const machine_config &mconfig, device_type type, const char *tag)
26	26	: driver_device(mconfig, type, tag) { }
27	27
	28	DECLARE_WRITE8_MEMBER(mw18w_sound0_w);
	29	DECLARE_WRITE8_MEMBER(mw18w_sound1_w);
	30	DECLARE_WRITE8_MEMBER(mw18w_lamps_w);
	31	DECLARE_WRITE8_MEMBER(mw18w_led_display_w);
	32	DECLARE_WRITE8_MEMBER(mw18w_irq0_clear_w);
28	33	};
29	34
30	35
31		static WRITE8_HANDLER( mw18w_sound0_w )
	36	WRITE8_MEMBER(mw18w_state::mw18w_sound0_w)
32	37	{
33	38	// sound write (airhorn, brake, crash) plus motor speed for backdrop, and coin counter
34		coin_counter_w(space->machine(), 0, data&1);
	39	coin_counter_w(machine(), 0, data&1);
35	40	}
36	41
37		static WRITE8_HANDLER( mw18w_sound1_w )
	42	WRITE8_MEMBER(mw18w_state::mw18w_sound1_w)
38	43	{
39	44	// sound write (bell, engine) plus lamp dim control for backdrop lamp
40	45	;
41	46	}
42	47
43		static WRITE8_HANDLER( mw18w_lamps_w )
	48	WRITE8_MEMBER(mw18w_state::mw18w_lamps_w)
44	49	{
45	50	;
46	51	}
47	52
48		static WRITE8_HANDLER( mw18w_led_display_w )
	53	WRITE8_MEMBER(mw18w_state::mw18w_led_display_w)
49	54	{
50	55	// d0-3: 7448 (BCD to LED segment)
51	56	const UINT8 ls48_map[16] =
r14845	r14846
56	61	output_set_digit_value(data>>4, ls48_map[data&0xf]);
57	62	}
58	63
59		static WRITE8_HANDLER( mw18w_irq0_clear_w )
	64	WRITE8_MEMBER(mw18w_state::mw18w_irq0_clear_w)
60	65	{
61		cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
	66	cputag_set_input_line(machine(), "maincpu", 0, CLEAR_LINE);
62	67	}
63	68
64	69	static CUSTOM_INPUT( mw18w_sensors_r )
r14845	r14846
79	84	static ADDRESS_MAP_START( mw18w_portmap, AS_IO, 8, mw18w_state )
80	85	ADDRESS_MAP_UNMAP_HIGH
81	86	ADDRESS_MAP_GLOBAL_MASK(0xff)
82		AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0") AM_WRITE_LEGACY(mw18w_sound0_w)
83		AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1") AM_WRITE_LEGACY(mw18w_sound1_w)
84		AM_RANGE(0x02, 0x02) AM_READ_PORT("IN2") AM_WRITE_LEGACY(mw18w_lamps_w)
85		AM_RANGE(0x03, 0x03) AM_READ_PORT("DSW") AM_WRITE_LEGACY(mw18w_led_display_w)
	87	AM_RANGE(0x00, 0x00) AM_READ_PORT("IN0") AM_WRITE(mw18w_sound0_w)
	88	AM_RANGE(0x01, 0x01) AM_READ_PORT("IN1") AM_WRITE(mw18w_sound1_w)
	89	AM_RANGE(0x02, 0x02) AM_READ_PORT("IN2") AM_WRITE(mw18w_lamps_w)
	90	AM_RANGE(0x03, 0x03) AM_READ_PORT("DSW") AM_WRITE(mw18w_led_display_w)
86	91	AM_RANGE(0x04, 0x04) AM_READ_PORT("IN4")
87	92	AM_RANGE(0x06, 0x06) AM_WRITE_LEGACY(watchdog_reset_w)
88		AM_RANGE(0x07, 0x07) AM_WRITE_LEGACY(mw18w_irq0_clear_w)
	93	AM_RANGE(0x07, 0x07) AM_WRITE(mw18w_irq0_clear_w)
89	94	ADDRESS_MAP_END
90	95
91	96	static const UINT32 mw18w_controller_table[] =

src/mame/drivers/jokrwild.c

r14845	r14846
106	106	UINT8 *m_videoram;
107	107	UINT8 *m_colorram;
108	108	tilemap_t *m_bg_tilemap;
	109	DECLARE_WRITE8_MEMBER(jokrwild_videoram_w);
	110	DECLARE_WRITE8_MEMBER(jokrwild_colorram_w);
	111	DECLARE_READ8_MEMBER(rng_r);
109	112	};
110	113
111	114
r14845	r14846
114	117	*************************/
115	118
116	119
117		static WRITE8_HANDLER( jokrwild_videoram_w )
	120	WRITE8_MEMBER(jokrwild_state::jokrwild_videoram_w)
118	121	{
119		jokrwild_state *state = space->machine().driver_data<jokrwild_state>();
120		state->m_videoram[offset] = data;
121		state->m_bg_tilemap->mark_tile_dirty(offset);
	122	m_videoram[offset] = data;
	123	m_bg_tilemap->mark_tile_dirty(offset);
122	124	}
123	125
124	126
125		static WRITE8_HANDLER( jokrwild_colorram_w )
	127	WRITE8_MEMBER(jokrwild_state::jokrwild_colorram_w)
126	128	{
127		jokrwild_state *state = space->machine().driver_data<jokrwild_state>();
128		state->m_colorram[offset] = data;
129		state->m_bg_tilemap->mark_tile_dirty(offset);
	129	m_colorram[offset] = data;
	130	m_bg_tilemap->mark_tile_dirty(offset);
130	131	}
131	132
132	133
r14845	r14846
176	177	*    Read/Write  Handlers    *
177	178	*****************************/
178	179
179		static READ8_HANDLER( rng_r )
	180	READ8_MEMBER(jokrwild_state::rng_r)
180	181	{
181		if(cpu_get_pc(&space->device()) == 0xab32)
	182	if(cpu_get_pc(&space.device()) == 0xab32)
182	183	return (offset == 0) ? 0x9e : 0x27;
183	184
184		if(cpu_get_pc(&space->device()) == 0xab3a)
	185	if(cpu_get_pc(&space.device()) == 0xab3a)
185	186	return (offset == 2) ? 0x49 : 0x92;
186	187
187		return space->machine().rand() & 0xff;
	188	return machine().rand() & 0xff;
188	189	}
189	190
190	191	/*************************
r14845	r14846
192	193	*************************/
193	194
194	195	static ADDRESS_MAP_START( jokrwild_map, AS_PROGRAM, 8, jokrwild_state )
195		AM_RANGE(0x0000, 0x03ff) AM_RAM_WRITE_LEGACY(jokrwild_videoram_w) AM_BASE(m_videoram)
	196	AM_RANGE(0x0000, 0x03ff) AM_RAM_WRITE(jokrwild_videoram_w) AM_BASE(m_videoram)
196	197	AM_RANGE(0x0400, 0x07ff) AM_RAM //FIXME: backup RAM
197		AM_RANGE(0x2000, 0x23ff) AM_RAM_WRITE_LEGACY(jokrwild_colorram_w) AM_BASE(m_colorram)
	198	AM_RANGE(0x2000, 0x23ff) AM_RAM_WRITE(jokrwild_colorram_w) AM_BASE(m_colorram)
198	199	AM_RANGE(0x2400, 0x27ff) AM_RAM //stack RAM
199	200	AM_RANGE(0x4004, 0x4007) AM_DEVREADWRITE("pia0", pia6821_device, read, write)
200	201	AM_RANGE(0x4008, 0x400b) AM_DEVREADWRITE("pia1", pia6821_device, read, write) //optical sensor is here
r14845	r14846
202	203	AM_RANGE(0x6000, 0x6000) AM_DEVWRITE("crtc", mc6845_device, address_w)
203	204	AM_RANGE(0x6001, 0x6001) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
204	205	AM_RANGE(0x6100, 0x6100) AM_READ_PORT("SW1")
205		AM_RANGE(0x6200, 0x6203) AM_READ_LEGACY(rng_r)//another PIA?
	206	AM_RANGE(0x6200, 0x6203) AM_READ(rng_r)//another PIA?
206	207	AM_RANGE(0x6300, 0x6300) AM_READ_PORT("SW2")
207	208	AM_RANGE(0x8000, 0xffff) AM_ROM
208	209	ADDRESS_MAP_END

src/mame/drivers/ecoinf3.c

r14845	r14846
8	8	public:
9	9	ecoinf3_state(const machine_config &mconfig, device_type type, const char *tag)
10	10	: driver_device(mconfig, type, tag) { }
	11	DECLARE_WRITE8_MEMBER(py_port58_out_w);
11	12	};
12	13
13		static WRITE8_HANDLER( py_port58_out_w )
	14	WRITE8_MEMBER(ecoinf3_state::py_port58_out_w)
14	15	{
15	16	// Watchdog?
16	17	}
r14845	r14846
23	24	static ADDRESS_MAP_START( pyramid_portmap, AS_IO, 8, ecoinf3_state )
24	25	ADDRESS_MAP_GLOBAL_MASK(0xff)
25	26
26		AM_RANGE(0x58, 0x58) AM_WRITE_LEGACY(py_port58_out_w)
	27	AM_RANGE(0x58, 0x58) AM_WRITE(py_port58_out_w)
27	28	ADDRESS_MAP_END
28	29
29	30	/*

src/mame/drivers/imolagp.c

r14845	r14846
113	113	UINT8  m_videoram[3][0x4000];
114	114
115	115	required_device<cpu_device> m_maincpu;
	116	DECLARE_WRITE8_MEMBER(transmit_data_w);
	117	DECLARE_READ8_MEMBER(trigger_slave_nmi_r);
	118	DECLARE_READ8_MEMBER(receive_data_r);
	119	DECLARE_WRITE8_MEMBER(imola_ledram_w);
	120	DECLARE_READ8_MEMBER(steerlatch_r);
	121	DECLARE_WRITE8_MEMBER(screenram_w);
	122	DECLARE_READ8_MEMBER(imola_slave_port05r);
	123	DECLARE_READ8_MEMBER(imola_slave_port06r);
	124	DECLARE_READ8_MEMBER(imola_slave_port81r);
	125	DECLARE_READ8_MEMBER(imola_slave_port82r);
	126	DECLARE_WRITE8_MEMBER(vreg_control_w);
	127	DECLARE_WRITE8_MEMBER(vreg_data_w);
116	128	};
117	129
118	130
119	131	#ifdef HLE_COM
120	132
121		static WRITE8_HANDLER( transmit_data_w )
	133	WRITE8_MEMBER(imolagp_state::transmit_data_w)
122	134	{
123		imolagp_state *state = space->machine().driver_data<imolagp_state>();
124		state->m_mComData[state->m_mComCount++] = data;
	135	m_mComData[m_mComCount++] = data;
125	136	}
126	137
127		static READ8_HANDLER( trigger_slave_nmi_r )
	138	READ8_MEMBER(imolagp_state::trigger_slave_nmi_r)
128	139	{
129	140	return 0;
130	141	}
131	142
132		static READ8_HANDLER( receive_data_r )
	143	READ8_MEMBER(imolagp_state::receive_data_r)
133	144	{
134	145	return 0;
135	146	}
r14845	r14846
138	149	/* the master cpu transmits data to the slave CPU one word at a time using a rapid sequence of triggered NMIs
139	150	* the slave cpu pauses as it enters its irq, awaiting this burst of data
140	151	*/
141		static WRITE8_HANDLER( transmit_data_w )
	152	WRITE8_MEMBER(imolagp_state::transmit_data_w)
142	153	{
143		imolagp_state *state = space->machine().driver_data<imolagp_state>();
144		state->m_mLatchedData[offset] = data;
	154	m_mLatchedData[offset] = data;
145	155	}
146		static READ8_HANDLER( trigger_slave_nmi_r )
	156	READ8_MEMBER(imolagp_state::trigger_slave_nmi_r)
147	157	{
148		imolagp_state *state = space->machine().driver_data<imolagp_state>();
149		device_set_input_line(state->m_slave, INPUT_LINE_NMI, PULSE_LINE);
	158	device_set_input_line(m_slave, INPUT_LINE_NMI, PULSE_LINE);
150	159	return 0;
151	160	}
152	161
153		static READ8_HANDLER( receive_data_r )
	162	READ8_MEMBER(imolagp_state::receive_data_r)
154	163	{
155		imolagp_state *state = space->machine().driver_data<imolagp_state>();
156		return state->m_mLatchedData[offset];
	164	return m_mLatchedData[offset];
157	165	}
158	166	#endif
159	167
r14845	r14846
229	237	return 0;
230	238	}
231	239
232		static WRITE8_HANDLER( imola_ledram_w )
	240	WRITE8_MEMBER(imolagp_state::imola_ledram_w)
233	241	{
234	242	data &= 0xf;
235	243
r14845	r14846
276	284	}
277	285	}
278	286
279		static READ8_HANDLER( steerlatch_r )
	287	READ8_MEMBER(imolagp_state::steerlatch_r)
280	288	{
281		imolagp_state *state = space->machine().driver_data<imolagp_state>();
282		return state->m_steerlatch;
	289	return m_steerlatch;
283	290	}
284	291
285		static WRITE8_HANDLER( screenram_w )
	292	WRITE8_MEMBER(imolagp_state::screenram_w)
286	293	{ /* ?! */
287		imolagp_state *state = space->machine().driver_data<imolagp_state>();
288		switch (state->m_draw_mode)
	294	switch (m_draw_mode)
289	295	{
290	296	case 0x82:
291	297	case 0x81:
292	298	case 0x05:
293		state->m_videoram[1][offset] = data;
	299	m_videoram[1][offset] = data;
294	300	break;
295	301	case 0x06:
296		state->m_videoram[0][offset] = data;
	302	m_videoram[0][offset] = data;
297	303	break;
298	304	default:
299	305	break;
300	306	}
301	307	}
302	308
303		static READ8_HANDLER( imola_slave_port05r )
	309	READ8_MEMBER(imolagp_state::imola_slave_port05r)
304	310	{
305		imolagp_state *state = space->machine().driver_data<imolagp_state>();
306		memcpy(state->m_videoram[2], state->m_videoram[1], 0x4000); /* hack! capture before sprite plane is erased */
307		state->m_draw_mode = 0x05;
	311	memcpy(m_videoram[2], m_videoram[1], 0x4000); /* hack! capture before sprite plane is erased */
	312	m_draw_mode = 0x05;
308	313	return 0;
309	314	}
310	315
311		static READ8_HANDLER( imola_slave_port06r )
	316	READ8_MEMBER(imolagp_state::imola_slave_port06r)
312	317	{
313		imolagp_state *state = space->machine().driver_data<imolagp_state>();
314		state->m_draw_mode = 0x06;
	318	m_draw_mode = 0x06;
315	319	return 0;
316	320	}
317	321
318		static READ8_HANDLER( imola_slave_port81r )
	322	READ8_MEMBER(imolagp_state::imola_slave_port81r)
319	323	{
320		imolagp_state *state = space->machine().driver_data<imolagp_state>();
321		state->m_draw_mode = 0x81;
322		memcpy(state->m_videoram[2], state->m_videoram[1], 0x4000); /* hack! capture before sprite plane is erased */
	324	m_draw_mode = 0x81;
	325	memcpy(m_videoram[2], m_videoram[1], 0x4000); /* hack! capture before sprite plane is erased */
323	326	return 0;
324	327	}
325	328
326		static READ8_HANDLER( imola_slave_port82r )
	329	READ8_MEMBER(imolagp_state::imola_slave_port82r)
327	330	{
328		imolagp_state *state = space->machine().driver_data<imolagp_state>();
329		state->m_draw_mode = 0x82;
	331	m_draw_mode = 0x82;
330	332	return 0;
331	333	}
332	334
333		static WRITE8_HANDLER( vreg_control_w )
	335	WRITE8_MEMBER(imolagp_state::vreg_control_w)
334	336	{
335		imolagp_state *state = space->machine().driver_data<imolagp_state>();
336		state->m_control = data;
	337	m_control = data;
337	338	}
338	339
339		static WRITE8_HANDLER( vreg_data_w )
	340	WRITE8_MEMBER(imolagp_state::vreg_data_w)
340	341	{
341		imolagp_state *state = space->machine().driver_data<imolagp_state>();
342		switch (state->m_control)
	342	switch (m_control)
343	343	{
344	344	case 0x0e:
345		state->m_scroll = data;
	345	m_scroll = data;
346	346	break;
347	347	case 0x07: /* always 0xff? */
348	348	case 0x0f: /* 0xff or 0x00 */
349	349	default:
350		logerror("vreg[0x%02x]:=0x%02x\n", state->m_control, data);
	350	logerror("vreg[0x%02x]:=0x%02x\n", m_control, data);
351	351	break;
352	352	}
353	353	}
354	354
355	355	static ADDRESS_MAP_START( readport_master, AS_IO, 8, imolagp_state )
356	356	ADDRESS_MAP_GLOBAL_MASK(0xff)
357		AM_RANGE(0x00, 0x00) AM_READ_LEGACY(trigger_slave_nmi_r)
	357	AM_RANGE(0x00, 0x00) AM_READ(trigger_slave_nmi_r)
358	358	ADDRESS_MAP_END
359	359
360	360	static ADDRESS_MAP_START( imolagp_master, AS_PROGRAM, 8, imolagp_state )
361	361	AM_RANGE(0x0000, 0x1fff) AM_ROM
362	362	AM_RANGE(0x2000, 0x23ff) AM_RAM
363	363	AM_RANGE(0x2800, 0x2800) AM_READ_PORT("2800")   /* gas */
364		AM_RANGE(0x2802, 0x2802) AM_READ_LEGACY(steerlatch_r) AM_WRITENOP
	364	AM_RANGE(0x2802, 0x2802) AM_READ(steerlatch_r) AM_WRITENOP
365	365	/*  AM_RANGE(0x2803, 0x2803) ? */
366		AM_RANGE(0x3000, 0x3000) AM_WRITE_LEGACY(vreg_control_w)
	366	AM_RANGE(0x3000, 0x3000) AM_WRITE(vreg_control_w)
367	367	AM_RANGE(0x37f0, 0x37f0) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w)
368	368	/*  AM_RANGE(0x37f7, 0x37f7) ? */
369		AM_RANGE(0x3800, 0x3800) AM_WRITE_LEGACY(vreg_data_w)
	369	AM_RANGE(0x3800, 0x3800) AM_WRITE(vreg_data_w)
370	370	AM_RANGE(0x3810, 0x3810) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_w)
371	371	AM_RANGE(0x4000, 0x4000) AM_READ_PORT("DSWA")   /* DSWA */
372		AM_RANGE(0x5000, 0x50ff) AM_WRITE_LEGACY(imola_ledram_w)
373		AM_RANGE(0x47ff, 0x4800) AM_WRITE_LEGACY(transmit_data_w)
	372	AM_RANGE(0x5000, 0x50ff) AM_WRITE(imola_ledram_w)
	373	AM_RANGE(0x47ff, 0x4800) AM_WRITE(transmit_data_w)
374	374	AM_RANGE(0x6000, 0x6000) AM_READ_PORT("DSWB")   /* DSWB */
375	375	ADDRESS_MAP_END
376	376
377	377	static ADDRESS_MAP_START( readport_slave, AS_IO, 8, imolagp_state )
378	378	ADDRESS_MAP_GLOBAL_MASK(0xff)
379		AM_RANGE(0x05,0x05) AM_READ_LEGACY(imola_slave_port05r)
380		AM_RANGE(0x06,0x06) AM_READ_LEGACY(imola_slave_port06r)
381		AM_RANGE(0x81,0x81) AM_READ_LEGACY(imola_slave_port81r)
382		AM_RANGE(0x82,0x82) AM_READ_LEGACY(imola_slave_port82r)
	379	AM_RANGE(0x05,0x05) AM_READ(imola_slave_port05r)
	380	AM_RANGE(0x06,0x06) AM_READ(imola_slave_port06r)
	381	AM_RANGE(0x81,0x81) AM_READ(imola_slave_port81r)
	382	AM_RANGE(0x82,0x82) AM_READ(imola_slave_port82r)
383	383	ADDRESS_MAP_END
384	384
385	385	static ADDRESS_MAP_START( imolagp_slave, AS_PROGRAM, 8, imolagp_state )
r14845	r14846
388	388	AM_RANGE(0x1000, 0x13ff) AM_ROM
389	389	AM_RANGE(0x1c00, 0x3fff) AM_ROM
390	390	AM_RANGE(0x4000, 0x43ff) AM_RAM AM_BASE(m_slave_workram)
391		AM_RANGE(0x9fff, 0xa000) AM_READ_LEGACY(receive_data_r)
392		AM_RANGE(0xc000, 0xffff) AM_WRITE_LEGACY(screenram_w)
	391	AM_RANGE(0x9fff, 0xa000) AM_READ(receive_data_r)
	392	AM_RANGE(0xc000, 0xffff) AM_WRITE(screenram_w)
393	393	ADDRESS_MAP_END
394	394
395	395

src/mame/drivers/poker72.c

r14845	r14846
24	24	UINT8 *m_vram;
25	25	UINT8 *m_pal;
26	26	UINT8 m_tile_bank;
	27	DECLARE_WRITE8_MEMBER(poker72_paletteram_w);
	28	DECLARE_WRITE8_MEMBER(output_w);
	29	DECLARE_WRITE8_MEMBER(tile_bank_w);
27	30	};
28	31
29	32
r14845	r14846
58	61	return 0;
59	62	}
60	63
61		static WRITE8_HANDLER( poker72_paletteram_w )
	64	WRITE8_MEMBER(poker72_state::poker72_paletteram_w)
62	65	{
63		poker72_state *state = space->machine().driver_data<poker72_state>();
64	66	int r,g,b;
65		state->m_pal[offset] = data;
	67	m_pal[offset] = data;
66	68
67		r = state->m_pal[(offset & 0x3ff)+0x000] & 0x3f;
68		g = state->m_pal[(offset & 0x3ff)+0x400] & 0x3f;
69		b = state->m_pal[(offset & 0x3ff)+0x800] & 0x3f;
	69	r = m_pal[(offset & 0x3ff)+0x000] & 0x3f;
	70	g = m_pal[(offset & 0x3ff)+0x400] & 0x3f;
	71	b = m_pal[(offset & 0x3ff)+0x800] & 0x3f;
70	72
71		palette_set_color_rgb( space->machine(), offset & 0x3ff, pal6bit(r), pal6bit(g), pal6bit(b));
	73	palette_set_color_rgb( machine(), offset & 0x3ff, pal6bit(r), pal6bit(g), pal6bit(b));
72	74	}
73	75
74		static WRITE8_HANDLER( output_w )
	76	WRITE8_MEMBER(poker72_state::output_w)
75	77	{
76		UINT8 *ROM = space->machine().region("maincpu")->base();
	78	UINT8 *ROM = machine().region("maincpu")->base();
77	79
78	80	printf("%02x\n",data);
79	81
80	82	/*  if((data & 0xc) == 0xc)
81		memory_set_bankptr(space->machine(), "bank1", &ROM[0x10000]);
	83	memory_set_bankptr(machine(), "bank1", &ROM[0x10000]);
82	84	else*/
83	85	if(data & 8)
84		memory_set_bankptr(space->machine(), "bank1", &ROM[0x08000]);
	86	memory_set_bankptr(machine(), "bank1", &ROM[0x08000]);
85	87	else
86		memory_set_bankptr(space->machine(), "bank1", &ROM[0x00000]);
	88	memory_set_bankptr(machine(), "bank1", &ROM[0x00000]);
87	89	}
88	90
89		static WRITE8_HANDLER( tile_bank_w )
	91	WRITE8_MEMBER(poker72_state::tile_bank_w)
90	92	{
91		poker72_state *state = space->machine().driver_data<poker72_state>();
92		state->m_tile_bank = (data & 4) >> 2;
	93	m_tile_bank = (data & 4) >> 2;
93	94	}
94	95
95	96	static ADDRESS_MAP_START( poker72_map, AS_PROGRAM, 8, poker72_state )
96	97	AM_RANGE(0x0000, 0xbfff) AM_ROMBANK("bank1")
97	98	AM_RANGE(0xc000, 0xdfff) AM_RAM //work ram
98	99	AM_RANGE(0xe000, 0xefff) AM_RAM AM_BASE(m_vram)
99		AM_RANGE(0xf000, 0xfbff) AM_RAM_WRITE_LEGACY(poker72_paletteram_w) AM_BASE(m_pal)
	100	AM_RANGE(0xf000, 0xfbff) AM_RAM_WRITE(poker72_paletteram_w) AM_BASE(m_pal)
100	101	AM_RANGE(0xfc00, 0xfdff) AM_RAM //???
101	102	AM_RANGE(0xfe08, 0xfe08) AM_READ_PORT("IN0")
102	103	AM_RANGE(0xfe09, 0xfe09) AM_READ_PORT("IN1")
r14845	r14846
106	107	AM_RANGE(0xfe0e, 0xfe0e) AM_READ_PORT("IN5")
107	108
108	109	AM_RANGE(0xfe17, 0xfe17) AM_READNOP //irq ack
109		AM_RANGE(0xfe20, 0xfe20) AM_WRITE_LEGACY(output_w) //output, irq enable?
110		AM_RANGE(0xfe22, 0xfe22) AM_WRITE_LEGACY(tile_bank_w)
	110	AM_RANGE(0xfe20, 0xfe20) AM_WRITE(output_w) //output, irq enable?
	111	AM_RANGE(0xfe22, 0xfe22) AM_WRITE(tile_bank_w)
111	112	AM_RANGE(0xfe40, 0xfe40) AM_DEVREADWRITE_LEGACY("ay", ay8910_r, ay8910_data_w)
112	113	AM_RANGE(0xfe60, 0xfe60) AM_DEVWRITE_LEGACY("ay", ay8910_address_w)
113	114	ADDRESS_MAP_END

src/mame/drivers/umipoker.c

r14845	r14846
38	38	tilemap_t *m_tilemap_3;
39	39	UINT8 *m_z80_wram;
40	40	int m_umipoker_scrolly[4];
	41	DECLARE_READ8_MEMBER(z80_rom_readback_r);
	42	DECLARE_READ8_MEMBER(z80_shared_ram_r);
	43	DECLARE_WRITE8_MEMBER(z80_shared_ram_w);
	44	DECLARE_WRITE16_MEMBER(umipoker_irq_ack_w);
	45	DECLARE_WRITE16_MEMBER(umipoker_scrolly_0_w);
	46	DECLARE_WRITE16_MEMBER(umipoker_scrolly_1_w);
	47	DECLARE_WRITE16_MEMBER(umipoker_scrolly_2_w);
	48	DECLARE_WRITE16_MEMBER(umipoker_scrolly_3_w);
	49	DECLARE_WRITE16_MEMBER(umipoker_vram_0_w);
	50	DECLARE_WRITE16_MEMBER(umipoker_vram_1_w);
	51	DECLARE_WRITE16_MEMBER(umipoker_vram_2_w);
	52	DECLARE_WRITE16_MEMBER(umipoker_vram_3_w);
	53	DECLARE_WRITE16_MEMBER(lamps_w);
	54	DECLARE_WRITE16_MEMBER(umi_counters_w);
	55	DECLARE_WRITE16_MEMBER(saiyu_counters_w);
41	56	};
42	57
43	58	static TILE_GET_INFO( get_tile_info_0 )
r14845	r14846
127	142	return 0;
128	143	}
129	144
130		static READ8_HANDLER( z80_rom_readback_r )
	145	READ8_MEMBER(umipoker_state::z80_rom_readback_r)
131	146	{
132		UINT8 *ROM = space->machine().region("audiocpu")->base();
	147	UINT8 *ROM = machine().region("audiocpu")->base();
133	148
134	149	return ROM[offset];
135	150	}
136	151
137		static READ8_HANDLER( z80_shared_ram_r )
	152	READ8_MEMBER(umipoker_state::z80_shared_ram_r)
138	153	{
139		umipoker_state *state = space->machine().driver_data<umipoker_state>();
140	154
141		space->machine().scheduler().synchronize(); // force resync
	155	machine().scheduler().synchronize(); // force resync
142	156
143		return state->m_z80_wram[offset];
	157	return m_z80_wram[offset];
144	158	}
145	159
146		static WRITE8_HANDLER( z80_shared_ram_w )
	160	WRITE8_MEMBER(umipoker_state::z80_shared_ram_w)
147	161	{
148		umipoker_state *state = space->machine().driver_data<umipoker_state>();
149	162
150		space->machine().scheduler().synchronize(); // force resync
	163	machine().scheduler().synchronize(); // force resync
151	164
152		state->m_z80_wram[offset] = data;
	165	m_z80_wram[offset] = data;
153	166	}
154	167
155		static WRITE16_HANDLER( umipoker_irq_ack_w )
	168	WRITE16_MEMBER(umipoker_state::umipoker_irq_ack_w)
156	169	{
157		cputag_set_input_line(space->machine(), "maincpu", 6, CLEAR_LINE);
	170	cputag_set_input_line(machine(), "maincpu", 6, CLEAR_LINE);
158	171
159	172	/* shouldn't happen */
160	173	if(data)
161	174	popmessage("%04x IRQ ACK, contact MAMEdev",data);
162	175	}
163	176
164		static WRITE16_HANDLER( umipoker_scrolly_0_w ) { umipoker_state *state = space->machine().driver_data<umipoker_state>(); COMBINE_DATA(&state->m_umipoker_scrolly[0]); }
165		static WRITE16_HANDLER( umipoker_scrolly_1_w ) { umipoker_state *state = space->machine().driver_data<umipoker_state>(); COMBINE_DATA(&state->m_umipoker_scrolly[1]); }
166		static WRITE16_HANDLER( umipoker_scrolly_2_w ) { umipoker_state *state = space->machine().driver_data<umipoker_state>(); COMBINE_DATA(&state->m_umipoker_scrolly[2]); }
167		static WRITE16_HANDLER( umipoker_scrolly_3_w ) { umipoker_state *state = space->machine().driver_data<umipoker_state>(); COMBINE_DATA(&state->m_umipoker_scrolly[3]); }
	177	WRITE16_MEMBER(umipoker_state::umipoker_scrolly_0_w){ COMBINE_DATA(&m_umipoker_scrolly[0]); }
	178	WRITE16_MEMBER(umipoker_state::umipoker_scrolly_1_w){ COMBINE_DATA(&m_umipoker_scrolly[1]); }
	179	WRITE16_MEMBER(umipoker_state::umipoker_scrolly_2_w){ COMBINE_DATA(&m_umipoker_scrolly[2]); }
	180	WRITE16_MEMBER(umipoker_state::umipoker_scrolly_3_w){ COMBINE_DATA(&m_umipoker_scrolly[3]); }
168	181
169		static WRITE16_HANDLER( umipoker_vram_0_w )
	182	WRITE16_MEMBER(umipoker_state::umipoker_vram_0_w)
170	183	{
171		umipoker_state *state = space->machine().driver_data<umipoker_state>();
172	184
173		COMBINE_DATA(&state->m_vram_0[offset]);
174		state->m_tilemap_0->mark_tile_dirty(offset >> 1);
	185	COMBINE_DATA(&m_vram_0[offset]);
	186	m_tilemap_0->mark_tile_dirty(offset >> 1);
175	187	}
176	188
177		static WRITE16_HANDLER( umipoker_vram_1_w )
	189	WRITE16_MEMBER(umipoker_state::umipoker_vram_1_w)
178	190	{
179		umipoker_state *state = space->machine().driver_data<umipoker_state>();
180	191
181		COMBINE_DATA(&state->m_vram_1[offset]);
182		state->m_tilemap_1->mark_tile_dirty(offset >> 1);
	192	COMBINE_DATA(&m_vram_1[offset]);
	193	m_tilemap_1->mark_tile_dirty(offset >> 1);
183	194	}
184	195
185	196
186		static WRITE16_HANDLER( umipoker_vram_2_w )
	197	WRITE16_MEMBER(umipoker_state::umipoker_vram_2_w)
187	198	{
188		umipoker_state *state = space->machine().driver_data<umipoker_state>();
189	199
190		COMBINE_DATA(&state->m_vram_2[offset]);
191		state->m_tilemap_2->mark_tile_dirty(offset >> 1);
	200	COMBINE_DATA(&m_vram_2[offset]);
	201	m_tilemap_2->mark_tile_dirty(offset >> 1);
192	202	}
193	203
194		static WRITE16_HANDLER( umipoker_vram_3_w )
	204	WRITE16_MEMBER(umipoker_state::umipoker_vram_3_w)
195	205	{
196		umipoker_state *state = space->machine().driver_data<umipoker_state>();
197	206
198		COMBINE_DATA(&state->m_vram_3[offset]);
199		state->m_tilemap_3->mark_tile_dirty(offset >> 1);
	207	COMBINE_DATA(&m_vram_3[offset]);
	208	m_tilemap_3->mark_tile_dirty(offset >> 1);
200	209	}
201	210
202		static WRITE16_HANDLER( lamps_w )
	211	WRITE16_MEMBER(umipoker_state::lamps_w)
203	212	{
204	213	/*
205	214	Umipoker buttons layout:
r14845	r14846
248	257	output_set_lamp_value(5, (data >> 13) & 1);      /* Lamp 5 - START */
249	258	}
250	259
251		static WRITE16_HANDLER( umi_counters_w )
	260	WRITE16_MEMBER(umipoker_state::umi_counters_w)
252	261	{/*
253	262	0x0000 - Normal State (lamps off).
254	263	0x0001 - Payout pulse.
r14845	r14846
264	273	xxxx xxxx x--x xxx-  Unknown / Not used.
265	274
266	275	*/
267		coin_counter_w(space->machine(), 0, data & 0x20);   /* COIN 1 */
268		coin_counter_w(space->machine(), 1, data & 0x40);   /* COIN 2 */
269		coin_counter_w(space->machine(), 2, data & 0x01);   /* PAYOUT */
	276	coin_counter_w(machine(), 0, data & 0x20);   /* COIN 1 */
	277	coin_counter_w(machine(), 1, data & 0x40);   /* COIN 2 */
	278	coin_counter_w(machine(), 2, data & 0x01);   /* PAYOUT */
270	279	}
271	280
272		static WRITE16_HANDLER( saiyu_counters_w )
	281	WRITE16_MEMBER(umipoker_state::saiyu_counters_w)
273	282	{
274	283	/*
275	284	0x0000 - Normal State (lamps off).
r14845	r14846
286	295	x--x xxx- xxxx xxxx  Unknown / Not used.
287	296
288	297	*/
289		coin_counter_w(space->machine(), 0, data & 0x2000);   /* COIN 1 */
290		coin_counter_w(space->machine(), 1, data & 0x4000);   /* COIN 2 */
291		coin_counter_w(space->machine(), 2, data & 0x0100);   /* PAYOUT */
	298	coin_counter_w(machine(), 0, data & 0x2000);   /* COIN 1 */
	299	coin_counter_w(machine(), 1, data & 0x4000);   /* COIN 2 */
	300	coin_counter_w(machine(), 2, data & 0x0100);   /* PAYOUT */
292	301	}
293	302
294	303
r14845	r14846
297	306	AM_RANGE(0x000000, 0x03ffff) AM_ROM
298	307	AM_RANGE(0x400000, 0x403fff) AM_RAM AM_SHARE("nvram")
299	308	AM_RANGE(0x600000, 0x6007ff) AM_RAM_WRITE_LEGACY(paletteram16_xRRRRRGGGGGBBBBB_word_w) AM_BASE_GENERIC(paletteram)   // Palette
300		AM_RANGE(0x800000, 0x801fff) AM_RAM_WRITE_LEGACY(umipoker_vram_0_w) AM_BASE(m_vram_0)
301		AM_RANGE(0x802000, 0x803fff) AM_RAM_WRITE_LEGACY(umipoker_vram_1_w) AM_BASE(m_vram_1)
302		AM_RANGE(0x804000, 0x805fff) AM_RAM_WRITE_LEGACY(umipoker_vram_2_w) AM_BASE(m_vram_2)
303		AM_RANGE(0x806000, 0x807fff) AM_RAM_WRITE_LEGACY(umipoker_vram_3_w) AM_BASE(m_vram_3)
304		AM_RANGE(0xc00000, 0xc0ffff) AM_READ8_LEGACY(z80_rom_readback_r,0x00ff)
305		AM_RANGE(0xc1f000, 0xc1ffff) AM_READWRITE8_LEGACY(z80_shared_ram_r,z80_shared_ram_w,0x00ff)
	309	AM_RANGE(0x800000, 0x801fff) AM_RAM_WRITE(umipoker_vram_0_w) AM_BASE(m_vram_0)
	310	AM_RANGE(0x802000, 0x803fff) AM_RAM_WRITE(umipoker_vram_1_w) AM_BASE(m_vram_1)
	311	AM_RANGE(0x804000, 0x805fff) AM_RAM_WRITE(umipoker_vram_2_w) AM_BASE(m_vram_2)
	312	AM_RANGE(0x806000, 0x807fff) AM_RAM_WRITE(umipoker_vram_3_w) AM_BASE(m_vram_3)
	313	AM_RANGE(0xc00000, 0xc0ffff) AM_READ8(z80_rom_readback_r,0x00ff)
	314	AM_RANGE(0xc1f000, 0xc1ffff) AM_READWRITE8(z80_shared_ram_r,z80_shared_ram_w,0x00ff)
306	315	AM_RANGE(0xe00000, 0xe00001) AM_READ_PORT("IN0")
307	316	AM_RANGE(0xe00004, 0xe00005) AM_READ_PORT("IN1") // unused?
308	317	AM_RANGE(0xe00008, 0xe00009) AM_READ_PORT("IN2")
309		//  AM_RANGE(0xe0000c, 0xe0000d) AM_WRITE_LEGACY(lamps_w) -----> lamps only for saiyukip.
	318	//  AM_RANGE(0xe0000c, 0xe0000d) AM_WRITE(lamps_w) -----> lamps only for saiyukip.
310	319	//  AM_RANGE(0xe00010, 0xe00011) AM_WRITE_LEGACY(counters_w) --> coin counters for both games.
311	320	AM_RANGE(0xe00014, 0xe00015) AM_READ_PORT("DSW1-2")
312	321	AM_RANGE(0xe00018, 0xe00019) AM_READ_PORT("DSW3-4")
313		AM_RANGE(0xe00020, 0xe00021) AM_WRITE_LEGACY(umipoker_scrolly_0_w)
314		AM_RANGE(0xe00022, 0xe00023) AM_WRITE_LEGACY(umipoker_irq_ack_w)
315		AM_RANGE(0xe00026, 0xe00027) AM_WRITE_LEGACY(umipoker_scrolly_2_w)
316		AM_RANGE(0xe0002a, 0xe0002b) AM_WRITE_LEGACY(umipoker_scrolly_1_w)
	322	AM_RANGE(0xe00020, 0xe00021) AM_WRITE(umipoker_scrolly_0_w)
	323	AM_RANGE(0xe00022, 0xe00023) AM_WRITE(umipoker_irq_ack_w)
	324	AM_RANGE(0xe00026, 0xe00027) AM_WRITE(umipoker_scrolly_2_w)
	325	AM_RANGE(0xe0002a, 0xe0002b) AM_WRITE(umipoker_scrolly_1_w)
317	326	AM_RANGE(0xe0002c, 0xe0002d) AM_WRITENOP // unknown meaning, bit 0 goes from 0 -> 1 on IRQ service routine
318		AM_RANGE(0xe0002e, 0xe0002f) AM_WRITE_LEGACY(umipoker_scrolly_3_w)
	327	AM_RANGE(0xe0002e, 0xe0002f) AM_WRITE(umipoker_scrolly_3_w)
319	328	ADDRESS_MAP_END
320	329
321	330	static ADDRESS_MAP_START( umipoker_audio_map, AS_PROGRAM, 8, umipoker_state )
322	331	AM_RANGE(0x0000, 0x7fff) AM_ROM
323		AM_RANGE(0xf800, 0xffff) AM_READWRITE_LEGACY(z80_shared_ram_r,z80_shared_ram_w) AM_BASE(m_z80_wram)
	332	AM_RANGE(0xf800, 0xffff) AM_READWRITE(z80_shared_ram_r,z80_shared_ram_w) AM_BASE(m_z80_wram)
324	333	ADDRESS_MAP_END
325	334
326	335	static ADDRESS_MAP_START( umipoker_audio_io_map, AS_IO, 8, umipoker_state )
r14845	r14846
734	743
735	744	static DRIVER_INIT( umipoker )
736	745	{
737		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xe00010, 0xe00011, FUNC(umi_counters_w) );
	746	umipoker_state *state = machine.driver_data<umipoker_state>();
	747	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0xe00010, 0xe00011, write16_delegate(FUNC(umipoker_state::umi_counters_w), state));
738	748	}
739	749
740	750	static DRIVER_INIT( saiyukip )
741	751	{
742		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xe00010, 0xe00011, FUNC(saiyu_counters_w) );
743		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_write_handler(0xe0000c, 0xe0000d, FUNC(lamps_w) );
	752	umipoker_state *state = machine.driver_data<umipoker_state>();
	753	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0xe00010, 0xe00011, write16_delegate(FUNC(umipoker_state::saiyu_counters_w), state));
	754	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0xe0000c, 0xe0000d, write16_delegate(FUNC(umipoker_state::lamps_w), state));
744	755	}
745	756
746	757

src/mame/drivers/wldarrow.c

r14845	r14846
35	35	UINT8 *m_videoram_1;
36	36	UINT8 *m_videoram_2;
37	37	size_t m_videoram_size;
	38	DECLARE_WRITE8_MEMBER(lights_1_w);
	39	DECLARE_WRITE8_MEMBER(lights_2_w);
	40	DECLARE_WRITE8_MEMBER(counter_w);
38	41	};
39	42
40	43
r14845	r14846
110	113	*
111	114	*************************************/
112	115
113		static WRITE8_HANDLER( lights_1_w )
	116	WRITE8_MEMBER(wldarrow_state::lights_1_w)
114	117	{
115	118	/* not sure how it is hooked up */
116	119	}
117	120
118	121
119		static WRITE8_HANDLER( lights_2_w )
	122	WRITE8_MEMBER(wldarrow_state::lights_2_w)
120	123	{
121	124	/* not sure how it is hooked up */
122	125	}
123	126
124	127
125		static WRITE8_HANDLER( counter_w )
	128	WRITE8_MEMBER(wldarrow_state::counter_w)
126	129	{
127		coin_counter_w(space->machine(), 0, data);
	130	coin_counter_w(machine(), 0, data);
128	131	}
129	132
130	133
r14845	r14846
179	182	AM_RANGE(0x8000, 0x9fff) AM_RAM AM_BASE(m_videoram_2)
180	183	AM_RANGE(0xcd00, 0xcdff) AM_RAM AM_SHARE("nvram")
181	184	AM_RANGE(0xf000, 0xf000) AM_READ_PORT("BITSW") AM_DEVWRITE_LEGACY("dac", wldarrow_dac_1_w)
182		AM_RANGE(0xf004, 0xf004) AM_READ_PORT("IN1") AM_WRITE_LEGACY(lights_1_w)
183		AM_RANGE(0xf006, 0xf006) AM_READ_PORT("IN2") AM_WRITE_LEGACY(lights_2_w)
184		AM_RANGE(0xf008, 0xf008) AM_WRITE_LEGACY(counter_w)
	185	AM_RANGE(0xf004, 0xf004) AM_READ_PORT("IN1") AM_WRITE(lights_1_w)
	186	AM_RANGE(0xf006, 0xf006) AM_READ_PORT("IN2") AM_WRITE(lights_2_w)
	187	AM_RANGE(0xf008, 0xf008) AM_WRITE(counter_w)
185	188	AM_RANGE(0xf00f, 0xf00f) AM_DEVWRITE_LEGACY("dac", wldarrow_dac_2_w)
186	189	AM_RANGE(0xf0f0, 0xf0f0) AM_DEVWRITE_LEGACY("dac", wldarrow_dac_3_w)
187	190	AM_RANGE(0xf0ff, 0xf0ff) AM_DEVWRITE_LEGACY("dac", wldarrow_dac_4_w)

src/mame/drivers/hotblock.c

r14845	r14846
60	60
61	61	/* memory */
62	62	UINT8    m_pal[0x10000];
	63	DECLARE_READ8_MEMBER(hotblock_video_read);
	64	DECLARE_READ8_MEMBER(hotblock_port4_r);
	65	DECLARE_WRITE8_MEMBER(hotblock_port4_w);
	66	DECLARE_WRITE8_MEMBER(hotblock_port0_w);
	67	DECLARE_WRITE8_MEMBER(hotblock_video_write);
63	68	};
64	69
65	70
66	71
67		static READ8_HANDLER( hotblock_video_read )
	72	READ8_MEMBER(hotblock_state::hotblock_video_read)
68	73	{
69		hotblock_state *state = space->machine().driver_data<hotblock_state>();
70	74	/* right?, anything else?? */
71		if (state->m_port0 & 0x20) // port 0 = a8 e8 -- palette
	75	if (m_port0 & 0x20) // port 0 = a8 e8 -- palette
72	76	{
73		return state->m_pal[offset];
	77	return m_pal[offset];
74	78	}
75	79	else // port 0 = 88 c8
76	80	{
77		return state->m_vram[offset];
	81	return m_vram[offset];
78	82	}
79	83	}
80	84
81	85	/* port 4 is some kind of eeprom / storage .. used to store the scores */
82		static READ8_HANDLER( hotblock_port4_r )
	86	READ8_MEMBER(hotblock_state::hotblock_port4_r)
83	87	{
84	88	//  mame_printf_debug("port4_r\n");
85	89	return 0x00;
86	90	}
87	91
88	92
89		static WRITE8_HANDLER( hotblock_port4_w )
	93	WRITE8_MEMBER(hotblock_state::hotblock_port4_w)
90	94	{
91		//  mame_printf_debug("port4_w: pc = %06x : data %04x\n", cpu_get_pc(&space->device()), data);
92		//  popmessage("port4_w: pc = %06x : data %04x", cpu_get_pc(&space->device()), data);
93		hotblock_state *state = space->machine().driver_data<hotblock_state>();
94		state->m_port4 = data;
	95	//  mame_printf_debug("port4_w: pc = %06x : data %04x\n", cpu_get_pc(&space.device()), data);
	96	//  popmessage("port4_w: pc = %06x : data %04x", cpu_get_pc(&space.device()), data);
	97
	98	m_port4 = data;
95	99	}
96	100
97	101
98	102
99		static WRITE8_HANDLER( hotblock_port0_w )
	103	WRITE8_MEMBER(hotblock_state::hotblock_port0_w)
100	104	{
101		//  popmessage("port4_w: pc = %06x : data %04x", cpu_get_pc(&space->device()), data);
102		hotblock_state *state = space->machine().driver_data<hotblock_state>();
103		state->m_port0 = data;
	105	//  popmessage("port4_w: pc = %06x : data %04x", cpu_get_pc(&space.device()), data);
	106
	107	m_port0 = data;
104	108	}
105	109
106		static WRITE8_HANDLER( hotblock_video_write )
	110	WRITE8_MEMBER(hotblock_state::hotblock_video_write)
107	111	{
108		hotblock_state *state = space->machine().driver_data<hotblock_state>();
109	112	/* right?, anything else?? */
110		if (state->m_port0 & 0x20) // port 0 = a8 e8 -- palette
	113	if (m_port0 & 0x20) // port 0 = a8 e8 -- palette
111	114	{
112		state->m_pal[offset] = data;
	115	m_pal[offset] = data;
113	116	}
114	117	else // port 0 = 88 c8
115	118	{
116		state->m_vram[offset] = data;
	119	m_vram[offset] = data;
117	120	}
118	121	}
119	122
120	123	static ADDRESS_MAP_START( hotblock_map, AS_PROGRAM, 8, hotblock_state )
121	124	AM_RANGE(0x00000, 0x0ffff) AM_RAM
122		AM_RANGE(0x10000, 0x1ffff) AM_READWRITE_LEGACY(hotblock_video_read, hotblock_video_write) AM_BASE(m_vram)
	125	AM_RANGE(0x10000, 0x1ffff) AM_READWRITE(hotblock_video_read, hotblock_video_write) AM_BASE(m_vram)
123	126	AM_RANGE(0x20000, 0xfffff) AM_ROM
124	127	ADDRESS_MAP_END
125	128
126	129	static ADDRESS_MAP_START( hotblock_io, AS_IO, 8, hotblock_state )
127		AM_RANGE(0x0000, 0x0000) AM_WRITE_LEGACY(hotblock_port0_w)
128		AM_RANGE(0x0004, 0x0004) AM_READWRITE_LEGACY(hotblock_port4_r, hotblock_port4_w)
	130	AM_RANGE(0x0000, 0x0000) AM_WRITE(hotblock_port0_w)
	131	AM_RANGE(0x0004, 0x0004) AM_READWRITE(hotblock_port4_r, hotblock_port4_w)
129	132	AM_RANGE(0x8000, 0x8001) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
130	133	AM_RANGE(0x8001, 0x8001) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
131	134	ADDRESS_MAP_END

src/mame/drivers/nwk-tr.c

r14845	r14846
240	240	int m_lanc2_ram_w;
241	241	UINT8 *m_lanc2_ram;
242	242	UINT32 *m_sharc_dataram;
	243	DECLARE_WRITE32_MEMBER(paletteram32_w);
	244	DECLARE_READ32_MEMBER(sysreg_r);
	245	DECLARE_WRITE32_MEMBER(sysreg_w);
	246	DECLARE_READ32_MEMBER(lanc1_r);
	247	DECLARE_WRITE32_MEMBER(lanc1_w);
	248	DECLARE_READ32_MEMBER(lanc2_r);
	249	DECLARE_WRITE32_MEMBER(lanc2_w);
	250	DECLARE_READ32_MEMBER(dsp_dataram_r);
	251	DECLARE_WRITE32_MEMBER(dsp_dataram_w);
243	252	};
244	253
245	254
246	255
247	256
248	257
249		static WRITE32_HANDLER( paletteram32_w )
	258	WRITE32_MEMBER(nwktr_state::paletteram32_w)
250	259	{
251		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
252		data = space->machine().generic.paletteram.u32[offset];
253		palette_set_color_rgb(space->machine(), offset, pal5bit(data >> 10), pal5bit(data >> 5), pal5bit(data >> 0));
	260	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
	261	data = machine().generic.paletteram.u32[offset];
	262	palette_set_color_rgb(machine(), offset, pal5bit(data >> 10), pal5bit(data >> 5), pal5bit(data >> 0));
254	263	}
255	264
256	265	static void voodoo_vblank_0(device_t *device, int param)
r14845	r14846
278	287
279	288	/*****************************************************************************/
280	289
281		static READ32_HANDLER( sysreg_r )
	290	READ32_MEMBER(nwktr_state::sysreg_r)
282	291	{
283		device_t *adc12138 = space->machine().device("adc12138");
	292	device_t *adc12138 = machine().device("adc12138");
284	293	UINT32 r = 0;
285	294	if (offset == 0)
286	295	{
287	296	if (ACCESSING_BITS_24_31)
288	297	{
289		r |= input_port_read(space->machine(), "IN0") << 24;
	298	r |= input_port_read(machine(), "IN0") << 24;
290	299	}
291	300	if (ACCESSING_BITS_16_23)
292	301	{
293		r |= input_port_read(space->machine(), "IN1") << 16;
	302	r |= input_port_read(machine(), "IN1") << 16;
294	303	}
295	304	if (ACCESSING_BITS_8_15)
296	305	{
297		r |= input_port_read(space->machine(), "IN2") << 8;
	306	r |= input_port_read(machine(), "IN2") << 8;
298	307	}
299	308	if (ACCESSING_BITS_0_7)
300	309	{
r14845	r14846
305	314	{
306	315	if (ACCESSING_BITS_24_31)
307	316	{
308		r |= input_port_read(space->machine(), "DSW") << 24;
	317	r |= input_port_read(machine(), "DSW") << 24;
309	318	}
310	319	}
311	320	return r;
312	321	}
313	322
314		static WRITE32_HANDLER( sysreg_w )
	323	WRITE32_MEMBER(nwktr_state::sysreg_w)
315	324	{
316		nwktr_state *state = space->machine().driver_data<nwktr_state>();
317		device_t *adc12138 = space->machine().device("adc12138");
	325	device_t *adc12138 = machine().device("adc12138");
318	326	if( offset == 0 )
319	327	{
320	328	if (ACCESSING_BITS_24_31)
321	329	{
322		state->m_led_reg0 = (data >> 24) & 0xff;
	330	m_led_reg0 = (data >> 24) & 0xff;
323	331	}
324	332	if (ACCESSING_BITS_16_23)
325	333	{
326		state->m_led_reg1 = (data >> 16) & 0xff;
	334	m_led_reg1 = (data >> 16) & 0xff;
327	335	}
328	336	return;
329	337	}
r14845	r14846
345	353	{
346	354	if (data & 0x80)   // CG Board 1 IRQ Ack
347	355	{
348		//cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ1, CLEAR_LINE);
	356	//cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ1, CLEAR_LINE);
349	357	}
350	358	if (data & 0x40)   // CG Board 0 IRQ Ack
351	359	{
352		//cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
	360	//cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ0, CLEAR_LINE);
353	361	}
354	362	}
355	363	return;
r14845	r14846
366	374	state->m_lanc2_ram = auto_alloc_array(machine, UINT8, 0x8000);
367	375	}
368	376
369		static READ32_HANDLER( lanc1_r )
	377	READ32_MEMBER(nwktr_state::lanc1_r)
370	378	{
371		nwktr_state *state = space->machine().driver_data<nwktr_state>();
372	379	switch (offset)
373	380	{
374	381	case 0x40/4:
375	382	{
376	383	UINT32 r = 0;
377	384
378		r |= (state->m_fpga_uploaded) ? (1 << 6) : 0;
	385	r |= (m_fpga_uploaded) ? (1 << 6) : 0;
379	386	r |= 1 << 5;
380	387
381	388	return (r) << 24;
r14845	r14846
383	390
384	391	default:
385	392	{
386		//printf("lanc1_r: %08X, %08X at %08X\n", offset, mem_mask, cpu_get_pc(&space->device()));
	393	//printf("lanc1_r: %08X, %08X at %08X\n", offset, mem_mask, cpu_get_pc(&space.device()));
387	394	return 0xffffffff;
388	395	}
389	396	}
390	397	}
391	398
392		static WRITE32_HANDLER( lanc1_w )
	399	WRITE32_MEMBER(nwktr_state::lanc1_w)
393	400	{
394		//printf("lanc1_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, cpu_get_pc(&space->device()));
	401	//printf("lanc1_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, cpu_get_pc(&space.device()));
395	402	}
396	403
397		static READ32_HANDLER( lanc2_r )
	404	READ32_MEMBER(nwktr_state::lanc2_r)
398	405	{
399		nwktr_state *state = space->machine().driver_data<nwktr_state>();
400	406	UINT32 r = 0;
401	407
402	408	if (offset == 0)
403	409	{
404	410	if (ACCESSING_BITS_0_7)
405	411	{
406		r |= state->m_lanc2_ram[state->m_lanc2_ram_r & 0x7fff];
407		state->m_lanc2_ram_r++;
	412	r |= m_lanc2_ram[m_lanc2_ram_r & 0x7fff];
	413	m_lanc2_ram_r++;
408	414	}
409	415	else
410	416	{
r14845	r14846
420	426	}
421	427	}
422	428
423		//printf("lanc2_r: %08X, %08X at %08X\n", offset, mem_mask, cpu_get_pc(&space->device()));
	429	//printf("lanc2_r: %08X, %08X at %08X\n", offset, mem_mask, cpu_get_pc(&space.device()));
424	430
425	431	return r;
426	432	}
427	433
428		static WRITE32_HANDLER( lanc2_w )
	434	WRITE32_MEMBER(nwktr_state::lanc2_w)
429	435	{
430		nwktr_state *state = space->machine().driver_data<nwktr_state>();
431	436	if (offset == 0)
432	437	{
433	438	if (ACCESSING_BITS_24_31)
r14845	r14846
443	448	((value << 5) & 0x40) |
444	449	((value << 7) & 0x80);
445	450
446		state->m_fpga_uploaded = 1;
	451	m_fpga_uploaded = 1;
447	452
448		//printf("lanc2_fpga_w: %02X at %08X\n", value, cpu_get_pc(&space->device()));
	453	//printf("lanc2_fpga_w: %02X at %08X\n", value, cpu_get_pc(&space.device()));
449	454	}
450	455	else if (ACCESSING_BITS_0_7)
451	456	{
452		state->m_lanc2_ram[state->m_lanc2_ram_w & 0x7fff] = data & 0xff;
453		state->m_lanc2_ram_w++;
	457	m_lanc2_ram[m_lanc2_ram_w & 0x7fff] = data & 0xff;
	458	m_lanc2_ram_w++;
454	459	}
455	460	else
456	461	{
457		//printf("lanc2_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, cpu_get_pc(&space->device()));
	462	//printf("lanc2_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, cpu_get_pc(&space.device()));
458	463	}
459	464	}
460	465	if (offset == 4)
461	466	{
462		if (mame_stricmp(space->machine().system().name, "thrilld") == 0)
	467	if (mame_stricmp(machine().system().name, "thrilld") == 0)
463	468	{
464		state->m_work_ram[(0x3ffed0/4) + 0] = 0x472a3731;
465		state->m_work_ram[(0x3ffed0/4) + 1] = 0x33202020;
466		state->m_work_ram[(0x3ffed0/4) + 2] = 0x2d2d2a2a;
467		state->m_work_ram[(0x3ffed0/4) + 3] = 0x2a207878;
	469	m_work_ram[(0x3ffed0/4) + 0] = 0x472a3731;
	470	m_work_ram[(0x3ffed0/4) + 1] = 0x33202020;
	471	m_work_ram[(0x3ffed0/4) + 2] = 0x2d2d2a2a;
	472	m_work_ram[(0x3ffed0/4) + 3] = 0x2a207878;
468	473
469		state->m_work_ram[(0x3fff40/4) + 0] = 0x47433731;
470		state->m_work_ram[(0x3fff40/4) + 1] = 0x33000000;
471		state->m_work_ram[(0x3fff40/4) + 2] = 0x19994a41;
472		state->m_work_ram[(0x3fff40/4) + 3] = 0x4100a9b1;
	474	m_work_ram[(0x3fff40/4) + 0] = 0x47433731;
	475	m_work_ram[(0x3fff40/4) + 1] = 0x33000000;
	476	m_work_ram[(0x3fff40/4) + 2] = 0x19994a41;
	477	m_work_ram[(0x3fff40/4) + 3] = 0x4100a9b1;
473	478	}
474	479	}
475	480
476		//printf("lanc2_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, cpu_get_pc(&space->device()));
	481	//printf("lanc2_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, cpu_get_pc(&space.device()));
477	482	}
478	483
479	484	/*****************************************************************************/
r14845	r14846
491	496	static ADDRESS_MAP_START( nwktr_map, AS_PROGRAM, 32, nwktr_state )
492	497	AM_RANGE(0x00000000, 0x003fffff) AM_RAM AM_BASE(m_work_ram)      /* Work RAM */
493	498	AM_RANGE(0x74000000, 0x740000ff) AM_DEVREADWRITE_LEGACY("k001604", k001604_reg_r, k001604_reg_w)
494		AM_RANGE(0x74010000, 0x74017fff) AM_RAM_WRITE_LEGACY(paletteram32_w) AM_BASE_GENERIC(paletteram)
	499	AM_RANGE(0x74010000, 0x74017fff) AM_RAM_WRITE(paletteram32_w) AM_BASE_GENERIC(paletteram)
495	500	AM_RANGE(0x74020000, 0x7403ffff) AM_DEVREADWRITE_LEGACY("k001604", k001604_tile_r, k001604_tile_w)
496	501	AM_RANGE(0x74040000, 0x7407ffff) AM_DEVREADWRITE_LEGACY("k001604", k001604_char_r, k001604_char_w)
497	502	AM_RANGE(0x78000000, 0x7800ffff) AM_READWRITE_LEGACY(cgboard_dsp_shared_r_ppc, cgboard_dsp_shared_w_ppc)
498	503	AM_RANGE(0x780c0000, 0x780c0003) AM_READWRITE_LEGACY(cgboard_dsp_comm_r_ppc, cgboard_dsp_comm_w_ppc)
499		AM_RANGE(0x7d000000, 0x7d00ffff) AM_READ_LEGACY(sysreg_r)
500		AM_RANGE(0x7d010000, 0x7d01ffff) AM_WRITE_LEGACY(sysreg_w)
	504	AM_RANGE(0x7d000000, 0x7d00ffff) AM_READ(sysreg_r)
	505	AM_RANGE(0x7d010000, 0x7d01ffff) AM_WRITE(sysreg_w)
501	506	AM_RANGE(0x7d020000, 0x7d021fff) AM_DEVREADWRITE8_LEGACY("m48t58", timekeeper_r, timekeeper_w, 0xffffffff)   /* M48T58Y RTC/NVRAM */
502	507	AM_RANGE(0x7d030000, 0x7d030007) AM_DEVREAD_LEGACY("k056800", k056800_host_r)
503	508	AM_RANGE(0x7d030000, 0x7d030007) AM_DEVWRITE_LEGACY("k056800", k056800_host_w)
504	509	AM_RANGE(0x7d030008, 0x7d03000f) AM_DEVWRITE_LEGACY("k056800", k056800_host_w)
505		AM_RANGE(0x7d040000, 0x7d04ffff) AM_READWRITE_LEGACY(lanc1_r, lanc1_w)
506		AM_RANGE(0x7d050000, 0x7d05ffff) AM_READWRITE_LEGACY(lanc2_r, lanc2_w)
	510	AM_RANGE(0x7d040000, 0x7d04ffff) AM_READWRITE(lanc1_r, lanc1_w)
	511	AM_RANGE(0x7d050000, 0x7d05ffff) AM_READWRITE(lanc2_r, lanc2_w)
507	512	AM_RANGE(0x7e000000, 0x7e7fffff) AM_ROM AM_REGION("user2", 0)   /* Data ROM */
508	513	AM_RANGE(0x7f000000, 0x7f1fffff) AM_ROM AM_SHARE("share2")
509	514	AM_RANGE(0x7fe00000, 0x7fffffff) AM_ROM AM_REGION("user1", 0) AM_SHARE("share2")   /* Program ROM */
r14845	r14846
522	527	/*****************************************************************************/
523	528
524	529
525		static READ32_HANDLER( dsp_dataram_r )
	530	READ32_MEMBER(nwktr_state::dsp_dataram_r)
526	531	{
527		nwktr_state *state = space->machine().driver_data<nwktr_state>();
528		return state->m_sharc_dataram[offset] & 0xffff;
	532	return m_sharc_dataram[offset] & 0xffff;
529	533	}
530	534
531		static WRITE32_HANDLER( dsp_dataram_w )
	535	WRITE32_MEMBER(nwktr_state::dsp_dataram_w)
532	536	{
533		nwktr_state *state = space->machine().driver_data<nwktr_state>();
534		state->m_sharc_dataram[offset] = data;
	537	m_sharc_dataram[offset] = data;
535	538	}
536	539
537	540	static ADDRESS_MAP_START( sharc_map, AS_DATA, 32, nwktr_state )
538	541	AM_RANGE(0x0400000, 0x041ffff) AM_READWRITE_LEGACY(cgboard_0_shared_sharc_r, cgboard_0_shared_sharc_w)
539		AM_RANGE(0x0500000, 0x05fffff) AM_READWRITE_LEGACY(dsp_dataram_r, dsp_dataram_w)
	542	AM_RANGE(0x0500000, 0x05fffff) AM_READWRITE(dsp_dataram_r, dsp_dataram_w)
540	543	AM_RANGE(0x1400000, 0x14fffff) AM_RAM
541	544	AM_RANGE(0x2400000, 0x27fffff) AM_DEVREADWRITE_LEGACY("voodoo", nwk_voodoo_0_r, nwk_voodoo_0_w)
542	545	AM_RANGE(0x3400000, 0x34000ff) AM_READWRITE_LEGACY(cgboard_0_comm_sharc_r, cgboard_0_comm_sharc_w)

src/mame/drivers/jpmsys5.c

r14845	r14846
69	69	UINT8 m_a2_acia_dcd;
70	70	UINT8 m_a2_data_out;
71	71	UINT8 m_a2_data_in;
	72	DECLARE_WRITE16_MEMBER(sys5_tms34061_w);
	73	DECLARE_READ16_MEMBER(sys5_tms34061_r);
	74	DECLARE_WRITE16_MEMBER(ramdac_w);
	75	DECLARE_WRITE16_MEMBER(rombank_w);
	76	DECLARE_READ16_MEMBER(coins_r);
	77	DECLARE_WRITE16_MEMBER(coins_w);
	78	DECLARE_READ16_MEMBER(unk_r);
	79	DECLARE_WRITE16_MEMBER(mux_w);
	80	DECLARE_READ16_MEMBER(mux_r);
72	81	};
73	82
74	83
r14845	r14846
110	119	tms_interrupt   /* Interrupt gen callback */
111	120	};
112	121
113		static WRITE16_HANDLER( sys5_tms34061_w )
	122	WRITE16_MEMBER(jpmsys5_state::sys5_tms34061_w)
114	123	{
115	124	int func = (offset >> 19) & 3;
116	125	int row = (offset >> 7) & 0x1ff;
r14845	r14846
127	136	}
128	137
129	138	if (ACCESSING_BITS_8_15)
130		tms34061_w(space, col, row, func, data >> 8);
	139	tms34061_w(&space, col, row, func, data >> 8);
131	140
132	141	if (ACCESSING_BITS_0_7)
133		tms34061_w(space, col | 1, row, func, data & 0xff);
	142	tms34061_w(&space, col | 1, row, func, data & 0xff);
134	143	}
135	144
136		static READ16_HANDLER( sys5_tms34061_r )
	145	READ16_MEMBER(jpmsys5_state::sys5_tms34061_r)
137	146	{
138	147	UINT16 data = 0;
139	148	int func = (offset >> 19) & 3;
r14845	r14846
151	160	}
152	161
153	162	if (ACCESSING_BITS_8_15)
154		data |= tms34061_r(space, col, row, func) << 8;
	163	data |= tms34061_r(&space, col, row, func) << 8;
155	164
156	165	if (ACCESSING_BITS_0_7)
157		data |= tms34061_r(space, col | 1, row, func);
	166	data |= tms34061_r(&space, col | 1, row, func);
158	167
159	168	return data;
160	169	}
161	170
162		static WRITE16_HANDLER( ramdac_w )
	171	WRITE16_MEMBER(jpmsys5_state::ramdac_w)
163	172	{
164		jpmsys5_state *state = space->machine().driver_data<jpmsys5_state>();
165	173	if (offset == 0)
166	174	{
167		state->m_pal_addr = data;
168		state->m_pal_idx = 0;
	175	m_pal_addr = data;
	176	m_pal_idx = 0;
169	177	}
170	178	else if (offset == 1)
171	179	{
172		state->m_palette[state->m_pal_addr][state->m_pal_idx] = data;
	180	m_palette[m_pal_addr][m_pal_idx] = data;
173	181
174		if (++state->m_pal_idx == 3)
	182	if (++m_pal_idx == 3)
175	183	{
176	184	/* Update the MAME palette */
177		palette_set_color_rgb(space->machine(), state->m_pal_addr, pal6bit(state->m_palette[state->m_pal_addr][0]), pal6bit(state->m_palette[state->m_pal_addr][1]), pal6bit(state->m_palette[state->m_pal_addr][2]));
178		state->m_pal_addr++;
179		state->m_pal_idx = 0;
	185	palette_set_color_rgb(machine(), m_pal_addr, pal6bit(m_palette[m_pal_addr][0]), pal6bit(m_palette[m_pal_addr][1]), pal6bit(m_palette[m_pal_addr][2]));
	186	m_pal_addr++;
	187	m_pal_idx = 0;
180	188	}
181	189	}
182	190	else
r14845	r14846
238	246	*
239	247	****************************************/
240	248
241		static WRITE16_HANDLER( rombank_w )
	249	WRITE16_MEMBER(jpmsys5_state::rombank_w)
242	250	{
243		UINT8 *rom = space->machine().region("maincpu")->base();
	251	UINT8 *rom = machine().region("maincpu")->base();
244	252	data &= 0x1f;
245		memory_set_bankptr(space->machine(), "bank1", &rom[0x20000 + 0x20000 * data]);
	253	memory_set_bankptr(machine(), "bank1", &rom[0x20000 + 0x20000 * data]);
246	254	}
247	255
248		static READ16_HANDLER( coins_r )
	256	READ16_MEMBER(jpmsys5_state::coins_r)
249	257	{
250	258	if (offset == 2)
251		return input_port_read(space->machine(), "COINS") << 8;
	259	return input_port_read(machine(), "COINS") << 8;
252	260	else
253	261	return 0xffff;
254	262	}
255	263
256		static WRITE16_HANDLER( coins_w )
	264	WRITE16_MEMBER(jpmsys5_state::coins_w)
257	265	{
258	266	/* TODO */
259	267	}
260	268
261		static READ16_HANDLER( unk_r )
	269	READ16_MEMBER(jpmsys5_state::unk_r)
262	270	{
263	271	return 0xffff;
264	272	}
265	273
266		static WRITE16_HANDLER( mux_w )
	274	WRITE16_MEMBER(jpmsys5_state::mux_w)
267	275	{
268		jpmsys5_state *state = space->machine().driver_data<jpmsys5_state>();
269		state->m_muxram[offset]=data;
	276	m_muxram[offset]=data;
270	277	}
271	278
272		static READ16_HANDLER( mux_r )
	279	READ16_MEMBER(jpmsys5_state::mux_r)
273	280	{
274	281	if (offset == 0x81/2)
275		return input_port_read(space->machine(), "DSW");
	282	return input_port_read(machine(), "DSW");
276	283
277	284	return 0xffff;
278	285	}
r14845	r14846
310	317
311	318	static ADDRESS_MAP_START( 68000_map, AS_PROGRAM, 16, jpmsys5_state )
312	319	AM_RANGE(0x000000, 0x01ffff) AM_ROM
313		AM_RANGE(0x01fffe, 0x01ffff) AM_WRITE_LEGACY(rombank_w)
	320	AM_RANGE(0x01fffe, 0x01ffff) AM_WRITE(rombank_w)
314	321	AM_RANGE(0x020000, 0x03ffff) AM_ROMBANK("bank1")
315	322	AM_RANGE(0x040000, 0x043fff) AM_RAM AM_SHARE("nvram")
316	323	AM_RANGE(0x046000, 0x046001) AM_WRITENOP
r14845	r14846
323	330	AM_RANGE(0x046066, 0x046067) AM_WRITENOP
324	331	AM_RANGE(0x046080, 0x046081) AM_DEVREADWRITE8("acia6850_1", acia6850_device, status_read, control_write, 0xff)
325	332	AM_RANGE(0x046082, 0x046083) AM_DEVREADWRITE8("acia6850_1", acia6850_device, data_read, data_write, 0xff)
326		AM_RANGE(0x046084, 0x046085) AM_READ_LEGACY(unk_r) // PIA?
327		AM_RANGE(0x046088, 0x046089) AM_READ_LEGACY(unk_r) // PIA?
	333	AM_RANGE(0x046084, 0x046085) AM_READ(unk_r) // PIA?
	334	AM_RANGE(0x046088, 0x046089) AM_READ(unk_r) // PIA?
328	335	AM_RANGE(0x04608c, 0x04608d) AM_DEVREADWRITE8("acia6850_2", acia6850_device, status_read, control_write, 0xff)
329	336	AM_RANGE(0x04608e, 0x04608f) AM_DEVREADWRITE8("acia6850_2", acia6850_device, data_read, data_write, 0xff)
330	337	AM_RANGE(0x0460a0, 0x0460a3) AM_DEVWRITE8_LEGACY("ym2413", ym2413_w, 0x00ff)
331	338	AM_RANGE(0x0460c0, 0x0460c1) AM_WRITENOP
332		AM_RANGE(0x0460e0, 0x0460e5) AM_WRITE_LEGACY(ramdac_w)
333		AM_RANGE(0x048000, 0x04801f) AM_READWRITE_LEGACY(coins_r, coins_w)
334		AM_RANGE(0x04c000, 0x04c0ff) AM_READ_LEGACY(mux_r) AM_WRITE_LEGACY(mux_w)
	339	AM_RANGE(0x0460e0, 0x0460e5) AM_WRITE(ramdac_w)
	340	AM_RANGE(0x048000, 0x04801f) AM_READWRITE(coins_r, coins_w)
	341	AM_RANGE(0x04c000, 0x04c0ff) AM_READ(mux_r) AM_WRITE(mux_w)
335	342	AM_RANGE(0x04c100, 0x04c105) AM_DEVREADWRITE_LEGACY("upd7759", jpm_upd7759_r, jpm_upd7759_w)
336		AM_RANGE(0x800000, 0xcfffff) AM_READWRITE_LEGACY(sys5_tms34061_r, sys5_tms34061_w)
	343	AM_RANGE(0x800000, 0xcfffff) AM_READWRITE(sys5_tms34061_r, sys5_tms34061_w)
337	344	ADDRESS_MAP_END
338	345
339	346
r14845	r14846
694	701
695	702	static ADDRESS_MAP_START( 68000_awp_map, AS_PROGRAM, 16, jpmsys5_state )
696	703	AM_RANGE(0x000000, 0x01ffff) AM_ROM
697		AM_RANGE(0x01fffe, 0x01ffff) AM_WRITE_LEGACY(rombank_w)
	704	AM_RANGE(0x01fffe, 0x01ffff) AM_WRITE(rombank_w)
698	705	AM_RANGE(0x020000, 0x03ffff) AM_ROMBANK("bank1")
699	706	AM_RANGE(0x040000, 0x043fff) AM_RAM AM_SHARE("nvram")
700	707	AM_RANGE(0x046000, 0x046001) AM_WRITENOP
r14845	r14846
707	714	AM_RANGE(0x046066, 0x046067) AM_WRITENOP
708	715	AM_RANGE(0x046080, 0x046081) AM_DEVREADWRITE8("acia6850_1", acia6850_device, status_read, control_write, 0xff)
709	716	AM_RANGE(0x046082, 0x046083) AM_DEVREADWRITE8("acia6850_1", acia6850_device, data_read, data_write, 0xff)
710		AM_RANGE(0x046084, 0x046085) AM_READ_LEGACY(unk_r) // PIA?
711		AM_RANGE(0x046088, 0x046089) AM_READ_LEGACY(unk_r) // PIA?
	717	AM_RANGE(0x046084, 0x046085) AM_READ(unk_r) // PIA?
	718	AM_RANGE(0x046088, 0x046089) AM_READ(unk_r) // PIA?
712	719	AM_RANGE(0x04608c, 0x04608d) AM_DEVREADWRITE8("acia6850_2", acia6850_device, status_read, control_write, 0xff)
713	720	AM_RANGE(0x04608e, 0x04608f) AM_DEVREADWRITE8("acia6850_2", acia6850_device, data_read, data_write, 0xff)
714	721	AM_RANGE(0x0460a0, 0x0460a3) AM_DEVWRITE8_LEGACY("ym2413", ym2413_w, 0x00ff)
715	722	AM_RANGE(0x0460c0, 0x0460c1) AM_WRITENOP
716		AM_RANGE(0x048000, 0x04801f) AM_READWRITE_LEGACY(coins_r, coins_w)
717		AM_RANGE(0x04c000, 0x04c0ff) AM_READ_LEGACY(mux_r) AM_WRITE_LEGACY(mux_w)
	723	AM_RANGE(0x048000, 0x04801f) AM_READWRITE(coins_r, coins_w)
	724	AM_RANGE(0x04c000, 0x04c0ff) AM_READ(mux_r) AM_WRITE(mux_w)
718	725	AM_RANGE(0x04c100, 0x04c105) AM_DEVREADWRITE_LEGACY("upd7759", jpm_upd7759_r, jpm_upd7759_w)
719	726	ADDRESS_MAP_END
720	727

src/mame/drivers/igs011.c

r14845	r14846
108	108	blitter_t m_blitter;
109	109
110	110	required_device<cpu_device> m_maincpu;
	111	DECLARE_WRITE16_MEMBER(igs011_priority_w);
	112	DECLARE_READ16_MEMBER(igs011_layers_r);
	113	DECLARE_WRITE16_MEMBER(igs011_layers_w);
	114	DECLARE_WRITE16_MEMBER(igs011_palette);
	115	DECLARE_WRITE16_MEMBER(igs011_blit_x_w);
	116	DECLARE_WRITE16_MEMBER(igs011_blit_y_w);
	117	DECLARE_WRITE16_MEMBER(igs011_blit_gfx_lo_w);
	118	DECLARE_WRITE16_MEMBER(igs011_blit_gfx_hi_w);
	119	DECLARE_WRITE16_MEMBER(igs011_blit_w_w);
	120	DECLARE_WRITE16_MEMBER(igs011_blit_h_w);
	121	DECLARE_WRITE16_MEMBER(igs011_blit_depth_w);
	122	DECLARE_WRITE16_MEMBER(igs011_blit_pen_w);
	123	DECLARE_WRITE16_MEMBER(igs011_blit_flags_w);
	124	DECLARE_WRITE16_MEMBER(igs_dips_w);
	125	DECLARE_READ16_MEMBER(igs_3_dips_r);
	126	DECLARE_READ16_MEMBER(igs_4_dips_r);
	127	DECLARE_READ16_MEMBER(igs_5_dips_r);
	128	DECLARE_WRITE16_MEMBER(igs011_prot1_w);
	129	DECLARE_READ16_MEMBER(igs011_prot1_r);
	130	DECLARE_WRITE16_MEMBER(igs011_prot_addr_w);
	131	DECLARE_READ16_MEMBER(igs011_prot_fake_r);
	132	DECLARE_WRITE16_MEMBER(igs011_prot2_reset_w);
	133	DECLARE_READ16_MEMBER(igs011_prot2_reset_r);
	134	DECLARE_WRITE16_MEMBER(igs011_prot2_inc_w);
	135	DECLARE_WRITE16_MEMBER(igs011_prot2_dec_w);
	136	DECLARE_WRITE16_MEMBER(drgnwrld_igs011_prot2_swap_w);
	137	DECLARE_WRITE16_MEMBER(lhb_igs011_prot2_swap_w);
	138	DECLARE_WRITE16_MEMBER(wlcc_igs011_prot2_swap_w);
	139	DECLARE_WRITE16_MEMBER(vbowl_igs011_prot2_swap_w);
	140	DECLARE_READ16_MEMBER(drgnwrldv21_igs011_prot2_r);
	141	DECLARE_READ16_MEMBER(drgnwrldv20j_igs011_prot2_r);
	142	DECLARE_READ16_MEMBER(lhb_igs011_prot2_r);
	143	DECLARE_READ16_MEMBER(dbc_igs011_prot2_r);
	144	DECLARE_READ16_MEMBER(ryukobou_igs011_prot2_r);
	145	DECLARE_READ16_MEMBER(lhb2_igs011_prot2_r);
	146	DECLARE_READ16_MEMBER(vbowl_igs011_prot2_r);
	147	DECLARE_WRITE16_MEMBER(igs012_prot_reset_w);
	148	DECLARE_READ16_MEMBER(igs012_prot_fake_r);
	149	DECLARE_WRITE16_MEMBER(igs012_prot_mode_w);
	150	DECLARE_WRITE16_MEMBER(igs012_prot_inc_w);
	151	DECLARE_WRITE16_MEMBER(igs012_prot_dec_inc_w);
	152	DECLARE_WRITE16_MEMBER(igs012_prot_dec_copy_w);
	153	DECLARE_WRITE16_MEMBER(igs012_prot_copy_w);
	154	DECLARE_WRITE16_MEMBER(igs012_prot_swap_w);
	155	DECLARE_READ16_MEMBER(igs012_prot_r);
	156	DECLARE_WRITE16_MEMBER(drgnwrld_igs003_w);
	157	DECLARE_READ16_MEMBER(drgnwrld_igs003_r);
	158	DECLARE_WRITE16_MEMBER(lhb_inputs_w);
	159	DECLARE_READ16_MEMBER(lhb_inputs_r);
	160	DECLARE_WRITE16_MEMBER(lhb2_igs003_w);
	161	DECLARE_READ16_MEMBER(lhb2_igs003_r);
	162	DECLARE_WRITE16_MEMBER(wlcc_igs003_w);
	163	DECLARE_READ16_MEMBER(wlcc_igs003_r);
	164	DECLARE_WRITE16_MEMBER(xymg_igs003_w);
	165	DECLARE_READ16_MEMBER(xymg_igs003_r);
	166	DECLARE_WRITE16_MEMBER(vbowl_igs003_w);
	167	DECLARE_READ16_MEMBER(vbowl_igs003_r);
	168	DECLARE_WRITE16_MEMBER(lhb_irq_enable_w);
	169	DECLARE_READ16_MEMBER(vbowl_unk_r);
	170	DECLARE_WRITE16_MEMBER(vbowl_pen_hi_w);
	171	DECLARE_WRITE16_MEMBER(vbowl_link_0_w);
	172	DECLARE_WRITE16_MEMBER(vbowl_link_1_w);
	173	DECLARE_WRITE16_MEMBER(vbowl_link_2_w);
	174	DECLARE_WRITE16_MEMBER(vbowl_link_3_w);
	175	UINT16 igs_dips_r(int NUM);
111	176	};
112	177
113	178
r14845	r14846
132	197
133	198
134	199
135		static WRITE16_HANDLER( igs011_priority_w )
	200	WRITE16_MEMBER(igs011_state::igs011_priority_w)
136	201	{
137		igs011_state *state = space->machine().driver_data<igs011_state>();
138		COMBINE_DATA(&state->m_priority);
	202	COMBINE_DATA(&m_priority);
139	203
140		//  logerror("%06x: priority = %02x\n", cpu_get_pc(&space->device()), state->m_priority);
	204	//  logerror("%06x: priority = %02x\n", cpu_get_pc(&space.device()), m_priority);
141	205
142	206	if (data & ~0x7)
143		logerror("%06x: warning, unknown bits written to priority = %02x\n", cpu_get_pc(&space->device()), state->m_priority);
	207	logerror("%06x: warning, unknown bits written to priority = %02x\n", cpu_get_pc(&space.device()), m_priority);
144	208	}
145	209
146	210
r14845	r14846
234	298
235	299	***************************************************************************/
236	300
237		static READ16_HANDLER( igs011_layers_r )
	301	READ16_MEMBER(igs011_state::igs011_layers_r)
238	302	{
239		igs011_state *state = space->machine().driver_data<igs011_state>();
240	303	int layer0 = ((offset & (0x80000/2)) ? 4 : 0) + ((offset & 1) ? 0 : 2);
241	304
242		UINT8 *l0 = state->m_layer[layer0];
243		UINT8 *l1 = state->m_layer[layer0+1];
	305	UINT8 *l0 = m_layer[layer0];
	306	UINT8 *l1 = m_layer[layer0+1];
244	307
245	308	offset >>= 1;
246	309	offset &= 0x1ffff;
r14845	r14846
248	311	return (l0[offset] << 8) | l1[offset];
249	312	}
250	313
251		static WRITE16_HANDLER( igs011_layers_w )
	314	WRITE16_MEMBER(igs011_state::igs011_layers_w)
252	315	{
253		igs011_state *state = space->machine().driver_data<igs011_state>();
254	316	UINT16 word;
255	317
256	318	int layer0 = ((offset & (0x80000/2)) ? 4 : 0) + ((offset & 1) ? 0 : 2);
257	319
258		UINT8 *l0 = state->m_layer[layer0];
259		UINT8 *l1 = state->m_layer[layer0+1];
	320	UINT8 *l0 = m_layer[layer0];
	321	UINT8 *l1 = m_layer[layer0+1];
260	322
261	323	offset >>= 1;
262	324	offset &= 0x1ffff;
r14845	r14846
276	338
277	339	***************************************************************************/
278	340
279		static WRITE16_HANDLER( igs011_palette )
	341	WRITE16_MEMBER(igs011_state::igs011_palette)
280	342	{
281	343	int rgb;
282	344
283		COMBINE_DATA(&space->machine().generic.paletteram.u16[offset]);
	345	COMBINE_DATA(&machine().generic.paletteram.u16[offset]);
284	346
285		rgb = (space->machine().generic.paletteram.u16[offset & 0x7ff] & 0xff) | ((space->machine().generic.paletteram.u16[offset | 0x800] & 0xff) << 8);
286		palette_set_color_rgb(space->machine(),offset & 0x7ff,pal5bit(rgb >> 0),pal5bit(rgb >> 5),pal5bit(rgb >> 10));
	347	rgb = (machine().generic.paletteram.u16[offset & 0x7ff] & 0xff) | ((machine().generic.paletteram.u16[offset | 0x800] & 0xff) << 8);
	348	palette_set_color_rgb(machine(),offset & 0x7ff,pal5bit(rgb >> 0),pal5bit(rgb >> 5),pal5bit(rgb >> 10));
287	349	}
288	350
289	351	/***************************************************************************
r14845	r14846
293	355	***************************************************************************/
294	356
295	357
296		static WRITE16_HANDLER( igs011_blit_x_w )
	358	WRITE16_MEMBER(igs011_state::igs011_blit_x_w)
297	359	{
298		igs011_state *state = space->machine().driver_data<igs011_state>();
299		struct blitter_t &blitter = state->m_blitter;
	360	struct blitter_t &blitter = m_blitter;
300	361	COMBINE_DATA(&blitter.x);
301	362	}
302	363
303		static WRITE16_HANDLER( igs011_blit_y_w )
	364	WRITE16_MEMBER(igs011_state::igs011_blit_y_w)
304	365	{
305		igs011_state *state = space->machine().driver_data<igs011_state>();
306		struct blitter_t &blitter = state->m_blitter;
	366	struct blitter_t &blitter = m_blitter;
307	367	COMBINE_DATA(&blitter.y);
308	368	}
309	369
310		static WRITE16_HANDLER( igs011_blit_gfx_lo_w )
	370	WRITE16_MEMBER(igs011_state::igs011_blit_gfx_lo_w)
311	371	{
312		igs011_state *state = space->machine().driver_data<igs011_state>();
313		struct blitter_t &blitter = state->m_blitter;
	372	struct blitter_t &blitter = m_blitter;
314	373	COMBINE_DATA(&blitter.gfx_lo);
315	374	}
316	375
317		static WRITE16_HANDLER( igs011_blit_gfx_hi_w )
	376	WRITE16_MEMBER(igs011_state::igs011_blit_gfx_hi_w)
318	377	{
319		igs011_state *state = space->machine().driver_data<igs011_state>();
320		struct blitter_t &blitter = state->m_blitter;
	378	struct blitter_t &blitter = m_blitter;
321	379	COMBINE_DATA(&blitter.gfx_hi);
322	380	}
323	381
324		static WRITE16_HANDLER( igs011_blit_w_w )
	382	WRITE16_MEMBER(igs011_state::igs011_blit_w_w)
325	383	{
326		igs011_state *state = space->machine().driver_data<igs011_state>();
327		struct blitter_t &blitter = state->m_blitter;
	384	struct blitter_t &blitter = m_blitter;
328	385	COMBINE_DATA(&blitter.w);
329	386	}
330	387
331		static WRITE16_HANDLER( igs011_blit_h_w )
	388	WRITE16_MEMBER(igs011_state::igs011_blit_h_w)
332	389	{
333		igs011_state *state = space->machine().driver_data<igs011_state>();
334		struct blitter_t &blitter = state->m_blitter;
	390	struct blitter_t &blitter = m_blitter;
335	391	COMBINE_DATA(&blitter.h);
336	392	}
337	393
338		static WRITE16_HANDLER( igs011_blit_depth_w )
	394	WRITE16_MEMBER(igs011_state::igs011_blit_depth_w)
339	395	{
340		igs011_state *state = space->machine().driver_data<igs011_state>();
341		struct blitter_t &blitter = state->m_blitter;
	396	struct blitter_t &blitter = m_blitter;
342	397	COMBINE_DATA(&blitter.depth);
343	398	}
344	399
345		static WRITE16_HANDLER( igs011_blit_pen_w )
	400	WRITE16_MEMBER(igs011_state::igs011_blit_pen_w)
346	401	{
347		igs011_state *state = space->machine().driver_data<igs011_state>();
348		struct blitter_t &blitter = state->m_blitter;
	402	struct blitter_t &blitter = m_blitter;
349	403	COMBINE_DATA(&blitter.pen);
350	404	}
351	405
352	406
353		static WRITE16_HANDLER( igs011_blit_flags_w )
	407	WRITE16_MEMBER(igs011_state::igs011_blit_flags_w)
354	408	{
355		igs011_state *state = space->machine().driver_data<igs011_state>();
356		struct blitter_t &blitter = state->m_blitter;
	409	struct blitter_t &blitter = m_blitter;
357	410	int x, xstart, xend, xinc, flipx;
358	411	int y, ystart, yend, yinc, flipy;
359	412	int depth4, clear, opaque, z;
360	413	UINT8 trans_pen, clear_pen, pen_hi, *dest;
361	414	UINT8 pen = 0;
362	415
363		UINT8 *gfx      =   space->machine().region("blitter")->base();
364		UINT8 *gfx2      =   space->machine().region("blitter_hi")->base();
365		int gfx_size   =   space->machine().region("blitter")->bytes();
366		int gfx2_size   =   space->machine().region("blitter_hi")->bytes();
	416	UINT8 *gfx      =   machine().region("blitter")->base();
	417	UINT8 *gfx2      =   machine().region("blitter_hi")->base();
	418	int gfx_size   =   machine().region("blitter")->bytes();
	419	int gfx2_size   =   machine().region("blitter_hi")->bytes();
367	420
368		const rectangle &clip = space->machine().primary_screen->visible_area();
	421	const rectangle &clip = machine().primary_screen->visible_area();
369	422
370	423	COMBINE_DATA(&blitter.flags);
371	424
372	425	#if LOG_BLITTER
373		logerror("%06x: blit x %03x, y %03x, w %03x, h %03x, gfx %03x%04x, depth %02x, pen %02x, flags %03x\n", cpu_get_pc(&space->device()),
	426	logerror("%06x: blit x %03x, y %03x, w %03x, h %03x, gfx %03x%04x, depth %02x, pen %02x, flags %03x\n", cpu_get_pc(&space.device()),
374	427	blitter.x,blitter.y,blitter.w,blitter.h,blitter.gfx_hi,blitter.gfx_lo,blitter.depth,blitter.pen,blitter.flags);
375	428	#endif
376	429
377		dest   =   state->m_layer[      blitter.flags & 0x0007   ];
	430	dest   =   m_layer[      blitter.flags & 0x0007   ];
378	431	opaque   =          !(blitter.flags & 0x0008);
379	432	clear   =            blitter.flags & 0x0010;
380	433	flipx   =            blitter.flags & 0x0020;
381	434	flipy   =            blitter.flags & 0x0040;
382	435	if               (!(blitter.flags & 0x0400)) return;
383	436
384		pen_hi   =   (state->m_lhb2_pen_hi & 0x07) << 5;
	437	pen_hi   =   (m_lhb2_pen_hi & 0x07) << 5;
385	438
386	439	// pixel address
387	440	z      =   blitter.gfx_lo  + (blitter.gfx_hi << 16);
r14845	r14846
449	502
450	503	#ifdef MAME_DEBUG
451	504	#if 1
452		if (space->machine().input().code_pressed(KEYCODE_Z))
	505	if (machine().input().code_pressed(KEYCODE_Z))
453	506	{   char buf[20];
454	507	sprintf(buf, "%02X%02X",blitter.depth,blitter.flags&0xff);
455	508	//      ui_draw_text(buf, blitter.x, blitter.y);    // crashes mame!
r14845	r14846
473	526	return (state->m_igs_hopper && ((field.machine().primary_screen->frame_number()/5)&1)) ? 0x0000 : 0x0001;
474	527	}
475	528
476		static WRITE16_HANDLER( igs_dips_w )
	529	WRITE16_MEMBER(igs011_state::igs_dips_w)
477	530	{
478		igs011_state *state = space->machine().driver_data<igs011_state>();
479		COMBINE_DATA(&state->m_igs_dips_sel);
	531	COMBINE_DATA(&m_igs_dips_sel);
480	532	}
481	533
482		INLINE UINT16 igs_dips_r(address_space *space, int NUM)
	534	UINT16 igs011_state::igs_dips_r(int NUM)
483	535	{
484		igs011_state *state = space->machine().driver_data<igs011_state>();
485	536	int i;
486	537	UINT16 ret=0;
487	538	static const char *const dipnames[] = { "DSW1", "DSW2", "DSW3", "DSW4", "DSW5" };
488	539
489	540	for (i = 0; i < NUM; i++)
490		if ((~state->m_igs_dips_sel) & (1 << i) )
491		ret = input_port_read(space->machine(), dipnames[i]);
	541	if ((~m_igs_dips_sel) & (1 << i) )
	542	ret = input_port_read(machine(), dipnames[i]);
492	543	/* 0x0100 is blitter busy */
493	544	return   (ret & 0xff) | 0x0000;
494	545	}
495	546
496	547	// Games have 3 to 5 dips
497		static READ16_HANDLER( igs_3_dips_r ) { return igs_dips_r(space, 3); }
498		static READ16_HANDLER( igs_4_dips_r ) { return igs_dips_r(space, 4); }
499		static READ16_HANDLER( igs_5_dips_r ) { return igs_dips_r(space, 5); }
	548	READ16_MEMBER(igs011_state::igs_3_dips_r){ return igs_dips_r(3); }
	549	READ16_MEMBER(igs011_state::igs_4_dips_r){ return igs_dips_r(4); }
	550	READ16_MEMBER(igs011_state::igs_5_dips_r){ return igs_dips_r(5); }
500	551
501	552	/***************************************************************************
502	553
r14845	r14846
903	954
904	955
905	956
906		static WRITE16_HANDLER( igs011_prot1_w )
	957	WRITE16_MEMBER(igs011_state::igs011_prot1_w)
907	958	{
908		igs011_state *state = space->machine().driver_data<igs011_state>();
909	959	offset *= 2;
910	960
911	961	switch (offset)
r14845	r14846
913	963	case 0:   // COPY
914	964	if (ACCESSING_BITS_8_15 && (data & 0xff00) == 0x3300)
915	965	{
916		state->m_prot1 = state->m_prot1_swap;
	966	m_prot1 = m_prot1_swap;
917	967	return;
918	968	}
919	969	break;
r14845	r14846
921	971	case 2:   // INC
922	972	if (ACCESSING_BITS_8_15 && (data & 0xff00) == 0xff00)
923	973	{
924		state->m_prot1++;
	974	m_prot1++;
925	975	return;
926	976	}
927	977	break;
r14845	r14846
929	979	case 4:   // DEC
930	980	if (ACCESSING_BITS_8_15 && (data & 0xff00) == 0xaa00)
931	981	{
932		state->m_prot1--;
	982	m_prot1--;
933	983	return;
934	984	}
935	985	break;
r14845	r14846
938	988	if (ACCESSING_BITS_8_15 && (data & 0xff00) == 0x5500)
939	989	{
940	990	// b1 . (b2|b3) . b2 . (b0&b3)
941		UINT8 x = state->m_prot1;
942		state->m_prot1_swap = (BIT(x,1)<<3) | ((BIT(x,2)|BIT(x,3))<<2) | (BIT(x,2)<<1) | (BIT(x,0)&BIT(x,3));
	991	UINT8 x = m_prot1;
	992	m_prot1_swap = (BIT(x,1)<<3) | ((BIT(x,2)|BIT(x,3))<<2) | (BIT(x,2)<<1) | (BIT(x,0)&BIT(x,3));
943	993	return;
944	994	}
945	995	break;
946	996	}
947	997
948		logerror("%s: warning, unknown igs011_prot1_w( %04x, %04x )\n", space->machine().describe_context(), offset, data);
	998	logerror("%s: warning, unknown igs011_prot1_w( %04x, %04x )\n", machine().describe_context(), offset, data);
949	999	}
950		static READ16_HANDLER( igs011_prot1_r )
	1000	READ16_MEMBER(igs011_state::igs011_prot1_r)
951	1001	{
952		igs011_state *state = space->machine().driver_data<igs011_state>();
953	1002	// !(b1&b2) . 0 . 0 . (b0^b3) . 0 . 0
954		UINT8 x = state->m_prot1;
	1003	UINT8 x = m_prot1;
955	1004	return (((BIT(x,1)&BIT(x,2))^1)<<5) | ((BIT(x,0)^BIT(x,3))<<2);
956	1005	}
957	1006
958	1007
959		static WRITE16_HANDLER( igs011_prot_addr_w )
	1008	WRITE16_MEMBER(igs011_state::igs011_prot_addr_w)
960	1009	{
961		igs011_state *state = space->machine().driver_data<igs011_state>();
962		state->m_prot1 = 0x00;
963		state->m_prot1_swap = 0x00;
	1010	m_prot1 = 0x00;
	1011	m_prot1_swap = 0x00;
964	1012
965		//  state->m_prot2 = 0x00;
	1013	//  m_prot2 = 0x00;
966	1014
967		address_space *sp = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
968		UINT8 *rom = space->machine().region("maincpu")->base();
	1015	address_space *sp = machine().device("maincpu")->memory().space(AS_PROGRAM);
	1016	UINT8 *rom = machine().region("maincpu")->base();
969	1017
970	1018	// Plug previous address range with ROM access
971		sp->install_rom(state->m_prot1_addr + 0, state->m_prot1_addr + 9, rom + state->m_prot1_addr);
	1019	sp->install_rom(m_prot1_addr + 0, m_prot1_addr + 9, rom + m_prot1_addr);
972	1020
973		state->m_prot1_addr = (data << 4) ^ 0x8340;
	1021	m_prot1_addr = (data << 4) ^ 0x8340;
974	1022
975	1023	// Add protection memory range
976		sp->install_legacy_write_handler(state->m_prot1_addr + 0, state->m_prot1_addr + 7, FUNC(igs011_prot1_w));
977		sp->install_legacy_read_handler (state->m_prot1_addr + 8, state->m_prot1_addr + 9, FUNC(igs011_prot1_r));
	1024	sp->install_write_handler(m_prot1_addr + 0, m_prot1_addr + 7, write16_delegate(FUNC(igs011_state::igs011_prot1_w), this));
	1025	sp->install_read_handler (m_prot1_addr + 8, m_prot1_addr + 9, read16_delegate(FUNC(igs011_state::igs011_prot1_r), this));
978	1026	}
979	1027	/*
980		static READ16_HANDLER( igs011_prot_fake_r )
	1028	READ16_MEMBER(igs011_state::igs011_prot_fake_r)
981	1029	{
982		igs011_state *state = space->machine().driver_data<igs011_state>();
983	1030	switch (offset)
984	1031	{
985		case 0: return state->m_prot1;
986		case 1: return state->m_prot1_swap;
987		case 2: return state->m_prot2;
	1032	case 0: return m_prot1;
	1033	case 1: return m_prot1_swap;
	1034	case 2: return m_prot2;
988	1035	}
989	1036	return 0;
990	1037	}
r14845	r14846
998	1045	// Prot2
999	1046
1000	1047	// drgnwrld (33)
1001		static WRITE16_HANDLER( igs011_prot2_reset_w )
	1048	WRITE16_MEMBER(igs011_state::igs011_prot2_reset_w)
1002	1049	{
1003		igs011_state *state = space->machine().driver_data<igs011_state>();
1004		state->m_prot2 = 0x00;
	1050	m_prot2 = 0x00;
1005	1051	}
1006	1052
1007	1053	// wlcc
1008		static READ16_HANDLER( igs011_prot2_reset_r )
	1054	READ16_MEMBER(igs011_state::igs011_prot2_reset_r)
1009	1055	{
1010		igs011_state *state = space->machine().driver_data<igs011_state>();
1011		state->m_prot2 = 0x00;
	1056	m_prot2 = 0x00;
1012	1057	return 0;
1013	1058	}
1014	1059
1015	1060
1016	1061
1017	1062	// lhb2 (55), lhb/dbc/ryukobou (33)
1018		static WRITE16_HANDLER( igs011_prot2_inc_w )
	1063	WRITE16_MEMBER(igs011_state::igs011_prot2_inc_w)
1019	1064	{
1020		igs011_state *state = space->machine().driver_data<igs011_state>();
1021	1065	//  if ( (ACCESSING_BITS_8_15 && (data & 0xff00) == 0x5500) || ((ACCESSING_BITS_0_7 && (data & 0x00ff) == 0x0055)) )
1022	1066	{
1023		state->m_prot2++;
	1067	m_prot2++;
1024	1068	}
1025	1069	//  else
1026		//      logerror("%s: warning, unknown igs011_prot2_inc_w( %04x, %04x )\n", space->machine().describe_context(), offset, data);
	1070	//      logerror("%s: warning, unknown igs011_prot2_inc_w( %04x, %04x )\n", machine().describe_context(), offset, data);
1027	1071	}
1028	1072
1029	1073	// vbowl (33)
1030		static WRITE16_HANDLER( igs011_prot2_dec_w )
	1074	WRITE16_MEMBER(igs011_state::igs011_prot2_dec_w)
1031	1075	{
1032		igs011_state *state = space->machine().driver_data<igs011_state>();
1033	1076	//  if ( (ACCESSING_BITS_8_15 && (data & 0xff00) == 0x3300) || ((ACCESSING_BITS_0_7 && (data & 0x00ff) == 0x0033)) )
1034	1077	{
1035		state->m_prot2--;
	1078	m_prot2--;
1036	1079	}
1037	1080	//  else
1038		//      logerror("%s: warning, unknown igs011_prot2_dec_w( %04x, %04x )\n", space->machine().describe_context(), offset, data);
	1081	//      logerror("%s: warning, unknown igs011_prot2_dec_w( %04x, %04x )\n", machine().describe_context(), offset, data);
1039	1082	}
1040	1083
1041	1084
1042	1085
1043		static WRITE16_HANDLER( drgnwrld_igs011_prot2_swap_w )
	1086	WRITE16_MEMBER(igs011_state::drgnwrld_igs011_prot2_swap_w)
1044	1087	{
1045		igs011_state *state = space->machine().driver_data<igs011_state>();
1046	1088	offset *= 2;
1047	1089
1048	1090	//  if ( (ACCESSING_BITS_8_15 && (data & 0xff00) == 0x3300) || ((ACCESSING_BITS_0_7 && (data & 0x00ff) == 0x0033)) )
1049	1091	{
1050	1092	// (b3&b0) . b2 . (b0|b1) . (b2^!b4) . (!b1^b3)
1051		UINT8 x = state->m_prot2;
1052		state->m_prot2 = ((BIT(x,3)&BIT(x,0))<<4) | (BIT(x,2)<<3) | ((BIT(x,0)|BIT(x,1))<<2) | ((BIT(x,2)^BIT(x,4)^1)<<1) | (BIT(x,1)^1^BIT(x,3));
	1093	UINT8 x = m_prot2;
	1094	m_prot2 = ((BIT(x,3)&BIT(x,0))<<4) | (BIT(x,2)<<3) | ((BIT(x,0)|BIT(x,1))<<2) | ((BIT(x,2)^BIT(x,4)^1)<<1) | (BIT(x,1)^1^BIT(x,3));
1053	1095	}
1054	1096	//  else
1055		//      logerror("%s: warning, unknown igs011_prot2_swap_w( %04x, %04x )\n", space->machine().describe_context(), offset, data);
	1097	//      logerror("%s: warning, unknown igs011_prot2_swap_w( %04x, %04x )\n", machine().describe_context(), offset, data);
1056	1098	}
1057	1099
1058	1100	// lhb, xymg, lhb2
1059		static WRITE16_HANDLER( lhb_igs011_prot2_swap_w )
	1101	WRITE16_MEMBER(igs011_state::lhb_igs011_prot2_swap_w)
1060	1102	{
1061		igs011_state *state = space->machine().driver_data<igs011_state>();
1062	1103	offset *= 2;
1063	1104
1064	1105	//  if ( (ACCESSING_BITS_8_15 && (data & 0xff00) == 0x3300) || ((ACCESSING_BITS_0_7 && (data & 0x00ff) == 0x0033)) )
1065	1106	{
1066	1107	// (!b0|b1) . b2 . (b0&b1)
1067		UINT8 x = state->m_prot2;
1068		state->m_prot2 = (((BIT(x,0)^1)|BIT(x,1))<<2) | (BIT(x,2)<<1) | (BIT(x,0)&BIT(x,1));
	1108	UINT8 x = m_prot2;
	1109	m_prot2 = (((BIT(x,0)^1)|BIT(x,1))<<2) | (BIT(x,2)<<1) | (BIT(x,0)&BIT(x,1));
1069	1110	}
1070	1111	//  else
1071		//      logerror("%s: warning, unknown igs011_prot2_swap_w( %04x, %04x )\n", space->machine().describe_context(), offset, data);
	1112	//      logerror("%s: warning, unknown igs011_prot2_swap_w( %04x, %04x )\n", machine().describe_context(), offset, data);
1072	1113	}
1073	1114
1074	1115	// wlcc
1075		static WRITE16_HANDLER( wlcc_igs011_prot2_swap_w )
	1116	WRITE16_MEMBER(igs011_state::wlcc_igs011_prot2_swap_w)
1076	1117	{
1077		igs011_state *state = space->machine().driver_data<igs011_state>();
1078	1118	offset *= 2;
1079	1119
1080	1120	//  if ( (ACCESSING_BITS_8_15 && (data & 0xff00) == 0x3300) || ((ACCESSING_BITS_0_7 && (data & 0x00ff) == 0x0033)) )
1081	1121	{
1082	1122	// (b3 ^ b2) . (b2 ^ b1) . (b1 ^ b0) . !(b4 ^ b0) . !(b4 ^ b3)
1083		UINT8 x = state->m_prot2;
1084		state->m_prot2 = ((BIT(x,3)^BIT(x,2))<<4) | ((BIT(x,2)^BIT(x,1))<<3) | ((BIT(x,1)^BIT(x,0))<<2) | ((BIT(x,4)^BIT(x,0)^1)<<1) | (BIT(x,4)^BIT(x,3)^1);
	1123	UINT8 x = m_prot2;
	1124	m_prot2 = ((BIT(x,3)^BIT(x,2))<<4) | ((BIT(x,2)^BIT(x,1))<<3) | ((BIT(x,1)^BIT(x,0))<<2) | ((BIT(x,4)^BIT(x,0)^1)<<1) | (BIT(x,4)^BIT(x,3)^1);
1085	1125	}
1086	1126	//  else
1087		//      logerror("%s: warning, unknown igs011_prot2_swap_w( %04x, %04x )\n", space->machine().describe_context(), offset, data);
	1127	//      logerror("%s: warning, unknown igs011_prot2_swap_w( %04x, %04x )\n", machine().describe_context(), offset, data);
1088	1128	}
1089	1129
1090	1130	// vbowl
1091		static WRITE16_HANDLER( vbowl_igs011_prot2_swap_w )
	1131	WRITE16_MEMBER(igs011_state::vbowl_igs011_prot2_swap_w)
1092	1132	{
1093		igs011_state *state = space->machine().driver_data<igs011_state>();
1094	1133	offset *= 2;
1095	1134
1096	1135	//  if ( (ACCESSING_BITS_8_15 && (data & 0xff00) == 0x3300) || ((ACCESSING_BITS_0_7 && (data & 0x00ff) == 0x0033)) )
1097	1136	{
1098	1137	// (b3 ^ b2) . (b2 ^ b1) . (b1 ^ b0) . (b4 ^ b0) . (b4 ^ b3)
1099		UINT8 x = state->m_prot2;
1100		state->m_prot2 = ((BIT(x,3)^BIT(x,2))<<4) | ((BIT(x,2)^BIT(x,1))<<3) | ((BIT(x,1)^BIT(x,0))<<2) | ((BIT(x,4)^BIT(x,0))<<1) | (BIT(x,4)^BIT(x,3));
	1138	UINT8 x = m_prot2;
	1139	m_prot2 = ((BIT(x,3)^BIT(x,2))<<4) | ((BIT(x,2)^BIT(x,1))<<3) | ((BIT(x,1)^BIT(x,0))<<2) | ((BIT(x,4)^BIT(x,0))<<1) | (BIT(x,4)^BIT(x,3));
1101	1140	}
1102	1141	//  else
1103		//      logerror("%s: warning, unknown igs011_prot2_swap_w( %04x, %04x )\n", space->machine().describe_context(), offset, data);
	1142	//      logerror("%s: warning, unknown igs011_prot2_swap_w( %04x, %04x )\n", machine().describe_context(), offset, data);
1104	1143	}
1105	1144
1106	1145
1107	1146
1108	1147	// drgnwrld
1109		static READ16_HANDLER( drgnwrldv21_igs011_prot2_r )
	1148	READ16_MEMBER(igs011_state::drgnwrldv21_igs011_prot2_r)
1110	1149	{
1111		igs011_state *state = space->machine().driver_data<igs011_state>();
1112	1150	// b9 = (!b4) | (!b0 & b2) | (!(b3 ^ b1) & !(!(b4 & b0) | b2))
1113		UINT8 x = state->m_prot2;
	1151	UINT8 x = m_prot2;
1114	1152	UINT8 b9 = (BIT(x,4)^1) | ((BIT(x,0)^1) & BIT(x,2)) | ( (BIT(x,3)^BIT(x,1)^1) & ((((BIT(x,4)^1) & BIT(x,0)) | BIT(x,2))^1) );
1115	1153	return (b9 << 9);
1116	1154	}
1117		static READ16_HANDLER( drgnwrldv20j_igs011_prot2_r )
	1155	READ16_MEMBER(igs011_state::drgnwrldv20j_igs011_prot2_r)
1118	1156	{
1119		igs011_state *state = space->machine().driver_data<igs011_state>();
1120	1157	// b9 = (!b4 | !b0) | !(b3 | b1) | !(b2 & b0)
1121		UINT8 x = state->m_prot2;
	1158	UINT8 x = m_prot2;
1122	1159	UINT8 b9 = ((BIT(x,4)^1) | (BIT(x,0)^1)) | ((BIT(x,3) | BIT(x,1))^1) | ((BIT(x,2) & BIT(x,0))^1);
1123	1160	return (b9 << 9);
1124	1161	}
1125	1162
1126	1163	// lhb, xymg
1127		static READ16_HANDLER( lhb_igs011_prot2_r )
	1164	READ16_MEMBER(igs011_state::lhb_igs011_prot2_r)
1128	1165	{
1129		igs011_state *state = space->machine().driver_data<igs011_state>();
1130	1166	// b9 = !b2 | (b1 & b0)
1131		UINT8 x = state->m_prot2;
	1167	UINT8 x = m_prot2;
1132	1168	UINT8 b9 = (BIT(x,2)^1) | (BIT(x,1) & BIT(x,0));
1133	1169	return (b9 << 9);
1134	1170	}
1135	1171
1136	1172	// dbc
1137		static READ16_HANDLER( dbc_igs011_prot2_r )
	1173	READ16_MEMBER(igs011_state::dbc_igs011_prot2_r)
1138	1174	{
1139		igs011_state *state = space->machine().driver_data<igs011_state>();
1140	1175	// b9 = !b1 | (!b0 & b2)
1141		UINT8 x = state->m_prot2;
	1176	UINT8 x = m_prot2;
1142	1177	UINT8 b9 = (BIT(x,1)^1) | ((BIT(x,0)^1) & BIT(x,2));
1143	1178	return (b9 << 9);
1144	1179	}
1145	1180
1146	1181	// ryukobou
1147		static READ16_HANDLER( ryukobou_igs011_prot2_r )
	1182	READ16_MEMBER(igs011_state::ryukobou_igs011_prot2_r)
1148	1183	{
1149		igs011_state *state = space->machine().driver_data<igs011_state>();
1150	1184	// b9 = (!b1 | b2) & b0
1151		UINT8 x = state->m_prot2;
	1185	UINT8 x = m_prot2;
1152	1186	UINT8 b9 = ((BIT(x,1)^1) | BIT(x,2)) & BIT(x,0);
1153	1187	return (b9 << 9);
1154	1188	}
1155	1189
1156	1190	// lhb2
1157		static READ16_HANDLER( lhb2_igs011_prot2_r )
	1191	READ16_MEMBER(igs011_state::lhb2_igs011_prot2_r)
1158	1192	{
1159		igs011_state *state = space->machine().driver_data<igs011_state>();
1160	1193	// b3 = !b2 | !b1 | b0
1161		UINT8 x = state->m_prot2;
	1194	UINT8 x = m_prot2;
1162	1195	UINT8 b3 = (BIT(x,2)^1) | (BIT(x,1)^1) | BIT(x,0);
1163	1196	return (b3 << 3);
1164	1197	}
1165	1198
1166	1199	// vbowl
1167		static READ16_HANDLER( vbowl_igs011_prot2_r )
	1200	READ16_MEMBER(igs011_state::vbowl_igs011_prot2_r)
1168	1201	{
1169		igs011_state *state = space->machine().driver_data<igs011_state>();
1170		UINT8 x = state->m_prot2;
	1202	UINT8 x = m_prot2;
1171	1203	UINT8 b9 = ((BIT(x,4)^1) & (BIT(x,3)^1)) | ((BIT(x,2) & BIT(x,1))^1) | ((BIT(x,4) | BIT(x,0))^1);
1172	1204	return (b9 << 9);
1173	1205	}
r14845	r14846
1194	1226	***************************************************************************/
1195	1227
1196	1228
1197		static WRITE16_HANDLER( igs012_prot_reset_w )
	1229	WRITE16_MEMBER(igs011_state::igs012_prot_reset_w)
1198	1230	{
1199		igs011_state *state = space->machine().driver_data<igs011_state>();
1200		state->m_igs012_prot = 0x00;
1201		state->m_igs012_prot_swap = 0x00;
	1231	m_igs012_prot = 0x00;
	1232	m_igs012_prot_swap = 0x00;
1202	1233
1203		state->m_igs012_prot_mode = 0;
	1234	m_igs012_prot_mode = 0;
1204	1235	}
1205	1236	/*
1206		static READ16_HANDLER( igs012_prot_fake_r )
	1237	READ16_MEMBER(igs011_state::igs012_prot_fake_r)
1207	1238	{
1208		igs011_state *state = space->machine().driver_data<igs011_state>();
1209	1239	switch (offset)
1210	1240	{
1211		case 0: return state->m_igs012_prot;
1212		case 1: return state->m_igs012_prot_swap;
1213		case 2: return state->m_igs012_prot_mode;
	1241	case 0: return m_igs012_prot;
	1242	case 1: return m_igs012_prot_swap;
	1243	case 2: return m_igs012_prot_mode;
1214	1244	}
1215	1245	return 0;
1216	1246	}
1217	1247	*/
1218	1248
1219	1249	// Macro that checks whether the current mode and data byte written match the arguments
1220		#define MODE_AND_DATA(_MODE,_DATA)   (state->m_igs012_prot_mode == (_MODE) && ( (ACCESSING_BITS_8_15 && (data & 0xff00) == ((_DATA)<<8)) || (ACCESSING_BITS_0_7 && ((data & 0x00ff) == (_DATA))) ) )
	1250	#define MODE_AND_DATA(_MODE,_DATA)   (m_igs012_prot_mode == (_MODE) && ( (ACCESSING_BITS_8_15 && (data & 0xff00) == ((_DATA)<<8)) || (ACCESSING_BITS_0_7 && ((data & 0x00ff) == (_DATA))) ) )
1221	1251
1222		static WRITE16_HANDLER( igs012_prot_mode_w )
	1252	WRITE16_MEMBER(igs011_state::igs012_prot_mode_w)
1223	1253	{
1224		igs011_state *state = space->machine().driver_data<igs011_state>();
1225	1254	if ( MODE_AND_DATA(0, 0xcc) || MODE_AND_DATA(1, 0xdd) )
1226	1255	{
1227		state->m_igs012_prot_mode = state->m_igs012_prot_mode ^ 1;
	1256	m_igs012_prot_mode = m_igs012_prot_mode ^ 1;
1228	1257	}
1229	1258	else
1230		logerror("%s: warning, unknown igs012_prot_mode_w( %04x, %04x ), mode %x\n", space->machine().describe_context(), offset, data, state->m_igs012_prot_mode);
	1259	logerror("%s: warning, unknown igs012_prot_mode_w( %04x, %04x ), mode %x\n", machine().describe_context(), offset, data, m_igs012_prot_mode);
1231	1260	}
1232	1261
1233		static WRITE16_HANDLER( igs012_prot_inc_w )
	1262	WRITE16_MEMBER(igs011_state::igs012_prot_inc_w)
1234	1263	{
1235		igs011_state *state = space->machine().driver_data<igs011_state>();
1236	1264	if ( MODE_AND_DATA(0, 0xff) )
1237	1265	{
1238		state->m_igs012_prot = (state->m_igs012_prot + 1) & 0x1f;
	1266	m_igs012_prot = (m_igs012_prot + 1) & 0x1f;
1239	1267	}
1240	1268	else
1241		logerror("%s: warning, unknown igs012_prot_inc_w( %04x, %04x ), mode %x\n", space->machine().describe_context(), offset, data, state->m_igs012_prot_mode);
	1269	logerror("%s: warning, unknown igs012_prot_inc_w( %04x, %04x ), mode %x\n", machine().describe_context(), offset, data, m_igs012_prot_mode);
1242	1270	}
1243	1271
1244		static WRITE16_HANDLER( igs012_prot_dec_inc_w )
	1272	WRITE16_MEMBER(igs011_state::igs012_prot_dec_inc_w)
1245	1273	{
1246		igs011_state *state = space->machine().driver_data<igs011_state>();
1247	1274	if ( MODE_AND_DATA(0, 0xaa) )
1248	1275	{
1249		state->m_igs012_prot = (state->m_igs012_prot - 1) & 0x1f;
	1276	m_igs012_prot = (m_igs012_prot - 1) & 0x1f;
1250	1277	}
1251	1278	else if ( MODE_AND_DATA(1, 0xfa) )
1252	1279	{
1253		state->m_igs012_prot = (state->m_igs012_prot + 1) & 0x1f;
	1280	m_igs012_prot = (m_igs012_prot + 1) & 0x1f;
1254	1281	}
1255	1282	else
1256		logerror("%s: warning, unknown igs012_prot_dec_inc_w( %04x, %04x ), mode %x\n", space->machine().describe_context(), offset, data, state->m_igs012_prot_mode);
	1283	logerror("%s: warning, unknown igs012_prot_dec_inc_w( %04x, %04x ), mode %x\n", machine().describe_context(), offset, data, m_igs012_prot_mode);
1257	1284	}
1258	1285
1259		static WRITE16_HANDLER( igs012_prot_dec_copy_w )
	1286	WRITE16_MEMBER(igs011_state::igs012_prot_dec_copy_w)
1260	1287	{
1261		igs011_state *state = space->machine().driver_data<igs011_state>();
1262	1288	if ( MODE_AND_DATA(0, 0x33) )
1263	1289	{
1264		state->m_igs012_prot = state->m_igs012_prot_swap;
	1290	m_igs012_prot = m_igs012_prot_swap;
1265	1291	}
1266	1292	else if ( MODE_AND_DATA(1, 0x5a) )
1267	1293	{
1268		state->m_igs012_prot = (state->m_igs012_prot - 1) & 0x1f;
	1294	m_igs012_prot = (m_igs012_prot - 1) & 0x1f;
1269	1295	}
1270	1296	else
1271		logerror("%s: warning, unknown igs012_prot_dec_copy_w( %04x, %04x ), mode %x\n", space->machine().describe_context(), offset, data, state->m_igs012_prot_mode);
	1297	logerror("%s: warning, unknown igs012_prot_dec_copy_w( %04x, %04x ), mode %x\n", machine().describe_context(), offset, data, m_igs012_prot_mode);
1272	1298	}
1273	1299
1274		static WRITE16_HANDLER( igs012_prot_copy_w )
	1300	WRITE16_MEMBER(igs011_state::igs012_prot_copy_w)
1275	1301	{
1276		igs011_state *state = space->machine().driver_data<igs011_state>();
1277	1302	if ( MODE_AND_DATA(1, 0x22) )
1278	1303	{
1279		state->m_igs012_prot = state->m_igs012_prot_swap;
	1304	m_igs012_prot = m_igs012_prot_swap;
1280	1305	}
1281	1306	else
1282		logerror("%s: warning, unknown igs012_prot_copy_w( %04x, %04x ), mode %x\n", space->machine().describe_context(), offset, data, state->m_igs012_prot_mode);
	1307	logerror("%s: warning, unknown igs012_prot_copy_w( %04x, %04x ), mode %x\n", machine().describe_context(), offset, data, m_igs012_prot_mode);
1283	1308	}
1284	1309
1285		static WRITE16_HANDLER( igs012_prot_swap_w )
	1310	WRITE16_MEMBER(igs011_state::igs012_prot_swap_w)
1286	1311	{
1287		igs011_state *state = space->machine().driver_data<igs011_state>();
1288	1312	if ( MODE_AND_DATA(0, 0x55) || MODE_AND_DATA(1, 0xa5) )
1289	1313	{
1290	1314	// !(3 | 1)..(2 & 1)..(3 ^ 0)..(!2)
1291		UINT8 x = state->m_igs012_prot;
1292		state->m_igs012_prot_swap = (((BIT(x,3)|BIT(x,1))^1)<<3) | ((BIT(x,2)&BIT(x,1))<<2) | ((BIT(x,3)^BIT(x,0))<<1) | (BIT(x,2)^1);
	1315	UINT8 x = m_igs012_prot;
	1316	m_igs012_prot_swap = (((BIT(x,3)|BIT(x,1))^1)<<3) | ((BIT(x,2)&BIT(x,1))<<2) | ((BIT(x,3)^BIT(x,0))<<1) | (BIT(x,2)^1);
1293	1317	}
1294	1318	else
1295		logerror("%s: warning, unknown igs012_prot_swap_w( %04x, %04x ), mode %x\n", space->machine().describe_context(), offset, data, state->m_igs012_prot_mode);
	1319	logerror("%s: warning, unknown igs012_prot_swap_w( %04x, %04x ), mode %x\n", machine().describe_context(), offset, data, m_igs012_prot_mode);
1296	1320	}
1297	1321
1298		static READ16_HANDLER( igs012_prot_r )
	1322	READ16_MEMBER(igs011_state::igs012_prot_r)
1299	1323	{
1300		igs011_state *state = space->machine().driver_data<igs011_state>();
1301	1324	// FIXME: mode 0 and mode 1 are mapped to different memory ranges
1302		UINT8 x = state->m_igs012_prot;
	1325	UINT8 x = m_igs012_prot;
1303	1326
1304	1327	UINT8 b1 = (BIT(x,3) | BIT(x,1))^1;
1305	1328	UINT8 b0 = BIT(x,3) ^ BIT(x,0);
r14845	r14846
1314	1337	***************************************************************************/
1315	1338
1316	1339
1317		static WRITE16_HANDLER( drgnwrld_igs003_w )
	1340	WRITE16_MEMBER(igs011_state::drgnwrld_igs003_w)
1318	1341	{
1319		igs011_state *state = space->machine().driver_data<igs011_state>();
1320		COMBINE_DATA(&state->m_igs003_reg[offset]);
	1342	COMBINE_DATA(&m_igs003_reg[offset]);
1321	1343
1322	1344	if (offset == 0)
1323	1345	return;
1324	1346
1325		switch(state->m_igs003_reg[0])
	1347	switch(m_igs003_reg[0])
1326	1348	{
1327	1349
1328	1350	case 0x00:
1329	1351	if (ACCESSING_BITS_0_7)
1330		coin_counter_w(space->machine(), 0,data & 2);
	1352	coin_counter_w(machine(), 0,data & 2);
1331	1353
1332	1354	if (data & ~0x2)
1333		logerror("%06x: warning, unknown bits written in coin counter = %02x\n", cpu_get_pc(&space->device()), data);
	1355	logerror("%06x: warning, unknown bits written in coin counter = %02x\n", cpu_get_pc(&space.device()), data);
1334	1356
1335	1357	break;
1336	1358
r14845	r14846
1342	1364	//      case 0x05:
1343	1365
1344	1366	default:
1345		//          popmessage("igs003 %x <- %04x",state->m_igs003_reg[0],data);
1346		logerror("%06x: warning, writing to igs003_reg %02x = %02x\n", cpu_get_pc(&space->device()), state->m_igs003_reg[0], data);
	1367	//          popmessage("igs003 %x <- %04x",m_igs003_reg[0],data);
	1368	logerror("%06x: warning, writing to igs003_reg %02x = %02x\n", cpu_get_pc(&space.device()), m_igs003_reg[0], data);
1347	1369	}
1348	1370	}
1349		static READ16_HANDLER( drgnwrld_igs003_r )
	1371	READ16_MEMBER(igs011_state::drgnwrld_igs003_r)
1350	1372	{
1351		igs011_state *state = space->machine().driver_data<igs011_state>();
1352		switch(state->m_igs003_reg[0])
	1373	switch(m_igs003_reg[0])
1353	1374	{
1354		case 0x00:   return input_port_read(space->machine(), "IN0");
1355		case 0x01:   return input_port_read(space->machine(), "IN1");
1356		case 0x02:   return input_port_read(space->machine(), "IN2");
	1375	case 0x00:   return input_port_read(machine(), "IN0");
	1376	case 0x01:   return input_port_read(machine(), "IN1");
	1377	case 0x02:   return input_port_read(machine(), "IN2");
1357	1378
1358	1379	case 0x20:   return 0x49;
1359	1380	case 0x21:   return 0x47;
r14845	r14846
1378	1399	case 0x34:   return 0x32;
1379	1400
1380	1401	default:
1381		logerror("%06x: warning, reading with igs003_reg = %02x\n", cpu_get_pc(&space->device()), state->m_igs003_reg[0]);
	1402	logerror("%06x: warning, reading with igs003_reg = %02x\n", cpu_get_pc(&space.device()), m_igs003_reg[0]);
1382	1403	}
1383	1404
1384	1405	return 0;
r14845	r14846
1386	1407
1387	1408
1388	1409
1389		static WRITE16_HANDLER( lhb_inputs_w )
	1410	WRITE16_MEMBER(igs011_state::lhb_inputs_w)
1390	1411	{
1391		igs011_state *state = space->machine().driver_data<igs011_state>();
1392		COMBINE_DATA(&state->m_igs_input_sel);
	1412	COMBINE_DATA(&m_igs_input_sel);
1393	1413
1394	1414	if (ACCESSING_BITS_0_7)
1395	1415	{
1396		coin_counter_w(space->machine(), 0,   data & 0x20   );
	1416	coin_counter_w(machine(), 0,   data & 0x20   );
1397	1417	//  coin out        data & 0x40
1398		state->m_igs_hopper      =   data & 0x80;
	1418	m_igs_hopper      =   data & 0x80;
1399	1419	}
1400	1420
1401		if ( state->m_igs_input_sel & (~0xff) )
1402		logerror("%06x: warning, unknown bits written in igs_input_sel = %02x\n", cpu_get_pc(&space->device()), state->m_igs_input_sel);
	1421	if ( m_igs_input_sel & (~0xff) )
	1422	logerror("%06x: warning, unknown bits written in igs_input_sel = %02x\n", cpu_get_pc(&space.device()), m_igs_input_sel);
1403	1423
1404		//  popmessage("sel2 %02x",state->m_igs_input_sel&~0x1f);
	1424	//  popmessage("sel2 %02x",m_igs_input_sel&~0x1f);
1405	1425	}
1406		static READ16_HANDLER( lhb_inputs_r )
	1426	READ16_MEMBER(igs011_state::lhb_inputs_r)
1407	1427	{
1408		igs011_state *state = space->machine().driver_data<igs011_state>();
1409	1428	switch(offset)
1410	1429	{
1411		case 0:      return state->m_igs_input_sel;
	1430	case 0:      return m_igs_input_sel;
1412	1431
1413	1432	case 1:
1414		if (~state->m_igs_input_sel & 0x01)   return input_port_read(space->machine(), "KEY0");
1415		if (~state->m_igs_input_sel & 0x02)   return input_port_read(space->machine(), "KEY1");
1416		if (~state->m_igs_input_sel & 0x04)   return input_port_read(space->machine(), "KEY2");
1417		if (~state->m_igs_input_sel & 0x08)   return input_port_read(space->machine(), "KEY3");
1418		if (~state->m_igs_input_sel & 0x10)   return input_port_read(space->machine(), "KEY4");
	1433	if (~m_igs_input_sel & 0x01)   return input_port_read(machine(), "KEY0");
	1434	if (~m_igs_input_sel & 0x02)   return input_port_read(machine(), "KEY1");
	1435	if (~m_igs_input_sel & 0x04)   return input_port_read(machine(), "KEY2");
	1436	if (~m_igs_input_sel & 0x08)   return input_port_read(machine(), "KEY3");
	1437	if (~m_igs_input_sel & 0x10)   return input_port_read(machine(), "KEY4");
1419	1438
1420		logerror("%06x: warning, reading with igs_input_sel = %02x\n", cpu_get_pc(&space->device()), state->m_igs_input_sel);
	1439	logerror("%06x: warning, reading with igs_input_sel = %02x\n", cpu_get_pc(&space.device()), m_igs_input_sel);
1421	1440	break;
1422	1441	}
1423	1442	return 0;
r14845	r14846
1425	1444
1426	1445
1427	1446
1428		static WRITE16_HANDLER( lhb2_igs003_w )
	1447	WRITE16_MEMBER(igs011_state::lhb2_igs003_w)
1429	1448	{
1430		igs011_state *state = space->machine().driver_data<igs011_state>();
1431		COMBINE_DATA(&state->m_igs003_reg[offset]);
	1449	COMBINE_DATA(&m_igs003_reg[offset]);
1432	1450
1433	1451	if (offset == 0)
1434	1452	return;
1435	1453
1436		switch(state->m_igs003_reg[0])
	1454	switch(m_igs003_reg[0])
1437	1455	{
1438	1456	case 0x00:
1439		COMBINE_DATA(&state->m_igs_input_sel);
	1457	COMBINE_DATA(&m_igs_input_sel);
1440	1458
1441	1459	if (ACCESSING_BITS_0_7)
1442	1460	{
1443		coin_counter_w(space->machine(), 0,   data & 0x20);
	1461	coin_counter_w(machine(), 0,   data & 0x20);
1444	1462	//  coin out        data & 0x40
1445		state->m_igs_hopper      =   data & 0x80;
	1463	m_igs_hopper      =   data & 0x80;
1446	1464	}
1447	1465
1448		if ( state->m_igs_input_sel & ~0x7f )
1449		logerror("%06x: warning, unknown bits written in igs_input_sel = %02x\n", cpu_get_pc(&space->device()), state->m_igs_input_sel);
	1466	if ( m_igs_input_sel & ~0x7f )
	1467	logerror("%06x: warning, unknown bits written in igs_input_sel = %02x\n", cpu_get_pc(&space.device()), m_igs_input_sel);
1450	1468
1451		//          popmessage("sel2 %02x",state->m_igs_input_sel&~0x1f);
	1469	//          popmessage("sel2 %02x",m_igs_input_sel&~0x1f);
1452	1470	break;
1453	1471
1454	1472	case 0x02:
1455	1473	if (ACCESSING_BITS_0_7)
1456	1474	{
1457		state->m_lhb2_pen_hi = data & 0x07;
	1475	m_lhb2_pen_hi = data & 0x07;
1458	1476
1459		okim6295_device *oki = space->machine().device<okim6295_device>("oki");
	1477	okim6295_device *oki = machine().device<okim6295_device>("oki");
1460	1478	oki->set_bank_base((data & 0x08) ? 0x40000 : 0);
1461	1479	}
1462	1480
1463		if ( state->m_lhb2_pen_hi & ~0xf )
1464		logerror("%06x: warning, unknown bits written in lhb2_pen_hi = %02x\n", cpu_get_pc(&space->device()), state->m_lhb2_pen_hi);
	1481	if ( m_lhb2_pen_hi & ~0xf )
	1482	logerror("%06x: warning, unknown bits written in lhb2_pen_hi = %02x\n", cpu_get_pc(&space.device()), m_lhb2_pen_hi);
1465	1483
1466		//          popmessage("oki %02x",state->m_lhb2_pen_hi & 0x08);
	1484	//          popmessage("oki %02x",m_lhb2_pen_hi & 0x08);
1467	1485	break;
1468	1486
1469	1487	default:
1470		logerror("%06x: warning, writing to igs003_reg %02x = %02x\n", cpu_get_pc(&space->device()), state->m_igs003_reg[0], data);
	1488	logerror("%06x: warning, writing to igs003_reg %02x = %02x\n", cpu_get_pc(&space.device()), m_igs003_reg[0], data);
1471	1489	}
1472	1490	}
1473		static READ16_HANDLER( lhb2_igs003_r )
	1491	READ16_MEMBER(igs011_state::lhb2_igs003_r)
1474	1492	{
1475		igs011_state *state = space->machine().driver_data<igs011_state>();
1476		switch(state->m_igs003_reg[0])
	1493	switch(m_igs003_reg[0])
1477	1494	{
1478	1495	case 0x01:
1479		if (~state->m_igs_input_sel & 0x01)   return input_port_read(space->machine(), "KEY0");
1480		if (~state->m_igs_input_sel & 0x02)   return input_port_read(space->machine(), "KEY1");
1481		if (~state->m_igs_input_sel & 0x04)   return input_port_read(space->machine(), "KEY2");
1482		if (~state->m_igs_input_sel & 0x08)   return input_port_read(space->machine(), "KEY3");
1483		if (~state->m_igs_input_sel & 0x10)   return input_port_read(space->machine(), "KEY4");
	1496	if (~m_igs_input_sel & 0x01)   return input_port_read(machine(), "KEY0");
	1497	if (~m_igs_input_sel & 0x02)   return input_port_read(machine(), "KEY1");
	1498	if (~m_igs_input_sel & 0x04)   return input_port_read(machine(), "KEY2");
	1499	if (~m_igs_input_sel & 0x08)   return input_port_read(machine(), "KEY3");
	1500	if (~m_igs_input_sel & 0x10)   return input_port_read(machine(), "KEY4");
1484	1501	/* fall through */
1485	1502	default:
1486		logerror("%06x: warning, reading with igs003_reg = %02x\n", cpu_get_pc(&space->device()), state->m_igs003_reg[0]);
	1503	logerror("%06x: warning, reading with igs003_reg = %02x\n", cpu_get_pc(&space.device()), m_igs003_reg[0]);
1487	1504	break;
1488	1505
1489	1506	//      case 0x03:
r14845	r14846
1521	1538
1522	1539
1523	1540
1524		static WRITE16_HANDLER( wlcc_igs003_w )
	1541	WRITE16_MEMBER(igs011_state::wlcc_igs003_w)
1525	1542	{
1526		igs011_state *state = space->machine().driver_data<igs011_state>();
1527		COMBINE_DATA(&state->m_igs003_reg[offset]);
	1543	COMBINE_DATA(&m_igs003_reg[offset]);
1528	1544
1529	1545	if (offset == 0)
1530	1546	return;
1531	1547
1532		switch(state->m_igs003_reg[0])
	1548	switch(m_igs003_reg[0])
1533	1549	{
1534	1550	case 0x02:
1535	1551	if (ACCESSING_BITS_0_7)
1536	1552	{
1537		coin_counter_w(space->machine(), 0,   data & 0x01);
	1553	coin_counter_w(machine(), 0,   data & 0x01);
1538	1554	//  coin out        data & 0x02
1539	1555
1540		okim6295_device *oki = space->machine().device<okim6295_device>("oki");
	1556	okim6295_device *oki = machine().device<okim6295_device>("oki");
1541	1557	oki->set_bank_base((data & 0x10) ? 0x40000 : 0);
1542		state->m_igs_hopper      =   data & 0x20;
	1558	m_igs_hopper      =   data & 0x20;
1543	1559	}
1544	1560
1545	1561	if (data & ~0x33)
1546		logerror("%06x: warning, unknown bits written in coin counter = %02x\n", cpu_get_pc(&space->device()), data);
	1562	logerror("%06x: warning, unknown bits written in coin counter = %02x\n", cpu_get_pc(&space.device()), data);
1547	1563
1548	1564	//          popmessage("coin %02x",data);
1549	1565	break;
1550	1566
1551	1567	default:
1552		logerror("%06x: warning, writing to igs003_reg %02x = %02x\n", cpu_get_pc(&space->device()), state->m_igs003_reg[0], data);
	1568	logerror("%06x: warning, writing to igs003_reg %02x = %02x\n", cpu_get_pc(&space.device()), m_igs003_reg[0], data);
1553	1569	}
1554	1570	}
1555		static READ16_HANDLER( wlcc_igs003_r )
	1571	READ16_MEMBER(igs011_state::wlcc_igs003_r)
1556	1572	{
1557		igs011_state *state = space->machine().driver_data<igs011_state>();
1558		switch(state->m_igs003_reg[0])
	1573	switch(m_igs003_reg[0])
1559	1574	{
1560		case 0x00:   return input_port_read(space->machine(), "IN0");
	1575	case 0x00:   return input_port_read(machine(), "IN0");
1561	1576
1562	1577	case 0x20:   return 0x49;
1563	1578	case 0x21:   return 0x47;
r14845	r14846
1582	1597	case 0x34:   return 0x32;
1583	1598
1584	1599	default:
1585		logerror("%06x: warning, reading with igs003_reg = %02x\n", cpu_get_pc(&space->device()), state->m_igs003_reg[0]);
	1600	logerror("%06x: warning, reading with igs003_reg = %02x\n", cpu_get_pc(&space.device()), m_igs003_reg[0]);
1586	1601	}
1587	1602
1588	1603	return 0;
r14845	r14846
1590	1605
1591	1606
1592	1607
1593		static WRITE16_HANDLER( xymg_igs003_w )
	1608	WRITE16_MEMBER(igs011_state::xymg_igs003_w)
1594	1609	{
1595		igs011_state *state = space->machine().driver_data<igs011_state>();
1596		COMBINE_DATA(&state->m_igs003_reg[offset]);
	1610	COMBINE_DATA(&m_igs003_reg[offset]);
1597	1611
1598	1612	if (offset == 0)
1599	1613	return;
1600	1614
1601		switch(state->m_igs003_reg[0])
	1615	switch(m_igs003_reg[0])
1602	1616	{
1603	1617	case 0x01:
1604		COMBINE_DATA(&state->m_igs_input_sel);
	1618	COMBINE_DATA(&m_igs_input_sel);
1605	1619
1606	1620	if (ACCESSING_BITS_0_7)
1607	1621	{
1608		coin_counter_w(space->machine(), 0,   data & 0x20);
	1622	coin_counter_w(machine(), 0,   data & 0x20);
1609	1623	//  coin out        data & 0x40
1610		state->m_igs_hopper      =   data & 0x80;
	1624	m_igs_hopper      =   data & 0x80;
1611	1625	}
1612	1626
1613		if ( state->m_igs_input_sel & 0x40 )
1614		logerror("%06x: warning, unknown bits written in igs_input_sel = %02x\n", cpu_get_pc(&space->device()), state->m_igs_input_sel);
	1627	if ( m_igs_input_sel & 0x40 )
	1628	logerror("%06x: warning, unknown bits written in igs_input_sel = %02x\n", cpu_get_pc(&space.device()), m_igs_input_sel);
1615	1629
1616		//          popmessage("sel2 %02x",state->m_igs_input_sel&~0x1f);
	1630	//          popmessage("sel2 %02x",m_igs_input_sel&~0x1f);
1617	1631	break;
1618	1632
1619	1633	default:
1620		logerror("%06x: warning, writing to igs003_reg %02x = %02x\n", cpu_get_pc(&space->device()), state->m_igs003_reg[0], data);
	1634	logerror("%06x: warning, writing to igs003_reg %02x = %02x\n", cpu_get_pc(&space.device()), m_igs003_reg[0], data);
1621	1635	}
1622	1636	}
1623		static READ16_HANDLER( xymg_igs003_r )
	1637	READ16_MEMBER(igs011_state::xymg_igs003_r)
1624	1638	{
1625		igs011_state *state = space->machine().driver_data<igs011_state>();
1626		switch(state->m_igs003_reg[0])
	1639	switch(m_igs003_reg[0])
1627	1640	{
1628		case 0x00:   return input_port_read(space->machine(), "COIN");
	1641	case 0x00:   return input_port_read(machine(), "COIN");
1629	1642
1630	1643	case 0x02:
1631		if (~state->m_igs_input_sel & 0x01)   return input_port_read(space->machine(), "KEY0");
1632		if (~state->m_igs_input_sel & 0x02)   return input_port_read(space->machine(), "KEY1");
1633		if (~state->m_igs_input_sel & 0x04)   return input_port_read(space->machine(), "KEY2");
1634		if (~state->m_igs_input_sel & 0x08)   return input_port_read(space->machine(), "KEY3");
1635		if (~state->m_igs_input_sel & 0x10)   return input_port_read(space->machine(), "KEY4");
	1644	if (~m_igs_input_sel & 0x01)   return input_port_read(machine(), "KEY0");
	1645	if (~m_igs_input_sel & 0x02)   return input_port_read(machine(), "KEY1");
	1646	if (~m_igs_input_sel & 0x04)   return input_port_read(machine(), "KEY2");
	1647	if (~m_igs_input_sel & 0x08)   return input_port_read(machine(), "KEY3");
	1648	if (~m_igs_input_sel & 0x10)   return input_port_read(machine(), "KEY4");
1636	1649	/* fall through */
1637	1650
1638	1651	case 0x20:   return 0x49;
r14845	r14846
1658	1671	case 0x34:   return 0x32;
1659	1672
1660	1673	default:
1661		logerror("%06x: warning, reading with igs003_reg = %02x\n", cpu_get_pc(&space->device()), state->m_igs003_reg[0]);
	1674	logerror("%06x: warning, reading with igs003_reg = %02x\n", cpu_get_pc(&space.device()), m_igs003_reg[0]);
1662	1675	break;
1663	1676	}
1664	1677
r14845	r14846
1667	1680
1668	1681
1669	1682
1670		static WRITE16_HANDLER( vbowl_igs003_w )
	1683	WRITE16_MEMBER(igs011_state::vbowl_igs003_w)
1671	1684	{
1672		igs011_state *state = space->machine().driver_data<igs011_state>();
1673		COMBINE_DATA(&state->m_igs003_reg[offset]);
	1685	COMBINE_DATA(&m_igs003_reg[offset]);
1674	1686
1675	1687	if (offset == 0)
1676	1688	return;
1677	1689
1678		switch(state->m_igs003_reg[0])
	1690	switch(m_igs003_reg[0])
1679	1691	{
1680	1692	case 0x02:
1681	1693	if (ACCESSING_BITS_0_7)
1682	1694	{
1683		coin_counter_w(space->machine(), 0, data & 1);
1684		coin_counter_w(space->machine(), 1, data & 2);
	1695	coin_counter_w(machine(), 0, data & 1);
	1696	coin_counter_w(machine(), 1, data & 2);
1685	1697	}
1686	1698
1687	1699	if (data & ~0x3)
1688		logerror("%06x: warning, unknown bits written in coin counter = %02x\n", cpu_get_pc(&space->device()), data);
	1700	logerror("%06x: warning, unknown bits written in coin counter = %02x\n", cpu_get_pc(&space.device()), data);
1689	1701
1690	1702	break;
1691	1703
1692	1704	default:
1693		//          popmessage("igs003 %x <- %04x",state->m_igs003_reg[0],data);
1694		logerror("%06x: warning, writing to igs003_reg %02x = %02x\n", cpu_get_pc(&space->device()), state->m_igs003_reg[0], data);
	1705	//          popmessage("igs003 %x <- %04x",m_igs003_reg[0],data);
	1706	logerror("%06x: warning, writing to igs003_reg %02x = %02x\n", cpu_get_pc(&space.device()), m_igs003_reg[0], data);
1695	1707	}
1696	1708	}
1697		static READ16_HANDLER( vbowl_igs003_r )
	1709	READ16_MEMBER(igs011_state::vbowl_igs003_r)
1698	1710	{
1699		igs011_state *state = space->machine().driver_data<igs011_state>();
1700		switch(state->m_igs003_reg[0])
	1711	switch(m_igs003_reg[0])
1701	1712	{
1702		case 0x00:   return input_port_read(space->machine(), "IN0");
1703		case 0x01:   return input_port_read(space->machine(), "IN1");
	1713	case 0x00:   return input_port_read(machine(), "IN0");
	1714	case 0x01:   return input_port_read(machine(), "IN1");
1704	1715
1705	1716	//      case 0x03:
1706	1717	//          return 0xff;    // parametric bitswaps?
r14845	r14846
1728	1739	case 0x34:   return 0x32;
1729	1740
1730	1741	default:
1731		logerror("%06x: warning, reading with igs003_reg = %02x\n", cpu_get_pc(&space->device()), state->m_igs003_reg[0]);
	1742	logerror("%06x: warning, reading with igs003_reg = %02x\n", cpu_get_pc(&space.device()), m_igs003_reg[0]);
1732	1743	}
1733	1744
1734	1745	return 0;
r14845	r14846
1800	1811
1801	1812	drgnwrld_type2_decrypt(machine);
1802	1813	drgnwrld_gfx_decrypt(machine);
1803
1804		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0xd4c0, 0xd4ff, FUNC(drgnwrldv21_igs011_prot2_r));
	1814	igs011_state *state = machine.driver_data<igs011_state>();
	1815	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0xd4c0, 0xd4ff, read16_delegate(FUNC(igs011_state::drgnwrldv21_igs011_prot2_r), state));
1805	1816	/*
1806	1817	// PROTECTION CHECKS
1807	1818	// bp 32ee; bp 11ca8; bp 23d5e; bp 23fd0; bp 24170; bp 24348; bp 2454e; bp 246cc; bp 24922; bp 24b66; bp 24de2; bp 2502a; bp 25556; bp 269de; bp 2766a; bp 2a830
r14845	r14846
1941	1952
1942	1953	dbc_decrypt(machine);
1943	1954
1944		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x10600, 0x107ff, FUNC(dbc_igs011_prot2_r));
	1955	igs011_state *state = machine.driver_data<igs011_state>();
	1956	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x10600, 0x107ff, read16_delegate(FUNC(igs011_state::dbc_igs011_prot2_r), state));
1945	1957	/*
1946	1958	// PROTECTION CHECKS
1947	1959	rom[0x04c42/2]  =   0x602e;     // 004C42: 6604         bne 4c48  (rom test error otherwise)
r14845	r14846
1970	1982
1971	1983	ryukobou_decrypt(machine);
1972	1984
1973		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x10600, 0x107ff, FUNC(ryukobou_igs011_prot2_r));
	1985	igs011_state *state = machine.driver_data<igs011_state>();
	1986	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x10600, 0x107ff, read16_delegate(FUNC(igs011_state::ryukobou_igs011_prot2_r), state));
1974	1987
1975	1988	// PROTECTION CHECKS
1976	1989	//  rom[0x2df68/2]  =   0x4e75;     // 02DF68: 4E56 FE00    link A6, #-$200  (fills palette with pink otherwise)
r14845	r14846
2120	2133
2121	2134	static ADDRESS_MAP_START( drgnwrld, AS_PROGRAM, 16, igs011_state )
2122	2135	//  drgnwrld: IGS011 protection dynamically mapped at 1dd7x
2123		//  AM_RANGE( 0x01dd70, 0x01dd77 ) AM_WRITE_LEGACY(igs011_prot1_w )
	2136	//  AM_RANGE( 0x01dd70, 0x01dd77 ) AM_WRITE(igs011_prot1_w )
2124	2137	//  AM_RANGE( 0x01dd78, 0x01dd79 ) AM_READ ( igs011_prot1_r )
2125	2138
2126	2139	AM_RANGE( 0x000000, 0x07ffff ) AM_ROM
2127	2140	AM_RANGE( 0x100000, 0x103fff ) AM_RAM AM_SHARE("nvram")
2128	2141	AM_RANGE( 0x200000, 0x200fff ) AM_RAM AM_BASE(m_priority_ram )
2129		AM_RANGE( 0x400000, 0x401fff ) AM_RAM_WRITE_LEGACY(igs011_palette ) AM_BASE_GENERIC( paletteram )
	2142	AM_RANGE( 0x400000, 0x401fff ) AM_RAM_WRITE(igs011_palette ) AM_BASE_GENERIC( paletteram )
2130	2143	AM_RANGE( 0x500000, 0x500001 ) AM_READ_PORT( "COIN" )
2131	2144	AM_RANGE( 0x600000, 0x600001 ) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff )
2132	2145	AM_RANGE( 0x700000, 0x700003 ) AM_DEVWRITE8_LEGACY("ymsnd", ym3812_w, 0x00ff )
2133	2146
2134		AM_RANGE( 0x800000, 0x800003 ) AM_WRITE_LEGACY(drgnwrld_igs003_w )
2135		AM_RANGE( 0x800002, 0x800003 ) AM_READ_LEGACY(drgnwrld_igs003_r )
	2147	AM_RANGE( 0x800000, 0x800003 ) AM_WRITE(drgnwrld_igs003_w )
	2148	AM_RANGE( 0x800002, 0x800003 ) AM_READ(drgnwrld_igs003_r )
2136	2149
2137		AM_RANGE( 0xa20000, 0xa20001 ) AM_WRITE_LEGACY(igs011_priority_w )
2138		AM_RANGE( 0xa40000, 0xa40001 ) AM_WRITE_LEGACY(igs_dips_w )
	2150	AM_RANGE( 0xa20000, 0xa20001 ) AM_WRITE(igs011_priority_w )
	2151	AM_RANGE( 0xa40000, 0xa40001 ) AM_WRITE(igs_dips_w )
2139	2152
2140		AM_RANGE( 0xa50000, 0xa50001 ) AM_WRITE_LEGACY(igs011_prot_addr_w )
2141		//  AM_RANGE( 0xa50000, 0xa50005 ) AM_READ_LEGACY(igs011_prot_fake_r )
	2153	AM_RANGE( 0xa50000, 0xa50001 ) AM_WRITE(igs011_prot_addr_w )
	2154	//  AM_RANGE( 0xa50000, 0xa50005 ) AM_READ(igs011_prot_fake_r )
2142	2155
2143		AM_RANGE( 0xa58000, 0xa58001 ) AM_WRITE_LEGACY(igs011_blit_x_w )
2144		AM_RANGE( 0xa58800, 0xa58801 ) AM_WRITE_LEGACY(igs011_blit_y_w )
2145		AM_RANGE( 0xa59000, 0xa59001 ) AM_WRITE_LEGACY(igs011_blit_w_w )
2146		AM_RANGE( 0xa59800, 0xa59801 ) AM_WRITE_LEGACY(igs011_blit_h_w )
2147		AM_RANGE( 0xa5a000, 0xa5a001 ) AM_WRITE_LEGACY(igs011_blit_gfx_lo_w )
2148		AM_RANGE( 0xa5a800, 0xa5a801 ) AM_WRITE_LEGACY(igs011_blit_gfx_hi_w )
2149		AM_RANGE( 0xa5b000, 0xa5b001 ) AM_WRITE_LEGACY(igs011_blit_flags_w )
2150		AM_RANGE( 0xa5b800, 0xa5b801 ) AM_WRITE_LEGACY(igs011_blit_pen_w )
2151		AM_RANGE( 0xa5c000, 0xa5c001 ) AM_WRITE_LEGACY(igs011_blit_depth_w )
2152		AM_RANGE( 0xa88000, 0xa88001 ) AM_READ_LEGACY(igs_3_dips_r )
	2156	AM_RANGE( 0xa58000, 0xa58001 ) AM_WRITE(igs011_blit_x_w )
	2157	AM_RANGE( 0xa58800, 0xa58801 ) AM_WRITE(igs011_blit_y_w )
	2158	AM_RANGE( 0xa59000, 0xa59001 ) AM_WRITE(igs011_blit_w_w )
	2159	AM_RANGE( 0xa59800, 0xa59801 ) AM_WRITE(igs011_blit_h_w )
	2160	AM_RANGE( 0xa5a000, 0xa5a001 ) AM_WRITE(igs011_blit_gfx_lo_w )
	2161	AM_RANGE( 0xa5a800, 0xa5a801 ) AM_WRITE(igs011_blit_gfx_hi_w )
	2162	AM_RANGE( 0xa5b000, 0xa5b001 ) AM_WRITE(igs011_blit_flags_w )
	2163	AM_RANGE( 0xa5b800, 0xa5b801 ) AM_WRITE(igs011_blit_pen_w )
	2164	AM_RANGE( 0xa5c000, 0xa5c001 ) AM_WRITE(igs011_blit_depth_w )
	2165	AM_RANGE( 0xa88000, 0xa88001 ) AM_READ(igs_3_dips_r )
2153	2166	ADDRESS_MAP_END
2154	2167
2155	2168	static ADDRESS_MAP_START( drgnwrld_igs012, AS_PROGRAM, 16, igs011_state )
2156	2169	// IGS012
2157		AM_RANGE( 0x001600, 0x00160f ) AM_WRITE_LEGACY(igs012_prot_swap_w      )   AM_MIRROR(0x01c000)   // swap (a5 / 55)
2158		AM_RANGE( 0x001610, 0x00161f ) AM_READ_LEGACY(igs012_prot_r         )   AM_MIRROR(0x01c000)   // read (mode 0)
2159		AM_RANGE( 0x001620, 0x00162f ) AM_WRITE_LEGACY(igs012_prot_dec_inc_w   )   AM_MIRROR(0x01c000)   // dec  (aa), inc  (fa)
2160		AM_RANGE( 0x001630, 0x00163f ) AM_WRITE_LEGACY(igs012_prot_inc_w      )   AM_MIRROR(0x01c000)   // inc  (ff)
2161		AM_RANGE( 0x001640, 0x00164f ) AM_WRITE_LEGACY(igs012_prot_copy_w      )   AM_MIRROR(0x01c000)   // copy (22)
2162		AM_RANGE( 0x001650, 0x00165f ) AM_WRITE_LEGACY(igs012_prot_dec_copy_w   )   AM_MIRROR(0x01c000)   // dec  (5a), copy (33)
2163		AM_RANGE( 0x001660, 0x00166f ) AM_READ_LEGACY(igs012_prot_r         )   AM_MIRROR(0x01c000)   // read (mode 1)
2164		AM_RANGE( 0x001670, 0x00167f ) AM_WRITE_LEGACY(igs012_prot_mode_w      )   AM_MIRROR(0x01c000)   // mode (cc / dd)
	2170	AM_RANGE( 0x001600, 0x00160f ) AM_WRITE(igs012_prot_swap_w      )   AM_MIRROR(0x01c000)   // swap (a5 / 55)
	2171	AM_RANGE( 0x001610, 0x00161f ) AM_READ(igs012_prot_r         )   AM_MIRROR(0x01c000)   // read (mode 0)
	2172	AM_RANGE( 0x001620, 0x00162f ) AM_WRITE(igs012_prot_dec_inc_w   )   AM_MIRROR(0x01c000)   // dec  (aa), inc  (fa)
	2173	AM_RANGE( 0x001630, 0x00163f ) AM_WRITE(igs012_prot_inc_w      )   AM_MIRROR(0x01c000)   // inc  (ff)
	2174	AM_RANGE( 0x001640, 0x00164f ) AM_WRITE(igs012_prot_copy_w      )   AM_MIRROR(0x01c000)   // copy (22)
	2175	AM_RANGE( 0x001650, 0x00165f ) AM_WRITE(igs012_prot_dec_copy_w   )   AM_MIRROR(0x01c000)   // dec  (5a), copy (33)
	2176	AM_RANGE( 0x001660, 0x00166f ) AM_READ(igs012_prot_r         )   AM_MIRROR(0x01c000)   // read (mode 1)
	2177	AM_RANGE( 0x001670, 0x00167f ) AM_WRITE(igs012_prot_mode_w      )   AM_MIRROR(0x01c000)   // mode (cc / dd)
2165	2178
2166		AM_RANGE( 0x00d400, 0x00d43f ) AM_WRITE_LEGACY(igs011_prot2_dec_w            )   // dec   (33)
2167		AM_RANGE( 0x00d440, 0x00d47f ) AM_WRITE_LEGACY(drgnwrld_igs011_prot2_swap_w   )   // swap  (33)
2168		AM_RANGE( 0x00d480, 0x00d4bf ) AM_WRITE_LEGACY(igs011_prot2_reset_w         )   // reset (33)
2169		AM_RANGE( 0x00d4c0, 0x00d4ff ) AM_READ_LEGACY(drgnwrldv20j_igs011_prot2_r   )   // read
	2179	AM_RANGE( 0x00d400, 0x00d43f ) AM_WRITE(igs011_prot2_dec_w            )   // dec   (33)
	2180	AM_RANGE( 0x00d440, 0x00d47f ) AM_WRITE(drgnwrld_igs011_prot2_swap_w   )   // swap  (33)
	2181	AM_RANGE( 0x00d480, 0x00d4bf ) AM_WRITE(igs011_prot2_reset_w         )   // reset (33)
	2182	AM_RANGE( 0x00d4c0, 0x00d4ff ) AM_READ(drgnwrldv20j_igs011_prot2_r   )   // read
2170	2183
2171		AM_RANGE( 0x902000, 0x902fff ) AM_WRITE_LEGACY(igs012_prot_reset_w   )   // reset?
2172		//  AM_RANGE( 0x902000, 0x902005 ) AM_WRITE_LEGACY(igs012_prot_fake_r )
	2184	AM_RANGE( 0x902000, 0x902fff ) AM_WRITE(igs012_prot_reset_w   )   // reset?
	2185	//  AM_RANGE( 0x902000, 0x902005 ) AM_WRITE(igs012_prot_fake_r )
2173	2186
2174	2187	AM_IMPORT_FROM(drgnwrld)
2175	2188	ADDRESS_MAP_END
r14845	r14846
2177	2190
2178	2191
2179	2192	// Only values 0 and 7 are written (1 bit per irq source?)
2180		static WRITE16_HANDLER( lhb_irq_enable_w )
	2193	WRITE16_MEMBER(igs011_state::lhb_irq_enable_w)
2181	2194	{
2182		igs011_state *state = space->machine().driver_data<igs011_state>();
2183		COMBINE_DATA( &state->m_lhb_irq_enable );
	2195	COMBINE_DATA( &m_lhb_irq_enable );
2184	2196	}
2185	2197
2186	2198	static WRITE16_DEVICE_HANDLER( lhb_okibank_w )
r14845	r14846
2199	2211
2200	2212	static ADDRESS_MAP_START( lhb, AS_PROGRAM, 16, igs011_state )
2201	2213	//  lhb: IGS011 protection dynamically mapped at 834x
2202		//  AM_RANGE( 0x008340, 0x008347 ) AM_WRITE_LEGACY(igs011_prot1_w )
	2214	//  AM_RANGE( 0x008340, 0x008347 ) AM_WRITE(igs011_prot1_w )
2203	2215	//  AM_RANGE( 0x008348, 0x008349 ) AM_READ ( igs011_prot1_r )
2204	2216
2205	2217	AM_RANGE( 0x010000, 0x010001 ) AM_DEVWRITE_LEGACY("oki", lhb_okibank_w )
2206	2218
2207		AM_RANGE( 0x010200, 0x0103ff ) AM_WRITE_LEGACY(igs011_prot2_inc_w         )
2208		AM_RANGE( 0x010400, 0x0105ff ) AM_WRITE_LEGACY(lhb_igs011_prot2_swap_w   )
2209		AM_RANGE( 0x010600, 0x0107ff ) AM_READ_LEGACY(lhb_igs011_prot2_r         )
	2219	AM_RANGE( 0x010200, 0x0103ff ) AM_WRITE(igs011_prot2_inc_w         )
	2220	AM_RANGE( 0x010400, 0x0105ff ) AM_WRITE(lhb_igs011_prot2_swap_w   )
	2221	AM_RANGE( 0x010600, 0x0107ff ) AM_READ(lhb_igs011_prot2_r         )
2210	2222	// no reset
2211	2223
2212	2224	AM_RANGE( 0x000000, 0x07ffff ) AM_ROM
2213	2225	AM_RANGE( 0x100000, 0x103fff ) AM_RAM AM_SHARE("nvram")
2214	2226	AM_RANGE( 0x200000, 0x200fff ) AM_RAM AM_BASE(m_priority_ram )
2215		AM_RANGE( 0x300000, 0x3fffff ) AM_READWRITE_LEGACY(igs011_layers_r, igs011_layers_w )
2216		AM_RANGE( 0x400000, 0x401fff ) AM_RAM_WRITE_LEGACY(igs011_palette ) AM_BASE_GENERIC( paletteram )
	2227	AM_RANGE( 0x300000, 0x3fffff ) AM_READWRITE(igs011_layers_r, igs011_layers_w )
	2228	AM_RANGE( 0x400000, 0x401fff ) AM_RAM_WRITE(igs011_palette ) AM_BASE_GENERIC( paletteram )
2217	2229	AM_RANGE( 0x600000, 0x600001 ) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff )
2218	2230	AM_RANGE( 0x700000, 0x700001 ) AM_READ_PORT( "COIN" )
2219		AM_RANGE( 0x700002, 0x700005 ) AM_READ_LEGACY(lhb_inputs_r )
2220		AM_RANGE( 0x700002, 0x700003 ) AM_WRITE_LEGACY(lhb_inputs_w )
2221		AM_RANGE( 0x820000, 0x820001 ) AM_WRITE_LEGACY(igs011_priority_w )
2222		AM_RANGE( 0x838000, 0x838001 ) AM_WRITE_LEGACY(lhb_irq_enable_w )
2223		AM_RANGE( 0x840000, 0x840001 ) AM_WRITE_LEGACY(igs_dips_w )
	2231	AM_RANGE( 0x700002, 0x700005 ) AM_READ(lhb_inputs_r )
	2232	AM_RANGE( 0x700002, 0x700003 ) AM_WRITE(lhb_inputs_w )
	2233	AM_RANGE( 0x820000, 0x820001 ) AM_WRITE(igs011_priority_w )
	2234	AM_RANGE( 0x838000, 0x838001 ) AM_WRITE(lhb_irq_enable_w )
	2235	AM_RANGE( 0x840000, 0x840001 ) AM_WRITE(igs_dips_w )
2224	2236
2225		AM_RANGE( 0x850000, 0x850001 ) AM_WRITE_LEGACY(igs011_prot_addr_w )
2226		//  AM_RANGE( 0x850000, 0x850005 ) AM_WRITE_LEGACY(igs011_prot_fake_r )
	2237	AM_RANGE( 0x850000, 0x850001 ) AM_WRITE(igs011_prot_addr_w )
	2238	//  AM_RANGE( 0x850000, 0x850005 ) AM_WRITE(igs011_prot_fake_r )
2227	2239
2228		AM_RANGE( 0x858000, 0x858001 ) AM_WRITE_LEGACY(igs011_blit_x_w )
2229		AM_RANGE( 0x858800, 0x858801 ) AM_WRITE_LEGACY(igs011_blit_y_w )
2230		AM_RANGE( 0x859000, 0x859001 ) AM_WRITE_LEGACY(igs011_blit_w_w )
2231		AM_RANGE( 0x859800, 0x859801 ) AM_WRITE_LEGACY(igs011_blit_h_w )
2232		AM_RANGE( 0x85a000, 0x85a001 ) AM_WRITE_LEGACY(igs011_blit_gfx_lo_w )
2233		AM_RANGE( 0x85a800, 0x85a801 ) AM_WRITE_LEGACY(igs011_blit_gfx_hi_w )
2234		AM_RANGE( 0x85b000, 0x85b001 ) AM_WRITE_LEGACY(igs011_blit_flags_w )
2235		AM_RANGE( 0x85b800, 0x85b801 ) AM_WRITE_LEGACY(igs011_blit_pen_w )
2236		AM_RANGE( 0x85c000, 0x85c001 ) AM_WRITE_LEGACY(igs011_blit_depth_w )
2237		AM_RANGE( 0x888000, 0x888001 ) AM_READ_LEGACY(igs_5_dips_r )
	2240	AM_RANGE( 0x858000, 0x858001 ) AM_WRITE(igs011_blit_x_w )
	2241	AM_RANGE( 0x858800, 0x858801 ) AM_WRITE(igs011_blit_y_w )
	2242	AM_RANGE( 0x859000, 0x859001 ) AM_WRITE(igs011_blit_w_w )
	2243	AM_RANGE( 0x859800, 0x859801 ) AM_WRITE(igs011_blit_h_w )
	2244	AM_RANGE( 0x85a000, 0x85a001 ) AM_WRITE(igs011_blit_gfx_lo_w )
	2245	AM_RANGE( 0x85a800, 0x85a801 ) AM_WRITE(igs011_blit_gfx_hi_w )
	2246	AM_RANGE( 0x85b000, 0x85b001 ) AM_WRITE(igs011_blit_flags_w )
	2247	AM_RANGE( 0x85b800, 0x85b801 ) AM_WRITE(igs011_blit_pen_w )
	2248	AM_RANGE( 0x85c000, 0x85c001 ) AM_WRITE(igs011_blit_depth_w )
	2249	AM_RANGE( 0x888000, 0x888001 ) AM_READ(igs_5_dips_r )
2238	2250	ADDRESS_MAP_END
2239	2251
2240	2252	static ADDRESS_MAP_START( xymg, AS_PROGRAM, 16, igs011_state )
2241	2253	//  xymg: IGS011 protection dynamically mapped at 834x
2242		//  AM_RANGE( 0x008340, 0x008347 ) AM_WRITE_LEGACY(igs011_prot1_w )
	2254	//  AM_RANGE( 0x008340, 0x008347 ) AM_WRITE(igs011_prot1_w )
2243	2255	//  AM_RANGE( 0x008348, 0x008349 ) AM_READ ( igs011_prot1_r )
2244	2256
2245	2257	AM_RANGE( 0x010000, 0x010001 ) AM_DEVWRITE_LEGACY("oki", lhb_okibank_w )
2246	2258
2247		AM_RANGE( 0x010200, 0x0103ff ) AM_WRITE_LEGACY(igs011_prot2_inc_w         )   // inc  (33)
2248		AM_RANGE( 0x010400, 0x0105ff ) AM_WRITE_LEGACY(lhb_igs011_prot2_swap_w   )   // swap (33)
2249		AM_RANGE( 0x010600, 0x0107ff ) AM_READ_LEGACY(lhb_igs011_prot2_r         )   // read
	2259	AM_RANGE( 0x010200, 0x0103ff ) AM_WRITE(igs011_prot2_inc_w         )   // inc  (33)
	2260	AM_RANGE( 0x010400, 0x0105ff ) AM_WRITE(lhb_igs011_prot2_swap_w   )   // swap (33)
	2261	AM_RANGE( 0x010600, 0x0107ff ) AM_READ(lhb_igs011_prot2_r         )   // read
2250	2262	// no reset
2251	2263
2252	2264	AM_RANGE( 0x000000, 0x07ffff ) AM_ROM
2253	2265	AM_RANGE( 0x100000, 0x103fff ) AM_RAM
2254	2266	AM_RANGE( 0x1f0000, 0x1f3fff ) AM_RAM AM_SHARE("nvram") // extra ram
2255	2267	AM_RANGE( 0x200000, 0x200fff ) AM_RAM AM_BASE(m_priority_ram )
2256		AM_RANGE( 0x300000, 0x3fffff ) AM_READWRITE_LEGACY(igs011_layers_r, igs011_layers_w )
2257		AM_RANGE( 0x400000, 0x401fff ) AM_RAM_WRITE_LEGACY(igs011_palette ) AM_BASE_GENERIC( paletteram )
	2268	AM_RANGE( 0x300000, 0x3fffff ) AM_READWRITE(igs011_layers_r, igs011_layers_w )
	2269	AM_RANGE( 0x400000, 0x401fff ) AM_RAM_WRITE(igs011_palette ) AM_BASE_GENERIC( paletteram )
2258	2270	AM_RANGE( 0x600000, 0x600001 ) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff )
2259		AM_RANGE( 0x700000, 0x700003 ) AM_WRITE_LEGACY(xymg_igs003_w )
2260		AM_RANGE( 0x700002, 0x700003 ) AM_READ_LEGACY(xymg_igs003_r )
2261		AM_RANGE( 0x820000, 0x820001 ) AM_WRITE_LEGACY(igs011_priority_w )
2262		AM_RANGE( 0x840000, 0x840001 ) AM_WRITE_LEGACY(igs_dips_w )
	2271	AM_RANGE( 0x700000, 0x700003 ) AM_WRITE(xymg_igs003_w )
	2272	AM_RANGE( 0x700002, 0x700003 ) AM_READ(xymg_igs003_r )
	2273	AM_RANGE( 0x820000, 0x820001 ) AM_WRITE(igs011_priority_w )
	2274	AM_RANGE( 0x840000, 0x840001 ) AM_WRITE(igs_dips_w )
2263	2275
2264		AM_RANGE( 0x850000, 0x850001 ) AM_WRITE_LEGACY(igs011_prot_addr_w )
2265		//  AM_RANGE( 0x850000, 0x850005 ) AM_WRITE_LEGACY(igs011_prot_fake_r )
	2276	AM_RANGE( 0x850000, 0x850001 ) AM_WRITE(igs011_prot_addr_w )
	2277	//  AM_RANGE( 0x850000, 0x850005 ) AM_WRITE(igs011_prot_fake_r )
2266	2278
2267		AM_RANGE( 0x858000, 0x858001 ) AM_WRITE_LEGACY(igs011_blit_x_w )
2268		AM_RANGE( 0x858800, 0x858801 ) AM_WRITE_LEGACY(igs011_blit_y_w )
2269		AM_RANGE( 0x859000, 0x859001 ) AM_WRITE_LEGACY(igs011_blit_w_w )
2270		AM_RANGE( 0x859800, 0x859801 ) AM_WRITE_LEGACY(igs011_blit_h_w )
2271		AM_RANGE( 0x85a000, 0x85a001 ) AM_WRITE_LEGACY(igs011_blit_gfx_lo_w )
2272		AM_RANGE( 0x85a800, 0x85a801 ) AM_WRITE_LEGACY(igs011_blit_gfx_hi_w )
2273		AM_RANGE( 0x85b000, 0x85b001 ) AM_WRITE_LEGACY(igs011_blit_flags_w )
2274		AM_RANGE( 0x85b800, 0x85b801 ) AM_WRITE_LEGACY(igs011_blit_pen_w )
2275		AM_RANGE( 0x85c000, 0x85c001 ) AM_WRITE_LEGACY(igs011_blit_depth_w )
2276		AM_RANGE( 0x888000, 0x888001 ) AM_READ_LEGACY(igs_3_dips_r )
	2279	AM_RANGE( 0x858000, 0x858001 ) AM_WRITE(igs011_blit_x_w )
	2280	AM_RANGE( 0x858800, 0x858801 ) AM_WRITE(igs011_blit_y_w )
	2281	AM_RANGE( 0x859000, 0x859001 ) AM_WRITE(igs011_blit_w_w )
	2282	AM_RANGE( 0x859800, 0x859801 ) AM_WRITE(igs011_blit_h_w )
	2283	AM_RANGE( 0x85a000, 0x85a001 ) AM_WRITE(igs011_blit_gfx_lo_w )
	2284	AM_RANGE( 0x85a800, 0x85a801 ) AM_WRITE(igs011_blit_gfx_hi_w )
	2285	AM_RANGE( 0x85b000, 0x85b001 ) AM_WRITE(igs011_blit_flags_w )
	2286	AM_RANGE( 0x85b800, 0x85b801 ) AM_WRITE(igs011_blit_pen_w )
	2287	AM_RANGE( 0x85c000, 0x85c001 ) AM_WRITE(igs011_blit_depth_w )
	2288	AM_RANGE( 0x888000, 0x888001 ) AM_READ(igs_3_dips_r )
2277	2289	ADDRESS_MAP_END
2278	2290
2279	2291	static ADDRESS_MAP_START( wlcc, AS_PROGRAM, 16, igs011_state )
2280	2292	//  wlcc: IGS011 protection dynamically mapped at 834x
2281		//  AM_RANGE( 0x008340, 0x008347 ) AM_WRITE_LEGACY(igs011_prot1_w )
2282		//  AM_RANGE( 0x008348, 0x008349 ) AM_READ_LEGACY(igs011_prot1_r )
	2293	//  AM_RANGE( 0x008340, 0x008347 ) AM_WRITE(igs011_prot1_w )
	2294	//  AM_RANGE( 0x008348, 0x008349 ) AM_READ(igs011_prot1_r )
2283	2295
2284		AM_RANGE( 0x518000, 0x5181ff ) AM_WRITE_LEGACY(igs011_prot2_inc_w         )   // inc   (33)
2285		AM_RANGE( 0x518200, 0x5183ff ) AM_WRITE_LEGACY(wlcc_igs011_prot2_swap_w   )   // swap  (33)
2286		AM_RANGE( 0x518800, 0x5189ff ) AM_READ_LEGACY(igs011_prot2_reset_r      )   // reset
2287		AM_RANGE( 0x519000, 0x5195ff ) AM_READ_LEGACY(lhb_igs011_prot2_r         )   // read
	2296	AM_RANGE( 0x518000, 0x5181ff ) AM_WRITE(igs011_prot2_inc_w         )   // inc   (33)
	2297	AM_RANGE( 0x518200, 0x5183ff ) AM_WRITE(wlcc_igs011_prot2_swap_w   )   // swap  (33)
	2298	AM_RANGE( 0x518800, 0x5189ff ) AM_READ(igs011_prot2_reset_r      )   // reset
	2299	AM_RANGE( 0x519000, 0x5195ff ) AM_READ(lhb_igs011_prot2_r         )   // read
2288	2300
2289	2301	AM_RANGE( 0x000000, 0x07ffff ) AM_ROM
2290	2302	AM_RANGE( 0x100000, 0x103fff ) AM_RAM AM_SHARE("nvram")
2291	2303	AM_RANGE( 0x200000, 0x200fff ) AM_RAM AM_BASE(m_priority_ram )
2292		AM_RANGE( 0x300000, 0x3fffff ) AM_READWRITE_LEGACY(igs011_layers_r, igs011_layers_w )
2293		AM_RANGE( 0x400000, 0x401fff ) AM_RAM_WRITE_LEGACY(igs011_palette ) AM_BASE_GENERIC( paletteram )
	2304	AM_RANGE( 0x300000, 0x3fffff ) AM_READWRITE(igs011_layers_r, igs011_layers_w )
	2305	AM_RANGE( 0x400000, 0x401fff ) AM_RAM_WRITE(igs011_palette ) AM_BASE_GENERIC( paletteram )
2294	2306	AM_RANGE( 0x520000, 0x520001 ) AM_READ_PORT( "COIN" )
2295	2307	AM_RANGE( 0x600000, 0x600001 ) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff )
2296		AM_RANGE( 0x800000, 0x800003 ) AM_WRITE_LEGACY(wlcc_igs003_w )
2297		AM_RANGE( 0x800002, 0x800003 ) AM_READ_LEGACY(wlcc_igs003_r )
2298		AM_RANGE( 0xa20000, 0xa20001 ) AM_WRITE_LEGACY(igs011_priority_w )
2299		AM_RANGE( 0xa40000, 0xa40001 ) AM_WRITE_LEGACY(igs_dips_w )
	2308	AM_RANGE( 0x800000, 0x800003 ) AM_WRITE(wlcc_igs003_w )
	2309	AM_RANGE( 0x800002, 0x800003 ) AM_READ(wlcc_igs003_r )
	2310	AM_RANGE( 0xa20000, 0xa20001 ) AM_WRITE(igs011_priority_w )
	2311	AM_RANGE( 0xa40000, 0xa40001 ) AM_WRITE(igs_dips_w )
2300	2312
2301		AM_RANGE( 0xa50000, 0xa50001 ) AM_WRITE_LEGACY(igs011_prot_addr_w )
2302		//  AM_RANGE( 0xa50000, 0xa50005 ) AM_READ_LEGACY(igs011_prot_fake_r )
	2313	AM_RANGE( 0xa50000, 0xa50001 ) AM_WRITE(igs011_prot_addr_w )
	2314	//  AM_RANGE( 0xa50000, 0xa50005 ) AM_READ(igs011_prot_fake_r )
2303	2315
2304		AM_RANGE( 0xa58000, 0xa58001 ) AM_WRITE_LEGACY(igs011_blit_x_w )
2305		AM_RANGE( 0xa58800, 0xa58801 ) AM_WRITE_LEGACY(igs011_blit_y_w )
2306		AM_RANGE( 0xa59000, 0xa59001 ) AM_WRITE_LEGACY(igs011_blit_w_w )
2307		AM_RANGE( 0xa59800, 0xa59801 ) AM_WRITE_LEGACY(igs011_blit_h_w )
2308		AM_RANGE( 0xa5a000, 0xa5a001 ) AM_WRITE_LEGACY(igs011_blit_gfx_lo_w )
2309		AM_RANGE( 0xa5a800, 0xa5a801 ) AM_WRITE_LEGACY(igs011_blit_gfx_hi_w )
2310		AM_RANGE( 0xa5b000, 0xa5b001 ) AM_WRITE_LEGACY(igs011_blit_flags_w )
2311		AM_RANGE( 0xa5b800, 0xa5b801 ) AM_WRITE_LEGACY(igs011_blit_pen_w )
2312		AM_RANGE( 0xa5c000, 0xa5c001 ) AM_WRITE_LEGACY(igs011_blit_depth_w )
2313		AM_RANGE( 0xa88000, 0xa88001 ) AM_READ_LEGACY(igs_4_dips_r )
	2316	AM_RANGE( 0xa58000, 0xa58001 ) AM_WRITE(igs011_blit_x_w )
	2317	AM_RANGE( 0xa58800, 0xa58801 ) AM_WRITE(igs011_blit_y_w )
	2318	AM_RANGE( 0xa59000, 0xa59001 ) AM_WRITE(igs011_blit_w_w )
	2319	AM_RANGE( 0xa59800, 0xa59801 ) AM_WRITE(igs011_blit_h_w )
	2320	AM_RANGE( 0xa5a000, 0xa5a001 ) AM_WRITE(igs011_blit_gfx_lo_w )
	2321	AM_RANGE( 0xa5a800, 0xa5a801 ) AM_WRITE(igs011_blit_gfx_hi_w )
	2322	AM_RANGE( 0xa5b000, 0xa5b001 ) AM_WRITE(igs011_blit_flags_w )
	2323	AM_RANGE( 0xa5b800, 0xa5b801 ) AM_WRITE(igs011_blit_pen_w )
	2324	AM_RANGE( 0xa5c000, 0xa5c001 ) AM_WRITE(igs011_blit_depth_w )
	2325	AM_RANGE( 0xa88000, 0xa88001 ) AM_READ(igs_4_dips_r )
2314	2326	ADDRESS_MAP_END
2315	2327
2316	2328
2317	2329
2318	2330	static ADDRESS_MAP_START( lhb2, AS_PROGRAM, 16, igs011_state )
2319	2331	//  lhb2: IGS011 protection dynamically mapped at 1ff8x
2320		//  AM_RANGE( 0x01ff80, 0x01ff87 ) AM_WRITE_LEGACY(igs011_prot1_w )
	2332	//  AM_RANGE( 0x01ff80, 0x01ff87 ) AM_WRITE(igs011_prot1_w )
2321	2333	//  AM_RANGE( 0x01ff88, 0x01ff89 ) AM_READ ( igs011_prot1_r )
2322	2334
2323		AM_RANGE( 0x020000, 0x0201ff ) AM_WRITE_LEGACY(igs011_prot2_inc_w         )   // inc   (55)
2324		AM_RANGE( 0x020200, 0x0203ff ) AM_WRITE_LEGACY(lhb_igs011_prot2_swap_w   )   // swap  (33)
2325		AM_RANGE( 0x020400, 0x0205ff ) AM_READ_LEGACY(lhb2_igs011_prot2_r      )   // read
2326		AM_RANGE( 0x020600, 0x0207ff ) AM_WRITE_LEGACY(igs011_prot2_reset_w      )   // reset (55)
	2335	AM_RANGE( 0x020000, 0x0201ff ) AM_WRITE(igs011_prot2_inc_w         )   // inc   (55)
	2336	AM_RANGE( 0x020200, 0x0203ff ) AM_WRITE(lhb_igs011_prot2_swap_w   )   // swap  (33)
	2337	AM_RANGE( 0x020400, 0x0205ff ) AM_READ(lhb2_igs011_prot2_r      )   // read
	2338	AM_RANGE( 0x020600, 0x0207ff ) AM_WRITE(igs011_prot2_reset_w      )   // reset (55)
2327	2339
2328	2340	AM_RANGE( 0x000000, 0x07ffff ) AM_ROM
2329	2341	AM_RANGE( 0x100000, 0x103fff ) AM_RAM AM_SHARE("nvram")
2330	2342	AM_RANGE( 0x200000, 0x200001 ) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff )
2331	2343	AM_RANGE( 0x204000, 0x204003 ) AM_DEVWRITE8_LEGACY("ymsnd", ym2413_w, 0x00ff )
2332		AM_RANGE( 0x208000, 0x208003 ) AM_WRITE_LEGACY(lhb2_igs003_w )
2333		AM_RANGE( 0x208002, 0x208003 ) AM_READ_LEGACY(lhb2_igs003_r )
	2344	AM_RANGE( 0x208000, 0x208003 ) AM_WRITE(lhb2_igs003_w )
	2345	AM_RANGE( 0x208002, 0x208003 ) AM_READ(lhb2_igs003_r )
2334	2346	AM_RANGE( 0x20c000, 0x20cfff ) AM_RAM AM_BASE(m_priority_ram)
2335		AM_RANGE( 0x210000, 0x211fff ) AM_RAM_WRITE_LEGACY(igs011_palette ) AM_BASE_GENERIC( paletteram )
	2347	AM_RANGE( 0x210000, 0x211fff ) AM_RAM_WRITE(igs011_palette ) AM_BASE_GENERIC( paletteram )
2336	2348	AM_RANGE( 0x214000, 0x214001 ) AM_READ_PORT( "COIN" )
2337		AM_RANGE( 0x300000, 0x3fffff ) AM_READWRITE_LEGACY(igs011_layers_r, igs011_layers_w )
2338		AM_RANGE( 0xa20000, 0xa20001 ) AM_WRITE_LEGACY(igs011_priority_w )
2339		AM_RANGE( 0xa40000, 0xa40001 ) AM_WRITE_LEGACY(igs_dips_w )
	2349	AM_RANGE( 0x300000, 0x3fffff ) AM_READWRITE(igs011_layers_r, igs011_layers_w )
	2350	AM_RANGE( 0xa20000, 0xa20001 ) AM_WRITE(igs011_priority_w )
	2351	AM_RANGE( 0xa40000, 0xa40001 ) AM_WRITE(igs_dips_w )
2340	2352
2341		AM_RANGE( 0xa50000, 0xa50001 ) AM_WRITE_LEGACY(igs011_prot_addr_w )
2342		//  AM_RANGE( 0xa50000, 0xa50005 ) AM_READ_LEGACY(igs011_prot_fake_r )
	2353	AM_RANGE( 0xa50000, 0xa50001 ) AM_WRITE(igs011_prot_addr_w )
	2354	//  AM_RANGE( 0xa50000, 0xa50005 ) AM_READ(igs011_prot_fake_r )
2343	2355
2344		AM_RANGE( 0xa58000, 0xa58001 ) AM_WRITE_LEGACY(igs011_blit_x_w )
2345		AM_RANGE( 0xa58800, 0xa58801 ) AM_WRITE_LEGACY(igs011_blit_y_w )
2346		AM_RANGE( 0xa59000, 0xa59001 ) AM_WRITE_LEGACY(igs011_blit_w_w )
2347		AM_RANGE( 0xa59800, 0xa59801 ) AM_WRITE_LEGACY(igs011_blit_h_w )
2348		AM_RANGE( 0xa5a000, 0xa5a001 ) AM_WRITE_LEGACY(igs011_blit_gfx_lo_w )
2349		AM_RANGE( 0xa5a800, 0xa5a801 ) AM_WRITE_LEGACY(igs011_blit_gfx_hi_w )
2350		AM_RANGE( 0xa5b000, 0xa5b001 ) AM_WRITE_LEGACY(igs011_blit_flags_w )
2351		AM_RANGE( 0xa5b800, 0xa5b801 ) AM_WRITE_LEGACY(igs011_blit_pen_w )
2352		AM_RANGE( 0xa5c000, 0xa5c001 ) AM_WRITE_LEGACY(igs011_blit_depth_w )
2353		AM_RANGE( 0xa88000, 0xa88001 ) AM_READ_LEGACY(igs_3_dips_r )
	2356	AM_RANGE( 0xa58000, 0xa58001 ) AM_WRITE(igs011_blit_x_w )
	2357	AM_RANGE( 0xa58800, 0xa58801 ) AM_WRITE(igs011_blit_y_w )
	2358	AM_RANGE( 0xa59000, 0xa59001 ) AM_WRITE(igs011_blit_w_w )
	2359	AM_RANGE( 0xa59800, 0xa59801 ) AM_WRITE(igs011_blit_h_w )
	2360	AM_RANGE( 0xa5a000, 0xa5a001 ) AM_WRITE(igs011_blit_gfx_lo_w )
	2361	AM_RANGE( 0xa5a800, 0xa5a801 ) AM_WRITE(igs011_blit_gfx_hi_w )
	2362	AM_RANGE( 0xa5b000, 0xa5b001 ) AM_WRITE(igs011_blit_flags_w )
	2363	AM_RANGE( 0xa5b800, 0xa5b801 ) AM_WRITE(igs011_blit_pen_w )
	2364	AM_RANGE( 0xa5c000, 0xa5c001 ) AM_WRITE(igs011_blit_depth_w )
	2365	AM_RANGE( 0xa88000, 0xa88001 ) AM_READ(igs_3_dips_r )
2354	2366	ADDRESS_MAP_END
2355	2367
2356	2368	/* trap15's note:
r14845	r14846
2383	2395	}
2384	2396	}
2385	2397
2386		static READ16_HANDLER( vbowl_unk_r )
	2398	READ16_MEMBER(igs011_state::vbowl_unk_r)
2387	2399	{
2388	2400	return 0xffff;
2389	2401	}
r14845	r14846
2399	2411	}
2400	2412	}
2401	2413
2402		static WRITE16_HANDLER( vbowl_pen_hi_w )
	2414	WRITE16_MEMBER(igs011_state::vbowl_pen_hi_w)
2403	2415	{
2404		igs011_state *state = space->machine().driver_data<igs011_state>();
2405	2416	if (ACCESSING_BITS_0_7)
2406	2417	{
2407		state->m_lhb2_pen_hi = data & 0x07;
	2418	m_lhb2_pen_hi = data & 0x07;
2408	2419	}
2409	2420
2410	2421	if (data & ~0x7)
2411		logerror("%06x: warning, unknown bits written to pen_hi = %04x\n", cpu_get_pc(&space->device()), state->m_priority);
	2422	logerror("%06x: warning, unknown bits written to pen_hi = %04x\n", cpu_get_pc(&space.device()), m_priority);
2412	2423	}
2413	2424
2414		static WRITE16_HANDLER( vbowl_link_0_w )   { }
2415		static WRITE16_HANDLER( vbowl_link_1_w )   { }
2416		static WRITE16_HANDLER( vbowl_link_2_w )   { }
2417		static WRITE16_HANDLER( vbowl_link_3_w )   { }
	2425	WRITE16_MEMBER(igs011_state::vbowl_link_0_w){ }
	2426	WRITE16_MEMBER(igs011_state::vbowl_link_1_w){ }
	2427	WRITE16_MEMBER(igs011_state::vbowl_link_2_w){ }
	2428	WRITE16_MEMBER(igs011_state::vbowl_link_3_w){ }
2418	2429
2419	2430	static ADDRESS_MAP_START( vbowl, AS_PROGRAM, 16, igs011_state )
2420	2431	//  vbowl: IGS011 protection dynamically mapped at 834x
2421		//  AM_RANGE( 0x008340, 0x008347 ) AM_WRITE_LEGACY(igs011_prot1_w )
2422		//  AM_RANGE( 0x008348, 0x008349 ) AM_READ_LEGACY(igs011_prot1_r )
	2432	//  AM_RANGE( 0x008340, 0x008347 ) AM_WRITE(igs011_prot1_w )
	2433	//  AM_RANGE( 0x008348, 0x008349 ) AM_READ(igs011_prot1_r )
2423	2434
2424	2435	// IGS012
2425		AM_RANGE( 0x001600, 0x00160f ) AM_WRITE_LEGACY(igs012_prot_swap_w      )   AM_MIRROR(0x01c000)   // swap (a5 / 55)
2426		AM_RANGE( 0x001610, 0x00161f ) AM_READ_LEGACY(igs012_prot_r         )   AM_MIRROR(0x01c000)   // read (mode 0)
2427		AM_RANGE( 0x001620, 0x00162f ) AM_WRITE_LEGACY(igs012_prot_dec_inc_w   )   AM_MIRROR(0x01c000)   // dec  (aa), inc  (fa)
2428		AM_RANGE( 0x001630, 0x00163f ) AM_WRITE_LEGACY(igs012_prot_inc_w      )   AM_MIRROR(0x01c000)   // inc  (ff)
2429		AM_RANGE( 0x001640, 0x00164f ) AM_WRITE_LEGACY(igs012_prot_copy_w      )   AM_MIRROR(0x01c000)   // copy (22)
2430		AM_RANGE( 0x001650, 0x00165f ) AM_WRITE_LEGACY(igs012_prot_dec_copy_w   )   AM_MIRROR(0x01c000)   // dec  (5a), copy (33)
2431		AM_RANGE( 0x001660, 0x00166f ) AM_READ_LEGACY(igs012_prot_r         )   AM_MIRROR(0x01c000)   // read (mode 1)
2432		AM_RANGE( 0x001670, 0x00167f ) AM_WRITE_LEGACY(igs012_prot_mode_w      )   AM_MIRROR(0x01c000)   // mode (cc / dd)
	2436	AM_RANGE( 0x001600, 0x00160f ) AM_WRITE(igs012_prot_swap_w      )   AM_MIRROR(0x01c000)   // swap (a5 / 55)
	2437	AM_RANGE( 0x001610, 0x00161f ) AM_READ(igs012_prot_r         )   AM_MIRROR(0x01c000)   // read (mode 0)
	2438	AM_RANGE( 0x001620, 0x00162f ) AM_WRITE(igs012_prot_dec_inc_w   )   AM_MIRROR(0x01c000)   // dec  (aa), inc  (fa)
	2439	AM_RANGE( 0x001630, 0x00163f ) AM_WRITE(igs012_prot_inc_w      )   AM_MIRROR(0x01c000)   // inc  (ff)
	2440	AM_RANGE( 0x001640, 0x00164f ) AM_WRITE(igs012_prot_copy_w      )   AM_MIRROR(0x01c000)   // copy (22)
	2441	AM_RANGE( 0x001650, 0x00165f ) AM_WRITE(igs012_prot_dec_copy_w   )   AM_MIRROR(0x01c000)   // dec  (5a), copy (33)
	2442	AM_RANGE( 0x001660, 0x00166f ) AM_READ(igs012_prot_r         )   AM_MIRROR(0x01c000)   // read (mode 1)
	2443	AM_RANGE( 0x001670, 0x00167f ) AM_WRITE(igs012_prot_mode_w      )   AM_MIRROR(0x01c000)   // mode (cc / dd)
2433	2444
2434		AM_RANGE( 0x00d400, 0x00d43f ) AM_WRITE_LEGACY(igs011_prot2_dec_w            )   // dec   (33)
2435		AM_RANGE( 0x00d440, 0x00d47f ) AM_WRITE_LEGACY(drgnwrld_igs011_prot2_swap_w   )   // swap  (33)
2436		AM_RANGE( 0x00d480, 0x00d4bf ) AM_WRITE_LEGACY(igs011_prot2_reset_w         )   // reset (33)
2437		AM_RANGE( 0x00d4c0, 0x00d4ff ) AM_READ_LEGACY(drgnwrldv20j_igs011_prot2_r   )   // read
	2445	AM_RANGE( 0x00d400, 0x00d43f ) AM_WRITE(igs011_prot2_dec_w            )   // dec   (33)
	2446	AM_RANGE( 0x00d440, 0x00d47f ) AM_WRITE(drgnwrld_igs011_prot2_swap_w   )   // swap  (33)
	2447	AM_RANGE( 0x00d480, 0x00d4bf ) AM_WRITE(igs011_prot2_reset_w         )   // reset (33)
	2448	AM_RANGE( 0x00d4c0, 0x00d4ff ) AM_READ(drgnwrldv20j_igs011_prot2_r   )   // read
2438	2449
2439		AM_RANGE( 0x50f000, 0x50f1ff ) AM_WRITE_LEGACY(igs011_prot2_dec_w         )   // dec   (33)
2440		AM_RANGE( 0x50f200, 0x50f3ff ) AM_WRITE_LEGACY(vbowl_igs011_prot2_swap_w   )   // swap  (33)
2441		AM_RANGE( 0x50f400, 0x50f5ff ) AM_WRITE_LEGACY(igs011_prot2_reset_w      )   // reset (33)
2442		AM_RANGE( 0x50f600, 0x50f7ff ) AM_READ_LEGACY(vbowl_igs011_prot2_r      )   // read
	2450	AM_RANGE( 0x50f000, 0x50f1ff ) AM_WRITE(igs011_prot2_dec_w         )   // dec   (33)
	2451	AM_RANGE( 0x50f200, 0x50f3ff ) AM_WRITE(vbowl_igs011_prot2_swap_w   )   // swap  (33)
	2452	AM_RANGE( 0x50f400, 0x50f5ff ) AM_WRITE(igs011_prot2_reset_w      )   // reset (33)
	2453	AM_RANGE( 0x50f600, 0x50f7ff ) AM_READ(vbowl_igs011_prot2_r      )   // read
2443	2454
2444		AM_RANGE( 0x902000, 0x902fff ) AM_WRITE_LEGACY(igs012_prot_reset_w   )   // reset?
2445		//  AM_RANGE( 0x902000, 0x902005 ) AM_WRITE_LEGACY(igs012_prot_fake_r )
	2455	AM_RANGE( 0x902000, 0x902fff ) AM_WRITE(igs012_prot_reset_w   )   // reset?
	2456	//  AM_RANGE( 0x902000, 0x902005 ) AM_WRITE(igs012_prot_fake_r )
2446	2457
2447	2458	AM_RANGE( 0x000000, 0x07ffff ) AM_ROM
2448	2459	AM_RANGE( 0x100000, 0x103fff ) AM_RAM AM_SHARE("nvram")
2449	2460	AM_RANGE( 0x200000, 0x200fff ) AM_RAM AM_BASE(m_priority_ram )
2450		AM_RANGE( 0x300000, 0x3fffff ) AM_READWRITE_LEGACY(igs011_layers_r, igs011_layers_w )
2451		AM_RANGE( 0x400000, 0x401fff ) AM_RAM_WRITE_LEGACY(igs011_palette ) AM_BASE_GENERIC( paletteram )
	2461	AM_RANGE( 0x300000, 0x3fffff ) AM_READWRITE(igs011_layers_r, igs011_layers_w )
	2462	AM_RANGE( 0x400000, 0x401fff ) AM_RAM_WRITE(igs011_palette ) AM_BASE_GENERIC( paletteram )
2452	2463	AM_RANGE( 0x520000, 0x520001 ) AM_READ_PORT( "COIN" )
2453	2464	AM_RANGE( 0x600000, 0x600007 ) AM_DEVREADWRITE_LEGACY("ics", ics2115_word_r, ics2115_word_w )
2454	2465	AM_RANGE( 0x700000, 0x700003 ) AM_RAM AM_BASE(m_vbowl_trackball )
2455		AM_RANGE( 0x700004, 0x700005 ) AM_WRITE_LEGACY(vbowl_pen_hi_w )
2456		AM_RANGE( 0x800000, 0x800003 ) AM_WRITE_LEGACY(vbowl_igs003_w )
2457		AM_RANGE( 0x800002, 0x800003 ) AM_READ_LEGACY(vbowl_igs003_r )
	2466	AM_RANGE( 0x700004, 0x700005 ) AM_WRITE(vbowl_pen_hi_w )
	2467	AM_RANGE( 0x800000, 0x800003 ) AM_WRITE(vbowl_igs003_w )
	2468	AM_RANGE( 0x800002, 0x800003 ) AM_READ(vbowl_igs003_r )
2458	2469
2459		AM_RANGE( 0xa00000, 0xa00001 ) AM_WRITE_LEGACY(vbowl_link_0_w )
2460		AM_RANGE( 0xa08000, 0xa08001 ) AM_WRITE_LEGACY(vbowl_link_1_w )
2461		AM_RANGE( 0xa10000, 0xa10001 ) AM_WRITE_LEGACY(vbowl_link_2_w )
2462		AM_RANGE( 0xa18000, 0xa18001 ) AM_WRITE_LEGACY(vbowl_link_3_w )
	2470	AM_RANGE( 0xa00000, 0xa00001 ) AM_WRITE(vbowl_link_0_w )
	2471	AM_RANGE( 0xa08000, 0xa08001 ) AM_WRITE(vbowl_link_1_w )
	2472	AM_RANGE( 0xa10000, 0xa10001 ) AM_WRITE(vbowl_link_2_w )
	2473	AM_RANGE( 0xa18000, 0xa18001 ) AM_WRITE(vbowl_link_3_w )
2463	2474
2464		AM_RANGE( 0xa20000, 0xa20001 ) AM_WRITE_LEGACY(igs011_priority_w )
2465		AM_RANGE( 0xa40000, 0xa40001 ) AM_WRITE_LEGACY(igs_dips_w )
	2475	AM_RANGE( 0xa20000, 0xa20001 ) AM_WRITE(igs011_priority_w )
	2476	AM_RANGE( 0xa40000, 0xa40001 ) AM_WRITE(igs_dips_w )
2466	2477
2467		AM_RANGE( 0xa48000, 0xa48001 ) AM_WRITE_LEGACY(igs011_prot_addr_w )
2468		//  AM_RANGE( 0xa48000, 0xa48005 ) AM_WRITE_LEGACY(igs011_prot_fake_r )
	2478	AM_RANGE( 0xa48000, 0xa48001 ) AM_WRITE(igs011_prot_addr_w )
	2479	//  AM_RANGE( 0xa48000, 0xa48005 ) AM_WRITE(igs011_prot_fake_r )
2469	2480
2470		AM_RANGE( 0xa58000, 0xa58001 ) AM_WRITE_LEGACY(igs011_blit_x_w )
2471		AM_RANGE( 0xa58800, 0xa58801 ) AM_WRITE_LEGACY(igs011_blit_y_w )
2472		AM_RANGE( 0xa59000, 0xa59001 ) AM_WRITE_LEGACY(igs011_blit_w_w )
2473		AM_RANGE( 0xa59800, 0xa59801 ) AM_WRITE_LEGACY(igs011_blit_h_w )
2474		AM_RANGE( 0xa5a000, 0xa5a001 ) AM_WRITE_LEGACY(igs011_blit_gfx_lo_w )
2475		AM_RANGE( 0xa5a800, 0xa5a801 ) AM_WRITE_LEGACY(igs011_blit_gfx_hi_w )
2476		AM_RANGE( 0xa5b000, 0xa5b001 ) AM_WRITE_LEGACY(igs011_blit_flags_w )
2477		AM_RANGE( 0xa5b800, 0xa5b801 ) AM_WRITE_LEGACY(igs011_blit_pen_w )
2478		AM_RANGE( 0xa5c000, 0xa5c001 ) AM_WRITE_LEGACY(igs011_blit_depth_w )
	2481	AM_RANGE( 0xa58000, 0xa58001 ) AM_WRITE(igs011_blit_x_w )
	2482	AM_RANGE( 0xa58800, 0xa58801 ) AM_WRITE(igs011_blit_y_w )
	2483	AM_RANGE( 0xa59000, 0xa59001 ) AM_WRITE(igs011_blit_w_w )
	2484	AM_RANGE( 0xa59800, 0xa59801 ) AM_WRITE(igs011_blit_h_w )
	2485	AM_RANGE( 0xa5a000, 0xa5a001 ) AM_WRITE(igs011_blit_gfx_lo_w )
	2486	AM_RANGE( 0xa5a800, 0xa5a801 ) AM_WRITE(igs011_blit_gfx_hi_w )
	2487	AM_RANGE( 0xa5b000, 0xa5b001 ) AM_WRITE(igs011_blit_flags_w )
	2488	AM_RANGE( 0xa5b800, 0xa5b801 ) AM_WRITE(igs011_blit_pen_w )
	2489	AM_RANGE( 0xa5c000, 0xa5c001 ) AM_WRITE(igs011_blit_depth_w )
2479	2490
2480		AM_RANGE( 0xa80000, 0xa80001 ) AM_READ_LEGACY(vbowl_unk_r )
2481		AM_RANGE( 0xa88000, 0xa88001 ) AM_READ_LEGACY(igs_4_dips_r )
2482		AM_RANGE( 0xa90000, 0xa90001 ) AM_READ_LEGACY(vbowl_unk_r )
2483		AM_RANGE( 0xa98000, 0xa98001 ) AM_READ_LEGACY(vbowl_unk_r )
	2491	AM_RANGE( 0xa80000, 0xa80001 ) AM_READ(vbowl_unk_r )
	2492	AM_RANGE( 0xa88000, 0xa88001 ) AM_READ(igs_4_dips_r )
	2493	AM_RANGE( 0xa90000, 0xa90001 ) AM_READ(vbowl_unk_r )
	2494	AM_RANGE( 0xa98000, 0xa98001 ) AM_READ(vbowl_unk_r )
2484	2495	ADDRESS_MAP_END
2485	2496
2486	2497

src/mame/drivers/srmp6.c

r14845	r14846
90	90	unsigned short m_lastb;
91	91	unsigned short m_lastb2;
92	92	int m_destl;
	93	DECLARE_WRITE16_MEMBER(srmp6_input_select_w);
	94	DECLARE_READ16_MEMBER(srmp6_inputs_r);
	95	DECLARE_WRITE16_MEMBER(video_regs_w);
	96	DECLARE_READ16_MEMBER(video_regs_r);
	97	DECLARE_WRITE16_MEMBER(srmp6_dma_w);
	98	DECLARE_READ16_MEMBER(tileram_r);
	99	DECLARE_WRITE16_MEMBER(tileram_w);
	100	DECLARE_WRITE16_MEMBER(paletteram_w);
	101	DECLARE_READ16_MEMBER(srmp6_irq_ack_r);
93	102	};
94	103
95	104	#define VERBOSE 0
r14845	r14846
288	297	Main CPU memory handlers
289	298	***************************************************************************/
290	299
291		static WRITE16_HANDLER( srmp6_input_select_w )
	300	WRITE16_MEMBER(srmp6_state::srmp6_input_select_w)
292	301	{
293		srmp6_state *state = space->machine().driver_data<srmp6_state>();
294	302
295		state->m_input_select = data & 0x0f;
	303	m_input_select = data & 0x0f;
296	304	}
297	305
298		static READ16_HANDLER( srmp6_inputs_r )
	306	READ16_MEMBER(srmp6_state::srmp6_inputs_r)
299	307	{
300		srmp6_state *state = space->machine().driver_data<srmp6_state>();
301	308
302	309	if (offset == 0)         // DSW
303		return input_port_read(space->machine(), "DSW");
	310	return input_port_read(machine(), "DSW");
304	311
305		switch (state->m_input_select)   // inputs
	312	switch (m_input_select)   // inputs
306	313	{
307		case 1<<0: return input_port_read(space->machine(), "KEY0");
308		case 1<<1: return input_port_read(space->machine(), "KEY1");
309		case 1<<2: return input_port_read(space->machine(), "KEY2");
310		case 1<<3: return input_port_read(space->machine(), "KEY3");
	314	case 1<<0: return input_port_read(machine(), "KEY0");
	315	case 1<<1: return input_port_read(machine(), "KEY1");
	316	case 1<<2: return input_port_read(machine(), "KEY2");
	317	case 1<<3: return input_port_read(machine(), "KEY3");
311	318	}
312	319
313	320	return 0;
314	321	}
315	322
316	323
317		static WRITE16_HANDLER( video_regs_w )
	324	WRITE16_MEMBER(srmp6_state::video_regs_w)
318	325	{
319		srmp6_state *state = space->machine().driver_data<srmp6_state>();
320	326
321	327	switch(offset)
322	328	{
323	329
324	330	case 0x5e/2: // bank switch, used by ROM check
325	331	{
326		const UINT8 *rom = space->machine().region("nile")->base();
	332	const UINT8 *rom = machine().region("nile")->base();
327	333	LOG(("%x\n",data));
328		memory_set_bankptr(space->machine(), "bank1",(UINT16 *)(rom + (data & 0x0f)*0x200000));
	334	memory_set_bankptr(machine(), "bank1",(UINT16 *)(rom + (data & 0x0f)*0x200000));
329	335	break;
330	336	}
331	337
r14845	r14846
333	339	case 0x5c/2: // either 0x40 explicitely in many places, or according $2083b0 (IT4)
334	340	//Fade in/out (0x40(dark)-0x60(normal)-0x7e?(bright) reset by 0x00?
335	341	data = (!data)?0x60:(data == 0x5e)?0x60:data;
336		if (state->m_brightness != data) {
337		state->m_brightness = data;
338		update_palette(space->machine());
	342	if (m_brightness != data) {
	343	m_brightness = data;
	344	update_palette(machine());
339	345	}
340	346	break;
341	347
r14845	r14846
350	356	case 0x56/2: // written 8,9,8,9 successively
351	357
352	358	default:
353		logerror("video_regs_w (PC=%06X): %04x = %04x & %04x\n", cpu_get_previouspc(&space->device()), offset*2, data, mem_mask);
	359	logerror("video_regs_w (PC=%06X): %04x = %04x & %04x\n", cpu_get_previouspc(&space.device()), offset*2, data, mem_mask);
354	360	break;
355	361	}
356		COMBINE_DATA(&state->m_video_regs[offset]);
	362	COMBINE_DATA(&m_video_regs[offset]);
357	363	}
358	364
359		static READ16_HANDLER( video_regs_r )
	365	READ16_MEMBER(srmp6_state::video_regs_r)
360	366	{
361		srmp6_state *state = space->machine().driver_data<srmp6_state>();
362	367
363		logerror("video_regs_r (PC=%06X): %04x\n", cpu_get_previouspc(&space->device()), offset*2);
364		return state->m_video_regs[offset];
	368	logerror("video_regs_r (PC=%06X): %04x\n", cpu_get_previouspc(&space.device()), offset*2);
	369	return m_video_regs[offset];
365	370	}
366	371
367	372
r14845	r14846
402	407	}
403	408
404	409
405		static WRITE16_HANDLER(srmp6_dma_w)
	410	WRITE16_MEMBER(srmp6_state::srmp6_dma_w)
406	411	{
407		srmp6_state *state = space->machine().driver_data<srmp6_state>();
408		UINT16* dmaram = state->m_dmaram;
	412	UINT16* dmaram = m_dmaram;
409	413
410	414	COMBINE_DATA(&dmaram[offset]);
411	415	if (offset==13 && dmaram[offset]==0x40)
412	416	{
413		const UINT8 *rom = space->machine().region("nile")->base();
	417	const UINT8 *rom = machine().region("nile")->base();
414	418	UINT32 srctab=2*((((UINT32)dmaram[5])<<16)|dmaram[4]);
415	419	UINT32 srcdata=2*((((UINT32)dmaram[11])<<16)|dmaram[10]);
416	420	UINT32 len=4*(((((UINT32)dmaram[7]&3)<<16)|dmaram[6])+1); //??? WRONG!
r14845	r14846
433	437	dmaram[0x18/2],
434	438	dmaram[0x1a/2]));
435	439
436		state->m_destl = dmaram[9]*0x40000;
	440	m_destl = dmaram[9]*0x40000;
437	441
438		state->m_lastb = 0xfffe;
439		state->m_lastb2 = 0xffff;
	442	m_lastb = 0xfffe;
	443	m_lastb2 = 0xffff;
440	444
441	445	while(1)
442	446	{
r14845	r14846
452	456	{
453	457	UINT8 real_byte;
454	458	real_byte = rom[srctab+p*2];
455		tempidx+=process(space->machine(),real_byte,tempidx);
	459	tempidx+=process(machine(),real_byte,tempidx);
456	460	real_byte = rom[srctab+p*2+1];//px[DMA_XOR((current_table_address+p*2+1))];
457		tempidx+=process(space->machine(),real_byte,tempidx);
	461	tempidx+=process(machine(),real_byte,tempidx);
458	462	}
459	463	else
460	464	{
461		tempidx+=process(space->machine(),p,tempidx);
	465	tempidx+=process(machine(),p,tempidx);
462	466	}
463	467
464	468	ctrl<<=1;
r14845	r14846
476	480	}
477	481
478	482	/* if tileram is actually bigger than the mapped area, how do we access the rest? */
479		static READ16_HANDLER(tileram_r)
	483	READ16_MEMBER(srmp6_state::tileram_r)
480	484	{
481		srmp6_state *state = space->machine().driver_data<srmp6_state>();
482	485
483		return state->m_chrram[offset];
	486	return m_chrram[offset];
484	487	}
485	488
486		static WRITE16_HANDLER(tileram_w)
	489	WRITE16_MEMBER(srmp6_state::tileram_w)
487	490	{
488		srmp6_state *state = space->machine().driver_data<srmp6_state>();
489	491
490	492	//UINT16 tmp;
491		COMBINE_DATA(&state->m_chrram[offset]);
	493	COMBINE_DATA(&m_chrram[offset]);
492	494
493	495	/* are the DMA registers enabled some other way, or always mapped here, over RAM? */
494	496	if (offset >= 0xfff00/2 && offset <= 0xfff1a/2 )
r14845	r14846
498	500	}
499	501	}
500	502
501		static WRITE16_HANDLER(paletteram_w)
	503	WRITE16_MEMBER(srmp6_state::paletteram_w)
502	504	{
503		srmp6_state *state = space->machine().driver_data<srmp6_state>();
504	505	INT8 r, g, b;
505		int brg = state->m_brightness - 0x60;
	506	int brg = m_brightness - 0x60;
506	507
507	508	paletteram16_xBBBBBGGGGGRRRRR_word_w(space, offset, data, mem_mask);
508	509
r14845	r14846
529	530	if(b > 0x1F) b = 0x1F;
530	531	}
531	532
532		palette_set_color(space->machine(), offset, MAKE_RGB(r << 3, g << 3, b << 3));
	533	palette_set_color(machine(), offset, MAKE_RGB(r << 3, g << 3, b << 3));
533	534	}
534	535	}
535	536
536		static READ16_HANDLER( srmp6_irq_ack_r )
	537	READ16_MEMBER(srmp6_state::srmp6_irq_ack_r)
537	538	{
538		cputag_set_input_line(space->machine(), "maincpu", 4, CLEAR_LINE);
	539	cputag_set_input_line(machine(), "maincpu", 4, CLEAR_LINE);
539	540	return 0; // value read doesn't matter
540	541	}
541	542
r14845	r14846
545	546	AM_RANGE(0x600000, 0x7fffff) AM_ROMBANK("bank1")      // banked ROM (used by ROM check)
546	547	AM_RANGE(0x800000, 0x9fffff) AM_ROM AM_REGION("user1", 0)
547	548
548		AM_RANGE(0x300000, 0x300005) AM_READWRITE_LEGACY(srmp6_inputs_r, srmp6_input_select_w)      // inputs
549		AM_RANGE(0x480000, 0x480fff) AM_RAM_WRITE_LEGACY(paletteram_w) AM_BASE_GENERIC(paletteram)
550		AM_RANGE(0x4d0000, 0x4d0001) AM_READ_LEGACY(srmp6_irq_ack_r)
	549	AM_RANGE(0x300000, 0x300005) AM_READWRITE(srmp6_inputs_r, srmp6_input_select_w)      // inputs
	550	AM_RANGE(0x480000, 0x480fff) AM_RAM_WRITE(paletteram_w) AM_BASE_GENERIC(paletteram)
	551	AM_RANGE(0x4d0000, 0x4d0001) AM_READ(srmp6_irq_ack_r)
551	552
552	553	// OBJ RAM: checked [$400000-$47dfff]
553	554	AM_RANGE(0x400000, 0x47ffff) AM_RAM AM_BASE(m_sprram)
554	555
555	556	// CHR RAM: checked [$500000-$5fffff]
556		AM_RANGE(0x500000, 0x5fffff) AM_READWRITE_LEGACY(tileram_r,tileram_w) AM_BASE(m_chrram)
	557	AM_RANGE(0x500000, 0x5fffff) AM_READWRITE(tileram_r,tileram_w) AM_BASE(m_chrram)
557	558	//AM_RANGE(0x5fff00, 0x5fffff) AM_WRITE_LEGACY(dma_w) AM_BASE(m_dmaram)
558	559
559		AM_RANGE(0x4c0000, 0x4c006f) AM_READWRITE_LEGACY(video_regs_r, video_regs_w) AM_BASE(m_video_regs)   // ? gfx regs ST-0026 NiLe
	560	AM_RANGE(0x4c0000, 0x4c006f) AM_READWRITE(video_regs_r, video_regs_w) AM_BASE(m_video_regs)   // ? gfx regs ST-0026 NiLe
560	561	AM_RANGE(0x4e0000, 0x4e00ff) AM_DEVREADWRITE_LEGACY("nile", nile_snd_r, nile_snd_w)
561	562	AM_RANGE(0x4e0100, 0x4e0101) AM_DEVREADWRITE_LEGACY("nile", nile_sndctrl_r, nile_sndctrl_w)
562	563	//AM_RANGE(0x4e0110, 0x4e0111) AM_NOP // ? accessed once ($268dc, written $b.w)

src/mame/drivers/konamim2.c

r14845	r14846
226	226	int m_cde_qchannel_offset;
227	227	cdrom_toc m_cde_toc;
228	228	CDE_DMA m_cde_dma[2];
	229	DECLARE_READ64_MEMBER(irq_enable_r);
	230	DECLARE_WRITE64_MEMBER(irq_enable_w);
	231	DECLARE_READ64_MEMBER(irq_active_r);
	232	DECLARE_READ64_MEMBER(unk1_r);
	233	DECLARE_READ64_MEMBER(unk2_r);
	234	DECLARE_READ64_MEMBER(unk3_r);
	235	DECLARE_READ64_MEMBER(unk4_r);
	236	DECLARE_WRITE64_MEMBER(unk4_w);
	237	DECLARE_READ64_MEMBER(unk30000_r);
	238	DECLARE_READ64_MEMBER(unk30030_r);
	239	DECLARE_WRITE64_MEMBER(video_w);
	240	DECLARE_WRITE64_MEMBER(video_irq_ack_w);
	241	DECLARE_READ64_MEMBER(unk4000280_r);
	242	DECLARE_WRITE64_MEMBER(unk4000010_w);
	243	DECLARE_WRITE64_MEMBER(unk4000418_w);
	244	DECLARE_WRITE64_MEMBER(reset_w);
	245	DECLARE_READ64_MEMBER(cde_r);
	246	DECLARE_WRITE64_MEMBER(cde_w);
	247	DECLARE_READ64_MEMBER(device2_r);
	248	DECLARE_READ64_MEMBER(cpu_r);
229	249	};
230	250
231	251
r14845	r14846
264	284	return 0;
265	285	}
266	286
267		static READ64_HANDLER(irq_enable_r)
	287	READ64_MEMBER(konamim2_state::irq_enable_r)
268	288	{
269		konamim2_state *state = space->machine().driver_data<konamim2_state>();
270	289	UINT64 r = 0;
271	290
272	291	if (ACCESSING_BITS_32_63)
273	292	{
274		r |= (UINT64)(state->m_irq_enable) << 32;
	293	r |= (UINT64)(m_irq_enable) << 32;
275	294	}
276	295
277	296	return r;
278	297	}
279	298
280		static WRITE64_HANDLER(irq_enable_w)
	299	WRITE64_MEMBER(konamim2_state::irq_enable_w)
281	300	{
282		konamim2_state *state = space->machine().driver_data<konamim2_state>();
283	301	if (ACCESSING_BITS_32_63)
284	302	{
285		state->m_irq_enable |= (UINT32)(data >> 32);
	303	m_irq_enable |= (UINT32)(data >> 32);
286	304	}
287	305	}
288	306
289		static READ64_HANDLER(irq_active_r)
	307	READ64_MEMBER(konamim2_state::irq_active_r)
290	308	{
291		konamim2_state *state = space->machine().driver_data<konamim2_state>();
292	309	UINT64 r = 0;
293	310
294	311	if (ACCESSING_BITS_32_63)
295	312	{
296		r |= (UINT64)(state->m_irq_active) << 32;
	313	r |= (UINT64)(m_irq_active) << 32;
297	314	}
298	315
299	316	return r;
r14845	r14846
301	318
302	319
303	320
304		static READ64_HANDLER(unk1_r)
	321	READ64_MEMBER(konamim2_state::unk1_r)
305	322	{
306	323	return U64(0xffffffffffffffff);
307	324	//return 0;
308	325	}
309	326
310	327	#ifdef UNUSED_FUNCTION
311		static READ64_HANDLER(unk2_r)
	328	READ64_MEMBER(konamim2_state::unk2_r)
312	329	{
313	330	if (ACCESSING_BITS_32_63)
314	331	{
r14845	r14846
318	335	}
319	336	#endif
320	337
321		static READ64_HANDLER(unk3_r)
	338	READ64_MEMBER(konamim2_state::unk3_r)
322	339	{
323		konamim2_state *state = space->machine().driver_data<konamim2_state>();
324	340	//return U64(0xffffffffffffffff);
325		return state->m_unk3;
	341	return m_unk3;
326	342	}
327	343
328		static READ64_HANDLER(unk4_r)
	344	READ64_MEMBER(konamim2_state::unk4_r)
329	345	{
330		konamim2_state *state = space->machine().driver_data<konamim2_state>();
331	346	UINT64 r = 0;
332		//  logerror("unk4_r: %08X, %08X%08X at %08X\n", offset, (UINT32)(mem_mask>>32), (UINT32)(mem_mask), cpu_get_pc(&space->device()));
	347	//  logerror("unk4_r: %08X, %08X%08X at %08X\n", offset, (UINT32)(mem_mask>>32), (UINT32)(mem_mask), cpu_get_pc(&space.device()));
333	348
334	349	if (ACCESSING_BITS_32_63)
335	350	{
r14845	r14846
338	353	}
339	354	if (ACCESSING_BITS_0_31)
340	355	{
341		r |= state->m_unk20004 & ~0x800000;
	356	r |= m_unk20004 & ~0x800000;
342	357	}
343	358	return r;
344	359	}
345	360
346		static WRITE64_HANDLER(unk4_w)
	361	WRITE64_MEMBER(konamim2_state::unk4_w)
347	362	{
348		konamim2_state *state = space->machine().driver_data<konamim2_state>();
349	363	//  logerror("unk4_w: %08X%08X, %08X, %08X%08X at %08X\n", (UINT32)(data >> 32), (UINT32)(data),
350		//      offset, (UINT32)(mem_mask>>32), (UINT32)(mem_mask), cpu_get_pc(&space->device()));
	364	//      offset, (UINT32)(mem_mask>>32), (UINT32)(mem_mask), cpu_get_pc(&space.device()));
351	365
352	366	if (ACCESSING_BITS_0_31)
353	367	{
354	368	if (data & 0x800000)
355	369	{
356		//          mame_printf_debug("CPU '%s': CPU1 IRQ at %08X\n", space->device().tag(), cpu_get_pc(&space->device()));
357		cputag_set_input_line(space->machine(), "sub", INPUT_LINE_IRQ0, ASSERT_LINE);
	370	//          mame_printf_debug("CPU '%s': CPU1 IRQ at %08X\n", device().tag(), cpu_get_pc(&space.device()));
	371	cputag_set_input_line(machine(), "sub", INPUT_LINE_IRQ0, ASSERT_LINE);
358	372	}
359	373
360		state->m_unk20004 = (UINT32)(data);
	374	m_unk20004 = (UINT32)(data);
361	375	return;
362	376	}
363	377	}
364	378
365		static READ64_HANDLER(unk30000_r)
	379	READ64_MEMBER(konamim2_state::unk30000_r)
366	380	{
367		konamim2_state *state = space->machine().driver_data<konamim2_state>();
368		state->m_counter1++;
369		return (UINT64)(state->m_counter1 & 0x7f) << 32;
	381	m_counter1++;
	382	return (UINT64)(m_counter1 & 0x7f) << 32;
370	383	}
371	384
372		static READ64_HANDLER(unk30030_r)
	385	READ64_MEMBER(konamim2_state::unk30030_r)
373	386	{
374	387	if (ACCESSING_BITS_0_31)
375	388	{
r14845	r14846
378	391	return 0;
379	392	}
380	393
381		static WRITE64_HANDLER(video_w)
	394	WRITE64_MEMBER(konamim2_state::video_w)
382	395	{
383		konamim2_state *state = space->machine().driver_data<konamim2_state>();
384	396	if (ACCESSING_BITS_32_63)
385	397	{
386		state->m_vdl0_address = (UINT32)(data >> 32);
	398	m_vdl0_address = (UINT32)(data >> 32);
387	399	}
388	400	if (ACCESSING_BITS_0_31)
389	401	{
390		state->m_vdl1_address = (UINT32)(data);
	402	m_vdl1_address = (UINT32)(data);
391	403	}
392	404	}
393	405
394		static WRITE64_HANDLER(video_irq_ack_w)
	406	WRITE64_MEMBER(konamim2_state::video_irq_ack_w)
395	407	{
396		konamim2_state *state = space->machine().driver_data<konamim2_state>();
397	408	if (ACCESSING_BITS_32_63)
398	409	{
399	410	if ((data >> 32) & 0x8000)
400	411	{
401		state->m_irq_active &= ~0x800000;
	412	m_irq_active &= ~0x800000;
402	413	}
403	414	}
404	415	}
405	416
406	417
407	418
408		static READ64_HANDLER(unk4000280_r)
	419	READ64_MEMBER(konamim2_state::unk4000280_r)
409	420	{
410	421	// SysCfg
411	422
r14845	r14846
429	440
430	441	}
431	442
432		static WRITE64_HANDLER(unk4000010_w)
	443	WRITE64_MEMBER(konamim2_state::unk4000010_w)
433	444	{
434	445	if ((data & 0xff) == 0xd)
435	446	{
r14845	r14846
441	452	}
442	453	}
443	454
444		static WRITE64_HANDLER(unk4000418_w)
	455	WRITE64_MEMBER(konamim2_state::unk4000418_w)
445	456	{
446	457	}
447	458
448		static WRITE64_HANDLER(reset_w)
	459	WRITE64_MEMBER(konamim2_state::reset_w)
449	460	{
450		konamim2_state *state = space->machine().driver_data<konamim2_state>();
451	461	if (ACCESSING_BITS_32_63)
452	462	{
453	463	if (data & U64(0x100000000))
454	464	{
455		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE);
456		state->m_unk3 = 0;
	465	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE);
	466	m_unk3 = 0;
457	467	}
458	468	}
459	469	}
r14845	r14846
832	842	}
833	843	}
834	844
835		static READ64_HANDLER(cde_r)
	845	READ64_MEMBER(konamim2_state::cde_r)
836	846	{
837		konamim2_state *state = space->machine().driver_data<konamim2_state>();
838	847	UINT32 r = 0;
839	848	int reg = offset * 2;
840	849
r14845	r14846
852	861	{
853	862	r = 0x100038;
854	863
855		r |= state->m_cde_dma[0].dma_done ? 0x400 : 0;
856		r |= state->m_cde_dma[1].dma_done ? 0x800 : 0;
	864	r |= m_cde_dma[0].dma_done ? 0x400 : 0;
	865	r |= m_cde_dma[1].dma_done ? 0x800 : 0;
857	866	break;
858	867	}
859	868	case 0x02c/4:
860	869	{
861		r = state->m_cde_status_bytes[state->m_cde_status_byte_ptr++];
	870	r = m_cde_status_bytes[m_cde_status_byte_ptr++];
862	871
863		if (state->m_cde_status_byte_ptr <= state->m_cde_num_status_bytes)
	872	if (m_cde_status_byte_ptr <= m_cde_num_status_bytes)
864	873	{
865	874	r |= 0x100;
866	875	}
867	876	else
868	877	{
869	878	//if (cde_enable_reports &&
870		//  !state->m_cde_response &&
871		//  state->m_cde_command_bytes[0] != ((cde_report_type >> 8) & 0xff))
	879	//  !m_cde_response &&
	880	//  m_cde_command_bytes[0] != ((cde_report_type >> 8) & 0xff))
872	881
873		if (!state->m_cde_response)
	882	if (!m_cde_response)
874	883	{
875		cde_handle_reports(space->machine());
	884	cde_handle_reports(machine());
876	885
877		//      state->m_cde_command_byte_ptr = 0;
878		//      state->m_cde_command_bytes[state->m_cde_command_byte_ptr++] = 0x1c;
	886	//      m_cde_command_byte_ptr = 0;
	887	//      m_cde_command_bytes[m_cde_command_byte_ptr++] = 0x1c;
879	888
880		//      state->m_cde_response = 1;
	889	//      m_cde_response = 1;
881	890	}
882	891	}
883	892
884		//      printf("status byte %d\n", state->m_cde_status_byte_ptr);
	893	//      printf("status byte %d\n", m_cde_status_byte_ptr);
885	894	break;
886	895	}
887	896
r14845	r14846
893	902
894	903	default:
895	904	{
896		//                      mame_printf_debug("cde_r: %08X at %08X\n", reg*4, cpu_get_pc(&space->device()));
	905	//                      mame_printf_debug("cde_r: %08X at %08X\n", reg*4, cpu_get_pc(&space.device()));
897	906	break;
898	907	}
899	908	}
r14845	r14846
908	917	}
909	918	}
910	919
911		static WRITE64_HANDLER(cde_w)
	920	WRITE64_MEMBER(konamim2_state::cde_w)
912	921	{
913		konamim2_state *state = space->machine().driver_data<konamim2_state>();
914	922	int reg = offset * 2;
915	923	UINT32 d;
916	924
r14845	r14846
928	936	{
929	937	case 0x028/4:      // Command write
930	938	{
931		//printf("cde_w: %08X, %08X at %08X\n", d, reg*4, cpu_get_pc(&space->device()));
	939	//printf("cde_w: %08X, %08X at %08X\n", d, reg*4, cpu_get_pc(&space.device()));
932	940
933	941	if (d == 0x0180)
934	942	{
935		if (state->m_cde_response)
	943	if (m_cde_response)
936	944	{
937		cde_handle_command(space->machine());
	945	cde_handle_command(machine());
938	946
939		state->m_cde_response = 0;
	947	m_cde_response = 0;
940	948	}
941	949
942		state->m_cde_command_byte_ptr = 0;
	950	m_cde_command_byte_ptr = 0;
943	951	}
944		else if (state->m_cde_command_byte_ptr == 0)
	952	else if (m_cde_command_byte_ptr == 0)
945	953	{
946		state->m_cde_num_status_bytes = 1;
	954	m_cde_num_status_bytes = 1;
947	955
948		state->m_cde_status_bytes[0] = d & 0xff;
949		state->m_cde_status_byte_ptr = 0;
	956	m_cde_status_bytes[0] = d & 0xff;
	957	m_cde_status_byte_ptr = 0;
950	958
951		state->m_cde_response = 1;
	959	m_cde_response = 1;
952	960	}
953	961
954	962	if (d != 0x180)
955	963	{
956		state->m_cde_command_bytes[state->m_cde_command_byte_ptr++] = d;
	964	m_cde_command_bytes[m_cde_command_byte_ptr++] = d;
957	965	}
958	966
959	967	break;
r14845	r14846
965	973
966	974	if (d & 0x20)
967	975	{
968		state->m_cde_dma[0].dma_done = 1;
	976	m_cde_dma[0].dma_done = 1;
969	977
970		cde_dma_transfer(space, 0, 0);
	978	cde_dma_transfer(&space, 0, 0);
971	979	}
972	980	if (d & 0x40)
973	981	{
974		state->m_cde_dma[0].dma_done = 1;
	982	m_cde_dma[0].dma_done = 1;
975	983
976		cde_dma_transfer(space, 0, 1);
	984	cde_dma_transfer(&space, 0, 1);
977	985	}
978	986	break;
979	987	}
r14845	r14846
981	989	{
982	990	//          mame_printf_debug("CDE: DMA0 dst addr %08X\n", d);
983	991
984		state->m_cde_dma[0].dst_addr = d;
	992	m_cde_dma[0].dst_addr = d;
985	993	break;
986	994	}
987	995	case 0x30c/4:      // DMA Channel 0 length?
988	996	{
989	997	//          mame_printf_debug("CDE: DMA0 length %08X\n", d);
990	998
991		state->m_cde_dma[0].length = d;
	999	m_cde_dma[0].length = d;
992	1000	break;
993	1001	}
994	1002	case 0x318/4:      // DMA Channel 0 next destination address
995	1003	{
996	1004	//          mame_printf_debug("CDE: DMA0 next dst addr %08X\n", d);
997	1005
998		state->m_cde_dma[0].next_dst_addr = d;
	1006	m_cde_dma[0].next_dst_addr = d;
999	1007	break;
1000	1008	}
1001	1009	case 0x31c/4:      // DMA Channel 0 next length?
1002	1010	{
1003	1011	//          mame_printf_debug("CDE: DMA0 next length %08X\n", d);
1004	1012
1005		state->m_cde_dma[0].next_length = d;
	1013	m_cde_dma[0].next_length = d;
1006	1014	break;
1007	1015	}
1008	1016
r14845	r14846
1015	1023	{
1016	1024	//          mame_printf_debug("CDE: DMA1 dst addr %08X\n", d);
1017	1025
1018		state->m_cde_dma[1].dst_addr = d;
	1026	m_cde_dma[1].dst_addr = d;
1019	1027	break;
1020	1028	}
1021	1029	case 0x32c/4:      // DMA Channel 1 length?
1022	1030	{
1023	1031	//          mame_printf_debug("CDE: DMA1 length %08X\n", d);
1024	1032
1025		state->m_cde_dma[1].length = d;
	1033	m_cde_dma[1].length = d;
1026	1034	break;
1027	1035	}
1028	1036	case 0x338/4:      // DMA Channel 1 next destination address
1029	1037	{
1030	1038	//          mame_printf_debug("CDE: DMA1 next dst addr %08X\n", d);
1031	1039
1032		state->m_cde_dma[1].next_dst_addr = d;
	1040	m_cde_dma[1].next_dst_addr = d;
1033	1041	break;
1034	1042	}
1035	1043	case 0x33c/4:      // DMA Channel 1 next length?
1036	1044	{
1037	1045	//          mame_printf_debug("CDE: DMA1 next length %08X\n", d);
1038	1046
1039		state->m_cde_dma[1].next_length = d;
	1047	m_cde_dma[1].next_length = d;
1040	1048	break;
1041	1049	}
1042	1050
r14845	r14846
1044	1052	{
1045	1053	if (d & 0x80000000)
1046	1054	{
1047		state->m_irq_active &= ~0x8;
	1055	m_irq_active &= ~0x8;
1048	1056	}
1049	1057	if (d & 0x60000000)
1050	1058	{
1051		state->m_cde_dma[0].dma_done = 0;
1052		state->m_cde_dma[1].dma_done = 0;
	1059	m_cde_dma[0].dma_done = 0;
	1060	m_cde_dma[1].dma_done = 0;
1053	1061	}
1054	1062	break;
1055	1063	}
1056	1064
1057	1065	default:
1058	1066	{
1059		//                      mame_printf_debug("cde_w: %08X, %08X at %08X\n", d, reg*4, cpu_get_pc(&space->device()));
	1067	//                      mame_printf_debug("cde_w: %08X, %08X at %08X\n", d, reg*4, cpu_get_pc(&space.device()));
1060	1068	break;
1061	1069	}
1062	1070	}
1063	1071	}
1064	1072
1065		static READ64_HANDLER(device2_r)
	1073	READ64_MEMBER(konamim2_state::device2_r)
1066	1074	{
1067	1075	UINT32 r = 0;
1068	1076	int reg = offset * 2;
r14845	r14846
1093	1101	}
1094	1102	}
1095	1103
1096		static READ64_HANDLER(cpu_r)
	1104	READ64_MEMBER(konamim2_state::cpu_r)
1097	1105	{
1098	1106	UINT64 r = 0;
1099	1107
1100	1108	if (ACCESSING_BITS_32_63)
1101	1109	{
1102		r = (UINT64)((&space->device() != space->machine().device("maincpu")) ? 0x80000000 : 0);
	1110	r = (UINT64)((&space.device() != machine().device("maincpu")) ? 0x80000000 : 0);
1103	1111	//r |= 0x40000000;  // sets Video-LowRes !?
1104	1112	return r << 32;
1105	1113	}
r14845	r14846
1108	1116	}
1109	1117
1110	1118	static ADDRESS_MAP_START( m2_main, AS_PROGRAM, 64, konamim2_state )
1111		AM_RANGE(0x00010040, 0x00010047) AM_READWRITE_LEGACY(irq_enable_r, irq_enable_w)
1112		AM_RANGE(0x00010050, 0x00010057) AM_READ_LEGACY(irq_active_r)
1113		AM_RANGE(0x00020000, 0x00020007) AM_READWRITE_LEGACY(unk4_r, unk4_w)
1114		AM_RANGE(0x00030000, 0x00030007) AM_READ_LEGACY(unk30000_r)
1115		AM_RANGE(0x00030010, 0x00030017) AM_WRITE_LEGACY(video_w)
1116		AM_RANGE(0x00030030, 0x00030037) AM_READ_LEGACY(unk30030_r)
1117		AM_RANGE(0x00030400, 0x00030407) AM_WRITE_LEGACY(video_irq_ack_w)
1118		AM_RANGE(0x01000000, 0x01000fff) AM_READWRITE_LEGACY(cde_r, cde_w)
1119		AM_RANGE(0x02000000, 0x02000fff) AM_READ_LEGACY(device2_r)
1120		AM_RANGE(0x04000010, 0x04000017) AM_WRITE_LEGACY(unk4000010_w)
1121		AM_RANGE(0x04000018, 0x0400001f) AM_READ_LEGACY(unk1_r)
1122		AM_RANGE(0x04000020, 0x04000027) AM_WRITE_LEGACY(reset_w)
1123		AM_RANGE(0x04000418, 0x0400041f) AM_WRITE_LEGACY(unk4000418_w)
1124		AM_RANGE(0x04000208, 0x0400020f) AM_READ_LEGACY(unk3_r)
1125		AM_RANGE(0x04000280, 0x04000287) AM_READ_LEGACY(unk4000280_r)
1126		AM_RANGE(0x10000000, 0x10000007) AM_READ_LEGACY(cpu_r)
	1119	AM_RANGE(0x00010040, 0x00010047) AM_READWRITE(irq_enable_r, irq_enable_w)
	1120	AM_RANGE(0x00010050, 0x00010057) AM_READ(irq_active_r)
	1121	AM_RANGE(0x00020000, 0x00020007) AM_READWRITE(unk4_r, unk4_w)
	1122	AM_RANGE(0x00030000, 0x00030007) AM_READ(unk30000_r)
	1123	AM_RANGE(0x00030010, 0x00030017) AM_WRITE(video_w)
	1124	AM_RANGE(0x00030030, 0x00030037) AM_READ(unk30030_r)
	1125	AM_RANGE(0x00030400, 0x00030407) AM_WRITE(video_irq_ack_w)
	1126	AM_RANGE(0x01000000, 0x01000fff) AM_READWRITE(cde_r, cde_w)
	1127	AM_RANGE(0x02000000, 0x02000fff) AM_READ(device2_r)
	1128	AM_RANGE(0x04000010, 0x04000017) AM_WRITE(unk4000010_w)
	1129	AM_RANGE(0x04000018, 0x0400001f) AM_READ(unk1_r)
	1130	AM_RANGE(0x04000020, 0x04000027) AM_WRITE(reset_w)
	1131	AM_RANGE(0x04000418, 0x0400041f) AM_WRITE(unk4000418_w)
	1132	AM_RANGE(0x04000208, 0x0400020f) AM_READ(unk3_r)
	1133	AM_RANGE(0x04000280, 0x04000287) AM_READ(unk4000280_r)
	1134	AM_RANGE(0x10000000, 0x10000007) AM_READ(cpu_r)
1127	1135	AM_RANGE(0x10000008, 0x10001007) AM_NOP      // ???
1128	1136	AM_RANGE(0x20000000, 0x201fffff) AM_ROM AM_SHARE("share2")
1129	1137	AM_RANGE(0x40000000, 0x407fffff) AM_RAM AM_SHARE("share3") AM_BASE(m_main_ram)

src/mame/drivers/cball.c

r14845	r14846
22	22
23	23	/* devices */
24	24	device_t *m_maincpu;
	25	DECLARE_WRITE8_MEMBER(cball_vram_w);
	26	DECLARE_READ8_MEMBER(cball_wram_r);
	27	DECLARE_WRITE8_MEMBER(cball_wram_w);
25	28	};
26	29
27	30
r14845	r14846
34	37	}
35	38
36	39
37		static WRITE8_HANDLER( cball_vram_w )
	40	WRITE8_MEMBER(cball_state::cball_vram_w)
38	41	{
39		cball_state *state = space->machine().driver_data<cball_state>();
40	42
41		state->m_video_ram[offset] = data;
42		state->m_bg_tilemap->mark_tile_dirty(offset);
	43	m_video_ram[offset] = data;
	44	m_bg_tilemap->mark_tile_dirty(offset);
43	45	}
44	46
45	47
r14845	r14846
107	109	}
108	110
109	111
110		static READ8_HANDLER( cball_wram_r )
	112	READ8_MEMBER(cball_state::cball_wram_r)
111	113	{
112		cball_state *state = space->machine().driver_data<cball_state>();
113	114
114		return state->m_video_ram[0x380 + offset];
	115	return m_video_ram[0x380 + offset];
115	116	}
116	117
117	118
118		static WRITE8_HANDLER( cball_wram_w )
	119	WRITE8_MEMBER(cball_state::cball_wram_w)
119	120	{
120		cball_state *state = space->machine().driver_data<cball_state>();
121	121
122		state->m_video_ram[0x380 + offset] = data;
	122	m_video_ram[0x380 + offset] = data;
123	123	}
124	124
125	125
r14845	r14846
127	127	static ADDRESS_MAP_START( cpu_map, AS_PROGRAM, 8, cball_state )
128	128	ADDRESS_MAP_GLOBAL_MASK(0x7fff)
129	129
130		AM_RANGE(0x0000, 0x03ff) AM_READ_LEGACY(cball_wram_r) AM_MASK(0x7f)
	130	AM_RANGE(0x0000, 0x03ff) AM_READ(cball_wram_r) AM_MASK(0x7f)
131	131	AM_RANGE(0x0400, 0x07ff) AM_READONLY
132	132	AM_RANGE(0x1001, 0x1001) AM_READ_PORT("1001")
133	133	AM_RANGE(0x1003, 0x1003) AM_READ_PORT("1003")
r14845	r14846
137	137	AM_RANGE(0x2000, 0x2001) AM_NOP
138	138	AM_RANGE(0x2800, 0x2800) AM_READ_PORT("2800")
139	139
140		AM_RANGE(0x0000, 0x03ff) AM_WRITE_LEGACY(cball_wram_w) AM_MASK(0x7f)
141		AM_RANGE(0x0400, 0x07ff) AM_WRITE_LEGACY(cball_vram_w) AM_BASE(m_video_ram)
	140	AM_RANGE(0x0000, 0x03ff) AM_WRITE(cball_wram_w) AM_MASK(0x7f)
	141	AM_RANGE(0x0400, 0x07ff) AM_WRITE(cball_vram_w) AM_BASE(m_video_ram)
142	142	AM_RANGE(0x1800, 0x1800) AM_NOP /* watchdog? */
143	143	AM_RANGE(0x1810, 0x1811) AM_NOP
144	144	AM_RANGE(0x1820, 0x1821) AM_NOP

src/mame/drivers/slotcarn.c

r14845	r14846
41	41	UINT8 *m_ram_video;
42	42	UINT8 *m_ram_palette;
43	43	UINT8 *m_backup_ram;
	44	DECLARE_READ8_MEMBER(palette_r);
	45	DECLARE_WRITE8_MEMBER(palette_w);
44	46	};
45	47
46	48
r14845	r14846
54	56
55	57	*/
56	58
57		static READ8_HANDLER( palette_r )
	59	READ8_MEMBER(slotcarn_state::palette_r)
58	60	{
59		slotcarn_state *state = space->machine().driver_data<slotcarn_state>();
60	61	int co;
61	62
62		co = ((state->m_ram_attr[offset] & 0x7F) << 3) | (offset & 0x07);
63		return state->m_ram_palette[co];
	63	co = ((m_ram_attr[offset] & 0x7F) << 3) | (offset & 0x07);
	64	return m_ram_palette[co];
64	65	}
65	66
66		static WRITE8_HANDLER( palette_w )
	67	WRITE8_MEMBER(slotcarn_state::palette_w)
67	68	{
68		slotcarn_state *state = space->machine().driver_data<slotcarn_state>();
69	69	int co;
70	70
71		space->machine().primary_screen->update_now();
	71	machine().primary_screen->update_now();
72	72	data &= 0x0f;
73	73
74		co = ((state->m_ram_attr[offset] & 0x7F) << 3) | (offset & 0x07);
75		state->m_ram_palette[co] = data;
	74	co = ((m_ram_attr[offset] & 0x7F) << 3) | (offset & 0x07);
	75	m_ram_palette[co] = data;
76	76
77	77	}
78	78
r14845	r14846
203	203
204	204	AM_RANGE(0xe800, 0xefff) AM_RAM AM_BASE(m_ram_attr)
205	205	AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_BASE(m_ram_video)
206		AM_RANGE(0xf800, 0xfbff) AM_READWRITE_LEGACY(palette_r, palette_w)
	206	AM_RANGE(0xf800, 0xfbff) AM_READWRITE(palette_r, palette_w)
207	207	ADDRESS_MAP_END
208	208
209	209	// spielbud - is the ay mirrored, or are there now 2?

src/mame/drivers/rabbit.c

r14845	r14846
111	111	UINT32 *m_tilemap_ram[4];
112	112	UINT32 *m_spriteram;
113	113	tilemap_t *m_tilemap[4];
	114	DECLARE_WRITE32_MEMBER(rabbit_tilemap0_w);
	115	DECLARE_WRITE32_MEMBER(rabbit_tilemap1_w);
	116	DECLARE_WRITE32_MEMBER(rabbit_tilemap2_w);
	117	DECLARE_WRITE32_MEMBER(rabbit_tilemap3_w);
	118	DECLARE_WRITE32_MEMBER(rabbit_paletteram_dword_w);
	119	DECLARE_READ32_MEMBER(rabbit_tilemap0_r);
	120	DECLARE_READ32_MEMBER(rabbit_tilemap1_r);
	121	DECLARE_READ32_MEMBER(rabbit_tilemap2_r);
	122	DECLARE_READ32_MEMBER(rabbit_tilemap3_r);
	123	DECLARE_READ32_MEMBER(randomrabbits);
	124	DECLARE_WRITE32_MEMBER(rabbit_rombank_w);
	125	DECLARE_WRITE32_MEMBER(rabbit_audio_w);
	126	DECLARE_WRITE32_MEMBER(rabbit_blitter_w);
114	127	};
115	128
116	129
r14845	r14846
182	195	get_rabbit_tilemap_info(machine,tileinfo,tile_index,3,0);
183	196	}
184	197
185		static WRITE32_HANDLER( rabbit_tilemap0_w )
	198	WRITE32_MEMBER(rabbit_state::rabbit_tilemap0_w)
186	199	{
187		rabbit_state *state = space->machine().driver_data<rabbit_state>();
188		COMBINE_DATA(&state->m_tilemap_ram[0][offset]);
189		state->m_tilemap[0]->mark_tile_dirty(offset);
	200	COMBINE_DATA(&m_tilemap_ram[0][offset]);
	201	m_tilemap[0]->mark_tile_dirty(offset);
190	202	}
191	203
192		static WRITE32_HANDLER( rabbit_tilemap1_w )
	204	WRITE32_MEMBER(rabbit_state::rabbit_tilemap1_w)
193	205	{
194		rabbit_state *state = space->machine().driver_data<rabbit_state>();
195		COMBINE_DATA(&state->m_tilemap_ram[1][offset]);
196		state->m_tilemap[1]->mark_tile_dirty(offset);
	206	COMBINE_DATA(&m_tilemap_ram[1][offset]);
	207	m_tilemap[1]->mark_tile_dirty(offset);
197	208	}
198	209
199		static WRITE32_HANDLER( rabbit_tilemap2_w )
	210	WRITE32_MEMBER(rabbit_state::rabbit_tilemap2_w)
200	211	{
201		rabbit_state *state = space->machine().driver_data<rabbit_state>();
202		COMBINE_DATA(&state->m_tilemap_ram[2][offset]);
203		state->m_tilemap[2]->mark_tile_dirty(offset);
	212	COMBINE_DATA(&m_tilemap_ram[2][offset]);
	213	m_tilemap[2]->mark_tile_dirty(offset);
204	214	}
205	215
206	216
207		static WRITE32_HANDLER( rabbit_tilemap3_w )
	217	WRITE32_MEMBER(rabbit_state::rabbit_tilemap3_w)
208	218	{
209		rabbit_state *state = space->machine().driver_data<rabbit_state>();
210		COMBINE_DATA(&state->m_tilemap_ram[3][offset]);
211		state->m_tilemap[3]->mark_tile_dirty(offset);
	219	COMBINE_DATA(&m_tilemap_ram[3][offset]);
	220	m_tilemap[3]->mark_tile_dirty(offset);
212	221	}
213	222
214	223	/*
r14845	r14846
465	474	}
466	475
467	476
468		static WRITE32_HANDLER( rabbit_paletteram_dword_w )
	477	WRITE32_MEMBER(rabbit_state::rabbit_paletteram_dword_w)
469	478	{
470	479	int r,g,b;
471		COMBINE_DATA(&space->machine().generic.paletteram.u32[offset]);
	480	COMBINE_DATA(&machine().generic.paletteram.u32[offset]);
472	481
473		b = ((space->machine().generic.paletteram.u32[offset] & 0x000000ff) >>0);
474		r = ((space->machine().generic.paletteram.u32[offset] & 0x0000ff00) >>8);
475		g = ((space->machine().generic.paletteram.u32[offset] & 0x00ff0000) >>16);
	482	b = ((machine().generic.paletteram.u32[offset] & 0x000000ff) >>0);
	483	r = ((machine().generic.paletteram.u32[offset] & 0x0000ff00) >>8);
	484	g = ((machine().generic.paletteram.u32[offset] & 0x00ff0000) >>16);
476	485
477		palette_set_color(space->machine(),offset,MAKE_RGB(r,g,b));
	486	palette_set_color(machine(),offset,MAKE_RGB(r,g,b));
478	487	}
479	488
480		static READ32_HANDLER( rabbit_tilemap0_r )
	489	READ32_MEMBER(rabbit_state::rabbit_tilemap0_r)
481	490	{
482		rabbit_state *state = space->machine().driver_data<rabbit_state>();
483		return state->m_tilemap_ram[0][offset];
	491	return m_tilemap_ram[0][offset];
484	492	}
485	493
486		static READ32_HANDLER( rabbit_tilemap1_r )
	494	READ32_MEMBER(rabbit_state::rabbit_tilemap1_r)
487	495	{
488		rabbit_state *state = space->machine().driver_data<rabbit_state>();
489		return state->m_tilemap_ram[1][offset];
	496	return m_tilemap_ram[1][offset];
490	497	}
491	498
492		static READ32_HANDLER( rabbit_tilemap2_r )
	499	READ32_MEMBER(rabbit_state::rabbit_tilemap2_r)
493	500	{
494		rabbit_state *state = space->machine().driver_data<rabbit_state>();
495		return state->m_tilemap_ram[2][offset];
	501	return m_tilemap_ram[2][offset];
496	502	}
497	503
498		static READ32_HANDLER( rabbit_tilemap3_r )
	504	READ32_MEMBER(rabbit_state::rabbit_tilemap3_r)
499	505	{
500		rabbit_state *state = space->machine().driver_data<rabbit_state>();
501		return state->m_tilemap_ram[3][offset];
	506	return m_tilemap_ram[3][offset];
502	507	}
503	508
504		static READ32_HANDLER( randomrabbits )
	509	READ32_MEMBER(rabbit_state::randomrabbits)
505	510	{
506		return space->machine().rand();
	511	return machine().rand();
507	512	}
508	513
509	514	/* rom bank is used when testing roms, not currently hooked up */
510		static WRITE32_HANDLER ( rabbit_rombank_w )
	515	WRITE32_MEMBER(rabbit_state::rabbit_rombank_w)
511	516	{
512		UINT8 *dataroms = space->machine().region("gfx1")->base();
	517	UINT8 *dataroms = machine().region("gfx1")->base();
513	518	#if 0
514	519	int bank;
515	520	printf("rabbit rombank %08x\n",data);
516	521	bank = data & 0x3ff;
517	522
518		memory_set_bankptr(space->machine(), "bank1",&dataroms[0x40000*(bank&0x3ff)]);
	523	memory_set_bankptr(machine(), "bank1",&dataroms[0x40000*(bank&0x3ff)]);
519	524	#else
520		memory_set_bankptr(space->machine(), "bank1",&dataroms[0]);
	525	memory_set_bankptr(machine(), "bank1",&dataroms[0]);
521	526	#endif
522	527
523	528	}
r14845	r14846
540	545	time (timer?  the game seems to "play music" fine with just the VBL).
541	546	*/
542	547
543		static WRITE32_HANDLER( rabbit_audio_w )
	548	WRITE32_MEMBER(rabbit_state::rabbit_audio_w)
544	549	{
545	550	int reg, voice, base, i;
546	551
r14845	r14846
703	708
704	709
705	710
706		static WRITE32_HANDLER( rabbit_blitter_w )
	711	WRITE32_MEMBER(rabbit_state::rabbit_blitter_w)
707	712	{
708		rabbit_state *state = space->machine().driver_data<rabbit_state>();
709		COMBINE_DATA(&state->m_blitterregs[offset]);
	713	COMBINE_DATA(&m_blitterregs[offset]);
710	714
711	715	if (offset == 0x0c/4)
712	716	{
713		rabbit_do_blit(space->machine());
	717	rabbit_do_blit(machine());
714	718	}
715	719	}
716	720
r14845	r14846
739	743	AM_RANGE(0x000024, 0x000027) AM_WRITENOP // bug in code / emulation?
740	744	AM_RANGE(0x00719c, 0x00719f) AM_WRITENOP // bug in code / emulation?
741	745	AM_RANGE(0x200000, 0x200003) AM_READ_PORT("INPUTS") AM_DEVWRITE_LEGACY("eeprom", rabbit_eeprom_write)
742		AM_RANGE(0x400010, 0x400013) AM_READ_LEGACY(randomrabbits) // gfx chip status?
743		AM_RANGE(0x400980, 0x400983) AM_READ_LEGACY(randomrabbits) // sound chip status?
744		AM_RANGE(0x400984, 0x400987) AM_READ_LEGACY(randomrabbits) // sound chip status?
	746	AM_RANGE(0x400010, 0x400013) AM_READ(randomrabbits) // gfx chip status?
	747	AM_RANGE(0x400980, 0x400983) AM_READ(randomrabbits) // sound chip status?
	748	AM_RANGE(0x400984, 0x400987) AM_READ(randomrabbits) // sound chip status?
745	749	/* this lot are probably gfxchip/blitter etc. related */
746	750	AM_RANGE(0x400010, 0x400013) AM_WRITEONLY AM_BASE(m_viewregs0 )
747	751	AM_RANGE(0x400100, 0x400117) AM_WRITEONLY AM_BASE(m_tilemap_regs[0] ) // tilemap regs1
r14845	r14846
749	753	AM_RANGE(0x400140, 0x400157) AM_WRITEONLY AM_BASE(m_tilemap_regs[2] ) // tilemap regs3
750	754	AM_RANGE(0x400160, 0x400177) AM_WRITEONLY AM_BASE(m_tilemap_regs[3] ) // tilemap regs4
751	755	AM_RANGE(0x400200, 0x40021b) AM_WRITEONLY AM_BASE(m_spriteregs ) // sprregs?
752		AM_RANGE(0x400300, 0x400303) AM_WRITE_LEGACY(rabbit_rombank_w) // used during rom testing, rombank/area select + something else?
	756	AM_RANGE(0x400300, 0x400303) AM_WRITE(rabbit_rombank_w) // used during rom testing, rombank/area select + something else?
753	757	AM_RANGE(0x400400, 0x400413) AM_WRITEONLY AM_BASE(m_viewregs6 ) // some global controls? (brightness etc.?)
754	758	AM_RANGE(0x400500, 0x400503) AM_WRITEONLY AM_BASE(m_viewregs7 )
755		AM_RANGE(0x400700, 0x40070f) AM_WRITE_LEGACY(rabbit_blitter_w) AM_BASE(m_blitterregs )
	759	AM_RANGE(0x400700, 0x40070f) AM_WRITE(rabbit_blitter_w) AM_BASE(m_blitterregs )
756	760	AM_RANGE(0x400800, 0x40080f) AM_WRITEONLY AM_BASE(m_viewregs9 ) // never changes?
757		AM_RANGE(0x400900, 0x40098f) AM_WRITE_LEGACY(rabbit_audio_w)
	761	AM_RANGE(0x400900, 0x40098f) AM_WRITE(rabbit_audio_w)
758	762	/* hmm */
759	763	AM_RANGE(0x479700, 0x479713) AM_WRITEONLY AM_BASE(m_viewregs10 )
760	764
761	765	AM_RANGE(0x440000, 0x47ffff) AM_ROMBANK("bank1") // data (gfx / sound) rom readback for ROM testing
762	766	/* tilemaps */
763		AM_RANGE(0x480000, 0x483fff) AM_READWRITE_LEGACY(rabbit_tilemap0_r,rabbit_tilemap0_w)
764		AM_RANGE(0x484000, 0x487fff) AM_READWRITE_LEGACY(rabbit_tilemap1_r,rabbit_tilemap1_w)
765		AM_RANGE(0x488000, 0x48bfff) AM_READWRITE_LEGACY(rabbit_tilemap2_r,rabbit_tilemap2_w)
766		AM_RANGE(0x48c000, 0x48ffff) AM_READWRITE_LEGACY(rabbit_tilemap3_r,rabbit_tilemap3_w)
	767	AM_RANGE(0x480000, 0x483fff) AM_READWRITE(rabbit_tilemap0_r,rabbit_tilemap0_w)
	768	AM_RANGE(0x484000, 0x487fff) AM_READWRITE(rabbit_tilemap1_r,rabbit_tilemap1_w)
	769	AM_RANGE(0x488000, 0x48bfff) AM_READWRITE(rabbit_tilemap2_r,rabbit_tilemap2_w)
	770	AM_RANGE(0x48c000, 0x48ffff) AM_READWRITE(rabbit_tilemap3_r,rabbit_tilemap3_w)
767	771	AM_RANGE(0x494000, 0x497fff) AM_RAM AM_BASE(m_spriteram) // sprites?
768		AM_RANGE(0x4a0000, 0x4affff) AM_RAM_WRITE_LEGACY(rabbit_paletteram_dword_w) AM_BASE_GENERIC(paletteram)
	772	AM_RANGE(0x4a0000, 0x4affff) AM_RAM_WRITE(rabbit_paletteram_dword_w) AM_BASE_GENERIC(paletteram)
769	773	AM_RANGE(0xff0000, 0xffffff) AM_RAM
770	774	ADDRESS_MAP_END
771	775

src/mame/drivers/hvyunit.c

r14845	r14846
99	99	device_t   *m_sound_cpu;
100	100	device_t   *m_mermaid;
101	101	device_t   *m_pandora;
	102	DECLARE_WRITE8_MEMBER(trigger_nmi_on_slave_cpu);
	103	DECLARE_WRITE8_MEMBER(master_bankswitch_w);
	104	DECLARE_WRITE8_MEMBER(mermaid_data_w);
	105	DECLARE_READ8_MEMBER(mermaid_data_r);
	106	DECLARE_READ8_MEMBER(mermaid_status_r);
	107	DECLARE_WRITE8_MEMBER(trigger_nmi_on_sound_cpu2);
	108	DECLARE_WRITE8_MEMBER(hu_videoram_w);
	109	DECLARE_WRITE8_MEMBER(hu_colorram_w);
	110	DECLARE_WRITE8_MEMBER(slave_bankswitch_w);
	111	DECLARE_WRITE8_MEMBER(hu_scrollx_w);
	112	DECLARE_WRITE8_MEMBER(hu_scrolly_w);
	113	DECLARE_WRITE8_MEMBER(coin_count_w);
	114	DECLARE_WRITE8_MEMBER(sound_bankswitch_w);
	115	DECLARE_READ8_MEMBER(mermaid_p0_r);
	116	DECLARE_WRITE8_MEMBER(mermaid_p0_w);
	117	DECLARE_READ8_MEMBER(mermaid_p1_r);
	118	DECLARE_WRITE8_MEMBER(mermaid_p1_w);
	119	DECLARE_READ8_MEMBER(mermaid_p2_r);
	120	DECLARE_WRITE8_MEMBER(mermaid_p2_w);
	121	DECLARE_READ8_MEMBER(mermaid_p3_r);
	122	DECLARE_WRITE8_MEMBER(mermaid_p3_w);
102	123	};
103	124
104	125
r14845	r14846
186	207	*
187	208	*************************************/
188	209
189		static WRITE8_HANDLER( trigger_nmi_on_slave_cpu )
	210	WRITE8_MEMBER(hvyunit_state::trigger_nmi_on_slave_cpu)
190	211	{
191		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
192		device_set_input_line(state->m_slave_cpu, INPUT_LINE_NMI, PULSE_LINE);
	212	device_set_input_line(m_slave_cpu, INPUT_LINE_NMI, PULSE_LINE);
193	213	}
194	214
195		static WRITE8_HANDLER( master_bankswitch_w )
	215	WRITE8_MEMBER(hvyunit_state::master_bankswitch_w)
196	216	{
197		unsigned char *ROM = space->machine().region("master")->base();
	217	unsigned char *ROM = machine().region("master")->base();
198	218	int bank = data & 7;
199	219	ROM = &ROM[0x4000 * bank];
200		memory_set_bankptr(space->machine(), "bank1", ROM);
	220	memory_set_bankptr(machine(), "bank1", ROM);
201	221	}
202	222
203		static WRITE8_HANDLER( mermaid_data_w )
	223	WRITE8_MEMBER(hvyunit_state::mermaid_data_w)
204	224	{
205		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
206	225
207		state->m_data_to_mermaid = data;
208		state->m_z80_to_mermaid_full = 1;
209		state->m_mermaid_int0_l = 0;
210		device_set_input_line(state->m_mermaid, INPUT_LINE_IRQ0, ASSERT_LINE);
	226	m_data_to_mermaid = data;
	227	m_z80_to_mermaid_full = 1;
	228	m_mermaid_int0_l = 0;
	229	device_set_input_line(m_mermaid, INPUT_LINE_IRQ0, ASSERT_LINE);
211	230	}
212	231
213		static READ8_HANDLER( mermaid_data_r )
	232	READ8_MEMBER(hvyunit_state::mermaid_data_r)
214	233	{
215		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
216	234
217		state->m_mermaid_to_z80_full = 0;
218		return state->m_data_to_z80;
	235	m_mermaid_to_z80_full = 0;
	236	return m_data_to_z80;
219	237	}
220	238
221		static READ8_HANDLER( mermaid_status_r )
	239	READ8_MEMBER(hvyunit_state::mermaid_status_r)
222	240	{
223		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
224	241
225		return (!state->m_mermaid_to_z80_full << 2) | (state->m_z80_to_mermaid_full << 3);
	242	return (!m_mermaid_to_z80_full << 2) | (m_z80_to_mermaid_full << 3);
226	243	}
227	244
228	245
r14845	r14846
232	249	*
233	250	*************************************/
234	251
235		static WRITE8_HANDLER( trigger_nmi_on_sound_cpu2 )
	252	WRITE8_MEMBER(hvyunit_state::trigger_nmi_on_sound_cpu2)
236	253	{
237		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
238	254
239	255	soundlatch_w(space, 0, data);
240		device_set_input_line(state->m_sound_cpu, INPUT_LINE_NMI, PULSE_LINE);
	256	device_set_input_line(m_sound_cpu, INPUT_LINE_NMI, PULSE_LINE);
241	257	}
242	258
243		static WRITE8_HANDLER( hu_videoram_w )
	259	WRITE8_MEMBER(hvyunit_state::hu_videoram_w)
244	260	{
245		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
246	261
247		state->m_videoram[offset] = data;
248		state->m_bg_tilemap->mark_tile_dirty(offset);
	262	m_videoram[offset] = data;
	263	m_bg_tilemap->mark_tile_dirty(offset);
249	264	}
250	265
251		static WRITE8_HANDLER( hu_colorram_w )
	266	WRITE8_MEMBER(hvyunit_state::hu_colorram_w)
252	267	{
253		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
254	268
255		state->m_colorram[offset] = data;
256		state->m_bg_tilemap->mark_tile_dirty(offset);
	269	m_colorram[offset] = data;
	270	m_bg_tilemap->mark_tile_dirty(offset);
257	271	}
258	272
259		static WRITE8_HANDLER( slave_bankswitch_w )
	273	WRITE8_MEMBER(hvyunit_state::slave_bankswitch_w)
260	274	{
261		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
262	275
263		unsigned char *ROM = space->machine().region("slave")->base();
	276	unsigned char *ROM = machine().region("slave")->base();
264	277	int bank = (data & 0x03);
265		state->m_port0_data = data;
	278	m_port0_data = data;
266	279	ROM = &ROM[0x4000 * bank];
267	280
268		memory_set_bankptr(space->machine(), "bank2", ROM);
	281	memory_set_bankptr(machine(), "bank2", ROM);
269	282	}
270	283
271		static WRITE8_HANDLER( hu_scrollx_w )
	284	WRITE8_MEMBER(hvyunit_state::hu_scrollx_w)
272	285	{
273		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
274		state->m_scrollx = data;
	286	m_scrollx = data;
275	287	}
276	288
277		static WRITE8_HANDLER( hu_scrolly_w )
	289	WRITE8_MEMBER(hvyunit_state::hu_scrolly_w)
278	290	{
279		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
280		state->m_scrolly = data;
	291	m_scrolly = data;
281	292	}
282	293
283		static WRITE8_HANDLER( coin_count_w )
	294	WRITE8_MEMBER(hvyunit_state::coin_count_w)
284	295	{
285		coin_counter_w(space->machine(), 0, data & 1);
286		coin_counter_w(space->machine(), 1, data & 2);
	296	coin_counter_w(machine(), 0, data & 1);
	297	coin_counter_w(machine(), 1, data & 2);
287	298	}
288	299
289	300
r14845	r14846
293	304	*
294	305	*************************************/
295	306
296		static WRITE8_HANDLER( sound_bankswitch_w )
	307	WRITE8_MEMBER(hvyunit_state::sound_bankswitch_w)
297	308	{
298		unsigned char *ROM = space->machine().region("soundcpu")->base();
	309	unsigned char *ROM = machine().region("soundcpu")->base();
299	310	int bank = data & 0x3;
300	311	ROM = &ROM[0x4000 * bank];
301	312
302		memory_set_bankptr(space->machine(), "bank3", ROM);
	313	memory_set_bankptr(machine(), "bank3", ROM);
303	314	}
304	315
305	316
r14845	r14846
309	320	*
310	321	*************************************/
311	322
312		static READ8_HANDLER( mermaid_p0_r )
	323	READ8_MEMBER(hvyunit_state::mermaid_p0_r)
313	324	{
314	325	// ?
315	326	return 0;
316	327	}
317	328
318		static WRITE8_HANDLER( mermaid_p0_w )
	329	WRITE8_MEMBER(hvyunit_state::mermaid_p0_w)
319	330	{
320		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
321	331
322		if (!BIT(state->m_mermaid_p[0], 1) && BIT(data, 1))
	332	if (!BIT(m_mermaid_p[0], 1) && BIT(data, 1))
323	333	{
324		state->m_mermaid_to_z80_full = 1;
325		state->m_data_to_z80 = state->m_mermaid_p[1];
	334	m_mermaid_to_z80_full = 1;
	335	m_data_to_z80 = m_mermaid_p[1];
326	336	}
327	337
328	338	if (BIT(data, 0) == 1)
329		state->m_z80_to_mermaid_full = 0;
	339	m_z80_to_mermaid_full = 0;
330	340
331		state->m_mermaid_p[0] = data;
	341	m_mermaid_p[0] = data;
332	342	}
333	343
334		static READ8_HANDLER( mermaid_p1_r )
	344	READ8_MEMBER(hvyunit_state::mermaid_p1_r)
335	345	{
336		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
337	346
338		if (BIT(state->m_mermaid_p[0], 0) == 0)
339		return state->m_data_to_mermaid;
	347	if (BIT(m_mermaid_p[0], 0) == 0)
	348	return m_data_to_mermaid;
340	349	else
341	350	return 0; // ?
342	351	}
343	352
344		static WRITE8_HANDLER( mermaid_p1_w )
	353	WRITE8_MEMBER(hvyunit_state::mermaid_p1_w)
345	354	{
346		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
347	355
348	356	if (data == 0xff)
349	357	{
350		state->m_mermaid_int0_l = 1;
351		device_set_input_line(state->m_mermaid, INPUT_LINE_IRQ0, CLEAR_LINE);
	358	m_mermaid_int0_l = 1;
	359	device_set_input_line(m_mermaid, INPUT_LINE_IRQ0, CLEAR_LINE);
352	360	}
353	361
354		state->m_mermaid_p[1] = data;
	362	m_mermaid_p[1] = data;
355	363	}
356	364
357		static READ8_HANDLER( mermaid_p2_r )
	365	READ8_MEMBER(hvyunit_state::mermaid_p2_r)
358	366	{
359		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
360	367
361		switch ((state->m_mermaid_p[0] >> 2) & 3)
	368	switch ((m_mermaid_p[0] >> 2) & 3)
362	369	{
363		case 0: return input_port_read(space->machine(), "IN1");
364		case 1: return input_port_read(space->machine(), "IN2");
365		case 2: return input_port_read(space->machine(), "IN0");
	370	case 0: return input_port_read(machine(), "IN1");
	371	case 1: return input_port_read(machine(), "IN2");
	372	case 2: return input_port_read(machine(), "IN0");
366	373	default: return 0xff;
367	374	}
368	375	}
369	376
370		static WRITE8_HANDLER( mermaid_p2_w )
	377	WRITE8_MEMBER(hvyunit_state::mermaid_p2_w)
371	378	{
372		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
373	379
374		state->m_mermaid_p[2] = data;
	380	m_mermaid_p[2] = data;
375	381	}
376	382
377		static READ8_HANDLER( mermaid_p3_r )
	383	READ8_MEMBER(hvyunit_state::mermaid_p3_r)
378	384	{
379		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
380	385
381	386	UINT8 dsw = 0;
382		UINT8 dsw1 = input_port_read(space->machine(), "DSW1");
383		UINT8 dsw2 = input_port_read(space->machine(), "DSW2");
	387	UINT8 dsw1 = input_port_read(machine(), "DSW1");
	388	UINT8 dsw2 = input_port_read(machine(), "DSW2");
384	389
385		switch ((state->m_mermaid_p[0] >> 5) & 3)
	390	switch ((m_mermaid_p[0] >> 5) & 3)
386	391	{
387	392	case 0: dsw = (BIT(dsw2, 4) << 3) | (BIT(dsw2, 0) << 2) | (BIT(dsw1, 4) << 1) | BIT(dsw1, 0); break;
388	393	case 1: dsw = (BIT(dsw2, 5) << 3) | (BIT(dsw2, 1) << 2) | (BIT(dsw1, 5) << 1) | BIT(dsw1, 1); break;
r14845	r14846
390	395	case 3: dsw = (BIT(dsw2, 7) << 3) | (BIT(dsw2, 3) << 2) | (BIT(dsw1, 7) << 1) | BIT(dsw1, 3); break;
391	396	}
392	397
393		return (dsw << 4) | (state->m_mermaid_int0_l << 2) | (state->m_mermaid_to_z80_full << 3);
	398	return (dsw << 4) | (m_mermaid_int0_l << 2) | (m_mermaid_to_z80_full << 3);
394	399	}
395	400
396		static WRITE8_HANDLER( mermaid_p3_w )
	401	WRITE8_MEMBER(hvyunit_state::mermaid_p3_w)
397	402	{
398		hvyunit_state *state = space->machine().driver_data<hvyunit_state>();
399	403
400		state->m_mermaid_p[3] = data;
401		device_set_input_line(state->m_slave_cpu, INPUT_LINE_RESET, data & 2 ? CLEAR_LINE : ASSERT_LINE);
	404	m_mermaid_p[3] = data;
	405	device_set_input_line(m_slave_cpu, INPUT_LINE_RESET, data & 2 ? CLEAR_LINE : ASSERT_LINE);
402	406	}
403	407
404	408
r14845	r14846
418	422
419	423	static ADDRESS_MAP_START( master_io, AS_IO, 8, hvyunit_state )
420	424	ADDRESS_MAP_GLOBAL_MASK(0xff)
421		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(master_bankswitch_w)
422		AM_RANGE(0x01, 0x01) AM_WRITE_LEGACY(master_bankswitch_w) // correct?
423		AM_RANGE(0x02, 0x02) AM_WRITE_LEGACY(trigger_nmi_on_slave_cpu)
	425	AM_RANGE(0x00, 0x00) AM_WRITE(master_bankswitch_w)
	426	AM_RANGE(0x01, 0x01) AM_WRITE(master_bankswitch_w) // correct?
	427	AM_RANGE(0x02, 0x02) AM_WRITE(trigger_nmi_on_slave_cpu)
424	428	ADDRESS_MAP_END
425	429
426	430
427	431	static ADDRESS_MAP_START( slave_memory, AS_PROGRAM, 8, hvyunit_state )
428	432	AM_RANGE(0x0000, 0x7fff) AM_ROM
429	433	AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank2")
430		AM_RANGE(0xc000, 0xc3ff) AM_RAM_WRITE_LEGACY(hu_videoram_w) AM_BASE(m_videoram)
431		AM_RANGE(0xc400, 0xc7ff) AM_RAM_WRITE_LEGACY(hu_colorram_w) AM_BASE(m_colorram)
	434	AM_RANGE(0xc000, 0xc3ff) AM_RAM_WRITE(hu_videoram_w) AM_BASE(m_videoram)
	435	AM_RANGE(0xc400, 0xc7ff) AM_RAM_WRITE(hu_colorram_w) AM_BASE(m_colorram)
432	436	AM_RANGE(0xd000, 0xd1ff) AM_RAM_WRITE_LEGACY(paletteram_xxxxRRRRGGGGBBBB_split2_w) AM_BASE_GENERIC(paletteram2)
433	437	AM_RANGE(0xd800, 0xd9ff) AM_RAM_WRITE_LEGACY(paletteram_xxxxRRRRGGGGBBBB_split1_w) AM_BASE_GENERIC(paletteram)
434	438	AM_RANGE(0xd000, 0xdfff) AM_RAM
r14845	r14846
437	441
438	442	static ADDRESS_MAP_START( slave_io, AS_IO, 8, hvyunit_state )
439	443	ADDRESS_MAP_GLOBAL_MASK(0xff)
440		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(slave_bankswitch_w)
441		AM_RANGE(0x02, 0x02) AM_WRITE_LEGACY(trigger_nmi_on_sound_cpu2)
442		AM_RANGE(0x04, 0x04) AM_READWRITE_LEGACY(mermaid_data_r, mermaid_data_w)
443		AM_RANGE(0x06, 0x06) AM_WRITE_LEGACY(hu_scrolly_w)
444		AM_RANGE(0x08, 0x08) AM_WRITE_LEGACY(hu_scrollx_w)
445		AM_RANGE(0x0c, 0x0c) AM_READ_LEGACY(mermaid_status_r)
446		AM_RANGE(0x0e, 0x0e) AM_WRITE_LEGACY(coin_count_w)
	444	AM_RANGE(0x00, 0x00) AM_WRITE(slave_bankswitch_w)
	445	AM_RANGE(0x02, 0x02) AM_WRITE(trigger_nmi_on_sound_cpu2)
	446	AM_RANGE(0x04, 0x04) AM_READWRITE(mermaid_data_r, mermaid_data_w)
	447	AM_RANGE(0x06, 0x06) AM_WRITE(hu_scrolly_w)
	448	AM_RANGE(0x08, 0x08) AM_WRITE(hu_scrollx_w)
	449	AM_RANGE(0x0c, 0x0c) AM_READ(mermaid_status_r)
	450	AM_RANGE(0x0e, 0x0e) AM_WRITE(coin_count_w)
447	451
448	452	//  AM_RANGE(0x22, 0x22) AM_READ_LEGACY(hu_scrolly_hi_reset) //22/a2 taken from ram $f065
449	453	//  AM_RANGE(0xa2, 0xa2) AM_READ_LEGACY(hu_scrolly_hi_set)
r14845	r14846
458	462
459	463	static ADDRESS_MAP_START( sound_io, AS_IO, 8, hvyunit_state )
460	464	ADDRESS_MAP_GLOBAL_MASK(0xff)
461		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(sound_bankswitch_w)
	465	AM_RANGE(0x00, 0x00) AM_WRITE(sound_bankswitch_w)
462	466	AM_RANGE(0x02, 0x03) AM_DEVREADWRITE_LEGACY("ymsnd", ym2203_r, ym2203_w)
463	467	AM_RANGE(0x04, 0x04) AM_READ_LEGACY(soundlatch_r)
464	468	ADDRESS_MAP_END
465	469
466	470
467	471	static ADDRESS_MAP_START( mcu_io, AS_IO, 8, hvyunit_state )
468		AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_READWRITE_LEGACY(mermaid_p0_r, mermaid_p0_w)
469		AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE_LEGACY(mermaid_p1_r, mermaid_p1_w)
470		AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READWRITE_LEGACY(mermaid_p2_r, mermaid_p2_w)
471		AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE_LEGACY(mermaid_p3_r, mermaid_p3_w)
	472	AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_READWRITE(mermaid_p0_r, mermaid_p0_w)
	473	AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(mermaid_p1_r, mermaid_p1_w)
	474	AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READWRITE(mermaid_p2_r, mermaid_p2_w)
	475	AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(mermaid_p3_r, mermaid_p3_w)
472	476	ADDRESS_MAP_END
473	477
474	478

src/mame/drivers/royalmah.c

r14845	r14846
123	123	UINT8 m_mjifb_rom_enable;
124	124
125	125	required_device<cpu_device> m_maincpu;
	126	DECLARE_WRITE8_MEMBER(royalmah_palbank_w);
	127	DECLARE_WRITE8_MEMBER(mjderngr_coin_w);
	128	DECLARE_WRITE8_MEMBER(mjderngr_palbank_w);
	129	DECLARE_WRITE8_MEMBER(royalmah_rom_w);
	130	DECLARE_WRITE8_MEMBER(input_port_select_w);
	131	DECLARE_READ8_MEMBER(majs101b_dsw_r);
	132	DECLARE_READ8_MEMBER(suzume_dsw_r);
	133	DECLARE_WRITE8_MEMBER(suzume_bank_w);
	134	DECLARE_WRITE8_MEMBER(mjapinky_bank_w);
	135	DECLARE_WRITE8_MEMBER(mjapinky_palbank_w);
	136	DECLARE_READ8_MEMBER(mjapinky_dsw_r);
	137	DECLARE_WRITE8_MEMBER(tontonb_bank_w);
	138	DECLARE_WRITE8_MEMBER(dynax_bank_w);
	139	DECLARE_READ8_MEMBER(daisyari_dsw_r);
	140	DECLARE_WRITE8_MEMBER(daisyari_bank_w);
	141	DECLARE_READ8_MEMBER(mjclub_dsw_r);
	142	DECLARE_WRITE8_MEMBER(mjclub_bank_w);
	143	DECLARE_WRITE8_MEMBER(jansou_dsw_sel_w);
	144	DECLARE_READ8_MEMBER(jansou_dsw_r);
	145	DECLARE_WRITE8_MEMBER(jansou_colortable_w);
	146	DECLARE_WRITE8_MEMBER(jansou_6400_w);
	147	DECLARE_WRITE8_MEMBER(jansou_6401_w);
	148	DECLARE_WRITE8_MEMBER(jansou_6402_w);
	149	DECLARE_READ8_MEMBER(jansou_6403_r);
	150	DECLARE_READ8_MEMBER(jansou_6404_r);
	151	DECLARE_READ8_MEMBER(jansou_6405_r);
	152	DECLARE_WRITE8_MEMBER(jansou_sound_w);
	153	DECLARE_WRITE8_MEMBER(janptr96_dswsel_w);
	154	DECLARE_READ8_MEMBER(janptr96_dswsel_r);
	155	DECLARE_READ8_MEMBER(janptr96_dsw_r);
	156	DECLARE_WRITE8_MEMBER(janptr96_rombank_w);
	157	DECLARE_WRITE8_MEMBER(janptr96_rambank_w);
	158	DECLARE_READ8_MEMBER(janptr96_unknown_r);
	159	DECLARE_WRITE8_MEMBER(janptr96_coin_counter_w);
	160	DECLARE_WRITE8_MEMBER(mjifb_coin_counter_w);
	161	DECLARE_READ8_MEMBER(mjifb_rom_io_r);
	162	DECLARE_WRITE8_MEMBER(mjifb_rom_io_w);
	163	DECLARE_WRITE8_MEMBER(mjifb_videoram_w);
	164	DECLARE_READ8_MEMBER(mjifb_p3_r);
	165	DECLARE_READ8_MEMBER(mjifb_p5_r);
	166	DECLARE_READ8_MEMBER(mjifb_p6_r);
	167	DECLARE_READ8_MEMBER(mjifb_p7_r);
	168	DECLARE_READ8_MEMBER(mjifb_p8_r);
	169	DECLARE_WRITE8_MEMBER(mjifb_p3_w);
	170	DECLARE_WRITE8_MEMBER(mjifb_p4_w);
	171	DECLARE_WRITE8_MEMBER(mjifb_p8_w);
	172	DECLARE_READ8_MEMBER(mjdejavu_rom_io_r);
	173	DECLARE_WRITE8_MEMBER(mjdejavu_rom_io_w);
	174	DECLARE_READ8_MEMBER(mjtensin_p3_r);
	175	DECLARE_WRITE8_MEMBER(mjtensin_p4_w);
	176	DECLARE_WRITE8_MEMBER(mjtensin_6ff3_w);
	177	DECLARE_WRITE8_MEMBER(cafetime_p4_w);
	178	DECLARE_WRITE8_MEMBER(cafetime_p3_w);
	179	DECLARE_WRITE8_MEMBER(cafetime_dsw_w);
	180	DECLARE_READ8_MEMBER(cafetime_dsw_r);
	181	DECLARE_READ8_MEMBER(cafetime_7fe4_r);
	182	DECLARE_WRITE8_MEMBER(cafetime_7fe3_w);
	183	DECLARE_WRITE8_MEMBER(mjvegasa_p4_w);
	184	DECLARE_WRITE8_MEMBER(mjvegasa_p3_w);
	185	DECLARE_WRITE8_MEMBER(mjvegasa_rombank_w);
	186	DECLARE_READ8_MEMBER(mjvegasa_rom_io_r);
	187	DECLARE_WRITE8_MEMBER(mjvegasa_rom_io_w);
	188	DECLARE_WRITE8_MEMBER(mjvegasa_coin_counter_w);
	189	DECLARE_WRITE8_MEMBER(mjvegasa_12400_w);
	190	DECLARE_READ8_MEMBER(mjvegasa_12500_r);
126	191	};
127	192
128	193
r14845	r14846
183	248	}
184	249
185	250
186		static WRITE8_HANDLER( royalmah_palbank_w )
	251	WRITE8_MEMBER(royalmah_state::royalmah_palbank_w)
187	252	{
188		royalmah_state *state = space->machine().driver_data<royalmah_state>();
189	253	/* bit 1 = coin counter */
190		coin_counter_w(space->machine(), 0,data & 2);
	254	coin_counter_w(machine(), 0,data & 2);
191	255
192	256	/* bit 2 always set? */
193	257
194	258	/* bit 3 = palette bank */
195		state->m_palette_base = (data >> 3) & 0x01;
	259	m_palette_base = (data >> 3) & 0x01;
196	260	}
197	261
198	262
199		static WRITE8_HANDLER( mjderngr_coin_w )
	263	WRITE8_MEMBER(royalmah_state::mjderngr_coin_w)
200	264	{
201	265	/* bit 1 = coin counter */
202		coin_counter_w(space->machine(), 0,data & 2);
	266	coin_counter_w(machine(), 0,data & 2);
203	267
204	268	/* bit 2 always set? */
205	269	}
206	270
207	271
208		static WRITE8_HANDLER( mjderngr_palbank_w )
	272	WRITE8_MEMBER(royalmah_state::mjderngr_palbank_w)
209	273	{
210		royalmah_state *state = space->machine().driver_data<royalmah_state>();
211		state->m_palette_base = data;
	274	m_palette_base = data;
212	275	}
213	276
214	277
r14845	r14846
248	311
249	312
250	313
251		static WRITE8_HANDLER( royalmah_rom_w )
	314	WRITE8_MEMBER(royalmah_state::royalmah_rom_w)
252	315	{
253	316	/* using this handler will avoid all the entries in the error log that are the result of
254	317	the RLD and RRD instructions this games uses to print text on the screen */
255	318	}
256	319
257	320
258		static WRITE8_HANDLER( input_port_select_w )
	321	WRITE8_MEMBER(royalmah_state::input_port_select_w)
259	322	{
260		royalmah_state *state = space->machine().driver_data<royalmah_state>();
261		state->m_input_port_select = data;
	323	m_input_port_select = data;
262	324	}
263	325
264	326	static READ8_DEVICE_HANDLER( royalmah_player_1_port_r )
r14845	r14846
291	353
292	354
293	355
294		static READ8_HANDLER ( majs101b_dsw_r )
	356	READ8_MEMBER(royalmah_state::majs101b_dsw_r)
295	357	{
296		royalmah_state *state = space->machine().driver_data<royalmah_state>();
297		switch (state->m_dsw_select)
	358	switch (m_dsw_select)
298	359	{
299		case 0x00: return input_port_read(space->machine(), "DSW3");   /* DSW3 */
300		case 0x20: return input_port_read(space->machine(), "DSW4");   /* DSW4 */
301		case 0x40: return input_port_read(space->machine(), "DSW2");   /* DSW2 */
	360	case 0x00: return input_port_read(machine(), "DSW3");   /* DSW3 */
	361	case 0x20: return input_port_read(machine(), "DSW4");   /* DSW4 */
	362	case 0x40: return input_port_read(machine(), "DSW2");   /* DSW2 */
302	363	}
303	364	return 0;
304	365	}
305	366
306	367
307	368
308		static READ8_HANDLER ( suzume_dsw_r )
	369	READ8_MEMBER(royalmah_state::suzume_dsw_r)
309	370	{
310		royalmah_state *state = space->machine().driver_data<royalmah_state>();
311		if (state->m_suzume_bank & 0x40)
	371	if (m_suzume_bank & 0x40)
312	372	{
313		return state->m_suzume_bank;
	373	return m_suzume_bank;
314	374	}
315	375	else
316	376	{
317		switch (state->m_suzume_bank)
	377	switch (m_suzume_bank)
318	378	{
319		case 0x08: return input_port_read(space->machine(), "DSW4");   /* DSW4 */
320		case 0x10: return input_port_read(space->machine(), "DSW3");   /* DSW3 */
321		case 0x18: return input_port_read(space->machine(), "DSW2");   /* DSW2 */
	379	case 0x08: return input_port_read(machine(), "DSW4");   /* DSW4 */
	380	case 0x10: return input_port_read(machine(), "DSW3");   /* DSW3 */
	381	case 0x18: return input_port_read(machine(), "DSW2");   /* DSW2 */
322	382	}
323	383	return 0;
324	384	}
325	385	}
326	386
327		static WRITE8_HANDLER ( suzume_bank_w )
	387	WRITE8_MEMBER(royalmah_state::suzume_bank_w)
328	388	{
329		royalmah_state *state = space->machine().driver_data<royalmah_state>();
330		UINT8 *rom = space->machine().region("maincpu")->base();
	389	UINT8 *rom = machine().region("maincpu")->base();
331	390	int address;
332	391
333		state->m_suzume_bank = data;
	392	m_suzume_bank = data;
334	393
335		logerror("%04x: bank %02x\n",cpu_get_pc(&space->device()),data);
	394	logerror("%04x: bank %02x\n",cpu_get_pc(&space.device()),data);
336	395
337	396	/* bits 6, 4 and 3 used for something input related? */
338	397
339	398	address = 0x10000 + (data & 0x07) * 0x8000;
340		memory_set_bankptr(space->machine(), "bank1",&rom[address]);
	399	memory_set_bankptr(machine(), "bank1",&rom[address]);
341	400	}
342	401
343	402
344		static WRITE8_HANDLER ( mjapinky_bank_w )
	403	WRITE8_MEMBER(royalmah_state::mjapinky_bank_w)
345	404	{
346		royalmah_state *state = space->machine().driver_data<royalmah_state>();
347		UINT8 *ROM = space->machine().region("maincpu")->base();
348		state->m_rombank = data;
349		memory_set_bankptr(space->machine(), "bank1",ROM + 0x10000 + 0x8000 * data);
	405	UINT8 *ROM = machine().region("maincpu")->base();
	406	m_rombank = data;
	407	memory_set_bankptr(machine(), "bank1",ROM + 0x10000 + 0x8000 * data);
350	408	}
351	409
352		static WRITE8_HANDLER( mjapinky_palbank_w )
	410	WRITE8_MEMBER(royalmah_state::mjapinky_palbank_w)
353	411	{
354		royalmah_state *state = space->machine().driver_data<royalmah_state>();
355		flip_screen_set(space->machine(), ~data & 4);
356		state->m_palette_base = (data >> 3) & 0x01;
357		coin_counter_w(space->machine(), 0,data & 2);   // in
358		coin_counter_w(space->machine(), 1,data & 1);   // out
	412	flip_screen_set(machine(), ~data & 4);
	413	m_palette_base = (data >> 3) & 0x01;
	414	coin_counter_w(machine(), 0,data & 2);   // in
	415	coin_counter_w(machine(), 1,data & 1);   // out
359	416	}
360	417
361		static READ8_HANDLER( mjapinky_dsw_r )
	418	READ8_MEMBER(royalmah_state::mjapinky_dsw_r)
362	419	{
363		royalmah_state *state = space->machine().driver_data<royalmah_state>();
364		if (state->m_rombank == 0x0e)   return input_port_read(space->machine(), "DSW3");
365		else               return *(space->machine().region("maincpu")->base() + 0x10000 + 0x8000 * state->m_rombank);
	420	if (m_rombank == 0x0e)   return input_port_read(machine(), "DSW3");
	421	else               return *(machine().region("maincpu")->base() + 0x10000 + 0x8000 * m_rombank);
366	422	}
367	423
368		static WRITE8_HANDLER ( tontonb_bank_w )
	424	WRITE8_MEMBER(royalmah_state::tontonb_bank_w)
369	425	{
370		UINT8 *rom = space->machine().region("maincpu")->base();
	426	UINT8 *rom = machine().region("maincpu")->base();
371	427	int address;
372	428
373		logerror("%04x: bank %02x\n",cpu_get_pc(&space->device()),data);
	429	logerror("%04x: bank %02x\n",cpu_get_pc(&space.device()),data);
374	430
375	431	if (data == 0) return;   // tontonb fix?
376	432
r14845	r14846
378	434
379	435	address = 0x10000 + data * 0x8000;
380	436
381		memory_set_bankptr(space->machine(), "bank1",&rom[address]);
	437	memory_set_bankptr(machine(), "bank1",&rom[address]);
382	438	}
383	439
384	440
385	441	/* bits 5 and 6 seem to affect which Dip Switch to read in 'majs101b' */
386		static WRITE8_HANDLER ( dynax_bank_w )
	442	WRITE8_MEMBER(royalmah_state::dynax_bank_w)
387	443	{
388		royalmah_state *state = space->machine().driver_data<royalmah_state>();
389		UINT8 *rom = space->machine().region("maincpu")->base();
	444	UINT8 *rom = machine().region("maincpu")->base();
390	445	int address;
391	446
392		//logerror("%04x: bank %02x\n",cpu_get_pc(&space->device()),data);
	447	//logerror("%04x: bank %02x\n",cpu_get_pc(&space.device()),data);
393	448
394		state->m_dsw_select = data & 0x60;
	449	m_dsw_select = data & 0x60;
395	450
396	451	data &= 0x1f;
397	452
398	453	address = 0x10000 + data * 0x8000;
399	454
400		memory_set_bankptr(space->machine(), "bank1",&rom[address]);
	455	memory_set_bankptr(machine(), "bank1",&rom[address]);
401	456	}
402	457
403		static READ8_HANDLER ( daisyari_dsw_r )
	458	READ8_MEMBER(royalmah_state::daisyari_dsw_r)
404	459	{
405		royalmah_state *state = space->machine().driver_data<royalmah_state>();
406		switch (state->m_dsw_select)
	460	switch (m_dsw_select)
407	461	{
408		case 0x00: return input_port_read(space->machine(), "DSW4");
409		case 0x04: return input_port_read(space->machine(), "DSW1");
410		case 0x08: return input_port_read(space->machine(), "DSW2");
411		case 0x0c: return input_port_read(space->machine(), "DSW3");
	462	case 0x00: return input_port_read(machine(), "DSW4");
	463	case 0x04: return input_port_read(machine(), "DSW1");
	464	case 0x08: return input_port_read(machine(), "DSW2");
	465	case 0x0c: return input_port_read(machine(), "DSW3");
412	466	}
413	467
414	468	return 0;
415	469	}
416	470
417		static WRITE8_HANDLER ( daisyari_bank_w )
	471	WRITE8_MEMBER(royalmah_state::daisyari_bank_w)
418	472	{
419		royalmah_state *state = space->machine().driver_data<royalmah_state>();
420		UINT8 *rom = space->machine().region("maincpu")->base();
	473	UINT8 *rom = machine().region("maincpu")->base();
421	474	int address;
422	475
423		state->m_dsw_select = (data & 0xc);
	476	m_dsw_select = (data & 0xc);
424	477
425	478	address = 0x10000 + ((data & 0x30)>>4) * 0x10000 + (data & 0x1) * 0x8000;
426	479	//  printf("%08x %02x\n",address,data);
427	480
428		memory_set_bankptr(space->machine(), "bank1",&rom[address]);
	481	memory_set_bankptr(machine(), "bank1",&rom[address]);
429	482
430	483	/* bit 1 used too but unknown purpose. */
431	484	}
432	485
433		static READ8_HANDLER ( mjclub_dsw_r )
	486	READ8_MEMBER(royalmah_state::mjclub_dsw_r)
434	487	{
435		royalmah_state *state = space->machine().driver_data<royalmah_state>();
436		switch (state->m_dsw_select)
	488	switch (m_dsw_select)
437	489	{
438		//      case 0x00: return input_port_read(space->machine(), "DSW4");
439		case 0x40: return input_port_read(space->machine(), "DSW2");
440		case 0x80: return input_port_read(space->machine(), "DSW3");
441		case 0xc0: return input_port_read(space->machine(), "DSW4");
	490	//      case 0x00: return input_port_read(machine(), "DSW4");
	491	case 0x40: return input_port_read(machine(), "DSW2");
	492	case 0x80: return input_port_read(machine(), "DSW3");
	493	case 0xc0: return input_port_read(machine(), "DSW4");
442	494	}
443	495
444	496	return 0;
445	497	}
446	498
447		static WRITE8_HANDLER ( mjclub_bank_w )
	499	WRITE8_MEMBER(royalmah_state::mjclub_bank_w)
448	500	{
449		royalmah_state *state = space->machine().driver_data<royalmah_state>();
450		UINT8 *rom = space->machine().region("maincpu")->base();
	501	UINT8 *rom = machine().region("maincpu")->base();
451	502	int address;
452	503
453		state->m_dsw_select = data & 0xc0;
	504	m_dsw_select = data & 0xc0;
454	505
455	506	data &= 0x0f;
456	507
457	508	address = 0x10000 + data * 0x8000;
458	509	//  printf("%08x\n",address);
459	510
460		memory_set_bankptr(space->machine(), "bank1",&rom[address]);
	511	memory_set_bankptr(machine(), "bank1",&rom[address]);
461	512
462	513	/* bit 5 used too but unknown purpose. */
463	514	}
464	515
465	516
466	517	static ADDRESS_MAP_START( royalmah_map, AS_PROGRAM, 8, royalmah_state )
467		AM_RANGE( 0x0000, 0x6fff ) AM_ROM AM_WRITE_LEGACY(royalmah_rom_w )
	518	AM_RANGE( 0x0000, 0x6fff ) AM_ROM AM_WRITE(royalmah_rom_w )
468	519	AM_RANGE( 0x7000, 0x7fff ) AM_RAM AM_SHARE("nvram")
469	520	AM_RANGE( 0x8000, 0xffff ) AM_ROMBANK( "bank1" )   // banked ROMs not present in royalmah
470	521	AM_RANGE( 0x8000, 0xffff ) AM_WRITEONLY AM_BASE(m_videoram)
r14845	r14846
472	523
473	524
474	525	static ADDRESS_MAP_START( mjapinky_map, AS_PROGRAM, 8, royalmah_state )
475		AM_RANGE( 0x0000, 0x6fff ) AM_ROM AM_WRITE_LEGACY(royalmah_rom_w )
	526	AM_RANGE( 0x0000, 0x6fff ) AM_ROM AM_WRITE(royalmah_rom_w )
476	527	AM_RANGE( 0x7000, 0x77ff ) AM_RAM AM_SHARE("nvram")
477	528	AM_RANGE( 0x7800, 0x7fff ) AM_RAM
478		AM_RANGE( 0x8000, 0x8000 ) AM_READ_LEGACY(mjapinky_dsw_r )
	529	AM_RANGE( 0x8000, 0x8000 ) AM_READ(mjapinky_dsw_r )
479	530	AM_RANGE( 0x8000, 0xffff ) AM_ROMBANK( "bank1" )
480	531	AM_RANGE( 0x8000, 0xffff ) AM_WRITEONLY AM_BASE(m_videoram)
481	532	ADDRESS_MAP_END
r14845	r14846
487	538	ADDRESS_MAP_GLOBAL_MASK(0xff)
488	539	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
489	540	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
490		AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(royalmah_palbank_w )
491		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
	541	AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE(royalmah_palbank_w )
	542	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
492	543	ADDRESS_MAP_END
493	544
494	545	static ADDRESS_MAP_START( ippatsu_iomap, AS_IO, 8, royalmah_state )
495	546	ADDRESS_MAP_GLOBAL_MASK(0xff)
496	547	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
497	548	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
498		AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(royalmah_palbank_w )
499		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
	549	AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE(royalmah_palbank_w )
	550	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
500	551	AM_RANGE( 0x12, 0x12 ) AM_READ_PORT("DSW2")
501	552	AM_RANGE( 0x13, 0x13 ) AM_READ_PORT("DSW3")
502	553	ADDRESS_MAP_END
r14845	r14846
505	556	ADDRESS_MAP_GLOBAL_MASK(0xff)
506	557	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
507	558	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
508		AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(royalmah_palbank_w )
509		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
510		AM_RANGE( 0x80, 0x80 ) AM_READ_LEGACY(suzume_dsw_r )
511		AM_RANGE( 0x81, 0x81 ) AM_WRITE_LEGACY(suzume_bank_w )
	559	AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE(royalmah_palbank_w )
	560	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
	561	AM_RANGE( 0x80, 0x80 ) AM_READ(suzume_dsw_r )
	562	AM_RANGE( 0x81, 0x81 ) AM_WRITE(suzume_bank_w )
512	563	ADDRESS_MAP_END
513	564
514	565	static ADDRESS_MAP_START( dondenmj_iomap, AS_IO, 8, royalmah_state )
515	566	ADDRESS_MAP_GLOBAL_MASK(0xff)
516	567	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
517	568	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
518		AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(royalmah_palbank_w )
519		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
	569	AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE(royalmah_palbank_w )
	570	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
520	571	AM_RANGE( 0x85, 0x85 ) AM_READ_PORT("DSW2")   // DSW2
521	572	AM_RANGE( 0x86, 0x86 ) AM_READ_PORT("DSW3")   // DSW3
522		AM_RANGE( 0x87, 0x87 ) AM_WRITE_LEGACY(dynax_bank_w )
	573	AM_RANGE( 0x87, 0x87 ) AM_WRITE(dynax_bank_w )
523	574	ADDRESS_MAP_END
524	575
525	576	static ADDRESS_MAP_START( makaijan_iomap, AS_IO, 8, royalmah_state )
526	577	ADDRESS_MAP_GLOBAL_MASK(0xff)
527	578	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
528	579	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
529		AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(royalmah_palbank_w )
530		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
	580	AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE(royalmah_palbank_w )
	581	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
531	582	AM_RANGE( 0x84, 0x84 ) AM_READ_PORT("DSW2")   // DSW2
532	583	AM_RANGE( 0x85, 0x85 ) AM_READ_PORT("DSW3")   // DSW3
533		AM_RANGE( 0x86, 0x86 ) AM_WRITE_LEGACY(dynax_bank_w )
	584	AM_RANGE( 0x86, 0x86 ) AM_WRITE(dynax_bank_w )
534	585	ADDRESS_MAP_END
535	586
536	587	static ADDRESS_MAP_START( daisyari_iomap, AS_IO, 8, royalmah_state )
537	588	ADDRESS_MAP_GLOBAL_MASK(0xff)
538	589	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
539	590	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
540		AM_RANGE( 0x10, 0x10 ) AM_WRITE_LEGACY(royalmah_palbank_w )
541		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
542		AM_RANGE( 0xc0, 0xc0 ) AM_READWRITE_LEGACY(daisyari_dsw_r, daisyari_bank_w )
	591	AM_RANGE( 0x10, 0x10 ) AM_WRITE(royalmah_palbank_w )
	592	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
	593	AM_RANGE( 0xc0, 0xc0 ) AM_READWRITE(daisyari_dsw_r, daisyari_bank_w )
543	594	ADDRESS_MAP_END
544	595
545	596	static ADDRESS_MAP_START( mjclub_iomap, AS_IO, 8, royalmah_state )
546	597	ADDRESS_MAP_GLOBAL_MASK(0xff)
547		AM_RANGE( 0x00, 0x00 ) AM_READWRITE_LEGACY(mjclub_dsw_r, mjclub_bank_w )
	598	AM_RANGE( 0x00, 0x00 ) AM_READWRITE(mjclub_dsw_r, mjclub_bank_w )
548	599	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
549	600	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
550		AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(royalmah_palbank_w )
551		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
	601	AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE(royalmah_palbank_w )
	602	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
552	603	ADDRESS_MAP_END
553	604
554	605	static ADDRESS_MAP_START( mjdiplob_iomap, AS_IO, 8, royalmah_state )
555	606	ADDRESS_MAP_GLOBAL_MASK(0xff)
556	607	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
557	608	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
558		AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(royalmah_palbank_w )
559		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
560		AM_RANGE( 0x61, 0x61 ) AM_WRITE_LEGACY(tontonb_bank_w)
	609	AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE(royalmah_palbank_w )
	610	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
	611	AM_RANGE( 0x61, 0x61 ) AM_WRITE(tontonb_bank_w)
561	612	AM_RANGE( 0x62, 0x62 ) AM_READ_PORT("DSW2")   // DSW2
562	613	AM_RANGE( 0x63, 0x63 ) AM_READ_PORT("DSW3")   // DSW3
563	614	ADDRESS_MAP_END
r14845	r14846
566	617	ADDRESS_MAP_GLOBAL_MASK(0xff)
567	618	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
568	619	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
569		AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(royalmah_palbank_w )
570		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
571		AM_RANGE( 0x44, 0x44 ) AM_WRITE_LEGACY(tontonb_bank_w )
	620	AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE(royalmah_palbank_w )
	621	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
	622	AM_RANGE( 0x44, 0x44 ) AM_WRITE(tontonb_bank_w )
572	623	AM_RANGE( 0x46, 0x46 ) AM_READ_PORT("DSW2")   // DSW2
573	624	AM_RANGE( 0x47, 0x47 ) AM_READ_PORT("DSW3")   // DSW3
574	625	ADDRESS_MAP_END
r14845	r14846
577	628	ADDRESS_MAP_GLOBAL_MASK(0xff)
578	629	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
579	630	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
580		AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(royalmah_palbank_w )
581		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
582		AM_RANGE( 0x00, 0x00 ) AM_READWRITE_LEGACY(majs101b_dsw_r, dynax_bank_w )
	631	AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE(royalmah_palbank_w )
	632	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
	633	AM_RANGE( 0x00, 0x00 ) AM_READWRITE(majs101b_dsw_r, dynax_bank_w )
583	634	ADDRESS_MAP_END
584	635
585	636	static ADDRESS_MAP_START( mjderngr_iomap, AS_IO, 8, royalmah_state )
r14845	r14846
587	638	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
588	639	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
589	640	//  AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1")
590		AM_RANGE( 0x10, 0x10 ) AM_WRITE_LEGACY(mjderngr_coin_w )   // palette bank is set separately
591		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
592		AM_RANGE( 0x20, 0x20 ) AM_WRITE_LEGACY(dynax_bank_w )
	641	AM_RANGE( 0x10, 0x10 ) AM_WRITE(mjderngr_coin_w )   // palette bank is set separately
	642	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
	643	AM_RANGE( 0x20, 0x20 ) AM_WRITE(dynax_bank_w )
593	644	AM_RANGE( 0x40, 0x40 ) AM_READ_PORT("DSW3")
594	645	AM_RANGE( 0x4c, 0x4c ) AM_READ_PORT("DSW2")
595		AM_RANGE( 0x60, 0x60 ) AM_WRITE_LEGACY(mjderngr_palbank_w )
	646	AM_RANGE( 0x60, 0x60 ) AM_WRITE(mjderngr_palbank_w )
596	647	ADDRESS_MAP_END
597	648
598	649	static ADDRESS_MAP_START( mjapinky_iomap, AS_IO, 8, royalmah_state )
599	650	ADDRESS_MAP_GLOBAL_MASK(0xff)
600		AM_RANGE( 0x00, 0x00 ) AM_WRITE_LEGACY(mjapinky_bank_w )
	651	AM_RANGE( 0x00, 0x00 ) AM_WRITE(mjapinky_bank_w )
601	652	AM_RANGE( 0x01, 0x01 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
602	653	AM_RANGE( 0x02, 0x03 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
603	654	AM_RANGE( 0x04, 0x04 ) AM_READ_PORT("DSW2")
604		AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(mjapinky_palbank_w )
605		AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
	655	AM_RANGE( 0x10, 0x10 ) AM_READ_PORT("DSW1") AM_WRITE(mjapinky_palbank_w )
	656	AM_RANGE( 0x11, 0x11 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
606	657	ADDRESS_MAP_END
607	658
608	659
609	660	static ADDRESS_MAP_START( janoh_map, AS_PROGRAM, 8, royalmah_state )
610		AM_RANGE( 0x0000, 0x6fff ) AM_ROM AM_WRITE_LEGACY(royalmah_rom_w )
	661	AM_RANGE( 0x0000, 0x6fff ) AM_ROM AM_WRITE(royalmah_rom_w )
611	662	AM_RANGE( 0x7000, 0x7fff ) AM_RAM AM_SHARE("nvram")
612	663	AM_RANGE( 0x8000, 0xffff ) AM_WRITEONLY AM_BASE(m_videoram)
613	664	ADDRESS_MAP_END
r14845	r14846
634	685
635	686
636	687
637		static WRITE8_HANDLER( jansou_dsw_sel_w )
	688	WRITE8_MEMBER(royalmah_state::jansou_dsw_sel_w)
638	689	{
639		royalmah_state *state = space->machine().driver_data<royalmah_state>();
640		state->m_dsw_select = data;
	690	m_dsw_select = data;
641	691	}
642	692
643		static READ8_HANDLER( jansou_dsw_r )
	693	READ8_MEMBER(royalmah_state::jansou_dsw_r)
644	694	{
645		royalmah_state *state = space->machine().driver_data<royalmah_state>();
646		switch (state->m_dsw_select & 7)
	695	switch (m_dsw_select & 7)
647	696	{
648		case 1: return input_port_read(space->machine(), "DSW1");
649		case 2: return input_port_read(space->machine(), "DSW2");
650		case 4: return input_port_read(space->machine(), "DSW3");
	697	case 1: return input_port_read(machine(), "DSW1");
	698	case 2: return input_port_read(machine(), "DSW2");
	699	case 4: return input_port_read(machine(), "DSW3");
651	700	}
652	701
653	702	return 0xff;
654	703	}
655	704
656		static WRITE8_HANDLER( jansou_colortable_w )
	705	WRITE8_MEMBER(royalmah_state::jansou_colortable_w)
657	706	{
658		royalmah_state *state = space->machine().driver_data<royalmah_state>();
659		state->m_jansou_colortable[offset] = data;
	707	m_jansou_colortable[offset] = data;
660	708	}
661	709
662		static WRITE8_HANDLER( jansou_6400_w )
	710	WRITE8_MEMBER(royalmah_state::jansou_6400_w)
663	711	{
664		royalmah_state *state = space->machine().driver_data<royalmah_state>();
665		state->m_gfx_adr_l = data;
666		state->m_gfx_adr = state->m_gfx_adr_h*0x10000 + state->m_gfx_adr_m*0x100 + state->m_gfx_adr_l;
	712	m_gfx_adr_l = data;
	713	m_gfx_adr = m_gfx_adr_h*0x10000 + m_gfx_adr_m*0x100 + m_gfx_adr_l;
667	714	}
668	715
669		static WRITE8_HANDLER( jansou_6401_w )
	716	WRITE8_MEMBER(royalmah_state::jansou_6401_w)
670	717	{
671		royalmah_state *state = space->machine().driver_data<royalmah_state>();
672		state->m_gfx_adr_m = data;
673		state->m_gfx_adr = state->m_gfx_adr_h*0x10000 + state->m_gfx_adr_m*0x100 + state->m_gfx_adr_l;
	718	m_gfx_adr_m = data;
	719	m_gfx_adr = m_gfx_adr_h*0x10000 + m_gfx_adr_m*0x100 + m_gfx_adr_l;
674	720	}
675	721
676		static WRITE8_HANDLER( jansou_6402_w )
	722	WRITE8_MEMBER(royalmah_state::jansou_6402_w)
677	723	{
678		royalmah_state *state = space->machine().driver_data<royalmah_state>();
679		state->m_gfx_adr_h = data & 1;
680		state->m_gfx_adr = state->m_gfx_adr_h*0x10000 + state->m_gfx_adr_m*0x100 + state->m_gfx_adr_l;
	724	m_gfx_adr_h = data & 1;
	725	m_gfx_adr = m_gfx_adr_h*0x10000 + m_gfx_adr_m*0x100 + m_gfx_adr_l;
681	726	}
682	727
683		static READ8_HANDLER( jansou_6403_r )
	728	READ8_MEMBER(royalmah_state::jansou_6403_r)
684	729	{
685		royalmah_state *state = space->machine().driver_data<royalmah_state>();
686		UINT8 *GFXROM = space->machine().region("gfx1")->base();
687		int d0 = GFXROM[state->m_gfx_adr];
688		int d1 = GFXROM[state->m_gfx_adr+1];
689		int c0 = state->m_jansou_colortable[d1 & 0x0f] & 0x0f;
690		int c1 = state->m_jansou_colortable[(d1 & 0xf0) >> 4] >> 4;
691		int c2 = state->m_jansou_colortable[d0 & 0x0f] & 0x0f;
692		int c3 = state->m_jansou_colortable[(d0 & 0xf0) >> 4] >> 4;
	730	UINT8 *GFXROM = machine().region("gfx1")->base();
	731	int d0 = GFXROM[m_gfx_adr];
	732	int d1 = GFXROM[m_gfx_adr+1];
	733	int c0 = m_jansou_colortable[d1 & 0x0f] & 0x0f;
	734	int c1 = m_jansou_colortable[(d1 & 0xf0) >> 4] >> 4;
	735	int c2 = m_jansou_colortable[d0 & 0x0f] & 0x0f;
	736	int c3 = m_jansou_colortable[(d0 & 0xf0) >> 4] >> 4;
693	737
694		state->m_gfx_adr += 2;
	738	m_gfx_adr += 2;
695	739
696		state->m_gfxdata0 = (c3 & 1) << 0 | ((c2 & 1) << 1) | ((c1 & 1) << 2) | ((c0 & 1) << 3)
	740	m_gfxdata0 = (c3 & 1) << 0 | ((c2 & 1) << 1) | ((c1 & 1) << 2) | ((c0 & 1) << 3)
697	741	| ((c3 & 2) << 3) | ((c2 & 2) << 4) | ((c1 & 2) << 5) | ((c0 & 2) << 6);
698		state->m_gfxdata1 = (c3 & 4) >> 2 | ((c2 & 4) >> 1) | (c1 & 4) | ((c0 & 4) << 1)
	742	m_gfxdata1 = (c3 & 4) >> 2 | ((c2 & 4) >> 1) | (c1 & 4) | ((c0 & 4) << 1)
699	743	| ((c3 & 8) << 1) | ((c2 & 8) << 2) | ((c1 & 8) << 3) | ((c0 & 8) << 4);
700	744
701	745	return 0xff;
702	746	}
703	747
704		static READ8_HANDLER( jansou_6404_r )
	748	READ8_MEMBER(royalmah_state::jansou_6404_r)
705	749	{
706		royalmah_state *state = space->machine().driver_data<royalmah_state>();
707		return state->m_gfxdata0;
	750	return m_gfxdata0;
708	751	}
709	752
710		static READ8_HANDLER( jansou_6405_r )
	753	READ8_MEMBER(royalmah_state::jansou_6405_r)
711	754	{
712		royalmah_state *state = space->machine().driver_data<royalmah_state>();
713		return state->m_gfxdata1;
	755	return m_gfxdata1;
714	756	}
715	757
716		static WRITE8_HANDLER( jansou_sound_w )
	758	WRITE8_MEMBER(royalmah_state::jansou_sound_w)
717	759	{
718	760	soundlatch_w(space, 0, data);
719		cputag_set_input_line(space->machine(), "audiocpu", INPUT_LINE_NMI, PULSE_LINE);
	761	cputag_set_input_line(machine(), "audiocpu", INPUT_LINE_NMI, PULSE_LINE);
720	762	}
721	763
722	764
r14845	r14846
724	766	static ADDRESS_MAP_START( jansou_map, AS_PROGRAM, 8, royalmah_state )
725	767	AM_RANGE( 0x0000, 0x3fff ) AM_ROM
726	768
727		AM_RANGE( 0x6000, 0x600f ) AM_WRITE_LEGACY(jansou_colortable_w)
728		AM_RANGE( 0x6400, 0x6400 ) AM_WRITE_LEGACY(jansou_6400_w)
729		AM_RANGE( 0x6401, 0x6401 ) AM_WRITE_LEGACY(jansou_6401_w)
730		AM_RANGE( 0x6402, 0x6402 ) AM_WRITE_LEGACY(jansou_6402_w)
731		AM_RANGE( 0x6403, 0x6403 ) AM_READ_LEGACY(jansou_6403_r)
732		AM_RANGE( 0x6404, 0x6404 ) AM_READ_LEGACY(jansou_6404_r)
733		AM_RANGE( 0x6405, 0x6405 ) AM_READ_LEGACY(jansou_6405_r)
734		AM_RANGE( 0x6406, 0x6406 ) AM_WRITE_LEGACY(jansou_dsw_sel_w)
735		AM_RANGE( 0x6407, 0x6407 ) AM_READ_LEGACY(jansou_dsw_r)
736		AM_RANGE( 0x6800, 0x6800 ) AM_WRITE_LEGACY(jansou_sound_w)
	769	AM_RANGE( 0x6000, 0x600f ) AM_WRITE(jansou_colortable_w)
	770	AM_RANGE( 0x6400, 0x6400 ) AM_WRITE(jansou_6400_w)
	771	AM_RANGE( 0x6401, 0x6401 ) AM_WRITE(jansou_6401_w)
	772	AM_RANGE( 0x6402, 0x6402 ) AM_WRITE(jansou_6402_w)
	773	AM_RANGE( 0x6403, 0x6403 ) AM_READ(jansou_6403_r)
	774	AM_RANGE( 0x6404, 0x6404 ) AM_READ(jansou_6404_r)
	775	AM_RANGE( 0x6405, 0x6405 ) AM_READ(jansou_6405_r)
	776	AM_RANGE( 0x6406, 0x6406 ) AM_WRITE(jansou_dsw_sel_w)
	777	AM_RANGE( 0x6407, 0x6407 ) AM_READ(jansou_dsw_r)
	778	AM_RANGE( 0x6800, 0x6800 ) AM_WRITE(jansou_sound_w)
737	779
738	780	AM_RANGE( 0x7000, 0x77ff ) AM_RAM AM_SHARE("nvram")
739	781	AM_RANGE( 0x8000, 0xffff ) AM_WRITEONLY AM_BASE(m_videoram)
r14845	r14846
762	804	AM_RANGE( 0x8000, 0xffff ) AM_WRITEONLY AM_BASE(m_videoram)
763	805	ADDRESS_MAP_END
764	806
765		static WRITE8_HANDLER( janptr96_dswsel_w )
	807	WRITE8_MEMBER(royalmah_state::janptr96_dswsel_w)
766	808	{
767		royalmah_state *state = space->machine().driver_data<royalmah_state>();
768	809	// 0x20 = 0 -> hopper on
769	810	// 0x40 ?
770		state->m_dsw_select = data;
	811	m_dsw_select = data;
771	812	}
772	813
773		static READ8_HANDLER( janptr96_dswsel_r )
	814	READ8_MEMBER(royalmah_state::janptr96_dswsel_r)
774	815	{
775		royalmah_state *state = space->machine().driver_data<royalmah_state>();
776		return state->m_dsw_select;
	816	return m_dsw_select;
777	817	}
778	818
779		static READ8_HANDLER( janptr96_dsw_r )
	819	READ8_MEMBER(royalmah_state::janptr96_dsw_r)
780	820	{
781		royalmah_state *state = space->machine().driver_data<royalmah_state>();
782		if (~state->m_dsw_select & 0x01) return input_port_read(space->machine(), "DSW4");
783		if (~state->m_dsw_select & 0x02) return input_port_read(space->machine(), "DSW3");
784		if (~state->m_dsw_select & 0x04) return input_port_read(space->machine(), "DSW2");
785		if (~state->m_dsw_select & 0x08) return input_port_read(space->machine(), "DSW1");
786		if (~state->m_dsw_select & 0x10) return input_port_read(space->machine(), "DSWTOP");
	821	if (~m_dsw_select & 0x01) return input_port_read(machine(), "DSW4");
	822	if (~m_dsw_select & 0x02) return input_port_read(machine(), "DSW3");
	823	if (~m_dsw_select & 0x04) return input_port_read(machine(), "DSW2");
	824	if (~m_dsw_select & 0x08) return input_port_read(machine(), "DSW1");
	825	if (~m_dsw_select & 0x10) return input_port_read(machine(), "DSWTOP");
787	826	return 0xff;
788	827	}
789	828
790		static WRITE8_HANDLER( janptr96_rombank_w )
	829	WRITE8_MEMBER(royalmah_state::janptr96_rombank_w)
791	830	{
792		UINT8 *ROM = space->machine().region("maincpu")->base();
793		memory_set_bankptr(space->machine(), "bank1",ROM + 0x10000 + 0x8000 * data);
	831	UINT8 *ROM = machine().region("maincpu")->base();
	832	memory_set_bankptr(machine(), "bank1",ROM + 0x10000 + 0x8000 * data);
794	833	}
795	834
796		static WRITE8_HANDLER( janptr96_rambank_w )
	835	WRITE8_MEMBER(royalmah_state::janptr96_rambank_w)
797	836	{
798		royalmah_state *state = space->machine().driver_data<royalmah_state>();
799		memory_set_bankptr(space->machine(), "bank2", state->m_janptr96_nvram + 0x1000 + 0x1000 * data);
	837	memory_set_bankptr(machine(), "bank2", m_janptr96_nvram + 0x1000 + 0x1000 * data);
800	838	}
801	839
802		static READ8_HANDLER( janptr96_unknown_r )
	840	READ8_MEMBER(royalmah_state::janptr96_unknown_r)
803	841	{
804	842	// 0x08 = 0 makes the game crash (e.g. in the m-ram test: nested interrupts?)
805	843	return 0xff;
806	844	}
807	845
808		static WRITE8_HANDLER( janptr96_coin_counter_w )
	846	WRITE8_MEMBER(royalmah_state::janptr96_coin_counter_w)
809	847	{
810		flip_screen_set(space->machine(), ~data & 4);
811		coin_counter_w(space->machine(), 0,data & 2);   // in
812		coin_counter_w(space->machine(), 1,data & 1);   // out
	848	flip_screen_set(machine(), ~data & 4);
	849	coin_counter_w(machine(), 0,data & 2);   // in
	850	coin_counter_w(machine(), 1,data & 1);   // out
813	851	}
814	852
815	853	static ADDRESS_MAP_START( janptr96_iomap, AS_IO, 8, royalmah_state )
816	854	ADDRESS_MAP_GLOBAL_MASK(0xff)
817		AM_RANGE( 0x00, 0x00 ) AM_WRITE_LEGACY(janptr96_rombank_w )   // BANK ROM Select
818		AM_RANGE( 0x1e, 0x1e ) AM_READWRITE_LEGACY(janptr96_dswsel_r, janptr96_dswsel_w )
819		AM_RANGE( 0x1c, 0x1c ) AM_READ_LEGACY(janptr96_dsw_r )
820		AM_RANGE( 0x20, 0x20 ) AM_READWRITE_LEGACY(janptr96_unknown_r, janptr96_rambank_w )
821		AM_RANGE( 0x50, 0x50 ) AM_WRITE_LEGACY(mjderngr_palbank_w )
	855	AM_RANGE( 0x00, 0x00 ) AM_WRITE(janptr96_rombank_w )   // BANK ROM Select
	856	AM_RANGE( 0x1e, 0x1e ) AM_READWRITE(janptr96_dswsel_r, janptr96_dswsel_w )
	857	AM_RANGE( 0x1c, 0x1c ) AM_READ(janptr96_dsw_r )
	858	AM_RANGE( 0x20, 0x20 ) AM_READWRITE(janptr96_unknown_r, janptr96_rambank_w )
	859	AM_RANGE( 0x50, 0x50 ) AM_WRITE(mjderngr_palbank_w )
822	860	AM_RANGE( 0x60, 0x6f ) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
823	861	AM_RANGE( 0x81, 0x81 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
824	862	AM_RANGE( 0x82, 0x83 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
825		AM_RANGE( 0x93, 0x93 ) AM_WRITE_LEGACY(input_port_select_w )
826		AM_RANGE( 0xd8, 0xd8 ) AM_WRITE_LEGACY(janptr96_coin_counter_w )
	863	AM_RANGE( 0x93, 0x93 ) AM_WRITE(input_port_select_w )
	864	AM_RANGE( 0xd8, 0xd8 ) AM_WRITE(janptr96_coin_counter_w )
827	865	AM_RANGE( 0xd9, 0xd9 ) AM_READ_PORT("SYSTEM")
828	866	ADDRESS_MAP_END
829	867
r14845	r14846
832	870	****************************************************************************/
833	871
834	872
835		static WRITE8_HANDLER( mjifb_coin_counter_w )
	873	WRITE8_MEMBER(royalmah_state::mjifb_coin_counter_w)
836	874	{
837		flip_screen_set(space->machine(),  data & 4);
838		coin_counter_w(space->machine(), 0,data & 2);   // in
839		coin_counter_w(space->machine(), 1,data & 1);   // out
	875	flip_screen_set(machine(),  data & 4);
	876	coin_counter_w(machine(), 0,data & 2);   // in
	877	coin_counter_w(machine(), 1,data & 1);   // out
840	878	}
841	879
842		static READ8_HANDLER( mjifb_rom_io_r )
	880	READ8_MEMBER(royalmah_state::mjifb_rom_io_r)
843	881	{
844		royalmah_state *state = space->machine().driver_data<royalmah_state>();
845		if (state->m_mjifb_rom_enable)
846		return ((UINT8*)(space->machine().region("maincpu")->base() + 0x10000 + state->m_rombank * 0x4000))[offset];
	882	if (m_mjifb_rom_enable)
	883	return ((UINT8*)(machine().region("maincpu")->base() + 0x10000 + m_rombank * 0x4000))[offset];
847	884
848	885	offset += 0x8000;
849	886
850	887	switch(offset)
851	888	{
852		case 0x8000:   return input_port_read(space->machine(), "DSW4");      // dsw 4
853		case 0x8200:   return input_port_read(space->machine(), "DSW3");      // dsw 3
854		case 0x9001:   return ay8910_r(space->machine().device("aysnd"), 0);   // inputs
855		case 0x9011:   return input_port_read(space->machine(), "SYSTEM");
	889	case 0x8000:   return input_port_read(machine(), "DSW4");      // dsw 4
	890	case 0x8200:   return input_port_read(machine(), "DSW3");      // dsw 3
	891	case 0x9001:   return ay8910_r(machine().device("aysnd"), 0);   // inputs
	892	case 0x9011:   return input_port_read(machine(), "SYSTEM");
856	893	}
857	894
858		logerror("%04X: unmapped input read at %04X\n", cpu_get_pc(&space->device()), offset);
	895	logerror("%04X: unmapped input read at %04X\n", cpu_get_pc(&space.device()), offset);
859	896	return 0xff;
860	897	}
861	898
862		static WRITE8_HANDLER( mjifb_rom_io_w )
	899	WRITE8_MEMBER(royalmah_state::mjifb_rom_io_w)
863	900	{
864		royalmah_state *state = space->machine().driver_data<royalmah_state>();
865		UINT8 *videoram = state->m_videoram;
866		if (state->m_mjifb_rom_enable)
	901	UINT8 *videoram = m_videoram;
	902	if (m_mjifb_rom_enable)
867	903	{
868	904	videoram[offset] = data;
869	905	return;
r14845	r14846
873	909
874	910	switch(offset)
875	911	{
876		case 0x8e00:   state->m_palette_base = data & 0x1f;   return;
877		case 0x9002:   ay8910_data_w(space->machine().device("aysnd"),0,data);         return;
878		case 0x9003:   ay8910_address_w(space->machine().device("aysnd"),0,data);      return;
	912	case 0x8e00:   m_palette_base = data & 0x1f;   return;
	913	case 0x9002:   ay8910_data_w(machine().device("aysnd"),0,data);         return;
	914	case 0x9003:   ay8910_address_w(machine().device("aysnd"),0,data);      return;
879	915	case 0x9010:
880	916	mjifb_coin_counter_w(space,0,data);
881	917	return;
r14845	r14846
885	921	return;
886	922	}
887	923
888		logerror("%04X: unmapped input write at %04X = %02X\n", cpu_get_pc(&space->device()), offset,data);
	924	logerror("%04X: unmapped input write at %04X = %02X\n", cpu_get_pc(&space.device()), offset,data);
889	925	}
890	926
891		static WRITE8_HANDLER( mjifb_videoram_w )
	927	WRITE8_MEMBER(royalmah_state::mjifb_videoram_w)
892	928	{
893		royalmah_state *state = space->machine().driver_data<royalmah_state>();
894		UINT8 *videoram = state->m_videoram;
	929	UINT8 *videoram = m_videoram;
895	930	videoram[offset + 0x4000] = data;
896	931	}
897	932
898	933	static ADDRESS_MAP_START( mjifb_map, AS_PROGRAM, 8, royalmah_state )
899	934	AM_RANGE( 0x0000, 0x6fff ) AM_ROM
900	935	AM_RANGE( 0x7000, 0x7fff ) AM_RAM AM_SHARE("nvram")
901		AM_RANGE( 0x8000, 0xbfff ) AM_READWRITE_LEGACY(mjifb_rom_io_r, mjifb_rom_io_w) AM_BASE(m_videoram)
902		AM_RANGE( 0xc000, 0xffff ) AM_ROM AM_WRITE_LEGACY(mjifb_videoram_w)
	936	AM_RANGE( 0x8000, 0xbfff ) AM_READWRITE(mjifb_rom_io_r, mjifb_rom_io_w) AM_BASE(m_videoram)
	937	AM_RANGE( 0xc000, 0xffff ) AM_ROM AM_WRITE(mjifb_videoram_w)
903	938	//  AM_RANGE( 0xc000, 0xffff ) AM_ROM AM_WRITEONLY  This should, but doesn't work
904	939	ADDRESS_MAP_END
905	940
906		static READ8_HANDLER( mjifb_p3_r )
	941	READ8_MEMBER(royalmah_state::mjifb_p3_r)
907	942	{
908		return input_port_read(space->machine(), "PORT3_5") >> 6;
	943	return input_port_read(machine(), "PORT3_5") >> 6;
909	944	}
910		static READ8_HANDLER( mjifb_p5_r )
	945	READ8_MEMBER(royalmah_state::mjifb_p5_r)
911	946	{
912		return input_port_read(space->machine(), "PORT3_5");
	947	return input_port_read(machine(), "PORT3_5");
913	948	}
914		static READ8_HANDLER( mjifb_p6_r )
	949	READ8_MEMBER(royalmah_state::mjifb_p6_r)
915	950	{
916		return input_port_read(space->machine(), "PORT6_7");
	951	return input_port_read(machine(), "PORT6_7");
917	952	}
918		static READ8_HANDLER( mjifb_p7_r )
	953	READ8_MEMBER(royalmah_state::mjifb_p7_r)
919	954	{
920		return input_port_read(space->machine(), "PORT6_7") >> 4;
	955	return input_port_read(machine(), "PORT6_7") >> 4;
921	956	}
922		static READ8_HANDLER( mjifb_p8_r )
	957	READ8_MEMBER(royalmah_state::mjifb_p8_r)
923	958	{
924	959	return 0xff;
925	960	}
926	961
927		static WRITE8_HANDLER( mjifb_p3_w )
	962	WRITE8_MEMBER(royalmah_state::mjifb_p3_w)
928	963	{
929		royalmah_state *state = space->machine().driver_data<royalmah_state>();
930		state->m_rombank = (state->m_rombank & 0x0f) | ((data & 0x0c) << 2);
	964	m_rombank = (m_rombank & 0x0f) | ((data & 0x0c) << 2);
931	965	}
932		static WRITE8_HANDLER( mjifb_p4_w )
	966	WRITE8_MEMBER(royalmah_state::mjifb_p4_w)
933	967	{
934		royalmah_state *state = space->machine().driver_data<royalmah_state>();
935		state->m_rombank = (state->m_rombank & 0xf0) | (data & 0x0f);
	968	m_rombank = (m_rombank & 0xf0) | (data & 0x0f);
936	969	}
937		static WRITE8_HANDLER( mjifb_p8_w )
	970	WRITE8_MEMBER(royalmah_state::mjifb_p8_w)
938	971	{
939		royalmah_state *state = space->machine().driver_data<royalmah_state>();
940		state->m_mjifb_rom_enable = (data & 0x08);
	972	m_mjifb_rom_enable = (data & 0x08);
941	973	}
942	974
943	975	static ADDRESS_MAP_START( mjifb_iomap, AS_IO, 8, royalmah_state )
944		AM_RANGE( T90_P3, T90_P3 ) AM_READWRITE_LEGACY(mjifb_p3_r, mjifb_p3_w )
945		AM_RANGE( T90_P4, T90_P4 ) AM_WRITE_LEGACY(mjifb_p4_w )
946		AM_RANGE( T90_P5, T90_P5 ) AM_READ_LEGACY(mjifb_p5_r )
947		AM_RANGE( T90_P6, T90_P6 ) AM_READ_LEGACY(mjifb_p6_r )
948		AM_RANGE( T90_P7, T90_P7 ) AM_READ_LEGACY(mjifb_p7_r )
949		AM_RANGE( T90_P8, T90_P8 ) AM_READWRITE_LEGACY(mjifb_p8_r, mjifb_p8_w )
	976	AM_RANGE( T90_P3, T90_P3 ) AM_READWRITE(mjifb_p3_r, mjifb_p3_w )
	977	AM_RANGE( T90_P4, T90_P4 ) AM_WRITE(mjifb_p4_w )
	978	AM_RANGE( T90_P5, T90_P5 ) AM_READ(mjifb_p5_r )
	979	AM_RANGE( T90_P6, T90_P6 ) AM_READ(mjifb_p6_r )
	980	AM_RANGE( T90_P7, T90_P7 ) AM_READ(mjifb_p7_r )
	981	AM_RANGE( T90_P8, T90_P8 ) AM_READWRITE(mjifb_p8_r, mjifb_p8_w )
950	982	ADDRESS_MAP_END
951	983
952	984
r14845	r14846
954	986	Mahjong Shinkirou Deja Vu
955	987	****************************************************************************/
956	988
957		static READ8_HANDLER( mjdejavu_rom_io_r )
	989	READ8_MEMBER(royalmah_state::mjdejavu_rom_io_r)
958	990	{
959		royalmah_state *state = space->machine().driver_data<royalmah_state>();
960		if (state->m_mjifb_rom_enable)
961		return ((UINT8*)(space->machine().region("maincpu")->base() + 0x10000 + state->m_rombank * 0x4000))[offset];
	991	if (m_mjifb_rom_enable)
	992	return ((UINT8*)(machine().region("maincpu")->base() + 0x10000 + m_rombank * 0x4000))[offset];
962	993
963	994	offset += 0x8000;
964	995
965	996	switch(offset)
966	997	{
967		case 0x8000:   return input_port_read(space->machine(), "DSW2");      // dsw 2
968		case 0x8001:   return input_port_read(space->machine(), "DSW1");      // dsw 1
969		case 0x9001:   return ay8910_r(space->machine().device("aysnd"), 0);   // inputs
970		case 0x9011:   return input_port_read(space->machine(), "SYSTEM");
	998	case 0x8000:   return input_port_read(machine(), "DSW2");      // dsw 2
	999	case 0x8001:   return input_port_read(machine(), "DSW1");      // dsw 1
	1000	case 0x9001:   return ay8910_r(machine().device("aysnd"), 0);   // inputs
	1001	case 0x9011:   return input_port_read(machine(), "SYSTEM");
971	1002	}
972	1003
973		logerror("%04X: unmapped input read at %04X\n", cpu_get_pc(&space->device()), offset);
	1004	logerror("%04X: unmapped input read at %04X\n", cpu_get_pc(&space.device()), offset);
974	1005	return 0xff;
975	1006	}
976	1007
977		static WRITE8_HANDLER( mjdejavu_rom_io_w )
	1008	WRITE8_MEMBER(royalmah_state::mjdejavu_rom_io_w)
978	1009	{
979		royalmah_state *state = space->machine().driver_data<royalmah_state>();
980		UINT8 *videoram = state->m_videoram;
981		if (state->m_mjifb_rom_enable)
	1010	UINT8 *videoram = m_videoram;
	1011	if (m_mjifb_rom_enable)
982	1012	{
983	1013	videoram[offset] = data;
984	1014	return;
r14845	r14846
987	1017	offset += 0x8000;
988	1018	switch(offset)
989	1019	{
990		case 0x8802:   state->m_palette_base = data & 0x1f;               return;
991		case 0x9002:   ay8910_data_w(space->machine().device("aysnd"),0,data);      return;
992		case 0x9003:   ay8910_address_w(space->machine().device("aysnd"),0,data);   return;
	1020	case 0x8802:   m_palette_base = data & 0x1f;               return;
	1021	case 0x9002:   ay8910_data_w(machine().device("aysnd"),0,data);      return;
	1022	case 0x9003:   ay8910_address_w(machine().device("aysnd"),0,data);   return;
993	1023	case 0x9010:   mjifb_coin_counter_w(space,0,data);      return;
994	1024	case 0x9011:   input_port_select_w(space,0,data);      return;
995	1025	case 0x9013:
r14845	r14846
997	1027	return;
998	1028	}
999	1029
1000		logerror("%04X: unmapped input write at %04X = %02X\n", cpu_get_pc(&space->device()), offset,data);
	1030	logerror("%04X: unmapped input write at %04X = %02X\n", cpu_get_pc(&space.device()), offset,data);
1001	1031	}
1002	1032
1003	1033	static ADDRESS_MAP_START( mjdejavu_map, AS_PROGRAM, 8, royalmah_state )
1004	1034	AM_RANGE( 0x0000, 0x6fff ) AM_ROM
1005	1035	AM_RANGE( 0x7000, 0x7fff ) AM_RAM AM_SHARE("nvram")
1006		AM_RANGE( 0x8000, 0xbfff ) AM_READWRITE_LEGACY(mjdejavu_rom_io_r, mjdejavu_rom_io_w) AM_BASE(m_videoram)
1007		AM_RANGE( 0xc000, 0xffff ) AM_ROM AM_WRITE_LEGACY(mjifb_videoram_w)
	1036	AM_RANGE( 0x8000, 0xbfff ) AM_READWRITE(mjdejavu_rom_io_r, mjdejavu_rom_io_w) AM_BASE(m_videoram)
	1037	AM_RANGE( 0xc000, 0xffff ) AM_ROM AM_WRITE(mjifb_videoram_w)
1008	1038	ADDRESS_MAP_END
1009	1039
1010	1040
r14845	r14846
1012	1042	Mahjong Tensinhai
1013	1043	****************************************************************************/
1014	1044
1015		static READ8_HANDLER( mjtensin_p3_r )
	1045	READ8_MEMBER(royalmah_state::mjtensin_p3_r)
1016	1046	{
1017	1047	return 0xff;
1018	1048	}
r14845	r14846
1022	1052	royalmah_state *state = machine.driver_data<royalmah_state>();
1023	1053	memory_set_bankptr(machine,  "bank1", machine.region("maincpu")->base() + 0x10000 + state->m_rombank * 0x8000 );
1024	1054	}
1025		static WRITE8_HANDLER( mjtensin_p4_w )
	1055	WRITE8_MEMBER(royalmah_state::mjtensin_p4_w)
1026	1056	{
1027		royalmah_state *state = space->machine().driver_data<royalmah_state>();
1028		state->m_rombank = (state->m_rombank & 0xf0) | (data & 0x0f);
1029		mjtensin_update_rombank(space->machine());
	1057	m_rombank = (m_rombank & 0xf0) | (data & 0x0f);
	1058	mjtensin_update_rombank(machine());
1030	1059	}
1031		static WRITE8_HANDLER( mjtensin_6ff3_w )
	1060	WRITE8_MEMBER(royalmah_state::mjtensin_6ff3_w)
1032	1061	{
1033		royalmah_state *state = space->machine().driver_data<royalmah_state>();
1034		state->m_rombank = (data << 4) | (state->m_rombank & 0x0f);
1035		mjtensin_update_rombank(space->machine());
	1062	m_rombank = (data << 4) | (m_rombank & 0x0f);
	1063	mjtensin_update_rombank(machine());
1036	1064	}
1037	1065
1038	1066	static ADDRESS_MAP_START( mjtensin_map, AS_PROGRAM, 8, royalmah_state )
r14845	r14846
1040	1068	AM_RANGE( 0x6000, 0x6fbf ) AM_RAM
1041	1069	AM_RANGE( 0x6fc1, 0x6fc1 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
1042	1070	AM_RANGE( 0x6fc2, 0x6fc3 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
1043		AM_RANGE( 0x6fd0, 0x6fd0 ) AM_WRITE_LEGACY(janptr96_coin_counter_w )
1044		AM_RANGE( 0x6fd1, 0x6fd1 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
	1071	AM_RANGE( 0x6fd0, 0x6fd0 ) AM_WRITE(janptr96_coin_counter_w )
	1072	AM_RANGE( 0x6fd1, 0x6fd1 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
1045	1073	AM_RANGE( 0x6fe0, 0x6fef ) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
1046		AM_RANGE( 0x6ff0, 0x6ff0 ) AM_READWRITE_LEGACY(janptr96_dsw_r, janptr96_dswsel_w )
1047		AM_RANGE( 0x6ff1, 0x6ff1 ) AM_WRITE_LEGACY(mjderngr_palbank_w )
1048		AM_RANGE( 0x6ff3, 0x6ff3 ) AM_WRITE_LEGACY(mjtensin_6ff3_w )
	1074	AM_RANGE( 0x6ff0, 0x6ff0 ) AM_READWRITE(janptr96_dsw_r, janptr96_dswsel_w )
	1075	AM_RANGE( 0x6ff1, 0x6ff1 ) AM_WRITE(mjderngr_palbank_w )
	1076	AM_RANGE( 0x6ff3, 0x6ff3 ) AM_WRITE(mjtensin_6ff3_w )
1049	1077	AM_RANGE( 0x7000, 0x7fff ) AM_RAM AM_SHARE("nvram")
1050	1078	AM_RANGE( 0x8000, 0xffff ) AM_ROMBANK( "bank1" )
1051	1079	AM_RANGE( 0x8000, 0xffff ) AM_WRITEONLY AM_BASE(m_videoram)
1052	1080	ADDRESS_MAP_END
1053	1081
1054	1082	static ADDRESS_MAP_START( mjtensin_iomap, AS_IO, 8, royalmah_state )
1055		AM_RANGE( T90_P3, T90_P3 ) AM_READ_LEGACY(mjtensin_p3_r )
1056		AM_RANGE( T90_P4, T90_P4 ) AM_WRITE_LEGACY(mjtensin_p4_w )
	1083	AM_RANGE( T90_P3, T90_P3 ) AM_READ(mjtensin_p3_r )
	1084	AM_RANGE( T90_P4, T90_P4 ) AM_WRITE(mjtensin_p4_w )
1057	1085	ADDRESS_MAP_END
1058	1086
1059	1087
r14845	r14846
1066	1094	royalmah_state *state = machine.driver_data<royalmah_state>();
1067	1095	memory_set_bankptr(machine,  "bank1", machine.region("maincpu")->base() + 0x10000 + state->m_rombank * 0x8000 );
1068	1096	}
1069		static WRITE8_HANDLER( cafetime_p4_w )
	1097	WRITE8_MEMBER(royalmah_state::cafetime_p4_w)
1070	1098	{
1071		royalmah_state *state = space->machine().driver_data<royalmah_state>();
1072		state->m_rombank = (state->m_rombank & 0xf0) | (data & 0x0f);
1073		cafetime_update_rombank(space->machine());
	1099	m_rombank = (m_rombank & 0xf0) | (data & 0x0f);
	1100	cafetime_update_rombank(machine());
1074	1101	}
1075		static WRITE8_HANDLER( cafetime_p3_w )
	1102	WRITE8_MEMBER(royalmah_state::cafetime_p3_w)
1076	1103	{
1077		royalmah_state *state = space->machine().driver_data<royalmah_state>();
1078		state->m_rombank = (state->m_rombank & 0x0f) | ((data & 0x0c) << 2);
1079		cafetime_update_rombank(space->machine());
	1104	m_rombank = (m_rombank & 0x0f) | ((data & 0x0c) << 2);
	1105	cafetime_update_rombank(machine());
1080	1106	}
1081	1107
1082		static WRITE8_HANDLER( cafetime_dsw_w )
	1108	WRITE8_MEMBER(royalmah_state::cafetime_dsw_w)
1083	1109	{
1084		royalmah_state *state = space->machine().driver_data<royalmah_state>();
1085		state->m_dsw_select = data;
	1110	m_dsw_select = data;
1086	1111	}
1087		static READ8_HANDLER( cafetime_dsw_r )
	1112	READ8_MEMBER(royalmah_state::cafetime_dsw_r)
1088	1113	{
1089		royalmah_state *state = space->machine().driver_data<royalmah_state>();
1090		switch( state->m_dsw_select )
	1114	switch( m_dsw_select )
1091	1115	{
1092		case 0x00: return input_port_read(space->machine(), "DSW1");
1093		case 0x01: return input_port_read(space->machine(), "DSW2");
1094		case 0x02: return input_port_read(space->machine(), "DSW3");
1095		case 0x03: return input_port_read(space->machine(), "DSW4");
1096		case 0x04: return input_port_read(space->machine(), "DSWTOP");
	1116	case 0x00: return input_port_read(machine(), "DSW1");
	1117	case 0x01: return input_port_read(machine(), "DSW2");
	1118	case 0x02: return input_port_read(machine(), "DSW3");
	1119	case 0x03: return input_port_read(machine(), "DSW4");
	1120	case 0x04: return input_port_read(machine(), "DSWTOP");
1097	1121	}
1098		logerror("%04X: unmapped dsw read %02X\n", cpu_get_pc(&space->device()), state->m_dsw_select);
	1122	logerror("%04X: unmapped dsw read %02X\n", cpu_get_pc(&space.device()), m_dsw_select);
1099	1123	return 0xff;
1100	1124	}
1101	1125
1102		static READ8_HANDLER( cafetime_7fe4_r )
	1126	READ8_MEMBER(royalmah_state::cafetime_7fe4_r)
1103	1127	{
1104	1128	return 0xff;
1105	1129	}
1106		static WRITE8_HANDLER( cafetime_7fe3_w )
	1130	WRITE8_MEMBER(royalmah_state::cafetime_7fe3_w)
1107	1131	{
1108	1132	//  popmessage("%02x",data);
1109	1133	}
r14845	r14846
1113	1137	AM_RANGE( 0x6000, 0x7eff ) AM_RAM AM_SHARE("nvram")
1114	1138	AM_RANGE( 0x7fc1, 0x7fc1 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
1115	1139	AM_RANGE( 0x7fc2, 0x7fc3 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
1116		AM_RANGE( 0x7fd0, 0x7fd0 ) AM_WRITE_LEGACY(janptr96_coin_counter_w )
	1140	AM_RANGE( 0x7fd0, 0x7fd0 ) AM_WRITE(janptr96_coin_counter_w )
1117	1141	AM_RANGE( 0x7fd1, 0x7fd1 ) AM_READ_PORT("SYSTEM") AM_WRITENOP
1118		AM_RANGE( 0x7fd3, 0x7fd3 ) AM_WRITE_LEGACY(input_port_select_w )
1119		AM_RANGE( 0x7fe0, 0x7fe0 ) AM_READ_LEGACY(cafetime_dsw_r )
1120		AM_RANGE( 0x7fe1, 0x7fe1 ) AM_WRITE_LEGACY(cafetime_dsw_w )
1121		AM_RANGE( 0x7fe2, 0x7fe2 ) AM_WRITE_LEGACY(mjderngr_palbank_w )
1122		AM_RANGE( 0x7fe3, 0x7fe3 ) AM_WRITE_LEGACY(cafetime_7fe3_w )
1123		AM_RANGE( 0x7fe4, 0x7fe4 ) AM_READ_LEGACY(cafetime_7fe4_r )
	1142	AM_RANGE( 0x7fd3, 0x7fd3 ) AM_WRITE(input_port_select_w )
	1143	AM_RANGE( 0x7fe0, 0x7fe0 ) AM_READ(cafetime_dsw_r )
	1144	AM_RANGE( 0x7fe1, 0x7fe1 ) AM_WRITE(cafetime_dsw_w )
	1145	AM_RANGE( 0x7fe2, 0x7fe2 ) AM_WRITE(mjderngr_palbank_w )
	1146	AM_RANGE( 0x7fe3, 0x7fe3 ) AM_WRITE(cafetime_7fe3_w )
	1147	AM_RANGE( 0x7fe4, 0x7fe4 ) AM_READ(cafetime_7fe4_r )
1124	1148	AM_RANGE( 0x7ff0, 0x7fff ) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
1125	1149	AM_RANGE( 0x8000, 0xffff ) AM_ROMBANK( "bank1" )
1126	1150	AM_RANGE( 0x8000, 0xffff ) AM_WRITEONLY AM_BASE(m_videoram)
r14845	r14846
1128	1152
1129	1153
1130	1154	static ADDRESS_MAP_START( cafetime_iomap, AS_IO, 8, royalmah_state )
1131		AM_RANGE( T90_P3, T90_P3 ) AM_WRITE_LEGACY(cafetime_p3_w )
1132		AM_RANGE( T90_P4, T90_P4 ) AM_WRITE_LEGACY(cafetime_p4_w )
	1155	AM_RANGE( T90_P3, T90_P3 ) AM_WRITE(cafetime_p3_w )
	1156	AM_RANGE( T90_P4, T90_P4 ) AM_WRITE(cafetime_p4_w )
1133	1157	ADDRESS_MAP_END
1134	1158
1135	1159
r14845	r14846
1137	1161	Mahjong Vegas
1138	1162	****************************************************************************/
1139	1163
1140		static WRITE8_HANDLER( mjvegasa_p4_w )
	1164	WRITE8_MEMBER(royalmah_state::mjvegasa_p4_w)
1141	1165	{
1142		royalmah_state *state = space->machine().driver_data<royalmah_state>();
1143		state->m_rombank = (state->m_rombank & 0xf8) | ((data & 0x0e) >> 1);
	1166	m_rombank = (m_rombank & 0xf8) | ((data & 0x0e) >> 1);
1144	1167	}
1145		static WRITE8_HANDLER( mjvegasa_p3_w )
	1168	WRITE8_MEMBER(royalmah_state::mjvegasa_p3_w)
1146	1169	{
1147		royalmah_state *state = space->machine().driver_data<royalmah_state>();
1148		state->m_rombank = (state->m_rombank & 0xf7) | ((data & 0x04) << 1);
	1170	m_rombank = (m_rombank & 0xf7) | ((data & 0x04) << 1);
1149	1171	}
1150		static WRITE8_HANDLER( mjvegasa_rombank_w )
	1172	WRITE8_MEMBER(royalmah_state::mjvegasa_rombank_w)
1151	1173	{
1152		royalmah_state *state = space->machine().driver_data<royalmah_state>();
1153		state->m_rombank = (state->m_rombank & 0x0f) | ((data & 0x0f) << 4);
	1174	m_rombank = (m_rombank & 0x0f) | ((data & 0x0f) << 4);
1154	1175	}
1155	1176
1156		static READ8_HANDLER( mjvegasa_rom_io_r )
	1177	READ8_MEMBER(royalmah_state::mjvegasa_rom_io_r)
1157	1178	{
1158		royalmah_state *state = space->machine().driver_data<royalmah_state>();
1159		if ((state->m_rombank & 0x70) != 0x70)
1160		return space->machine().region("maincpu")->base()[0x10000 + state->m_rombank * 0x8000 + offset];
	1179	if ((m_rombank & 0x70) != 0x70)
	1180	return machine().region("maincpu")->base()[0x10000 + m_rombank * 0x8000 + offset];
1161	1181
1162	1182	offset += 0x8000;
1163	1183
1164	1184	if((offset & 0xfff0) == 0x8000)
1165	1185	{
1166		msm6242_device *rtc = space->machine().device<msm6242_device>("rtc");
	1186	msm6242_device *rtc = machine().device<msm6242_device>("rtc");
1167	1187
1168		return rtc->read(*space, offset & 0xf);
	1188	return rtc->read(*&space, offset & 0xf);
1169	1189	}
1170	1190
1171		logerror("%04X: unmapped IO read at %04X\n", cpu_get_pc(&space->device()), offset);
	1191	logerror("%04X: unmapped IO read at %04X\n", cpu_get_pc(&space.device()), offset);
1172	1192	return 0xff;
1173	1193	}
1174	1194
1175		static WRITE8_HANDLER( mjvegasa_rom_io_w )
	1195	WRITE8_MEMBER(royalmah_state::mjvegasa_rom_io_w)
1176	1196	{
1177		royalmah_state *state = space->machine().driver_data<royalmah_state>();
1178		UINT8 *videoram = state->m_videoram;
1179		if ((state->m_rombank & 0x70) != 0x70)
	1197	UINT8 *videoram = m_videoram;
	1198	if ((m_rombank & 0x70) != 0x70)
1180	1199	{
1181	1200	videoram[offset] = data;
1182	1201	return;
r14845	r14846
1186	1205
1187	1206	if((offset & 0xfff0) == 0x8000)
1188	1207	{
1189		msm6242_device *rtc = space->machine().device<msm6242_device>("rtc");
	1208	msm6242_device *rtc = machine().device<msm6242_device>("rtc");
1190	1209
1191		rtc->write(*space, offset & 0xf,data);
	1210	rtc->write(*&space, offset & 0xf,data);
1192	1211	return;
1193	1212	}
1194	1213
1195		logerror("%04X: unmapped IO write at %04X = %02X\n", cpu_get_pc(&space->device()), offset,data);
	1214	logerror("%04X: unmapped IO write at %04X = %02X\n", cpu_get_pc(&space.device()), offset,data);
1196	1215	}
1197	1216
1198		static WRITE8_HANDLER( mjvegasa_coin_counter_w )
	1217	WRITE8_MEMBER(royalmah_state::mjvegasa_coin_counter_w)
1199	1218	{
1200		flip_screen_set(space->machine(),  data & 4);
1201		coin_counter_w(space->machine(), 0,data & 2);   // in
1202		coin_counter_w(space->machine(), 1,data & 1);   // out
	1219	flip_screen_set(machine(),  data & 4);
	1220	coin_counter_w(machine(), 0,data & 2);   // in
	1221	coin_counter_w(machine(), 1,data & 1);   // out
1203	1222	}
1204	1223
1205	1224	// hopper?
1206		static WRITE8_HANDLER( mjvegasa_12400_w )
	1225	WRITE8_MEMBER(royalmah_state::mjvegasa_12400_w)
1207	1226	{
1208	1227	// bits 0 & 1
1209	1228	//  popmessage("UNK: %02x",data);
1210	1229	}
1211		static READ8_HANDLER( mjvegasa_12500_r )
	1230	READ8_MEMBER(royalmah_state::mjvegasa_12500_r)
1212	1231	{
1213	1232	// bits 0 & 2
1214	1233	return 0xff;
r14845	r14846
1218	1237
1219	1238	AM_RANGE( 0x00000, 0x05fff ) AM_ROM
1220	1239	AM_RANGE( 0x06000, 0x07fff ) AM_RAM AM_SHARE("nvram")
1221		AM_RANGE( 0x08000, 0x0ffff ) AM_READWRITE_LEGACY(mjvegasa_rom_io_r, mjvegasa_rom_io_w) AM_BASE(m_videoram)
	1240	AM_RANGE( 0x08000, 0x0ffff ) AM_READWRITE(mjvegasa_rom_io_r, mjvegasa_rom_io_w) AM_BASE(m_videoram)
1222	1241
1223	1242	AM_RANGE( 0x10001, 0x10001 ) AM_DEVREAD_LEGACY("aysnd", ay8910_r )
1224	1243	AM_RANGE( 0x10002, 0x10003 ) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w )
1225		AM_RANGE( 0x10010, 0x10010 ) AM_WRITE_LEGACY(mjvegasa_coin_counter_w )
1226		AM_RANGE( 0x10011, 0x10011 ) AM_READ_PORT("SYSTEM") AM_WRITE_LEGACY(input_port_select_w )
1227		AM_RANGE( 0x10013, 0x10013 ) AM_WRITE_LEGACY(input_port_select_w )
	1244	AM_RANGE( 0x10010, 0x10010 ) AM_WRITE(mjvegasa_coin_counter_w )
	1245	AM_RANGE( 0x10011, 0x10011 ) AM_READ_PORT("SYSTEM") AM_WRITE(input_port_select_w )
	1246	AM_RANGE( 0x10013, 0x10013 ) AM_WRITE(input_port_select_w )
1228	1247
1229		AM_RANGE( 0x12000, 0x12000 ) AM_WRITE_LEGACY(mjvegasa_rombank_w )
1230		AM_RANGE( 0x12100, 0x12100 ) AM_READ_LEGACY(cafetime_dsw_r )
1231		AM_RANGE( 0x12200, 0x12200 ) AM_WRITE_LEGACY(cafetime_dsw_w )
1232		AM_RANGE( 0x12300, 0x12300 ) AM_WRITE_LEGACY(mjderngr_palbank_w )
1233		AM_RANGE( 0x12400, 0x12400 ) AM_WRITE_LEGACY(mjvegasa_12400_w )
1234		AM_RANGE( 0x12500, 0x12500 ) AM_READ_LEGACY(mjvegasa_12500_r )
	1248	AM_RANGE( 0x12000, 0x12000 ) AM_WRITE(mjvegasa_rombank_w )
	1249	AM_RANGE( 0x12100, 0x12100 ) AM_READ(cafetime_dsw_r )
	1250	AM_RANGE( 0x12200, 0x12200 ) AM_WRITE(cafetime_dsw_w )
	1251	AM_RANGE( 0x12300, 0x12300 ) AM_WRITE(mjderngr_palbank_w )
	1252	AM_RANGE( 0x12400, 0x12400 ) AM_WRITE(mjvegasa_12400_w )
	1253	AM_RANGE( 0x12500, 0x12500 ) AM_READ(mjvegasa_12500_r )
1235	1254
1236	1255	ADDRESS_MAP_END
1237	1256
1238	1257	static ADDRESS_MAP_START( mjvegasa_iomap, AS_IO, 8, royalmah_state )
1239		AM_RANGE( T90_P3, T90_P3 ) AM_READWRITE_LEGACY(mjtensin_p3_r, mjvegasa_p3_w )
1240		AM_RANGE( T90_P4, T90_P4 ) AM_WRITE_LEGACY(mjvegasa_p4_w )
	1258	AM_RANGE( T90_P3, T90_P3 ) AM_READWRITE(mjtensin_p3_r, mjvegasa_p3_w )
	1259	AM_RANGE( T90_P4, T90_P4 ) AM_WRITE(mjvegasa_p4_w )
1241	1260	ADDRESS_MAP_END
1242	1261
1243	1262

src/mame/drivers/nmk16.c

r14845	r14846
3918	3918	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
3919	3919	MCFG_SCREEN_SIZE(256, 256)
3920	3920	MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 2*8, 30*8-1)
3921		MCFG_SCREEN_UPDATE_STATIC(tdragon)
	3921	MCFG_SCREEN_UPDATE_STATIC(macross)
3922	3922	MCFG_SCREEN_VBLANK_STATIC(nmk)
3923	3923
3924	3924	MCFG_GFXDECODE(macross)
r14845	r14846
4034	4034	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
4035	4035	MCFG_SCREEN_SIZE(256, 256)
4036	4036	MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 2*8, 30*8-1)
4037		MCFG_SCREEN_UPDATE_STATIC(hachamf)
	4037	MCFG_SCREEN_UPDATE_STATIC(macross)
4038	4038	MCFG_SCREEN_VBLANK_STATIC(nmk)
4039	4039
4040	4040	MCFG_GFXDECODE(macross)
r14845	r14846
4243	4243	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
4244	4244	MCFG_SCREEN_SIZE(512, 256)
4245	4245	MCFG_SCREEN_VISIBLE_AREA(0*8, 48*8-1, 2*8, 30*8-1)
4246		MCFG_SCREEN_UPDATE_STATIC(gunnail)
	4246	MCFG_SCREEN_UPDATE_STATIC(tdragon2)
4247	4247	MCFG_SCREEN_VBLANK_STATIC(nmk)
4248	4248
4249	4249	MCFG_GFXDECODE(macross2)
r14845	r14846
4284	4284	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
4285	4285	MCFG_SCREEN_SIZE(512, 256)
4286	4286	MCFG_SCREEN_VISIBLE_AREA(0*8, 48*8-1, 2*8, 30*8-1)
4287		MCFG_SCREEN_UPDATE_STATIC(gunnail)
	4287	MCFG_SCREEN_UPDATE_STATIC(tdragon2)
4288	4288	MCFG_SCREEN_VBLANK_STATIC(nmk)
4289	4289
4290	4290	MCFG_GFXDECODE(macross2)
r14845	r14846
7125	7125	***************************************************************************/
7126	7126
7127	7127
7128		GAME( 1989, tharrier, 0,        tharrier, tharrier, 0,        ROT270, "UPL (American Sammy license)", "Task Force Harrier", 0  )
7129		GAME( 1989, tharrierj,tharrier, tharrier, tharrier, 0,        ROT270, "UPL",                          "Task Force Harrier (Japan)", 0 )
	7128	GAME( 1989, tharrier, 0,        tharrier, tharrier, 0,        ROT270, "UPL (American Sammy license)", "Task Force Harrier", GAME_IMPERFECT_GRAPHICS )
	7129	GAME( 1989, tharrierj,tharrier, tharrier, tharrier, 0,        ROT270, "UPL",                          "Task Force Harrier (Japan)", GAME_IMPERFECT_GRAPHICS )
7130	7130
7131		GAME( 1990, mustang,  0,        mustang,  mustang,  0,        ROT0,   "UPL",                          "US AAF Mustang (25th May. 1990)", GAME_IMPERFECT_SOUND)
7132		GAME( 1990, mustangs, mustang,  mustang,  mustang,  0,        ROT0,   "UPL (Seoul Trading license)",  "US AAF Mustang (25th May. 1990 / Seoul Trading)", GAME_IMPERFECT_SOUND )
	7131	GAME( 1990, mustang,  0,        mustang,  mustang,  0,        ROT0,   "UPL",                          "US AAF Mustang (25th May. 1990)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
	7132	GAME( 1990, mustangs, mustang,  mustang,  mustang,  0,        ROT0,   "UPL (Seoul Trading license)",  "US AAF Mustang (25th May. 1990 / Seoul Trading)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
7133	7133
7134		GAME( 1990, bioship,  0,        bioship,  bioship,  0,        ROT0,   "UPL (American Sammy license)", "Bio-ship Paladin", GAME_IMPERFECT_SOUND )
7135		GAME( 1990, sbsgomo,  bioship,  bioship,  bioship,  0,        ROT0,   "UPL",                          "Space Battle Ship Gomorrah", GAME_IMPERFECT_SOUND )
	7134	GAME( 1990, bioship,  0,        bioship,  bioship,  0,        ROT0,   "UPL (American Sammy license)", "Bio-ship Paladin", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
	7135	GAME( 1990, sbsgomo,  bioship,  bioship,  bioship,  0,        ROT0,   "UPL",                          "Space Battle Ship Gomorrah", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
7136	7136
7137		GAME( 1990, vandyke,    0,       vandyke,  vandyke, 0,        ROT270, "UPL",                          "Vandyke (Japan)",  GAME_IMPERFECT_SOUND )
7138		GAME( 1990, vandykejal, vandyke, vandyke,  vandyke, 0,        ROT270, "UPL (Jaleco license)",         "Vandyke (Jaleco, set 1)",  GAME_IMPERFECT_SOUND )
7139		GAME( 1990, vandykejal2,vandyke, vandyke,  vandyke, 0,        ROT270, "UPL (Jaleco license)",         "Vandyke (Jaleco, set 2)",  GAME_IMPERFECT_SOUND )
7140		GAME( 1990, vandykeb,  vandyke, vandykeb, vandykeb, vandykeb, ROT270, "bootleg",                      "Vandyke (bootleg with PIC16c57)",  GAME_NO_SOUND )
	7137	GAME( 1990, vandyke,    0,       vandyke,  vandyke, 0,        ROT270, "UPL",                          "Vandyke (Japan)",  GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
	7138	GAME( 1990, vandykejal, vandyke, vandyke,  vandyke, 0,        ROT270, "UPL (Jaleco license)",         "Vandyke (Jaleco, set 1)",  GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
	7139	GAME( 1990, vandykejal2,vandyke, vandyke,  vandyke, 0,        ROT270, "UPL (Jaleco license)",         "Vandyke (Jaleco, set 2)",  GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
	7140	GAME( 1990, vandykeb,  vandyke, vandykeb, vandykeb, vandykeb, ROT270, "bootleg",                      "Vandyke (bootleg with PIC16c57)",  GAME_NO_SOUND | GAME_IMPERFECT_GRAPHICS )
7141	7141
7142		GAME( 1991, blkheart, 0,        blkheart,  blkheart, 0,       ROT0,   "UPL",                          "Black Heart", GAME_IMPERFECT_SOUND  )
7143		GAME( 1991, blkheartj,blkheart, blkheart,  blkheart, 0,       ROT0,   "UPL",                          "Black Heart (Japan)", GAME_IMPERFECT_SOUND )
	7142	GAME( 1991, blkheart, 0,        blkheart,  blkheart, 0,       ROT0,   "UPL",                          "Black Heart", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
	7143	GAME( 1991, blkheartj,blkheart, blkheart,  blkheart, 0,       ROT0,   "UPL",                          "Black Heart (Japan)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
7144	7144
7145		GAME( 1991, acrobatm, 0,        acrobatm, acrobatm, 0,        ROT270, "UPL (Taito license)",          "Acrobat Mission", GAME_IMPERFECT_SOUND )
	7145	GAME( 1991, acrobatm, 0,        acrobatm, acrobatm, 0,        ROT270, "UPL (Taito license)",          "Acrobat Mission", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
7146	7146
7147		GAME( 1992, strahl,   0,        strahl,   strahl,   0,        ROT0,   "UPL",                          "Koutetsu Yousai Strahl (Japan set 1)", GAME_IMPERFECT_SOUND )
7148		GAME( 1992, strahla,  strahl,   strahl,   strahl,   0,        ROT0,   "UPL",                          "Koutetsu Yousai Strahl (Japan set 2)", GAME_IMPERFECT_SOUND )
	7147	GAME( 1992, strahl,   0,        strahl,   strahl,   0,        ROT0,   "UPL",                          "Koutetsu Yousai Strahl (Japan set 1)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
	7148	GAME( 1992, strahla,  strahl,   strahl,   strahl,   0,        ROT0,   "UPL",                          "Koutetsu Yousai Strahl (Japan set 2)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
7149	7149
7150		GAME( 1991, tdragon,  0,        tdragon,  tdragon,  tdragon,  ROT270, "NMK (Tecmo license)",          "Thunder Dragon (9th Jan. 1992)", GAME_IMPERFECT_SOUND )
7151		GAME( 1991, tdragon1, tdragon,  tdragon,  tdragon,  tdragon,  ROT270, "NMK (Tecmo license)",          "Thunder Dragon (4th Jun. 1991)", GAME_IMPERFECT_SOUND )
	7150	GAME( 1991, tdragon,  0,        tdragon,  tdragon,  tdragon,  ROT270, "NMK (Tecmo license)",          "Thunder Dragon (9th Jan. 1992)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
	7151	GAME( 1991, tdragon1, tdragon,  tdragon,  tdragon,  tdragon,  ROT270, "NMK (Tecmo license)",          "Thunder Dragon (4th Jun. 1991)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
7152	7152
7153	7153	GAME( 1991, hachamf,  0,        hachamf,  hachamf,  hachamf,  ROT0,   "NMK",                          "Hacha Mecha Fighter (19th Sep. 1991)", GAME_UNEMULATED_PROTECTION | GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND )
7154		GAME( 1992, macross,  0,        macross,  macross,  nmk,      ROT270, "Banpresto",                    "Super Spacefortress Macross / Chou-Jikuu Yousai Macross", GAME_IMPERFECT_SOUND )
7155		GAME( 1993, gunnail,  0,        gunnail,  gunnail,  nmk,      ROT270, "NMK / Tecmo",                  "GunNail (28th May. 1992)", GAME_IMPERFECT_SOUND )
7156		GAME( 1993, macross2, 0,        macross2, macross2, 0,        ROT0,   "Banpresto",                    "Super Spacefortress Macross II / Chou-Jikuu Yousai Macross II", GAME_NO_COCKTAIL )
	7154	GAME( 1992, macross,  0,        macross,  macross,  nmk,      ROT270, "Banpresto",                    "Super Spacefortress Macross / Chou-Jikuu Yousai Macross", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
	7155	GAME( 1993, gunnail,  0,        gunnail,  gunnail,  nmk,      ROT270, "NMK / Tecmo",                  "GunNail (28th May. 1992)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS )
	7156	GAME( 1993, macross2, 0,        macross2, macross2, 0,        ROT0,   "Banpresto",                    "Super Spacefortress Macross II / Chou-Jikuu Yousai Macross II", GAME_NO_COCKTAIL | GAME_IMPERFECT_GRAPHICS )
7157	7157
7158		GAME( 1993, tdragon2, 0,        tdragon2, tdragon2, 0,        ROT270, "NMK",                          "Thunder Dragon 2 (9th Nov. 1993)", GAME_NO_COCKTAIL )
7159		GAME( 1993, tdragon2a,tdragon2, tdragon2, tdragon2, 0,        ROT270, "NMK",                          "Thunder Dragon 2 (1st Oct. 1993)", GAME_NO_COCKTAIL )
7160		GAME( 1993, bigbang,  tdragon2, tdragon2, tdragon2, 0,        ROT270, "NMK",                          "Big Bang (9th Nov. 1993)", GAME_NO_COCKTAIL )
	7158	GAME( 1993, tdragon2, 0,        tdragon2, tdragon2, 0,        ROT270, "NMK",                          "Thunder Dragon 2 (9th Nov. 1993)", GAME_NO_COCKTAIL | GAME_IMPERFECT_GRAPHICS )
	7159	GAME( 1993, tdragon2a,tdragon2, tdragon2, tdragon2, 0,        ROT270, "NMK",                          "Thunder Dragon 2 (1st Oct. 1993)", GAME_NO_COCKTAIL | GAME_IMPERFECT_GRAPHICS )
	7160	GAME( 1993, bigbang,  tdragon2, tdragon2, tdragon2, 0,        ROT270, "NMK",                          "Big Bang (9th Nov. 1993)", GAME_NO_COCKTAIL | GAME_IMPERFECT_GRAPHICS )
7161	7161
7162		GAME( 1994, raphero,  0,        raphero,  raphero,  0,        ROT270, "NMK / Media Shoji",            "Rapid Hero", GAME_IMPERFECT_SOUND ) // 23rd July 1993 in test mode, (c)1994 on title screen
	7162	GAME( 1994, raphero,  0,        raphero,  raphero,  0,        ROT270, "NMK / Media Shoji",            "Rapid Hero", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS ) // 23rd July 1993 in test mode, (c)1994 on title screen
7163	7163
7164	7164	/* both sets of both these games show a date of 9th Mar 1992 in the test mode, they look like different revisions so I doubt this is accurate */
7165	7165	GAME( 1992, sabotenb, 0,        bjtwin,   sabotenb, nmk,      ROT0,   "NMK / Tecmo",                  "Saboten Bombers (set 1)", GAME_NO_COCKTAIL )

src/mame/drivers/miniboy7.c

r14845	r14846
161	161	UINT8 *m_videoram;
162	162	UINT8 *m_colorram;
163	163	tilemap_t *m_bg_tilemap;
	164	DECLARE_WRITE8_MEMBER(miniboy7_videoram_w);
	165	DECLARE_WRITE8_MEMBER(miniboy7_colorram_w);
164	166	};
165	167
166	168
r14845	r14846
168	170	*          Video Hardware          *
169	171	***********************************/
170	172
171		static WRITE8_HANDLER( miniboy7_videoram_w )
	173	WRITE8_MEMBER(miniboy7_state::miniboy7_videoram_w)
172	174	{
173		miniboy7_state *state = space->machine().driver_data<miniboy7_state>();
174		state->m_videoram[offset] = data;
175		state->m_bg_tilemap->mark_tile_dirty(offset);
	175	m_videoram[offset] = data;
	176	m_bg_tilemap->mark_tile_dirty(offset);
176	177	}
177	178
178		static WRITE8_HANDLER( miniboy7_colorram_w )
	179	WRITE8_MEMBER(miniboy7_state::miniboy7_colorram_w)
179	180	{
180		miniboy7_state *state = space->machine().driver_data<miniboy7_state>();
181		state->m_colorram[offset] = data;
182		state->m_bg_tilemap->mark_tile_dirty(offset);
	181	m_colorram[offset] = data;
	182	m_bg_tilemap->mark_tile_dirty(offset);
183	183	}
184	184
185	185	static TILE_GET_INFO( get_bg_tile_info )
r14845	r14846
268	268
269	269	static ADDRESS_MAP_START( miniboy7_map, AS_PROGRAM, 8, miniboy7_state )
270	270	AM_RANGE(0x0000, 0x07ff) AM_RAM   AM_SHARE("nvram") /* battery backed RAM? */
271		AM_RANGE(0x0800, 0x0fff) AM_RAM_WRITE_LEGACY(miniboy7_videoram_w) AM_BASE(m_videoram)
272		AM_RANGE(0x1000, 0x17ff) AM_RAM_WRITE_LEGACY(miniboy7_colorram_w) AM_BASE(m_colorram)
	271	AM_RANGE(0x0800, 0x0fff) AM_RAM_WRITE(miniboy7_videoram_w) AM_BASE(m_videoram)
	272	AM_RANGE(0x1000, 0x17ff) AM_RAM_WRITE(miniboy7_colorram_w) AM_BASE(m_colorram)
273	273	AM_RANGE(0x1800, 0x25ff) AM_RAM   /* looks like videoram */
274	274	AM_RANGE(0x2600, 0x27ff) AM_RAM
275	275	AM_RANGE(0x2800, 0x2800) AM_DEVWRITE("crtc", mc6845_device, address_w)

src/emu/sound/ymf271.c

r14845	r14846
1452	1452	{
1453	1453	chip->timerA |= (data & 0xff)<<8;
1454	1454	}
1455		else
1456		chip->timerA |= 0x200;
1457	1455	}
1458	1456	break;
1459	1457
r14845	r14846
1484	1482	{   // timer A reset
1485	1483	chip->irqstate &= ~1;
1486	1484	chip->status &= ~1;
	1485	chip->timerAVal |= 0x300;
1487	1486
1488	1487	if (chip->irq_callback) chip->irq_callback(chip->device, 0);
1489	1488
1490		//period = (double)(256.0 - chip->timerAVal ) * ( 384.0 * 4.0 / (double)CLOCK);
1491		period = attotime::from_hz(chip->clock) * (384 * (1024 - chip->timerAVal));
	1489	period = attotime::from_hz(chip->clock) * (384 * 4 * (1024 - chip->timerAVal));
1492	1490
1493	1491	chip->timA->adjust(period, 0, period);
1494	1492	}

src/emu/machine/i8155.c

r14845	r14846
1	1	/**********************************************************************
2	2
3		Intel 8155 - 2048-Bit Static MOS RAM with I/O Ports and Timer emulation
	3	Intel 8155/8156 - 2048-Bit Static MOS RAM with I/O Ports and Timer emulation
4	4
5	5	Copyright MESS Team.
6	6	Visit http://mamedev.org for licensing and usage restrictions.
r14845	r14846
19	19	#include "i8155.h"
20	20
21	21
22		// device type definition
	22	// device type definitions
23	23	const device_type I8155 = &device_creator<i8155_device>;
	24	const device_type I8156 = &device_creator<i8155_device>;
24	25
25	26
26	27	//**************************************************************************

src/emu/machine/i8155.h

r14845	r14846
1	1	/**********************************************************************
2	2
3		Intel 8155 - 2048-Bit Static MOS RAM with I/O Ports and Timer emulation
	3	Intel 8155/8156 - 2048-Bit Static MOS RAM with I/O Ports and Timer emulation
	4	8156 is the same as 8155, except that chip enable is active high instead of low
4	5
5	6	Copyright MESS Team.
6	7	Visit http://mamedev.org for licensing and usage restrictions.
r14845	r14846
54	55	MCFG_DEVICE_ADD((_tag), I8155, _clock)   \
55	56	MCFG_DEVICE_CONFIG(_config)
56	57
	58
	59	#define MCFG_I8156_ADD(_tag, _clock, _config) \
	60	MCFG_DEVICE_ADD((_tag), I8156, _clock)   \
	61	MCFG_DEVICE_CONFIG(_config)
	62
	63
57	64	#define I8155_INTERFACE(name) \
58	65	const i8155_interface (name) =
59	66
60	67
	68	#define I8156_INTERFACE(name) \
	69	const i8155_interface (name) =
61	70
	71
	72
62	73	//**************************************************************************
63	74	//  TYPE DEFINITIONS
64	75	//**************************************************************************
r14845	r14846
148	159
149	160	// device type definition
150	161	extern const device_type I8155;
	162	extern const device_type I8156;
151	163
152	164
153	165

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