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r14845 Tuesday 3rd April, 2012 at 11:21:16 UTC by Miodrag Milanović
MESS going modern (no whatsnew)

[src/mess/drivers]

a310.c atm.c dectalk.c ex800.c fp6000.c ip20.c jr100.c jr200.c juicebox.c mmodular.c multi8.c mz2000.c mz2500.c osbexec.c paso1600.c pc6001.c pc8801.c pc88va.c pc9801.c pk8000.c pockstat.c px4.c pyl601.c rt1715.c rvoice.c sgi_ip2.c sgi_ip6.c smc777.c socrates.c spc1000.c ti990_4.c ti99_2.c tvc.c vtech1.c

src/mess/drivers/dectalk.c

r14844	r14845
179	179	UINT8 m_hack_self_test; // temp variable for hack below
180	180
181	181	required_device<generic_terminal_device> m_terminal;
	182	DECLARE_READ8_MEMBER(nvram_read);
	183	DECLARE_WRITE8_MEMBER(led_write);
	184	DECLARE_WRITE8_MEMBER(nvram_write);
	185	DECLARE_WRITE16_MEMBER(m68k_infifo_w);
	186	DECLARE_READ16_MEMBER(m68k_spcflags_r);
	187	DECLARE_WRITE16_MEMBER(m68k_spcflags_w);
	188	DECLARE_READ16_MEMBER(m68k_tlcflags_r);
	189	DECLARE_WRITE16_MEMBER(m68k_tlcflags_w);
	190	DECLARE_READ16_MEMBER(m68k_tlc_dtmf_r);
	191	DECLARE_WRITE16_MEMBER(spc_latch_outfifo_error_stats);
	192	DECLARE_READ16_MEMBER(spc_infifo_data_r);
	193	DECLARE_WRITE16_MEMBER(spc_outfifo_data_w);
	194	DECLARE_READ16_MEMBER(spc_semaphore_r);
182	195	};
183	196
184	197
r14844	r14845
337	350	}
338	351
339	352	/* Begin 68k i/o handlers */
340		static READ8_HANDLER( nvram_read ) // read from x2212 nvram chip and possibly do recall
	353	READ8_MEMBER(dectalk_state::nvram_read)// read from x2212 nvram chip and possibly do recall
341	354	{
342		dectalk_state *state = space->machine().driver_data<dectalk_state>();
343	355	UINT8 data = 0xFF;
344		data = state->m_x2214_sram[offset&0xff]; // TODO: should this be before or after a possible /RECALL? I'm guessing before.
	356	data = m_x2214_sram[offset&0xff]; // TODO: should this be before or after a possible /RECALL? I'm guessing before.
345	357	#ifdef NVRAM_LOG
346	358	logerror("m68k: nvram read at %08X: %02X\n", offset, data);
347	359	#endif
348	360	if (offset&0x200) // if a9 is set, do a /RECALL
349		dectalk_x2212_recall(space->machine());
	361	dectalk_x2212_recall(machine());
350	362	return data;
351	363	}
352	364
353		static WRITE8_HANDLER( led_write )
	365	WRITE8_MEMBER(dectalk_state::led_write)
354	366	{
355		dectalk_state *state = space->machine().driver_data<dectalk_state>();
356		state->m_statusLED = data&0xFF;
	367	m_statusLED = data&0xFF;
357	368	popmessage("LED status: %02X\n", data&0xFF);
358	369	#ifdef VERBOSE
359	370	logerror("m68k: LED status: %02X\n", data&0xFF);
r14844	r14845
361	372	//popmessage("LED status: %x %x %x %x %x %x %x %x\n", data&0x80, data&0x40, data&0x20, data&0x10, data&0x8, data&0x4, data&0x2, data&0x1);
362	373	}
363	374
364		static WRITE8_HANDLER( nvram_write ) // write to X2212 NVRAM chip and possibly do store
	375	WRITE8_MEMBER(dectalk_state::nvram_write)// write to X2212 NVRAM chip and possibly do store
365	376	{
366		dectalk_state *state = space->machine().driver_data<dectalk_state>();
367	377	#ifdef NVRAM_LOG
368	378	logerror("m68k: nvram write at %08X: %02X\n", offset, data&0x0f);
369	379	#endif
370		state->m_x2214_sram[offset&0xff] = (UINT8)data&0x0f; // TODO: should this be before or after a possible /STORE? I'm guessing before.
	380	m_x2214_sram[offset&0xff] = (UINT8)data&0x0f; // TODO: should this be before or after a possible /STORE? I'm guessing before.
371	381	if (offset&0x200) // if a9 is set, do a /STORE
372		dectalk_x2212_store(space->machine());
	382	dectalk_x2212_store(machine());
373	383	}
374	384
375		static WRITE16_HANDLER( m68k_infifo_w ) // 68k write to the speech input fifo
	385	WRITE16_MEMBER(dectalk_state::m68k_infifo_w)// 68k write to the speech input fifo
376	386	{
377		dectalk_state *state = space->machine().driver_data<dectalk_state>();
378	387	#ifdef USE_LOOSE_TIMING
379		space->machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(25));
	388	machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(25));
380	389	#endif
381	390	#ifdef SPC_LOG_68K
382		logerror("m68k: SPC infifo written with data = %04X, fifo head was: %02X; fifo tail: %02X\n",data, state->m_infifo_head_ptr, state->m_infifo_tail_ptr);
	391	logerror("m68k: SPC infifo written with data = %04X, fifo head was: %02X; fifo tail: %02X\n",data, m_infifo_head_ptr, m_infifo_tail_ptr);
383	392	#endif
384	393	// if fifo is full (head ptr = tail ptr-1), do not increment the head ptr and do not store the data
385		if (((state->m_infifo_tail_ptr-1)&0x1F) == state->m_infifo_head_ptr)
	394	if (((m_infifo_tail_ptr-1)&0x1F) == m_infifo_head_ptr)
386	395	{
387	396	#ifdef SPC_LOG_68K
388	397	logerror("infifo was full, write ignored!\n");
389	398	#endif
390	399	return;
391	400	}
392		state->m_infifo[state->m_infifo_head_ptr] = data;
393		state->m_infifo_head_ptr++;
394		state->m_infifo_head_ptr&=0x1F;
	401	m_infifo[m_infifo_head_ptr] = data;
	402	m_infifo_head_ptr++;
	403	m_infifo_head_ptr&=0x1F;
395	404	}
396	405
397		static READ16_HANDLER( m68k_spcflags_r ) // 68k read from the speech flags
	406	READ16_MEMBER(dectalk_state::m68k_spcflags_r)// 68k read from the speech flags
398	407	{
399		dectalk_state *state = space->machine().driver_data<dectalk_state>();
400	408	UINT8 data = 0;
401		data |= state->m_m68k_spcflags_latch; // bits 0 and 6
402		data |= state->m_spc_error_latch<<5; // bit 5
403		data |= state->m_infifo_semaphore<<7; // bit 7
	409	data |= m_m68k_spcflags_latch; // bits 0 and 6
	410	data |= m_spc_error_latch<<5; // bit 5
	411	data |= m_infifo_semaphore<<7; // bit 7
404	412	#ifdef SPC_LOG_68K
405	413	logerror("m68k: SPC flags read, returning data = %04X\n",data);
406	414	#endif
407	415	return data;
408	416	}
409	417
410		static WRITE16_HANDLER( m68k_spcflags_w ) // 68k write to the speech flags (only 3 bits do anything)
	418	WRITE16_MEMBER(dectalk_state::m68k_spcflags_w)// 68k write to the speech flags (only 3 bits do anything)
411	419	{
412		dectalk_state *state = space->machine().driver_data<dectalk_state>();
413	420	#ifdef USE_LOOSE_TIMING
414		space->machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(25));
	421	machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(25));
415	422	#endif
416	423	#ifdef SPC_LOG_68K
417	424	logerror("m68k: SPC flags written with %04X, only storing %04X\n",data, data&0x41);
418	425	#endif
419		state->m_m68k_spcflags_latch = data&0x41; // ONLY store bits 6 and 0!
	426	m_m68k_spcflags_latch = data&0x41; // ONLY store bits 6 and 0!
420	427	// d0: initialize speech flag (reset tms32010 and clear infifo and outfifo if high)
421	428	if ((data&0x1) == 0x1) // bit 0
422	429	{
423	430	#ifdef SPC_LOG_68K
424	431	logerror(" | 0x01: initialize speech: fifos reset, clear error+semaphore latches and dsp reset\n");
425	432	#endif
426		dectalk_clear_all_fifos(space->machine());
427		cputag_set_input_line(space->machine(), "dsp", INPUT_LINE_RESET, ASSERT_LINE); // speech reset forces the CLR line active on the tms32010
	433	dectalk_clear_all_fifos(machine());
	434	cputag_set_input_line(machine(), "dsp", INPUT_LINE_RESET, ASSERT_LINE); // speech reset forces the CLR line active on the tms32010
428	435	// clear the two speech side latches
429		state->m_spc_error_latch = 0;
430		dectalk_semaphore_w(space->machine(), 0);
	436	m_spc_error_latch = 0;
	437	dectalk_semaphore_w(machine(), 0);
431	438	}
432	439	else // (data&0x1) == 0
433	440	{
434	441	#ifdef SPC_LOG_68K
435	442	logerror(" | 0x01 = 0: initialize speech off, dsp running\n");
436	443	#endif
437		cputag_set_input_line(space->machine(), "dsp", INPUT_LINE_RESET, CLEAR_LINE); // speech reset deassert clears the CLR line on the tms32010
	444	cputag_set_input_line(machine(), "dsp", INPUT_LINE_RESET, CLEAR_LINE); // speech reset deassert clears the CLR line on the tms32010
438	445	}
439	446	if ((data&0x2) == 0x2) // bit 1 - clear error and semaphore latches
440	447	{
r14844	r14845
442	449	logerror(" | 0x02: clear error+semaphore latches\n");
443	450	#endif
444	451	// clear the two speech side latches
445		state->m_spc_error_latch = 0;
446		dectalk_semaphore_w(space->machine(), 0);
	452	m_spc_error_latch = 0;
	453	dectalk_semaphore_w(machine(), 0);
447	454	}
448	455	if ((data&0x40) == 0x40) // bit 6 - spc irq enable
449	456	{
450	457	#ifdef SPC_LOG_68K
451	458	logerror(" | 0x40: speech int enabled\n");
452	459	#endif
453		if (state->m_infifo_semaphore == 1)
	460	if (m_infifo_semaphore == 1)
454	461	{
455	462	#ifdef SPC_LOG_68K
456	463	logerror("    speech int fired!\n");
457	464	#endif
458		cputag_set_input_line_and_vector(space->machine(), "maincpu", M68K_IRQ_5, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR); // set int because semaphore was set
	465	cputag_set_input_line_and_vector(machine(), "maincpu", M68K_IRQ_5, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR); // set int because semaphore was set
459	466	}
460	467	}
461	468	else // data&0x40 == 0
r14844	r14845
463	470	#ifdef SPC_LOG_68K
464	471	logerror(" | 0x40 = 0: speech int disabled\n");
465	472	#endif
466		cputag_set_input_line_and_vector(space->machine(), "maincpu", M68K_IRQ_5, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR); // clear int because int is now disabled
	473	cputag_set_input_line_and_vector(machine(), "maincpu", M68K_IRQ_5, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR); // clear int because int is now disabled
467	474	}
468	475	}
469	476
470		static READ16_HANDLER( m68k_tlcflags_r ) // dtmf flags read
	477	READ16_MEMBER(dectalk_state::m68k_tlcflags_r)// dtmf flags read
471	478	{
472		dectalk_state *state = space->machine().driver_data<dectalk_state>();
473	479	UINT16 data = 0;
474		data |= state->m_m68k_tlcflags_latch; // bits 6, 8, 14;
475		data |= state->m_tlc_tonedetect<<7; // bit 7 is tone detect
476		data |= state->m_tlc_ringdetect<<14; // bit 15 is ring detect
	480	data |= m_m68k_tlcflags_latch; // bits 6, 8, 14;
	481	data |= m_tlc_tonedetect<<7; // bit 7 is tone detect
	482	data |= m_tlc_ringdetect<<14; // bit 15 is ring detect
477	483	#ifdef TLC_LOG
478	484	logerror("m68k: TLC flags read, returning data = %04X\n",data);
479	485	#endif
480	486	return data;
481	487	}
482	488
483		static WRITE16_HANDLER( m68k_tlcflags_w ) // dtmf flags write
	489	WRITE16_MEMBER(dectalk_state::m68k_tlcflags_w)// dtmf flags write
484	490	{
485		dectalk_state *state = space->machine().driver_data<dectalk_state>();
486	491	#ifdef TLC_LOG
487	492	logerror("m68k: TLC flags written with %04X, only storing %04X\n",data, data&0x4140);
488	493	#endif
489		state->m_m68k_tlcflags_latch = data&0x4140; // ONLY store bits 6 8 and 14!
	494	m_m68k_tlcflags_latch = data&0x4140; // ONLY store bits 6 8 and 14!
490	495	if ((data&0x40) == 0x40) // bit 6: tone detect interrupt enable
491	496	{
492	497	#ifdef TLC_LOG
493	498	logerror(" | 0x40: tone detect int enabled\n");
494	499	#endif
495		if (state->m_tlc_tonedetect == 1)
	500	if (m_tlc_tonedetect == 1)
496	501	{
497	502	#ifdef TLC_LOG
498	503	logerror("    TLC int fired!\n");
499	504	#endif
500		cputag_set_input_line_and_vector(space->machine(), "maincpu", M68K_IRQ_4, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR); // set int because tone detect was set
	505	cputag_set_input_line_and_vector(machine(), "maincpu", M68K_IRQ_4, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR); // set int because tone detect was set
501	506	}
502	507	}
503	508	else // data&0x40 == 0
r14844	r14845
505	510	#ifdef TLC_LOG
506	511	logerror(" | 0x40 = 0: tone detect int disabled\n");
507	512	#endif
508		if (((data&0x4000)!=0x4000) || (state->m_tlc_ringdetect == 0)) // check to be sure we don't disable int if both ints fired at once
509		cputag_set_input_line_and_vector(space->machine(), "maincpu", M68K_IRQ_4, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR); // clear int because int is now disabled
	513	if (((data&0x4000)!=0x4000) || (m_tlc_ringdetect == 0)) // check to be sure we don't disable int if both ints fired at once
	514	cputag_set_input_line_and_vector(machine(), "maincpu", M68K_IRQ_4, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR); // clear int because int is now disabled
510	515	}
511	516	if ((data&0x100) == 0x100) // bit 8: answer phone relay enable
512	517	{
r14844	r14845
525	530	#ifdef TLC_LOG
526	531	logerror(" | 0x4000: ring detect int enabled\n");
527	532	#endif
528		if (state->m_tlc_ringdetect == 1)
	533	if (m_tlc_ringdetect == 1)
529	534	{
530	535	#ifdef TLC_LOG
531	536	logerror("    TLC int fired!\n");
532	537	#endif
533		cputag_set_input_line_and_vector(space->machine(), "maincpu", M68K_IRQ_4, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR); // set int because tone detect was set
	538	cputag_set_input_line_and_vector(machine(), "maincpu", M68K_IRQ_4, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR); // set int because tone detect was set
534	539	}
535	540	}
536	541	else // data&0x4000 == 0
r14844	r14845
538	543	#ifdef TLC_LOG
539	544	logerror(" | 0x4000 = 0: ring detect int disabled\n");
540	545	#endif
541		if (((data&0x40)!=0x40) || (state->m_tlc_tonedetect == 0)) // check to be sure we don't disable int if both ints fired at once
542		cputag_set_input_line_and_vector(space->machine(), "maincpu", M68K_IRQ_4, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR); // clear int because int is now disabled
	546	if (((data&0x40)!=0x40) || (m_tlc_tonedetect == 0)) // check to be sure we don't disable int if both ints fired at once
	547	cputag_set_input_line_and_vector(machine(), "maincpu", M68K_IRQ_4, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR); // clear int because int is now disabled
543	548	}
544	549	}
545	550
546		static READ16_HANDLER( m68k_tlc_dtmf_r ) // dtmf chip read
	551	READ16_MEMBER(dectalk_state::m68k_tlc_dtmf_r)// dtmf chip read
547	552	{
548	553	#ifdef TLC_LOG
549		dectalk_state *state = space->machine().driver_data<dectalk_state>();
550	554	UINT16 data = 0xFFFF;
551		data = state->m_tlc_dtmf&0xF;
	555	data = m_tlc_dtmf&0xF;
552	556	logerror("m68k: TLC dtmf detector read, returning data = %02X", data);
553	557	#endif
554	558	return 0;
r14844	r14845
556	560	/* End 68k i/o handlers */
557	561
558	562	/* Begin tms32010 i/o handlers */
559		static WRITE16_HANDLER( spc_latch_outfifo_error_stats ) // latch 74ls74 @ E64 upper and lower halves with d0 and 1 respectively
	563	WRITE16_MEMBER(dectalk_state::spc_latch_outfifo_error_stats)// latch 74ls74 @ E64 upper and lower halves with d0 and 1 respectively
560	564	{
561		dectalk_state *state = space->machine().driver_data<dectalk_state>();
562	565	#ifdef USE_LOOSE_TIMING
563		space->machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(25));
	566	machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(25));
564	567	#endif
565	568	#ifdef SPC_LOG_DSP
566	569	logerror("dsp: set fifo semaphore and set error status = %01X\n",data&1);
567	570	#endif
568		dectalk_semaphore_w(space->machine(), (~state->m_simulate_outfifo_error)&1); // always set to 1 here, unless outfifo error.
569		state->m_spc_error_latch = (data&1);
	571	dectalk_semaphore_w(machine(), (~m_simulate_outfifo_error)&1); // always set to 1 here, unless outfifo error.
	572	m_spc_error_latch = (data&1);
570	573	}
571	574
572		static READ16_HANDLER( spc_infifo_data_r )
	575	READ16_MEMBER(dectalk_state::spc_infifo_data_r)
573	576	{
574		dectalk_state *state = space->machine().driver_data<dectalk_state>();
575	577	UINT16 data = 0xFFFF;
576		data = state->m_infifo[state->m_infifo_tail_ptr];
	578	data = m_infifo[m_infifo_tail_ptr];
577	579	#ifdef SPC_LOG_DSP
578		logerror("dsp: SPC infifo read with data = %04X, fifo head: %02X; fifo tail was: %02X\n",data, state->m_infifo_head_ptr, state->m_infifo_tail_ptr);
	580	logerror("dsp: SPC infifo read with data = %04X, fifo head: %02X; fifo tail was: %02X\n",data, m_infifo_head_ptr, m_infifo_tail_ptr);
579	581	#endif
580	582	// if fifo is empty (tail ptr == head ptr), do not increment the tail ptr, otherwise do.
581		if (state->m_infifo_tail_ptr != state->m_infifo_head_ptr) state->m_infifo_tail_ptr++; // technically correct but doesn't match sn74ls224 sheet
582		//if (((state->m_infifo_head_ptr-1)&0x1F) != state->m_infifo_tail_ptr) state->m_infifo_tail_ptr++; // matches sn74ls224 sheet
583		state->m_infifo_tail_ptr&=0x1F;
	583	if (m_infifo_tail_ptr != m_infifo_head_ptr) m_infifo_tail_ptr++; // technically correct but doesn't match sn74ls224 sheet
	584	//if (((m_infifo_head_ptr-1)&0x1F) != m_infifo_tail_ptr) m_infifo_tail_ptr++; // matches sn74ls224 sheet
	585	m_infifo_tail_ptr&=0x1F;
584	586	return data;
585	587	}
586	588
587		static WRITE16_HANDLER( spc_outfifo_data_w )
	589	WRITE16_MEMBER(dectalk_state::spc_outfifo_data_w)
588	590	{
589		dectalk_state *state = space->machine().driver_data<dectalk_state>();
590	591	// the low 4 data bits are thrown out on the real unit due to use of a 12 bit dac (and to save use of another 16x4 fifo chip), though technically they're probably valid, and with suitable hacking a dtc-01 could probably output full 16 bit samples at 10khz.
591	592	#ifdef SPC_LOG_DSP
592		logerror("dsp: SPC outfifo write, data = %04X, fifo head was: %02X; fifo tail: %02X\n", data, state->m_outfifo_head_ptr, state->m_outfifo_tail_ptr);
	593	logerror("dsp: SPC outfifo write, data = %04X, fifo head was: %02X; fifo tail: %02X\n", data, m_outfifo_head_ptr, m_outfifo_tail_ptr);
593	594	#endif
594		cputag_set_input_line(space->machine(), "dsp", 0, CLEAR_LINE); //TMS32010 INT (cleared because LDCK inverts the IR line, clearing int on any outfifo write... for a moment at least.)
	595	cputag_set_input_line(machine(), "dsp", 0, CLEAR_LINE); //TMS32010 INT (cleared because LDCK inverts the IR line, clearing int on any outfifo write... for a moment at least.)
595	596	// if fifo is full (head ptr = tail ptr-1), do not increment the head ptr and do not store the data
596		if (((state->m_outfifo_tail_ptr-1)&0xF) == state->m_outfifo_head_ptr)
	597	if (((m_outfifo_tail_ptr-1)&0xF) == m_outfifo_head_ptr)
597	598	{
598	599	#ifdef SPC_LOG_DSP
599	600	logerror("outfifo was full, write ignored!\n");
600	601	#endif
601	602	return;
602	603	}
603		state->m_outfifo[state->m_outfifo_head_ptr] = data;
604		state->m_outfifo_head_ptr++;
605		state->m_outfifo_head_ptr&=0xF;
606		//dectalk_outfifo_check(space->machine()); // commented to allow int to clear
	604	m_outfifo[m_outfifo_head_ptr] = data;
	605	m_outfifo_head_ptr++;
	606	m_outfifo_head_ptr&=0xF;
	607	//dectalk_outfifo_check(machine()); // commented to allow int to clear
607	608	}
608	609
609		static READ16_HANDLER( spc_semaphore_r ) // Return state of d-latch 74ls74 @ E64 'lower half' in d0 which indicates whether infifo is readable
	610	READ16_MEMBER(dectalk_state::spc_semaphore_r)// Return state of d-latch 74ls74 @ E64 'lower half' in d0 which indicates whether infifo is readable
610	611	{
611		dectalk_state *state = space->machine().driver_data<dectalk_state>();
612	612	#ifdef SPC_LOG_DSP
613		//logerror("dsp: read infifo semaphore, returned %d\n", state->m_infifo_semaphore); // commented due to extreme annoyance factor
614		if (!state->m_infifo_semaphore) logerror("dsp: read infifo semaphore, returned %d\n", state->m_infifo_semaphore);
	613	//logerror("dsp: read infifo semaphore, returned %d\n", m_infifo_semaphore); // commented due to extreme annoyance factor
	614	if (!m_infifo_semaphore) logerror("dsp: read infifo semaphore, returned %d\n", m_infifo_semaphore);
615	615	#endif
616		return state->m_infifo_semaphore;
	616	return m_infifo_semaphore;
617	617	}
618	618	/* end tms32010 i/o handlers */
619	619
r14844	r14845
644	644	AM_RANGE(0x000000, 0x03ffff) AM_ROM AM_MIRROR(0x740000) /* ROM */
645	645	AM_RANGE(0x080000, 0x093fff) AM_RAM AM_MIRROR(0x760000) /* RAM */
646	646	//AM_RANGE(0x094000, 0x0943ff) AM_READWRITE_LEGACY(led_sw_nvr_read, led_sw_nv_write) AM_MIRROR(0x763C00) /* LED array and Xicor X2212 NVRAM */
647		AM_RANGE(0x094000, 0x0943ff) AM_WRITE8_LEGACY(led_write, 0x00FF) AM_MIRROR(0x763C00) /* LED array */
648		AM_RANGE(0x094000, 0x0943ff) AM_READWRITE8_LEGACY(nvram_read, nvram_write, 0xFF00) AM_MIRROR(0x763C00) /* Xicor X2212 NVRAM */
	647	AM_RANGE(0x094000, 0x0943ff) AM_WRITE8(led_write, 0x00FF) AM_MIRROR(0x763C00) /* LED array */
	648	AM_RANGE(0x094000, 0x0943ff) AM_READWRITE8(nvram_read, nvram_write, 0xFF00) AM_MIRROR(0x763C00) /* Xicor X2212 NVRAM */
649	649	AM_RANGE(0x098000, 0x09801f) AM_DEVREADWRITE8_LEGACY("duart68681", duart68681_r, duart68681_w, 0xff) AM_MIRROR(0x763FE0) /* DUART */
650		AM_RANGE(0x09C000, 0x09C001) AM_READWRITE_LEGACY(m68k_spcflags_r, m68k_spcflags_w) AM_MIRROR(0x763FF8) /* SPC flags reg */
651		AM_RANGE(0x09C002, 0x09C003) AM_WRITE_LEGACY(m68k_infifo_w) AM_MIRROR(0x763FF8) /* SPC fifo reg */
652		AM_RANGE(0x09C004, 0x09C005) AM_READWRITE_LEGACY(m68k_tlcflags_r, m68k_tlcflags_w) AM_MIRROR(0x763FF8) /* telephone status flags */
653		AM_RANGE(0x09C006, 0x09C007) AM_READ_LEGACY(m68k_tlc_dtmf_r) AM_MIRROR(0x763FF8) /* telephone dtmf read */
	650	AM_RANGE(0x09C000, 0x09C001) AM_READWRITE(m68k_spcflags_r, m68k_spcflags_w) AM_MIRROR(0x763FF8) /* SPC flags reg */
	651	AM_RANGE(0x09C002, 0x09C003) AM_WRITE(m68k_infifo_w) AM_MIRROR(0x763FF8) /* SPC fifo reg */
	652	AM_RANGE(0x09C004, 0x09C005) AM_READWRITE(m68k_tlcflags_r, m68k_tlcflags_w) AM_MIRROR(0x763FF8) /* telephone status flags */
	653	AM_RANGE(0x09C006, 0x09C007) AM_READ(m68k_tlc_dtmf_r) AM_MIRROR(0x763FF8) /* telephone dtmf read */
654	654	ADDRESS_MAP_END
655	655
656	656	// do we even need this below?
r14844	r14845
663	663	ADDRESS_MAP_END
664	664
665	665	static ADDRESS_MAP_START(tms32010_io, AS_IO, 16, dectalk_state )
666		AM_RANGE(0, 0) AM_WRITE_LEGACY(spc_latch_outfifo_error_stats) // *set* the outfifo_status_r semaphore, and also latch the error bit at D0.
667		AM_RANGE(1, 1) AM_READWRITE_LEGACY(spc_infifo_data_r, spc_outfifo_data_w) //read from input fifo, write to sound fifo
668		AM_RANGE(TMS32010_BIO, TMS32010_BIO) AM_READ_LEGACY(spc_semaphore_r) //read output fifo writable status
	666	AM_RANGE(0, 0) AM_WRITE(spc_latch_outfifo_error_stats) // *set* the outfifo_status_r semaphore, and also latch the error bit at D0.
	667	AM_RANGE(1, 1) AM_READWRITE(spc_infifo_data_r, spc_outfifo_data_w) //read from input fifo, write to sound fifo
	668	AM_RANGE(TMS32010_BIO, TMS32010_BIO) AM_READ(spc_semaphore_r) //read output fifo writable status
669	669	ADDRESS_MAP_END
670	670
671	671	/******************************************************************************

src/mess/drivers/pc9801.c

r14844	r14845
312	312
313	313	/* PC9821 specific */
314	314	UINT8 m_analog256,m_analog256e;
	315	DECLARE_READ8_MEMBER(pc9801_xx_r);
	316	DECLARE_WRITE8_MEMBER(pc9801_xx_w);
	317	DECLARE_READ8_MEMBER(pc9801_00_r);
	318	DECLARE_WRITE8_MEMBER(pc9801_00_w);
	319	DECLARE_READ8_MEMBER(pc9801_20_r);
	320	DECLARE_WRITE8_MEMBER(pc9801_20_w);
	321	DECLARE_READ8_MEMBER(pc9801_30_r);
	322	DECLARE_WRITE8_MEMBER(pc9801_30_w);
	323	DECLARE_READ8_MEMBER(pc9801_40_r);
	324	DECLARE_WRITE8_MEMBER(pc9801_40_w);
	325	DECLARE_READ8_MEMBER(pc9801_50_r);
	326	DECLARE_WRITE8_MEMBER(pc9801_50_w);
	327	DECLARE_READ8_MEMBER(pc9801_60_r);
	328	DECLARE_WRITE8_MEMBER(pc9801_60_w);
	329	DECLARE_WRITE8_MEMBER(pc9801_vrtc_mask_w);
	330	DECLARE_WRITE8_MEMBER(pc9801_video_ff_w);
	331	DECLARE_READ8_MEMBER(pc9801_70_r);
	332	DECLARE_WRITE8_MEMBER(pc9801_70_w);
	333	DECLARE_READ8_MEMBER(pc9801_sasi_r);
	334	DECLARE_WRITE8_MEMBER(pc9801_sasi_w);
	335	DECLARE_READ8_MEMBER(pc9801_a0_r);
	336	DECLARE_WRITE8_MEMBER(pc9801_a0_w);
	337	DECLARE_READ8_MEMBER(pc9801_fdc_2hd_r);
	338	DECLARE_WRITE8_MEMBER(pc9801_fdc_2hd_w);
	339	DECLARE_READ8_MEMBER(pc9801_fdc_2dd_r);
	340	DECLARE_WRITE8_MEMBER(pc9801_fdc_2dd_w);
	341	DECLARE_READ8_MEMBER(pc9801_tvram_r);
	342	DECLARE_WRITE8_MEMBER(pc9801_tvram_w);
	343	DECLARE_READ8_MEMBER(pc9801_gvram_r);
	344	DECLARE_WRITE8_MEMBER(pc9801_gvram_w);
	345	DECLARE_READ8_MEMBER(pc9801_opn_r);
	346	DECLARE_WRITE8_MEMBER(pc9801_opn_w);
	347	DECLARE_READ8_MEMBER(pc9801rs_wram_r);
	348	DECLARE_WRITE8_MEMBER(pc9801rs_wram_w);
	349	DECLARE_READ8_MEMBER(pc9801rs_ex_wram_r);
	350	DECLARE_WRITE8_MEMBER(pc9801rs_ex_wram_w);
	351	DECLARE_READ8_MEMBER(pc9801rs_ipl_r);
	352	DECLARE_READ8_MEMBER(pc9801rs_knjram_r);
	353	DECLARE_WRITE8_MEMBER(pc9801rs_knjram_w);
	354	DECLARE_WRITE8_MEMBER(pc9801rs_bank_w);
	355	DECLARE_READ8_MEMBER(pc9801rs_f0_r);
	356	DECLARE_WRITE8_MEMBER(pc9801rs_f0_w);
	357	DECLARE_READ8_MEMBER(pc9801rs_30_r);
	358	DECLARE_READ8_MEMBER(pc9801rs_memory_r);
	359	DECLARE_WRITE8_MEMBER(pc9801rs_memory_w);
	360	DECLARE_READ8_MEMBER(pc9810rs_fdc_ctrl_r);
	361	DECLARE_WRITE8_MEMBER(pc9810rs_fdc_ctrl_w);
	362	DECLARE_READ8_MEMBER(pc9801rs_2hd_r);
	363	DECLARE_WRITE8_MEMBER(pc9801rs_2hd_w);
	364	DECLARE_READ8_MEMBER(pc9801rs_2dd_r);
	365	DECLARE_WRITE8_MEMBER(pc9801rs_2dd_w);
	366	DECLARE_WRITE8_MEMBER(pc9801rs_video_ff_w);
	367	DECLARE_WRITE8_MEMBER(pc9801rs_a0_w);
	368	DECLARE_READ8_MEMBER(pc980ux_memory_r);
	369	DECLARE_WRITE8_MEMBER(pc9801ux_memory_w);
	370	DECLARE_WRITE8_MEMBER(pc9821_video_ff_w);
	371	DECLARE_READ8_MEMBER(pc9821_a0_r);
	372	DECLARE_WRITE8_MEMBER(pc9821_a0_w);
	373	DECLARE_READ8_MEMBER(ide_status_r);
	374	DECLARE_READ8_MEMBER(pc_dma_read_byte);
	375	DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
315	376	};
316	377
317	378
r14844	r14845
473	534
474	535
475	536	#if 0
476		static READ8_HANDLER( pc9801_xx_r )
	537	READ8_MEMBER(pc9801_state::pc9801_xx_r)
477	538	{
478	539	if((offset & 1) == 0)
479	540	{
r14844	r14845
487	548	}
488	549	}
489	550
490		static WRITE8_HANDLER( pc9801_xx_w )
	551	WRITE8_MEMBER(pc9801_state::pc9801_xx_w)
491	552	{
492	553	if((offset & 1) == 0)
493	554	{
r14844	r14845
501	562
502	563	#endif
503	564
504		static READ8_HANDLER( pc9801_00_r )
	565	READ8_MEMBER(pc9801_state::pc9801_00_r)
505	566	{
506	567	if((offset & 1) == 0)
507	568	{
508	569	if(offset & 0x14)
509	570	printf("Read to undefined port [%02x]\n",offset+0x00);
510	571	else
511		return pic8259_r(space->machine().device((offset & 8) ? "pic8259_slave" : "pic8259_master"), (offset & 2) >> 1);
	572	return pic8259_r(machine().device((offset & 8) ? "pic8259_slave" : "pic8259_master"), (offset & 2) >> 1);
512	573	}
513	574	else // odd
514	575	{
515		return i8237_r(space->machine().device("dma8237"), (offset & 0x1e) >> 1);
	576	return i8237_r(machine().device("dma8237"), (offset & 0x1e) >> 1);
516	577	}
517	578
518	579	return 0xff;
519	580	}
520	581
521		static WRITE8_HANDLER( pc9801_00_w )
	582	WRITE8_MEMBER(pc9801_state::pc9801_00_w)
522	583	{
523	584	if((offset & 1) == 0)
524	585	{
525	586	if(offset & 0x14)
526	587	printf("Write to undefined port [%02x] <- %02x\n",offset+0x00,data);
527	588	else
528		pic8259_w(space->machine().device((offset & 8) ? "pic8259_slave" : "pic8259_master"), (offset & 2) >> 1, data);
	589	pic8259_w(machine().device((offset & 8) ? "pic8259_slave" : "pic8259_master"), (offset & 2) >> 1, data);
529	590	}
530	591	else // odd
531	592	{
532		i8237_w(space->machine().device("dma8237"), (offset & 0x1e) >> 1, data);
	593	i8237_w(machine().device("dma8237"), (offset & 0x1e) >> 1, data);
533	594	}
534	595	}
535	596
536		static READ8_HANDLER( pc9801_20_r )
	597	READ8_MEMBER(pc9801_state::pc9801_20_r)
537	598	{
538	599	if((offset & 1) == 0)
539	600	{
r14844	r14845
551	612	}
552	613	}
553	614
554		static WRITE8_HANDLER( pc9801_20_w )
	615	WRITE8_MEMBER(pc9801_state::pc9801_20_w)
555	616	{
556		pc9801_state *state = space->machine().driver_data<pc9801_state>();
557	617
558	618	if((offset & 1) == 0)
559	619	{
560	620	if(offset == 0)
561	621	{
562		state->m_rtc->c0_w((data & 0x01) >> 0);
563		state->m_rtc->c1_w((data & 0x02) >> 1);
564		state->m_rtc->c2_w((data & 0x04) >> 2);
565		state->m_rtc->stb_w((data & 0x08) >> 3);
566		state->m_rtc->clk_w((data & 0x10) >> 4);
567		state->m_rtc->data_in_w((data & 0x20) >> 5);
	622	m_rtc->c0_w((data & 0x01) >> 0);
	623	m_rtc->c1_w((data & 0x02) >> 1);
	624	m_rtc->c2_w((data & 0x04) >> 2);
	625	m_rtc->stb_w((data & 0x08) >> 3);
	626	m_rtc->clk_w((data & 0x10) >> 4);
	627	m_rtc->data_in_w((data & 0x20) >> 5);
568	628	if(data & 0xc0)
569	629	printf("RTC write to undefined bits %02x\n",data & 0xc0);
570	630	}
r14844	r14845
574	634	else // odd
575	635	{
576	636	printf("Write to DMA bank register %d %02x\n",((offset >> 1)+1) & 3,data);
577		state->m_dma_offset[0][((offset >> 1)+1) & 3] = data & 0x0f;
	637	m_dma_offset[0][((offset >> 1)+1) & 3] = data & 0x0f;
578	638	}
579	639	}
580	640
581		static READ8_HANDLER( pc9801_30_r )
	641	READ8_MEMBER(pc9801_state::pc9801_30_r)
582	642	{
583	643	if((offset & 1) == 0)
584	644	{
r14844	r14845
591	651	}
592	652	else // odd
593	653	{
594		return space->machine().device<i8255_device>("ppi8255_sys")->read(*space, (offset & 6) >> 1);
	654	return machine().device<i8255_device>("ppi8255_sys")->read(*&space, (offset & 6) >> 1);
595	655	}
596	656	}
597	657
598		static WRITE8_HANDLER( pc9801_30_w )
	658	WRITE8_MEMBER(pc9801_state::pc9801_30_w)
599	659	{
600	660	if((offset & 1) == 0)
601	661	{
r14844	r14845
606	666	}
607	667	else // odd
608	668	{
609		space->machine().device<i8255_device>("ppi8255_sys")->write(*space, (offset & 6) >> 1,data);
	669	machine().device<i8255_device>("ppi8255_sys")->write(*&space, (offset & 6) >> 1,data);
610	670	}
611	671	}
612	672
613		static READ8_HANDLER( pc9801_40_r )
	673	READ8_MEMBER(pc9801_state::pc9801_40_r)
614	674	{
615		pc9801_state *state = space->machine().driver_data<pc9801_state>();
616	675
617	676	if((offset & 1) == 0)
618	677	{
619		return space->machine().device<i8255_device>("ppi8255_prn")->read(*space, (offset & 6) >> 1);
	678	return machine().device<i8255_device>("ppi8255_prn")->read(*&space, (offset & 6) >> 1);
620	679	}
621	680	else // odd
622	681	{
r14844	r14845
629	688	{
630	689	UINT8 res;
631	690
632		res = state->m_keyb_press;
	691	res = m_keyb_press;
633	692
634	693	return res;
635	694	}
r14844	r14845
641	700	return 0xff;
642	701	}
643	702
644		static WRITE8_HANDLER( pc9801_40_w )
	703	WRITE8_MEMBER(pc9801_state::pc9801_40_w)
645	704	{
646	705	if((offset & 1) == 0)
647	706	{
648		space->machine().device<i8255_device>("ppi8255_prn")->write(*space, (offset & 6) >> 1,data);
	707	machine().device<i8255_device>("ppi8255_prn")->write(*&space, (offset & 6) >> 1,data);
649	708	}
650	709	else // odd
651	710	{
r14844	r14845
656	715	}
657	716	}
658	717
659		static READ8_HANDLER( pc9801_50_r )
	718	READ8_MEMBER(pc9801_state::pc9801_50_r)
660	719	{
661		//pc9801_state *state = space->machine().driver_data<pc9801_state>();
662	720
663	721	if((offset & 1) == 0)
664	722	{
r14844	r14845
671	729	}
672	730	else // odd
673	731	{
674		return space->machine().device<i8255_device>("ppi8255_fdd")->read(*space, (offset & 6) >> 1);
	732	return machine().device<i8255_device>("ppi8255_fdd")->read(*&space, (offset & 6) >> 1);
675	733	}
676	734	}
677	735
678		static WRITE8_HANDLER( pc9801_50_w )
	736	WRITE8_MEMBER(pc9801_state::pc9801_50_w)
679	737	{
680		pc9801_state *state = space->machine().driver_data<pc9801_state>();
681	738
682	739	if((offset & 1) == 0)
683	740	{
684	741	if(offset & 4)
685	742	printf("Write to undefined port [%02x] %02x\n",offset+0x50,data);
686	743	else
687		state->m_nmi_ff = (offset & 2) >> 1;
	744	m_nmi_ff = (offset & 2) >> 1;
688	745
689	746	}
690	747	else // odd
691	748	{
692		space->machine().device<i8255_device>("ppi8255_fdd")->write(*space, (offset & 6) >> 1,data);
	749	machine().device<i8255_device>("ppi8255_fdd")->write(*&space, (offset & 6) >> 1,data);
693	750	}
694	751	}
695	752
696		static READ8_HANDLER( pc9801_60_r )
	753	READ8_MEMBER(pc9801_state::pc9801_60_r)
697	754	{
698		pc9801_state *state = space->machine().driver_data<pc9801_state>();
699	755
700	756	if((offset & 1) == 0)
701	757	{
702		return state->m_hgdc1->read(*space, (offset & 2) >> 1); // upd7220 character port
	758	return m_hgdc1->read(*&space, (offset & 2) >> 1); // upd7220 character port
703	759	}
704	760	else // odd
705	761	{
r14844	r14845
708	764	}
709	765	}
710	766
711		static WRITE8_HANDLER( pc9801_60_w )
	767	WRITE8_MEMBER(pc9801_state::pc9801_60_w)
712	768	{
713		pc9801_state *state = space->machine().driver_data<pc9801_state>();
714	769
715	770	if((offset & 1) == 0)
716	771	{
717		state->m_hgdc1->write(*space, (offset & 2) >> 1,data); // upd7220 character port
	772	m_hgdc1->write(*&space, (offset & 2) >> 1,data); // upd7220 character port
718	773	}
719	774	else // odd
720	775	{
r14844	r14845
722	777	}
723	778	}
724	779
725		static WRITE8_HANDLER( pc9801_vrtc_mask_w )
	780	WRITE8_MEMBER(pc9801_state::pc9801_vrtc_mask_w)
726	781	{
727		pc9801_state *state = space->machine().driver_data<pc9801_state>();
728	782
729	783	if((offset & 1) == 0)
730	784	{
731		state->m_vrtc_irq_mask = 1;
	785	m_vrtc_irq_mask = 1;
732	786	}
733	787	else // odd
734	788	{
r14844	r14845
736	790	}
737	791	}
738	792
739		static WRITE8_HANDLER( pc9801_video_ff_w )
	793	WRITE8_MEMBER(pc9801_state::pc9801_video_ff_w)
740	794	{
741		pc9801_state *state = space->machine().driver_data<pc9801_state>();
742	795
743	796	if((offset & 1) == 0)
744	797	{
745		state->m_video_ff[(data & 0x0e) >> 1] = data & 1;
	798	m_video_ff[(data & 0x0e) >> 1] = data & 1;
746	799
747	800	if(0)
748	801	{
r14844	r14845
768	821	}
769	822
770	823
771		static READ8_HANDLER( pc9801_70_r )
	824	READ8_MEMBER(pc9801_state::pc9801_70_r)
772	825	{
773	826	if((offset & 1) == 0)
774	827	{
r14844	r14845
780	833	if(offset & 0x08)
781	834	printf("Read to undefined port [%02x]\n",offset+0x70);
782	835	else
783		return pit8253_r(space->machine().device("pit8253"), (offset & 6) >> 1);
	836	return pit8253_r(machine().device("pit8253"), (offset & 6) >> 1);
784	837	}
785	838
786	839	return 0xff;
787	840	}
788	841
789		static WRITE8_HANDLER( pc9801_70_w )
	842	WRITE8_MEMBER(pc9801_state::pc9801_70_w)
790	843	{
791		pc9801_state *state = space->machine().driver_data<pc9801_state>();
792	844
793	845	if((offset & 1) == 0)
794	846	{
795	847	printf("Write to display register [%02x] %02x\n",offset+0x70,data);
796		state->m_video_reg[offset >> 1] = data;
	848	m_video_reg[offset >> 1] = data;
797	849	}
798	850	else // odd
799	851	{
800	852	if(offset < 0x08)
801		pit8253_w(space->machine().device("pit8253"), (offset & 6) >> 1, data);
	853	pit8253_w(machine().device("pit8253"), (offset & 6) >> 1, data);
802	854	else
803	855	printf("Write to undefined port [%02x] <- %02x\n",offset+0x70,data);
804	856	}
805	857	}
806	858
807		static READ8_HANDLER( pc9801_sasi_r )
	859	READ8_MEMBER(pc9801_state::pc9801_sasi_r)
808	860	{
809	861	if((offset & 1) == 0)
810	862	{
r14844	r14845
818	870	}
819	871	}
820	872
821		static WRITE8_HANDLER( pc9801_sasi_w )
	873	WRITE8_MEMBER(pc9801_state::pc9801_sasi_w)
822	874	{
823	875	if((offset & 1) == 0)
824	876	{
r14844	r14845
830	882	}
831	883	}
832	884
833		static READ8_HANDLER( pc9801_a0_r )
	885	READ8_MEMBER(pc9801_state::pc9801_a0_r)
834	886	{
835		pc9801_state *state = space->machine().driver_data<pc9801_state>();
836	887
837	888	if((offset & 1) == 0)
838	889	{
r14844	r14845
840	891	{
841	892	case 0x00:
842	893	case 0x02:
843		return state->m_hgdc2->read(*space, (offset & 2) >> 1);
	894	return m_hgdc2->read(*&space, (offset & 2) >> 1);
844	895	/* bitmap palette clut read */
845	896	case 0x04:
846		return state->m_vram_disp & 1;
	897	return m_vram_disp & 1;
847	898	case 0x06:
848		return state->m_vram_bank & 1;
	899	return m_vram_bank & 1;
849	900	case 0x08:
850	901	case 0x0a:
851	902	case 0x0c:
852	903	case 0x0e:
853		return state->m_pal_clut[(offset & 0x6) >> 1];
	904	return m_pal_clut[(offset & 0x6) >> 1];
854	905	}
855	906
856	907	return 0xff; //code unreachable
r14844	r14845
861	912	{
862	913	case 0x09://cg window font read
863	914	{
864		UINT8 *pcg = space->machine().region("pcg")->base();
	915	UINT8 *pcg = machine().region("pcg")->base();
865	916
866		return pcg[((state->m_font_addr & 0x7f7f) << 4) | state->m_font_lr | (state->m_font_line & 0x0f)];
	917	return pcg[((m_font_addr & 0x7f7f) << 4) | m_font_lr | (m_font_line & 0x0f)];
867	918	}
868	919	}
869	920
r14844	r14845
872	923	}
873	924	}
874	925
875		static WRITE8_HANDLER( pc9801_a0_w )
	926	WRITE8_MEMBER(pc9801_state::pc9801_a0_w)
876	927	{
877		pc9801_state *state = space->machine().driver_data<pc9801_state>();
878	928
879	929	if((offset & 1) == 0)
880	930	{
r14844	r14845
882	932	{
883	933	case 0x00:
884	934	case 0x02:
885		state->m_hgdc2->write(*space, (offset & 2) >> 1,data);
	935	m_hgdc2->write(*&space, (offset & 2) >> 1,data);
886	936	return;
887		case 0x04: state->m_vram_disp = data & 1; return;
	937	case 0x04: m_vram_disp = data & 1; return;
888	938	case 0x06:
889		state->m_vram_bank = data & 1;
890		//state->m_hgdc2->bank_w(*space, 0,(data & 1) << 2); //TODO: check me
	939	m_vram_bank = data & 1;
	940	//m_hgdc2->bank_w(*&space, 0,(data & 1) << 2); //TODO: check me
891	941	return;
892	942	/* bitmap palette clut write */
893	943	case 0x08:
r14844	r14845
897	947	{
898	948	UINT8 pal_entry;
899	949
900		state->m_pal_clut[(offset & 0x6) >> 1] = data;
	950	m_pal_clut[(offset & 0x6) >> 1] = data;
901	951
902	952	/* can't be more twisted I presume ... :-/ */
903	953	pal_entry = (((offset & 4) >> 1) | ((offset & 2) << 1)) >> 1;
904	954	pal_entry ^= 3;
905	955
906		palette_set_color_rgb(space->machine(), (pal_entry)|4|8, pal1bit((data & 0x2) >> 1), pal1bit((data & 4) >> 2), pal1bit((data & 1) >> 0));
907		palette_set_color_rgb(space->machine(), (pal_entry)|8, pal1bit((data & 0x20) >> 5), pal1bit((data & 0x40) >> 6), pal1bit((data & 0x10) >> 4));
	956	palette_set_color_rgb(machine(), (pal_entry)|4|8, pal1bit((data & 0x2) >> 1), pal1bit((data & 4) >> 2), pal1bit((data & 1) >> 0));
	957	palette_set_color_rgb(machine(), (pal_entry)|8, pal1bit((data & 0x20) >> 5), pal1bit((data & 0x40) >> 6), pal1bit((data & 0x10) >> 4));
908	958	return;
909	959	}
910	960	default:
r14844	r14845
917	967	switch((offset & 0xe) + 1)
918	968	{
919	969	case 0x01:
920		state->m_font_addr = (data << 8) | (state->m_font_addr & 0xff);
	970	m_font_addr = (data << 8) | (m_font_addr & 0xff);
921	971	return;
922	972	case 0x03:
923		state->m_font_addr = (data & 0xff) | (state->m_font_addr & 0xff00);
	973	m_font_addr = (data & 0xff) | (m_font_addr & 0xff00);
924	974	return;
925	975	case 0x05:
926		state->m_font_line = data & 0x1f;
927		state->m_font_lr = data & 0x20 ? 0x000 : 0x800;
	976	m_font_line = data & 0x1f;
	977	m_font_lr = data & 0x20 ? 0x000 : 0x800;
928	978	return;
929	979	case 0x09: //cg window font write
930	980	{
931		UINT8 *pcg = space->machine().region("pcg")->base();
	981	UINT8 *pcg = machine().region("pcg")->base();
932	982
933		pcg[((state->m_font_addr & 0x7f7f) << 4) | state->m_font_lr | state->m_font_line] = data;
	983	pcg[((m_font_addr & 0x7f7f) << 4) | m_font_lr | m_font_line] = data;
934	984	return;
935	985	}
936	986	}
r14844	r14845
939	989	}
940	990	}
941	991
942		static READ8_HANDLER( pc9801_fdc_2hd_r )
	992	READ8_MEMBER(pc9801_state::pc9801_fdc_2hd_r)
943	993	{
944		pc9801_state *state = space->machine().driver_data<pc9801_state>();
945	994
946	995	if((offset & 1) == 0)
947	996	{
948	997	switch(offset & 6)
949	998	{
950		case 0:   return upd765_status_r(space->machine().device("upd765_2hd"),0);
951		case 2: return upd765_data_r(space->machine().device("upd765_2hd"),0);
	999	case 0:   return upd765_status_r(machine().device("upd765_2hd"),0);
	1000	case 2: return upd765_data_r(machine().device("upd765_2hd"),0);
952	1001	case 4: return 0x5f; //unknown port meaning
953	1002	}
954	1003	}
r14844	r14845
956	1005	{
957	1006	switch((offset & 6) + 1)
958	1007	{
959		case 1: return state->m_sio->data_r(*space, 0);
960		case 3: return state->m_sio->status_r(*space, 0);
	1008	case 1: return m_sio->data_r(*&space, 0);
	1009	case 3: return m_sio->status_r(*&space, 0);
961	1010	}
962	1011	printf("Read to undefined port [%02x]\n",offset+0x90);
963	1012	return 0xff;
r14844	r14845
966	1015	return 0xff;
967	1016	}
968	1017
969		static WRITE8_HANDLER( pc9801_fdc_2hd_w )
	1018	WRITE8_MEMBER(pc9801_state::pc9801_fdc_2hd_w)
970	1019	{
971		pc9801_state *state = space->machine().driver_data<pc9801_state>();
972	1020
973	1021	if((offset & 1) == 0)
974	1022	{
975	1023	switch(offset & 6)
976	1024	{
977	1025	case 0: printf("Write to undefined port [%02x] <- %02x\n",offset+0x90,data); return;
978		case 2: upd765_data_w(space->machine().device("upd765_2hd"),0,data); return;
	1026	case 2: upd765_data_w(machine().device("upd765_2hd"),0,data); return;
979	1027	case 4:
980	1028	printf("%02x ctrl\n",data);
981		if(((state->m_fdc_2hd_ctrl & 0x80) == 0) && (data & 0x80))
982		upd765_reset_w(space->machine().device("upd765_2hd"),1);
983		if((state->m_fdc_2hd_ctrl & 0x80) && (!(data & 0x80)))
984		upd765_reset_w(space->machine().device("upd765_2hd"),0);
	1029	if(((m_fdc_2hd_ctrl & 0x80) == 0) && (data & 0x80))
	1030	upd765_reset_w(machine().device("upd765_2hd"),1);
	1031	if((m_fdc_2hd_ctrl & 0x80) && (!(data & 0x80)))
	1032	upd765_reset_w(machine().device("upd765_2hd"),0);
985	1033
986		state->m_fdc_2hd_ctrl = data;
987		floppy_mon_w(floppy_get_device(space->machine(), 0), (data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
988		floppy_mon_w(floppy_get_device(space->machine(), 1), (data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
989		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 0), (data & 0x40), 0);
990		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 1), (data & 0x40), 0);
	1034	m_fdc_2hd_ctrl = data;
	1035	floppy_mon_w(floppy_get_device(machine(), 0), (data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
	1036	floppy_mon_w(floppy_get_device(machine(), 1), (data & 0x40) ? CLEAR_LINE : ASSERT_LINE);
	1037	floppy_drive_set_ready_state(floppy_get_device(machine(), 0), (data & 0x40), 0);
	1038	floppy_drive_set_ready_state(floppy_get_device(machine(), 1), (data & 0x40), 0);
991	1039	break;
992	1040	}
993	1041	}
r14844	r14845
995	1043	{
996	1044	switch((offset & 6) + 1)
997	1045	{
998		case 1: state->m_sio->data_w(*space, 0, data); return;
999		case 3: state->m_sio->control_w(*space, 0, data); return;
	1046	case 1: m_sio->data_w(*&space, 0, data); return;
	1047	case 3: m_sio->control_w(*&space, 0, data); return;
1000	1048	}
1001	1049	printf("Write to undefined port [%02x] <- %02x\n",offset+0x90,data);
1002	1050	}
1003	1051	}
1004	1052
1005	1053
1006		static READ8_HANDLER( pc9801_fdc_2dd_r )
	1054	READ8_MEMBER(pc9801_state::pc9801_fdc_2dd_r)
1007	1055	{
1008	1056	if((offset & 1) == 0)
1009	1057	{
1010	1058	switch(offset & 6)
1011	1059	{
1012		case 0:   return upd765_status_r(space->machine().device("upd765_2dd"),0);
1013		case 2: return upd765_data_r(space->machine().device("upd765_2dd"),0);
	1060	case 0:   return upd765_status_r(machine().device("upd765_2dd"),0);
	1061	case 2: return upd765_data_r(machine().device("upd765_2dd"),0);
1014	1062	case 4: return 0x40; //unknown port meaning, might be 0x70
1015	1063	}
1016	1064	}
r14844	r14845
1023	1071	return 0xff;
1024	1072	}
1025	1073
1026		static WRITE8_HANDLER( pc9801_fdc_2dd_w )
	1074	WRITE8_MEMBER(pc9801_state::pc9801_fdc_2dd_w)
1027	1075	{
1028		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1029	1076
1030	1077	if((offset & 1) == 0)
1031	1078	{
1032	1079	switch(offset & 6)
1033	1080	{
1034	1081	case 0: printf("Write to undefined port [%02x] <- %02x\n",offset+0xc8,data); return;
1035		case 2: upd765_data_w(space->machine().device("upd765_2dd"),0,data); return;
	1082	case 2: upd765_data_w(machine().device("upd765_2dd"),0,data); return;
1036	1083	case 4:
1037	1084	printf("%02x ctrl\n",data);
1038		if(((state->m_fdc_2dd_ctrl & 0x80) == 0) && (data & 0x80))
1039		upd765_reset_w(space->machine().device("upd765_2dd"),1);
1040		if((state->m_fdc_2dd_ctrl & 0x80) && (!(data & 0x80)))
1041		upd765_reset_w(space->machine().device("upd765_2dd"),0);
	1085	if(((m_fdc_2dd_ctrl & 0x80) == 0) && (data & 0x80))
	1086	upd765_reset_w(machine().device("upd765_2dd"),1);
	1087	if((m_fdc_2dd_ctrl & 0x80) && (!(data & 0x80)))
	1088	upd765_reset_w(machine().device("upd765_2dd"),0);
1042	1089
1043		state->m_fdc_2dd_ctrl = data;
1044		//floppy_mon_w(floppy_get_device(space->machine(), 0), (data & 8) ? CLEAR_LINE : ASSERT_LINE);
1045		//floppy_mon_w(floppy_get_device(space->machine(), 1), (data & 8) ? CLEAR_LINE : ASSERT_LINE);
1046		//floppy_drive_set_ready_state(floppy_get_device(space->machine(), 0), (data & 8), 0);
1047		//floppy_drive_set_ready_state(floppy_get_device(space->machine(), 1), (data & 8), 0);
	1090	m_fdc_2dd_ctrl = data;
	1091	//floppy_mon_w(floppy_get_device(machine(), 0), (data & 8) ? CLEAR_LINE : ASSERT_LINE);
	1092	//floppy_mon_w(floppy_get_device(machine(), 1), (data & 8) ? CLEAR_LINE : ASSERT_LINE);
	1093	//floppy_drive_set_ready_state(floppy_get_device(machine(), 0), (data & 8), 0);
	1094	//floppy_drive_set_ready_state(floppy_get_device(machine(), 1), (data & 8), 0);
1048	1095	break;
1049	1096	}
1050	1097	}
r14844	r14845
1056	1103
1057	1104
1058	1105	/* TODO: banking? */
1059		static READ8_HANDLER( pc9801_tvram_r )
	1106	READ8_MEMBER(pc9801_state::pc9801_tvram_r)
1060	1107	{
1061		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1062	1108	UINT8 res;
1063	1109
1064	1110	if((offset & 0x2000) && offset & 1)
1065	1111	return 0xff;
1066	1112
1067		//res = upd7220_vram_r(space->machine().device("upd7220_chr"),offset);
1068		res = state->m_tvram[offset];
	1113	//res = upd7220_vram_r(machine().device("upd7220_chr"),offset);
	1114	res = m_tvram[offset];
1069	1115
1070	1116	return res;
1071	1117	}
1072	1118
1073		static WRITE8_HANDLER( pc9801_tvram_w )
	1119	WRITE8_MEMBER(pc9801_state::pc9801_tvram_w)
1074	1120	{
1075		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1076	1121
1077		if(offset < (0x3fe2) || state->m_video_ff[MEMSW_REG])
1078		state->m_tvram[offset] = data;
	1122	if(offset < (0x3fe2) || m_video_ff[MEMSW_REG])
	1123	m_tvram[offset] = data;
1079	1124
1080		state->m_video_ram_1[offset] = data; //TODO: check me
	1125	m_video_ram_1[offset] = data; //TODO: check me
1081	1126	}
1082	1127
1083		static READ8_HANDLER( pc9801_gvram_r )
	1128	READ8_MEMBER(pc9801_state::pc9801_gvram_r)
1084	1129	{
1085		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1086	1130
1087		return state->m_video_ram_2[offset+0x8000+state->m_vram_bank*0x20000];
	1131	return m_video_ram_2[offset+0x8000+m_vram_bank*0x20000];
1088	1132	}
1089	1133
1090		static WRITE8_HANDLER( pc9801_gvram_w )
	1134	WRITE8_MEMBER(pc9801_state::pc9801_gvram_w)
1091	1135	{
1092		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1093	1136
1094		state->m_video_ram_2[offset+0x8000+state->m_vram_bank*0x20000] = data;
	1137	m_video_ram_2[offset+0x8000+m_vram_bank*0x20000] = data;
1095	1138	}
1096	1139
1097		static READ8_HANDLER( pc9801_opn_r )
	1140	READ8_MEMBER(pc9801_state::pc9801_opn_r)
1098	1141	{
1099	1142	if((offset & 1) == 0)
1100		return ym2203_r(space->machine().device("opn"),offset >> 1);
	1143	return ym2203_r(machine().device("opn"),offset >> 1);
1101	1144	else // odd
1102	1145	{
1103	1146	printf("Read to undefined port [%02x]\n",offset+0x188);
r14844	r14845
1105	1148	}
1106	1149	}
1107	1150
1108		static WRITE8_HANDLER( pc9801_opn_w )
	1151	WRITE8_MEMBER(pc9801_state::pc9801_opn_w)
1109	1152	{
1110	1153	if((offset & 1) == 0)
1111		ym2203_w(space->machine().device("opn"),offset >> 1,data);
	1154	ym2203_w(machine().device("opn"),offset >> 1,data);
1112	1155	else // odd
1113	1156	{
1114	1157	printf("Write to undefined port [%02x] %02x\n",offset+0x188,data);
r14844	r14845
1118	1161
1119	1162	static ADDRESS_MAP_START( pc9801_map, AS_PROGRAM, 16, pc9801_state )
1120	1163	AM_RANGE(0x00000, 0x9ffff) AM_RAM //work RAM
1121		AM_RANGE(0xa0000, 0xa3fff) AM_READWRITE8_LEGACY(pc9801_tvram_r,pc9801_tvram_w,0xffff) //TVRAM
1122		AM_RANGE(0xa8000, 0xbffff) AM_READWRITE8_LEGACY(pc9801_gvram_r,pc9801_gvram_w,0xffff) //bitmap VRAM
	1164	AM_RANGE(0xa0000, 0xa3fff) AM_READWRITE8(pc9801_tvram_r,pc9801_tvram_w,0xffff) //TVRAM
	1165	AM_RANGE(0xa8000, 0xbffff) AM_READWRITE8(pc9801_gvram_r,pc9801_gvram_w,0xffff) //bitmap VRAM
1123	1166	AM_RANGE(0xcc000, 0xcdfff) AM_ROM AM_REGION("sound_bios",0) //sound BIOS
1124	1167	AM_RANGE(0xd6000, 0xd6fff) AM_ROM AM_REGION("fdc_bios_2dd",0) //floppy BIOS 2dd
1125	1168	AM_RANGE(0xd7000, 0xd7fff) AM_ROM AM_REGION("fdc_bios_2hd",0) //floppy BIOS 2hd
r14844	r14845
1128	1171
1129	1172	/* first device is even offsets, second one is odd offsets */
1130	1173	static ADDRESS_MAP_START( pc9801_io, AS_IO, 16, pc9801_state )
1131		AM_RANGE(0x0000, 0x001f) AM_READWRITE8_LEGACY(pc9801_00_r,pc9801_00_w,0xffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
1132		AM_RANGE(0x0020, 0x0027) AM_READWRITE8_LEGACY(pc9801_20_r,pc9801_20_w,0xffff) // RTC / DMA registers (LS244)
1133		AM_RANGE(0x0030, 0x0037) AM_READWRITE8_LEGACY(pc9801_30_r,pc9801_30_w,0xffff) //i8251 RS232c / i8255 system port
1134		AM_RANGE(0x0040, 0x0047) AM_READWRITE8_LEGACY(pc9801_40_r,pc9801_40_w,0xffff) //i8255 printer port / i8251 keyboard
1135		AM_RANGE(0x0050, 0x0057) AM_READWRITE8_LEGACY(pc9801_50_r,pc9801_50_w,0xffff) // NMI FF / i8255 floppy port (2d?)
1136		AM_RANGE(0x0060, 0x0063) AM_READWRITE8_LEGACY(pc9801_60_r,pc9801_60_w,0xffff) //upd7220 character ports / <undefined>
1137		AM_RANGE(0x0064, 0x0065) AM_WRITE8_LEGACY(pc9801_vrtc_mask_w,0xffff)
1138		AM_RANGE(0x0068, 0x0069) AM_WRITE8_LEGACY(pc9801_video_ff_w,0xffff) //mode FF / <undefined>
	1174	AM_RANGE(0x0000, 0x001f) AM_READWRITE8(pc9801_00_r,pc9801_00_w,0xffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
	1175	AM_RANGE(0x0020, 0x0027) AM_READWRITE8(pc9801_20_r,pc9801_20_w,0xffff) // RTC / DMA registers (LS244)
	1176	AM_RANGE(0x0030, 0x0037) AM_READWRITE8(pc9801_30_r,pc9801_30_w,0xffff) //i8251 RS232c / i8255 system port
	1177	AM_RANGE(0x0040, 0x0047) AM_READWRITE8(pc9801_40_r,pc9801_40_w,0xffff) //i8255 printer port / i8251 keyboard
	1178	AM_RANGE(0x0050, 0x0057) AM_READWRITE8(pc9801_50_r,pc9801_50_w,0xffff) // NMI FF / i8255 floppy port (2d?)
	1179	AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,pc9801_60_w,0xffff) //upd7220 character ports / <undefined>
	1180	AM_RANGE(0x0064, 0x0065) AM_WRITE8(pc9801_vrtc_mask_w,0xffff)
	1181	AM_RANGE(0x0068, 0x0069) AM_WRITE8(pc9801_video_ff_w,0xffff) //mode FF / <undefined>
1139	1182	//  AM_RANGE(0x006c, 0x006f) border color / <undefined>
1140		AM_RANGE(0x0070, 0x007b) AM_READWRITE8_LEGACY(pc9801_70_r,pc9801_70_w,0xffff) //display registers / i8253 pit
1141		AM_RANGE(0x0080, 0x0083) AM_READWRITE8_LEGACY(pc9801_sasi_r,pc9801_sasi_w,0xffff) //HDD SASI interface / <undefined>
1142		AM_RANGE(0x0090, 0x0097) AM_READWRITE8_LEGACY(pc9801_fdc_2hd_r,pc9801_fdc_2hd_w,0xffff) //upd765a 2hd / cmt
1143		AM_RANGE(0x00a0, 0x00af) AM_READWRITE8_LEGACY(pc9801_a0_r,pc9801_a0_w,0xffff) //upd7220 bitmap ports / display registers
1144		AM_RANGE(0x00c8, 0x00cd) AM_READWRITE8_LEGACY(pc9801_fdc_2dd_r,pc9801_fdc_2dd_w,0xffff) //upd765a 2dd / <undefined>
1145		AM_RANGE(0x0188, 0x018b) AM_READWRITE8_LEGACY(pc9801_opn_r,pc9801_opn_w,0xffff) //ym2203 opn / <undefined>
	1183	AM_RANGE(0x0070, 0x007b) AM_READWRITE8(pc9801_70_r,pc9801_70_w,0xffff) //display registers / i8253 pit
	1184	AM_RANGE(0x0080, 0x0083) AM_READWRITE8(pc9801_sasi_r,pc9801_sasi_w,0xffff) //HDD SASI interface / <undefined>
	1185	AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801_fdc_2hd_r,pc9801_fdc_2hd_w,0xffff) //upd765a 2hd / cmt
	1186	AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,pc9801_a0_w,0xffff) //upd7220 bitmap ports / display registers
	1187	AM_RANGE(0x00c8, 0x00cd) AM_READWRITE8(pc9801_fdc_2dd_r,pc9801_fdc_2dd_w,0xffff) //upd765a 2dd / <undefined>
	1188	AM_RANGE(0x0188, 0x018b) AM_READWRITE8(pc9801_opn_r,pc9801_opn_w,0xffff) //ym2203 opn / <undefined>
1146	1189	ADDRESS_MAP_END
1147	1190
1148	1191	/*************************************
r14844	r14845
1151	1194	*
1152	1195	************************************/
1153	1196
1154		static READ8_HANDLER( pc9801rs_wram_r )
	1197	READ8_MEMBER(pc9801_state::pc9801rs_wram_r)
1155	1198	{
1156		UINT8 *WRAM = space->machine().region("wram")->base();
	1199	UINT8 *WRAM = machine().region("wram")->base();
1157	1200
1158	1201	return WRAM[offset];
1159	1202	}
1160	1203
1161		static WRITE8_HANDLER( pc9801rs_wram_w )
	1204	WRITE8_MEMBER(pc9801_state::pc9801rs_wram_w)
1162	1205	{
1163		UINT8 *WRAM = space->machine().region("wram")->base();
	1206	UINT8 *WRAM = machine().region("wram")->base();
1164	1207
1165	1208	WRAM[offset] = data;
1166	1209	}
1167	1210
1168		static READ8_HANDLER( pc9801rs_ex_wram_r )
	1211	READ8_MEMBER(pc9801_state::pc9801rs_ex_wram_r)
1169	1212	{
1170		UINT8 *EX_WRAM = space->machine().region("ex_wram")->base();
	1213	UINT8 *EX_WRAM = machine().region("ex_wram")->base();
1171	1214
1172	1215	return EX_WRAM[offset];
1173	1216	}
1174	1217
1175		static WRITE8_HANDLER( pc9801rs_ex_wram_w )
	1218	WRITE8_MEMBER(pc9801_state::pc9801rs_ex_wram_w)
1176	1219	{
1177		UINT8 *EX_WRAM = space->machine().region("ex_wram")->base();
	1220	UINT8 *EX_WRAM = machine().region("ex_wram")->base();
1178	1221
1179	1222	EX_WRAM[offset] = data;
1180	1223	}
1181	1224
1182		static READ8_HANDLER( pc9801rs_ipl_r )
	1225	READ8_MEMBER(pc9801_state::pc9801rs_ipl_r)
1183	1226	{
1184		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1185		UINT8 *ROM = space->machine().region("ipl")->base();
	1227	UINT8 *ROM = machine().region("ipl")->base();
1186	1228
1187		return ROM[(offset & 0x1ffff)+(state->m_rom_bank*0x20000)];
	1229	return ROM[(offset & 0x1ffff)+(m_rom_bank*0x20000)];
1188	1230	}
1189	1231
1190		static READ8_HANDLER( pc9801rs_knjram_r )
	1232	READ8_MEMBER(pc9801_state::pc9801rs_knjram_r)
1191	1233	{
1192	1234
1193		UINT8 *KNJRAM = space->machine().region("kanji")->base();
	1235	UINT8 *KNJRAM = machine().region("kanji")->base();
1194	1236
1195	1237	return KNJRAM[offset];
1196	1238	}
1197	1239
1198		static WRITE8_HANDLER( pc9801rs_knjram_w )
	1240	WRITE8_MEMBER(pc9801_state::pc9801rs_knjram_w)
1199	1241	{
1200		UINT8 *KNJRAM = space->machine().region("kanji")->base();
	1242	UINT8 *KNJRAM = machine().region("kanji")->base();
1201	1243
1202	1244	KNJRAM[offset] = data;
1203	1245	}
1204	1246
1205	1247	/* FF-based */
1206		static WRITE8_HANDLER( pc9801rs_bank_w )
	1248	WRITE8_MEMBER(pc9801_state::pc9801rs_bank_w)
1207	1249	{
1208		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1209	1250
1210	1251	if(offset == 1)
1211	1252	{
r14844	r14845
1213	1254	{
1214	1255	if((data & 0xed) == 0x00)
1215	1256	{
1216		state->m_rom_bank = (data & 2) >> 1;
	1257	m_rom_bank = (data & 2) >> 1;
1217	1258	return;
1218	1259	}
1219	1260	}
r14844	r14845
1223	1264	if(offset == 3)
1224	1265	{
1225	1266	if((data & 0xf0) == 0x20)
1226		state->m_vram_bank = (data & 2) >> 1;
	1267	m_vram_bank = (data & 2) >> 1;
1227	1268	else
1228	1269	printf("Unknown EMS RAM setting %02x\n",data);
1229	1270	}
1230	1271	}
1231	1272
1232		static READ8_HANDLER( pc9801rs_f0_r )
	1273	READ8_MEMBER(pc9801_state::pc9801rs_f0_r)
1233	1274	{
1234		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1235	1275
1236	1276	if(offset == 0x02)
1237		return (state->m_gate_a20 ^ 1) | 0x2e;
	1277	return (m_gate_a20 ^ 1) | 0x2e;
1238	1278	else if(offset == 0x06)
1239		return (state->m_gate_a20 ^ 1) | 0x5e;
	1279	return (m_gate_a20 ^ 1) | 0x5e;
1240	1280
1241	1281	return 0x00;
1242	1282	}
1243	1283
1244		static WRITE8_HANDLER( pc9801rs_f0_w )
	1284	WRITE8_MEMBER(pc9801_state::pc9801rs_f0_w)
1245	1285	{
1246		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1247	1286
1248	1287	if(offset == 0x00)
1249	1288	{
1250		state->m_por = 0x00;
1251		cputag_set_input_line(space->machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE);
	1289	m_por = 0x00;
	1290	cputag_set_input_line(machine(), "maincpu", INPUT_LINE_RESET, PULSE_LINE);
1252	1291	}
1253	1292
1254	1293	if(offset == 0x02)
1255		state->m_gate_a20 = 1;
	1294	m_gate_a20 = 1;
1256	1295
1257	1296	if(offset == 0x06)
1258	1297	{
1259	1298	if(data == 0x02)
1260		state->m_gate_a20 = 1;
	1299	m_gate_a20 = 1;
1261	1300	else if(data == 0x03)
1262		state->m_gate_a20 = 0;
	1301	m_gate_a20 = 0;
1263	1302	}
1264	1303	}
1265	1304
1266		static READ8_HANDLER( pc9801rs_30_r )
	1305	READ8_MEMBER(pc9801_state::pc9801rs_30_r)
1267	1306	{
1268		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1269	1307
1270	1308	if(offset == 5)
1271		return (pc9801_30_r(space,offset) & ~0xa0) | state->m_por; //ppi bug?
	1309	return (pc9801_30_r(space,offset) & ~0xa0) | m_por; //ppi bug?
1272	1310
1273	1311	return pc9801_30_r(space,offset);
1274	1312	}
1275	1313
1276		static READ8_HANDLER( pc9801rs_memory_r )
	1314	READ8_MEMBER(pc9801_state::pc9801rs_memory_r)
1277	1315	{
1278		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1279	1316
1280		if(state->m_gate_a20 == 0)
	1317	if(m_gate_a20 == 0)
1281	1318	offset &= 0xfffff;
1282	1319
1283	1320	if      (                        offset <= 0x0009ffff)                   { return pc9801rs_wram_r(space,offset);               }
r14844	r14845
1285	1322	else if(offset >= 0x000a4000 && offset <= 0x000a4fff)                   { return pc9801rs_knjram_r(space,offset & 0xfff);     }
1286	1323	else if(offset >= 0x000a8000 && offset <= 0x000bffff)                   { return pc9801_gvram_r(space,offset-0xa8000);        }
1287	1324	else if(offset >= 0x000e0000 && offset <= 0x000fffff)                   { return pc9801rs_ipl_r(space,offset & 0x1ffff);      }
1288		else if(offset >= 0x00100000 && offset <= 0x00100000+state->m_ram_size-1) { return pc9801rs_ex_wram_r(space,offset-0x00100000); }
	1325	else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { return pc9801rs_ex_wram_r(space,offset-0x00100000); }
1289	1326	else if(offset >= 0xfffe0000 && offset <= 0xffffffff)                   { return pc9801rs_ipl_r(space,offset & 0x1ffff);      }
1290	1327
1291	1328	//printf("%08x\n",offset);
r14844	r14845
1293	1330	}
1294	1331
1295	1332
1296		static WRITE8_HANDLER( pc9801rs_memory_w )
	1333	WRITE8_MEMBER(pc9801_state::pc9801rs_memory_w)
1297	1334	{
1298		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1299	1335
1300		if(state->m_gate_a20 == 0)
	1336	if(m_gate_a20 == 0)
1301	1337	offset &= 0xfffff;
1302	1338
1303	1339	if      (                        offset <= 0x0009ffff)                   { pc9801rs_wram_w(space,offset,data);                  }
1304	1340	else if(offset >= 0x000a0000 && offset <= 0x000a3fff)                   { pc9801_tvram_w(space,offset-0xa0000,data);           }
1305	1341	else if(offset >= 0x000a4000 && offset <= 0x000a4fff)                   { pc9801rs_knjram_w(space,offset & 0xfff,data);        }
1306	1342	else if(offset >= 0x000a8000 && offset <= 0x000bffff)                   { pc9801_gvram_w(space,offset-0xa8000,data);           }
1307		else if(offset >= 0x00100000 && offset <= 0x00100000+state->m_ram_size-1) { pc9801rs_ex_wram_w(space,offset-0x00100000,data);    }
	1343	else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { pc9801rs_ex_wram_w(space,offset-0x00100000,data);    }
1308	1344	//else
1309	1345	//  printf("%08x %08x\n",offset,data);
1310	1346
1311	1347	}
1312	1348
1313		static READ8_HANDLER( pc9810rs_fdc_ctrl_r )
	1349	READ8_MEMBER(pc9801_state::pc9810rs_fdc_ctrl_r)
1314	1350	{
1315		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1316	1351
1317		return (state->m_fdc_ctrl & 3) | 8;
	1352	return (m_fdc_ctrl & 3) | 8;
1318	1353	}
1319	1354
1320		static WRITE8_HANDLER( pc9810rs_fdc_ctrl_w )
	1355	WRITE8_MEMBER(pc9801_state::pc9810rs_fdc_ctrl_w)
1321	1356	{
1322	1357	/*
1323	1358	---- x--- ready line?
1324	1359	---- --x- select type (1) 2hd (0) 2dd
1325	1360	---- ---x select irq
1326	1361	*/
1327		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1328	1362
1329		state->m_fdc_ctrl = data;
	1363	m_fdc_ctrl = data;
1330	1364	if(data & 0xfc)
1331	1365	printf("FDC ctrl called with %02x\n",data);
1332	1366	}
1333	1367
1334		static READ8_HANDLER( pc9801rs_2hd_r )
	1368	READ8_MEMBER(pc9801_state::pc9801rs_2hd_r)
1335	1369	{
1336	1370	if((offset & 1) == 0)
1337	1371	{
1338	1372	switch(offset & 6)
1339	1373	{
1340		case 0:   return upd765_status_r(space->machine().device("upd765_2hd"),0);
1341		case 2: return upd765_data_r(space->machine().device("upd765_2hd"),0);
	1374	case 0:   return upd765_status_r(machine().device("upd765_2hd"),0);
	1375	case 2: return upd765_data_r(machine().device("upd765_2hd"),0);
1342	1376	case 4: return 0x40; //2hd flag
1343	1377	}
1344	1378	}
r14844	r14845
1348	1382	return 0xff;
1349	1383	}
1350	1384
1351		static WRITE8_HANDLER( pc9801rs_2hd_w )
	1385	WRITE8_MEMBER(pc9801_state::pc9801rs_2hd_w)
1352	1386	{
1353	1387	if((offset & 1) == 0)
1354	1388	{
1355	1389	switch(offset & 6)
1356	1390	{
1357		case 2: upd765_data_w(space->machine().device("upd765_2hd"),0,data); return;
	1391	case 2: upd765_data_w(machine().device("upd765_2hd"),0,data); return;
1358	1392	case 4: printf("%02x FDC ctrl\n",data); return;
1359	1393	}
1360	1394	}
r14844	r14845
1362	1396	printf("Write to undefined port [%02x] %02x\n",offset+0x90,data);
1363	1397	}
1364	1398
1365		static READ8_HANDLER( pc9801rs_2dd_r )
	1399	READ8_MEMBER(pc9801_state::pc9801rs_2dd_r)
1366	1400	{
1367		//  pc9801_state *state = space->machine().driver_data<pc9801_state>();
1368	1401
1369		//  if(state->m_fdc_ctrl & 1)
	1402	//  if(m_fdc_ctrl & 1)
1370	1403	//      return 0xff;
1371	1404
1372	1405	if((offset & 1) == 0)
1373	1406	{
1374	1407	switch(offset & 6)
1375	1408	{
1376		case 0:   return upd765_status_r(space->machine().device("upd765_2hd"),0);
1377		case 2: return upd765_data_r(space->machine().device("upd765_2hd"),0);
	1409	case 0:   return upd765_status_r(machine().device("upd765_2hd"),0);
	1410	case 2: return upd765_data_r(machine().device("upd765_2hd"),0);
1378	1411	case 4: return 0x70; //2dd flag
1379	1412	}
1380	1413	}
r14844	r14845
1384	1417	return 0xff;
1385	1418	}
1386	1419
1387		static WRITE8_HANDLER( pc9801rs_2dd_w )
	1420	WRITE8_MEMBER(pc9801_state::pc9801rs_2dd_w)
1388	1421	{
1389		//  pc9801_state *state = space->machine().driver_data<pc9801_state>();
1390	1422
1391		//  if(state->m_fdc_ctrl & 1)
	1423	//  if(m_fdc_ctrl & 1)
1392	1424	//      return;
1393	1425
1394	1426	if((offset & 1) == 0)
1395	1427	{
1396	1428	switch(offset & 6)
1397	1429	{
1398		case 2: upd765_data_w(space->machine().device("upd765_2hd"),0,data); return;
	1430	case 2: upd765_data_w(machine().device("upd765_2hd"),0,data); return;
1399	1431	case 4: printf("%02x FDC ctrl\n",data); return;
1400	1432	}
1401	1433	}
r14844	r14845
1403	1435	printf("Write to undefined port [%02x] %02x\n",offset+0x90,data);
1404	1436	}
1405	1437
1406		static WRITE8_HANDLER( pc9801rs_video_ff_w )
	1438	WRITE8_MEMBER(pc9801_state::pc9801rs_video_ff_w)
1407	1439	{
1408		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1409	1440
1410	1441	if(offset == 2)
1411	1442	{
1412	1443	if((data & 0xf8) == 0)
1413	1444	{
1414		state->m_ex_video_ff[(data & 0x6) >> 1] = data & 1;
	1445	m_ex_video_ff[(data & 0x6) >> 1] = data & 1;
1415	1446
1416	1447	if(1)
1417	1448	{
r14844	r14845
1434	1465	pc9801_video_ff_w(space,offset,data);
1435	1466	}
1436	1467
1437		static WRITE8_HANDLER( pc9801rs_a0_w )
	1468	WRITE8_MEMBER(pc9801_state::pc9801rs_a0_w)
1438	1469	{
1439		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1440	1470
1441		if((offset & 1) == 0 && offset & 8 && state->m_ex_video_ff[ANALOG_16])
	1471	if((offset & 1) == 0 && offset & 8 && m_ex_video_ff[ANALOG_16])
1442	1472	{
1443	1473	switch(offset)
1444	1474	{
1445		case 0x08: state->m_analog16.pal_entry = data & 0xf; break;
1446		case 0x0a: state->m_analog16.g[state->m_analog16.pal_entry] = data & 0xf; break;
1447		case 0x0c: state->m_analog16.r[state->m_analog16.pal_entry] = data & 0xf; break;
1448		case 0x0e: state->m_analog16.b[state->m_analog16.pal_entry] = data & 0xf; break;
	1475	case 0x08: m_analog16.pal_entry = data & 0xf; break;
	1476	case 0x0a: m_analog16.g[m_analog16.pal_entry] = data & 0xf; break;
	1477	case 0x0c: m_analog16.r[m_analog16.pal_entry] = data & 0xf; break;
	1478	case 0x0e: m_analog16.b[m_analog16.pal_entry] = data & 0xf; break;
1449	1479	}
1450	1480
1451		palette_set_color_rgb(space->machine(), (state->m_analog16.pal_entry)+0x10,
1452		pal4bit(state->m_analog16.r[state->m_analog16.pal_entry]),
1453		pal4bit(state->m_analog16.g[state->m_analog16.pal_entry]),
1454		pal4bit(state->m_analog16.b[state->m_analog16.pal_entry]));
	1481	palette_set_color_rgb(machine(), (m_analog16.pal_entry)+0x10,
	1482	pal4bit(m_analog16.r[m_analog16.pal_entry]),
	1483	pal4bit(m_analog16.g[m_analog16.pal_entry]),
	1484	pal4bit(m_analog16.b[m_analog16.pal_entry]));
1455	1485	return;
1456	1486	}
1457	1487
r14844	r14845
1459	1489	}
1460	1490
1461	1491	static ADDRESS_MAP_START( pc9801rs_map, AS_PROGRAM, 32, pc9801_state )
1462		AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE8_LEGACY(pc9801rs_memory_r,pc9801rs_memory_w,0xffffffff)
	1492	AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE8(pc9801rs_memory_r,pc9801rs_memory_w,0xffffffff)
1463	1493	ADDRESS_MAP_END
1464	1494
1465	1495	static ADDRESS_MAP_START( pc9801rs_io, AS_IO, 32, pc9801_state )
1466		AM_RANGE(0x0000, 0x001f) AM_READWRITE8_LEGACY(pc9801_00_r,        pc9801_00_w,        0xffffffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
	1496	AM_RANGE(0x0000, 0x001f) AM_READWRITE8(pc9801_00_r,        pc9801_00_w,        0xffffffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
1467	1497
1468		AM_RANGE(0x0030, 0x0037) AM_READWRITE8_LEGACY(pc9801rs_30_r,      pc9801_30_w,        0xffffffff) //i8251 RS232c / i8255 system port
1469		AM_RANGE(0x0040, 0x0047) AM_READWRITE8_LEGACY(pc9801_40_r,        pc9801_40_w,        0xffffffff) //i8255 printer port / i8251 keyboard
1470		AM_RANGE(0x0060, 0x0063) AM_READWRITE8_LEGACY(pc9801_60_r,        pc9801_60_w,        0xffffffff) //upd7220 character ports / <undefined>
1471		AM_RANGE(0x0064, 0x0067) AM_WRITE8_LEGACY(pc9801_vrtc_mask_w, 0xffffffff)
1472		AM_RANGE(0x0068, 0x006b) AM_WRITE8_LEGACY(pc9801rs_video_ff_w,0xffffffff) //mode FF / <undefined>
1473		AM_RANGE(0x0070, 0x007b) AM_READWRITE8_LEGACY(pc9801_70_r,        pc9801_70_w,        0xffffffff) //display registers "GRCG" / i8253 pit
1474		AM_RANGE(0x0090, 0x0097) AM_READWRITE8_LEGACY(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
1475		AM_RANGE(0x00a0, 0x00af) AM_READWRITE8_LEGACY(pc9801_a0_r,        pc9801rs_a0_w,      0xffffffff) //upd7220 bitmap ports / display registers
1476		AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8_LEGACY(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffffffff)
1477		AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8_LEGACY(pc9801rs_2dd_r,     pc9801rs_2dd_w,     0xffffffff)
1478		AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8_LEGACY(pc9801rs_f0_r,      pc9801rs_f0_w,      0xffffffff)
1479		AM_RANGE(0x043c, 0x043f) AM_WRITE8_LEGACY(pc9801rs_bank_w,    0xffffffff) //ROM/RAM bank
	1498	AM_RANGE(0x0030, 0x0037) AM_READWRITE8(pc9801rs_30_r,      pc9801_30_w,        0xffffffff) //i8251 RS232c / i8255 system port
	1499	AM_RANGE(0x0040, 0x0047) AM_READWRITE8(pc9801_40_r,        pc9801_40_w,        0xffffffff) //i8255 printer port / i8251 keyboard
	1500	AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,        pc9801_60_w,        0xffffffff) //upd7220 character ports / <undefined>
	1501	AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffffffff)
	1502	AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9801rs_video_ff_w,0xffffffff) //mode FF / <undefined>
	1503	AM_RANGE(0x0070, 0x007b) AM_READWRITE8(pc9801_70_r,        pc9801_70_w,        0xffffffff) //display registers "GRCG" / i8253 pit
	1504	AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
	1505	AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,        pc9801rs_a0_w,      0xffffffff) //upd7220 bitmap ports / display registers
	1506	AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffffffff)
	1507	AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8(pc9801rs_2dd_r,     pc9801rs_2dd_w,     0xffffffff)
	1508	AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r,      pc9801rs_f0_w,      0xffffffff)
	1509	AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w,    0xffffffff) //ROM/RAM bank
1480	1510
1481	1511	ADDRESS_MAP_END
1482	1512
1483		static READ8_HANDLER( pc980ux_memory_r )
	1513	READ8_MEMBER(pc9801_state::pc980ux_memory_r)
1484	1514	{
1485		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1486	1515
1487		//printf("%08x %d\n",offset,state->m_gate_a20);
	1516	//printf("%08x %d\n",offset,m_gate_a20);
1488	1517
1489		//if(state->m_gate_a20 == 0)
	1518	//if(m_gate_a20 == 0)
1490	1519	//  offset &= 0xfffff;
1491	1520
1492	1521	if      (                        offset <= 0x0009ffff)                   { return pc9801rs_wram_r(space,offset);               }
r14844	r14845
1494	1523	else if(offset >= 0x000a4000 && offset <= 0x000a4fff)                   { return pc9801rs_knjram_r(space,offset & 0xfff);     }
1495	1524	else if(offset >= 0x000a8000 && offset <= 0x000bffff)                   { return pc9801_gvram_r(space,offset-0xa8000);        }
1496	1525	else if(offset >= 0x000e0000 && offset <= 0x000fffff)                   { return pc9801rs_ipl_r(space,offset & 0x1ffff);      }
1497		else if(offset >= 0x00100000 && offset <= 0x00100000+state->m_ram_size-1) { return pc9801rs_ex_wram_r(space,offset-0x00100000); }
	1526	else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { return pc9801rs_ex_wram_r(space,offset-0x00100000); }
1498	1527	else if(offset >= 0x00fe0000 && offset <= 0x00ffffff)                   { return pc9801rs_ipl_r(space,offset & 0x1ffff);      }
1499	1528
1500	1529	return 0x00;
1501	1530	}
1502	1531
1503	1532
1504		static WRITE8_HANDLER( pc9801ux_memory_w )
	1533	WRITE8_MEMBER(pc9801_state::pc9801ux_memory_w)
1505	1534	{
1506		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1507	1535
1508		//if(state->m_gate_a20 == 0)
	1536	//if(m_gate_a20 == 0)
1509	1537	//  offset &= 0xfffff;
1510	1538
1511	1539	if      (                        offset <= 0x0009ffff)                   { pc9801rs_wram_w(space,offset,data);                  }
1512	1540	else if(offset >= 0x000a0000 && offset <= 0x000a3fff)                   { pc9801_tvram_w(space,offset-0xa0000,data);           }
1513	1541	else if(offset >= 0x000a4000 && offset <= 0x000a4fff)                   { pc9801rs_knjram_w(space,offset & 0xfff,data);        }
1514	1542	else if(offset >= 0x000a8000 && offset <= 0x000bffff)                   { pc9801_gvram_w(space,offset-0xa8000,data);           }
1515		else if(offset >= 0x00100000 && offset <= 0x00100000+state->m_ram_size-1) { pc9801rs_ex_wram_w(space,offset-0x00100000,data);    }
	1543	else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { pc9801rs_ex_wram_w(space,offset-0x00100000,data);    }
1516	1544	//else
1517	1545	//  printf("%08x %08x\n",offset,data);
1518	1546
r14844	r14845
1520	1548
1521	1549	static ADDRESS_MAP_START( pc9801ux_map, AS_PROGRAM, 16, pc9801_state )
1522	1550	/* TODO! */
1523		AM_RANGE(0x000000, 0xffffff) AM_READWRITE8_LEGACY(pc980ux_memory_r,pc9801ux_memory_w,0xffff)
	1551	AM_RANGE(0x000000, 0xffffff) AM_READWRITE8(pc980ux_memory_r,pc9801ux_memory_w,0xffff)
1524	1552	ADDRESS_MAP_END
1525	1553
1526	1554	static ADDRESS_MAP_START( pc9801ux_io, AS_IO, 16, pc9801_state )
1527		AM_RANGE(0x0000, 0x001f) AM_READWRITE8_LEGACY(pc9801_00_r,        pc9801_00_w,        0xffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
	1555	AM_RANGE(0x0000, 0x001f) AM_READWRITE8(pc9801_00_r,        pc9801_00_w,        0xffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
1528	1556
1529		AM_RANGE(0x0030, 0x0037) AM_READWRITE8_LEGACY(pc9801rs_30_r,      pc9801_30_w,        0xffff) //i8251 RS232c / i8255 system port
1530		AM_RANGE(0x0040, 0x0047) AM_READWRITE8_LEGACY(pc9801_40_r,        pc9801_40_w,        0xffff) //i8255 printer port / i8251 keyboard
1531		AM_RANGE(0x0060, 0x0063) AM_READWRITE8_LEGACY(pc9801_60_r,        pc9801_60_w,        0xffff) //upd7220 character ports / <undefined>
1532		AM_RANGE(0x0064, 0x0067) AM_WRITE8_LEGACY(pc9801_vrtc_mask_w, 0xffff)
1533		AM_RANGE(0x0068, 0x006b) AM_WRITE8_LEGACY(pc9801rs_video_ff_w,0xffff) //mode FF / <undefined>
1534		AM_RANGE(0x0070, 0x007b) AM_READWRITE8_LEGACY(pc9801_70_r,        pc9801_70_w,        0xffff) //display registers "GRCG" / i8253 pit
1535		AM_RANGE(0x0090, 0x0097) AM_READWRITE8_LEGACY(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffff)
1536		AM_RANGE(0x00a0, 0x00af) AM_READWRITE8_LEGACY(pc9801_a0_r,        pc9801rs_a0_w,      0xffff) //upd7220 bitmap ports / display registers
1537		AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8_LEGACY(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffff)
1538		AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8_LEGACY(pc9801rs_2dd_r,     pc9801rs_2dd_w,     0xffff)
1539		AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8_LEGACY(pc9801rs_f0_r,      pc9801rs_f0_w,      0xffff)
1540		AM_RANGE(0x043c, 0x043f) AM_WRITE8_LEGACY(pc9801rs_bank_w,    0xffff) //ROM/RAM bank
	1557	AM_RANGE(0x0030, 0x0037) AM_READWRITE8(pc9801rs_30_r,      pc9801_30_w,        0xffff) //i8251 RS232c / i8255 system port
	1558	AM_RANGE(0x0040, 0x0047) AM_READWRITE8(pc9801_40_r,        pc9801_40_w,        0xffff) //i8255 printer port / i8251 keyboard
	1559	AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,        pc9801_60_w,        0xffff) //upd7220 character ports / <undefined>
	1560	AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffff)
	1561	AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9801rs_video_ff_w,0xffff) //mode FF / <undefined>
	1562	AM_RANGE(0x0070, 0x007b) AM_READWRITE8(pc9801_70_r,        pc9801_70_w,        0xffff) //display registers "GRCG" / i8253 pit
	1563	AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffff)
	1564	AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r,        pc9801rs_a0_w,      0xffff) //upd7220 bitmap ports / display registers
	1565	AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffff)
	1566	AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8(pc9801rs_2dd_r,     pc9801rs_2dd_w,     0xffff)
	1567	AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r,      pc9801rs_f0_w,      0xffff)
	1568	AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w,    0xffff) //ROM/RAM bank
1541	1569
1542	1570	ADDRESS_MAP_END
1543	1571
r14844	r14845
1548	1576	*
1549	1577	************************************/
1550	1578
1551		static WRITE8_HANDLER( pc9821_video_ff_w )
	1579	WRITE8_MEMBER(pc9801_state::pc9821_video_ff_w)
1552	1580	{
1553		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1554	1581
1555	1582	if(offset == 2)
1556	1583	{
1557	1584	switch(data & 0xf8)   // pc-9821 specific extended registers
1558	1585	{
1559		case 0x20: state->m_analog256 = data & 1; return;
1560		case 0x68: state->m_analog256e = data & 1; return;
	1586	case 0x20: m_analog256 = data & 1; return;
	1587	case 0x68: m_analog256e = data & 1; return;
1561	1588	} // intentional fall-through
1562	1589	}
1563	1590
1564	1591	pc9801rs_video_ff_w(space,offset,data);
1565	1592	}
1566	1593
1567		static READ8_HANDLER( pc9821_a0_r )
	1594	READ8_MEMBER(pc9801_state::pc9821_a0_r)
1568	1595	{
1569		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1570	1596
1571	1597	if((offset & 1) == 0 && offset & 8)
1572	1598	{
1573		if(state->m_analog256)
	1599	if(m_analog256)
1574	1600	{
1575	1601	printf("256 color mode [%02x] R\n",offset);
1576	1602	return 0;
1577	1603	}
1578		else if(state->m_ex_video_ff[ANALOG_16]) //16 color mode, readback possible there
	1604	else if(m_ex_video_ff[ANALOG_16]) //16 color mode, readback possible there
1579	1605	{
1580	1606	UINT8 res = 0;
1581	1607
1582	1608	switch(offset)
1583	1609	{
1584		case 0x08: res = state->m_analog16.pal_entry & 0xf; break;
1585		case 0x0a: res = state->m_analog16.g[state->m_analog16.pal_entry] & 0xf; break;
1586		case 0x0c: res = state->m_analog16.r[state->m_analog16.pal_entry] & 0xf; break;
1587		case 0x0e: res = state->m_analog16.b[state->m_analog16.pal_entry] & 0xf; break;
	1610	case 0x08: res = m_analog16.pal_entry & 0xf; break;
	1611	case 0x0a: res = m_analog16.g[m_analog16.pal_entry] & 0xf; break;
	1612	case 0x0c: res = m_analog16.r[m_analog16.pal_entry] & 0xf; break;
	1613	case 0x0e: res = m_analog16.b[m_analog16.pal_entry] & 0xf; break;
1588	1614	}
1589	1615
1590	1616	return res;
r14844	r14845
1594	1620	return pc9801_a0_r(space,offset);
1595	1621	}
1596	1622
1597		static WRITE8_HANDLER( pc9821_a0_w )
	1623	WRITE8_MEMBER(pc9801_state::pc9821_a0_w)
1598	1624	{
1599		pc9801_state *state = space->machine().driver_data<pc9801_state>();
1600	1625
1601		if((offset & 1) == 0 && offset & 8 && state->m_analog256)
	1626	if((offset & 1) == 0 && offset & 8 && m_analog256)
1602	1627	{
1603	1628	printf("256 color mode [%02x] %02x W\n",offset,data);
1604	1629	return;
r14844	r14845
1607	1632	pc9801rs_a0_w(space,offset,data);
1608	1633	}
1609	1634
1610		static READ8_HANDLER( ide_status_r )
	1635	READ8_MEMBER(pc9801_state::ide_status_r)
1611	1636	{
1612	1637	return 0x50; // status
1613	1638	}
1614	1639
1615	1640	static ADDRESS_MAP_START( pc9821_map, AS_PROGRAM, 32, pc9801_state )
1616		AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE8_LEGACY(pc9801rs_memory_r,pc9801rs_memory_w,0xffffffff)
	1641	AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE8(pc9801rs_memory_r,pc9801rs_memory_w,0xffffffff)
1617	1642	ADDRESS_MAP_END
1618	1643
1619	1644	static ADDRESS_MAP_START( pc9821_io, AS_IO, 32, pc9801_state )
1620		AM_RANGE(0x0000, 0x001f) AM_READWRITE8_LEGACY(pc9801_00_r,        pc9801_00_w,        0xffffffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
	1645	AM_RANGE(0x0000, 0x001f) AM_READWRITE8(pc9801_00_r,        pc9801_00_w,        0xffffffff) // i8259 PIC (bit 3 ON slave / master) / i8237 DMA
1621	1646
1622		AM_RANGE(0x0030, 0x0037) AM_READWRITE8_LEGACY(pc9801rs_30_r,      pc9801_30_w,        0xffffffff) //i8251 RS232c / i8255 system port
1623		AM_RANGE(0x0040, 0x0047) AM_READWRITE8_LEGACY(pc9801_40_r,        pc9801_40_w,        0xffffffff) //i8255 printer port / i8251 keyboard
	1647	AM_RANGE(0x0030, 0x0037) AM_READWRITE8(pc9801rs_30_r,      pc9801_30_w,        0xffffffff) //i8251 RS232c / i8255 system port
	1648	AM_RANGE(0x0040, 0x0047) AM_READWRITE8(pc9801_40_r,        pc9801_40_w,        0xffffffff) //i8255 printer port / i8251 keyboard
1624	1649	AM_RANGE(0x005c, 0x005f) AM_NOP //ARTIC (serial card?)
1625		AM_RANGE(0x0060, 0x0063) AM_READWRITE8_LEGACY(pc9801_60_r,        pc9801_60_w,        0xffffffff) //upd7220 character ports / <undefined>
1626		AM_RANGE(0x0064, 0x0067) AM_WRITE8_LEGACY(pc9801_vrtc_mask_w, 0xffffffff)
1627		AM_RANGE(0x0068, 0x006b) AM_WRITE8_LEGACY(pc9821_video_ff_w,  0xffffffff) //mode FF / <undefined>
1628		AM_RANGE(0x0070, 0x007b) AM_READWRITE8_LEGACY(pc9801_70_r,        pc9801_70_w,        0xffffffff) //display registers "GRCG" / i8253 pit
	1650	AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r,        pc9801_60_w,        0xffffffff) //upd7220 character ports / <undefined>
	1651	AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffffffff)
	1652	AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9821_video_ff_w,  0xffffffff) //mode FF / <undefined>
	1653	AM_RANGE(0x0070, 0x007b) AM_READWRITE8(pc9801_70_r,        pc9801_70_w,        0xffffffff) //display registers "GRCG" / i8253 pit
1629	1654	//  AM_RANGE(0x0080, 0x0083) SASI interface / <undefined>
1630		AM_RANGE(0x0090, 0x0097) AM_READWRITE8_LEGACY(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
1631		AM_RANGE(0x00a0, 0x00af) AM_READWRITE8_LEGACY(pc9821_a0_r,        pc9821_a0_w,        0xffffffff) //upd7220 bitmap ports / display registers
	1655	AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r,     pc9801rs_2hd_w,     0xffffffff)
	1656	AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9821_a0_r,        pc9821_a0_w,        0xffffffff) //upd7220 bitmap ports / display registers
1632	1657	//  AM_RANGE(0x00b0, 0x00b3) PC9861k (serial port?)
1633	1658	//  AM_RANGE(0x00b9, 0x00b9) PC9861k
1634	1659	//  AM_RANGE(0x00bb, 0x00bb) PC9861k
1635		AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8_LEGACY(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffffffff)
1636		AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8_LEGACY(pc9801rs_2dd_r,     pc9801rs_2dd_w,     0xffffffff)
	1660	AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffffffff)
	1661	AM_RANGE(0x00c8, 0x00cf) AM_READWRITE8(pc9801rs_2dd_r,     pc9801rs_2dd_w,     0xffffffff)
1637	1662	//  AM_RANGE(0x00d8, 0x00df) AMD98 (sound?) board
1638		AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8_LEGACY(pc9801rs_f0_r,      pc9801rs_f0_w,      0xffffffff)
	1663	AM_RANGE(0x00f0, 0x00ff) AM_READWRITE8(pc9801rs_f0_r,      pc9801rs_f0_w,      0xffffffff)
1639	1664	//  AM_RANGE(0x0188, 0x018b) YM2203 OPN board / <undefined>
1640	1665	//  AM_RANGE(0x018c, 0x018f) YM2203 OPN extended ports / <undefined>
1641	1666	//  AM_RANGE(0x0430, 0x0430) IDE bank register
1642	1667	//  AM_RANGE(0x0432, 0x0432) IDE bank register (mirror)
1643	1668	//  AM_RANGE(0x0439, 0x0439) ROM/RAM bank (NEC)
1644	1669	//  AM_RANGE(0x043d, 0x043d) ROM/RAM bank (NEC)
1645		AM_RANGE(0x043c, 0x043f) AM_WRITE8_LEGACY(pc9801rs_bank_w,    0xffffffff) //ROM/RAM bank (EPSON)
	1670	AM_RANGE(0x043c, 0x043f) AM_WRITE8(pc9801rs_bank_w,    0xffffffff) //ROM/RAM bank (EPSON)
1646	1671	//  AM_RANGE(0x04a0, 0x04af) EGC
1647	1672	//  AM_RANGE(0x04be, 0x04be) FDC "RPM" register
1648	1673	//  AM_RANGE(0x0642, 0x064f) IDE registers / <undefined>
1649		AM_RANGE(0x074c, 0x074f) AM_READ8_LEGACY(ide_status_r, 0x000000ff) // IDE status (r) - IDE control registers (w) / <undefined>
	1674	AM_RANGE(0x074c, 0x074f) AM_READ8(ide_status_r, 0x000000ff) // IDE status (r) - IDE control registers (w) / <undefined>
1650	1675	//  AM_RANGE(0x08e0, 0x08ea) <undefined> / EMM SIO registers
1651	1676	//  AM_RANGE(0x09a0, 0x09a0) GDC extended register r/w
1652	1677	//  AM_RANGE(0x09a8, 0x09a8) GDC 31KHz register r/w
r14844	r14845
2120	2145	}
2121	2146
2122	2147
2123		static READ8_HANDLER( pc_dma_read_byte )
	2148	READ8_MEMBER(pc9801_state::pc_dma_read_byte)
2124	2149	{
2125		pc9801_state *state = space->machine().driver_data<pc9801_state>();
2126		offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
	2150	offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
2127	2151	& 0xFF0000;
2128	2152
2129		return space->read_byte(page_offset + offset);
	2153	return space.read_byte(page_offset + offset);
2130	2154	}
2131	2155
2132	2156
2133		static WRITE8_HANDLER( pc_dma_write_byte )
	2157	WRITE8_MEMBER(pc9801_state::pc_dma_write_byte)
2134	2158	{
2135		pc9801_state *state = space->machine().driver_data<pc9801_state>();
2136		offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
	2159	offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
2137	2160	& 0xFF0000;
2138	2161
2139		space->write_byte(page_offset + offset, data);
	2162	space.write_byte(page_offset + offset, data);
2140	2163	}
2141	2164
2142	2165	static void set_dma_channel(device_t *device, int channel, int state)
r14844	r14845
2166	2189	{
2167	2190	DEVCB_LINE(pc_dma_hrq_changed),
2168	2191	DEVCB_NULL,
2169		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
2170		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
	2192	DEVCB_DRIVER_MEMBER(pc9801_state, pc_dma_read_byte),
	2193	DEVCB_DRIVER_MEMBER(pc9801_state, pc_dma_write_byte),
2171	2194	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_HANDLER(test_r) },
2172	2195	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_HANDLER(test_w) },
2173	2196	{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }

src/mess/drivers/mz2000.c

r14844	r14845
51	51	UINT8 m_color_mode;
52	52	UINT8 m_has_fdc;
53	53	UINT8 m_hi_mode;
	54	DECLARE_READ8_MEMBER(mz2000_ipl_r);
	55	DECLARE_READ8_MEMBER(mz2000_wram_r);
	56	DECLARE_WRITE8_MEMBER(mz2000_wram_w);
	57	DECLARE_READ8_MEMBER(mz2000_tvram_r);
	58	DECLARE_WRITE8_MEMBER(mz2000_tvram_w);
	59	DECLARE_READ8_MEMBER(mz2000_gvram_r);
	60	DECLARE_WRITE8_MEMBER(mz2000_gvram_w);
	61	DECLARE_READ8_MEMBER(mz2000_mem_r);
	62	DECLARE_WRITE8_MEMBER(mz2000_mem_w);
	63	DECLARE_WRITE8_MEMBER(mz2000_gvram_bank_w);
	64	DECLARE_WRITE8_MEMBER(mz2000_fdc_w);
	65	DECLARE_WRITE8_MEMBER(timer_w);
	66	DECLARE_WRITE8_MEMBER(mz2000_tvram_attr_w);
	67	DECLARE_WRITE8_MEMBER(mz2000_gvram_mask_w);
54	68	};
55	69
56	70	static VIDEO_START( mz2000 )
r14844	r14845
154	168	return 0;
155	169	}
156	170
157		static READ8_HANDLER( mz2000_ipl_r )
	171	READ8_MEMBER(mz2000_state::mz2000_ipl_r)
158	172	{
159		UINT8 *ipl = space->machine().region("ipl")->base();
	173	UINT8 *ipl = machine().region("ipl")->base();
160	174
161	175	return ipl[offset];
162	176	}
163	177
164		static READ8_HANDLER( mz2000_wram_r )
	178	READ8_MEMBER(mz2000_state::mz2000_wram_r)
165	179	{
166		UINT8 *wram = space->machine().region("wram")->base();
	180	UINT8 *wram = machine().region("wram")->base();
167	181
168	182	return wram[offset];
169	183	}
170	184
171		static WRITE8_HANDLER( mz2000_wram_w )
	185	WRITE8_MEMBER(mz2000_state::mz2000_wram_w)
172	186	{
173		UINT8 *wram = space->machine().region("wram")->base();
	187	UINT8 *wram = machine().region("wram")->base();
174	188
175	189	wram[offset] = data;
176	190	}
177	191
178		static READ8_HANDLER( mz2000_tvram_r )
	192	READ8_MEMBER(mz2000_state::mz2000_tvram_r)
179	193	{
180		UINT8 *tvram = space->machine().region("tvram")->base();
	194	UINT8 *tvram = machine().region("tvram")->base();
181	195
182	196	return tvram[offset];
183	197	}
184	198
185		static WRITE8_HANDLER( mz2000_tvram_w )
	199	WRITE8_MEMBER(mz2000_state::mz2000_tvram_w)
186	200	{
187		UINT8 *tvram = space->machine().region("tvram")->base();
	201	UINT8 *tvram = machine().region("tvram")->base();
188	202
189	203	tvram[offset] = data;
190	204	}
191	205
192		static READ8_HANDLER( mz2000_gvram_r )
	206	READ8_MEMBER(mz2000_state::mz2000_gvram_r)
193	207	{
194		mz2000_state *state = space->machine().driver_data<mz2000_state>();
195		UINT8 *gvram = space->machine().region("gvram")->base();
	208	UINT8 *gvram = machine().region("gvram")->base();
196	209
197		return gvram[offset+state->m_gvram_bank*0x4000];
	210	return gvram[offset+m_gvram_bank*0x4000];
198	211	}
199	212
200		static WRITE8_HANDLER( mz2000_gvram_w )
	213	WRITE8_MEMBER(mz2000_state::mz2000_gvram_w)
201	214	{
202		mz2000_state *state = space->machine().driver_data<mz2000_state>();
203		UINT8 *gvram = space->machine().region("gvram")->base();
	215	UINT8 *gvram = machine().region("gvram")->base();
204	216
205		gvram[offset+state->m_gvram_bank*0x4000] = data;
	217	gvram[offset+m_gvram_bank*0x4000] = data;
206	218	}
207	219
208	220
209		static READ8_HANDLER( mz2000_mem_r )
	221	READ8_MEMBER(mz2000_state::mz2000_mem_r)
210	222	{
211		mz2000_state *state = space->machine().driver_data<mz2000_state>();
212	223	UINT8 page_mem;
213	224
214	225	page_mem = (offset & 0xf000) >> 12;
215	226
216		if(page_mem == 0 && state->m_ipl_enable)
	227	if(page_mem == 0 && m_ipl_enable)
217	228	return mz2000_ipl_r(space,offset & 0xfff);
218	229
219		if(((page_mem & 8) == 0) && state->m_ipl_enable == 0) // if ipl is enabled, 0x1000 - 0x7fff accesses to dummy region
	230	if(((page_mem & 8) == 0) && m_ipl_enable == 0) // if ipl is enabled, 0x1000 - 0x7fff accesses to dummy region
220	231	return mz2000_wram_r(space,offset);
221	232
222	233	if(page_mem & 8)
223	234	{
224		if(page_mem == 0xd && state->m_tvram_enable)
	235	if(page_mem == 0xd && m_tvram_enable)
225	236	return mz2000_tvram_r(space,offset & 0xfff);
226		else if(page_mem >= 0xc && state->m_gvram_enable)
	237	else if(page_mem >= 0xc && m_gvram_enable)
227	238	return mz2000_gvram_r(space,offset & 0x3fff);
228	239	else
229	240	{
230		UINT16 wram_mask = (state->m_ipl_enable) ? 0x7fff : 0xffff;
	241	UINT16 wram_mask = (m_ipl_enable) ? 0x7fff : 0xffff;
231	242	return mz2000_wram_r(space,offset & wram_mask);
232	243	}
233	244	}
r14844	r14845
235	246	return 0xff;
236	247	}
237	248
238		static WRITE8_HANDLER( mz2000_mem_w )
	249	WRITE8_MEMBER(mz2000_state::mz2000_mem_w)
239	250	{
240		mz2000_state *state = space->machine().driver_data<mz2000_state>();
241	251	UINT8 page_mem;
242	252
243	253	page_mem = (offset & 0xf000) >> 12;
244	254
245		if((page_mem & 8) == 0 && state->m_ipl_enable == 0)
	255	if((page_mem & 8) == 0 && m_ipl_enable == 0)
246	256	mz2000_wram_w(space,offset,data);
247	257
248	258	if(page_mem & 8)
249	259	{
250		if(page_mem == 0xd && state->m_tvram_enable)
	260	if(page_mem == 0xd && m_tvram_enable)
251	261	mz2000_tvram_w(space,offset & 0xfff,data);
252		else if(page_mem >= 0xc && state->m_gvram_enable)
	262	else if(page_mem >= 0xc && m_gvram_enable)
253	263	mz2000_gvram_w(space,offset & 0x3fff,data);
254	264	else
255	265	{
256		UINT16 wram_mask = (state->m_ipl_enable) ? 0x7fff : 0xffff;
	266	UINT16 wram_mask = (m_ipl_enable) ? 0x7fff : 0xffff;
257	267
258	268	mz2000_wram_w(space,offset & wram_mask,data);
259	269	}
260	270	}
261	271	}
262	272
263		static WRITE8_HANDLER( mz2000_gvram_bank_w )
	273	WRITE8_MEMBER(mz2000_state::mz2000_gvram_bank_w)
264	274	{
265		mz2000_state *state = space->machine().driver_data<mz2000_state>();
266	275
267		state->m_gvram_bank = data & 3;
	276	m_gvram_bank = data & 3;
268	277	}
269	278
270	279	static READ8_DEVICE_HANDLER( mz2000_wd17xx_r )
r14844	r14845
285	294	wd17xx_w(device, offset, data ^ 0xff);
286	295	}
287	296
288		static WRITE8_HANDLER( mz2000_fdc_w )
	297	WRITE8_MEMBER(mz2000_state::mz2000_fdc_w)
289	298	{
290		device_t* dev = space->machine().device("mb8877a");
	299	device_t* dev = machine().device("mb8877a");
291	300
292	301	switch(offset+0xdc)
293	302	{
294	303	case 0xdc:
295	304	wd17xx_set_drive(dev,data & 3);
296		floppy_mon_w(floppy_get_device(space->machine(), data & 3), (data & 0x80) ? CLEAR_LINE : ASSERT_LINE);
297		floppy_drive_set_ready_state(floppy_get_device(space->machine(), data & 3), 1,0);
	305	floppy_mon_w(floppy_get_device(machine(), data & 3), (data & 0x80) ? CLEAR_LINE : ASSERT_LINE);
	306	floppy_drive_set_ready_state(floppy_get_device(machine(), data & 3), 1,0);
298	307	break;
299	308	case 0xdd:
300	309	wd17xx_set_side(dev,(data & 1));
r14844	r14845
302	311	}
303	312	}
304	313
305		static WRITE8_HANDLER( timer_w )
	314	WRITE8_MEMBER(mz2000_state::timer_w)
306	315	{
307		device_t *pit8253 = space->machine().device("pit");
	316	device_t *pit8253 = machine().device("pit");
308	317
309	318	pit8253_gate0_w(pit8253, 1);
310	319	pit8253_gate1_w(pit8253, 1);
r14844	r14845
314	323	pit8253_gate1_w(pit8253, 1);
315	324	}
316	325
317		static WRITE8_HANDLER( mz2000_tvram_attr_w )
	326	WRITE8_MEMBER(mz2000_state::mz2000_tvram_attr_w)
318	327	{
319		mz2000_state *state = space->machine().driver_data<mz2000_state>();
320		state->m_tvram_attr = data;
	328	m_tvram_attr = data;
321	329	}
322	330
323		static WRITE8_HANDLER( mz2000_gvram_mask_w )
	331	WRITE8_MEMBER(mz2000_state::mz2000_gvram_mask_w)
324	332	{
325		mz2000_state *state = space->machine().driver_data<mz2000_state>();
326		state->m_gvram_mask = data;
	333	m_gvram_mask = data;
327	334	}
328	335
329	336	static ADDRESS_MAP_START(mz2000_map, AS_PROGRAM, 8, mz2000_state )
330	337	ADDRESS_MAP_UNMAP_HIGH
331		AM_RANGE( 0x0000, 0xffff ) AM_READWRITE_LEGACY(mz2000_mem_r,mz2000_mem_w)
	338	AM_RANGE( 0x0000, 0xffff ) AM_READWRITE(mz2000_mem_r,mz2000_mem_w)
332	339	ADDRESS_MAP_END
333	340
334	341	static ADDRESS_MAP_START(mz2000_io, AS_IO, 8, mz2000_state )
335	342	ADDRESS_MAP_UNMAP_HIGH
336	343	ADDRESS_MAP_GLOBAL_MASK(0xff)
337	344	AM_RANGE(0xd8, 0xdb) AM_DEVREADWRITE_LEGACY("mb8877a", mz2000_wd17xx_r, mz2000_wd17xx_w)
338		AM_RANGE(0xdc, 0xdd) AM_WRITE_LEGACY(mz2000_fdc_w)
	345	AM_RANGE(0xdc, 0xdd) AM_WRITE(mz2000_fdc_w)
339	346	AM_RANGE(0xe0, 0xe3) AM_DEVREADWRITE("i8255_0", i8255_device, read, write)
340	347	AM_RANGE(0xe4, 0xe7) AM_DEVREADWRITE_LEGACY("pit", pit8253_r, pit8253_w)
341	348	AM_RANGE(0xe8, 0xeb) AM_DEVREADWRITE_LEGACY("z80pio_1", z80pio_ba_cd_r, z80pio_ba_cd_w)
342		AM_RANGE(0xf0, 0xf3) AM_WRITE_LEGACY(timer_w)
	349	AM_RANGE(0xf0, 0xf3) AM_WRITE(timer_w)
343	350	//  AM_RANGE(0xf4, 0xf7) CRTC
344		AM_RANGE(0xf5, 0xf5) AM_WRITE_LEGACY(mz2000_tvram_attr_w)
345		AM_RANGE(0xf6, 0xf6) AM_WRITE_LEGACY(mz2000_gvram_mask_w)
346		AM_RANGE(0xf7, 0xf7) AM_WRITE_LEGACY(mz2000_gvram_bank_w)
	351	AM_RANGE(0xf5, 0xf5) AM_WRITE(mz2000_tvram_attr_w)
	352	AM_RANGE(0xf6, 0xf6) AM_WRITE(mz2000_gvram_mask_w)
	353	AM_RANGE(0xf7, 0xf7) AM_WRITE(mz2000_gvram_bank_w)
347	354	ADDRESS_MAP_END
348	355
349	356

src/mess/drivers/osbexec.c

r14844	r14845
102	102	else
103	103	device_set_input_line( m_maincpu, 0, CLEAR_LINE );
104	104	}
	105	DECLARE_WRITE8_MEMBER(osbexec_0000_w);
	106	DECLARE_READ8_MEMBER(osbexec_c000_r);
	107	DECLARE_WRITE8_MEMBER(osbexec_c000_w);
	108	DECLARE_READ8_MEMBER(osbexec_kbd_r);
	109	DECLARE_READ8_MEMBER(osbexec_rtc_r);
105	110	};
106	111
107	112
108		static WRITE8_HANDLER( osbexec_0000_w )
	113	WRITE8_MEMBER(osbexec_state::osbexec_0000_w)
109	114	{
110		osbexec_state *state = space->machine().driver_data<osbexec_state>();
111	115
112	116	/* Font RAM writing is enabled when ROM bank is enabled */
113		if ( state->m_pia0_porta & 0x80 )
	117	if ( m_pia0_porta & 0x80 )
114	118	{
115	119	if ( offset < 0x1000 )
116		state->m_fontram[ offset ] = data;
	120	m_fontram[ offset ] = data;
117	121	}
118	122	else
119	123	{
120		state->m_ram_0000[ offset ] = data;
	124	m_ram_0000[ offset ] = data;
121	125	}
122	126	}
123	127
124	128
125		static READ8_HANDLER( osbexec_c000_r )
	129	READ8_MEMBER(osbexec_state::osbexec_c000_r)
126	130	{
127		osbexec_state *state = space->machine().driver_data<osbexec_state>();
128		UINT8   data = state->m_ram_c000[offset];
	131	UINT8   data = m_ram_c000[offset];
129	132
130		if ( ( state->m_pia0_porta & 0x40 ) && offset < 0x1000 )
	133	if ( ( m_pia0_porta & 0x40 ) && offset < 0x1000 )
131	134	{
132		state->m_temp_attr = state->m_ram_c000[ 0x1000 + offset ];
	135	m_temp_attr = m_ram_c000[ 0x1000 + offset ];
133	136	}
134	137
135	138	return data;
136	139	}
137	140
138	141
139		static WRITE8_HANDLER( osbexec_c000_w )
	142	WRITE8_MEMBER(osbexec_state::osbexec_c000_w)
140	143	{
141		osbexec_state *state = space->machine().driver_data<osbexec_state>();
142	144
143		state->m_ram_c000[offset] = data;
	145	m_ram_c000[offset] = data;
144	146
145		if ( ( state->m_pia0_porta & 0x40 ) && offset < 0x1000 )
	147	if ( ( m_pia0_porta & 0x40 ) && offset < 0x1000 )
146	148	{
147		state->m_ram_c000[ 0x1000 + offset ] = state->m_temp_attr;
	149	m_ram_c000[ 0x1000 + offset ] = m_temp_attr;
148	150	}
149	151	}
150	152
151	153
152		static READ8_HANDLER( osbexec_kbd_r )
	154	READ8_MEMBER(osbexec_state::osbexec_kbd_r)
153	155	{
154	156	UINT8 data = 0xFF;
155	157
156	158	if ( offset & 0x0100 )
157		data &= input_port_read( space->machine(), "ROW0" );
	159	data &= input_port_read( machine(), "ROW0" );
158	160
159	161	if ( offset & 0x0200 )
160		data &= input_port_read( space->machine(), "ROW1" );
	162	data &= input_port_read( machine(), "ROW1" );
161	163
162	164	if ( offset & 0x0400 )
163		data &= input_port_read( space->machine(), "ROW2" );
	165	data &= input_port_read( machine(), "ROW2" );
164	166
165	167	if ( offset & 0x0800 )
166		data &= input_port_read( space->machine(), "ROW3" );
	168	data &= input_port_read( machine(), "ROW3" );
167	169
168	170	if ( offset & 0x1000 )
169		data &= input_port_read( space->machine(), "ROW4" );
	171	data &= input_port_read( machine(), "ROW4" );
170	172
171	173	if ( offset & 0x2000 )
172		data &= input_port_read( space->machine(), "ROW5" );
	174	data &= input_port_read( machine(), "ROW5" );
173	175
174	176	if ( offset & 0x4000 )
175		data &= input_port_read( space->machine(), "ROW6" );
	177	data &= input_port_read( machine(), "ROW6" );
176	178
177	179	if ( offset & 0x8000 )
178		data &= input_port_read( space->machine(), "ROW7" );
	180	data &= input_port_read( machine(), "ROW7" );
179	181
180	182	return data;
181	183	}
182	184
183	185
184		static READ8_HANDLER( osbexec_rtc_r )
	186	READ8_MEMBER(osbexec_state::osbexec_rtc_r)
185	187	{
186		osbexec_state *state = space->machine().driver_data<osbexec_state>();
187	188
188		return state->m_rtc;
	189	return m_rtc;
189	190	}
190	191
191	192
192	193	static ADDRESS_MAP_START( osbexec_mem, AS_PROGRAM, 8, osbexec_state )
193		AM_RANGE( 0x0000, 0x1FFF ) AM_READ_BANK("0000") AM_WRITE_LEGACY(osbexec_0000_w )   /* ROM and maybe also banked ram */
	194	AM_RANGE( 0x0000, 0x1FFF ) AM_READ_BANK("0000") AM_WRITE(osbexec_0000_w )   /* ROM and maybe also banked ram */
194	195	AM_RANGE( 0x2000, 0x3FFF ) AM_RAMBANK("2000")                        /* Banked RAM */
195	196	AM_RANGE( 0x4000, 0xBFFF ) AM_RAMBANK("4000")                        /* Banked RAM */
196		AM_RANGE( 0xC000, 0xDFFF ) AM_READWRITE_LEGACY(osbexec_c000_r, osbexec_c000_w )   /* Video ram / Banked RAM */
	197	AM_RANGE( 0xC000, 0xDFFF ) AM_READWRITE(osbexec_c000_r, osbexec_c000_w )   /* Video ram / Banked RAM */
197	198	AM_RANGE( 0xE000, 0xEFFF ) AM_RAMBANK("e000")                        /* Banked RAM */
198	199	AM_RANGE( 0xF000, 0xFFFF ) AM_RAM                                 /* 4KB of non-banked RAM for system stack etc */
199	200	ADDRESS_MAP_END
r14844	r14845
206	207	AM_RANGE( 0x08, 0x0B ) AM_MIRROR( 0xff00 ) AM_DEVREADWRITE_LEGACY("mb8877", wd17xx_r, wd17xx_w )            /* MB8877 @ UB17 input clock = 1MHz */
207	208	AM_RANGE( 0x0C, 0x0F ) AM_MIRROR( 0xff00 ) AM_DEVREADWRITE_LEGACY("sio", z80dart_ba_cd_r, z80dart_ba_cd_w )   /* SIO @ UD4 */
208	209	AM_RANGE( 0x10, 0x13 ) AM_MIRROR( 0xff00 ) AM_DEVREADWRITE( "pia_1", pia6821_device, read, write)            /* 6821 PIA @ UD8 */
209		AM_RANGE( 0x14, 0x17 ) AM_MIRROR( 0xff00 ) AM_MASK( 0xff00 ) AM_READ_LEGACY(osbexec_kbd_r )               /* KBD */
210		AM_RANGE( 0x18, 0x1b ) AM_MIRROR( 0xff00 ) AM_READ_LEGACY(osbexec_rtc_r )                              /* "RTC" @ UE13/UF13 */
	210	AM_RANGE( 0x14, 0x17 ) AM_MIRROR( 0xff00 ) AM_MASK( 0xff00 ) AM_READ(osbexec_kbd_r )               /* KBD */
	211	AM_RANGE( 0x18, 0x1b ) AM_MIRROR( 0xff00 ) AM_READ(osbexec_rtc_r )                              /* "RTC" @ UE13/UF13 */
211	212	/* ?? - vid ? */
212	213	ADDRESS_MAP_END
213	214

src/mess/drivers/pc88va.c

r14844	r14845
71	71	UINT8 m_i8255_1_pc;
72	72	UINT8 m_fdc_mode;
73	73	UINT8 m_fdc_irq_opcode;
	74	DECLARE_READ16_MEMBER(sys_mem_r);
	75	DECLARE_WRITE16_MEMBER(sys_mem_w);
	76	DECLARE_READ8_MEMBER(idp_status_r);
	77	DECLARE_WRITE8_MEMBER(idp_command_w);
	78	DECLARE_WRITE8_MEMBER(idp_param_w);
	79	DECLARE_WRITE16_MEMBER(palette_ram_w);
	80	DECLARE_READ16_MEMBER(sys_port4_r);
	81	DECLARE_READ16_MEMBER(bios_bank_r);
	82	DECLARE_WRITE16_MEMBER(bios_bank_w);
	83	DECLARE_READ8_MEMBER(rom_bank_r);
	84	DECLARE_READ8_MEMBER(key_r);
	85	DECLARE_WRITE16_MEMBER(backupram_wp_1_w);
	86	DECLARE_WRITE16_MEMBER(backupram_wp_0_w);
	87	DECLARE_READ8_MEMBER(hdd_status_r);
	88	DECLARE_WRITE8_MEMBER(upd765_mc_w);
	89	DECLARE_READ8_MEMBER(upd765_tc_r);
	90	DECLARE_READ8_MEMBER(pc88va_fdc_r);
	91	DECLARE_WRITE8_MEMBER(pc88va_fdc_w);
	92	DECLARE_READ16_MEMBER(sysop_r);
	93	DECLARE_READ16_MEMBER(screen_ctrl_r);
	94	DECLARE_WRITE16_MEMBER(screen_ctrl_w);
	95	DECLARE_WRITE8_MEMBER(timer3_ctrl_reg_w);
	96	DECLARE_WRITE16_MEMBER(video_pri_w);
	97	DECLARE_READ8_MEMBER(backupram_dsw_r);
	98	DECLARE_WRITE8_MEMBER(sys_port1_w);
	99	DECLARE_WRITE8_MEMBER(fdc_irq_vector_w);
74	100	};
75	101
76	102
r14844	r14845
428	454	return 0;
429	455	}
430	456
431		static READ16_HANDLER( sys_mem_r )
	457	READ16_MEMBER(pc88va_state::sys_mem_r)
432	458	{
433		pc88va_state *state = space->machine().driver_data<pc88va_state>();
434		switch((state->m_bank_reg & 0xf00) >> 8)
	459	switch((m_bank_reg & 0xf00) >> 8)
435	460	{
436	461	case 0: // select bus slot
437	462	return 0xffff;
438	463	case 1: // TVRAM
439	464	{
440		UINT16 *tvram = (UINT16 *)(*space->machine().region("tvram"));
	465	UINT16 *tvram = (UINT16 *)(*machine().region("tvram"));
441	466
442	467	if(((offset*2) & 0x30000) == 0)
443	468	return tvram[offset];
r14844	r14845
446	471	}
447	472	case 4:
448	473	{
449		UINT16 *gvram = (UINT16 *)(*space->machine().region("gvram"));
	474	UINT16 *gvram = (UINT16 *)(*machine().region("gvram"));
450	475
451	476	return gvram[offset];
452	477	}
453	478	case 8: // kanji ROM
454	479	case 9:
455	480	{
456		UINT16 *knj_ram = (UINT16 *)(*space->machine().region("kanji"));
	481	UINT16 *knj_ram = (UINT16 *)(*machine().region("kanji"));
457	482	UINT32 knj_offset;
458	483
459		knj_offset = (offset + (((state->m_bank_reg & 0x100) >> 8)*0x20000));
	484	knj_offset = (offset + (((m_bank_reg & 0x100) >> 8)*0x20000));
460	485
461	486	/* 0x00000 - 0x3ffff Kanji ROM 1*/
462	487	/* 0x40000 - 0x4ffff Kanji ROM 2*/
r14844	r14845
469	494	case 0xc: // Dictionary ROM
470	495	case 0xd:
471	496	{
472		UINT16 *dic_rom = (UINT16 *)(*space->machine().region("dictionary"));
	497	UINT16 *dic_rom = (UINT16 *)(*machine().region("dictionary"));
473	498	UINT32 dic_offset;
474	499
475		dic_offset = (offset + (((state->m_bank_reg & 0x100) >> 8)*0x20000));
	500	dic_offset = (offset + (((m_bank_reg & 0x100) >> 8)*0x20000));
476	501
477	502	return dic_rom[dic_offset];
478	503	}
r14844	r14845
481	506	return 0xffff;
482	507	}
483	508
484		static WRITE16_HANDLER( sys_mem_w )
	509	WRITE16_MEMBER(pc88va_state::sys_mem_w)
485	510	{
486		pc88va_state *state = space->machine().driver_data<pc88va_state>();
487		switch((state->m_bank_reg & 0xf00) >> 8)
	511	switch((m_bank_reg & 0xf00) >> 8)
488	512	{
489	513	case 0: // select bus slot
490	514	break;
491	515	case 1: // TVRAM
492	516	{
493		UINT16 *tvram = (UINT16 *)(*space->machine().region("tvram"));
	517	UINT16 *tvram = (UINT16 *)(*machine().region("tvram"));
494	518
495	519	if(((offset*2) & 0x30000) == 0)
496	520	COMBINE_DATA(&tvram[offset]);
r14844	r14845
498	522	break;
499	523	case 4: // TVRAM
500	524	{
501		UINT16 *gvram = (UINT16 *)(*space->machine().region("gvram"));
	525	UINT16 *gvram = (UINT16 *)(*machine().region("gvram"));
502	526
503	527	COMBINE_DATA(&gvram[offset]);
504	528	}
r14844	r14845
506	530	case 8: // kanji ROM, backup RAM at 0xb0000 - 0xb3fff
507	531	case 9:
508	532	{
509		UINT16 *knj_ram = (UINT16 *)(*space->machine().region("kanji"));
	533	UINT16 *knj_ram = (UINT16 *)(*machine().region("kanji"));
510	534	UINT32 knj_offset;
511	535
512		knj_offset = ((offset) + (((state->m_bank_reg & 0x100) >> 8)*0x20000));
	536	knj_offset = ((offset) + (((m_bank_reg & 0x100) >> 8)*0x20000));
513	537
514	538	if(knj_offset >= 0x50000/2 && knj_offset <= 0x53fff/2) // TODO: there's an area that can be write protected
515	539	{
516	540	COMBINE_DATA(&knj_ram[knj_offset]);
517		gfx_element_mark_dirty(space->machine().gfx[0], (knj_offset * 2) / 8);
518		gfx_element_mark_dirty(space->machine().gfx[1], (knj_offset * 2) / 32);
	541	gfx_element_mark_dirty(machine().gfx[0], (knj_offset * 2) / 8);
	542	gfx_element_mark_dirty(machine().gfx[1], (knj_offset * 2) / 32);
519	543	}
520	544	}
521	545	break;
r14844	r14845
531	555	static ADDRESS_MAP_START( pc88va_map, AS_PROGRAM, 16, pc88va_state )
532	556	AM_RANGE(0x00000, 0x7ffff) AM_RAM
533	557	//  AM_RANGE(0x80000, 0x9ffff) AM_RAM // EMM
534		AM_RANGE(0xa0000, 0xdffff) AM_READWRITE_LEGACY(sys_mem_r,sys_mem_w)
	558	AM_RANGE(0xa0000, 0xdffff) AM_READWRITE(sys_mem_r,sys_mem_w)
535	559	AM_RANGE(0xe0000, 0xeffff) AM_ROMBANK("rom00_bank")
536	560	AM_RANGE(0xf0000, 0xfffff) AM_ROMBANK("rom10_bank")
537	561	ADDRESS_MAP_END
538	562
539		static READ8_HANDLER( idp_status_r )
	563	READ8_MEMBER(pc88va_state::idp_status_r)
540	564	{
541	565	/*
542	566	x--- ---- LP   Light-pen signal detection (with VA use failure)
r14844	r14845
566	590	#define SPRSW  0x85
567	591	#define SPROV  0x81
568	592
569		static WRITE8_HANDLER( idp_command_w )
	593	WRITE8_MEMBER(pc88va_state::idp_command_w)
570	594	{
571		pc88va_state *state = space->machine().driver_data<pc88va_state>();
572	595	switch(data)
573	596	{
574	597	/* 0x10 - SYNC: sets CRTC values */
575		case SYNC:   state->m_cmd = SYNC;  state->m_buf_size = 14; state->m_buf_index = 0; break;
	598	case SYNC:   m_cmd = SYNC;  m_buf_size = 14; m_buf_index = 0; break;
576	599
577	600	/* 0x12 - DSPON: set DiSPlay ON and set up tvram table vreg */
578		case DSPON:  state->m_cmd = DSPON; state->m_buf_size = 3;  state->m_buf_index = 0; break;
	601	case DSPON:  m_cmd = DSPON; m_buf_size = 3;  m_buf_index = 0; break;
579	602
580	603	/* 0x13 - DSPOFF: set DiSPlay OFF */
581		case DSPOFF: state->m_cmd = DSPOFF; state->m_tsp.disp_on = 0; break;
	604	case DSPOFF: m_cmd = DSPOFF; m_tsp.disp_on = 0; break;
582	605
583	606	/* 0x14 - DSPDEF: set DiSPlay DEFinitions */
584		case DSPDEF: state->m_cmd = DSPDEF; state->m_buf_size = 6; state->m_buf_index = 0; break;
	607	case DSPDEF: m_cmd = DSPDEF; m_buf_size = 6; m_buf_index = 0; break;
585	608
586	609	/* 0x15 - CURDEF: set CURsor DEFinition */
587		case CURDEF: state->m_cmd = CURDEF; state->m_buf_size = 1; state->m_buf_index = 0; break;
	610	case CURDEF: m_cmd = CURDEF; m_buf_size = 1; m_buf_index = 0; break;
588	611
589	612	/* 0x16 - ACTSCR: ??? */
590		case ACTSCR: state->m_cmd = ACTSCR; state->m_buf_size = 1; state->m_buf_index = 0; break;
	613	case ACTSCR: m_cmd = ACTSCR; m_buf_size = 1; m_buf_index = 0; break;
591	614
592	615	/* 0x15 - CURS: set CURSor position */
593		case CURS:   state->m_cmd = CURS;   state->m_buf_size = 4; state->m_buf_index = 0; break;
	616	case CURS:   m_cmd = CURS;   m_buf_size = 4; m_buf_index = 0; break;
594	617
595	618	/* 0x8c - EMUL: set 3301 EMULation */
596		case EMUL:   state->m_cmd = EMUL;   state->m_buf_size = 4; state->m_buf_index = 0; break;
	619	case EMUL:   m_cmd = EMUL;   m_buf_size = 4; m_buf_index = 0; break;
597	620
598	621	/* 0x88 - EXIT: ??? */
599		case EXIT:   state->m_cmd = EXIT; break;
	622	case EXIT:   m_cmd = EXIT; break;
600	623
601	624	/* 0x82 - SPRON: set SPRite ON */
602		case SPRON:  state->m_cmd = SPRON;  state->m_buf_size = 3; state->m_buf_index = 0; break;
	625	case SPRON:  m_cmd = SPRON;  m_buf_size = 3; m_buf_index = 0; break;
603	626
604	627	/* 0x83 - SPROFF: set SPRite OFF */
605		case SPROFF: state->m_cmd = SPROFF; state->m_tsp.spr_on = 0; break;
	628	case SPROFF: m_cmd = SPROFF; m_tsp.spr_on = 0; break;
606	629
607	630	/* 0x85 - SPRSW: ??? */
608		case SPRSW:  state->m_cmd = SPRSW;  state->m_buf_size = 1; state->m_buf_index = 0; break;
	631	case SPRSW:  m_cmd = SPRSW;  m_buf_size = 1; m_buf_index = 0; break;
609	632
610	633	/* 0x81 - SPROV: set SPRite OVerflow information */
611	634	/*
r14844	r14845
613	636	--x- ---- Sprite Collision flag
614	637	---x xxxx First sprite that caused Sprite Over event
615	638	*/
616		case SPROV:  state->m_cmd = SPROV; /* TODO: where it returns the info? */ break;
	639	case SPROV:  m_cmd = SPROV; /* TODO: where it returns the info? */ break;
617	640
618	641	/* TODO: 0x89 shouldn't trigger, should be one of the above commands */
619		default:   state->m_cmd = 0x00; printf("PC=%05x: Unknown IDP %02x cmd set\n",cpu_get_pc(&space->device()),data); break;
	642	default:   m_cmd = 0x00; printf("PC=%05x: Unknown IDP %02x cmd set\n",cpu_get_pc(&space.device()),data); break;
620	643	}
621	644	}
622	645
r14844	r14845
786	809	tsp_sprite_enable(machine, 0xa0000 + state->m_tsp.spr_offset + (state->m_buf_ram[0] & 0xf8), (state->m_buf_ram[0] & 2) << 8);
787	810	}
788	811
789		static WRITE8_HANDLER( idp_param_w )
	812	WRITE8_MEMBER(pc88va_state::idp_param_w)
790	813	{
791		pc88va_state *state = space->machine().driver_data<pc88va_state>();
792		if(state->m_cmd == DSPOFF || state->m_cmd == EXIT || state->m_cmd == SPROFF || state->m_cmd == SPROV) // no param commands
	814	if(m_cmd == DSPOFF || m_cmd == EXIT || m_cmd == SPROFF || m_cmd == SPROV) // no param commands
793	815	return;
794	816
795		state->m_buf_ram[state->m_buf_index] = data;
796		state->m_buf_index++;
	817	m_buf_ram[m_buf_index] = data;
	818	m_buf_index++;
797	819
798		if(state->m_buf_index >= state->m_buf_size)
	820	if(m_buf_index >= m_buf_size)
799	821	{
800		state->m_buf_index = 0;
801		switch(state->m_cmd)
	822	m_buf_index = 0;
	823	switch(m_cmd)
802	824	{
803		case SYNC:      execute_sync_cmd(space->machine());   break;
804		case DSPON:    execute_dspon_cmd(space->machine());   break;
805		case DSPDEF:   execute_dspdef_cmd(space->machine()); break;
806		case CURDEF:   execute_curdef_cmd(space->machine()); break;
807		case ACTSCR:   execute_actscr_cmd(space->machine()); break;
808		case CURS:      execute_curs_cmd(space->machine());   break;
809		case EMUL:      execute_emul_cmd(space->machine());   break;
810		case SPRON:      execute_spron_cmd(space->machine());  break;
811		case SPRSW:      execute_sprsw_cmd(space->machine());   break;
	825	case SYNC:      execute_sync_cmd(machine());   break;
	826	case DSPON:    execute_dspon_cmd(machine());   break;
	827	case DSPDEF:   execute_dspdef_cmd(machine()); break;
	828	case CURDEF:   execute_curdef_cmd(machine()); break;
	829	case ACTSCR:   execute_actscr_cmd(machine()); break;
	830	case CURS:      execute_curs_cmd(machine());   break;
	831	case EMUL:      execute_emul_cmd(machine());   break;
	832	case SPRON:      execute_spron_cmd(machine());  break;
	833	case SPRSW:      execute_sprsw_cmd(machine());   break;
812	834
813	835	default:
814	836	//printf("%02x\n",data);
r14844	r14845
817	839	}
818	840	}
819	841
820		static WRITE16_HANDLER( palette_ram_w )
	842	WRITE16_MEMBER(pc88va_state::palette_ram_w)
821	843	{
822		pc88va_state *state = space->machine().driver_data<pc88va_state>();
823	844	int r,g,b;
824		COMBINE_DATA(&state->m_palram[offset]);
	845	COMBINE_DATA(&m_palram[offset]);
825	846
826		b = (state->m_palram[offset] & 0x001e) >> 1;
827		r = (state->m_palram[offset] & 0x03c0) >> 6;
828		g = (state->m_palram[offset] & 0x7800) >> 11;
	847	b = (m_palram[offset] & 0x001e) >> 1;
	848	r = (m_palram[offset] & 0x03c0) >> 6;
	849	g = (m_palram[offset] & 0x7800) >> 11;
829	850
830		palette_set_color_rgb(space->machine(),offset,pal4bit(r),pal4bit(g),pal4bit(b));
	851	palette_set_color_rgb(machine(),offset,pal4bit(r),pal4bit(g),pal4bit(b));
831	852	}
832	853
833		static READ16_HANDLER( sys_port4_r )
	854	READ16_MEMBER(pc88va_state::sys_port4_r)
834	855	{
835	856	UINT8 vrtc,sw1;
836		vrtc = (space->machine().primary_screen->vpos() < 200) ? 0x20 : 0x00; // vblank
	857	vrtc = (machine().primary_screen->vpos() < 200) ? 0x20 : 0x00; // vblank
837	858
838		sw1 = (input_port_read(space->machine(), "DSW") & 1) ? 2 : 0;
	859	sw1 = (input_port_read(machine(), "DSW") & 1) ? 2 : 0;
839	860
840	861	return vrtc | sw1 | 0xc0;
841	862	}
842	863
843		static READ16_HANDLER( bios_bank_r )
	864	READ16_MEMBER(pc88va_state::bios_bank_r)
844	865	{
845		pc88va_state *state = space->machine().driver_data<pc88va_state>();
846		return state->m_bank_reg;
	866	return m_bank_reg;
847	867	}
848	868
849		static WRITE16_HANDLER( bios_bank_w )
	869	WRITE16_MEMBER(pc88va_state::bios_bank_w)
850	870	{
851		pc88va_state *state = space->machine().driver_data<pc88va_state>();
852	871	/*
853	872	-x-- ---- ---- ---- SMM (compatibility mode)
854	873	---x ---- ---- ---- GMSP (VRAM drawing Mode)
r14844	r14845
857	876	---- ---- ---- xxxx RBC0 (0xe0000 - 0xeffff ROM bank)
858	877	*/
859	878	if ((mem_mask&0xffff) == 0xffff)
860		state->m_bank_reg = data;
	879	m_bank_reg = data;
861	880	else if ((mem_mask & 0xffff) == 0xff00)
862		state->m_bank_reg = (data & 0xff00) | (state->m_bank_reg & 0x00ff);
	881	m_bank_reg = (data & 0xff00) | (m_bank_reg & 0x00ff);
863	882	else if ((mem_mask & 0xffff) == 0x00ff)
864		state->m_bank_reg = (data & 0x00ff) | (state->m_bank_reg & 0xff00);
	883	m_bank_reg = (data & 0x00ff) | (m_bank_reg & 0xff00);
865	884
866	885
867	886	/* RBC1 */
868	887	{
869		UINT8 *ROM10 = space->machine().region("rom10")->base();
	888	UINT8 *ROM10 = machine().region("rom10")->base();
870	889
871		if((state->m_bank_reg & 0xe0) == 0x00)
872		memory_set_bankptr(space->machine(), "rom10_bank", &ROM10[(state->m_bank_reg & 0x10) ? 0x10000 : 0x00000]);
	890	if((m_bank_reg & 0xe0) == 0x00)
	891	memory_set_bankptr(machine(), "rom10_bank", &ROM10[(m_bank_reg & 0x10) ? 0x10000 : 0x00000]);
873	892	}
874	893
875	894	/* RBC0 */
876	895	{
877		UINT8 *ROM00 = space->machine().region("rom00")->base();
	896	UINT8 *ROM00 = machine().region("rom00")->base();
878	897
879		memory_set_bankptr(space->machine(), "rom00_bank", &ROM00[(state->m_bank_reg & 0xf)*0x10000]); // TODO: docs says that only 0 - 5 are used, dunno why ...
	898	memory_set_bankptr(machine(), "rom00_bank", &ROM00[(m_bank_reg & 0xf)*0x10000]); // TODO: docs says that only 0 - 5 are used, dunno why ...
880	899	}
881	900	}
882	901
883		static READ8_HANDLER( rom_bank_r )
	902	READ8_MEMBER(pc88va_state::rom_bank_r)
884	903	{
885	904	return 0xff; // bit 7 low is va91 rom bank status
886	905	}
887	906
888		static READ8_HANDLER( key_r )
	907	READ8_MEMBER(pc88va_state::key_r)
889	908	{
890	909	// note row C bit 2 does something at POST ... some kind of test mode?
891	910	static const char *const keynames[] = { "KEY0", "KEY1", "KEY2", "KEY3",
r14844	r14845
893	912	"KEY8", "KEY9", "KEYA", "KEYB",
894	913	"KEYC", "KEYD", "KEYE", "KEYF" };
895	914
896		return input_port_read(space->machine(), keynames[offset]);
	915	return input_port_read(machine(), keynames[offset]);
897	916	}
898	917
899		static WRITE16_HANDLER( backupram_wp_1_w )
	918	WRITE16_MEMBER(pc88va_state::backupram_wp_1_w)
900	919	{
901		pc88va_state *state = space->machine().driver_data<pc88va_state>();
902		state->m_backupram_wp = 1;
	920	m_backupram_wp = 1;
903	921	}
904	922
905		static WRITE16_HANDLER( backupram_wp_0_w )
	923	WRITE16_MEMBER(pc88va_state::backupram_wp_0_w)
906	924	{
907		pc88va_state *state = space->machine().driver_data<pc88va_state>();
908		state->m_backupram_wp = 0;
	925	m_backupram_wp = 0;
909	926	}
910	927
911		static READ8_HANDLER( hdd_status_r )
	928	READ8_MEMBER(pc88va_state::hdd_status_r)
912	929	{
913	930	return 0x20;
914	931	}
915	932
916		static WRITE8_HANDLER( upd765_mc_w )
	933	WRITE8_MEMBER(pc88va_state::upd765_mc_w)
917	934	{
918		floppy_mon_w(floppy_get_device(space->machine(), 0), (data & 1) ? CLEAR_LINE : ASSERT_LINE);
919		floppy_mon_w(floppy_get_device(space->machine(), 1), (data & 2) ? CLEAR_LINE : ASSERT_LINE);
920		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 0), (data & 1), 0);
921		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 1), (data & 2), 0);
	935	floppy_mon_w(floppy_get_device(machine(), 0), (data & 1) ? CLEAR_LINE : ASSERT_LINE);
	936	floppy_mon_w(floppy_get_device(machine(), 1), (data & 2) ? CLEAR_LINE : ASSERT_LINE);
	937	floppy_drive_set_ready_state(floppy_get_device(machine(), 0), (data & 1), 0);
	938	floppy_drive_set_ready_state(floppy_get_device(machine(), 1), (data & 2), 0);
922	939	}
923	940
924	941	static TIMER_CALLBACK( pc8801fd_upd765_tc_to_zero )
r14844	r14845
928	945	upd765_tc_w(machine.device("upd765"), 0);
929	946	}
930	947
931		static READ8_HANDLER( upd765_tc_r )
	948	READ8_MEMBER(pc88va_state::upd765_tc_r)
932	949	{
933		//pc88va_state *state = space->machine().driver_data<pc88va_state>();
934	950
935		upd765_tc_w(space->machine().device("upd765"), 1);
936		space->machine().scheduler().timer_set(attotime::from_usec(500), FUNC(pc8801fd_upd765_tc_to_zero));
	951	upd765_tc_w(machine().device("upd765"), 1);
	952	machine().scheduler().timer_set(attotime::from_usec(500), FUNC(pc8801fd_upd765_tc_to_zero));
937	953	return 0;
938	954	}
939	955
940		static READ8_HANDLER( pc88va_fdc_r )
	956	READ8_MEMBER(pc88va_state::pc88va_fdc_r)
941	957	{
942	958	switch(offset*2)
943	959	{
r14844	r14845
947	963	/* ---x ---- RDY: (0) Busy (1) Ready */
948	964	case 0x06: // FDC control port 2
949	965	return 0;
950		case 0x08: return upd765_status_r(space->machine().device("upd765"), 0);
951		case 0x0a: return upd765_data_r(space->machine().device("upd765"), 0);
	966	case 0x08: return upd765_status_r(machine().device("upd765"), 0);
	967	case 0x0a: return upd765_data_r(machine().device("upd765"), 0);
952	968	}
953	969
954	970	return 0xff;
955	971	}
956	972
957		static WRITE8_HANDLER( pc88va_fdc_w )
	973	WRITE8_MEMBER(pc88va_state::pc88va_fdc_w)
958	974	{
959		pc88va_state *state = space->machine().driver_data<pc88va_state>();
960	975	switch(offset*2)
961	976	{
962	977	/*
963	978	---- ---x MODE: FDC op mode (0) Intelligent (1) DMA
964	979	*/
965	980	case 0x00: // FDC mode register
966		state->m_fdc_mode = data & 1;
967		cputag_set_input_line(space->machine(), "fdccpu", INPUT_LINE_HALT, (state->m_fdc_mode) ? ASSERT_LINE : CLEAR_LINE);
	981	m_fdc_mode = data & 1;
	982	cputag_set_input_line(machine(), "fdccpu", INPUT_LINE_HALT, (m_fdc_mode) ? ASSERT_LINE : CLEAR_LINE);
968	983	break;
969	984	/*
970	985	--x- ---- CLK: FDC clock selection (0) 4.8MHz (1) 8 MHz
r14844	r14845
990	1005	printf("%02x\n",data);
991	1006	break; // FDC control port 2
992	1007	case 0x08: break; // UPD765 status
993		case 0x0a: upd765_data_w(space->machine().device("upd765"), 0,data); break;
	1008	case 0x0a: upd765_data_w(machine().device("upd765"), 0,data); break;
994	1009	}
995	1010	}
996	1011
997	1012
998		static READ16_HANDLER( sysop_r )
	1013	READ16_MEMBER(pc88va_state::sysop_r)
999	1014	{
1000	1015	UINT8 sys_op;
1001	1016
1002		sys_op = input_port_read(space->machine(), "SYSOP_SW") & 3;
	1017	sys_op = input_port_read(machine(), "SYSOP_SW") & 3;
1003	1018
1004	1019	return 0xfffc | sys_op; // docs says all the other bits are high
1005	1020	}
1006	1021
1007		static READ16_HANDLER( screen_ctrl_r )
	1022	READ16_MEMBER(pc88va_state::screen_ctrl_r)
1008	1023	{
1009		pc88va_state *state = space->machine().driver_data<pc88va_state>();
1010		return state->m_screen_ctrl_reg;
	1024	return m_screen_ctrl_reg;
1011	1025	}
1012	1026
1013		static WRITE16_HANDLER( screen_ctrl_w )
	1027	WRITE16_MEMBER(pc88va_state::screen_ctrl_w)
1014	1028	{
1015		pc88va_state *state = space->machine().driver_data<pc88va_state>();
1016		state->m_screen_ctrl_reg = data;
	1029	m_screen_ctrl_reg = data;
1017	1030	}
1018	1031
1019	1032	static TIMER_CALLBACK( t3_mouse_callback )
r14844	r14845
1026	1039	}
1027	1040	}
1028	1041
1029		static WRITE8_HANDLER( timer3_ctrl_reg_w )
	1042	WRITE8_MEMBER(pc88va_state::timer3_ctrl_reg_w)
1030	1043	{
1031		pc88va_state *state = space->machine().driver_data<pc88va_state>();
1032	1044	/*
1033	1045	x--- ---- MINTEN (TCU irq enable)
1034	1046	---- --xx general purpose timer 3 interval (120, 60, 30, 15)
1035	1047	*/
1036		state->m_timer3_io_reg = data;
	1048	m_timer3_io_reg = data;
1037	1049
1038	1050	if(data & 0x80)
1039		state->m_t3_mouse_timer->adjust(attotime::from_hz(120 >> (state->m_timer3_io_reg & 3)));
	1051	m_t3_mouse_timer->adjust(attotime::from_hz(120 >> (m_timer3_io_reg & 3)));
1040	1052	else
1041	1053	{
1042		pic8259_ir5_w(space->machine().device("pic8259_slave"), 0);
1043		state->m_t3_mouse_timer->adjust(attotime::never);
	1054	pic8259_ir5_w(machine().device("pic8259_slave"), 0);
	1055	m_t3_mouse_timer->adjust(attotime::never);
1044	1056	}
1045	1057	}
1046	1058
1047		static WRITE16_HANDLER( video_pri_w )
	1059	WRITE16_MEMBER(pc88va_state::video_pri_w)
1048	1060	{
1049		pc88va_state *state = space->machine().driver_data<pc88va_state>();
1050		COMBINE_DATA(&state->m_video_pri_reg[offset]);
	1061	COMBINE_DATA(&m_video_pri_reg[offset]);
1051	1062	}
1052	1063
1053		static READ8_HANDLER( backupram_dsw_r )
	1064	READ8_MEMBER(pc88va_state::backupram_dsw_r)
1054	1065	{
1055		UINT16 *knj_ram = (UINT16 *)(*space->machine().region("kanji"));
	1066	UINT16 *knj_ram = (UINT16 *)(*machine().region("kanji"));
1056	1067
1057	1068	if(offset == 0)
1058	1069	return knj_ram[(0x50000 + 0x1fc2) / 2] & 0xff;
r14844	r14845
1060	1071	return knj_ram[(0x50000 + 0x1fc6) / 2] & 0xff;
1061	1072	}
1062	1073
1063		static WRITE8_HANDLER( sys_port1_w )
	1074	WRITE8_MEMBER(pc88va_state::sys_port1_w)
1064	1075	{
1065	1076	// ...
1066	1077	}
1067	1078
1068	1079	static ADDRESS_MAP_START( pc88va_io_map, AS_IO, 16, pc88va_state )
1069		AM_RANGE(0x0000, 0x000f) AM_READ8_LEGACY(key_r,0xffff) // Keyboard ROW reading
	1080	AM_RANGE(0x0000, 0x000f) AM_READ8(key_r,0xffff) // Keyboard ROW reading
1070	1081	//  AM_RANGE(0x0010, 0x0010) Printer / Calendar Clock Interface
1071	1082	AM_RANGE(0x0020, 0x0021) AM_NOP // RS-232C
1072		AM_RANGE(0x0030, 0x0031) AM_READWRITE8_LEGACY(backupram_dsw_r,sys_port1_w,0xffff) // 0x30 (R) DSW1 (W) Text Control Port 0 / 0x31 (R) DSW2 (W) System Port 1
	1083	AM_RANGE(0x0030, 0x0031) AM_READWRITE8(backupram_dsw_r,sys_port1_w,0xffff) // 0x30 (R) DSW1 (W) Text Control Port 0 / 0x31 (R) DSW2 (W) System Port 1
1073	1084	//  AM_RANGE(0x0032, 0x0032) (R) ? (W) System Port 2
1074	1085	//  AM_RANGE(0x0034, 0x0034) GVRAM Control Port 1
1075	1086	//  AM_RANGE(0x0035, 0x0035) GVRAM Control Port 2
1076		AM_RANGE(0x0040, 0x0041) AM_READ_LEGACY(sys_port4_r) // (R) System Port 4 (W) System port 3 (strobe port)
	1087	AM_RANGE(0x0040, 0x0041) AM_READ(sys_port4_r) // (R) System Port 4 (W) System port 3 (strobe port)
1077	1088	AM_RANGE(0x0044, 0x0045) AM_MIRROR(0x0002) AM_DEVREADWRITE8_LEGACY("ym", ym2203_r,ym2203_w,0xffff)
1078	1089	//  AM_RANGE(0x005c, 0x005c) (R) GVRAM status
1079	1090	//  AM_RANGE(0x005c, 0x005f) (W) GVRAM selection
r14844	r14845
1081	1092	//  AM_RANGE(0x0071, 0x0071) Expansion ROM select (*)
1082	1093	//  AM_RANGE(0x0078, 0x0078) Memory offset increment (*)
1083	1094	//  AM_RANGE(0x0080, 0x0081) HDD related
1084		AM_RANGE(0x0082, 0x0083) AM_READ8_LEGACY(hdd_status_r,0x00ff)// HDD control, byte access 7-0
	1095	AM_RANGE(0x0082, 0x0083) AM_READ8(hdd_status_r,0x00ff)// HDD control, byte access 7-0
1085	1096	//  AM_RANGE(0x00bc, 0x00bf) d8255 1
1086	1097	//  AM_RANGE(0x00e2, 0x00e3) Expansion RAM selection (*)
1087	1098	//  AM_RANGE(0x00e4, 0x00e4) 8214 IRQ control (*)
r14844	r14845
1090	1101	//  AM_RANGE(0x00ec, 0x00ed) ? (*)
1091	1102	AM_RANGE(0x00fc, 0x00ff) AM_DEVREADWRITE8("d8255_2", i8255_device, read, write, 0xffff) // d8255 2, FDD
1092	1103
1093		AM_RANGE(0x0100, 0x0101) AM_READWRITE_LEGACY(screen_ctrl_r,screen_ctrl_w) // Screen Control Register
	1104	AM_RANGE(0x0100, 0x0101) AM_READWRITE(screen_ctrl_r,screen_ctrl_w) // Screen Control Register
1094	1105	//  AM_RANGE(0x0102, 0x0103) Graphic Screen Control Register
1095		AM_RANGE(0x0106, 0x0109) AM_WRITE_LEGACY(video_pri_w) // Palette Control Register (priority) / Direct Color Control Register (priority)
	1106	AM_RANGE(0x0106, 0x0109) AM_WRITE(video_pri_w) // Palette Control Register (priority) / Direct Color Control Register (priority)
1096	1107	//  AM_RANGE(0x010a, 0x010b) Picture Mask Mode Register
1097	1108	//  AM_RANGE(0x010c, 0x010d) Color Palette Mode Register
1098	1109	//  AM_RANGE(0x010e, 0x010f) Backdrop Color Register
r14844	r14845
1101	1112	//  AM_RANGE(0x0126, 0x0127) ? (related to Transparent Color of Graphic Screen 1)
1102	1113	//  AM_RANGE(0x012e, 0x012f) ? (related to Transparent Color of Text/Sprite)
1103	1114	//  AM_RANGE(0x0130, 0x0137) Picture Mask Parameter
1104		AM_RANGE(0x0142, 0x0143) AM_READWRITE8_LEGACY(idp_status_r,idp_command_w,0x00ff) //Text Controller (IDP) - (R) Status (W) command
1105		AM_RANGE(0x0146, 0x0147) AM_WRITE8_LEGACY(idp_param_w,0x00ff) //Text Controller (IDP) - (R/W) Parameter
	1115	AM_RANGE(0x0142, 0x0143) AM_READWRITE8(idp_status_r,idp_command_w,0x00ff) //Text Controller (IDP) - (R) Status (W) command
	1116	AM_RANGE(0x0146, 0x0147) AM_WRITE8(idp_param_w,0x00ff) //Text Controller (IDP) - (R/W) Parameter
1106	1117	//  AM_RANGE(0x0148, 0x0149) Text control port 1
1107	1118	//  AM_RANGE(0x014c, 0x014f) ? CG Port
1108		AM_RANGE(0x0150, 0x0151) AM_READ_LEGACY(sysop_r) // System Operational Mode
1109		AM_RANGE(0x0152, 0x0153) AM_READWRITE_LEGACY(bios_bank_r,bios_bank_w) // Memory Map Register
	1119	AM_RANGE(0x0150, 0x0151) AM_READ(sysop_r) // System Operational Mode
	1120	AM_RANGE(0x0152, 0x0153) AM_READWRITE(bios_bank_r,bios_bank_w) // Memory Map Register
1110	1121	//  AM_RANGE(0x0154, 0x0155) Refresh Register (wait states)
1111		AM_RANGE(0x0156, 0x0157) AM_READ8_LEGACY(rom_bank_r,0x00ff) // ROM bank status
	1122	AM_RANGE(0x0156, 0x0157) AM_READ8(rom_bank_r,0x00ff) // ROM bank status
1112	1123	//  AM_RANGE(0x0158, 0x0159) Interruption Mode Modification
1113	1124	//  AM_RANGE(0x015c, 0x015f) NMI mask port (strobe port)
1114	1125	//  AM_RANGE(0x0160, 0x016f) DMA Controller
r14844	r14845
1116	1127	AM_RANGE(0x0188, 0x018b) AM_DEVREADWRITE8_LEGACY("pic8259_master", pic8259_r, pic8259_w, 0x00ff) // ICU, also controls 8214 emulation
1117	1128	//  AM_RANGE(0x0190, 0x0191) System Port 5
1118	1129	//  AM_RANGE(0x0196, 0x0197) Keyboard sub CPU command port
1119		AM_RANGE(0x0198, 0x0199) AM_WRITE_LEGACY(backupram_wp_1_w) //Backup RAM write inhibit
1120		AM_RANGE(0x019a, 0x019b) AM_WRITE_LEGACY(backupram_wp_0_w) //Backup RAM write permission
	1130	AM_RANGE(0x0198, 0x0199) AM_WRITE(backupram_wp_1_w) //Backup RAM write inhibit
	1131	AM_RANGE(0x019a, 0x019b) AM_WRITE(backupram_wp_0_w) //Backup RAM write permission
1121	1132	AM_RANGE(0x01a0, 0x01a7) AM_DEVREADWRITE8_LEGACY("pit8253", pit8253_r, pit8253_w, 0x00ff)// vTCU (timer counter unit)
1122		AM_RANGE(0x01a8, 0x01a9) AM_WRITE8_LEGACY(timer3_ctrl_reg_w,0x00ff) // General-purpose timer 3 control port
1123		AM_RANGE(0x01b0, 0x01bb) AM_READWRITE8_LEGACY(pc88va_fdc_r,pc88va_fdc_w,0x00ff)// FDC related (765)
	1133	AM_RANGE(0x01a8, 0x01a9) AM_WRITE8(timer3_ctrl_reg_w,0x00ff) // General-purpose timer 3 control port
	1134	AM_RANGE(0x01b0, 0x01bb) AM_READWRITE8(pc88va_fdc_r,pc88va_fdc_w,0x00ff)// FDC related (765)
1124	1135	//  AM_RANGE(0x01c0, 0x01c1) ?
1125	1136	AM_RANGE(0x01c6, 0x01c7) AM_WRITENOP // ???
1126	1137	AM_RANGE(0x01c8, 0x01cf) AM_DEVREADWRITE8("d8255_3", i8255_device, read, write,0xff00) //i8255 3 (byte access)
r14844	r14845
1129	1140	AM_RANGE(0x0220, 0x023f) AM_RAM // Frame buffer 1 control parameter
1130	1141	AM_RANGE(0x0240, 0x025f) AM_RAM // Frame buffer 2 control parameter
1131	1142	AM_RANGE(0x0260, 0x027f) AM_RAM // Frame buffer 3 control parameter
1132		AM_RANGE(0x0300, 0x033f) AM_RAM_WRITE_LEGACY(palette_ram_w) AM_BASE(m_palram) // Palette RAM (xBBBBxRRRRxGGGG format)
	1143	AM_RANGE(0x0300, 0x033f) AM_RAM_WRITE(palette_ram_w) AM_BASE(m_palram) // Palette RAM (xBBBBxRRRRxGGGG format)
1133	1144
1134	1145	//  AM_RANGE(0x0500, 0x05ff) GVRAM
1135	1146	//  AM_RANGE(0x1000, 0xfeff) user area (???)
r14844	r14845
1143	1154	AM_RANGE(0x4000, 0x7fff) AM_RAM
1144	1155	ADDRESS_MAP_END
1145	1156
1146		static WRITE8_HANDLER( fdc_irq_vector_w )
	1157	WRITE8_MEMBER(pc88va_state::fdc_irq_vector_w)
1147	1158	{
1148		pc88va_state *state = space->machine().driver_data<pc88va_state>();
1149		state->m_fdc_irq_opcode = data;
	1159	m_fdc_irq_opcode = data;
1150	1160	}
1151	1161
1152	1162	static ADDRESS_MAP_START( pc88va_z80_io_map, AS_IO, 8, pc88va_state )
1153	1163	ADDRESS_MAP_GLOBAL_MASK(0xff)
1154		AM_RANGE(0xf0, 0xf0) AM_WRITE_LEGACY(fdc_irq_vector_w) // Interrupt Opcode Port
	1164	AM_RANGE(0xf0, 0xf0) AM_WRITE(fdc_irq_vector_w) // Interrupt Opcode Port
1155	1165	//  AM_RANGE(0xf4, 0xf4) // Drive Control Port
1156		AM_RANGE(0xf8, 0xf8) AM_READWRITE_LEGACY(upd765_tc_r,upd765_mc_w) // (R) Terminal Count Port (W) Motor Control Port
	1166	AM_RANGE(0xf8, 0xf8) AM_READWRITE(upd765_tc_r,upd765_mc_w) // (R) Terminal Count Port (W) Motor Control Port
1157	1167	AM_RANGE(0xfa, 0xfa) AM_DEVREAD_LEGACY("upd765", upd765_status_r )
1158	1168	AM_RANGE(0xfb, 0xfb) AM_DEVREADWRITE_LEGACY("upd765", upd765_data_r, upd765_data_w )
1159	1169	AM_RANGE(0xfc, 0xff) AM_DEVREADWRITE("d8255_2s", i8255_device, read, write)

src/mess/drivers/pc6001.c

r14844	r14845
176	176	UINT32 m_old_key1;
177	177	UINT32 m_old_key2;
178	178	UINT32 m_old_key3;
	179	DECLARE_WRITE8_MEMBER(pc6001_system_latch_w);
	180	DECLARE_READ8_MEMBER(nec_ppi8255_r);
	181	DECLARE_WRITE8_MEMBER(nec_ppi8255_w);
	182	DECLARE_WRITE8_MEMBER(pc6001m2_bank_r0_w);
	183	DECLARE_WRITE8_MEMBER(pc6001m2_bank_r1_w);
	184	DECLARE_WRITE8_MEMBER(pc6001m2_bank_w0_w);
	185	DECLARE_WRITE8_MEMBER(pc6001m2_opt_bank_w);
	186	DECLARE_WRITE8_MEMBER(work_ram0_w);
	187	DECLARE_WRITE8_MEMBER(work_ram1_w);
	188	DECLARE_WRITE8_MEMBER(work_ram2_w);
	189	DECLARE_WRITE8_MEMBER(work_ram3_w);
	190	DECLARE_WRITE8_MEMBER(work_ram4_w);
	191	DECLARE_WRITE8_MEMBER(work_ram5_w);
	192	DECLARE_WRITE8_MEMBER(work_ram6_w);
	193	DECLARE_WRITE8_MEMBER(work_ram7_w);
	194	DECLARE_WRITE8_MEMBER(necmk2_ppi8255_w);
	195	DECLARE_WRITE8_MEMBER(pc6001m2_system_latch_w);
	196	DECLARE_WRITE8_MEMBER(pc6001m2_vram_bank_w);
	197	DECLARE_WRITE8_MEMBER(pc6001m2_col_bank_w);
	198	DECLARE_READ8_MEMBER(upd7752_reg_r);
	199	DECLARE_WRITE8_MEMBER(upd7752_reg_w);
	200	DECLARE_WRITE8_MEMBER(pc6001m2_0xf3_w);
	201	DECLARE_WRITE8_MEMBER(pc6001m2_timer_adj_w);
	202	DECLARE_WRITE8_MEMBER(pc6001m2_timer_irqv_w);
	203	DECLARE_READ8_MEMBER(pc6001m2_bank_r0_r);
	204	DECLARE_READ8_MEMBER(pc6001m2_bank_r1_r);
	205	DECLARE_READ8_MEMBER(pc6001m2_bank_w0_r);
	206	DECLARE_READ8_MEMBER(pc6601_fdc_r);
	207	DECLARE_WRITE8_MEMBER(pc6601_fdc_w);
	208	DECLARE_READ8_MEMBER(pc6001sr_bank_rn_r);
	209	DECLARE_WRITE8_MEMBER(pc6001sr_bank_rn_w);
	210	DECLARE_READ8_MEMBER(pc6001sr_bank_wn_r);
	211	DECLARE_WRITE8_MEMBER(pc6001sr_bank_wn_w);
	212	DECLARE_WRITE8_MEMBER(sr_work_ram0_w);
	213	DECLARE_WRITE8_MEMBER(sr_work_ram1_w);
	214	DECLARE_WRITE8_MEMBER(sr_work_ram2_w);
	215	DECLARE_WRITE8_MEMBER(sr_work_ram3_w);
	216	DECLARE_WRITE8_MEMBER(sr_work_ram4_w);
	217	DECLARE_WRITE8_MEMBER(sr_work_ram5_w);
	218	DECLARE_WRITE8_MEMBER(sr_work_ram6_w);
	219	DECLARE_WRITE8_MEMBER(sr_work_ram7_w);
	220	DECLARE_WRITE8_MEMBER(pc6001sr_mode_w);
	221	DECLARE_WRITE8_MEMBER(pc6001sr_vram_bank_w);
	222	DECLARE_WRITE8_MEMBER(pc6001sr_system_latch_w);
	223	DECLARE_WRITE8_MEMBER(necsr_ppi8255_w);
179	224	};
180	225
181	226
r14844	r14845
663	708	return 0;
664	709	}
665	710
666		static WRITE8_HANDLER ( pc6001_system_latch_w )
	711	WRITE8_MEMBER(pc6001_state::pc6001_system_latch_w)
667	712	{
668		pc6001_state *state = space->machine().driver_data<pc6001_state>();
669	713	static const UINT16 startaddr[] = {0xC000, 0xE000, 0x8000, 0xA000 };
670	714
671		state->m_video_ram =  state->m_ram + startaddr[(data >> 1) & 0x03] - 0x8000;
	715	m_video_ram =  m_ram + startaddr[(data >> 1) & 0x03] - 0x8000;
672	716
673		if((!(state->m_sys_latch & 8)) && data & 0x8) //PLAY tape cmd
	717	if((!(m_sys_latch & 8)) && data & 0x8) //PLAY tape cmd
674	718	{
675		state->m_cas_switch = 1;
676		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_ENABLED,CASSETTE_MASK_MOTOR);
677		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_PLAY,CASSETTE_MASK_UISTATE);
	719	m_cas_switch = 1;
	720	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_ENABLED,CASSETTE_MASK_MOTOR);
	721	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_PLAY,CASSETTE_MASK_UISTATE);
678	722	}
679		if((state->m_sys_latch & 8) && ((data & 0x8) == 0)) //STOP tape cmd
	723	if((m_sys_latch & 8) && ((data & 0x8) == 0)) //STOP tape cmd
680	724	{
681		state->m_cas_switch = 0;
682		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
683		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_STOPPED,CASSETTE_MASK_UISTATE);
684		//state->m_irq_vector = 0x00;
685		//cputag_set_input_line(space->machine(),"maincpu", 0, ASSERT_LINE);
	725	m_cas_switch = 0;
	726	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
	727	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_STOPPED,CASSETTE_MASK_UISTATE);
	728	//m_irq_vector = 0x00;
	729	//cputag_set_input_line(machine(),"maincpu", 0, ASSERT_LINE);
686	730	}
687	731
688		state->m_sys_latch = data;
689		state->m_timer_irq_mask = data & 1;
	732	m_sys_latch = data;
	733	m_timer_irq_mask = data & 1;
690	734	//printf("%02x\n",data);
691	735	}
692	736
r14844	r14845
721	765	#endif
722	766
723	767
724		static READ8_HANDLER(nec_ppi8255_r)
	768	READ8_MEMBER(pc6001_state::nec_ppi8255_r)
725	769	{
726		pc6001_state *state = space->machine().driver_data<pc6001_state>();
727	770	if (offset==2)
728		return state->m_port_c_8255;
	771	return m_port_c_8255;
729	772	else if(offset==0)
730	773	{
731	774	UINT8 res;
732		res = state->m_cur_keycode;
733		//state->m_cur_keycode = 0;
	775	res = m_cur_keycode;
	776	//m_cur_keycode = 0;
734	777	return res;
735	778	}
736	779
737		return state->m_ppi->read(*space, offset);
	780	return m_ppi->read(*&space, offset);
738	781	}
739	782
740		static WRITE8_HANDLER(nec_ppi8255_w)
	783	WRITE8_MEMBER(pc6001_state::nec_ppi8255_w)
741	784	{
742		pc6001_state *state = space->machine().driver_data<pc6001_state>();
743	785	if (offset==3)
744	786	{
745	787	if(data & 1)
746		state->m_port_c_8255 |=   1<<((data>>1)&0x07);
	788	m_port_c_8255 |=   1<<((data>>1)&0x07);
747	789	else
748		state->m_port_c_8255 &= ~(1<<((data>>1)&0x07));
	790	m_port_c_8255 &= ~(1<<((data>>1)&0x07));
749	791
750	792	switch(data) {
751		case 0x08: state->m_port_c_8255 |= 0x88; break;
752		case 0x09: state->m_port_c_8255 &= 0xf7; break;
753		case 0x0c: state->m_port_c_8255 |= 0x28; break;
754		case 0x0d: state->m_port_c_8255 &= 0xf7; break;
	793	case 0x08: m_port_c_8255 |= 0x88; break;
	794	case 0x09: m_port_c_8255 &= 0xf7; break;
	795	case 0x0c: m_port_c_8255 |= 0x28; break;
	796	case 0x0d: m_port_c_8255 &= 0xf7; break;
755	797	default: break;
756	798	}
757	799
758		state->m_port_c_8255 |= 0xa8;
	800	m_port_c_8255 |= 0xa8;
759	801
760	802	{
761		UINT8 *gfx_data = space->machine().region("gfx1")->base();
762		UINT8 *ext_rom = space->machine().region("cart_img")->base();
	803	UINT8 *gfx_data = machine().region("gfx1")->base();
	804	UINT8 *ext_rom = machine().region("cart_img")->base();
763	805
764	806	//printf("%02x\n",data);
765	807
766	808	if((data & 0x0f) == 0x05)
767		memory_set_bankptr(space->machine(), "bank1", &ext_rom[0x2000]);
	809	memory_set_bankptr(machine(), "bank1", &ext_rom[0x2000]);
768	810	if((data & 0x0f) == 0x04)
769		memory_set_bankptr(space->machine(), "bank1", &gfx_data[0]);
	811	memory_set_bankptr(machine(), "bank1", &gfx_data[0]);
770	812	}
771	813	}
772		state->m_ppi->write(*space,offset,data);
	814	m_ppi->write(*&space,offset,data);
773	815	}
774	816
775	817	static ADDRESS_MAP_START(pc6001_map, AS_PROGRAM, 8, pc6001_state )
r14844	r14845
785	827	ADDRESS_MAP_GLOBAL_MASK(0xff)
786	828	AM_RANGE(0x80, 0x80) AM_DEVREADWRITE("uart", i8251_device, data_r, data_w)
787	829	AM_RANGE(0x81, 0x81) AM_DEVREADWRITE("uart", i8251_device, status_r, control_w)
788		AM_RANGE(0x90, 0x93) AM_MIRROR(0x0c) AM_READWRITE_LEGACY(nec_ppi8255_r, nec_ppi8255_w)
	830	AM_RANGE(0x90, 0x93) AM_MIRROR(0x0c) AM_READWRITE(nec_ppi8255_r, nec_ppi8255_w)
789	831	AM_RANGE(0xa0, 0xa0) AM_MIRROR(0x0c) AM_DEVWRITE_LEGACY("ay8910", ay8910_address_w)
790	832	AM_RANGE(0xa1, 0xa1) AM_MIRROR(0x0c) AM_DEVWRITE_LEGACY("ay8910", ay8910_data_w)
791	833	AM_RANGE(0xa2, 0xa2) AM_MIRROR(0x0c) AM_DEVREAD_LEGACY("ay8910", ay8910_r)
792	834	AM_RANGE(0xa3, 0xa3) AM_MIRROR(0x0c) AM_WRITENOP
793		AM_RANGE(0xb0, 0xb0) AM_MIRROR(0x0f) AM_WRITE_LEGACY(pc6001_system_latch_w)
	835	AM_RANGE(0xb0, 0xb0) AM_MIRROR(0x0f) AM_WRITE(pc6001_system_latch_w)
794	836	AM_RANGE(0xd0, 0xd3) AM_MIRROR(0x0c) AM_NOP // disk device
795	837	ADDRESS_MAP_END
796	838
r14844	r14845
970	1012	{ INVALID(0),   INVALID(0),      INVALID(0),      INVALID(0)  }   //0x0f: <invalid setting>
971	1013	};
972	1014
973		static WRITE8_HANDLER( pc6001m2_bank_r0_w )
	1015	WRITE8_MEMBER(pc6001_state::pc6001m2_bank_r0_w)
974	1016	{
975		pc6001_state *state = space->machine().driver_data<pc6001_state>();
976		UINT8 *ROM = space->machine().region("maincpu")->base();
977		UINT8 *gfx_data = space->machine().region("gfx1")->base();
	1017	UINT8 *ROM = machine().region("maincpu")->base();
	1018	UINT8 *gfx_data = machine().region("gfx1")->base();
978	1019
979	1020	//  bankaddress = 0x10000 + (0x4000 * ((data & 0x40)>>6));
980		//  memory_set_bankptr(space->machine(), 1, &ROM[bankaddress]);
	1021	//  memory_set_bankptr(machine(), 1, &ROM[bankaddress]);
981	1022
982		state->m_bank_r0 = data;
	1023	m_bank_r0 = data;
983	1024
984		//  printf("%02x BANK | %02x\n",data,state->m_bank_opt);
985		memory_set_bankptr(space->machine(), "bank1", &ROM[banksw_table_r0[(data & 0xf)+(state->m_bank_opt*0x10)][0]]);
986		memory_set_bankptr(space->machine(), "bank2", &ROM[banksw_table_r0[(data & 0xf)+(state->m_bank_opt*0x10)][1]]);
987		memory_set_bankptr(space->machine(), "bank3", &ROM[banksw_table_r0[((data & 0xf0)>>4)+(state->m_bank_opt*0x10)][2]]);
988		if(!state->m_gfx_bank_on)
989		memory_set_bankptr(space->machine(), "bank4", &ROM[banksw_table_r0[((state->m_bank_r0 & 0xf0)>>4)+(state->m_bank_opt*0x10)][3]]);
	1025	//  printf("%02x BANK | %02x\n",data,m_bank_opt);
	1026	memory_set_bankptr(machine(), "bank1", &ROM[banksw_table_r0[(data & 0xf)+(m_bank_opt*0x10)][0]]);
	1027	memory_set_bankptr(machine(), "bank2", &ROM[banksw_table_r0[(data & 0xf)+(m_bank_opt*0x10)][1]]);
	1028	memory_set_bankptr(machine(), "bank3", &ROM[banksw_table_r0[((data & 0xf0)>>4)+(m_bank_opt*0x10)][2]]);
	1029	if(!m_gfx_bank_on)
	1030	memory_set_bankptr(machine(), "bank4", &ROM[banksw_table_r0[((m_bank_r0 & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
990	1031	else
991		memory_set_bankptr(space->machine(), "bank4", &gfx_data[state->m_cgrom_bank_addr]);
	1032	memory_set_bankptr(machine(), "bank4", &gfx_data[m_cgrom_bank_addr]);
992	1033	}
993	1034
994		static WRITE8_HANDLER( pc6001m2_bank_r1_w )
	1035	WRITE8_MEMBER(pc6001_state::pc6001m2_bank_r1_w)
995	1036	{
996		pc6001_state *state = space->machine().driver_data<pc6001_state>();
997		UINT8 *ROM = space->machine().region("maincpu")->base();
	1037	UINT8 *ROM = machine().region("maincpu")->base();
998	1038
999	1039	//  bankaddress = 0x10000 + (0x4000 * ((data & 0x40)>>6));
1000		//  memory_set_bankptr(space->machine(), 1, &ROM[bankaddress]);
	1040	//  memory_set_bankptr(machine(), 1, &ROM[bankaddress]);
1001	1041
1002		state->m_bank_r1 = data;
	1042	m_bank_r1 = data;
1003	1043
1004	1044	//  printf("%02x BANK\n",data);
1005		memory_set_bankptr(space->machine(), "bank5", &ROM[banksw_table_r1[(data & 0xf)+(state->m_bank_opt*0x10)][0]]);
1006		memory_set_bankptr(space->machine(), "bank6", &ROM[banksw_table_r1[(data & 0xf)+(state->m_bank_opt*0x10)][1]]);
1007		memory_set_bankptr(space->machine(), "bank7", &ROM[banksw_table_r1[((data & 0xf0)>>4)+(state->m_bank_opt*0x10)][2]]);
1008		memory_set_bankptr(space->machine(), "bank8", &ROM[banksw_table_r1[((data & 0xf0)>>4)+(state->m_bank_opt*0x10)][3]]);
	1045	memory_set_bankptr(machine(), "bank5", &ROM[banksw_table_r1[(data & 0xf)+(m_bank_opt*0x10)][0]]);
	1046	memory_set_bankptr(machine(), "bank6", &ROM[banksw_table_r1[(data & 0xf)+(m_bank_opt*0x10)][1]]);
	1047	memory_set_bankptr(machine(), "bank7", &ROM[banksw_table_r1[((data & 0xf0)>>4)+(m_bank_opt*0x10)][2]]);
	1048	memory_set_bankptr(machine(), "bank8", &ROM[banksw_table_r1[((data & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
1009	1049	}
1010	1050
1011		static WRITE8_HANDLER( pc6001m2_bank_w0_w )
	1051	WRITE8_MEMBER(pc6001_state::pc6001m2_bank_w0_w)
1012	1052	{
1013		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1014		state->m_bank_w = data;
	1053	m_bank_w = data;
1015	1054	}
1016	1055
1017		static WRITE8_HANDLER( pc6001m2_opt_bank_w )
	1056	WRITE8_MEMBER(pc6001_state::pc6001m2_opt_bank_w)
1018	1057	{
1019		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1020		UINT8 *ROM = space->machine().region("maincpu")->base();
1021		UINT8 *gfx_data = space->machine().region("gfx1")->base();
	1058	UINT8 *ROM = machine().region("maincpu")->base();
	1059	UINT8 *gfx_data = machine().region("gfx1")->base();
1022	1060
1023	1061	/*
1024	1062	0 - TVROM / VOICE ROM
r14844	r14845
1026	1064	2 - KANJI ROM bank 1
1027	1065	3 - TVROM / VOICE ROM
1028	1066	*/
1029		state->m_bank_opt = data & 3;
	1067	m_bank_opt = data & 3;
1030	1068
1031		memory_set_bankptr(space->machine(), "bank1", &ROM[banksw_table_r0[(state->m_bank_r0 & 0xf)+(state->m_bank_opt*0x10)][0]]);
1032		memory_set_bankptr(space->machine(), "bank2", &ROM[banksw_table_r0[(state->m_bank_r0 & 0xf)+(state->m_bank_opt*0x10)][1]]);
1033		memory_set_bankptr(space->machine(), "bank3", &ROM[banksw_table_r0[((state->m_bank_r0 & 0xf0)>>4)+(state->m_bank_opt*0x10)][2]]);
1034		if(!state->m_gfx_bank_on)
1035		memory_set_bankptr(space->machine(), "bank4", &ROM[banksw_table_r0[((state->m_bank_r0 & 0xf0)>>4)+(state->m_bank_opt*0x10)][3]]);
	1069	memory_set_bankptr(machine(), "bank1", &ROM[banksw_table_r0[(m_bank_r0 & 0xf)+(m_bank_opt*0x10)][0]]);
	1070	memory_set_bankptr(machine(), "bank2", &ROM[banksw_table_r0[(m_bank_r0 & 0xf)+(m_bank_opt*0x10)][1]]);
	1071	memory_set_bankptr(machine(), "bank3", &ROM[banksw_table_r0[((m_bank_r0 & 0xf0)>>4)+(m_bank_opt*0x10)][2]]);
	1072	if(!m_gfx_bank_on)
	1073	memory_set_bankptr(machine(), "bank4", &ROM[banksw_table_r0[((m_bank_r0 & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
1036	1074	else
1037		memory_set_bankptr(space->machine(), "bank4", &gfx_data[state->m_cgrom_bank_addr]);
1038		memory_set_bankptr(space->machine(), "bank4", &ROM[banksw_table_r0[((state->m_bank_r0 & 0xf0)>>4)+(state->m_bank_opt*0x10)][3]]);
1039		memory_set_bankptr(space->machine(), "bank5", &ROM[banksw_table_r1[(state->m_bank_r1 & 0xf)+(state->m_bank_opt*0x10)][0]]);
1040		memory_set_bankptr(space->machine(), "bank6", &ROM[banksw_table_r1[(state->m_bank_r1 & 0xf)+(state->m_bank_opt*0x10)][1]]);
1041		memory_set_bankptr(space->machine(), "bank7", &ROM[banksw_table_r1[((state->m_bank_r1 & 0xf0)>>4)+(state->m_bank_opt*0x10)][2]]);
1042		memory_set_bankptr(space->machine(), "bank8", &ROM[banksw_table_r1[((state->m_bank_r1 & 0xf0)>>4)+(state->m_bank_opt*0x10)][3]]);
	1075	memory_set_bankptr(machine(), "bank4", &gfx_data[m_cgrom_bank_addr]);
	1076	memory_set_bankptr(machine(), "bank4", &ROM[banksw_table_r0[((m_bank_r0 & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
	1077	memory_set_bankptr(machine(), "bank5", &ROM[banksw_table_r1[(m_bank_r1 & 0xf)+(m_bank_opt*0x10)][0]]);
	1078	memory_set_bankptr(machine(), "bank6", &ROM[banksw_table_r1[(m_bank_r1 & 0xf)+(m_bank_opt*0x10)][1]]);
	1079	memory_set_bankptr(machine(), "bank7", &ROM[banksw_table_r1[((m_bank_r1 & 0xf0)>>4)+(m_bank_opt*0x10)][2]]);
	1080	memory_set_bankptr(machine(), "bank8", &ROM[banksw_table_r1[((m_bank_r1 & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
1043	1081
1044	1082	}
1045	1083
1046		static WRITE8_HANDLER( work_ram0_w )
	1084	WRITE8_MEMBER(pc6001_state::work_ram0_w)
1047	1085	{
1048		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1049		UINT8 *ROM = space->machine().region("maincpu")->base();
1050		ROM[offset+((state->m_bank_w & 0x01) ? WRAM(0) : EXWRAM(0))] = data;
	1086	UINT8 *ROM = machine().region("maincpu")->base();
	1087	ROM[offset+((m_bank_w & 0x01) ? WRAM(0) : EXWRAM(0))] = data;
1051	1088	}
1052	1089
1053		static WRITE8_HANDLER( work_ram1_w )
	1090	WRITE8_MEMBER(pc6001_state::work_ram1_w)
1054	1091	{
1055		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1056		UINT8 *ROM = space->machine().region("maincpu")->base();
1057		ROM[offset+((state->m_bank_w & 0x01) ? WRAM(1) : EXWRAM(1))] = data;
	1092	UINT8 *ROM = machine().region("maincpu")->base();
	1093	ROM[offset+((m_bank_w & 0x01) ? WRAM(1) : EXWRAM(1))] = data;
1058	1094	}
1059	1095
1060		static WRITE8_HANDLER( work_ram2_w )
	1096	WRITE8_MEMBER(pc6001_state::work_ram2_w)
1061	1097	{
1062		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1063		UINT8 *ROM = space->machine().region("maincpu")->base();
1064		ROM[offset+((state->m_bank_w & 0x04) ? WRAM(2) : EXWRAM(2))] = data;
	1098	UINT8 *ROM = machine().region("maincpu")->base();
	1099	ROM[offset+((m_bank_w & 0x04) ? WRAM(2) : EXWRAM(2))] = data;
1065	1100	}
1066	1101
1067		static WRITE8_HANDLER( work_ram3_w )
	1102	WRITE8_MEMBER(pc6001_state::work_ram3_w)
1068	1103	{
1069		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1070		UINT8 *ROM = space->machine().region("maincpu")->base();
1071		ROM[offset+((state->m_bank_w & 0x04) ? WRAM(3) : EXWRAM(3))] = data;
	1104	UINT8 *ROM = machine().region("maincpu")->base();
	1105	ROM[offset+((m_bank_w & 0x04) ? WRAM(3) : EXWRAM(3))] = data;
1072	1106	}
1073	1107
1074		static WRITE8_HANDLER( work_ram4_w )
	1108	WRITE8_MEMBER(pc6001_state::work_ram4_w)
1075	1109	{
1076		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1077		UINT8 *ROM = space->machine().region("maincpu")->base();
1078		ROM[offset+((state->m_bank_w & 0x10) ? WRAM(4) : EXWRAM(4))] = data;
	1110	UINT8 *ROM = machine().region("maincpu")->base();
	1111	ROM[offset+((m_bank_w & 0x10) ? WRAM(4) : EXWRAM(4))] = data;
1079	1112	}
1080	1113
1081		static WRITE8_HANDLER( work_ram5_w )
	1114	WRITE8_MEMBER(pc6001_state::work_ram5_w)
1082	1115	{
1083		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1084		UINT8 *ROM = space->machine().region("maincpu")->base();
1085		ROM[offset+((state->m_bank_w & 0x10) ? WRAM(5) : EXWRAM(5))] = data;
	1116	UINT8 *ROM = machine().region("maincpu")->base();
	1117	ROM[offset+((m_bank_w & 0x10) ? WRAM(5) : EXWRAM(5))] = data;
1086	1118	}
1087	1119
1088		static WRITE8_HANDLER( work_ram6_w )
	1120	WRITE8_MEMBER(pc6001_state::work_ram6_w)
1089	1121	{
1090		pc6001_state *state = space->machine().driver_data<pc6001_state>(); UINT8 *ROM = space->machine().region("maincpu")->base(); ROM[offset+((state->m_bank_w & 0x40) ? WRAM(6) : EXWRAM(6))] = data;
1091	1122	}
1092	1123
1093		static WRITE8_HANDLER( work_ram7_w )
	1124	WRITE8_MEMBER(pc6001_state::work_ram7_w)
1094	1125	{
1095		pc6001_state *state = space->machine().driver_data<pc6001_state>(); UINT8 *ROM = space->machine().region("maincpu")->base(); ROM[offset+((state->m_bank_w & 0x40) ? WRAM(7) : EXWRAM(7))] = data;
1096	1126	}
1097	1127
1098	1128
1099		static WRITE8_HANDLER(necmk2_ppi8255_w)
	1129	WRITE8_MEMBER(pc6001_state::necmk2_ppi8255_w)
1100	1130	{
1101		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1102	1131	if (offset==3)
1103	1132	{
1104	1133	if(data & 1)
1105		state->m_port_c_8255 |=   1<<((data>>1)&0x07);
	1134	m_port_c_8255 |=   1<<((data>>1)&0x07);
1106	1135	else
1107		state->m_port_c_8255 &= ~(1<<((data>>1)&0x07));
	1136	m_port_c_8255 &= ~(1<<((data>>1)&0x07));
1108	1137
1109	1138	switch(data) {
1110		case 0x08: state->m_port_c_8255 |= 0x88; break;
1111		case 0x09: state->m_port_c_8255 &= 0xf7; break;
1112		case 0x0c: state->m_port_c_8255 |= 0x28; break;
1113		case 0x0d: state->m_port_c_8255 &= 0xf7; break;
	1139	case 0x08: m_port_c_8255 |= 0x88; break;
	1140	case 0x09: m_port_c_8255 &= 0xf7; break;
	1141	case 0x0c: m_port_c_8255 |= 0x28; break;
	1142	case 0x0d: m_port_c_8255 &= 0xf7; break;
1114	1143	default: break;
1115	1144	}
1116	1145
1117		state->m_port_c_8255 |= 0xa8;
	1146	m_port_c_8255 |= 0xa8;
1118	1147
1119	1148	{
1120		UINT8 *ROM = space->machine().region("maincpu")->base();
1121		UINT8 *gfx_data = space->machine().region("gfx1")->base();
	1149	UINT8 *ROM = machine().region("maincpu")->base();
	1150	UINT8 *gfx_data = machine().region("gfx1")->base();
1122	1151
1123	1152	//printf("%02x\n",data);
1124	1153
1125	1154	if((data & 0x0f) == 0x05)
1126	1155	{
1127		state->m_gfx_bank_on = 0;
1128		memory_set_bankptr(space->machine(), "bank4", &ROM[banksw_table_r0[((state->m_bank_r0 & 0xf0)>>4)+(state->m_bank_opt*0x10)][3]]);
	1156	m_gfx_bank_on = 0;
	1157	memory_set_bankptr(machine(), "bank4", &ROM[banksw_table_r0[((m_bank_r0 & 0xf0)>>4)+(m_bank_opt*0x10)][3]]);
1129	1158	}
1130	1159	if((data & 0x0f) == 0x04)
1131	1160	{
1132		state->m_gfx_bank_on = 1;
1133		memory_set_bankptr(space->machine(), "bank4", &gfx_data[state->m_cgrom_bank_addr]);
	1161	m_gfx_bank_on = 1;
	1162	memory_set_bankptr(machine(), "bank4", &gfx_data[m_cgrom_bank_addr]);
1134	1163	}
1135	1164	}
1136	1165	}
1137		state->m_ppi->write(*space,offset,data);
	1166	m_ppi->write(*&space,offset,data);
1138	1167	}
1139	1168
1140	1169	static void vram_bank_change(running_machine &machine,UINT8 vram_bank)
r14844	r14845
1165	1194	}
1166	1195	}
1167	1196
1168		static WRITE8_HANDLER ( pc6001m2_system_latch_w )
	1197	WRITE8_MEMBER(pc6001_state::pc6001m2_system_latch_w)
1169	1198	{
1170		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1171		if((!(state->m_sys_latch & 8)) && data & 0x8) //PLAY tape cmd
	1199	if((!(m_sys_latch & 8)) && data & 0x8) //PLAY tape cmd
1172	1200	{
1173		state->m_cas_switch = 1;
1174		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_ENABLED,CASSETTE_MASK_MOTOR);
1175		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_PLAY,CASSETTE_MASK_UISTATE);
	1201	m_cas_switch = 1;
	1202	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_ENABLED,CASSETTE_MASK_MOTOR);
	1203	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_PLAY,CASSETTE_MASK_UISTATE);
1176	1204	}
1177		if((state->m_sys_latch & 8) && ((data & 0x8) == 0)) //STOP tape cmd
	1205	if((m_sys_latch & 8) && ((data & 0x8) == 0)) //STOP tape cmd
1178	1206	{
1179		state->m_cas_switch = 0;
1180		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
1181		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_STOPPED,CASSETTE_MASK_UISTATE);
1182		//state->m_irq_vector = 0x00;
1183		//cputag_set_input_line(space->machine(),"maincpu", 0, ASSERT_LINE);
	1207	m_cas_switch = 0;
	1208	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
	1209	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_STOPPED,CASSETTE_MASK_UISTATE);
	1210	//m_irq_vector = 0x00;
	1211	//cputag_set_input_line(machine(),"maincpu", 0, ASSERT_LINE);
1184	1212	}
1185	1213
1186		state->m_sys_latch = data;
	1214	m_sys_latch = data;
1187	1215
1188		state->m_timer_irq_mask = data & 1;
1189		vram_bank_change(space->machine(),(state->m_ex_vram_bank & 0x06) | ((state->m_sys_latch & 0x06) << 4));
	1216	m_timer_irq_mask = data & 1;
	1217	vram_bank_change(machine(),(m_ex_vram_bank & 0x06) | ((m_sys_latch & 0x06) << 4));
1190	1218
1191	1219	//printf("%02x B0\n",data);
1192	1220	}
1193	1221
1194	1222
1195		static WRITE8_HANDLER( pc6001m2_vram_bank_w )
	1223	WRITE8_MEMBER(pc6001_state::pc6001m2_vram_bank_w)
1196	1224	{
1197		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1198	1225	//static const UINT32 startaddr[] = {WRAM(6), WRAM(6), WRAM(0), WRAM(4) };
1199	1226
1200		state->m_ex_vram_bank = data;
1201		vram_bank_change(space->machine(),(state->m_ex_vram_bank & 0x06) | ((state->m_sys_latch & 0x06) << 4));
	1227	m_ex_vram_bank = data;
	1228	vram_bank_change(machine(),(m_ex_vram_bank & 0x06) | ((m_sys_latch & 0x06) << 4));
1202	1229
1203		state->m_exgfx_text_mode = ((data & 2) == 0);
1204		state->m_cgrom_bank_addr = (data & 2) ? 0x0000 : 0x2000;
	1230	m_exgfx_text_mode = ((data & 2) == 0);
	1231	m_cgrom_bank_addr = (data & 2) ? 0x0000 : 0x2000;
1205	1232
1206		state->m_exgfx_bitmap_mode = (data & 8);
1207		state->m_exgfx_2bpp_mode = ((data & 6) == 0);
	1233	m_exgfx_bitmap_mode = (data & 8);
	1234	m_exgfx_2bpp_mode = ((data & 6) == 0);
1208	1235
1209	1236	{
1210	1237	/* Apparently bitmap modes changes the screen res to 320 x 200 */
1211	1238	{
1212		rectangle visarea = space->machine().primary_screen->visible_area();
	1239	rectangle visarea = machine().primary_screen->visible_area();
1213	1240	int y_height;
1214	1241
1215		y_height = (state->m_exgfx_bitmap_mode || state->m_exgfx_2bpp_mode) ? 200 : 240;
	1242	y_height = (m_exgfx_bitmap_mode || m_exgfx_2bpp_mode) ? 200 : 240;
1216	1243
1217	1244	visarea.set(0, (320) - 1, 0, (y_height) - 1);
1218	1245
1219		space->machine().primary_screen->configure(320, 240, visarea, space->machine().primary_screen->frame_period().attoseconds);
	1246	machine().primary_screen->configure(320, 240, visarea, machine().primary_screen->frame_period().attoseconds);
1220	1247	}
1221	1248	}
1222	1249
1223	1250	//  popmessage("%02x",data);
1224	1251
1225		//  state->m_video_ram = work_ram + startaddr[(data >> 1) & 0x03];
	1252	//  m_video_ram = work_ram + startaddr[(data >> 1) & 0x03];
1226	1253	}
1227	1254
1228		static WRITE8_HANDLER( pc6001m2_col_bank_w )
	1255	WRITE8_MEMBER(pc6001_state::pc6001m2_col_bank_w)
1229	1256	{
1230		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1231		state->m_bgcol_bank = (data & 7);
	1257	m_bgcol_bank = (data & 7);
1232	1258	}
1233	1259
1234	1260	/* voice synth is a NEC uPD7752 sound chip (currently unemulated) */
1235		static READ8_HANDLER( upd7752_reg_r )
	1261	READ8_MEMBER(pc6001_state::upd7752_reg_r)
1236	1262	{
1237	1263	switch(offset & 3)
1238	1264	{
r14844	r14845
1250	1276	return 0xff;
1251	1277	}
1252	1278
1253		static WRITE8_HANDLER( upd7752_reg_w )
	1279	WRITE8_MEMBER(pc6001_state::upd7752_reg_w)
1254	1280	{
1255	1281	switch(offset & 3)
1256	1282	{
r14844	r14845
1270	1296	}
1271	1297	}
1272	1298
1273		static WRITE8_HANDLER( pc6001m2_0xf3_w )
	1299	WRITE8_MEMBER(pc6001_state::pc6001m2_0xf3_w)
1274	1300	{
1275		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1276	1301	/*
1277	1302	x--- ---- M1 (?) wait setting
1278	1303	-x-- ---- ROM wait setting
r14844	r14845
1283	1308	---- --x- custom irq 2 mask
1284	1309	---- ---x custom irq 1 mask
1285	1310	*/
1286		state->m_timer_irq_mask2 = data & 4;
	1311	m_timer_irq_mask2 = data & 4;
1287	1312	}
1288	1313
1289	1314	static TIMER_CALLBACK(audio_callback)
r14844	r14845
1298	1323	}
1299	1324
1300	1325
1301		static WRITE8_HANDLER( pc6001m2_timer_adj_w )
	1326	WRITE8_MEMBER(pc6001_state::pc6001m2_timer_adj_w)
1302	1327	{
1303		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1304		state->m_timer_hz_div = data;
1305		attotime period = attotime::from_hz((487.5*4)/(state->m_timer_hz_div+1));
1306		state->m_timer_irq_timer->adjust(period,  0, period);
	1328	m_timer_hz_div = data;
	1329	attotime period = attotime::from_hz((487.5*4)/(m_timer_hz_div+1));
	1330	m_timer_irq_timer->adjust(period,  0, period);
1307	1331	}
1308	1332
1309		static WRITE8_HANDLER( pc6001m2_timer_irqv_w )
	1333	WRITE8_MEMBER(pc6001_state::pc6001m2_timer_irqv_w)
1310	1334	{
1311		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1312		state->m_timer_irq_vector = data;
	1335	m_timer_irq_vector = data;
1313	1336	}
1314	1337
1315		static READ8_HANDLER( pc6001m2_bank_r0_r )
	1338	READ8_MEMBER(pc6001_state::pc6001m2_bank_r0_r)
1316	1339	{
1317		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1318		return state->m_bank_r0;
	1340	return m_bank_r0;
1319	1341	}
1320	1342
1321		static READ8_HANDLER( pc6001m2_bank_r1_r )
	1343	READ8_MEMBER(pc6001_state::pc6001m2_bank_r1_r)
1322	1344	{
1323		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1324		return state->m_bank_r1;
	1345	return m_bank_r1;
1325	1346	}
1326	1347
1327		static READ8_HANDLER( pc6001m2_bank_w0_r )
	1348	READ8_MEMBER(pc6001_state::pc6001m2_bank_w0_r)
1328	1349	{
1329		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1330		return state->m_bank_w;
	1350	return m_bank_w;
1331	1351	}
1332	1352
1333	1353	static ADDRESS_MAP_START(pc6001m2_map, AS_PROGRAM, 8, pc6001_state )
1334	1354	ADDRESS_MAP_UNMAP_HIGH
1335		AM_RANGE(0x0000, 0x1fff) AM_ROMBANK("bank1") AM_WRITE_LEGACY(work_ram0_w)
1336		AM_RANGE(0x2000, 0x3fff) AM_ROMBANK("bank2") AM_WRITE_LEGACY(work_ram1_w)
1337		AM_RANGE(0x4000, 0x5fff) AM_ROMBANK("bank3") AM_WRITE_LEGACY(work_ram2_w)
1338		AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank4") AM_WRITE_LEGACY(work_ram3_w)
1339		AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("bank5") AM_WRITE_LEGACY(work_ram4_w)
1340		AM_RANGE(0xa000, 0xbfff) AM_ROMBANK("bank6") AM_WRITE_LEGACY(work_ram5_w)
1341		AM_RANGE(0xc000, 0xdfff) AM_ROMBANK("bank7") AM_WRITE_LEGACY(work_ram6_w)
1342		AM_RANGE(0xe000, 0xffff) AM_ROMBANK("bank8") AM_WRITE_LEGACY(work_ram7_w)
	1355	AM_RANGE(0x0000, 0x1fff) AM_ROMBANK("bank1") AM_WRITE(work_ram0_w)
	1356	AM_RANGE(0x2000, 0x3fff) AM_ROMBANK("bank2") AM_WRITE(work_ram1_w)
	1357	AM_RANGE(0x4000, 0x5fff) AM_ROMBANK("bank3") AM_WRITE(work_ram2_w)
	1358	AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank4") AM_WRITE(work_ram3_w)
	1359	AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("bank5") AM_WRITE(work_ram4_w)
	1360	AM_RANGE(0xa000, 0xbfff) AM_ROMBANK("bank6") AM_WRITE(work_ram5_w)
	1361	AM_RANGE(0xc000, 0xdfff) AM_ROMBANK("bank7") AM_WRITE(work_ram6_w)
	1362	AM_RANGE(0xe000, 0xffff) AM_ROMBANK("bank8") AM_WRITE(work_ram7_w)
1343	1363	ADDRESS_MAP_END
1344	1364
1345	1365	static ADDRESS_MAP_START( pc6001m2_io , AS_IO, 8, pc6001_state )
r14844	r14845
1348	1368	AM_RANGE(0x80, 0x80) AM_DEVREADWRITE("uart", i8251_device, data_r, data_w)
1349	1369	AM_RANGE(0x81, 0x81) AM_DEVREADWRITE("uart", i8251_device, status_r, control_w)
1350	1370
1351		AM_RANGE(0x90, 0x93) AM_MIRROR(0x0c) AM_READWRITE_LEGACY(nec_ppi8255_r, necmk2_ppi8255_w)
	1371	AM_RANGE(0x90, 0x93) AM_MIRROR(0x0c) AM_READWRITE(nec_ppi8255_r, necmk2_ppi8255_w)
1352	1372
1353	1373	AM_RANGE(0xa0, 0xa0) AM_MIRROR(0x0c) AM_DEVWRITE_LEGACY("ay8910", ay8910_address_w)
1354	1374	AM_RANGE(0xa1, 0xa1) AM_MIRROR(0x0c) AM_DEVWRITE_LEGACY("ay8910", ay8910_data_w)
1355	1375	AM_RANGE(0xa2, 0xa2) AM_MIRROR(0x0c) AM_DEVREAD_LEGACY("ay8910", ay8910_r)
1356	1376	AM_RANGE(0xa3, 0xa3) AM_MIRROR(0x0c) AM_NOP
1357	1377
1358		AM_RANGE(0xb0, 0xb0) AM_MIRROR(0x0f) AM_WRITE_LEGACY(pc6001m2_system_latch_w)
	1378	AM_RANGE(0xb0, 0xb0) AM_MIRROR(0x0f) AM_WRITE(pc6001m2_system_latch_w)
1359	1379
1360		AM_RANGE(0xc0, 0xc0) AM_WRITE_LEGACY(pc6001m2_col_bank_w)
1361		AM_RANGE(0xc1, 0xc1) AM_WRITE_LEGACY(pc6001m2_vram_bank_w)
1362		AM_RANGE(0xc2, 0xc2) AM_WRITE_LEGACY(pc6001m2_opt_bank_w)
	1380	AM_RANGE(0xc0, 0xc0) AM_WRITE(pc6001m2_col_bank_w)
	1381	AM_RANGE(0xc1, 0xc1) AM_WRITE(pc6001m2_vram_bank_w)
	1382	AM_RANGE(0xc2, 0xc2) AM_WRITE(pc6001m2_opt_bank_w)
1363	1383
1364	1384	AM_RANGE(0xd0, 0xd3) AM_MIRROR(0x0c) AM_NOP // disk device
1365	1385
1366		AM_RANGE(0xe0, 0xe3) AM_MIRROR(0x0c) AM_READWRITE_LEGACY(upd7752_reg_r,upd7752_reg_w)
	1386	AM_RANGE(0xe0, 0xe3) AM_MIRROR(0x0c) AM_READWRITE(upd7752_reg_r,upd7752_reg_w)
1367	1387
1368		AM_RANGE(0xf0, 0xf0) AM_READWRITE_LEGACY(pc6001m2_bank_r0_r,pc6001m2_bank_r0_w)
1369		AM_RANGE(0xf1, 0xf1) AM_READWRITE_LEGACY(pc6001m2_bank_r1_r,pc6001m2_bank_r1_w)
1370		AM_RANGE(0xf2, 0xf2) AM_READWRITE_LEGACY(pc6001m2_bank_w0_r,pc6001m2_bank_w0_w)
1371		AM_RANGE(0xf3, 0xf3) AM_WRITE_LEGACY(pc6001m2_0xf3_w)
	1388	AM_RANGE(0xf0, 0xf0) AM_READWRITE(pc6001m2_bank_r0_r,pc6001m2_bank_r0_w)
	1389	AM_RANGE(0xf1, 0xf1) AM_READWRITE(pc6001m2_bank_r1_r,pc6001m2_bank_r1_w)
	1390	AM_RANGE(0xf2, 0xf2) AM_READWRITE(pc6001m2_bank_w0_r,pc6001m2_bank_w0_w)
	1391	AM_RANGE(0xf3, 0xf3) AM_WRITE(pc6001m2_0xf3_w)
1372	1392	//  AM_RANGE(0xf4
1373	1393	//  AM_RANGE(0xf5
1374		AM_RANGE(0xf6, 0xf6) AM_WRITE_LEGACY(pc6001m2_timer_adj_w)
1375		AM_RANGE(0xf7, 0xf7) AM_WRITE_LEGACY(pc6001m2_timer_irqv_w)
	1394	AM_RANGE(0xf6, 0xf6) AM_WRITE(pc6001m2_timer_adj_w)
	1395	AM_RANGE(0xf7, 0xf7) AM_WRITE(pc6001m2_timer_irqv_w)
1376	1396	ADDRESS_MAP_END
1377	1397
1378	1398	/* disk device placeholder (TODO: identify & hook-up this) */
1379		static READ8_HANDLER( pc6601_fdc_r )
	1399	READ8_MEMBER(pc6001_state::pc6601_fdc_r)
1380	1400	{
1381		return space->machine().rand();
	1401	return machine().rand();
1382	1402	}
1383	1403
1384		static WRITE8_HANDLER( pc6601_fdc_w )
	1404	WRITE8_MEMBER(pc6001_state::pc6601_fdc_w)
1385	1405	{
1386	1406	}
1387	1407
r14844	r14845
1391	1411	AM_RANGE(0x80, 0x80) AM_DEVREADWRITE("uart", i8251_device, data_r, data_w)
1392	1412	AM_RANGE(0x81, 0x81) AM_DEVREADWRITE("uart", i8251_device, status_r, control_w)
1393	1413
1394		AM_RANGE(0x90, 0x93) AM_MIRROR(0x0c) AM_READWRITE_LEGACY(nec_ppi8255_r, necmk2_ppi8255_w)
	1414	AM_RANGE(0x90, 0x93) AM_MIRROR(0x0c) AM_READWRITE(nec_ppi8255_r, necmk2_ppi8255_w)
1395	1415
1396	1416	AM_RANGE(0xa0, 0xa0) AM_MIRROR(0x0c) AM_DEVWRITE_LEGACY("ay8910", ay8910_address_w)
1397	1417	AM_RANGE(0xa1, 0xa1) AM_MIRROR(0x0c) AM_DEVWRITE_LEGACY("ay8910", ay8910_data_w)
1398	1418	AM_RANGE(0xa2, 0xa2) AM_MIRROR(0x0c) AM_DEVREAD_LEGACY("ay8910", ay8910_r)
1399	1419	AM_RANGE(0xa3, 0xa3) AM_MIRROR(0x0c) AM_NOP
1400	1420
1401		AM_RANGE(0xb0, 0xb0) AM_WRITE_LEGACY(pc6001m2_system_latch_w)
	1421	AM_RANGE(0xb0, 0xb0) AM_WRITE(pc6001m2_system_latch_w)
1402	1422	/* these are disk related */
1403	1423	//  AM_RANGE(0xb1
1404	1424	//  AM_RANGE(0xb2
1405	1425	//  AM_RANGE(0xb3
1406	1426
1407		AM_RANGE(0xc0, 0xc0) AM_WRITE_LEGACY(pc6001m2_col_bank_w)
1408		AM_RANGE(0xc1, 0xc1) AM_WRITE_LEGACY(pc6001m2_vram_bank_w)
1409		AM_RANGE(0xc2, 0xc2) AM_WRITE_LEGACY(pc6001m2_opt_bank_w)
	1427	AM_RANGE(0xc0, 0xc0) AM_WRITE(pc6001m2_col_bank_w)
	1428	AM_RANGE(0xc1, 0xc1) AM_WRITE(pc6001m2_vram_bank_w)
	1429	AM_RANGE(0xc2, 0xc2) AM_WRITE(pc6001m2_opt_bank_w)
1410	1430
1411		AM_RANGE(0xd0, 0xdf) AM_READWRITE_LEGACY(pc6601_fdc_r,pc6601_fdc_w) // disk device
	1431	AM_RANGE(0xd0, 0xdf) AM_READWRITE(pc6601_fdc_r,pc6601_fdc_w) // disk device
1412	1432
1413		AM_RANGE(0xe0, 0xe3) AM_MIRROR(0x0c) AM_READWRITE_LEGACY(upd7752_reg_r,upd7752_reg_w)
	1433	AM_RANGE(0xe0, 0xe3) AM_MIRROR(0x0c) AM_READWRITE(upd7752_reg_r,upd7752_reg_w)
1414	1434
1415		AM_RANGE(0xf0, 0xf0) AM_READWRITE_LEGACY(pc6001m2_bank_r0_r,pc6001m2_bank_r0_w)
1416		AM_RANGE(0xf1, 0xf1) AM_READWRITE_LEGACY(pc6001m2_bank_r1_r,pc6001m2_bank_r1_w)
1417		AM_RANGE(0xf2, 0xf2) AM_READWRITE_LEGACY(pc6001m2_bank_w0_r,pc6001m2_bank_w0_w)
1418		AM_RANGE(0xf3, 0xf3) AM_WRITE_LEGACY(pc6001m2_0xf3_w)
	1435	AM_RANGE(0xf0, 0xf0) AM_READWRITE(pc6001m2_bank_r0_r,pc6001m2_bank_r0_w)
	1436	AM_RANGE(0xf1, 0xf1) AM_READWRITE(pc6001m2_bank_r1_r,pc6001m2_bank_r1_w)
	1437	AM_RANGE(0xf2, 0xf2) AM_READWRITE(pc6001m2_bank_w0_r,pc6001m2_bank_w0_w)
	1438	AM_RANGE(0xf3, 0xf3) AM_WRITE(pc6001m2_0xf3_w)
1419	1439	//  AM_RANGE(0xf4
1420	1440	//  AM_RANGE(0xf5
1421		AM_RANGE(0xf6, 0xf6) AM_WRITE_LEGACY(pc6001m2_timer_adj_w)
1422		AM_RANGE(0xf7, 0xf7) AM_WRITE_LEGACY(pc6001m2_timer_irqv_w)
	1441	AM_RANGE(0xf6, 0xf6) AM_WRITE(pc6001m2_timer_adj_w)
	1442	AM_RANGE(0xf7, 0xf7) AM_WRITE(pc6001m2_timer_irqv_w)
1423	1443	ADDRESS_MAP_END
1424	1444
1425	1445	/* PC-6001 SR */
r14844	r14845
1448	1468	#define SR_NULL(_v_) \
1449	1469	0x80000+(0x1000*_v_) \
1450	1470
1451		static READ8_HANDLER( pc6001sr_bank_rn_r )
	1471	READ8_MEMBER(pc6001_state::pc6001sr_bank_rn_r)
1452	1472	{
1453		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1454		return state->m_sr_bank_r[offset];
	1473	return m_sr_bank_r[offset];
1455	1474	}
1456	1475
1457		static WRITE8_HANDLER( pc6001sr_bank_rn_w )
	1476	WRITE8_MEMBER(pc6001_state::pc6001sr_bank_rn_w)
1458	1477	{
1459		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1460	1478	static const char *const bank_name[8] = { "bank1","bank2","bank3", "bank4", "bank5", "bank6", "bank7", "bank8" };
1461		UINT8 *ROM = space->machine().region("maincpu")->base();
	1479	UINT8 *ROM = machine().region("maincpu")->base();
1462	1480	UINT8 bank_num;
1463	1481
1464		state->m_sr_bank_r[offset] = data;
	1482	m_sr_bank_r[offset] = data;
1465	1483	bank_num = data & 0x0f;
1466	1484
1467	1485	switch(data & 0xf0)
1468	1486	{
1469		case 0xf0: memory_set_bankptr(space->machine(), bank_name[offset], &ROM[SR_SYSROM_1(bank_num)]); break;
1470		case 0xe0: memory_set_bankptr(space->machine(), bank_name[offset], &ROM[SR_SYSROM_2(bank_num)]); break;
1471		case 0xd0: memory_set_bankptr(space->machine(), bank_name[offset], &ROM[SR_CGROM1(bank_num)]); break;
1472		case 0xc0: memory_set_bankptr(space->machine(), bank_name[offset], &ROM[SR_EXROM0(bank_num)]); break;
1473		case 0xb0: memory_set_bankptr(space->machine(), bank_name[offset], &ROM[SR_EXROM1(bank_num)]); break;
1474		case 0x20: memory_set_bankptr(space->machine(), bank_name[offset], &ROM[SR_EXRAM0(bank_num)]); break;
1475		case 0x00: memory_set_bankptr(space->machine(), bank_name[offset], &ROM[SR_WRAM0(bank_num)]); break;
1476		default:   memory_set_bankptr(space->machine(), bank_name[offset], &ROM[SR_NULL(bank_num)]); break;
	1487	case 0xf0: memory_set_bankptr(machine(), bank_name[offset], &ROM[SR_SYSROM_1(bank_num)]); break;
	1488	case 0xe0: memory_set_bankptr(machine(), bank_name[offset], &ROM[SR_SYSROM_2(bank_num)]); break;
	1489	case 0xd0: memory_set_bankptr(machine(), bank_name[offset], &ROM[SR_CGROM1(bank_num)]); break;
	1490	case 0xc0: memory_set_bankptr(machine(), bank_name[offset], &ROM[SR_EXROM0(bank_num)]); break;
	1491	case 0xb0: memory_set_bankptr(machine(), bank_name[offset], &ROM[SR_EXROM1(bank_num)]); break;
	1492	case 0x20: memory_set_bankptr(machine(), bank_name[offset], &ROM[SR_EXRAM0(bank_num)]); break;
	1493	case 0x00: memory_set_bankptr(machine(), bank_name[offset], &ROM[SR_WRAM0(bank_num)]); break;
	1494	default:   memory_set_bankptr(machine(), bank_name[offset], &ROM[SR_NULL(bank_num)]); break;
1477	1495	}
1478	1496	}
1479	1497
1480		static READ8_HANDLER( pc6001sr_bank_wn_r )
	1498	READ8_MEMBER(pc6001_state::pc6001sr_bank_wn_r)
1481	1499	{
1482		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1483		return state->m_sr_bank_w[offset];
	1500	return m_sr_bank_w[offset];
1484	1501	}
1485	1502
1486		static WRITE8_HANDLER( pc6001sr_bank_wn_w )
	1503	WRITE8_MEMBER(pc6001_state::pc6001sr_bank_wn_w)
1487	1504	{
1488		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1489		state->m_sr_bank_w[offset] = data;
	1505	m_sr_bank_w[offset] = data;
1490	1506	}
1491	1507
1492	1508	#define SR_WRAM_BANK_W(_v_) \
1493	1509	{ \
1494		pc6001_state *state = space->machine().driver_data<pc6001_state>(); \
1495		UINT8 *ROM = space->machine().region("maincpu")->base(); \
	1510	UINT8 *ROM = machine().region("maincpu")->base(); \
1496	1511	UINT8 bank_num; \
1497		bank_num = state->m_sr_bank_w[_v_] & 0x0f; \
1498		if((state->m_sr_bank_w[_v_] & 0xf0) != 0x20) \
	1512	bank_num = m_sr_bank_w[_v_] & 0x0f; \
	1513	if((m_sr_bank_w[_v_] & 0xf0) != 0x20) \
1499	1514	ROM[offset+(SR_WRAM0(bank_num))] = data; \
1500	1515	else \
1501	1516	ROM[offset+(SR_EXRAM0(bank_num))] = data; \
1502	1517	} \
1503	1518
1504		static WRITE8_HANDLER( sr_work_ram0_w ) { SR_WRAM_BANK_W(0); }
1505		static WRITE8_HANDLER( sr_work_ram1_w ) { SR_WRAM_BANK_W(1); }
1506		static WRITE8_HANDLER( sr_work_ram2_w ) { SR_WRAM_BANK_W(2); }
1507		static WRITE8_HANDLER( sr_work_ram3_w ) { SR_WRAM_BANK_W(3); }
1508		static WRITE8_HANDLER( sr_work_ram4_w ) { SR_WRAM_BANK_W(4); }
1509		static WRITE8_HANDLER( sr_work_ram5_w ) { SR_WRAM_BANK_W(5); }
1510		static WRITE8_HANDLER( sr_work_ram6_w ) { SR_WRAM_BANK_W(6); }
1511		static WRITE8_HANDLER( sr_work_ram7_w ) { SR_WRAM_BANK_W(7); }
	1519	WRITE8_MEMBER(pc6001_state::sr_work_ram0_w){ SR_WRAM_BANK_W(0); }
	1520	WRITE8_MEMBER(pc6001_state::sr_work_ram1_w){ SR_WRAM_BANK_W(1); }
	1521	WRITE8_MEMBER(pc6001_state::sr_work_ram2_w){ SR_WRAM_BANK_W(2); }
	1522	WRITE8_MEMBER(pc6001_state::sr_work_ram3_w){ SR_WRAM_BANK_W(3); }
	1523	WRITE8_MEMBER(pc6001_state::sr_work_ram4_w){ SR_WRAM_BANK_W(4); }
	1524	WRITE8_MEMBER(pc6001_state::sr_work_ram5_w){ SR_WRAM_BANK_W(5); }
	1525	WRITE8_MEMBER(pc6001_state::sr_work_ram6_w){ SR_WRAM_BANK_W(6); }
	1526	WRITE8_MEMBER(pc6001_state::sr_work_ram7_w){ SR_WRAM_BANK_W(7); }
1512	1527
1513		static WRITE8_HANDLER( pc6001sr_mode_w )
	1528	WRITE8_MEMBER(pc6001_state::pc6001sr_mode_w)
1514	1529	{
1515		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1516		state->m_sr_video_mode = data;
	1530	m_sr_video_mode = data;
1517	1531
1518	1532	if(data & 1)
1519	1533	assert("PC-6001SR in Mk-2 compatibility mode not yet supported!\n");
1520	1534	}
1521	1535
1522		static WRITE8_HANDLER( pc6001sr_vram_bank_w )
	1536	WRITE8_MEMBER(pc6001_state::pc6001sr_vram_bank_w)
1523	1537	{
1524		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1525		UINT8 *work_ram = space->machine().region("maincpu")->base();
	1538	UINT8 *work_ram = machine().region("maincpu")->base();
1526	1539
1527		state->m_video_ram = work_ram + 0x70000 + ((data & 0x0f)*0x1000);
	1540	m_video_ram = work_ram + 0x70000 + ((data & 0x0f)*0x1000);
1528	1541	}
1529	1542
1530		static WRITE8_HANDLER ( pc6001sr_system_latch_w )
	1543	WRITE8_MEMBER(pc6001_state::pc6001sr_system_latch_w)
1531	1544	{
1532		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1533		if((!(state->m_sys_latch & 8)) && data & 0x8) //PLAY tape cmd
	1545	if((!(m_sys_latch & 8)) && data & 0x8) //PLAY tape cmd
1534	1546	{
1535		state->m_cas_switch = 1;
1536		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_ENABLED,CASSETTE_MASK_MOTOR);
1537		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_PLAY,CASSETTE_MASK_UISTATE);
	1547	m_cas_switch = 1;
	1548	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_ENABLED,CASSETTE_MASK_MOTOR);
	1549	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_PLAY,CASSETTE_MASK_UISTATE);
1538	1550	}
1539		if((state->m_sys_latch & 8) && ((data & 0x8) == 0)) //STOP tape cmd
	1551	if((m_sys_latch & 8) && ((data & 0x8) == 0)) //STOP tape cmd
1540	1552	{
1541		state->m_cas_switch = 0;
1542		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
1543		//space->machine().device(CASSETTE_TAG )->change_state(CASSETTE_STOPPED,CASSETTE_MASK_UISTATE);
1544		//state->m_irq_vector = 0x00;
1545		//cputag_set_input_line(space->machine(),"maincpu", 0, ASSERT_LINE);
	1553	m_cas_switch = 0;
	1554	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
	1555	//machine().device(CASSETTE_TAG )->change_state(CASSETTE_STOPPED,CASSETTE_MASK_UISTATE);
	1556	//m_irq_vector = 0x00;
	1557	//cputag_set_input_line(machine(),"maincpu", 0, ASSERT_LINE);
1546	1558	}
1547	1559
1548		state->m_sys_latch = data;
	1560	m_sys_latch = data;
1549	1561
1550		state->m_timer_irq_mask = data & 1;
1551		//vram_bank_change(space->machine(),(state->m_ex_vram_bank & 0x06) | ((state->m_sys_latch & 0x06) << 4));
	1562	m_timer_irq_mask = data & 1;
	1563	//vram_bank_change(machine(),(m_ex_vram_bank & 0x06) | ((m_sys_latch & 0x06) << 4));
1552	1564
1553	1565	//printf("%02x B0\n",data);
1554	1566	}
1555	1567
1556		static WRITE8_HANDLER(necsr_ppi8255_w)
	1568	WRITE8_MEMBER(pc6001_state::necsr_ppi8255_w)
1557	1569	{
1558		pc6001_state *state = space->machine().driver_data<pc6001_state>();
1559	1570	if (offset==3)
1560	1571	{
1561	1572	if(data & 1)
1562		state->m_port_c_8255 |=   1<<((data>>1)&0x07);
	1573	m_port_c_8255 |=   1<<((data>>1)&0x07);
1563	1574	else
1564		state->m_port_c_8255 &= ~(1<<((data>>1)&0x07));
	1575	m_port_c_8255 &= ~(1<<((data>>1)&0x07));
1565	1576
1566	1577	switch(data) {
1567		case 0x08: state->m_port_c_8255 |= 0x88; break;
1568		case 0x09: state->m_port_c_8255 &= 0xf7; break;
1569		case 0x0c: state->m_port_c_8255 |= 0x28; break;
1570		case 0x0d: state->m_port_c_8255 &= 0xf7; break;
	1578	case 0x08: m_port_c_8255 |= 0x88; break;
	1579	case 0x09: m_port_c_8255 &= 0xf7; break;
	1580	case 0x0c: m_port_c_8255 |= 0x28; break;
	1581	case 0x0d: m_port_c_8255 &= 0xf7; break;
1571	1582	default: break;
1572	1583	}
1573	1584
1574		state->m_port_c_8255 |= 0xa8;
	1585	m_port_c_8255 |= 0xa8;
1575	1586
1576	1587	if(0)
1577	1588	{
1578		UINT8 *gfx_data = space->machine().region("gfx1")->base();
1579		UINT8 *ext_rom = space->machine().region("cart_img")->base();
	1589	UINT8 *gfx_data = machine().region("gfx1")->base();
	1590	UINT8 *ext_rom = machine().region("cart_img")->base();
1580	1591
1581	1592	//printf("%02x\n",data);
1582	1593
1583	1594	if((data & 0x0f) == 0x05)
1584		memory_set_bankptr(space->machine(), "bank1", &ext_rom[0x2000]);
	1595	memory_set_bankptr(machine(), "bank1", &ext_rom[0x2000]);
1585	1596	if((data & 0x0f) == 0x04)
1586		memory_set_bankptr(space->machine(), "bank1", &gfx_data[0]);
	1597	memory_set_bankptr(machine(), "bank1", &gfx_data[0]);
1587	1598	}
1588	1599	}
1589		state->m_ppi->write(*space,offset,data);
	1600	m_ppi->write(*&space,offset,data);
1590	1601	}
1591	1602
1592	1603
1593	1604	static ADDRESS_MAP_START(pc6001sr_map, AS_PROGRAM, 8, pc6001_state )
1594	1605	ADDRESS_MAP_UNMAP_HIGH
1595		AM_RANGE(0x0000, 0x1fff) AM_ROMBANK("bank1") AM_WRITE_LEGACY(sr_work_ram0_w)
1596		AM_RANGE(0x2000, 0x3fff) AM_ROMBANK("bank2") AM_WRITE_LEGACY(sr_work_ram1_w)
1597		AM_RANGE(0x4000, 0x5fff) AM_ROMBANK("bank3") AM_WRITE_LEGACY(sr_work_ram2_w)
1598		AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank4") AM_WRITE_LEGACY(sr_work_ram3_w)
1599		AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("bank5") AM_WRITE_LEGACY(sr_work_ram4_w)
1600		AM_RANGE(0xa000, 0xbfff) AM_ROMBANK("bank6") AM_WRITE_LEGACY(sr_work_ram5_w)
1601		AM_RANGE(0xc000, 0xdfff) AM_ROMBANK("bank7") AM_WRITE_LEGACY(sr_work_ram6_w)
1602		AM_RANGE(0xe000, 0xffff) AM_ROMBANK("bank8") AM_WRITE_LEGACY(sr_work_ram7_w)
	1606	AM_RANGE(0x0000, 0x1fff) AM_ROMBANK("bank1") AM_WRITE(sr_work_ram0_w)
	1607	AM_RANGE(0x2000, 0x3fff) AM_ROMBANK("bank2") AM_WRITE(sr_work_ram1_w)
	1608	AM_RANGE(0x4000, 0x5fff) AM_ROMBANK("bank3") AM_WRITE(sr_work_ram2_w)
	1609	AM_RANGE(0x6000, 0x7fff) AM_ROMBANK("bank4") AM_WRITE(sr_work_ram3_w)
	1610	AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("bank5") AM_WRITE(sr_work_ram4_w)
	1611	AM_RANGE(0xa000, 0xbfff) AM_ROMBANK("bank6") AM_WRITE(sr_work_ram5_w)
	1612	AM_RANGE(0xc000, 0xdfff) AM_ROMBANK("bank7") AM_WRITE(sr_work_ram6_w)
	1613	AM_RANGE(0xe000, 0xffff) AM_ROMBANK("bank8") AM_WRITE(sr_work_ram7_w)
1603	1614	ADDRESS_MAP_END
1604	1615
1605	1616	static ADDRESS_MAP_START( pc6001sr_io , AS_IO, 8, pc6001_state )
1606	1617	ADDRESS_MAP_UNMAP_HIGH
1607	1618	ADDRESS_MAP_GLOBAL_MASK(0xff)
1608		AM_RANGE(0x60, 0x67) AM_READWRITE_LEGACY(pc6001sr_bank_rn_r,pc6001sr_bank_rn_w)
1609		AM_RANGE(0x68, 0x6f) AM_READWRITE_LEGACY(pc6001sr_bank_wn_r,pc6001sr_bank_wn_w)
	1619	AM_RANGE(0x60, 0x67) AM_READWRITE(pc6001sr_bank_rn_r,pc6001sr_bank_rn_w)
	1620	AM_RANGE(0x68, 0x6f) AM_READWRITE(pc6001sr_bank_wn_r,pc6001sr_bank_wn_w)
1610	1621	AM_RANGE(0x80, 0x80) AM_DEVREADWRITE("uart", i8251_device, data_r, data_w)
1611	1622	AM_RANGE(0x81, 0x81) AM_DEVREADWRITE("uart", i8251_device, status_r, control_w)
1612	1623
1613		AM_RANGE(0x90, 0x93) AM_MIRROR(0x0c) AM_READWRITE_LEGACY(nec_ppi8255_r, necsr_ppi8255_w)
	1624	AM_RANGE(0x90, 0x93) AM_MIRROR(0x0c) AM_READWRITE(nec_ppi8255_r, necsr_ppi8255_w)
1614	1625
1615	1626	AM_RANGE(0xa0, 0xa0) AM_MIRROR(0x0c) AM_DEVWRITE_LEGACY("ay8910", ay8910_address_w)
1616	1627	AM_RANGE(0xa1, 0xa1) AM_MIRROR(0x0c) AM_DEVWRITE_LEGACY("ay8910", ay8910_data_w)
1617	1628	AM_RANGE(0xa2, 0xa2) AM_MIRROR(0x0c) AM_DEVREAD_LEGACY("ay8910", ay8910_r)
1618	1629	AM_RANGE(0xa3, 0xa3) AM_MIRROR(0x0c) AM_NOP
1619	1630
1620		AM_RANGE(0xb0, 0xb0) AM_WRITE_LEGACY(pc6001sr_system_latch_w)
	1631	AM_RANGE(0xb0, 0xb0) AM_WRITE(pc6001sr_system_latch_w)
1621	1632	/* these are disk related */
1622	1633	//  AM_RANGE(0xb1
1623	1634	//  AM_RANGE(0xb2
1624	1635	//  AM_RANGE(0xb3
1625	1636
1626		//  AM_RANGE(0xc0, 0xc0) AM_WRITE_LEGACY(pc6001m2_col_bank_w)
1627		//  AM_RANGE(0xc1, 0xc1) AM_WRITE_LEGACY(pc6001m2_vram_bank_w)
1628		//  AM_RANGE(0xc2, 0xc2) AM_WRITE_LEGACY(pc6001m2_opt_bank_w)
	1637	//  AM_RANGE(0xc0, 0xc0) AM_WRITE(pc6001m2_col_bank_w)
	1638	//  AM_RANGE(0xc1, 0xc1) AM_WRITE(pc6001m2_vram_bank_w)
	1639	//  AM_RANGE(0xc2, 0xc2) AM_WRITE(pc6001m2_opt_bank_w)
1629	1640
1630		AM_RANGE(0xc8, 0xc8) AM_WRITE_LEGACY(pc6001sr_mode_w)
1631		AM_RANGE(0xc9, 0xc9) AM_WRITE_LEGACY(pc6001sr_vram_bank_w)
	1641	AM_RANGE(0xc8, 0xc8) AM_WRITE(pc6001sr_mode_w)
	1642	AM_RANGE(0xc9, 0xc9) AM_WRITE(pc6001sr_vram_bank_w)
1632	1643
1633		AM_RANGE(0xd0, 0xdf) AM_READWRITE_LEGACY(pc6601_fdc_r,pc6601_fdc_w) // disk device
	1644	AM_RANGE(0xd0, 0xdf) AM_READWRITE(pc6601_fdc_r,pc6601_fdc_w) // disk device
1634	1645
1635		AM_RANGE(0xe0, 0xe3) AM_MIRROR(0x0c) AM_READWRITE_LEGACY(upd7752_reg_r,upd7752_reg_w)
	1646	AM_RANGE(0xe0, 0xe3) AM_MIRROR(0x0c) AM_READWRITE(upd7752_reg_r,upd7752_reg_w)
1636	1647
1637		//  AM_RANGE(0xf0, 0xf0) AM_READWRITE_LEGACY(pc6001m2_bank_r0_r,pc6001m2_bank_r0_w)
1638		//  AM_RANGE(0xf1, 0xf1) AM_READWRITE_LEGACY(pc6001m2_bank_r1_r,pc6001m2_bank_r1_w)
1639		//  AM_RANGE(0xf2, 0xf2) AM_READWRITE_LEGACY(pc6001m2_bank_w0_r,pc6001m2_bank_w0_w)
1640		AM_RANGE(0xf3, 0xf3) AM_WRITE_LEGACY(pc6001m2_0xf3_w)
	1648	//  AM_RANGE(0xf0, 0xf0) AM_READWRITE(pc6001m2_bank_r0_r,pc6001m2_bank_r0_w)
	1649	//  AM_RANGE(0xf1, 0xf1) AM_READWRITE(pc6001m2_bank_r1_r,pc6001m2_bank_r1_w)
	1650	//  AM_RANGE(0xf2, 0xf2) AM_READWRITE(pc6001m2_bank_w0_r,pc6001m2_bank_w0_w)
	1651	AM_RANGE(0xf3, 0xf3) AM_WRITE(pc6001m2_0xf3_w)
1641	1652	//  AM_RANGE(0xf4
1642	1653	//  AM_RANGE(0xf5
1643		AM_RANGE(0xf6, 0xf6) AM_WRITE_LEGACY(pc6001m2_timer_adj_w)
1644		AM_RANGE(0xf7, 0xf7) AM_WRITE_LEGACY(pc6001m2_timer_irqv_w)
	1654	AM_RANGE(0xf6, 0xf6) AM_WRITE(pc6001m2_timer_adj_w)
	1655	AM_RANGE(0xf7, 0xf7) AM_WRITE(pc6001m2_timer_irqv_w)
1645	1656	ADDRESS_MAP_END
1646	1657
1647	1658	/* Input ports */

src/mess/drivers/spc1000.c

r14844	r14845
33	33	spc1000_state *state = machine.driver_data<spc1000_state>();
34	34	return state->m_video_ram[0x1000+(ch&0x7F)*16+line];
35	35	}
	36	DECLARE_WRITE8_MEMBER(spc1000_iplk_w);
	37	DECLARE_READ8_MEMBER(spc1000_iplk_r);
	38	DECLARE_WRITE8_MEMBER(spc1000_video_ram_w);
	39	DECLARE_READ8_MEMBER(spc1000_video_ram_r);
	40	DECLARE_READ8_MEMBER(spc1000_keyboard_r);
36	41	};
37	42
38	43
r14844	r14845
43	48	AM_RANGE( 0x8000, 0xffff ) AM_READ_BANK("bank3") AM_WRITE_BANK("bank4")
44	49	ADDRESS_MAP_END
45	50
46		static WRITE8_HANDLER(spc1000_iplk_w)
	51	WRITE8_MEMBER(spc1000_state::spc1000_iplk_w)
47	52	{
48		spc1000_state *state = space->machine().driver_data<spc1000_state>();
49		state->m_IPLK = state->m_IPLK ? 0 : 1;
50		if (state->m_IPLK == 1) {
51		UINT8 *mem = space->machine().region("maincpu")->base();
52		memory_set_bankptr(space->machine(), "bank1", mem);
53		memory_set_bankptr(space->machine(), "bank3", mem);
	53	m_IPLK = m_IPLK ? 0 : 1;
	54	if (m_IPLK == 1) {
	55	UINT8 *mem = machine().region("maincpu")->base();
	56	memory_set_bankptr(machine(), "bank1", mem);
	57	memory_set_bankptr(machine(), "bank3", mem);
54	58	} else {
55		UINT8 *ram = space->machine().device<ram_device>(RAM_TAG)->pointer();
56		memory_set_bankptr(space->machine(), "bank1", ram);
57		memory_set_bankptr(space->machine(), "bank3", ram + 0x8000);
	59	UINT8 *ram = machine().device<ram_device>(RAM_TAG)->pointer();
	60	memory_set_bankptr(machine(), "bank1", ram);
	61	memory_set_bankptr(machine(), "bank3", ram + 0x8000);
58	62	}
59	63	}
60	64
61		static READ8_HANDLER(spc1000_iplk_r)
	65	READ8_MEMBER(spc1000_state::spc1000_iplk_r)
62	66	{
63		spc1000_state *state = space->machine().driver_data<spc1000_state>();
64		state->m_IPLK = state->m_IPLK ? 0 : 1;
65		if (state->m_IPLK == 1) {
66		UINT8 *mem = space->machine().region("maincpu")->base();
67		memory_set_bankptr(space->machine(), "bank1", mem);
68		memory_set_bankptr(space->machine(), "bank3", mem);
	67	m_IPLK = m_IPLK ? 0 : 1;
	68	if (m_IPLK == 1) {
	69	UINT8 *mem = machine().region("maincpu")->base();
	70	memory_set_bankptr(machine(), "bank1", mem);
	71	memory_set_bankptr(machine(), "bank3", mem);
69	72	} else {
70		UINT8 *ram = space->machine().device<ram_device>(RAM_TAG)->pointer();
71		memory_set_bankptr(space->machine(), "bank1", ram);
72		memory_set_bankptr(space->machine(), "bank3", ram + 0x8000);
	73	UINT8 *ram = machine().device<ram_device>(RAM_TAG)->pointer();
	74	memory_set_bankptr(machine(), "bank1", ram);
	75	memory_set_bankptr(machine(), "bank3", ram + 0x8000);
73	76	}
74	77	return 0;
75	78	}
76	79
77	80
78	81
79		static WRITE8_HANDLER(spc1000_video_ram_w)
	82	WRITE8_MEMBER(spc1000_state::spc1000_video_ram_w)
80	83	{
81		spc1000_state *state = space->machine().driver_data<spc1000_state>();
82		state->m_video_ram[offset] = data;
	84	m_video_ram[offset] = data;
83	85	}
84	86
85		static READ8_HANDLER(spc1000_video_ram_r)
	87	READ8_MEMBER(spc1000_state::spc1000_video_ram_r)
86	88	{
87		spc1000_state *state = space->machine().driver_data<spc1000_state>();
88		return state->m_video_ram[offset];
	89	return m_video_ram[offset];
89	90	}
90	91
91		static READ8_HANDLER(spc1000_keyboard_r) {
	92	READ8_MEMBER(spc1000_state::spc1000_keyboard_r){
92	93	static const char *const keynames[] = {
93	94	"LINE0", "LINE1", "LINE2", "LINE3", "LINE4",
94	95	"LINE5", "LINE6", "LINE7", "LINE8", "LINE9"
95	96	};
96		return input_port_read(space->machine(), keynames[offset]);
	97	return input_port_read(machine(), keynames[offset]);
97	98	}
98	99
99	100	static WRITE8_DEVICE_HANDLER(spc1000_gmode_w)
r14844	r14845
117	118
118	119	static ADDRESS_MAP_START( spc1000_io , AS_IO, 8, spc1000_state )
119	120	ADDRESS_MAP_UNMAP_HIGH
120		AM_RANGE(0x0000, 0x1fff) AM_READWRITE_LEGACY(spc1000_video_ram_r, spc1000_video_ram_w)
	121	AM_RANGE(0x0000, 0x1fff) AM_READWRITE(spc1000_video_ram_r, spc1000_video_ram_w)
121	122	AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE_LEGACY("mc6847", spc1000_gmode_r, spc1000_gmode_w)
122		AM_RANGE(0x8000, 0x8009) AM_READ_LEGACY(spc1000_keyboard_r)
123		AM_RANGE(0xA000, 0xA000) AM_READWRITE_LEGACY(spc1000_iplk_r, spc1000_iplk_w)
	123	AM_RANGE(0x8000, 0x8009) AM_READ(spc1000_keyboard_r)
	124	AM_RANGE(0xA000, 0xA000) AM_READWRITE(spc1000_iplk_r, spc1000_iplk_w)
124	125	AM_RANGE(0x4000, 0x4000) AM_DEVWRITE_LEGACY("ay8910", ay8910_address_w)
125	126	AM_RANGE(0x4001, 0x4001) AM_DEVREADWRITE_LEGACY("ay8910", ay8910_r, ay8910_data_w)
126	127	ADDRESS_MAP_END

src/mess/drivers/sgi_ip6.c

r14844	r14845
31	31	: driver_device(mconfig, type, tag) { }
32	32
33	33	ip6_regs_t m_ip6_regs;
	34	DECLARE_READ32_MEMBER(ip6_unk1_r);
	35	DECLARE_WRITE32_MEMBER(ip6_unk1_w);
	36	DECLARE_READ32_MEMBER(ip6_unk2_r);
	37	DECLARE_WRITE32_MEMBER(ip6_unk2_w);
	38	DECLARE_READ32_MEMBER(ip6_unk3_r);
	39	DECLARE_WRITE32_MEMBER(ip6_unk3_w);
34	40	};
35	41
36	42
r14844	r14845
73	79	***************************************************************************/
74	80
75	81
76		static READ32_HANDLER( ip6_unk1_r )
	82	READ32_MEMBER(sgi_ip6_state::ip6_unk1_r)
77	83	{
78		sgi_ip6_state *state = space->machine().driver_data<sgi_ip6_state>();
79	84	UINT32 ret = 0;
80	85	switch(offset)
81	86	{
82	87	case 0x0000/4:
83	88	if(ACCESSING_BITS_16_31)
84	89	{
85		verboselog(space->machine(), 0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	90	verboselog(machine(), 0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
86	91	}
87	92	if(ACCESSING_BITS_0_15)
88	93	{
89		verboselog(space->machine(), 0, "ip6_unk1_r: Unknown Halfword 0: %08x & %08x\n", state->m_ip6_regs.unknown_half_0, mem_mask );
90		ret |= state->m_ip6_regs.unknown_half_0;
	94	verboselog(machine(), 0, "ip6_unk1_r: Unknown Halfword 0: %08x & %08x\n", m_ip6_regs.unknown_half_0, mem_mask );
	95	ret |= m_ip6_regs.unknown_half_0;
91	96	}
92	97	break;
93	98	default:
94		verboselog(space->machine(), 0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	99	verboselog(machine(), 0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
95	100	break;
96	101	}
97	102	return ret;
98	103	}
99	104
100		static WRITE32_HANDLER( ip6_unk1_w )
	105	WRITE32_MEMBER(sgi_ip6_state::ip6_unk1_w)
101	106	{
102		sgi_ip6_state *state = space->machine().driver_data<sgi_ip6_state>();
103	107	switch(offset)
104	108	{
105	109	case 0x0000/4:
106	110	if(ACCESSING_BITS_16_31)
107	111	{
108		verboselog(space->machine(), 0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	112	verboselog(machine(), 0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
109	113	}
110	114	if(ACCESSING_BITS_0_15)
111	115	{
112		verboselog(space->machine(), 0, "ip6_unk1_w: Unknown Halfword 0 = %04x & %04x\n", data & 0x0000ffff, mem_mask & 0x0000ffff );
113		state->m_ip6_regs.unknown_half_0 = data & 0x0000ffff;
	116	verboselog(machine(), 0, "ip6_unk1_w: Unknown Halfword 0 = %04x & %04x\n", data & 0x0000ffff, mem_mask & 0x0000ffff );
	117	m_ip6_regs.unknown_half_0 = data & 0x0000ffff;
114	118	}
115	119	break;
116	120	default:
117		verboselog(space->machine(), 0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	121	verboselog(machine(), 0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
118	122	break;
119	123	}
120	124	}
121	125
122		static READ32_HANDLER( ip6_unk2_r )
	126	READ32_MEMBER(sgi_ip6_state::ip6_unk2_r)
123	127	{
124		sgi_ip6_state *state = space->machine().driver_data<sgi_ip6_state>();
125	128	UINT32 ret = 0;
126	129	switch(offset)
127	130	{
128	131	case 0x0000/4:
129	132	if(!ACCESSING_BITS_24_31)
130	133	{
131		verboselog(space->machine(), 0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	134	verboselog(machine(), 0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
132	135	}
133	136	if(ACCESSING_BITS_24_31)
134	137	{
135		verboselog(space->machine(), 0, "ip6_unk2_r: Unknown Byte 0 = %02x & %02x\n", state->m_ip6_regs.unknown_byte_0, mem_mask >> 24 );
136		ret |= state->m_ip6_regs.unknown_byte_0 << 24;
	138	verboselog(machine(), 0, "ip6_unk2_r: Unknown Byte 0 = %02x & %02x\n", m_ip6_regs.unknown_byte_0, mem_mask >> 24 );
	139	ret |= m_ip6_regs.unknown_byte_0 << 24;
137	140	}
138	141	break;
139	142	default:
140		verboselog(space->machine(), 0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	143	verboselog(machine(), 0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
141	144	break;
142	145	}
143	146	return ret;
144	147	}
145	148
146		static WRITE32_HANDLER( ip6_unk2_w )
	149	WRITE32_MEMBER(sgi_ip6_state::ip6_unk2_w)
147	150	{
148		sgi_ip6_state *state = space->machine().driver_data<sgi_ip6_state>();
149	151	switch(offset)
150	152	{
151	153	case 0x0000/4:
152	154	if(!ACCESSING_BITS_24_31)
153	155	{
154		verboselog(space->machine(), 0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	156	verboselog(machine(), 0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
155	157	}
156	158	if(ACCESSING_BITS_24_31)
157	159	{
158		verboselog(space->machine(), 0, "ip6_unk2_w: Unknown Byte 0 = %02x & %02x\n", data >> 24, mem_mask >> 24 );
159		state->m_ip6_regs.unknown_byte_0 = (data & 0xff000000) >> 24;
	160	verboselog(machine(), 0, "ip6_unk2_w: Unknown Byte 0 = %02x & %02x\n", data >> 24, mem_mask >> 24 );
	161	m_ip6_regs.unknown_byte_0 = (data & 0xff000000) >> 24;
160	162	}
161	163	break;
162	164	default:
163		verboselog(space->machine(), 0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	165	verboselog(machine(), 0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
164	166	break;
165	167	}
166	168	}
167	169
168		static READ32_HANDLER(ip6_unk3_r)
	170	READ32_MEMBER(sgi_ip6_state::ip6_unk3_r)
169	171	{
170		sgi_ip6_state *state = space->machine().driver_data<sgi_ip6_state>();
171	172	UINT32 ret = 0;
172	173	if(ACCESSING_BITS_16_23)
173	174	{
174		verboselog(space->machine(), 0, "ip6_unk3_r: Unknown Byte 1: %02x & %02x\n", state->m_ip6_regs.unknown_byte_1, (mem_mask >> 16) & 0x000000ff);
175		ret |= state->m_ip6_regs.unknown_byte_1 << 16;
	175	verboselog(machine(), 0, "ip6_unk3_r: Unknown Byte 1: %02x & %02x\n", m_ip6_regs.unknown_byte_1, (mem_mask >> 16) & 0x000000ff);
	176	ret |= m_ip6_regs.unknown_byte_1 << 16;
176	177	}
177	178	else
178	179	{
179		verboselog(space->machine(), 0, "ip6_unk3_r: Unknown address: %08x & %08x\n", 0x1fb00000 + (offset << 2), mem_mask );
	180	verboselog(machine(), 0, "ip6_unk3_r: Unknown address: %08x & %08x\n", 0x1fb00000 + (offset << 2), mem_mask );
180	181	}
181	182	return ret;
182	183	}
183	184
184		static WRITE32_HANDLER(ip6_unk3_w)
	185	WRITE32_MEMBER(sgi_ip6_state::ip6_unk3_w)
185	186	{
186		verboselog(space->machine(), 0, "ip6_unk3_w: Unknown address: %08x = %08x & %08x\n", 0x1fb00000 + (offset << 2), data, mem_mask );
	187	verboselog(machine(), 0, "ip6_unk3_w: Unknown address: %08x = %08x & %08x\n", 0x1fb00000 + (offset << 2), data, mem_mask );
187	188	}
188	189
189	190	static INTERRUPT_GEN( sgi_ip6_vbl )
r14844	r14845
207	208	***************************************************************************/
208	209
209	210	static ADDRESS_MAP_START( sgi_ip6_map, AS_PROGRAM, 32, sgi_ip6_state )
210		AM_RANGE( 0x1f880000, 0x1f880003 ) AM_READWRITE_LEGACY(ip6_unk1_r, ip6_unk1_w)
211		AM_RANGE( 0x1fb00000, 0x1fb00003 ) AM_READWRITE_LEGACY(ip6_unk3_r, ip6_unk3_w)
212		AM_RANGE( 0x1fbc004c, 0x1fbc004f ) AM_READWRITE_LEGACY(ip6_unk2_r, ip6_unk2_w)
	211	AM_RANGE( 0x1f880000, 0x1f880003 ) AM_READWRITE(ip6_unk1_r, ip6_unk1_w)
	212	AM_RANGE( 0x1fb00000, 0x1fb00003 ) AM_READWRITE(ip6_unk3_r, ip6_unk3_w)
	213	AM_RANGE( 0x1fbc004c, 0x1fbc004f ) AM_READWRITE(ip6_unk2_r, ip6_unk2_w)
213	214	AM_RANGE( 0x1fc00000, 0x1fc3ffff ) AM_ROM AM_REGION( "user1", 0 )
214	215	ADDRESS_MAP_END
215	216

src/mess/drivers/smc777.c

r14844	r14845
52	52	UINT8 m_keyb_direct;
53	53	UINT8 m_pal_mode;
54	54	UINT8 m_keyb_cmd;
	55	DECLARE_WRITE8_MEMBER(smc777_6845_w);
	56	DECLARE_READ8_MEMBER(smc777_vram_r);
	57	DECLARE_READ8_MEMBER(smc777_attr_r);
	58	DECLARE_READ8_MEMBER(smc777_pcg_r);
	59	DECLARE_WRITE8_MEMBER(smc777_vram_w);
	60	DECLARE_WRITE8_MEMBER(smc777_attr_w);
	61	DECLARE_WRITE8_MEMBER(smc777_pcg_w);
	62	DECLARE_READ8_MEMBER(smc777_fbuf_r);
	63	DECLARE_WRITE8_MEMBER(smc777_fbuf_w);
	64	DECLARE_READ8_MEMBER(smc777_fdc1_r);
	65	DECLARE_WRITE8_MEMBER(smc777_fdc1_w);
	66	DECLARE_READ8_MEMBER(key_r);
	67	DECLARE_WRITE8_MEMBER(key_w);
	68	DECLARE_WRITE8_MEMBER(border_col_w);
	69	DECLARE_READ8_MEMBER(system_input_r);
	70	DECLARE_WRITE8_MEMBER(system_output_w);
	71	DECLARE_READ8_MEMBER(smc777_joystick_r);
	72	DECLARE_WRITE8_MEMBER(smc777_color_mode_w);
	73	DECLARE_WRITE8_MEMBER(smc777_ramdac_w);
	74	DECLARE_READ8_MEMBER(display_reg_r);
	75	DECLARE_WRITE8_MEMBER(display_reg_w);
	76	DECLARE_READ8_MEMBER(smc777_mem_r);
	77	DECLARE_WRITE8_MEMBER(smc777_mem_w);
	78	DECLARE_READ8_MEMBER(smc777_irq_mask_r);
	79	DECLARE_WRITE8_MEMBER(smc777_irq_mask_w);
	80	DECLARE_READ8_MEMBER(smc777_io_r);
	81	DECLARE_WRITE8_MEMBER(smc777_io_w);
55	82	};
56	83
57	84
r14844	r14845
197	224	return 0;
198	225	}
199	226
200		static WRITE8_HANDLER( smc777_6845_w )
	227	WRITE8_MEMBER(smc777_state::smc777_6845_w)
201	228	{
202		smc777_state *state = space->machine().driver_data<smc777_state>();
203	229	if(offset == 0)
204	230	{
205		state->m_addr_latch = data;
206		//mc6845_address_w(space->machine().device("crtc"), 0,data);
	231	m_addr_latch = data;
	232	//mc6845_address_w(machine().device("crtc"), 0,data);
207	233	}
208	234	else
209	235	{
210		if(state->m_addr_latch == 0x0a)
211		state->m_cursor_raster = data;
212		else if(state->m_addr_latch == 0x0e)
213		state->m_cursor_addr = ((data<<8) & 0x3f00) | (state->m_cursor_addr & 0xff);
214		else if(state->m_addr_latch == 0x0f)
215		state->m_cursor_addr = (state->m_cursor_addr & 0x3f00) | (data & 0xff);
	236	if(m_addr_latch == 0x0a)
	237	m_cursor_raster = data;
	238	else if(m_addr_latch == 0x0e)
	239	m_cursor_addr = ((data<<8) & 0x3f00) | (m_cursor_addr & 0xff);
	240	else if(m_addr_latch == 0x0f)
	241	m_cursor_addr = (m_cursor_addr & 0x3f00) | (data & 0xff);
216	242
217		//mc6845_register_w(space->machine().device("crtc"), 0,data);
	243	//mc6845_register_w(machine().device("crtc"), 0,data);
218	244	}
219	245	}
220	246
221		static READ8_HANDLER( smc777_vram_r )
	247	READ8_MEMBER(smc777_state::smc777_vram_r)
222	248	{
223		UINT8 *vram = space->machine().region("vram")->base();
	249	UINT8 *vram = machine().region("vram")->base();
224	250	UINT16 vram_index;
225	251
226	252	vram_index  = ((offset & 0x0007) << 8);
r14844	r14845
229	255	return vram[vram_index];
230	256	}
231	257
232		static READ8_HANDLER( smc777_attr_r )
	258	READ8_MEMBER(smc777_state::smc777_attr_r)
233	259	{
234		UINT8 *attr = space->machine().region("attr")->base();
	260	UINT8 *attr = machine().region("attr")->base();
235	261	UINT16 vram_index;
236	262
237	263	vram_index  = ((offset & 0x0007) << 8);
r14844	r14845
240	266	return attr[vram_index];
241	267	}
242	268
243		static READ8_HANDLER( smc777_pcg_r )
	269	READ8_MEMBER(smc777_state::smc777_pcg_r)
244	270	{
245		UINT8 *pcg = space->machine().region("pcg")->base();
	271	UINT8 *pcg = machine().region("pcg")->base();
246	272	UINT16 vram_index;
247	273
248	274	vram_index  = ((offset & 0x0007) << 8);
r14844	r14845
251	277	return pcg[vram_index];
252	278	}
253	279
254		static WRITE8_HANDLER( smc777_vram_w )
	280	WRITE8_MEMBER(smc777_state::smc777_vram_w)
255	281	{
256		UINT8 *vram = space->machine().region("vram")->base();
	282	UINT8 *vram = machine().region("vram")->base();
257	283	UINT16 vram_index;
258	284
259	285	vram_index  = ((offset & 0x0007) << 8);
r14844	r14845
262	288	vram[vram_index] = data;
263	289	}
264	290
265		static WRITE8_HANDLER( smc777_attr_w )
	291	WRITE8_MEMBER(smc777_state::smc777_attr_w)
266	292	{
267		UINT8 *attr = space->machine().region("attr")->base();
	293	UINT8 *attr = machine().region("attr")->base();
268	294	UINT16 vram_index;
269	295
270	296	vram_index  = ((offset & 0x0007) << 8);
r14844	r14845
273	299	attr[vram_index] = data;
274	300	}
275	301
276		static WRITE8_HANDLER( smc777_pcg_w )
	302	WRITE8_MEMBER(smc777_state::smc777_pcg_w)
277	303	{
278		UINT8 *pcg = space->machine().region("pcg")->base();
	304	UINT8 *pcg = machine().region("pcg")->base();
279	305	UINT16 vram_index;
280	306
281	307	vram_index  = ((offset & 0x0007) << 8);
r14844	r14845
283	309
284	310	pcg[vram_index] = data;
285	311
286		gfx_element_mark_dirty(space->machine().gfx[0], vram_index >> 3);
	312	gfx_element_mark_dirty(machine().gfx[0], vram_index >> 3);
287	313	}
288	314
289		static READ8_HANDLER( smc777_fbuf_r )
	315	READ8_MEMBER(smc777_state::smc777_fbuf_r)
290	316	{
291		UINT8 *fbuf = space->machine().region("fbuf")->base();
	317	UINT8 *fbuf = machine().region("fbuf")->base();
292	318	UINT16 vram_index;
293	319
294	320	vram_index  = ((offset & 0x007f) << 8);
r14844	r14845
297	323	return fbuf[vram_index];
298	324	}
299	325
300		static WRITE8_HANDLER( smc777_fbuf_w )
	326	WRITE8_MEMBER(smc777_state::smc777_fbuf_w)
301	327	{
302		UINT8 *fbuf = space->machine().region("fbuf")->base();
	328	UINT8 *fbuf = machine().region("fbuf")->base();
303	329	UINT16 vram_index;
304	330
305	331	vram_index  = ((offset & 0x00ff) << 8);
r14844	r14845
324	350	}
325	351	}
326	352
327		static READ8_HANDLER( smc777_fdc1_r )
	353	READ8_MEMBER(smc777_state::smc777_fdc1_r)
328	354	{
329		smc777_state *state = space->machine().driver_data<smc777_state>();
330		device_t* dev = space->machine().device("fdc");
	355	device_t* dev = machine().device("fdc");
331	356
332		check_floppy_inserted(space->machine());
	357	check_floppy_inserted(machine());
333	358
334	359	switch(offset)
335	360	{
r14844	r14845
342	367	case 0x03:
343	368	return wd17xx_data_r(dev,offset) ^ 0xff;
344	369	case 0x04: //irq / drq status
345		//popmessage("%02x %02x\n",state->m_fdc_irq_flag,state->m_fdc_drq_flag);
	370	//popmessage("%02x %02x\n",m_fdc_irq_flag,m_fdc_drq_flag);
346	371
347		return (state->m_fdc_irq_flag ? 0x80 : 0x00) | (state->m_fdc_drq_flag ? 0x00 : 0x40);
	372	return (m_fdc_irq_flag ? 0x80 : 0x00) | (m_fdc_drq_flag ? 0x00 : 0x40);
348	373	}
349	374
350	375	return 0x00;
351	376	}
352	377
353		static WRITE8_HANDLER( smc777_fdc1_w )
	378	WRITE8_MEMBER(smc777_state::smc777_fdc1_w)
354	379	{
355		device_t* dev = space->machine().device("fdc");
	380	device_t* dev = machine().device("fdc");
356	381
357		check_floppy_inserted(space->machine());
	382	check_floppy_inserted(machine());
358	383
359	384	switch(offset)
360	385	{
r14844	r14845
392	417	drvstate->m_fdc_drq_flag = state;
393	418	}
394	419
395		static READ8_HANDLER( key_r )
	420	READ8_MEMBER(smc777_state::key_r)
396	421	{
397		smc777_state *state = space->machine().driver_data<smc777_state>();
398	422	/*
399	423	-x-- ---- shift key
400	424	---- -x-- MCU data ready
401	425	---- ---x handshake bit?
402	426	*/
403	427
404		switch(state->m_keyb_cmd)
	428	switch(m_keyb_cmd)
405	429	{
406	430	case 0x00: //poll keyboard input
407	431	{
408	432	if(offset == 0)
409		state->m_keyb_press_flag = 0;
	433	m_keyb_press_flag = 0;
410	434
411		return (offset == 0) ? state->m_keyb_press : ((state->m_shift_press_flag << 6) | (state->m_keyb_press_flag << 2) | (state->m_keyb_press_flag));
	435	return (offset == 0) ? m_keyb_press : ((m_shift_press_flag << 6) | (m_keyb_press_flag << 2) | (m_keyb_press_flag));
412	436	}
413	437	break;
414	438	default:
415	439	{
416	440	//if(offset == 1)
417		//  printf("Unknown keyboard command %02x read-back\n",state->m_keyb_cmd);
	441	//  printf("Unknown keyboard command %02x read-back\n",m_keyb_cmd);
418	442
419		return (offset == 0) ? 0x00 : (space->machine().rand() & 0x5);
	443	return (offset == 0) ? 0x00 : (machine().rand() & 0x5);
420	444	}
421	445	}
422	446
r14844	r14845
424	448	}
425	449
426	450	/* TODO: the packet commands strikes me as something I've already seen before, don't remember where however ... */
427		static WRITE8_HANDLER( key_w )
	451	WRITE8_MEMBER(smc777_state::key_w)
428	452	{
429		smc777_state *state = space->machine().driver_data<smc777_state>();
430	453
431	454	if(offset == 1) //keyboard command
432		state->m_keyb_cmd = data;
	455	m_keyb_cmd = data;
433	456	else
434	457	{
435	458	// keyboard command param
436	459	}
437	460	}
438	461
439		static WRITE8_HANDLER( border_col_w )
	462	WRITE8_MEMBER(smc777_state::border_col_w)
440	463	{
441		smc777_state *state = space->machine().driver_data<smc777_state>();
442	464	if(data & 0xf0)
443	465	printf("Special border color enabled %02x\n",data);
444	466
445		state->m_backdrop_pen = data & 0xf;
	467	m_backdrop_pen = data & 0xf;
446	468	}
447	469
448	470
449		static READ8_HANDLER( system_input_r )
	471	READ8_MEMBER(smc777_state::system_input_r)
450	472	{
451		smc777_state *state = space->machine().driver_data<smc777_state>();
452	473
453		printf("System FF R %02x\n",state->m_system_data & 0x0f);
	474	printf("System FF R %02x\n",m_system_data & 0x0f);
454	475
455		switch(state->m_system_data & 0x0f)
	476	switch(m_system_data & 0x0f)
456	477	{
457	478	case 0x00:
458		return ((state->m_raminh & 1) << 4); //unknown bit, Dragon's Alphabet and Bird Crush relies on this for correct colors
	479	return ((m_raminh & 1) << 4); //unknown bit, Dragon's Alphabet and Bird Crush relies on this for correct colors
459	480	}
460	481
461		return state->m_system_data;
	482	return m_system_data;
462	483	}
463	484
464	485
465	486
466		static WRITE8_HANDLER( system_output_w )
	487	WRITE8_MEMBER(smc777_state::system_output_w)
467	488	{
468		smc777_state *state = space->machine().driver_data<smc777_state>();
469	489	/*
470	490	---x 0000 ram inibit signal
471	491	---x 1001 beep
472	492	all the rest is unknown at current time
473	493	*/
474		state->m_system_data = data;
475		switch(state->m_system_data & 0x0f)
	494	m_system_data = data;
	495	switch(m_system_data & 0x0f)
476	496	{
477	497	case 0x00:
478		state->m_raminh_pending_change = ((data & 0x10) >> 4) ^ 1;
479		state->m_raminh_prefetch = (UINT8)(cpu_get_reg(&space->device(), Z80_R)) & 0x7f;
	498	m_raminh_pending_change = ((data & 0x10) >> 4) ^ 1;
	499	m_raminh_prefetch = (UINT8)(cpu_get_reg(&space.device(), Z80_R)) & 0x7f;
480	500	break;
481	501	case 0x02: printf("Interlace %s\n",data & 0x10 ? "on" : "off"); break;
482		case 0x05: beep_set_state(space->machine().device(BEEPER_TAG),data & 0x10); break;
	502	case 0x05: beep_set_state(machine().device(BEEPER_TAG),data & 0x10); break;
483	503	default: printf("System FF W %02x\n",data); break;
484	504	}
485	505	}
486	506
487	507	/* presumably SMC-777 specific */
488		static READ8_HANDLER( smc777_joystick_r )
	508	READ8_MEMBER(smc777_state::smc777_joystick_r)
489	509	{
490		//smc777_state *state = space->machine().driver_data<smc777_state>();
491	510
492		return input_port_read(space->machine(), "JOY_1P");
	511	return input_port_read(machine(), "JOY_1P");
493	512	}
494	513
495		static WRITE8_HANDLER( smc777_color_mode_w )
	514	WRITE8_MEMBER(smc777_state::smc777_color_mode_w)
496	515	{
497		smc777_state *state = space->machine().driver_data<smc777_state>();
498	516
499	517	switch(data & 0x0f)
500	518	{
501		case 0x06: state->m_pal_mode = (data & 0x10) ^ 0x10; break;
	519	case 0x06: m_pal_mode = (data & 0x10) ^ 0x10; break;
502	520	default: printf("Color FF %02x\n",data); break;
503	521	}
504	522	}
505	523
506		static WRITE8_HANDLER( smc777_ramdac_w )
	524	WRITE8_MEMBER(smc777_state::smc777_ramdac_w)
507	525	{
508		smc777_state *state = space->machine().driver_data<smc777_state>();
509	526	UINT8 pal_index;
510	527	pal_index = (offset & 0xf00) >> 8;
511	528
r14844	r14845
514	531
515	532	switch((offset & 0x3000) >> 12)
516	533	{
517		case 0: state->m_pal.r = (data & 0xf0) >> 4; palette_set_color_rgb(space->machine(), pal_index, pal4bit(state->m_pal.r), pal4bit(state->m_pal.g), pal4bit(state->m_pal.b)); break;
518		case 1: state->m_pal.g = (data & 0xf0) >> 4; palette_set_color_rgb(space->machine(), pal_index, pal4bit(state->m_pal.r), pal4bit(state->m_pal.g), pal4bit(state->m_pal.b)); break;
519		case 2: state->m_pal.b = (data & 0xf0) >> 4; palette_set_color_rgb(space->machine(), pal_index, pal4bit(state->m_pal.r), pal4bit(state->m_pal.g), pal4bit(state->m_pal.b)); break;
	534	case 0: m_pal.r = (data & 0xf0) >> 4; palette_set_color_rgb(machine(), pal_index, pal4bit(m_pal.r), pal4bit(m_pal.g), pal4bit(m_pal.b)); break;
	535	case 1: m_pal.g = (data & 0xf0) >> 4; palette_set_color_rgb(machine(), pal_index, pal4bit(m_pal.r), pal4bit(m_pal.g), pal4bit(m_pal.b)); break;
	536	case 2: m_pal.b = (data & 0xf0) >> 4; palette_set_color_rgb(machine(), pal_index, pal4bit(m_pal.r), pal4bit(m_pal.g), pal4bit(m_pal.b)); break;
520	537	case 3: printf("RAMdac used with gradient index = 3! pal_index = %02x data = %02x\n",pal_index,data); break;
521	538	}
522	539	}
523	540
524		static READ8_HANDLER( display_reg_r )
	541	READ8_MEMBER(smc777_state::display_reg_r)
525	542	{
526		smc777_state *state = space->machine().driver_data<smc777_state>();
527		return state->m_display_reg;
	543	return m_display_reg;
528	544	}
529	545
530	546	/* x */
531		static WRITE8_HANDLER( display_reg_w )
	547	WRITE8_MEMBER(smc777_state::display_reg_w)
532	548	{
533		smc777_state *state = space->machine().driver_data<smc777_state>();
534	549	/*
535	550	x--- ---- width 80 / 40 switch (0 = 640 x 200 1 = 320 x 200)
536	551	---- -x-- mode select?
537	552	*/
538	553
539	554	{
540		if((state->m_display_reg & 0x80) != (data & 0x80))
	555	if((m_display_reg & 0x80) != (data & 0x80))
541	556	{
542		rectangle visarea = space->machine().primary_screen->visible_area();
	557	rectangle visarea = machine().primary_screen->visible_area();
543	558	int x_width;
544	559
545	560	x_width = (data & 0x80) ? 320 : 640;
546	561
547	562	visarea.set(0, (x_width+(CRTC_MIN_X*2)) - 1, 0, (200+(CRTC_MIN_Y*2)) - 1);
548	563
549		space->machine().primary_screen->configure(660, 220, visarea, space->machine().primary_screen->frame_period().attoseconds);
	564	machine().primary_screen->configure(660, 220, visarea, machine().primary_screen->frame_period().attoseconds);
550	565	}
551	566	}
552	567
553		state->m_display_reg = data;
	568	m_display_reg = data;
554	569	}
555	570
556		static READ8_HANDLER( smc777_mem_r )
	571	READ8_MEMBER(smc777_state::smc777_mem_r)
557	572	{
558		smc777_state *state = space->machine().driver_data<smc777_state>();
559		UINT8 *wram = space->machine().region("wram")->base();
560		UINT8 *bios = space->machine().region("bios")->base();
	573	UINT8 *wram = machine().region("wram")->base();
	574	UINT8 *bios = machine().region("bios")->base();
561	575	UINT8 z80_r;
562	576
563		if(state->m_raminh_prefetch != 0xff) //do the bankswitch AFTER that the prefetch instruction is executed (FIXME: this is an hackish implementation)
	577	if(m_raminh_prefetch != 0xff) //do the bankswitch AFTER that the prefetch instruction is executed (FIXME: this is an hackish implementation)
564	578	{
565		z80_r = (UINT8)cpu_get_reg(&space->device(), Z80_R);
	579	z80_r = (UINT8)cpu_get_reg(&space.device(), Z80_R);
566	580
567		if(z80_r == ((state->m_raminh_prefetch+2) & 0x7f))
	581	if(z80_r == ((m_raminh_prefetch+2) & 0x7f))
568	582	{
569		state->m_raminh = state->m_raminh_pending_change;
570		state->m_raminh_prefetch = 0xff;
	583	m_raminh = m_raminh_pending_change;
	584	m_raminh_prefetch = 0xff;
571	585	}
572	586	}
573	587
574		if(state->m_raminh == 1 && ((offset & 0xc000) == 0))
	588	if(m_raminh == 1 && ((offset & 0xc000) == 0))
575	589	return bios[offset];
576	590
577	591	return wram[offset];
578	592	}
579	593
580		static WRITE8_HANDLER( smc777_mem_w )
	594	WRITE8_MEMBER(smc777_state::smc777_mem_w)
581	595	{
582		//smc777_state *state = space->machine().driver_data<smc777_state>();
583		UINT8 *wram = space->machine().region("wram")->base();
	596	UINT8 *wram = machine().region("wram")->base();
584	597
585	598	wram[offset] = data;
586	599	}
587	600
588		static READ8_HANDLER( smc777_irq_mask_r )
	601	READ8_MEMBER(smc777_state::smc777_irq_mask_r)
589	602	{
590		smc777_state *state = space->machine().driver_data<smc777_state>();
591	603
592		return state->m_irq_mask;
	604	return m_irq_mask;
593	605	}
594	606
595		static WRITE8_HANDLER( smc777_irq_mask_w )
	607	WRITE8_MEMBER(smc777_state::smc777_irq_mask_w)
596	608	{
597		smc777_state *state = space->machine().driver_data<smc777_state>();
598	609
599	610	if(data & 0xfe)
600	611	printf("Irq mask = %02x\n",data & 0xfe);
601	612
602		state->m_irq_mask = data & 1;
	613	m_irq_mask = data & 1;
603	614	}
604	615
605	616	static ADDRESS_MAP_START(smc777_mem, AS_PROGRAM, 8, smc777_state )
606	617	ADDRESS_MAP_UNMAP_HIGH
607		AM_RANGE(0x0000, 0xffff) AM_READWRITE_LEGACY(smc777_mem_r,smc777_mem_w)
	618	AM_RANGE(0x0000, 0xffff) AM_READWRITE(smc777_mem_r,smc777_mem_w)
608	619	ADDRESS_MAP_END
609	620
610		static READ8_HANDLER( smc777_io_r )
	621	READ8_MEMBER(smc777_state::smc777_io_r)
611	622	{
612	623	UINT8 low_offs;
613	624
r14844	r14845
619	630	else if(low_offs >= 0x18 && low_offs <= 0x19) { logerror("6845 read %02x",low_offs & 1); }
620	631	else if(low_offs >= 0x1a && low_offs <= 0x1b) { return key_r(space,low_offs & 1); }
621	632	else if(low_offs == 0x1c)                 { return system_input_r(space,0); }
622		else if(low_offs == 0x1d)                 { logerror("System and control data R PC=%04x\n",cpu_get_pc(&space->device())); return 0xff; }
	633	else if(low_offs == 0x1d)                 { logerror("System and control data R PC=%04x\n",cpu_get_pc(&space.device())); return 0xff; }
623	634	else if(low_offs == 0x20)                 { return display_reg_r(space,0); }
624	635	else if(low_offs == 0x21)                 { return smc777_irq_mask_r(space,0); }
625		else if(low_offs == 0x25)                 { logerror("RTC read PC=%04x\n",cpu_get_pc(&space->device())); return 0xff; }
626		else if(low_offs == 0x26)                 { logerror("RS-232c RX %04x\n",cpu_get_pc(&space->device())); return 0xff; }
	636	else if(low_offs == 0x25)                 { logerror("RTC read PC=%04x\n",cpu_get_pc(&space.device())); return 0xff; }
	637	else if(low_offs == 0x26)                 { logerror("RS-232c RX %04x\n",cpu_get_pc(&space.device())); return 0xff; }
627	638	else if(low_offs >= 0x28 && low_offs <= 0x2c) { logerror("FDC 2 read %02x\n",low_offs & 7); return 0xff; }
628	639	else if(low_offs >= 0x2d && low_offs <= 0x2f) { logerror("RS-232c no. 2 read %02x\n",low_offs & 3); return 0xff; }
629	640	else if(low_offs >= 0x30 && low_offs <= 0x34) { return smc777_fdc1_r(space,low_offs & 7); }
r14844	r14845
641	652	else if(low_offs == 0x7e || low_offs == 0x7f) { logerror("Kanji ROM read %02x\n",low_offs & 1); }
642	653	else if(low_offs >= 0x80)                 { return smc777_fbuf_r(space,offset & 0xff7f); }
643	654
644		logerror("Undefined read at %04x offset = %02x\n",cpu_get_pc(&space->device()),low_offs);
	655	logerror("Undefined read at %04x offset = %02x\n",cpu_get_pc(&space.device()),low_offs);
645	656	return 0xff;
646	657	}
647	658
648		static WRITE8_HANDLER( smc777_io_w )
	659	WRITE8_MEMBER(smc777_state::smc777_io_w)
649	660	{
650	661	UINT8 low_offs;
651	662
r14844	r14845
675	686	else if(low_offs >= 0x48 && low_offs <= 0x4f) { logerror("HDD (Winchester) write %02x %02x\n",low_offs & 1,data); } //might be 0x48 - 0x50
676	687	else if(low_offs == 0x51)                 { smc777_color_mode_w(space,0,data); }
677	688	else if(low_offs == 0x52)                 { smc777_ramdac_w(space,offset & 0xff00,data); }
678		else if(low_offs == 0x53)                 { sn76496_w(space->machine().device("sn1"),0,data); }
	689	else if(low_offs == 0x53)                 { sn76496_w(machine().device("sn1"),0,data); }
679	690	else if(low_offs >= 0x54 && low_offs <= 0x59) { logerror("VTR Controller write [%02x] %02x\n",low_offs & 7,data); }
680	691	else if(low_offs == 0x5a || low_offs == 0x5b) { logerror("RAM Banking write [%02x] %02x\n",low_offs & 1,data); }
681	692	else if(low_offs == 0x70)                 { logerror("Auto-start ROM write %02x\n",data); }
r14844	r14845
683	694	else if(low_offs == 0x75)                 { logerror("VTR Controller ROM write %02x\n",data); }
684	695	else if(low_offs == 0x7e || low_offs == 0x7f) { logerror("Kanji ROM write [%02x] %02x\n",low_offs & 1,data); }
685	696	else if(low_offs >= 0x80)                 { smc777_fbuf_w(space,offset & 0xff7f,data); }
686		else                                { logerror("Undefined write at %04x offset = %02x data = %02x\n",cpu_get_pc(&space->device()),low_offs,data); }
	697	else                                { logerror("Undefined write at %04x offset = %02x data = %02x\n",cpu_get_pc(&space.device()),low_offs,data); }
687	698	}
688	699
689	700	static ADDRESS_MAP_START( smc777_io , AS_IO, 8, smc777_state )
690	701	ADDRESS_MAP_UNMAP_HIGH
691		AM_RANGE(0x0000, 0xffff) AM_READWRITE_LEGACY(smc777_io_r,smc777_io_w)
	702	AM_RANGE(0x0000, 0xffff) AM_READWRITE(smc777_io_r,smc777_io_w)
692	703	ADDRESS_MAP_END
693	704
694	705	/* Input ports */

src/mess/drivers/rt1715.c

r14844	r14845
35	35
36	36	int m_led1_val;
37	37	int m_led2_val;
	38	DECLARE_WRITE8_MEMBER(rt1715_floppy_enable);
	39	DECLARE_READ8_MEMBER(k7658_led1_r);
	40	DECLARE_READ8_MEMBER(k7658_led2_r);
	41	DECLARE_READ8_MEMBER(k7658_data_r);
	42	DECLARE_WRITE8_MEMBER(k7658_data_w);
	43	DECLARE_WRITE8_MEMBER(rt1715_rom_disable);
38	44	};
39	45
40	46
r14844	r14845
42	48	FLOPPY
43	49	***************************************************************************/
44	50
45		static WRITE8_HANDLER( rt1715_floppy_enable )
	51	WRITE8_MEMBER(rt1715_state::rt1715_floppy_enable)
46	52	{
47		logerror("%s: rt1715_floppy_enable %02x\n", space->machine().describe_context(), data);
	53	logerror("%s: rt1715_floppy_enable %02x\n", machine().describe_context(), data);
48	54	}
49	55
50	56
r14844	r14845
53	59	***************************************************************************/
54	60
55	61	/* si/so led */
56		static READ8_HANDLER( k7658_led1_r )
	62	READ8_MEMBER(rt1715_state::k7658_led1_r)
57	63	{
58		rt1715_state *state = space->machine().driver_data<rt1715_state>();
59		state->m_led1_val ^= 1;
60		logerror("%s: k7658_led1_r %02x\n", space->machine().describe_context(), state->m_led1_val);
	64	m_led1_val ^= 1;
	65	logerror("%s: k7658_led1_r %02x\n", machine().describe_context(), m_led1_val);
61	66	return 0xff;
62	67	}
63	68
64	69	/* caps led */
65		static READ8_HANDLER( k7658_led2_r )
	70	READ8_MEMBER(rt1715_state::k7658_led2_r)
66	71	{
67		rt1715_state *state = space->machine().driver_data<rt1715_state>();
68		state->m_led2_val ^= 1;
69		logerror("%s: k7658_led2_r %02x\n", space->machine().describe_context(), state->m_led2_val);
	72	m_led2_val ^= 1;
	73	logerror("%s: k7658_led2_r %02x\n", machine().describe_context(), m_led2_val);
70	74	return 0xff;
71	75	}
72	76
73	77	/* read key state */
74		static READ8_HANDLER( k7658_data_r )
	78	READ8_MEMBER(rt1715_state::k7658_data_r)
75	79	{
76	80	UINT8 result = 0xff;
77	81
78		if (BIT(offset,  0)) result &= input_port_read(space->machine(), "row_00");
79		if (BIT(offset,  1)) result &= input_port_read(space->machine(), "row_10");
80		if (BIT(offset,  2)) result &= input_port_read(space->machine(), "row_20");
81		if (BIT(offset,  3)) result &= input_port_read(space->machine(), "row_30");
82		if (BIT(offset,  4)) result &= input_port_read(space->machine(), "row_40");
83		if (BIT(offset,  5)) result &= input_port_read(space->machine(), "row_50");
84		if (BIT(offset,  6)) result &= input_port_read(space->machine(), "row_60");
85		if (BIT(offset,  7)) result &= input_port_read(space->machine(), "row_70");
86		if (BIT(offset,  8)) result &= input_port_read(space->machine(), "row_08");
87		if (BIT(offset,  9)) result &= input_port_read(space->machine(), "row_18");
88		if (BIT(offset, 10)) result &= input_port_read(space->machine(), "row_28");
89		if (BIT(offset, 11)) result &= input_port_read(space->machine(), "row_38");
90		if (BIT(offset, 12)) result &= input_port_read(space->machine(), "row_48");
	82	if (BIT(offset,  0)) result &= input_port_read(machine(), "row_00");
	83	if (BIT(offset,  1)) result &= input_port_read(machine(), "row_10");
	84	if (BIT(offset,  2)) result &= input_port_read(machine(), "row_20");
	85	if (BIT(offset,  3)) result &= input_port_read(machine(), "row_30");
	86	if (BIT(offset,  4)) result &= input_port_read(machine(), "row_40");
	87	if (BIT(offset,  5)) result &= input_port_read(machine(), "row_50");
	88	if (BIT(offset,  6)) result &= input_port_read(machine(), "row_60");
	89	if (BIT(offset,  7)) result &= input_port_read(machine(), "row_70");
	90	if (BIT(offset,  8)) result &= input_port_read(machine(), "row_08");
	91	if (BIT(offset,  9)) result &= input_port_read(machine(), "row_18");
	92	if (BIT(offset, 10)) result &= input_port_read(machine(), "row_28");
	93	if (BIT(offset, 11)) result &= input_port_read(machine(), "row_38");
	94	if (BIT(offset, 12)) result &= input_port_read(machine(), "row_48");
91	95
92	96	return result;
93	97	}
94	98
95	99	/* serial output on D0 */
96		static WRITE8_HANDLER( k7658_data_w )
	100	WRITE8_MEMBER(rt1715_state::k7658_data_w)
97	101	{
98		logerror("%s: k7658_data_w %02x\n", space->machine().describe_context(), BIT(data, 0));
	102	logerror("%s: k7658_data_w %02x\n", machine().describe_context(), BIT(data, 0));
99	103	}
100	104
101	105
r14844	r14845
115	119	memory_set_bankptr(machine, "bank1", machine.region("ipl")->base());
116	120	}
117	121
118		static WRITE8_HANDLER( rt1715_rom_disable )
	122	WRITE8_MEMBER(rt1715_state::rt1715_rom_disable)
119	123	{
120		logerror("%s: rt1715_set_bank %02x\n", space->machine().describe_context(), data);
	124	logerror("%s: rt1715_set_bank %02x\n", machine().describe_context(), data);
121	125
122	126	/* disable ROM, enable RAM */
123		memory_set_bankptr(space->machine(), "bank1", space->machine().device<ram_device>(RAM_TAG)->pointer());
	127	memory_set_bankptr(machine(), "bank1", machine().device<ram_device>(RAM_TAG)->pointer());
124	128	}
125	129
126	130	/***************************************************************************
r14844	r14845
191	195	AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE_LEGACY("a30", z80ctc_r, z80ctc_w)
192	196	AM_RANGE(0x0c, 0x0f) AM_DEVREADWRITE_LEGACY("a29", z80sio_ba_cd_r, z80sio_ba_cd_w)
193	197	AM_RANGE(0x18, 0x19) AM_DEVREADWRITE_LEGACY("a26", i8275_r, i8275_w)
194		AM_RANGE(0x20, 0x20) AM_WRITE_LEGACY(rt1715_floppy_enable)
195		AM_RANGE(0x28, 0x28) AM_WRITE_LEGACY(rt1715_rom_disable)
	198	AM_RANGE(0x20, 0x20) AM_WRITE(rt1715_floppy_enable)
	199	AM_RANGE(0x28, 0x28) AM_WRITE(rt1715_rom_disable)
196	200	ADDRESS_MAP_END
197	201
198	202	static ADDRESS_MAP_START( k7658_mem, AS_PROGRAM, 8, rt1715_state )
199		AM_RANGE(0x0000, 0xffff) AM_WRITE_LEGACY(k7658_data_w)
	203	AM_RANGE(0x0000, 0xffff) AM_WRITE(k7658_data_w)
200	204	AM_RANGE(0x0000, 0x07ff) AM_MIRROR(0xf800) AM_ROM
201	205	ADDRESS_MAP_END
202	206
203	207	static ADDRESS_MAP_START( k7658_io, AS_IO, 8, rt1715_state )
204		AM_RANGE(0x2000, 0x2000) AM_MIRROR(0x8000) AM_READ_LEGACY(k7658_led1_r)
205		AM_RANGE(0x4000, 0x4000) AM_MIRROR(0x8000) AM_READ_LEGACY(k7658_led2_r)
206		AM_RANGE(0x8000, 0x9fff) AM_READ_LEGACY(k7658_data_r)
	208	AM_RANGE(0x2000, 0x2000) AM_MIRROR(0x8000) AM_READ(k7658_led1_r)
	209	AM_RANGE(0x4000, 0x4000) AM_MIRROR(0x8000) AM_READ(k7658_led2_r)
	210	AM_RANGE(0x8000, 0x9fff) AM_READ(k7658_data_r)
207	211	ADDRESS_MAP_END
208	212
209	213

src/mess/drivers/ex800.c

r14844	r14845
139	139	: driver_device(mconfig, type, tag) { }
140	140
141	141	int m_irq_state;
	142	DECLARE_READ8_MEMBER(ex800_porta_r);
	143	DECLARE_READ8_MEMBER(ex800_portb_r);
	144	DECLARE_READ8_MEMBER(ex800_portc_r);
	145	DECLARE_WRITE8_MEMBER(ex800_porta_w);
	146	DECLARE_WRITE8_MEMBER(ex800_portb_w);
	147	DECLARE_WRITE8_MEMBER(ex800_portc_w);
	148	DECLARE_READ8_MEMBER(ex800_devsel_r);
	149	DECLARE_WRITE8_MEMBER(ex800_devsel_w);
	150	DECLARE_READ8_MEMBER(ex800_gate5a_r);
	151	DECLARE_WRITE8_MEMBER(ex800_gate5a_w);
	152	DECLARE_READ8_MEMBER(ex800_iosel_r);
	153	DECLARE_WRITE8_MEMBER(ex800_iosel_w);
	154	DECLARE_READ8_MEMBER(ex800_gate7a_r);
	155	DECLARE_WRITE8_MEMBER(ex800_gate7a_w);
142	156	};
143	157
144	158
r14844	r14845
199	213	}
200	214
201	215
202		static READ8_HANDLER(ex800_porta_r)
	216	READ8_MEMBER(ex800_state::ex800_porta_r)
203	217	{
204		logerror("PA R @%x\n", cpu_get_pc(&space->device()));
205		return space->machine().rand();
	218	logerror("PA R @%x\n", cpu_get_pc(&space.device()));
	219	return machine().rand();
206	220	}
207	221
208		static READ8_HANDLER(ex800_portb_r)
	222	READ8_MEMBER(ex800_state::ex800_portb_r)
209	223	{
210		logerror("PB R @%x\n", cpu_get_pc(&space->device()));
211		return space->machine().rand();
	224	logerror("PB R @%x\n", cpu_get_pc(&space.device()));
	225	return machine().rand();
212	226	}
213	227
214		static READ8_HANDLER(ex800_portc_r)
	228	READ8_MEMBER(ex800_state::ex800_portc_r)
215	229	{
216		logerror("PC R @%x\n", cpu_get_pc(&space->device()));
217		return space->machine().rand();
	230	logerror("PC R @%x\n", cpu_get_pc(&space.device()));
	231	return machine().rand();
218	232	}
219	233
220		static WRITE8_HANDLER(ex800_porta_w)
	234	WRITE8_MEMBER(ex800_state::ex800_porta_w)
221	235	{
222	236	if (PA6) logerror("BNK0 selected.\n");
223	237	if (PA7) logerror("BNK1 selected.\n");
224	238
225		logerror("PA W %x @%x\n", data, cpu_get_pc(&space->device()));
	239	logerror("PA W %x @%x\n", data, cpu_get_pc(&space.device()));
226	240	}
227	241
228		static WRITE8_HANDLER(ex800_portb_w)
	242	WRITE8_MEMBER(ex800_state::ex800_portb_w)
229	243	{
230	244	if (data & 3)
231		logerror("PB0/1 Line feed @%x\n", cpu_get_pc(&space->device()));
	245	logerror("PB0/1 Line feed @%x\n", cpu_get_pc(&space.device()));
232	246	if (!(data & 4))
233		logerror("PB2 Line feed @%x\n", cpu_get_pc(&space->device()));
	247	logerror("PB2 Line feed @%x\n", cpu_get_pc(&space.device()));
234	248	if (data & 8)
235		logerror("PB3 Online LED on @%x\n", cpu_get_pc(&space->device()));
	249	logerror("PB3 Online LED on @%x\n", cpu_get_pc(&space.device()));
236	250	else
237		logerror("PB3 Online LED off @%x\n", cpu_get_pc(&space->device()));
	251	logerror("PB3 Online LED off @%x\n", cpu_get_pc(&space.device()));
238	252	if (data & 16)
239		logerror("PB4 Serial @%x\n", cpu_get_pc(&space->device()));
	253	logerror("PB4 Serial @%x\n", cpu_get_pc(&space.device()));
240	254	if (data & 32)
241		logerror("PB4 Serial @%x\n", cpu_get_pc(&space->device()));
	255	logerror("PB4 Serial @%x\n", cpu_get_pc(&space.device()));
242	256	if (data & 64)
243		logerror("PB4 Serial @%x\n", cpu_get_pc(&space->device()));
	257	logerror("PB4 Serial @%x\n", cpu_get_pc(&space.device()));
244	258	if (data & 128)
245		logerror("PB3 Paper empty LED on @%x\n", cpu_get_pc(&space->device()));
	259	logerror("PB3 Paper empty LED on @%x\n", cpu_get_pc(&space.device()));
246	260	else
247		logerror("PB3 Paper empty LED off @%x\n", cpu_get_pc(&space->device()));
	261	logerror("PB3 Paper empty LED off @%x\n", cpu_get_pc(&space.device()));
248	262
249		//  logerror("PB W %x @%x\n", data, cpu_get_pc(&space->device()));
	263	//  logerror("PB W %x @%x\n", data, cpu_get_pc(&space.device()));
250	264	}
251	265
252		static WRITE8_HANDLER(ex800_portc_w)
	266	WRITE8_MEMBER(ex800_state::ex800_portc_w)
253	267	{
254		device_t *speaker = space->machine().device(BEEPER_TAG);
	268	device_t *speaker = machine().device(BEEPER_TAG);
255	269	if (data & 0x80)
256	270	beep_set_state(speaker, 0);
257	271	else
258	272	beep_set_state(speaker, 1);
259	273
260		logerror("PC W %x @%x\n", data, cpu_get_pc(&space->device()));
	274	logerror("PC W %x @%x\n", data, cpu_get_pc(&space.device()));
261	275	}
262	276
263	277
264	278	/* Memory mapped I/O access */
265	279
266		static READ8_HANDLER(ex800_devsel_r)
	280	READ8_MEMBER(ex800_state::ex800_devsel_r)
267	281	{
268		logerror("DEVSEL R @%x with offset %x\n", cpu_get_pc(&space->device()), offset);
269		return space->machine().rand();
	282	logerror("DEVSEL R @%x with offset %x\n", cpu_get_pc(&space.device()), offset);
	283	return machine().rand();
270	284	}
271	285
272		static WRITE8_HANDLER(ex800_devsel_w)
	286	WRITE8_MEMBER(ex800_state::ex800_devsel_w)
273	287	{
274		logerror("DEVSEL W %x @%x with offset %x\n", data, cpu_get_pc(&space->device()), offset);
	288	logerror("DEVSEL W %x @%x with offset %x\n", data, cpu_get_pc(&space.device()), offset);
275	289	}
276	290
277		static READ8_HANDLER(ex800_gate5a_r)
	291	READ8_MEMBER(ex800_state::ex800_gate5a_r)
278	292	{
279		logerror("GATE5A R @%x with offset %x\n", cpu_get_pc(&space->device()), offset);
280		return space->machine().rand();
	293	logerror("GATE5A R @%x with offset %x\n", cpu_get_pc(&space.device()), offset);
	294	return machine().rand();
281	295	}
282	296
283		static WRITE8_HANDLER(ex800_gate5a_w)
	297	WRITE8_MEMBER(ex800_state::ex800_gate5a_w)
284	298	{
285		logerror("GATE5A W %x @%x with offset %x\n", data, cpu_get_pc(&space->device()), offset);
	299	logerror("GATE5A W %x @%x with offset %x\n", data, cpu_get_pc(&space.device()), offset);
286	300	}
287	301
288		static READ8_HANDLER(ex800_iosel_r)
	302	READ8_MEMBER(ex800_state::ex800_iosel_r)
289	303	{
290		logerror("IOSEL R @%x with offset %x\n", cpu_get_pc(&space->device()), offset);
291		return space->machine().rand();
	304	logerror("IOSEL R @%x with offset %x\n", cpu_get_pc(&space.device()), offset);
	305	return machine().rand();
292	306	}
293	307
294		static WRITE8_HANDLER(ex800_iosel_w)
	308	WRITE8_MEMBER(ex800_state::ex800_iosel_w)
295	309	{
296		logerror("IOSEL W %x @%x with offset %x\n", data, cpu_get_pc(&space->device()), offset);
	310	logerror("IOSEL W %x @%x with offset %x\n", data, cpu_get_pc(&space.device()), offset);
297	311	}
298	312
299		static READ8_HANDLER(ex800_gate7a_r)
	313	READ8_MEMBER(ex800_state::ex800_gate7a_r)
300	314	{
301		logerror("GATE7A R @%x with offset %x\n", cpu_get_pc(&space->device()), offset);
302		return space->machine().rand();
	315	logerror("GATE7A R @%x with offset %x\n", cpu_get_pc(&space.device()), offset);
	316	return machine().rand();
303	317	}
304	318
305		static WRITE8_HANDLER(ex800_gate7a_w)
	319	WRITE8_MEMBER(ex800_state::ex800_gate7a_w)
306	320	{
307		logerror("GATE7A W %x @%x with offset %x\n", data, cpu_get_pc(&space->device()), offset);
	321	logerror("GATE7A W %x @%x with offset %x\n", data, cpu_get_pc(&space.device()), offset);
308	322	}
309	323
310	324
r14844	r14845
316	330	static ADDRESS_MAP_START( ex800_mem, AS_PROGRAM, 8, ex800_state )
317	331	AM_RANGE(0x0000, 0x7fff) AM_ROM AM_REGION("maincpu", 0)
318	332	AM_RANGE(0x8000, 0xbfff) AM_RAM /* external RAM */
319		AM_RANGE(0xc000, 0xc7ff) AM_MIRROR(0x1800) AM_READWRITE_LEGACY(ex800_devsel_r, ex800_devsel_w)
320		AM_RANGE(0xe000, 0xe7ff) AM_READWRITE_LEGACY(ex800_gate5a_r, ex800_gate5a_w)
321		AM_RANGE(0xe800, 0xefff) AM_READWRITE_LEGACY(ex800_iosel_r, ex800_iosel_w)
322		AM_RANGE(0xf000, 0xf001) AM_MIRROR(0x07fc) AM_READ_LEGACY(ex800_gate7a_r)
323		AM_RANGE(0xf002, 0xf003) AM_MIRROR(0x07fc) AM_WRITE_LEGACY(ex800_gate7a_w)
	333	AM_RANGE(0xc000, 0xc7ff) AM_MIRROR(0x1800) AM_READWRITE(ex800_devsel_r, ex800_devsel_w)
	334	AM_RANGE(0xe000, 0xe7ff) AM_READWRITE(ex800_gate5a_r, ex800_gate5a_w)
	335	AM_RANGE(0xe800, 0xefff) AM_READWRITE(ex800_iosel_r, ex800_iosel_w)
	336	AM_RANGE(0xf000, 0xf001) AM_MIRROR(0x07fc) AM_READ(ex800_gate7a_r)
	337	AM_RANGE(0xf002, 0xf003) AM_MIRROR(0x07fc) AM_WRITE(ex800_gate7a_w)
324	338	AM_RANGE(0xf800, 0xfeff) AM_NOP /* not connected */
325	339	AM_RANGE(0xff00, 0xffff) AM_RAM /* internal CPU RAM */
326	340	ADDRESS_MAP_END
327	341
328	342
329	343	static ADDRESS_MAP_START( ex800_io, AS_IO, 8, ex800_state )
330		AM_RANGE(UPD7810_PORTA, UPD7810_PORTA) AM_READ_LEGACY(ex800_porta_r) AM_WRITE_LEGACY(ex800_porta_w)
331		AM_RANGE(UPD7810_PORTB, UPD7810_PORTB) AM_READ_LEGACY(ex800_portb_r) AM_WRITE_LEGACY(ex800_portb_w)
332		AM_RANGE(UPD7810_PORTC, UPD7810_PORTC) AM_READ_LEGACY(ex800_portc_r) AM_WRITE_LEGACY(ex800_portc_w)
	344	AM_RANGE(UPD7810_PORTA, UPD7810_PORTA) AM_READ(ex800_porta_r) AM_WRITE(ex800_porta_w)
	345	AM_RANGE(UPD7810_PORTB, UPD7810_PORTB) AM_READ(ex800_portb_r) AM_WRITE(ex800_portb_w)
	346	AM_RANGE(UPD7810_PORTC, UPD7810_PORTC) AM_READ(ex800_portc_r) AM_WRITE(ex800_portc_w)
333	347	ADDRESS_MAP_END
334	348
335	349

src/mess/drivers/tvc.c

r14844	r14845
22	22	UINT8 m_keyline;
23	23	UINT8 m_flipflop;
24	24	UINT8 m_col[4];
	25	DECLARE_WRITE8_MEMBER(tvc_bank_w);
	26	DECLARE_WRITE8_MEMBER(tvc_video_mode_w);
	27	DECLARE_WRITE8_MEMBER(tvc_palette_w);
	28	DECLARE_WRITE8_MEMBER(tvc_keyboard_w);
	29	DECLARE_READ8_MEMBER(tvc_keyboard_r);
	30	DECLARE_READ8_MEMBER(tvc_flipflop_r);
	31	DECLARE_WRITE8_MEMBER(tvc_flipflop_w);
	32	DECLARE_READ8_MEMBER(tvc_port59_r);
	33	DECLARE_WRITE8_MEMBER(tvc_port0_w);
25	34	};
26	35
27	36
r14844	r14845
78	87	}
79	88	}
80	89
81		static WRITE8_HANDLER( tvc_bank_w )
	90	WRITE8_MEMBER(tvc_state::tvc_bank_w)
82	91	{
83		tvc_set_mem_page(space->machine(), data);
	92	tvc_set_mem_page(machine(), data);
84	93	}
85	94
86		static WRITE8_HANDLER( tvc_video_mode_w )
	95	WRITE8_MEMBER(tvc_state::tvc_video_mode_w)
87	96	{
88		tvc_state *state = space->machine().driver_data<tvc_state>();
89		state->m_video_mode = data & 0x03;
	97	m_video_mode = data & 0x03;
90	98	}
91	99
92	100
93		static WRITE8_HANDLER( tvc_palette_w )
	101	WRITE8_MEMBER(tvc_state::tvc_palette_w)
94	102	{
95		tvc_state *state = space->machine().driver_data<tvc_state>();
96	103	//  0 I 0 R | 0 G 0 B
97	104	//  0 0 0 0 | I R G B
98	105	int i = ((data&0x40)>>3) | ((data&0x10)>>2) | ((data&0x04)>>1) | (data&0x01);
99	106
100		state->m_col[offset] = i;
	107	m_col[offset] = i;
101	108	}
102	109
103		static WRITE8_HANDLER( tvc_keyboard_w )
	110	WRITE8_MEMBER(tvc_state::tvc_keyboard_w)
104	111	{
105		tvc_state *state = space->machine().driver_data<tvc_state>();
106		state->m_keyline = data;
	112	m_keyline = data;
107	113	}
108	114
109		static READ8_HANDLER( tvc_keyboard_r )
	115	READ8_MEMBER(tvc_state::tvc_keyboard_r)
110	116	{
111		tvc_state *state = space->machine().driver_data<tvc_state>();
112	117	static const char *const keynames[] = {
113	118	"LINE0", "LINE1", "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7",
114	119	"LINE8", "LINE9", "LINEA", "LINEB", "LINEC", "LINED", "LINEE", "LINEF"
115	120	};
116		return input_port_read(space->machine(), keynames[state->m_keyline & 0x0f]);
	121	return input_port_read(machine(), keynames[m_keyline & 0x0f]);
117	122	}
118	123
119		static READ8_HANDLER( tvc_flipflop_r )
	124	READ8_MEMBER(tvc_state::tvc_flipflop_r)
120	125	{
121		tvc_state *state = space->machine().driver_data<tvc_state>();
122		return state->m_flipflop;
	126	return m_flipflop;
123	127	}
124	128
125		static WRITE8_HANDLER( tvc_flipflop_w )
	129	WRITE8_MEMBER(tvc_state::tvc_flipflop_w)
126	130	{
127		tvc_state *state = space->machine().driver_data<tvc_state>();
128		state->m_flipflop |= 0x10;
	131	m_flipflop |= 0x10;
129	132	}
130		static READ8_HANDLER( tvc_port59_r )
	133	READ8_MEMBER(tvc_state::tvc_port59_r)
131	134	{
132	135	return 0xff;
133	136	}
134	137
135		static WRITE8_HANDLER( tvc_port0_w )
	138	WRITE8_MEMBER(tvc_state::tvc_port0_w)
136	139	{
137	140	}
138	141	static ADDRESS_MAP_START(tvc_mem, AS_PROGRAM, 8, tvc_state )
r14844	r14845
145	148	static ADDRESS_MAP_START( tvc_io , AS_IO, 8, tvc_state )
146	149	ADDRESS_MAP_UNMAP_HIGH
147	150	ADDRESS_MAP_GLOBAL_MASK(0xff)
148		AM_RANGE(0x00, 0x00) AM_WRITE_LEGACY(tvc_port0_w)
149		AM_RANGE(0x02, 0x02) AM_WRITE_LEGACY(tvc_bank_w)
150		AM_RANGE(0x03, 0x03) AM_WRITE_LEGACY(tvc_keyboard_w)
151		AM_RANGE(0x06, 0x06) AM_WRITE_LEGACY(tvc_video_mode_w)
152		AM_RANGE(0x07, 0x07) AM_WRITE_LEGACY(tvc_flipflop_w)
153		AM_RANGE(0x58, 0x58) AM_READ_LEGACY(tvc_keyboard_r)
154		AM_RANGE(0x59, 0x59) AM_READ_LEGACY(tvc_flipflop_r)
155		AM_RANGE(0x5a, 0x5a) AM_READ_LEGACY(tvc_port59_r)
156		AM_RANGE(0x60, 0x64) AM_WRITE_LEGACY(tvc_palette_w)
	151	AM_RANGE(0x00, 0x00) AM_WRITE(tvc_port0_w)
	152	AM_RANGE(0x02, 0x02) AM_WRITE(tvc_bank_w)
	153	AM_RANGE(0x03, 0x03) AM_WRITE(tvc_keyboard_w)
	154	AM_RANGE(0x06, 0x06) AM_WRITE(tvc_video_mode_w)
	155	AM_RANGE(0x07, 0x07) AM_WRITE(tvc_flipflop_w)
	156	AM_RANGE(0x58, 0x58) AM_READ(tvc_keyboard_r)
	157	AM_RANGE(0x59, 0x59) AM_READ(tvc_flipflop_r)
	158	AM_RANGE(0x5a, 0x5a) AM_READ(tvc_port59_r)
	159	AM_RANGE(0x60, 0x64) AM_WRITE(tvc_palette_w)
157	160	AM_RANGE(0x70, 0x70) AM_DEVWRITE("crtc", mc6845_device, address_w)
158	161	AM_RANGE(0x71, 0x71) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
159	162	ADDRESS_MAP_END

src/mess/drivers/mz2500.c

r14844	r14845
111	111	UINT8 m_prev_col_val;
112	112	UINT8 m_pio_latchb;
113	113	UINT8 m_ym_porta;
	114	DECLARE_READ8_MEMBER(bank0_r);
	115	DECLARE_READ8_MEMBER(bank1_r);
	116	DECLARE_READ8_MEMBER(bank2_r);
	117	DECLARE_READ8_MEMBER(bank3_r);
	118	DECLARE_READ8_MEMBER(bank4_r);
	119	DECLARE_READ8_MEMBER(bank5_r);
	120	DECLARE_READ8_MEMBER(bank6_r);
	121	DECLARE_READ8_MEMBER(bank7_r);
	122	DECLARE_WRITE8_MEMBER(bank0_w);
	123	DECLARE_WRITE8_MEMBER(bank1_w);
	124	DECLARE_WRITE8_MEMBER(bank2_w);
	125	DECLARE_WRITE8_MEMBER(bank3_w);
	126	DECLARE_WRITE8_MEMBER(bank4_w);
	127	DECLARE_WRITE8_MEMBER(bank5_w);
	128	DECLARE_WRITE8_MEMBER(bank6_w);
	129	DECLARE_WRITE8_MEMBER(bank7_w);
	130	DECLARE_READ8_MEMBER(mz2500_bank_addr_r);
	131	DECLARE_WRITE8_MEMBER(mz2500_bank_addr_w);
	132	DECLARE_READ8_MEMBER(mz2500_bank_data_r);
	133	DECLARE_WRITE8_MEMBER(mz2500_bank_data_w);
	134	DECLARE_WRITE8_MEMBER(mz2500_kanji_bank_w);
	135	DECLARE_WRITE8_MEMBER(mz2500_dictionary_bank_w);
	136	DECLARE_READ8_MEMBER(mz2500_crtc_hvblank_r);
	137	DECLARE_WRITE8_MEMBER(mz2500_tv_crtc_w);
	138	DECLARE_WRITE8_MEMBER(mz2500_irq_sel_w);
	139	DECLARE_WRITE8_MEMBER(mz2500_irq_data_w);
	140	DECLARE_WRITE8_MEMBER(mz2500_fdc_w);
	141	DECLARE_READ8_MEMBER(mz2500_rom_r);
	142	DECLARE_WRITE8_MEMBER(mz2500_rom_w);
	143	DECLARE_WRITE8_MEMBER(palette4096_io_w);
	144	DECLARE_READ8_MEMBER(mz2500_bplane_latch_r);
	145	DECLARE_READ8_MEMBER(mz2500_rplane_latch_r);
	146	DECLARE_READ8_MEMBER(mz2500_gplane_latch_r);
	147	DECLARE_READ8_MEMBER(mz2500_iplane_latch_r);
	148	DECLARE_WRITE8_MEMBER(mz2500_cg_addr_w);
	149	DECLARE_WRITE8_MEMBER(mz2500_cg_data_w);
	150	DECLARE_WRITE8_MEMBER(timer_w);
	151	DECLARE_READ8_MEMBER(mz2500_joystick_r);
	152	DECLARE_WRITE8_MEMBER(mz2500_joystick_w);
	153	DECLARE_READ8_MEMBER(mz2500_kanji_r);
	154	DECLARE_WRITE8_MEMBER(mz2500_kanji_w);
	155	DECLARE_READ8_MEMBER(rp5c15_8_r);
	156	DECLARE_WRITE8_MEMBER(rp5c15_8_w);
	157	DECLARE_READ8_MEMBER(mz2500_emm_data_r);
	158	DECLARE_WRITE8_MEMBER(mz2500_emm_addr_w);
	159	DECLARE_WRITE8_MEMBER(mz2500_emm_data_w);
	160	UINT8 mz2500_cg_latch_compare();
	161	UINT8 mz2500_ram_read(UINT16 offset, UINT8 bank_num);
	162	void mz2500_ram_write(UINT16 offset, UINT8 data, UINT8 bank_num);
114	163	};
115	164
116	165
r14844	r14845
664	713	}
665	714	}
666	715
667		static UINT8 mz2500_cg_latch_compare(mz2500_state *state)
	716	UINT8 mz2500_state::mz2500_cg_latch_compare()
668	717	{
669		UINT8 compare_val = state->m_cg_reg[0x07] & 0xf;
	718	UINT8 compare_val = m_cg_reg[0x07] & 0xf;
670	719	UINT8 pix_val;
671	720	UINT8 res;
672	721	UINT16 i;
r14844	r14845
674	723
675	724	for(i=1;i<0x100;i<<=1)
676	725	{
677		pix_val = ((state->m_cg_latch[0] & i) ? 1 : 0) | ((state->m_cg_latch[1] & i) ? 2 : 0) | ((state->m_cg_latch[2] & i) ? 4 : 0) | ((state->m_cg_latch[3] & i) ? 8 : 0);
	726	pix_val = ((m_cg_latch[0] & i) ? 1 : 0) | ((m_cg_latch[1] & i) ? 2 : 0) | ((m_cg_latch[2] & i) ? 4 : 0) | ((m_cg_latch[3] & i) ? 8 : 0);
678	727	if(pix_val == compare_val)
679	728	res|=i;
680	729	}
r14844	r14845
682	731	return res;
683	732	}
684	733
685		static UINT8 mz2500_ram_read(running_machine &machine, UINT16 offset, UINT8 bank_num)
	734	UINT8 mz2500_state::mz2500_ram_read(UINT16 offset, UINT8 bank_num)
686	735	{
687		mz2500_state *state = machine.driver_data<mz2500_state>();
688		UINT8 *ram = machine.region("maincpu")->base();
689		UINT8 cur_bank = state->m_bank_val[bank_num];
	736	UINT8 *ram = machine().region("maincpu")->base();
	737	UINT8 cur_bank = m_bank_val[bank_num];
690	738
691	739	switch(cur_bank)
692	740	{
r14844	r14845
696	744	case 0x33:
697	745	{
698	746	// READ MODIFY WRITE
699		if(state->m_cg_reg[0x0e] == 0x3)
	747	if(m_cg_reg[0x0e] == 0x3)
700	748	{
701	749	// ...
702	750	}
703	751	else
704	752	{
705	753	int plane;
706		state->m_cg_latch[0] = ram[offset+((cur_bank & 3)*0x2000)+0x40000]; //B
707		state->m_cg_latch[1] = ram[offset+((cur_bank & 3)*0x2000)+0x44000]; //R
708		state->m_cg_latch[2] = ram[offset+((cur_bank & 3)*0x2000)+0x48000]; //G
709		state->m_cg_latch[3] = ram[offset+((cur_bank & 3)*0x2000)+0x4c000]; //I
710		plane = state->m_cg_reg[0x07] & 3;
	754	m_cg_latch[0] = ram[offset+((cur_bank & 3)*0x2000)+0x40000]; //B
	755	m_cg_latch[1] = ram[offset+((cur_bank & 3)*0x2000)+0x44000]; //R
	756	m_cg_latch[2] = ram[offset+((cur_bank & 3)*0x2000)+0x48000]; //G
	757	m_cg_latch[3] = ram[offset+((cur_bank & 3)*0x2000)+0x4c000]; //I
	758	plane = m_cg_reg[0x07] & 3;
711	759
712		if(state->m_cg_reg[0x07] & 0x10)
713		return mz2500_cg_latch_compare(state);
	760	if(m_cg_reg[0x07] & 0x10)
	761	return mz2500_cg_latch_compare();
714	762	else
715		return state->m_cg_latch[plane];
	763	return m_cg_latch[plane];
716	764	}
717	765	}
718	766	break;
719	767	case 0x39:
720	768	{
721		if(state->m_kanji_bank & 0x80) //kanji ROM
	769	if(m_kanji_bank & 0x80) //kanji ROM
722	770	{
723		UINT8 *knj_rom = machine.region("kanji")->base();
	771	UINT8 *knj_rom = machine().region("kanji")->base();
724	772
725		return knj_rom[(offset & 0x7ff)+((state->m_kanji_bank & 0x7f)*0x800)];
	773	return knj_rom[(offset & 0x7ff)+((m_kanji_bank & 0x7f)*0x800)];
726	774	}
727	775	else //PCG RAM
728	776	{
729		UINT8 *pcg_ram = machine.region("pcg")->base();
	777	UINT8 *pcg_ram = machine().region("pcg")->base();
730	778
731	779	return pcg_ram[offset];
732	780	}
r14844	r14845
734	782	break;
735	783	case 0x3a:
736	784	{
737		UINT8 *dic_rom = machine.region("dictionary")->base();
	785	UINT8 *dic_rom = machine().region("dictionary")->base();
738	786
739		return dic_rom[(offset & 0x1fff) + ((state->m_dic_bank & 0x1f)*0x2000)];
	787	return dic_rom[(offset & 0x1fff) + ((m_dic_bank & 0x1f)*0x2000)];
740	788	}
741	789	break;
742	790	case 0x3c:
r14844	r14845
744	792	case 0x3e:
745	793	case 0x3f:
746	794	{
747		UINT8 *phone_rom = machine.region("phone")->base();
	795	UINT8 *phone_rom = machine().region("phone")->base();
748	796
749	797	return phone_rom[offset+(cur_bank & 3)*0x2000];
750	798	}
r14844	r14845
755	803	return 0xff;
756	804	}
757	805
758		static void mz2500_ram_write(running_machine &machine, UINT16 offset, UINT8 data, UINT8 bank_num)
	806	void mz2500_state::mz2500_ram_write(UINT16 offset, UINT8 data, UINT8 bank_num)
759	807	{
760		mz2500_state *state = machine.driver_data<mz2500_state>();
761		UINT8 *ram = machine.region("maincpu")->base();
762		UINT8 cur_bank = state->m_bank_val[bank_num];
	808	UINT8 *ram = machine().region("maincpu")->base();
	809	UINT8 cur_bank = m_bank_val[bank_num];
763	810
764	811	//  if(cur_bank >= 0x30 && cur_bank <= 0x33)
765		//      printf("CG REG = %02x %02x %02x %02x | offset = %04x | data = %02x\n",state->m_cg_reg[0],state->m_cg_reg[1],state->m_cg_reg[2],state->m_cg_reg[3],offset,data);
	812	//      printf("CG REG = %02x %02x %02x %02x | offset = %04x | data = %02x\n",m_cg_reg[0],m_cg_reg[1],m_cg_reg[2],m_cg_reg[3],offset,data);
766	813
767	814	switch(cur_bank)
768	815	{
r14844	r14845
772	819	case 0x33:
773	820	{
774	821	// READ MODIFY WRITE
775		if(state->m_cg_reg[0x0e] == 0x3)
	822	if(m_cg_reg[0x0e] == 0x3)
776	823	{
777	824	// ...
778	825	}
779	826	else
780	827	{
781		if((state->m_cg_reg[0x05] & 0xc0) == 0x00) //replace
	828	if((m_cg_reg[0x05] & 0xc0) == 0x00) //replace
782	829	{
783		if(state->m_cg_reg[5] & 1) //B
	830	if(m_cg_reg[5] & 1) //B
784	831	{
785		ram[offset+((cur_bank & 3)*0x2000)+0x40000] &= ~state->m_cg_reg[6];
786		ram[offset+((cur_bank & 3)*0x2000)+0x40000] |= (state->m_cg_reg[4] & 1) ? (data & state->m_cg_reg[0] & state->m_cg_reg[6]) : 0;
	832	ram[offset+((cur_bank & 3)*0x2000)+0x40000] &= ~m_cg_reg[6];
	833	ram[offset+((cur_bank & 3)*0x2000)+0x40000] |= (m_cg_reg[4] & 1) ? (data & m_cg_reg[0] & m_cg_reg[6]) : 0;
787	834	}
788		if(state->m_cg_reg[5] & 2) //R
	835	if(m_cg_reg[5] & 2) //R
789	836	{
790		ram[offset+((cur_bank & 3)*0x2000)+0x44000] &= ~state->m_cg_reg[6];
791		ram[offset+((cur_bank & 3)*0x2000)+0x44000] |= (state->m_cg_reg[4] & 2) ? (data & state->m_cg_reg[1] & state->m_cg_reg[6]) : 0;
	837	ram[offset+((cur_bank & 3)*0x2000)+0x44000] &= ~m_cg_reg[6];
	838	ram[offset+((cur_bank & 3)*0x2000)+0x44000] |= (m_cg_reg[4] & 2) ? (data & m_cg_reg[1] & m_cg_reg[6]) : 0;
792	839	}
793		if(state->m_cg_reg[5] & 4) //G
	840	if(m_cg_reg[5] & 4) //G
794	841	{
795		ram[offset+((cur_bank & 3)*0x2000)+0x48000] &= ~state->m_cg_reg[6];
796		ram[offset+((cur_bank & 3)*0x2000)+0x48000] |= (state->m_cg_reg[4] & 4) ? (data & state->m_cg_reg[2] & state->m_cg_reg[6]) : 0;
	842	ram[offset+((cur_bank & 3)*0x2000)+0x48000] &= ~m_cg_reg[6];
	843	ram[offset+((cur_bank & 3)*0x2000)+0x48000] |= (m_cg_reg[4] & 4) ? (data & m_cg_reg[2] & m_cg_reg[6]) : 0;
797	844	}
798		if(state->m_cg_reg[5] & 8) //I
	845	if(m_cg_reg[5] & 8) //I
799	846	{
800		ram[offset+((cur_bank & 3)*0x2000)+0x4c000] &= ~state->m_cg_reg[6];
801		ram[offset+((cur_bank & 3)*0x2000)+0x4c000] |= (state->m_cg_reg[4] & 8) ? (data & state->m_cg_reg[3] & state->m_cg_reg[6]) : 0;
	847	ram[offset+((cur_bank & 3)*0x2000)+0x4c000] &= ~m_cg_reg[6];
	848	ram[offset+((cur_bank & 3)*0x2000)+0x4c000] |= (m_cg_reg[4] & 8) ? (data & m_cg_reg[3] & m_cg_reg[6]) : 0;
802	849	}
803	850	}
804		else if((state->m_cg_reg[0x05] & 0xc0) == 0x40) //pset
	851	else if((m_cg_reg[0x05] & 0xc0) == 0x40) //pset
805	852	{
806		if(state->m_cg_reg[5] & 1) //B
	853	if(m_cg_reg[5] & 1) //B
807	854	{
808	855	ram[offset+((cur_bank & 3)*0x2000)+0x40000] &= ~data;
809		ram[offset+((cur_bank & 3)*0x2000)+0x40000] |= (state->m_cg_reg[4] & 1) ? (data & state->m_cg_reg[0]) : 0;
	856	ram[offset+((cur_bank & 3)*0x2000)+0x40000] |= (m_cg_reg[4] & 1) ? (data & m_cg_reg[0]) : 0;
810	857	}
811		if(state->m_cg_reg[5] & 2) //R
	858	if(m_cg_reg[5] & 2) //R
812	859	{
813	860	ram[offset+((cur_bank & 3)*0x2000)+0x44000] &= ~data;
814		ram[offset+((cur_bank & 3)*0x2000)+0x44000] |= (state->m_cg_reg[4] & 2) ? (data & state->m_cg_reg[1]) : 0;
	861	ram[offset+((cur_bank & 3)*0x2000)+0x44000] |= (m_cg_reg[4] & 2) ? (data & m_cg_reg[1]) : 0;
815	862	}
816		if(state->m_cg_reg[5] & 4) //G
	863	if(m_cg_reg[5] & 4) //G
817	864	{
818	865	ram[offset+((cur_bank & 3)*0x2000)+0x48000] &= ~data;
819		ram[offset+((cur_bank & 3)*0x2000)+0x48000] |= (state->m_cg_reg[4] & 4) ? (data & state->m_cg_reg[2]) : 0;
	866	ram[offset+((cur_bank & 3)*0x2000)+0x48000] |= (m_cg_reg[4] & 4) ? (data & m_cg_reg[2]) : 0;
820	867	}
821		if(state->m_cg_reg[5] & 8) //I
	868	if(m_cg_reg[5] & 8) //I
822	869	{
823	870	ram[offset+((cur_bank & 3)*0x2000)+0x4c000] &= ~data;
824		ram[offset+((cur_bank & 3)*0x2000)+0x4c000] |= (state->m_cg_reg[4] & 8) ? (data & state->m_cg_reg[3]) : 0;
	871	ram[offset+((cur_bank & 3)*0x2000)+0x4c000] |= (m_cg_reg[4] & 8) ? (data & m_cg_reg[3]) : 0;
825	872	}
826	873	}
827	874	}
r14844	r14845
845	892	case 0x39:
846	893	{
847	894	ram[offset+cur_bank*0x2000] = data;
848		if(state->m_kanji_bank & 0x80) //kanji ROM
	895	if(m_kanji_bank & 0x80) //kanji ROM
849	896	{
850	897	//NOP
851	898	}
852	899	else //PCG RAM
853	900	{
854		UINT8 *pcg_ram = machine.region("pcg")->base();
	901	UINT8 *pcg_ram = machine().region("pcg")->base();
855	902	pcg_ram[offset] = data;
856	903	if((offset & 0x1800) == 0x0000)
857		gfx_element_mark_dirty(machine.gfx[3], (offset) >> 3);
	904	gfx_element_mark_dirty(machine().gfx[3], (offset) >> 3);
858	905	else
859		gfx_element_mark_dirty(machine.gfx[4], (offset & 0x7ff) >> 3);
	906	gfx_element_mark_dirty(machine().gfx[4], (offset & 0x7ff) >> 3);
860	907	}
861	908	break;
862	909	}
r14844	r14845
877	924	}
878	925	}
879	926
880		static READ8_HANDLER( bank0_r ) { return mz2500_ram_read(space->machine(), offset, 0); }
881		static READ8_HANDLER( bank1_r ) { return mz2500_ram_read(space->machine(), offset, 1); }
882		static READ8_HANDLER( bank2_r ) { return mz2500_ram_read(space->machine(), offset, 2); }
883		static READ8_HANDLER( bank3_r ) { return mz2500_ram_read(space->machine(), offset, 3); }
884		static READ8_HANDLER( bank4_r ) { return mz2500_ram_read(space->machine(), offset, 4); }
885		static READ8_HANDLER( bank5_r ) { return mz2500_ram_read(space->machine(), offset, 5); }
886		static READ8_HANDLER( bank6_r ) { return mz2500_ram_read(space->machine(), offset, 6); }
887		static READ8_HANDLER( bank7_r ) { return mz2500_ram_read(space->machine(), offset, 7); }
888		static WRITE8_HANDLER( bank0_w ) { mz2500_ram_write(space->machine(), offset, data, 0); }
889		static WRITE8_HANDLER( bank1_w ) { mz2500_ram_write(space->machine(), offset, data, 1); }
890		static WRITE8_HANDLER( bank2_w ) { mz2500_ram_write(space->machine(), offset, data, 2); }
891		static WRITE8_HANDLER( bank3_w ) { mz2500_ram_write(space->machine(), offset, data, 3); }
892		static WRITE8_HANDLER( bank4_w ) { mz2500_ram_write(space->machine(), offset, data, 4); }
893		static WRITE8_HANDLER( bank5_w ) { mz2500_ram_write(space->machine(), offset, data, 5); }
894		static WRITE8_HANDLER( bank6_w ) { mz2500_ram_write(space->machine(), offset, data, 6); }
895		static WRITE8_HANDLER( bank7_w ) { mz2500_ram_write(space->machine(), offset, data, 7); }
	927	READ8_MEMBER(mz2500_state::bank0_r){ return mz2500_ram_read(offset, 0); }
	928	READ8_MEMBER(mz2500_state::bank1_r){ return mz2500_ram_read(offset, 1); }
	929	READ8_MEMBER(mz2500_state::bank2_r){ return mz2500_ram_read(offset, 2); }
	930	READ8_MEMBER(mz2500_state::bank3_r){ return mz2500_ram_read(offset, 3); }
	931	READ8_MEMBER(mz2500_state::bank4_r){ return mz2500_ram_read(offset, 4); }
	932	READ8_MEMBER(mz2500_state::bank5_r){ return mz2500_ram_read(offset, 5); }
	933	READ8_MEMBER(mz2500_state::bank6_r){ return mz2500_ram_read(offset, 6); }
	934	READ8_MEMBER(mz2500_state::bank7_r){ return mz2500_ram_read(offset, 7); }
	935	WRITE8_MEMBER(mz2500_state::bank0_w){ mz2500_ram_write(offset, data, 0); }
	936	WRITE8_MEMBER(mz2500_state::bank1_w){ mz2500_ram_write(offset, data, 1); }
	937	WRITE8_MEMBER(mz2500_state::bank2_w){ mz2500_ram_write(offset, data, 2); }
	938	WRITE8_MEMBER(mz2500_state::bank3_w){ mz2500_ram_write(offset, data, 3); }
	939	WRITE8_MEMBER(mz2500_state::bank4_w){ mz2500_ram_write(offset, data, 4); }
	940	WRITE8_MEMBER(mz2500_state::bank5_w){ mz2500_ram_write(offset, data, 5); }
	941	WRITE8_MEMBER(mz2500_state::bank6_w){ mz2500_ram_write(offset, data, 6); }
	942	WRITE8_MEMBER(mz2500_state::bank7_w){ mz2500_ram_write(offset, data, 7); }
896	943
897	944
898		static READ8_HANDLER( mz2500_bank_addr_r )
	945	READ8_MEMBER(mz2500_state::mz2500_bank_addr_r)
899	946	{
900		mz2500_state *state = space->machine().driver_data<mz2500_state>();
901		return state->m_bank_addr;
	947	return m_bank_addr;
902	948	}
903	949
904		static WRITE8_HANDLER( mz2500_bank_addr_w )
	950	WRITE8_MEMBER(mz2500_state::mz2500_bank_addr_w)
905	951	{
906		mz2500_state *state = space->machine().driver_data<mz2500_state>();
907	952	//  printf("%02x\n",data);
908		state->m_bank_addr = data & 7;
	953	m_bank_addr = data & 7;
909	954	}
910	955
911		static READ8_HANDLER( mz2500_bank_data_r )
	956	READ8_MEMBER(mz2500_state::mz2500_bank_data_r)
912	957	{
913		mz2500_state *state = space->machine().driver_data<mz2500_state>();
914	958	UINT8 res;
915	959
916		res = state->m_bank_val[state->m_bank_addr];
	960	res = m_bank_val[m_bank_addr];
917	961
918		state->m_bank_addr++;
919		state->m_bank_addr&=7;
	962	m_bank_addr++;
	963	m_bank_addr&=7;
920	964
921	965	return res;
922	966	}
923	967
924		static WRITE8_HANDLER( mz2500_bank_data_w )
	968	WRITE8_MEMBER(mz2500_state::mz2500_bank_data_w)
925	969	{
926		mz2500_state *state = space->machine().driver_data<mz2500_state>();
927		//  UINT8 *ROM = space->machine().region("maincpu")->base();
	970	//  UINT8 *ROM = machine().region("maincpu")->base();
928	971	//  static const char *const bank_name[] = { "bank0", "bank1", "bank2", "bank3", "bank4", "bank5", "bank6", "bank7" };
929	972
930		state->m_bank_val[state->m_bank_addr] = data & 0x3f;
	973	m_bank_val[m_bank_addr] = data & 0x3f;
931	974
932	975	//  if((data*2) >= 0x70)
933		//  printf("%s %02x\n",bank_name[state->m_bank_addr],state->m_bank_val[state->m_bank_addr]*2);
	976	//  printf("%s %02x\n",bank_name[m_bank_addr],m_bank_val[m_bank_addr]*2);
934	977
935		//  memory_set_bankptr(space->machine(), bank_name[state->m_bank_addr], &ROM[state->m_bank_val[state->m_bank_addr]*0x2000]);
	978	//  memory_set_bankptr(machine(), bank_name[m_bank_addr], &ROM[m_bank_val[m_bank_addr]*0x2000]);
936	979
937		state->m_bank_addr++;
938		state->m_bank_addr&=7;
	980	m_bank_addr++;
	981	m_bank_addr&=7;
939	982	}
940	983
941		static WRITE8_HANDLER( mz2500_kanji_bank_w )
	984	WRITE8_MEMBER(mz2500_state::mz2500_kanji_bank_w)
942	985	{
943		mz2500_state *state = space->machine().driver_data<mz2500_state>();
944		state->m_kanji_bank = data;
	986	m_kanji_bank = data;
945	987	}
946	988
947		static WRITE8_HANDLER( mz2500_dictionary_bank_w )
	989	WRITE8_MEMBER(mz2500_state::mz2500_dictionary_bank_w)
948	990	{
949		mz2500_state *state = space->machine().driver_data<mz2500_state>();
950		state->m_dic_bank = data;
	991	m_dic_bank = data;
951	992	}
952	993
953	994	/* 0xf4 - 0xf7 all returns vblank / hblank states */
954		static READ8_HANDLER( mz2500_crtc_hvblank_r )
	995	READ8_MEMBER(mz2500_state::mz2500_crtc_hvblank_r)
955	996	{
956	997	UINT8 vblank_bit, hblank_bit;
957	998
958		vblank_bit = space->machine().primary_screen->vblank() ? 0 : 1;
959		hblank_bit = space->machine().primary_screen->hblank() ? 0 : 2;
	999	vblank_bit = machine().primary_screen->vblank() ? 0 : 1;
	1000	hblank_bit = machine().primary_screen->hblank() ? 0 : 2;
960	1001
961	1002	return vblank_bit | hblank_bit;
962	1003	}
r14844	r14845
1000	1041	return val;
1001	1042	}
1002	1043
1003		static WRITE8_HANDLER( mz2500_tv_crtc_w )
	1044	WRITE8_MEMBER(mz2500_state::mz2500_tv_crtc_w)
1004	1045	{
1005		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1006	1046	switch(offset)
1007	1047	{
1008		case 0: state->m_text_reg_index = data; break;
	1048	case 0: m_text_reg_index = data; break;
1009	1049	case 1:
1010		state->m_text_reg[state->m_text_reg_index] = data;
	1050	m_text_reg[m_text_reg_index] = data;
1011	1051
1012	1052	#if 0
1013		//printf("[%02x] <- %02x\n",state->m_text_reg_index,data);
	1053	//printf("[%02x] <- %02x\n",m_text_reg_index,data);
1014	1054	popmessage("(%02x %02x) (%02x %02x %02x %02x) (%02x %02x %02x) (%02x %02x %02x %02x)"
1015		,state->m_text_reg[0] & ~0x1e,state->m_text_reg[3]
1016		,state->m_text_reg[4],state->m_text_reg[5],state->m_text_reg[6],state->m_text_reg[7]
1017		,state->m_text_reg[8],state->m_text_reg[10],state->m_text_reg[11]
1018		,state->m_text_reg[12],state->m_text_reg[13],state->m_text_reg[14],state->m_text_reg[15]);
	1055	,m_text_reg[0] & ~0x1e,m_text_reg[3]
	1056	,m_text_reg[4],m_text_reg[5],m_text_reg[6],m_text_reg[7]
	1057	,m_text_reg[8],m_text_reg[10],m_text_reg[11]
	1058	,m_text_reg[12],m_text_reg[13],m_text_reg[14],m_text_reg[15]);
1019	1059
1020	1060	#endif
1021		//popmessage("%d %02x %d %02x %d %d",state->m_text_reg[3],state->m_text_reg[4],state->m_text_reg[5],state->m_text_reg[6],state->m_text_reg[7]*8,state->m_text_reg[8]*8);
	1061	//popmessage("%d %02x %d %02x %d %d",m_text_reg[3],m_text_reg[4],m_text_reg[5],m_text_reg[6],m_text_reg[7]*8,m_text_reg[8]*8);
1022	1062
1023		mz2500_reconfigure_screen(space->machine());
	1063	mz2500_reconfigure_screen(machine());
1024	1064
1025		if(state->m_text_reg_index == 0x0a) // set 256 color palette
	1065	if(m_text_reg_index == 0x0a) // set 256 color palette
1026	1066	{
1027	1067	int i,r,g,b;
1028	1068	UINT8 b_param,r_param,g_param;
r14844	r14845
1048	1088	bit2 = i & 0x40 ? 4 : 0;
1049	1089	g = bit0|bit1|bit2;
1050	1090
1051		palette_set_color_rgb(space->machine(), i+0x100,pal3bit(r),pal3bit(g),pal3bit(b));
	1091	palette_set_color_rgb(machine(), i+0x100,pal3bit(r),pal3bit(g),pal3bit(b));
1052	1092	}
1053	1093	}
1054		if(state->m_text_reg_index >= 0x80 && state->m_text_reg_index <= 0x8f) //Bitmap 16 clut registers
	1094	if(m_text_reg_index >= 0x80 && m_text_reg_index <= 0x8f) //Bitmap 16 clut registers
1055	1095	{
1056	1096	/*
1057	1097	---x ---- priority
1058	1098	---- xxxx clut number
1059	1099	*/
1060		state->m_clut16[state->m_text_reg_index & 0xf] = data & 0x1f;
1061		//printf("%02x -> [%02x]\n",state->m_text_reg[state->m_text_reg_index],state->m_text_reg_index);
	1100	m_clut16[m_text_reg_index & 0xf] = data & 0x1f;
	1101	//printf("%02x -> [%02x]\n",m_text_reg[m_text_reg_index],m_text_reg_index);
1062	1102
1063	1103	{
1064	1104	int i;
1065	1105
1066	1106	for(i=0;i<0x10;i++)
1067	1107	{
1068		state->m_clut256[(state->m_text_reg_index & 0xf) | (i << 4)] = (((data & 0x1f) << 4) | i);
	1108	m_clut256[(m_text_reg_index & 0xf) | (i << 4)] = (((data & 0x1f) << 4) | i);
1069	1109	}
1070	1110	}
1071	1111	}
1072	1112	break;
1073	1113	case 2: /* CG Mask reg (priority mixer) */
1074		state->m_cg_mask = data;
	1114	m_cg_mask = data;
1075	1115	break;
1076	1116	case 3:
1077	1117	/* Font size reg */
1078		state->m_text_font_reg = data & 1;
1079		mz2500_reconfigure_screen(space->machine());
	1118	m_text_font_reg = data & 1;
	1119	mz2500_reconfigure_screen(machine());
1080	1120	break;
1081	1121	}
1082	1122	}
1083	1123
1084		static WRITE8_HANDLER( mz2500_irq_sel_w )
	1124	WRITE8_MEMBER(mz2500_state::mz2500_irq_sel_w)
1085	1125	{
1086		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1087		state->m_irq_sel = data;
1088		//printf("%02x\n",state->m_irq_sel);
	1126	m_irq_sel = data;
	1127	//printf("%02x\n",m_irq_sel);
1089	1128	// activeness is trusted, see Tower of Druaga
1090		state->m_irq_mask[0] = (data & 0x08); //CRTC
1091		state->m_irq_mask[1] = (data & 0x04); //i8253
1092		state->m_irq_mask[2] = (data & 0x02); //printer
1093		state->m_irq_mask[3] = (data & 0x01); //RP5c15
	1129	m_irq_mask[0] = (data & 0x08); //CRTC
	1130	m_irq_mask[1] = (data & 0x04); //i8253
	1131	m_irq_mask[2] = (data & 0x02); //printer
	1132	m_irq_mask[3] = (data & 0x01); //RP5c15
1094	1133	}
1095	1134
1096		static WRITE8_HANDLER( mz2500_irq_data_w )
	1135	WRITE8_MEMBER(mz2500_state::mz2500_irq_data_w)
1097	1136	{
1098		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1099		if(state->m_irq_sel & 0x80)
1100		state->m_irq_vector[0] = data; //CRTC
1101		if(state->m_irq_sel & 0x40)
1102		state->m_irq_vector[1] = data; //i8253
1103		if(state->m_irq_sel & 0x20)
1104		state->m_irq_vector[2] = data; //printer
1105		if(state->m_irq_sel & 0x10)
1106		state->m_irq_vector[3] = data; //RP5c15
	1137	if(m_irq_sel & 0x80)
	1138	m_irq_vector[0] = data; //CRTC
	1139	if(m_irq_sel & 0x40)
	1140	m_irq_vector[1] = data; //i8253
	1141	if(m_irq_sel & 0x20)
	1142	m_irq_vector[2] = data; //printer
	1143	if(m_irq_sel & 0x10)
	1144	m_irq_vector[3] = data; //RP5c15
1107	1145
1108		//  popmessage("%02x %02x %02x %02x",state->m_irq_vector[0],state->m_irq_vector[1],state->m_irq_vector[2],state->m_irq_vector[3]);
	1146	//  popmessage("%02x %02x %02x %02x",m_irq_vector[0],m_irq_vector[1],m_irq_vector[2],m_irq_vector[3]);
1109	1147	}
1110	1148
1111		static WRITE8_HANDLER( mz2500_fdc_w )
	1149	WRITE8_MEMBER(mz2500_state::mz2500_fdc_w)
1112	1150	{
1113		device_t* dev = space->machine().device("mb8877a");
	1151	device_t* dev = machine().device("mb8877a");
1114	1152
1115	1153	switch(offset+0xdc)
1116	1154	{
1117	1155	case 0xdc:
1118	1156	wd17xx_set_drive(dev,data & 3);
1119		floppy_mon_w(floppy_get_device(space->machine(), data & 3), (data & 0x80) ? CLEAR_LINE : ASSERT_LINE);
1120		floppy_drive_set_ready_state(floppy_get_device(space->machine(), data & 3), 1,0);
	1157	floppy_mon_w(floppy_get_device(machine(), data & 3), (data & 0x80) ? CLEAR_LINE : ASSERT_LINE);
	1158	floppy_drive_set_ready_state(floppy_get_device(machine(), data & 3), 1,0);
1121	1159	break;
1122	1160	case 0xdd:
1123	1161	wd17xx_set_side(dev,(data & 1));
r14844	r14845
1156	1194	};
1157	1195
1158	1196	static ADDRESS_MAP_START(mz2500_map, AS_PROGRAM, 8, mz2500_state )
1159		AM_RANGE(0x0000, 0x1fff) AM_READWRITE_LEGACY(bank0_r,bank0_w)
1160		AM_RANGE(0x2000, 0x3fff) AM_READWRITE_LEGACY(bank1_r,bank1_w)
1161		AM_RANGE(0x4000, 0x5fff) AM_READWRITE_LEGACY(bank2_r,bank2_w)
1162		AM_RANGE(0x6000, 0x7fff) AM_READWRITE_LEGACY(bank3_r,bank3_w)
1163		AM_RANGE(0x8000, 0x9fff) AM_READWRITE_LEGACY(bank4_r,bank4_w)
1164		AM_RANGE(0xa000, 0xbfff) AM_READWRITE_LEGACY(bank5_r,bank5_w)
1165		AM_RANGE(0xc000, 0xdfff) AM_READWRITE_LEGACY(bank6_r,bank6_w)
1166		AM_RANGE(0xe000, 0xffff) AM_READWRITE_LEGACY(bank7_r,bank7_w)
	1197	AM_RANGE(0x0000, 0x1fff) AM_READWRITE(bank0_r,bank0_w)
	1198	AM_RANGE(0x2000, 0x3fff) AM_READWRITE(bank1_r,bank1_w)
	1199	AM_RANGE(0x4000, 0x5fff) AM_READWRITE(bank2_r,bank2_w)
	1200	AM_RANGE(0x6000, 0x7fff) AM_READWRITE(bank3_r,bank3_w)
	1201	AM_RANGE(0x8000, 0x9fff) AM_READWRITE(bank4_r,bank4_w)
	1202	AM_RANGE(0xa000, 0xbfff) AM_READWRITE(bank5_r,bank5_w)
	1203	AM_RANGE(0xc000, 0xdfff) AM_READWRITE(bank6_r,bank6_w)
	1204	AM_RANGE(0xe000, 0xffff) AM_READWRITE(bank7_r,bank7_w)
1167	1205	ADDRESS_MAP_END
1168	1206
1169	1207
1170		static READ8_HANDLER( mz2500_rom_r )
	1208	READ8_MEMBER(mz2500_state::mz2500_rom_r)
1171	1209	{
1172		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1173		UINT8 *rom = space->machine().region("rom")->base();
	1210	UINT8 *rom = machine().region("rom")->base();
1174	1211	UINT8 res;
1175	1212
1176		state->m_lrom_index = (cpu_get_reg(space->machine().device("maincpu"), Z80_B));
	1213	m_lrom_index = (cpu_get_reg(machine().device("maincpu"), Z80_B));
1177	1214
1178		state->m_rom_index = (state->m_rom_index & 0xffff00) | (state->m_lrom_index & 0xff);
	1215	m_rom_index = (m_rom_index & 0xffff00) | (m_lrom_index & 0xff);
1179	1216
1180		res = rom[state->m_rom_index];
	1217	res = rom[m_rom_index];
1181	1218
1182	1219	return res;
1183	1220	}
1184	1221
1185		static WRITE8_HANDLER( mz2500_rom_w )
	1222	WRITE8_MEMBER(mz2500_state::mz2500_rom_w)
1186	1223	{
1187		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1188		state->m_hrom_index = (cpu_get_reg(space->machine().device("maincpu"), Z80_B));
	1224	m_hrom_index = (cpu_get_reg(machine().device("maincpu"), Z80_B));
1189	1225
1190		state->m_rom_index = (data << 8) | (state->m_rom_index & 0x0000ff) | ((state->m_hrom_index & 0xff)<<16);
	1226	m_rom_index = (data << 8) | (m_rom_index & 0x0000ff) | ((m_hrom_index & 0xff)<<16);
1191	1227	//printf("%02x\n",data);
1192	1228	}
1193	1229
1194	1230	/* sets 16 color entries out of 4096 possible combinations */
1195		static WRITE8_HANDLER( palette4096_io_w )
	1231	WRITE8_MEMBER(mz2500_state::palette4096_io_w)
1196	1232	{
1197		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1198	1233	UINT8 pal_index;
1199	1234	UINT8 pal_entry;
1200	1235
1201		pal_index = cpu_get_reg(space->machine().device("maincpu"), Z80_B);
	1236	pal_index = cpu_get_reg(machine().device("maincpu"), Z80_B);
1202	1237	pal_entry = (pal_index & 0x1e) >> 1;
1203	1238
1204	1239	if(pal_index & 1)
1205		state->m_pal[pal_entry].g = (data & 0x0f);
	1240	m_pal[pal_entry].g = (data & 0x0f);
1206	1241	else
1207	1242	{
1208		state->m_pal[pal_entry].r = (data & 0xf0) >> 4;
1209		state->m_pal[pal_entry].b = data & 0x0f;
	1243	m_pal[pal_entry].r = (data & 0xf0) >> 4;
	1244	m_pal[pal_entry].b = data & 0x0f;
1210	1245	}
1211	1246
1212		palette_set_color_rgb(space->machine(), pal_entry+0x10, pal4bit(state->m_pal[pal_entry].r), pal4bit(state->m_pal[pal_entry].g), pal4bit(state->m_pal[pal_entry].b));
	1247	palette_set_color_rgb(machine(), pal_entry+0x10, pal4bit(m_pal[pal_entry].r), pal4bit(m_pal[pal_entry].g), pal4bit(m_pal[pal_entry].b));
1213	1248	}
1214	1249
1215	1250	static READ8_DEVICE_HANDLER( mz2500_wd17xx_r )
r14844	r14845
1224	1259	wd17xx_w(device, offset, data ^ state->m_fdc_reverse);
1225	1260	}
1226	1261
1227		static READ8_HANDLER( mz2500_bplane_latch_r )
	1262	READ8_MEMBER(mz2500_state::mz2500_bplane_latch_r)
1228	1263	{
1229		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1230		if(state->m_cg_reg[7] & 0x10)
1231		return mz2500_cg_latch_compare(state);
	1264	if(m_cg_reg[7] & 0x10)
	1265	return mz2500_cg_latch_compare();
1232	1266	else
1233		return state->m_cg_latch[0];
	1267	return m_cg_latch[0];
1234	1268	}
1235	1269
1236	1270
1237		static READ8_HANDLER( mz2500_rplane_latch_r )
	1271	READ8_MEMBER(mz2500_state::mz2500_rplane_latch_r)
1238	1272	{
1239		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1240		if(state->m_cg_reg[0x07] & 0x10)
	1273	if(m_cg_reg[0x07] & 0x10)
1241	1274	{
1242	1275	UINT8 vblank_bit;
1243	1276
1244		vblank_bit = space->machine().primary_screen->vblank() ? 0 : 0x80 | state->m_cg_clear_flag;
	1277	vblank_bit = machine().primary_screen->vblank() ? 0 : 0x80 | m_cg_clear_flag;
1245	1278
1246	1279	return vblank_bit;
1247	1280	}
1248	1281	else
1249		return state->m_cg_latch[1];
	1282	return m_cg_latch[1];
1250	1283	}
1251	1284
1252		static READ8_HANDLER( mz2500_gplane_latch_r )
	1285	READ8_MEMBER(mz2500_state::mz2500_gplane_latch_r)
1253	1286	{
1254		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1255		return state->m_cg_latch[2];
	1287	return m_cg_latch[2];
1256	1288	}
1257	1289
1258		static READ8_HANDLER( mz2500_iplane_latch_r )
	1290	READ8_MEMBER(mz2500_state::mz2500_iplane_latch_r)
1259	1291	{
1260		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1261		return state->m_cg_latch[3];
	1292	return m_cg_latch[3];
1262	1293	}
1263	1294
1264	1295	/*
r14844	r14845
1291	1322	0x18: CG color masking
1292	1323	*/
1293	1324
1294		static WRITE8_HANDLER( mz2500_cg_addr_w )
	1325	WRITE8_MEMBER(mz2500_state::mz2500_cg_addr_w)
1295	1326	{
1296		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1297		state->m_cg_reg_index = data;
	1327	m_cg_reg_index = data;
1298	1328	}
1299	1329
1300		static WRITE8_HANDLER( mz2500_cg_data_w )
	1330	WRITE8_MEMBER(mz2500_state::mz2500_cg_data_w)
1301	1331	{
1302		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1303		state->m_cg_reg[state->m_cg_reg_index & 0x1f] = data;
	1332	m_cg_reg[m_cg_reg_index & 0x1f] = data;
1304	1333
1305		if((state->m_cg_reg_index & 0x1f) == 0x08) //accessing VS LO reg clears VS HI reg
1306		state->m_cg_reg[0x09] = 0;
	1334	if((m_cg_reg_index & 0x1f) == 0x08) //accessing VS LO reg clears VS HI reg
	1335	m_cg_reg[0x09] = 0;
1307	1336
1308		if((state->m_cg_reg_index & 0x1f) == 0x0a) //accessing VE LO reg clears VE HI reg
1309		state->m_cg_reg[0x0b] = 0;
	1337	if((m_cg_reg_index & 0x1f) == 0x0a) //accessing VE LO reg clears VE HI reg
	1338	m_cg_reg[0x0b] = 0;
1310	1339
1311		if((state->m_cg_reg_index & 0x1f) == 0x05 && (state->m_cg_reg[0x05] & 0xc0) == 0x80) //clear bitmap buffer
	1340	if((m_cg_reg_index & 0x1f) == 0x05 && (m_cg_reg[0x05] & 0xc0) == 0x80) //clear bitmap buffer
1312	1341	{
1313	1342	UINT32 i;
1314		UINT8 *vram = space->machine().region("maincpu")->base();
	1343	UINT8 *vram = machine().region("maincpu")->base();
1315	1344	UINT32 layer_bank;
1316	1345
1317		layer_bank = (state->m_cg_reg[0x0e] & 0x80) ? 0x10000 : 0x00000;
	1346	layer_bank = (m_cg_reg[0x0e] & 0x80) ? 0x10000 : 0x00000;
1318	1347
1319	1348	/* TODO: this isn't yet 100% accurate */
1320		if(state->m_cg_reg[0x05] & 1)
	1349	if(m_cg_reg[0x05] & 1)
1321	1350	{
1322	1351	for(i=0;i<0x4000;i++)
1323	1352	vram[i+0x40000+layer_bank] = 0x00; //clear B
1324	1353	}
1325		if(state->m_cg_reg[0x05] & 2)
	1354	if(m_cg_reg[0x05] & 2)
1326	1355	{
1327	1356	for(i=0;i<0x4000;i++)
1328	1357	vram[i+0x44000+layer_bank] = 0x00; //clear R
1329	1358	}
1330		if(state->m_cg_reg[0x05] & 4)
	1359	if(m_cg_reg[0x05] & 4)
1331	1360	{
1332	1361	for(i=0;i<0x4000;i++)
1333	1362	vram[i+0x48000+layer_bank] = 0x00; //clear G
1334	1363	}
1335		if(state->m_cg_reg[0x05] & 8)
	1364	if(m_cg_reg[0x05] & 8)
1336	1365	{
1337	1366	for(i=0;i<0x4000;i++)
1338	1367	vram[i+0x4c000+layer_bank] = 0x00; //clear I
1339	1368	}
1340		state->m_cg_clear_flag = 1;
	1369	m_cg_clear_flag = 1;
1341	1370	}
1342	1371
1343	1372	{
1344		mz2500_reconfigure_screen(space->machine());
	1373	mz2500_reconfigure_screen(machine());
1345	1374	}
1346	1375
1347		if(state->m_cg_reg_index & 0x80) //enable auto-inc
1348		state->m_cg_reg_index = (state->m_cg_reg_index & 0xfc) | ((state->m_cg_reg_index + 1) & 0x03);
	1376	if(m_cg_reg_index & 0x80) //enable auto-inc
	1377	m_cg_reg_index = (m_cg_reg_index & 0xfc) | ((m_cg_reg_index + 1) & 0x03);
1349	1378	}
1350	1379
1351		static WRITE8_HANDLER( timer_w )
	1380	WRITE8_MEMBER(mz2500_state::timer_w)
1352	1381	{
1353		device_t *pit8253 = space->machine().device("pit");
	1382	device_t *pit8253 = machine().device("pit");
1354	1383
1355	1384	pit8253_gate0_w(pit8253, 1);
1356	1385	pit8253_gate1_w(pit8253, 1);
r14844	r14845
1361	1390	}
1362	1391
1363	1392
1364		static READ8_HANDLER( mz2500_joystick_r )
	1393	READ8_MEMBER(mz2500_state::mz2500_joystick_r)
1365	1394	{
1366		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1367	1395	UINT8 res,dir_en,in_r;
1368	1396
1369	1397	res = 0xff;
1370		in_r = ~input_port_read(space->machine(), state->m_joy_mode & 0x40 ? "JOY_2P" : "JOY_1P");
	1398	in_r = ~input_port_read(machine(), m_joy_mode & 0x40 ? "JOY_2P" : "JOY_1P");
1371	1399
1372		if(state->m_joy_mode & 0x40)
	1400	if(m_joy_mode & 0x40)
1373	1401	{
1374		if(!(state->m_joy_mode & 0x04)) res &= ~0x20;
1375		if(!(state->m_joy_mode & 0x08)) res &= ~0x10;
1376		dir_en = (state->m_joy_mode & 0x20) ? 0 : 1;
	1402	if(!(m_joy_mode & 0x04)) res &= ~0x20;
	1403	if(!(m_joy_mode & 0x08)) res &= ~0x10;
	1404	dir_en = (m_joy_mode & 0x20) ? 0 : 1;
1377	1405	}
1378	1406	else
1379	1407	{
1380		if(!(state->m_joy_mode & 0x01)) res &= ~0x20;
1381		if(!(state->m_joy_mode & 0x02)) res &= ~0x10;
1382		dir_en = (state->m_joy_mode & 0x10) ? 0 : 1;
	1408	if(!(m_joy_mode & 0x01)) res &= ~0x20;
	1409	if(!(m_joy_mode & 0x02)) res &= ~0x10;
	1410	dir_en = (m_joy_mode & 0x10) ? 0 : 1;
1383	1411	}
1384	1412
1385	1413	if(dir_en)
r14844	r14845
1390	1418	return res;
1391	1419	}
1392	1420
1393		static WRITE8_HANDLER( mz2500_joystick_w )
	1421	WRITE8_MEMBER(mz2500_state::mz2500_joystick_w)
1394	1422	{
1395		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1396		state->m_joy_mode = data;
	1423	m_joy_mode = data;
1397	1424	}
1398	1425
1399	1426
1400		static READ8_HANDLER( mz2500_kanji_r )
	1427	READ8_MEMBER(mz2500_state::mz2500_kanji_r)
1401	1428	{
1402		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1403		UINT8 *knj2_rom = space->machine().region("kanji2")->base();
	1429	UINT8 *knj2_rom = machine().region("kanji2")->base();
1404	1430
1405	1431	printf("Read from kanji 2 ROM\n");
1406	1432
1407		return knj2_rom[(state->m_kanji_index << 1) | (offset & 1)];
	1433	return knj2_rom[(m_kanji_index << 1) | (offset & 1)];
1408	1434	}
1409	1435
1410		static WRITE8_HANDLER( mz2500_kanji_w )
	1436	WRITE8_MEMBER(mz2500_state::mz2500_kanji_w)
1411	1437	{
1412		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1413		(offset & 1) ? (state->m_kanji_index = (data << 8) | (state->m_kanji_index & 0xff)) : (state->m_kanji_index = (data & 0xff) | (state->m_kanji_index & 0xff00));
	1438	(offset & 1) ? (m_kanji_index = (data << 8) | (m_kanji_index & 0xff)) : (m_kanji_index = (data & 0xff) | (m_kanji_index & 0xff00));
1414	1439	}
1415	1440
1416		static READ8_HANDLER( rp5c15_8_r )
	1441	READ8_MEMBER(mz2500_state::rp5c15_8_r)
1417	1442	{
1418		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1419		UINT8 rtc_index = (cpu_get_reg(space->machine().device("maincpu"), Z80_B));
	1443	UINT8 rtc_index = (cpu_get_reg(machine().device("maincpu"), Z80_B));
1420	1444
1421		return state->m_rtc->read(*space, rtc_index);
	1445	return m_rtc->read(*&space, rtc_index);
1422	1446	}
1423	1447
1424		static WRITE8_HANDLER( rp5c15_8_w )
	1448	WRITE8_MEMBER(mz2500_state::rp5c15_8_w)
1425	1449	{
1426		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1427		UINT8 rtc_index = (cpu_get_reg(space->machine().device("maincpu"), Z80_B));
	1450	UINT8 rtc_index = (cpu_get_reg(machine().device("maincpu"), Z80_B));
1428	1451
1429		state->m_rtc->write(*space, rtc_index, data);
	1452	m_rtc->write(*&space, rtc_index, data);
1430	1453	}
1431	1454
1432	1455
1433		static READ8_HANDLER( mz2500_emm_data_r )
	1456	READ8_MEMBER(mz2500_state::mz2500_emm_data_r)
1434	1457	{
1435		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1436		UINT8 *emm_ram = space->machine().region("emm")->base();
	1458	UINT8 *emm_ram = machine().region("emm")->base();
1437	1459	UINT8 emm_lo_index;
1438	1460
1439		emm_lo_index = (cpu_get_reg(space->machine().device("maincpu"), Z80_B));
	1461	emm_lo_index = (cpu_get_reg(machine().device("maincpu"), Z80_B));
1440	1462
1441		state->m_emm_offset = (state->m_emm_offset & 0xffff00) | (emm_lo_index & 0xff);
	1463	m_emm_offset = (m_emm_offset & 0xffff00) | (emm_lo_index & 0xff);
1442	1464
1443		if(state->m_emm_offset < 0x100000) //emm max size
1444		return emm_ram[state->m_emm_offset];
	1465	if(m_emm_offset < 0x100000) //emm max size
	1466	return emm_ram[m_emm_offset];
1445	1467
1446	1468	return 0xff;
1447	1469	}
1448	1470
1449		static WRITE8_HANDLER( mz2500_emm_addr_w )
	1471	WRITE8_MEMBER(mz2500_state::mz2500_emm_addr_w)
1450	1472	{
1451		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1452	1473	UINT8 emm_hi_index;
1453	1474
1454		emm_hi_index = (cpu_get_reg(space->machine().device("maincpu"), Z80_B));
	1475	emm_hi_index = (cpu_get_reg(machine().device("maincpu"), Z80_B));
1455	1476
1456		state->m_emm_offset = ((emm_hi_index & 0xff) << 16) | ((data & 0xff) << 8) | (state->m_emm_offset & 0xff);
	1477	m_emm_offset = ((emm_hi_index & 0xff) << 16) | ((data & 0xff) << 8) | (m_emm_offset & 0xff);
1457	1478	}
1458	1479
1459		static WRITE8_HANDLER( mz2500_emm_data_w )
	1480	WRITE8_MEMBER(mz2500_state::mz2500_emm_data_w)
1460	1481	{
1461		mz2500_state *state = space->machine().driver_data<mz2500_state>();
1462		UINT8 *emm_ram = space->machine().region("emm")->base();
	1482	UINT8 *emm_ram = machine().region("emm")->base();
1463	1483	UINT8 emm_lo_index;
1464	1484
1465		emm_lo_index = (cpu_get_reg(space->machine().device("maincpu"), Z80_B));
	1485	emm_lo_index = (cpu_get_reg(machine().device("maincpu"), Z80_B));
1466	1486
1467		state->m_emm_offset = (state->m_emm_offset & 0xffff00) | (emm_lo_index & 0xff);
	1487	m_emm_offset = (m_emm_offset & 0xffff00) | (emm_lo_index & 0xff);
1468	1488
1469		if(state->m_emm_offset < 0x100000) //emm max size
1470		emm_ram[state->m_emm_offset] = data;
	1489	if(m_emm_offset < 0x100000) //emm max size
	1490	emm_ram[m_emm_offset] = data;
1471	1491	}
1472	1492
1473	1493	static ADDRESS_MAP_START(mz2500_io, AS_IO, 8, mz2500_state )
r14844	r14845
1477	1497	//  AM_RANGE(0x98, 0x99) ADPCM, unknown type, custom?
1478	1498	AM_RANGE(0xa0, 0xa3) AM_DEVREADWRITE_LEGACY("z80sio",z80sio_ba_cd_r,z80sio_ba_cd_w)
1479	1499	//  AM_RANGE(0xa4, 0xa5) AM_READWRITE_LEGACY(sasi_r, sasi_w)
1480		AM_RANGE(0xa8, 0xa8) AM_WRITE_LEGACY(mz2500_rom_w)
1481		AM_RANGE(0xa9, 0xa9) AM_READ_LEGACY(mz2500_rom_r)
1482		AM_RANGE(0xac, 0xac) AM_WRITE_LEGACY(mz2500_emm_addr_w)
1483		AM_RANGE(0xad, 0xad) AM_READ_LEGACY(mz2500_emm_data_r) AM_WRITE_LEGACY(mz2500_emm_data_w)
1484		AM_RANGE(0xae, 0xae) AM_WRITE_LEGACY(palette4096_io_w)
	1500	AM_RANGE(0xa8, 0xa8) AM_WRITE(mz2500_rom_w)
	1501	AM_RANGE(0xa9, 0xa9) AM_READ(mz2500_rom_r)
	1502	AM_RANGE(0xac, 0xac) AM_WRITE(mz2500_emm_addr_w)
	1503	AM_RANGE(0xad, 0xad) AM_READ(mz2500_emm_data_r) AM_WRITE(mz2500_emm_data_w)
	1504	AM_RANGE(0xae, 0xae) AM_WRITE(palette4096_io_w)
1485	1505	//  AM_RANGE(0xb0, 0xb3) AM_READWRITE_LEGACY(sio_r,sio_w)
1486		AM_RANGE(0xb4, 0xb4) AM_READWRITE_LEGACY(mz2500_bank_addr_r,mz2500_bank_addr_w)
1487		AM_RANGE(0xb5, 0xb5) AM_READWRITE_LEGACY(mz2500_bank_data_r,mz2500_bank_data_w)
	1506	AM_RANGE(0xb4, 0xb4) AM_READWRITE(mz2500_bank_addr_r,mz2500_bank_addr_w)
	1507	AM_RANGE(0xb5, 0xb5) AM_READWRITE(mz2500_bank_data_r,mz2500_bank_data_w)
1488	1508	AM_RANGE(0xb7, 0xb7) AM_WRITENOP
1489		AM_RANGE(0xb8, 0xb9) AM_READWRITE_LEGACY(mz2500_kanji_r,mz2500_kanji_w)
1490		AM_RANGE(0xbc, 0xbc) AM_READ_LEGACY(mz2500_bplane_latch_r) AM_WRITE_LEGACY(mz2500_cg_addr_w)
1491		AM_RANGE(0xbd, 0xbd) AM_READ_LEGACY(mz2500_rplane_latch_r) AM_WRITE_LEGACY(mz2500_cg_data_w)
1492		AM_RANGE(0xbe, 0xbe) AM_READ_LEGACY(mz2500_gplane_latch_r)
1493		AM_RANGE(0xbf, 0xbf) AM_READ_LEGACY(mz2500_iplane_latch_r)
1494		AM_RANGE(0xc6, 0xc6) AM_WRITE_LEGACY(mz2500_irq_sel_w)
1495		AM_RANGE(0xc7, 0xc7) AM_WRITE_LEGACY(mz2500_irq_data_w)
	1509	AM_RANGE(0xb8, 0xb9) AM_READWRITE(mz2500_kanji_r,mz2500_kanji_w)
	1510	AM_RANGE(0xbc, 0xbc) AM_READ(mz2500_bplane_latch_r) AM_WRITE(mz2500_cg_addr_w)
	1511	AM_RANGE(0xbd, 0xbd) AM_READ(mz2500_rplane_latch_r) AM_WRITE(mz2500_cg_data_w)
	1512	AM_RANGE(0xbe, 0xbe) AM_READ(mz2500_gplane_latch_r)
	1513	AM_RANGE(0xbf, 0xbf) AM_READ(mz2500_iplane_latch_r)
	1514	AM_RANGE(0xc6, 0xc6) AM_WRITE(mz2500_irq_sel_w)
	1515	AM_RANGE(0xc7, 0xc7) AM_WRITE(mz2500_irq_data_w)
1496	1516	AM_RANGE(0xc8, 0xc9) AM_DEVREADWRITE_LEGACY("ym", ym2203_r, ym2203_w)
1497	1517	//  AM_RANGE(0xca, 0xca) AM_READWRITE_LEGACY(voice_r,voice_w)
1498		AM_RANGE(0xcc, 0xcc) AM_READWRITE_LEGACY(rp5c15_8_r, rp5c15_8_w)
1499		AM_RANGE(0xce, 0xce) AM_WRITE_LEGACY(mz2500_dictionary_bank_w)
1500		AM_RANGE(0xcf, 0xcf) AM_WRITE_LEGACY(mz2500_kanji_bank_w)
	1518	AM_RANGE(0xcc, 0xcc) AM_READWRITE(rp5c15_8_r, rp5c15_8_w)
	1519	AM_RANGE(0xce, 0xce) AM_WRITE(mz2500_dictionary_bank_w)
	1520	AM_RANGE(0xcf, 0xcf) AM_WRITE(mz2500_kanji_bank_w)
1501	1521	AM_RANGE(0xd8, 0xdb) AM_DEVREADWRITE_LEGACY("mb8877a", mz2500_wd17xx_r, mz2500_wd17xx_w)
1502		AM_RANGE(0xdc, 0xdd) AM_WRITE_LEGACY(mz2500_fdc_w)
	1522	AM_RANGE(0xdc, 0xdd) AM_WRITE(mz2500_fdc_w)
1503	1523	AM_RANGE(0xde, 0xde) AM_WRITENOP
1504	1524	AM_RANGE(0xe0, 0xe3) AM_DEVREADWRITE("i8255_0", i8255_device, read, write)
1505	1525	AM_RANGE(0xe4, 0xe7) AM_DEVREADWRITE_LEGACY("pit", pit8253_r, pit8253_w)
1506	1526	AM_RANGE(0xe8, 0xeb) AM_DEVREADWRITE_LEGACY("z80pio_1", z80pio_ba_cd_r, z80pio_ba_cd_w)
1507		AM_RANGE(0xef, 0xef) AM_READWRITE_LEGACY(mz2500_joystick_r,mz2500_joystick_w)
1508		AM_RANGE(0xf0, 0xf3) AM_WRITE_LEGACY(timer_w)
1509		AM_RANGE(0xf4, 0xf7) AM_READ_LEGACY(mz2500_crtc_hvblank_r) AM_WRITE_LEGACY(mz2500_tv_crtc_w)
	1527	AM_RANGE(0xef, 0xef) AM_READWRITE(mz2500_joystick_r,mz2500_joystick_w)
	1528	AM_RANGE(0xf0, 0xf3) AM_WRITE(timer_w)
	1529	AM_RANGE(0xf4, 0xf7) AM_READ(mz2500_crtc_hvblank_r) AM_WRITE(mz2500_tv_crtc_w)
1510	1530	//  AM_RANGE(0xf8, 0xf9) AM_READWRITE_LEGACY(extrom_r,extrom_w)
1511	1531	ADDRESS_MAP_END
1512	1532

src/mess/drivers/ti99_2.c

r14844	r14845
92	92	int m_ROM_paged;
93	93	int m_irq_state;
94	94	int m_KeyRow;
	95	DECLARE_WRITE8_MEMBER(ti99_2_write_kbd);
	96	DECLARE_WRITE8_MEMBER(ti99_2_write_misc_cru);
95	97	};
96	98
97	99
r14844	r14845
110	112	state->m_ROM_paged = 1;
111	113	}
112	114
113		#define TI99_2_32_ROMPAGE0 (space->machine().region("maincpu")->base()+0x4000)
114		#define TI99_2_32_ROMPAGE1 (space->machine().region("maincpu")->base()+0x10000)
	115	#define TI99_2_32_ROMPAGE0 (machine().region("maincpu")->base()+0x4000)
	116	#define TI99_2_32_ROMPAGE1 (machine().region("maincpu")->base()+0x10000)
115	117
116	118	static MACHINE_RESET( ti99_2 )
117	119	{
r14844	r14845
217	219	/* current keyboard row */
218	220
219	221	/* write the current keyboard row */
220		static WRITE8_HANDLER ( ti99_2_write_kbd )
	222	WRITE8_MEMBER(ti99_2_state::ti99_2_write_kbd)
221	223	{
222		ti99_2_state *state = space->machine().driver_data<ti99_2_state>();
223	224	offset &= 0x7;  /* other address lines are not decoded */
224	225
225	226	if (offset <= 2)
226	227	{
227	228	/* this implementation is just a guess */
228	229	if (data)
229		state->m_KeyRow |= 1 << offset;
	230	m_KeyRow |= 1 << offset;
230	231	else
231		state->m_KeyRow &= ~ (1 << offset);
	232	m_KeyRow &= ~ (1 << offset);
232	233	}
233	234	/* now, we handle ROM paging */
234		if (state->m_ROM_paged)
	235	if (m_ROM_paged)
235	236	{   /* if we have paged ROMs, page according to S0 keyboard interface line */
236		memory_set_bankptr(space->machine(), "bank1", (state->m_KeyRow == 0) ? TI99_2_32_ROMPAGE1 : TI99_2_32_ROMPAGE0);
	237	memory_set_bankptr(machine(), "bank1", (m_KeyRow == 0) ? TI99_2_32_ROMPAGE1 : TI99_2_32_ROMPAGE0);
237	238	}
238	239	}
239	240
240		static WRITE8_HANDLER ( ti99_2_write_misc_cru )
	241	WRITE8_MEMBER(ti99_2_state::ti99_2_write_misc_cru)
241	242	{
242	243	offset &= 0x7;  /* other address lines are not decoded */
243	244
r14844	r14845
281	282	static ADDRESS_MAP_START(ti99_2_io, AS_IO, 8, ti99_2_state )
282	283	AM_RANGE(0x0E00, 0x0E7f) AM_READ_LEGACY(ti99_2_read_kbd)
283	284	AM_RANGE(0x0E80, 0x0Eff) AM_READ_LEGACY(ti99_2_read_misc_cru)
284		AM_RANGE(0x7000, 0x73ff) AM_WRITE_LEGACY(ti99_2_write_kbd)
285		AM_RANGE(0x7400, 0x77ff) AM_WRITE_LEGACY(ti99_2_write_misc_cru)
	285	AM_RANGE(0x7000, 0x73ff) AM_WRITE(ti99_2_write_kbd)
	286	AM_RANGE(0x7400, 0x77ff) AM_WRITE(ti99_2_write_misc_cru)
286	287	ADDRESS_MAP_END
287	288
288	289

src/mess/drivers/multi8.c

r14844	r14845
62	62	UINT8 m_pen_clut[8];
63	63	UINT8 m_bw_mode;
64	64	UINT16 m_knj_addr;
	65	DECLARE_READ8_MEMBER(ay8912_0_r);
	66	DECLARE_READ8_MEMBER(ay8912_1_r);
65	67	};
66	68
67	69	#define mc6845_h_char_total    (state->m_crtc_vreg[0])
r14844	r14845
321	323	}
322	324	}
323	325
324		static READ8_HANDLER( ay8912_0_r ) { return ay8910_r(space->machine().device("aysnd"),0); }
325		static READ8_HANDLER( ay8912_1_r ) { return ay8910_r(space->machine().device("aysnd"),1); }
	326	READ8_MEMBER(multi8_state::ay8912_0_r){ return ay8910_r(machine().device("aysnd"),0); }
	327	READ8_MEMBER(multi8_state::ay8912_1_r){ return ay8910_r(machine().device("aysnd"),1); }
326	328
327	329	READ8_MEMBER( multi8_state::multi8_kanji_r )
328	330	{
r14844	r14845
347	349	AM_RANGE(0x00, 0x00) AM_READ(key_input_r) AM_WRITENOP//keyboard
348	350	AM_RANGE(0x01, 0x01) AM_READ(key_status_r) AM_WRITENOP//keyboard
349	351	AM_RANGE(0x18, 0x19) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
350		AM_RANGE(0x18, 0x18) AM_READ_LEGACY(ay8912_0_r)
351		AM_RANGE(0x1a, 0x1a) AM_READ_LEGACY(ay8912_1_r)
	352	AM_RANGE(0x18, 0x18) AM_READ(ay8912_0_r)
	353	AM_RANGE(0x1a, 0x1a) AM_READ(ay8912_1_r)
352	354	AM_RANGE(0x1c, 0x1d) AM_WRITE(multi8_6845_w)
353	355	//  AM_RANGE(0x20, 0x21) //sio, cmt
354	356	//  AM_RANGE(0x24, 0x27) //pit

src/mess/drivers/vtech1.c

r14844	r14845
187	187	int m_fdc_write;
188	188	int m_fdc_offs;
189	189	int m_fdc_latch;
	190	DECLARE_READ8_MEMBER(vtech1_fdc_r);
	191	DECLARE_WRITE8_MEMBER(vtech1_fdc_w);
	192	DECLARE_READ8_MEMBER(vtech1_serial_r);
	193	DECLARE_WRITE8_MEMBER(vtech1_serial_w);
	194	DECLARE_READ8_MEMBER(vtech1_lightpen_r);
	195	DECLARE_READ8_MEMBER(vtech1_joystick_r);
	196	DECLARE_READ8_MEMBER(vtech1_keyboard_r);
	197	DECLARE_WRITE8_MEMBER(vtech1_latch_w);
	198	DECLARE_WRITE8_MEMBER(vtech1_memory_bank_w);
	199	DECLARE_WRITE8_MEMBER(vtech1_video_bank_w);
190	200	};
191	201
192	202
r14844	r14845
309	319	}
310	320	}
311	321
312		static READ8_HANDLER( vtech1_fdc_r )
	322	READ8_MEMBER(vtech1_state::vtech1_fdc_r)
313	323	{
314		vtech1_state *vtech1 = space->machine().driver_data<vtech1_state>();
315	324	int data = 0xff;
316	325
317	326	switch (offset)
318	327	{
319	328	case 1: /* data (read-only) */
320		if (vtech1->m_fdc_bits > 0)
	329	if (m_fdc_bits > 0)
321	330	{
322		if( vtech1->m_fdc_status & 0x80 )
323		vtech1->m_fdc_bits--;
324		data = (vtech1->m_data >> vtech1->m_fdc_bits) & 0xff;
	331	if( m_fdc_status & 0x80 )
	332	m_fdc_bits--;
	333	data = (m_data >> m_fdc_bits) & 0xff;
325	334	if (LOG_VTECH1_FDC) {
326	335	logerror("vtech1_fdc_r bits %d%d%d%d%d%d%d%d\n",
327	336	(data>>7)&1,(data>>6)&1,(data>>5)&1,(data>>4)&1,
328	337	(data>>3)&1,(data>>2)&1,(data>>1)&1,(data>>0)&1 );
329	338	}
330	339	}
331		if (vtech1->m_fdc_bits == 0)
	340	if (m_fdc_bits == 0)
332	341	{
333		vtech1->m_data = vtech1->m_fdc_data[vtech1->m_fdc_offs];
	342	m_data = m_fdc_data[m_fdc_offs];
334	343	if (LOG_VTECH1_FDC)
335		logerror("vtech1_fdc_r %d : data ($%04X) $%02X\n", offset, vtech1->m_fdc_offs, vtech1->m_data);
336		if(vtech1->m_fdc_status & 0x80)
	344	logerror("vtech1_fdc_r %d : data ($%04X) $%02X\n", offset, m_fdc_offs, m_data);
	345	if(m_fdc_status & 0x80)
337	346	{
338		vtech1->m_fdc_bits = 8;
339		vtech1->m_fdc_offs = (vtech1->m_fdc_offs + 1) % TRKSIZE_FM;
	347	m_fdc_bits = 8;
	348	m_fdc_offs = (m_fdc_offs + 1) % TRKSIZE_FM;
340	349	}
341		vtech1->m_fdc_status &= ~0x80;
	350	m_fdc_status &= ~0x80;
342	351	}
343	352	break;
344	353	case 2: /* polling (read-only) */
345	354	/* fake */
346		if (vtech1->m_drive >= 0)
347		vtech1->m_fdc_status |= 0x80;
348		data = vtech1->m_fdc_status;
	355	if (m_drive >= 0)
	356	m_fdc_status |= 0x80;
	357	data = m_fdc_status;
349	358	break;
350	359	case 3: /* write protect status (read-only) */
351		if (vtech1->m_drive >= 0)
352		data = vtech1->m_fdc_wrprot[vtech1->m_drive];
	360	if (m_drive >= 0)
	361	data = m_fdc_wrprot[m_drive];
353	362	if (LOG_VTECH1_FDC)
354	363	logerror("vtech1_fdc_r %d : write_protect $%02X\n", offset, data);
355	364	break;
r14844	r14845
357	366	return data;
358	367	}
359	368
360		static WRITE8_HANDLER( vtech1_fdc_w )
	369	WRITE8_MEMBER(vtech1_state::vtech1_fdc_w)
361	370	{
362		vtech1_state *vtech1 = space->machine().driver_data<vtech1_state>();
363	371	int drive;
364	372
365	373	switch (offset)
366	374	{
367	375	case 0: /* latch (write-only) */
368	376	drive = (data & 0x10) ? 0 : (data & 0x80) ? 1 : -1;
369		if (drive != vtech1->m_drive)
	377	if (drive != m_drive)
370	378	{
371		vtech1->m_drive = drive;
372		if (vtech1->m_drive >= 0)
373		vtech1_get_track(space->machine());
	379	m_drive = drive;
	380	if (m_drive >= 0)
	381	vtech1_get_track(machine());
374	382	}
375		if (vtech1->m_drive >= 0)
	383	if (m_drive >= 0)
376	384	{
377		if ((PHI0(data) && !(PHI1(data) || PHI2(data) || PHI3(data)) && PHI1(vtech1->m_fdc_latch)) ||
378		(PHI1(data) && !(PHI0(data) || PHI2(data) || PHI3(data)) && PHI2(vtech1->m_fdc_latch)) ||
379		(PHI2(data) && !(PHI0(data) || PHI1(data) || PHI3(data)) && PHI3(vtech1->m_fdc_latch)) ||
380		(PHI3(data) && !(PHI0(data) || PHI1(data) || PHI2(data)) && PHI0(vtech1->m_fdc_latch)))
	385	if ((PHI0(data) && !(PHI1(data) || PHI2(data) || PHI3(data)) && PHI1(m_fdc_latch)) ||
	386	(PHI1(data) && !(PHI0(data) || PHI2(data) || PHI3(data)) && PHI2(m_fdc_latch)) ||
	387	(PHI2(data) && !(PHI0(data) || PHI1(data) || PHI3(data)) && PHI3(m_fdc_latch)) ||
	388	(PHI3(data) && !(PHI0(data) || PHI1(data) || PHI2(data)) && PHI0(m_fdc_latch)))
381	389	{
382		if (vtech1->m_fdc_track_x2[vtech1->m_drive] > 0)
383		vtech1->m_fdc_track_x2[vtech1->m_drive]--;
	390	if (m_fdc_track_x2[m_drive] > 0)
	391	m_fdc_track_x2[m_drive]--;
384	392	if (LOG_VTECH1_FDC)
385		logerror("vtech1_fdc_w(%d) $%02X drive %d: stepout track #%2d.%d\n", offset, data, vtech1->m_drive, vtech1->m_fdc_track_x2[vtech1->m_drive]/2,5*(vtech1->m_fdc_track_x2[vtech1->m_drive]&1));
386		if ((vtech1->m_fdc_track_x2[vtech1->m_drive] & 1) == 0)
387		vtech1_get_track(space->machine());
	393	logerror("vtech1_fdc_w(%d) $%02X drive %d: stepout track #%2d.%d\n", offset, data, m_drive, m_fdc_track_x2[m_drive]/2,5*(m_fdc_track_x2[m_drive]&1));
	394	if ((m_fdc_track_x2[m_drive] & 1) == 0)
	395	vtech1_get_track(machine());
388	396	}
389	397	else
390		if ((PHI0(data) && !(PHI1(data) || PHI2(data) || PHI3(data)) && PHI3(vtech1->m_fdc_latch)) ||
391		(PHI1(data) && !(PHI0(data) || PHI2(data) || PHI3(data)) && PHI0(vtech1->m_fdc_latch)) ||
392		(PHI2(data) && !(PHI0(data) || PHI1(data) || PHI3(data)) && PHI1(vtech1->m_fdc_latch)) ||
393		(PHI3(data) && !(PHI0(data) || PHI1(data) || PHI2(data)) && PHI2(vtech1->m_fdc_latch)))
	398	if ((PHI0(data) && !(PHI1(data) || PHI2(data) || PHI3(data)) && PHI3(m_fdc_latch)) ||
	399	(PHI1(data) && !(PHI0(data) || PHI2(data) || PHI3(data)) && PHI0(m_fdc_latch)) ||
	400	(PHI2(data) && !(PHI0(data) || PHI1(data) || PHI3(data)) && PHI1(m_fdc_latch)) ||
	401	(PHI3(data) && !(PHI0(data) || PHI1(data) || PHI2(data)) && PHI2(m_fdc_latch)))
394	402	{
395		if (vtech1->m_fdc_track_x2[vtech1->m_drive] < 2*40)
396		vtech1->m_fdc_track_x2[vtech1->m_drive]++;
	403	if (m_fdc_track_x2[m_drive] < 2*40)
	404	m_fdc_track_x2[m_drive]++;
397	405	if (LOG_VTECH1_FDC)
398		logerror("vtech1_fdc_w(%d) $%02X drive %d: stepin track #%2d.%d\n", offset, data, vtech1->m_drive, vtech1->m_fdc_track_x2[vtech1->m_drive]/2,5*(vtech1->m_fdc_track_x2[vtech1->m_drive]&1));
399		if ((vtech1->m_fdc_track_x2[vtech1->m_drive] & 1) == 0)
400		vtech1_get_track(space->machine());
	406	logerror("vtech1_fdc_w(%d) $%02X drive %d: stepin track #%2d.%d\n", offset, data, m_drive, m_fdc_track_x2[m_drive]/2,5*(m_fdc_track_x2[m_drive]&1));
	407	if ((m_fdc_track_x2[m_drive] & 1) == 0)
	408	vtech1_get_track(machine());
401	409	}
402	410	if ((data & 0x40) == 0)
403	411	{
404		vtech1->m_data <<= 1;
405		if ((vtech1->m_fdc_latch ^ data) & 0x20)
406		vtech1->m_data |= 1;
407		if ((vtech1->m_fdc_edge ^= 1) == 0)
	412	m_data <<= 1;
	413	if ((m_fdc_latch ^ data) & 0x20)
	414	m_data |= 1;
	415	if ((m_fdc_edge ^= 1) == 0)
408	416	{
409		vtech1->m_fdc_bits--;
	417	m_fdc_bits--;
410	418
411		if (vtech1->m_fdc_bits == 0)
	419	if (m_fdc_bits == 0)
412	420	{
413	421	UINT8 value = 0;
414		vtech1->m_data &= 0xffff;
415		if (vtech1->m_data & 0x4000 ) value |= 0x80;
416		if (vtech1->m_data & 0x1000 ) value |= 0x40;
417		if (vtech1->m_data & 0x0400 ) value |= 0x20;
418		if (vtech1->m_data & 0x0100 ) value |= 0x10;
419		if (vtech1->m_data & 0x0040 ) value |= 0x08;
420		if (vtech1->m_data & 0x0010 ) value |= 0x04;
421		if (vtech1->m_data & 0x0004 ) value |= 0x02;
422		if (vtech1->m_data & 0x0001 ) value |= 0x01;
	422	m_data &= 0xffff;
	423	if (m_data & 0x4000 ) value |= 0x80;
	424	if (m_data & 0x1000 ) value |= 0x40;
	425	if (m_data & 0x0400 ) value |= 0x20;
	426	if (m_data & 0x0100 ) value |= 0x10;
	427	if (m_data & 0x0040 ) value |= 0x08;
	428	if (m_data & 0x0010 ) value |= 0x04;
	429	if (m_data & 0x0004 ) value |= 0x02;
	430	if (m_data & 0x0001 ) value |= 0x01;
423	431	if (LOG_VTECH1_FDC)
424		logerror("vtech1_fdc_w(%d) data($%04X) $%02X <- $%02X ($%04X)\n", offset, vtech1->m_fdc_offs, vtech1->m_fdc_data[vtech1->m_fdc_offs], value, vtech1->m_data);
425		vtech1->m_fdc_data[vtech1->m_fdc_offs] = value;
426		vtech1->m_fdc_offs = (vtech1->m_fdc_offs + 1) % TRKSIZE_FM;
427		vtech1->m_fdc_write++;
428		vtech1->m_fdc_bits = 8;
	432	logerror("vtech1_fdc_w(%d) data($%04X) $%02X <- $%02X ($%04X)\n", offset, m_fdc_offs, m_fdc_data[m_fdc_offs], value, m_data);
	433	m_fdc_data[m_fdc_offs] = value;
	434	m_fdc_offs = (m_fdc_offs + 1) % TRKSIZE_FM;
	435	m_fdc_write++;
	436	m_fdc_bits = 8;
429	437	}
430	438	}
431	439	}
432	440	/* change of write signal? */
433		if ((vtech1->m_fdc_latch ^ data) & 0x40)
	441	if ((m_fdc_latch ^ data) & 0x40)
434	442	{
435	443	/* falling edge? */
436		if (vtech1->m_fdc_latch & 0x40)
	444	if (m_fdc_latch & 0x40)
437	445	{
438		vtech1->m_fdc_start = vtech1->m_fdc_offs;
439		vtech1->m_fdc_edge = 0;
	446	m_fdc_start = m_fdc_offs;
	447	m_fdc_edge = 0;
440	448	}
441	449	else
442	450	{
443	451	/* data written to track before? */
444		if (vtech1->m_fdc_write)
445		vtech1_put_track(space->machine());
	452	if (m_fdc_write)
	453	vtech1_put_track(machine());
446	454	}
447		vtech1->m_fdc_bits = 8;
448		vtech1->m_fdc_write = 0;
	455	m_fdc_bits = 8;
	456	m_fdc_write = 0;
449	457	}
450	458	}
451		vtech1->m_fdc_latch = data;
	459	m_fdc_latch = data;
452	460	break;
453	461	}
454	462	}
r14844	r14845
489	497	RS232 SERIAL
490	498	***************************************************************************/
491	499
492		static READ8_HANDLER( vtech1_serial_r )
	500	READ8_MEMBER(vtech1_state::vtech1_serial_r)
493	501	{
494	502	logerror("vtech1_serial_r offset $%02x\n", offset);
495	503	return 0xff;
496	504	}
497	505
498		static WRITE8_HANDLER( vtech1_serial_w )
	506	WRITE8_MEMBER(vtech1_state::vtech1_serial_w)
499	507	{
500	508	logerror("vtech1_serial_w $%02x, offset %02x\n", data, offset);
501	509	}
r14844	r14845
505	513	INPUTS
506	514	***************************************************************************/
507	515
508		static READ8_HANDLER( vtech1_lightpen_r )
	516	READ8_MEMBER(vtech1_state::vtech1_lightpen_r)
509	517	{
510	518	logerror("vtech1_lightpen_r(%d)\n", offset);
511	519	return 0xff;
512	520	}
513	521
514		static READ8_HANDLER( vtech1_joystick_r )
	522	READ8_MEMBER(vtech1_state::vtech1_joystick_r)
515	523	{
516	524	int result = 0xff;
517	525
518		if (!BIT(offset, 0)) result &= input_port_read(space->machine(), "joystick_0");
519		if (!BIT(offset, 1)) result &= input_port_read(space->machine(), "joystick_0_arm");
520		if (!BIT(offset, 2)) result &= input_port_read(space->machine(), "joystick_1");
521		if (!BIT(offset, 3)) result &= input_port_read(space->machine(), "joystick_1_arm");
	526	if (!BIT(offset, 0)) result &= input_port_read(machine(), "joystick_0");
	527	if (!BIT(offset, 1)) result &= input_port_read(machine(), "joystick_0_arm");
	528	if (!BIT(offset, 2)) result &= input_port_read(machine(), "joystick_1");
	529	if (!BIT(offset, 3)) result &= input_port_read(machine(), "joystick_1_arm");
522	530
523	531	return result;
524	532	}
525	533
526		static READ8_HANDLER( vtech1_keyboard_r )
	534	READ8_MEMBER(vtech1_state::vtech1_keyboard_r)
527	535	{
528		vtech1_state *vtech1 = space->machine().driver_data<vtech1_state>();
529	536	UINT8 result = 0x3f;
530	537
531	538	/* bit 0 to 5, keyboard input */
532		if (!BIT(offset, 0)) result &= input_port_read(space->machine(), "keyboard_0");
533		if (!BIT(offset, 1)) result &= input_port_read(space->machine(), "keyboard_1");
534		if (!BIT(offset, 2)) result &= input_port_read(space->machine(), "keyboard_2");
535		if (!BIT(offset, 3)) result &= input_port_read(space->machine(), "keyboard_3");
536		if (!BIT(offset, 4)) result &= input_port_read(space->machine(), "keyboard_4");
537		if (!BIT(offset, 5)) result &= input_port_read(space->machine(), "keyboard_5");
538		if (!BIT(offset, 6)) result &= input_port_read(space->machine(), "keyboard_6");
539		if (!BIT(offset, 7)) result &= input_port_read(space->machine(), "keyboard_7");
	539	if (!BIT(offset, 0)) result &= input_port_read(machine(), "keyboard_0");
	540	if (!BIT(offset, 1)) result &= input_port_read(machine(), "keyboard_1");
	541	if (!BIT(offset, 2)) result &= input_port_read(machine(), "keyboard_2");
	542	if (!BIT(offset, 3)) result &= input_port_read(machine(), "keyboard_3");
	543	if (!BIT(offset, 4)) result &= input_port_read(machine(), "keyboard_4");
	544	if (!BIT(offset, 5)) result &= input_port_read(machine(), "keyboard_5");
	545	if (!BIT(offset, 6)) result &= input_port_read(machine(), "keyboard_6");
	546	if (!BIT(offset, 7)) result &= input_port_read(machine(), "keyboard_7");
540	547
541	548	/* bit 6, cassette input */
542		result |= ((vtech1->m_cassette->input()) > 0 ? 1 : 0) << 6;
	549	result |= ((m_cassette->input()) > 0 ? 1 : 0) << 6;
543	550
544	551	/* bit 7, field sync */
545		result |= vtech1->m_mc6847->fs_r() << 7;
	552	result |= m_mc6847->fs_r() << 7;
546	553
547	554	return result;
548	555	}
r14844	r14845
552	559	I/O LATCH
553	560	***************************************************************************/
554	561
555		static WRITE8_HANDLER( vtech1_latch_w )
	562	WRITE8_MEMBER(vtech1_state::vtech1_latch_w)
556	563	{
557		vtech1_state *vtech1 = space->machine().driver_data<vtech1_state>();
558	564
559	565	if (LOG_VTECH1_LATCH)
560	566	logerror("vtech1_latch_w $%02X\n", data);
561	567
562	568	/* bit 1, SHRG mod (if installed) */
563		if (vtech1->m_videoram_size == 0x2000)
	569	if (m_videoram_size == 0x2000)
564	570	{
565		vtech1->m_mc6847->gm0_w(BIT(data, 1));
566		vtech1->m_mc6847->gm2_w(BIT(data, 1));
	571	m_mc6847->gm0_w(BIT(data, 1));
	572	m_mc6847->gm2_w(BIT(data, 1));
567	573	}
568	574
569	575	/* bit 2, cassette out */
570		vtech1->m_cassette->output( BIT(data, 2) ? +1.0 : -1.0);
	576	m_cassette->output( BIT(data, 2) ? +1.0 : -1.0);
571	577
572	578	/* bit 3 and 4, vdc mode control lines */
573		vtech1->m_mc6847->ag_w(BIT(data, 3));
574		vtech1->m_mc6847->css_w(BIT(data, 4));
	579	m_mc6847->ag_w(BIT(data, 3));
	580	m_mc6847->css_w(BIT(data, 4));
575	581
576	582	/* bit 0 and 5, speaker */
577		speaker_level_w(vtech1->m_speaker, (BIT(data, 5) << 1) | BIT(data, 0));
	583	speaker_level_w(m_speaker, (BIT(data, 5) << 1) | BIT(data, 0));
578	584	}
579	585
580	586
r14844	r14845
582	588	MEMORY BANKING
583	589	***************************************************************************/
584	590
585		static WRITE8_HANDLER( vtech1_memory_bank_w )
	591	WRITE8_MEMBER(vtech1_state::vtech1_memory_bank_w)
586	592	{
587		vtech1_state *vtech1 = space->machine().driver_data<vtech1_state>();
588	593
589	594	logerror("vtech1_memory_bank_w $%02X\n", data);
590	595
591	596	if (data >= 1)
592		if ((data <= 3 && vtech1->m_ram_size == 66*1024) || (vtech1->m_ram_size == 4098*1024))
593		memory_set_bank(space->machine(), "bank3", data - 1);
	597	if ((data <= 3 && m_ram_size == 66*1024) || (m_ram_size == 4098*1024))
	598	memory_set_bank(machine(), "bank3", data - 1);
594	599	}
595	600
596		static WRITE8_HANDLER( vtech1_video_bank_w )
	601	WRITE8_MEMBER(vtech1_state::vtech1_video_bank_w)
597	602	{
598	603	logerror("vtech1_video_bank_w $%02X\n", data);
599		memory_set_bank(space->machine(), "bank4", data & 0x03);
	604	memory_set_bank(machine(), "bank4", data & 0x03);
600	605	}
601	606
602	607
r14844	r14845
697	702	AM_RANGE(0x0000, 0x3fff) AM_ROM   /* basic rom */
698	703	AM_RANGE(0x4000, 0x5fff) AM_ROM   /* dos rom or other catridges */
699	704	AM_RANGE(0x6000, 0x67ff) AM_ROM   /* reserved for cartridges */
700		AM_RANGE(0x6800, 0x6fff) AM_READWRITE_LEGACY(vtech1_keyboard_r, vtech1_latch_w)
	705	AM_RANGE(0x6800, 0x6fff) AM_READWRITE(vtech1_keyboard_r, vtech1_latch_w)
701	706	AM_RANGE(0x7000, 0x77ff) AM_RAM AM_BASE(m_videoram) /* (6847) */
702	707	AM_RANGE(0x7800, 0x7fff) AM_RAMBANK("bank1") /* 2k user ram */
703	708	AM_RANGE(0x8000, 0xbfff) AM_NOP /* 16k ram expansion */
r14844	r14845
708	713	AM_RANGE(0x0000, 0x3fff) AM_ROM   /* basic rom */
709	714	AM_RANGE(0x4000, 0x5fff) AM_ROM   /* dos rom or other catridges */
710	715	AM_RANGE(0x6000, 0x67ff) AM_ROM   /* reserved for cartridges */
711		AM_RANGE(0x6800, 0x6fff) AM_READWRITE_LEGACY(vtech1_keyboard_r, vtech1_latch_w)
	716	AM_RANGE(0x6800, 0x6fff) AM_READWRITE(vtech1_keyboard_r, vtech1_latch_w)
712	717	AM_RANGE(0x7000, 0x77ff) AM_RAM AM_BASE(m_videoram) /* U7 (6847) */
713	718	AM_RANGE(0x7800, 0x8fff) AM_RAMBANK("bank1") /* 6k user ram */
714	719	AM_RANGE(0x9000, 0xcfff) AM_NOP /* 16k ram expansion */
r14844	r14845
719	724	AM_RANGE(0x0000, 0x3fff) AM_ROM   /* basic rom */
720	725	AM_RANGE(0x4000, 0x5fff) AM_ROM   /* dos rom or other catridges */
721	726	AM_RANGE(0x6000, 0x67ff) AM_ROM   /* reserved for cartridges */
722		AM_RANGE(0x6800, 0x6fff) AM_READWRITE_LEGACY(vtech1_keyboard_r, vtech1_latch_w)
	727	AM_RANGE(0x6800, 0x6fff) AM_READWRITE(vtech1_keyboard_r, vtech1_latch_w)
723	728	AM_RANGE(0x7000, 0x77ff) AM_RAM AM_BASE(m_videoram) /* (6847) */
724	729	AM_RANGE(0x7800, 0xb7ff) AM_RAMBANK("bank1") /* 16k user ram */
725	730	AM_RANGE(0xb800, 0xf7ff) AM_NOP /* 16k ram expansion */
r14844	r14845
731	736	AM_RANGE(0x00, 0x00) AM_DEVREAD_LEGACY("centronics", vtech1_printer_r)
732	737	AM_RANGE(0x0d, 0x0d) AM_DEVWRITE_LEGACY("centronics", vtech1_strobe_w)
733	738	AM_RANGE(0x0e, 0x0e) AM_DEVWRITE("centronics", centronics_device, write)
734		AM_RANGE(0x10, 0x1f) AM_READWRITE_LEGACY(vtech1_fdc_r, vtech1_fdc_w)
735		AM_RANGE(0x20, 0x2f) AM_READ_LEGACY(vtech1_joystick_r)
736		AM_RANGE(0x30, 0x3f) AM_READWRITE_LEGACY(vtech1_serial_r, vtech1_serial_w)
737		AM_RANGE(0x40, 0x4f) AM_READ_LEGACY(vtech1_lightpen_r)
738		AM_RANGE(0x70, 0x7f) AM_WRITE_LEGACY(vtech1_memory_bank_w)
	739	AM_RANGE(0x10, 0x1f) AM_READWRITE(vtech1_fdc_r, vtech1_fdc_w)
	740	AM_RANGE(0x20, 0x2f) AM_READ(vtech1_joystick_r)
	741	AM_RANGE(0x30, 0x3f) AM_READWRITE(vtech1_serial_r, vtech1_serial_w)
	742	AM_RANGE(0x40, 0x4f) AM_READ(vtech1_lightpen_r)
	743	AM_RANGE(0x70, 0x7f) AM_WRITE(vtech1_memory_bank_w)
739	744	ADDRESS_MAP_END
740	745
741	746	static ADDRESS_MAP_START( vtech1_shrg_io, AS_IO, 8, vtech1_state )
742	747	AM_IMPORT_FROM(vtech1_io)
743		AM_RANGE(0xd0, 0xdf) AM_WRITE_LEGACY(vtech1_video_bank_w)
	748	AM_RANGE(0xd0, 0xdf) AM_WRITE(vtech1_video_bank_w)
744	749	ADDRESS_MAP_END
745	750
746	751

src/mess/drivers/atm.c

r14844	r14845
10	10	#include "machine/ram.h"
11	11
12	12
13		class atm_state : public driver_device
	13	class atm_state : public spectrum_state
14	14	{
15	15	public:
16	16	atm_state(const machine_config &mconfig, device_type type, const char *tag)
17		: driver_device(mconfig, type, tag) { }
	17	: spectrum_state(mconfig, type, tag) { }
18	18
	19	DECLARE_WRITE8_MEMBER(atm_port_7ffd_w);
19	20	};
20	21
21	22
r14844	r14845
77	78	memory_set_bankptr(machine, "bank1", machine.region("maincpu")->base() + 0x010000 + (state->m_ROMSelection<<14));
78	79	}
79	80
80		static WRITE8_HANDLER(atm_port_7ffd_w)
	81	WRITE8_MEMBER(atm_state::atm_port_7ffd_w)
81	82	{
82		spectrum_state *state = space->machine().driver_data<spectrum_state>();
83	83
84	84	/* disable paging */
85		if (state->m_port_7ffd_data & 0x20)
	85	if (m_port_7ffd_data & 0x20)
86	86	return;
87	87
88	88	/* store new state */
89		state->m_port_7ffd_data = data;
	89	m_port_7ffd_data = data;
90	90
91	91	/* update memory */
92		atm_update_memory(space->machine());
	92	atm_update_memory(machine());
93	93	}
94	94
95		static ADDRESS_MAP_START (atm_io, AS_IO, 8, spectrum_state )
	95	static ADDRESS_MAP_START (atm_io, AS_IO, 8, atm_state )
96	96	ADDRESS_MAP_UNMAP_HIGH
97	97	AM_RANGE(0x001f, 0x001f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_status_r,betadisk_command_w) AM_MIRROR(0xff00)
98	98	AM_RANGE(0x003f, 0x003f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_track_r,betadisk_track_w) AM_MIRROR(0xff00)
r14844	r14845
100	100	AM_RANGE(0x007f, 0x007f) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_data_r,betadisk_data_w) AM_MIRROR(0xff00)
101	101	AM_RANGE(0x00fe, 0x00fe) AM_READWRITE_LEGACY(spectrum_port_fe_r,spectrum_port_fe_w) AM_MIRROR(0xff00) AM_MASK(0xffff)
102	102	AM_RANGE(0x00ff, 0x00ff) AM_DEVREADWRITE_LEGACY(BETA_DISK_TAG, betadisk_state_r, betadisk_param_w) AM_MIRROR(0xff00)
103		AM_RANGE(0x4000, 0x4000) AM_WRITE_LEGACY(atm_port_7ffd_w)  AM_MIRROR(0x3ffd)
	103	AM_RANGE(0x4000, 0x4000) AM_WRITE(atm_port_7ffd_w)  AM_MIRROR(0x3ffd)
104	104	AM_RANGE(0x8000, 0x8000) AM_DEVWRITE_LEGACY("ay8912", ay8910_data_w) AM_MIRROR(0x3ffd)
105	105	AM_RANGE(0xc000, 0xc000) AM_DEVREADWRITE_LEGACY("ay8912", ay8910_r, ay8910_address_w) AM_MIRROR(0x3ffd)
106	106	ADDRESS_MAP_END

src/mess/drivers/pockstat.c

r14844	r14845
102	102	UINT32 m_lcd_control;
103	103	INT32 m_ps_flash_write_enable_count;
104	104	INT32 m_ps_flash_write_count;
	105	DECLARE_READ32_MEMBER(ps_ftlb_r);
	106	DECLARE_WRITE32_MEMBER(ps_ftlb_w);
	107	DECLARE_READ32_MEMBER(ps_intc_r);
	108	DECLARE_WRITE32_MEMBER(ps_intc_w);
	109	DECLARE_READ32_MEMBER(ps_timer_r);
	110	DECLARE_WRITE32_MEMBER(ps_timer_w);
	111	DECLARE_READ32_MEMBER(ps_clock_r);
	112	DECLARE_WRITE32_MEMBER(ps_clock_w);
	113	DECLARE_READ32_MEMBER(ps_rtc_r);
	114	DECLARE_WRITE32_MEMBER(ps_rtc_w);
	115	DECLARE_READ32_MEMBER(ps_lcd_r);
	116	DECLARE_WRITE32_MEMBER(ps_lcd_w);
	117	DECLARE_READ32_MEMBER(ps_rombank_r);
	118	DECLARE_WRITE32_MEMBER(ps_flash_w);
	119	DECLARE_READ32_MEMBER(ps_audio_r);
	120	DECLARE_WRITE32_MEMBER(ps_audio_w);
	121	DECLARE_WRITE32_MEMBER(ps_dac_w);
105	122	};
106	123
107	124
r14844	r14845
150	167
151	168
152	169	// Flash TLB
153		static READ32_HANDLER( ps_ftlb_r );
154		static WRITE32_HANDLER( ps_ftlb_w );
155	170
	171
	172
156	173	// Interrupt Controller
157	174	static UINT32 ps_intc_get_interrupt_line(running_machine &machine, UINT32 line);
158	175	static void ps_intc_set_interrupt_line(running_machine &machine, UINT32 line, int state);
159		static READ32_HANDLER( ps_intc_r );
160		static WRITE32_HANDLER( ps_intc_w );
161	176
	177
	178
162	179	// Timers
163	180	static TIMER_CALLBACK( timer_tick );
164	181	static void ps_timer_start(running_machine &machine, int index);
165		static READ32_HANDLER( ps_timer_r );
166		static WRITE32_HANDLER( ps_timer_w );
167	182
	183
	184
168	185	// Clock
169		static READ32_HANDLER( ps_clock_r );
170		static WRITE32_HANDLER( ps_clock_w );
171	186
	187
	188
172	189	// RTC
173	190	static TIMER_CALLBACK( rtc_tick );
174		static READ32_HANDLER( ps_rtc_r );
175		static WRITE32_HANDLER( ps_rtc_w );
176	191
	192
	193
177	194	#define PS_INT_BTN_ACTION      0x00000001 // "Action button"
178	195	#define PS_INT_BTN_RIGHT      0x00000002 // "Right button"
179	196	#define PS_INT_BTN_LEFT         0x00000004 // "Left button"
r14844	r14845
192	209	#define PS_INT_FIQ_MASK         0x00002040
193	210	#define PS_INT_STATUS_MASK      0x0000021f
194	211
195		static READ32_HANDLER( ps_ftlb_r )
	212	READ32_MEMBER(pockstat_state::ps_ftlb_r)
196	213	{
197		pockstat_state *state = space->machine().driver_data<pockstat_state>();
198	214	switch(offset)
199	215	{
200	216	case 0x0000/4:
201		verboselog(space->machine(), 0, "ps_ftlb_r: FlashROM TLB Control = %08x & %08x\n", state->m_ftlb_regs.control, mem_mask );
202		return state->m_ftlb_regs.control | 1; // ???
	217	verboselog(machine(), 0, "ps_ftlb_r: FlashROM TLB Control = %08x & %08x\n", m_ftlb_regs.control, mem_mask );
	218	return m_ftlb_regs.control | 1; // ???
203	219	case 0x0004/4:
204		verboselog(space->machine(), 0, "ps_ftlb_r: Unknown (F_STAT) = %08x & %08x\n", state->m_ftlb_regs.stat, mem_mask );
205		return state->m_ftlb_regs.stat;
	220	verboselog(machine(), 0, "ps_ftlb_r: Unknown (F_STAT) = %08x & %08x\n", m_ftlb_regs.stat, mem_mask );
	221	return m_ftlb_regs.stat;
206	222	case 0x0008/4:
207		verboselog(space->machine(), 0, "ps_ftlb_r: FlashROM TLB Valid Tag = %08x & %08x\n", state->m_ftlb_regs.valid, mem_mask );
208		return state->m_ftlb_regs.valid;
	223	verboselog(machine(), 0, "ps_ftlb_r: FlashROM TLB Valid Tag = %08x & %08x\n", m_ftlb_regs.valid, mem_mask );
	224	return m_ftlb_regs.valid;
209	225	case 0x000c/4:
210		verboselog(space->machine(), 0, "ps_ftlb_r: Unknown (F_WAIT1) = %08x & %08x\n", state->m_ftlb_regs.wait1, mem_mask );
211		return state->m_ftlb_regs.wait1;
	226	verboselog(machine(), 0, "ps_ftlb_r: Unknown (F_WAIT1) = %08x & %08x\n", m_ftlb_regs.wait1, mem_mask );
	227	return m_ftlb_regs.wait1;
212	228	case 0x0010/4:
213		verboselog(space->machine(), 0, "ps_ftlb_r: Unknown (F_WAIT2) = %08x & %08x\n", state->m_ftlb_regs.wait2 | 0x04, mem_mask );
214		return state->m_ftlb_regs.wait2 | 0x04;
	229	verboselog(machine(), 0, "ps_ftlb_r: Unknown (F_WAIT2) = %08x & %08x\n", m_ftlb_regs.wait2 | 0x04, mem_mask );
	230	return m_ftlb_regs.wait2 | 0x04;
215	231	case 0x0100/4:
216	232	case 0x0104/4:
217	233	case 0x0108/4:
r14844	r14845
228	244	case 0x0134/4:
229	245	case 0x0138/4:
230	246	case 0x013c/4:
231		verboselog(space->machine(), 0, "ps_ftlb_r: FlashROM TLB Entry %d = %08x & %08x\n", offset - 0x100/4, state->m_ftlb_regs.entry[offset - 0x100/4], mem_mask );
232		return state->m_ftlb_regs.entry[offset - 0x100/4];
	247	verboselog(machine(), 0, "ps_ftlb_r: FlashROM TLB Entry %d = %08x & %08x\n", offset - 0x100/4, m_ftlb_regs.entry[offset - 0x100/4], mem_mask );
	248	return m_ftlb_regs.entry[offset - 0x100/4];
233	249	case 0x0300/4:
234		verboselog(space->machine(), 0, "ps_ftlb_r: Unknown (F_SN) = %08x & %08x\n", state->m_ftlb_regs.serial, mem_mask );
235		return state->m_ftlb_regs.serial;
	250	verboselog(machine(), 0, "ps_ftlb_r: Unknown (F_SN) = %08x & %08x\n", m_ftlb_regs.serial, mem_mask );
	251	return m_ftlb_regs.serial;
236	252	default:
237		verboselog(space->machine(), 0, "ps_ftlb_r: Unknown Register %08x & %08x\n", 0x06000000 + (offset << 2), mem_mask );
	253	verboselog(machine(), 0, "ps_ftlb_r: Unknown Register %08x & %08x\n", 0x06000000 + (offset << 2), mem_mask );
238	254	break;
239	255	}
240	256	return 0;
241	257	}
242	258
243		static WRITE32_HANDLER( ps_ftlb_w )
	259	WRITE32_MEMBER(pockstat_state::ps_ftlb_w)
244	260	{
245		pockstat_state *state = space->machine().driver_data<pockstat_state>();
246	261	switch(offset)
247	262	{
248	263	case 0x0000/4:
249		verboselog(space->machine(), 0, "ps_ftlb_w: FlashROM TLB Control = %08x & %08x\n", data, mem_mask );
250		COMBINE_DATA(&state->m_ftlb_regs.control);
	264	verboselog(machine(), 0, "ps_ftlb_w: FlashROM TLB Control = %08x & %08x\n", data, mem_mask );
	265	COMBINE_DATA(&m_ftlb_regs.control);
251	266	break;
252	267	case 0x0004/4:
253		verboselog(space->machine(), 0, "ps_ftlb_w: Unknown (F_STAT) = %08x & %08x\n", data, mem_mask );
254		COMBINE_DATA(&state->m_ftlb_regs.stat);
	268	verboselog(machine(), 0, "ps_ftlb_w: Unknown (F_STAT) = %08x & %08x\n", data, mem_mask );
	269	COMBINE_DATA(&m_ftlb_regs.stat);
255	270	break;
256	271	case 0x0008/4:
257		verboselog(space->machine(), 0, "ps_ftlb_w: FlashROM TLB Valid Tag = %08x & %08x\n", data, mem_mask );
258		COMBINE_DATA(&state->m_ftlb_regs.valid);
	272	verboselog(machine(), 0, "ps_ftlb_w: FlashROM TLB Valid Tag = %08x & %08x\n", data, mem_mask );
	273	COMBINE_DATA(&m_ftlb_regs.valid);
259	274	break;
260	275	case 0x000c/4:
261		verboselog(space->machine(), 0, "ps_ftlb_w: Unknown (F_WAIT1) = %08x & %08x\n", data, mem_mask );
262		COMBINE_DATA(&state->m_ftlb_regs.wait1);
	276	verboselog(machine(), 0, "ps_ftlb_w: Unknown (F_WAIT1) = %08x & %08x\n", data, mem_mask );
	277	COMBINE_DATA(&m_ftlb_regs.wait1);
263	278	break;
264	279	case 0x0010/4:
265		verboselog(space->machine(), 0, "ps_ftlb_w: Unknown (F_WAIT2) = %08x & %08x\n", data, mem_mask );
266		COMBINE_DATA(&state->m_ftlb_regs.wait2);
	280	verboselog(machine(), 0, "ps_ftlb_w: Unknown (F_WAIT2) = %08x & %08x\n", data, mem_mask );
	281	COMBINE_DATA(&m_ftlb_regs.wait2);
267	282	break;
268	283	case 0x0100/4:
269	284	case 0x0104/4:
r14844	r14845
281	296	case 0x0134/4:
282	297	case 0x0138/4:
283	298	case 0x013c/4:
284		verboselog(space->machine(), 0, "ps_ftlb_w: FlashROM TLB Entry %d = %08x & %08x\n", offset - 0x100/4, data, mem_mask );
285		COMBINE_DATA(&state->m_ftlb_regs.entry[offset - 0x100/4]);
	299	verboselog(machine(), 0, "ps_ftlb_w: FlashROM TLB Entry %d = %08x & %08x\n", offset - 0x100/4, data, mem_mask );
	300	COMBINE_DATA(&m_ftlb_regs.entry[offset - 0x100/4]);
286	301	break;
287	302	case 0x0300/4:
288		verboselog(space->machine(), 0, "ps_ftlb_w: Unknown (F_SN) = %08x & %08x\n", data, mem_mask );
289		COMBINE_DATA(&state->m_ftlb_regs.serial);
	303	verboselog(machine(), 0, "ps_ftlb_w: Unknown (F_SN) = %08x & %08x\n", data, mem_mask );
	304	COMBINE_DATA(&m_ftlb_regs.serial);
290	305	break;
291	306	default:
292		verboselog(space->machine(), 0, "ps_ftlb_w: Unknown Register %08x = %08x & %08x\n", 0x06000000 + (offset << 2), data, mem_mask );
	307	verboselog(machine(), 0, "ps_ftlb_w: Unknown Register %08x = %08x & %08x\n", 0x06000000 + (offset << 2), data, mem_mask );
293	308	break;
294	309	}
295	310	}
r14844	r14845
337	352	}
338	353	}
339	354
340		static READ32_HANDLER( ps_intc_r )
	355	READ32_MEMBER(pockstat_state::ps_intc_r)
341	356	{
342		pockstat_state *state = space->machine().driver_data<pockstat_state>();
343	357	switch(offset)
344	358	{
345	359	case 0x0000/4:
346		verboselog(space->machine(), 0, "ps_intc_r: Held Interrupt = %08x & %08x\n", state->m_intc_regs.hold, mem_mask );
347		return state->m_intc_regs.hold;
	360	verboselog(machine(), 0, "ps_intc_r: Held Interrupt = %08x & %08x\n", m_intc_regs.hold, mem_mask );
	361	return m_intc_regs.hold;
348	362	case 0x0004/4:
349		verboselog(space->machine(), 0, "ps_intc_r: Interrupt Status = %08x & %08x\n", state->m_intc_regs.status, mem_mask );
350		return state->m_intc_regs.status;
	363	verboselog(machine(), 0, "ps_intc_r: Interrupt Status = %08x & %08x\n", m_intc_regs.status, mem_mask );
	364	return m_intc_regs.status;
351	365	case 0x0008/4:
352		verboselog(space->machine(), 0, "ps_intc_r: Interrupt Enable = %08x & %08x\n", state->m_intc_regs.enable, mem_mask );
353		return state->m_intc_regs.enable;
	366	verboselog(machine(), 0, "ps_intc_r: Interrupt Enable = %08x & %08x\n", m_intc_regs.enable, mem_mask );
	367	return m_intc_regs.enable;
354	368	case 0x000c/4:
355		verboselog(space->machine(), 0, "ps_intc_r: Interrupt Mask (Invalid Read) = %08x & %08x\n", 0, mem_mask );
	369	verboselog(machine(), 0, "ps_intc_r: Interrupt Mask (Invalid Read) = %08x & %08x\n", 0, mem_mask );
356	370	return 0;
357	371	case 0x0010/4:
358		verboselog(space->machine(), 0, "ps_intc_r: Interrupt Acknowledge (Invalid Read) = %08x & %08x\n", 0, mem_mask );
	372	verboselog(machine(), 0, "ps_intc_r: Interrupt Acknowledge (Invalid Read) = %08x & %08x\n", 0, mem_mask );
359	373	return 0;
360	374	default:
361		verboselog(space->machine(), 0, "ps_intc_r: Unknown Register %08x & %08x\n", 0x0a000000 + (offset << 2), mem_mask );
	375	verboselog(machine(), 0, "ps_intc_r: Unknown Register %08x & %08x\n", 0x0a000000 + (offset << 2), mem_mask );
362	376	break;
363	377	}
364	378	return 0;
365	379	}
366	380
367		static WRITE32_HANDLER( ps_intc_w )
	381	WRITE32_MEMBER(pockstat_state::ps_intc_w)
368	382	{
369		pockstat_state *state = space->machine().driver_data<pockstat_state>();
370	383	switch(offset)
371	384	{
372	385	case 0x0000/4:
373		verboselog(space->machine(), 0, "ps_intc_w: Held Interrupt (Invalid Write) = %08x & %08x\n", data, mem_mask );
	386	verboselog(machine(), 0, "ps_intc_w: Held Interrupt (Invalid Write) = %08x & %08x\n", data, mem_mask );
374	387	break;
375	388	case 0x0004/4:
376		verboselog(space->machine(), 0, "ps_intc_w: Interrupt Status (Invalid Write) = %08x & %08x\n", data, mem_mask );
	389	verboselog(machine(), 0, "ps_intc_w: Interrupt Status (Invalid Write) = %08x & %08x\n", data, mem_mask );
377	390	break;
378	391	case 0x0008/4:
379		verboselog(space->machine(), 0, "ps_intc_w: Interrupt Enable = %08x & %08x\n", data, mem_mask );
380		state->m_intc_regs.enable |= data;
381		//COMBINE_DATA(&state->m_intc_regs.enable);
382		//state->m_intc_regs.status &= state->m_intc_regs.enable;
383		//state->m_intc_regs.hold &= state->m_intc_regs.enable;
384		ps_intc_set_interrupt_line(space->machine(), 0, 0);
	392	verboselog(machine(), 0, "ps_intc_w: Interrupt Enable = %08x & %08x\n", data, mem_mask );
	393	m_intc_regs.enable |= data;
	394	//COMBINE_DATA(&m_intc_regs.enable);
	395	//m_intc_regs.status &= m_intc_regs.enable;
	396	//m_intc_regs.hold &= m_intc_regs.enable;
	397	ps_intc_set_interrupt_line(machine(), 0, 0);
385	398	break;
386	399	case 0x000c/4:
387		verboselog(space->machine(), 0, "ps_intc_w: Interrupt Mask = %08x & %08x\n", data, mem_mask );
388		state->m_intc_regs.enable &= ~data;
389		COMBINE_DATA(&state->m_intc_regs.mask);
390		//state->m_intc_regs.status &= state->m_intc_regs.enable;
391		//state->m_intc_regs.hold &= state->m_intc_regs.enable;
392		ps_intc_set_interrupt_line(space->machine(), 0, 0);
	400	verboselog(machine(), 0, "ps_intc_w: Interrupt Mask = %08x & %08x\n", data, mem_mask );
	401	m_intc_regs.enable &= ~data;
	402	COMBINE_DATA(&m_intc_regs.mask);
	403	//m_intc_regs.status &= m_intc_regs.enable;
	404	//m_intc_regs.hold &= m_intc_regs.enable;
	405	ps_intc_set_interrupt_line(machine(), 0, 0);
393	406	break;
394	407	case 0x0010/4:
395		verboselog(space->machine(), 0, "ps_intc_w: Interrupt Acknowledge = %08x & %08x\n", data, mem_mask );
396		state->m_intc_regs.hold &= ~data;
397		state->m_intc_regs.status &= ~data;
398		ps_intc_set_interrupt_line(space->machine(), 0, 0);
399		//COMBINE_DATA(&state->m_intc_regs.acknowledge);
	408	verboselog(machine(), 0, "ps_intc_w: Interrupt Acknowledge = %08x & %08x\n", data, mem_mask );
	409	m_intc_regs.hold &= ~data;
	410	m_intc_regs.status &= ~data;
	411	ps_intc_set_interrupt_line(machine(), 0, 0);
	412	//COMBINE_DATA(&m_intc_regs.acknowledge);
400	413	break;
401	414	default:
402		verboselog(space->machine(), 0, "ps_intc_w: Unknown Register %08x = %08x & %08x\n", 0x0a000000 + (offset << 2), data, mem_mask );
	415	verboselog(machine(), 0, "ps_intc_w: Unknown Register %08x = %08x & %08x\n", 0x0a000000 + (offset << 2), data, mem_mask );
403	416	break;
404	417	}
405	418	}
r14844	r14845
436	449	state->m_timer_regs.timer[index].timer->adjust(period, index);
437	450	}
438	451
439		static READ32_HANDLER( ps_timer_r )
	452	READ32_MEMBER(pockstat_state::ps_timer_r)
440	453	{
441		pockstat_state *state = space->machine().driver_data<pockstat_state>();
442	454	switch(offset)
443	455	{
444	456	case 0x0000/4:
445	457	case 0x0010/4:
446	458	case 0x0020/4:
447		verboselog(space->machine(), 0, "ps_timer_r: Timer %d Period = %08x & %08x\n", offset / (0x10/4), state->m_timer_regs.timer[offset / (0x10/4)].period, mem_mask );
448		return state->m_timer_regs.timer[offset / (0x10/4)].period;
	459	verboselog(machine(), 0, "ps_timer_r: Timer %d Period = %08x & %08x\n", offset / (0x10/4), m_timer_regs.timer[offset / (0x10/4)].period, mem_mask );
	460	return m_timer_regs.timer[offset / (0x10/4)].period;
449	461	case 0x0004/4:
450	462	case 0x0014/4:
451	463	case 0x0024/4:
452		verboselog(space->machine(), 0, "ps_timer_r: Timer %d Count = %08x & %08x\n", offset / (0x10/4), state->m_timer_regs.timer[offset / (0x10/4)].count, mem_mask );
453		if(state->m_timer_regs.timer[offset / (0x10/4)].control & 4)
	464	verboselog(machine(), 0, "ps_timer_r: Timer %d Count = %08x & %08x\n", offset / (0x10/4), m_timer_regs.timer[offset / (0x10/4)].count, mem_mask );
	465	if(m_timer_regs.timer[offset / (0x10/4)].control & 4)
454	466	{
455		state->m_timer_regs.timer[offset / (0x10/4)].count--;
456		if(state->m_timer_regs.timer[offset / (0x10/4)].count > state->m_timer_regs.timer[offset / (0x10/4)].period)
	467	m_timer_regs.timer[offset / (0x10/4)].count--;
	468	if(m_timer_regs.timer[offset / (0x10/4)].count > m_timer_regs.timer[offset / (0x10/4)].period)
457	469	{
458		state->m_timer_regs.timer[offset / (0x10/4)].count = state->m_timer_regs.timer[offset / (0x10/4)].period;
	470	m_timer_regs.timer[offset / (0x10/4)].count = m_timer_regs.timer[offset / (0x10/4)].period;
459	471	}
460		return --state->m_timer_regs.timer[offset / (0x10/4)].count;
	472	return --m_timer_regs.timer[offset / (0x10/4)].count;
461	473	}
462		return state->m_timer_regs.timer[offset / (0x10/4)].count;
	474	return m_timer_regs.timer[offset / (0x10/4)].count;
463	475	case 0x0008/4:
464	476	case 0x0018/4:
465	477	case 0x0028/4:
466		verboselog(space->machine(), 0, "ps_timer_r: Timer %d Control = %08x & %08x\n", offset / (0x10/4), state->m_timer_regs.timer[offset / (0x10/4)].control, mem_mask );
467		return state->m_timer_regs.timer[offset / (0x10/4)].control;
	478	verboselog(machine(), 0, "ps_timer_r: Timer %d Control = %08x & %08x\n", offset / (0x10/4), m_timer_regs.timer[offset / (0x10/4)].control, mem_mask );
	479	return m_timer_regs.timer[offset / (0x10/4)].control;
468	480	default:
469		verboselog(space->machine(), 0, "ps_timer_r: Unknown Register %08x & %08x\n", 0x0a800000 + (offset << 2), mem_mask );
	481	verboselog(machine(), 0, "ps_timer_r: Unknown Register %08x & %08x\n", 0x0a800000 + (offset << 2), mem_mask );
470	482	break;
471	483	}
472	484	return 0;
473	485	}
474	486
475		static WRITE32_HANDLER( ps_timer_w )
	487	WRITE32_MEMBER(pockstat_state::ps_timer_w)
476	488	{
477		pockstat_state *state = space->machine().driver_data<pockstat_state>();
478	489	switch(offset)
479	490	{
480	491	case 0x0000/4:
481	492	case 0x0010/4:
482	493	case 0x0020/4:
483		verboselog(space->machine(), 0, "ps_timer_w: Timer %d Period = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
484		COMBINE_DATA(&state->m_timer_regs.timer[offset / (0x10/4)].period);
	494	verboselog(machine(), 0, "ps_timer_w: Timer %d Period = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
	495	COMBINE_DATA(&m_timer_regs.timer[offset / (0x10/4)].period);
485	496	break;
486	497	case 0x0004/4:
487	498	case 0x0014/4:
488	499	case 0x0024/4:
489		verboselog(space->machine(), 0, "ps_timer_w: Timer %d Count = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
490		COMBINE_DATA(&state->m_timer_regs.timer[offset / (0x10/4)].count);
	500	verboselog(machine(), 0, "ps_timer_w: Timer %d Count = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
	501	COMBINE_DATA(&m_timer_regs.timer[offset / (0x10/4)].count);
491	502	break;
492	503	case 0x0008/4:
493	504	case 0x0018/4:
494	505	case 0x0028/4:
495		verboselog(space->machine(), 0, "ps_timer_w: Timer %d Control = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
496		COMBINE_DATA(&state->m_timer_regs.timer[offset / (0x10/4)].control);
497		if(state->m_timer_regs.timer[offset / (0x10/4)].control & 4)
	506	verboselog(machine(), 0, "ps_timer_w: Timer %d Control = %08x & %08x\n", offset / (0x10/4), data, mem_mask );
	507	COMBINE_DATA(&m_timer_regs.timer[offset / (0x10/4)].control);
	508	if(m_timer_regs.timer[offset / (0x10/4)].control & 4)
498	509	{
499		ps_timer_start(space->machine(), offset / (0x10/4));
	510	ps_timer_start(machine(), offset / (0x10/4));
500	511	}
501	512	else
502	513	{
503		state->m_timer_regs.timer[offset / (0x10/4)].timer->adjust(attotime::never, offset / (0x10/4));
	514	m_timer_regs.timer[offset / (0x10/4)].timer->adjust(attotime::never, offset / (0x10/4));
504	515	}
505	516	break;
506	517	default:
507		verboselog(space->machine(), 0, "ps_timer_w: Unknown Register %08x = %08x & %08x\n", 0x0a800000 + (offset << 2), data, mem_mask );
	518	verboselog(machine(), 0, "ps_timer_w: Unknown Register %08x = %08x & %08x\n", 0x0a800000 + (offset << 2), data, mem_mask );
508	519	break;
509	520	}
510	521	}
511	522
512		static READ32_HANDLER( ps_clock_r )
	523	READ32_MEMBER(pockstat_state::ps_clock_r)
513	524	{
514		pockstat_state *state = space->machine().driver_data<pockstat_state>();
515	525	switch(offset)
516	526	{
517	527	case 0x0000/4:
518		verboselog(space->machine(), 0, "ps_clock_r: Clock Mode = %08x & %08x\n", state->m_clock_regs.mode | 0x10, mem_mask );
519		return state->m_clock_regs.mode | PS_CLOCK_STEADY;
	528	verboselog(machine(), 0, "ps_clock_r: Clock Mode = %08x & %08x\n", m_clock_regs.mode | 0x10, mem_mask );
	529	return m_clock_regs.mode | PS_CLOCK_STEADY;
520	530	case 0x0004/4:
521		verboselog(space->machine(), 0, "ps_clock_r: Clock Control = %08x & %08x\n", state->m_clock_regs.control, mem_mask );
522		return state->m_clock_regs.control;
	531	verboselog(machine(), 0, "ps_clock_r: Clock Control = %08x & %08x\n", m_clock_regs.control, mem_mask );
	532	return m_clock_regs.control;
523	533	default:
524		verboselog(space->machine(), 0, "ps_clock_r: Unknown Register %08x & %08x\n", 0x0b000000 + (offset << 2), mem_mask );
	534	verboselog(machine(), 0, "ps_clock_r: Unknown Register %08x & %08x\n", 0x0b000000 + (offset << 2), mem_mask );
525	535	break;
526	536	}
527	537	return 0;
528	538	}
529	539
530		static WRITE32_HANDLER( ps_clock_w )
	540	WRITE32_MEMBER(pockstat_state::ps_clock_w)
531	541	{
532		pockstat_state *state = space->machine().driver_data<pockstat_state>();
533	542	switch(offset)
534	543	{
535	544	case 0x0000/4:
536		verboselog(space->machine(), 0, "ps_clock_w: Clock Mode = %08x & %08x\n", data, mem_mask );
537		COMBINE_DATA(&state->m_clock_regs.mode);
538		space->machine().device("maincpu")->set_unscaled_clock(CPU_FREQ[state->m_clock_regs.mode & 0x0f]);
	545	verboselog(machine(), 0, "ps_clock_w: Clock Mode = %08x & %08x\n", data, mem_mask );
	546	COMBINE_DATA(&m_clock_regs.mode);
	547	machine().device("maincpu")->set_unscaled_clock(CPU_FREQ[m_clock_regs.mode & 0x0f]);
539	548	break;
540	549	case 0x0004/4:
541		verboselog(space->machine(), 0, "ps_clock_w: Clock Control = %08x & %08x\n", data, mem_mask );
542		COMBINE_DATA(&state->m_clock_regs.control);
	550	verboselog(machine(), 0, "ps_clock_w: Clock Control = %08x & %08x\n", data, mem_mask );
	551	COMBINE_DATA(&m_clock_regs.control);
543	552	break;
544	553	default:
545		verboselog(space->machine(), 0, "ps_clock_w: Unknown Register %08x = %08x & %08x\n", 0x0b000000 + (offset << 2), data, mem_mask );
	554	verboselog(machine(), 0, "ps_clock_w: Unknown Register %08x = %08x & %08x\n", 0x0b000000 + (offset << 2), data, mem_mask );
546	555	break;
547	556	}
548	557	}
r14844	r14845
594	603	state->m_rtc_regs.timer->adjust(attotime::from_hz(1));
595	604	}
596	605
597		static READ32_HANDLER( ps_rtc_r )
	606	READ32_MEMBER(pockstat_state::ps_rtc_r)
598	607	{
599		pockstat_state *state = space->machine().driver_data<pockstat_state>();
600	608	switch(offset)
601	609	{
602	610	case 0x0000/4:
603		verboselog(space->machine(), 0, "ps_rtc_r: RTC Mode = %08x & %08x\n", state->m_rtc_regs.mode, mem_mask );
604		return state->m_rtc_regs.mode;
	611	verboselog(machine(), 0, "ps_rtc_r: RTC Mode = %08x & %08x\n", m_rtc_regs.mode, mem_mask );
	612	return m_rtc_regs.mode;
605	613	case 0x0004/4:
606		verboselog(space->machine(), 0, "ps_rtc_r: RTC Control = %08x & %08x\n", state->m_rtc_regs.control, mem_mask );
607		return state->m_rtc_regs.control;
	614	verboselog(machine(), 0, "ps_rtc_r: RTC Control = %08x & %08x\n", m_rtc_regs.control, mem_mask );
	615	return m_rtc_regs.control;
608	616	case 0x0008/4:
609		verboselog(space->machine(), 0, "ps_rtc_r: RTC Time = %08x & %08x\n", state->m_rtc_regs.time, mem_mask );
610		return state->m_rtc_regs.time;
	617	verboselog(machine(), 0, "ps_rtc_r: RTC Time = %08x & %08x\n", m_rtc_regs.time, mem_mask );
	618	return m_rtc_regs.time;
611	619	case 0x000c/4:
612		verboselog(space->machine(), 0, "ps_rtc_r: RTC Date = %08x & %08x\n", state->m_rtc_regs.date, mem_mask );
613		return state->m_rtc_regs.date;
	620	verboselog(machine(), 0, "ps_rtc_r: RTC Date = %08x & %08x\n", m_rtc_regs.date, mem_mask );
	621	return m_rtc_regs.date;
614	622	default:
615		verboselog(space->machine(), 0, "ps_rtc_r: Unknown Register %08x & %08x\n", 0x0b800000 + (offset << 2), mem_mask );
	623	verboselog(machine(), 0, "ps_rtc_r: Unknown Register %08x & %08x\n", 0x0b800000 + (offset << 2), mem_mask );
616	624	break;
617	625	}
618	626	return 0;
619	627	}
620	628
621		static WRITE32_HANDLER( ps_rtc_w )
	629	WRITE32_MEMBER(pockstat_state::ps_rtc_w)
622	630	{
623		pockstat_state *state = space->machine().driver_data<pockstat_state>();
624	631	switch(offset)
625	632	{
626	633	case 0x0000/4:
627		verboselog(space->machine(), 0, "ps_rtc_w: RTC Mode = %08x & %08x\n", data, mem_mask );
628		COMBINE_DATA(&state->m_rtc_regs.mode);
	634	verboselog(machine(), 0, "ps_rtc_w: RTC Mode = %08x & %08x\n", data, mem_mask );
	635	COMBINE_DATA(&m_rtc_regs.mode);
629	636	break;
630	637	case 0x0004/4:
631		verboselog(space->machine(), 0, "ps_rtc_w: RTC Control = %08x & %08x\n", data, mem_mask );
632		if(state->m_rtc_regs.control == 1 && data == 1)
	638	verboselog(machine(), 0, "ps_rtc_w: RTC Control = %08x & %08x\n", data, mem_mask );
	639	if(m_rtc_regs.control == 1 && data == 1)
633	640	{
634		switch(state->m_rtc_regs.mode >> 1)
	641	switch(m_rtc_regs.mode >> 1)
635	642	{
636	643	case 0: // Seconds
637		state->m_rtc_regs.time += 0x00000001;
638		if((state->m_rtc_regs.time & 0x0000000f) == 0x0000000a)
	644	m_rtc_regs.time += 0x00000001;
	645	if((m_rtc_regs.time & 0x0000000f) == 0x0000000a)
639	646	{
640		state->m_rtc_regs.time &= 0xfffffff0;
641		state->m_rtc_regs.time += 0x00000010;
642		if((state->m_rtc_regs.time & 0x000000ff) == 0x00000060)
	647	m_rtc_regs.time &= 0xfffffff0;
	648	m_rtc_regs.time += 0x00000010;
	649	if((m_rtc_regs.time & 0x000000ff) == 0x00000060)
643	650	{
644		state->m_rtc_regs.time &= 0xffffff00;
	651	m_rtc_regs.time &= 0xffffff00;
645	652	}
646	653	}
647	654	break;
648	655	case 1: // Minutes
649		state->m_rtc_regs.time += 0x00000100;
650		if((state->m_rtc_regs.time & 0x00000f00) == 0x00000a00)
	656	m_rtc_regs.time += 0x00000100;
	657	if((m_rtc_regs.time & 0x00000f00) == 0x00000a00)
651	658	{
652		state->m_rtc_regs.time &= 0xfffff0ff;
653		state->m_rtc_regs.time += 0x00001000;
654		if((state->m_rtc_regs.time & 0x0000ff00) == 0x00006000)
	659	m_rtc_regs.time &= 0xfffff0ff;
	660	m_rtc_regs.time += 0x00001000;
	661	if((m_rtc_regs.time & 0x0000ff00) == 0x00006000)
655	662	{
656		state->m_rtc_regs.time &= 0xffff00ff;
	663	m_rtc_regs.time &= 0xffff00ff;
657	664	}
658	665	}
659	666	break;
660	667	case 2: // Hours
661		state->m_rtc_regs.time += 0x00010000;
662		if((state->m_rtc_regs.time & 0x00ff0000) == 0x00240000)
	668	m_rtc_regs.time += 0x00010000;
	669	if((m_rtc_regs.time & 0x00ff0000) == 0x00240000)
663	670	{
664		state->m_rtc_regs.time &= 0xff00ffff;
	671	m_rtc_regs.time &= 0xff00ffff;
665	672	}
666		else if((state->m_rtc_regs.time & 0x000f0000) == 0x000a0000)
	673	else if((m_rtc_regs.time & 0x000f0000) == 0x000a0000)
667	674	{
668		state->m_rtc_regs.time &= 0xfff0ffff;
669		state->m_rtc_regs.time += 0x00100000;
	675	m_rtc_regs.time &= 0xfff0ffff;
	676	m_rtc_regs.time += 0x00100000;
670	677	}
671	678	break;
672	679	case 3: // Day of the week
673		state->m_rtc_regs.time += 0x01000000;
674		if((state->m_rtc_regs.time & 0x0f000000) == 0x08000000)
	680	m_rtc_regs.time += 0x01000000;
	681	if((m_rtc_regs.time & 0x0f000000) == 0x08000000)
675	682	{
676		state->m_rtc_regs.time &= 0xf0ffffff;
677		state->m_rtc_regs.time |= 0x01000000;
	683	m_rtc_regs.time &= 0xf0ffffff;
	684	m_rtc_regs.time |= 0x01000000;
678	685	}
679	686	break;
680	687	case 4: // Day
681		state->m_rtc_regs.date += 0x00000001;
682		if((state->m_rtc_regs.date & 0x000000ff) == 0x00000032)
	688	m_rtc_regs.date += 0x00000001;
	689	if((m_rtc_regs.date & 0x000000ff) == 0x00000032)
683	690	{
684		state->m_rtc_regs.date &= 0xffffff00;
	691	m_rtc_regs.date &= 0xffffff00;
685	692	}
686		else if((state->m_rtc_regs.date & 0x0000000f) == 0x0000000a)
	693	else if((m_rtc_regs.date & 0x0000000f) == 0x0000000a)
687	694	{
688		state->m_rtc_regs.date &= 0xfffffff0;
689		state->m_rtc_regs.date += 0x00000010;
	695	m_rtc_regs.date &= 0xfffffff0;
	696	m_rtc_regs.date += 0x00000010;
690	697	}
691	698	break;
692	699	case 5: // Month
693		state->m_rtc_regs.date += 0x00000100;
694		if((state->m_rtc_regs.date & 0x0000ff00) == 0x00001300)
	700	m_rtc_regs.date += 0x00000100;
	701	if((m_rtc_regs.date & 0x0000ff00) == 0x00001300)
695	702	{
696		state->m_rtc_regs.date &= 0xffffff00;
697		state->m_rtc_regs.date |= 0x00000001;
	703	m_rtc_regs.date &= 0xffffff00;
	704	m_rtc_regs.date |= 0x00000001;
698	705	}
699		else if((state->m_rtc_regs.date & 0x00000f00) == 0x00000a00)
	706	else if((m_rtc_regs.date & 0x00000f00) == 0x00000a00)
700	707	{
701		state->m_rtc_regs.date &= 0xfffff0ff;
702		state->m_rtc_regs.date += 0x00001000;
	708	m_rtc_regs.date &= 0xfffff0ff;
	709	m_rtc_regs.date += 0x00001000;
703	710	}
704	711	break;
705	712	case 6: // Year (LSB)
706		state->m_rtc_regs.date += 0x00010000;
707		if((state->m_rtc_regs.date & 0x000f0000) == 0x000a0000)
	713	m_rtc_regs.date += 0x00010000;
	714	if((m_rtc_regs.date & 0x000f0000) == 0x000a0000)
708	715	{
709		state->m_rtc_regs.date &= 0xfff0ffff;
710		state->m_rtc_regs.date += 0x00100000;
711		if((state->m_rtc_regs.date & 0x00f00000) == 0x00a00000)
	716	m_rtc_regs.date &= 0xfff0ffff;
	717	m_rtc_regs.date += 0x00100000;
	718	if((m_rtc_regs.date & 0x00f00000) == 0x00a00000)
712	719	{
713		state->m_rtc_regs.date &= 0xff00ffff;
	720	m_rtc_regs.date &= 0xff00ffff;
714	721	}
715	722	}
716	723	break;
717	724	case 7: // Year (MSB)
718	725	break;
719	726	}
720		state->m_rtc_regs.control = 0;
	727	m_rtc_regs.control = 0;
721	728	}
722		else if(state->m_rtc_regs.control == 0)
	729	else if(m_rtc_regs.control == 0)
723	730	{
724		COMBINE_DATA(&state->m_rtc_regs.control);
	731	COMBINE_DATA(&m_rtc_regs.control);
725	732	}
726	733	break;
727	734	default:
728		verboselog(space->machine(), 0, "ps_rtc_w: Unknown Register %08x = %08x & %08x\n", 0x0b800000 + (offset << 2), data, mem_mask );
	735	verboselog(machine(), 0, "ps_rtc_w: Unknown Register %08x = %08x & %08x\n", 0x0b800000 + (offset << 2), data, mem_mask );
729	736	break;
730	737	}
731	738	}
732	739
733	740
734		static READ32_HANDLER( ps_lcd_r )
	741	READ32_MEMBER(pockstat_state::ps_lcd_r)
735	742	{
736		pockstat_state *state = space->machine().driver_data<pockstat_state>();
737	743	switch(offset)
738	744	{
739	745	case 0x0000/4:
740		verboselog(space->machine(), 0, "ps_lcd_r: LCD Control = %08x & %08x\n", state->m_lcd_control | 0x100, mem_mask );
741		return state->m_lcd_control;
	746	verboselog(machine(), 0, "ps_lcd_r: LCD Control = %08x & %08x\n", m_lcd_control | 0x100, mem_mask );
	747	return m_lcd_control;
742	748	default:
743		verboselog(space->machine(), 0, "ps_lcd_r: Unknown Register %08x & %08x\n", 0x0d000000 + (offset << 2), mem_mask );
	749	verboselog(machine(), 0, "ps_lcd_r: Unknown Register %08x & %08x\n", 0x0d000000 + (offset << 2), mem_mask );
744	750	break;
745	751	}
746	752	return 0;
747	753	}
748	754
749		static WRITE32_HANDLER( ps_lcd_w )
	755	WRITE32_MEMBER(pockstat_state::ps_lcd_w)
750	756	{
751		pockstat_state *state = space->machine().driver_data<pockstat_state>();
752	757	switch(offset)
753	758	{
754	759	case 0x0000/4:
755		verboselog(space->machine(), 0, "ps_lcd_w: LCD Control = %08x & %08x\n", data, mem_mask );
756		COMBINE_DATA(&state->m_lcd_control);
	760	verboselog(machine(), 0, "ps_lcd_w: LCD Control = %08x & %08x\n", data, mem_mask );
	761	COMBINE_DATA(&m_lcd_control);
757	762	break;
758	763	default:
759		verboselog(space->machine(), 0, "ps_lcd_w: Unknown Register %08x = %08x & %08x\n", 0x0d000000 + (offset << 2), data, mem_mask );
	764	verboselog(machine(), 0, "ps_lcd_w: Unknown Register %08x = %08x & %08x\n", 0x0d000000 + (offset << 2), data, mem_mask );
760	765	break;
761	766	}
762	767	}
r14844	r14845
772	777	ps_intc_set_interrupt_line(field.machine(), PS_INT_BTN_UP,   (buttons & 16) ? 1 : 0);
773	778	}
774	779
775		static READ32_HANDLER(ps_rombank_r)
	780	READ32_MEMBER(pockstat_state::ps_rombank_r)
776	781	{
777		pockstat_state *state = space->machine().driver_data<pockstat_state>();
778	782	INT32 bank = (offset >> 11) & 0x0f;
779	783	int index = 0;
780	784	for(index = 0; index < 32; index++)
781	785	{
782		if(state->m_ftlb_regs.valid & (1 << index))
	786	if(m_ftlb_regs.valid & (1 << index))
783	787	{
784		if(state->m_ftlb_regs.entry[index] == bank)
	788	if(m_ftlb_regs.entry[index] == bank)
785	789	{
786	790	//printf( "Address %08x is assigned to %08x in entry %d\n", 0x02000000 + (offset << 2), index * 0x2000 + ((offset << 2) & 0x1fff), index );
787		return space->machine().region("flash")->u32(index * (0x2000/4) + (offset & (0x1fff/4)));
	791	return machine().region("flash")->u32(index * (0x2000/4) + (offset & (0x1fff/4)));
788	792	}
789	793	}
790	794	}
791		return space->machine().region("flash")->u32(offset & 0x7fff);
	795	return machine().region("flash")->u32(offset & 0x7fff);
792	796	}
793	797
794	798
795	799	// Horrible hack, probably wrong
796		static WRITE32_HANDLER(ps_flash_w)
	800	WRITE32_MEMBER(pockstat_state::ps_flash_w)
797	801	{
798		pockstat_state *state = space->machine().driver_data<pockstat_state>();
799	802	if(offset == (0x55a8/4))
800	803	{
801		state->m_ps_flash_write_enable_count++;
	804	m_ps_flash_write_enable_count++;
802	805	return;
803	806	}
804	807	if(offset == (0x2a54/4))
805	808	{
806		state->m_ps_flash_write_enable_count++;
	809	m_ps_flash_write_enable_count++;
807	810	return;
808	811	}
809		if(state->m_ps_flash_write_enable_count == 3)
	812	if(m_ps_flash_write_enable_count == 3)
810	813	{
811		state->m_ps_flash_write_enable_count = 0;
812		state->m_ps_flash_write_count = 0x40;
	814	m_ps_flash_write_enable_count = 0;
	815	m_ps_flash_write_count = 0x40;
813	816	return;
814	817	}
815		if(state->m_ps_flash_write_count)
	818	if(m_ps_flash_write_count)
816	819	{
817		state->m_ps_flash_write_count--;
818		COMBINE_DATA(&((UINT32*)(*space->machine().region("flash")))[offset]);
	820	m_ps_flash_write_count--;
	821	COMBINE_DATA(&((UINT32*)(*machine().region("flash")))[offset]);
819	822	}
820	823	}
821	824
822		static READ32_HANDLER( ps_audio_r )
	825	READ32_MEMBER(pockstat_state::ps_audio_r)
823	826	{
824		verboselog(space->machine(), 0, "ps_audio_r: Unknown Read: %08x = %08x & %08x\n", 0xd800000 + (offset << 2), 0x10, mem_mask);
	827	verboselog(machine(), 0, "ps_audio_r: Unknown Read: %08x = %08x & %08x\n", 0xd800000 + (offset << 2), 0x10, mem_mask);
825	828	return 0;
826	829	}
827	830
828		static WRITE32_HANDLER( ps_audio_w )
	831	WRITE32_MEMBER(pockstat_state::ps_audio_w)
829	832	{
830		verboselog(space->machine(), 0, "ps_audio_w: Unknown Write: %08x = %08x & %08x\n", 0xd800000 + (offset << 2), data, mem_mask);
	833	verboselog(machine(), 0, "ps_audio_w: Unknown Write: %08x = %08x & %08x\n", 0xd800000 + (offset << 2), data, mem_mask);
831	834	}
832	835
833		static WRITE32_HANDLER( ps_dac_w )
	836	WRITE32_MEMBER(pockstat_state::ps_dac_w)
834	837	{
835		dac_data_16_w(space->machine().device("dac"), (UINT16)((data + 0x8000) & 0x0000ffff));
	838	dac_data_16_w(machine().device("dac"), (UINT16)((data + 0x8000) & 0x0000ffff));
836	839	}
837	840
838	841	static ADDRESS_MAP_START(pockstat_mem, AS_PROGRAM, 32, pockstat_state )
839	842	AM_RANGE(0x00000000, 0x000007ff) AM_RAM
840		AM_RANGE(0x02000000, 0x02ffffff) AM_READ_LEGACY(ps_rombank_r)
	843	AM_RANGE(0x02000000, 0x02ffffff) AM_READ(ps_rombank_r)
841	844	AM_RANGE(0x04000000, 0x04003fff) AM_ROM AM_REGION("maincpu", 0)
842		AM_RANGE(0x06000000, 0x06000307) AM_READWRITE_LEGACY(ps_ftlb_r, ps_ftlb_w)
843		AM_RANGE(0x08000000, 0x0801ffff) AM_ROM AM_WRITE_LEGACY(ps_flash_w) AM_REGION("flash", 0)
844		AM_RANGE(0x0a000000, 0x0a000013) AM_READWRITE_LEGACY(ps_intc_r, ps_intc_w)
845		AM_RANGE(0x0a800000, 0x0a80002b) AM_READWRITE_LEGACY(ps_timer_r, ps_timer_w)
846		AM_RANGE(0x0b000000, 0x0b000007) AM_READWRITE_LEGACY(ps_clock_r, ps_clock_w)
847		AM_RANGE(0x0b800000, 0x0b80000f) AM_READWRITE_LEGACY(ps_rtc_r, ps_rtc_w)
848		AM_RANGE(0x0d000000, 0x0d000003) AM_READWRITE_LEGACY(ps_lcd_r, ps_lcd_w)
	845	AM_RANGE(0x06000000, 0x06000307) AM_READWRITE(ps_ftlb_r, ps_ftlb_w)
	846	AM_RANGE(0x08000000, 0x0801ffff) AM_ROM AM_WRITE(ps_flash_w) AM_REGION("flash", 0)
	847	AM_RANGE(0x0a000000, 0x0a000013) AM_READWRITE(ps_intc_r, ps_intc_w)
	848	AM_RANGE(0x0a800000, 0x0a80002b) AM_READWRITE(ps_timer_r, ps_timer_w)
	849	AM_RANGE(0x0b000000, 0x0b000007) AM_READWRITE(ps_clock_r, ps_clock_w)
	850	AM_RANGE(0x0b800000, 0x0b80000f) AM_READWRITE(ps_rtc_r, ps_rtc_w)
	851	AM_RANGE(0x0d000000, 0x0d000003) AM_READWRITE(ps_lcd_r, ps_lcd_w)
849	852	AM_RANGE(0x0d000100, 0x0d00017f) AM_RAM AM_BASE(m_lcd_buffer)
850		AM_RANGE(0x0d80000c, 0x0d80000f) AM_READWRITE_LEGACY(ps_audio_r, ps_audio_w)
851		AM_RANGE(0x0d800014, 0x0d800017) AM_WRITE_LEGACY(ps_dac_w)
	853	AM_RANGE(0x0d80000c, 0x0d80000f) AM_READWRITE(ps_audio_r, ps_audio_w)
	854	AM_RANGE(0x0d800014, 0x0d800017) AM_WRITE(ps_dac_w)
852	855	ADDRESS_MAP_END
853	856
854	857	/* Input ports */

src/mess/drivers/fp6000.c

r14844	r14845
37	37	struct {
38	38	UINT16 cmd;
39	39	}m_key;
	40	DECLARE_READ8_MEMBER(fp6000_pcg_r);
	41	DECLARE_WRITE8_MEMBER(fp6000_pcg_w);
	42	DECLARE_WRITE8_MEMBER(fp6000_6845_address_w);
	43	DECLARE_WRITE8_MEMBER(fp6000_6845_data_w);
	44	DECLARE_READ8_MEMBER(fp6000_key_r);
	45	DECLARE_WRITE8_MEMBER(fp6000_key_w);
	46	DECLARE_READ16_MEMBER(unk_r);
	47	DECLARE_READ16_MEMBER(ex_board_r);
	48	DECLARE_READ16_MEMBER(pit_r);
40	49	};
41	50
42	51	static VIDEO_START( fp6000 )
r14844	r14845
126	135	return 0;
127	136	}
128	137
129		static READ8_HANDLER( fp6000_pcg_r )
	138	READ8_MEMBER(fp6000_state::fp6000_pcg_r)
130	139	{
131		fp6000_state *state = space->machine().driver_data<fp6000_state>();
132	140
133		return state->m_char_rom[offset];
	141	return m_char_rom[offset];
134	142	}
135	143
136		static WRITE8_HANDLER( fp6000_pcg_w )
	144	WRITE8_MEMBER(fp6000_state::fp6000_pcg_w)
137	145	{
138		fp6000_state *state = space->machine().driver_data<fp6000_state>();
139	146
140		state->m_char_rom[offset] = data;
141		gfx_element_mark_dirty(space->machine().gfx[0], offset >> 4);
	147	m_char_rom[offset] = data;
	148	gfx_element_mark_dirty(machine().gfx[0], offset >> 4);
142	149	}
143	150
144		static WRITE8_HANDLER( fp6000_6845_address_w )
	151	WRITE8_MEMBER(fp6000_state::fp6000_6845_address_w)
145	152	{
146		fp6000_state *state = space->machine().driver_data<fp6000_state>();
147	153
148		state->m_crtc_index = data;
149		state->m_mc6845->address_w(*space, offset, data);
	154	m_crtc_index = data;
	155	m_mc6845->address_w(*&space, offset, data);
150	156	}
151	157
152		static WRITE8_HANDLER( fp6000_6845_data_w )
	158	WRITE8_MEMBER(fp6000_state::fp6000_6845_data_w)
153	159	{
154		fp6000_state *state = space->machine().driver_data<fp6000_state>();
155	160
156		state->m_crtc_vreg[state->m_crtc_index] = data;
157		state->m_mc6845->register_w(*space, offset, data);
	161	m_crtc_vreg[m_crtc_index] = data;
	162	m_mc6845->register_w(*&space, offset, data);
158	163	}
159	164
160	165	static ADDRESS_MAP_START(fp6000_map, AS_PROGRAM, 16, fp6000_state )
r14844	r14845
162	167	AM_RANGE(0x00000,0xbffff) AM_RAM
163	168	AM_RANGE(0xc0000,0xdffff) AM_RAM AM_BASE(m_gvram)//gvram
164	169	AM_RANGE(0xe0000,0xe0fff) AM_RAM AM_BASE(m_vram)
165		AM_RANGE(0xe7000,0xe7fff) AM_READWRITE8_LEGACY(fp6000_pcg_r,fp6000_pcg_w,0xffff)
	170	AM_RANGE(0xe7000,0xe7fff) AM_READWRITE8(fp6000_pcg_r,fp6000_pcg_w,0xffff)
166	171	AM_RANGE(0xf0000,0xfffff) AM_ROM AM_REGION("ipl", 0)
167	172	ADDRESS_MAP_END
168	173
169	174	/* Hack until I understand what UART is this one ... */
170		static READ8_HANDLER( fp6000_key_r )
	175	READ8_MEMBER(fp6000_state::fp6000_key_r)
171	176	{
172		fp6000_state *state = space->machine().driver_data<fp6000_state>();
173	177
174	178	if(offset)
175	179	{
176		switch(state->m_key.cmd)
	180	switch(m_key.cmd)
177	181	{
178	182	case 0x7e15: return 3;
179	183	case 0x1b15: return 1;
180	184	case 0x2415: return 0;
181		default: printf("%04x\n",state->m_key.cmd);
	185	default: printf("%04x\n",m_key.cmd);
182	186	}
183	187	return 0;
184	188	}
r14844	r14845
186	190	return 0x40;
187	191	}
188	192
189		static WRITE8_HANDLER( fp6000_key_w )
	193	WRITE8_MEMBER(fp6000_state::fp6000_key_w)
190	194	{
191		fp6000_state *state = space->machine().driver_data<fp6000_state>();
192	195
193	196	if(offset)
194		state->m_key.cmd = (data & 0xff) | (state->m_key.cmd << 8);
	197	m_key.cmd = (data & 0xff) | (m_key.cmd << 8);
195	198	else
196		state->m_key.cmd = (data << 8) | (state->m_key.cmd & 0xff);
	199	m_key.cmd = (data << 8) | (m_key.cmd & 0xff);
197	200	}
198	201
199		static READ16_HANDLER( unk_r )
	202	READ16_MEMBER(fp6000_state::unk_r)
200	203	{
201	204	return 0x40;
202	205	}
203	206
204		static READ16_HANDLER( ex_board_r )
	207	READ16_MEMBER(fp6000_state::ex_board_r)
205	208	{
206	209	return 0xffff;
207	210	}
208	211
209		static READ16_HANDLER( pit_r )
	212	READ16_MEMBER(fp6000_state::pit_r)
210	213	{
211		return space->machine().rand();
	214	return machine().rand();
212	215	}
213	216
214	217	static ADDRESS_MAP_START(fp6000_io, AS_IO, 16, fp6000_state )
215	218	ADDRESS_MAP_UNMAP_HIGH
216		AM_RANGE(0x08, 0x09) AM_READ_LEGACY(ex_board_r) // BIOS of some sort ...
	219	AM_RANGE(0x08, 0x09) AM_READ(ex_board_r) // BIOS of some sort ...
217	220	AM_RANGE(0x0a, 0x0b) AM_READ_PORT("DSW") // installed RAM id?
218	221	AM_RANGE(0x10, 0x11) AM_READNOP
219		AM_RANGE(0x20, 0x23) AM_READWRITE8_LEGACY(fp6000_key_r,fp6000_key_w,0x00ff)
220		AM_RANGE(0x38, 0x39) AM_READ_LEGACY(pit_r) // pit?
221		AM_RANGE(0x70, 0x71) AM_WRITE8_LEGACY(fp6000_6845_address_w,0x00ff)
222		AM_RANGE(0x72, 0x73) AM_WRITE8_LEGACY(fp6000_6845_data_w,0x00ff)
223		AM_RANGE(0x74, 0x75) AM_READ_LEGACY(unk_r) //bit 6 busy flag
	222	AM_RANGE(0x20, 0x23) AM_READWRITE8(fp6000_key_r,fp6000_key_w,0x00ff)
	223	AM_RANGE(0x38, 0x39) AM_READ(pit_r) // pit?
	224	AM_RANGE(0x70, 0x71) AM_WRITE8(fp6000_6845_address_w,0x00ff)
	225	AM_RANGE(0x72, 0x73) AM_WRITE8(fp6000_6845_data_w,0x00ff)
	226	AM_RANGE(0x74, 0x75) AM_READ(unk_r) //bit 6 busy flag
224	227	ADDRESS_MAP_END
225	228
226	229	/* Input ports */

src/mess/drivers/jr100.c

r14844	r14845
35	35	UINT8 m_speaker;
36	36	UINT16 m_t1latch;
37	37	UINT8 m_beep_en;
	38	DECLARE_WRITE8_MEMBER(jr100_via_w);
38	39	};
39	40
40	41
41	42
42	43
43		static WRITE8_HANDLER( jr100_via_w )
	44	WRITE8_MEMBER(jr100_state::jr100_via_w)
44	45	{
45		jr100_state *state = space->machine().driver_data<jr100_state>();
46	46	/* ACR: beeper masking */
47	47	if(offset == 0x0b)
48	48	{
49	49	//printf("BEEP %s\n",((data & 0xe0) == 0xe0) ? "ON" : "OFF");
50		state->m_beep_en = ((data & 0xe0) == 0xe0);
	50	m_beep_en = ((data & 0xe0) == 0xe0);
51	51
52		if(!state->m_beep_en)
53		beep_set_state(space->machine().device(BEEPER_TAG),0);
	52	if(!m_beep_en)
	53	beep_set_state(machine().device(BEEPER_TAG),0);
54	54	}
55	55
56	56	/* T1L-L */
57	57	if(offset == 0x04)
58	58	{
59		state->m_t1latch = (state->m_t1latch & 0xff00) | (data & 0xff);
	59	m_t1latch = (m_t1latch & 0xff00) | (data & 0xff);
60	60	//printf("BEEP T1CL %02x\n",data);
61	61	}
62	62
63	63	/* T1L-H */
64	64	if(offset == 0x05)
65	65	{
66		state->m_t1latch = (state->m_t1latch & 0xff) | ((data & 0xff) << 8);
	66	m_t1latch = (m_t1latch & 0xff) | ((data & 0xff) << 8);
67	67	//printf("BEEP T1CH %02x\n",data);
68	68
69	69	/* writing here actually enables the beeper, if above masking condition is satisfied */
70		if(state->m_beep_en)
	70	if(m_beep_en)
71	71	{
72		beep_set_state(space->machine().device(BEEPER_TAG),1);
73		beep_set_frequency(space->machine().device(BEEPER_TAG),894886.25 / (double)(state->m_t1latch) / 2.0);
	72	beep_set_state(machine().device(BEEPER_TAG),1);
	73	beep_set_frequency(machine().device(BEEPER_TAG),894886.25 / (double)(m_t1latch) / 2.0);
74	74	}
75	75	}
76		via6522_device *via = space->machine().device<via6522_device>("via");
77		via->write(*space,offset,data);
	76	via6522_device *via = machine().device<via6522_device>("via");
	77	via->write(*&space,offset,data);
78	78	}
79	79
80	80	static ADDRESS_MAP_START(jr100_mem, AS_PROGRAM, 8, jr100_state )
r14844	r14845
82	82	AM_RANGE(0x0000, 0x3fff) AM_RAM AM_BASE(m_ram)
83	83	AM_RANGE(0xc000, 0xc0ff) AM_RAM AM_BASE(m_pcg)
84	84	AM_RANGE(0xc100, 0xc3ff) AM_RAM AM_BASE(m_vram)
85		AM_RANGE(0xc800, 0xc80f) AM_DEVREAD("via", via6522_device, read) AM_WRITE_LEGACY(jr100_via_w)
	85	AM_RANGE(0xc800, 0xc80f) AM_DEVREAD("via", via6522_device, read) AM_WRITE(jr100_via_w)
86	86	AM_RANGE(0xe000, 0xffff) AM_ROM
87	87	ADDRESS_MAP_END
88	88

src/mess/drivers/pk8000.c

r14844	r14845
25	25	: driver_device(mconfig, type, tag) { }
26	26
27	27	UINT8 m_keyboard_line;
	28	DECLARE_READ8_MEMBER(pk8000_joy_1_r);
	29	DECLARE_READ8_MEMBER(pk8000_joy_2_r);
28	30	};
29	31
30	32
r14844	r14845
155	157	DEVCB_HANDLER(pk8000_84_portc_w)
156	158	};
157	159
158		static READ8_HANDLER(pk8000_joy_1_r)
	160	READ8_MEMBER(pk8000_state::pk8000_joy_1_r)
159	161	{
160		UINT8 retVal = (cassette_device_image(space->machine())->input() > 0.0038 ? 0x80 : 0);
161		retVal |= input_port_read(space->machine(), "JOY1") & 0x7f;
	162	UINT8 retVal = (cassette_device_image(machine())->input() > 0.0038 ? 0x80 : 0);
	163	retVal |= input_port_read(machine(), "JOY1") & 0x7f;
162	164	return retVal;
163	165	}
164		static READ8_HANDLER(pk8000_joy_2_r)
	166	READ8_MEMBER(pk8000_state::pk8000_joy_2_r)
165	167	{
166		UINT8 retVal = (cassette_device_image(space->machine())->input() > 0.0038 ? 0x80 : 0);
167		retVal |= input_port_read(space->machine(), "JOY2") & 0x7f;
	168	UINT8 retVal = (cassette_device_image(machine())->input() > 0.0038 ? 0x80 : 0);
	169	retVal |= input_port_read(machine(), "JOY2") & 0x7f;
168	170	return retVal;
169	171	}
170	172
r14844	r14845
181	183	AM_RANGE(0x80, 0x83) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
182	184	AM_RANGE(0x84, 0x87) AM_DEVREADWRITE("ppi8255_2", i8255_device, read, write)
183	185	AM_RANGE(0x88, 0x88) AM_READWRITE_LEGACY(pk8000_video_color_r,pk8000_video_color_w)
184		AM_RANGE(0x8c, 0x8c) AM_READ_LEGACY(pk8000_joy_1_r)
185		AM_RANGE(0x8d, 0x8d) AM_READ_LEGACY(pk8000_joy_2_r)
	186	AM_RANGE(0x8c, 0x8c) AM_READ(pk8000_joy_1_r)
	187	AM_RANGE(0x8d, 0x8d) AM_READ(pk8000_joy_2_r)
186	188	AM_RANGE(0x90, 0x90) AM_READWRITE_LEGACY(pk8000_text_start_r,pk8000_text_start_w)
187	189	AM_RANGE(0x91, 0x91) AM_READWRITE_LEGACY(pk8000_chargen_start_r,pk8000_chargen_start_w)
188	190	AM_RANGE(0x92, 0x92) AM_READWRITE_LEGACY(pk8000_video_start_r,pk8000_video_start_w)

src/mess/drivers/sgi_ip2.c

r14844	r14845
69	69	UINT8 m_mbp;
70	70
71	71	required_device<generic_terminal_device> m_terminal;
	72	DECLARE_READ8_MEMBER(sgi_ip2_m_but_r);
	73	DECLARE_WRITE8_MEMBER(sgi_ip2_m_but_w);
	74	DECLARE_READ16_MEMBER(sgi_ip2_m_quad_r);
	75	DECLARE_WRITE16_MEMBER(sgi_ip2_m_quad_w);
	76	DECLARE_READ16_MEMBER(sgi_ip2_swtch_r);
	77	DECLARE_READ8_MEMBER(sgi_ip2_clock_ctl_r);
	78	DECLARE_WRITE8_MEMBER(sgi_ip2_clock_ctl_w);
	79	DECLARE_READ8_MEMBER(sgi_ip2_clock_data_r);
	80	DECLARE_WRITE8_MEMBER(sgi_ip2_clock_data_w);
	81	DECLARE_READ8_MEMBER(sgi_ip2_os_base_r);
	82	DECLARE_WRITE8_MEMBER(sgi_ip2_os_base_w);
	83	DECLARE_READ16_MEMBER(sgi_ip2_status_r);
	84	DECLARE_WRITE16_MEMBER(sgi_ip2_status_w);
	85	DECLARE_READ8_MEMBER(sgi_ip2_parctl_r);
	86	DECLARE_WRITE8_MEMBER(sgi_ip2_parctl_w);
	87	DECLARE_READ8_MEMBER(sgi_ip2_mbp_r);
	88	DECLARE_WRITE8_MEMBER(sgi_ip2_mbp_w);
	89	DECLARE_READ32_MEMBER(sgi_ip2_ptmap_r);
	90	DECLARE_WRITE32_MEMBER(sgi_ip2_ptmap_w);
	91	DECLARE_READ16_MEMBER(sgi_ip2_tdbase_r);
	92	DECLARE_WRITE16_MEMBER(sgi_ip2_tdbase_w);
	93	DECLARE_READ16_MEMBER(sgi_ip2_tdlmt_r);
	94	DECLARE_WRITE16_MEMBER(sgi_ip2_tdlmt_w);
	95	DECLARE_READ16_MEMBER(sgi_ip2_stkbase_r);
	96	DECLARE_WRITE16_MEMBER(sgi_ip2_stkbase_w);
	97	DECLARE_READ16_MEMBER(sgi_ip2_stklmt_r);
	98	DECLARE_WRITE16_MEMBER(sgi_ip2_stklmt_w);
72	99	};
73	100
74	101
r14844	r14845
104	131	#define BOARD_REV2      0x50   /* Board revision - #2 */
105	132
106	133
107		static READ8_HANDLER(sgi_ip2_m_but_r)
	134	READ8_MEMBER(sgi_ip2_state::sgi_ip2_m_but_r)
108	135	{
109		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
110		verboselog(space->machine(), 0, "sgi_ip2_m_but_r: %02x\n", state->m_mbut | BOARD_REV1);
111		return state->m_mbut | BOARD_REV1;
	136	verboselog(machine(), 0, "sgi_ip2_m_but_r: %02x\n", m_mbut | BOARD_REV1);
	137	return m_mbut | BOARD_REV1;
112	138	}
113	139
114		static WRITE8_HANDLER(sgi_ip2_m_but_w)
	140	WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_m_but_w)
115	141	{
116		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
117		verboselog(space->machine(), 0, "sgi_ip2_m_but_w: %02x\n", data);
118		state->m_mbut = data;
	142	verboselog(machine(), 0, "sgi_ip2_m_but_w: %02x\n", data);
	143	m_mbut = data;
119	144	}
120	145
121	146	#define MOUSE_XFIRE      0x01   /* X Quadrature Fired, active low */
r14844	r14845
124	149	#define MOUSE_YCHANGE   0x08   /* MOUSE_YCHANGE ? y-- : y++ */
125	150
126	151
127		static READ16_HANDLER(sgi_ip2_m_quad_r)
	152	READ16_MEMBER(sgi_ip2_state::sgi_ip2_m_quad_r)
128	153	{
129		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
130		verboselog(space->machine(), 0, "sgi_ip2_m_quad_r: %04x\n", state->m_mquad);
131		return state->m_mquad;
	154	verboselog(machine(), 0, "sgi_ip2_m_quad_r: %04x\n", m_mquad);
	155	return m_mquad;
132	156	}
133	157
134		static WRITE16_HANDLER(sgi_ip2_m_quad_w)
	158	WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_m_quad_w)
135	159	{
136		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
137		verboselog(space->machine(), 0, "sgi_ip2_m_quad_w = %04x & %04x\n", data, mem_mask);
138		COMBINE_DATA(&state->m_mquad);
	160	verboselog(machine(), 0, "sgi_ip2_m_quad_w = %04x & %04x\n", data, mem_mask);
	161	COMBINE_DATA(&m_mquad);
139	162	}
140	163
141		static READ16_HANDLER(sgi_ip2_swtch_r)
	164	READ16_MEMBER(sgi_ip2_state::sgi_ip2_swtch_r)
142	165	{
143		verboselog(space->machine(), 0, "sgi_ip2_swtch_r: %04x\n", input_port_read(space->machine(), "SWTCH"));
144		return input_port_read(space->machine(), "SWTCH");
	166	verboselog(machine(), 0, "sgi_ip2_swtch_r: %04x\n", input_port_read(machine(), "SWTCH"));
	167	return input_port_read(machine(), "SWTCH");
145	168	}
146	169
147		static READ8_HANDLER(sgi_ip2_clock_ctl_r)
	170	READ8_MEMBER(sgi_ip2_state::sgi_ip2_clock_ctl_r)
148	171	{
149		mc146818_device *rtc = space->machine().device<mc146818_device>("rtc");
150		UINT8 ret = rtc->read(*space, 1);
151		verboselog(space->machine(), 1, "sgi_ip2_clock_ctl_r: %02x\n", ret);
	172	mc146818_device *rtc = machine().device<mc146818_device>("rtc");
	173	UINT8 ret = rtc->read(*&space, 1);
	174	verboselog(machine(), 1, "sgi_ip2_clock_ctl_r: %02x\n", ret);
152	175	return ret;
153	176	}
154	177
155		static WRITE8_HANDLER(sgi_ip2_clock_ctl_w)
	178	WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_clock_ctl_w)
156	179	{
157		verboselog(space->machine(), 1, "sgi_ip2_clock_ctl_w: %02x\n", data);
158		mc146818_device *rtc = space->machine().device<mc146818_device>("rtc");
159		rtc->write(*space, 1, data);
	180	verboselog(machine(), 1, "sgi_ip2_clock_ctl_w: %02x\n", data);
	181	mc146818_device *rtc = machine().device<mc146818_device>("rtc");
	182	rtc->write(*&space, 1, data);
160	183	}
161	184
162		static READ8_HANDLER(sgi_ip2_clock_data_r)
	185	READ8_MEMBER(sgi_ip2_state::sgi_ip2_clock_data_r)
163	186	{
164		mc146818_device *rtc = space->machine().device<mc146818_device>("rtc");
165		UINT8 ret = rtc->read(*space, 0);
	187	mc146818_device *rtc = machine().device<mc146818_device>("rtc");
	188	UINT8 ret = rtc->read(*&space, 0);
166	189
167		verboselog(space->machine(), 1, "sgi_ip2_clock_data_r: %02x\n", ret);
	190	verboselog(machine(), 1, "sgi_ip2_clock_data_r: %02x\n", ret);
168	191	return ret;
169	192	}
170	193
171		static WRITE8_HANDLER(sgi_ip2_clock_data_w)
	194	WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_clock_data_w)
172	195	{
173		verboselog(space->machine(), 1, "sgi_ip2_clock_data_w: %02x\n", data);
174		mc146818_device *rtc = space->machine().device<mc146818_device>("rtc");
175		rtc->write(*space, 0, data);
	196	verboselog(machine(), 1, "sgi_ip2_clock_data_w: %02x\n", data);
	197	mc146818_device *rtc = machine().device<mc146818_device>("rtc");
	198	rtc->write(*&space, 0, data);
176	199	}
177	200
178	201
179		static READ8_HANDLER(sgi_ip2_os_base_r)
	202	READ8_MEMBER(sgi_ip2_state::sgi_ip2_os_base_r)
180	203	{
181	204	switch(offset)
182	205	{
183	206	default:
184		verboselog(space->machine(), 0, "sgi_ip2_os_base_r: Unknown Register %08x\n", 0x36000000 + offset);
	207	verboselog(machine(), 0, "sgi_ip2_os_base_r: Unknown Register %08x\n", 0x36000000 + offset);
185	208	break;
186	209	}
187	210	return 0;
188	211	}
189	212
190		static WRITE8_HANDLER(sgi_ip2_os_base_w)
	213	WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_os_base_w)
191	214	{
192	215	switch(offset)
193	216	{
194	217	default:
195		verboselog(space->machine(), 0, "sgi_ip2_os_base_w: Unknown Register %08x = %02x\n", 0x36000000 + offset, data);
	218	verboselog(machine(), 0, "sgi_ip2_os_base_w: Unknown Register %08x = %02x\n", 0x36000000 + offset, data);
196	219	break;
197	220	}
198	221	}
199	222
200		static READ16_HANDLER(sgi_ip2_status_r)
	223	READ16_MEMBER(sgi_ip2_state::sgi_ip2_status_r)
201	224	{
202	225	switch(offset)
203	226	{
204	227	default:
205		verboselog(space->machine(), 0, "sgi_ip2_status_r: Unknown Register %08x & %04x\n", 0x38000000 + (offset << 1), mem_mask);
	228	verboselog(machine(), 0, "sgi_ip2_status_r: Unknown Register %08x & %04x\n", 0x38000000 + (offset << 1), mem_mask);
206	229	break;
207	230	}
208	231	return 0;
209	232	}
210	233
211		static WRITE16_HANDLER(sgi_ip2_status_w)
	234	WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_status_w)
212	235	{
213	236	switch(offset)
214	237	{
215	238	default:
216		verboselog(space->machine(), 0, "sgi_ip2_status_w: Unknown Register %08x = %04x & %04x\n", 0x38000000 + (offset << 1), data, mem_mask);
	239	verboselog(machine(), 0, "sgi_ip2_status_w: Unknown Register %08x = %04x & %04x\n", 0x38000000 + (offset << 1), data, mem_mask);
217	240	break;
218	241	}
219	242	}
r14844	r14845
228	251	#define PAR_MBW      0x80   /* Check parity on multibus writes */
229	252
230	253
231		static READ8_HANDLER(sgi_ip2_parctl_r)
	254	READ8_MEMBER(sgi_ip2_state::sgi_ip2_parctl_r)
232	255	{
233		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
234		verboselog(space->machine(), 0, "sgi_ip2_parctl_r: %02x\n", state->m_parctl);
235		return state->m_parctl;
	256	verboselog(machine(), 0, "sgi_ip2_parctl_r: %02x\n", m_parctl);
	257	return m_parctl;
236	258	}
237	259
238		static WRITE8_HANDLER(sgi_ip2_parctl_w)
	260	WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_parctl_w)
239	261	{
240		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
241		verboselog(space->machine(), 0, "sgi_ip2_parctl_w: %02x\n", data);
242		state->m_parctl = data;
	262	verboselog(machine(), 0, "sgi_ip2_parctl_w: %02x\n", data);
	263	m_parctl = data;
243	264	}
244	265
245	266	#define MBP_DCACC   0x01   /* Display controller access (I/O page 4) */
r14844	r14845
252	273	#define MBP_HMACC   0x80   /* Allow upper memory access (0x8nnnnn - 0xfnnnnn) */
253	274
254	275
255		static READ8_HANDLER(sgi_ip2_mbp_r)
	276	READ8_MEMBER(sgi_ip2_state::sgi_ip2_mbp_r)
256	277	{
257		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
258		verboselog(space->machine(), 0, "sgi_ip2_mbp_r: %02x\n", state->m_mbp);
259		return state->m_mbp;
	278	verboselog(machine(), 0, "sgi_ip2_mbp_r: %02x\n", m_mbp);
	279	return m_mbp;
260	280	}
261	281
262		static WRITE8_HANDLER(sgi_ip2_mbp_w)
	282	WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_mbp_w)
263	283	{
264		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
265		verboselog(space->machine(), 0, "sgi_ip2_mbp_w: %02x\n", data);
266		state->m_mbp = data;
	284	verboselog(machine(), 0, "sgi_ip2_mbp_w: %02x\n", data);
	285	m_mbp = data;
267	286	}
268	287
269	288
270		static READ32_HANDLER(sgi_ip2_ptmap_r)
	289	READ32_MEMBER(sgi_ip2_state::sgi_ip2_ptmap_r)
271	290	{
272		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
273		verboselog(space->machine(), 0, "sgi_ip2_ptmap_r: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), state->m_ptmap[offset], mem_mask);
274		return state->m_ptmap[offset];
	291	verboselog(machine(), 0, "sgi_ip2_ptmap_r: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), m_ptmap[offset], mem_mask);
	292	return m_ptmap[offset];
275	293	}
276	294
277		static WRITE32_HANDLER(sgi_ip2_ptmap_w)
	295	WRITE32_MEMBER(sgi_ip2_state::sgi_ip2_ptmap_w)
278	296	{
279		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
280		verboselog(space->machine(), 0, "sgi_ip2_ptmap_w: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), data, mem_mask);
281		COMBINE_DATA(&state->m_ptmap[offset]);
	297	verboselog(machine(), 0, "sgi_ip2_ptmap_w: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), data, mem_mask);
	298	COMBINE_DATA(&m_ptmap[offset]);
282	299	}
283	300
284	301
285		static READ16_HANDLER(sgi_ip2_tdbase_r)
	302	READ16_MEMBER(sgi_ip2_state::sgi_ip2_tdbase_r)
286	303	{
287		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
288		verboselog(space->machine(), 0, "sgi_ip2_tdbase_r: %04x\n", state->m_tdbase);
289		return state->m_tdbase;
	304	verboselog(machine(), 0, "sgi_ip2_tdbase_r: %04x\n", m_tdbase);
	305	return m_tdbase;
290	306	}
291	307
292		static WRITE16_HANDLER(sgi_ip2_tdbase_w)
	308	WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_tdbase_w)
293	309	{
294		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
295		verboselog(space->machine(), 0, "sgi_ip2_tdbase_w: %04x & %04x\n", data, mem_mask);
296		COMBINE_DATA(&state->m_tdbase);
	310	verboselog(machine(), 0, "sgi_ip2_tdbase_w: %04x & %04x\n", data, mem_mask);
	311	COMBINE_DATA(&m_tdbase);
297	312	}
298	313
299	314
300		static READ16_HANDLER(sgi_ip2_tdlmt_r)
	315	READ16_MEMBER(sgi_ip2_state::sgi_ip2_tdlmt_r)
301	316	{
302		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
303		verboselog(space->machine(), 0, "sgi_ip2_tdlmt_r: %04x\n", state->m_tdlmt);
304		return state->m_tdlmt;
	317	verboselog(machine(), 0, "sgi_ip2_tdlmt_r: %04x\n", m_tdlmt);
	318	return m_tdlmt;
305	319	}
306	320
307		static WRITE16_HANDLER(sgi_ip2_tdlmt_w)
	321	WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_tdlmt_w)
308	322	{
309		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
310		verboselog(space->machine(), 0, "sgi_ip2_tdlmt_w: %04x & %04x\n", data, mem_mask);
311		COMBINE_DATA(&state->m_tdlmt);
	323	verboselog(machine(), 0, "sgi_ip2_tdlmt_w: %04x & %04x\n", data, mem_mask);
	324	COMBINE_DATA(&m_tdlmt);
312	325	}
313	326
314	327
315		static READ16_HANDLER(sgi_ip2_stkbase_r)
	328	READ16_MEMBER(sgi_ip2_state::sgi_ip2_stkbase_r)
316	329	{
317		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
318		verboselog(space->machine(), 0, "sgi_ip2_stkbase_r: %04x\n", state->m_stkbase);
319		return state->m_stkbase;
	330	verboselog(machine(), 0, "sgi_ip2_stkbase_r: %04x\n", m_stkbase);
	331	return m_stkbase;
320	332	}
321	333
322		static WRITE16_HANDLER(sgi_ip2_stkbase_w)
	334	WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_stkbase_w)
323	335	{
324		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
325		verboselog(space->machine(), 0, "sgi_ip2_stkbase_w: %04x & %04x\n", data, mem_mask);
326		COMBINE_DATA(&state->m_stkbase);
	336	verboselog(machine(), 0, "sgi_ip2_stkbase_w: %04x & %04x\n", data, mem_mask);
	337	COMBINE_DATA(&m_stkbase);
327	338	}
328	339
329	340
330		static READ16_HANDLER(sgi_ip2_stklmt_r)
	341	READ16_MEMBER(sgi_ip2_state::sgi_ip2_stklmt_r)
331	342	{
332		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
333		verboselog(space->machine(), 0, "sgi_ip2_stklmt_r: %04x\n", state->m_stklmt);
334		return state->m_stklmt;
	343	verboselog(machine(), 0, "sgi_ip2_stklmt_r: %04x\n", m_stklmt);
	344	return m_stklmt;
335	345	}
336	346
337		static WRITE16_HANDLER(sgi_ip2_stklmt_w)
	347	WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_stklmt_w)
338	348	{
339		sgi_ip2_state *state = space->machine().driver_data<sgi_ip2_state>();
340		verboselog(space->machine(), 0, "sgi_ip2_stklmt_w: %04x & %04x\n", data, mem_mask);
341		COMBINE_DATA(&state->m_stklmt);
	349	verboselog(machine(), 0, "sgi_ip2_stklmt_w: %04x & %04x\n", data, mem_mask);
	350	COMBINE_DATA(&m_stklmt);
342	351	}
343	352
344	353	static WRITE8_DEVICE_HANDLER( sgi_kbd_put )
r14844	r14845
373	382	AM_RANGE(0x00000000, 0x00ffffff) AM_RAM AM_BASE(m_mainram)
374	383	AM_RANGE(0x02100000, 0x0210ffff) AM_RAM AM_BASE(m_bss) // ??? I don't understand the need for this...
375	384	AM_RANGE(0x30000000, 0x30017fff) AM_ROM AM_REGION("user1", 0)
376		AM_RANGE(0x30800000, 0x30800003) AM_READWRITE8_LEGACY(sgi_ip2_m_but_r,       sgi_ip2_m_but_w,      0xffffffff)
377		AM_RANGE(0x31000000, 0x31000003) AM_READWRITE16_LEGACY(sgi_ip2_m_quad_r,      sgi_ip2_m_quad_w,      0xffffffff)
378		AM_RANGE(0x31800000, 0x31800003) AM_READ16_LEGACY(sgi_ip2_swtch_r,                              0xffffffff)
	385	AM_RANGE(0x30800000, 0x30800003) AM_READWRITE8(sgi_ip2_m_but_r,       sgi_ip2_m_but_w,      0xffffffff)
	386	AM_RANGE(0x31000000, 0x31000003) AM_READWRITE16(sgi_ip2_m_quad_r,      sgi_ip2_m_quad_w,      0xffffffff)
	387	AM_RANGE(0x31800000, 0x31800003) AM_READ16(sgi_ip2_swtch_r,                              0xffffffff)
379	388	AM_RANGE(0x32000000, 0x3200000f) AM_DEVREADWRITE8_LEGACY("duart68681a",      duart68681_r,      duart68681_w, 0xffffffff)
380	389	AM_RANGE(0x32800000, 0x3280000f) AM_DEVREADWRITE8_LEGACY("duart68681b",      duart68681_r,      duart68681_w, 0xffffffff)
381	390	AM_RANGE(0x33000000, 0x330007ff) AM_RAM
382		AM_RANGE(0x34000000, 0x34000003) AM_READWRITE8_LEGACY(sgi_ip2_clock_ctl_r,    sgi_ip2_clock_ctl_w,   0xffffffff)
383		AM_RANGE(0x35000000, 0x35000003) AM_READWRITE8_LEGACY(sgi_ip2_clock_data_r,   sgi_ip2_clock_data_w,   0xffffffff)
384		AM_RANGE(0x36000000, 0x36000003) AM_READWRITE8_LEGACY(sgi_ip2_os_base_r,      sgi_ip2_os_base_w,      0xffffffff)
385		AM_RANGE(0x38000000, 0x38000003) AM_READWRITE16_LEGACY(sgi_ip2_status_r,      sgi_ip2_status_w,      0xffffffff)
386		AM_RANGE(0x39000000, 0x39000003) AM_READWRITE8_LEGACY(sgi_ip2_parctl_r,      sgi_ip2_parctl_w,      0xffffffff)
387		AM_RANGE(0x3a000000, 0x3a000003) AM_READWRITE8_LEGACY(sgi_ip2_mbp_r,         sgi_ip2_mbp_w,         0xffffffff)
388		AM_RANGE(0x3b000000, 0x3b003fff) AM_READWRITE_LEGACY(sgi_ip2_ptmap_r, sgi_ip2_ptmap_w) AM_BASE(m_ptmap)
389		AM_RANGE(0x3c000000, 0x3c000003) AM_READWRITE16_LEGACY(sgi_ip2_tdbase_r,      sgi_ip2_tdbase_w,      0xffffffff)
390		AM_RANGE(0x3d000000, 0x3d000003) AM_READWRITE16_LEGACY(sgi_ip2_tdlmt_r,      sgi_ip2_tdlmt_w,      0xffffffff)
391		AM_RANGE(0x3e000000, 0x3e000003) AM_READWRITE16_LEGACY(sgi_ip2_stkbase_r,      sgi_ip2_stkbase_w,      0xffffffff)
392		AM_RANGE(0x3f000000, 0x3f000003) AM_READWRITE16_LEGACY(sgi_ip2_stklmt_r,      sgi_ip2_stklmt_w,      0xffffffff)
	391	AM_RANGE(0x34000000, 0x34000003) AM_READWRITE8(sgi_ip2_clock_ctl_r,    sgi_ip2_clock_ctl_w,   0xffffffff)
	392	AM_RANGE(0x35000000, 0x35000003) AM_READWRITE8(sgi_ip2_clock_data_r,   sgi_ip2_clock_data_w,   0xffffffff)
	393	AM_RANGE(0x36000000, 0x36000003) AM_READWRITE8(sgi_ip2_os_base_r,      sgi_ip2_os_base_w,      0xffffffff)
	394	AM_RANGE(0x38000000, 0x38000003) AM_READWRITE16(sgi_ip2_status_r,      sgi_ip2_status_w,      0xffffffff)
	395	AM_RANGE(0x39000000, 0x39000003) AM_READWRITE8(sgi_ip2_parctl_r,      sgi_ip2_parctl_w,      0xffffffff)
	396	AM_RANGE(0x3a000000, 0x3a000003) AM_READWRITE8(sgi_ip2_mbp_r,         sgi_ip2_mbp_w,         0xffffffff)
	397	AM_RANGE(0x3b000000, 0x3b003fff) AM_READWRITE(sgi_ip2_ptmap_r, sgi_ip2_ptmap_w) AM_BASE(m_ptmap)
	398	AM_RANGE(0x3c000000, 0x3c000003) AM_READWRITE16(sgi_ip2_tdbase_r,      sgi_ip2_tdbase_w,      0xffffffff)
	399	AM_RANGE(0x3d000000, 0x3d000003) AM_READWRITE16(sgi_ip2_tdlmt_r,      sgi_ip2_tdlmt_w,      0xffffffff)
	400	AM_RANGE(0x3e000000, 0x3e000003) AM_READWRITE16(sgi_ip2_stkbase_r,      sgi_ip2_stkbase_w,      0xffffffff)
	401	AM_RANGE(0x3f000000, 0x3f000003) AM_READWRITE16(sgi_ip2_stklmt_r,      sgi_ip2_stklmt_w,      0xffffffff)
393	402	ADDRESS_MAP_END
394	403
395	404	/***************************************************************************

src/mess/drivers/ti990_4.c

r14844	r14845
55	55	: driver_device(mconfig, type, tag) { }
56	56
57	57	device_t *m_terminal;
	58	DECLARE_WRITE8_MEMBER(rset_callback);
	59	DECLARE_WRITE8_MEMBER(ckon_ckof_callback);
	60	DECLARE_WRITE8_MEMBER(lrex_callback);
58	61	};
59	62
60	63
r14844	r14845
87	90	}
88	91	#endif
89	92
90		static WRITE8_HANDLER ( rset_callback )
	93	WRITE8_MEMBER(ti990_4_state::rset_callback)
91	94	{
92	95	ti990_cpuboard_reset();
93	96
r14844	r14845
96	99	/* clear controller panel and smi fault LEDs */
97	100	}
98	101
99		static WRITE8_HANDLER ( ckon_ckof_callback )
	102	WRITE8_MEMBER(ti990_4_state::ckon_ckof_callback)
100	103	{
101		device_t *maincpu = space->machine().device("maincpu");
	104	device_t *maincpu = machine().device("maincpu");
102	105	ti990_ckon_ckof_callback(maincpu, (offset & 0x1000) ? 1 : 0);
103	106	}
104	107
105		static WRITE8_HANDLER ( lrex_callback )
	108	WRITE8_MEMBER(ti990_4_state::lrex_callback)
106	109	{
107	110	/* right??? */
108		ti990_hold_load(space->machine());
	111	ti990_hold_load(machine());
109	112	}
110	113
111	114	#if VIDEO_911
r14844	r14845
211	214
212	215	/* external instruction decoding */
213	216	/*  AM_RANGE(0x2000, 0x2fff) AM_WRITE_LEGACY(idle_callback)*/
214		AM_RANGE(0x3000, 0x3fff) AM_WRITE_LEGACY(rset_callback)
215		AM_RANGE(0x5000, 0x6fff) AM_WRITE_LEGACY(ckon_ckof_callback)
216		AM_RANGE(0x7000, 0x7fff) AM_WRITE_LEGACY(lrex_callback)
	217	AM_RANGE(0x3000, 0x3fff) AM_WRITE(rset_callback)
	218	AM_RANGE(0x5000, 0x6fff) AM_WRITE(ckon_ckof_callback)
	219	AM_RANGE(0x7000, 0x7fff) AM_WRITE(lrex_callback)
217	220	ADDRESS_MAP_END
218	221
219	222	#if 0

src/mess/drivers/paso1600.c

r14844	r14845
48	48	struct{
49	49	UINT8 portb;
50	50	}m_keyb;
	51	DECLARE_READ8_MEMBER(pc_dma_read_byte);
	52	DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
51	53	};
52	54
53	55	#define mc6845_h_char_total    (state->m_crtc_vreg[0])
r14844	r14845
296	298	{
297	299	}
298	300
299		static READ8_HANDLER( pc_dma_read_byte )
	301	READ8_MEMBER(paso1600_state::pc_dma_read_byte)
300	302	{
301		//  paso1600_state *state = space->machine().driver_data<paso1600_state>();
302		//offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
	303	//offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
303	304	//  & 0xFF0000;
304	305
305		return space->read_byte(offset);
	306	return space.read_byte(offset);
306	307	}
307	308
308	309
309		static WRITE8_HANDLER( pc_dma_write_byte )
	310	WRITE8_MEMBER(paso1600_state::pc_dma_write_byte)
310	311	{
311		//  paso1600_state *state = space->machine().driver_data<paso1600_state>();
312		//offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
	312	//offs_t page_offset = (((offs_t) m_dma_offset[0][m_dma_channel]) << 16)
313	313	//  & 0xFF0000;
314	314
315		space->write_byte(offset, data);
	315	space.write_byte(offset, data);
316	316	}
317	317
318	318	static I8237_INTERFACE( paso1600_dma8237_interface )
319	319	{
320	320	DEVCB_NULL,
321	321	DEVCB_NULL,
322		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
323		DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
	322	DEVCB_DRIVER_MEMBER(paso1600_state, pc_dma_read_byte),
	323	DEVCB_DRIVER_MEMBER(paso1600_state, pc_dma_write_byte),
324	324	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
325	325	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
326	326	{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }

src/mess/drivers/rvoice.c

r14844	r14845
77	77
78	78	hd63701y0_t m_hd63701y0;
79	79	rvoicepc_t m_rvoicepc;
	80	DECLARE_READ8_MEMBER(main_hd63701_internal_registers_r);
	81	DECLARE_WRITE8_MEMBER(main_hd63701_internal_registers_w);
80	82	};
81	83
82	84
r14844	r14845
126	128	state->m_hd63701y0.P6CSR = 0x00;
127	129	}
128	130
129		static READ8_HANDLER( main_hd63701_internal_registers_r )
	131	READ8_MEMBER(rvoice_state::main_hd63701_internal_registers_r)
130	132	{
131		rvoice_state *state = space->machine().driver_data<rvoice_state>();
132	133	UINT8 data = 0;
133		logerror("main hd637B01Y0: %04x: read from 0x%02X: ", cpu_get_pc(&space->device()), offset);
	134	logerror("main hd637B01Y0: %04x: read from 0x%02X: ", cpu_get_pc(&space.device()), offset);
134	135	switch(offset)
135	136	{
136	137	case 0x00: // Port 1 DDR
r14844	r14845
146	147	return data;
147	148	case 0x02: // Port 1
148	149	logerror("Port 1\n");
149		data = state->m_hd63701y0.PORT1;
	150	data = m_hd63701y0.PORT1;
150	151	break;
151	152	case 0x03: // Port 2
152	153	logerror("Port 2\n");
153		data = state->m_hd63701y0.PORT1;
	154	data = m_hd63701y0.PORT1;
154	155	break;
155	156	case 0x06: // Port 3
156	157	logerror("Port 3\n");
157		data = state->m_hd63701y0.PORT3;
	158	data = m_hd63701y0.PORT3;
158	159	break;
159	160	case 0x07: // Port 4
160	161	logerror("Port 4\n");
161		data = state->m_hd63701y0.PORT4;
	162	data = m_hd63701y0.PORT4;
162	163	break;
163	164	case 0x08: // Timer Control/Status Register 1
164	165	logerror("Timer Control/Status Register 1\n");
165		data = state->m_hd63701y0.TCSR1;
	166	data = m_hd63701y0.TCSR1;
166	167	break;
167	168	case 0x09: // Free Running Counter (MSB)
168	169	logerror("Free Running Counter (MSB)\n");
169		data = state->m_hd63701y0.FRCH;
	170	data = m_hd63701y0.FRCH;
170	171	break;
171	172	case 0x0A: // Free Running Counter (LSB)
172	173	logerror("Free Running Counter (LSB)\n");
173		data = state->m_hd63701y0.FRCL;
	174	data = m_hd63701y0.FRCL;
174	175	break;
175	176	// B C (D E)
176	177	case 0x0F: // Timer Control/Status Register 2
177	178	logerror("Timer Control/Status Register 2\n");
178		data = state->m_hd63701y0.TCSR2;
	179	data = m_hd63701y0.TCSR2;
179	180	break;
180	181	// 10 11 (12)
181	182
182	183	case 0x14: // RAM/Port 5 Control Register
183	184	logerror("RAM/Port 5 Control Register\n");
184		data = state->m_hd63701y0.RP5CR;
	185	data = m_hd63701y0.RP5CR;
185	186	break;
186	187	case 0x15: // Port 5
187	188	logerror("Port 5\n");
188		data = state->m_hd63701y0.PORT5;
	189	data = m_hd63701y0.PORT5;
189	190	break;
190	191	case 0x17: // Port 6
191	192	logerror("Port 6\n");
192		data = state->m_hd63701y0.PORT6;
	193	data = m_hd63701y0.PORT6;
193	194	break;
194	195	case 0x18: // Port 7
195	196	logerror("Port 7\n");
196		data = state->m_hd63701y0.PORT7;
	197	data = m_hd63701y0.PORT7;
197	198	break;
198	199	// 19 1a 1b 1c 1d 1e 1f
199	200	case 0x21: // Port 6 Control/Status Register
200	201	logerror("Port 6 Control/Status Register\n");
201		data = state->m_hd63701y0.P6CSR;
	202	data = m_hd63701y0.P6CSR;
202	203	break;
203	204	default:
204	205	logerror("\n");
r14844	r14845
210	211	}
211	212
212	213
213		static WRITE8_HANDLER( main_hd63701_internal_registers_w )
	214	WRITE8_MEMBER(rvoice_state::main_hd63701_internal_registers_w)
214	215	{
215		rvoice_state *state = space->machine().driver_data<rvoice_state>();
216		logerror("main hd637B01Y0: %04x: write to 0x%02X: ", cpu_get_pc(&space->device()), offset);
	216	logerror("main hd637B01Y0: %04x: write to 0x%02X: ", cpu_get_pc(&space.device()), offset);
217	217	switch(offset)
218	218	{
219	219	case 0x00: // Port 1 DDR
220	220	logerror("Port 1 DDR of %02X\n", data);
221		state->m_hd63701y0.P1DDR = data;
222		state->m_rvoicepc.port1 = (state->m_hd63701y0.PORT1 & state->m_hd63701y0.P1DDR);
	221	m_hd63701y0.P1DDR = data;
	222	m_rvoicepc.port1 = (m_hd63701y0.PORT1 & m_hd63701y0.P1DDR);
223	223	break;
224	224	case 0x01: // Port 2 DDR
225	225	logerror("Port 2 DDR of %02X\n", data);
226		state->m_hd63701y0.P2DDR = data;
227		state->m_rvoicepc.port2 = (state->m_hd63701y0.PORT2 & state->m_hd63701y0.P2DDR);
	226	m_hd63701y0.P2DDR = data;
	227	m_rvoicepc.port2 = (m_hd63701y0.PORT2 & m_hd63701y0.P2DDR);
228	228	break;
229	229	case 0x02: // Port 1
230	230	logerror("Port 1 of %02X\n", data);
231		state->m_hd63701y0.PORT1 = data;
232		state->m_rvoicepc.port1 = (state->m_hd63701y0.PORT1 & state->m_hd63701y0.P1DDR);
	231	m_hd63701y0.PORT1 = data;
	232	m_rvoicepc.port1 = (m_hd63701y0.PORT1 & m_hd63701y0.P1DDR);
233	233	break;
234	234	case 0x03: // Port 2
235	235	logerror("Port 2 of %02X\n", data);
236		state->m_hd63701y0.PORT2 = data;
237		state->m_rvoicepc.port2 = (state->m_hd63701y0.PORT2 & state->m_hd63701y0.P2DDR);
	236	m_hd63701y0.PORT2 = data;
	237	m_rvoicepc.port2 = (m_hd63701y0.PORT2 & m_hd63701y0.P2DDR);
238	238	break;
239	239	case 0x04: // Port 3 DDR
240	240	logerror("Port 3 DDR of %02X\n", data);
241		state->m_hd63701y0.P3DDR = data;
242		state->m_rvoicepc.port3 = (state->m_hd63701y0.PORT3 & state->m_hd63701y0.P3DDR);
	241	m_hd63701y0.P3DDR = data;
	242	m_rvoicepc.port3 = (m_hd63701y0.PORT3 & m_hd63701y0.P3DDR);
243	243	break;
244	244	case 0x05: // Port 4 DDR
245	245	logerror("Port 4 DDR of %02X\n", data);
246		state->m_hd63701y0.P4DDR = data;
247		state->m_rvoicepc.port4 = (state->m_hd63701y0.PORT4 & state->m_hd63701y0.P4DDR);
	246	m_hd63701y0.P4DDR = data;
	247	m_rvoicepc.port4 = (m_hd63701y0.PORT4 & m_hd63701y0.P4DDR);
248	248	break;
249	249	case 0x06: // Port 3
250	250	logerror("Port 3 of %02X\n", data);
251		state->m_hd63701y0.PORT3 = data;
252		state->m_rvoicepc.port3 = (state->m_hd63701y0.PORT3 & state->m_hd63701y0.P3DDR);
	251	m_hd63701y0.PORT3 = data;
	252	m_rvoicepc.port3 = (m_hd63701y0.PORT3 & m_hd63701y0.P3DDR);
253	253	break;
254	254	case 0x07: // Port 4
255	255	logerror("Port 4 of %02X\n", data);
256		state->m_hd63701y0.PORT4 = data;
257		state->m_rvoicepc.port4 = (state->m_hd63701y0.PORT4 & state->m_hd63701y0.P4DDR);
	256	m_hd63701y0.PORT4 = data;
	257	m_rvoicepc.port4 = (m_hd63701y0.PORT4 & m_hd63701y0.P4DDR);
258	258	break;
259	259	case 0x08: // Timer Control/Status Register 1
260	260	logerror("Timer Control/Status Register 1 of %02X\n", data);
261		state->m_hd63701y0.TCSR1 = data;
	261	m_hd63701y0.TCSR1 = data;
262	262	break;
263	263	case 0x09: // Free Running Counter (MSB)
264	264	logerror("Free Running Counter (MSB) of %02X\n", data);
265		state->m_hd63701y0.FRCH = data;
	265	m_hd63701y0.FRCH = data;
266	266	break;
267	267	case 0x0A: // Free Running Counter (LSB)
268	268	logerror("Free Running Counter (LSB) of %02X\n", data);
269		state->m_hd63701y0.FRCL = data;
	269	m_hd63701y0.FRCL = data;
270	270	break;
271	271	// B C (D E)
272	272	case 0x0F: // Timer Control/Status Register 2
273	273	logerror("Timer Control/Status Register 2 of %02X\n", data);
274		state->m_hd63701y0.TCSR2 = data;
	274	m_hd63701y0.TCSR2 = data;
275	275	break;
276	276	// 10 11 (12)
277	277	case 0x13: // TxD Register
278	278	logerror("TxD Register of %02X\n", data);
279		state->m_hd63701y0.TDR = data;
	279	m_hd63701y0.TDR = data;
280	280	break;
281	281	case 0x14: // RAM/Port 5 Control Register
282	282	logerror("RAM/Port 5 Control Register of %02X\n", data);
283		state->m_hd63701y0.RP5CR = data;
	283	m_hd63701y0.RP5CR = data;
284	284	break;
285	285	case 0x15: // Port 5
286	286	logerror("Port 5 of %02X\n", data);
287		state->m_hd63701y0.PORT5 = data;
288		state->m_rvoicepc.port5 = (state->m_hd63701y0.PORT5 & state->m_hd63701y0.P5DDR);
	287	m_hd63701y0.PORT5 = data;
	288	m_rvoicepc.port5 = (m_hd63701y0.PORT5 & m_hd63701y0.P5DDR);
289	289	break;
290	290	case 0x16: // Port 6 DDR
291	291	logerror("Port 6 DDR of %02X\n", data);
292		state->m_hd63701y0.P6DDR = data;
293		state->m_rvoicepc.port6 = (state->m_hd63701y0.PORT6 & state->m_hd63701y0.P6DDR);
	292	m_hd63701y0.P6DDR = data;
	293	m_rvoicepc.port6 = (m_hd63701y0.PORT6 & m_hd63701y0.P6DDR);
294	294	break;
295	295	case 0x17: // Port 6
296	296	logerror("Port 6 of %02X\n", data);
297		state->m_hd63701y0.PORT6 = data;
298		state->m_rvoicepc.port6 = (state->m_hd63701y0.PORT6 & state->m_hd63701y0.P6DDR);
	297	m_hd63701y0.PORT6 = data;
	298	m_rvoicepc.port6 = (m_hd63701y0.PORT6 & m_hd63701y0.P6DDR);
299	299	break;
300	300	case 0x18: // Port 7
301	301	logerror("Port 7 of %02X\n", data);
302		state->m_hd63701y0.PORT7 = data;
303		state->m_rvoicepc.port7 = data;
	302	m_hd63701y0.PORT7 = data;
	303	m_rvoicepc.port7 = data;
304	304	break;
305	305	// 19 1a 1b 1c 1d 1e 1f
306	306	case 0x20: // Port 5 DDR
307	307	logerror("Port 5 DDR of %02X\n", data);
308		state->m_hd63701y0.P5DDR = data;
309		state->m_rvoicepc.port5 = (state->m_hd63701y0.PORT5 & state->m_hd63701y0.P5DDR);
	308	m_hd63701y0.P5DDR = data;
	309	m_rvoicepc.port5 = (m_hd63701y0.PORT5 & m_hd63701y0.P5DDR);
310	310	break;
311	311	case 0x21: // Port 6 Control/Status Register
312	312	logerror("Port 6 Control/Status Register of %02X\n", data);
313		state->m_hd63701y0.P6CSR = data;
	313	m_hd63701y0.P6CSR = data;
314	314	break;
315	315	default:
316	316	logerror("with data of %02X\n", data);
r14844	r14845
325	325
326	326	static ADDRESS_MAP_START(hd63701_main_mem, AS_PROGRAM, 8, rvoice_state )
327	327	ADDRESS_MAP_UNMAP_HIGH
328		AM_RANGE(0x0000, 0x0027) AM_READWRITE_LEGACY(main_hd63701_internal_registers_r, main_hd63701_internal_registers_w) // INTERNAL REGS
	328	AM_RANGE(0x0000, 0x0027) AM_READWRITE(main_hd63701_internal_registers_r, main_hd63701_internal_registers_w) // INTERNAL REGS
329	329	AM_RANGE(0x0040, 0x013f) AM_RAM // INTERNAL RAM (overlaps acia)
330	330	AM_RANGE(0x0060, 0x007f) AM_DEVREADWRITE("acia65c51", acia6551_device, read, write) // ACIA 65C51
331	331	AM_RANGE(0x2000, 0x7fff) AM_RAM // EXTERNAL SRAM

src/mess/drivers/px4.c

r14844	r14845
56	56	MACROS
57	57	***************************************************************************/
58	58
59		#define ART_TX_ENABLED   (BIT(px4->m_artcr, 0))
	59	#define ART_TX_ENABLED   (BIT(m_artcr, 0))
60	60	#define ART_RX_ENABLED   (BIT(px4->m_artcr, 2))
61	61
62	62	#define ART_DATA      (BIT(px4->m_artmr, 2))   /* number of data bits, 7 or 8 */
r14844	r14845
128	128	/* external devices */
129	129	device_t *m_sio_device;
130	130	device_t *m_rs232c_device;
	131	DECLARE_READ8_MEMBER(px4_icrlc_r);
	132	DECLARE_WRITE8_MEMBER(px4_ctrl1_w);
	133	DECLARE_READ8_MEMBER(px4_icrhc_r);
	134	DECLARE_WRITE8_MEMBER(px4_cmdr_w);
	135	DECLARE_READ8_MEMBER(px4_icrlb_r);
	136	DECLARE_WRITE8_MEMBER(px4_ctrl2_w);
	137	DECLARE_READ8_MEMBER(px4_icrhb_r);
	138	DECLARE_READ8_MEMBER(px4_isr_r);
	139	DECLARE_WRITE8_MEMBER(px4_ier_w);
	140	DECLARE_READ8_MEMBER(px4_str_r);
	141	DECLARE_WRITE8_MEMBER(px4_bankr_w);
	142	DECLARE_READ8_MEMBER(px4_sior_r);
	143	DECLARE_WRITE8_MEMBER(px4_sior_w);
	144	DECLARE_WRITE8_MEMBER(px4_vadr_w);
	145	DECLARE_WRITE8_MEMBER(px4_yoff_w);
	146	DECLARE_WRITE8_MEMBER(px4_fr_w);
	147	DECLARE_WRITE8_MEMBER(px4_spur_w);
	148	DECLARE_READ8_MEMBER(px4_ctgif_r);
	149	DECLARE_WRITE8_MEMBER(px4_ctgif_w);
	150	DECLARE_READ8_MEMBER(px4_artdir_r);
	151	DECLARE_WRITE8_MEMBER(px4_artdor_w);
	152	DECLARE_READ8_MEMBER(px4_artsr_r);
	153	DECLARE_WRITE8_MEMBER(px4_artmr_w);
	154	DECLARE_READ8_MEMBER(px4_iostr_r);
	155	DECLARE_WRITE8_MEMBER(px4_artcr_w);
	156	DECLARE_WRITE8_MEMBER(px4_swr_w);
	157	DECLARE_WRITE8_MEMBER(px4_ioctlr_w);
	158	DECLARE_WRITE8_MEMBER(px4_ramdisk_address_w);
	159	DECLARE_READ8_MEMBER(px4_ramdisk_data_r);
	160	DECLARE_WRITE8_MEMBER(px4_ramdisk_data_w);
	161	DECLARE_READ8_MEMBER(px4_ramdisk_control_r);
131	162	};
132	163
133	164
r14844	r14845
317	348	}
318	349
319	350	/* input capture register low command trigger */
320		static READ8_HANDLER( px4_icrlc_r )
	351	READ8_MEMBER(px4_state::px4_icrlc_r)
321	352	{
322		px4_state *px4 = space->machine().driver_data<px4_state>();
323	353
324	354	if (VERBOSE)
325		logerror("%s: px4_icrlc_r\n", space->machine().describe_context());
	355	logerror("%s: px4_icrlc_r\n", machine().describe_context());
326	356
327	357	/* latch value */
328		px4->m_frc_latch = px4->m_frc_value;
	358	m_frc_latch = m_frc_value;
329	359
330		return px4->m_frc_latch & 0xff;
	360	return m_frc_latch & 0xff;
331	361	}
332	362
333	363	/* control register 1 */
334		static WRITE8_HANDLER( px4_ctrl1_w )
	364	WRITE8_MEMBER(px4_state::px4_ctrl1_w)
335	365	{
336		px4_state *px4 = space->machine().driver_data<px4_state>();
337	366	int baud;
338	367
339	368	if (VERBOSE)
340		logerror("%s: px4_ctrl1_w (0x%02x)\n", space->machine().describe_context(), data);
	369	logerror("%s: px4_ctrl1_w (0x%02x)\n", machine().describe_context(), data);
341	370
342	371	/* baudrate generator */
343	372	baud = data >> 4;
344	373
345	374	if (baud <= 12)
346	375	{
347		px4->m_transmit_timer->adjust(attotime::zero, 0, attotime::from_hz(XTAL_7_3728MHz/2/transmit_rate[baud]));
348		px4->m_receive_timer->adjust(attotime::zero, 0, attotime::from_hz(XTAL_7_3728MHz/2/receive_rate[baud]));
	376	m_transmit_timer->adjust(attotime::zero, 0, attotime::from_hz(XTAL_7_3728MHz/2/transmit_rate[baud]));
	377	m_receive_timer->adjust(attotime::zero, 0, attotime::from_hz(XTAL_7_3728MHz/2/receive_rate[baud]));
349	378	}
350	379
351		px4->m_ctrl1 = data;
	380	m_ctrl1 = data;
352	381	}
353	382
354	383	/* input capture register high command trigger */
355		static READ8_HANDLER( px4_icrhc_r )
	384	READ8_MEMBER(px4_state::px4_icrhc_r)
356	385	{
357		px4_state *px4 = space->machine().driver_data<px4_state>();
358	386
359	387	if (VERBOSE)
360		logerror("%s: px4_icrhc_r\n", space->machine().describe_context());
	388	logerror("%s: px4_icrhc_r\n", machine().describe_context());
361	389
362		return (px4->m_frc_latch >> 8) & 0xff;
	390	return (m_frc_latch >> 8) & 0xff;
363	391	}
364	392
365	393	/* command register */
366		static WRITE8_HANDLER( px4_cmdr_w )
	394	WRITE8_MEMBER(px4_state::px4_cmdr_w)
367	395	{
368		px4_state *px4 = space->machine().driver_data<px4_state>();
369	396
370	397	if (VERBOSE)
371		logerror("%s: px4_cmdr_w (0x%02x)\n", space->machine().describe_context(), data);
	398	logerror("%s: px4_cmdr_w (0x%02x)\n", machine().describe_context(), data);
372	399
373	400	/* clear overflow interrupt? */
374	401	if (BIT(data, 2))
375	402	{
376		px4->m_isr &= ~INT3_OVF;
377		gapnit_interrupt(space->machine());
	403	m_isr &= ~INT3_OVF;
	404	gapnit_interrupt(machine());
378	405	}
379	406	}
380	407
381	408	/* input capture register low barcode trigger */
382		static READ8_HANDLER( px4_icrlb_r )
	409	READ8_MEMBER(px4_state::px4_icrlb_r)
383	410	{
384		px4_state *px4 = space->machine().driver_data<px4_state>();
385	411
386	412	if (VERBOSE)
387		logerror("%s: px4_icrlb_r\n", space->machine().describe_context());
	413	logerror("%s: px4_icrlb_r\n", machine().describe_context());
388	414
389		return px4->m_icrb & 0xff;
	415	return m_icrb & 0xff;
390	416	}
391	417
392	418	/* control register 2 */
393		static WRITE8_HANDLER( px4_ctrl2_w )
	419	WRITE8_MEMBER(px4_state::px4_ctrl2_w)
394	420	{
395		px4_state *px4 = space->machine().driver_data<px4_state>();
396	421
397	422	if (VERBOSE)
398		logerror("%s: px4_ctrl2_w (0x%02x)\n", space->machine().describe_context(), data);
	423	logerror("%s: px4_ctrl2_w (0x%02x)\n", machine().describe_context(), data);
399	424
400	425	/* bit 0, MIC, cassette output */
401		px4->m_ext_cas->output( BIT(data, 0) ? -1.0 : +1.0);
	426	m_ext_cas->output( BIT(data, 0) ? -1.0 : +1.0);
402	427
403	428	/* bit 1, RMT, cassette motor */
404	429	if (BIT(data, 1))
405	430	{
406		px4->m_ext_cas->change_state(CASSETTE_MOTOR_ENABLED,CASSETTE_MASK_MOTOR);
407		px4->m_ext_cas_timer->adjust(attotime::zero, 0, attotime::from_hz(44100));
	431	m_ext_cas->change_state(CASSETTE_MOTOR_ENABLED,CASSETTE_MASK_MOTOR);
	432	m_ext_cas_timer->adjust(attotime::zero, 0, attotime::from_hz(44100));
408	433	}
409	434	else
410	435	{
411		px4->m_ext_cas->change_state(CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
412		px4->m_ext_cas_timer->adjust(attotime::zero);
	436	m_ext_cas->change_state(CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
	437	m_ext_cas_timer->adjust(attotime::zero);
413	438	}
414	439	}
415	440
416	441	/* input capture register high barcode trigger */
417		static READ8_HANDLER( px4_icrhb_r )
	442	READ8_MEMBER(px4_state::px4_icrhb_r)
418	443	{
419		px4_state *px4 = space->machine().driver_data<px4_state>();
420	444
421	445	if (VERBOSE)
422		logerror("%s: px4_icrhb_r\n", space->machine().describe_context());
	446	logerror("%s: px4_icrhb_r\n", machine().describe_context());
423	447
424	448	/* clear icf interrupt */
425		px4->m_isr &= ~INT2_ICF;
426		gapnit_interrupt(space->machine());
	449	m_isr &= ~INT2_ICF;
	450	gapnit_interrupt(machine());
427	451
428		return (px4->m_icrb >> 8) & 0xff;
	452	return (m_icrb >> 8) & 0xff;
429	453	}
430	454
431	455	/* interrupt status register */
432		static READ8_HANDLER( px4_isr_r )
	456	READ8_MEMBER(px4_state::px4_isr_r)
433	457	{
434		px4_state *px4 = space->machine().driver_data<px4_state>();
435	458
436	459	if (VERBOSE)
437		logerror("%s: px4_isr_r\n", space->machine().describe_context());
	460	logerror("%s: px4_isr_r\n", machine().describe_context());
438	461
439		return px4->m_isr;
	462	return m_isr;
440	463	}
441	464
442	465	/* interrupt enable register */
443		static WRITE8_HANDLER( px4_ier_w )
	466	WRITE8_MEMBER(px4_state::px4_ier_w)
444	467	{
445		px4_state *px4 = space->machine().driver_data<px4_state>();
446	468
447	469	if (VERBOSE)
448		logerror("%s: px4_ier_w (0x%02x)\n", space->machine().describe_context(), data);
	470	logerror("%s: px4_ier_w (0x%02x)\n", machine().describe_context(), data);
449	471
450		px4->m_ier = data;
451		gapnit_interrupt(space->machine());
	472	m_ier = data;
	473	gapnit_interrupt(machine());
452	474	}
453	475
454	476	/* status register */
455		static READ8_HANDLER( px4_str_r )
	477	READ8_MEMBER(px4_state::px4_str_r)
456	478	{
457		px4_state *px4 = space->machine().driver_data<px4_state>();
458	479	UINT8 result = 0;
459	480
460	481	if (VERBOSE)
461		logerror("%s: px4_str_r\n", space->machine().describe_context());
	482	logerror("%s: px4_str_r\n", machine().describe_context());
462	483
463		result |= (px4->m_ext_cas)->input() > 0 ? 1 : 0;
	484	result |= (m_ext_cas)->input() > 0 ? 1 : 0;
464	485	result |= 1 << 1;   /* BCRD, barcode reader input */
465	486	result |= 1 << 2;   /* RDY signal from 7805 */
466	487	result |= 1 << 3;   /* RDYSIO, enable access to the 7805 */
467		result |= px4->m_bankr & 0xf0;   /* bit 4-7, BANK - memory bank */
	488	result |= m_bankr & 0xf0;   /* bit 4-7, BANK - memory bank */
468	489
469	490	return result;
470	491	}
r14844	r14845
497	518	}
498	519
499	520	/* bank register */
500		static WRITE8_HANDLER( px4_bankr_w )
	521	WRITE8_MEMBER(px4_state::px4_bankr_w)
501	522	{
502		px4_state *px4 = space->machine().driver_data<px4_state>();
503		address_space *space_program = space->machine().device("maincpu")->memory().space(AS_PROGRAM);
	523	address_space *space_program = machine().device("maincpu")->memory().space(AS_PROGRAM);
504	524
505	525	if (VERBOSE)
506		logerror("%s: px4_bankr_w (0x%02x)\n", space->machine().describe_context(), data);
	526	logerror("%s: px4_bankr_w (0x%02x)\n", machine().describe_context(), data);
507	527
508		px4->m_bankr = data;
	528	m_bankr = data;
509	529
510	530	/* bank switch */
511	531	switch (data >> 4)
r14844	r14845
514	534	/* system bank */
515	535	space_program->install_read_bank(0x0000, 0x7fff, "bank1");
516	536	space_program->nop_write(0x0000, 0x7fff);
517		memory_set_bankptr(space->machine(), "bank1", space->machine().region("os")->base());
	537	memory_set_bankptr(machine(), "bank1", machine().region("os")->base());
518	538	space_program->install_readwrite_bank(0x8000, 0xffff, "bank2");
519		memory_set_bankptr(space->machine(), "bank2", px4->m_ram->pointer() + 0x8000);
	539	memory_set_bankptr(machine(), "bank2", m_ram->pointer() + 0x8000);
520	540	break;
521	541
522	542	case 0x04:
523	543	/* memory */
524	544	space_program->install_readwrite_bank(0x0000, 0xffff, "bank1");
525		memory_set_bankptr(space->machine(), "bank1", px4->m_ram->pointer());
	545	memory_set_bankptr(machine(), "bank1", m_ram->pointer());
526	546	break;
527	547
528	548	case 0x08: install_rom_capsule(space_program, 0x2000, "capsule1"); break;
r14844	r14845
540	560	}
541	561
542	562	/* serial io register */
543		static READ8_HANDLER( px4_sior_r )
	563	READ8_MEMBER(px4_state::px4_sior_r)
544	564	{
545		px4_state *px4 = space->machine().driver_data<px4_state>();
546	565
547	566	if (VERBOSE)
548		logerror("%s: px4_sior_r 0x%02x\n", space->machine().describe_context(), px4->m_sior);
	567	logerror("%s: px4_sior_r 0x%02x\n", machine().describe_context(), m_sior);
549	568
550		return px4->m_sior;
	569	return m_sior;
551	570	}
552	571
553	572	/* serial io register */
554		static WRITE8_HANDLER( px4_sior_w )
	573	WRITE8_MEMBER(px4_state::px4_sior_w)
555	574	{
556		px4_state *px4 = space->machine().driver_data<px4_state>();
557	575
558	576	if (VERBOSE)
559		logerror("%s: px4_sior_w (0x%02x)\n", space->machine().describe_context(), data);
	577	logerror("%s: px4_sior_w (0x%02x)\n", machine().describe_context(), data);
560	578
561		px4->m_sior = data;
	579	m_sior = data;
562	580
563	581	switch (data)
564	582	{
r14844	r14845
574	592	if (VERBOSE)
575	593	logerror("7508 cmd: Read Status\n");
576	594
577		if (px4->m_interrupt_status != 0)
	595	if (m_interrupt_status != 0)
578	596	{
579	597	if (VERBOSE)
580		logerror("> 7508 has interrupts pending: 0x%02x\n", px4->m_interrupt_status);
	598	logerror("> 7508 has interrupts pending: 0x%02x\n", m_interrupt_status);
581	599
582	600	/* signal the interrupt(s) */
583		px4->m_sior = 0xc1 | px4->m_interrupt_status;
584		px4->m_interrupt_status = 0x00;
	601	m_sior = 0xc1 | m_interrupt_status;
	602	m_interrupt_status = 0x00;
585	603	}
586		else if (px4->m_key_status != 0xff)
	604	else if (m_key_status != 0xff)
587	605	{
588		px4->m_sior = px4->m_key_status;
589		px4->m_key_status = 0xff;
	606	m_sior = m_key_status;
	607	m_key_status = 0xff;
590	608	}
591	609	else
592	610	{
593	611	/* nothing happenend */
594		px4->m_sior = 0xbf;
	612	m_sior = 0xbf;
595	613	}
596	614
597	615	break;
r14844	r14845
609	627	if (VERBOSE)
610	628	logerror("7508 cmd: KB Interrupt OFF\n");
611	629
612		px4->m_key_int_enabled = FALSE;
	630	m_key_int_enabled = FALSE;
613	631	break;
614	632
615	633	case 0x16:
r14844	r14845
617	635	if (VERBOSE)
618	636	logerror("7508 cmd: KB Interrupt ON\n");
619	637
620		px4->m_key_int_enabled = TRUE;
	638	m_key_int_enabled = TRUE;
621	639	break;
622	640
623	641	case 0x07: if (VERBOSE) logerror("7508 cmd: Clock Read\n"); break;
r14844	r14845
629	647	logerror("7508 cmd: Power Switch Read\n");
630	648
631	649	/* indicate that the power switch is in the "ON" position */
632		px4->m_sior = 0x01;
	650	m_sior = 0x01;
633	651	break;
634	652
635	653	case 0x09: if (VERBOSE) logerror("7508 cmd: Alarm Read\n"); break;
r14844	r14845
641	659
642	660	if (VERBOSE)
643	661	logerror("7508 cmd: DIP Switch Read\n");
644		px4->m_sior = input_port_read(space->machine(), "dips");
	662	m_sior = input_port_read(machine(), "dips");
645	663	break;
646	664
647	665	case 0x0b: if (VERBOSE) logerror("7508 cmd: Stop Key Interrupt disable\n"); break;
r14844	r14845
654	672	if (VERBOSE)
655	673	logerror("7508 cmd: 1 sec. Interrupt OFF\n");
656	674
657		px4->m_one_sec_int_enabled = FALSE;
	675	m_one_sec_int_enabled = FALSE;
658	676	break;
659	677
660	678	case 0x1d:
r14844	r14845
662	680	if (VERBOSE)
663	681	logerror("7508 cmd: 1 sec. Interrupt ON\n");
664	682
665		px4->m_one_sec_int_enabled = TRUE;
	683	m_one_sec_int_enabled = TRUE;
666	684	break;
667	685
668	686	case 0x0e:
r14844	r14845
670	688	if (VERBOSE)
671	689	logerror("7508 cmd: KB Clear\n");
672	690
673		px4->m_sior = 0xbf;
	691	m_sior = 0xbf;
674	692	break;
675	693
676	694	case 0x0f: if (VERBOSE) logerror("7508 cmd: System Reset\n"); break;
r14844	r14845
683	701	***************************************************************************/
684	702
685	703	/* vram start address register */
686		static WRITE8_HANDLER( px4_vadr_w )
	704	WRITE8_MEMBER(px4_state::px4_vadr_w)
687	705	{
688		px4_state *px4 = space->machine().driver_data<px4_state>();
689	706
690	707	if (VERBOSE)
691		logerror("%s: px4_vadr_w (0x%02x)\n", space->machine().describe_context(), data);
	708	logerror("%s: px4_vadr_w (0x%02x)\n", machine().describe_context(), data);
692	709
693		px4->m_vadr = data;
	710	m_vadr = data;
694	711	}
695	712
696	713	/* y offset register */
697		static WRITE8_HANDLER( px4_yoff_w )
	714	WRITE8_MEMBER(px4_state::px4_yoff_w)
698	715	{
699		px4_state *px4 = space->machine().driver_data<px4_state>();
700	716
701	717	if (VERBOSE)
702		logerror("%s: px4_yoff_w (0x%02x)\n", space->machine().describe_context(), data);
	718	logerror("%s: px4_yoff_w (0x%02x)\n", machine().describe_context(), data);
703	719
704		px4->m_yoff = data;
	720	m_yoff = data;
705	721	}
706	722
707	723	/* frame register */
708		static WRITE8_HANDLER( px4_fr_w )
	724	WRITE8_MEMBER(px4_state::px4_fr_w)
709	725	{
710	726	if (VERBOSE)
711		logerror("%s: px4_fr_w (0x%02x)\n", space->machine().describe_context(), data);
	727	logerror("%s: px4_fr_w (0x%02x)\n", machine().describe_context(), data);
712	728	}
713	729
714	730	/* speed-up register */
715		static WRITE8_HANDLER( px4_spur_w )
	731	WRITE8_MEMBER(px4_state::px4_spur_w)
716	732	{
717	733	if (VERBOSE)
718		logerror("%s: px4_spur_w (0x%02x)\n", space->machine().describe_context(), data);
	734	logerror("%s: px4_spur_w (0x%02x)\n", machine().describe_context(), data);
719	735	}
720	736
721	737
r14844	r14845
727	743	{
728	744	px4_state *px4 = machine.driver_data<px4_state>();
729	745
730		if (ART_TX_ENABLED)
	746	if (BIT(px4->m_artcr, 0))// ART_TX_ENABLED
731	747	{
732	748
733	749	}
r14844	r14845
744	760	}
745	761
746	762	/* cartridge interface */
747		static READ8_HANDLER( px4_ctgif_r )
	763	READ8_MEMBER(px4_state::px4_ctgif_r)
748	764	{
749	765	if (VERBOSE)
750		logerror("%s: px4_ctgif_r @ 0x%02x\n", space->machine().describe_context(), offset);
	766	logerror("%s: px4_ctgif_r @ 0x%02x\n", machine().describe_context(), offset);
751	767
752	768	return 0xff;
753	769	}
754	770
755	771	/* cartridge interface */
756		static WRITE8_HANDLER( px4_ctgif_w )
	772	WRITE8_MEMBER(px4_state::px4_ctgif_w)
757	773	{
758	774	if (VERBOSE)
759		logerror("%s: px4_ctgif_w (0x%02x @ 0x%02x)\n", space->machine().describe_context(), data, offset);
	775	logerror("%s: px4_ctgif_w (0x%02x @ 0x%02x)\n", machine().describe_context(), data, offset);
760	776	}
761	777
762	778	/* art data input register */
763		static READ8_HANDLER( px4_artdir_r )
	779	READ8_MEMBER(px4_state::px4_artdir_r)
764	780	{
765		px4_state *px4 = space->machine().driver_data<px4_state>();
766	781
767	782	if (VERBOSE)
768		logerror("%s: px4_artdir_r\n", space->machine().describe_context());
	783	logerror("%s: px4_artdir_r\n", machine().describe_context());
769	784
770		return px4->m_artdir;
	785	return m_artdir;
771	786	}
772	787
773	788	/* art data output register */
774		static WRITE8_HANDLER( px4_artdor_w )
	789	WRITE8_MEMBER(px4_state::px4_artdor_w)
775	790	{
776		px4_state *px4 = space->machine().driver_data<px4_state>();
777	791
778	792	if (VERBOSE)
779		logerror("%s: px4_artdor_w (0x%02x)\n", space->machine().describe_context(), data);
	793	logerror("%s: px4_artdor_w (0x%02x)\n", machine().describe_context(), data);
780	794
781	795	/* clear ready */
782		px4->m_artsr &= ~ART_TXRDY;
	796	m_artsr &= ~ART_TXRDY;
783	797
784		px4->m_artdor = data;
	798	m_artdor = data;
785	799	}
786	800
787	801	/* art status register */
788		static READ8_HANDLER( px4_artsr_r )
	802	READ8_MEMBER(px4_state::px4_artsr_r)
789	803	{
790		px4_state *px4 = space->machine().driver_data<px4_state>();
791	804	UINT8 result = 0;
792	805
793	806	if (VERBOSE)
794		logerror("%s: px4_artsr_r\n", space->machine().describe_context());
	807	logerror("%s: px4_artsr_r\n", machine().describe_context());
795	808
796		result |= px4_rs232c_dsr(px4->m_rs232c_device) << 7;
	809	result |= px4_rs232c_dsr(m_rs232c_device) << 7;
797	810
798		return result | px4->m_artsr;
	811	return result | m_artsr;
799	812	}
800	813
801	814	/* art mode register */
802		static WRITE8_HANDLER( px4_artmr_w )
	815	WRITE8_MEMBER(px4_state::px4_artmr_w)
803	816	{
804		px4_state *px4 = space->machine().driver_data<px4_state>();
805	817
806	818	if (VERBOSE)
807		logerror("%s: px4_artmr_w (0x%02x)\n", space->machine().describe_context(), data);
	819	logerror("%s: px4_artmr_w (0x%02x)\n", machine().describe_context(), data);
808	820
809		px4->m_artmr = data;
	821	m_artmr = data;
810	822	}
811	823
812	824	/* io status register */
813		static READ8_HANDLER( px4_iostr_r )
	825	READ8_MEMBER(px4_state::px4_iostr_r)
814	826	{
815		px4_state *px4 = space->machine().driver_data<px4_state>();
816	827	UINT8 result = 0;
817	828
818	829	if (VERBOSE)
819		logerror("%s: px4_iostr_r\n", space->machine().describe_context());
	830	logerror("%s: px4_iostr_r\n", machine().describe_context());
820	831
821		result |= px4->m_centronics->busy_r() << 0;
822		result |= !px4->m_centronics->pe_r() << 1;
823		result |= px4_sio_pin(px4->m_sio_device) << 2;
824		result |= px4_sio_rxd(px4->m_sio_device) << 3;
825		result |= px4_rs232c_dcd(px4->m_rs232c_device) << 4;
826		result |= px4_rs232c_cts(px4->m_rs232c_device) << 5;
	832	result |= m_centronics->busy_r() << 0;
	833	result |= !m_centronics->pe_r() << 1;
	834	result |= px4_sio_pin(m_sio_device) << 2;
	835	result |= px4_sio_rxd(m_sio_device) << 3;
	836	result |= px4_rs232c_dcd(m_rs232c_device) << 4;
	837	result |= px4_rs232c_cts(m_rs232c_device) << 5;
827	838	result |= 1 << 6;   /* bit 6, csel, cartridge option select signal, set to 'other mode' */
828	839	result |= 0 << 7;   /* bit 7, caud - audio input from cartridge */
829	840
r14844	r14845
831	842	}
832	843
833	844	/* art command register */
834		static WRITE8_HANDLER( px4_artcr_w )
	845	WRITE8_MEMBER(px4_state::px4_artcr_w)
835	846	{
836		px4_state *px4 = space->machine().driver_data<px4_state>();
837	847
838	848	if (VERBOSE)
839		logerror("%s: px4_artcr_w (0x%02x)\n", space->machine().describe_context(), data);
	849	logerror("%s: px4_artcr_w (0x%02x)\n", machine().describe_context(), data);
840	850
841		px4->m_artcr = data;
	851	m_artcr = data;
842	852
843	853	/* bit 0, txe - transmit enable */
844	854	if (!ART_TX_ENABLED)
845	855	{
846	856	/* force high when disabled */
847		px4_sio_txd(px4->m_sio_device, ASSERT_LINE);
848		px4_rs232c_txd(px4->m_rs232c_device, ASSERT_LINE);
	857	px4_sio_txd(m_sio_device, ASSERT_LINE);
	858	px4_rs232c_txd(m_rs232c_device, ASSERT_LINE);
849	859	}
850	860
851	861	/* bit 3, sbrk - break output */
852	862	if (ART_TX_ENABLED && BIT(data, 3))
853	863	{
854	864	/* force low when enabled and transmit enabled */
855		px4_sio_txd(px4->m_sio_device, CLEAR_LINE);
856		px4_rs232c_txd(px4->m_rs232c_device, CLEAR_LINE);
	865	px4_sio_txd(m_sio_device, CLEAR_LINE);
	866	px4_rs232c_txd(m_rs232c_device, CLEAR_LINE);
857	867	}
858	868
859	869	/* error reset */
860	870	if (BIT(data, 4))
861		px4->m_artsr &= ~(ART_PE | ART_OE | ART_FE);
	871	m_artsr &= ~(ART_PE | ART_OE | ART_FE);
862	872
863		px4_rs232c_dtr(px4->m_rs232c_device, BIT(data, 1));
864		px4_rs232c_rts(px4->m_rs232c_device, BIT(data, 5));
	873	px4_rs232c_dtr(m_rs232c_device, BIT(data, 1));
	874	px4_rs232c_rts(m_rs232c_device, BIT(data, 5));
865	875	}
866	876
867	877	/* switch register */
868		static WRITE8_HANDLER( px4_swr_w )
	878	WRITE8_MEMBER(px4_state::px4_swr_w)
869	879	{
870		px4_state *px4 = space->machine().driver_data<px4_state>();
871	880
872	881	if (VERBOSE)
873		logerror("%s: px4_swr_w (0x%02x)\n", space->machine().describe_context(), data);
	882	logerror("%s: px4_swr_w (0x%02x)\n", machine().describe_context(), data);
874	883
875		px4->m_swr = data;
	884	m_swr = data;
876	885	}
877	886
878	887	/* io control register */
879		static WRITE8_HANDLER( px4_ioctlr_w )
	888	WRITE8_MEMBER(px4_state::px4_ioctlr_w)
880	889	{
881		px4_state *px4 = space->machine().driver_data<px4_state>();
882	890
883	891	if (VERBOSE)
884		logerror("%s: px4_ioctlr_w (0x%02x)\n", space->machine().describe_context(), data);
	892	logerror("%s: px4_ioctlr_w (0x%02x)\n", machine().describe_context(), data);
885	893
886		px4->m_centronics->strobe_w(!BIT(data, 0));
887		px4->m_centronics->init_prime_w(BIT(data, 1));
	894	m_centronics->strobe_w(!BIT(data, 0));
	895	m_centronics->init_prime_w(BIT(data, 1));
888	896
889		px4_sio_pout(px4->m_sio_device, BIT(data, 2));
	897	px4_sio_pout(m_sio_device, BIT(data, 2));
890	898
891	899	/* bit 3, cartridge reset */
892	900
r14844	r14845
962	970	EXTERNAL RAM-DISK
963	971	***************************************************************************/
964	972
965		static WRITE8_HANDLER( px4_ramdisk_address_w )
	973	WRITE8_MEMBER(px4_state::px4_ramdisk_address_w)
966	974	{
967		px4_state *px4 = space->machine().driver_data<px4_state>();
968	975
969	976	switch (offset)
970	977	{
971		case 0x00: px4->m_ramdisk_address = (px4->m_ramdisk_address & 0xffff00) | data; break;
972		case 0x01: px4->m_ramdisk_address = (px4->m_ramdisk_address & 0xff00ff) | (data << 8); break;
973		case 0x02: px4->m_ramdisk_address = (px4->m_ramdisk_address & 0x00ffff) | ((data & 0x07) << 16); break;
	978	case 0x00: m_ramdisk_address = (m_ramdisk_address & 0xffff00) | data; break;
	979	case 0x01: m_ramdisk_address = (m_ramdisk_address & 0xff00ff) | (data << 8); break;
	980	case 0x02: m_ramdisk_address = (m_ramdisk_address & 0x00ffff) | ((data & 0x07) << 16); break;
974	981	}
975	982	}
976	983
977		static READ8_HANDLER( px4_ramdisk_data_r )
	984	READ8_MEMBER(px4_state::px4_ramdisk_data_r)
978	985	{
979		px4_state *px4 = space->machine().driver_data<px4_state>();
980	986	UINT8 ret = 0xff;
981	987
982		if (px4->m_ramdisk_address < 0x20000)
	988	if (m_ramdisk_address < 0x20000)
983	989	{
984	990	/* read from ram */
985		ret = px4->m_ramdisk[px4->m_ramdisk_address];
	991	ret = m_ramdisk[m_ramdisk_address];
986	992	}
987		else if (px4->m_ramdisk_address < 0x40000)
	993	else if (m_ramdisk_address < 0x40000)
988	994	{
989	995	/* read from rom */
990		ret = space->machine().region("ramdisk")->base()[px4->m_ramdisk_address];
	996	ret = machine().region("ramdisk")->base()[m_ramdisk_address];
991	997	}
992	998
993		px4->m_ramdisk_address = (px4->m_ramdisk_address & 0xffff00) | ((px4->m_ramdisk_address & 0xff) + 1);
	999	m_ramdisk_address = (m_ramdisk_address & 0xffff00) | ((m_ramdisk_address & 0xff) + 1);
994	1000
995	1001	return ret;
996	1002	}
997	1003
998		static WRITE8_HANDLER( px4_ramdisk_data_w )
	1004	WRITE8_MEMBER(px4_state::px4_ramdisk_data_w)
999	1005	{
1000		px4_state *px4 = space->machine().driver_data<px4_state>();
1001	1006
1002		if (px4->m_ramdisk_address < 0x20000)
1003		px4->m_ramdisk[px4->m_ramdisk_address] = data;
	1007	if (m_ramdisk_address < 0x20000)
	1008	m_ramdisk[m_ramdisk_address] = data;
1004	1009
1005		px4->m_ramdisk_address = (px4->m_ramdisk_address & 0xffff00) | ((px4->m_ramdisk_address & 0xff) + 1);
	1010	m_ramdisk_address = (m_ramdisk_address & 0xffff00) | ((m_ramdisk_address & 0xff) + 1);
1006	1011	}
1007	1012
1008		static READ8_HANDLER( px4_ramdisk_control_r )
	1013	READ8_MEMBER(px4_state::px4_ramdisk_control_r)
1009	1014	{
1010	1015	/* bit 7 determines the presence of a ram-disk */
1011	1016	return 0x7f;
r14844	r14845
1133	1138	ADDRESS_MAP_UNMAP_HIGH
1134	1139	ADDRESS_MAP_GLOBAL_MASK(0xff)
1135	1140	/* gapnit, 0x00-0x07 */
1136		AM_RANGE(0x00, 0x00) AM_READWRITE_LEGACY(px4_icrlc_r, px4_ctrl1_w)
1137		AM_RANGE(0x01, 0x01) AM_READWRITE_LEGACY(px4_icrhc_r, px4_cmdr_w)
1138		AM_RANGE(0x02, 0x02) AM_READWRITE_LEGACY(px4_icrlb_r, px4_ctrl2_w)
1139		AM_RANGE(0x03, 0x03) AM_READ_LEGACY(px4_icrhb_r)
1140		AM_RANGE(0x04, 0x04) AM_READWRITE_LEGACY(px4_isr_r, px4_ier_w)
1141		AM_RANGE(0x05, 0x05) AM_READWRITE_LEGACY(px4_str_r, px4_bankr_w)
1142		AM_RANGE(0x06, 0x06) AM_READWRITE_LEGACY(px4_sior_r, px4_sior_w)
	1141	AM_RANGE(0x00, 0x00) AM_READWRITE(px4_icrlc_r, px4_ctrl1_w)
	1142	AM_RANGE(0x01, 0x01) AM_READWRITE(px4_icrhc_r, px4_cmdr_w)
	1143	AM_RANGE(0x02, 0x02) AM_READWRITE(px4_icrlb_r, px4_ctrl2_w)
	1144	AM_RANGE(0x03, 0x03) AM_READ(px4_icrhb_r)
	1145	AM_RANGE(0x04, 0x04) AM_READWRITE(px4_isr_r, px4_ier_w)
	1146	AM_RANGE(0x05, 0x05) AM_READWRITE(px4_str_r, px4_bankr_w)
	1147	AM_RANGE(0x06, 0x06) AM_READWRITE(px4_sior_r, px4_sior_w)
1143	1148	AM_RANGE(0x07, 0x07) AM_NOP
1144	1149	/* gapndl, 0x08-0x0f */
1145		AM_RANGE(0x08, 0x08) AM_WRITE_LEGACY(px4_vadr_w)
1146		AM_RANGE(0x09, 0x09) AM_WRITE_LEGACY(px4_yoff_w)
1147		AM_RANGE(0x0a, 0x0a) AM_WRITE_LEGACY(px4_fr_w)
1148		AM_RANGE(0x0b, 0x0b) AM_WRITE_LEGACY(px4_spur_w)
	1150	AM_RANGE(0x08, 0x08) AM_WRITE(px4_vadr_w)
	1151	AM_RANGE(0x09, 0x09) AM_WRITE(px4_yoff_w)
	1152	AM_RANGE(0x0a, 0x0a) AM_WRITE(px4_fr_w)
	1153	AM_RANGE(0x0b, 0x0b) AM_WRITE(px4_spur_w)
1149	1154	AM_RANGE(0x0c, 0x0f) AM_NOP
1150	1155	/* gapnio, 0x10-0x1f */
1151		AM_RANGE(0x10, 0x13) AM_READWRITE_LEGACY(px4_ctgif_r, px4_ctgif_w)
1152		AM_RANGE(0x14, 0x14) AM_READWRITE_LEGACY(px4_artdir_r, px4_artdor_w)
1153		AM_RANGE(0x15, 0x15) AM_READWRITE_LEGACY(px4_artsr_r, px4_artmr_w)
1154		AM_RANGE(0x16, 0x16) AM_READWRITE_LEGACY(px4_iostr_r, px4_artcr_w)
	1156	AM_RANGE(0x10, 0x13) AM_READWRITE(px4_ctgif_r, px4_ctgif_w)
	1157	AM_RANGE(0x14, 0x14) AM_READWRITE(px4_artdir_r, px4_artdor_w)
	1158	AM_RANGE(0x15, 0x15) AM_READWRITE(px4_artsr_r, px4_artmr_w)
	1159	AM_RANGE(0x16, 0x16) AM_READWRITE(px4_iostr_r, px4_artcr_w)
1155	1160	AM_RANGE(0x17, 0x17) AM_DEVWRITE("centronics", centronics_device, write)
1156		AM_RANGE(0x18, 0x18) AM_WRITE_LEGACY(px4_swr_w)
1157		AM_RANGE(0x19, 0x19) AM_WRITE_LEGACY(px4_ioctlr_w)
	1161	AM_RANGE(0x18, 0x18) AM_WRITE(px4_swr_w)
	1162	AM_RANGE(0x19, 0x19) AM_WRITE(px4_ioctlr_w)
1158	1163	AM_RANGE(0x1a, 0x1f) AM_NOP
1159	1164	ADDRESS_MAP_END
1160	1165
1161	1166	static ADDRESS_MAP_START( px4p_io, AS_IO, 8, px4_state )
1162	1167	AM_IMPORT_FROM(px4_io)
1163		AM_RANGE(0x90, 0x92) AM_WRITE_LEGACY(px4_ramdisk_address_w)
1164		AM_RANGE(0x93, 0x93) AM_READWRITE_LEGACY(px4_ramdisk_data_r, px4_ramdisk_data_w)
1165		AM_RANGE(0x94, 0x94) AM_READ_LEGACY(px4_ramdisk_control_r)
	1168	AM_RANGE(0x90, 0x92) AM_WRITE(px4_ramdisk_address_w)
	1169	AM_RANGE(0x93, 0x93) AM_READWRITE(px4_ramdisk_data_r, px4_ramdisk_data_w)
	1170	AM_RANGE(0x94, 0x94) AM_READ(px4_ramdisk_control_r)
1166	1171	ADDRESS_MAP_END
1167	1172
1168	1173

src/mess/drivers/mmodular.c

r14844	r14845
137	137	UINT8 lcd_char;
138	138	//UINT8 led7;
139	139	UINT8 latch_data;
	140	DECLARE_WRITE8_MEMBER(write_polgar_IO);
	141	DECLARE_WRITE8_MEMBER(write_LCD_polgar);
	142	DECLARE_READ8_MEMBER(read_1ff1_sfortea);
	143	DECLARE_READ8_MEMBER(read_1ff0_sfortea);
	144	DECLARE_WRITE8_MEMBER(write_latch_sfortea);
	145	DECLARE_WRITE8_MEMBER(write_lcd_IO_sfortea);
	146	DECLARE_WRITE8_MEMBER(write_LCD_academy);
	147	//   DECLARE_WRITE16_MEMBER(diablo68_aciawrite);
	148	//   DECLARE_READ16_MEMBER(diablo68_aciaread);
	149	DECLARE_WRITE16_MEMBER(diablo68_reg_select);
	150	DECLARE_WRITE16_MEMBER(diablo68_write_LCD);
	151	DECLARE_WRITE8_MEMBER(milano_write_LED);
	152	DECLARE_WRITE8_MEMBER(megaiv_write_LED);
	153	DECLARE_WRITE8_MEMBER(academy_write_LED);
	154	DECLARE_WRITE8_MEMBER(academy_inhibitNMI);
	155	DECLARE_WRITE32_MEMBER(write_LED_BPL32);
	156	DECLARE_WRITE8_MEMBER(polgar_write_LED);
	157	DECLARE_WRITE8_MEMBER(monteciv_write_LCD);
	158	DECLARE_WRITE8_MEMBER(monteciv_3007);
	159	DECLARE_WRITE8_MEMBER(monteciv_3005);
	160	DECLARE_WRITE8_MEMBER(monteciv_3006);
	161	DECLARE_WRITE8_MEMBER(academy_write_board);
	162	DECLARE_WRITE8_MEMBER(milano_write_board);
	163	DECLARE_READ8_MEMBER(milano_read_board);
	164	DECLARE_READ8_MEMBER(read_keys);
	165	DECLARE_READ8_MEMBER(read_keys_megaiv);
	166	DECLARE_READ32_MEMBER(read_keys_BPL32);
	167	DECLARE_WRITE8_MEMBER(beep_academy);
	168	DECLARE_WRITE8_MEMBER(megaiv_IO);
	169	DECLARE_WRITE8_MEMBER(monteciv_select_line);
	170	DECLARE_READ8_MEMBER(read_keys_board_monteciv);
	171	DECLARE_READ8_MEMBER(read_keys_board_academy);
	172	DECLARE_WRITE32_MEMBER(write_board_BPL32);
	173	DECLARE_READ32_MEMBER(read_buttons_gen32);
	174	DECLARE_READ32_MEMBER(read_buttons_van32);
	175	DECLARE_READ16_MEMBER(read_buttons_van16);
	176	DECLARE_WRITE32_MEMBER(write_LCD_data_32);
	177	DECLARE_WRITE16_MEMBER(write_LCD_data);
	178	DECLARE_WRITE32_MEMBER(write_IOenables_32);
	179	DECLARE_WRITE16_MEMBER(write_IOenables);
	180	DECLARE_READ32_MEMBER(read_unknown1_32);
	181	DECLARE_READ16_MEMBER(read_unknown1);
	182	DECLARE_WRITE32_MEMBER(write_unknown2_32);
	183	DECLARE_WRITE16_MEMBER(write_unknown2);
	184	DECLARE_READ32_MEMBER(read_unknown3_32);
	185	DECLARE_READ16_MEMBER(read_unknown3);
	186	DECLARE_READ32_MEMBER(read_1800000);
	187	DECLARE_WRITE32_MEMBER(write_1000000);
140	188	};
141	189
142	190	static const hd44780_interface chess_display =
r14844	r14845
182	230	return NOT_VALID;
183	231	}
184	232
185		static WRITE8_HANDLER ( write_polgar_IO )
	233	WRITE8_MEMBER(polgar_state::write_polgar_IO)
186	234	{
187		polgar_state *state = space->machine().driver_data<polgar_state>();
188	235	int i;
189	236
190	237	if (BIT(data,1)) {
191		hd44780_device *hd44780 = space->machine().device<hd44780_device>("hd44780");
	238	hd44780_device *hd44780 = machine().device<hd44780_device>("hd44780");
192	239	if (BIT(data,0)) {
193		hd44780->data_write(*space, 128, state->lcd_char);
	240	hd44780->data_write(*&space, 128, lcd_char);
194	241	} else {
195		hd44780->control_write(*space, 128, state->lcd_char);
	242	hd44780->control_write(*&space, 128, lcd_char);
196	243	}
197	244	}
198	245
199		if (BIT(data,2) || BIT(data,3)) beep_set_state(space->machine().device("beep"),1); else beep_set_state(space->machine().device("beep"),0);
	246	if (BIT(data,2) || BIT(data,3)) beep_set_state(machine().device("beep"),1); else beep_set_state(machine().device("beep"),0);
200	247
201	248	if (BIT(data,7) && BIT(data, 4)) {
202	249	for (i = 0;i < 8;i++)
203		output_set_led_value(i,!BIT(state->latch_data,i));
	250	output_set_led_value(i,!BIT(latch_data,i));
204	251	}
205	252	else if (BIT(data,6) && BIT(data,5)) {
206	253	for (i = 0;i < 8;i++)
207		output_set_led_value(10+i,!BIT(state->latch_data,7-i));
	254	output_set_led_value(10+i,!BIT(latch_data,7-i));
208	255	}
209		else if (!data && (!strcmp(space->machine().system().name,"milano"))) {
	256	else if (!data && (!strcmp(machine().system().name,"milano"))) {
210	257	for (i=0;i<8;i++) {
211		output_set_led_value(i,!BIT(state->latch_data,i));
212		output_set_led_value(10+i,!BIT(state->latch_data,7-i));
	258	output_set_led_value(i,!BIT(latch_data,i));
	259	output_set_led_value(10+i,!BIT(latch_data,7-i));
213	260	}
214	261	}
215	262
r14844	r14845
219	266	}
220	267
221	268
222		static WRITE8_HANDLER ( write_LCD_polgar )
	269	WRITE8_MEMBER(polgar_state::write_LCD_polgar)
223	270	{
224		polgar_state *state = space->machine().driver_data<polgar_state>();
225	271
226		state->lcd_char = data;
	272	lcd_char = data;
227	273
228	274	logerror("LCD Data = %d %02x [%c]\n",data,data,(data&0xff));
229	275
230	276	}
231	277
232		static READ8_HANDLER ( read_1ff1_sfortea )
	278	READ8_MEMBER(polgar_state::read_1ff1_sfortea)
233	279	{
234	280	UINT8 data;
235		data = input_port_read(space->machine(),  "BUTTONS_SFOR1");
	281	data = input_port_read(machine(),  "BUTTONS_SFOR1");
236	282	logerror("1ff0 data %02x\n",data);
237	283	return 0;
238	284	//  return data;
239	285	}
240	286
241		static READ8_HANDLER ( read_1ff0_sfortea )
	287	READ8_MEMBER(polgar_state::read_1ff0_sfortea)
242	288	{
243	289	UINT8 data;
244		data = input_port_read(space->machine(),  "BUTTONS_SFOR2");
	290	data = input_port_read(machine(),  "BUTTONS_SFOR2");
245	291	logerror("1ff0 data %02x\n",data);
246	292	return 0;
247	293	//  return data;
r14844	r14845
256	302
257	303
258	304
259		static WRITE8_HANDLER ( write_latch_sfortea )
	305	WRITE8_MEMBER(polgar_state::write_latch_sfortea)
260	306	{
261	307	sfortea_latch = data;
262	308	logerror("latch data %02x\n",data);
r14844	r14845
264	310
265	311	}
266	312
267		static WRITE8_HANDLER ( write_lcd_IO_sfortea )
	313	WRITE8_MEMBER(polgar_state::write_lcd_IO_sfortea)
268	314	{
269	315	/* bits
270	316	7
r14844	r14845
280	326
281	327	if (BIT(sfortea_latch,2))
282	328	{
283		hd44780_device *hd44780 = space->machine().device<hd44780_device>("hd44780");
	329	hd44780_device *hd44780 = machine().device<hd44780_device>("hd44780");
284	330	if(BIT(sfortea_latch,0)) {
285		hd44780->data_write(*space, 128, data);
	331	hd44780->data_write(*&space, 128, data);
286	332	logerror("LCD DTA = %02x\n",data);
287	333	} else {
288	334	if (BIT(data,7)) {
289	335	if ((data & 0x7f) >= 0x40) data -= 56;  // adjust for 16x1 display as 2 sets of 8
290	336	}
291		hd44780->control_write(*space, 128, data);
	337	hd44780->control_write(*&space, 128, data);
292	338	logerror("LCD CMD = %02x\n",data);
293	339	}
294	340	}
295	341	}
296	342
297		static WRITE8_HANDLER ( write_LCD_academy )
	343	WRITE8_MEMBER(polgar_state::write_LCD_academy)
298	344	{
299		hd44780_device *hd44780 = space->machine().device<hd44780_device>("hd44780");
	345	hd44780_device *hd44780 = machine().device<hd44780_device>("hd44780");
300	346
301	347	if (offset) {
302		hd44780->data_write(*space, 128, data);
	348	hd44780->data_write(*&space, 128, data);
303	349	} else {
304		hd44780->control_write(*space, 128, data);
	350	hd44780->control_write(*&space, 128, data);
305	351	}
306	352	}
307	353
308		//  AM_RANGE( 0x3a0000,0x3a0000 ) AM_READ_LEGACY(diablo68_write_LCD)
309		//  AM_RANGE( 0x3c0000,0x3c0000 ) AM_READ_LEGACY(diablo68_reg_select)
	354	//  AM_RANGE( 0x3a0000,0x3a0000 ) AM_READ(diablo68_write_LCD)
	355	//  AM_RANGE( 0x3c0000,0x3c0000 ) AM_READ(diablo68_reg_select)
310	356
311		/*static WRITE16_HANDLER ( diablo68_aciawrite )
	357	/*WRITE16_MEMBER(polgar_state::diablo68_aciawrite)
312	358	{
313		//  device_t *acia = space->machine().device("acia65c51");
	359	//  device_t *acia = machine().device("acia65c51");
314	360	//  acia_6551_w(acia, offset & 0x03, data >> 8);
315	361	//  printf("ACIA write data %04x offset %02x\n",data,offset);
316	362	logerror("ACIA write data %04x offset %02x\n",data,offset);
317	363	}
318	364
319		static READ16_HANDLER ( diablo68_aciaread )
	365	READ16_MEMBER(polgar_state::diablo68_aciaread)
320	366	{
321		//  device_t *acia = space->machine().device("acia65c51");
	367	//  device_t *acia = machine().device("acia65c51");
322	368	UINT16 result;
323	369	//  result = acia_6551_r(acia, offset & 0x03);
324	370	//  logerror("ACIA read offset %02x\n",offset);
r14844	r14845
330	376	}
331	377	*/
332	378
333		static WRITE16_HANDLER ( diablo68_reg_select )
	379	WRITE16_MEMBER(polgar_state::diablo68_reg_select)
334	380	{
335	381	diablo68_3c0000 = data >> 8;
336	382	//printf("3c0000 = %04x\n",data>>8);
r14844	r14845
339	385	}
340	386
341	387
342		static WRITE16_HANDLER ( diablo68_write_LCD )
	388	WRITE16_MEMBER(polgar_state::diablo68_write_LCD)
343	389	{
344		hd44780_device *hd44780 = space->machine().device<hd44780_device>("hd44780");
	390	hd44780_device *hd44780 = machine().device<hd44780_device>("hd44780");
345	391	data >>= 8;
346	392	if (!(diablo68_3c0000 & 0x02)) {
347	393	if (BIT(data,7)) {
348	394	if ((data & 0x7f) >= 0x40) data -= 56;  // adjust for 16x1 display as 2 sets of 8
349	395	}
350		hd44780->control_write(*space, 128, data);
	396	hd44780->control_write(*&space, 128, data);
351	397	//      logerror("Control %02x\n", data);
352	398	//      printf("Control %02x\n", data);
353	399	} else {
354		hd44780->data_write(*space, 128, data);
	400	hd44780->data_write(*&space, 128, data);
355	401	//      printf("LCDdata %04x [%c]\n", data,data);
356	402	//      logerror("LCDdata %04x [%c]\n", data,data);
357	403	}
r14844	r14845
360	406
361	407	}
362	408
363		static WRITE8_HANDLER ( milano_write_LED )
	409	WRITE8_MEMBER(polgar_state::milano_write_LED)
364	410	{
365	411	UINT8 LED_offset = 100;
366	412	if (data == 0xff)   output_set_led_value(LED_offset+offset,1);
r14844	r14845
369	415	//logerror("LEDs  Offset = %d Data = %d\n",offset,data);
370	416	}
371	417
372		static WRITE8_HANDLER ( megaiv_write_LED )
	418	WRITE8_MEMBER(polgar_state::megaiv_write_LED)
373	419	{
374		if (BIT(data,7)) beep_set_state(space->machine().device("beep"),1); else beep_set_state(space->machine().device("beep"),0);
	420	if (BIT(data,7)) beep_set_state(machine().device("beep"),1); else beep_set_state(machine().device("beep"),0);
375	421	output_set_led_value(102,BIT(data,1)?1:0);
376	422	output_set_led_value(107,BIT(data,6)?1:0);
377	423
r14844	r14845
382	428	}
383	429
384	430
385		static WRITE8_HANDLER ( academy_write_LED )
	431	WRITE8_MEMBER(polgar_state::academy_write_LED)
386	432	{
387	433	int found = 0;
388	434
r14844	r14845
431	477	found = 1;
432	478	}
433	479
434		if (BIT(data,7)) beep_set_state(space->machine().device("beep"),1); else beep_set_state(space->machine().device("beep"),0);
435		if (BIT(data,1)) beep_set_state(space->machine().device("beep"),1); else beep_set_state(space->machine().device("beep"),0);
	480	if (BIT(data,7)) beep_set_state(machine().device("beep"),1); else beep_set_state(machine().device("beep"),0);
	481	if (BIT(data,1)) beep_set_state(machine().device("beep"),1); else beep_set_state(machine().device("beep"),0);
436	482	//  logerror("LEDs  FUNC = %02x found = %d\n",data,found);
437	483	if (!found) {
438	484	logerror("unknown LED mask %d\n",data);
r14844	r14845
441	487	}
442	488
443	489
444		static WRITE8_HANDLER ( academy_inhibitNMI )
	490	WRITE8_MEMBER(polgar_state::academy_inhibitNMI)
445	491	{
446	492	academyallowNMI = data;
447	493
448	494	}
449	495
450	496
451		static WRITE32_HANDLER ( write_LED_BPL32 )
	497	WRITE32_MEMBER(polgar_state::write_LED_BPL32)
452	498	{
453	499	int i;
454	500
r14844	r14845
463	509	}
464	510
465	511
466		static WRITE8_HANDLER ( polgar_write_LED )
	512	WRITE8_MEMBER(polgar_state::polgar_write_LED)
467	513	{
468	514	#define LED_offset 100
469		polgar_state *state = space->machine().driver_data<polgar_state>();
470	515
471	516	data &= 0x80;
472	517
473	518	if (data == 0) {
474		state->led_status &= 255-(1<<offset);
	519	led_status &= 255-(1<<offset);
475	520	} else {
476		state->led_status|=1<<offset;
	521	led_status|=1<<offset;
477	522	}
478	523
479		if (offset < 6) output_set_led_value(LED_offset+offset, state->led_status&1<<offset?1:0);
	524	if (offset < 6) output_set_led_value(LED_offset+offset, led_status&1<<offset?1:0);
480	525	logerror("LEDs  Offset = %d Data = %d\n",offset,data);
481	526	}
482	527
r14844	r14845
494	539	return data;
495	540	}
496	541
497		static WRITE8_HANDLER ( monteciv_write_LCD )
	542	WRITE8_MEMBER(polgar_state::monteciv_write_LCD)
498	543	// first write == 00 (start) then 8 writes (to 74595) x 4 chars, then ff to finish
499	544	{
500	545	static UINT8 charstodisplay[4] = { 0,0,0,0 };
r14844	r14845
561	606	//    printf("$3004 %02x %02x \n",data,tempchar);
562	607	}
563	608
564		static WRITE8_HANDLER ( monteciv_3007 )
	609	WRITE8_MEMBER(polgar_state::monteciv_3007)
565	610	{
566	611	//    logerror("$3007 SELECTTOP %02x\n",data);
567	612	//    printf("$3007 SELECTTOP %02x\n",data);
r14844	r14845
569	614	montecivtopnew = 1;
570	615	}
571	616
572		static WRITE8_HANDLER ( monteciv_3005 )
	617	WRITE8_MEMBER(polgar_state::monteciv_3005)
573	618	{
574	619	//    logerror("$3005 SELECTBOT %02x\n",data);
575	620	//    printf("$3005 SELECTBOT %02x\n",data);
r14844	r14845
577	622	montecivbotnew = 1;
578	623	}
579	624
580		static WRITE8_HANDLER ( monteciv_3006 )
	625	WRITE8_MEMBER(polgar_state::monteciv_3006)
581	626	{
582	627	logerror("$3006 CLK %02x\n",data);
583	628	//    printf("$3006 CLK %02x\n",data);
584	629	}
585	630
586	631
587		static WRITE8_HANDLER ( academy_write_board )
	632	WRITE8_MEMBER(polgar_state::academy_write_board)
588	633	{
589		polgar_state *state = space->machine().driver_data<polgar_state>();
590	634
591		state->latch_data = data;
	635	latch_data = data;
592	636	//    logerror("acad_write_latch %02x\n",data);
593		if (data != 0xff) mboard_write_board_8(space,0, data);
	637	if (data != 0xff) mboard_write_board_8(&space,0, data);
594	638	}
595	639
596		static WRITE8_HANDLER ( milano_write_board )
	640	WRITE8_MEMBER(polgar_state::milano_write_board)
597	641	{
598		polgar_state *state = space->machine().driver_data<polgar_state>();
599	642
600		state->latch_data = data;
	643	latch_data = data;
601	644	}
602	645
603		static READ8_HANDLER(milano_read_board)
	646	READ8_MEMBER(polgar_state::milano_read_board)
604	647	{
605	648	int line;
606		polgar_state *state = space->machine().driver_data<polgar_state>();
607	649	static const char *const board_lines[8] =
608	650	{ "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7", "LINE8", "LINE9" };
609	651
610	652	UINT8 data = 0x00;
611	653	UINT8 tmp; // = 0xff;
612	654
613		if (state->latch_data)
	655	if (latch_data)
614	656	{
615		line = get_first_cleared_bit(state->latch_data);
616		tmp = input_port_read(space->machine(),  board_lines[line]);
	657	line = get_first_cleared_bit(latch_data);
	658	tmp = input_port_read(machine(),  board_lines[line]);
617	659
618	660	if (tmp != 0xff)
619	661	data = convert_imputmask(tmp);
r14844	r14845
624	666
625	667	}
626	668
627		static READ8_HANDLER(read_keys)
	669	READ8_MEMBER(polgar_state::read_keys)
628	670	{
629	671	UINT8 data;
630	672	static const char *const keynames[1][8] =
r14844	r14845
632	674	{ "KEY1_0", "KEY1_1", "KEY1_2", "KEY1_3", "KEY1_4", "KEY1_5", "KEY1_6", "KEY1_7" }
633	675	};
634	676
635		data = input_port_read(space->machine(), keynames[0][offset]);
	677	data = input_port_read(machine(), keynames[0][offset]);
636	678	// logerror("Keyboard Port = %s Data = %d\n  ", ((led_status & 0x80) == 0x00) ? keynames[0][offset] : keynames[1][offset], data);
637	679	return data | 0x7f;
638	680	}
639	681
640		static READ8_HANDLER(read_keys_megaiv)
	682	READ8_MEMBER(polgar_state::read_keys_megaiv)
641	683	{
642	684	UINT8 data;
643	685	static const char *const keynames[1][8] =
r14844	r14845
645	687	{ "KEY1_0", "KEY1_1", "KEY1_2", "KEY1_3", "KEY1_4", "KEY1_5", "KEY1_6", "KEY1_7" }
646	688	};
647	689
648		data = input_port_read(space->machine(), keynames[0][offset]);
	690	data = input_port_read(machine(), keynames[0][offset]);
649	691	logerror("Keyboard Port = %s Data = %d\n  ", keynames[0][offset] , data);
650	692	return data | 0x7f;
651	693	}
652	694
653	695
654		static READ32_HANDLER(read_keys_BPL32)
	696	READ32_MEMBER(polgar_state::read_keys_BPL32)
655	697	{
656	698	UINT32 data = 0;
657	699	UINT8 tmp = 0xff, line = 0;
r14844	r14845
659	701	{ "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7", "LINE8", "LINE9" };
660	702
661	703	if (BPL32latch_data == 0xff) {
662		tmp = input_port_read(space->machine(),  "BUTTONS_BPL");
	704	tmp = input_port_read(machine(),  "BUTTONS_BPL");
663	705	logerror("Keyboard Port Offset = %d tmp %d\n", offset,tmp);
664	706
665	707	data = tmp << 24;
r14844	r14845
667	709	if (BPL32latch_data & 0x7f) {
668	710	logerror("ReadingBoard %02x\n",BPL32latch_data);
669	711	line = get_first_cleared_bit(BPL32latch_data);
670		tmp = input_port_read(space->machine(),  board_lines[line]);
	712	tmp = input_port_read(machine(),  board_lines[line]);
671	713
672	714	if (tmp != 0xff)
673	715	data = convert_imputmask(tmp) << 24;
r14844	r14845
678	720	return data;
679	721	}
680	722
681		static WRITE8_HANDLER(beep_academy)
	723	WRITE8_MEMBER(polgar_state::beep_academy)
682	724	{
683		if (!BIT(data,7)) beep_set_state(space->machine().device("beep"),1); else beep_set_state(space->machine().device("beep"),0);
	725	if (!BIT(data,7)) beep_set_state(machine().device("beep"),1); else beep_set_state(machine().device("beep"),0);
684	726	}
685	727
686		static WRITE8_HANDLER(megaiv_IO)
	728	WRITE8_MEMBER(polgar_state::megaiv_IO)
687	729	{
688		//  if (BIT(data,0)) beep_set_state(space->machine->device("beep"),1); else beep_set_state(space->machine->device("beep"),0);
	730	//  if (BIT(data,0)) beep_set_state(machine->device("beep"),1); else beep_set_state(machine->device("beep"),0);
689	731	logerror("$2400 = %02x\n",data);
690	732	latch2400 = data;
691	733	}
692	734
693	735
694		static WRITE8_HANDLER( monteciv_select_line )
	736	WRITE8_MEMBER(polgar_state::monteciv_select_line)
695	737	{
696	738	monteciv_select[offset] = data;
697	739	}
698	740
699	741	// FIXME : unlike polgar, academy shares port IO for keys and board, and i just can't seem to get the board latched right (H7 and H8 are always flashing) -- Cow
700		static READ8_HANDLER(read_keys_board_monteciv)
	742	READ8_MEMBER(polgar_state::read_keys_board_monteciv)
701	743	{
702	744	UINT8 data = 0;
703	745
704	746	if (monteciv_select[0] == 0xff && monteciv_select[1] == 0xff) {
705		data = mboard_read_board_8(space,0);
	747	data = mboard_read_board_8(&space,0);
706	748	} else {
707	749	if (monteciv_select[0] == 0x0) {
708		data = input_port_read(space->machine(),  "BUTTONS_MONTE2");
	750	data = input_port_read(machine(),  "BUTTONS_MONTE2");
709	751	#if 0
710	752	if (data) {
711	753	output_set_digit_value(0,64);
r14844	r14845
720	762	}
721	763	#endif
722	764	} else {
723		data = input_port_read(space->machine(),  "BUTTONS_MONTE1");
	765	data = input_port_read(machine(),  "BUTTONS_MONTE1");
724	766	}
725	767	}
726	768	return data;
r14844	r14845
728	770
729	771
730	772	// FIXME : unlike polgar, academy shares port IO for keys and board, and I just can't seem to get the board latched right (H7 and H8 are always flashing) -- Cow
731		static READ8_HANDLER(read_keys_board_academy)
	773	READ8_MEMBER(polgar_state::read_keys_board_academy)
732	774	{
733	775	//  static int startup = 0;
734		polgar_state *state = space->machine().driver_data<polgar_state>();
735	776	UINT8 data = 0;
736	777	//  UINT8 tmp = 0xff, line = 0;
737	778	//  static const char *const board_lines[8] =
738	779	//          { "LINE2", "LINE3", "LINE4", "LINE5", "LINE6", "LINE7", "LINE8", "LINE9" };
739	780
740		if (state->latch_data == 0xff) {
741		data = input_port_read(space->machine(),  "BUTTONS_ACAD");
	781	if (latch_data == 0xff) {
	782	data = input_port_read(machine(),  "BUTTONS_ACAD");
742	783	} else {
743		//      if (state->latch_data & 0x7f) {
744		data = mboard_read_board_8(space,0);
	784	//      if (latch_data & 0x7f) {
	785	data = mboard_read_board_8(&space,0);
745	786	//      data = milano_read_board(space,0);
746	787
747		//          logerror("ReadingBoard %02x\n",state->latch_data);
748		//          line = get_first_cleared_bit(state->latch_data);
749		//          tmp = input_port_read(space->machine,  board_lines[line]);
750		//          mboard_write_board_8(space,0, state->latch_data);
751		//          data = mboard_read_board_8(space,0);
752		//          logerror("BoardRead Port Offset = %d data %02x Latch %02x\n", offset,data,state->latch_data);
753		//          printf  ("BoardRead Port Offset = %d data %02x Latch %02x\n", offset,data,state->latch_data);
	788	//          logerror("ReadingBoard %02x\n",latch_data);
	789	//          line = get_first_cleared_bit(latch_data);
	790	//          tmp = input_port_read(machine,  board_lines[line]);
	791	//          mboard_write_board_8(&space,0, latch_data);
	792	//          data = mboard_read_board_8(&space,0);
	793	//          logerror("BoardRead Port Offset = %d data %02x Latch %02x\n", offset,data,latch_data);
	794	//          printf  ("BoardRead Port Offset = %d data %02x Latch %02x\n", offset,data,latch_data);
754	795	//      } else {
755	796	//          logerror("no keys or board\n");
756	797	//      }
757	798	}
758		//  logerror("Keyboard Port Offset = %d tmp %d Latch %d\n", offset,tmp,state->latch_data);
	799	//  logerror("Keyboard Port Offset = %d tmp %d Latch %d\n", offset,tmp,latch_data);
759	800	//  logerror("Keyboard Port = %s Data = %d Offset = %d tmp %d line %02x\n", keynames[0][line], data, offset,tmp,line);
760	801	return data;
761	802	}
r14844	r14845
773	814	}
774	815
775	816
776		static WRITE32_HANDLER( write_board_BPL32 )
	817	WRITE32_MEMBER(polgar_state::write_board_BPL32)
777	818	{
778	819	BPL32latch_data = data >> 24;
779	820	logerror("Write BPL32 board Data Latch %08x Offset: %08x\n",BPL32latch_data,offset);
780	821
781	822	}
782	823
783		static READ32_HANDLER( read_buttons_gen32 )
	824	READ32_MEMBER(polgar_state::read_buttons_gen32)
784	825	{
785	826	UINT32 data;
786	827	static const char *const keynames[4] = { "BUTTON_1", "BUTTON_2", "", "BUTTON_3" };
787	828
788		data = input_port_read(space->machine(), keynames[offset]);
	829	data = input_port_read(machine(), keynames[offset]);
789	830
790	831	data = data|data<<8|data<<16|data<<24;  // this might not be needed if MAME does handle odd alignment over 32bit boundaries right
791	832	logerror("Read from Buttons: %08x %08x\n",offset,data);
792	833	return data;
793	834	}
794	835
795		static READ32_HANDLER( read_buttons_van32 )
	836	READ32_MEMBER(polgar_state::read_buttons_van32)
796	837	{
797	838	UINT32 data;
798	839	static const char *const keynames[4] = { "BUTTON_1", "", "BUTTON_2", "BUTTON_3" };
799	840
800	841
801		data = input_port_read(space->machine(), keynames[offset]);
	842	data = input_port_read(machine(), keynames[offset]);
802	843
803	844	data = data << 8;
804	845	logerror("Read from Buttons: %08x %08x\n",offset,data);
805	846	return data;
806	847	}
807	848
808		static READ16_HANDLER( read_buttons_van16 )
	849	READ16_MEMBER(polgar_state::read_buttons_van16)
809	850	{
810	851	UINT16 data;
811	852	static const char *const keynames[3] = { "BUTTON_1", "BUTTON_2", "BUTTON_3" };
812	853
813	854
814		data = input_port_read(space->machine(), keynames[offset>>1]) << 8;
	855	data = input_port_read(machine(), keynames[offset>>1]) << 8;
815	856
816	857	logerror("Read from %06x offset: %x %04x\n",0xf00000,offset,data);
817	858	return data;
818	859	}
819	860
820		static WRITE32_HANDLER( write_LCD_data_32 )
	861	WRITE32_MEMBER(polgar_state::write_LCD_data_32)
821	862	{
822	863
823	864	//  printf("Write LCD Data Latch %08x o: %08x\n",data,offset);
824	865	logerror("Write LCD Data Latch %08x o: %08x\n",data,offset);
825	866	lcd32_char = data>>24;
826		//  cpu_adjust_icount(space->cpu,-5000);
	867	//  cpu_adjust_icount(cpu,-5000);
827	868
828	869	}
829	870
830		static WRITE16_HANDLER( write_LCD_data )
	871	WRITE16_MEMBER(polgar_state::write_LCD_data)
831	872	{
832	873
833	874	lcd32_char = data>>8;
r14844	r14845
867	908
868	909	}
869	910
870		static WRITE32_HANDLER( write_IOenables_32 ) {
	911	WRITE32_MEMBER(polgar_state::write_IOenables_32){
871	912
872		write_IOenable(data>>24,space);
	913	write_IOenable(data>>24,&space);
873	914	}
874	915
875		static WRITE16_HANDLER( write_IOenables )
	916	WRITE16_MEMBER(polgar_state::write_IOenables)
876	917	{
877		write_IOenable(data>>8,space);
	918	write_IOenable(data>>8,&space);
878	919	}
879	920
880	921	/* Unknown read/write */
881	922
882		static READ32_HANDLER( read_unknown1_32 )
	923	READ32_MEMBER(polgar_state::read_unknown1_32)
883	924	{
884	925	logerror("Read from unknown1 offset: %x\n",offset);
885	926	return 0xff00ff00;
886	927	}
887	928
888		static READ16_HANDLER( read_unknown1 )
	929	READ16_MEMBER(polgar_state::read_unknown1)
889	930	{
890	931	logerror("Read from %06x offset: %x\n",0xe80002,offset);
891	932	return 0xff00;
892	933	}
893	934
894		static WRITE32_HANDLER( write_unknown2_32 )
	935	WRITE32_MEMBER(polgar_state::write_unknown2_32)
895	936	{
896	937	//unknown2_data = data;
897	938	logerror("Write to   unknown2 data: %04x\n",data);
898	939	}
899	940
900		static WRITE16_HANDLER( write_unknown2 )
	941	WRITE16_MEMBER(polgar_state::write_unknown2)
901	942	{
902	943	//unknown2_data = data;
903	944	logerror("Write from %06x data: %04x\n",0xe80004,data);
904	945	}
905	946
906		static READ32_HANDLER( read_unknown3_32 )
	947	READ32_MEMBER(polgar_state::read_unknown3_32)
907	948	{
908		logerror("Read from unknown3 offset: %x %08x\n",offset,(unsigned int) cpu_get_reg(space->machine().device("maincpu"), M68K_PC));
	949	logerror("Read from unknown3 offset: %x %08x\n",offset,(unsigned int) cpu_get_reg(machine().device("maincpu"), M68K_PC));
909	950	return 0xffffffff;
910	951	//return unknown2_data|unknown2_data<<24;
911	952
912	953	}
913	954
914		static READ16_HANDLER( read_unknown3 )
	955	READ16_MEMBER(polgar_state::read_unknown3)
915	956	{
916	957	logerror("Read from %06x offset: %x\n",0xe80006,offset);
917	958	return 0xffff;
r14844	r14845
919	960
920	961	}
921	962
922		static READ32_HANDLER( read_1800000 )
	963	READ32_MEMBER(polgar_state::read_1800000)
923	964	{
924	965	logerror("Read from RISC2500 1800000\n");
925	966	return 0;
926	967	}
927	968
928		static WRITE32_HANDLER( write_1000000 )
	969	WRITE32_MEMBER(polgar_state::write_1000000)
929	970	{
930	971	logerror("Write to  RISC2500 1000000\n");
931	972	}
r14844	r14845
1070	1111	AM_RANGE( 0x2400, 0x2400 ) AM_WRITE_LEGACY(mboard_write_LED_8 )      // Chessboard
1071	1112	AM_RANGE( 0x2800, 0x2800 ) AM_WRITE_LEGACY(mboard_write_board_8)      // Chessboard
1072	1113	AM_RANGE( 0x3000, 0x3000 ) AM_READ_LEGACY(mboard_read_board_8 )      // Chessboard
1073		AM_RANGE( 0x3400, 0x3405 ) AM_WRITE_LEGACY(polgar_write_LED)   // Function LEDs
1074		AM_RANGE( 0x2c00, 0x2c07 ) AM_READ_LEGACY(read_keys)
1075		AM_RANGE( 0x2004, 0x2004 ) AM_WRITE_LEGACY(write_polgar_IO )   // LCD Instr. Reg + Beeper
1076		AM_RANGE( 0x2000, 0x2000 ) AM_WRITE_LEGACY(write_LCD_polgar )           // LCD Char Reg.
	1114	AM_RANGE( 0x3400, 0x3405 ) AM_WRITE(polgar_write_LED)   // Function LEDs
	1115	AM_RANGE( 0x2c00, 0x2c07 ) AM_READ(read_keys)
	1116	AM_RANGE( 0x2004, 0x2004 ) AM_WRITE(write_polgar_IO )   // LCD Instr. Reg + Beeper
	1117	AM_RANGE( 0x2000, 0x2000 ) AM_WRITE(write_LCD_polgar )           // LCD Char Reg.
1077	1118	AM_RANGE( 0x4000, 0xffff ) AM_ROM
1078	1119	ADDRESS_MAP_END
1079	1120
1080	1121	static ADDRESS_MAP_START(sfortea_mem , AS_PROGRAM, 8, polgar_state )
1081	1122	AM_RANGE( 0x0000, 0x1fef ) AM_RAM
1082		AM_RANGE( 0x1ff6, 0x1ff6 ) AM_WRITE_LEGACY(write_latch_sfortea)   // IO control
1083		AM_RANGE( 0x1ff7, 0x1ff7 ) AM_WRITE_LEGACY(write_lcd_IO_sfortea)   // LCD Char Reg.
	1123	AM_RANGE( 0x1ff6, 0x1ff6 ) AM_WRITE(write_latch_sfortea)   // IO control
	1124	AM_RANGE( 0x1ff7, 0x1ff7 ) AM_WRITE(write_lcd_IO_sfortea)   // LCD Char Reg.
1084	1125	//  AM_RANGE( 0x1ffc, 0x1fff ) AM_DEVREADWRITE_LEGACY("acia65c51", acia_6551_r,acia_6551_w)
1085		AM_RANGE( 0x1ff1, 0x1ff1 ) AM_READ_LEGACY(read_1ff1_sfortea )
1086		AM_RANGE( 0x1ff0, 0x1ff0 ) AM_READ_LEGACY(read_1ff0_sfortea )
	1126	AM_RANGE( 0x1ff1, 0x1ff1 ) AM_READ(read_1ff1_sfortea )
	1127	AM_RANGE( 0x1ff0, 0x1ff0 ) AM_READ(read_1ff0_sfortea )
1087	1128	AM_RANGE( 0x2000, 0xffff ) AM_ROM
1088	1129	ADDRESS_MAP_END
1089	1130
r14844	r14845
1097	1138	AM_RANGE( 0xc8000004 , 0xc8000007 )  AM_WRITE_LEGACY(mboard_write_board_32 )
1098	1139	AM_RANGE( 0xd0000000 , 0xd0000003 )  AM_WRITE_LEGACY(mboard_write_LED_32 )
1099	1140	AM_RANGE( 0xd0000004 , 0xd0000007 )  AM_WRITE_LEGACY(mboard_write_LED_32 )
1100		AM_RANGE( 0xf0000004 , 0xf0000013 )  AM_READ_LEGACY(read_buttons_gen32 )
1101		AM_RANGE( 0xe0000000 , 0xe0000003 )  AM_WRITE_LEGACY(write_LCD_data_32 )
1102		AM_RANGE( 0xe0000010 , 0xe0000013 )  AM_WRITE_LEGACY(write_IOenables_32 )
1103		AM_RANGE( 0xd8000008 , 0xd800000b )  AM_WRITE_LEGACY(write_unknown2_32 )
1104		AM_RANGE( 0xd8000004 , 0xd8000007 )  AM_READ_LEGACY(read_unknown1_32 )
1105		AM_RANGE( 0xd800000c , 0xd800000f )  AM_READ_LEGACY(read_unknown3_32 )
	1141	AM_RANGE( 0xf0000004 , 0xf0000013 )  AM_READ(read_buttons_gen32 )
	1142	AM_RANGE( 0xe0000000 , 0xe0000003 )  AM_WRITE(write_LCD_data_32 )
	1143	AM_RANGE( 0xe0000010 , 0xe0000013 )  AM_WRITE(write_IOenables_32 )
	1144	AM_RANGE( 0xd8000008 , 0xd800000b )  AM_WRITE(write_unknown2_32 )
	1145	AM_RANGE( 0xd8000004 , 0xd8000007 )  AM_READ(read_unknown1_32 )
	1146	AM_RANGE( 0xd800000c , 0xd800000f )  AM_READ(read_unknown3_32 )
1106	1147
1107	1148	AM_RANGE( 0x40000000, 0x4007ffff )  AM_RAM      /* 512KB */
1108	1149	AM_RANGE( 0x80000000, 0x8003ffff )  AM_RAM      /* 256KB */
r14844	r14845
1113	1154	static ADDRESS_MAP_START(bpl32_mem, AS_PROGRAM, 32, polgar_state )
1114	1155
1115	1156	AM_RANGE( 0x000000,  0x03ffff )  AM_ROM
1116		AM_RANGE( 0x800000 , 0x800003 )  AM_READ_LEGACY(read_keys_BPL32 )
1117		AM_RANGE( 0x900000 , 0x900003 )  AM_WRITE_LEGACY(write_board_BPL32 )
1118		AM_RANGE( 0xa00000 , 0xa00003 )  AM_WRITE_LEGACY(write_LED_BPL32 )
1119		AM_RANGE( 0xc00000 , 0xc00003 )  AM_WRITE_LEGACY(write_LCD_data_32 )
1120		AM_RANGE( 0xb00000 , 0xb00003 )  AM_WRITE_LEGACY(write_IOenables_32 )
	1157	AM_RANGE( 0x800000 , 0x800003 )  AM_READ(read_keys_BPL32 )
	1158	AM_RANGE( 0x900000 , 0x900003 )  AM_WRITE(write_board_BPL32 )
	1159	AM_RANGE( 0xa00000 , 0xa00003 )  AM_WRITE(write_LED_BPL32 )
	1160	AM_RANGE( 0xc00000 , 0xc00003 )  AM_WRITE(write_LCD_data_32 )
	1161	AM_RANGE( 0xb00000 , 0xb00003 )  AM_WRITE(write_IOenables_32 )
1121	1162	AM_RANGE( 0x400000 , 0x4fffff )  AM_RAM      /* 1024KB */
1122	1163	AM_RANGE( 0xd00000 , 0xd07fff )  AM_RAM AM_BASE_LEGACY(&save_ram32) AM_SHARE("nvram")
1123	1164
r14844	r14845
1130	1171	AM_RANGE( 0x800000fc , 0x800000ff )  AM_READ_LEGACY(mboard_read_board_32 )
1131	1172	AM_RANGE( 0x88000000 , 0x88000007 )  AM_WRITE_LEGACY(mboard_write_board_32 )
1132	1173	AM_RANGE( 0x90000000 , 0x90000007 )  AM_WRITE_LEGACY(mboard_write_LED_32 )
1133		AM_RANGE( 0x800000ec , 0x800000ff )  AM_READ_LEGACY(read_buttons_van32 )
1134		AM_RANGE( 0xa0000000 , 0xa0000003 )  AM_WRITE_LEGACY(write_LCD_data_32 )
1135		AM_RANGE( 0xa0000010 , 0xa0000013 )  AM_WRITE_LEGACY(write_IOenables_32 )
1136		AM_RANGE( 0x98000008 , 0x9800000b )  AM_WRITE_LEGACY(write_unknown2_32 )
1137		AM_RANGE( 0x98000004 , 0x98000007 )  AM_READ_LEGACY(read_unknown1_32 )
1138		AM_RANGE( 0x9800000c , 0x9800000f )  AM_READ_LEGACY(read_unknown3_32 )
	1174	AM_RANGE( 0x800000ec , 0x800000ff )  AM_READ(read_buttons_van32 )
	1175	AM_RANGE( 0xa0000000 , 0xa0000003 )  AM_WRITE(write_LCD_data_32 )
	1176	AM_RANGE( 0xa0000010 , 0xa0000013 )  AM_WRITE(write_IOenables_32 )
	1177	AM_RANGE( 0x98000008 , 0x9800000b )  AM_WRITE(write_unknown2_32 )
	1178	AM_RANGE( 0x98000004 , 0x98000007 )  AM_READ(read_unknown1_32 )
	1179	AM_RANGE( 0x9800000c , 0x9800000f )  AM_READ(read_unknown3_32 )
1139	1180
1140	1181	AM_RANGE( 0x40000000, 0x400fffff )  AM_RAM      /* 1024KB */
1141	1182	AM_RANGE( 0xa8000000, 0xa8007fff )  AM_RAM AM_BASE_LEGACY(&save_ram32) AM_SHARE("nvram")
r14844	r14845
1150	1191	AM_RANGE( 0x800000fc , 0x800000ff )  AM_READ_LEGACY(mboard_read_board_32 )
1151	1192	AM_RANGE( 0x88000000 , 0x88000007 )  AM_WRITE_LEGACY(mboard_write_board_32 )
1152	1193	AM_RANGE( 0x90000000 , 0x90000007 )  AM_WRITE_LEGACY(mboard_write_LED_32 )
1153		AM_RANGE( 0x800000ec , 0x800000ff )  AM_READ_LEGACY(read_buttons_van32 )
1154		AM_RANGE( 0xa0000000 , 0xa0000003 )  AM_WRITE_LEGACY(write_LCD_data_32 )
1155		AM_RANGE( 0xa0000010 , 0xa0000013 )  AM_WRITE_LEGACY(write_IOenables_32 )
1156		AM_RANGE( 0x98000008 , 0x9800000b )  AM_WRITE_LEGACY(write_unknown2_32 )
1157		AM_RANGE( 0x98000004 , 0x98000007 )  AM_READ_LEGACY(read_unknown1_32 )
1158		AM_RANGE( 0x9800000c , 0x9800000f )  AM_READ_LEGACY(read_unknown3_32 )
	1194	AM_RANGE( 0x800000ec , 0x800000ff )  AM_READ(read_buttons_van32 )
	1195	AM_RANGE( 0xa0000000 , 0xa0000003 )  AM_WRITE(write_LCD_data_32 )
	1196	AM_RANGE( 0xa0000010 , 0xa0000013 )  AM_WRITE(write_IOenables_32 )
	1197	AM_RANGE( 0x98000008 , 0x9800000b )  AM_WRITE(write_unknown2_32 )
	1198	AM_RANGE( 0x98000004 , 0x98000007 )  AM_READ(read_unknown1_32 )
	1199	AM_RANGE( 0x9800000c , 0x9800000f )  AM_READ(read_unknown3_32 )
1159	1200
1160	1201	AM_RANGE( 0x40000000, 0x400fffff )  AM_RAM
1161	1202	AM_RANGE( 0xa8000000, 0xa8007fff )  AM_RAM AM_BASE_LEGACY(&save_ram32) AM_SHARE("nvram")
r14844	r14845
1165	1206	static ADDRESS_MAP_START(risc_mem, AS_PROGRAM, 32, polgar_state )
1166	1207
1167	1208	AM_RANGE( 0x02000000,  0x0201ffff )  AM_ROM AM_REGION("maincpu", 0) // AM_MIRROR(0x2000000)
1168		AM_RANGE( 0x01000000,  0x01000003 )  AM_WRITE_LEGACY(write_1000000 )
1169		AM_RANGE( 0x01800000,  0x01800003 )  AM_READ_LEGACY(read_1800000 )
	1209	AM_RANGE( 0x01000000,  0x01000003 )  AM_WRITE(write_1000000 )
	1210	AM_RANGE( 0x01800000,  0x01800003 )  AM_READ(read_1800000 )
1170	1211	AM_RANGE( 0x00000000,  0x0001ffff )  AM_RAM
1171	1212
1172	1213	ADDRESS_MAP_END
r14844	r14845
1178	1219	AM_RANGE( 0xc00000 , 0xc00001 )  AM_READ_LEGACY(mboard_read_board_16 )
1179	1220	AM_RANGE( 0xc80000 , 0xc80001 )  AM_WRITE_LEGACY(mboard_write_board_16 )
1180	1221	AM_RANGE( 0xd00000 , 0xd00001 )  AM_WRITE_LEGACY(mboard_write_LED_16 )
1181		AM_RANGE( 0xf00000 , 0xf00009 )  AM_READ_LEGACY(read_buttons_van16 )
1182		AM_RANGE( 0xd80000 , 0xd80001 )  AM_WRITE_LEGACY(write_LCD_data )
1183		AM_RANGE( 0xd80008 , 0xd80009 )  AM_WRITE_LEGACY(write_IOenables )
1184		AM_RANGE( 0xe80004 , 0xe80005 )  AM_WRITE_LEGACY(write_unknown2 )
1185		AM_RANGE( 0xe80002 , 0xe80003 )  AM_READ_LEGACY(read_unknown1 )
1186		AM_RANGE( 0xe80006 , 0xe80007 )  AM_READ_LEGACY(read_unknown3 )
	1222	AM_RANGE( 0xf00000 , 0xf00009 )  AM_READ(read_buttons_van16 )
	1223	AM_RANGE( 0xd80000 , 0xd80001 )  AM_WRITE(write_LCD_data )
	1224	AM_RANGE( 0xd80008 , 0xd80009 )  AM_WRITE(write_IOenables )
	1225	AM_RANGE( 0xe80004 , 0xe80005 )  AM_WRITE(write_unknown2 )
	1226	AM_RANGE( 0xe80002 , 0xe80003 )  AM_READ(read_unknown1 )
	1227	AM_RANGE( 0xe80006 , 0xe80007 )  AM_READ(read_unknown3 )
1187	1228
1188	1229	AM_RANGE( 0x400000, 0x47ffff )  AM_RAM      /* 512KB */
1189	1230	AM_RANGE( 0x800000, 0x803fff )  AM_RAM AM_BASE_LEGACY(&save_ram) AM_SHARE("nvram")
r14844	r14845
1197	1238	AM_RANGE( 0xc00000 , 0xc00001 )  AM_READ_LEGACY(mboard_read_board_16 )
1198	1239	AM_RANGE( 0xc80000 , 0xc80001 )  AM_WRITE_LEGACY(mboard_write_board_16 )
1199	1240	AM_RANGE( 0xd00000 , 0xd00001 )  AM_WRITE_LEGACY(mboard_write_LED_16 )
1200		AM_RANGE( 0xf00000 , 0xf00009 )  AM_READ_LEGACY(read_buttons_van16 )
1201		AM_RANGE( 0xd80000 , 0xd80001 )  AM_WRITE_LEGACY(write_LCD_data )
1202		AM_RANGE( 0xd80008 , 0xd80009 )  AM_WRITE_LEGACY(write_IOenables )
1203		//  AM_RANGE( 0xe80004 , 0xe80005 )  AM_WRITE_LEGACY(write_unknown2 )
1204		//  AM_RANGE( 0xe80002 , 0xe80003 )  AM_READ_LEGACY(read_unknown1 )
1205		//  AM_RANGE( 0xe80006 , 0xe80007 )  AM_READ_LEGACY(read_unknown3 )
	1241	AM_RANGE( 0xf00000 , 0xf00009 )  AM_READ(read_buttons_van16 )
	1242	AM_RANGE( 0xd80000 , 0xd80001 )  AM_WRITE(write_LCD_data )
	1243	AM_RANGE( 0xd80008 , 0xd80009 )  AM_WRITE(write_IOenables )
	1244	//  AM_RANGE( 0xe80004 , 0xe80005 )  AM_WRITE(write_unknown2 )
	1245	//  AM_RANGE( 0xe80002 , 0xe80003 )  AM_READ(read_unknown1 )
	1246	//  AM_RANGE( 0xe80006 , 0xe80007 )  AM_READ(read_unknown3 )
1206	1247
1207	1248
1208	1249	AM_RANGE( 0x400000, 0x47ffff )  AM_RAM      /* 512KB */
r14844	r14845
1212	1253
1213	1254	static ADDRESS_MAP_START(milano_mem , AS_PROGRAM, 8, polgar_state )
1214	1255	AM_RANGE( 0x0000, 0x1f9f ) AM_RAM
1215		AM_RANGE( 0x1fd0, 0x1fd0 ) AM_WRITE_LEGACY(milano_write_board )      // Chessboard
1216		AM_RANGE( 0x1fe0, 0x1fe0 ) AM_READ_LEGACY(milano_read_board )      // Chessboard
1217		AM_RANGE( 0x1fe8, 0x1fed ) AM_WRITE_LEGACY(milano_write_LED )   // Function LEDs
1218		AM_RANGE( 0x1fd8, 0x1fdf ) AM_READ_LEGACY(read_keys)
1219		AM_RANGE( 0x1ff0, 0x1ff0 ) AM_WRITE_LEGACY(write_polgar_IO)   // IO control
1220		AM_RANGE( 0x1fc0, 0x1fc0 ) AM_WRITE_LEGACY(write_LCD_polgar)   // LCD Char Reg. (latched)
	1256	AM_RANGE( 0x1fd0, 0x1fd0 ) AM_WRITE(milano_write_board )      // Chessboard
	1257	AM_RANGE( 0x1fe0, 0x1fe0 ) AM_READ(milano_read_board )      // Chessboard
	1258	AM_RANGE( 0x1fe8, 0x1fed ) AM_WRITE(milano_write_LED )   // Function LEDs
	1259	AM_RANGE( 0x1fd8, 0x1fdf ) AM_READ(read_keys)
	1260	AM_RANGE( 0x1ff0, 0x1ff0 ) AM_WRITE(write_polgar_IO)   // IO control
	1261	AM_RANGE( 0x1fc0, 0x1fc0 ) AM_WRITE(write_LCD_polgar)   // LCD Char Reg. (latched)
1221	1262	AM_RANGE( 0x2000, 0xffff ) AM_ROM
1222	1263	ADDRESS_MAP_END
1223	1264
1224	1265
1225	1266	static ADDRESS_MAP_START(academy_mem , AS_PROGRAM, 8, polgar_state )
1226	1267	AM_RANGE( 0x0000, 0x1fff ) AM_RAM
1227		AM_RANGE( 0x2400, 0x2400 ) AM_READ_LEGACY(read_keys_board_academy )
1228		AM_RANGE( 0x2800, 0x2800 ) AM_WRITE_LEGACY(academy_write_board )      // Chessboard
	1268	AM_RANGE( 0x2400, 0x2400 ) AM_READ(read_keys_board_academy )
	1269	AM_RANGE( 0x2800, 0x2800 ) AM_WRITE(academy_write_board )      // Chessboard
1229	1270	AM_RANGE( 0x2c00, 0x2c00 ) AM_WRITE_LEGACY(mboard_write_LED_8 )      // Chessboard
1230		AM_RANGE( 0x3002, 0x3002 ) AM_WRITE_LEGACY(beep_academy )
1231		AM_RANGE( 0x3001, 0x3001 ) AM_WRITE_LEGACY(academy_inhibitNMI )
1232		AM_RANGE( 0x3400, 0x3400 ) AM_WRITE_LEGACY(academy_write_LED )
1233		AM_RANGE( 0x3800, 0x3801 ) AM_WRITE_LEGACY(write_LCD_academy )
	1271	AM_RANGE( 0x3002, 0x3002 ) AM_WRITE(beep_academy )
	1272	AM_RANGE( 0x3001, 0x3001 ) AM_WRITE(academy_inhibitNMI )
	1273	AM_RANGE( 0x3400, 0x3400 ) AM_WRITE(academy_write_LED )
	1274	AM_RANGE( 0x3800, 0x3801 ) AM_WRITE(write_LCD_academy )
1234	1275	AM_RANGE( 0x4000, 0xffff ) AM_ROM
1235	1276	ADDRESS_MAP_END
1236	1277
1237	1278	static ADDRESS_MAP_START(monteciv_mem , AS_PROGRAM, 8, polgar_state )
1238	1279	AM_RANGE( 0x0000, 0x1fff ) AM_RAM
1239		AM_RANGE( 0x2400, 0x2400 ) AM_READ_LEGACY(read_keys_board_monteciv )
1240		AM_RANGE( 0x2800, 0x2800 ) AM_WRITE_LEGACY(academy_write_board )      // Chessboard
	1280	AM_RANGE( 0x2400, 0x2400 ) AM_READ(read_keys_board_monteciv )
	1281	AM_RANGE( 0x2800, 0x2800 ) AM_WRITE(academy_write_board )      // Chessboard
1241	1282	AM_RANGE( 0x2c00, 0x2c00 ) AM_WRITE_LEGACY(mboard_write_LED_8 )      // Chessboard
1242		AM_RANGE( 0x3400, 0x3400 ) AM_WRITE_LEGACY(academy_write_LED )         // Status LEDs
1243		AM_RANGE( 0x3000, 0x3001 ) AM_WRITE_LEGACY(monteciv_select_line )         // Select Keyline
1244		AM_RANGE( 0x3002, 0x3002 ) AM_WRITE_LEGACY(beep_academy )
1245		AM_RANGE( 0x3004, 0x3004 ) AM_WRITE_LEGACY(monteciv_write_LCD )
1246		AM_RANGE( 0x3005, 0x3005 ) AM_WRITE_LEGACY(monteciv_3005 )
1247		AM_RANGE( 0x3007, 0x3007 ) AM_WRITE_LEGACY(monteciv_3007 )
1248		AM_RANGE( 0x3006, 0x3006 ) AM_WRITE_LEGACY(monteciv_3006 )
1249		AM_RANGE( 0x2000, 0x2000 ) AM_WRITE_LEGACY(academy_inhibitNMI )
	1283	AM_RANGE( 0x3400, 0x3400 ) AM_WRITE(academy_write_LED )         // Status LEDs
	1284	AM_RANGE( 0x3000, 0x3001 ) AM_WRITE(monteciv_select_line )         // Select Keyline
	1285	AM_RANGE( 0x3002, 0x3002 ) AM_WRITE(beep_academy )
	1286	AM_RANGE( 0x3004, 0x3004 ) AM_WRITE(monteciv_write_LCD )
	1287	AM_RANGE( 0x3005, 0x3005 ) AM_WRITE(monteciv_3005 )
	1288	AM_RANGE( 0x3007, 0x3007 ) AM_WRITE(monteciv_3007 )
	1289	AM_RANGE( 0x3006, 0x3006 ) AM_WRITE(monteciv_3006 )
	1290	AM_RANGE( 0x2000, 0x2000 ) AM_WRITE(academy_inhibitNMI )
1250	1291	AM_RANGE( 0x8000, 0xffff ) AM_ROM
1251	1292	ADDRESS_MAP_END
1252	1293
1253	1294	static ADDRESS_MAP_START(megaiv_mem , AS_PROGRAM, 8, polgar_state )
1254	1295	AM_RANGE( 0x0000, 0x1fff ) AM_RAM
1255		/// AM_RANGE( 0x2400, 0x2400 ) AM_READ_LEGACY(read_keys_board_monteciv )
1256		AM_RANGE( 0x6800, 0x6800 ) AM_WRITE_LEGACY(academy_write_board )   // 2800 // Chessboard
	1296	/// AM_RANGE( 0x2400, 0x2400 ) AM_READ(read_keys_board_monteciv )
	1297	AM_RANGE( 0x6800, 0x6800 ) AM_WRITE(academy_write_board )   // 2800 // Chessboard
1257	1298	/// AM_RANGE( 0x2c00, 0x2c00 ) AM_WRITE_LEGACY(mboard_write_LED_8 )      // Chessboard
1258		/// AM_RANGE( 0x3400, 0x3400 ) AM_WRITE_LEGACY(academy_write_LED )           // Status LEDs
1259		AM_RANGE( 0x4400, 0x4400 ) AM_WRITE_LEGACY(megaiv_write_LED )   // 2400     // Select Keyline
1260		AM_RANGE( 0x7000, 0x7001 ) AM_WRITE_LEGACY(megaiv_IO )         // Select Keyline
1261		/// AM_RANGE( 0x3002, 0x3002 ) AM_WRITE_LEGACY(beep_academy )
1262		AM_RANGE( 0x4000, 0x4007 ) AM_READ_LEGACY(read_keys_megaiv ) // 3000-7 fixio
1263		AM_RANGE( 0x2c04, 0x2c04 ) AM_WRITE_LEGACY(monteciv_write_LCD ) // 2c04
1264		AM_RANGE( 0x2c05, 0x2c05 ) AM_WRITE_LEGACY(monteciv_3005 ) // 2c05
1265		AM_RANGE( 0x2c07, 0x2c07 ) AM_WRITE_LEGACY(monteciv_3007 ) // 2c07
1266		AM_RANGE( 0x2c06, 0x2c06 ) AM_WRITE_LEGACY(monteciv_3006 ) // 2c06
1267		/// AM_RANGE( 0x2000, 0x2000 ) AM_WRITE_LEGACY(academy_inhibitNMI )
	1299	/// AM_RANGE( 0x3400, 0x3400 ) AM_WRITE(academy_write_LED )           // Status LEDs
	1300	AM_RANGE( 0x4400, 0x4400 ) AM_WRITE(megaiv_write_LED )   // 2400     // Select Keyline
	1301	AM_RANGE( 0x7000, 0x7001 ) AM_WRITE(megaiv_IO )         // Select Keyline
	1302	/// AM_RANGE( 0x3002, 0x3002 ) AM_WRITE(beep_academy )
	1303	AM_RANGE( 0x4000, 0x4007 ) AM_READ(read_keys_megaiv ) // 3000-7 fixio
	1304	AM_RANGE( 0x2c04, 0x2c04 ) AM_WRITE(monteciv_write_LCD ) // 2c04
	1305	AM_RANGE( 0x2c05, 0x2c05 ) AM_WRITE(monteciv_3005 ) // 2c05
	1306	AM_RANGE( 0x2c07, 0x2c07 ) AM_WRITE(monteciv_3007 ) // 2c07
	1307	AM_RANGE( 0x2c06, 0x2c06 ) AM_WRITE(monteciv_3006 ) // 2c06
	1308	/// AM_RANGE( 0x2000, 0x2000 ) AM_WRITE(academy_inhibitNMI )
1268	1309	AM_RANGE( 0x8000, 0xffff ) AM_ROM
1269	1310	ADDRESS_MAP_END
1270	1311
r14844	r14845
1272	1313	AM_RANGE( 0x00000000, 0x0000ffff ) AM_ROM // OS
1273	1314	//  AM_RANGE( 0x00200000, 0x0020ffff ) AM_ROM AM_REGION("maincpu", 0)
1274	1315	AM_RANGE( 0x00ff0000, 0x00ff7fff ) AM_ROM AM_REGION("maincpu",10000) // Opening Book
1275		//  AM_RANGE( 0x00300000, 0x00300007 ) AM_READ_LEGACY(diablo68_aciaread)
1276		//  AM_RANGE( 0x00300000, 0x00300007 ) AM_READ_LEGACY(diablo68_aciawrite)
	1316	//  AM_RANGE( 0x00300000, 0x00300007 ) AM_READ(diablo68_aciaread)
	1317	//  AM_RANGE( 0x00300000, 0x00300007 ) AM_READ(diablo68_aciawrite)
1277	1318	//  AM_RANGE( 0x00300002, 0x00300003 ) AM_READ_LEGACY(diablo68_flags)
1278		AM_RANGE( 0x003a0000, 0x003a0001 ) AM_WRITE_LEGACY(diablo68_write_LCD)
1279		AM_RANGE( 0x003c0000, 0x003c0001 ) AM_WRITE_LEGACY(diablo68_reg_select)
	1319	AM_RANGE( 0x003a0000, 0x003a0001 ) AM_WRITE(diablo68_write_LCD)
	1320	AM_RANGE( 0x003c0000, 0x003c0001 ) AM_WRITE(diablo68_reg_select)
1280	1321	AM_RANGE( 0x00280000, 0x0028ffff ) AM_RAM  // hash tables
1281	1322	AM_RANGE( 0x00ff8000, 0x00ffffff ) AM_RAM
1282	1323	ADDRESS_MAP_END

src/mess/drivers/pc8801.c

r14844	r14845
226	226	struct { UINT8 r, g, b; } m_palram[8];
227	227	UINT8 m_dmac_ff;
228	228	UINT32 m_knj_addr[2];
	229	DECLARE_READ8_MEMBER(pc8801_alu_r);
	230	DECLARE_WRITE8_MEMBER(pc8801_alu_w);
	231	DECLARE_READ8_MEMBER(pc8801_wram_r);
	232	DECLARE_WRITE8_MEMBER(pc8801_wram_w);
	233	DECLARE_READ8_MEMBER(pc8801_ext_wram_r);
	234	DECLARE_WRITE8_MEMBER(pc8801_ext_wram_w);
	235	DECLARE_READ8_MEMBER(pc8801_nbasic_rom_r);
	236	DECLARE_READ8_MEMBER(pc8801_n88basic_rom_r);
	237	DECLARE_READ8_MEMBER(pc8801_gvram_r);
	238	DECLARE_WRITE8_MEMBER(pc8801_gvram_w);
	239	DECLARE_READ8_MEMBER(pc8801_high_wram_r);
	240	DECLARE_WRITE8_MEMBER(pc8801_high_wram_w);
	241	DECLARE_READ8_MEMBER(pc8801ma_dic_r);
	242	DECLARE_READ8_MEMBER(pc8801_cdbios_rom_r);
	243	DECLARE_READ8_MEMBER(pc8801_mem_r);
	244	DECLARE_WRITE8_MEMBER(pc8801_mem_w);
	245	DECLARE_READ8_MEMBER(pc8801_ctrl_r);
	246	DECLARE_WRITE8_MEMBER(pc8801_ctrl_w);
	247	DECLARE_READ8_MEMBER(pc8801_ext_rom_bank_r);
	248	DECLARE_WRITE8_MEMBER(pc8801_ext_rom_bank_w);
	249	DECLARE_WRITE8_MEMBER(pc8801_gfx_ctrl_w);
	250	DECLARE_READ8_MEMBER(pc8801_vram_select_r);
	251	DECLARE_WRITE8_MEMBER(pc8801_vram_select_w);
	252	DECLARE_WRITE8_MEMBER(i8214_irq_level_w);
	253	DECLARE_WRITE8_MEMBER(i8214_irq_mask_w);
	254	DECLARE_WRITE8_MEMBER(pc8801_irq_level_w);
	255	DECLARE_WRITE8_MEMBER(pc8801_irq_mask_w);
	256	DECLARE_READ8_MEMBER(pc8801_window_bank_r);
	257	DECLARE_WRITE8_MEMBER(pc8801_window_bank_w);
	258	DECLARE_WRITE8_MEMBER(pc8801_window_bank_inc_w);
	259	DECLARE_READ8_MEMBER(pc8801_misc_ctrl_r);
	260	DECLARE_WRITE8_MEMBER(pc8801_misc_ctrl_w);
	261	DECLARE_WRITE8_MEMBER(pc8801_bgpal_w);
	262	DECLARE_WRITE8_MEMBER(pc8801_palram_w);
	263	DECLARE_WRITE8_MEMBER(pc8801_layer_masking_w);
	264	DECLARE_READ8_MEMBER(pc8801_crtc_param_r);
	265	DECLARE_WRITE8_MEMBER(pc88_crtc_param_w);
	266	DECLARE_READ8_MEMBER(pc8801_crtc_status_r);
	267	DECLARE_WRITE8_MEMBER(pc88_crtc_cmd_w);
	268	DECLARE_WRITE8_MEMBER(pc8801_dmac_w);
	269	DECLARE_WRITE8_MEMBER(pc8801_dmac_mode_w);
	270	DECLARE_READ8_MEMBER(pc8801_extram_mode_r);
	271	DECLARE_WRITE8_MEMBER(pc8801_extram_mode_w);
	272	DECLARE_READ8_MEMBER(pc8801_extram_bank_r);
	273	DECLARE_WRITE8_MEMBER(pc8801_extram_bank_w);
	274	DECLARE_WRITE8_MEMBER(pc8801_alu_ctrl1_w);
	275	DECLARE_WRITE8_MEMBER(pc8801_alu_ctrl2_w);
	276	DECLARE_WRITE8_MEMBER(pc8801_pcg8100_w);
	277	DECLARE_READ8_MEMBER(sio_status_r);
	278	DECLARE_WRITE8_MEMBER(pc8801_txt_cmt_ctrl_w);
	279	DECLARE_READ8_MEMBER(pc8801_kanji_r);
	280	DECLARE_WRITE8_MEMBER(pc8801_kanji_w);
	281	DECLARE_READ8_MEMBER(pc8801_kanji_lv2_r);
	282	DECLARE_WRITE8_MEMBER(pc8801_kanji_lv2_w);
	283	DECLARE_WRITE8_MEMBER(pc8801_dic_bank_w);
	284	DECLARE_WRITE8_MEMBER(pc8801_dic_ctrl_w);
	285	DECLARE_READ8_MEMBER(pc8801_cdrom_r);
	286	DECLARE_WRITE8_MEMBER(pc8801_cdrom_w);
	287	DECLARE_READ8_MEMBER(pc8801_cpuclock_r);
	288	DECLARE_READ8_MEMBER(pc8801_baudrate_r);
	289	DECLARE_WRITE8_MEMBER(pc8801_baudrate_w);
	290	DECLARE_WRITE8_MEMBER(pc8801_rtc_w);
	291	DECLARE_WRITE8_MEMBER(upd765_mc_w);
	292	DECLARE_READ8_MEMBER(upd765_tc_r);
	293	DECLARE_WRITE8_MEMBER(fdc_irq_vector_w);
	294	DECLARE_WRITE8_MEMBER(fdc_drive_mode_w);
229	295	};
230	296
231	297	/*
r14844	r14845
623	689	return 0;
624	690	}
625	691
626		static READ8_HANDLER( pc8801_alu_r )
	692	READ8_MEMBER(pc8801_state::pc8801_alu_r)
627	693	{
628		pc8801_state *state = space->machine().driver_data<pc8801_state>();
629	694	int i;
630		UINT8 *gvram = space->machine().region("gvram")->base();
	695	UINT8 *gvram = machine().region("gvram")->base();
631	696	UINT8 b,r,g;
632	697
633	698	/* store data to ALU regs */
634	699	for(i=0;i<3;i++)
635		state->m_alu_reg[i] = gvram[i*0x4000 + offset];
	700	m_alu_reg[i] = gvram[i*0x4000 + offset];
636	701
637	702	b = gvram[offset + 0x0000];
638	703	r = gvram[offset + 0x4000];
639	704	g = gvram[offset + 0x8000];
640		if(!(state->m_alu_ctrl2 & 1)) { b^=0xff; }
641		if(!(state->m_alu_ctrl2 & 2)) { r^=0xff; }
642		if(!(state->m_alu_ctrl2 & 4)) { g^=0xff; }
	705	if(!(m_alu_ctrl2 & 1)) { b^=0xff; }
	706	if(!(m_alu_ctrl2 & 2)) { r^=0xff; }
	707	if(!(m_alu_ctrl2 & 4)) { g^=0xff; }
643	708
644	709	return b & r & g;
645	710	}
646	711
647		static WRITE8_HANDLER( pc8801_alu_w )
	712	WRITE8_MEMBER(pc8801_state::pc8801_alu_w)
648	713	{
649		pc8801_state *state = space->machine().driver_data<pc8801_state>();
650	714	int i;
651		UINT8 *gvram = space->machine().region("gvram")->base();
	715	UINT8 *gvram = machine().region("gvram")->base();
652	716
653		switch(state->m_alu_ctrl2 & 0x30) // alu write mode
	717	switch(m_alu_ctrl2 & 0x30) // alu write mode
654	718	{
655	719	case 0x00: //logic operation
656	720	{
r14844	r14845
658	722
659	723	for(i=0;i<3;i++)
660	724	{
661		logic_op = (state->m_alu_ctrl1 & (0x11 << i)) >> i;
	725	logic_op = (m_alu_ctrl1 & (0x11 << i)) >> i;
662	726
663	727	switch(logic_op)
664	728	{
r14844	r14845
674	738	case 0x10: // restore data from ALU regs
675	739	{
676	740	for(i=0;i<3;i++)
677		gvram[i*0x4000 + offset] = state->m_alu_reg[i];
	741	gvram[i*0x4000 + offset] = m_alu_reg[i];
678	742	}
679	743	break;
680	744
681	745	case 0x20: // swap ALU reg 1 into R GVRAM
682		gvram[0x0000 + offset] = state->m_alu_reg[1];
	746	gvram[0x0000 + offset] = m_alu_reg[1];
683	747	break;
684	748
685	749	case 0x30: // swap ALU reg 0 into B GVRAM
686		gvram[0x4000 + offset] = state->m_alu_reg[0];
	750	gvram[0x4000 + offset] = m_alu_reg[0];
687	751	break;
688	752	}
689	753	}
690	754
691	755
692		static READ8_HANDLER( pc8801_wram_r )
	756	READ8_MEMBER(pc8801_state::pc8801_wram_r)
693	757	{
694		UINT8 *work_ram = space->machine().region("wram")->base();
	758	UINT8 *work_ram = machine().region("wram")->base();
695	759
696	760	return work_ram[offset];
697	761	}
698	762
699		static WRITE8_HANDLER( pc8801_wram_w )
	763	WRITE8_MEMBER(pc8801_state::pc8801_wram_w)
700	764	{
701		UINT8 *work_ram = space->machine().region("wram")->base();
	765	UINT8 *work_ram = machine().region("wram")->base();
702	766
703	767	work_ram[offset] = data;
704	768	}
705	769
706		static READ8_HANDLER( pc8801_ext_wram_r )
	770	READ8_MEMBER(pc8801_state::pc8801_ext_wram_r)
707	771	{
708		UINT8 *ext_work_ram = space->machine().region("ewram")->base();
	772	UINT8 *ext_work_ram = machine().region("ewram")->base();
709	773
710	774	/* TODO: check max range here */
711	775
712	776	return ext_work_ram[offset];
713	777	}
714	778
715		static WRITE8_HANDLER( pc8801_ext_wram_w )
	779	WRITE8_MEMBER(pc8801_state::pc8801_ext_wram_w)
716	780	{
717		UINT8 *ext_work_ram = space->machine().region("ewram")->base();
	781	UINT8 *ext_work_ram = machine().region("ewram")->base();
718	782
719	783	/* TODO: check max range here */
720	784
721	785	ext_work_ram[offset] = data;
722	786	}
723	787
724		static READ8_HANDLER( pc8801_nbasic_rom_r )
	788	READ8_MEMBER(pc8801_state::pc8801_nbasic_rom_r)
725	789	{
726		UINT8 *n80_rom = space->machine().region("n80rom")->base();
	790	UINT8 *n80_rom = machine().region("n80rom")->base();
727	791
728	792	return n80_rom[offset];
729	793	}
730	794
731		static READ8_HANDLER( pc8801_n88basic_rom_r )
	795	READ8_MEMBER(pc8801_state::pc8801_n88basic_rom_r)
732	796	{
733		UINT8 *n88_rom = space->machine().region("n88rom")->base();
	797	UINT8 *n88_rom = machine().region("n88rom")->base();
734	798
735	799	return n88_rom[offset];
736	800	}
737	801
738		static READ8_HANDLER( pc8801_gvram_r )
	802	READ8_MEMBER(pc8801_state::pc8801_gvram_r)
739	803	{
740		UINT8 *gvram = space->machine().region("gvram")->base();
	804	UINT8 *gvram = machine().region("gvram")->base();
741	805
742	806	return gvram[offset];
743	807	}
744	808
745		static WRITE8_HANDLER( pc8801_gvram_w )
	809	WRITE8_MEMBER(pc8801_state::pc8801_gvram_w)
746	810	{
747		UINT8 *gvram = space->machine().region("gvram")->base();
	811	UINT8 *gvram = machine().region("gvram")->base();
748	812
749	813	gvram[offset] = data;
750	814	}
751	815
752		static READ8_HANDLER( pc8801_high_wram_r )
	816	READ8_MEMBER(pc8801_state::pc8801_high_wram_r)
753	817	{
754		UINT8 *hi_work_ram = space->machine().region("hiwram")->base();
	818	UINT8 *hi_work_ram = machine().region("hiwram")->base();
755	819
756	820	return hi_work_ram[offset];
757	821	}
758	822
759		static WRITE8_HANDLER( pc8801_high_wram_w )
	823	WRITE8_MEMBER(pc8801_state::pc8801_high_wram_w)
760	824	{
761		UINT8 *hi_work_ram = space->machine().region("hiwram")->base();
	825	UINT8 *hi_work_ram = machine().region("hiwram")->base();
762	826
763	827	hi_work_ram[offset] = data;
764	828	}
765	829
766		static READ8_HANDLER( pc8801ma_dic_r )
	830	READ8_MEMBER(pc8801_state::pc8801ma_dic_r)
767	831	{
768		UINT8 *dic_rom = space->machine().region("dictionary")->base();
	832	UINT8 *dic_rom = machine().region("dictionary")->base();
769	833
770	834	return dic_rom[offset];
771	835	}
772	836
773		static READ8_HANDLER( pc8801_cdbios_rom_r )
	837	READ8_MEMBER(pc8801_state::pc8801_cdbios_rom_r)
774	838	{
775		UINT8 *cdrom_bios = space->machine().region("cdrom")->base();
	839	UINT8 *cdrom_bios = machine().region("cdrom")->base();
776	840
777	841	return cdrom_bios[offset];
778	842	}
779	843
780		static READ8_HANDLER( pc8801_mem_r )
	844	READ8_MEMBER(pc8801_state::pc8801_mem_r)
781	845	{
782		pc8801_state *state = space->machine().driver_data<pc8801_state>();
783	846	if(offset <= 0x7fff)
784	847	{
785		if(state->m_extram_mode & 1)
786		return pc8801_ext_wram_r(space,offset | (state->m_extram_bank * 0x8000));
	848	if(m_extram_mode & 1)
	849	return pc8801_ext_wram_r(space,offset | (m_extram_bank * 0x8000));
787	850
788		if(state->m_gfx_ctrl & 2)
	851	if(m_gfx_ctrl & 2)
789	852	return pc8801_wram_r(space,offset);
790	853
791		if(state->m_has_cdrom && state->m_cdrom_reg[9] & 0x10)
792		return pc8801_cdbios_rom_r(space,(offset & 0x7fff) | ((state->m_gfx_ctrl & 4) ? 0x8000 : 0x0000));
	854	if(m_has_cdrom && m_cdrom_reg[9] & 0x10)
	855	return pc8801_cdbios_rom_r(space,(offset & 0x7fff) | ((m_gfx_ctrl & 4) ? 0x8000 : 0x0000));
793	856
794		if(state->m_gfx_ctrl & 4)
	857	if(m_gfx_ctrl & 4)
795	858	return pc8801_nbasic_rom_r(space,offset);
796	859
797		if(offset >= 0x6000 && offset <= 0x7fff && ((state->m_ext_rom_bank & 1) == 0))
798		return pc8801_n88basic_rom_r(space,0x8000 + (offset & 0x1fff) + (0x2000 * (state->m_misc_ctrl & 3)));
	860	if(offset >= 0x6000 && offset <= 0x7fff && ((m_ext_rom_bank & 1) == 0))
	861	return pc8801_n88basic_rom_r(space,0x8000 + (offset & 0x1fff) + (0x2000 * (m_misc_ctrl & 3)));
799	862
800	863	return pc8801_n88basic_rom_r(space,offset);
801	864	}
r14844	r14845
803	866	{
804	867	UINT32 window_offset;
805	868
806		if(state->m_gfx_ctrl & 6) //wram read select or n basic select banks this as normal wram
	869	if(m_gfx_ctrl & 6) //wram read select or n basic select banks this as normal wram
807	870	return pc8801_wram_r(space,offset);
808	871
809		window_offset = (offset & 0x3ff) + (state->m_window_offset_bank << 8);
	872	window_offset = (offset & 0x3ff) + (m_window_offset_bank << 8);
810	873
811	874	if((window_offset & 0xf000) == 0xf000)
812	875	printf("Read from 0xf000 - 0xffff window offset\n"); //accessed by Castle Excellent, no noticeable quirk
813	876
814		if(((window_offset & 0xf000) == 0xf000) && (state->m_misc_ctrl & 0x10))
	877	if(((window_offset & 0xf000) == 0xf000) && (m_misc_ctrl & 0x10))
815	878	return pc8801_high_wram_r(space,window_offset & 0xfff);
816	879
817	880	return pc8801_wram_r(space,window_offset);
r14844	r14845
822	885	}
823	886	else if(offset >= 0xc000 && offset <= 0xffff)
824	887	{
825		if(state->m_has_dictionary && state->m_dic_ctrl)
826		return pc8801ma_dic_r(space,(offset & 0x3fff) + ((state->m_dic_bank & 0x1f) * 0x4000));
	888	if(m_has_dictionary && m_dic_ctrl)
	889	return pc8801ma_dic_r(space,(offset & 0x3fff) + ((m_dic_bank & 0x1f) * 0x4000));
827	890
828		if(state->m_misc_ctrl & 0x40)
	891	if(m_misc_ctrl & 0x40)
829	892	{
830		state->m_vram_sel = 3;
831		if(state->m_alu_ctrl2 & 0x80)
	893	m_vram_sel = 3;
	894	if(m_alu_ctrl2 & 0x80)
832	895	return pc8801_alu_r(space,offset & 0x3fff);
833	896	}
834	897
835		if(state->m_vram_sel == 3)
	898	if(m_vram_sel == 3)
836	899	{
837		if(offset >= 0xf000 && offset <= 0xffff && (state->m_misc_ctrl & 0x10))
	900	if(offset >= 0xf000 && offset <= 0xffff && (m_misc_ctrl & 0x10))
838	901	return pc8801_high_wram_r(space,offset & 0xfff);
839	902
840	903	return pc8801_wram_r(space,offset);
841	904	}
842	905
843		return pc8801_gvram_r(space,(offset & 0x3fff) + (0x4000 * state->m_vram_sel));
	906	return pc8801_gvram_r(space,(offset & 0x3fff) + (0x4000 * m_vram_sel));
844	907	}
845	908
846	909	return 0xff;
847	910	}
848	911
849		static WRITE8_HANDLER( pc8801_mem_w )
	912	WRITE8_MEMBER(pc8801_state::pc8801_mem_w)
850	913	{
851		pc8801_state *state = space->machine().driver_data<pc8801_state>();
852	914	if(offset <= 0x7fff)
853	915	{
854		if(state->m_extram_mode & 0x10)
855		pc8801_ext_wram_w(space,offset | (state->m_extram_bank * 0x8000),data);
	916	if(m_extram_mode & 0x10)
	917	pc8801_ext_wram_w(space,offset | (m_extram_bank * 0x8000),data);
856	918	else
857	919	pc8801_wram_w(space,offset,data);
858	920
r14844	r14845
860	922	}
861	923	else if(offset >= 0x8000 && offset <= 0x83ff)
862	924	{
863		if(state->m_gfx_ctrl & 6) //wram read select or n basic select banks this as normal wram
	925	if(m_gfx_ctrl & 6) //wram read select or n basic select banks this as normal wram
864	926	pc8801_wram_w(space,offset,data);
865	927	else
866	928	{
867	929	UINT32 window_offset;
868	930
869		window_offset = (offset & 0x3ff) + (state->m_window_offset_bank << 8);
	931	window_offset = (offset & 0x3ff) + (m_window_offset_bank << 8);
870	932
871	933	if((window_offset & 0xf000) == 0xf000)
872	934	printf("Write to 0xf000 - 0xffff window offset\n"); //accessed by Castle Excellent, no noticeable quirk
873	935
874		if(((window_offset & 0xf000) == 0xf000) && (state->m_misc_ctrl & 0x10))
	936	if(((window_offset & 0xf000) == 0xf000) && (m_misc_ctrl & 0x10))
875	937	pc8801_high_wram_w(space,window_offset & 0xfff,data);
876	938	else
877	939	pc8801_wram_w(space,window_offset,data);
r14844	r14845
886	948	}
887	949	else if(offset >= 0xc000 && offset <= 0xffff)
888	950	{
889		if(state->m_misc_ctrl & 0x40)
	951	if(m_misc_ctrl & 0x40)
890	952	{
891		state->m_vram_sel = 3;
892		if(state->m_alu_ctrl2 & 0x80)
	953	m_vram_sel = 3;
	954	if(m_alu_ctrl2 & 0x80)
893	955	{
894	956	pc8801_alu_w(space,offset & 0x3fff,data);
895	957	return;
896	958	}
897	959	}
898	960
899		if(state->m_vram_sel == 3)
	961	if(m_vram_sel == 3)
900	962	{
901		if(offset >= 0xf000 && offset <= 0xffff && (state->m_misc_ctrl & 0x10))
	963	if(offset >= 0xf000 && offset <= 0xffff && (m_misc_ctrl & 0x10))
902	964	{
903	965	pc8801_high_wram_w(space,offset & 0xfff,data);
904	966	return;
r14844	r14845
908	970	return;
909	971	}
910	972
911		pc8801_gvram_w(space,(offset & 0x3fff) + (0x4000 * state->m_vram_sel),data);
	973	pc8801_gvram_w(space,(offset & 0x3fff) + (0x4000 * m_vram_sel),data);
912	974	return;
913	975	}
914	976	}
915	977
916	978	static ADDRESS_MAP_START( pc8801_mem, AS_PROGRAM, 8, pc8801_state )
917		AM_RANGE(0x0000, 0xffff) AM_READWRITE_LEGACY(pc8801_mem_r,pc8801_mem_w)
	979	AM_RANGE(0x0000, 0xffff) AM_READWRITE(pc8801_mem_r,pc8801_mem_w)
918	980	ADDRESS_MAP_END
919	981
920		static READ8_HANDLER( pc8801_ctrl_r )
	982	READ8_MEMBER(pc8801_state::pc8801_ctrl_r)
921	983	{
922	984	/*
923	985	11-- ----
r14844	r14845
928	990	---- --x- monitor refresh rate DIP-SW
929	991	---- ---x (pbsy?)
930	992	*/
931		return input_port_read(space->machine(), "CTRL");
	993	return input_port_read(machine(), "CTRL");
932	994	}
933	995
934		static WRITE8_HANDLER( pc8801_ctrl_w )
	996	WRITE8_MEMBER(pc8801_state::pc8801_ctrl_w)
935	997	{
936	998	/*
937	999	x--- ---- SING (buzzer mask?)
r14844	r14845
941	1003	---- --x- upd1990a strobe bit
942	1004	*/
943	1005
944		pc8801_state *state = space->machine().driver_data<pc8801_state>();
945	1006
946		state->m_rtc->stb_w((data & 2) >> 1);
947		state->m_rtc->clk_w((data & 4) >> 2);
	1007	m_rtc->stb_w((data & 2) >> 1);
	1008	m_rtc->clk_w((data & 4) >> 2);
948	1009
949		if(((state->m_device_ctrl_data & 0x20) == 0x00) && ((data & 0x20) == 0x20))
950		beep_set_state(space->machine().device(BEEPER_TAG),1);
	1010	if(((m_device_ctrl_data & 0x20) == 0x00) && ((data & 0x20) == 0x20))
	1011	beep_set_state(machine().device(BEEPER_TAG),1);
951	1012
952		if(((state->m_device_ctrl_data & 0x20) == 0x20) && ((data & 0x20) == 0x00))
953		beep_set_state(space->machine().device(BEEPER_TAG),0);
	1013	if(((m_device_ctrl_data & 0x20) == 0x20) && ((data & 0x20) == 0x00))
	1014	beep_set_state(machine().device(BEEPER_TAG),0);
954	1015
955	1016	/* TODO: is SING a buzzer mask? Bastard Special relies on this ... */
956		if(state->m_device_ctrl_data & 0x80)
957		beep_set_state(space->machine().device(BEEPER_TAG),0);
	1017	if(m_device_ctrl_data & 0x80)
	1018	beep_set_state(machine().device(BEEPER_TAG),0);
958	1019
959		state->m_device_ctrl_data = data;
	1020	m_device_ctrl_data = data;
960	1021	}
961	1022
962		static READ8_HANDLER( pc8801_ext_rom_bank_r )
	1023	READ8_MEMBER(pc8801_state::pc8801_ext_rom_bank_r)
963	1024	{
964		pc8801_state *state = space->machine().driver_data<pc8801_state>();
965		return state->m_ext_rom_bank;
	1025	return m_ext_rom_bank;
966	1026	}
967	1027
968		static WRITE8_HANDLER( pc8801_ext_rom_bank_w )
	1028	WRITE8_MEMBER(pc8801_state::pc8801_ext_rom_bank_w)
969	1029	{
970		pc8801_state *state = space->machine().driver_data<pc8801_state>();
971		state->m_ext_rom_bank = data;
	1030	m_ext_rom_bank = data;
972	1031	}
973	1032
974	1033	static void pc8801_dynamic_res_change(running_machine &machine)
r14844	r14845
981	1040	machine.primary_screen->configure(640, 480, visarea, machine.primary_screen->frame_period().attoseconds);
982	1041	}
983	1042
984		static WRITE8_HANDLER( pc8801_gfx_ctrl_w )
	1043	WRITE8_MEMBER(pc8801_state::pc8801_gfx_ctrl_w)
985	1044	{
986		pc8801_state *state = space->machine().driver_data<pc8801_state>();
987	1045	/*
988	1046	--x- ---- VRAM y 25 (1) / 20 (0)
989	1047	---x ---- graphic color yes (1) / no (0)
r14844	r14845
993	1051	---- ---x VRAM 200 lines (1) / 400 lines (0), 15 KHz / 24 KHz
994	1052	*/
995	1053
996		state->m_gfx_ctrl = data;
	1054	m_gfx_ctrl = data;
997	1055
998		pc8801_dynamic_res_change(space->machine());
	1056	pc8801_dynamic_res_change(machine());
999	1057	}
1000	1058
1001		static READ8_HANDLER( pc8801_vram_select_r )
	1059	READ8_MEMBER(pc8801_state::pc8801_vram_select_r)
1002	1060	{
1003		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1004		return 0xf8 | ((state->m_vram_sel == 3) ? 0 : (1 << state->m_vram_sel));
	1061	return 0xf8 | ((m_vram_sel == 3) ? 0 : (1 << m_vram_sel));
1005	1062	}
1006	1063
1007		static WRITE8_HANDLER( pc8801_vram_select_w )
	1064	WRITE8_MEMBER(pc8801_state::pc8801_vram_select_w)
1008	1065	{
1009		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1010		state->m_vram_sel = offset & 3;
	1066	m_vram_sel = offset & 3;
1011	1067	}
1012	1068
1013	1069	#ifdef USE_PROPER_I8214
1014	1070
1015		static WRITE8_HANDLER( i8214_irq_level_w )
	1071	WRITE8_MEMBER(pc8801_state::i8214_irq_level_w)
1016	1072	{
1017	1073	if(data & 8)
1018	1074	m_pic->b_w(7);
r14844	r14845
1020	1076	m_pic->b_w(data & 0x07);
1021	1077	}
1022	1078
1023		static WRITE8_HANDLER( i8214_irq_mask_w )
	1079	WRITE8_MEMBER(pc8801_state::i8214_irq_mask_w)
1024	1080	{
1025		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1026		state->m_timer_irq_mask = data & 1;
1027		state->m_vblank_irq_mask = data & 2;
	1081	m_timer_irq_mask = data & 1;
	1082	m_vblank_irq_mask = data & 2;
1028	1083	}
1029	1084
1030	1085
1031	1086	#else
1032		static WRITE8_HANDLER( pc8801_irq_level_w )
	1087	WRITE8_MEMBER(pc8801_state::pc8801_irq_level_w)
1033	1088	{
1034		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1035	1089	if(data & 8)
1036		state->m_i8214_irq_level = 7;
	1090	m_i8214_irq_level = 7;
1037	1091	else
1038		state->m_i8214_irq_level = data & 7;
	1092	m_i8214_irq_level = data & 7;
1039	1093	}
1040	1094
1041	1095
1042		static WRITE8_HANDLER( pc8801_irq_mask_w )
	1096	WRITE8_MEMBER(pc8801_state::pc8801_irq_mask_w)
1043	1097	{
1044		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1045		state->m_timer_irq_mask = data & 1;
1046		state->m_vrtc_irq_mask = data & 2;
	1098	m_timer_irq_mask = data & 1;
	1099	m_vrtc_irq_mask = data & 2;
1047	1100
1048		if(state->m_timer_irq_mask == 0)
1049		state->m_timer_irq_latch = 0;
	1101	if(m_timer_irq_mask == 0)
	1102	m_timer_irq_latch = 0;
1050	1103
1051		if(state->m_vrtc_irq_mask == 0)
1052		state->m_vrtc_irq_latch = 0;
	1104	if(m_vrtc_irq_mask == 0)
	1105	m_vrtc_irq_latch = 0;
1053	1106
1054	1107	//if(data & 4)
1055	1108	//  printf("IRQ mask %02x\n",data);
1056	1109	}
1057	1110	#endif
1058	1111
1059		static READ8_HANDLER( pc8801_window_bank_r )
	1112	READ8_MEMBER(pc8801_state::pc8801_window_bank_r)
1060	1113	{
1061		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1062		return state->m_window_offset_bank;
	1114	return m_window_offset_bank;
1063	1115	}
1064	1116
1065		static WRITE8_HANDLER( pc8801_window_bank_w )
	1117	WRITE8_MEMBER(pc8801_state::pc8801_window_bank_w)
1066	1118	{
1067		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1068		state->m_window_offset_bank = data;
	1119	m_window_offset_bank = data;
1069	1120	}
1070	1121
1071		static WRITE8_HANDLER( pc8801_window_bank_inc_w )
	1122	WRITE8_MEMBER(pc8801_state::pc8801_window_bank_inc_w)
1072	1123	{
1073		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1074		state->m_window_offset_bank++;
1075		state->m_window_offset_bank&=0xff;
	1124	m_window_offset_bank++;
	1125	m_window_offset_bank&=0xff;
1076	1126	}
1077	1127
1078		static READ8_HANDLER( pc8801_misc_ctrl_r )
	1128	READ8_MEMBER(pc8801_state::pc8801_misc_ctrl_r)
1079	1129	{
1080		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1081		return state->m_misc_ctrl;
	1130	return m_misc_ctrl;
1082	1131	}
1083	1132
1084		static WRITE8_HANDLER( pc8801_misc_ctrl_w )
	1133	WRITE8_MEMBER(pc8801_state::pc8801_misc_ctrl_w)
1085	1134	{
1086		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1087		state->m_misc_ctrl = data;
	1135	m_misc_ctrl = data;
1088	1136
1089	1137	#ifdef USE_PROPER_I8214
1090		state->m_sound_irq_mask = ((data & 0x80) == 0);
	1138	m_sound_irq_mask = ((data & 0x80) == 0);
1091	1139	#else
1092		state->m_sound_irq_mask = ((data & 0x80) == 0);
	1140	m_sound_irq_mask = ((data & 0x80) == 0);
1093	1141
1094		if(state->m_sound_irq_mask == 0)
1095		state->m_sound_irq_latch = 0;
	1142	if(m_sound_irq_mask == 0)
	1143	m_sound_irq_latch = 0;
1096	1144	#endif
1097	1145	}
1098	1146
1099		static WRITE8_HANDLER( pc8801_bgpal_w )
	1147	WRITE8_MEMBER(pc8801_state::pc8801_bgpal_w)
1100	1148	{
1101	1149	if(data)
1102	1150	printf("BG Pal %02x\n",data);
1103	1151	}
1104	1152
1105		static WRITE8_HANDLER( pc8801_palram_w )
	1153	WRITE8_MEMBER(pc8801_state::pc8801_palram_w)
1106	1154	{
1107		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1108	1155
1109		if(state->m_misc_ctrl & 0x20) //analog palette
	1156	if(m_misc_ctrl & 0x20) //analog palette
1110	1157	{
1111	1158	if((data & 0x40) == 0)
1112	1159	{
1113		state->m_palram[offset].b = data & 0x7;
1114		state->m_palram[offset].r = (data & 0x38) >> 3;
	1160	m_palram[offset].b = data & 0x7;
	1161	m_palram[offset].r = (data & 0x38) >> 3;
1115	1162	}
1116	1163	else
1117	1164	{
1118		state->m_palram[offset].g = data & 0x7;
	1165	m_palram[offset].g = data & 0x7;
1119	1166	}
1120	1167	}
1121	1168	else //digital palette
1122	1169	{
1123		state->m_palram[offset].b = data & 1 ? 7 : 0;
1124		state->m_palram[offset].r = data & 2 ? 7 : 0;
1125		state->m_palram[offset].g = data & 4 ? 7 : 0;
	1170	m_palram[offset].b = data & 1 ? 7 : 0;
	1171	m_palram[offset].r = data & 2 ? 7 : 0;
	1172	m_palram[offset].g = data & 4 ? 7 : 0;
1126	1173	}
1127	1174
1128		palette_set_color_rgb(space->machine(), offset, pal3bit(state->m_palram[offset].r), pal3bit(state->m_palram[offset].g), pal3bit(state->m_palram[offset].b));
	1175	palette_set_color_rgb(machine(), offset, pal3bit(m_palram[offset].r), pal3bit(m_palram[offset].g), pal3bit(m_palram[offset].b));
1129	1176	}
1130	1177
1131		static WRITE8_HANDLER( pc8801_layer_masking_w )
	1178	WRITE8_MEMBER(pc8801_state::pc8801_layer_masking_w)
1132	1179	{
1133		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1134	1180	/*
1135	1181	---- x--- green gvram masked flag
1136	1182	---- -x-- red gvram masked flag
r14844	r14845
1138	1184	---- ---x text vram masked
1139	1185	*/
1140	1186
1141		state->m_layer_mask = data;
	1187	m_layer_mask = data;
1142	1188	}
1143	1189
1144		static READ8_HANDLER( pc8801_crtc_param_r )
	1190	READ8_MEMBER(pc8801_state::pc8801_crtc_param_r)
1145	1191	{
1146	1192	return 0xff;
1147	1193	}
1148	1194
1149		static WRITE8_HANDLER( pc88_crtc_param_w )
	1195	WRITE8_MEMBER(pc8801_state::pc88_crtc_param_w)
1150	1196	{
1151		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1152		if(state->m_crtc.param_count < 5)
	1197	if(m_crtc.param_count < 5)
1153	1198	{
1154		state->m_crtc.param[state->m_crtc.cmd][state->m_crtc.param_count] = data;
1155		state->m_crtc.param_count++;
	1199	m_crtc.param[m_crtc.cmd][m_crtc.param_count] = data;
	1200	m_crtc.param_count++;
1156	1201	}
1157	1202	}
1158	1203
1159		static READ8_HANDLER( pc8801_crtc_status_r )
	1204	READ8_MEMBER(pc8801_state::pc8801_crtc_status_r)
1160	1205	{
1161		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1162	1206	/*
1163	1207	---x ---- video enable
1164	1208	---- x--- DMA is running
r14844	r14845
1167	1211	---- ---x light pen input
1168	1212	*/
1169	1213
1170		return state->m_crtc.status;
	1214	return m_crtc.status;
1171	1215	}
1172	1216
1173	1217	static const char *const crtc_command[] =
r14844	r14845
1182	1226	"Read Status"                  // 7
1183	1227	};
1184	1228
1185		static WRITE8_HANDLER( pc88_crtc_cmd_w )
	1229	WRITE8_MEMBER(pc8801_state::pc88_crtc_cmd_w)
1186	1230	{
1187		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1188		state->m_crtc.cmd = (data & 0xe0) >> 5;
1189		state->m_crtc.param_count = 0;
	1231	m_crtc.cmd = (data & 0xe0) >> 5;
	1232	m_crtc.param_count = 0;
1190	1233
1191		switch(state->m_crtc.cmd)
	1234	switch(m_crtc.cmd)
1192	1235	{
1193	1236	case 0:  // reset CRTC
1194		state->m_crtc.status &= (~0x16);
	1237	m_crtc.status &= (~0x16);
1195	1238	break;
1196	1239	case 1:  // start display
1197		state->m_crtc.status |= 0x10;
1198		state->m_crtc.status &= (~0x08);
	1240	m_crtc.status |= 0x10;
	1241	m_crtc.status &= (~0x08);
1199	1242	if(data & 1)
1200	1243	printf("CRTC reverse display ON\n");
1201	1244	break;
1202	1245	case 2:  // set irq mask
1203		state->m_crtc.irq_mask = data & 3;
	1246	m_crtc.irq_mask = data & 3;
1204	1247	break;
1205	1248	case 3:  // read light pen
1206		state->m_crtc.status &= (~0x01);
	1249	m_crtc.status &= (~0x01);
1207	1250	break;
1208	1251	case 4:  // load cursor position ON/OFF
1209		state->m_crtc.cursor_on = data & 1;
	1252	m_crtc.cursor_on = data & 1;
1210	1253	break;
1211	1254	case 5:  // reset IRQ
1212	1255	case 6:  // reset counters
1213		state->m_crtc.status &= (~0x06);
	1256	m_crtc.status &= (~0x06);
1214	1257	break;
1215	1258	}
1216	1259
r14844	r14845
1218	1261	//  printf("CRTC cmd %s polled\n",crtc_command[data >> 5]);
1219	1262	}
1220	1263
1221		static WRITE8_HANDLER( pc8801_dmac_w )
	1264	WRITE8_MEMBER(pc8801_state::pc8801_dmac_w)
1222	1265	{
1223		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1224	1266
1225	1267	if(offset & 1)
1226		state->m_dma_counter[offset >> 1] = (state->m_dmac_ff) ? (state->m_dma_counter[offset >> 1]&0xff)|(data<<8) : (state->m_dma_counter[offset >> 1]&0xff00)|(data&0xff);
	1268	m_dma_counter[offset >> 1] = (m_dmac_ff) ? (m_dma_counter[offset >> 1]&0xff)|(data<<8) : (m_dma_counter[offset >> 1]&0xff00)|(data&0xff);
1227	1269	else
1228		state->m_dma_address[offset >> 1] = (state->m_dmac_ff) ? (state->m_dma_address[offset >> 1]&0xff)|(data<<8) : (state->m_dma_address[offset >> 1]&0xff00)|(data&0xff);
	1270	m_dma_address[offset >> 1] = (m_dmac_ff) ? (m_dma_address[offset >> 1]&0xff)|(data<<8) : (m_dma_address[offset >> 1]&0xff00)|(data&0xff);
1229	1271
1230		state->m_dmac_ff ^= 1;
	1272	m_dmac_ff ^= 1;
1231	1273	}
1232	1274
1233		static WRITE8_HANDLER( pc8801_dmac_mode_w )
	1275	WRITE8_MEMBER(pc8801_state::pc8801_dmac_mode_w)
1234	1276	{
1235		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1236		state->m_dmac_mode = data;
	1277	m_dmac_mode = data;
1237	1278	}
1238	1279
1239		static READ8_HANDLER( pc8801_extram_mode_r )
	1280	READ8_MEMBER(pc8801_state::pc8801_extram_mode_r)
1240	1281	{
1241		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1242		return (state->m_extram_mode ^ 0x11) | 0xee;
	1282	return (m_extram_mode ^ 0x11) | 0xee;
1243	1283	}
1244	1284
1245		static WRITE8_HANDLER( pc8801_extram_mode_w )
	1285	WRITE8_MEMBER(pc8801_state::pc8801_extram_mode_w)
1246	1286	{
1247		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1248	1287	/*
1249	1288	---x ---- Write EXT RAM access at 0x0000 - 0x7fff
1250	1289	---- ---x Read EXT RAM access at 0x0000 - 0x7fff
1251	1290	*/
1252	1291
1253		state->m_extram_mode = data & 0x11;
	1292	m_extram_mode = data & 0x11;
1254	1293	}
1255	1294
1256		static READ8_HANDLER( pc8801_extram_bank_r )
	1295	READ8_MEMBER(pc8801_state::pc8801_extram_bank_r)
1257	1296	{
1258		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1259		return state->m_extram_bank;
	1297	return m_extram_bank;
1260	1298	}
1261	1299
1262		static WRITE8_HANDLER( pc8801_extram_bank_w )
	1300	WRITE8_MEMBER(pc8801_state::pc8801_extram_bank_w)
1263	1301	{
1264		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1265		state->m_extram_bank = data;
	1302	m_extram_bank = data;
1266	1303	}
1267	1304
1268		static WRITE8_HANDLER( pc8801_alu_ctrl1_w )
	1305	WRITE8_MEMBER(pc8801_state::pc8801_alu_ctrl1_w)
1269	1306	{
1270		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1271		state->m_alu_ctrl1 = data;
	1307	m_alu_ctrl1 = data;
1272	1308	}
1273	1309
1274		static WRITE8_HANDLER( pc8801_alu_ctrl2_w )
	1310	WRITE8_MEMBER(pc8801_state::pc8801_alu_ctrl2_w)
1275	1311	{
1276		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1277		state->m_alu_ctrl2 = data;
	1312	m_alu_ctrl2 = data;
1278	1313	}
1279	1314
1280		static WRITE8_HANDLER( pc8801_pcg8100_w )
	1315	WRITE8_MEMBER(pc8801_state::pc8801_pcg8100_w)
1281	1316	{
1282	1317	if(data)
1283	1318	printf("Write to PCG-8100 %02x %02x\n",offset,data);
1284	1319	}
1285	1320
1286	1321	/* Balance of Power temp work-around */
1287		static READ8_HANDLER( sio_status_r )
	1322	READ8_MEMBER(pc8801_state::sio_status_r)
1288	1323	{
1289	1324	return 0;
1290	1325	}
1291	1326
1292		static WRITE8_HANDLER( pc8801_txt_cmt_ctrl_w )
	1327	WRITE8_MEMBER(pc8801_state::pc8801_txt_cmt_ctrl_w)
1293	1328	{
1294		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1295	1329	/* bits 2 to 5 are cmt related */
1296	1330
1297		state->m_txt_width = data & 1;
1298		state->m_txt_color = data & 2;
	1331	m_txt_width = data & 1;
	1332	m_txt_color = data & 2;
1299	1333	}
1300	1334
1301	1335
1302		static READ8_HANDLER( pc8801_kanji_r )
	1336	READ8_MEMBER(pc8801_state::pc8801_kanji_r)
1303	1337	{
1304		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1305		UINT8 *knj_rom = space->machine().region("kanji")->base();
	1338	UINT8 *knj_rom = machine().region("kanji")->base();
1306	1339	if((offset & 2) == 0)
1307		return knj_rom[state->m_knj_addr[0]*2+((offset & 1) ^ 1)];
	1340	return knj_rom[m_knj_addr[0]*2+((offset & 1) ^ 1)];
1308	1341
1309	1342	return 0xff;
1310	1343	}
1311	1344
1312		static WRITE8_HANDLER( pc8801_kanji_w )
	1345	WRITE8_MEMBER(pc8801_state::pc8801_kanji_w)
1313	1346	{
1314		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1315	1347	if((offset & 2) == 0)
1316		state->m_knj_addr[0] = ((offset & 1) == 0) ? ((state->m_knj_addr[0]&0xff00)|(data&0xff)) : ((state->m_knj_addr[0]&0x00ff)|(data<<8));
	1348	m_knj_addr[0] = ((offset & 1) == 0) ? ((m_knj_addr[0]&0xff00)|(data&0xff)) : ((m_knj_addr[0]&0x00ff)|(data<<8));
1317	1349	}
1318	1350
1319		static READ8_HANDLER( pc8801_kanji_lv2_r )
	1351	READ8_MEMBER(pc8801_state::pc8801_kanji_lv2_r)
1320	1352	{
1321		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1322		UINT8 *knj_rom = space->machine().region("kanji")->base() + 0x20000;
	1353	UINT8 *knj_rom = machine().region("kanji")->base() + 0x20000;
1323	1354	if((offset & 2) == 0)
1324		return knj_rom[state->m_knj_addr[1]*2+((offset & 1) ^ 1)];
	1355	return knj_rom[m_knj_addr[1]*2+((offset & 1) ^ 1)];
1325	1356
1326	1357	return 0xff;
1327	1358	}
1328	1359
1329		static WRITE8_HANDLER( pc8801_kanji_lv2_w )
	1360	WRITE8_MEMBER(pc8801_state::pc8801_kanji_lv2_w)
1330	1361	{
1331		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1332	1362	if((offset & 2) == 0)
1333		state->m_knj_addr[1] = ((offset & 1) == 0) ? ((state->m_knj_addr[1]&0xff00)|(data&0xff)) : ((state->m_knj_addr[1]&0x00ff)|(data<<8));
	1363	m_knj_addr[1] = ((offset & 1) == 0) ? ((m_knj_addr[1]&0xff00)|(data&0xff)) : ((m_knj_addr[1]&0x00ff)|(data<<8));
1334	1364	}
1335	1365
1336		static WRITE8_HANDLER( pc8801_dic_bank_w )
	1366	WRITE8_MEMBER(pc8801_state::pc8801_dic_bank_w)
1337	1367	{
1338		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1339	1368	printf("JISHO BANK = %02x\n",data);
1340		if(state->m_has_dictionary)
1341		state->m_dic_bank = data  & 0x1f;
	1369	if(m_has_dictionary)
	1370	m_dic_bank = data  & 0x1f;
1342	1371	}
1343	1372
1344		static WRITE8_HANDLER( pc8801_dic_ctrl_w )
	1373	WRITE8_MEMBER(pc8801_state::pc8801_dic_ctrl_w)
1345	1374	{
1346		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1347	1375	printf("JISHO CTRL = %02x\n",data);
1348		if(state->m_has_dictionary)
1349		state->m_dic_ctrl = (data ^ 1) & 1;
	1376	if(m_has_dictionary)
	1377	m_dic_ctrl = (data ^ 1) & 1;
1350	1378	}
1351	1379
1352		static READ8_HANDLER( pc8801_cdrom_r )
	1380	READ8_MEMBER(pc8801_state::pc8801_cdrom_r)
1353	1381	{
1354		//pc8801_state *state = space->machine().driver_data<pc8801_state>();
1355	1382	//printf("CD-ROM read [%02x]\n",offset);
1356	1383
1357		//if(state->m_has_cdrom)
1358		//  return state->m_cdrom_reg[offset];
	1384	//if(m_has_cdrom)
	1385	//  return m_cdrom_reg[offset];
1359	1386
1360	1387	return 0xff;
1361	1388	}
1362	1389
1363		static WRITE8_HANDLER( pc8801_cdrom_w )
	1390	WRITE8_MEMBER(pc8801_state::pc8801_cdrom_w)
1364	1391	{
1365		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1366	1392	/*
1367	1393	[9] ---x ---- CD-ROM BIOS bank
1368	1394	---- ---x CD-ROM E-ROM bank (?)
1369	1395	*/
1370	1396	//printf("CD-ROM write %02x -> [%02x]\n",data,offset);
1371	1397
1372		if(state->m_has_cdrom)
1373		state->m_cdrom_reg[offset] = data;
	1398	if(m_has_cdrom)
	1399	m_cdrom_reg[offset] = data;
1374	1400	}
1375	1401
1376		static READ8_HANDLER( pc8801_cpuclock_r )
	1402	READ8_MEMBER(pc8801_state::pc8801_cpuclock_r)
1377	1403	{
1378		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1379		if(state->m_has_clock_speed)
1380		return 0x10 | state->m_clock_setting;
	1404	if(m_has_clock_speed)
	1405	return 0x10 | m_clock_setting;
1381	1406
1382	1407	return 0xff;
1383	1408	}
1384	1409
1385		static READ8_HANDLER( pc8801_baudrate_r )
	1410	READ8_MEMBER(pc8801_state::pc8801_baudrate_r)
1386	1411	{
1387		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1388		if(state->m_has_clock_speed)
1389		return 0xf0 | state->m_baudrate_val;
	1412	if(m_has_clock_speed)
	1413	return 0xf0 | m_baudrate_val;
1390	1414
1391	1415	return 0xff;
1392	1416	}
1393	1417
1394		static WRITE8_HANDLER( pc8801_baudrate_w )
	1418	WRITE8_MEMBER(pc8801_state::pc8801_baudrate_w)
1395	1419	{
1396		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1397		if(state->m_has_clock_speed)
1398		state->m_baudrate_val = data & 0xf;
	1420	if(m_has_clock_speed)
	1421	m_baudrate_val = data & 0xf;
1399	1422	}
1400	1423
1401		static WRITE8_HANDLER( pc8801_rtc_w )
	1424	WRITE8_MEMBER(pc8801_state::pc8801_rtc_w)
1402	1425	{
1403		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1404	1426
1405		state->m_rtc->c0_w((data & 1) >> 0);
1406		state->m_rtc->c1_w((data & 2) >> 1);
1407		state->m_rtc->c2_w((data & 4) >> 2);
1408		state->m_rtc->data_in_w((data & 8) >> 3);
	1427	m_rtc->c0_w((data & 1) >> 0);
	1428	m_rtc->c1_w((data & 2) >> 1);
	1429	m_rtc->c2_w((data & 4) >> 2);
	1430	m_rtc->data_in_w((data & 8) >> 3);
1409	1431
1410	1432	/* TODO: remaining bits */
1411	1433	}
r14844	r14845
1429	1451	AM_RANGE(0x0d, 0x0d) AM_READ_PORT("KEY13")
1430	1452	AM_RANGE(0x0e, 0x0e) AM_READ_PORT("KEY14")
1431	1453	AM_RANGE(0x0f, 0x0f) AM_READ_PORT("KEY15")
1432		AM_RANGE(0x00, 0x02) AM_WRITE_LEGACY(pc8801_pcg8100_w)
1433		AM_RANGE(0x10, 0x10) AM_WRITE_LEGACY(pc8801_rtc_w)
1434		AM_RANGE(0x21, 0x21) AM_READ_LEGACY(sio_status_r)                                /* RS-232C and cassette */
1435		AM_RANGE(0x30, 0x30) AM_READ_PORT("DSW1") AM_WRITE_LEGACY(pc8801_txt_cmt_ctrl_w)
1436		AM_RANGE(0x31, 0x31) AM_READ_PORT("DSW2") AM_WRITE_LEGACY(pc8801_gfx_ctrl_w)
1437		AM_RANGE(0x32, 0x32) AM_READWRITE_LEGACY(pc8801_misc_ctrl_r, pc8801_misc_ctrl_w)
	1454	AM_RANGE(0x00, 0x02) AM_WRITE(pc8801_pcg8100_w)
	1455	AM_RANGE(0x10, 0x10) AM_WRITE(pc8801_rtc_w)
	1456	AM_RANGE(0x21, 0x21) AM_READ(sio_status_r)                                /* RS-232C and cassette */
	1457	AM_RANGE(0x30, 0x30) AM_READ_PORT("DSW1") AM_WRITE(pc8801_txt_cmt_ctrl_w)
	1458	AM_RANGE(0x31, 0x31) AM_READ_PORT("DSW2") AM_WRITE(pc8801_gfx_ctrl_w)
	1459	AM_RANGE(0x32, 0x32) AM_READWRITE(pc8801_misc_ctrl_r, pc8801_misc_ctrl_w)
1438	1460	//0x33, 0x33 sets something kanji related
1439		AM_RANGE(0x34, 0x34) AM_WRITE_LEGACY(pc8801_alu_ctrl1_w)
1440		AM_RANGE(0x35, 0x35) AM_WRITE_LEGACY(pc8801_alu_ctrl2_w)
1441		AM_RANGE(0x40, 0x40) AM_READWRITE_LEGACY(pc8801_ctrl_r, pc8801_ctrl_w)
	1461	AM_RANGE(0x34, 0x34) AM_WRITE(pc8801_alu_ctrl1_w)
	1462	AM_RANGE(0x35, 0x35) AM_WRITE(pc8801_alu_ctrl2_w)
	1463	AM_RANGE(0x40, 0x40) AM_READWRITE(pc8801_ctrl_r, pc8801_ctrl_w)
1442	1464	AM_RANGE(0x44, 0x45) AM_DEVREADWRITE_LEGACY("opn", ym2203_r,ym2203_w)
1443	1465	//  AM_RANGE(0x46, 0x47) AM_NOP                                     /* OPNA extra port */
1444		AM_RANGE(0x50, 0x50) AM_READWRITE_LEGACY(pc8801_crtc_param_r, pc88_crtc_param_w)
1445		AM_RANGE(0x51, 0x51) AM_READWRITE_LEGACY(pc8801_crtc_status_r, pc88_crtc_cmd_w)
1446		AM_RANGE(0x52, 0x52) AM_WRITE_LEGACY(pc8801_bgpal_w)
1447		AM_RANGE(0x53, 0x53) AM_WRITE_LEGACY(pc8801_layer_masking_w)
1448		AM_RANGE(0x54, 0x5b) AM_WRITE_LEGACY(pc8801_palram_w)
1449		AM_RANGE(0x5c, 0x5c) AM_READ_LEGACY(pc8801_vram_select_r)
1450		AM_RANGE(0x5c, 0x5f) AM_WRITE_LEGACY(pc8801_vram_select_w)
1451		AM_RANGE(0x60, 0x67) AM_WRITE_LEGACY(pc8801_dmac_w)
1452		AM_RANGE(0x68, 0x68) AM_WRITE_LEGACY(pc8801_dmac_mode_w)
1453		AM_RANGE(0x6e, 0x6e) AM_READ_LEGACY(pc8801_cpuclock_r)
1454		AM_RANGE(0x6f, 0x6f) AM_READWRITE_LEGACY(pc8801_baudrate_r,pc8801_baudrate_w)
1455		AM_RANGE(0x70, 0x70) AM_READWRITE_LEGACY(pc8801_window_bank_r, pc8801_window_bank_w)
1456		AM_RANGE(0x71, 0x71) AM_READWRITE_LEGACY(pc8801_ext_rom_bank_r, pc8801_ext_rom_bank_w)
1457		AM_RANGE(0x78, 0x78) AM_WRITE_LEGACY(pc8801_window_bank_inc_w)
1458		AM_RANGE(0x90, 0x9f) AM_READWRITE_LEGACY(pc8801_cdrom_r,pc8801_cdrom_w)
	1466	AM_RANGE(0x50, 0x50) AM_READWRITE(pc8801_crtc_param_r, pc88_crtc_param_w)
	1467	AM_RANGE(0x51, 0x51) AM_READWRITE(pc8801_crtc_status_r, pc88_crtc_cmd_w)
	1468	AM_RANGE(0x52, 0x52) AM_WRITE(pc8801_bgpal_w)
	1469	AM_RANGE(0x53, 0x53) AM_WRITE(pc8801_layer_masking_w)
	1470	AM_RANGE(0x54, 0x5b) AM_WRITE(pc8801_palram_w)
	1471	AM_RANGE(0x5c, 0x5c) AM_READ(pc8801_vram_select_r)
	1472	AM_RANGE(0x5c, 0x5f) AM_WRITE(pc8801_vram_select_w)
	1473	AM_RANGE(0x60, 0x67) AM_WRITE(pc8801_dmac_w)
	1474	AM_RANGE(0x68, 0x68) AM_WRITE(pc8801_dmac_mode_w)
	1475	AM_RANGE(0x6e, 0x6e) AM_READ(pc8801_cpuclock_r)
	1476	AM_RANGE(0x6f, 0x6f) AM_READWRITE(pc8801_baudrate_r,pc8801_baudrate_w)
	1477	AM_RANGE(0x70, 0x70) AM_READWRITE(pc8801_window_bank_r, pc8801_window_bank_w)
	1478	AM_RANGE(0x71, 0x71) AM_READWRITE(pc8801_ext_rom_bank_r, pc8801_ext_rom_bank_w)
	1479	AM_RANGE(0x78, 0x78) AM_WRITE(pc8801_window_bank_inc_w)
	1480	AM_RANGE(0x90, 0x9f) AM_READWRITE(pc8801_cdrom_r,pc8801_cdrom_w)
1459	1481	//  AM_RANGE(0xa0, 0xa3) AM_NOP                                     /* music & network */
1460	1482	//  AM_RANGE(0xa8, 0xad) AM_NOP                                     /* second sound board */
1461	1483	//  AM_RANGE(0xb4, 0xb5) AM_NOP                                     /* Video art board */
r14844	r14845
1464	1486	//  AM_RANGE(0xd0, 0xd7) AM_NOP                                     /* music & GP-IB */
1465	1487	//  AM_RANGE(0xd8, 0xd8) AM_NOP                                     /* GP-IB */
1466	1488	//  AM_RANGE(0xdc, 0xdf) AM_NOP                                     /* MODEM */
1467		AM_RANGE(0xe2, 0xe2) AM_READWRITE_LEGACY(pc8801_extram_mode_r,pc8801_extram_mode_w)         /* expand RAM mode */
1468		AM_RANGE(0xe3, 0xe3) AM_READWRITE_LEGACY(pc8801_extram_bank_r,pc8801_extram_bank_w)         /* expand RAM bank */
	1489	AM_RANGE(0xe2, 0xe2) AM_READWRITE(pc8801_extram_mode_r,pc8801_extram_mode_w)         /* expand RAM mode */
	1490	AM_RANGE(0xe3, 0xe3) AM_READWRITE(pc8801_extram_bank_r,pc8801_extram_bank_w)         /* expand RAM bank */
1469	1491	#ifdef USE_PROPER_I8214
1470		AM_RANGE(0xe4, 0xe4) AM_WRITE_LEGACY(i8214_irq_level_w)
1471		AM_RANGE(0xe6, 0xe6) AM_WRITE_LEGACY(i8214_irq_mask_w)
	1492	AM_RANGE(0xe4, 0xe4) AM_WRITE(i8214_irq_level_w)
	1493	AM_RANGE(0xe6, 0xe6) AM_WRITE(i8214_irq_mask_w)
1472	1494	#else
1473		AM_RANGE(0xe4, 0xe4) AM_WRITE_LEGACY(pc8801_irq_level_w)
1474		AM_RANGE(0xe6, 0xe6) AM_WRITE_LEGACY(pc8801_irq_mask_w)
	1495	AM_RANGE(0xe4, 0xe4) AM_WRITE(pc8801_irq_level_w)
	1496	AM_RANGE(0xe6, 0xe6) AM_WRITE(pc8801_irq_mask_w)
1475	1497	#endif
1476	1498	//  AM_RANGE(0xe7, 0xe7) AM_NOP                                     /* Arcus writes here, almost likely to be a mirror of above */
1477		AM_RANGE(0xe8, 0xeb) AM_READWRITE_LEGACY(pc8801_kanji_r, pc8801_kanji_w)
1478		AM_RANGE(0xec, 0xef) AM_READWRITE_LEGACY(pc8801_kanji_lv2_r, pc8801_kanji_lv2_w)
1479		AM_RANGE(0xf0, 0xf0) AM_WRITE_LEGACY(pc8801_dic_bank_w)
1480		AM_RANGE(0xf1, 0xf1) AM_WRITE_LEGACY(pc8801_dic_ctrl_w)
	1499	AM_RANGE(0xe8, 0xeb) AM_READWRITE(pc8801_kanji_r, pc8801_kanji_w)
	1500	AM_RANGE(0xec, 0xef) AM_READWRITE(pc8801_kanji_lv2_r, pc8801_kanji_lv2_w)
	1501	AM_RANGE(0xf0, 0xf0) AM_WRITE(pc8801_dic_bank_w)
	1502	AM_RANGE(0xf1, 0xf1) AM_WRITE(pc8801_dic_ctrl_w)
1481	1503	//  AM_RANGE(0xf3, 0xf3) AM_NOP                                     /* DMA floppy (unknown) */
1482	1504	//  AM_RANGE(0xf4, 0xf7) AM_NOP                                     /* DMA 5'floppy (may be not released) */
1483	1505	//  AM_RANGE(0xf8, 0xfb) AM_NOP                                     /* DMA 8'floppy (unknown) */
r14844	r14845
1548	1570	upd765_tc_w(machine.device("upd765"), 0);
1549	1571	}
1550	1572
1551		static WRITE8_HANDLER( upd765_mc_w )
	1573	WRITE8_MEMBER(pc8801_state::upd765_mc_w)
1552	1574	{
1553		floppy_mon_w(floppy_get_device(space->machine(), 0), (data & 1) ? CLEAR_LINE : ASSERT_LINE);
1554		floppy_mon_w(floppy_get_device(space->machine(), 1), (data & 2) ? CLEAR_LINE : ASSERT_LINE);
1555		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 0), (data & 1), 0);
1556		floppy_drive_set_ready_state(floppy_get_device(space->machine(), 1), (data & 2), 0);
	1575	floppy_mon_w(floppy_get_device(machine(), 0), (data & 1) ? CLEAR_LINE : ASSERT_LINE);
	1576	floppy_mon_w(floppy_get_device(machine(), 1), (data & 2) ? CLEAR_LINE : ASSERT_LINE);
	1577	floppy_drive_set_ready_state(floppy_get_device(machine(), 0), (data & 1), 0);
	1578	floppy_drive_set_ready_state(floppy_get_device(machine(), 1), (data & 2), 0);
1557	1579	}
1558	1580
1559		static READ8_HANDLER( upd765_tc_r )
	1581	READ8_MEMBER(pc8801_state::upd765_tc_r)
1560	1582	{
1561		//pc88va_state *state = space->machine().driver_data<pc88va_state>();
1562	1583
1563		upd765_tc_w(space->machine().device("upd765"), 1);
	1584	upd765_tc_w(machine().device("upd765"), 1);
1564	1585	//TODO: I'm not convinced that this works correctly with current hook-up ... 1000 usec is needed by Aploon, a bigger value breaks Alpha.
1565		space->machine().scheduler().timer_set(attotime::from_usec(750), FUNC(pc8801fd_upd765_tc_to_zero));
	1586	machine().scheduler().timer_set(attotime::from_usec(750), FUNC(pc8801fd_upd765_tc_to_zero));
1566	1587	return 0xff; // value is meaningless
1567	1588	}
1568	1589
1569		static WRITE8_HANDLER( fdc_irq_vector_w )
	1590	WRITE8_MEMBER(pc8801_state::fdc_irq_vector_w)
1570	1591	{
1571		pc8801_state *state = space->machine().driver_data<pc8801_state>();
1572		state->m_fdc_irq_opcode = data;
	1592	m_fdc_irq_opcode = data;
1573	1593	}
1574	1594
1575		static WRITE8_HANDLER( fdc_drive_mode_w )
	1595	WRITE8_MEMBER(pc8801_state::fdc_drive_mode_w)
1576	1596	{
1577	1597	if(data & 5)
1578	1598	printf("drive 0 sets up %s floppy format\n",data & 1 ? "2hd" : "2dd");
r14844	r14845
1582	1602
1583	1603	static ADDRESS_MAP_START( pc8801fdc_io, AS_IO, 8, pc8801_state )
1584	1604	ADDRESS_MAP_GLOBAL_MASK(0xff)
1585		AM_RANGE(0xf0, 0xf0) AM_WRITE_LEGACY(fdc_irq_vector_w) // Interrupt Opcode Port
1586		AM_RANGE(0xf4, 0xf4) AM_WRITE_LEGACY(fdc_drive_mode_w) // Drive mode, 2d, 2dd, 2hd
	1605	AM_RANGE(0xf0, 0xf0) AM_WRITE(fdc_irq_vector_w) // Interrupt Opcode Port
	1606	AM_RANGE(0xf4, 0xf4) AM_WRITE(fdc_drive_mode_w) // Drive mode, 2d, 2dd, 2hd
1587	1607	//  AM_RANGE(0xf7, 0xf7) AM_WRITENOP // printer port output
1588		AM_RANGE(0xf8, 0xf8) AM_READWRITE_LEGACY(upd765_tc_r,upd765_mc_w) // (R) Terminal Count Port (W) Motor Control Port
	1608	AM_RANGE(0xf8, 0xf8) AM_READWRITE(upd765_tc_r,upd765_mc_w) // (R) Terminal Count Port (W) Motor Control Port
1589	1609	AM_RANGE(0xfa, 0xfa) AM_DEVREAD_LEGACY("upd765", upd765_status_r )
1590	1610	AM_RANGE(0xfb, 0xfb) AM_DEVREADWRITE_LEGACY("upd765", upd765_data_r, upd765_data_w )
1591	1611	AM_RANGE(0xfc, 0xff) AM_DEVREADWRITE("d8255_slave", i8255_device, read, write)

src/mess/drivers/socrates.c

r14844	r14845
101	101	UINT8 m_speech_dummy_read; // have we done a dummy read yet?
102	102	UINT8 m_speech_load_address_count; // number of times load address has happened
103	103	UINT8 m_speech_load_settings_count; // number of times load settings has happened
	104	DECLARE_READ8_MEMBER(socrates_rom_bank_r);
	105	DECLARE_WRITE8_MEMBER(socrates_rom_bank_w);
	106	DECLARE_READ8_MEMBER(socrates_ram_bank_r);
	107	DECLARE_WRITE8_MEMBER(socrates_ram_bank_w);
	108	DECLARE_READ8_MEMBER(read_f3);
	109	DECLARE_WRITE8_MEMBER(unknownlatch_30);
	110	DECLARE_READ8_MEMBER(status_and_speech);
	111	DECLARE_WRITE8_MEMBER(speech_command);
	112	DECLARE_READ8_MEMBER(socrates_keyboard_low_r);
	113	DECLARE_READ8_MEMBER(socrates_keyboard_high_r);
	114	DECLARE_WRITE8_MEMBER(socrates_keyboard_clear);
	115	DECLARE_WRITE8_MEMBER(reset_speech);
	116	DECLARE_WRITE8_MEMBER(socrates_scroll_w);
	117	DECLARE_WRITE8_MEMBER(socrates_sound_w);
104	118	};
105	119
106	120
r14844	r14845
215	229	machine.device("maincpu")->set_clock_scale(0.45f); /* RAM access waitstates etc. aren't emulated - slow the CPU to compensate */
216	230	}
217	231
218		static READ8_HANDLER( socrates_rom_bank_r )
	232	READ8_MEMBER(socrates_state::socrates_rom_bank_r)
219	233	{
220		socrates_state *state = space->machine().driver_data<socrates_state>();
221	234	UINT8 data = 0xFF;
222		data = state->m_rom_bank;
	235	data = m_rom_bank;
223	236	return data;
224	237	}
225	238
226		static WRITE8_HANDLER( socrates_rom_bank_w )
	239	WRITE8_MEMBER(socrates_state::socrates_rom_bank_w)
227	240	{
228		socrates_state *state = space->machine().driver_data<socrates_state>();
229		state->m_rom_bank = data;
230		socrates_set_rom_bank(space->machine());
	241	m_rom_bank = data;
	242	socrates_set_rom_bank(machine());
231	243	}
232	244
233		static READ8_HANDLER( socrates_ram_bank_r )
	245	READ8_MEMBER(socrates_state::socrates_ram_bank_r)
234	246	{
235		socrates_state *state = space->machine().driver_data<socrates_state>();
236	247	UINT8 data = 0xFF;
237		data = state->m_ram_bank;
	248	data = m_ram_bank;
238	249	return data;
239	250	}
240	251
241		static WRITE8_HANDLER( socrates_ram_bank_w )
	252	WRITE8_MEMBER(socrates_state::socrates_ram_bank_w)
242	253	{
243		socrates_state *state = space->machine().driver_data<socrates_state>();
244		state->m_ram_bank = data&0xF;
245		socrates_set_ram_bank(space->machine());
	254	m_ram_bank = data&0xF;
	255	socrates_set_ram_bank(machine());
246	256	}
247	257
248		static READ8_HANDLER( read_f3 ) // used for read-only i/o ports as mame/mess doesn't have a way to set the unmapped area to read as 0xF3
	258	READ8_MEMBER(socrates_state::read_f3)// used for read-only i/o ports as mame/mess doesn't have a way to set the unmapped area to read as 0xF3
249	259	{
250	260	return 0xF3;
251	261	}
252	262
253		static WRITE8_HANDLER( unknownlatch_30 ) // writes to i/o 0x3x do SOMETHING, possibly waitstate related (may halt cpu until vblank start?) or involve status reg bit 6
	263	WRITE8_MEMBER(socrates_state::unknownlatch_30)// writes to i/o 0x3x do SOMETHING, possibly waitstate related (may halt cpu until vblank start?) or involve status reg bit 6
254	264	{
255	265	//logerror("write to i/o 0x30, data %x\n", data); // too annoying to leave enabled
256	266	}
257	267
258		static READ8_HANDLER( status_and_speech ) // read 0x4x, some sort of status reg
	268	READ8_MEMBER(socrates_state::status_and_speech)// read 0x4x, some sort of status reg
259	269	{
260		socrates_state *state = space->machine().driver_data<socrates_state>();
261	270	// bit 7 - speech status: high when speech is playing, low when it is not (or when speech cart is not present)
262	271	// bit 6 - unknown, usually set, may involve the writes to 0x30, possibly some sort of fixed-length timer?
263	272	// bit 5 - vblank status, high when not in vblank
r14844	r14845
266	275	// bit 2 - speech chip bit 2
267	276	// bit 1 - speech chip bit 1
268	277	// bit 0 - speech chip bit 0
269		UINT8 *speechromint = space->machine().region("speechint")->base();
270		UINT8 *speechromext = space->machine().region("speechext")->base();
	278	UINT8 *speechromint = machine().region("speechint")->base();
	279	UINT8 *speechromext = machine().region("speechext")->base();
271	280	int temp = 0;
272		temp |= (state->m_speech_running)?0x80:0;
	281	temp |= (m_speech_running)?0x80:0;
273	282	temp |= 0x40; // unknown
274		temp |= (state->m_vblankstate)?0:0x20;
275		temp |= (state->m_hblankstate)?0:0x10;
276		switch(state->m_io40_latch&0xF0) // what was last opcode sent?
	283	temp |= (m_vblankstate)?0:0x20;
	284	temp |= (m_hblankstate)?0:0x10;
	285	switch(m_io40_latch&0xF0) // what was last opcode sent?
277	286	{
278	287	case 0x60: case 0xE0:// speech status 'read' register
279		if(state->m_speech_settings&0x04) // external speech roms (outside of speech ic but still in cart) enabled
	288	if(m_speech_settings&0x04) // external speech roms (outside of speech ic but still in cart) enabled
280	289	{
281		logerror("reading external speech rom nybble from nybble address %x (byte address %x)\n",state->m_speech_address, state->m_speech_address>>1);
282		temp |= ((speechromext[((state->m_speech_address>>1)&0xffff)]>>((state->m_speech_address&1)*4))&0xF);
	290	logerror("reading external speech rom nybble from nybble address %x (byte address %x)\n",m_speech_address, m_speech_address>>1);
	291	temp |= ((speechromext[((m_speech_address>>1)&0xffff)]>>((m_speech_address&1)*4))&0xF);
283	292	}
284	293	else
285	294	{
286		logerror("reading internal speech rom nybble from nybble address %x (byte address %x)\n",state->m_speech_address, state->m_speech_address>>1);
287		temp |= ((speechromint[((state->m_speech_address>>1)&0x1fff)]>>((state->m_speech_address&1)*4))&0xF);
	295	logerror("reading internal speech rom nybble from nybble address %x (byte address %x)\n",m_speech_address, m_speech_address>>1);
	296	temp |= ((speechromint[((m_speech_address>>1)&0x1fff)]>>((m_speech_address&1)*4))&0xF);
288	297	}
289		if (state->m_speech_dummy_read == 0) // if we havent done the dummy read yet, do so now
	298	if (m_speech_dummy_read == 0) // if we havent done the dummy read yet, do so now
290	299	{
291		state->m_speech_dummy_read++;
	300	m_speech_dummy_read++;
292	301	}
293	302	else
294	303	{
295		state->m_speech_address++;
	304	m_speech_address++;
296	305	}
297	306	break;
298	307	default:
299		temp |= state->m_io40_latch&0xF; // read open bus
	308	temp |= m_io40_latch&0xF; // read open bus
300	309	break;
301	310	}
302	311	logerror("read from i/o 0x4x of %x\n", temp);
r14844	r14845
310	319	state->m_speech_load_settings_count = 0;
311	320	}
312	321
313		static WRITE8_HANDLER( speech_command ) // write 0x4x, some sort of bitfield; speech chip is probably hitachi hd38880 related but not exact, w/4 bit interface
	322	WRITE8_MEMBER(socrates_state::speech_command)// write 0x4x, some sort of bitfield; speech chip is probably hitachi hd38880 related but not exact, w/4 bit interface
314	323	{
315		socrates_state *state = space->machine().driver_data<socrates_state>();
316	324	logerror("write to i/o 0x4x of %x\n", data);
317	325	/*
318	326	// the high 4 bits of the write control which 'register' is written to, the low 4 bits are data (this is based on a readback test)
r14844	r14845
370	378	if (data==0x80)
371	379	{
372	380	/* write me: start talking */
373		state->m_speech_running = 1;
374		space->machine().scheduler().timer_set(attotime::from_seconds(4), FUNC(clear_speech_cb)); // hack
	381	m_speech_running = 1;
	382	machine().scheduler().timer_set(attotime::from_seconds(4), FUNC(clear_speech_cb)); // hack
375	383	}
376	384	break;
377	385	case 0x90: // unknown, one of these is probably read and branch
r14844	r14845
381	389	case 0xB0: // unknown
382	390	break;
383	391	case 0xC0: // load address to vsm
384		state->m_speech_address |= (((int)data&0xF)<<(state->m_speech_load_address_count*4))<<1;
385		state->m_speech_load_address_count++;
386		logerror("loaded address nybble %X, byte address is currently %5X with %d nybbles loaded\n", data&0xF, state->m_speech_address>>1, state->m_speech_load_address_count);
	392	m_speech_address |= (((int)data&0xF)<<(m_speech_load_address_count*4))<<1;
	393	m_speech_load_address_count++;
	394	logerror("loaded address nybble %X, byte address is currently %5X with %d nybbles loaded\n", data&0xF, m_speech_address>>1, m_speech_load_address_count);
387	395	break;
388	396	case 0xD0: // load settings
389		state->m_speech_settings |= ((data&0xF)<<(state->m_speech_load_settings_count*4));
390		state->m_speech_load_settings_count++;
	397	m_speech_settings |= ((data&0xF)<<(m_speech_load_settings_count*4));
	398	m_speech_load_settings_count++;
391	399	break;
392	400	case 0xE0: // read byte, handled elsewhere
393	401	break;
394	402	case 0xF0: // command: sub 0 is speak, sub 8 is reset
395	403	if ((data&0xF) == 0) // speak
396	404	{
397		state->m_speech_running = 1;
398		space->machine().scheduler().timer_set(attotime::from_seconds(4), FUNC(clear_speech_cb)); // hack
	405	m_speech_running = 1;
	406	machine().scheduler().timer_set(attotime::from_seconds(4), FUNC(clear_speech_cb)); // hack
399	407	}
400	408	else if ((data&0xF) == 8) // reset
401	409	{
402		state->m_speech_running = 0;
403		state->m_speech_address = 0;
404		state->m_speech_settings = 0;
405		state->m_speech_dummy_read = 0;
406		state->m_speech_load_address_count = 0;
407		state->m_speech_load_settings_count = 0;
408		state->m_io40_latch &= 0x0f; // set last command to 0 to prevent problems
	410	m_speech_running = 0;
	411	m_speech_address = 0;
	412	m_speech_settings = 0;
	413	m_speech_dummy_read = 0;
	414	m_speech_load_address_count = 0;
	415	m_speech_load_settings_count = 0;
	416	m_io40_latch &= 0x0f; // set last command to 0 to prevent problems
409	417	}
410	418	else // other
411	419	{
r14844	r14845
415	423	default: // 00 through 70 are packets without the write bit set, ignore them
416	424	break;
417	425	}
418		state->m_io40_latch = data;
	426	m_io40_latch = data;
419	427	}
420	428
421		static READ8_HANDLER( socrates_keyboard_low_r ) // keyboard code low
	429	READ8_MEMBER(socrates_state::socrates_keyboard_low_r)// keyboard code low
422	430	{
423		socrates_state *state = space->machine().driver_data<socrates_state>();
424		socrates_update_kb(space->machine());
425		socrates_check_kb_latch(space->machine());
426		return state->m_kb_latch_low[0];
	431	socrates_update_kb(machine());
	432	socrates_check_kb_latch(machine());
	433	return m_kb_latch_low[0];
427	434	}
428	435
429		static READ8_HANDLER( socrates_keyboard_high_r ) // keyboard code high
	436	READ8_MEMBER(socrates_state::socrates_keyboard_high_r)// keyboard code high
430	437	{
431		socrates_state *state = space->machine().driver_data<socrates_state>();
432		socrates_update_kb(space->machine());
433		socrates_check_kb_latch(space->machine());
434		return state->m_kb_latch_high[0];
	438	socrates_update_kb(machine());
	439	socrates_check_kb_latch(machine());
	440	return m_kb_latch_high[0];
435	441	}
436	442
437		static WRITE8_HANDLER( socrates_keyboard_clear ) // keyboard latch shift/clear
	443	WRITE8_MEMBER(socrates_state::socrates_keyboard_clear)// keyboard latch shift/clear
438	444	{
439		socrates_state *state = space->machine().driver_data<socrates_state>();
440		state->m_kb_latch_low[0] = state->m_kb_latch_low[1];
441		state->m_kb_latch_high[0] = state->m_kb_latch_high[1];
442		state->m_kb_latch_low[1] = 0;
443		state->m_kb_latch_high[1] = 1;
	445	m_kb_latch_low[0] = m_kb_latch_low[1];
	446	m_kb_latch_high[0] = m_kb_latch_high[1];
	447	m_kb_latch_low[1] = 0;
	448	m_kb_latch_high[1] = 1;
444	449	}
445	450
446		static WRITE8_HANDLER( reset_speech ) // i/o 60: reset speech synth
	451	WRITE8_MEMBER(socrates_state::reset_speech)// i/o 60: reset speech synth
447	452	{
448		socrates_state *state = space->machine().driver_data<socrates_state>();
449		state->m_speech_running = 0;
450		state->m_speech_address = 0;
451		state->m_speech_settings = 0;
452		state->m_speech_dummy_read = 0;
453		state->m_speech_load_address_count = 0;
454		state->m_speech_load_settings_count = 0;
455		state->m_io40_latch &= 0x0f; // set last command to 0 to prevent problems
	453	m_speech_running = 0;
	454	m_speech_address = 0;
	455	m_speech_settings = 0;
	456	m_speech_dummy_read = 0;
	457	m_speech_load_address_count = 0;
	458	m_speech_load_settings_count = 0;
	459	m_io40_latch &= 0x0f; // set last command to 0 to prevent problems
456	460	logerror("write to i/o 0x60 of %x\n",data);
457	461	}
458	462
459	463	/* stuff below belongs in video/nc.c */
460	464
461		static WRITE8_HANDLER( socrates_scroll_w )
	465	WRITE8_MEMBER(socrates_state::socrates_scroll_w)
462	466	{
463		socrates_state *state = space->machine().driver_data<socrates_state>();
464	467	if (offset == 0)
465		state->m_scroll_offset = (state->m_scroll_offset&0x100) | data;
	468	m_scroll_offset = (m_scroll_offset&0x100) | data;
466	469	else
467		state->m_scroll_offset = (state->m_scroll_offset&0xFF) | ((data&1)<<8);
	470	m_scroll_offset = (m_scroll_offset&0xFF) | ((data&1)<<8);
468	471	}
469	472
470	473	/* NTSC-based Palette stuff */
r14844	r14845
628	631
629	632	/* below belongs in sound/nc.c */
630	633
631		static WRITE8_HANDLER(socrates_sound_w)
	634	WRITE8_MEMBER(socrates_state::socrates_sound_w)
632	635	{
633		device_t *socr_snd = space->machine().device("soc_snd");
	636	device_t *socr_snd = machine().device("soc_snd");
634	637	switch(offset)
635	638	{
636	639	case 0:
r14844	r14845
666	669	static ADDRESS_MAP_START(z80_io, AS_IO, 8, socrates_state )
667	670	ADDRESS_MAP_UNMAP_HIGH
668	671	ADDRESS_MAP_GLOBAL_MASK(0xff)
669		AM_RANGE(0x00, 0x00) AM_READWRITE_LEGACY(socrates_rom_bank_r, socrates_rom_bank_w) AM_MIRROR(0x7) /* rom bank select - RW - 8 bits */
670		AM_RANGE(0x08, 0x08) AM_READWRITE_LEGACY(socrates_ram_bank_r, socrates_ram_bank_w) AM_MIRROR(0x7) /* ram banks select - RW - 4 low bits; Format: 0b****HHLL where LL controls whether window 0 points at ram area: 0b00: 0x0000-0x3fff; 0b01: 0x4000-0x7fff; 0b10: 0x8000-0xbfff; 0b11: 0xc000-0xffff. HH controls the same thing for window 1 */
671		AM_RANGE(0x10, 0x17) AM_READWRITE_LEGACY(read_f3, socrates_sound_w) AM_MIRROR (0x8) /* sound section:
	672	AM_RANGE(0x00, 0x00) AM_READWRITE(socrates_rom_bank_r, socrates_rom_bank_w) AM_MIRROR(0x7) /* rom bank select - RW - 8 bits */
	673	AM_RANGE(0x08, 0x08) AM_READWRITE(socrates_ram_bank_r, socrates_ram_bank_w) AM_MIRROR(0x7) /* ram banks select - RW - 4 low bits; Format: 0b****HHLL where LL controls whether window 0 points at ram area: 0b00: 0x0000-0x3fff; 0b01: 0x4000-0x7fff; 0b10: 0x8000-0xbfff; 0b11: 0xc000-0xffff. HH controls the same thing for window 1 */
	674	AM_RANGE(0x10, 0x17) AM_READWRITE(read_f3, socrates_sound_w) AM_MIRROR (0x8) /* sound section:
672	675	0x10 - W - frequency control for channel 1 (louder channel) - 01=high pitch, ff=low; time between 1->0/0->1 transitions = (XTAL_21_4772MHz/(512+256) / (freq_reg+1)) (note that this is double the actual frequency since each full low and high squarewave pulse is two transitions)
673	676	0x11 - W - frequency control for channel 2 (softer channel) - 01=high pitch, ff=low; same equation as above
674	677	0x12 - W - 0b***EVVVV enable, volume control for channel 1
r14844	r14845
680	683	0xC0 produces a DMC wave read from an unknown address at around 342hz
681	684	0x
682	685	*/
683		AM_RANGE(0x20, 0x21) AM_READWRITE_LEGACY(read_f3, socrates_scroll_w) AM_MIRROR (0xe) /* graphics section:
	686	AM_RANGE(0x20, 0x21) AM_READWRITE(read_f3, socrates_scroll_w) AM_MIRROR (0xe) /* graphics section:
684	687	0x20 - W - lsb offset of screen display
685	688	0x21 - W - msb offset of screen display
686	689	resulting screen line is one of 512 total offsets on 128-byte boundaries in the whole 64k ram
687	690	*/
688		AM_RANGE(0x30, 0x30) AM_READWRITE_LEGACY(read_f3, unknownlatch_30) AM_MIRROR (0xf) /* unknown, write only. may relate to waitstate timing? */
689		AM_RANGE(0x40, 0x40) AM_READWRITE_LEGACY(status_and_speech, speech_command ) AM_MIRROR(0xf) /* reads status register for vblank/hblank/speech, also reads and writes speech module */
690		AM_RANGE(0x50, 0x50) AM_READWRITE_LEGACY(socrates_keyboard_low_r, socrates_keyboard_clear) AM_MIRROR(0xE) /* Keyboard keycode low, latched on keypress, can be unlatched by writing anything here */
691		AM_RANGE(0x51, 0x51) AM_READWRITE_LEGACY(socrates_keyboard_high_r, socrates_keyboard_clear) AM_MIRROR(0xE) /* Keyboard keycode high, latched as above, unlatches same as above */
692		AM_RANGE(0x60, 0x60) AM_READWRITE_LEGACY(read_f3, reset_speech) AM_MIRROR(0xF) /* reset the speech module, or perhaps fire an NMI?  */
693		AM_RANGE(0x70, 0xFF) AM_READ_LEGACY(read_f3) // nothing mapped here afaik
	691	AM_RANGE(0x30, 0x30) AM_READWRITE(read_f3, unknownlatch_30) AM_MIRROR (0xf) /* unknown, write only. may relate to waitstate timing? */
	692	AM_RANGE(0x40, 0x40) AM_READWRITE(status_and_speech, speech_command ) AM_MIRROR(0xf) /* reads status register for vblank/hblank/speech, also reads and writes speech module */
	693	AM_RANGE(0x50, 0x50) AM_READWRITE(socrates_keyboard_low_r, socrates_keyboard_clear) AM_MIRROR(0xE) /* Keyboard keycode low, latched on keypress, can be unlatched by writing anything here */
	694	AM_RANGE(0x51, 0x51) AM_READWRITE(socrates_keyboard_high_r, socrates_keyboard_clear) AM_MIRROR(0xE) /* Keyboard keycode high, latched as above, unlatches same as above */
	695	AM_RANGE(0x60, 0x60) AM_READWRITE(read_f3, reset_speech) AM_MIRROR(0xF) /* reset the speech module, or perhaps fire an NMI?  */
	696	AM_RANGE(0x70, 0xFF) AM_READ(read_f3) // nothing mapped here afaik
694	697	ADDRESS_MAP_END
695	698
696	699

src/mess/drivers/jr200.c

r14844	r14845
33	33	UINT8 m_old_keydata;
34	34	UINT8 m_freq_reg[2];
35	35	emu_timer *m_timer_d;
	36	DECLARE_READ8_MEMBER(jr200_pcg_1_r);
	37	DECLARE_READ8_MEMBER(jr200_pcg_2_r);
	38	DECLARE_WRITE8_MEMBER(jr200_pcg_1_w);
	39	DECLARE_WRITE8_MEMBER(jr200_pcg_2_w);
	40	DECLARE_READ8_MEMBER(jr200_bios_char_r);
	41	DECLARE_WRITE8_MEMBER(jr200_bios_char_w);
	42	DECLARE_READ8_MEMBER(mcu_keyb_r);
	43	DECLARE_WRITE8_MEMBER(jr200_beep_w);
	44	DECLARE_WRITE8_MEMBER(jr200_beep_freq_w);
	45	DECLARE_WRITE8_MEMBER(jr200_border_col_w);
	46	DECLARE_READ8_MEMBER(mn1271_io_r);
	47	DECLARE_WRITE8_MEMBER(mn1271_io_w);
36	48	};
37	49
38	50
r14844	r14845
153	165	return 0;
154	166	}
155	167
156		static READ8_HANDLER( jr200_pcg_1_r )
	168	READ8_MEMBER(jr200_state::jr200_pcg_1_r)
157	169	{
158		UINT8 *pcg = space->machine().region("pcg")->base();
	170	UINT8 *pcg = machine().region("pcg")->base();
159	171
160	172	return pcg[offset+0x000];
161	173	}
162	174
163		static READ8_HANDLER( jr200_pcg_2_r )
	175	READ8_MEMBER(jr200_state::jr200_pcg_2_r)
164	176	{
165		UINT8 *pcg = space->machine().region("pcg")->base();
	177	UINT8 *pcg = machine().region("pcg")->base();
166	178
167	179	return pcg[offset+0x400];
168	180	}
169	181
170		static WRITE8_HANDLER( jr200_pcg_1_w )
	182	WRITE8_MEMBER(jr200_state::jr200_pcg_1_w)
171	183	{
172		UINT8 *pcg = space->machine().region("pcg")->base();
	184	UINT8 *pcg = machine().region("pcg")->base();
173	185
174	186	pcg[offset+0x000] = data;
175		gfx_element_mark_dirty(space->machine().gfx[1], (offset+0x000) >> 3);
	187	gfx_element_mark_dirty(machine().gfx[1], (offset+0x000) >> 3);
176	188	}
177	189
178		static WRITE8_HANDLER( jr200_pcg_2_w )
	190	WRITE8_MEMBER(jr200_state::jr200_pcg_2_w)
179	191	{
180		UINT8 *pcg = space->machine().region("pcg")->base();
	192	UINT8 *pcg = machine().region("pcg")->base();
181	193
182	194	pcg[offset+0x400] = data;
183		gfx_element_mark_dirty(space->machine().gfx[1], (offset+0x400) >> 3);
	195	gfx_element_mark_dirty(machine().gfx[1], (offset+0x400) >> 3);
184	196	}
185	197
186		static READ8_HANDLER( jr200_bios_char_r )
	198	READ8_MEMBER(jr200_state::jr200_bios_char_r)
187	199	{
188		UINT8 *gfx = space->machine().region("gfx_ram")->base();
	200	UINT8 *gfx = machine().region("gfx_ram")->base();
189	201
190	202	return gfx[offset];
191	203	}
192	204
193	205
194		static WRITE8_HANDLER( jr200_bios_char_w )
	206	WRITE8_MEMBER(jr200_state::jr200_bios_char_w)
195	207	{
196		//  UINT8 *gfx = space->machine().region("gfx_ram")->base();
	208	//  UINT8 *gfx = machine().region("gfx_ram")->base();
197	209
198	210	/* TODO: writing is presumably controlled by an I/O bit */
199	211	//  gfx[offset] = data;
200		//  gfx_element_mark_dirty(space->machine().gfx[0], offset >> 3);
	212	//  gfx_element_mark_dirty(machine().gfx[0], offset >> 3);
201	213	}
202	214
203	215	/*
r14844	r14845
206	218
207	219	*/
208	220
209		static READ8_HANDLER( mcu_keyb_r )
	221	READ8_MEMBER(jr200_state::mcu_keyb_r)
210	222	{
211		jr200_state *state = space->machine().driver_data<jr200_state>();
212	223	int row, col, table = 0;
213	224	UINT8 keydata = 0;
214	225	static const char *const keynames[] = { "ROW0", "ROW1", "ROW2", "ROW3", "ROW4", "ROW5", "ROW6", "ROW7", "ROW8" };
215	226
216		if (input_port_read(space->machine(), "ROW9") & 0x07)
	227	if (input_port_read(machine(), "ROW9") & 0x07)
217	228	{
218	229	/* shift, upper case */
219	230	table = 1;
r14844	r14845
222	233	/* scan keyboard */
223	234	for (row = 0; row < 9; row++)
224	235	{
225		UINT8 data = input_port_read(space->machine(), keynames[row]);
	236	UINT8 data = input_port_read(machine(), keynames[row]);
226	237
227	238	for (col = 0; col < 8; col++)
228	239	{
r14844	r14845
234	245	}
235	246	}
236	247
237		if(state->m_old_keydata == keydata)
	248	if(m_old_keydata == keydata)
238	249	return 0x00;
239	250
240		state->m_old_keydata = keydata;
	251	m_old_keydata = keydata;
241	252
242	253	return keydata;
243	254	}
244	255
245		static WRITE8_HANDLER( jr200_beep_w )
	256	WRITE8_MEMBER(jr200_state::jr200_beep_w)
246	257	{
247	258	/* writing 0x0e enables the beeper, writing anything else disables it */
248		beep_set_state(space->machine().device(BEEPER_TAG),((data & 0xf) == 0x0e) ? 1 : 0);
	259	beep_set_state(machine().device(BEEPER_TAG),((data & 0xf) == 0x0e) ? 1 : 0);
249	260	}
250	261
251		static WRITE8_HANDLER( jr200_beep_freq_w )
	262	WRITE8_MEMBER(jr200_state::jr200_beep_freq_w)
252	263	{
253		jr200_state *state = space->machine().driver_data<jr200_state>();
254	264	UINT32 beep_freq;
255	265
256		state->m_freq_reg[offset] = data;
	266	m_freq_reg[offset] = data;
257	267
258		beep_freq = ((state->m_freq_reg[0]<<8) | (state->m_freq_reg[1] & 0xff)) + 1;
	268	beep_freq = ((m_freq_reg[0]<<8) | (m_freq_reg[1] & 0xff)) + 1;
259	269
260		beep_set_frequency(space->machine().device(BEEPER_TAG),84000 / beep_freq);
	270	beep_set_frequency(machine().device(BEEPER_TAG),84000 / beep_freq);
261	271	}
262	272
263		static WRITE8_HANDLER( jr200_border_col_w )
	273	WRITE8_MEMBER(jr200_state::jr200_border_col_w)
264	274	{
265		jr200_state *state = space->machine().driver_data<jr200_state>();
266		state->m_border_col = data;
	275	m_border_col = data;
267	276	}
268	277
269	278
r14844	r14845
272	281	device_set_input_line(machine.firstcpu, 0, HOLD_LINE);
273	282	}
274	283
275		static READ8_HANDLER( mn1271_io_r )
	284	READ8_MEMBER(jr200_state::mn1271_io_r)
276	285	{
277		jr200_state *state = space->machine().driver_data<jr200_state>();
278		UINT8 retVal = state->m_mn1271_ram[offset];
	286	UINT8 retVal = m_mn1271_ram[offset];
279	287	if((offset+0xc800) > 0xca00)
280	288	retVal= 0xff;
281	289
282	290	switch(offset+0xc800)
283	291	{
284	292	case 0xc801: retVal= mcu_keyb_r(space,0); break;
285		case 0xc803: retVal= (state->m_mn1271_ram[0x03] & 0xcf) | 0x30;  break;//---x ---- printer status ready (ACTIVE HIGH)
286		case 0xc807: retVal= (state->m_mn1271_ram[0x07] & 0x80) | 0x60; break;
287		case 0xc80a: retVal= (state->m_mn1271_ram[0x0a] & 0xfe); break;
288		case 0xc80c: retVal= (state->m_mn1271_ram[0x0c] & 0xdf) | 0x20; break;
	293	case 0xc803: retVal= (m_mn1271_ram[0x03] & 0xcf) | 0x30;  break;//---x ---- printer status ready (ACTIVE HIGH)
	294	case 0xc807: retVal= (m_mn1271_ram[0x07] & 0x80) | 0x60; break;
	295	case 0xc80a: retVal= (m_mn1271_ram[0x0a] & 0xfe); break;
	296	case 0xc80c: retVal= (m_mn1271_ram[0x0c] & 0xdf) | 0x20; break;
289	297	case 0xc80e: retVal= 0; break;
290	298	case 0xc810: retVal= 0; break;
291	299	case 0xc816: retVal= 0x4e; break;
292		case 0xc81c: retVal= (state->m_mn1271_ram[0x1c] & 0xfe) | 1;  break;//bit 0 needs to be high otherwise system refuses to boot
293		case 0xc81d: retVal= (state->m_mn1271_ram[0x1d] & 0xed); break;
	300	case 0xc81c: retVal= (m_mn1271_ram[0x1c] & 0xfe) | 1;  break;//bit 0 needs to be high otherwise system refuses to boot
	301	case 0xc81d: retVal= (m_mn1271_ram[0x1d] & 0xed); break;
294	302	}
295	303	//logerror("mn1271_io_r [%04x] = %02x\n",offset+0xc800,retVal);
296	304	return retVal;
297	305	}
298	306
299		static WRITE8_HANDLER( mn1271_io_w )
	307	WRITE8_MEMBER(jr200_state::mn1271_io_w)
300	308	{
301		jr200_state *state = space->machine().driver_data<jr200_state>();
302		state->m_mn1271_ram[offset] = data;
	309	m_mn1271_ram[offset] = data;
303	310	switch(offset+0xc800)
304	311	{
305	312	case 0xc805: break; //LPT printer port W
306	313	case 0xc816: if (data!=0) {
307		state->m_timer_d->adjust(attotime::zero, 0, attotime::from_hz(XTAL_14_31818MHz) * (state->m_mn1271_ram[0x17]*0x100 + state->m_mn1271_ram[0x18]));
	314	m_timer_d->adjust(attotime::zero, 0, attotime::from_hz(XTAL_14_31818MHz) * (m_mn1271_ram[0x17]*0x100 + m_mn1271_ram[0x18]));
308	315	} else {
309		state->m_timer_d->adjust(attotime::zero, 0,  attotime::zero);
	316	m_timer_d->adjust(attotime::zero, 0,  attotime::zero);
310	317	}
311	318	break;
312	319	case 0xc819: jr200_beep_w(space,0,data); break;
r14844	r14845
327	334
328	335	AM_RANGE(0xa000, 0xbfff) AM_ROM
329	336
330		AM_RANGE(0xc000, 0xc0ff) AM_READWRITE_LEGACY(jr200_pcg_1_r,jr200_pcg_1_w) //PCG area (1)
	337	AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(jr200_pcg_1_r,jr200_pcg_1_w) //PCG area (1)
331	338	AM_RANGE(0xc100, 0xc3ff) AM_RAM AM_BASE(m_vram)
332		AM_RANGE(0xc400, 0xc4ff) AM_READWRITE_LEGACY(jr200_pcg_2_r,jr200_pcg_2_w) //PCG area (2)
	339	AM_RANGE(0xc400, 0xc4ff) AM_READWRITE(jr200_pcg_2_r,jr200_pcg_2_w) //PCG area (2)
333	340	AM_RANGE(0xc500, 0xc7ff) AM_RAM AM_BASE(m_cram)
334	341
335	342	//  0xc800 - 0xcfff I / O area
336		AM_RANGE(0xc800, 0xcfff) AM_READWRITE_LEGACY(mn1271_io_r,mn1271_io_w) AM_BASE(m_mn1271_ram)
	343	AM_RANGE(0xc800, 0xcfff) AM_READWRITE(mn1271_io_r,mn1271_io_w) AM_BASE(m_mn1271_ram)
337	344
338		AM_RANGE(0xd000, 0xd7ff) AM_READWRITE_LEGACY(jr200_bios_char_r,jr200_bios_char_w) //BIOS PCG RAM area
	345	AM_RANGE(0xd000, 0xd7ff) AM_READWRITE(jr200_bios_char_r,jr200_bios_char_w) //BIOS PCG RAM area
339	346	AM_RANGE(0xd800, 0xdfff) AM_ROM // cart space (header 0x7e)
340	347	AM_RANGE(0xe000, 0xffff) AM_ROM
341	348	ADDRESS_MAP_END

src/mess/drivers/pyl601.c

r14844	r14845
28	28	UINT8 m_video_mode;
29	29	UINT8 m_tick50_mark;
30	30	UINT8 m_floppy_ctrl;
	31	DECLARE_READ8_MEMBER(rom_page_r);
	32	DECLARE_WRITE8_MEMBER(rom_page_w);
	33	DECLARE_WRITE8_MEMBER(vdisk_page_w);
	34	DECLARE_WRITE8_MEMBER(vdisk_h_w);
	35	DECLARE_WRITE8_MEMBER(vdisk_l_w);
	36	DECLARE_WRITE8_MEMBER(vdisk_data_w);
	37	DECLARE_READ8_MEMBER(vdisk_data_r);
	38	DECLARE_READ8_MEMBER(keyboard_r);
	39	DECLARE_READ8_MEMBER(keycheck_r);
	40	DECLARE_WRITE8_MEMBER(video_mode_w);
	41	DECLARE_READ8_MEMBER(video_mode_r);
	42	DECLARE_READ8_MEMBER(timer_r);
	43	DECLARE_WRITE8_MEMBER(speaker_w);
	44	DECLARE_WRITE8_MEMBER(led_w);
	45	DECLARE_WRITE8_MEMBER(floppy_w);
	46	DECLARE_READ8_MEMBER(floppy_r);
31	47	};
32	48
33	49
34	50
35		static READ8_HANDLER (rom_page_r)
	51	READ8_MEMBER(pyl601_state::rom_page_r)
36	52	{
37		pyl601_state *state = space->machine().driver_data<pyl601_state>();
38		return state->m_rom_page;
	53	return m_rom_page;
39	54	}
40	55
41		static WRITE8_HANDLER (rom_page_w)
	56	WRITE8_MEMBER(pyl601_state::rom_page_w)
42	57	{
43		pyl601_state *state = space->machine().driver_data<pyl601_state>();
44		state->m_rom_page =data;
	58	m_rom_page =data;
45	59	if (data & 8)
46	60	{
47	61	int chip = (data >> 4) % 5;
48	62	int page = data & 7;
49		memory_set_bankptr(space->machine(), "bank2", space->machine().region("romdisk")->base() + chip*0x10000 + page * 0x2000);
	63	memory_set_bankptr(machine(), "bank2", machine().region("romdisk")->base() + chip*0x10000 + page * 0x2000);
50	64	}
51	65	else
52	66	{
53		memory_set_bankptr(space->machine(), "bank2", space->machine().device<ram_device>(RAM_TAG)->pointer() + 0xc000);
	67	memory_set_bankptr(machine(), "bank2", machine().device<ram_device>(RAM_TAG)->pointer() + 0xc000);
54	68	}
55	69	}
56	70
57	71
58		static WRITE8_HANDLER (vdisk_page_w)
	72	WRITE8_MEMBER(pyl601_state::vdisk_page_w)
59	73	{
60		pyl601_state *state = space->machine().driver_data<pyl601_state>();
61		state->m_vdisk_addr = (state->m_vdisk_addr & 0x0ffff) | ((data & 0x0f)<<16);
	74	m_vdisk_addr = (m_vdisk_addr & 0x0ffff) | ((data & 0x0f)<<16);
62	75	}
63	76
64		static WRITE8_HANDLER (vdisk_h_w)
	77	WRITE8_MEMBER(pyl601_state::vdisk_h_w)
65	78	{
66		pyl601_state *state = space->machine().driver_data<pyl601_state>();
67		state->m_vdisk_addr = (state->m_vdisk_addr & 0xf00ff) | (data<<8);
	79	m_vdisk_addr = (m_vdisk_addr & 0xf00ff) | (data<<8);
68	80	}
69	81
70		static WRITE8_HANDLER (vdisk_l_w)
	82	WRITE8_MEMBER(pyl601_state::vdisk_l_w)
71	83	{
72		pyl601_state *state = space->machine().driver_data<pyl601_state>();
73		state->m_vdisk_addr = (state->m_vdisk_addr & 0xfff00) | data;
	84	m_vdisk_addr = (m_vdisk_addr & 0xfff00) | data;
74	85	}
75	86
76		static WRITE8_HANDLER (vdisk_data_w)
	87	WRITE8_MEMBER(pyl601_state::vdisk_data_w)
77	88	{
78		pyl601_state *state = space->machine().driver_data<pyl601_state>();
79		space->machine().device<ram_device>(RAM_TAG)->pointer()[0x10000 + (state->m_vdisk_addr & 0x7ffff)] = data;
80		state->m_vdisk_addr++;
81		state->m_vdisk_addr&=0x7ffff;
	89	machine().device<ram_device>(RAM_TAG)->pointer()[0x10000 + (m_vdisk_addr & 0x7ffff)] = data;
	90	m_vdisk_addr++;
	91	m_vdisk_addr&=0x7ffff;
82	92	}
83	93
84		static READ8_HANDLER (vdisk_data_r)
	94	READ8_MEMBER(pyl601_state::vdisk_data_r)
85	95	{
86		pyl601_state *state = space->machine().driver_data<pyl601_state>();
87		UINT8 retVal = space->machine().device<ram_device>(RAM_TAG)->pointer()[0x10000 + (state->m_vdisk_addr & 0x7ffff)];
88		state->m_vdisk_addr++;
89		state->m_vdisk_addr &= 0x7ffff;
	96	UINT8 retVal = machine().device<ram_device>(RAM_TAG)->pointer()[0x10000 + (m_vdisk_addr & 0x7ffff)];
	97	m_vdisk_addr++;
	98	m_vdisk_addr &= 0x7ffff;
90	99	return retVal;
91	100	}
92	101
r14844	r14845
103	112	return 0;
104	113	}
105	114
106		static READ8_HANDLER ( keyboard_r )
	115	READ8_MEMBER(pyl601_state::keyboard_r)
107	116	{
108		pyl601_state *state = space->machine().driver_data<pyl601_state>();
109		return state->m_key_code;
	117	return m_key_code;
110	118	}
111	119
112		static READ8_HANDLER ( keycheck_r )
	120	READ8_MEMBER(pyl601_state::keycheck_r)
113	121	{
114		pyl601_state *state = space->machine().driver_data<pyl601_state>();
115	122	UINT8 retVal = 0x3f;
116		UINT8 *keyboard = space->machine().region("keyboard")->base();
117		UINT16 row1 = input_port_read(space->machine(), "ROW1");
118		UINT16 row2 = input_port_read(space->machine(), "ROW2");
119		UINT16 row3 = input_port_read(space->machine(), "ROW3");
120		UINT16 row4 = input_port_read(space->machine(), "ROW4");
121		UINT16 row5 = input_port_read(space->machine(), "ROW5");
	123	UINT8 *keyboard = machine().region("keyboard")->base();
	124	UINT16 row1 = input_port_read(machine(), "ROW1");
	125	UINT16 row2 = input_port_read(machine(), "ROW2");
	126	UINT16 row3 = input_port_read(machine(), "ROW3");
	127	UINT16 row4 = input_port_read(machine(), "ROW4");
	128	UINT16 row5 = input_port_read(machine(), "ROW5");
122	129	UINT16 all = row1 | row2 | row3 | row4 | row5;
123		UINT16 addr = (input_port_read(space->machine(), "SHIFT") & 1) | (input_port_read(space->machine(), "CTRL") & 1) << 1;
	130	UINT16 addr = (input_port_read(machine(), "SHIFT") & 1) | (input_port_read(machine(), "CTRL") & 1) << 1;
124	131	if (all != 0xff)
125	132	{
126	133	addr |= selectedline(all) << 2;
r14844	r14845
131	138	addr |=  ((row2 == 0x00) ? 1 : 0) << 9;
132	139	addr |=  ((row1 == 0x00) ? 1 : 0) << 10;
133	140
134		state->m_key_code = keyboard[addr];
135		state->m_keyboard_clk = ~state->m_keyboard_clk;
	141	m_key_code = keyboard[addr];
	142	m_keyboard_clk = ~m_keyboard_clk;
136	143
137		if (state->m_keyboard_clk)
	144	if (m_keyboard_clk)
138	145	retVal |= 0x80;
139	146	}
140	147	return retVal;
141	148	}
142	149
143	150
144		static WRITE8_HANDLER (video_mode_w)
	151	WRITE8_MEMBER(pyl601_state::video_mode_w)
145	152	{
146		pyl601_state *state = space->machine().driver_data<pyl601_state>();
147		state->m_video_mode = data;
	153	m_video_mode = data;
148	154	}
149		static READ8_HANDLER (video_mode_r)
	155	READ8_MEMBER(pyl601_state::video_mode_r)
150	156	{
151		pyl601_state *state = space->machine().driver_data<pyl601_state>();
152		return state->m_video_mode;
	157	return m_video_mode;
153	158	}
154	159
155		static READ8_HANDLER (timer_r)
	160	READ8_MEMBER(pyl601_state::timer_r)
156	161	{
157		pyl601_state *state = space->machine().driver_data<pyl601_state>();
158		UINT8 retVal= state->m_tick50_mark | 0x37;
159		state->m_tick50_mark = 0;
	162	UINT8 retVal= m_tick50_mark | 0x37;
	163	m_tick50_mark = 0;
160	164	return retVal;
161	165	}
162	166
163		static WRITE8_HANDLER (speaker_w)
	167	WRITE8_MEMBER(pyl601_state::speaker_w)
164	168	{
165	169	}
166	170
167		static WRITE8_HANDLER (led_w)
	171	WRITE8_MEMBER(pyl601_state::led_w)
168	172	{
169	173	//  UINT8 caps_led = BIT(data,4);
170	174	}
r14844	r14845
178	182	{
179	183	return get_floppy_image(device->machine(), (floppy_index & 1)^1);
180	184	}
181		static WRITE8_HANDLER( floppy_w )
	185	WRITE8_MEMBER(pyl601_state::floppy_w)
182	186	{
183		pyl601_state *state = space->machine().driver_data<pyl601_state>();
184	187	// bit 0 is reset (if zero)
185	188	// bit 1 is TC state
186	189	// bit 2 is drive selected
187	190	// bit 3 is motor state
188		device_t *floppy = space->machine().device("upd765");
	191	device_t *floppy = machine().device("upd765");
189	192	if (BIT(data,0)==0) {
190	193	//reset
191	194	upd765_reset(floppy,0);
192	195	}
193		floppy_mon_w(get_floppy_image(space->machine(), BIT(data,2)), !BIT(data, 3));
	196	floppy_mon_w(get_floppy_image(machine(), BIT(data,2)), !BIT(data, 3));
194	197
195		floppy_drive_set_ready_state(get_floppy_image(space->machine(), 0), BIT(data,2), 0);
	198	floppy_drive_set_ready_state(get_floppy_image(machine(), 0), BIT(data,2), 0);
196	199
197	200	upd765_tc_w(floppy, BIT(data,1));
198	201
199		state->m_floppy_ctrl = data;
	202	m_floppy_ctrl = data;
200	203	}
201		static READ8_HANDLER (floppy_r)
	204	READ8_MEMBER(pyl601_state::floppy_r)
202	205	{
203		pyl601_state *state = space->machine().driver_data<pyl601_state>();
204		return state->m_floppy_ctrl;
	206	return m_floppy_ctrl;
205	207	}
206	208
207	209	static const struct upd765_interface pyldin_upd765_interface =
r14844	r14845
222	224	AM_RANGE( 0xe601, 0xe601 ) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
223	225	AM_RANGE( 0xe604, 0xe604 ) AM_DEVWRITE("crtc", mc6845_device, address_w)
224	226	AM_RANGE( 0xe605, 0xe605 ) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
225		AM_RANGE( 0xe628, 0xe628 ) AM_READ_LEGACY(keyboard_r)
226		AM_RANGE( 0xe629, 0xe629 ) AM_READWRITE_LEGACY(video_mode_r,video_mode_w)
227		AM_RANGE( 0xe62a, 0xe62a ) AM_READWRITE_LEGACY(keycheck_r,led_w)
228		AM_RANGE( 0xe62b, 0xe62b ) AM_READWRITE_LEGACY(timer_r,speaker_w)
229		AM_RANGE( 0xe62d, 0xe62d ) AM_READ_LEGACY(video_mode_r)
230		AM_RANGE( 0xe62e, 0xe62e ) AM_READWRITE_LEGACY(keycheck_r,led_w)
231		AM_RANGE( 0xe680, 0xe680 ) AM_WRITE_LEGACY(vdisk_page_w)
232		AM_RANGE( 0xe681, 0xe681 ) AM_WRITE_LEGACY(vdisk_h_w)
233		AM_RANGE( 0xe682, 0xe682 ) AM_WRITE_LEGACY(vdisk_l_w)
234		AM_RANGE( 0xe683, 0xe683 ) AM_READWRITE_LEGACY(vdisk_data_r,vdisk_data_w)
235		AM_RANGE( 0xe6c0, 0xe6c0 ) AM_READWRITE_LEGACY(floppy_r, floppy_w)
	227	AM_RANGE( 0xe628, 0xe628 ) AM_READ(keyboard_r)
	228	AM_RANGE( 0xe629, 0xe629 ) AM_READWRITE(video_mode_r,video_mode_w)
	229	AM_RANGE( 0xe62a, 0xe62a ) AM_READWRITE(keycheck_r,led_w)
	230	AM_RANGE( 0xe62b, 0xe62b ) AM_READWRITE(timer_r,speaker_w)
	231	AM_RANGE( 0xe62d, 0xe62d ) AM_READ(video_mode_r)
	232	AM_RANGE( 0xe62e, 0xe62e ) AM_READWRITE(keycheck_r,led_w)
	233	AM_RANGE( 0xe680, 0xe680 ) AM_WRITE(vdisk_page_w)
	234	AM_RANGE( 0xe681, 0xe681 ) AM_WRITE(vdisk_h_w)
	235	AM_RANGE( 0xe682, 0xe682 ) AM_WRITE(vdisk_l_w)
	236	AM_RANGE( 0xe683, 0xe683 ) AM_READWRITE(vdisk_data_r,vdisk_data_w)
	237	AM_RANGE( 0xe6c0, 0xe6c0 ) AM_READWRITE(floppy_r, floppy_w)
236	238	AM_RANGE( 0xe6d0, 0xe6d0 ) AM_DEVREAD_LEGACY("upd765", upd765_status_r)
237	239	AM_RANGE( 0xe6d1, 0xe6d1 ) AM_DEVREADWRITE_LEGACY("upd765", upd765_data_r, upd765_data_w)
238		AM_RANGE( 0xe6f0, 0xe6f0 ) AM_READWRITE_LEGACY(rom_page_r, rom_page_w)
	240	AM_RANGE( 0xe6f0, 0xe6f0 ) AM_READWRITE(rom_page_r, rom_page_w)
239	241	AM_RANGE( 0xe700, 0xefff ) AM_RAMBANK("bank4")
240	242	AM_RANGE( 0xf000, 0xffff ) AM_READ_BANK("bank5") AM_WRITE_BANK("bank6")
241	243	ADDRESS_MAP_END

src/mess/drivers/a310.c

r14844	r14845
71	71	a310_state(const machine_config &mconfig, device_type type, const char *tag)
72	72	: driver_device(mconfig, type, tag) { }
73	73
	74	DECLARE_READ32_MEMBER(a310_psy_wram_r);
	75	DECLARE_WRITE32_MEMBER(a310_psy_wram_w);
74	76	};
75	77
76	78
r14844	r14845
90	92	archimedes_clear_fiq(device->machine(), ARCHIMEDES_FIQ_FLOPPY_DRQ);
91	93	}
92	94
93		static READ32_HANDLER( a310_psy_wram_r )
	95	READ32_MEMBER(a310_state::a310_psy_wram_r)
94	96	{
95	97	return archimedes_memc_physmem[offset];
96	98	}
97	99
98		static WRITE32_HANDLER( a310_psy_wram_w )
	100	WRITE32_MEMBER(a310_state::a310_psy_wram_w)
99	101	{
100	102	COMBINE_DATA(&archimedes_memc_physmem[offset]);
101	103	}
r14844	r14845
104	106	static DRIVER_INIT(a310)
105	107	{
106	108	UINT32 ram_size = machine.device<ram_device>(RAM_TAG)->size();
107
	109	a310_state *state = machine.driver_data<a310_state>();
108	110	archimedes_memc_physmem = auto_alloc_array(machine, UINT32, 0x01000000);
109	111
110		machine.device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler( 0x02000000, 0x02000000+(ram_size-1), FUNC(a310_psy_wram_r), FUNC(a310_psy_wram_w) );
	112	machine.device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler( 0x02000000, 0x02000000+(ram_size-1), read32_delegate(FUNC(a310_state::a310_psy_wram_r), state), write32_delegate(FUNC(a310_state::a310_psy_wram_w), state));
111	113
112	114	archimedes_driver_init(machine);
113	115	}

src/mess/drivers/juicebox.c

r14844	r14845
54	54	#if defined(JUICEBOX_ENTER_DEBUG_MENU) || defined(JUICEBOX_DISPLAY_ROM_ID)
55	55	int port_g_read_count;
56	56	#endif
	57	DECLARE_READ32_MEMBER(juicebox_nand_r);
	58	DECLARE_WRITE32_MEMBER(juicebox_nand_w);
57	59	};
58	60
59	61	/***************************************************************************
r14844	r14845
203	205
204	206	// ...
205	207
206		static READ32_HANDLER( juicebox_nand_r )
	208	READ32_MEMBER(juicebox_state::juicebox_nand_r)
207	209	{
208		running_machine &machine = space->machine();
209	210	UINT32 data = 0;
210		if (mem_mask & 0x000000FF) data = data | (smc_read( machine) <<  0);
211		if (mem_mask & 0x0000FF00) data = data | (smc_read( machine) <<  8);
212		if (mem_mask & 0x00FF0000) data = data | (smc_read( machine) << 16);
213		if (mem_mask & 0xFF000000) data = data | (smc_read( machine) << 24);
214		verboselog( machine, 5, "juicebox_nand_r %08X %08X %08X\n", offset, mem_mask, data);
	211	if (mem_mask & 0x000000FF) data = data | (smc_read(machine()) <<  0);
	212	if (mem_mask & 0x0000FF00) data = data | (smc_read(machine()) <<  8);
	213	if (mem_mask & 0x00FF0000) data = data | (smc_read(machine()) << 16);
	214	if (mem_mask & 0xFF000000) data = data | (smc_read(machine()) << 24);
	215	verboselog( machine(), 5, "juicebox_nand_r %08X %08X %08X\n", offset, mem_mask, data);
215	216	return data;
216	217	}
217	218
218		static WRITE32_HANDLER( juicebox_nand_w )
	219	WRITE32_MEMBER(juicebox_state::juicebox_nand_w)
219	220	{
220		running_machine &machine = space->machine();
221		verboselog( machine, 5, "juicebox_nand_w %08X %08X %08X\n", offset, mem_mask, data);
222		if (mem_mask & 0x000000FF) smc_write( machine, (data >>  0) & 0xFF);
223		if (mem_mask & 0x0000FF00) smc_write( machine, (data >>  8) & 0xFF);
224		if (mem_mask & 0x00FF0000) smc_write( machine, (data >> 16) & 0xFF);
225		if (mem_mask & 0xFF000000) smc_write( machine, (data >> 24) & 0xFF);
	221	verboselog( machine(), 5, "juicebox_nand_w %08X %08X %08X\n", offset, mem_mask, data);
	222	if (mem_mask & 0x000000FF) smc_write(machine(), (data >>  0) & 0xFF);
	223	if (mem_mask & 0x0000FF00) smc_write(machine(), (data >>  8) & 0xFF);
	224	if (mem_mask & 0x00FF0000) smc_write(machine(), (data >> 16) & 0xFF);
	225	if (mem_mask & 0xFF000000) smc_write(machine(), (data >> 24) & 0xFF);
226	226	}
227	227
228	228	// I2S
r14844	r14845
264	264
265	265	static ADDRESS_MAP_START( juicebox_map, AS_PROGRAM, 32, juicebox_state )
266	266	AM_RANGE(0x00000000, 0x007fffff) AM_ROM
267		AM_RANGE(0x04000000, 0x04ffffff) AM_READWRITE_LEGACY(juicebox_nand_r, juicebox_nand_w )
	267	AM_RANGE(0x04000000, 0x04ffffff) AM_READWRITE(juicebox_nand_r, juicebox_nand_w )
268	268	AM_RANGE(0x0c000000, 0x0c1fffff) AM_RAM AM_MIRROR(0x00600000)
269	269	ADDRESS_MAP_END
270	270

src/mess/drivers/ip20.c

r14844	r14845
52	52
53	53	HPC_t m_HPC;
54	54	RTC_t m_RTC;
	55	DECLARE_READ32_MEMBER(hpc_r);
	56	DECLARE_WRITE32_MEMBER(hpc_w);
	57	DECLARE_READ32_MEMBER(int_r);
	58	DECLARE_WRITE32_MEMBER(int_w);
55	59	};
56	60
57	61
r14844	r14845
102	106	#define RTC_SECOND      state->m_RTC.nRAM[0x06]
103	107	#define RTC_HUNDREDTH   state->m_RTC.nRAM[0x05]
104	108
105		static READ32_HANDLER( hpc_r )
	109	READ32_MEMBER(ip20_state::hpc_r)
106	110	{
107		ip20_state *state = space->machine().driver_data<ip20_state>();
108	111	scc8530_t *scc;
109		running_machine &machine = space->machine();
110
111	112	offset <<= 2;
112	113	if( offset >= 0x0e00 && offset <= 0x0e7c )
113	114	{
114		verboselog(machine, 2, "RTC RAM[0x%02x] Read: %02x\n", ( offset - 0xe00 ) >> 2, state->m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ] );
115		return state->m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ];
	115	verboselog(machine(), 2, "RTC RAM[0x%02x] Read: %02x\n", ( offset - 0xe00 ) >> 2, m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ] );
	116	return m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ];
116	117	}
117	118	switch( offset )
118	119	{
119	120	case 0x05c:
120		verboselog(machine, 2, "HPC Unknown Read: %08x (%08x) (returning 0x000000a5 as kludge)\n", 0x1fb80000 + offset, mem_mask );
	121	verboselog(machine(), 2, "HPC Unknown Read: %08x (%08x) (returning 0x000000a5 as kludge)\n", 0x1fb80000 + offset, mem_mask );
121	122	return 0x0000a500;
122	123	case 0x00ac:
123		verboselog(machine, 2, "HPC Parallel Buffer Pointer Read: %08x (%08x)\n", state->m_HPC.nParBufPtr, mem_mask );
124		return state->m_HPC.nParBufPtr;
	124	verboselog(machine(), 2, "HPC Parallel Buffer Pointer Read: %08x (%08x)\n", m_HPC.nParBufPtr, mem_mask );
	125	return m_HPC.nParBufPtr;
125	126	case 0x00c0:
126		verboselog(machine, 2, "HPC Endianness Read: %08x (%08x)\n", 0x0000001f, mem_mask );
	127	verboselog(machine(), 2, "HPC Endianness Read: %08x (%08x)\n", 0x0000001f, mem_mask );
127	128	return 0x0000001f;
128	129	case 0x0120:
129	130	if (ACCESSING_BITS_8_15)
130	131	{
131		return ( wd33c93_r( space, 0 ) << 8 );
	132	return ( wd33c93_r( &space, 0 ) << 8 );
132	133	}
133	134	else
134	135	{
r14844	r14845
137	138	case 0x0124:
138	139	if (ACCESSING_BITS_8_15)
139	140	{
140		return ( wd33c93_r( space, 1 ) << 8 );
	141	return ( wd33c93_r( &space, 1 ) << 8 );
141	142	}
142	143	else
143	144	{
144	145	return 0;
145	146	}
146	147	case 0x01b0:
147		verboselog(machine, 2, "HPC Misc. Status Read: %08x (%08x)\n", state->m_HPC.nMiscStatus, mem_mask );
148		return state->m_HPC.nMiscStatus;
	148	verboselog(machine(), 2, "HPC Misc. Status Read: %08x (%08x)\n", m_HPC.nMiscStatus, mem_mask );
	149	return m_HPC.nMiscStatus;
149	150	case 0x01bc:
150	151	//      verboselog(machine, 2, "HPC CPU Serial EEPROM Read\n" );
151		return ( (space->machine().device<eeprom_device>("eeprom")->read_bit() << 4 ) );
	152	return ( (machine().device<eeprom_device>("eeprom")->read_bit() << 4 ) );
152	153	case 0x01c4:
153		verboselog(machine, 2, "HPC Local IO Register 0 Mask Read: %08x (%08x)\n", state->m_HPC.nLocalIOReg0Mask, mem_mask );
154		return state->m_HPC.nLocalIOReg0Mask;
	154	verboselog(machine(), 2, "HPC Local IO Register 0 Mask Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
	155	return m_HPC.nLocalIOReg0Mask;
155	156	case 0x01cc:
156		verboselog(machine, 2, "HPC Local IO Register 1 Mask Read: %08x (%08x)\n", state->m_HPC.nLocalIOReg0Mask, mem_mask );
157		return state->m_HPC.nLocalIOReg1Mask;
	157	verboselog(machine(), 2, "HPC Local IO Register 1 Mask Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
	158	return m_HPC.nLocalIOReg1Mask;
158	159	case 0x01d4:
159		verboselog(machine, 2, "HPC VME Interrupt Mask 0 Read: %08x (%08x)\n", state->m_HPC.nLocalIOReg0Mask, mem_mask );
160		return state->m_HPC.nVMEIntMask0;
	160	verboselog(machine(), 2, "HPC VME Interrupt Mask 0 Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
	161	return m_HPC.nVMEIntMask0;
161	162	case 0x01d8:
162		verboselog(machine, 2, "HPC VME Interrupt Mask 1 Read: %08x (%08x)\n", state->m_HPC.nLocalIOReg0Mask, mem_mask );
163		return state->m_HPC.nVMEIntMask1;
	163	verboselog(machine(), 2, "HPC VME Interrupt Mask 1 Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
	164	return m_HPC.nVMEIntMask1;
164	165	case 0x0d00:
165		verboselog(machine, 2, "HPC DUART0 Channel B Control Read\n" );
	166	verboselog(machine(), 2, "HPC DUART0 Channel B Control Read\n" );
166	167	//      return 0x00000004;
167		return 0x7c; //scc->reg_r(*space, 0);
	168	return 0x7c; //scc->reg_r(*&space, 0);
168	169	case 0x0d04:
169		verboselog(machine, 2, "HPC DUART0 Channel B Data Read\n" );
	170	verboselog(machine(), 2, "HPC DUART0 Channel B Data Read\n" );
170	171	//      return 0;
171		scc = space->machine().device<scc8530_t>("scc");
172		return scc->reg_r(*space, 2);
	172	scc = machine().device<scc8530_t>("scc");
	173	return scc->reg_r(*&space, 2);
173	174	case 0x0d08:
174		verboselog(machine, 2, "HPC DUART0 Channel A Control Read (%08x)\n", mem_mask    );
	175	verboselog(machine(), 2, "HPC DUART0 Channel A Control Read (%08x)\n", mem_mask    );
175	176	//      return 0x40;
176		return 0x7c; //scc->reg_r(*space, 1);
	177	return 0x7c; //scc->reg_r(*&space, 1);
177	178	case 0x0d0c:
178		verboselog(machine, 2, "HPC DUART0 Channel A Data Read\n" );
	179	verboselog(machine(), 2, "HPC DUART0 Channel A Data Read\n" );
179	180	//      return 0;
180		scc = space->machine().device<scc8530_t>("scc");
181		return scc->reg_r(*space, 3);
	181	scc = machine().device<scc8530_t>("scc");
	182	return scc->reg_r(*&space, 3);
182	183	case 0x0d10:
183	184	//      verboselog(machine, 2, "HPC DUART1 Channel B Control Read\n" );
184	185	return 0x00000004;
185	186	case 0x0d14:
186		verboselog(machine, 2, "HPC DUART1 Channel B Data Read\n" );
	187	verboselog(machine(), 2, "HPC DUART1 Channel B Data Read\n" );
187	188	return 0;
188	189	case 0x0d18:
189		verboselog(machine, 2, "HPC DUART1 Channel A Control Read\n" );
	190	verboselog(machine(), 2, "HPC DUART1 Channel A Control Read\n" );
190	191	return 0;
191	192	case 0x0d1c:
192		verboselog(machine, 2, "HPC DUART1 Channel A Data Read\n" );
	193	verboselog(machine(), 2, "HPC DUART1 Channel A Data Read\n" );
193	194	return 0;
194	195	case 0x0d20:
195		verboselog(machine, 2, "HPC DUART2 Channel B Control Read\n" );
	196	verboselog(machine(), 2, "HPC DUART2 Channel B Control Read\n" );
196	197	return 0x00000004;
197	198	case 0x0d24:
198		verboselog(machine, 2, "HPC DUART2 Channel B Data Read\n" );
	199	verboselog(machine(), 2, "HPC DUART2 Channel B Data Read\n" );
199	200	return 0;
200	201	case 0x0d28:
201		verboselog(machine, 2, "HPC DUART2 Channel A Control Read\n" );
	202	verboselog(machine(), 2, "HPC DUART2 Channel A Control Read\n" );
202	203	return 0;
203	204	case 0x0d2c:
204		verboselog(machine, 2, "HPC DUART2 Channel A Data Read\n" );
	205	verboselog(machine(), 2, "HPC DUART2 Channel A Data Read\n" );
205	206	return 0;
206	207	case 0x0d30:
207		verboselog(machine, 2, "HPC DUART3 Channel B Control Read\n" );
	208	verboselog(machine(), 2, "HPC DUART3 Channel B Control Read\n" );
208	209	return 0x00000004;
209	210	case 0x0d34:
210		verboselog(machine, 2, "HPC DUART3 Channel B Data Read\n" );
	211	verboselog(machine(), 2, "HPC DUART3 Channel B Data Read\n" );
211	212	return 0;
212	213	case 0x0d38:
213		verboselog(machine, 2, "HPC DUART3 Channel A Control Read\n" );
	214	verboselog(machine(), 2, "HPC DUART3 Channel A Control Read\n" );
214	215	return 0;
215	216	case 0x0d3c:
216		verboselog(machine, 2, "HPC DUART3 Channel A Data Read\n" );
	217	verboselog(machine(), 2, "HPC DUART3 Channel A Data Read\n" );
217	218	return 0;
218	219	}
219		verboselog(machine, 0, "Unmapped HPC read: 0x%08x (%08x)\n", 0x1fb80000 + offset, mem_mask );
	220	verboselog(machine(), 0, "Unmapped HPC read: 0x%08x (%08x)\n", 0x1fb80000 + offset, mem_mask );
220	221	return 0;
221	222	}
222	223
223		static WRITE32_HANDLER( hpc_w )
	224	WRITE32_MEMBER(ip20_state::hpc_w)
224	225	{
225		ip20_state *state = space->machine().driver_data<ip20_state>();
226	226	scc8530_t *scc;
227	227	eeprom_device *eeprom;
228		running_machine &machine = space->machine();
229
230		eeprom = space->machine().device<eeprom_device>("eeprom");
	228	eeprom = machine().device<eeprom_device>("eeprom");
231	229	offset <<= 2;
232	230	if( offset >= 0x0e00 && offset <= 0x0e7c )
233	231	{
234		verboselog(machine, 2, "RTC RAM[0x%02x] Write: %02x\n", ( offset - 0xe00 ) >> 2, data & 0x000000ff );
235		state->m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ] = data & 0x000000ff;
	232	verboselog(machine(), 2, "RTC RAM[0x%02x] Write: %02x\n", ( offset - 0xe00 ) >> 2, data & 0x000000ff );
	233	m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ] = data & 0x000000ff;
236	234	switch( ( offset - 0xe00 ) >> 2 )
237	235	{
238	236	case 0:
239	237	break;
240	238	case 4:
241		if( !( state->m_RTC.nRAM[0x00] & 0x80 ) )
	239	if( !( m_RTC.nRAM[0x00] & 0x80 ) )
242	240	{
243	241	if( data & 0x80 )
244	242	{
245		state->m_RTC.nRAM[0x19] = RTC_SECOND;
246		state->m_RTC.nRAM[0x1a] = RTC_MINUTE;
247		state->m_RTC.nRAM[0x1b] = RTC_HOUR;
248		state->m_RTC.nRAM[0x1c] = RTC_DAY;
249		state->m_RTC.nRAM[0x1d] = RTC_MONTH;
	243	m_RTC.nRAM[0x19] = m_RTC.nRAM[0x06]; //RTC_SECOND;
	244	m_RTC.nRAM[0x1a] = m_RTC.nRAM[0x07]; //RTC_MINUTE;
	245	m_RTC.nRAM[0x1b] = m_RTC.nRAM[0x08]; //RTC_HOUR;
	246	m_RTC.nRAM[0x1c] = m_RTC.nRAM[0x09]; //RTC_DAY;
	247	m_RTC.nRAM[0x1d] = m_RTC.nRAM[0x0a]; //RTC_MONTH;
250	248	}
251	249	}
252	250	break;
r14844	r14845
256	254	switch( offset )
257	255	{
258	256	case 0x0090:   // SCSI0 next descriptor pointer
259		state->m_HPC.nSCSI0Descriptor = data;
	257	m_HPC.nSCSI0Descriptor = data;
260	258	break;
261	259
262	260	case 0x0094:   // SCSI0 control flags
263		state->m_HPC.nSCSI0DMACtrl = data;
	261	m_HPC.nSCSI0DMACtrl = data;
264	262	#if 0
265	263	if (data & 0x80)
266	264	{
r14844	r14845
269	267	mame_printf_info("DMA activated for SCSI0\n");
270	268	mame_printf_info("Descriptor block:\n");
271	269	mame_printf_info("CTL: %08x BUFPTR: %08x DESCPTR %08x\n",
272		program_read_dword(state->m_HPC.nSCSI0Descriptor), program_read_dword(state->m_HPC.nSCSI0Descriptor+4),
273		program_read_dword(state->m_HPC.nSCSI0Descriptor+8));
	270	program_read_dword(m_HPC.nSCSI0Descriptor), program_read_dword(m_HPC.nSCSI0Descriptor+4),
	271	program_read_dword(m_HPC.nSCSI0Descriptor+8));
274	272
275		next = program_read_dword(state->m_HPC.nSCSI0Descriptor+8);
	273	next = program_read_dword(m_HPC.nSCSI0Descriptor+8);
276	274	mame_printf_info("CTL: %08x BUFPTR: %08x DESCPTR %08x\n",
277	275	program_read_dword(next), program_read_dword(next+4),
278	276	program_read_dword(next+8));
r14844	r14845
281	279	break;
282	280
283	281	case 0x00ac:
284		verboselog(machine, 2, "HPC Parallel Buffer Pointer Write: %08x (%08x)\n", data, mem_mask );
285		state->m_HPC.nParBufPtr = data;
	282	verboselog(machine(), 2, "HPC Parallel Buffer Pointer Write: %08x (%08x)\n", data, mem_mask );
	283	m_HPC.nParBufPtr = data;
286	284	break;
287	285	case 0x0120:
288	286	if (ACCESSING_BITS_8_15)
289	287	{
290		verboselog(machine, 2, "HPC SCSI Controller Register Write: %08x\n", ( data >> 8 ) & 0x000000ff );
291		wd33c93_w( space, 0, ( data >> 8 ) & 0x000000ff );
	288	verboselog(machine(), 2, "HPC SCSI Controller Register Write: %08x\n", ( data >> 8 ) & 0x000000ff );
	289	wd33c93_w( &space, 0, ( data >> 8 ) & 0x000000ff );
292	290	}
293	291	else
294	292	{
r14844	r14845
298	296	case 0x0124:
299	297	if (ACCESSING_BITS_8_15)
300	298	{
301		verboselog(machine, 2, "HPC SCSI Controller Data Write: %08x\n", ( data >> 8 ) & 0x000000ff );
302		wd33c93_w( space, 1, ( data >> 8 ) & 0x000000ff );
	299	verboselog(machine(), 2, "HPC SCSI Controller Data Write: %08x\n", ( data >> 8 ) & 0x000000ff );
	300	wd33c93_w( &space, 1, ( data >> 8 ) & 0x000000ff );
303	301	}
304	302	else
305	303	{
r14844	r14845
307	305	}
308	306	break;
309	307	case 0x01b0:
310		verboselog(machine, 2, "HPC Misc. Status Write: %08x (%08x)\n", data, mem_mask );
	308	verboselog(machine(), 2, "HPC Misc. Status Write: %08x (%08x)\n", data, mem_mask );
311	309	if( data & 0x00000001 )
312	310	{
313		verboselog(machine, 2, "  Force DSP hard reset\n" );
	311	verboselog(machine(), 2, "  Force DSP hard reset\n" );
314	312	}
315	313	if( data & 0x00000002 )
316	314	{
317		verboselog(machine, 2, "  Force IRQA\n" );
	315	verboselog(machine(), 2, "  Force IRQA\n" );
318	316	}
319	317	if( data & 0x00000004 )
320	318	{
321		verboselog(machine, 2, "  Set IRQA polarity high\n" );
	319	verboselog(machine(), 2, "  Set IRQA polarity high\n" );
322	320	}
323	321	else
324	322	{
325		verboselog(machine, 2, "  Set IRQA polarity low\n" );
	323	verboselog(machine(), 2, "  Set IRQA polarity low\n" );
326	324	}
327	325	if( data & 0x00000008 )
328	326	{
329		verboselog(machine, 2, "  SRAM size: 32K\n" );
	327	verboselog(machine(), 2, "  SRAM size: 32K\n" );
330	328	}
331	329	else
332	330	{
333		verboselog(machine, 2, "  SRAM size:  8K\n" );
	331	verboselog(machine(), 2, "  SRAM size:  8K\n" );
334	332	}
335		state->m_HPC.nMiscStatus = data;
	333	m_HPC.nMiscStatus = data;
336	334	break;
337	335	case 0x01bc:
338	336	//      verboselog(machine, 2, "HPC CPU Serial EEPROM Write: %08x (%08x)\n", data, mem_mask );
339	337	if( data & 0x00000001 )
340	338	{
341		verboselog(machine, 2, "    CPU board LED on\n" );
	339	verboselog(machine(), 2, "    CPU board LED on\n" );
342	340	}
343	341	eeprom->write_bit((data & 0x00000008) ? 1 : 0 );
344	342	eeprom->set_cs_line((data & 0x00000002) ? ASSERT_LINE : CLEAR_LINE );
345	343	eeprom->set_clock_line((data & 0x00000004) ? CLEAR_LINE : ASSERT_LINE );
346	344	break;
347	345	case 0x01c4:
348		verboselog(machine, 2, "HPC Local IO Register 0 Mask Write: %08x (%08x)\n", data, mem_mask );
349		state->m_HPC.nLocalIOReg0Mask = data;
	346	verboselog(machine(), 2, "HPC Local IO Register 0 Mask Write: %08x (%08x)\n", data, mem_mask );
	347	m_HPC.nLocalIOReg0Mask = data;
350	348	break;
351	349	case 0x01cc:
352		verboselog(machine, 2, "HPC Local IO Register 1 Mask Write: %08x (%08x)\n", data, mem_mask );
353		state->m_HPC.nLocalIOReg1Mask = data;
	350	verboselog(machine(), 2, "HPC Local IO Register 1 Mask Write: %08x (%08x)\n", data, mem_mask );
	351	m_HPC.nLocalIOReg1Mask = data;
354	352	break;
355	353	case 0x01d4:
356		verboselog(machine, 2, "HPC VME Interrupt Mask 0 Write: %08x (%08x)\n", data, mem_mask );
357		state->m_HPC.nVMEIntMask0 = data;
	354	verboselog(machine(), 2, "HPC VME Interrupt Mask 0 Write: %08x (%08x)\n", data, mem_mask );
	355	m_HPC.nVMEIntMask0 = data;
358	356	break;
359	357	case 0x01d8:
360		verboselog(machine, 2, "HPC VME Interrupt Mask 1 Write: %08x (%08x)\n", data, mem_mask );
361		state->m_HPC.nVMEIntMask1 = data;
	358	verboselog(machine(), 2, "HPC VME Interrupt Mask 1 Write: %08x (%08x)\n", data, mem_mask );
	359	m_HPC.nVMEIntMask1 = data;
362	360	break;
363	361	case 0x0d00:
364		verboselog(machine, 2, "HPC DUART0 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
365		scc = space->machine().device<scc8530_t>("scc");
366		scc->reg_w(*space, 0, data);
	362	verboselog(machine(), 2, "HPC DUART0 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
	363	scc = machine().device<scc8530_t>("scc");
	364	scc->reg_w(*&space, 0, data);
367	365	break;
368	366	case 0x0d04:
369		verboselog(machine, 2, "HPC DUART0 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
370		scc = space->machine().device<scc8530_t>("scc");
371		scc->reg_w(*space, 2, data);
	367	verboselog(machine(), 2, "HPC DUART0 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
	368	scc = machine().device<scc8530_t>("scc");
	369	scc->reg_w(*&space, 2, data);
372	370	break;
373	371	case 0x0d08:
374		verboselog(machine, 2, "HPC DUART0 Channel A Control Write: %08x (%08x)\n", data, mem_mask );
375		scc = space->machine().device<scc8530_t>("scc");
376		scc->reg_w(*space, 1, data);
	372	verboselog(machine(), 2, "HPC DUART0 Channel A Control Write: %08x (%08x)\n", data, mem_mask );
	373	scc = machine().device<scc8530_t>("scc");
	374	scc->reg_w(*&space, 1, data);
377	375	break;
378	376	case 0x0d0c:
379		verboselog(machine, 2, "HPC DUART0 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
380		scc = space->machine().device<scc8530_t>("scc");
381		scc->reg_w(*space, 3, data);
	377	verboselog(machine(), 2, "HPC DUART0 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
	378	scc = machine().device<scc8530_t>("scc");
	379	scc->reg_w(*&space, 3, data);
382	380	break;
383	381	case 0x0d10:
384	382	if( ( data & 0x000000ff ) >= 0x00000020 )
385	383	{
386		//          verboselog(machine, 2, "HPC DUART1 Channel B Control Write: %08x (%08x) %c\n", data, mem_mask, data & 0x000000ff );
	384	//          verboselog(machine(), 2, "HPC DUART1 Channel B Control Write: %08x (%08x) %c\n", data, mem_mask, data & 0x000000ff );
387	385	//mame_printf_info( "%c", data & 0x000000ff );
388	386	}
389	387	else
390	388	{
391		//          verboselog(machine, 2, "HPC DUART1 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
	389	//          verboselog(machine(), 2, "HPC DUART1 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
392	390	}
393	391	break;
394	392	case 0x0d14:
395	393	if( ( data & 0x000000ff ) >= 0x00000020 || ( data & 0x000000ff ) == 0x0d || ( data & 0x000000ff ) == 0x0a )
396	394	{
397		verboselog(machine, 2, "HPC DUART1 Channel B Data Write: %08x (%08x) %c\n", data, mem_mask, data & 0x000000ff );
	395	verboselog(machine(), 2, "HPC DUART1 Channel B Data Write: %08x (%08x) %c\n", data, mem_mask, data & 0x000000ff );
398	396	mame_printf_info( "%c", data & 0x000000ff );
399	397	}
400	398	else
401	399	{
402		verboselog(machine, 2, "HPC DUART1 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
	400	verboselog(machine(), 2, "HPC DUART1 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
403	401	}
404	402	break;
405	403	case 0x0d18:
406	404	mame_printf_info("HPC DUART1 Channel A Control Write: %08x (%08x)\n", data, mem_mask );
407	405	break;
408	406	case 0x0d1c:
409		verboselog(machine, 2, "HPC DUART1 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
	407	verboselog(machine(), 2, "HPC DUART1 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
410	408	break;
411	409	case 0x0d20:
412	410	mame_printf_info("HPC DUART2 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
413	411	break;
414	412	case 0x0d24:
415		verboselog(machine, 2, "HPC DUART2 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
	413	verboselog(machine(), 2, "HPC DUART2 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
416	414	break;
417	415	case 0x0d28:
418	416	mame_printf_info("HPC DUART2 Channel A Control Write: %08x (%08x)\n", data, mem_mask );
419	417	break;
420	418	case 0x0d2c:
421		verboselog(machine, 2, "HPC DUART2 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
	419	verboselog(machine(), 2, "HPC DUART2 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
422	420	break;
423	421	case 0x0d30:
424	422	mame_printf_info("HPC DUART3 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
425	423	break;
426	424	case 0x0d34:
427		verboselog(machine, 2, "HPC DUART3 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
	425	verboselog(machine(), 2, "HPC DUART3 Channel B Data Write: %08x (%08x)\n", data, mem_mask );
428	426	break;
429	427	case 0x0d38:
430	428	mame_printf_info("HPC DUART3 Channel A Control Write: %08x (%08x)\n", data, mem_mask );
431	429	break;
432	430	case 0x0d3c:
433		verboselog(machine, 2, "HPC DUART3 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
	431	verboselog(machine(), 2, "HPC DUART3 Channel A Data Write: %08x (%08x)\n", data, mem_mask );
434	432	break;
435	433	default:
436	434	mame_printf_info("Unmapped HPC write: 0x%08x (%08x): %08x\n", 0x1fb80000 + offset, mem_mask, data);
r14844	r14845
439	437	}
440	438
441	439	// INT/INT2/INT3 interrupt controllers
442		static READ32_HANDLER( int_r )
	440	READ32_MEMBER(ip20_state::int_r)
443	441	{
444		mame_printf_info("INT: read @ ofs %x (mask %x) (PC=%x)\n", offset, mem_mask, cpu_get_pc(&space->device()));
	442	mame_printf_info("INT: read @ ofs %x (mask %x) (PC=%x)\n", offset, mem_mask, cpu_get_pc(&space.device()));
445	443	return 0;
446	444	}
447	445
448		static WRITE32_HANDLER( int_w )
	446	WRITE32_MEMBER(ip20_state::int_w)
449	447	{
450		mame_printf_info("INT: write %x to ofs %x (mask %x) (PC=%x)\n", data, offset, mem_mask, cpu_get_pc(&space->device()));
	448	mame_printf_info("INT: write %x to ofs %x (mask %x) (PC=%x)\n", data, offset, mem_mask, cpu_get_pc(&space.device()));
451	449	}
452	450
453	451	static ADDRESS_MAP_START( ip204415_map, AS_PROGRAM, 32, ip20_state )
r14844	r14845
459	457	AM_RANGE( 0x10000000, 0x107fffff ) AM_RAM AM_SHARE("share9")
460	458	AM_RANGE( 0x18000000, 0x187fffff ) AM_RAM AM_SHARE("share1")
461	459	AM_RANGE( 0x1fa00000, 0x1fa1ffff ) AM_READWRITE_LEGACY(sgi_mc_r, sgi_mc_w )
462		AM_RANGE( 0x1fb80000, 0x1fb8ffff ) AM_READWRITE_LEGACY(hpc_r, hpc_w )
463		AM_RANGE( 0x1fbd9000, 0x1fbd903f ) AM_READWRITE_LEGACY(int_r, int_w )
	460	AM_RANGE( 0x1fb80000, 0x1fb8ffff ) AM_READWRITE(hpc_r, hpc_w )
	461	AM_RANGE( 0x1fbd9000, 0x1fbd903f ) AM_READWRITE(int_r, int_w )
464	462	AM_RANGE( 0x1fc00000, 0x1fc7ffff ) AM_ROM AM_SHARE("share2") AM_REGION( "user1", 0 )
465	463	AM_RANGE( 0x80000000, 0x801fffff ) AM_RAM AM_SHARE("share10")
466	464	AM_RANGE( 0x88000000, 0x88ffffff ) AM_RAM AM_SHARE("share5")
r14844	r14845
472	470	AM_RANGE( 0xb0000000, 0xb07fffff ) AM_RAM AM_SHARE("share9")
473	471	AM_RANGE( 0xb8000000, 0xb87fffff ) AM_RAM AM_SHARE("share1")
474	472	AM_RANGE( 0xbfa00000, 0xbfa1ffff ) AM_READWRITE_LEGACY(sgi_mc_r, sgi_mc_w )
475		AM_RANGE( 0xbfb80000, 0xbfb8ffff ) AM_READWRITE_LEGACY(hpc_r, hpc_w )
476		AM_RANGE( 0xbfbd9000, 0xbfbd903f ) AM_READWRITE_LEGACY(int_r, int_w )
	473	AM_RANGE( 0xbfb80000, 0xbfb8ffff ) AM_READWRITE(hpc_r, hpc_w )
	474	AM_RANGE( 0xbfbd9000, 0xbfbd903f ) AM_READWRITE(int_r, int_w )
477	475	AM_RANGE( 0xbfc00000, 0xbfc7ffff ) AM_ROM AM_SHARE("share2") /* BIOS Mirror */
478	476	ADDRESS_MAP_END
479	477

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