src/mess/drivers/pc88va.c
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| 15 | 15 | #include "emu.h" |
| 16 | 16 | #include "cpu/nec/nec.h" |
| 17 | 17 | //#include "cpu/z80/z80.h" |
| 18 | #include "machine/i8255a.h" |
| 18 | 19 | |
| 19 | 20 | static UINT16 *palram; |
| 20 | 21 | static UINT16 bank_reg; |
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| 212 | 213 | ---- ---- xxxx ---- RBC1 (0xf0000 - 0xfffff ROM bank) |
| 213 | 214 | ---- ---- ---- xxxx RBC0 (0xe0000 - 0xeffff ROM bank) |
| 214 | 215 | */ |
| 215 | | bank_reg = data; |
| 216 | if ((mem_mask&0xffff) == 0xffff) |
| 217 | bank_reg = data; |
| 218 | else if ((mem_mask & 0xffff) == 0xff00) |
| 219 | bank_reg = (data & 0xff00) | (bank_reg & 0x00ff); |
| 220 | else if ((mem_mask & 0xffff) == 0x00ff) |
| 221 | bank_reg = (data & 0x00ff) | (bank_reg & 0xff00); |
| 216 | 222 | |
| 223 | |
| 217 | 224 | /* RBC1 */ |
| 218 | 225 | { |
| 219 | 226 | UINT8 *ROM10 = memory_region(space->machine, "rom10"); |
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| 251 | 258 | backupram_wp = 0; |
| 252 | 259 | } |
| 253 | 260 | |
| 261 | static READ8_HANDLER( hdd_status_r ) |
| 262 | { |
| 263 | return 0x20; |
| 264 | } |
| 265 | |
| 266 | static READ8_HANDLER( fdc_r ) |
| 267 | { |
| 268 | return mame_rand(space->machine); |
| 269 | } |
| 270 | |
| 254 | 271 | static ADDRESS_MAP_START( pc88va_io_map, ADDRESS_SPACE_IO, 16 ) |
| 255 | 272 | AM_RANGE(0x0000, 0x000f) AM_READ8(key_r,0xffff) // Keyboard ROW reading |
| 256 | 273 | // AM_RANGE(0x0010, 0x0010) Printer / Calendar Clock Interface |
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| 268 | 285 | // AM_RANGE(0x0070, 0x0070) ? (*) |
| 269 | 286 | // AM_RANGE(0x0071, 0x0071) Expansion ROM select (*) |
| 270 | 287 | // AM_RANGE(0x0078, 0x0078) Memory offset increment (*) |
| 271 | | // AM_RANGE(0x0080, 0x0083) HDD control, byte access 7-0 |
| 288 | // AM_RANGE(0x0080, 0x0081) HDD related |
| 289 | AM_RANGE(0x0082, 0x0083) AM_READ8(hdd_status_r,0xff)// HDD control, byte access 7-0 |
| 272 | 290 | // AM_RANGE(0x00bc, 0x00bf) d8255 1 |
| 273 | 291 | // AM_RANGE(0x00e2, 0x00e3) Expansion RAM selection (*) |
| 274 | 292 | // AM_RANGE(0x00e4, 0x00e4) 8214 IRQ control (*) |
| 275 | 293 | // AM_RANGE(0x00e6, 0x00e6) 8214 IRQ mask (*) |
| 276 | 294 | // AM_RANGE(0x00e8, 0x00e9) ? (*) |
| 277 | 295 | // AM_RANGE(0x00ec, 0x00ed) ? (*) |
| 278 | | // AM_RANGE(0x00fc, 0x00ff) d8255 2, FDD |
| 296 | |
| 279 | 297 | |
| 280 | 298 | // AM_RANGE(0x0100, 0x0101) Screen Control Register |
| 281 | 299 | // AM_RANGE(0x0102, 0x0103) Graphic Screen Control Register |
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| 307 | 325 | AM_RANGE(0x019a, 0x019b) AM_WRITE(backupram_wp_0_w) //Backup RAM write permission |
| 308 | 326 | // AM_RANGE(0x01a0, 0x01a7) TCU (timer counter unit) |
| 309 | 327 | // AM_RANGE(0x01a8, 0x01a9) General-purpose timer 3 control port |
| 310 | | // AM_RANGE(0x01b0, 0x01bb) FDC related (765) |
| 328 | |
| 311 | 329 | // AM_RANGE(0x01c0, 0x01c1) ? |
| 312 | 330 | // AM_RANGE(0x01c8, 0x01cf) i8255 3 (byte access) |
| 313 | 331 | // AM_RANGE(0x01d0, 0x01d1) Expansion RAM bank selection |
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| 375 | 393 | GFXDECODE_ENTRY( "kanji", 0x00000, pc88va_chars_16x16, 0, 1 ) |
| 376 | 394 | GFXDECODE_END |
| 377 | 395 | |
| 396 | static READ8_DEVICE_HANDLER( fdd_porta_r ) |
| 397 | { |
| 398 | return 0xff; |
| 399 | } |
| 378 | 400 | |
| 401 | static READ8_DEVICE_HANDLER( fdd_portb_r ) |
| 402 | { |
| 403 | return 0xff; |
| 404 | } |
| 405 | |
| 406 | static READ8_DEVICE_HANDLER( fdd_portc_r ) |
| 407 | { |
| 408 | static UINT8 test1,test2; |
| 409 | |
| 410 | test1^=4; |
| 411 | test2^=1; |
| 412 | |
| 413 | return 0xff ^ test1 ^ test2; |
| 414 | } |
| 415 | |
| 416 | static WRITE8_DEVICE_HANDLER( fdd_porta_w ) |
| 417 | { |
| 418 | // ... |
| 419 | } |
| 420 | |
| 421 | static WRITE8_DEVICE_HANDLER( fdd_portb_w ) |
| 422 | { |
| 423 | // ... |
| 424 | } |
| 425 | |
| 426 | static WRITE8_DEVICE_HANDLER( fdd_portc_w ) |
| 427 | { |
| 428 | // ... |
| 429 | } |
| 430 | |
| 431 | static I8255A_INTERFACE( fdd_intf ) |
| 432 | { |
| 433 | DEVCB_HANDLER(fdd_porta_r), /* Port A read */ |
| 434 | DEVCB_HANDLER(fdd_portb_r), /* Port B read */ |
| 435 | DEVCB_HANDLER(fdd_portc_r), /* Port C read */ |
| 436 | DEVCB_HANDLER(fdd_porta_w), /* Port A write */ |
| 437 | DEVCB_HANDLER(fdd_portb_w), /* Port B write */ |
| 438 | DEVCB_HANDLER(fdd_portc_w) /* Port C write */ |
| 439 | }; |
| 440 | |
| 379 | 441 | static MACHINE_CONFIG_START( pc88va, driver_device ) |
| 380 | 442 | |
| 381 | 443 | MDRV_CPU_ADD("maincpu", V30, 8000000) /* 8 MHz */ |
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| 402 | 464 | |
| 403 | 465 | MDRV_MACHINE_RESET( pc88va ) |
| 404 | 466 | |
| 467 | MDRV_I8255A_ADD( "d8255_2", fdd_intf ) |
| 468 | |
| 469 | |
| 405 | 470 | MACHINE_CONFIG_END |
| 406 | 471 | |
| 407 | 472 | |