src/mess/drivers/pc88va.c
| r9446 | r9447 | |
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| 18 | 18 | |
| 19 | 19 | static UINT16 *palram; |
| 20 | 20 | static UINT16 bank_reg; |
| 21 | static UINT8 backupram_wp; |
| 21 | 22 | |
| 22 | 23 | static VIDEO_START( pc88va ) |
| 23 | 24 | { |
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| 39 | 40 | { |
| 40 | 41 | UINT16 *tvram = (UINT16 *)memory_region(space->machine, "tvram"); |
| 41 | 42 | |
| 42 | | if((offset & 0x30000) == 0) |
| 43 | if(((offset*2) & 0x30000) == 0) |
| 43 | 44 | return tvram[offset]; |
| 44 | 45 | |
| 45 | 46 | return 0xffff; |
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| 56 | 57 | UINT16 *knj_ram = (UINT16 *)memory_region(space->machine, "kanji"); |
| 57 | 58 | UINT32 knj_offset; |
| 58 | 59 | |
| 59 | | knj_offset = (offset + (((bank_reg & 0x100) >> 8)*0x40000)) / 2; |
| 60 | knj_offset = (offset + (((bank_reg & 0x100) >> 8)*0x20000)) |
| 60 | 61 | |
| 61 | 62 | /* 0x00000 - 0x3ffff Kanji ROM 1*/ |
| 62 | 63 | /* 0x40000 - 0x4ffff Kanji ROM 2*/ |
| 63 | | /* 0x50000 - 0x53fff Kanji RAM */ |
| 64 | /* 0x50000 - 0x53fff Backup RAM */ |
| 64 | 65 | /* anything else is a NOP (I presume?) */ |
| 65 | 66 | |
| 66 | 67 | return knj_ram[knj_offset]; |
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| 72 | 73 | UINT16 *dic_rom = (UINT16 *)memory_region(space->machine, "dictionary"); |
| 73 | 74 | UINT32 dic_offset; |
| 74 | 75 | |
| 75 | | dic_offset = (offset + (((bank_reg & 0x100) >> 8)*0x40000)) / 2; |
| 76 | dic_offset = (offset + (((bank_reg & 0x100) >> 8)*0x20000)) |
| 76 | 77 | |
| 77 | 78 | return dic_rom[dic_offset]; |
| 78 | 79 | } |
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| 91 | 92 | { |
| 92 | 93 | UINT16 *tvram = (UINT16 *)memory_region(space->machine, "tvram"); |
| 93 | 94 | |
| 94 | | if((offset & 0x30000) == 0) |
| 95 | if(((offset*2) & 0x30000) == 0) |
| 95 | 96 | COMBINE_DATA(&tvram[offset]); |
| 96 | 97 | } |
| 97 | 98 | break; |
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| 108 | 109 | UINT16 *knj_ram = (UINT16 *)memory_region(space->machine, "kanji"); |
| 109 | 110 | UINT32 knj_offset; |
| 110 | 111 | |
| 111 | | knj_offset = offset + (((bank_reg & 0x100) >> 8)*0x40000); |
| 112 | knj_offset = ((offset) + (((bank_reg & 0x100) >> 8)*0x20000)); |
| 112 | 113 | |
| 113 | | if(knj_offset >= 0x50000 && knj_offset <= 0x53fff) |
| 114 | if(knj_offset >= 0x50000/2 && knj_offset <= 0x53fff/2) // TODO: there's an area that can be write protected |
| 115 | { |
| 114 | 116 | COMBINE_DATA(&knj_ram[knj_offset]); |
| 117 | gfx_element_mark_dirty(space->machine->gfx[0], (knj_offset * 2) / 8); |
| 118 | gfx_element_mark_dirty(space->machine->gfx[1], (knj_offset * 2) / 32); |
| 119 | } |
| 115 | 120 | } |
| 116 | 121 | break; |
| 117 | 122 | case 0xc: // Dictionary ROM |
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| 148 | 153 | |
| 149 | 154 | static WRITE8_HANDLER( idp_command_w ) |
| 150 | 155 | { |
| 151 | | // ... |
| 156 | switch(data) |
| 157 | { |
| 158 | case 0x10: printf("Unemulated IDP SYNC cmd set\n"); break; |
| 159 | case 0x12: printf("Unemulated IDP DSPON cmd set\n"); break; |
| 160 | case 0x13: printf("Unemulated IDP DSPOFF cmd set\n"); break; |
| 161 | case 0x14: printf("Unemulated IDP DSPDEF cmd set\n"); break; |
| 162 | case 0x15: printf("Unemulated IDP CURDEF cmd set\n"); break; |
| 163 | case 0x16: printf("Unemulated IDP ACTSCR cmd set\n"); break; |
| 164 | case 0x1e: printf("Unemulated IDP CURS cmd set\n"); break; |
| 165 | case 0x8c: printf("Unemulated IDP EMUL cmd set\n"); break; |
| 166 | case 0x88: printf("Unemulated IDP EXIT cmd set\n"); break; |
| 167 | case 0x82: printf("Unemulated IDP SPRON cmd set\n"); break; |
| 168 | case 0x83: printf("Unemulated IDP SPROFF cmd set\n"); break; |
| 169 | case 0x85: printf("Unemulated IDP SPRSW cmd set\n"); break; |
| 170 | case 0x81: printf("Unemulated IDP SPROV cmd set\n"); break; |
| 171 | |
| 172 | default: printf("Unknown IDP %02x cmd set\n",data); break; |
| 173 | } |
| 152 | 174 | } |
| 153 | 175 | |
| 154 | 176 | static WRITE8_HANDLER( idp_param_w ) |
| 155 | 177 | { |
| 156 | | // ... |
| 178 | printf("%02x\n",data); |
| 157 | 179 | } |
| 158 | 180 | |
| 159 | 181 | static WRITE16_HANDLER( palette_ram_w ) |
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| 219 | 241 | return 0xff; // TODO |
| 220 | 242 | } |
| 221 | 243 | |
| 244 | static WRITE16_HANDLER( backupram_wp_1_w ) |
| 245 | { |
| 246 | backupram_wp = 1; |
| 247 | } |
| 248 | |
| 249 | static WRITE16_HANDLER( backupram_wp_0_w ) |
| 250 | { |
| 251 | backupram_wp = 0; |
| 252 | } |
| 253 | |
| 222 | 254 | static ADDRESS_MAP_START( pc88va_io_map, ADDRESS_SPACE_IO, 16 ) |
| 223 | 255 | AM_RANGE(0x0000, 0x000f) AM_READ8(key_r,0xffff) // Keyboard ROW reading |
| 224 | 256 | // AM_RANGE(0x0010, 0x0010) Printer / Calendar Clock Interface |
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| 271 | 303 | // AM_RANGE(0x0184, 0x018b) IRQ Controller |
| 272 | 304 | // AM_RANGE(0x0190, 0x0191) System Port 5 |
| 273 | 305 | // AM_RANGE(0x0196, 0x0197) Keyboard sub CPU command port |
| 274 | | // AM_RANGE(0x0198, 0x019b) Memory switch write inhibit/permission |
| 306 | AM_RANGE(0x0198, 0x0199) AM_WRITE(backupram_wp_1_w) //Backup RAM write inhibit |
| 307 | AM_RANGE(0x019a, 0x019b) AM_WRITE(backupram_wp_0_w) //Backup RAM write permission |
| 275 | 308 | // AM_RANGE(0x01a0, 0x01a7) TCU (timer counter unit) |
| 276 | 309 | // AM_RANGE(0x01a8, 0x01a9) General-purpose timer 3 control port |
| 277 | 310 | // AM_RANGE(0x01b0, 0x01bb) FDC related (765) |
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| 311 | 344 | memory_set_bankptr(machine, "rom00_bank", &ROM00[0x00000]); |
| 312 | 345 | |
| 313 | 346 | bank_reg = 0x4100; |
| 347 | backupram_wp = 1; |
| 314 | 348 | } |
| 315 | 349 | |
| 316 | 350 | static const gfx_layout pc88va_chars_8x8 = |