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r9153 Friday 17th September, 2010 at 07:02:04 UTC by Miodrag Milanović
Sync with MAME, some drivers commented (pcw16, avigo and gba)

[src/emu]	devintrf.c devintrf.h timer.c timer.h
[src/emu/machine]	6522via.c 6522via.h 8257dma.c 8257dma.h intelfsh.c intelfsh.h mc146818.c mc146818.h
[src/mess]	mess.mak messdriv.c
[src/mess/drivers]	bebox.c pcw16.c
[src/mess/includes]	bebox.h
[src/mess/machine]	bebox.c

src/emu/devintrf.c

r9152	r9153
873	873	//  fires
874	874	//-------------------------------------------------
875	875
876		void device_t::device_timer(emu_timer &timer, int param, void *ptr)
	876	void device_t::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
877	877	{
878	878	// do nothing by default
879	879	}

src/emu/devintrf.h

r9152	r9153
137	137	typedef device_config *(*device_type)(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock);
138	138
139	139
	140	// timer IDs for devices
	141	typedef UINT32 device_timer_id;
	142
	143
140	144	// read/write types for I/O lines (similar to read/write handlers but no offset)
141	145	typedef int (*read_line_device_func)(device_t *device);
142	146	typedef void (*write_line_device_func)(device_t *device, int state);
r9152	r9153
425	429	void set_clock_scale(double clockscale);
426	430	attotime clocks_to_attotime(UINT64 clocks) const;
427	431	UINT64 attotime_to_clocks(attotime duration) const;
428		void timer_fired(emu_timer &timer, int param, void *ptr) { device_timer(timer, param, ptr); }
	432	void timer_fired(emu_timer &timer, device_timer_id id, int param, void *ptr) { device_timer(timer, id, param, ptr); }
429	433
430	434	// debugging
431	435	device_debug *debug() const { return m_debug; }
r9152	r9153
460	464	virtual void device_post_load();
461	465	virtual void device_clock_changed();
462	466	virtual void device_debug_setup();
463		virtual void device_timer(emu_timer &timer, int param, void *ptr);
	467	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
464	468
465	469	//------------------- end derived class overrides
466	470

src/emu/machine/mc146818.h

r9152	r9153
82	82	protected:
83	83	// device-level overrides
84	84	virtual void device_start();
85		virtual void device_timer(emu_timer &timer, int param, void *ptr);
	85	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
86	86
87	87	// device_mc146818_interface overrides
88	88	virtual void nvram_default();

src/emu/machine/6522via.c

r9152	r9153
218	218	m_t2ll = 0xff; /* taken from vice */
219	219	m_t2lh = 0xff;
220	220	m_time2 = m_time1 = timer_get_time(&m_machine);
221		m_t1 = device_timer_alloc(*this);
222		m_t2 = device_timer_alloc(*this);
223		m_shift_timer = device_timer_alloc(*this);
	221	m_t1 = device_timer_alloc(*this, TIMER_T1);
	222	m_t2 = device_timer_alloc(*this, TIMER_T2);
	223	m_shift_timer = device_timer_alloc(*this, TIMER_SHIFT);
224	224
225	225	/* Default clock is from CPU1 */
226	226	if (clock() == 0)
r9152	r9153
415	415	}
416	416
417	417
418		void via6522_device::device_timer(emu_timer &timer, int param, void *ptr)
	418	void via6522_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
419	419	{
420		// shift timer
421		if (&timer == m_shift_timer)
422		shift();
423
424		// t1 timeout
425		else if (&timer == m_t1)
	420	switch (id)
426	421	{
427		if (T1_CONTINUOUS (m_acr))
428		{
429		if (T1_SET_PB7(m_acr))
430		{
431		m_out_b ^= 0x80;
432		}
433		timer_adjust_oneshot(m_t1, cycles_to_time(TIMER1_VALUE + IFR_DELAY), 0);
434		}
435		else
436		{
437		if (T1_SET_PB7(m_acr))
438		{
439		m_out_b |= 0x80;
440		}
441		m_t1_active = 0;
442		m_time1 = timer_get_time(&m_machine);
443		}
444		if (m_ddr_b)
445		{
446		UINT8 write_data = (m_out_b & m_ddr_b) | (m_ddr_b ^ 0xff);
447		devcb_call_write8(&m_out_b_func, 0, write_data);
448		}
	422	// shift timer
	423	case TIMER_SHIFT:
	424	shift();
	425	break;
	426
	427	// t1 timeout
	428	case TIMER_T1:
	429	if (T1_CONTINUOUS (m_acr))
	430	{
	431	if (T1_SET_PB7(m_acr))
	432	{
	433	m_out_b ^= 0x80;
	434	}
	435	timer_adjust_oneshot(m_t1, cycles_to_time(TIMER1_VALUE + IFR_DELAY), 0);
	436	}
	437	else
	438	{
	439	if (T1_SET_PB7(m_acr))
	440	{
	441	m_out_b |= 0x80;
	442	}
	443	m_t1_active = 0;
	444	m_time1 = timer_get_time(&m_machine);
	445	}
	446	if (m_ddr_b)
	447	{
	448	UINT8 write_data = (m_out_b & m_ddr_b) | (m_ddr_b ^ 0xff);
	449	devcb_call_write8(&m_out_b_func, 0, write_data);
	450	}
449	451
450		if (!(m_ifr & INT_T1))
451		{
452		set_int(INT_T1);
453		}
454		}
455
456		// t2 timeout
457		else if (&timer == m_t2)
458		{
459		m_t2_active = 0;
460		m_time2 = timer_get_time(&m_machine);
	452	if (!(m_ifr & INT_T1))
	453	{
	454	set_int(INT_T1);
	455	}
	456	break;
	457
	458	// t2 timeout
	459	case TIMER_T2:
	460	m_t2_active = 0;
	461	m_time2 = timer_get_time(&m_machine);
461	462
462		if (!(m_ifr & INT_T2))
463		{
464		set_int(INT_T2);
465		}
	463	if (!(m_ifr & INT_T2))
	464	{
	465	set_int(INT_T2);
	466	}
	467	break;
466	468	}
467	469	}
468	470

src/emu/machine/6522via.h

r9152	r9153
133	133	// device-level overrides
134	134	virtual void device_start();
135	135	virtual void device_reset();
136		virtual void device_timer(emu_timer &timer, int param, void *ptr);
	136	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
137	137
138	138	private:
	139	static const device_timer_id TIMER_SHIFT = 0;
	140	static const device_timer_id TIMER_T1 = 1;
	141	static const device_timer_id TIMER_T2 = 2;
	142
139	143	attotime cycles_to_time(int c);
140	144	UINT32 time_to_cycles(attotime t);
141	145	UINT16 get_counter1_value();

src/emu/machine/8257dma.c

r9152	r9153
101	101
102	102	i8257_device::i8257_device(running_machine &_machine, const i8257_device_config &config)
103	103	: device_t(_machine, config),
	104	m_mode(0),
	105	m_rr(0),
	106	m_msb(0),
	107	m_drq(0),
	108	m_status(0x0f),
104	109	m_config(config)
105	110	{
106
	111	memset(m_registers, 0, sizeof(m_registers));
	112	memset(m_address, 0, sizeof(m_address));
	113	memset(m_count, 0, sizeof(m_count));
	114	memset(m_rwmode, 0, sizeof(m_rwmode));
107	115	}
108	116
109	117	//-------------------------------------------------
r9152	r9153
129	137	}
130	138
131	139	/* set initial values */
132		m_status = 0x0f;
133		m_timer = timer_alloc(&m_machine, i8257_timerproc_callback, (void *) this);
134		m_msbflip_timer = timer_alloc(&m_machine, i8257_msbflip_timerproc_callback, (void *) this);
	140	m_timer = device_timer_alloc(*this, TIMER_OPERATION);
	141	m_msbflip_timer = device_timer_alloc(*this, TIMER_MSBFLIP);
135	142
136	143	/* register for state saving */
137	144	state_save_register_device_item_array(this, 0, m_address);
r9152	r9153
243	250	}
244	251
245	252
246		TIMER_CALLBACK( i8257_device::i8257_timerproc_callback )
	253	void i8257_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
247	254	{
248		reinterpret_cast<i8257_device*>(ptr)->i8257_timerproc();
249		}
250
251		void i8257_device::i8257_timerproc()
252		{
253		int i, channel = 0, rr;
254		int done;
255
256		rr = DMA_MODE_ROTPRIO(m_mode) ? m_rr : 0;
257		for (i = 0; i < I8257_NUM_CHANNELS; i++)
	255	switch (id)
258	256	{
259		channel = (i + rr) % I8257_NUM_CHANNELS;
260		if ((m_status & (1 << channel)) == 0)
	257	case TIMER_OPERATION:
261	258	{
262		if (m_mode & m_drq & (1 << channel))
	259	int i, channel = 0, rr;
	260	int done;
	261
	262	rr = DMA_MODE_ROTPRIO(m_mode) ? m_rr : 0;
	263	for (i = 0; i < I8257_NUM_CHANNELS; i++)
263	264	{
264		break;
	265	channel = (i + rr) % I8257_NUM_CHANNELS;
	266	if ((m_status & (1 << channel)) == 0)
	267	{
	268	if (m_mode & m_drq & (1 << channel))
	269	{
	270	break;
	271	}
	272	}
265	273	}
266		}
267		}
268		done = i8257_do_operation(channel);
	274	done = i8257_do_operation(channel);
269	275
270		m_rr = (channel + 1) & 0x03;
	276	m_rr = (channel + 1) & 0x03;
271	277
272		if (done)
273		{
274		m_drq &= ~(0x01 << channel);
275		i8257_update_status();
276		if (!(DMA_MODE_AUTOLOAD(m_mode) && channel==2))
	278	if (done)
	279	{
	280	m_drq &= ~(0x01 << channel);
	281	i8257_update_status();
	282	if (!(DMA_MODE_AUTOLOAD(m_mode) && channel==2))
	283	{
	284	if (DMA_MODE_TCSTOP(m_mode))
	285	{
	286	m_mode &= ~(0x01 << channel);
	287	}
	288	}
	289	}
	290	break;
	291	}
	292
	293	case TIMER_MSBFLIP:
	294	m_msb ^= 1;
	295	break;
	296
	297	case TIMER_DRQ_SYNC:
277	298	{
278		if (DMA_MODE_TCSTOP(m_mode))
	299	int channel = param >> 1;
	300	int state = param & 0x01;
	301
	302	/* normalize state */
	303	if (state)
279	304	{
280		m_mode &= ~(0x01 << channel);
	305	m_drq |= 0x01 << channel;
	306	m_address[channel] =  m_registers[channel * 2];
	307	m_count[channel] =  m_registers[channel * 2 + 1] & 0x3FFF;
	308	m_rwmode[channel] =  m_registers[channel * 2 + 1] >> 14;
	309	/* clear channel TC */
	310	m_status &= ~(0x01 << channel);
281	311	}
	312	else
	313	m_drq &= ~(0x01 << channel);
	314
	315	i8257_update_status();
	316	break;
282	317	}
283	318	}
284	319	}
285	320
286	321
287		TIMER_CALLBACK( i8257_device::i8257_msbflip_timerproc_callback )
288		{
289		reinterpret_cast<i8257_device*>(ptr)->i8257_msbflip_timerproc();
290		}
291
292		void i8257_device::i8257_msbflip_timerproc()
293		{
294		m_msb ^= 1;
295		}
296
297
298	322	void i8257_device::i8257_update_status()
299	323	{
300	324	UINT16 pending_transfer;
r9152	r9153
421	445	}
422	446
423	447
424		TIMER_CALLBACK( i8257_device::i8257_drq_write_callback )
425		{
426		reinterpret_cast<i8257_device*>(ptr)->i8257_drq_write_timerproc(param);
427		}
428
429		void i8257_device::i8257_drq_write_timerproc(INT32 param)
430		{
431		int channel = param >> 1;
432		int state = param & 0x01;
433
434		/* normalize state */
435		if (state)
436		{
437		m_drq |= 0x01 << channel;
438		m_address[channel] =  m_registers[channel * 2];
439		m_count[channel] =  m_registers[channel * 2 + 1] & 0x3FFF;
440		m_rwmode[channel] =  m_registers[channel * 2 + 1] >> 14;
441		/* clear channel TC */
442		m_status &= ~(0x01 << channel);
443		}
444		else
445		m_drq &= ~(0x01 << channel);
446
447		i8257_update_status();
448		}
449
450	448	void i8257_device::i8257_drq_w(int channel, int state)
451	449	{
452	450	int param = (channel << 1) | (state ? 1 : 0);
453	451
454		timer_call_after_resynch(&m_machine, (void *)this, param, i8257_drq_write_callback);
	452	device_timer_call_after_resynch(*this, TIMER_DRQ_SYNC, param);
455	453	}
456	454
457	455	WRITE_LINE_DEVICE_HANDLER( i8257_hlda_w ) { }

src/emu/machine/8257dma.h

r9152	r9153
117	117	/* data request */
118	118	void i8257_drq_w(int channel, int state);
119	119
120		void i8257_timerproc();
121		void i8257_msbflip_timerproc();
122		void i8257_drq_write_timerproc(INT32 param);
123
124	120	protected:
125	121	// device-level overrides
126	122	virtual void device_start();
127	123	virtual void device_reset();
128		virtual void device_post_load() { }
129		virtual void device_clock_changed() { }
	124	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
130	125
131		static TIMER_CALLBACK( i8257_timerproc_callback );
132		static TIMER_CALLBACK( i8257_msbflip_timerproc_callback );
133		static TIMER_CALLBACK( i8257_drq_write_callback );
134
135	126	private:
	127	static const device_timer_id TIMER_OPERATION = 0;
	128	static const device_timer_id TIMER_MSBFLIP = 1;
	129	static const device_timer_id TIMER_DRQ_SYNC = 2;
136	130
137	131	int i8257_do_operation(int channel);
138	132	void i8257_update_status();

src/emu/machine/intelfsh.c

r9152	r9153
14	14	#include "emu.h"
15	15	#include "intelfsh.h"
16	16
	17
	18	//**************************************************************************
	19	//  CONSTANTS
	20	//**************************************************************************
	21
17	22	enum
18	23	{
19	24	FM_NORMAL,   // normal read/write
r9152	r9153
32	37	FM_BYTEPROGRAM,
33	38	};
34	39
35		struct flash_chip
36		{
37		int type;
38		int size;
39		int bits;
40		int status;
41		int erase_sector;
42		int sector_is_4k;
43		INT32 flash_mode;
44		INT32 flash_master_lock;
45		int device_id;
46		int maker_id;
47		emu_timer *timer;
48		void *flash_memory;
49		};
50	40
51		static struct flash_chip chips[FLASH_CHIPS_MAX];
52	41
53		static TIMER_CALLBACK( erase_finished )
54		{
55		struct flash_chip *c = (struct flash_chip *)ptr;
	42	//**************************************************************************
	43	//  DEVICE DEFINITIONS
	44	//**************************************************************************
56	45
57		switch( c->flash_mode )
58		{
59		case FM_READSTATUS:
60		c->status = 0x80;
61		break;
	46	// 8-bit variants
	47	DEFINE_TRIVIAL_DERIVED_DEVICE(intel_28f016s5_device_config, intelfsh8_device_config, intel_28f016s5_device, intelfsh8_device, "Sharp LH28F400 Flash", intelfsh_device_config::FLASH_SHARP_LH28F400)
	48	DEFINE_TRIVIAL_DERIVED_DEVICE(fujitsu_29f016a_device_config, intelfsh8_device_config, fujitsu_29f016a_device, intelfsh8_device, "Fujitsu 29F016A Flash", intelfsh_device_config::FLASH_FUJITSU_29F016A)
	49	DEFINE_TRIVIAL_DERIVED_DEVICE(sharp_lh28f016s_device_config, intelfsh8_device_config, sharp_lh28f016s_device, intelfsh8_device, "Sharp LH28F016S Flash", intelfsh_device_config::FLASH_SHARP_LH28F016S)
	50	DEFINE_TRIVIAL_DERIVED_DEVICE(intel_e28f008sa_device_config, intelfsh8_device_config, intel_e28f008sa_device, intelfsh8_device, "Intel E28F008SA Flash", intelfsh_device_config::FLASH_INTEL_E28F008SA)
	51	DEFINE_TRIVIAL_DERIVED_DEVICE(macronix_29l001mc_device_config, intelfsh8_device_config, macronix_29l001mc_device, intelfsh8_device, "Macronix 29L001MC Flash", intelfsh_device_config::FLASH_MACRONIX_29L001MC)
	52	DEFINE_TRIVIAL_DERIVED_DEVICE(panasonic_mn63f805mnp_device_config, intelfsh8_device_config, panasonic_mn63f805mnp_device, intelfsh8_device, "Panasonic MN63F805MNP Flash", intelfsh_device_config::FLASH_PANASONIC_MN63F805MNP)
	53	DEFINE_TRIVIAL_DERIVED_DEVICE(sanyo_le26fv10n1ts_device_config, intelfsh8_device_config, sanyo_le26fv10n1ts_device, intelfsh8_device, "Sanyo LE26FV10N1TS Flash", intelfsh_device_config::FLASH_SANYO_LE26FV10N1TS)
62	54
63		case FM_ERASEAMD4:
64		c->flash_mode = FM_NORMAL;
65		break;
66		}
67		}
	55	const device_type INTEL_28F016S5 = intel_28f016s5_device_config::static_alloc_device_config;
	56	const device_type SHARP_LH28F016S = sharp_lh28f016s_device_config::static_alloc_device_config;
	57	const device_type FUJITSU_29F016A = fujitsu_29f016a_device_config::static_alloc_device_config;
	58	const device_type INTEL_E28F008SA = intel_e28f008sa_device_config::static_alloc_device_config;
	59	const device_type MACRONIX_29L001MC = macronix_29l001mc_device_config::static_alloc_device_config;
	60	const device_type PANASONIC_MN63F805MNP = panasonic_mn63f805mnp_device_config::static_alloc_device_config;
	61	const device_type SANYO_LE26FV10N1TS = sanyo_le26fv10n1ts_device_config::static_alloc_device_config;
68	62
69		void* intelflash_getmemptr(int chip)
70		{
71		struct flash_chip *c;
72		if( chip >= FLASH_CHIPS_MAX )
73		{
74		logerror( "intelflash_init: invalid chip %d\n", chip );
75		return 0;
76		}
77		c = &chips[ chip ];
78	63
79		return c->flash_memory;
80		}
	64	// 16-bit variants
	65	DEFINE_TRIVIAL_DERIVED_DEVICE(sharp_lh28f400_device_config, intelfsh16_device_config, sharp_lh28f400_device, intelfsh16_device, "Sharp LH28F400 Flash", intelfsh_device_config::FLASH_SHARP_LH28F400)
	66	DEFINE_TRIVIAL_DERIVED_DEVICE(intel_te28f160_device_config, intelfsh16_device_config, intel_te28f160_device, intelfsh16_device, "Intel TE28F160 Flash", intelfsh_device_config::FLASH_INTEL_TE28F160)
	67	DEFINE_TRIVIAL_DERIVED_DEVICE(intel_e28f400_device_config, intelfsh16_device_config, intel_e28f400_device, intelfsh16_device, "Intel E28F400 Flash", intelfsh_device_config::FLASH_INTEL_E28F400)
	68	DEFINE_TRIVIAL_DERIVED_DEVICE(sharp_unk128mbit_device_config, intelfsh16_device_config, sharp_unk128mbit_device, intelfsh16_device, "Sharp Unknown 128Mb Flash", intelfsh_device_config::FLASH_SHARP_UNK128MBIT)
81	69
82		void intelflash_init(running_machine *machine, int chip, int type, void *data)
	70	const device_type SHARP_LH28F400 = sharp_lh28f400_device_config::static_alloc_device_config;
	71	const device_type INTEL_TE28F160 = intel_te28f160_device_config::static_alloc_device_config;
	72	const device_type INTEL_E28F400 = intel_e28f400_device_config::static_alloc_device_config;
	73	const device_type SHARP_UNK128MBIT = sharp_unk128mbit_device_config::static_alloc_device_config;
	74
	75
	76
	77	//**************************************************************************
	78	//  GLOBAL VARIABLES
	79	//**************************************************************************
	80
	81	static ADDRESS_MAP_START( memory_map8_512Kb, ADDRESS_SPACE_PROGRAM, 8 )
	82	AM_RANGE(0x00000, 0x00ffff) AM_RAM
	83	ADDRESS_MAP_END
	84
	85	static ADDRESS_MAP_START( memory_map8_1Mb, ADDRESS_SPACE_PROGRAM, 8 )
	86	AM_RANGE(0x00000, 0x01ffff) AM_RAM
	87	ADDRESS_MAP_END
	88
	89	static ADDRESS_MAP_START( memory_map8_8Mb, ADDRESS_SPACE_PROGRAM, 8 )
	90	AM_RANGE(0x00000, 0x0fffff) AM_RAM
	91	ADDRESS_MAP_END
	92
	93	static ADDRESS_MAP_START( memory_map8_16Mb, ADDRESS_SPACE_PROGRAM, 8 )
	94	AM_RANGE(0x00000, 0x1fffff) AM_RAM
	95	ADDRESS_MAP_END
	96
	97
	98	static ADDRESS_MAP_START( memory_map16_4Mb, ADDRESS_SPACE_PROGRAM, 16 )
	99	AM_RANGE(0x00000, 0x07ffff) AM_RAM
	100	ADDRESS_MAP_END
	101
	102	static ADDRESS_MAP_START( memory_map16_16Mb, ADDRESS_SPACE_PROGRAM, 16 )
	103	AM_RANGE(0x00000, 0x1fffff) AM_RAM
	104	ADDRESS_MAP_END
	105
	106	static ADDRESS_MAP_START( memory_map16_64Mb, ADDRESS_SPACE_PROGRAM, 16 )
	107	AM_RANGE(0x00000, 0x7fffff) AM_RAM
	108	ADDRESS_MAP_END
	109
	110
	111
	112	//**************************************************************************
	113	//  DEVICE CONFIGURATION
	114	//**************************************************************************
	115
	116	//-------------------------------------------------
	117	//  intelfsh_device_config - constructor
	118	//-------------------------------------------------
	119
	120	intelfsh_device_config::intelfsh_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant)
	121	: device_config(mconfig, type, name, tag, owner, clock),
	122	device_config_memory_interface(mconfig, *this),
	123	device_config_nvram_interface(mconfig, *this),
	124	m_type(variant),
	125	m_size(0),
	126	m_bits(8),
	127	m_device_id(0),
	128	m_maker_id(0),
	129	m_sector_is_4k(false)
83	130	{
84		struct flash_chip *c;
85		if( chip >= FLASH_CHIPS_MAX )
86		{
87		logerror( "intelflash_init: invalid chip %d\n", chip );
88		return;
89		}
90		c = &chips[ chip ];
	131	address_map_constructor map = NULL;
91	132
92		c->type = type;
93		c->sector_is_4k = 0;
94		switch( c->type )
	133	switch( variant )
95	134	{
96	135	case FLASH_INTEL_28F016S5:
97	136	case FLASH_SHARP_LH28F016S:
98		c->bits = 8;
99		c->size = 0x200000;
100		c->maker_id = 0x89;
101		c->device_id = 0xaa;
	137	m_bits = 8;
	138	m_size = 0x200000;
	139	m_maker_id = 0x89;
	140	m_device_id = 0xaa;
	141	map = ADDRESS_MAP_NAME( memory_map8_16Mb );
102	142	break;
103	143	case FLASH_SHARP_LH28F400:
104	144	case FLASH_INTEL_E28F400:
105		c->bits = 16;
106		c->size = 0x80000;
107		c->maker_id = 0xb0;
108		c->device_id = 0xed;
	145	m_bits = 16;
	146	m_size = 0x80000;
	147	m_maker_id = 0xb0;
	148	m_device_id = 0xed;
	149	map = ADDRESS_MAP_NAME( memory_map16_4Mb );
109	150	break;
110	151	case FLASH_FUJITSU_29F016A:
111		c->bits = 8;
112		c->size = 0x200000;
113		c->maker_id = 0x04;
114		c->device_id = 0xad;
	152	m_bits = 8;
	153	m_size = 0x200000;
	154	m_maker_id = 0x04;
	155	m_device_id = 0xad;
	156	map = ADDRESS_MAP_NAME( memory_map8_16Mb );
115	157	break;
116	158	case FLASH_INTEL_E28F008SA:
117		c->bits = 8;
118		c->size = 0x100000;
119		c->maker_id = 0x89;
120		c->device_id = 0xa2;
	159	m_bits = 8;
	160	m_size = 0x100000;
	161	m_maker_id = 0x89;
	162	m_device_id = 0xa2;
	163	map = ADDRESS_MAP_NAME( memory_map8_8Mb );
121	164	break;
122	165	case FLASH_INTEL_TE28F160:
123		c->bits = 16;
124		c->size = 0x200000;
125		c->maker_id = 0xb0;
126		c->device_id = 0xd0;
	166	m_bits = 16;
	167	m_size = 0x200000;
	168	m_maker_id = 0xb0;
	169	m_device_id = 0xd0;
	170	map = ADDRESS_MAP_NAME( memory_map16_16Mb );
127	171	break;
128	172	case FLASH_SHARP_UNK128MBIT:
129		c->bits = 16;
130		c->size = 0x800000;
131		c->maker_id = 0xb0;
132		c->device_id = 0xb0;
	173	m_bits = 16;
	174	m_size = 0x800000;
	175	m_maker_id = 0xb0;
	176	m_device_id = 0xb0;
	177	map = ADDRESS_MAP_NAME( memory_map16_64Mb );
133	178	break;
134	179	case FLASH_MACRONIX_29L001MC:
135		c->bits = 8;
136		c->size = 0x20000;
137		c->maker_id = 0xc2;
138		c->device_id = 0x51;
	180	m_bits = 8;
	181	m_size = 0x20000;
	182	m_maker_id = 0xc2;
	183	m_device_id = 0x51;
	184	map = ADDRESS_MAP_NAME( memory_map8_1Mb );
139	185	break;
140
141	186	case FLASH_PANASONIC_MN63F805MNP:
142		c->bits = 8;
143		c->size = 0x10000;
144		c->maker_id = 0x32;
145		c->device_id = 0x1b;
146		c->sector_is_4k = 1;
	187	m_bits = 8;
	188	m_size = 0x10000;
	189	m_maker_id = 0x32;
	190	m_device_id = 0x1b;
	191	m_sector_is_4k = true;
	192	map = ADDRESS_MAP_NAME( memory_map8_512Kb );
147	193	break;
148
149	194	case FLASH_SANYO_LE26FV10N1TS:
150		c->bits = 8;
151		c->size = 0x20000;
152		c->maker_id = 0x62;
153		c->device_id = 0x13;
154		c->sector_is_4k = 1;
	195	m_bits = 8;
	196	m_size = 0x20000;
	197	m_maker_id = 0x62;
	198	m_device_id = 0x13;
	199	m_sector_is_4k = true;
	200	map = ADDRESS_MAP_NAME( memory_map8_1Mb );
155	201	break;
156	202	}
157		if( data == NULL )
	203
	204	int addrbits;
	205	for (addrbits = 24; addrbits > 0; addrbits--)
	206	if ((m_size & (1 << addrbits)) != 0)
	207	break;
	208
	209	m_space_config = address_space_config("flash", ENDIANNESS_BIG, m_bits, addrbits, 0, map);
	210	}
	211
	212	intelfsh8_device_config::intelfsh8_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant)
	213	: intelfsh_device_config(mconfig, type, name, tag, owner, clock, variant)
	214	{
	215	}
	216
	217	intelfsh16_device_config::intelfsh16_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant)
	218	: intelfsh_device_config(mconfig, type, name, tag, owner, clock, variant)
	219	{
	220	}
	221
	222
	223	//-------------------------------------------------
	224	//  memory_space_config - return a description of
	225	//  any address spaces owned by this device
	226	//-------------------------------------------------
	227
	228	const address_space_config *intelfsh_device_config::memory_space_config(int spacenum) const
	229	{
	230	return (spacenum == 0) ? &m_space_config : NULL;
	231	}
	232
	233
	234
	235	//**************************************************************************
	236	//  LIVE DEVICE
	237	//**************************************************************************
	238
	239	//-------------------------------------------------
	240	//  intelfsh_device - constructor
	241	//-------------------------------------------------
	242
	243	intelfsh_device::intelfsh_device(running_machine &_machine, const intelfsh_device_config &config)
	244	: device_t(_machine, config),
	245	device_memory_interface(_machine, config, *this),
	246	device_nvram_interface(_machine, config, *this),
	247	m_config(config),
	248	m_status(0x80),
	249	m_erase_sector(0),
	250	m_flash_mode(FM_NORMAL),
	251	m_flash_master_lock(false),
	252	m_timer(NULL)
	253	{
	254	}
	255
	256	intelfsh8_device::intelfsh8_device(running_machine &_machine, const intelfsh_device_config &config)
	257	: intelfsh_device(_machine, config) { }
	258
	259	intelfsh16_device::intelfsh16_device(running_machine &_machine, const intelfsh_device_config &config)
	260	: intelfsh_device(_machine, config) { }
	261
	262
	263	//-------------------------------------------------
	264	//  device_start - device-specific startup
	265	//-------------------------------------------------
	266
	267	void intelfsh_device::device_start()
	268	{
	269	m_timer = device_timer_alloc(*this);
	270
	271	state_save_register_device_item( this, 0, m_status );
	272	state_save_register_device_item( this, 0, m_flash_mode );
	273	state_save_register_device_item( this, 0, m_flash_master_lock );
	274	}
	275
	276
	277	//-------------------------------------------------
	278	//  device_timer - handler timer events
	279	//-------------------------------------------------
	280
	281	void intelfsh_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
	282	{
	283	switch( m_flash_mode )
158	284	{
159		data = auto_alloc_array( machine, UINT8, c->size );
160		memset( data, 0xff, c->size );
	285	case FM_READSTATUS:
	286	m_status = 0x80;
	287	break;
	288
	289	case FM_ERASEAMD4:
	290	m_flash_mode = FM_NORMAL;
	291	break;
161	292	}
	293	}
162	294
163		c->status = 0x80;
164		c->flash_mode = FM_NORMAL;
165		c->flash_master_lock = 0;
166		c->timer = timer_alloc(machine, erase_finished, c);
167		c->flash_memory = data;
168	295
169		state_save_register_item( machine, "intelfsh", NULL, chip, c->status );
170		state_save_register_item( machine, "intelfsh", NULL, chip, c->flash_mode );
171		state_save_register_item( machine, "intelfsh", NULL, chip, c->flash_master_lock );
172		state_save_register_memory( machine, "intelfsh", NULL, chip, "flash_memory", c->flash_memory, c->bits/8, c->size / (c->bits/8), __FILE__, __LINE__ );
173		}
	296	//-------------------------------------------------
	297	//  nvram_default - called to initialize NVRAM to
	298	//  its default state
	299	//-------------------------------------------------
174	300
175		UINT32 intelflash_read(int chip, UINT32 address)
	301	void intelfsh_device::nvram_default()
176	302	{
177		UINT32 data = 0;
178		struct flash_chip *c;
179		if( chip >= FLASH_CHIPS_MAX )
	303	// region always wins
	304	if (m_region != NULL)
180	305	{
181		logerror( "intelflash_read: invalid chip %d\n", chip );
182		return 0;
	306	UINT32 bytes = m_region->bytes();
	307	if (bytes > m_config.m_size)
	308	bytes = m_config.m_size;
	309
	310	if (m_config.m_bits == 8)
	311	{
	312	for (offs_t offs = 0; offs < bytes; offs++)
	313	m_addrspace[0]->write_byte(offs, m_region->u8(offs));
	314	}
	315	else
	316	{
	317	for (offs_t offs = 0; offs < bytes; offs += 2)
	318	m_addrspace[0]->write_word(offs, m_region->u16(offs / 2));
	319	}
	320	return;
183	321	}
184		c = &chips[ chip ];
185	322
186		switch( c->flash_mode )
	323	// otherwise, default to 0xff
	324	for (offs_t offs = 0; offs < m_config.m_size; offs++)
	325	m_addrspace[0]->write_byte(offs, 0xff);
	326	}
	327
	328
	329	//-------------------------------------------------
	330	//  nvram_read - called to read NVRAM from the
	331	//  .nv file
	332	//-------------------------------------------------
	333
	334	void intelfsh_device::nvram_read(mame_file &file)
	335	{
	336	UINT8 *buffer = global_alloc_array(UINT8, m_config.m_size);
	337	mame_fread(&file, buffer, m_config.m_size);
	338	for (int byte = 0; byte < m_config.m_size; byte++)
	339	m_addrspace[0]->write_byte(byte, buffer[byte]);
	340	global_free(buffer);
	341	}
	342
	343
	344	//-------------------------------------------------
	345	//  nvram_write - called to write NVRAM to the
	346	//  .nv file
	347	//-------------------------------------------------
	348
	349	void intelfsh_device::nvram_write(mame_file &file)
	350	{
	351	UINT8 *buffer = global_alloc_array(UINT8, m_config.m_size);
	352	for (int byte = 0; byte < m_config.m_size; byte++)
	353	buffer[byte] = m_addrspace[0]->read_byte(byte);
	354	mame_fwrite(&file, buffer, m_config.m_size);
	355	global_free(buffer);
	356	}
	357
	358
	359	//-------------------------------------------------
	360	//  read_full - generic read, called by the
	361	//  bit-width-specific readers
	362	//-------------------------------------------------
	363
	364	UINT32 intelfsh_device::read_full(UINT32 address)
	365	{
	366	UINT32 data = 0;
	367	switch( m_flash_mode )
187	368	{
188	369	default:
189	370	case FM_NORMAL:
190		switch( c->bits )
	371	switch( m_config.m_bits )
191	372	{
192	373	case 8:
193	374	{
194		UINT8 *flash_memory = (UINT8 *)c->flash_memory;
195		data = flash_memory[ address ];
	375	data = m_addrspace[0]->read_byte(address);
196	376	}
197	377	break;
198	378	case 16:
199	379	{
200		UINT16 *flash_memory = (UINT16 *)c->flash_memory;
201		data = flash_memory[ address ];
	380	data = m_addrspace[0]->read_word(address * 2);
202	381	}
203	382	break;
204	383	}
205	384	break;
206	385	case FM_READSTATUS:
207		data = c->status;
	386	data = m_status;
208	387	break;
209	388	case FM_READAMDID3:
210	389	switch (address)
211	390	{
212		case 0:   data = c->maker_id; break;
213		case 1: data = c->device_id; break;
	391	case 0:   data = m_config.m_maker_id; break;
	392	case 1: data = m_config.m_device_id; break;
214	393	case 2: data = 0; break;
215	394	}
216	395	break;
r9152	r9153
218	397	switch (address)
219	398	{
220	399	case 0:   // maker ID
221		data = c->maker_id;
	400	data = m_config.m_maker_id;
222	401	break;
223	402	case 1:   // chip ID
224		data = c->device_id;
	403	data = m_config.m_device_id;
225	404	break;
226	405	case 2:   // block lock config
227	406	data = 0; // we don't support this yet
228	407	break;
229	408	case 3: // master lock config
230		if (c->flash_master_lock)
	409	if (m_flash_master_lock)
231	410	{
232	411	data = 1;
233	412	}
r9152	r9153
240	419	break;
241	420	case FM_ERASEAMD4:
242	421	// reads outside of the erasing sector return normal data
243		if ((address < c->erase_sector) || (address >= c->erase_sector+(64*1024)))
	422	if ((address < m_erase_sector) || (address >= m_erase_sector+(64*1024)))
244	423	{
245		switch( c->bits )
	424	switch( m_config.m_bits )
246	425	{
247	426	case 8:
248	427	{
249		UINT8 *flash_memory = (UINT8 *)c->flash_memory;
250		data = flash_memory[ address ];
	428	data = m_addrspace[0]->read_byte(address);
251	429	}
252	430	break;
253	431	case 16:
254	432	{
255		UINT16 *flash_memory = (UINT16 *)c->flash_memory;
256		data = flash_memory[ address ];
	433	data = m_addrspace[0]->read_word(address * 2);
257	434	}
258	435	break;
259	436	}
260	437	}
261	438	else
262	439	{
263		c->status ^= ( 1 << 6 ) | ( 1 << 2 );
264		data = c->status;
	440	m_status ^= ( 1 << 6 ) | ( 1 << 2 );
	441	data = m_status;
265	442	}
266	443	break;
267	444	}
r9152	r9153
271	448	return data;
272	449	}
273	450
274		void intelflash_write(int chip, UINT32 address, UINT32 data)
	451
	452	//-------------------------------------------------
	453	//  write_full - generic write, called by the
	454	//  bit-width-specific writers
	455	//-------------------------------------------------
	456
	457	void intelfsh_device::write_full(UINT32 address, UINT32 data)
275	458	{
276		struct flash_chip *c;
277		if( chip >= FLASH_CHIPS_MAX )
278		{
279		logerror( "intelflash_write: invalid chip %d\n", chip );
280		return;
281		}
282		c = &chips[ chip ];
283
284	459	//  logerror( "intelflash_write( %d, %08x, %08x )\n", chip, address, data );
285	460
286		switch( c->flash_mode )
	461	switch( m_flash_mode )
287	462	{
288	463	case FM_NORMAL:
289	464	case FM_READSTATUS:
r9152	r9153
293	468	{
294	469	case 0xf0:
295	470	case 0xff:   // reset chip mode
296		c->flash_mode = FM_NORMAL;
	471	m_flash_mode = FM_NORMAL;
297	472	break;
298	473	case 0x90:   // read ID
299		c->flash_mode = FM_READID;
	474	m_flash_mode = FM_READID;
300	475	break;
301	476	case 0x40:
302	477	case 0x10:   // program
303		c->flash_mode = FM_WRITEPART1;
	478	m_flash_mode = FM_WRITEPART1;
304	479	break;
305	480	case 0x50:   // clear status reg
306		c->status = 0x80;
307		c->flash_mode = FM_READSTATUS;
	481	m_status = 0x80;
	482	m_flash_mode = FM_READSTATUS;
308	483	break;
309	484	case 0x20:   // block erase
310		c->flash_mode = FM_CLEARPART1;
	485	m_flash_mode = FM_CLEARPART1;
311	486	break;
312	487	case 0x60:   // set master lock
313		c->flash_mode = FM_SETMASTER;
	488	m_flash_mode = FM_SETMASTER;
314	489	break;
315	490	case 0x70:   // read status
316		c->flash_mode = FM_READSTATUS;
	491	m_flash_mode = FM_READSTATUS;
317	492	break;
318	493	case 0xaa:   // AMD ID select part 1
319	494	if( ( address & 0xfff ) == 0x555 )
320	495	{
321		c->flash_mode = FM_READAMDID1;
	496	m_flash_mode = FM_READAMDID1;
322	497	}
323	498	break;
324	499	default:
r9152	r9153
329	504	case FM_READAMDID1:
330	505	if( ( address & 0xffff ) == 0x2aa && ( data & 0xff ) == 0x55 )
331	506	{
332		c->flash_mode = FM_READAMDID2;
	507	m_flash_mode = FM_READAMDID2;
333	508	}
334	509	else if( ( address & 0xffff ) == 0x2aaa && ( data & 0xff ) == 0x55 )
335	510	{
336		c->flash_mode = FM_READAMDID2;
	511	m_flash_mode = FM_READAMDID2;
337	512	}
338	513	else
339	514	{
340	515	logerror( "unexpected %08x=%02x in FM_READAMDID1\n", address, data & 0xff );
341		c->flash_mode = FM_NORMAL;
	516	m_flash_mode = FM_NORMAL;
342	517	}
343	518	break;
344	519	case FM_READAMDID2:
345	520	if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0x90 )
346	521	{
347		c->flash_mode = FM_READAMDID3;
	522	m_flash_mode = FM_READAMDID3;
348	523	}
349	524	else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0x90 )
350	525	{
351		c->flash_mode = FM_READAMDID3;
	526	m_flash_mode = FM_READAMDID3;
352	527	}
353	528	else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0x80 )
354	529	{
355		c->flash_mode = FM_ERASEAMD1;
	530	m_flash_mode = FM_ERASEAMD1;
356	531	}
357	532	else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0x80 )
358	533	{
359		c->flash_mode = FM_ERASEAMD1;
	534	m_flash_mode = FM_ERASEAMD1;
360	535	}
361	536	else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0xa0 )
362	537	{
363		c->flash_mode = FM_BYTEPROGRAM;
	538	m_flash_mode = FM_BYTEPROGRAM;
364	539	}
365	540	else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0xa0 )
366	541	{
367		c->flash_mode = FM_BYTEPROGRAM;
	542	m_flash_mode = FM_BYTEPROGRAM;
368	543	}
369	544	else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0xf0 )
370	545	{
371		c->flash_mode = FM_NORMAL;
	546	m_flash_mode = FM_NORMAL;
372	547	}
373	548	else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0xf0 )
374	549	{
375		c->flash_mode = FM_NORMAL;
	550	m_flash_mode = FM_NORMAL;
376	551	}
377	552	else
378	553	{
379	554	logerror( "unexpected %08x=%02x in FM_READAMDID2\n", address, data & 0xff );
380		c->flash_mode = FM_NORMAL;
	555	m_flash_mode = FM_NORMAL;
381	556	}
382	557	break;
383	558	case FM_ERASEAMD1:
384	559	if( ( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0xaa )
385	560	{
386		c->flash_mode = FM_ERASEAMD2;
	561	m_flash_mode = FM_ERASEAMD2;
387	562	}
388	563	else
389	564	{
r9152	r9153
393	568	case FM_ERASEAMD2:
394	569	if( ( address & 0xffff ) == 0x2aa && ( data & 0xff ) == 0x55 )
395	570	{
396		c->flash_mode = FM_ERASEAMD3;
	571	m_flash_mode = FM_ERASEAMD3;
397	572	}
398	573	else if( ( address & 0xffff ) == 0x2aaa && ( data & 0xff ) == 0x55 )
399	574	{
400		c->flash_mode = FM_ERASEAMD3;
	575	m_flash_mode = FM_ERASEAMD3;
401	576	}
402	577	else
403	578	{
r9152	r9153
408	583	if( ( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0x10 )
409	584	{
410	585	// chip erase
411		memset( c->flash_memory, 0xff, c->size);
	586	for (offs_t offs = 0; offs < m_config.m_size; offs++)
	587	m_addrspace[0]->write_byte(offs, 0xff);
412	588
413		c->status = 1 << 3;
414		c->flash_mode = FM_ERASEAMD4;
	589	m_status = 1 << 3;
	590	m_flash_mode = FM_ERASEAMD4;
415	591
416		timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 17 ), 0 );
	592	timer_adjust_oneshot( m_timer, ATTOTIME_IN_SEC( 17 ), 0 );
417	593	}
418	594	else if( ( data & 0xff ) == 0x30 )
419	595	{
420	596	// sector erase
421	597	// clear the 4k/64k block containing the current address to all 0xffs
422		switch( c->bits )
	598	if (m_config.m_sector_is_4k)
423	599	{
424		case 8:
425		{
426		UINT8 *flash_memory = (UINT8 *)c->flash_memory;
427		if (c->sector_is_4k)
428		{
429		memset( &flash_memory[ address & ~0xfff ], 0xff, 4 * 1024 );
430		c->erase_sector = address & ~0xfff;
431		timer_adjust_oneshot( c->timer, ATTOTIME_IN_MSEC( 125 ), 0 );
432		}
433		else
434		{
435		memset( &flash_memory[ address & ~0xffff ], 0xff, 64 * 1024 );
436		c->erase_sector = address & ~0xffff;
437		timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 1 ), 0 );
438		}
439		}
440		break;
441		case 16:
442		{
443		UINT16 *flash_memory = (UINT16 *)c->flash_memory;
444		if (c->sector_is_4k)
445		{
446		memset( &flash_memory[ address & ~0x7ff ], 0xff, 4 * 1024 );
447		c->erase_sector = address & ~0x7ff;
448		timer_adjust_oneshot( c->timer, ATTOTIME_IN_MSEC( 125 ), 0 );
449		}
450		else
451		{
452		memset( &flash_memory[ address & ~0x7fff ], 0xff, 64 * 1024 );
453		c->erase_sector = address & ~0x7fff;
454		timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 1 ), 0 );
455		}
456		}
457		break;
	600	for (offs_t offs = 0; offs < 4 * 1024; offs++)
	601	m_addrspace[0]->write_byte((address & ~0xfff) + offs, 0xff);
	602	m_erase_sector = address & ~0xfff;
	603	timer_adjust_oneshot( m_timer, ATTOTIME_IN_MSEC( 125 ), 0 );
458	604	}
	605	else
	606	{
	607	for (offs_t offs = 0; offs < 64 * 1024; offs++)
	608	m_addrspace[0]->write_byte((address & ~0xffff) + offs, 0xff);
	609	m_erase_sector = address & ~0xffff;
	610	timer_adjust_oneshot( m_timer, ATTOTIME_IN_SEC( 1 ), 0 );
	611	}
459	612
460		c->status = 1 << 3;
461		c->flash_mode = FM_ERASEAMD4;
	613	m_status = 1 << 3;
	614	m_flash_mode = FM_ERASEAMD4;
462	615	}
463	616	else
464	617	{
r9152	r9153
466	619	}
467	620	break;
468	621	case FM_BYTEPROGRAM:
469		switch( c->bits )
	622	switch( m_config.m_bits )
470	623	{
471	624	case 8:
472	625	{
473		UINT8 *flash_memory = (UINT8 *)c->flash_memory;
474		flash_memory[ address ] = data;
	626	m_addrspace[0]->write_byte(address, data);
475	627	}
476	628	break;
477	629	default:
478		logerror( "FM_BYTEPROGRAM not supported when c->bits == %d\n", c->bits );
	630	logerror( "FM_BYTEPROGRAM not supported when m_bits == %d\n", m_config.m_bits );
479	631	break;
480	632	}
481		c->flash_mode = FM_NORMAL;
	633	m_flash_mode = FM_NORMAL;
482	634	break;
483	635	case FM_WRITEPART1:
484		switch( c->bits )
	636	switch( m_config.m_bits )
485	637	{
486	638	case 8:
487	639	{
488		UINT8 *flash_memory = (UINT8 *)c->flash_memory;
489		flash_memory[ address ] = data;
	640	m_addrspace[0]->write_byte(address, data);
490	641	}
491	642	break;
492	643	case 16:
493	644	{
494		UINT16 *flash_memory = (UINT16 *)c->flash_memory;
495		flash_memory[ address ] = data;
	645	m_addrspace[0]->write_word(address * 2, data);
496	646	}
497	647	break;
498	648	default:
499		logerror( "FM_WRITEPART1 not supported when c->bits == %d\n", c->bits );
	649	logerror( "FM_WRITEPART1 not supported when m_bits == %d\n", m_config.m_bits );
500	650	break;
501	651	}
502		c->status = 0x80;
503		c->flash_mode = FM_READSTATUS;
	652	m_status = 0x80;
	653	m_flash_mode = FM_READSTATUS;
504	654	break;
505	655	case FM_CLEARPART1:
506	656	if( ( data & 0xff ) == 0xd0 )
507	657	{
508	658	// clear the 64k block containing the current address to all 0xffs
509		switch( c->bits )
510		{
511		case 8:
512		{
513		UINT8 *flash_memory = (UINT8 *)c->flash_memory;
514		memset( &flash_memory[ address & ~0xffff ], 0xff, 64 * 1024 );
515		}
516		break;
517		case 16:
518		{
519		UINT16 *flash_memory = (UINT16 *)c->flash_memory;
520		memset( &flash_memory[ address & ~0x7fff ], 0xff, 64 * 1024 );
521		}
522		break;
523		default:
524		logerror( "FM_CLEARPART1 not supported when c->bits == %d\n", c->bits );
525		break;
526		}
527		c->status = 0x00;
528		c->flash_mode = FM_READSTATUS;
	659	for (offs_t offs = 0; offs < 64 * 1024; offs++)
	660	m_addrspace[0]->write_byte((address & ~0xffff) + offs, 0xff);
529	661
530		timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 1 ), 0 );
	662	m_status = 0x00;
	663	m_flash_mode = FM_READSTATUS;
	664
	665	timer_adjust_oneshot( m_timer, ATTOTIME_IN_SEC( 1 ), 0 );
531	666	break;
532	667	}
533	668	else
r9152	r9153
539	674	switch( data & 0xff )
540	675	{
541	676	case 0xf1:
542		c->flash_master_lock = 1;
	677	m_flash_master_lock = true;
543	678	break;
544	679	case 0xd0:
545		c->flash_master_lock = 0;
	680	m_flash_master_lock = false;
546	681	break;
547	682	default:
548	683	logerror( "unexpected %08x=%02x in FM_SETMASTER:\n", address, data & 0xff );
549	684	break;
550	685	}
551		c->flash_mode = FM_NORMAL;
	686	m_flash_mode = FM_NORMAL;
552	687	break;
553	688	}
554	689	}
555
556		void nvram_handler_intelflash(running_machine *machine, int chip,mame_file *file,int read_or_write)
557		{
558		struct flash_chip *c;
559		if( chip >= FLASH_CHIPS_MAX )
560		{
561		logerror( "intelflash_nvram: invalid chip %d\n", chip );
562		return;
563		}
564		c = &chips[ chip ];
565
566		switch( c->bits )
567		{
568		case 8:
569		if (read_or_write)
570		{
571		mame_fwrite( file, c->flash_memory, c->size );
572		}
573		else if (file)
574		{
575		mame_fread( file, c->flash_memory, c->size );
576		}
577		break;
578		case 16:
579		if (read_or_write)
580		{
581		/// TODO: endian conversion
582		mame_fwrite( file, c->flash_memory, c->size );
583		}
584		else if (file)
585		{
586		mame_fread( file, c->flash_memory, c->size );
587		/// TODO: endian conversion
588		}
589		break;
590		}
591		}

src/emu/machine/intelfsh.h

r9152	r9153
5	5	#ifndef _INTELFLASH_H_
6	6	#define _INTELFLASH_H_
7	7
8		#define FLASH_CHIPS_MAX   ( 56 )
9	8
10		#define FLASH_INTEL_28F016S5 ( 0 )
11		#define FLASH_SHARP_LH28F400 ( 1 )
12		#define FLASH_FUJITSU_29F016A ( 2 )
13		#define FLASH_INTEL_E28F008SA ( 3 )
14		#define FLASH_INTEL_TE28F160 ( 4 )
15		#define FLASH_SHARP_LH28F016S ( 5 )
16		#define FLASH_INTEL_E28F400 ( 6 )
17		#define FLASH_SHARP_UNK128MBIT ( 7 )
18		#define FLASH_MACRONIX_29L001MC ( 8 )
19		#define FLASH_PANASONIC_MN63F805MNP ( 9 )
20		#define FLASH_SANYO_LE26FV10N1TS ( 10 )
	9	//**************************************************************************
	10	//  INTERFACE CONFIGURATION MACROS
	11	//**************************************************************************
21	12
22		extern void intelflash_init( running_machine *machine, int chip, int type, void *data );
23		extern UINT32 intelflash_read( int chip, UINT32 address );
24		extern void intelflash_write( int chip, UINT32 address, UINT32 value );
25		extern void nvram_handler_intelflash( running_machine *machine, int chip, mame_file *file, int read_or_write );
26		extern void* intelflash_getmemptr(int chip);
	13	#define MDRV_INTEL_28F016S5_ADD(_tag) \
	14	MDRV_DEVICE_ADD(_tag, INTEL_28F016S5, 0)
27	15
	16	#define MDRV_SHARP_LH28F016S_ADD(_tag) \
	17	MDRV_DEVICE_ADD(_tag, SHARP_LH28F016S, 0)
	18
	19	#define MDRV_FUJITSU_29F016A_ADD(_tag) \
	20	MDRV_DEVICE_ADD(_tag, FUJITSU_29F016A, 0)
	21
	22	#define MDRV_INTEL_E28F400_ADD(_tag) \
	23	MDRV_DEVICE_ADD(_tag, INTEL_E28F400, 0)
	24
	25	#define MDRV_MACRONIX_29L001MC_ADD(_tag) \
	26	MDRV_DEVICE_ADD(_tag, MACRONIX_29L001MC, 0)
	27
	28	#define MDRV_PANASONIC_MN63F805MNP_ADD(_tag) \
	29	MDRV_DEVICE_ADD(_tag, PANASONIC_MN63F805MNP, 0)
	30
	31	#define MDRV_SANYO_LE26FV10N1TS_ADD(_tag) \
	32	MDRV_DEVICE_ADD(_tag, SANYO_LE26FV10N1TS, 0)
	33
	34	#define MDRV_SHARP_LH28F400_ADD(_tag) \
	35	MDRV_DEVICE_ADD(_tag, SHARP_LH28F400, 0)
	36
	37	#define MDRV_INTEL_E28F008SA_ADD(_tag) \
	38	MDRV_DEVICE_ADD(_tag, INTEL_E28F008SA, 0)
	39
	40	#define MDRV_INTEL_TE28F160_ADD(_tag) \
	41	MDRV_DEVICE_ADD(_tag, INTEL_TE28F160, 0)
	42
	43	#define MDRV_SHARP_UNK128MBIT_ADD(_tag) \
	44	MDRV_DEVICE_ADD(_tag, SHARP_UNK128MBIT, 0)
	45
	46
	47
	48	//**************************************************************************
	49	//  TYPE DEFINITIONS
	50	//**************************************************************************
	51
	52	class intelfsh_device;
	53
	54
	55	// ======================> intelfsh_device_config
	56
	57	class intelfsh_device_config :   public device_config,
	58	public device_config_memory_interface,
	59	public device_config_nvram_interface
	60	{
	61	friend class intelfsh_device;
	62
	63	protected:
	64	// constants
	65	enum
	66	{
	67	// 8-bit variants
	68	FLASH_INTEL_28F016S5 = 0x0800,
	69	FLASH_FUJITSU_29F016A,
	70	FLASH_SHARP_LH28F016S,
	71	FLASH_INTEL_E28F400,
	72	FLASH_MACRONIX_29L001MC,
	73	FLASH_PANASONIC_MN63F805MNP,
	74	FLASH_SANYO_LE26FV10N1TS,
	75
	76	// 16-bit variants
	77	FLASH_SHARP_LH28F400 = 0x1000,
	78	FLASH_INTEL_E28F008SA,
	79	FLASH_INTEL_TE28F160,
	80	FLASH_SHARP_UNK128MBIT
	81	};
	82
	83	// construction/destruction
	84	intelfsh_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant);
	85
	86	// device_config_memory_interface overrides
	87	virtual const address_space_config *memory_space_config(int spacenum = 0) const;
	88
	89	// internal state
	90	address_space_config   m_space_config;
	91	UINT32                m_type;
	92	INT32                m_size;
	93	UINT8                m_bits;
	94	UINT8                m_device_id;
	95	UINT8                m_maker_id;
	96	bool                m_sector_is_4k;
	97	};
	98
	99
	100	// ======================> intelfsh_device
	101
	102	class intelfsh_device :   public device_t,
	103	public device_memory_interface,
	104	public device_nvram_interface
	105	{
	106	friend class intelfsh_device_config;
	107
	108	protected:
	109	// construction/destruction
	110	intelfsh_device(running_machine &_machine, const intelfsh_device_config &config);
	111
	112	protected:
	113	// device-level overrides
	114	virtual void device_start();
	115	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	116
	117	// device_config_nvram_interface overrides
	118	virtual void nvram_default();
	119	virtual void nvram_read(mame_file &file);
	120	virtual void nvram_write(mame_file &file);
	121
	122	// derived helpers
	123	UINT32 read_full(UINT32 offset);
	124	void write_full(UINT32 offset, UINT32 data);
	125
	126	// internal state
	127	const intelfsh_device_config &   m_config;
	128
	129	UINT8                   m_status;
	130	INT32                   m_erase_sector;
	131	INT32                   m_flash_mode;
	132	bool                   m_flash_master_lock;
	133	emu_timer *               m_timer;
	134	};
	135
	136
	137	// ======================> intelfsh8_device_config
	138
	139	class intelfsh8_device_config : public intelfsh_device_config
	140	{
	141	friend class intelfsh8_device;
	142
	143	protected:
	144	// construction/destruction
	145	intelfsh8_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant);
	146	};
	147
	148
	149	// ======================> intelfsh8_device
	150
	151	class intelfsh8_device : public intelfsh_device
	152	{
	153	friend class intelfsh8_device_config;
	154	friend class intel_28f016s5_device_config;
	155	friend class fujitsu_29f016a_device_config;
	156	friend class sharp_lh28f016s_device_config;
	157	friend class intel_e28f008sa_device_config;
	158	friend class macronix_29l001mc_device_config;
	159	friend class panasonic_mn63f805mnp_device_config;
	160	friend class sanyo_le26fv10n1ts_device_config;
	161
	162	protected:
	163	// construction/destruction
	164	intelfsh8_device(running_machine &_machine, const intelfsh_device_config &config);
	165
	166	public:
	167	// public interface
	168	UINT8 read(offs_t offset) { return read_full(offset); }
	169	void write(offs_t offset, UINT8 data) { write_full(offset, data); }
	170
	171	UINT8 read_raw(offs_t offset) { return m_addrspace[0]->read_byte(offset); }
	172	void write_raw(offs_t offset, UINT8 data) { m_addrspace[0]->write_byte(offset, data); }
	173	};
	174
	175
	176	// ======================> intelfsh16_device_config
	177
	178	class intelfsh16_device_config : public intelfsh_device_config
	179	{
	180	friend class intelfsh16_device;
	181
	182	protected:
	183	// construction/destruction
	184	intelfsh16_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant);
	185	};
	186
	187
	188	// ======================> intelfsh16_device
	189
	190	class intelfsh16_device : public intelfsh_device
	191	{
	192	friend class intelfsh16_device_config;
	193	friend class sharp_lh28f400_device_config;
	194	friend class intel_te28f160_device_config;
	195	friend class intel_e28f400_device_config;
	196	friend class sharp_unk128mbit_device_config;
	197
	198	protected:
	199	// construction/destruction
	200	intelfsh16_device(running_machine &_machine, const intelfsh_device_config &config);
	201
	202	public:
	203	// public interface
	204	UINT16 read(offs_t offset) { return read_full(offset); }
	205	void write(offs_t offset, UINT16 data) { write_full(offset, data); }
	206
	207	UINT16 read_raw(offs_t offset) { return m_addrspace[0]->read_word(offset * 2); }
	208	void write_raw(offs_t offset, UINT16 data) { m_addrspace[0]->write_word(offset * 2, data); }
	209	};
	210
	211
	212	// ======================> trivial variants
	213
	214	// 8-bit variants
	215	DECLARE_TRIVIAL_DERIVED_DEVICE(intel_28f016s5_device_config, intelfsh8_device_config, intel_28f016s5_device, intelfsh8_device)
	216	DECLARE_TRIVIAL_DERIVED_DEVICE(fujitsu_29f016a_device_config, intelfsh8_device_config, fujitsu_29f016a_device, intelfsh8_device)
	217	DECLARE_TRIVIAL_DERIVED_DEVICE(sharp_lh28f016s_device_config, intelfsh8_device_config, sharp_lh28f016s_device, intelfsh8_device)
	218	DECLARE_TRIVIAL_DERIVED_DEVICE(intel_e28f008sa_device_config, intelfsh8_device_config, intel_e28f008sa_device, intelfsh8_device)
	219	DECLARE_TRIVIAL_DERIVED_DEVICE(macronix_29l001mc_device_config, intelfsh8_device_config, macronix_29l001mc_device, intelfsh8_device)
	220	DECLARE_TRIVIAL_DERIVED_DEVICE(panasonic_mn63f805mnp_device_config, intelfsh8_device_config, panasonic_mn63f805mnp_device, intelfsh8_device)
	221	DECLARE_TRIVIAL_DERIVED_DEVICE(sanyo_le26fv10n1ts_device_config, intelfsh8_device_config, sanyo_le26fv10n1ts_device, intelfsh8_device)
	222
	223
	224	// 16-bit variants
	225	DECLARE_TRIVIAL_DERIVED_DEVICE(sharp_lh28f400_device_config, intelfsh16_device_config, sharp_lh28f400_device, intelfsh16_device)
	226	DECLARE_TRIVIAL_DERIVED_DEVICE(intel_te28f160_device_config, intelfsh16_device_config, intel_te28f160_device, intelfsh16_device)
	227	DECLARE_TRIVIAL_DERIVED_DEVICE(intel_e28f400_device_config, intelfsh16_device_config, intel_e28f400_device, intelfsh16_device)
	228	DECLARE_TRIVIAL_DERIVED_DEVICE(sharp_unk128mbit_device_config, intelfsh16_device_config, sharp_unk128mbit_device, intelfsh16_device)
	229
	230
	231
	232	// device type definition
	233	extern const device_type INTEL_28F016S5;
	234	extern const device_type SHARP_LH28F016S;
	235	extern const device_type FUJITSU_29F016A;
	236	extern const device_type INTEL_E28F400;
	237	extern const device_type MACRONIX_29L001MC;
	238	extern const device_type PANASONIC_MN63F805MNP;
	239	extern const device_type SANYO_LE26FV10N1TS;
	240
	241	extern const device_type SHARP_LH28F400;
	242	extern const device_type INTEL_E28F008SA;
	243	extern const device_type INTEL_TE28F160;
	244	extern const device_type SHARP_UNK128MBIT;
	245
	246
28	247	#endif

src/emu/machine/mc146818.c

r9152	r9153
192	192	//  device_timer - handler timer events
193	193	//-------------------------------------------------
194	194
195		void mc146818_device::device_timer(emu_timer &timer, int param, void *ptr)
	195	void mc146818_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
196	196	{
197	197	int year/*, month*/;
198	198

src/emu/timer.c

r9152	r9153
57	57	attotime            start;         /* time when the timer was started */
58	58	attotime            expire;         /* time when the timer will expire */
59	59	device_t *            device;         /* for device timers, a pointer to the device */
	60	device_timer_id            id;            /* for device timers, the ID of the timer */
60	61	};
61	62
62	63
r9152	r9153
372	373	if (was_enabled)
373	374	{
374	375	if (timer->device != NULL)
375		timer->device->timer_fired(*timer, timer->param, timer->ptr);
	376	timer->device->timer_fired(*timer, timer->id, timer->param, timer->ptr);
376	377	else if (timer->callback != NULL)
377	378	{
378	379	LOG(("Timer %s:%d[%s] fired (expire=%s)\n", timer->file, timer->line, timer->func, attotime_string(timer->expire, 9)));
r9152	r9153
519	520	state_save_register_item(timer->machine, "timer", timer->func, count, timer->start.attoseconds);
520	521	state_save_register_item(timer->machine, "timer", timer->func, count, timer->expire.seconds);
521	522	state_save_register_item(timer->machine, "timer", timer->func, count, timer->expire.attoseconds);
	523	if (timer->device != NULL)
	524	state_save_register_item(timer->machine, "timer", timer->func, count, timer->id);
522	525	}
523	526
524	527
r9152	r9153
594	597	isn't primed yet
595	598	-------------------------------------------------*/
596	599
597		INLINE emu_timer *_timer_alloc_common(running_machine *machine, timer_fired_func callback, void *ptr, const char *file, int line, const char *func, int temp)
	600	INLINE emu_timer *_timer_alloc_common(running_machine *machine, device_t *device, device_timer_id id, timer_fired_func callback, void *ptr, const char *file, int line, const char *func, int temp)
598	601	{
599	602	attotime time = get_current_time(machine);
600	603	emu_timer *timer = timer_new(machine);
r9152	r9153
609	612	timer->file = file;
610	613	timer->line = line;
611	614	timer->func = func;
612		timer->device = NULL;
	615	timer->device = device;
	616	timer->id = id;
613	617
614	618	/* compute the time of the next firing and insert into the list */
615	619	timer->start = time;
r9152	r9153
630	634
631	635	emu_timer *_timer_alloc_internal(running_machine *machine, timer_fired_func callback, void *ptr, const char *file, int line, const char *func)
632	636	{
633		return _timer_alloc_common(machine, callback, ptr, file, line, func, FALSE);
	637	return _timer_alloc_common(machine, NULL, 0, callback, ptr, file, line, func, FALSE);
634	638	}
635	639
636		emu_timer *device_timer_alloc(device_t &device, void *ptr, int param)
	640	emu_timer *device_timer_alloc(device_t &device, UINT32 id, void *ptr)
637	641	{
638		emu_timer *timer = _timer_alloc_common(device.machine, NULL, ptr, __FILE__, __LINE__, device.tag(), FALSE);
639		timer->param = param;
640		timer->device = &device;
641		return timer;
	642	return _timer_alloc_common(device.machine, &device, id, NULL, ptr, __FILE__, __LINE__, device.tag(), FALSE);
642	643	}
643	644
644	645
r9152	r9153
728	729	SIMPLIFIED ANONYMOUS TIMER MANAGEMENT
729	730	***************************************************************************/
730	731
	732	void device_timer_call_after_resynch(device_t &device, device_timer_id id, INT32 param, void *ptr)
	733	{
	734	emu_timer *timer = _timer_alloc_common(device.machine, &device, id, NULL, ptr, __FILE__, __LINE__, device.tag(), TRUE);
	735	timer_adjust_oneshot(timer, attotime_zero, param);
	736	}
	737
	738
731	739	/*-------------------------------------------------
732	740	timer_pulse - allocate a pulse timer, which
733	741	repeatedly calls the callback using the given
r9152	r9153
736	744
737	745	void _timer_pulse_internal(running_machine *machine, attotime period, void *ptr, INT32 param, timer_fired_func callback, const char *file, int line, const char *func)
738	746	{
739		emu_timer *timer = _timer_alloc_common(machine, callback, ptr, file, line, func, FALSE);
	747	emu_timer *timer = _timer_alloc_common(machine, NULL, 0, callback, ptr, file, line, func, FALSE);
740	748	timer_adjust_periodic(timer, period, param, period);
741	749	}
742	750
r9152	r9153
748	756
749	757	void _timer_set_internal(running_machine *machine, attotime duration, void *ptr, INT32 param, timer_fired_func callback, const char *file, int line, const char *func)
750	758	{
751		emu_timer *timer = _timer_alloc_common(machine, callback, ptr, file, line, func, TRUE);
	759	emu_timer *timer = _timer_alloc_common(machine, NULL, 0, callback, ptr, file, line, func, TRUE);
752	760	timer_adjust_oneshot(timer, duration, param);
753	761	}
754	762

src/emu/timer.h

r9152	r9153
149	149	emu_timer *_timer_alloc_internal(running_machine *machine, timer_fired_func callback, void *param, const char *file, int line, const char *func);
150	150
151	151	/* allocate a permament device timer that isn't primed yet */
152		emu_timer *device_timer_alloc(device_t &device, void *ptr = NULL, int param = 0);
	152	emu_timer *device_timer_alloc(device_t &device, device_timer_id id = 0, void *ptr = NULL);
153	153
154	154	/* adjust the time when this timer will fire and disable any periodic firings */
155	155	void timer_adjust_oneshot(emu_timer *which, attotime duration, INT32 param);
r9152	r9153
161	161
162	162	/* ----- anonymous timer management ----- */
163	163
	164	/* request a one-shot temporary timer for a device */
	165	void device_timer_call_after_resynch(device_t &device, device_timer_id id = 0, INT32 param = 0, void *ptr = NULL);
	166
164	167	/* allocate a one-shot timer, which calls the callback after the given duration */
165	168	void _timer_set_internal(running_machine *machine, attotime duration, void *ptr, INT32 param, timer_fired_func callback, const char *file, int line, const char *func);
166	169

src/mess/machine/bebox.c

r9152	r9153
815	815
816	816	static READ8_HANDLER( bebox_flash8_r )
817	817	{
	818	fujitsu_29f016a_device *flash = space->machine->device<fujitsu_29f016a_device>("flash");
818	819	offset = (offset & ~7) | (7 - (offset & 7));
819		return intelflash_read(0, offset);
	820	return flash->read(offset);
820	821	}
821	822
822	823
823	824	static WRITE8_HANDLER( bebox_flash8_w )
824	825	{
	826	fujitsu_29f016a_device *flash = space->machine->device<fujitsu_29f016a_device>("flash");
825	827	offset = (offset & ~7) | (7 - (offset & 7));
826		intelflash_write(0, offset, data);
	828	flash->write(offset, data);
827	829	}
828	830
829	831
r9152	r9153
1056	1058	*
1057	1059	*************************************/
1058	1060
1059		NVRAM_HANDLER( bebox )
1060		{
1061		nvram_handler_intelflash(machine, 0, file, read_or_write);
1062		}
1063
1064	1061	MACHINE_RESET( bebox )
1065	1062	{
1066	1063	bebox_devices.pic8259_master = NULL;
r9152	r9153
1098	1095
1099	1096	/* set up boot and flash ROM */
1100	1097	memory_set_bankptr(machine, "bank2", memory_region(machine, "user2"));
1101		intelflash_init(machine, 0, FLASH_FUJITSU_29F016A, memory_region(machine, "user1"));
1102	1098
1103	1099	/* install MESS managed RAM */
1104	1100	memory_install_readwrite_bank(space_0, 0, messram_get_size(machine->device("messram")) - 1, 0, 0x02000000, "bank3");

src/mess/includes/bebox.h

r9152	r9153
27	27	MACHINE_START( bebox );
28	28	MACHINE_RESET( bebox );
29	29	DRIVER_INIT( bebox );
30		NVRAM_HANDLER( bebox );
31	30
32	31	READ64_HANDLER( bebox_cpu0_imask_r );
33	32	READ64_HANDLER( bebox_cpu1_imask_r );

src/mess/messdriv.c

r9152	r9153
65	65	DRIVER( gbpocket )  /* Nintendo Game Boy Pocket Handheld */
66	66	DRIVER( gblight )   /* Nintendo Game Boy Light Handheld */
67	67	DRIVER( gbcolor )   /* Nintendo Game Boy Color Handheld */
68		DRIVER( gba )       /* Nintendo Game Boy Advance Handheld */
	68	//   DRIVER( gba )       /* Nintendo Game Boy Advance Handheld */
69	69	DRIVER( snes )      /* Nintendo Super Nintendo NTSC */
70	70	DRIVER( snespal )   /* Nintendo Super Nintendo PAL */
71	71	DRIVER( snessfx )   /* Nintendo Super Nintendo NTSC w/SuperFX CPU*/
r9152	r9153
346	346	DRIVER( pcw9256 )   /* 198? PCW9256  */
347	347	DRIVER( pcw9512 )   /* 198? PCW9512 (+)  */
348	348	DRIVER( pcw10 )    /* 198? PCW10     */
349		DRIVER( pcw16 )    /* 1995 PCW16     */
	349	//   DRIVER( pcw16 )    /* 1995 PCW16     */
350	350	DRIVER( nc100 )    /* 1992 NC100     */
351	351	DRIVER( nc150 )    /* 1992 NC150     */
352	352	DRIVER( nc200 )    /* 1993 NC200     */
r9152	r9153
768	768	DRIVER( genmod )   /* 199?? Myarc Geneve 9640    */
769	769	DRIVER( ti99_4p )   /* 1996 SNUG 99/4P (a.k.a. SGCPU)      */
770	770
771		DRIVER( avigo )    /*   */
	771	//   DRIVER( avigo )    /*   */
772	772
773	773	/* Texas Instruments Calculators */
774	774	DRIVER( ti73 )     /* 1990 TI-73    */

src/mess/mess.mak

r9152	r9153
584	584	$(MESS_MACHINE)/nc.o      \
585	585	$(MESS_VIDEO)/pcw.o         \
586	586	$(MESS_DRIVERS)/pcw.o      \
587		$(MESS_DRIVERS)/pcw16.o      \
588	587	$(MESS_VIDEO)/pcw16.o      \
589	588	$(MESS_DRIVERS)/pda600.o   \
	589	#$(MESS_DRIVERS)/pcw16.o      \
590	590
591	591	$(MESSOBJ)/apf.a:            \
592	592	$(MESS_DRIVERS)/apf.o      \
r9152	r9153
1172	1172	$(MESS_MACHINE)/pokemini.o   \
1173	1173	$(MESS_DRIVERS)/pokemini.o   \
1174	1174	$(MESS_DRIVERS)/vboy.o      \
1175		$(MESS_DRIVERS)/gba.o      \
1176		$(MESS_VIDEO)/gba.o      \
	1175	#   $(MESS_DRIVERS)/gba.o      \
	1176	#   $(MESS_VIDEO)/gba.o      \
1177	1177
1178	1178	$(MESSOBJ)/nokia.a:            \
1179	1179	$(MESS_DRIVERS)/mikromik.o   \
r9152	r9153
1516	1516	$(MESS_FORMATS)/thom_cas.o   \
1517	1517
1518	1518	$(MESSOBJ)/ti.a:            \
1519		$(MESS_VIDEO)/avigo.o      \
1520		$(MESS_DRIVERS)/avigo.o      \
1521	1519	$(MESS_DRIVERS)/ti85.o      \
1522	1520	$(MESS_FORMATS)/ti85_ser.o   \
1523	1521	$(MESS_VIDEO)/ti85.o      \
r9152	r9153
1551	1549	$(MESS_VIDEO)/733_asr.o      \
1552	1550	$(MESS_DRIVERS)/ti990_10.o   \
1553	1551	$(MESS_DRIVERS)/ti99_2.o   \
	1552	#   $(MESS_VIDEO)/avigo.o      \
	1553	#   $(MESS_DRIVERS)/avigo.o      \
1554	1554
1555	1555	$(MESSOBJ)/tiger.a:            \
1556	1556	$(MESS_DRIVERS)/gamecom.o   \

src/mess/drivers/pcw16.c

r9152	r9153
192	192	/* PCW16 Flash interface */
193	193	/* PCW16 can have two 1mb flash chips */
194	194
195		static NVRAM_HANDLER( pcw16 )
196		{
197		nvram_handler_intelflash( machine, 0, file, read_or_write );
198		nvram_handler_intelflash( machine, 1, file, read_or_write );
199		}
200
201	195	/* read flash0 */
202		static int pcw16_flash0_bank_handler_r(int bank, int offset)
	196	static int pcw16_flash0_bank_handler_r(running_machine *machine, int bank, int offset)
203	197	{
204		int flash_offset = (pcw16_banks[bank]<<14) | offset;
205
206		return intelflash_read(0, flash_offset);
	198	intel_e28f008sa_device *flash = machine->device<intel_e28f008sa_device>("flash0");
	199	int flash_offset = (pcw16_banks[bank]<<14) | offset;
	200	return flash->read(flash_offset);
207	201	}
208	202
209	203	/* read flash1 */
210		static int pcw16_flash1_bank_handler_r(int bank, int offset)
	204	static int pcw16_flash1_bank_handler_r(running_machine *machine, int bank, int offset)
211	205	{
	206	intel_e28f008sa_device *flash = machine->device<intel_e28f008sa_device>("flash1");
212	207	int flash_offset = ((pcw16_banks[bank]&0x03f)<<14) | offset;
213	208
214		return intelflash_read(1, flash_offset);
	209	return flash->read(flash_offset);
215	210	}
216	211
217	212	/* flash 0 */
218	213	static  READ8_HANDLER(pcw16_flash0_bank_handler0_r)
219	214	{
220		return pcw16_flash0_bank_handler_r(0, offset);
	215	return pcw16_flash0_bank_handler_r(space->machine,0, offset);
221	216	}
222	217
223	218	static  READ8_HANDLER(pcw16_flash0_bank_handler1_r)
224	219	{
225		return pcw16_flash0_bank_handler_r(1, offset);
	220	return pcw16_flash0_bank_handler_r(space->machine,1, offset);
226	221	}
227	222
228	223	static  READ8_HANDLER(pcw16_flash0_bank_handler2_r)
229	224	{
230		return pcw16_flash0_bank_handler_r(2, offset);
	225	return pcw16_flash0_bank_handler_r(space->machine,2, offset);
231	226	}
232	227
233	228	static  READ8_HANDLER(pcw16_flash0_bank_handler3_r)
234	229	{
235		return pcw16_flash0_bank_handler_r(3, offset);
	230	return pcw16_flash0_bank_handler_r(space->machine,3, offset);
236	231	}
237	232
238	233	/* flash 1 */
239	234	static  READ8_HANDLER(pcw16_flash1_bank_handler0_r)
240	235	{
241		return pcw16_flash1_bank_handler_r(0, offset);
	236	return pcw16_flash1_bank_handler_r(space->machine,0, offset);
242	237	}
243	238
244	239	static  READ8_HANDLER(pcw16_flash1_bank_handler1_r)
245	240	{
246		return pcw16_flash1_bank_handler_r(1, offset);
	241	return pcw16_flash1_bank_handler_r(space->machine,1, offset);
247	242	}
248	243
249	244	static  READ8_HANDLER(pcw16_flash1_bank_handler2_r)
250	245	{
251		return pcw16_flash1_bank_handler_r(2, offset);
	246	return pcw16_flash1_bank_handler_r(space->machine,2, offset);
252	247	}
253	248
254	249	static  READ8_HANDLER(pcw16_flash1_bank_handler3_r)
255	250	{
256		return pcw16_flash1_bank_handler_r(3, offset);
	251	return pcw16_flash1_bank_handler_r(space->machine,3, offset);
257	252	}
258	253
259	254	static const read8_space_func pcw16_flash0_bank_handlers_r[4] =
r9152	r9153
273	268	};
274	269
275	270	/* write flash0 */
276		static void pcw16_flash0_bank_handler_w(int bank, int offset, int data)
	271	static void pcw16_flash0_bank_handler_w(running_machine *machine, int bank, int offset, int data)
277	272	{
	273	intel_e28f008sa_device *flash = machine->device<intel_e28f008sa_device>("flash0");
	274
278	275	int flash_offset = (pcw16_banks[bank]<<14) | offset;
279	276
280		intelflash_write(0, flash_offset, data);
	277	flash->write(flash_offset, data);
281	278	}
282	279
283	280	/* read flash1 */
284		static void pcw16_flash1_bank_handler_w(int bank, int offset, int data)
	281	static void pcw16_flash1_bank_handler_w(running_machine *machine, int bank, int offset, int data)
285	282	{
	283	intel_e28f008sa_device *flash = machine->device<intel_e28f008sa_device>("flash1");
	284
286	285	int flash_offset = ((pcw16_banks[bank]&0x03f)<<14) | offset;
287	286
288		intelflash_write(1, flash_offset,data);
	287	flash->write(flash_offset,data);
289	288	}
290	289
291	290	/* flash 0 */
292	291	static WRITE8_HANDLER(pcw16_flash0_bank_handler0_w)
293	292	{
294		pcw16_flash0_bank_handler_w(0, offset, data);
	293	pcw16_flash0_bank_handler_w(space->machine,0, offset, data);
295	294	}
296	295
297	296
298	297	static WRITE8_HANDLER(pcw16_flash0_bank_handler1_w)
299	298	{
300		pcw16_flash0_bank_handler_w(1, offset, data);
	299	pcw16_flash0_bank_handler_w(space->machine,1, offset, data);
301	300	}
302	301
303	302	static WRITE8_HANDLER(pcw16_flash0_bank_handler2_w)
304	303	{
305		pcw16_flash0_bank_handler_w(2, offset, data);
	304	pcw16_flash0_bank_handler_w(space->machine,2, offset, data);
306	305	}
307	306
308	307	static WRITE8_HANDLER(pcw16_flash0_bank_handler3_w)
309	308	{
310		pcw16_flash0_bank_handler_w(3, offset, data);
	309	pcw16_flash0_bank_handler_w(space->machine,3, offset, data);
311	310	}
312	311
313	312
314	313	/* flash 1 */
315	314	static WRITE8_HANDLER(pcw16_flash1_bank_handler0_w)
316	315	{
317		pcw16_flash1_bank_handler_w(0, offset, data);
	316	pcw16_flash1_bank_handler_w(space->machine,0, offset, data);
318	317	}
319	318
320	319
321	320	static WRITE8_HANDLER(pcw16_flash1_bank_handler1_w)
322	321	{
323		pcw16_flash1_bank_handler_w(1, offset, data);
	322	pcw16_flash1_bank_handler_w(space->machine,1, offset, data);
324	323	}
325	324
326	325	static WRITE8_HANDLER(pcw16_flash1_bank_handler2_w)
327	326	{
328		pcw16_flash1_bank_handler_w(2, offset, data);
	327	pcw16_flash1_bank_handler_w(space->machine,2, offset, data);
329	328	}
330	329
331	330	static WRITE8_HANDLER(pcw16_flash1_bank_handler3_w)
332	331	{
333		pcw16_flash1_bank_handler_w(3, offset, data);
	332	pcw16_flash1_bank_handler_w(space->machine,3, offset, data);
334	333	}
335	334
336	335	static const write8_space_func pcw16_flash0_bank_handlers_w[4] =
r9152	r9153
431	430	{
432	431	/* nvram */
433	432	if ((bank_id & 0x040)==0)
434		{
	433	{
435	434	mem_ptr = (unsigned char *)intelflash_getmemptr(0);
436	435	}
437	436	else
r9152	r9153
1399	1398	MDRV_QUANTUM_TIME(HZ(60))
1400	1399
1401	1400	MDRV_MACHINE_START( pcw16 )
1402		MDRV_NVRAM_HANDLER( pcw16 )
1403	1401
1404	1402	MDRV_NS16550_ADD( "ns16550_1", pcw16_com_interface[0] )            /* TODO: Verify uart model */
1405	1403
r9152	r9153
1431	1429	/* internal ram */
1432	1430	MDRV_RAM_ADD("messram")
1433	1431	MDRV_RAM_DEFAULT_SIZE("2M")
	1432	MDRV_INTEL_E28F008SA_ADD("flash0")
	1433	MDRV_INTEL_E28F008SA_ADD("flash1")
1434	1434	MACHINE_CONFIG_END
1435	1435
1436
1437		static DRIVER_INIT( pcw16 )
1438		{
1439		/* init flashes */
1440		intelflash_init(machine, 0, FLASH_INTEL_E28F008SA, NULL);
1441		intelflash_init(machine, 1, FLASH_INTEL_E28F008SA, NULL);
1442		}
1443
1444	1436	/***************************************************************************
1445	1437
1446	1438	Game driver(s)
r9152	r9153
1456	1448
1457	1449
1458	1450	/*     YEAR  NAME     PARENT    COMPAT  MACHINE    INPUT     INIT    COMPANY          FULLNAME */
1459		COMP( 1995, pcw16,     0,      0,      pcw16,      pcw16,    pcw16,    "Amstrad plc",   "PCW16", GAME_NOT_WORKING )
	1451	COMP( 1995, pcw16,     0,      0,      pcw16,      pcw16,    0,       "Amstrad plc",   "PCW16", GAME_NOT_WORKING )

src/mess/drivers/bebox.c

r9152	r9153
28	28	#include "machine/pit8253.h"
29	29	#include "machine/idectrl.h"
30	30	#include "machine/mpc105.h"
	31	#include "machine/intelfsh.h"
31	32
32	33	/* Devices */
33	34	#include "devices/flopdrv.h"
r9152	r9153
155	156	MDRV_SOUND_ADD("ym3812", YM3812, 3579545)
156	157	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
157	158
158		MDRV_NVRAM_HANDLER( bebox )
	159	MDRV_FUJITSU_29F016A_ADD("flash")
159	160
160	161	MDRV_CDROM_ADD( "cdrom" )
161	162	MDRV_HARDDISK_ADD( "harddisk1" )

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