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r1003 Tuesday 18th September, 2007 at 20:23:21 UTC by Wilbert Pol
[PCE] Added support for 192KB extra RAM on Super CD System v3 HuCards.
[src/mess/drivers]pce.c
[src/mess/machine]pce.c

src/mess/machine/pce.c
r1002r1003
33#include "video/vdc.h"
44#include "cpu/h6280/h6280.h"
55#include "includes/pce.h"
6#include "sound/msm5205.h"
67#include "image.h"
78
89/* the largest possible cartridge image (street fighter 2 - 2.5MB) */
r1002r1003
1516/* CD Unit RAM */
1617UINT8   *pce_cd_ram;         /* 64KB RAM from a CD unit */
1718static UINT8   *pce_cd_bram;
18static int      pce_cd_bram_locked;
1919
20static struct {
21   UINT8   regs[16];
22   int      bram_locked;
23   int      adpcm_read_ptr;
24   int      adpcm_write_ptr;
25   int      adpcm_length;
26} pce_cd;
27
2028struct pce_struct pce;
2129
2230static UINT8 *cartridge_ram;
r1002r1003
2937static int joystick_port_select;        /* internal index of joystick ports */
3038static int joystick_data_select;        /* which nibble of joystick data we want */
3139
40/* prototypes */
41static void pce_cd_init( void );
42
43
3244static WRITE8_HANDLER( pce_sf2_banking_w ) {
33   memory_set_bankptr( 2, memory_region(REGION_USER1) + ( offset + 1 ) * 0x080000 );
34   memory_set_bankptr( 3, memory_region(REGION_USER1) + ( offset + 1 ) * 0x080000 + 0x8000 );
45   memory_set_bankptr( 2, memory_region(REGION_USER1) + offset * 0x080000 + 0x080000 );
46   memory_set_bankptr( 3, memory_region(REGION_USER1) + offset * 0x080000 + 0x088000 );
47   memory_set_bankptr( 4, memory_region(REGION_USER1) + offset * 0x080000 + 0x0D0000 );
3548}
3649
37static WRITE8_HANDLER( pce_populous_ram_w ) {
50static WRITE8_HANDLER( pce_cartridge_ram_w ) {
3851   cartridge_ram[ offset ] = data;
3952}
4053
r1002r1003
123136   memory_set_bankptr( 1, ROM );
124137   memory_set_bankptr( 2, ROM + 0x080000 );
125138   memory_set_bankptr( 3, ROM + 0x088000 );
139   memory_set_bankptr( 4, ROM + 0x0D0000 );
126140
127141   /* Check for Street fighter 2 */
128142   if ( size == PCE_ROM_MAXSIZE ) {
r1002r1003
133147   if ( ! memcmp( ROM + 0x1F26, "POPULOUS", 8 ) ) {
134148      cartridge_ram = auto_malloc( 0x8000 );
135149      memory_set_bankptr( 2, cartridge_ram );
136      memory_install_write8_handler( 0, ADDRESS_SPACE_PROGRAM, 0x080000, 0x087FFF, 0, 0, pce_populous_ram_w );
150      memory_install_write8_handler( 0, ADDRESS_SPACE_PROGRAM, 0x080000, 0x087FFF, 0, 0, pce_cartridge_ram_w );
137151   }
138152
139153   /* Check for CD system card */
140154   if ( ! memcmp( ROM + 0x3FFB6, "PC Engine CD-ROM SYSTEM", 23 ) ) {
141      /* Check for additional system card ram here */
155      /* Check if 192KB additional system card ram should be used */
156      if ( ! memcmp( ROM + 0x29D1, "VER. 3.", 7 ) || ! memcmp( ROM + 0x29C4, "VER. 3.", 7 ) ) {
157         cartridge_ram = auto_malloc( 0x30000 );
158         memory_set_bankptr( 4, cartridge_ram );
159         memory_install_write8_handler( 0, ADDRESS_SPACE_PROGRAM, 0x0D0000, 0x0FFFFF, 0, 0, pce_cartridge_ram_w );
160      }
142161   }
143162   return 0;
144163}
145164
146NVRAM_HANDLER( pce )
147{
148   if (read_or_write)
149   {
150      mame_fwrite(file, pce_cd_bram, PCE_BRAM_SIZE);
151   }
152   else
153   {
154       /* load battery backed memory from disk */
155      memset(pce_cd_bram, 0, PCE_BRAM_SIZE);
156      if (file)
157         mame_fread(file, pce_cd_bram, PCE_BRAM_SIZE);
158   }
159}
160
161static void pce_cd_bram_init( void ) {
162   pce_cd_bram = auto_malloc( PCE_BRAM_SIZE * 2 );
163   memset( pce_cd_bram, 0, PCE_BRAM_SIZE );
164   memset( pce_cd_bram + PCE_BRAM_SIZE, 0xFF, PCE_BRAM_SIZE );
165   memory_set_bankptr( 10, pce_cd_bram + PCE_BRAM_SIZE );
166   pce_cd_bram_locked = 1;
167}
168
169165DRIVER_INIT( pce ) {
170   pce_cd_bram_init();
166   pce_cd_init();
171167   pce.io_port_options = PCE_JOY_SIG | CONST_SIG;
172168}
173169
174170DRIVER_INIT( tg16 ) {
175   pce_cd_bram_init();
171   pce_cd_init();
176172   pce.io_port_options = TG_16_JOY_SIG | CONST_SIG;
177173}
178174
179175DRIVER_INIT( sgx ) {
180   pce_cd_bram_init();
176   pce_cd_init();
181177   pce.io_port_options = PCE_JOY_SIG | CONST_SIG;
182178}
183179
r1002r1003
213209   return (ret);
214210}
215211
212NVRAM_HANDLER( pce )
213{
214   if (read_or_write)
215   {
216      mame_fwrite(file, pce_cd_bram, PCE_BRAM_SIZE);
217   }
218   else
219   {
220      /* load battery backed memory from disk */
221      if (file)
222         mame_fread(file, pce_cd_bram, PCE_BRAM_SIZE);
223   }
224}
225
226static void pce_set_cd_bram( void ) {
227   memory_set_bankptr( 10, pce_cd_bram + ( pce_cd.bram_locked ? PCE_BRAM_SIZE : 0 ) );
228}
229
230static void pce_cd_reset( void ) {
231}
232
233static void pce_cd_init( void ) {
234   /* Initialize pce_cd struct */
235   memset( &pce_cd, 0, sizeof(pce_cd) );
236
237   /* Initialize BRAM */
238   pce_cd_bram = auto_malloc( PCE_BRAM_SIZE * 2 );
239   memset( pce_cd_bram, 0, PCE_BRAM_SIZE );
240   memset( pce_cd_bram + PCE_BRAM_SIZE, 0xFF, PCE_BRAM_SIZE );
241   pce_cd.bram_locked = 1;
242   pce_set_cd_bram();
243}
244
216245WRITE8_HANDLER( pce_cd_bram_w ) {
217   if ( ! pce_cd_bram_locked ) {
246   if ( ! pce_cd.bram_locked ) {
218247      pce_cd_bram[ offset ] = data;
219248   }
220249}
221250
222251WRITE8_HANDLER( pce_cd_intf_w ) {
252   logerror("%04X: write to CD interface offset %02X, data %02X\n", activecpu_get_pc(), offset, data );
253
223254   switch( offset & 0x0F ) {
224255   case 0x00:   /* CDC status */
225256   case 0x01:   /* CDC command / status / data */
257      break;
226258   case 0x02:   /* ADPCM / CD control */
227   case 0x03:   /* BRAM lock / CD status */
259      /* 00 is written here during booting */
260      break;
261   case 0x03:   /* BRAM lock / CD status - Read Only register */
262      break;
228263   case 0x04:   /* CD reset */
264      if ( data & 0x02 ) {
265         pce_cd_reset();
266      }
267      break;
229268   case 0x05:   /* Convert PCM data / PCM data */
230269   case 0x06:   /* PCM data */
231270      break;
232271   case 0x07:   /* BRAM unlock / CD status */
233272      if ( data & 0x80 ) {
234         pce_cd_bram_locked = 0;
235         memory_set_bankptr( 10, pce_cd_bram );
273         pce_cd.bram_locked = 0;
274         pce_set_cd_bram();
236275      }
237276      break;
238277   case 0x08:   /* ADPCM address (LSB) / CD data */
239278   case 0x09:   /* ADPCM address (MSB) */
240279   case 0x0A:   /* ADPCM RAM data port */
241280   case 0x0B:   /* ADPCM DMA control */
281      if ( ! ( pce_cd.regs[0x0B] & 0x02 ) && ( data & 0x02 ) ) {
282         /* Start CD to ADPCM transfer */
283      }
284      break;
242285   case 0x0C:   /* ADPCM status */
286      break;
243287   case 0x0D:   /* ADPCM address control */
288      if ( ( pce_cd.regs[0x0D] & 0x80 ) && ! ( data & 0x80 ) ) {
289         /* Reset ADPCM hardware */
290         pce_cd.adpcm_read_ptr = 0;
291         pce_cd.adpcm_write_ptr = 0;
292      }
293      if ( data & 0x10 ) {
294         pce_cd.adpcm_length = ( pce_cd.regs[0x09] << 8 ) | pce_cd.regs[0x08];
295      }
296      break;
244297   case 0x0E:   /* ADPCM playback rate */
298      break;
245299   case 0x0F:   /* ADPCM and CD audio fade timer */
246300      break;
247301   }
302
303   pce_cd.regs[offset] = data;
248304}
249305
250306READ8_HANDLER( pce_cd_intf_r ) {
251   UINT8 data = 0xFF;
307   UINT8 data = pce_cd.regs[offset];
252308
309   logerror("%04X: read from CD interface offset %02X\n", activecpu_get_pc(), offset );
253310   switch( offset & 0x0F ) {
254311   case 0x00:   /* CDC status */
255312   case 0x01:   /* CDC command / status / data */
256313   case 0x02:   /* ADPCM / CD control */
257314      break;
258315   case 0x03:   /* BRAM lock / CD status */
259      pce_cd_bram_locked = 1;
260      memory_set_bankptr( 10, pce_cd_bram + PCE_BRAM_SIZE );
316      /* bit 4 set when CD motor is on */
317      /* bit 2 set when less than half of the ADPCM data is remaining */
318      pce_cd.bram_locked = 1;
319      pce_set_cd_bram();
320      data = 0;
261321      break;
262322   case 0x04:   /* CD reset */
263323   case 0x05:   /* Convert PCM data / PCM data */
264324   case 0x06:   /* PCM data */
265325   case 0x07:   /* BRAM unlock / CD status */
326      data = ( pce_cd.bram_locked ? ( data & 0x7F ) : ( data | 0x80 ) );
327      break;
266328   case 0x08:   /* ADPCM address (LSB) / CD data */
267329   case 0x09:   /* ADPCM address (MSB) */
268330   case 0x0A:   /* ADPCM RAM data port */
src/mess/drivers/pce.c
r1002r1003
5757#include "includes/pce.h"
5858#include "devices/cartslot.h"
5959#include "sound/c6280.h"
60#include "sound/msm5205.h"
6061#include "hash.h"
6162
6263#define   MAIN_CLOCK   21477270
r1002r1003
6566ADDRESS_MAP_START( pce_mem , ADDRESS_SPACE_PROGRAM, 8)
6667   AM_RANGE( 0x000000, 0x07FFFF) AM_ROMBANK(1)
6768   AM_RANGE( 0x080000, 0x087FFF) AM_ROMBANK(2)
68   AM_RANGE( 0x088000, 0x0FFFFF) AM_ROMBANK(3)
69   AM_RANGE( 0x088000, 0x0CFFFF) AM_ROMBANK(3)
70   AM_RANGE( 0x0D0000, 0x0FFFFF) AM_ROMBANK(4)
6971   AM_RANGE( 0x100000, 0x10FFFF) AM_RAM AM_BASE( &pce_cd_ram )
7072   AM_RANGE( 0x110000, 0x1EDFFF) AM_NOP
7173   AM_RANGE( 0x1EE000, 0x1EE7FF) AM_ROMBANK(10) AM_WRITE( pce_cd_bram_w )
r1002r1003
8789ADDRESS_MAP_START( sgx_mem , ADDRESS_SPACE_PROGRAM, 8)
8890   AM_RANGE( 0x000000, 0x07FFFF) AM_ROMBANK(1)
8991   AM_RANGE( 0x080000, 0x087FFF) AM_ROMBANK(2)
90   AM_RANGE( 0x088000, 0x0FFFFF) AM_ROMBANK(3)
92   AM_RANGE( 0x088000, 0x0CFFFF) AM_ROMBANK(3)
93   AM_RANGE( 0x0D0000, 0x0FFFFF) AM_ROMBANK(4)
9194   AM_RANGE( 0x100000, 0x10FFFF) AM_RAM AM_BASE( &pce_cd_ram )
9295   AM_RANGE( 0x110000, 0x1EDFFF) AM_NOP
9396   AM_RANGE( 0x1EE000, 0x1EE7FF) AM_ROMBANK(10) AM_WRITE( pce_cd_bram_w )

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