src/mess/machine/pce.c
| r1001 | r1002 | |
| 7 | 7 | |
| 8 | 8 | /* the largest possible cartridge image (street fighter 2 - 2.5MB) */ |
| 9 | 9 | #define PCE_ROM_MAXSIZE (0x280000) |
| 10 | #define PCE_BRAM_SIZE 0x800 |
| 10 | 11 | |
| 11 | 12 | /* system RAM */ |
| 12 | 13 | unsigned char *pce_user_ram; /* scratch RAM at F8 */ |
| 13 | | UINT8 *pce_nvram; |
| 14 | 14 | |
| 15 | /* CD Unit RAM */ |
| 16 | UINT8 *pce_cd_ram; /* 64KB RAM from a CD unit */ |
| 17 | static UINT8 *pce_cd_bram; |
| 18 | static int pce_cd_bram_locked; |
| 19 | |
| 15 | 20 | struct pce_struct pce; |
| 16 | 21 | |
| 17 | 22 | static UINT8 *cartridge_ram; |
| r1001 | r1002 | |
| 118 | 123 | memory_set_bankptr( 1, ROM ); |
| 119 | 124 | memory_set_bankptr( 2, ROM + 0x080000 ); |
| 120 | 125 | memory_set_bankptr( 3, ROM + 0x088000 ); |
| 121 | | memory_set_bankptr( 4, ROM + 0x100000 ); |
| 122 | 126 | |
| 123 | 127 | /* Check for Street fighter 2 */ |
| 124 | 128 | if ( size == PCE_ROM_MAXSIZE ) { |
| r1001 | r1002 | |
| 131 | 135 | memory_set_bankptr( 2, cartridge_ram ); |
| 132 | 136 | memory_install_write8_handler( 0, ADDRESS_SPACE_PROGRAM, 0x080000, 0x087FFF, 0, 0, pce_populous_ram_w ); |
| 133 | 137 | } |
| 138 | |
| 139 | /* Check for CD system card */ |
| 140 | if ( ! memcmp( ROM + 0x3FFB6, "PC Engine CD-ROM SYSTEM", 23 ) ) { |
| 141 | /* Check for additional system card ram here */ |
| 142 | } |
| 134 | 143 | return 0; |
| 135 | 144 | } |
| 136 | 145 | |
| r1001 | r1002 | |
| 138 | 147 | { |
| 139 | 148 | if (read_or_write) |
| 140 | 149 | { |
| 141 | | mame_fwrite(file, pce_nvram, 0x2000); |
| 150 | mame_fwrite(file, pce_cd_bram, PCE_BRAM_SIZE); |
| 142 | 151 | } |
| 143 | 152 | else |
| 144 | 153 | { |
| 145 | 154 | /* load battery backed memory from disk */ |
| 146 | | memset(pce_nvram, 0, 0x2000); |
| 155 | memset(pce_cd_bram, 0, PCE_BRAM_SIZE); |
| 147 | 156 | if (file) |
| 148 | | mame_fread(file, pce_nvram, 0x2000); |
| 157 | mame_fread(file, pce_cd_bram, PCE_BRAM_SIZE); |
| 149 | 158 | } |
| 150 | 159 | } |
| 151 | 160 | |
| 152 | | DRIVER_INIT( pce ) |
| 153 | | { |
| 154 | | pce.io_port_options = NO_CD_SIG | PCE_JOY_SIG | CONST_SIG; |
| 161 | static void pce_cd_bram_init( void ) { |
| 162 | pce_cd_bram = auto_malloc( PCE_BRAM_SIZE * 2 ); |
| 163 | memset( pce_cd_bram, 0, PCE_BRAM_SIZE ); |
| 164 | memset( pce_cd_bram + PCE_BRAM_SIZE, 0xFF, PCE_BRAM_SIZE ); |
| 165 | memory_set_bankptr( 10, pce_cd_bram + PCE_BRAM_SIZE ); |
| 166 | pce_cd_bram_locked = 1; |
| 155 | 167 | } |
| 156 | 168 | |
| 157 | | DRIVER_INIT( tg16 ) |
| 158 | | { |
| 159 | | pce.io_port_options = NO_CD_SIG | TG_16_JOY_SIG | CONST_SIG; |
| 169 | DRIVER_INIT( pce ) { |
| 170 | pce_cd_bram_init(); |
| 171 | pce.io_port_options = PCE_JOY_SIG | CONST_SIG; |
| 160 | 172 | } |
| 161 | 173 | |
| 174 | DRIVER_INIT( tg16 ) { |
| 175 | pce_cd_bram_init(); |
| 176 | pce.io_port_options = TG_16_JOY_SIG | CONST_SIG; |
| 177 | } |
| 178 | |
| 162 | 179 | DRIVER_INIT( sgx ) { |
| 163 | | pce.io_port_options = NO_CD_SIG | PCE_JOY_SIG | CONST_SIG; |
| 180 | pce_cd_bram_init(); |
| 181 | pce.io_port_options = PCE_JOY_SIG | CONST_SIG; |
| 164 | 182 | } |
| 165 | 183 | |
| 166 | 184 | /* todo: how many input ports does the PCE have? */ |
| r1001 | r1002 | |
| 195 | 213 | return (ret); |
| 196 | 214 | } |
| 197 | 215 | |
| 216 | WRITE8_HANDLER( pce_cd_bram_w ) { |
| 217 | if ( ! pce_cd_bram_locked ) { |
| 218 | pce_cd_bram[ offset ] = data; |
| 219 | } |
| 220 | } |
| 221 | |
| 198 | 222 | WRITE8_HANDLER( pce_cd_intf_w ) { |
| 199 | 223 | switch( offset & 0x0F ) { |
| 200 | 224 | case 0x00: /* CDC status */ |
| r1001 | r1002 | |
| 204 | 228 | case 0x04: /* CD reset */ |
| 205 | 229 | case 0x05: /* Convert PCM data / PCM data */ |
| 206 | 230 | case 0x06: /* PCM data */ |
| 231 | break; |
| 207 | 232 | case 0x07: /* BRAM unlock / CD status */ |
| 233 | if ( data & 0x80 ) { |
| 234 | pce_cd_bram_locked = 0; |
| 235 | memory_set_bankptr( 10, pce_cd_bram ); |
| 236 | } |
| 237 | break; |
| 208 | 238 | case 0x08: /* ADPCM address (LSB) / CD data */ |
| 209 | 239 | case 0x09: /* ADPCM address (MSB) */ |
| 210 | 240 | case 0x0A: /* ADPCM RAM data port */ |
| r1001 | r1002 | |
| 224 | 254 | case 0x00: /* CDC status */ |
| 225 | 255 | case 0x01: /* CDC command / status / data */ |
| 226 | 256 | case 0x02: /* ADPCM / CD control */ |
| 257 | break; |
| 227 | 258 | case 0x03: /* BRAM lock / CD status */ |
| 259 | pce_cd_bram_locked = 1; |
| 260 | memory_set_bankptr( 10, pce_cd_bram + PCE_BRAM_SIZE ); |
| 261 | break; |
| 228 | 262 | case 0x04: /* CD reset */ |
| 229 | 263 | case 0x05: /* Convert PCM data / PCM data */ |
| 230 | 264 | case 0x06: /* PCM data */ |
src/mess/drivers/pce.c
| r1001 | r1002 | |
| 66 | 66 | AM_RANGE( 0x000000, 0x07FFFF) AM_ROMBANK(1) |
| 67 | 67 | AM_RANGE( 0x080000, 0x087FFF) AM_ROMBANK(2) |
| 68 | 68 | AM_RANGE( 0x088000, 0x0FFFFF) AM_ROMBANK(3) |
| 69 | | AM_RANGE( 0x100000, 0x1EDFFF) AM_ROMBANK(4) |
| 70 | | AM_RANGE( 0x1EE000, 0x1EFFFF) AM_RAM AM_BASE( &pce_nvram ) |
| 69 | AM_RANGE( 0x100000, 0x10FFFF) AM_RAM AM_BASE( &pce_cd_ram ) |
| 70 | AM_RANGE( 0x110000, 0x1EDFFF) AM_NOP |
| 71 | AM_RANGE( 0x1EE000, 0x1EE7FF) AM_ROMBANK(10) AM_WRITE( pce_cd_bram_w ) |
| 72 | AM_RANGE( 0x1EE800, 0x1EFFFF) AM_NOP |
| 71 | 73 | AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000) AM_BASE( &pce_user_ram ) |
| 72 | 74 | AM_RANGE( 0x1FE000, 0x1FE3FF) AM_READWRITE( vdc_0_r, vdc_0_w ) |
| 73 | 75 | AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE( vce_r, vce_w ) |
| r1001 | r1002 | |
| 86 | 88 | AM_RANGE( 0x000000, 0x07FFFF) AM_ROMBANK(1) |
| 87 | 89 | AM_RANGE( 0x080000, 0x087FFF) AM_ROMBANK(2) |
| 88 | 90 | AM_RANGE( 0x088000, 0x0FFFFF) AM_ROMBANK(3) |
| 89 | | AM_RANGE( 0x100000, 0x1EDFFF) AM_ROMBANK(4) |
| 90 | | AM_RANGE( 0x1EE000, 0x1EFFFF) AM_RAM AM_BASE( &pce_nvram ) |
| 91 | AM_RANGE( 0x100000, 0x10FFFF) AM_RAM AM_BASE( &pce_cd_ram ) |
| 92 | AM_RANGE( 0x110000, 0x1EDFFF) AM_NOP |
| 93 | AM_RANGE( 0x1EE000, 0x1EE7FF) AM_ROMBANK(10) AM_WRITE( pce_cd_bram_w ) |
| 94 | AM_RANGE( 0x1EE800, 0x1EFFFF) AM_NOP |
| 91 | 95 | AM_RANGE( 0x1F0000, 0x1F7FFF) AM_RAM AM_BASE( &pce_user_ram ) |
| 92 | 96 | AM_RANGE( 0x1FE000, 0x1FE007) AM_READWRITE( vdc_0_r, vdc_0_w ) AM_MIRROR(0x03E0) |
| 93 | 97 | AM_RANGE( 0x1FE008, 0x1FE00F) AM_READWRITE( vpc_r, vpc_w ) AM_MIRROR(0x03E0) |