src/emu/cpu/mips/mips3fe.c
| r9903 | r9904 | |
|---|
| 44 | 44 | UINT32 op, opswitch; |
| 45 | 45 | |
| 46 | 46 | /* compute the physical PC */ |
| 47 | assert((desc->physpc & 3) == 0); |
| 47 | 48 | if (!mips3com_translate_address(mips, ADDRESS_SPACE_PROGRAM, TRANSLATE_FETCH, &desc->physpc)) |
| 48 | 49 | { |
| 49 | 50 | /* uh-oh: a page fault; leave the description empty and just if this is the first instruction, leave it empty and */ |
| r9903 | r9904 | |
|---|
| 53 | 54 | } |
| 54 | 55 | |
| 55 | 56 | /* fetch the opcode */ |
| 57 | assert((desc->physpc & 3) == 0); |
| 56 | 58 | op = desc->opptr.l[0] = mips->direct->read_decrypted_dword(desc->physpc); |
| 57 | 59 | |
| 58 | 60 | /* all instructions are 4 bytes and default to a single cycle each */ |
src/emu/cpu/mips/mips3drc.c
| r9903 | r9904 | |
|---|
| 1104 | 1104 | UML_EXH(block, mips3->impstate->exception[EXCEPTION_TLBLOAD_FILL], IREG(0)); // exh exception[TLBLOAD_FILL],i0 |
| 1105 | 1105 | UML_LABEL(block, 1); // 1: |
| 1106 | 1106 | save_fast_iregs(mips3, block); |
| 1107 | |
| 1108 | // the saved PC may be set 1 instruction back with the low bit set to indicate |
| 1109 | // a delay slot; in this path we want the original instruction address, so recover it |
| 1110 | UML_ADD(block, IREG(0), MEM(&mips3->pc), IMM(3)); // add i0,<pc>,3 |
| 1111 | UML_AND(block, MEM(&mips3->pc), IREG(0), IMM(~3)); // and <pc>,i0,~3 |
| 1107 | 1112 | UML_EXIT(block, IMM(EXECUTE_MISSING_CODE)); // exit EXECUTE_MISSING_CODE |
| 1108 | 1113 | |
| 1109 | 1114 | drcuml_block_end(block); |