src/mame/machine/n64.c
| r9890 | r9891 | |
|---|
| 57 | 57 | |
| 58 | 58 | WRITE32_HANDLER( n64_mi_reg_w ) |
| 59 | 59 | { |
| 60 | //printf("MI %08x %08x\n", offset, data); |
| 60 | 61 | switch (offset) |
| 61 | 62 | { |
| 62 | 63 | case 0x00/4: // MI_INIT_MODE_REG |
| r9890 | r9891 | |
|---|
| 277 | 278 | |
| 278 | 279 | WRITE32_HANDLER( n64_rdram_reg_w ) |
| 279 | 280 | { |
| 281 | //printf("RD %08x %08x\n", offset, data); |
| 282 | |
| 280 | 283 | switch (offset) |
| 281 | 284 | { |
| 282 | 285 | case 0x00/4: // RDRAM_CONFIG_REG / RDRAM_DEVICE_TYPE_REG |
| r9890 | r9891 | |
|---|
| 509 | 512 | |
| 510 | 513 | WRITE32_DEVICE_HANDLER( n64_sp_reg_w ) |
| 511 | 514 | { |
| 515 | //printf("SP %08x %08x\n", offset, data); |
| 516 | |
| 512 | 517 | if ((offset & 0x10000) == 0) |
| 513 | 518 | { |
| 514 | 519 | switch (offset & 0xffff) |
| r9890 | r9891 | |
|---|
| 760 | 765 | |
| 761 | 766 | WRITE32_DEVICE_HANDLER( n64_dp_reg_w ) |
| 762 | 767 | { |
| 768 | //printf("DP %08x %08x\n", offset, data); |
| 769 | |
| 763 | 770 | _n64_state *state = device->machine->driver_data<_n64_state>(); |
| 764 | 771 | |
| 765 | 772 | //printf("%08x: %08x\n", offset, data); |
| r9890 | r9891 | |
|---|
| 923 | 930 | { |
| 924 | 931 | _n64_state *state = space->machine->driver_data<_n64_state>(); |
| 925 | 932 | |
| 933 | //printf("VI %08x %08x\n", offset, data); |
| 926 | 934 | switch (offset) |
| 927 | 935 | { |
| 928 | 936 | case 0x00/4: // VI_CONTROL_REG |
| r9890 | r9891 | |
|---|
| 1179 | 1187 | { |
| 1180 | 1188 | // UINT16 *ram = (UINT16*)rdram; |
| 1181 | 1189 | |
| 1190 | //printf("AI %08x %08x\n", offset, data); |
| 1182 | 1191 | switch (offset) |
| 1183 | 1192 | { |
| 1184 | 1193 | case 0x00/4: // AI_DRAM_ADDR_REG |
| 1185 | 1194 | // mame_printf_debug("ai_dram_addr = %08X at %08X\n", data, cpu_get_pc(space->cpu)); |
| 1186 | | ai_dram_addr = data & 0xffffff; |
| 1195 | ai_dram_addr = data & 0xfffff8; |
| 1187 | 1196 | break; |
| 1188 | 1197 | |
| 1189 | 1198 | case 0x04/4: // AI_LEN_REG |
| 1190 | 1199 | // mame_printf_debug("ai_len = %08X at %08X\n", data, cpu_get_pc(space->cpu)); |
| 1191 | | ai_len = data & 0x3ffff; // Hardware v2.0 has 18 bits, v1.0 has 15 bits |
| 1200 | ai_len = data & 0x3fff8; // Hardware v2.0 has 18 bits, v1.0 has 15 bits |
| 1192 | 1201 | audio_fifo_push(space->machine, ai_dram_addr, ai_len); |
| 1193 | 1202 | break; |
| 1194 | 1203 | |
| r9890 | r9891 | |
|---|
| 1282 | 1291 | |
| 1283 | 1292 | WRITE32_HANDLER( n64_pi_reg_w ) |
| 1284 | 1293 | { |
| 1294 | //printf("PI %08x %08x\n", offset, data); |
| 1295 | |
| 1285 | 1296 | switch (offset) |
| 1286 | 1297 | { |
| 1287 | 1298 | case 0x00/4: // PI_DRAM_ADDR_REG |
| r9890 | r9891 | |
|---|
| 1462 | 1473 | WRITE32_HANDLER( n64_ri_reg_w ) |
| 1463 | 1474 | { |
| 1464 | 1475 | //printf( "n64_ri_reg_w: 0x%02x/4 = %08x (%08x)\n", offset << 2, data, mem_mask ); |
| 1476 | //printf("RI %08x %08x\n", offset, data); |
| 1465 | 1477 | switch (offset) |
| 1466 | 1478 | { |
| 1467 | 1479 | case 0x00/4: // RI_MODE_REG |
| r9890 | r9891 | |
|---|
| 1938 | 1950 | |
| 1939 | 1951 | WRITE32_HANDLER( n64_si_reg_w ) |
| 1940 | 1952 | { |
| 1953 | //printf("SI %08x %08x\n", offset, data); |
| 1954 | |
| 1941 | 1955 | switch (offset) |
| 1942 | 1956 | { |
| 1943 | 1957 | case 0x00/4: // SI_DRAM_ADDR_REG |
| r9890 | r9891 | |
|---|
| 2016 | 2030 | |
| 2017 | 2031 | MACHINE_START( n64 ) |
| 2018 | 2032 | { |
| 2019 | | mips3drc_set_options(machine->device("maincpu"), MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY); |
| 2033 | mips3drc_set_options(machine->device("maincpu"), MIPS3DRC_COMPA |
| 2020 | 2034 | |
| 2021 | 2035 | /* configure fast RAM regions for DRC */ |
| 2022 | 2036 | mips3drc_add_fastram(machine->device("maincpu"), 0x00000000, 0x007fffff, FALSE, rdram); |