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r9882 Sunday 2nd January, 2011 at 01:34:54 UTC by MooglyGuy
Sync with MAME
[src/emu/cpu]cpu.mak
[src/emu/cpu/mips]mips3.c mips3com.h mips3drc.c

src/emu/cpu/cpu.mak
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832832ifneq ($(filter MIPS,$(CPUS)),)
833833OBJDIRS += $(CPUOBJ)/mips
834834CPUOBJS += $(CPUOBJ)/mips/r3000.o
835CPUOBJS += $(CPUOBJ)/mips/mips3com.o $(CPUOBJ)/mips/mips3fe.o $(CPUOBJ)/mips/mips3drc.o $(DRCOBJ)
835CPUOBJS += $(CPUOBJ)/mips/mips3com.o $(CPUOBJ)/mips/mips3.o $(CPUOBJ)/mips/mips3fe.o $(CPUOBJ)/mips/mips3drc.o $(DRCOBJ)
836836CPUOBJS += $(CPUOBJ)/mips/psx.o
837837DASMOBJS += $(CPUOBJ)/mips/r3kdasm.o
838838DASMOBJS += $(CPUOBJ)/mips/mips3dsm.o
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842842$(CPUOBJ)/mips/r3000.o:   $(CPUSRC)/mips/r3000.c \
843843         $(CPUSRC)/mips/r3000.h
844844
845$(CPUOBJ)/mips/mips3.o:   $(CPUSRC)/mips/mips3.h \
846         $(CPUSRC)/mips/mips3com.h \
847         $(CPUSRC)/mips/mips3.c
848
845849$(CPUOBJ)/mips/mips3com.o:   $(CPUSRC)/mips/mips3.h \
846850            $(CPUSRC)/mips/mips3com.h
847851
src/emu/cpu/mips/mips3com.h
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1919    CONSTANTS
2020***************************************************************************/
2121
22#define MIPS3_USE_DRC
23
2224/* core parameters */
2325#define MIPS3_MIN_PAGE_SHIFT      12
2426#define MIPS3_MIN_PAGE_SIZE         (1 << MIPS3_MIN_PAGE_SHIFT)
src/emu/cpu/mips/mips3drc.c
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3636
3737extern unsigned dasmmips3(char *buffer, unsigned pc, UINT32 op);
3838
39#ifdef MIPS3_USE_DRC
3940
40
4141/***************************************************************************
4242    DEBUGGING
4343***************************************************************************/
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36653665   }
36663666}
36673667
3668
36693668/***************************************************************************
36703669    NEC VR4300 VARIANTS
36713670***************************************************************************/
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40874086
40884087DEFINE_LEGACY_CPU_DEVICE(RM7000BE, rm7000be);
40894088DEFINE_LEGACY_CPU_DEVICE(RM7000LE, rm7000le);
4089
4090#endif   // MIPS3_USE_DRC
4091
src/emu/cpu/mips/mips3.c
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1111
1212#include "emu.h"
1313#include "debugger.h"
14#include "profiler.h"
15#include "mips3.h"
1416#include "mips3com.h"
1517
1618
1719#define ENABLE_OVERFLOWS   0
1820
21#ifndef MIPS3_USE_DRC
1922
2023/***************************************************************************
2124    HELPER MACROS
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98101   int         interrupt_cycles;
99102   UINT32      ll_value;
100103   UINT64      lld_value;
104   UINT32      badcop_value;
101105   const vtlb_entry *tlb_table;
102106
103107   /* endian-dependent load/store */
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156160#define ROPCODE(pc)      mips3.core.direct->read_decrypted_dword(pc)
157161
158162
163/***************************************************************************
164    DRC COMPATIBILITY
165***************************************************************************/
159166
167void mips3drc_set_options(device_t *device, UINT32 options)
168{
169}
170
171void mips3drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base)
172{
173}
174
175void mips3drc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycles)
176{
177}
178
160179/***************************************************************************
161180    EXECEPTION HANDLING
162181***************************************************************************/
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183202   /* put the cause in the low 8 bits and clear the branch delay flag */
184203   CAUSE = (CAUSE & ~0x800000ff) | (exception << 2);
185204
205   /* set the appropriate bits for coprocessor exceptions */
206   if(exception == EXCEPTION_BADCOP)
207   {
208      CAUSE |= mips3.badcop_value << 28;
209   }
210
186211   /* if we were in a branch delay slot, adjust */
187212   if (mips3.nextpc != ~0)
188213   {
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567592INLINE void handle_cop0(UINT32 op)
568593{
569594   if ((SR & SR_KSU_MASK) != SR_KSU_KERNEL && !(SR & SR_COP0))
595   {
596      mips3.badcop_value = 0;
570597      generate_exception(EXCEPTION_BADCOP, 1);
598   }
571599
572600   switch (RSREG)
573601   {
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703731   /* note: additional condition codes available on R5000 only */
704732
705733   if (!(SR & SR_COP1))
734   {
735      mips3.badcop_value = 1;
706736      generate_exception(EXCEPTION_BADCOP, 1);
737   }
707738
708739   switch (RSREG)
709740   {
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10591090   /* note: additional condition codes available on R5000 only */
10601091
10611092   if (!(SR & SR_COP1))
1093   {
1094      mips3.badcop_value = 1;
10621095      generate_exception(EXCEPTION_BADCOP, 1);
1096   }
10631097
10641098   switch (RSREG)
10651099   {
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14191453   UINT32 temp;
14201454
14211455   if (!(SR & SR_COP1))
1456   {
1457      mips3.badcop_value = 1;
14221458      generate_exception(EXCEPTION_BADCOP, 1);
1459   }
14231460
14241461   switch (op & 0x3f)
14251462   {
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14951532   UINT32 temp;
14961533
14971534   if (!(SR & SR_COP1))
1535   {
1536      mips3.badcop_value = 1;
14981537      generate_exception(EXCEPTION_BADCOP, 1);
1538   }
14991539
15001540   switch (op & 0x3f)
15011541   {
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15931633INLINE void handle_cop2(UINT32 op)
15941634{
15951635   if (!(SR & SR_COP2))
1636   {
1637      mips3.badcop_value = 2;
15961638      generate_exception(EXCEPTION_BADCOP, 1);
1639   }
15971640
15981641   switch (RSREG)
15991642   {
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25462589   }
25472590}
25482591
2549void mips3drc_set_options(running_device *device, UINT32 options)
2550{
2551}
2552
2553void mips3drc_add_fastram(running_device *device, offs_t start, offs_t end, UINT8 readonly, void *base)
2554{
2555}
2556
25572592DEFINE_LEGACY_CPU_DEVICE(VR4300BE, vr4300be);
25582593DEFINE_LEGACY_CPU_DEVICE(VR4300LE, vr4300le);
25592594DEFINE_LEGACY_CPU_DEVICE(VR4310BE, vr4310be);
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25762611
25772612DEFINE_LEGACY_CPU_DEVICE(RM7000BE, rm7000be);
25782613DEFINE_LEGACY_CPU_DEVICE(RM7000LE, rm7000le);
2614
2615#endif

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