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r9822 Sunday 26th December, 2010 at 14:53:47 UTC by Tim Schuerewegen
Synced the S3C24xx device with MAME and updated it to the latest version

[src/emu/machine]	s3c2400.c s3c2400.h s3c2410.c s3c2410.h s3c2440.c s3c2440.h s3c24xx.c
[src/mame/drivers]	ghosteo.c

src/mame/drivers/ghosteo.c

r9821	r9822
395	395
396	396	static READ32_HANDLER( bballoon_speedup_r )
397	397	{
398		UINT32 ret = s3c24xx_lcd_r(s3c2410, offset+0x10/4, mem_mask);
	398	UINT32 ret = s3c2410_lcd_r(s3c2410, offset+0x10/4, mem_mask);
399	399
400	400
401	401	int pc = cpu_get_pc(space->cpu);

src/emu/machine/s3c2400.c

r9821	r9822
9	9	#include "emu.h"
10	10	#include "cpu/arm7/arm7.h"
11	11	#include "cpu/arm7/arm7core.h"
12		#include "s3c2400.h"
	12	#include "machine/s3c2400.h"
13	13	#include "sound/dac.h"
14	14
15	15	#define VERBOSE_LEVEL ( 0 )
r9821	r9822
27	27	}
28	28	}
29	29
30		#include "machine/s3c2400.h"
31
32	30	#define DEVICE_S3C2400
33	31	#include "machine/s3c24xx.c"
34	32	#undef DEVICE_S3C2400
r9821	r9822
57	55	memory_install_readwrite32_device_handler( space, device, 0x14600040, 0x1460005b, 0, 0, s3c24xx_dma_2_r, s3c24xx_dma_2_w);
58	56	memory_install_readwrite32_device_handler( space, device, 0x14600060, 0x1460007b, 0, 0, s3c24xx_dma_3_r, s3c24xx_dma_3_w);
59	57	memory_install_readwrite32_device_handler( space, device, 0x14800000, 0x14800017, 0, 0, s3c24xx_clkpow_r, s3c24xx_clkpow_w);
60		memory_install_readwrite32_device_handler( space, device, 0x14a00000, 0x14a003ff, 0, 0, s3c24xx_lcd_r, s3c24xx_lcd_w);
	58	memory_install_readwrite32_device_handler( space, device, 0x14a00000, 0x14a003ff, 0, 0, s3c2400_lcd_r, s3c24xx_lcd_w);
61	59	memory_install_readwrite32_device_handler( space, device, 0x14a00400, 0x14a007ff, 0, 0, s3c24xx_lcd_palette_r, s3c24xx_lcd_palette_w);
62	60	memory_install_readwrite32_device_handler( space, device, 0x15000000, 0x1500002b, 0, 0, s3c24xx_uart_0_r, s3c24xx_uart_0_w);
63	61	memory_install_readwrite32_device_handler( space, device, 0x15004000, 0x1500402b, 0, 0, s3c24xx_uart_1_r, s3c24xx_uart_1_w);
r9821	r9822
90	88	{
91	89	s3c24xx_uart_fifo_w( device, uart, data);
92	90	}
	91
	92	DEFINE_LEGACY_DEVICE(S3C2400, s3c2400);

src/emu/machine/s3c2400.h

r9821	r9822
1	1	/*******************************************************************************
2	2
3		Samsung S3C2400 private data
	3	Samsung S3C2400
4	4
5	5	*******************************************************************************/
6	6
7	7	#ifndef __S3C2400_H__
8	8	#define __S3C2400_H__
9	9
	10	#include "devlegcy.h"
	11
10	12	/*******************************************************************************
11	13	MACROS / CONSTANTS
12	14	*******************************************************************************/
13	15
14	16	#define S3C2400_TAG "s3c2400"
15	17
16		#define S3C2400 DEVICE_GET_INFO_NAME( s3c2400 )
17
18	18	#define MDRV_S3C2400_ADD(_tag, _clock, _config) \
19	19	MDRV_DEVICE_ADD(_tag, S3C2400, _clock) \
20	20	MDRV_DEVICE_CONFIG(_config)
r9821	r9822
33	33	S3C2400_GPIO_PORT_G
34	34	};
35	35
	36	DECLARE_LEGACY_DEVICE(S3C2400, s3c2400);
	37
36	38	/*******************************************************************************
37	39	TYPE DEFINITIONS
38	40	*******************************************************************************/
r9821	r9822
583	585	typedef struct
584	586	{
585	587	s3c24xx_irq_regs_t regs;
	588	int line_irq, line_fiq;
586	589	} s3c24xx_irq_t;
587	590
588	591	typedef struct

src/emu/machine/s3c2410.c

r9821	r9822
9	9	#include "emu.h"
10	10	#include "cpu/arm7/arm7.h"
11	11	#include "cpu/arm7/arm7core.h"
12		#include "s3c2410.h"
	12	#include "machine/s3c2410.h"
13	13	#include "sound/dac.h"
14	14
15	15	#define VERBOSE_LEVEL ( 0 )
r9821	r9822
27	27	}
28	28	}
29	29
30		#include "machine/s3c2410.h"
31
32	30	#define DEVICE_S3C2410
33	31	#include "machine/s3c24xx.c"
34	32	#undef DEVICE_S3C2410
r9821	r9822
57	55	memory_install_readwrite32_device_handler( space, device, 0x4b000080, 0x4b0000a3, 0, 0, s3c24xx_dma_2_r, s3c24xx_dma_2_w);
58	56	memory_install_readwrite32_device_handler( space, device, 0x4b0000c0, 0x4b0000e3, 0, 0, s3c24xx_dma_3_r, s3c24xx_dma_3_w);
59	57	memory_install_readwrite32_device_handler( space, device, 0x4c000000, 0x4c000017, 0, 0, s3c24xx_clkpow_r, s3c24xx_clkpow_w);
60		memory_install_readwrite32_device_handler( space, device, 0x4d000000, 0x4d000063, 0, 0, s3c24xx_lcd_r, s3c24xx_lcd_w);
	58	memory_install_readwrite32_device_handler( space, device, 0x4d000000, 0x4d000063, 0, 0, s3c2410_lcd_r, s3c24xx_lcd_w);
61	59	memory_install_readwrite32_device_handler( space, device, 0x4d000400, 0x4d0007ff, 0, 0, s3c24xx_lcd_palette_r, s3c24xx_lcd_palette_w);
62	60	memory_install_readwrite32_device_handler( space, device, 0x4e000000, 0x4e000017, 0, 0, s3c24xx_nand_r, s3c24xx_nand_w);
63	61	memory_install_readwrite32_device_handler( space, device, 0x50000000, 0x5000002b, 0, 0, s3c24xx_uart_0_r, s3c24xx_uart_0_w);
r9821	r9822
110	108	for (int i = 0; i < size; i++) nand_update_mecc( mecc, i, data[i]);
111	109	}
112	110
	111	void s3c2410_request_eint( running_device *device, UINT32 number)
	112	{
	113	s3c24xx_request_eint( device, number);
	114	}
	115
113	116	DEFINE_LEGACY_DEVICE(S3C2410, s3c2410);

src/emu/machine/s3c2410.h

r9821	r9822
1	1	/*******************************************************************************
2	2
3		Samsung S3C2410 private data
	3	Samsung S3C2410
4	4
5	5	*******************************************************************************/
6	6
r9821	r9822
36	36
37	37	DECLARE_LEGACY_DEVICE(S3C2410, s3c2410);
38	38
39		READ32_DEVICE_HANDLER( s3c24xx_lcd_r );
	39	READ32_DEVICE_HANDLER( s3c2410_lcd_r );
40	40
41	41	/*******************************************************************************
42	42	TYPE DEFINITIONS
r9821	r9822
102	102
103	103	void s3c2410_uart_fifo_w( running_device *device, int uart, UINT8 data);
104	104	void s3c2410_touch_screen( running_device *device, int state);
	105	void s3c2410_request_eint( running_device *device, UINT32 number);
105	106
106	107	WRITE_LINE_DEVICE_HANDLER( s3c2410_pin_frnb_w );
107	108
r9821	r9822
711	712	typedef struct
712	713	{
713	714	s3c24xx_irq_regs_t regs;
	715	int line_irq, line_fiq;
714	716	} s3c24xx_irq_t;
715	717
716	718	typedef struct
r9821	r9822
778	780	{
779	781	s3c24xx_wdt_regs_t regs;
780	782	emu_timer *timer;
	783	UINT32 freq, cnt;
781	784	} s3c24xx_wdt_t;
782	785
783	786	typedef struct

src/emu/machine/s3c2440.c

r9821	r9822
9	9	#include "emu.h"
10	10	#include "cpu/arm7/arm7.h"
11	11	#include "cpu/arm7/arm7core.h"
12		#include "s3c2440.h"
	12	#include "machine/s3c2440.h"
13	13	#include "sound/dac.h"
14	14
15	15	#define VERBOSE_LEVEL ( 0 )
r9821	r9822
27	27	}
28	28	}
29	29
30		#include "machine/s3c2440.h"
31
32	30	#define DEVICE_S3C2440
33	31	#include "machine/s3c24xx.c"
34	32	#undef DEVICE_S3C2440
r9821	r9822
56	54	memory_install_readwrite32_device_handler( space, device, 0x4b000080, 0x4b0000a3, 0, 0, s3c24xx_dma_2_r, s3c24xx_dma_2_w);
57	55	memory_install_readwrite32_device_handler( space, device, 0x4b0000c0, 0x4b0000e3, 0, 0, s3c24xx_dma_3_r, s3c24xx_dma_3_w);
58	56	memory_install_readwrite32_device_handler( space, device, 0x4c000000, 0x4c00001b, 0, 0, s3c24xx_clkpow_r, s3c24xx_clkpow_w);
59		memory_install_readwrite32_device_handler( space, device, 0x4d000000, 0x4d000063, 0, 0, s3c24xx_lcd_r, s3c24xx_lcd_w);
	57	memory_install_readwrite32_device_handler( space, device, 0x4d000000, 0x4d000063, 0, 0, s3c2440_lcd_r, s3c24xx_lcd_w);
60	58	memory_install_readwrite32_device_handler( space, device, 0x4d000400, 0x4d0007ff, 0, 0, s3c24xx_lcd_palette_r, s3c24xx_lcd_palette_w);
61	59	memory_install_readwrite32_device_handler( space, device, 0x4e000000, 0x4e00003f, 0, 0, s3c24xx_nand_r, s3c24xx_nand_w);
62	60	memory_install_readwrite32_device_handler( space, device, 0x4f000000, 0x4f0000a3, 0, 0, s3c24xx_cam_r, s3c24xx_cam_w);
r9821	r9822
115	113	{
116	114	s3c24xx_pin_frnb_w( device, state);
117	115	}
	116
	117	DEFINE_LEGACY_DEVICE(S3C2440, s3c2440);

src/emu/machine/s3c2440.h

r9821	r9822
1	1	/*******************************************************************************
2	2
3		Samsung S3C2440 private data
	3	Samsung S3C2440
4	4
5	5	*******************************************************************************/
6	6
r9821	r9822
13	13
14	14	#define S3C2440_TAG "s3c2440"
15	15
16		#define S3C2440 DEVICE_GET_INFO_NAME( s3c2440 )
17
18	16	#define MDRV_S3C2440_ADD(_tag, _clock, _config) \
19	17	MDRV_DEVICE_ADD(_tag, S3C2440, _clock) \
20	18	MDRV_DEVICE_CONFIG(_config)
r9821	r9822
35	33	S3C2440_GPIO_PORT_J
36	34	};
37	35
	36	DECLARE_LEGACY_DEVICE(S3C2440, s3c2440);
	37
38	38	/*******************************************************************************
39	39	TYPE DEFINITIONS
40	40	*******************************************************************************/
r9821	r9822
770	770	typedef struct
771	771	{
772	772	s3c24xx_irq_regs_t regs;
	773	int line_irq, line_fiq;
773	774	} s3c24xx_irq_t;
774	775
775	776	typedef struct

src/emu/machine/s3c24xx.c

r9821	r9822
243	243	s3c24xx->lcd.dma_bits = 0;
244	244	}
245	245
246		/*
	246	#if 0
247	247	static UINT32 s3c24xx_lcd_dma_read( running_device *device)
248	248	{
249		s3c24xx_t *s3c24xx = get_token( device);
250		address_space* space = cputag_get_address_space( device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
251		UINT8 *vram, data[4];
252		vram = (UINT8 *)space->get_read_ptr( s3c24xx->lcd.vramaddr_cur);
253		for (int i = 0; i < 2; i++)
254		{
255		data[i*2+0] = *vram++;
256		data[i*2+1] = *vram++;
257		s3c24xx->lcd.vramaddr_cur += 2;
258		s3c24xx->lcd.pagewidth_cur++;
259		if (s3c24xx->lcd.pagewidth_cur >= s3c24xx->lcd.pagewidth_max)
260		{
261		s3c24xx->lcd.vramaddr_cur += s3c24xx->lcd.offsize << 1;
262		s3c24xx->lcd.pagewidth_cur = 0;
263		vram = (UINT8 *)space->get_read_ptr( s3c24xx->lcd.vramaddr_cur);
264		}
265		}
266		if (s3c24xx->lcd.hwswp == 0)
267		{
268		if (s3c24xx->lcd.bswp == 0)
269		{
270		return (data[3] << 24) | (data[2] << 16) | (data[1] << 8) | (data[0] << 0);
271		}
272		else
273		{
274		return (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | (data[3] << 0);
275		}
276		}
277		else
278		{
279		if (s3c24xx->lcd.bswp == 0)
280		{
281		return (data[1] << 24) | (data[0] << 16) | (data[3] << 8) | (data[2] << 0);
282		}
283		else
284		{
285		return (data[2] << 24) | (data[3] << 16) | (data[0] << 8) | (data[1] << 0);
286		}
287		}
	249	s3c24xx_t *s3c24xx = get_token( device);
	250	address_space* space = cputag_get_address_space( device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
	251	UINT8 *vram, data[4];
	252	vram = (UINT8 *)space->get_read_ptr( s3c24xx->lcd.vramaddr_cur);
	253	for (int i = 0; i < 2; i++)
	254	{
	255	data[i*2+0] = *vram++;
	256	data[i*2+1] = *vram++;
	257	s3c24xx->lcd.vramaddr_cur += 2;
	258	s3c24xx->lcd.pagewidth_cur++;
	259	if (s3c24xx->lcd.pagewidth_cur >= s3c24xx->lcd.pagewidth_max)
	260	{
	261	s3c24xx->lcd.vramaddr_cur += s3c24xx->lcd.offsize << 1;
	262	s3c24xx->lcd.pagewidth_cur = 0;
	263	vram = (UINT8 *)space->get_read_ptr( s3c24xx->lcd.vramaddr_cur);
	264	}
	265	}
	266	if (s3c24xx->lcd.hwswp == 0)
	267	{
	268	if (s3c24xx->lcd.bswp == 0)
	269	{
	270	return (data[3] << 24) | (data[2] << 16) | (data[1] << 8) | (data[0] << 0);
	271	}
	272	else
	273	{
	274	return (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | (data[3] << 0);
	275	}
	276	}
	277	else
	278	{
	279	if (s3c24xx->lcd.bswp == 0)
	280	{
	281	return (data[1] << 24) | (data[0] << 16) | (data[3] << 8) | (data[2] << 0);
	282	}
	283	else
	284	{
	285	return (data[2] << 24) | (data[3] << 16) | (data[0] << 8) | (data[1] << 0);
	286	}
	287	}
288	288	}
289		*/
	289	#endif
290	290
291	291	static UINT32 s3c24xx_lcd_dma_read( running_device *device)
292	292	{
r9821	r9822
521	521	}
522	522	}
523	523
	524	static void s3c24xx_lcd_render_stn_12_u( running_device *device) // not tested
	525	{
	526	s3c24xx_t *s3c24xx = get_token( device);
	527	bitmap_t *bitmap = s3c24xx->lcd.bitmap[0];
	528	UINT32 *scanline = BITMAP_ADDR32( bitmap, s3c24xx->lcd.vpos, s3c24xx->lcd.hpos);
	529	for (int i = 0; i < 4; i++)
	530	{
	531	UINT32 data = s3c24xx_lcd_dma_read( device);
	532	for (int j = 0; j < 2; j++)
	533	{
	534	*scanline++ = s3c24xx_get_color_stn_12( device, (data >> 16) & 0x0FFF);
	535	data = data << 16;
	536	s3c24xx->lcd.hpos++;
	537	if (s3c24xx->lcd.hpos >= s3c24xx->lcd.hpos_min + (s3c24xx->lcd.pagewidth_max << 0))
	538	{
	539	s3c24xx->lcd.vpos++;
	540	if (s3c24xx->lcd.vpos > s3c24xx->lcd.vpos_max) s3c24xx->lcd.vpos = s3c24xx->lcd.vpos_min;
	541	s3c24xx->lcd.hpos = s3c24xx->lcd.hpos_min;
	542	scanline = BITMAP_ADDR32( bitmap, s3c24xx->lcd.vpos, s3c24xx->lcd.hpos);
	543	}
	544	}
	545	}
	546	}
	547
524	548	static void s3c24xx_lcd_render_tft_01( running_device *device)
525	549	{
526	550	s3c24xx_t *s3c24xx = get_token( device);
r9821	r9822
668	692	case S3C24XX_BPPMODE_STN_04   : s3c24xx_lcd_render_stn_04( device); break;
669	693	case S3C24XX_BPPMODE_STN_08   : s3c24xx_lcd_render_stn_08( device); break;
670	694	case S3C24XX_BPPMODE_STN_12_P : s3c24xx_lcd_render_stn_12_p( device); break;
	695	case S3C24XX_BPPMODE_STN_12_U : s3c24xx_lcd_render_stn_12_u( device); break;
671	696	case S3C24XX_BPPMODE_TFT_01   : s3c24xx_lcd_render_tft_01( device); break;
672	697	case S3C24XX_BPPMODE_TFT_02   : s3c24xx_lcd_render_tft_02( device); break;
673	698	case S3C24XX_BPPMODE_TFT_04   : s3c24xx_lcd_render_tft_04( device); break;
r9821	r9822
734	759	return 0;
735	760	}
736	761
737		READ32_DEVICE_HANDLER( s3c24xx_lcd_r )
	762	#if defined(DEVICE_S3C2400)
	763	READ32_DEVICE_HANDLER( s3c2400_lcd_r )
	764	#elif defined(DEVICE_S3C2410)
	765	READ32_DEVICE_HANDLER( s3c2410_lcd_r )
	766	#elif defined(DEVICE_S3C2440)
	767	READ32_DEVICE_HANDLER( s3c2440_lcd_r )
	768	#endif
738	769	{
739	770	s3c24xx_t *s3c24xx = get_token( device);
740	771	UINT32 data = ((UINT32*)&s3c24xx->lcd.regs)[offset];
r9821	r9822
759	790	}
760	791	break;
761	792	}
762		if (offset != S3C24XX_LCDCON5)
763	793	verboselog( device->machine, 9, "(LCD) %08X -> %08X\n", S3C24XX_BASE_LCD + (offset << 2), data);
764	794	return data;
765	795	}
r9821	r9822
1005	1035	static void s3c24xx_check_pending_irq( running_device *device)
1006	1036	{
1007	1037	s3c24xx_t *s3c24xx = get_token( device);
1008		UINT32 temp = s3c24xx->irq.regs.srcpnd & ~s3c24xx->irq.regs.intmsk;
	1038	UINT32 temp;
	1039	// normal irq
	1040	temp = (s3c24xx->irq.regs.srcpnd & ~s3c24xx->irq.regs.intmsk) & ~s3c24xx->irq.regs.intmod;
1009	1041	if (temp != 0)
1010	1042	{
1011	1043	UINT32 int_type = 0;
r9821	r9822
1016	1048	}
1017	1049	s3c24xx->irq.regs.intpnd |= (1 << int_type);
1018	1050	s3c24xx->irq.regs.intoffset = int_type;
1019		cputag_set_input_line( device->machine, "maincpu", ARM7_IRQ_LINE, ASSERT_LINE);
	1051	if (s3c24xx->irq.line_irq != ASSERT_LINE)
	1052	{
	1053	cputag_set_input_line( device->machine, "maincpu", ARM7_IRQ_LINE, ASSERT_LINE);
	1054	s3c24xx->irq.line_irq = ASSERT_LINE;
	1055	}
1020	1056	}
1021	1057	else
1022	1058	{
1023		cputag_set_input_line( device->machine, "maincpu", ARM7_IRQ_LINE, CLEAR_LINE);
	1059	if (s3c24xx->irq.line_irq != CLEAR_LINE)
	1060	{
	1061	cputag_set_input_line( device->machine, "maincpu", ARM7_IRQ_LINE, CLEAR_LINE);
	1062	s3c24xx->irq.line_irq = CLEAR_LINE;
	1063	}
1024	1064	}
	1065	// fast irq
	1066	temp = (s3c24xx->irq.regs.srcpnd & ~s3c24xx->irq.regs.intmsk) & s3c24xx->irq.regs.intmod;
	1067	if (temp != 0)
	1068	{
	1069	UINT32 int_type = 0;
	1070	while ((temp & 1) == 0)
	1071	{
	1072	int_type++;
	1073	temp = temp >> 1;
	1074	}
	1075	if (s3c24xx->irq.line_fiq != ASSERT_LINE)
	1076	{
	1077	cputag_set_input_line( device->machine, "maincpu", ARM7_FIRQ_LINE, ASSERT_LINE);
	1078	s3c24xx->irq.line_fiq = ASSERT_LINE;
	1079	}
	1080	}
	1081	else
	1082	{
	1083	if (s3c24xx->irq.line_fiq != CLEAR_LINE)
	1084	{
	1085	cputag_set_input_line( device->machine, "maincpu", ARM7_FIRQ_LINE, CLEAR_LINE);
	1086	s3c24xx->irq.line_fiq = CLEAR_LINE;
	1087	}
	1088	}
1025	1089	}
1026	1090
1027	1091	static void s3c24xx_request_irq( running_device *device, UINT32 int_type)
r9821	r9822
1524	1588	{
1525	1589	case S3C24XX_DCON :
1526	1590	{
1527		/* --- is this code necessary ???
1528		if ((data & (1 << 22)) != 0) // reload
1529		{
1530		s3c24xx_dma_regs_t *regs = &s3c24xx->dma[ch].regs;
1531		regs->dmasktrig &= ~(1 << 1); // clear on/off
1532		}
1533		*/
	1591	#if 0 // is this code necessary ???
	1592	if ((data & (1 << 22)) != 0) // reload
	1593	{
	1594	s3c24xx_dma_regs_t *regs = &s3c24xx->dma[ch].regs;
	1595	regs->dmasktrig &= ~(1 << 1); // clear on/off
	1596	}
	1597	#endif
1534	1598	}
1535	1599	break;
1536	1600	case S3C24XX_DMASKTRIG :
r9821	r9822
1918	1982
1919	1983	/* Watchdog Timer */
1920	1984
	1985	#if defined(DEVICE_S3C2410)
	1986
	1987	static UINT16 s3c24xx_wdt_calc_current_count( running_device *device)
	1988	{
	1989	s3c24xx_t *s3c24xx = get_token( device);
	1990	double timeleft, x1, x2;
	1991	UINT32 cnt;
	1992	timeleft = attotime_to_double( timer_timeleft( s3c24xx->wdt.timer));
	1993	//   printf( "timeleft %f freq %d cnt %d\n", timeleft, s3c24xx->wdt.freq, s3c24xx->wdt.cnt);
	1994	x1 = 1 / ((double)s3c24xx->wdt.freq / s3c24xx->wdt.cnt);
	1995	x2 = x1 / timeleft;
	1996	//   printf( "x1 %f\n", x1);
	1997	cnt = s3c24xx->wdt.cnt / x2;
	1998	//   printf( "cnt %d\n", cnt);
	1999	return cnt;
	2000	}
	2001
	2002	#else
	2003
	2004	static UINT16 s3c24xx_wdt_calc_current_count( running_device *device)
	2005	{
	2006	return 0;
	2007	}
	2008
	2009	#endif
	2010
1921	2011	static READ32_DEVICE_HANDLER( s3c24xx_wdt_r )
1922	2012	{
1923	2013	s3c24xx_t *s3c24xx = get_token( device);
r9821	r9822
1926	2016	{
1927	2017	case S3C24XX_WTCNT :
1928	2018	{
1929		data = 0;
	2019	// is wdt active?
	2020	if ((s3c24xx->wdt.regs.wtcon & (1 << 5)) != 0)
	2021	{
	2022	data = s3c24xx_wdt_calc_current_count( device);
	2023	}
1930	2024	}
1931	2025	break;
1932	2026	}
r9821	r9822
1947	2041	hz = freq / s3c24xx->wdt.regs.wtcnt;
1948	2042	verboselog( device->machine, 5, "WDT pclk %d prescaler %d clock %d freq %f hz %f\n", pclk, prescaler, clock, freq, hz);
1949	2043	timer_adjust_periodic( s3c24xx->wdt.timer, ATTOTIME_IN_HZ( hz), 0, ATTOTIME_IN_HZ( hz));
	2044	#if defined(DEVICE_S3C2410)
	2045	s3c24xx->wdt.freq = freq;
	2046	s3c24xx->wdt.cnt = s3c24xx->wdt.regs.wtcnt;
	2047	#endif
1950	2048	}
1951	2049
1952	2050	static void s3c24xx_wdt_stop( running_device *device)
1953	2051	{
1954	2052	s3c24xx_t *s3c24xx = get_token( device);
1955	2053	verboselog( device->machine, 1, "WDT stop\n");
	2054	s3c24xx->wdt.regs.wtcnt = s3c24xx_wdt_calc_current_count( device);
1956	2055	timer_adjust_oneshot( s3c24xx->wdt.timer, attotime_never, 0);
1957	2056	}
1958	2057
r9821	r9822
3044	3143	s3c24xx_t *s3c24xx = get_token( device);
3045	3144	s3c24xx->iis.fifo_index = 0;
3046	3145	//  s3c24xx->iic.data_index = 0;
	3146	#if defined(DEVICE_S3C2410) || defined(DEVICE_S3C2440)
	3147	s3c24xx->gpio.regs.gstatus2 = 0x00000001; // Boot is caused by power on reset
	3148	#endif
	3149	s3c24xx->irq.line_irq = s3c24xx->irq.line_fiq = CLEAR_LINE;
3047	3150	}
3048	3151
3049	3152	static DEVICE_START( s3c24xx )

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