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r9785 Saturday 18th December, 2010 at 05:05:36 UTC by Nathan Woods
Converted gameboy to driver_device. [Atari Ace]

[src/mess/audio]	gb.c gb.h*
[src/mess/drivers]	gb.c gba.c pcw.c sapi1.c tx0.c
[src/mess/includes]	cpschngr.h gb.h kc.h pcw.h sapi1.h
[src/mess/machine]	gb.c kc.c
[src/mess/video]	cpschngr.c gb.c

src/mess/audio/gb.c

r9784	r9785
40	40	***************************************************************************************/
41	41
42	42	#include "emu.h"
43		#include "includes/gb.h"
44	43	#include "streams.h"
	44	#include "gb.h"
45	45
46	46
47	47	/***************************************************************************

src/mess/audio/gb.h

r0	r9785
	1	DECLARE_LEGACY_SOUND_DEVICE(GAMEBOY, gameboy_sound);
	2
	3	READ8_DEVICE_HANDLER( gb_sound_r );
	4	WRITE8_DEVICE_HANDLER( gb_sound_w );
	5	READ8_DEVICE_HANDLER( gb_wave_r );
	6	WRITE8_DEVICE_HANDLER( gb_wave_w );

src/mess/machine/gb.c

r9784	r9785
36	36	#define __MACHINE_GB_C
37	37
38	38	#include "emu.h"
39		#include "includes/gb.h"
40	39	#include "cpu/lr35902/lr35902.h"
41	40	#include "devices/cartslot.h"
42	41	#include "devices/messram.h"
43	42	#include "image.h"
	43	#include "audio/gb.h"
	44	#include "includes/gb.h"
44	45
45	46	/* Memory bank controller types */
46	47	enum {
r9784	r9785
66	67	#define CGB_START_VRAM_BANKS   0x0000
67	68	#define CGB_START_RAM_BANKS   ( 2 * 8 * 1024 )
68	69
69		#define MAX_ROMBANK 512
70		#define MAX_RAMBANK 256
	70	#define JOYPAD      state->gb_io[0x00]   /* Joystick: 1.1.P15.P14.P13.P12.P11.P10       */
	71	#define SIODATA      state->gb_io[0x01]   /* Serial IO data buffer                       */
	72	#define SIOCONT      state->gb_io[0x02]   /* Serial IO control register                  */
	73	#define DIVREG      state->gb_io[0x04]   /* Divider register (???)                      */
	74	#define TIMECNT      state->gb_io[0x05]   /* Timer counter. Gen. int. when it overflows  */
	75	#define TIMEMOD      state->gb_io[0x06]   /* New value of TimeCount after it overflows   */
	76	#define TIMEFRQ      state->gb_io[0x07]   /* Timer frequency and start/stop switch       */
71	77
72		#define JOYPAD      gb_driver_data.gb_io[0x00]   /* Joystick: 1.1.P15.P14.P13.P12.P11.P10       */
73		#define SIODATA      gb_driver_data.gb_io[0x01]   /* Serial IO data buffer                       */
74		#define SIOCONT      gb_driver_data.gb_io[0x02]   /* Serial IO control register                  */
75		#define DIVREG      gb_driver_data.gb_io[0x04]   /* Divider register (???)                      */
76		#define TIMECNT      gb_driver_data.gb_io[0x05]   /* Timer counter. Gen. int. when it overflows  */
77		#define TIMEMOD      gb_driver_data.gb_io[0x06]   /* New value of TimeCount after it overflows   */
78		#define TIMEFRQ      gb_driver_data.gb_io[0x07]   /* Timer frequency and start/stop switch       */
79	78
80		UINT8 *sgb_tile_data;
81		UINT16 sgb_pal[128];   /* SGB palette remapping */
82		UINT16 sgb_pal_data[4096];   /* 512 palettes of 4 colours            */
83		UINT8 sgb_pal_map[20][18];   /* Palette tile map                     */
84		UINT8 sgb_tile_map[2048];   /* 32x32 tile map data (0-tile,1-attribute) */
85		UINT8 sgb_window_mask;      /* Current GB screen mask               */
86		UINT8 sgb_hack;            /* Flag set if we're using a hack       */
87	79
88
89		typedef struct _gb_state gb_state;
90		struct _gb_state {
91		UINT8      gb_io[0x10];
92
93		/* Timer related */
94		UINT16      divcount;
95		UINT8      shift;
96		UINT16      shift_cycles;
97		UINT8      triggering_irq;
98		UINT8      reloading;
99
100		/* Serial I/O related */
101		UINT32      SIOCount;            /* Serial I/O counter */
102		emu_timer   *gb_serial_timer;
103
104		/* SGB variables */
105		UINT8      sgb_atf_data[4050];      /* (SGB) Attributes files */
106
107		/* Cartridge/mapper */
108		UINT16      MBCType;            /* MBC type: 0 for none */
109		UINT8      CartType;            /* Cartridge type (battery, ram, rtc, etc) */
110		UINT8      *ROMMap[MAX_ROMBANK];   /* Addresses of ROM banks */
111		UINT16      ROMBank;            /* Index of ROM bank currently used at 4000-7fff */
112		UINT16      ROMBank00;            /* Index of ROM bank currently used at 0000-3fff */
113		UINT8      ROMMask;            /* Mask for the ROM bank number */
114		UINT16      ROMBanks;            /* Total number of ROM banks */
115		UINT8      *RAMMap[MAX_RAMBANK];   /* Addresses of RAM banks */
116		UINT8      RAMBank;            /* Number of RAM bank currently used */
117		UINT8      RAMMask;            /* Mask for the RAM bank number */
118		UINT8      RAMBanks;            /* Total number of RAM banks */
119		UINT8      MBC1Mode;            /* MBC1 ROM/RAM mode */
120		UINT8      *MBC3RTCData;         /* MBC3 RTC data */
121		UINT8      MBC3RTCMap[5];         /* MBC3 RTC banks */
122		UINT8      MBC3RTCBank;         /* MBC3 RTC bank */
123		UINT8      *GBC_RAMMap[8];         /* (CGB) Addresses of internal RAM banks */
124		UINT8      GBC_RAMBank;         /* (CGB) Current CGB RAM bank */
125		UINT8      gbTama5Memory[32];
126		UINT8      gbTama5Byte;
127		UINT8      gbTama5Address;
128		UINT8      gbLastTama5Command;
129		UINT8      *gb_cart;
130		UINT8      *gb_cart_ram;
131		UINT8      *gb_dummy_rom_bank;
132		UINT8      *gb_dummy_ram_bank;
133		};
134
135		static gb_state gb_driver_data;
136
137	80	/*
138	81	Prototypes
139	82	*/
r9784	r9785
172	115
173	116	static void gb_init_regs(running_machine *machine)
174	117	{
	118	gb_state *state = machine->driver_data<gb_state>();
175	119	/* Initialize the registers */
176	120	SIODATA = 0x00;
177	121	SIOCONT = 0x7E;
r9784	r9785
206	150
207	151	static void gb_init(running_machine *machine)
208	152	{
	153	gb_state *state = machine->driver_data<gb_state>();
209	154	address_space *space = cputag_get_address_space( machine, "maincpu", ADDRESS_SPACE_PROGRAM );
210	155
211	156	/* Initialize the memory banks */
212		gb_driver_data.MBC1Mode = 0;
213		gb_driver_data.MBC3RTCBank = 0;
214		gb_driver_data.ROMBank = gb_driver_data.ROMBank00 + 1;
215		gb_driver_data.RAMBank = 0;
	157	state->MBC1Mode = 0;
	158	state->MBC3RTCBank = 0;
	159	state->ROMBank = state->ROMBank00 + 1;
	160	state->RAMBank = 0;
216	161
217		if (gb_driver_data.gb_cart)
	162	if (state->gb_cart)
218	163	{
219		if ( gb_driver_data.MBCType != MBC_MEGADUCK )
	164	if ( state->MBCType != MBC_MEGADUCK )
220	165	{
221		gb_rom16_4000( machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank] );
222		memory_set_bankptr (machine, "bank2", gb_driver_data.RAMMap[gb_driver_data.RAMBank] ? gb_driver_data.RAMMap[gb_driver_data.RAMBank] : gb_driver_data.gb_dummy_ram_bank);
	166	gb_rom16_4000( machine, state->ROMMap[state->ROMBank] );
	167	memory_set_bankptr (machine, "bank2", state->RAMMap[state->RAMBank] ? state->RAMMap[state->RAMBank] : state->gb_dummy_ram_bank);
223	168	}
224	169	else
225	170	{
226		memory_set_bankptr( machine, "bank1", gb_driver_data.ROMMap[gb_driver_data.ROMBank] );
227		memory_set_bankptr( machine, "bank10", gb_driver_data.ROMMap[0] );
	171	memory_set_bankptr( machine, "bank1", state->ROMMap[state->ROMBank] );
	172	memory_set_bankptr( machine, "bank10", state->ROMMap[0] );
228	173	}
229	174	}
230	175
231	176	/* Set handlers based on the Memory Bank Controller in the cart */
232		switch( gb_driver_data.MBCType )
	177	switch( state->MBCType )
233	178	{
234	179	case MBC_NONE:
235	180	break;
r9784	r9785
292	237
293	238	gb_sound_w(space->machine->device("custom"), 0x16, 0x00 );       /* Initialize sound hardware */
294	239
295		gb_driver_data.divcount = 0;
296		gb_driver_data.triggering_irq = 0;
297		gb_driver_data.gb_io[0x07] = 0xF8;      /* Upper bits of TIMEFRQ register are set to 1 */
	240	state->divcount = 0;
	241	state->triggering_irq = 0;
	242	state->gb_io[0x07] = 0xF8;      /* Upper bits of TIMEFRQ register are set to 1 */
298	243	}
299	244
300	245	MACHINE_START( gb )
301	246	{
	247	gb_state *state = machine->driver_data<gb_state>();
302	248	machine->add_notifier(MACHINE_NOTIFY_EXIT, gb_machine_stop);
303	249
304	250	/* Allocate the serial timer, and disable it */
305		gb_driver_data.gb_serial_timer = timer_alloc(machine,  gb_serial_timer_proc , NULL);
306		timer_enable( gb_driver_data.gb_serial_timer, 0 );
	251	state->gb_serial_timer = timer_alloc(machine,  gb_serial_timer_proc , NULL);
	252	timer_enable( state->gb_serial_timer, 0 );
307	253
308	254	MACHINE_START_CALL( gb_video );
309	255	}
310	256
311	257	MACHINE_START( gbc )
312	258	{
	259	gb_state *state = machine->driver_data<gb_state>();
313	260	machine->add_notifier(MACHINE_NOTIFY_EXIT, gb_machine_stop);
314	261
315	262	/* Allocate the serial timer, and disable it */
316		gb_driver_data.gb_serial_timer = timer_alloc(machine,  gb_serial_timer_proc , NULL);
317		timer_enable( gb_driver_data.gb_serial_timer, 0 );
	263	state->gb_serial_timer = timer_alloc(machine,  gb_serial_timer_proc , NULL);
	264	timer_enable( state->gb_serial_timer, 0 );
318	265
319	266	MACHINE_START_CALL( gbc_video );
320	267	}
321	268
322	269	MACHINE_RESET( gb )
323	270	{
	271	gb_state *state = machine->driver_data<gb_state>();
324	272	gb_init(machine);
325	273
326	274	gb_video_reset( machine, GB_VIDEO_DMG );
327	275
328		gb_rom16_0000( machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank00] );
	276	gb_rom16_0000( machine, state->ROMMap[state->ROMBank00] );
329	277
330	278	/* Enable BIOS rom */
331	279	memory_set_bankptr(machine, "bank5", memory_region(machine, "maincpu") );
332	280
333		gb_driver_data.divcount = 0x0004;
	281	state->divcount = 0x0004;
334	282	}
335	283
336	284
337	285	MACHINE_START( sgb )
338	286	{
339		sgb_tile_data = auto_alloc_array_clear(machine, UINT8, 0x2000 );
	287	gb_state *state = machine->driver_data<gb_state>();
	288	state->sgb_tile_data = auto_alloc_array_clear(machine, UINT8, 0x2000 );
340	289
341	290	machine->add_notifier(MACHINE_NOTIFY_EXIT, gb_machine_stop);
342	291
343	292	/* Allocate the serial timer, and disable it */
344		gb_driver_data.gb_serial_timer = timer_alloc(machine,  gb_serial_timer_proc , NULL);
345		timer_enable( gb_driver_data.gb_serial_timer, 0 );
	293	state->gb_serial_timer = timer_alloc(machine,  gb_serial_timer_proc , NULL);
	294	timer_enable( state->gb_serial_timer, 0 );
346	295
347	296	MACHINE_START_CALL( gb_video );
348	297	}
349	298
350	299	MACHINE_RESET( sgb )
351	300	{
	301	gb_state *state = machine->driver_data<gb_state>();
352	302	gb_init(machine);
353	303
354	304	gb_video_reset( machine, GB_VIDEO_SGB );
355	305
356	306	gb_init_regs(machine);
357	307
358		gb_rom16_0000( machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank00] ? gb_driver_data.ROMMap[gb_driver_data.ROMBank00] : gb_driver_data.gb_dummy_rom_bank );
	308	gb_rom16_0000( machine, state->ROMMap[state->ROMBank00] ? state->ROMMap[state->ROMBank00] : state->gb_dummy_rom_bank );
359	309
360	310	/* Enable BIOS rom */
361	311	memory_set_bankptr(machine, "bank5", memory_region(machine, "maincpu") );
362	312
363		memset( sgb_tile_data, 0, 0x2000 );
	313	memset( state->sgb_tile_data, 0, 0x2000 );
364	314
365		sgb_window_mask = 0;
366		memset( sgb_pal_map, 0, sizeof(sgb_pal_map) );
367		memset( gb_driver_data.sgb_atf_data, 0, sizeof(gb_driver_data.sgb_atf_data) );
	315	state->sgb_window_mask = 0;
	316	memset( state->sgb_pal_map, 0, sizeof(state->sgb_pal_map) );
	317	memset( state->sgb_atf_data, 0, sizeof(state->sgb_atf_data) );
368	318
369	319	/* HACKS for Donkey Kong Land 2 + 3.
370	320	For some reason that I haven't figured out, they store the tile
371	321	data differently.  Hacks will go once I figure it out */
372		sgb_hack = 0;
	322	state->sgb_hack = 0;
373	323
374		if (gb_driver_data.gb_cart)   // make sure cart is in
	324	if (state->gb_cart)   // make sure cart is in
375	325	{
376		if( strncmp( (const char*)(gb_driver_data.gb_cart + 0x134), "DONKEYKONGLAND 2", 16 ) == 0 ||
377		strncmp( (const char*)(gb_driver_data.gb_cart + 0x134), "DONKEYKONGLAND 3", 16 ) == 0 )
378		sgb_hack = 1;
	326	if( strncmp( (const char*)(state->gb_cart + 0x134), "DONKEYKONGLAND 2", 16 ) == 0 ||
	327	strncmp( (const char*)(state->gb_cart + 0x134), "DONKEYKONGLAND 3", 16 ) == 0 )
	328	state->sgb_hack = 1;
379	329	}
380	330
381		gb_driver_data.divcount = 0x0004;
	331	state->divcount = 0x0004;
382	332	}
383	333
384	334	MACHINE_RESET( gbpocket )
385	335	{
	336	gb_state *state = machine->driver_data<gb_state>();
386	337	gb_init(machine);
387	338
388	339	gb_video_reset( machine, GB_VIDEO_MGB );
r9784	r9785
395	346	gb_sound_w(machine->device("custom"), 0x14,0x77);
396	347
397	348	/* Enable BIOS rom if we have one */
398		gb_rom16_0000( machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank00] ? gb_driver_data.ROMMap[gb_driver_data.ROMBank00] : gb_driver_data.gb_dummy_rom_bank );
	349	gb_rom16_0000( machine, state->ROMMap[state->ROMBank00] ? state->ROMMap[state->ROMBank00] : state->gb_dummy_rom_bank );
399	350
400		gb_driver_data.divcount = 0xABC8;
	351	state->divcount = 0xABC8;
401	352	}
402	353
403	354	MACHINE_RESET( gbc )
404	355	{
	356	gb_state *state = machine->driver_data<gb_state>();
405	357	int ii;
406	358
407	359	gb_init(machine);
r9784	r9785
410	362
411	363	gb_init_regs(machine);
412	364
413		gb_rom16_0000( machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank00] ? gb_driver_data.ROMMap[gb_driver_data.ROMBank00] : gb_driver_data.gb_dummy_rom_bank );
	365	gb_rom16_0000( machine, state->ROMMap[state->ROMBank00] ? state->ROMMap[state->ROMBank00] : state->gb_dummy_rom_bank );
414	366
415	367	/* Enable BIOS rom */
416	368	memory_set_bankptr(machine, "bank5", memory_region(machine, "maincpu") );
r9784	r9785
419	371	/* Allocate memory for internal ram */
420	372	for( ii = 0; ii < 8; ii++ )
421	373	{
422		gb_driver_data.GBC_RAMMap[ii] = messram_get_ptr(machine->device("messram")) + CGB_START_RAM_BANKS + ii * 0x1000;
423		memset (gb_driver_data.GBC_RAMMap[ii], 0, 0x1000);
	374	state->GBC_RAMMap[ii] = messram_get_ptr(machine->device("messram")) + CGB_START_RAM_BANKS + ii * 0x1000;
	375	memset (state->GBC_RAMMap[ii], 0, 0x1000);
424	376	}
425	377	}
426	378
427	379	static void gb_machine_stop(running_machine &machine)
428	380	{
	381	gb_state *state = machine.driver_data<gb_state>();
429	382	/* Don't save if there was no battery */
430		if(!(gb_driver_data.CartType & BATTERY) || !gb_driver_data.RAMBanks)
	383	if(!(state->CartType & BATTERY) || !state->RAMBanks)
431	384	return;
432	385
433	386	/* NOTE: The reason we save the carts RAM this way instead of using MAME's
434	387	built in macros is because they force the filename to be the name of
435	388	the machine.  We need to have a separate name for each game. */
436	389	device_image_interface *image = dynamic_cast<device_image_interface *>(machine.device("cart"));
437		image->battery_save(gb_driver_data.gb_cart_ram, gb_driver_data.RAMBanks * 0x2000);
	390	image->battery_save(state->gb_cart_ram, state->RAMBanks * 0x2000);
438	391	}
439	392
440	393	static void gb_set_mbc1_banks( running_machine *machine )
441	394	{
442		gb_rom16_4000( machine, gb_driver_data.ROMMap[ gb_driver_data.ROMBank ] );
443		memory_set_bankptr( machine, "bank2", gb_driver_data.RAMMap[ gb_driver_data.MBC1Mode ? ( gb_driver_data.ROMBank >> 5 ) : 0 ] );
	395	gb_state *state = machine->driver_data<gb_state>();
	396	gb_rom16_4000( machine, state->ROMMap[ state->ROMBank ] );
	397	memory_set_bankptr( machine, "bank2", state->RAMMap[ state->MBC1Mode ? ( state->ROMBank >> 5 ) : 0 ] );
444	398	}
445	399
446	400	static WRITE8_HANDLER( gb_rom_bank_select_mbc1 )
447	401	{
	402	gb_state *state = space->machine->driver_data<gb_state>();
448	403	data &= 0x1F; /* Only uses lower 5 bits */
449	404	/* Selecting bank 0 == selecting bank 1 */
450	405	if( data == 0 )
451	406	data = 1;
452	407
453		gb_driver_data.ROMBank = ( gb_driver_data.ROMBank & 0x01E0 ) | data;
	408	state->ROMBank = ( state->ROMBank & 0x01E0 ) | data;
454	409	/* Switch banks */
455	410	gb_set_mbc1_banks( space->machine );
456	411	}
457	412
458	413	static WRITE8_HANDLER( gb_rom_bank_select_mbc2 )
459	414	{
	415	gb_state *state = space->machine->driver_data<gb_state>();
460	416	data &= 0x0F; /* Only uses lower 4 bits */
461	417	/* Selecting bank 0 == selecting bank 1 */
462	418	if( data == 0 )
r9784	r9785
464	420
465	421	/* The least significant bit of the upper address byte must be 1 */
466	422	if( offset & 0x0100 )
467		gb_driver_data.ROMBank = ( gb_driver_data.ROMBank & 0x100 ) | data;
	423	state->ROMBank = ( state->ROMBank & 0x100 ) | data;
468	424	/* Switch banks */
469		gb_rom16_4000( space->machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank] );
	425	gb_rom16_4000( space->machine, state->ROMMap[state->ROMBank] );
470	426	}
471	427
472	428	static WRITE8_HANDLER( gb_rom_bank_select_mbc3 )
473	429	{
	430	gb_state *state = space->machine->driver_data<gb_state>();
474	431	logerror( "0x%04X: write to mbc3 rom bank select register 0x%04X <- 0x%02X\n", cpu_get_pc( space->cpu ), offset, data );
475	432	data &= 0x7F; /* Only uses lower 7 bits */
476	433	/* Selecting bank 0 == selecting bank 1 */
477	434	if( data == 0 )
478	435	data = 1;
479	436
480		gb_driver_data.ROMBank = ( gb_driver_data.ROMBank & 0x0100 ) | data;
	437	state->ROMBank = ( state->ROMBank & 0x0100 ) | data;
481	438	/* Switch banks */
482		gb_rom16_4000( space->machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank] );
	439	gb_rom16_4000( space->machine, state->ROMMap[state->ROMBank] );
483	440	}
484	441
485	442	static WRITE8_HANDLER( gb_rom_bank_select_mbc5 )
486	443	{
	444	gb_state *state = space->machine->driver_data<gb_state>();
487	445	/* MBC5 has a 9 bit bank select
488	446	Writing into 2000-2FFF sets the lower 8 bits
489	447	Writing into 3000-3FFF sets the 9th bit
r9784	r9785
491	449	logerror( "0x%04X: MBC5 ROM Bank select write 0x%04X <- 0x%02X\n", cpu_get_pc( space->cpu ), offset, data );
492	450	if( offset & 0x1000 )
493	451	{
494		gb_driver_data.ROMBank = (gb_driver_data.ROMBank & 0xFF ) | ( ( data & 0x01 ) << 8 );
	452	state->ROMBank = (state->ROMBank & 0xFF ) | ( ( data & 0x01 ) << 8 );
495	453	}
496	454	else
497	455	{
498		gb_driver_data.ROMBank = (gb_driver_data.ROMBank & 0x100 ) | data;
	456	state->ROMBank = (state->ROMBank & 0x100 ) | data;
499	457	}
500	458	/* Switch banks */
501		gb_rom16_4000( space->machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank] );
	459	gb_rom16_4000( space->machine, state->ROMMap[state->ROMBank] );
502	460	}
503	461
504	462	static WRITE8_HANDLER( gb_ram_bank_select_mbc6 )
r9784	r9785
508	466
509	467	static WRITE8_HANDLER( gb_rom_bank_select_mbc6_1 )
510	468	{
	469	gb_state *state = space->machine->driver_data<gb_state>();
511	470	logerror( "0x%04X: write to mbc6 rom area: 0x%04X <- 0x%02X\n", cpu_get_pc( space->cpu ), 0x2000 + offset, data );
512	471	if ( offset & 0x0800 )
513	472	{
514	473	if ( data == 0x00 )
515	474	{
516		gb_rom8_4000( space->machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank>>1] + ( ( gb_driver_data.ROMBank & 0x01 ) ? 0x2000 : 0x0000 ) );
	475	gb_rom8_4000( space->machine, state->ROMMap[state->ROMBank>>1] + ( ( state->ROMBank & 0x01 ) ? 0x2000 : 0x0000 ) );
517	476	}
518	477	}
519	478	else
520	479	{
521		gb_driver_data.ROMBank = data;
	480	state->ROMBank = data;
522	481	}
523	482	}
524	483
525	484	static WRITE8_HANDLER( gb_rom_bank_select_mbc6_2 )
526	485	{
	486	gb_state *state = space->machine->driver_data<gb_state>();
527	487	logerror( "0x%04X: write to mbc6 rom area: 0x%04X <- 0x%02X\n", cpu_get_pc( space->cpu ), 0x3000 + offset, data );
528	488	if ( offset & 0x0800 )
529	489	{
530	490	if ( data == 0x00 )
531	491	{
532		gb_rom8_6000( space->machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank00>>1] + ( ( gb_driver_data.ROMBank00 & 0x01 ) ? 0x2000 : 0x0000 ) );
	492	gb_rom8_6000( space->machine, state->ROMMap[state->ROMBank00>>1] + ( ( state->ROMBank00 & 0x01 ) ? 0x2000 : 0x0000 ) );
533	493	}
534	494	}
535	495	else
536	496	{
537		gb_driver_data.ROMBank00 = data;
	497	state->ROMBank00 = data;
538	498	}
539	499	}
540	500
541	501	static WRITE8_HANDLER( gb_rom_bank_select_mbc7 )
542	502	{
	503	gb_state *state = space->machine->driver_data<gb_state>();
543	504	logerror( "0x%04X: write to mbc7 rom select register: 0x%04X <- 0x%02X\n", cpu_get_pc( space->cpu ), 0x2000 + offset, data );
544	505	/* Bit 12 must be set for writing to the mbc register */
545	506	if ( offset & 0x0100 )
546	507	{
547		gb_driver_data.ROMBank = data;
548		gb_rom16_4000( space->machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank] );
	508	state->ROMBank = data;
	509	gb_rom16_4000( space->machine, state->ROMMap[state->ROMBank] );
549	510	}
550	511	}
551	512
r9784	r9785
569	530
570	531	static WRITE8_HANDLER( gb_rom_bank_select_wisdom )
571	532	{
	533	gb_state *state = space->machine->driver_data<gb_state>();
572	534	logerror( "0x%04X: wisdom tree mapper write to address 0x%04X\n", cpu_get_pc( space->cpu ), offset );
573	535	/* The address determines the bank to select */
574		gb_driver_data.ROMBank = ( offset << 1 ) & 0x1FF;
575		memory_set_bankptr( space->machine, "bank5", gb_driver_data.ROMMap[ gb_driver_data.ROMBank ] );
576		memory_set_bankptr( space->machine, "bank10", gb_driver_data.ROMMap[ gb_driver_data.ROMBank ] + 0x0100 );
577		gb_rom16_4000( space->machine, gb_driver_data.ROMMap[ gb_driver_data.ROMBank + 1 ] );
	536	state->ROMBank = ( offset << 1 ) & 0x1FF;
	537	memory_set_bankptr( space->machine, "bank5", state->ROMMap[ state->ROMBank ] );
	538	memory_set_bankptr( space->machine, "bank10", state->ROMMap[ state->ROMBank ] + 0x0100 );
	539	gb_rom16_4000( space->machine, state->ROMMap[ state->ROMBank + 1 ] );
578	540	}
579	541
580	542	static WRITE8_HANDLER( gb_ram_bank_select_mbc1 )
581	543	{
	544	gb_state *state = space->machine->driver_data<gb_state>();
582	545	data &= 0x3; /* Only uses the lower 2 bits */
583	546
584	547	/* Select the upper bits of the ROMMask */
585		gb_driver_data.ROMBank = ( gb_driver_data.ROMBank & 0x1F ) | ( data << 5 );
	548	state->ROMBank = ( state->ROMBank & 0x1F ) | ( data << 5 );
586	549
587	550	/* Switch banks */
588	551	gb_set_mbc1_banks( space->machine );
r9784	r9785
590	553
591	554	static WRITE8_HANDLER( gb_ram_bank_select_mbc3 )
592	555	{
	556	gb_state *state = space->machine->driver_data<gb_state>();
593	557	logerror( "0x%04X: write mbc3 ram bank select register 0x%04X <- 0x%02X\n", cpu_get_pc( space->cpu ), offset, data );
594	558	if( data & 0x8 )
595	559	{   /* RTC banks */
596		if ( gb_driver_data.CartType & TIMER )
	560	if ( state->CartType & TIMER )
597	561	{
598		gb_driver_data.MBC3RTCBank = data & 0x07;
	562	state->MBC3RTCBank = data & 0x07;
599	563	if ( data < 5 )
600	564	{
601		memset( gb_driver_data.MBC3RTCData, gb_driver_data.MBC3RTCMap[gb_driver_data.MBC3RTCBank], 0x2000 );
602		memory_set_bankptr( space->machine, "bank2", gb_driver_data.MBC3RTCData );
	565	memset( state->MBC3RTCData, state->MBC3RTCMap[state->MBC3RTCBank], 0x2000 );
	566	memory_set_bankptr( space->machine, "bank2", state->MBC3RTCData );
603	567	}
604	568	}
605	569	}
606	570	else
607	571	{   /* RAM banks */
608		gb_driver_data.RAMBank = data & 0x3;
609		gb_driver_data.MBC3RTCBank = 0xFF;
	572	state->RAMBank = data & 0x3;
	573	state->MBC3RTCBank = 0xFF;
610	574	/* Switch banks */
611		memory_set_bankptr( space->machine, "bank2", gb_driver_data.RAMMap[gb_driver_data.RAMBank] );
	575	memory_set_bankptr( space->machine, "bank2", state->RAMMap[state->RAMBank] );
612	576	}
613	577	}
614	578
615	579	static WRITE8_HANDLER( gb_ram_bank_select_mbc5 )
616	580	{
	581	gb_state *state = space->machine->driver_data<gb_state>();
617	582	logerror( "0x%04X: MBC5 RAM Bank select write 0x%04X <- 0x%02X\n", cpu_get_pc( space->cpu ), offset, data );
618	583	data &= 0x0F;
619		if( gb_driver_data.CartType & RUMBLE )
	584	if( state->CartType & RUMBLE )
620	585	{
621	586	data &= 0x7;
622	587	}
623		gb_driver_data.RAMBank = data;
	588	state->RAMBank = data;
624	589	/* Switch banks */
625		memory_set_bankptr (space->machine, "bank2", gb_driver_data.RAMMap[gb_driver_data.RAMBank] );
	590	memory_set_bankptr (space->machine, "bank2", state->RAMMap[state->RAMBank] );
626	591	}
627	592
628	593	WRITE8_HANDLER ( gb_ram_enable )
r9784	r9785
634	599
635	600	static WRITE8_HANDLER( gb_mem_mode_select_mbc1 )
636	601	{
637		gb_driver_data.MBC1Mode = data & 0x1;
	602	gb_state *state = space->machine->driver_data<gb_state>();
	603	state->MBC1Mode = data & 0x1;
638	604	gb_set_mbc1_banks( space->machine );
639	605	}
640	606
641	607	static WRITE8_HANDLER( gb_mem_mode_select_mbc3 )
642	608	{
	609	gb_state *state = space->machine->driver_data<gb_state>();
643	610	logerror( "0x%04X: Write to mbc3 mem mode select register 0x%04X <- 0x%02X\n", cpu_get_pc( space->cpu ), offset, data );
644		if( gb_driver_data.CartType & TIMER )
	611	if( state->CartType & TIMER )
645	612	{
646	613	/* FIXME: RTC Latch goes here */
647		gb_driver_data.MBC3RTCMap[0] = 50;    /* Seconds */
648		gb_driver_data.MBC3RTCMap[1] = 40;    /* Minutes */
649		gb_driver_data.MBC3RTCMap[2] = 15;    /* Hours */
650		gb_driver_data.MBC3RTCMap[3] = 25;    /* Day counter lowest 8 bits */
651		gb_driver_data.MBC3RTCMap[4] = 0x01;  /* Day counter upper bit, timer off, no day overflow occured (bit7) */
	614	state->MBC3RTCMap[0] = 50;    /* Seconds */
	615	state->MBC3RTCMap[1] = 40;    /* Minutes */
	616	state->MBC3RTCMap[2] = 15;    /* Hours */
	617	state->MBC3RTCMap[3] = 25;    /* Day counter lowest 8 bits */
	618	state->MBC3RTCMap[4] = 0x01;  /* Day counter upper bit, timer off, no day overflow occured (bit7) */
652	619	}
653	620	}
654	621
655	622	static WRITE8_HANDLER( gb_ram_tama5 )
656	623	{
	624	gb_state *state = space->machine->driver_data<gb_state>();
657	625	logerror( "0x%04X: TAMA5 write 0x%04X <- 0x%02X\n", cpu_get_pc( space->cpu ), 0xA000 + offset, data );
658	626	switch( offset & 0x0001 )
659	627	{
660	628	case 0x0000:    /* Write to data register */
661		switch( gb_driver_data.gbLastTama5Command )
	629	switch( state->gbLastTama5Command )
662	630	{
663	631	case 0x00:      /* Bits 0-3 for rom bank selection */
664		gb_driver_data.ROMBank = ( gb_driver_data.ROMBank & 0xF0 ) | ( data & 0x0F );
665		gb_rom16_4000( space->machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank] );
	632	state->ROMBank = ( state->ROMBank & 0xF0 ) | ( data & 0x0F );
	633	gb_rom16_4000( space->machine, state->ROMMap[state->ROMBank] );
666	634	break;
667	635	case 0x01:      /* Bit 4(-7?) for rom bank selection */
668		gb_driver_data.ROMBank = ( gb_driver_data.ROMBank & 0x0F ) | ( ( data & 0x0F ) << 4 );
669		gb_rom16_4000( space->machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank] );
	636	state->ROMBank = ( state->ROMBank & 0x0F ) | ( ( data & 0x0F ) << 4 );
	637	gb_rom16_4000( space->machine, state->ROMMap[state->ROMBank] );
670	638	break;
671	639	case 0x04:      /* Data to write lo */
672		gb_driver_data.gbTama5Byte = ( gb_driver_data.gbTama5Byte & 0xF0 ) | ( data & 0x0F );
	640	state->gbTama5Byte = ( state->gbTama5Byte & 0xF0 ) | ( data & 0x0F );
673	641	break;
674	642	case 0x05:      /* Data to write hi */
675		gb_driver_data.gbTama5Byte = ( gb_driver_data.gbTama5Byte & 0x0F ) | ( ( data & 0x0F ) << 4 );
	643	state->gbTama5Byte = ( state->gbTama5Byte & 0x0F ) | ( ( data & 0x0F ) << 4 );
676	644	break;
677	645	case 0x06:      /* Address selection hi */
678		gb_driver_data.gbTama5Address = ( gb_driver_data.gbTama5Address & 0x0F ) | ( ( data & 0x0F ) << 4 );
	646	state->gbTama5Address = ( state->gbTama5Address & 0x0F ) | ( ( data & 0x0F ) << 4 );
679	647	break;
680	648	case 0x07:      /* Address selection lo */
681	649	/* This address always seems to written last, so we'll just
682	650	execute the command here */
683		gb_driver_data.gbTama5Address = ( gb_driver_data.gbTama5Address & 0xF0 ) | ( data & 0x0F );
684		switch ( gb_driver_data.gbTama5Address & 0xE0 )
	651	state->gbTama5Address = ( state->gbTama5Address & 0xF0 ) | ( data & 0x0F );
	652	switch ( state->gbTama5Address & 0xE0 )
685	653	{
686	654	case 0x00:      /* Write memory */
687		logerror( "Write tama5 memory 0x%02X <- 0x%02X\n", gb_driver_data.gbTama5Address & 0x1F, gb_driver_data.gbTama5Byte );
688		gb_driver_data.gbTama5Memory[ gb_driver_data.gbTama5Address & 0x1F ] = gb_driver_data.gbTama5Byte;
	655	logerror( "Write tama5 memory 0x%02X <- 0x%02X\n", state->gbTama5Address & 0x1F, state->gbTama5Byte );
	656	state->gbTama5Memory[ state->gbTama5Address & 0x1F ] = state->gbTama5Byte;
689	657	break;
690	658	case 0x20:      /* Read memory */
691		logerror( "Read tama5 memory 0x%02X\n", gb_driver_data.gbTama5Address & 0x1F );
692		gb_driver_data.gbTama5Byte = gb_driver_data.gbTama5Memory[ gb_driver_data.gbTama5Address & 0x1F ];
	659	logerror( "Read tama5 memory 0x%02X\n", state->gbTama5Address & 0x1F );
	660	state->gbTama5Byte = state->gbTama5Memory[ state->gbTama5Address & 0x1F ];
693	661	break;
694	662	case 0x40:      /* Unknown, some kind of read */
695		if ( ( gb_driver_data.gbTama5Address & 0x1F ) == 0x12 )
	663	if ( ( state->gbTama5Address & 0x1F ) == 0x12 )
696	664	{
697		gb_driver_data.gbTama5Byte = 0xFF;
	665	state->gbTama5Byte = 0xFF;
698	666	}
699	667	case 0x80:      /* Unknown, some kind of read (when 07=01)/write (when 07=00/02) */
700	668	default:
r9784	r9785
715	683	case 0x07:      /* Address register lo */
716	684	break;
717	685	case 0x0A:      /* Are we ready for the next command? */
718		gb_driver_data.MBC3RTCData[0] = 0x01;
719		memory_set_bankptr( space->machine, "bank2", gb_driver_data.MBC3RTCData );
	686	state->MBC3RTCData[0] = 0x01;
	687	memory_set_bankptr( space->machine, "bank2", state->MBC3RTCData );
720	688	break;
721	689	case 0x0C:      /* Data read register lo */
722		gb_driver_data.MBC3RTCData[0] = gb_driver_data.gbTama5Byte & 0x0F;
	690	state->MBC3RTCData[0] = state->gbTama5Byte & 0x0F;
723	691	break;
724	692	case 0x0D:      /* Data read register hi */
725		gb_driver_data.MBC3RTCData[0] = ( gb_driver_data.gbTama5Byte & 0xF0 ) >> 4;
	693	state->MBC3RTCData[0] = ( state->gbTama5Byte & 0xF0 ) >> 4;
726	694	break;
727	695	default:
728	696	logerror( "0x%04X: Unknown tama5 command 0x%02X\n", cpu_get_pc( space->cpu ), data );
729	697	break;
730	698	}
731		gb_driver_data.gbLastTama5Command = data;
	699	state->gbLastTama5Command = data;
732	700	break;
733	701	}
734	702	}
735	703
736	704	/* This mmm01 implementation is mostly guess work, no clue how correct it all is */
737	705
738		static UINT8 mmm01_bank_offset;
739		static UINT8 mmm01_reg1;
740		static UINT8 mmm01_bank;
741		static UINT8 mmm01_bank_mask;
742	706
743	707	static WRITE8_HANDLER( gb_rom_bank_mmm01_0000_w )
744	708	{
	709	gb_state *state = space->machine->driver_data<gb_state>();
745	710	logerror( "0x%04X: write 0x%02X to 0x%04X\n", cpu_get_pc( space->cpu ), data, offset+0x000 );
746	711	if ( data & 0x40 )
747	712	{
748		mmm01_bank_offset = mmm01_reg1;
749		memory_set_bankptr( space->machine, "bank5", gb_driver_data.ROMMap[ mmm01_bank_offset ] );
750		memory_set_bankptr( space->machine, "bank10", gb_driver_data.ROMMap[ mmm01_bank_offset ] + 0x0100 );
751		gb_rom16_4000( space->machine, gb_driver_data.ROMMap[ mmm01_bank_offset + mmm01_bank ] );
	713	state->mmm01_bank_offset = state->mmm01_reg1;
	714	memory_set_bankptr( space->machine, "bank5", state->ROMMap[ state->mmm01_bank_offset ] );
	715	memory_set_bankptr( space->machine, "bank10", state->ROMMap[ state->mmm01_bank_offset ] + 0x0100 );
	716	gb_rom16_4000( space->machine, state->ROMMap[ state->mmm01_bank_offset + state->mmm01_bank ] );
752	717	}
753	718	}
754	719
755	720	static WRITE8_HANDLER( gb_rom_bank_mmm01_2000_w )
756	721	{
	722	gb_state *state = space->machine->driver_data<gb_state>();
757	723	logerror( "0x%04X: write 0x%02X to 0x%04X\n", cpu_get_pc( space->cpu ), data, offset+0x2000 );
758	724
759		mmm01_reg1 = data & gb_driver_data.ROMMask;
760		mmm01_bank = mmm01_reg1 & mmm01_bank_mask;
761		if ( mmm01_bank == 0 )
	725	state->mmm01_reg1 = data & state->ROMMask;
	726	state->mmm01_bank = state->mmm01_reg1 & state->mmm01_bank_mask;
	727	if ( state->mmm01_bank == 0 )
762	728	{
763		mmm01_bank = 1;
	729	state->mmm01_bank = 1;
764	730	}
765		gb_rom16_4000( space->machine, gb_driver_data.ROMMap[ mmm01_bank_offset + mmm01_bank ] );
	731	gb_rom16_4000( space->machine, state->ROMMap[ state->mmm01_bank_offset + state->mmm01_bank ] );
766	732	}
767	733
768	734	static WRITE8_HANDLER( gb_rom_bank_mmm01_4000_w )
r9784	r9785
772	738
773	739	static WRITE8_HANDLER( gb_rom_bank_mmm01_6000_w )
774	740	{
	741	gb_state *state = space->machine->driver_data<gb_state>();
775	742	logerror( "0x%04X: write 0x%02X to 0x%04X\n", cpu_get_pc( space->cpu ), data, offset+0x6000 );
776	743	/* Not sure if this is correct, Taito Variety Pack sets these values */
777	744	/* Momotarou Collection 2 writes 01 and 21 here */
778	745	switch( data )
779	746	{
780		case 0x30:   mmm01_bank_mask = 0x07;   break;
781		case 0x38:   mmm01_bank_mask = 0x03;   break;
782		default:   mmm01_bank_mask = 0xFF; break;
	747	case 0x30:   state->mmm01_bank_mask = 0x07;   break;
	748	case 0x38:   state->mmm01_bank_mask = 0x03;   break;
	749	default:   state->mmm01_bank_mask = 0xFF; break;
783	750	}
784	751	}
785	752
r9784	r9785
787	754
788	755	static void gb_set_mbc1_kor_banks( running_machine *machine )
789	756	{
790		if ( gb_driver_data.ROMBank & 0x30 )
	757	gb_state *state = machine->driver_data<gb_state>();
	758	if ( state->ROMBank & 0x30 )
791	759	{
792		gb_rom16_0000( machine, gb_driver_data.ROMMap[ gb_driver_data.ROMBank & 0x30 ] );
	760	gb_rom16_0000( machine, state->ROMMap[ state->ROMBank & 0x30 ] );
793	761	}
794		gb_rom16_4000( machine, gb_driver_data.ROMMap[ gb_driver_data.ROMBank ] );
795		memory_set_bankptr( machine, "bank2", gb_driver_data.RAMMap[ gb_driver_data.MBC1Mode ? ( gb_driver_data.ROMBank >> 5 ) : 0 ] );
	762	gb_rom16_4000( machine, state->ROMMap[ state->ROMBank ] );
	763	memory_set_bankptr( machine, "bank2", state->RAMMap[ state->MBC1Mode ? ( state->ROMBank >> 5 ) : 0 ] );
796	764	}
797	765
798	766	static WRITE8_HANDLER( gb_rom_bank_select_mbc1_kor )
799	767	{
	768	gb_state *state = space->machine->driver_data<gb_state>();
800	769	data &= 0x0F; /* Only uses lower 5 bits */
801	770	/* Selecting bank 0 == selecting bank 1 */
802	771	if( data == 0 )
803	772	data = 1;
804	773
805		gb_driver_data.ROMBank = ( gb_driver_data.ROMBank & 0x01F0 ) | data;
	774	state->ROMBank = ( state->ROMBank & 0x01F0 ) | data;
806	775	/* Switch banks */
807	776	gb_set_mbc1_kor_banks( space->machine );
808	777	}
809	778
810	779	static WRITE8_HANDLER( gb_ram_bank_select_mbc1_kor )
811	780	{
	781	gb_state *state = space->machine->driver_data<gb_state>();
812	782	data &= 0x3; /* Only uses the lower 2 bits */
813	783
814	784	/* Select the upper bits of the ROMMask */
815		gb_driver_data.ROMBank = ( gb_driver_data.ROMBank & 0x0F ) | ( data << 4 );
	785	state->ROMBank = ( state->ROMBank & 0x0F ) | ( data << 4 );
816	786
817	787	/* Switch banks */
818	788	gb_set_mbc1_kor_banks( space->machine );
r9784	r9785
820	790
821	791	static WRITE8_HANDLER( gb_mem_mode_select_mbc1_kor )
822	792	{
823		gb_driver_data.MBC1Mode = data & 0x1;
	793	gb_state *state = space->machine->driver_data<gb_state>();
	794	state->MBC1Mode = data & 0x1;
824	795	gb_set_mbc1_kor_banks( space->machine );
825	796	}
826	797
827	798	WRITE8_HANDLER ( gb_io_w )
828	799	{
	800	gb_state *state = space->machine->driver_data<gb_state>();
829	801	static const UINT8 timer_shifts[4] = {10, 4, 6, 8};
830	802
831	803	switch (offset)
r9784	r9785
845	817	case 0x00:
846	818	case 0x01:
847	819	case 0x80:            /* enabled & external clock */
848		gb_driver_data.SIOCount = 0;
	820	state->SIOCount = 0;
849	821	break;
850	822	case 0x81:            /* enabled & internal clock */
851	823	SIODATA = 0xFF;
852		gb_driver_data.SIOCount = 8;
853		timer_adjust_periodic(gb_driver_data.gb_serial_timer, space->machine->device<cpu_device>("maincpu")->cycles_to_attotime(512), 0, space->machine->device<cpu_device>("maincpu")->cycles_to_attotime(512));
854		timer_enable( gb_driver_data.gb_serial_timer, 1 );
	824	state->SIOCount = 8;
	825	timer_adjust_periodic(state->gb_serial_timer, space->machine->device<cpu_device>("maincpu")->cycles_to_attotime(512), 0, space->machine->device<cpu_device>("maincpu")->cycles_to_attotime(512));
	826	timer_enable( state->gb_serial_timer, 1 );
855	827	break;
856	828	}
857	829	break;
858	830	case 0x04:                  /* DIV - Divider register */
859	831	/* Force increment of TIMECNT register */
860		if ( gb_driver_data.divcount >= 16 )
	832	if ( state->divcount >= 16 )
861	833	gb_timer_increment(space->machine);
862		gb_driver_data.divcount = 0;
	834	state->divcount = 0;
863	835	return;
864	836	case 0x05:                  /* TIMA - Timer counter */
865	837	/* Check if the counter is being reloaded in this cycle */
866		if ( gb_driver_data.reloading && ( gb_driver_data.divcount & ( gb_driver_data.shift_cycles - 1 ) ) == 4 )
	838	if ( state->reloading && ( state->divcount & ( state->shift_cycles - 1 ) ) == 4 )
867	839	{
868	840	data = TIMECNT;
869	841	}
870	842	break;
871	843	case 0x06:                  /* TMA - Timer module */
872	844	/* Check if the counter is being reloaded in this cycle */
873		if ( gb_driver_data.reloading && ( gb_driver_data.divcount & ( gb_driver_data.shift_cycles - 1 ) ) == 4 )
	845	if ( state->reloading && ( state->divcount & ( state->shift_cycles - 1 ) ) == 4 )
874	846	{
875	847	TIMECNT = data;
876	848	}
r9784	r9785
881	853	if ( ( ! ( data & 0x04 ) && ( TIMEFRQ & 0x04 ) ) || ( ( data & 0x04 ) && ( TIMEFRQ & 0x04 ) && ( data & 0x03 ) != ( TIMEFRQ & 0x03 ) ) )
882	854	{
883	855	/* Check if TIMECNT should be incremented */
884		if ( ( gb_driver_data.divcount & ( gb_driver_data.shift_cycles - 1 ) ) >= ( gb_driver_data.shift_cycles >> 1 ) )
	856	if ( ( state->divcount & ( state->shift_cycles - 1 ) ) >= ( state->shift_cycles >> 1 ) )
885	857	{
886	858	gb_timer_increment(space->machine);
887	859	}
888	860	}
889		gb_driver_data.shift = timer_shifts[data & 0x03];
890		gb_driver_data.shift_cycles = 1 << gb_driver_data.shift;
	861	state->shift = timer_shifts[data & 0x03];
	862	state->shift_cycles = 1 << state->shift;
891	863	break;
892	864	case 0x0F:                  /* IF - Interrupt flag */
893	865	data &= 0x1F;
r9784	r9785
895	867	break;
896	868	}
897	869
898		gb_driver_data.gb_io[offset] = data;
	870	state->gb_io[offset] = data;
899	871	}
900	872
901	873	WRITE8_HANDLER ( gb_io2_w )
902	874	{
	875	gb_state *state = space->machine->driver_data<gb_state>();
903	876	if ( offset == 0x10 )
904	877	{
905	878	/* disable BIOS ROM */
906		gb_rom16_0000( space->machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank00] );
	879	gb_rom16_0000( space->machine, state->ROMMap[state->ROMBank00] );
907	880	}
908	881	else
909	882	{
r9784	r9785
945	918
946	919	WRITE8_HANDLER ( sgb_io_w )
947	920	{
	921	gb_state *state = space->machine->driver_data<gb_state>();
948	922	static UINT8 sgb_bitcount = 0, sgb_bytecount = 0, sgb_start = 0, sgb_rest = 0;
949	923	static UINT8 sgb_controller_no = 0, sgb_controller_mode = 0;
950	924	static INT8 sgb_packets = -1;
r9784	r9785
1008	982	switch( sgb_data[0] >> 3 )
1009	983	{
1010	984	case 0x00:   /* PAL01 */
1011		sgb_pal[0*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1012		sgb_pal[0*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
1013		sgb_pal[0*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
1014		sgb_pal[0*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
1015		sgb_pal[1*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1016		sgb_pal[1*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
1017		sgb_pal[1*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
1018		sgb_pal[1*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
	985	state->sgb_pal[0*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	986	state->sgb_pal[0*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
	987	state->sgb_pal[0*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
	988	state->sgb_pal[0*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
	989	state->sgb_pal[1*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	990	state->sgb_pal[1*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
	991	state->sgb_pal[1*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
	992	state->sgb_pal[1*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
1019	993	break;
1020	994	case 0x01:   /* PAL23 */
1021		sgb_pal[2*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1022		sgb_pal[2*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
1023		sgb_pal[2*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
1024		sgb_pal[2*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
1025		sgb_pal[3*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1026		sgb_pal[3*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
1027		sgb_pal[3*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
1028		sgb_pal[3*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
	995	state->sgb_pal[2*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	996	state->sgb_pal[2*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
	997	state->sgb_pal[2*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
	998	state->sgb_pal[2*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
	999	state->sgb_pal[3*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	1000	state->sgb_pal[3*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
	1001	state->sgb_pal[3*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
	1002	state->sgb_pal[3*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
1029	1003	break;
1030	1004	case 0x02:   /* PAL03 */
1031		sgb_pal[0*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1032		sgb_pal[0*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
1033		sgb_pal[0*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
1034		sgb_pal[0*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
1035		sgb_pal[3*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1036		sgb_pal[3*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
1037		sgb_pal[3*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
1038		sgb_pal[3*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
	1005	state->sgb_pal[0*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	1006	state->sgb_pal[0*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
	1007	state->sgb_pal[0*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
	1008	state->sgb_pal[0*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
	1009	state->sgb_pal[3*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	1010	state->sgb_pal[3*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
	1011	state->sgb_pal[3*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
	1012	state->sgb_pal[3*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
1039	1013	break;
1040	1014	case 0x03:   /* PAL12 */
1041		sgb_pal[1*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1042		sgb_pal[1*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
1043		sgb_pal[1*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
1044		sgb_pal[1*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
1045		sgb_pal[2*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
1046		sgb_pal[2*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
1047		sgb_pal[2*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
1048		sgb_pal[2*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
	1015	state->sgb_pal[1*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	1016	state->sgb_pal[1*4 + 1] = sgb_data[3] | (sgb_data[4] << 8);
	1017	state->sgb_pal[1*4 + 2] = sgb_data[5] | (sgb_data[6] << 8);
	1018	state->sgb_pal[1*4 + 3] = sgb_data[7] | (sgb_data[8] << 8);
	1019	state->sgb_pal[2*4 + 0] = sgb_data[1] | (sgb_data[2] << 8);
	1020	state->sgb_pal[2*4 + 1] = sgb_data[9] | (sgb_data[10] << 8);
	1021	state->sgb_pal[2*4 + 2] = sgb_data[11] | (sgb_data[12] << 8);
	1022	state->sgb_pal[2*4 + 3] = sgb_data[13] | (sgb_data[14] << 8);
1049	1023	break;
1050	1024	case 0x04:   /* ATTR_BLK */
1051	1025	{
r9784	r9785
1059	1033	{
1060	1034	for( J = sgb_data[o + 5]; J <= sgb_data[o + 7]; J++ )
1061	1035	{
1062		sgb_pal_map[I][J] = sgb_data[o + 3] & 0x3;
	1036	state->sgb_pal_map[I][J] = sgb_data[o + 3] & 0x3;
1063	1037	}
1064	1038	}
1065	1039	}
r9784	r9785
1077	1051	{
1078	1052	for( J = 0; J < 20; J++ )
1079	1053	{
1080		sgb_pal_map[J][sgb_data[K + 1] & 0x1f] = (sgb_data[K + 1] & 0x60) >> 5;
	1054	state->sgb_pal_map[J][sgb_data[K + 1] & 0x1f] = (sgb_data[K + 1] & 0x60) >> 5;
1081	1055	}
1082	1056	}
1083	1057	else
1084	1058	{
1085	1059	for( J = 0; J < 18; J++ )
1086	1060	{
1087		sgb_pal_map[sgb_data[K + 1] & 0x1f][J] = (sgb_data[K + 1] & 0x60) >> 5;
	1061	state->sgb_pal_map[sgb_data[K + 1] & 0x1f][J] = (sgb_data[K + 1] & 0x60) >> 5;
1088	1062	}
1089	1063	}
1090	1064	}
r9784	r9785
1099	1073	{
1100	1074	for( J = 0; J < 20; J++ )
1101	1075	{
1102		sgb_pal_map[J][I] = (sgb_data[1] & 0xC) >> 2;
	1076	state->sgb_pal_map[J][I] = (sgb_data[1] & 0xC) >> 2;
1103	1077	}
1104	1078	}
1105	1079	for( J = 0; J < 20; J++ )
1106	1080	{
1107		sgb_pal_map[J][sgb_data[2]] = (sgb_data[1] & 0x30) >> 4;
	1081	state->sgb_pal_map[J][sgb_data[2]] = (sgb_data[1] & 0x30) >> 4;
1108	1082	}
1109	1083	for( I = sgb_data[2] + 1; I < 18; I++ )
1110	1084	{
1111	1085	for( J = 0; J < 20; J++ )
1112	1086	{
1113		sgb_pal_map[J][I] = sgb_data[1] & 0x3;
	1087	state->sgb_pal_map[J][I] = sgb_data[1] & 0x3;
1114	1088	}
1115	1089	}
1116	1090	}
r9784	r9785
1120	1094	{
1121	1095	for( J = 0; J < 18; J++ )
1122	1096	{
1123		sgb_pal_map[I][J] = (sgb_data[1] & 0xC) >> 2;
	1097	state->sgb_pal_map[I][J] = (sgb_data[1] & 0xC) >> 2;
1124	1098	}
1125	1099	}
1126	1100	for( J = 0; J < 18; J++ )
1127	1101	{
1128		sgb_pal_map[sgb_data[2]][J] = (sgb_data[1] & 0x30) >> 4;
	1102	state->sgb_pal_map[sgb_data[2]][J] = (sgb_data[1] & 0x30) >> 4;
1129	1103	}
1130	1104	for( I = sgb_data[2] + 1; I < 20; I++ )
1131	1105	{
1132	1106	for( J = 0; J < 18; J++ )
1133	1107	{
1134		sgb_pal_map[I][J] = sgb_data[1] & 0x3;
	1108	state->sgb_pal_map[I][J] = sgb_data[1] & 0x3;
1135	1109	}
1136	1110	}
1137	1111	}
r9784	r9785
1152	1126	{
1153	1127	for( I = 6; I < sets; I++ )
1154	1128	{
1155		sgb_pal_map[x][y++] = (sgb_data[I] & 0xC0) >> 6;
	1129	state->sgb_pal_map[x][y++] = (sgb_data[I] & 0xC0) >> 6;
1156	1130	if( y > 17 )
1157	1131	{
1158	1132	y = 0;
r9784	r9785
1161	1135	x = 0;
1162	1136	}
1163	1137
1164		sgb_pal_map[x][y++] = (sgb_data[I] & 0x30) >> 4;
	1138	state->sgb_pal_map[x][y++] = (sgb_data[I] & 0x30) >> 4;
1165	1139	if( y > 17 )
1166	1140	{
1167	1141	y = 0;
r9784	r9785
1170	1144	x = 0;
1171	1145	}
1172	1146
1173		sgb_pal_map[x][y++] = (sgb_data[I] & 0xC) >> 2;
	1147	state->sgb_pal_map[x][y++] = (sgb_data[I] & 0xC) >> 2;
1174	1148	if( y > 17 )
1175	1149	{
1176	1150	y = 0;
r9784	r9785
1179	1153	x = 0;
1180	1154	}
1181	1155
1182		sgb_pal_map[x][y++] = sgb_data[I] & 0x3;
	1156	state->sgb_pal_map[x][y++] = sgb_data[I] & 0x3;
1183	1157	if( y > 17 )
1184	1158	{
1185	1159	y = 0;
r9784	r9785
1193	1167	{
1194	1168	for( I = 6; I < sets; I++ )
1195	1169	{
1196		sgb_pal_map[x++][y] = (sgb_data[I] & 0xC0) >> 6;
	1170	state->sgb_pal_map[x++][y] = (sgb_data[I] & 0xC0) >> 6;
1197	1171	if( x > 19 )
1198	1172	{
1199	1173	x = 0;
r9784	r9785
1202	1176	y = 0;
1203	1177	}
1204	1178
1205		sgb_pal_map[x++][y] = (sgb_data[I] & 0x30) >> 4;
	1179	state->sgb_pal_map[x++][y] = (sgb_data[I] & 0x30) >> 4;
1206	1180	if( x > 19 )
1207	1181	{
1208	1182	x = 0;
r9784	r9785
1211	1185	y = 0;
1212	1186	}
1213	1187
1214		sgb_pal_map[x++][y] = (sgb_data[I] & 0xC) >> 2;
	1188	state->sgb_pal_map[x++][y] = (sgb_data[I] & 0xC) >> 2;
1215	1189	if( x > 19 )
1216	1190	{
1217	1191	x = 0;
r9784	r9785
1220	1194	y = 0;
1221	1195	}
1222	1196
1223		sgb_pal_map[x++][y] = sgb_data[I] & 0x3;
	1197	state->sgb_pal_map[x++][y] = sgb_data[I] & 0x3;
1224	1198	if( x > 19 )
1225	1199	{
1226	1200	x = 0;
r9784	r9785
1247	1221
1248	1222	/* Palette 0 */
1249	1223	index_ = (UINT16)(sgb_data[1] | (sgb_data[2] << 8)) * 4;
1250		sgb_pal[0] = sgb_pal_data[index_];
1251		sgb_pal[1] = sgb_pal_data[index_ + 1];
1252		sgb_pal[2] = sgb_pal_data[index_ + 2];
1253		sgb_pal[3] = sgb_pal_data[index_ + 3];
	1224	state->sgb_pal[0] = state->sgb_pal_data[index_];
	1225	state->sgb_pal[1] = state->sgb_pal_data[index_ + 1];
	1226	state->sgb_pal[2] = state->sgb_pal_data[index_ + 2];
	1227	state->sgb_pal[3] = state->sgb_pal_data[index_ + 3];
1254	1228	/* Palette 1 */
1255	1229	index_ = (UINT16)(sgb_data[3] | (sgb_data[4] << 8)) * 4;
1256		sgb_pal[4] = sgb_pal_data[index_];
1257		sgb_pal[5] = sgb_pal_data[index_ + 1];
1258		sgb_pal[6] = sgb_pal_data[index_ + 2];
1259		sgb_pal[7] = sgb_pal_data[index_ + 3];
	1230	state->sgb_pal[4] = state->sgb_pal_data[index_];
	1231	state->sgb_pal[5] = state->sgb_pal_data[index_ + 1];
	1232	state->sgb_pal[6] = state->sgb_pal_data[index_ + 2];
	1233	state->sgb_pal[7] = state->sgb_pal_data[index_ + 3];
1260	1234	/* Palette 2 */
1261	1235	index_ = (UINT16)(sgb_data[5] | (sgb_data[6] << 8)) * 4;
1262		sgb_pal[8] = sgb_pal_data[index_];
1263		sgb_pal[9] = sgb_pal_data[index_ + 1];
1264		sgb_pal[10] = sgb_pal_data[index_ + 2];
1265		sgb_pal[11] = sgb_pal_data[index_ + 3];
	1236	state->sgb_pal[8] = state->sgb_pal_data[index_];
	1237	state->sgb_pal[9] = state->sgb_pal_data[index_ + 1];
	1238	state->sgb_pal[10] = state->sgb_pal_data[index_ + 2];
	1239	state->sgb_pal[11] = state->sgb_pal_data[index_ + 3];
1266	1240	/* Palette 3 */
1267	1241	index_ = (UINT16)(sgb_data[7] | (sgb_data[8] << 8)) * 4;
1268		sgb_pal[12] = sgb_pal_data[index_];
1269		sgb_pal[13] = sgb_pal_data[index_ + 1];
1270		sgb_pal[14] = sgb_pal_data[index_ + 2];
1271		sgb_pal[15] = sgb_pal_data[index_ + 3];
	1242	state->sgb_pal[12] = state->sgb_pal_data[index_];
	1243	state->sgb_pal[13] = state->sgb_pal_data[index_ + 1];
	1244	state->sgb_pal[14] = state->sgb_pal_data[index_ + 2];
	1245	state->sgb_pal[15] = state->sgb_pal_data[index_ + 3];
1272	1246	/* Attribute File */
1273	1247	if( sgb_data[9] & 0x40 )
1274		sgb_window_mask = 0;
	1248	state->sgb_window_mask = 0;
1275	1249	sgb_atf = (sgb_data[9] & 0x3f) * (18 * 5);
1276	1250	if( sgb_data[9] & 0x80 )
1277	1251	{
r9784	r9785
1279	1253	{
1280	1254	for( I = 0; I < 5; I++ )
1281	1255	{
1282		sgb_pal_map[I * 4][J] = (gb_driver_data.sgb_atf_data[(J * 5) + sgb_atf + I] & 0xC0) >> 6;
1283		sgb_pal_map[(I * 4) + 1][J] = (gb_driver_data.sgb_atf_data[(J * 5) + sgb_atf + I] & 0x30) >> 4;
1284		sgb_pal_map[(I * 4) + 2][J] = (gb_driver_data.sgb_atf_data[(J * 5) + sgb_atf + I] & 0xC) >> 2;
1285		sgb_pal_map[(I * 4) + 3][J] = gb_driver_data.sgb_atf_data[(J * 5) + sgb_atf + I] & 0x3;
	1256	state->sgb_pal_map[I * 4][J] = (state->sgb_atf_data[(J * 5) + sgb_atf + I] & 0xC0) >> 6;
	1257	state->sgb_pal_map[(I * 4) + 1][J] = (state->sgb_atf_data[(J * 5) + sgb_atf + I] & 0x30) >> 4;
	1258	state->sgb_pal_map[(I * 4) + 2][J] = (state->sgb_atf_data[(J * 5) + sgb_atf + I] & 0xC) >> 2;
	1259	state->sgb_pal_map[(I * 4) + 3][J] = state->sgb_atf_data[(J * 5) + sgb_atf + I] & 0x3;
1286	1260	}
1287	1261	}
1288	1262	}
r9784	r9785
1296	1270	for( I = 0; I < 2048; I++ )
1297	1271	{
1298	1272	col = ( gb_vram[ 0x0800 + (I*2) + 1 ] << 8 ) | gb_vram[ 0x0800 + (I*2) ];
1299		sgb_pal_data[I] = col;
	1273	state->sgb_pal_data[I] = col;
1300	1274	}
1301	1275	}
1302	1276	break;
r9784	r9785
1326	1300	break;
1327	1301	case 0x13:   /* CHR_TRN */
1328	1302	if( sgb_data[1] & 0x1 )
1329		memcpy( sgb_tile_data + 4096, gb_get_vram_ptr(space->machine) + 0x0800, 4096 );
	1303	memcpy( state->sgb_tile_data + 4096, gb_get_vram_ptr(space->machine) + 0x0800, 4096 );
1330	1304	else
1331		memcpy( sgb_tile_data, gb_get_vram_ptr(space->machine) + 0x0800, 4096 );
	1305	memcpy( state->sgb_tile_data, gb_get_vram_ptr(space->machine) + 0x0800, 4096 );
1332	1306	break;
1333	1307	case 0x14:   /* PCT_TRN */
1334	1308	{
1335	1309	int I;
1336	1310	UINT16 col;
1337	1311	UINT8 *gb_vram = gb_get_vram_ptr( space->machine );
1338		if( sgb_hack )
	1312	if( state->sgb_hack )
1339	1313	{
1340		memcpy( sgb_tile_map, gb_vram + 0x1000, 2048 );
	1314	memcpy( state->sgb_tile_map, gb_vram + 0x1000, 2048 );
1341	1315	for( I = 0; I < 64; I++ )
1342	1316	{
1343	1317	col = ( gb_vram[ 0x0800 + (I*2) + 1 ] << 8 ) | gb_vram[ 0x0800 + (I*2) ];
1344		sgb_pal[SGB_BORDER_PAL_OFFSET + I] = col;
	1318	state->sgb_pal[SGB_BORDER_PAL_OFFSET + I] = col;
1345	1319	}
1346	1320	}
1347	1321	else /* Do things normally */
1348	1322	{
1349		memcpy( sgb_tile_map, gb_vram + 0x0800, 2048 );
	1323	memcpy( state->sgb_tile_map, gb_vram + 0x0800, 2048 );
1350	1324	for( I = 0; I < 64; I++ )
1351	1325	{
1352	1326	col = ( gb_vram[ 0x1000 + (I*2) + 1 ] << 8 ) | gb_vram[ 0x1000 + (I*2) ];
1353		sgb_pal[SGB_BORDER_PAL_OFFSET + I] = col;
	1327	state->sgb_pal[SGB_BORDER_PAL_OFFSET + I] = col;
1354	1328	}
1355	1329	}
1356	1330	}
1357	1331	break;
1358	1332	case 0x15:   /* ATTR_TRN */
1359		memcpy( gb_driver_data.sgb_atf_data, gb_get_vram_ptr( space->machine ) + 0x0800, 4050 );
	1333	memcpy( state->sgb_atf_data, gb_get_vram_ptr( space->machine ) + 0x0800, 4050 );
1360	1334	break;
1361	1335	case 0x16:   /* ATTR_SET */
1362	1336	{
r9784	r9785
1364	1338
1365	1339	/* Attribute File */
1366	1340	if( sgb_data[1] & 0x40 )
1367		sgb_window_mask = 0;
	1341	state->sgb_window_mask = 0;
1368	1342	sgb_atf = (sgb_data[1] & 0x3f) * (18 * 5);
1369	1343	for( J = 0; J < 18; J++ )
1370	1344	{
1371	1345	for( I = 0; I < 5; I++ )
1372	1346	{
1373		sgb_pal_map[I * 4][J] = (gb_driver_data.sgb_atf_data[(J * 5) + sgb_atf + I] & 0xC0) >> 6;
1374		sgb_pal_map[(I * 4) + 1][J] = (gb_driver_data.sgb_atf_data[(J * 5) + sgb_atf + I] & 0x30) >> 4;
1375		sgb_pal_map[(I * 4) + 2][J] = (gb_driver_data.sgb_atf_data[(J * 5) + sgb_atf + I] & 0xC) >> 2;
1376		sgb_pal_map[(I * 4) + 3][J] = gb_driver_data.sgb_atf_data[(J * 5) + sgb_atf + I] & 0x3;
	1347	state->sgb_pal_map[I * 4][J] = (state->sgb_atf_data[(J * 5) + sgb_atf + I] & 0xC0) >> 6;
	1348	state->sgb_pal_map[(I * 4) + 1][J] = (state->sgb_atf_data[(J * 5) + sgb_atf + I] & 0x30) >> 4;
	1349	state->sgb_pal_map[(I * 4) + 2][J] = (state->sgb_atf_data[(J * 5) + sgb_atf + I] & 0xC) >> 2;
	1350	state->sgb_pal_map[(I * 4) + 3][J] = state->sgb_atf_data[(J * 5) + sgb_atf + I] & 0x3;
1377	1351	}
1378	1352	}
1379	1353	}
1380	1354	break;
1381	1355	case 0x17:   /* MASK_EN */
1382		sgb_window_mask = sgb_data[1];
	1356	state->sgb_window_mask = sgb_data[1];
1383	1357	break;
1384	1358	case 0x18:   /* OBJ_TRN */
1385	1359	/* Not Implemnted */
r9784	r9785
1440	1414	return;
1441	1415	}
1442	1416
1443		gb_driver_data.gb_io[offset] = data;
	1417	state->gb_io[offset] = data;
1444	1418	}
1445	1419
1446	1420	/* Interrupt Enable register */
r9784	r9785
1457	1431	/* IO read */
1458	1432	READ8_HANDLER ( gb_io_r )
1459	1433	{
	1434	gb_state *state = space->machine->driver_data<gb_state>();
1460	1435	switch(offset)
1461	1436	{
1462	1437	case 0x04:
1463		return ( gb_driver_data.divcount >> 8 ) & 0xFF;
	1438	return ( state->divcount >> 8 ) & 0xFF;
1464	1439	case 0x00:
1465	1440	case 0x01:
1466	1441	case 0x02:
r9784	r9785
1468	1443	case 0x05:
1469	1444	case 0x06:
1470	1445	case 0x07:
1471		return gb_driver_data.gb_io[offset];
	1446	return state->gb_io[offset];
1472	1447	case 0x0F:
1473	1448	/* Make sure the internal states are up to date */
1474	1449	return 0xE0 | cpu_get_reg( space->machine->device("maincpu"), LR35902_IF );
r9784	r9785
1480	1455
1481	1456	DEVICE_START(gb_cart)
1482	1457	{
	1458	gb_state *state = device->machine->driver_data<gb_state>();
1483	1459	int I;
1484	1460
1485		memset(&gb_driver_data, 0, sizeof(gb_driver_data));
	1461	state->gb_dummy_rom_bank = auto_alloc_array(device->machine, UINT8, 0x4000);
	1462	memset(state->gb_dummy_rom_bank, 0xff, 0x4000);
1486	1463
1487		gb_driver_data.gb_dummy_rom_bank = auto_alloc_array(device->machine, UINT8, 0x4000);
1488		memset(gb_driver_data.gb_dummy_rom_bank, 0xff, 0x4000);
	1464	state->gb_dummy_ram_bank = auto_alloc_array(device->machine, UINT8, 0x2000);
	1465	memset(state->gb_dummy_ram_bank, 0xff, 0x2000 );
1489	1466
1490		gb_driver_data.gb_dummy_ram_bank = auto_alloc_array(device->machine, UINT8, 0x2000);
1491		memset(gb_driver_data.gb_dummy_ram_bank, 0xff, 0x2000 );
1492
1493	1467	for(I = 0; I < MAX_ROMBANK; I++)
1494	1468	{
1495		gb_driver_data.ROMMap[I] = gb_driver_data.gb_dummy_rom_bank;
	1469	state->ROMMap[I] = state->gb_dummy_rom_bank;
1496	1470	}
1497	1471	for(I = 0; I < MAX_RAMBANK; I++)
1498	1472	{
1499		gb_driver_data.RAMMap[I] = gb_driver_data.gb_dummy_ram_bank;
	1473	state->RAMMap[I] = state->gb_dummy_ram_bank;
1500	1474	}
1501		gb_driver_data.ROMBank00 = 0;
1502		gb_driver_data.ROMBanks = 0;
1503		gb_driver_data.RAMBanks = 0;
1504		gb_driver_data.MBCType = MBC_NONE;
1505		gb_driver_data.CartType = 0;
1506		gb_driver_data.ROMMask = 0;
1507		gb_driver_data.RAMMask = 0;
	1475	state->ROMBank00 = 0;
	1476	state->ROMBanks = 0;
	1477	state->RAMBanks = 0;
	1478	state->MBCType = MBC_NONE;
	1479	state->CartType = 0;
	1480	state->ROMMask = 0;
	1481	state->RAMMask = 0;
1508	1482	}
1509	1483
1510	1484	DEVICE_IMAGE_LOAD(gb_cart)
1511	1485	{
	1486	gb_state *state = image.device().machine->driver_data<gb_state>();
1512	1487	static const char *const CartTypes[] =
1513	1488	{
1514	1489	"ROM ONLY",
r9784	r9785
1662	1637	}
1663	1638
1664	1639	/* Claim memory */
1665		gb_driver_data.gb_cart = auto_alloc_array(image.device().machine, UINT8, filesize);
	1640	state->gb_cart = auto_alloc_array(image.device().machine, UINT8, filesize);
1666	1641
1667	1642	if (image.software_entry() == NULL)
1668	1643	{
r9784	r9785
1670	1645	image.fseek(load_start, SEEK_SET);
1671	1646
1672	1647	/* Read cartridge */
1673		if (image.fread( gb_driver_data.gb_cart, filesize) != filesize)
	1648	if (image.fread( state->gb_cart, filesize) != filesize)
1674	1649	{
1675	1650	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unable to fully read from file");
1676	1651	return IMAGE_INIT_FAIL;
1677	1652	}
1678	1653	}
1679	1654	else
1680		memcpy(gb_driver_data.gb_cart, image.get_software_region("rom") + load_start, filesize);
	1655	memcpy(state->gb_cart, image.get_software_region("rom") + load_start, filesize);
1681	1656
1682		gb_header = gb_driver_data.gb_cart;
1683		gb_driver_data.ROMBank00 = 0;
	1657	gb_header = state->gb_cart;
	1658	state->ROMBank00 = 0;
1684	1659
1685	1660	/* Check for presence of MMM01 mapper */
1686	1661	if (filesize >= 0x8000)
r9784	r9785
1691	1666	0x00, 0x08, 0x11, 0x1F, 0x88, 0x89, 0x00, 0x0E
1692	1667	};
1693	1668	int   bytes_matched = 0;
1694		gb_header = gb_driver_data.gb_cart + filesize - 0x8000;
	1669	gb_header = state->gb_cart + filesize - 0x8000;
1695	1670	for (I = 0; I < 0x18; I++)
1696	1671	{
1697	1672	if (gb_header[0x0104 + I] == nintendo_logo[I])
r9784	r9785
1702	1677
1703	1678	if (bytes_matched == 0x18 && gb_header[0x0147] >= 0x0B && gb_header[0x0147] <= 0x0D)
1704	1679	{
1705		gb_driver_data.ROMBank00 = (filesize / 0x4000) - 2;
1706		mmm01_bank_offset = gb_driver_data.ROMBank00;
	1680	state->ROMBank00 = (filesize / 0x4000) - 2;
	1681	state->mmm01_bank_offset = state->ROMBank00;
1707	1682	}
1708	1683	else
1709	1684	{
1710		gb_header = gb_driver_data.gb_cart;
	1685	gb_header = state->gb_cart;
1711	1686	}
1712	1687	}
1713	1688
1714	1689	/* Fill in our cart details */
1715	1690	switch(gb_header[0x0147])
1716	1691	{
1717		case 0x00:   gb_driver_data.MBCType = MBC_NONE;   gb_driver_data.CartType = 0;            break;
1718		case 0x01:   gb_driver_data.MBCType = MBC_MBC1;   gb_driver_data.CartType = 0;            break;
1719		case 0x02:   gb_driver_data.MBCType = MBC_MBC1;   gb_driver_data.CartType = RAM;            break;
1720		case 0x03:   gb_driver_data.MBCType = MBC_MBC1;   gb_driver_data.CartType = RAM | BATTERY;      break;
1721		case 0x05:   gb_driver_data.MBCType = MBC_MBC2;   gb_driver_data.CartType = 0;            break;
1722		case 0x06:   gb_driver_data.MBCType = MBC_MBC2;   gb_driver_data.CartType = BATTERY;         break;
1723		case 0x08:   gb_driver_data.MBCType = MBC_NONE;   gb_driver_data.CartType = RAM;            break;
1724		case 0x09:   gb_driver_data.MBCType = MBC_NONE;   gb_driver_data.CartType = RAM | BATTERY;      break;
1725		case 0x0B:   gb_driver_data.MBCType = MBC_MMM01;   gb_driver_data.CartType = 0;            break;
1726		case 0x0C:   gb_driver_data.MBCType = MBC_MMM01;   gb_driver_data.CartType = RAM;            break;
1727		case 0x0D:   gb_driver_data.MBCType = MBC_MMM01;   gb_driver_data.CartType = RAM | BATTERY;      break;
1728		case 0x0F:   gb_driver_data.MBCType = MBC_MBC3;   gb_driver_data.CartType = TIMER | BATTERY;      break;
1729		case 0x10:   gb_driver_data.MBCType = MBC_MBC3;   gb_driver_data.CartType = TIMER | RAM | BATTERY;   break;
1730		case 0x11:   gb_driver_data.MBCType = MBC_MBC3;   gb_driver_data.CartType = 0;            break;
1731		case 0x12:   gb_driver_data.MBCType = MBC_MBC3;   gb_driver_data.CartType = RAM;            break;
1732		case 0x13:   gb_driver_data.MBCType = MBC_MBC3;   gb_driver_data.CartType = RAM | BATTERY;      break;
1733		case 0x15:   gb_driver_data.MBCType = MBC_MBC4;   gb_driver_data.CartType = 0;            break;
1734		case 0x16:   gb_driver_data.MBCType = MBC_MBC4;   gb_driver_data.CartType = RAM;            break;
1735		case 0x17:   gb_driver_data.MBCType = MBC_MBC4;   gb_driver_data.CartType = RAM | BATTERY;      break;
1736		case 0x19:   gb_driver_data.MBCType = MBC_MBC5;   gb_driver_data.CartType = 0;            break;
1737		case 0x1A:   gb_driver_data.MBCType = MBC_MBC5;   gb_driver_data.CartType = RAM;            break;
1738		case 0x1B:   gb_driver_data.MBCType = MBC_MBC5;   gb_driver_data.CartType = RAM | BATTERY;      break;
1739		case 0x1C:   gb_driver_data.MBCType = MBC_MBC5;   gb_driver_data.CartType = RUMBLE;         break;
1740		case 0x1D:   gb_driver_data.MBCType = MBC_MBC5;   gb_driver_data.CartType = RUMBLE | SRAM;      break;
1741		case 0x1E:   gb_driver_data.MBCType = MBC_MBC5;   gb_driver_data.CartType = RUMBLE | SRAM | BATTERY;   break;
1742		case 0x20:   gb_driver_data.MBCType = MBC_MBC6;   gb_driver_data.CartType = SRAM; break;
1743		case 0x22:   gb_driver_data.MBCType = MBC_MBC7;   gb_driver_data.CartType = SRAM | BATTERY;      break;
1744		case 0xBE:   gb_driver_data.MBCType = MBC_NONE;   gb_driver_data.CartType = 0;            break;   /* used in Flash2Advance GB Bridge boot program */
1745		case 0xFD:   gb_driver_data.MBCType = MBC_TAMA5;   gb_driver_data.CartType = 0 /*RTC | BATTERY?*/;   break;
1746		case 0xFE:   gb_driver_data.MBCType = MBC_HUC3;   gb_driver_data.CartType = 0;            break;
1747		case 0xFF:   gb_driver_data.MBCType = MBC_HUC1;   gb_driver_data.CartType = 0;            break;
1748		default:   gb_driver_data.MBCType = MBC_UNKNOWN;   gb_driver_data.CartType = UNKNOWN;         break;
	1692	case 0x00:   state->MBCType = MBC_NONE;   state->CartType = 0;            break;
	1693	case 0x01:   state->MBCType = MBC_MBC1;   state->CartType = 0;            break;
	1694	case 0x02:   state->MBCType = MBC_MBC1;   state->CartType = RAM;            break;
	1695	case 0x03:   state->MBCType = MBC_MBC1;   state->CartType = RAM | BATTERY;      break;
	1696	case 0x05:   state->MBCType = MBC_MBC2;   state->CartType = 0;            break;
	1697	case 0x06:   state->MBCType = MBC_MBC2;   state->CartType = BATTERY;         break;
	1698	case 0x08:   state->MBCType = MBC_NONE;   state->CartType = RAM;            break;
	1699	case 0x09:   state->MBCType = MBC_NONE;   state->CartType = RAM | BATTERY;      break;
	1700	case 0x0B:   state->MBCType = MBC_MMM01;   state->CartType = 0;            break;
	1701	case 0x0C:   state->MBCType = MBC_MMM01;   state->CartType = RAM;            break;
	1702	case 0x0D:   state->MBCType = MBC_MMM01;   state->CartType = RAM | BATTERY;      break;
	1703	case 0x0F:   state->MBCType = MBC_MBC3;   state->CartType = TIMER | BATTERY;      break;
	1704	case 0x10:   state->MBCType = MBC_MBC3;   state->CartType = TIMER | RAM | BATTERY;   break;
	1705	case 0x11:   state->MBCType = MBC_MBC3;   state->CartType = 0;            break;
	1706	case 0x12:   state->MBCType = MBC_MBC3;   state->CartType = RAM;            break;
	1707	case 0x13:   state->MBCType = MBC_MBC3;   state->CartType = RAM | BATTERY;      break;
	1708	case 0x15:   state->MBCType = MBC_MBC4;   state->CartType = 0;            break;
	1709	case 0x16:   state->MBCType = MBC_MBC4;   state->CartType = RAM;            break;
	1710	case 0x17:   state->MBCType = MBC_MBC4;   state->CartType = RAM | BATTERY;      break;
	1711	case 0x19:   state->MBCType = MBC_MBC5;   state->CartType = 0;            break;
	1712	case 0x1A:   state->MBCType = MBC_MBC5;   state->CartType = RAM;            break;
	1713	case 0x1B:   state->MBCType = MBC_MBC5;   state->CartType = RAM | BATTERY;      break;
	1714	case 0x1C:   state->MBCType = MBC_MBC5;   state->CartType = RUMBLE;         break;
	1715	case 0x1D:   state->MBCType = MBC_MBC5;   state->CartType = RUMBLE | SRAM;      break;
	1716	case 0x1E:   state->MBCType = MBC_MBC5;   state->CartType = RUMBLE | SRAM | BATTERY;   break;
	1717	case 0x20:   state->MBCType = MBC_MBC6;   state->CartType = SRAM; break;
	1718	case 0x22:   state->MBCType = MBC_MBC7;   state->CartType = SRAM | BATTERY;      break;
	1719	case 0xBE:   state->MBCType = MBC_NONE;   state->CartType = 0;            break;   /* used in Flash2Advance GB Bridge boot program */
	1720	case 0xFD:   state->MBCType = MBC_TAMA5;   state->CartType = 0 /*RTC | BATTERY?*/;   break;
	1721	case 0xFE:   state->MBCType = MBC_HUC3;   state->CartType = 0;            break;
	1722	case 0xFF:   state->MBCType = MBC_HUC1;   state->CartType = 0;            break;
	1723	default:   state->MBCType = MBC_UNKNOWN;   state->CartType = UNKNOWN;         break;
1749	1724	}
1750	1725
1751	1726	/* Check whether we're dealing with a (possible) Wisdom Tree game here */
r9784	r9785
1758	1733	}
1759	1734	if (count == 0)
1760	1735	{
1761		gb_driver_data.MBCType = MBC_WISDOM;
	1736	state->MBCType = MBC_WISDOM;
1762	1737	}
1763	1738	}
1764	1739
1765	1740	/* Check if we're dealing with a Korean variant of the MBC1 mapper */
1766		if (gb_driver_data.MBCType == MBC_MBC1)
	1741	if (state->MBCType == MBC_MBC1)
1767	1742	{
1768	1743	if (gb_header[0x13F] == 0x42 && gb_header[0x140] == 0x32 && gb_header[0x141] == 0x43 && gb_header[0x142] == 0x4B)
1769	1744	{
1770		gb_driver_data.MBCType = MBC_MBC1_KOR;
	1745	state->MBCType = MBC_MBC1_KOR;
1771	1746	}
1772	1747	}
1773		if (gb_driver_data.MBCType == MBC_UNKNOWN)
	1748	if (state->MBCType == MBC_UNKNOWN)
1774	1749	{
1775	1750	image.seterror(IMAGE_ERROR_UNSUPPORTED, "Unknown mapper type");
1776	1751	return IMAGE_INIT_FAIL;
1777	1752	}
1778		if (gb_driver_data.MBCType == MBC_MMM01)
	1753	if (state->MBCType == MBC_MMM01)
1779	1754	{
1780	1755	//      image.seterror(IMAGE_ERROR_UNSUPPORTED, "Mapper MMM01 is not supported yet");
1781	1756	//      return IMAGE_INIT_FAIL;
1782	1757	}
1783		if (gb_driver_data.MBCType == MBC_MBC4)
	1758	if (state->MBCType == MBC_MBC4)
1784	1759	{
1785	1760	image.seterror(IMAGE_ERROR_UNSUPPORTED, "Mapper MBC4 is not supported yet");
1786	1761	return IMAGE_INIT_FAIL;
1787	1762	}
1788	1763	/* MBC7 support is still work-in-progress, so only enable it for debug builds */
1789	1764	#ifndef MAME_DEBUG
1790		if (gb_driver_data.MBCType == MBC_MBC7)
	1765	if (state->MBCType == MBC_MBC7)
1791	1766	{
1792	1767	image.seterror(IMAGE_ERROR_UNSUPPORTED, "Mapper MBC7 is not supported yet");
1793	1768	return IMAGE_INIT_FAIL;
1794	1769	}
1795	1770	#endif
1796	1771
1797		gb_driver_data.ROMBanks = filesize / 0x4000;
	1772	state->ROMBanks = filesize / 0x4000;
1798	1773	switch (gb_header[0x0148])
1799	1774	{
1800	1775	case 0x52:
r9784	r9785
1815	1790	reported_rom_banks = 256;
1816	1791	break;
1817	1792	}
1818		if (gb_driver_data.ROMBanks != reported_rom_banks && gb_driver_data.MBCType != MBC_WISDOM)
	1793	if (state->ROMBanks != reported_rom_banks && state->MBCType != MBC_WISDOM)
1819	1794	{
1820	1795	logerror("Warning loading cartridge: Filesize and reported ROM banks don't match.\n");
1821	1796	}
1822	1797
1823		gb_driver_data.RAMBanks = rambanks[gb_header[0x0149] & 7];
	1798	state->RAMBanks = rambanks[gb_header[0x0149] & 7];
1824	1799
1825	1800	/* Calculate and check checksum */
1826	1801	Checksum = ((UINT16) gb_header[0x014E] << 8) + gb_header[0x014F];
1827	1802	Checksum += gb_header[0x014E] + gb_header[0x014F];
1828	1803	for (I = 0; I < filesize; I++)
1829	1804	{
1830		Checksum -= gb_driver_data.gb_cart[I];
	1805	Checksum -= state->gb_cart[I];
1831	1806	}
1832	1807	if (Checksum & 0xFFFF)
1833	1808	{
r9784	r9785
1835	1810	}
1836	1811
1837	1812	/* Initialize ROMMap pointers */
1838		for (I = 0; I < gb_driver_data.ROMBanks; I++)
	1813	for (I = 0; I < state->ROMBanks; I++)
1839	1814	{
1840		gb_driver_data.ROMMap[I] = gb_driver_data.gb_cart + (I * 0x4000);
	1815	state->ROMMap[I] = state->gb_cart + (I * 0x4000);
1841	1816	}
1842	1817
1843	1818	/*
r9784	r9785
1847	1822	80 (1010000)  1001111 (79)
1848	1823	96 (1100000)  1011111 (95)
1849	1824	*/
1850		gb_driver_data.ROMMask = I - 1;
1851		if ((gb_driver_data.ROMBanks & gb_driver_data.ROMMask) != 0)
	1825	state->ROMMask = I - 1;
	1826	if ((state->ROMBanks & state->ROMMask) != 0)
1852	1827	{
1853		for( ; I & gb_driver_data.ROMBanks; I++)
	1828	for( ; I & state->ROMBanks; I++)
1854	1829	{
1855		gb_driver_data.ROMMap[I] = gb_driver_data.ROMMap[I & gb_driver_data.ROMMask];
	1830	state->ROMMap[I] = state->ROMMap[I & state->ROMMask];
1856	1831	}
1857		gb_driver_data.ROMMask = I - 1;
	1832	state->ROMMask = I - 1;
1858	1833	}
1859	1834
1860	1835	/* Fill out the remaining rom bank pointers, if any. */
1861	1836	for ( ; I < MAX_ROMBANK; I++)
1862	1837	{
1863		gb_driver_data.ROMMap[I] = gb_driver_data.ROMMap[I & gb_driver_data.ROMMask];
	1838	state->ROMMap[I] = state->ROMMap[I & state->ROMMask];
1864	1839	}
1865	1840
1866	1841	/* Log cart information */
r9784	r9785
1877	1852	logerror("\tType:             %s [0x%2X]\n", CartTypes[gb_header[0x0147]], gb_header[0x0147] );
1878	1853	logerror("\tGame Boy:         %s\n", (gb_header[0x0143] == 0xc0) ? "No" : "Yes" );
1879	1854	logerror("\tSuper GB:         %s [0x%2X]\n", (gb_header[0x0146] == 0x03) ? "Yes" : "No", gb_header[0x0146] );
1880		logerror("\tColor GB:         %s [0x%2X]\n", (gb_header[0x0143] == 0x80 || gb_header[0x0143] == 0xc0) ? "Yes" : "No", gb_driver_data.gb_cart[0x0143] );
1881		logerror("\tROM Size:         %d 16kB Banks [0x%2X]\n", gb_driver_data.ROMBanks, gb_header[0x0148]);
	1855	logerror("\tColor GB:         %s [0x%2X]\n", (gb_header[0x0143] == 0x80 || gb_header[0x0143] == 0xc0) ? "Yes" : "No", state->gb_cart[0x0143] );
	1856	logerror("\tROM Size:         %d 16kB Banks [0x%2X]\n", state->ROMBanks, gb_header[0x0148]);
1882	1857	logerror("\tRAM Size:         %d kB [0x%2X]\n", ramsize[ gb_header[0x0149] & 0x07 ], gb_header[0x0149]);
1883	1858	logerror("\tLicense code:     0x%2X%2X\n", gb_header[0x0145], gb_header[0x0144] );
1884	1859	J = ((UINT16) gb_header[0x014B] << 8) + gb_header[0x014A];
r9784	r9785
1895	1870	}
1896	1871
1897	1872	/* MBC2 has 512 * 4bits (8kb) internal RAM */
1898		if(gb_driver_data.MBCType == MBC_MBC2)
1899		gb_driver_data.RAMBanks = 1;
	1873	if(state->MBCType == MBC_MBC2)
	1874	state->RAMBanks = 1;
1900	1875	/* MBC7 has 512 bytes(?) of internal RAM */
1901		if (gb_driver_data.MBCType == MBC_MBC7)
	1876	if (state->MBCType == MBC_MBC7)
1902	1877	{
1903		gb_driver_data.RAMBanks = 1;
	1878	state->RAMBanks = 1;
1904	1879	}
1905	1880
1906		if (gb_driver_data.RAMBanks && gb_driver_data.MBCType)
	1881	if (state->RAMBanks && state->MBCType)
1907	1882	{
1908	1883	/* Claim memory */
1909		gb_driver_data.gb_cart_ram = auto_alloc_array(image.device().machine, UINT8, gb_driver_data.RAMBanks * 0x2000);
1910		memset(gb_driver_data.gb_cart_ram, 0xFF, gb_driver_data.RAMBank * 0x2000);
	1884	state->gb_cart_ram = auto_alloc_array(image.device().machine, UINT8, state->RAMBanks * 0x2000);
	1885	memset(state->gb_cart_ram, 0xFF, state->RAMBank * 0x2000);
1911	1886
1912		for (I = 0; I < gb_driver_data.RAMBanks; I++)
	1887	for (I = 0; I < state->RAMBanks; I++)
1913	1888	{
1914		gb_driver_data.RAMMap[I] = gb_driver_data.gb_cart_ram + (I * 0x2000);
	1889	state->RAMMap[I] = state->gb_cart_ram + (I * 0x2000);
1915	1890	}
1916	1891
1917	1892	/* Set up rest of the (mirrored) RAM pages */
1918		gb_driver_data.RAMMask = I - 1;
	1893	state->RAMMask = I - 1;
1919	1894	for ( ; I < MAX_RAMBANK; I++)
1920	1895	{
1921		gb_driver_data.RAMMap[I] = gb_driver_data.RAMMap[I & gb_driver_data.RAMMask];
	1896	state->RAMMap[I] = state->RAMMap[I & state->RAMMask];
1922	1897	}
1923	1898	}
1924	1899	else
1925	1900	{
1926		gb_driver_data.RAMMask = 0;
	1901	state->RAMMask = 0;
1927	1902	}
1928	1903
1929	1904	/* If there's an RTC claim memory to store the RTC contents */
1930		if (gb_driver_data.CartType & TIMER)
	1905	if (state->CartType & TIMER)
1931	1906	{
1932		gb_driver_data.MBC3RTCData = auto_alloc_array(image.device().machine, UINT8, 0x2000);
	1907	state->MBC3RTCData = auto_alloc_array(image.device().machine, UINT8, 0x2000);
1933	1908	}
1934	1909
1935		if (gb_driver_data.MBCType == MBC_TAMA5)
	1910	if (state->MBCType == MBC_TAMA5)
1936	1911	{
1937		gb_driver_data.MBC3RTCData = auto_alloc_array(image.device().machine, UINT8, 0x2000);
1938		memset(gb_driver_data.gbTama5Memory, 0xff, sizeof(gb_driver_data.gbTama5Memory));
	1912	state->MBC3RTCData = auto_alloc_array(image.device().machine, UINT8, 0x2000);
	1913	memset(state->gbTama5Memory, 0xff, sizeof(state->gbTama5Memory));
1939	1914	}
1940	1915
1941	1916	/* Load the saved RAM if this cart has a battery */
1942		if (gb_driver_data.CartType & BATTERY && gb_driver_data.RAMBanks)
	1917	if (state->CartType & BATTERY && state->RAMBanks)
1943	1918	{
1944		image.battery_load(gb_driver_data.gb_cart_ram, gb_driver_data.RAMBanks * 0x2000, 0x00);
	1919	image.battery_load(state->gb_cart_ram, state->RAMBanks * 0x2000, 0x00);
1945	1920	}
1946	1921
1947	1922	return IMAGE_INIT_PASS;
r9784	r9785
1953	1928
1954	1929	static TIMER_CALLBACK(gb_serial_timer_proc)
1955	1930	{
	1931	gb_state *state = machine->driver_data<gb_state>();
1956	1932	/* Shift in a received bit */
1957	1933	SIODATA = (SIODATA << 1) | 0x01;
1958	1934	/* Decrement number of handled bits */
1959		gb_driver_data.SIOCount--;
	1935	state->SIOCount--;
1960	1936	/* If all bits done, stop timer and trigger interrupt */
1961		if ( ! gb_driver_data.SIOCount )
	1937	if ( ! state->SIOCount )
1962	1938	{
1963	1939	SIOCONT &= 0x7F;
1964		timer_enable( gb_driver_data.gb_serial_timer, 0 );
	1940	timer_enable( state->gb_serial_timer, 0 );
1965	1941	cputag_set_input_line(machine, "maincpu", SIO_INT, ASSERT_LINE);
1966	1942	}
1967	1943	}
1968	1944
1969	1945	INLINE void gb_timer_check_irq( running_machine *machine )
1970	1946	{
1971		gb_driver_data.reloading = 0;
1972		if ( gb_driver_data.triggering_irq )
	1947	gb_state *state = machine->driver_data<gb_state>();
	1948	state->reloading = 0;
	1949	if ( state->triggering_irq )
1973	1950	{
1974		gb_driver_data.triggering_irq = 0;
	1951	state->triggering_irq = 0;
1975	1952	if ( TIMECNT == 0 )
1976	1953	{
1977	1954	TIMECNT = TIMEMOD;
1978	1955	cputag_set_input_line(machine, "maincpu", TIM_INT, ASSERT_LINE );
1979		gb_driver_data.reloading = 1;
	1956	state->reloading = 1;
1980	1957	}
1981	1958	}
1982	1959	}
1983	1960
1984	1961	static void gb_timer_increment( running_machine *machine )
1985	1962	{
	1963	gb_state *state = machine->driver_data<gb_state>();
1986	1964	gb_timer_check_irq(machine);
1987	1965
1988	1966	TIMECNT += 1;
1989	1967	if ( TIMECNT == 0 )
1990	1968	{
1991		gb_driver_data.triggering_irq = 1;
	1969	state->triggering_irq = 1;
1992	1970	}
1993	1971	}
1994	1972
1995	1973	void gb_timer_callback(running_device *device, int cycles)
1996	1974	{
1997		UINT16 old_gb_divcount = gb_driver_data.divcount;
1998		gb_driver_data.divcount += cycles;
	1975	gb_state *state = device->machine->driver_data<gb_state>();
	1976	UINT16 old_gb_divcount = state->divcount;
	1977	state->divcount += cycles;
1999	1978
2000	1979	gb_timer_check_irq(device->machine);
2001	1980
2002	1981	if ( TIMEFRQ & 0x04 )
2003	1982	{
2004		UINT16 old_count = old_gb_divcount >> gb_driver_data.shift;
2005		UINT16 new_count = gb_driver_data.divcount >> gb_driver_data.shift;
2006		if ( cycles > gb_driver_data.shift_cycles )
	1983	UINT16 old_count = old_gb_divcount >> state->shift;
	1984	UINT16 new_count = state->divcount >> state->shift;
	1985	if ( cycles > state->shift_cycles )
2007	1986	{
2008	1987	gb_timer_increment(device->machine);
2009	1988	old_count++;
r9784	r9785
2012	1991	{
2013	1992	gb_timer_increment(device->machine);
2014	1993	}
2015		if ( new_count << gb_driver_data.shift < gb_driver_data.divcount )
	1994	if ( new_count << state->shift < state->divcount )
2016	1995	{
2017	1996	gb_timer_check_irq(device->machine);
2018	1997	}
r9784	r9785
2021	2000
2022	2001	WRITE8_HANDLER ( gbc_io2_w )
2023	2002	{
	2003	gb_state *state = space->machine->driver_data<gb_state>();
2024	2004	switch( offset )
2025	2005	{
2026	2006	case 0x0D:   /* KEY1 - Prepare speed switch */
2027	2007	cpu_set_reg( space->machine->device("maincpu"), LR35902_SPEED, data );
2028	2008	return;
2029	2009	case 0x10:   /* BFF - Bios disable */
2030		gb_rom16_0000( space->machine, gb_driver_data.ROMMap[gb_driver_data.ROMBank00] );
	2010	gb_rom16_0000( space->machine, state->ROMMap[state->ROMBank00] );
2031	2011	return;
2032	2012	case 0x16:   /* RP - Infrared port */
2033	2013	break;
2034	2014	case 0x30:   /* SVBK - RAM bank select */
2035		gb_driver_data.GBC_RAMBank = data & 0x7;
2036		if ( ! gb_driver_data.GBC_RAMBank )
2037		gb_driver_data.GBC_RAMBank = 1;
2038		memory_set_bankptr (space->machine, "bank3", gb_driver_data.GBC_RAMMap[gb_driver_data.GBC_RAMBank]);
	2015	state->GBC_RAMBank = data & 0x7;
	2016	if ( ! state->GBC_RAMBank )
	2017	state->GBC_RAMBank = 1;
	2018	memory_set_bankptr (space->machine, "bank3", state->GBC_RAMMap[state->GBC_RAMBank]);
2039	2019	break;
2040	2020	default:
2041	2021	break;
r9784	r9785
2045	2025
2046	2026	READ8_HANDLER( gbc_io2_r )
2047	2027	{
	2028	gb_state *state = space->machine->driver_data<gb_state>();
2048	2029	switch( offset )
2049	2030	{
2050	2031	case 0x0D:   /* KEY1 */
r9784	r9785
2052	2033	case 0x16:   /* RP - Infrared port */
2053	2034	break;
2054	2035	case 0x30:   /* SVBK - RAM bank select */
2055		return gb_driver_data.GBC_RAMBank;
	2036	return state->GBC_RAMBank;
2056	2037	default:
2057	2038	break;
2058	2039	}
r9784	r9785
2067	2048
2068	2049	MACHINE_START( megaduck )
2069	2050	{
	2051	gb_state *state = machine->driver_data<gb_state>();
2070	2052	/* Allocate the serial timer, and disable it */
2071		gb_driver_data.gb_serial_timer = timer_alloc(machine,  gb_serial_timer_proc , NULL);
2072		timer_enable( gb_driver_data.gb_serial_timer, 0 );
	2053	state->gb_serial_timer = timer_alloc(machine,  gb_serial_timer_proc , NULL);
	2054	timer_enable( state->gb_serial_timer, 0 );
2073	2055
2074	2056	MACHINE_START_CALL( gb_video );
2075	2057	}
r9784	r9785
2190	2172
2191	2173	WRITE8_HANDLER( megaduck_rom_bank_select_type1 )
2192	2174	{
2193		if( gb_driver_data.ROMMask )
	2175	gb_state *state = space->machine->driver_data<gb_state>();
	2176	if( state->ROMMask )
2194	2177	{
2195		gb_driver_data.ROMBank = data & gb_driver_data.ROMMask;
	2178	state->ROMBank = data & state->ROMMask;
2196	2179
2197	2180	/* Switch banks */
2198		memory_set_bankptr (space->machine, "bank1", gb_driver_data.ROMMap[gb_driver_data.ROMBank]);
	2181	memory_set_bankptr (space->machine, "bank1", state->ROMMap[state->ROMBank]);
2199	2182	}
2200	2183	}
2201	2184
2202	2185	WRITE8_HANDLER( megaduck_rom_bank_select_type2 )
2203	2186	{
2204		if( gb_driver_data.ROMMask )
	2187	gb_state *state = space->machine->driver_data<gb_state>();
	2188	if( state->ROMMask )
2205	2189	{
2206		gb_driver_data.ROMBank = (data << 1) & gb_driver_data.ROMMask;
	2190	state->ROMBank = (data << 1) & state->ROMMask;
2207	2191
2208	2192	/* Switch banks */
2209		memory_set_bankptr( space->machine, "bank10", gb_driver_data.ROMMap[gb_driver_data.ROMBank]);
2210		memory_set_bankptr( space->machine, "bank1", gb_driver_data.ROMMap[gb_driver_data.ROMBank + 1]);
	2193	memory_set_bankptr( space->machine, "bank10", state->ROMMap[state->ROMBank]);
	2194	memory_set_bankptr( space->machine, "bank1", state->ROMMap[state->ROMBank + 1]);
2211	2195	}
2212	2196	}
2213	2197
2214	2198	DEVICE_IMAGE_LOAD(megaduck_cart)
2215	2199	{
	2200	gb_state *state = image.device().machine->driver_data<gb_state>();
2216	2201	int I;
2217	2202	UINT32 filesize;
2218	2203
2219	2204	for (I = 0; I < MAX_ROMBANK; I++)
2220		gb_driver_data.ROMMap[I] = NULL;
	2205	state->ROMMap[I] = NULL;
2221	2206	for (I = 0; I < MAX_RAMBANK; I++)
2222		gb_driver_data.RAMMap[I] = NULL;
	2207	state->RAMMap[I] = NULL;
2223	2208
2224	2209	if (image.software_entry() == NULL)
2225	2210	filesize = image.length();
r9784	r9785
2232	2217	return IMAGE_INIT_FAIL;
2233	2218	}
2234	2219
2235		gb_driver_data.ROMBanks = filesize / 0x4000;
	2220	state->ROMBanks = filesize / 0x4000;
2236	2221
2237	2222	/* Claim memory */
2238		gb_driver_data.gb_cart = auto_alloc_array(image.device().machine, UINT8, filesize);
	2223	state->gb_cart = auto_alloc_array(image.device().machine, UINT8, filesize);
2239	2224
2240	2225	/* Read cartridge */
2241	2226	if (image.software_entry() == NULL)
2242	2227	{
2243		if (image.fread( gb_driver_data.gb_cart, filesize) != filesize)
	2228	if (image.fread( state->gb_cart, filesize) != filesize)
2244	2229	{
2245	2230	image.seterror(IMAGE_ERROR_UNSPECIFIED, "Unable to fully read from file");
2246	2231	return IMAGE_INIT_FAIL;
r9784	r9785
2248	2233	}
2249	2234	else
2250	2235	{
2251		memcpy(gb_driver_data.gb_cart, image.get_software_region("rom"), filesize);
	2236	memcpy(state->gb_cart, image.get_software_region("rom"), filesize);
2252	2237	}
2253	2238
2254	2239	/* Log cart information */
2255	2240	{
2256	2241	logerror("Cart Information\n");
2257		logerror("\tRom Banks:        %d\n", gb_driver_data.ROMBanks);
	2242	logerror("\tRom Banks:        %d\n", state->ROMBanks);
2258	2243	}
2259	2244
2260		for (I = 0; I < gb_driver_data.ROMBanks; I++)
	2245	for (I = 0; I < state->ROMBanks; I++)
2261	2246	{
2262		gb_driver_data.ROMMap[I] = gb_driver_data.gb_cart + (I * 0x4000);
	2247	state->ROMMap[I] = state->gb_cart + (I * 0x4000);
2263	2248	}
2264	2249
2265	2250	/* Build rom bank Mask */
2266		if (gb_driver_data.ROMBanks < 3)
2267		gb_driver_data.ROMMask = 0;
	2251	if (state->ROMBanks < 3)
	2252	state->ROMMask = 0;
2268	2253	else
2269	2254	{
2270		for (I = 1; I < gb_driver_data.ROMBanks; I <<= 1) ;
2271		gb_driver_data.ROMMask = I - 1;
	2255	for (I = 1; I < state->ROMBanks; I <<= 1) ;
	2256	state->ROMMask = I - 1;
2272	2257	}
2273	2258
2274		gb_driver_data.MBCType = MBC_MEGADUCK;
	2259	state->MBCType = MBC_MEGADUCK;
2275	2260
2276	2261	return IMAGE_INIT_PASS;
2277	2262	}

src/mess/machine/kc.c

r9784	r9785
296	296	"Disk Interface"
297	297	};
298	298
299		static const struct kc85_module *modules[256>>2];
300	299	/*
301	300
302	301	port xx80
r9784	r9785
315	314
316	315	READ8_HANDLER(kc85_module_r)
317	316	{
	317	kc_state *state = space->machine->driver_data<kc_state>();
318	318	int port_upper;
319	319	int module_index;
320	320
r9784	r9785
330	330
331	331	module_index = (port_upper>>2) & 0x03f;
332	332
333		if (modules[module_index])
	333	if (state->modules[module_index])
334	334	{
335		return modules[module_index]->id;
	335	return state->modules[module_index]->id;
336	336	}
337	337
338	338	return 0x0ff;
r9784	r9785
351	351	state->kc85_module_rom = NULL;
352	352	for (i=0; i<64; i++)
353	353	{
354		modules[i] = NULL;
	354	state->modules[i] = NULL;
355	355	}
356	356
357		modules[30] = &kc85_disk_interface_device;
	357	state->modules[30] = &kc85_disk_interface_device;
358	358	}
359	359
360	360

src/mess/video/cpschngr.c

r9784	r9785
77	77	int bootleg_kludge;
78	78	};
79	79
80		static const struct CPS1config *cps1_game_config;
81
82
83	80	#define __not_applicable__   -1,-1,-1,-1,-1,-1,-1
84	81
85	82	/*                     CPSB ID    multiply protection      unknown      ctrl     priority masks   palctrl    layer enable masks  */
r9784	r9785
153	150
154	151	static MACHINE_RESET( cps )
155	152	{
	153	cpschngr_state *state = machine->driver_data<cpschngr_state>();
156	154	const char *gamename = machine->gamedrv->name;
157	155	const struct CPS1config *pCFG=&cps1_config_table[0];
158	156
r9784	r9785
164	162	}
165	163	pCFG++;
166	164	}
167		cps1_game_config=pCFG;
	165	state->cps1_game_config=pCFG;
168	166	}
169	167
170	168
r9784	r9785
193	191	/* Some games interrogate a couple of registers on bootup. */
194	192	/* These are CPS1 board B self test checks. They wander from game to */
195	193	/* game. */
196		if (offset == cps1_game_config->cpsb_addr/2)
197		return cps1_game_config->cpsb_value;
	194	if (offset == state->cps1_game_config->cpsb_addr/2)
	195	return state->cps1_game_config->cpsb_value;
198	196
199	197	/* some games use as a protection check the ability to do 16-bit multiplications */
200	198	/* with a 32-bit result, by writing the factors to two ports and reading the */
201	199	/* result from two other ports. */
202		if (offset == cps1_game_config->mult_result_lo/2)
203		return (state->cps1_cps_b_regs[cps1_game_config->mult_factor1/2] *
204		state->cps1_cps_b_regs[cps1_game_config->mult_factor2/2]) & 0xffff;
205		if (offset == cps1_game_config->mult_result_hi/2)
206		return (state->cps1_cps_b_regs[cps1_game_config->mult_factor1/2] *
207		state->cps1_cps_b_regs[cps1_game_config->mult_factor2/2]) >> 16;
	200	if (offset == state->cps1_game_config->mult_result_lo/2)
	201	return (state->cps1_cps_b_regs[state->cps1_game_config->mult_factor1/2] *
	202	state->cps1_cps_b_regs[state->cps1_game_config->mult_factor2/2]) & 0xffff;
	203	if (offset == state->cps1_game_config->mult_result_hi/2)
	204	return (state->cps1_cps_b_regs[state->cps1_game_config->mult_factor1/2] *
	205	state->cps1_cps_b_regs[state->cps1_game_config->mult_factor2/2]) >> 16;
208	206
209		if (offset == cps1_game_config->in2_addr/2)   /* Extra input ports (on C-board) */
	207	if (offset == state->cps1_game_config->in2_addr/2)   /* Extra input ports (on C-board) */
210	208	return input_port_read(space->machine, "IN2");
211	209
212		if (offset == cps1_game_config->in3_addr/2)   /* Player 4 controls (on C-board) ("Captain Commando") */
	210	if (offset == state->cps1_game_config->in3_addr/2)   /* Player 4 controls (on C-board) ("Captain Commando") */
213	211	return input_port_read(space->machine, "IN3");
214	212
215	213	return 0xffff;
r9784	r9785
222	220	data = COMBINE_DATA(&state->cps1_cps_b_regs[offset]);
223	221
224	222	// additional outputs on C-board
225		if (offset == cps1_game_config->out2_addr/2)
	223	if (offset == state->cps1_game_config->out2_addr/2)
226	224	{
227	225	if (ACCESSING_BITS_0_7)
228	226	{
229		if (cps1_game_config->cpsb_value == 0x0402)   // Mercs (CN2 connector)
	227	if (state->cps1_game_config->cpsb_value == 0x0402)   // Mercs (CN2 connector)
230	228	{
231	229	coin_lockout_w(space->machine,2,~data & 0x01);
232	230	set_led_status(space->machine,0,data & 0x02);
r9784	r9785
330	328	}
331	329
332	330	/* Some of the sf2 hacks use only sprite port 0x9100 and the scroll layers are offset */
333		if (cps1_game_config->bootleg_kludge == 1)
	331	if (state->cps1_game_config->bootleg_kludge == 1)
334	332	{
335	333	state->cps1_cps_a_regs[CPS1_OBJ_BASE] = 0x9100;
336	334	state->cps1_obj = cps1_base(state, CPS1_OBJ_BASE, cps1_obj_size);
r9784	r9785
360	358	state->stars2y = state->cps1_cps_a_regs[CPS1_STARS2_SCROLLY];
361	359
362	360	/* Get layer enable bits */
363		layercontrol = state->cps1_cps_b_regs[cps1_game_config->layer_control/2];
	361	layercontrol = state->cps1_cps_b_regs[state->cps1_game_config->layer_control/2];
364	362	videocontrol = state->cps1_cps_a_regs[CPS1_VIDEOCONTROL];
365		tilemap_set_enable(state->cps1_bg_tilemap[0],layercontrol & cps1_game_config->layer_enable_mask[0]);
366		tilemap_set_enable(state->cps1_bg_tilemap[1],(layercontrol & cps1_game_config->layer_enable_mask[1]) && (videocontrol & 4));
367		tilemap_set_enable(state->cps1_bg_tilemap[2],(layercontrol & cps1_game_config->layer_enable_mask[2]) && (videocontrol & 8));
368		state->cps1_stars_enabled[0] = layercontrol & cps1_game_config->layer_enable_mask[3];
369		state->cps1_stars_enabled[1] = layercontrol & cps1_game_config->layer_enable_mask[4];
	363	tilemap_set_enable(state->cps1_bg_tilemap[0],layercontrol & state->cps1_game_config->layer_enable_mask[0]);
	364	tilemap_set_enable(state->cps1_bg_tilemap[1],(layercontrol & state->cps1_game_config->layer_enable_mask[1]) && (videocontrol & 4));
	365	tilemap_set_enable(state->cps1_bg_tilemap[2],(layercontrol & state->cps1_game_config->layer_enable_mask[2]) && (videocontrol & 8));
	366	state->cps1_stars_enabled[0] = layercontrol & state->cps1_game_config->layer_enable_mask[3];
	367	state->cps1_stars_enabled[1] = layercontrol & state->cps1_game_config->layer_enable_mask[4];
370	368	}
371	369
372	370
r9784	r9785
388	386
389	387	static int gfxrom_bank_mapper(running_machine *machine, int type, int code)
390	388	{
391		const struct gfx_range *range = cps1_game_config->bank_mapper;
	389	cpschngr_state *state = machine->driver_data<cpschngr_state>();
	390	const struct gfx_range *range = state->cps1_game_config->bank_mapper;
392	391	int shift = 0;
393	392
394	393	assert(range);
r9784	r9785
413	412	int i;
414	413
415	414	for (i = 0; i < range->bank; ++i)
416		base += cps1_game_config->bank_sizes[i];
	415	base += state->cps1_game_config->bank_sizes[i];
417	416
418		return (base + (code & (cps1_game_config->bank_sizes[range->bank] - 1))) >> shift;
	417	return (base + (code & (state->cps1_game_config->bank_sizes[range->bank] - 1))) >> shift;
419	418	}
420	419	}
421	420
r9784	r9785
530	529	int mask;
531	530
532	531	/* Get transparency registers */
533		if (cps1_game_config->priority[i] != -1)
534		mask = state->cps1_cps_b_regs[cps1_game_config->priority[i]/2] ^ 0xffff;
	532	if (state->cps1_game_config->priority[i] != -1)
	533	mask = state->cps1_cps_b_regs[state->cps1_game_config->priority[i]/2] ^ 0xffff;
535	534	else mask = 0xffff;   /* completely transparent if priority masks not defined (qad) */
536	535
537	536	tilemap_set_transmask(state->cps1_bg_tilemap[0],i,mask,0x8000);
r9784	r9785
575	574	state->cps1_cps_a_regs[CPS1_SCROLL3_BASE] = 0x9080;
576	575	state->cps1_cps_a_regs[CPS1_OTHER_BASE]   = 0x9100;
577	576
578		assert_always(cps1_game_config, "cps1_game_config hasn't been set up yet");
	577	assert_always(state->cps1_game_config, "state->cps1_game_config hasn't been set up yet");
579	578
580	579	/* Set up old base */
581	580	cps1_get_video_base(state);   /* Calculate base pointers */
r9784	r9785
598	597	int offset, page;
599	598	const UINT16 *palette_ram = palette_base;
600	599
601		int ctrl = state->cps1_cps_b_regs[cps1_game_config->palette_control/2];
	600	int ctrl = state->cps1_cps_b_regs[state->cps1_game_config->palette_control/2];
602	601
603	602	for (page = 0; page < 6; ++page)
604	603	{
r9784	r9785
676	675	UINT16 *base=state->cps1_buffered_obj;
677	676
678	677	/* some sf2 hacks draw the sprites in reverse order */
679		if (cps1_game_config->bootleg_kludge == 1)
	678	if (state->cps1_game_config->bootleg_kludge == 1)
680	679	{
681	680	base += state->cps1_last_sprite_offset;
682	681	baseadd = -4;
r9784	r9785
912	911
913	912	flip_screen_set(screen->machine, videocontrol & 0x8000);
914	913
915		layercontrol = state->cps1_cps_b_regs[cps1_game_config->layer_control/2];
	914	layercontrol = state->cps1_cps_b_regs[state->cps1_game_config->layer_control/2];
916	915
917	916	/* Get video memory base registers */
918	917	cps1_get_video_base(state);

src/mess/video/gb.c

r9784	r9785
15	15	***************************************************************************/
16	16
17	17	#include "emu.h"
18		#include "includes/gb.h"
19	18	#include "cpu/lr35902/lr35902.h"
20	19	#include "profiler.h"
	20	#include "includes/gb.h"
21	21
22		#define LCDCONT      gb_lcd.gb_vid_regs[0x00]   /* LCD control register                       */
23		#define LCDSTAT      gb_lcd.gb_vid_regs[0x01]   /* LCD status register                        */
24		#define SCROLLY      gb_lcd.gb_vid_regs[0x02]   /* Starting Y position of the background      */
25		#define SCROLLX      gb_lcd.gb_vid_regs[0x03]   /* Starting X position of the background      */
26		#define CURLINE      gb_lcd.gb_vid_regs[0x04]   /* Current screen line being scanned          */
27		#define CMPLINE      gb_lcd.gb_vid_regs[0x05]   /* Gen. int. when scan reaches this line      */
28		#define BGRDPAL      gb_lcd.gb_vid_regs[0x07]   /* Background palette                         */
29		#define SPR0PAL      gb_lcd.gb_vid_regs[0x08]   /* Sprite palette #0                          */
30		#define SPR1PAL      gb_lcd.gb_vid_regs[0x09]   /* Sprite palette #1                          */
31		#define WNDPOSY      gb_lcd.gb_vid_regs[0x0A]   /* Window Y position                          */
32		#define WNDPOSX      gb_lcd.gb_vid_regs[0x0B]   /* Window X position                          */
33		#define KEY1      gb_lcd.gb_vid_regs[0x0D]   /* Prepare speed switch                       */
34		#define HDMA1      gb_lcd.gb_vid_regs[0x11]   /* HDMA source high byte                      */
35		#define HDMA2      gb_lcd.gb_vid_regs[0x12]   /* HDMA source low byte                       */
36		#define HDMA3      gb_lcd.gb_vid_regs[0x13]   /* HDMA destination high byte                 */
37		#define HDMA4      gb_lcd.gb_vid_regs[0x14]   /* HDMA destination low byte                  */
38		#define HDMA5      gb_lcd.gb_vid_regs[0x15]   /* HDMA length/mode/start                     */
39		#define GBCBCPS      gb_lcd.gb_vid_regs[0x28]   /* Backgound palette spec                     */
40		#define GBCBCPD      gb_lcd.gb_vid_regs[0x29]   /* Backgound palette data                     */
41		#define GBCOCPS      gb_lcd.gb_vid_regs[0x2A]   /* Object palette spec                        */
42		#define GBCOCPD      gb_lcd.gb_vid_regs[0x2B]   /* Object palette data                        */
	22	#define LCDCONT      state->lcd.gb_vid_regs[0x00]   /* LCD control register                       */
	23	#define LCDSTAT      state->lcd.gb_vid_regs[0x01]   /* LCD status register                        */
	24	#define SCROLLY      state->lcd.gb_vid_regs[0x02]   /* Starting Y position of the background      */
	25	#define SCROLLX      state->lcd.gb_vid_regs[0x03]   /* Starting X position of the background      */
	26	#define CURLINE      state->lcd.gb_vid_regs[0x04]   /* Current screen line being scanned          */
	27	#define CMPLINE      state->lcd.gb_vid_regs[0x05]   /* Gen. int. when scan reaches this line      */
	28	#define BGRDPAL      state->lcd.gb_vid_regs[0x07]   /* Background palette                         */
	29	#define SPR0PAL      state->lcd.gb_vid_regs[0x08]   /* Sprite palette #0                          */
	30	#define SPR1PAL      state->lcd.gb_vid_regs[0x09]   /* Sprite palette #1                          */
	31	#define WNDPOSY      state->lcd.gb_vid_regs[0x0A]   /* Window Y position                          */
	32	#define WNDPOSX      state->lcd.gb_vid_regs[0x0B]   /* Window X position                          */
	33	#define KEY1      state->lcd.gb_vid_regs[0x0D]   /* Prepare speed switch                       */
	34	#define HDMA1      state->lcd.gb_vid_regs[0x11]   /* HDMA source high byte                      */
	35	#define HDMA2      state->lcd.gb_vid_regs[0x12]   /* HDMA source low byte                       */
	36	#define HDMA3      state->lcd.gb_vid_regs[0x13]   /* HDMA destination high byte                 */
	37	#define HDMA4      state->lcd.gb_vid_regs[0x14]   /* HDMA destination low byte                  */
	38	#define HDMA5      state->lcd.gb_vid_regs[0x15]   /* HDMA length/mode/start                     */
	39	#define GBCBCPS      state->lcd.gb_vid_regs[0x28]   /* Backgound palette spec                     */
	40	#define GBCBCPD      state->lcd.gb_vid_regs[0x29]   /* Backgound palette data                     */
	41	#define GBCOCPS      state->lcd.gb_vid_regs[0x2A]   /* Object palette spec                        */
	42	#define GBCOCPD      state->lcd.gb_vid_regs[0x2B]   /* Object palette data                        */
43	43
44	44	enum {
45	45	UNLOCKED=0,
46	46	LOCKED
47	47	};
48	48
49		#define _NR_GB_VID_REGS      0x40
50	49
51		struct layer_struct {
52		UINT8  enabled;
53		UINT8  *bg_tiles;
54		UINT8  *bg_map;
55		UINT8  xindex;
56		UINT8  xshift;
57		UINT8  xstart;
58		UINT8  xend;
59		/* GBC specific */
60		UINT8  *gbc_map;
61		INT16  bgline;
62		};
63
64		static struct gb_lcd_struct {
65		int   window_lines_drawn;
66
67		UINT8   gb_vid_regs[_NR_GB_VID_REGS];
68		UINT8   bg_zbuf[160];
69
70		UINT16   cgb_bpal[32];   /* CGB current background palette table */
71		UINT16   cgb_spal[32];   /* CGB current sprite palette table */
72
73		UINT8   gb_bpal[4];      /* Background palette */
74		UINT8   gb_spal0[4];   /* Sprite 0 palette */
75		UINT8   gb_spal1[4];   /* Sprite 1 palette */
76
77		/* Things used to render current line */
78		int   current_line;      /* Current line */
79		int cmp_line;         /* Compare line */
80		int   sprCount;         /* Number of sprites on current line */
81		int   sprite[10];         /* References to sprites to draw on current line */
82		int   previous_line;      /* Previous line we've drawn in */
83		int   start_x;         /* Pixel to start drawing from (inclusive) */
84		int   end_x;            /* Pixel to end drawing (exclusive) */
85		int mode;            /* Keep track of internal STAT mode */
86		int state;            /* Current state of the video state machine */
87		int lcd_irq_line;
88		int triggering_line_irq;
89		int line_irq;
90		int triggering_mode_irq;
91		int mode_irq;
92		int delayed_line_irq;
93		int sprite_cycles;
94		int scrollx_adjust;
95		int oam_locked;
96		int vram_locked;
97		int pal_locked;
98		int hdma_enabled;
99		int hdma_possible;
100		struct layer_struct   layer[2];
101		emu_timer   *lcd_timer;
102		int gbc_mode;
103
104		region_info   *gb_vram;      /* Pointer to VRAM */
105		region_info *gb_oam;      /* Pointer to OAM memory */
106		UINT8   *gb_vram_ptr;
107		UINT8   *gb_chrgen;      /* Character generator */
108		UINT8   *gb_bgdtab;      /* Background character table */
109		UINT8   *gb_wndtab;      /* Window character table */
110		UINT8   gb_tile_no_mod;
111		UINT8   *gbc_chrgen;   /* CGB Character generator */
112		UINT8   *gbc_bgdtab;   /* CGB Background character table */
113		UINT8   *gbc_wndtab;   /* CGB Window character table */
114		} gb_lcd;
115
116		static void (*update_scanline)( running_machine *machine );
117
118	50	/* Prototypes */
119	51	static TIMER_CALLBACK(gb_lcd_timer_proc);
120	52	static TIMER_CALLBACK(gbc_lcd_timer_proc);
r9784	r9785
166	98
167	99	PALETTE_INIT( sgb )
168	100	{
	101	gb_state *state = machine->driver_data<gb_state>();
169	102	int ii, r, g, b;
170	103
171	104	for( ii = 0; ii < 32768; ii++ )
r9784	r9785
177	110	}
178	111
179	112	/* Some default colours for non-SGB games */
180		sgb_pal[0] = 32767;
181		sgb_pal[1] = 21140;
182		sgb_pal[2] = 10570;
183		sgb_pal[3] = 0;
	113	state->sgb_pal[0] = 32767;
	114	state->sgb_pal[1] = 21140;
	115	state->sgb_pal[2] = 10570;
	116	state->sgb_pal[3] = 0;
184	117	/* The rest of the colortable can be black */
185	118	for( ii = 4; ii < 8*16; ii++ )
186		sgb_pal[ii] = 0;
	119	state->sgb_pal[ii] = 0;
187	120	}
188	121
189	122	PALETTE_INIT( gbc )
190	123	{
	124	gb_state *state = machine->driver_data<gb_state>();
191	125	int ii, r, g, b;
192	126
193	127	for( ii = 0; ii < 32768; ii++ )
r9784	r9785
200	134
201	135	/* Background is initialised as white */
202	136	for( ii = 0; ii < 32; ii++ )
203		gb_lcd.cgb_bpal[ii] = 32767;
	137	state->lcd.cgb_bpal[ii] = 32767;
204	138	/* Sprites are supposed to be uninitialized, but we'll make them black */
205	139	for( ii = 0; ii < 32; ii++ )
206		gb_lcd.cgb_spal[ii] = 0;
	140	state->lcd.cgb_spal[ii] = 0;
207	141	}
208	142
209	143	PALETTE_INIT( megaduck )
r9784	r9785
225	159	Select which sprites should be drawn for the current scanline and return the
226	160	number of sprites selected.
227	161	*/
228		static void gb_select_sprites( void )
	162	static void gb_select_sprites( gb_state *state )
229	163	{
230	164	int   i, /*yindex,*/ line, height;
231		UINT8   *oam = gb_lcd.gb_oam->base() + 39 * 4;
	165	UINT8   *oam = state->lcd.gb_oam->base() + 39 * 4;
232	166
233		gb_lcd.sprCount = 0;
	167	state->lcd.sprCount = 0;
234	168
235	169	/* If video hardware is enabled and sprites are enabled */
236	170	if ( ( LCDCONT & 0x80 ) && ( LCDCONT & 0x02 ) )
r9784	r9785
245	179	height = 8;
246	180	}
247	181
248		//yindex = gb_lcd.current_line;
249		line = gb_lcd.current_line + 16;
	182	//yindex = state->lcd.current_line;
	183	line = state->lcd.current_line + 16;
250	184
251	185	for( i = 39; i >= 0; i-- )
252	186	{
r9784	r9785
254	188	{
255	189	/* We limit the sprite count to max 10 here;
256	190	proper games should not exceed this... */
257		if ( gb_lcd.sprCount < 10 )
	191	if ( state->lcd.sprCount < 10 )
258	192	{
259		gb_lcd.sprite[gb_lcd.sprCount] = i;
260		gb_lcd.sprCount++;
	193	state->lcd.sprite[state->lcd.sprCount] = i;
	194	state->lcd.sprCount++;
261	195	}
262	196	}
263	197	oam -= 4;
r9784	r9785
267	201
268	202	INLINE void gb_update_sprites ( running_machine *machine )
269	203	{
	204	gb_state *state = machine->driver_data<gb_state>();
270	205	bitmap_t *bitmap = machine->generic.tmpbitmap;
271	206	UINT8 height, tilemask, line, *oam, *vram;
272	207	int i, yindex;
r9784	r9785
282	217	tilemask = 0xFF;
283	218	}
284	219
285		yindex = gb_lcd.current_line;
286		line = gb_lcd.current_line + 16;
	220	yindex = state->lcd.current_line;
	221	line = state->lcd.current_line + 16;
287	222
288		oam = gb_lcd.gb_oam->base() + 39 * 4;
289		vram = gb_lcd.gb_vram->base();
	223	oam = state->lcd.gb_oam->base() + 39 * 4;
	224	vram = state->lcd.gb_vram->base();
290	225	for (i = 39; i >= 0; i--)
291	226	{
292	227	/* if sprite is on current line && x-coordinate && x-coordinate is < 168 */
r9784	r9785
296	231	UINT8 bit, *spal;
297	232	int xindex, adr;
298	233
299		spal = (oam[3] & 0x10) ? gb_lcd.gb_spal1 : gb_lcd.gb_spal0;
	234	spal = (oam[3] & 0x10) ? state->lcd.gb_spal1 : state->lcd.gb_spal0;
300	235	xindex = oam[1] - 8;
301	236	if (oam[3] & 0x40)         /* flip y ? */
302	237	{
r9784	r9785
314	249	for (bit = 0; bit < 8; bit++, xindex++)
315	250	{
316	251	register int colour = ((data & 0x0100) ? 2 : 0) | ((data & 0x0001) ? 1 : 0);
317		if (colour && !gb_lcd.bg_zbuf[xindex] && xindex >= 0 && xindex < 160)
	252	if (colour && !state->lcd.bg_zbuf[xindex] && xindex >= 0 && xindex < 160)
318	253	gb_plot_pixel(bitmap, xindex, yindex, spal[colour]);
319	254	data >>= 1;
320	255	}
r9784	r9785
332	267	for (bit = 0; bit < 8 && xindex < 160; bit++, xindex++)
333	268	{
334	269	register int colour = ((data & 0x8000) ? 2 : 0) | ((data & 0x0080) ? 1 : 0);
335		if (colour && !gb_lcd.bg_zbuf[xindex] && xindex >= 0 && xindex < 160)
	270	if (colour && !state->lcd.bg_zbuf[xindex] && xindex >= 0 && xindex < 160)
336	271	gb_plot_pixel(bitmap, xindex, yindex, spal[colour]);
337	272	data <<= 1;
338	273	}
r9784	r9785
354	289
355	290	static void gb_update_scanline( running_machine *machine )
356	291	{
	292	gb_state *state = machine->driver_data<gb_state>();
357	293	bitmap_t *bitmap = machine->generic.tmpbitmap;
358	294
359	295	g_profiler.start(PROFILER_VIDEO);
r9784	r9785
362	298	if ( ( LCDSTAT & 0x03 ) == 0x03 )
363	299	{
364	300	/* Calculate number of pixels to render based on time still left on the timer */
365		UINT32 cycles_to_go = machine->device<cpu_device>("maincpu")->attotime_to_cycles(timer_timeleft( gb_lcd.lcd_timer ) );
	301	UINT32 cycles_to_go = machine->device<cpu_device>("maincpu")->attotime_to_cycles(timer_timeleft( state->lcd.lcd_timer ) );
366	302	int l = 0;
367	303
368		if ( gb_lcd.start_x < 0 )
	304	if ( state->lcd.start_x < 0 )
369	305	{
370	306	/* Window is enabled if the hardware says so AND the current scanline is
371	307	* within the window AND the window X coordinate is <=166 */
372		gb_lcd.layer[1].enabled = ( ( LCDCONT & 0x20 ) && ( gb_lcd.current_line >= WNDPOSY ) && ( WNDPOSX <= 166 ) ) ? 1 : 0;
	308	state->lcd.layer[1].enabled = ( ( LCDCONT & 0x20 ) && ( state->lcd.current_line >= WNDPOSY ) && ( WNDPOSX <= 166 ) ) ? 1 : 0;
373	309
374	310	/* BG is enabled if the hardware says so AND (window_off OR (window_on
375	311	* AND window's X position is >=7 ) ) */
376		gb_lcd.layer[0].enabled = ( ( LCDCONT & 0x01 ) && ( ( ! gb_lcd.layer[1].enabled ) || ( gb_lcd.layer[1].enabled && ( WNDPOSX >= 7 ) ) ) ) ? 1 : 0;
	312	state->lcd.layer[0].enabled = ( ( LCDCONT & 0x01 ) && ( ( ! state->lcd.layer[1].enabled ) || ( state->lcd.layer[1].enabled && ( WNDPOSX >= 7 ) ) ) ) ? 1 : 0;
377	313
378		if ( gb_lcd.layer[0].enabled )
	314	if ( state->lcd.layer[0].enabled )
379	315	{
380		gb_lcd.layer[0].bgline = ( SCROLLY + gb_lcd.current_line ) & 0xFF;
381		gb_lcd.layer[0].bg_map = gb_lcd.gb_bgdtab;
382		gb_lcd.layer[0].bg_tiles = gb_lcd.gb_chrgen;
383		gb_lcd.layer[0].xindex = SCROLLX >> 3;
384		gb_lcd.layer[0].xshift = SCROLLX & 7;
385		gb_lcd.layer[0].xstart = 0;
386		gb_lcd.layer[0].xend = 160;
	316	state->lcd.layer[0].bgline = ( SCROLLY + state->lcd.current_line ) & 0xFF;
	317	state->lcd.layer[0].bg_map = state->lcd.gb_bgdtab;
	318	state->lcd.layer[0].bg_tiles = state->lcd.gb_chrgen;
	319	state->lcd.layer[0].xindex = SCROLLX >> 3;
	320	state->lcd.layer[0].xshift = SCROLLX & 7;
	321	state->lcd.layer[0].xstart = 0;
	322	state->lcd.layer[0].xend = 160;
387	323	}
388	324
389		if ( gb_lcd.layer[1].enabled )
	325	if ( state->lcd.layer[1].enabled )
390	326	{
391	327	int xpos;
392	328
r9784	r9785
394	330	if ( xpos < 0 )
395	331	xpos = 0;
396	332
397		gb_lcd.layer[1].bgline = gb_lcd.window_lines_drawn;
398		gb_lcd.layer[1].bg_map = gb_lcd.gb_wndtab;
399		gb_lcd.layer[1].bg_tiles = gb_lcd.gb_chrgen;
400		gb_lcd.layer[1].xindex = 0;
401		gb_lcd.layer[1].xshift = 0;
402		gb_lcd.layer[1].xstart = xpos;
403		gb_lcd.layer[1].xend = 160;
404		gb_lcd.layer[0].xend = xpos;
	333	state->lcd.layer[1].bgline = state->lcd.window_lines_drawn;
	334	state->lcd.layer[1].bg_map = state->lcd.gb_wndtab;
	335	state->lcd.layer[1].bg_tiles = state->lcd.gb_chrgen;
	336	state->lcd.layer[1].xindex = 0;
	337	state->lcd.layer[1].xshift = 0;
	338	state->lcd.layer[1].xstart = xpos;
	339	state->lcd.layer[1].xend = 160;
	340	state->lcd.layer[0].xend = xpos;
405	341	}
406		gb_lcd.start_x = 0;
	342	state->lcd.start_x = 0;
407	343	}
408	344
409	345	if ( cycles_to_go < 160 )
410	346	{
411		gb_lcd.end_x = MIN(160 - cycles_to_go,160);
	347	state->lcd.end_x = MIN(160 - cycles_to_go,160);
412	348	/* Draw empty pixels when the background is disabled */
413	349	if ( ! ( LCDCONT & 0x01 ) )
414	350	{
415	351	rectangle r;
416		r.min_y = r.max_y = gb_lcd.current_line;
417		r.min_x = gb_lcd.start_x;
418		r.max_x = gb_lcd.end_x - 1;
419		bitmap_fill( bitmap, &r , gb_lcd.gb_bpal[0]);
	352	r.min_y = r.max_y = state->lcd.current_line;
	353	r.min_x = state->lcd.start_x;
	354	r.max_x = state->lcd.end_x - 1;
	355	bitmap_fill( bitmap, &r , state->lcd.gb_bpal[0]);
420	356	}
421	357	while ( l < 2 )
422	358	{
r9784	r9785
424	360	UINT16   data;
425	361	int   i, tile_index;
426	362
427		if ( ! gb_lcd.layer[l].enabled )
	363	if ( ! state->lcd.layer[l].enabled )
428	364	{
429	365	l++;
430	366	continue;
431	367	}
432		map = gb_lcd.layer[l].bg_map + ( ( gb_lcd.layer[l].bgline << 2 ) & 0x3E0 );
433		tiles = gb_lcd.layer[l].bg_tiles + ( ( gb_lcd.layer[l].bgline & 7 ) << 1 );
434		xindex = gb_lcd.start_x;
435		if ( xindex < gb_lcd.layer[l].xstart )
436		xindex = gb_lcd.layer[l].xstart;
437		i = gb_lcd.end_x;
438		if ( i > gb_lcd.layer[l].xend )
439		i = gb_lcd.layer[l].xend;
	368	map = state->lcd.layer[l].bg_map + ( ( state->lcd.layer[l].bgline << 2 ) & 0x3E0 );
	369	tiles = state->lcd.layer[l].bg_tiles + ( ( state->lcd.layer[l].bgline & 7 ) << 1 );
	370	xindex = state->lcd.start_x;
	371	if ( xindex < state->lcd.layer[l].xstart )
	372	xindex = state->lcd.layer[l].xstart;
	373	i = state->lcd.end_x;
	374	if ( i > state->lcd.layer[l].xend )
	375	i = state->lcd.layer[l].xend;
440	376	i = i - xindex;
441	377
442		tile_index = ( map[ gb_lcd.layer[l].xindex ] ^ gb_lcd.gb_tile_no_mod ) * 16;
	378	tile_index = ( map[ state->lcd.layer[l].xindex ] ^ state->lcd.gb_tile_no_mod ) * 16;
443	379	data = tiles[ tile_index ] | ( tiles[ tile_index+1 ] << 8 );
444		data <<= gb_lcd.layer[l].xshift;
	380	data <<= state->lcd.layer[l].xshift;
445	381
446	382	while ( i > 0 )
447	383	{
448		while ( ( gb_lcd.layer[l].xshift < 8 ) && i )
	384	while ( ( state->lcd.layer[l].xshift < 8 ) && i )
449	385	{
450	386	register int colour = ( ( data & 0x8000 ) ? 2 : 0 ) | ( ( data & 0x0080 ) ? 1 : 0 );
451		gb_plot_pixel( bitmap, xindex, gb_lcd.current_line, gb_lcd.gb_bpal[ colour ] );
452		gb_lcd.bg_zbuf[ xindex ] = colour;
	387	gb_plot_pixel( bitmap, xindex, state->lcd.current_line, state->lcd.gb_bpal[ colour ] );
	388	state->lcd.bg_zbuf[ xindex ] = colour;
453	389	xindex++;
454	390	data <<= 1;
455		gb_lcd.layer[l].xshift++;
	391	state->lcd.layer[l].xshift++;
456	392	i--;
457	393	}
458		if ( gb_lcd.layer[l].xshift == 8 )
	394	if ( state->lcd.layer[l].xshift == 8 )
459	395	{
460	396	/* Take possible changes to SCROLLY into account */
461	397	if ( l == 0 )
462	398	{
463		gb_lcd.layer[0].bgline = ( SCROLLY + gb_lcd.current_line ) & 0xFF;
464		map = gb_lcd.layer[l].bg_map + ( ( gb_lcd.layer[l].bgline << 2 ) & 0x3E0 );
465		tiles = gb_lcd.layer[l].bg_tiles + ( ( gb_lcd.layer[l].bgline & 7 ) << 1 );
	399	state->lcd.layer[0].bgline = ( SCROLLY + state->lcd.current_line ) & 0xFF;
	400	map = state->lcd.layer[l].bg_map + ( ( state->lcd.layer[l].bgline << 2 ) & 0x3E0 );
	401	tiles = state->lcd.layer[l].bg_tiles + ( ( state->lcd.layer[l].bgline & 7 ) << 1 );
466	402	}
467	403
468		gb_lcd.layer[l].xindex = ( gb_lcd.layer[l].xindex + 1 ) & 31;
469		gb_lcd.layer[l].xshift = 0;
470		tile_index = ( map[ gb_lcd.layer[l].xindex ] ^ gb_lcd.gb_tile_no_mod ) * 16;
	404	state->lcd.layer[l].xindex = ( state->lcd.layer[l].xindex + 1 ) & 31;
	405	state->lcd.layer[l].xshift = 0;
	406	tile_index = ( map[ state->lcd.layer[l].xindex ] ^ state->lcd.gb_tile_no_mod ) * 16;
471	407	data = tiles[ tile_index ] | ( tiles[ tile_index+1 ] << 8 );
472	408	}
473	409	}
474	410	l++;
475	411	}
476		if ( gb_lcd.end_x == 160 && LCDCONT & 0x02 )
	412	if ( state->lcd.end_x == 160 && LCDCONT & 0x02 )
477	413	{
478	414	gb_update_sprites(machine);
479	415	}
480		gb_lcd.start_x = gb_lcd.end_x;
	416	state->lcd.start_x = state->lcd.end_x;
481	417	}
482	418	}
483	419	else
r9784	r9785
485	421	if ( ! ( LCDCONT & 0x80 ) )
486	422	{
487	423	/* Draw an empty line when LCD is disabled */
488		if ( gb_lcd.previous_line != gb_lcd.current_line )
	424	if ( state->lcd.previous_line != state->lcd.current_line )
489	425	{
490		if ( gb_lcd.current_line < 144 )
	426	if ( state->lcd.current_line < 144 )
491	427	{
492	428	screen_device *screen = machine->first_screen();
493	429	rectangle r1;
494	430	const rectangle &r = screen->visible_area();
495		r1.min_y = r1.max_y = gb_lcd.current_line;
	431	r1.min_y = r1.max_y = state->lcd.current_line;
496	432	r1.min_x = r.min_x;
497	433	r1.max_x = r.max_x;
498	434	bitmap_fill( bitmap, &r1 , 0);
499	435	}
500		gb_lcd.previous_line = gb_lcd.current_line;
	436	state->lcd.previous_line = state->lcd.current_line;
501	437	}
502	438	}
503	439	}
r9784	r9785
509	445
510	446	INLINE void sgb_update_sprites (running_machine *machine)
511	447	{
	448	gb_state *state = machine->driver_data<gb_state>();
512	449	bitmap_t *bitmap = machine->generic.tmpbitmap;
513	450	UINT8 height, tilemask, line, *oam, *vram, pal;
514	451	INT16 i, yindex;
r9784	r9785
525	462	}
526	463
527	464	/* Offset to center of screen */
528		yindex = gb_lcd.current_line + SGB_YOFFSET;
529		line = gb_lcd.current_line + 16;
	465	yindex = state->lcd.current_line + SGB_YOFFSET;
	466	line = state->lcd.current_line + 16;
530	467
531		oam = gb_lcd.gb_oam->base() + 39 * 4;
532		vram = gb_lcd.gb_vram->base();
	468	oam = state->lcd.gb_oam->base() + 39 * 4;
	469	vram = state->lcd.gb_vram->base();
533	470	for (i = 39; i >= 0; i--)
534	471	{
535	472	/* if sprite is on current line && x-coordinate && x-coordinate is < 168 */
r9784	r9785
540	477	INT16 xindex;
541	478	int adr;
542	479
543		spal = (oam[3] & 0x10) ? gb_lcd.gb_spal1 : gb_lcd.gb_spal0;
	480	spal = (oam[3] & 0x10) ? state->lcd.gb_spal1 : state->lcd.gb_spal0;
544	481	xindex = oam[1] - 8;
545	482	if (oam[3] & 0x40)         /* flip y ? */
546	483	{
r9784	r9785
553	490	data = (vram[adr + 1] << 8) | vram[adr];
554	491
555	492	/* Find the palette to use */
556		pal = sgb_pal_map[(xindex >> 3)][((yindex - SGB_YOFFSET) >> 3)] << 2;
	493	pal = state->sgb_pal_map[(xindex >> 3)][((yindex - SGB_YOFFSET) >> 3)] << 2;
557	494
558	495	/* Offset to center of screen */
559	496	xindex += SGB_XOFFSET;
r9784	r9785
564	501	for (bit = 0; bit < 8; bit++, xindex++)
565	502	{
566	503	register int colour = ((data & 0x0100) ? 2 : 0) | ((data & 0x0001) ? 1 : 0);
567		if ((xindex >= SGB_XOFFSET && xindex < SGB_XOFFSET + 160) && colour && !gb_lcd.bg_zbuf[xindex - SGB_XOFFSET])
568		gb_plot_pixel(bitmap, xindex, yindex, sgb_pal[pal + spal[colour]]);
	504	if ((xindex >= SGB_XOFFSET && xindex < SGB_XOFFSET + 160) && colour && !state->lcd.bg_zbuf[xindex - SGB_XOFFSET])
	505	gb_plot_pixel(bitmap, xindex, yindex, state->sgb_pal[pal + spal[colour]]);
569	506	data >>= 1;
570	507	}
571	508	break;
r9784	r9785
574	511	{
575	512	register int colour = ((data & 0x0100) ? 2 : 0) | ((data & 0x0001) ? 1 : 0);
576	513	if ((xindex >= SGB_XOFFSET && xindex < SGB_XOFFSET + 160) && colour)
577		gb_plot_pixel(bitmap, xindex, yindex, sgb_pal[pal + spal[colour]]);
	514	gb_plot_pixel(bitmap, xindex, yindex, state->sgb_pal[pal + spal[colour]]);
578	515	data >>= 1;
579	516	}
580	517	break;
r9784	r9785
582	519	for (bit = 0; bit < 8; bit++, xindex++)
583	520	{
584	521	register int colour = ((data & 0x8000) ? 2 : 0) | ((data & 0x0080) ? 1 : 0);
585		if ((xindex >= SGB_XOFFSET && xindex < SGB_XOFFSET + 160) && colour && !gb_lcd.bg_zbuf[xindex - SGB_XOFFSET])
586		gb_plot_pixel(bitmap, xindex, yindex, sgb_pal[pal + spal[colour]]);
	522	if ((xindex >= SGB_XOFFSET && xindex < SGB_XOFFSET + 160) && colour && !state->lcd.bg_zbuf[xindex - SGB_XOFFSET])
	523	gb_plot_pixel(bitmap, xindex, yindex, state->sgb_pal[pal + spal[colour]]);
587	524	data <<= 1;
588	525	}
589	526	break;
r9784	r9785
592	529	{
593	530	register int colour = ((data & 0x8000) ? 2 : 0) | ((data & 0x0080) ? 1 : 0);
594	531	if ((xindex >= SGB_XOFFSET && xindex < SGB_XOFFSET + 160) && colour)
595		gb_plot_pixel(bitmap, xindex, yindex, sgb_pal[pal + spal[colour]]);
	532	gb_plot_pixel(bitmap, xindex, yindex, state->sgb_pal[pal + spal[colour]]);
596	533	data <<= 1;
597	534	}
598	535	break;
r9784	r9785
604	541
605	542	static void sgb_refresh_border(running_machine *machine)
606	543	{
	544	gb_state *state = machine->driver_data<gb_state>();
607	545	UINT16 data, data2;
608	546	UINT16 yidx, xidx, xindex;
609	547	UINT8 *map, *tiles, *tiles2;
610	548	UINT8 pal, i;
611	549	bitmap_t *bitmap = machine->generic.tmpbitmap;
612	550
613		map = sgb_tile_map - 64;
	551	map = state->sgb_tile_map - 64;
614	552
615	553	for( yidx = 0; yidx < 224; yidx++ )
616	554	{
r9784	r9785
619	557	for( xidx = 0; xidx < 64; xidx+=2 )
620	558	{
621	559	if( map[xidx+1] & 0x80 ) /* Vertical flip */
622		tiles = sgb_tile_data + ( ( 7 - ( yidx % 8 ) ) << 1 );
	560	tiles = state->sgb_tile_data + ( ( 7 - ( yidx % 8 ) ) << 1 );
623	561	else /* No vertical flip */
624		tiles = sgb_tile_data + ( ( yidx % 8 ) << 1 );
	562	tiles = state->sgb_tile_data + ( ( yidx % 8 ) << 1 );
625	563	tiles2 = tiles + 16;
626	564
627	565	pal = (map[xidx+1] & 0x1C) >> 2;
r9784	r9785
629	567	pal = 1;
630	568	pal <<= 4;
631	569
632		if( sgb_hack )
	570	if( state->sgb_hack )
633	571	{ /* A few games do weird stuff */
634	572	UINT8 tileno = map[xidx];
635	573	if( tileno >= 128 ) tileno = ((64 + tileno) % 128) + 128;
r9784	r9785
667	605	if( !((yidx >= SGB_YOFFSET && yidx < SGB_YOFFSET + 144) &&
668	606	(xindex >= SGB_XOFFSET && xindex < SGB_XOFFSET + 160)) )
669	607	{
670		gb_plot_pixel(bitmap, xindex, yidx, sgb_pal[pal + colour]);
	608	gb_plot_pixel(bitmap, xindex, yidx, state->sgb_pal[pal + colour]);
671	609	}
672	610	xindex++;
673	611	}
r9784	r9785
677	615
678	616	static void sgb_update_scanline( running_machine *machine )
679	617	{
	618	gb_state *state = machine->driver_data<gb_state>();
680	619	bitmap_t *bitmap = machine->generic.tmpbitmap;
681	620
682	621	g_profiler.start(PROFILER_VIDEO);
r9784	r9785
684	623	if ( ( LCDSTAT & 0x03 ) == 0x03 )
685	624	{
686	625	/* Calcuate number of pixels to render based on time still left on the timer */
687		UINT32 cycles_to_go = machine->device<cpu_device>("maincpu")->attotime_to_cycles(timer_timeleft( gb_lcd.lcd_timer ) );
	626	UINT32 cycles_to_go = machine->device<cpu_device>("maincpu")->attotime_to_cycles(timer_timeleft( state->lcd.lcd_timer ) );
688	627	int l = 0;
689	628
690		if ( gb_lcd.start_x < 0 )
	629	if ( state->lcd.start_x < 0 )
691	630	{
692	631	/* Window is enabled if the hardware says so AND the current scanline is
693	632	* within the window AND the window X coordinate is <=166 */
694		gb_lcd.layer[1].enabled = ((LCDCONT & 0x20) && gb_lcd.current_line >= WNDPOSY && WNDPOSX <= 166) ? 1 : 0;
	633	state->lcd.layer[1].enabled = ((LCDCONT & 0x20) && state->lcd.current_line >= WNDPOSY && WNDPOSX <= 166) ? 1 : 0;
695	634
696	635	/* BG is enabled if the hardware says so AND (window_off OR (window_on
697	636	* AND window's X position is >=7 ) ) */
698		gb_lcd.layer[0].enabled = ((LCDCONT & 0x01) && ((!gb_lcd.layer[1].enabled) || (gb_lcd.layer[1].enabled && WNDPOSX >= 7))) ? 1 : 0;
	637	state->lcd.layer[0].enabled = ((LCDCONT & 0x01) && ((!state->lcd.layer[1].enabled) || (state->lcd.layer[1].enabled && WNDPOSX >= 7))) ? 1 : 0;
699	638
700		if ( gb_lcd.layer[0].enabled )
	639	if ( state->lcd.layer[0].enabled )
701	640	{
702		gb_lcd.layer[0].bgline = ( SCROLLY + gb_lcd.current_line ) & 0xFF;
703		gb_lcd.layer[0].bg_map = gb_lcd.gb_bgdtab;
704		gb_lcd.layer[0].bg_tiles = gb_lcd.gb_chrgen;
705		gb_lcd.layer[0].xindex = SCROLLX >> 3;
706		gb_lcd.layer[0].xshift = SCROLLX & 7;
707		gb_lcd.layer[0].xstart = 0;
708		gb_lcd.layer[0].xend = 160;
	641	state->lcd.layer[0].bgline = ( SCROLLY + state->lcd.current_line ) & 0xFF;
	642	state->lcd.layer[0].bg_map = state->lcd.gb_bgdtab;
	643	state->lcd.layer[0].bg_tiles = state->lcd.gb_chrgen;
	644	state->lcd.layer[0].xindex = SCROLLX >> 3;
	645	state->lcd.layer[0].xshift = SCROLLX & 7;
	646	state->lcd.layer[0].xstart = 0;
	647	state->lcd.layer[0].xend = 160;
709	648	}
710	649
711		if ( gb_lcd.layer[1].enabled )
	650	if ( state->lcd.layer[1].enabled )
712	651	{
713	652	int xpos;
714	653
r9784	r9785
717	656	if (xpos < 0)
718	657	xpos = 0;
719	658
720		gb_lcd.layer[1].bgline = gb_lcd.window_lines_drawn;
721		gb_lcd.layer[1].bg_map = gb_lcd.gb_wndtab;
722		gb_lcd.layer[1].bg_tiles = gb_lcd.gb_chrgen;
723		gb_lcd.layer[1].xindex = 0;
724		gb_lcd.layer[1].xshift = 0;
725		gb_lcd.layer[1].xstart = xpos;
726		gb_lcd.layer[1].xend = 160;
727		gb_lcd.layer[0].xend = xpos;
	659	state->lcd.layer[1].bgline = state->lcd.window_lines_drawn;
	660	state->lcd.layer[1].bg_map = state->lcd.gb_wndtab;
	661	state->lcd.layer[1].bg_tiles = state->lcd.gb_chrgen;
	662	state->lcd.layer[1].xindex = 0;
	663	state->lcd.layer[1].xshift = 0;
	664	state->lcd.layer[1].xstart = xpos;
	665	state->lcd.layer[1].xend = 160;
	666	state->lcd.layer[0].xend = xpos;
728	667	}
729		gb_lcd.start_x = 0;
	668	state->lcd.start_x = 0;
730	669	}
731	670
732	671	if ( cycles_to_go == 0 )
r9784	r9785
734	673
735	674	/* Does this belong here? or should it be moved to the else block */
736	675	/* Handle SGB mask */
737		switch( sgb_window_mask )
	676	switch( state->sgb_window_mask )
738	677	{
739	678	case 1: /* Freeze screen */
740	679	return;
r9784	r9785
759	698	}
760	699
761	700	/* Draw the "border" if we're on the first line */
762		if ( gb_lcd.current_line == 0 )
	701	if ( state->lcd.current_line == 0 )
763	702	{
764	703	sgb_refresh_border(machine);
765	704	}
766	705	}
767	706	if ( cycles_to_go < 160 )
768	707	{
769		gb_lcd.end_x = MIN(160 - cycles_to_go,160);
	708	state->lcd.end_x = MIN(160 - cycles_to_go,160);
770	709
771	710	/* if background or screen disabled clear line */
772	711	if ( ! ( LCDCONT & 0x01 ) )
r9784	r9785
774	713	rectangle r;
775	714	r.min_x = SGB_XOFFSET;
776	715	r.max_x = SGB_XOFFSET + 160 - 1;
777		r.min_y = r.max_y = gb_lcd.current_line + SGB_YOFFSET;
	716	r.min_y = r.max_y = state->lcd.current_line + SGB_YOFFSET;
778	717	bitmap_fill( bitmap, &r , 0);
779	718	}
780	719	while( l < 2 )
r9784	r9785
783	722	UINT16   data;
784	723	int   i, tile_index;
785	724
786		if ( ! gb_lcd.layer[l].enabled )
	725	if ( ! state->lcd.layer[l].enabled )
787	726	{
788	727	l++;
789	728	continue;
790	729	}
791		map = gb_lcd.layer[l].bg_map + ( ( gb_lcd.layer[l].bgline << 2 ) & 0x3E0 );
792		tiles = gb_lcd.layer[l].bg_tiles + ( ( gb_lcd.layer[l].bgline & 7 ) << 1 );
793		xindex = gb_lcd.start_x;
794		if ( xindex < gb_lcd.layer[l].xstart )
795		xindex = gb_lcd.layer[l].xstart;
796		i = gb_lcd.end_x;
797		if ( i > gb_lcd.layer[l].xend )
798		i = gb_lcd.layer[l].xend;
	730	map = state->lcd.layer[l].bg_map + ( ( state->lcd.layer[l].bgline << 2 ) & 0x3E0 );
	731	tiles = state->lcd.layer[l].bg_tiles + ( ( state->lcd.layer[l].bgline & 7 ) << 1 );
	732	xindex = state->lcd.start_x;
	733	if ( xindex < state->lcd.layer[l].xstart )
	734	xindex = state->lcd.layer[l].xstart;
	735	i = state->lcd.end_x;
	736	if ( i > state->lcd.layer[l].xend )
	737	i = state->lcd.layer[l].xend;
799	738	i = i - xindex;
800	739
801		tile_index = (map[gb_lcd.layer[l].xindex] ^ gb_lcd.gb_tile_no_mod) * 16;
	740	tile_index = (map[state->lcd.layer[l].xindex] ^ state->lcd.gb_tile_no_mod) * 16;
802	741	data = tiles[tile_index] | ( tiles[tile_index + 1] << 8 );
803		data <<= gb_lcd.layer[l].xshift;
	742	data <<= state->lcd.layer[l].xshift;
804	743
805	744	/* Figure out which palette we're using */
806		sgb_palette = sgb_pal_map[ ( gb_lcd.end_x - i ) >> 3 ][ gb_lcd.current_line >> 3 ] << 2;
	745	sgb_palette = state->sgb_pal_map[ ( state->lcd.end_x - i ) >> 3 ][ state->lcd.current_line >> 3 ] << 2;
807	746
808	747	while( i > 0 )
809	748	{
810		while( ( gb_lcd.layer[l].xshift < 8 ) && i )
	749	while( ( state->lcd.layer[l].xshift < 8 ) && i )
811	750	{
812	751	register int colour = ( ( data & 0x8000 ) ? 2 : 0 ) | ( ( data & 0x0080 ) ? 1 : 0 );
813		gb_plot_pixel( bitmap, xindex + SGB_XOFFSET, gb_lcd.current_line + SGB_YOFFSET, sgb_pal[ sgb_palette + gb_lcd.gb_bpal[colour]] );
814		gb_lcd.bg_zbuf[xindex] = colour;
	752	gb_plot_pixel( bitmap, xindex + SGB_XOFFSET, state->lcd.current_line + SGB_YOFFSET, state->sgb_pal[ sgb_palette + state->lcd.gb_bpal[colour]] );
	753	state->lcd.bg_zbuf[xindex] = colour;
815	754	xindex++;
816	755	data <<= 1;
817		gb_lcd.layer[l].xshift++;
	756	state->lcd.layer[l].xshift++;
818	757	i--;
819	758	}
820		if ( gb_lcd.layer[l].xshift == 8 )
	759	if ( state->lcd.layer[l].xshift == 8 )
821	760	{
822	761	/* Take possible changes to SCROLLY into account */
823	762	if ( l == 0 )
824	763	{
825		gb_lcd.layer[0].bgline = ( SCROLLY + gb_lcd.current_line ) & 0xFF;
826		map = gb_lcd.layer[l].bg_map + ( ( gb_lcd.layer[l].bgline << 2 ) & 0x3E0 );
827		tiles = gb_lcd.layer[l].bg_tiles + ( ( gb_lcd.layer[l].bgline & 7 ) << 1 );
	764	state->lcd.layer[0].bgline = ( SCROLLY + state->lcd.current_line ) & 0xFF;
	765	map = state->lcd.layer[l].bg_map + ( ( state->lcd.layer[l].bgline << 2 ) & 0x3E0 );
	766	tiles = state->lcd.layer[l].bg_tiles + ( ( state->lcd.layer[l].bgline & 7 ) << 1 );
828	767	}
829	768
830		gb_lcd.layer[l].xindex = ( gb_lcd.layer[l].xindex + 1 ) & 31;
831		gb_lcd.layer[l].xshift = 0;
832		tile_index = ( map[ gb_lcd.layer[l].xindex ] ^ gb_lcd.gb_tile_no_mod ) * 16;
	769	state->lcd.layer[l].xindex = ( state->lcd.layer[l].xindex + 1 ) & 31;
	770	state->lcd.layer[l].xshift = 0;
	771	tile_index = ( map[ state->lcd.layer[l].xindex ] ^ state->lcd.gb_tile_no_mod ) * 16;
833	772	data = tiles[ tile_index ] | ( tiles[ tile_index + 1 ] << 8 );
834		sgb_palette = sgb_pal_map[ ( gb_lcd.end_x - i ) >> 3 ][ gb_lcd.current_line >> 3 ] << 2;
	773	sgb_palette = state->sgb_pal_map[ ( state->lcd.end_x - i ) >> 3 ][ state->lcd.current_line >> 3 ] << 2;
835	774	}
836	775	}
837	776	l++;
838	777	}
839		if ( ( gb_lcd.end_x == 160 ) && ( LCDCONT & 0x02 ) )
	778	if ( ( state->lcd.end_x == 160 ) && ( LCDCONT & 0x02 ) )
840	779	{
841	780	sgb_update_sprites(machine);
842	781	}
843		gb_lcd.start_x = gb_lcd.end_x;
	782	state->lcd.start_x = state->lcd.end_x;
844	783	}
845	784	}
846	785	else
r9784	r9785
848	787	if ( ! ( LCDCONT * 0x80 ) )
849	788	{
850	789	/* if screen disabled clear line */
851		if ( gb_lcd.previous_line != gb_lcd.current_line )
	790	if ( state->lcd.previous_line != state->lcd.current_line )
852	791	{
853	792	/* Also refresh border here??? */
854		if ( gb_lcd.current_line < 144 )
	793	if ( state->lcd.current_line < 144 )
855	794	{
856	795	rectangle r;
857	796	r.min_x = SGB_XOFFSET;
858	797	r.max_x = SGB_XOFFSET + 160 - 1;
859		r.min_y = r.max_y = gb_lcd.current_line + SGB_YOFFSET;
	798	r.min_y = r.max_y = state->lcd.current_line + SGB_YOFFSET;
860	799	bitmap_fill(bitmap, &r, 0);
861	800	}
862		gb_lcd.previous_line = gb_lcd.current_line;
	801	state->lcd.previous_line = state->lcd.current_line;
863	802	}
864	803	}
865	804	}
r9784	r9785
871	810
872	811	INLINE void cgb_update_sprites ( running_machine *machine )
873	812	{
	813	gb_state *state = machine->driver_data<gb_state>();
874	814	bitmap_t *bitmap = machine->generic.tmpbitmap;
875	815	UINT8 height, tilemask, line, *oam;
876	816	int i, xindex, yindex;
r9784	r9785
886	826	tilemask = 0xFF;
887	827	}
888	828
889		yindex = gb_lcd.current_line;
890		line = gb_lcd.current_line + 16;
	829	yindex = state->lcd.current_line;
	830	line = state->lcd.current_line + 16;
891	831
892		oam = gb_lcd.gb_oam->base() + 39 * 4;
	832	oam = state->lcd.gb_oam->base() + 39 * 4;
893	833	for (i = 39; i >= 0; i--)
894	834	{
895	835	/* if sprite is on current line && x-coordinate && x-coordinate is < 168 */
r9784	r9785
899	839	UINT8 bit, pal;
900	840
901	841	/* Handle mono mode for GB games */
902		if( ! gb_lcd.gbc_mode )
	842	if( ! state->lcd.gbc_mode )
903	843	pal = (oam[3] & 0x10) ? 4 : 0;
904	844	else
905	845	pal = ((oam[3] & 0x7) * 4);
r9784	r9785
907	847	xindex = oam[1] - 8;
908	848	if (oam[3] & 0x40)         /* flip y ? */
909	849	{
910		data = *((UINT16 *) &gb_lcd.gb_vram->base()[ ((oam[3] & 0x8)<<10) + (oam[2] & tilemask) * 16 + (height - 1 - line + oam[0]) * 2]);
	850	data = *((UINT16 *) &state->lcd.gb_vram->base()[ ((oam[3] & 0x8)<<10) + (oam[2] & tilemask) * 16 + (height - 1 - line + oam[0]) * 2]);
911	851	}
912	852	else
913	853	{
914		data = *((UINT16 *) &gb_lcd.gb_vram->base()[ ((oam[3] & 0x8)<<10) + (oam[2] & tilemask) * 16 + (line - oam[0]) * 2]);
	854	data = *((UINT16 *) &state->lcd.gb_vram->base()[ ((oam[3] & 0x8)<<10) + (oam[2] & tilemask) * 16 + (line - oam[0]) * 2]);
915	855	}
916	856	#ifndef LSB_FIRST
917	857	data = (data << 8) | (data >> 8);
r9784	r9785
923	863	for (bit = 0; bit < 8; bit++, xindex++)
924	864	{
925	865	register int colour = ((data & 0x0100) ? 2 : 0) | ((data & 0x0001) ? 1 : 0);
926		if (colour && !gb_lcd.bg_zbuf[xindex] && xindex >= 0 && xindex < 160)
	866	if (colour && !state->lcd.bg_zbuf[xindex] && xindex >= 0 && xindex < 160)
927	867	{
928		if ( ! gb_lcd.gbc_mode )
929		colour = pal ? gb_lcd.gb_spal1[colour] : gb_lcd.gb_spal0[colour];
930		gb_plot_pixel(bitmap, xindex, yindex, gb_lcd.cgb_spal[pal + colour]);
	868	if ( ! state->lcd.gbc_mode )
	869	colour = pal ? state->lcd.gb_spal1[colour] : state->lcd.gb_spal0[colour];
	870	gb_plot_pixel(bitmap, xindex, yindex, state->lcd.cgb_spal[pal + colour]);
931	871	}
932	872	data >>= 1;
933	873	}
r9784	r9785
936	876	for (bit = 0; bit < 8; bit++, xindex++)
937	877	{
938	878	register int colour = ((data & 0x0100) ? 2 : 0) | ((data & 0x0001) ? 1 : 0);
939		if((gb_lcd.bg_zbuf[xindex] & 0x80) && (gb_lcd.bg_zbuf[xindex] & 0x7f) && (LCDCONT & 0x1))
	879	if((state->lcd.bg_zbuf[xindex] & 0x80) && (state->lcd.bg_zbuf[xindex] & 0x7f) && (LCDCONT & 0x1))
940	880	colour = 0;
941	881	if (colour && xindex >= 0 && xindex < 160)
942	882	{
943		if ( ! gb_lcd.gbc_mode )
944		colour = pal ? gb_lcd.gb_spal1[colour] : gb_lcd.gb_spal0[colour];
945		gb_plot_pixel(bitmap, xindex, yindex, gb_lcd.cgb_spal[pal + colour]);
	883	if ( ! state->lcd.gbc_mode )
	884	colour = pal ? state->lcd.gb_spal1[colour] : state->lcd.gb_spal0[colour];
	885	gb_plot_pixel(bitmap, xindex, yindex, state->lcd.cgb_spal[pal + colour]);
946	886	}
947	887	data >>= 1;
948	888	}
r9784	r9785
951	891	for (bit = 0; bit < 8; bit++, xindex++)
952	892	{
953	893	register int colour = ((data & 0x8000) ? 2 : 0) | ((data & 0x0080) ? 1 : 0);
954		if (colour && !gb_lcd.bg_zbuf[xindex] && xindex >= 0 && xindex < 160)
	894	if (colour && !state->lcd.bg_zbuf[xindex] && xindex >= 0 && xindex < 160)
955	895	{
956		if ( ! gb_lcd.gbc_mode )
957		colour = pal ? gb_lcd.gb_spal1[colour] : gb_lcd.gb_spal0[colour];
958		gb_plot_pixel(bitmap, xindex, yindex, gb_lcd.cgb_spal[pal + colour]);
	896	if ( ! state->lcd.gbc_mode )
	897	colour = pal ? state->lcd.gb_spal1[colour] : state->lcd.gb_spal0[colour];
	898	gb_plot_pixel(bitmap, xindex, yindex, state->lcd.cgb_spal[pal + colour]);
959	899	}
960	900	data <<= 1;
961	901	}
r9784	r9785
964	904	for (bit = 0; bit < 8; bit++, xindex++)
965	905	{
966	906	register int colour = ((data & 0x8000) ? 2 : 0) | ((data & 0x0080) ? 1 : 0);
967		if((gb_lcd.bg_zbuf[xindex] & 0x80) && (gb_lcd.bg_zbuf[xindex] & 0x7f) && (LCDCONT & 0x1))
	907	if((state->lcd.bg_zbuf[xindex] & 0x80) && (state->lcd.bg_zbuf[xindex] & 0x7f) && (LCDCONT & 0x1))
968	908	colour = 0;
969	909	if (colour && xindex >= 0 && xindex < 160)
970	910	{
971		if ( ! gb_lcd.gbc_mode )
972		colour = pal ? gb_lcd.gb_spal1[colour] : gb_lcd.gb_spal0[colour];
973		gb_plot_pixel(bitmap, xindex, yindex, gb_lcd.cgb_spal[pal + colour]);
	911	if ( ! state->lcd.gbc_mode )
	912	colour = pal ? state->lcd.gb_spal1[colour] : state->lcd.gb_spal0[colour];
	913	gb_plot_pixel(bitmap, xindex, yindex, state->lcd.cgb_spal[pal + colour]);
974	914	}
975	915	data <<= 1;
976	916	}
r9784	r9785
983	923
984	924	static void cgb_update_scanline ( running_machine *machine )
985	925	{
	926	gb_state *state = machine->driver_data<gb_state>();
986	927	bitmap_t *bitmap = machine->generic.tmpbitmap;
987	928
988	929	g_profiler.start(PROFILER_VIDEO);
r9784	r9785
990	931	if ( ( LCDSTAT & 0x03 ) == 0x03 )
991	932	{
992	933	/* Calcuate number of pixels to render based on time still left on the timer */
993		UINT32 cycles_to_go = machine->device<cpu_device>("maincpu")->attotime_to_cycles(timer_timeleft( gb_lcd.lcd_timer ) );
	934	UINT32 cycles_to_go = machine->device<cpu_device>("maincpu")->attotime_to_cycles(timer_timeleft( state->lcd.lcd_timer ) );
994	935	int l = 0;
995	936
996		if ( gb_lcd.start_x < 0 )
	937	if ( state->lcd.start_x < 0 )
997	938	{
998	939	/* Window is enabled if the hardware says so AND the current scanline is
999	940	* within the window AND the window X coordinate is <=166 */
1000		gb_lcd.layer[1].enabled = ( ( LCDCONT & 0x20 ) && ( gb_lcd.current_line >= WNDPOSY ) && ( WNDPOSX <= 166 ) ) ? 1 : 0;
	941	state->lcd.layer[1].enabled = ( ( LCDCONT & 0x20 ) && ( state->lcd.current_line >= WNDPOSY ) && ( WNDPOSX <= 166 ) ) ? 1 : 0;
1001	942
1002	943	/* BG is enabled if the hardware says so AND (window_off OR (window_on
1003	944	* AND window's X position is >=7 ) ) */
1004		gb_lcd.layer[0].enabled = ( ( LCDCONT & 0x01 ) && ( ( ! gb_lcd.layer[1].enabled ) || ( gb_lcd.layer[1].enabled && ( WNDPOSX >= 7 ) ) ) ) ? 1 : 0;
	945	state->lcd.layer[0].enabled = ( ( LCDCONT & 0x01 ) && ( ( ! state->lcd.layer[1].enabled ) || ( state->lcd.layer[1].enabled && ( WNDPOSX >= 7 ) ) ) ) ? 1 : 0;
1005	946
1006		if ( gb_lcd.layer[0].enabled )
	947	if ( state->lcd.layer[0].enabled )
1007	948	{
1008		gb_lcd.layer[0].bgline = ( SCROLLY + gb_lcd.current_line ) & 0xFF;
1009		gb_lcd.layer[0].bg_map = gb_lcd.gb_bgdtab;
1010		gb_lcd.layer[0].gbc_map = gb_lcd.gbc_bgdtab;
1011		gb_lcd.layer[0].xindex = SCROLLX >> 3;
1012		gb_lcd.layer[0].xshift = SCROLLX & 7;
1013		gb_lcd.layer[0].xstart = 0;
1014		gb_lcd.layer[0].xend = 160;
	949	state->lcd.layer[0].bgline = ( SCROLLY + state->lcd.current_line ) & 0xFF;
	950	state->lcd.layer[0].bg_map = state->lcd.gb_bgdtab;
	951	state->lcd.layer[0].gbc_map = state->lcd.gbc_bgdtab;
	952	state->lcd.layer[0].xindex = SCROLLX >> 3;
	953	state->lcd.layer[0].xshift = SCROLLX & 7;
	954	state->lcd.layer[0].xstart = 0;
	955	state->lcd.layer[0].xend = 160;
1015	956	}
1016	957
1017		if ( gb_lcd.layer[1].enabled )
	958	if ( state->lcd.layer[1].enabled )
1018	959	{
1019	960	int xpos;
1020	961
r9784	r9785
1023	964	if (xpos < 0)
1024	965	xpos = 0;
1025	966
1026		gb_lcd.layer[1].bgline = gb_lcd.window_lines_drawn;
1027		gb_lcd.layer[1].bg_map = gb_lcd.gb_wndtab;
1028		gb_lcd.layer[1].gbc_map = gb_lcd.gbc_wndtab;
1029		gb_lcd.layer[1].xindex = 0;
1030		gb_lcd.layer[1].xshift = 0;
1031		gb_lcd.layer[1].xstart = xpos;
1032		gb_lcd.layer[1].xend = 160;
1033		gb_lcd.layer[0].xend = xpos;
	967	state->lcd.layer[1].bgline = state->lcd.window_lines_drawn;
	968	state->lcd.layer[1].bg_map = state->lcd.gb_wndtab;
	969	state->lcd.layer[1].gbc_map = state->lcd.gbc_wndtab;
	970	state->lcd.layer[1].xindex = 0;
	971	state->lcd.layer[1].xshift = 0;
	972	state->lcd.layer[1].xstart = xpos;
	973	state->lcd.layer[1].xend = 160;
	974	state->lcd.layer[0].xend = xpos;
1034	975	}
1035		gb_lcd.start_x = 0;
	976	state->lcd.start_x = 0;
1036	977	}
1037	978
1038	979	if ( cycles_to_go < 160 )
1039	980	{
1040		gb_lcd.end_x = MIN(160 - cycles_to_go,160);
	981	state->lcd.end_x = MIN(160 - cycles_to_go,160);
1041	982	/* Draw empty line when the background is disabled */
1042	983	if ( ! ( LCDCONT & 0x01 ) )
1043	984	{
1044	985	rectangle r;
1045		r.min_y = r.max_y = gb_lcd.current_line;
1046		r.min_x = gb_lcd.start_x;
1047		r.max_x = gb_lcd.end_x - 1;
1048		bitmap_fill( bitmap, &r , ( ! gb_lcd.gbc_mode ) ? 0 : 32767);
	986	r.min_y = r.max_y = state->lcd.current_line;
	987	r.min_x = state->lcd.start_x;
	988	r.max_x = state->lcd.end_x - 1;
	989	bitmap_fill( bitmap, &r , ( ! state->lcd.gbc_mode ) ? 0 : 32767);
1049	990	}
1050	991	while ( l < 2 )
1051	992	{
r9784	r9785
1053	994	UINT16   data;
1054	995	int   i, tile_index;
1055	996
1056		if ( ! gb_lcd.layer[l].enabled )
	997	if ( ! state->lcd.layer[l].enabled )
1057	998	{
1058	999	l++;
1059	1000	continue;
1060	1001	}
1061		map = gb_lcd.layer[l].bg_map + ( ( gb_lcd.layer[l].bgline << 2 ) & 0x3E0 );
1062		gbcmap = gb_lcd.layer[l].gbc_map + ( ( gb_lcd.layer[l].bgline << 2 ) & 0x3E0 );
1063		tiles = ( gbcmap[ gb_lcd.layer[l].xindex ] & 0x08 ) ? gb_lcd.gbc_chrgen : gb_lcd.gb_chrgen;
	1002	map = state->lcd.layer[l].bg_map + ( ( state->lcd.layer[l].bgline << 2 ) & 0x3E0 );
	1003	gbcmap = state->lcd.layer[l].gbc_map + ( ( state->lcd.layer[l].bgline << 2 ) & 0x3E0 );
	1004	tiles = ( gbcmap[ state->lcd.layer[l].xindex ] & 0x08 ) ? state->lcd.gbc_chrgen : state->lcd.gb_chrgen;
1064	1005
1065	1006	/* Check for vertical flip */
1066		if ( gbcmap[ gb_lcd.layer[l].xindex ] & 0x40 )
	1007	if ( gbcmap[ state->lcd.layer[l].xindex ] & 0x40 )
1067	1008	{
1068		tiles += ( ( 7 - ( gb_lcd.layer[l].bgline & 0x07 ) ) << 1 );
	1009	tiles += ( ( 7 - ( state->lcd.layer[l].bgline & 0x07 ) ) << 1 );
1069	1010	}
1070	1011	else
1071	1012	{
1072		tiles += ( ( gb_lcd.layer[l].bgline & 0x07 ) << 1 );
	1013	tiles += ( ( state->lcd.layer[l].bgline & 0x07 ) << 1 );
1073	1014	}
1074		xindex = gb_lcd.start_x;
1075		if ( xindex < gb_lcd.layer[l].xstart )
1076		xindex = gb_lcd.layer[l].xstart;
1077		i = gb_lcd.end_x;
1078		if ( i > gb_lcd.layer[l].xend )
1079		i = gb_lcd.layer[l].xend;
	1015	xindex = state->lcd.start_x;
	1016	if ( xindex < state->lcd.layer[l].xstart )
	1017	xindex = state->lcd.layer[l].xstart;
	1018	i = state->lcd.end_x;
	1019	if ( i > state->lcd.layer[l].xend )
	1020	i = state->lcd.layer[l].xend;
1080	1021	i = i - xindex;
1081	1022
1082		tile_index = ( map[ gb_lcd.layer[l].xindex ] ^ gb_lcd.gb_tile_no_mod ) * 16;
	1023	tile_index = ( map[ state->lcd.layer[l].xindex ] ^ state->lcd.gb_tile_no_mod ) * 16;
1083	1024	data = tiles[ tile_index ] | ( tiles[ tile_index + 1 ] << 8 );
1084	1025	/* Check for horinzontal flip */
1085		if ( gbcmap[ gb_lcd.layer[l].xindex ] & 0x20 )
	1026	if ( gbcmap[ state->lcd.layer[l].xindex ] & 0x20 )
1086	1027	{
1087		data >>= gb_lcd.layer[l].xshift;
	1028	data >>= state->lcd.layer[l].xshift;
1088	1029	}
1089	1030	else
1090	1031	{
1091		data <<= gb_lcd.layer[l].xshift;
	1032	data <<= state->lcd.layer[l].xshift;
1092	1033	}
1093	1034
1094	1035	while ( i > 0 )
1095	1036	{
1096		while ( ( gb_lcd.layer[l].xshift < 8 ) && i )
	1037	while ( ( state->lcd.layer[l].xshift < 8 ) && i )
1097	1038	{
1098	1039	int colour;
1099	1040	/* Check for horinzontal flip */
1100		if ( gbcmap[ gb_lcd.layer[l].xindex ] & 0x20 )
	1041	if ( gbcmap[ state->lcd.layer[l].xindex ] & 0x20 )
1101	1042	{
1102	1043	colour = ( ( data & 0x0100 ) ? 2 : 0 ) | ( ( data & 0x0001 ) ? 1 : 0 );
1103	1044	data >>= 1;
r9784	r9785
1107	1048	colour = ( ( data & 0x8000 ) ? 2 : 0 ) | ( ( data & 0x0080 ) ? 1 : 0 );
1108	1049	data <<= 1;
1109	1050	}
1110		gb_plot_pixel( bitmap, xindex, gb_lcd.current_line, gb_lcd.cgb_bpal[ ( ! gb_lcd.gbc_mode ) ? gb_lcd.gb_bpal[colour] : ( ( ( gbcmap[ gb_lcd.layer[l].xindex ] & 0x07 ) * 4 ) + colour ) ] );
1111		gb_lcd.bg_zbuf[ xindex ] = colour + ( gbcmap[ gb_lcd.layer[l].xindex ] & 0x80 );
	1051	gb_plot_pixel( bitmap, xindex, state->lcd.current_line, state->lcd.cgb_bpal[ ( ! state->lcd.gbc_mode ) ? state->lcd.gb_bpal[colour] : ( ( ( gbcmap[ state->lcd.layer[l].xindex ] & 0x07 ) * 4 ) + colour ) ] );
	1052	state->lcd.bg_zbuf[ xindex ] = colour + ( gbcmap[ state->lcd.layer[l].xindex ] & 0x80 );
1112	1053	xindex++;
1113		gb_lcd.layer[l].xshift++;
	1054	state->lcd.layer[l].xshift++;
1114	1055	i--;
1115	1056	}
1116		if ( gb_lcd.layer[l].xshift == 8 )
	1057	if ( state->lcd.layer[l].xshift == 8 )
1117	1058	{
1118	1059	/* Take possible changes to SCROLLY into account */
1119	1060	if ( l == 0 )
1120	1061	{
1121		gb_lcd.layer[0].bgline = ( SCROLLY + gb_lcd.current_line ) & 0xFF;
1122		map = gb_lcd.layer[l].bg_map + ( ( gb_lcd.layer[l].bgline << 2 ) & 0x3E0 );
1123		gbcmap = gb_lcd.layer[l].gbc_map + ( ( gb_lcd.layer[l].bgline << 2 ) & 0x3E0 );
	1062	state->lcd.layer[0].bgline = ( SCROLLY + state->lcd.current_line ) & 0xFF;
	1063	map = state->lcd.layer[l].bg_map + ( ( state->lcd.layer[l].bgline << 2 ) & 0x3E0 );
	1064	gbcmap = state->lcd.layer[l].gbc_map + ( ( state->lcd.layer[l].bgline << 2 ) & 0x3E0 );
1124	1065	}
1125	1066
1126		gb_lcd.layer[l].xindex = ( gb_lcd.layer[l].xindex + 1 ) & 31;
1127		gb_lcd.layer[l].xshift = 0;
1128		tiles = ( gbcmap[ gb_lcd.layer[l].xindex ] & 0x08 ) ? gb_lcd.gbc_chrgen : gb_lcd.gb_chrgen;
	1067	state->lcd.layer[l].xindex = ( state->lcd.layer[l].xindex + 1 ) & 31;
	1068	state->lcd.layer[l].xshift = 0;
	1069	tiles = ( gbcmap[ state->lcd.layer[l].xindex ] & 0x08 ) ? state->lcd.gbc_chrgen : state->lcd.gb_chrgen;
1129	1070
1130	1071	/* Check for vertical flip */
1131		if ( gbcmap[ gb_lcd.layer[l].xindex ] & 0x40 )
	1072	if ( gbcmap[ state->lcd.layer[l].xindex ] & 0x40 )
1132	1073	{
1133		tiles += ( ( 7 - ( gb_lcd.layer[l].bgline & 0x07 ) ) << 1 );
	1074	tiles += ( ( 7 - ( state->lcd.layer[l].bgline & 0x07 ) ) << 1 );
1134	1075	}
1135	1076	else
1136	1077	{
1137		tiles += ( ( gb_lcd.layer[l].bgline & 0x07 ) << 1 );
	1078	tiles += ( ( state->lcd.layer[l].bgline & 0x07 ) << 1 );
1138	1079	}
1139		tile_index = ( map[ gb_lcd.layer[l].xindex ] ^ gb_lcd.gb_tile_no_mod ) * 16;
	1080	tile_index = ( map[ state->lcd.layer[l].xindex ] ^ state->lcd.gb_tile_no_mod ) * 16;
1140	1081	data = tiles[ tile_index ] | ( tiles[ tile_index + 1 ] << 8 );
1141	1082	}
1142	1083	}
1143	1084	l++;
1144	1085	}
1145		if ( gb_lcd.end_x == 160 && ( LCDCONT & 0x02 ) )
	1086	if ( state->lcd.end_x == 160 && ( LCDCONT & 0x02 ) )
1146	1087	{
1147	1088	cgb_update_sprites( machine );
1148	1089	}
1149		gb_lcd.start_x = gb_lcd.end_x;
	1090	state->lcd.start_x = state->lcd.end_x;
1150	1091	}
1151	1092	}
1152	1093	else
r9784	r9785
1154	1095	if ( ! ( LCDCONT & 0x80 ) )
1155	1096	{
1156	1097	/* Draw an empty line when LCD is disabled */
1157		if ( gb_lcd.previous_line != gb_lcd.current_line )
	1098	if ( state->lcd.previous_line != state->lcd.current_line )
1158	1099	{
1159		if ( gb_lcd.current_line < 144 )
	1100	if ( state->lcd.current_line < 144 )
1160	1101	{
1161	1102	screen_device *screen = machine->first_screen();
1162	1103	rectangle r;
1163	1104	const rectangle &r1 = screen->visible_area();
1164	1105	r.min_x = r1.min_x;
1165	1106	r.max_x = r1.max_x;
1166		r.min_y = r.max_y = gb_lcd.current_line;
1167		bitmap_fill( bitmap, &r , ( ! gb_lcd.gbc_mode ) ? 0 : 32767);
	1107	r.min_y = r.max_y = state->lcd.current_line;
	1108	bitmap_fill( bitmap, &r , ( ! state->lcd.gbc_mode ) ? 0 : 32767);
1168	1109	}
1169		gb_lcd.previous_line = gb_lcd.current_line;
	1110	state->lcd.previous_line = state->lcd.current_line;
1170	1111	}
1171	1112	}
1172	1113	}
r9784	r9785
1289	1230
1290	1231	MACHINE_START( gb_video )
1291	1232	{
1292		gb_lcd.lcd_timer = timer_alloc(machine, gb_lcd_timer_proc, NULL);
	1233	gb_state *state = machine->driver_data<gb_state>();
	1234	state->lcd.lcd_timer = timer_alloc(machine, gb_lcd_timer_proc, NULL);
1293	1235	}
1294	1236
1295	1237	MACHINE_START( gbc_video )
1296	1238	{
1297		gb_lcd.lcd_timer = timer_alloc(machine, gbc_lcd_timer_proc, NULL);
	1239	gb_state *state = machine->driver_data<gb_state>();
	1240	state->lcd.lcd_timer = timer_alloc(machine, gbc_lcd_timer_proc, NULL);
1298	1241	}
1299	1242
1300	1243	void gb_video_reset( running_machine *machine, int mode )
1301	1244	{
	1245	gb_state *state = machine->driver_data<gb_state>();
1302	1246	int   i;
1303	1247	int vram_size = 0x2000;
1304	1248	address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
1305		emu_timer *old_timer = gb_lcd.lcd_timer;
	1249	emu_timer *old_timer = state->lcd.lcd_timer;
1306	1250
1307		memset( &gb_lcd, 0, sizeof(gb_lcd) );
1308		gb_lcd.lcd_timer = old_timer;
	1251	memset( &state->lcd, 0, sizeof(state->lcd) );
	1252	state->lcd.lcd_timer = old_timer;
1309	1253
1310	1254	if (mode == GB_VIDEO_CGB) vram_size = 0x4000;
1311	1255
r9784	r9785
1313	1257	if (memory_region(machine, "gfx1"))      machine->region_free("gfx1");
1314	1258	if (memory_region(machine, "gfx2"))      machine->region_free("gfx2");
1315	1259
1316		gb_lcd.gb_vram = machine->region_alloc("gfx1", vram_size, 0 );
1317		gb_lcd.gb_oam = machine->region_alloc("gfx2", 0x100, 0 );
1318		memset( gb_lcd.gb_vram->base(), 0, vram_size );
	1260	state->lcd.gb_vram = machine->region_alloc("gfx1", vram_size, 0 );
	1261	state->lcd.gb_oam = machine->region_alloc("gfx2", 0x100, 0 );
	1262	memset( state->lcd.gb_vram->base(), 0, vram_size );
1319	1263
1320		gb_lcd.gb_vram_ptr = gb_lcd.gb_vram->base();
1321		gb_lcd.gb_chrgen = gb_lcd.gb_vram->base();
1322		gb_lcd.gb_bgdtab = gb_lcd.gb_vram->base() + 0x1C00;
1323		gb_lcd.gb_wndtab = gb_lcd.gb_vram->base() + 0x1C00;
	1264	state->lcd.gb_vram_ptr = state->lcd.gb_vram->base();
	1265	state->lcd.gb_chrgen = state->lcd.gb_vram->base();
	1266	state->lcd.gb_bgdtab = state->lcd.gb_vram->base() + 0x1C00;
	1267	state->lcd.gb_wndtab = state->lcd.gb_vram->base() + 0x1C00;
1324	1268
1325		gb_lcd.gb_vid_regs[0x06] = 0xFF;
	1269	state->lcd.gb_vid_regs[0x06] = 0xFF;
1326	1270	for( i = 0x0c; i < _NR_GB_VID_REGS; i++ )
1327	1271	{
1328		gb_lcd.gb_vid_regs[i] = 0xFF;
	1272	state->lcd.gb_vid_regs[i] = 0xFF;
1329	1273	}
1330	1274
1331	1275	LCDSTAT = 0x80;
1332	1276	LCDCONT = 0x00;      /* Video hardware is turned off at boot time */
1333		gb_lcd.current_line = CURLINE = CMPLINE = 0x00;
	1277	state->lcd.current_line = CURLINE = CMPLINE = 0x00;
1334	1278	SCROLLX = SCROLLY = 0x00;
1335	1279	SPR0PAL = SPR1PAL = 0xFF;
1336	1280	WNDPOSX = WNDPOSY = 0x00;
r9784	r9785
1338	1282	/* Initialize palette arrays */
1339	1283	for( i = 0; i < 4; i++ )
1340	1284	{
1341		gb_lcd.gb_bpal[i] = gb_lcd.gb_spal0[i] = gb_lcd.gb_spal1[i] = i;
	1285	state->lcd.gb_bpal[i] = state->lcd.gb_spal0[i] = state->lcd.gb_spal1[i] = i;
1342	1286	}
1343	1287
1344	1288	switch( mode )
1345	1289	{
1346	1290	case GB_VIDEO_DMG:
1347		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(456), 0);
	1291	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(456), 0);
1348	1292
1349	1293	/* set the scanline update function */
1350		update_scanline = gb_update_scanline;
	1294	state->update_scanline = gb_update_scanline;
1351	1295
1352		memcpy( gb_lcd.gb_oam->base(), dmg_oam_fingerprint, 0x100 );
	1296	memcpy( state->lcd.gb_oam->base(), dmg_oam_fingerprint, 0x100 );
1353	1297
1354	1298	break;
1355	1299	case GB_VIDEO_MGB:
1356	1300	/* set the scanline update function */
1357		update_scanline = gb_update_scanline;
	1301	state->update_scanline = gb_update_scanline;
1358	1302	/* Initialize part of VRAM. This code must be deleted when we have added the bios dump */
1359	1303	for( i = 1; i < 0x0D; i++ )
1360	1304	{
1361		gb_lcd.gb_vram->base()[ 0x1903 + i ] = i;
1362		gb_lcd.gb_vram->base()[ 0x1923 + i ] = i + 0x0C;
	1305	state->lcd.gb_vram->base()[ 0x1903 + i ] = i;
	1306	state->lcd.gb_vram->base()[ 0x1923 + i ] = i + 0x0C;
1363	1307	}
1364		gb_lcd.gb_vram->base()[ 0x1910 ] = 0x19;
	1308	state->lcd.gb_vram->base()[ 0x1910 ] = 0x19;
1365	1309
1366	1310
1367		memcpy( gb_lcd.gb_oam->base(), mgb_oam_fingerprint, 0x100 );
	1311	memcpy( state->lcd.gb_oam->base(), mgb_oam_fingerprint, 0x100 );
1368	1312
1369	1313	/* Make sure the VBlank interrupt is set when the first instruction gets executed */
1370	1314	timer_set(machine,  machine->device<cpu_device>("maincpu")->cycles_to_attotime(1), NULL, 0, gb_video_init_vbl );
r9784	r9785
1375	1319	gb_video_w( space, 0x8, 0xFC );    /* SPR0PAL */
1376	1320	gb_video_w( space, 0x9, 0xFC );    /* SPR1PAL */
1377	1321
1378		CURLINE = gb_lcd.current_line = 0;
	1322	CURLINE = state->lcd.current_line = 0;
1379	1323	LCDSTAT = ( LCDSTAT & 0xF8 ) | 0x05;
1380		gb_lcd.mode = 1;
1381		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(60), GB_LCD_STATE_LY00_M0);
	1324	state->lcd.mode = 1;
	1325	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(60), GB_LCD_STATE_LY00_M0);
1382	1326
1383	1327	break;
1384	1328	case GB_VIDEO_SGB:
1385	1329	/* set the scanline update function */
1386		update_scanline = sgb_update_scanline;
	1330	state->update_scanline = sgb_update_scanline;
1387	1331
1388	1332	break;
1389	1333
1390	1334	case GB_VIDEO_CGB:
1391	1335	/* set the scanline update function */
1392		update_scanline = cgb_update_scanline;
	1336	state->update_scanline = cgb_update_scanline;
1393	1337
1394		memcpy( gb_lcd.gb_oam->base(), cgb_oam_fingerprint, 0x100 );
	1338	memcpy( state->lcd.gb_oam->base(), cgb_oam_fingerprint, 0x100 );
1395	1339
1396		gb_lcd.gb_chrgen = gb_lcd.gb_vram->base();
1397		gb_lcd.gbc_chrgen = gb_lcd.gb_vram->base() + 0x2000;
1398		gb_lcd.gb_bgdtab = gb_lcd.gb_wndtab = gb_lcd.gb_vram->base() + 0x1C00;
1399		gb_lcd.gbc_bgdtab = gb_lcd.gbc_wndtab = gb_lcd.gb_vram->base() + 0x3C00;
	1340	state->lcd.gb_chrgen = state->lcd.gb_vram->base();
	1341	state->lcd.gbc_chrgen = state->lcd.gb_vram->base() + 0x2000;
	1342	state->lcd.gb_bgdtab = state->lcd.gb_wndtab = state->lcd.gb_vram->base() + 0x1C00;
	1343	state->lcd.gbc_bgdtab = state->lcd.gbc_wndtab = state->lcd.gb_vram->base() + 0x3C00;
1400	1344
1401	1345	/* HDMA disabled */
1402		gb_lcd.hdma_enabled = 0;
1403		gb_lcd.hdma_possible = 0;
	1346	state->lcd.hdma_enabled = 0;
	1347	state->lcd.hdma_possible = 0;
1404	1348
1405		gb_lcd.gbc_mode = 1;
	1349	state->lcd.gbc_mode = 1;
1406	1350	break;
1407	1351	}
1408	1352	}
1409	1353
1410	1354	static void gbc_hdma(running_machine *machine, UINT16 length)
1411	1355	{
	1356	gb_state *state = machine->driver_data<gb_state>();
1412	1357	UINT16 src, dst;
1413	1358	address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
1414	1359
r9784	r9785
1428	1373	if( (HDMA5 & 0x7f) == 0x7f )
1429	1374	{
1430	1375	HDMA5 = 0xff;
1431		gb_lcd.hdma_enabled = 0;
	1376	state->lcd.hdma_enabled = 0;
1432	1377	}
1433	1378	}
1434	1379
1435		static void gb_increment_scanline( void )
	1380	static void gb_increment_scanline( gb_state *state )
1436	1381	{
1437		gb_lcd.current_line = ( gb_lcd.current_line + 1 ) % 154;
	1382	state->lcd.current_line = ( state->lcd.current_line + 1 ) % 154;
1438	1383	if ( LCDCONT & 0x80 )
1439	1384	{
1440		CURLINE = gb_lcd.current_line;
	1385	CURLINE = state->lcd.current_line;
1441	1386	}
1442		if ( gb_lcd.current_line == 0 )
	1387	if ( state->lcd.current_line == 0 )
1443	1388	{
1444		gb_lcd.window_lines_drawn = 0;
	1389	state->lcd.window_lines_drawn = 0;
1445	1390	}
1446	1391	}
1447	1392
1448	1393	static TIMER_CALLBACK(gb_lcd_timer_proc)
1449	1394	{
	1395	gb_state *state = machine->driver_data<gb_state>();
1450	1396	static const int sprite_cycles[] = { 0, 8, 20, 32, 44, 52, 64, 76, 88, 96, 108 };
1451	1397
1452		gb_lcd.state = param;
	1398	state->lcd.state = param;
1453	1399
1454	1400	if ( LCDCONT & 0x80 )
1455	1401	{
1456		switch( gb_lcd.state )
	1402	switch( state->lcd.state )
1457	1403	{
1458	1404	case GB_LCD_STATE_LYXX_PRE_M0:   /* Just before switching to mode 0 */
1459		gb_lcd.mode = 0;
	1405	state->lcd.mode = 0;
1460	1406	if ( LCDSTAT & 0x08 )
1461	1407	{
1462		if ( ! gb_lcd.mode_irq )
	1408	if ( ! state->lcd.mode_irq )
1463	1409	{
1464		if ( ! gb_lcd.line_irq && ! gb_lcd.delayed_line_irq )
	1410	if ( ! state->lcd.line_irq && ! state->lcd.delayed_line_irq )
1465	1411	{
1466		gb_lcd.mode_irq = 1;
	1412	state->lcd.mode_irq = 1;
1467	1413	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1468	1414	}
1469	1415	}
1470	1416	else
1471	1417	{
1472		gb_lcd.mode_irq = 0;
	1418	state->lcd.mode_irq = 0;
1473	1419	}
1474	1420	}
1475		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0);
	1421	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0);
1476	1422	break;
1477	1423	case GB_LCD_STATE_LYXX_M0:      /* Switch to mode 0 */
1478	1424	/* update current scanline */
1479		update_scanline( machine );
	1425	(*state->update_scanline)( machine );
1480	1426	/* Increment the number of window lines drawn if enabled */
1481		if ( gb_lcd.layer[1].enabled )
	1427	if ( state->lcd.layer[1].enabled )
1482	1428	{
1483		gb_lcd.window_lines_drawn++;
	1429	state->lcd.window_lines_drawn++;
1484	1430	}
1485		gb_lcd.previous_line = gb_lcd.current_line;
	1431	state->lcd.previous_line = state->lcd.current_line;
1486	1432	/* Set Mode 0 lcdstate */
1487		gb_lcd.mode = 0;
	1433	state->lcd.mode = 0;
1488	1434	LCDSTAT &= 0xFC;
1489		gb_lcd.oam_locked = UNLOCKED;
1490		gb_lcd.vram_locked = UNLOCKED;
	1435	state->lcd.oam_locked = UNLOCKED;
	1436	state->lcd.vram_locked = UNLOCKED;
1491	1437	/*
1492	1438	There seems to a kind of feature in the Game Boy hardware when the lowest bits of the
1493	1439	SCROLLX register equals 3 or 7, then the delayed M0 irq is triggered 4 cycles later
r9784	r9785
1496	1442	*/
1497	1443	if ( ( SCROLLX & 0x03 ) == 0x03 )
1498	1444	{
1499		gb_lcd.scrollx_adjust += 4;
1500		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0_SCX3);
	1445	state->lcd.scrollx_adjust += 4;
	1446	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0_SCX3);
1501	1447	break;
1502	1448	}
1503	1449	case GB_LCD_STATE_LYXX_M0_SCX3:
1504	1450	/* Generate lcd interrupt if requested */
1505		if ( ! gb_lcd.mode_irq && ( LCDSTAT & 0x08 ) &&
1506		( ( ! gb_lcd.line_irq && gb_lcd.delayed_line_irq ) || ! ( LCDSTAT & 0x40 ) ) )
	1451	if ( ! state->lcd.mode_irq && ( LCDSTAT & 0x08 ) &&
	1452	( ( ! state->lcd.line_irq && state->lcd.delayed_line_irq ) || ! ( LCDSTAT & 0x40 ) ) )
1507	1453	{
1508	1454	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1509	1455	}
1510		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(196 - gb_lcd.scrollx_adjust - gb_lcd.sprite_cycles), GB_LCD_STATE_LYXX_M0_PRE_INC);
	1456	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(196 - state->lcd.scrollx_adjust - state->lcd.sprite_cycles), GB_LCD_STATE_LYXX_M0_PRE_INC);
1511	1457	break;
1512	1458	case GB_LCD_STATE_LYXX_M0_PRE_INC:   /* Just before incrementing the line counter go to mode 2 internally */
1513	1459	if ( CURLINE < 143 )
1514	1460	{
1515		gb_lcd.mode = 2;
1516		gb_lcd.triggering_mode_irq = ( LCDSTAT & 0x20 ) ? 1 : 0;
1517		if ( gb_lcd.triggering_mode_irq )
	1461	state->lcd.mode = 2;
	1462	state->lcd.triggering_mode_irq = ( LCDSTAT & 0x20 ) ? 1 : 0;
	1463	if ( state->lcd.triggering_mode_irq )
1518	1464	{
1519		if ( ! gb_lcd.mode_irq )
	1465	if ( ! state->lcd.mode_irq )
1520	1466	{
1521		if ( ! gb_lcd.line_irq && ! gb_lcd.delayed_line_irq )
	1467	if ( ! state->lcd.line_irq && ! state->lcd.delayed_line_irq )
1522	1468	{
1523		gb_lcd.mode_irq = 1;
	1469	state->lcd.mode_irq = 1;
1524	1470	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1525	1471	}
1526	1472	}
1527	1473	else
1528	1474	{
1529		gb_lcd.mode_irq = 0;
	1475	state->lcd.mode_irq = 0;
1530	1476	}
1531	1477	}
1532	1478	}
1533		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0_INC);
	1479	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0_INC);
1534	1480	break;
1535	1481	case GB_LCD_STATE_LYXX_M0_INC:   /* Increment LY, stay in M0 for 4 more cycles */
1536		gb_increment_scanline();
1537		gb_lcd.delayed_line_irq = gb_lcd.line_irq;
1538		gb_lcd.triggering_line_irq = ( ( CMPLINE == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
1539		gb_lcd.line_irq = 0;
1540		if ( ! gb_lcd.mode_irq && ! gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq && ! gb_lcd.triggering_mode_irq )
	1482	gb_increment_scanline(state);
	1483	state->lcd.delayed_line_irq = state->lcd.line_irq;
	1484	state->lcd.triggering_line_irq = ( ( CMPLINE == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
	1485	state->lcd.line_irq = 0;
	1486	if ( ! state->lcd.mode_irq && ! state->lcd.delayed_line_irq && state->lcd.triggering_line_irq && ! state->lcd.triggering_mode_irq )
1541	1487	{
1542		gb_lcd.line_irq = gb_lcd.triggering_line_irq;
	1488	state->lcd.line_irq = state->lcd.triggering_line_irq;
1543	1489	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1544	1490	}
1545	1491	/* Reset LY==LYC STAT bit */
r9784	r9785
1547	1493	/* Check if we're going into VBlank next */
1548	1494	if ( CURLINE == 144 )
1549	1495	{
1550		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY9X_M1);
	1496	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY9X_M1);
1551	1497	}
1552	1498	else
1553	1499	{
1554	1500	/* Internally switch to mode 2 */
1555		gb_lcd.mode = 2;
	1501	state->lcd.mode = 2;
1556	1502	/* Generate lcd interrupt if requested */
1557		if ( ! gb_lcd.mode_irq && gb_lcd.triggering_mode_irq &&
1558		( ( ! gb_lcd.triggering_line_irq && ! gb_lcd.delayed_line_irq ) || ! ( LCDSTAT & 0x40 ) ) )
	1503	if ( ! state->lcd.mode_irq && state->lcd.triggering_mode_irq &&
	1504	( ( ! state->lcd.triggering_line_irq && ! state->lcd.delayed_line_irq ) || ! ( LCDSTAT & 0x40 ) ) )
1559	1505	{
1560		gb_lcd.mode_irq = 1;
	1506	state->lcd.mode_irq = 1;
1561	1507	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1562	1508	}
1563		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M2);
	1509	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M2);
1564	1510	}
1565	1511	break;
1566	1512	case GB_LCD_STATE_LY00_M2:      /* Switch to mode 2 on line #0 */
1567	1513	/* Set Mode 2 lcdstate */
1568		gb_lcd.mode = 2;
	1514	state->lcd.mode = 2;
1569	1515	LCDSTAT = ( LCDSTAT & 0xFC ) | 0x02;
1570		gb_lcd.oam_locked = LOCKED;
	1516	state->lcd.oam_locked = LOCKED;
1571	1517	/* Generate lcd interrupt if requested */
1572		if ( ( LCDSTAT & 0x20 ) && ! gb_lcd.line_irq && ! gb_lcd.line_irq )
	1518	if ( ( LCDSTAT & 0x20 ) && ! state->lcd.line_irq && ! state->lcd.line_irq )
1573	1519	{
1574	1520	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1575	1521	}
1576	1522	/* Check for regular compensation of x-scroll register */
1577		gb_lcd.scrollx_adjust = ( SCROLLX & 0x04 ) ? 4 : 0;
	1523	state->lcd.scrollx_adjust = ( SCROLLX & 0x04 ) ? 4 : 0;
1578	1524	/* Mode 2 lasts approximately 80 clock cycles */
1579		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(80), GB_LCD_STATE_LYXX_M3);
	1525	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(80), GB_LCD_STATE_LYXX_M3);
1580	1526	break;
1581	1527	case GB_LCD_STATE_LYXX_M2:      /* Switch to mode 2 */
1582	1528	/* Update STAT register to the correct state */
1583	1529	LCDSTAT = (LCDSTAT & 0xFC) | 0x02;
1584		gb_lcd.oam_locked = LOCKED;
	1530	state->lcd.oam_locked = LOCKED;
1585	1531	/* Generate lcd interrupt if requested */
1586		if ( ( gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq && ! ( LCDSTAT & 0x20 ) ) ||
1587		( ! gb_lcd.mode_irq && ! gb_lcd.line_irq && ! gb_lcd.delayed_line_irq && gb_lcd.triggering_mode_irq ) )
	1532	if ( ( state->lcd.delayed_line_irq && state->lcd.triggering_line_irq && ! ( LCDSTAT & 0x20 ) ) ||
	1533	( ! state->lcd.mode_irq && ! state->lcd.line_irq && ! state->lcd.delayed_line_irq && state->lcd.triggering_mode_irq ) )
1588	1534	{
1589	1535	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1590	1536	}
1591		gb_lcd.line_irq = gb_lcd.triggering_line_irq;
1592		gb_lcd.triggering_mode_irq = 0;
	1537	state->lcd.line_irq = state->lcd.triggering_line_irq;
	1538	state->lcd.triggering_mode_irq = 0;
1593	1539	/* Check if LY==LYC STAT bit should be set */
1594	1540	if ( CURLINE == CMPLINE )
1595	1541	{
1596	1542	LCDSTAT |= 0x04;
1597	1543	}
1598	1544	/* Check for regular compensation of x-scroll register */
1599		gb_lcd.scrollx_adjust = ( SCROLLX & 0x04 ) ? 4 : 0;
	1545	state->lcd.scrollx_adjust = ( SCROLLX & 0x04 ) ? 4 : 0;
1600	1546	/* Mode 2 last for approximately 80 clock cycles */
1601		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(80), GB_LCD_STATE_LYXX_M3);
	1547	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(80), GB_LCD_STATE_LYXX_M3);
1602	1548	break;
1603	1549	case GB_LCD_STATE_LYXX_M3:      /* Switch to mode 3 */
1604		gb_select_sprites();
1605		gb_lcd.sprite_cycles = sprite_cycles[ gb_lcd.sprCount ];
	1550	gb_select_sprites(state);
	1551	state->lcd.sprite_cycles = sprite_cycles[ state->lcd.sprCount ];
1606	1552	/* Set Mode 3 lcdstate */
1607		gb_lcd.mode = 3;
	1553	state->lcd.mode = 3;
1608	1554	LCDSTAT = (LCDSTAT & 0xFC) | 0x03;
1609		gb_lcd.vram_locked = LOCKED;
	1555	state->lcd.vram_locked = LOCKED;
1610	1556	/* Check for compensations of x-scroll register */
1611	1557	/* Mode 3 lasts for approximately 172+cycles needed to handle sprites clock cycles */
1612		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(168 + gb_lcd.scrollx_adjust + gb_lcd.sprite_cycles), GB_LCD_STATE_LYXX_PRE_M0);
1613		gb_lcd.start_x = -1;
	1558	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(168 + state->lcd.scrollx_adjust + state->lcd.sprite_cycles), GB_LCD_STATE_LYXX_PRE_M0);
	1559	state->lcd.start_x = -1;
1614	1560	break;
1615	1561	case GB_LCD_STATE_LY9X_M1:      /* Switch to or stay in mode 1 */
1616	1562	if ( CURLINE == 144 )
r9784	r9785
1618	1564	/* Trigger VBlank interrupt */
1619	1565	cputag_set_input_line( machine, "maincpu", VBL_INT, ASSERT_LINE );
1620	1566	/* Set VBlank lcdstate */
1621		gb_lcd.mode = 1;
	1567	state->lcd.mode = 1;
1622	1568	LCDSTAT = (LCDSTAT & 0xFC) | 0x01;
1623	1569	/* Trigger LCD interrupt if requested */
1624	1570	if ( LCDSTAT & 0x10 )
r9784	r9785
1631	1577	{
1632	1578	LCDSTAT |= 0x04;
1633	1579	}
1634		if ( gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq )
	1580	if ( state->lcd.delayed_line_irq && state->lcd.triggering_line_irq )
1635	1581	{
1636	1582	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1637	1583	}
1638		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(452), GB_LCD_STATE_LY9X_M1_INC);
	1584	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(452), GB_LCD_STATE_LY9X_M1_INC);
1639	1585	break;
1640	1586	case GB_LCD_STATE_LY9X_M1_INC:      /* Increment scanline counter */
1641		gb_increment_scanline();
1642		gb_lcd.delayed_line_irq = gb_lcd.line_irq;
1643		gb_lcd.triggering_line_irq = ( ( CMPLINE == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
1644		gb_lcd.line_irq = 0;
1645		if ( ! gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq )
	1587	gb_increment_scanline(state);
	1588	state->lcd.delayed_line_irq = state->lcd.line_irq;
	1589	state->lcd.triggering_line_irq = ( ( CMPLINE == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
	1590	state->lcd.line_irq = 0;
	1591	if ( ! state->lcd.delayed_line_irq && state->lcd.triggering_line_irq )
1646	1592	{
1647		gb_lcd.line_irq = gb_lcd.triggering_line_irq;
	1593	state->lcd.line_irq = state->lcd.triggering_line_irq;
1648	1594	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1649	1595	}
1650	1596	/* Reset LY==LYC STAT bit */
1651	1597	LCDSTAT &= 0xFB;
1652		if ( gb_lcd.current_line == 153 )
	1598	if ( state->lcd.current_line == 153 )
1653	1599	{
1654		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M1);
	1600	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M1);
1655	1601	}
1656	1602	else
1657	1603	{
1658		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY9X_M1);
	1604	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY9X_M1);
1659	1605	}
1660	1606	break;
1661	1607	case GB_LCD_STATE_LY00_M1:      /* we stay in VBlank but current line counter should already be incremented */
1662	1608	/* Check LY=LYC for line #153 */
1663		if ( gb_lcd.delayed_line_irq )
	1609	if ( state->lcd.delayed_line_irq )
1664	1610	{
1665		if ( gb_lcd.triggering_line_irq )
	1611	if ( state->lcd.triggering_line_irq )
1666	1612	{
1667	1613	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1668	1614	}
1669	1615	}
1670		gb_lcd.delayed_line_irq = gb_lcd.delayed_line_irq | gb_lcd.line_irq;
	1616	state->lcd.delayed_line_irq = state->lcd.delayed_line_irq | state->lcd.line_irq;
1671	1617	if ( CURLINE == CMPLINE )
1672	1618	{
1673	1619	LCDSTAT |= 0x04;
1674	1620	}
1675		gb_increment_scanline();
1676		gb_lcd.triggering_line_irq = ( ( CMPLINE == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
1677		gb_lcd.line_irq = 0;
	1621	gb_increment_scanline(state);
	1622	state->lcd.triggering_line_irq = ( ( CMPLINE == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
	1623	state->lcd.line_irq = 0;
1678	1624	LCDSTAT &= 0xFB;
1679		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4/*8*/), GB_LCD_STATE_LY00_M1_1);
	1625	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4/*8*/), GB_LCD_STATE_LY00_M1_1);
1680	1626	break;
1681	1627	case GB_LCD_STATE_LY00_M1_1:
1682		if ( ! gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq )
	1628	if ( ! state->lcd.delayed_line_irq && state->lcd.triggering_line_irq )
1683	1629	{
1684		gb_lcd.line_irq = gb_lcd.triggering_line_irq;
	1630	state->lcd.line_irq = state->lcd.triggering_line_irq;
1685	1631	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1686	1632	}
1687		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M1_2);
	1633	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M1_2);
1688	1634	break;
1689	1635	case GB_LCD_STATE_LY00_M1_2:   /* Rest of line #0 during VBlank */
1690		if ( gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq )
	1636	if ( state->lcd.delayed_line_irq && state->lcd.triggering_line_irq )
1691	1637	{
1692		gb_lcd.line_irq = gb_lcd.triggering_line_irq;
	1638	state->lcd.line_irq = state->lcd.triggering_line_irq;
1693	1639	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1694	1640	}
1695	1641	if ( CURLINE == CMPLINE )
1696	1642	{
1697	1643	LCDSTAT |= 0x04;
1698	1644	}
1699		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(444), GB_LCD_STATE_LY00_M0);
	1645	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(444), GB_LCD_STATE_LY00_M0);
1700	1646	break;
1701	1647	case GB_LCD_STATE_LY00_M0:      /* The STAT register seems to go to 0 for about 4 cycles */
1702	1648	/* Set Mode 0 lcdstat */
1703		gb_lcd.mode = 0;
	1649	state->lcd.mode = 0;
1704	1650	LCDSTAT = ( LCDSTAT & 0xFC );
1705		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M2);
	1651	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M2);
1706	1652	break;
1707	1653	}
1708	1654	}
1709	1655	else
1710	1656	{
1711		gb_increment_scanline();
1712		if ( gb_lcd.current_line < 144 )
	1657	gb_increment_scanline(state);
	1658	if ( state->lcd.current_line < 144 )
1713	1659	{
1714		update_scanline( machine );
	1660	(*state->update_scanline)( machine );
1715	1661	}
1716		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(456), 0);
	1662	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(456), 0);
1717	1663	}
1718	1664	}
1719	1665
1720	1666	static TIMER_CALLBACK(gbc_lcd_timer_proc)
1721	1667	{
	1668	gb_state *state = machine->driver_data<gb_state>();
1722	1669	static const int sprite_cycles[] = { 0, 8, 20, 32, 44, 52, 64, 76, 88, 96, 108 };
1723	1670
1724		gb_lcd.state = param;
	1671	state->lcd.state = param;
1725	1672
1726	1673	if ( LCDCONT & 0x80 )
1727	1674	{
1728		switch( gb_lcd.state )
	1675	switch( state->lcd.state )
1729	1676	{
1730	1677	case GB_LCD_STATE_LYXX_PRE_M0:   /* Just before switching to mode 0 */
1731		gb_lcd.mode = 0;
	1678	state->lcd.mode = 0;
1732	1679	if ( LCDSTAT & 0x08 )
1733	1680	{
1734		if ( ! gb_lcd.mode_irq )
	1681	if ( ! state->lcd.mode_irq )
1735	1682	{
1736		if ( ! gb_lcd.line_irq && ! gb_lcd.delayed_line_irq )
	1683	if ( ! state->lcd.line_irq && ! state->lcd.delayed_line_irq )
1737	1684	{
1738		gb_lcd.mode_irq = 1;
	1685	state->lcd.mode_irq = 1;
1739	1686	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1740	1687	}
1741	1688	}
1742	1689	else
1743	1690	{
1744		gb_lcd.mode_irq = 0;
	1691	state->lcd.mode_irq = 0;
1745	1692	}
1746	1693	}
1747		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0);
	1694	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0);
1748	1695	break;
1749	1696	case GB_LCD_STATE_LYXX_M0:      /* Switch to mode 0 */
1750	1697	/* update current scanline */
1751		update_scanline( machine );
	1698	(*state->update_scanline)( machine );
1752	1699	/* Increment the number of window lines drawn if enabled */
1753		if ( gb_lcd.layer[1].enabled )
	1700	if ( state->lcd.layer[1].enabled )
1754	1701	{
1755		gb_lcd.window_lines_drawn++;
	1702	state->lcd.window_lines_drawn++;
1756	1703	}
1757		gb_lcd.previous_line = gb_lcd.current_line;
	1704	state->lcd.previous_line = state->lcd.current_line;
1758	1705	/* Set Mode 0 lcdstate */
1759		gb_lcd.mode = 0;
	1706	state->lcd.mode = 0;
1760	1707	LCDSTAT &= 0xFC;
1761		gb_lcd.oam_locked = UNLOCKED;
1762		gb_lcd.vram_locked = UNLOCKED;
	1708	state->lcd.oam_locked = UNLOCKED;
	1709	state->lcd.vram_locked = UNLOCKED;
1763	1710	/*
1764	1711	There seems to a kind of feature in the Game Boy hardware when the lowest bits of the
1765	1712	SCROLLX register equals 3 or 7, then the delayed M0 irq is triggered 4 cycles later
1766	1713	than usual.
1767	1714	The SGB probably has the same bug.
1768	1715	*/
1769		gb_lcd.triggering_mode_irq = ( LCDSTAT & 0x08 ) ? 1 : 0;
	1716	state->lcd.triggering_mode_irq = ( LCDSTAT & 0x08 ) ? 1 : 0;
1770	1717	if ( ( SCROLLX & 0x03 ) == 0x03 )
1771	1718	{
1772		gb_lcd.scrollx_adjust += 4;
1773		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0_SCX3);
	1719	state->lcd.scrollx_adjust += 4;
	1720	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0_SCX3);
1774	1721	break;
1775	1722	}
1776	1723	case GB_LCD_STATE_LYXX_M0_SCX3:
1777	1724	/* Generate lcd interrupt if requested */
1778		if ( ! gb_lcd.mode_irq && gb_lcd.triggering_mode_irq &&
1779		( ( ! gb_lcd.line_irq && gb_lcd.delayed_line_irq ) || ! ( LCDSTAT & 0x40 ) ) )
	1725	if ( ! state->lcd.mode_irq && state->lcd.triggering_mode_irq &&
	1726	( ( ! state->lcd.line_irq && state->lcd.delayed_line_irq ) || ! ( LCDSTAT & 0x40 ) ) )
1780	1727	{
1781	1728	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1782		gb_lcd.triggering_mode_irq = 0;
	1729	state->lcd.triggering_mode_irq = 0;
1783	1730	}
1784	1731	if ( ( SCROLLX & 0x03 ) == 0x03 )
1785	1732	{
1786		gb_lcd.pal_locked = UNLOCKED;
	1733	state->lcd.pal_locked = UNLOCKED;
1787	1734	}
1788		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0_GBC_PAL);
	1735	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0_GBC_PAL);
1789	1736	break;
1790	1737	case GB_LCD_STATE_LYXX_M0_GBC_PAL:
1791		gb_lcd.pal_locked = UNLOCKED;
	1738	state->lcd.pal_locked = UNLOCKED;
1792	1739	/* Check for HBLANK DMA */
1793		if( gb_lcd.hdma_enabled )
	1740	if( state->lcd.hdma_enabled )
1794	1741	{
1795	1742	gbc_hdma(machine, 0x10);
1796	1743	//              cpunum_set_reg( 0, LR35902_DMA_CYCLES, 36 );
1797	1744	}
1798	1745	else
1799	1746	{
1800		gb_lcd.hdma_possible = 1;
	1747	state->lcd.hdma_possible = 1;
1801	1748	}
1802		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(192 - gb_lcd.scrollx_adjust - gb_lcd.sprite_cycles), GB_LCD_STATE_LYXX_M0_PRE_INC);
	1749	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(192 - state->lcd.scrollx_adjust - state->lcd.sprite_cycles), GB_LCD_STATE_LYXX_M0_PRE_INC);
1803	1750	break;
1804	1751	case GB_LCD_STATE_LYXX_M0_PRE_INC:   /* Just before incrementing the line counter go to mode 2 internally */
1805		gb_lcd.cmp_line = CMPLINE;
	1752	state->lcd.cmp_line = CMPLINE;
1806	1753	if ( CURLINE < 143 )
1807	1754	{
1808		gb_lcd.mode = 2;
	1755	state->lcd.mode = 2;
1809	1756	if ( LCDSTAT & 0x20 )
1810	1757	{
1811		if ( ! gb_lcd.mode_irq )
	1758	if ( ! state->lcd.mode_irq )
1812	1759	{
1813		if ( ! gb_lcd.line_irq && ! gb_lcd.delayed_line_irq )
	1760	if ( ! state->lcd.line_irq && ! state->lcd.delayed_line_irq )
1814	1761	{
1815		gb_lcd.mode_irq = 1;
	1762	state->lcd.mode_irq = 1;
1816	1763	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1817	1764	}
1818	1765	}
1819	1766	else
1820	1767	{
1821		gb_lcd.mode_irq = 0;
	1768	state->lcd.mode_irq = 0;
1822	1769	}
1823	1770	}
1824	1771	}
1825		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0_INC);
	1772	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M0_INC);
1826	1773	break;
1827	1774	case GB_LCD_STATE_LYXX_M0_INC:   /* Increment LY, stay in M0 for 4 more cycles */
1828		gb_increment_scanline();
1829		gb_lcd.delayed_line_irq = gb_lcd.line_irq;
1830		gb_lcd.triggering_line_irq = ( ( gb_lcd.cmp_line == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
1831		gb_lcd.line_irq = 0;
1832		if ( ! gb_lcd.mode_irq && ! gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq && ! ( LCDSTAT & 0x20 ) )
	1775	gb_increment_scanline(state);
	1776	state->lcd.delayed_line_irq = state->lcd.line_irq;
	1777	state->lcd.triggering_line_irq = ( ( state->lcd.cmp_line == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
	1778	state->lcd.line_irq = 0;
	1779	if ( ! state->lcd.mode_irq && ! state->lcd.delayed_line_irq && state->lcd.triggering_line_irq && ! ( LCDSTAT & 0x20 ) )
1833	1780	{
1834		gb_lcd.line_irq = gb_lcd.triggering_line_irq;
	1781	state->lcd.line_irq = state->lcd.triggering_line_irq;
1835	1782	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1836	1783	}
1837		gb_lcd.hdma_possible = 0;
	1784	state->lcd.hdma_possible = 0;
1838	1785	/* Check if we're going into VBlank next */
1839	1786	if ( CURLINE == 144 )
1840	1787	{
1841		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY9X_M1);
	1788	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY9X_M1);
1842	1789	}
1843	1790	else
1844	1791	{
1845	1792	/* Internally switch to mode 2 */
1846		gb_lcd.mode = 2;
	1793	state->lcd.mode = 2;
1847	1794	/* Generate lcd interrupt if requested */
1848		if ( ! gb_lcd.mode_irq && ( LCDSTAT & 0x20 ) &&
1849		( ( ! gb_lcd.triggering_line_irq && ! gb_lcd.delayed_line_irq ) || ! ( LCDSTAT & 0x40 ) ) )
	1795	if ( ! state->lcd.mode_irq && ( LCDSTAT & 0x20 ) &&
	1796	( ( ! state->lcd.triggering_line_irq && ! state->lcd.delayed_line_irq ) || ! ( LCDSTAT & 0x40 ) ) )
1850	1797	{
1851		gb_lcd.mode_irq = 1;
	1798	state->lcd.mode_irq = 1;
1852	1799	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1853	1800	}
1854		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M2);
	1801	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LYXX_M2);
1855	1802	}
1856	1803	break;
1857	1804	case GB_LCD_STATE_LY00_M2:      /* Switch to mode 2 on line #0 */
1858	1805	/* Set Mode 2 lcdstate */
1859		gb_lcd.mode = 2;
	1806	state->lcd.mode = 2;
1860	1807	LCDSTAT = ( LCDSTAT & 0xFC ) | 0x02;
1861		gb_lcd.oam_locked = LOCKED;
	1808	state->lcd.oam_locked = LOCKED;
1862	1809	/* Generate lcd interrupt if requested */
1863		if ( ( LCDSTAT & 0x20 ) && ! gb_lcd.line_irq && ! gb_lcd.line_irq )
	1810	if ( ( LCDSTAT & 0x20 ) && ! state->lcd.line_irq && ! state->lcd.line_irq )
1864	1811	{
1865	1812	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1866	1813	}
1867	1814	/* Check for regular compensation of x-scroll register */
1868		gb_lcd.scrollx_adjust = ( SCROLLX & 0x04 ) ? 4 : 0;
	1815	state->lcd.scrollx_adjust = ( SCROLLX & 0x04 ) ? 4 : 0;
1869	1816	/* Mode 2 lasts approximately 80 clock cycles */
1870		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(80), GB_LCD_STATE_LYXX_M3);
	1817	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(80), GB_LCD_STATE_LYXX_M3);
1871	1818	break;
1872	1819	case GB_LCD_STATE_LYXX_M2:      /* Switch to mode 2 */
1873	1820	/* Update STAT register to the correct state */
1874	1821	LCDSTAT = (LCDSTAT & 0xFC) | 0x02;
1875		gb_lcd.oam_locked = LOCKED;
	1822	state->lcd.oam_locked = LOCKED;
1876	1823	/* Generate lcd interrupt if requested */
1877		if ( ( gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq && ! ( LCDSTAT & 0x20 ) ) ||
1878		( !gb_lcd.mode_irq && ! gb_lcd.line_irq && ! gb_lcd.delayed_line_irq && ( LCDSTAT & 0x20 ) ) )
	1824	if ( ( state->lcd.delayed_line_irq && state->lcd.triggering_line_irq && ! ( LCDSTAT & 0x20 ) ) ||
	1825	( !state->lcd.mode_irq && ! state->lcd.line_irq && ! state->lcd.delayed_line_irq && ( LCDSTAT & 0x20 ) ) )
1879	1826	{
1880	1827	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1881	1828	}
1882		gb_lcd.line_irq = gb_lcd.triggering_line_irq;
	1829	state->lcd.line_irq = state->lcd.triggering_line_irq;
1883	1830	/* Check if LY==LYC STAT bit should be set */
1884	1831	if ( CURLINE == CMPLINE )
1885	1832	{
r9784	r9785
1890	1837	LCDSTAT &= ~0x04;
1891	1838	}
1892	1839	/* Check for regular compensation of x-scroll register */
1893		gb_lcd.scrollx_adjust = ( SCROLLX & 0x04 ) ? 4 : 0;
	1840	state->lcd.scrollx_adjust = ( SCROLLX & 0x04 ) ? 4 : 0;
1894	1841	/* Mode 2 last for approximately 80 clock cycles */
1895		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(80), GB_LCD_STATE_LYXX_M3);
	1842	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(80), GB_LCD_STATE_LYXX_M3);
1896	1843	break;
1897	1844	case GB_LCD_STATE_LYXX_M3:      /* Switch to mode 3 */
1898		gb_select_sprites();
1899		gb_lcd.sprite_cycles = sprite_cycles[ gb_lcd.sprCount ];
	1845	gb_select_sprites(state);
	1846	state->lcd.sprite_cycles = sprite_cycles[ state->lcd.sprCount ];
1900	1847	/* Set Mode 3 lcdstate */
1901		gb_lcd.mode = 3;
	1848	state->lcd.mode = 3;
1902	1849	LCDSTAT = (LCDSTAT & 0xFC) | 0x03;
1903		gb_lcd.vram_locked = LOCKED;
1904		gb_lcd.pal_locked = LOCKED;
	1850	state->lcd.vram_locked = LOCKED;
	1851	state->lcd.pal_locked = LOCKED;
1905	1852	/* Check for compensations of x-scroll register */
1906	1853	/* Mode 3 lasts for approximately 172+cycles needed to handle sprites clock cycles */
1907		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(168 + gb_lcd.scrollx_adjust + gb_lcd.sprite_cycles), GB_LCD_STATE_LYXX_PRE_M0);
1908		gb_lcd.start_x = -1;
	1854	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(168 + state->lcd.scrollx_adjust + state->lcd.sprite_cycles), GB_LCD_STATE_LYXX_PRE_M0);
	1855	state->lcd.start_x = -1;
1909	1856	break;
1910	1857	case GB_LCD_STATE_LY9X_M1:      /* Switch to or stay in mode 1 */
1911	1858	if ( CURLINE == 144 )
r9784	r9785
1913	1860	/* Trigger VBlank interrupt */
1914	1861	cputag_set_input_line( machine, "maincpu", VBL_INT, ASSERT_LINE );
1915	1862	/* Set VBlank lcdstate */
1916		gb_lcd.mode = 1;
	1863	state->lcd.mode = 1;
1917	1864	LCDSTAT = (LCDSTAT & 0xFC) | 0x01;
1918	1865	/* Trigger LCD interrupt if requested */
1919	1866	if ( LCDSTAT & 0x10 )
r9784	r9785
1930	1877	{
1931	1878	LCDSTAT &= ~0x04;
1932	1879	}
1933		if ( gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq )
	1880	if ( state->lcd.delayed_line_irq && state->lcd.triggering_line_irq )
1934	1881	{
1935	1882	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1936	1883	}
1937		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(452), GB_LCD_STATE_LY9X_M1_INC);
	1884	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(452), GB_LCD_STATE_LY9X_M1_INC);
1938	1885	break;
1939	1886	case GB_LCD_STATE_LY9X_M1_INC:      /* Increment scanline counter */
1940		gb_increment_scanline();
1941		gb_lcd.delayed_line_irq = gb_lcd.line_irq;
1942		gb_lcd.triggering_line_irq = ( ( CMPLINE == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
1943		gb_lcd.line_irq = 0;
1944		if ( ! gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq )
	1887	gb_increment_scanline(state);
	1888	state->lcd.delayed_line_irq = state->lcd.line_irq;
	1889	state->lcd.triggering_line_irq = ( ( CMPLINE == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
	1890	state->lcd.line_irq = 0;
	1891	if ( ! state->lcd.delayed_line_irq && state->lcd.triggering_line_irq )
1945	1892	{
1946		gb_lcd.line_irq = gb_lcd.triggering_line_irq;
	1893	state->lcd.line_irq = state->lcd.triggering_line_irq;
1947	1894	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1948	1895	}
1949		if ( gb_lcd.current_line == 153 )
	1896	if ( state->lcd.current_line == 153 )
1950	1897	{
1951		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M1);
	1898	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M1);
1952	1899	}
1953	1900	else
1954	1901	{
1955		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY9X_M1);
	1902	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY9X_M1);
1956	1903	}
1957	1904	break;
1958	1905	case GB_LCD_STATE_LY00_M1:      /* we stay in VBlank but current line counter should already be incremented */
1959	1906	/* Check LY=LYC for line #153 */
1960		if ( gb_lcd.delayed_line_irq )
	1907	if ( state->lcd.delayed_line_irq )
1961	1908	{
1962		if ( gb_lcd.triggering_line_irq )
	1909	if ( state->lcd.triggering_line_irq )
1963	1910	{
1964	1911	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1965	1912	}
1966	1913	}
1967		gb_lcd.delayed_line_irq = gb_lcd.delayed_line_irq | gb_lcd.line_irq;
	1914	state->lcd.delayed_line_irq = state->lcd.delayed_line_irq | state->lcd.line_irq;
1968	1915	if ( CURLINE == CMPLINE )
1969	1916	{
1970	1917	LCDSTAT |= 0x04;
r9784	r9785
1973	1920	{
1974	1921	LCDSTAT &= ~0x04;
1975	1922	}
1976		gb_increment_scanline();
1977		gb_lcd.triggering_line_irq = ( ( CMPLINE == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
1978		gb_lcd.line_irq = 0;
	1923	gb_increment_scanline(state);
	1924	state->lcd.triggering_line_irq = ( ( CMPLINE == CURLINE ) && ( LCDSTAT & 0x40 ) ) ? 1 : 0;
	1925	state->lcd.line_irq = 0;
1979	1926	LCDSTAT &= 0xFB;
1980		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M1_1);
	1927	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M1_1);
1981	1928	break;
1982	1929	case GB_LCD_STATE_LY00_M1_1:
1983		if ( ! gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq )
	1930	if ( ! state->lcd.delayed_line_irq && state->lcd.triggering_line_irq )
1984	1931	{
1985		gb_lcd.line_irq = gb_lcd.triggering_line_irq;
	1932	state->lcd.line_irq = state->lcd.triggering_line_irq;
1986	1933	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1987	1934	}
1988		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M1_2);
	1935	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M1_2);
1989	1936	break;
1990	1937	case GB_LCD_STATE_LY00_M1_2:   /* Rest of line #0 during VBlank */
1991		if ( gb_lcd.delayed_line_irq && gb_lcd.triggering_line_irq )
	1938	if ( state->lcd.delayed_line_irq && state->lcd.triggering_line_irq )
1992	1939	{
1993		gb_lcd.line_irq = gb_lcd.triggering_line_irq;
	1940	state->lcd.line_irq = state->lcd.triggering_line_irq;
1994	1941	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
1995	1942	}
1996	1943	if ( CURLINE == CMPLINE )
r9784	r9785
2001	1948	{
2002	1949	LCDSTAT &= ~0x04;
2003	1950	}
2004		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(444), GB_LCD_STATE_LY00_M0);
	1951	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(444), GB_LCD_STATE_LY00_M0);
2005	1952	break;
2006	1953	case GB_LCD_STATE_LY00_M0:      /* The STAT register seems to go to 0 for about 4 cycles */
2007	1954	/* Set Mode 0 lcdstat */
2008		gb_lcd.mode = 0;
2009		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M2);
	1955	state->lcd.mode = 0;
	1956	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(4), GB_LCD_STATE_LY00_M2);
2010	1957	break;
2011	1958	}
2012	1959	}
2013	1960	else
2014	1961	{
2015		gb_increment_scanline();
2016		if ( gb_lcd.current_line < 144 )
	1962	gb_increment_scanline(state);
	1963	if ( state->lcd.current_line < 144 )
2017	1964	{
2018		update_scanline( machine );
	1965	(*state->update_scanline)( machine );
2019	1966	}
2020		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(456), 0);
	1967	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(456), 0);
2021	1968	}
2022	1969	}
2023	1970
2024	1971	static void gb_lcd_switch_on( running_machine *machine )
2025	1972	{
2026		gb_lcd.current_line = 0;
2027		gb_lcd.previous_line = 153;
2028		gb_lcd.window_lines_drawn = 0;
2029		gb_lcd.line_irq = 0;
2030		gb_lcd.delayed_line_irq = 0;
2031		gb_lcd.mode = 0;
2032		gb_lcd.oam_locked = LOCKED;   /* TODO: Investigate whether this OAM locking is correct. */
	1973	gb_state *state = machine->driver_data<gb_state>();
	1974	state->lcd.current_line = 0;
	1975	state->lcd.previous_line = 153;
	1976	state->lcd.window_lines_drawn = 0;
	1977	state->lcd.line_irq = 0;
	1978	state->lcd.delayed_line_irq = 0;
	1979	state->lcd.mode = 0;
	1980	state->lcd.oam_locked = LOCKED;   /* TODO: Investigate whether this OAM locking is correct. */
2033	1981	/* Check for LY=LYC coincidence */
2034	1982	if ( CURLINE == CMPLINE )
2035	1983	{
r9784	r9785
2040	1988	cputag_set_input_line( machine, "maincpu", LCD_INT, ASSERT_LINE );
2041	1989	}
2042	1990	}
2043		gb_lcd.state = GB_LCD_STATE_LY00_M2;
2044		timer_adjust_oneshot(gb_lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(80), GB_LCD_STATE_LYXX_M3);
	1991	state->lcd.state = GB_LCD_STATE_LY00_M2;
	1992	timer_adjust_oneshot(state->lcd.lcd_timer, machine->device<cpu_device>("maincpu")->cycles_to_attotime(80), GB_LCD_STATE_LYXX_M3);
2045	1993	}
2046	1994
2047	1995	READ8_HANDLER( gb_video_r )
2048	1996	{
2049		return gb_lcd.gb_vid_regs[offset];
	1997	gb_state *state = space->machine->driver_data<gb_state>();
	1998	return state->lcd.gb_vid_regs[offset];
2050	1999	}
2051	2000
2052	2001	READ8_HANDLER( gb_vram_r )
2053	2002	{
2054		return ( gb_lcd.vram_locked == LOCKED ) ? 0xFF : gb_lcd.gb_vram_ptr[offset];
	2003	gb_state *state = space->machine->driver_data<gb_state>();
	2004	return ( state->lcd.vram_locked == LOCKED ) ? 0xFF : state->lcd.gb_vram_ptr[offset];
2055	2005	}
2056	2006
2057	2007	WRITE8_HANDLER( gb_vram_w )
2058	2008	{
2059		if ( gb_lcd.vram_locked == LOCKED )
	2009	gb_state *state = space->machine->driver_data<gb_state>();
	2010	if ( state->lcd.vram_locked == LOCKED )
2060	2011	{
2061	2012	return;
2062	2013	}
2063		gb_lcd.gb_vram_ptr[offset] = data;
	2014	state->lcd.gb_vram_ptr[offset] = data;
2064	2015	}
2065	2016
2066	2017	READ8_HANDLER( gb_oam_r )
2067	2018	{
2068		return ( gb_lcd.oam_locked == LOCKED ) ? 0xFF : gb_lcd.gb_oam->base()[offset];
	2019	gb_state *state = space->machine->driver_data<gb_state>();
	2020	return ( state->lcd.oam_locked == LOCKED ) ? 0xFF : state->lcd.gb_oam->base()[offset];
2069	2021	}
2070	2022
2071	2023	WRITE8_HANDLER( gb_oam_w )
2072	2024	{
2073		if ( gb_lcd.oam_locked == LOCKED || offset >= 0xa0 )
	2025	gb_state *state = space->machine->driver_data<gb_state>();
	2026	if ( state->lcd.oam_locked == LOCKED || offset >= 0xa0 )
2074	2027	{
2075	2028	return;
2076	2029	}
2077		gb_lcd.gb_oam->base()[offset] = data;
	2030	state->lcd.gb_oam->base()[offset] = data;
2078	2031	}
2079	2032
2080	2033	WRITE8_HANDLER ( gb_video_w )
2081	2034	{
	2035	gb_state *state = space->machine->driver_data<gb_state>();
2082	2036	switch (offset)
2083	2037	{
2084	2038	case 0x00:                  /* LCDC - LCD Control */
2085		gb_lcd.gb_chrgen = gb_lcd.gb_vram->base() + ((data & 0x10) ? 0x0000 : 0x0800);
2086		gb_lcd.gb_tile_no_mod = (data & 0x10) ? 0x00 : 0x80;
2087		gb_lcd.gb_bgdtab = gb_lcd.gb_vram->base() + ((data & 0x08) ? 0x1C00 : 0x1800 );
2088		gb_lcd.gb_wndtab = gb_lcd.gb_vram->base() + ((data & 0x40) ? 0x1C00 : 0x1800 );
	2039	state->lcd.gb_chrgen = state->lcd.gb_vram->base() + ((data & 0x10) ? 0x0000 : 0x0800);
	2040	state->lcd.gb_tile_no_mod = (data & 0x10) ? 0x00 : 0x80;
	2041	state->lcd.gb_bgdtab = state->lcd.gb_vram->base() + ((data & 0x08) ? 0x1C00 : 0x1800 );
	2042	state->lcd.gb_wndtab = state->lcd.gb_vram->base() + ((data & 0x40) ? 0x1C00 : 0x1800 );
2089	2043	/* if LCD controller is switched off, set STAT and LY to 00 */
2090	2044	if ( ! ( data & 0x80 ) )
2091	2045	{
2092	2046	LCDSTAT &= ~0x03;
2093	2047	CURLINE = 0;
2094		gb_lcd.oam_locked = UNLOCKED;
2095		gb_lcd.vram_locked = UNLOCKED;
	2048	state->lcd.oam_locked = UNLOCKED;
	2049	state->lcd.vram_locked = UNLOCKED;
2096	2050	}
2097	2051	/* If LCD is being switched on */
2098	2052	if ( !( LCDCONT & 0x80 ) && ( data & 0x80 ) )
r9784	r9785
2123	2077	- 0x20 -> 0x00/0x08/0x10/0x20/0x40 (mode 2, after m2int) - don't trigger
2124	2078	- 0x20 -> 0x00/0x08/0x10/0x20/0x40 (mode 3, after m2int) - don't trigger
2125	2079	*/
2126		if ( ! gb_lcd.mode_irq && ( ( gb_lcd.mode == 1 ) ||
	2080	if ( ! state->lcd.mode_irq && ( ( state->lcd.mode == 1 ) ||
2127	2081	( ( LCDSTAT & 0x40 ) && ! ( data & 0x68 ) ) ||
2128	2082	( ! ( LCDSTAT & 0x40 ) && ( data & 0x40 ) && ( LCDSTAT & 0x04 ) ) ||
2129	2083	( ! ( LCDSTAT & 0x48 ) && ( data & 0x08 ) ) ||
r9784	r9785
2138	2092	- 0x20 -> 0x00/0x10/0x20/0x40 (mode 0, after m2int) - trigger (stat bug)
2139	2093	- 0x00 -> 0xXX (mode 0) - trigger stat bug
2140	2094	*/
2141		if ( gb_lcd.mode_irq && gb_lcd.mode == 0 )
	2095	if ( state->lcd.mode_irq && state->lcd.mode == 0 )
2142	2096	{
2143	2097	cputag_set_input_line( space->machine, "maincpu", LCD_INT, ASSERT_LINE );
2144	2098	}
r9784	r9785
2151	2105	{
2152	2106	if ( CURLINE == data )
2153	2107	{
2154		if ( gb_lcd.state != GB_LCD_STATE_LYXX_M0_INC && gb_lcd.state != GB_LCD_STATE_LY9X_M1_INC )
	2108	if ( state->lcd.state != GB_LCD_STATE_LYXX_M0_INC && state->lcd.state != GB_LCD_STATE_LY9X_M1_INC )
2155	2109	{
2156	2110	LCDSTAT |= 0x04;
2157	2111	/* Generate lcd interrupt if requested */
r9784	r9785
2164	2118	else
2165	2119	{
2166	2120	LCDSTAT &= 0xFB;
2167		gb_lcd.triggering_line_irq = 0;
	2121	state->lcd.triggering_line_irq = 0;
2168	2122	}
2169	2123	}
2170	2124	break;
2171	2125	case 0x06:                  /* DMA - DMA Transfer and Start Address */
2172	2126	{
2173		UINT8 *P = gb_lcd.gb_oam->base();
	2127	UINT8 *P = state->lcd.gb_oam->base();
2174	2128	offset = (UINT16) data << 8;
2175	2129	for (data = 0; data < 0xA0; data++)
2176	2130	*P++ = space->read_byte(offset++);
2177	2131	}
2178	2132	return;
2179	2133	case 0x07:                  /* BGP - Background Palette */
2180		update_scanline( space->machine );
2181		gb_lcd.gb_bpal[0] = data & 0x3;
2182		gb_lcd.gb_bpal[1] = (data & 0xC) >> 2;
2183		gb_lcd.gb_bpal[2] = (data & 0x30) >> 4;
2184		gb_lcd.gb_bpal[3] = (data & 0xC0) >> 6;
	2134	(*state->update_scanline)( space->machine );
	2135	state->lcd.gb_bpal[0] = data & 0x3;
	2136	state->lcd.gb_bpal[1] = (data & 0xC) >> 2;
	2137	state->lcd.gb_bpal[2] = (data & 0x30) >> 4;
	2138	state->lcd.gb_bpal[3] = (data & 0xC0) >> 6;
2185	2139	break;
2186	2140	case 0x08:                  /* OBP0 - Object Palette 0 */
2187		//      update_scanline( machine );
2188		gb_lcd.gb_spal0[0] = data & 0x3;
2189		gb_lcd.gb_spal0[1] = (data & 0xC) >> 2;
2190		gb_lcd.gb_spal0[2] = (data & 0x30) >> 4;
2191		gb_lcd.gb_spal0[3] = (data & 0xC0) >> 6;
	2141	//      (*state->update_scanline)( machine );
	2142	state->lcd.gb_spal0[0] = data & 0x3;
	2143	state->lcd.gb_spal0[1] = (data & 0xC) >> 2;
	2144	state->lcd.gb_spal0[2] = (data & 0x30) >> 4;
	2145	state->lcd.gb_spal0[3] = (data & 0xC0) >> 6;
2192	2146	break;
2193	2147	case 0x09:                  /* OBP1 - Object Palette 1 */
2194		//      update_scanline( machine );
2195		gb_lcd.gb_spal1[0] = data & 0x3;
2196		gb_lcd.gb_spal1[1] = (data & 0xC) >> 2;
2197		gb_lcd.gb_spal1[2] = (data & 0x30) >> 4;
2198		gb_lcd.gb_spal1[3] = (data & 0xC0) >> 6;
	2148	//      (*state->update_scanline)( machine );
	2149	state->lcd.gb_spal1[0] = data & 0x3;
	2150	state->lcd.gb_spal1[1] = (data & 0xC) >> 2;
	2151	state->lcd.gb_spal1[2] = (data & 0x30) >> 4;
	2152	state->lcd.gb_spal1[3] = (data & 0xC0) >> 6;
2199	2153	break;
2200	2154	case 0x02:                  /* SCY - Scroll Y */
2201	2155	case 0x03:                  /* SCX - Scroll X */
2202		update_scanline( space->machine );
	2156	(*state->update_scanline)( space->machine );
2203	2157	case 0x0A:                  /* WY - Window Y position */
2204	2158	case 0x0B:                  /* WX - Window X position */
2205	2159	break;
2206	2160	default:                  /* Unknown register, no change */
2207	2161	return;
2208	2162	}
2209		gb_lcd.gb_vid_regs[ offset ] = data;
	2163	state->lcd.gb_vid_regs[ offset ] = data;
2210	2164	}
2211	2165
2212	2166	READ8_HANDLER( gbc_video_r )
2213	2167	{
	2168	gb_state *state = space->machine->driver_data<gb_state>();
2214	2169	switch( offset )
2215	2170	{
2216	2171	case 0x11:   /* FF51 */
r9784	r9785
2220	2175	return 0xFF;
2221	2176	case 0x29:   /* FF69 */
2222	2177	case 0x2B:   /* FF6B */
2223		if ( gb_lcd.pal_locked == LOCKED )
	2178	if ( state->lcd.pal_locked == LOCKED )
2224	2179	{
2225	2180	return 0xFF;
2226	2181	}
2227	2182	break;
2228	2183	}
2229		return gb_lcd.gb_vid_regs[offset];
	2184	return state->lcd.gb_vid_regs[offset];
2230	2185	}
2231	2186
2232	2187	WRITE8_HANDLER ( gbc_video_w )
2233	2188	{
	2189	gb_state *state = space->machine->driver_data<gb_state>();
2234	2190	switch( offset )
2235	2191	{
2236	2192	case 0x00:      /* LCDC - LCD Control */
2237		gb_lcd.gb_chrgen = gb_lcd.gb_vram->base() + ((data & 0x10) ? 0x0000 : 0x0800);
2238		gb_lcd.gbc_chrgen = gb_lcd.gb_vram->base() + ((data & 0x10) ? 0x2000 : 0x2800);
2239		gb_lcd.gb_tile_no_mod = (data & 0x10) ? 0x00 : 0x80;
2240		gb_lcd.gb_bgdtab = gb_lcd.gb_vram->base() + ((data & 0x08) ? 0x1C00 : 0x1800);
2241		gb_lcd.gbc_bgdtab = gb_lcd.gb_vram->base() + ((data & 0x08) ? 0x3C00 : 0x3800);
2242		gb_lcd.gb_wndtab = gb_lcd.gb_vram->base() + ((data & 0x40) ? 0x1C00 : 0x1800);
2243		gb_lcd.gbc_wndtab = gb_lcd.gb_vram->base() + ((data & 0x40) ? 0x3C00 : 0x3800);
	2193	state->lcd.gb_chrgen = state->lcd.gb_vram->base() + ((data & 0x10) ? 0x0000 : 0x0800);
	2194	state->lcd.gbc_chrgen = state->lcd.gb_vram->base() + ((data & 0x10) ? 0x2000 : 0x2800);
	2195	state->lcd.gb_tile_no_mod = (data & 0x10) ? 0x00 : 0x80;
	2196	state->lcd.gb_bgdtab = state->lcd.gb_vram->base() + ((data & 0x08) ? 0x1C00 : 0x1800);
	2197	state->lcd.gbc_bgdtab = state->lcd.gb_vram->base() + ((data & 0x08) ? 0x3C00 : 0x3800);
	2198	state->lcd.gb_wndtab = state->lcd.gb_vram->base() + ((data & 0x40) ? 0x1C00 : 0x1800);
	2199	state->lcd.gbc_wndtab = state->lcd.gb_vram->base() + ((data & 0x40) ? 0x3C00 : 0x3800);
2244	2200	/* if LCD controller is switched off, set STAT to 00 */
2245	2201	if ( ! ( data & 0x80 ) )
2246	2202	{
2247	2203	LCDSTAT &= ~0x03;
2248	2204	CURLINE = 0;
2249		gb_lcd.oam_locked = UNLOCKED;
2250		gb_lcd.vram_locked = UNLOCKED;
2251		gb_lcd.pal_locked = UNLOCKED;
	2205	state->lcd.oam_locked = UNLOCKED;
	2206	state->lcd.vram_locked = UNLOCKED;
	2207	state->lcd.pal_locked = UNLOCKED;
2252	2208	}
2253	2209	/* If LCD is being switched on */
2254	2210	if ( !( LCDCONT & 0x80 ) && ( data & 0x80 ) )
r9784	r9785
2263	2219	/*
2264	2220	- 0x20 -> 0x08/0x18/0x28/0x48 (mode 0, after m2int) - trigger
2265	2221	*/
2266		if ( gb_lcd.mode_irq && gb_lcd.mode == 0 && ( LCDSTAT & 0x28 ) == 0x20 && ( data & 0x08 ) )
	2222	if ( state->lcd.mode_irq && state->lcd.mode == 0 && ( LCDSTAT & 0x28 ) == 0x20 && ( data & 0x08 ) )
2267	2223	{
2268	2224	cputag_set_input_line( space->machine, "maincpu", LCD_INT, ASSERT_LINE );
2269	2225	}
2270	2226	/* Check if line irqs are being disabled */
2271	2227	if ( ! ( data & 0x40 ) )
2272	2228	{
2273		gb_lcd.delayed_line_irq = 0;
	2229	state->lcd.delayed_line_irq = 0;
2274	2230	}
2275	2231	/* Check if line irqs are being enabled */
2276	2232	if ( ! ( LCDSTAT & 0x40 ) && ( data & 0x40 ) )
2277	2233	{
2278	2234	if ( CMPLINE == CURLINE )
2279	2235	{
2280		gb_lcd.line_irq = 1;
	2236	state->lcd.line_irq = 1;
2281	2237	cputag_set_input_line( space->machine, "maincpu", LCD_INT, ASSERT_LINE );
2282	2238	}
2283	2239	}
r9784	r9785
2286	2242	case 0x05:                      /* LYC */
2287	2243	if ( CMPLINE != data )
2288	2244	{
2289		if ( ( gb_lcd.state != GB_LCD_STATE_LYXX_M0_PRE_INC && CURLINE == data ) ||
2290		( gb_lcd.state == GB_LCD_STATE_LYXX_M0_INC && gb_lcd.triggering_line_irq ) )
	2245	if ( ( state->lcd.state != GB_LCD_STATE_LYXX_M0_PRE_INC && CURLINE == data ) ||
	2246	( state->lcd.state == GB_LCD_STATE_LYXX_M0_INC && state->lcd.triggering_line_irq ) )
2291	2247	{
2292	2248	LCDSTAT |= 0x04;
2293	2249	/* Generate lcd interrupt if requested */
r9784	r9785
2299	2255	else
2300	2256	{
2301	2257	LCDSTAT &= 0xFB;
2302		gb_lcd.triggering_line_irq = 0;
2303		gb_lcd.cmp_line = data;
	2258	state->lcd.triggering_line_irq = 0;
	2259	state->lcd.cmp_line = data;
2304	2260	}
2305	2261	}
2306	2262	break;
2307	2263	case 0x07:      /* BGP - GB background palette */
2308		update_scanline( space->machine );
2309		gb_lcd.gb_bpal[0] = data & 0x3;
2310		gb_lcd.gb_bpal[1] = (data & 0xC) >> 2;
2311		gb_lcd.gb_bpal[2] = (data & 0x30) >> 4;
2312		gb_lcd.gb_bpal[3] = (data & 0xC0) >> 6;
	2264	(*state->update_scanline)( space->machine );
	2265	state->lcd.gb_bpal[0] = data & 0x3;
	2266	state->lcd.gb_bpal[1] = (data & 0xC) >> 2;
	2267	state->lcd.gb_bpal[2] = (data & 0x30) >> 4;
	2268	state->lcd.gb_bpal[3] = (data & 0xC0) >> 6;
2313	2269	break;
2314	2270	case 0x08:      /* OBP0 - GB Object 0 palette */
2315		gb_lcd.gb_spal0[0] = data & 0x3;
2316		gb_lcd.gb_spal0[1] = (data & 0xC) >> 2;
2317		gb_lcd.gb_spal0[2] = (data & 0x30) >> 4;
2318		gb_lcd.gb_spal0[3] = (data & 0xC0) >> 6;
	2271	state->lcd.gb_spal0[0] = data & 0x3;
	2272	state->lcd.gb_spal0[1] = (data & 0xC) >> 2;
	2273	state->lcd.gb_spal0[2] = (data & 0x30) >> 4;
	2274	state->lcd.gb_spal0[3] = (data & 0xC0) >> 6;
2319	2275	break;
2320	2276	case 0x09:      /* OBP1 - GB Object 1 palette */
2321		gb_lcd.gb_spal1[0] = data & 0x3;
2322		gb_lcd.gb_spal1[1] = (data & 0xC) >> 2;
2323		gb_lcd.gb_spal1[2] = (data & 0x30) >> 4;
2324		gb_lcd.gb_spal1[3] = (data & 0xC0) >> 6;
	2277	state->lcd.gb_spal1[0] = data & 0x3;
	2278	state->lcd.gb_spal1[1] = (data & 0xC) >> 2;
	2279	state->lcd.gb_spal1[2] = (data & 0x30) >> 4;
	2280	state->lcd.gb_spal1[3] = (data & 0xC0) >> 6;
2325	2281	break;
2326	2282	case 0x0c:      /* Undocumented register involved in selecting gb/gbc mode */
2327	2283	logerror( "Write to undocumented register: %X = %X\n", offset, data );
2328	2284	break;
2329	2285	case 0x0F:      /* VBK - VRAM bank select */
2330		gb_lcd.gb_vram_ptr = gb_lcd.gb_vram->base() + ( data & 0x01 ) * 0x2000;
	2286	state->lcd.gb_vram_ptr = state->lcd.gb_vram->base() + ( data & 0x01 ) * 0x2000;
2331	2287	data |= 0xFE;
2332	2288	break;
2333	2289	case 0x11:      /* HDMA1 - HBL General DMA - Source High */
r9784	r9785
2344	2300	case 0x15:      /* HDMA5 - HBL General DMA - Mode, Length */
2345	2301	if( !(data & 0x80) )
2346	2302	{
2347		if( gb_lcd.hdma_enabled )
	2303	if( state->lcd.hdma_enabled )
2348	2304	{
2349		gb_lcd.hdma_enabled = 0;
	2305	state->lcd.hdma_enabled = 0;
2350	2306	data = HDMA5 & 0x80;
2351	2307	}
2352	2308	else
r9784	r9785
2360	2316	else
2361	2317	{
2362	2318	/* H-Blank DMA */
2363		gb_lcd.hdma_enabled = 1;
	2319	state->lcd.hdma_enabled = 1;
2364	2320	data &= 0x7f;
2365		gb_lcd.gb_vid_regs[offset] = data;
	2321	state->lcd.gb_vid_regs[offset] = data;
2366	2322	/* Check if HDMA should be immediately performed */
2367		if ( gb_lcd.hdma_possible )
	2323	if ( state->lcd.hdma_possible )
2368	2324	{
2369	2325	gbc_hdma( space->machine, 0x10 );
2370	2326	//              cpunum_set_reg( 0, LR35902_DMA_CYCLES, 36 );
2371		gb_lcd.hdma_possible = 0;
	2327	state->lcd.hdma_possible = 0;
2372	2328	}
2373	2329	}
2374	2330	break;
2375	2331	case 0x28:      /* BCPS - Background palette specification */
2376	2332	GBCBCPS = data;
2377	2333	if (data & 0x01)
2378		GBCBCPD = gb_lcd.cgb_bpal[( data >> 1 ) & 0x1F] >> 8;
	2334	GBCBCPD = state->lcd.cgb_bpal[( data >> 1 ) & 0x1F] >> 8;
2379	2335	else
2380		GBCBCPD = gb_lcd.cgb_bpal[( data >> 1 ) & 0x1F] & 0xFF;
	2336	GBCBCPD = state->lcd.cgb_bpal[( data >> 1 ) & 0x1F] & 0xFF;
2381	2337	break;
2382	2338	case 0x29:      /* BCPD - background palette data */
2383		if ( gb_lcd.pal_locked == LOCKED )
	2339	if ( state->lcd.pal_locked == LOCKED )
2384	2340	{
2385	2341	return;
2386	2342	}
2387	2343	GBCBCPD = data;
2388	2344	if (GBCBCPS & 0x01)
2389		gb_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] = ((data << 8) | (gb_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] & 0xFF)) & 0x7FFF;
	2345	state->lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] = ((data << 8) | (state->lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] & 0xFF)) & 0x7FFF;
2390	2346	else
2391		gb_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] = ((gb_lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] & 0xFF00) | data) & 0x7FFF;
	2347	state->lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] = ((state->lcd.cgb_bpal[( GBCBCPS >> 1 ) & 0x1F] & 0xFF00) | data) & 0x7FFF;
2392	2348	if( GBCBCPS & 0x80 )
2393	2349	{
2394	2350	GBCBCPS++;
r9784	r9785
2398	2354	case 0x2A:      /* OCPS - Object palette specification */
2399	2355	GBCOCPS = data;
2400	2356	if (data & 0x01)
2401		GBCOCPD = gb_lcd.cgb_spal[( data >> 1 ) & 0x1F] >> 8;
	2357	GBCOCPD = state->lcd.cgb_spal[( data >> 1 ) & 0x1F] >> 8;
2402	2358	else
2403		GBCOCPD = gb_lcd.cgb_spal[( data >> 1 ) & 0x1F] & 0xFF;
	2359	GBCOCPD = state->lcd.cgb_spal[( data >> 1 ) & 0x1F] & 0xFF;
2404	2360	break;
2405	2361	case 0x2B:      /* OCPD - Object palette data */
2406		if ( gb_lcd.pal_locked == LOCKED )
	2362	if ( state->lcd.pal_locked == LOCKED )
2407	2363	{
2408	2364	return;
2409	2365	}
2410	2366	GBCOCPD = data;
2411	2367	if (GBCOCPS & 0x01)
2412		gb_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] = ((data << 8) | (gb_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] & 0xFF)) & 0x7FFF;
	2368	state->lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] = ((data << 8) | (state->lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] & 0xFF)) & 0x7FFF;
2413	2369	else
2414		gb_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] = ((gb_lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] & 0xFF00) | data) & 0x7FFF;
	2370	state->lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] = ((state->lcd.cgb_spal[( GBCOCPS >> 1 ) & 0x1F] & 0xFF00) | data) & 0x7FFF;
2415	2371	if( GBCOCPS & 0x80 )
2416	2372	{
2417	2373	GBCOCPS++;
r9784	r9785
2425	2381	data = 0xFE | ( data & 0x01 );
2426	2382	if ( data & 0x01 )
2427	2383	{
2428		gb_lcd.gbc_mode = 0;
	2384	state->lcd.gbc_mode = 0;
2429	2385	}
2430	2386	break;
2431	2387	case 0x32:
r9784	r9785
2449	2405	return;
2450	2406	}
2451	2407
2452		gb_lcd.gb_vid_regs[offset] = data;
	2408	state->lcd.gb_vid_regs[offset] = data;
2453	2409	}
2454	2410
2455	2411
2456	2412	UINT8 *gb_get_vram_ptr(running_machine *machine)
2457	2413	{
2458		return gb_lcd.gb_vram_ptr;
	2414	gb_state *state = machine->driver_data<gb_state>();
	2415	return state->lcd.gb_vram_ptr;
2459	2416	}
2460	2417

src/mess/includes/kc.h

r9784	r9785
74	74	int kc85_blink_state;
75	75	unsigned char *kc85_4_display_video_ram;
76	76	unsigned char *kc85_4_video_ram;
	77	const struct kc85_module *modules[256>>2];
77	78	};
78	79
79	80

src/mess/includes/cpschngr.h

r9784	r9785
33	33	int stars1y;
34	34	int stars2x;
35	35	int stars2y;
	36	const struct CPS1config *cps1_game_config;
36	37	UINT8 empty_tile8x8[8*8];
37	38	UINT8 empty_tile[32*32/2];
38	39	};

src/mess/includes/gb.h

r9784	r9785
32	32	#define SGB_FRAMES_PER_SECOND   61.17
33	33
34	34
35		/*----------- defined in audio/gb.c -----------*/
	35	#define MAX_ROMBANK 512
	36	#define MAX_RAMBANK 256
36	37
37		DECLARE_LEGACY_SOUND_DEVICE(GAMEBOY, gameboy_sound);
38	38
39		/* Custom Sound Interface */
40		READ8_DEVICE_HANDLER( gb_sound_r );
41		WRITE8_DEVICE_HANDLER( gb_sound_w );
42		READ8_DEVICE_HANDLER( gb_wave_r );
43		WRITE8_DEVICE_HANDLER( gb_wave_w );
	39	#define _NR_GB_VID_REGS      0x40
44	40
	41	struct layer_struct {
	42	UINT8  enabled;
	43	UINT8  *bg_tiles;
	44	UINT8  *bg_map;
	45	UINT8  xindex;
	46	UINT8  xshift;
	47	UINT8  xstart;
	48	UINT8  xend;
	49	/* GBC specific */
	50	UINT8  *gbc_map;
	51	INT16  bgline;
	52	};
45	53
	54	typedef struct {
	55	int   window_lines_drawn;
	56
	57	UINT8   gb_vid_regs[_NR_GB_VID_REGS];
	58	UINT8   bg_zbuf[160];
	59
	60	UINT16   cgb_bpal[32];   /* CGB current background palette table */
	61	UINT16   cgb_spal[32];   /* CGB current sprite palette table */
	62
	63	UINT8   gb_bpal[4];      /* Background palette */
	64	UINT8   gb_spal0[4];   /* Sprite 0 palette */
	65	UINT8   gb_spal1[4];   /* Sprite 1 palette */
	66
	67	/* Things used to render current line */
	68	int current_line;      /* Current line */
	69	int cmp_line;         /* Compare line */
	70	int sprCount;         /* Number of sprites on current line */
	71	int sprite[10];         /* References to sprites to draw on current line */
	72	int previous_line;      /* Previous line we've drawn in */
	73	int start_x;         /* Pixel to start drawing from (inclusive) */
	74	int end_x;            /* Pixel to end drawing (exclusive) */
	75	int mode;            /* Keep track of internal STAT mode */
	76	int state;            /* Current state of the video state machine */
	77	int lcd_irq_line;
	78	int triggering_line_irq;
	79	int line_irq;
	80	int triggering_mode_irq;
	81	int mode_irq;
	82	int delayed_line_irq;
	83	int sprite_cycles;
	84	int scrollx_adjust;
	85	int oam_locked;
	86	int vram_locked;
	87	int pal_locked;
	88	int hdma_enabled;
	89	int hdma_possible;
	90	struct layer_struct   layer[2];
	91	emu_timer *lcd_timer;
	92	int gbc_mode;
	93
	94	region_info *gb_vram;      /* Pointer to VRAM */
	95	region_info *gb_oam;      /* Pointer to OAM memory */
	96	UINT8   *gb_vram_ptr;
	97	UINT8   *gb_chrgen;      /* Character generator */
	98	UINT8   *gb_bgdtab;      /* Background character table */
	99	UINT8   *gb_wndtab;      /* Window character table */
	100	UINT8   gb_tile_no_mod;
	101	UINT8   *gbc_chrgen;   /* CGB Character generator */
	102	UINT8   *gbc_bgdtab;   /* CGB Background character table */
	103	UINT8   *gbc_wndtab;   /* CGB Window character table */
	104	} gb_lcd_t;
	105
	106
	107
	108	class gb_state : public driver_device
	109	{
	110	public:
	111	gb_state(running_machine &machine, const driver_device_config_base &config)
	112	: driver_device(machine, config) { }
	113
	114	UINT16 sgb_pal_data[4096];
	115	UINT8 sgb_pal_map[20][18];
	116	UINT16 sgb_pal[128];
	117	UINT8 *sgb_tile_data;
	118	UINT8 sgb_tile_map[2048];
	119	UINT8 sgb_window_mask;
	120	UINT8 sgb_hack;
	121	//gb_state driver_data;
	122	UINT8      gb_io[0x10];
	123
	124	/* Timer related */
	125	UINT16      divcount;
	126	UINT8      shift;
	127	UINT16      shift_cycles;
	128	UINT8      triggering_irq;
	129	UINT8      reloading;
	130
	131	/* Serial I/O related */
	132	UINT32      SIOCount;            /* Serial I/O counter */
	133	emu_timer   *gb_serial_timer;
	134
	135	/* SGB variables */
	136	UINT8      sgb_atf_data[4050];      /* (SGB) Attributes files */
	137
	138	/* Cartridge/mapper */
	139	UINT16      MBCType;            /* MBC type: 0 for none */
	140	UINT8      CartType;            /* Cartridge type (battery, ram, rtc, etc) */
	141	UINT8      *ROMMap[MAX_ROMBANK];   /* Addresses of ROM banks */
	142	UINT16      ROMBank;            /* Index of ROM bank currently used at 4000-7fff */
	143	UINT16      ROMBank00;            /* Index of ROM bank currently used at 0000-3fff */
	144	UINT8      ROMMask;            /* Mask for the ROM bank number */
	145	UINT16      ROMBanks;            /* Total number of ROM banks */
	146	UINT8      *RAMMap[MAX_RAMBANK];   /* Addresses of RAM banks */
	147	UINT8      RAMBank;            /* Number of RAM bank currently used */
	148	UINT8      RAMMask;            /* Mask for the RAM bank number */
	149	UINT8      RAMBanks;            /* Total number of RAM banks */
	150	UINT8      MBC1Mode;            /* MBC1 ROM/RAM mode */
	151	UINT8      *MBC3RTCData;         /* MBC3 RTC data */
	152	UINT8      MBC3RTCMap[5];         /* MBC3 RTC banks */
	153	UINT8      MBC3RTCBank;         /* MBC3 RTC bank */
	154	UINT8      *GBC_RAMMap[8];         /* (CGB) Addresses of internal RAM banks */
	155	UINT8      GBC_RAMBank;         /* (CGB) Current CGB RAM bank */
	156	UINT8      gbTama5Memory[32];
	157	UINT8      gbTama5Byte;
	158	UINT8      gbTama5Address;
	159	UINT8      gbLastTama5Command;
	160	UINT8      *gb_cart;
	161	UINT8      *gb_cart_ram;
	162	UINT8      *gb_dummy_rom_bank;
	163	UINT8      *gb_dummy_ram_bank;
	164
	165	UINT8 mmm01_bank_offset;
	166	UINT8 mmm01_reg1;
	167	UINT8 mmm01_bank;
	168	UINT8 mmm01_bank_mask;
	169	gb_lcd_t lcd;
	170	void (*update_scanline)( running_machine *machine );
	171	};
	172
	173
46	174	/*----------- defined in machine/gb.c -----------*/
47	175
48	176	WRITE8_HANDLER( gb_ram_enable );
r9784	r9785
66	194	#define SGB_XOFFSET            48   /* GB screen starts at column 48        */
67	195	#define SGB_YOFFSET            40   /* GB screen starts at row 40           */
68	196
69		extern UINT16 sgb_pal_data[4096];   /* 512 palettes of 4 colours            */
70		extern UINT8 sgb_pal_map[20][18];   /* Palette tile map                     */
71		extern UINT16 sgb_pal[128];         /* SGB palette remapping                */
72		extern UINT8 *sgb_tile_data;      /* 256 tiles of 32 bytes each           */
73		extern UINT8 sgb_tile_map[2048];   /* 32x32 tile map data (0-tile,1-attribute) */
74		extern UINT8 sgb_window_mask;      /* Current GB screen mask               */
75		extern UINT8 sgb_hack;            /* Flag set if we're using a hack       */
76	197
77	198	extern MACHINE_START( sgb );
78	199	extern MACHINE_RESET( sgb );

src/mess/includes/pcw.h

r9784	r9785
57	57	UINT8 printer_p2;  // MCU port P2 state
58	58	UINT8 paper_feed;  // amount of paper fed through printer, by n/360 inches.  One line feed is 61/360in (from the linefeed command in CP/M;s ptr menu)
59	59	bitmap_t* prn_output;
	60	UINT8 printer_p2_prev;
60	61	};
61	62
62	63

src/mess/includes/sapi1.h

r9784	r9785
16	16	UINT8* sapi_video_ram;
17	17	UINT8 keyboard_mask;
18	18	UINT8 refresh_counter;
	19	UINT8 zps3_25;
19	20	};
20	21
21	22

src/mess/drivers/gb.c

r9784	r9785
436	436	***************************************************************************/
437	437
438	438	#include "emu.h"
439		#include "includes/gb.h"
440	439	#include "cpu/lr35902/lr35902.h"
441	440	#include "devices/cartslot.h"
442	441	#include "devices/messram.h"
443	442	#include "rendlay.h"
	443	#include "audio/gb.h"
	444	#include "includes/gb.h"
444	445
445	446
446	447	/* Initial value of the cpu registers (hacks until we get bios dumps) */
r9784	r9785
551	552	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SELECT) PORT_NAME("Select")
552	553	INPUT_PORTS_END
553	554
554		static MACHINE_CONFIG_START( gb_common, driver_device )
	555	static MACHINE_CONFIG_START( gb_common, gb_state )
555	556	/* basic machine hardware */
556	557	MDRV_CPU_ADD("maincpu", LR35902, 4194304)         /* 4.194304 MHz */
557	558	MDRV_CPU_PROGRAM_MAP(gb_map)
r9784	r9785
652	653	MDRV_SOFTWARE_LIST_COMPATIBLE_ADD("gameboy","gameboy")
653	654	MACHINE_CONFIG_END
654	655
655		static MACHINE_CONFIG_START( megaduck, driver_device )
	656	static MACHINE_CONFIG_START( megaduck, gb_state )
656	657	/* basic machine hardware */
657	658	MDRV_CPU_ADD("maincpu", LR35902, 4194304)         /* 4.194304 MHz */
658	659	MDRV_CPU_PROGRAM_MAP( megaduck_map)

src/mess/drivers/tx0.c

r9784	r9785
219	219	pen_typewriter_bg, pen_red      /* red typing in typewriter */
220	220	};
221	221
222		static UINT8 total_colors_needed = pen_crt_num_levels + sizeof(tx0_colors) / 3;
	222	static const UINT8 total_colors_needed = pen_crt_num_levels + sizeof(tx0_colors) / 3;
223	223
224	224	static GFXDECODE_START( tx0 )
225	225	GFXDECODE_ENTRY( "gfx1", 0, fontlayout, pen_crt_num_levels + sizeof(tx0_colors) / 3, 3 )

src/mess/drivers/pcw.c

r9784	r9785
771	771	static WRITE8_HANDLER(mcu_printer_p2_w)
772	772	{
773	773	pcw_state *state = space->machine->driver_data<pcw_state>();
774		static UINT8 prev;
775	774
776	775	//logerror("PRN: MCU writing %02x to P2\n",data);
777	776	state->printer_p2 = data & 0x70;
778	777
779		if((data & 0x40) == 0 && (prev & 0x40) != 0)
	778	if((data & 0x40) == 0 && (state->printer_p2_prev & 0x40) != 0)
780	779	pcw_printer_fire_pins(space->machine,state->printer_pins);
781	780
782	781	// handle shift/store
r9784	r9785
841	840	state->printer_pins |= 0x0100;
842	841	else
843	842	state->printer_pins &= ~0x0100;
844		prev = data;
	843	state->printer_p2_prev = data;
845	844	//popmessage("PRN: P2 bits %s %s %s\nSerial: %02x\nHeadpos: %i",data & 0x40 ? " " : "6",data & 0x20 ? " " : "5",data & 0x10 ? " " : "4",state->printer_shift_output,state->printer_headpos);
846	845	}
847	846

src/mess/drivers/sapi1.c

r9784	r9785
20	20	#include "includes/sapi1.h"
21	21	#include "devices/messram.h"
22	22
23		static UINT8 sapizps3_25;
24	23
25	24	/* switch out the rom shadow */
26	25	static WRITE8_HANDLER( sapizps3_00_w )
r9784	r9785
31	30	/* to stop execution in random ram */
32	31	static READ8_HANDLER( sapizps3_25_r )
33	32	{
34		return sapizps3_25;
	33	sapi1_state *state = space->machine->driver_data<sapi1_state>();
	34	return state->zps3_25;
35	35	}
36	36
37	37	static WRITE8_HANDLER( sapizps3_25_w )
38	38	{
39		sapizps3_25 = data & 0xfc; //??
	39	sapi1_state *state = space->machine->driver_data<sapi1_state>();
	40	state->zps3_25 = data & 0xfc; //??
40	41	}
41	42
42	43

src/mess/drivers/gba.c

r9784	r9785
20	20	#include "cpu/arm7/arm7.h"
21	21	#include "cpu/arm7/arm7core.h"
22	22	#include "devices/cartslot.h"
23		#include "includes/gba.h"
24		#include "includes/gb.h"
25	23	#include "sound/dac.h"
26	24	#include "machine/intelfsh.h"
	25	#include "audio/gb.h"
	26	#include "includes/gba.h"
27	27
28	28	#define VERBOSE_LEVEL   (0)
29	29

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