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r9775 Tuesday 14th December, 2010 at 14:57:58 UTC by Curt Coder
[QL] Microdrive WIP.

[src/mess/devices]	microdrv.c microdrv.h
[src/mess/drivers]	ql.c
[src/mess/includes]	ql.h
[src/mess/machine]	zx8302.c zx8302.h

src/mess/devices/microdrv.c

r9774	r9775
1		/****************************************************************************
	1	/*********************************************************************
2	2
3	3	microdrv.c
4	4
5		Code for handling Microdrive devices
	5	MESS interface to the Sinclair Microdrive image abstraction code
6	6
7		****************************************************************************/
	7	*********************************************************************/
8	8
9	9	#include "emu.h"
10	10	#include "microdrv.h"
11	11
12		static DEVICE_START(microdrv)
	12	/***************************************************************************
	13	CONSTANTS
	14	***************************************************************************/
	15
	16	#define LOG 1
	17
	18	#define MDV_SECTOR_COUNT         255
	19	#define MDV_SECTOR_LENGTH         686
	20	#define MDV_IMAGE_LENGTH         (MDV_SECTOR_COUNT * MDV_SECTOR_LENGTH)
	21
	22	#define MDV_PREAMBLE_LENGTH         12
	23	#define MDV_GAP_LENGTH            120
	24
	25	#define MDV_OFFSET_HEADER_PREAMBLE   0
	26	#define MDV_OFFSET_HEADER         MDV_OFFSET_HEADER_PREAMBLE + MDV_PREAMBLE_LENGTH
	27	#define MDV_OFFSET_DATA_PREAMBLE   28
	28	#define MDV_OFFSET_DATA            MDV_OFFSET_DATA_PREAMBLE + MDV_PREAMBLE_LENGTH
	29	#define MDV_OFFSET_GAP            566
	30
	31	#define MDV_BITRATE               120000 // invalid, from ZX microdrive
	32
	33	/***************************************************************************
	34	TYPE DEFINITIONS
	35	***************************************************************************/
	36
	37	typedef struct _microdrive_t microdrive_t;
	38	struct _microdrive_t
13	39	{
	40	devcb_resolved_write_line out_comms_out_func;
	41
	42	int clk;
	43	int comms_in;
	44	int comms_out;
	45	int erase;
	46	int read_write;
	47
	48	UINT8 *left;
	49	UINT8 *right;
	50
	51	int bit_offset;
	52	int byte_offset;
	53
	54	emu_timer *bit_timer;
	55	};
	56
	57	/***************************************************************************
	58	INLINE HELPERS
	59	***************************************************************************/
	60
	61	INLINE microdrive_t *get_safe_token(running_device *device)
	62	{
	63	assert(device != NULL);
	64	assert(device->type() == MICRODRIVE);
	65	return (microdrive_t *) downcast<legacy_device_base *>(device)->token();
14	66	}
15	67
16		DEVICE_GET_INFO(microdrv)
	68	/***************************************************************************
	69	LIVE DEVICE
	70	***************************************************************************/
	71
	72	static TIMER_CALLBACK( bit_timer_tick )
17	73	{
	74	running_device *device = (running_device *) ptr;
	75	microdrive_t *mdv = get_safe_token(device);
	76
	77	mdv->bit_offset++;
	78
	79	if (mdv->bit_offset == 8)
	80	{
	81	mdv->bit_offset = 0;
	82	mdv->byte_offset++;
	83
	84	if (mdv->byte_offset == MDV_IMAGE_LENGTH)
	85	{
	86	mdv->byte_offset = 0;
	87	}
	88	}
	89	}
	90
	91	WRITE_LINE_DEVICE_HANDLER( microdrive_clk_w )
	92	{
	93	microdrive_t *mdv = get_safe_token(device);
	94
	95	if (LOG) logerror("Microdrive '%s' CLK: %u\n", device->tag(), state);
	96
	97	if (!mdv->clk && state)
	98	{
	99	mdv->comms_out = mdv->comms_in;
	100
	101	if (LOG) logerror("Microdrive '%s' COMMS OUT: %u\n", device->tag(), mdv->comms_out);
	102
	103	devcb_call_write_line(&mdv->out_comms_out_func, mdv->comms_out);
	104
	105	timer_enable(mdv->bit_timer, mdv->comms_out);
	106	}
	107
	108	mdv->clk = state;
	109	}
	110
	111	WRITE_LINE_DEVICE_HANDLER( microdrive_comms_in_w )
	112	{
	113	microdrive_t *mdv = get_safe_token(device);
	114
	115	if (LOG) logerror("Microdrive '%s' COMMS IN: %u\n", device->tag(), state);
	116
	117	mdv->comms_in = state;
	118	}
	119
	120	WRITE_LINE_DEVICE_HANDLER( microdrive_erase_w )
	121	{
	122	microdrive_t *mdv = get_safe_token(device);
	123
	124	if (LOG) logerror("Microdrive '%s' ERASE: %u\n", device->tag(), state);
	125
	126	mdv->erase = state;
	127	}
	128
	129	WRITE_LINE_DEVICE_HANDLER( microdrive_read_write_w )
	130	{
	131	microdrive_t *mdv = get_safe_token(device);
	132
	133	if (LOG) logerror("Microdrive '%s' READ/WRITE: %u\n", device->tag(), state);
	134
	135	mdv->read_write = state;
	136	}
	137
	138	WRITE_LINE_DEVICE_HANDLER( microdrive_data1_w )
	139	{
	140	microdrive_t *mdv = get_safe_token(device);
	141
	142	if (mdv->comms_out && !mdv->read_write)
	143	{
	144	// TODO
	145	}
	146	}
	147
	148	WRITE_LINE_DEVICE_HANDLER( microdrive_data2_w )
	149	{
	150	microdrive_t *mdv = get_safe_token(device);
	151
	152	if (mdv->comms_out && !mdv->read_write)
	153	{
	154	// TODO
	155	}
	156	}
	157
	158	READ_LINE_DEVICE_HANDLER( microdrive_data1_r )
	159	{
	160	microdrive_t *mdv = get_safe_token(device);
	161
	162	int data = 0;
	163
	164	if (mdv->comms_out && mdv->read_write)
	165	{
	166	data = BIT(mdv->left[mdv->byte_offset], 7 - mdv->bit_offset);
	167	}
	168
	169	return data;
	170	}
	171
	172	READ_LINE_DEVICE_HANDLER( microdrive_data2_r )
	173	{
	174	microdrive_t *mdv = get_safe_token(device);
	175
	176	int data = 0;
	177
	178	if (mdv->comms_out && mdv->read_write)
	179	{
	180	data = BIT(mdv->right[mdv->byte_offset], 7 - mdv->bit_offset);
	181	}
	182
	183	return data;
	184	}
	185
	186	/***************************************************************************
	187	DEVICE CONFIGURATION
	188	***************************************************************************/
	189
	190	static DEVICE_START( microdrive )
	191	{
	192	microdrive_t *mdv = get_safe_token(device);
	193	const microdrive_config *config = (const microdrive_config*) device->baseconfig().static_config();
	194
	195	// resolve callbacks
	196	devcb_resolve_write_line(&mdv->out_comms_out_func, &config->out_comms_out_func, device);
	197
	198	// allocate track buffers
	199	mdv->left = auto_alloc_array(device->machine, UINT8, MDV_IMAGE_LENGTH / 2);
	200	mdv->right = auto_alloc_array(device->machine, UINT8, MDV_IMAGE_LENGTH / 2);
	201
	202	// allocate timers
	203	mdv->bit_timer = timer_alloc(device->machine, bit_timer_tick, (void *) device);
	204	timer_adjust_periodic(mdv->bit_timer, attotime_zero, 0, ATTOTIME_IN_HZ(MDV_BITRATE));
	205	timer_enable(mdv->bit_timer, 0);
	206	}
	207
	208	static DEVICE_IMAGE_LOAD( microdrive )
	209	{
	210	device_t *device = &image.device();
	211	microdrive_t *mdv = get_safe_token(device);
	212
	213	if (image.length() != MDV_IMAGE_LENGTH)
	214	return IMAGE_INIT_FAIL;
	215
	216	for (int i = 0; i < MDV_IMAGE_LENGTH / 2; i++)
	217	{
	218	image.fread(mdv->left, 1);
	219	image.fread(mdv->right, 1);
	220	}
	221
	222	mdv->bit_offset = 0;
	223	mdv->byte_offset = 0;
	224
	225	return IMAGE_INIT_PASS;
	226	}
	227
	228	static DEVICE_IMAGE_UNLOAD( microdrive )
	229	{
	230	device_t *device = &image.device();
	231	microdrive_t *mdv = get_safe_token(device);
	232
	233	memset(mdv->left, 0, MDV_IMAGE_LENGTH / 2);
	234	memset(mdv->right, 0, MDV_IMAGE_LENGTH / 2);
	235	}
	236
	237	DEVICE_GET_INFO( microdrive )
	238	{
18	239	switch (state)
19	240	{
20	241	/* --- the following bits of info are returned as 64-bit signed integers --- */
21		case DEVINFO_INT_TOKEN_BYTES:               info->i = 1; break;
	242	case DEVINFO_INT_TOKEN_BYTES:               info->i = sizeof(microdrive_t); break;
22	243	case DEVINFO_INT_INLINE_CONFIG_BYTES:         info->i = 0; break;
23	244	case DEVINFO_INT_IMAGE_TYPE:               info->i = IO_CASSETTE; break;
24	245	case DEVINFO_INT_IMAGE_READABLE:            info->i = 1; break;
r9774	r9775
26	247	case DEVINFO_INT_IMAGE_CREATABLE:            info->i = 0; break;
27	248
28	249	/* --- the following bits of info are returned as pointers to data or functions --- */
29		case DEVINFO_FCT_START:                     info->start = DEVICE_START_NAME(microdrv); break;
	250	case DEVINFO_FCT_START:                     info->start = DEVICE_START_NAME(microdrive); break;
	251	case DEVINFO_FCT_IMAGE_LOAD:               info->f = (genf *) DEVICE_IMAGE_LOAD_NAME(microdrive); break;
	252	case DEVINFO_FCT_IMAGE_UNLOAD:               info->f = (genf *) DEVICE_IMAGE_UNLOAD_NAME(microdrive); break;
30	253
31	254	/* --- the following bits of info are returned as NULL-terminated strings --- */
32	255	case DEVINFO_STR_NAME:                     strcpy(info->s, "Microdrive"); break;
r9774	r9775
36	259	}
37	260	}
38	261
39		DEFINE_LEGACY_IMAGE_DEVICE(MICRODRIVE, microdrv);
	262	DEFINE_LEGACY_IMAGE_DEVICE(MICRODRIVE, microdrive);

src/mess/devices/microdrv.h

r9774	r9775
	1	/*********************************************************************
	2
	3	microdrv.h
	4
	5	MESS interface to the Sinclair Microdrive image abstraction code
	6
	7	*********************************************************************/
	8
	9	#pragma once
	10
1	11	#ifndef __MICRODRV__
2	12	#define __MICRODRV__
3	13
4		#define MDV_SECTOR_COUNT   255
5		#define MDV_SECTOR_LENGTH   686
6		#define MDV_IMAGE_LENGTH   (MDV_SECTOR_COUNT * MDV_SECTOR_LENGTH)
	14	/***************************************************************************
	15	TYPE DEFINITIONS
	16	***************************************************************************/
	17	typedef struct microdrive_config_t   microdrive_config;
	18	struct microdrive_config_t
	19	{
	20	devcb_write_line   out_comms_out_func;
	21	};
7	22
8		#define MDV_PREAMBLE_LENGTH         12
9		#define MDV_GAP_LENGTH            120
	23	/***************************************************************************
	24	FUNCTION PROTOTYPES
	25	***************************************************************************/
10	26
11		#define MDV_OFFSET_HEADER_PREAMBLE   0
12		#define MDV_OFFSET_HEADER         MDV_OFFSET_HEADER_PREAMBLE + MDV_PREAMBLE_LENGTH
13		#define MDV_OFFSET_DATA_PREAMBLE   28
14		#define MDV_OFFSET_DATA            MDV_OFFSET_DATA_PREAMBLE + MDV_PREAMBLE_LENGTH
15		#define MDV_OFFSET_GAP            566
	27	WRITE_LINE_DEVICE_HANDLER( microdrive_clk_w );
	28	WRITE_LINE_DEVICE_HANDLER( microdrive_comms_in_w );
	29	WRITE_LINE_DEVICE_HANDLER( microdrive_erase_w );
	30	WRITE_LINE_DEVICE_HANDLER( microdrive_read_write_w );
	31	WRITE_LINE_DEVICE_HANDLER( microdrive_data1_w );
	32	WRITE_LINE_DEVICE_HANDLER( microdrive_data2_w );
	33	READ_LINE_DEVICE_HANDLER( microdrive_data1_r );
	34	READ_LINE_DEVICE_HANDLER( microdrive_data2_r );
16	35
17		DECLARE_LEGACY_IMAGE_DEVICE(MICRODRIVE, microdrv);
	36	DECLARE_LEGACY_IMAGE_DEVICE(MICRODRIVE, microdrive);
18	37
	38	/***************************************************************************
	39	DEVICE CONFIGURATION MACROS
	40	***************************************************************************/
	41
	42	#define MDV_1 "mdv1"
	43	#define MDV_2 "mdv2"
	44
	45	#define MDRV_MICRODRIVE_ADD(_tag, _config) \
	46	MDRV_DEVICE_ADD(_tag, MICRODRIVE, 0) \
	47	MDRV_DEVICE_CONFIG(_config)
	48
	49	#define MICRODRIVE_CONFIG(_name) \
	50	const microdrive_config (_name) =
	51
19	52	#endif

src/mess/machine/zx8302.c

r9774	r9775
129	129	memset(&in_cts2_func, 0, sizeof(in_cts2_func));
130	130	memset(&out_netout_func, 0, sizeof(out_netout_func));
131	131	memset(&in_netin_func, 0, sizeof(in_netin_func));
	132	memset(&out_mdselck_func, 0, sizeof(out_mdselck_func));
	133	memset(&out_mdseld_func, 0, sizeof(out_mdseld_func));
	134	memset(&out_mdrdw_func, 0, sizeof(out_mdrdw_func));
	135	memset(&out_erase_func, 0, sizeof(out_erase_func));
	136	memset(&out_raw1_func, 0, sizeof(out_raw1_func));
	137	memset(&in_raw1_func, 0, sizeof(in_raw1_func));
	138	memset(&out_raw2_func, 0, sizeof(out_raw2_func));
	139	memset(&in_raw2_func, 0, sizeof(in_raw2_func));
132	140	}
133	141	}
134	142
r9774	r9775
319	327	devcb_resolve_read_line(&m_in_cts2_func, &m_config.in_cts2_func, this);
320	328	devcb_resolve_write_line(&m_out_netout_func, &m_config.out_netout_func, this);
321	329	devcb_resolve_read_line(&m_in_netin_func, &m_config.in_netin_func, this);
	330	devcb_resolve_write_line(&m_out_mdselck_func, &m_config.out_mdselck_func, this);
	331	devcb_resolve_write_line(&m_out_mdseld_func, &m_config.out_mdseld_func, this);
	332	devcb_resolve_write_line(&m_out_mdrdw_func, &m_config.out_mdrdw_func, this);
	333	devcb_resolve_write_line(&m_out_erase_func, &m_config.out_erase_func, this);
	334	devcb_resolve_write_line(&m_out_raw1_func, &m_config.out_raw1_func, this);
	335	devcb_resolve_read_line(&m_in_raw1_func, &m_config.in_raw1_func, this);
	336	devcb_resolve_write_line(&m_out_raw2_func, &m_config.out_raw2_func, this);
	337	devcb_resolve_read_line(&m_in_raw2_func, &m_config.in_raw2_func, this);
322	338
323	339	// allocate timers
324	340	m_txd_timer = device_timer_alloc(*this, TIMER_TXD);
r9774	r9775
344	360	state_save_register_device_item(this, 0, m_ipc_busy);
345	361	state_save_register_device_item(this, 0, m_baudx4);
346	362	state_save_register_device_item(this, 0, m_tx_bits);
347		state_save_register_device_item(this, 0, m_mdrdw);
348		state_save_register_device_item(this, 0, m_mdselck);
349		state_save_register_device_item(this, 0, m_mdseld);
350		state_save_register_device_item(this, 0, m_erase);
351		state_save_register_device_item(this, 0, m_mdv_motor);
352	363	state_save_register_device_item_array(this, 0, m_mdv_data);
353	364	state_save_register_device_item(this, 0, m_track);
354	365	}
r9774	r9775
376	387	break;
377	388
378	389	case TIMER_GAP:
379		if (m_mdv_motor)
380		{
381		trigger_interrupt(INT_GAP);
382		}
	390	trigger_interrupt(INT_GAP);
383	391	break;
384	392
385	393	case TIMER_IPC:
r9774	r9775
547	555
548	556	if (LOG) logerror("ZX8302 '%s' Microdrive Control: %02x\n", tag(), data);
549	557
550		m_mdseld = BIT(data, 0);
551		m_mdselck = BIT(data, 1);
552		m_mdrdw = BIT(data, 2) ? 0 : 1;
553		m_erase = BIT(data, 3);
	558	devcb_call_write_line(&m_out_mdseld_func, BIT(data, 0));
	559	devcb_call_write_line(&m_out_mdselck_func, BIT(data, 1));
	560	devcb_call_write_line(&m_out_mdrdw_func, BIT(data, 2));
	561	devcb_call_write_line(&m_out_erase_func, BIT(data, 3));
554	562
555		// Microdrive selection shift register
556		if (m_mdselck)
	563	if (BIT(data, 1))
557	564	{
558		m_mdv_motor >>= 1;
559		m_mdv_motor |= (m_mdseld << 7);
560
561	565	m_status &= ~STATUS_RX_BUFFER_FULL;
562	566	}
563	567	}

src/mess/machine/zx8302.h

r9774	r9775
14	14	BAUDX4   5 |             | 36  DB1
15	15	DTR1L   6 |             | 35  COMDATA
16	16	CTS2L   7 |             | 34  MDSELDH
17		DCSML   8 |             | 33  MDSELCKH
	17	DCSML   8 |             | 33  MDSELCKN
18	18	ROWL   9 |             | 32  VSYNCH
19	19	PCENL  10 |    ZX8302   | 31  XTAL2
20	20	Vdd  11 |     ULA     | 30  XTAL1
r9774	r9775
69	69	{
70	70	int rtc_clock;            // the RTC clock (pin 30) of the chip
71	71
	72	// serial
72	73	devcb_write_line   out_ipl1l_func;
73	74	devcb_write_line   out_baudx4_func;
74	75	devcb_write_line   out_comdata_func;
r9774	r9775
78	79	devcb_read_line      in_cts2_func;
79	80	devcb_write_line   out_netout_func;
80	81	devcb_read_line      in_netin_func;
	82
	83	// microdrive
	84	devcb_write_line   out_mdselck_func;
	85	devcb_write_line   out_mdseld_func;
	86	devcb_write_line   out_mdrdw_func;
	87	devcb_write_line   out_erase_func;
	88	devcb_write_line   out_raw1_func;
	89	devcb_read_line      in_raw1_func;
	90	devcb_write_line   out_raw2_func;
	91	devcb_read_line      in_raw2_func;
81	92	};
82	93
83	94
r9774	r9775
154	165	devcb_resolved_write_line   m_out_netout_func;
155	166	devcb_resolved_read_line   m_in_netin_func;
156	167
	168	devcb_resolved_write_line   m_out_mdselck_func;
	169	devcb_resolved_write_line   m_out_mdseld_func;
	170	devcb_resolved_write_line   m_out_mdrdw_func;
	171	devcb_resolved_write_line   m_out_erase_func;
	172	devcb_resolved_write_line   m_out_raw1_func;
	173	devcb_resolved_read_line   m_in_raw1_func;
	174	devcb_resolved_write_line   m_out_raw2_func;
	175	devcb_resolved_read_line   m_in_raw2_func;
	176
157	177	// registers
158	178	UINT8 m_idr;               // IPC data register
159	179	UINT8 m_tcr;               // transfer control register
r9774	r9775
174	194	int m_tx_bits;               // bits transmitted
175	195
176	196	// microdrive state
177		int m_mdrdw;               // read/write
178		int m_mdselck;               // select clock
179		int m_mdseld;               // select data
180		int m_erase;               // erase head
181		int m_mdv_motor;            // selected motor
182	197	UINT8 m_mdv_data[2];         // track data register
183	198	int m_track;               // current track
184	199

src/mess/includes/ql.h

r9774	r9775
	1	#pragma once
	2
1	3	#ifndef __QL__
2	4	#define __QL__
3	5
r9774	r9775
10	12	#define ZX8302_TAG   "ic23"
11	13	#define SPEAKER_TAG   "speaker"
12	14
13		#define MDV1_TAG   "mdv1"
14		#define MDV2_TAG   "mdv2"
15
16	15	#define X1 XTAL_15MHz
17	16	#define X2 XTAL_32_768kHz
18	17	#define X3 XTAL_4_436MHz
r9774	r9775
29	28	m_zx8301(*this, ZX8301_TAG),
30	29	m_zx8302(*this, ZX8302_TAG),
31	30	m_speaker(*this, SPEAKER_TAG),
	31	m_mdv1(*this, MDV_1),
	32	m_mdv2(*this, MDV_2),
32	33	m_ram(*this, "messram")
33	34	{ }
34	35
r9774	r9775
37	38	required_device<zx8301_device> m_zx8301;
38	39	required_device<zx8302_device> m_zx8302;
39	40	required_device<running_device> m_speaker;
	41	required_device<running_device> m_mdv1;
	42	required_device<running_device> m_mdv2;
40	43	required_device<running_device> m_ram;
41	44
42	45	virtual void machine_start();
r9774	r9775
53	56	DECLARE_WRITE8_MEMBER( ql_ram_w );
54	57	DECLARE_WRITE_LINE_MEMBER( ql_baudx4_w );
55	58	DECLARE_WRITE_LINE_MEMBER( ql_comdata_w );
	59	DECLARE_WRITE_LINE_MEMBER( zx8302_mdselck_w );
	60	DECLARE_WRITE_LINE_MEMBER( zx8302_mdrdw_w );
	61	DECLARE_WRITE_LINE_MEMBER( zx8302_erase_w );
	62	DECLARE_WRITE_LINE_MEMBER( zx8302_raw1_w );
	63	DECLARE_READ_LINE_MEMBER( zx8302_raw1_r );
	64	DECLARE_WRITE_LINE_MEMBER( zx8302_raw2_w );
	65	DECLARE_READ_LINE_MEMBER( zx8302_raw2_r );
56	66
57	67	/* IPC state */
58	68	UINT8 m_keylatch;
59		int m_ser1_txd;
60		int m_ser1_dtr;
61		int m_ser2_rxd;
62		int m_ser2_cts;
63	69	int m_ipl;
64	70	int m_comdata;
65	71	int m_baudx4;

src/mess/drivers/ql.c

r9774	r9775
10	10
11	11	TODO:
12	12
	13	- microdrive
	14	- ZX8301 memory access slowdown
13	15	- use resnet.h to create palette
14	16	- Tyche bios is broken
15	17	- several disk interfaces (720K/1.44MB/3.2MB)
16		- discrete sound
17	18	- Gold Card (68000 @ 16MHz, 2MB RAM)
18	19	- Super Gold Card (68020 @ 24MHz, 4MB RAM)
19	20	- QLToolkit II ROM
r9774	r9775
54	55	#include "video/zx8301.h"
55	56	#include "includes/ql.h"
56	57
57		/* Intelligent Peripheral Controller (IPC) */
58	58
	59
	60
	61	//**************************************************************************
	62	//   INTELLIGENT PERIPHERAL CONTROLLER
	63	//**************************************************************************
	64
	65	//-------------------------------------------------
	66	//  ipc_w -
	67	//-------------------------------------------------
	68
59	69	WRITE8_MEMBER( ql_state::ipc_w )
60	70	{
61	71	m_zx8302->comctl_w(0);
62	72	m_zx8302->comctl_w(1);
63	73	}
64	74
	75
	76	//-------------------------------------------------
	77	//  ipc_port1_w -
	78	//-------------------------------------------------
	79
65	80	WRITE8_MEMBER( ql_state::ipc_port1_w )
66	81	{
67	82	/*
r9774	r9775
82	97	m_keylatch = data;
83	98	}
84	99
	100
	101	//-------------------------------------------------
	102	//  ipc_port2_w -
	103	//-------------------------------------------------
	104
85	105	WRITE8_MEMBER( ql_state::ipc_port2_w )
86	106	{
87	107	/*
r9774	r9775
92	112	1       Speaker output
93	113	2       Interrupt output (IPL0-2)
94	114	3       Interrupt output (IPL1)
95		4       Serial Clear-to-Send output (SER2 CTS)
96		5       Serial Data Terminal Ready output (SER1 DTR)
	115	4       Serial Clear-to-Send output (SER1 CTS)
	116	5       Serial Data Terminal Ready output (SER2 DTR)
97	117	6       not connected
98	118	7       ZX8302 serial link input/output (COMDATA)
99	119
100	120	*/
101	121
	122	// speaker
	123	speaker_level_w(m_speaker, BIT(data, 1));
	124
	125	// interrupts
102	126	int ipl = (BIT(data, 2) << 1) | BIT(data, 3);
103	127
104	128	if (ipl != m_ipl)
105	129	{
106	130	switch (ipl)
107	131	{
108		case 0:
109		cpu_set_input_line(m_maincpu, M68K_IRQ_7, ASSERT_LINE);
110		break;
111
112		case 1:
113		// CTRL-ALT-7 pressed
114		cpu_set_input_line(m_maincpu, M68K_IRQ_5, ASSERT_LINE);
115		break;
116
117		case 2:
118		cpu_set_input_line(m_maincpu, M68K_IRQ_2, ASSERT_LINE);
119		break;
120
121		case 3:
122		cpu_set_input_line(m_maincpu, M68K_IRQ_7, CLEAR_LINE);
123		break;
	132	case 0:   cpu_set_input_line(m_maincpu, M68K_IRQ_7, ASSERT_LINE);   break;
	133	case 1:   cpu_set_input_line(m_maincpu, M68K_IRQ_5, ASSERT_LINE);   break; // CTRL-ALT-7 pressed
	134	case 2:   cpu_set_input_line(m_maincpu, M68K_IRQ_2, ASSERT_LINE);   break;
	135	case 3:   cpu_set_input_line(m_maincpu, M68K_IRQ_7, CLEAR_LINE);   break;
124	136	}
125	137
126	138	m_ipl = ipl;
127	139	}
128	140
129		speaker_level_w(m_speaker, BIT(data, 1));
	141	// clear to send
	142	//rs232_cts_w(m_ser1, !BIT(data, 4));
130	143
131		m_ser2_cts = BIT(data, 4);
132		m_ser1_dtr = BIT(data, 5);
	144	// data terminal ready
	145	//rs232_dtr_w(m_ser2, !BIT(data, 5));
133	146
	147	// COMDATA
134	148	m_comdata = BIT(data, 7);
135	149
136	150	m_zx8302->comdata_w(BIT(data, 7));
137	151	}
138	152
	153
	154	//-------------------------------------------------
	155	//  ipc_port2_r -
	156	//-------------------------------------------------
	157
139	158	READ8_MEMBER( ql_state::ipc_port2_r )
140	159	{
141	160	/*
r9774	r9775
153	172
154	173	*/
155	174
156		int irq = (m_ser2_rxd | m_ser1_txd);
	175	//   int irq = (m_ser2_rxd | m_ser1_txd);
157	176
158		cpu_set_input_line(m_ipc, INPUT_LINE_IRQ0, irq);
	177	//   cpu_set_input_line(m_ipc, INPUT_LINE_IRQ0, irq);
159	178
160		return (m_comdata << 7) | irq;
	179	return (m_comdata << 7);
161	180	}
162	181
	182
	183	//-------------------------------------------------
	184	//  ipc_t1_r -
	185	//-------------------------------------------------
	186
163	187	READ8_MEMBER( ql_state::ipc_t1_r )
164	188	{
165	189	return m_baudx4;
166	190	}
167	191
	192
	193	//-------------------------------------------------
	194	//  ipc_bus_r -
	195	//-------------------------------------------------
	196
168	197	READ8_MEMBER( ql_state::ipc_bus_r )
169	198	{
170	199	/*
r9774	r9775
196	225	return data;
197	226	}
198	227
199		/* Memory Maps */
200	228
201		static ADDRESS_MAP_START( ql_map, ADDRESS_SPACE_PROGRAM, 8, ql_state )
	229
	230	//**************************************************************************
	231	//   ADDRESS MAPS
	232	//**************************************************************************
	233
	234	//-------------------------------------------------
	235	//  ADDRESS_MAP( ql_mem )
	236	//-------------------------------------------------
	237
	238	static ADDRESS_MAP_START( ql_mem, ADDRESS_SPACE_PROGRAM, 8, ql_state )
202	239	AM_RANGE(0x000000, 0x00bfff) AM_ROM   // 48K System ROM
203	240	AM_RANGE(0x00c000, 0x00ffff) AM_ROM // 16K Cartridge ROM
204	241	AM_RANGE(0x010000, 0x017fff) AM_UNMAP // 32K Expansion I/O
r9774	r9775
216	253	AM_RANGE(0x040000, 0x0fffff) AM_RAM
217	254	ADDRESS_MAP_END
218	255
219		static ADDRESS_MAP_START( ipc_io_map, ADDRESS_SPACE_IO, 8, ql_state )
	256
	257	//-------------------------------------------------
	258	//  ADDRESS_MAP( ipc_io )
	259	//-------------------------------------------------
	260
	261	static ADDRESS_MAP_START( ipc_io, ADDRESS_SPACE_IO, 8, ql_state )
220	262	AM_RANGE(0x00, 0x7f) AM_WRITE(ipc_w)
221	263	AM_RANGE(0x27, 0x28) AM_READNOP // IPC reads these to set P0 (bus) to Hi-Z mode
222	264	AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_WRITE(ipc_port1_w)
r9774	r9775
225	267	AM_RANGE(MCS48_PORT_BUS, MCS48_PORT_BUS) AM_READ(ipc_bus_r) AM_WRITENOP
226	268	ADDRESS_MAP_END
227	269
228		/* Input Ports */
229	270
	271
	272	//**************************************************************************
	273	//   INPUT PORTS
	274	//**************************************************************************
	275
	276	//-------------------------------------------------
	277	//  INPUT_PORTS( ql )
	278	//-------------------------------------------------
	279
230	280	static INPUT_PORTS_START( ql )
231	281	PORT_START("ROW0")
232	282	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F4) PORT_CHAR(UCHAR_MAMEKEY(F4)) PORT_NAME("F4")
r9774	r9775
329	379	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )   PORT_PLAYER(2) PORT_8WAY PORT_CODE(KEYCODE_DOWN)
330	380	INPUT_PORTS_END
331	381
	382
	383	//-------------------------------------------------
	384	//  INPUT_PORTS( ql_es )
	385	//-------------------------------------------------
	386
332	387	static INPUT_PORTS_START( ql_es )
333	388	PORT_INCLUDE(ql)
334	389
r9774	r9775
357	412	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('?')
358	413	INPUT_PORTS_END
359	414
	415
	416	//-------------------------------------------------
	417	//  INPUT_PORTS( ql_de )
	418	//-------------------------------------------------
	419
360	420	static INPUT_PORTS_START( ql_de )
361	421	PORT_INCLUDE(ql)
362	422
r9774	r9775
397	457	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR(';')
398	458	INPUT_PORTS_END
399	459
	460
	461	//-------------------------------------------------
	462	//  INPUT_PORTS( ql_it )
	463	//-------------------------------------------------
	464
400	465	static INPUT_PORTS_START( ql_it )
401	466	PORT_INCLUDE(ql)
402	467
r9774	r9775
441	506	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('.')
442	507	INPUT_PORTS_END
443	508
	509
	510	//-------------------------------------------------
	511	//  INPUT_PORTS( ql_fr )
	512	//-------------------------------------------------
	513
444	514	static INPUT_PORTS_START( ql_fr )
445	515	PORT_INCLUDE(ql)
446	516	INPUT_PORTS_END
447	517
	518
	519	//-------------------------------------------------
	520	//  INPUT_PORTS( ql_se )
	521	//-------------------------------------------------
	522
448	523	static INPUT_PORTS_START( ql_se )
449	524	PORT_INCLUDE(ql)
450	525	INPUT_PORTS_END
451	526
	527
	528	//-------------------------------------------------
	529	//  INPUT_PORTS( ql_dk )
	530	//-------------------------------------------------
	531
452	532	static INPUT_PORTS_START( ql_dk )
453	533	PORT_INCLUDE(ql)
454	534	INPUT_PORTS_END
455	535
456		/* ZX8301 Interface */
457	536
	537
	538	//**************************************************************************
	539	//   VIDEO
	540	//**************************************************************************
	541
	542	//-------------------------------------------------
	543	//  PALETTE_INIT( ql )
	544	//-------------------------------------------------
	545
	546	static PALETTE_INIT( ql )
	547	{
	548	palette_set_color_rgb(machine, 0, 0x00, 0x00, 0x00 ); // black
	549	palette_set_color_rgb(machine, 1, 0x00, 0x00, 0xff ); // blue
	550	palette_set_color_rgb(machine, 2, 0xff, 0x00, 0x00 ); // red
	551	palette_set_color_rgb(machine, 3, 0xff, 0x00, 0xff ); // magenta
	552	palette_set_color_rgb(machine, 4, 0x00, 0xff, 0x00 ); // green
	553	palette_set_color_rgb(machine, 5, 0x00, 0xff, 0xff ); // cyan
	554	palette_set_color_rgb(machine, 6, 0xff, 0xff, 0x00 ); // yellow
	555	palette_set_color_rgb(machine, 7, 0xff, 0xff, 0xff ); // white
	556	}
	557
	558
	559	//-------------------------------------------------
	560	//  VIDEO_UPDATE( ql )
	561	//-------------------------------------------------
	562
	563	bool ql_state::video_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect)
	564	{
	565	m_zx8301->update_screen(&bitmap, &cliprect);
	566
	567	return 0;
	568	}
	569
	570
	571
	572	//**************************************************************************
	573	//   DEVICE CONFIGURATION
	574	//**************************************************************************
	575
	576	//-------------------------------------------------
	577	//  ZX8301_INTERFACE( ql_zx8301_intf )
	578	//-------------------------------------------------
	579
458	580	static ZX8301_INTERFACE( ql_zx8301_intf )
459	581	{
460	582	M68008_TAG,
r9774	r9775
462	584	DEVCB_DEVICE_LINE_MEMBER(ZX8302_TAG, zx8302_device, vsync_w)
463	585	};
464	586
465		/* ZX8302 Interface */
466	587
	588	//-------------------------------------------------
	589	//  ZX8302_INTERFACE( ql_zx8302_intf )
	590	//-------------------------------------------------
	591
467	592	WRITE_LINE_MEMBER( ql_state::ql_baudx4_w )
468	593	{
469	594	m_baudx4 = state;
r9774	r9775
474	599	m_comdata = state;
475	600	}
476	601
477		static ZX8302_INTERFACE( ql_zx8302_intf )
	602	WRITE_LINE_MEMBER( ql_state::zx8302_mdselck_w )
478	603	{
479		X2,
480		DEVCB_CPU_INPUT_LINE(M68008_TAG, M68K_IRQ_2),
481		DEVCB_DRIVER_LINE_MEMBER(ql_state, ql_baudx4_w),
482		DEVCB_DRIVER_LINE_MEMBER(ql_state, ql_comdata_w),
483		DEVCB_NULL,
484		DEVCB_NULL,
485		DEVCB_NULL,
486		DEVCB_NULL,
487		DEVCB_NULL,
488		DEVCB_NULL
489		};
	604	microdrive_clk_w(m_mdv2, state);
	605	microdrive_clk_w(m_mdv1, state);
	606	}
490	607
491		static PALETTE_INIT( ql )
	608	WRITE_LINE_MEMBER( ql_state::zx8302_mdrdw_w )
492	609	{
493		palette_set_color_rgb(machine, 0, 0x00, 0x00, 0x00 ); // black
494		palette_set_color_rgb(machine, 1, 0x00, 0x00, 0xff ); // blue
495		palette_set_color_rgb(machine, 2, 0xff, 0x00, 0x00 ); // red
496		palette_set_color_rgb(machine, 3, 0xff, 0x00, 0xff ); // magenta
497		palette_set_color_rgb(machine, 4, 0x00, 0xff, 0x00 ); // green
498		palette_set_color_rgb(machine, 5, 0x00, 0xff, 0xff ); // cyan
499		palette_set_color_rgb(machine, 6, 0xff, 0xff, 0x00 ); // yellow
500		palette_set_color_rgb(machine, 7, 0xff, 0xff, 0xff ); // white
	610	microdrive_read_write_w(m_mdv1, state);
	611	microdrive_read_write_w(m_mdv2, state);
501	612	}
502	613
503		bool ql_state::video_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect)
	614	WRITE_LINE_MEMBER( ql_state::zx8302_erase_w )
504	615	{
505		m_zx8301->update_screen(&bitmap, &cliprect);
	616	microdrive_erase_w(m_mdv1, state);
	617	microdrive_erase_w(m_mdv2, state);
	618	}
506	619
507		return 0;
	620	WRITE_LINE_MEMBER( ql_state::zx8302_raw1_w )
	621	{
	622	microdrive_data1_w(m_mdv1, state);
	623	microdrive_data1_w(m_mdv2, state);
508	624	}
509	625
510		/* Machine Drivers */
	626	READ_LINE_MEMBER( ql_state::zx8302_raw1_r )
	627	{
	628	return microdrive_data1_r(m_mdv1) | microdrive_data1_r(m_mdv2);
	629	}
511	630
512		void ql_state::machine_start()
	631	WRITE_LINE_MEMBER( ql_state::zx8302_raw2_w )
513	632	{
514		address_space *program = cpu_get_address_space(m_maincpu, ADDRESS_SPACE_PROGRAM);
	633	microdrive_data2_w(m_mdv1, state);
	634	microdrive_data2_w(m_mdv2, state);
	635	}
515	636
516		// configure RAM
517		switch (messram_get_size(m_ram))
518		{
519		case 128*1024:
520		memory_unmap_readwrite(program, 0x040000, 0x0fffff, 0, 0);
521		break;
	637	READ_LINE_MEMBER( ql_state::zx8302_raw2_r )
	638	{
	639	return microdrive_data2_r(m_mdv1) | microdrive_data2_r(m_mdv2);
	640	}
522	641
523		case 192*1024:
524		memory_unmap_readwrite(program, 0x050000, 0x0fffff, 0, 0);
525		break;
	642	static ZX8302_INTERFACE( ql_zx8302_intf )
	643	{
	644	X2,
	645	DEVCB_CPU_INPUT_LINE(M68008_TAG, M68K_IRQ_2),
	646	DEVCB_DRIVER_LINE_MEMBER(ql_state, ql_baudx4_w),
	647	DEVCB_DRIVER_LINE_MEMBER(ql_state, ql_comdata_w),
	648	DEVCB_NULL, // TXD1
	649	DEVCB_NULL, // TXD2
	650	DEVCB_NULL, // DTR1
	651	DEVCB_NULL, // CTS2
	652	DEVCB_NULL, // NETOUT
	653	DEVCB_NULL, // NETIN
	654	DEVCB_DRIVER_LINE_MEMBER(ql_state, zx8302_mdselck_w),
	655	DEVCB_DEVICE_LINE(MDV_1, microdrive_comms_in_w),
	656	DEVCB_DRIVER_LINE_MEMBER(ql_state, zx8302_mdrdw_w),
	657	DEVCB_DRIVER_LINE_MEMBER(ql_state, zx8302_erase_w),
	658	DEVCB_DRIVER_LINE_MEMBER(ql_state, zx8302_raw1_w),
	659	DEVCB_DRIVER_LINE_MEMBER(ql_state, zx8302_raw1_r),
	660	DEVCB_DRIVER_LINE_MEMBER(ql_state, zx8302_raw2_w),
	661	DEVCB_DRIVER_LINE_MEMBER(ql_state, zx8302_raw2_r)
	662	};
526	663
527		case 256*1024:
528		memory_unmap_readwrite(program, 0x060000, 0x0fffff, 0, 0);
529		break;
530	664
531		case 384*1024:
532		memory_unmap_readwrite(program, 0x080000, 0x0fffff, 0, 0);
533		break;
	665	//-------------------------------------------------
	666	//  floppy_config ql_floppy_config
	667	//-------------------------------------------------
534	668
535		case 640*1024:
536		memory_unmap_readwrite(program, 0x0c0000, 0x0fffff, 0, 0);
537		break;
538		}
539
540		// register for state saving
541		state_save_register_global(machine, m_keylatch);
542		state_save_register_global(machine, m_ser1_txd);
543		state_save_register_global(machine, m_ser1_dtr);
544		state_save_register_global(machine, m_ser2_rxd);
545		state_save_register_global(machine, m_ser2_cts);
546		state_save_register_global(machine, m_ipl);
547		state_save_register_global(machine, m_comdata);
548		state_save_register_global(machine, m_baudx4);
549		}
550
551	669	static FLOPPY_OPTIONS_START( ql )
552	670	FLOPPY_OPTION(ql, "dsk", "SSSD disk image", basicdsk_identify_default, basicdsk_construct_default,
553	671	HEADS([1])
r9774	r9775
593	711	NULL
594	712	};
595	713
	714
	715	//-------------------------------------------------
	716	//  MICRODRIVE_CONFIG( mdv1_config )
	717	//-------------------------------------------------
	718
	719	static MICRODRIVE_CONFIG( mdv1_config )
	720	{
	721	DEVCB_DEVICE_LINE(MDV_2, microdrive_comms_in_w)
	722	};
	723
	724
	725	//-------------------------------------------------
	726	//  MICRODRIVE_CONFIG( mdv2_config )
	727	//-------------------------------------------------
	728
	729	static MICRODRIVE_CONFIG( mdv2_config )
	730	{
	731	DEVCB_NULL
	732	};
	733
	734
	735
	736	//**************************************************************************
	737	//   MACHINE INITIALIZATION
	738	//**************************************************************************
	739
	740	//-------------------------------------------------
	741	//  MACHINE_START( ql )
	742	//-------------------------------------------------
	743
	744	void ql_state::machine_start()
	745	{
	746	address_space *program = cpu_get_address_space(m_maincpu, ADDRESS_SPACE_PROGRAM);
	747
	748	// configure RAM
	749	switch (messram_get_size(m_ram))
	750	{
	751	case 128*1024:
	752	memory_unmap_readwrite(program, 0x040000, 0x0fffff, 0, 0);
	753	break;
	754
	755	case 192*1024:
	756	memory_unmap_readwrite(program, 0x050000, 0x0fffff, 0, 0);
	757	break;
	758
	759	case 256*1024:
	760	memory_unmap_readwrite(program, 0x060000, 0x0fffff, 0, 0);
	761	break;
	762
	763	case 384*1024:
	764	memory_unmap_readwrite(program, 0x080000, 0x0fffff, 0, 0);
	765	break;
	766
	767	case 640*1024:
	768	memory_unmap_readwrite(program, 0x0c0000, 0x0fffff, 0, 0);
	769	break;
	770	}
	771
	772	// register for state saving
	773	state_save_register_global(machine, m_keylatch);
	774	state_save_register_global(machine, m_ipl);
	775	state_save_register_global(machine, m_comdata);
	776	state_save_register_global(machine, m_baudx4);
	777	}
	778
	779
	780
	781	//**************************************************************************
	782	//   MACHINE CONFIGURATION
	783	//**************************************************************************
	784
	785	//-------------------------------------------------
	786	//  MACHINE_CONFIG( ql )
	787	//-------------------------------------------------
	788
596	789	static MACHINE_CONFIG_START( ql, ql_state )
597	790	// basic machine hardware
598	791	MDRV_CPU_ADD(M68008_TAG, M68008, X1/2)
599		MDRV_CPU_PROGRAM_MAP(ql_map)
	792	MDRV_CPU_PROGRAM_MAP(ql_mem)
600	793
601	794	MDRV_CPU_ADD(I8749_TAG, I8749, X4)
602		MDRV_CPU_IO_MAP(ipc_io_map)
	795	MDRV_CPU_IO_MAP(ipc_io)
603	796
604		MDRV_ZX8302_ADD(ZX8302_TAG, X1, ql_zx8302_intf)
605
606		MDRV_DEVICE_ADD(MDV1_TAG, MICRODRIVE, 0)
607		MDRV_DEVICE_ADD(MDV2_TAG, MICRODRIVE, 0)
608
609	797	// video hardware
610	798	MDRV_SCREEN_ADD(SCREEN_TAG, RASTER)
611	799	MDRV_SCREEN_REFRESH_RATE(50.08)
612		MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
	800	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) // not accurate
613	801	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
614	802	MDRV_SCREEN_SIZE(960, 312)
615	803	MDRV_SCREEN_VISIBLE_AREA(0, 512-1, 0, 256-1)
r9774	r9775
617	805	MDRV_PALETTE_LENGTH(8)
618	806	MDRV_PALETTE_INIT(ql)
619	807
620		MDRV_ZX8301_ADD(ZX8301_TAG, X1, ql_zx8301_intf)
621
622	808	// sound hardware
623	809	MDRV_SPEAKER_STANDARD_MONO("mono")
624	810	MDRV_SOUND_ADD("speaker", SPEAKER_SOUND, 0)
625	811	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
626	812
627		/* cartridge */
	813	// devices
	814	MDRV_ZX8301_ADD(ZX8301_TAG, X1, ql_zx8301_intf)
	815	MDRV_ZX8302_ADD(ZX8302_TAG, X1, ql_zx8302_intf)
	816
	817	MDRV_FLOPPY_2_DRIVES_ADD(ql_floppy_config)
	818
	819	MDRV_MICRODRIVE_ADD(MDV_1, mdv1_config)
	820	MDRV_MICRODRIVE_ADD(MDV_2, mdv2_config)
	821
	822	// cartridge
628	823	MDRV_CARTSLOT_ADD("cart")
629	824	MDRV_CARTSLOT_EXTENSION_LIST("bin,rom")
630	825	MDRV_CARTSLOT_NOT_MANDATORY
	826	MDRV_CARTSLOT_INTERFACE("ql_cart")
631	827
632		MDRV_FLOPPY_2_DRIVES_ADD(ql_floppy_config)
	828	// software lists
	829	MDRV_SOFTWARE_LIST_ADD("cart_list", "ql")
633	830
634		/* internal ram */
	831	// internal ram
635	832	MDRV_RAM_ADD("messram")
636	833	MDRV_RAM_DEFAULT_SIZE("128K")
637	834	MDRV_RAM_EXTRA_OPTIONS("192K,256K,384K,640K,896K")
638	835	MACHINE_CONFIG_END
639	836
	837
	838	//-------------------------------------------------
	839	//  MACHINE_CONFIG( ql_ntsc )
	840	//-------------------------------------------------
	841
640	842	static MACHINE_CONFIG_DERIVED( ql_ntsc, ql )
	843	// video hardware
641	844	MDRV_SCREEN_MODIFY(SCREEN_TAG)
642	845	MDRV_SCREEN_REFRESH_RATE(60)
643	846	MDRV_SCREEN_SIZE(960, 262)
644	847	MDRV_SCREEN_VISIBLE_AREA(0, 512-1, 0, 256-1)
645	848	MACHINE_CONFIG_END
646	849
	850
	851	//-------------------------------------------------
	852	//  MACHINE_CONFIG( opd )
	853	//-------------------------------------------------
	854
647	855	static MACHINE_CONFIG_DERIVED( opd, ql )
648		/* internal ram */
	856	// internal ram
649	857	MDRV_RAM_MODIFY("messram")
650	858	MDRV_RAM_DEFAULT_SIZE("128K")
651	859	MDRV_RAM_EXTRA_OPTIONS("256K")
652	860	MACHINE_CONFIG_END
653	861
	862
	863	//-------------------------------------------------
	864	//  MACHINE_CONFIG( megaopd )
	865	//-------------------------------------------------
	866
654	867	static MACHINE_CONFIG_DERIVED( megaopd, ql )
655		/* internal ram */
	868	// internal ram
656	869	MDRV_RAM_MODIFY("messram")
657	870	MDRV_RAM_DEFAULT_SIZE("256K")
658	871	MACHINE_CONFIG_END
659	872
660		/* ROMs */
661	873
	874
	875	//**************************************************************************
	876	//   ROMS
	877	//**************************************************************************
	878
	879	//-------------------------------------------------
	880	//  ROM( ql )
	881	//-------------------------------------------------
	882
662	883	ROM_START( ql )
663	884	ROM_REGION( 0x10000, M68008_TAG, 0 )
664	885	ROM_DEFAULT_BIOS("js")
r9774	r9775
694	915	ROM_LOAD( "hal16l8.ic38", 0x0000, 0x0400, NO_DUMP )
695	916	ROM_END
696	917
	918
	919	//-------------------------------------------------
	920	//  ROM( ql_us )
	921	//-------------------------------------------------
	922
697	923	ROM_START( ql_us )
698	924	ROM_REGION( 0x10000, M68008_TAG, 0 )
699	925	ROM_LOAD( "jsu.ic33", 0x0000, 0x8000, BAD_DUMP CRC(e397f49f) SHA1(c06f92eabaf3e6dd298c51cb7f7535d8ef0ef9c5) )
r9774	r9775
707	933	ROM_LOAD( "hal16l8.ic38", 0x0000, 0x0400, NO_DUMP )
708	934	ROM_END
709	935
	936
	937	//-------------------------------------------------
	938	//  ROM( ql_es )
	939	//-------------------------------------------------
	940
710	941	ROM_START( ql_es )
711	942	ROM_REGION( 0x10000, M68008_TAG, 0 )
712	943	ROM_LOAD( "mge.ic33", 0x0000, 0x8000, BAD_DUMP CRC(d5293bde) SHA1(bf5af7e53a472d4e9871f182210787d601db0634) )
r9774	r9775
720	951	ROM_LOAD( "hal16l8.ic38", 0x0000, 0x0400, NO_DUMP )
721	952	ROM_END
722	953
	954
	955	//-------------------------------------------------
	956	//  ROM( ql_fr )
	957	//-------------------------------------------------
	958
723	959	ROM_START( ql_fr )
724	960	ROM_REGION( 0x10000, M68008_TAG, 0 )
725	961	ROM_LOAD( "mgf.ic33", 0x0000, 0x8000, NO_DUMP )
r9774	r9775
733	969	ROM_LOAD( "hal16l8.ic38", 0x0000, 0x0400, NO_DUMP )
734	970	ROM_END
735	971
	972
	973	//-------------------------------------------------
	974	//  ROM( ql_de )
	975	//-------------------------------------------------
	976
736	977	ROM_START( ql_de )
737	978	ROM_REGION( 0x10000, M68008_TAG, 0 )
738	979	ROM_SYSTEM_BIOS( 0, "mg", "v1.10 (MG)" )
r9774	r9775
752	993	ROM_LOAD( "hal16l8.ic38", 0x0000, 0x0400, NO_DUMP )
753	994	ROM_END
754	995
	996
	997	//-------------------------------------------------
	998	//  ROM( ql_it )
	999	//-------------------------------------------------
	1000
755	1001	ROM_START( ql_it )
756	1002	ROM_REGION( 0x10000, M68008_TAG, 0 )
757	1003	ROM_LOAD( "mgi.ic33", 0x0000, 0x8000, BAD_DUMP CRC(d5293bde) SHA1(bf5af7e53a472d4e9871f182210787d601db0634) )
r9774	r9775
765	1011	ROM_LOAD( "hal16l8.ic38", 0x0000, 0x0400, NO_DUMP )
766	1012	ROM_END
767	1013
	1014
	1015	//-------------------------------------------------
	1016	//  ROM( ql_se )
	1017	//-------------------------------------------------
	1018
768	1019	ROM_START( ql_se )
769	1020	ROM_REGION( 0x10000, M68008_TAG, 0 )
770	1021	ROM_LOAD( "mgs.ic33", 0x0000, 0x8000, NO_DUMP )
r9774	r9775
778	1029	ROM_LOAD( "hal16l8.ic38", 0x0000, 0x0400, NO_DUMP )
779	1030	ROM_END
780	1031
	1032
	1033	//-------------------------------------------------
	1034	//  ROM( ql_gr )
	1035	//-------------------------------------------------
	1036
781	1037	ROM_START( ql_gr )
782	1038	ROM_REGION( 0x10000, M68008_TAG, 0 )
783	1039	ROM_LOAD( "efp.ic33", 0x0000, 0x8000, BAD_DUMP CRC(eb181641) SHA1(43c1e0215cf540cbbda240b1048910ff55681059) )
r9774	r9775
791	1047	ROM_LOAD( "hal16l8.ic38", 0x0000, 0x0400, NO_DUMP )
792	1048	ROM_END
793	1049
	1050
	1051	//-------------------------------------------------
	1052	//  ROM( ql_dk )
	1053	//-------------------------------------------------
	1054
794	1055	ROM_START( ql_dk )
795	1056	ROM_REGION( 0x10000, M68008_TAG, 0 )
796	1057	ROM_LOAD( "mgd.ic33",  0x0000, 0x8000, BAD_DUMP CRC(f57755eb) SHA1(dc57939ffb8741e17967a1d2479c339750ec7ff6) )
r9774	r9775
807	1068	ROM_LOAD( "hal16l8.ic38", 0x0000, 0x0400, NO_DUMP )
808	1069	ROM_END
809	1070
	1071
	1072	//-------------------------------------------------
	1073	//  ROM( tonto )
	1074	//-------------------------------------------------
	1075
810	1076	ROM_START( tonto )
811	1077	ROM_REGION( 0x400000, M68008_TAG, 0 )
812	1078	ROM_LOAD( "bios-1.rom", 0x000000, 0x008000, NO_DUMP )
r9774	r9775
828	1094	ROM_LOAD( "rompack-5.rom", 0x020000, 0x008000, NO_DUMP )
829	1095	ROM_END
830	1096
	1097
	1098	//-------------------------------------------------
	1099	//  ROM( megaopd )
	1100	//-------------------------------------------------
	1101
831	1102	ROM_START( megaopd )
832	1103	ROM_REGION( 0x400000, M68008_TAG, 0 )
833	1104	ROM_LOAD( "bios-1.rom", 0x000000, 0x008000, NO_DUMP )
r9774	r9775
849	1120	ROM_LOAD( "rompack-5.rom", 0x020000, 0x008000, NO_DUMP )
850	1121	ROM_END
851	1122
852		/* Computer Drivers */
853	1123
854		/*    YEAR  NAME    PARENT  COMPAT  MACHINE     INPUT   INIT    COMPANY                     FULLNAME        FLAGS */
	1124
	1125	//**************************************************************************
	1126	//   SYSTEM DRIVERS
	1127	//**************************************************************************
	1128
	1129	//    YEAR  NAME    PARENT  COMPAT  MACHINE     INPUT   INIT    COMPANY                     FULLNAME        FLAGS
855	1130	COMP( 1984, ql,     0,      0,      ql,         ql,     0,      "Sinclair Research Ltd",    "QL (UK)",      GAME_SUPPORTS_SAVE )
856	1131	COMP( 1985, ql_us,  ql,     0,      ql_ntsc,    ql,     0,      "Sinclair Research Ltd",    "QL (USA)",     GAME_SUPPORTS_SAVE )
857	1132	COMP( 1985, ql_es,  ql,     0,      ql,         ql_es,  0,      "Sinclair Research Ltd",    "QL (Spain)",   GAME_SUPPORTS_SAVE )

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