MESS SVN History

15994 Revisions

r950 Tuesday 11th September, 2007 at 22:19:35 UTC by Nathan Woods
Updated to MAME 0.118u6 core

[ROOT]	makefile
[docs]	messnew.txt
[src/emu]	audit.c audit.h clifront.c clifront.h drawgfx.c emuopts.c emuopts.h emupal.c fileio.c fileio.h mame.c mame.h memory.c profiler.c rendlay.c romload.c romload.h streams.c uimenu.c video.c
[src/emu/cpu]	cpu.mak x86drc.c x86drc.h x86emit.h
[src/emu/cpu/hd6309]	6309ops.c hd6309.c
[src/emu/cpu/mb86233]	mb86233.c
[src/emu/cpu/mips]	mdrcold.c mips3drc.c
[src/emu/cpu/powerpc]	drc_ops.c ppc.c ppcdrc.c
[src/emu/sound]	fm.c tms5220.c tms5220r.c
[src/lib/util]	bitmap.c bitmap.h corefile.c corefile.h
[src/mame]	mame.mak mamedriv.c
[src/mame/audio]	vicdual.c
[src/mame/drivers]	8080bw.c comebaby.c* cps2.c exidy440.c galaxian.c istellar.c ksys573.c model2.c pacland.c pacman.c playmark.c rabbit.c raiden.c rockola.c scramble.c spaceg.c speglsht.c ssfindo.c thayers.c wheelfir.c xain.c
[src/mame/includes]	exidy440.h m107.h m72.h m92.h taitoipt.h
[src/mame/machine]	cps2crpt.c scsicd.c scsidev.h scsihd.c wd33c93.c wd33c93.h
[src/mame/video]	bfm_adr2.c cave.c cclimber.c deco16ic.c exidy440.c gaelco3d.c hng64.c model1.c namcona1.c pacland.c splash.c tmnt.c tunhunt.c twin16.c
[src/mess]	climess.c climess.h mess.h messopts.c messopts.h
[src/mess/tools/imgtool]	main.c
[src/mess/tools/imgtool/windows]	wmain.c
[src/mess/tools/messtest]	testmess.c
[src/osd/windows]	vconv.c window.c
[src/osd/windows/ui]	audit32.c win32ui.c

src/mame/audio/vicdual.c
r949	r950
435	435
436	436	WRITE8_HANDLER( headon_audio_w )
437	437	{
	438	if (!sndti_exists(SOUND_DISCRETE, 0))
	439	return;
438	440	discrete_sound_w(HEADON_HISPEED_PC_EN, data & 0x01);
439	441	discrete_sound_w(HEADON_SCREECH1_EN, data & 0x02);
440	442	discrete_sound_w(HEADON_CRASH_EN, data & 0x04);
r949	r950
447	449
448	450	WRITE8_HANDLER( invho2_audio_w )
449	451	{
	452	if (!sndti_exists(SOUND_DISCRETE, 0))
	453	return;
450	454	discrete_sound_w(HEADON_HISPEED_PC_EN, data & 0x10);
451	455	discrete_sound_w(HEADON_SCREECH1_EN, data & 0x08);
452	456	discrete_sound_w(HEADON_CRASH_EN, data & 0x80);

src/mame/machine/scsihd.c
r949	r950
18	18	int last_command;
19	19	hard_disk_file *disk;
20	20	UINT8 last_packet[16];
	21	UINT8 inquiry_buffer[96];
21	22	} SCSIHd;
22	23
23	24
r949	r950
129	130	break;
130	131
131	132	case 0x12: // INQUIRY
132		pData[0] = 0x00; // device is direct-access (e.g. hard disk)
133		pData[1] = 0x00; // media is not removable
134		pData[2] = 0x05; // device complies with SPC-3 standard
135		pData[3] = 0x02; // response data format = SPC-3 standard
136		memset(&pData[8], 0, 8*3);
137		// Apple HD SC setup utility needs to see this
138		// we should make it configurable at some point.
139		strcpy((char *)&pData[8], " SEAGATE ST225N");
140		strcpy((char *)&pData[32], "1.0");
	133	i = sizeof( our_this->inquiry_buffer );
	134	if( i > bytes )
	135	{
	136	i = bytes;
	137	}
	138
	139	memcpy( pData, our_this->inquiry_buffer, i );
	140
	141	if( i < bytes )
	142	{
	143	memset( pData + i, 0, bytes - i );
	144	}
	145
141	146	break;
142	147
143	148	case 0x1a: // MODE SENSE (6 byte)
r949	r950
229	234
230	235	int scsihd_dispatch(int operation, void file, INT64 intparm, UINT8 ptrparm)
231	236	{
232		SCSIHd instance, *result;
233		hard_disk_file **devptr;
	237	SCSIHd *instance;
	238	void **ptrresult;
234	239
235	240	switch (operation)
236	241	{
r949	r950
252	257	instance->lba = 0;
253	258	instance->blocks = 0;
254	259
	260	memset(instance->inquiry_buffer, 0, sizeof(instance->inquiry_buffer));
	261	instance->inquiry_buffer[0] = 0x00; // device is direct-access (e.g. hard disk)
	262	instance->inquiry_buffer[1] = 0x00; // media is not removable
	263	instance->inquiry_buffer[2] = 0x05; // device complies with SPC-3 standard
	264	instance->inquiry_buffer[3] = 0x02; // response data format = SPC-3 standard
	265	// Apple HD SC setup utility needs to see this
	266	strcpy((char *)&instance->inquiry_buffer[8], " SEAGATE");
	267	strcpy((char *)&instance->inquiry_buffer[16], " ST225N");
	268	strcpy((char *)&instance->inquiry_buffer[32], "1.0");
	269
255	270	#ifdef MESS
256	271	instance->disk = mess_hd_get_hard_disk_file_by_number(intparm);
257	272	#else
r949	r950
263	278	}
264	279	#endif
265	280
266		result = (SCSIHd **) file;
267		*result = instance;
	281	ptrresult = file;
	282	*ptrresult = instance;
268	283	break;
269	284
270	285	case SCSIOP_DELETE_INSTANCE:
r949	r950
272	287	break;
273	288
274	289	case SCSIOP_GET_DEVICE:
275		~~dev~~ptr = (~~hard_d~~i~~sk_file~~ **)ptrparm;
	290	ptrresult = (void **)ptrparm;
276	291	instance = (SCSIHd *)file;
277		*~~dev~~ptr = instance->disk;
	292	*ptrresult = instance->disk;
278	293	break;
279	294
280	295	case SCSIOP_SET_DEVICE:
r949	r950
282	297	instance->disk = (hard_disk_file *)ptrparm;
283	298	break;
284	299
	300
	301	case SCSIOP_GET_INQUIRY_BUFFER:
	302	ptrresult = (void **)ptrparm;
	303	instance = (SCSIHd *)file;
	304
	305	if( intparm > sizeof( instance->inquiry_buffer ) )
	306	{
	307	*ptrresult = NULL;
	308	}
	309	else
	310	{
	311	*ptrresult = instance->inquiry_buffer;
	312	}
	313	break;
285	314	}
286	315
287	316	return 0;

src/mame/machine/scsidev.h
r949	r950
48	48	SCSIOP_DELETE_INSTANCE, // delete an instance of the device
49	49	SCSIOP_GET_DEVICE, // get the device's internal device (CDROM or HDD pointer)
50	50	SCSIOP_SET_DEVICE, // set the device's internal device (CDROM or HDD pointer)
	51	SCSIOP_GET_INQUIRY_BUFFER, // get the device's inquiry buffer
51	52	};
52	53
53	54	// macros to make config structs cleaner

src/mame/machine/scsicd.c
r949	r950
18	18	int last_command, last_retval;
19	19	cdrom_file *cdrom;
20	20	UINT8 last_packet[16];
	21	UINT8 inquiry_buffer[96];
21	22	} SCSICd;
22	23
23	24
r949	r950
338	339	break;
339	340
340	341	case 0x12: // INQUIRY
341		pData[0] = 0x05; // device is present, device is CD/DVD (MMC-3)
342		pData[1] = 0x80; // media is removable
343		pData[2] = 0x05; // device complies with SPC-3 standard
344		pData[3] = 0x02; // response data format = SPC-3 standard
345		memset(&pData[8], 0, 8*3);
346		strcpy((char *)&pData[8], "Sony"); // some Konami games freak out if this isn't "Sony", so we'll lie
347		strcpy((char *)&pData[16], "CDU-76S"); // this is the actual drive on my Nagano '98 board
348		strcpy((char *)&pData[32], "1.0");
	342	i = sizeof( our_this->inquiry_buffer );
	343	if( i > bytes )
	344	{
	345	i = bytes;
	346	}
	347
	348	memcpy( pData, our_this->inquiry_buffer, i );
	349
	350	if( i < bytes )
	351	{
	352	memset( pData + i, 0, bytes - i );
	353	}
	354
349	355	break;
350	356
351	357	case 0x25: // READ CAPACITY
r949	r950
651	657
652	658	int scsicd_dispatch(int operation, void file, INT64 intparm, UINT8 ptrparm)
653	659	{
654		SCSICd instance, *result;
655		cdrom_file **devptr;
	660	SCSICd *instance;
	661	void **ptrresult;
656	662
657	663	switch (operation)
658	664	{
r949	r950
678	684	instance->cur_subblock = 0;
679	685	instance->play_err_flag = 0;
680	686
	687	memset(instance->inquiry_buffer, 0, sizeof(instance->inquiry_buffer));
	688	instance->inquiry_buffer[0] = 0x05; // device is present, device is CD/DVD (MMC-3)
	689	instance->inquiry_buffer[1] = 0x80; // media is removable
	690	instance->inquiry_buffer[2] = 0x05; // device complies with SPC-3 standard
	691	instance->inquiry_buffer[3] = 0x02; // response data format = SPC-3 standard
	692	// some Konami games freak out if this isn't "Sony", so we'll lie
	693	// this is the actual drive on my Nagano '98 board
	694	strcpy((char *)&instance->inquiry_buffer[8], "Sony");
	695	strcpy((char *)&instance->inquiry_buffer[16], "CDU-76S");
	696	strcpy((char *)&instance->inquiry_buffer[32], "1.0");
	697
681	698	#ifdef MESS
682	699	instance->cdrom = mess_cd_get_cdrom_file_by_number(intparm);
683	700	#else
r949	r950
689	706	}
690	707	#endif
691	708
692		result = (SCSICd **) file;
693		*result = instance;
	709	ptrresult = file;
	710	*ptrresult = instance;
694	711	break;
695	712
696	713	case SCSIOP_DELETE_INSTANCE:
r949	r950
706	723	break;
707	724
708	725	case SCSIOP_GET_DEVICE:
709		~~dev~~ptr = (~~cdr~~o~~m_f~~ile **)ptrparm;
	726	ptrresult = (void **)ptrparm;
710	727	instance = (SCSICd *)file;
711		*~~dev~~ptr = instance->cdrom;
	728	*ptrresult = instance->cdrom;
712	729	break;
713	730
714	731	case SCSIOP_SET_DEVICE:
715	732	instance = (SCSICd *)file;
716	733	instance->cdrom = (cdrom_file *)ptrparm;
717	734	break;
	735
	736	case SCSIOP_GET_INQUIRY_BUFFER:
	737	ptrresult = (void **)ptrparm;
	738	instance = (SCSICd *)file;
	739
	740	if( intparm > sizeof( instance->inquiry_buffer ) )
	741	{
	742	*ptrresult = NULL;
	743	}
	744	else
	745	{
	746	*ptrresult = instance->inquiry_buffer;
	747	}
	748	break;
718	749	}
719	750
720	751	return 0;

src/mame/machine/wd33c93.c
r949	r950
870	870	{
871	871	return wd33c93_get_xfer_count();
872	872	}
873		/*
874		* wd33c93.c
875		*
876		* WD/AMD 33c93 SCSI controller, as seen in
877		* early PCs, some MSX add-ons, NEC PC-88, and SGI
878		* Indigo, Indigo2, and Indy systems.
879		*
880		* References:
881		* WD 33c93 manual
882		* NetBSD 33c93 driver
883		*
884		*/
885
886		#include "driver.h"
887		#include "state.h"
888		#include "wd33c93.h"
889
890		#define VERBOSE 0
891
892		typedef struct
893		{
894		void *data; // device's "this" pointer
895		pSCSIDispatch handler; // device's handler routine
896		} SCSIDev;
897
898		static SCSIDev devices[8]; // SCSI IDs 0-7
899		static struct WD33C93interface *intf;
900
901		/* wd register names */
902		#define WD_OWN_ID 0x00
903		#define WD_CONTROL 0x01
904		#define WD_TIMEOUT_PERIOD 0x02
905		#define WD_CDB_1 0x03
906		#define WD_CDB_2 0x04
907		#define WD_CDB_3 0x05
908		#define WD_CDB_4 0x06
909		#define WD_CDB_5 0x07
910		#define WD_CDB_6 0x08
911		#define WD_CDB_7 0x09
912		#define WD_CDB_8 0x0a
913		#define WD_CDB_9 0x0b
914		#define WD_CDB_10 0x0c
915		#define WD_CDB_11 0x0d
916		#define WD_CDB_12 0x0e
917		#define WD_TARGET_LUN 0x0f
918		#define WD_COMMAND_PHASE 0x10
919		#define WD_SYNCHRONOUS_TRANSFER 0x11
920		#define WD_TRANSFER_COUNT_MSB 0x12
921		#define WD_TRANSFER_COUNT 0x13
922		#define WD_TRANSFER_COUNT_LSB 0x14
923		#define WD_DESTINATION_ID 0x15
924		#define WD_SOURCE_ID 0x16
925		#define WD_SCSI_STATUS 0x17
926		#define WD_COMMAND 0x18
927		#define WD_DATA 0x19
928		#define WD_QUEUE_TAG 0x1a
929		#define WD_AUXILIARY_STATUS 0x1f
930
931		/* WD commands */
932		#define WD_CMD_RESET 0x00
933		#define WD_CMD_ABORT 0x01
934		#define WD_CMD_ASSERT_ATN 0x02
935		#define WD_CMD_NEGATE_ACK 0x03
936		#define WD_CMD_DISCONNECT 0x04
937		#define WD_CMD_RESELECT 0x05
938		#define WD_CMD_SEL_ATN 0x06
939		#define WD_CMD_SEL 0x07
940		#define WD_CMD_SEL_ATN_XFER 0x08
941		#define WD_CMD_SEL_XFER 0x09
942		#define WD_CMD_RESEL_RECEIVE 0x0a
943		#define WD_CMD_RESEL_SEND 0x0b
944		#define WD_CMD_WAIT_SEL_RECEIVE 0x0c
945		#define WD_CMD_SSCC 0x0d
946		#define WD_CMD_SND_DISC 0x0e
947		#define WD_CMD_SET_IDI 0x0f
948		#define WD_CMD_RCV_CMD 0x10
949		#define WD_CMD_RCV_DATA 0x11
950		#define WD_CMD_RCV_MSG_OUT 0x12
951		#define WD_CMD_RCV 0x13
952		#define WD_CMD_SND_STATUS 0x14
953		#define WD_CMD_SND_DATA 0x15
954		#define WD_CMD_SND_MSG_IN 0x16
955		#define WD_CMD_SND 0x17
956		#define WD_CMD_TRANS_ADDR 0x18
957		#define WD_CMD_XFER_PAD 0x19
958		#define WD_CMD_TRANS_INFO 0x20
959		#define WD_CMD_TRANSFER_PAD 0x21
960		#define WD_CMD_SBT_MODE 0x80
961
962		/* ASR register */
963		#define ASR_INT 0x80
964		#define ASR_LCI 0x40
965		#define ASR_BSY 0x20
966		#define ASR_CIP 0x10
967		#define ASR_PE 0x02
968		#define ASR_DBR 0x01
969
970		/* SCSI Bus Phases */
971		#define PHS_DATA_OUT 0x00
972		#define PHS_DATA_IN 0x01
973		#define PHS_COMMAND 0x02
974		#define PHS_STATUS 0x03
975		#define PHS_MESS_OUT 0x06
976		#define PHS_MESS_IN 0x07
977
978		/* Command Status Register definitions */
979
980		/* reset state interrupts */
981		#define CSR_RESET 0x00
982		#define CSR_RESET_AF 0x01
983
984		/* successful completion interrupts */
985		#define CSR_RESELECT 0x10
986		#define CSR_SELECT 0x11
987		#define CSR_SEL_XFER_DONE 0x16
988		#define CSR_XFER_DONE 0x18
989
990		/* paused or aborted interrupts */
991		#define CSR_MSGIN 0x20
992		#define CSR_SDP 0x21
993		#define CSR_SEL_ABORT 0x22
994		#define CSR_RESEL_ABORT 0x25
995		#define CSR_RESEL_ABORT_AM 0x27
996		#define CSR_ABORT 0x28
997
998		/* terminated interrupts */
999		#define CSR_INVALID 0x40
1000		#define CSR_UNEXP_DISC 0x41
1001		#define CSR_TIMEOUT 0x42
1002		#define CSR_PARITY 0x43
1003		#define CSR_PARITY_ATN 0x44
1004		#define CSR_BAD_STATUS 0x45
1005		#define CSR_UNEXP 0x48
1006
1007		/* service required interrupts */
1008		#define CSR_RESEL 0x80
1009		#define CSR_RESEL_AM 0x81
1010		#define CSR_DISC 0x85
1011		#define CSR_SRV_REQ 0x88
1012
1013		/* Own ID/CDB Size register */
1014		#define OWNID_EAF 0x08
1015		#define OWNID_EHP 0x10
1016		#define OWNID_RAF 0x20
1017		#define OWNID_FS_8 0x00
1018		#define OWNID_FS_12 0x40
1019		#define OWNID_FS_16 0x80
1020
1021		/* Control register */
1022		#define CTRL_HSP 0x01
1023		#define CTRL_HA 0x02
1024		#define CTRL_IDI 0x04
1025		#define CTRL_EDI 0x08
1026		#define CTRL_HHP 0x10
1027		#define CTRL_POLLED 0x00
1028		#define CTRL_BURST 0x20
1029		#define CTRL_BUS 0x40
1030		#define CTRL_DMA 0x80
1031
1032		/* Synchronous Transfer Register */
1033		#define STR_FSS 0x80
1034
1035		/* Destination ID register */
1036		#define DSTID_DPD 0x40
1037		#define DATA_OUT_DIR 0
1038		#define DATA_IN_DIR 1
1039		#define DSTID_SCC 0x80
1040
1041		/* Source ID register */
1042		#define SRCID_MASK 0x07
1043		#define SRCID_SIV 0x08
1044		#define SRCID_DSP 0x20
1045		#define SRCID_ES 0x40
1046		#define SRCID_ER 0x80
1047
1048		/* command handler definition */
1049		typedef void (*cmd_handler)(void);
1050
1051		#define TEMP_INPUT_LEN 65536
1052		#define FIFO_SIZE 12
1053
1054		/* internal controller data definition */
1055		typedef struct
1056		{
1057		UINT8 sasr;
1058		UINT8 regs[WD_AUXILIARY_STATUS+1];
1059		UINT8 fifo[FIFO_SIZE];
1060		int fifo_pos;
1061		UINT8 *temp_input;
1062		int temp_input_pos;
1063		UINT8 busphase;
1064		UINT8 identify;
1065		int read_pending;
1066		mame_timer *cmd_timer;
1067		} _wd33c93_data;
1068
1069		/* local instance of controller data */
1070		static _wd33c93_data scsi_data;
1071
1072
1073		/* convernience functions */
1074		static UINT8 wd33c93_getunit( void )
1075		{
1076		/* return the destination unit id */
1077		return scsi_data.regs[WD_DESTINATION_ID] & SRCID_MASK;
1078		}
1079
1080		static void wd33c93_set_xfer_count( int count )
1081		{
1082		/* set the count */
1083		scsi_data.regs[ WD_TRANSFER_COUNT_LSB ] = count & 0xff;
1084		scsi_data.regs[ WD_TRANSFER_COUNT ] = ( count >> 8 ) & 0xff;
1085		scsi_data.regs[ WD_TRANSFER_COUNT_MSB ] = ( count >> 16 ) & 0xff;
1086		}
1087
1088		static int wd33c93_get_xfer_count( void )
1089		{
1090		/* get the count */
1091		int count = scsi_data.regs[ WD_TRANSFER_COUNT_MSB ];
1092
1093		count <<= 8;
1094		count \|= scsi_data.regs[ WD_TRANSFER_COUNT ];
1095		count <<= 8;
1096		count \|= scsi_data.regs[ WD_TRANSFER_COUNT_LSB ];
1097
1098		return count;
1099		}
1100
1101		static void wd33c93_read_data(int bytes, UINT8 *pData)
1102		{
1103		UINT8 unit = wd33c93_getunit();
1104
1105		if ( devices[unit].handler )
1106		{
1107		devices[unit].handler(SCSIOP_READ_DATA, devices[unit].data, bytes, pData);
1108		}
1109		else
1110		{
1111		logerror("wd33c93: request for unknown device SCSI ID %d\n", unit);
1112		}
1113		}
1114
1115		static void wd33c93_complete_immediate( int status )
1116		{
1117		/* reset our timer */
1118		mame_timer_reset( scsi_data.cmd_timer, time_never );
1119
1120		/* set the new status */
1121		scsi_data.regs[WD_SCSI_STATUS] = status & 0xff;
1122
1123		/* set interrupt pending */
1124		scsi_data.regs[WD_AUXILIARY_STATUS] \|= ASR_INT;
1125
1126		/* check for error conditions */
1127		if ( wd33c93_get_xfer_count() > 0 )
1128		{
1129		/* set data buffer ready */
1130		scsi_data.regs[WD_AUXILIARY_STATUS] \|= ASR_DBR;
1131		}
1132		else
1133		{
1134		/* clear data buffer ready */
1135		scsi_data.regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
1136		}
1137
1138		/* clear command in progress and bus busy */
1139		scsi_data.regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP \| ASR_BSY);
1140
1141		/* if we have a callback, call it */
1142		if (intf && intf->irq_callback)
1143		{
1144		intf->irq_callback(1);
1145		}
1146		}
1147
1148		static TIMER_CALLBACK(wd33c93_complete_cb)
1149		{
1150		wd33c93_complete_immediate( param );
1151		}
1152
1153		static TIMER_CALLBACK(wd33c93_service_request)
1154		{
1155		/* issue a message out request */
1156		wd33c93_complete_immediate(CSR_SRV_REQ \| scsi_data.busphase);
1157		}
1158
1159		static TIMER_CALLBACK(wd33c93_deassert_cip)
1160		{
1161		scsi_data.regs[WD_AUXILIARY_STATUS] &= ~ASR_CIP;
1162		}
1163
1164		static void wd33c93_complete_cmd( UINT8 status )
1165		{
1166		/* fire off a timer to complete the command */
1167		mame_timer_adjust( scsi_data.cmd_timer, MAME_TIME_IN_USEC(1), status, time_zero );
1168		}
1169
1170		/* command handlers */
1171		static void wd33c93_invalid_cmd( void )
1172		{
1173		logerror( "Unknown/Unimplemented SCSI controller command: %02x (PC=%x)\n", scsi_data.regs[WD_COMMAND], activecpu_get_pc() );
1174
1175		/* complete the command */
1176		wd33c93_complete_cmd( CSR_INVALID );
1177		}
1178
1179		static void wd33c93_reset_cmd( void )
1180		{
1181		int advanced = 0;
1182
1183		/* see if it wants us to reset with advanced features */
1184		if ( scsi_data.regs[WD_OWN_ID] & OWNID_EAF )
1185		{
1186		advanced = 1;
1187		}
1188
1189		/* clear out all registers */
1190		memset( scsi_data.regs, 0, sizeof( scsi_data.regs ) );
1191
1192		/* complete the command */
1193		wd33c93_complete_cmd(advanced ? CSR_RESET_AF : CSR_RESET);
1194		}
1195
1196		static void wd33c93_abort_cmd( void )
1197		{
1198		/* complete the command */
1199		wd33c93_complete_cmd(CSR_ABORT);
1200		}
1201
1202		static void wd33c93_disconnect_cmd( void )
1203		{
1204		/* complete the command */
1205		scsi_data.regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP \| ASR_BSY);
1206		}
1207
1208		static void wd33c93_select_cmd( void )
1209		{
1210		UINT8 unit = wd33c93_getunit();
1211		UINT8 newstatus;
1212
1213		/* see if we can select that device */
1214		if ( devices[unit].handler )
1215		{
1216		/* device is available - signal selection done */
1217		newstatus = CSR_SELECT;
1218
1219		/* determine the next bus phase depending on the command */
1220		if ( (scsi_data.regs[WD_COMMAND] & 0x7f) == WD_CMD_SEL_ATN )
1221		{
1222		/* /ATN asserted during select: Move to Message Out Phase to read identify */
1223		scsi_data.busphase = PHS_MESS_OUT;
1224		}
1225		else
1226		{
1227		/* No /ATN asserted: Move to Command Phase */
1228		scsi_data.busphase = PHS_COMMAND;
1229		}
1230
1231		/* queue up a service request out in the future */
1232		mame_timer_set( MAME_TIME_IN_USEC(50), 0, wd33c93_service_request );
1233		}
1234		else
1235		{
1236		/* device is not available */
1237		newstatus = CSR_TIMEOUT;
1238		}
1239
1240		/* complete the command */
1241		wd33c93_complete_cmd(newstatus);
1242		}
1243
1244		static void wd33c93_selectxfer_cmd( void )
1245		{
1246		UINT8 unit = wd33c93_getunit();
1247		UINT8 newstatus;
1248
1249		/* see if we can select that device */
1250		if ( devices[unit].handler )
1251		{
1252		if ( scsi_data.regs[WD_COMMAND_PHASE] < 0x45 )
1253		{
1254		/* device is available */
1255		int xfercount;
1256
1257		/* do the request */
1258		xfercount = devices[unit].handler(SCSIOP_EXEC_COMMAND, devices[unit].data, 0, &scsi_data.regs[WD_CDB_1]);
1259
1260		/* set transfer count */
1261		if ( wd33c93_get_xfer_count() > TEMP_INPUT_LEN )
1262		{
1263		logerror( "WD33C93: Transfer count too big. Please increase TEMP_INPUT_LEN (size=%d)\n", wd33c93_get_xfer_count() );
1264		wd33c93_set_xfer_count( TEMP_INPUT_LEN );
1265		}
1266
1267		scsi_data.read_pending = 1;
1268		}
1269
1270		if ( scsi_data.read_pending )
1271		{
1272		int len = TEMP_INPUT_LEN;
1273
1274		if ( wd33c93_get_xfer_count() < len ) len = wd33c93_get_xfer_count();
1275
1276		memset( &scsi_data.temp_input[0], 0, TEMP_INPUT_LEN );
1277		wd33c93_read_data( len, &scsi_data.temp_input[0] );
1278		scsi_data.temp_input_pos = 0;
1279		scsi_data.read_pending = 0;
1280		}
1281
1282		scsi_data.regs[WD_TARGET_LUN] = 0;
1283		scsi_data.regs[WD_CONTROL] \|= CTRL_EDI;
1284		scsi_data.regs[WD_COMMAND_PHASE] = 0x60;
1285
1286		/* signal transfer ready */
1287		newstatus = CSR_SEL_XFER_DONE;
1288
1289		/* if allowed disconnect, queue a service request */
1290		if ( scsi_data.identify & 0x40 )
1291		{
1292		/* queue disconnect message in */
1293		scsi_data.busphase = PHS_MESS_IN;
1294
1295		/* queue up a service request out in the future */
1296		mame_timer_set( MAME_TIME_IN_MSEC(50), 0, wd33c93_service_request );
1297		}
1298		}
1299		else
1300		{
1301		/* device is not available */
1302		newstatus = CSR_TIMEOUT;
1303
1304		wd33c93_set_xfer_count( 0 );
1305		}
1306
1307		/* complete the command */
1308		wd33c93_complete_cmd(newstatus);
1309		}
1310
1311		static void wd33c93_negate_ack( void )
1312		{
1313		logerror( "WD33C93: ACK Negated\n" );
1314
1315		/* complete the command */
1316		scsi_data.regs[WD_AUXILIARY_STATUS] &= ~(ASR_CIP \| ASR_BSY);
1317		}
1318
1319		static void wd33c93_xferinfo_cmd( void )
1320		{
1321		/* make the buffer available right away */
1322		scsi_data.regs[WD_AUXILIARY_STATUS] \|= ASR_DBR;
1323		scsi_data.regs[WD_AUXILIARY_STATUS] \|= ASR_CIP;
1324
1325		/* the command will be completed once the data is transferred */
1326		mame_timer_set( MAME_TIME_IN_MSEC(1), 0, wd33c93_deassert_cip );
1327		}
1328
1329		/* Command handlers */
1330		static cmd_handler wd33c93_cmds[0x22] =
1331		{
1332		&wd33c93_reset_cmd, /* 0x00 - WD_CMD_RESET */
1333		&wd33c93_abort_cmd, /* 0x01 - WD_CMD_ABORT */
1334		&wd33c93_invalid_cmd, /* 0x02 - WD_CMD_ASSERT_ATN (uninmplemented) */
1335		&wd33c93_negate_ack, /* 0x03 - WD_CMD_NEGATE_ACK */
1336		&wd33c93_disconnect_cmd,/* 0x04 - WD_CMD_DISCONNECT */
1337		&wd33c93_invalid_cmd, /* 0x05 - WD_CMD_RESELECT (uninmplemented) */
1338		&wd33c93_select_cmd, /* 0x06 - WD_CMD_SEL_ATN */
1339		&wd33c93_select_cmd, /* 0x07 - WD_CMD_SEL */
1340		&wd33c93_selectxfer_cmd,/* 0x08 - WD_CMD_SEL_ATN_XFER */
1341		&wd33c93_selectxfer_cmd,/* 0x09 - WD_CMD_SEL_XFER */
1342		&wd33c93_invalid_cmd, /* 0x0a - WD_CMD_RESEL_RECEIVE (uninmplemented) */
1343		&wd33c93_invalid_cmd, /* 0x0b - WD_CMD_RESEL_SEND (uninmplemented) */
1344		&wd33c93_invalid_cmd, /* 0x0c - WD_CMD_WAIT_SEL_RECEIVE (uninmplemented) */
1345		&wd33c93_invalid_cmd, /* 0x0d - WD_CMD_SSCC (uninmplemented) */
1346		&wd33c93_invalid_cmd, /* 0x0e - WD_CMD_SND_DISC (uninmplemented) */
1347		&wd33c93_invalid_cmd, /* 0x0f - WD_CMD_SET_IDI (uninmplemented) */
1348		&wd33c93_invalid_cmd, /* 0x10 - WD_CMD_RCV_CMD (uninmplemented) */
1349		&wd33c93_invalid_cmd, /* 0x11 - WD_CMD_RCV_DATA (uninmplemented) */
1350		&wd33c93_invalid_cmd, /* 0x12 - WD_CMD_RCV_MSG_OUT (uninmplemented) */
1351		&wd33c93_invalid_cmd, /* 0x13 - WD_CMD_RCV (uninmplemented) */
1352		&wd33c93_invalid_cmd, /* 0x14 - WD_CMD_SND_STATUS (uninmplemented) */
1353		&wd33c93_invalid_cmd, /* 0x15 - WD_CMD_SND_DATA (uninmplemented) */
1354		&wd33c93_invalid_cmd, /* 0x16 - WD_CMD_SND_MSG_IN (uninmplemented) */
1355		&wd33c93_invalid_cmd, /* 0x17 - WD_CMD_SND (uninmplemented) */
1356		&wd33c93_invalid_cmd, /* 0x18 - WD_CMD_TRANS_ADDR (uninmplemented) */
1357		&wd33c93_invalid_cmd, /* 0x19 - WD_CMD_XFER_PAD (uninmplemented) */
1358		&wd33c93_invalid_cmd, /* 0x1a - invalid */
1359		&wd33c93_invalid_cmd, /* 0x1b - invalid */
1360		&wd33c93_invalid_cmd, /* 0x1c - invalid */
1361		&wd33c93_invalid_cmd, /* 0x1d - invalid */
1362		&wd33c93_invalid_cmd, /* 0x1e - invalid */
1363		&wd33c93_invalid_cmd, /* 0x1f - invalid */
1364		&wd33c93_xferinfo_cmd, /* 0x20 - WD_CMD_TRANS_INFO) */
1365		&wd33c93_invalid_cmd /* 0x21 - WD_CMD_TRANSFER_PAD (uninmplemented) */
1366		};
1367
1368		/* Handle pending commands */
1369		static void wd33c93_command( void )
1370		{
1371		/* get the command */
1372		UINT8 cmd = scsi_data.regs[WD_COMMAND];
1373
1374		/* check if its within valid bounds */
1375		if ( (cmd & 0x7F) > WD_CMD_TRANSFER_PAD )
1376		{
1377		wd33c93_invalid_cmd();
1378		return;
1379		}
1380
1381		/* call the command handler */
1382		(*wd33c93_cmds[cmd & 0x7F])();
1383		}
1384
1385		WRITE8_HANDLER(wd33c93_w)
1386		{
1387		switch( offset )
1388		{
1389		case 0:
1390		{
1391		/* update register select */
1392		scsi_data.sasr = data & 0x1f;
1393		}
1394		break;
1395
1396		case 1:
1397		{
1398		#if VERBOSE
1399		logerror( "WD33C93: PC=%08x - Write REG=%02x, data = %02x\n", safe_activecpu_get_pc(), scsi_data.sasr, data );
1400		#endif
1401
1402		/* update the register */
1403		scsi_data.regs[scsi_data.sasr] = data;
1404
1405		/* if we receive a command, schedule to process it */
1406		if ( scsi_data.sasr == WD_COMMAND )
1407		{
1408		#if VERBOSE
1409		logerror( "WDC33C93: PC=%08x - Executing command %08x - unit %d\n", safe_activecpu_get_pc(), data, wd33c93_getunit() );
1410		#endif
1411
1412		/* signal we're processing it */
1413		scsi_data.regs[WD_AUXILIARY_STATUS] \|= ASR_CIP;
1414
1415		/* process the command */
1416		wd33c93_command();
1417		}
1418		else if ( scsi_data.sasr == WD_CDB_1 )
1419		{
1420		scsi_data.regs[WD_COMMAND_PHASE] = 0;
1421		}
1422		else if ( scsi_data.sasr == WD_DATA )
1423		{
1424		/* if data was written, and we have a count, send to device */
1425		int count = wd33c93_get_xfer_count();
1426
1427		if ( scsi_data.regs[WD_COMMAND] & 0x80 )
1428		count = 1;
1429
1430		if ( count-- > 0 )
1431		{
1432		/* write to FIFO */
1433		if ( scsi_data.fifo_pos < FIFO_SIZE )
1434		{
1435		scsi_data.fifo[scsi_data.fifo_pos++] = data;
1436		}
1437
1438		/* update count */
1439		wd33c93_set_xfer_count( count );
1440
1441		/* if we're done with the write, see where we're at */
1442		if ( count == 0 )
1443		{
1444		scsi_data.regs[WD_AUXILIARY_STATUS] \|= ASR_INT;
1445		scsi_data.regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
1446
1447		switch( scsi_data.busphase )
1448		{
1449		case PHS_MESS_OUT:
1450		{
1451		/* reset fifo */
1452		scsi_data.fifo_pos = 0;
1453
1454		/* Message out phase. Data is probably SCSI Identify. Move to command phase. */
1455		scsi_data.busphase = PHS_COMMAND;
1456
1457		scsi_data.identify = scsi_data.fifo[0];
1458		}
1459		break;
1460
1461		case PHS_COMMAND:
1462		{
1463		UINT8 unit = wd33c93_getunit();
1464		int xfercount;
1465
1466		/* Execute the command. Depending on the command, we'll move to data in or out */
1467		xfercount = devices[unit].handler(SCSIOP_EXEC_COMMAND, devices[unit].data, 0, &scsi_data.fifo[0]);
1468
1469		/* reset fifo */
1470		scsi_data.fifo_pos = 0;
1471
1472		/* set the new count */
1473		wd33c93_set_xfer_count( xfercount );
1474
1475		if ( xfercount == 0 )
1476		{
1477		/* move to status phase */
1478		scsi_data.busphase = PHS_STATUS;
1479		}
1480		else
1481		{
1482		/* update bus phase */
1483		if ( scsi_data.fifo[0] == 0x15 \|\| scsi_data.fifo[0] == 0x55 ) /* MODE SELECT */
1484		{
1485		scsi_data.busphase = PHS_DATA_OUT;
1486		}
1487		else
1488		{
1489		scsi_data.busphase = PHS_DATA_IN;
1490		scsi_data.read_pending = 1;
1491		}
1492		}
1493		}
1494		break;
1495
1496		case PHS_DATA_OUT:
1497		{
1498		/* write data out to device */
1499		wd33c93_write_data( scsi_data.fifo_pos, scsi_data.fifo );
1500
1501		/* reset fifo */
1502		scsi_data.fifo_pos = 0;
1503
1504		/* move to status phase */
1505		scsi_data.busphase = PHS_STATUS;
1506		}
1507		break;
1508		}
1509
1510		/* complete the command */
1511		wd33c93_complete_immediate(CSR_XFER_DONE \| scsi_data.busphase);
1512		}
1513		}
1514		else
1515		{
1516		logerror( "WD33C93: Sending data to device with transfer count = 0!. Ignoring...\n" );
1517		}
1518		}
1519
1520		/* auto-increment register select if not on special registers */
1521		if ( scsi_data.sasr != WD_COMMAND && scsi_data.sasr != WD_DATA && scsi_data.sasr != WD_AUXILIARY_STATUS )
1522		{
1523		scsi_data.sasr = ( scsi_data.sasr + 1 ) & 0x1f;
1524		}
1525		}
1526		break;
1527
1528		default:
1529		{
1530		logerror( "WD33C93: Write to invalid offset %d (data=%02x)\n", offset, data );
1531		}
1532		break;
1533		}
1534		}
1535
1536		READ8_HANDLER(wd33c93_r)
1537		{
1538		switch( offset )
1539		{
1540		case 0:
1541		{
1542		/* read aux status */
1543		return scsi_data.regs[WD_AUXILIARY_STATUS];
1544		}
1545		break;
1546
1547		case 1:
1548		{
1549		UINT8 ret;
1550
1551		/* if reading status, clear irq flag */
1552		if ( scsi_data.sasr == WD_SCSI_STATUS )
1553		{
1554		scsi_data.regs[WD_AUXILIARY_STATUS] &= ~ASR_INT;
1555
1556		if (intf && intf->irq_callback)
1557		{
1558		intf->irq_callback(0);
1559		}
1560
1561		#if VERBOSE
1562		logerror( "WD33C93: PC=%08x - Status read (%02x)\n", safe_activecpu_get_pc(), scsi_data.regs[WD_SCSI_STATUS] );
1563		#endif
1564		}
1565		else if ( scsi_data.sasr == WD_DATA )
1566		{
1567		/* we're going to be doing synchronous reads */
1568
1569		/* get the transfer count */
1570		int count = wd33c93_get_xfer_count();
1571
1572		/* initialize the return value */
1573		scsi_data.regs[WD_DATA] = 0;
1574
1575		if ( count <= 0 && scsi_data.busphase == PHS_MESS_IN )
1576		{
1577		/* move to disconnect */
1578		wd33c93_complete_cmd(CSR_DISC);
1579		}
1580		else if ( count == 1 && scsi_data.busphase == PHS_STATUS )
1581		{
1582		/* update the count */
1583		wd33c93_set_xfer_count( 0 );
1584
1585		/* move to message in phase */
1586		scsi_data.busphase = PHS_MESS_IN;
1587
1588		/* complete the command */
1589		wd33c93_complete_cmd(CSR_XFER_DONE \| scsi_data.busphase);
1590		}
1591		else if ( count-- > 0 ) /* make sure we still have data to send */
1592		{
1593		if ( scsi_data.read_pending )
1594		{
1595		int len = TEMP_INPUT_LEN;
1596
1597		if ( (count+1) < len ) len = count+1;
1598		wd33c93_read_data( len, &scsi_data.temp_input[0] );
1599		scsi_data.temp_input_pos = 0;
1600		scsi_data.read_pending = 0;
1601		}
1602
1603		scsi_data.regs[WD_AUXILIARY_STATUS] &= ~ASR_INT;
1604
1605		/* read in one byte */
1606		if ( scsi_data.temp_input_pos < TEMP_INPUT_LEN )
1607		scsi_data.regs[WD_DATA] = scsi_data.temp_input[scsi_data.temp_input_pos++];
1608
1609		/* update the count */
1610		wd33c93_set_xfer_count( count );
1611
1612		/* transfer finished, see where we're at */
1613		if ( count == 0 )
1614		{
1615		if ( scsi_data.regs[WD_COMMAND_PHASE] != 0x60 )
1616		{
1617		/* move to status phase */
1618		scsi_data.busphase = PHS_STATUS;
1619
1620		/* complete the command */
1621		wd33c93_complete_cmd(CSR_XFER_DONE \| scsi_data.busphase);
1622		}
1623		else
1624		{
1625		scsi_data.regs[WD_AUXILIARY_STATUS] \|= ASR_INT;
1626		scsi_data.regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
1627		}
1628		}
1629		}
1630		}
1631
1632		#if VERBOSE
1633		logerror( "WD33C93: PC=%08x - Data read (%02x)\n", safe_activecpu_get_pc(), scsi_data.regs[WD_DATA] );
1634		#endif
1635
1636		/* get the register value */
1637		ret = scsi_data.regs[scsi_data.sasr];
1638
1639		/* auto-increment register select if not on special registers */
1640		if ( scsi_data.sasr != WD_COMMAND && scsi_data.sasr != WD_DATA && scsi_data.sasr != WD_AUXILIARY_STATUS )
1641		{
1642		scsi_data.sasr = ( scsi_data.sasr + 1 ) & 0x1f;
1643		}
1644
1645		return ret;
1646		}
1647
1648		default:
1649		{
1650		logerror( "WD33C93: Read from invalid offset %d\n", offset );
1651		}
1652		break;
1653		}
1654
1655		return 0;
1656		}
1657
1658		extern void wd33c93_init( struct WD33C93interface *interface )
1659		{
1660		int i;
1661
1662		// save interface pointer for later
1663		intf = interface;
1664
1665		memset(&scsi_data, 0, sizeof(scsi_data));
1666		memset(devices, 0, sizeof(devices));
1667
1668		// try to open the devices
1669		for (i = 0; i < interface->scsidevs->devs_present; i++)
1670		{
1671		devices[interface->scsidevs->devices[i].scsiID].handler = interface->scsidevs->devices[i].handler;
1672		interface->scsidevs->devices[i].handler(SCSIOP_ALLOC_INSTANCE, &devices[interface->scsidevs->devices[i].scsiID].data, interface->scsidevs->devices[i].diskID, (UINT8 *)NULL);
1673		}
1674
1675		/* allocate a timer for commands */
1676		scsi_data.cmd_timer = mame_timer_alloc(wd33c93_complete_cb);
1677
1678		scsi_data.temp_input = auto_malloc( TEMP_INPUT_LEN );
1679
1680		// state_save_register_item_array("wd33c93", 0, scsi_data);
1681		}
1682
1683		void wd33c93_get_dma_data( int bytes, UINT8 *pData )
1684		{
1685		int len = bytes;
1686
1687		if ( len >= wd33c93_get_xfer_count() )
1688		len = wd33c93_get_xfer_count();
1689
1690		if ( len == 0 )
1691		return;
1692
1693		if ( (scsi_data.temp_input_pos+len) >= TEMP_INPUT_LEN )
1694		{
1695		logerror( "Reading past end of buffer, increase TEMP_INPUT_LEN size\n" );
1696		len = TEMP_INPUT_LEN - len;
1697		}
1698
1699		memcpy( pData, &scsi_data.temp_input[scsi_data.temp_input_pos], len );
1700
1701		scsi_data.temp_input_pos += len;
1702		len = wd33c93_get_xfer_count() - len;
1703		wd33c93_set_xfer_count(len);
1704		}
1705
1706		void wd33c93_write_data(int bytes, UINT8 *pData)
1707		{
1708		UINT8 unit = wd33c93_getunit();
1709
1710		if (devices[unit].handler)
1711		{
1712		devices[unit].handler(SCSIOP_WRITE_DATA, devices[unit].data, bytes, pData);
1713		}
1714		else
1715		{
1716		logerror("wd33c93: request for unknown device SCSI ID %d\n", unit);
1717		}
1718		}
1719
1720		void *wd33c93_get_device(int id)
1721		{
1722		void *ret;
1723
1724		if (devices[id].handler)
1725		{
1726		devices[id].handler(SCSIOP_GET_DEVICE, devices[id].data, 0, (UINT8 *)&ret);
1727
1728		return ret;
1729		}
1730
1731		return NULL;
1732		}
1733
1734		void wd33c93_clear_dma(void)
1735		{
1736		/* indicate DMA completed by clearing the transfer count */
1737		wd33c93_set_xfer_count(0);
1738		scsi_data.regs[WD_AUXILIARY_STATUS] &= ~ASR_DBR;
1739		}
1740
1741		int wd33c93_get_dma_count(void)
1742		{
1743		return wd33c93_get_xfer_count();
1744		}

src/mame/machine/wd33c93.h
r949	r950
25	25	extern WRITE8_HANDLER(wd33c93_w);
26	26
27	27	#endif
28		/*
29		* wd33c93.h
30		*
31		*/
32
33		#ifndef _WD33C93_H_
34		#define _WD33C93_H_
35
36		#include "machine/scsidev.h"
37
38		struct WD33C93interface
39		{
40		SCSIConfigTable scsidevs; / SCSI devices */
41		void (irq_callback)(int state); / irq callback */
42		};
43
44		extern void wd33c93_init( struct WD33C93interface *interface );
45		extern void wd33c93_get_dma_data(int bytes, UINT8 *pData);
46		extern void wd33c93_write_data(int bytes, UINT8 *pData);
47		extern void *wd33c93_get_device(int id);
48		extern void wd33c93_set_device(int id, void *);
49		extern void wd33c93_clear_dma(void);
50		extern int wd33c93_get_dma_count(void);
51		extern READ8_HANDLER(wd33c93_r);
52		extern WRITE8_HANDLER(wd33c93_w);
53
54		#endif

src/mame/machine/cps2crpt.c
r949	r950
834	834	{ "sfzh", { 0x876b0e39,0x5ca24fd1 }, 0x080000 }, // 0C80 0564 2194 cmpi.l #$05642194,D0
835	835	{ "sfzb", { 0xef415bd3,0x7a92c680 }, 0x080000 }, // 0C80 0564 2194 cmpi.l #$05642194,D0
836	836	{ "sfzbr1", { 0xef415bd3,0x7a92c680 }, 0x080000 }, // 0C80 0564 2194 cmpi.l #$05642194,D0
837		// { "mmancp2u", { /* MISSING */ }, 0x100000 }, // 0C80 0564 2194 cmpi.l #$05642194,D0 (found in CPS1 version)
838		// { "rmancp2j", { /* MISSING */ }, 0x100000 }, // 0C80 0564 2194 cmpi.l #$05642194,D0 (found in CPS1 version)
	837	{ "mmancp2u", { 0x054893fa,0x94642525 }, 0x100000 }, // 0C80 0564 2194 cmpi.l #$05642194,D0
	838	{ "rmancp2j", { 0x07215501,0x37fa32d0 }, 0x100000 }, // 0C80 0564 2194 cmpi.l #$05642194,D0
839	839	{ "19xx", { 0x0e07181f,0x5fd0f080 }, 0x200000 }, // 0C81 0095 1101 cmpi.l #$00951101,D1
840	840	{ "19xxa", { 0xcce74cf5,0xb7da3711 }, 0x200000 }, // 0C81 0095 1101 cmpi.l #$00951101,D1
841	841	{ "19xxj", { 0x00115df8,0x000ff87e }, 0x200000 }, // 0C81 0095 1101 cmpi.l #$00951101,D1
r949	r950
919	919	{ "mvscar1", { 0xf248aec6,0x7905cd17 }, 0x100000 }, // 0C81 1972 0121 cmpi.l #$19720121,D1
920	920	{ "mvsch", { 0x9d5c7a23,0xe56b18ef }, 0x100000 }, // 0C81 1972 0121 cmpi.l #$19720121,D1
921	921	{ "mvscb", { 0x0874d6eb,0x51c2b798 }, 0x100000 }, // 0C81 1972 0121 cmpi.l #$19720121,D1
922		{ "sfa3", { 0xe7bbf0e5,0x67943248 }, 0x100000 }, // 0C80 1C62 F5A8 cmpi.l #$1C62F5A8,D0
923		{ "sfa3r1", { 0xe7bbf0e5,0x67943248 }, 0x100000 }, // 0C80 1C62 F5A8 cmpi.l #$1C62F5A8,D0
	922	{ "sfa3", { 0x6abfc8e0,0x2780ddc1 }, 0x100000 }, // 0C80 1C62 F5A8 cmpi.l #$1C62F5A8,D0
	923	{ "sfa3u", { 0xe7bbf0e5,0x67943248 }, 0x100000 }, // 0C80 1C62 F5A8 cmpi.l #$1C62F5A8,D0
	924	{ "sfa3ur1", { 0xe7bbf0e5,0x67943248 }, 0x100000 }, // 0C80 1C62 F5A8 cmpi.l #$1C62F5A8,D0
924	925	{ "sfa3b", { 0xd421c0b2,0x8116d296 }, 0x100000 }, // 0C80 1C62 F5A8 cmpi.l #$1C62F5A8,D0
925	926	{ "sfz3j", { 0x7d49f803,0x0cbe2d79 }, 0x100000 }, // 0C80 1C62 F5A8 cmpi.l #$1C62F5A8,D0
926	927	{ "sfz3jr1", { 0x7d49f803,0x0cbe2d79 }, 0x100000 }, // 0C80 1C62 F5A8 cmpi.l #$1C62F5A8,D0
r949	r950
940	941	{ "pzloop2", { 0xa054f812,0xc40d36b4 }, 0x400000 }, // 0C82 9A73 15F1 cmpi.l #$9A7315F1,D2
941	942	{ "pzloop2j", { 0xa054f812,0xc40d36b4 }, 0x400000 }, // 0C82 9A73 15F1 cmpi.l #$9A7315F1,D2
942	943	{ "choko", { 0xd3fb12c6,0x7f8e17b5 }, 0x400000 }, // 0C86 4D17 5B3C cmpi.l #$4D175B3C,D6
943		{ "dimahoo", { 0x6575af59,0xb0fea691 }, 0x080000 }, // BE4C B244 B6C5 cmp.w A4,D7 cmp.w D4,D1 cmpa.w D5,A3
	944	{ "dimahoo", { 0x0ddb8e40,0x2817fd2b }, 0x080000 }, // BE4C B244 B6C5 cmp.w A4,D7 cmp.w D4,D1 cmpa.w D5,A3
	945	{ "dimahoou", { 0x6575af59,0xb0fea691 }, 0x080000 }, // BE4C B244 B6C5 cmp.w A4,D7 cmp.w D4,D1 cmpa.w D5,A3
944	946	{ "gmahou", { 0x97f7be58,0x6121eb62 }, 0x080000 }, // BE4C B244 B6C5 cmp.w A4,D7 cmp.w D4,D1 cmpa.w D5,A3
945	947	{ "1944", { 0x1d3e724c,0x8b59fc7a }, 0x080000 }, // 0C86 7B5D 94F1 cmpi.l #$7B5D94F1,D6
946	948	{ "1944j", { 0x23d79c3a,0xe18b2746 }, 0x080000 }, // 0C86 7B5D 94F1 cmpi.l #$7B5D94F1,D6

src/mame/mamedriv.c
r949	r950
55	55	DRIVER( piranhah ) /* hack */
56	56	DRIVER( abscam ) /* hack */
57	57	DRIVER( crush ) /* (c) 1981 Kural Samno Electric Ltd */
	58	DRIVER( crushbl ) /* bootleg */
58	59	DRIVER( crush2 ) /* (c) 1981 Kural Esco Electric Ltd - bootleg? */
59	60	DRIVER( crush3 ) /* Kural Electric Ltd - bootleg? */
60	61	DRIVER( crush4 ) /* Kural TWT */
r949	r950
63	64	DRIVER( korosuke ) /* (c) 1981 Kural Electric */
64	65	DRIVER( mbrush ) /* 1981 bootleg */
65	66	DRIVER( paintrlr ) /* 1981 bootleg */
	67	DRIVER( crushs ) /* 1981 bootleg */
66	68	DRIVER( pacplus ) /* (c) 1982 Namco (Midway license) */
67	69	DRIVER( joyman ) /* hack */
68	70	DRIVER( ctrpllrp ) /* hack */
r949	r950
179	181	DRIVER( mooncrsa ) /* (c) 1980 Nichibutsu */
180	182	DRIVER( mooncrsg ) /* (c) 1980 Gremlin */
181	183	DRIVER( smooncrs ) /* Gremlin */
	184	DRIVER( mooncmw ) /* bootleg */
182	185	DRIVER( mooncrsb ) /* bootleg */
183	186	DRIVER( mooncrs2 ) /* bootleg */
184	187	DRIVER( spcdrag ) /* bootleg */
r949	r950
225	228	DRIVER( luctoday ) /* 1980 Sigma */
226	229	DRIVER( chewing ) /* ?? unknown */
227	230	DRIVER( catacomb ) /* 1982 MTM Games */
228		DRIVER( ckongg ) /* 1981 bootleg */
	231	DRIVER( ckongg ) /* 1981 bootleg */
	232	DRIVER( porter ) /* 19?? bootleg */
229	233
230	234	/* Has some similarities with Moon Cresta but Board is very different */
231	235	DRIVER( rockclim ) /* (c)1981 Taito */
r949	r950
316	320	DRIVER( imago ) /* (c) 1983 Acom */
317	321	DRIVER( scorpion ) /* (c) 1982 Zaccaria */
318	322	DRIVER( scrpiona ) /* (c) 1982 Zaccaria */
	323	DRIVER( scrpionb ) /* (c) 1982 Zaccaria */
319	324	DRIVER( ad2083 ) /* (c) 1983 Midcoin */
320	325
321	326	/* "Crazy Climber hardware" games */
r949	r950
1164	1169	DRIVER( yosakdoa ) /* (c) 1979 Yosaku To Donbei */
1165	1170	DRIVER( spceking ) /* (c) 1978 Leijac Corporation (Konami) */
1166	1171	DRIVER( spcewars ) /* (c) 1978 Sanritsu */
	1172	DRIVER( astropal ) /* (c) 19?? Sidam */
1167	1173	DRIVER( cosmo ) /* TDS+Mints */
1168	1174	DRIVER( darthvdr ) /* bootleg */
1169	1175
r949	r950
2607	2613	DRIVER( mvsch ) /* 23/01/1998 (c) 1998 (Hispanic) */
2608	2614	DRIVER( mvscb ) /* 23/01/1998 (c) 1998 (Brazil) */
2609	2615	DRIVER( sfa3 ) /* 04/09/1998 (c) 1998 (US) */
2610		DRIVER( sfa3r1 ) /* 29/06/1998 (c) 1998 (US) */
	2616	DRIVER( sfa3u ) /* 04/09/1998 (c) 1998 (US) */
	2617	DRIVER( sfa3ur1 ) /* 29/06/1998 (c) 1998 (US) */
2611	2618	DRIVER( sfa3b ) /* 29/06/1998 (c) 1998 (Brazil) */
2612	2619	DRIVER( sfz3j ) /* 04/09/1998 (c) 1998 (Japan) */
2613	2620	DRIVER( sfz3jr1 ) /* 27/07/1998 (c) 1998 (Japan) */
r949	r950
2619	2626	DRIVER( gwinga ) /* 22/02/1999 (c) 1999 Takumi (Asia) */
2620	2627	DRIVER( jyangoku ) /* 27/05/1999 (c) 1999 (Japan) */
2621	2628	DRIVER( dimahoo ) /* 21/01/2000 (c) 2000 Eighting/Raizing (US) */
	2629	DRIVER( dimahoou ) /* 21/01/2000 (c) 2000 Eighting/Raizing (US) */
2622	2630	DRIVER( gmahou ) /* 21/01/2000 (c) 2000 Eighting/Raizing (Japan) */
2623	2631	DRIVER( mmatrix ) /* 12/04/2000 (c) 2000 Takumi (US) */
2624	2632	DRIVER( mmatrixj ) /* 12/04/2000 (c) 2000 Takumi (Japan) */
r949	r950
2880	2888	DRIVER( dncfrks ) /* 2000 - Dance Freaks (G874 VER. KAA) /
2881	2889	DRIVER( dmx ) /* 2000 - Dance Maniax (G874 VER. JAA) /
2882	2890	DRIVER( gtrfrk3m ) /* 2000 - Guitar Freaks 3rd Mix (GE949 VER. JAB) */
	2891	DRIVER( gtfrk3ma ) /* 2000 - Guitar Freaks 3rd Mix - security cassette versionup (949JAZ02) */
2883	2892	DRIVER( salarymc ) /* 2000 - Salary Man Champ (GA18 VER. JAA) /
2884	2893	DRIVER( ddr3mp ) /* 2000 - Dance Dance Revolution 3rd Mix Plus (GA22 VER. JAA) /
2885	2894	DRIVER( pcnfrk3m ) /* 2000 - Percussion Freaks 3rd Mix (GA23 VER. KAA) /
r949	r950
4788	4797	DRIVER( hitnmis2 ) /* (c) 1987 */
4789	4798	DRIVER( whodunit ) /* (c) 1988 */
4790	4799	DRIVER( showdown ) /* (c) 1988 */
	4800	DRIVER( yukon ) /* (c) 1989 */
	4801	DRIVER( yukon1 ) /* (c) 1989 */
4791	4802
4792	4803	/* Exidy Max-A-Flex */
4793	4804	DRIVER( maxaflex )
r949	r950
5240	5251	/* SNK / Rock-ola games */
5241	5252	DRIVER( sasuke ) /* [1980] Shin Nihon Kikaku (SNK) */
5242	5253	DRIVER( satansat ) /* (c) 1981 SNK */
	5254	DRIVER( satansaa ) /* (c) 1981 SNK */
5243	5255	DRIVER( zarzon ) /* (c) 1981 Taito, gameplay says SNK */
5244	5256	DRIVER( vanguard ) /* (c) 1981 SNK */
5245	5257	DRIVER( vangrdce ) /* (c) 1981 SNK + Centuri */
r949	r950
6598	6610	/* R3000 + ST-0016 */
6599	6611	DRIVER( srmp5 ) /* (c) 199? Seta */
6600	6612	DRIVER( speglsht ) /* (c) 1994 Seta */
6601		DRIVER( speglsha ) /* (c) 1994 Seta */
6602	6613	/* V810 + ST-0016 */
6603	6614	DRIVER( mayjinsn ) /* (c) 1994 Seta */
6604	6615	DRIVER( mayjisn2 ) /* (c) 1994 Seta */
r949	r950
6757	6768	DRIVER( excelsr ) /* (c) 1995 */
6758	6769	DRIVER( hotmind ) /* (c) 1995 */
6759	6770	DRIVER( hrdtimes ) /* (c) 1994 */
	6771	DRIVER( hrdtimea ) /* (c) 1994 */
6760	6772	DRIVER( drtomy ) /* (c) 1993 no copyright message (1993 on pcb), some code taken from 'Big Karnak' */
6761	6773	DRIVER( sderby ) /* (c) 1996 */
6762	6774	DRIVER( pmroulet )
r949	r950
7706	7718	DRIVER( thayers ) /* (c) 1983 RDI Video Systems */
7707	7719	DRIVER( thayersa ) /* (c) 1983 RDI Video Systems */
7708	7720	DRIVER( istellar ) /* (c) 1983 Funai / Gakken */
	7721	DRIVER( comebaby ) /* (c) 2000 ExPotato */
7709	7722
7710	7723	#endif /* DRIVER_RECURSIVE */

src/mame/includes/taitoipt.h
r949	r950
377	377	#define TAITO_JOY_DUAL_UDRL(PL_L, PL_H) \
378	378	TAITO_GENERIC_JOY_DUAL_UDRL(PL_L, PL_H)
379	379
380		/*******************************************************************************
381
382		Input port macros used by many games in mutiple Taito drivers
383
384		*******************************************************************************/
385
386
387		/************************** Machine Dip Swicthes **************************/
388
389		/* with location */
390		#define TAITO_DSWA_BITS_2_TO_3_LOC(DIPBANK) \
391		PORT_SERVICE_DIPLOC( 0x04, IP_ACTIVE_LOW, #DIPBANK":3" ) \
392		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION(#DIPBANK":4") \
393		PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) \
394		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
395
396		#define TAITO_DSWA_BITS_1_TO_3_LOC(DIPBANK) \
397		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION(#DIPBANK":2") \
398		PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) \
399		PORT_DIPSETTING( 0x00, DEF_STR( On ) ) \
400		TAITO_DSWA_BITS_2_TO_3_LOC(DIPBANK)
401
402		#define TAITO_MACHINE_COCKTAIL_LOC(DIPBANK) \
403		PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION(#DIPBANK":1") \
404		PORT_DIPSETTING( 0x00, DEF_STR( Upright ) ) \
405		PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) ) \
406		TAITO_DSWA_BITS_1_TO_3_LOC(DIPBANK)
407
408		#define TAITO_MACHINE_NO_COCKTAIL_LOC(DIPBANK) \
409		PORT_DIPUNUSED_DIPLOC( 0x01, IP_ACTIVE_LOW, #DIPBANK":1" ) \
410		TAITO_DSWA_BITS_1_TO_3_LOC(DIPBANK)
411
412
413		/* without location */
414		#define TAITO_DSWA_BITS_2_TO_3 \
415		PORT_SERVICE( 0x04, IP_ACTIVE_LOW ) \
416		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) \
417		PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) \
418		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
419
420		#define TAITO_DSWA_BITS_1_TO_3 \
421		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) ) \
422		PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) \
423		PORT_DIPSETTING( 0x00, DEF_STR( On ) ) \
424		TAITO_DSWA_BITS_2_TO_3
425
426		#define TAITO_MACHINE_COCKTAIL \
427		PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) ) \
428		PORT_DIPSETTING( 0x00, DEF_STR( Upright ) ) \
429		PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) ) \
430		TAITO_DSWA_BITS_1_TO_3
431
432		#define TAITO_MACHINE_NO_COCKTAIL \
433		PORT_DIPUNUSED( 0x01, IP_ACTIVE_LOW ) \
434		TAITO_DSWA_BITS_1_TO_3
435
436
437		/************************** Coinage Dip Swicthes **************************/
438
439		/* with location */
440		#define TAITO_COINAGE_JAPAN_OLD_COIN_A_LOC(DIPBANK) \
441		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) PORT_DIPLOCATION(#DIPBANK":5,6") \
442		PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) ) \
443		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
444		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) ) \
445		PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) )
446
447		#define TAITO_COINAGE_JAPAN_OLD_COIN_B_LOC(DIPBANK) \
448		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION(#DIPBANK":7,8") \
449		PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
450		PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) ) \
451		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) ) \
452		PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )
453
454		#define TAITO_COINAGE_JAPAN_NEW_COIN_A_LOC(DIPBANK) \
455		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) PORT_DIPLOCATION(#DIPBANK":5,6") \
456		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) \
457		PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) ) \
458		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
459		PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) )
460
461		#define TAITO_COINAGE_JAPAN_NEW_COIN_B_LOC(DIPBANK) \
462		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION(#DIPBANK":7,8") \
463		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) \
464		PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
465		PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) ) \
466		PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )
467
468		#define TAITO_COINAGE_WORLD_COIN_A_LOC(DIPBANK) \
469		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) PORT_DIPLOCATION(#DIPBANK":5,6") \
470		PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) ) \
471		PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) ) \
472		PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) ) \
473		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
474
475		#define TAITO_COINAGE_WORLD_COIN_B_LOC(DIPBANK) \
476		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION(#DIPBANK":7,8") \
477		PORT_DIPSETTING( 0xc0, DEF_STR( 1C_2C ) ) \
478		PORT_DIPSETTING( 0x80, DEF_STR( 1C_3C ) ) \
479		PORT_DIPSETTING( 0x40, DEF_STR( 1C_4C ) ) \
480		PORT_DIPSETTING( 0x00, DEF_STR( 1C_6C ) )
481
482		#define TAITO_COINAGE_US_COIN_START_LOC(DIPBANK) \
483		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coinage ) ) PORT_DIPLOCATION(#DIPBANK":5,6") \
484		PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) ) \
485		PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) ) \
486		PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) ) \
487		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
488
489		#define TAITO_COINAGE_US_COIN_CONT_LOC(DIPBANK) \
490		PORT_DIPNAME( 0xc0, 0xc0, "Price to Continue" ) PORT_DIPLOCATION(#DIPBANK":7,8") \
491		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) \
492		PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
493		PORT_DIPSETTING( 0x80, DEF_STR( 1C_1C ) ) \
494		PORT_DIPSETTING( 0xc0, "Same as Start" )
495
496		#define TAITO_COINAGE_JAPAN_OLD_LOC(DIPBANK) \
497		TAITO_COINAGE_JAPAN_OLD_COIN_A_LOC(DIPBANK) \
498		TAITO_COINAGE_JAPAN_OLD_COIN_B_LOC(DIPBANK)
499
500		#define TAITO_COINAGE_JAPAN_NEW_LOC(DIPBANK) \
501		TAITO_COINAGE_JAPAN_NEW_COIN_A_LOC(DIPBANK) \
502		TAITO_COINAGE_JAPAN_NEW_COIN_B_LOC(DIPBANK)
503
504		#define TAITO_COINAGE_WORLD_LOC(DIPBANK) \
505		TAITO_COINAGE_WORLD_COIN_A_LOC(DIPBANK) \
506		TAITO_COINAGE_WORLD_COIN_B_LOC(DIPBANK)
507
508		#define TAITO_COINAGE_US_LOC(DIPBANK) \
509		TAITO_COINAGE_US_COIN_START_LOC(DIPBANK) \
510		TAITO_COINAGE_US_COIN_CONT_LOC(DIPBANK)
511
512
513		/* without location */
514		#define TAITO_COINAGE_JAPAN_OLD_COIN_A \
515		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) \
516		PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) ) \
517		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
518		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) ) \
519		PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) )
520
521		#define TAITO_COINAGE_JAPAN_OLD_COIN_B \
522		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) \
523		PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
524		PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) ) \
525		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) ) \
526		PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )
527
528		#define TAITO_COINAGE_JAPAN_NEW_COIN_A \
529		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) \
530		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) \
531		PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) ) \
532		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
533		PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) )
534
535		#define TAITO_COINAGE_JAPAN_NEW_COIN_B \
536		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) \
537		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) \
538		PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
539		PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) ) \
540		PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )
541
542		#define TAITO_COINAGE_WORLD_COIN_A \
543		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) \
544		PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) ) \
545		PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) ) \
546		PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) ) \
547		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
548
549		#define TAITO_COINAGE_WORLD_COIN_B \
550		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) \
551		PORT_DIPSETTING( 0xc0, DEF_STR( 1C_2C ) ) \
552		PORT_DIPSETTING( 0x80, DEF_STR( 1C_3C ) ) \
553		PORT_DIPSETTING( 0x40, DEF_STR( 1C_4C ) ) \
554		PORT_DIPSETTING( 0x00, DEF_STR( 1C_6C ) )
555
556		#define TAITO_COINAGE_US_COIN_START \
557		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coinage ) ) \
558		PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) ) \
559		PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) ) \
560		PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) ) \
561		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) )
562
563		#define TAITO_COINAGE_US_COIN_CONT \
564		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Continue_Price ) ) \
565		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) \
566		PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
567		PORT_DIPSETTING( 0x80, DEF_STR( 1C_1C ) ) \
568		PORT_DIPSETTING( 0xc0, "Same as Start" )
569
570		#define TAITO_COINAGE_JAPAN_OLD \
571		TAITO_COINAGE_JAPAN_OLD_COIN_A \
572		TAITO_COINAGE_JAPAN_OLD_COIN_B
573
574		#define TAITO_COINAGE_JAPAN_NEW \
575		TAITO_COINAGE_JAPAN_NEW_COIN_A \
576		TAITO_COINAGE_JAPAN_NEW_COIN_B
577
578		#define TAITO_COINAGE_WORLD \
579		TAITO_COINAGE_WORLD_COIN_A \
580		TAITO_COINAGE_WORLD_COIN_B
581
582		#define TAITO_COINAGE_US \
583		TAITO_COINAGE_US_COIN_START \
584		TAITO_COINAGE_US_COIN_CONT
585
586
587		/************************ Difficulty Dip Swicthes *************************/
588
589		/* with location */
590		#define TAITO_DIFFICULTY_LOC(DIPBANK) \
591		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION(#DIPBANK":1,2") \
592		PORT_DIPSETTING( 0x02, DEF_STR( Easy ) ) \
593		PORT_DIPSETTING( 0x03, DEF_STR( Medium ) ) \
594		PORT_DIPSETTING( 0x01, DEF_STR( Hard ) ) \
595		PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
596
597		/* without location */
598		#define TAITO_DIFFICULTY \
599		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) \
600		PORT_DIPSETTING( 0x02, DEF_STR( Easy ) ) \
601		PORT_DIPSETTING( 0x03, DEF_STR( Medium ) ) \
602		PORT_DIPSETTING( 0x01, DEF_STR( Hard ) ) \
603		PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
604
605
606		/************************ Joysticks and buttons ***************************/
607
608		/* generic (might be moved elsewhere) */
609		#define INPUT_GENERIC_JOY_LOW_NIBBLE(PL, STATE, WAY, B01, B02, B04, B08) \
610		PORT_BIT( 0x01, STATE, IPT_JOYSTICK_##B01 ) WAY PORT_PLAYER(PL) \
611		PORT_BIT( 0x02, STATE, IPT_JOYSTICK_##B02 ) WAY PORT_PLAYER(PL) \
612		PORT_BIT( 0x04, STATE, IPT_JOYSTICK_##B04 ) WAY PORT_PLAYER(PL) \
613		PORT_BIT( 0x08, STATE, IPT_JOYSTICK_##B08 ) WAY PORT_PLAYER(PL)
614
615		#define INPUT_GENERIC_JOY_HIGH_NIBBLE(PL, STATE, WAY, B10, B20, B40, B80) \
616		PORT_BIT( 0x10, STATE, IPT_JOYSTICK_##B10 ) WAY PORT_PLAYER(PL) \
617		PORT_BIT( 0x20, STATE, IPT_JOYSTICK_##B20 ) WAY PORT_PLAYER(PL) \
618		PORT_BIT( 0x40, STATE, IPT_JOYSTICK_##B40 ) WAY PORT_PLAYER(PL) \
619		PORT_BIT( 0x80, STATE, IPT_JOYSTICK_##B80 ) WAY PORT_PLAYER(PL)
620
621
622		/* Taito generic (more might be needed) */
623		#define TAITO_GENERIC_JOY_MONO_UDLR(PL) \
624		INPUT_GENERIC_JOY_LOW_NIBBLE(PL, IP_ACTIVE_LOW, PORT_8WAY, UP, DOWN, LEFT, RIGHT)
625
626		#define TAITO_GENERIC_JOY_MONO_UDRL(PL) \
627		INPUT_GENERIC_JOY_LOW_NIBBLE(PL, IP_ACTIVE_LOW, PORT_8WAY, UP, DOWN, RIGHT, LEFT)
628
629		#define TAITO_GENERIC_JOY_MONO_LRUD(PL) \
630		INPUT_GENERIC_JOY_LOW_NIBBLE(PL, IP_ACTIVE_LOW, PORT_8WAY, LEFT, RIGHT, UP, DOWN)
631
632		#define TAITO_GENERIC_JOY_DUAL_UDLR(PL_L, PL_H) \
633		INPUT_GENERIC_JOY_LOW_NIBBLE(PL_L, IP_ACTIVE_LOW, PORT_8WAY, UP, DOWN, LEFT, RIGHT) \
634		INPUT_GENERIC_JOY_HIGH_NIBBLE(PL_H, IP_ACTIVE_LOW, PORT_8WAY, UP, DOWN, LEFT, RIGHT)
635
636		#define TAITO_GENERIC_JOY_DUAL_UDRL(PL_L, PL_H) \
637		INPUT_GENERIC_JOY_LOW_NIBBLE(PL_L, IP_ACTIVE_LOW, PORT_8WAY, UP, DOWN, RIGHT, LEFT) \
638		INPUT_GENERIC_JOY_HIGH_NIBBLE(PL_H, IP_ACTIVE_LOW, PORT_8WAY, UP, DOWN, RIGHT, LEFT)
639
640
641		#define TAITO_GENERIC_BUTTONS_LOW_NIBBLE(PL, STATE, BUTTON_A, BUTTON_B, BUTTON_C) \
642		PORT_BIT( 0x01, STATE, IPT_##BUTTON_A ) PORT_PLAYER(PL) \
643		PORT_BIT( 0x02, STATE, IPT_##BUTTON_B ) PORT_PLAYER(PL) \
644		PORT_BIT( 0x04, STATE, IPT_##BUTTON_C ) PORT_PLAYER(PL)
645		/* DO NOT fill bit 3 as it may be defined as START button ! */
646
647		#define TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, STATE, BUTTON_A, BUTTON_B, BUTTON_C) \
648		PORT_BIT( 0x10, STATE, IPT_##BUTTON_A ) PORT_PLAYER(PL) \
649		PORT_BIT( 0x20, STATE, IPT_##BUTTON_B ) PORT_PLAYER(PL) \
650		PORT_BIT( 0x40, STATE, IPT_##BUTTON_C ) PORT_PLAYER(PL)
651		/* DO NOT fill bit 7 as it may be defined as START button ! */
652
653		#define TAITO_GENERIC_1_BUTTON(PL) \
654		TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, IP_ACTIVE_LOW, BUTTON1, UNKNOWN, UNKNOWN) \
655		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
656
657		#define TAITO_GENERIC_2_BUTTONS(PL) \
658		TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, IP_ACTIVE_LOW, BUTTON1, BUTTON2, UNKNOWN) \
659		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
660
661		#define TAITO_GENERIC_3_BUTTONS(PL) \
662		TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, IP_ACTIVE_LOW, BUTTON1, BUTTON2, BUTTON3) \
663		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
664
665		#define TAITO_GENERIC_1_BUTTON_START(PL) \
666		TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, IP_ACTIVE_LOW, BUTTON1, UNKNOWN, UNKNOWN) \
667		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START##PL )
668
669		#define TAITO_GENERIC_2_BUTTONS_START(PL) \
670		TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, IP_ACTIVE_LOW, BUTTON1, BUTTON2, UNKNOWN) \
671		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START##PL )
672
673		#define TAITO_GENERIC_3_BUTTONS_START(PL) \
674		TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, IP_ACTIVE_LOW, BUTTON1, BUTTON2, BUTTON3) \
675		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START##PL )
676
677
678		/* Taito games (more might be needed) */
679		#define TAITO_JOY_UDLR_1_BUTTON(PL) \
680		TAITO_GENERIC_JOY_MONO_UDLR(PL) \
681		TAITO_GENERIC_1_BUTTON(PL)
682
683		#define TAITO_JOY_UDLR_2_BUTTONS(PL) \
684		TAITO_GENERIC_JOY_MONO_UDLR(PL) \
685		TAITO_GENERIC_2_BUTTONS(PL)
686
687		#define TAITO_JOY_UDLR_3_BUTTONS(PL) \
688		TAITO_GENERIC_JOY_MONO_UDLR(PL) \
689		TAITO_GENERIC_3_BUTTONS(PL)
690
691		#define TAITO_JOY_UDRL_1_BUTTON(PL) \
692		TAITO_GENERIC_JOY_MONO_UDRL(PL) \
693		TAITO_GENERIC_1_BUTTON(PL)
694
695		#define TAITO_JOY_UDRL_2_BUTTONS(PL) \
696		TAITO_GENERIC_JOY_MONO_UDRL(PL) \
697		TAITO_GENERIC_2_BUTTONS(PL)
698
699		#define TAITO_JOY_UDRL_3_BUTTONS(PL) \
700		TAITO_GENERIC_JOY_MONO_UDRL(PL) \
701		TAITO_GENERIC_3_BUTTONS(PL)
702
703		#define TAITO_JOY_LRUD_1_BUTTON(PL) \
704		TAITO_GENERIC_JOY_MONO_LRUD(PL) \
705		TAITO_GENERIC_1_BUTTON(PL)
706
707		#define TAITO_JOY_LRUD_2_BUTTONS(PL) \
708		TAITO_GENERIC_JOY_MONO_LRUD(PL) \
709		TAITO_GENERIC_2_BUTTONS(PL)
710
711		#define TAITO_JOY_LRUD_3_BUTTONS(PL) \
712		TAITO_GENERIC_JOY_MONO_LRUD(PL) \
713		TAITO_GENERIC_3_BUTTONS(PL)
714
715
716		#define TAITO_JOY_UDLR_1_BUTTON_START(PL) \
717		TAITO_GENERIC_JOY_MONO_UDLR(PL) \
718		TAITO_GENERIC_1_BUTTON_START(PL)
719
720		#define TAITO_JOY_UDLR_2_BUTTONS_START(PL) \
721		TAITO_GENERIC_JOY_MONO_UDLR(PL) \
722		TAITO_GENERIC_2_BUTTONS_START(PL)
723
724		#define TAITO_JOY_UDLR_3_BUTTONS_START(PL) \
725		TAITO_GENERIC_JOY_MONO_UDLR(PL) \
726		TAITO_GENERIC_3_BUTTONS_START(PL)
727
728		#define TAITO_JOY_UDRL_1_BUTTON_START(PL) \
729		TAITO_GENERIC_JOY_MONO_UDRL(PL) \
730		TAITO_GENERIC_1_BUTTONS_START(PL)
731
732		#define TAITO_JOY_UDRL_2_BUTTONS_START(PL) \
733		TAITO_GENERIC_JOY_MONO_UDRL(PL) \
734		TAITO_GENERIC_2_BUTTONS_START(PL)
735
736		#define TAITO_JOY_UDRL_3_BUTTONS_START(PL) \
737		TAITO_GENERIC_JOY_MONO_UDRL(PL) \
738		TAITO_GENERIC_3_BUTTONS_START(PL)
739
740		#define TAITO_JOY_LRUD_1_BUTTON_START(PL) \
741		TAITO_GENERIC_JOY_MONO_LRUD(PL) \
742		TAITO_GENERIC_1_BUTTON_START(PL)
743
744		#define TAITO_JOY_LRUD_2_BUTTONS_START(PL) \
745		TAITO_GENERIC_JOY_MONO_LRUD(PL) \
746		TAITO_GENERIC_2_BUTTONS_START(PL)
747
748		#define TAITO_JOY_LRUD_3_BUTTONS_START(PL) \
749		TAITO_GENERIC_JOY_MONO_LRUD(PL) \
750		TAITO_GENERIC_3_BUTTONS_START(PL)
751
752
753		#define TAITO_JOY_DUAL_UDLR(PL_L, PL_H) \
754		TAITO_GENERIC_JOY_DUAL_UDLR(PL_L, PL_H)
755
756		#define TAITO_JOY_DUAL_UDRL(PL_L, PL_H) \
757		TAITO_GENERIC_JOY_DUAL_UDRL(PL_L, PL_H)
758

src/mame/includes/m92.h
r949	r950
23	23
24	24	VIDEO_START( m92 );
25	25	VIDEO_UPDATE( m92 );
26		/*************************************************************************
27
28		Irem M92 hardware
29
30		*************************************************************************/
31
32		/----------- defined in video/m92.c -----------/
33
34		extern int m92_raster_irq_position, m92_raster_enable;
35		extern UINT16 m92_vram_data, m92_spritecontrol;
36
37		extern UINT8 m92_sprite_buffer_busy, m92_game_kludge;
38
39		WRITE16_HANDLER( m92_spritecontrol_w );
40		WRITE16_HANDLER( m92_videocontrol_w );
41		READ16_HANDLER( m92_paletteram_r );
42		WRITE16_HANDLER( m92_paletteram_w );
43		WRITE16_HANDLER( m92_vram_w );
44		WRITE16_HANDLER( m92_pf1_control_w );
45		WRITE16_HANDLER( m92_pf2_control_w );
46		WRITE16_HANDLER( m92_pf3_control_w );
47		WRITE16_HANDLER( m92_master_control_w );
48
49		VIDEO_START( m92 );
50		VIDEO_UPDATE( m92 );

src/mame/includes/exidy440.h
r949	r950
27	27
28	28	/----------- defined in drivers/exidy440.c -----------/
29	29
30		extern UINT8 exidy440_bank;
31	30	extern UINT8 exidy440_topsecret;
	31	void exidy440_bank_select(UINT8 bank);
32	32
33	33
	34
34	35	/----------- defined in audio/exidy440.c -----------/
35	36
36	37	extern UINT8 exidy440_sound_command;

src/mame/includes/m107.h
r949	r950
17	17	VIDEO_START( m107 );
18	18	WRITE16_HANDLER( m107_control_w );
19	19	WRITE16_HANDLER( m107_vram_w );
20		/*************************************************************************
21
22		Irem M107 hardware
23
24		*************************************************************************/
25
26
27		/----------- defined in video/m107.c -----------/
28
29		extern UINT16 *m107_vram_data;
30		extern UINT8 m107_spritesystem;
31		extern UINT16 m107_raster_irq_position;
32
33		WRITE16_HANDLER( m107_spritebuffer_w );
34		VIDEO_UPDATE( m107 );
35		VIDEO_UPDATE( dsoccr );
36		VIDEO_START( m107 );
37		WRITE16_HANDLER( m107_control_w );
38		WRITE16_HANDLER( m107_vram_w );

src/mame/includes/m72.h
r949	r950
38	38
39	39	VIDEO_UPDATE( m72 );
40	40	VIDEO_UPDATE( majtitle );
41		/*************************************************************************
42
43		Irem M72 hardware
44
45		*************************************************************************/
46
47		/----------- defined in video/m72.c -----------/
48
49		extern UINT16 m72_videoram1,m72_videoram2,*majtitle_rowscrollram;
50
51		MACHINE_RESET( m72 );
52		MACHINE_RESET( xmultipl );
53		MACHINE_RESET( kengo );
54
55		INTERRUPT_GEN( m72_interrupt );
56
57		VIDEO_START( m72 );
58		VIDEO_START( rtype2 );
59		VIDEO_START( majtitle );
60		VIDEO_START( hharry );
61		VIDEO_START( poundfor );
62
63		READ16_HANDLER( m72_palette1_r );
64		READ16_HANDLER( m72_palette2_r );
65		WRITE16_HANDLER( m72_palette1_w );
66		WRITE16_HANDLER( m72_palette2_w );
67		WRITE16_HANDLER( m72_videoram1_w );
68		WRITE16_HANDLER( m72_videoram2_w );
69		WRITE16_HANDLER( m72_irq_line_w );
70		WRITE16_HANDLER( m72_scrollx1_w );
71		WRITE16_HANDLER( m72_scrollx2_w );
72		WRITE16_HANDLER( m72_scrolly1_w );
73		WRITE16_HANDLER( m72_scrolly2_w );
74		WRITE16_HANDLER( m72_dmaon_w );
75		WRITE16_HANDLER( m72_port02_w );
76		WRITE16_HANDLER( rtype2_port02_w );
77		WRITE16_HANDLER( majtitle_gfx_ctrl_w );
78
79		VIDEO_UPDATE( m72 );
80		VIDEO_UPDATE( majtitle );

src/mame/mame.mak
r949	r950
1542	1542	$(DRIVERS)/cherrym.o \
1543	1543	$(DRIVERS)/cidelsa.o $(VIDEO)/cdp1869.o \
1544	1544	$(DRIVERS)/coinmstr.o \
	1545	$(DRIVERS)/comebaby.o \
1545	1546	$(DRIVERS)/coolpool.o \
1546	1547	$(DRIVERS)/cowrace.o \
1547	1548	$(DRIVERS)/crystal.o $(MACHINE)/ds1302.o $(VIDEO)/vrender0.o \

src/mame/video/tunhunt.c
r949	r950
237	237	if( span_data == 0xff ) break;
238	238	color = ((span_data>>6)&0x3)^0x3;
239	239	count = (span_data&0x1f)+1;
240		while( count-- )
	240	while( count-- && x < 256 )
241	241	{
242	242	*BITMAP_ADDR16(tmpbitmap, line, x++) = machine->pens[color];
243	243	}
r949	r950
307	307
308	308	for( y=0; y<256; y++ )
309	309	{
310		for( x=0; x<256; x++ )
311		{
312		color = 0;
313		z = 0;
314		for( span=3; span<16; span++ )
	310	if (0xff-y >= cliprect->min_y && 0xff-y <= cliprect->max_y)
	311	for( x=0; x<256; x++ )
315	312	{
316		x0 = tunhunt_ram[span+0x1080];
317		y0 = tunhunt_ram[span+0x1480];
318		y1 = tunhunt_ram[span+0x1400];
	313	color = 0;
	314	z = 0;
	315	for( span=3; span<16; span++ )
	316	{
	317	x0 = tunhunt_ram[span+0x1080];
	318	y0 = tunhunt_ram[span+0x1480];
	319	y1 = tunhunt_ram[span+0x1400];
319	320
320		if( y>=y0 && y<=y1 && x>=x0 && x0>=z )
321		{
322		color = tunhunt_ram[span+0x1280]&0xf;
323		z = x0; /* give priority to rightmost spans */
	321	if( y>=y0 && y<=y1 && x>=x0 && x0>=z )
	322	{
	323	color = tunhunt_ram[span+0x1280]&0xf;
	324	z = x0; /* give priority to rightmost spans */
	325	}
324	326	}
	327	if (x >= cliprect->min_x && x <= cliprect->max_x)
	328	*BITMAP_ADDR16(bitmap, 0xff-y, x) = machine->pens[color];
325	329	}
326		*BITMAP_ADDR16(bitmap, 0xff-y, x) = machine->pens[color];
327		}
328	330	}
329	331	}
330	332

src/mame/video/cclimber.c
r949	r950
659	659	/* bg gradient */
660	660	fillbitmap(bitmap, 0, cliprect);
661	661
662		for(i=0;i<256;i++)
	662	for(i=8;i<256;i++)
663	663	{
664	664	pen_t pen = 164+84 + memory_region(REGION_USER1)[(flip_screen_x?0x1280:0x1200)+(i>>1)];
665	665

src/mame/video/namcona1.c
r949	r950
249	249
250	250	static void pdraw_masked_tile(running_machine *machine,
251	251	mame_bitmap *bitmap,
	252	const rectangle *cliprect,
252	253	unsigned code,
253	254	int color,
254	255	int sx, int sy,
r949	r950
266	267
267	268	/*
268	269	* custom blitter for drawing a masked 8x8x8BPP tile
269		* - assumes there is an 8 pixel overdraw region on the screen bitmap for clipping
270	270	*/
271		if( sx > -8 &&
272		sy > -8 &&
273		sx < bitmap->width &&
274		sy < bitmap->height ) /* all-or-nothing clip */
	271	if( sx > cliprect->min_x-8 &&
	272	sy > cliprect->min_y-8 &&
	273	sx <= cliprect->max_x &&
	274	sy <= cliprect->max_y ) /* all-or-nothing clip */
275	275	{
276	276	gfx = machine->gfx[0];
277	277	mask = machine->gfx[1];
r949	r950
292	292	for( y=0; y<8; y++ )
293	293	{
294	294	int ypos = sy+(flipy?7-y:y);
295		UINT8 *pri = BITMAP_ADDR8(priority_bitmap, ypos, 0);
296		UINT16 *dest = BITMAP_ADDR16(bitmap, ypos, 0);
297		if( flipx )
	295	if (ypos >= cliprect->min_y && ypos <= cliprect->max_y)
298	296	{
299		dest += sx+7;
300		pri += sx+7;
301		for( x=0; x<8; x++ )
	297	UINT8 *pri = BITMAP_ADDR8(priority_bitmap, ypos, 0);
	298	UINT16 *dest = BITMAP_ADDR16(bitmap, ypos, 0);
	299	if( flipx )
302	300	{
303		if( mask_addr[x] )
304		{ /* sprite pixel is opaque */
305		if( priority>=pri[-x] )
	301	dest += sx+7;
	302	pri += sx+7;
	303	for( x=0; x<8; x++ )
	304	if (sx+x >= cliprect->min_x && sx+x <= cliprect->max_x)
306	305	{
307		dest[-x] \|= 0x1000;
	306	if( mask_addr[x] )
	307	{ /* sprite pixel is opaque */
	308	if( priority>=pri[-x] )
	309	{
	310	dest[-x] \|= 0x1000;
	311	}
	312	pri[-x] = 0xff;
	313	}
308	314	}
309		pri[-x] = 0xff;
310		}
311	315	}
312		}
313		else
314		{
315		dest += sx;
316		pri += sx;
317		for( x=0; x<8; x++ )
	316	else
318	317	{
319		if( mask_addr[x] )
320		{ /* sprite pixel is opaque */
321		if( priority>=pri[x] )
	318	dest += sx;
	319	pri += sx;
	320	for( x=0; x<8; x++ )
	321	if (sx+x >= cliprect->min_x && sx+x <= cliprect->max_x)
322	322	{
323		dest[x] \|= 0x1000;
	323	if( mask_addr[x] )
	324	{ /* sprite pixel is opaque */
	325	if( priority>=pri[x] )
	326	{
	327	dest[x] \|= 0x1000;
	328	}
	329	pri[x] = 0xff;
	330	}
324	331	}
325		pri[x] = 0xff;
326		}
327	332	}
328	333	}
329	334	mask_addr += mask_pitch;
r949	r950
334	339	for( y=0; y<8; y++ )
335	340	{
336	341	int ypos = sy+(flipy?7-y:y);
337		UINT8 *pri = BITMAP_ADDR8(priority_bitmap, ypos, 0);
338		UINT16 *dest = BITMAP_ADDR16(bitmap, ypos, 0);
339		if( flipx )
	342	if (ypos >= cliprect->min_y && ypos <= cliprect->max_y)
340	343	{
341		dest += sx+7;
342		pri += sx+7;
343		for( x=0; x<8; x++ )
	344	UINT8 *pri = BITMAP_ADDR8(priority_bitmap, ypos, 0);
	345	UINT16 *dest = BITMAP_ADDR16(bitmap, ypos, 0);
	346	if( flipx )
344	347	{
345		if( mask_addr[x] )
346		{ /* sprite pixel is opaque */
347		if( priority>=pri[-x] )
	348	dest += sx+7;
	349	pri += sx+7;
	350	for( x=0; x<8; x++ )
	351	if (sx-x >= cliprect->min_x && sx-x <= cliprect->max_x)
348	352	{
349		dest[-x] = paldata[gfx_addr[x]];
	353	if( mask_addr[x] )
	354	{ /* sprite pixel is opaque */
	355	if( priority>=pri[-x] )
	356	{
	357	dest[-x] = paldata[gfx_addr[x]];
	358	}
	359	pri[-x] = 0xff;
	360	}
350	361	}
351		pri[-x] = 0xff;
352		}
353	362	}
354		}
355		else
356		{
357		dest += sx;
358		pri += sx;
359		for( x=0; x<8; x++ )
	363	else
360	364	{
361		if( mask_addr[x] )
362		{ /* sprite pixel is opaque */
363		if( priority>=pri[x] )
	365	dest += sx;
	366	pri += sx;
	367	for( x=0; x<8; x++ )
	368	if (sx+x >= cliprect->min_x && sx+x <= cliprect->max_x)
364	369	{
365		dest[x] = paldata[gfx_addr[x]];
366		}
367		pri[x] = 0xff;
368		}
369		} /* next x */
370		} /* !flipx */
	370	if( mask_addr[x] )
	371	{ /* sprite pixel is opaque */
	372	if( priority>=pri[x] )
	373	{
	374	dest[x] = paldata[gfx_addr[x]];
	375	}
	376	pri[x] = 0xff;
	377	}
	378	} /* next x */
	379	} /* !flipx */
	380	}
371	381	gfx_addr += gfx_pitch;
372	382	mask_addr += mask_pitch;
373	383	} /* next y */
r949	r950
377	387
378	388	static void pdraw_opaque_tile(running_machine *machine,
379	389	mame_bitmap *bitmap,
	390	const rectangle *cliprect,
380	391	unsigned code,
381	392	int color,
382	393	int sx, int sy,
r949	r950
393	404	UINT8 *pri;
394	405	UINT16 *dest;
395	406
396		if( sx > -8 &&
397		sy > -8 &&
398		sx < bitmap->width &&
399		sy < bitmap->height ) /* all-or-nothing clip */
	407	if( sx > cliprect->min_x-8 &&
	408	sy > cliprect->min_y-8 &&
	409	sx <= cliprect->max_x &&
	410	sy <= cliprect->max_y ) /* all-or-nothing clip */
400	411	{
401	412	gfx = machine->gfx[0];
402	413	code %= gfx->total_elements;
r949	r950
408	419	for( y=0; y<8; y++ )
409	420	{
410	421	ypos = sy+(flipy?7-y:y);
411		pri = BITMAP_ADDR8(priority_bitmap, ypos, 0);
412		dest = BITMAP_ADDR16(bitmap, ypos, 0);
413		if( flipx )
	422	if (ypos >= cliprect->min_y && ypos <= cliprect->max_y)
414	423	{
415		dest += sx+7;
416		pri += sx+7;
417		for( x=0; x<8; x++ )
	424	pri = BITMAP_ADDR8(priority_bitmap, ypos, 0);
	425	dest = BITMAP_ADDR16(bitmap, ypos, 0);
	426	if( flipx )
418	427	{
419		if( priority>=pri[-x] )
420		{
421		dest[-x] = paldata[gfx_addr[x]];
422		}
423		pri[-x] = 0xff;
	428	dest += sx+7;
	429	pri += sx+7;
	430	for( x=0; x<8; x++ )
	431	if (sx-x >= cliprect->min_x && sx-x <= cliprect->max_x)
	432	{
	433	if( priority>=pri[-x] )
	434	{
	435	dest[-x] = paldata[gfx_addr[x]];
	436	}
	437	pri[-x] = 0xff;
	438	}
424	439	}
	440	else
	441	{
	442	dest += sx;
	443	pri += sx;
	444	for( x=0; x<8; x++ )
	445	if (sx+x >= cliprect->min_x && sx+x <= cliprect->max_x)
	446	{
	447	if( priority>=pri[x] )
	448	{
	449	dest[x] = paldata[gfx_addr[x]];
	450	}
	451	pri[x] = 0xff;
	452	} /* next x */
	453	} /* !flipx */
425	454	}
426		else
427		{
428		dest += sx;
429		pri += sx;
430		for( x=0; x<8; x++ )
431		{
432		if( priority>=pri[x] )
433		{
434		dest[x] = paldata[gfx_addr[x]];
435		}
436		pri[x] = 0xff;
437		} /* next x */
438		} /* !flipx */
439	455	gfx_addr += gfx_pitch;
440	456	} /* next y */
441	457	}
r949	r950
443	459
444	460	static const UINT8 pri_mask[8] = { 0x00,0x01,0x03,0x07,0x0f,0x1f,0x3f,0x7f };
445	461
446		static void draw_sprites(running_machine machine, mame_bitmap bitmap )
	462	static void draw_sprites(running_machine machine, mame_bitmap bitmap, const rectangle *cliprect)
447	463	{
448	464	int which;
449	465	const UINT16 *source = spriteram16;
450	466	void (drawtile)(running_machine ,
451	467	mame_bitmap *,
	468	const rectangle *,
452	469	unsigned code,
453	470	int color,
454	471	int sx, int sy,
r949	r950
511	528	}
512	529	drawtile(machine,
513	530	bitmap,
	531	cliprect,
514	532	tile + row*64+col,
515	533	(color>>4)&0xf,
516	534	((sx+16)&0x1ff)-8,
r949	r950
643	661	}
644	662	} /* next tilemap */
645	663	} /* next priority level */
646		draw_sprites(machine,bitmap );
	664	draw_sprites(machine,bitmap,cliprect);
647	665	} /* gfx enabled */
648	666	return 0;
649	667	}

src/mame/video/model1.c
r949	r950
449	449	{
450	450	int count = quadpt - quaddb;
451	451	int i;
	452
	453	/* clip to the cliprect */
	454	int save_x1 = view.x1;
	455	int save_x2 = view.x2;
	456	int save_y1 = view.y1;
	457	int save_y2 = view.y2;
	458	view.x1 = MAX(view.x1, cliprect->min_x);
	459	view.x2 = MIN(view.x2, cliprect->max_x);
	460	view.y1 = MAX(view.y1, cliprect->min_y);
	461	view.y2 = MIN(view.y2, cliprect->max_y);
	462
452	463	for(i=0; i<count; i++) {
453	464	struct quad *q = quadind[i];
454	465
r949	r950
460	471	draw_line(bitmap, get_black_pen(machine), q->p[3]->s.x, q->p[3]->s.y, q->p[0]->s.x, q->p[0]->s.y);
461	472	#endif
462	473	}
	474
	475	view.x1 = save_x1;
	476	view.x2 = save_x2;
	477	view.y1 = save_y1;
	478	view.y2 = save_y2;
463	479	}
464	480	#if 0
465	481	static UINT16 scale_color(UINT16 color, float level)
r949	r950
1493	1509	ayyc = cos(ayy);
1494	1510	ayys = sin(ayy);
1495	1511
1496		fillbitmap(priority_bitmap, 0, 0);
	1512	fillbitmap(priority_bitmap, 0, NULL);
1497	1513	fillbitmap(bitmap, machine->pens[0], &machine->screen[0].visarea);
1498	1514
1499	1515	sys24_tile_draw(machine, bitmap, cliprect, 6, 0, 0);

src/mame/video/gaelco3d.c
r949	r950
191	191
192	192	/* compute the adjusted clip */
193	193	clip.min_x = Machine->screen[0].visarea.min_x - midx;
194		clip.min_y = Machine->screen[0].visarea.min_~~y - mid~~y;
	194	clip.min_y = midy - Machine->screen[0].visarea.max_y;
195	195	clip.max_x = Machine->screen[0].visarea.max_x - midx;
196		clip.max_y = Machine->screen[0].visarea.m~~ax_y - m~~idy;
	196	clip.max_y = midy - Machine->screen[0].visarea.min_y;
197	197
198	198	/* extract the first two vertices */
199	199	vert[0].x = (((INT32)polydata[13] >> 16) + (GAELCO3D_RESOLUTION_DIVIDE/2)) / GAELCO3D_RESOLUTION_DIVIDE;
r949	r950
234	234	{
235	235	const struct poly_scanline *scan = &scans->scanline[y - scans->sy];
236	236	UINT16 *dest = BITMAP_ADDR16(screenbits, midy - y, midx);
237		UINT16 *zbuf = BITMAP_ADDR16(zbuffer, midy - y, 0);
	237	UINT16 *zbuf = BITMAP_ADDR16(zbuffer, midy - y, midx);
238	238	float uoz = (uoz_dy * y + scan->sx * uoz_dx + uoz_base) * zbase;
239	239	float voz = (voz_dy * y + scan->sx * voz_dx + voz_base) * zbase;
240	240
r949	r950
288	288	{
289	289	const struct poly_scanline *scan = &scans->scanline[y - scans->sy];
290	290	UINT16 *dest = BITMAP_ADDR16(screenbits, midy - y, midx);
291		UINT16 *zbuf = BITMAP_ADDR16(zbuffer, midy - y, 0);
	291	UINT16 *zbuf = BITMAP_ADDR16(zbuffer, midy - y, midx);
292	292	float ooz = ooz_dy * y + scan->sx * ooz_dx + ooz_base;
293	293	float uoz = uoz_dy * y + scan->sx * uoz_dx + uoz_base;
294	294	float voz = voz_dy * y + scan->sx * voz_dx + voz_base;
r949	r950
354	354	{
355	355	const struct poly_scanline *scan = &scans->scanline[y - scans->sy];
356	356	UINT16 *dest = BITMAP_ADDR16(screenbits, midy - y, midx);
357		UINT16 *zbuf = BITMAP_ADDR16(zbuffer, midy - y, 0);
	357	UINT16 *zbuf = BITMAP_ADDR16(zbuffer, midy - y, midx);
358	358	float ooz = ooz_dy * y + scan->sx * ooz_dx + ooz_base;
359	359	float uoz = uoz_dy * y + scan->sx * uoz_dx + uoz_base;
360	360	float voz = voz_dy * y + scan->sx * voz_dx + voz_base;

src/mame/video/tmnt.c
r949	r950
693	693	if (layerpri[0] >= 0x30 && layerpri[1] < 0x30)
694	694	{
695	695	K053936_0_zoom_draw(bitmap,cliprect,roz_tilemap,0,1);
696		glfgreat_pixel = *BITMAP_ADDR16(bitmap,0x105,0x80);
	696	glfgreat_pixel = *BITMAP_ADDR16(bitmap,0x80,0x105);
697	697	}
698	698	tilemap_draw(bitmap,cliprect,K052109_tilemap[sorted_layer[1]],0,2);
699	699	if (layerpri[1] >= 0x30 && layerpri[2] < 0x30)
700	700	{
701	701	K053936_0_zoom_draw(bitmap,cliprect,roz_tilemap,0,1);
702		glfgreat_pixel = *BITMAP_ADDR16(bitmap,0x105,0x80);
	702	glfgreat_pixel = *BITMAP_ADDR16(bitmap,0x80,0x105);
703	703	}
704	704	tilemap_draw(bitmap,cliprect,K052109_tilemap[sorted_layer[2]],0,4);
705	705	if (layerpri[2] >= 0x30)
706	706	{
707	707	K053936_0_zoom_draw(bitmap,cliprect,roz_tilemap,0,1);
708		glfgreat_pixel = *BITMAP_ADDR16(bitmap,0x105,0x80);
	708	glfgreat_pixel = *BITMAP_ADDR16(bitmap,0x80,0x105);
709	709	}
710	710
711	711	K053245_sprites_draw(0, bitmap,cliprect);

src/mame/video/bfm_adr2.c
r949	r950
212	212	}
213	213
214	214	// video update ///////////////////////////////////////////////////////////
215		static rectangle visible1 = { 0, 400, 0, 280 }; //minx,maxx, miny,maxy
	215	static rectangle visible1 = { 0, 400-1, 0, 280-1 }; //minx,maxx, miny,maxy
216	216
217	217	VIDEO_UPDATE( adder2 )
218	218	{

src/mame/video/deco16ic.c
r949	r950
863	863	UINT8 *pri = BITMAP_ADDR8(priority_bitmap, sy, 0);
864	864	UINT8 *spri = BITMAP_ADDR8(sprite_priority_bitmap, sy, 0);
865	865
866		if (flipx) { source+=15-(sx-ox); x_index=-1; } else { x_index=1; source+=(sx-ox); }
	866	if (sy >= 0 && sy < 248)
	867	{
	868	if (flipx) { source+=15-(sx-ox); x_index=-1; } else { x_index=1; source+=(sx-ox); }
867	869
868		for (x=sx; x<cx; x++)
869		{
870		int c = *source;
871		if( c != transparent_color )
	870	for (x=sx; x<cx; x++)
872	871	{
873		if (pri_mask>pri[x] && sprite_mask>spri[x]) {
874		if (transparency == TRANSPARENCY_ALPHA)
875		destb[x] = alpha_blend32(destb[x], pal[c]);
876		else
877		destb[x] = pal[c];
878		if (write_pri)
879		pri[x] \|= pri_mask;
	872	int c = *source;
	873	if( c != transparent_color && x >= 0 && x < 320 )
	874	{
	875	if (pri_mask>pri[x] && sprite_mask>spri[x]) {
	876	if (transparency == TRANSPARENCY_ALPHA)
	877	destb[x] = alpha_blend32(destb[x], pal[c]);
	878	else
	879	destb[x] = pal[c];
	880	if (write_pri)
	881	pri[x] \|= pri_mask;
	882	}
	883	spri[x]\|=sprite_mask;
880	884	}
881		spr~~i[x]\|~~=~~spr~~ite~~_mask~~;
	885	source+=x_index;
882	886	}
883		source+=x_index;
884	887	}
885	888
886	889	sy++;

src/mame/video/pacland.c
r949	r950
29	29
30	30	UINT8 pacland_videoram,pacland_videoram2,*pacland_spriteram;
31	31
32		static ~~int~~ palette_bank;
	32	static UINT8 palette_bank;
33	33	static const UINT8 *pacland_color_prom;
34	34
35	35	static colortable *pacland_colortable;
36	36	static tilemap bg_tilemap, fg_tilemap;
37		static mame_bitmap sprite_bitmap,fg_bitmap;
	37	static mame_bitmap *fg_bitmap;
38	38
39		static ~~int~~ scr~~oll0,~~s~~croll1~~;
	39	static UINT32 *transmask[3];
40	40
	41	static UINT16 scroll0,scroll1;
	42
41	43	/***************************************************************************
42	44
43	45	Convert the color PROMs.
r949	r950
109	111	color_prom += 2 * 0x400;
110	112	/* color_prom now points to the beginning of the lookup table */
111	113
112		/* Foreground */
113	114	for (i = 0;i < 0x400;i++)
114	115	colortable_entry_set_value(pacland_colortable, machine->gfx[0]->color_base + i, *color_prom++);
115	116
r949	r950
119	120
120	121	/* Sprites */
121	122	for (i = 0;i < 0x400;i++)
122		{
123		colortable_entry_set_value(pacland_colortable, machine->gfx[2]->color_base + i, *color_prom);
124		colortable_entry_set_value(pacland_colortable, machine->gfx[2]->color_base + i + 0x400, (*color_prom++ < 0x80) ? 0x7f : 0xff); // for high priority mask (round 19)
125		}
	123	colortable_entry_set_value(pacland_colortable, machine->gfx[2]->color_base + i, *color_prom++);
126	124
127	125	palette_bank = 0;
128	126	switch_palette(machine);
	127
	128	/* precalculate transparency masks for sprites */
	129	transmask[0] = auto_malloc(64 * sizeof(transmask[0][0]));
	130	transmask[1] = auto_malloc(64 * sizeof(transmask[0][0]));
	131	transmask[2] = auto_malloc(64 * sizeof(transmask[0][0]));
	132	for (i = 0; i < 64; i++)
	133	{
	134	int palentry;
	135
	136	/* start with no transparency */
	137	transmask[0][i] = transmask[1][i] = transmask[2][i] = 0;
	138
	139	/* iterate over all palette entries except the last one */
	140	for (palentry = 0; palentry < 0x100; palentry++)
	141	{
	142	UINT32 mask = colortable_get_transpen_mask(pacland_colortable, machine->gfx[2], i, palentry);
	143
	144	/* transmask[0] is a mask that is used to draw only high priority sprite pixels; thus, pens
	145	$00-$7F are opaque, and others are transparent */
	146	if (palentry >= 0x80)
	147	transmask[0][i] \|= mask;
	148
	149	/* transmask[1] is a normal drawing masking with palette entries $7F and $FF transparent */
	150	if ((palentry & 0x7f) == 0x7f)
	151	transmask[1][i] \|= mask;
	152
	153	/* transmask[2] is a mask of the topmost priority sprite pixels; thus pens $F0-$FE are
	154	opaque, and others are transparent */
	155	if (palentry < 0xf0 \|\| palentry == 0xff)
	156	transmask[2][i] \|= mask;
	157	}
	158	}
129	159	}
130	160
131	161
r949	r950
171	201
172	202	VIDEO_START( pacland )
173	203	{
	204	int color;
	205
174	206	fg_bitmap = auto_bitmap_alloc(machine->screen[0].width,machine->screen[0].height,machine->screen[0].format);
175		~~spr~~i~~te_~~bitmap ~~= auto~~_bitmap~~_alloc(machine->screen[0].width~~,~~machine->screen[~~0~~].height,machine->screen[0].~~f~~ormat~~);
	207	fillbitmap(fg_bitmap, 0xffff, NULL);
176	208
177	209	bg_tilemap = tilemap_create(get_bg_tile_info,tilemap_scan_rows,TILEMAP_TYPE_PEN,8,8,64,32);
178	210	fg_tilemap = tilemap_create(get_fg_tile_info,tilemap_scan_rows,TILEMAP_TYPE_PEN,8,8,64,32);
179	211
180	212	tilemap_set_scroll_rows(fg_tilemap, 32);
181		colortable_configure_tilemap_groups(pacland_colortable, fg_tilemap, machine->gfx[0], 0xff);
182	213
	214	/* create one group per color code; for each group, set the transparency mask
	215	to correspond to the pens that are 0x7f or 0xff */
	216	assert(machine->gfx[0]->total_colors <= TILEMAP_NUM_GROUPS);
	217	for (color = 0; color < machine->gfx[0]->total_colors; color++)
	218	{
	219	UINT32 mask = colortable_get_transpen_mask(pacland_colortable, machine->gfx[0], color, 0x7f);
	220	mask \|= colortable_get_transpen_mask(pacland_colortable, machine->gfx[0], color, 0xff);
	221	tilemap_set_transmask(fg_tilemap, color, mask, 0);
	222	}
	223
183	224	spriteram = pacland_spriteram + 0x780;
184	225	spriteram_2 = spriteram + 0x800;
185	226	spriteram_3 = spriteram_2 + 0x800;
	227
	228	state_save_register_global(palette_bank);
	229	state_save_register_global(scroll0);
	230	state_save_register_global(scroll1);
186	231	}
187	232
188	233
r949	r950
241	286	***************************************************************************/
242	287
243	288	/* the sprite generator IC is the same as Mappy */
244		static void draw_sprites(running_machine machine, mame_bitmap bitmap, const rectangle *cliprect, int ~~dra~~w_mask )
	289	static void draw_sprites(running_machine machine, mame_bitmap bitmap, const rectangle *cliprect, int whichmask)
245	290	{
246	291	int offs;
247	292
r949	r950
253	298	{ 2, 3 }
254	299	};
255	300	int sprite = spriteram[offs] + ((spriteram_3[offs] & 0x80) << 1);
256		int color = (spriteram[offs+1] & 0x3f~~) + draw_mask * 64~~;
	301	int color = spriteram[offs+1] & 0x3f;
257	302	int sx = (spriteram_2[offs+1]) + 0x100*(spriteram_3[offs+1] & 1) - 47;
258	303	int sy = 256 - spriteram_2[offs] + 9;
259	304	int flipx = (spriteram_3[offs] & 0x01);
r949	r950
278	323	{
279	324	for (x = 0;x <= sizex;x++)
280	325	{
281		drawgfx(bitmap,machine->gfx[2],
282		sprite + gfx_offs[y ^ (sizey * flipy)][x ^ (sizex * flipx)],
283		color,
284		flipx,flipy,
285		sx + 16x,sy + 16y,
286		cliprect,TRANSPARENCY_PENS,
287		colortable_get_transpen_mask(pacland_colortable, machine->gfx[2], color, 0xff));
	326	if (whichmask != 0)
	327	drawgfx(bitmap,machine->gfx[2],
	328	sprite + gfx_offs[y ^ (sizey * flipy)][x ^ (sizex * flipx)],
	329	color,
	330	flipx,flipy,
	331	sx + 16x,sy + 16y,
	332	cliprect,TRANSPARENCY_PENS,transmask[whichmask][color]);
	333	else
	334	pdrawgfx(bitmap,machine->gfx[2],
	335	sprite + gfx_offs[y ^ (sizey * flipy)][x ^ (sizex * flipx)],
	336	color,
	337	flipx,flipy,
	338	sx + 16x,sy + 16y,
	339	cliprect,TRANSPARENCY_PENS,transmask[whichmask][color],0);
288	340	}
289	341	}
290	342	}
291	343	}
292	344
293	345
294		static void draw_fg(~~running_machine machine,~~ mame_bitmap bitmap, const rectangle *cliprect, int priority )
	346	static void draw_fg(mame_bitmap bitmap, const rectangle cliprect, int priority )
295	347	{
296		/* clear temp bitmap using color 0x7f */
297		fillbitmap(fg_bitmap, 0x7f, cliprect);
	348	int y, x;
298	349
299		/* draw tilemap over it (transparent color is 0xff) */
	350	/* draw tilemap transparently over it; this will leave invalid pens (0xffff)
	351	anywhere where the fg_tilemap should be transparent; note that we assume
	352	the fg_bitmap has been pre-erased to 0xffff */
300	353	tilemap_draw(fg_bitmap, cliprect, fg_tilemap, priority, 0);
301	354
302		/* draw sprite high priority mask (color 0x7f) over it */
303		draw_sprites(machine, fg_bitmap, cliprect, 1);
	355	/* now copy the fg_bitmap to the destination wherever the sprite pixel allows */
	356	for (y = cliprect->min_y; y <= cliprect->max_y; y++)
	357	{
	358	const UINT8 *pri = BITMAP_ADDR8(priority_bitmap, y, 0);
	359	UINT16 *src = BITMAP_ADDR16(fg_bitmap, y, 0);
	360	UINT16 *dst = BITMAP_ADDR16(bitmap, y, 0);
304	361
305		/* copy temp bitmap to the screen (transparent color is 0x7f) */
306		copybitmap(bitmap, fg_bitmap, 0, 0, 0, 0, cliprect, TRANSPARENCY_COLOR, 0x7f);
	362	/* only copy if the priority bitmap is 0 (no high priority sprite) and the
	363	source pixel is not the invalid pen; also clear to 0xffff when finished */
	364	for (x = cliprect->min_x; x <= cliprect->max_x; x++)
	365	{
	366	UINT16 pix = src[x];
	367	if (pix != 0xffff)
	368	{
	369	src[x] = 0xffff;
	370	if (pri[x] == 0)
	371	dst[x] = pix;
	372	}
	373	}
	374	}
307	375	}
308	376
309	377
310	378	VIDEO_UPDATE( pacland )
311	379	{
312		int x,y,pen;
313	380	int row;
314	381
315	382	for (row = 5; row < 29; row++)
316	383	tilemap_set_scrollx(fg_tilemap, row, flip_screen ? scroll0-7 : scroll0);
317	384	tilemap_set_scrollx(bg_tilemap, 0, flip_screen ? scroll1-4 : scroll1-3);
318	385
	386	/* draw high priority sprite pixels, setting priority bitmap to non-zero
	387	wherever there is a high-priority pixel; note that we draw to the bitmap
	388	which is safe because the bg_tilemap draw will overwrite everything */
	389	fillbitmap(priority_bitmap, 0x00, cliprect);
	390	draw_sprites(machine, bitmap, cliprect, 0);
	391
319	392	/* draw background */
320	393	tilemap_draw(bitmap, cliprect, bg_tilemap, 0, 0);
321	394
322	395	/* draw low priority fg tiles */
323		draw_fg(~~machine,~~ bitmap, cliprect, 0);
	396	draw_fg(bitmap, cliprect, 0);
324	397
325		/* draw sprites in a temporary bitmap */
326		fillbitmap(sprite_bitmap, 0x7f, cliprect);
327		draw_sprites(machine, sprite_bitmap, cliprect, 0);
328		/* copy sprites */
329		copybitmap(bitmap, sprite_bitmap, 0, 0, 0, 0, cliprect, TRANSPARENCY_COLOR, 0x7f);
	398	/* draw sprites with regular transparency */
	399	draw_sprites(machine, bitmap, cliprect, 1);
330	400
331	401	/* draw high priority fg tiles */
332		draw_fg(~~machine,~~ bitmap, cliprect, 1);
	402	draw_fg(bitmap, cliprect, 1);
333	403
334		/* sprite colors >=0xf0 still have priority over that */
335		for (y = 0;y < sprite_bitmap->height;y++)
336		{
337		for (x = 0;x < sprite_bitmap->width;x++)
338		{
339		pen = *BITMAP_ADDR16(sprite_bitmap, y, x);
340		if (pen >= 0xf0)
341		*BITMAP_ADDR16(bitmap, y, x) = pen;
342		}
343		}
	404	/* draw sprite pixels with colortable values >= 0xf0, which have priority over everything */
	405	draw_sprites(machine, bitmap, cliprect, 2);
344	406	return 0;
345	407	}

src/mame/video/splash.c
r949	r950
164	164	break;
165	165	}
166	166
167		*BITMAP_ADDR16(bitmap, sy, sx-9) = machine->pens[0x300+(color^colxor)];
	167	if (sy >= cliprect->min_y && sy <= cliprect->max_y && sx-9 >= cliprect->min_x && sx-9 <= cliprect->max_x)
	168	*BITMAP_ADDR16(bitmap, sy, sx-9) = machine->pens[0x300+(color^colxor)];
168	169	}
169	170	}
170	171

src/mame/video/exidy440.c
r949	r950
179	179	int oldvis = palettebank_vis;
180	180
181	181	/* extract the various bits */
182		exidy440_bank = data >> 4;
	182	exidy440_bank_select(data >> 4);
183	183	firq_enable = (data >> 3) & 1;
184	184	firq_select = (data >> 2) & 1;
185	185	palettebank_io = (data >> 1) & 1;
186	186	palettebank_vis = data & 1;
187	187
188		/* set the memory bank for the main CPU from the upper 4 bits */
189		memory_set_bankptr(1, &memory_region(REGION_CPU1)[0x10000 + exidy440_bank * 0x4000]);
190
191	188	/* update the FIRQ in case we enabled something */
192	189	exidy440_update_firq();
193	190

src/mame/video/hng64.c
r949	r950
1061	1061	// mame_printf_debug("(%d,%d) (%d,%d)\n", startX, startY, endX, endY) ;
1062	1062
1063	1063	// CLAMP - BUT I'M PRETTY SURE THIS ISN'T QUITE RIGHT !!! ???
1064		startX += 1024 ; if (startX < 0) startX = 0 ; else if (startX > 2048) startX = 2048 ;
1065		startY += 1024 ; if (startY < 0) startY = 0 ; else if (startY > 2048) startY = 2048 ;
1066		endX += 1024 ; if (endX < 0) endX = 0 ; else if (endX > 2048) endX = 2048 ;
1067		endY += 1024 ; if (endY < 0) endY = 0 ; else if (endY > 2048) endY = 2048 ;
	1064	startX += 1024 ; if (startX < 0) startX = 0 ; else if (startX >= 2048) startX = 2048-1 ;
	1065	startY += 1024 ; if (startY < 0) startY = 0 ; else if (startY >= 2048) startY = 2048-1 ;
	1066	endX += 1024 ; if (endX < 0) endX = 0 ; else if (endX >= 2048) endX = 2048-1 ;
	1067	endY += 1024 ; if (endY < 0) endY = 0 ; else if (endY >= 2048) endY = 2048-1 ;
1068	1068
1069	1069	numPix = gatherPixelsForLine(tilemapBitmap, startX, startY, endX, endY, penList) ;
1070	1070

src/mame/video/twin16.c
r949	r950
284	284	static void draw_layer( mame_bitmap *bitmap, int opaque ){
285	285	const UINT16 *gfx_base;
286	286	const UINT16 *source = videoram16;
287		int i, y1, y~~2, yd~~;
	287	int i, xxor, yxor;
288	288	int bank_table[4];
289	289	int dx, dy, palette;
290	290	int tile_flipx = 0; // video_register&TWIN16_TILE_FLIPX;
r949	r950
328	328	tile_flipy = !tile_flipy;
329	329	}
330	330
331		if( tile_flipy ){
332		y1 = 7; y2 = -1; yd = -1;
333		}
334		else {
335		y1 = 0; y2 = 8; yd = 1;
336		}
	331	xxor = tile_flipx ? 7 : 0;
	332	yxor = tile_flipy ? 7 : 0;
337	333
338		for( i=0; i<64*64; i++ ){
	334	for( i=0; i<64*64; i++ )
	335	{
	336	int y1, y2, x1, x2;
339	337	int sx = (i%64)*8;
340	338	int sy = (i/64)*8;
341	339	int xpos,ypos;
r949	r950
348	346	if( xpos>=320 ) xpos -= 512;
349	347	if( ypos>=256 ) ypos -= 512;
350	348
351		if( xpos>-8 && ypos>8 && xpos<320 && ypos<256-16 ){
	349	x1 = MAX(xpos, 0);
	350	x2 = MIN(xpos+7, bitmap->width-1);
	351	y1 = MAX(ypos, 0);
	352	y2 = MIN(ypos+7, bitmap->height-1);
	353
	354	if (x1 <= x2 && y1 <= y2)
	355	{
352	356	int code = source[i];
353	357	/*
354	358	xxx------------- color
r949	r950
358	362	const UINT16 gfx_data = gfx_base + (code&0x7ff)16 + bank_table[(code>>11)&0x3]*0x8000;
359	363	int color = (code>>13);
360	364	const pen_t pal_data = Machine->pens + 16(0x20+color+8*palette);
	365	int x, y;
361	366
	367	if( opaque )
362	368	{
363		int y;
364		UINT16 data;
365		int pen;
366
367		if( tile_flipx )
	369	for (y = y1; y <= y2; y++)
368	370	{
369		if( opaque )
370		{
371		{
372		for( y=y1; y!=y2; y+=yd )
373		{
374		UINT16 *dest = BITMAP_ADDR16(bitmap, ypos+y, xpos);
375		UINT8 *pdest = BITMAP_ADDR8(priority_bitmap, ypos+y, xpos);
	371	const UINT16 gfxptr = gfx_data + ((y - ypos) ^ yxor) 2;
	372	UINT16 *dest = BITMAP_ADDR16(bitmap, y, 0);
	373	UINT8 *pdest = BITMAP_ADDR8(priority_bitmap, y, 0);
376	374
377		data = *gfx_data++;
378		dest[7] = pal_data[(data>>4*3)&0xf];
379		dest[6] = pal_data[(data>>4*2)&0xf];
380		dest[5] = pal_data[(data>>4*1)&0xf];
381		dest[4] = pal_data[(data>>4*0)&0xf];
382		data = *gfx_data++;
383		dest[3] = pal_data[(data>>4*3)&0xf];
384		dest[2] = pal_data[(data>>4*2)&0xf];
385		dest[1] = pal_data[(data>>4*1)&0xf];
386		dest[0] = pal_data[(data>>4*0)&0xf];
387
388		pdest[7]\|=1;
389		pdest[6]\|=1;
390		pdest[5]\|=1;
391		pdest[4]\|=1;
392		pdest[3]\|=1;
393		pdest[2]\|=1;
394		pdest[1]\|=1;
395		pdest[0]\|=1;
396		}
397		}
398		}
399		else
	375	for (x = x1; x <= x2; x++)
400	376	{
401		{
402		for( y=y1; y!=y2; y+=yd )
403		{
404		UINT16 *dest = BITMAP_ADDR16(bitmap, ypos+y, xpos);
405		UINT8 *pdest = BITMAP_ADDR8(priority_bitmap, ypos+y, xpos);
406
407		data = *gfx_data++;
408		if( data )
409		{
410		pen = (data>>4*3)&0xf; if( pen ) { dest[7] = pal_data[pen]; pdest[7]\|=4; }
411		pen = (data>>4*2)&0xf; if( pen ) { dest[6] = pal_data[pen]; pdest[6]\|=4; }
412		pen = (data>>4*1)&0xf; if( pen ) { dest[5] = pal_data[pen]; pdest[5]\|=4; }
413		pen = (data>>4*0)&0xf; if( pen ) { dest[4] = pal_data[pen]; pdest[4]\|=4; }
414		}
415		data = *gfx_data++;
416		if( data )
417		{
418		pen = (data>>4*3)&0xf; if( pen ) { dest[3] = pal_data[pen]; pdest[3]\|=4; }
419		pen = (data>>4*2)&0xf; if( pen ) { dest[2] = pal_data[pen]; pdest[2]\|=4; }
420		pen = (data>>4*1)&0xf; if( pen ) { dest[1] = pal_data[pen]; pdest[1]\|=4; }
421		pen = (data>>4*0)&0xf; if( pen ) { dest[0] = pal_data[pen]; pdest[0]\|=4; }
422		}
423		}
424		}
	377	int effx = (x - xpos) ^ xxor;
	378	UINT16 data = gfxptr[effx / 4];
	379	dest[x] = pal_data[(data >> 4*(~effx & 3)) & 0x0f];
	380	pdest[x] \|= 1;
425	381	}
426	382	}
427		else
	383	}
	384	else
	385	{
	386	for (y = y1; y <= y2; y++)
428	387	{
429		if( opaque )
430		{
431		{
432		for( y=y1; y!=y2; y+=yd )
433		{
434		UINT16 *dest = BITMAP_ADDR16(bitmap, ypos+y, xpos);
435		UINT8 *pdest = BITMAP_ADDR8(priority_bitmap, ypos+y, xpos);
	388	const UINT16 gfxptr = gfx_data + ((y - ypos) ^ yxor) 2;
	389	UINT16 *dest = BITMAP_ADDR16(bitmap, y, 0);
	390	UINT8 *pdest = BITMAP_ADDR8(priority_bitmap, y, 0);
436	391
437		data = *gfx_data++;
438		dest++ = pal_data[(data>>43)&0xf];
439		dest++ = pal_data[(data>>42)&0xf];
440		dest++ = pal_data[(data>>41)&0xf];
441		dest++ = pal_data[(data>>40)&0xf];
442		data = *gfx_data++;
443		dest++ = pal_data[(data>>43)&0xf];
444		dest++ = pal_data[(data>>42)&0xf];
445		dest++ = pal_data[(data>>41)&0xf];
446		dest++ = pal_data[(data>>40)&0xf];
447
448		pdest[7]\|=1;
449		pdest[6]\|=1;
450		pdest[5]\|=1;
451		pdest[4]\|=1;
452		pdest[3]\|=1;
453		pdest[2]\|=1;
454		pdest[1]\|=1;
455		pdest[0]\|=1;
456
457		}
458		}
459		}
460		else
	392	for (x = x1; x <= x2; x++)
461	393	{
	394	int effx = (x - xpos) ^ xxor;
	395	UINT16 data = gfxptr[effx / 4];
	396	UINT8 pen = (data >> 4*(~effx & 3)) & 0x0f;
	397	if (pen)
462	398	{
463		for( y=y1; y!=y2; y+=yd )
464		{
465		UINT16 *dest = BITMAP_ADDR16(bitmap, ypos+y, xpos);
466		UINT8 *pdest = BITMAP_ADDR8(priority_bitmap, ypos+y, xpos);
467
468		data = *gfx_data++;
469		if( data )
470		{
471		pen = (data>>4*3)&0xf; if( pen ) { dest[0] = pal_data[pen]; pdest[0]\|=4; }
472		pen = (data>>4*2)&0xf; if( pen ) { dest[1] = pal_data[pen]; pdest[1]\|=4; }
473		pen = (data>>4*1)&0xf; if( pen ) { dest[2] = pal_data[pen]; pdest[2]\|=4; }
474		pen = (data>>4*0)&0xf; if( pen ) { dest[3] = pal_data[pen]; pdest[3]\|=4; }
475		}
476		data = *gfx_data++;
477		if( data )
478		{
479		pen = (data>>4*3)&0xf; if( pen ) { dest[4] = pal_data[pen]; pdest[4]\|=4; }
480		pen = (data>>4*2)&0xf; if( pen ) { dest[5] = pal_data[pen]; pdest[5]\|=4; }
481		pen = (data>>4*1)&0xf; if( pen ) { dest[6] = pal_data[pen]; pdest[6]\|=4; }
482		pen = (data>>4*0)&0xf; if( pen ) { dest[7] = pal_data[pen]; pdest[7]\|=4; }
483		}
484		}
	399	dest[x] = pal_data[pen];
	400	pdest[x] \|= 4;
485	401	}
486	402	}
487	403	}

src/mame/video/cave.c
r949	r950
1315	1315	A tilemap line is specified for each scan line. This is handled
1316	1316	using many horizontal clipping regions (slices) and calling
1317	1317	tilemap_draw multiple times.
1318
1319		Note: tilemap.c has a limitation on the size of a clipping
1320		region, which can only be a multiple of 8 pixels.
1321		Thus in vertical games (where our horizontal slices
1322		become vertical) there may be graphical glitches.
1323	1318	*/
1324	1319
1325	1320	clip.min_x = cliprect->min_x;
r949	r950
1329	1324	{
1330	1325	/* Find the largest slice */
1331	1326	vramdata0 = (vramdata1 = VRAM[(0x1002+(((sy+offs_row+startline)*4)&0x7ff))/2]);
1332		for(endline = startline + 1; endline <= cliprect->max_y ~~+ 1~~; endline++)
	1327	for(endline = startline + 1; endline <= cliprect->max_y; endline++)
1333	1328	if((++vramdata1) != VRAM[(0x1002+(((sy+offs_row+endline)*4)&0x7ff))/2]) break;
1334	1329
1335	1330	tilemap_set_scrolly(TILEMAP, 0, vramdata0 - startline);

src/mame/drivers/galaxian.c
r949	r950
3889	3889	PORT_BIT( 0xf0, IP_ACTIVE_HIGH, IPT_UNUSED )
3890	3890	INPUT_PORTS_END
3891	3891
	3892
	3893	INPUT_PORTS_START( porter )
	3894	PORT_START_TAG("IN0")\
	3895	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
	3896	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )
	3897	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT )
	3898	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT )
	3899	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )
	3900	PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
	3901	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	3902	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3903	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
	3904	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	3905	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3906	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )
	3907
	3908	PORT_START_TAG("IN1")
	3909	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 ) // and START
	3910	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2) // and START2
	3911	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
	3912	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
	3913	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
	3914	PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
	3915	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	3916	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3917	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
	3918	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	3919	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3920	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
	3921	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	3922	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3923
	3924	PORT_START_TAG("DSW")
	3925	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ) )
	3926	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	3927	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3928	PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
	3929	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	3930	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3931	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
	3932	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	3933	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3934	PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
	3935	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	3936	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3937	PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
	3938	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	3939	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3940	PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
	3941	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	3942	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3943	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
	3944	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	3945	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3946	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
	3947	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	3948	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	3949	INPUT_PORTS_END
	3950
3892	3951	static const gfx_layout galaxian_charlayout =
3893	3952	{
3894	3953	8,8,
r949	r950
5719	5778	ROM_LOAD( "mmi6331.6l", 0x0000, 0x0020, CRC(6a0c7d87) SHA1(140335d85c67c75b65689d4e76d29863c209cf32) ) /* Compatible with 82s123 prom */
5720	5779	ROM_END
5721	5780
	5781
	5782	ROM_START( mooncmw )
	5783	ROM_REGION( 0x10000, REGION_CPU1, 0 )
	5784	ROM_LOAD( "60.1x", 0x0000, 0x0800, CRC(322859e6) SHA1(292dccb66c38c8de837ec3ac10928d092494958e) )
	5785	ROM_LOAD( "61.2x", 0x0800, 0x0800, CRC(c249902d) SHA1(0015461173fb991fd99c824e0eab054c3c17d0f1) )
	5786	ROM_LOAD( "62.3x", 0x1000, 0x0800, CRC(29a2b0ab) SHA1(e9fc7161d0566e36307c45b7132e2262c0af4845) )
	5787	ROM_LOAD( "63.4x", 0x1800, 0x0800, CRC(4c6a5a6d) SHA1(366516f63c9b5239e703e4dfb672659049ddbf44) )
	5788	ROM_LOAD( "64.5x", 0x2000, 0x0800, CRC(06d378a6) SHA1(99dbe9fc7f95f8fdce86eb5c32bd1ca1bea0ca3c) )
	5789	ROM_LOAD( "65.6x", 0x2800, 0x0800, CRC(6e84a927) SHA1(82e8e825d157c3c947a3a222bca059a735169c7d) )
	5790	ROM_LOAD( "66.7x", 0x3000, 0x0800, CRC(f23cd8ce) SHA1(a77e7eca239de6a72a8cabed6444ae8efb9e40bd) )
	5791	ROM_LOAD( "67.8x", 0x3800, 0x0800, CRC(66da55d5) SHA1(39e2f6107e77ee97860147f64b9673cd9a2ae612) )
	5792
	5793	ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
	5794	ROM_LOAD( "68.1h", 0x0000, 0x1000, CRC(78663d86) SHA1(8648a3e60259404a05ad58b1641190e5b33a24eb) )
	5795	ROM_LOAD( "69.1k", 0x1000, 0x1000, CRC(162c50d3) SHA1(67d9c87782cf29c443590d7ad687fbeaa6218346) )
	5796
	5797	ROM_REGION( 0x0020, REGION_PROMS, 0 )
	5798	ROM_LOAD( "prom-sn74s288n-71.6l", 0x0000, 0x0020, CRC(6a0c7d87) SHA1(140335d85c67c75b65689d4e76d29863c209cf32) ) /* Compatible with 82s123 prom */
	5799	ROM_END
	5800
5722	5801	ROM_START( spcdrag )
5723	5802	ROM_REGION( 0x10000, REGION_CPU1, 0 )
5724	5803	ROM_LOAD( "a.bin", 0x0000, 0x0800, CRC(38cc9839) SHA1(71c5853fc14a9c0b93e3b7660b925021680a0fe1) )
r949	r950
6616	6695	ROM_LOAD( "ck_cp.bin", 0x0000, 0x0020, CRC(7e0b79cb) SHA1(72ef3eb5f09e10c13dcf6fd568a6d16658055a16) )
6617	6696	ROM_END
6618	6697
	6698
	6699	ROM_START( porter )
	6700	ROM_REGION( 0x10000, REGION_CPU1, 0 )
	6701	ROM_LOAD( "port1.bin", 0x0000, 0x0800, CRC(babaf7fe) SHA1(2138abf57990df9b6f9953efd3be9b2bede49520) )
	6702	ROM_CONTINUE( 0x2000, 0x0800)
	6703	ROM_LOAD( "port2.bin", 0x0800, 0x0800, CRC(8f7eb0e3) SHA1(7ac5bfc0bb8b6a7a3e9acab5ce9a53f7cba1fca5) )
	6704	ROM_CONTINUE( 0x2800, 0x0800)
	6705	ROM_LOAD( "port3.bin", 0x1000, 0x0800, CRC(683939b5) SHA1(caf69b03794cb5cf63b1aa52cf8ef355a3aeef87) )
	6706	ROM_CONTINUE( 0x3000, 0x0800)
	6707	ROM_LOAD( "port4.bin", 0x1800, 0x0800, CRC(6a65d58d) SHA1(05824a41b2912f12bff7887e7483cb3f4367d339) )
	6708	ROM_CONTINUE( 0x3800,0x0800)
	6709	ROM_LOAD( "port5.bin", 0x4000, 0x0800, CRC(2978a9aa) SHA1(99ec75c7f83f4858b26e083b50fde41fbcfe449a) )
	6710	ROM_LOAD( "port6.bin", 0x4800, 0x0800, CRC(7ecdffb5) SHA1(18ce71b670503bef039c6bfb0aed5e8c10e9eb2d) )
	6711
	6712	ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
	6713	ROM_LOAD( "port7.bin", 0x0000, 0x1000, CRC(603294f9) SHA1(168b90fdf38cd2e2c7f54cde16b4d83dc5bb3046) )
	6714	ROM_LOAD( "port8.bin", 0x1000, 0x1000, CRC(b66a763d) SHA1(995b473b1942ff666b0989993587e41e89542172) )
	6715
	6716	ROM_REGION( 0x0020, REGION_PROMS, 0 ) // not in the set
	6717	ROM_LOAD( "mmi6331.6l", 0x0000, 0x0020, BAD_DUMP CRC(6a0c7d87) SHA1(140335d85c67c75b65689d4e76d29863c209cf32) ) /* Compatible with 82s123 prom */
	6718	ROM_END
	6719
6619	6720	GAME( 1979, galaxian, 0, galaxian, galaxian, 0, ROT90, "Namco", "Galaxian (Namco set 1)", GAME_SUPPORTS_SAVE )
6620	6721	GAME( 1979, galaxiaj, galaxian, galaxian, superg, 0, ROT90, "Namco", "Galaxian (Namco set 2)", GAME_SUPPORTS_SAVE )
6621	6722	GAME( 1979, galmidw, galaxian, galaxian, galaxian, 0, ROT90, "[Namco] (Midway license)", "Galaxian (Midway)", GAME_SUPPORTS_SAVE )
r949	r950
6674	6775	GAME( 1980, eagle3, mooncrst, mooncrst, eagle, mooncrsu, ROT90, "Centuri", "Eagle (set 3)", GAME_SUPPORTS_SAVE )
6675	6776	GAME( 1981?,spctbird, mooncrst, mooncrst, eagle2, mooncrsu, ROT90, "Fortrek", "Space Thunderbird", GAME_SUPPORTS_SAVE )
6676	6777	GAME( 1980?,smooncrs, mooncrst, mooncrst, smooncrs, mooncrsu, ROT90, "Gremlin", "Super Moon Cresta", GAME_SUPPORTS_SAVE )
	6778	GAME( 198?, mooncmw, mooncrst, mooncrst, mooncrsa, mooncrsu, ROT90, "bootleg", "Moon War (Moon Cresta bootleg)", GAME_SUPPORTS_SAVE )
6677	6779	// The boards were marked 'Space Dragon' although this doesn't appear in the games.
6678	6780	GAME( 1980, spcdrag, mooncrst, mooncrst, spcdrag, mooncrsu, ROT90, "bootleg", "Space Dragon (Moon Cresta bootleg, set 1)", GAME_SUPPORTS_SAVE )
6679	6781	GAME( 1980, spcdraga, mooncrst, mooncrst, spcdrag, mooncrsu, ROT90, "bootleg", "Space Dragon (Moon Cresta bootleg, set 2)", GAME_SUPPORTS_SAVE )
r949	r950
6712	6814	GAME( 19??, chewing, 0, galaxian, luctoday, 0, ROT90, "unknown", "Chewing Gum", GAME_SUPPORTS_SAVE )
6713	6815	GAME( 1982, catacomb, 0, galaxian, catacomb, 0, ROT90, "MTM Games", "Catacomb", GAME_WRONG_COLORS \| GAME_SUPPORTS_SAVE )
6714	6816	GAME( 1981, ckongg, 0, ckongg , ckongg, 0, ROT90, "bootleg", "Crazy Kong (galaxian)", GAME_SUPPORTS_SAVE )
	6817	GAME( 19??, porter, 0, mooncrst, porter, 0, ROT90, "[Nova Games Ltd.] (bootleg)", "Port Man (bootleg on Moon Cresta hardware)", GAME_IMPERFECT_GRAPHICS ) // missing GFX bank switch!

src/mame/drivers/model2.c
r949	r950
2202	2202
2203	2203	ROM_START( manxtt )
2204	2204	ROM_REGION( 0x200000, REGION_CPU1, 0 ) // i960 program
2205		ROM_LOAD32_WORD( "epr-18822.12", 0x000000, 0x020000, CRC(c7b3e45a) SHA1(d3a6910bf6efc138e0e40332219b90dea7d6ea56) )
2206		ROM_LOAD32_WORD( "epr-18823.13", 0x000002, 0x020000, CRC(6b0c1dfb) SHA1(6da5c071e3ce842a99f928f473d4ccf7165785ac) )
2207		ROM_LOAD32_WORD( "epr-18824.14", 0x040000, 0x020000, CRC(352bb817) SHA1(389cbf951ba606acb9ab7bff5cda85d9166e64ff) )
2208		ROM_LOAD32_WORD( "epr-18825.15", 0x040002, 0x020000, CRC(f88b036c) SHA1(f6196e8da5e6579fe3fa5c24ab9538964c98e267) )
	2205	ROM_LOAD32_WORD( "epr-18822c.12", 0x000000, 0x020000, CRC(c7b3e45a) SHA1(d3a6910bf6efc138e0e40332219b90dea7d6ea56) )
	2206	ROM_LOAD32_WORD( "epr-18823c.13", 0x000002, 0x020000, CRC(6b0c1dfb) SHA1(6da5c071e3ce842a99f928f473d4ccf7165785ac) )
	2207	ROM_LOAD32_WORD( "epr-18824c.14", 0x040000, 0x020000, CRC(352bb817) SHA1(389cbf951ba606acb9ab7bff5cda85d9166e64ff) )
	2208	ROM_LOAD32_WORD( "epr-18825c.15", 0x040002, 0x020000, CRC(f88b036c) SHA1(f6196e8da5e6579fe3fa5c24ab9538964c98e267) )
2209	2209
2210	2210	ROM_REGION32_LE( 0x2400000, REGION_USER1, 0 ) // Data
2211		ROM_LOAD32_WORD( "mpr-18751.bin", 0x000000, 0x200000, CRC(773ad43d) SHA1(4d1601dc08a08b724e33e7cd90a4f22e18cfed9c) )
2212		ROM_LOAD32_WORD( "mpr-18752.bin", 0x000002, 0x200000, CRC(4da3719e) SHA1(24007e4ae3ba1a06321328d14e2bd6002fa1936e) )
2213		ROM_LOAD32_WORD( "mpr-18749.bin", 0x400000, 0x200000, CRC(c3fe0eea) SHA1(ada21405a136935ac4da1a3535c25fccf903f2d1) )
2214		ROM_LOAD32_WORD( "mpr-18750.bin", 0x400002, 0x200000, CRC(40b55494) SHA1(d98ae5518c5d31b155b1a7c4f7d9d67f44d7beae) )
2215		ROM_LOAD32_WORD( "mpr-18747.bin", 0x800000, 0x200000, CRC(f2ecac6f) SHA1(879d7b277e238d1d8713f2b604bc3db407aa249d) )
2216		ROM_LOAD32_WORD( "mpr-18748.bin", 0x800002, 0x200000, CRC(7815d634) SHA1(bfeff77630759c88b2191ea7e1ff78e0d70cbdf5) )
2217		ROM_LOAD32_WORD( "mpr-18862.bin", 0xc00000, 0x080000, CRC(9adc3a30) SHA1(029db946338f8e0eccace8590082cc96bdf13e31) )
2218		ROM_LOAD32_WORD( "mpr-18863.bin", 0xc00002, 0x080000, CRC(603742e9) SHA1(f78a5f7e582d313880c734158bb0fa68b256a58a) )
	2211	ROM_LOAD32_WORD( "mpr-18751.10", 0x000000, 0x200000, CRC(773ad43d) SHA1(4d1601dc08a08b724e33e7cd90a4f22e18cfed9c) )
	2212	ROM_LOAD32_WORD( "mpr-18752.11", 0x000002, 0x200000, CRC(4da3719e) SHA1(24007e4ae3ba1a06321328d14e2bd6002fa1936e) )
	2213	ROM_LOAD32_WORD( "mpr-18749.8", 0x400000, 0x200000, CRC(c3fe0eea) SHA1(ada21405a136935ac4da1a3535c25fccf903f2d1) )
	2214	ROM_LOAD32_WORD( "mpr-18750.9", 0x400002, 0x200000, CRC(40b55494) SHA1(d98ae5518c5d31b155b1a7c4f7d9d67f44d7beae) )
	2215	ROM_LOAD32_WORD( "mpr-18747.6", 0x800000, 0x200000, CRC(a65ec1e8) SHA1(92636bdff0ae4cdb43dfc2986fad2d1b59469323) )
	2216	ROM_LOAD32_WORD( "mpr-18748.7", 0x800002, 0x200000, CRC(375e3748) SHA1(6c2e903dd073b130bcabb347631b876dc868b494) )
	2217	ROM_LOAD32_WORD( "epr-18862.4", 0xc00000, 0x080000, CRC(9adc3a30) SHA1(029db946338f8e0eccace8590082cc96bdf13e31) )
	2218	ROM_LOAD32_WORD( "epr-18863.5", 0xc00002, 0x080000, CRC(603742e9) SHA1(f78a5f7e582d313880c734158bb0fa68b256a58a) )
2219	2219	ROM_COPY( REGION_USER1, 0xc00000, 0xd00000, 0x100000 )
2220	2220	ROM_COPY( REGION_USER1, 0xc00000, 0xe00000, 0x100000 )
2221	2221	ROM_COPY( REGION_USER1, 0xc00000, 0xf00000, 0x100000 )
2222	2222
2223	2223	ROM_REGION( 0x2000000, REGION_USER2, 0 ) // Models
2224		ROM_LOAD32_WORD( "mpr-18753.bin", 0x000000, 0x200000, CRC(33ddaa0d) SHA1(26f643d6b9cecf08bd249290a670a0edea1b5be4) )
2225		ROM_LOAD32_WORD( "mpr-18756.bin", 0x000002, 0x200000, CRC(e1678c59) SHA1(d55828c2ed9714c4e07455a8eed7fc39967a9124) )
2226		ROM_LOAD32_WORD( "mpr-18754.bin", 0x400000, 0x200000, CRC(09aabde5) SHA1(e50646efb2ca59792833ce91398c4efa861ad6d1) )
2227		ROM_LOAD32_WORD( "mpr-18757.bin", 0x400004, 0x200000, CRC(25fc92e9) SHA1(226c4c7289b3b6009c1ffea4a171e3fb4e31a67c) )
2228		ROM_LOAD32_WORD( "mpr-18755.bin", 0x000000, 0x200000, CRC(fd1fa53c) SHA1(d8dabbd6efcc2752879cce3df2cb99b65e043eca) )
2229		ROM_LOAD32_WORD( "mpr-18758.bin", 0x800002, 0x200000, CRC(1b5473d0) SHA1(658e33503f6990f4d9a954c63efad5f53d15f3a4) )
	2224	ROM_LOAD32_WORD( "mpr-18753.16", 0x000000, 0x200000, CRC(33ddaa0d) SHA1(26f643d6b9cecf08bd249290a670a0edea1b5be4) )
	2225	ROM_LOAD32_WORD( "mpr-18756.20", 0x000002, 0x200000, CRC(28713617) SHA1(fc2a6258387a1bc3fae2109b2dae6dd2a1984ab5) )
	2226	ROM_LOAD32_WORD( "mpr-18754.17", 0x400000, 0x200000, CRC(09aabde5) SHA1(e50646efb2ca59792833ce91398c4efa861ad6d1) )
	2227	ROM_LOAD32_WORD( "mpr-18757.21", 0x400004, 0x200000, CRC(25fc92e9) SHA1(226c4c7289b3b6009c1ffea4a171e3fb4e31a67c) )
	2228	ROM_LOAD32_WORD( "mpr-18755.18", 0x000000, 0x200000, CRC(bf094d9e) SHA1(2cd7130b226a28098191a6caf6fd761bb0bfac7b) )
	2229	ROM_LOAD32_WORD( "mpr-18758.22", 0x800002, 0x200000, CRC(1b5473d0) SHA1(658e33503f6990f4d9a954c63efad5f53d15f3a4) )
2230	2230
2231	2231	ROM_REGION( 0x800000, REGION_CPU3, 0 ) // TGP program? (COPRO socket)
2232		ROM_LOAD32_WORD( "mpr-18761.bin", 0x000000, 0x200000, CRC(4e39ec05) SHA1(50696cd320f1a6492e0c193713acbce085d959cd) )
2233		ROM_LOAD32_WORD( "mpr-18762.bin", 0x000002, 0x200000, CRC(4ab165d8) SHA1(7ff42a4c7236fec76f94f2d0c5537e503bcc98e5) )
	2232	ROM_LOAD32_WORD( "mpr-18761.28", 0x000000, 0x200000, CRC(4e39ec05) SHA1(50696cd320f1a6492e0c193713acbce085d959cd) )
	2233	ROM_LOAD32_WORD( "mpr-18762.29", 0x000002, 0x200000, CRC(4ab165d8) SHA1(7ff42a4c7236fec76f94f2d0c5537e503bcc98e5) )
2234	2234
2235	2235	ROM_REGION( 0x1000000, REGION_USER3, 0 ) // Textures
2236		ROM_LOAD32_WORD( "mpr-18759.bin", 0x000000, 0x200000, CRC(89d7927d) SHA1(6908de9cbb71b36fc7dd35aace6bfd61408bb30b) )
2237		ROM_LOAD32_WORD( "mpr-18760.bin", 0x000002, 0x200000, CRC(4e3a4a89) SHA1(bba6cd2a15b3f963388a3a87880da86b10f6e0a2) )
	2236	ROM_LOAD32_WORD( "mpr-18760.25", 0x000000, 0x200000, CRC(4e3a4a89) SHA1(bba6cd2a15b3f963388a3a87880da86b10f6e0a2) )
	2237	ROM_LOAD32_WORD( "mpr-18759.24", 0x000002, 0x200000, CRC(278d8742) SHA1(5f285fc8cfe88c00ba2bbe1b509b49abd38e00ec) )
2238	2238
2239	2239	ROM_REGION( 0x100000, REGION_CPU2, 0 ) // Sound program
2240		ROM_LOAD16_WORD_SWAP( "epr-18826.30", 0x080000, 0x040000, CRC(ed9fe4c1) SHA1(c3dd8a1324a4dc9b012bd9bf21d1f48578870f72) )
	2240	// ROM_LOAD16_WORD_SWAP( "epr-18826.30", 0x080000, 0x040000, CRC(ed9fe4c1) SHA1(c3dd8a1324a4dc9b012bd9bf21d1f48578870f72) ) /* Alternate sound program */
	2241	ROM_LOAD16_WORD_SWAP( "epr-18924a.30", 0x080000, 0x040000, CRC(ad6f40ec) SHA1(27aa0477dc325162766d459ffe95b61ee65dd28f) )
2241	2242
2242	2243	ROM_REGION( 0x800000, REGION_SOUND1, 0 ) // Samples
2243		ROM_LOAD( "mpr-18827.31", 0x000000, 0x200000, CRC(58d78ca1) SHA1(95275ed8315c044bfde2f23c10416f22627b34df) )
	2244	// ROM_LOAD( "mpr-18827.31", 0x000000, 0x200000, CRC(58d78ca1) SHA1(95275ed8315c044bfde2f23c10416f22627b34df) ) /* Alternate sound sample */
	2245	ROM_LOAD( "mpr-18763.31", 0x000000, 0x200000, CRC(1bcb2283) SHA1(a4a8a2f8f0901bfb57778351210ccfc421cacbd4) )
2244	2246	ROM_LOAD( "mpr-18764.32", 0x200000, 0x200000, CRC(0dc6a860) SHA1(cb2ada0f8a592940de11ee781ad4beb5095c3b37) )
2245	2247	ROM_LOAD( "mpr-18765.36", 0x400000, 0x200000, CRC(ca4a803c) SHA1(70b59da8f2532a02e980caba5bb86ec13a4d7ab5) )
2246		ROM_LOAD( "mpr-18766.37", 0x600000, 0x200000, CRC(1~~0f3c~~932) SHA1(5f6da~~9825~~b70c1ea83~~a421e~~3~~5038042~~fb~~178~~62ec) )
	2248	ROM_LOAD( "mpr-18766.37", 0x600000, 0x200000, CRC(e41892ea) SHA1(9ef5e26db4abf0ed36df63fc246b568e1c5d6cfa) )
2247	2249
2248	2250	MODEL2_CPU_BOARD
2249	2251	MODEL2A_VID_BOARD
r949	r950
2251	2253
2252	2254	ROM_START( motoraid )
2253	2255	ROM_REGION( 0x200000, REGION_CPU1, 0 ) // i960 program
2254		ROM_LOAD32_WORD( "epr20007.12", 0x000000, 0x080000, CRC(f040c108) SHA1(a6a0fa8fb9d62d0cc2ac84ea3ad457953952d980) )
2255		ROM_LOAD32_WORD( "epr20008.13", 0x000002, 0x080000, CRC(78976e1a) SHA1(fd15e8c81b3b2f3bdf3bb8d9414b9b8a6f1f000f) )
	2256	ROM_LOAD32_WORD( "epr-20007.12", 0x000000, 0x080000, CRC(f040c108) SHA1(a6a0fa8fb9d62d0cc2ac84ea3ad457953952d980) )
	2257	ROM_LOAD32_WORD( "epr-20008.13", 0x000002, 0x080000, CRC(78976e1a) SHA1(fd15e8c81b3b2f3bdf3bb8d9414b9b8a6f1f000f) )
2256	2258
2257	2259	ROM_REGION32_LE( 0x2400000, REGION_USER1, 0 ) // Data
2258	2260	ROM_LOAD32_WORD( "mpr-20019.10", 0x0000000, 0x400000, CRC(49053727) SHA1(0543d19d1d60b1d12b4409c1491782f2232da685) )
r949	r950
2261	2263	ROM_LOAD32_WORD( "mpr-20018.9", 0x0800002, 0x400000, CRC(e7ed0e85) SHA1(78a0c72095a664c4b6e529beea46a31ae0a99e5a) )
2262	2264	ROM_LOAD32_WORD( "mpr-20015.6", 0x1000000, 0x400000, CRC(23427339) SHA1(3e37cfcb4dcc8976805934faf8805cd83acde66e) )
2263	2265	ROM_LOAD32_WORD( "mpr-20016.7", 0x1000002, 0x400000, CRC(c99a83f4) SHA1(b057d61478f7dc7a32ad233473f1a63498b3779e) )
2264		ROM_LOAD32_WORD( "epr20013.4", 0x1800000, 0x080000, CRC(a4478f52) SHA1(28f430319b34e715ca57ce4e01be23a786eab4bc) )
2265		ROM_LOAD32_WORD( "epr20014.5", 0x1800002, 0x080000, CRC(1aa541be) SHA1(c4cc61a42e89aaae075ad1b6e8df2907c5710d3e) )
	2266	ROM_LOAD32_WORD( "epr-20013.4", 0x1800000, 0x080000, CRC(a4478f52) SHA1(28f430319b34e715ca57ce4e01be23a786eab4bc) )
	2267	ROM_LOAD32_WORD( "epr-20014.5", 0x1800002, 0x080000, CRC(1aa541be) SHA1(c4cc61a42e89aaae075ad1b6e8df2907c5710d3e) )
2266	2268	ROM_COPY( REGION_USER1, 0x1800000, 0x1900000, 0x100000 ) // rgn,srcoffset,offset,length.
2267	2269	ROM_COPY( REGION_USER1, 0x1800000, 0x1a00000, 0x100000 )
2268	2270	ROM_COPY( REGION_USER1, 0x1800000, 0x1b00000, 0x100000 )
r949	r950
2272	2274	ROM_COPY( REGION_USER1, 0x1800000, 0x1f00000, 0x100000 )
2273	2275
2274	2276	ROM_REGION( 0x2000000, REGION_USER2, 0 ) // Models
2275		ROM_LOAD32_WORD( "mpr-20023", 0x0000000, 0x400000, CRC(016be8d6) SHA1(804f69cd342e25cf1bed48e778981d67c4d1c9c7) )
2276		ROM_LOAD32_WORD( "mpr-20026", 0x0000002, 0x400000, CRC(20044a30) SHA1(46be0cc2b8a4a3f530d081d11c6099d814977270) )
2277		ROM_LOAD32_WORD( "mpr-20024", 0x0800000, 0x400000, CRC(62fd2d5b) SHA1(6a386a666ae57da5e47364da7b97da9c913710ef) )
2278		ROM_LOAD32_WORD( "mpr-20027", 0x0800002, 0x400000, CRC(b2504ea6) SHA1(17c23c64b1080ab6a8eb282cabcd7d7612193045) )
2279		ROM_LOAD32_WORD( "mpr-20025", 0x1000000, 0x400000, CRC(d4ecd0be) SHA1(9df0d1db32b818dad28f9eeab3bc19c56d27ec6d) )
2280		ROM_LOAD32_WORD( "mpr-20028", 0x1000002, 0x400000, CRC(3147e0e1) SHA1(9aa0e13c8dc5073a603279a538cc7662531dfd19) )
	2277	ROM_LOAD32_WORD( "mpr-20023.16", 0x0000000, 0x400000, CRC(016be8d6) SHA1(804f69cd342e25cf1bed48e778981d67c4d1c9c7) )
	2278	ROM_LOAD32_WORD( "mpr-20026.20", 0x0000002, 0x400000, CRC(20044a30) SHA1(46be0cc2b8a4a3f530d081d11c6099d814977270) )
	2279	ROM_LOAD32_WORD( "mpr-20024.17", 0x0800000, 0x400000, CRC(62fd2d5b) SHA1(6a386a666ae57da5e47364da7b97da9c913710ef) )
	2280	ROM_LOAD32_WORD( "mpr-20027.21", 0x0800002, 0x400000, CRC(b2504ea6) SHA1(17c23c64b1080ab6a8eb282cabcd7d7612193045) )
	2281	ROM_LOAD32_WORD( "mpr-20025.18", 0x1000000, 0x400000, CRC(d4ecd0be) SHA1(9df0d1db32b818dad28f9eeab3bc19c56d27ec6d) )
	2282	ROM_LOAD32_WORD( "mpr-20028.22", 0x1000002, 0x400000, CRC(3147e0e1) SHA1(9aa0e13c8dc5073a603279a538cc7662531dfd19) )
2281	2283
2282	2284	ROM_REGION( 0x800000, REGION_CPU3, 0 ) // TGP program? (COPRO socket)
2283		ROM_LOAD32_WORD( "epr20012", 0x000000, 0x100000, CRC(f53db4e3) SHA1(4474610eed52248e5e36be438eff5d39f076b134) )
2284		ROM_LOAD32_WORD( "epr20011", 0x000002, 0x100000, CRC(794c026c) SHA1(85abd667491fd019ee18ba256fd580356f4e1fe9) )
	2285	ROM_LOAD32_WORD( "epr-20012", 0x000000, 0x100000, CRC(f53db4e3) SHA1(4474610eed52248e5e36be438eff5d39f076b134) ) /* are these two in the wrong order? */
	2286	ROM_LOAD32_WORD( "epr-20011", 0x000002, 0x100000, CRC(794c026c) SHA1(85abd667491fd019ee18ba256fd580356f4e1fe9) )
2285	2287
2286	2288	ROM_REGION( 0x1000000, REGION_USER3, 0 ) // Textures
2287		ROM_LOAD32_WORD( "mpr-20022", 0x000000, 0x400000, CRC(9e47b3c2) SHA1(c73279e837f56c0417c07ba3c642af28fe9a24fa))
2288		ROM_LOAD32_WORD( "mpr-20021", 0x000002, 0x400000, CRC(3cbf36cb) SHA1(059cea17f9d6f5960d9fd869c36ffb6fcf230c1a) )
	2289	ROM_LOAD32_WORD( "mpr-20022.25", 0x000000, 0x400000, CRC(9e47b3c2) SHA1(c73279e837f56c0417c07ba3c642af28fe9a24fa) )
	2290	ROM_LOAD32_WORD( "mpr-20021.24", 0x000002, 0x400000, CRC(3cbf36cb) SHA1(059cea17f9d6f5960d9fd869c36ffb6fcf230c1a) )
2289	2291
2290	2292	ROM_REGION( 0x100000, REGION_CPU2, 0 ) // Sound program
2291		ROM_LOAD16_WORD_SWAP( "epr20029", 0x080000, 0x080000, CRC(927d31b9) SHA1(e7a18ccf5a0b9ebf18ae1d5518973fa3b4eb4653) )
	2293	ROM_LOAD16_WORD_SWAP( "epr-20029.30", 0x080000, 0x080000, CRC(927d31b9) SHA1(e7a18ccf5a0b9ebf18ae1d5518973fa3b4eb4653) )
2292	2294
2293	2295	ROM_REGION( 0x800000, REGION_SOUND1, 0 ) // Samples
2294		ROM_LOAD( "mpr20030", 0x000000, 0x200000, CRC(b70ab686) SHA1(006911ce6332091d17808855c60a72fe928df778) )
2295		ROM_LOAD( "mpr20031", 0x200000, 0x200000, CRC(84da70e4) SHA1(77962afcac82589cc7bc852329335676ae3e23cf) )
2296		ROM_LOAD( "mpr20032", 0x400000, 0x200000, CRC(15516d35) SHA1(bced0d30f9b6ab579a11ac069cbb9d6d91352246) )
2297		ROM_LOAD( "mpr20033", 0x600000, 0x200000, CRC(8c8ed187) SHA1(a9e8e2d38b23716df2e211748c52b6b666f4c111) )
	2296	ROM_LOAD( "mpr-20030.31", 0x000000, 0x200000, CRC(b70ab686) SHA1(006911ce6332091d17808855c60a72fe928df778) )
	2297	ROM_LOAD( "mpr-20031.32", 0x200000, 0x200000, CRC(84da70e4) SHA1(77962afcac82589cc7bc852329335676ae3e23cf) )
	2298	ROM_LOAD( "mpr-20032.36", 0x400000, 0x200000, CRC(15516d35) SHA1(bced0d30f9b6ab579a11ac069cbb9d6d91352246) )
	2299	ROM_LOAD( "mpr-20033.37", 0x600000, 0x200000, CRC(8c8ed187) SHA1(a9e8e2d38b23716df2e211748c52b6b666f4c111) )
2298	2300
2299	2301	MODEL2_CPU_BOARD
2300	2302	MODEL2A_VID_BOARD

src/mame/drivers/cps2.c
r949	r950
2737	2737
2738	2738	ROM_START( dimahoo )
2739	2739	ROM_REGION( CODE_SIZE, REGION_CPU1, 0 ) /* 68000 code */
	2740	ROM_LOAD16_WORD_SWAP( "gdme_03.03", 0x000000, 0x80000, CRC(968fcecd) SHA1(82d6eb6488df48bc7b977fc900c24b29bd6573a9) )
	2741	ROM_LOAD16_WORD_SWAP( "gmd.04", 0x080000, 0x80000, CRC(37485567) SHA1(643c41fce6057bcaef0e0bedc62914c33d97eeaf) )
	2742	ROM_LOAD16_WORD_SWAP( "gmd.05", 0x100000, 0x80000, CRC(da269ffb) SHA1(e99b04192030b6006cf67b563f40cea29c1b2e78) )
	2743	ROM_LOAD16_WORD_SWAP( "gmd.06", 0x180000, 0x80000, CRC(55b483c9) SHA1(d47e077312f3c044d3647b79fa9e0581ccff5992) )
	2744
	2745	ROM_REGION( 0x1000000, REGION_GFX1, 0 )
	2746	ROMX_LOAD( "gmd.13m", 0x000000, 0x400000, CRC(80dd19f0) SHA1(0fd8b1e8d73cc83e6c34f0d94487938da2344f76) , ROM_GROUPWORD \| ROM_SKIP(6) )
	2747	ROMX_LOAD( "gmd.15m", 0x000002, 0x400000, CRC(dfd93a78) SHA1(c343d5ddcc25bd0739491e7439d7c0d0a8881a04) , ROM_GROUPWORD \| ROM_SKIP(6) )
	2748	ROMX_LOAD( "gmd.17m", 0x000004, 0x400000, CRC(16356520) SHA1(058713bef30c1b1d8b7dd0ceaaa57a3ab9751a70) , ROM_GROUPWORD \| ROM_SKIP(6) )
	2749	ROMX_LOAD( "gmd.19m", 0x000006, 0x400000, CRC(dfc33031) SHA1(a1ceaeddc2a79d5b79f1b107cac2ef6a5e621e77) , ROM_GROUPWORD \| ROM_SKIP(6) )
	2750
	2751	ROM_REGION( QSOUND_SIZE, REGION_CPU2, 0 ) /* 64k for the audio CPU (+banks) */
	2752	ROM_LOAD( "gmd.01", 0x00000, 0x08000, CRC(3f9bc985) SHA1(1616bbee82877b1052a07531066f5009a80706be) )
	2753	ROM_CONTINUE( 0x10000, 0x18000 )
	2754	ROM_LOAD( "gmd.02", 0x28000, 0x20000, CRC(3fd39dde) SHA1(6a6e3ef9baa430ee83ab2312aa0221bae4d73dbd) )
	2755
	2756	ROM_REGION( 0x800000, REGION_SOUND1, 0 ) /* QSound samples */
	2757	ROM_LOAD16_WORD_SWAP( "gmd.11m", 0x000000, 0x400000, CRC(06a65542) SHA1(a1b3df70c90055a3cd59d0149fd18a74eff5bcc9) )
	2758	ROM_LOAD16_WORD_SWAP( "gmd.12m", 0x400000, 0x400000, CRC(50bc7a31) SHA1(7283569fc646c39f4c693f14e0ce7ff2ee49111a) )
	2759	ROM_END
	2760
	2761	ROM_START( dimahoou )
	2762	ROM_REGION( CODE_SIZE, REGION_CPU1, 0 ) /* 68000 code */
2740	2763	ROM_LOAD16_WORD_SWAP( "gmdu.03", 0x000000, 0x80000, CRC(43bcb15f) SHA1(8cf758f9b3b416273e5b20e5d1c09c0a67029a01) )
2741	2764	ROM_LOAD16_WORD_SWAP( "gmd.04", 0x080000, 0x80000, CRC(37485567) SHA1(643c41fce6057bcaef0e0bedc62914c33d97eeaf) )
2742	2765	ROM_LOAD16_WORD_SWAP( "gmd.05", 0x100000, 0x80000, CRC(da269ffb) SHA1(e99b04192030b6006cf67b563f40cea29c1b2e78) )
r949	r950
4691	4714	ROM_REGION( 0x1000000, REGION_GFX1, 0 )
4692	4715	ROM_FILL( 0x000000, 0x800000, 0 )
4693	4716	ROMX_LOAD( "rcm.73", 0x800000, 0x80000, CRC(774c6e04) SHA1(6bd14960218e31d5a043b20a1b9d2d69cace761e) , ROM_GROUPWORD \| ROM_SKIP(6) )
4694		ROMX_LOAD( "rcm.74", 0x880000, 0x80000, CRC(004ec725) SHA1(b1d3bcf920b0a1d0f4b59c77f5962e8162bbef65) , ROM_GROUPWORD \| ROM_SKIP(6) )
4695		ROMX_LOAD( "rcm.75", 0x900000, 0x80000, CRC(70a73f99) SHA1(6dd126b4e64e34d5911ed5877b1b94b503404249) , ROM_GROUPWORD \| ROM_SKIP(6) )
4696		ROMX_LOAD( "rcm.76", 0x980000, 0x80000, CRC(89a889ad) SHA1(1ffe112051a3afc94df1326f17ef58dc2fc531aa) , ROM_GROUPWORD \| ROM_SKIP(6) )
4697	4717	ROMX_LOAD( "rcm.63", 0x800002, 0x80000, CRC(acad7c62) SHA1(eec10990339c9fd8fdae896a5fd98d5bf0220ed1) , ROM_GROUPWORD \| ROM_SKIP(6) )
4698		ROMX_LOAD( "rcm.64", 0x880002, 0x80000, CRC(65c0464e) SHA1(4a035f4d28fc8aa72bfe0a06392b93b0abfba458) , ROM_GROUPWORD \| ROM_SKIP(6) )
4699		ROMX_LOAD( "rcm.65", 0x900002, 0x80000, CRC(ecedad3d) SHA1(dea1377f086ea3a45ced983e258beb6607b295c9) , ROM_GROUPWORD \| ROM_SKIP(6) )
4700		ROMX_LOAD( "rcm.66", 0x980002, 0x80000, CRC(1300eb7b) SHA1(db4f53b1cf521df99d073dcf0bfafe7b113e95d5) , ROM_GROUPWORD \| ROM_SKIP(6) )
4701		ROMX_LOAD( "rcm.83", 0x800002, 0x80000, CRC(6af30499) SHA1(a97bf2f382b6edc1e920e18d8ad5ca18131a2f21) , ROM_GROUPWORD \| ROM_SKIP(6) )
4702		ROMX_LOAD( "rcm.84", 0x880004, 0x80000, CRC(fb3097cc) SHA1(7bff2372809cdfa4dcd8537a448b177c0e86a94e) , ROM_GROUPWORD \| ROM_SKIP(6) )
4703		ROMX_LOAD( "rcm.85", 0x900004, 0x80000, CRC(3d6186d8) SHA1(70f1ff678dd1ec533360458a564953fc5634cbc5) , ROM_GROUPWORD \| ROM_SKIP(6) )
4704		ROMX_LOAD( "rcm.86", 0x980004, 0x80000, CRC(6d974ebd) SHA1(41de66481a64fa8a6471c512fc5dcaf96d95ee69) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4718	ROMX_LOAD( "rcm.83", 0x800004, 0x80000, CRC(6af30499) SHA1(a97bf2f382b6edc1e920e18d8ad5ca18131a2f21) , ROM_GROUPWORD \| ROM_SKIP(6) )
4705	4719	ROMX_LOAD( "rcm.93", 0x800006, 0x80000, CRC(7a5a5166) SHA1(2160015e2e43e2c024a3af56da961ac02ffc74e9) , ROM_GROUPWORD \| ROM_SKIP(6) )
4706		ROMX_LOAD( "rcm.94", 0x880006, 0x80000, CRC(2e16557a) SHA1(f4a916c1524a8de23fc6afabc8c724a89530c631) , ROM_GROUPWORD \| ROM_SKIP(6) )
4707		ROMX_LOAD( "rcm.95", 0x900006, 0x80000, CRC(8c7700f1) SHA1(84846af535e9e333e911486d545988568554b67b) , ROM_GROUPWORD \| ROM_SKIP(6) )
4708		ROMX_LOAD( "rcm.96", 0x980006, 0x80000, CRC(7da4cd24) SHA1(dd44377ff9f83f15cac032c4e7ef2071adcfa196) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4720	ROMX_LOAD( "rcm.74", 0xa00000, 0x80000, CRC(004ec725) SHA1(b1d3bcf920b0a1d0f4b59c77f5962e8162bbef65) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4721	ROMX_LOAD( "rcm.64", 0xa00002, 0x80000, CRC(65c0464e) SHA1(4a035f4d28fc8aa72bfe0a06392b93b0abfba458) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4722	ROMX_LOAD( "rcm.84", 0xa00004, 0x80000, CRC(fb3097cc) SHA1(7bff2372809cdfa4dcd8537a448b177c0e86a94e) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4723	ROMX_LOAD( "rcm.94", 0xa00006, 0x80000, CRC(2e16557a) SHA1(f4a916c1524a8de23fc6afabc8c724a89530c631) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4724	ROMX_LOAD( "rcm.75", 0xc00000, 0x80000, CRC(70a73f99) SHA1(6dd126b4e64e34d5911ed5877b1b94b503404249) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4725	ROMX_LOAD( "rcm.65", 0xc00002, 0x80000, CRC(ecedad3d) SHA1(dea1377f086ea3a45ced983e258beb6607b295c9) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4726	ROMX_LOAD( "rcm.85", 0xc00004, 0x80000, CRC(3d6186d8) SHA1(70f1ff678dd1ec533360458a564953fc5634cbc5) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4727	ROMX_LOAD( "rcm.95", 0xc00006, 0x80000, CRC(8c7700f1) SHA1(84846af535e9e333e911486d545988568554b67b) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4728	ROMX_LOAD( "rcm.76", 0xe00000, 0x80000, CRC(89a889ad) SHA1(1ffe112051a3afc94df1326f17ef58dc2fc531aa) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4729	ROMX_LOAD( "rcm.66", 0xe00002, 0x80000, CRC(1300eb7b) SHA1(db4f53b1cf521df99d073dcf0bfafe7b113e95d5) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4730	ROMX_LOAD( "rcm.86", 0xe00004, 0x80000, CRC(6d974ebd) SHA1(41de66481a64fa8a6471c512fc5dcaf96d95ee69) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4731	ROMX_LOAD( "rcm.96", 0xe00006, 0x80000, CRC(7da4cd24) SHA1(dd44377ff9f83f15cac032c4e7ef2071adcfa196) , ROM_GROUPWORD \| ROM_SKIP(6) )
4709	4732
4710	4733	ROM_REGION(QSOUND_SIZE, REGION_CPU2, 0 ) /* 64k for the audio CPU (+banks) */
4711	4734	ROM_LOAD( "rcm.01", 0x00000, 0x08000, CRC(d60cf8a3) SHA1(dccd84b93e62489c703011422d0fe84444c7f7db) )
r949	r950
4731	4754	ROM_REGION( 0x1000000, REGION_GFX1, 0 )
4732	4755	ROM_FILL( 0x000000, 0x800000, 0 )
4733	4756	ROMX_LOAD( "rcm.73", 0x800000, 0x80000, CRC(774c6e04) SHA1(6bd14960218e31d5a043b20a1b9d2d69cace761e) , ROM_GROUPWORD \| ROM_SKIP(6) )
4734		ROMX_LOAD( "rcm.74", 0x880000, 0x80000, CRC(004ec725) SHA1(b1d3bcf920b0a1d0f4b59c77f5962e8162bbef65) , ROM_GROUPWORD \| ROM_SKIP(6) )
4735		ROMX_LOAD( "rcm.75", 0x900000, 0x80000, CRC(70a73f99) SHA1(6dd126b4e64e34d5911ed5877b1b94b503404249) , ROM_GROUPWORD \| ROM_SKIP(6) )
4736		ROMX_LOAD( "rcm.76", 0x980000, 0x80000, CRC(89a889ad) SHA1(1ffe112051a3afc94df1326f17ef58dc2fc531aa) , ROM_GROUPWORD \| ROM_SKIP(6) )
4737	4757	ROMX_LOAD( "rcm.63", 0x800002, 0x80000, CRC(acad7c62) SHA1(eec10990339c9fd8fdae896a5fd98d5bf0220ed1) , ROM_GROUPWORD \| ROM_SKIP(6) )
4738		ROMX_LOAD( "rcm.64", 0x880002, 0x80000, CRC(65c0464e) SHA1(4a035f4d28fc8aa72bfe0a06392b93b0abfba458) , ROM_GROUPWORD \| ROM_SKIP(6) )
4739		ROMX_LOAD( "rcm.65", 0x900002, 0x80000, CRC(ecedad3d) SHA1(dea1377f086ea3a45ced983e258beb6607b295c9) , ROM_GROUPWORD \| ROM_SKIP(6) )
4740		ROMX_LOAD( "rcm.66", 0x980002, 0x80000, CRC(1300eb7b) SHA1(db4f53b1cf521df99d073dcf0bfafe7b113e95d5) , ROM_GROUPWORD \| ROM_SKIP(6) )
4741		ROMX_LOAD( "rcm.83", 0x800002, 0x80000, CRC(6af30499) SHA1(a97bf2f382b6edc1e920e18d8ad5ca18131a2f21) , ROM_GROUPWORD \| ROM_SKIP(6) )
4742		ROMX_LOAD( "rcm.84", 0x880004, 0x80000, CRC(fb3097cc) SHA1(7bff2372809cdfa4dcd8537a448b177c0e86a94e) , ROM_GROUPWORD \| ROM_SKIP(6) )
4743		ROMX_LOAD( "rcm.85", 0x900004, 0x80000, CRC(3d6186d8) SHA1(70f1ff678dd1ec533360458a564953fc5634cbc5) , ROM_GROUPWORD \| ROM_SKIP(6) )
4744		ROMX_LOAD( "rcm.86", 0x980004, 0x80000, CRC(6d974ebd) SHA1(41de66481a64fa8a6471c512fc5dcaf96d95ee69) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4758	ROMX_LOAD( "rcm.83", 0x800004, 0x80000, CRC(6af30499) SHA1(a97bf2f382b6edc1e920e18d8ad5ca18131a2f21) , ROM_GROUPWORD \| ROM_SKIP(6) )
4745	4759	ROMX_LOAD( "rcm.93", 0x800006, 0x80000, CRC(7a5a5166) SHA1(2160015e2e43e2c024a3af56da961ac02ffc74e9) , ROM_GROUPWORD \| ROM_SKIP(6) )
4746		ROMX_LOAD( "rcm.94", 0x880006, 0x80000, CRC(2e16557a) SHA1(f4a916c1524a8de23fc6afabc8c724a89530c631) , ROM_GROUPWORD \| ROM_SKIP(6) )
4747		ROMX_LOAD( "rcm.95", 0x900006, 0x80000, CRC(8c7700f1) SHA1(84846af535e9e333e911486d545988568554b67b) , ROM_GROUPWORD \| ROM_SKIP(6) )
4748		ROMX_LOAD( "rcm.96", 0x980006, 0x80000, CRC(7da4cd24) SHA1(dd44377ff9f83f15cac032c4e7ef2071adcfa196) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4760	ROMX_LOAD( "rcm.74", 0xa00000, 0x80000, CRC(004ec725) SHA1(b1d3bcf920b0a1d0f4b59c77f5962e8162bbef65) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4761	ROMX_LOAD( "rcm.64", 0xa00002, 0x80000, CRC(65c0464e) SHA1(4a035f4d28fc8aa72bfe0a06392b93b0abfba458) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4762	ROMX_LOAD( "rcm.84", 0xa00004, 0x80000, CRC(fb3097cc) SHA1(7bff2372809cdfa4dcd8537a448b177c0e86a94e) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4763	ROMX_LOAD( "rcm.94", 0xa00006, 0x80000, CRC(2e16557a) SHA1(f4a916c1524a8de23fc6afabc8c724a89530c631) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4764	ROMX_LOAD( "rcm.75", 0xc00000, 0x80000, CRC(70a73f99) SHA1(6dd126b4e64e34d5911ed5877b1b94b503404249) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4765	ROMX_LOAD( "rcm.65", 0xc00002, 0x80000, CRC(ecedad3d) SHA1(dea1377f086ea3a45ced983e258beb6607b295c9) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4766	ROMX_LOAD( "rcm.85", 0xc00004, 0x80000, CRC(3d6186d8) SHA1(70f1ff678dd1ec533360458a564953fc5634cbc5) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4767	ROMX_LOAD( "rcm.95", 0xc00006, 0x80000, CRC(8c7700f1) SHA1(84846af535e9e333e911486d545988568554b67b) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4768	ROMX_LOAD( "rcm.76", 0xe00000, 0x80000, CRC(89a889ad) SHA1(1ffe112051a3afc94df1326f17ef58dc2fc531aa) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4769	ROMX_LOAD( "rcm.66", 0xe00002, 0x80000, CRC(1300eb7b) SHA1(db4f53b1cf521df99d073dcf0bfafe7b113e95d5) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4770	ROMX_LOAD( "rcm.86", 0xe00004, 0x80000, CRC(6d974ebd) SHA1(41de66481a64fa8a6471c512fc5dcaf96d95ee69) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4771	ROMX_LOAD( "rcm.96", 0xe00006, 0x80000, CRC(7da4cd24) SHA1(dd44377ff9f83f15cac032c4e7ef2071adcfa196) , ROM_GROUPWORD \| ROM_SKIP(6) )
4749	4772
4750	4773	ROM_REGION(QSOUND_SIZE, REGION_CPU2, 0 ) /* 64k for the audio CPU (+banks) */
4751	4774	ROM_LOAD( "rcm.01", 0x00000, 0x08000, CRC(d60cf8a3) SHA1(dccd84b93e62489c703011422d0fe84444c7f7db) )
r949	r950
5371	5394
5372	5395	ROM_START( sfa3 )
5373	5396	ROM_REGION( CODE_SIZE, REGION_CPU1, 0 ) /* 68000 code */
	5397	ROM_LOAD16_WORD_SWAP( "sz3e_03c.03", 0x000000, 0x80000, CRC(9762b206) SHA1(fc4561ca990dd11ed2c5203540102078b721db2f) )
	5398	ROM_LOAD16_WORD_SWAP( "sz3e_04c.04", 0x080000, 0x80000, CRC(5ad3f721) SHA1(fec11cc5f63593f0181eb28ae85ad916686793eb) )
	5399	ROM_LOAD16_WORD_SWAP( "sz3.05c", 0x100000, 0x80000, CRC(57fd0a40) SHA1(bc2d5f4d57117bbf58b1adb088e00424ef489e92) )
	5400	ROM_LOAD16_WORD_SWAP( "sz3.06c", 0x180000, 0x80000, CRC(f6305f8b) SHA1(3fd1ebdbad96103aca604e950b488e52460a71ec) )
	5401	ROM_LOAD16_WORD_SWAP( "sz3.07c", 0x200000, 0x80000, CRC(6eab0f6f) SHA1(f8d093dda65cf4e8a3000dc1b96355bb03dcb495) )
	5402	ROM_LOAD16_WORD_SWAP( "sz3.08c", 0x280000, 0x80000, CRC(910c4a3b) SHA1(dbd41280f9b16ad6a5b8f12092549970349395f1) )
	5403	ROM_LOAD16_WORD_SWAP( "sz3.09c", 0x300000, 0x80000, CRC(b29e5199) SHA1(c6c215eb5aa37f678a9cafcbd8620969fb5ca12f) )
	5404	ROM_LOAD16_WORD_SWAP( "sz3.10b", 0x380000, 0x80000, CRC(deb2ff52) SHA1(0aa4722aad68a04164946c78bf05752f947b4322) )
	5405
	5406	ROM_REGION( 0x2000000, REGION_GFX1, 0 )
	5407	ROMX_LOAD( "sz3.13m", 0x0000000, 0x400000, CRC(0f7a60d9) SHA1(c69e0ee22537312909dacc86d2e4be319d54e426) , ROM_GROUPWORD \| ROM_SKIP(6) )
	5408	ROMX_LOAD( "sz3.15m", 0x0000002, 0x400000, CRC(8e933741) SHA1(f4ac4bfe830dc7df9fe4f680e4e0c053e7cbd8fe) , ROM_GROUPWORD \| ROM_SKIP(6) )
	5409	ROMX_LOAD( "sz3.17m", 0x0000004, 0x400000, CRC(d6e98147) SHA1(37f331fbb1284db446faecade6f484f58c0e1b2a) , ROM_GROUPWORD \| ROM_SKIP(6) )
	5410	ROMX_LOAD( "sz3.19m", 0x0000006, 0x400000, CRC(f31a728a) SHA1(f14136564648f006c1b74afda78349f260524b5f) , ROM_GROUPWORD \| ROM_SKIP(6) )
	5411	ROMX_LOAD( "sz3.14m", 0x1000000, 0x400000, CRC(5ff98297) SHA1(9e0ce43380b776c7a03872bafd4856f6fa60bda7) , ROM_GROUPWORD \| ROM_SKIP(6) )
	5412	ROMX_LOAD( "sz3.16m", 0x1000002, 0x400000, CRC(52b5bdee) SHA1(7918204dc457f7a146d8fb8cf7242dfed3109fd8) , ROM_GROUPWORD \| ROM_SKIP(6) )
	5413	ROMX_LOAD( "sz3.18m", 0x1000004, 0x400000, CRC(40631ed5) SHA1(c18c56822b90a71ca5fbdf3440eb2671011f3d8f) , ROM_GROUPWORD \| ROM_SKIP(6) )
	5414	ROMX_LOAD( "sz3.20m", 0x1000006, 0x400000, CRC(763409b4) SHA1(af60a5116c1ca9050366a35ea29128921867f3cc) , ROM_GROUPWORD \| ROM_SKIP(6) )
	5415
	5416	ROM_REGION( QSOUND_SIZE, REGION_CPU2, 0 ) /* 64k for the audio CPU (+banks) */
	5417	ROM_LOAD( "sz3.01", 0x00000, 0x08000, CRC(de810084) SHA1(fd0b969b732921ed8b40c16fbfa30ee09c7a7cbd) )
	5418	ROM_CONTINUE( 0x10000, 0x18000 )
	5419	ROM_LOAD( "sz3.02", 0x28000, 0x20000, CRC(72445dc4) SHA1(14fca7596ac45ba655016eef5b6120f9f9671c23) )
	5420
	5421	ROM_REGION( 0x800000, REGION_SOUND1, 0 ) /* QSound samples */
	5422	ROM_LOAD16_WORD_SWAP( "sz3.11m", 0x000000, 0x400000, CRC(1c89eed1) SHA1(649a0b0a3eb72e2e69e9fb1ac51a58b70daa39f3) )
	5423	ROM_LOAD16_WORD_SWAP( "sz3.12m", 0x400000, 0x400000, CRC(f392b13a) SHA1(fa04ce0370144a49bd1d5acd873eef87b0dc9d15) )
	5424	ROM_END
	5425
	5426	ROM_START( sfa3u )
	5427	ROM_REGION( CODE_SIZE, REGION_CPU1, 0 ) /* 68000 code */
5374	5428	ROM_LOAD16_WORD_SWAP( "sz3u.03c", 0x000000, 0x80000, CRC(e007da2e) SHA1(d190ac7ca2c27f11b9b4f96860b226bbea0ee403) )
5375	5429	ROM_LOAD16_WORD_SWAP( "sz3u.04c", 0x080000, 0x80000, CRC(5f78f0e7) SHA1(f4df30fd3515fe9f1125f470b96028052c61f57b) )
5376	5430	ROM_LOAD16_WORD_SWAP( "sz3.05c", 0x100000, 0x80000, CRC(57fd0a40) SHA1(bc2d5f4d57117bbf58b1adb088e00424ef489e92) )
r949	r950
5400	5454	ROM_LOAD16_WORD_SWAP( "sz3.12m", 0x400000, 0x400000, CRC(f392b13a) SHA1(fa04ce0370144a49bd1d5acd873eef87b0dc9d15) )
5401	5455	ROM_END
5402	5456
5403		ROM_START( sfa3r1 )
	5457	ROM_START( sfa3ur1 )
5404	5458	ROM_REGION( CODE_SIZE, REGION_CPU1, 0 ) /* 68000 code */
5405	5459	ROM_LOAD16_WORD_SWAP( "sz3u.03", 0x000000, 0x80000, CRC(b5984a19) SHA1(e225dd1d3a5d1b94adcfc5f720775e9ba321996e) )
5406	5460	ROM_LOAD16_WORD_SWAP( "sz3u.04", 0x080000, 0x80000, CRC(7e8158ba) SHA1(a9984d7c9d02a9ebaf98cfd0dcbcf26e82e904de) )
r949	r950
7234	7288	GAME( 1995, sfzh, sfa, cps2, ssf2, cps2, ROT0, "Capcom", "Street Fighter Zero (Hispanic 950627)", 0 )
7235	7289	GAME( 1995, sfzb, sfa, cps2, ssf2, cps2, ROT0, "Capcom", "Street Fighter Zero (Brazil 951109)", 0 )
7236	7290	GAME( 1995, sfzbr1, sfa, cps2, ssf2, cps2, ROT0, "Capcom", "Street Fighter Zero (Brazil 950727)", 0 )
7237		GAME( 1995, mmancp2u, megaman, cps2, sgemf, cps2, ROT0, "Capcom", "Mega Man - The Power Battle (CPS2, USA 951006)", GAME_NOT_WORKING ) // no key
7238		GAME( 1995, rmancp2j, megaman, cps2, sgemf, cps2, ROT0, "Capcom", "Rockman: The Power Battle (CPS2, Japan 950922)", GAME_NOT_WORKING ) // no key
	7291	GAME( 1995, mmancp2u, megaman, cps2, sgemf, cps2, ROT0, "Capcom", "Mega Man - The Power Battle (CPS2, USA 951006, SAMPLE Version)", 0 )
	7292	GAME( 1995, rmancp2j, megaman, cps2, sgemf, cps2, ROT0, "Capcom", "Rockman: The Power Battle (CPS2, Japan 950922)", 0 )
7239	7293	GAME( 1996, 19xx, 0, cps2, 19xx, cps2, ROT270, "Capcom", "19XX: The War Against Destiny (USA 951207)", 0 )
7240	7294	GAME( 1996, 19xxa, 19xx, cps2, 19xx, cps2, ROT270, "Capcom", "19XX: The War Against Destiny (Asia 951207)", 0 )
7241	7295	GAME( 1996, 19xxj, 19xx, cps2, 19xx, cps2, ROT270, "Capcom", "19XX: The War Against Destiny (Japan 951225)", 0 )
r949	r950
7319	7373	GAME( 1998, mvscar1, mvsc, cps2, ssf2, cps2, ROT0, "Capcom", "Marvel Vs. Capcom: Clash of Super Heroes (Asia 980112)", 0 )
7320	7374	GAME( 1998, mvsch, mvsc, cps2, ssf2, cps2, ROT0, "Capcom", "Marvel Vs. Capcom: Clash of Super Heroes (Hispanic 980123)", 0 )
7321	7375	GAME( 1998, mvscb, mvsc, cps2, ssf2, cps2, ROT0, "Capcom", "Marvel Vs. Capcom: Clash of Super Heroes (Brazil 980123)", 0 )
7322		GAME( 1998, sfa3, 0, cps2, ssf2, cps2, ROT0, "Capcom", "Street Fighter Alpha 3 (USA 980904)", 0 )
7323		GAME( 1998, sfa3r1, sfa3, cps2, ssf2, cps2, ROT0, "Capcom", "Street Fighter Alpha 3 (USA 980629)", 0 )
	7376	GAME( 1998, sfa3, 0, cps2, ssf2, cps2, ROT0, "Capcom", "Street Fighter Alpha 3 (Euro 980904)", 0 )
	7377	GAME( 1998, sfa3u, sfa3, cps2, ssf2, cps2, ROT0, "Capcom", "Street Fighter Alpha 3 (USA 980904)", 0 )
	7378	GAME( 1998, sfa3ur1, sfa3, cps2, ssf2, cps2, ROT0, "Capcom", "Street Fighter Alpha 3 (USA 980629)", 0 )
7324	7379	GAME( 1998, sfa3b, sfa3, cps2, ssf2, cps2, ROT0, "Capcom", "Street Fighter Alpha 3 (Brazil 980629)", 0 )
7325	7380	GAME( 1998, sfz3j, sfa3, cps2, ssf2, cps2, ROT0, "Capcom", "Street Fighter Zero 3 (Japan 980904)", 0 )
7326	7381	GAME( 1998, sfz3jr1, sfa3, cps2, ssf2, cps2, ROT0, "Capcom", "Street Fighter Zero 3 (Japan 980727)", 0 )
r949	r950
7349	7404
7350	7405	/* Games released on CPS-2 hardware by Eighting/Raizing */
7351	7406
7352		GAME( 2000, dimahoo, 0, cps2, sgemf, cps2, ROT270, "Eighting/Raizing, distributed by Capcom", "Dimahoo (USA 000121)", 0 )
	7407	GAME( 2000, dimahoo, 0, cps2, sgemf, cps2, ROT270, "Eighting/Raizing, distributed by Capcom", "Dimahoo (Euro 000121)", 0 )
	7408	GAME( 2000, dimahoou, dimahoo, cps2, sgemf, cps2, ROT270, "Eighting/Raizing, distributed by Capcom", "Dimahoo (USA 000121)", 0 )
7353	7409	GAME( 2000, gmahou, dimahoo, cps2, sgemf, cps2, ROT270, "Eighting/Raizing, distributed by Capcom", "Great Mahou Daisakusen (Japan 000121)", 0 )
7354	7410	GAME( 2000, 1944, 0, cps2, 19xx, cps2, ROT0, "Capcom, supported by Eighting/Raizing", "1944: The Loop Master (USA 000620)", 0 )
7355	7411	GAME( 2000, 1944j, 1944, cps2, 19xx, cps2, ROT0, "Capcom, supported by Eighting/Raizing", "1944: The Loop Master (Japan 000620)", 0 )

src/mame/drivers/scramble.c
r949	r950
3244	3244	ROM_LOAD( "prom.6e", 0x0000, 0x0020, CRC(4e3caeab) SHA1(a25083c3e36d28afdefe4af6e6d4f3155e303625) )
3245	3245	ROM_END
3246	3246
	3247
3247	3248	ROM_START( scrpiona )
3248	3249	/* this dump is bad (at least one rom) */
3249	3250	ROM_REGION( 0x10000, REGION_CPU1, 0 )
r949	r950
3298	3299	ROM_END
3299	3300
3300	3301
	3302	ROM_START( scrpionb )
	3303	ROM_REGION( 0x10000, REGION_CPU1, 0 )
	3304	ROM_LOAD( "ic109.2d", 0x0000, 0x1000, CRC(f54688c9) SHA1(2881d5238733353b9c277a2829d157688a87601b) )
	3305	ROM_LOAD( "ic110.2e", 0x1000, 0x1000, CRC(91aaaa12) SHA1(2a5e5eb5aeec5637ee4675930f67158a969e0d5d) )
	3306	ROM_LOAD( "ic111.2g", 0x2000, 0x1000, CRC(4c3720da) SHA1(5b2758c8a91f9463bf98abf2b52af946c5e90cf0) )
	3307	ROM_LOAD( "ic112.2h", 0x3000, 0x1000, CRC(53e2a983) SHA1(cfe272055a92793de76dd1cff617b13281815485) )
	3308	ROM_LOAD( "ic113.2k", 0x6000, 0x0800, CRC(e4ad299a) SHA1(712cab86eadeba9e859f7bae98eb289f00d2e217) )
	3309	ROM_CONTINUE( 0x5800, 0x0800 )
	3310
	3311	ROM_REGION( 0x10000, REGION_CPU2, 0 )
	3312	ROM_LOAD( "32_a4.7c", 0x0000, 0x1000, CRC(361b8a36) SHA1(550ac5f721aaa9fea5f6d63ba590d6b367525c23) ) // missing in this dump
	3313	ROM_LOAD( "ic13.7d", 0x1000, 0x1000, CRC(addecdd4) SHA1(ba28f1d9c7c6b5e8ecef56a4b3f64be13fc10d43) )
	3314
	3315	ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
	3316	ROM_LOAD( "ic72.5f", 0x0000, 0x1000, CRC(1e5da9d6) SHA1(ca8b27e6dd40e4ca13e7e6b5f813bafca78b62f4) )
	3317	ROM_LOAD( "ic73.5h", 0x1000, 0x1000, CRC(a57adb0a) SHA1(d97c7dc4a6c5efb59cc0148e2498156c682c6714) )
	3318
	3319	ROM_REGION( 0x3000, REGION_SOUND1, 0 ) /* Samples? / Speech? */
	3320	ROM_LOAD( "ic25.6e", 0x0000, 0x1000, CRC(04abf178) SHA1(2e7f231413d9ec461ca21840f31d1d6b8b17c4d5) )
	3321	ROM_LOAD( "ic24.6d", 0x1000, 0x1000, CRC(90352dd4) SHA1(62c261a2f2fbd8eff31d5c72cf532d5e43d86dd3) )
	3322	ROM_LOAD( "ic23.6c", 0x2000, 0x1000, CRC(3bf2452d) SHA1(7a163e0ef108dd40d3beab5e9805886e45be744b) )
	3323
	3324	ROM_REGION( 0x0020, REGION_PROMS, 0 )
	3325	ROM_LOAD( "prom.6e", 0x0000, 0x0020, CRC(4e3caeab) SHA1(a25083c3e36d28afdefe4af6e6d4f3155e303625) )
	3326	ROM_END
	3327
	3328
3301	3329	GAME( 1981, scramble, 0, fscramble,scramble, scramble, ROT90, "Konami", "Scramble", GAME_SUPPORTS_SAVE )
3302	3330	GAME( 1981, scrambls, scramble, fscramble,scramble, scrambls, ROT90, "[Konami] (Stern license)", "Scramble (Stern)", GAME_SUPPORTS_SAVE )
3303	3331	GAME( 1981, explorer, scramble, explorer, explorer, 0, ROT90, "bootleg", "Explorer", GAME_SUPPORTS_SAVE )
r949	r950
3332	3360	GAME( 198?, mimonscr, mimonkey, mimonscr, mimonscr, mimonscr, ROT90, "bootleg", "Mighty Monkey (bootleg on Scramble hardware)", GAME_SUPPORTS_SAVE )
3333	3361	GAME( 1982, scorpion, 0, scorpion, scorpion, scorpion, ROT90, "Zaccaria", "Scorpion (set 1)", GAME_IMPERFECT_SOUND \| GAME_SUPPORTS_SAVE)
3334	3362	GAME( 1982, scrpiona, scorpion, scorpion, scorpion, scorpion, ROT90, "Zaccaria", "Scorpion (set 2)", GAME_NOT_WORKING \| GAME_IMPERFECT_SOUND \| GAME_SUPPORTS_SAVE)
	3363	GAME( 1982, scrpionb, scorpion, scorpion, scorpion, scorpion, ROT90, "Zaccaria", "Scorpion (set 3)", GAME_IMPERFECT_SOUND \| GAME_SUPPORTS_SAVE)
3335	3364	GAME( 1983, ad2083, 0, ad2083, ad2083, ad2083, ROT90, "Midcoin", "A. D. 2083", GAME_IMPERFECT_SOUND \| GAME_SUPPORTS_SAVE)

src/mame/drivers/playmark.c
r949	r950
31	31	TODO:
32	32	- World Beach Volley sound is controlled by a pic16c57 whose ROM is missing for this game.
33	33
	34	- One stage in Hard Times has large white blocks instead of GFX in places, are they using an
	35	invalid tile number that should be invisible?
	36
	37	- In Hard Times the last boss appears on left side of screen as it scrolls into view, are we
	38	missing part of the X co-ordinate?
	39
34	40	***************************************************************************/
35	41
36	42	#include "driver.h"
r949	r950
838	844	32*8
839	845	};
840	846
841		static const gfx_layout hrdtimes_charlayout =
842		{
843		8,8,
844		RGN_FRAC(1,4),
845		4,
846		{ RGN_FRAC(3,4), RGN_FRAC(2,4), RGN_FRAC(1,4), RGN_FRAC(0,4) },
847		{ 0, 1, 2, 3, 4, 5, 6, 7 },
848		{ 08, 18, 28, 38, 48, 58, 68, 78 },
849		8*8
850		};
851	847
852	848	static const gfx_layout tilelayout =
853	849	{
r949	r950
944	940	{ -1 }
945	941	};
946	942
	943	static const gfx_layout hrdtimes_tilelayout =
	944	{
	945	16,16,
	946	RGN_FRAC(1,2),
	947	4,
	948	{ RGN_FRAC(2,4)+8, RGN_FRAC(2,4), RGN_FRAC(0,4)+8, RGN_FRAC(0,4) },
	949	{ 0, 1, 2, 3, 4, 5, 6, 7,
	950	1616+0, 1616+1, 1616+2, 1616+3, 1616+4, 1616+5, 1616+6, 1616+7 },
	951	{ 016, 116, 216, 316, 416, 516, 616, 716,
	952	816, 916, 1016, 1116, 1216, 1316, 1416, 1516 },
	953	32*16
	954	};
	955
	956	static const gfx_layout hrdtimes_charlayout =
	957	{
	958	8,8,
	959	RGN_FRAC(1,2),
	960	4,
	961	{ RGN_FRAC(2,4)+8, RGN_FRAC(2,4), RGN_FRAC(0,4)+8, RGN_FRAC(0,4) },
	962	{ 0, 1, 2, 3, 4, 5, 6, 7 },
	963	{ 016, 116, 216, 316, 416, 516, 616, 716 },
	964	8*16
	965	};
	966
	967
947	968	static const gfx_decode hrdtimes_gfxdecodeinfo[] =
948	969	{
949		{ REGION_GFX2, 0, &tilelayout, 0x200, 32 }, /* colors 0x200-0x2ff */
950		{ REGION_GFX1, 0, &tilelayout, 0x000, 16 }, /* colors 0x000-0x0ff */
	970	{ REGION_GFX2, 0, &hrdtimes_tilelayout, 0x200, 32 }, /* colors 0x200-0x2ff */
	971	{ REGION_GFX1, 0, &hrdtimes_tilelayout, 0x000, 16 }, /* colors 0x000-0x0ff */
951	972	{ REGION_GFX1, 0, &hrdtimes_charlayout, 0x100, 8 }, /* colors 0x100-0x17f */
952	973	{ -1 }
953	974	};
r949	r950
1342	1363	ROM_LOAD( "pic16c57-hs.i015", 0x0000, 0x2d4c, BAD_DUMP CRC(022c6941) SHA1(8ead40bfa7aa783b1ce62bd6cfa673cb876e29e7) )
1343	1364
1344	1365	ROM_REGION( 0x200000, REGION_GFX1, ROMREGION_DISPOSE )
1345		ROM_LOAD( "23.u36", 0x000000, 0x10000, CRC(ddcf60b9) SHA1(0c0fbc44131cb7d36c21bf5aead87b498c5684f5) )
1346		ROM_CONTINUE( 0x040000, 0x10000 )
1347		ROM_LOAD( "27.u42", 0x080000, 0x10000, CRC(413bbcf4) SHA1(d82ae9d26df1a69b760b3025048e47ab757d9175) )
1348		ROM_CONTINUE( 0x0c0000, 0x10000 )
1349		ROM_LOAD( "24.u39", 0x100000, 0x10000, CRC(4baa5b4c) SHA1(ee953ed9a4a45715d1ae39b5bb8b9b6505a4e95d) )
1350		ROM_CONTINUE( 0x140000, 0x10000 )
1351		ROM_LOAD( "28.u49", 0x180000, 0x10000, CRC(8df34d6a) SHA1(ca0d2ca7e0f2a302bc8b1a03c0c18ac72fe105ac) )
1352		ROM_CONTINUE( 0x1c0000, 0x10000 )
	1366	ROM_LOAD16_BYTE( "23.u36", 0x000000, 0x10000, CRC(ddcf60b9) SHA1(0c0fbc44131cb7d36c21bf5aead87b498c5684f5) )
	1367	ROM_CONTINUE( 0x080000, 0x10000 )
	1368	ROM_LOAD16_BYTE( "27.u42", 0x000001, 0x10000, CRC(413bbcf4) SHA1(d82ae9d26df1a69b760b3025048e47ab757d9175) )
	1369	ROM_CONTINUE( 0x080001, 0x10000 )
	1370	ROM_LOAD16_BYTE( "24.u39", 0x100000, 0x10000, CRC(4baa5b4c) SHA1(ee953ed9a4a45715d1ae39b5bb8b9b6505a4e95d) )
	1371	ROM_CONTINUE( 0x180000, 0x10000 )
	1372	ROM_LOAD16_BYTE( "28.u49", 0x100001, 0x10000, CRC(8df34d6a) SHA1(ca0d2ca7e0f2a302bc8b1a03c0c18ac72fe105ac) )
	1373	ROM_CONTINUE( 0x180001, 0x10000 )
1353	1374
1354	1375	ROM_REGION( 0x80000, REGION_GFX2, ROMREGION_DISPOSE )
1355		ROM_LOAD( "26.u34", 0x00000, 0x20000, CRC(ff8d3b75) SHA1(5427b70a61dee4c125877e040be21cb1cadb1af5) )
1356		ROM_LOAD( "30.u85", 0x20000, 0x20000, CRC(87a640c7) SHA1(818ff3243cb3ed0189988348e6c2e954f0d3dd4f) )
1357		ROM_LOAD( "25.u35", 0x40000, 0x20000, CRC(c4fd4445) SHA1(ab0c5a328a312740595b5c92a1050527140518f3) )
1358		ROM_LOAD( "29.u83", 0x60000, 0x20000, CRC(0bebfb53) SHA1(d4342f808141b70af98c370004153a31d120e2a4) )
	1376	ROM_LOAD16_BYTE( "26.u34", 0x00000, 0x20000, CRC(ff8d3b75) SHA1(5427b70a61dee4c125877e040be21cb1cadb1af5) )
	1377	ROM_LOAD16_BYTE( "30.u85", 0x00001, 0x20000, CRC(87a640c7) SHA1(818ff3243cb3ed0189988348e6c2e954f0d3dd4f) )
	1378	ROM_LOAD16_BYTE( "25.u35", 0x40000, 0x20000, CRC(c4fd4445) SHA1(ab0c5a328a312740595b5c92a1050527140518f3) )
	1379	ROM_LOAD16_BYTE( "29.u83", 0x40001, 0x20000, CRC(0bebfb53) SHA1(d4342f808141b70af98c370004153a31d120e2a4) )
1359	1380
1360	1381	ROM_REGION( 0xc0000, REGION_SOUND1, 0 ) /* Samples */
1361	1382	ROM_LOAD( "20.io13", 0x00000, 0x40000, CRC(0bf3a3e5) SHA1(2ae06f37a6bcd20bc5fbaa90d970aba2ebf3cf5a) )
r949	r950
1370	1391	ROM_LOAD( "pic16c57", 0x0000, 0x1000, NO_DUMP )
1371	1392
1372	1393	ROM_REGION( 0x200000, REGION_GFX1, ROMREGION_DISPOSE )
1373		ROM_LOAD( "33.u36", 0x000000, 0x80000, CRC(d1239ce5) SHA1(8e966a39a47f66c5e904ec4357c751e896ed47cb) )
1374		ROM_LOAD( "37.u42", 0x080000, 0x80000, CRC(aa692005) SHA1(1e274da358a25ceebdc71cb8f7228ef39348a895) )
1375		ROM_LOAD( "34.u39", 0x100000, 0x80000, CRC(e4108c59) SHA1(15f7b53a7bbdc4aefdae31a00be64c419326bfd1) )
1376		ROM_LOAD( "38.u45", 0x180000, 0x80000, CRC(ff7cacf3) SHA1(5ed93e86fe3b0b594bdd62e314cd9e2ffd3c2a2a) )
	1394	ROM_LOAD16_BYTE( "33.u36", 0x000000, 0x80000, CRC(d1239ce5) SHA1(8e966a39a47f66c5e904ec4357c751e896ed47cb) )
	1395	ROM_LOAD16_BYTE( "37.u42", 0x000001, 0x80000, CRC(aa692005) SHA1(1e274da358a25ceebdc71cb8f7228ef39348a895) )
	1396	ROM_LOAD16_BYTE( "34.u39", 0x100000, 0x80000, CRC(e4108c59) SHA1(15f7b53a7bbdc4aefdae31a00be64c419326bfd1) )
	1397	ROM_LOAD16_BYTE( "38.u45", 0x100001, 0x80000, CRC(ff7cacf3) SHA1(5ed93e86fe3b0b594bdd62e314cd9e2ffd3c2a2a) )
1377	1398
1378	1399	ROM_REGION( 0x200000, REGION_GFX2, ROMREGION_DISPOSE )
1379		ROM_LOAD( "36.u86", 0x000000, 0x80000, CRC(f2fc1ca3) SHA1(f70913d9b89338932e62ca6bb60e5f5e412d7f64) )
1380		ROM_LOAD( "40.u85", 0x080000, 0x80000, CRC(368c15f4) SHA1(8ae95fd672448921964c4d0312d7366903362e27) )
1381		ROM_LOAD( "35.u84", 0x100000, 0x80000, CRC(7bde46ec) SHA1(1d26d268e1fc937e23ae7d93a1f86386b899a0c2) )
1382		ROM_LOAD( "39.u83", 0x180000, 0x80000, CRC(a0bae586) SHA1(0b2bb0c5c51b2717b820f0176d5775df21652667) )
	1400	ROM_LOAD16_BYTE( "36.u86", 0x000000, 0x80000, CRC(f2fc1ca3) SHA1(f70913d9b89338932e62ca6bb60e5f5e412d7f64) )
	1401	ROM_LOAD16_BYTE( "40.u85", 0x000001, 0x80000, CRC(368c15f4) SHA1(8ae95fd672448921964c4d0312d7366903362e27) )
	1402	ROM_LOAD16_BYTE( "35.u84", 0x100000, 0x80000, CRC(7bde46ec) SHA1(1d26d268e1fc937e23ae7d93a1f86386b899a0c2) )
	1403	ROM_LOAD16_BYTE( "39.u83", 0x100001, 0x80000, CRC(a0bae586) SHA1(0b2bb0c5c51b2717b820f0176d5775df21652667) )
1383	1404
1384	1405	ROM_REGION( 0x80000, REGION_USER2, 0 ) /* OKIM6295 samples */
1385	1406	ROM_LOAD( "30.id13", 0x00000, 0x80000, CRC(fa5e50ae) SHA1(f3bd87c83fca9269cc2f19db1fbf55540c96f931) )
r949	r950
1395	1416	ROM_COPY( REGION_USER2, 0x060000, 0x0a0000, 0x020000)
1396	1417	ROM_END
1397	1418
	1419	/* Different revision of the PCB, uses larger gfx ROMs, however the content is the same */
	1420
	1421	ROM_START( hrdtimea )
	1422	ROM_REGION( 0x100000, REGION_CPU1, 0 ) /* 68000 code */
	1423	ROM_LOAD16_BYTE( "u67.bin", 0x00000, 0x80000, CRC(3e1334cb) SHA1(9523c04f92371a35c297280b42b1604e23790a1e) )
	1424	ROM_LOAD16_BYTE( "u66.bin", 0x00001, 0x80000, CRC(041ec30a) SHA1(00476ebd0a64cbd027be159cae7666d2df6d11ba) )
	1425
	1426	ROM_REGION( 0x1000, REGION_CPU2, ROMREGION_ERASE00 ) /* sound (PIC16C57) */
	1427	ROM_LOAD( "pic16c57", 0x0000, 0x1000, NO_DUMP )
	1428
	1429	ROM_REGION( 0x200000, REGION_GFX1, ROMREGION_DISPOSE )
	1430	ROM_LOAD( "fh1_playmark_ht", 0x000000, 0x100000, CRC(3cca02b0) SHA1(22c57f4192bf81dd26caa6adfb1c80665bdc305c) )
	1431	ROM_LOAD( "fh2_playmark_th", 0x100000, 0x100000, CRC(ed699acd) SHA1(23cf1da4e7462f7434e946a80bdd6df0395b3059) )
	1432
	1433	ROM_REGION( 0x200000, REGION_GFX2, ROMREGION_DISPOSE )
	1434	ROM_LOAD( "mh1_playmark_ht", 0x000000, 0x100000, CRC(927e5989) SHA1(b01444a3ff57cc2e10594e23c0343c956ed3ee32) )
	1435	ROM_LOAD( "mh2_playmark_ht", 0x100000, 0x100000, CRC(e76f001b) SHA1(217c06ca3618275c22e33cfe318ec6c970d4862c) )
	1436
	1437	ROM_REGION( 0x80000, REGION_USER2, 0 ) /* OKIM6295 samples */
	1438	ROM_LOAD( "io13.bin", 0x00000, 0x80000, CRC(fa5e50ae) SHA1(f3bd87c83fca9269cc2f19db1fbf55540c96f931) )
	1439
	1440	/* $00000-$20000 stays the same in all sound banks, */
	1441	/* the second half of the bank is what gets switched */
	1442	ROM_REGION( 0xc0000, REGION_SOUND1, 0 ) /* Samples */
	1443	ROM_COPY( REGION_USER2, 0x000000, 0x000000, 0x020000)
	1444	ROM_COPY( REGION_USER2, 0x020000, 0x020000, 0x020000)
	1445	ROM_COPY( REGION_USER2, 0x000000, 0x040000, 0x020000)
	1446	ROM_COPY( REGION_USER2, 0x040000, 0x060000, 0x020000)
	1447	ROM_COPY( REGION_USER2, 0x000000, 0x080000, 0x020000)
	1448	ROM_COPY( REGION_USER2, 0x060000, 0x0a0000, 0x020000)
	1449	ROM_END
	1450
	1451
1398	1452	static UINT8 playmark_asciitohex(UINT8 data)
1399	1453	{
1400	1454	/* Convert ASCII data to HEX */
r949	r950
1475	1529	GAME( 1995, wbeachv2, wbeachvl, wbeachvl, wbeachvl, 0, ROT0, "Playmark", "World Beach Volley (set 2)", GAME_NO_COCKTAIL \| GAME_NO_SOUND )
1476	1530	GAME( 1996, excelsr, 0, excelsr, excelsr, bigtwin, ROT0, "Playmark", "Excelsior", 0 )
1477	1531	GAME( 1995, hotmind, 0, hotmind, hotmind, bigtwin, ROT0, "Playmark", "Hot Mind", 0 )
1478		GAME( 1994, hrdtimes, 0, hrdtimes, hrdtimes, 0, ROT0, "Playmark", "Hard Times", GAME_NO_SOUND )
	1532	GAME( 1994, hrdtimes, 0, hrdtimes, hrdtimes, 0, ROT0, "Playmark", "Hard Times (set 1)", GAME_NO_SOUND )
	1533	GAME( 1994, hrdtimea, hrdtimes, hrdtimes, hrdtimes, 0, ROT0, "Playmark", "Hard Times (set 2)", GAME_NO_SOUND )

src/mame/drivers/speglsht.c
r949	r950
1	1	/*
2	2	Super Eagle Shot
3		(c)1993 Seta (distributed by Visco)
	3	(c)1994 Seta (distributed by Visco)
4	4	-----------------------------------
5	5	driver by Tomasz Slanina
6	6
r949	r950
306	306
307	307	ROM_START( speglsht )
308	308	ROM_REGION( 0x210000, REGION_CPU1, 0 )
309		ROM_LOAD( "sx004-07", 0x010000, 0x200000, CRC(2d759cc4) SHA1(9fedd829190b2aab850b2f1088caaec91e8715dd) )
310
	309	ROM_LOAD( "sx004-07.u70", 0x010000, 0x200000, CRC(2d759cc4) SHA1(9fedd829190b2aab850b2f1088caaec91e8715dd) ) /* Noted as "ZPRO0" IE: Z80 (ST0016) Program 0 */
	310	/* U71 unpopulated, Noted as ZPRO1 */
311	311	ROM_COPY( REGION_CPU1, 0x10000, 0x00000, 0x08000 )
312	312
313	313	ROM_REGION32_BE( 0x200000, REGION_USER1, 0 )
314		ROM_LOAD32_BYTE( "sx004-04.u33", 0x00000, 0x80000, CRC(e46d2e57) SHA1(b1fb836ab2ce547dc2e8d1046d7ef835b87bb04e) )
315		ROM_LOAD32_BYTE( "sx004-03.u32", 0x00001, 0x80000, CRC(c6ffb00e) SHA1(f57ef45bb5c690c3e63101a36835d2687abfcdbd) )
316		ROM_LOAD32_BYTE( "sx004-02.u31", 0x00002, 0x80000, CRC(21eb46e4) SHA1(0ab21ed012c9a76e01c83b60c6f4670836dfa718) )
317		ROM_LOAD32_BYTE( "sx004-01.u30", 0x00003, 0x80000, CRC(65646949) SHA1(74931c230f4e4b1008fbc5fba169292e216aa23b) )
	314	ROM_LOAD32_BYTE( "sx004-04.u33", 0x00000, 0x80000, CRC(e46d2e57) SHA1(b1fb836ab2ce547dc2e8d1046d7ef835b87bb04e) ) /* Noted as "RPRO3" IE: R3000 Program 3 */
	315	ROM_LOAD32_BYTE( "sx004-03.u32", 0x00001, 0x80000, CRC(c6ffb00e) SHA1(f57ef45bb5c690c3e63101a36835d2687abfcdbd) ) /* Noted as "RPRO2" */
	316	ROM_LOAD32_BYTE( "sx004-02.u31", 0x00002, 0x80000, CRC(21eb46e4) SHA1(0ab21ed012c9a76e01c83b60c6f4670836dfa718) ) /* Noted as "RPRO1" */
	317	ROM_LOAD32_BYTE( "sx004-01.u30", 0x00003, 0x80000, CRC(65646949) SHA1(74931c230f4e4b1008fbc5fba169292e216aa23b) ) /* Noted as "RPRO0" */
318	318
319	319	ROM_REGION( 0x200000, REGION_USER2,0)
320		ROM_LOAD32_WORD( "sx004-05.rd0", 0x000000, 0x100000, CRC(f3c69468) SHA1(81daef6d0596cb67bb6f87b39874aae1b1ffe6a6) )
321		ROM_LOAD32_WORD( "sx004-06", 0x000002, 0x100000, CRC(5af78e44) SHA1(0131d50348fef80c2b100d74b7c967c6a710d548) )
	320	ROM_LOAD32_WORD( "sx004-05.u34", 0x000000, 0x100000, CRC(f3c69468) SHA1(81daef6d0596cb67bb6f87b39874aae1b1ffe6a6) ) /* Noted as "RD0" IE: R3000 Data 0 */
	321	ROM_LOAD32_WORD( "sx004-06.u35", 0x000002, 0x100000, CRC(5af78e44) SHA1(0131d50348fef80c2b100d74b7c967c6a710d548) ) /* Noted as "RD1" */
322	322
323	323	ROM_END
324	324
325	325
326		ROM_START( speglsha )
327		ROM_REGION( 0x210000, REGION_CPU1, 0 )
328		ROM_LOAD( "sx004-07", 0x10000, 0x200000, CRC(2d759cc4) SHA1(9fedd829190b2aab850b2f1088caaec91e8715dd) )
329		ROM_COPY( REGION_CPU1, 0x10000, 0x00000, 0x08000 )
330	326
331		ROM_REGION32_BE( 0x200000, REGION_USER1, 0 )
332		ROM_LOAD32_BYTE( "sx004-04.u33", 0x00000, 0x80000, CRC(e46d2e57) SHA1(b1fb836ab2ce547dc2e8d1046d7ef835b87bb04e) )
333		ROM_LOAD32_BYTE( "sx004-03.u32", 0x00001, 0x80000, CRC(c6ffb00e) SHA1(f57ef45bb5c690c3e63101a36835d2687abfcdbd) )
334		ROM_LOAD32_BYTE( "sx004-02.u31", 0x00002, 0x80000, CRC(21eb46e4) SHA1(0ab21ed012c9a76e01c83b60c6f4670836dfa718) )
335		ROM_LOAD32_BYTE( "sx004-01.u30", 0x00003, 0x80000, CRC(65646949) SHA1(74931c230f4e4b1008fbc5fba169292e216aa23b) )
336
337		ROM_REGION( 0x200000, REGION_USER2,0)
338		ROM_LOAD( "sx004-05.rd0", 0x000000, 0x100000, CRC(f3c69468) SHA1(81daef6d0596cb67bb6f87b39874aae1b1ffe6a6) )
339		ROM_LOAD( "sx004-06", 0x100000, 0x100000, CRC(5af78e44) SHA1(0131d50348fef80c2b100d74b7c967c6a710d548) )
340		ROM_END
341
342
343
344	327	static DRIVER_INIT(speglsht)
345	328	{
346	329	st0016_game=3;
347	330	}
348	331
349	332
350		GAME( 1994, speglsht, 0, speglsht, speglsht, speglsht, ROT0, "Seta", "Super Eagle Shot", GAME_IMPERFECT_GRAPHICS)
351		GAME( 1994, speglsha, speglsht, speglsht, speglsht, speglsht, ROT0, "Seta", "Super Eagle Shot (set 2)",GAME_NOT_WORKING)
	333	GAME( 1994, speglsht, 0, speglsht, speglsht, speglsht, ROT0, "Seta", "Super Eagle Shot", GAME_IMPERFECT_GRAPHICS )

src/mame/drivers/rockola.c
r949	r950
1219	1219	ROM_LOAD( "zarz134.54", 0x0800, 0x0800, CRC(580934d2) SHA1(c1c7eba56bca2a0ea6a68c0245b071a3308f92bd) )
1220	1220	ROM_END
1221	1221
	1222	ROM_START( satansaa )
	1223	ROM_REGION( 0x10000, REGION_CPU1, 0 )
	1224	ROM_LOAD( "ic7.bin", 0x4000, 0x0800, CRC(549dd13a) SHA1(06b55d0b1da84bef30857faa398aabfd04365eb6) )
	1225	ROM_LOAD( "ic8.bin", 0x4800, 0x0800, CRC(04972fa8) SHA1(89833a7c893168acd5599ca7ad4b33a8f3df40c5) )
	1226	ROM_LOAD( "ic9.bin", 0x5000, 0x0800, CRC(9caf9057) SHA1(26d439678e5e4d375ffac60126f45de599575bfd) )
	1227	ROM_LOAD( "ic10.bin", 0x5800, 0x0800, CRC(e1bdcfe1) SHA1(c99457c18fae8de79bbbe6bc0471fdc83f1e9b19) )
	1228	ROM_LOAD( "ic13.bin", 0x6000, 0x0800, CRC(d454de19) SHA1(ae8abb8a9d999d11ba6ad341bf635ae822d5746f) )
	1229	ROM_LOAD( "ic14.bin", 0x6800, 0x0800, CRC(7fbd5d30) SHA1(be0554ade440bf255131466ee8bd2905d3f446a8) )
	1230	ROM_LOAD( "ic15.bin", 0x7000, 0x0800, CRC(93ea2df9) SHA1(4f7d076deef1e14b568b06974194861d3789ab5c) )
	1231	ROM_LOAD( "ic16.bin", 0x7800, 0x0800, CRC(9ec5fe09) SHA1(ab50373b330f21f7f64657e088ba6968a3176be4) ) // different
	1232	ROM_RELOAD( 0xf800, 0x0800 ) /* for the reset/interrupt vectors */
	1233	ROM_LOAD( "ic22.bin", 0x8000, 0x0800, CRC(21092f1f) SHA1(dd8be669cd7a51ec84e020d0a7fa50708155d084) ) // different
	1234	ROM_LOAD( "ic23.bin", 0x8800, 0x0800, CRC(8f1b313a) SHA1(0c7832505a1287533d9b2d7f2d54000b3b44e40d) )
	1235	ROM_LOAD( "ic24.bin", 0x9000, 0x0800, CRC(e74f98e0) SHA1(89a93de6105195e0e5d255bfa240538ded155fb9) )
	1236
	1237	ROM_REGION( 0x1000, REGION_GFX1, ROMREGION_DISPOSE )
	1238	ROM_LOAD( "ic73.bin", 0x0000, 0x0800, CRC(e837c62b) SHA1(97552b1e413a3934f4dc5a6fc9fc1fa8ba7a2e7e) )
	1239	ROM_LOAD( "ic75.bin", 0x0800, 0x0800, CRC(83f61623) SHA1(4cb28f85f32d13bfa364c376ea3e30fd451b5884) )
	1240
	1241	ROM_REGION( 0x0020, REGION_PROMS, 0 )
	1242	ROM_LOAD( "zarz138.03", 0x0000, 0x0020, CRC(5dd6933a) SHA1(417d827d9e47b6db01fecc2164e5ef332d4cd70e) )
	1243
	1244	ROM_REGION( 0x1000, REGION_SOUND1, 0 ) /* sound data for Vanguard-style audio section */
	1245	ROM_LOAD( "ic53.bin", 0x0000, 0x0800, CRC(8cb95a6b) SHA1(41d3986f1c2876a914b0087127ae99e9a2b41564) ) // different
	1246	ROM_LOAD( "ic54.bin", 0x0800, 0x0800, CRC(580934d2) SHA1(c1c7eba56bca2a0ea6a68c0245b071a3308f92bd) )
	1247	ROM_END
	1248
1222	1249	ROM_START( zarzon )
1223	1250	ROM_REGION( 0x10000, REGION_CPU1, 0 )
1224	1251	ROM_LOAD( "zarz122.07", 0x4000, 0x0800, CRC(bdfa67e2) SHA1(0de06cf53ee21b8f14b933b61e6dc706338746c4) )
r949	r950
1574	1601	/* Game Drivers */
1575	1602
1576	1603	GAME( 1980, sasuke, 0, sasuke, sasuke, 0, ROT90, "SNK", "Sasuke vs. Commander", 0 )
1577		GAME( 1981, satansat, 0, satansat, satansat, 0, ROT90, "SNK", "Satan of Saturn", GAME_IMPERFECT_SOUND )
	1604	GAME( 1981, satansat, 0, satansat, satansat, 0, ROT90, "SNK", "Satan of Saturn (set 1)", GAME_IMPERFECT_SOUND )
	1605	GAME( 1981, satansaa, satansat, satansat, satansat, 0, ROT90, "SNK", "Satan of Saturn (set 2)", GAME_IMPERFECT_SOUND )
1578	1606	GAME( 1981, zarzon, satansat, satansat, satansat, 0, ROT90, "[SNK] (Taito America license)", "Zarzon", GAME_IMPERFECT_SOUND )
1579	1607	GAME( 1981, vanguard, 0, vanguard, vanguard, 0, ROT90, "SNK", "Vanguard (SNK)", 0 )
1580	1608	GAME( 1981, vangrdce, vanguard, vanguard, vanguard, 0, ROT90, "SNK (Centuri license)", "Vanguard (Centuri)", 0 )

src/mame/drivers/wheelfir.c
r949	r950
39	39
40	40	uses a blitter for the gfx, this is not fully understood...
41	41
42		interrupts are guessed / wrong, probably also related to the blitter.
	42	level 5 interrupt = raster interrupt, used for road
	43	level 3 interrupt = vblank interrupt
	44	level 1 interrupt = blitter interrupt
43	45
44	46	something is missing, currently needs a hack to boot
45	47
r949	r950
146	148
147	149	/* it draws the background and road with direct writes to port 6... but where does this really go? an extra blit source page? */
148	150	static int wheelfir_six_pos = 0;
	151	static mame_bitmap* render_bitmap;
149	152
150	153	static WRITE16_HANDLER(wheelfir_blit_w)
151	154	{
r949	r950
175	178	/* probably wrong, see above! */
176	179	if(offset==0xf && data==0xffff)
177	180	{
	181
	182
178	183	int x,y;
179	184	int xsize,ysize;
180	185	UINT8 *rom = memory_region(REGION_GFX1);
r949	r950
206	211	xsize=0x100-xsize;
207	212	}
208	213
209		for(y=0;y<=ysize/((wheelfir_blitdata[9]?wheelfir_blitdata[9]:16)/;y++)
210		for(x=0;x<=xsize/(wheelfir_blitdata[9]?wheelfir_blitdata[9]:16)/;x++)
	214	for(y=0;y<=ysize+1/((wheelfir_blitdata[9]?wheelfir_blitdata[9]:16)/;y++)
	215	for(x=0;x<=xsize+1/(wheelfir_blitdata[9]?wheelfir_blitdata[9]:16)/;x++)
211	216	{
212	217	int destx=wheelfir_blitdata[0]&0xff;
213	218	int desty=wheelfir_blitdata[2]&0xff;
r949	r950
256	261	pix = rom[offs];
257	262
258	263
259		if(pix && destx<Machine->screen[0].width && desty <Machine->screen[0].height)
	264	if(pix && destx >0 && desty >0 && destx<Machine->screen[0].width && desty <Machine->screen[0].height)
260	265	*BITMAP_ADDR16(wheelfir_tmp_bitmap[vpage], desty, destx) = pix;
261	266	}
262	267	}
r949	r950
271	276	wheelfir_tmp_bitmap[0] = auto_bitmap_alloc(machine->screen[0].width,machine->screen[0].height,machine->screen[0].format);
272	277	wheelfir_tmp_bitmap[1] = auto_bitmap_alloc(machine->screen[0].width,machine->screen[0].height,machine->screen[0].format);
273	278	wheelfir_tmp_bitmap[2] = auto_bitmap_alloc(machine->screen[0].width,machine->screen[0].height,machine->screen[0].format);
	279
	280	render_bitmap = auto_bitmap_alloc(machine->screen[0].width,machine->screen[0].height,machine->screen[0].format);
	281
274	282	}
275	283
276	284	static UINT8 wheelfir_palette[8192];
r949	r950
278	286	/* Press R to show a page of gfx, Q / E to move between pages, and W to clear the framebuffer */
279	287	VIDEO_UPDATE(wheelfir)
280	288	{
281		int x,y;
282		static int base = 0;
	289	/*
	290	int x,y;
	291	static int base = 0;
283	292
284		if ( input_code_pressed_once(KEYCODE_E) )
285		base += 512*512;
	293	if ( input_code_pressed_once(KEYCODE_E) )
	294	base += 512*512;
286	295
287		if ( input_code_pressed_once(KEYCODE_Q) )
288		base -= 512*512;
	296	if ( input_code_pressed_once(KEYCODE_Q) )
	297	base -= 512*512;
289	298
290		if (base<0x000000) base = 0x000000;
291		if (base>0x3c0000) base = 0x3c0000;
	299	if (base<0x000000) base = 0x000000;
	300	if (base>0x3c0000) base = 0x3c0000;
292	301
293		copybitmap(bitmap, wheelfir_tmp_bitmap[2], 0, 0, 0, 0, cliprect, TRANSPARENCY_NONE, 0);
294		//copybitmap(bitmap, wheelfir_tmp_bitmap[1], 0, 0, 0, 0, cliprect, TRANSPARENCY_PEN, 0);
295		copybitmap(bitmap, wheelfir_tmp_bitmap[0], 0, 0, 0, 0, cliprect, TRANSPARENCY_PEN, 0);
296		fillbitmap(wheelfir_tmp_bitmap[0], 0,&machine->screen[0].visarea);
	302	copybitmap(bitmap, wheelfir_tmp_bitmap[2], 0, 0, 0, 0, cliprect, TRANSPARENCY_NONE, 0);
	303	//copybitmap(bitmap, wheelfir_tmp_bitmap[1], 0, 0, 0, 0, cliprect, TRANSPARENCY_PEN, 0);
	304	copybitmap(bitmap, wheelfir_tmp_bitmap[0], 0, 0, 0, 0, cliprect, TRANSPARENCY_PEN, 0);
	305	fillbitmap(wheelfir_tmp_bitmap[0], 0,&machine->screen[0].visarea);
297	306
298		if ( input_code_pressed(KEYCODE_R) )
299		{
300		for (y=0;y<128;y++)
301		{
302		for (x=0;x<512;x++)
303		{
304		int romoffs;
305		UINT8 romdata;
	307	if ( input_code_pressed(KEYCODE_R) )
	308	{
	309	for (y=0;y<128;y++)
	310	{
	311	for (x=0;x<512;x++)
	312	{
	313	int romoffs;
	314	UINT8 romdata;
306	315
307		romoffs = base+y*512+x;
	316	romoffs = base+y*512+x;
308	317
309		romdata = memory_region(REGION_GFX1)[romoffs];
	318	romdata = memory_region(REGION_GFX1)[romoffs];
310	319
311		*BITMAP_ADDR16(bitmap, y, x) = romdata;
312		}
313		}
314		}
	320	*BITMAP_ADDR16(bitmap, y, x) = romdata;
	321	}
	322	}
	323	}
	324	*/
315	325
316		for (x=0;x<8192;x+=3)
	326	copybitmap(bitmap, render_bitmap, 0, 0, 0, 0, cliprect, TRANSPARENCY_NONE, 0);
	327	copybitmap(bitmap, wheelfir_tmp_bitmap[0], 0, 0, 0, 0, cliprect, TRANSPARENCY_PEN, 0);
	328
317	329	{
318		//int paldat = (wheelfir_palette[x]<<8) \| wheelfir_palette[x+1];
319		int b,g,r;
	330	int x;
	331	for (x=0;x<8192;x+=3)
	332	{
	333	//int paldat = (wheelfir_palette[x]<<8) \| wheelfir_palette[x+1];
	334	int b,g,r;
320	335
321		r = wheelfir_palette[x];
322		g = wheelfir_palette[x+1];
323		b = wheelfir_palette[x+2];
324		palette_set_color(machine,x/3,MAKE_RGB(r,g,b));
325
	336	r = wheelfir_palette[x];
	337	g = wheelfir_palette[x+1];
	338	b = wheelfir_palette[x+2];
	339	palette_set_color(machine,x/3,MAKE_RGB(r,g,b));
	340	}
326	341	}
327
328	342	/*
329	343	{
330	344	FILE* fp;
r949	r950
336	350	}
337	351	}
338	352	*/
	353
339	354	return 0;
340	355	}
341	356
r949	r950
522	537	PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
523	538	INPUT_PORTS_END
524	539
	540	static mame_timer* frame_timer;
	541	static mame_timer* scanline_timer;
525	542
	543	static TIMER_CALLBACK( frame_timer_callback )
	544	{
	545	/* callback */
	546	}
526	547
527		static INTERRUPT_GEN( wheelfir_irq )
	548	static int scanline_counter = 0;
	549	static int total_scanlines = 262;
	550
	551	void render_background_to_render_buffer(int scanline)
528	552	{
529		switch ( cpu_getiloops() )
	553	int x;
	554	UINT16 yscroll = (wheelfir_blitdata[0xb]&0x00ff) \| (wheelfir_blitdata[0x8]&0x0080) << 1;
	555	UINT16 xscroll = (wheelfir_blitdata[0xa]&0x00ff) \| (wheelfir_blitdata[0x8]&0x0040) << 2;
	556
	557	UINT16 *source = BITMAP_ADDR16(wheelfir_tmp_bitmap[2], (scanline+yscroll)&511, 0);
	558	UINT16 *dest = BITMAP_ADDR16(render_bitmap, scanline, 0);
	559
	560	// if (scanline==100)
	561	// printf("%04x %04x %04x %04x\n", wheelfir_blitdata[0x8],wheelfir_blitdata[0x9],wheelfir_blitdata[0xa],wheelfir_blitdata[0xb]);
	562
	563	for (x=0;x<336;x++)
530	564	{
531		case 0:
532		cpunum_set_input_line(0, 3, HOLD_LINE);
533		break;
534		case 1:
535		cpunum_set_input_line(0, 5, HOLD_LINE);
536		toggle_bit ^= 0x8000; // must toggle..
537		break;
538		default:
539		cpunum_set_input_line(0, 1, HOLD_LINE);
540		break;
	565	dest[x] = source[ (x+xscroll) &511];
541	566	}
	567
542	568	}
543	569
	570	static TIMER_CALLBACK( scanline_timer_callback )
	571	{
	572	timer_call_after_resynch(0, 0);
544	573
	574	if (scanline_counter!=(total_scanlines-1))
	575	{
	576	scanline_counter++;
	577	cpunum_set_input_line(0, 5, HOLD_LINE); // raster IRQ, changes scroll values for road
	578	mame_timer_adjust(scanline_timer, scale_down_mame_time(MAME_TIME_IN_HZ(60), total_scanlines), 0, time_zero);
	579
	580	if (scanline_counter<256)
	581	{
	582	render_background_to_render_buffer(scanline_counter);
	583	}
	584
	585	if (scanline_counter==256)
	586	{
	587	cpunum_set_input_line(0, 3, HOLD_LINE); // vblank IRQ?
	588	toggle_bit = 0x8000; // must toggle..
	589	}
	590
	591	if (scanline_counter==0)
	592	{
	593	toggle_bit = 0x0000; // must toggle..
	594	}
	595
	596	// printf("scanline %d\n",scanline_counter);
	597	}
	598	else /* pretend we're still on the same scanline to compensate for rounding errors */
	599	{
	600	scanline_counter = total_scanlines-1;
	601	}
	602	}
	603
	604	static VIDEO_EOF( wheelfir )
	605	{
	606	scanline_counter = -1;
	607	fillbitmap(wheelfir_tmp_bitmap[0], 0,&machine->screen[0].visarea);
	608
	609	mame_timer_adjust(frame_timer, time_zero, 0, time_zero);
	610	mame_timer_adjust(scanline_timer, time_zero, 0, time_zero);
	611	}
	612
	613	static MACHINE_RESET(wheelfir)
	614	{
	615	frame_timer = mame_timer_alloc(frame_timer_callback);
	616	scanline_timer = mame_timer_alloc(scanline_timer_callback);
	617	mame_timer_adjust(frame_timer, time_zero, 0, time_zero);
	618	mame_timer_adjust(scanline_timer, time_zero, 0, time_zero);
	619	scanline_counter = -1;
	620	}
	621
	622	static INTERRUPT_GEN( wheelfir_irq )
	623	{
	624	// we seem to need this interrupt at least once for every object drawn on the screen, otherwise things flicker + slowdown
	625	cpunum_set_input_line(0, 1, HOLD_LINE); // blitter IRQ?
	626	}
	627
	628
545	629	static MACHINE_DRIVER_START( wheelfir )
546		MDRV_CPU_ADD_TAG("main", M68000, 32000000/2)
	630	MDRV_CPU_ADD_TAG("main", M68000, 32000000)
547	631	MDRV_CPU_PROGRAM_MAP(wheelfir_main, 0)
548		MDRV_CPU_VBLANK_INT(wheelfir_irq,30) // 1,3,5 valid
	632	MDRV_CPU_VBLANK_INT(wheelfir_irq,256) // 1,3,5 valid
549	633
550	634	MDRV_CPU_ADD_TAG("main", M68000, 32000000/2)
551	635	MDRV_CPU_PROGRAM_MAP(wheelfir_sub, 0)
r949	r950
555	639	MDRV_SCREEN_REFRESH_RATE(60)
556	640	MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
557	641
	642	MDRV_MACHINE_RESET (wheelfir)
	643
558	644	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
559	645	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
560	646	MDRV_SCREEN_SIZE(648, 648)
r949	r950
564	650
565	651	MDRV_VIDEO_START(wheelfir)
566	652	MDRV_VIDEO_UPDATE(wheelfir)
	653	MDRV_VIDEO_EOF(wheelfir)
567	654	MACHINE_DRIVER_END
568	655
569	656

src/mame/drivers/raiden.c
r949	r950
490	490
491	491	for (i = 0; i < 0x20000; i++)
492	492	{
493		static const UINT16 xor_table[] = { 0x200e,0x0006,0x000a,0x0002,0x240e,0x000e,0x04c2,0x00c2,0x008c,0x0004,0x0088,0x0000,0x048c,0x000c,0x04c0,0xc000 };
	493	static const UINT16 xor_table[] = { 0x200e,0x0006,0x000a,0x0002,0x240e,0x000e,0x04c2,0x00c2,0x008c,0x0004,0x0088,0x0000,0x048c,0x000c,0x04c0,0x00c0 };
494	494	UINT16 data = RAM[0xc0000/2 + i];
495	495	data ^= xor_table[i & 0x0f];
496	496	data = BITSWAP16(data, 15,14,10,12,11,13,9,8,3,2,5,4,7,1,6,0);

src/mame/drivers/xain.c
r949	r950
423	423
424	424	static const gfx_layout charlayout =
425	425	{
426		8,8, /* 88 chars /
427		1024, /* 1024 characters */
428		4, /* 4 bits per pixel */
429		{ 0, 2, 4, 6 }, /* plane offset */
430		{ 1, 0, 88+1, 88+0, 168+1, 168+0, 248+1, 248+0 },
431		{ 08, 18, 28, 38, 48, 58, 68, 78 },
432		328 / every char takes 32 consecutive bytes */
	426	8,8,
	427	RGN_FRAC(1,1),
	428	4,
	429	{ 0, 2, 4, 6 },
	430	{ STEP2(08+1,-1), STEP2(88+1,-1), STEP2(168+1,-1), STEP2(248+1,-1) },
	431	{ STEP8(0,8) },
	432	32*8
433	433	};
434	434
435	435	static const gfx_layout tilelayout =
436	436	{
437		16,16, /* 88 chars /
438		4512, / 512 characters */
439		4, /* 4 bits per pixel */
440		{ 0x800048+0, 0x800048+4, 0, 4 }, /* plane offset */
441		{ 3, 2, 1, 0, 168+3, 168+2, 168+1, 168+0,
442		328+3,328+2 ,328+1 ,328+0 ,488+3 ,488+2 ,488+1 ,488+0 },
443		{ 08, 18, 28, 38, 48, 58, 68, 78,
444		88, 98, 108, 118, 128, 138, 148, 158 },
445		648 / every char takes 64 consecutive bytes */
	437	16,16,
	438	RGN_FRAC(1,2),
	439	4,
	440	{ RGN_FRAC(1,2)+0, RGN_FRAC(1,2)+4, 0, 4 },
	441	{ STEP4(08+3,-1), STEP4(168+3,-1), STEP4(328+3,-1), STEP4(488+3,-1) },
	442	{ STEP16(0,8) },
	443	64*8
446	444	};
447	445
448	446	static const gfx_decode gfxdecodeinfo[] =
r949	r950
468	466	};
469	467
470	468
	469	static MACHINE_START( xsleena )
	470	{
	471	/* initialize the bank pointers */
	472	xainCPUA_bankswitch_w(0,0);
	473	xainCPUB_bankswitch_w(0,0);
	474	}
471	475
	476
472	477	static MACHINE_DRIVER_START( xsleena )
473	478
474	479	/* basic machine hardware */
r949	r950
486	491	// MDRV_CPU_ADD(M68705, 3000000/M68705_CLOCK_DIVIDER) /* Confirmed 3MHz */
487	492	// MDRV_CPU_PROGRAM_MAP(mcu_readmem,mcu_writemem)
488	493
	494	MDRV_MACHINE_START(xsleena)
	495
489	496	MDRV_SCREEN_REFRESH_RATE(57)
490	497	MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
491	498	MDRV_INTERLEAVE(100)

src/mame/drivers/istellar.c
r949	r950
406	406
407	407	/* YEAR NAME PARENT MACHINE INPUT INIT MONITOR COMPANY FULLNAME FLAGS) */
408	408	GAME( 1983, istellar, 0, istellar, istellar, istellar, ROT0, "Funai/Gakken", "Interstellar Laser Fantasy", GAME_NOT_WORKING\|GAME_NO_SOUND)
409		/*
410		Funai / Gakken Interstellar Laser Fantasy laserdisc hardware
411		Driver by Andrew Gardner with help from Daphne Source
412
413		Notes:
414		Holding down the TEST switch (T) while hitting reset will bring up the Self Test.
415		Hit T twice more for color and monitor calibration.
416		This is somewhat strange hardware : More z80's than necessary
417		3 bpp sprites
418		6-pin dip switches with odd handling
419		inverted DIP logic?
420		CPU2 maps RAM over where its ROM lives
421		The DIP switch settings seem to be inverted (or the test mode shows 1 for open and 0 for closed). This is fine, but
422		the DIPLOC stuff displays the switches off when they should be on and vice-versa. Maybe a fix the DIPlOCc code is needed?
423
424		Todo:
425		How does one best make one DIP switch bit from address 0x02 tie to two bits from address 0x03?
426		Get real ROM labels! The current labels are unfortunately a bit odd.
427		Add sprite drawing.
428		Convert to tilemaps.
429		Make it work - this one should be close right now :/.
430		*/
431
432		#include "driver.h"
433		#include "render.h"
434		#include "machine/laserdsc.h"
435
436		/* There is only 1 crystal on the stack of 3 boards - speed is unknown, the following is Daphne's guess */
437		#define GUESSED_CLOCK (3072000)
438
439
440		/* Misc variables */
441		static laserdisc_info *discinfo;
442
443		static UINT8 *tile_ram;
444		static UINT8 *tile_control_ram;
445		static UINT8 *sprite_ram;
446
447		static UINT8 ldp_latch1;
448		static UINT8 ldp_latch2;
449
450		static UINT8 z80_2_nmi_enable;
451
452		/* VIDEO GOODS */
453		VIDEO_UPDATE( istellar )
454		{
455		int charx, chary;
456
457		/* clear */
458		fillbitmap(bitmap, 0, cliprect);
459
460		/* display disc information */
461		if (discinfo != NULL)
462		popmessage("%s", laserdisc_describe_state(discinfo));
463
464		/* DEBUG */
465		/*
466		for (charx = 0; charx < 0x400; charx ++)
467		{
468		printf ("%x ", sprite_ram[charx]) ;
469		}
470		printf("\n\n\n");
471		*/
472
473		/* Draw tiles */
474		for (charx = 0; charx < 32; charx++)
475		{
476		for (chary = 0; chary < 32; chary++)
477		{
478		int current_screen_character = (chary*32) + charx;
479
480		drawgfx(bitmap, machine->gfx[0],
481		tile_ram[current_screen_character],
482		(tile_control_ram[current_screen_character] & 0x0f),
483		0, 0, charx8, chary8, cliprect, TRANSPARENCY_PEN, 0);
484		}
485		}
486
487
488		/* Draw sprites */
489
490		return 0;
491		}
492
493
494
495		/* MEMORY HANDLERS */
496		/* Z80 0 R/W */
497		READ8_HANDLER(z80_0_latch1_read)
498		{
499		/logerror("CPU0 : reading LDP status latch (%x)\n", ldp_latch1);/
500		return ldp_latch1;
501		}
502
503		WRITE8_HANDLER(z80_0_latch2_write)
504		{
505		/logerror("CPU0 : writing cpu_latch2 (%x). Potentially followed by an IRQ.\n", data);/
506		ldp_latch2 = data;
507
508		/* A CPU2 NMI */
509		if (z80_2_nmi_enable)
510		{
511		logerror("Executing an NMI on CPU2\n");
512		cpunum_set_input_line(2, INPUT_LINE_NMI, PULSE_LINE); /* Maybe this is a ASSERT_LINE, CLEAR_LINE combo? */
513		z80_2_nmi_enable = 0;
514		}
515		}
516
517
518		/* Z80 1 R/W */
519
520
521		/* Z80 2 R/W */
522		READ8_HANDLER(z80_2_ldp_read)
523		{
524		UINT8 readResult = laserdisc_data_r(discinfo);
525		logerror("CPU2 : reading LDP : %x\n", readResult);
526		return readResult;
527		}
528
529		READ8_HANDLER(z80_2_latch2_read)
530		{
531		logerror("CPU2 : reading latch2 (%x)\n", ldp_latch2);
532		return ldp_latch2;
533		}
534
535		READ8_HANDLER(z80_2_nmienable)
536		{
537		logerror("CPU2 : ENABLING NMI\n");
538		z80_2_nmi_enable = 1;
539		return 0x00;
540		}
541
542		READ8_HANDLER(z80_2_unknown_read)
543		{
544		logerror("CPU2 : c000!\n");
545		return 0x00;
546		}
547
548		WRITE8_HANDLER(z80_2_latch1_write)
549		{
550		logerror("CPU2 : writing latch1 (%x)\n", data);
551		ldp_latch1 = data;
552		}
553
554		WRITE8_HANDLER(z80_2_ldp_write)
555		{
556		logerror("CPU2 : writing LDP : 0x%x\n", data);
557		laserdisc_data_w(discinfo,data);
558		}
559
560
561
562		/* PROGRAM MAPS */
563		static ADDRESS_MAP_START( z80_0_mem, ADDRESS_SPACE_PROGRAM, 8 )
564		AM_RANGE(0x0000,0x9fff) AM_ROM
565		AM_RANGE(0xa000,0xa7ff) AM_RAM
566		AM_RANGE(0xa800,0xabff) AM_RAM AM_BASE(&tile_ram)
567		AM_RANGE(0xac00,0xafff) AM_RAM AM_BASE(&tile_control_ram)
568		AM_RANGE(0xb000,0xb3ff) AM_RAM AM_BASE(&sprite_ram)
569		ADDRESS_MAP_END
570
571		static ADDRESS_MAP_START( z80_1_mem, ADDRESS_SPACE_PROGRAM, 8 )
572		AM_RANGE(0x0000,0x1fff) AM_ROM
573		AM_RANGE(0x4000,0x47ff) AM_RAM
574		ADDRESS_MAP_END
575
576		static ADDRESS_MAP_START( z80_2_mem, ADDRESS_SPACE_PROGRAM, 8 )
577		AM_RANGE(0x0000,0x17ff) AM_ROM
578		AM_RANGE(0x1800,0x1fff) AM_RAM
579		AM_RANGE(0xc000,0xc000) AM_READ(z80_2_unknown_read) /* Seems to be thrown away every time it's read - maybe interrupt related? */
580		ADDRESS_MAP_END
581
582
583		/* IO MAPS */
584		static ADDRESS_MAP_START( z80_0_io, ADDRESS_SPACE_IO, 8 )
585		ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
586		AM_RANGE(0x00,0x00) AM_READ_PORT("IN0")
587		AM_RANGE(0x02,0x02) AM_READ_PORT("DSW1")
588		AM_RANGE(0x03,0x03) AM_READ_PORT("DSW2")
589		/AM_RANGE(0x04,0x04) AM_WRITE(volatile_palette_write)/
590		AM_RANGE(0x05,0x05) AM_READWRITE(z80_0_latch1_read,z80_0_latch2_write)
591		ADDRESS_MAP_END
592
593		static ADDRESS_MAP_START( z80_1_io, ADDRESS_SPACE_IO, 8 )
594		ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
595		AM_RANGE(0x00,0x00) AM_NOP /AM_READWRITE(z80_1_slatch_read,z80_1_slatch_write)/
596		AM_RANGE(0x01,0x01) AM_NOP /AM_READWRITE(z80_1_nmienable,z80_1_soundwrite_front)/
597		AM_RANGE(0x02,0x02) AM_NOP /AM_WRITE(z80_1_soundwrite_rear)/
598		ADDRESS_MAP_END
599
600		static ADDRESS_MAP_START( z80_2_io, ADDRESS_SPACE_IO, 8 )
601		ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
602		AM_RANGE(0x00,0x00) AM_READWRITE(z80_2_ldp_read,z80_2_ldp_write)
603		AM_RANGE(0x01,0x01) AM_READWRITE(z80_2_latch2_read,z80_2_latch1_write)
604		AM_RANGE(0x02,0x02) AM_READ(z80_2_nmienable)
605		/* AM_RANGE(0x03,0x03) AM_WRITE(z80_2_ldtrans_write)*/
606		ADDRESS_MAP_END
607
608
609		/* PORTS */
610		INPUT_PORTS_START( istellar )
611		/* TEST MODE might display a 0 for a short and a 1 for an open circuit? If so, everything below is inverted. */
612		PORT_START_TAG("DSW1")
613		PORT_DIPNAME( 0x01, 0x01, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:1")
614		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
615		PORT_DIPSETTING( 0x01, DEF_STR( On ) )
616		PORT_DIPNAME( 0x0e, 0x00, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:2,3,4")
617		PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
618		PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
619		PORT_DIPSETTING( 0x06, DEF_STR( 2C_3C ) )
620		PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
621		PORT_DIPSETTING( 0x04, DEF_STR( 1C_3C ) )
622		PORT_DIPSETTING( 0x0c, DEF_STR( 1C_6C ) )
623		PORT_DIPNAME( 0x30, 0x00, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW1:5,6")
624		PORT_DIPSETTING( 0x00, "3" )
625		PORT_DIPSETTING( 0x10, "4" )
626		PORT_DIPSETTING( 0x20, "5" )
627		PORT_DIPSETTING( 0x30, "10" )
628		PORT_DIPNAME( 0x40, 0x00, "Barrier UFO" ) PORT_DIPLOCATION("SW2:1")
629		PORT_DIPSETTING( 0x40, DEF_STR( No ) )
630		PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
631		PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unused ) ) PORT_DIPLOCATION("SW2:2")
632		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
633		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
634
635		/* NOTE - bit 0x80 in the above read is combined with bits 0x03 in the below read to form the Coin_B
636		settings. I'm unaware of what mechanism MAME will use to make this work right? */
637
638		/* "In case of inter-stellar upright type the coin switch 2 is not used." Quoth the manual. */
639		PORT_START_TAG("DSW2")
640		PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unused ) ) PORT_DIPLOCATION("SW2:3")
641		PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
642		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
643		PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unused ) ) PORT_DIPLOCATION("SW2:4")
644		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
645		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
646		PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unused ) ) PORT_DIPLOCATION("SW2:5") /* Maybe SERVICE? */
647		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
648		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
649		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "TEST" ) PORT_CODE( KEYCODE_T )
650		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 )
651		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
652		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_START2 )
653		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_START1 )
654
655		PORT_START_TAG("IN0")
656		PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_4WAY
657		PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_4WAY
658		PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_4WAY
659		PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_4WAY
660		PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 )
661		PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 )
662		/* SERVICE might be hanging out back here */
663		INPUT_PORTS_END
664
665		PALETTE_INIT( istellar )
666		{
667		int i;
668
669		/* Oddly enough, the top 4 bits of each byte is 0 */
670		for (i = 0; i < machine->drv->total_colors; i++)
671		{
672		int r,g,b;
673		int bit0,bit1,bit2,bit3;
674
675		/* Daphne says "TODO: get the real interstellar resistor values" */
676
677		/* red component */
678		bit0 = (color_prom[i+0x000] >> 0) & 0x01;
679		bit1 = (color_prom[i+0x000] >> 1) & 0x01;
680		bit2 = (color_prom[i+0x000] >> 2) & 0x01;
681		bit3 = (color_prom[i+0x000] >> 3) & 0x01;
682		r = (0x8f * bit3) + (0x43 * bit2) + (0x1f * bit1) + (0x0e * bit0);
683
684		/* green component */
685		bit0 = (color_prom[i+0x100] >> 0) & 0x01;
686		bit1 = (color_prom[i+0x100] >> 1) & 0x01;
687		bit2 = (color_prom[i+0x100] >> 2) & 0x01;
688		bit3 = (color_prom[i+0x100] >> 3) & 0x01;
689		g = (0x8f * bit3) + (0x43 * bit2) + (0x1f * bit1) + (0x0e * bit0);
690
691		/* blue component */
692		bit0 = (color_prom[i+0x200] >> 0) & 0x01;
693		bit1 = (color_prom[i+0x200] >> 1) & 0x01;
694		bit2 = (color_prom[i+0x200] >> 2) & 0x01;
695		bit3 = (color_prom[i+0x200] >> 3) & 0x01;
696		b = (0x8f * bit3) + (0x43 * bit2) + (0x1f * bit1) + (0x0e * bit0);
697
698		palette_set_color(machine,i,MAKE_RGB(r,g,b));
699		}
700		}
701
702		static const gfx_layout istellar_gfx_layout =
703		{
704		8,8,
705		0x2000/8,
706		3,
707		{ 0, 0x20008, 0x40008 },
708		{ 0,1,2,3,4,5,6,7 },
709		{ 08, 18, 28, 38, 48, 58, 68, 78 },
710		8*8
711		};
712
713		static const gfx_decode gfxdecodeinfo[] =
714		{
715		{ REGION_GFX1, 0, &istellar_gfx_layout, 0x0, 0x100 },
716		{ -1 }
717		};
718
719		static MACHINE_START( istellar )
720		{
721		discinfo = laserdisc_init(LASERDISC_TYPE_LDV1000, get_disk_handle(0), 0);
722		return;
723		}
724
725		static INTERRUPT_GEN( vblank_callback_istellar )
726		{
727		/* Interrupt presumably comes from VBlank */
728		cpunum_set_input_line(0, 0, ASSERT_LINE);
729
730		/* Interrupt presumably comes from the LDP's status strobe */
731		cpunum_set_input_line(2, 0, ASSERT_LINE);
732
733		/* Only do the LDP's sync once */
734		if (cpu_getactivecpu() == 0)
735		laserdisc_vsync(discinfo);
736		}
737
738
739		/* DRIVER */
740		static MACHINE_DRIVER_START( istellar )
741		/* main cpu */
742		MDRV_CPU_ADD(Z80, GUESSED_CLOCK)
743		MDRV_CPU_PROGRAM_MAP(z80_0_mem,0)
744		MDRV_CPU_IO_MAP(z80_0_io,0)
745		MDRV_CPU_VBLANK_INT(vblank_callback_istellar, 1)
746
747		/* sound cpu */
748		MDRV_CPU_ADD(Z80, GUESSED_CLOCK)
749		MDRV_CPU_PROGRAM_MAP(z80_1_mem,0)
750		MDRV_CPU_IO_MAP(z80_1_io,0)
751
752		/* ldp comm cpu */
753		MDRV_CPU_ADD(Z80, GUESSED_CLOCK)
754		MDRV_CPU_PROGRAM_MAP(z80_2_mem,0)
755		MDRV_CPU_IO_MAP(z80_2_io,0)
756
757		MDRV_MACHINE_START(istellar)
758
759		/* video */
760		MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
761
762		MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
763		MDRV_SCREEN_REFRESH_RATE(60)
764		MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
765		MDRV_SCREEN_SIZE(328, 328)
766		MDRV_SCREEN_VISIBLE_AREA(08, 328-1, 08, 328-1)
767
768		MDRV_PALETTE_LENGTH(256)
769		MDRV_PALETTE_INIT(istellar)
770
771		MDRV_GFXDECODE(gfxdecodeinfo)
772		MDRV_VIDEO_UPDATE(istellar)
773
774		/* sound */
775		MACHINE_DRIVER_END
776
777
778		/* There is a photo of the PCB with blurry IC locations and labels. Comments reflect what I can (barely) see. */
779		ROM_START( istellar )
780		/* Main program CPU */
781		ROM_REGION( 0xa000, REGION_CPU1, 0 )
782		ROM_LOAD( "rom2.top", 0x0000, 0x2000, CRC(5d643381) SHA1(75ca52c28a52f534eda00c18b0db97e9923ff670) ) /* At IC location C63 (top board) - label ? */
783		ROM_LOAD( "rom3.top", 0x2000, 0x2000, CRC(ce5a2b09) SHA1(2de6a6e993c3411577ac0c834db8aaf16fb007ed) ) /* At IC location C64 (top board) - label ? */
784		ROM_LOAD( "rom4.top", 0x4000, 0x2000, CRC(7c2cb1f1) SHA1(ffd92510c03c2d35a59d233883c2b9f57394a51c) ) /* At IC location C65 (top board) - label ? */
785		ROM_LOAD( "rom5.top", 0x6000, 0x2000, CRC(354377f6) SHA1(bcf95b7ee1b47854e10baf24b0d8af3d56738b99) ) /* At IC location C66 (top board) - label ? */
786		ROM_LOAD( "rom6.top", 0x8000, 0x2000, CRC(0319bf40) SHA1(f324626e457c3eb7d6b74bc6afbfcc3aab2b3c72) ) /* At IC location C67 (top board) - label ? */
787
788		/* Sound CPU */
789		ROM_REGION( 0x2000, REGION_CPU2, 0 )
790		ROM_LOAD( "rom1.top", 0x0000, 0x2000, CRC(4f34fb1d) SHA1(56ca19344c84c5989d0be797e2759f84760310be) ) /* At IC location C62 (top board) - label ? */
791
792		/* LDP Communications CPU */
793		ROM_REGION( 0x2000, REGION_CPU3, 0 )
794		ROM_LOAD( "rom11.bot", 0x0000, 0x2000, CRC(165cbc57) SHA1(39463888f22ec3125f0686066d923a9aae79a8f7) ) /* At IC location C12 (bottom board) - label IS11 */
795
796		/* Tiles */
797		ROM_REGION( 0x6000, REGION_GFX1, ROMREGION_DISPOSE )
798		ROM_LOAD( "rom9.bot", 0x0000, 0x2000, CRC(9d79acb6) SHA1(72af972695face0016afce8a26c629d963e86d48) ) /* At IC location C47? (bottom board) - label ? */
799		ROM_LOAD( "rom8.bot", 0x2000, 0x2000, CRC(e9c9e490) SHA1(79aa35552b984018bc723adece5c40a0833a313c) ) /* At IC location C48? (bottom board) - label ? */
800		ROM_LOAD( "rom7.bot", 0x4000, 0x2000, CRC(1447ce3a) SHA1(8545cec108df6adab303802b1407c89b2dceba21) ) /* At IC location C49? (bottom board) - label ? */
801
802		/* Color PROMs */
803		ROM_REGION( 0x300, REGION_PROMS, 0 )
804		ROM_LOAD( "red6b.bot", 0x000, 0x100, CRC(5c52f844) SHA1(a8a3d91f3247ad13c805d8d8288b07f3cdaf1189) ) /* At IC location C63? (bottom board) - label ? */
805		ROM_LOAD( "green6c.bot", 0x100, 0x100, CRC(7d8c845c) SHA1(04ae2ca0cc6679e21346ce34e9e01aa5bf4e2067) ) /* At IC location C62? (bottom board) - label ? */
806		ROM_LOAD( "blue6d.bot", 0x200, 0x100, CRC(5ebb81f9) SHA1(285d60f2894c524ca80fc68ad7c2dfd9093a67ea) ) /* At IC location C61? (bottom board) - label ? */
807		ROM_END
808
809
810		static DRIVER_INIT( istellar )
811		{
812		z80_2_nmi_enable = 0;
813		}
814
815		/* YEAR NAME PARENT MACHINE INPUT INIT MONITOR COMPANY FULLNAME FLAGS) */
816		GAME( 1983, istellar, 0, istellar, istellar, istellar, ROT0, "Funai/Gakken", "Interstellar Laser Fantasy", GAME_NOT_WORKING\|GAME_NO_SOUND)

src/mame/drivers/8080bw.c
r949	r950
3167	3167	ROM_LOAD( "rom5", 0x1400, 0x0400, CRC(cc52a4bb) SHA1(857b75a8b01fc707db940197d6bf3b0466c4a7b5) )
3168	3168	ROM_END
3169	3169
	3170	ROM_START( astropal )
	3171	ROM_REGION( 0x10000, REGION_CPU1, 0 )
	3172	ROM_LOAD( "2708.0a", 0x0000, 0x0400, CRC(e6883322) SHA1(05b0ab0dc6297209dcfdd173e762bfae3a720e8d) )
	3173	ROM_LOAD( "2708.1a", 0x0400, 0x0400, CRC(4401df1d) SHA1(16f3b957278aa67cb37bcd5defb6e4dd8ccf7d1f) )
	3174	ROM_LOAD( "2708.2a", 0x0800, 0x0400, CRC(5bac1ee4) SHA1(8c3e5f882f4798f8ed0523b60a216c989324a7c2) )
	3175	ROM_LOAD( "2708.3a", 0x0c00, 0x0400, CRC(a870afad) SHA1(1a256db2bc6baa238ee1df4eff2fdce0888f812c) )
	3176	ROM_LOAD( "2708.4a", 0x1000, 0x0400, CRC(8bd2d985) SHA1(3ff9110c1bad7d4562664da772d14750d738c2d6) )
	3177	ROM_LOAD( "2708.5a", 0x1400, 0x0400, CRC(5e97a86b) SHA1(f3500d48ecb3969b8aaea9c4e812fbf6cf4170af) )
	3178	ROM_LOAD( "2708.6a", 0x1800, 0x0400, CRC(22c354d0) SHA1(c465ca5787ad8de3be97deac1214d3abd0b27e6b) )
	3179	ROM_LOAD( "2708.7a", 0x1c00, 0x0400, CRC(aeca51c1) SHA1(767bca1e6bca41327b9ff6c3570edcabe46dec21) )
	3180	ROM_END
3170	3181
3171
3172	3182	/* board # rom parent machine inp */
3173	3183
3174	3184	/* Taito games */
r949	r950
3209	3219	GAMEL(19??, alieninv, invaders, invaders, searthin, 0, ROT270, "bootleg", "Alien Invasion Part II", 0, layout_invaders )
3210	3220	GAMEL(1978, spceking, invaders, invaders, sicv, 0, ROT270, "Leijac Corporation (Konami)","Space King", 0, layout_invaders )
3211	3221	GAMEL(1978, spcewars, invaders, spcewars, spcewars, 0, ROT270, "Sanritsu", "Space War (Sanritsu)", 0, layout_invaders )
	3222	GAME (19??, astropal, 0, invaders, spcewars, 0, ROT0, "Sidam?", "Astropal", GAME_NOT_WORKING )
3212	3223	GAMEL(1978, spacewr3, invaders, spcewars, sicv, 0, ROT270, "bootleg", "Space War Part 3", 0, layout_invaders )
3213	3224	GAMEL(1978, invaderl, invaders, invaders, sicv, 0, ROT270, "Logitec", "Space Invaders (Logitec)", 0, layout_invaders )
3214	3225	GAMEL(1978, invader4, invaders, invaders, sicv, 0, ROT270, "bootleg", "Space Invaders Part Four", 0, layout_invaders )

src/mame/drivers/pacland.c
r949	r950
396	396	{
397	397	{ REGION_GFX1, 0, &charlayout, 0, 256 },
398	398	{ REGION_GFX2, 0, &charlayout, 256*4, 256 },
399		{ REGION_GFX3, 0, &spritelayout, 2564+2564, 2*64 },
	399	{ REGION_GFX3, 0, &spritelayout, 2564+2564, 64 },
400	400	{ -1 }
401	401	};
402	402
r949	r950
433	433	MDRV_SCREEN_SIZE(648, 328)
434	434	MDRV_SCREEN_VISIBLE_AREA(38, 398-1, 28, 308-1)
435	435	MDRV_GFXDECODE(gfxdecodeinfo)
436		MDRV_PALETTE_LENGTH(2564+2564+26416)
	436	MDRV_PALETTE_LENGTH(2564+2564+64*16)
437	437
438	438	MDRV_PALETTE_INIT(pacland)
439	439	MDRV_VIDEO_START(pacland)
r949	r950
592	592
593	593
594	594
595		GAME( 1984, pacland, 0, pacland, pacland, 0, ROT0, "Namco", "Pac-Land (World)", 0 )
596		GAME( 1984, pacland2, pacland, pacland, pacland, 0, ROT0, "Namco", "Pac-Land (Japan newer)", 0 )
597		GAME( 1984, pacland3, pacland, pacland, pacland, 0, ROT0, "Namco", "Pac-Land (Japan older)", 0 )
598		GAME( 1984, paclandm, pacland, pacland, pacland, 0, ROT0, "[Namco] (Bally Midway license)", "Pac-Land (Midway)", 0 )
	595	GAME( 1984, pacland, 0, pacland, pacland, 0, ROT0, "Namco", "Pac-Land (World)", GAME_SUPPORTS_SAVE )
	596	GAME( 1984, pacland2, pacland, pacland, pacland, 0, ROT0, "Namco", "Pac-Land (Japan newer)", GAME_SUPPORTS_SAVE )
	597	GAME( 1984, pacland3, pacland, pacland, pacland, 0, ROT0, "Namco", "Pac-Land (Japan older)", GAME_SUPPORTS_SAVE )
	598	GAME( 1984, paclandm, pacland, pacland, pacland, 0, ROT0, "[Namco] (Bally Midway license)", "Pac-Land (Midway)", GAME_SUPPORTS_SAVE )

src/mame/drivers/exidy440.c
r949	r950
15	15	* Hit 'n Miss
16	16	* Who Dunit
17	17	* Showdown
	18	* Yukon
18	19
19	20	****************************************************************************
20	21
r949	r950
45	46	R x------- (VBLANK FIRQ latched, active low)
46	47	R -x------ (collision/beam detect FIRQ latched, active low)
47	48	R --xxxx-- (4 position DIP switch, active low)
48		R ------x- (trigger, active low)
49		R -------x (mirror of VBLANK FIRQ latch, Whodunit only)
	49	R ------x- (trigger, active low)
	50	R -------x (mirror of VBLANK FIRQ latch, Whodunit only)
50	51	2B03 W xxxxxxxx Control port
51	52	W xxxx---- (ROM bank select, 0-15)
52	53	W ----x--- (collision/beam detect FIRQ enable)
r949	r950
75	76	R ------x- (coin 2, active low)
76	77	R -------x (coin 1, active low)
77	78	2EC0-2EDF R xxxxxxxx Copy protection check (Clay Pigeon)
78		2EC0-2EDF R/W xxxxxxxx Copy protection and I/O space (Top Secret)
	79	2EC0-2EDF R/W xxxxxxxx Copy protection and I/O space (Top Secret)
79	80	3000-3FFF R/W xxxxxxxx RAM
80	81	4000-7FFF R xxxxxxxx Banked ROM
81	82	6000-7FFF R/W xxxxxxxx EEROM (when bank 15 is selected only)
r949	r950
218	219
219	220
220	221	/* globals */
221		UINT8 exidy440_bank;
222	222	UINT8 exidy440_topsecret;
223	223
224	224
225	225	/* local variables */
	226	static UINT8 exidy440_bank;
226	227	static UINT8 port_0_xor;
227	228	static UINT8 port_2_xor;
228	229	static UINT8 port_3_xor;
229	230	static UINT8 mirror_vblank_bit;
230	231	static UINT8 mirror_trigger_bit;
231	232	static UINT8 copy_protection_read;
232		static UINT8 coin_state;
233	233	static UINT8 last_coins;
234		static UINT8 showdown_bank_triggered;
235	234
	235	static const UINT8 *showdown_bank_data[2];
	236	static INT8 showdown_bank_select;
	237	static UINT8 showdown_bank_offset;
236	238
	239	static READ8_HANDLER( showdown_bank0_r );
237	240
	241
	242
238	243	/*************************************
239	244	*
240	245	* EEROM save/load
r949	r950
267	272	int coins;
268	273
269	274	/* if we got a coin, set the IRQ on the main CPU */
270		coins = input_port~~_3_r~~(0) & 3;
	275	coins = readinputport(3) & 3;
271	276	if (((coins ^ last_coins) & 0x01) && (coins & 0x01) == 0)
272		{
273		coin_state &= ~0x01;
274	277	cpunum_set_input_line(0, 0, ASSERT_LINE);
275		}
276	278	if (((coins ^ last_coins) & 0x02) && (coins & 0x02) == 0)
277		{
278		coin_state &= ~0x02;
279	279	cpunum_set_input_line(0, 0, ASSERT_LINE);
280		}
281	280	last_coins = coins;
282	281	}
283	282
r949	r950
292	291
293	292	MACHINE_RESET( exidy440 )
294	293	{
295		exidy440_bank = 0;
296		memory_set_bankptr(1, &memory_region(REGION_CPU1)[0x10000]);
297
	294	exidy440_bank = 0xff;
	295	exidy440_bank_select(0);
298	296	last_coins = input_port_3_r(0) & 3;
299		coin_state = 3;
300	297	}
301	298
302	299
r949	r950
333	330	*
334	331	*************************************/
335	332
	333	void exidy440_bank_select(UINT8 bank)
	334	{
	335	/* for the showdown case, bank 0 is a PLD */
	336	if (showdown_bank_data[0] != NULL)
	337	{
	338	if (bank == 0 && exidy440_bank != 0)
	339	memory_install_read8_handler(0, ADDRESS_SPACE_PROGRAM, 0x4000, 0x7fff, 0, 0, showdown_bank0_r);
	340	else if (bank != 0 && exidy440_bank == 0)
	341	memory_install_read8_handler(0, ADDRESS_SPACE_PROGRAM, 0x4000, 0x7fff, 0, 0, MRA8_BANK1);
	342	}
	343
	344	/* select the bank and update the bank pointer */
	345	exidy440_bank = bank;
	346	memory_set_bankptr(1, &memory_region(REGION_CPU1)[0x10000 + exidy440_bank * 0x4000]);
	347	}
	348
	349
336	350	static WRITE8_HANDLER( bankram_w )
337	351	{
338	352	/* EEROM lives in the upper 8k of bank 15 */
r949	r950
353	367	*
354	368	*************************************/
355	369
356		static READ8_HANDLER( io1_r )
	370	static READ8_HANDLER( io_r )
357	371	{
358	372	int result = 0xff;
359	373
r949	r950
364	378	break;
365	379
366	380	case 0x20: /* coin bits I/O1 */
367		result = (input_port_3_r(offset) & 0xfc) \| coin_state;
368		result ^= port_3_xor;
	381	result = readinputport(3) ^ port_3_xor;
369	382
370		/* sound command acknowledgements come on bit 3 here */
371		if (!exidy440_sound_command_ack)
372		result ^= 0x08;
373
374	383	/* I/O1 accesses clear the CIRQ flip/flop */
375	384	cpunum_set_input_line(0, 0, CLEAR_LINE);
376	385	break;
377	386
378	387	case 0x40: /* clear coin counters I/O2 */
379		result = 0xff;
380	388	break;
381	389
382	390	case 0x60: /* dip switches (8) */
r949	r950
387	395	result = input_port_2_r(offset) ^ port_2_xor;
388	396	break;
389	397
390		case 0xa0: /* coin bits I/O3 */
391		result = (input_port_3_r(offset) & 0xfc) \| coin_state;
392		result ^= port_3_xor;
393
	398	case 0xa0: /* coin bits I/O5 */
394	399	/* sound command acknowledgements come on bit 3 here */
395	400	if (exidy440_sound_command_ack)
396	401	result ^= 0x08;
r949	r950
433	438	}
434	439
435	440
436		static WRITE8_HANDLER( io1_w )
	441	static WRITE8_HANDLER( io_w )
437	442	{
438	443	logerror("W I/O1[%02X]=%02X\n", offset, data);
439	444
r949	r950
450	455	cpunum_set_input_line(0, 0, CLEAR_LINE);
451	456	break;
452	457
453		case 0x40: /* clear coin counters I/O2 */
454		coin_state = 3;
	458	case 0x40: /* coin counter I/O2 */
	459	coin_counter_w(0, data & 1);
455	460	break;
456	461
457	462	case 0x60: /* dip switches (8) */
r949	r950
479	484	*
480	485	*************************************/
481	486
482		READ8_HANDLER( showdown_~~pld_trigger~~_r )
	487	static READ8_HANDLER( showdown_bank0_r )
483	488	{
484		/* bank 0 is where the PLD lives - a read here will set the trigger */
485		if (exidy440_bank == 0)
486		showdown_bank_triggered = 1;
	489	/* showdown relies on different values from different memory locations */
	490	/* yukon relies on multiple reads from the same location returning different values */
	491	UINT8 result = 0xff;
487	492
488		/* just return the value from the current bank */
489		return memory_region(REGION_CPU1)[0x10000 + exidy440_bank * 0x4000 + 0x0055 + offset];
490		}
491
492
493		READ8_HANDLER( showdown_pld_select1_r )
494		{
495		/* bank 0 is where the PLD lives - a read here after a trigger will set bank "1" */
496		if (exidy440_bank == 0 && showdown_bank_triggered)
	493	/* fetch the special data if a bank is selected */
	494	if (showdown_bank_select >= 0)
497	495	{
498		static const UINT8 bankdata[0x18] =
499		{
500		0x15,0x40,0xc1,0x8d,0x4c,0x84,0x0e,0xce,
501		0x52,0xd0,0x99,0x48,0x80,0x09,0xc9,0x45,
502		0xc4,0x8e,0x5a,0x92,0x18,0xd8,0x51,0xc0
503		};
	496	result = showdown_bank_data[showdown_bank_select][showdown_bank_offset++];
504	497
505		/* clear the trigger and copy the expected 24 bytes to the RAM area */
506		showdown_bank_triggered = 0;
507		memcpy(&memory_region(REGION_CPU1)[0x10000], bankdata, 0x18);
	498	/* after 24 bytes, stop and revert back to the beginning */
	499	if (showdown_bank_offset == 0x18)
	500	showdown_bank_offset = 0;
508	501	}
509	502
510		/* just return the value from the current bank */
511		return memory_region(REGION_CPU1)[0x10000 + exidy440_bank * 0x4000 + 0x00ed + offset];
512		}
513
514
515		READ8_HANDLER( showdown_pld_select2_r )
516		{
517		/* bank 0 is where the PLD lives - a read here after a trigger will set bank "2" */
518		if (exidy440_bank == 0 && showdown_bank_triggered)
	503	/* look for special offsets to adjust our behavior */
	504	if (offset == 0x0055)
	505	showdown_bank_select = -1;
	506	else if (showdown_bank_select == -1)
519	507	{
520		static const UINT8 bankdata[0x18] =
521		{
522		0x11,0x51,0xc0,0x89,0x4d,0x85,0x0c,0xcc,
523		0x46,0xd2,0x98,0x59,0x91,0x08,0xc8,0x41,
524		0xc5,0x8c,0x4e,0x86,0x1a,0xda,0x50,0xd1
525		};
526
527		/* clear the trigger and copy the expected 24 bytes to the RAM area */
528		showdown_bank_triggered = 0;
529		memcpy(&memory_region(REGION_CPU1)[0x10000], bankdata, 0x18);
	508	showdown_bank_select = (offset == 0x00ed) ? 0 : (offset == 0x1243) ? 1 : 0;
	509	showdown_bank_offset = 0;
530	510	}
531	511
532		/* just return the value from the current bank */
533		return memory_region(REGION_CPU1)[0x10000 + exidy440_bank * 0x4000 + 0x1243 + offset];
	512	return result;
534	513	}
535	514
536	515
r949	r950
541	520	*
542	521	*************************************/
543	522
544		static ADDRESS_MAP_START( readmem_cpu1, ADDRESS_SPACE_PROGRAM, 8 )
545		AM_RANGE(0x0000, 0x1fff) AM_READ(MRA8_RAM)
546		AM_RANGE(0x2000, 0x209f) AM_READ(MRA8_RAM)
547		AM_RANGE(0x20a0, 0x29ff) AM_READ(MRA8_RAM)
548		AM_RANGE(0x2a00, 0x2aff) AM_READ(exidy440_videoram_r)
	523	static ADDRESS_MAP_START( cpu1_map, ADDRESS_SPACE_PROGRAM, 8 )
	524	AM_RANGE(0x0000, 0x1fff) AM_RAM AM_BASE(&exidy440_imageram)
	525	AM_RANGE(0x2000, 0x209f) AM_READWRITE(MRA8_RAM, exidy440_spriteram_w) AM_BASE(&spriteram)
	526	AM_RANGE(0x20a0, 0x29ff) AM_RAM
	527	AM_RANGE(0x2a00, 0x2aff) AM_READWRITE(exidy440_videoram_r, exidy440_videoram_w)
549	528	AM_RANGE(0x2b00, 0x2b00) AM_READ(exidy440_vertical_pos_r)
550		AM_RANGE(0x2b01, 0x2b01) AM_READ(exidy440_horizontal_pos_r)
551		AM_RANGE(0x2b02, 0x2b02) AM_READ(MRA8_RAM)
552		AM_RANGE(0x2b03, 0x2b03) AM_READ(input_r)
553		AM_RANGE(0x2c00, 0x2dff) AM_READ(exidy440_paletteram_r)
554		AM_RANGE(0x2e00, 0x2eff) AM_READ(io1_r)
555		AM_RANGE(0x3000, 0x3fff) AM_READ(MRA8_RAM)
556		AM_RANGE(0x4000, 0x7fff) AM_READ(MRA8_BANK1)
557		AM_RANGE(0x8000, 0xffff) AM_READ(MRA8_ROM)
	529	AM_RANGE(0x2b01, 0x2b01) AM_READWRITE(exidy440_horizontal_pos_r, exidy440_interrupt_clear_w)
	530	AM_RANGE(0x2b02, 0x2b02) AM_RAM AM_BASE(&exidy440_scanline)
	531	AM_RANGE(0x2b03, 0x2b03) AM_READWRITE(input_r, exidy440_control_w)
	532	AM_RANGE(0x2c00, 0x2dff) AM_READWRITE(exidy440_paletteram_r, exidy440_paletteram_w)
	533	AM_RANGE(0x2e00, 0x2eff) AM_READWRITE(io_r, io_w)
	534	AM_RANGE(0x3000, 0x3fff) AM_RAM
	535	AM_RANGE(0x4000, 0x7fff) AM_READWRITE(MRA8_BANK1, bankram_w)
	536	AM_RANGE(0x8000, 0xffff) AM_ROM
558	537	ADDRESS_MAP_END
559	538
560	539
561		static ADDRESS_MAP_START( writemem_cpu1, ADDRESS_SPACE_PROGRAM, 8 )
562		AM_RANGE(0x0000, 0x1fff) AM_WRITE(MWA8_RAM) AM_BASE(&exidy440_imageram)
563		AM_RANGE(0x2000, 0x209f) AM_WRITE(exidy440_spriteram_w) AM_BASE(&spriteram)
564		AM_RANGE(0x20a0, 0x29ff) AM_WRITE(MWA8_RAM)
565		AM_RANGE(0x2a00, 0x2aff) AM_WRITE(exidy440_videoram_w)
566		AM_RANGE(0x2b01, 0x2b01) AM_WRITE(exidy440_interrupt_clear_w)
567		AM_RANGE(0x2b02, 0x2b02) AM_WRITE(MWA8_RAM) AM_BASE(&exidy440_scanline)
568		AM_RANGE(0x2b03, 0x2b03) AM_WRITE(exidy440_control_w)
569		AM_RANGE(0x2c00, 0x2dff) AM_WRITE(exidy440_paletteram_w)
570		AM_RANGE(0x2e00, 0x2eff) AM_WRITE(io1_w)
571		AM_RANGE(0x3000, 0x3fff) AM_WRITE(MWA8_RAM)
572		AM_RANGE(0x4000, 0x7fff) AM_WRITE(bankram_w)
573		AM_RANGE(0x8000, 0xffff) AM_WRITE(MWA8_ROM)
574		ADDRESS_MAP_END
575	540
576
577
578	541	/*************************************
579	542	*
580	543	* Sound CPU memory handlers
581	544	*
582	545	*************************************/
583	546
584		static ADDRESS_MAP_START( readmem_cpu2, ADDRESS_SPACE_PROGRAM, 8 )
585		AM_RANGE(0x8000, 0x8016) AM_READ(exidy440_m6844_r)
586		AM_RANGE(0x8400, 0x8407) AM_READ(MRA8_RAM)
	547	static ADDRESS_MAP_START( cpu2_map, ADDRESS_SPACE_PROGRAM, 8 )
	548	AM_RANGE(0x8000, 0x8016) AM_READWRITE(exidy440_m6844_r, exidy440_m6844_w) AM_BASE(&exidy440_m6844_data)
	549	AM_RANGE(0x8400, 0x8407) AM_READWRITE(MRA8_RAM, exidy440_sound_volume_w) AM_BASE(&exidy440_sound_volume)
587	550	AM_RANGE(0x8800, 0x8800) AM_READ(exidy440_sound_command_r)
588		AM_RANGE(0x9800, 0x9800) AM_READ(MRA8_NOP)
589		AM_RANGE(0xa000, 0xbfff) AM_READ(MRA8_RAM)
590		AM_RANGE(0xe000, 0xffff) AM_READ(MRA8_ROM)
591		ADDRESS_MAP_END
592
593
594		static ADDRESS_MAP_START( writemem_cpu2, ADDRESS_SPACE_PROGRAM, 8 )
595		AM_RANGE(0x8000, 0x8016) AM_WRITE(exidy440_m6844_w) AM_BASE(&exidy440_m6844_data)
596		AM_RANGE(0x8400, 0x8407) AM_WRITE(exidy440_sound_volume_w) AM_BASE(&exidy440_sound_volume)
597	551	AM_RANGE(0x9400, 0x9403) AM_WRITE(MWA8_RAM) AM_BASE(&exidy440_sound_banks)
598		AM_RANGE(0x9800, 0x9800) AM_WRITE(exidy440_sound_interrupt_clear_w)
599		AM_RANGE(0xa000, 0xbfff) AM_WRITE(MWA8_RAM)
600		AM_RANGE(0xe000, 0xffff) AM_WRITE(MWA8_ROM)
	552	AM_RANGE(0x9800, 0x9800) AM_READWRITE(MRA8_NOP, exidy440_sound_interrupt_clear_w)
	553	AM_RANGE(0xa000, 0xbfff) AM_RAM
	554	AM_RANGE(0xe000, 0xffff) AM_ROM
601	555	ADDRESS_MAP_END
602	556
603	557
r949	r950
1044	998	PORT_START /* audio board dips */
1045	999	COINAGE
1046	1000	PORT_DIPNAME( 0x70, 0x70, DEF_STR( Unknown ) )
1047		PORT_DIPSETTING( 0x07, "1" )
1048		PORT_DIPSETTING( 0x06, "2" )
1049		PORT_DIPSETTING( 0x05, "3" )
1050		PORT_DIPSETTING( 0x04, "4" )
1051		PORT_DIPSETTING( 0x03, "5" )
1052		PORT_DIPSETTING( 0x02, "6" )
1053		PORT_DIPSETTING( 0x01, "7" )
	1001	PORT_DIPSETTING( 0x70, "1" )
	1002	PORT_DIPSETTING( 0x60, "2" )
	1003	PORT_DIPSETTING( 0x50, "3" )
	1004	PORT_DIPSETTING( 0x40, "4" )
	1005	PORT_DIPSETTING( 0x30, "5" )
	1006	PORT_DIPSETTING( 0x20, "6" )
	1007	PORT_DIPSETTING( 0x10, "7" )
1054	1008	PORT_DIPSETTING( 0x00, "1/Freeplay" )
1055	1009	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1056	1010	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
r949	r950
1104	1058
1105	1059	/* basic machine hardware */
1106	1060	MDRV_CPU_ADD(M6809,EXIDY440_MAIN_CPU_CLOCK)
1107		MDRV_CPU_PROGRAM_MAP(~~readmem_~~cpu1~~,writemem~~_cpu1)
	1061	MDRV_CPU_PROGRAM_MAP(cpu1_map,0)
1108	1062	MDRV_CPU_VBLANK_INT(main_interrupt,1)
1109	1063
1110	1064	MDRV_CPU_ADD(M6809,12979200/4/4)
1111		/* audio CPU */
1112		MDRV_CPU_PROGRAM_MAP(readmem_cpu2,writemem_cpu2)
	1065	MDRV_CPU_PROGRAM_MAP(cpu2_map,0)
1113	1066	MDRV_CPU_VBLANK_INT(irq0_line_assert,1)
1114	1067
1115	1068	MDRV_MACHINE_RESET(exidy440)
r949	r950
1915	1868	ROM_END
1916	1869
1917	1870
	1871	ROM_START( yukon )
	1872	ROM_REGION( 0x50000, REGION_CPU1, 0 ) /* 64k for code for the first CPU, plus lots of banked ROMs */
	1873	ROM_LOAD( "yul-20.1a", 0x08000, 0x2000, CRC(d8929303) SHA1(29a4b1b44016584ca99e4744b0f5cf49c635584a) )
	1874	ROM_LOAD( "yul-1.3a", 0x0a000, 0x2000, CRC(165fd218) SHA1(bc8b759f7753c91b694e9c38577292e040a8612f) )
	1875	ROM_LOAD( "yul-1.4a", 0x0c000, 0x2000, CRC(308232ce) SHA1(5b54660ae7080be6c8795c597100923da09e755c) )
	1876	ROM_LOAD( "yul-1.6a", 0x0e000, 0x2000, CRC(7ddd6235) SHA1(a946783627ffa3223ef40271e8326fdee13b3b4b) )
	1877	ROM_LOAD( "yul-1.4d", 0x24000, 0x2000, CRC(bcd5676e) SHA1(c4e92546058746966fb42b95c601b93ebe5251f0) )
	1878	ROM_LOAD( "yul-1.6d", 0x26000, 0x2000, CRC(283c1e25) SHA1(8272849964a7d82f8caa91189e818794eaa886f7) )
	1879	ROM_LOAD( "yul-1.7d", 0x28000, 0x2000, CRC(7d03232a) SHA1(dd7b40f355fc6727805a62da00d721077c354462) )
	1880	ROM_LOAD( "yul-1.8d", 0x2a000, 0x2000, CRC(a46a0253) SHA1(417b0c616671a68cb532637237e6b46a8e65d402) )
	1881	ROM_LOAD( "yul-1.10d", 0x2c000, 0x2000, CRC(9e2ca5b3) SHA1(5a286f55598de0e99f00584cabdba3a35491d0f2) )
	1882	ROM_LOAD( "yul-1.11d", 0x2e000, 0x2000, CRC(1d9f0981) SHA1(a58f113a87cad01ae2fb3257dd69739b4d3792c7) )
	1883	ROM_LOAD( "yul-1.1c", 0x30000, 0x2000, CRC(dc1a8ce7) SHA1(bfa511232fe9533bc5cfdbb4b87a8c1da5f33acb) )
	1884	ROM_LOAD( "yul-1.3c", 0x32000, 0x2000, CRC(ce840607) SHA1(c2b9da1976b3af8ac9fdacd878a72d89ff3db8fe) )
	1885	ROM_LOAD( "yul-1.4c", 0x34000, 0x2000, CRC(f0c736ae) SHA1(73a6bcbe0a91300502da8eaf7196587c32002d03) )
	1886	ROM_LOAD( "yul-1.6c", 0x36000, 0x2000, CRC(48779436) SHA1(413734020c07d8d8a59ec73f492d057e226042af) )
	1887	ROM_LOAD( "yul-1.7c", 0x38000, 0x2000, CRC(b653ab9e) SHA1(8de6855244e0aacb689626bda02047cd5e3a6b1a) )
	1888	ROM_LOAD( "yul-1.8c", 0x3a000, 0x2000, CRC(3e291d7e) SHA1(7d6287e138473b59f731b06775025b3552a34883) )
	1889	ROM_LOAD( "yul-1.10c", 0x3c000, 0x2000, CRC(7f677082) SHA1(61910492d638a1d254c8903bd5c2038c523a1e2b) )
	1890	ROM_LOAD( "yul-1.11c", 0x3e000, 0x2000, CRC(b7f5ea8d) SHA1(2e4831574323fe496d98ed661ce9264f897d6162) )
	1891	ROM_LOAD( "yul-1.1b", 0x40000, 0x2000, CRC(75cb768d) SHA1(bbcb2e09370937ea476829940a0a41b0f505b315) )
	1892	ROM_LOAD( "yul-1.3b", 0x42000, 0x2000, CRC(b76c4ec9) SHA1(d671dc399adc6e07c30636224d9679c1a4ddfc41) )
	1893	ROM_LOAD( "yul-1.4b", 0x44000, 0x2000, CRC(1b981516) SHA1(16c417c9c1918a00dee976f3513925f8f28e6f41) )
	1894	ROM_LOAD( "yul-1.6b", 0x46000, 0x2000, CRC(ab7b77e2) SHA1(40bc7dc10f06c4297b5e44b05ebcdcb5c1448072) )
	1895	ROM_LOAD( "yul-1.7b", 0x48000, 0x2000, CRC(30a62d8f) SHA1(8b2cefd5c7393ec238d2d7b53320c08cce43c93b) )
	1896	ROM_LOAD( "yul-1.8b", 0x4a000, 0x2000, CRC(fa85b58e) SHA1(11c18bff9f473281bcf6677ffffd499496af7b9d) )
1918	1897
	1898	ROM_REGION( 0x10000, REGION_CPU2, 0 )
	1899	ROM_LOAD( "yua-1.1h", 0x0e000, 0x2000, CRC(f0df665a) SHA1(1fac03007563f569fdf57d5b16a0501e9a4dff01) )
	1900
	1901	ROM_REGION( 0x20000, REGION_SOUND1, 0 )
	1902	ROM_LOAD( "yua-1.2k", 0x00000, 0x2000, CRC(67a86f7f) SHA1(a4f70aab90acd2502e8f3f39efdafcd71b1a22b4) )
	1903	ROM_LOAD( "yua-1.2l", 0x02000, 0x2000, CRC(0bb8874b) SHA1(8b643dbd5412a713b3e2831dd1ba2b7d1f613ac2) )
	1904	ROM_LOAD( "yua-1.2m", 0x04000, 0x2000, CRC(8b77eac8) SHA1(d70038cd6655e71c6488c555ecb1d1a424d00d49) )
	1905	ROM_LOAD( "yua-1.2n", 0x06000, 0x2000, CRC(78e6eed6) SHA1(d9218745fc497a67373b0f6fd82caeef33bb4b3e) )
	1906	ROM_LOAD( "yua-1.2p", 0x08000, 0x2000, CRC(a8fa14b7) SHA1(6687bc7c790f050da1b4f36a75e257c2b6a7d59e) )
	1907	ROM_LOAD( "yua-1.2r", 0x0a000, 0x2000, CRC(ca978863) SHA1(cb45b89df4dbaff7191bdab84ac5c0ba16d9d314) )
	1908	ROM_LOAD( "yua-1.2s", 0x0c000, 0x2000, CRC(74d51be4) SHA1(4368ed0a5d889f879e4059ebea039947c6e874cb) )
	1909	ROM_LOAD( "yua-1.2t", 0x0e000, 0x2000, CRC(e8a9543e) SHA1(32b0a57bb2b9fd251ff3ba621960a1851c4098fd) )
	1910	ROM_LOAD( "yua-1.1k", 0x10000, 0x2000, CRC(4e1f4f15) SHA1(cf075e09eaeab1e630b5b2e28c806d4c34eece48) )
	1911	ROM_LOAD( "yua-1.1l", 0x12000, 0x2000, CRC(6779a745) SHA1(de7d8e39f053eaa45238844e477732295d9af494) )
	1912	ROM_LOAD( "yua-1.1m", 0x14000, 0x2000, CRC(9cebd8ea) SHA1(ff8121c16e8fe93a59c49c20459287f6b002bbbc) )
	1913	ROM_LOAD( "yua-1.1n", 0x16000, 0x2000, CRC(689d8a3f) SHA1(aa592b9edcac8d264c9c89871283dfeebce2300e) )
	1914	ROM_LOAD( "yua-1.1p", 0x18000, 0x2000, CRC(862b350d) SHA1(12e6c92ba424df578eac5a820a68aaaffd73c577) )
	1915	ROM_LOAD( "yua-1.1r", 0x1a000, 0x2000, CRC(95b099ed) SHA1(1327852712ade3fc96bd8192045c081c4d32f4ba) )
	1916	ROM_LOAD( "yua-1.1s", 0x1c000, 0x2000, CRC(8f230881) SHA1(daa8efc355fb042b2fce89a0d2950a90e56a806f) )
	1917	ROM_LOAD( "yua-1.1t", 0x1e000, 0x2000, CRC(80926a5c) SHA1(6f9fb18ffb131f5eccade104a289c2d3032bac78) )
	1918
	1919	ROM_REGION( 0x00900, REGION_USER1, 0 )
	1920	/* vertical sync timing */
	1921	ROM_LOAD( "xbl.12h", 0x00000, 0x0100, CRC(375c8bfc) SHA1(2602dde6961cc6b63d1652e2f3e4cfae2d8a34d9) )
	1922	/* horizontal sync timing */
	1923	ROM_LOAD( "xbl.9h", 0x00100, 0x0100, CRC(2e7d5562) SHA1(7cd51fad8236b9853eff2eb84b474838ae1b44e8) )
	1924	ROM_LOAD( "xbl.2h", 0x00200, 0x0100, CRC(b078c1e4) SHA1(13834da4384ad43bc1671366fd428520cc3d1c1a) )
	1925	ROM_LOAD( "xbl.3k", 0x00300, 0x0100, CRC(016fe2f7) SHA1(909f815a61e759fdf998674ee383512ecd8fee65) )
	1926	ROM_LOAD( "xbl.4k", 0x00400, 0x0100, CRC(31a9549c) SHA1(5bfba7ef3f3f5fc59bc03feca39bb16d54a92778) )
	1927	ROM_LOAD( "xbl.5k", 0x00500, 0x0100, CRC(1379bb2a) SHA1(51e9e21aeb0db8727f58fda708ddea8fb53378d9) )
	1928	ROM_LOAD( "xbl.6k", 0x00600, 0x0100, CRC(588969f7) SHA1(316db275c4026e3a24e44f39f160e10189d310a3) )
	1929	ROM_LOAD( "xbl.7k", 0x00700, 0x0100, CRC(eda360b8) SHA1(79d84207e28c1289210cebd96abad6cfe1b4c1d0) )
	1930	ROM_LOAD( "xbl.8k", 0x00800, 0x0100, CRC(9d434cb1) SHA1(c3390bc1c02fe74ff2067f7fccfd1ad2c30b54a9) )
	1931	ROM_END
	1932
	1933
	1934	ROM_START( yukon1 )
	1935	ROM_REGION( 0x50000, REGION_CPU1, 0 ) /* 64k for code for the first CPU, plus lots of banked ROMs */
	1936	ROM_LOAD( "yul-1.1a", 0x08000, 0x2000, CRC(0286411b) SHA1(46f3335cb78458fab44e7976ab0c4ed318626ab3) )
	1937	ROM_LOAD( "yul-1.3a", 0x0a000, 0x2000, CRC(165fd218) SHA1(bc8b759f7753c91b694e9c38577292e040a8612f) )
	1938	ROM_LOAD( "yul-1.4a", 0x0c000, 0x2000, CRC(308232ce) SHA1(5b54660ae7080be6c8795c597100923da09e755c) )
	1939	ROM_LOAD( "yul-1.6a", 0x0e000, 0x2000, CRC(7ddd6235) SHA1(a946783627ffa3223ef40271e8326fdee13b3b4b) )
	1940	ROM_LOAD( "yul-1.4d", 0x24000, 0x2000, CRC(bcd5676e) SHA1(c4e92546058746966fb42b95c601b93ebe5251f0) )
	1941	ROM_LOAD( "yul-1.6d", 0x26000, 0x2000, CRC(283c1e25) SHA1(8272849964a7d82f8caa91189e818794eaa886f7) )
	1942	ROM_LOAD( "yul-1.7d", 0x28000, 0x2000, CRC(7d03232a) SHA1(dd7b40f355fc6727805a62da00d721077c354462) )
	1943	ROM_LOAD( "yul-1.8d", 0x2a000, 0x2000, CRC(a46a0253) SHA1(417b0c616671a68cb532637237e6b46a8e65d402) )
	1944	ROM_LOAD( "yul-1.10d", 0x2c000, 0x2000, CRC(9e2ca5b3) SHA1(5a286f55598de0e99f00584cabdba3a35491d0f2) )
	1945	ROM_LOAD( "yul-1.11d", 0x2e000, 0x2000, CRC(1d9f0981) SHA1(a58f113a87cad01ae2fb3257dd69739b4d3792c7) )
	1946	ROM_LOAD( "yul-1.1c", 0x30000, 0x2000, CRC(dc1a8ce7) SHA1(bfa511232fe9533bc5cfdbb4b87a8c1da5f33acb) )
	1947	ROM_LOAD( "yul-1.3c", 0x32000, 0x2000, CRC(ce840607) SHA1(c2b9da1976b3af8ac9fdacd878a72d89ff3db8fe) )
	1948	ROM_LOAD( "yul-1.4c", 0x34000, 0x2000, CRC(f0c736ae) SHA1(73a6bcbe0a91300502da8eaf7196587c32002d03) )
	1949	ROM_LOAD( "yul-1.6c", 0x36000, 0x2000, CRC(48779436) SHA1(413734020c07d8d8a59ec73f492d057e226042af) )
	1950	ROM_LOAD( "yul-1.7c", 0x38000, 0x2000, CRC(b653ab9e) SHA1(8de6855244e0aacb689626bda02047cd5e3a6b1a) )
	1951	ROM_LOAD( "yul-1.8c", 0x3a000, 0x2000, CRC(3e291d7e) SHA1(7d6287e138473b59f731b06775025b3552a34883) )
	1952	ROM_LOAD( "yul-1.10c", 0x3c000, 0x2000, CRC(7f677082) SHA1(61910492d638a1d254c8903bd5c2038c523a1e2b) )
	1953	ROM_LOAD( "yul-1.11c", 0x3e000, 0x2000, CRC(b7f5ea8d) SHA1(2e4831574323fe496d98ed661ce9264f897d6162) )
	1954	ROM_LOAD( "yul-1.1b", 0x40000, 0x2000, CRC(75cb768d) SHA1(bbcb2e09370937ea476829940a0a41b0f505b315) )
	1955	ROM_LOAD( "yul-1.3b", 0x42000, 0x2000, CRC(b76c4ec9) SHA1(d671dc399adc6e07c30636224d9679c1a4ddfc41) )
	1956	ROM_LOAD( "yul-1.4b", 0x44000, 0x2000, CRC(1b981516) SHA1(16c417c9c1918a00dee976f3513925f8f28e6f41) )
	1957	ROM_LOAD( "yul-1.6b", 0x46000, 0x2000, CRC(ab7b77e2) SHA1(40bc7dc10f06c4297b5e44b05ebcdcb5c1448072) )
	1958	ROM_LOAD( "yul-1.7b", 0x48000, 0x2000, CRC(30a62d8f) SHA1(8b2cefd5c7393ec238d2d7b53320c08cce43c93b) )
	1959	ROM_LOAD( "yul-1.8b", 0x4a000, 0x2000, CRC(fa85b58e) SHA1(11c18bff9f473281bcf6677ffffd499496af7b9d) )
	1960
	1961	ROM_REGION( 0x10000, REGION_CPU2, 0 )
	1962	ROM_LOAD( "yua-1.1h", 0x0e000, 0x2000, CRC(f0df665a) SHA1(1fac03007563f569fdf57d5b16a0501e9a4dff01) )
	1963
	1964	ROM_REGION( 0x20000, REGION_SOUND1, 0 )
	1965	ROM_LOAD( "yua-1.2k", 0x00000, 0x2000, CRC(67a86f7f) SHA1(a4f70aab90acd2502e8f3f39efdafcd71b1a22b4) )
	1966	ROM_LOAD( "yua-1.2l", 0x02000, 0x2000, CRC(0bb8874b) SHA1(8b643dbd5412a713b3e2831dd1ba2b7d1f613ac2) )
	1967	ROM_LOAD( "yua-1.2m", 0x04000, 0x2000, CRC(8b77eac8) SHA1(d70038cd6655e71c6488c555ecb1d1a424d00d49) )
	1968	ROM_LOAD( "yua-1.2n", 0x06000, 0x2000, CRC(78e6eed6) SHA1(d9218745fc497a67373b0f6fd82caeef33bb4b3e) )
	1969	ROM_LOAD( "yua-1.2p", 0x08000, 0x2000, CRC(a8fa14b7) SHA1(6687bc7c790f050da1b4f36a75e257c2b6a7d59e) )
	1970	ROM_LOAD( "yua-1.2r", 0x0a000, 0x2000, CRC(ca978863) SHA1(cb45b89df4dbaff7191bdab84ac5c0ba16d9d314) )
	1971	ROM_LOAD( "yua-1.2s", 0x0c000, 0x2000, CRC(74d51be4) SHA1(4368ed0a5d889f879e4059ebea039947c6e874cb) )
	1972	ROM_LOAD( "yua-1.2t", 0x0e000, 0x2000, CRC(e8a9543e) SHA1(32b0a57bb2b9fd251ff3ba621960a1851c4098fd) )
	1973	ROM_LOAD( "yua-1.1k", 0x10000, 0x2000, CRC(4e1f4f15) SHA1(cf075e09eaeab1e630b5b2e28c806d4c34eece48) )
	1974	ROM_LOAD( "yua-1.1l", 0x12000, 0x2000, CRC(6779a745) SHA1(de7d8e39f053eaa45238844e477732295d9af494) )
	1975	ROM_LOAD( "yua-1.1m", 0x14000, 0x2000, CRC(9cebd8ea) SHA1(ff8121c16e8fe93a59c49c20459287f6b002bbbc) )
	1976	ROM_LOAD( "yua-1.1n", 0x16000, 0x2000, CRC(689d8a3f) SHA1(aa592b9edcac8d264c9c89871283dfeebce2300e) )
	1977	ROM_LOAD( "yua-1.1p", 0x18000, 0x2000, CRC(862b350d) SHA1(12e6c92ba424df578eac5a820a68aaaffd73c577) )
	1978	ROM_LOAD( "yua-1.1r", 0x1a000, 0x2000, CRC(95b099ed) SHA1(1327852712ade3fc96bd8192045c081c4d32f4ba) )
	1979	ROM_LOAD( "yua-1.1s", 0x1c000, 0x2000, CRC(8f230881) SHA1(daa8efc355fb042b2fce89a0d2950a90e56a806f) )
	1980	ROM_LOAD( "yua-1.1t", 0x1e000, 0x2000, CRC(80926a5c) SHA1(6f9fb18ffb131f5eccade104a289c2d3032bac78) )
	1981
	1982	ROM_REGION( 0x00900, REGION_USER1, 0 )
	1983	/* vertical sync timing */
	1984	ROM_LOAD( "xbl.12h", 0x00000, 0x0100, CRC(375c8bfc) SHA1(2602dde6961cc6b63d1652e2f3e4cfae2d8a34d9) )
	1985	/* horizontal sync timing */
	1986	ROM_LOAD( "xbl.9h", 0x00100, 0x0100, CRC(2e7d5562) SHA1(7cd51fad8236b9853eff2eb84b474838ae1b44e8) )
	1987	ROM_LOAD( "xbl.2h", 0x00200, 0x0100, CRC(b078c1e4) SHA1(13834da4384ad43bc1671366fd428520cc3d1c1a) )
	1988	ROM_LOAD( "xbl.3k", 0x00300, 0x0100, CRC(016fe2f7) SHA1(909f815a61e759fdf998674ee383512ecd8fee65) )
	1989	ROM_LOAD( "xbl.4k", 0x00400, 0x0100, CRC(31a9549c) SHA1(5bfba7ef3f3f5fc59bc03feca39bb16d54a92778) )
	1990	ROM_LOAD( "xbl.5k", 0x00500, 0x0100, CRC(1379bb2a) SHA1(51e9e21aeb0db8727f58fda708ddea8fb53378d9) )
	1991	ROM_LOAD( "xbl.6k", 0x00600, 0x0100, CRC(588969f7) SHA1(316db275c4026e3a24e44f39f160e10189d310a3) )
	1992	ROM_LOAD( "xbl.7k", 0x00700, 0x0100, CRC(eda360b8) SHA1(79d84207e28c1289210cebd96abad6cfe1b4c1d0) )
	1993	ROM_LOAD( "xbl.8k", 0x00800, 0x0100, CRC(9d434cb1) SHA1(c3390bc1c02fe74ff2067f7fccfd1ad2c30b54a9) )
	1994	ROM_END
	1995
	1996
	1997
1919	1998	/*************************************
1920	1999	*
1921	2000	* Driver initialization
r949	r950
1923	2002	*************************************/
1924	2003
1925	2004	#define SET_PARAMS(top,p0,p2,p3,mv,mt,cpr) \
	2005	showdown_bank_data[0] = showdown_bank_data[1] = NULL;\
1926	2006	exidy440_topsecret = top;\
1927	2007	port_0_xor = p0;\
1928	2008	port_2_xor = p2;\
r949	r950
1940	2020	static DRIVER_INIT( topsecex ) { SET_PARAMS(1, 0xff, 0xff, 0x04, 0, 0, 0x00); }
1941	2021	static DRIVER_INIT( hitnmiss ) { SET_PARAMS(0, 0xff, 0xff, 0x04, 0, 1, 0x00); }
1942	2022	static DRIVER_INIT( whodunit ) { SET_PARAMS(0, 0xff, 0xff, 0x04, 1, 0, 0x00); }
	2023
1943	2024	static DRIVER_INIT( showdown )
1944	2025	{
	2026	static const UINT8 bankdata0[0x18] =
	2027	{
	2028	0x15,0x40,0xc1,0x8d,0x4c,0x84,0x0e,0xce,
	2029	0x52,0xd0,0x99,0x48,0x80,0x09,0xc9,0x45,
	2030	0xc4,0x8e,0x5a,0x92,0x18,0xd8,0x51,0xc0
	2031	};
	2032	static const UINT8 bankdata1[0x18] =
	2033	{
	2034	0x11,0x51,0xc0,0x89,0x4d,0x85,0x0c,0xcc,
	2035	0x46,0xd2,0x98,0x59,0x91,0x08,0xc8,0x41,
	2036	0xc5,0x8c,0x4e,0x86,0x1a,0xda,0x50,0xd1
	2037	};
1945	2038	SET_PARAMS(0, 0xff, 0xff, 0x04, 0, 0, 0x00);
1946	2039
1947	2040	/* set up the fake PLD */
1948		showdown_bank_triggered = 0;
1949		memory_install_read8_handler(0, ADDRESS_SPACE_PROGRAM, 0x4055, 0x4055, 0, 0, showdown_pld_trigger_r);
1950		memory_install_read8_handler(0, ADDRESS_SPACE_PROGRAM, 0x40ed, 0x40ed, 0, 0, showdown_pld_select1_r);
1951		memory_install_read8_handler(0, ADDRESS_SPACE_PROGRAM, 0x5243, 0x5243, 0, 0, showdown_pld_select2_r);
	2041	showdown_bank_data[0] = bankdata0;
	2042	showdown_bank_data[1] = bankdata1;
	2043	}
1952	2044
1953		/* ensure that we're triggered to bank "1" to start */
1954		exidy440_bank = 0;
1955		showdown_pld_trigger_r(0);
1956		showdown_pld_select1_r(0);
	2045	static DRIVER_INIT( yukon )
	2046	{
	2047	static const UINT8 bankdata0[0x18] =
	2048	{
	2049	0x31,0x40,0xc1,0x95,0x54,0x90,0x16,0xd6,
	2050	0x62,0xe0,0xa5,0x44,0x80,0x05,0xc5,0x51,
	2051	0xd0,0x96,0x66,0xa2,0x24,0xe4,0x61,0xc0
	2052	};
	2053	static const UINT8 bankdata1[0x18] =
	2054	{
	2055	0x21,0x61,0xc0,0x85,0x55,0x91,0x14,0xd4,
	2056	0x52,0xe2,0xa4,0x65,0xa1,0x04,0xc4,0x41,
	2057	0xd1,0x94,0x56,0x92,0x26,0xe6,0x60,0xe1
	2058	};
	2059	SET_PARAMS(0, 0xff, 0xff, 0x04, 0, 0, 0x00);
	2060
	2061	/* set up the fake PLD */
	2062	showdown_bank_data[0] = bankdata0;
	2063	showdown_bank_data[1] = bankdata1;
1957	2064	}
1958	2065
1959	2066
r949	r950
1976	2083	GAME( 1987, hitnmis2, hitnmiss, exidy440, hitnmiss, hitnmiss, ROT0, "Exidy", "Hit 'n Miss (version 2.0)", 0 )
1977	2084	GAME( 1988, whodunit, 0, exidy440, whodunit, whodunit, ROT0, "Exidy", "Who Dunit (version 8.0)", 0 )
1978	2085	GAME( 1988, showdown, 0, exidy440, showdown, showdown, ROT0, "Exidy", "Showdown (version 5.0)", 0 )
	2086	GAME( 1989, yukon, 0, exidy440, showdown, yukon, ROT0, "Exidy", "Yukon (version 2.0)", 0 )
	2087	GAME( 1989, yukon1, yukon, exidy440, showdown, yukon, ROT0, "Exidy", "Yukon (version 1.0)", 0 )

src/mame/drivers/thayers.c
r949	r950
507	507	cop_g_latch = 0xff;
508	508	}
509	509
510		/* YEAR NAME PARENT MACHINE INPUT INIT MONITOR COMPANY FULLNAME FLAGS) */
511		GAME( 1983, thayers, 0, thayers, thayers, thayers, ROT0, "RDI Video Systems", "Thayer's Quest", GAME_NOT_WORKING\|GAME_NO_SOUND)
512		/*
513		RDI Video Systems Thayer's Quest laserdisc hardware
514		Driver by Andrew Gardner from schematics with help from Daphne Source
515
516		Notes:
517		How odd. The schematics say there's a COP421L hooked up, but they also make mention of
518		a COP404L - A ROMless COP420 with 1k of RAM. I wonder which one is correct?
519
520		Todo:
521		Add SIO to the cop420 core.
522		Fix up my poor interpretation of the hard-to-read schematics.
523		Write a real SC-01 (SSI-263) emulator for MAME.
524		Convert to tilemaps.
525		*/
526
527		#include "driver.h"
528		#include "render.h"
529		#include "machine/laserdsc.h"
530		#include "cpu/cop400/cop400.h"
531
532		#define SCHEMATIC_CLOCK (4000000)
533
534		/*
535		* Z80 IRQ Status bit
536		* ------------------
537		*
538		* Bit \| Use
539		* 76543210-+----------------
540		* -------x \| Unused
541		* ------x- \| Unused
542		* -----x-- \| SSI-263 Request Data.
543		* ----x--- \| always high. (? but it's checked at 0x1bb ?)
544		* ---x---- \| /TIMER INT.
545		* --x----- \| /DATA RDY INT.
546		* -x------ \| /CART PRES.
547		* x------- \| Unused
548		*/
549		static UINT8 z80_irq_status;
550
551		#define Z80_IRQ_STATUS_SET() (z80_irq_status = 0x00)
552		#define Z80_IRQ_STATUS_CLEAR() (z80_irq_status = 0xff)
553
554		#define Z80_SSI_REQUEST() ((z80_irq_status & 0x04) >> 2)
555		#define Z80_TIMER_INT() ((z80_irq_status & 0x10) >> 4)
556		#define Z80_DATA_RDY_INT() ((z80_irq_status & 0x20) >> 5)
557		#define Z80_CART_PRES() ((z80_irq_status & 0x40) >> 6)
558
559		#define SET_Z80_SSI_REQUEST() (z80_irq_status &= ~0x04)
560		#define SET_Z80_TIMER_INT() (z80_irq_status &= ~0x10)
561		#define SET_Z80_DATA_RDY_INT() (z80_irq_status &= ~0x20)
562		#define SET_Z80_CART_PRES() (z80_irq_status &= ~0x40)
563
564		#define CLEAR_Z80_SSI_REQUEST() (z80_irq_status \|= 0x04)
565		#define CLEAR_Z80_TIMER_INT() (z80_irq_status \|= 0x10)
566		#define CLEAR_Z80_DATA_RDY_INT() (z80_irq_status \|= 0x20)
567		#define CLEAR_Z80_CART_PRES() (z80_irq_status \|= 0x40)
568
569
570		/* Misc variables */
571		static UINT8* ram_ic;
572		static laserdisc_info *discinfo;
573
574		static UINT8 m_ssi_control;
575		static UINT8 cop_g_latch;
576		static UINT8 cop_l_latch;
577
578
579
580		/* VIDEO GOODS */
581		VIDEO_UPDATE( thayers )
582		{
583		/* display disc information */
584		if (discinfo != NULL)
585		popmessage("%s", laserdisc_describe_state(discinfo));
586
587		return 0;
588		}
589
590
591
592		/* MEMORY HANDLERS */
593		/* Z80 R/W */
594		READ8_HANDLER(z80_irq_status_r)
595		{
596		return z80_irq_status;
597		}
598
599		READ8_HANDLER(ram_ic_read)
600		{
601		/* Daphne patches.
602		if (offset == 0xbe07-0x8000)
603		return 0x02;
604
605		if (offset == 0xbe17-0x8000)
606		return 0x01;
607		*/
608
609		return ram_ic[offset];
610		}
611
612		static UINT32 laserdisc_status_r(void *param)
613		{
614		if (discinfo == NULL)
615		return 0;
616
617		/* Someday handle multiple LD players */
618		return (laserdisc_line_r(discinfo, LASERDISC_LINE_STATUS) == ASSERT_LINE) ? 0 : 1;
619		}
620
621		static UINT32 laserdisc_command_r(void *param)
622		{
623		if (discinfo == NULL)
624		return 0;
625
626		/* Someday handle multiple LD players */
627		return (laserdisc_line_r(discinfo, LASERDISC_LINE_COMMAND) == ASSERT_LINE) ? 0 : 1;
628		}
629
630		WRITE8_HANDLER(ram_ic_write)
631		{
632		ram_ic[offset] = data;
633		}
634
635		WRITE8_HANDLER(data_ready_int_w)
636		{
637		CLEAR_Z80_DATA_RDY_INT();
638		/* Hackaroo? */
639		/* cop_l_latch = 0x00; */
640		}
641
642		WRITE8_HANDLER(timer_int_w)
643		{
644		CLEAR_Z80_TIMER_INT();
645		}
646
647		WRITE8_HANDLER(write_cop)
648		{
649		logerror("Writing 0x%x to COP port G\n", data);
650
651		/* Bits 5-7 write to COP421 ports G0-G2 */
652		cop_g_latch = (data >> 5) & 0x07;
653
654		/* Bit 2 goes to BANKSELT */
655		/* bankselect = (data & 0x04) >> 2; */
656
657		/* Bit 1 goes to CS128x? (illegible schems) */
658		}
659
660		WRITE8_HANDLER(data_write_cop)
661		{
662		cop_l_latch = data;
663		}
664
665		WRITE8_HANDLER(intrq_w)
666		{
667		cpunum_set_input_line(0, 0, ASSERT_LINE);
668		}
669
670		WRITE8_HANDLER(sc01_register_w)
671		{
672		/* (Thank you Daphne) */
673		switch (offset)
674		{
675		case 0x00:
676		if (m_ssi_control)
677		{
678		logerror("SC-01 control mode : 0x%x\n", data);
679
680		switch(data)
681		{
682		/* Stop requesting phonemes */
683		case 0x00:
684		CLEAR_Z80_SSI_REQUEST();
685		break;
686
687		/* Start adding phonemes */
688		case 0xc0:
689		SET_Z80_SSI_REQUEST();
690		if (!(Z80_SSI_REQUEST()))
691		logerror("SETTING IRQ LINE sc01\n");
692		cpunum_set_input_line(0, 0, ASSERT_LINE);
693		break;
694
695		default:
696		logerror("SC-01 control mode invalid code 0x%x\n", data);
697		break;
698		}
699		}
700		else
701		{
702		logerror("SC-01 receiving phonemes 0x%x\n", data & 0x3f);
703		}
704		break;
705
706		case 0x01:
707		logerror("SC-01 inflection changed to 0x%x\n", data);
708		break;
709
710		case 0x02:
711		logerror("SC-01 speech rate changed to 0x%x\n", data);
712		break;
713
714		case 0x03:
715		if (data & 0x80)
716		{
717		m_ssi_control = 1;
718		logerror("SC-01 now in control mode.\n");
719		}
720		else if (data & 0x70)
721		{
722		m_ssi_control = 0;
723		logerror("SC-01 control mode cleared.\n");
724		}
725		else
726		{
727		logerror("SC-01 amplitude manipulated 0x%x.\n", data);
728		}
729		break;
730
731		case 0x04:
732		logerror("SC-01 filter frequency changed to 0x%x.\n", data);
733		break;
734		}
735		}
736
737
738		/* COP R/W */
739		/* All 8 l pins are hooked up here */
740		READ8_HANDLER(cop_l_read)
741		{
742		logerror("COP - Reading from L @ (0x%x)\n", activecpu_get_pc());
743		return cop_l_latch;
744		}
745
746		/* Pins g0, g1, g2, and g3 are all hooked up */
747		READ8_HANDLER(cop_g_read)
748		{
749		logerror("COP - Reading from G @ (0x%x)\n", activecpu_get_pc());
750		return cop_g_latch;
751		}
752
753		WRITE8_HANDLER(cop_l_write)
754		{
755		logerror("COP - WRITING TO L 0x%x @ (0x%x)\n", data, activecpu_get_pc());
756		cop_l_latch = data;
757		}
758
759		WRITE8_HANDLER(cop_g_write)
760		{
761		logerror("COP - WRITING TO G 0x%x @ (0x%x)\n", data, activecpu_get_pc());
762
763		/* Bit 3 goes to an enable pin on the data latch? */
764		/* Bits 0-2 seem to go into the wrong side of a logic IC? */
765		}
766
767		/* Schematics say pins d0 and d1 are the only two that are hooked up */
768		WRITE8_HANDLER(cop_d_write)
769		{
770		int irq_flag = 0;
771
772		logerror("COP - WRITING TO D 0x%x @ (0x%x)\n", data, activecpu_get_pc());
773
774		/* Pin d0 - TIMER INT */
775		if (!(data & 0x01))
776		{
777		SET_Z80_TIMER_INT();
778		irq_flag = 1;
779		logerror("THE COP IS TRIPPING THE TIMER INTERRUPT\n");
780		}
781		else
782		{
783		CLEAR_Z80_TIMER_INT();
784		}
785
786		/* Pin d1 - DATA READY INT */
787		if (!(data & 0x02))
788		{
789		SET_Z80_DATA_RDY_INT();
790		irq_flag = 1;
791		logerror("THE COP IS TRIPPING THE DATA READY INTERRUPT\n");
792		}
793		else
794		{
795		CLEAR_Z80_DATA_RDY_INT();
796		}
797
798		/* Assert the Z80's interrupt line if necessary */
799		if (irq_flag)
800		{
801		cpunum_set_input_line(0, 0, ASSERT_LINE);
802		}
803		}
804
805		WRITE8_HANDLER(cop_sk_write)
806		{
807		/* I think this data falls off into a black hole - the pins aren't hooked up.
808		The COP400 XAS instruction writes to both SK and SIO, that's why the CPU writes data here at all. */
809		}
810
811		WRITE8_HANDLER(cop_sio_write)
812		{
813		/* This data is sent to the CLK pin of the keyboard handling logic. We don't need to emulate it here. */
814		}
815
816
817
818		/* PROGRAM MAPS */
819		static ADDRESS_MAP_START( mainmem, ADDRESS_SPACE_PROGRAM, 8 )
820		AM_RANGE(0x0000, 0x7fff) AM_ROM
821		AM_RANGE(0x8000, 0xbfff) AM_READWRITE(ram_ic_read,ram_ic_write) AM_BASE(&ram_ic) /* Not quite sure how big the RAM IC is. */
822		AM_RANGE(0xc000, 0xdfff) AM_ROM /* This is what Daphne says - we'll soon see. */
823		ADDRESS_MAP_END
824
825		static ADDRESS_MAP_START( copmem, ADDRESS_SPACE_PROGRAM, 8 )
826		AM_RANGE(0x000, 0x3ff) AM_ROM /* The schematics seem to claim this is a 2716 (0x800 bytes) - is the dump too small? */
827		ADDRESS_MAP_END
828
829
830		/* IO MAPS */
831		static ADDRESS_MAP_START( mainio, ADDRESS_SPACE_IO, 8 )
832		ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
833		AM_RANGE(0x00,0x04) AM_WRITE(sc01_register_w)
834		AM_RANGE(0x20,0x20) AM_WRITE(write_cop)
835		AM_RANGE(0x40,0x40) AM_READ(z80_irq_status_r)
836		/* AM_RANGE(0x80,0x80) AM_WRITE(data_write_cop) */
837		AM_RANGE(0xa0,0xa0) AM_WRITE(timer_int_w)
838		AM_RANGE(0xc0,0xc0) AM_WRITE(data_ready_int_w)
839
840		/* AM_RANGE(0xf0,0xf0) / / Laserdisc data read */
841		AM_RANGE(0xf1,0xf1) AM_READ_PORT("DSWB") /* 4 dips, 2 coins, Laserdisc 'ready' and 'enter' pins */
842		AM_RANGE(0xf2,0xf2) AM_READ_PORT("DSWA") /* 8 dips */
843		AM_RANGE(0xf3,0xf3) AM_WRITE(intrq_w) /* goes to /INTRQ */
844		/* AM_RANGE(0xf4,0xf4) / / Laserdisc data write */
845		/* AM_RANGE(0xf5,0xf5) / / Coin counter, 0xf4 write enable, DIP-controlled (SWB-6) LDV1000 'enter' line, and LDV1000 INT/!EXT line */
846		/* AM_RANGE(0xf6,0xf6) / / Scoreboard DEN1 */
847		/* AM_RANGE(0xf7,0xf7) / / Scoreboard DEN2 */
848		ADDRESS_MAP_END
849
850		static ADDRESS_MAP_START( copio, ADDRESS_SPACE_IO, 8 )
851		AM_RANGE(COP400_PORT_L, COP400_PORT_L) AM_READWRITE(cop_l_read,cop_l_write)
852		AM_RANGE(COP400_PORT_G, COP400_PORT_G) AM_READWRITE(cop_g_read,cop_g_write)
853		AM_RANGE(COP400_PORT_D, COP400_PORT_D) AM_WRITE(cop_d_write)
854		AM_RANGE(COP400_PORT_SK, COP400_PORT_SK) AM_WRITE(cop_sk_write)
855		AM_RANGE(COP400_PORT_SIO,COP400_PORT_SIO) AM_READWRITE(port_tag_to_handler8("THAYERS_LETTERS"),cop_sio_write) /* Unemulated in COP40x core, so nothing happens ATM */
856		ADDRESS_MAP_END /* This is also very wrong. The keyboard interface needs to
857		be understood much better than what I have here */
858
859		/* PORTS */
860		INPUT_PORTS_START( thayers )
861		PORT_START_TAG("DSWA")
862		PORT_DIPNAME( 0x07, 0x07, "Time Per Coin" ) PORT_DIPLOCATION( "A:3,2,1" )
863		PORT_DIPSETTING( 0x07, "110 Seconds" )
864		PORT_DIPSETTING( 0x06, "95 Seconds" )
865		PORT_DIPSETTING( 0x05, "80 Seconds" )
866		PORT_DIPSETTING( 0x04, "70 Seconds" )
867		PORT_DIPSETTING( 0x03, "60 Seconds" )
868		PORT_DIPSETTING( 0x02, "45 Seconds" )
869		PORT_DIPSETTING( 0x01, "30 Seconds" )
870		PORT_DIPSETTING( 0x00, DEF_STR ( Free_Play ) )
871		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Coinage ) ) PORT_DIPLOCATION( "A:4" )
872		PORT_DIPSETTING( 0x00, DEF_STR( 2C_1C ) )
873		PORT_DIPSETTING( 0x08, DEF_STR( 1C_1C ) )
874		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Lives ) ) PORT_DIPLOCATION( "A:5" )
875		PORT_DIPSETTING( 0x10, "3" )
876		PORT_DIPSETTING( 0x00, "5" )
877		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION( "A:6" )
878		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
879		PORT_DIPSETTING( 0x20, DEF_STR( On ) )
880		PORT_DIPNAME( 0x40, 0x40, "Attract Mode Audio" ) PORT_DIPLOCATION( "A:7" )
881		PORT_DIPSETTING( 0x40, "Always Playing" )
882		PORT_DIPSETTING( 0x00, "One Out of 8 Times" )
883		PORT_DIPUNUSED_DIPLOC( 0x80, IP_ACTIVE_LOW, "A:8" )
884
885		PORT_START_TAG("DSWB")
886		PORT_DIPNAME( 0x01, 0x01, "Gameplay Mode" ) PORT_DIPLOCATION( "B:1" )
887		PORT_DIPSETTING( 0x01, "Normal Play" )
888		PORT_DIPSETTING( 0x00, "Self-Diagnostics Mode" )
889		PORT_DIPUNUSED_DIPLOC( 0x02, IP_ACTIVE_LOW, "B:2" )
890		PORT_DIPUNUSED_DIPLOC( 0x04, IP_ACTIVE_LOW, "B:3" )
891		PORT_DIPNAME( 0x08, 0x08, "LD Player" ) PORT_DIPLOCATION( "B:4" )
892		PORT_DIPSETTING( 0x08, "LDV-1000" )
893		PORT_DIPSETTING( 0x00, "PR-7820" )
894		/* DIP SWITCH 5 isn't read here, but it also controls LD player selection - I wonder how to add it properly? */
895		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
896		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
897		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(laserdisc_command_r, 0 ) /* Enter pin on LD player */
898		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(laserdisc_status_r, 0 ) /* Ready pin on LD player */
899
900		/* The following 3 port definitions can be combined into one (thus making this scheme work) if the port bit limit is raised from 32 to 64 */
901		/* But maybe there's a better way to do it than what I have here? */
902		/* Or maybe this doesn't even work at all :) */
903		/* "Scan codes" heisted from Daphne - need to be tested! */
904		PORT_START_TAG("THAYERS_ACTIONS")
905		PORT_BIT( 0x30, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( DEF_STR( No ) ) PORT_CODE( KEYCODE_DEL_PAD )
906		PORT_BIT( 0x31, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( DEF_STR( Yes ) ) PORT_CODE( KEYCODE_0_PAD )
907		PORT_BIT( 0x32, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Items" ) PORT_CODE( KEYCODE_1_PAD )
908		PORT_BIT( 0x33, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Drop Item" ) PORT_CODE( KEYCODE_2_PAD )
909		PORT_BIT( 0x34, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Give Score" ) PORT_CODE( KEYCODE_3_PAD )
910		PORT_BIT( 0x35, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Replay" ) PORT_CODE( KEYCODE_4_PAD )
911		PORT_BIT( 0x36, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Combine Action" ) PORT_CODE( KEYCODE_6_PAD )
912		PORT_BIT( 0x37, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Save Game" ) PORT_CODE( KEYCODE_7_PAD )
913		PORT_BIT( 0x38, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Update" ) PORT_CODE( KEYCODE_8_PAD )
914		PORT_BIT( 0x39, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Hint" ) PORT_CODE( KEYCODE_9_PAD )
915
916		PORT_START_TAG("THAYERS_LETTERS")
917		PORT_BIT( 0x41, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "A" ) PORT_CODE( KEYCODE_A )
918		PORT_BIT( 0x42, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "B - Silver Wheat" ) PORT_CODE( KEYCODE_B )
919		PORT_BIT( 0x43, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "C - Spell of Seeing" ) PORT_CODE( KEYCODE_C )
920		PORT_BIT( 0x44, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "D - Great Circlet" ) PORT_CODE( KEYCODE_D )
921		PORT_BIT( 0x45, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "E - Black Mace" ) PORT_CODE( KEYCODE_E )
922		PORT_BIT( 0x46, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "F - Hunting Horn" ) PORT_CODE( KEYCODE_F )
923		PORT_BIT( 0x47, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "G - Long Bow" ) PORT_CODE( KEYCODE_G )
924		PORT_BIT( 0x48, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "H - Medallion" ) PORT_CODE( KEYCODE_H )
925		PORT_BIT( 0x49, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "I - Crown" ) PORT_CODE( KEYCODE_I )
926		PORT_BIT( 0x4a, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "J - Onyx Seal" ) PORT_CODE( KEYCODE_J )
927		PORT_BIT( 0x4b, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "K - Orb of Quoid" ) PORT_CODE( KEYCODE_K )
928		PORT_BIT( 0x4c, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "L" ) PORT_CODE( KEYCODE_L )
929		PORT_BIT( 0x4d, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "M - Spell of Understanding" ) PORT_CODE( KEYCODE_M )
930		PORT_BIT( 0x4e, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "N - Staff" ) PORT_CODE( KEYCODE_N )
931		PORT_BIT( 0x4f, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "O - Crystal" ) PORT_CODE( KEYCODE_O )
932		PORT_BIT( 0x50, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "P" ) PORT_CODE( KEYCODE_P )
933		PORT_BIT( 0x51, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Q" ) PORT_CODE( KEYCODE_Q )
934		PORT_BIT( 0x52, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "R - Blood Sword" ) PORT_CODE( KEYCODE_R )
935		PORT_BIT( 0x53, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "S - Dagger" ) PORT_CODE( KEYCODE_S )
936		PORT_BIT( 0x54, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "T - Chalice" ) PORT_CODE( KEYCODE_T )
937		PORT_BIT( 0x55, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "U - Cold Fire" ) PORT_CODE( KEYCODE_U )
938		PORT_BIT( 0x56, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "V - Shield" ) PORT_CODE( KEYCODE_V )
939		PORT_BIT( 0x57, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "W - Amulet" ) PORT_CODE( KEYCODE_W )
940		PORT_BIT( 0x58, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "X - Scepter" ) PORT_CODE( KEYCODE_X )
941		PORT_BIT( 0x59, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Y - Coins" ) PORT_CODE( KEYCODE_Y )
942		PORT_BIT( 0x5a, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "Z - Spell of Release" ) PORT_CODE( KEYCODE_Z )
943
944		PORT_START_TAG("THAYERS_NUMBERS")
945		PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "1 - Clear" ) PORT_CODE( KEYCODE_LCONTROL )
946		PORT_BIT( 0x81, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "2" ) PORT_CODE( KEYCODE_RCONTROL )
947		PORT_BIT( 0x82, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "3 - Enter" ) PORT_CODE( KEYCODE_ENTER )
948		PORT_BIT( 0x83, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "4 - Space" ) PORT_CODE( KEYCODE_SPACE )
949		INPUT_PORTS_END
950
951
952		static MACHINE_START( thayers )
953		{
954		discinfo = laserdisc_init(LASERDISC_TYPE_LDV1000, get_disk_handle(0), 0);
955		return;
956		}
957
958		static INTERRUPT_GEN( vblank_callback_thayers )
959		{
960		laserdisc_vsync(discinfo);
961		}
962
963
964		/* DRIVER */
965		static MACHINE_DRIVER_START( thayers )
966		/* main cpu */
967		MDRV_CPU_ADD(Z80, SCHEMATIC_CLOCK)
968		MDRV_CPU_PROGRAM_MAP(mainmem,0)
969		MDRV_CPU_IO_MAP(mainio,0)
970		MDRV_CPU_VBLANK_INT(vblank_callback_thayers, 1)
971
972		MDRV_MACHINE_START(thayers)
973
974		/* io device cpu */
975		MDRV_CPU_ADD(COP420, SCHEMATIC_CLOCK/2/8); /* Can't read the schematics, but this is what daphne says */
976		MDRV_CPU_PROGRAM_MAP(copmem,0)
977		MDRV_CPU_IO_MAP(copio,0)
978
979		/* video */
980		MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
981
982		MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
983		MDRV_SCREEN_REFRESH_RATE(60)
984		MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
985		MDRV_SCREEN_SIZE(3210, 328)
986		MDRV_SCREEN_VISIBLE_AREA(010, 3210-1, 08, 328-1)
987
988		MDRV_PALETTE_LENGTH(256)
989		MDRV_VIDEO_UPDATE(thayers)
990
991		/* sound */
992		MACHINE_DRIVER_END
993
994
995		ROM_START( thayers )
996		ROM_REGION( 0xe000, REGION_CPU1, 0 )
997		ROM_LOAD( "tq_u33.bin", 0x0000, 0x8000, CRC(82df5d89) SHA1(58dfd62bf8c5a55d1eba397d2c284e99a4685a3f) )
998		ROM_LOAD( "tq_u1.bin", 0xc000, 0x2000, CRC(e8e7f566) SHA1(df7b83ef465c65446c8418bc6007447693b75021) )
999
1000		ROM_REGION( 0x400, REGION_CPU2, 0 )
1001		ROM_LOAD( "tq_cop.bin", 0x000, 0x400, CRC(6748e6b3) SHA1(5d7d1ecb57c1501ef6a2d9691eecc9970586606b) )
1002		ROM_END
1003
1004		ROM_START( thayersa )
1005		ROM_REGION( 0xe000, REGION_CPU1, 0 )
1006		ROM_LOAD( "tq_u33.bin", 0x0000, 0x8000, CRC(82df5d89) SHA1(58dfd62bf8c5a55d1eba397d2c284e99a4685a3f) )
1007		ROM_LOAD( "tq_u1.bin", 0xc000, 0x2000, CRC(33817e25) SHA1(f9750da863dd57fe2f5b6e8fce9c6695dc5c9adc) )
1008
1009		ROM_REGION( 0x400, REGION_CPU2, 0 )
1010		ROM_LOAD( "tq_cop.bin", 0x000, 0x400, CRC(6748e6b3) SHA1(5d7d1ecb57c1501ef6a2d9691eecc9970586606b) )
1011		ROM_END
1012
1013		static DRIVER_INIT( thayers )
1014		{
1015		Z80_IRQ_STATUS_CLEAR();
1016		m_ssi_control = 0;
1017
1018		cop_g_latch = 0xff;
1019		}
1020
1021	510	/* YEAR NAME PARENT MACHINE INPUT INIT MONITOR COMPANY FULLNAME FLAGS) */
1022	511	GAME( 1983, thayers, 0, thayers, thayers, thayers, ROT0, "RDI Video Systems", "Thayer's Quest", GAME_NOT_WORKING\|GAME_NO_SOUND)
1023	512	GAME( 1983, thayersa, thayers, thayers, thayers, thayers, ROT0, "RDI Video Systems", "Thayer's Quest (Alternate Set)", GAME_NOT_WORKING\|GAME_NO_SOUND)

src/mame/drivers/ksys573.c
r949	r950
4060	4060	ROM_LOAD( "949jaa.u1", 0x000000, 0x000224, BAD_DUMP CRC(96c21d71) SHA1(871f1f0429154a486e547e182534db1557008dd6) )
4061	4061
4062	4062	ROM_REGION( 0x0001014, REGION_USER8, 0 ) /* game security cart eeprom */
4063		ROM_LOAD( "ge949jab.u1", 0x000000, 0x001014, BAD_DUMP CRC(~~395a~~4c79) SHA1(a~~270~~c95~~4a474~~8~~5210b3~~70dc~~1a5~~d9749a~~b321~~063c) )
	4063	ROM_LOAD( "ge949jab.u1", 0x000000, 0x001014, BAD_DUMP CRC(8645e17f) SHA1(e8a833384cb6bdb05870fcd44e7c8ed48a03c852) )
4064	4064
4065	4065	ROM_REGION( 0x1000000, REGION_USER3, 0 ) /* onboard flash */
4066	4066	ROM_FILL( 0x0000000, 0x1000000, 0xff )
r949	r950
4078	4078	DISK_IMAGE_READONLY( "949jab02", 0, MD5(331a7516a33d9cf9f04b8c9aa5de5fc1) SHA1(9aae90c6b0f5c31f47a420f876c0dbc81d43b756) )
4079	4079	ROM_END
4080	4080
	4081	ROM_START( gtfrk3ma )
	4082	ROM_REGION32_LE( 0x080000, REGION_USER1, 0 )
	4083	SYS573_BIOS_A
	4084
	4085	ROM_REGION( 0x0001014, REGION_USER2, 0 ) /* game security cart eeprom */
	4086	ROM_LOAD( "ge949jaa.u1", 0x000000, 0x001014, BAD_DUMP CRC(61f35ee1) SHA1(0a2b66742364d76ec18647b2761590bd49229625) )
	4087
	4088	ROM_REGION( 0x1000000, REGION_USER3, 0 ) /* onboard flash */
	4089	ROM_FILL( 0x0000000, 0x1000000, 0xff )
	4090
	4091	ROM_REGION( 0x2000000, REGION_USER4, 0 ) /* PCCARD1 */
	4092	ROM_FILL( 0x0000000, 0x2000000, 0xff )
	4093
	4094	ROM_REGION( 0x000008, REGION_USER9, 0 ) /* game security cart id */
	4095	ROM_LOAD( "ge949jaa.u6", 0x000000, 0x000008, BAD_DUMP CRC(ce84419e) SHA1(839e8ee080ecfc79021a06417d930e8b32dfc6a1) )
	4096
	4097	DISK_REGION( REGION_DISKS )
	4098	DISK_IMAGE_READONLY( "949jaz02", 0, MD5(22f7e1e61ea5f627e28c32f2209b5138) SHA1(62bd62cafb4bd4a1e393071f5e55d5ab57e3a880) )
	4099	ROM_END
	4100
4081	4101	ROM_START( gtrfrk4m )
4082	4102	ROM_REGION32_LE( 0x080000, REGION_USER1, 0 )
4083	4103	SYS573_BIOS_A
r949	r950
4338	4358	GAME( 2000, dncfrks, sys573, konami573, dmx, dmx, ROT0, "Konami", "Dance Freaks (G874 VER. KAA)", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING ) / BOOT VER 1.6 */
4339	4359	GAME( 2000, dmx, dncfrks, konami573, dmx, dmx, ROT0, "Konami", "Dance Maniax (G874 VER. JAA)", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING ) / BOOT VER 1.6 */
4340	4360	GAME( 2000, gtrfrk3m, sys573, konami573, gtrfrks, gtrfrkdigital,ROT0, "Konami", "Guitar Freaks 3rd Mix (GE949 VER. JAB)", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING ) /* BOOT VER 1.4 */
	4361	GAME( 2000, gtfrk3ma, gtrfrk3m, konami573, gtrfrks, gtrfrkdigital,ROT0, "Konami", "Guitar Freaks 3rd Mix - security cassette versionup (949JAZ02)", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING ) /* BOOT VER 1.4 */
4341	4362	GAME( 2000, salarymc, sys573, konami573, konami573, salarymc, ROT0, "Konami", "Salary Man Champ (GCA18 VER. JAA)", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND )
4342	4363	GAME( 2000, ddr3mp, sys573, konami573, ddr, ddrdigital, ROT0, "Konami", "Dance Dance Revolution 3rd Mix Plus (GA22 VER. JAA)", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING ) / BOOT VER 1.6 */
4343	4364	GAME( 2000, pcnfrk3m, sys573, konami573, drmn, drmndigital,ROT0, "Konami", "Percussion Freaks 3rd Mix (GA23 VER. KAA)", GAME_IMPERFECT_GRAPHICS \| GAME_IMPERFECT_SOUND \| GAME_NOT_WORKING ) / BOOT VER 1.8 */

src/mame/drivers/spaceg.c
r949	r950
243	243
244	244	y= 255 - (offset & 0xff);
245	245	x= 255 - ((offset>>8)*8);
	246	x -= ((io9400&0xe0)>>5);
246	247
247	248	/* draw modified eight pixels */
248		for (i = 0; i < 8; i++)
249		{
250		*BITMAP_ADDR16(tmpbitmap, y, x-((io9400&0xe0)>>5)) = (data&1)?Machine->pens[col]:Machine->pens[0];
251		x++;
252		data >>= 1;
253		}
	249	if (y >= 0 && y < tmpbitmap->height)
	250	for (i = 0; i < 8; i++)
	251	{
	252	if (x >= 0 && y < tmpbitmap->width)
	253	*BITMAP_ADDR16(tmpbitmap, y, x) = (data&1)?Machine->pens[col]:Machine->pens[0];
	254	x++;
	255	data >>= 1;
	256	}
254	257	}
255	258
256	259	static READ8_HANDLER(fake_r)
r949	r950
306	309
307	310	y= 255 - (offset & 0xff);
308	311	x= 255 - ((offset>>8)*8);
	312	x -= ((io9400&0xe0)>>5);
309	313
310	314	/* draw modified eight pixels */
311		for (i = 0; i < 8; i++)
312		{
313		*BITMAP_ADDR16(tmpbitmap, y, x-((io9400&0xe0)>>5)) = (data&1)?Machine->pens[col]:Machine->pens[0];
314		x++;
315		data >>= 1;
316		}
	315	if (y >= 0 && y < tmpbitmap->height)
	316	for (i = 0; i < 8; i++)
	317	{
	318	if (x >= 0 && x < tmpbitmap->width)
	319	*BITMAP_ADDR16(tmpbitmap, y, x) = (data&1)?Machine->pens[col]:Machine->pens[0];
	320	x++;
	321	data >>= 1;
	322	}
317	323	}
318	324
319	325

src/mame/drivers/ssfindo.c
r949	r950
232	232	for(y=0;y<256;y++)
233	233	for(x=0;x<320;x+=4)
234	234	{
235		*BITMAP_ADDR16(bitmap, y, x+1) = vram[s]&0xff;
236		*BITMAP_ADDR16(bitmap, y, x+2) = (vram[s]>>8)&0xff;
237		*BITMAP_ADDR16(bitmap, y, x+3) = (vram[s]>>16)&0xff;
238		*BITMAP_ADDR16(bitmap, y, x+4) = (vram[s]>>24)&0xff;
	235	*BITMAP_ADDR16(bitmap, y, x+0) = vram[s]&0xff;
	236	*BITMAP_ADDR16(bitmap, y, x+1) = (vram[s]>>8)&0xff;
	237	*BITMAP_ADDR16(bitmap, y, x+2) = (vram[s]>>16)&0xff;
	238	*BITMAP_ADDR16(bitmap, y, x+3) = (vram[s]>>24)&0xff;
239	239	s++;
240	240	}
241	241	}

src/mame/drivers/pacman.c
r949	r950
1092	1092	AM_RANGE(0x8000, 0xbfff) AM_READWRITE(MRA8_BANK2,MWA8_ROM)
1093	1093	ADDRESS_MAP_END
1094	1094
	1095	static ADDRESS_MAP_START( crushs_map, ADDRESS_SPACE_PROGRAM, 8 )
	1096	//A lot of games don't have an a15 at the cpu. Generally only games with a cpu daughter board can access the full 32k of romspace.
	1097	AM_RANGE(0x0000, 0x3fff) AM_MIRROR(0x8000) AM_ROM
	1098	AM_RANGE(0x4000, 0x43ff) AM_MIRROR(0xa000) AM_READWRITE(MRA8_RAM,pacman_videoram_w) AM_BASE(&videoram) AM_SIZE(&videoram_size)
	1099	AM_RANGE(0x4400, 0x47ff) AM_MIRROR(0xa000) AM_READWRITE(MRA8_RAM,pacman_colorram_w) AM_BASE(&colorram)
	1100	AM_RANGE(0x4800, 0x4bff) AM_MIRROR(0xa000) AM_READWRITE(pacman_read_nop,MWA8_NOP)
	1101	AM_RANGE(0x4c00, 0x4fef) AM_MIRROR(0xa000) AM_RAM
	1102	AM_RANGE(0x4ff0, 0x4fff) AM_MIRROR(0xa000) AM_RAM AM_BASE(&spriteram) AM_SIZE(&spriteram_size)
	1103	AM_RANGE(0x5000, 0x5000) AM_MIRROR(0xaf38) AM_WRITE(interrupt_enable_w)
	1104	AM_RANGE(0x5001, 0x5001) AM_MIRROR(0xaf38) AM_WRITE(pacman_sound_enable_w)
	1105	AM_RANGE(0x5002, 0x5002) AM_MIRROR(0xaf38) AM_WRITE(MWA8_NOP)
	1106	AM_RANGE(0x5003, 0x5003) AM_MIRROR(0xaf38) AM_WRITE(pacman_flipscreen_w)
	1107	AM_RANGE(0x5004, 0x5005) AM_MIRROR(0xaf38) AM_WRITE(MWA8_NOP) // AM_WRITE(pacman_leds_w)
	1108	AM_RANGE(0x5006, 0x5006) AM_MIRROR(0xaf38) AM_WRITE(MWA8_NOP) // AM_WRITE(pacman_coin_lockout_global_w)
	1109	AM_RANGE(0x5007, 0x5007) AM_MIRROR(0xaf38) AM_WRITE(pacman_coin_counter_w)
	1110	AM_RANGE(0x5040, 0x505f) AM_MIRROR(0xaf00) AM_WRITE(MWA8_NOP) // doesn't use pacman sound hw
	1111	AM_RANGE(0x5060, 0x506f) AM_MIRROR(0xaf00) AM_WRITE(MWA8_RAM) AM_BASE(&spriteram_2)
	1112	AM_RANGE(0x5070, 0x507f) AM_MIRROR(0xaf00) AM_WRITE(MWA8_NOP)
	1113	AM_RANGE(0x5080, 0x5080) AM_MIRROR(0xaf3f) AM_WRITE(MWA8_NOP)
	1114	AM_RANGE(0x50c0, 0x50c0) AM_MIRROR(0xaf3f) AM_WRITE(watchdog_reset_w)
	1115	AM_RANGE(0x5000, 0x5000) AM_MIRROR(0xaf3f) AM_READ(input_port_0_r)
	1116	AM_RANGE(0x5080, 0x5080) AM_MIRROR(0xaf3f) AM_READ(input_port_1_r)
	1117	ADDRESS_MAP_END
1095	1118
1096	1119	/*************************************
1097	1120	*
r949	r950
1167	1190	AM_RANGE(S2650_DATA_PORT, S2650_DATA_PORT) AM_WRITE(SN76496_0_w)
1168	1191	ADDRESS_MAP_END
1169	1192
	1193	static ADDRESS_MAP_START( crushs_readport, ADDRESS_SPACE_IO, 8 )
	1194	ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
	1195	AM_RANGE(0x01, 0x01) AM_READ(input_port_3_r)
	1196	AM_RANGE(0x02, 0x02) AM_READ(input_port_2_r)
	1197	ADDRESS_MAP_END
1170	1198
	1199	static ADDRESS_MAP_START( crushs_writeport, ADDRESS_SPACE_IO, 8 )
	1200	ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
	1201	AM_RANGE(0x00, 0x00) AM_WRITE(AY8910_write_port_0_w)
	1202	AM_RANGE(0x01, 0x01) AM_WRITE(AY8910_control_port_0_w)
	1203	ADDRESS_MAP_END
	1204
1171	1205	/*************************************
1172	1206	*
1173	1207	* Port definitions
r949	r950
1607	1641	INPUT_PORTS_END
1608	1642
1609	1643
	1644	INPUT_PORTS_START( crushs )
	1645	PORT_START_TAG("IN0")
	1646	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY
	1647	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY
	1648	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY
	1649	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY
	1650	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED ) /* ?? */
	1651	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
	1652	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
	1653	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE1 )
	1654
	1655	PORT_START_TAG("IN1")
	1656	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_COCKTAIL
	1657	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_COCKTAIL
	1658	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_COCKTAIL
	1659	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_COCKTAIL
	1660	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNUSED ) /* Protection */
	1661	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
	1662	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START2 )
	1663	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) /* service mode? */
	1664
	1665	PORT_START
	1666	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ))
	1667	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	1668	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1669	PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
	1670	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	1671	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1672	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
	1673	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	1674	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1675	PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
	1676	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	1677	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1678	PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
	1679	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	1680	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1681	PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
	1682	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	1683	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1684	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
	1685	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	1686	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1687	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
	1688	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	1689	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1690
	1691	/* Coinage dips, more complex than crush? */
	1692	PORT_START
	1693	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ))
	1694	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	1695	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1696	PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
	1697	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	1698	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1699	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
	1700	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	1701	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1702	PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
	1703	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
	1704	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1705	PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
	1706	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	1707	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1708	PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
	1709	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
	1710	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1711	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
	1712	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	1713	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1714	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
	1715	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	1716	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1717	INPUT_PORTS_END
	1718
	1719
1610	1720	INPUT_PORTS_START( ponpoko )
1611	1721	PORT_START_TAG("IN0")
1612	1722	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_8WAY
r949	r950
3153	3263	MDRV_GFXDECODE(crush4_gfxdecodeinfo)
3154	3264	MACHINE_DRIVER_END
3155	3265
	3266	static struct AY8910interface crushs_ay8910_interface =
	3267	{
	3268	NULL
	3269	};
3156	3270
	3271	static MACHINE_DRIVER_START( crushs )
3157	3272
	3273	/* basic machine hardware */
	3274	MDRV_IMPORT_FROM(pacman)
	3275
	3276	MDRV_CPU_MODIFY("main")
	3277	MDRV_CPU_PROGRAM_MAP(crushs_map,0)
	3278	MDRV_CPU_IO_MAP(crushs_readport,crushs_writeport)
	3279
	3280	/* sound hardware */
	3281	MDRV_SOUND_REPLACE("namco", AY8912, 1789750)
	3282	MDRV_SOUND_CONFIG(crushs_ay8910_interface)
	3283	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75)
	3284	MACHINE_DRIVER_END
	3285
3158	3286	/*************************************
3159	3287	*
3160	3288	* ROM definitions
r949	r950
3832	3960	ROM_END
3833	3961
3834	3962
	3963	ROM_START( crushbl )
	3964	ROM_REGION( 20x10000, REGION_CPU1, 0 ) / 64k for code + 64k for opcode copy to hack protection */
	3965	ROM_LOAD( "cr1.bin", 0x0000, 0x1000, CRC(e2e84cd1) SHA1(3fc5a9aa3ee219b386a1d0622547c77aca27533d) )
	3966	ROM_LOAD( "cr2.bin", 0x1000, 0x1000, CRC(ec020e6f) SHA1(eef9008c38a68ed20c1e3596016d97d4e72de9f2) )
	3967	ROM_LOAD( "cr3.bin", 0x2000, 0x1000, CRC(d4455f27) SHA1(53f8ffc28be664fa8a2d756b4c70045a3f041bea) ) // matches original
	3968	ROM_LOAD( "cr4.bin", 0x3000, 0x1000, CRC(9936ae06) SHA1(80aff9a12dab97e9d5818f7a7fac54dc52b579d4) )
	3969
	3970	/* no other roms in this set */
	3971	ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
	3972	ROM_LOAD( "maketrax.5e", 0x0000, 0x1000, CRC(91bad2da) SHA1(096197d0cb6d55bf72b5be045224f4bd6a9cfa1b) )
	3973	ROM_LOAD( "maketrax.5f", 0x1000, 0x1000, CRC(aea79f55) SHA1(279021e6771dfa5bd0b7c557aae44434286d91b7) )
	3974
	3975	ROM_REGION( 0x0120, REGION_PROMS, 0 )
	3976	ROM_LOAD( "82s123.7f", 0x0000, 0x0020, CRC(2fc650bd) SHA1(8d0268dee78e47c712202b0ec4f1f51109b1f2a5) )
	3977	ROM_LOAD( "2s140.4a", 0x0020, 0x0100, CRC(63efb927) SHA1(5c144a613fc4960a1dfd7ead89e7fee258a63171) )
	3978
	3979	ROM_REGION( 0x0200, REGION_SOUND1, 0 ) /* sound PROMs */
	3980	ROM_LOAD( "82s126.1m", 0x0000, 0x0100, CRC(a9cc86bf) SHA1(bbcec0570aeceb582ff8238a4bc8546a23430081) )
	3981	ROM_LOAD( "82s126.3m", 0x0100, 0x0100, CRC(77245b66) SHA1(0c4d0bee858b97632411c440bea6948a74759746) ) /* timing - not used */
	3982	ROM_END
	3983
3835	3984	ROM_START( crush2 )
3836	3985	ROM_REGION( 0x10000, REGION_CPU1, 0 )
3837	3986	ROM_LOAD( "tp1", 0x0000, 0x0800, CRC(f276592e) SHA1(68ebb7d9f70af868d99ec42c26bc55a54ba1f22c) )
r949	r950
4021	4170	ROM_LOAD( "82s126.3m", 0x0100, 0x0100, CRC(77245b66) SHA1(0c4d0bee858b97632411c440bea6948a74759746) ) /* timing - not used */
4022	4171	ROM_END
4023	4172
	4173	/*
4024	4174
	4175	Crush Roller (Sidam PCB)
	4176
	4177	CPU
	4178	1x SGS Z80ACPUB1 (main)
	4179	1x AY-3-8912 (sound)
	4180	1x oscillator (no speed markings)
	4181	ROMs
	4182	6x TMS2532
	4183	1x SN74S288N
	4184	1x TBP24S10N
	4185	Note
	4186	1x 22x2 edge connector
	4187	1x trimmer (volume)
	4188	2x 8 switches dip
	4189	1x 4 switches dip
	4190	1x red led
	4191	*/
	4192
	4193	ROM_START( crushs )
	4194	ROM_REGION( 20x10000, REGION_CPU1, 0 ) / 64k for code + 64k for opcode copy to hack protection */
	4195	ROM_LOAD( "11105-0.0j", 0x0000, 0x1000, CRC(dd425429) SHA1(dc3fd8b71384c25dc807caea9187a775144ad24e) )
	4196	ROM_LOAD( "11105-1.1j", 0x1000, 0x1000, CRC(f9d89eef) SHA1(4de911b68cf6044d1e50fd3f455a61327483540b) )
	4197	ROM_LOAD( "11105-2.2j", 0x2000, 0x1000, CRC(40c23a27) SHA1(b59586ec18446b866b9ef267bb876c410f2972b0) )
	4198	ROM_LOAD( "11105-3.3j", 0x3000, 0x1000, CRC(5802644f) SHA1(3ba078c9ab8c6e251f6d1a3e8b6f8bf4820340a5) )
	4199
	4200	ROM_REGION( 0x2000, REGION_GFX1, ROMREGION_DISPOSE )
	4201	ROM_LOAD( "11105-4.4j", 0x0000, 0x1000, CRC(91bad2da) SHA1(096197d0cb6d55bf72b5be045224f4bd6a9cfa1b) )
	4202	ROM_LOAD( "11105-5.5j", 0x1000, 0x1000, CRC(b5c14376) SHA1(2c8c57f96c51f12f73daf65dc2a73e8185aaacea) )
	4203
	4204	ROM_REGION( 0x0120, REGION_PROMS, 0 )
	4205	ROM_LOAD( "74s288.8a", 0x0000, 0x0020, CRC(ff344446) SHA1(45eb37533da8912645a089b014f3b3384702114a) )
	4206	ROM_LOAD( "24s10.6b", 0x0020, 0x0100, CRC(63efb927) SHA1(5c144a613fc4960a1dfd7ead89e7fee258a63171) )
	4207
	4208	/* No Sound Proms (not Namco Sound) */
	4209	ROM_END
	4210
	4211
	4212
4025	4213	ROM_START( ponpoko )
4026	4214	ROM_REGION( 0x10000, REGION_CPU1, 0 )
4027	4215	ROM_LOAD( "ppokoj1.bin", 0x0000, 0x1000, CRC(ffa3c004) SHA1(d9e3186dcd4eb94d02bd24ad56030b248721537f) )
r949	r950
5082	5270	GAME( 1981, hangly3, puckman, pacman, pacman, 0, ROT90, "hack", "Hangly-Man (set 3)", GAME_SUPPORTS_SAVE )
5083	5271	GAME( 1981, piranhah, puckman, pacman, mspacman, 0, ROT90, "hack", "Piranha (hack)", GAME_SUPPORTS_SAVE )
5084	5272	GAME( 1981, crush, 0, pacman, maketrax, maketrax, ROT90, "Kural Samno Electric", "Crush Roller (Kural Samno)", GAME_SUPPORTS_SAVE )
	5273	GAME( 1981, crushbl, crush, pacman, maketrax, 0, ROT90, "bootleg", "Crush Roller (bootleg)", GAME_SUPPORTS_SAVE )
5085	5274	GAME( 1981, crush2, crush, pacman, maketrax, 0, ROT90, "Kural Esco Electric", "Crush Roller (Kural Esco - bootleg?)", GAME_SUPPORTS_SAVE )
5086	5275	GAME( 1981, crush3, crush, pacman, maketrax, eyes, ROT90, "Kural Electric", "Crush Roller (Kural - bootleg?)", GAME_SUPPORTS_SAVE )
5087	5276	GAME( 19??, crush4, crush, crush4, crush4, 0, ROT90, "Kural TWT", "Crush Roller (Kural TWT)", GAME_SUPPORTS_SAVE )
r949	r950
5090	5279	GAME( 1981, korosuke, crush, pacman, korosuke, korosuke, ROT90, "Kural Electric", "Korosuke Roller", GAME_SUPPORTS_SAVE )
5091	5280	GAME( 1981, mbrush, crush, pacman, mbrush, maketrax, ROT90, "bootleg", "Magic Brush", GAME_SUPPORTS_SAVE )
5092	5281	GAME( 1981, paintrlr, crush, pacman, paintrlr, 0, ROT90, "bootleg", "Paint Roller", GAME_SUPPORTS_SAVE )
	5282	GAME( 19??, crushs, crush, crushs, crushs, 0, ROT90, "[Kural] (Sidam bootleg)", "Crush Roller (Sidam bootleg)", GAME_SUPPORTS_SAVE ) // Sidam PCB, no Sidam text
5093	5283	GAME( 1982, pacplus, 0, pacman, pacman, pacplus, ROT90, "[Namco] (Midway license)", "Pac-Man Plus", GAME_SUPPORTS_SAVE )
5094	5284	GAME( 1982, joyman, puckman, pacman, pacman, 0, ROT90, "hack", "Joyman", GAME_SUPPORTS_SAVE )
5095	5285	GAME( 1982, ctrpllrp, puckman, pacman, pacman, 0, ROT90, "hack", "Caterpillar Pacman Hack", GAME_SUPPORTS_SAVE )

src/mame/drivers/comebaby.c
r0	r950
	1	/* Come On Baby
	2	(c) 2000 ExPotato Co. Ltd (Excellent Potato)
	3
	4	There also appears to be a sequel which may be running on the same hardware
	5	Come On Baby - Ballympic Heroes! (c) 2001
	6
	7	This is a Korean PC based board running Windows. The game runs fully from
	8	the hard disk making these things rather fragile and prone to damage.
	9
	10	Very little is known about the actual PC at this time, and the driver is
	11	just a skeleton placeholder for the CHD dump of the hard disk.
	12
	13	*/
	14
	15	#include "driver.h"
	16
	17	VIDEO_START(comebaby)
	18	{
	19	}
	20
	21	VIDEO_UPDATE(comebaby)
	22	{
	23	return 0;
	24	}
	25
	26	static ADDRESS_MAP_START( comebaby_map, ADDRESS_SPACE_PROGRAM, 32 )
	27	AM_RANGE(0x00000000, 0x0001ffff) AM_ROM
	28	ADDRESS_MAP_END
	29
	30	INPUT_PORTS_START( comebaby )
	31	INPUT_PORTS_END
	32
	33
	34	static MACHINE_DRIVER_START( comebaby )
	35	/* basic machine hardware */
	36	MDRV_CPU_ADD(PENTIUM, 2000000000) /* Probably a Pentium .. ?? Mhz*/
	37	MDRV_CPU_PROGRAM_MAP(comebaby_map, 0)
	38
	39	/* video hardware */
	40	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
	41	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
	42	MDRV_SCREEN_REFRESH_RATE(60)
	43	MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
	44	MDRV_SCREEN_SIZE(648, 328)
	45	MDRV_SCREEN_VISIBLE_AREA(08, 648-1, 08, 328-1)
	46	MDRV_PALETTE_LENGTH(0x100)
	47
	48	MDRV_VIDEO_START(comebaby)
	49	MDRV_VIDEO_UPDATE(comebaby)
	50	MACHINE_DRIVER_END
	51
	52
	53	ROM_START(comebaby)
	54	ROM_REGION32_LE(0x20000, REGION_CPU1, 0) /* motherboard bios */
	55	ROM_LOAD("comeonbaby.pcbios", 0x000000, 0x10000, NO_DUMP )
	56
	57	DISK_REGION( REGION_DISKS )
	58	DISK_IMAGE( "comebaby", 0, SHA1(e187db3d99f7a2b0f1c33727ad6716e695ac250e) MD5(ed1c8e13a34bbf348493d2848d351849) )
	59	ROM_END
	60
	61
	62	GAME( 2000, comebaby, 0, comebaby, comebaby, 0, ROT0, "ExPotato", "Come On Baby", GAME_NOT_WORKING\|GAME_NO_SOUND )

src/mame/drivers/rabbit.c
r949	r950
254	254	/* the sprite bitmap can probably be handled better than this ... */
255	255	static void rabbit_clearspritebitmap( mame_bitmap bitmap, const rectangle cliprect )
256	256	{
257		~~UINT32~~ startx, starty;
	257	int startx, starty;
258	258	int y;
259	259	int amountx,amounty;
260	260	UINT16 *dstline;
r949	r950
268	268	amountx =650;
269	269	amounty =600;
270	270
	271	if (startx < 0) { amountx += startx; startx = 0; }
271	272	if ((startx+amountx)>=0x1000) amountx-=(0x1000-(startx+amountx));
272	273
273	274	for (y=0; y<amounty;y++)

src/osd/windows/vconv.c
r949	r950
65	65	{ 0, "-g", "/Zi" },
66	66	{ VS2005, "-fno-strict-aliasing", "" }, // deprecated in VS2005
67	67	{ 0, "-fno-strict-aliasing", "/Oa" },
	68	{ 0, "-fno-omit-frame-pointer", "" },
68	69	{ 0, "-Werror", "/WX" },
69	70	{ VS2005, "-Wall", "/Wall /W3 /wd4018 /wd4146 /wd4242 /wd4244 /wd4305 /wd4619 /wd4702 /wd4706 /wd4710 /wd4711 /wd4738 /wd4826" },
70	71	{ VS7, "-Wall", "/Wall /W3 /wd4018 /wd4146 /wd4242 /wd4244 /wd4305 /wd4550 /wd4619 /wd4702 /wd4706 /wd4710 /wd4711 /wd4826" },

src/osd/windows/window.c
r949	r950
326	326
327	327
328	328	//============================================================
	329	// is_mame_window
	330	//============================================================
	331
	332	static BOOL is_mame_window(HWND hwnd)
	333	{
	334	win_window_info *window;
	335
	336	for (window = win_window_list; window != NULL; window = window->next)
	337	if (window->hwnd == hwnd)
	338	return TRUE;
	339
	340	return FALSE;
	341	}
	342
	343
	344
	345	//============================================================
329	346	// winwindow_process_events
330	347	// (main thread)
331	348	//============================================================
332	349
333	350	void winwindow_process_events(int ingame)
334	351	{
335		int is_debugger_visible = 0;
336	352	MSG message;
337	353
338	354	assert(GetCurrentThreadId() == main_threadid);
r949	r950
340	356	// if we're running, disable some parts of the debugger
341	357	#if defined(MAME_DEBUG)
342	358	if (ingame)
343		{
344		is_debugger_visible = (Machine != NULL && Machine->debug_mode && debugwin_is_debugger_visible());
345	359	debugwin_update_during_game();
346		}
347	360	#endif
348	361
349	362	// remember the last time we did this
r949	r950
360	373	{
361	374	int dispatch = TRUE;
362	375
363		swi~~tch~~ (message.message)
	376	if ((message.hwnd == NULL) \|\| is_mame_window(message.hwnd))
364	377	{
365		// ignore keyboard messages
366		case WM_SYSKEYUP:
367		case WM_SYSKEYDOWN:
	378	switch (message.message)
	379	{
	380	// ignore keyboard messages
	381	case WM_SYSKEYUP:
	382	case WM_SYSKEYDOWN:
368	383	#ifndef MESS
369		case WM_KEYUP:
370		case WM_KEYDOWN:
371		case WM_CHAR:
	384	case WM_KEYUP:
	385	case WM_KEYDOWN:
	386	case WM_CHAR:
372	387	#endif
373		dispatch = is_debugger_visible;
374		break;
	388	dispatch = FALSE;
	389	break;
375	390
376		// special case for quit
377		case WM_QUIT:
378		mame_schedule_exit(Machine);
379		break;
	391	// special case for quit
	392	case WM_QUIT:
	393	mame_schedule_exit(Machine);
	394	break;
380	395
381		// temporary pause from the window thread
382		case WM_USER_UI_TEMP_PAUSE:
383		winwindow_ui_pause_from_main_thread(message.wParam);
384		dispatch = FALSE;
385		break;
	396	// temporary pause from the window thread
	397	case WM_USER_UI_TEMP_PAUSE:
	398	winwindow_ui_pause_from_main_thread(message.wParam);
	399	dispatch = FALSE;
	400	break;
386	401
387		// execute arbitrary function
388		case WM_USER_EXEC_FUNC:
389		{
390		void (func)(void ) = (void ()(void )) message.wParam;
391		void param = (void ) message.lParam;
392		func(param);
393		}
394		break;
	402	// execute arbitrary function
	403	case WM_USER_EXEC_FUNC:
	404	{
	405	void (func)(void ) = (void ()(void )) message.wParam;
	406	void param = (void ) message.lParam;
	407	func(param);
	408	}
	409	break;
395	410
396		// forward mouse button downs to the input system
397		case WM_LBUTTONDOWN:
398		wininput_handle_mouse_button(0, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
399		dispatch = is_debugger_visible;
400		break;
	411	// forward mouse button downs to the input system
	412	case WM_LBUTTONDOWN:
	413	wininput_handle_mouse_button(0, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	414	dispatch = FALSE;
	415	break;
401	416
402		case WM_RBUTTONDOWN:
403		wininput_handle_mouse_button(1, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
404		dispatch = is_debugger_visible;
405		break;
	417	case WM_RBUTTONDOWN:
	418	wininput_handle_mouse_button(1, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	419	dispatch = FALSE;
	420	break;
406	421
407		case WM_MBUTTONDOWN:
408		wininput_handle_mouse_button(2, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
409		dispatch = is_debugger_visible;
410		break;
	422	case WM_MBUTTONDOWN:
	423	wininput_handle_mouse_button(2, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	424	dispatch = FALSE;
	425	break;
411	426
412		case WM_XBUTTONDOWN:
413		wininput_handle_mouse_button(3, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
414		dispatch = is_debugger_visible;
415		break;
	427	case WM_XBUTTONDOWN:
	428	wininput_handle_mouse_button(3, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	429	dispatch = FALSE;
	430	break;
416	431
417		// forward mouse button ups to the input system
418		case WM_LBUTTONUP:
419		wininput_handle_mouse_button(0, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
420		dispatch = is_debugger_visible;
421		break;
	432	// forward mouse button ups to the input system
	433	case WM_LBUTTONUP:
	434	wininput_handle_mouse_button(0, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	435	dispatch = FALSE;
	436	break;
422	437
423		case WM_RBUTTONUP:
424		wininput_handle_mouse_button(1, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
425		dispatch = is_debugger_visible;
426		break;
	438	case WM_RBUTTONUP:
	439	wininput_handle_mouse_button(1, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	440	dispatch = FALSE;
	441	break;
427	442
428		case WM_MBUTTONUP:
429		wininput_handle_mouse_button(2, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
430		dispatch = is_debugger_visible;
431		break;
	443	case WM_MBUTTONUP:
	444	wininput_handle_mouse_button(2, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	445	dispatch = FALSE;
	446	break;
432	447
433		case WM_XBUTTONUP:
434		wininput_handle_mouse_button(3, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
435		dispatch = is_debugger_visible;
436		break;
	448	case WM_XBUTTONUP:
	449	wininput_handle_mouse_button(3, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	450	dispatch = FALSE;
	451	break;
	452	}
437	453	}
438	454
439	455	// dispatch if necessary
r949	r950
1049	1065	{
1050	1066	int dispatch = TRUE;
1051	1067
1052		swi~~tch~~ (message.message)
	1068	if ((message.hwnd == NULL) \|\| is_mame_window(message.hwnd))
1053	1069	{
1054		// ignore input messages here
1055		case WM_SYSKEYUP:
1056		case WM_SYSKEYDOWN:
	1070	switch (message.message)
	1071	{
	1072	// ignore input messages here
	1073	case WM_SYSKEYUP:
	1074	case WM_SYSKEYDOWN:
1057	1075	#ifndef MESS
1058		case WM_KEYUP:
1059		case WM_KEYDOWN:
1060		case WM_CHAR:
	1076	case WM_KEYUP:
	1077	case WM_KEYDOWN:
	1078	case WM_CHAR:
1061	1079	#endif // MESS
1062		dispatch = FALSE;
1063		break;
	1080	dispatch = FALSE;
	1081	break;
1064	1082
1065		// forward mouse button downs to the input system
1066		case WM_LBUTTONDOWN:
1067		wininput_handle_mouse_button(0, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
1068		dispatch = FALSE;
1069		break;
	1083	// forward mouse button downs to the input system
	1084	case WM_LBUTTONDOWN:
	1085	wininput_handle_mouse_button(0, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	1086	dispatch = FALSE;
	1087	break;
1070	1088
1071		case WM_RBUTTONDOWN:
1072		wininput_handle_mouse_button(1, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
1073		dispatch = FALSE;
1074		break;
	1089	case WM_RBUTTONDOWN:
	1090	wininput_handle_mouse_button(1, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	1091	dispatch = FALSE;
	1092	break;
1075	1093
1076		case WM_MBUTTONDOWN:
1077		wininput_handle_mouse_button(2, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
1078		dispatch = FALSE;
1079		break;
	1094	case WM_MBUTTONDOWN:
	1095	wininput_handle_mouse_button(2, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	1096	dispatch = FALSE;
	1097	break;
1080	1098
1081		case WM_XBUTTONDOWN:
1082		wininput_handle_mouse_button(3, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
1083		dispatch = FALSE;
1084		break;
	1099	case WM_XBUTTONDOWN:
	1100	wininput_handle_mouse_button(3, TRUE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	1101	dispatch = FALSE;
	1102	break;
1085	1103
1086		// forward mouse button ups to the input system
1087		case WM_LBUTTONUP:
1088		wininput_handle_mouse_button(0, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
1089		dispatch = FALSE;
1090		break;
	1104	// forward mouse button ups to the input system
	1105	case WM_LBUTTONUP:
	1106	wininput_handle_mouse_button(0, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	1107	dispatch = FALSE;
	1108	break;
1091	1109
1092		case WM_RBUTTONUP:
1093		wininput_handle_mouse_button(1, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
1094		dispatch = FALSE;
1095		break;
	1110	case WM_RBUTTONUP:
	1111	wininput_handle_mouse_button(1, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	1112	dispatch = FALSE;
	1113	break;
1096	1114
1097		case WM_MBUTTONUP:
1098		wininput_handle_mouse_button(2, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
1099		dispatch = FALSE;
1100		break;
	1115	case WM_MBUTTONUP:
	1116	wininput_handle_mouse_button(2, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	1117	dispatch = FALSE;
	1118	break;
1101	1119
1102		case WM_XBUTTONUP:
1103		wininput_handle_mouse_button(3, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
1104		dispatch = FALSE;
1105		break;
	1120	case WM_XBUTTONUP:
	1121	wininput_handle_mouse_button(3, FALSE, GET_X_LPARAM(message.lParam), GET_Y_LPARAM(message.lParam));
	1122	dispatch = FALSE;
	1123	break;
1106	1124
1107		// a terminate message to the thread posts a quit
1108		case WM_USER_SELF_TERMINATE:
1109		PostQuitMessage(0);
1110		dispatch = FALSE;
1111		break;
	1125	// a terminate message to the thread posts a quit
	1126	case WM_USER_SELF_TERMINATE:
	1127	PostQuitMessage(0);
	1128	dispatch = FALSE;
	1129	break;
1112	1130
1113		// handle the "complete create" message
1114		case WM_USER_FINISH_CREATE_WINDOW:
1115		{
1116		win_window_info window = (win_window_info )message.lParam;
1117		window->init_state = complete_create(window) ? -1 : 1;
1118		dispatch = FALSE;
1119		break;
	1131	// handle the "complete create" message
	1132	case WM_USER_FINISH_CREATE_WINDOW:
	1133	{
	1134	win_window_info window = (win_window_info )message.lParam;
	1135	window->init_state = complete_create(window) ? -1 : 1;
	1136	dispatch = FALSE;
	1137	break;
	1138	}
1120	1139	}
1121	1140	}
1122	1141

src/osd/windows/ui/win32ui.c
r949	r950
911	911	{
912	912	DWORD dwExitCode = 0;
913	913	core_options *pOpts;
	914	core_options *opts;
914	915	LPTREEFOLDER folder;
915	916	int i;
916	917
917	918	// set up MAME options
918		mame_options_init(mame_win_options);
	919	opts = mame_options_init(mame_win_options);
919	920
920	921	// retrieve the options we're going to pass
921	922	folder = GetFolderByName(FOLDER_SOURCE, GetDriverFilename(nGameIndex));
r949	r950
926	927
927	928	#ifdef MESS
928	929	// add MESS specific device options
929		mess_add_device_options(~~mame_~~opt~~ion~~s(), drivers[nGameIndex]);
	930	mess_add_device_options(opts, drivers[nGameIndex]);
930	931	#endif // MESS
931	932
932	933	// load MAME options
933		CopyOptions(mame_options(), Mame32Global());
934		CopyOptions(mame_options(), pOpts);
	934	CopyOptions(opts, Mame32Global());
	935	CopyOptions(opts, pOpts);
935	936
936	937	// load specified play options
937	938	if (playopts != NULL)
938	939	{
939	940	if (playopts->record != NULL)
940		options_set_string(~~mame_~~opt~~ion~~s(), OPTION_RECORD, playopts->record, OPTION_PRIORITY_CMDLINE);
	941	options_set_string(opts, OPTION_RECORD, playopts->record, OPTION_PRIORITY_CMDLINE);
941	942	if (playopts->playback != NULL)
942		options_set_string(~~mame_~~opt~~ion~~s(), OPTION_PLAYBACK, playopts->playback, OPTION_PRIORITY_CMDLINE);
	943	options_set_string(opts, OPTION_PLAYBACK, playopts->playback, OPTION_PRIORITY_CMDLINE);
943	944	if (playopts->state != NULL)
944		options_set_string(~~mame_~~opt~~ion~~s(), OPTION_STATE, playopts->state, OPTION_PRIORITY_CMDLINE);
	945	options_set_string(opts, OPTION_STATE, playopts->state, OPTION_PRIORITY_CMDLINE);
945	946	if (playopts->wavwrite != NULL)
946		options_set_string(~~mame_~~opt~~ion~~s(), OPTION_WAVWRITE, playopts->wavwrite, OPTION_PRIORITY_CMDLINE);
	947	options_set_string(opts, OPTION_WAVWRITE, playopts->wavwrite, OPTION_PRIORITY_CMDLINE);
947	948	if (playopts->mngwrite != NULL)
948		options_set_string(~~mame_~~opt~~ion~~s(), OPTION_MNGWRITE, playopts->mngwrite, OPTION_PRIORITY_CMDLINE);
	949	options_set_string(opts, OPTION_MNGWRITE, playopts->mngwrite, OPTION_PRIORITY_CMDLINE);
949	950	}
950	951
951	952	// prepare MAME32 to run the game
r949	r950
954	955	Picker_ClearIdle(GetDlgItem(hMain, s_nPickers[i]));
955	956
956	957	// run the emulation
957		options_set_string(mame_options(), OPTION_GAMENAME, drivers[nGameIndex]->name, OPTION_PRIORITY_CMDLINE);
958		mame_execute();
	958	options_set_string(opts, OPTION_GAMENAME, drivers[nGameIndex]->name, OPTION_PRIORITY_CMDLINE);
	959	mame_execute(opts);
959	960
960	961	// the emulation is complete; continue
961	962	for (i = 0; i < ARRAY_LENGTH(s_nPickers); i++)
r949	r950
964	965	SetForegroundWindow(hMain);
965	966
966	967	// close out MAME options
967		~~mame_~~options_e~~xit~~();
	968	options_free(opts);
968	969
969	970	// NPW 16-Apr-2007 - God I hate this hack
970	971	if (GetGameUsesDefaults(nGameIndex))

src/osd/windows/ui/audit32.c
r949	r950
177	177	audit_record *audit;
178	178	int audit_records;
179	179	int res;
	180	core_options *opts;
180	181
181		mame_options_init(mame_win_options);
182		options_set_string(mame_options(), OPTION_ROMPATH, GetRomDirs(), OPTION_PRIORITY_CMDLINE);
183		options_set_string(mame_options(), OPTION_SAMPLEPATH, GetSampleDirs(), OPTION_PRIORITY_CMDLINE);
	182	opts = mame_options_init(mame_win_options);
	183	options_set_string(opts, OPTION_ROMPATH, GetRomDirs(), OPTION_PRIORITY_CMDLINE);
	184	options_set_string(opts, OPTION_SAMPLEPATH, GetSampleDirs(), OPTION_PRIORITY_CMDLINE);
184	185
185	186	// perform the audit
186		audit_records = audit_images(drivers[game], AUDIT_VALIDATE_FAST, &audit);
	187	audit_records = audit_images(mame_options(), drivers[game], AUDIT_VALIDATE_FAST, &audit);
187	188	res = ProcessAuditResults(game, audit, audit_records);
188	189	if (audit_records > 0)
189	190	free(audit);
190	191
191	192	SetRomAuditResults(game, res);
192		~~mame_~~options_e~~xit~~();
	193	options_free(opts);
193	194	return res;
194	195	}
195	196
r949	r950
199	200	audit_record *audit;
200	201	int audit_records;
201	202	int res;
	203	core_options *opts;
202	204
203		mame_options_init(mame_win_options);
204		options_set_string(mame_options(), OPTION_ROMPATH, GetRomDirs(), OPTION_PRIORITY_CMDLINE);
205		options_set_string(mame_options(), OPTION_SAMPLEPATH, GetSampleDirs(), OPTION_PRIORITY_CMDLINE);
	205	opts = mame_options_init(mame_win_options);
	206	options_set_string(opts, OPTION_ROMPATH, GetRomDirs(), OPTION_PRIORITY_CMDLINE);
	207	options_set_string(opts, OPTION_SAMPLEPATH, GetSampleDirs(), OPTION_PRIORITY_CMDLINE);
206	208
207	209	// perform the audit
208		audit_records = audit_samples(drivers[game], &audit);
	210	audit_records = audit_samples(opts, drivers[game], &audit);
209	211	res = ProcessAuditResults(game, audit, audit_records);
210	212	if (audit_records > 0)
211	213	free(audit);
212	214
213	215	SetSampleAuditResults(game, res);
214		~~mame_~~options_e~~xit~~();
	216	options_free(opts);
215	217	return res;
216	218	}
217	219

src/emu/romload.h
r949	r950
283	283
284	284	/* disk handling */
285	285	chd_error open_disk_image(const game_driver gamedrv, const rom_entry romp, mame_file image_file, chd_file image_chd);
	286	chd_error open_disk_image_options(core_options options, const game_driver gamedrv, const rom_entry romp, mame_file image_file, chd_file *image_chd);
286	287	chd_file *get_disk_handle(int diskindex);
287	288
288	289	/* ROM processing */

src/emu/cpu/cpu.mak
r949	r950
32	32
33	33	DRCOBJ = $(CPUOBJ)/x86drc.o
34	34
35		DRCDEPS = $(CPUSRC)/x86drc.c \
	35	DRCDEPS = $(CPUSRC)/x86emit.h \
	36	$(CPUSRC)/x86drc.c \
36	37	$(CPUSRC)/x86drc.h \
37	38
38	39	$(DRCOBJ): $(DRCDEPS)

src/emu/cpu/hd6309/6309ops.c
r949	r950
260	260	q.d = SIGNED_16(W);
261	261	D = q.w.h;
262	262	W = q.w.l;
263		CLR_NZV;
	263	CLR_NZ;
264	264	SET_N16(D);
265	265	SET_Z(q.d);
266	266	}
r949	r950
971	971	INLINE void tfmpp( void )
972	972	{
973	973	UINT8 tb, srcValue = 0;
974		int done = FALSE;
975	974
976	975	IMMBYTE(tb);
977	976
r949	r950
983	982	case 2: srcValue = RM(Y++); break;
984	983	case 3: srcValue = RM(U++); break;
985	984	case 4: srcValue = RM(S++); break;
986		case 5: /* PC */ done = TRUE; break;
987		case 6: /* W */ done = TRUE; break;
988		case 7: /* V */ done = TRUE; break;
989		case 8: /* A */ done = TRUE; break;
990		case 9: /* B */ done = TRUE; break;
991		case 10: /* CC */ done = TRUE; break;
992		case 11: /* DP */ done = TRUE; break;
993		case 12: /* 0 */ done = TRUE; break;
994		case 13: /* 0 */ done = TRUE; break;
995		case 14: /* E */ done = TRUE; break;
996		default: /* F */ done = TRUE; break;
	985	default: IIError(); return; break; /* reg PC thru F */
997	986	}
998	987
999		if ( !done )
1000		{
1001		switch(tb&15) {
1002		case 0: WM(D++, srcValue); break;
1003		case 1: WM(X++, srcValue); break;
1004		case 2: WM(Y++, srcValue); break;
1005		case 3: WM(U++, srcValue); break;
1006		case 4: WM(S++, srcValue); break;
1007		case 5: /* PC */ done = TRUE; break;
1008		case 6: /* W */ done = TRUE; break;
1009		case 7: /* V */ done = TRUE; break;
1010		case 8: /* A */ done = TRUE; break;
1011		case 9: /* B */ done = TRUE; break;
1012		case 10: /* CC */ done = TRUE; break;
1013		case 11: /* DP */ done = TRUE; break;
1014		case 12: /* 0 */ done = TRUE; break;
1015		case 13: /* 0 */ done = TRUE; break;
1016		case 14: /* E */ done = TRUE; break;
1017		default: /* F */ done = TRUE; break;
1018		}
1019
1020		PCD = PCD - 3;
1021		CHANGE_PC;
1022		W--;
	988	switch(tb&15) {
	989	case 0: WM(D++, srcValue); break;
	990	case 1: WM(X++, srcValue); break;
	991	case 2: WM(Y++, srcValue); break;
	992	case 3: WM(U++, srcValue); break;
	993	case 4: WM(S++, srcValue); break;
	994	default: IIError(); return; break; /* reg PC thru F */
1023	995	}
	996
	997	PCD = PCD - 3;
	998	CHANGE_PC;
	999	W--;
1024	1000	}
1025	1001	else
1026	1002	hd6309_ICount -= 6; /* Needs six aditional cycles to get the 6+3n */
r949	r950
1030	1006	INLINE void tfmmm( void )
1031	1007	{
1032	1008	UINT8 tb, srcValue = 0;
1033		int done = FALSE;
1034	1009
1035	1010	IMMBYTE(tb);
1036	1011
r949	r950
1042	1017	case 2: srcValue = RM(Y--); break;
1043	1018	case 3: srcValue = RM(U--); break;
1044	1019	case 4: srcValue = RM(S--); break;
1045		case 5: /* PC */ done = TRUE; break;
1046		case 6: /* W */ done = TRUE; break;
1047		case 7: /* V */ done = TRUE; break;
1048		case 8: /* A */ done = TRUE; break;
1049		case 9: /* B */ done = TRUE; break;
1050		case 10: /* CC */ done = TRUE; break;
1051		case 11: /* DP */ done = TRUE; break;
1052		case 12: /* 0 */ done = TRUE; break;
1053		case 13: /* 0 */ done = TRUE; break;
1054		case 14: /* E */ done = TRUE; break;
1055		default: /* F */ done = TRUE; break;
	1020	default: IIError(); return; break; /* reg PC thru F */
1056	1021	}
1057	1022
1058		if ( !done )
1059		{
1060		switch(tb&15) {
1061		case 0: WM(D--, srcValue); break;
1062		case 1: WM(X--, srcValue); break;
1063		case 2: WM(Y--, srcValue); break;
1064		case 3: WM(U--, srcValue); break;
1065		case 4: WM(S--, srcValue); break;
1066		case 5: /* PC */ done = TRUE; break;
1067		case 6: /* W */ done = TRUE; break;
1068		case 7: /* V */ done = TRUE; break;
1069		case 8: /* A */ done = TRUE; break;
1070		case 9: /* B */ done = TRUE; break;
1071		case 10: /* CC */ done = TRUE; break;
1072		case 11: /* DP */ done = TRUE; break;
1073		case 12: /* 0 */ done = TRUE; break;
1074		case 13: /* 0 */ done = TRUE; break;
1075		case 14: /* E */ done = TRUE; break;
1076		default: /* F */ done = TRUE; break;
1077		}
1078
1079		PCD = PCD - 3;
1080		CHANGE_PC;
1081		W--;
	1023	switch(tb&15) {
	1024	case 0: WM(D--, srcValue); break;
	1025	case 1: WM(X--, srcValue); break;
	1026	case 2: WM(Y--, srcValue); break;
	1027	case 3: WM(U--, srcValue); break;
	1028	case 4: WM(S--, srcValue); break;
	1029	default: IIError(); return; break; /* reg PC thru F */
1082	1030	}
	1031
	1032	PCD = PCD - 3;
	1033	CHANGE_PC;
	1034	W--;
1083	1035	}
1084	1036	else
1085	1037	hd6309_ICount -= 6; /* Needs six aditional cycles to get the 6+3n */
r949	r950
1089	1041	INLINE void tfmpc( void )
1090	1042	{
1091	1043	UINT8 tb, srcValue = 0;
1092		int done = FALSE;
1093	1044
1094	1045	IMMBYTE(tb);
1095	1046
r949	r950
1101	1052	case 2: srcValue = RM(Y++); break;
1102	1053	case 3: srcValue = RM(U++); break;
1103	1054	case 4: srcValue = RM(S++); break;
1104		case 5: /* PC */ done = TRUE; break;
1105		case 6: /* W */ done = TRUE; break;
1106		case 7: /* V */ done = TRUE; break;
1107		case 8: /* A */ done = TRUE; break;
1108		case 9: /* B */ done = TRUE; break;
1109		case 10: /* CC */ done = TRUE; break;
1110		case 11: /* DP */ done = TRUE; break;
1111		case 12: /* 0 */ done = TRUE; break;
1112		case 13: /* 0 */ done = TRUE; break;
1113		case 14: /* E */ done = TRUE; break;
1114		default: /* F */ done = TRUE; break;
	1055	default: IIError(); return; break; /* reg PC thru F */
1115	1056	}
1116	1057
1117		if ( !done )
1118		{
1119		switch(tb&15) {
1120		case 0: WM(D, srcValue); break;
1121		case 1: WM(X, srcValue); break;
1122		case 2: WM(Y, srcValue); break;
1123		case 3: WM(U, srcValue); break;
1124		case 4: WM(S, srcValue); break;
1125		case 5: /* PC */ done = TRUE; break;
1126		case 6: /* W */ done = TRUE; break;
1127		case 7: /* V */ done = TRUE; break;
1128		case 8: /* A */ done = TRUE; break;
1129		case 9: /* B */ done = TRUE; break;
1130		case 10: /* CC */ done = TRUE; break;
1131		case 11: /* DP */ done = TRUE; break;
1132		case 12: /* 0 */ done = TRUE; break;
1133		case 13: /* 0 */ done = TRUE; break;
1134		case 14: /* E */ done = TRUE; break;
1135		default: /* F */ done = TRUE; break;
1136		}
1137
1138		PCD = PCD - 3;
1139		CHANGE_PC;
1140		W--;
	1058	switch(tb&15) {
	1059	case 0: WM(D, srcValue); break;
	1060	case 1: WM(X, srcValue); break;
	1061	case 2: WM(Y, srcValue); break;
	1062	case 3: WM(U, srcValue); break;
	1063	case 4: WM(S, srcValue); break;
	1064	default: IIError(); return; break; /* reg PC thru F */
1141	1065	}
	1066
	1067	PCD = PCD - 3;
	1068	CHANGE_PC;
	1069	W--;
1142	1070	}
1143	1071	else
1144	1072	hd6309_ICount -= 6; /* Needs six aditional cycles to get the 6+3n */
r949	r950
1148	1076	INLINE void tfmcp( void )
1149	1077	{
1150	1078	UINT8 tb, srcValue = 0;
1151		int done = FALSE;
1152	1079
1153	1080	IMMBYTE(tb);
1154	1081
r949	r950
1160	1087	case 2: srcValue = RM(Y); break;
1161	1088	case 3: srcValue = RM(U); break;
1162	1089	case 4: srcValue = RM(S); break;
1163		case 5: /* PC */ done = TRUE; break;
1164		case 6: /* W */ done = TRUE; break;
1165		case 7: /* V */ done = TRUE; break;
1166		case 8: /* A */ done = TRUE; break;
1167		case 9: /* B */ done = TRUE; break;
1168		case 10: /* CC */ done = TRUE; break;
1169		case 11: /* DP */ done = TRUE; break;
1170		case 12: /* 0 */ done = TRUE; break;
1171		case 13: /* 0 */ done = TRUE; break;
1172		case 14: /* E */ done = TRUE; break;
1173		default: /* F */ done = TRUE; break;
	1090	default: IIError(); return; break; /* reg PC thru F */
1174	1091	}
1175	1092
1176		if ( !done )
1177		{
1178		switch(tb&15) {
1179		case 0: WM(D++, srcValue); break;
1180		case 1: WM(X++, srcValue); break;
1181		case 2: WM(Y++, srcValue); break;
1182		case 3: WM(U++, srcValue); break;
1183		case 4: WM(S++, srcValue); break;
1184		case 5: /* PC */ done = TRUE; break;
1185		case 6: /* W */ done = TRUE; break;
1186		case 7: /* V */ done = TRUE; break;
1187		case 8: /* A */ done = TRUE; break;
1188		case 9: /* B */ done = TRUE; break;
1189		case 10: /* CC */ done = TRUE; break;
1190		case 11: /* DP */ done = TRUE; break;
1191		case 12: /* 0 */ done = TRUE; break;
1192		case 13: /* 0 */ done = TRUE; break;
1193		case 14: /* E */ done = TRUE; break;
1194		default: /* F */ done = TRUE; break;
1195		}
1196
1197		PCD = PCD - 3;
1198		CHANGE_PC;
1199		W--;
	1093	switch(tb&15) {
	1094	case 0: WM(D++, srcValue); break;
	1095	case 1: WM(X++, srcValue); break;
	1096	case 2: WM(Y++, srcValue); break;
	1097	case 3: WM(U++, srcValue); break;
	1098	case 4: WM(S++, srcValue); break;
	1099	default: IIError(); return; break; /* reg PC thru F */
1200	1100	}
	1101
	1102	PCD = PCD - 3;
	1103	CHANGE_PC;
	1104	W--;
1201	1105	}
1202	1106	else
1203	1107	hd6309_ICount -= 6; /* Needs six aditional cycles to get the 6+3n */

src/emu/cpu/hd6309/hd6309.c
r949	r950
93	93	to not set I and F condition codes. Credit to Darren Atkinson for the
94	94	discovery of these bugs.
95	95
	96	090907 TJL:
	97	The SEXW instruction is clearing the Overflow flag (V). It should not do
	98	that. When an invalid source or destination register is specified for
	99	the TFM instructions, real hardware invokes the Illegal Instruction
	100	trap, whereas the emulator simply ignores the instruction. Credit to
	101	Darren Atkinson for the discovery of these bugs.
	102
96	103	*****************************************************************************/
97	104
98	105	#include "debugger.h"

src/emu/cpu/x86drc.c
r949	r950
83	83	drc->cache_size = config->cache_size - sizeof(*drc);
84	84	drc->cache_end = drc->cache_base + drc->cache_size;
85	85	drc->cache_danger = drc->cache_end - 65536;
86		drc->cache_allocated = ~~drc->~~cache_allocated;
	86	drc->cache_allocated = cache_allocated;
87	87
88	88	/* compute shifts and masks */
89	89	drc->l1bits = effective_address_bits/2;
r949	r950
162	162	append_out_of_cycles(drc);
163	163
164	164	/* append an INT 3 before the recompile so that BREAK_ON_MODIFIED_CODE works */
165		_int(3);
	165	emit_int_3(DRCTOP);
166	166	drc->recompile = drc->cache_top;
167	167	append_recompile(drc);
168	168	drc->dispatch = drc->cache_top;
r949	r950
262	262	{
263	263	UINT8 *cache_save = drc->cache_top;
264	264	drc->cache_top = drc->lookup_l1[l1index][l2index];
265		_jmp(drc->dispatch);
	265	emit_jmp(DRCTOP, drc->dispatch);
266	266	drc->cache_top = cache_save;
267	267	}
268	268
r949	r950
286	286	{
287	287	UINT8 *cache_save = drc->cache_top;
288	288	drc->cache_top = drc->tentative_list[i].target;
289		_jmp(drc->sequence_list[j].target);
	289	emit_jmp(DRCTOP, drc->sequence_list[j].target);
290	290	drc->cache_top = cache_save;
291	291	break;
292	292	}
r949	r950
326	326	void drc_append_verify_code(drc_core drc, void code, UINT8 length)
327	327	{
328	328	#if BREAK_ON_MODIFIED_CODE
329		void recompile = ~~(UINT8 )~~drc->recompile - 1;
	329	x86code *recompile = drc->recompile - 1;
330	330	#else
331		void *recompile = drc->recompile;
	331	x86code *recompile = drc->recompile;
332	332	#endif
333	333
334	334	if (length > 8)
r949	r950
343	343	sum += *codeptr++;
344	344	}
345	345
346		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
347		_mov_r32_imm(REG_EBX, code); // mov ebx,code
348		_mov_r32_imm(REG_ECX, length / 4); // mov ecx,length / 4
349		target = drc->cache_top; // target:
350		_ror_r32_imm(REG_EAX, 1); // ror eax,1
351		_add_r32_m32bd(REG_EAX, REG_EBX, 0); // add eax,[ebx]
352		_sub_or_dec_r32_imm(REG_ECX, 1); // sub ecx,1
353		_lea_r32_m32bd(REG_EBX, REG_EBX, 4); // lea ebx,[ebx+4]
354		_jcc(COND_NZ, target); // jnz target
355		_cmp_r32_imm(REG_EAX, sum); // cmp eax,sum
356		_jcc(COND_NE, recompile); // jne recompile
	346	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX); // xor eax,eax
	347	emit_mov_r32_imm(DRCTOP, REG_EBX, (FPTR)code); // mov ebx,code
	348	emit_mov_r32_imm(DRCTOP, REG_ECX, length / 4); // mov ecx,length / 4
	349	target = drc->cache_top; // target:
	350	emit_ror_r32_imm(DRCTOP, REG_EAX, 1); // ror eax,1
	351	emit_add_r32_m32(DRCTOP, REG_EAX, MBD(REG_EBX, 0)); // add eax,[ebx]
	352	emit_sub_r32_imm(DRCTOP, REG_ECX, 1); // sub ecx,1
	353	emit_lea_r32_m32(DRCTOP, REG_EBX, MBD(REG_EBX, 4)); // lea ebx,[ebx+4]
	354	emit_jcc(DRCTOP, COND_NZ, target); // jnz target
	355	emit_cmp_r32_imm(DRCTOP, REG_EAX, sum); // cmp eax,sum
	356	emit_jcc(DRCTOP, COND_NE, recompile); // jne recompile
357	357	}
358	358	else if (length >= 12)
359	359	{
360		_cmp_m32abs_imm(code, (UINT32 )code); // cmp [pc],opcode
361		_jcc(COND_NE, recompile); // jne recompile
362		_cmp_m32abs_imm((UINT8 )code + 4, ((UINT32 )code)[1]); // cmp [pc+4],opcode+4
363		_jcc(COND_NE, recompile); // jne recompile
364		_cmp_m32abs_imm((UINT8 )code + 8, ((UINT32 )code)[2]); // cmp [pc+8],opcode+8
365		_jcc(COND_NE, recompile); // jne recompile
	360	emit_cmp_m32_imm(DRCTOP, MABS(code), (UINT32 )code); // cmp [pc],opcode
	361	emit_jcc(DRCTOP, COND_NE, recompile); // jne recompile
	362	emit_cmp_m32_imm(DRCTOP, MABS((UINT8 )code + 4), ((UINT32 )code)[1]); // cmp [pc+4],opcode+4
	363	emit_jcc(DRCTOP, COND_NE, recompile); // jne recompile
	364	emit_cmp_m32_imm(DRCTOP, MABS((UINT8 )code + 8), ((UINT32 )code)[2]); // cmp [pc+8],opcode+8
	365	emit_jcc(DRCTOP, COND_NE, recompile); // jne recompile
366	366	}
367	367	else if (length >= 8)
368	368	{
369		_cmp_m32abs_imm(code, (UINT32 )code); // cmp [pc],opcode
370		_jcc(COND_NE, recompile); // jne recompile
371		_cmp_m32abs_imm((UINT8 )code + 4, ((UINT32 )code)[1]); // cmp [pc+4],opcode+4
372		_jcc(COND_NE, recompile); // jne recompile
	369	emit_cmp_m32_imm(DRCTOP, MABS(code), (UINT32 )code); // cmp [pc],opcode
	370	emit_jcc(DRCTOP, COND_NE, recompile); // jne recompile
	371	emit_cmp_m32_imm(DRCTOP, MABS((UINT8 )code + 4), ((UINT32 )code)[1]); // cmp [pc+4],opcode+4
	372	emit_jcc(DRCTOP, COND_NE, recompile); // jne recompile
373	373	}
374	374	else if (length >= 4)
375	375	{
376		_cmp_m32abs_imm(code, (UINT32 )code); // cmp [pc],opcode
377		_jcc(COND_NE, recompile); // jne recompile
	376	emit_cmp_m32_imm(DRCTOP, MABS(code), (UINT32 )code); // cmp [pc],opcode
	377	emit_jcc(DRCTOP, COND_NE, recompile); // jne recompile
378	378	}
379	379	else if (length >= 2)
380	380	{
381		_cmp_m16abs_imm(code, (UINT16 )code); // cmp [pc],opcode
382		_jcc(COND_NE, recompile); // jne recompile
	381	emit_cmp_m16_imm(DRCTOP, MABS(code), (UINT16 )code); // cmp [pc],opcode
	382	emit_jcc(DRCTOP, COND_NE, recompile); // jne recompile
383	383	}
384	384	else
385	385	{
386		_cmp_m8abs_imm(code, (UINT8 )code); // cmp [pc],opcode
387		_jcc(COND_NE, recompile); // jne recompile
	386	emit_cmp_m8_imm(DRCTOP, MABS(code), (UINT8 )code); // cmp [pc],opcode
	387	emit_jcc(DRCTOP, COND_NE, recompile); // jne recompile
388	388	}
389	389	}
390	390
r949	r950
398	398	#ifdef MAME_DEBUG
399	399	if (Machine->debug_mode)
400	400	{
401		link_info link;
402		_cmp_m32abs_imm(&Machine->debug_mode, 0); // cmp [Machine->debug_mode],0
403		_jcc_short_link(COND_E, &link); // je skip
404		_sub_r32_imm(REG_ESP, 12); // align stack
405		drc_append_save_call_restore(drc, (genf *)mame_debug_hook, 12); // save volatiles
406		_resolve_link(&link);
	401	emit_link link;
	402	emit_cmp_m32_imm(DRCTOP, MABS(&Machine->debug_mode), 0); // cmp [Machine->debug_mode],0
	403	emit_jcc_short_link(DRCTOP, COND_E, &link); // je skip
	404	emit_sub_r32_imm(DRCTOP, REG_ESP, 12); // align stack
	405	drc_append_save_call_restore(drc, (x86code *)mame_debug_hook, 12); // save volatiles
	406	resolve_link(DRCTOP, &link);
407	407	}
408	408	#endif
409	409	}
r949	r950
416	416	void drc_append_save_volatiles(drc_core *drc)
417	417	{
418	418	if (drc->icountptr && !drc->icount_in_memory)
419		_mov_m32~~abs~~_r32(drc->icountptr, REG_EBP);
	419	emit_mov_m32_r32(DRCTOP, MABS(drc->icountptr), REG_EBP);
420	420	if (drc->pcptr && !drc->pc_in_memory)
421		_mov_m32~~abs~~_r32(drc->pcptr, REG_EDI);
	421	emit_mov_m32_r32(DRCTOP, MABS(drc->pcptr), REG_EDI);
422	422	if (drc->esiptr)
423		_mov_m32~~abs~~_r32(drc->esiptr, REG_ESI);
	423	emit_mov_m32_r32(DRCTOP, MABS(drc->esiptr), REG_ESI);
424	424	}
425	425
426	426
r949	r950
431	431	void drc_append_restore_volatiles(drc_core *drc)
432	432	{
433	433	if (drc->icountptr && !drc->icount_in_memory)
434		_mov_r32_m32~~abs~~(REG_EBP, drc->icountptr);
	434	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(drc->icountptr));
435	435	if (drc->pcptr && !drc->pc_in_memory)
436		_mov_r32_m32~~abs~~(REG_EDI, drc->pcptr);
	436	emit_mov_r32_m32(DRCTOP, REG_EDI, MABS(drc->pcptr));
437	437	if (drc->esiptr)
438		_mov_r32_m32~~abs~~(REG_ESI, drc->esiptr);
	438	emit_mov_r32_m32(DRCTOP, REG_ESI, MABS(drc->esiptr));
439	439	}
440	440
441	441
r949	r950
443	443	drc_append_save_call_restore
444	444	------------------------------------------------------------------*/
445	445
446		void drc_append_save_call_restore(drc_core drc, genf target, UINT32 stackadj)
	446	void drc_append_save_call_restore(drc_core drc, x86code target, UINT32 stackadj)
447	447	{
448		drc_append_save_volatiles(drc); // save volatiles
449		_call(target); // call target
450		drc_append_restore_volatiles(drc); // restore volatiles
	448	drc_append_save_volatiles(drc); // save volatiles
	449	emit_call(DRCTOP, target); // call target
	450	drc_append_restore_volatiles(drc); // restore volatiles
451	451	if (stackadj)
452		_add_r32_imm(REG_ESP, stackadj); // adjust stack
	452	emit_add_r32_imm(DRCTOP, REG_ESP, stackadj); // adjust stack
453	453	}
454	454
455	455
r949	r950
460	460	void drc_append_standard_epilogue(drc_core *drc, INT32 cycles, INT32 pcdelta, int allow_exit)
461	461	{
462	462	if (pcdelta != 0 && drc->pc_in_memory)
463		_add_m32~~abs~~_imm(drc->pcptr, pcdelta); // add [pc],pcdelta
	463	emit_add_m32_imm(DRCTOP, MABS(drc->pcptr), pcdelta); // add [pc],pcdelta
464	464	if (cycles != 0)
465	465	{
466	466	if (drc->icount_in_memory)
467		_sub_m32~~abs~~_imm(drc->icountptr, cycles); // sub [icount],cycles
	467	emit_sub_m32_imm(DRCTOP, MABS(drc->icountptr), cycles); // sub [icount],cycles
468	468	else
469		_sub_or~~_dec_r~~32_imm(REG_EBP, cycles); // sub ebp,cycles
	469	emit_sub_r32_imm(DRCTOP, REG_EBP, cycles); // sub ebp,cycles
470	470	}
471	471	if (pcdelta != 0 && !drc->pc_in_memory)
472		_lea_r32_m32bd(REG_EDI, REG_EDI, pcdelta); // lea edi,[edi+pcdelta]
	472	emit_lea_r32_m32(DRCTOP, REG_EDI, MBD(REG_EDI, pcdelta)); // lea edi,[edi+pcdelta]
473	473	if (allow_exit && cycles != 0)
474		_jcc(COND_S, drc->out_of_cycles); // js out_of_cycles
	474	emit_jcc(DRCTOP, COND_S, drc->out_of_cycles); // js out_of_cycles
475	475	}
476	476
477	477
r949	r950
482	482	void drc_append_dispatcher(drc_core *drc)
483	483	{
484	484	#if LOG_DISPATCHES
485		_sub_r32_imm(REG_ESP, 8); // align stack
486		_push_imm(drc); // push drc
487		drc_append_save_call_restore(drc, (void *)log_dispatch, 12); // call log_dispatch
	485	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // align stack
	486	emit_push_imm(DRCTOP, drc); // push drc
	487	drc_append_save_call_restore(drc, (x86code *)log_dispatch, 12); // call log_dispatch
488	488	#endif
489	489	if (drc->pc_in_memory)
490		_mov_r32_m32abs(REG_EDI, drc->pcptr); // mov edi,[pc]
491		_mov_r32_r32(REG_EAX, REG_EDI); // mov eax,edi
492		_shr_r32_imm(REG_EAX, drc->l1shift); // shr eax,l1shift
493		_mov_r32_r32(REG_EDX, REG_EDI); // mov edx,edi
494		_mov_r32_m32isd(REG_EAX, REG_EAX, 4, drc->lookup_l1); // mov eax,[eax*4 + l1lookup]
495		_and_r32_imm(REG_EDX, drc->l2mask); // and edx,l2mask
496		_jmp_m32bisd(REG_EAX, REG_EDX, drc->l2scale, 0); // jmp [eax+edx*l2scale]
	490	emit_mov_r32_m32(DRCTOP, REG_EDI, MABS(drc->pcptr)); // mov edi,[pc]
	491	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_EDI); // mov eax,edi
	492	emit_shr_r32_imm(DRCTOP, REG_EAX, drc->l1shift); // shr eax,l1shift
	493	emit_mov_r32_r32(DRCTOP, REG_EDX, REG_EDI); // mov edx,edi
	494	emit_mov_r32_m32(DRCTOP, REG_EAX, MISD(REG_EAX, 4, (FPTR)drc->lookup_l1)); // mov eax,[eax*4 + l1lookup]
	495	emit_and_r32_imm(DRCTOP, REG_EDX, drc->l2mask); // and edx,l2mask
	496	emit_jmp_m32(DRCTOP, MBISD(REG_EAX, REG_EDX, drc->l2scale, 0)); // jmp [eax+edx*l2scale]
497	497	}
498	498
499	499
r949	r950
503	503
504	504	void drc_append_fixed_dispatcher(drc_core *drc, UINT32 newpc)
505	505	{
506		void **base = drc->lookup_l1[newpc >> drc->l1shift];
	506	x86code **base = drc->lookup_l1[newpc >> drc->l1shift];
507	507	if (base == drc->lookup_l2_recompile)
508	508	{
509		_mov_r32_m32abs(REG_EAX, &drc->lookup_l1[newpc >> drc->l1shift]);// mov eax,[(newpc >> l1shift)*4 + l1lookup]
510		_jmp_m32bd(REG_EAX, (newpc & drc->l2mask) * drc->l2scale); // jmp [eax+(newpc & l2mask)*l2scale]
	509	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&drc->lookup_l1[newpc >> drc->l1shift]));
	510	// mov eax,[(newpc >> l1shift)*4 + l1lookup]
	511	emit_jmp_m32(DRCTOP, MBD(REG_EAX, (newpc & drc->l2mask) * drc->l2scale));
	512	// jmp [eax+(newpc & l2mask)*l2scale]
511	513	}
512	514	else
513		_jmp_m32abs((UINT8 )base + (newpc & drc->l2mask) drc->l2scale); // jmp [eax+(newpc & l2mask)*l2scale]
	515	emit_jmp_m32(DRCTOP, MABS((UINT8 )base + (newpc & drc->l2mask) drc->l2scale));
	516	// jmp [eax+(newpc & l2mask)*l2scale]
514	517	}
515	518
516	519
r949	r950
535	538
536	539	void drc_append_set_fp_rounding(drc_core *drc, UINT8 regindex)
537	540	{
538		_fldcw_m16isd(regindex, 2, &fp_control[0]); // fldcw [fp_control + reg*2]
539		_fnstcw_m16abs(&drc->fpcw_curr); // fnstcw [fpcw_curr]
	541	emit_fldcw_m16(DRCTOP, MISD(regindex, 2, (INT32)&fp_control[0])); // fldcw [fp_control + reg*2]
	542	emit_fstcw_m16(DRCTOP, MABS(&drc->fpcw_curr)); // fnstcw [fpcw_curr]
540	543	}
541	544
542	545
r949	r950
547	550
548	551	void drc_append_set_temp_fp_rounding(drc_core *drc, UINT8 rounding)
549	552	{
550		_fldcw_m16~~abs~~(&fp_control[rounding]); // fldcw [fp_control]
	553	emit_fldcw_m16(DRCTOP, MABS(&fp_control[rounding])); // fldcw [fp_control]
551	554	}
552	555
553	556
r949	r950
558	561
559	562	void drc_append_restore_fp_rounding(drc_core *drc)
560	563	{
561		_fldcw_m16~~abs~~(&drc->fpcw_curr); // fldcw [fpcw_curr]
	564	emit_fldcw_m16(DRCTOP, MABS(&drc->fpcw_curr)); // fldcw [fpcw_curr]
562	565	}
563	566
564	567
r949	r950
569	572
570	573	void drc_append_set_sse_rounding(drc_core *drc, UINT8 regindex)
571	574	{
572		_ldmxcsr_m32isd(regindex, 4, &sse_control[0]); // ldmxcsr [sse_control + reg*2]
573		_stmxcsr_m32abs(&drc->mxcsr_curr); // stmxcsr [mxcsr_curr]
	575	emit_ldmxcsr_m32(DRCTOP, MISD(regindex, 4, (INT32)&sse_control[0])); // ldmxcsr [sse_control + reg*2]
	576	emit_stmxcsr_m32(DRCTOP, MABS(&drc->mxcsr_curr)); // stmxcsr [mxcsr_curr]
574	577	}
575	578
576	579
r949	r950
581	584
582	585	void drc_append_set_temp_sse_rounding(drc_core *drc, UINT8 rounding)
583	586	{
584		_ldmxcsr_m32~~abs~~(&sse_control[rounding]); // ldmxcsr [sse_control]
	587	emit_ldmxcsr_m32(DRCTOP, MABS(&sse_control[rounding])); // ldmxcsr [sse_control]
585	588	}
586	589
587	590
r949	r950
592	595
593	596	void drc_append_restore_sse_rounding(drc_core *drc)
594	597	{
595		_ldmxcsr_m32~~abs~~(&drc->mxcsr_curr); // ldmxcsr [mxcsr_curr]
	598	emit_ldmxcsr_m32(DRCTOP, MABS(&drc->mxcsr_curr)); // ldmxcsr [mxcsr_curr]
596	599	}
597	600
598	601
r949	r950
642	645
643	646	static void append_entry_point(drc_core *drc)
644	647	{
645		_pushad(); // pushad
	648	emit_pushad(DRCTOP); // pushad
646	649	if (drc->uses_fp)
647	650	{
648		_fnstcw_m16abs(&drc->fpcw_save); // fstcw [fpcw_save]
649		_fldcw_m16abs(&drc->fpcw_curr); // fldcw [fpcw_curr]
	651	emit_fstcw_m16(DRCTOP, MABS(&drc->fpcw_save)); // fstcw [fpcw_save]
	652	emit_fldcw_m16(DRCTOP, MABS(&drc->fpcw_curr)); // fldcw [fpcw_curr]
650	653	}
651	654	if (drc->uses_sse)
652	655	{
653		_stmxcsr_m32abs(&drc->mxcsr_save); // stmxcsr [mxcsr_save]
654		_ldmxcsr_m32abs(&drc->mxcsr_curr); // ldmxcsr [mxcsr_curr]
	656	emit_stmxcsr_m32(DRCTOP, MABS(&drc->mxcsr_save)); // stmxcsr [mxcsr_save]
	657	emit_ldmxcsr_m32(DRCTOP, MABS(&drc->mxcsr_curr)); // ldmxcsr [mxcsr_curr]
655	658	}
656		drc_append_restore_volatiles(drc); // load volatiles
	659	drc_append_restore_volatiles(drc); // load volatiles
657	660	if (drc->cb_entrygen)
658		(*drc->cb_entrygen)(drc); // additional entry point duties
659		drc_append_dispatcher(drc); // dispatch
	661	(*drc->cb_entrygen)(drc); // additional entry point duties
	662	drc_append_dispatcher(drc); // dispatch
660	663	}
661	664
662	665
r949	r950
678	681
679	682	static void append_recompile(drc_core *drc)
680	683	{
681		_sub_r32_imm(REG_ESP, 8); // align stack
682		_push_imm(drc); // push drc
683		drc_append_save_call_restore(drc, (genf *)recompile_code, 12); // call recompile_code
684		drc_append_dispatcher(drc); // dispatch
	684	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // align stack
	685	emit_push_imm(DRCTOP, (FPTR)drc); // push drc
	686	drc_append_save_call_restore(drc, (x86code *)recompile_code, 12); // call recompile_code
	687	drc_append_dispatcher(drc); // dispatch
685	688	}
686	689
687	690
r949	r950
691	694
692	695	static void append_flush(drc_core *drc)
693	696	{
694		_sub_r32_imm(REG_ESP, 8); // align stack
695		_push_imm(drc); // push drc
696		drc_append_save_call_restore(drc, (genf *)drc_cache_reset, 12); // call drc_cache_reset
697		drc_append_dispatcher(drc); // dispatch
	697	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // align stack
	698	emit_push_imm(DRCTOP, (FPTR)drc); // push drc
	699	drc_append_save_call_restore(drc, (x86code *)drc_cache_reset, 12); // call drc_cache_reset
	700	drc_append_dispatcher(drc); // dispatch
698	701	}
699	702
700	703
r949	r950
704	707
705	708	static void append_out_of_cycles(drc_core *drc)
706	709	{
707		drc_append_save_volatiles(drc); // save volatiles
	710	drc_append_save_volatiles(drc); // save volatiles
708	711	if (drc->uses_fp)
709	712	{
710		_fnclex(); // fnclex
711		_fldcw_m16abs(&drc->fpcw_save); // fldcw [fpcw_save]
	713	emit_fclex(DRCTOP); // fnclex
	714	emit_fldcw_m16(DRCTOP, MABS(&drc->fpcw_save)); // fldcw [fpcw_save]
712	715	}
713	716	if (drc->uses_sse)
714		_ldmxcsr_m32abs(&drc->mxcsr_save); // ldmxcsr [mxcsr_save]
715		_popad(); // popad
716		_ret(); // ret
	717	emit_ldmxcsr_m32(DRCTOP, MABS(&drc->mxcsr_save)); // ldmxcsr [mxcsr_save]
	718	emit_popad(DRCTOP); // popad
	719	emit_ret(DRCTOP); // ret
717	720	}
718	721
719	722
r949	r950
737	740	#else /* !_MSC_VER */
738	741	__asm__
739	742	(
740		"pushl %%ebx ; "
	743	"pushl %%ebx ; "
741	744	"movl $1,%%eax ; "
742	745	"xorl %%ebx,%%ebx ; "
743	746	"xorl %%ecx,%%ecx ; "
744	747	"xorl %%edx,%%edx ; "
745	748	"cpuid ; "
746	749	"movl %%edx,%0 ; "
747		"popl %%ebx ; "
	750	"popl %%ebx ; "
748	751	: "=&a" (features) /* result has to go in eax */
749	752	: /* no inputs */
750	753	: "%ecx", "%edx" /* clobbers ebx, ecx and edx */

src/emu/cpu/x86drc.h
r949	r950
15	15	#define __X86DRC_H__
16	16
17	17	#include "cpuintrf.h"
	18	#include "x86emit.h"
18	19
19	20
20	21	/***************************************************************************
r949	r950
22	23	***************************************************************************/
23	24
24	25	/* PC and pointer pair */
	26	typedef struct _pc_ptr_pair pc_ptr_pair;
25	27	struct _pc_ptr_pair
26	28	{
27	29	UINT32 pc;
28		~~UINT~~8 * target;
	30	x86code * target;
29	31	};
30		typedef struct _pc_ptr_pair pc_ptr_pair;
31	32
	33
32	34	/* core interface structure for the drc common code */
	35	typedef struct _drc_core drc_core;
33	36	struct _drc_core
34	37	{
35	38	UINT8 * cache_base; /* base pointer to the compiler cache */
r949	r950
39	42	size_t cache_size; /* cache allocated size */
40	43	UINT8 cache_allocated; /* did the DRC core allocate the cache? */
41	44
42		void *** lookup_l1; /* level 1 lookup */
43		void ** lookup_l2_recompile; /* level 2 lookup populated with recompile pointers */
	45	x86code *** lookup_l1; /* level 1 lookup */
	46	x86code ** lookup_l2_recompile; /* level 2 lookup populated with recompile pointers */
44	47	UINT8 l1bits; /* number of bits in level 1 lookup */
45	48	UINT8 l2bits; /* number of bits in level 2 lookup */
46	49	UINT8 l1shift; /* shift to go from PC to level 1 lookup */
r949	r950
48	51	UINT8 l2scale; /* scale to get from masked PC value to final level 2 lookup */
49	52
50	53	void (entry_point)(void); / pointer to asm entry point */
51		void * out_of_cycles; /* pointer to out of cycles jump point */
52		void * recompile; /* pointer to recompile jump point */
53		void * dispatch; /* pointer to dispatch jump point */
54		void * flush; /* pointer to flush jump point */
	54	x86code * out_of_cycles; /* pointer to out of cycles jump point */
	55	x86code * recompile; /* pointer to recompile jump point */
	56	x86code * dispatch; /* pointer to dispatch jump point */
	57	x86code * flush; /* pointer to flush jump point */
55	58
56	59	UINT32 * pcptr; /* pointer to where the PC is stored */
57	60	UINT32 * icountptr; /* pointer to where the icount is stored */
r949	r950
77	80	void (cb_recompile)(struct _drc_core drc); /* callback when code needs to be recompiled */
78	81	void (cb_entrygen)(struct _drc_core drc); /* callback before generating the dispatcher on entry */
79	82	};
80		typedef struct _drc_core drc_core;
81	83
	84
82	85	/* configuration structure for the drc common code */
	86	typedef struct _drc_config drc_config;
83	87	struct _drc_config
84	88	{
85	89	UINT8 * cache_base; /* base pointer to the compiler cache */
r949	r950
100	104	void (cb_recompile)(drc_core drc); /* callback when code needs to be recompiled */
101	105	void (cb_entrygen)(drc_core drc); /* callback before generating the dispatcher on entry */
102	106	};
103		typedef struct _drc_config drc_config;
104	107
	108
105	109	/* structure to hold link data to be filled in later */
	110	typedef struct _link_info link_info;
106	111	struct _link_info
107	112	{
108	113	UINT8 size;
109	114	UINT8 * target;
110	115	};
111		typedef struct _link_info link_info;
112	116
113	117
114	118
115	119	/***************************************************************************
	120	MACROS
	121	***************************************************************************/
	122
	123	/* use this macro in emit_* instructions to make them shorter */
	124	#define DRCTOP &drc->cache_top
	125
	126
	127
	128	/***************************************************************************
116	129	HELPER MACROS
117	130	***************************************************************************/
118	131
r949	r950
120	133	#define LO(x) (&(((UINT32 *)(UINT32)(x))[0]))
121	134	#define HI(x) (&(((UINT32 *)(UINT32)(x))[1]))
122	135
123		extern const UINT8 scale_lookup[];
124	136
125	137
126	138	/***************************************************************************
127	139	CONSTANTS
128	140	***************************************************************************/
129	141
130		/* architectural defines */
131		#define REG_EAX 0
132		#define REG_ECX 1
133		#define REG_EDX 2
134		#define REG_EBX 3
135		#define REG_ESP 4
136		#define REG_EBP 5
137		#define REG_ESI 6
138		#define REG_EDI 7
139
140		#define REG_AX 0
141		#define REG_CX 1
142		#define REG_DX 2
143		#define REG_BX 3
144		#define REG_SP 4
145		#define REG_BP 5
146		#define REG_SI 6
147		#define REG_DI 7
148
149		#define REG_AL 0
150		#define REG_CL 1
151		#define REG_DL 2
152		#define REG_BL 3
153		#define REG_AH 4
154		#define REG_CH 5
155		#define REG_DH 6
156		#define REG_BH 7
157
158		#define REG_MM0 0
159		#define REG_MM1 1
160		#define REG_MM2 2
161		#define REG_MM3 3
162		#define REG_MM4 4
163		#define REG_MM5 5
164		#define REG_MM6 6
165		#define REG_MM7 7
166
167		#define REG_XMM0 0
168		#define REG_XMM1 1
169		#define REG_XMM2 2
170		#define REG_XMM3 3
171		#define REG_XMM4 4
172		#define REG_XMM5 5
173		#define REG_XMM6 6
174		#define REG_XMM7 7
175
176		#define NO_BASE 5
177
178		#define COND_A 7
179		#define COND_AE 3
180		#define COND_B 2
181		#define COND_BE 6
182		#define COND_C 2
183		#define COND_E 4
184		#define COND_Z 4
185		#define COND_G 15
186		#define COND_GE 13
187		#define COND_L 12
188		#define COND_LE 14
189		#define COND_NA 6
190		#define COND_NAE 2
191		#define COND_NB 3
192		#define COND_NBE 7
193		#define COND_NC 3
194		#define COND_NE 5
195		#define COND_NG 14
196		#define COND_NGE 12
197		#define COND_NL 13
198		#define COND_NLE 15
199		#define COND_NO 1
200		#define COND_NP 11
201		#define COND_NS 9
202		#define COND_NZ 5
203		#define COND_O 0
204		#define COND_P 10
205		#define COND_PE 10
206		#define COND_PO 11
207		#define COND_S 8
208		#define COND_Z 4
209
210		/* rounding modes */
211		#define FPRND_NEAR 0
212		#define FPRND_DOWN 1
213		#define FPRND_UP 2
214		#define FPRND_CHOP 3
215
216		/* register counts */
217		#define REGCOUNT_MMX 8
218		#define REGCOUNT_SSE 8
219
220	142	/* features */
221	143	#define CPUID_FEATURES_MMX (1 << 23)
222	144	#define CPUID_FEATURES_SSE (1 << 26)
r949	r950
227	149
228	150
229	151	/***************************************************************************
230		LOW-LEVEL OPCODE EMITTERS
231		***************************************************************************/
232
233		/* lowest-level opcode emitters */
234		#define OP1(x) do { *drc->cache_top++ = (UINT8)(x); } while (0)
235		#define OP2(x) do { (UINT16 )drc->cache_top = (UINT16)(x); drc->cache_top += 2; } while (0)
236		#define OP4(x) do { (UINT32 )drc->cache_top = (UINT32)(x); drc->cache_top += 4; } while (0)
237
238
239
240		/***************************************************************************
241		MODRM EMITTERS
242		***************************************************************************/
243
244		// op reg,reg
245		#define MODRM_REG(reg, rm) \
246		do { OP1(0xc0 \| (((reg) & 7) << 3) \| ((rm) & 7)); } while (0)
247
248		// op reg,[addr]
249		#define MODRM_MABS(reg, addr) \
250		do { OP1(0x05 \| (((reg) & 7) << 3)); OP4(addr); } while (0)
251
252		// op reg,[base+disp]
253		#define MODRM_MBD(reg, base, disp) \
254		do { \
255		if ((UINT32)(disp) == 0 && (base) != REG_ESP && (base) != REG_EBP) \
256		{ \
257		OP1(0x00 \| (((reg) & 7) << 3) \| ((base) & 7)); \
258		} \
259		else if ((INT8)(INT32)(disp) == (INT32)(disp)) \
260		{ \
261		if ((base) == REG_ESP) \
262		{ \
263		OP1(0x44 \| (((reg) & 7) << 3)); \
264		OP1(0x24); \
265		OP1((INT32)disp); \
266		} \
267		else \
268		{ \
269		OP1(0x40 \| (((reg) & 7) << 3) \| ((base) & 7)); \
270		OP1((INT32)disp); \
271		} \
272		} \
273		else \
274		{ \
275		if ((base) == REG_ESP) \
276		{ \
277		OP1(0x84 \| (((reg) & 7) << 3)); \
278		OP1(0x24); \
279		OP4(disp); \
280		} \
281		else \
282		{ \
283		OP1(0x80 \| (((reg) & 7) << 3) \| ((base) & 7)); \
284		OP4(disp); \
285		} \
286		} \
287		} while (0)
288
289		// op reg,[base+indx*scale+disp]
290		#define MODRM_MBISD(reg, base, indx, scale, disp) \
291		do { \
292		if ((scale) == 1 && (base) == NO_BASE) \
293		MODRM_MBD(reg,indx,disp); \
294		else if ((UINT32)(disp) == 0 \|\| (base) == NO_BASE) \
295		{ \
296		OP1(0x04 \| (((reg) & 7) << 3)); \
297		OP1((scale_lookup[scale] << 6) \| (((indx) & 7) << 3) \| ((base) & 7));\
298		if ((UINT32)(disp) != 0 \|\| (base) == NO_BASE) OP4(disp);\
299		} \
300		else if ((INT8)(INT32)(disp) == (INT32)(disp)) \
301		{ \
302		OP1(0x44 \| (((reg) & 7) << 3)); \
303		OP1((scale_lookup[scale] << 6) \| (((indx) & 7) << 3) \| ((base) & 7));\
304		OP1((INT32)disp); \
305		} \
306		else \
307		{ \
308		OP1(0x84 \| (((reg) & 7) << 3)); \
309		OP1((scale_lookup[scale] << 6) \| (((indx) & 7) << 3) \| ((base) & 7));\
310		OP4(disp); \
311		} \
312		} while (0)
313
314
315
316		/***************************************************************************
317		SIMPLE OPCODE EMITTERS
318		***************************************************************************/
319
320		#define _pushad() \
321		do { OP1(0x60); } while (0)
322
323		#define _push_r32(reg) \
324		do { OP1(0x50+(reg)); } while (0)
325
326		#define _push_imm(imm) \
327		do { OP1(0x68); OP4(imm); } while (0)
328
329		#define _push_m32abs(addr) \
330		do { OP1(0xff); MODRM_MABS(6, addr); } while (0)
331
332		#define _push_m32bd(base, disp) \
333		do { OP1(0xff); MODRM_MBD(6, base, disp); } while (0)
334
335		#define _popad() \
336		do { OP1(0x61); } while (0)
337
338		#define _pop_r32(reg) \
339		do { OP1(0x58+(reg)); } while (0)
340
341		#define _pop_m32abs(addr) \
342		do { OP1(0x8f); MODRM_MABS(0, addr); } while (0)
343
344		#define _ret() \
345		do { OP1(0xc3); } while (0)
346
347		#define _cdq() \
348		do { OP1(0x99); } while (0)
349
350		#define _lahf() \
351		do { OP1(0x9F); } while(0);
352
353		#define _sahf() \
354		do { OP1(0x9E); } while(0);
355
356		#define _pushfd() \
357		do { OP1(0x9c); } while(0);
358
359		#define _popfd() \
360		do { OP1(0x9d); } while(0);
361
362		#define _bswap_r32(reg) \
363		do { OP1(0x0F); OP1(0xC8+(reg)); } while (0)
364
365		#define _cmc() \
366		do { OP1(0xf5); } while(0);
367
368		#define _int(interrupt) \
369		do { if (interrupt == 3) { OP1(0xcc); } else { OP1(0xcd); OP1(interrupt); } } while(0)
370
371
372
373		/***************************************************************************
374		MOVE EMITTERS
375		***************************************************************************/
376
377		#define _mov_r8_imm(dreg, imm) \
378		do { OP1(0xb0 + (dreg)); OP1(imm); } while (0)
379
380		#define _mov_r8_r8(dreg, sreg) \
381		do { OP1(0x8a); MODRM_REG(dreg, sreg); } while (0)
382
383		#define _mov_r8_m8abs(dreg, addr) \
384		do { OP1(0x8a); MODRM_MABS(dreg, addr); } while (0)
385
386		#define _mov_r8_m8bd(dreg, base, disp) \
387		do { OP1(0x8a); MODRM_MBD(dreg, base, disp); } while (0)
388
389		#define _mov_r8_m8isd(dreg, indx, scale, disp) \
390		do { OP1(0x8a); MODRM_MBISD(dreg, NO_BASE, indx, scale, disp); } while (0)
391
392		#define _mov_r8_m8bisd(dreg, base, indx, scale, disp) \
393		do { OP1(0x8a); MODRM_MBISD(dreg, base, indx, scale, disp); } while (0)
394
395
396
397		#define _mov_r16_imm(dreg, imm) \
398		do { OP1(0x66); OP1(0xb8 + (dreg)); OP2(imm); } while (0)
399
400		#define _mov_r16_r16(dreg, sreg) \
401		do { OP1(0x66); OP1(0x8b); MODRM_REG(dreg, sreg); } while (0)
402
403		#define _mov_r16_m16abs(dreg, addr) \
404		do { OP1(0x66); OP1(0x8b); MODRM_MABS(dreg, addr); } while (0)
405
406		#define _mov_r16_m16bd(dreg, base, disp) \
407		do { OP1(0x66); OP1(0x8b); MODRM_MBD(dreg, base, disp); } while (0)
408
409		#define _mov_r16_m16isd(dreg, indx, scale, disp) \
410		do { OP1(0x66); OP1(0x8b); MODRM_MBISD(dreg, NO_BASE, indx, scale, disp); } while (0)
411
412		#define _mov_r16_m16bisd(dreg, base, indx, scale, disp) \
413		do { OP1(0x66); OP1(0x8b); MODRM_MBISD(dreg, base, indx, scale, disp); } while (0)
414
415
416
417		#define _mov_r32_imm(dreg, imm) \
418		do { OP1(0xb8 + (dreg)); OP4(imm); } while (0)
419
420		#define _mov_r32_r32(dreg, sreg) \
421		do { OP1(0x8b); MODRM_REG(dreg, sreg); } while (0)
422
423		#define _mov_r32_m32abs(dreg, addr) \
424		do { OP1(0x8b); MODRM_MABS(dreg, addr); } while (0)
425
426		#define _mov_r32_m32bd(dreg, base, disp) \
427		do { OP1(0x8b); MODRM_MBD(dreg, base, disp); } while (0)
428
429		#define _mov_r32_m32isd(dreg, indx, scale, disp) \
430		do { OP1(0x8b); MODRM_MBISD(dreg, NO_BASE, indx, scale, disp); } while (0)
431
432		#define _mov_r32_m32bisd(dreg, base, indx, scale, disp) \
433		do { OP1(0x8b); MODRM_MBISD(dreg, base, indx, scale, disp); } while (0)
434
435
436
437		#define _cmov_r32_r32(cond, dreg, sreg) \
438		do { OP1(0x0f); OP1(0x40 + (cond)); MODRM_REG(dreg, sreg); } while (0)
439
440		#define _cmov_r32_m32abs(cond, dreg, addr) \
441		do { OP1(0x0f); OP1(0x40 + (cond)); MODRM_MABS(dreg, addr); } while (0)
442
443		#define _cmov_r32_m32bd(cond, dreg, base, disp) \
444		do { OP1(0x0f); OP1(0x40 + (cond)); MODRM_MBD(dreg, base, disp); } while (0)
445
446		#define _cmov_r32_m32isd(cond, dreg, indx, scale, disp) \
447		do { OP1(0x0f); OP1(0x40 + (cond)); MODRM_MBISD(dreg, NO_BASE, indx, scale, disp); } while (0)
448
449		#define _cmov_r32_m32bisd(cond, dreg, base, indx, scale, disp) \
450		do { OP1(0x0f); OP1(0x40 + (cond)); MODRM_MBISD(dreg, base, indx, scale, disp); } while (0)
451
452
453
454		#define _mov_m8abs_imm(addr, imm) \
455		do { OP1(0xc6); MODRM_MABS(0, addr); OP1(imm); } while (0)
456
457		#define _mov_m8abs_r8(addr, sreg) \
458		do { OP1(0x88); MODRM_MABS(sreg, addr); } while (0)
459
460		#define _mov_m8bd_r8(base, disp, sreg) \
461		do { OP1(0x88); MODRM_MBD(sreg, base, disp); } while (0)
462
463		#define _mov_m8isd_r8(indx, scale, disp, sreg) \
464		do { OP1(0x88); MODRM_MBISD(sreg, NO_BASE, indx, scale, disp); } while (0)
465
466		#define _mov_m8bisd_r8(base, indx, scale, disp, sreg) \
467		do { OP1(0x88); MODRM_MBISD(sreg, base, indx, scale, disp); } while (0)
468
469
470
471		#define _mov_m16abs_imm(addr, imm) \
472		do { OP1(0x66); OP1(0xc7); MODRM_MABS(0, addr); OP2(imm); } while (0)
473
474		#define _mov_m16abs_r16(addr, sreg) \
475		do { OP1(0x66); OP1(0x89); MODRM_MABS(sreg, addr); } while (0)
476
477		#define _mov_m16bd_r16(base, disp, sreg) \
478		do { OP1(0x66); OP1(0x89); MODRM_MBD(sreg, base, disp); } while (0)
479
480		#define _mov_m16bisd_r16(base, indx, scale, disp, sreg) \
481		do { OP1(0x66); OP1(0x89); MODRM_MBISD(sreg, base, indx, scale, disp); } while (0)
482
483
484
485
486		#define _mov_m32abs_imm(addr, imm) \
487		do { OP1(0xc7); MODRM_MABS(0, addr); OP4(imm); } while (0)
488
489		#define _mov_m32bd_imm(base, disp, imm) \
490		do { OP1(0xc7); MODRM_MBD(0, base, disp); OP4(imm); } while (0)
491
492		#define _mov_m32bisd_imm(base, indx, scale, addr, imm) \
493		do { OP1(0xc7); MODRM_MBISD(0, base, indx, scale, addr); OP4(imm); } while (0)
494
495
496
497		#define _mov_m32abs_r32(addr, sreg) \
498		do { OP1(0x89); MODRM_MABS(sreg, addr); } while (0)
499
500		#define _mov_m32bd_r32(base, disp, sreg) \
501		do { OP1(0x89); MODRM_MBD(sreg, base, disp); } while (0)
502
503		#define _mov_m32isd_r32(indx, scale, addr, dreg) \
504		do { OP1(0x89); MODRM_MBISD(dreg, NO_BASE, indx, scale, addr); } while (0)
505
506		#define _mov_m32bisd_r32(base, indx, scale, addr, dreg) \
507		do { OP1(0x89); MODRM_MBISD(dreg, base, indx, scale, addr); } while (0)
508
509
510
511		#define _mov_r64_m64abs(reghi, reglo, addr) \
512		do { _mov_r32_m32abs(reglo, LO(addr)); _mov_r32_m32abs(reghi, HI(addr)); } while (0)
513
514		#define _mov_m64abs_r64(addr, reghi, reglo) \
515		do { _mov_m32abs_r32(LO(addr), reglo); _mov_m32abs_r32(HI(addr), reghi); } while (0)
516
517		#define _mov_m64abs_imm32(addr, imm) \
518		do { _mov_m32abs_imm(LO(addr), imm); _mov_m32abs_imm(HI(addr), ((INT32)(imm) >> 31)); } while (0)
519
520
521
522		#define _mov_r64_m64bd(reghi, reglo, base, disp) \
523		do { _mov_r32_m32bd(reglo, base, disp); _mov_r32_m32bd(reghi, base, (UINT8 *)(disp) + 4); } while (0)
524
525		#define _mov_m64bd_r64(base, disp, reghi, reglo) \
526		do { _mov_m32bd_r32(base, disp, reglo); _mov_m32bd_r32(base, (UINT8 *)(disp) + 4, reghi); } while (0)
527
528		#define _mov_m64bd_imm32(base, disp, imm) \
529		do { _mov_m32bd_imm(base, disp, imm); _mov_m32bd_imm(base, (UINT8 *)(disp) + 4, ((INT32)(imm) >> 31)); } while (0)
530
531
532
533		#define _movsx_r32_r8(dreg, sreg) \
534		do { OP1(0x0f); OP1(0xbe); MODRM_REG(dreg, sreg); } while (0)
535
536		#define _movsx_r32_r16(dreg, sreg) \
537		do { OP1(0x0f); OP1(0xbf); MODRM_REG(dreg, sreg); } while (0)
538
539		#define _movsx_r32_m8abs(dreg, addr) \
540		do { OP1(0x0f); OP1(0xbe); MODRM_MABS(dreg, addr); } while (0)
541
542		#define _movsx_r32_m16abs(dreg, addr) \
543		do { OP1(0x0f); OP1(0xbf); MODRM_MABS(dreg, addr); } while (0)
544
545		#define _movsx_r32_m8bd(dreg, base, disp) \
546		do { OP1(0x0f); OP1(0xbe); MODRM_MBD(dreg, base, disp); } while (0)
547
548		#define _movsx_r32_m16bd(dreg, base, disp) \
549		do { OP1(0x0f); OP1(0xbf); MODRM_MBD(dreg, base, disp); } while (0)
550
551		#define _movzx_r32_r8(dreg, sreg) \
552		do { OP1(0x0f); OP1(0xb6); MODRM_REG(dreg, sreg); } while (0)
553
554		#define _movzx_r32_r16(dreg, sreg) \
555		do { OP1(0x0f); OP1(0xb7); MODRM_REG(dreg, sreg); } while (0)
556
557		#define _movzx_r32_m8abs(dreg, addr) \
558		do { OP1(0x0f); OP1(0xb6); MODRM_MABS(dreg, addr); } while (0)
559
560		#define _movzx_r32_m16abs(dreg, addr) \
561		do { OP1(0x0f); OP1(0xb7); MODRM_MABS(dreg, addr); } while (0)
562
563		#define _movzx_r32_m8bd(dreg, base, disp) \
564		do { OP1(0x0f); OP1(0xb6); MODRM_MBD(dreg, base, disp); } while (0)
565
566		#define _movzx_r32_m16bd(dreg, base, disp) \
567		do { OP1(0x0f); OP1(0xb7); MODRM_MBD(dreg, base, disp); } while (0)
568
569		#define _movzx_r32_m8isd(dreg, indx, scale, disp) \
570		do { OP1(0x0f); OP1(0xb6); MODRM_MBISD(dreg, NO_BASE, indx, scale, disp); } while (0)
571
572		#define _movzx_r32_m16isd(dreg, indx, scale, disp) \
573		do { OP1(0x0f); OP1(0xb7); MODRM_MBISD(dreg, NO_BASE, indx, scale, disp); } while (0)
574
575		#define _movzx_r32_m8bisd(dreg, base, indx, scale, disp) \
576		do { OP1(0x0f); OP1(0xb6); MODRM_MBISD(dreg, base, indx, scale, disp); } while (0)
577
578		#define _movzx_r32_m16bisd(dreg, base, indx, scale, disp) \
579		do { OP1(0x0f); OP1(0xb7); MODRM_MBISD(dreg, base, indx, scale, disp); } while (0)
580
581
582
583		#define _lea_r32_m32bd(dest, base, disp) \
584		do { OP1(0x8d); MODRM_MBD(dest, base, disp); } while (0)
585
586		#define _lea_r32_m32isd(dest, indx, scale, disp) \
587		do { OP1(0x8d); MODRM_MBISD(dest, NO_BASE, indx, scale, disp); } while (0)
588
589		#define _lea_r32_m32bisd(dest, base, indx, scale, disp) \
590		do { OP1(0x8d); MODRM_MBISD(dest, base, indx, scale, disp); } while (0)
591
592
593
594		/***************************************************************************
595		32-BIT SHIFT EMITTERS
596		***************************************************************************/
597
598		#define _sar_r32_cl(dreg) \
599		do { OP1(0xd3); MODRM_REG(7, dreg); } while (0)
600
601		#define _shl_r32_cl(dreg) \
602		do { OP1(0xd3); MODRM_REG(4, dreg); } while (0)
603
604		#define _shr_r32_cl(dreg) \
605		do { OP1(0xd3); MODRM_REG(5, dreg); } while (0)
606
607		#define _sar_r32_imm(dreg, imm) \
608		do { \
609		if ((imm) == 1) { OP1(0xd1); MODRM_REG(7, dreg); } \
610		else { OP1(0xc1); MODRM_REG(7, dreg); OP1(imm); } \
611		} while (0)
612
613		#define _shl_r32_imm(dreg, imm) \
614		do { \
615		if ((imm) == 1) { OP1(0xd1); MODRM_REG(4, dreg); } \
616		else { OP1(0xc1); MODRM_REG(4, dreg); OP1(imm); } \
617		} while (0)
618
619		#define _shr_r32_imm(dreg, imm) \
620		do { \
621		if ((imm) == 1) { OP1(0xd1); MODRM_REG(5, dreg); } \
622		else { OP1(0xc1); MODRM_REG(5, dreg); OP1(imm); } \
623		} while (0)
624
625		#define _rol_r32_imm(dreg, imm) \
626		do { \
627		if ((imm) == 1) { OP1(0xd1); MODRM_REG(0, dreg); } \
628		else { OP1(0xc1); MODRM_REG(0, dreg); OP1(imm); } \
629		} while (0)
630
631		#define _ror_r32_imm(dreg, imm) \
632		do { \
633		if ((imm) == 1) { OP1(0xd1); MODRM_REG(1, dreg); } \
634		else { OP1(0xc1); MODRM_REG(1, dreg); OP1(imm); } \
635		} while (0)
636
637
638
639		#define _rol_m32abs_imm(addr, imm) \
640		do { \
641		if ((imm) == 1) { OP1(0xd1); MODRM_MABS(0, addr); } \
642		else { OP1(0xc1); MODRM_MABS(0, addr); OP1(imm); } \
643		} while (0)
644
645
646
647		#define _shld_r32_r32_cl(dreg, sreg) \
648		do { OP1(0x0f); OP1(0xa5); MODRM_REG(sreg, dreg); } while (0)
649
650		#define _shld_r32_r32_imm(dreg, sreg, imm) \
651		do { OP1(0x0f); OP1(0xa4); MODRM_REG(sreg, dreg); OP1(imm); } while (0)
652
653		#define _shrd_r32_r32_cl(dreg, sreg) \
654		do { OP1(0x0f); OP1(0xad); MODRM_REG(sreg, dreg); } while (0)
655
656		#define _shrd_r32_r32_imm(dreg, sreg, imm) \
657		do { OP1(0x0f); OP1(0xac); MODRM_REG(sreg, dreg); OP1(imm); } while (0)
658
659
660
661		#define _bt_m32bd_r32(base, disp, reg) \
662		do { OP1(0x0f); OP1(0xa3); MODRM_MBD(reg, base, disp); } while (0)
663
664		#define _bt_m32abs_imm(addr, imm) \
665		do { OP1(0x0f); OP1(0xba); MODRM_MABS(4, addr); OP1(imm); } while (0)
666
667		#define _bt_r32_imm(reg, imm) \
668		do { OP1(0x0f); OP1(0xba); MODRM_REG(4, reg); OP1(imm); } while (0)
669
670		#define _bsr_r32_r32(dreg, sreg) \
671		do { OP1(0x0f); OP1(0xbd); MODRM_REG(dreg, sreg); } while (0)
672
673
674
675
676		/***************************************************************************
677		16-BIT SHIFT EMITTERS
678		***************************************************************************/
679
680		#define _sar_r16_cl(dreg) \
681		do { OP1(0x66); OP1(0xd3); MODRM_REG(7, dreg); } while (0)
682
683		#define _shl_r16_cl(dreg) \
684		do { OP1(0x66); OP1(0xd3); MODRM_REG(4, dreg); } while (0)
685
686		#define _shr_r16_cl(dreg) \
687		do { OP1(0x66); OP1(0xd3); MODRM_REG(5, dreg); } while (0)
688
689		#define _sar_r16_imm(dreg, imm) \
690		do { \
691		if ((imm) == 1) { OP1(0x66); OP1(0xd1); MODRM_REG(7, dreg); } \
692		else { OP1(0x66); OP1(0xc1); MODRM_REG(7, dreg); OP1(imm); } \
693		} while (0)
694
695		#define _shl_r16_imm(dreg, imm) \
696		do { \
697		if ((imm) == 1) { OP1(0x66); OP1(0xd1); MODRM_REG(4, dreg); } \
698		else { OP1(0x66); OP1(0xc1); MODRM_REG(4, dreg); OP1(imm); } \
699		} while (0)
700
701		#define _shr_r16_imm(dreg, imm) \
702		do { \
703		if ((imm) == 1) { OP1(0x66); OP1(0xd1); MODRM_REG(5, dreg); } \
704		else { OP1(0x66); OP1(0xc1); MODRM_REG(5, dreg); OP1(imm); } \
705		} while (0)
706
707		#define _rol_r16_imm(dreg, imm) \
708		do { \
709		if ((imm) == 1) { OP1(0x66); OP1(0xd1); MODRM_REG(0, dreg); } \
710		else { OP1(0x66); OP1(0xc1); MODRM_REG(0, dreg); OP1(imm); } \
711		} while (0)
712
713		#define _ror_r16_imm(dreg, imm) \
714		do { \
715		if ((imm) == 1) { OP1(0x66); OP1(0xd1); MODRM_REG(1, dreg); } \
716		else { OP1(0x66); OP1(0xc1); MODRM_REG(1, dreg); OP1(imm); } \
717		} while (0)
718
719
720
721		/***************************************************************************
722		UNARY ARITHMETIC EMITTERS
723		***************************************************************************/
724
725		#define _neg_r32(reg) \
726		do { OP1(0xf7); MODRM_REG(3, reg); } while (0)
727
728		#define _not_r32(reg) \
729		do { OP1(0xf7); MODRM_REG(2, reg); } while (0)
730
731
732
733		/***************************************************************************
734		32-BIT ARITHMETIC EMITTERS
735		***************************************************************************/
736
737		#define _add_r32_r32(r1, r2) \
738		do { OP1(0x01); MODRM_REG(r2, r1); } while (0)
739
740		#define _adc_r32_r32(r1, r2) \
741		do { OP1(0x11); MODRM_REG(r2, r1); } while (0)
742
743		#define _or_r32_r32(r1, r2) \
744		do { OP1(0x09); MODRM_REG(r2, r1); } while (0)
745
746		#define _sub_r32_r32(r1, r2) \
747		do { OP1(0x29); MODRM_REG(r2, r1); } while (0)
748
749		#define _sbb_r32_r32(r1, r2) \
750		do { OP1(0x19); MODRM_REG(r2, r1); } while (0)
751
752		#define _xor_r32_r32(r1, r2) \
753		do { OP1(0x31); MODRM_REG(r2, r1); } while (0)
754
755		#define _cmp_r32_r32(r1, r2) \
756		do { OP1(0x39); MODRM_REG(r2, r1); } while (0)
757
758		#define _test_r32_r32(r1, r2) \
759		do { OP1(0x85); MODRM_REG(r2, r1); } while (0)
760
761
762
763		#define _add_r32_m32abs(dreg, addr) \
764		do { OP1(0x03); MODRM_MABS(dreg, addr); } while (0)
765
766		#define _adc_r32_m32abs(dreg, addr) \
767		do { OP1(0x13); MODRM_MABS(dreg, addr); } while (0)
768
769		#define _and_r32_m32abs(dreg, addr) \
770		do { OP1(0x23); MODRM_MABS(dreg, addr); } while (0)
771
772		#define _cmp_r32_m32abs(dreg, addr) \
773		do { OP1(0x3b); MODRM_MABS(dreg, addr); } while (0)
774
775		#define _or_r32_m32abs(dreg, addr) \
776		do { OP1(0x0b); MODRM_MABS(dreg, addr); } while (0)
777
778		#define _sub_r32_m32abs(dreg, addr) \
779		do { OP1(0x2b); MODRM_MABS(dreg, addr); } while (0)
780
781		#define _sbb_r32_m32abs(dreg, addr) \
782		do { OP1(0x1b); MODRM_MABS(dreg, addr); } while (0)
783
784		#define _xor_r32_m32abs(dreg, addr) \
785		do { OP1(0x33); MODRM_MABS(dreg, addr); } while (0)
786
787
788
789		#define _add_r32_m32bd(dreg, base, disp) \
790		do { OP1(0x03); MODRM_MBD(dreg, base, disp); } while (0)
791
792		#define _adc_r32_m32bd(dreg, base, disp) \
793		do { OP1(0x13); MODRM_MBD(dreg, base, disp); } while (0)
794
795		#define _and_r32_m32bd(dreg, base, disp) \
796		do { OP1(0x23); MODRM_MBD(dreg, base, disp); } while (0)
797
798		#define _cmp_r32_m32bd(dreg, base, disp) \
799		do { OP1(0x3b); MODRM_MBD(dreg, base, disp); } while (0)
800
801		#define _or_r32_m32bd(dreg, base, disp) \
802		do { OP1(0x0b); MODRM_MBD(dreg, base, disp); } while (0)
803
804		#define _sub_r32_m32bd(dreg, base, disp) \
805		do { OP1(0x2b); MODRM_MBD(dreg, base, disp); } while (0)
806
807		#define _sbb_r32_m32bd(dreg, base, disp) \
808		do { OP1(0x1b); MODRM_MBD(dreg, base, disp); } while (0)
809
810		#define _xor_r32_m32bd(dreg, base, disp) \
811		do { OP1(0x33); MODRM_MBD(dreg, base, disp); } while (0)
812
813		#define _imul_r32_m32bd(dreg, base, disp) \
814		do { OP1(0x0f); OP1(0xaf); MODRM_MBD(dreg, base, disp); } while (0)
815
816
817
818		#define _add_m32abs_r32(addr, sreg) \
819		do { OP1(0x01); MODRM_MABS(sreg, addr); } while (0)
820
821		#define _or_m32abs_r32(addr, sreg) \
822		do { OP1(0x09); MODRM_MABS(sreg, addr); } while (0)
823
824
825		#define _arith_r32_imm_common(reg, dreg, imm) \
826		do { \
827		if ((INT8)(imm) == (INT32)(imm)) \
828		{ \
829		OP1(0x83); MODRM_REG(reg, dreg); OP1(imm); \
830		} \
831		else \
832		{ \
833		OP1(0x81); MODRM_REG(reg, dreg); OP4(imm); \
834		} \
835		} while (0)
836
837		#define _add_r32_imm(dreg, imm) \
838		do { if ((imm) == 1) OP1(0x40 + dreg); else _arith_r32_imm_common(0, dreg, imm); } while (0)
839
840		#define _adc_r32_imm(dreg, imm) \
841		do { _arith_r32_imm_common(2, dreg, imm); } while (0)
842
843		#define _or_r32_imm(dreg, imm) \
844		do { _arith_r32_imm_common(1, dreg, imm); } while (0)
845
846		#define _sbb_r32_imm(dreg, imm) \
847		do { _arith_r32_imm_common(3, dreg, imm); } while (0)
848
849		#define _and_r32_imm(dreg, imm) \
850		do { _arith_r32_imm_common(4, dreg, imm); } while (0)
851
852		#define _sub_r32_imm(dreg, imm) \
853		do { _arith_r32_imm_common(5, dreg, imm); } while (0)
854
855		#define _sub_or_dec_r32_imm(dreg, imm) \
856		do { if ((imm) == 1) OP1(0x48 + dreg); else _arith_r32_imm_common(5, dreg, imm); } while (0)
857
858		#define _sub_or_dec_m32abs_imm(addr, imm) \
859		do { if ((imm) == 1) {OP1(0xff); MODRM_MABS(1, addr); } else _arith_m32abs_imm_common(5, addr, imm); } while (0)
860
861		#define _xor_r32_imm(dreg, imm) \
862		do { _arith_r32_imm_common(6, dreg, imm); } while (0)
863
864		#define _cmp_r32_imm(dreg, imm) \
865		do { _arith_r32_imm_common(7, dreg, imm); } while (0)
866
867		#define _test_r32_imm(dreg, imm) \
868		do { OP1(0xf7); MODRM_REG(0, dreg); OP4(imm); } while (0)
869
870		#define _and_r32_r32(dreg, sreg) \
871		do { OP1(0x23); MODRM_REG(dreg, sreg); } while (0)
872
873		#define _imul_r32_r32(dreg, sreg) \
874		do { OP1(0x0f); OP1(0xaf); MODRM_REG(dreg, sreg); } while (0)
875
876
877
878		#define _arith_m32abs_imm_common(reg, addr, imm) \
879		do { \
880		if ((INT8)(imm) == (INT32)(imm)) \
881		{ \
882		OP1(0x83); MODRM_MABS(reg, addr); OP1(imm); \
883		} \
884		else \
885		{ \
886		OP1(0x81); MODRM_MABS(reg, addr); OP4(imm); \
887		} \
888		} while (0)
889
890		#define _add_m32abs_imm(addr, imm) \
891		do { _arith_m32abs_imm_common(0, addr, imm); } while (0)
892
893		#define _adc_m32abs_imm(addr, imm) \
894		do { _arith_m32abs_imm_common(2, addr, imm); } while (0)
895
896		#define _or_m32abs_imm(addr, imm) \
897		do { _arith_m32abs_imm_common(1, addr, imm); } while (0)
898
899		#define _sbb_m32abs_imm(addr, imm) \
900		do { _arith_m32abs_imm_common(3, addr, imm); } while (0)
901
902		#define _and_m32abs_imm(addr, imm) \
903		do { _arith_m32abs_imm_common(4, addr, imm); } while (0)
904
905		#define _sub_m32abs_imm(addr, imm) \
906		do { _arith_m32abs_imm_common(5, addr, imm); } while (0)
907
908		#define _xor_m32abs_imm(addr, imm) \
909		do { _arith_m32abs_imm_common(6, addr, imm); } while (0)
910
911		#define _cmp_m32abs_imm(addr, imm) \
912		do { _arith_m32abs_imm_common(7, addr, imm); } while (0)
913
914		#define _test_m32abs_imm(addr, imm) \
915		do { OP1(0xf7); MODRM_MABS(0, addr); OP4(imm); } while (0)
916
917
918
919		#define _arith_m32bd_imm_common(reg, base, disp, imm) \
920		do { \
921		if ((INT8)(imm) == (INT32)(imm)) \
922		{ \
923		OP1(0x83); MODRM_MBD(reg, base, disp); OP1(imm);\
924		} \
925		else \
926		{ \
927		OP1(0x81); MODRM_MBD(reg, base, disp); OP4(imm);\
928		} \
929		} while (0)
930
931		#define _add_m32bd_imm(base, disp, imm) \
932		do { _arith_m32bd_imm_common(0, base, disp, imm); } while (0)
933
934		#define _adc_m32bd_imm(base, disp, imm) \
935		do { _arith_m32bd_imm_common(2, base, disp, imm); } while (0)
936
937		#define _or_m32bd_imm(base, disp, imm) \
938		do { _arith_m32bd_imm_common(1, base, disp, imm); } while (0)
939
940		#define _sbb_m32bd_imm(base, disp, imm) \
941		do { _arith_m32bd_imm_common(3, base, disp, imm); } while (0)
942
943		#define _and_m32bd_imm(base, disp, imm) \
944		do { _arith_m32bd_imm_common(4, base, disp, imm); } while (0)
945
946		#define _sub_m32bd_imm(base, disp, imm) \
947		do { _arith_m32bd_imm_common(5, base, disp, imm); } while (0)
948
949		#define _xor_m32bd_imm(base, disp, imm) \
950		do { _arith_m32bd_imm_common(6, base, disp, imm); } while (0)
951
952		#define _cmp_m32bd_imm(base, disp, imm) \
953		do { _arith_m32bd_imm_common(7, base, disp, imm); } while (0)
954
955		#define _test_m32bd_imm(base, disp, imm) \
956		do { OP1(0xf7); MODRM_MBD(0, base, disp); OP4(imm); } while (0)
957
958
959
960		#define _and_r32_m32bd(dreg, base, disp) \
961		do { OP1(0x23); MODRM_MBD(dreg, base, disp); } while (0)
962
963		#define _add_r32_m32bd(dreg, base, disp) \
964		do { OP1(0x03); MODRM_MBD(dreg, base, disp); } while (0)
965
966
967
968		#define _imul_r32(reg) \
969		do { OP1(0xf7); MODRM_REG(5, reg); } while (0)
970
971		#define _mul_r32(reg) \
972		do { OP1(0xf7); MODRM_REG(4, reg); } while (0)
973
974		#define _mul_m32abs(addr) \
975		do { OP1(0xf7); MODRM_MABS(4, addr); } while (0)
976
977		#define _mul_m32bd(base, disp) \
978		do { OP1(0xf7); MODRM_MBD(4, base, disp); } while (0)
979
980		#define _idiv_r32(reg) \
981		do { OP1(0xf7); MODRM_REG(7, reg); } while (0)
982
983		#define _div_r32(reg) \
984		do { OP1(0xf7); MODRM_REG(6, reg); } while (0)
985
986		#define _and_m32bd_r32(base, disp, sreg) \
987		do { OP1(0x21); MODRM_MBD(sreg, base, disp); } while (0)
988
989		#define _add_m32bd_r32(base, disp, sreg) \
990		do { OP1(0x89); MODRM_MBD(sreg, base, disp); } while (0)
991
992		#define _sub_m32bd_r32(base, disp, sreg) \
993		do { OP1(0x29); MODRM_MBD(sreg, base, disp); } while (0)
994
995		#define _rol_r32_cl(reg) \
996		do { OP1(0xd3); OP1(0xc0 \| ((reg) & 7)); } while(0)
997
998		#define _ror_r32_cl(reg) \
999		do { OP1(0xd3); OP1(0xc8 \| ((reg) & 7)); } while(0)
1000
1001		#define _rcl_r32_cl(reg) \
1002		do { OP1(0xd3); OP1(0xd0 \| ((reg) & 7)); } while(0)
1003
1004		#define _rcr_r32_cl(reg) \
1005		do { OP1(0xd3); OP1(0xd8 \| ((reg) & 7)); } while(0)
1006
1007
1008
1009
1010		/***************************************************************************
1011		16-BIT ARITHMETIC EMITTERS
1012		***************************************************************************/
1013
1014		#define _add_r16_r16(r1, r2) \
1015		do { OP1(0x66); OP1(0x03); MODRM_REG(r2, r1); } while (0)
1016
1017		#define _adc_r16_r16(r1, r2) \
1018		do { OP1(0x66); OP1(0x11); MODRM_REG(r2, r1); } while (0)
1019
1020		#define _or_r16_r16(r1, r2) \
1021		do { OP1(0x66); OP1(0x09); MODRM_REG(r2, r1); } while (0)
1022
1023		#define _sub_r16_r16(r1, r2) \
1024		do { OP1(0x66); OP1(0x29); MODRM_REG(r2, r1); } while (0)
1025
1026		#define _sbb_r16_r16(r1, r2) \
1027		do { OP1(0x66); OP1(0x19); MODRM_REG(r2, r1); } while (0)
1028
1029		#define _xor_r16_r16(r1, r2) \
1030		do { OP1(0x66); OP1(0x31); MODRM_REG(r2, r1); } while (0)
1031
1032		#define _cmp_r16_r16(r1, r2) \
1033		do { OP1(0x66); OP1(0x39); MODRM_REG(r2, r1); } while (0)
1034
1035		#define _test_r16_r16(r1, r2) \
1036		do { OP1(0x66); OP1(0x85); MODRM_REG(r2, r1); } while (0)
1037
1038
1039
1040		#define _arith_r16_imm_common(reg, dreg, imm) \
1041		do { \
1042		if ((INT8)(imm) == (INT16)(imm)) \
1043		{ \
1044		OP1(0x66); OP1(0x83); MODRM_REG(reg, dreg); OP1(imm); \
1045		} \
1046		else \
1047		{ \
1048		OP1(0x66); OP1(0x81); MODRM_REG(reg, dreg); OP2(imm); \
1049		} \
1050		} while (0)
1051
1052		#define _add_r16_imm(dreg, imm) \
1053		do { if ((imm) == 1) { OP1(0x66); OP1(0x40 + dreg); } else _arith_r16_imm_common(0, dreg, imm); } while (0)
1054
1055		#define _adc_r16_imm(dreg, imm) \
1056		do { _arith_r16_imm_common(2, dreg, imm); } while (0)
1057
1058		#define _or_r16_imm(dreg, imm) \
1059		do { _arith_r16_imm_common(1, dreg, imm); } while (0)
1060
1061		#define _sbb_r16_imm(dreg, imm) \
1062		do { _arith_r16_imm_common(3, dreg, imm); } while (0)
1063
1064		#define _and_r16_imm(dreg, imm) \
1065		do { _arith_r16_imm_common(4, dreg, imm); } while (0)
1066
1067		#define _sub_r16_imm(dreg, imm) \
1068		do { _arith_r16_imm_common(5, dreg, imm); } while (0)
1069
1070		#define _sub_or_dec_r16_imm(dreg, imm) \
1071		do { if ((imm) == 1) OP1(0x48 + dreg); else _arith_r16_imm_common(5, dreg, imm); } while (0)
1072
1073		#define _xor_r16_imm(dreg, imm) \
1074		do { _arith_r16_imm_common(6, dreg, imm); } while (0)
1075
1076		#define _cmp_r16_imm(dreg, imm) \
1077		do { _arith_r16_imm_common(7, dreg, imm); } while (0)
1078
1079
1080
1081		/***************************************************************************
1082		16-BIT AND 8-BIT ARITHMETIC EMITTERS
1083		***************************************************************************/
1084
1085		#define _or_r8_r8(r1, r2) \
1086		do { OP1(0x08); MODRM_REG(r2, r1); } while (0)
1087
1088		#define _arith_m16abs_imm_common(reg, addr, imm) \
1089		do { \
1090		OP1(0x66); \
1091		if ((INT8)(imm) == (INT16)(imm)) \
1092		{ \
1093		OP1(0x83); MODRM_MABS(reg, addr); OP1(imm); \
1094		} \
1095		else \
1096		{ \
1097		OP1(0x81); MODRM_MABS(reg, addr); OP2(imm); \
1098		} \
1099		} while (0)
1100
1101		#define _add_m16abs_imm(addr, imm) \
1102		do { _arith_m16abs_imm_common(0, addr, imm); } while (0)
1103
1104		#define _or_m16abs_imm(addr, imm) \
1105		do { _arith_m16abs_imm_common(1, addr, imm); } while (0)
1106
1107		#define _sbb_m16abs_imm(addr, imm) \
1108		do { _arith_m16abs_imm_common(3, addr, imm); } while (0)
1109
1110		#define _and_m16abs_imm(addr, imm) \
1111		do { _arith_m16abs_imm_common(4, addr, imm); } while (0)
1112
1113		#define _sub_m16abs_imm(addr, imm) \
1114		do { _arith_m16abs_imm_common(5, addr, imm); } while (0)
1115
1116		#define _xor_m16abs_imm(addr, imm) \
1117		do { _arith_m16abs_imm_common(6, addr, imm); } while (0)
1118
1119		#define _cmp_m16abs_imm(addr, imm) \
1120		do { _arith_m16abs_imm_common(7, addr, imm); } while (0)
1121
1122		#define _test_m16abs_imm(addr, imm) \
1123		do { OP1(0xf7); MODRM_MABS(0, addr); OP2(imm); } while (0)
1124
1125		#define _and_m16bd_r16(base, disp, sreg) \
1126		do { OP1(0x66); OP1(0x21); MODRM_MBD(sreg, base, disp); } while (0)
1127
1128		#define _and_r16_m16abs(dreg, addr) \
1129		do { OP1(0x66); OP1(0x25); MODRM_MABS(dreg, addr); } while (0)
1130
1131		#define _shl_r16_cl(dreg) \
1132		do { OP1(0x66); OP1(0xd3); MODRM_REG(4, dreg); } while (0)
1133
1134		#define _shr_r16_cl(dreg) \
1135		do { OP1(0x66); OP1(0xd3); MODRM_REG(5, dreg); } while (0)
1136
1137		#define _rol_r16_cl(reg) \
1138		do { OP1(0x66); OP1(0xd3); OP1(0xc0 \| ((reg) & 7)); } while(0)
1139
1140		#define _ror_r16_cl(reg) \
1141		do { OP1(0x66); OP1(0xd3); OP1(0xc8 \| ((reg) & 7)); } while(0)
1142
1143		#define _rcl_r16_cl(reg) \
1144		do { OP1(0x66); OP1(0xd3); OP1(0xd0 \| ((reg) & 7)); } while(0)
1145
1146		#define _rcr_r16_cl(reg) \
1147		do { OP1(0x66); OP1(0xd3); OP1(0xd8 \| ((reg) & 7)); } while(0)
1148
1149		#define _cmp_r16_m16bisd(reg, base, indx, scale, disp) \
1150		do { OP1(0x66); OP1(0x3b); MODRM_MBISD(reg, base, indx, scale, disp); } while(0)
1151
1152
1153
1154		#define _arith_m8abs_imm_common(reg, addr, imm) \
1155		do { OP1(0x80); MODRM_MABS(reg, addr); OP1(imm); } while (0)
1156
1157		#define _add_m8abs_imm(addr, imm) \
1158		do { _arith_m8abs_imm_common(0, addr, imm); } while (0)
1159
1160		#define _or_m8abs_imm(addr, imm) \
1161		do { _arith_m8abs_imm_common(1, addr, imm); } while (0)
1162
1163		#define _adc_m8abs_imm(addr, imm) \
1164		do { _arith_m8abs_imm_common(2, addr, imm); } while (0)
1165
1166		#define _sbb_m8abs_imm(addr, imm) \
1167		do { _arith_m8abs_imm_common(3, addr, imm); } while (0)
1168
1169		#define _and_m8abs_imm(addr, imm) \
1170		do { _arith_m8abs_imm_common(4, addr, imm); } while (0)
1171
1172		#define _sub_m8abs_imm(addr, imm) \
1173		do { _arith_m8abs_imm_common(5, addr, imm); } while (0)
1174
1175		#define _xor_m8abs_imm(addr, imm) \
1176		do { _arith_m8abs_imm_common(6, addr, imm); } while (0)
1177
1178		#define _cmp_m8abs_imm(addr, imm) \
1179		do { _arith_m8abs_imm_common(7, addr, imm); } while (0)
1180
1181		#define _test_m8abs_imm(addr, imm) \
1182		do { OP1(0xf6); MODRM_MABS(0, addr); OP1(imm); } while (0)
1183
1184		#define _test_r8_imm(reg, imm) \
1185		do { OP1(0xf6); MODRM_REG(0, reg); OP1(imm); } while (0)
1186
1187		#define _and_m8bd_r8(base, disp, sreg) \
1188		do { OP1(0x20); MODRM_MBD(sreg, base, disp); } while (0)
1189
1190		#define _shl_r8_imm(dreg, imm) \
1191		do { \
1192		if ((imm) == 1) { OP1(0xd0); MODRM_REG(4, dreg); } \
1193		else { OP1(0xc0); MODRM_REG(4, dreg); OP1(imm); } \
1194		} while (0)
1195
1196		#define _shr_r8_imm(dreg, imm) \
1197		do { \
1198		if ((imm) == 1) { OP1(0xd0); MODRM_REG(5, dreg); } \
1199		else { OP1(0xc0); MODRM_REG(5, dreg); OP1(imm); } \
1200		} while (0)
1201
1202		#define _shl_r8_cl(dreg) \
1203		do { OP1(0xd2); MODRM_REG(4, dreg); } while (0)
1204
1205		#define _shr_r8_cl(dreg) \
1206		do { OP1(0xd2); MODRM_REG(5, dreg); } while (0)
1207
1208		#define _rol_r8_cl(reg) \
1209		do { OP1(0xd2); OP1(0xc0 \| ((reg) & 7)); } while(0)
1210
1211		#define _ror_r8_cl(reg) \
1212		do { OP1(0xd2); OP1(0xc8 \| ((reg) & 7)); } while(0)
1213
1214		#define _rcl_r8_cl(reg) \
1215		do { OP1(0xd2); OP1(0xd0 \| ((reg) & 7)); } while(0)
1216
1217		#define _rcr_r8_cl(reg) \
1218		do { OP1(0xd2); OP1(0xd8 \| ((reg) & 7)); } while(0)
1219
1220
1221
1222		/***************************************************************************
1223		FLOATING POINT EMITTERS
1224		***************************************************************************/
1225
1226		#define _fnclex() \
1227		do { OP1(0xdb); OP1(0xe2); } while (0)
1228
1229		#define _fnstsw_ax() \
1230		do { OP1(0xdf); OP1(0xe0); } while (0)
1231
1232		#define _fldcw_m16abs(addr) \
1233		do { OP1(0xd9); MODRM_MABS(5, addr); } while (0)
1234
1235		#define _fldcw_m16isd(indx, scale, addr) \
1236		do { OP1(0xd9); MODRM_MBISD(5, NO_BASE, indx, scale, addr); } while (0)
1237
1238		#define _fnstcw_m16abs(addr) \
1239		do { OP1(0xd9); MODRM_MABS(7, addr); } while (0)
1240
1241
1242
1243		#define _fabs() \
1244		do { OP1(0xd9); OP1(0xe1); } while (0)
1245
1246		#define _faddp() \
1247		do { OP1(0xde); OP1(0xc1); } while (0)
1248
1249		#define _fchs() \
1250		do { OP1(0xd9); OP1(0xe0); } while (0)
1251
1252		#define _fcompp() \
1253		do { OP1(0xde); OP1(0xd9); } while (0)
1254
1255		#define _fdivp() \
1256		do { OP1(0xde); OP1(0xf9); } while (0)
1257
1258		#define _fmulp() \
1259		do { OP1(0xde); OP1(0xc9); } while (0)
1260
1261		#define _fsqrt() \
1262		do { OP1(0xd9); OP1(0xfa); } while (0)
1263
1264		#define _fsubp() \
1265		do { OP1(0xde); OP1(0xe9); } while (0)
1266
1267		#define _fsubrp() \
1268		do { OP1(0xde); OP1(0xe1); } while (0)
1269
1270		#define _fucompp() \
1271		do { OP1(0xda); OP1(0xe9); } while (0)
1272
1273
1274
1275		#define _fld1() \
1276		do { OP1(0xd9); OP1(0xe8); } while (0)
1277
1278		#define _fld_m32abs(addr) \
1279		do { OP1(0xd9); MODRM_MABS(0, addr); } while (0)
1280
1281		#define _fld_m64abs(addr) \
1282		do { OP1(0xdd); MODRM_MABS(0, addr); } while (0)
1283
1284		#define _fild_m32abs(addr) \
1285		do { OP1(0xdb); MODRM_MABS(0, addr); } while (0)
1286
1287		#define _fild_m64abs(addr) \
1288		do { OP1(0xdf); MODRM_MABS(5, addr); } while (0)
1289
1290
1291
1292		#define _fistp_m32abs(addr) \
1293		do { OP1(0xdb); MODRM_MABS(3, addr); } while (0)
1294
1295		#define _fistp_m64abs(addr) \
1296		do { OP1(0xdf); MODRM_MABS(7, addr); } while (0)
1297
1298		#define _fstp_m32abs(addr) \
1299		do { OP1(0xd9); MODRM_MABS(3, addr); } while (0)
1300
1301		#define _fstp_m64abs(addr) \
1302		do { OP1(0xdd); MODRM_MABS(3, addr); } while (0)
1303
1304
1305
1306		/***************************************************************************
1307		BRANCH EMITTERS
1308		***************************************************************************/
1309
1310		#define _setcc_r8(cond, dreg) \
1311		do { OP1(0x0f); OP1(0x90 + cond); MODRM_REG(0, dreg); } while (0)
1312
1313		#define _setcc_m8abs(cond, addr) \
1314		do { OP1(0x0f); OP1(0x90 + cond); MODRM_MABS(0, addr); } while (0)
1315
1316
1317		#define _jcc_short_link(cond, link) \
1318		do { OP1(0x70 + (cond)); OP1(0x00); (link)->target = drc->cache_top; (link)->size = 1; } while (0)
1319
1320		#define _jcc_near_link(cond, link) \
1321		do { OP1(0x0f); OP1(0x80 + (cond)); OP4(0x00); (link)->target = drc->cache_top; (link)->size = 4; } while (0)
1322
1323		#define _jcc(cond, target) \
1324		do { \
1325		INT32 delta = (UINT8 *)(target) - (drc->cache_top + 2); \
1326		if ((INT8)delta == (INT32)delta) \
1327		{ \
1328		OP1(0x70 + (cond)); OP1(delta); \
1329		} \
1330		else \
1331		{ \
1332		delta = (UINT8 *)(target) - (drc->cache_top + 6); \
1333		OP1(0x0f); OP1(0x80 + (cond)); OP4(delta); \
1334		} \
1335		} while (0)
1336
1337
1338
1339		#define _jmp_short_link(link) \
1340		do { OP1(0xeb); OP1(0x00); (link)->target = drc->cache_top; (link)->size = 1; } while (0)
1341
1342		#define _jmp_near_link(link) \
1343		do { OP1(0xe9); OP4(0x00); (link)->target = drc->cache_top; (link)->size = 4; } while (0)
1344
1345		#define _jmp(target) \
1346		do { OP1(0xe9); OP4((UINT32)(target) - ((UINT32)drc->cache_top + 4)); } while (0)
1347
1348		#define _jmp_r32(reg) \
1349		do { OP1(0xff); MODRM_REG(4, reg); } while (0)
1350
1351
1352
1353		#define _call(target) \
1354		do { OP1(0xe8); OP4((UINT32)(target) - ((UINT32)drc->cache_top + 4)); } while (0)
1355
1356
1357
1358		#define _jmp_m32abs(addr) \
1359		do { OP1(0xff); MODRM_MABS(4, addr); } while (0)
1360
1361		#define _jmp_m32bd(base, disp) \
1362		do { OP1(0xff); MODRM_MBD(4, base, disp); } while (0)
1363
1364		#define _jmp_m32bisd(base, indx, scale, disp) \
1365		do { OP1(0xff); MODRM_MBISD(4, base, indx, scale, disp); } while (0)
1366
1367
1368
1369		#define _resolve_link(link) \
1370		do { \
1371		INT32 delta = drc->cache_top - (link)->target; \
1372		if ((link)->size == 1) \
1373		{ \
1374		if ((INT8)delta != delta) \
1375		fatalerror("Error: link out of range!\n"); \
1376		(link)->target[-1] = delta; \
1377		} \
1378		else if ((link)->size == 4) \
1379		(UINT32 )&(link)->target[-4] = delta; \
1380		else \
1381		fatalerror("Unsized link!\n"); \
1382		} while (0)
1383
1384
1385
1386		/***************************************************************************
1387		SSE EMITTERS
1388		***************************************************************************/
1389
1390		#define _ldmxcsr_m32abs(addr) \
1391		do { OP1(0x0f); OP1(0xae); MODRM_MABS(2, addr); } while (0)
1392
1393		#define _ldmxcsr_m32isd(indx, scale, disp) \
1394		do { OP1(0x0f); OP1(0xae); MODRM_MBISD(2, NO_BASE, indx, scale, disp); } while (0)
1395
1396		#define _stmxcsr_m32abs(addr) \
1397		do { OP1(0x0f); OP1(0xae); MODRM_MABS(3, addr); } while (0)
1398
1399
1400		#define _movd_mmx_r32(r1, r2) \
1401		do { OP1(0x0f); OP1(0x6e); MODRM_REG(r1, r2); } while (0)
1402
1403		#define _movd_r32_mmx(r1, r2) \
1404		do { OP1(0x0f); OP1(0x7e); MODRM_REG(r1, r2); } while (0)
1405
1406		#define _movd_mmx_m32bd(reg, base, disp) \
1407		do { OP1(0x0f); OP1(0x6e); MODRM_MBD(reg, base, disp); } while (0)
1408
1409		#define _movd_mmx_m32bisd(reg, base, indx, scale, disp) \
1410		do { OP1(0x0f); OP1(0x6e); MODRM_MBISD(reg, base, indx, scale, disp); } while (0)
1411
1412		#define _movd_r128_r32(r1, r2) \
1413		do { OP1(0x66); OP1(0x0f); OP1(0x6e); MODRM_REG(r1, r2); } while (0)
1414
1415		#define _movd_r32_r128(r1, r2) \
1416		do { OP1(0x66); OP1(0x0f); OP1(0x7e); MODRM_REG(r2, r1); } while (0)
1417
1418		#define _movd_r128_m32abs(reg, addr) \
1419		do { OP1(0x66); OP1(0x0f); OP1(0x6e); MODRM_MABS(reg, addr); } while (0)
1420
1421		#define _movd_r128_m32isd(reg, indx, scale, disp) \
1422		do { OP1(0x66); OP1(0x0f); OP1(0x6e); MODRM_MBISD(reg, NO_BASE, indx, scale, disp); } while (0)
1423
1424
1425		#define _movq_r128_m64abs(reg, addr) \
1426		do { OP1(0xf3); OP1(0x0f); OP1(0x7e); MODRM_MABS(reg, addr); } while (0)
1427
1428		#define _movq_r128_m64isd(reg, indx, scale, disp) \
1429		do { OP1(0xf3); OP1(0x0f); OP1(0x7e); MODRM_MBISD(reg, NO_BASE, indx, scale, disp); } while (0)
1430
1431		#define _movq_r128_m64bisd(reg, base, indx, scale, disp) \
1432		do { OP1(0xf3); OP1(0x0f); OP1(0x7e); MODRM_MBISD(reg, base, indx, scale, disp); } while (0)
1433
1434		#define _movq_m64abs_r128(addr, reg) \
1435		do { OP1(0x66); OP1(0x0f); OP1(0xd6); MODRM_MABS(reg, addr); } while (0)
1436
1437
1438		#define _movdqa_r128_r128(r1, r2) \
1439		do { OP1(0x66); OP1(0x0f); OP1(0x6f); MODRM_REG(r1, r2); } while (0)
1440
1441		#define _movdqa_r128_m128abs(reg, addr) \
1442		do { OP1(0x66); OP1(0x0f); OP1(0x6f); MODRM_MABS(reg, addr); } while (0)
1443
1444		#define _movdqa_m128abs_r128(addr, reg) \
1445		do { OP1(0x66); OP1(0x0f); OP1(0x7f); MODRM_MABS(reg, addr); } while (0)
1446
1447
1448		#define _movaps_r128_m128abs(reg, addr) \
1449		do { OP1(0x0f); OP1(0x28); MODRM_MABS(reg, addr); } while (0)
1450
1451		#define _movaps_m128abs_r128(addr, reg) \
1452		do { OP1(0x0f); OP1(0x29); MODRM_MABS(reg, addr); } while (0)
1453
1454
1455		#define _movss_r128_m32abs(reg, addr) \
1456		do { OP1(0xf3); OP1(0x0f); OP1(0x10); MODRM_MABS(reg, addr); } while (0)
1457
1458		#define _movss_r128_m32bd(reg, base, disp) \
1459		do { OP1(0xf3); OP1(0x0f); OP1(0x10); MODRM_MBD(reg, base, disp); } while (0)
1460
1461		#define _movss_r128_r128(r1, r2) \
1462		do { OP1(0xf3); OP1(0x0f); OP1(0x10); MODRM_REG(r1, r2); } while (0)
1463
1464		#define _movss_m32abs_r128(addr, reg) \
1465		do { OP1(0xf3); OP1(0x0f); OP1(0x11); MODRM_MABS(reg, addr); } while (0)
1466
1467
1468		#define _movsd_r128_m64abs(reg, addr) \
1469		do { OP1(0xf2); OP1(0x0f); OP1(0x10); MODRM_MABS(reg, addr); } while (0)
1470
1471		#define _movsd_r128_m64bd(reg, base, disp) \
1472		do { OP1(0xf2); OP1(0x0f); OP1(0x10); MODRM_MBD(reg, base, disp); } while (0)
1473
1474		#define _movsd_r128_r128(r1, r2) \
1475		do { OP1(0xf2); OP1(0x0f); OP1(0x10); MODRM_REG(r1, r2); } while (0)
1476
1477		#define _movsd_m64abs_r128(addr, reg) \
1478		do { OP1(0xf2); OP1(0x0f); OP1(0x11); MODRM_MABS(reg, addr); } while (0)
1479
1480		#define _movsd_m64bd_r128(base, disp, reg) \
1481		do { OP1(0xf2); OP1(0x0f); OP1(0x11); MODRM_MBD(reg, base, disp); } while (0)
1482
1483
1484
1485		#define _addps_r128_m128abs(reg, addr) \
1486		do { OP1(0x0f); OP1(0x58); MODRM_MABS(reg, addr); } while (0)
1487
1488		#define _addss_r128_m32abs(reg, addr) \
1489		do { OP1(0xf3); OP1(0x0f); OP1(0x58); MODRM_MABS(reg, addr); } while (0)
1490
1491		#define _addss_r128_m32bd(reg, base, disp) \
1492		do { OP1(0xf3); OP1(0x0f); OP1(0x58); MODRM_MBD(reg, base, disp); } while (0)
1493
1494		#define _addsd_r128_m64abs(reg, addr) \
1495		do { OP1(0xf2); OP1(0x0f); OP1(0x58); MODRM_MABS(reg, addr); } while (0)
1496
1497		#define _andps_r128_m128abs(reg, addr) \
1498		do { OP1(0x0f); OP1(0x54); MODRM_MABS(reg, addr); } while (0)
1499
1500		#define _andpd_r128_m128abs(reg, addr) \
1501		do { OP1(0x66); OP1(0x0f); OP1(0x54); MODRM_MABS(reg, addr); } while (0)
1502
1503		#define _comiss_r128_m32abs(reg, addr) \
1504		do { OP1(0x0f); OP1(0x2f); MODRM_MABS(reg, addr); } while (0)
1505
1506		#define _comisd_r128_m64abs(reg, addr) \
1507		do { OP1(0x66); OP1(0x0f); OP1(0x2f); MODRM_MABS(reg, addr); } while (0)
1508
1509		#define _cvtsi2ss_r128_m32abs(reg, addr) \
1510		do { OP1(0xf3); OP1(0x0f); OP1(0x2a); MODRM_MABS(reg, addr); } while (0)
1511
1512		#define _cvttss2si_r32_m32abs(reg, addr) \
1513		do { OP1(0xf3); OP1(0x0f); OP1(0x2c); MODRM_MABS(reg, addr); } while (0)
1514
1515		#define _cvttsd2si_r32_m64abs(reg, addr) \
1516		do { OP1(0xf2); OP1(0x0f); OP1(0x2c); MODRM_MABS(reg, addr); } while (0)
1517
1518		#define _divss_r128_m32abs(reg, addr) \
1519		do { OP1(0xf3); OP1(0x0f); OP1(0x5e); MODRM_MABS(reg, addr); } while (0)
1520
1521		#define _divsd_r128_m64abs(reg, addr) \
1522		do { OP1(0xf2); OP1(0x0f); OP1(0x5e); MODRM_MABS(reg, addr); } while (0)
1523
1524		#define _mulss_r128_m32abs(reg, addr) \
1525		do { OP1(0xf3); OP1(0x0f); OP1(0x59); MODRM_MABS(reg, addr); } while (0)
1526
1527		#define _mulss_r128_m32bd(reg, base, disp) \
1528		do { OP1(0xf3); OP1(0x0f); OP1(0x59); MODRM_MBD(reg, base, disp); } while (0)
1529
1530		#define _mulsd_r128_m64abs(reg, addr) \
1531		do { OP1(0xf2); OP1(0x0f); OP1(0x59); MODRM_MABS(reg, addr); } while (0)
1532
1533		#define _mulps_r128_m128abs(reg, addr) \
1534		do { OP1(0x0f); OP1(0x59); MODRM_MABS(reg, addr); } while (0)
1535
1536		#define _orps_r128_m128abs(reg, addr) \
1537		do { OP1(0x0f); OP1(0x56); MODRM_MABS(reg, addr); } while (0)
1538
1539		#define _orpd_r128_m128abs(reg, addr) \
1540		do { OP1(0x66); OP1(0x0f); OP1(0x56); MODRM_MABS(reg, addr); } while (0)
1541
1542		#define _rcpss_r128_m32abs(reg, addr) \
1543		do { OP1(0xf3); OP1(0x0f); OP1(0x53); MODRM_MABS(reg, addr); } while (0)
1544
1545		#define _rsqrtss_r128_m32abs(reg, addr) \
1546		do { OP1(0xf3); OP1(0x0f); OP1(0x52); MODRM_MABS(reg, addr); } while (0)
1547
1548		#define _sqrtss_r128_m32abs(reg, addr) \
1549		do { OP1(0xf3); OP1(0x0f); OP1(0x51); MODRM_MABS(reg, addr); } while (0)
1550
1551		#define _sqrtsd_r128_m64abs(reg, addr) \
1552		do { OP1(0xf2); OP1(0x0f); OP1(0x51); MODRM_MABS(reg, addr); } while (0)
1553
1554		#define _subss_r128_m32abs(reg, addr) \
1555		do { OP1(0xf3); OP1(0x0f); OP1(0x5c); MODRM_MABS(reg, addr); } while (0)
1556
1557		#define _subss_r128_m32bd(reg, base, disp) \
1558		do { OP1(0xf3); OP1(0x0f); OP1(0x5c); MODRM_MBD(reg, base, disp); } while (0)
1559
1560		#define _subsd_r128_m64abs(reg, addr) \
1561		do { OP1(0xf2); OP1(0x0f); OP1(0x5c); MODRM_MABS(reg, addr); } while (0)
1562
1563		#define _ucomiss_r128_m32abs(reg, addr) \
1564		do { OP1(0x0f); OP1(0x2e); MODRM_MABS(reg, addr); } while (0)
1565
1566		#define _ucomisd_r128_m64abs(reg, addr) \
1567		do { OP1(0x66); OP1(0x0f); OP1(0x2e); MODRM_MABS(reg, addr); } while (0)
1568
1569		#define _xorps_r128_m128abs(reg, addr) \
1570		do { OP1(0x0f); OP1(0x57); MODRM_MABS(reg, addr); } while (0)
1571
1572		#define _xorpd_r128_m128abs(reg, addr) \
1573		do { OP1(0x66); OP1(0x0f); OP1(0x57); MODRM_MABS(reg, addr); } while (0)
1574
1575
1576
1577		#define _addps_r128_r128(r1, r2) \
1578		do { OP1(0x0f); OP1(0x58); MODRM_REG(r1, r2); } while (0)
1579
1580		#define _addss_r128_r128(r1, r2) \
1581		do { OP1(0xf3); OP1(0x0f); OP1(0x58); MODRM_REG(r1, r2); } while (0)
1582
1583		#define _addsd_r128_r128(r1, r2) \
1584		do { OP1(0xf2); OP1(0x0f); OP1(0x58); MODRM_REG(r1, r2); } while (0)
1585
1586		#define _andps_r128_r128(r1, r2) \
1587		do { OP1(0x0f); OP1(0x54); MODRM_REG(r1, r2); } while (0)
1588
1589		#define _andpd_r128_r128(r1, r2) \
1590		do { OP1(0x66); OP1(0x0f); OP1(0x54); MODRM_REG(r1, r2); } while (0)
1591
1592		#define _cmpps_r128_r128(r1, r2, typ) \
1593		do { OP1(0x0f); OP1(0xc2); MODRM_REG(r1, r2); OP1(typ); } while (0)
1594
1595		#define _comiss_r128_r128(r1, r2) \
1596		do { OP1(0x0f); OP1(0x2f); MODRM_REG(r1, r2); } while (0)
1597
1598		#define _comiss_r128_m32bd(reg, base, disp) \
1599		do { OP1(0x0f); OP1(0x2f); MODRM_MBD(reg, base, disp); } while (0)
1600
1601		#define _comisd_r128_r128(r1, r2) \
1602		do { OP1(0x66); OP1(0x0f); OP1(0x2f); MODRM_REG(r1, r2); } while (0)
1603
1604		#define _cvtdq2ps_r128_r128(r1, r2) \
1605		do { OP1(0x0f); OP1(0x5b); MODRM_REG(r1, r2); } while (0)
1606
1607		#define _cvtdq2pd_r128_r128(r1, r2) \
1608		do { OP1(0xf3); OP1(0x0f); OP1(0xe6); MODRM_REG(r1, r2); } while (0)
1609
1610		#define _cvtps2dq_r128_r128(r1, r2) \
1611		do { OP1(0x66); OP1(0x0f); OP1(0x5b); MODRM_REG(r1, r2); } while (0)
1612
1613		#define _cvtpd2dq_r128_r128(r1, r2) \
1614		do { OP1(0xf2); OP1(0x0f); OP1(0xe6); MODRM_REG(r1, r2); } while (0)
1615
1616		#define _cvtpd2ps_r128_r128(r1, r2) \
1617		do { OP1(0x66); OP1(0x0f); OP1(0x5a); MODRM_REG(r1, r2); } while (0)
1618
1619		#define _cvtps2pd_r128_r128(r1, r2) \
1620		do { OP1(0x0f); OP1(0x5a); MODRM_REG(r1, r2); } while (0)
1621
1622		#define _cvtsd2ss_r128_r128(r1, r2) \
1623		do { OP1(0xf2); OP1(0x0f); OP1(0x5a); MODRM_REG(r1, r2); } while (0)
1624
1625		#define _cvtsi2ss_r128_r32(r1, r2) \
1626		do { OP1(0xf3); OP1(0x0f); OP1(0x2a); MODRM_REG(r1, r2); } while (0)
1627
1628		#define _cvtss2sd_r128_r128(r1, r2) \
1629		do { OP1(0xf3); OP1(0x0f); OP1(0x5a); MODRM_REG(r1, r2); } while (0)
1630
1631		#define _cvttps2dq_r128_r128(r1, r2) \
1632		do { OP1(0xf3); OP1(0x0f); OP1(0x5b); MODRM_REG(r1, r2); } while (0)
1633
1634		#define _cvttpd2dq_r128_r128(r1, r2) \
1635		do { OP1(0x66); OP1(0x0f); OP1(0xe6); MODRM_REG(r1, r2); } while (0)
1636
1637		#define _cvttss2si_r32_r128(r1, r2) \
1638		do { OP1(0xf3); OP1(0x0f); OP1(0x2c); MODRM_REG(r1, r2); } while (0)
1639
1640		#define _cvttsd2si_r32_r128(r1, r2) \
1641		do { OP1(0xf2); OP1(0x0f); OP1(0x2c); MODRM_REG(r1, r2); } while (0)
1642
1643		#define _divps_r128_r128(r1, r2) \
1644		do { OP1(0x0f); OP1(0x5e); MODRM_REG(r1, r2); } while (0)
1645
1646		#define _divss_r128_r128(r1, r2) \
1647		do { OP1(0xf3); OP1(0x0f); OP1(0x5e); MODRM_REG(r1, r2); } while (0)
1648
1649		#define _divsd_r128_r128(r1, r2) \
1650		do { OP1(0xf2); OP1(0x0f); OP1(0x5e); MODRM_REG(r1, r2); } while (0)
1651
1652		#define _maxss_r128_r128(r1, r2) \
1653		do { OP1(0xf3); OP1(0x0f); OP1(0x5f); MODRM_REG(r1, r2); } while (0)
1654
1655		#define _mulps_r128_r128(r1, r2) \
1656		do { OP1(0x0f); OP1(0x59); MODRM_REG(r1, r2); } while (0)
1657
1658		#define _mulss_r128_r128(r1, r2) \
1659		do { OP1(0xf3); OP1(0x0f); OP1(0x59); MODRM_REG(r1, r2); } while (0)
1660
1661		#define _mulsd_r128_r128(r1, r2) \
1662		do { OP1(0xf2); OP1(0x0f); OP1(0x59); MODRM_REG(r1, r2); } while (0)
1663
1664		#define _orps_r128_r128(r1, r2) \
1665		do { OP1(0x0f); OP1(0x56); MODRM_REG(r1, r2); } while (0)
1666
1667		#define _orpd_r128_r128(r1, r2) \
1668		do { OP1(0x66); OP1(0x0f); OP1(0x56); MODRM_REG(r1, r2); } while (0)
1669
1670		#define _rcpps_r128_r128(r1, r2) \
1671		do { OP1(0x0f); OP1(0x53); MODRM_REG(r1, r2); } while (0)
1672
1673		#define _rcpss_r128_r128(r1, r2) \
1674		do { OP1(0xf3); OP1(0x0f); OP1(0x53); MODRM_REG(r1, r2); } while (0)
1675
1676		#define _rsqrtss_r128_r128(r1, r2) \
1677		do { OP1(0xf3); OP1(0x0f); OP1(0x52); MODRM_REG(r1, r2); } while (0)
1678
1679		#define _shufps_r128_r128(r1, r2, imm) \
1680		do { OP1(0x0f); OP1(0xc6); MODRM_REG(r1, r2); OP1(imm); } while (0)
1681
1682		#define _sqrtss_r128_r128(r1, r2) \
1683		do { OP1(0xf3); OP1(0x0f); OP1(0x51); MODRM_REG(r1, r2); } while (0)
1684
1685		#define _sqrtsd_r128_r128(r1, r2) \
1686		do { OP1(0xf2); OP1(0x0f); OP1(0x51); MODRM_REG(r1, r2); } while (0)
1687
1688		#define _subss_r128_r128(r1, r2) \
1689		do { OP1(0xf3); OP1(0x0f); OP1(0x5c); MODRM_REG(r1, r2); } while (0)
1690
1691		#define _subsd_r128_r128(r1, r2) \
1692		do { OP1(0xf2); OP1(0x0f); OP1(0x5c); MODRM_REG(r1, r2); } while (0)
1693
1694		#define _ucomiss_r128_r128(r1, r2) \
1695		do { OP1(0x0f); OP1(0x2e); MODRM_REG(r1, r2); } while (0)
1696
1697		#define _ucomisd_r128_r128(r1, r2) \
1698		do { OP1(0x66); OP1(0x0f); OP1(0x2e); MODRM_REG(r1, r2); } while (0)
1699
1700		#define _unpcklps_r128_r128(r1, r2) \
1701		do { OP1(0x0f); OP1(0x14); MODRM_REG(r1, r2); } while (0)
1702
1703		#define _xorps_r128_r128(r1, r2) \
1704		do { OP1(0x0f); OP1(0x57); MODRM_REG(r1, r2); } while (0)
1705
1706		#define _xorpd_r128_r128(r1, r2) \
1707		do { OP1(0x66); OP1(0x0f); OP1(0x57); MODRM_REG(r1, r2); } while (0)
1708
1709
1710
1711		#define _packuswb_r128_r128(r1, r2) \
1712		do { OP1(0x66); OP1(0x0f); OP1(0x67); MODRM_REG(r1, r2); } while (0)
1713
1714		#define _paddw_r128_r128(r1, r2) \
1715		do { OP1(0x66); OP1(0x0f); OP1(0xfd); MODRM_REG(r1, r2); } while (0)
1716
1717		#define _paddw_r128_m128abs(reg, addr) \
1718		do { OP1(0x66); OP1(0x0f); OP1(0xfd); MODRM_MABS(reg, addr); } while (0)
1719
1720		#define _paddw_r128_m128bisd(reg, base, indx, scale, disp) \
1721		do { OP1(0x66); OP1(0x0f); OP1(0xfd); MODRM_MBISD(reg, base, indx, scale, disp); } while (0)
1722
1723		#define _paddd_r128_m128abs(reg, addr) \
1724		do { OP1(0x66); OP1(0x0f); OP1(0xfe); MODRM_MABS(reg, addr); } while (0)
1725
1726		#define _paddd_r128_m128bd(reg, base, disp) \
1727		do { OP1(0x66); OP1(0x0f); OP1(0xfe); MODRM_MBD(reg, base, disp); } while (0)
1728
1729		#define _paddq_r128_r128(r1, r2) \
1730		do { OP1(0x66); OP1(0x0f); OP1(0xd4); MODRM_REG(r1, r2); } while (0)
1731
1732		#define _pand_r128_r128(r1, r2) \
1733		do { OP1(0x66); OP1(0x0f); OP1(0xdb); MODRM_REG(r1, r2); } while (0)
1734
1735		#define _pand_r128_m128abs(reg, addr) \
1736		do { OP1(0x66); OP1(0x0f); OP1(0xdb); MODRM_MABS(reg, addr); } while (0)
1737
1738		#define _pandn_r128_r128(r1, r2) \
1739		do { OP1(0x66); OP1(0x0f); OP1(0xdf); MODRM_REG(r1, r2); } while (0)
1740
1741		#define _packssdw_r128_r128(r1, r2) \
1742		do { OP1(0x66); OP1(0x0f); OP1(0x6b); MODRM_REG(r1, r2); } while (0)
1743
1744		#define _pextrw_r32_r128(r1, r2, imm) \
1745		do { OP1(0x66); OP1(0x0f); OP1(0xc5); MODRM_REG(r1, r2); OP1(imm); } while (0)
1746
1747		#define _pinsrw_r128_r32(r1, r2, imm) \
1748		do { OP1(0x66); OP1(0x0f); OP1(0xc4); MODRM_REG(r1, r2); OP1(imm); } while (0)
1749
1750		#define _pmaxsw_r128_m128abs(reg, addr) \
1751		do { OP1(0x66); OP1(0x0f); OP1(0xee); MODRM_MABS(reg, addr); } while (0)
1752
1753		#define _pminsw_r128_m128abs(reg, addr) \
1754		do { OP1(0x66); OP1(0x0f); OP1(0xea); MODRM_MABS(reg, addr); } while (0)
1755
1756		#define _pmullw_r128_r128(r1, r2) \
1757		do { OP1(0x66); OP1(0x0f); OP1(0xd5); MODRM_REG(r1, r2); } while (0)
1758
1759		#define _por_r128_r128(r1, r2) \
1760		do { OP1(0x66); OP1(0x0f); OP1(0xeb); MODRM_REG(r1, r2); } while (0)
1761
1762		#define _pshufd_r128_r128(r1, r2, imm) \
1763		do { OP1(0x66); OP1(0x0f); OP1(0x70); MODRM_REG(r1, r2); OP1(imm); } while (0)
1764
1765		#define _pshufhw_r128_r128(r1, r2, imm) \
1766		do { OP1(0xf3); OP1(0x0f); OP1(0x70); MODRM_REG(r1, r2); OP1(imm); } while (0)
1767
1768		#define _pshuflw_r128_r128(r1, r2, imm) \
1769		do { OP1(0xf2); OP1(0x0f); OP1(0x70); MODRM_REG(r1, r2); OP1(imm); } while (0)
1770
1771		#define _psllw_r128_imm(reg, imm) \
1772		do { OP1(0x66); OP1(0x0f); OP1(0x71); MODRM_REG(6, reg); OP1(imm); } while (0)
1773
1774		#define _psllq_r128_imm(reg, imm) \
1775		do { OP1(0x66); OP1(0x0f); OP1(0x73); MODRM_REG(6, reg); OP1(imm); } while (0)
1776
1777		#define _psllq_r128_r128(r1, r2) \
1778		do { OP1(0x66); OP1(0x0f); OP1(0xf3); MODRM_REG(r1, r2); } while (0)
1779
1780		#define _psrlw_r128_imm(reg, imm) \
1781		do { OP1(0x66); OP1(0x0f); OP1(0x71); MODRM_REG(2, reg); OP1(imm); } while (0)
1782
1783		#define _psrld_r128_imm(reg, imm) \
1784		do { OP1(0x66); OP1(0x0f); OP1(0x72); MODRM_REG(2, reg); OP1(imm); } while (0)
1785
1786		#define _psrlq_r128_imm(reg, imm) \
1787		do { OP1(0x66); OP1(0x0f); OP1(0x73); MODRM_REG(2, reg); OP1(imm); } while (0)
1788
1789		#define _psrlq_r128_r128(r1, r2) \
1790		do { OP1(0x66); OP1(0x0f); OP1(0xd3); MODRM_REG(r1, r2); } while (0)
1791
1792		#define _psrldq_r128_imm(reg, imm) \
1793		do { OP1(0x66); OP1(0x0f); OP1(0x73); MODRM_REG(3, reg); OP1(imm); } while (0)
1794
1795		#define _psubw_r128_r128(r1, r2) \
1796		do { OP1(0x66); OP1(0x0f); OP1(0xf9); MODRM_REG(r1, r2); } while (0)
1797
1798		#define _psubw_r128_m128abs(reg, addr) \
1799		do { OP1(0x66); OP1(0x0f); OP1(0xf9); MODRM_MABS(reg, addr); } while (0)
1800
1801		#define _psubd_r128_r128(r1, r2) \
1802		do { OP1(0x66); OP1(0x0f); OP1(0xfa); MODRM_REG(r1, r2); } while (0)
1803
1804		#define _psubd_r128_m128abs(reg, addr) \
1805		do { OP1(0x66); OP1(0x0f); OP1(0xfa); MODRM_MABS(reg, addr); } while (0)
1806
1807		#define _psubd_r128_m128bd(reg, base, disp) \
1808		do { OP1(0x66); OP1(0x0f); OP1(0xfa); MODRM_MBD(reg, base, disp); } while (0)
1809
1810		#define _psubq_r128_r128(r1, r2) \
1811		do { OP1(0x66); OP1(0x0f); OP1(0xfb); MODRM_REG(r1, r2); } while (0)
1812
1813		#define _punpcklbw_r128_r128(r1, r2) \
1814		do { OP1(0x66); OP1(0x0f); OP1(0x60); MODRM_REG(r1, r2); } while (0)
1815
1816		#define _punpcklbw_r128_m128abs(reg, addr) \
1817		do { OP1(0x66); OP1(0x0f); OP1(0x60); MODRM_MABS(reg, addr); } while (0)
1818
1819		#define _punpckldq_r128_r128(r1, r2) \
1820		do { OP1(0x66); OP1(0x0f); OP1(0x62); MODRM_REG(r1, r2); } while (0)
1821
1822		#define _punpcklqdq_r128_r128(r1, r2) \
1823		do { OP1(0x66); OP1(0x0f); OP1(0x6c); MODRM_REG(r1, r2); } while (0)
1824
1825		#define _pxor_r128_r128(r1, r2) \
1826		do { OP1(0x66); OP1(0x0f); OP1(0xef); MODRM_REG(r1, r2); } while (0)
1827
1828		#define _pxor_r128_m128abs(reg, addr) \
1829		do { OP1(0x66); OP1(0x0f); OP1(0xef); MODRM_MABS(reg, addr); } while (0)
1830
1831		#define _punpcklbw_mmx_mmx(r1, r2) \
1832		do { OP1(0x0f); OP1(0x60); MODRM_REG(r1, r2); } while (0)
1833
1834		#define _punpcklwd_mmx_mmx(r1, r2) \
1835		do { OP1(0x0f); OP1(0x61); MODRM_REG(r1, r2); } while (0)
1836
1837		#define _punpckldq_mmx_mmx(r1, r2) \
1838		do { OP1(0x0f); OP1(0x62); MODRM_REG(r1, r2); } while (0)
1839
1840		#define _punpckhwd_mmx_mmx(r1, r2) \
1841		do { OP1(0x0f); OP1(0x69); MODRM_REG(r1, r2); } while (0)
1842
1843		#define _punpckhdq_mmx_mmx(r1, r2) \
1844		do { OP1(0x0f); OP1(0x6A); MODRM_REG(r1, r2); } while (0)
1845
1846
1847		#define _prefetch_m8abs(type, addr) \
1848		do { OP1(0x0f); OP1(0x18); MODRM_MABS(type, addr); } while (0)
1849
1850		#define _prefetch_m8bd(type, base, disp) \
1851		do { OP1(0x0f); OP1(0x18); MODRM_MBD(type, base, disp); } while (0)
1852
1853
1854		#define _emms() \
1855		do { OP1(0x0f); OP1(0x77); } while(0)
1856
1857		#define _mfence() \
1858		do { OP1(0x0f); OP1(0xae); OP1(0xf0); } while(0)
1859
1860		#define _sfence() \
1861		do { OP1(0x0f); OP1(0xae); OP1(0xf8); } while(0)
1862
1863
1864		#define _movnti_m32abs_r32(addr, sreg) \
1865		do { OP1(0x0f); OP1(0xc3); MODRM_MABS(sreg, addr); } while (0)
1866
1867		#define _movnti_m32bd_r32(base, disp, sreg) \
1868		do { OP1(0x0f); OP1(0xc3); MODRM_MBD(sreg, base, disp); } while (0)
1869
1870		#define _movnti_m32isd_r32(indx, scale, addr, dreg) \
1871		do { OP1(0x0f); OP1(0xc3); MODRM_MBISD(dreg, NO_BASE, indx, scale, addr); } while (0)
1872
1873		#define _movnti_m32bisd_r32(base, indx, scale, addr, dreg) \
1874		do { OP1(0x0f); OP1(0xc3); MODRM_MBISD(dreg, base, indx, scale, addr); } while (0)
1875
1876		#define _movntq_m64abs_mmx(addr, sreg) \
1877		do { OP1(0x0f); OP1(0xe7); MODRM_MABS(sreg, addr); } while (0)
1878
1879		#define _movntq_m64bd_mmx(base, disp, sreg) \
1880		do { OP1(0x0f); OP1(0xe7); MODRM_MBD(sreg, base, disp); } while (0)
1881
1882		#define _movntq_m64isd_mmx(indx, scale, addr, dreg) \
1883		do { OP1(0x0f); OP1(0xe7); MODRM_MBISD(dreg, NO_BASE, indx, scale, addr); } while (0)
1884
1885		#define _movntq_m64bisd_mmx(base, indx, scale, addr, dreg) \
1886		do { OP1(0x0f); OP1(0xe7); MODRM_MBISD(dreg, base, indx, scale, addr); } while (0)
1887
1888		#define _movq_mmx_mmx(dreg, sreg) \
1889		do { OP1(0x0f); OP1(0x7f); MODRM_REG(sreg, dreg); } while (0)
1890
1891		#define _movq_mmx_m64bd(dreg, base, disp) \
1892		do { OP1(0x0f); OP1(0x6f); MODRM_MBD(dreg, base, disp); } while (0)
1893
1894		#define _movq_m64abs_mmx(addr, sreg) \
1895		do { OP1(0x0f); OP1(0x7f); MODRM_MABS(sreg, addr); } while (0)
1896
1897		#define _movq_m64bd_mmx(base, disp, sreg) \
1898		do { OP1(0x0f); OP1(0x7f); MODRM_MBD(sreg, base, disp); } while (0)
1899
1900		#define _movq_m64isd_mmx(indx, scale, addr, dreg) \
1901		do { OP1(0x0f); OP1(0x7f); MODRM_MBISD(dreg, NO_BASE, indx, scale, addr); } while (0)
1902
1903		#define _movq_m64bisd_mmx(base, indx, scale, addr, dreg) \
1904		do { OP1(0x0f); OP1(0x7f); MODRM_MBISD(dreg, base, indx, scale, addr); } while (0)
1905
1906		#define _pand_mmx_mmx(r1, r2) \
1907		do { OP1(0x0f); OP1(0xdb); MODRM_REG(r1, r2); } while (0)
1908
1909		#define _pand_mmx_m64abs(reg, addr) \
1910		do { OP1(0x0f); OP1(0xdb); MODRM_MABS(reg, addr); } while (0)
1911
1912		#define _por_mmx_mmx(r1, r2) \
1913		do { OP1(0x0f); OP1(0xeb); MODRM_REG(r1, r2); } while (0)
1914
1915		#define _pxor_mmx_mmx(r1, r2) \
1916		do { OP1(0x0f); OP1(0xef); MODRM_REG(r1, r2); } while (0)
1917
1918		#define _por_mmx_m64abs(reg, addr) \
1919		do { OP1(0x0f); OP1(0xeb); MODRM_MABS(reg, addr); } while (0)
1920
1921		#define _pssrd_mmx_imm(reg, imm) \
1922		do { OP1(0x0f); OP1(0x72); MODRM_REG(2, reg); OP1(imm); } while (0)
1923
1924		#define _pssld_mmx_imm(reg, imm) \
1925		do { OP1(0x0f); OP1(0x72); MODRM_REG(6, reg); OP1(imm); } while (0)
1926
1927		#define _pshufw_mmx_mmx_imm(dreg, sreg, imm) \
1928		do { OP1(0x0f); OP1(0x70); MODRM_REG(dreg, sreg); OP1(imm); } while (0)
1929
1930		#define _packssdw_mmx_mmx(r1, r2) \
1931		do { OP1(0x0f); OP1(0x6b); MODRM_REG(r1, r2); } while (0)
1932
1933
1934
1935		/***************************************************************************
1936	152	FUNCTION PROTOTYPES
1937	153	***************************************************************************/
1938	154
r949	r950
1957	173	void drc_append_standard_epilogue(drc_core *drc, INT32 cycles, INT32 pcdelta, int allow_exit);
1958	174	void drc_append_save_volatiles(drc_core *drc);
1959	175	void drc_append_restore_volatiles(drc_core *drc);
1960		void drc_append_save_call_restore(drc_core drc, genf target, UINT32 stackadj);
	176	void drc_append_save_call_restore(drc_core drc, x86code target, UINT32 stackadj);
1961	177	void drc_append_verify_code(drc_core drc, void code, UINT8 length);
1962	178
1963	179	void drc_append_set_fp_rounding(drc_core *drc, UINT8 regindex);

src/emu/cpu/powerpc/ppc.c
r949	r950
1367	1367	static void ppc601_init(int index, int clock, const void _config, int (irqcallback)(int))
1368	1368	{
1369	1369	const ppc_config *config = _config;
1370		int pll_config = 0;
1371	1370	float multiplier;
1372	1371	int i ;
1373	1372

src/emu/cpu/powerpc/drc_ops.c
r949	r950
13	13	#define RECOMPILE_END_OF_STRING 0x0002
14	14	#define RECOMPILE_ADD_DISPATCH 0x0004
15	15
	16	INLINE void emit_mov_r64_m64(x86code **emitptr, UINT8 reghi, UINT8 reglo, DECLARE_MEMPARAMS)
	17	{
	18	emit_mov_r32_m32(emitptr, reglo, MEMPARAMS);
	19	emit_mov_r32_m32(emitptr, reghi, base, index, scale, disp+4);
	20	}
	21
	22	INLINE void emit_mov_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 reghi, UINT8 reglo)
	23	{
	24	emit_mov_m32_r32(emitptr, MEMPARAMS, reglo);
	25	emit_mov_m32_r32(emitptr, base, index, scale, disp+4, reghi);
	26	}
	27
	28
16	29	static UINT32 compile_one(drc_core *drc, UINT32 pc);
17	30
18	31	static void append_generate_exception(drc_core *drc, UINT8 exception);
r949	r950
49	62
50	63	static void ppcdrc_reset(drc_core *drc)
51	64	{
	65	code_log_reset();
	66
	67	code_log("entry_point:", (x86code *)drc->entry_point, drc->out_of_cycles);
	68	code_log("out_of_cycles:", drc->out_of_cycles, drc->recompile);
	69	code_log("recompile:", drc->recompile, drc->dispatch);
	70	code_log("dispatch:", drc->dispatch, drc->flush);
	71	code_log("flush:", drc->flush, drc->cache_top);
	72
52	73	ppc.invoke_exception_handler = drc->cache_top;
53	74	drc_append_restore_volatiles(drc);
54		_mov_r32_m32bd(REG_EAX, REG_ESP, 4);
55		_mov_r32_m32abs(REG_ESP, &ppc.host_esp);
56		_mov_m32abs_r32(&SRR0, REG_EDI); /* save return address */
57		_jmp_r32(REG_EAX);
	75	emit_mov_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 4));
	76	emit_mov_r32_m32(DRCTOP, REG_ESP, MABS(&ppc.host_esp));
	77	emit_mov_m32_r32(DRCTOP, MABS(&SRR0), REG_EDI); /* save return address */
	78	emit_jmp_r32(DRCTOP, REG_EAX);
	79	code_log("invoke_exception_handler:", ppc.invoke_exception_handler, drc->cache_top);
58	80
59	81	ppc.generate_interrupt_exception = drc->cache_top;
60	82	append_generate_exception(drc, EXCEPTION_IRQ);
	83	code_log("generate_interrupt_exception:", ppc.generate_interrupt_exception, drc->cache_top);
61	84
62	85	ppc.generate_syscall_exception = drc->cache_top;
63	86	append_generate_exception(drc, EXCEPTION_SYSTEM_CALL);
	87	code_log("generate_syscall_exception:", ppc.generate_syscall_exception, drc->cache_top);
64	88
65	89	ppc.generate_decrementer_exception = drc->cache_top;
66	90	append_generate_exception(drc, EXCEPTION_DECREMENTER);
	91	code_log("generate_decrementer_exception:", ppc.generate_decrementer_exception, drc->cache_top);
67	92
68	93	ppc.generate_trap_exception = drc->cache_top;
69	94	append_generate_exception(drc, EXCEPTION_TRAP);
	95	code_log("generate_trap_exception:", ppc.generate_trap_exception, drc->cache_top);
70	96
71	97	ppc.generate_dsi_exception = drc->cache_top;
72	98	append_generate_exception(drc, EXCEPTION_DSI);
	99	code_log("generate_dsi_exception:", ppc.generate_dsi_exception, drc->cache_top);
73	100
74	101	ppc.generate_isi_exception = drc->cache_top;
75	102	append_generate_exception(drc, EXCEPTION_ISI);
	103	code_log("generate_isi_exception:", ppc.generate_isi_exception, drc->cache_top);
76	104
77	105	if (!ppc.is603 && !ppc.is602)
78	106	{
79	107	ppc.generate_fit_exception = drc->cache_top;
80	108	append_generate_exception(drc, EXCEPTION_FIXED_INTERVAL_TIMER);
	109	code_log("generate_fit_exception:", ppc.generate_fit_exception, drc->cache_top);
81	110	}
82	111	}
83	112
r949	r950
107	136	static void ppcdrc_recompile(drc_core *drc)
108	137	{
109	138	int remaining = MAX_INSTRUCTIONS;
	139	x86code *start = drc->cache_top;
110	140	UINT32 pc = ppc.pc;
111	141	UINT32 *opptr;
112	142
	143	(void)start;
	144
113	145	/* begin the sequence */
114	146	drc_begin_sequence(drc, pc);
	147	code_log_reset();
115	148
116	149	/* loose verification case: one verification here only */
117	150	if (!(ppc.drcoptions & PPCDRC_OPTIONS_CHECK_SELFMOD_CODE))
r949	r950
146	179
147	180	/* end the sequence */
148	181	drc_end_sequence(drc);
149		log_code(drc);
	182
	183	#if LOG_CODE
	184	{
	185	char label[40];
	186	sprintf(label, "Code @ %08X", ppc.pc);
	187	code_log(label, start, drc->cache_top);
150	188	}
	189	#endif
	190	}
151	191
152	192	static void update_counters(drc_core *drc)
153	193	{
154		link_info link1;
	194	emit_link link1;
155	195
156	196	/* decrementer */
157	197	if (ppc.is603 \|\| ppc.is602)
158	198	{
159		_cmp_r32_m32abs(REG_EBP, &ppc_dec_trigger_cycle);
160		_jcc_short_link(COND_NZ, &link1);
161		_or_m32abs_imm(&ppc.exception_pending, 0x2);
162		_resolve_link(&link1);
	199	emit_cmp_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_dec_trigger_cycle));
	200	emit_jcc_short_link(DRCTOP, COND_NZ, &link1);
	201	emit_or_m32_imm(DRCTOP, MABS(&ppc.exception_pending), 0x2);
	202	resolve_link(DRCTOP, &link1);
163	203	}
164	204
165	205	/* FIT */
166	206	if (!ppc.is603 && !ppc.is602)
167	207	{
168		link_info link2;
169		_cmp_r32_m32abs(REG_EBP, &ppc_fit_trigger_cycle);
170		_jcc_short_link(COND_NZ, &link1);
171		_cmp_r32_m32abs(REG_EBP, &ppc.fit_int_enable);
172		_jcc_short_link(COND_Z, &link2);
173		_or_m32abs_imm(&ppc.exception_pending, 0x4);
174		_resolve_link(&link1);
175		_resolve_link(&link2);
	208	emit_link link2;
	209	emit_cmp_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_fit_trigger_cycle));
	210	emit_jcc_short_link(DRCTOP, COND_NZ, &link1);
	211	emit_cmp_r32_m32(DRCTOP, REG_EBP, MABS(&ppc.fit_int_enable));
	212	emit_jcc_short_link(DRCTOP, COND_Z, &link2);
	213	emit_or_m32_imm(DRCTOP, MABS(&ppc.exception_pending), 0x4);
	214	resolve_link(DRCTOP, &link1);
	215	resolve_link(DRCTOP, &link2);
176	216	}
177	217	}
178	218
179	219	static void ppcdrc_entrygen(drc_core *drc)
180	220	{
181		_mov_m32~~abs~~_r32(&ppc.host_esp, REG_ESP);
	221	emit_mov_m32_r32(DRCTOP, MABS(&ppc.host_esp), REG_ESP);
182	222	append_check_interrupts(drc, 0);
183	223	}
184	224
r949	r950
204	244	if (!opptr)
205	245	{
206	246	/* first check to see if the code is up to date; if not, recompile */
207		_push_imm(pc);
208		_call(ppcdrc_getopptr);
209		_add_r32_imm(REG_ESP, 4);
210		_cmp_r32_imm(REG_EAX, 0);
211		_jcc(COND_NZ, drc->recompile);
	247	emit_push_imm(DRCTOP, pc);
	248	emit_call(DRCTOP, (x86code *)ppcdrc_getopptr);
	249	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	250	emit_cmp_r32_imm(DRCTOP, REG_EAX, 0);
	251	emit_jcc(DRCTOP, COND_NZ, drc->recompile);
212	252
213	253	/* code is up to date; do the exception */
214		_mov_m32abs_r32(&SRR0, REG_EDI); /* save return address */
215		_mov_r32_m32abs(REG_EAX, &ppc.generate_isi_exception);
216		_jmp_r32(REG_EAX);
	254	emit_mov_m32_r32(DRCTOP, MABS(&SRR0), REG_EDI); /* save return address */
	255	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.generate_isi_exception));
	256	emit_jmp_r32(DRCTOP, REG_EAX);
217	257	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
218	258	}
219	259
r949	r950
250	290
251	291	opcode = *opptr;
252	292
	293	code_log_add_entry(pc, opcode, drc->cache_top);
	294
253	295	if (opcode != 0) { // this is a little workaround for VF3
254	296	switch(opcode >> 26)
255	297	{
r949	r950
273	315
274	316	static void append_generate_exception(drc_core *drc, UINT8 exception)
275	317	{
276		link_info link1, link2, link3;
	318	emit_link link1, link2, link3;
277	319
278		_mov_r32_m32abs(REG_EAX, &ppc.msr);
279		_and_r32_imm(REG_EAX, 0xff73);
280		_mov_m32abs_r32(&SRR1, REG_EAX);
281		_mov_r32_m32abs(REG_EAX, &ppc.msr);
	320	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.msr));
	321	emit_and_r32_imm(DRCTOP, REG_EAX, 0xff73);
	322	emit_mov_m32_r32(DRCTOP, MABS(&SRR1), REG_EAX);
	323	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.msr));
282	324
283	325	// Clear POW, EE, PR, FP, FE0, SE, BE, FE1, IR, DR, RI
284		_and_r32_imm(REG_EAX, ~(MSR_POW \| MSR_EE \| MSR_PR \| MSR_FP \| MSR_FE0 \| MSR_SE \| MSR_BE \| MSR_FE1 \| MSR_IR \| MSR_DR \| MSR_RI));
	326	emit_and_r32_imm(DRCTOP, REG_EAX, ~(MSR_POW \| MSR_EE \| MSR_PR \| MSR_FP \| MSR_FE0 \| MSR_SE \| MSR_BE \| MSR_FE1 \| MSR_IR \| MSR_DR \| MSR_RI));
285	327	// Set LE to ILE
286		_and_r32_imm(REG_EAX, ~MSR_LE); // clear LE first
287		_test_r32_imm(REG_EAX, MSR_ILE);
288		_jcc_short_link(COND_Z, &link1); // if Z == 0, bit == 1
289		_or_r32_imm(REG_EAX, MSR_LE); // set LE
290		_resolve_link(&link1);
291		_mov_m32abs_r32(&ppc_icount, REG_EBP);
292		_push_r32(REG_EAX);
293		_call((genf *)ppc_set_msr);
294		_pop_r32(REG_EDX);
295		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	328	emit_and_r32_imm(DRCTOP, REG_EAX, ~MSR_LE); // clear LE first
	329	emit_test_r32_imm(DRCTOP, REG_EAX, MSR_ILE);
	330	emit_jcc_short_link(DRCTOP, COND_Z, &link1); // if Z == 0, bit == 1
	331	emit_or_r32_imm(DRCTOP, REG_EAX, MSR_LE); // set LE
	332	resolve_link(DRCTOP, &link1);
	333	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	334	emit_push_r32(DRCTOP, REG_EAX);
	335	emit_call(DRCTOP, (x86code *)ppc_set_msr);
	336	emit_pop_r32(DRCTOP, REG_EDX);
	337	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
296	338
297	339	if (ppc.is603)
298	340	{
299		_mov_r32_imm(REG_EDI, exception_vector[exception]); // first move the exception handler offset
300		_test_r32_imm(REG_EDX, MSR_IP); // test if the base should be 0xfff0 or EVPR
301		_jcc_short_link(COND_Z, &link2); // if Z == 1, bit == 0 means base == 0x00000000
302		_or_r32_imm(REG_EDI, 0xfff00000); // else base == 0xfff00000
303		_resolve_link(&link2);
	341	emit_mov_r32_imm(DRCTOP, REG_EDI, exception_vector[exception]); // first move the exception handler offset
	342	emit_test_r32_imm(DRCTOP, REG_EDX, MSR_IP); // test if the base should be 0xfff0 or EVPR
	343	emit_jcc_short_link(DRCTOP, COND_Z, &link2); // if Z == 1, bit == 0 means base == 0x00000000
	344	emit_or_r32_imm(DRCTOP, REG_EDI, 0xfff00000); // else base == 0xfff00000
	345	resolve_link(DRCTOP, &link2);
304	346	}
305	347	else if (ppc.is602)
306	348	{
307		_mov_r32_imm(REG_EDI, exception_vector[exception]); // first move the exception handler offset
308		_test_r32_imm(REG_EDX, MSR_IP); // test if the base should be 0xfff0 or IBR
309		_jcc_short_link(COND_NZ, &link2); // if Z == 0, bit == 1 means base == 0xfff00000
310		_or_r32_m32abs(REG_EDI, &ppc.ibr); // else base == IBR
311		_jmp_short_link(&link3);
312		_resolve_link(&link2);
313		_or_r32_imm(REG_EDI, 0xfff00000);
314		_resolve_link(&link3);
	349	emit_mov_r32_imm(DRCTOP, REG_EDI, exception_vector[exception]); // first move the exception handler offset
	350	emit_test_r32_imm(DRCTOP, REG_EDX, MSR_IP); // test if the base should be 0xfff0 or IBR
	351	emit_jcc_short_link(DRCTOP, COND_NZ, &link2); // if Z == 0, bit == 1 means base == 0xfff00000
	352	emit_or_r32_m32(DRCTOP, REG_EDI, MABS(&ppc.ibr)); // else base == IBR
	353	emit_jmp_short_link(DRCTOP, &link3);
	354	resolve_link(DRCTOP, &link2);
	355	emit_or_r32_imm(DRCTOP, REG_EDI, 0xfff00000);
	356	resolve_link(DRCTOP, &link3);
315	357	}
316	358	else
317	359	{
318		_mov_r32_imm(REG_EDI, exception_vector[exception]); // first move the exception handler offset
319		_test_r32_imm(REG_EDX, MSR_IP); // test if the base should be 0xfff0 or EVPR
320		_jcc_short_link(COND_NZ, &link2); // if Z == 0, bit == 1 means base == 0xfff00000
321		_or_r32_m32abs(REG_EDI, &EVPR); // else base == EVPR
322		_jmp_short_link(&link3);
323		_resolve_link(&link2);
324		_or_r32_imm(REG_EDI, 0xfff00000);
325		_resolve_link(&link3);
	360	emit_mov_r32_imm(DRCTOP, REG_EDI, exception_vector[exception]); // first move the exception handler offset
	361	emit_test_r32_imm(DRCTOP, REG_EDX, MSR_IP); // test if the base should be 0xfff0 or EVPR
	362	emit_jcc_short_link(DRCTOP, COND_NZ, &link2); // if Z == 0, bit == 1 means base == 0xfff00000
	363	emit_or_r32_m32(DRCTOP, REG_EDI, MABS(&EVPR)); // else base == EVPR
	364	emit_jmp_short_link(DRCTOP, &link3);
	365	resolve_link(DRCTOP, &link2);
	366	emit_or_r32_imm(DRCTOP, REG_EDI, 0xfff00000);
	367	resolve_link(DRCTOP, &link3);
326	368	}
327	369
328	370	if (exception == EXCEPTION_IRQ)
329	371	{
330		_and_m32~~abs~~_imm(&ppc.exception_pending, ~0x1); // clear pending irq
	372	emit_and_m32_imm(DRCTOP, MABS(&ppc.exception_pending), ~0x1); // clear pending irq
331	373	}
332	374	if (exception == EXCEPTION_DECREMENTER)
333	375	{
334		_and_m32~~abs~~_imm(&ppc.exception_pending, ~0x2); // clear pending decrementer exception
	376	emit_and_m32_imm(DRCTOP, MABS(&ppc.exception_pending), ~0x2); // clear pending decrementer exception
335	377	}
336	378	if (exception == EXCEPTION_FIXED_INTERVAL_TIMER)
337	379	{
338		_and_m32~~abs~~_imm(&ppc.exception_pending, ~0x4); // clear pending fit exception
	380	emit_and_m32_imm(DRCTOP, MABS(&ppc.exception_pending), ~0x4); // clear pending fit exception
339	381	}
340	382
341	383	drc_append_dispatcher(drc);
r949	r950
345	387	{
346	388	if (ppc.is602 \|\| ppc.is603)
347	389	{
348		link_info link1, link2, link3, link4;
349		_test_m32abs_imm(&ppc.msr, MSR_EE); /* no interrupt if external interrupts are not enabled */
350		_jcc_short_link(COND_Z, &link1); /* ZF = 1 if bit == 0 */
	390	emit_link link1, link2, link3, link4;
	391	emit_test_m32_imm(DRCTOP, MABS(&ppc.msr), MSR_EE); /* no interrupt if external interrupts are not enabled */
	392	emit_jcc_short_link(DRCTOP, COND_Z, &link1); /* ZF = 1 if bit == 0 */
351	393
352	394	/* else check if any interrupt are pending */
353		_mov_r32_m32abs(REG_EAX, &ppc.exception_pending);
354		_cmp_r32_imm(REG_EAX, 0);
355		_jcc_short_link(COND_Z, &link2); /* reg == 0, no exceptions are pending */
	395	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.exception_pending));
	396	emit_cmp_r32_imm(DRCTOP, REG_EAX, 0);
	397	emit_jcc_short_link(DRCTOP, COND_Z, &link2); /* reg == 0, no exceptions are pending */
356	398
357	399	/* else handle the first pending exception */
358		_test_r32_imm(REG_EAX, 0x1); /* is it a IRQ? */
359		_jcc_short_link(COND_Z, &link3);
	400	emit_test_r32_imm(DRCTOP, REG_EAX, 0x1); /* is it a IRQ? */
	401	emit_jcc_short_link(DRCTOP, COND_Z, &link3);
360	402
361		_mov_m32abs_r32(&SRR0, REG_EDI); /* save return address */
362		_mov_r32_m32abs(REG_EAX, &ppc.generate_interrupt_exception);
363		_jmp_r32(REG_EAX);
364		_resolve_link(&link3);
	403	emit_mov_m32_r32(DRCTOP, MABS(&SRR0), REG_EDI); /* save return address */
	404	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.generate_interrupt_exception));
	405	emit_jmp_r32(DRCTOP, REG_EAX);
	406	resolve_link(DRCTOP, &link3);
365	407
366		_test_r32_imm(REG_EAX, 0x2); /* is it a decrementer exception */
367		_jcc_short_link(COND_Z, &link4);
368		_mov_m32abs_r32(&SRR0, REG_EDI); /* save return address */
369		_mov_r32_m32abs(REG_EAX, &ppc.generate_decrementer_exception);
370		_jmp_r32(REG_EAX);
371		_resolve_link(&link4);
	408	emit_test_r32_imm(DRCTOP, REG_EAX, 0x2); /* is it a decrementer exception */
	409	emit_jcc_short_link(DRCTOP, COND_Z, &link4);
	410	emit_mov_m32_r32(DRCTOP, MABS(&SRR0), REG_EDI); /* save return address */
	411	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.generate_decrementer_exception));
	412	emit_jmp_r32(DRCTOP, REG_EAX);
	413	resolve_link(DRCTOP, &link4);
372	414
373		_resolve_link(&link1);
374		_resolve_link(&link2);
	415	resolve_link(DRCTOP, &link1);
	416	resolve_link(DRCTOP, &link2);
375	417	}
376	418	else
377	419	{
378		link_info link1, link2, link3, link4, link5, link6;
379		_test_m32abs_imm(&ppc.msr, MSR_EE); /* no interrupt if external interrupts are not enabled */
380		_jcc_short_link(COND_Z, &link1); /* ZF = 1 if bit == 0 */
	420	emit_link link1, link2, link3, link4, link5, link6;
	421	emit_test_m32_imm(DRCTOP, MABS(&ppc.msr), MSR_EE); /* no interrupt if external interrupts are not enabled */
	422	emit_jcc_short_link(DRCTOP, COND_Z, &link1); /* ZF = 1 if bit == 0 */
381	423
382	424	/* else check if any interrupt are pending */
383		_mov_r32_m32abs(REG_EAX, &ppc.exception_pending);
384		_cmp_r32_imm(REG_EAX, 0);
385		_jcc_short_link(COND_Z, &link2); /* reg == 0, no exceptions are pending */
	425	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.exception_pending));
	426	emit_cmp_r32_imm(DRCTOP, REG_EAX, 0);
	427	emit_jcc_short_link(DRCTOP, COND_Z, &link2); /* reg == 0, no exceptions are pending */
386	428
387	429	/* else handle the first pending exception */
388		_test_r32_imm(REG_EAX, 0x1); /* is it a IRQ? */
389		_jcc_short_link(COND_Z, &link3);
	430	emit_test_r32_imm(DRCTOP, REG_EAX, 0x1); /* is it a IRQ? */
	431	emit_jcc_short_link(DRCTOP, COND_Z, &link3);
390	432
391		_mov_r32_m32abs(REG_EAX, &ppc.exisr);
392		_and_r32_m32abs(REG_EAX, &ppc.exier);
393		_cmp_r32_imm(REG_EAX, 0);
394		_jcc_short_link(COND_Z, &link4);
	433	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.exisr));
	434	emit_and_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.exier));
	435	emit_cmp_r32_imm(DRCTOP, REG_EAX, 0);
	436	emit_jcc_short_link(DRCTOP, COND_Z, &link4);
395	437
396		_mov_m32abs_r32(&SRR0, REG_EDI); /* save return address */
397		_mov_r32_m32abs(REG_EAX, &ppc.generate_interrupt_exception);
398		_jmp_r32(REG_EAX);
	438	emit_mov_m32_r32(DRCTOP, MABS(&SRR0), REG_EDI); /* save return address */
	439	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.generate_interrupt_exception));
	440	emit_jmp_r32(DRCTOP, REG_EAX);
399	441
400	442	/* check if it's FIT exception */
401		_resolve_link(&link3);
402		_test_r32_imm(REG_EAX, 0x4);
403		_jcc_short_link(COND_Z, &link5);
	443	resolve_link(DRCTOP, &link3);
	444	emit_test_r32_imm(DRCTOP, REG_EAX, 0x4);
	445	emit_jcc_short_link(DRCTOP, COND_Z, &link5);
404	446
405	447	// check if FIT interrupts are enabled
406		_test_m32abs_imm(&ppc.fit_int_enable, 0x1);
407		_jcc_short_link(COND_Z, &link6);
	448	emit_test_m32_imm(DRCTOP, MABS(&ppc.fit_int_enable), 0x1);
	449	emit_jcc_short_link(DRCTOP, COND_Z, &link6);
408	450
409	451	// calculate the next trigger cycle for FIT
410		_mov_r32_m32abs(REG_EAX, &ppc_fit_trigger_cycle);
411		_sub_r32_m32abs(REG_EAX, &ppc.fit_bit);
412		_mov_m32abs_r32(&ppc_fit_trigger_cycle, REG_EAX);
	452	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc_fit_trigger_cycle));
	453	emit_sub_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.fit_bit));
	454	emit_mov_m32_r32(DRCTOP, MABS(&ppc_fit_trigger_cycle), REG_EAX);
413	455
414		_mov_m32abs_r32(&SRR0, REG_EDI); /* save return address */
415		_mov_r32_m32abs(REG_EAX, &ppc.generate_fit_exception);
416		_jmp_r32(REG_EAX);
	456	emit_mov_m32_r32(DRCTOP, MABS(&SRR0), REG_EDI); /* save return address */
	457	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.generate_fit_exception));
	458	emit_jmp_r32(DRCTOP, REG_EAX);
417	459
418		_resolve_link(&link1);
419		_resolve_link(&link2);
420		_resolve_link(&link4);
421		_resolve_link(&link5);
422		_resolve_link(&link6);
	460	resolve_link(DRCTOP, &link1);
	461	resolve_link(DRCTOP, &link2);
	462	resolve_link(DRCTOP, &link4);
	463	resolve_link(DRCTOP, &link5);
	464	resolve_link(DRCTOP, &link6);
423	465	}
424	466	}
425	467
426	468	static void append_branch_or_dispatch(drc_core *drc, UINT32 newpc, int cycles)
427	469	{
428	470	void *code = drc_get_code_at_pc(drc, newpc);
429		_mov_r32_imm(REG_EDI, newpc);
	471	emit_mov_r32_imm(DRCTOP, REG_EDI, newpc);
430	472
431	473	update_counters(drc);
432	474	append_check_interrupts(drc, 0);
r949	r950
435	477
436	478
437	479	if (code)
438		_jmp(code);
	480	emit_jmp(DRCTOP, code);
439	481	else
440	482	drc_append_tentative_fixed_dispatcher(drc, newpc);
441	483	}
r949	r950
454	496	// expects the result value in EDX!!!
455	497	static void append_set_cr0(drc_core *drc)
456	498	{
457		_xor_r32_r32(REG_EBX, REG_EBX);
458		_xor_r32_r32(REG_EAX, REG_EAX);
459		_cmp_r32_imm(REG_EDX, 0);
	499	emit_xor_r32_r32(DRCTOP, REG_EBX, REG_EBX);
	500	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	501	emit_cmp_r32_imm(DRCTOP, REG_EDX, 0);
460	502	/*_lahf();
461	503
462	504	_shr_r32_imm(REG_EAX, 14);
463	505
464	506	_add_r32_imm(REG_EAX, &condition_table);
465		_mov_r8_m8bd(REG_BL, REG_EAX, 0);
	507	_mov_r8_m8(REG_BL, MBD(REG_EAX, 0));
466	508	*/
467	509
468		_setcc_r8(COND_Z, REG_AL);
469		_setcc_r8(COND_L, REG_AH);
470		_setcc_r8(COND_G, REG_BL);
471		_shl_r8_imm(REG_AL, 1);
472		_shl_r8_imm(REG_AH, 3);
473		_shl_r8_imm(REG_BL, 2);
474		_or_r8_r8(REG_BL, REG_AH);
475		_or_r8_r8(REG_BL, REG_AL);
	510	emit_setcc_r8(DRCTOP, COND_Z, REG_AL);
	511	emit_setcc_r8(DRCTOP, COND_L, REG_AH);
	512	emit_setcc_r8(DRCTOP, COND_G, REG_BL);
	513	emit_shl_r8_imm(DRCTOP, REG_AL, 1);
	514	emit_shl_r8_imm(DRCTOP, REG_AH, 3);
	515	emit_shl_r8_imm(DRCTOP, REG_BL, 2);
	516	emit_or_r8_r8(DRCTOP, REG_BL, REG_AH);
	517	emit_or_r8_r8(DRCTOP, REG_BL, REG_AL);
476	518
477		_bt_m32abs_imm(&XER, 31); // set XER SO bit to carry
478		_adc_r32_imm(REG_EBX, 0); // effectively sets bit 0 to carry
	519	emit_bt_m32_imm(DRCTOP, MABS(&XER), 31); // set XER SO bit to carry
	520	emit_adc_r32_imm(DRCTOP, REG_EBX, 0); // effectively sets bit 0 to carry
479	521
480		_mov_m8~~abs~~_r8(&ppc.cr[0], REG_BL);
	522	emit_mov_m8_r8(DRCTOP, MABS(&ppc.cr[0]), REG_BL);
481	523	}
482	524
483	525	static void append_set_cr1(drc_core *drc)
484	526	{
485		_mov_r32_m32abs(REG_EAX, &ppc.fpscr);
486		_shr_r32_imm(REG_EAX, 28);
487		_and_r32_imm(REG_EAX, 0xf);
488		_mov_m8abs_r8(&ppc.cr[1], REG_AL);
	527	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.fpscr));
	528	emit_shr_r32_imm(DRCTOP, REG_EAX, 28);
	529	emit_and_r32_imm(DRCTOP, REG_EAX, 0xf);
	530	emit_mov_m8_r8(DRCTOP, MABS(&ppc.cr[1]), REG_AL);
489	531	}
490	532
491	533	static UINT32 recompile_addx(drc_core *drc, UINT32 op)
492	534	{
493		_mov_r32_m32abs(REG_EDX, &REG(RA));
494		_add_r32_m32abs(REG_EDX, &REG(RB));
495		_mov_m32abs_r32(&REG(RT), REG_EDX);
	535	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	536	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	537	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
496	538
497	539	if (OEBIT) {
498	540	mame_printf_debug("recompile_addx: OE bit set !\n");
r949	r950
507	549
508	550	static UINT32 recompile_addcx(drc_core *drc, UINT32 op)
509	551	{
510		_xor_r32_r32(REG_EAX, REG_EAX);
511		_mov_r32_m32abs(REG_EBX, &XER);
512		_and_r32_imm(REG_EBX, ~0x20000000); // clear carry
513		_mov_r32_m32abs(REG_EDX, &REG(RA));
514		_add_r32_m32abs(REG_EDX, &REG(RB));
515		_mov_m32abs_r32(&REG(RT), REG_EDX);
	552	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	553	emit_mov_r32_m32(DRCTOP, REG_EBX, MABS(&XER));
	554	emit_and_r32_imm(DRCTOP, REG_EBX, ~0x20000000); // clear carry
	555	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	556	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	557	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
516	558
517		_setcc_r8(COND_C, REG_AL); // carry to AL
518		_shl_r32_imm(REG_EAX, 29); // shift to carry bit
519		_or_r32_r32(REG_EBX, REG_EAX);
520		_mov_m32abs_r32(&XER, REG_EBX);
	559	emit_setcc_r8(DRCTOP, COND_C, REG_AL); // carry to AL
	560	emit_shl_r32_imm(DRCTOP, REG_EAX, 29); // shift to carry bit
	561	emit_or_r32_r32(DRCTOP, REG_EBX, REG_EAX);
	562	emit_mov_m32_r32(DRCTOP, MABS(&XER), REG_EBX);
521	563
522	564	if (OEBIT) {
523	565	mame_printf_debug("recompile_addcx: OE bit set !\n");
r949	r950
532	574
533	575	static UINT32 recompile_addex(drc_core *drc, UINT32 op)
534	576	{
535		_mov_m32abs_r32(&ppc_icount, REG_EBP);
536		_push_imm(op);
537		_call((genf *)ppc_addex);
538		_add_r32_imm(REG_ESP, 4);
539		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	577	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	578	emit_push_imm(DRCTOP, op);
	579	emit_call(DRCTOP, (x86code *)ppc_addex);
	580	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	581	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
540	582	return RECOMPILE_SUCCESSFUL_CP(1,4);
541	583	}
542	584
r949	r950
544	586	{
545	587	if (RA == 0)
546	588	{
547		_mov_m32~~abs~~_imm(&REG(RT), SIMM16);
	589	emit_mov_m32_imm(DRCTOP, MABS(&REG(RT)), SIMM16);
548	590	}
549	591	else
550	592	{
551		_mov_r32_m32abs(REG_EAX, &REG(RA));
552		_add_r32_imm(REG_EAX, SIMM16);
553		_mov_m32abs_r32(&REG(RT), REG_EAX);
	593	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	594	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	595	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
554	596	}
555	597
556	598	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
558	600
559	601	static UINT32 recompile_addic(drc_core *drc, UINT32 op)
560	602	{
561		_xor_r32_r32(REG_EAX, REG_EAX);
562		_mov_r32_m32abs(REG_EBX, &XER);
563		_and_r32_imm(REG_EBX, ~0x20000000); // clear carry bit
564		_mov_r32_m32abs(REG_EDX, &REG(RA));
565		_add_r32_imm(REG_EDX, SIMM16);
566		_mov_m32abs_r32(&REG(RT), REG_EDX);
	603	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	604	emit_mov_r32_m32(DRCTOP, REG_EBX, MABS(&XER));
	605	emit_and_r32_imm(DRCTOP, REG_EBX, ~0x20000000); // clear carry bit
	606	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	607	emit_add_r32_imm(DRCTOP, REG_EDX, SIMM16);
	608	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
567	609
568		_setcc_r8(COND_C, REG_AL); // carry to AL
569		_shl_r32_imm(REG_EAX, 29); // shift to carry bit
570		_or_r32_r32(REG_EBX, REG_EAX);
571		_mov_m32abs_r32(&XER, REG_EBX);
	610	emit_setcc_r8(DRCTOP, COND_C, REG_AL); // carry to AL
	611	emit_shl_r32_imm(DRCTOP, REG_EAX, 29); // shift to carry bit
	612	emit_or_r32_r32(DRCTOP, REG_EBX, REG_EAX);
	613	emit_mov_m32_r32(DRCTOP, MABS(&XER), REG_EBX);
572	614
573	615	return RECOMPILE_SUCCESSFUL_CP(1,4);
574	616	}
575	617
576	618	static UINT32 recompile_addic_rc(drc_core *drc, UINT32 op)
577	619	{
578		_xor_r32_r32(REG_EAX, REG_EAX);
579		_mov_r32_m32abs(REG_EBX, &XER);
580		_and_r32_imm(REG_EBX, ~0x20000000); // clear carry bit
581		_mov_r32_m32abs(REG_EDX, &REG(RA));
582		_add_r32_imm(REG_EDX, SIMM16);
583		_mov_m32abs_r32(&REG(RT), REG_EDX);
	620	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	621	emit_mov_r32_m32(DRCTOP, REG_EBX, MABS(&XER));
	622	emit_and_r32_imm(DRCTOP, REG_EBX, ~0x20000000); // clear carry bit
	623	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	624	emit_add_r32_imm(DRCTOP, REG_EDX, SIMM16);
	625	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
584	626
585		_setcc_r8(COND_C, REG_AL); // carry to AL
586		_shl_r32_imm(REG_EAX, 29); // shift to carry bit
587		_or_r32_r32(REG_EBX, REG_EAX);
588		_mov_m32abs_r32(&XER, REG_EBX);
	627	emit_setcc_r8(DRCTOP, COND_C, REG_AL); // carry to AL
	628	emit_shl_r32_imm(DRCTOP, REG_EAX, 29); // shift to carry bit
	629	emit_or_r32_r32(DRCTOP, REG_EBX, REG_EAX);
	630	emit_mov_m32_r32(DRCTOP, MABS(&XER), REG_EBX);
589	631
590	632	append_set_cr0(drc);
591	633
r949	r950
596	638	{
597	639	if (RA == 0)
598	640	{
599		_mov_m32~~abs~~_imm(&REG(RT), UIMM16 << 16);
	641	emit_mov_m32_imm(DRCTOP, MABS(&REG(RT)), UIMM16 << 16);
600	642	}
601	643	else
602	644	{
603		_mov_r32_m32abs(REG_EAX, &REG(RA));
604		_add_r32_imm(REG_EAX, UIMM16 << 16);
605		_mov_m32abs_r32(&REG(RT), REG_EAX);
	645	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	646	emit_add_r32_imm(DRCTOP, REG_EAX, UIMM16 << 16);
	647	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
606	648	}
607	649
608	650	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
610	652
611	653	static UINT32 recompile_addmex(drc_core *drc, UINT32 op)
612	654	{
613		_mov_m32abs_r32(&ppc_icount, REG_EBP);
614		_push_imm(op);
615		_call((genf *)ppc_addmex);
616		_add_r32_imm(REG_ESP, 4);
617		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	655	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	656	emit_push_imm(DRCTOP, op);
	657	emit_call(DRCTOP, (x86code *)ppc_addmex);
	658	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	659	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
618	660	return RECOMPILE_SUCCESSFUL_CP(1,4);
619	661	}
620	662
621	663	static UINT32 recompile_addzex(drc_core *drc, UINT32 op)
622	664	{
623		_mov_m32abs_r32(&ppc_icount, REG_EBP);
624		_push_imm(op);
625		_call((genf *)ppc_addzex);
626		_add_r32_imm(REG_ESP, 4);
627		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	665	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	666	emit_push_imm(DRCTOP, op);
	667	emit_call(DRCTOP, (x86code *)ppc_addzex);
	668	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	669	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
628	670	return RECOMPILE_SUCCESSFUL_CP(1,4);
629	671	}
630	672
631	673	static UINT32 recompile_andx(drc_core *drc, UINT32 op)
632	674	{
633		_mov_r32_m32abs(REG_EDX, &REG(RS));
634		_and_r32_m32abs(REG_EDX, &REG(RB));
635		_mov_m32abs_r32(&REG(RA), REG_EDX);
	675	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	676	emit_and_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	677	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
636	678
637	679	if (RCBIT) {
638	680	append_set_cr0(drc);
r949	r950
643	685
644	686	static UINT32 recompile_andcx(drc_core *drc, UINT32 op)
645	687	{
646		_mov_r32_m32abs(REG_EDX, &REG(RS));
647		_mov_r32_m32abs(REG_EAX, &REG(RB));
648		_not_r32(REG_EAX);
649		_and_r32_r32(REG_EDX, REG_EAX);
650		_mov_m32abs_r32(&REG(RA), REG_EDX);
	688	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	689	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
	690	emit_not_r32(DRCTOP, REG_EAX);
	691	emit_and_r32_r32(DRCTOP, REG_EDX, REG_EAX);
	692	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
651	693
652	694	if (RCBIT) {
653	695	append_set_cr0(drc);
r949	r950
658	700
659	701	static UINT32 recompile_andi_rc(drc_core *drc, UINT32 op)
660	702	{
661		_mov_r32_m32abs(REG_EDX, &REG(RS));
662		_and_r32_imm(REG_EDX, UIMM16);
663		_mov_m32abs_r32(&REG(RA), REG_EDX);
	703	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	704	emit_and_r32_imm(DRCTOP, REG_EDX, UIMM16);
	705	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
664	706
665	707	append_set_cr0(drc);
666	708
r949	r950
669	711
670	712	static UINT32 recompile_andis_rc(drc_core *drc, UINT32 op)
671	713	{
672		_mov_r32_m32abs(REG_EDX, &REG(RS));
673		_and_r32_imm(REG_EDX, UIMM16 << 16);
674		_mov_m32abs_r32(&REG(RA), REG_EDX);
	714	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	715	emit_and_r32_imm(DRCTOP, REG_EDX, UIMM16 << 16);
	716	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
675	717
676	718	append_set_cr0(drc);
677	719
r949	r950
692	734	}
693	735
694	736	if( LKBIT ) {
695		_mov_m32~~abs~~_imm(&LR, temp_ppc_pc + 4);
	737	emit_mov_m32_imm(DRCTOP, MABS(&LR), temp_ppc_pc + 4);
696	738	}
697	739
698	740	append_branch_or_dispatch(drc, newpc, 1);
r949	r950
702	744
703	745	static UINT32 recompile_bcx(drc_core *drc, UINT32 op)
704	746	{
705		link_info link1 = {0}, link2 = {0};
	747	emit_link link1 = {0}, link2 = {0};
706	748	int do_link1 = 0, do_link2 = 0;
707	749	UINT32 newpc;
708	750
r949	r950
713	755	}
714	756
715	757	if( LKBIT ) {
716		_mov_m32~~abs~~_imm(&LR, temp_ppc_pc + 4);
	758	emit_mov_m32_imm(DRCTOP, MABS(&LR), temp_ppc_pc + 4);
717	759	}
718	760
719	761	if (BO == 20) /* condition is always true, so the basic block ends here */
r949	r950
729	771	{
730	772	do_link1 = 1;
731	773	//_dec_m32abs(&CTR);
732		_sub_m32~~abs~~_imm(&CTR, 1);
	774	emit_sub_m32_imm(DRCTOP, MABS(&CTR), 1);
733	775
734	776	// if BO[1] == 0, branch if CTR != 0
735	777	if ((BO & 0x2) == 0)
736	778	{
737		_jcc_near_link(COND_Z, &link1);
	779	emit_jcc_near_link(DRCTOP, COND_Z, &link1);
738	780	}
739	781	else
740	782	{
741		_jcc_near_link(COND_NZ, &link1);
	783	emit_jcc_near_link(DRCTOP, COND_NZ, &link1);
742	784	}
743	785	}
744	786
r949	r950
746	788	if ((BO & 0x10) == 0)
747	789	{
748	790	do_link2 = 1;
749		_movzx_r32_m8abs(REG_EAX, &ppc.cr[(BI)/4]);
750		_test_r32_imm(REG_EAX, 1 << (3 - ((BI) & 0x3))); // test if condition register bit is set
	791	emit_movzx_r32_m8(DRCTOP, REG_EAX, MABS(&ppc.cr[(BI)/4]));
	792	emit_test_r32_imm(DRCTOP, REG_EAX, 1 << (3 - ((BI) & 0x3))); // test if condition register bit is set
751	793
752	794	// if BO[3] == 0, branch if condition == FALSE (bit zero)
753	795	if ((BO & 0x8) == 0)
754	796	{
755		_jcc_near_link(COND_NZ, &link2); // bit not zero, skip branch
	797	emit_jcc_near_link(DRCTOP, COND_NZ, &link2); // bit not zero, skip branch
756	798	}
757	799	// if BO[3] == 1, branch if condition == TRUE (bit not zero)
758	800	else
759	801	{
760		_jcc_near_link(COND_Z, &link2); // bit zero, skip branch
	802	emit_jcc_near_link(DRCTOP, COND_Z, &link2); // bit zero, skip branch
761	803	}
762	804	}
763	805
r949	r950
766	808
767	809	// skip the branch
768	810	if (do_link1) {
769		_resolve_link(&link1);
	811	resolve_link(DRCTOP, &link1);
770	812	}
771	813	if (do_link2) {
772		_resolve_link(&link2);
	814	resolve_link(DRCTOP, &link2);
773	815	}
774	816
775	817	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
778	820
779	821	static UINT32 recompile_bcctrx(drc_core *drc, UINT32 op)
780	822	{
781		link_info link1 = {0} ,link2 = {0};
	823	emit_link link1 = {0} ,link2 = {0};
782	824	int do_link1 = 0, do_link2 = 0;
783	825
784	826	if (BO == 20) /* condition is always true, so the basic block ends here */
785	827	{
786		_mov_r32_m32~~abs~~(REG_EDI, &CTR); // mov edi, CTR
	828	emit_mov_r32_m32(DRCTOP, REG_EDI, MABS(&CTR)); // mov edi, CTR
787	829
788	830	if( LKBIT ) {
789		_mov_m32~~abs~~_imm(&LR, temp_ppc_pc + 4);
	831	emit_mov_m32_imm(DRCTOP, MABS(&LR), temp_ppc_pc + 4);
790	832	}
791	833	return RECOMPILE_SUCCESSFUL_CP(1,0) \| RECOMPILE_END_OF_STRING \| RECOMPILE_ADD_DISPATCH;
792	834	}
r949	r950
797	839	{
798	840	do_link1 = 1;
799	841	//_dec_m32abs(&CTR);
800		_sub_m32~~abs~~_imm(&CTR, 1);
	842	emit_sub_m32_imm(DRCTOP, MABS(&CTR), 1);
801	843
802	844	// if BO[1] == 0, branch if CTR != 0
803	845	if ((BO & 0x2) == 0)
804	846	{
805		_jcc_near_link(COND_Z, &link1);
	847	emit_jcc_near_link(DRCTOP, COND_Z, &link1);
806	848	}
807	849	else
808	850	{
809		_jcc_near_link(COND_NZ, &link1);
	851	emit_jcc_near_link(DRCTOP, COND_NZ, &link1);
810	852	}
811	853	}
812	854
r949	r950
814	856	if ((BO & 0x10) == 0)
815	857	{
816	858	do_link2 = 1;
817		_movzx_r32_m8abs(REG_EAX, &ppc.cr[(BI)/4]);
818		_test_r32_imm(REG_EAX, 1 << (3 - ((BI) & 0x3))); // test if condition register bit is set
	859	emit_movzx_r32_m8(DRCTOP, REG_EAX, MABS(&ppc.cr[(BI)/4]));
	860	emit_test_r32_imm(DRCTOP, REG_EAX, 1 << (3 - ((BI) & 0x3))); // test if condition register bit is set
819	861
820	862	// if BO[3] == 0, branch if condition == FALSE (bit zero)
821	863	if ((BO & 0x8) == 0)
822	864	{
823		_jcc_near_link(COND_NZ, &link2); // bit not zero, skip branch
	865	emit_jcc_near_link(DRCTOP, COND_NZ, &link2); // bit not zero, skip branch
824	866	}
825	867	// if BO[3] == 1, branch if condition == TRUE (bit not zero)
826	868	else
827	869	{
828		_jcc_near_link(COND_Z, &link2); // bit zero, skip branch
	870	emit_jcc_near_link(DRCTOP, COND_Z, &link2); // bit zero, skip branch
829	871	}
830	872	}
831	873
832	874	// take the branch
833		_mov_r32_m32~~abs~~(REG_EDI, &CTR); // mov edi, CTR
	875	emit_mov_r32_m32(DRCTOP, REG_EDI, MABS(&CTR)); // mov edi, CTR
834	876	if( LKBIT ) {
835		_mov_m32~~abs~~_imm(&LR, temp_ppc_pc + 4);
	877	emit_mov_m32_imm(DRCTOP, MABS(&LR), temp_ppc_pc + 4);
836	878	}
837	879	append_check_interrupts(drc, 0);
838	880	drc_append_standard_epilogue(drc, 1, 0, 1);
r949	r950
840	882
841	883	// skip the branch
842	884	if (do_link1) {
843		_resolve_link(&link1);
	885	resolve_link(DRCTOP, &link1);
844	886	}
845	887	if (do_link2) {
846		_resolve_link(&link2);
	888	resolve_link(DRCTOP, &link2);
847	889	}
848	890	if( LKBIT ) {
849		_mov_m32~~abs~~_imm(&LR, temp_ppc_pc + 4);
	891	emit_mov_m32_imm(DRCTOP, MABS(&LR), temp_ppc_pc + 4);
850	892	}
851	893
852	894	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
855	897
856	898	static UINT32 recompile_bclrx(drc_core *drc, UINT32 op)
857	899	{
858		link_info link1 = {0}, link2 = {0};
	900	emit_link link1 = {0}, link2 = {0};
859	901	int do_link1 = 0, do_link2 = 0;
860	902
861	903	if (BO == 20) /* condition is always true, so the basic block ends here */
862	904	{
863		_mov_r32_m32~~abs~~(REG_EDI, &LR); // mov edi, LR
	905	emit_mov_r32_m32(DRCTOP, REG_EDI, MABS(&LR)); // mov edi, LR
864	906
865	907	if( LKBIT ) {
866		_mov_m32~~abs~~_imm(&LR, temp_ppc_pc + 4);
	908	emit_mov_m32_imm(DRCTOP, MABS(&LR), temp_ppc_pc + 4);
867	909	}
868	910	return RECOMPILE_SUCCESSFUL_CP(1,0) \| RECOMPILE_END_OF_STRING \| RECOMPILE_ADD_DISPATCH;
869	911	}
r949	r950
874	916	{
875	917	do_link1 = 1;
876	918	//_dec_m32abs(&CTR);
877		_sub_m32~~abs~~_imm(&CTR, 1);
	919	emit_sub_m32_imm(DRCTOP, MABS(&CTR), 1);
878	920
879	921	// if BO[1] == 0, branch if CTR != 0
880	922	if ((BO & 0x2) == 0)
881	923	{
882		_jcc_near_link(COND_Z, &link1);
	924	emit_jcc_near_link(DRCTOP, COND_Z, &link1);
883	925	}
884	926	else
885	927	{
886		_jcc_near_link(COND_NZ, &link1);
	928	emit_jcc_near_link(DRCTOP, COND_NZ, &link1);
887	929	}
888	930	}
889	931
r949	r950
891	933	if ((BO & 0x10) == 0)
892	934	{
893	935	do_link2 = 1;
894		_movzx_r32_m8abs(REG_EAX, &ppc.cr[(BI)/4]);
895		_test_r32_imm(REG_EAX, 1 << (3 - ((BI) & 0x3))); // test if condition register bit is set
	936	emit_movzx_r32_m8(DRCTOP, REG_EAX, MABS(&ppc.cr[(BI)/4]));
	937	emit_test_r32_imm(DRCTOP, REG_EAX, 1 << (3 - ((BI) & 0x3))); // test if condition register bit is set
896	938
897	939	// if BO[3] == 0, branch if condition == FALSE (bit zero)
898	940	if ((BO & 0x8) == 0)
899	941	{
900		_jcc_near_link(COND_NZ, &link2); // bit not zero, skip branch
	942	emit_jcc_near_link(DRCTOP, COND_NZ, &link2); // bit not zero, skip branch
901	943	}
902	944	// if BO[3] == 1, branch if condition == TRUE (bit not zero)
903	945	else
904	946	{
905		_jcc_near_link(COND_Z, &link2); // bit zero, skip branch
	947	emit_jcc_near_link(DRCTOP, COND_Z, &link2); // bit zero, skip branch
906	948	}
907	949	}
908	950
909	951	// take the branch
910		_mov_r32_m32~~abs~~(REG_EDI, &LR); // mov edi, LR
	952	emit_mov_r32_m32(DRCTOP, REG_EDI, MABS(&LR)); // mov edi, LR
911	953	if( LKBIT ) {
912		_mov_m32~~abs~~_imm(&LR, temp_ppc_pc + 4);
	954	emit_mov_m32_imm(DRCTOP, MABS(&LR), temp_ppc_pc + 4);
913	955	}
914	956	append_check_interrupts(drc, 0);
915	957	drc_append_standard_epilogue(drc, 1, 0, 1);
r949	r950
917	959
918	960	// skip the branch
919	961	if (do_link1) {
920		_resolve_link(&link1);
	962	resolve_link(DRCTOP, &link1);
921	963	}
922	964	if (do_link2) {
923		_resolve_link(&link2);
	965	resolve_link(DRCTOP, &link2);
924	966	}
925	967	if( LKBIT ) {
926		_mov_m32~~abs~~_imm(&LR, temp_ppc_pc + 4);
	968	emit_mov_m32_imm(DRCTOP, MABS(&LR), temp_ppc_pc + 4);
927	969	}
928	970
929	971	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
932	974
933	975	static UINT32 recompile_cmp(drc_core *drc, UINT32 op)
934	976	{
935		_xor_r32_r32(REG_EAX, REG_EAX);
936		_xor_r32_r32(REG_EBX, REG_EBX);
937		_mov_r32_m32abs(REG_ECX, &REG(RA));
938		_cmp_r32_m32abs(REG_ECX, &REG(RB));
	977	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	978	emit_xor_r32_r32(DRCTOP, REG_EBX, REG_EBX);
	979	emit_mov_r32_m32(DRCTOP, REG_ECX, MABS(&REG(RA)));
	980	emit_cmp_r32_m32(DRCTOP, REG_ECX, MABS(&REG(RB)));
939	981
940		_setcc_r8(COND_Z, REG_AL);
941		_setcc_r8(COND_L, REG_AH);
942		_setcc_r8(COND_G, REG_BL);
943		_shl_r8_imm(REG_AL, 1);
944		_shl_r8_imm(REG_AH, 3);
945		_shl_r8_imm(REG_BL, 2);
946		_or_r8_r8(REG_BL, REG_AH);
947		_or_r8_r8(REG_BL, REG_AL);
	982	emit_setcc_r8(DRCTOP, COND_Z, REG_AL);
	983	emit_setcc_r8(DRCTOP, COND_L, REG_AH);
	984	emit_setcc_r8(DRCTOP, COND_G, REG_BL);
	985	emit_shl_r8_imm(DRCTOP, REG_AL, 1);
	986	emit_shl_r8_imm(DRCTOP, REG_AH, 3);
	987	emit_shl_r8_imm(DRCTOP, REG_BL, 2);
	988	emit_or_r8_r8(DRCTOP, REG_BL, REG_AH);
	989	emit_or_r8_r8(DRCTOP, REG_BL, REG_AL);
948	990
949		_bt_m32abs_imm(&XER, 31); // set XER SO bit to carry
950		_adc_r32_imm(REG_EBX, 0); // effectively sets bit 0 to carry
951		_mov_m8abs_r8(&ppc.cr[CRFD], REG_BL);
	991	emit_bt_m32_imm(DRCTOP, MABS(&XER), 31); // set XER SO bit to carry
	992	emit_adc_r32_imm(DRCTOP, REG_EBX, 0); // effectively sets bit 0 to carry
	993	emit_mov_m8_r8(DRCTOP, MABS(&ppc.cr[CRFD]), REG_BL);
952	994
953	995	return RECOMPILE_SUCCESSFUL_CP(1,4);
954	996	}
955	997
956	998	static UINT32 recompile_cmpi(drc_core *drc, UINT32 op)
957	999	{
958		_xor_r32_r32(REG_EAX, REG_EAX);
959		_xor_r32_r32(REG_EBX, REG_EBX);
960		_mov_r32_m32abs(REG_ECX, &REG(RA));
961		_cmp_r32_imm(REG_ECX, SIMM16);
	1000	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	1001	emit_xor_r32_r32(DRCTOP, REG_EBX, REG_EBX);
	1002	emit_mov_r32_m32(DRCTOP, REG_ECX, MABS(&REG(RA)));
	1003	emit_cmp_r32_imm(DRCTOP, REG_ECX, SIMM16);
962	1004
963		_setcc_r8(COND_Z, REG_AL);
964		_setcc_r8(COND_L, REG_AH);
965		_setcc_r8(COND_G, REG_BL);
966		_shl_r8_imm(REG_AL, 1);
967		_shl_r8_imm(REG_AH, 3);
968		_shl_r8_imm(REG_BL, 2);
969		_or_r8_r8(REG_BL, REG_AH);
970		_or_r8_r8(REG_BL, REG_AL);
	1005	emit_setcc_r8(DRCTOP, COND_Z, REG_AL);
	1006	emit_setcc_r8(DRCTOP, COND_L, REG_AH);
	1007	emit_setcc_r8(DRCTOP, COND_G, REG_BL);
	1008	emit_shl_r8_imm(DRCTOP, REG_AL, 1);
	1009	emit_shl_r8_imm(DRCTOP, REG_AH, 3);
	1010	emit_shl_r8_imm(DRCTOP, REG_BL, 2);
	1011	emit_or_r8_r8(DRCTOP, REG_BL, REG_AH);
	1012	emit_or_r8_r8(DRCTOP, REG_BL, REG_AL);
971	1013
972		_bt_m32abs_imm(&XER, 31); // set XER SO bit to carry
973		_adc_r32_imm(REG_EBX, 0); // effectively sets bit 0 to carry
974		_mov_m8abs_r8(&ppc.cr[CRFD], REG_BL);
	1014	emit_bt_m32_imm(DRCTOP, MABS(&XER), 31); // set XER SO bit to carry
	1015	emit_adc_r32_imm(DRCTOP, REG_EBX, 0); // effectively sets bit 0 to carry
	1016	emit_mov_m8_r8(DRCTOP, MABS(&ppc.cr[CRFD]), REG_BL);
975	1017
976	1018	return RECOMPILE_SUCCESSFUL_CP(1,4);
977	1019	}
978	1020
979	1021	static UINT32 recompile_cmpl(drc_core *drc, UINT32 op)
980	1022	{
981		_xor_r32_r32(REG_EAX, REG_EAX);
982		_xor_r32_r32(REG_EBX, REG_EBX);
983		_mov_r32_m32abs(REG_ECX, &REG(RA));
984		_cmp_r32_m32abs(REG_ECX, &REG(RB));
	1023	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	1024	emit_xor_r32_r32(DRCTOP, REG_EBX, REG_EBX);
	1025	emit_mov_r32_m32(DRCTOP, REG_ECX, MABS(&REG(RA)));
	1026	emit_cmp_r32_m32(DRCTOP, REG_ECX, MABS(&REG(RB)));
985	1027
986		_setcc_r8(COND_Z, REG_AL);
987		_setcc_r8(COND_B, REG_AH);
988		_setcc_r8(COND_A, REG_BL);
989		_shl_r8_imm(REG_AL, 1);
990		_shl_r8_imm(REG_AH, 3);
991		_shl_r8_imm(REG_BL, 2);
992		_or_r8_r8(REG_BL, REG_AH);
993		_or_r8_r8(REG_BL, REG_AL);
	1028	emit_setcc_r8(DRCTOP, COND_Z, REG_AL);
	1029	emit_setcc_r8(DRCTOP, COND_B, REG_AH);
	1030	emit_setcc_r8(DRCTOP, COND_A, REG_BL);
	1031	emit_shl_r8_imm(DRCTOP, REG_AL, 1);
	1032	emit_shl_r8_imm(DRCTOP, REG_AH, 3);
	1033	emit_shl_r8_imm(DRCTOP, REG_BL, 2);
	1034	emit_or_r8_r8(DRCTOP, REG_BL, REG_AH);
	1035	emit_or_r8_r8(DRCTOP, REG_BL, REG_AL);
994	1036
995		_bt_m32abs_imm(&XER, 31); // set XER SO bit to carry
996		_adc_r32_imm(REG_EBX, 0); // effectively sets bit 0 to carry
997		_mov_m8abs_r8(&ppc.cr[CRFD], REG_BL);
	1037	emit_bt_m32_imm(DRCTOP, MABS(&XER), 31); // set XER SO bit to carry
	1038	emit_adc_r32_imm(DRCTOP, REG_EBX, 0); // effectively sets bit 0 to carry
	1039	emit_mov_m8_r8(DRCTOP, MABS(&ppc.cr[CRFD]), REG_BL);
998	1040
999	1041	return RECOMPILE_SUCCESSFUL_CP(1,4);
1000	1042	}
1001	1043
1002	1044	static UINT32 recompile_cmpli(drc_core *drc, UINT32 op)
1003	1045	{
1004		_xor_r32_r32(REG_EAX, REG_EAX);
1005		_xor_r32_r32(REG_EBX, REG_EBX);
1006		_mov_r32_m32abs(REG_ECX, &REG(RA));
1007		_cmp_r32_imm(REG_ECX, UIMM16);
	1046	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	1047	emit_xor_r32_r32(DRCTOP, REG_EBX, REG_EBX);
	1048	emit_mov_r32_m32(DRCTOP, REG_ECX, MABS(&REG(RA)));
	1049	emit_cmp_r32_imm(DRCTOP, REG_ECX, UIMM16);
1008	1050
1009		_setcc_r8(COND_Z, REG_AL);
1010		_setcc_r8(COND_B, REG_AH);
1011		_setcc_r8(COND_A, REG_BL);
1012		_shl_r8_imm(REG_AL, 1);
1013		_shl_r8_imm(REG_AH, 3);
1014		_shl_r8_imm(REG_BL, 2);
1015		_or_r8_r8(REG_BL, REG_AH);
1016		_or_r8_r8(REG_BL, REG_AL);
	1051	emit_setcc_r8(DRCTOP, COND_Z, REG_AL);
	1052	emit_setcc_r8(DRCTOP, COND_B, REG_AH);
	1053	emit_setcc_r8(DRCTOP, COND_A, REG_BL);
	1054	emit_shl_r8_imm(DRCTOP, REG_AL, 1);
	1055	emit_shl_r8_imm(DRCTOP, REG_AH, 3);
	1056	emit_shl_r8_imm(DRCTOP, REG_BL, 2);
	1057	emit_or_r8_r8(DRCTOP, REG_BL, REG_AH);
	1058	emit_or_r8_r8(DRCTOP, REG_BL, REG_AL);
1017	1059
1018		_bt_m32abs_imm(&XER, 31); // set XER SO bit to carry
1019		_adc_r32_imm(REG_EBX, 0); // effectively sets bit 0 to carry
1020		_mov_m8abs_r8(&ppc.cr[CRFD], REG_BL);
	1060	emit_bt_m32_imm(DRCTOP, MABS(&XER), 31); // set XER SO bit to carry
	1061	emit_adc_r32_imm(DRCTOP, REG_EBX, 0); // effectively sets bit 0 to carry
	1062	emit_mov_m8_r8(DRCTOP, MABS(&ppc.cr[CRFD]), REG_BL);
1021	1063
1022	1064	return RECOMPILE_SUCCESSFUL_CP(1,4);
1023	1065	}
1024	1066
1025	1067	static UINT32 recompile_cntlzw(drc_core *drc, UINT32 op)
1026	1068	{
1027		_xor_r32_r32(REG_EBX, REG_EBX);
1028		_mov_r32_imm(REG_EDX, 31);
1029		_mov_r32_m32abs(REG_EAX, &REG(RT));
1030		_bsr_r32_r32(REG_EAX, REG_EAX);
1031		_setcc_r8(COND_Z, REG_BL); // if all zeros, set BL to 1, so result becomes 32
1032		_sub_r32_r32(REG_EDX, REG_EAX);
1033		_add_r32_r32(REG_EDX, REG_EBX);
1034		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1069	emit_xor_r32_r32(DRCTOP, REG_EBX, REG_EBX);
	1070	emit_mov_r32_imm(DRCTOP, REG_EDX, 31);
	1071	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RT)));
	1072	emit_bsr_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	1073	emit_setcc_r8(DRCTOP, COND_Z, REG_BL); // if all zeros, set BL to 1, so result becomes 32
	1074	emit_sub_r32_r32(DRCTOP, REG_EDX, REG_EAX);
	1075	emit_add_r32_r32(DRCTOP, REG_EDX, REG_EBX);
	1076	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1035	1077
1036	1078	if (RCBIT) {
1037	1079	append_set_cr0(drc);
r949	r950
1042	1084
1043	1085	static UINT32 recompile_crand(drc_core *drc, UINT32 op)
1044	1086	{
1045		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1046		_push_imm(op);
1047		_call((genf *)ppc_crand);
1048		_add_r32_imm(REG_ESP, 4);
1049		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1087	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1088	emit_push_imm(DRCTOP, op);
	1089	emit_call(DRCTOP, (x86code *)ppc_crand);
	1090	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1091	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1050	1092	return RECOMPILE_SUCCESSFUL_CP(1,4);
1051	1093	}
1052	1094
1053	1095	static UINT32 recompile_crandc(drc_core *drc, UINT32 op)
1054	1096	{
1055		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1056		_push_imm(op);
1057		_call((genf *)ppc_crandc);
1058		_add_r32_imm(REG_ESP, 4);
1059		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1097	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1098	emit_push_imm(DRCTOP, op);
	1099	emit_call(DRCTOP, (x86code *)ppc_crandc);
	1100	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1101	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1060	1102	return RECOMPILE_SUCCESSFUL_CP(1,4);
1061	1103	}
1062	1104
1063	1105	static UINT32 recompile_creqv(drc_core *drc, UINT32 op)
1064	1106	{
1065		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1066		_push_imm(op);
1067		_call((genf *)ppc_creqv);
1068		_add_r32_imm(REG_ESP, 4);
1069		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1107	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1108	emit_push_imm(DRCTOP, op);
	1109	emit_call(DRCTOP, (x86code *)ppc_creqv);
	1110	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1111	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1070	1112	return RECOMPILE_SUCCESSFUL_CP(1,4);
1071	1113	}
1072	1114
1073	1115	static UINT32 recompile_crnand(drc_core *drc, UINT32 op)
1074	1116	{
1075		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1076		_push_imm(op);
1077		_call((genf *)ppc_crnand);
1078		_add_r32_imm(REG_ESP, 4);
1079		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1117	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1118	emit_push_imm(DRCTOP, op);
	1119	emit_call(DRCTOP, (x86code *)ppc_crnand);
	1120	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1121	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1080	1122	return RECOMPILE_SUCCESSFUL_CP(1,4);
1081	1123	}
1082	1124
1083	1125	static UINT32 recompile_crnor(drc_core *drc, UINT32 op)
1084	1126	{
1085		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1086		_push_imm(op);
1087		_call((genf *)ppc_crnor);
1088		_add_r32_imm(REG_ESP, 4);
1089		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1127	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1128	emit_push_imm(DRCTOP, op);
	1129	emit_call(DRCTOP, (x86code *)ppc_crnor);
	1130	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1131	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1090	1132	return RECOMPILE_SUCCESSFUL_CP(1,4);
1091	1133	}
1092	1134
1093	1135	static UINT32 recompile_cror(drc_core *drc, UINT32 op)
1094	1136	{
1095		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1096		_push_imm(op);
1097		_call((genf *)ppc_cror);
1098		_add_r32_imm(REG_ESP, 4);
1099		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1137	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1138	emit_push_imm(DRCTOP, op);
	1139	emit_call(DRCTOP, (x86code *)ppc_cror);
	1140	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1141	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1100	1142	return RECOMPILE_SUCCESSFUL_CP(1,4);
1101	1143	}
1102	1144
1103	1145	static UINT32 recompile_crorc(drc_core *drc, UINT32 op)
1104	1146	{
1105		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1106		_push_imm(op);
1107		_call((genf *)ppc_crorc);
1108		_add_r32_imm(REG_ESP, 4);
1109		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1147	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1148	emit_push_imm(DRCTOP, op);
	1149	emit_call(DRCTOP, (x86code *)ppc_crorc);
	1150	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1151	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1110	1152	return RECOMPILE_SUCCESSFUL_CP(1,4);
1111	1153	}
1112	1154
1113	1155	static UINT32 recompile_crxor(drc_core *drc, UINT32 op)
1114	1156	{
1115		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1116		_push_imm(op);
1117		_call((genf *)ppc_crxor);
1118		_add_r32_imm(REG_ESP, 4);
1119		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1157	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1158	emit_push_imm(DRCTOP, op);
	1159	emit_call(DRCTOP, (x86code *)ppc_crxor);
	1160	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1161	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1120	1162	return RECOMPILE_SUCCESSFUL_CP(1,4);
1121	1163	}
1122	1164
r949	r950
1152	1194
1153	1195	static UINT32 recompile_divwx(drc_core *drc, UINT32 op)
1154	1196	{
1155		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1156		_push_imm(op);
1157		_call((genf *)ppc_divwx);
1158		_add_r32_imm(REG_ESP, 4);
1159		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1197	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1198	emit_push_imm(DRCTOP, op);
	1199	emit_call(DRCTOP, (x86code *)ppc_divwx);
	1200	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1201	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1160	1202	return RECOMPILE_SUCCESSFUL_CP(1,4);
1161	1203	}
1162	1204
1163	1205	static UINT32 recompile_divwux(drc_core *drc, UINT32 op)
1164	1206	{
1165		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1166		_push_imm(op);
1167		_call((genf *)ppc_divwux);
1168		_add_r32_imm(REG_ESP, 4);
1169		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1207	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1208	emit_push_imm(DRCTOP, op);
	1209	emit_call(DRCTOP, (x86code *)ppc_divwux);
	1210	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1211	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1170	1212	return RECOMPILE_SUCCESSFUL_CP(1,4);
1171	1213	}
1172	1214
r949	r950
1177	1219
1178	1220	static UINT32 recompile_eqvx(drc_core *drc, UINT32 op)
1179	1221	{
1180		_mov_r32_m32abs(REG_EDX, &REG(RS));
1181		_xor_r32_m32abs(REG_EDX, &REG(RB));
1182		_not_r32(REG_EDX);
1183		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1222	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	1223	emit_xor_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	1224	emit_not_r32(DRCTOP, REG_EDX);
	1225	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1184	1226
1185	1227	if (RCBIT) {
1186	1228	append_set_cr0(drc);
r949	r950
1191	1233
1192	1234	static UINT32 recompile_extsbx(drc_core *drc, UINT32 op)
1193	1235	{
1194		_mov_r32_m32abs(REG_EDX, &REG(RS));
1195		_movsx_r32_r8(REG_EDX, REG_DL);
1196		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1236	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	1237	emit_movsx_r32_r8(DRCTOP, REG_EDX, REG_DL);
	1238	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1197	1239
1198	1240	if (RCBIT) {
1199	1241	append_set_cr0(drc);
r949	r950
1204	1246
1205	1247	static UINT32 recompile_extshx(drc_core *drc, UINT32 op)
1206	1248	{
1207		_mov_r32_m32abs(REG_EDX, &REG(RS));
1208		_movsx_r32_r16(REG_EDX, REG_DX);
1209		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1249	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	1250	emit_movsx_r32_r16(DRCTOP, REG_EDX, REG_DX);
	1251	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1210	1252
1211	1253	if (RCBIT) {
1212	1254	append_set_cr0(drc);
r949	r950
1227	1269
1228	1270	static UINT32 recompile_lbz(drc_core *drc, UINT32 op)
1229	1271	{
1230		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	1272	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
1231	1273	if (RA == 0)
1232	1274	{
1233		_push_imm(SIMM16);
	1275	emit_push_imm(DRCTOP, SIMM16);
1234	1276	}
1235	1277	else
1236	1278	{
1237		_mov_r32_m32abs(REG_EAX, &REG(RA));
1238		_add_r32_imm(REG_EAX, SIMM16);
1239		_push_r32(REG_EAX);
	1279	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	1280	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	1281	emit_push_r32(DRCTOP, REG_EAX);
1240	1282	}
1241		_call((genf *)READ8);
1242		_add_r32_imm(REG_ESP, 4);
1243		_movzx_r32_r8(REG_EAX, REG_AL);
1244		_mov_m32abs_r32(&REG(RT), REG_EAX);
1245		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1283	emit_call(DRCTOP, (x86code *)READ8);
	1284	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1285	emit_movzx_r32_r8(DRCTOP, REG_EAX, REG_AL);
	1286	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1287	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1246	1288
1247	1289	return RECOMPILE_SUCCESSFUL_CP(1,4);
1248	1290	}
1249	1291
1250	1292	static UINT32 recompile_lbzu(drc_core *drc, UINT32 op)
1251	1293	{
1252		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1253		_mov_r32_m32abs(REG_EDX, &REG(RA));
1254		_add_r32_imm(REG_EDX, SIMM16);
1255		_mov_m32abs_r32(&REG(RA), REG_EDX);
1256		_push_r32(REG_EDX);
1257		_call((genf *)READ8);
1258		_add_r32_imm(REG_ESP, 4);
1259		_movzx_r32_r8(REG_EAX, REG_AL);
1260		_mov_m32abs_r32(&REG(RT), REG_EAX);
1261		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1294	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1295	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	1296	emit_add_r32_imm(DRCTOP, REG_EDX, SIMM16);
	1297	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	1298	emit_push_r32(DRCTOP, REG_EDX);
	1299	emit_call(DRCTOP, (x86code *)READ8);
	1300	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1301	emit_movzx_r32_r8(DRCTOP, REG_EAX, REG_AL);
	1302	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1303	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1262	1304
1263	1305	return RECOMPILE_SUCCESSFUL_CP(1,4);
1264	1306	}
1265	1307
1266	1308	static UINT32 recompile_lbzux(drc_core *drc, UINT32 op)
1267	1309	{
1268		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1269		_mov_r32_m32abs(REG_EDX, &REG(RA));
1270		_add_r32_m32abs(REG_EDX, &REG(RB));
1271		_mov_m32abs_r32(&REG(RA), REG_EDX);
1272		_push_r32(REG_EDX);
1273		_call((genf *)READ8);
1274		_add_r32_imm(REG_ESP, 4);
1275		_movzx_r32_r8(REG_EAX, REG_AL);
1276		_mov_m32abs_r32(&REG(RT), REG_EAX);
1277		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1310	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1311	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	1312	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	1313	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	1314	emit_push_r32(DRCTOP, REG_EDX);
	1315	emit_call(DRCTOP, (x86code *)READ8);
	1316	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1317	emit_movzx_r32_r8(DRCTOP, REG_EAX, REG_AL);
	1318	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1319	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1278	1320
1279	1321	return RECOMPILE_SUCCESSFUL_CP(1,4);
1280	1322	}
1281	1323
1282	1324	static UINT32 recompile_lbzx(drc_core *drc, UINT32 op)
1283	1325	{
1284		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1285		_mov_r32_m32abs(REG_EAX, &REG(RB));
	1326	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1327	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
1286	1328	if (RA != 0)
1287	1329	{
1288		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	1330	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
1289	1331	}
1290		_push_r32(REG_EAX);
1291		_call((genf *)READ8);
1292		_add_r32_imm(REG_ESP, 4);
1293		_movzx_r32_r8(REG_EAX, REG_AL);
1294		_mov_m32abs_r32(&REG(RT), REG_EAX);
1295		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1332	emit_push_r32(DRCTOP, REG_EAX);
	1333	emit_call(DRCTOP, (x86code *)READ8);
	1334	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1335	emit_movzx_r32_r8(DRCTOP, REG_EAX, REG_AL);
	1336	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1337	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1296	1338
1297	1339	return RECOMPILE_SUCCESSFUL_CP(1,4);
1298	1340	}
1299	1341
1300	1342	static UINT32 recompile_lha(drc_core *drc, UINT32 op)
1301	1343	{
1302		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	1344	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
1303	1345	if (RA == 0)
1304	1346	{
1305		_push_imm(SIMM16);
	1347	emit_push_imm(DRCTOP, SIMM16);
1306	1348	}
1307	1349	else
1308	1350	{
1309		_mov_r32_m32abs(REG_EAX, &REG(RA));
1310		_add_r32_imm(REG_EAX, SIMM16);
1311		_push_r32(REG_EAX);
	1351	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	1352	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	1353	emit_push_r32(DRCTOP, REG_EAX);
1312	1354	}
1313		_call((genf *)READ16);
1314		_add_r32_imm(REG_ESP, 4);
1315		_movsx_r32_r16(REG_EAX, REG_AX);
1316		_mov_m32abs_r32(&REG(RT), REG_EAX);
1317		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1355	emit_call(DRCTOP, (x86code *)READ16);
	1356	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1357	emit_movsx_r32_r16(DRCTOP, REG_EAX, REG_AX);
	1358	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1359	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1318	1360
1319	1361	return RECOMPILE_SUCCESSFUL_CP(1,4);
1320	1362	}
1321	1363
1322	1364	static UINT32 recompile_lhau(drc_core *drc, UINT32 op)
1323	1365	{
1324		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1325		_mov_r32_m32abs(REG_EDX, &REG(RA));
1326		_add_r32_imm(REG_EDX, SIMM16);
1327		_mov_m32abs_r32(&REG(RA), REG_EDX);
1328		_push_r32(REG_EDX);
1329		_call((genf *)READ16);
1330		_add_r32_imm(REG_ESP, 4);
1331		_movsx_r32_r16(REG_EAX, REG_AX);
1332		_mov_m32abs_r32(&REG(RT), REG_EAX);
1333		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1366	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1367	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	1368	emit_add_r32_imm(DRCTOP, REG_EDX, SIMM16);
	1369	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	1370	emit_push_r32(DRCTOP, REG_EDX);
	1371	emit_call(DRCTOP, (x86code *)READ16);
	1372	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1373	emit_movsx_r32_r16(DRCTOP, REG_EAX, REG_AX);
	1374	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1375	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1334	1376
1335	1377	return RECOMPILE_SUCCESSFUL_CP(1,4);
1336	1378	}
1337	1379
1338	1380	static UINT32 recompile_lhaux(drc_core *drc, UINT32 op)
1339	1381	{
1340		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1341		_mov_r32_m32abs(REG_EDX, &REG(RA));
1342		_add_r32_m32abs(REG_EDX, &REG(RB));
1343		_mov_m32abs_r32(&REG(RA), REG_EDX);
1344		_push_r32(REG_EDX);
1345		_call((genf *)READ16);
1346		_add_r32_imm(REG_ESP, 4);
1347		_movsx_r32_r16(REG_EAX, REG_AX);
1348		_mov_m32abs_r32(&REG(RT), REG_EAX);
1349		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1382	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1383	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	1384	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	1385	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	1386	emit_push_r32(DRCTOP, REG_EDX);
	1387	emit_call(DRCTOP, (x86code *)READ16);
	1388	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1389	emit_movsx_r32_r16(DRCTOP, REG_EAX, REG_AX);
	1390	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1391	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1350	1392
1351	1393	return RECOMPILE_SUCCESSFUL_CP(1,4);
1352	1394	}
1353	1395
1354	1396	static UINT32 recompile_lhax(drc_core *drc, UINT32 op)
1355	1397	{
1356		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1357		_mov_r32_m32abs(REG_EAX, &REG(RB));
	1398	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1399	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
1358	1400	if (RA != 0)
1359	1401	{
1360		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	1402	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
1361	1403	}
1362		_push_r32(REG_EAX);
1363		_call((genf *)READ16);
1364		_add_r32_imm(REG_ESP, 4);
1365		_movsx_r32_r16(REG_EAX, REG_AX);
1366		_mov_m32abs_r32(&REG(RT), REG_EAX);
1367		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1404	emit_push_r32(DRCTOP, REG_EAX);
	1405	emit_call(DRCTOP, (x86code *)READ16);
	1406	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1407	emit_movsx_r32_r16(DRCTOP, REG_EAX, REG_AX);
	1408	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1409	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1368	1410
1369	1411	return RECOMPILE_SUCCESSFUL_CP(1,4);
1370	1412	}
1371	1413
1372	1414	static UINT32 recompile_lhbrx(drc_core *drc, UINT32 op)
1373	1415	{
1374		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1375		_mov_r32_m32abs(REG_EAX, &REG(RB));
	1416	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1417	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
1376	1418	if (RA != 0)
1377	1419	{
1378		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	1420	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
1379	1421	}
1380		_push_r32(REG_EAX);
1381		_call((genf *)READ16);
1382		_add_r32_imm(REG_ESP, 4);
1383		_mov_r32_imm(REG_ECX, 8);
1384		_rol_r16_cl(REG_AX);
1385		_mov_m32abs_r32(&REG(RT), REG_EAX);
1386		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1422	emit_push_r32(DRCTOP, REG_EAX);
	1423	emit_call(DRCTOP, (x86code *)READ16);
	1424	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1425	emit_mov_r32_imm(DRCTOP, REG_ECX, 8);
	1426	emit_rol_r16_cl(DRCTOP, REG_AX);
	1427	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1428	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1387	1429
1388	1430	return RECOMPILE_SUCCESSFUL_CP(1,4);
1389	1431	}
1390	1432
1391	1433	static UINT32 recompile_lhz(drc_core *drc, UINT32 op)
1392	1434	{
1393		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	1435	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
1394	1436	if (RA == 0)
1395	1437	{
1396		_push_imm(SIMM16);
	1438	emit_push_imm(DRCTOP, SIMM16);
1397	1439	}
1398	1440	else
1399	1441	{
1400		_mov_r32_m32abs(REG_EAX, &REG(RA));
1401		_add_r32_imm(REG_EAX, SIMM16);
1402		_push_r32(REG_EAX);
	1442	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	1443	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	1444	emit_push_r32(DRCTOP, REG_EAX);
1403	1445	}
1404		_call((genf *)READ16);
1405		_add_r32_imm(REG_ESP, 4);
1406		_mov_m32abs_r32(&REG(RT), REG_EAX);
1407		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1446	emit_call(DRCTOP, (x86code *)READ16);
	1447	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1448	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1449	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1408	1450
1409	1451	return RECOMPILE_SUCCESSFUL_CP(1,4);
1410	1452	}
1411	1453
1412	1454	static UINT32 recompile_lhzu(drc_core *drc, UINT32 op)
1413	1455	{
1414		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1415		_mov_r32_m32abs(REG_EDX, &REG(RA));
1416		_add_r32_imm(REG_EDX, SIMM16);
1417		_mov_m32abs_r32(&REG(RA), REG_EDX);
1418		_push_r32(REG_EDX);
1419		_call((genf *)READ16);
1420		_add_r32_imm(REG_ESP, 4);
1421		_mov_m32abs_r32(&REG(RT), REG_EAX);
1422		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1456	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1457	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	1458	emit_add_r32_imm(DRCTOP, REG_EDX, SIMM16);
	1459	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	1460	emit_push_r32(DRCTOP, REG_EDX);
	1461	emit_call(DRCTOP, (x86code *)READ16);
	1462	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1463	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1464	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1423	1465
1424	1466	return RECOMPILE_SUCCESSFUL_CP(1,4);
1425	1467	}
1426	1468
1427	1469	static UINT32 recompile_lhzux(drc_core *drc, UINT32 op)
1428	1470	{
1429		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1430		_mov_r32_m32abs(REG_EDX, &REG(RA));
1431		_add_r32_m32abs(REG_EDX, &REG(RB));
1432		_mov_m32abs_r32(&REG(RA), REG_EDX);
1433		_push_r32(REG_EDX);
1434		_call((genf *)READ16);
1435		_add_r32_imm(REG_ESP, 4);
1436		_mov_m32abs_r32(&REG(RT), REG_EAX);
1437		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1471	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1472	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	1473	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	1474	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	1475	emit_push_r32(DRCTOP, REG_EDX);
	1476	emit_call(DRCTOP, (x86code *)READ16);
	1477	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1478	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1479	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1438	1480
1439	1481	return RECOMPILE_SUCCESSFUL_CP(1,4);
1440	1482	}
1441	1483
1442	1484	static UINT32 recompile_lhzx(drc_core *drc, UINT32 op)
1443	1485	{
1444		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1445		_mov_r32_m32abs(REG_EAX, &REG(RB));
	1486	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1487	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
1446	1488	if (RA != 0)
1447	1489	{
1448		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	1490	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
1449	1491	}
1450		_push_r32(REG_EAX);
1451		_call((genf *)READ16);
1452		_add_r32_imm(REG_ESP, 4);
1453		_mov_m32abs_r32(&REG(RT), REG_EAX);
1454		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1492	emit_push_r32(DRCTOP, REG_EAX);
	1493	emit_call(DRCTOP, (x86code *)READ16);
	1494	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1495	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1496	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1455	1497
1456	1498	return RECOMPILE_SUCCESSFUL_CP(1,4);
1457	1499	}
1458	1500
1459	1501	static UINT32 recompile_lmw(drc_core *drc, UINT32 op)
1460	1502	{
1461		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1462		_push_imm(op);
1463		_call((genf *)ppc_lmw);
1464		_add_r32_imm(REG_ESP, 4);
1465		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1503	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1504	emit_push_imm(DRCTOP, op);
	1505	emit_call(DRCTOP, (x86code *)ppc_lmw);
	1506	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1507	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1466	1508
1467	1509	return RECOMPILE_SUCCESSFUL_CP(1,4);
1468	1510	}
1469	1511
1470	1512	static UINT32 recompile_lswi(drc_core *drc, UINT32 op)
1471	1513	{
1472		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1473		_push_imm(op);
1474		_call((genf *)ppc_lswi);
1475		_add_r32_imm(REG_ESP, 4);
1476		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1514	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1515	emit_push_imm(DRCTOP, op);
	1516	emit_call(DRCTOP, (x86code *)ppc_lswi);
	1517	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1518	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1477	1519
1478	1520	return RECOMPILE_SUCCESSFUL_CP(1,4);
1479	1521	}
1480	1522
1481	1523	static UINT32 recompile_lswx(drc_core *drc, UINT32 op)
1482	1524	{
1483		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1484		_push_imm(op);
1485		_call((genf *)ppc_lswx);
1486		_add_r32_imm(REG_ESP, 4);
1487		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1525	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1526	emit_push_imm(DRCTOP, op);
	1527	emit_call(DRCTOP, (x86code *)ppc_lswx);
	1528	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1529	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1488	1530
1489	1531	return RECOMPILE_SUCCESSFUL_CP(1,4);
1490	1532	}
1491	1533
1492	1534	static UINT32 recompile_lwarx(drc_core *drc, UINT32 op)
1493	1535	{
1494		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1495		_push_imm(op);
1496		_call((genf *)ppc_lwarx);
1497		_add_r32_imm(REG_ESP, 4);
1498		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1536	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1537	emit_push_imm(DRCTOP, op);
	1538	emit_call(DRCTOP, (x86code *)ppc_lwarx);
	1539	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1540	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1499	1541
1500	1542	return RECOMPILE_SUCCESSFUL_CP(1,4);
1501	1543	}
1502	1544
1503	1545	static UINT32 recompile_lwbrx(drc_core *drc, UINT32 op)
1504	1546	{
1505		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1506		_mov_r32_m32abs(REG_EAX, &REG(RB));
	1547	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1548	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
1507	1549	if (RA != 0)
1508	1550	{
1509		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	1551	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
1510	1552	}
1511		_push_r32(REG_EAX);
1512		_call((genf *)READ32);
1513		_add_r32_imm(REG_ESP, 4);
1514		_bswap_r32(REG_EAX);
1515		_mov_m32abs_r32(&REG(RT), REG_EAX);
1516		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1553	emit_push_r32(DRCTOP, REG_EAX);
	1554	emit_call(DRCTOP, (x86code *)READ32);
	1555	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1556	emit_bswap_r32(DRCTOP, REG_EAX);
	1557	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1558	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1517	1559
1518	1560	return RECOMPILE_SUCCESSFUL_CP(1,4);
1519	1561	}
1520	1562
1521	1563	static UINT32 recompile_lwz(drc_core *drc, UINT32 op)
1522	1564	{
1523		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	1565	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
1524	1566	if (RA == 0)
1525	1567	{
1526		_push_imm(SIMM16);
	1568	emit_push_imm(DRCTOP, SIMM16);
1527	1569	}
1528	1570	else
1529	1571	{
1530		_mov_r32_m32abs(REG_EAX, &REG(RA));
1531		_add_r32_imm(REG_EAX, SIMM16);
1532		_push_r32(REG_EAX);
	1572	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	1573	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	1574	emit_push_r32(DRCTOP, REG_EAX);
1533	1575	}
1534		_call((genf *)READ32);
1535		_add_r32_imm(REG_ESP, 4);
1536		_mov_m32abs_r32(&REG(RT), REG_EAX);
1537		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1576	emit_call(DRCTOP, (x86code *)READ32);
	1577	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1578	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1579	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1538	1580
1539	1581	return RECOMPILE_SUCCESSFUL_CP(1,4);
1540	1582	}
1541	1583
1542	1584	static UINT32 recompile_lwzu(drc_core *drc, UINT32 op)
1543	1585	{
1544		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1545		_mov_r32_m32abs(REG_EDX, &REG(RA));
1546		_add_r32_imm(REG_EDX, SIMM16);
1547		_mov_m32abs_r32(&REG(RA), REG_EDX);
1548		_push_r32(REG_EDX);
1549		_call((genf *)READ32);
1550		_add_r32_imm(REG_ESP, 4);
1551		_mov_m32abs_r32(&REG(RT), REG_EAX);
1552		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1586	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1587	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	1588	emit_add_r32_imm(DRCTOP, REG_EDX, SIMM16);
	1589	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	1590	emit_push_r32(DRCTOP, REG_EDX);
	1591	emit_call(DRCTOP, (x86code *)READ32);
	1592	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1593	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1594	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1553	1595
1554	1596	return RECOMPILE_SUCCESSFUL_CP(1,4);
1555	1597	}
1556	1598
1557	1599	static UINT32 recompile_lwzux(drc_core *drc, UINT32 op)
1558	1600	{
1559		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1560		_mov_r32_m32abs(REG_EDX, &REG(RA));
1561		_add_r32_m32abs(REG_EDX, &REG(RB));
1562		_mov_m32abs_r32(&REG(RA), REG_EDX);
1563		_push_r32(REG_EDX);
1564		_call((genf *)READ32);
1565		_add_r32_imm(REG_ESP, 4);
1566		_mov_m32abs_r32(&REG(RT), REG_EAX);
1567		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1601	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1602	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	1603	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	1604	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	1605	emit_push_r32(DRCTOP, REG_EDX);
	1606	emit_call(DRCTOP, (x86code *)READ32);
	1607	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1608	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1609	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1568	1610
1569	1611	return RECOMPILE_SUCCESSFUL_CP(1,4);
1570	1612	}
1571	1613
1572	1614	static UINT32 recompile_lwzx(drc_core *drc, UINT32 op)
1573	1615	{
1574		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1575		_mov_r32_m32abs(REG_EAX, &REG(RB));
	1616	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1617	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
1576	1618	if (RA != 0)
1577	1619	{
1578		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	1620	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
1579	1621	}
1580		_push_r32(REG_EAX);
1581		_call((genf *)READ32);
1582		_add_r32_imm(REG_ESP, 4);
1583		_mov_m32abs_r32(&REG(RT), REG_EAX);
1584		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1622	emit_push_r32(DRCTOP, REG_EAX);
	1623	emit_call(DRCTOP, (x86code *)READ32);
	1624	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1625	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
	1626	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1585	1627
1586	1628	return RECOMPILE_SUCCESSFUL_CP(1,4);
1587	1629	}
1588	1630
1589	1631	static UINT32 recompile_mcrf(drc_core *drc, UINT32 op)
1590	1632	{
1591		_mov_r8_m8abs(REG_AL, &ppc.cr[RA >> 2]);
1592		_mov_m8abs_r8(&ppc.cr[RT >> 2], REG_AL);
	1633	emit_mov_r8_m8(DRCTOP, REG_AL, MABS(&ppc.cr[RA >> 2]));
	1634	emit_mov_m8_r8(DRCTOP, MABS(&ppc.cr[RT >> 2]), REG_AL);
1593	1635
1594	1636	return RECOMPILE_SUCCESSFUL_CP(1,4);
1595	1637	}
r949	r950
1603	1645	static UINT32 recompile_mfcr(drc_core *drc, UINT32 op)
1604	1646	{
1605	1647	int i;
1606		_xor_r32_r32(REG_EAX, REG_EAX);
	1648	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
1607	1649
1608	1650	// generate code for each condition register
1609	1651	for (i=0; i < 8; i++)
1610	1652	{
1611		_xor_r32_r32(REG_EDX, REG_EDX);
1612		_mov_r8_m8abs(REG_DL, &ppc.cr[i]);
1613		_shl_r32_imm(REG_EDX, ((7-i) * 4));
1614		_or_r32_r32(REG_EAX, REG_EDX);
	1653	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EDX);
	1654	emit_mov_r8_m8(DRCTOP, REG_DL, MABS(&ppc.cr[i]));
	1655	emit_shl_r32_imm(DRCTOP, REG_EDX, ((7-i) * 4));
	1656	emit_or_r32_r32(DRCTOP, REG_EAX, REG_EDX);
1615	1657	}
1616		_mov_m32~~abs~~_r32(&REG(RT), REG_EAX);
	1658	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
1617	1659
1618	1660	return RECOMPILE_SUCCESSFUL_CP(1,4);
1619	1661	}
1620	1662
1621	1663	static UINT32 recompile_mfmsr(drc_core *drc, UINT32 op)
1622	1664	{
1623		_mov_r32_m32abs(REG_EAX, &ppc.msr);
1624		_mov_m32abs_r32(&REG(RT), REG_EAX);
	1665	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.msr));
	1666	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
1625	1667
1626	1668	return RECOMPILE_SUCCESSFUL_CP(1,4);
1627	1669	}
r949	r950
1630	1672	{
1631	1673	if (SPR == SPR_LR) // optimized case, LR
1632	1674	{
1633		_mov_r32_m32~~abs~~(REG_EAX, &LR);
	1675	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&LR));
1634	1676	}
1635	1677	else if(SPR == SPR_CTR) // optimized case, CTR
1636	1678	{
1637		_mov_r32_m32~~abs~~(REG_EAX, &CTR);
	1679	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&CTR));
1638	1680	}
1639	1681	else
1640	1682	{
1641		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1642		_push_imm(SPR);
1643		_call((genf *)ppc_get_spr);
1644		_add_r32_imm(REG_ESP, 4);
1645		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1683	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1684	emit_push_imm(DRCTOP, SPR);
	1685	emit_call(DRCTOP, (x86code *)ppc_get_spr);
	1686	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1687	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1646	1688	}
1647		_mov_m32~~abs~~_r32(&REG(RT), REG_EAX);
	1689	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
1648	1690
1649	1691	return RECOMPILE_SUCCESSFUL_CP(1,4);
1650	1692	}
1651	1693
1652	1694	static UINT32 recompile_mtcrf(drc_core *drc, UINT32 op)
1653	1695	{
1654		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1655		_push_imm(op);
1656		_call((genf *)ppc_mtcrf);
1657		_add_r32_imm(REG_ESP, 4);
1658		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1696	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1697	emit_push_imm(DRCTOP, op);
	1698	emit_call(DRCTOP, (x86code *)ppc_mtcrf);
	1699	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1700	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1659	1701
1660	1702	return RECOMPILE_SUCCESSFUL_CP(1,4);
1661	1703	}
1662	1704
1663	1705	static UINT32 recompile_mtmsr(drc_core *drc, UINT32 op)
1664	1706	{
1665		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1666		_mov_r32_m32abs(REG_EAX, &REG(RS));
1667		_push_r32(REG_EAX);
1668		_call((genf *)ppc_set_msr);
1669		_add_r32_imm(REG_ESP, 4);
1670		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1707	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1708	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	1709	emit_push_r32(DRCTOP, REG_EAX);
	1710	emit_call(DRCTOP, (x86code *)ppc_set_msr);
	1711	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1712	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1671	1713
1672	1714	return RECOMPILE_SUCCESSFUL_CP(1,4);
1673	1715	}
1674	1716
1675	1717	static UINT32 recompile_mtspr(drc_core *drc, UINT32 op)
1676	1718	{
1677		_mov_r32_m32~~abs~~(REG_EAX, &REG(RS));
	1719	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
1678	1720	if (SPR == SPR_LR) // optimized case, LR
1679	1721	{
1680		_mov_m32~~abs~~_r32(&LR, REG_EAX);
	1722	emit_mov_m32_r32(DRCTOP, MABS(&LR), REG_EAX);
1681	1723	}
1682	1724	else if(SPR == SPR_CTR) // optimized case, CTR
1683	1725	{
1684		_mov_m32~~abs~~_r32(&CTR, REG_EAX);
	1726	emit_mov_m32_r32(DRCTOP, MABS(&CTR), REG_EAX);
1685	1727	}
1686	1728	else
1687	1729	{
1688		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1689		_push_r32(REG_EAX);
1690		_push_imm(SPR);
1691		_call((genf *)ppc_set_spr);
1692		_add_r32_imm(REG_ESP, 8);
1693		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1730	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1731	emit_push_r32(DRCTOP, REG_EAX);
	1732	emit_push_imm(DRCTOP, SPR);
	1733	emit_call(DRCTOP, (x86code *)ppc_set_spr);
	1734	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	1735	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1694	1736	}
1695	1737
1696	1738	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
1698	1740
1699	1741	static UINT32 recompile_mulhwx(drc_core *drc, UINT32 op)
1700	1742	{
1701		_mov_r32_m32abs(REG_EAX, &REG(RA));
1702		_mov_r32_m32abs(REG_EBX, &REG(RB));
1703		_imul_r32(REG_EBX);
1704		_mov_m32abs_r32(&REG(RT), REG_EDX);
	1743	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	1744	emit_mov_r32_m32(DRCTOP, REG_EBX, MABS(&REG(RB)));
	1745	emit_imul_r32(DRCTOP, REG_EBX);
	1746	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
1705	1747
1706	1748	if (RCBIT) {
1707	1749	append_set_cr0(drc);
r949	r950
1712	1754
1713	1755	static UINT32 recompile_mulhwux(drc_core *drc, UINT32 op)
1714	1756	{
1715		_mov_r32_m32abs(REG_EAX, &REG(RA));
1716		_mov_r32_m32abs(REG_EBX, &REG(RB));
1717		_mul_r32(REG_EBX);
1718		_mov_m32abs_r32(&REG(RT), REG_EDX);
	1757	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	1758	emit_mov_r32_m32(DRCTOP, REG_EBX, MABS(&REG(RB)));
	1759	emit_mul_r32(DRCTOP, REG_EBX);
	1760	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
1719	1761
1720	1762	if (RCBIT) {
1721	1763	append_set_cr0(drc);
r949	r950
1726	1768
1727	1769	static UINT32 recompile_mulli(drc_core *drc, UINT32 op)
1728	1770	{
1729		_mov_r32_m32abs(REG_EAX, &REG(RA));
1730		_mov_r32_imm(REG_EBX, SIMM16);
1731		_imul_r32(REG_EBX);
1732		_mov_m32abs_r32(&REG(RT), REG_EAX);
	1771	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	1772	emit_mov_r32_imm(DRCTOP, REG_EBX, SIMM16);
	1773	emit_imul_r32(DRCTOP, REG_EBX);
	1774	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EAX);
1733	1775
1734	1776	return RECOMPILE_SUCCESSFUL_CP(1,4);
1735	1777	}
1736	1778
1737	1779	static UINT32 recompile_mullwx(drc_core *drc, UINT32 op)
1738	1780	{
1739		_mov_r32_m32abs(REG_EAX, &REG(RA));
1740		_mov_r32_m32abs(REG_EBX, &REG(RB));
1741		_mul_r32(REG_EBX);
1742		_mov_r32_r32(REG_EDX, REG_EAX);
1743		_mov_m32abs_r32(&REG(RT), REG_EDX);
	1781	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	1782	emit_mov_r32_m32(DRCTOP, REG_EBX, MABS(&REG(RB)));
	1783	emit_mul_r32(DRCTOP, REG_EBX);
	1784	emit_mov_r32_r32(DRCTOP, REG_EDX, REG_EAX);
	1785	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
1744	1786
1745	1787	if (OEBIT) {
1746	1788	mame_printf_debug("recompile_mullwx: OEBIT set!\n");
r949	r950
1756	1798
1757	1799	static UINT32 recompile_nandx(drc_core *drc, UINT32 op)
1758	1800	{
1759		_mov_r32_m32abs(REG_EDX, &REG(RS));
1760		_and_r32_m32abs(REG_EDX, &REG(RB));
1761		_not_r32(REG_EDX);
1762		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1801	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	1802	emit_and_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	1803	emit_not_r32(DRCTOP, REG_EDX);
	1804	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1763	1805
1764	1806	if (RCBIT) {
1765	1807	append_set_cr0(drc);
r949	r950
1770	1812
1771	1813	static UINT32 recompile_negx(drc_core *drc, UINT32 op)
1772	1814	{
1773		_mov_r32_m32abs(REG_EDX, &REG(RA));
1774		_neg_r32(REG_EDX);
1775		_mov_m32abs_r32(&REG(RT), REG_EDX);
	1815	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	1816	emit_neg_r32(DRCTOP, REG_EDX);
	1817	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
1776	1818
1777	1819	if (RCBIT) {
1778	1820	append_set_cr0(drc);
r949	r950
1783	1825
1784	1826	static UINT32 recompile_norx(drc_core *drc, UINT32 op)
1785	1827	{
1786		_mov_r32_m32abs(REG_EDX, &REG(RS));
1787		_or_r32_m32abs(REG_EDX, &REG(RB));
1788		_not_r32(REG_EDX);
1789		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1828	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	1829	emit_or_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	1830	emit_not_r32(DRCTOP, REG_EDX);
	1831	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1790	1832
1791	1833	if (RCBIT) {
1792	1834	append_set_cr0(drc);
r949	r950
1797	1839
1798	1840	static UINT32 recompile_orx(drc_core *drc, UINT32 op)
1799	1841	{
1800		_mov_r32_m32abs(REG_EDX, &REG(RS));
1801		_or_r32_m32abs(REG_EDX, &REG(RB));
1802		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1842	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	1843	emit_or_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	1844	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1803	1845
1804	1846	if (RCBIT) {
1805	1847	append_set_cr0(drc);
r949	r950
1810	1852
1811	1853	static UINT32 recompile_orcx(drc_core *drc, UINT32 op)
1812	1854	{
1813		_mov_r32_m32abs(REG_EDX, &REG(RB));
1814		_not_r32(REG_EDX);
1815		_or_r32_m32abs(REG_EDX, &REG(RS));
1816		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1855	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	1856	emit_not_r32(DRCTOP, REG_EDX);
	1857	emit_or_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	1858	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1817	1859
1818	1860	if (RCBIT) {
1819	1861	append_set_cr0(drc);
r949	r950
1825	1867	static UINT32 recompile_ori(drc_core *drc, UINT32 op)
1826	1868	{
1827	1869
1828		_mov_r32_m32abs(REG_EAX, &REG(RS));
1829		_or_r32_imm(REG_EAX, UIMM16);
1830		_mov_m32abs_r32(&REG(RA), REG_EAX);
	1870	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	1871	emit_or_r32_imm(DRCTOP, REG_EAX, UIMM16);
	1872	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EAX);
1831	1873
1832	1874	return RECOMPILE_SUCCESSFUL_CP(1,4);
1833	1875	}
1834	1876
1835	1877	static UINT32 recompile_oris(drc_core *drc, UINT32 op)
1836	1878	{
1837		_mov_r32_m32abs(REG_EAX, &REG(RS));
1838		_or_r32_imm(REG_EAX, UIMM16 << 16);
1839		_mov_m32abs_r32(&REG(RA), REG_EAX);
	1879	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	1880	emit_or_r32_imm(DRCTOP, REG_EAX, UIMM16 << 16);
	1881	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EAX);
1840	1882
1841	1883	return RECOMPILE_SUCCESSFUL_CP(1,4);
1842	1884	}
1843	1885
1844	1886	static UINT32 recompile_rfi(drc_core *drc, UINT32 op)
1845	1887	{
1846		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1847		_mov_r32_m32abs(REG_EDI, &ppc.srr0); /* get saved PC from SRR0 */
1848		_mov_r32_m32abs(REG_EAX, &ppc.srr1); /* get saved MSR from SRR1 */
	1888	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1889	emit_mov_r32_m32(DRCTOP, REG_EDI, MABS(&ppc.srr0)); /* get saved PC from SRR0 */
	1890	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&ppc.srr1)); /* get saved MSR from SRR1 */
1849	1891
1850		_push_r32(REG_EAX);
1851		_call((genf )ppc_set_msr); / set MSR */
1852		_add_r32_imm(REG_ESP, 4);
1853		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1892	emit_push_r32(DRCTOP, REG_EAX);
	1893	emit_call(DRCTOP, (x86code )ppc_set_msr); / set MSR */
	1894	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1895	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1854	1896
1855	1897	return RECOMPILE_SUCCESSFUL_CP(1,0) \| RECOMPILE_END_OF_STRING \| RECOMPILE_ADD_DISPATCH;
1856	1898	}
r949	r950
1859	1901	{
1860	1902	UINT32 mask = GET_ROTATE_MASK(MB, ME);
1861	1903
1862		_mov_r32_m32abs(REG_EDX, &REG(RS));
1863		_mov_r32_m32abs(REG_EAX, &REG(RA));
1864		_rol_r32_imm(REG_EDX, (SH));
1865		_and_r32_imm(REG_EDX, mask);
1866		_and_r32_imm(REG_EAX, ~mask);
1867		_or_r32_r32(REG_EDX, REG_EAX);
1868		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1904	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	1905	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	1906	emit_rol_r32_imm(DRCTOP, REG_EDX, (SH));
	1907	emit_and_r32_imm(DRCTOP, REG_EDX, mask);
	1908	emit_and_r32_imm(DRCTOP, REG_EAX, ~mask);
	1909	emit_or_r32_r32(DRCTOP, REG_EDX, REG_EAX);
	1910	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1869	1911
1870	1912	if (RCBIT) {
1871	1913	append_set_cr0(drc);
r949	r950
1878	1920	{
1879	1921	UINT32 mask = GET_ROTATE_MASK(MB, ME);
1880	1922
1881		_mov_r32_m32abs(REG_EDX, &REG(RS));
1882		_rol_r32_imm(REG_EDX, (SH));
1883		_and_r32_imm(REG_EDX, mask);
1884		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1923	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	1924	emit_rol_r32_imm(DRCTOP, REG_EDX, (SH));
	1925	emit_and_r32_imm(DRCTOP, REG_EDX, mask);
	1926	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1885	1927
1886	1928	if (RCBIT) {
1887	1929	append_set_cr0(drc);
r949	r950
1894	1936	{
1895	1937	UINT32 mask = GET_ROTATE_MASK(MB, ME);
1896	1938
1897		_mov_r32_m32abs(REG_ECX, &REG(RB)); // x86 rotate instruction use only 5 bits, so no need to mask this
1898		_mov_r32_m32abs(REG_EDX, &REG(RS));
1899		_rol_r32_cl(REG_EDX);
1900		_and_r32_imm(REG_EDX, mask);
1901		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1939	emit_mov_r32_m32(DRCTOP, REG_ECX, MABS(&REG(RB))); // x86 rotate instruction use only 5 bits, so no need to mask this
	1940	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	1941	emit_rol_r32_cl(DRCTOP, REG_EDX);
	1942	emit_and_r32_imm(DRCTOP, REG_EDX, mask);
	1943	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1902	1944
1903	1945	if (RCBIT) {
1904	1946	append_set_cr0(drc);
r949	r950
1909	1951
1910	1952	static UINT32 recompile_sc(drc_core *drc, UINT32 op)
1911	1953	{
1912		_mov_m32abs_imm(&SRR0, temp_ppc_pc + 4);
1913		_jmp(ppc.generate_syscall_exception);
	1954	emit_mov_m32_imm(DRCTOP, MABS(&SRR0), temp_ppc_pc + 4);
	1955	emit_jmp(DRCTOP, ppc.generate_syscall_exception);
1914	1956	return RECOMPILE_SUCCESSFUL_CP(1,4);
1915	1957	}
1916	1958
1917	1959	static UINT32 recompile_slwx(drc_core *drc, UINT32 op)
1918	1960	{
1919	1961	#if USE_SSE2
1920		_mov_r32_m32abs(REG_ECX, &REG(RB));
1921		_and_r32_imm(REG_ECX, 0x3f);
1922		_movd_r128_m32abs(REG_XMM0, &REG(RS));
1923		_movd_r128_r32(REG_XMM1, REG_ECX);
1924		_psllq_r128_r128(REG_XMM0, REG_XMM1);
1925		_movd_r32_r128(REG_EDX, REG_XMM0);
1926		_mov_m32abs_r32(&REG(RA), REG_EDX);
	1962	emit_mov_r32_m32(DRCTOP, REG_ECX, MABS(&REG(RB)));
	1963	emit_and_r32_imm(DRCTOP, REG_ECX, 0x3f);
	1964	emit_movd_r128_m32(DRCTOP, REG_XMM0, MABS(&REG(RS)));
	1965	emit_movd_r128_r32(DRCTOP, REG_XMM1, REG_ECX);
	1966	emit_psllq_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	1967	emit_movd_r32_r128(DRCTOP, REG_EDX, REG_XMM0);
	1968	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1927	1969
1928	1970	if (RCBIT) {
1929	1971	append_set_cr0(drc);
1930	1972	}
1931	1973	#else
1932		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1933		_push_imm(op);
1934		_call((genf *)ppc_slwx);
1935		_add_r32_imm(REG_ESP, 4);
1936		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1974	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1975	emit_push_imm(DRCTOP, op);
	1976	emit_call(DRCTOP, (x86code *)ppc_slwx);
	1977	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1978	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1937	1979	#endif
1938	1980
1939	1981	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
1941	1983
1942	1984	static UINT32 recompile_srawx(drc_core *drc, UINT32 op)
1943	1985	{
1944		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1945		_push_imm(op);
1946		_call((genf *)ppc_srawx);
1947		_add_r32_imm(REG_ESP, 4);
1948		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1986	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1987	emit_push_imm(DRCTOP, op);
	1988	emit_call(DRCTOP, (x86code *)ppc_srawx);
	1989	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	1990	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1949	1991
1950	1992	return RECOMPILE_SUCCESSFUL_CP(1,4);
1951	1993	}
1952	1994
1953	1995	static UINT32 recompile_srawix(drc_core *drc, UINT32 op)
1954	1996	{
1955		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1956		_push_imm(op);
1957		_call((genf *)ppc_srawix);
1958		_add_r32_imm(REG_ESP, 4);
1959		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	1997	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	1998	emit_push_imm(DRCTOP, op);
	1999	emit_call(DRCTOP, (x86code *)ppc_srawix);
	2000	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2001	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1960	2002
1961	2003	return RECOMPILE_SUCCESSFUL_CP(1,4);
1962	2004	}
r949	r950
1964	2006	static UINT32 recompile_srwx(drc_core *drc, UINT32 op)
1965	2007	{
1966	2008	#if USE_SSE2
1967		_mov_r32_m32abs(REG_ECX, &REG(RB));
1968		_and_r32_imm(REG_ECX, 0x3f);
1969		_movd_r128_m32abs(REG_XMM0, &REG(RS));
1970		_movd_r128_r32(REG_XMM1, REG_ECX);
1971		_psrlq_r128_r128(REG_XMM0, REG_XMM1);
1972		_movd_r32_r128(REG_EDX, REG_XMM0);
1973		_mov_m32abs_r32(&REG(RA), REG_EDX);
	2009	emit_mov_r32_m32(DRCTOP, REG_ECX, MABS(&REG(RB)));
	2010	emit_and_r32_imm(DRCTOP, REG_ECX, 0x3f);
	2011	emit_movd_r128_m32(DRCTOP, REG_XMM0, MABS(&REG(RS)));
	2012	emit_movd_r128_r32(DRCTOP, REG_XMM1, REG_ECX);
	2013	emit_psrlq_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	2014	emit_movd_r32_r128(DRCTOP, REG_EDX, REG_XMM0);
	2015	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
1974	2016
1975	2017	if (RCBIT) {
1976	2018	append_set_cr0(drc);
1977	2019	}
1978	2020	#else
1979		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1980		_push_imm(op);
1981		_call((genf *)ppc_srwx);
1982		_add_r32_imm(REG_ESP, 4);
1983		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2021	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2022	emit_push_imm(DRCTOP, op);
	2023	emit_call(DRCTOP, (x86code *)ppc_srwx);
	2024	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2025	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
1984	2026	#endif
1985	2027
1986	2028	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
1988	2030
1989	2031	static UINT32 recompile_stb(drc_core *drc, UINT32 op)
1990	2032	{
1991		_mov_m32abs_r32(&ppc_icount, REG_EBP);
1992		_mov_r32_m32abs(REG_EAX, &REG(RS));
1993		_movzx_r32_r8(REG_EAX, REG_AL);
1994		_push_r32(REG_EAX);
	2033	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2034	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	2035	emit_movzx_r32_r8(DRCTOP, REG_EAX, REG_AL);
	2036	emit_push_r32(DRCTOP, REG_EAX);
1995	2037
1996	2038	if (RA == 0)
1997	2039	{
1998		_push_imm(SIMM16);
	2040	emit_push_imm(DRCTOP, SIMM16);
1999	2041	}
2000	2042	else
2001	2043	{
2002		_mov_r32_m32abs(REG_EAX, &REG(RA));
2003		_add_r32_imm(REG_EAX, SIMM16);
2004		_push_r32(REG_EAX);
	2044	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2045	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	2046	emit_push_r32(DRCTOP, REG_EAX);
2005	2047	}
2006		_call((genf *)WRITE8);
2007		_add_r32_imm(REG_ESP, 8);
2008		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2048	emit_call(DRCTOP, (x86code *)WRITE8);
	2049	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2050	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2009	2051
2010	2052	return RECOMPILE_SUCCESSFUL_CP(1,4);
2011	2053	}
2012	2054
2013	2055	static UINT32 recompile_stbu(drc_core *drc, UINT32 op)
2014	2056	{
2015		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2016		_mov_r32_m32abs(REG_EAX, &REG(RS));
2017		_movzx_r32_r8(REG_EAX, REG_AL);
2018		_push_r32(REG_EAX);
	2057	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2058	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	2059	emit_movzx_r32_r8(DRCTOP, REG_EAX, REG_AL);
	2060	emit_push_r32(DRCTOP, REG_EAX);
2019	2061
2020		_mov_r32_m32abs(REG_EDX, &REG(RA));
2021		_add_r32_imm(REG_EDX, SIMM16);
2022		_mov_m32abs_r32(&REG(RA), REG_EDX);
2023		_push_r32(REG_EDX);
2024		_call((genf *)WRITE8);
2025		_add_r32_imm(REG_ESP, 8);
2026		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2062	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2063	emit_add_r32_imm(DRCTOP, REG_EDX, SIMM16);
	2064	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	2065	emit_push_r32(DRCTOP, REG_EDX);
	2066	emit_call(DRCTOP, (x86code *)WRITE8);
	2067	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2068	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2027	2069
2028	2070	return RECOMPILE_SUCCESSFUL_CP(1,4);
2029	2071	}
2030	2072
2031	2073	static UINT32 recompile_stbux(drc_core *drc, UINT32 op)
2032	2074	{
2033		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2034		_mov_r32_m32abs(REG_EAX, &REG(RS));
2035		_movzx_r32_r8(REG_EAX, REG_AL);
2036		_push_r32(REG_EAX);
	2075	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2076	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	2077	emit_movzx_r32_r8(DRCTOP, REG_EAX, REG_AL);
	2078	emit_push_r32(DRCTOP, REG_EAX);
2037	2079
2038		_mov_r32_m32abs(REG_EDX, &REG(RA));
2039		_add_r32_m32abs(REG_EDX, &REG(RB));
2040		_mov_m32abs_r32(&REG(RA), REG_EDX);
2041		_push_r32(REG_EDX);
2042		_call((genf *)WRITE8);
2043		_add_r32_imm(REG_ESP, 8);
2044		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2080	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2081	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	2082	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	2083	emit_push_r32(DRCTOP, REG_EDX);
	2084	emit_call(DRCTOP, (x86code *)WRITE8);
	2085	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2086	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2045	2087
2046	2088	return RECOMPILE_SUCCESSFUL_CP(1,4);
2047	2089	}
2048	2090
2049	2091	static UINT32 recompile_stbx(drc_core *drc, UINT32 op)
2050	2092	{
2051		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2052		_mov_r32_m32abs(REG_EAX, &REG(RS));
2053		_movzx_r32_r8(REG_EAX, REG_AL);
2054		_push_r32(REG_EAX);
	2093	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2094	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	2095	emit_movzx_r32_r8(DRCTOP, REG_EAX, REG_AL);
	2096	emit_push_r32(DRCTOP, REG_EAX);
2055	2097
2056		_mov_r32_m32~~abs~~(REG_EDX, &REG(RB));
	2098	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
2057	2099	if (RA != 0)
2058	2100	{
2059		_add_r32_m32~~abs~~(REG_EDX, &REG(RA));
	2101	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
2060	2102	}
2061		_push_r32(REG_EDX);
2062		_call((genf *)WRITE8);
2063		_add_r32_imm(REG_ESP, 8);
2064		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2103	emit_push_r32(DRCTOP, REG_EDX);
	2104	emit_call(DRCTOP, (x86code *)WRITE8);
	2105	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2106	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2065	2107
2066	2108	return RECOMPILE_SUCCESSFUL_CP(1,4);
2067	2109	}
2068	2110
2069	2111	static UINT32 recompile_sth(drc_core *drc, UINT32 op)
2070	2112	{
2071		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2072		_mov_r32_m32abs(REG_EAX, &REG(RS));
2073		_movzx_r32_r16(REG_EAX, REG_AX);
2074		_push_r32(REG_EAX);
	2113	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2114	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	2115	emit_movzx_r32_r16(DRCTOP, REG_EAX, REG_AX);
	2116	emit_push_r32(DRCTOP, REG_EAX);
2075	2117
2076	2118	if (RA == 0)
2077	2119	{
2078		_push_imm(SIMM16);
	2120	emit_push_imm(DRCTOP, SIMM16);
2079	2121	}
2080	2122	else
2081	2123	{
2082		_mov_r32_m32abs(REG_EDX, &REG(RA));
2083		_add_r32_imm(REG_EDX, SIMM16);
2084		_push_r32(REG_EDX);
	2124	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2125	emit_add_r32_imm(DRCTOP, REG_EDX, SIMM16);
	2126	emit_push_r32(DRCTOP, REG_EDX);
2085	2127	}
2086		_call((genf *)WRITE16);
2087		_add_r32_imm(REG_ESP, 8);
2088		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2128	emit_call(DRCTOP, (x86code *)WRITE16);
	2129	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2130	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2089	2131
2090	2132	return RECOMPILE_SUCCESSFUL_CP(1,4);
2091	2133	}
2092	2134
2093	2135	static UINT32 recompile_sthbrx(drc_core *drc, UINT32 op)
2094	2136	{
2095		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2096		_mov_r32_m32abs(REG_EAX, &REG(RS));
2097		_movzx_r32_r16(REG_EAX, REG_AX);
2098		_mov_r32_imm(REG_ECX, 8);
2099		_rol_r16_cl(REG_AX);
2100		_push_r32(REG_EAX);
	2137	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2138	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	2139	emit_movzx_r32_r16(DRCTOP, REG_EAX, REG_AX);
	2140	emit_mov_r32_imm(DRCTOP, REG_ECX, 8);
	2141	emit_rol_r16_cl(DRCTOP, REG_AX);
	2142	emit_push_r32(DRCTOP, REG_EAX);
2101	2143
2102		_mov_r32_m32~~abs~~(REG_EDX, &REG(RB));
	2144	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
2103	2145	if (RA != 0)
2104	2146	{
2105		_add_r32_m32~~abs~~(REG_EDX, &REG(RA));
	2147	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
2106	2148	}
2107		_push_r32(REG_EDX);
2108		_call((genf *)WRITE16);
2109		_add_r32_imm(REG_ESP, 8);
2110		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2149	emit_push_r32(DRCTOP, REG_EDX);
	2150	emit_call(DRCTOP, (x86code *)WRITE16);
	2151	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2152	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2111	2153
2112	2154	return RECOMPILE_SUCCESSFUL_CP(1,4);
2113	2155	}
2114	2156
2115	2157	static UINT32 recompile_sthu(drc_core *drc, UINT32 op)
2116	2158	{
2117		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2118		_mov_r32_m32abs(REG_EAX, &REG(RS));
2119		_movzx_r32_r16(REG_EAX, REG_AX);
2120		_push_r32(REG_EAX);
	2159	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2160	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	2161	emit_movzx_r32_r16(DRCTOP, REG_EAX, REG_AX);
	2162	emit_push_r32(DRCTOP, REG_EAX);
2121	2163
2122		_mov_r32_m32abs(REG_EDX, &REG(RA));
2123		_add_r32_imm(REG_EDX, SIMM16);
2124		_mov_m32abs_r32(&REG(RA), REG_EDX);
2125		_push_r32(REG_EDX);
2126		_call((genf *)WRITE16);
2127		_add_r32_imm(REG_ESP, 8);
2128		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2164	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2165	emit_add_r32_imm(DRCTOP, REG_EDX, SIMM16);
	2166	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	2167	emit_push_r32(DRCTOP, REG_EDX);
	2168	emit_call(DRCTOP, (x86code *)WRITE16);
	2169	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2170	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2129	2171
2130	2172	return RECOMPILE_SUCCESSFUL_CP(1,4);
2131	2173	}
2132	2174
2133	2175	static UINT32 recompile_sthux(drc_core *drc, UINT32 op)
2134	2176	{
2135		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2136		_mov_r32_m32abs(REG_EAX, &REG(RS));
2137		_movzx_r32_r16(REG_EAX, REG_AX);
2138		_push_r32(REG_EAX);
	2177	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2178	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	2179	emit_movzx_r32_r16(DRCTOP, REG_EAX, REG_AX);
	2180	emit_push_r32(DRCTOP, REG_EAX);
2139	2181
2140		_mov_r32_m32abs(REG_EDX, &REG(RA));
2141		_add_r32_m32abs(REG_EDX, &REG(RB));
2142		_mov_m32abs_r32(&REG(RA), REG_EDX);
2143		_push_r32(REG_EDX);
2144		_call((genf *)WRITE16);
2145		_add_r32_imm(REG_ESP, 8);
2146		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2182	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2183	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	2184	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	2185	emit_push_r32(DRCTOP, REG_EDX);
	2186	emit_call(DRCTOP, (x86code *)WRITE16);
	2187	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2188	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2147	2189
2148	2190	return RECOMPILE_SUCCESSFUL_CP(1,4);
2149	2191	}
2150	2192
2151	2193	static UINT32 recompile_sthx(drc_core *drc, UINT32 op)
2152	2194	{
2153		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2154		_mov_r32_m32abs(REG_EAX, &REG(RS));
2155		_movzx_r32_r16(REG_EAX, REG_AX);
2156		_push_r32(REG_EAX);
	2195	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2196	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	2197	emit_movzx_r32_r16(DRCTOP, REG_EAX, REG_AX);
	2198	emit_push_r32(DRCTOP, REG_EAX);
2157	2199
2158		_mov_r32_m32~~abs~~(REG_EDX, &REG(RB));
	2200	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
2159	2201	if (RA != 0)
2160	2202	{
2161		_add_r32_m32~~abs~~(REG_EDX, &REG(RA));
	2203	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
2162	2204	}
2163		_push_r32(REG_EDX);
2164		_call((genf *)WRITE16);
2165		_add_r32_imm(REG_ESP, 8);
2166		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2205	emit_push_r32(DRCTOP, REG_EDX);
	2206	emit_call(DRCTOP, (x86code *)WRITE16);
	2207	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2208	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2167	2209
2168	2210	return RECOMPILE_SUCCESSFUL_CP(1,4);
2169	2211	}
2170	2212
2171	2213	static UINT32 recompile_stmw(drc_core *drc, UINT32 op)
2172	2214	{
2173		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2174		_push_imm(op);
2175		_call((genf *)ppc_stmw);
2176		_add_r32_imm(REG_ESP, 4);
2177		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2215	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2216	emit_push_imm(DRCTOP, op);
	2217	emit_call(DRCTOP, (x86code *)ppc_stmw);
	2218	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2219	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2178	2220
2179	2221	return RECOMPILE_SUCCESSFUL_CP(1,4);
2180	2222	}
2181	2223
2182	2224	static UINT32 recompile_stswi(drc_core *drc, UINT32 op)
2183	2225	{
2184		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2185		_push_imm(op);
2186		_call((genf *)ppc_stswi);
2187		_add_r32_imm(REG_ESP, 4);
2188		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2226	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2227	emit_push_imm(DRCTOP, op);
	2228	emit_call(DRCTOP, (x86code *)ppc_stswi);
	2229	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2230	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2189	2231
2190	2232	return RECOMPILE_SUCCESSFUL_CP(1,4);
2191	2233	}
2192	2234
2193	2235	static UINT32 recompile_stswx(drc_core *drc, UINT32 op)
2194	2236	{
2195		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2196		_push_imm(op);
2197		_call((genf *)ppc_stswx);
2198		_add_r32_imm(REG_ESP, 4);
2199		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2237	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2238	emit_push_imm(DRCTOP, op);
	2239	emit_call(DRCTOP, (x86code *)ppc_stswx);
	2240	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2241	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2200	2242
2201	2243	return RECOMPILE_SUCCESSFUL_CP(1,4);
2202	2244	}
2203	2245
2204	2246	static UINT32 recompile_stw(drc_core *drc, UINT32 op)
2205	2247	{
2206		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2207		_push_m32abs(&REG(RS));
	2248	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2249	emit_push_m32(DRCTOP, MABS(&REG(RS)));
2208	2250	if (RA == 0)
2209	2251	{
2210		_push_imm(SIMM16);
	2252	emit_push_imm(DRCTOP, SIMM16);
2211	2253	}
2212	2254	else
2213	2255	{
2214		_mov_r32_m32abs(REG_EAX, &REG(RA));
2215		_add_r32_imm(REG_EAX, SIMM16);
2216		_push_r32(REG_EAX);
	2256	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2257	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	2258	emit_push_r32(DRCTOP, REG_EAX);
2217	2259	}
2218		_call((genf *)WRITE32);
2219		_add_r32_imm(REG_ESP, 8);
2220		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2260	emit_call(DRCTOP, (x86code *)WRITE32);
	2261	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2262	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2221	2263
2222	2264	return RECOMPILE_SUCCESSFUL_CP(1,4);
2223	2265	}
2224	2266
2225	2267	static UINT32 recompile_stwbrx(drc_core *drc, UINT32 op)
2226	2268	{
2227		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2228		_mov_r32_m32abs(REG_EAX, &REG(RS));
2229		_bswap_r32(REG_EAX);
2230		_push_r32(REG_EAX);
	2269	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2270	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RS)));
	2271	emit_bswap_r32(DRCTOP, REG_EAX);
	2272	emit_push_r32(DRCTOP, REG_EAX);
2231	2273
2232		_mov_r32_m32~~abs~~(REG_EDX, &REG(RB));
	2274	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
2233	2275	if (RA != 0)
2234	2276	{
2235		_add_r32_m32~~abs~~(REG_EDX, &REG(RA));
	2277	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
2236	2278	}
2237		_push_r32(REG_EDX);
2238		_call((genf *)WRITE32);
2239		_add_r32_imm(REG_ESP, 8);
2240		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2279	emit_push_r32(DRCTOP, REG_EDX);
	2280	emit_call(DRCTOP, (x86code *)WRITE32);
	2281	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2282	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2241	2283
2242	2284	return RECOMPILE_SUCCESSFUL_CP(1,4);
2243	2285	}
2244	2286
2245	2287	static UINT32 recompile_stwcx_rc(drc_core *drc, UINT32 op)
2246	2288	{
2247		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2248		_push_imm(op);
2249		_call((genf *)ppc_stwcx_rc);
2250		_add_r32_imm(REG_ESP, 4);
2251		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2289	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2290	emit_push_imm(DRCTOP, op);
	2291	emit_call(DRCTOP, (x86code *)ppc_stwcx_rc);
	2292	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2293	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2252	2294
2253	2295	return RECOMPILE_SUCCESSFUL_CP(1,4);
2254	2296	}
2255	2297
2256	2298	static UINT32 recompile_stwu(drc_core *drc, UINT32 op)
2257	2299	{
2258		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2259		_push_m32abs(&REG(RS));
	2300	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2301	emit_push_m32(DRCTOP, MABS(&REG(RS)));
2260	2302
2261		_mov_r32_m32abs(REG_EAX, &REG(RA));
2262		_add_r32_imm(REG_EAX, SIMM16);
2263		_mov_m32abs_r32(&REG(RA), REG_EAX);
2264		_push_r32(REG_EAX);
2265		_call((genf *)WRITE32);
2266		_add_r32_imm(REG_ESP, 8);
2267		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2303	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2304	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	2305	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EAX);
	2306	emit_push_r32(DRCTOP, REG_EAX);
	2307	emit_call(DRCTOP, (x86code *)WRITE32);
	2308	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2309	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2268	2310
2269	2311	return RECOMPILE_SUCCESSFUL_CP(1,4);
2270	2312	}
2271	2313
2272	2314	static UINT32 recompile_stwux(drc_core *drc, UINT32 op)
2273	2315	{
2274		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2275		_push_m32abs(&REG(RS));
	2316	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2317	emit_push_m32(DRCTOP, MABS(&REG(RS)));
2276	2318
2277		_mov_r32_m32abs(REG_EAX, &REG(RA));
2278		_add_r32_m32abs(REG_EAX, &REG(RB));
2279		_mov_m32abs_r32(&REG(RA), REG_EAX);
2280		_push_r32(REG_EAX);
2281		_call((genf *)WRITE32);
2282		_add_r32_imm(REG_ESP, 8);
2283		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2319	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2320	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
	2321	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EAX);
	2322	emit_push_r32(DRCTOP, REG_EAX);
	2323	emit_call(DRCTOP, (x86code *)WRITE32);
	2324	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2325	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2284	2326
2285	2327	return RECOMPILE_SUCCESSFUL_CP(1,4);
2286	2328	}
2287	2329
2288	2330	static UINT32 recompile_stwx(drc_core *drc, UINT32 op)
2289	2331	{
2290		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2291		_push_m32abs(&REG(RS));
	2332	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2333	emit_push_m32(DRCTOP, MABS(&REG(RS)));
2292	2334
2293		_mov_r32_m32~~abs~~(REG_EAX, &REG(RB));
	2335	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
2294	2336	if (RA != 0)
2295	2337	{
2296		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	2338	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
2297	2339	}
2298		_push_r32(REG_EAX);
2299		_call((genf *)WRITE32);
2300		_add_r32_imm(REG_ESP, 8);
2301		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2340	emit_push_r32(DRCTOP, REG_EAX);
	2341	emit_call(DRCTOP, (x86code *)WRITE32);
	2342	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
	2343	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2302	2344
2303	2345	return RECOMPILE_SUCCESSFUL_CP(1,4);
2304	2346	}
2305	2347
2306	2348	static UINT32 recompile_subfx(drc_core *drc, UINT32 op)
2307	2349	{
2308		_mov_r32_m32abs(REG_EDX, &REG(RB));
2309		_sub_r32_m32abs(REG_EDX, &REG(RA));
2310		_mov_m32abs_r32(&REG(RT), REG_EDX);
	2350	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	2351	emit_sub_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2352	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
2311	2353
2312	2354	if (OEBIT) {
2313	2355	mame_printf_debug("recompile_subfx: OEBIT set !\n");
r949	r950
2324	2366	{
2325	2367	if (OEBIT)
2326	2368	{
2327		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2328		_push_imm(op);
2329		_call((genf *)ppc_subfcx);
2330		_add_r32_imm(REG_ESP, 4);
2331		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2369	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2370	emit_push_imm(DRCTOP, op);
	2371	emit_call(DRCTOP, (x86code *)ppc_subfcx);
	2372	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2373	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2332	2374	}
2333	2375	else
2334	2376	{
2335		_xor_r32_r32(REG_EAX, REG_EAX);
2336		_mov_r32_m32abs(REG_EBX, &XER);
2337		_and_r32_imm(REG_EBX, ~0x20000000); // clear carry
2338		_mov_r32_m32abs(REG_EDX, &REG(RB));
2339		_sub_r32_m32abs(REG_EDX, &REG(RA));
2340		_mov_m32abs_r32(&REG(RT), REG_EDX);
2341		_setcc_r8(COND_NC, REG_AL); // subtract carry is inverse
2342		_shl_r32_imm(REG_EAX, 29); // move carry to correct location in XER
2343		_or_r32_r32(REG_EBX, REG_EAX); // insert carry to XER
2344		_mov_m32abs_r32(&XER, REG_EBX);
	2377	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	2378	emit_mov_r32_m32(DRCTOP, REG_EBX, MABS(&XER));
	2379	emit_and_r32_imm(DRCTOP, REG_EBX, ~0x20000000); // clear carry
	2380	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	2381	emit_sub_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2382	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
	2383	emit_setcc_r8(DRCTOP, COND_NC, REG_AL); // subtract carry is inverse
	2384	emit_shl_r32_imm(DRCTOP, REG_EAX, 29); // move carry to correct location in XER
	2385	emit_or_r32_r32(DRCTOP, REG_EBX, REG_EAX); // insert carry to XER
	2386	emit_mov_m32_r32(DRCTOP, MABS(&XER), REG_EBX);
2345	2387
2346	2388	//if (OEBIT) {
2347	2389	// mame_printf_debug("recompile_subfcx: OEBIT set !\n");
r949	r950
2356	2398
2357	2399	static UINT32 recompile_subfex(drc_core *drc, UINT32 op)
2358	2400	{
2359		_xor_r32_r32(REG_EAX, REG_EAX);
2360		_mov_r32_m32abs(REG_EBX, &XER);
2361		_mov_r32_m32abs(REG_EDX, &REG(RB));
2362		_mov_r32_m32abs(REG_ECX, &REG(RA));
2363		_bt_r32_imm(REG_EBX, 29); // XER carry to carry flag
2364		_cmc(); // invert carry
2365		_adc_r32_imm(REG_ECX, 0);
2366		_sub_r32_r32(REG_EDX, REG_ECX);
2367		_mov_m32abs_r32(&REG(RT), REG_EDX);
2368		_setcc_r8(COND_NC, REG_AL); // subtract carry is inverse
2369		_and_r32_imm(REG_EBX, ~0x20000000); // clear carry
2370		_shl_r32_imm(REG_EAX, 29); // move carry to correct location in XER
2371		_or_r32_r32(REG_EBX, REG_EAX); // insert carry to XER
2372		_mov_m32abs_r32(&XER, REG_EBX);
	2401	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	2402	emit_mov_r32_m32(DRCTOP, REG_EBX, MABS(&XER));
	2403	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	2404	emit_mov_r32_m32(DRCTOP, REG_ECX, MABS(&REG(RA)));
	2405	emit_bt_r32_imm(DRCTOP, REG_EBX, 29); // XER carry to carry flag
	2406	emit_cmc(DRCTOP); // invert carry
	2407	emit_adc_r32_imm(DRCTOP, REG_ECX, 0);
	2408	emit_sub_r32_r32(DRCTOP, REG_EDX, REG_ECX);
	2409	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
	2410	emit_setcc_r8(DRCTOP, COND_NC, REG_AL); // subtract carry is inverse
	2411	emit_and_r32_imm(DRCTOP, REG_EBX, ~0x20000000); // clear carry
	2412	emit_shl_r32_imm(DRCTOP, REG_EAX, 29); // move carry to correct location in XER
	2413	emit_or_r32_r32(DRCTOP, REG_EBX, REG_EAX); // insert carry to XER
	2414	emit_mov_m32_r32(DRCTOP, MABS(&XER), REG_EBX);
2373	2415
2374	2416	if (OEBIT) {
2375	2417	mame_printf_debug("recompile_subfex: OEBIT set !\n");
r949	r950
2384	2426
2385	2427	static UINT32 recompile_subfic(drc_core *drc, UINT32 op)
2386	2428	{
2387		_xor_r32_r32(REG_EAX, REG_EAX);
2388		_mov_r32_m32abs(REG_EBX, &XER);
2389		_and_r32_imm(REG_EBX, ~0x20000000); // clear carry
2390		_mov_r32_imm(REG_EDX, SIMM16);
2391		_sub_r32_m32abs(REG_EDX, &REG(RA));
2392		_mov_m32abs_r32(&REG(RT), REG_EDX);
2393		_setcc_r8(COND_NC, REG_AL); // subtract carry is inverse
2394		_shl_r32_imm(REG_EAX, 29); // move carry to correct location in XER
2395		_or_r32_r32(REG_EBX, REG_EAX); // insert carry to XER
2396		_mov_m32abs_r32(&XER, REG_EBX);
	2429	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX);
	2430	emit_mov_r32_m32(DRCTOP, REG_EBX, MABS(&XER));
	2431	emit_and_r32_imm(DRCTOP, REG_EBX, ~0x20000000); // clear carry
	2432	emit_mov_r32_imm(DRCTOP, REG_EDX, SIMM16);
	2433	emit_sub_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2434	emit_mov_m32_r32(DRCTOP, MABS(&REG(RT)), REG_EDX);
	2435	emit_setcc_r8(DRCTOP, COND_NC, REG_AL); // subtract carry is inverse
	2436	emit_shl_r32_imm(DRCTOP, REG_EAX, 29); // move carry to correct location in XER
	2437	emit_or_r32_r32(DRCTOP, REG_EBX, REG_EAX); // insert carry to XER
	2438	emit_mov_m32_r32(DRCTOP, MABS(&XER), REG_EBX);
2397	2439
2398	2440	return RECOMPILE_SUCCESSFUL_CP(1,4);
2399	2441	}
2400	2442
2401	2443	static UINT32 recompile_subfmex(drc_core *drc, UINT32 op)
2402	2444	{
2403		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2404		_push_imm(op);
2405		_call((genf *)ppc_subfmex);
2406		_add_r32_imm(REG_ESP, 4);
2407		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2445	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2446	emit_push_imm(DRCTOP, op);
	2447	emit_call(DRCTOP, (x86code *)ppc_subfmex);
	2448	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2449	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2408	2450
2409	2451	return RECOMPILE_SUCCESSFUL_CP(1,4);
2410	2452	}
2411	2453
2412	2454	static UINT32 recompile_subfzex(drc_core *drc, UINT32 op)
2413	2455	{
2414		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2415		_push_imm(op);
2416		_call((genf *)ppc_subfzex);
2417		_add_r32_imm(REG_ESP, 4);
2418		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2456	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2457	emit_push_imm(DRCTOP, op);
	2458	emit_call(DRCTOP, (x86code *)ppc_subfzex);
	2459	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2460	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2419	2461
2420	2462	return RECOMPILE_SUCCESSFUL_CP(1,4);
2421	2463	}
r949	r950
2427	2469
2428	2470	static UINT32 recompile_tw(drc_core *drc, UINT32 op)
2429	2471	{
2430		link_info link1 = {0}, link2 = {0}, link3 = {0}, link4 = {0}, link5 = {0}, link6 = {0};
	2472	emit_link link1 = {0}, link2 = {0}, link3 = {0}, link4 = {0}, link5 = {0}, link6 = {0};
2431	2473	int do_link1 = 0;
2432	2474	int do_link2 = 0;
2433	2475	int do_link3 = 0;
2434	2476	int do_link4 = 0;
2435	2477	int do_link5 = 0;
2436	2478
2437		_mov_r32_m32abs(REG_EAX, &REG(RA));
2438		_mov_r32_m32abs(REG_EDX, &REG(RB));
2439		_cmp_r32_r32(REG_EAX, REG_EDX);
	2479	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2480	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	2481	emit_cmp_r32_r32(DRCTOP, REG_EAX, REG_EDX);
2440	2482
2441	2483	if (RT & 0x10) {
2442		_jcc_near_link(COND_L, &link1); // less than = signed <
	2484	emit_jcc_near_link(DRCTOP, COND_L, &link1); // less than = signed <
2443	2485	do_link1 = 1;
2444	2486	}
2445	2487	if (RT & 0x08) {
2446		_jcc_near_link(COND_G, &link2); // greater = signed >
	2488	emit_jcc_near_link(DRCTOP, COND_G, &link2); // greater = signed >
2447	2489	do_link2 = 1;
2448	2490	}
2449	2491	if (RT & 0x04) {
2450		_jcc_near_link(COND_E, &link3); // equal
	2492	emit_jcc_near_link(DRCTOP, COND_E, &link3); // equal
2451	2493	do_link3 = 1;
2452	2494	}
2453	2495	if (RT & 0x02) {
2454		_jcc_near_link(COND_B, &link4); // below = unsigned <
	2496	emit_jcc_near_link(DRCTOP, COND_B, &link4); // below = unsigned <
2455	2497	do_link4 = 1;
2456	2498	}
2457	2499	if (RT & 0x01) {
2458		_jcc_near_link(COND_A, &link5); // above = unsigned >
	2500	emit_jcc_near_link(DRCTOP, COND_A, &link5); // above = unsigned >
2459	2501	do_link5 = 1;
2460	2502	}
2461		_jmp_near_link(&link6);
	2503	emit_jmp_near_link(DRCTOP, &link6);
2462	2504
2463	2505	if (do_link1) {
2464		_resolve_link(&link1);
	2506	resolve_link(DRCTOP, &link1);
2465	2507	}
2466	2508	if (do_link2) {
2467		_resolve_link(&link2);
	2509	resolve_link(DRCTOP, &link2);
2468	2510	}
2469	2511	if (do_link3) {
2470		_resolve_link(&link3);
	2512	resolve_link(DRCTOP, &link3);
2471	2513	}
2472	2514	if (do_link4) {
2473		_resolve_link(&link4);
	2515	resolve_link(DRCTOP, &link4);
2474	2516	}
2475	2517	if (do_link5) {
2476		_resolve_link(&link5);
	2518	resolve_link(DRCTOP, &link5);
2477	2519	}
2478	2520	// generate exception
2479		_mov_m32abs_imm(&SRR0, temp_ppc_pc + 4);
2480		_jmp(ppc.generate_trap_exception);
	2521	emit_mov_m32_imm(DRCTOP, MABS(&SRR0), temp_ppc_pc + 4);
	2522	emit_jmp(DRCTOP, ppc.generate_trap_exception);
2481	2523
2482	2524	// no exception
2483		_resolve_link(&link6);
	2525	resolve_link(DRCTOP, &link6);
2484	2526
2485	2527	return RECOMPILE_SUCCESSFUL_CP(1,4);
2486	2528	}
2487	2529
2488	2530	static UINT32 recompile_twi(drc_core *drc, UINT32 op)
2489	2531	{
2490		link_info link1 = {0}, link2 = {0}, link3 = {0}, link4 = {0}, link5 = {0}, link6 = {0};
	2532	emit_link link1 = {0}, link2 = {0}, link3 = {0}, link4 = {0}, link5 = {0}, link6 = {0};
2491	2533	int do_link1 = 0;
2492	2534	int do_link2 = 0;
2493	2535	int do_link3 = 0;
2494	2536	int do_link4 = 0;
2495	2537	int do_link5 = 0;
2496	2538
2497		_mov_r32_m32abs(REG_EAX, &REG(RA));
2498		_mov_r32_imm(REG_EDX, SIMM16);
2499		_cmp_r32_r32(REG_EAX, REG_EDX);
	2539	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2540	emit_mov_r32_imm(DRCTOP, REG_EDX, SIMM16);
	2541	emit_cmp_r32_r32(DRCTOP, REG_EAX, REG_EDX);
2500	2542
2501	2543	if (RT & 0x10) {
2502		_jcc_near_link(COND_L, &link1); // less than = signed <
	2544	emit_jcc_near_link(DRCTOP, COND_L, &link1); // less than = signed <
2503	2545	do_link1 = 1;
2504	2546	}
2505	2547	if (RT & 0x08) {
2506		_jcc_near_link(COND_G, &link2); // greater = signed >
	2548	emit_jcc_near_link(DRCTOP, COND_G, &link2); // greater = signed >
2507	2549	do_link2 = 1;
2508	2550	}
2509	2551	if (RT & 0x04) {
2510		_jcc_near_link(COND_E, &link3); // equal
	2552	emit_jcc_near_link(DRCTOP, COND_E, &link3); // equal
2511	2553	do_link3 = 1;
2512	2554	}
2513	2555	if (RT & 0x02) {
2514		_jcc_near_link(COND_B, &link4); // below = unsigned <
	2556	emit_jcc_near_link(DRCTOP, COND_B, &link4); // below = unsigned <
2515	2557	do_link4 = 1;
2516	2558	}
2517	2559	if (RT & 0x01) {
2518		_jcc_near_link(COND_A, &link5); // above = unsigned >
	2560	emit_jcc_near_link(DRCTOP, COND_A, &link5); // above = unsigned >
2519	2561	do_link5 = 1;
2520	2562	}
2521		_jmp_near_link(&link6);
	2563	emit_jmp_near_link(DRCTOP, &link6);
2522	2564
2523	2565	if (do_link1) {
2524		_resolve_link(&link1);
	2566	resolve_link(DRCTOP, &link1);
2525	2567	}
2526	2568	if (do_link2) {
2527		_resolve_link(&link2);
	2569	resolve_link(DRCTOP, &link2);
2528	2570	}
2529	2571	if (do_link3) {
2530		_resolve_link(&link3);
	2572	resolve_link(DRCTOP, &link3);
2531	2573	}
2532	2574	if (do_link4) {
2533		_resolve_link(&link4);
	2575	resolve_link(DRCTOP, &link4);
2534	2576	}
2535	2577	if (do_link5) {
2536		_resolve_link(&link5);
	2578	resolve_link(DRCTOP, &link5);
2537	2579	}
2538	2580	// generate exception
2539		_mov_m32abs_imm(&SRR0, temp_ppc_pc + 4);
2540		_jmp(ppc.generate_trap_exception);
	2581	emit_mov_m32_imm(DRCTOP, MABS(&SRR0), temp_ppc_pc + 4);
	2582	emit_jmp(DRCTOP, ppc.generate_trap_exception);
2541	2583
2542	2584	// no exception
2543		_resolve_link(&link6);
	2585	resolve_link(DRCTOP, &link6);
2544	2586
2545	2587	return RECOMPILE_SUCCESSFUL_CP(1,4);
2546	2588	}
2547	2589
2548	2590	static UINT32 recompile_xorx(drc_core *drc, UINT32 op)
2549	2591	{
2550		_mov_r32_m32abs(REG_EDX, &REG(RS));
2551		_xor_r32_m32abs(REG_EDX, &REG(RB));
2552		_mov_m32abs_r32(&REG(RA), REG_EDX);
	2592	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	2593	emit_xor_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	2594	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
2553	2595
2554	2596	if (RCBIT) {
2555	2597	append_set_cr0(drc);
r949	r950
2560	2602
2561	2603	static UINT32 recompile_xori(drc_core *drc, UINT32 op)
2562	2604	{
2563		_mov_r32_m32abs(REG_EDX, &REG(RS));
2564		_xor_r32_imm(REG_EDX, UIMM16);
2565		_mov_m32abs_r32(&REG(RA), REG_EDX);
	2605	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	2606	emit_xor_r32_imm(DRCTOP, REG_EDX, UIMM16);
	2607	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
2566	2608
2567	2609	return RECOMPILE_SUCCESSFUL_CP(1,4);
2568	2610	}
2569	2611
2570	2612	static UINT32 recompile_xoris(drc_core *drc, UINT32 op)
2571	2613	{
2572		_mov_r32_m32abs(REG_EDX, &REG(RS));
2573		_xor_r32_imm(REG_EDX, UIMM16 << 16);
2574		_mov_m32abs_r32(&REG(RA), REG_EDX);
	2614	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RS)));
	2615	emit_xor_r32_imm(DRCTOP, REG_EDX, UIMM16 << 16);
	2616	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
2575	2617
2576	2618	return RECOMPILE_SUCCESSFUL_CP(1,4);
2577	2619	}
r949	r950
2610	2652	#if HAS_PPC403
2611	2653	static UINT32 recompile_mfdcr(drc_core *drc, UINT32 op)
2612	2654	{
2613		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2614		_push_imm(op);
2615		_call((genf *)ppc_mfdcr);
2616		_add_r32_imm(REG_ESP, 4);
2617		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2655	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2656	emit_push_imm(DRCTOP, op);
	2657	emit_call(DRCTOP, (x86code *)ppc_mfdcr);
	2658	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2659	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2618	2660
2619	2661	return RECOMPILE_SUCCESSFUL_CP(1,4);
2620	2662	}
2621	2663
2622	2664	static UINT32 recompile_mtdcr(drc_core *drc, UINT32 op)
2623	2665	{
2624		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2625		_push_imm(op);
2626		_call((genf *)ppc_mtdcr);
2627		_add_r32_imm(REG_ESP, 4);
2628		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2666	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2667	emit_push_imm(DRCTOP, op);
	2668	emit_call(DRCTOP, (x86code *)ppc_mtdcr);
	2669	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2670	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2629	2671
2630	2672	return RECOMPILE_SUCCESSFUL_CP(1,4);
2631	2673	}
2632	2674
2633	2675	static UINT32 recompile_wrtee(drc_core *drc, UINT32 op)
2634	2676	{
2635		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2636		_push_imm(op);
2637		_call((genf *)ppc_wrtee);
2638		_add_r32_imm(REG_ESP, 4);
2639		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2677	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2678	emit_push_imm(DRCTOP, op);
	2679	emit_call(DRCTOP, (x86code *)ppc_wrtee);
	2680	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2681	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2640	2682
2641	2683	return RECOMPILE_SUCCESSFUL_CP(1,4);
2642	2684	}
2643	2685
2644	2686	static UINT32 recompile_wrteei(drc_core *drc, UINT32 op)
2645	2687	{
2646		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2647		_push_imm(op);
2648		_call((genf *)ppc_wrteei);
2649		_add_r32_imm(REG_ESP, 4);
2650		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2688	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2689	emit_push_imm(DRCTOP, op);
	2690	emit_call(DRCTOP, (x86code *)ppc_wrteei);
	2691	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2692	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2651	2693
2652	2694	return RECOMPILE_SUCCESSFUL_CP(1,4);
2653	2695	}
r949	r950
2667	2709
2668	2710	static UINT32 recompile_lfs(drc_core *drc,UINT32 op)
2669	2711	{
2670		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	2712	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
2671	2713	#if USE_SSE2
2672	2714	if (RA == 0)
2673	2715	{
2674		_push_imm(SIMM16);
	2716	emit_push_imm(DRCTOP, SIMM16);
2675	2717	}
2676	2718	else
2677	2719	{
2678		_mov_r32_m32abs(REG_EAX, &REG(RA));
2679		_add_r32_imm(REG_EAX, SIMM16);
2680		_push_r32(REG_EAX);
	2720	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2721	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	2722	emit_push_r32(DRCTOP, REG_EAX);
2681	2723	}
2682		_call((genf*)READ32);
2683		_add_r32_imm(REG_ESP, 4);
2684		_movd_r128_r32(REG_XMM0, REG_EAX);
2685		_cvtss2sd_r128_r128(REG_XMM1, REG_XMM0); // convert float to double
2686		_movq_m64abs_r128(&FPR(RT), REG_XMM1);
	2724	emit_call(DRCTOP, (genf*)READ32);
	2725	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2726	emit_movd_r128_r32(DRCTOP, REG_XMM0, REG_EAX);
	2727	emit_cvtss2sd_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // convert float to double
	2728	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM1);
2687	2729	#else
2688		_push_imm(op);
2689		_call((genf *)ppc_lfs);
2690		_add_r32_imm(REG_ESP, 4);
	2730	emit_push_imm(DRCTOP, op);
	2731	emit_call(DRCTOP, (x86code *)ppc_lfs);
	2732	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
2691	2733	#endif
2692		_mov_r32_m32~~abs~~(REG_EBP, &ppc_icount);
	2734	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2693	2735
2694	2736	return RECOMPILE_SUCCESSFUL_CP(1,4);
2695	2737	}
2696	2738
2697	2739	static UINT32 recompile_lfsu(drc_core *drc, UINT32 op)
2698	2740	{
2699		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	2741	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
2700	2742	#if USE_SSE2
2701		_mov_r32_m32abs(REG_EDX, &REG(RA));
2702		_add_r32_imm(REG_EDX, SIMM16);
2703		_mov_m32abs_r32(&REG(RA), REG_EDX);
2704		_push_r32(REG_EDX);
2705		_call((genf *)READ32);
2706		_add_r32_imm(REG_ESP, 4);
2707		_movd_r128_r32(REG_XMM0, REG_EAX);
2708		_cvtss2sd_r128_r128(REG_XMM1, REG_XMM0); // convert float to double
2709		_movq_m64abs_r128(&FPR(RT), REG_XMM1);
	2743	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2744	emit_add_r32_imm(DRCTOP, REG_EDX, SIMM16);
	2745	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	2746	emit_push_r32(DRCTOP, REG_EDX);
	2747	emit_call(DRCTOP, (x86code *)READ32);
	2748	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2749	emit_movd_r128_r32(DRCTOP, REG_XMM0, REG_EAX);
	2750	emit_cvtss2sd_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // convert float to double
	2751	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM1);
2710	2752	#else
2711		_push_imm(op);
2712		_call((genf *)ppc_lfsu);
2713		_add_r32_imm(REG_ESP, 4);
	2753	emit_push_imm(DRCTOP, op);
	2754	emit_call(DRCTOP, (x86code *)ppc_lfsu);
	2755	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
2714	2756	#endif
2715		_mov_r32_m32~~abs~~(REG_EBP, &ppc_icount);
	2757	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2716	2758
2717	2759	return RECOMPILE_SUCCESSFUL_CP(1,4);
2718	2760	}
2719	2761
2720	2762	static UINT32 recompile_lfd(drc_core *drc, UINT32 op)
2721	2763	{
2722		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	2764	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
2723	2765	if (RA == 0)
2724	2766	{
2725		_push_imm(SIMM16);
	2767	emit_push_imm(DRCTOP, SIMM16);
2726	2768	}
2727	2769	else
2728	2770	{
2729		_mov_r32_m32abs(REG_EAX, &REG(RA));
2730		_add_r32_imm(REG_EAX, SIMM16);
2731		_push_r32(REG_EAX);
	2771	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2772	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	2773	emit_push_r32(DRCTOP, REG_EAX);
2732	2774	}
2733		_call((genf*)READ64);
2734		_add_r32_imm(REG_ESP, 4);
2735		_mov_m64abs_r64(&FPR(RT), REG_EDX, REG_EAX);
2736		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2775	emit_call(DRCTOP, (x86code *)READ64);
	2776	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2777	emit_mov_m64_r64(DRCTOP, MABS(&FPR(RT)), REG_EDX, REG_EAX);
	2778	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2737	2779
2738	2780	return RECOMPILE_SUCCESSFUL_CP(1,4);
2739	2781	}
2740	2782
2741	2783	static UINT32 recompile_lfdu(drc_core *drc, UINT32 op)
2742	2784	{
2743		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2744		_mov_r32_m32abs(REG_EDX, &REG(RA));
2745		_add_r32_imm(REG_EDX, SIMM16);
2746		_mov_m32abs_r32(&REG(RA), REG_EDX);
2747		_push_r32(REG_EDX);
2748		_call((genf*)READ64);
2749		_add_r32_imm(REG_ESP, 4);
2750		_mov_m64abs_r64(&FPR(RT), REG_EDX, REG_EAX);
2751		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2785	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2786	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2787	emit_add_r32_imm(DRCTOP, REG_EDX, SIMM16);
	2788	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	2789	emit_push_r32(DRCTOP, REG_EDX);
	2790	emit_call(DRCTOP, (x86code *)READ64);
	2791	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2792	emit_mov_m64_r64(DRCTOP, MABS(&FPR(RT)), REG_EDX, REG_EAX);
	2793	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2752	2794
2753	2795	return RECOMPILE_SUCCESSFUL_CP(1,4);
2754	2796	}
2755	2797
2756	2798	static UINT32 recompile_stfs(drc_core *drc, UINT32 op)
2757	2799	{
2758		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	2800	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
2759	2801	#if USE_SSE2
2760		_movq_r128_m64abs(REG_XMM0, &FPR(RT));
2761		_cvtsd2ss_r128_r128(REG_XMM1, REG_XMM0); // convert double to float
2762		_movd_r32_r128(REG_EAX, REG_XMM1);
2763		_push_r32(REG_EAX);
	2802	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RT)));
	2803	emit_cvtsd2ss_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // convert double to float
	2804	emit_movd_r32_r128(DRCTOP, REG_EAX, REG_XMM1);
	2805	emit_push_r32(DRCTOP, REG_EAX);
2764	2806	if (RA == 0)
2765	2807	{
2766		_push_imm(SIMM16);
	2808	emit_push_imm(DRCTOP, SIMM16);
2767	2809	}
2768	2810	else
2769	2811	{
2770		_mov_r32_m32abs(REG_EAX, &REG(RA));
2771		_add_r32_imm(REG_EAX, SIMM16);
2772		_push_r32(REG_EAX);
	2812	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2813	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	2814	emit_push_r32(DRCTOP, REG_EAX);
2773	2815	}
2774		_call((genf *)WRITE32);
2775		_add_r32_imm(REG_ESP, 8);
	2816	emit_call(DRCTOP, (x86code *)WRITE32);
	2817	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
2776	2818	#else
2777		_push_imm(op);
2778		_call((genf *)ppc_stfs);
2779		_add_r32_imm(REG_ESP, 4);
	2819	emit_push_imm(DRCTOP, op);
	2820	emit_call(DRCTOP, (x86code *)ppc_stfs);
	2821	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
2780	2822	#endif
2781		_mov_r32_m32~~abs~~(REG_EBP, &ppc_icount);
	2823	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2782	2824
2783	2825	return RECOMPILE_SUCCESSFUL_CP(1,4);
2784	2826	}
2785	2827
2786	2828	static UINT32 recompile_stfsu(drc_core *drc, UINT32 op)
2787	2829	{
2788		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	2830	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
2789	2831	#if USE_SSE2
2790		_movq_r128_m64abs(REG_XMM0, &FPR(RT));
2791		_cvtsd2ss_r128_r128(REG_XMM1, REG_XMM0); // convert double to float
2792		_movd_r32_r128(REG_EAX, REG_XMM1);
2793		_push_r32(REG_EAX);
	2832	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RT)));
	2833	emit_cvtsd2ss_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // convert double to float
	2834	emit_movd_r32_r128(DRCTOP, REG_EAX, REG_XMM1);
	2835	emit_push_r32(DRCTOP, REG_EAX);
2794	2836
2795		_mov_r32_m32abs(REG_EAX, &REG(RA));
2796		_add_r32_imm(REG_EAX, SIMM16);
2797		_mov_m32abs_r32(&REG(RA), REG_EAX);
2798		_push_r32(REG_EAX);
2799		_call((genf *)WRITE32);
2800		_add_r32_imm(REG_ESP, 8);
	2837	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2838	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	2839	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EAX);
	2840	emit_push_r32(DRCTOP, REG_EAX);
	2841	emit_call(DRCTOP, (x86code *)WRITE32);
	2842	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
2801	2843	#else
2802		_push_imm(op);
2803		_call((genf *)ppc_stfsu);
2804		_add_r32_imm(REG_ESP, 4);
	2844	emit_push_imm(DRCTOP, op);
	2845	emit_call(DRCTOP, (x86code *)ppc_stfsu);
	2846	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
2805	2847	#endif
2806		_mov_r32_m32~~abs~~(REG_EBP, &ppc_icount);
	2848	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2807	2849
2808	2850	return RECOMPILE_SUCCESSFUL_CP(1,4);
2809	2851	}
2810	2852
2811	2853	static UINT32 recompile_stfd(drc_core *drc, UINT32 op)
2812	2854	{
2813		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2814		_mov_r64_m64abs(REG_EDX, REG_EAX, &FPR(RT));
2815		_push_r32(REG_EDX);
2816		_push_r32(REG_EAX);
	2855	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2856	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, MABS(&FPR(RT)));
	2857	emit_push_r32(DRCTOP, REG_EDX);
	2858	emit_push_r32(DRCTOP, REG_EAX);
2817	2859	if (RA == 0)
2818	2860	{
2819		_push_imm(SIMM16);
	2861	emit_push_imm(DRCTOP, SIMM16);
2820	2862	}
2821	2863	else
2822	2864	{
2823		_mov_r32_m32abs(REG_EAX, &REG(RA));
2824		_add_r32_imm(REG_EAX, SIMM16);
2825		_push_r32(REG_EAX);
	2865	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2866	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	2867	emit_push_r32(DRCTOP, REG_EAX);
2826	2868	}
2827		_call((genf *)WRITE64);
2828		_add_r32_imm(REG_ESP, 12);
2829		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2869	emit_call(DRCTOP, (x86code *)WRITE64);
	2870	emit_add_r32_imm(DRCTOP, REG_ESP, 12);
	2871	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2830	2872
2831	2873	return RECOMPILE_SUCCESSFUL_CP(1,4);
2832	2874	}
2833	2875
2834	2876	static UINT32 recompile_stfdu(drc_core *drc, UINT32 op)
2835	2877	{
2836		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2837		_mov_r64_m64abs(REG_EDX, REG_EAX, &FPR(RT));
2838		_push_r32(REG_EDX);
2839		_push_r32(REG_EAX);
	2878	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2879	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, MABS(&FPR(RT)));
	2880	emit_push_r32(DRCTOP, REG_EDX);
	2881	emit_push_r32(DRCTOP, REG_EAX);
2840	2882
2841		_mov_r32_m32abs(REG_EAX, &REG(RA));
2842		_add_r32_imm(REG_EAX, SIMM16);
2843		_mov_m32abs_r32(&REG(RA), REG_EAX);
2844		_push_r32(REG_EAX);
2845		_call((genf *)WRITE64);
2846		_add_r32_imm(REG_ESP, 12);
2847		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2883	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	2884	emit_add_r32_imm(DRCTOP, REG_EAX, SIMM16);
	2885	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EAX);
	2886	emit_push_r32(DRCTOP, REG_EAX);
	2887	emit_call(DRCTOP, (x86code *)WRITE64);
	2888	emit_add_r32_imm(DRCTOP, REG_ESP, 12);
	2889	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2848	2890
2849	2891	return RECOMPILE_SUCCESSFUL_CP(1,4);
2850	2892	}
2851	2893
2852	2894	static UINT32 recompile_lfdux(drc_core *drc, UINT32 op)
2853	2895	{
2854		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2855		_mov_r32_m32abs(REG_EDX, &REG(RA));
2856		_add_r32_m32abs(REG_EDX, &REG(RB));
2857		_mov_m32abs_r32(&REG(RA), REG_EDX);
2858		_push_r32(REG_EDX);
2859		_call((genf*)READ64);
2860		_add_r32_imm(REG_ESP, 4);
2861		_mov_m64abs_r64(&FPR(RT), REG_EDX, REG_EAX);
2862		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2896	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2897	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2898	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	2899	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	2900	emit_push_r32(DRCTOP, REG_EDX);
	2901	emit_call(DRCTOP, (x86code *)READ64);
	2902	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2903	emit_mov_m64_r64(DRCTOP, MABS(&FPR(RT)), REG_EDX, REG_EAX);
	2904	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2863	2905
2864	2906	return RECOMPILE_SUCCESSFUL_CP(1,4);
2865	2907	}
2866	2908
2867	2909	static UINT32 recompile_lfdx(drc_core *drc, UINT32 op)
2868	2910	{
2869		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2870		_mov_r32_m32abs(REG_EAX, &REG(RB));
	2911	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2912	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
2871	2913	if (RA != 0)
2872	2914	{
2873		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	2915	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
2874	2916	}
2875		_push_r32(REG_EAX);
2876		_call((genf*)READ64);
2877		_add_r32_imm(REG_ESP, 4);
2878		_mov_m64abs_r64(&FPR(RT), REG_EDX, REG_EAX);
2879		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2917	emit_push_r32(DRCTOP, REG_EAX);
	2918	emit_call(DRCTOP, (x86code *)READ64);
	2919	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2920	emit_mov_m64_r64(DRCTOP, MABS(&FPR(RT)), REG_EDX, REG_EAX);
	2921	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2880	2922
2881	2923	return RECOMPILE_SUCCESSFUL_CP(1,4);
2882	2924	}
2883	2925
2884	2926	static UINT32 recompile_lfsux(drc_core *drc, UINT32 op)
2885	2927	{
2886		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	2928	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
2887	2929	#if USE_SSE2
2888		_mov_r32_m32abs(REG_EDX, &REG(RA));
2889		_add_r32_m32abs(REG_EDX, &REG(RB));
2890		_mov_m32abs_r32(&REG(RA), REG_EDX);
2891		_push_r32(REG_EDX);
2892		_call((genf *)READ32);
2893		_add_r32_imm(REG_ESP, 4);
2894		_movd_r128_r32(REG_XMM0, REG_EAX);
2895		_cvtss2sd_r128_r128(REG_XMM1, REG_XMM0); // convert float to double
2896		_movq_m64abs_r128(&FPR(RT), REG_XMM1);
	2930	emit_mov_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RA)));
	2931	emit_add_r32_m32(DRCTOP, REG_EDX, MABS(&REG(RB)));
	2932	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EDX);
	2933	emit_push_r32(DRCTOP, REG_EDX);
	2934	emit_call(DRCTOP, (x86code *)READ32);
	2935	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2936	emit_movd_r128_r32(DRCTOP, REG_XMM0, REG_EAX);
	2937	emit_cvtss2sd_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // convert float to double
	2938	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM1);
2897	2939	#else
2898		_push_imm(op);
2899		_call((genf *)ppc_lfsux);
2900		_add_r32_imm(REG_ESP, 4);
	2940	emit_push_imm(DRCTOP, op);
	2941	emit_call(DRCTOP, (x86code *)ppc_lfsux);
	2942	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
2901	2943	#endif
2902		_mov_r32_m32~~abs~~(REG_EBP, &ppc_icount);
	2944	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2903	2945
2904	2946	return RECOMPILE_SUCCESSFUL_CP(1,4);
2905	2947	}
2906	2948
2907	2949	static UINT32 recompile_lfsx(drc_core *drc, UINT32 op)
2908	2950	{
2909		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	2951	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
2910	2952	#if USE_SSE2
2911		_mov_r32_m32~~abs~~(REG_EAX, &REG(RB));
	2953	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
2912	2954	if (RA != 0)
2913	2955	{
2914		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	2956	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
2915	2957	}
2916		_push_r32(REG_EAX);
2917		_call((genf *)READ32);
2918		_add_r32_imm(REG_ESP, 4);
2919		_movd_r128_r32(REG_XMM0, REG_EAX);
2920		_cvtss2sd_r128_r128(REG_XMM1, REG_XMM0); // convert float to double
2921		_movq_m64abs_r128(&FPR(RT), REG_XMM1);
	2958	emit_push_r32(DRCTOP, REG_EAX);
	2959	emit_call(DRCTOP, (x86code *)READ32);
	2960	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2961	emit_movd_r128_r32(DRCTOP, REG_XMM0, REG_EAX);
	2962	emit_cvtss2sd_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // convert float to double
	2963	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM1);
2922	2964	#else
2923		_push_imm(op);
2924		_call((genf *)ppc_lfsx);
2925		_add_r32_imm(REG_ESP, 4);
	2965	emit_push_imm(DRCTOP, op);
	2966	emit_call(DRCTOP, (x86code *)ppc_lfsx);
	2967	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
2926	2968	#endif
2927		_mov_r32_m32~~abs~~(REG_EBP, &ppc_icount);
	2969	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2928	2970
2929	2971	return RECOMPILE_SUCCESSFUL_CP(1,4);
2930	2972	}
2931	2973
2932	2974	static UINT32 recompile_mfsr(drc_core *drc, UINT32 op)
2933	2975	{
2934		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2935		_push_imm(op);
2936		_call((genf *)ppc_mfsr);
2937		_add_r32_imm(REG_ESP, 4);
2938		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2976	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2977	emit_push_imm(DRCTOP, op);
	2978	emit_call(DRCTOP, (x86code *)ppc_mfsr);
	2979	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2980	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2939	2981
2940	2982	return RECOMPILE_SUCCESSFUL_CP(1,4);
2941	2983	}
2942	2984
2943	2985	static UINT32 recompile_mfsrin(drc_core *drc, UINT32 op)
2944	2986	{
2945		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2946		_push_imm(op);
2947		_call((genf *)ppc_mfsrin);
2948		_add_r32_imm(REG_ESP, 4);
2949		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2987	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2988	emit_push_imm(DRCTOP, op);
	2989	emit_call(DRCTOP, (x86code *)ppc_mfsrin);
	2990	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	2991	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2950	2992
2951	2993	return RECOMPILE_SUCCESSFUL_CP(1,4);
2952	2994	}
2953	2995
2954	2996	static UINT32 recompile_mftb(drc_core *drc, UINT32 op)
2955	2997	{
2956		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2957		_push_imm(op);
2958		_call((genf *)ppc_mftb);
2959		_add_r32_imm(REG_ESP, 4);
2960		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	2998	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	2999	emit_push_imm(DRCTOP, op);
	3000	emit_call(DRCTOP, (x86code *)ppc_mftb);
	3001	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3002	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2961	3003
2962	3004	return RECOMPILE_SUCCESSFUL_CP(1,4);
2963	3005	}
2964	3006
2965	3007	static UINT32 recompile_mtsr(drc_core *drc, UINT32 op)
2966	3008	{
2967		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2968		_push_imm(op);
2969		_call((genf *)ppc_mtsr);
2970		_add_r32_imm(REG_ESP, 4);
2971		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3009	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3010	emit_push_imm(DRCTOP, op);
	3011	emit_call(DRCTOP, (x86code *)ppc_mtsr);
	3012	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3013	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2972	3014
2973	3015	return RECOMPILE_SUCCESSFUL_CP(1,4);
2974	3016	}
2975	3017
2976	3018	static UINT32 recompile_mtsrin(drc_core *drc, UINT32 op)
2977	3019	{
2978		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2979		_push_imm(op);
2980		_call((genf *)ppc_mtsrin);
2981		_add_r32_imm(REG_ESP, 4);
2982		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3020	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3021	emit_push_imm(DRCTOP, op);
	3022	emit_call(DRCTOP, (x86code *)ppc_mtsrin);
	3023	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3024	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
2983	3025
2984	3026	return RECOMPILE_SUCCESSFUL_CP(1,4);
2985	3027	}
r949	r950
2991	3033
2992	3034	static UINT32 recompile_stfdux(drc_core *drc, UINT32 op)
2993	3035	{
2994		_mov_m32abs_r32(&ppc_icount, REG_EBP);
2995		_mov_r64_m64abs(REG_EDX, REG_EAX, &FPR(RT));
2996		_push_r32(REG_EDX);
2997		_push_r32(REG_EAX);
	3036	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3037	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, MABS(&FPR(RT)));
	3038	emit_push_r32(DRCTOP, REG_EDX);
	3039	emit_push_r32(DRCTOP, REG_EAX);
2998	3040
2999		_mov_r32_m32abs(REG_EAX, &REG(RA));
3000		_add_r32_m32abs(REG_EAX, &REG(RB));
3001		_mov_m32abs_r32(&REG(RA), REG_EAX);
3002		_push_r32(REG_EAX);
3003		_call((genf *)WRITE64);
3004		_add_r32_imm(REG_ESP, 12);
3005		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3041	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	3042	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
	3043	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EAX);
	3044	emit_push_r32(DRCTOP, REG_EAX);
	3045	emit_call(DRCTOP, (x86code *)WRITE64);
	3046	emit_add_r32_imm(DRCTOP, REG_ESP, 12);
	3047	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3006	3048
3007	3049	return RECOMPILE_SUCCESSFUL_CP(1,4);
3008	3050	}
3009	3051
3010	3052	static UINT32 recompile_stfdx(drc_core *drc, UINT32 op)
3011	3053	{
3012		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3013		_mov_r64_m64abs(REG_EDX, REG_EAX, &FPR(RT));
3014		_push_r32(REG_EDX);
3015		_push_r32(REG_EAX);
	3054	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3055	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, MABS(&FPR(RT)));
	3056	emit_push_r32(DRCTOP, REG_EDX);
	3057	emit_push_r32(DRCTOP, REG_EAX);
3016	3058
3017		_mov_r32_m32~~abs~~(REG_EAX, &REG(RB));
	3059	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
3018	3060	if (RA != 0)
3019	3061	{
3020		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	3062	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
3021	3063	}
3022		_push_r32(REG_EAX);
3023		_call((genf *)WRITE64);
3024		_add_r32_imm(REG_ESP, 12);
	3064	emit_push_r32(DRCTOP, REG_EAX);
	3065	emit_call(DRCTOP, (x86code *)WRITE64);
	3066	emit_add_r32_imm(DRCTOP, REG_ESP, 12);
3025	3067
3026		_push_imm(op);
3027		_call((genf *)ppc_stfdx);
3028		_add_r32_imm(REG_ESP, 4);
3029		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3068	emit_push_imm(DRCTOP, op);
	3069	emit_call(DRCTOP, (x86code *)ppc_stfdx);
	3070	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3071	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3030	3072
3031	3073	return RECOMPILE_SUCCESSFUL_CP(1,4);
3032	3074	}
3033	3075
3034	3076	static UINT32 recompile_stfiwx(drc_core *drc, UINT32 op)
3035	3077	{
3036		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	3078	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
3037	3079	#if USE_SSE2
3038		_movq_r128_m64abs(REG_XMM0, &FPR(RT));
3039		_movd_r32_r128(REG_EAX, REG_XMM0);
3040		_push_r32(REG_EAX);
	3080	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RT)));
	3081	emit_movd_r32_r128(DRCTOP, REG_EAX, REG_XMM0);
	3082	emit_push_r32(DRCTOP, REG_EAX);
3041	3083
3042		_mov_r32_m32~~abs~~(REG_EAX, &REG(RB));
	3084	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
3043	3085	if (RA != 0)
3044	3086	{
3045		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	3087	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
3046	3088	}
3047		_push_r32(REG_EAX);
3048		_call((genf *)WRITE32);
3049		_add_r32_imm(REG_ESP, 8);
	3089	emit_push_r32(DRCTOP, REG_EAX);
	3090	emit_call(DRCTOP, (x86code *)WRITE32);
	3091	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
3050	3092	#else
3051		_push_imm(op);
3052		_call((genf *)ppc_stfiwx);
3053		_add_r32_imm(REG_ESP, 4);
	3093	emit_push_imm(DRCTOP, op);
	3094	emit_call(DRCTOP, (x86code *)ppc_stfiwx);
	3095	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
3054	3096	#endif
3055		_mov_r32_m32~~abs~~(REG_EBP, &ppc_icount);
	3097	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3056	3098
3057	3099	return RECOMPILE_SUCCESSFUL_CP(1,4);
3058	3100	}
3059	3101
3060	3102	static UINT32 recompile_stfsux(drc_core *drc, UINT32 op)
3061	3103	{
3062		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	3104	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
3063	3105	#if USE_SSE2
3064		_movq_r128_m64abs(REG_XMM0, &FPR(RT));
3065		_cvtsd2ss_r128_r128(REG_XMM1, REG_XMM0); // convert double to float
3066		_movd_r32_r128(REG_EAX, REG_XMM1);
3067		_push_r32(REG_EAX);
	3106	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RT)));
	3107	emit_cvtsd2ss_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // convert double to float
	3108	emit_movd_r32_r128(DRCTOP, REG_EAX, REG_XMM1);
	3109	emit_push_r32(DRCTOP, REG_EAX);
3068	3110
3069		_mov_r32_m32abs(REG_EAX, &REG(RA));
3070		_add_r32_m32abs(REG_EAX, &REG(RB));
3071		_mov_m32abs_r32(&REG(RA), REG_EAX);
3072		_push_r32(REG_EAX);
3073		_call((genf *)WRITE32);
3074		_add_r32_imm(REG_ESP, 8);
	3111	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
	3112	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
	3113	emit_mov_m32_r32(DRCTOP, MABS(&REG(RA)), REG_EAX);
	3114	emit_push_r32(DRCTOP, REG_EAX);
	3115	emit_call(DRCTOP, (x86code *)WRITE32);
	3116	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
3075	3117	#else
3076		_push_imm(op);
3077		_call((genf *)ppc_stfsux);
3078		_add_r32_imm(REG_ESP, 4);
	3118	emit_push_imm(DRCTOP, op);
	3119	emit_call(DRCTOP, (x86code *)ppc_stfsux);
	3120	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
3079	3121	#endif
3080		_mov_r32_m32~~abs~~(REG_EBP, &ppc_icount);
	3122	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3081	3123
3082	3124	return RECOMPILE_SUCCESSFUL_CP(1,4);
3083	3125	}
3084	3126
3085	3127	static UINT32 recompile_stfsx(drc_core *drc, UINT32 op)
3086	3128	{
3087		_mov_m32~~abs~~_r32(&ppc_icount, REG_EBP);
	3129	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
3088	3130	#if USE_SSE2
3089		_movq_r128_m64abs(REG_XMM0, &FPR(RT));
3090		_cvtsd2ss_r128_r128(REG_XMM1, REG_XMM0); // convert double to float
3091		_movd_r32_r128(REG_EAX, REG_XMM1);
3092		_push_r32(REG_EAX);
	3131	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RT)));
	3132	emit_cvtsd2ss_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // convert double to float
	3133	emit_movd_r32_r128(DRCTOP, REG_EAX, REG_XMM1);
	3134	emit_push_r32(DRCTOP, REG_EAX);
3093	3135
3094		_mov_r32_m32~~abs~~(REG_EAX, &REG(RB));
	3136	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RB)));
3095	3137	if (RA != 0)
3096	3138	{
3097		_add_r32_m32~~abs~~(REG_EAX, &REG(RA));
	3139	emit_add_r32_m32(DRCTOP, REG_EAX, MABS(&REG(RA)));
3098	3140	}
3099		_push_r32(REG_EAX);
3100		_call((genf *)WRITE32);
3101		_add_r32_imm(REG_ESP, 8);
	3141	emit_push_r32(DRCTOP, REG_EAX);
	3142	emit_call(DRCTOP, (x86code *)WRITE32);
	3143	emit_add_r32_imm(DRCTOP, REG_ESP, 8);
3102	3144	#else
3103		_push_imm(op);
3104		_call((genf *)ppc_stfsx);
3105		_add_r32_imm(REG_ESP, 4);
	3145	emit_push_imm(DRCTOP, op);
	3146	emit_call(DRCTOP, (x86code *)ppc_stfsx);
	3147	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
3106	3148	#endif
3107		_mov_r32_m32~~abs~~(REG_EBP, &ppc_icount);
	3149	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3108	3150
3109	3151	return RECOMPILE_SUCCESSFUL_CP(1,4);
3110	3152	}
r949	r950
3139	3181	static UINT32 recompile_fabsx(drc_core *drc, UINT32 op)
3140	3182	{
3141	3183	#if !COMPILE_FPU \|\| !USE_SSE2
3142		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3143		_push_imm(op);
3144		_call((genf *)ppc_fabsx);
3145		_add_r32_imm(REG_ESP, 4);
3146		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3184	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3185	emit_push_imm(DRCTOP, op);
	3186	emit_call(DRCTOP, (x86code *)ppc_fabsx);
	3187	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3188	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3147	3189	#else
3148		_mov_r64_m64abs(REG_EDX, REG_EAX, &FPR(RB));
3149		_and_r32_imm(REG_EDX, 0x7fffffff);
3150		_mov_m64abs_r64(&FPR(RT), REG_EDX, REG_EAX);
	3190	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, MABS(&FPR(RB)));
	3191	emit_and_r32_imm(DRCTOP, REG_EDX, 0x7fffffff);
	3192	emit_mov_m64_r64(DRCTOP, MABS(&FPR(RT)), REG_EDX, REG_EAX);
3151	3193
3152	3194	if (RCBIT) {
3153	3195	append_set_cr1(drc);
r949	r950
3159	3201	static UINT32 recompile_faddx(drc_core *drc, UINT32 op)
3160	3202	{
3161	3203	#if !COMPILE_FPU \|\| !USE_SSE2
3162		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3163		_push_imm(op);
3164		_call((genf *)ppc_faddx);
3165		_add_r32_imm(REG_ESP, 4);
3166		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3204	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3205	emit_push_imm(DRCTOP, op);
	3206	emit_call(DRCTOP, (x86code *)ppc_faddx);
	3207	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3208	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3167	3209	#else
3168		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3169		_movq_r128_m64abs(REG_XMM1, &FPR(RB));
3170		_addsd_r128_r128(REG_XMM0, REG_XMM1);
3171		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3210	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3211	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RB)));
	3212	emit_addsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3213	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3172	3214
3173	3215	if (RCBIT) {
3174	3216	append_set_cr1(drc);
r949	r950
3179	3221
3180	3222	static UINT32 recompile_fcmpo(drc_core *drc, UINT32 op)
3181	3223	{
3182		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3183		_push_imm(op);
3184		_call((genf *)ppc_fcmpo);
3185		_add_r32_imm(REG_ESP, 4);
3186		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3224	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3225	emit_push_imm(DRCTOP, op);
	3226	emit_call(DRCTOP, (x86code *)ppc_fcmpo);
	3227	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3228	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3187	3229
3188	3230	return RECOMPILE_SUCCESSFUL_CP(1,4);
3189	3231	}
3190	3232
3191	3233	static UINT32 recompile_fcmpu(drc_core *drc, UINT32 op)
3192	3234	{
3193		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3194		_push_imm(op);
3195		_call((genf *)ppc_fcmpu);
3196		_add_r32_imm(REG_ESP, 4);
3197		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3235	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3236	emit_push_imm(DRCTOP, op);
	3237	emit_call(DRCTOP, (x86code *)ppc_fcmpu);
	3238	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3239	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3198	3240
3199	3241	return RECOMPILE_SUCCESSFUL_CP(1,4);
3200	3242	}
3201	3243
3202	3244	static UINT32 recompile_fctiwx(drc_core *drc, UINT32 op)
3203	3245	{
3204		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3205		_push_imm(op);
3206		_call((genf *)ppc_fctiwx);
3207		_add_r32_imm(REG_ESP, 4);
3208		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3246	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3247	emit_push_imm(DRCTOP, op);
	3248	emit_call(DRCTOP, (x86code *)ppc_fctiwx);
	3249	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3250	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3209	3251
3210	3252	return RECOMPILE_SUCCESSFUL_CP(1,4);
3211	3253	}
3212	3254
3213	3255	static UINT32 recompile_fctiwzx(drc_core *drc, UINT32 op)
3214	3256	{
3215		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3216		_push_imm(op);
3217		_call((genf *)ppc_fctiwzx);
3218		_add_r32_imm(REG_ESP, 4);
3219		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3257	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3258	emit_push_imm(DRCTOP, op);
	3259	emit_call(DRCTOP, (x86code *)ppc_fctiwzx);
	3260	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3261	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3220	3262
3221	3263	return RECOMPILE_SUCCESSFUL_CP(1,4);
3222	3264	}
r949	r950
3224	3266	static UINT32 recompile_fdivx(drc_core *drc, UINT32 op)
3225	3267	{
3226	3268	#if !COMPILE_FPU \|\| !USE_SSE2
3227		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3228		_push_imm(op);
3229		_call((genf *)ppc_fdivx);
3230		_add_r32_imm(REG_ESP, 4);
3231		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3269	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3270	emit_push_imm(DRCTOP, op);
	3271	emit_call(DRCTOP, (x86code *)ppc_fdivx);
	3272	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3273	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3232	3274	#else
3233		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3234		_movq_r128_m64abs(REG_XMM1, &FPR(RB));
3235		_divsd_r128_r128(REG_XMM0, REG_XMM1);
3236		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3275	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3276	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RB)));
	3277	emit_divsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3278	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3237	3279
3238	3280	if (RCBIT) {
3239	3281	append_set_cr1(drc);
r949	r950
3246	3288	static UINT32 recompile_fmrx(drc_core *drc, UINT32 op)
3247	3289	{
3248	3290	#if USE_SSE2
3249		_movq_r128_m64abs(REG_XMM0, &FPR(RB));
3250		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3291	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RB)));
	3292	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3251	3293
3252	3294	if (RCBIT) {
3253	3295	append_set_cr1(drc);
3254	3296	}
3255	3297	#else
3256		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3257		_push_imm(op);
3258		_call((genf *)ppc_fmrx);
3259		_add_r32_imm(REG_ESP, 4);
3260		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3298	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3299	emit_push_imm(DRCTOP, op);
	3300	emit_call(DRCTOP, (x86code *)ppc_fmrx);
	3301	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3302	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3261	3303	#endif
3262	3304
3263	3305	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
3266	3308	static UINT32 recompile_fnabsx(drc_core *drc, UINT32 op)
3267	3309	{
3268	3310	#if !COMPILE_FPU \|\| !USE_SSE2
3269		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3270		_push_imm(op);
3271		_call((genf *)ppc_fnabsx);
3272		_add_r32_imm(REG_ESP, 4);
3273		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3311	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3312	emit_push_imm(DRCTOP, op);
	3313	emit_call(DRCTOP, (x86code *)ppc_fnabsx);
	3314	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3315	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3274	3316	#else
3275		_mov_r64_m64abs(REG_EDX, REG_EAX, &FPR(RB));
3276		_or_r32_imm(REG_EDX, 0x80000000);
3277		_mov_m64abs_r64(&FPR(RT), REG_EDX, REG_EAX);
	3317	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, MABS(&FPR(RB)));
	3318	emit_or_r32_imm(DRCTOP, REG_EDX, 0x80000000);
	3319	emit_mov_m64_r64(DRCTOP, MABS(&FPR(RT)), REG_EDX, REG_EAX);
3278	3320
3279	3321	if (RCBIT) {
3280	3322	append_set_cr1(drc);
r949	r950
3287	3329	static UINT32 recompile_fnegx(drc_core *drc, UINT32 op)
3288	3330	{
3289	3331	#if !COMPILE_FPU \|\| !USE_SSE2
3290		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3291		_push_imm(op);
3292		_call((genf *)ppc_fnegx);
3293		_add_r32_imm(REG_ESP, 4);
3294		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3332	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3333	emit_push_imm(DRCTOP, op);
	3334	emit_call(DRCTOP, (x86code *)ppc_fnegx);
	3335	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3336	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3295	3337	#else
3296		_mov_r64_m64abs(REG_EDX, REG_EAX, &FPR(RB));
3297		_xor_r32_imm(REG_EDX, 0x80000000);
3298		_mov_m64abs_r64(&FPR(RT), REG_EDX, REG_EAX);
	3338	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, MABS(&FPR(RB)));
	3339	emit_xor_r32_imm(DRCTOP, REG_EDX, 0x80000000);
	3340	emit_mov_m64_r64(DRCTOP, MABS(&FPR(RT)), REG_EDX, REG_EAX);
3299	3341
3300	3342	if (RCBIT) {
3301	3343	append_set_cr1(drc);
r949	r950
3307	3349
3308	3350	static UINT32 recompile_frspx(drc_core *drc, UINT32 op)
3309	3351	{
3310		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3311		_push_imm(op);
3312		_call((genf *)ppc_frspx);
3313		_add_r32_imm(REG_ESP, 4);
3314		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3352	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3353	emit_push_imm(DRCTOP, op);
	3354	emit_call(DRCTOP, (x86code *)ppc_frspx);
	3355	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3356	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3315	3357	/*
3316		_movq_r128_m64~~abs~~(REG_XMM0, &FPR(RB));
	3358	_movq_r128_m64(REG_XMM0, MABS(&FPR(RB)));
3317	3359	_movq_m64abs_r128(&FPR(RT), REG_XMM0);
3318	3360
3319	3361	if (RCBIT) {
r949	r950
3325	3367
3326	3368	static UINT32 recompile_frsqrtex(drc_core *drc, UINT32 op)
3327	3369	{
3328		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3329		_push_imm(op);
3330		_call((genf *)ppc_frsqrtex);
3331		_add_r32_imm(REG_ESP, 4);
3332		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3370	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3371	emit_push_imm(DRCTOP, op);
	3372	emit_call(DRCTOP, (x86code *)ppc_frsqrtex);
	3373	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3374	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3333	3375
3334	3376	return RECOMPILE_SUCCESSFUL_CP(1,4);
3335	3377	}
3336	3378
3337	3379	static UINT32 recompile_fsqrtx(drc_core *drc, UINT32 op)
3338	3380	{
3339		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3340		_push_imm(op);
3341		_call((genf *)ppc_fsqrtx);
3342		_add_r32_imm(REG_ESP, 4);
3343		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3381	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3382	emit_push_imm(DRCTOP, op);
	3383	emit_call(DRCTOP, (x86code *)ppc_fsqrtx);
	3384	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3385	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3344	3386
3345	3387	return RECOMPILE_SUCCESSFUL_CP(1,4);
3346	3388	}
r949	r950
3348	3390	static UINT32 recompile_fsubx(drc_core *drc, UINT32 op)
3349	3391	{
3350	3392	#if !COMPILE_FPU \|\| !USE_SSE2
3351		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3352		_push_imm(op);
3353		_call((genf *)ppc_fsubx);
3354		_add_r32_imm(REG_ESP, 4);
3355		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3393	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3394	emit_push_imm(DRCTOP, op);
	3395	emit_call(DRCTOP, (x86code *)ppc_fsubx);
	3396	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3397	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3356	3398	#else
3357		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3358		_movq_r128_m64abs(REG_XMM1, &FPR(RB));
3359		_subsd_r128_r128(REG_XMM0, REG_XMM1);
3360		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3399	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3400	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RB)));
	3401	emit_subsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3402	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3361	3403
3362	3404	if (RCBIT) {
3363	3405	append_set_cr1(drc);
r949	r950
3369	3411
3370	3412	static UINT32 recompile_mffsx(drc_core *drc, UINT32 op)
3371	3413	{
3372		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3373		_push_imm(op);
3374		_call((genf *)ppc_mffsx);
3375		_add_r32_imm(REG_ESP, 4);
3376		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3414	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3415	emit_push_imm(DRCTOP, op);
	3416	emit_call(DRCTOP, (x86code *)ppc_mffsx);
	3417	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3418	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3377	3419
3378	3420	return RECOMPILE_SUCCESSFUL_CP(1,4);
3379	3421	}
3380	3422
3381	3423	static UINT32 recompile_mtfsb0x(drc_core *drc, UINT32 op)
3382	3424	{
3383		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3384		_push_imm(op);
3385		_call((genf *)ppc_mtfsb0x);
3386		_add_r32_imm(REG_ESP, 4);
3387		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3425	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3426	emit_push_imm(DRCTOP, op);
	3427	emit_call(DRCTOP, (x86code *)ppc_mtfsb0x);
	3428	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3429	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3388	3430
3389	3431	return RECOMPILE_SUCCESSFUL_CP(1,4);
3390	3432	}
3391	3433
3392	3434	static UINT32 recompile_mtfsb1x(drc_core *drc, UINT32 op)
3393	3435	{
3394		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3395		_push_imm(op);
3396		_call((genf *)ppc_mtfsb1x);
3397		_add_r32_imm(REG_ESP, 4);
3398		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3436	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3437	emit_push_imm(DRCTOP, op);
	3438	emit_call(DRCTOP, (x86code *)ppc_mtfsb1x);
	3439	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3440	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3399	3441
3400	3442	return RECOMPILE_SUCCESSFUL_CP(1,4);
3401	3443	}
3402	3444
3403	3445	static UINT32 recompile_mtfsfx(drc_core *drc, UINT32 op)
3404	3446	{
3405		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3406		_push_imm(op);
3407		_call((genf *)ppc_mtfsfx);
3408		_add_r32_imm(REG_ESP, 4);
3409		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3447	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3448	emit_push_imm(DRCTOP, op);
	3449	emit_call(DRCTOP, (x86code *)ppc_mtfsfx);
	3450	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3451	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3410	3452
3411	3453	return RECOMPILE_SUCCESSFUL_CP(1,4);
3412	3454	}
3413	3455
3414	3456	static UINT32 recompile_mtfsfix(drc_core *drc, UINT32 op)
3415	3457	{
3416		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3417		_push_imm(op);
3418		_call((genf *)ppc_mtfsfix);
3419		_add_r32_imm(REG_ESP, 4);
3420		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3458	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3459	emit_push_imm(DRCTOP, op);
	3460	emit_call(DRCTOP, (x86code *)ppc_mtfsfix);
	3461	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3462	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3421	3463
3422	3464	return RECOMPILE_SUCCESSFUL_CP(1,4);
3423	3465	}
3424	3466
3425	3467	static UINT32 recompile_mcrfs(drc_core *drc, UINT32 op)
3426	3468	{
3427		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3428		_push_imm(op);
3429		_call((genf *)ppc_mcrfs);
3430		_add_r32_imm(REG_ESP, 4);
3431		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3469	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3470	emit_push_imm(DRCTOP, op);
	3471	emit_call(DRCTOP, (x86code *)ppc_mcrfs);
	3472	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3473	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3432	3474
3433	3475	return RECOMPILE_SUCCESSFUL_CP(1,4);
3434	3476	}
r949	r950
3436	3478	static UINT32 recompile_faddsx(drc_core *drc, UINT32 op)
3437	3479	{
3438	3480	#if !COMPILE_FPU \|\| !USE_SSE2
3439		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3440		_push_imm(op);
3441		_call((genf *)ppc_faddsx);
3442		_add_r32_imm(REG_ESP, 4);
3443		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3481	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3482	emit_push_imm(DRCTOP, op);
	3483	emit_call(DRCTOP, (x86code *)ppc_faddsx);
	3484	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3485	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3444	3486	#else
3445		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3446		_movq_r128_m64abs(REG_XMM1, &FPR(RB));
3447		_addsd_r128_r128(REG_XMM0, REG_XMM1);
3448		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3487	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3488	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RB)));
	3489	emit_addsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3490	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3449	3491
3450	3492	if (RCBIT) {
3451	3493	append_set_cr1(drc);
r949	r950
3458	3500	static UINT32 recompile_fdivsx(drc_core *drc, UINT32 op)
3459	3501	{
3460	3502	#if !COMPILE_FPU \|\| !USE_SSE2
3461		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3462		_push_imm(op);
3463		_call((genf *)ppc_fdivsx);
3464		_add_r32_imm(REG_ESP, 4);
3465		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3503	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3504	emit_push_imm(DRCTOP, op);
	3505	emit_call(DRCTOP, (x86code *)ppc_fdivsx);
	3506	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3507	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3466	3508	#else
3467		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3468		_movq_r128_m64abs(REG_XMM1, &FPR(RB));
3469		_divsd_r128_r128(REG_XMM0, REG_XMM1);
3470		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3509	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3510	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RB)));
	3511	emit_divsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3512	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3471	3513
3472	3514	if (RCBIT) {
3473	3515	append_set_cr1(drc);
r949	r950
3479	3521
3480	3522	static UINT32 recompile_fresx(drc_core *drc, UINT32 op)
3481	3523	{
3482		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3483		_push_imm(op);
3484		_call((genf *)ppc_fresx);
3485		_add_r32_imm(REG_ESP, 4);
3486		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3524	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3525	emit_push_imm(DRCTOP, op);
	3526	emit_call(DRCTOP, (x86code *)ppc_fresx);
	3527	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3528	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3487	3529
3488	3530	return RECOMPILE_SUCCESSFUL_CP(1,4);
3489	3531	}
3490	3532
3491	3533	static UINT32 recompile_fsqrtsx(drc_core *drc, UINT32 op)
3492	3534	{
3493		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3494		_push_imm(op);
3495		_call((genf *)ppc_fsqrtsx);
3496		_add_r32_imm(REG_ESP, 4);
3497		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3535	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3536	emit_push_imm(DRCTOP, op);
	3537	emit_call(DRCTOP, (x86code *)ppc_fsqrtsx);
	3538	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3539	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3498	3540
3499	3541	return RECOMPILE_SUCCESSFUL_CP(1,4);
3500	3542	}
r949	r950
3502	3544	static UINT32 recompile_fsubsx(drc_core *drc, UINT32 op)
3503	3545	{
3504	3546	#if !COMPILE_FPU \|\| !USE_SSE2
3505		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3506		_push_imm(op);
3507		_call((genf *)ppc_fsubsx);
3508		_add_r32_imm(REG_ESP, 4);
3509		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3547	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3548	emit_push_imm(DRCTOP, op);
	3549	emit_call(DRCTOP, (x86code *)ppc_fsubsx);
	3550	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3551	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3510	3552	#else
3511		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3512		_movq_r128_m64abs(REG_XMM1, &FPR(RB));
3513		_subsd_r128_r128(REG_XMM0, REG_XMM1);
3514		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3553	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3554	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RB)));
	3555	emit_subsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3556	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3515	3557
3516	3558	if (RCBIT) {
3517	3559	append_set_cr1(drc);
r949	r950
3524	3566	static UINT32 recompile_fmaddx(drc_core *drc, UINT32 op)
3525	3567	{
3526	3568	#if !COMPILE_FPU \|\| !USE_SSE2
3527		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3528		_push_imm(op);
3529		_call((genf *)ppc_fmaddx);
3530		_add_r32_imm(REG_ESP, 4);
3531		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3569	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3570	emit_push_imm(DRCTOP, op);
	3571	emit_call(DRCTOP, (x86code *)ppc_fmaddx);
	3572	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3573	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3532	3574	#else
3533		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3534		_movq_r128_m64abs(REG_XMM1, &FPR(RC));
3535		_movq_r128_m64abs(REG_XMM2, &FPR(RB));
3536		_mulsd_r128_r128(REG_XMM0, REG_XMM1);
3537		_addsd_r128_r128(REG_XMM0, REG_XMM2);
3538		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3575	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3576	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RC)));
	3577	emit_movq_r128_m64(DRCTOP, REG_XMM2, MABS(&FPR(RB)));
	3578	emit_mulsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3579	emit_addsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM2);
	3580	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3539	3581
3540	3582	if (RCBIT) {
3541	3583	append_set_cr1(drc);
r949	r950
3548	3590	static UINT32 recompile_fmsubx(drc_core *drc, UINT32 op)
3549	3591	{
3550	3592	#if !COMPILE_FPU \|\| !USE_SSE2
3551		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3552		_push_imm(op);
3553		_call((genf *)ppc_fmsubx);
3554		_add_r32_imm(REG_ESP, 4);
3555		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3593	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3594	emit_push_imm(DRCTOP, op);
	3595	emit_call(DRCTOP, (x86code *)ppc_fmsubx);
	3596	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3597	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3556	3598	#else
3557		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3558		_movq_r128_m64abs(REG_XMM1, &FPR(RC));
3559		_movq_r128_m64abs(REG_XMM2, &FPR(RB));
3560		_mulsd_r128_r128(REG_XMM0, REG_XMM1);
3561		_subsd_r128_r128(REG_XMM0, REG_XMM2);
3562		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3599	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3600	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RC)));
	3601	emit_movq_r128_m64(DRCTOP, REG_XMM2, MABS(&FPR(RB)));
	3602	emit_mulsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3603	emit_subsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM2);
	3604	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3563	3605
3564	3606	if (RCBIT) {
3565	3607	append_set_cr1(drc);
r949	r950
3572	3614	static UINT32 recompile_fmulx(drc_core *drc, UINT32 op)
3573	3615	{
3574	3616	#if !COMPILE_FPU \|\| !USE_SSE2
3575		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3576		_push_imm(op);
3577		_call((genf *)ppc_fmulx);
3578		_add_r32_imm(REG_ESP, 4);
3579		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3617	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3618	emit_push_imm(DRCTOP, op);
	3619	emit_call(DRCTOP, (x86code *)ppc_fmulx);
	3620	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3621	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3580	3622	#else
3581		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3582		_movq_r128_m64abs(REG_XMM1, &FPR(RC));
3583		_mulsd_r128_r128(REG_XMM0, REG_XMM1);
3584		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3623	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3624	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RC)));
	3625	emit_mulsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3626	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3585	3627
3586	3628	if (RCBIT) {
3587	3629	append_set_cr1(drc);
r949	r950
3593	3635
3594	3636	static UINT32 recompile_fnmaddx(drc_core *drc, UINT32 op)
3595	3637	{
3596		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3597		_push_imm(op);
3598		_call((genf *)ppc_fnmaddx);
3599		_add_r32_imm(REG_ESP, 4);
3600		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3638	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3639	emit_push_imm(DRCTOP, op);
	3640	emit_call(DRCTOP, (x86code *)ppc_fnmaddx);
	3641	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3642	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3601	3643
3602	3644	return RECOMPILE_SUCCESSFUL_CP(1,4);
3603	3645	}
3604	3646
3605	3647	static UINT32 recompile_fnmsubx(drc_core *drc, UINT32 op)
3606	3648	{
3607		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3608		_push_imm(op);
3609		_call((genf *)ppc_fnmsubx);
3610		_add_r32_imm(REG_ESP, 4);
3611		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3649	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3650	emit_push_imm(DRCTOP, op);
	3651	emit_call(DRCTOP, (x86code *)ppc_fnmsubx);
	3652	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3653	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3612	3654
3613	3655	return RECOMPILE_SUCCESSFUL_CP(1,4);
3614	3656	}
3615	3657
3616	3658	static UINT32 recompile_fselx(drc_core *drc, UINT32 op)
3617	3659	{
3618		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3619		_push_imm(op);
3620		_call((genf *)ppc_fselx);
3621		_add_r32_imm(REG_ESP, 4);
3622		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3660	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3661	emit_push_imm(DRCTOP, op);
	3662	emit_call(DRCTOP, (x86code *)ppc_fselx);
	3663	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3664	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3623	3665
3624	3666	return RECOMPILE_SUCCESSFUL_CP(1,4);
3625	3667	}
r949	r950
3627	3669	static UINT32 recompile_fmaddsx(drc_core *drc, UINT32 op)
3628	3670	{
3629	3671	#if !COMPILE_FPU \|\| !USE_SSE2
3630		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3631		_push_imm(op);
3632		_call((genf *)ppc_fmaddsx);
3633		_add_r32_imm(REG_ESP, 4);
3634		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3672	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3673	emit_push_imm(DRCTOP, op);
	3674	emit_call(DRCTOP, (x86code *)ppc_fmaddsx);
	3675	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3676	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3635	3677	#else
3636		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3637		_movq_r128_m64abs(REG_XMM1, &FPR(RC));
3638		_movq_r128_m64abs(REG_XMM2, &FPR(RB));
3639		_mulsd_r128_r128(REG_XMM0, REG_XMM1);
3640		_addsd_r128_r128(REG_XMM0, REG_XMM2);
3641		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3678	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3679	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RC)));
	3680	emit_movq_r128_m64(DRCTOP, REG_XMM2, MABS(&FPR(RB)));
	3681	emit_mulsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3682	emit_addsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM2);
	3683	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3642	3684
3643	3685	if (RCBIT) {
3644	3686	append_set_cr1(drc);
r949	r950
3651	3693	static UINT32 recompile_fmsubsx(drc_core *drc, UINT32 op)
3652	3694	{
3653	3695	#if !COMPILE_FPU \|\| !USE_SSE2
3654		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3655		_push_imm(op);
3656		_call((genf *)ppc_fmsubsx);
3657		_add_r32_imm(REG_ESP, 4);
3658		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3696	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3697	emit_push_imm(DRCTOP, op);
	3698	emit_call(DRCTOP, (x86code *)ppc_fmsubsx);
	3699	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3700	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3659	3701	#else
3660		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3661		_movq_r128_m64abs(REG_XMM1, &FPR(RC));
3662		_movq_r128_m64abs(REG_XMM2, &FPR(RB));
3663		_mulsd_r128_r128(REG_XMM0, REG_XMM1);
3664		_subsd_r128_r128(REG_XMM0, REG_XMM2);
3665		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3702	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3703	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RC)));
	3704	emit_movq_r128_m64(DRCTOP, REG_XMM2, MABS(&FPR(RB)));
	3705	emit_mulsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3706	emit_subsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM2);
	3707	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3666	3708
3667	3709	if (RCBIT) {
3668	3710	append_set_cr1(drc);
r949	r950
3675	3717	static UINT32 recompile_fmulsx(drc_core *drc, UINT32 op)
3676	3718	{
3677	3719	#if !COMPILE_FPU \|\| !USE_SSE2
3678		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3679		_push_imm(op);
3680		_call((genf *)ppc_fmulsx);
3681		_add_r32_imm(REG_ESP, 4);
3682		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3720	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3721	emit_push_imm(DRCTOP, op);
	3722	emit_call(DRCTOP, (x86code *)ppc_fmulsx);
	3723	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3724	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3683	3725	#else
3684		_movq_r128_m64abs(REG_XMM0, &FPR(RA));
3685		_movq_r128_m64abs(REG_XMM1, &FPR(RC));
3686		_mulsd_r128_r128(REG_XMM0, REG_XMM1);
3687		_movq_m64abs_r128(&FPR(RT), REG_XMM0);
	3726	emit_movq_r128_m64(DRCTOP, REG_XMM0, MABS(&FPR(RA)));
	3727	emit_movq_r128_m64(DRCTOP, REG_XMM1, MABS(&FPR(RC)));
	3728	emit_mulsd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1);
	3729	emit_movq_m64_r128(DRCTOP, MABS(&FPR(RT)), REG_XMM0);
3688	3730
3689	3731	if (RCBIT) {
3690	3732	append_set_cr1(drc);
r949	r950
3696	3738
3697	3739	static UINT32 recompile_fnmaddsx(drc_core *drc, UINT32 op)
3698	3740	{
3699		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3700		_push_imm(op);
3701		_call((genf *)ppc_fnmaddsx);
3702		_add_r32_imm(REG_ESP, 4);
3703		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3741	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3742	emit_push_imm(DRCTOP, op);
	3743	emit_call(DRCTOP, (x86code *)ppc_fnmaddsx);
	3744	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3745	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3704	3746
3705	3747	return RECOMPILE_SUCCESSFUL_CP(1,4);
3706	3748	}
3707	3749
3708	3750	static UINT32 recompile_fnmsubsx(drc_core *drc, UINT32 op)
3709	3751	{
3710		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3711		_push_imm(op);
3712		_call((genf *)ppc_fnmsubsx);
3713		_add_r32_imm(REG_ESP, 4);
3714		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3752	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3753	emit_push_imm(DRCTOP, op);
	3754	emit_call(DRCTOP, (x86code *)ppc_fnmsubsx);
	3755	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3756	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3715	3757
3716	3758	return RECOMPILE_SUCCESSFUL_CP(1,4);
3717	3759	}
r949	r950
3721	3763	#if (HAS_PPC602)
3722	3764	static UINT32 recompile_esa(drc_core *drc, UINT32 op)
3723	3765	{
3724		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3725		_push_imm(op);
3726		_call((genf *)ppc_esa);
3727		_add_r32_imm(REG_ESP, 4);
3728		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3766	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3767	emit_push_imm(DRCTOP, op);
	3768	emit_call(DRCTOP, (x86code *)ppc_esa);
	3769	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3770	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3729	3771
3730	3772	return RECOMPILE_SUCCESSFUL_CP(1,4);
3731	3773	}
3732	3774
3733	3775	static UINT32 recompile_dsa(drc_core *drc, UINT32 op)
3734	3776	{
3735		_mov_m32abs_r32(&ppc_icount, REG_EBP);
3736		_push_imm(op);
3737		_call((genf *)ppc_dsa);
3738		_add_r32_imm(REG_ESP, 4);
3739		_mov_r32_m32abs(REG_EBP, &ppc_icount);
	3777	emit_mov_m32_r32(DRCTOP, MABS(&ppc_icount), REG_EBP);
	3778	emit_push_imm(DRCTOP, op);
	3779	emit_call(DRCTOP, (x86code *)ppc_dsa);
	3780	emit_add_r32_imm(DRCTOP, REG_ESP, 4);
	3781	emit_mov_r32_m32(DRCTOP, REG_EBP, MABS(&ppc_icount));
3740	3782
3741	3783	return RECOMPILE_SUCCESSFUL_CP(1,4);
3742	3784	}

src/emu/cpu/powerpc/ppcdrc.c
r949	r950
270	270	drc_core *drc;
271	271	UINT32 drcoptions;
272	272
273		void * invoke_exception_handler;
274		void * generate_interrupt_exception;
275		void * generate_syscall_exception;
276		void * generate_decrementer_exception;
277		void * generate_trap_exception;
278		void * generate_dsi_exception;
279		void * generate_isi_exception;
280		void * generate_fit_exception;
	273	x86code * invoke_exception_handler;
	274	x86code * generate_interrupt_exception;
	275	x86code * generate_syscall_exception;
	276	x86code * generate_decrementer_exception;
	277	x86code * generate_trap_exception;
	278	x86code * generate_dsi_exception;
	279	x86code * generate_isi_exception;
	280	x86code * generate_fit_exception;
281	281
282	282	// PowerPC 60x specific registers */
283	283	UINT32 dec, dec_frac;
r949	r950
326	326	} PPC_OPCODE;
327	327
328	328
	329	/* code logging info */
	330	typedef struct _code_log_entry code_log_entry;
	331	struct _code_log_entry
	332	{
	333	UINT32 pc;
	334	UINT32 op;
	335	void * base;
	336	};
329	337
	338
	339
330	340	static int ppc_icount;
331	341	static int ppc_tb_base_icount;
332	342	static int ppc_dec_base_icount;
r949	r950
862	872	#include "ppc602.c"
863	873	#endif
864	874
	875	/***************************************************************************
	876	CODE LOGGING
	877	***************************************************************************/
	878
	879	#if LOG_CODE
	880
	881	static code_log_entry code_log_buffer[MAX_INSTRUCTIONS*2];
	882	static int code_log_index;
	883	static FILE *logfile;
	884
	885
	886	/*-------------------------------------------------
	887	open_logfile - open the log file if it is
	888	not already opened
	889	-------------------------------------------------*/
	890
	891	INLINE int open_logfile(void)
	892	{
	893	if (logfile == NULL)
	894	logfile = fopen("ppcdrc.asm", "w");
	895	return (logfile != NULL);
	896	}
	897
	898
	899	/*-------------------------------------------------
	900	code_log_reset - reset the logging index
	901	-------------------------------------------------*/
	902
	903	INLINE void code_log_reset(void)
	904	{
	905	code_log_index = 0;
	906	}
	907
	908
	909	/*-------------------------------------------------
	910	code_log_add_entry - add an entry to the log
	911	-------------------------------------------------*/
	912
	913	INLINE void code_log_add_entry(UINT32 pc, UINT32 op, void *base)
	914	{
	915	code_log_buffer[code_log_index].pc = pc;
	916	code_log_buffer[code_log_index].op = op;
	917	code_log_buffer[code_log_index].base = base;
	918	code_log_index++;
	919	}
	920
	921
	922	/*-------------------------------------------------
	923	code_log - actually log some code
	924	-------------------------------------------------*/
	925
	926	static void code_log(const char label, x86code start, x86code *stop)
	927	{
	928	extern int i386_dasm_one(char buffer, UINT32 eip, UINT8 oprom, int mode);
	929	offs_t ppc_dasm_one(char *buffer, UINT32 pc, UINT32 op);
	930	UINT8 *cur = start;
	931
	932	/* open the file, creating it if necessary */
	933	if (!open_logfile())
	934	return;
	935	fprintf(logfile, "\n%s\n", label);
	936
	937	/* loop from the start until the cache top */
	938	while (cur < stop)
	939	{
	940	char buffer[100];
	941	int bytes;
	942	int op;
	943
	944	/* skip filler opcodes */
	945	if (*cur == 0xcc)
	946	{
	947	cur++;
	948	continue;
	949	}
	950
	951	/* disassemble this instruction */
	952	#ifdef PTR64
	953	bytes = i386_dasm_one(buffer, (UINT32)(FPTR)cur, cur, 64) & DASMFLAG_LENGTHMASK;
	954	#else
	955	bytes = i386_dasm_one(buffer, (UINT32)cur, cur, 32) & DASMFLAG_LENGTHMASK;
	956	#endif
	957
	958	/* look for a match in the registered opcodes */
	959	for (op = 0; op < code_log_index; op++)
	960	if (code_log_buffer[op].base == (void *)cur)
	961	break;
	962
	963	/* if no match, just output the current instruction */
	964	if (op == code_log_index)
	965	fprintf(logfile, "%p: %s\n", cur, buffer);
	966
	967	/* otherwise, output with the original instruction to the right */
	968	else
	969	{
	970	char buffer2[100];
	971	ppc_dasm_one(buffer2, code_log_buffer[op].pc, code_log_buffer[op].op);
	972	fprintf(logfile, "%p: %-50s %08X: %s\n", cur, buffer, code_log_buffer[op].pc, buffer2);
	973	}
	974
	975	/* advance past this instruction */
	976	cur += bytes;
	977	}
	978
	979	/* flush the file */
	980	fflush(logfile);
	981	}
	982
	983	#else
	984
	985	#define code_log_reset()
	986	#define code_log_add_entry(a,b,c)
	987	#define code_log(a,b,c)
	988
	989	#endif
	990
	991
865	992	/********************************************************************/
866	993
867	994	#include "ppc_ops.c"

src/emu/cpu/mips/mdrcold.c
r949	r950
33	33
34	34
35	35	/***************************************************************************
	36	MACROS
	37	***************************************************************************/
	38
	39	#define REGDISP(reg) (offsetof(mips3_state, r[reg]) - offsetof(mips3_state, r[17]))
	40	#define REGADDR(reg) MBD(REG_ESI, REGDISP(reg))
	41	#define REGADDRLO(reg) MBD(REG_ESI, REGDISP(reg))
	42	#define REGADDRHI(reg) MBD(REG_ESI, REGDISP(reg)+4)
	43
	44	#define HIADDR MABS((UINT8 *)&mips3.core->hi)
	45	#define HIADDRLO MABS((UINT8 *)&mips3.core->hi)
	46	#define HIADDRHI MABS((UINT8 *)&mips3.core->hi + 4)
	47
	48	#define LOADDR MABS((UINT8 *)&mips3.core->lo)
	49	#define LOADDRLO MABS((UINT8 *)&mips3.core->lo)
	50	#define LOADDRHI MABS((UINT8 *)&mips3.core->lo + 4)
	51
	52	#define CPR0ADDR(reg) MABS((UINT8 *)&mips3.core->cpr[0][reg])
	53	#define CPR0ADDRLO(reg) MABS((UINT8 *)&mips3.core->cpr[0][reg])
	54	#define CPR0ADDRHI(reg) MABS((UINT8 *)&mips3.core->cpr[0][reg] + 4)
	55
	56	#define CCR0ADDR(reg) MABS((UINT8 *)&mips3.core->ccr[0][reg])
	57	#define CCR0ADDRLO(reg) MABS((UINT8 *)&mips3.core->ccr[0][reg])
	58	#define CCR0ADDRHI(reg) MABS((UINT8 *)&mips3.core->ccr[0][reg] + 4)
	59
	60	#define CPR1ADDR(reg) MABS((UINT8 *)&mips3.core->cpr[1][reg])
	61	#define CPR1ADDRLO(reg) MABS((UINT8 *)&mips3.core->cpr[1][reg])
	62	#define CPR1ADDRHI(reg) MABS((UINT8 *)&mips3.core->cpr[1][reg] + 4)
	63
	64	#define CCR1ADDR(reg) MABS((UINT8 *)&mips3.core->ccr[1][reg])
	65	#define CCR1ADDRLO(reg) MABS((UINT8 *)&mips3.core->ccr[1][reg])
	66	#define CCR1ADDRHI(reg) MABS((UINT8 *)&mips3.core->ccr[1][reg] + 4)
	67
	68	#define CPR2ADDR(reg) MABS((UINT8 *)&mips3.core->cpr[2][reg])
	69	#define CPR2ADDRLO(reg) MABS((UINT8 *)&mips3.core->cpr[2][reg])
	70	#define CPR2ADDRHI(reg) MABS((UINT8 *)&mips3.core->cpr[2][reg] + 4)
	71
	72	#define CCR2ADDR(reg) MABS((UINT8 *)&mips3.core->ccr[2][reg])
	73	#define CCR2ADDRLO(reg) MABS((UINT8 *)&mips3.core->ccr[2][reg])
	74	#define CCR2ADDRHI(reg) MABS((UINT8 *)&mips3.core->ccr[2][reg] + 4)
	75
	76	#define FPR32(reg) (IS_FR0 ? &((float )&mips3.core->cpr[1][0])[reg] : (float )&mips3.core->cpr[1][reg])
	77	#define FPR32ADDR(reg) MABS(FPR32(reg))
	78	#define FPR32ADDRLO(reg) MABS(FPR32(reg))
	79	#define FPR32ADDRHI(reg) MABS((UINT8 *)FPR32(reg) + 4)
	80
	81	#define FPR64(reg) (IS_FR0 ? (double )&mips3.core->cpr[1][(reg)/2] : (double )&mips3.core->cpr[1][reg])
	82	#define FPR64ADDR(reg) MABS(FPR64(reg))
	83	#define FPR64ADDR(reg) MABS(FPR64(reg))
	84	#define FPR64ADDRLO(reg) MABS(FPR64(reg))
	85	#define FPR64ADDRHI(reg) MABS((UINT8 *)FPR64(reg) + 4)
	86
	87	#define CF1ADDR(which) MABS(&mips3.core->cf[1][(mips3.core->flavor < MIPS3_TYPE_MIPS_IV) ? 0 : (which)])
	88
	89	#define ICOUNTADDR MABS(&mips3.core->icount)
	90
	91
	92	/***************************************************************************
	93	USEFUL PRIMITIVES
	94	***************************************************************************/
	95
	96	INLINE void emit_mov_r64_m64(x86code **emitptr, UINT8 reghi, UINT8 reglo, DECLARE_MEMPARAMS)
	97	{
	98	emit_mov_r32_m32(emitptr, reglo, MEMPARAMS);
	99	emit_mov_r32_m32(emitptr, reghi, base, index, scale, disp+4);
	100	}
	101
	102	INLINE void emit_mov_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 reghi, UINT8 reglo)
	103	{
	104	emit_mov_m32_r32(emitptr, MEMPARAMS, reglo);
	105	emit_mov_m32_r32(emitptr, base, index, scale, disp+4, reghi);
	106	}
	107
	108	INLINE void emit_mov_m64_imm32(x86code **emitptr, DECLARE_MEMPARAMS, INT32 imm)
	109	{
	110	emit_mov_m32_imm(emitptr, MEMPARAMS, imm);
	111	emit_mov_m32_imm(emitptr, base, index, scale, disp+4, (INT32)imm >> 31);
	112	}
	113
	114	INLINE void emit_zero_m64(x86code **emitptr, DECLARE_MEMPARAMS)
	115	{
	116	if (USE_SSE)
	117	{
	118	emit_xorpd_r128_r128(emitptr, REG_XMM0, REG_XMM0);
	119	emit_movsd_m64_r128(emitptr, MEMPARAMS, REG_XMM0);
	120	}
	121	else
	122	emit_mov_m64_imm32(emitptr, MEMPARAMS, 0);
	123	}
	124
	125	INLINE void emit_mov_m64_m64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 base2, UINT8 index2, UINT8 scale2, INT32 disp2)
	126	{
	127	if (USE_SSE)
	128	{
	129	emit_movsd_r128_m64(emitptr, REG_XMM0, base2, index2, scale2, disp2);
	130	emit_movsd_m64_r128(emitptr, MEMPARAMS, REG_XMM0);
	131	}
	132	else
	133	{
	134	emit_mov_r64_m64(emitptr, REG_EDX, REG_EAX, base2, index2, scale2, disp2);
	135	emit_mov_m64_r64(emitptr, MEMPARAMS, REG_EDX, REG_EAX);
	136	}
	137	}
	138
	139	#define emit_save_pc_before_call(e) \
	140	do { \
	141	if (mips3.drcoptions & MIPS3DRC_FLUSH_PC) \
	142	emit_mov_m32_r32(e, MABS(drc->pcptr), REG_EDI); \
	143	} while (0)
	144
	145
	146
	147
	148	/***************************************************************************
36	149	TYPEDEFS
37	150	***************************************************************************/
38	151
39	152	struct _mips3drc_data
40	153	{
41		void * generate_interrupt_exception;
42		void * generate_cop_exception;
43		void * generate_overflow_exception;
44		void * generate_invalidop_exception;
45		void * generate_syscall_exception;
46		void * generate_break_exception;
47		void * generate_trap_exception;
48		void * generate_tlbload_exception;
49		void * generate_tlbstore_exception;
50		void * handle_pc_tlb_mismatch;
51		void * read_and_translate_byte_signed;
52		void * read_and_translate_byte_unsigned;
53		void * read_and_translate_word_signed;
54		void * read_and_translate_word_unsigned;
55		void * read_and_translate_long;
56		void * read_and_translate_long_masked;
57		void * read_and_translate_double;
58		void * read_and_translate_double_masked;
59		void * write_and_translate_byte;
60		void * write_and_translate_word;
61		void * write_and_translate_long;
62		void * write_and_translate_long_masked;
63		void * write_and_translate_double;
64		void * write_and_translate_double_masked;
	154	x86code * generate_interrupt_exception;
	155	x86code * generate_cop_exception;
	156	x86code * generate_overflow_exception;
	157	x86code * generate_invalidop_exception;
	158	x86code * generate_syscall_exception;
	159	x86code * generate_break_exception;
	160	x86code * generate_trap_exception;
	161	x86code * generate_tlbload_exception;
	162	x86code * generate_tlbstore_exception;
	163	x86code * handle_pc_tlb_mismatch;
	164	x86code * read_and_translate_byte_signed;
	165	x86code * read_and_translate_byte_unsigned;
	166	x86code * read_and_translate_word_signed;
	167	x86code * read_and_translate_word_unsigned;
	168	x86code * read_and_translate_long;
	169	x86code * read_and_translate_long_masked;
	170	x86code * read_and_translate_double;
	171	x86code * read_and_translate_double_masked;
	172	x86code * write_and_translate_byte;
	173	x86code * write_and_translate_word;
	174	x86code * write_and_translate_long;
	175	x86code * write_and_translate_long_masked;
	176	x86code * write_and_translate_double;
	177	x86code * write_and_translate_double_masked;
65	178	};
66	179
67	180
r949	r950
169	282	{
170	283	code_log_reset();
171	284
	285	code_log("entry_point:", (x86code *)drc->entry_point, drc->out_of_cycles);
	286	code_log("out_of_cycles:", drc->out_of_cycles, drc->recompile);
	287	code_log("recompile:", drc->recompile, drc->dispatch);
	288	code_log("dispatch:", drc->dispatch, drc->flush);
	289	code_log("flush:", drc->flush, drc->cache_top);
	290
172	291	mips3.drcdata->generate_interrupt_exception = drc->cache_top;
173	292	append_generate_exception(drc, EXCEPTION_INTERRUPT);
174	293	code_log("generate_interrupt_exception:", mips3.drcdata->generate_interrupt_exception, drc->cache_top);
r949	r950
206	325	code_log("generate_tlbstore_exception:", mips3.drcdata->generate_tlbstore_exception, drc->cache_top);
207	326
208	327	mips3.drcdata->handle_pc_tlb_mismatch = drc->cache_top;
209		_mov_r32_r32(REG_EAX, REG_EDI); // mov eax,edi
210		_shr_r32_imm(REG_EAX, 12); // shr eax,12
211		_mov_r32_m32isd(REG_EBX, REG_EAX, 4, mips3.core->tlb_table); // mov ebx,tlb_table[eax*4]
212		_test_r32_imm(REG_EBX, 2); // test ebx,2
213		_mov_r32_r32(REG_EAX, REG_EDI); // mov eax,edi
214		_jcc(COND_NZ, mips3.drcdata->generate_tlbload_exception); // jnz generate_tlbload_exception
215		_mov_m32abs_r32(drc->pcptr, REG_EDI); // mov [pcptr],edi
216		_jmp(drc->recompile); // call recompile
	328	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_EDI); // mov eax,edi
	329	emit_shr_r32_imm(DRCTOP, REG_EAX, 12); // shr eax,12
	330	emit_mov_r32_m32(DRCTOP, REG_EBX, MISD(REG_EAX, 4, mips3.core->tlb_table)); // mov ebx,tlb_table[eax*4]
	331	emit_test_r32_imm(DRCTOP, REG_EBX, 2); // test ebx,2
	332	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_EDI); // mov eax,edi
	333	emit_jcc(DRCTOP, COND_NZ, mips3.drcdata->generate_tlbload_exception); // jnz generate_tlbload_exception
	334	emit_mov_m32_r32(DRCTOP, MABS(drc->pcptr), REG_EDI); // mov [pcptr],edi
	335	emit_jmp(DRCTOP, drc->recompile); // jmp recompile
217	336	code_log("handle_pc_tlb_mismatch:", mips3.drcdata->handle_pc_tlb_mismatch, drc->cache_top);
218	337
219	338	mips3.drcdata->read_and_translate_byte_signed = drc->cache_top;
r949	r950
281	400	static void drc_recompile_callback(drc_core *drc)
282	401	{
283	402	int remaining = MAX_INSTRUCTIONS;
284		void *start = drc->cache_top;
	403	x86code *start = drc->cache_top;
285	404	UINT32 pc = mips3.core->pc;
286	405	UINT32 lastpc = pc;
287	406	UINT32 physpc;
r949	r950
293	412	code_log_reset();
294	413
295	414	/* make sure our FR flag matches the last time */
296		_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_FR); // test [COP0_Status],SR_FR
297		_jcc(IS_FR0 ? COND_NZ : COND_Z, drc->recompile); // jnz/z recompile
	415	emit_test_m32_imm(DRCTOP, CPR0ADDR(COP0_Status), SR_FR); // test [COP0_Status],SR_FR
	416	emit_jcc(DRCTOP, IS_FR0 ? COND_NZ : COND_Z, drc->recompile); // jnz/z recompile
298	417
299	418	/* ensure that we are still mapped */
300	419	append_tlb_verify(drc, pc, mips3.drcdata->handle_pc_tlb_mismatch);
301	420	physpc = pc;
302	421	if (!mips3com_translate_address(mips3.core, ADDRESS_SPACE_PROGRAM, &physpc))
303	422	{
304		_mov_r32_r32(REG_EAX, REG_EDI); // mov eax,edi
305		_jmp(mips3.drcdata->generate_tlbload_exception); // jmp tlbload_exception
	423	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_EDI); // mov eax,edi
	424	emit_jmp(DRCTOP, mips3.drcdata->generate_tlbload_exception); // jmp tlbload_exception
306	425	goto exit;
307	426	}
308	427	change_pc(physpc);
r949	r950
361	480
362	481	static void drc_entrygen_callback(drc_core *drc)
363	482	{
364		_mov_r32_imm(REG_ESI, &mips3.core->r[17]);
	483	emit_mov_r32_imm(DRCTOP, REG_ESI, (FPTR)&mips3.core->r[17]);
365	484	append_check_interrupts(drc, 1);
366	485	}
367	486
r949	r950
448	567	static void append_generate_exception(drc_core *drc, UINT8 exception)
449	568	{
450	569	UINT32 offset = (exception >= EXCEPTION_TLBMOD && exception <= EXCEPTION_TLBSTORE) ? 0x00 : 0x180;
451		link_info link1, link2;
	570	emit_link link1, link2;
452	571
453	572	/* assumes address is in EAX */
454	573	if (exception == EXCEPTION_TLBLOAD \|\| exception == EXCEPTION_TLBSTORE)
455	574	{
456		_mov_m32abs_r32(&mips3.core->cpr[0][COP0_BadVAddr], REG_EAX); // mov [mips3.core->cpr[0][BadVAddr]],eax
457		_and_m32abs_imm(&mips3.core->cpr[0][COP0_EntryHi], 0x000000ff); // and [mips3.core->cpr[0][EntryHi]],0x000000ff
458		_and_r32_imm(REG_EAX, 0xffffe000); // and eax,0xffffe000
459		_or_m32abs_r32(&mips3.core->cpr[0][COP0_EntryHi], REG_EAX); // or [mips3.core->cpr[0][EntryHi]],eax
460		_and_m32abs_imm(&mips3.core->cpr[0][COP0_Context], 0xff800000); // and [mips3.core->cpr[0][Context]],0xff800000
461		_shr_r32_imm(REG_EAX, 9); // shr eax,9
462		_or_m32abs_r32(&mips3.core->cpr[0][COP0_Context], REG_EAX); // or [mips3.core->cpr[0][Context]],eax
	575	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_BadVAddr), REG_EAX); // mov [BadVAddr],eax
	576	emit_and_m32_imm(DRCTOP, CPR0ADDR(COP0_EntryHi), 0x000000ff); // and [EntryHi],0x000000ff
	577	emit_and_r32_imm(DRCTOP, REG_EAX, 0xffffe000); // and eax,0xffffe000
	578	emit_or_m32_r32(DRCTOP, CPR0ADDR(COP0_EntryHi), REG_EAX); // or [EntryHi],eax
	579	emit_and_m32_imm(DRCTOP, CPR0ADDR(COP0_Context), 0xff800000); // and [Context],0xff800000
	580	emit_shr_r32_imm(DRCTOP, REG_EAX, 9); // shr eax,9
	581	emit_or_m32_r32(DRCTOP, CPR0ADDR(COP0_Context), REG_EAX); // or [Context],eax
463	582	}
464	583
465		_mov_m32abs_r32(&mips3.core->cpr[0][COP0_EPC], REG_EDI); // mov [mips3.core->cpr[0][COP0_EPC]],edi
466		_mov_r32_m32abs(REG_EAX, &mips3.core->cpr[0][COP0_Cause]); // mov eax,[mips3.core->cpr[0][COP0_Cause]]
467		_and_r32_imm(REG_EAX, ~0x800000ff); // and eax,~0x800000ff
	584	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_EPC), REG_EDI); // mov [COP0_EPC],edi
	585	emit_mov_r32_m32(DRCTOP, REG_EAX, CPR0ADDR(COP0_Cause)); // mov eax,[COP0_Cause]
	586	emit_and_r32_imm(DRCTOP, REG_EAX, ~0x800000ff); // and eax,~0x800000ff
468	587	if (exception)
469		_or_r32_imm(REG_EAX, exception << 2); // or eax,exception << 2
470		_cmp_m32abs_imm(&mips3.nextpc, ~0); // cmp [mips3.nextpc],~0
471		_jcc_short_link(COND_E, &link1); // je skip
472		_mov_m32abs_imm(&mips3.nextpc, ~0); // mov [mips3.nextpc],~0
473		_sub_m32abs_imm(&mips3.core->cpr[0][COP0_EPC], 4); // sub [mips3.core->cpr[0][COP0_EPC]],4
474		_or_r32_imm(REG_EAX, 0x80000000); // or eax,0x80000000
475		_resolve_link(&link1); // skip:
476		_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Cause], REG_EAX); // mov [mips3.core->cpr[0][COP0_Cause]],eax
477		_mov_r32_m32abs(REG_EAX, &mips3.core->cpr[0][COP0_Status]); // mov eax,[[mips3.core->cpr[0][COP0_Status]]
478		_or_r32_imm(REG_EAX, SR_EXL); // or eax,SR_EXL
479		_test_r32_imm(REG_EAX, SR_BEV); // test eax,SR_BEV
480		_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Status], REG_EAX); // mov [[mips3.core->cpr[0][COP0_Status]],eax
481		_mov_r32_imm(REG_EDI, 0xbfc00200 + offset); // mov edi,0xbfc00200+offset
482		_jcc_short_link(COND_NZ, &link2); // jnz skip2
483		_mov_r32_imm(REG_EDI, 0x80000000 + offset); // mov edi,0x80000000+offset
484		_resolve_link(&link2); // skip2:
485		drc_append_dispatcher(drc); // dispatch
	588	emit_or_r32_imm(DRCTOP, REG_EAX, exception << 2); // or eax,exception << 2
	589	emit_cmp_m32_imm(DRCTOP, MABS(&mips3.nextpc), ~0); // cmp [mips3.nextpc],~0
	590	emit_jcc_short_link(DRCTOP, COND_E, &link1); // je skip
	591	emit_mov_m32_imm(DRCTOP, MABS(&mips3.nextpc), ~0); // mov [mips3.nextpc],~0
	592	emit_sub_m32_imm(DRCTOP, CPR0ADDR(COP0_EPC), 4); // sub [COP0_EPC],4
	593	emit_or_r32_imm(DRCTOP, REG_EAX, 0x80000000); // or eax,0x80000000
	594	resolve_link(DRCTOP, &link1); // skip:
	595	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_Cause), REG_EAX); // mov [COP0_Cause],eax
	596	emit_mov_r32_m32(DRCTOP, REG_EAX, CPR0ADDR(COP0_Status)); // mov eax,[COP0_Status]
	597	emit_or_r32_imm(DRCTOP, REG_EAX, SR_EXL); // or eax,SR_EXL
	598	emit_test_r32_imm(DRCTOP, REG_EAX, SR_BEV); // test eax,SR_BEV
	599	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_Status), REG_EAX); // mov [COP0_Status],eax
	600	emit_mov_r32_imm(DRCTOP, REG_EDI, 0xbfc00200 + offset); // mov edi,0xbfc00200+offset
	601	emit_jcc_short_link(DRCTOP, COND_NZ, &link2); // jnz skip2
	602	emit_mov_r32_imm(DRCTOP, REG_EDI, 0x80000000 + offset); // mov edi,0x80000000+offset
	603	resolve_link(DRCTOP, &link2); // skip2:
	604	drc_append_dispatcher(drc); // dispatch
486	605	}
487	606
488	607
r949	r950
492	611
493	612	static void append_readwrite_and_translate(drc_core *drc, int size, UINT8 flags)
494	613	{
495		link_info link1 = { 0 }, link2 = { 0 }, link3 = { 0 };
	614	emit_link link1 = { 0 }, link2 = { 0 }, link3 = { 0 };
496	615	int ramnum;
497	616
498		_mov_r32_m32bd(REG_EAX, REG_ESP, 4); // mov eax,[esp+4]
499		_mov_r32_r32(REG_EBX, REG_EAX); // mov ebx,eax
500		_shr_r32_imm(REG_EBX, 12); // shr ebx,12
501		_mov_r32_m32isd(REG_EBX, REG_EBX, 4, mips3.core->tlb_table); // mov ebx,tlb_table[ebx*4]
502		_and_r32_imm(REG_EAX, 0xfff); // and eax,0xfff
503		_shr_r32_imm(REG_EBX, ((flags & ARW_WRITE) ? 1 : 2)); // shr ebx,2/1 (read/write)
504		_lea_r32_m32bisd(REG_EBX, REG_EAX, REG_EBX, ((flags & ARW_WRITE) ? 2 : 4), 0); // lea ebx,[eax+ebx*4/2] (read/write)
505		_jcc_near_link(COND_C, &link1); // jc error
	617	emit_mov_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 4)); // mov eax,[esp+4]
	618	emit_mov_r32_r32(DRCTOP, REG_EBX, REG_EAX); // mov ebx,eax
	619	emit_shr_r32_imm(DRCTOP, REG_EBX, 12); // shr ebx,12
	620	emit_mov_r32_m32(DRCTOP, REG_EBX, MISD(REG_EBX, 4, mips3.core->tlb_table)); // mov ebx,tlb_table[ebx*4]
	621	emit_and_r32_imm(DRCTOP, REG_EAX, 0xfff); // and eax,0xfff
	622	emit_shr_r32_imm(DRCTOP, REG_EBX, ((flags & ARW_WRITE) ? 1 : 2)); // shr ebx,2/1 (read/write)
	623	emit_lea_r32_m32(DRCTOP, REG_EBX, MBISD(REG_EAX, REG_EBX, ((flags & ARW_WRITE) ? 2 : 4), 0));
	624	// lea ebx,[eax+ebx*4/2] (read/write)
	625	emit_jcc_near_link(DRCTOP, COND_C, &link1); // jc error
506	626	for (ramnum = 0; ramnum < MIPS3_MAX_FASTRAM; ramnum++)
507	627	if (!Machine->debug_mode && mips3.fastram[ramnum].base && (!(flags & ARW_WRITE) \|\| !mips3.fastram[ramnum].readonly))
508	628	{
509	629	UINT32 fastbase = (UINT32)((UINT8 *)mips3.fastram[ramnum].base - mips3.fastram[ramnum].start);
510	630	if (mips3.fastram[ramnum].end != 0xffffffff)
511	631	{
512		_cmp_r32_imm(REG_EBX, mips3.fastram[ramnum].end); // cmp ebx,fastram_end
513		_jcc_short_link(COND_A, &link2); // ja notram
	632	emit_cmp_r32_imm(DRCTOP, REG_EBX, mips3.fastram[ramnum].end); // cmp ebx,fastram_end
	633	emit_jcc_short_link(DRCTOP, COND_A, &link2); // ja notram
514	634	}
515	635	if (mips3.fastram[ramnum].start != 0x00000000)
516	636	{
517		_cmp_r32_imm(REG_EBX, mips3.fastram[ramnum].start); // cmp ebx,fastram_start
518		_jcc_short_link(COND_B, &link3); // jb notram
	637	emit_cmp_r32_imm(DRCTOP, REG_EBX, mips3.fastram[ramnum].start); // cmp ebx,fastram_start
	638	emit_jcc_short_link(DRCTOP, COND_B, &link3); // jb notram
519	639	}
520	640
521	641	if (!(flags & ARW_WRITE))
r949	r950
523	643	if (size == 1)
524	644	{
525	645	if (mips3.core->bigendian)
526		_xor_r32_imm(REG_EBX, 3); // xor ebx,3
	646	emit_xor_r32_imm(DRCTOP, REG_EBX, 3); // xor ebx,3
527	647	if (flags & ARW_SIGNED)
528		_movsx_r32_m8bd(REG_EAX, REG_EBX, fastbase); // movsx eax,byte ptr [ebx+fastbase]
	648	emit_movsx_r32_m8(DRCTOP, REG_EAX, MBD(REG_EBX, fastbase)); // movsx eax,byte ptr [ebx+fastbase]
529	649	else
530		_movzx_r32_m8bd(REG_EAX, REG_EBX, fastbase); // movzx eax,byte ptr [ebx+fastbase]
	650	emit_movzx_r32_m8(DRCTOP, REG_EAX, MBD(REG_EBX, fastbase)); // movzx eax,byte ptr [ebx+fastbase]
531	651	}
532	652	else if (size == 2)
533	653	{
534	654	if (mips3.core->bigendian)
535		_xor_r32_imm(REG_EBX, 2); // xor ebx,2
	655	emit_xor_r32_imm(DRCTOP, REG_EBX, 2); // xor ebx,2
536	656	if (flags & ARW_SIGNED)
537		_movsx_r32_m16bd(REG_EAX, REG_EBX, fastbase); // movsx eax,word ptr [ebx+fastbase]
	657	emit_movsx_r32_m16(DRCTOP, REG_EAX, MBD(REG_EBX, fastbase)); // movsx eax,word ptr [ebx+fastbase]
538	658	else
539		_movzx_r32_m16bd(REG_EAX, REG_EBX, fastbase); // movzx eax,word ptr [ebx+fastbase]
	659	emit_movzx_r32_m16(DRCTOP, REG_EAX, MBD(REG_EBX, fastbase)); // movzx eax,word ptr [ebx+fastbase]
540	660	}
541	661	else if (size == 4)
542		_mov_r32_m32bd(REG_EAX, REG_EBX, fastbase); // mov eax,[ebx+fastbase]
	662	emit_mov_r32_m32(DRCTOP, REG_EAX, MBD(REG_EBX, fastbase)); // mov eax,[ebx+fastbase]
543	663	else if (size == 8)
544	664	{
545	665	if (mips3.core->bigendian)
546		_mov_r64_m64bd(REG_EAX, REG_EDX, REG_EBX, fastbase); // mov eax:edx,[ebx+fastbase]
	666	emit_mov_r64_m64(DRCTOP, REG_EAX, REG_EDX, MBD(REG_EBX, (FPTR)fastbase));
	667	// mov eax:edx,[ebx+fastbase]
547	668	else
548		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_EBX, fastbase); // mov edx:eax,[ebx+fastbase]
	669	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, MBD(REG_EBX, (FPTR)fastbase));
	670	// mov edx:eax,[ebx+fastbase]
549	671	}
550		_ret(); // ret
	672	emit_ret(DRCTOP); // ret
551	673	}
552	674	else
553	675	{
554	676	if (size == 1)
555	677	{
556		_mov_r8_m8bd(REG_AL, REG_ESP, 8); // mov al,[esp+8]
	678	emit_mov_r8_m8(DRCTOP, REG_AL, MBD(REG_ESP, 8)); // mov al,[esp+8]
557	679	if (mips3.core->bigendian)
558		_xor_r32_imm(REG_EBX, 3); // xor ebx,3
559		_mov_m8bd_r8(REG_EBX, fastbase, REG_AL); // mov [ebx+fastbase],al
	680	emit_xor_r32_imm(DRCTOP, REG_EBX, 3); // xor ebx,3
	681	emit_mov_m8_r8(DRCTOP, MBD(REG_EBX, fastbase), REG_AL); // mov [ebx+fastbase],al
560	682	}
561	683	else if (size == 2)
562	684	{
563		_mov_r16_m16bd(REG_AX, REG_ESP, 8); // mov ax,[esp+8]
	685	emit_mov_r16_m16(DRCTOP, REG_AX, MBD(REG_ESP, 8)); // mov ax,[esp+8]
564	686	if (mips3.core->bigendian)
565		_xor_r32_imm(REG_EBX, 2); // xor ebx,2
566		_mov_m16bd_r16(REG_EBX, fastbase, REG_AX); // mov [ebx+fastbase],ax
	687	emit_xor_r32_imm(DRCTOP, REG_EBX, 2); // xor ebx,2
	688	emit_mov_m16_r16(DRCTOP, MBD(REG_EBX, fastbase), REG_AX); // mov [ebx+fastbase],ax
567	689	}
568	690	else if (size == 4)
569	691	{
570	692	if (!(flags & ARW_MASKED))
571	693	{
572		_mov_r32_m32bd(REG_EAX, REG_ESP, 8); // mov eax,[esp+8]
573		_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
	694	emit_mov_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 8)); // mov eax,[esp+8]
	695	emit_mov_m32_r32(DRCTOP, MBD(REG_EBX, fastbase), REG_EAX); // mov [ebx+fastbase],eax
574	696	}
575	697	else
576	698	{
577		_mov_r32_m32bd(REG_ECX, REG_ESP, 12); // mov ecx,[esp+12]
578		_mov_r32_r32(REG_EAX, REG_ECX); // mov eax,ecx
579		_and_r32_m32bd(REG_ECX, REG_EBX, fastbase); // and ecx,[ebx+fastbase]
580		_not_r32(REG_EAX); // not eax
581		_and_r32_m32bd(REG_EAX, REG_ESP, 8); // and eax,[esp+8]
582		_or_r32_r32(REG_EAX, REG_ECX); // or eax,ecx
583		_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
	699	emit_mov_r32_m32(DRCTOP, REG_ECX, MBD(REG_ESP, 12)); // mov ecx,[esp+12]
	700	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_ECX); // mov eax,ecx
	701	emit_and_r32_m32(DRCTOP, REG_ECX, MBD(REG_EBX, fastbase)); // and ecx,[ebx+fastbase]
	702	emit_not_r32(DRCTOP, REG_EAX); // not eax
	703	emit_and_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 8)); // and eax,[esp+8]
	704	emit_or_r32_r32(DRCTOP, REG_EAX, REG_ECX); // or eax,ecx
	705	emit_mov_m32_r32(DRCTOP, MBD(REG_EBX, fastbase), REG_EAX); // mov [ebx+fastbase],eax
584	706	}
585	707	}
586	708	else if (size == 8)
r949	r950
589	711	{
590	712	if (mips3.core->bigendian)
591	713	{
592		_mov_r32_m32bd(REG_EAX, REG_ESP, 8); // mov eax,[esp+8]
593		_mov_m32bd_r32(REG_EBX, fastbase+4, REG_EAX); // mov [ebx+fastbase+4],eax
594		_mov_r32_m32bd(REG_EAX, REG_ESP, 12); // mov eax,[esp+12]
595		_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
	714	emit_mov_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 8)); // mov eax,[esp+8]
	715	emit_mov_m32_r32(DRCTOP, MBD(REG_EBX, fastbase+4), REG_EAX); // mov [ebx+fastbase+4],eax
	716	emit_mov_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 12)); // mov eax,[esp+12]
	717	emit_mov_m32_r32(DRCTOP, MBD(REG_EBX, fastbase), REG_EAX); // mov [ebx+fastbase],eax
596	718	}
597	719	else
598	720	{
599		_mov_r32_m32bd(REG_EAX, REG_ESP, 8); // mov eax,[esp+8]
600		_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
601		_mov_r32_m32bd(REG_EAX, REG_ESP, 12); // mov eax,[esp+12]
602		_mov_m32bd_r32(REG_EBX, fastbase+4, REG_EAX); // mov [ebx+fastbase+4],eax
	721	emit_mov_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 8)); // mov eax,[esp+8]
	722	emit_mov_m32_r32(DRCTOP, MBD(REG_EBX, fastbase), REG_EAX); // mov [ebx+fastbase],eax
	723	emit_mov_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 12)); // mov eax,[esp+12]
	724	emit_mov_m32_r32(DRCTOP, MBD(REG_EBX, fastbase+4), REG_EAX); // mov [ebx+fastbase+4],eax
603	725	}
604	726	}
605	727	else
606	728	{
607	729	if (mips3.core->bigendian)
608	730	{
609		_mov_r32_m32bd(REG_ECX, REG_ESP, 16); // mov ecx,[esp+16]
610		_mov_r32_r32(REG_EAX, REG_ECX); // mov eax,ecx
611		_and_r32_m32bd(REG_ECX, REG_EBX, fastbase+4); // and ecx,[ebx+fastbase+4]
612		_not_r32(REG_EAX); // not eax
613		_and_r32_m32bd(REG_EAX, REG_ESP, 8); // and eax,[esp+8]
614		_or_r32_r32(REG_EAX, REG_ECX); // or eax,ecx
615		_mov_m32bd_r32(REG_EBX, fastbase+4, REG_EAX); // mov [ebx+fastbase+4],eax
616		_mov_r32_m32bd(REG_ECX, REG_ESP, 20); // mov ecx,[esp+20]
617		_mov_r32_r32(REG_EAX, REG_ECX); // mov eax,ecx
618		_and_r32_m32bd(REG_ECX, REG_EBX, fastbase); // and ecx,[ebx+fastbase]
619		_not_r32(REG_EAX); // not eax
620		_and_r32_m32bd(REG_EAX, REG_ESP, 12); // and eax,[esp+12]
621		_or_r32_r32(REG_EAX, REG_ECX); // or eax,ecx
622		_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
	731	emit_mov_r32_m32(DRCTOP, REG_ECX, MBD(REG_ESP, 16)); // mov ecx,[esp+16]
	732	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_ECX); // mov eax,ecx
	733	emit_and_r32_m32(DRCTOP, REG_ECX, MBD(REG_EBX, fastbase+4)); // and ecx,[ebx+fastbase+4]
	734	emit_not_r32(DRCTOP, REG_EAX); // not eax
	735	emit_and_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 8)); // and eax,[esp+8]
	736	emit_or_r32_r32(DRCTOP, REG_EAX, REG_ECX); // or eax,ecx
	737	emit_mov_m32_r32(DRCTOP, MBD(REG_EBX, fastbase+4), REG_EAX); // mov [ebx+fastbase+4],eax
	738	emit_mov_r32_m32(DRCTOP, REG_ECX, MBD(REG_ESP, 20)); // mov ecx,[esp+20]
	739	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_ECX); // mov eax,ecx
	740	emit_and_r32_m32(DRCTOP, REG_ECX, MBD(REG_EBX, fastbase)); // and ecx,[ebx+fastbase]
	741	emit_not_r32(DRCTOP, REG_EAX); // not eax
	742	emit_and_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 12)); // and eax,[esp+12]
	743	emit_or_r32_r32(DRCTOP, REG_EAX, REG_ECX); // or eax,ecx
	744	emit_mov_m32_r32(DRCTOP, MBD(REG_EBX, fastbase), REG_EAX); // mov [ebx+fastbase],eax
623	745	}
624	746	else
625	747	{
626		_mov_r32_m32bd(REG_ECX, REG_ESP, 16); // mov ecx,[esp+16]
627		_mov_r32_r32(REG_EAX, REG_ECX); // mov eax,ecx
628		_and_r32_m32bd(REG_ECX, REG_EBX, fastbase); // and ecx,[ebx+fastbase]
629		_not_r32(REG_EAX); // not eax
630		_and_r32_m32bd(REG_EAX, REG_ESP, 8); // and eax,[esp+8]
631		_or_r32_r32(REG_EAX, REG_ECX); // or eax,ecx
632		_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
633		_mov_r32_m32bd(REG_ECX, REG_ESP, 20); // mov ecx,[esp+20]
634		_mov_r32_r32(REG_EAX, REG_ECX); // mov eax,ecx
635		_and_r32_m32bd(REG_ECX, REG_EBX, fastbase+4); // and ecx,[ebx+fastbase+4]
636		_not_r32(REG_EAX); // not eax
637		_and_r32_m32bd(REG_EAX, REG_ESP, 12); // and eax,[esp+12]
638		_or_r32_r32(REG_EAX, REG_ECX); // or eax,ecx
639		_mov_m32bd_r32(REG_EBX, fastbase+4, REG_EAX); // mov [ebx+fastbase+4],eax
	748	emit_mov_r32_m32(DRCTOP, REG_ECX, MBD(REG_ESP, 16)); // mov ecx,[esp+16]
	749	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_ECX); // mov eax,ecx
	750	emit_and_r32_m32(DRCTOP, REG_ECX, MBD(REG_EBX, fastbase)); // and ecx,[ebx+fastbase]
	751	emit_not_r32(DRCTOP, REG_EAX); // not eax
	752	emit_and_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 8)); // and eax,[esp+8]
	753	emit_or_r32_r32(DRCTOP, REG_EAX, REG_ECX); // or eax,ecx
	754	emit_mov_m32_r32(DRCTOP, MBD(REG_EBX, fastbase), REG_EAX); // mov [ebx+fastbase],eax
	755	emit_mov_r32_m32(DRCTOP, REG_ECX, MBD(REG_ESP, 20)); // mov ecx,[esp+20]
	756	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_ECX); // mov eax,ecx
	757	emit_and_r32_m32(DRCTOP, REG_ECX, MBD(REG_EBX, fastbase+4)); // and ecx,[ebx+fastbase+4]
	758	emit_not_r32(DRCTOP, REG_EAX); // not eax
	759	emit_and_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 12)); // and eax,[esp+12]
	760	emit_or_r32_r32(DRCTOP, REG_EAX, REG_ECX); // or eax,ecx
	761	emit_mov_m32_r32(DRCTOP, MBD(REG_EBX, fastbase+4), REG_EAX); // mov [ebx+fastbase+4],eax
640	762	}
641	763	}
642	764	}
643		_ret(); // ret
	765	emit_ret(DRCTOP); // ret
644	766	}
645	767
646		if (mips3.fastram[ramnum].end != 0xffffffff) // notram:
647		_resolve_link(&link2);
	768	if (mips3.fastram[ramnum].end != 0xffffffff) // notram:
	769	resolve_link(DRCTOP, &link2);
648	770	if (mips3.fastram[ramnum].start != 0x00000000)
649		_resolve_link(&link3);
	771	resolve_link(DRCTOP, &link3);
650	772	}
651	773
652	774	if (flags & ARW_WRITE)
653	775	{
654		_mov_m32bd_r32(REG_ESP, 4, REG_EBX); // mov [esp+4],ebx
	776	emit_mov_m32_r32(DRCTOP, MBD(REG_ESP, 4), REG_EBX); // mov [esp+4],ebx
655	777	if (size == 1)
656		_jmp(mips3.core->memory.writebyte); // jmp writebyte
	778	emit_jmp(DRCTOP, (x86code *)mips3.core->memory.writebyte); // jmp writebyte
657	779	else if (size == 2)
658		_jmp(mips3.core->memory.writeword); // jmp writeword
	780	emit_jmp(DRCTOP, (x86code *)mips3.core->memory.writeword); // jmp writeword
659	781	else if (size == 4)
660	782	{
661	783	if (!(flags & ARW_MASKED))
662		_jmp(mips3.core->memory.writelong); // jmp writelong
	784	emit_jmp(DRCTOP, (x86code *)mips3.core->memory.writelong); // jmp writelong
663	785	else
664		_jmp(mips3.core->memory.writelong_masked); // jmp writelong_masked
	786	emit_jmp(DRCTOP, (x86code *)mips3.core->memory.writelong_masked); // jmp writelong_masked
665	787	}
666	788	else
667	789	{
668	790	if (!(flags & ARW_MASKED))
669		_jmp(mips3.core->memory.writedouble); // jmp writedouble
	791	emit_jmp(DRCTOP, (x86code *)mips3.core->memory.writedouble); // jmp writedouble
670	792	else
671		_jmp(mips3.core->memory.writedouble_masked); // jmp writedouble_masked
	793	emit_jmp(DRCTOP, (x86code *)mips3.core->memory.writedouble_masked); // jmp writedouble_masked
672	794	}
673	795	}
674	796	else
675	797	{
676	798	if (size == 1)
677	799	{
678		_sub_r32_imm(REG_ESP, 8); // sub esp,8
679		_push_r32(REG_EBX); // push ebx
680		_call(mips3.core->memory.readbyte); // call readbyte
	800	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
	801	emit_push_r32(DRCTOP, REG_EBX); // push ebx
	802	emit_call(DRCTOP, (x86code *)mips3.core->memory.readbyte); // call readbyte
681	803	if (flags & ARW_SIGNED)
682		_movsx_r32_r8(REG_EAX, REG_AL); // movsx eax,al
	804	emit_movsx_r32_r8(DRCTOP, REG_EAX, REG_AL); // movsx eax,al
683	805	else
684		_movzx_r32_r8(REG_EAX, REG_AL); // movzx eax,al
685		_add_r32_imm(REG_ESP, 12); // add esp,12
686		_ret(); // ret
	806	emit_movzx_r32_r8(DRCTOP, REG_EAX, REG_AL); // movzx eax,al
	807	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	808	emit_ret(DRCTOP); // ret
687	809	}
688	810	else if (size == 2)
689	811	{
690		_sub_r32_imm(REG_ESP, 8); // sub esp,8
691		_push_r32(REG_EBX); // push ebx
692		_call(mips3.core->memory.readword); // call readword
	812	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
	813	emit_push_r32(DRCTOP, REG_EBX); // push ebx
	814	emit_call(DRCTOP, (x86code *)mips3.core->memory.readword); // call readword
693	815	if (flags & ARW_SIGNED)
694		_movsx_r32_r16(REG_EAX, REG_AX); // movsx eax,ax
	816	emit_movsx_r32_r16(DRCTOP, REG_EAX, REG_AX); // movsx eax,ax
695	817	else
696		_movzx_r32_r16(REG_EAX, REG_AX); // movzx eax,ax
697		_add_r32_imm(REG_ESP, 12); // add esp,12
698		_ret(); // ret
	818	emit_movzx_r32_r16(DRCTOP, REG_EAX, REG_AX); // movzx eax,ax
	819	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	820	emit_ret(DRCTOP); // ret
699	821	}
700	822	else if (size == 4)
701	823	{
702		_mov_m32bd_r32(REG_ESP, 4, REG_EBX); // mov [esp+4],ebx
	824	emit_mov_m32_r32(DRCTOP, MBD(REG_ESP, 4), REG_EBX); // mov [esp+4],ebx
703	825	if (!(flags & ARW_MASKED))
704		_jmp(mips3.core->memory.readlong); // jmp readlong
	826	emit_jmp(DRCTOP, (x86code *)mips3.core->memory.readlong); // jmp readlong
705	827	else
706		_jmp(mips3.core->memory.readlong_masked); // jmp readlong_masked
	828	emit_jmp(DRCTOP, (x86code *)mips3.core->memory.readlong_masked); // jmp readlong_masked
707	829	}
708	830	else
709	831	{
710		_mov_m32bd_r32(REG_ESP, 4, REG_EBX); // mov [esp+4],ebx
	832	emit_mov_m32_r32(DRCTOP, MBD(REG_ESP, 4), REG_EBX); // mov [esp+4],ebx
711	833	if (!(flags & ARW_MASKED))
712		_jmp(mips3.core->memory.readdouble); // jmp readdouble
	834	emit_jmp(DRCTOP, (x86code *)mips3.core->memory.readdouble); // jmp readdouble
713	835	else
714		_jmp(mips3.core->memory.readdouble_masked); // jmp readdouble_masked
	836	emit_jmp(DRCTOP, (x86code *)mips3.core->memory.readdouble_masked); // jmp readdouble_masked
715	837	}
716	838	}
717	839	{
718	840	int valuebytes = (size == 8) ? 8 : 4;
719	841	int stackbytes = 4 + ((flags & ARW_WRITE) ? 4 + valuebytes : 4) + ((flags & ARW_MASKED) ? valuebytes : 0);
720		_resolve_link(&link1); // error:
721		_mov_r32_m32bd(REG_EAX, REG_ESP, 4); // mov eax,[esp+4]
722		_add_r32_imm(REG_ESP, stackbytes); // add esp,stack_bytes
723		_jmp((flags & ARW_WRITE) ? mips3.drcdata->generate_tlbstore_exception : mips3.drcdata->generate_tlbload_exception);// jmp generate_exception
	842	resolve_link(DRCTOP, &link1); // error:
	843	emit_mov_r32_m32(DRCTOP, REG_EAX, MBD(REG_ESP, 4)); // mov eax,[esp+4]
	844	emit_add_r32_imm(DRCTOP, REG_ESP, stackbytes); // add esp,stack_bytes
	845	emit_jmp(DRCTOP, (flags & ARW_WRITE) ? (x86code )mips3.drcdata->generate_tlbstore_exception : (x86code )mips3.drcdata->generate_tlbload_exception);
	846	// jmp generate_exception
724	847	}
725	848	}
726	849
r949	r950
734	857	/* addresses 0x80000000-0xbfffffff are direct-mapped; no checking needed */
735	858	if (pc < 0x80000000 \|\| pc >= 0xc0000000)
736	859	{
737		_cmp_m32abs_imm(&mips3.core->tlb_table[pc >> 12], mips3.core->tlb_table[pc >> 12]);// cmp tlbtable[pc >> 12],physpc & 0xfffff000
738		_jcc(COND_NE, target); // jne handle_pc_tlb_mismatch
	860	emit_cmp_m32_imm(DRCTOP, MABS(&mips3.core->tlb_table[pc >> 12]), mips3.core->tlb_table[pc >> 12]);
	861	// cmp tlbtable[pc >> 12],physpc & 0xfffff000
	862	emit_jcc(DRCTOP, COND_NE, target); // jne handle_pc_tlb_mismatch
739	863	}
740	864	}
741	865
r949	r950
746	870
747	871	static void append_update_cycle_counting(drc_core *drc)
748	872	{
749		_sub_r32_imm(REG_ESP, 8);
750		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
751		_push_imm(mips3.core); // sub esp,12
752		_call((genf *)mips3com_update_cycle_counting); // call update_cycle_counting
753		_add_r32_imm(REG_ESP, 12); // add esp,12
754		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	873	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
	874	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	875	emit_push_imm(DRCTOP, (FPTR)mips3.core); // push mips3.core
	876	emit_call(DRCTOP, (x86code *)mips3com_update_cycle_counting); // call update_cycle_counting
	877	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	878	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
755	879	}
756	880
757	881
r949	r950
761	885
762	886	static void append_check_interrupts(drc_core *drc, int inline_generate)
763	887	{
764		link_info link1, link2, link3;
765		_mov_r32_m32abs(REG_EAX, &mips3.core->cpr[0][COP0_Cause]); // mov eax,[mips3.core->cpr[0][COP0_Cause]]
766		_and_r32_m32abs(REG_EAX, &mips3.core->cpr[0][COP0_Status]); // and eax,[mips3.core->cpr[0][COP0_Status]]
767		_and_r32_imm(REG_EAX, 0xfc00); // and eax,0xfc00
	888	emit_link link1, link2, link3;
	889	emit_mov_r32_m32(DRCTOP, REG_EAX, CPR0ADDR(COP0_Cause)); // mov eax,[COP0_Cause]
	890	emit_and_r32_m32(DRCTOP, REG_EAX, CPR0ADDR(COP0_Status)); // and eax,[COP0_Status]
	891	emit_and_r32_imm(DRCTOP, REG_EAX, 0xfc00); // and eax,0xfc00
768	892	if (!inline_generate)
769		_jcc_short_link(COND_Z, &link1); // jz skip
	893	emit_jcc_short_link(DRCTOP, COND_Z, &link1); // jz skip
770	894	else
771		_jcc_near_link(COND_Z, &link1); // jz skip
772		_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_IE); // test [mips3.core->cpr[0][COP0_Status],SR_IE
	895	emit_jcc_near_link(DRCTOP, COND_Z, &link1); // jz skip
	896	emit_test_m32_imm(DRCTOP, CPR0ADDR(COP0_Status), SR_IE); // test [COP0_Status,SR_IE
773	897	if (!inline_generate)
774		_jcc_short_link(COND_Z, &link2); // jz skip
	898	emit_jcc_short_link(DRCTOP, COND_Z, &link2); // jz skip
775	899	else
776		_jcc_near_link(COND_Z, &link2); // jz skip
777		_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_EXL \| SR_ERL); // test [mips3.core->cpr[0][COP0_Status],SR_EXL \| SR_ERL
	900	emit_jcc_near_link(DRCTOP, COND_Z, &link2); // jz skip
	901	emit_test_m32_imm(DRCTOP, CPR0ADDR(COP0_Status), SR_EXL \| SR_ERL); // test [COP0_Status,SR_EXL \| SR_ERL
778	902	if (!inline_generate)
779		_jcc(COND_Z, mips3.drcdata->generate_interrupt_exception); // jz generate_interrupt_exception
	903	emit_jcc(DRCTOP, COND_Z, mips3.drcdata->generate_interrupt_exception); // jz generate_interrupt_exception
780	904	else
781	905	{
782		_jcc_near_link(COND_NZ, &link3); // jnz skip
783		append_generate_exception(drc, EXCEPTION_INTERRUPT); // <generate exception>
784		_resolve_link(&link3); // skip:
	906	emit_jcc_near_link(DRCTOP, COND_NZ, &link3); // jnz skip
	907	append_generate_exception(drc, EXCEPTION_INTERRUPT); // <generate exception>
	908	resolve_link(DRCTOP, &link3); // skip:
785	909	}
786		_resolve_link(&link1); // skip:
787		_resolve_link(&link2);
	910	resolve_link(DRCTOP, &link1); // skip:
	911	resolve_link(DRCTOP, &link2);
788	912	}
789	913
790	914
r949	r950
794	918
795	919	static void append_check_sw_interrupts(drc_core *drc, int inline_generate)
796	920	{
797		_test_m32abs_imm(&mips3.core->cpr[0][COP0_Cause], 0x300); // test [mips3.core->cpr[0][COP0_Cause]],0x300
798		_jcc(COND_NZ, mips3.drcdata->generate_interrupt_exception); // jnz generate_interrupt_exception
	921	emit_test_m32_imm(DRCTOP, CPR0ADDR(COP0_Cause), 0x300); // test [COP0_Cause],0x300
	922	emit_jcc(DRCTOP, COND_NZ, mips3.drcdata->generate_interrupt_exception); // jnz generate_interrupt_exception
799	923	}
800	924
801	925
r949	r950
806	930	static void append_branch_or_dispatch(drc_core *drc, UINT32 newpc, int cycles)
807	931	{
808	932	void *code = drc_get_code_at_pc(drc, newpc);
809		_mov_r32_imm(REG_EDI, newpc);
810		drc_append_standard_epilogue(drc, cycles, 0, 1);
	933	emit_mov_r32_imm(DRCTOP, REG_EDI, newpc); // mov edi,newpc
	934	drc_append_standard_epilogue(drc, cycles, 0, 1); // <epilogue>
811	935
812	936	if (code)
813		_jmp(code);
	937	emit_jmp(DRCTOP, code); // jmp code
814	938	else
815		drc_append_tentative_fixed_dispatcher(drc, newpc);
	939	drc_append_tentative_fixed_dispatcher(drc, newpc); // <dispatch>
816	940	}
817	941
818	942
819	943
820	944	/***************************************************************************
821		USEFUL PRIMITIVES
822		***************************************************************************/
823
824		#define REGDISP(reg) offsetof(mips3_state, r[reg]) - offsetof(mips3_state, r[17])
825
826		#define _zero_m64abs(addr) \
827		do { \
828		if (USE_SSE) \
829		{ \
830		_pxor_r128_r128(REG_XMM0, REG_XMM0); \
831		_movsd_m64abs_r128(addr, REG_XMM0); \
832		} \
833		else \
834		_mov_m64abs_imm32(addr, 0); \
835		} while (0) \
836
837		#define _zero_m64bd(base, disp) \
838		do { \
839		if (USE_SSE) \
840		{ \
841		_pxor_r128_r128(REG_XMM0, REG_XMM0); \
842		_movsd_m64bd_r128(base, disp, REG_XMM0); \
843		} \
844		else \
845		_mov_m64bd_imm32(base, disp, 0); \
846		} while (0) \
847
848		#define _mov_m64abs_m64abs(dst, src) \
849		do { \
850		if (USE_SSE) \
851		{ \
852		_movsd_r128_m64abs(REG_XMM0, src); \
853		_movsd_m64abs_r128(dst, REG_XMM0); \
854		} \
855		else \
856		{ \
857		_mov_r64_m64abs(REG_EDX, REG_EAX, src); \
858		_mov_m64abs_r64(dst, REG_EDX, REG_EAX); \
859		} \
860		} while (0) \
861
862		#define _mov_m64bd_m64bd(dstb, dstd, srcb, srcd) \
863		do { \
864		if (USE_SSE) \
865		{ \
866		_movsd_r128_m64bd(REG_XMM0, srcb, srcd); \
867		_movsd_m64bd_r128(dstb, dstd, REG_XMM0); \
868		} \
869		else \
870		{ \
871		_mov_r64_m64bd(REG_EDX, REG_EAX, srcb, srcd);\
872		_mov_m64bd_r64(dstb, dstd, REG_EDX, REG_EAX);\
873		} \
874		} while (0) \
875
876		#define _mov_m64bd_m64abs(dstb, dstd, src) \
877		do { \
878		if (USE_SSE) \
879		{ \
880		_movsd_r128_m64abs(REG_XMM0, src); \
881		_movsd_m64bd_r128(dstb, dstd, REG_XMM0); \
882		} \
883		else \
884		{ \
885		_mov_r64_m64abs(REG_EDX, REG_EAX, src); \
886		_mov_m64bd_r64(dstb, dstd, REG_EDX, REG_EAX);\
887		} \
888		} while (0) \
889
890		#define _mov_m64abs_m64bd(dst, srcb, srcd) \
891		do { \
892		if (USE_SSE) \
893		{ \
894		_movsd_r128_m64bd(REG_XMM0, srcb, srcd); \
895		_movsd_m64abs_r128(dst, REG_XMM0); \
896		} \
897		else \
898		{ \
899		_mov_r64_m64bd(REG_EDX, REG_EAX, srcb, srcd);\
900		_mov_m64abs_r64(dst, REG_EDX, REG_EAX); \
901		} \
902		} while (0) \
903
904		#define _save_pc_before_call() \
905		do { \
906		if (mips3.drcoptions & MIPS3DRC_FLUSH_PC) \
907		_mov_m32abs_r32(drc->pcptr, REG_EDI); \
908		} while (0)
909
910		#define FPR32(x) \
911		(IS_FR0 ? &((float *)&mips3.core->cpr[1][0])[x] :\
912		(float *)&mips3.core->cpr[1][x]) \
913
914		#define FPR64(x) \
915		(IS_FR0 ? (double *)&mips3.core->cpr[1][(x)/2] : \
916		(double *)&mips3.core->cpr[1][x]) \
917
918
919		/***************************************************************************
920	945	CORE RECOMPILATION
921	946	***************************************************************************/
922	947
r949	r950
953	978	if (Machine->debug_mode)
954	979	{
955	980	/* emit debugging */
956		_mov_r32_imm(REG_EDI, pc);
	981	emit_mov_r32_imm(DRCTOP, REG_EDI, pc);
957	982	drc_append_call_debugger(drc);
958	983	}
959	984	#endif
r949	r950
964	989	in_delay_slot = 1;
965	990	physpc = pc;
966	991	mips3com_translate_address(mips3.core, ADDRESS_SPACE_PROGRAM, &physpc);
967		result = recompile_instruction(drc, pc, physpc); // <next instruction>
	992	result = recompile_instruction(drc, pc, physpc); // <next instruction>
968	993	in_delay_slot = 0;
969	994
970	995	/* if the instruction can cause an exception, recompile setting nextpc */
971	996	if (result & RECOMPILE_MAY_CAUSE_EXCEPTION)
972	997	{
973	998	drc->cache_top = saved_top;
974		_mov_m32abs_imm(&mips3.nextpc, 0); // bogus nextpc for exceptions
975		result = recompile_instruction(drc, pc, physpc); // <next instruction>
976		_mov_m32abs_imm(&mips3.nextpc, ~0); // reset nextpc
	999	emit_mov_m32_imm(DRCTOP, MABS(&mips3.nextpc), 0); // bogus nextpc for exceptions
	1000	result = recompile_instruction(drc, pc, physpc); // <next instruction>
	1001	emit_mov_m32_imm(DRCTOP, MABS(&mips3.nextpc), ~0); // reset nextpc
977	1002	}
978	1003
979	1004	return (result >> 8) & 0xfff;
r949	r950
986	1011
987	1012	static UINT32 recompile_instruction(drc_core *drc, UINT32 pc, UINT32 physpc)
988	1013	{
989		link_info link1, link2 = { 0 }, link3;
	1014	emit_link link1, link2 = { 0 }, link3;
990	1015	UINT32 op = cpu_readop32(physpc);
991	1016	int cycles;
992	1017
r949	r950
1001	1026	return recompile_regimm(drc, pc, op);
1002	1027
1003	1028	case 0x02: /* J */
1004		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1005		append_branch_or_dispatch(drc, (pc & 0xf0000000) \| (LIMMVAL << 2), 1+cycles);// <branch or dispatch>
	1029	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1030	append_branch_or_dispatch(drc, (pc & 0xf0000000) \| (LIMMVAL << 2), 1+cycles); // <branch or dispatch>
1006	1031	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
1007	1032
1008	1033	case 0x03: /* JAL */
1009		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1010		_mov_m64bd_imm32(REG_ESI, REGDISP(31), pc + 8); // mov [31],pc + 8
1011		append_branch_or_dispatch(drc, (pc & 0xf0000000) \| (LIMMVAL << 2), 1+cycles);// <branch or dispatch>
	1034	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1035	emit_mov_m64_imm32(DRCTOP, REGADDR(31), pc + 8); // mov [31],pc + 8
	1036	append_branch_or_dispatch(drc, (pc & 0xf0000000) \| (LIMMVAL << 2), 1+cycles); // <branch or dispatch>
1012	1037	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
1013	1038
1014	1039	case 0x04: /* BEQ */
1015	1040	if (RSREG == RTREG)
1016	1041	{
1017		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1018		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1042	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1043	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1019	1044	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
1020	1045	}
1021	1046	else if (RSREG == 0)
1022	1047	{
1023		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg].lo
1024		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // or eax,[rtreg].hi
1025		_jcc_near_link(COND_NZ, &link1); // jnz skip
	1048	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	1049	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // or eax,[rtreg].hi
	1050	emit_jcc_near_link(DRCTOP, COND_NZ, &link1); // jnz skip
1026	1051	}
1027	1052	else if (RTREG == 0)
1028	1053	{
1029		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
1030		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // or eax,[rsreg].hi
1031		_jcc_near_link(COND_NZ, &link1); // jnz skip
	1054	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1055	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // or eax,[rsreg].hi
	1056	emit_jcc_near_link(DRCTOP, COND_NZ, &link1); // jnz skip
1032	1057	}
1033	1058	else
1034	1059	{
1035		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
1036		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
1037		_jcc_near_link(COND_NE, &link1); // jne skip
1038		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
1039		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // cmp eax,[rtreg].hi
1040		_jcc_near_link(COND_NE, &link2); // jne skip
	1060	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1061	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // cmp eax,[rtreg].lo
	1062	emit_jcc_near_link(DRCTOP, COND_NE, &link1); // jne skip
	1063	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	1064	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // cmp eax,[rtreg].hi
	1065	emit_jcc_near_link(DRCTOP, COND_NE, &link2); // jne skip
1041	1066	}
1042	1067
1043		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1044		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1045		_resolve_link(&link1); // skip:
	1068	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1069	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1070	resolve_link(DRCTOP, &link1); // skip:
1046	1071	if (RSREG != 0 && RTREG != 0)
1047		_resolve_link(&link2); // skip:
	1072	resolve_link(DRCTOP, &link2); // skip:
1048	1073	return RECOMPILE_SUCCESSFUL_CP(1,4);
1049	1074
1050	1075	case 0x05: /* BNE */
1051	1076	if (RSREG == 0)
1052	1077	{
1053		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg].lo
1054		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // or eax,[rtreg].hi
1055		_jcc_near_link(COND_Z, &link1); // jz skip
	1078	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	1079	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // or eax,[rtreg].hi
	1080	emit_jcc_near_link(DRCTOP, COND_Z, &link1); // jz skip
1056	1081	}
1057	1082	else if (RTREG == 0)
1058	1083	{
1059		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
1060		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // or eax,[rsreg].hi
1061		_jcc_near_link(COND_Z, &link1); // jz skip
	1084	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1085	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // or eax,[rsreg].hi
	1086	emit_jcc_near_link(DRCTOP, COND_Z, &link1); // jz skip
1062	1087	}
1063	1088	else
1064	1089	{
1065		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
1066		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
1067		_jcc_short_link(COND_NE, &link2); // jne takeit
1068		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
1069		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // cmp eax,[rtreg].hi
1070		_jcc_near_link(COND_E, &link1); // je skip
1071		_resolve_link(&link2); // takeit:
	1090	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1091	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // cmp eax,[rtreg].lo
	1092	emit_jcc_short_link(DRCTOP, COND_NE, &link2); // jne takeit
	1093	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	1094	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // cmp eax,[rtreg].hi
	1095	emit_jcc_near_link(DRCTOP, COND_E, &link1); // je skip
	1096	resolve_link(DRCTOP, &link2); // takeit:
1072	1097	}
1073	1098
1074		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1075		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1076		_resolve_link(&link1); // skip:
	1099	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1100	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1101	resolve_link(DRCTOP, &link1); // skip:
1077	1102	return RECOMPILE_SUCCESSFUL_CP(1,4);
1078	1103
1079	1104	case 0x06: /* BLEZ */
1080	1105	if (RSREG == 0)
1081	1106	{
1082		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1083		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1107	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1108	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1084	1109	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
1085	1110	}
1086	1111	else
1087	1112	{
1088		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
1089		_jcc_near_link(COND_G, &link1); // jg skip
1090		_jcc_short_link(COND_L, &link2); // jl takeit
1091		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), 0); // cmp [rsreg].lo,0
1092		_jcc_near_link(COND_NE, &link3); // jne skip
1093		_resolve_link(&link2); // takeit:
	1113	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	1114	emit_jcc_near_link(DRCTOP, COND_G, &link1); // jg skip
	1115	emit_jcc_short_link(DRCTOP, COND_L, &link2); // jl takeit
	1116	emit_cmp_m32_imm(DRCTOP, REGADDRLO(RSREG), 0); // cmp [rsreg].lo,0
	1117	emit_jcc_near_link(DRCTOP, COND_NE, &link3); // jne skip
	1118	resolve_link(DRCTOP, &link2); // takeit:
1094	1119	}
1095	1120
1096		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1097		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1098		_resolve_link(&link1); // skip:
1099		_resolve_link(&link3); // skip:
	1121	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1122	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1123	resolve_link(DRCTOP, &link1); // skip:
	1124	resolve_link(DRCTOP, &link3); // skip:
1100	1125	return RECOMPILE_SUCCESSFUL_CP(1,4);
1101	1126
1102	1127	case 0x07: /* BGTZ */
r949	r950
1104	1129	return RECOMPILE_SUCCESSFUL_CP(1,4);
1105	1130	else
1106	1131	{
1107		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
1108		_jcc_near_link(COND_L, &link1); // jl skip
1109		_jcc_short_link(COND_G, &link2); // jg takeit
1110		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), 0); // cmp [rsreg].lo,0
1111		_jcc_near_link(COND_E, &link3); // je skip
1112		_resolve_link(&link2); // takeit:
	1132	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	1133	emit_jcc_near_link(DRCTOP, COND_L, &link1); // jl skip
	1134	emit_jcc_short_link(DRCTOP, COND_G, &link2); // jg takeit
	1135	emit_cmp_m32_imm(DRCTOP, REGADDRLO(RSREG), 0); // cmp [rsreg].lo,0
	1136	emit_jcc_near_link(DRCTOP, COND_E, &link3); // je skip
	1137	resolve_link(DRCTOP, &link2); // takeit:
1113	1138	}
1114	1139
1115		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1116		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1117		_resolve_link(&link1); // skip:
1118		_resolve_link(&link3); // skip:
	1140	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1141	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1142	resolve_link(DRCTOP, &link1); // skip:
	1143	resolve_link(DRCTOP, &link3); // skip:
1119	1144	return RECOMPILE_SUCCESSFUL_CP(1,4);
1120	1145
1121	1146	case 0x08: /* ADDI */
1122	1147	if (RSREG != 0)
1123	1148	{
1124		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1125		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1126		_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
	1149	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1150	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1151	emit_jcc(DRCTOP, COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
1127	1152	if (RTREG != 0)
1128	1153	{
1129		_cdq(); // cdq
1130		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1154	emit_cdq(DRCTOP); // cdq
	1155	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1131	1156	}
1132	1157	}
1133	1158	else if (RTREG != 0)
1134		_mov_m64bd_imm32(R~~EG_ESI~~, REGD~~ISP~~(RTREG), SIMMVAL); // mov [rtreg],const
	1159	emit_mov_m64_imm32(DRCTOP, REGADDR(RTREG), SIMMVAL); // mov [rtreg],const
1135	1160	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
1136	1161
1137	1162	case 0x09: /* ADDIU */
r949	r950
1139	1164	{
1140	1165	if (RSREG != 0)
1141	1166	{
1142		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1143		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1144		_cdq(); // cdq
1145		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1167	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1168	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1169	emit_cdq(DRCTOP); // cdq
	1170	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1146	1171	}
1147	1172	else
1148		_mov_m64bd_imm32(R~~EG_ESI~~, REGD~~ISP~~(RTREG), SIMMVAL); // mov [rtreg],const
	1173	emit_mov_m64_imm32(DRCTOP, REGADDR(RTREG), SIMMVAL); // mov [rtreg],const
1149	1174	}
1150	1175	return RECOMPILE_SUCCESSFUL_CP(1,4);
1151	1176
r949	r950
1154	1179	{
1155	1180	if (RSREG != 0)
1156	1181	{
1157		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
1158		_sub_r32_imm(REG_EAX, SIMMVAL); // sub eax,[rtreg].lo
1159		_sbb_r32_imm(REG_EDX, ((INT32)SIMMVAL >> 31)); // sbb edx,[rtreg].lo
1160		_shr_r32_imm(REG_EDX, 31); // shr edx,31
1161		_mov_m32bd_r32(REG_ESI, REGDISP(RTREG), REG_EDX); // mov [rdreg].lo,edx
1162		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rdreg].hi,0
	1182	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	1183	emit_sub_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // sub eax,[rtreg].lo
	1184	emit_sbb_r32_imm(DRCTOP, REG_EDX, ((INT32)SIMMVAL >> 31)); // sbb edx,[rtreg].lo
	1185	emit_shr_r32_imm(DRCTOP, REG_EDX, 31); // shr edx,31
	1186	emit_mov_m32_r32(DRCTOP, REGADDRLO(RTREG), REG_EDX); // mov [rdreg].lo,edx
	1187	emit_mov_m32_imm(DRCTOP, REGADDRHI(RTREG), 0); // mov [rdreg].hi,0
1163	1188	}
1164	1189	else
1165	1190	{
1166		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG), (0 < SIMMVAL)); // mov [rtreg].lo,const
1167		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,sign-extend(const)
	1191	emit_mov_m32_imm(DRCTOP, REGADDRLO(RTREG), (0 < SIMMVAL)); // mov [rtreg].lo,const
	1192	emit_mov_m32_imm(DRCTOP, REGADDRHI(RTREG), 0); // mov [rtreg].hi,sign-extend(const)
1168	1193	}
1169	1194	}
1170	1195	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
1174	1199	{
1175	1200	if (RSREG != 0)
1176	1201	{
1177		_xor_r32_r32(REG_ECX, REG_ECX); // xor ecx,ecx
1178		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, ((INT32)SIMMVAL >> 31));// cmp [rsreg].hi,upper
1179		_jcc_short_link(COND_B, &link1); // jb takeit
1180		_jcc_short_link(COND_A, &link2); // ja skip
1181		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
1182		_jcc_short_link(COND_AE, &link3); // jae skip
1183		_resolve_link(&link1); // takeit:
1184		_add_r32_imm(REG_ECX, 1); // add ecx,1
1185		_resolve_link(&link2); // skip:
1186		_resolve_link(&link3); // skip:
1187		_mov_m32bd_r32(REG_ESI, REGDISP(RTREG), REG_ECX); // mov [rtreg].lo,ecx
1188		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,sign-extend(const)
	1202	emit_xor_r32_r32(DRCTOP, REG_ECX, REG_ECX); // xor ecx,ecx
	1203	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), ((INT32)SIMMVAL >> 31)); // cmp [rsreg].hi,upper
	1204	emit_jcc_short_link(DRCTOP, COND_B, &link1); // jb takeit
	1205	emit_jcc_short_link(DRCTOP, COND_A, &link2); // ja skip
	1206	emit_cmp_m32_imm(DRCTOP, REGADDRLO(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
	1207	emit_jcc_short_link(DRCTOP, COND_AE, &link3); // jae skip
	1208	resolve_link(DRCTOP, &link1); // takeit:
	1209	emit_add_r32_imm(DRCTOP, REG_ECX, 1); // add ecx,1
	1210	resolve_link(DRCTOP, &link2); // skip:
	1211	resolve_link(DRCTOP, &link3); // skip:
	1212	emit_mov_m32_r32(DRCTOP, REGADDRLO(RTREG), REG_ECX); // mov [rtreg].lo,ecx
	1213	emit_mov_m32_imm(DRCTOP, REGADDRHI(RTREG), 0); // mov [rtreg].hi,sign-extend(const)
1189	1214	}
1190	1215	else
1191	1216	{
1192		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG), (0 < SIMMVAL)); // mov [rtreg].lo,const
1193		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,sign-extend(const)
	1217	emit_mov_m32_imm(DRCTOP, REGADDRLO(RTREG), (0 < SIMMVAL)); // mov [rtreg].lo,const
	1218	emit_mov_m32_imm(DRCTOP, REGADDRHI(RTREG), 0); // mov [rtreg].hi,sign-extend(const)
1194	1219	}
1195	1220	}
1196	1221	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
1200	1225	{
1201	1226	if (RSREG == RTREG)
1202	1227	{
1203		_and_m32bd_imm(REG_ESI, REGDISP(RTREG), UIMMVAL); // and [rtreg],UIMMVAL
1204		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,0
	1228	emit_and_m32_imm(DRCTOP, REGADDRLO(RTREG), UIMMVAL); // and [rtreg],UIMMVAL
	1229	emit_mov_m32_imm(DRCTOP, REGADDRHI(RTREG), 0); // mov [rtreg].hi,0
1205	1230	}
1206	1231	else if (RSREG != 0)
1207	1232	{
1208		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
1209		_and_r32_imm(REG_EAX, UIMMVAL); // and eax,UIMMVAL
1210		_mov_m32bd_r32(REG_ESI, REGDISP(RTREG), REG_EAX); // mov [rtreg].lo,eax
1211		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,0
	1233	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1234	emit_and_r32_imm(DRCTOP, REG_EAX, UIMMVAL); // and eax,UIMMVAL
	1235	emit_mov_m32_r32(DRCTOP, REGADDRLO(RTREG), REG_EAX); // mov [rtreg].lo,eax
	1236	emit_mov_m32_imm(DRCTOP, REGADDRHI(RTREG), 0); // mov [rtreg].hi,0
1212	1237	}
1213	1238	else
1214		_mov_m64bd_imm32(R~~EG_ESI~~, REGD~~ISP~~(RTREG), 0); // mov [rtreg],0
	1239	emit_mov_m64_imm32(DRCTOP, REGADDR(RTREG), 0); // mov [rtreg],0
1215	1240	}
1216	1241	return RECOMPILE_SUCCESSFUL_CP(1,4);
1217	1242
r949	r950
1219	1244	if (RTREG != 0)
1220	1245	{
1221	1246	if (RSREG == RTREG)
1222		_or_m32bd_imm(R~~EG_ESI~~, REGD~~ISP~~(RTREG), UIMMVAL); // or [rtreg],UIMMVAL
	1247	emit_or_m32_imm(DRCTOP, REGADDRLO(RTREG), UIMMVAL); // or [rtreg].lo,UIMMVAL
1223	1248	else if (RSREG != 0)
1224	1249	{
1225		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
1226		_or_r32_imm(REG_EAX, UIMMVAL); // or eax,UIMMVAL
1227		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1250	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	1251	emit_or_r32_imm(DRCTOP, REG_EAX, UIMMVAL); // or eax,UIMMVAL
	1252	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1228	1253	}
1229	1254	else
1230		_mov_m64bd_imm32(R~~EG_ESI~~, REGD~~ISP~~(RTREG), UIMMVAL); // mov [rtreg],const
	1255	emit_mov_m64_imm32(DRCTOP, REGADDR(RTREG), UIMMVAL); // mov [rtreg],const
1231	1256	}
1232	1257	return RECOMPILE_SUCCESSFUL_CP(1,4);
1233	1258
r949	r950
1235	1260	if (RTREG != 0)
1236	1261	{
1237	1262	if (RSREG == RTREG)
1238		_xor_m32bd_imm(R~~EG_ESI~~, REGD~~ISP~~(RTREG), UIMMVAL); // xor [rtreg],UIMMVAL
	1263	emit_xor_m32_imm(DRCTOP, REGADDRLO(RTREG), UIMMVAL); // xor [rtreg].lo,UIMMVAL
1239	1264	else if (RSREG != 0)
1240	1265	{
1241		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
1242		_xor_r32_imm(REG_EAX, UIMMVAL); // xor eax,UIMMVAL
1243		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1266	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	1267	emit_xor_r32_imm(DRCTOP, REG_EAX, UIMMVAL); // xor eax,UIMMVAL
	1268	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1244	1269	}
1245	1270	else
1246		_mov_m64bd_imm32(R~~EG_ESI~~, REGD~~ISP~~(RTREG), UIMMVAL); // mov [rtreg],const
	1271	emit_mov_m64_imm32(DRCTOP, REGADDR(RTREG), UIMMVAL); // mov [rtreg],const
1247	1272	}
1248	1273	return RECOMPILE_SUCCESSFUL_CP(1,4);
1249	1274
1250	1275	case 0x0f: /* LUI */
1251	1276	if (RTREG != 0)
1252		_mov_m64bd_imm32(R~~EG_ESI~~, REGD~~ISP~~(RTREG), UIMMVAL << 16); // mov [rtreg],const << 16
	1277	emit_mov_m64_imm32(DRCTOP, REGADDR(RTREG), UIMMVAL << 16); // mov [rtreg],const << 16
1253	1278	return RECOMPILE_SUCCESSFUL_CP(1,4);
1254	1279
1255	1280	case 0x10: /* COP0 */
r949	r950
1259	1284	return recompile_cop1(drc, pc, op) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
1260	1285
1261	1286	case 0x12: /* COP2 */
1262		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	1287	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
1263	1288	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
1264	1289
1265	1290	case 0x13: /* COP1X - R5000 */
1266	1291	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
1267	1292	{
1268		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	1293	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
1269	1294	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
1270	1295	}
1271	1296	return recompile_cop1x(drc, pc, op) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
r949	r950
1273	1298	case 0x14: /* BEQL */
1274	1299	if (RSREG == RTREG)
1275	1300	{
1276		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1277		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1301	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1302	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1278	1303	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
1279	1304	}
1280	1305	else if (RSREG == 0)
1281	1306	{
1282		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg].lo
1283		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // or eax,[rtreg].hi
1284		_jcc_near_link(COND_NZ, &link1); // jnz skip
	1307	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	1308	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // or eax,[rtreg].hi
	1309	emit_jcc_near_link(DRCTOP, COND_NZ, &link1); // jnz skip
1285	1310	}
1286	1311	else if (RTREG == 0)
1287	1312	{
1288		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
1289		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // or eax,[rsreg].hi
1290		_jcc_near_link(COND_NZ, &link1); // jnz skip
	1313	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1314	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // or eax,[rsreg].hi
	1315	emit_jcc_near_link(DRCTOP, COND_NZ, &link1); // jnz skip
1291	1316	}
1292	1317	else
1293	1318	{
1294		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
1295		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
1296		_jcc_near_link(COND_NE, &link1); // jne skip
1297		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
1298		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // cmp eax,[rtreg].hi
1299		_jcc_near_link(COND_NE, &link2); // jne skip
	1319	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1320	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // cmp eax,[rtreg].lo
	1321	emit_jcc_near_link(DRCTOP, COND_NE, &link1); // jne skip
	1322	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	1323	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // cmp eax,[rtreg].hi
	1324	emit_jcc_near_link(DRCTOP, COND_NE, &link2); // jne skip
1300	1325	}
1301	1326
1302		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1303		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1304		_resolve_link(&link1); // skip:
	1327	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1328	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1329	resolve_link(DRCTOP, &link1); // skip:
1305	1330	if (RSREG != 0 && RTREG != 0)
1306		_resolve_link(&link2); // skip:
	1331	resolve_link(DRCTOP, &link2); // skip:
1307	1332	return RECOMPILE_SUCCESSFUL_CP(1,8);
1308	1333
1309	1334	case 0x15: /* BNEL */
1310	1335	if (RSREG == 0)
1311	1336	{
1312		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg].lo
1313		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // or eax,[rtreg].hi
1314		_jcc_near_link(COND_Z, &link1); // jz skip
	1337	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	1338	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // or eax,[rtreg].hi
	1339	emit_jcc_near_link(DRCTOP, COND_Z, &link1); // jz skip
1315	1340	}
1316	1341	else if (RTREG == 0)
1317	1342	{
1318		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
1319		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // or eax,[rsreg].hi
1320		_jcc_near_link(COND_Z, &link1); // jz skip
	1343	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1344	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // or eax,[rsreg].hi
	1345	emit_jcc_near_link(DRCTOP, COND_Z, &link1); // jz skip
1321	1346	}
1322	1347	else
1323	1348	{
1324		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
1325		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
1326		_jcc_short_link(COND_NE, &link2); // jne takeit
1327		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
1328		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // cmp eax,[rtreg].hi
1329		_jcc_near_link(COND_E, &link1); // je skip
1330		_resolve_link(&link2); // takeit:
	1349	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1350	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // cmp eax,[rtreg].lo
	1351	emit_jcc_short_link(DRCTOP, COND_NE, &link2); // jne takeit
	1352	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	1353	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // cmp eax,[rtreg].hi
	1354	emit_jcc_near_link(DRCTOP, COND_E, &link1); // je skip
	1355	resolve_link(DRCTOP, &link2); // takeit:
1331	1356	}
1332	1357
1333		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1334		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1335		_resolve_link(&link1); // skip:
	1358	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1359	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1360	resolve_link(DRCTOP, &link1); // skip:
1336	1361	return RECOMPILE_SUCCESSFUL_CP(1,8);
1337	1362
1338	1363	case 0x16: /* BLEZL */
1339	1364	if (RSREG == 0)
1340	1365	{
1341		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1342		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1366	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1367	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1343	1368	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
1344	1369	}
1345	1370	else
1346	1371	{
1347		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
1348		_jcc_near_link(COND_G, &link1); // jg skip
1349		_jcc_short_link(COND_L, &link2); // jl takeit
1350		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), 0); // cmp [rsreg].lo,0
1351		_jcc_near_link(COND_NE, &link3); // jne skip
1352		_resolve_link(&link2); // takeit:
	1372	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	1373	emit_jcc_near_link(DRCTOP, COND_G, &link1); // jg skip
	1374	emit_jcc_short_link(DRCTOP, COND_L, &link2); // jl takeit
	1375	emit_cmp_m32_imm(DRCTOP, REGADDRLO(RSREG), 0); // cmp [rsreg].lo,0
	1376	emit_jcc_near_link(DRCTOP, COND_NE, &link3); // jne skip
	1377	resolve_link(DRCTOP, &link2); // takeit:
1353	1378	}
1354	1379
1355		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1356		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1357		_resolve_link(&link1); // skip:
1358		_resolve_link(&link3); // skip:
	1380	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1381	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1382	resolve_link(DRCTOP, &link1); // skip:
	1383	resolve_link(DRCTOP, &link3); // skip:
1359	1384	return RECOMPILE_SUCCESSFUL_CP(1,8);
1360	1385
1361	1386	case 0x17: /* BGTZL */
r949	r950
1363	1388	return RECOMPILE_SUCCESSFUL_CP(1,8);
1364	1389	else
1365	1390	{
1366		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
1367		_jcc_near_link(COND_L, &link1); // jl skip
1368		_jcc_short_link(COND_G, &link2); // jg takeit
1369		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), 0); // cmp [rsreg].lo,0
1370		_jcc_near_link(COND_E, &link3); // je skip
1371		_resolve_link(&link2); // takeit:
	1391	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	1392	emit_jcc_near_link(DRCTOP, COND_L, &link1); // jl skip
	1393	emit_jcc_short_link(DRCTOP, COND_G, &link2); // jg takeit
	1394	emit_cmp_m32_imm(DRCTOP, REGADDRLO(RSREG), 0); // cmp [rsreg].lo,0
	1395	emit_jcc_near_link(DRCTOP, COND_E, &link3); // je skip
	1396	resolve_link(DRCTOP, &link2); // takeit:
1372	1397	}
1373	1398
1374		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
1375		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
1376		_resolve_link(&link1); // skip:
1377		_resolve_link(&link3); // skip:
	1399	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	1400	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	1401	resolve_link(DRCTOP, &link1); // skip:
	1402	resolve_link(DRCTOP, &link3); // skip:
1378	1403	return RECOMPILE_SUCCESSFUL_CP(1,8);
1379	1404
1380	1405	case 0x18: /* DADDI */
1381	1406	if (RSREG != 0)
1382	1407	{
1383		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
1384		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1385		_adc_r32_imm(REG_EDX, (SIMMVAL < 0) ? -1 : 0); // adc edx,signext(SIMMVAL)
1386		_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
	1408	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	1409	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1410	emit_adc_r32_imm(DRCTOP, REG_EDX, (SIMMVAL < 0) ? -1 : 0); // adc edx,signext(SIMMVAL)
	1411	emit_jcc(DRCTOP, COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
1387	1412	if (RTREG != 0)
1388		_mov_m64bd_r64(R~~EG_ESI~~, REGD~~ISP~~(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1413	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1389	1414	}
1390	1415	else if (RTREG != 0)
1391		_mov_m64bd_imm32(R~~EG_ESI~~, REGD~~ISP~~(RTREG), SIMMVAL); // mov [rtreg],const
	1416	emit_mov_m64_imm32(DRCTOP, REGADDR(RTREG), SIMMVAL); // mov [rtreg],const
1392	1417	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
1393	1418
1394	1419	case 0x19: /* DADDIU */
r949	r950
1396	1421	{
1397	1422	if (RSREG != 0)
1398	1423	{
1399		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
1400		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1401		_adc_r32_imm(REG_EDX, (SIMMVAL < 0) ? -1 : 0); // adc edx,signext(SIMMVAL)
1402		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1424	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	1425	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1426	emit_adc_r32_imm(DRCTOP, REG_EDX, (SIMMVAL < 0) ? -1 : 0); // adc edx,signext(SIMMVAL)
	1427	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1403	1428	}
1404	1429	else
1405		_mov_m64bd_imm32(R~~EG_ESI~~, REGD~~ISP~~(RTREG), SIMMVAL); // mov [rtreg],const
	1430	emit_mov_m64_imm32(DRCTOP, REGADDR(RTREG), SIMMVAL); // mov [rtreg],const
1406	1431	}
1407	1432	return RECOMPILE_SUCCESSFUL_CP(1,4);
1408	1433
1409	1434	case 0x1a: /* LDL */
1410		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1411		_save_pc_before_call(); // save pc
1412		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
	1435	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1436	emit_save_pc_before_call(DRCTOP); // save pc
	1437	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
1413	1438	if (SIMMVAL)
1414		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1415		_lea_r32_m32isd(REG_ECX, REG_EAX, 4, 0); // lea ecx,[eax*4]
1416		_and_r32_imm(REG_EAX, ~7); // and eax,~7
1417		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
1418		_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
	1439	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1440	emit_lea_r32_m32(DRCTOP, REG_ECX, MISD(REG_EAX, 4, 0)); // lea ecx,[eax*4]
	1441	emit_and_r32_imm(DRCTOP, REG_EAX, ~7); // and eax,~7
	1442	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
	1443	emit_mov_r32_imm(DRCTOP, REG_EBP, -1); // mov ebp,-1
1419	1444	if (!mips3.core->bigendian)
1420		_xor_r32_imm(REG_ECX, 0x1c); // xor ecx,0x1c
1421		_shr_r32_cl(REG_EBP); // shr ebp,cl
1422		_shrd_r32_r32_cl(REG_EBX, REG_EBP); // shrd ebx,ebp,cl
1423		_shr_r32_cl(REG_EBP); // shr ebp,cl
1424		_not_r32(REG_EBX); // not ebx
1425		_not_r32(REG_EBP); // not ebp
1426		_push_r32(REG_ECX); // push ecx
1427		_push_r32(REG_EBP); // push ebp
1428		_push_r32(REG_EBX); // push ebx
1429		_push_r32(REG_EAX); // push eax
1430		_call((genf *)mips3.drcdata->read_and_translate_double_masked); // call read_and_translate_double_masked
1431		_add_r32_imm(REG_ESP, 12); // add esp,12
1432		_pop_r32(REG_ECX); // pop ecx
	1445	emit_xor_r32_imm(DRCTOP, REG_ECX, 0x1c); // xor ecx,0x1c
	1446	emit_shr_r32_cl(DRCTOP, REG_EBP); // shr ebp,cl
	1447	emit_shrd_r32_r32_cl(DRCTOP, REG_EBX, REG_EBP); // shrd ebx,ebp,cl
	1448	emit_shr_r32_cl(DRCTOP, REG_EBP); // shr ebp,cl
	1449	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1450	emit_not_r32(DRCTOP, REG_EBP); // not ebp
	1451	emit_push_r32(DRCTOP, REG_ECX); // push ecx
	1452	emit_push_r32(DRCTOP, REG_EBP); // push ebp
	1453	emit_push_r32(DRCTOP, REG_EBX); // push ebx
	1454	emit_push_r32(DRCTOP, REG_EAX); // push eax
	1455	emit_call(DRCTOP, mips3.drcdata->read_and_translate_double_masked); // call read_and_translate_double_masked
	1456	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	1457	emit_pop_r32(DRCTOP, REG_ECX); // pop ecx
1433	1458
1434	1459	if (RTREG != 0)
1435	1460	{
1436		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
1437		_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
1438		_shl_r32_cl(REG_EBX); // shl ebx,cl
1439		_shld_r32_r32_cl(REG_EBP, REG_EBX); // shld ebp,ebx,cl
1440		_shl_r32_cl(REG_EBX); // shl ebx,cl
1441		_not_r32(REG_EBX); // not ebx
1442		_not_r32(REG_EBP); // not ebp
1443		_shld_r32_r32_cl(REG_EDX, REG_EAX); // shld edx,eax,cl
1444		_shl_r32_cl(REG_EAX); // shl eax,cl
1445		_shld_r32_r32_cl(REG_EDX, REG_EAX); // shld edx,eax,cl
1446		_shl_r32_cl(REG_EAX); // shl eax,cl
1447		_and_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // and ebx,[rtreg].lo
1448		_and_r32_m32bd(REG_EBP, REG_ESI, REGDISP(RTREG)+4); // and ebp,[rtreg].hi
1449		_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
1450		_or_r32_r32(REG_EDX, REG_EBP); // or edx,ebp
1451		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1461	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
	1462	emit_mov_r32_imm(DRCTOP, REG_EBP, -1); // mov ebp,-1
	1463	emit_shl_r32_cl(DRCTOP, REG_EBX); // shl ebx,cl
	1464	emit_shld_r32_r32_cl(DRCTOP, REG_EBP, REG_EBX); // shld ebp,ebx,cl
	1465	emit_shl_r32_cl(DRCTOP, REG_EBX); // shl ebx,cl
	1466	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1467	emit_not_r32(DRCTOP, REG_EBP); // not ebp
	1468	emit_shld_r32_r32_cl(DRCTOP, REG_EDX, REG_EAX); // shld edx,eax,cl
	1469	emit_shl_r32_cl(DRCTOP, REG_EAX); // shl eax,cl
	1470	emit_shld_r32_r32_cl(DRCTOP, REG_EDX, REG_EAX); // shld edx,eax,cl
	1471	emit_shl_r32_cl(DRCTOP, REG_EAX); // shl eax,cl
	1472	emit_and_r32_m32(DRCTOP, REG_EBX, REGADDRLO(RTREG)); // and ebx,[rtreg].lo
	1473	emit_and_r32_m32(DRCTOP, REG_EBP, REGADDRHI(RTREG)); // and ebp,[rtreg].hi
	1474	emit_or_r32_r32(DRCTOP, REG_EAX, REG_EBX); // or eax,ebx
	1475	emit_or_r32_r32(DRCTOP, REG_EDX, REG_EBP); // or edx,ebp
	1476	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1452	1477	}
1453		_mov_r32_m32~~abs~~(REG_EBP, ~~&mips3.core->icount~~); // mov ebp,[~~mips3.core->~~icount]
	1478	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1454	1479	return RECOMPILE_SUCCESSFUL_CP(1,4);
1455	1480
1456	1481	case 0x1b: /* LDR */
1457		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1458		_save_pc_before_call(); // save pc
1459		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
	1482	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1483	emit_save_pc_before_call(DRCTOP); // save pc
	1484	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
1460	1485	if (SIMMVAL)
1461		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1462		_lea_r32_m32isd(REG_ECX, REG_EAX, 4, 0); // lea ecx,[eax*4]
1463		_and_r32_imm(REG_EAX, ~7); // and eax,~7
1464		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
1465		_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
	1486	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1487	emit_lea_r32_m32(DRCTOP, REG_ECX, MISD(REG_EAX, 4, 0)); // lea ecx,[eax*4]
	1488	emit_and_r32_imm(DRCTOP, REG_EAX, ~7); // and eax,~7
	1489	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
	1490	emit_mov_r32_imm(DRCTOP, REG_EBP, -1); // mov ebp,-1
1466	1491	if (mips3.core->bigendian)
1467		_xor_r32_imm(REG_ECX, 0x1c); // xor ecx,0x1c
1468		_shl_r32_cl(REG_EBX); // shl ebx,cl
1469		_shld_r32_r32_cl(REG_EBP, REG_EBX); // shld ebp,ebx,cl
1470		_shl_r32_cl(REG_EBX); // shl ebx,cl
1471		_not_r32(REG_EBX); // not ebx
1472		_not_r32(REG_EBP); // not ebp
1473		_push_r32(REG_ECX); // push ecx
1474		_push_r32(REG_EBP); // push ebp
1475		_push_r32(REG_EBX); // push ebx
1476		_push_r32(REG_EAX); // push eax
1477		_call((genf *)mips3.drcdata->read_and_translate_double_masked); // call read_and_translate_double_masked
1478		_add_r32_imm(REG_ESP, 12); // add esp,12
1479		_pop_r32(REG_ECX); // pop ecx
	1492	emit_xor_r32_imm(DRCTOP, REG_ECX, 0x1c); // xor ecx,0x1c
	1493	emit_shl_r32_cl(DRCTOP, REG_EBX); // shl ebx,cl
	1494	emit_shld_r32_r32_cl(DRCTOP, REG_EBP, REG_EBX); // shld ebp,ebx,cl
	1495	emit_shl_r32_cl(DRCTOP, REG_EBX); // shl ebx,cl
	1496	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1497	emit_not_r32(DRCTOP, REG_EBP); // not ebp
	1498	emit_push_r32(DRCTOP, REG_ECX); // push ecx
	1499	emit_push_r32(DRCTOP, REG_EBP); // push ebp
	1500	emit_push_r32(DRCTOP, REG_EBX); // push ebx
	1501	emit_push_r32(DRCTOP, REG_EAX); // push eax
	1502	emit_call(DRCTOP, mips3.drcdata->read_and_translate_double_masked); // call read_and_translate_double_masked
	1503	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	1504	emit_pop_r32(DRCTOP, REG_ECX); // pop ecx
1480	1505
1481	1506	if (RTREG != 0)
1482	1507	{
1483		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
1484		_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
1485		_shr_r32_cl(REG_EBP); // shr ebp,cl
1486		_shrd_r32_r32_cl(REG_EBX, REG_EBP); // shrd ebx,ebp,cl
1487		_shr_r32_cl(REG_EBP); // shr ebp,cl
1488		_not_r32(REG_EBX); // not ebx
1489		_not_r32(REG_EBP); // not ebp
1490		_shrd_r32_r32_cl(REG_EAX, REG_EDX); // shld eax,edx,cl
1491		_shr_r32_cl(REG_EDX); // shl edx,cl
1492		_shrd_r32_r32_cl(REG_EAX, REG_EDX); // shld eax,edx,cl
1493		_shr_r32_cl(REG_EDX); // shl edx,cl
1494		_and_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // and ebx,[rtreg].lo
1495		_and_r32_m32bd(REG_EBP, REG_ESI, REGDISP(RTREG)+4); // and ebp,[rtreg].hi
1496		_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
1497		_or_r32_r32(REG_EDX, REG_EBP); // or edx,ebp
1498		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1508	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
	1509	emit_mov_r32_imm(DRCTOP, REG_EBP, -1); // mov ebp,-1
	1510	emit_shr_r32_cl(DRCTOP, REG_EBP); // shr ebp,cl
	1511	emit_shrd_r32_r32_cl(DRCTOP, REG_EBX, REG_EBP); // shrd ebx,ebp,cl
	1512	emit_shr_r32_cl(DRCTOP, REG_EBP); // shr ebp,cl
	1513	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1514	emit_not_r32(DRCTOP, REG_EBP); // not ebp
	1515	emit_shrd_r32_r32_cl(DRCTOP, REG_EAX, REG_EDX); // shld eax,edx,cl
	1516	emit_shr_r32_cl(DRCTOP, REG_EDX); // shl edx,cl
	1517	emit_shrd_r32_r32_cl(DRCTOP, REG_EAX, REG_EDX); // shld eax,edx,cl
	1518	emit_shr_r32_cl(DRCTOP, REG_EDX); // shl edx,cl
	1519	emit_and_r32_m32(DRCTOP, REG_EBX, REGADDRLO(RTREG)); // and ebx,[rtreg].lo
	1520	emit_and_r32_m32(DRCTOP, REG_EBP, REGADDRHI(RTREG)); // and ebp,[rtreg].hi
	1521	emit_or_r32_r32(DRCTOP, REG_EAX, REG_EBX); // or eax,ebx
	1522	emit_or_r32_r32(DRCTOP, REG_EDX, REG_EBP); // or edx,ebp
	1523	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1499	1524	}
1500		_mov_r32_m32~~abs~~(REG_EBP, ~~&mips3.core->icount~~); // mov ebp,[~~mips3.core->~~icount]
	1525	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1501	1526	return RECOMPILE_SUCCESSFUL_CP(1,4);
1502	1527
1503	1528	case 0x1c: /* IDT-specific opcodes: mad/madu/mul on R4640/4650, msub on RC32364 */
r949	r950
1506	1531	case 0: /* MAD */
1507	1532	if (RSREG != 0 && RTREG != 0)
1508	1533	{
1509		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1510		_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)); // mov edx,[rtreg]
1511		_imul_r32(REG_EDX); // imul edx
1512		_add_r32_m32abs(REG_EAX, &mips3.core->lo); // add eax,[lo]
1513		_adc_r32_m32abs(REG_EDX, &mips3.core->hi); // adc edx,[hi]
1514		_mov_r32_r32(REG_EBX, REG_EDX); // mov ebx,edx
1515		_cdq(); // cdq
1516		_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
1517		_mov_r32_r32(REG_EAX, REG_EBX); // mov eax,ebx
1518		_cdq(); // cdq
1519		_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
	1534	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg]
	1535	emit_mov_r32_m32(DRCTOP, REG_EDX, REGADDRLO(RTREG)); // mov edx,[rtreg]
	1536	emit_imul_r32(DRCTOP, REG_EDX); // imul edx
	1537	emit_add_r32_m32(DRCTOP, REG_EAX, LOADDRLO); // add eax,[lo]
	1538	emit_adc_r32_m32(DRCTOP, REG_EDX, HIADDRLO); // adc edx,[hi]
	1539	emit_mov_r32_r32(DRCTOP, REG_EBX, REG_EDX); // mov ebx,edx
	1540	emit_cdq(DRCTOP); // cdq
	1541	emit_mov_m64_r64(DRCTOP, LOADDR, REG_EDX, REG_EAX); // mov [lo],edx:eax
	1542	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_EBX); // mov eax,ebx
	1543	emit_cdq(DRCTOP); // cdq
	1544	emit_mov_m64_r64(DRCTOP, HIADDR, REG_EDX, REG_EAX); // mov [hi],edx:eax
1520	1545	}
1521	1546	return RECOMPILE_SUCCESSFUL_CP(3,4);
1522	1547
1523	1548	case 1: /* MADU */
1524	1549	if (RSREG != 0 && RTREG != 0)
1525	1550	{
1526		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1527		_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)); // mov edx,[rtreg]
1528		_mul_r32(REG_EDX); // mul edx
1529		_add_r32_m32abs(REG_EAX, &mips3.core->lo); // add eax,[lo]
1530		_adc_r32_m32abs(REG_EDX, &mips3.core->hi); // adc edx,[hi]
1531		_mov_r32_r32(REG_EBX, REG_EDX); // mov ebx,edx
1532		_cdq(); // cdq
1533		_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
1534		_mov_r32_r32(REG_EAX, REG_EBX); // mov eax,ebx
1535		_cdq(); // cdq
1536		_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
	1551	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg]
	1552	emit_mov_r32_m32(DRCTOP, REG_EDX, REGADDRLO(RTREG)); // mov edx,[rtreg]
	1553	emit_mul_r32(DRCTOP, REG_EDX); // mul edx
	1554	emit_add_r32_m32(DRCTOP, REG_EAX, LOADDRLO); // add eax,[lo]
	1555	emit_adc_r32_m32(DRCTOP, REG_EDX, HIADDRLO); // adc edx,[hi]
	1556	emit_mov_r32_r32(DRCTOP, REG_EBX, REG_EDX); // mov ebx,edx
	1557	emit_cdq(DRCTOP); // cdq
	1558	emit_mov_m64_r64(DRCTOP, LOADDR, REG_EDX, REG_EAX); // mov [lo],edx:eax
	1559	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_EBX); // mov eax,ebx
	1560	emit_cdq(DRCTOP); // cdq
	1561	emit_mov_m64_r64(DRCTOP, HIADDR, REG_EDX, REG_EAX); // mov [hi],edx:eax
1537	1562	}
1538	1563	return RECOMPILE_SUCCESSFUL_CP(3,4);
1539	1564
r949	r950
1542	1567	{
1543	1568	if (RSREG != 0 && RTREG != 0)
1544	1569	{
1545		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1546		_imul_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // imul eax,[rtreg]
1547		_cdq(); // cdq
1548		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX);// mov [rdreg],edx:eax
	1570	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1571	emit_imul_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // imul eax,[rtreg].lo
	1572	emit_cdq(DRCTOP); // cdq
	1573	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
1549	1574	}
1550	1575	else
1551		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	1576	emit_zero_m64(DRCTOP, REGADDR(RDREG)); // mov [rdreg],0
1552	1577	}
1553	1578	return RECOMPILE_SUCCESSFUL_CP(3,4);
1554	1579	}
1555	1580	break;
1556	1581
1557	1582	case 0x20: /* LB */
1558		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1559		_save_pc_before_call(); // save pc
1560		_sub_r32_imm(REG_ESP, 8); // sub esp,8
	1583	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1584	emit_save_pc_before_call(DRCTOP); // save pc
	1585	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
1561	1586	if (RSREG != 0 && SIMMVAL != 0)
1562	1587	{
1563		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1564		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1565		_push_r32(REG_EAX); // push eax
	1588	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1589	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1590	emit_push_r32(DRCTOP, REG_EAX); // push eax
1566	1591	}
1567	1592	else if (RSREG != 0)
1568		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	1593	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
1569	1594	else
1570		_push_imm(SIMMVAL); // push SIMMVAL
1571		_call(mips3.drcdata->read_and_translate_byte_signed); // call read_and_translate_byte_signed
1572		_add_r32_imm(REG_ESP, 12); // add esp,12
	1595	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	1596	emit_call(DRCTOP, mips3.drcdata->read_and_translate_byte_signed); // call read_and_translate_byte_signed
	1597	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
1573	1598	if (RTREG != 0)
1574	1599	{
1575		_cdq(); // cdq
1576		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1600	emit_cdq(DRCTOP); // cdq
	1601	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1577	1602	}
1578		_mov_r32_m32~~abs~~(REG_EBP, ~~&mips3.core->icount~~); // mov ebp,[~~mips3.core->~~icount]
	1603	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1579	1604	return RECOMPILE_SUCCESSFUL_CP(1,4);
1580	1605
1581	1606	case 0x21: /* LH */
1582		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1583		_save_pc_before_call(); // save pc
1584		_sub_r32_imm(REG_ESP, 8); // sub esp,8
	1607	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1608	emit_save_pc_before_call(DRCTOP); // save pc
	1609	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
1585	1610	if (RSREG != 0 && SIMMVAL != 0)
1586	1611	{
1587		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1588		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1589		_push_r32(REG_EAX); // push eax
	1612	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1613	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1614	emit_push_r32(DRCTOP, REG_EAX); // push eax
1590	1615	}
1591	1616	else if (RSREG != 0)
1592		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	1617	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
1593	1618	else
1594		_push_imm(SIMMVAL); // push SIMMVAL
1595		_call(mips3.drcdata->read_and_translate_word_signed); // call read_and_translate_word_signed
1596		_add_r32_imm(REG_ESP, 12); // add esp,12
	1619	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	1620	emit_call(DRCTOP, mips3.drcdata->read_and_translate_word_signed); // call read_and_translate_word_signed
	1621	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
1597	1622	if (RTREG != 0)
1598	1623	{
1599		_cdq(); // cdq
1600		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1624	emit_cdq(DRCTOP); // cdq
	1625	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1601	1626	}
1602		_mov_r32_m32~~abs~~(REG_EBP, ~~&mips3.core->icount~~); // mov ebp,[~~mips3.core->~~icount]
	1627	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1603	1628	return RECOMPILE_SUCCESSFUL_CP(1,4);
1604	1629
1605	1630	case 0x22: /* LWL */
1606		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1607		_save_pc_before_call(); // save pc
1608		_sub_r32_imm(REG_ESP, 4); // sub esp,4
1609		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
	1631	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1632	emit_save_pc_before_call(DRCTOP); // save pc
	1633	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
	1634	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
1610	1635	if (SIMMVAL)
1611		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1612		_lea_r32_m32isd(REG_ECX, REG_EAX, 8, 0); // lea ecx,[eax*8]
1613		_and_r32_imm(REG_EAX, ~3); // and eax,~3
1614		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1636	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1637	emit_lea_r32_m32(DRCTOP, REG_ECX, MISD(REG_EAX, 8, 0)); // lea ecx,[eax*8]
	1638	emit_and_r32_imm(DRCTOP, REG_EAX, ~3); // and eax,~3
	1639	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
1615	1640	if (!mips3.core->bigendian)
1616		_xor_r32_imm(REG_ECX, 0x18); // xor ecx,0x18
1617		_shr_r32_cl(REG_EBX); // shr ebx,cl
1618		_not_r32(REG_EBX); // not ebx
1619		_push_r32(REG_ECX); // push ecx
1620		_push_r32(REG_EBX); // push ebx
1621		_push_r32(REG_EAX); // push eax
1622		_call((genf *)mips3.drcdata->read_and_translate_long_masked); // call read_and_translate_long_masked
1623		_add_r32_imm(REG_ESP, 8); // add esp,8
1624		_pop_r32(REG_ECX); // pop ecx
	1641	emit_xor_r32_imm(DRCTOP, REG_ECX, 0x18); // xor ecx,0x18
	1642	emit_shr_r32_cl(DRCTOP, REG_EBX); // shr ebx,cl
	1643	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1644	emit_push_r32(DRCTOP, REG_ECX); // push ecx
	1645	emit_push_r32(DRCTOP, REG_EBX); // push ebx
	1646	emit_push_r32(DRCTOP, REG_EAX); // push eax
	1647	emit_call(DRCTOP, mips3.drcdata->read_and_translate_long_masked); // call read_and_translate_long_masked
	1648	emit_add_r32_imm(DRCTOP, REG_ESP, 8); // add esp,8
	1649	emit_pop_r32(DRCTOP, REG_ECX); // pop ecx
1625	1650
1626	1651	if (RTREG != 0)
1627	1652	{
1628		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
1629		_shl_r32_cl(REG_EBX); // shl ebx,cl
1630		_not_r32(REG_EBX); // not ebx
1631		_shl_r32_cl(REG_EAX); // shl eax,cl
1632		_and_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // and ebx,[rtreg].lo
1633		_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
1634		_cdq(); // cdq
1635		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1653	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
	1654	emit_shl_r32_cl(DRCTOP, REG_EBX); // shl ebx,cl
	1655	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1656	emit_shl_r32_cl(DRCTOP, REG_EAX); // shl eax,cl
	1657	emit_and_r32_m32(DRCTOP, REG_EBX, REGADDRLO(RTREG)); // and ebx,[rtreg].lo
	1658	emit_or_r32_r32(DRCTOP, REG_EAX, REG_EBX); // or eax,ebx
	1659	emit_cdq(DRCTOP); // cdq
	1660	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1636	1661	}
1637		_add_r32_imm(REG_ESP, 4); // add esp,4
1638		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	1662	emit_add_r32_imm(DRCTOP, REG_ESP, 4); // add esp,4
	1663	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1639	1664	return RECOMPILE_SUCCESSFUL_CP(1,4);
1640	1665
1641	1666	case 0x23: /* LW */
1642		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1643		_save_pc_before_call(); // save pc
1644		_sub_r32_imm(REG_ESP, 8); // sub esp,8
	1667	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1668	emit_save_pc_before_call(DRCTOP); // save pc
	1669	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
1645	1670	if (RSREG != 0 && SIMMVAL != 0)
1646	1671	{
1647		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1648		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1649		_push_r32(REG_EAX); // push eax
	1672	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1673	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1674	emit_push_r32(DRCTOP, REG_EAX); // push eax
1650	1675	}
1651	1676	else if (RSREG != 0)
1652		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	1677	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
1653	1678	else
1654		_push_imm(SIMMVAL); // push SIMMVAL
1655		_call(mips3.drcdata->read_and_translate_long); // call read_and_translate_long
1656		_add_r32_imm(REG_ESP, 12); // add esp,12
	1679	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	1680	emit_call(DRCTOP, mips3.drcdata->read_and_translate_long); // call read_and_translate_long
	1681	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
1657	1682	if (RTREG != 0)
1658	1683	{
1659		_cdq(); // cdq
1660		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1684	emit_cdq(DRCTOP); // cdq
	1685	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1661	1686	}
1662		_mov_r32_m32~~abs~~(REG_EBP, ~~&mips3.core->icount~~); // mov ebp,[~~mips3.core->~~icount]
	1687	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1663	1688	return RECOMPILE_SUCCESSFUL_CP(1,4);
1664	1689
1665	1690	case 0x24: /* LBU */
1666		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1667		_save_pc_before_call(); // save pc
1668		_sub_r32_imm(REG_ESP, 8); // sub esp,8
	1691	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1692	emit_save_pc_before_call(DRCTOP); // save pc
	1693	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
1669	1694	if (RSREG != 0 && SIMMVAL != 0)
1670	1695	{
1671		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1672		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1673		_push_r32(REG_EAX); // push eax
	1696	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1697	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1698	emit_push_r32(DRCTOP, REG_EAX); // push eax
1674	1699	}
1675	1700	else if (RSREG != 0)
1676		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	1701	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
1677	1702	else
1678		_push_imm(SIMMVAL); // push SIMMVAL
1679		_call(mips3.drcdata->read_and_translate_byte_unsigned); // call read_and_translate_byte_unsigned
1680		_add_r32_imm(REG_ESP, 12); // add esp,12
	1703	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	1704	emit_call(DRCTOP, mips3.drcdata->read_and_translate_byte_unsigned); // call read_and_translate_byte_unsigned
	1705	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
1681	1706	if (RTREG != 0)
1682	1707	{
1683		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,0
1684		_mov_m32bd_r32(REG_ESI, REGDISP(RTREG), REG_EAX); // mov [rtreg].lo,eax
	1708	emit_mov_m32_imm(DRCTOP, REGADDRHI(RTREG), 0); // mov [rtreg].hi,0
	1709	emit_mov_m32_r32(DRCTOP, REGADDRLO(RTREG), REG_EAX); // mov [rtreg].lo,eax
1685	1710	}
1686		_mov_r32_m32~~abs~~(REG_EBP, ~~&mips3.core->icount~~); // mov ebp,[~~mips3.core->~~icount]
	1711	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1687	1712	return RECOMPILE_SUCCESSFUL_CP(1,4);
1688	1713
1689	1714	case 0x25: /* LHU */
1690		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1691		_save_pc_before_call(); // save pc
1692		_sub_r32_imm(REG_ESP, 8); // sub esp,8
	1715	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1716	emit_save_pc_before_call(DRCTOP); // save pc
	1717	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
1693	1718	if (RSREG != 0 && SIMMVAL != 0)
1694	1719	{
1695		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1696		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1697		_push_r32(REG_EAX); // push eax
	1720	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1721	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1722	emit_push_r32(DRCTOP, REG_EAX); // push eax
1698	1723	}
1699	1724	else if (RSREG != 0)
1700		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	1725	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
1701	1726	else
1702		_push_imm(SIMMVAL); // push SIMMVAL
1703		_call(mips3.drcdata->read_and_translate_word_unsigned); // call read_and_translate_word_unsigned
1704		_add_r32_imm(REG_ESP, 12); // add esp,12
	1727	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	1728	emit_call(DRCTOP, mips3.drcdata->read_and_translate_word_unsigned); // call read_and_translate_word_unsigned
	1729	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
1705	1730	if (RTREG != 0)
1706	1731	{
1707		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,0
1708		_mov_m32bd_r32(REG_ESI, REGDISP(RTREG), REG_EAX); // mov [rtreg].lo,eax
	1732	emit_mov_m32_imm(DRCTOP, REGADDRHI(RTREG), 0); // mov [rtreg].hi,0
	1733	emit_mov_m32_r32(DRCTOP, REGADDRLO(RTREG), REG_EAX); // mov [rtreg].lo,eax
1709	1734	}
1710		_mov_r32_m32~~abs~~(REG_EBP, ~~&mips3.core->icount~~); // mov ebp,[~~mips3.core->~~icount]
	1735	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1711	1736	return RECOMPILE_SUCCESSFUL_CP(1,4);
1712	1737
1713	1738	case 0x26: /* LWR */
1714		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1715		_save_pc_before_call(); // save pc
1716		_sub_r32_imm(REG_ESP, 4); // sub esp,4
1717		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
	1739	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1740	emit_save_pc_before_call(DRCTOP); // save pc
	1741	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
	1742	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
1718	1743	if (SIMMVAL)
1719		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1720		_lea_r32_m32isd(REG_ECX, REG_EAX, 8, 0); // lea ecx,[eax*8]
1721		_and_r32_imm(REG_EAX, ~3); // and eax,~3
1722		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1744	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1745	emit_lea_r32_m32(DRCTOP, REG_ECX, MISD(REG_EAX, 8, 0)); // lea ecx,[eax*8]
	1746	emit_and_r32_imm(DRCTOP, REG_EAX, ~3); // and eax,~3
	1747	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
1723	1748	if (mips3.core->bigendian)
1724		_xor_r32_imm(REG_ECX, 0x18); // xor ecx,0x18
1725		_shl_r32_cl(REG_EBX); // shl ebx,cl
1726		_not_r32(REG_EBX); // not ebx
1727		_push_r32(REG_ECX); // push ecx
1728		_push_r32(REG_EBX); // push ebx
1729		_push_r32(REG_EAX); // push eax
1730		_call((genf *)mips3.drcdata->read_and_translate_long_masked); // call read_and_translate_long_masked
1731		_add_r32_imm(REG_ESP, 8); // add esp,8
1732		_pop_r32(REG_ECX); // pop ecx
	1749	emit_xor_r32_imm(DRCTOP, REG_ECX, 0x18); // xor ecx,0x18
	1750	emit_shl_r32_cl(DRCTOP, REG_EBX); // shl ebx,cl
	1751	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1752	emit_push_r32(DRCTOP, REG_ECX); // push ecx
	1753	emit_push_r32(DRCTOP, REG_EBX); // push ebx
	1754	emit_push_r32(DRCTOP, REG_EAX); // push eax
	1755	emit_call(DRCTOP, mips3.drcdata->read_and_translate_long_masked); // call read_and_translate_long_masked
	1756	emit_add_r32_imm(DRCTOP, REG_ESP, 8); // add esp,8
	1757	emit_pop_r32(DRCTOP, REG_ECX); // pop ecx
1733	1758
1734	1759	if (RTREG != 0)
1735	1760	{
1736		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
1737		_shr_r32_cl(REG_EBX); // shr ebx,cl
1738		_not_r32(REG_EBX); // not ebx
1739		_shr_r32_cl(REG_EAX); // shr eax,cl
1740		_and_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // and ebx,[rtreg].lo
1741		_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
1742		_cdq(); // cdq
1743		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	1761	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
	1762	emit_shr_r32_cl(DRCTOP, REG_EBX); // shr ebx,cl
	1763	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1764	emit_shr_r32_cl(DRCTOP, REG_EAX); // shr eax,cl
	1765	emit_and_r32_m32(DRCTOP, REG_EBX, REGADDRLO(RTREG)); // and ebx,[rtreg].lo
	1766	emit_or_r32_r32(DRCTOP, REG_EAX, REG_EBX); // or eax,ebx
	1767	emit_cdq(DRCTOP); // cdq
	1768	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1744	1769	}
1745		_add_r32_imm(REG_ESP, 4); // add esp,4
1746		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	1770	emit_add_r32_imm(DRCTOP, REG_ESP, 4); // add esp,4
	1771	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1747	1772	return RECOMPILE_SUCCESSFUL_CP(1,4);
1748	1773
1749	1774	case 0x27: /* LWU */
1750		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1751		_save_pc_before_call(); // save pc
1752		_sub_r32_imm(REG_ESP, 8); // sub esp,8
	1775	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1776	emit_save_pc_before_call(DRCTOP); // save pc
	1777	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
1753	1778	if (RSREG != 0 && SIMMVAL != 0)
1754	1779	{
1755		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1756		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1757		_push_r32(REG_EAX); // push eax
	1780	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1781	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1782	emit_push_r32(DRCTOP, REG_EAX); // push eax
1758	1783	}
1759	1784	else if (RSREG != 0)
1760		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	1785	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
1761	1786	else
1762		_push_imm(SIMMVAL); // push SIMMVAL
1763		_call(mips3.drcdata->read_and_translate_long); // call read_and_translate_long
1764		_add_r32_imm(REG_ESP, 12); // add esp,12
	1787	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	1788	emit_call(DRCTOP, mips3.drcdata->read_and_translate_long); // call read_and_translate_long
	1789	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
1765	1790	if (RTREG != 0)
1766	1791	{
1767		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,0
1768		_mov_m32bd_r32(REG_ESI, REGDISP(RTREG), REG_EAX); // mov [rtreg].lo,eax
	1792	emit_mov_m32_imm(DRCTOP, REGADDRHI(RTREG), 0); // mov [rtreg].hi,0
	1793	emit_mov_m32_r32(DRCTOP, REGADDRLO(RTREG), REG_EAX); // mov [rtreg].lo,eax
1769	1794	}
1770		_mov_r32_m32~~abs~~(REG_EBP, ~~&mips3.core->icount~~); // mov ebp,[~~mips3.core->~~icount]
	1795	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1771	1796	return RECOMPILE_SUCCESSFUL_CP(1,4);
1772	1797
1773	1798	case 0x28: /* SB */
1774		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1775		_save_pc_before_call(); // save pc
1776		_sub_r32_imm(REG_ESP, 4); // sub esp,4
	1799	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1800	emit_save_pc_before_call(DRCTOP); // save pc
	1801	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
1777	1802	if (RTREG != 0)
1778		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RTREG)); // push dword [rtreg]
	1803	emit_push_m32(DRCTOP, REGADDRLO(RTREG)); // push dword [rtreg].lo
1779	1804	else
1780		_push_imm(0); // push 0
	1805	emit_push_imm(DRCTOP, 0); // push 0
1781	1806	if (RSREG != 0 && SIMMVAL != 0)
1782	1807	{
1783		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1784		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1785		_push_r32(REG_EAX); // push eax
	1808	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1809	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1810	emit_push_r32(DRCTOP, REG_EAX); // push eax
1786	1811	}
1787	1812	else if (RSREG != 0)
1788		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	1813	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
1789	1814	else
1790		_push_imm(SIMMVAL); // push SIMMVAL
1791		_call(mips3.drcdata->write_and_translate_byte); // call writebyte
1792		_add_r32_imm(REG_ESP, 12); // add esp,12
1793		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	1815	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	1816	emit_call(DRCTOP, mips3.drcdata->write_and_translate_byte); // call writebyte
	1817	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	1818	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1794	1819	return RECOMPILE_SUCCESSFUL_CP(1,4);
1795	1820
1796	1821	case 0x29: /* SH */
1797		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1798		_save_pc_before_call(); // save pc
1799		_sub_r32_imm(REG_ESP, 4); // sub esp,4
	1822	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1823	emit_save_pc_before_call(DRCTOP); // save pc
	1824	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
1800	1825	if (RTREG != 0)
1801		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RTREG)); // push dword [rtreg]
	1826	emit_push_m32(DRCTOP, REGADDRLO(RTREG)); // push dword [rtreg].lo
1802	1827	else
1803		_push_imm(0); // push 0
	1828	emit_push_imm(DRCTOP, 0); // push 0
1804	1829	if (RSREG != 0 && SIMMVAL != 0)
1805	1830	{
1806		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1807		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1808		_push_r32(REG_EAX); // push eax
	1831	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1832	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1833	emit_push_r32(DRCTOP, REG_EAX); // push eax
1809	1834	}
1810	1835	else if (RSREG != 0)
1811		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	1836	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
1812	1837	else
1813		_push_imm(SIMMVAL); // push SIMMVAL
1814		_call(mips3.drcdata->write_and_translate_word); // call writeword
1815		_add_r32_imm(REG_ESP, 12); // add esp,12
1816		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	1838	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	1839	emit_call(DRCTOP, mips3.drcdata->write_and_translate_word); // call writeword
	1840	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	1841	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1817	1842	return RECOMPILE_SUCCESSFUL_CP(1,4);
1818	1843
1819	1844	case 0x2a: /* SWL */
1820		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1821		_save_pc_before_call(); // save pc
1822		_sub_r32_imm(REG_ESP, 4); // sub esp,4
1823		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
	1845	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1846	emit_save_pc_before_call(DRCTOP); // save pc
	1847	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
	1848	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
1824	1849	if (SIMMVAL)
1825		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1826		_lea_r32_m32isd(REG_ECX, REG_EAX, 8, 0); // lea ecx,[eax*8]
1827		_and_r32_imm(REG_EAX, ~3); // and eax,~3
1828		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1850	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1851	emit_lea_r32_m32(DRCTOP, REG_ECX, MISD(REG_EAX, 8, 0)); // lea ecx,[eax*8]
	1852	emit_and_r32_imm(DRCTOP, REG_EAX, ~3); // and eax,~3
	1853	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
1829	1854	if (!mips3.core->bigendian)
1830		_xor_r32_imm(REG_ECX, 0x18); // xor ecx,0x18
1831		_shr_r32_cl(REG_EBX); // shr ebx,cl
1832		_not_r32(REG_EBX); // not ebx
1833		_push_r32(REG_EBX); // push ebx
	1855	emit_xor_r32_imm(DRCTOP, REG_ECX, 0x18); // xor ecx,0x18
	1856	emit_shr_r32_cl(DRCTOP, REG_EBX); // shr ebx,cl
	1857	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1858	emit_push_r32(DRCTOP, REG_EBX); // push ebx
1834	1859	if (RTREG != 0)
1835	1860	{
1836		_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)); // mov edx,[rtreg]
1837		_shr_r32_cl(REG_EDX); // shr edx,cl
1838		_push_r32(REG_EDX); // push edx
	1861	emit_mov_r32_m32(DRCTOP, REG_EDX, REGADDRLO(RTREG)); // mov edx,[rtreg].lo
	1862	emit_shr_r32_cl(DRCTOP, REG_EDX); // shr edx,cl
	1863	emit_push_r32(DRCTOP, REG_EDX); // push edx
1839	1864	}
1840	1865	else
1841		_push_imm(0); // push 0
1842		_push_r32(REG_EAX); // push eax
1843		_call((genf *)mips3.drcdata->write_and_translate_long_masked); // call write_and_translate_long_masked
1844		_add_r32_imm(REG_ESP, 16); // add esp,16
1845		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	1866	emit_push_imm(DRCTOP, 0); // push 0
	1867	emit_push_r32(DRCTOP, REG_EAX); // push eax
	1868	emit_call(DRCTOP, mips3.drcdata->write_and_translate_long_masked); // call write_and_translate_long_masked
	1869	emit_add_r32_imm(DRCTOP, REG_ESP, 16); // add esp,16
	1870	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1846	1871	return RECOMPILE_SUCCESSFUL_CP(1,4);
1847	1872
1848	1873	case 0x2b: /* SW */
1849		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1850		_save_pc_before_call(); // save pc
1851		_sub_r32_imm(REG_ESP, 4); // sub esp,4
	1874	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1875	emit_save_pc_before_call(DRCTOP); // save pc
	1876	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
1852	1877	if (RTREG != 0)
1853		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RTREG)); // push dword [rtreg]
	1878	emit_push_m32(DRCTOP, REGADDRLO(RTREG)); // push dword [rtreg].lo
1854	1879	else
1855		_push_imm(0); // push 0
	1880	emit_push_imm(DRCTOP, 0); // push 0
1856	1881	if (RSREG != 0 && SIMMVAL != 0)
1857	1882	{
1858		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1859		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1860		_push_r32(REG_EAX); // push eax
	1883	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	1884	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1885	emit_push_r32(DRCTOP, REG_EAX); // push eax
1861	1886	}
1862	1887	else if (RSREG != 0)
1863		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	1888	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
1864	1889	else
1865		_push_imm(SIMMVAL); // push SIMMVAL
1866		_call(mips3.drcdata->write_and_translate_long); // call write_and_translate_long
1867		_add_r32_imm(REG_ESP, 12); // add esp,12
1868		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	1890	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	1891	emit_call(DRCTOP, mips3.drcdata->write_and_translate_long); // call write_and_translate_long
	1892	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	1893	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1869	1894	return RECOMPILE_SUCCESSFUL_CP(1,4);
1870	1895
1871	1896	case 0x2c: /* SDL */
1872		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1873		_save_pc_before_call(); // save pc
1874		_sub_r32_imm(REG_ESP, 12); // sub esp,12
1875		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
	1897	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1898	emit_save_pc_before_call(DRCTOP); // save pc
	1899	emit_sub_r32_imm(DRCTOP, REG_ESP, 12); // sub esp,12
	1900	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
1876	1901	if (SIMMVAL)
1877		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1878		_lea_r32_m32isd(REG_ECX, REG_EAX, 4, 0); // lea ecx,[eax*4]
1879		_and_r32_imm(REG_EAX, ~7); // and eax,~7
1880		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
1881		_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
	1902	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1903	emit_lea_r32_m32(DRCTOP, REG_ECX, MISD(REG_EAX, 4, 0)); // lea ecx,[eax*4]
	1904	emit_and_r32_imm(DRCTOP, REG_EAX, ~7); // and eax,~7
	1905	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
	1906	emit_mov_r32_imm(DRCTOP, REG_EBP, -1); // mov ebp,-1
1882	1907	if (!mips3.core->bigendian)
1883		_xor_r32_imm(REG_ECX, 0x1c); // xor ecx,0x1c
1884		_shr_r32_cl(REG_EBP); // shr ebp,cl
1885		_shrd_r32_r32_cl(REG_EBX, REG_EBP); // shrd ebx,ebp,cl
1886		_shr_r32_cl(REG_EBP); // shr ebp,cl
1887		_not_r32(REG_EBP); // not ebp
1888		_not_r32(REG_EBX); // not ebx
1889		_push_r32(REG_EBP); // push ebp
1890		_push_r32(REG_EBX); // push ebx
	1908	emit_xor_r32_imm(DRCTOP, REG_ECX, 0x1c); // xor ecx,0x1c
	1909	emit_shr_r32_cl(DRCTOP, REG_EBP); // shr ebp,cl
	1910	emit_shrd_r32_r32_cl(DRCTOP, REG_EBX, REG_EBP); // shrd ebx,ebp,cl
	1911	emit_shr_r32_cl(DRCTOP, REG_EBP); // shr ebp,cl
	1912	emit_not_r32(DRCTOP, REG_EBP); // not ebp
	1913	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1914	emit_push_r32(DRCTOP, REG_EBP); // push ebp
	1915	emit_push_r32(DRCTOP, REG_EBX); // push ebx
1891	1916	if (RTREG != 0)
1892	1917	{
1893		_mov_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // mov ebx,[rtreg].lo
1894		_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // mov edx,[rtreg].hi
1895		_shrd_r32_r32_cl(REG_EBX, REG_EDX); // shrd ebx,edx,cl
1896		_shr_r32_cl(REG_EDX); // shr edx,cl
1897		_shrd_r32_r32_cl(REG_EBX, REG_EDX); // shrd ebx,edx,cl
1898		_shr_r32_cl(REG_EDX); // shr edx,cl
1899		_push_r32(REG_EDX); // push edx
1900		_push_r32(REG_EBX); // push ebx
	1918	emit_mov_r32_m32(DRCTOP, REG_EBX, REGADDRLO(RTREG)); // mov ebx,[rtreg].lo
	1919	emit_mov_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // mov edx,[rtreg].hi
	1920	emit_shrd_r32_r32_cl(DRCTOP, REG_EBX, REG_EDX); // shrd ebx,edx,cl
	1921	emit_shr_r32_cl(DRCTOP, REG_EDX); // shr edx,cl
	1922	emit_shrd_r32_r32_cl(DRCTOP, REG_EBX, REG_EDX); // shrd ebx,edx,cl
	1923	emit_shr_r32_cl(DRCTOP, REG_EDX); // shr edx,cl
	1924	emit_push_r32(DRCTOP, REG_EDX); // push edx
	1925	emit_push_r32(DRCTOP, REG_EBX); // push ebx
1901	1926	}
1902	1927	else
1903	1928	{
1904		_push_imm(0); // push 0
1905		_push_imm(0); // push 0
	1929	emit_push_imm(DRCTOP, 0); // push 0
	1930	emit_push_imm(DRCTOP, 0); // push 0
1906	1931	}
1907		_push_r32(REG_EAX); // push eax
1908		_call((genf *)mips3.drcdata->write_and_translate_double_masked); // call write_and_translate_double_masked
1909		_add_r32_imm(REG_ESP, 32); // add esp,32
1910		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	1932	emit_push_r32(DRCTOP, REG_EAX); // push eax
	1933	emit_call(DRCTOP, mips3.drcdata->write_and_translate_double_masked); // call write_and_translate_double_masked
	1934	emit_add_r32_imm(DRCTOP, REG_ESP, 32); // add esp,32
	1935	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1911	1936	return RECOMPILE_SUCCESSFUL_CP(1,4);
1912	1937
1913	1938	case 0x2d: /* SDR */
1914		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1915		_save_pc_before_call(); // save pc
1916		_sub_r32_imm(REG_ESP, 12); // sub esp,12
1917		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
	1939	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1940	emit_save_pc_before_call(DRCTOP); // save pc
	1941	emit_sub_r32_imm(DRCTOP, REG_ESP, 12); // sub esp,12
	1942	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
1918	1943	if (SIMMVAL)
1919		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1920		_lea_r32_m32isd(REG_ECX, REG_EAX, 4, 0); // lea ecx,[eax*4]
1921		_and_r32_imm(REG_EAX, ~7); // and eax,~7
1922		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
1923		_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
	1944	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1945	emit_lea_r32_m32(DRCTOP, REG_ECX, MISD(REG_EAX, 4, 0)); // lea ecx,[eax*4]
	1946	emit_and_r32_imm(DRCTOP, REG_EAX, ~7); // and eax,~7
	1947	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
	1948	emit_mov_r32_imm(DRCTOP, REG_EBP, -1); // mov ebp,-1
1924	1949	if (mips3.core->bigendian)
1925		_xor_r32_imm(REG_ECX, 0x1c); // xor ecx,0x1c
1926		_shl_r32_cl(REG_EBX); // shl ebx,cl
1927		_shld_r32_r32_cl(REG_EBP, REG_EBX); // shld ebp,ebx,cl
1928		_shl_r32_cl(REG_EBX); // shl ebx,cl
1929		_not_r32(REG_EBP); // not ebp
1930		_not_r32(REG_EBX); // not ebx
1931		_push_r32(REG_EBP); // push ebp
1932		_push_r32(REG_EBX); // push ebx
	1950	emit_xor_r32_imm(DRCTOP, REG_ECX, 0x1c); // xor ecx,0x1c
	1951	emit_shl_r32_cl(DRCTOP, REG_EBX); // shl ebx,cl
	1952	emit_shld_r32_r32_cl(DRCTOP, REG_EBP, REG_EBX); // shld ebp,ebx,cl
	1953	emit_shl_r32_cl(DRCTOP, REG_EBX); // shl ebx,cl
	1954	emit_not_r32(DRCTOP, REG_EBP); // not ebp
	1955	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1956	emit_push_r32(DRCTOP, REG_EBP); // push ebp
	1957	emit_push_r32(DRCTOP, REG_EBX); // push ebx
1933	1958	if (RTREG != 0)
1934	1959	{
1935		_mov_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // mov ebx,[rtreg].lo
1936		_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // mov edx,[rtreg].hi
1937		_shld_r32_r32_cl(REG_EDX, REG_EBX); // shld edx,ebx,cl
1938		_shl_r32_cl(REG_EBX); // shl ebx,cl
1939		_shld_r32_r32_cl(REG_EDX, REG_EBX); // shld edx,ebx,cl
1940		_shl_r32_cl(REG_EBX); // shl ebx,cl
1941		_push_r32(REG_EDX); // push edx
1942		_push_r32(REG_EBX); // push ebx
	1960	emit_mov_r32_m32(DRCTOP, REG_EBX, REGADDRLO(RTREG)); // mov ebx,[rtreg].lo
	1961	emit_mov_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // mov edx,[rtreg].hi
	1962	emit_shld_r32_r32_cl(DRCTOP, REG_EDX, REG_EBX); // shld edx,ebx,cl
	1963	emit_shl_r32_cl(DRCTOP, REG_EBX); // shl ebx,cl
	1964	emit_shld_r32_r32_cl(DRCTOP, REG_EDX, REG_EBX); // shld edx,ebx,cl
	1965	emit_shl_r32_cl(DRCTOP, REG_EBX); // shl ebx,cl
	1966	emit_push_r32(DRCTOP, REG_EDX); // push edx
	1967	emit_push_r32(DRCTOP, REG_EBX); // push ebx
1943	1968	}
1944	1969	else
1945	1970	{
1946		_push_imm(0); // push 0
1947		_push_imm(0); // push 0
	1971	emit_push_imm(DRCTOP, 0); // push 0
	1972	emit_push_imm(DRCTOP, 0); // push 0
1948	1973	}
1949		_push_r32(REG_EAX); // push eax
1950		_call((genf *)mips3.drcdata->write_and_translate_double_masked); // call write_and_translate_double_masked
1951		_add_r32_imm(REG_ESP, 32); // add esp,32
1952		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	1974	emit_push_r32(DRCTOP, REG_EAX); // push eax
	1975	emit_call(DRCTOP, mips3.drcdata->write_and_translate_double_masked); // call write_and_translate_double_masked
	1976	emit_add_r32_imm(DRCTOP, REG_ESP, 32); // add esp,32
	1977	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1953	1978	return RECOMPILE_SUCCESSFUL_CP(1,4);
1954	1979
1955	1980	case 0x2e: /* SWR */
1956		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1957		_save_pc_before_call(); // save pc
1958		_sub_r32_imm(REG_ESP, 4); // sub esp,4
1959		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
	1981	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	1982	emit_save_pc_before_call(DRCTOP); // save pc
	1983	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
	1984	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
1960	1985	if (SIMMVAL)
1961		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1962		_lea_r32_m32isd(REG_ECX, REG_EAX, 8, 0); // lea ecx,[eax*8]
1963		_and_r32_imm(REG_EAX, ~3); // and eax,~3
1964		_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1986	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	1987	emit_lea_r32_m32(DRCTOP, REG_ECX, MISD(REG_EAX, 8, 0)); // lea ecx,[eax*8]
	1988	emit_and_r32_imm(DRCTOP, REG_EAX, ~3); // and eax,~3
	1989	emit_mov_r32_imm(DRCTOP, REG_EBX, -1); // mov ebx,-1
1965	1990	if (mips3.core->bigendian)
1966		_xor_r32_imm(REG_ECX, 0x18); // xor ecx,0x18
1967		_shl_r32_cl(REG_EBX); // shl ebx,cl
1968		_not_r32(REG_EBX); // not ebx
1969		_push_r32(REG_EBX); // push ebx
	1991	emit_xor_r32_imm(DRCTOP, REG_ECX, 0x18); // xor ecx,0x18
	1992	emit_shl_r32_cl(DRCTOP, REG_EBX); // shl ebx,cl
	1993	emit_not_r32(DRCTOP, REG_EBX); // not ebx
	1994	emit_push_r32(DRCTOP, REG_EBX); // push ebx
1970	1995	if (RTREG != 0)
1971	1996	{
1972		_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)); // mov edx,[rtreg]
1973		_shl_r32_cl(REG_EDX); // shl edx,cl
1974		_push_r32(REG_EDX); // push edx
	1997	emit_mov_r32_m32(DRCTOP, REG_EDX, REGADDRLO(RTREG)); // mov edx,[rtreg].lo
	1998	emit_shl_r32_cl(DRCTOP, REG_EDX); // shl edx,cl
	1999	emit_push_r32(DRCTOP, REG_EDX); // push edx
1975	2000	}
1976	2001	else
1977		_push_imm(0); // push 0
1978		_push_r32(REG_EAX); // push eax
1979		_call((genf *)mips3.drcdata->write_and_translate_long_masked); // call write_and_translate_long_masked
1980		_add_r32_imm(REG_ESP, 16); // add esp,16
1981		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	2002	emit_push_imm(DRCTOP, 0); // push 0
	2003	emit_push_r32(DRCTOP, REG_EAX); // push eax
	2004	emit_call(DRCTOP, mips3.drcdata->write_and_translate_long_masked); // call write_and_translate_long_masked
	2005	emit_add_r32_imm(DRCTOP, REG_ESP, 16); // add esp,16
	2006	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
1982	2007	return RECOMPILE_SUCCESSFUL_CP(1,4);
1983	2008
1984	2009	case 0x2f: /* CACHE */
r949	r950
1987	2012	// case 0x30: /* LL */ logerror("mips3 Unhandled op: LL\n"); break;
1988	2013
1989	2014	case 0x31: /* LWC1 */
1990		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1991		_save_pc_before_call(); // save pc
1992		_sub_r32_imm(REG_ESP, 8); // sub esp,8
	2015	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	2016	emit_save_pc_before_call(DRCTOP); // save pc
	2017	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
1993	2018	if (RSREG != 0 && SIMMVAL != 0)
1994	2019	{
1995		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1996		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1997		_push_r32(REG_EAX); // push eax
	2020	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].los
	2021	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	2022	emit_push_r32(DRCTOP, REG_EAX); // push eax
1998	2023	}
1999	2024	else if (RSREG != 0)
2000		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	2025	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
2001	2026	else
2002		_push_imm(SIMMVAL); // push SIMMVAL
2003		_call(mips3.drcdata->read_and_translate_long); // call read_and_translate_long
2004		_add_r32_imm(REG_ESP, 12); // add esp,12
2005		_mov_m32abs_r32(FPR32(RTREG), REG_EAX); // mov [rtreg],eax
2006		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	2027	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	2028	emit_call(DRCTOP, mips3.drcdata->read_and_translate_long); // call read_and_translate_long
	2029	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	2030	emit_mov_m32_r32(DRCTOP, FPR32ADDR(RTREG), REG_EAX); // mov [rtreg],eax
	2031	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
2007	2032	return RECOMPILE_SUCCESSFUL_CP(1,4);
2008	2033
2009	2034	case 0x32: /* LWC2 */
2010		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2011		_save_pc_before_call(); // save pc
2012		_sub_r32_imm(REG_ESP, 8); // sub esp,8
	2035	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	2036	emit_save_pc_before_call(DRCTOP); // save pc
	2037	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
2013	2038	if (RSREG != 0 && SIMMVAL != 0)
2014	2039	{
2015		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2016		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
2017		_push_r32(REG_EAX); // push eax
	2040	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2041	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	2042	emit_push_r32(DRCTOP, REG_EAX); // push eax
2018	2043	}
2019	2044	else if (RSREG != 0)
2020		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	2045	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
2021	2046	else
2022		_push_imm(SIMMVAL); // push SIMMVAL
2023		_call(mips3.drcdata->read_and_translate_long); // call read_and_translate_long
2024		_add_r32_imm(REG_ESP, 12); // add esp,12
2025		_mov_m32abs_r32(&mips3.core->cpr[2][RTREG], REG_EAX); // mov [rtreg],eax
2026		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	2047	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	2048	emit_call(DRCTOP, mips3.drcdata->read_and_translate_long); // call read_and_translate_long
	2049	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	2050	emit_mov_m32_r32(DRCTOP, CPR2ADDR(RTREG), REG_EAX); // mov [rtreg],eax
	2051	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
2027	2052	return RECOMPILE_SUCCESSFUL_CP(1,4);
2028	2053
2029	2054	case 0x33: /* PREF */
r949	r950
2031	2056	return RECOMPILE_SUCCESSFUL_CP(1,4);
2032	2057	else
2033	2058	{
2034		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	2059	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
2035	2060	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2036	2061	}
2037	2062
2038	2063	// case 0x34: /* LLD */ logerror("mips3 Unhandled op: LLD\n"); break;
2039	2064
2040	2065	case 0x35: /* LDC1 */
2041		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2042		_save_pc_before_call(); // save pc
2043		_sub_r32_imm(REG_ESP, 8); // sub esp,8
	2066	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	2067	emit_save_pc_before_call(DRCTOP); // save pc
	2068	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
2044	2069	if (RSREG != 0 && SIMMVAL != 0)
2045	2070	{
2046		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2047		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
2048		_push_r32(REG_EAX); // push eax
	2071	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2072	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	2073	emit_push_r32(DRCTOP, REG_EAX); // push eax
2049	2074	}
2050	2075	else if (RSREG != 0)
2051		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	2076	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
2052	2077	else
2053		_push_imm(SIMMVAL); // push SIMMVAL
2054		_call((genf *)mips3.drcdata->read_and_translate_double); // call read_and_translate_double
2055		_mov_m32abs_r32(LO(FPR64(RTREG)), REG_EAX); // mov [rtreg].lo,eax
2056		_mov_m32abs_r32(HI(FPR64(RTREG)), REG_EDX); // mov [rtreg].hi,edx
2057		_add_r32_imm(REG_ESP, 12); // add esp,12
2058		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	2078	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	2079	emit_call(DRCTOP, mips3.drcdata->read_and_translate_double); // call read_and_translate_double
	2080	emit_mov_m64_r64(DRCTOP, FPR64ADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	2081	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	2082	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
2059	2083	return RECOMPILE_SUCCESSFUL_CP(1,4);
2060	2084
2061	2085	case 0x36: /* LDC2 */
2062		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2063		_save_pc_before_call(); // save pc
2064		_sub_r32_imm(REG_ESP, 8); // sub esp,8
	2086	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	2087	emit_save_pc_before_call(DRCTOP); // save pc
	2088	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
2065	2089	if (RSREG != 0 && SIMMVAL != 0)
2066	2090	{
2067		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2068		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
2069		_push_r32(REG_EAX); // push eax
	2091	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2092	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	2093	emit_push_r32(DRCTOP, REG_EAX); // push eax
2070	2094	}
2071	2095	else if (RSREG != 0)
2072		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	2096	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
2073	2097	else
2074		_push_imm(SIMMVAL); // push SIMMVAL
2075		_call((genf *)mips3.drcdata->read_and_translate_double); // call read_and_translate_long
2076		_mov_m32abs_r32(LO(&mips3.core->cpr[2][RTREG]), REG_EAX); // mov [rtreg].lo,eax
2077		_mov_m32abs_r32(HI(&mips3.core->cpr[2][RTREG]), REG_EDX); // mov [rtreg].hi,edx
2078		_add_r32_imm(REG_ESP, 12); // add esp,12
2079		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	2098	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	2099	emit_call(DRCTOP, mips3.drcdata->read_and_translate_double); // call read_and_translate_long
	2100	emit_mov_m64_r64(DRCTOP, CPR2ADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	2101	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	2102	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
2080	2103	return RECOMPILE_SUCCESSFUL_CP(1,4);
2081	2104
2082	2105	case 0x37: /* LD */
2083		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2084		_save_pc_before_call(); // save pc
2085		_sub_r32_imm(REG_ESP, 8); // sub esp,8
	2106	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	2107	emit_save_pc_before_call(DRCTOP); // save pc
	2108	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
2086	2109	if (RSREG != 0 && SIMMVAL != 0)
2087	2110	{
2088		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2089		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
2090		_push_r32(REG_EAX); // push eax
	2111	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2112	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	2113	emit_push_r32(DRCTOP, REG_EAX); // push eax
2091	2114	}
2092	2115	else if (RSREG != 0)
2093		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	2116	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
2094	2117	else
2095		_push_imm(SIMMVAL); // push SIMMVAL
2096		_call((genf *)mips3.drcdata->read_and_translate_double); // call read_and_translate_double
	2118	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	2119	emit_call(DRCTOP, mips3.drcdata->read_and_translate_double); // call read_and_translate_double
2097	2120	if (RTREG != 0)
2098		{
2099		_mov_m32bd_r32(REG_ESI, REGDISP(RTREG), REG_EAX); // mov [rtreg].lo,eax
2100		_mov_m32bd_r32(REG_ESI, REGDISP(RTREG)+4, REG_EDX); // mov [rtreg].hi,edx
2101		}
2102
2103		_add_r32_imm(REG_ESP, 12); // add esp,12
2104		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	2121	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	2122	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	2123	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
2105	2124	return RECOMPILE_SUCCESSFUL_CP(1,4);
2106	2125
2107	2126	// case 0x38: /* SC */ logerror("mips3 Unhandled op: SC\n"); break;
2108	2127
2109	2128	case 0x39: /* SWC1 */
2110		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2111		_save_pc_before_call(); // save pc
2112		_sub_r32_imm(REG_ESP, 4); // sub esp,4
2113		_push_m32abs(FPR32(RTREG)); // push dword [rtreg]
	2129	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	2130	emit_save_pc_before_call(DRCTOP); // save pc
	2131	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
	2132	emit_push_m32(DRCTOP, FPR32ADDR(RTREG)); // push dword [rtreg]
2114	2133	if (RSREG != 0 && SIMMVAL != 0)
2115	2134	{
2116		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2117		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
2118		_push_r32(REG_EAX); // push eax
	2135	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2136	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	2137	emit_push_r32(DRCTOP, REG_EAX); // push eax
2119	2138	}
2120	2139	else if (RSREG != 0)
2121		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	2140	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
2122	2141	else
2123		_push_imm(SIMMVAL); // push SIMMVAL
2124		_call(mips3.drcdata->write_and_translate_long); // call write_and_translate_long
2125		_add_r32_imm(REG_ESP, 12); // add esp,12
2126		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	2142	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	2143	emit_call(DRCTOP, mips3.drcdata->write_and_translate_long); // call write_and_translate_long
	2144	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	2145	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
2127	2146	return RECOMPILE_SUCCESSFUL_CP(1,4);
2128	2147
2129	2148	case 0x3a: /* SWC2 */
2130		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2131		_save_pc_before_call(); // save pc
2132		_sub_r32_imm(REG_ESP, 4); // sub esp,4
2133		_push_m32abs(&mips3.core->cpr[2][RTREG]); // push dword [rtreg]
	2149	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	2150	emit_save_pc_before_call(DRCTOP); // save pc
	2151	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
	2152	emit_push_m32(DRCTOP, CPR2ADDR(RTREG)); // push dword [rtreg]
2134	2153	if (RSREG != 0 && SIMMVAL != 0)
2135	2154	{
2136		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2137		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
2138		_push_r32(REG_EAX); // push eax
	2155	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2156	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	2157	emit_push_r32(DRCTOP, REG_EAX); // push eax
2139	2158	}
2140	2159	else if (RSREG != 0)
2141		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	2160	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
2142	2161	else
2143		_push_imm(SIMMVAL); // push SIMMVAL
2144		_call(mips3.drcdata->write_and_translate_long); // call write_and_translate_long
2145		_add_r32_imm(REG_ESP, 12); // add esp,12
2146		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	2162	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	2163	emit_call(DRCTOP, mips3.drcdata->write_and_translate_long); // call write_and_translate_long
	2164	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	2165	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
2147	2166	return RECOMPILE_SUCCESSFUL_CP(1,4);
2148	2167
2149	2168	// case 0x3b: /* SWC3 */ invalid_instruction(op); break;
2150	2169	// case 0x3c: /* SCD */ logerror("mips3 Unhandled op: SCD\n"); break;
2151	2170
2152	2171	case 0x3d: /* SDC1 */
2153		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2154		_save_pc_before_call(); // save pc
2155		_push_m32abs(HI(FPR64(RTREG))); // push dword [rtreg].hi
2156		_push_m32abs(LO(FPR64(RTREG))); // push dword [rtreg].lo
	2172	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	2173	emit_save_pc_before_call(DRCTOP); // save pc
	2174	emit_push_m32(DRCTOP, FPR64ADDRHI(RTREG)); // push dword [rtreg].hi
	2175	emit_push_m32(DRCTOP, FPR64ADDRLO(RTREG)); // push dword [rtreg].lo
2157	2176	if (RSREG != 0 && SIMMVAL != 0)
2158	2177	{
2159		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2160		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
2161		_push_r32(REG_EAX); // push eax
	2178	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2179	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	2180	emit_push_r32(DRCTOP, REG_EAX); // push eax
2162	2181	}
2163	2182	else if (RSREG != 0)
2164		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	2183	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
2165	2184	else
2166		_push_imm(SIMMVAL); // push SIMMVAL
2167		_call((genf *)mips3.drcdata->write_and_translate_double); // call write_and_translate_double
2168		_add_r32_imm(REG_ESP, 12); // add esp,12
2169		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	2185	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	2186	emit_call(DRCTOP, mips3.drcdata->write_and_translate_double); // call write_and_translate_double
	2187	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	2188	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
2170	2189	return RECOMPILE_SUCCESSFUL_CP(1,4);
2171	2190
2172	2191	case 0x3e: /* SDC2 */
2173		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2174		_save_pc_before_call(); // save pc
2175		_push_m32abs(HI(&mips3.core->cpr[2][RTREG])); // push dword [rtreg].hi
2176		_push_m32abs(LO(&mips3.core->cpr[2][RTREG])); // push dword [rtreg].lo
	2192	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	2193	emit_save_pc_before_call(DRCTOP); // save pc
	2194	emit_push_m32(DRCTOP, CPR2ADDRHI(RTREG)); // push dword [rtreg].hi
	2195	emit_push_m32(DRCTOP, CPR2ADDRLO(RTREG)); // push dword [rtreg].lo
2177	2196	if (RSREG != 0 && SIMMVAL != 0)
2178	2197	{
2179		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2180		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
2181		_push_r32(REG_EAX); // push eax
	2198	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2199	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	2200	emit_push_r32(DRCTOP, REG_EAX); // push eax
2182	2201	}
2183	2202	else if (RSREG != 0)
2184		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	2203	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
2185	2204	else
2186		_push_imm(SIMMVAL); // push SIMMVAL
2187		_call((genf *)mips3.drcdata->write_and_translate_double); // call write_and_translate_double
2188		_add_r32_imm(REG_ESP, 12); // add esp,12
2189		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	2205	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	2206	emit_call(DRCTOP, mips3.drcdata->write_and_translate_double); // call write_and_translate_double
	2207	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	2208	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
2190	2209	return RECOMPILE_SUCCESSFUL_CP(1,4);
2191	2210
2192	2211	case 0x3f: /* SD */
2193		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2194		_save_pc_before_call(); // save pc
	2212	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	2213	emit_save_pc_before_call(DRCTOP); // save pc
2195	2214	if (RTREG != 0)
2196	2215	{
2197		_push_m32bd(REG_ESI, REGDISP(RTREG)+4); // push dword [rtreg].hi
2198		_push_m32bd(REG_ESI, REGDISP(RTREG)); // push dword [rtreg].lo
	2216	emit_push_m32(DRCTOP, REGADDRHI(RTREG)); // push dword [rtreg].hi
	2217	emit_push_m32(DRCTOP, REGADDRLO(RTREG)); // push dword [rtreg].lo
2199	2218	}
2200	2219	else
2201	2220	{
2202		_push_imm(0); // push 0
2203		_push_imm(0); // push 0
	2221	emit_push_imm(DRCTOP, 0); // push 0
	2222	emit_push_imm(DRCTOP, 0); // push 0
2204	2223	}
2205	2224	if (RSREG != 0 && SIMMVAL != 0)
2206	2225	{
2207		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2208		_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
2209		_push_r32(REG_EAX); // push eax
	2226	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2227	emit_add_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // add eax,SIMMVAL
	2228	emit_push_r32(DRCTOP, REG_EAX); // push eax
2210	2229	}
2211	2230	else if (RSREG != 0)
2212		_push_m32bd(R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // push [rsreg]
	2231	emit_push_m32(DRCTOP, REGADDRLO(RSREG)); // push [rsreg].lo
2213	2232	else
2214		_push_imm(SIMMVAL); // push SIMMVAL
2215		_call((genf *)mips3.drcdata->write_and_translate_double); // call write_and_translate_double
2216		_add_r32_imm(REG_ESP, 12); // add esp,12
2217		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	2233	emit_push_imm(DRCTOP, SIMMVAL); // push SIMMVAL
	2234	emit_call(DRCTOP, mips3.drcdata->write_and_translate_double); // call write_and_translate_double
	2235	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	2236	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
2218	2237	return RECOMPILE_SUCCESSFUL_CP(1,4);
2219	2238
2220	2239	// default: /* ??? */ invalid_instruction(op); break;
r949	r950
2229	2248
2230	2249	static UINT32 recompile_special1(drc_core *drc, UINT32 pc, UINT32 op)
2231	2250	{
2232		link_info link1, link2, link3;
	2251	emit_link link1, link2, link3;
2233	2252	int cycles;
2234	2253
2235	2254	switch (op & 63)
r949	r950
2239	2258	{
2240	2259	if (RTREG != 0)
2241	2260	{
2242		_mov_r32_m32bd(R~~EG_EAX~~, REG_ESI, REGD~~ISP~~(RTREG)); // mov eax,[rtreg]
	2261	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
2243	2262	if (SHIFT != 0)
2244		_shl_r32_imm(REG_EAX, SHIFT); // shl eax,SHIFT
2245		_cdq(); // cdq
2246		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2263	emit_shl_r32_imm(DRCTOP, REG_EAX, SHIFT); // shl eax,SHIFT
	2264	emit_cdq(DRCTOP); // cdq
	2265	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2247	2266	}
2248	2267	else
2249		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2268	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2250	2269	}
2251	2270	return RECOMPILE_SUCCESSFUL_CP(1,4);
2252	2271
2253	2272	case 0x01: /* MOVF - R5000*/
2254	2273	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
2255	2274	{
2256		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	2275	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
2257	2276	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2258	2277	}
2259		_cmp_m8abs_imm(&mips3.core->cf[1][(op >> 18) & 7], 0); // cmp [cf[x]],0
2260		_jcc_short_link(((op >> 16) & 1) ? COND_Z : COND_NZ, &link1); // jz/nz skip
2261		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
2262		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2263		_resolve_link(&link1); // skip:
	2278	emit_cmp_m8_imm(DRCTOP, CF1ADDR((op >> 18) & 7), 0); // cmp [cf[x]],0
	2279	emit_jcc_short_link(DRCTOP, ((op >> 16) & 1) ? COND_Z : COND_NZ, &link1); // jz/nz skip
	2280	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	2281	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2282	resolve_link(DRCTOP, &link1); // skip:
2264	2283	return RECOMPILE_SUCCESSFUL_CP(1,4);
2265	2284
2266	2285	case 0x02: /* SRL */
r949	r950
2268	2287	{
2269	2288	if (RTREG != 0)
2270	2289	{
2271		_mov_r32_m32bd(R~~EG_EAX~~, REG_ESI, REGD~~ISP~~(RTREG)); // mov eax,[rtreg]
	2290	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
2272	2291	if (SHIFT != 0)
2273		_shr_r32_imm(REG_EAX, SHIFT); // shr eax,SHIFT
2274		_cdq(); // cdq
2275		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2292	emit_shr_r32_imm(DRCTOP, REG_EAX, SHIFT); // shr eax,SHIFT
	2293	emit_cdq(DRCTOP); // cdq
	2294	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2276	2295	}
2277	2296	else
2278		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2297	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2279	2298	}
2280	2299	return RECOMPILE_SUCCESSFUL_CP(1,4);
2281	2300
r949	r950
2284	2303	{
2285	2304	if (RTREG != 0)
2286	2305	{
2287		_mov_r32_m32bd(R~~EG_EAX~~, REG_ESI, REGD~~ISP~~(RTREG)); // mov eax,[rtreg]
	2306	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
2288	2307	if (SHIFT != 0)
2289		_sar_r32_imm(REG_EAX, SHIFT); // sar eax,SHIFT
2290		_cdq(); // cdq
2291		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2308	emit_sar_r32_imm(DRCTOP, REG_EAX, SHIFT); // sar eax,SHIFT
	2309	emit_cdq(DRCTOP); // cdq
	2310	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2292	2311	}
2293	2312	else
2294		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2313	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2295	2314	}
2296	2315	return RECOMPILE_SUCCESSFUL_CP(1,4);
2297	2316
r949	r950
2300	2319	{
2301	2320	if (RTREG != 0)
2302	2321	{
2303		_mov_r32_m32bd(R~~EG_EAX~~, REG_ESI, REGD~~ISP~~(RTREG)); // mov eax,[rtreg]
	2322	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
2304	2323	if (RSREG != 0)
2305	2324	{
2306		_mov_r32_m32bd(REG_ECX, REG_ESI, REGDISP(RSREG)); // mov ecx,[rsreg]
2307		_shl_r32_cl(REG_EAX); // shl eax,cl
	2325	emit_mov_r32_m32(DRCTOP, REG_ECX, REGADDRLO(RSREG)); // mov ecx,[rsreg].lo
	2326	emit_shl_r32_cl(DRCTOP, REG_EAX); // shl eax,cl
2308	2327	}
2309		_cdq(); // cdq
2310		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2328	emit_cdq(DRCTOP); // cdq
	2329	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2311	2330	}
2312	2331	else
2313		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2332	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2314	2333	}
2315	2334	return RECOMPILE_SUCCESSFUL_CP(1,4);
2316	2335
r949	r950
2319	2338	{
2320	2339	if (RTREG != 0)
2321	2340	{
2322		_mov_r32_m32bd(R~~EG_EAX~~, REG_ESI, REGD~~ISP~~(RTREG)); // mov eax,[rtreg]
	2341	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
2323	2342	if (RSREG != 0)
2324	2343	{
2325		_mov_r32_m32bd(REG_ECX, REG_ESI, REGDISP(RSREG)); // mov ecx,[rsreg]
2326		_shr_r32_cl(REG_EAX); // shr eax,cl
	2344	emit_mov_r32_m32(DRCTOP, REG_ECX, REGADDRLO(RSREG)); // mov ecx,[rsreg].lo
	2345	emit_shr_r32_cl(DRCTOP, REG_EAX); // shr eax,cl
2327	2346	}
2328		_cdq(); // cdq
2329		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2347	emit_cdq(DRCTOP); // cdq
	2348	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2330	2349	}
2331	2350	else
2332		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2351	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2333	2352	}
2334	2353	return RECOMPILE_SUCCESSFUL_CP(1,4);
2335	2354
r949	r950
2338	2357	{
2339	2358	if (RTREG != 0)
2340	2359	{
2341		_mov_r32_m32bd(R~~EG_EAX~~, REG_ESI, REGD~~ISP~~(RTREG)); // mov eax,[rtreg]
	2360	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
2342	2361	if (RSREG != 0)
2343	2362	{
2344		_mov_r32_m32bd(REG_ECX, REG_ESI, REGDISP(RSREG)); // mov ecx,[rsreg]
2345		_sar_r32_cl(REG_EAX); // sar eax,cl
	2363	emit_mov_r32_m32(DRCTOP, REG_ECX, REGADDRLO(RSREG)); // mov ecx,[rsreg].lo
	2364	emit_sar_r32_cl(DRCTOP, REG_EAX); // sar eax,cl
2346	2365	}
2347		_cdq(); // cdq
2348		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2366	emit_cdq(DRCTOP); // cdq
	2367	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2349	2368	}
2350	2369	else
2351		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2370	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2352	2371	}
2353	2372	return RECOMPILE_SUCCESSFUL_CP(1,4);
2354	2373
2355	2374	case 0x08: /* JR */
2356		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2357		_mov_m32abs_r32(&jr_temp, REG_EAX); // mov jr_temp,eax
2358		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
2359		_mov_r32_m32abs(REG_EDI, &jr_temp); // mov edi,jr_temp
	2375	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2376	emit_mov_m32_r32(DRCTOP, MABS(&jr_temp), REG_EAX); // mov jr_temp,eax
	2377	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	2378	emit_mov_r32_m32(DRCTOP, REG_EDI, MABS(&jr_temp)); // mov edi,jr_temp
2360	2379	return RECOMPILE_SUCCESSFUL_CP(1+cycles,0) \| RECOMPILE_END_OF_STRING \| RECOMPILE_ADD_DISPATCH;
2361	2380
2362	2381	case 0x09: /* JALR */
2363		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	2382	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
2364	2383	if (RDREG != 0)
2365		_mov_m64bd_imm32(REG_ESI, REGDISP(RDREG), pc + 8); // mov [rdreg],pc + 8
2366		_mov_r32_m32bd(REG_EDI, REG_ESI, REGDISP(RSREG)); // mov edi,[rsreg]
	2384	emit_mov_m64_imm32(DRCTOP, REGADDR(RDREG), pc + 8); // mov [rdreg],pc + 8
	2385	emit_mov_r32_m32(DRCTOP, REG_EDI, REGADDRLO(RSREG)); // mov edi,[rsreg].lo
2367	2386	return RECOMPILE_SUCCESSFUL_CP(1+cycles,0) \| RECOMPILE_END_OF_STRING \| RECOMPILE_ADD_DISPATCH;
2368	2387
2369	2388	case 0x0a: /* MOVZ - R5000 */
2370	2389	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
2371	2390	{
2372		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	2391	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
2373	2392	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2374	2393	}
2375	2394	if (RDREG != 0)
2376	2395	{
2377		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg].lo
2378		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // or eax,[rtreg].hi
2379		_jcc_short_link(COND_NZ, &link1); // jnz skip
2380		_mov_m64bd_m64bd(REG_ESI, REGDISP(RDREG), REG_ESI, REGDISP(RSREG)); // mov [rdreg],[rsreg]
2381		_resolve_link(&link1); // skip:
	2396	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	2397	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // or eax,[rtreg].hi
	2398	emit_jcc_short_link(DRCTOP, COND_NZ, &link1); // jnz skip
	2399	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RSREG));
	2400	// mov [rdreg],[rsreg]
	2401	resolve_link(DRCTOP, &link1); // skip:
2382	2402	}
2383	2403	return RECOMPILE_SUCCESSFUL_CP(1,4);
2384	2404
2385	2405	case 0x0b: /* MOVN - R5000 */
2386	2406	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
2387	2407	{
2388		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	2408	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
2389	2409	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2390	2410	}
2391	2411	if (RDREG != 0)
2392	2412	{
2393		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg].lo
2394		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // or eax,[rtreg].hi
2395		_jcc_short_link(COND_Z, &link1); // jz skip
2396		_mov_m64bd_m64bd(REG_ESI, REGDISP(RDREG), REG_ESI, REGDISP(RSREG)); // mov [rdreg],[rsreg]
2397		_resolve_link(&link1); // skip:
	2413	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	2414	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // or eax,[rtreg].hi
	2415	emit_jcc_short_link(DRCTOP, COND_Z, &link1); // jz skip
	2416	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RSREG));
	2417	// mov [rdreg],[rsreg]
	2418	resolve_link(DRCTOP, &link1); // skip:
2398	2419	}
2399	2420	return RECOMPILE_SUCCESSFUL_CP(1,4);
2400	2421
2401	2422	case 0x0c: /* SYSCALL */
2402		_jmp((void *)mips3.drcdata->generate_syscall_exception); // jmp generate_syscall_exception
	2423	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_syscall_exception); // jmp generate_syscall_exception
2403	2424	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2404	2425
2405	2426	case 0x0d: /* BREAK */
2406		_jmp((void *)mips3.drcdata->generate_break_exception); // jmp generate_break_exception
	2427	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_break_exception); // jmp generate_break_exception
2407	2428	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2408	2429
2409	2430	case 0x0f: /* SYNC */
r949	r950
2411	2432
2412	2433	case 0x10: /* MFHI */
2413	2434	if (RDREG != 0)
2414		_mov_m64bd_m64~~abs~~(R~~EG_ESI~~, REGD~~ISP~~(RDREG), ~~&mips3.core->hi~~); // mov [rdreg],[hi]
	2435	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), HIADDR); // mov [rdreg],[hi]
2415	2436	return RECOMPILE_SUCCESSFUL_CP(1,4);
2416	2437
2417	2438	case 0x11: /* MTHI */
2418		_mov_m64~~abs~~_m64bd(~~&mips3.core->hi~~, ~~REG_ES~~I, REGD~~ISP~~(RSREG)); // mov [hi],[rsreg]
	2439	emit_mov_m64_m64(DRCTOP, HIADDR, REGADDR(RSREG)); // mov [hi],[rsreg]
2419	2440	return RECOMPILE_SUCCESSFUL_CP(1,4);
2420	2441
2421	2442	case 0x12: /* MFLO */
2422	2443	if (RDREG != 0)
2423		_mov_m64bd_m64~~abs~~(R~~EG_ESI~~, REGD~~ISP~~(RDREG), ~~&mips3.core->lo~~); // mov [rdreg],[lo]
	2444	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), LOADDR); // mov [rdreg],[lo]
2424	2445	return RECOMPILE_SUCCESSFUL_CP(1,4);
2425	2446
2426	2447	case 0x13: /* MTLO */
2427		_mov_m64~~abs~~_m64bd(~~&mips3.core->lo~~, R~~EG_ESI~~, REGD~~ISP~~(RSREG)); // mov [lo],[rsreg]
	2448	emit_mov_m64_m64(DRCTOP, LOADDR, REGADDR(RSREG)); // mov [lo],[rsreg]
2428	2449	return RECOMPILE_SUCCESSFUL_CP(1,4);
2429	2450
2430	2451	case 0x14: /* DSLLV */
r949	r950
2432	2453	{
2433	2454	if (RTREG != 0)
2434	2455	{
2435		_mov_r64_m64bd(REG_EDX, REG_EAX, REG~~_ESI, REG~~D~~ISP~~(RTREG)); // mov edx:eax,[rtreg]
	2456	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RTREG)); // mov edx:eax,[rtreg]
2436	2457	if (RSREG != 0)
2437	2458	{
2438		_mov_r32_m32bd(REG_ECX, REG_ESI, REGDISP(RSREG)); // mov ecx,[rsreg]
2439		_test_r32_imm(REG_ECX, 0x20); // test ecx,0x20
2440		_jcc_short_link(COND_Z, &link1); // jz skip
2441		_mov_r32_r32(REG_EDX, REG_EAX); // mov edx,eax
2442		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
2443		_resolve_link(&link1); // skip:
2444		_shld_r32_r32_cl(REG_EDX, REG_EAX); // shld edx,eax,cl
2445		_shl_r32_cl(REG_EAX); // shl eax,cl
	2459	emit_mov_r32_m32(DRCTOP, REG_ECX, REGADDRLO(RSREG)); // mov ecx,[rsreg].lo
	2460	emit_test_r32_imm(DRCTOP, REG_ECX, 0x20); // test ecx,0x20
	2461	emit_jcc_short_link(DRCTOP, COND_Z, &link1); // jz skip
	2462	emit_mov_r32_r32(DRCTOP, REG_EDX, REG_EAX); // mov edx,eax
	2463	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX); // xor eax,eax
	2464	resolve_link(DRCTOP, &link1); // skip:
	2465	emit_shld_r32_r32_cl(DRCTOP, REG_EDX, REG_EAX); // shld edx,eax,cl
	2466	emit_shl_r32_cl(DRCTOP, REG_EAX); // shl eax,cl
2446	2467	}
2447		_mov_m64bd_r64(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2468	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2448	2469	}
2449	2470	else
2450		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2471	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2451	2472	}
2452	2473	return RECOMPILE_SUCCESSFUL_CP(1,4);
2453	2474
r949	r950
2456	2477	{
2457	2478	if (RTREG != 0)
2458	2479	{
2459		_mov_r64_m64bd(REG_EDX, REG_EAX, REG~~_ESI, REG~~D~~ISP~~(RTREG)); // mov edx:eax,[rtreg]
	2480	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RTREG)); // mov edx:eax,[rtreg]
2460	2481	if (RSREG != 0)
2461	2482	{
2462		_mov_r32_m32bd(REG_ECX, REG_ESI, REGDISP(RSREG)); // mov ecx,[rsreg]
2463		_test_r32_imm(REG_ECX, 0x20); // test ecx,0x20
2464		_jcc_short_link(COND_Z, &link1); // jz skip
2465		_mov_r32_r32(REG_EAX, REG_EDX); // mov eax,edx
2466		_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
2467		_resolve_link(&link1); // skip:
2468		_shrd_r32_r32_cl(REG_EAX, REG_EDX); // shrd eax,edx,cl
2469		_shr_r32_cl(REG_EDX); // shr edx,cl
	2483	emit_mov_r32_m32(DRCTOP, REG_ECX, REGADDRLO(RSREG)); // mov ecx,[rsreg].lo
	2484	emit_test_r32_imm(DRCTOP, REG_ECX, 0x20); // test ecx,0x20
	2485	emit_jcc_short_link(DRCTOP, COND_Z, &link1); // jz skip
	2486	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_EDX); // mov eax,edx
	2487	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EDX); // xor edx,edx
	2488	resolve_link(DRCTOP, &link1); // skip:
	2489	emit_shrd_r32_r32_cl(DRCTOP, REG_EAX, REG_EDX); // shrd eax,edx,cl
	2490	emit_shr_r32_cl(DRCTOP, REG_EDX); // shr edx,cl
2470	2491	}
2471		_mov_m64bd_r64(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2492	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2472	2493	}
2473	2494	else
2474		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2495	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2475	2496	}
2476	2497	return RECOMPILE_SUCCESSFUL_CP(1,4);
2477	2498
r949	r950
2480	2501	{
2481	2502	if (RTREG != 0)
2482	2503	{
2483		_mov_r64_m64bd(REG_EDX, REG_EAX, REG~~_ESI, REG~~D~~ISP~~(RTREG)); // mov edx:eax,[rtreg]
	2504	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RTREG)); // mov edx:eax,[rtreg]
2484	2505	if (RSREG != 0)
2485	2506	{
2486		_mov_r32_m32bd(REG_ECX, REG_ESI, REGDISP(RSREG)); // mov ecx,[rsreg]
2487		_test_r32_imm(REG_ECX, 0x20); // test ecx,0x20
2488		_jcc_short_link(COND_Z, &link1); // jz skip
2489		_mov_r32_r32(REG_EAX, REG_EDX); // mov eax,edx
2490		_cdq(); // cdq
2491		_resolve_link(&link1); // skip:
2492		_shrd_r32_r32_cl(REG_EAX, REG_EDX); // shrd eax,edx,cl
2493		_sar_r32_cl(REG_EDX); // sar edx,cl
	2507	emit_mov_r32_m32(DRCTOP, REG_ECX, REGADDRLO(RSREG)); // mov ecx,[rsreg].lo
	2508	emit_test_r32_imm(DRCTOP, REG_ECX, 0x20); // test ecx,0x20
	2509	emit_jcc_short_link(DRCTOP, COND_Z, &link1); // jz skip
	2510	emit_mov_r32_r32(DRCTOP, REG_EAX, REG_EDX); // mov eax,edx
	2511	emit_cdq(DRCTOP); // cdq
	2512	resolve_link(DRCTOP, &link1); // skip:
	2513	emit_shrd_r32_r32_cl(DRCTOP, REG_EAX, REG_EDX); // shrd eax,edx,cl
	2514	emit_sar_r32_cl(DRCTOP, REG_EDX); // sar edx,cl
2494	2515	}
2495		_mov_m64bd_r64(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2516	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2496	2517	}
2497	2518	else
2498		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2519	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2499	2520	}
2500	2521	return RECOMPILE_SUCCESSFUL_CP(1,4);
2501	2522
2502	2523	case 0x18: /* MULT */
2503		_mov_r32_m32bd(REG_ECX, REG_ESI, REGDISP(RTREG)); // mov ecx,[rtreg].lo
2504		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
2505		_imul_r32(REG_ECX); // imul ecx
2506		_push_r32(REG_EDX); // push edx
2507		_cdq(); // cdq
2508		_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
2509		_pop_r32(REG_EAX); // pop eax
2510		_cdq(); // cdq
2511		_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
	2524	emit_mov_r32_m32(DRCTOP, REG_ECX, REGADDRLO(RTREG)); // mov ecx,[rtreg].lo
	2525	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2526	emit_imul_r32(DRCTOP, REG_ECX); // imul ecx
	2527	emit_push_r32(DRCTOP, REG_EDX); // push edx
	2528	emit_cdq(DRCTOP); // cdq
	2529	emit_mov_m64_r64(DRCTOP, LOADDR, REG_EDX, REG_EAX); // mov [lo],edx:eax
	2530	emit_pop_r32(DRCTOP, REG_EAX); // pop eax
	2531	emit_cdq(DRCTOP); // cdq
	2532	emit_mov_m64_r64(DRCTOP, HIADDR, REG_EDX, REG_EAX); // mov [hi],edx:eax
2512	2533	return RECOMPILE_SUCCESSFUL_CP(4,4);
2513	2534
2514	2535	case 0x19: /* MULTU */
2515		_mov_r32_m32bd(REG_ECX, REG_ESI, REGDISP(RTREG)); // mov ecx,[rtreg].lo
2516		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
2517		_mul_r32(REG_ECX); // mul ecx
2518		_push_r32(REG_EDX); // push edx
2519		_cdq(); // cdq
2520		_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
2521		_pop_r32(REG_EAX); // pop eax
2522		_cdq(); // cdq
2523		_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
	2536	emit_mov_r32_m32(DRCTOP, REG_ECX, REGADDRLO(RTREG)); // mov ecx,[rtreg].lo
	2537	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2538	emit_mul_r32(DRCTOP, REG_ECX); // mul ecx
	2539	emit_push_r32(DRCTOP, REG_EDX); // push edx
	2540	emit_cdq(DRCTOP); // cdq
	2541	emit_mov_m64_r64(DRCTOP, LOADDR, REG_EDX, REG_EAX); // mov [lo],edx:eax
	2542	emit_pop_r32(DRCTOP, REG_EAX); // pop eax
	2543	emit_cdq(DRCTOP); // cdq
	2544	emit_mov_m64_r64(DRCTOP, HIADDR, REG_EDX, REG_EAX); // mov [hi],edx:eax
2524	2545	return RECOMPILE_SUCCESSFUL_CP(4,4);
2525	2546
2526	2547	case 0x1a: /* DIV */
2527	2548	if (RTREG != 0)
2528	2549	{
2529		_mov_r32_m32bd(REG_ECX, REG_ESI, REGDISP(RTREG)); // mov ecx,[rtreg].lo
2530		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
2531		_cdq(); // cdq
2532		_cmp_r32_imm(REG_ECX, 0); // cmp ecx,0
2533		_jcc_short_link(COND_E, &link1); // je skip
2534		_idiv_r32(REG_ECX); // idiv ecx
2535		_push_r32(REG_EDX); // push edx
2536		_cdq(); // cdq
2537		_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
2538		_pop_r32(REG_EAX); // pop eax
2539		_cdq(); // cdq
2540		_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
2541		_resolve_link(&link1); // skip:
	2550	emit_mov_r32_m32(DRCTOP, REG_ECX, REGADDRLO(RTREG)); // mov ecx,[rtreg].lo
	2551	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2552	emit_cdq(DRCTOP); // cdq
	2553	emit_cmp_r32_imm(DRCTOP, REG_ECX, 0); // cmp ecx,0
	2554	emit_jcc_short_link(DRCTOP, COND_E, &link1); // je skip
	2555	emit_idiv_r32(DRCTOP, REG_ECX); // idiv ecx
	2556	emit_push_r32(DRCTOP, REG_EDX); // push edx
	2557	emit_cdq(DRCTOP); // cdq
	2558	emit_mov_m64_r64(DRCTOP, LOADDR, REG_EDX, REG_EAX); // mov [lo],edx:eax
	2559	emit_pop_r32(DRCTOP, REG_EAX); // pop eax
	2560	emit_cdq(DRCTOP); // cdq
	2561	emit_mov_m64_r64(DRCTOP, HIADDR, REG_EDX, REG_EAX); // mov [hi],edx:eax
	2562	resolve_link(DRCTOP, &link1); // skip:
2542	2563	}
2543	2564	return RECOMPILE_SUCCESSFUL_CP(36,4);
2544	2565
2545	2566	case 0x1b: /* DIVU */
2546	2567	if (RTREG != 0)
2547	2568	{
2548		_mov_r32_m32bd(REG_ECX, REG_ESI, REGDISP(RTREG)); // mov ecx,[rtreg].lo
2549		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
2550		_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
2551		_cmp_r32_imm(REG_ECX, 0); // cmp ecx,0
2552		_jcc_short_link(COND_E, &link1); // je skip
2553		_div_r32(REG_ECX); // div ecx
2554		_push_r32(REG_EDX); // push edx
2555		_cdq(); // cdq
2556		_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
2557		_pop_r32(REG_EAX); // pop eax
2558		_cdq(); // cdq
2559		_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
2560		_resolve_link(&link1); // skip:
	2569	emit_mov_r32_m32(DRCTOP, REG_ECX, REGADDRLO(RTREG)); // mov ecx,[rtreg].lo
	2570	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2571	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EDX); // xor edx,edx
	2572	emit_cmp_r32_imm(DRCTOP, REG_ECX, 0); // cmp ecx,0
	2573	emit_jcc_short_link(DRCTOP, COND_E, &link1); // je skip
	2574	emit_div_r32(DRCTOP, REG_ECX); // div ecx
	2575	emit_push_r32(DRCTOP, REG_EDX); // push edx
	2576	emit_cdq(DRCTOP); // cdq
	2577	emit_mov_m64_r64(DRCTOP, LOADDR, REG_EDX, REG_EAX); // mov [lo],edx:eax
	2578	emit_pop_r32(DRCTOP, REG_EAX); // pop eax
	2579	emit_cdq(DRCTOP); // cdq
	2580	emit_mov_m64_r64(DRCTOP, HIADDR, REG_EDX, REG_EAX); // mov [hi],edx:eax
	2581	resolve_link(DRCTOP, &link1); // skip:
2561	2582	}
2562	2583	return RECOMPILE_SUCCESSFUL_CP(36,4);
2563	2584
2564	2585	case 0x1c: /* DMULT */
2565		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
2566		_cmp_r32_imm(REG_EDX, 0); // cmp edx,0
2567		_jcc_short_link(COND_GE, &link1); // jge skip1
2568		_mov_r32_r32(REG_ECX, REG_EDX); // mov ecx,edx
2569		_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
2570		_neg_r32(REG_EAX); // neg eax
2571		_sbb_r32_r32(REG_EDX, REG_ECX); // sbb edx,ecx
2572		_resolve_link(&link1); // skip1:
2573		_mov_m64abs_r64(&dmult_temp1, REG_EDX, REG_EAX); // mov [dmult_temp1],edx:eax
	2586	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	2587	emit_cmp_r32_imm(DRCTOP, REG_EDX, 0); // cmp edx,0
	2588	emit_jcc_short_link(DRCTOP, COND_GE, &link1); // jge skip1
	2589	emit_mov_r32_r32(DRCTOP, REG_ECX, REG_EDX); // mov ecx,edx
	2590	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EDX); // xor edx,edx
	2591	emit_neg_r32(DRCTOP, REG_EAX); // neg eax
	2592	emit_sbb_r32_r32(DRCTOP, REG_EDX, REG_ECX); // sbb edx,ecx
	2593	resolve_link(DRCTOP, &link1); // skip1:
	2594	emit_mov_m64_r64(DRCTOP, MABS(&dmult_temp1), REG_EDX, REG_EAX); // mov [dmult_temp1],edx:eax
2574	2595
2575		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RTREG)); // mov edx:eax,[rtreg]
2576		_cmp_r32_imm(REG_EDX, 0); // cmp edx,0
2577		_jcc_short_link(COND_GE, &link2); // jge skip2
2578		_mov_r32_r32(REG_ECX, REG_EDX); // mov ecx,edx
2579		_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
2580		_neg_r32(REG_EAX); // neg eax
2581		_sbb_r32_r32(REG_EDX, REG_ECX); // sbb edx,ecx
2582		_resolve_link(&link2); // skip2:
2583		_mov_m64abs_r64(&dmult_temp2, REG_EDX, REG_EAX); // mov [dmult_temp2],edx:eax
	2596	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RTREG)); // mov edx:eax,[rtreg]
	2597	emit_cmp_r32_imm(DRCTOP, REG_EDX, 0); // cmp edx,0
	2598	emit_jcc_short_link(DRCTOP, COND_GE, &link2); // jge skip2
	2599	emit_mov_r32_r32(DRCTOP, REG_ECX, REG_EDX); // mov ecx,edx
	2600	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EDX); // xor edx,edx
	2601	emit_neg_r32(DRCTOP, REG_EAX); // neg eax
	2602	emit_sbb_r32_r32(DRCTOP, REG_EDX, REG_ECX); // sbb edx,ecx
	2603	resolve_link(DRCTOP, &link2); // skip2:
	2604	emit_mov_m64_r64(DRCTOP, MABS(&dmult_temp2), REG_EDX, REG_EAX); // mov [dmult_temp2],edx:eax
2584	2605
2585		_mov_r32_m32abs(REG_EAX, LO(&dmult_temp1)); // mov eax,[dmult_temp1].lo
2586		_mul_m32abs(LO(&dmult_temp2)); // mul [dmult_temp2].lo
2587		_mov_r32_r32(REG_ECX, REG_EDX); // mov ecx,edx
2588		_xor_r32_r32(REG_EBX, REG_EBX); // xor ebx,ebx
2589		_mov_m32abs_r32(LO(&mips3.core->lo), REG_EAX); // mov [lo].lo,eax
	2606	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(LO(&dmult_temp1))); // mov eax,[dmult_temp1].lo
	2607	emit_mul_m32(DRCTOP, MABS(LO(&dmult_temp2))); // mul [dmult_temp2].lo
	2608	emit_mov_r32_r32(DRCTOP, REG_ECX, REG_EDX); // mov ecx,edx
	2609	emit_xor_r32_r32(DRCTOP, REG_EBX, REG_EBX); // xor ebx,ebx
	2610	emit_mov_m32_r32(DRCTOP, LOADDRLO, REG_EAX); // mov [lo].lo,eax
2590	2611
2591		_mov_r32_m32abs(REG_EAX, HI(&dmult_temp1)); // mov eax,[dmult_temp1].hi
2592		_mul_m32abs(LO(&dmult_temp2)); // mul [dmult_temp2].lo
2593		_add_r32_r32(REG_ECX, REG_EAX); // add ecx,eax
2594		_adc_r32_r32(REG_EBX, REG_EDX); // adc ebx,edx
	2612	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(HI(&dmult_temp1))); // mov eax,[dmult_temp1].hi
	2613	emit_mul_m32(DRCTOP, MABS(LO(&dmult_temp2))); // mul [dmult_temp2].lo
	2614	emit_add_r32_r32(DRCTOP, REG_ECX, REG_EAX); // add ecx,eax
	2615	emit_adc_r32_r32(DRCTOP, REG_EBX, REG_EDX); // adc ebx,edx
2595	2616
2596		_mov_r32_m32abs(REG_EAX, LO(&dmult_temp1)); // mov eax,[dmult_temp1].lo
2597		_mul_m32abs(HI(&dmult_temp2)); // mul [dmult_temp2].hi
2598		_add_r32_r32(REG_ECX, REG_EAX); // add ecx,eax
2599		_adc_r32_r32(REG_EBX, REG_EDX); // adc ebx,edx
2600		_mov_m32abs_r32(HI(&mips3.core->lo), REG_ECX); // mov [lo].hi,ecx
	2617	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(LO(&dmult_temp1))); // mov eax,[dmult_temp1].lo
	2618	emit_mul_m32(DRCTOP, MABS(HI(&dmult_temp2))); // mul [dmult_temp2].hi
	2619	emit_add_r32_r32(DRCTOP, REG_ECX, REG_EAX); // add ecx,eax
	2620	emit_adc_r32_r32(DRCTOP, REG_EBX, REG_EDX); // adc ebx,edx
	2621	emit_mov_m32_r32(DRCTOP, LOADDRHI, REG_ECX); // mov [lo].hi,ecx
2601	2622
2602		_mov_r32_m32abs(REG_EAX, HI(&dmult_temp1)); // mov eax,[dmult_temp1].hi
2603		_mul_m32abs(HI(&dmult_temp2)); // mul [dmult_temp2].hi
2604		_add_r32_r32(REG_EBX, REG_EAX); // add ebx,eax
2605		_adc_r32_imm(REG_EDX, 0); // adc edx,0
2606		_mov_m32abs_r32(LO(&mips3.core->hi), REG_EBX); // mov [hi].lo,ebx
2607		_mov_m32abs_r32(HI(&mips3.core->hi), REG_EDX); // mov [hi].hi,edx
	2623	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(HI(&dmult_temp1))); // mov eax,[dmult_temp1].hi
	2624	emit_mul_m32(DRCTOP, MABS(HI(&dmult_temp2))); // mul [dmult_temp2].hi
	2625	emit_add_r32_r32(DRCTOP, REG_EBX, REG_EAX); // add ebx,eax
	2626	emit_adc_r32_imm(DRCTOP, REG_EDX, 0); // adc edx,0
	2627	emit_mov_m32_r32(DRCTOP, HIADDRLO, REG_EBX); // mov [hi].lo,ebx
	2628	emit_mov_m32_r32(DRCTOP, HIADDRHI, REG_EDX); // mov [hi].hi,edx
2608	2629
2609		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
2610		_xor_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // xor eax,[rtreg].hi
2611		_jcc_short_link(COND_NS, &link3); // jns noflip
2612		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
2613		_xor_r32_r32(REG_EBX, REG_EBX); // xor ebx,ebx
2614		_xor_r32_r32(REG_ECX, REG_ECX); // xor ecx,ecx
2615		_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
2616		_sub_r32_m32abs(REG_EAX, LO(&mips3.core->lo)); // sub eax,[lo].lo
2617		_sbb_r32_m32abs(REG_EBX, HI(&mips3.core->lo)); // sbb ebx,[lo].hi
2618		_sbb_r32_m32abs(REG_ECX, LO(&mips3.core->hi)); // sbb ecx,[hi].lo
2619		_sbb_r32_m32abs(REG_EDX, HI(&mips3.core->hi)); // sbb edx,[hi].hi
2620		_mov_m64abs_r64(&mips3.core->lo, REG_EBX, REG_EAX); // mov [lo],ebx:eax
2621		_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_ECX); // mov [lo],edx:ecx
2622		_resolve_link(&link3); // noflip:
	2630	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	2631	emit_xor_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // xor eax,[rtreg].hi
	2632	emit_jcc_short_link(DRCTOP, COND_NS, &link3); // jns noflip
	2633	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX); // xor eax,eax
	2634	emit_xor_r32_r32(DRCTOP, REG_EBX, REG_EBX); // xor ebx,ebx
	2635	emit_xor_r32_r32(DRCTOP, REG_ECX, REG_ECX); // xor ecx,ecx
	2636	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EDX); // xor edx,edx
	2637	emit_sub_r32_m32(DRCTOP, REG_EAX, MABS(LO(&mips3.core->lo))); // sub eax,[lo].lo
	2638	emit_sbb_r32_m32(DRCTOP, REG_EBX, MABS(HI(&mips3.core->lo))); // sbb ebx,[lo].hi
	2639	emit_sbb_r32_m32(DRCTOP, REG_ECX, MABS(LO(&mips3.core->hi))); // sbb ecx,[hi].lo
	2640	emit_sbb_r32_m32(DRCTOP, REG_EDX, MABS(HI(&mips3.core->hi))); // sbb edx,[hi].hi
	2641	emit_mov_m64_r64(DRCTOP, LOADDR, REG_EBX, REG_EAX); // mov [lo],ebx:eax
	2642	emit_mov_m64_r64(DRCTOP, HIADDR, REG_EDX, REG_ECX); // mov [hi],edx:ecx
	2643	resolve_link(DRCTOP, &link3); // noflip:
2623	2644	return RECOMPILE_SUCCESSFUL_CP(8,4);
2624	2645
2625	2646	case 0x1d: /* DMULTU */
2626		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
2627		_mul_m32bd(REG_ESI, REGDISP(RTREG)); // mul [rtreg].lo
2628		_mov_r32_r32(REG_ECX, REG_EDX); // mov ecx,edx
2629		_xor_r32_r32(REG_EBX, REG_EBX); // xor ebx,ebx
2630		_mov_m32abs_r32(LO(&mips3.core->lo), REG_EAX); // mov [lo].lo,eax
	2647	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2648	emit_mul_m32(DRCTOP, REGADDRLO(RTREG)); // mul [rtreg].lo
	2649	emit_mov_r32_r32(DRCTOP, REG_ECX, REG_EDX); // mov ecx,edx
	2650	emit_xor_r32_r32(DRCTOP, REG_EBX, REG_EBX); // xor ebx,ebx
	2651	emit_mov_m32_r32(DRCTOP, LOADDRLO, REG_EAX); // mov [lo].lo,eax
2631	2652
2632		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
2633		_mul_m32bd(REG_ESI, REGDISP(RTREG)); // mul [rtreg].lo
2634		_add_r32_r32(REG_ECX, REG_EAX); // add ecx,eax
2635		_adc_r32_r32(REG_EBX, REG_EDX); // adc ebx,edx
	2653	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	2654	emit_mul_m32(DRCTOP, REGADDRLO(RTREG)); // mul [rtreg].lo
	2655	emit_add_r32_r32(DRCTOP, REG_ECX, REG_EAX); // add ecx,eax
	2656	emit_adc_r32_r32(DRCTOP, REG_EBX, REG_EDX); // adc ebx,edx
2636	2657
2637		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
2638		_mul_m32bd(REG_ESI, REGDISP(RTREG)+4); // mul [rtreg].hi
2639		_add_r32_r32(REG_ECX, REG_EAX); // add ecx,eax
2640		_adc_r32_r32(REG_EBX, REG_EDX); // adc ebx,edx
2641		_mov_m32abs_r32(HI(&mips3.core->lo), REG_ECX); // mov [lo].hi,ecx
	2658	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2659	emit_mul_m32(DRCTOP, REGADDRHI(RTREG)); // mul [rtreg].hi
	2660	emit_add_r32_r32(DRCTOP, REG_ECX, REG_EAX); // add ecx,eax
	2661	emit_adc_r32_r32(DRCTOP, REG_EBX, REG_EDX); // adc ebx,edx
	2662	emit_mov_m32_r32(DRCTOP, LOADDRHI, REG_ECX); // mov [lo].hi,ecx
2642	2663
2643		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
2644		_mul_m32bd(REG_ESI, REGDISP(RTREG)+4); // mul [rtreg].hi
2645		_add_r32_r32(REG_EBX, REG_EAX); // add ebx,eax
2646		_adc_r32_imm(REG_EDX, 0); // adc edx,0
2647		_mov_m32abs_r32(LO(&mips3.core->hi), REG_EBX); // mov [hi].lo,ebx
2648		_mov_m32abs_r32(HI(&mips3.core->hi), REG_EDX); // mov [hi].hi,edx
	2664	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	2665	emit_mul_m32(DRCTOP, REGADDRHI(RTREG)); // mul [rtreg].hi
	2666	emit_add_r32_r32(DRCTOP, REG_EBX, REG_EAX); // add ebx,eax
	2667	emit_adc_r32_imm(DRCTOP, REG_EDX, 0); // adc edx,0
	2668	emit_mov_m32_r32(DRCTOP, HIADDRLO, REG_EBX); // mov [hi].lo,ebx
	2669	emit_mov_m32_r32(DRCTOP, HIADDRHI, REG_EDX); // mov [hi].hi,edx
2649	2670	return RECOMPILE_SUCCESSFUL_CP(8,4);
2650	2671
2651	2672	case 0x1e: /* DDIV */
2652		_sub_r32_imm(REG_ESP, 4); // sub esp,4
2653		_push_imm(&mips3.core->r[RTREG]); // push [rtreg]
2654		_push_imm(&mips3.core->r[RSREG]); // push [rsreg]
2655		_call((genf *)ddiv); // call ddiv
2656		_add_r32_imm(REG_ESP, 12); // add esp,12
	2673	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
	2674	emit_push_imm(DRCTOP, (FPTR)&mips3.core->r[RTREG]); // push [rtreg]
	2675	emit_push_imm(DRCTOP, (FPTR)&mips3.core->r[RSREG]); // push [rsreg]
	2676	emit_call(DRCTOP, (x86code *)ddiv); // call ddiv
	2677	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
2657	2678	return RECOMPILE_SUCCESSFUL_CP(68,4);
2658	2679
2659	2680	case 0x1f: /* DDIVU */
2660		_sub_r32_imm(REG_ESP, 4); // sub esp,4
2661		_push_imm(&mips3.core->r[RTREG]); // push [rtreg]
2662		_push_imm(&mips3.core->r[RSREG]); // push [rsreg]
2663		_call((genf *)ddivu); // call ddivu
2664		_add_r32_imm(REG_ESP, 12); // add esp,12
	2681	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
	2682	emit_push_imm(DRCTOP, (FPTR)&mips3.core->r[RTREG]); // push [rtreg]
	2683	emit_push_imm(DRCTOP, (FPTR)&mips3.core->r[RSREG]); // push [rsreg]
	2684	emit_call(DRCTOP, (x86code *)ddivu); // call ddivu
	2685	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
2665	2686	return RECOMPILE_SUCCESSFUL_CP(68,4);
2666	2687	}
2667	2688
2668		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	2689	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
2669	2690	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
2670	2691	}
2671	2692
2672	2693	static UINT32 recompile_special2(drc_core *drc, UINT32 pc, UINT32 op)
2673	2694	{
2674		link_info link1, link2, link3;
	2695	emit_link link1, link2, link3;
2675	2696
2676	2697	switch (op & 63)
2677	2698	{
2678	2699	case 0x20: /* ADD */
2679	2700	if (RSREG != 0 && RTREG != 0)
2680	2701	{
2681		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2682		_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg]
2683		_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
	2702	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2703	emit_add_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // add eax,[rtreg].lo
	2704	emit_jcc(DRCTOP, COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
2684	2705	if (RDREG != 0)
2685	2706	{
2686		_cdq(); // cdq
2687		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2707	emit_cdq(DRCTOP); // cdq
	2708	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2688	2709	}
2689	2710	}
2690	2711	else if (RDREG != 0)
2691	2712	{
2692	2713	if (RSREG != 0)
2693	2714	{
2694		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2695		_cdq(); // cdq
2696		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2715	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2716	emit_cdq(DRCTOP); // cdq
	2717	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2697	2718	}
2698	2719	else if (RTREG != 0)
2699	2720	{
2700		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg]
2701		_cdq(); // cdq
2702		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2721	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	2722	emit_cdq(DRCTOP); // cdq
	2723	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2703	2724	}
2704	2725	else
2705		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2726	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2706	2727	}
2707	2728	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
2708	2729
r949	r950
2711	2732	{
2712	2733	if (RSREG != 0 && RTREG != 0)
2713	2734	{
2714		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2715		_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg]
2716		_cdq(); // cdq
2717		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2735	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2736	emit_add_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // add eax,[rtreg].lo
	2737	emit_cdq(DRCTOP); // cdq
	2738	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2718	2739	}
2719	2740	else if (RSREG != 0)
2720	2741	{
2721		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2722		_cdq(); // cdq
2723		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2742	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2743	emit_cdq(DRCTOP); // cdq
	2744	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2724	2745	}
2725	2746	else if (RTREG != 0)
2726	2747	{
2727		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg]
2728		_cdq(); // cdq
2729		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2748	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	2749	emit_cdq(DRCTOP); // cdq
	2750	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2730	2751	}
2731	2752	else
2732		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2753	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2733	2754	}
2734	2755	return RECOMPILE_SUCCESSFUL_CP(1,4);
2735	2756
2736	2757	case 0x22: /* SUB */
2737	2758	if (RSREG != 0 && RTREG != 0)
2738	2759	{
2739		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2740		_sub_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // sub eax,[rtreg]
2741		_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
	2760	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2761	emit_sub_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // sub eax,[rtreg].lo
	2762	emit_jcc(DRCTOP, COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
2742	2763	if (RDREG != 0)
2743	2764	{
2744		_cdq(); // cdq
2745		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2765	emit_cdq(DRCTOP); // cdq
	2766	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2746	2767	}
2747	2768	}
2748	2769	else if (RDREG != 0)
2749	2770	{
2750	2771	if (RSREG != 0)
2751	2772	{
2752		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2753		_cdq(); // cdq
2754		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2773	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2774	emit_cdq(DRCTOP); // cdq
	2775	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2755	2776	}
2756	2777	else if (RTREG != 0)
2757	2778	{
2758		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg]
2759		_neg_r32(REG_EAX); // neg eax
2760		_cdq(); // cdq
2761		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2779	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	2780	emit_neg_r32(DRCTOP, REG_EAX); // neg eax
	2781	emit_cdq(DRCTOP); // cdq
	2782	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2762	2783	}
2763	2784	else
2764		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2785	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2765	2786	}
2766	2787	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
2767	2788
r949	r950
2770	2791	{
2771	2792	if (RSREG != 0 && RTREG != 0)
2772	2793	{
2773		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2774		_sub_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // sub eax,[rtreg]
2775		_cdq(); // cdq
2776		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2794	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2795	emit_sub_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // sub eax,[rtreg].lo
	2796	emit_cdq(DRCTOP); // cdq
	2797	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2777	2798	}
2778	2799	else if (RSREG != 0)
2779	2800	{
2780		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2781		_cdq(); // cdq
2782		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2801	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2802	emit_cdq(DRCTOP); // cdq
	2803	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2783	2804	}
2784	2805	else if (RTREG != 0)
2785	2806	{
2786		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg]
2787		_neg_r32(REG_EAX); // neg eax
2788		_cdq(); // cdq
2789		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2807	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	2808	emit_neg_r32(DRCTOP, REG_EAX); // neg eax
	2809	emit_cdq(DRCTOP); // cdq
	2810	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2790	2811	}
2791	2812	else
2792		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2813	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2793	2814	}
2794	2815	return RECOMPILE_SUCCESSFUL_CP(1,4);
2795	2816
r949	r950
2800	2821	{
2801	2822	if (USE_SSE)
2802	2823	{
2803		_movsd_r128_m64bd(REG_XMM0, REG_ESI, REGDISP(RSREG)); // movsd xmm0,[rsreg]
2804		_movsd_r128_m64bd(REG_XMM1, REG_ESI, REGDISP(RTREG)); // movsd xmm1,[rtreg]
2805		_pand_r128_r128(REG_XMM0, REG_XMM1); // pand xmm0,xmm1
2806		_movsd_m64bd_r128(REG_ESI, REGDISP(RDREG), REG_XMM0); // mov [rdreg],xmm0
	2824	emit_movsd_r128_m64(DRCTOP, REG_XMM0, REGADDR(RSREG)); // movsd xmm0,[rsreg]
	2825	emit_movsd_r128_m64(DRCTOP, REG_XMM1, REGADDR(RTREG)); // movsd xmm1,[rtreg]
	2826	emit_andpd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1); // andpd xmm0,xmm1
	2827	emit_movsd_m64_r128(DRCTOP, REGADDR(RDREG), REG_XMM0); // mov [rdreg],xmm0
2807	2828	}
2808	2829	else
2809	2830	{
2810		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
2811		_and_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // and eax,[rtreg].lo
2812		_and_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // and edx,[rtreg].hi
2813		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2831	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG));
	2832	// mov edx:eax,[rsreg]
	2833	emit_and_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // and eax,[rtreg].lo
	2834	emit_and_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // and edx,[rtreg].hi
	2835	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2814	2836	}
2815	2837	}
2816	2838	else
2817		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2839	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2818	2840	}
2819	2841	return RECOMPILE_SUCCESSFUL_CP(1,4);
2820	2842
r949	r950
2825	2847	{
2826	2848	if (USE_SSE)
2827	2849	{
2828		_movsd_r128_m64bd(REG_XMM0, REG_ESI, REGDISP(RSREG)); // movsd xmm0,[rsreg]
2829		_movsd_r128_m64bd(REG_XMM1, REG_ESI, REGDISP(RTREG)); // movsd xmm1,[rtreg]
2830		_por_r128_r128(REG_XMM0, REG_XMM1); // por xmm0,xmm1
2831		_movsd_m64bd_r128(REG_ESI, REGDISP(RDREG), REG_XMM0); // mov [rdreg],xmm0
	2850	emit_movsd_r128_m64(DRCTOP, REG_XMM0, REGADDR(RSREG)); // movsd xmm0,[rsreg]
	2851	emit_movsd_r128_m64(DRCTOP, REG_XMM1, REGADDR(RTREG)); // movsd xmm1,[rtreg]
	2852	emit_orpd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1); // orpd xmm0,xmm1
	2853	emit_movsd_m64_r128(DRCTOP, REGADDR(RDREG), REG_XMM0); // mov [rdreg],xmm0
2832	2854	}
2833	2855	else
2834	2856	{
2835		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
2836		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // or eax,[rtreg].lo
2837		_or_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // or edx,[rtreg].hi
2838		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2857	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG));
	2858	// mov edx:eax,[rsreg]
	2859	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // or eax,[rtreg].lo
	2860	emit_or_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // or edx,[rtreg].hi
	2861	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2839	2862	}
2840	2863	}
2841	2864	else if (RSREG != 0)
2842		_mov_m64bd_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG~~_ESI, REG~~D~~ISP~~(RSREG)); // mov [rdreg],[rsreg]
	2865	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RSREG)); // mov [rdreg],[rsreg]
2843	2866	else if (RTREG != 0)
2844		_mov_m64bd_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG~~_ESI, REG~~D~~ISP~~(RTREG)); // mov [rdreg],[rtreg]
	2867	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RTREG)); // mov [rdreg],[rtreg]
2845	2868	else
2846		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2869	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2847	2870	}
2848	2871	return RECOMPILE_SUCCESSFUL_CP(1,4);
2849	2872
r949	r950
2854	2877	{
2855	2878	if (USE_SSE)
2856	2879	{
2857		_movsd_r128_m64bd(REG_XMM0, REG_ESI, REGDISP(RSREG)); // movsd xmm0,[rsreg]
2858		_movsd_r128_m64bd(REG_XMM1, REG_ESI, REGDISP(RTREG)); // movsd xmm1,[rtreg]
2859		_pxor_r128_r128(REG_XMM0, REG_XMM1); // pxor xmm0,xmm1
2860		_movsd_m64bd_r128(REG_ESI, REGDISP(RDREG), REG_XMM0); // mov [rdreg],xmm0
	2880	emit_movsd_r128_m64(DRCTOP, REG_XMM0, REGADDR(RSREG)); // movsd xmm0,[rsreg]
	2881	emit_movsd_r128_m64(DRCTOP, REG_XMM1, REGADDR(RTREG)); // movsd xmm1,[rtreg]
	2882	emit_xorpd_r128_r128(DRCTOP, REG_XMM0, REG_XMM1); // xorpd xmm0,xmm1
	2883	emit_movsd_m64_r128(DRCTOP, REGADDR(RDREG), REG_XMM0); // mov [rdreg],xmm0
2861	2884	}
2862	2885	else
2863	2886	{
2864		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
2865		_xor_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // xor eax,[rtreg].lo
2866		_xor_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // xor edx,[rtreg].hi
2867		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2887	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG));
	2888	// mov edx:eax,[rsreg]
	2889	emit_xor_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // xor eax,[rtreg].lo
	2890	emit_xor_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // xor edx,[rtreg].hi
	2891	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2868	2892	}
2869	2893	}
2870	2894	else if (RSREG != 0)
2871		_mov_m64bd_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG~~_ESI, REG~~D~~ISP~~(RSREG)); // mov [rdreg],[rsreg]
	2895	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RSREG)); // mov [rdreg],[rsreg]
2872	2896	else if (RTREG != 0)
2873		_mov_m64bd_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG~~_ESI, REG~~D~~ISP~~(RTREG)); // mov [rdreg],[rtreg]
	2897	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RTREG)); // mov [rdreg],[rtreg]
2874	2898	else
2875		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2899	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2876	2900	}
2877	2901	return RECOMPILE_SUCCESSFUL_CP(1,4);
2878	2902
r949	r950
2881	2905	{
2882	2906	if (RSREG != 0 && RTREG != 0)
2883	2907	{
2884		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
2885		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // or eax,[rtreg].lo
2886		_or_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // or edx,[rtreg].hi
2887		_not_r32(REG_EDX); // not edx
2888		_not_r32(REG_EAX); // not eax
2889		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2908	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	2909	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // or eax,[rtreg].lo
	2910	emit_or_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // or edx,[rtreg].hi
	2911	emit_not_r32(DRCTOP, REG_EDX); // not edx
	2912	emit_not_r32(DRCTOP, REG_EAX); // not eax
	2913	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2890	2914	}
2891	2915	else if (RSREG != 0)
2892	2916	{
2893		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
2894		_not_r32(REG_EDX); // not edx
2895		_not_r32(REG_EAX); // not eax
2896		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2917	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	2918	emit_not_r32(DRCTOP, REG_EDX); // not edx
	2919	emit_not_r32(DRCTOP, REG_EAX); // not eax
	2920	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2897	2921	}
2898	2922	else if (RTREG != 0)
2899	2923	{
2900		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RTREG)); // mov edx:eax,[rtreg]
2901		_not_r32(REG_EDX); // not edx
2902		_not_r32(REG_EAX); // not eax
2903		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2924	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RTREG)); // mov edx:eax,[rtreg]
	2925	emit_not_r32(DRCTOP, REG_EDX); // not edx
	2926	emit_not_r32(DRCTOP, REG_EAX); // not eax
	2927	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2904	2928	}
2905	2929	else
2906	2930	{
2907		_mov_m32bd_imm(REG_ESI, REGDISP(RDREG), ~0); // mov [rtreg].lo,~0
2908		_mov_m32bd_imm(REG_ESI, REGDISP(RDREG)+4, ~0); // mov [rtreg].hi,~0
	2931	emit_mov_m32_imm(DRCTOP, REGADDRLO(RDREG), ~0); // mov [rtreg].lo,~0
	2932	emit_mov_m32_imm(DRCTOP, REGADDRHI(RDREG), ~0); // mov [rtreg].hi,~0
2909	2933	}
2910	2934	}
2911	2935	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
2914	2938	if (RDREG != 0)
2915	2939	{
2916	2940	if (RSREG != 0)
2917		_mov_r64_m64bd(REG_EDX, REG_EAX, REG~~_ESI, REG~~D~~ISP~~(RSREG)); // mov edx:eax,[rsreg]
	2941	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
2918	2942	else
2919	2943	{
2920		_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
2921		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
	2944	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EDX); // xor edx,edx
	2945	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX); // xor eax,eax
2922	2946	}
2923	2947	if (RTREG != 0)
2924	2948	{
2925		_sub_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // sub eax,[rtreg].lo
2926		_sbb_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // sbb edx,[rtreg].lo
	2949	emit_sub_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // sub eax,[rtreg].lo
	2950	emit_sbb_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // sbb edx,[rtreg].lo
2927	2951	}
2928		_shr_r32_imm(REG_EDX, 31); // shr edx,31
2929		_mov_m32bd_r32(REG_ESI, REGDISP(RDREG), REG_EDX); // mov [rdreg].lo,edx
2930		_mov_m32bd_imm(REG_ESI, REGDISP(RDREG)+4, 0); // mov [rdreg].hi,0
	2952	emit_shr_r32_imm(DRCTOP, REG_EDX, 31); // shr edx,31
	2953	emit_mov_m32_r32(DRCTOP, REGADDRLO(RDREG), REG_EDX); // mov [rdreg].lo,edx
	2954	emit_mov_m32_imm(DRCTOP, REGADDRHI(RDREG), 0); // mov [rdreg].hi,0
2931	2955	}
2932	2956	return RECOMPILE_SUCCESSFUL_CP(1,4);
2933	2957
2934	2958	case 0x2b: /* SLTU */
2935	2959	if (RDREG != 0)
2936	2960	{
2937		_xor_r32_r32(REG_ECX, REG_ECX); // xor ecx,ecx
2938		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
2939		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // cmp eax,[rtreg].hi
2940		_jcc_short_link(COND_B, &link1); // jb setit
2941		_jcc_short_link(COND_A, &link2); // ja skipit
2942		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
2943		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
2944		_jcc_short_link(COND_AE, &link3); // jae skipit
2945		_resolve_link(&link1); // setit:
2946		_add_r32_imm(REG_ECX, 1); // add ecx,1
2947		_resolve_link(&link2); // skipit:
2948		_resolve_link(&link3); // skipit:
2949		_mov_m32bd_r32(REG_ESI, REGDISP(RDREG), REG_ECX); // mov [rdreg].lo,ecx
2950		_mov_m32bd_imm(REG_ESI, REGDISP(RDREG)+4, 0); // mov [rdreg].hi,0
	2961	emit_xor_r32_r32(DRCTOP, REG_ECX, REG_ECX); // xor ecx,ecx
	2962	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	2963	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // cmp eax,[rtreg].hi
	2964	emit_jcc_short_link(DRCTOP, COND_B, &link1); // jb setit
	2965	emit_jcc_short_link(DRCTOP, COND_A, &link2); // ja skipit
	2966	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	2967	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // cmp eax,[rtreg].lo
	2968	emit_jcc_short_link(DRCTOP, COND_AE, &link3); // jae skipit
	2969	resolve_link(DRCTOP, &link1); // setit:
	2970	emit_add_r32_imm(DRCTOP, REG_ECX, 1); // add ecx,1
	2971	resolve_link(DRCTOP, &link2); // skipit:
	2972	resolve_link(DRCTOP, &link3); // skipit:
	2973	emit_mov_m32_r32(DRCTOP, REGADDRLO(RDREG), REG_ECX); // mov [rdreg].lo,ecx
	2974	emit_mov_m32_imm(DRCTOP, REGADDRHI(RDREG), 0); // mov [rdreg].hi,0
2951	2975	}
2952	2976	return RECOMPILE_SUCCESSFUL_CP(1,4);
2953	2977
2954	2978	case 0x2c: /* DADD */
2955	2979	if (RSREG != 0 && RTREG != 0)
2956	2980	{
2957		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
2958		_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg].lo
2959		_adc_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // adc edx,[rtreg].hi
2960		_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
	2981	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	2982	emit_add_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // add eax,[rtreg].lo
	2983	emit_adc_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // adc edx,[rtreg].hi
	2984	emit_jcc(DRCTOP, COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
2961	2985	if (RDREG != 0)
2962		_mov_m64bd_r64(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	2986	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2963	2987	}
2964	2988	else if (RDREG != 0)
2965	2989	{
2966	2990	if (RSREG != 0)
2967		_mov_m64bd_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG~~_ESI, REG~~D~~ISP~~(RSREG)); // mov [rdreg],[rsreg]
	2991	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RSREG)); // mov [rdreg],[rsreg]
2968	2992	else if (RTREG != 0)
2969		_mov_m64bd_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG~~_ESI, REG~~D~~ISP~~(RTREG)); // mov [rdreg],[rtreg]
	2993	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RTREG)); // mov [rdreg],[rtreg]
2970	2994	else
2971		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	2995	emit_zero_m64(DRCTOP, REGADDR(RDREG));
2972	2996	}
2973	2997	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
2974	2998
r949	r950
2977	3001	{
2978	3002	if (RSREG != 0 && RTREG != 0)
2979	3003	{
2980		if (USE_SSE)
2981		{
2982		_movsd_r128_m64bd(REG_XMM0, REG_ESI, REGDISP(RSREG)); // movsd xmm0,[rsreg]
2983		_movsd_r128_m64bd(REG_XMM1, REG_ESI, REGDISP(RTREG)); // movsd xmm1,[rtreg]
2984		_paddq_r128_r128(REG_XMM0, REG_XMM1); // paddq xmm0,xmm1
2985		_movsd_m64bd_r128(REG_ESI, REGDISP(RDREG), REG_XMM0); // mov [rdreg],xmm0
2986		}
2987		else
2988		{
2989		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
2990		_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg].lo
2991		_adc_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // adc edx,[rtreg].hi
2992		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2993		}
	3004	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	3005	emit_add_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // add eax,[rtreg].lo
	3006	emit_adc_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // adc edx,[rtreg].hi
	3007	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2994	3008	}
2995	3009	else if (RSREG != 0)
2996		_mov_m64bd_m64bd(REG_ESI, REGDISP(RDREG), REG_ESI, REGDISP(RSREG)); // mov [rdreg],[rsreg]
	3010	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RSREG));
	3011	// mov [rdreg],[rsreg]
2997	3012	else if (RTREG != 0)
2998		_mov_m64bd_m64bd(REG_ESI, REGDISP(RDREG), REG_ESI, REGDISP(RTREG)); // mov [rdreg],[rtreg]
	3013	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RTREG));
	3014	// mov [rdreg],[rtreg]
2999	3015	else
3000		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	3016	emit_zero_m64(DRCTOP, REGADDR(RDREG));
3001	3017	}
3002	3018	return RECOMPILE_SUCCESSFUL_CP(1,4);
3003	3019
3004	3020	case 0x2e: /* DSUB */
3005	3021	if (RSREG != 0 && RTREG != 0)
3006	3022	{
3007		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
3008		_sub_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // sub eax,[rtreg].lo
3009		_sbb_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // sbb edx,[rtreg].hi
3010		_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
	3023	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	3024	emit_sub_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // sub eax,[rtreg].lo
	3025	emit_sbb_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // sbb edx,[rtreg].hi
	3026	emit_jcc(DRCTOP, COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
3011	3027	if (RDREG != 0)
3012		_mov_m64bd_r64(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	3028	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3013	3029	}
3014	3030	else if (RDREG != 0)
3015	3031	{
3016	3032	if (RSREG != 0)
3017		_mov_m64bd_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG~~_ESI, REG~~D~~ISP~~(RSREG)); // mov [rdreg],[rsreg]
	3033	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RSREG)); // mov [rdreg],[rsreg]
3018	3034	else if (RTREG != 0)
3019	3035	{
3020		if (USE_SSE)
3021		{
3022		_pxor_r128_r128(REG_XMM0, REG_XMM0); // pxor xmm0,xmm0
3023		_movsd_r128_m64bd(REG_XMM1, REG_ESI, REGDISP(RTREG)); // movsd xmm1,[rtreg]
3024		_psubq_r128_r128(REG_XMM0, REG_XMM1); // psubq xmm0,xmm1
3025		_movsd_m64bd_r128(REG_ESI, REGDISP(RDREG), REG_XMM0); // mov [rdreg],xmm0
3026		}
3027		else
3028		{
3029		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
3030		_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
3031		_sub_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // sub eax,[rtreg].lo
3032		_sbb_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // sbb edx,[rtreg].hi
3033		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3034		}
	3036	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX); // xor eax,eax
	3037	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EDX); // xor edx,edx
	3038	emit_sub_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // sub eax,[rtreg].lo
	3039	emit_sbb_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // sbb edx,[rtreg].hi
	3040	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3035	3041	}
3036	3042	else
3037		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	3043	emit_zero_m64(DRCTOP, REGADDR(RDREG));
3038	3044	}
3039	3045	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3040	3046
r949	r950
3043	3049	{
3044	3050	if (RSREG != 0 && RTREG != 0)
3045	3051	{
3046		if (USE_SSE)
3047		{
3048		_movsd_r128_m64bd(REG_XMM0, REG_ESI, REGDISP(RSREG)); // movsd xmm0,[rsreg]
3049		_movsd_r128_m64bd(REG_XMM1, REG_ESI, REGDISP(RTREG)); // movsd xmm1,[rtreg]
3050		_psubq_r128_r128(REG_XMM0, REG_XMM1); // psubq xmm0,xmm1
3051		_movsd_m64bd_r128(REG_ESI, REGDISP(RDREG), REG_XMM0); // mov [rdreg],xmm0
3052		}
3053		else
3054		{
3055		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
3056		_sub_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // sub eax,[rtreg].lo
3057		_sbb_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // sbb edx,[rtreg].hi
3058		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3059		}
	3052	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	3053	emit_sub_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // sub eax,[rtreg].lo
	3054	emit_sbb_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // sbb edx,[rtreg].hi
	3055	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3060	3056	}
3061	3057	else if (RSREG != 0)
3062		_mov_m64bd_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG~~_ESI, REG~~D~~ISP~~(RSREG)); // mov [rdreg],[rsreg]
	3058	emit_mov_m64_m64(DRCTOP, REGADDR(RDREG), REGADDR(RSREG)); // mov [rdreg],[rsreg]
3063	3059	else if (RTREG != 0)
3064	3060	{
3065		if (USE_SSE)
3066		{
3067		_pxor_r128_r128(REG_XMM0, REG_XMM0); // pxor xmm0,xmm0
3068		_movsd_r128_m64bd(REG_XMM1, REG_ESI, REGDISP(RTREG)); // movsd xmm1,[rtreg]
3069		_psubq_r128_r128(REG_XMM0, REG_XMM1); // psubq xmm0,xmm1
3070		_movsd_m64bd_r128(REG_ESI, REGDISP(RDREG), REG_XMM0); // mov [rdreg],xmm0
3071		}
3072		else
3073		{
3074		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
3075		_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
3076		_sub_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // sub eax,[rtreg].lo
3077		_sbb_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // sbb edx,[rtreg].hi
3078		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3079		}
	3061	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX); // xor eax,eax
	3062	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EDX); // xor edx,edx
	3063	emit_sub_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // sub eax,[rtreg].lo
	3064	emit_sbb_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // sbb edx,[rtreg].hi
	3065	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3080	3066	}
3081	3067	else
3082		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	3068	emit_zero_m64(DRCTOP, REGADDR(RDREG));
3083	3069	}
3084	3070	return RECOMPILE_SUCCESSFUL_CP(1,4);
3085	3071
3086	3072	case 0x30: /* TGE */
3087	3073	if (RSREG != 0)
3088		_mov_r64_m64bd(REG_EDX, REG_EAX, REG~~_ESI, REG~~D~~ISP~~(RSREG)); // mov edx:eax,[rsreg]
	3074	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
3089	3075	else
3090	3076	{
3091		_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
3092		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
	3077	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EDX); // xor edx,edx
	3078	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX); // xor eax,eax
3093	3079	}
3094	3080	if (RTREG != 0)
3095	3081	{
3096		_sub_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // sub eax,[rtreg].lo
3097		_sbb_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // sbb edx,[rtreg].hi
	3082	emit_sub_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // sub eax,[rtreg].lo
	3083	emit_sbb_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // sbb edx,[rtreg].hi
3098	3084	}
3099	3085	else
3100		_cmp_r32_imm(REG_EDX, 0); // cmp edx,0
3101		_jcc(COND_GE, mips3.drcdata->generate_trap_exception); // jge generate_trap_exception
	3086	emit_cmp_r32_imm(DRCTOP, REG_EDX, 0); // cmp edx,0
	3087	emit_jcc(DRCTOP, COND_GE, mips3.drcdata->generate_trap_exception); // jge generate_trap_exception
3102	3088	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3103	3089
3104	3090	case 0x31: /* TGEU */
3105		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
3106		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // cmp eax,[rtreg].hi
3107		_jcc(COND_A, mips3.drcdata->generate_trap_exception); // ja generate_trap_exception
3108		_jcc_short_link(COND_B, &link1); // jb skipit
3109		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
3110		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
3111		_jcc(COND_AE, mips3.drcdata->generate_trap_exception); // jae generate_trap_exception
3112		_resolve_link(&link1); // skipit:
	3091	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	3092	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // cmp eax,[rtreg].hi
	3093	emit_jcc(DRCTOP, COND_A, mips3.drcdata->generate_trap_exception); // ja generate_trap_exception
	3094	emit_jcc_short_link(DRCTOP, COND_B, &link1); // jb skipit
	3095	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	3096	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // cmp eax,[rtreg].lo
	3097	emit_jcc(DRCTOP, COND_AE, mips3.drcdata->generate_trap_exception); // jae generate_trap_exception
	3098	resolve_link(DRCTOP, &link1); // skipit:
3113	3099	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3114	3100
3115	3101	case 0x32: /* TLT */
3116	3102	if (RSREG != 0)
3117		_mov_r64_m64bd(REG_EDX, REG_EAX, REG~~_ESI, REG~~D~~ISP~~(RSREG)); // mov edx:eax,[rsreg]
	3103	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
3118	3104	else
3119	3105	{
3120		_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
3121		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
	3106	emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EDX); // xor edx,edx
	3107	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX); // xor eax,eax
3122	3108	}
3123	3109	if (RTREG != 0)
3124	3110	{
3125		_sub_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // sub eax,[rtreg].lo
3126		_sbb_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // sbb edx,[rtreg].hi
	3111	emit_sub_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // sub eax,[rtreg].lo
	3112	emit_sbb_r32_m32(DRCTOP, REG_EDX, REGADDRHI(RTREG)); // sbb edx,[rtreg].hi
3127	3113	}
3128	3114	else
3129		_cmp_r32_imm(REG_EDX, 0); // cmp edx,0
3130		_jcc(COND_L, mips3.drcdata->generate_trap_exception); // jl generate_trap_exception
	3115	emit_cmp_r32_imm(DRCTOP, REG_EDX, 0); // cmp edx,0
	3116	emit_jcc(DRCTOP, COND_L, mips3.drcdata->generate_trap_exception); // jl generate_trap_exception
3131	3117	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3132	3118
3133	3119	case 0x33: /* TLTU */
3134		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
3135		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // cmp eax,[rtreg].hi
3136		_jcc(COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
3137		_jcc_short_link(COND_A, &link1); // ja skipit
3138		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
3139		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
3140		_jcc(COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
3141		_resolve_link(&link1); // skipit:
	3120	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	3121	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // cmp eax,[rtreg].hi
	3122	emit_jcc(DRCTOP, COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
	3123	emit_jcc_short_link(DRCTOP, COND_A, &link1); // ja skipit
	3124	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	3125	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // cmp eax,[rtreg].lo
	3126	emit_jcc(DRCTOP, COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
	3127	resolve_link(DRCTOP, &link1); // skipit:
3142	3128	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3143	3129
3144	3130	case 0x34: /* TEQ */
3145		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
3146		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // cmp eax,[rtreg].hi
3147		_jcc_short_link(COND_NE, &link1); // jne skipit
3148		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
3149		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
3150		_jcc(COND_E, mips3.drcdata->generate_trap_exception); // je generate_trap_exception
3151		_resolve_link(&link1); // skipit:
	3131	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	3132	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // cmp eax,[rtreg].hi
	3133	emit_jcc_short_link(DRCTOP, COND_NE, &link1); // jne skipit
	3134	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	3135	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // cmp eax,[rtreg].lo
	3136	emit_jcc(DRCTOP, COND_E, mips3.drcdata->generate_trap_exception); // je generate_trap_exception
	3137	resolve_link(DRCTOP, &link1); // skipit:
3152	3138	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3153	3139
3154	3140	case 0x36: /* TNE */
3155		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
3156		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // cmp eax,[rtreg].hi
3157		_jcc_short_link(COND_E, &link1); // je skipit
3158		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
3159		_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
3160		_jcc(COND_NE, mips3.drcdata->generate_trap_exception); // jne generate_trap_exception
3161		_resolve_link(&link1); // skipit:
	3141	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RSREG)); // mov eax,[rsreg].hi
	3142	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // cmp eax,[rtreg].hi
	3143	emit_jcc_short_link(DRCTOP, COND_E, &link1); // je skipit
	3144	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg].lo
	3145	emit_cmp_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // cmp eax,[rtreg].lo
	3146	emit_jcc(DRCTOP, COND_NE, mips3.drcdata->generate_trap_exception); // jne generate_trap_exception
	3147	resolve_link(DRCTOP, &link1); // skipit:
3162	3148	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3163	3149
3164	3150	case 0x38: /* DSLL */
r949	r950
3166	3152	{
3167	3153	if (RTREG != 0)
3168	3154	{
3169		if (USE_SSE)
	3155	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RTREG)); // mov edx:eax,[rtreg]
	3156	if (SHIFT != 0)
3170	3157	{
3171		_movsd_r128_m64bd(REG_XMM0, REG_ESI, REGDISP(RTREG)); // movsd xmm0,[rtreg]
3172		if (SHIFT)
3173		_psllq_r128_imm(REG_XMM0, SHIFT); // psllq xmm0,SHIFT
3174		_movsd_m64bd_r128(REG_ESI, REGDISP(RDREG), REG_XMM0); // movsd [rdreg],xmm0
	3158	emit_shld_r32_r32_imm(DRCTOP, REG_EDX, REG_EAX, SHIFT); // shld edx,eax,SHIFT
	3159	emit_shl_r32_imm(DRCTOP, REG_EAX, SHIFT); // shl eax,SHIFT
3175	3160	}
3176		else
3177		{
3178		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RTREG)); // mov edx:eax,[rtreg]
3179		if (SHIFT != 0)
3180		{
3181		_shld_r32_r32_imm(REG_EDX, REG_EAX, SHIFT); // shld edx,eax,SHIFT
3182		_shl_r32_imm(REG_EAX, SHIFT); // shl eax,SHIFT
3183		}
3184		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3185		}
	3161	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3186	3162	}
3187	3163	else
3188		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	3164	emit_zero_m64(DRCTOP, REGADDR(RDREG));
3189	3165	}
3190	3166	return RECOMPILE_SUCCESSFUL_CP(1,4);
3191	3167
r949	r950
3194	3170	{
3195	3171	if (RTREG != 0)
3196	3172	{
3197		if (USE_SSE)
	3173	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RTREG)); // mov edx:eax,[rtreg]
	3174	if (SHIFT != 0)
3198	3175	{
3199		_movsd_r128_m64bd(REG_XMM0, REG_ESI, REGDISP(RTREG)); // movsd xmm0,[rtreg]
3200		if (SHIFT)
3201		_psrlq_r128_imm(REG_XMM0, SHIFT); // psrlq xmm0,SHIFT
3202		_movsd_m64bd_r128(REG_ESI, REGDISP(RDREG), REG_XMM0); // movsd [rdreg],xmm0
	3176	emit_shrd_r32_r32_imm(DRCTOP, REG_EAX, REG_EDX, SHIFT); // shrd eax,edx,SHIFT
	3177	emit_shr_r32_imm(DRCTOP, REG_EDX, SHIFT); // shr edx,SHIFT
3203	3178	}
3204		else
3205		{
3206		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RTREG)); // mov edx:eax,[rtreg]
3207		if (SHIFT != 0)
3208		{
3209		_shrd_r32_r32_imm(REG_EAX, REG_EDX, SHIFT); // shrd eax,edx,SHIFT
3210		_shr_r32_imm(REG_EDX, SHIFT); // shr edx,SHIFT
3211		}
3212		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3213		}
	3179	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3214	3180	}
3215	3181	else
3216		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	3182	emit_zero_m64(DRCTOP, REGADDR(RDREG));
3217	3183	}
3218	3184	return RECOMPILE_SUCCESSFUL_CP(1,4);
3219	3185
r949	r950
3222	3188	{
3223	3189	if (RTREG != 0)
3224	3190	{
3225		_mov_r64_m64bd(REG_EDX, REG_EAX, REG~~_ESI, REG~~D~~ISP~~(RTREG)); // mov edx:eax,[rtreg]
	3191	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RTREG)); // mov edx:eax,[rtreg]
3226	3192	if (SHIFT != 0)
3227	3193	{
3228		_shrd_r32_r32_imm(REG_EAX, REG_EDX, SHIFT); // shrd eax,edx,SHIFT
3229		_sar_r32_imm(REG_EDX, SHIFT); // sar edx,SHIFT
	3194	emit_shrd_r32_r32_imm(DRCTOP, REG_EAX, REG_EDX, SHIFT); // shrd eax,edx,SHIFT
	3195	emit_sar_r32_imm(DRCTOP, REG_EDX, SHIFT); // sar edx,SHIFT
3230	3196	}
3231		_mov_m64bd_r64(R~~EG_ESI~~, REGD~~ISP~~(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	3197	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3232	3198	}
3233	3199	else
3234		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	3200	emit_zero_m64(DRCTOP, REGADDR(RDREG));
3235	3201	}
3236	3202	return RECOMPILE_SUCCESSFUL_CP(1,4);
3237	3203
r949	r950
3240	3206	{
3241	3207	if (RTREG != 0)
3242	3208	{
3243		if (USE_SSE)
3244		{
3245		_movsd_r128_m64bd(REG_XMM0, REG_ESI, REGDISP(RTREG)); // movsd xmm0,[rtreg]
3246		_psllq_r128_imm(REG_XMM0, SHIFT+32); // psllq xmm0,SHIFT+32
3247		_movsd_m64bd_r128(REG_ESI, REGDISP(RDREG), REG_XMM0); // movsd [rdreg],xmm0
3248		}
3249		else
3250		{
3251		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg].lo
3252		if (SHIFT != 0)
3253		_shl_r32_imm(REG_EAX, SHIFT); // shl eax,SHIFT
3254		_mov_m32bd_imm(REG_ESI, REGDISP(RDREG), 0); // mov [rdreg].lo,0
3255		_mov_m32bd_r32(REG_ESI, REGDISP(RDREG)+4, REG_EAX); // mov [rdreg].hi,eax
3256		}
	3209	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	3210	if (SHIFT != 0)
	3211	emit_shl_r32_imm(DRCTOP, REG_EAX, SHIFT); // shl eax,SHIFT
	3212	emit_mov_m32_imm(DRCTOP, REGADDRLO(RDREG), 0); // mov [rdreg].lo,0
	3213	emit_mov_m32_r32(DRCTOP, REGADDRHI(RDREG), REG_EAX); // mov [rdreg].hi,eax
3257	3214	}
3258	3215	else
3259		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	3216	emit_zero_m64(DRCTOP, REGADDR(RDREG));
3260	3217	}
3261	3218	return RECOMPILE_SUCCESSFUL_CP(1,4);
3262	3219
r949	r950
3265	3222	{
3266	3223	if (RTREG != 0)
3267	3224	{
3268		if (USE_SSE)
3269		{
3270		_movsd_r128_m64bd(REG_XMM0, REG_ESI, REGDISP(RTREG)); // movsd xmm0,[rtreg]
3271		_psrlq_r128_imm(REG_XMM0, SHIFT+32); // psrlq xmm0,SHIFT+32
3272		_movsd_m64bd_r128(REG_ESI, REGDISP(RDREG), REG_XMM0); // movsd [rdreg],xmm0
3273		}
3274		else
3275		{
3276		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // mov eax,[rtreg].hi
3277		if (SHIFT != 0)
3278		_shr_r32_imm(REG_EAX, SHIFT); // shr eax,SHIFT
3279		_mov_m32bd_imm(REG_ESI, REGDISP(RDREG)+4, 0); // mov [rdreg].hi,0
3280		_mov_m32bd_r32(REG_ESI, REGDISP(RDREG), REG_EAX); // mov [rdreg].lo,eax
3281		}
	3225	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // mov eax,[rtreg].hi
	3226	if (SHIFT != 0)
	3227	emit_shr_r32_imm(DRCTOP, REG_EAX, SHIFT); // shr eax,SHIFT
	3228	emit_mov_m32_imm(DRCTOP, REGADDRHI(RDREG), 0); // mov [rdreg].hi,0
	3229	emit_mov_m32_r32(DRCTOP, REGADDRLO(RDREG), REG_EAX); // mov [rdreg].lo,eax
3282	3230	}
3283	3231	else
3284		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	3232	emit_zero_m64(DRCTOP, REGADDR(RDREG));
3285	3233	}
3286	3234	return RECOMPILE_SUCCESSFUL_CP(1,4);
3287	3235
r949	r950
3290	3238	{
3291	3239	if (RTREG != 0)
3292	3240	{
3293		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // mov eax,[rtreg].hi
3294		_cdq(); // cdq
	3241	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // mov eax,[rtreg].hi
	3242	emit_cdq(DRCTOP); // cdq
3295	3243	if (SHIFT != 0)
3296		_sar_r32_imm(REG_EAX, SHIFT); // sar eax,SHIFT
3297		_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
	3244	emit_sar_r32_imm(DRCTOP, REG_EAX, SHIFT); // sar eax,SHIFT
	3245	emit_mov_m64_r64(DRCTOP, REGADDR(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3298	3246	}
3299	3247	else
3300		_zero_m64bd(R~~EG_ESI~~, REGD~~ISP~~(RDREG));
	3248	emit_zero_m64(DRCTOP, REGADDR(RDREG));
3301	3249	}
3302	3250	return RECOMPILE_SUCCESSFUL_CP(1,4);
3303	3251	}
3304	3252
3305		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	3253	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
3306	3254	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
3307	3255	}
3308	3256
r949	r950
3322	3270
3323	3271	static UINT32 recompile_regimm(drc_core *drc, UINT32 pc, UINT32 op)
3324	3272	{
3325		link_info link1;
	3273	emit_link link1;
3326	3274	int cycles;
3327	3275
3328	3276	switch (RTREG)
r949	r950
3332	3280	return RECOMPILE_SUCCESSFUL_CP(1,4);
3333	3281	else
3334	3282	{
3335		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
3336		_jcc_near_link(COND_GE, &link1); // jge skip
	3283	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	3284	emit_jcc_near_link(DRCTOP, COND_GE, &link1); // jge skip
3337	3285	}
3338	3286
3339		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3340		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3341		_resolve_link(&link1); // skip:
	3287	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3288	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3289	resolve_link(DRCTOP, &link1); // skip:
3342	3290	return RECOMPILE_SUCCESSFUL_CP(1,4);
3343	3291
3344	3292	case 0x01: /* BGEZ */
3345	3293	if (RSREG == 0)
3346	3294	{
3347		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3348		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3295	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3296	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3349	3297	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
3350	3298	}
3351	3299	else
3352	3300	{
3353		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
3354		_jcc_near_link(COND_L, &link1); // jl skip
	3301	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	3302	emit_jcc_near_link(DRCTOP, COND_L, &link1); // jl skip
3355	3303	}
3356	3304
3357		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3358		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3359		_resolve_link(&link1); // skip:
	3305	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3306	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3307	resolve_link(DRCTOP, &link1); // skip:
3360	3308	return RECOMPILE_SUCCESSFUL_CP(1,4);
3361	3309
3362	3310	case 0x02: /* BLTZL */
r949	r950
3364	3312	return RECOMPILE_SUCCESSFUL_CP(1,4);
3365	3313	else
3366	3314	{
3367		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
3368		_jcc_near_link(COND_GE, &link1); // jge skip
	3315	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	3316	emit_jcc_near_link(DRCTOP, COND_GE, &link1); // jge skip
3369	3317	}
3370	3318
3371		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3372		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3373		_resolve_link(&link1); // skip:
	3319	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3320	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3321	resolve_link(DRCTOP, &link1); // skip:
3374	3322	return RECOMPILE_SUCCESSFUL_CP(1,8);
3375	3323
3376	3324	case 0x03: /* BGEZL */
3377	3325	if (RSREG == 0)
3378	3326	{
3379		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3380		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3327	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3328	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3381	3329	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
3382	3330	}
3383	3331	else
3384	3332	{
3385		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
3386		_jcc_near_link(COND_L, &link1); // jl skip
	3333	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	3334	emit_jcc_near_link(DRCTOP, COND_L, &link1); // jl skip
3387	3335	}
3388	3336
3389		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3390		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3391		_resolve_link(&link1); // skip:
	3337	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3338	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3339	resolve_link(DRCTOP, &link1); // skip:
3392	3340	return RECOMPILE_SUCCESSFUL_CP(1,8);
3393	3341
3394	3342	case 0x08: /* TGEI */
3395	3343	if (RSREG != 0)
3396	3344	{
3397		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
3398		_sub_r32_imm(REG_EAX, SIMMVAL); // sub eax,[rtreg].lo
3399		_sbb_r32_imm(REG_EDX, ((INT32)SIMMVAL >> 31)); // sbb edx,[rtreg].lo
3400		_jcc(COND_GE, mips3.drcdata->generate_trap_exception); // jge generate_trap_exception
	3345	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	3346	emit_sub_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // sub eax,[rtreg].lo
	3347	emit_sbb_r32_imm(DRCTOP, REG_EDX, ((INT32)SIMMVAL >> 31)); // sbb edx,[rtreg].lo
	3348	emit_jcc(DRCTOP, COND_GE, mips3.drcdata->generate_trap_exception); // jge generate_trap_exception
3401	3349	}
3402	3350	else
3403	3351	{
3404	3352	if (0 >= SIMMVAL)
3405		_jmp(mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
	3353	emit_jmp(DRCTOP, mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
3406	3354	}
3407	3355	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3408	3356
3409	3357	case 0x09: /* TGEIU */
3410	3358	if (RSREG != 0)
3411	3359	{
3412		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, ((INT32)SIMMVAL >> 31)); // cmp [rsreg].hi,upper
3413		_jcc(COND_A, mips3.drcdata->generate_trap_exception); // ja generate_trap_exception
3414		_jcc_short_link(COND_B, &link1); // jb skip
3415		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
3416		_jcc(COND_AE, mips3.drcdata->generate_trap_exception); // jae generate_trap_exception
3417		_resolve_link(&link1); // skip:
	3360	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), ((INT32)SIMMVAL >> 31));
	3361	// cmp [rsreg].hi,upper
	3362	emit_jcc(DRCTOP, COND_A, mips3.drcdata->generate_trap_exception); // ja generate_trap_exception
	3363	emit_jcc_short_link(DRCTOP, COND_B, &link1); // jb skip
	3364	emit_cmp_m32_imm(DRCTOP, REGADDRLO(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
	3365	emit_jcc(DRCTOP, COND_AE, mips3.drcdata->generate_trap_exception); // jae generate_trap_exception
	3366	resolve_link(DRCTOP, &link1); // skip:
3418	3367	}
3419	3368	else
3420	3369	{
3421	3370	if (0 >= SIMMVAL)
3422		_jmp(mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
	3371	emit_jmp(DRCTOP, mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
3423	3372	}
3424	3373	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3425	3374
3426	3375	case 0x0a: /* TLTI */
3427	3376	if (RSREG != 0)
3428	3377	{
3429		_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
3430		_sub_r32_imm(REG_EAX, SIMMVAL); // sub eax,[rtreg].lo
3431		_sbb_r32_imm(REG_EDX, ((INT32)SIMMVAL >> 31)); // sbb edx,[rtreg].lo
3432		_jcc(COND_L, mips3.drcdata->generate_trap_exception); // jl generate_trap_exception
	3378	emit_mov_r64_m64(DRCTOP, REG_EDX, REG_EAX, REGADDR(RSREG)); // mov edx:eax,[rsreg]
	3379	emit_sub_r32_imm(DRCTOP, REG_EAX, SIMMVAL); // sub eax,[rtreg].lo
	3380	emit_sbb_r32_imm(DRCTOP, REG_EDX, ((INT32)SIMMVAL >> 31)); // sbb edx,[rtreg].lo
	3381	emit_jcc(DRCTOP, COND_L, mips3.drcdata->generate_trap_exception); // jl generate_trap_exception
3433	3382	}
3434	3383	else
3435	3384	{
3436	3385	if (0 < SIMMVAL)
3437		_jmp(mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
	3386	emit_jmp(DRCTOP, mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
3438	3387	}
3439	3388	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3440	3389
3441	3390	case 0x0b: /* TLTIU */
3442	3391	if (RSREG != 0)
3443	3392	{
3444		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, ((INT32)SIMMVAL >> 31)); // cmp [rsreg].hi,upper
3445		_jcc(COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
3446		_jcc_short_link(COND_A, &link1); // ja skip
3447		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
3448		_jcc(COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
3449		_resolve_link(&link1); // skip:
	3393	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), ((INT32)SIMMVAL >> 31));
	3394	// cmp [rsreg].hi,upper
	3395	emit_jcc(DRCTOP, COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
	3396	emit_jcc_short_link(DRCTOP, COND_A, &link1); // ja skip
	3397	emit_cmp_m32_imm(DRCTOP, REGADDRLO(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
	3398	emit_jcc(DRCTOP, COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
	3399	resolve_link(DRCTOP, &link1); // skip:
3450	3400	}
3451	3401	else
3452	3402	{
3453		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG), (0 < SIMMVAL)); // mov [rtreg].lo,const
3454		_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,sign-extend(const)
	3403	emit_mov_m32_imm(DRCTOP, REGADDRLO(RTREG), (0 < SIMMVAL)); // mov [rtreg].lo,const
	3404	emit_mov_m32_imm(DRCTOP, REGADDRHI(RTREG), 0); // mov [rtreg].hi,sign-extend(const)
3455	3405	}
3456	3406	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3457	3407
3458	3408	case 0x0c: /* TEQI */
3459	3409	if (RSREG != 0)
3460	3410	{
3461		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, ((INT32)SIMMVAL >> 31)); // cmp [rsreg].hi,upper
3462		_jcc_short_link(COND_NE, &link1); // jne skip
3463		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
3464		_jcc(COND_E, mips3.drcdata->generate_trap_exception); // je generate_trap_exception
3465		_resolve_link(&link1); // skip:
	3411	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), ((INT32)SIMMVAL >> 31));
	3412	// cmp [rsreg].hi,upper
	3413	emit_jcc_short_link(DRCTOP, COND_NE, &link1); // jne skip
	3414	emit_cmp_m32_imm(DRCTOP, REGADDRLO(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
	3415	emit_jcc(DRCTOP, COND_E, mips3.drcdata->generate_trap_exception); // je generate_trap_exception
	3416	resolve_link(DRCTOP, &link1); // skip:
3466	3417	}
3467	3418	else
3468	3419	{
3469	3420	if (0 == SIMMVAL)
3470		_jmp(mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
	3421	emit_jmp(DRCTOP, mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
3471	3422	}
3472	3423	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3473	3424
3474	3425	case 0x0e: /* TNEI */
3475	3426	if (RSREG != 0)
3476	3427	{
3477		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, ((INT32)SIMMVAL >> 31)); // cmp [rsreg].hi,upper
3478		_jcc_short_link(COND_E, &link1); // je skip
3479		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
3480		_jcc(COND_NE, mips3.drcdata->generate_trap_exception); // jne generate_trap_exception
3481		_resolve_link(&link1); // skip:
	3428	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), ((INT32)SIMMVAL >> 31));
	3429	// cmp [rsreg].hi,upper
	3430	emit_jcc_short_link(DRCTOP, COND_E, &link1); // je skip
	3431	emit_cmp_m32_imm(DRCTOP, REGADDRLO(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
	3432	emit_jcc(DRCTOP, COND_NE, mips3.drcdata->generate_trap_exception); // jne generate_trap_exception
	3433	resolve_link(DRCTOP, &link1); // skip:
3482	3434	}
3483	3435	else
3484	3436	{
3485	3437	if (0 != SIMMVAL)
3486		_jmp(mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
	3438	emit_jmp(DRCTOP, mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
3487	3439	}
3488	3440	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3489	3441
r949	r950
3492	3444	return RECOMPILE_SUCCESSFUL_CP(1,4);
3493	3445	else
3494	3446	{
3495		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
3496		_jcc_near_link(COND_GE, &link1); // jge skip
	3447	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	3448	emit_jcc_near_link(DRCTOP, COND_GE, &link1); // jge skip
3497	3449	}
3498	3450
3499		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3500		_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3501		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3502		_resolve_link(&link1); // skip:
	3451	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3452	emit_mov_m64_imm32(DRCTOP, MABS(&mips3.core->r[31]), pc + 8); // mov [31],pc + 8
	3453	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3454	resolve_link(DRCTOP, &link1); // skip:
3503	3455	return RECOMPILE_SUCCESSFUL_CP(1,4);
3504	3456
3505	3457	case 0x11: /* BGEZAL */
3506	3458	if (RSREG == 0)
3507	3459	{
3508		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3509		_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3510		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3460	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3461	emit_mov_m64_imm32(DRCTOP, MABS(&mips3.core->r[31]), pc + 8); // mov [31],pc + 8
	3462	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3511	3463	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
3512	3464	}
3513	3465	else
3514	3466	{
3515		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
3516		_jcc_near_link(COND_L, &link1); // jl skip
	3467	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	3468	emit_jcc_near_link(DRCTOP, COND_L, &link1); // jl skip
3517	3469	}
3518	3470
3519		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3520		_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3521		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3522		_resolve_link(&link1); // skip:
	3471	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3472	emit_mov_m64_imm32(DRCTOP, MABS(&mips3.core->r[31]), pc + 8); // mov [31],pc + 8
	3473	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3474	resolve_link(DRCTOP, &link1); // skip:
3523	3475	return RECOMPILE_SUCCESSFUL_CP(1,4);
3524	3476
3525	3477	case 0x12: /* BLTZALL */
r949	r950
3527	3479	return RECOMPILE_SUCCESSFUL_CP(1,4);
3528	3480	else
3529	3481	{
3530		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
3531		_jcc_near_link(COND_GE, &link1); // jge skip
	3482	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	3483	emit_jcc_near_link(DRCTOP, COND_GE, &link1); // jge skip
3532	3484	}
3533	3485
3534		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3535		_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3536		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3537		_resolve_link(&link1); // skip:
	3486	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3487	emit_mov_m64_imm32(DRCTOP, MABS(&mips3.core->r[31]), pc + 8); // mov [31],pc + 8
	3488	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3489	resolve_link(DRCTOP, &link1); // skip:
3538	3490	return RECOMPILE_SUCCESSFUL_CP(1,8);
3539	3491
3540	3492	case 0x13: /* BGEZALL */
3541	3493	if (RSREG == 0)
3542	3494	{
3543		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3544		_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3545		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3495	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3496	emit_mov_m64_imm32(DRCTOP, MABS(&mips3.core->r[31]), pc + 8); // mov [31],pc + 8
	3497	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3546	3498	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
3547	3499	}
3548	3500	else
3549	3501	{
3550		_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, 0); // cmp [rsreg].hi,0
3551		_jcc_near_link(COND_L, &link1); // jl skip
	3502	emit_cmp_m32_imm(DRCTOP, REGADDRHI(RSREG), 0); // cmp [rsreg].hi,0
	3503	emit_jcc_near_link(DRCTOP, COND_L, &link1); // jl skip
3552	3504	}
3553	3505
3554		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3555		_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3556		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3557		_resolve_link(&link1); // skip:
	3506	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3507	emit_mov_m64_imm32(DRCTOP, MABS(&mips3.core->r[31]), pc + 8); // mov [31],pc + 8
	3508	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3509	resolve_link(DRCTOP, &link1); // skip:
3558	3510	return RECOMPILE_SUCCESSFUL_CP(1,8);
3559	3511	}
3560	3512
3561		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	3513	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
3562	3514	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
3563	3515	}
3564	3516
r949	r950
3574	3526
3575	3527	static UINT32 recompile_set_cop0_reg(drc_core *drc, UINT8 reg)
3576	3528	{
3577		link_info link1;
	3529	emit_link link1;
3578	3530
3579	3531	switch (reg)
3580	3532	{
3581	3533	case COP0_Cause:
3582		_mov_r32_m32abs(REG_EBX, &mips3.core->cpr[0][COP0_Cause]); // mov ebx,[mips3.core->cpr[0][COP0_Cause]]
3583		_and_r32_imm(REG_EAX, ~0xfc00); // and eax,~0xfc00
3584		_and_r32_imm(REG_EBX, 0xfc00); // and ebx,0xfc00
3585		_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
3586		_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Cause], REG_EAX); // mov [mips3.core->cpr[0][COP0_Cause]],eax
3587		_and_r32_m32abs(REG_EAX, &mips3.core->cpr[0][COP0_Status]); // and eax,[mips3.core->cpr[0][COP0_Status]]
	3534	emit_mov_r32_m32(DRCTOP, REG_EBX, CPR0ADDR(COP0_Cause)); // mov ebx,[COP0_Cause]
	3535	emit_and_r32_imm(DRCTOP, REG_EAX, ~0xfc00); // and eax,~0xfc00
	3536	emit_and_r32_imm(DRCTOP, REG_EBX, 0xfc00); // and ebx,0xfc00
	3537	emit_or_r32_r32(DRCTOP, REG_EAX, REG_EBX); // or eax,ebx
	3538	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_Cause), REG_EAX); // mov [COP0_Cause],eax
	3539	emit_and_r32_m32(DRCTOP, REG_EAX, CPR0ADDR(COP0_Status)); // and eax,[COP0_Status]
3588	3540	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_CHECK_SW_INTERRUPTS;
3589	3541
3590	3542	case COP0_Status:
3591		_mov_r32_m32abs(REG_EBX, &mips3.core->cpr[0][COP0_Status]); // mov ebx,[mips3.core->cpr[0][COP0_Status]]
3592		_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Status], REG_EAX); // mov [mips3.core->cpr[0][COP0_Status]],eax
3593		_xor_r32_r32(REG_EBX, REG_EAX); // xor ebx,eax
	3543	emit_mov_r32_m32(DRCTOP, REG_EBX, CPR0ADDR(COP0_Status)); // mov ebx,[COP0_Status]
	3544	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_Status), REG_EAX); // mov [COP0_Status],eax
	3545	emit_xor_r32_r32(DRCTOP, REG_EBX, REG_EAX); // xor ebx,eax
3594	3546	/*
3595	3547	#ifdef MAME_DEBUG
3596		_test_r32_imm(REG_EAX, 0xe0); // test eax,0xe0
3597		_jcc_short_link(COND_Z, &link1); // jz skip
3598		_sub_r32_imm(REG_ESP, 4); // sub esp,4
3599		_push_r32(REG_EAX); // push eax
3600		_push_imm("System set 64-bit addressing mode, SR=%08X"); // push <string>
3601		_call(mame_printf_debug); // call mame_printf_debug
3602		_call(mame_debug_break); // call mame_debug_break
3603		_add_r32_imm(REG_ESP, 12); // add esp,12
3604		_resolve_link(&link1); // skip:
	3548	_test_r32_imm(REG_EAX, 0xe0); // test eax,0xe0
	3549	_jcc_short_link(COND_Z, &link1); // jz skip
	3550	_sub_r32_imm(REG_ESP, 4); // sub esp,4
	3551	_push_r32(REG_EAX); // push eax
	3552	_push_imm("System set 64-bit addressing mode, SR=%08X"); // push <string>
	3553	_call(mame_printf_debug); // call mame_printf_debug
	3554	_call(mame_debug_break); // call mame_debug_break
	3555	_add_r32_imm(REG_ESP, 12); // add esp,12
	3556	_resolve_link(&link1); // skip:
3605	3557	#endif
3606	3558	*/
3607		_test_r32_imm(REG_EBX, 0x8000); // test ebx,0x8000
3608		_jcc_short_link(COND_Z, &link1); // jz skip
3609		append_update_cycle_counting(drc); // update cycle counting
3610		_resolve_link(&link1); // skip:
	3559	emit_test_r32_imm(DRCTOP, REG_EBX, 0x8000); // test ebx,0x8000
	3560	emit_jcc_short_link(DRCTOP, COND_Z, &link1); // jz skip
	3561	append_update_cycle_counting(drc); // update cycle counting
	3562	resolve_link(DRCTOP, &link1); // skip:
3611	3563	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_CHECK_INTERRUPTS \| RECOMPILE_END_OF_STRING \| RECOMPILE_ADD_DISPATCH;
3612	3564
3613	3565	case COP0_Count:
3614		_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Count], REG_EAX); // mov [mips3.core->cpr[0][COP0_Count]],eax
3615		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
3616		_sub_r32_imm(REG_ESP, 8); // sub esp,8
3617		_push_r32(REG_EAX); // push eax
3618		_call((genf *)activecpu_gettotalcycles64); // call activecpu_gettotalcycles64
3619		_pop_r32(REG_EBX); // pop ebx
3620		_add_r32_imm(REG_ESP, 8); // add esp,8
3621		_sub_r32_r32(REG_EAX, REG_EBX); // sub eax,ebx
3622		_sbb_r32_imm(REG_EDX, 0); // sbb edx,0
3623		_sub_r32_r32(REG_EAX, REG_EBX); // sub eax,ebx
3624		_sbb_r32_imm(REG_EDX, 0); // sbb edx,0
3625		_mov_m64abs_r64(&mips3.core->count_zero_time, REG_EDX, REG_EAX); // mov [mips3.core->count_zero_time],edx:eax
3626		append_update_cycle_counting(drc); // update cycle counting
	3566	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_Count), REG_EAX); // mov [COP0_Count],eax
	3567	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	3568	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
	3569	emit_push_r32(DRCTOP, REG_EAX); // push eax
	3570	emit_call(DRCTOP, (x86code *)activecpu_gettotalcycles64); // call activecpu_gettotalcycles64
	3571	emit_pop_r32(DRCTOP, REG_EBX); // pop ebx
	3572	emit_add_r32_imm(DRCTOP, REG_ESP, 8); // add esp,8
	3573	emit_sub_r32_r32(DRCTOP, REG_EAX, REG_EBX); // sub eax,ebx
	3574	emit_sbb_r32_imm(DRCTOP, REG_EDX, 0); // sbb edx,0
	3575	emit_sub_r32_r32(DRCTOP, REG_EAX, REG_EBX); // sub eax,ebx
	3576	emit_sbb_r32_imm(DRCTOP, REG_EDX, 0); // sbb edx,0
	3577	emit_mov_m64_r64(DRCTOP, MABS(&mips3.core->count_zero_time), REG_EDX, REG_EAX); // mov [mips3.core->count_zero_time],edx:eax
	3578	append_update_cycle_counting(drc); // update cycle counting
3627	3579	return RECOMPILE_SUCCESSFUL_CP(1,4);
3628	3580
3629	3581	case COP0_Compare:
3630		_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Compare], REG_EAX); // mov [mips3.core->cpr[0][COP0_Compare]],eax
3631		_and_m32abs_imm(&mips3.core->cpr[0][COP0_Cause], ~0x8000); // and [mips3.core->cpr[0][COP0_Cause]],~0x8000
3632		append_update_cycle_counting(drc); // update cycle counting
	3582	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_Compare), REG_EAX); // mov [COP0_Compare],eax
	3583	emit_and_m32_imm(DRCTOP, CPR0ADDR(COP0_Cause), ~0x8000); // and [COP0_Cause],~0x8000
	3584	append_update_cycle_counting(drc); // update cycle counting
3633	3585	return RECOMPILE_SUCCESSFUL_CP(1,4);
3634	3586
3635	3587	case COP0_PRId:
3636	3588	return RECOMPILE_SUCCESSFUL_CP(1,4);
3637	3589
3638	3590	case COP0_Config:
3639		_mov_r32_m32abs(REG_EBX, &mips3.core->cpr[0][COP0_Config]); // mov ebx,[mips3.core->cpr[0][COP0_Cause]]
3640		_and_r32_imm(REG_EAX, 0x0007); // and eax,0x0007
3641		_and_r32_imm(REG_EBX, ~0x0007); // and ebx,~0x0007
3642		_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
3643		_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Config], REG_EAX); // mov [mips3.core->cpr[0][COP0_Cause]],eax
	3591	emit_mov_r32_m32(DRCTOP, REG_EBX, CPR0ADDR(COP0_Config)); // mov ebx,[COP0_Cause]
	3592	emit_and_r32_imm(DRCTOP, REG_EAX, 0x0007); // and eax,0x0007
	3593	emit_and_r32_imm(DRCTOP, REG_EBX, ~0x0007); // and ebx,~0x0007
	3594	emit_or_r32_r32(DRCTOP, REG_EAX, REG_EBX); // or eax,ebx
	3595	emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_Config), REG_EAX); // mov [COP0_Cause],eax
3644	3596	return RECOMPILE_SUCCESSFUL_CP(1,4);
3645	3597
3646	3598	default:
3647		_mov_m32~~abs~~_r32(~~&mips3.core->cpr[~~0][reg], REG_EAX); // mov [~~mips3.co~~re~~->cpr[0][re~~g]],eax
	3599	emit_mov_m32_r32(DRCTOP, CPR0ADDR(reg), REG_EAX); // mov [reg],eax
3648	3600	return RECOMPILE_SUCCESSFUL_CP(1,4);
3649	3601	}
3650	3602	return RECOMPILE_UNIMPLEMENTED;
r949	r950
3657	3609
3658	3610	static UINT32 recompile_get_cop0_reg(drc_core *drc, UINT8 reg)
3659	3611	{
3660		link_info link1;
	3612	emit_link link1;
3661	3613
3662	3614	switch (reg)
3663	3615	{
3664	3616	case COP0_Count:
3665		_sub_r32_imm(REG_EBP, 250); // sub ebp,24
3666		_jcc_short_link(COND_NS, &link1); // jns notneg
3667		_xor_r32_r32(REG_EBP, REG_EBP); // xor ebp,ebp
3668		_resolve_link(&link1); // notneg:
3669		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
3670		_sub_r32_imm(REG_ESP, 12); // sub esp,12
3671		_call((genf *)activecpu_gettotalcycles64); // call activecpu_gettotalcycles64
3672		_add_r32_imm(REG_ESP, 12); // add esp,12
3673		_sub_r32_m32abs(REG_EAX, LO(&mips3.core->count_zero_time)); // sub eax,[mips3.core->count_zero_time+0]
3674		_sbb_r32_m32abs(REG_EDX, HI(&mips3.core->count_zero_time)); // sbb edx,[mips3.core->count_zero_time+4]
3675		_shrd_r32_r32_imm(REG_EAX, REG_EDX, 1); // shrd eax,edx,1
	3617	emit_sub_r32_imm(DRCTOP, REG_EBP, 250); // sub ebp,24
	3618	emit_jcc_short_link(DRCTOP, COND_NS, &link1); // jns notneg
	3619	emit_xor_r32_r32(DRCTOP, REG_EBP, REG_EBP); // xor ebp,ebp
	3620	resolve_link(DRCTOP, &link1); // notneg:
	3621	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	3622	emit_sub_r32_imm(DRCTOP, REG_ESP, 12); // sub esp,12
	3623	emit_call(DRCTOP, (x86code *)activecpu_gettotalcycles64); // call activecpu_gettotalcycles64
	3624	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	3625	emit_sub_r32_m32(DRCTOP, REG_EAX, MABS(LO(&mips3.core->count_zero_time))); // sub eax,[mips3.core->count_zero_time+0]
	3626	emit_sbb_r32_m32(DRCTOP, REG_EDX, MABS(HI(&mips3.core->count_zero_time))); // sbb edx,[mips3.core->count_zero_time+4]
	3627	emit_shrd_r32_r32_imm(DRCTOP, REG_EAX, REG_EDX, 1); // shrd eax,edx,1
3676	3628	return RECOMPILE_SUCCESSFUL_CP(1,4);
3677	3629
3678	3630	case COP0_Cause:
3679		_sub_r32_imm(REG_EBP, 250); // sub ebp,24
3680		_jcc_short_link(COND_NS, &link1); // jns notneg
3681		_xor_r32_r32(REG_EBP, REG_EBP); // xor ebp,ebp
3682		_resolve_link(&link1); // notneg:
3683		_mov_r32_m32abs(REG_EAX, &mips3.core->cpr[0][reg]); // mov eax,[mips3.core->cpr[0][reg]]
	3631	emit_sub_r32_imm(DRCTOP, REG_EBP, 250); // sub ebp,24
	3632	emit_jcc_short_link(DRCTOP, COND_NS, &link1); // jns notneg
	3633	emit_xor_r32_r32(DRCTOP, REG_EBP, REG_EBP); // xor ebp,ebp
	3634	resolve_link(DRCTOP, &link1); // notneg:
	3635	emit_mov_r32_m32(DRCTOP, REG_EAX, CPR0ADDR(reg)); // mov eax,[reg]
3684	3636	return RECOMPILE_SUCCESSFUL_CP(1,4);
3685	3637
3686	3638	default:
3687		_mov_r32_m32~~abs~~(REG_EAX, ~~&mips3.core->cpr[~~0][reg]); // mov eax,[~~mips3.co~~re~~->cpr[0][re~~g]]
	3639	emit_mov_r32_m32(DRCTOP, REG_EAX, CPR0ADDR(reg)); // mov eax,[reg]
3688	3640	return RECOMPILE_SUCCESSFUL_CP(1,4);
3689	3641	}
3690	3642	return RECOMPILE_UNIMPLEMENTED;
r949	r950
3697	3649
3698	3650	static UINT32 recompile_cop0(drc_core *drc, UINT32 pc, UINT32 op)
3699	3651	{
3700		link_info checklink;
	3652	emit_link checklink;
3701	3653	UINT32 result;
3702	3654
3703	3655	if (mips3.drcoptions & MIPS3DRC_STRICT_COP0)
3704	3656	{
3705		_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_KSU_MASK); // test [mips3.core->cpr[0][COP0_Status]],SR_KSU_MASK
3706		_jcc_short_link(COND_Z, &checklink); // jz okay
3707		_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_COP0); // test [mips3.core->cpr[0][COP0_Status]],SR_COP0
3708		_jcc(COND_Z, mips3.drcdata->generate_cop_exception); // jz generate_cop_exception
3709		_resolve_link(&checklink); // okay:
	3657	emit_test_m32_imm(DRCTOP, CPR0ADDR(COP0_Status), SR_KSU_MASK); // test [COP0_Status],SR_KSU_MASK
	3658	emit_jcc_short_link(DRCTOP, COND_Z, &checklink); // jz okay
	3659	emit_test_m32_imm(DRCTOP, CPR0ADDR(COP0_Status), SR_COP0); // test [COP0_Status],SR_COP0
	3660	emit_jcc(DRCTOP, COND_Z, mips3.drcdata->generate_cop_exception); // jz generate_cop_exception
	3661	resolve_link(DRCTOP, &checklink); // okay:
3710	3662	}
3711	3663
3712	3664	switch (RSREG)
r949	r950
3715	3667	result = RECOMPILE_SUCCESSFUL_CP(1,4);
3716	3668	if (RTREG != 0)
3717	3669	{
3718		result = recompile_get_cop0_reg(drc, RDREG); // read cop0 reg
3719		_cdq(); // cdq
3720		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	3670	result = recompile_get_cop0_reg(drc, RDREG); // read cop0 reg
	3671	emit_cdq(DRCTOP); // cdq
	3672	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
3721	3673	}
3722	3674	return result;
3723	3675
r949	r950
3725	3677	result = RECOMPILE_SUCCESSFUL_CP(1,4);
3726	3678	if (RTREG != 0)
3727	3679	{
3728		result = recompile_get_cop0_reg(drc, RDREG); // read cop0 reg
3729		_cdq(); // cdq
3730		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	3680	result = recompile_get_cop0_reg(drc, RDREG); // read cop0 reg
	3681	emit_cdq(DRCTOP); // cdq
	3682	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
3731	3683	}
3732	3684	return result;
3733	3685
3734	3686	case 0x02: /* CFCz */
3735	3687	if (RTREG != 0)
3736	3688	{
3737		_mov_r32_m32abs(REG_EAX, &mips3.core->ccr[0][RDREG]); // mov eax,[mips3.core->ccr[0][rdreg]]
3738		_cdq(); // cdq
3739		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
	3689	emit_mov_r32_m32(DRCTOP, REG_EAX, CCR0ADDR(RDREG)); // mov eax,[mips3.core->ccr[0][rdreg]]
	3690	emit_cdq(DRCTOP); // cdq
	3691	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
3740	3692	}
3741	3693	return RECOMPILE_SUCCESSFUL_CP(1,4);
3742	3694
3743	3695	case 0x04: /* MTCz */
3744	3696	if (RTREG != 0)
3745		_mov_r32_m32bd(R~~EG_EAX~~, REG_ESI, REGD~~ISP~~(RTREG)); // mov eax,[mips3.core->r[RTREG]]
	3697	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[mips3.core->r[RTREG]]
3746	3698	else
3747		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
3748		result = recompile_set_cop0_reg(drc, RDREG); // write cop0 reg
	3699	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX); // xor eax,eax
	3700	result = recompile_set_cop0_reg(drc, RDREG); // write cop0 reg
3749	3701	return result;
3750	3702
3751	3703	case 0x05: /* DMTCz */
3752	3704	if (RTREG != 0)
3753		_mov_r32_m32bd(R~~EG_EAX~~, REG_ESI, REGD~~ISP~~(RTREG)); // mov eax,[mips3.core->r[RTREG]]
	3705	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[mips3.core->r[RTREG]]
3754	3706	else
3755		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
3756		result = recompile_set_cop0_reg(drc, RDREG); // write cop0 reg
	3707	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX); // xor eax,eax
	3708	result = recompile_set_cop0_reg(drc, RDREG); // write cop0 reg
3757	3709	return result;
3758	3710
3759	3711	case 0x06: /* CTCz */
3760	3712	if (RTREG != 0)
3761		_mov_r32_m32bd(R~~EG_EAX~~, REG_ESI, REGD~~ISP~~(RTREG)); // mov eax,[mips3.core->r[RTREG]]
	3713	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[mips3.core->r[RTREG]]
3762	3714	else
3763		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
3764		_mov_m32abs_r32(&mips3.core->ccr[0][RDREG], REG_EAX); // mov [mips3.core->ccr[0][RDREG]],eax
	3715	emit_xor_r32_r32(DRCTOP, REG_EAX, REG_EAX); // xor eax,eax
	3716	emit_mov_m32_r32(DRCTOP, CCR0ADDR(RDREG), REG_EAX); // mov [mips3.core->ccr[0][RDREG]],eax
3765	3717	return RECOMPILE_SUCCESSFUL_CP(1,4);
3766	3718
3767	3719	// case 0x08: /* BC */
r949	r950
3794	3746	switch (op & 0x01ffffff)
3795	3747	{
3796	3748	case 0x01: /* TLBR */
3797		_sub_r32_imm(REG_ESP, 8);
3798		_push_imm(mips3.core);
3799		drc_append_save_call_restore(drc, (genf *)mips3com_tlbr, 12);
	3749	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
	3750	emit_push_imm(DRCTOP, (FPTR)mips3.core); // push mips3.core
	3751	drc_append_save_call_restore(drc, (x86code *)mips3com_tlbr, 12); // call tlbr
3800	3752	return RECOMPILE_SUCCESSFUL_CP(1,4);
3801	3753
3802	3754	case 0x02: /* TLBWI */
3803		_sub_r32_imm(REG_ESP, 8);
3804		_push_imm(mips3.core);
3805		drc_append_save_call_restore(drc, (genf *)mips3com_tlbwi, 12);
	3755	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
	3756	emit_push_imm(DRCTOP, (FPTR)mips3.core); // push mips3.core
	3757	drc_append_save_call_restore(drc, (x86code *)mips3com_tlbwi, 12); // call tlbwi
3806	3758	return RECOMPILE_SUCCESSFUL_CP(1,4);
3807	3759
3808	3760	case 0x06: /* TLBWR */
3809		_sub_r32_imm(REG_ESP, 8);
3810		_push_imm(mips3.core);
3811		drc_append_save_call_restore(drc, (genf *)mips3com_tlbwr, 12);
	3761	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
	3762	emit_push_imm(DRCTOP, (FPTR)mips3.core); // push mips3.core
	3763	drc_append_save_call_restore(drc, (x86code *)mips3com_tlbwr, 12); // call tlbwr
3812	3764	return RECOMPILE_SUCCESSFUL_CP(1,4);
3813	3765
3814	3766	case 0x08: /* TLBP */
3815		_sub_r32_imm(REG_ESP, 8);
3816		_push_imm(mips3.core);
3817		drc_append_save_call_restore(drc, (genf *)mips3com_tlbp, 12);
	3767	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
	3768	emit_push_imm(DRCTOP, (FPTR)mips3.core); // push mips3.core
	3769	drc_append_save_call_restore(drc, (x86code *)mips3com_tlbp, 12); // call tlbp
3818	3770	return RECOMPILE_SUCCESSFUL_CP(1,4);
3819	3771
3820	3772	case 0x10: /* RFE */
3821		_jmp(mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	3773	emit_jmp(DRCTOP, mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
3822	3774	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
3823	3775
3824	3776	case 0x18: /* ERET */
3825		_mov_r32_m32abs(REG_EDI, &mips3.core->cpr[0][COP0_EPC]); // mov edi,[mips3.core->cpr[0][COP0_EPC]]
3826		_and_m32abs_imm(&mips3.core->cpr[0][COP0_Status], ~SR_EXL); // and [mips3.core->cpr[0][COP0_Status]],~SR_EXL
	3777	emit_mov_r32_m32(DRCTOP, REG_EDI, CPR0ADDR(COP0_EPC)); // mov edi,[COP0_EPC]
	3778	emit_and_m32_imm(DRCTOP, CPR0ADDR(COP0_Status), ~SR_EXL); // and [COP0_Status],~SR_EXL
3827	3779	return RECOMPILE_SUCCESSFUL_CP(1,0) \| RECOMPILE_CHECK_INTERRUPTS \| RECOMPILE_END_OF_STRING \| RECOMPILE_ADD_DISPATCH;
3828	3780
3829	3781	default:
3830		_jmp(mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	3782	emit_jmp(DRCTOP, mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
3831	3783	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
3832	3784	}
3833	3785	break;
3834	3786
3835	3787	// default:
3836		// _jmp(mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	3788	// _jmp(mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
3837	3789	// return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
3838	3790	}
3839	3791	return RECOMPILE_UNIMPLEMENTED;
r949	r950
3851	3803
3852	3804	static UINT32 recompile_cop1(drc_core *drc, UINT32 pc, UINT32 op)
3853	3805	{
3854		link_info link1;
	3806	emit_link link1;
3855	3807	int cycles, i;
3856	3808
3857	3809	if (mips3.drcoptions & MIPS3DRC_STRICT_COP1)
3858	3810	{
3859		_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_COP1); // test [mips3.core->cpr[0][COP0_Status]],SR_COP1
3860		_jcc(COND_Z, mips3.drcdata->generate_cop_exception); // jz generate_cop_exception
	3811	emit_test_m32_imm(DRCTOP, CPR0ADDR(COP0_Status), SR_COP1); // test [COP0_Status],SR_COP1
	3812	emit_jcc(DRCTOP, COND_Z, mips3.drcdata->generate_cop_exception); // jz generate_cop_exception
3861	3813	}
3862	3814
3863	3815	switch (RSREG)
r949	r950
3865	3817	case 0x00: /* MFCz */
3866	3818	if (RTREG != 0)
3867	3819	{
3868		_mov_r32_m32abs(REG_EAX, FPR32(RDREG)); // mov eax,[mips3.core->cpr[1][RDREG]]
3869		_cdq(); // cdq
3870		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [mips3.core->r[RTREG]],edx:eax
	3820	emit_mov_r32_m32(DRCTOP, REG_EAX, FPR32ADDR(RDREG)); // mov eax,[RDREG]
	3821	emit_cdq(DRCTOP); // cdq
	3822	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [RTREG],edx:eax
3871	3823	}
3872	3824	return RECOMPILE_SUCCESSFUL_CP(1,4);
3873	3825
3874	3826	case 0x01: /* DMFCz */
3875	3827	if (RTREG != 0)
3876		_mov_m64bd_m64~~abs~~(R~~EG_ESI~~, REGD~~ISP~~(RTREG), FPR64(RDREG));
	3828	emit_mov_m64_m64(DRCTOP, REGADDR(RTREG), FPR64ADDR(RDREG));
3877	3829	return RECOMPILE_SUCCESSFUL_CP(1,4);
3878	3830
3879	3831	case 0x02: /* CFCz */
3880	3832	if (RTREG != 0)
3881	3833	{
3882		_mov_r32_m32~~abs~~(REG_EAX, ~~&mips3.core->ccr[~~1][RDREG]); // mov eax,[mips3.core->ccr[1][RDREG]]
	3834	emit_mov_r32_m32(DRCTOP, REG_EAX, CCR1ADDR(RDREG)); // mov eax,[mips3.core->ccr[1][RDREG]]
3883	3835	if (RDREG == 31)
3884	3836	{
3885		_and_r32_imm(REG_EAX, ~0xfe800000); // and eax,~0xfe800000
3886		_xor_r32_r32(REG_EBX, REG_EBX); // xor ebx,ebx
3887		_cmp_m8abs_imm(&mips3.core->cf[1][0], 0); // cmp [cf[0]],0
3888		_setcc_r8(COND_NZ, REG_BL); // setnz bl
3889		_shl_r32_imm(REG_EBX, 23); // shl ebx,23
3890		_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
	3837	emit_and_r32_imm(DRCTOP, REG_EAX, ~0xfe800000); // and eax,~0xfe800000
	3838	emit_xor_r32_r32(DRCTOP, REG_EBX, REG_EBX); // xor ebx,ebx
	3839	emit_cmp_m8_imm(DRCTOP, MABS(&mips3.core->cf[1][0]), 0); // cmp [cf[0]],0
	3840	emit_setcc_r8(DRCTOP, COND_NZ, REG_BL); // setnz bl
	3841	emit_shl_r32_imm(DRCTOP, REG_EBX, 23); // shl ebx,23
	3842	emit_or_r32_r32(DRCTOP, REG_EAX, REG_EBX); // or eax,ebx
3891	3843	if (mips3.core->flavor >= MIPS3_TYPE_MIPS_IV)
3892	3844	for (i = 1; i <= 7; i++)
3893	3845	{
3894		_cmp_m8abs_imm(&mips3.core->cf[1][i], 0); // cmp [cf[i]],0
3895		_setcc_r8(COND_NZ, REG_BL); // setnz bl
3896		_shl_r32_imm(REG_EBX, 24+i); // shl ebx,24+i
3897		_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
	3846	emit_cmp_m8_imm(DRCTOP, MABS(&mips3.core->cf[1][i]), 0); // cmp [cf[i]],0
	3847	emit_setcc_r8(DRCTOP, COND_NZ, REG_BL); // setnz bl
	3848	emit_shl_r32_imm(DRCTOP, REG_EBX, 24+i); // shl ebx,24+i
	3849	emit_or_r32_r32(DRCTOP, REG_EAX, REG_EBX); // or eax,ebx
3898	3850	}
3899	3851	}
3900		_cdq(); // cdq
3901		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [mips3.core->r[RTREG]],edx:eax
	3852	emit_cdq(DRCTOP); // cdq
	3853	emit_mov_m64_r64(DRCTOP, REGADDR(RTREG), REG_EDX, REG_EAX); // mov [mips3.core->r[RTREG]],edx:eax
3902	3854	}
3903	3855	return RECOMPILE_SUCCESSFUL_CP(1,4);
3904	3856
3905	3857	case 0x04: /* MTCz */
3906	3858	if (RTREG != 0)
3907	3859	{
3908		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core->r[RTREG]]
3909		_mov_m32abs_r32(FPR32(RDREG), REG_EAX); // mov [mips3.core->cpr[1][RDREG]],eax
	3860	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[mips3.core->r[RTREG]]
	3861	emit_mov_m32_r32(DRCTOP, FPR32ADDR(RDREG), REG_EAX); // mov [mips3.core->cpr[1][RDREG]],eax
3910	3862	}
3911	3863	else
3912		_mov_m32~~abs~~_imm(FPR32(RDREG), 0); // mov [mips3.core->cpr[1][RDREG]],0
	3864	emit_mov_m32_imm(DRCTOP, FPR32ADDR(RDREG), 0); // mov [mips3.core->cpr[1][RDREG]],0
3913	3865	return RECOMPILE_SUCCESSFUL_CP(1,4);
3914	3866
3915	3867	case 0x05: /* DMTCz */
3916	3868	if (RTREG != 0)
3917		_mov_m64~~abs~~_m64bd(FPR64(RDREG), REG~~_ESI, REG~~D~~ISP~~(RTREG));
	3869	emit_mov_m64_m64(DRCTOP, FPR64ADDR(RDREG), REGADDR(RTREG));
3918	3870	else
3919		_zero_m64~~abs~~(FPR64(RDREG)); // mov [mips3.core->cpr[1][RDREG]],0
	3871	emit_zero_m64(DRCTOP, FPR64ADDR(RDREG)); // mov [mips3.core->cpr[1][RDREG]],0
3920	3872	return RECOMPILE_SUCCESSFUL_CP(1,4);
3921	3873
3922	3874	case 0x06: /* CTCz */
3923	3875	if (RTREG != 0)
3924	3876	{
3925		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core->r[RTREG]]
3926		_mov_m32abs_r32(&mips3.core->ccr[1][RDREG], REG_EAX); // mov [mips3.core->ccr[1][RDREG]],eax
	3877	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[mips3.core->r[RTREG]]
	3878	emit_mov_m32_r32(DRCTOP, CCR1ADDR(RDREG), REG_EAX); // mov [mips3.core->ccr[1][RDREG]],eax
3927	3879	}
3928	3880	else
3929		_mov_m32~~abs~~_imm(~~&mips3.core->ccr[~~1][RDREG], 0); // mov [mips3.core->ccr[1][RDREG]],0
	3881	emit_mov_m32_imm(DRCTOP, CCR1ADDR(RDREG), 0); // mov [mips3.core->ccr[1][RDREG]],0
3930	3882	if (RDREG == 31)
3931	3883	{
3932		_mov_r32_m32abs(REG_EAX, LO(&mips3.core->ccr[1][RDREG])); // mov eax,[mips3.core->ccr[1][RDREG]]
3933		_test_r32_imm(REG_EAX, 1 << 23); // test eax,1<<23
3934		_setcc_m8abs(COND_NZ, &mips3.core->cf[1][0]); // setnz [cf[0]]
	3884	emit_mov_r32_m32(DRCTOP, REG_EAX, MABS(LO(&mips3.core->ccr[1][RDREG]))); // mov eax,[mips3.core->ccr[1][RDREG]]
	3885	emit_test_r32_imm(DRCTOP, REG_EAX, 1 << 23); // test eax,1<<23
	3886	emit_setcc_m8(DRCTOP, COND_NZ, MABS(&mips3.core->cf[1][0])); // setnz [cf[0]]
3935	3887	if (mips3.core->flavor >= MIPS3_TYPE_MIPS_IV)
3936	3888	for (i = 1; i <= 7; i++)
3937	3889	{
3938		_test_r32_imm(REG_EAX, 1 << (24+i)); // test eax,1<<(24+i)
3939		_setcc_m8abs(COND_NZ, &mips3.core->cf[1][i]); // setnz [cf[i]]
	3890	emit_test_r32_imm(DRCTOP, REG_EAX, 1 << (24+i)); // test eax,1<<(24+i)
	3891	emit_setcc_m8(DRCTOP, COND_NZ, MABS(&mips3.core->cf[1][i])); // setnz [cf[i]]
3940	3892	}
3941		_and_r32_imm(REG_EAX, 3); // and eax,3
3942		_test_r32_imm(REG_EAX, 1); // test eax,1
3943		_jcc_near_link(COND_Z, &link1); // jz skip
3944		_xor_r32_imm(REG_EAX, 2); // xor eax,2
3945		_resolve_link(&link1); // skip:
3946		drc_append_set_fp_rounding(drc, REG_EAX); // set_rounding(EAX)
	3893	emit_and_r32_imm(DRCTOP, REG_EAX, 3); // and eax,3
	3894	emit_test_r32_imm(DRCTOP, REG_EAX, 1); // test eax,1
	3895	emit_jcc_near_link(DRCTOP, COND_Z, &link1); // jz skip
	3896	emit_xor_r32_imm(DRCTOP, REG_EAX, 2); // xor eax,2
	3897	resolve_link(DRCTOP, &link1); // skip:
	3898	drc_append_set_fp_rounding(drc, REG_EAX); // set_rounding(EAX)
3947	3899	}
3948	3900	return RECOMPILE_SUCCESSFUL_CP(1,4);
3949	3901
r949	r950
3951	3903	switch ((op >> 16) & 3)
3952	3904	{
3953	3905	case 0x00: /* BCzF */
3954		_cmp_m8abs_imm(&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
3955		_jcc_near_link(COND_NZ, &link1); // jnz link1
3956		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3957		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles);// <branch or dispatch>
3958		_resolve_link(&link1); // skip:
	3906	emit_cmp_m8_imm(DRCTOP, CF1ADDR((op >> 18) & 7), 0); // cmp [cf[x]],0
	3907	emit_jcc_near_link(DRCTOP, COND_NZ, &link1); // jnz link1
	3908	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3909	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3910	resolve_link(DRCTOP, &link1); // skip:
3959	3911	return RECOMPILE_SUCCESSFUL_CP(1,4);
3960	3912
3961	3913	case 0x01: /* BCzT */
3962		_cmp_m8abs_imm(&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
3963		_jcc_near_link(COND_Z, &link1); // jz link1
3964		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3965		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles);// <branch or dispatch>
3966		_resolve_link(&link1); // skip:
	3914	emit_cmp_m8_imm(DRCTOP, CF1ADDR((op >> 18) & 7), 0); // cmp [cf[x]],0
	3915	emit_jcc_near_link(DRCTOP, COND_Z, &link1); // jz link1
	3916	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3917	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3918	resolve_link(DRCTOP, &link1); // skip:
3967	3919	return RECOMPILE_SUCCESSFUL_CP(1,4);
3968	3920
3969	3921	case 0x02: /* BCzFL */
3970		_cmp_m8abs_imm(&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
3971		_jcc_near_link(COND_NZ, &link1); // jnz link1
3972		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3973		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles);// <branch or dispatch>
3974		_resolve_link(&link1); // skip:
	3922	emit_cmp_m8_imm(DRCTOP, CF1ADDR((op >> 18) & 7), 0); // cmp [cf[x]],0
	3923	emit_jcc_near_link(DRCTOP, COND_NZ, &link1); // jnz link1
	3924	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3925	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3926	resolve_link(DRCTOP, &link1); // skip:
3975	3927	return RECOMPILE_SUCCESSFUL_CP(1,8);
3976	3928
3977	3929	case 0x03: /* BCzTL */
3978		_cmp_m8abs_imm(&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
3979		_jcc_near_link(COND_Z, &link1); // jz link1
3980		cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3981		append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles);// <branch or dispatch>
3982		_resolve_link(&link1); // skip:
	3930	emit_cmp_m8_imm(DRCTOP, CF1ADDR((op >> 18) & 7), 0); // cmp [cf[x]],0
	3931	emit_jcc_near_link(DRCTOP, COND_Z, &link1); // jz link1
	3932	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
	3933	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
	3934	resolve_link(DRCTOP, &link1); // skip:
3983	3935	return RECOMPILE_SUCCESSFUL_CP(1,8);
3984	3936	}
3985	3937	break;
r949	r950
3992	3944	{
3993	3945	if (USE_SSE)
3994	3946	{
3995		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
3996		_addss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // addss xmm0,[ftreg]
3997		_movss_m32abs_r128(FPR32(FDREG), REG_XMM0); // movss [fdreg],xmm0
	3947	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	3948	emit_addss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // addss xmm0,[ftreg]
	3949	emit_movss_m32_r128(DRCTOP, FPR32ADDR(FDREG), REG_XMM0); // movss [fdreg],xmm0
3998	3950	}
3999	3951	else
4000	3952	{
4001		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4002		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4003		_faddp(); // faddp
4004		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	3953	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	3954	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	3955	emit_faddp(DRCTOP); // faddp
	3956	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4005	3957	}
4006	3958	}
4007	3959	else /* ADD.D */
4008	3960	{
4009	3961	if (USE_SSE)
4010	3962	{
4011		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4012		_addsd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // addsd xmm0,[ftreg]
4013		_movsd_m64abs_r128(FPR64(FDREG), REG_XMM0); // movsd [fdreg],xmm0
	3963	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	3964	emit_addsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // addsd xmm0,[ftreg]
	3965	emit_movsd_m64_r128(DRCTOP, FPR64ADDR(FDREG), REG_XMM0); // movsd [fdreg],xmm0
4014	3966	}
4015	3967	else
4016	3968	{
4017		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4018		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4019		_faddp(); // faddp
4020		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	3969	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	3970	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	3971	emit_faddp(DRCTOP); // faddp
	3972	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4021	3973	}
4022	3974	}
4023	3975	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
4027	3979	{
4028	3980	if (USE_SSE)
4029	3981	{
4030		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4031		_subss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // subss xmm0,[ftreg]
4032		_movss_m32abs_r128(FPR32(FDREG), REG_XMM0); // movss [fdreg],xmm0
	3982	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	3983	emit_subss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // subss xmm0,[ftreg]
	3984	emit_movss_m32_r128(DRCTOP, FPR32ADDR(FDREG), REG_XMM0); // movss [fdreg],xmm0
4033	3985	}
4034	3986	else
4035	3987	{
4036		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4037		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4038		_fsubp(); // fsubp
4039		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	3988	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	3989	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	3990	emit_fsubp(DRCTOP); // fsubp
	3991	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4040	3992	}
4041	3993	}
4042	3994	else /* SUB.D */
4043	3995	{
4044	3996	if (USE_SSE)
4045	3997	{
4046		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4047		_subsd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // subsd xmm0,[ftreg]
4048		_movsd_m64abs_r128(FPR64(FDREG), REG_XMM0); // movsd [fdreg],xmm0
	3998	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	3999	emit_subsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // subsd xmm0,[ftreg]
	4000	emit_movsd_m64_r128(DRCTOP, FPR64ADDR(FDREG), REG_XMM0); // movsd [fdreg],xmm0
4049	4001	}
4050	4002	else
4051	4003	{
4052		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4053		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4054		_fsubp(); // fsubp
4055		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4004	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4005	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4006	emit_fsubp(DRCTOP); // fsubp
	4007	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4056	4008	}
4057	4009	}
4058	4010	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
4062	4014	{
4063	4015	if (USE_SSE)
4064	4016	{
4065		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4066		_mulss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // mulss xmm0,[ftreg]
4067		_movss_m32abs_r128(FPR32(FDREG), REG_XMM0); // movss [fdreg],xmm0
	4017	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4018	emit_mulss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // mulss xmm0,[ftreg]
	4019	emit_movss_m32_r128(DRCTOP, FPR32ADDR(FDREG), REG_XMM0); // movss [fdreg],xmm0
4068	4020	}
4069	4021	else
4070	4022	{
4071		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4072		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4073		_fmulp(); // fmulp
4074		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4023	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4024	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4025	emit_fmulp(DRCTOP); // fmulp
	4026	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4075	4027	}
4076	4028	}
4077	4029	else /* MUL.D */
4078	4030	{
4079	4031	if (USE_SSE)
4080	4032	{
4081		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4082		_mulsd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // mulsd xmm0,[ftreg]
4083		_movsd_m64abs_r128(FPR64(FDREG), REG_XMM0); // movsd [fdreg],xmm0
	4033	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4034	emit_mulsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // mulsd xmm0,[ftreg]
	4035	emit_movsd_m64_r128(DRCTOP, FPR64ADDR(FDREG), REG_XMM0); // movsd [fdreg],xmm0
4084	4036	}
4085	4037	else
4086	4038	{
4087		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4088		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4089		_fmulp(); // fmulp
4090		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4039	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4040	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4041	emit_fmulp(DRCTOP); // fmulp
	4042	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4091	4043	}
4092	4044	}
4093	4045	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
4097	4049	{
4098	4050	if (USE_SSE)
4099	4051	{
4100		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4101		_divss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // divss xmm0,[ftreg]
4102		_movss_m32abs_r128(FPR32(FDREG), REG_XMM0); // movss [fdreg],xmm0
	4052	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4053	emit_divss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // divss xmm0,[ftreg]
	4054	emit_movss_m32_r128(DRCTOP, FPR32ADDR(FDREG), REG_XMM0); // movss [fdreg],xmm0
4103	4055	}
4104	4056	else
4105	4057	{
4106		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4107		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4108		_fdivp(); // fdivp
4109		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4058	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4059	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4060	emit_fdivp(DRCTOP); // fdivp
	4061	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4110	4062	}
4111	4063	}
4112	4064	else /* DIV.D */
4113	4065	{
4114	4066	if (USE_SSE)
4115	4067	{
4116		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4117		_divsd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // divsd xmm0,[ftreg]
4118		_movsd_m64abs_r128(FPR64(FDREG), REG_XMM0); // movsd [fdreg],xmm0
	4068	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4069	emit_divsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // divsd xmm0,[ftreg]
	4070	emit_movsd_m64_r128(DRCTOP, FPR64ADDR(FDREG), REG_XMM0); // movsd [fdreg],xmm0
4119	4071	}
4120	4072	else
4121	4073	{
4122		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4123		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4124		_fdivp(); // fdivp
4125		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4074	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4075	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4076	emit_fdivp(DRCTOP); // fdivp
	4077	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4126	4078	}
4127	4079	}
4128	4080	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
4132	4084	{
4133	4085	if (USE_SSE)
4134	4086	{
4135		_sqrtss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // sqrtss xmm0,[fsreg]
4136		_movss_m32abs_r128(FPR32(FDREG), REG_XMM0); // movss [fdreg],xmm0
	4087	emit_sqrtss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // sqrtss xmm0,[fsreg]
	4088	emit_movss_m32_r128(DRCTOP, FPR32ADDR(FDREG), REG_XMM0); // movss [fdreg],xmm0
4137	4089	}
4138	4090	else
4139	4091	{
4140		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4141		_fsqrt(); // fsqrt
4142		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4092	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4093	emit_fsqrt(DRCTOP); // fsqrt
	4094	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4143	4095	}
4144	4096	}
4145	4097	else /* SQRT.D */
4146	4098	{
4147	4099	if (USE_SSE)
4148	4100	{
4149		_sqrtsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // sqrtsd xmm0,[fsreg]
4150		_movsd_m64abs_r128(FPR64(FDREG), REG_XMM0); // movsd [fdreg],xmm0
	4101	emit_sqrtsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // sqrtsd xmm0,[fsreg]
	4102	emit_movsd_m64_r128(DRCTOP, FPR64ADDR(FDREG), REG_XMM0); // movsd [fdreg],xmm0
4151	4103	}
4152	4104	else
4153	4105	{
4154		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4155		_fsqrt(); // fsqrt
4156		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4106	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4107	emit_fsqrt(DRCTOP); // fsqrt
	4108	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4157	4109	}
4158	4110	}
4159	4111	return RECOMPILE_SUCCESSFUL_CP(1,4);
r949	r950
4161	4113	case 0x05:
4162	4114	if (IS_SINGLE(op)) /* ABS.S */
4163	4115	{
4164		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4165		_fabs(); // fabs
4166		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4116	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4117	emit_fabs(DRCTOP); // fabs
	4118	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4167	4119	}
4168	4120	else /* ABS.D */
4169	4121	{
4170		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4171		_fabs(); // fabs
4172		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4122	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4123	emit_fabs(DRCTOP); // fabs
	4124	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4173	4125	}
4174	4126	return RECOMPILE_SUCCESSFUL_CP(1,4);
4175	4127
4176	4128	case 0x06:
4177	4129	if (IS_SINGLE(op)) /* MOV.S */
4178	4130	{
4179		_mov_r32_m32abs(REG_EAX, FPR32(FSREG)); // mov eax,[fsreg]
4180		_mov_m32abs_r32(FPR32(FDREG), REG_EAX); // mov [fdreg],eax
	4131	emit_mov_r32_m32(DRCTOP, REG_EAX, FPR32ADDR(FSREG)); // mov eax,[fsreg]
	4132	emit_mov_m32_r32(DRCTOP, FPR32ADDR(FDREG), REG_EAX); // mov [fdreg],eax
4181	4133	}
4182	4134	else /* MOV.D */
4183		_mov_m64~~abs~~_m64~~abs~~(FPR64(FDREG), FPR64(FSREG));
	4135	emit_mov_m64_m64(DRCTOP, FPR64ADDR(FDREG), FPR64ADDR(FSREG));
4184	4136	return RECOMPILE_SUCCESSFUL_CP(1,4);
4185	4137
4186	4138	case 0x07:
4187	4139	if (IS_SINGLE(op)) /* NEG.S */
4188	4140	{
4189		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4190		_fchs(); // fchs
4191		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4141	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4142	emit_fchs(DRCTOP); // fchs
	4143	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4192	4144	}
4193	4145	else /* NEG.D */
4194	4146	{
4195		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4196		_fchs(); // fchs
4197		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4147	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4148	emit_fchs(DRCTOP); // fchs
	4149	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4198	4150	}
4199	4151	return RECOMPILE_SUCCESSFUL_CP(1,4);
4200	4152
4201	4153	case 0x08:
4202	4154	drc_append_set_temp_fp_rounding(drc, FPRND_NEAR);
4203	4155	if (IS_SINGLE(op)) /* ROUND.L.S */
4204		_fld_m32~~abs~~(FPR32(FSREG)); // fld [fsreg]
	4156	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4205	4157	else /* ROUND.L.D */
4206		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4207		_fistp_m64abs(FPR64(FDREG)); // fistp [fdreg]
	4158	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4159	emit_fistp_m64(DRCTOP, FPR64ADDR(FDREG)); // fistp [fdreg]
4208	4160	drc_append_restore_fp_rounding(drc);
4209	4161	return RECOMPILE_SUCCESSFUL_CP(1,4);
4210	4162
4211	4163	case 0x09:
4212	4164	drc_append_set_temp_fp_rounding(drc, FPRND_CHOP);
4213	4165	if (IS_SINGLE(op)) /* TRUNC.L.S */
4214		_fld_m32~~abs~~(FPR32(FSREG)); // fld [fsreg]
	4166	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4215	4167	else /* TRUNC.L.D */
4216		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4217		_fistp_m64abs(FPR64(FDREG)); // fistp [fdreg]
	4168	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4169	emit_fistp_m64(DRCTOP, FPR64ADDR(FDREG)); // fistp [fdreg]
4218	4170	drc_append_restore_fp_rounding(drc);
4219	4171	return RECOMPILE_SUCCESSFUL_CP(1,4);
4220	4172
4221	4173	case 0x0a:
4222	4174	drc_append_set_temp_fp_rounding(drc, FPRND_UP);
4223	4175	if (IS_SINGLE(op)) /* CEIL.L.S */
4224		_fld_m32~~abs~~(FPR32(FSREG)); // fld [fsreg]
	4176	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4225	4177	else /* CEIL.L.D */
4226		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4227		_fistp_m64abs(FPR64(FDREG)); // fistp [fdreg]
	4178	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4179	emit_fistp_m64(DRCTOP, FPR64ADDR(FDREG)); // fistp [fdreg]
4228	4180	drc_append_restore_fp_rounding(drc);
4229	4181	return RECOMPILE_SUCCESSFUL_CP(1,4);
4230	4182
4231	4183	case 0x0b:
4232	4184	drc_append_set_temp_fp_rounding(drc, FPRND_DOWN);
4233	4185	if (IS_SINGLE(op)) /* FLOOR.L.S */
4234		_fld_m32~~abs~~(FPR32(FSREG)); // fld [fsreg]
	4186	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4235	4187	else /* FLOOR.L.D */
4236		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4237		_fistp_m64abs(FPR64(FDREG)); // fistp [fdreg]
	4188	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4189	emit_fistp_m64(DRCTOP, FPR64ADDR(FDREG)); // fistp [fdreg]
4238	4190	drc_append_restore_fp_rounding(drc);
4239	4191	return RECOMPILE_SUCCESSFUL_CP(1,4);
4240	4192
4241	4193	case 0x0c:
4242	4194	drc_append_set_temp_fp_rounding(drc, FPRND_NEAR);
4243	4195	if (IS_SINGLE(op)) /* ROUND.W.S */
4244		_fld_m32~~abs~~(FPR32(FSREG)); // fld [fsreg]
	4196	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4245	4197	else /* ROUND.W.D */
4246		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4247		_fistp_m32abs(FPR32(FDREG)); // fistp [fdreg]
	4198	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4199	emit_fistp_m32(DRCTOP, FPR32ADDR(FDREG)); // fistp [fdreg]
4248	4200	drc_append_restore_fp_rounding(drc);
4249	4201	return RECOMPILE_SUCCESSFUL_CP(1,4);
4250	4202
4251	4203	case 0x0d:
4252	4204	drc_append_set_temp_fp_rounding(drc, FPRND_CHOP);
4253	4205	if (IS_SINGLE(op)) /* TRUNC.W.S */
4254		_fld_m32~~abs~~(FPR32(FSREG)); // fld [fsreg]
	4206	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4255	4207	else /* TRUNC.W.D */
4256		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4257		_fistp_m32abs(FPR32(FDREG)); // fistp [fdreg]
	4208	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4209	emit_fistp_m32(DRCTOP, FPR32ADDR(FDREG)); // fistp [fdreg]
4258	4210	drc_append_restore_fp_rounding(drc);
4259	4211	return RECOMPILE_SUCCESSFUL_CP(1,4);
4260	4212
4261	4213	case 0x0e:
4262	4214	drc_append_set_temp_fp_rounding(drc, FPRND_UP);
4263	4215	if (IS_SINGLE(op)) /* CEIL.W.S */
4264		_fld_m32~~abs~~(FPR32(FSREG)); // fld [fsreg]
	4216	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4265	4217	else /* CEIL.W.D */
4266		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4267		_fistp_m32abs(FPR32(FDREG)); // fistp [fdreg]
	4218	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4219	emit_fistp_m32(DRCTOP, FPR32ADDR(FDREG)); // fistp [fdreg]
4268	4220	drc_append_restore_fp_rounding(drc);
4269	4221	return RECOMPILE_SUCCESSFUL_CP(1,4);
4270	4222
4271	4223	case 0x0f:
4272	4224	drc_append_set_temp_fp_rounding(drc, FPRND_DOWN);
4273	4225	if (IS_SINGLE(op)) /* FLOOR.W.S */
4274		_fld_m32~~abs~~(FPR32(FSREG)); // fld [fsreg]
	4226	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4275	4227	else /* FLOOR.W.D */
4276		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4277		_fistp_m32abs(FPR32(FDREG)); // fistp [fdreg]
	4228	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4229	emit_fistp_m32(DRCTOP, FPR32ADDR(FDREG)); // fistp [fdreg]
4278	4230	drc_append_restore_fp_rounding(drc);
4279	4231	return RECOMPILE_SUCCESSFUL_CP(1,4);
4280	4232
4281	4233	case 0x11: /* R5000 */
4282	4234	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
4283	4235	{
4284		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	4236	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception);
	4237	// jmp generate_invalidop_exception
4285	4238	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4286	4239	}
4287		_cmp_m8abs_imm(&mips3.core->cf[1][(op >> 18) & 7], 0); // cmp [cf[x]],0
4288		_jcc_short_link(((op >> 16) & 1) ? COND_Z : COND_NZ, &link1); // jz/nz skip
	4240	emit_cmp_m8_imm(DRCTOP, CF1ADDR((op >> 18) & 7), 0); // cmp [cf[x]],0
	4241	emit_jcc_short_link(DRCTOP, ((op >> 16) & 1) ? COND_Z : COND_NZ, &link1);
	4242	// jz/nz skip
4289	4243	if (IS_SINGLE(op)) /* MOVT/F.S */
4290	4244	{
4291		_mov_r32_m32abs(REG_EAX, FPR32(FSREG)); // mov eax,[fsreg]
4292		_mov_m32abs_r32(FPR32(FDREG), REG_EAX); // mov [fdreg],eax
	4245	emit_mov_r32_m32(DRCTOP, REG_EAX, FPR32ADDR(FSREG)); // mov eax,[fsreg]
	4246	emit_mov_m32_r32(DRCTOP, FPR32ADDR(FDREG), REG_EAX); // mov [fdreg],eax
4293	4247	}
4294	4248	else /* MOVT/F.D */
4295		_mov_m64abs_m64abs(FPR64(FDREG), FPR64(FSREG));
4296		_resolve_link(&link1); // skip:
	4249	emit_mov_m64_m64(DRCTOP, FPR64ADDR(FDREG), FPR64ADDR(FSREG));
	4250	resolve_link(DRCTOP, &link1); // skip:
4297	4251	return RECOMPILE_SUCCESSFUL_CP(1,4);
4298	4252
4299	4253	case 0x12: /* R5000 */
4300	4254	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
4301	4255	{
4302		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	4256	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception);
	4257	// jmp generate_invalidop_exception
4303	4258	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4304	4259	}
4305		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg].lo
4306		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // or eax,[rtreg].hi
4307		_jcc_short_link(COND_NZ, &link1); // jnz skip
	4260	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	4261	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // or eax,[rtreg].hi
	4262	emit_jcc_short_link(DRCTOP, COND_NZ, &link1); // jnz skip
4308	4263	if (IS_SINGLE(op)) /* MOVZ.S */
4309	4264	{
4310		_mov_r32_m32abs(REG_EAX, FPR32(FSREG)); // mov eax,[fsreg]
4311		_mov_m32abs_r32(FPR32(FDREG), REG_EAX); // mov [fdreg],eax
	4265	emit_mov_r32_m32(DRCTOP, REG_EAX, FPR32ADDR(FSREG)); // mov eax,[fsreg]
	4266	emit_mov_m32_r32(DRCTOP, FPR32ADDR(FDREG), REG_EAX); // mov [fdreg],eax
4312	4267	}
4313	4268	else /* MOVZ.D */
4314		_mov_m64abs_m64abs(FPR64(FDREG), FPR64(FSREG));
4315		_resolve_link(&link1); // skip:
	4269	emit_mov_m64_m64(DRCTOP, FPR64ADDR(FDREG), FPR64ADDR(FSREG));
	4270	resolve_link(DRCTOP, &link1); // skip:
4316	4271	return RECOMPILE_SUCCESSFUL_CP(1,4);
4317	4272
4318	4273	case 0x13: /* R5000 */
4319	4274	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
4320	4275	{
4321		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	4276	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception);
	4277	// jmp generate_invalidop_exception
4322	4278	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4323	4279	}
4324		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg].lo
4325		_or_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // or eax,[rtreg].hi
4326		_jcc_short_link(COND_Z, &link1); // jz skip
	4280	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // mov eax,[rtreg].lo
	4281	emit_or_r32_m32(DRCTOP, REG_EAX, REGADDRHI(RTREG)); // or eax,[rtreg].hi
	4282	emit_jcc_short_link(DRCTOP, COND_Z, &link1); // jz skip
4327	4283	if (IS_SINGLE(op)) /* MOVN.S */
4328	4284	{
4329		_mov_r32_m32abs(REG_EAX, FPR32(FSREG)); // mov eax,[fsreg]
4330		_mov_m32abs_r32(FPR32(FDREG), REG_EAX); // mov [fdreg],eax
	4285	emit_mov_r32_m32(DRCTOP, REG_EAX, FPR32ADDR(FSREG)); // mov eax,[fsreg]
	4286	emit_mov_m32_r32(DRCTOP, FPR32ADDR(FDREG), REG_EAX); // mov [fdreg],eax
4331	4287	}
4332	4288	else /* MOVN.D */
4333		_mov_m64abs_m64abs(FPR64(FDREG), FPR64(FSREG));
4334		_resolve_link(&link1); // skip:
	4289	emit_mov_m64_m64(DRCTOP, FPR64ADDR(FDREG), FPR64ADDR(FSREG));
	4290	resolve_link(DRCTOP, &link1); // skip:
4335	4291	return RECOMPILE_SUCCESSFUL_CP(1,4);
4336	4292
4337	4293	case 0x15: /* R5000 */
4338	4294	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
4339	4295	{
4340		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	4296	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception);
	4297	// jmp generate_invalidop_exception
4341	4298	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4342	4299	}
4343		_fld1(); // fld1
	4300	emit_fld1(DRCTOP); // fld1
4344	4301	if (IS_SINGLE(op)) /* RECIP.S */
4345	4302	{
4346		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4347		_fdivp(); // fdivp
4348		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4303	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4304	emit_fdivp(DRCTOP); // fdivp
	4305	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4349	4306	}
4350	4307	else /* RECIP.D */
4351	4308	{
4352		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4353		_fdivp(); // fdivp
4354		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4309	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4310	emit_fdivp(DRCTOP); // fdivp
	4311	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4355	4312	}
4356	4313	return RECOMPILE_SUCCESSFUL_CP(1,4);
4357	4314
4358	4315	case 0x16: /* R5000 */
4359	4316	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
4360	4317	{
4361		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	4318	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception);
	4319	// jmp generate_invalidop_exception
4362	4320	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4363	4321	}
4364		_fld1(); // fld1
	4322	emit_fld1(DRCTOP); // fld1
4365	4323	if (IS_SINGLE(op)) /* RSQRT.S */
4366	4324	{
4367		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4368		_fsqrt(); // fsqrt
4369		_fdivp(); // fdivp
4370		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4325	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4326	emit_fsqrt(DRCTOP); // fsqrt
	4327	emit_fdivp(DRCTOP); // fdivp
	4328	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4371	4329	}
4372	4330	else /* RSQRT.D */
4373	4331	{
4374		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4375		_fsqrt(); // fsqrt
4376		_fdivp(); // fdivp
4377		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4332	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4333	emit_fsqrt(DRCTOP); // fsqrt
	4334	emit_fdivp(DRCTOP); // fdivp
	4335	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4378	4336	}
4379	4337	return RECOMPILE_SUCCESSFUL_CP(1,4);
4380	4338
r949	r950
4382	4340	if (IS_INTEGRAL(op))
4383	4341	{
4384	4342	if (IS_SINGLE(op)) /* CVT.S.W */
4385		_fild_m32~~abs~~(FPR32(FSREG)); // fild [fsreg]
	4343	emit_fild_m32(DRCTOP, FPR32ADDR(FSREG)); // fild [fsreg]
4386	4344	else /* CVT.S.L */
4387		_fild_m64~~abs~~(FPR64(FSREG)); // fild [fsreg]
	4345	emit_fild_m64(DRCTOP, FPR64ADDR(FSREG)); // fild [fsreg]
4388	4346	}
4389	4347	else /* CVT.S.D */
4390		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4391		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4348	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4349	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4392	4350	return RECOMPILE_SUCCESSFUL_CP(1,4);
4393	4351
4394	4352	case 0x21:
4395	4353	if (IS_INTEGRAL(op))
4396	4354	{
4397	4355	if (IS_SINGLE(op)) /* CVT.D.W */
4398		_fild_m32~~abs~~(FPR32(FSREG)); // fild [fsreg]
	4356	emit_fild_m32(DRCTOP, FPR32ADDR(FSREG)); // fild [fsreg]
4399	4357	else /* CVT.D.L */
4400		_fild_m64~~abs~~(FPR64(FSREG)); // fild [fsreg]
	4358	emit_fild_m64(DRCTOP, FPR64ADDR(FSREG)); // fild [fsreg]
4401	4359	}
4402	4360	else /* CVT.D.S */
4403		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4404		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4361	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4362	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4405	4363	return RECOMPILE_SUCCESSFUL_CP(1,4);
4406	4364
4407	4365	case 0x24:
4408	4366	if (IS_SINGLE(op)) /* CVT.W.S */
4409		_fld_m32~~abs~~(FPR32(FSREG)); // fld [fsreg]
	4367	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4410	4368	else /* CVT.W.D */
4411		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4412		_fistp_m32abs(FPR32(FDREG)); // fistp [fdreg]
	4369	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4370	emit_fistp_m32(DRCTOP, FPR32ADDR(FDREG)); // fistp [fdreg]
4413	4371	return RECOMPILE_SUCCESSFUL_CP(1,4);
4414	4372
4415	4373	case 0x25:
4416	4374	if (IS_SINGLE(op)) /* CVT.L.S */
4417		_fld_m32~~abs~~(FPR32(FSREG)); // fld [fsreg]
	4375	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4418	4376	else /* CVT.L.D */
4419		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4420		_fistp_m64abs(FPR64(FDREG)); // fistp [fdreg]
	4377	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4378	emit_fistp_m64(DRCTOP, FPR64ADDR(FDREG)); // fistp [fdreg]
4421	4379	return RECOMPILE_SUCCESSFUL_CP(1,4);
4422	4380
4423	4381	case 0x30:
4424	4382	case 0x38:
4425		_mov_m8~~abs~~_imm(~~&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_~~TYP~~E_MIPS_IV)~~ ? ((op >> 8) & 7) ~~: 0]~~, 0); /* C.F.S/D */
	4383	emit_mov_m8_imm(DRCTOP, CF1ADDR((op >> 8) & 7), 0); /* C.F.S/D */
4426	4384	return RECOMPILE_SUCCESSFUL_CP(1,4);
4427	4385
4428	4386	case 0x31:
4429	4387	case 0x39:
4430		_mov_m8~~abs~~_imm(~~&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_~~TYP~~E_MIPS_IV)~~ ? ((op >> 8) & 7) ~~: 0]~~, 0); /* C.UN.S/D */
	4388	emit_mov_m8_imm(DRCTOP, CF1ADDR((op >> 8) & 7), 0); /* C.UN.S/D */
4431	4389	return RECOMPILE_SUCCESSFUL_CP(1,4);
4432	4390
4433	4391	case 0x32:
r949	r950
4436	4394	{
4437	4395	if (IS_SINGLE(op)) /* C.EQ.S */
4438	4396	{
4439		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4440		_comiss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // comiss xmm0,[ftreg]
	4397	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4398	emit_comiss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // comiss xmm0,[ftreg]
4441	4399	}
4442	4400	else
4443	4401	{
4444		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4445		_comisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // comisd xmm0,[ftreg]
	4402	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4403	emit_comisd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // comisd xmm0,[ftreg]
4446	4404	}
4447		_setcc_m8~~abs~~(COND_E, ~~&mips3.core->cf[~~1][(~~mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ?~~ ((op >> 8) & 7) ~~: 0]~~); // sete [cf[x]]
	4405	emit_setcc_m8(DRCTOP, COND_E, CF1ADDR((op >> 8) & 7)); // sete [cf[x]]
4448	4406	}
4449	4407	else
4450	4408	{
4451	4409	if (IS_SINGLE(op)) /* C.EQ.S */
4452	4410	{
4453		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4454		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
	4411	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4412	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4455	4413	}
4456	4414	else
4457	4415	{
4458		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4459		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
	4416	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4417	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
4460	4418	}
4461		_fcompp(); // fcompp
4462		_fnstsw_ax(); // fnstsw ax
4463		_sahf(); // sahf
4464		_setcc_m8abs(COND_E, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // sete [cf[x]]
	4419	emit_fcompp(DRCTOP); // fcompp
	4420	emit_fstsw_ax(DRCTOP); // fnstsw ax
	4421	emit_sahf(DRCTOP); // sahf
	4422	emit_setcc_m8(DRCTOP, COND_E, CF1ADDR((op >> 8) & 7)); // sete [cf[x]]
4465	4423	}
4466	4424	return RECOMPILE_SUCCESSFUL_CP(1,4);
4467	4425
r949	r950
4471	4429	{
4472	4430	if (IS_SINGLE(op)) /* C.UEQ.S */
4473	4431	{
4474		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4475		_ucomiss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // ucomiss xmm0,[ftreg]
	4432	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4433	emit_ucomiss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // ucomiss xmm0,[ftreg]
4476	4434	}
4477	4435	else
4478	4436	{
4479		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4480		_ucomisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // ucomisd xmm0,[ftreg]
	4437	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4438	emit_ucomisd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // ucomisd xmm0,[ftreg]
4481	4439	}
4482		_setcc_m8~~abs~~(COND_E, ~~&mips3.core->cf[~~1][(~~mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ?~~ ((op >> 8) & 7) ~~: 0]~~); // sete [cf[x]]
	4440	emit_setcc_m8(DRCTOP, COND_E, CF1ADDR((op >> 8) & 7)); // sete [cf[x]]
4483	4441	}
4484	4442	else
4485	4443	{
4486	4444	if (IS_SINGLE(op)) /* C.UEQ.S */
4487	4445	{
4488		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4489		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
	4446	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4447	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4490	4448	}
4491	4449	else
4492	4450	{
4493		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4494		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
	4451	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4452	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
4495	4453	}
4496		_fucompp(); // fucompp
4497		_fnstsw_ax(); // fnstsw ax
4498		_sahf(); // sahf
4499		_setcc_m8abs(COND_E, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // sete [cf[x]]
	4454	emit_fucompp(DRCTOP); // fucompp
	4455	emit_fstsw_ax(DRCTOP); // fnstsw ax
	4456	emit_sahf(DRCTOP); // sahf
	4457	emit_setcc_m8(DRCTOP, COND_E, CF1ADDR((op >> 8) & 7)); // sete [cf[x]]
4500	4458	}
4501	4459	return RECOMPILE_SUCCESSFUL_CP(1,4);
4502	4460
r949	r950
4506	4464	{
4507	4465	if (IS_SINGLE(op)) /* C.OLT.S */
4508	4466	{
4509		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4510		_comiss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // comiss xmm0,[ftreg]
	4467	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4468	emit_comiss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // comiss xmm0,[ftreg]
4511	4469	}
4512	4470	else
4513	4471	{
4514		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4515		_comisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // comisd xmm0,[ftreg]
	4472	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4473	emit_comisd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // comisd xmm0,[ftreg]
4516	4474	}
4517		_setcc_m8~~abs~~(COND_B, ~~&mips3.core->cf[~~1][(~~mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ?~~ ((op >> 8) & 7) ~~: 0]~~); // setb [cf[x]]
	4475	emit_setcc_m8(DRCTOP, COND_B, CF1ADDR((op >> 8) & 7)); // setb [cf[x]]
4518	4476	}
4519	4477	else
4520	4478	{
4521	4479	if (IS_SINGLE(op)) /* C.OLT.S */
4522	4480	{
4523		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4524		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
	4481	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4482	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4525	4483	}
4526	4484	else
4527	4485	{
4528		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4529		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
	4486	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4487	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
4530	4488	}
4531		_fcompp(); // fcompp
4532		_fnstsw_ax(); // fnstsw ax
4533		_sahf(); // sahf
4534		_setcc_m8abs(COND_B, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setb [cf[x]]
	4489	emit_fcompp(DRCTOP); // fcompp
	4490	emit_fstsw_ax(DRCTOP); // fnstsw ax
	4491	emit_sahf(DRCTOP); // sahf
	4492	emit_setcc_m8(DRCTOP, COND_B, CF1ADDR((op >> 8) & 7)); // setb [cf[x]]
4535	4493	}
4536	4494	return RECOMPILE_SUCCESSFUL_CP(1,4);
4537	4495
r949	r950
4541	4499	{
4542	4500	if (IS_SINGLE(op)) /* C.ULT.S */
4543	4501	{
4544		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4545		_ucomiss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // ucomiss xmm0,[ftreg]
	4502	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4503	emit_ucomiss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // ucomiss xmm0,[ftreg]
4546	4504	}
4547	4505	else
4548	4506	{
4549		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4550		_ucomisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // ucomisd xmm0,[ftreg]
	4507	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4508	emit_ucomisd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // ucomisd xmm0,[ftreg]
4551	4509	}
4552		_setcc_m8~~abs~~(COND_B, ~~&mips3.core->cf[~~1][(~~mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ?~~ ((op >> 8) & 7) ~~: 0]~~); // setb [cf[x]]
	4510	emit_setcc_m8(DRCTOP, COND_B, CF1ADDR((op >> 8) & 7)); // setb [cf[x]]
4553	4511	}
4554	4512	else
4555	4513	{
4556	4514	if (IS_SINGLE(op)) /* C.ULT.S */
4557	4515	{
4558		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4559		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
	4516	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4517	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4560	4518	}
4561	4519	else
4562	4520	{
4563		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4564		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
	4521	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4522	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
4565	4523	}
4566		_fucompp(); // fucompp
4567		_fnstsw_ax(); // fnstsw ax
4568		_sahf(); // sahf
4569		_setcc_m8abs(COND_B, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setb [cf[x]]
	4524	emit_fucompp(DRCTOP); // fucompp
	4525	emit_fstsw_ax(DRCTOP); // fnstsw ax
	4526	emit_sahf(DRCTOP); // sahf
	4527	emit_setcc_m8(DRCTOP, COND_B, CF1ADDR((op >> 8) & 7)); // setb [cf[x]]
4570	4528	}
4571	4529	return RECOMPILE_SUCCESSFUL_CP(1,4);
4572	4530
r949	r950
4576	4534	{
4577	4535	if (IS_SINGLE(op)) /* C.OLE.S */
4578	4536	{
4579		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4580		_comiss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // comiss xmm0,[ftreg]
	4537	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4538	emit_comiss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // comiss xmm0,[ftreg]
4581	4539	}
4582	4540	else
4583	4541	{
4584		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4585		_comisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // comisd xmm0,[ftreg]
	4542	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4543	emit_comisd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // comisd xmm0,[ftreg]
4586	4544	}
4587		_setcc_m8~~abs~~(COND_BE, ~~&mips3.core->cf[~~1][(~~mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ?~~ ((op >> 8) & 7) ~~: 0]~~); // setle [cf[x]]
	4545	emit_setcc_m8(DRCTOP, COND_BE, CF1ADDR((op >> 8) & 7)); // setle [cf[x]]
4588	4546	}
4589	4547	else
4590	4548	{
4591	4549	if (IS_SINGLE(op)) /* C.OLE.S */
4592	4550	{
4593		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4594		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
	4551	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4552	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4595	4553	}
4596	4554	else
4597	4555	{
4598		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4599		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
	4556	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4557	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
4600	4558	}
4601		_fcompp(); // fcompp
4602		_fnstsw_ax(); // fnstsw ax
4603		_sahf(); // sahf
4604		_setcc_m8abs(COND_BE, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setbe [cf[x]]
	4559	emit_fcompp(DRCTOP); // fcompp
	4560	emit_fstsw_ax(DRCTOP); // fnstsw ax
	4561	emit_sahf(DRCTOP); // sahf
	4562	emit_setcc_m8(DRCTOP, COND_BE, CF1ADDR((op >> 8) & 7)); // setbe [cf[x]]
4605	4563	}
4606	4564	return RECOMPILE_SUCCESSFUL_CP(1,4);
4607	4565
r949	r950
4611	4569	{
4612	4570	if (IS_SINGLE(op)) /* C.ULE.S */
4613	4571	{
4614		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4615		_ucomiss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // ucomiss xmm0,[ftreg]
	4572	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4573	emit_ucomiss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // ucomiss xmm0,[ftreg]
4616	4574	}
4617	4575	else
4618	4576	{
4619		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4620		_ucomisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // ucomisd xmm0,[ftreg]
	4577	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4578	emit_ucomisd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // ucomisd xmm0,[ftreg]
4621	4579	}
4622		_setcc_m8~~abs~~(COND_BE, ~~&mips3.core->cf[~~1][(~~mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ?~~ ((op >> 8) & 7) ~~: 0]~~); // setl [cf[x]]
	4580	emit_setcc_m8(DRCTOP, COND_BE, CF1ADDR((op >> 8) & 7)); // setl [cf[x]]
4623	4581	}
4624	4582	else
4625	4583	{
4626	4584	if (IS_SINGLE(op)) /* C.ULE.S */
4627	4585	{
4628		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4629		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
	4586	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4587	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
4630	4588	}
4631	4589	else
4632	4590	{
4633		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4634		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
	4591	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4592	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
4635	4593	}
4636		_fucompp(); // fucompp
4637		_fnstsw_ax(); // fnstsw ax
4638		_sahf(); // sahf
4639		_setcc_m8abs(COND_BE, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setbe [cf[x]]
	4594	emit_fucompp(DRCTOP); // fucompp
	4595	emit_fstsw_ax(DRCTOP); // fnstsw ax
	4596	emit_sahf(DRCTOP); // sahf
	4597	emit_setcc_m8(DRCTOP, COND_BE, CF1ADDR((op >> 8) & 7)); // setbe [cf[x]]
4640	4598	}
4641	4599	return RECOMPILE_SUCCESSFUL_CP(1,4);
4642	4600	}
4643	4601	break;
4644	4602	}
4645		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	4603	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
4646	4604	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4647	4605	}
4648	4606
r949	r950
4660	4618	{
4661	4619	if (mips3.drcoptions & MIPS3DRC_STRICT_COP1)
4662	4620	{
4663		_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_COP1); // test [mips3.core->cpr[0][COP0_Status]],SR_COP1
4664		_jcc(COND_Z, mips3.drcdata->generate_cop_exception); // jz generate_cop_exception
	4621	emit_test_m32_imm(DRCTOP, CPR0ADDR(COP0_Status), SR_COP1); // test [COP0_Status],SR_COP1
	4622	emit_jcc(DRCTOP, COND_Z, mips3.drcdata->generate_cop_exception); // jz generate_cop_exception
4665	4623	}
4666	4624
4667	4625	switch (op & 0x3f)
4668	4626	{
4669	4627	case 0x00: /* LWXC1 */
4670		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
4671		_save_pc_before_call(); // save pc
4672		_sub_r32_imm(REG_ESP, 8); // sub esp,8
4673		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
4674		_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg]
4675		_push_r32(REG_EAX); // push eax
4676		_call(mips3.drcdata->read_and_translate_long); // call read_and_translate_long
4677		_add_r32_imm(REG_ESP, 12); // add esp,12
4678		_mov_m32abs_r32(FPR32(FDREG), REG_EAX); // mov [fdreg],eax
4679		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	4628	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	4629	emit_save_pc_before_call(DRCTOP); // save pc
	4630	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
	4631	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg]
	4632	emit_add_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // add eax,[rtreg]
	4633	emit_push_r32(DRCTOP, REG_EAX); // push eax
	4634	emit_call(DRCTOP, mips3.drcdata->read_and_translate_long); // call read_and_translate_long
	4635	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	4636	emit_mov_m32_r32(DRCTOP, FPR32ADDR(FDREG), REG_EAX); // mov [fdreg],eax
	4637	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
4680	4638	return RECOMPILE_SUCCESSFUL_CP(1,4);
4681	4639
4682	4640	case 0x01: /* LDXC1 */
4683		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
4684		_save_pc_before_call(); // save pc
4685		_sub_r32_imm(REG_ESP, 8); // sub esp,8
4686		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
4687		_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg]
4688		_push_r32(REG_EAX); // push eax
4689		_call(mips3.drcdata->read_and_translate_double); // call read_and_translate_double
4690		_mov_m32abs_r32(LO(FPR64(FDREG)), REG_EAX); // mov [fdreg].lo,eax
4691		_mov_m32abs_r32(HI(FPR64(FDREG)), REG_EDX); // mov [fdreg].hi,edx
4692		_add_r32_imm(REG_ESP, 12); // add esp,12
4693		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	4641	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	4642	emit_save_pc_before_call(DRCTOP); // save pc
	4643	emit_sub_r32_imm(DRCTOP, REG_ESP, 8); // sub esp,8
	4644	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg]
	4645	emit_add_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // add eax,[rtreg]
	4646	emit_push_r32(DRCTOP, REG_EAX); // push eax
	4647	emit_call(DRCTOP, mips3.drcdata->read_and_translate_double); // call read_and_translate_double
	4648	emit_mov_m32_r32(DRCTOP, FPR64ADDRLO(FDREG), REG_EAX); // mov [fdreg].lo,eax
	4649	emit_mov_m32_r32(DRCTOP, FPR64ADDRHI(FDREG), REG_EDX); // mov [fdreg].hi,edx
	4650	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	4651	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
4694	4652	return RECOMPILE_SUCCESSFUL_CP(1,4);
4695	4653
4696	4654	case 0x08: /* SWXC1 */
4697		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
4698		_save_pc_before_call(); // save pc
4699		_sub_r32_imm(REG_ESP, 4); // sub esp,4
4700		_push_m32abs(FPR32(FSREG)); // push [fsreg]
4701		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
4702		_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg]
4703		_push_r32(REG_EAX); // push eax
4704		_call(mips3.drcdata->write_and_translate_long); // call write_and_translate_long
4705		_add_r32_imm(REG_ESP, 12); // add esp,8
4706		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	4655	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	4656	emit_save_pc_before_call(DRCTOP); // save pc
	4657	emit_sub_r32_imm(DRCTOP, REG_ESP, 4); // sub esp,4
	4658	emit_push_m32(DRCTOP, FPR32ADDR(FSREG)); // push [fsreg]
	4659	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg]
	4660	emit_add_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // add eax,[rtreg]
	4661	emit_push_r32(DRCTOP, REG_EAX); // push eax
	4662	emit_call(DRCTOP, mips3.drcdata->write_and_translate_long); // call write_and_translate_long
	4663	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,8
	4664	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
4707	4665	return RECOMPILE_SUCCESSFUL_CP(1,4);
4708	4666
4709	4667	case 0x09: /* SDXC1 */
4710		// REVISIT: does this actually work?
4711		// Two 32-bit words are pushed, before the call, but three are popped afterwards!
4712		// This, as far as I can see, will kill off the return address.
4713		// All other calls to mips3.drcdata->write_and_translate_double take three 32-bit words as arguments.
4714		// So is one argument too few being pushed, or is one too many being popped?
4715		_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
4716		_save_pc_before_call(); // save pc
4717		_push_m32abs(HI(FPR64(FSREG))); // push [fsreg].hi
4718		_push_m32abs(LO(FPR64(FSREG))); // push [fsreg].lo
4719		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
4720		_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg]
4721		_call(mips3.drcdata->write_and_translate_double); // call write_and_translate_double
4722		_add_r32_imm(REG_ESP, 12); // add esp,12
4723		_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
	4668	emit_mov_m32_r32(DRCTOP, ICOUNTADDR, REG_EBP); // mov [icount],ebp
	4669	emit_save_pc_before_call(DRCTOP); // save pc
	4670	emit_push_m32(DRCTOP, FPR64ADDRHI(FSREG)); // push [fsreg].hi
	4671	emit_push_m32(DRCTOP, FPR64ADDRLO(FSREG)); // push [fsreg].lo
	4672	emit_mov_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RSREG)); // mov eax,[rsreg]
	4673	emit_add_r32_m32(DRCTOP, REG_EAX, REGADDRLO(RTREG)); // add eax,[rtreg]
	4674	emit_push_r32(DRCTOP, REG_EAX); // push eax
	4675	emit_call(DRCTOP, mips3.drcdata->write_and_translate_double); // call write_and_translate_double
	4676	emit_add_r32_imm(DRCTOP, REG_ESP, 12); // add esp,12
	4677	emit_mov_r32_m32(DRCTOP, REG_EBP, ICOUNTADDR); // mov ebp,[icount]
4724	4678	return RECOMPILE_SUCCESSFUL_CP(1,4);
4725	4679
4726	4680	case 0x0f: /* PREFX */
r949	r950
4729	4683	case 0x20: /* MADD.S */
4730	4684	if (USE_SSE)
4731	4685	{
4732		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4733		_mulss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // mulss xmm0,[ftreg]
4734		_addss_r128_m32abs(REG_XMM0, FPR32(FRREG)); // addss xmm0,[frreg]
4735		_movss_m32abs_r128(FPR32(FDREG), REG_XMM0); // movss [fdreg],xmm0
	4686	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4687	emit_mulss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // mulss xmm0,[ftreg]
	4688	emit_addss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FRREG)); // addss xmm0,[frreg]
	4689	emit_movss_m32_r128(DRCTOP, FPR32ADDR(FDREG), REG_XMM0); // movss [fdreg],xmm0
4736	4690	}
4737	4691	else
4738	4692	{
4739		_fld_m32abs(FPR32(FRREG)); // fld [frreg]
4740		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4741		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4742		_fmulp(); // fmulp
4743		_faddp(); // faddp
4744		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4693	emit_fld_m32(DRCTOP, FPR32ADDR(FRREG)); // fld [frreg]
	4694	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4695	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4696	emit_fmulp(DRCTOP); // fmulp
	4697	emit_faddp(DRCTOP); // faddp
	4698	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4745	4699	}
4746	4700	return RECOMPILE_SUCCESSFUL_CP(1,4);
4747	4701
4748	4702	case 0x21: /* MADD.D */
4749	4703	if (USE_SSE)
4750	4704	{
4751		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4752		_mulsd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // mulsd xmm0,[ftreg]
4753		_addsd_r128_m64abs(REG_XMM0, FPR64(FRREG)); // addsd xmm0,[frreg]
4754		_movsd_m64abs_r128(FPR64(FDREG), REG_XMM0); // movsd [fdreg],xmm0
	4705	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4706	emit_mulsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // mulsd xmm0,[ftreg]
	4707	emit_addsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FRREG)); // addsd xmm0,[frreg]
	4708	emit_movsd_m64_r128(DRCTOP, FPR64ADDR(FDREG), REG_XMM0); // movsd [fdreg],xmm0
4755	4709	}
4756	4710	else
4757	4711	{
4758		_fld_m64abs(FPR64(FRREG)); // fld [frreg]
4759		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4760		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4761		_fmulp(); // fmulp
4762		_faddp(); // faddp
4763		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4712	emit_fld_m64(DRCTOP, FPR64ADDR(FRREG)); // fld [frreg]
	4713	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4714	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4715	emit_fmulp(DRCTOP); // fmulp
	4716	emit_faddp(DRCTOP); // faddp
	4717	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4764	4718	}
4765	4719	return RECOMPILE_SUCCESSFUL_CP(1,4);
4766	4720
4767	4721	case 0x28: /* MSUB.S */
4768	4722	if (USE_SSE)
4769	4723	{
4770		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4771		_mulss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // mulss xmm0,[ftreg]
4772		_subss_r128_m32abs(REG_XMM0, FPR32(FRREG)); // subss xmm0,[frreg]
4773		_movss_m32abs_r128(FPR32(FDREG), REG_XMM0); // movss [fdreg],xmm0
	4724	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4725	emit_mulss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // mulss xmm0,[ftreg]
	4726	emit_subss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FRREG)); // subss xmm0,[frreg]
	4727	emit_movss_m32_r128(DRCTOP, FPR32ADDR(FDREG), REG_XMM0); // movss [fdreg],xmm0
4774	4728	}
4775	4729	else
4776	4730	{
4777		_fld_m32abs(FPR32(FRREG)); // fld [frreg]
4778		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4779		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4780		_fmulp(); // fmulp
4781		_fsubrp(); // fsubrp
4782		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4731	emit_fld_m32(DRCTOP, FPR32ADDR(FRREG)); // fld [frreg]
	4732	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4733	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4734	emit_fmulp(DRCTOP); // fmulp
	4735	emit_fsubrp(DRCTOP); // fsubrp
	4736	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4783	4737	}
4784	4738	return RECOMPILE_SUCCESSFUL_CP(1,4);
4785	4739
4786	4740	case 0x29: /* MSUB.D */
4787	4741	if (USE_SSE)
4788	4742	{
4789		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4790		_mulsd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // mulsd xmm0,[ftreg]
4791		_subsd_r128_m64abs(REG_XMM0, FPR64(FRREG)); // subsd xmm0,[frreg]
4792		_movsd_m64abs_r128(FPR64(FDREG), REG_XMM0); // movsd [fdreg],xmm0
	4743	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4744	emit_mulsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // mulsd xmm0,[ftreg]
	4745	emit_subsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FRREG)); // subsd xmm0,[frreg]
	4746	emit_movsd_m64_r128(DRCTOP, FPR64ADDR(FDREG), REG_XMM0); // movsd [fdreg],xmm0
4793	4747	}
4794	4748	else
4795	4749	{
4796		_fld_m64abs(FPR64(FRREG)); // fld [frreg]
4797		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4798		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4799		_fmulp(); // fmulp
4800		_fsubrp(); // fsubrp
4801		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4750	emit_fld_m64(DRCTOP, FPR64ADDR(FRREG)); // fld [frreg]
	4751	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4752	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4753	emit_fmulp(DRCTOP); // fmulp
	4754	emit_fsubrp(DRCTOP); // fsubrp
	4755	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4802	4756	}
4803	4757	return RECOMPILE_SUCCESSFUL_CP(1,4);
4804	4758
4805	4759	case 0x30: /* NMADD.S */
4806	4760	if (USE_SSE)
4807	4761	{
4808		_pxor_r128_r128(REG_XMM1, REG_XMM1); // pxor xmm1,xmm1
4809		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4810		_mulss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // mulss xmm0,[ftreg]
4811		_addss_r128_m32abs(REG_XMM0, FPR32(FRREG)); // addss xmm0,[frreg]
4812		_subss_r128_r128(REG_XMM1, REG_XMM0); // subss xmm1,xmm0
4813		_movss_m32abs_r128(FPR32(FDREG), REG_XMM1); // movss [fdreg],xmm1
	4762	emit_xorps_r128_r128(DRCTOP, REG_XMM1, REG_XMM1); // xorps xmm1,xmm1
	4763	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4764	emit_mulss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // mulss xmm0,[ftreg]
	4765	emit_addss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FRREG)); // addss xmm0,[frreg]
	4766	emit_subss_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // subss xmm1,xmm0
	4767	emit_movss_m32_r128(DRCTOP, FPR32ADDR(FDREG), REG_XMM1); // movss [fdreg],xmm1
4814	4768	}
4815	4769	else
4816	4770	{
4817		_fld_m32abs(FPR32(FRREG)); // fld [frreg]
4818		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4819		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4820		_fmulp(); // fmulp
4821		_faddp(); // faddp
4822		_fchs(); // fchs
4823		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4771	emit_fld_m32(DRCTOP, FPR32ADDR(FRREG)); // fld [frreg]
	4772	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4773	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4774	emit_fmulp(DRCTOP); // fmulp
	4775	emit_faddp(DRCTOP); // faddp
	4776	emit_fchs(DRCTOP); // fchs
	4777	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4824	4778	}
4825	4779	return RECOMPILE_SUCCESSFUL_CP(1,4);
4826	4780
4827	4781	case 0x31: /* NMADD.D */
4828	4782	if (USE_SSE)
4829	4783	{
4830		_pxor_r128_r128(REG_XMM1, REG_XMM1); // pxor xmm1,xmm1
4831		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4832		_mulsd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // mulsd xmm0,[ftreg]
4833		_addsd_r128_m64abs(REG_XMM0, FPR64(FRREG)); // addsd xmm0,[frreg]
4834		_subss_r128_r128(REG_XMM1, REG_XMM0); // subss xmm1,xmm0
4835		_movsd_m64abs_r128(FPR64(FDREG), REG_XMM1); // movsd [fdreg],xmm1
	4784	emit_xorps_r128_r128(DRCTOP, REG_XMM1, REG_XMM1); // xorps xmm1,xmm1
	4785	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4786	emit_mulsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // mulsd xmm0,[ftreg]
	4787	emit_addsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FRREG)); // addsd xmm0,[frreg]
	4788	emit_subss_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // subss xmm1,xmm0
	4789	emit_movsd_m64_r128(DRCTOP, FPR64ADDR(FDREG), REG_XMM1); // movsd [fdreg],xmm1
4836	4790	}
4837	4791	else
4838	4792	{
4839		_fld_m64abs(FPR64(FRREG)); // fld [frreg]
4840		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4841		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4842		_fmulp(); // fmulp
4843		_faddp(); // faddp
4844		_fchs(); // fchs
4845		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4793	emit_fld_m64(DRCTOP, FPR64ADDR(FRREG)); // fld [frreg]
	4794	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4795	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4796	emit_fmulp(DRCTOP); // fmulp
	4797	emit_faddp(DRCTOP); // faddp
	4798	emit_fchs(DRCTOP); // fchs
	4799	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4846	4800	}
4847	4801	return RECOMPILE_SUCCESSFUL_CP(1,4);
4848	4802
4849	4803	case 0x38: /* NMSUB.S */
4850	4804	if (USE_SSE)
4851	4805	{
4852		_movss_r128_m32abs(REG_XMM0, FPR32(FSREG)); // movss xmm0,[fsreg]
4853		_mulss_r128_m32abs(REG_XMM0, FPR32(FTREG)); // mulss xmm0,[ftreg]
4854		_movss_r128_m32abs(REG_XMM1, FPR32(FRREG)); // movss xmm1,[frreg]
4855		_subss_r128_r128(REG_XMM1, REG_XMM0); // subss xmm1,xmm0
4856		_movss_m32abs_r128(FPR32(FDREG), REG_XMM1); // movss [fdreg],xmm1
	4806	emit_movss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FSREG)); // movss xmm0,[fsreg]
	4807	emit_mulss_r128_m32(DRCTOP, REG_XMM0, FPR32ADDR(FTREG)); // mulss xmm0,[ftreg]
	4808	emit_movss_r128_m32(DRCTOP, REG_XMM1, FPR32ADDR(FRREG)); // movss xmm1,[frreg]
	4809	emit_subss_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // subss xmm1,xmm0
	4810	emit_movss_m32_r128(DRCTOP, FPR32ADDR(FDREG), REG_XMM1); // movss [fdreg],xmm1
4857	4811	}
4858	4812	else
4859	4813	{
4860		_fld_m32abs(FPR32(FRREG)); // fld [frreg]
4861		_fld_m32abs(FPR32(FSREG)); // fld [fsreg]
4862		_fld_m32abs(FPR32(FTREG)); // fld [ftreg]
4863		_fmulp(); // fmulp
4864		_fsubp(); // fsubp
4865		_fstp_m32abs(FPR32(FDREG)); // fstp [fdreg]
	4814	emit_fld_m32(DRCTOP, FPR32ADDR(FRREG)); // fld [frreg]
	4815	emit_fld_m32(DRCTOP, FPR32ADDR(FSREG)); // fld [fsreg]
	4816	emit_fld_m32(DRCTOP, FPR32ADDR(FTREG)); // fld [ftreg]
	4817	emit_fmulp(DRCTOP); // fmulp
	4818	emit_fsubp(DRCTOP); // fsubp
	4819	emit_fstp_m32(DRCTOP, FPR32ADDR(FDREG)); // fstp [fdreg]
4866	4820	}
4867	4821	return RECOMPILE_SUCCESSFUL_CP(1,4);
4868	4822
4869	4823	case 0x39: /* NMSUB.D */
4870	4824	if (USE_SSE)
4871	4825	{
4872		_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4873		_mulsd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // mulsd xmm0,[ftreg]
4874		_movsd_r128_m64abs(REG_XMM1, FPR64(FRREG)); // movsd xmm1,[frreg]
4875		_subss_r128_r128(REG_XMM1, REG_XMM0); // subss xmm1,xmm0
4876		_movsd_m64abs_r128(FPR64(FDREG), REG_XMM1); // movsd [fdreg],xmm1
	4826	emit_movsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FSREG)); // movsd xmm0,[fsreg]
	4827	emit_mulsd_r128_m64(DRCTOP, REG_XMM0, FPR64ADDR(FTREG)); // mulsd xmm0,[ftreg]
	4828	emit_movsd_r128_m64(DRCTOP, REG_XMM1, FPR64ADDR(FRREG)); // movsd xmm1,[frreg]
	4829	emit_subss_r128_r128(DRCTOP, REG_XMM1, REG_XMM0); // subss xmm1,xmm0
	4830	emit_movsd_m64_r128(DRCTOP, FPR64ADDR(FDREG), REG_XMM1); // movsd [fdreg],xmm1
4877	4831	}
4878	4832	else
4879	4833	{
4880		_fld_m64abs(FPR64(FRREG)); // fld [frreg]
4881		_fld_m64abs(FPR64(FSREG)); // fld [fsreg]
4882		_fld_m64abs(FPR64(FTREG)); // fld [ftreg]
4883		_fmulp(); // fmulp
4884		_fsubp(); // fsubrp
4885		_fstp_m64abs(FPR64(FDREG)); // fstp [fdreg]
	4834	emit_fld_m64(DRCTOP, FPR64ADDR(FRREG)); // fld [frreg]
	4835	emit_fld_m64(DRCTOP, FPR64ADDR(FSREG)); // fld [fsreg]
	4836	emit_fld_m64(DRCTOP, FPR64ADDR(FTREG)); // fld [ftreg]
	4837	emit_fmulp(DRCTOP); // fmulp
	4838	emit_fsubp(DRCTOP); // fsubrp
	4839	emit_fstp_m64(DRCTOP, FPR64ADDR(FDREG)); // fstp [fdreg]
4886	4840	}
4887	4841	return RECOMPILE_SUCCESSFUL_CP(1,4);
4888	4842
r949	r950
4898	4852	fprintf(stderr, "cop1x %X\n", op);
4899	4853	break;
4900	4854	}
4901		_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
	4855	emit_jmp(DRCTOP, (void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
4902	4856	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4903	4857	}

src/emu/cpu/mips/mips3drc.c
r949	r950
307	307	code_log - actually log some code
308	308	-------------------------------------------------*/
309	309
310		static void code_log(const char label, void start, void *stop)
	310	static void code_log(const char label, x86code start, x86code *stop)
311	311	{
312	312	extern int i386_dasm_one(char buffer, UINT32 eip, UINT8 oprom, int mode);
313	313	extern unsigned dasmmips3(char *buffer, unsigned pc, UINT32 op);
r949	r950
319	319	fprintf(logfile, "\n%s\n", label);
320	320
321	321	/* loop from the start until the cache top */
322		while (cur < ~~(UINT8 *)~~stop)
	322	while (cur < stop)
323	323	{
324	324	char buffer[100];
325	325	int bytes;

src/emu/cpu/x86emit.h
r949	r950
4	4
5	5	Generic x86/x64 code emitters.
6	6
7		Copyright (c) 1996-2007, Nicola Salmoria and the MAME Team.
	7	Copyright (c) 2007, Aaron Giles
	8	Released for general use under the MAME license
8	9	Visit http://mamedev.org for licensing and usage restrictions.
9	10
10	11	****************************************************************************
r949	r950
17	18
18	19	***************************************************************************/
19	20
	21	#ifndef __X86EMIT_H__
	22	#define __X86EMIT_H__
20	23
	24
21	25	/***************************************************************************
22	26	CONSTANTS
23	27	***************************************************************************/
24	28
25		/* 32-bit versus 64-bit opcode flag */
26		#define OP_32BIT 0
27		#define OP_64BIT 8
	29	/* opcode size flag; low 4 bits must match REX low 4 bits, hence the odd numbers here */
	30	#define OP_16BIT 0x10
	31	#define OP_32BIT 0x00
	32	#define OP_64BIT 0x08
28	33
29
30	34	/* 16 registers on x64, only 8 on x86 */
31	35	#ifdef PTR64
32	36	#define REG_MAX 16
r949	r950
34	38	#define REG_MAX 8
35	39	#endif
36	40
37
38	41	/* invalid register index for "none" */
39	42	#define REG_NONE REG_MAX
40	43
	44	/* 8-bit registers -- note that we assume a flat model for 64-bit */
	45	#define REG_AL 0
	46	#define REG_CL 1
	47	#define REG_DL 2
	48	#define REG_BL 3
	49	#ifndef PTR64
	50	#define REG_AH 4
	51	#define REG_CH 5
	52	#define REG_DH 6
	53	#define REG_BH 7
	54	#else
	55	#define REG_SPL 4
	56	#define REG_BPL 5
	57	#define REG_SIL 6
	58	#define REG_DIL 7
	59	#define REG_R8L 8
	60	#define REG_R9L 9
	61	#define REG_R10L 10
	62	#define REG_R11L 11
	63	#define REG_R12L 12
	64	#define REG_R13L 13
	65	#define REG_R14L 14
	66	#define REG_R15L 15
	67	#endif
41	68
42		/* 64-bit registers */
	69	/* 16-bit registers */
	70	#define REG_AX 0
	71	#define REG_CX 1
	72	#define REG_DX 2
	73	#define REG_BX 3
	74	#define REG_SP 4
	75	#define REG_BP 5
	76	#define REG_SI 6
	77	#define REG_DI 7
43	78	#ifdef PTR64
44		#define REG_RAX 0
45		#define REG_RCX 1
46		#define REG_RDX 2
47		#define REG_RBX 3
48		#define REG_RSP 4
49		#define REG_RBP 5
50		#define REG_RSI 6
51		#define REG_RDI 7
52		#define REG_R8 8
53		#define REG_R9 9
54		#define REG_R10 10
55		#define REG_R11 11
56		#define REG_R12 12
57		#define REG_R13 13
58		#define REG_R14 14
59		#define REG_R15 15
	79	#define REG_R8W 8
	80	#define REG_R9W 9
	81	#define REG_R10W 10
	82	#define REG_R11W 11
	83	#define REG_R12W 12
	84	#define REG_R13W 13
	85	#define REG_R14W 14
	86	#define REG_R15W 15
60	87	#endif
61	88
62	89	/* 32-bit registers */
r949	r950
79	106	#define REG_R15D 15
80	107	#endif
81	108
82		/* 16-bit registers */
83		#define REG_AX 0
84		#define REG_CX 1
85		#define REG_DX 2
86		#define REG_BX 3
87		#define REG_SP 4
88		#define REG_BP 5
89		#define REG_SI 6
90		#define REG_DI 7
	109	/* 64-bit registers */
91	110	#ifdef PTR64
92		#define REG_R8W 8
93		#define REG_R9W 9
94		#define REG_R10W 10
95		#define REG_R11W 11
96		#define REG_R12W 12
97		#define REG_R13W 13
98		#define REG_R14W 14
99		#define REG_R15W 15
	111	#define REG_RAX 0
	112	#define REG_RCX 1
	113	#define REG_RDX 2
	114	#define REG_RBX 3
	115	#define REG_RSP 4
	116	#define REG_RBP 5
	117	#define REG_RSI 6
	118	#define REG_RDI 7
	119	#define REG_R8 8
	120	#define REG_R9 9
	121	#define REG_R10 10
	122	#define REG_R11 11
	123	#define REG_R12 12
	124	#define REG_R13 13
	125	#define REG_R14 14
	126	#define REG_R15 15
100	127	#endif
101	128
102		/* 8-bit registers */
103		#define REG_AL 0
104		#define REG_CL 1
105		#define REG_DL 2
106		#define REG_BL 3
107		#ifndef PTR64
108		#define REG_AH 4
109		#define REG_CH 5
110		#define REG_DH 6
111		#define REG_BH 7
112		#else
113		#define REG_SPL 4
114		#define REG_BPL 5
115		#define REG_SIL 6
116		#define REG_DIL 7
117		#define REG_R8L 8
118		#define REG_R9L 9
119		#define REG_R10L 10
120		#define REG_R11L 11
121		#define REG_R12L 12
122		#define REG_R13L 13
123		#define REG_R14L 14
124		#define REG_R15L 15
125		#endif
126
127	129	/* 64-bit MMX registers */
128	130	#define REG_MM0 0
129	131	#define REG_MM1 1
r949	r950
164	166	#define REG_XMM15 15
165	167	#endif
166	168
167
168	169	/* conditions */
169	170	#define COND_A 7
170	171	#define COND_AE 3
r949	r950
198	199	#define COND_S 8
199	200	#define COND_Z 4
200	201
201
202	202	/* floating point rounding modes */
203	203	#define FPRND_NEAR 0
204	204	#define FPRND_DOWN 1
r949	r950
206	206	#define FPRND_CHOP 3
207	207
208	208
	209
	210	/***************************************************************************
	211	OPCODE DEFINITIONS
	212	***************************************************************************/
	213
209	214	/* opcode flags (in upper 8 bits of opcode) */
210	215	#define OPFLAG_8BITREG (1 << 24)
211	216	#define OPFLAG_8BITRM (1 << 25)
212	217
213
214	218	/* single byte opcodes */
215		#define OP_ADD_Eb_Gb 0x00 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	219	#define OP_ADD_Eb_Gb (0x00 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
216	220	#define OP_ADD_Ev_Gv 0x01
217		#define OP_ADD_Gb_Eb 0x02 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	221	#define OP_ADD_Gb_Eb (0x02 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
218	222	#define OP_ADD_Gv_Ev 0x03
219	223	#define OP_ADD_AL_Ib 0x04
220	224	#define OP_ADD_rAX_Iz 0x05
221	225	#define OP_PUSH_ES 0x06
222	226	#define OP_POP_ES 0x07
223		#define OP_OR_Eb_Gb 0x08 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	227	#define OP_OR_Eb_Gb (0x08 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
224	228	#define OP_OR_Ev_Gv 0x09
225		#define OP_OR_Gb_Eb 0x0a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	229	#define OP_OR_Gb_Eb (0x0a \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
226	230	#define OP_OR_Gv_Ev 0x0b
227	231	#define OP_OR_AL_Ib 0x0c
228	232	#define OP_OR_eAX_Iv 0x0d
229	233	#define OP_PUSH_CS 0x0e
230	234	#define OP_EXTENDED 0x0f
231	235
232		#define OP_ADC_Eb_Gb 0x10 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	236	#define OP_ADC_Eb_Gb (0x10 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
233	237	#define OP_ADC_Ev_Gv 0x11
234		#define OP_ADC_Gb_Eb 0x12 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	238	#define OP_ADC_Gb_Eb (0x12 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
235	239	#define OP_ADC_Gv_Ev 0x13
236	240	#define OP_ADC_AL_Ib 0x14
237	241	#define OP_ADC_rAX_Iz 0x15
238	242	#define OP_PUSH_SS 0x16
239	243	#define OP_POP_SS 0x17
240		#define OP_SBB_Eb_Gb 0x18 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	244	#define OP_SBB_Eb_Gb (0x18 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
241	245	#define OP_SBB_Ev_Gv 0x19
242		#define OP_SBB_Gb_Eb 0x1a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	246	#define OP_SBB_Gb_Eb (0x1a \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
243	247	#define OP_SBB_Gv_Ev 0x1b
244	248	#define OP_SBB_AL_Ib 0x1c
245	249	#define OP_SBB_eAX_Iv 0x1d
246	250	#define OP_PUSH_DS 0x1e
247	251	#define OP_POP_DS 0x1f
248	252
249		#define OP_AND_Eb_Gb 0x20 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	253	#define OP_AND_Eb_Gb (0x20 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
250	254	#define OP_AND_Ev_Gv 0x21
251		#define OP_AND_Gb_Eb 0x22 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	255	#define OP_AND_Gb_Eb (0x22 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
252	256	#define OP_AND_Gv_Ev 0x23
253	257	#define OP_AND_AL_Ib 0x24
254	258	#define OP_AND_rAX_Iz 0x25
255	259	#define PREFIX_ES 0x26
256	260	#define OP_DAA 0x27
257		#define OP_SUB_Eb_Gb 0x28 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	261	#define OP_SUB_Eb_Gb (0x28 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
258	262	#define OP_SUB_Ev_Gv 0x29
259		#define OP_SUB_Gb_Eb 0x2a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	263	#define OP_SUB_Gb_Eb (0x2a \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
260	264	#define OP_SUB_Gv_Ev 0x2b
261	265	#define OP_SUB_AL_Ib 0x2c
262	266	#define OP_SUB_eAX_Iv 0x2d
263	267	#define PREFIX_CS 0x2e
264	268	#define OP_DAS 0x2f
265	269
266		#define OP_XOR_Eb_Gb 0x30 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	270	#define OP_XOR_Eb_Gb (0x30 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
267	271	#define OP_XOR_Ev_Gv 0x31
268		#define OP_XOR_Gb_Eb 0x32 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	272	#define OP_XOR_Gb_Eb (0x32 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
269	273	#define OP_XOR_Gv_Ev 0x33
270	274	#define OP_XOR_AL_Ib 0x34
271	275	#define OP_XOR_rAX_Iz 0x35
272	276	#define PREFIX_SS 0x36
273	277	#define OP_AAA 0x37
274		#define OP_CMP_Eb_Gb 0x38 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	278	#define OP_CMP_Eb_Gb (0x38 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
275	279	#define OP_CMP_Ev_Gv 0x39
276		#define OP_CMP_Gb_Eb 0x3a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	280	#define OP_CMP_Gb_Eb (0x3a \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
277	281	#define OP_CMP_Gv_Ev 0x3b
278	282	#define OP_CMP_AL_Ib 0x3c
279	283	#define OP_CMP_eAX_Iv 0x3d
r949	r950
363	367	#define OP_JCC_NLE_Jb 0x7f
364	368	#define OP_JCC_G_Jb 0x7f
365	369
366		#define OP_G1_Eb_Ib 0x80 \| OPFLAG_8BITRM
	370	#define OP_G1_Eb_Ib (0x80 \| OPFLAG_8BITRM)
367	371	#define OP_G1_Ev_Iz 0x81
368		#define OP_G1_Eb_Ibx 0x82 \| OPFLAG_8BITRM
	372	#define OP_G1_Eb_Ibx (0x82 \| OPFLAG_8BITRM)
369	373	#define OP_G1_Ev_Ib 0x83
370		#define OP_TEST_Eb_Gb 0x84 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	374	#define OP_TEST_Eb_Gb (0x84 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
371	375	#define OP_TEST_Ev_Gv 0x85
372		#define OP_XCHG_Eb_Gb 0x86 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	376	#define OP_XCHG_Eb_Gb (0x86 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
373	377	#define OP_XCHG_Ev_Gv 0x87
374		#define OP_MOV_Eb_Gb 0x88 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	378	#define OP_MOV_Eb_Gb (0x88 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
375	379	#define OP_MOV_Ev_Gv 0x89
376		#define OP_MOV_Gb_Eb 0x8a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	380	#define OP_MOV_Gb_Eb (0x8a \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
377	381	#define OP_MOV_Gv_Ev 0x8b
378	382	#define OP_MOV_Ev_Sw 0x8c
379	383	#define OP_LEA_Gv_M 0x8d
r949	r950
436	440	#define OP_MOV_rSI_Iv 0xbe
437	441	#define OP_MOV_rDI_Iv 0xbf
438	442
439		#define OP_G2_Eb_Ib 0xc0 \| OPFLAG_8BITRM
	443	#define OP_G2_Eb_Ib (0xc0 \| OPFLAG_8BITRM)
440	444	#define OP_G2_Ev_Ib 0xc1
441	445	#define OP_RETN_Iw 0xc2
442	446	#define OP_RETN 0xc3
443	447	#define OP_LES_Gz_Mp 0xc4
444	448	#define OP_LDS_Gz_Mp 0xc5
445		#define OP_G11_Eb_Ib 0xc6 \| OPFLAG_8BITRM
	449	#define OP_G11_Eb_Ib (0xc6 \| OPFLAG_8BITRM)
446	450	#define OP_G11_Ev_Iz 0xc7
447	451	#define OP_ENTER_Iw_Ib 0xc8
448	452	#define OP_LEAVE 0xc9
r949	r950
453	457	#define OP_INTO 0xce
454	458	#define OP_IRET 0xcf
455	459
456		#define OP_G2_Eb_1 0xd0 \| OPFLAG_8BITRM
	460	#define OP_G2_Eb_1 (0xd0 \| OPFLAG_8BITRM)
457	461	#define OP_G2_Ev_1 0xd1
458		#define OP_G2_Eb_CL 0xd2 \| OPFLAG_8BITRM
	462	#define OP_G2_Eb_CL (0xd2 \| OPFLAG_8BITRM)
459	463	#define OP_G2_Ev_CL 0xd3
460	464	#define OP_AAM 0xd4
461	465	#define OP_AAD 0xd5
r949	r950
491	495	#define PREFIX_REPE 0xf3
492	496	#define OP_HLT 0xf4
493	497	#define OP_CMC 0xf5
494		#define OP_G3_Eb 0xf6 \| OPFLAG_8BITRM
	498	#define OP_G3_Eb (0xf6 \| OPFLAG_8BITRM)
495	499	#define OP_G3_Ev 0xf7
496	500	#define OP_CLC 0xf8
497	501	#define OP_STC 0xf9
r949	r950
741	745	#define OP_JCC_NLE_Jv 0x0f8f
742	746	#define OP_JCC_G_Jv 0x0f8f
743	747
744		#define OP_SETCC_O_Eb 0x0f90 \| OPFLAG_8BITRM
745		#define OP_SETCC_NO_Eb 0x0f91 \| OPFLAG_8BITRM
746		#define OP_SETCC_B_Eb 0x0f92 \| OPFLAG_8BITRM
747		#define OP_SETCC_C_Eb 0x0f92 \| OPFLAG_8BITRM
748		#define OP_SETCC_NAE_Eb 0x0f92 \| OPFLAG_8BITRM
749		#define OP_SETCC_AE_Eb 0x0f93 \| OPFLAG_8BITRM
750		#define OP_SETCC_NB_Eb 0x0f93 \| OPFLAG_8BITRM
751		#define OP_SETCC_NC_Eb 0x0f93 \| OPFLAG_8BITRM
752		#define OP_SETCC_E_Eb 0x0f94 \| OPFLAG_8BITRM
753		#define OP_SETCC_Z_Eb 0x0f94 \| OPFLAG_8BITRM
754		#define OP_SETCC_NE_Eb 0x0f95 \| OPFLAG_8BITRM
755		#define OP_SETCC_NZ_Eb 0x0f95 \| OPFLAG_8BITRM
756		#define OP_SETCC_BE_Eb 0x0f96 \| OPFLAG_8BITRM
757		#define OP_SETCC_NA_Eb 0x0f96 \| OPFLAG_8BITRM
758		#define OP_SETCC_A_Eb 0x0f97 \| OPFLAG_8BITRM
759		#define OP_SETCC_NBE_Eb 0x0f97 \| OPFLAG_8BITRM
760		#define OP_SETCC_S_Eb 0x0f98 \| OPFLAG_8BITRM
761		#define OP_SETCC_NS_Eb 0x0f99 \| OPFLAG_8BITRM
762		#define OP_SETCC_P_Eb 0x0f9a \| OPFLAG_8BITRM
763		#define OP_SETCC_PE_Eb 0x0f9a \| OPFLAG_8BITRM
764		#define OP_SETCC_NP_Eb 0x0f9b \| OPFLAG_8BITRM
765		#define OP_SETCC_PO_Eb 0x0f9b \| OPFLAG_8BITRM
766		#define OP_SETCC_L_Eb 0x0f9c \| OPFLAG_8BITRM
767		#define OP_SETCC_NGE_Eb 0x0f9c \| OPFLAG_8BITRM
768		#define OP_SETCC_NL_Eb 0x0f9d \| OPFLAG_8BITRM
769		#define OP_SETCC_GE_Eb 0x0f9d \| OPFLAG_8BITRM
770		#define OP_SETCC_LE_Eb 0x0f9e \| OPFLAG_8BITRM
771		#define OP_SETCC_NG_Eb 0x0f9e \| OPFLAG_8BITRM
772		#define OP_SETCC_NLE_Eb 0x0f9f \| OPFLAG_8BITRM
773		#define OP_SETCC_G_Eb 0x0f9f \| OPFLAG_8BITRM
	748	#define OP_SETCC_O_Eb (0x0f90 \| OPFLAG_8BITRM)
	749	#define OP_SETCC_NO_Eb (0x0f91 \| OPFLAG_8BITRM)
	750	#define OP_SETCC_B_Eb (0x0f92 \| OPFLAG_8BITRM)
	751	#define OP_SETCC_C_Eb (0x0f92 \| OPFLAG_8BITRM)
	752	#define OP_SETCC_NAE_Eb (0x0f92 \| OPFLAG_8BITRM)
	753	#define OP_SETCC_AE_Eb (0x0f93 \| OPFLAG_8BITRM)
	754	#define OP_SETCC_NB_Eb (0x0f93 \| OPFLAG_8BITRM)
	755	#define OP_SETCC_NC_Eb (0x0f93 \| OPFLAG_8BITRM)
	756	#define OP_SETCC_E_Eb (0x0f94 \| OPFLAG_8BITRM)
	757	#define OP_SETCC_Z_Eb (0x0f94 \| OPFLAG_8BITRM)
	758	#define OP_SETCC_NE_Eb (0x0f95 \| OPFLAG_8BITRM)
	759	#define OP_SETCC_NZ_Eb (0x0f95 \| OPFLAG_8BITRM)
	760	#define OP_SETCC_BE_Eb (0x0f96 \| OPFLAG_8BITRM)
	761	#define OP_SETCC_NA_Eb (0x0f96 \| OPFLAG_8BITRM)
	762	#define OP_SETCC_A_Eb (0x0f97 \| OPFLAG_8BITRM)
	763	#define OP_SETCC_NBE_Eb (0x0f97 \| OPFLAG_8BITRM)
	764	#define OP_SETCC_S_Eb (0x0f98 \| OPFLAG_8BITRM)
	765	#define OP_SETCC_NS_Eb (0x0f99 \| OPFLAG_8BITRM)
	766	#define OP_SETCC_P_Eb (0x0f9a \| OPFLAG_8BITRM)
	767	#define OP_SETCC_PE_Eb (0x0f9a \| OPFLAG_8BITRM)
	768	#define OP_SETCC_NP_Eb (0x0f9b \| OPFLAG_8BITRM)
	769	#define OP_SETCC_PO_Eb (0x0f9b \| OPFLAG_8BITRM)
	770	#define OP_SETCC_L_Eb (0x0f9c \| OPFLAG_8BITRM)
	771	#define OP_SETCC_NGE_Eb (0x0f9c \| OPFLAG_8BITRM)
	772	#define OP_SETCC_NL_Eb (0x0f9d \| OPFLAG_8BITRM)
	773	#define OP_SETCC_GE_Eb (0x0f9d \| OPFLAG_8BITRM)
	774	#define OP_SETCC_LE_Eb (0x0f9e \| OPFLAG_8BITRM)
	775	#define OP_SETCC_NG_Eb (0x0f9e \| OPFLAG_8BITRM)
	776	#define OP_SETCC_NLE_Eb (0x0f9f \| OPFLAG_8BITRM)
	777	#define OP_SETCC_G_Eb (0x0f9f \| OPFLAG_8BITRM)
774	778
775	779	#define OP_PUSH_FS 0x0fa0
776	780	#define OP_POP_FS 0x0fa1
r949	r950
787	791	#define OP_G16 0x0fae
788	792	#define OP_IMUL_Gv_Ev 0x0faf
789	793
790		#define OP_CMPXCHG_Eb_Gb 0x0fb0 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	794	#define OP_CMPXCHG_Eb_Gb (0x0fb0 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
791	795	#define OP_CMPXCHG_Ev_Gv 0x0fb1
792	796	#define OP_LSS_Mp 0x0fb2
793	797	#define OP_BTR_Ev_Gv 0x0fb3
794	798	#define OP_LFS_Mp 0x0fb4
795	799	#define OP_LGS_Mp 0x0fb5
796		#define OP_MOVZX_Gv_Eb 0x0fb6 \| OPFLAG_8BITRM
	800	#define OP_MOVZX_Gv_Eb (0x0fb6 \| OPFLAG_8BITRM)
797	801	#define OP_MOVZX_Gv_Ew 0x0fb7
798	802	#define OP_G10_INVALID 0x0fb9
799	803	#define OP_G8_Ev_Ib 0x0fba
800	804	#define OP_BTC_Ev_Gv 0x0fbb
801	805	#define OP_BSF_Gv_Ev 0x0fbc
802	806	#define OP_BSR_Gv_Ev 0x0fbd
803		#define OP_MOVSX_Gv_Eb 0x0fbe \| OPFLAG_8BITRM
	807	#define OP_MOVSX_Gv_Eb (0x0fbe \| OPFLAG_8BITRM)
804	808	#define OP_MOVSX_Gv_Ew 0x0fbf
805	809
806		#define OP_XADD_Eb_Gb 0x0fc0 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	810	#define OP_XADD_Eb_Gb (0x0fc0 \| OPFLAG_8BITRM \| OPFLAG_8BITREG)
807	811	#define OP_XADD_Ev_Gv 0x0fc1
808	812	#define OP_CMPPS_Vps_Wps_Ib 0x0fc2
809	813	#define OP_CMPSS_Vss_Wss_Ib 0xf30fc2
r949	r950
1004	1008	TYPE DEFINITIONS
1005	1009	***************************************************************************/
1006	1010
	1011	/* use x86code * to reference generated code */
1007	1012	typedef UINT8 x86code;
1008	1013
1009	1014
	1015	/* this structure tracks information about a link */
1010	1016	typedef struct _emit_link emit_link;
1011	1017	struct _emit_link
1012	1018	{
r949	r950
1017	1023
1018	1024
1019	1025	/***************************************************************************
	1026	MACROS
	1027	***************************************************************************/
	1028
	1029	#define DECLARE_MEMPARAMS UINT8 base, UINT8 index, UINT8 scale, INT32 disp
	1030	#define MEMPARAMS base, index, scale, disp
	1031
	1032	#ifndef PTR64
	1033	#define MBISD(base, index, scale, disp) (base), (index), (scale), (INT32)(disp)
	1034	#define MABS(addr) MBISD(REG_NONE, REG_NONE, 1, (addr))
	1035	#define MBD(base, disp) MBISD((base), REG_NONE, 1, (disp))
	1036	#define MISD(index, scale, disp) MBISD(REG_NONE, (index), (scale), (disp))
	1037	#else
	1038	#define MBISD(base, index, scale, disp) (base), (index), (scale), (disp)
	1039	#define MBD(base, disp) MBISD((base), REG_NONE, 1, (disp))
	1040	#define MISD(index, scale, disp) MBISD(REG_NONE, (index), (scale), (disp))
	1041	#endif
	1042
	1043
	1044
	1045	/***************************************************************************
1020	1046	CORE FUNCTIONS
1021	1047	***************************************************************************/
1022	1048
r949	r950
1103	1129	along with any necessary REX prefixes for x64
1104	1130	-------------------------------------------------*/
1105	1131
1106		INLINE void emit_op(x86code **emitptr, UINT32 op, UINT8 op64, UINT8 reg, UINT8 sib, UINT8 rm)
	1132	INLINE void emit_op(x86code **emitptr, UINT32 op, UINT8 opsize, UINT8 reg, UINT8 sib, UINT8 rm)
1107	1133	{
1108	1134	#ifdef PTR64
1109	1135	UINT8 rex;
1110	1136
1111		assert(op64 == OP_32BIT \|\| op64 == OP_64BIT);
	1137	assert(opsize == OP_16BIT \|\| opsize == OP_32BIT \|\| opsize == OP_64BIT);
1112	1138
1113		rex = op64 \| ((reg & 8) >> 1) \| ((sib & 8) >> 2) \| ((rm & 8) >> 3);
	1139	rex = (opsize & 8) \| ((reg & 8) >> 1) \| ((sib & 8) >> 2) \| ((rm & 8) >> 3);
1114	1140	if (rex != 0 \|\| ((op & OPFLAG_8BITREG) && reg >= 4) \|\| ((op & OPFLAG_8BITRM) && rm >= 4))
1115		emit_byte(emitptr, rex ~~\| 0x40~~);
	1141	emit_byte(emitptr, OP_REX + rex);
1116	1142	#else
1117		assert(op64 == OP_32BIT);
	1143	assert(opsize != OP_64BIT);
1118	1144	#endif
1119	1145
	1146	if (opsize == OP_16BIT)
	1147	emit_byte(emitptr, PREFIX_OPSIZE);
1120	1148	if ((op & 0xff0000) != 0)
1121	1149	emit_byte(emitptr, op >> 16);
1122	1150	if ((op & 0xff00) != 0)
r949	r950
1129	1157	emit_op_simple - emit a simple opcode
1130	1158	-------------------------------------------------*/
1131	1159
1132		INLINE void emit_op_simple(x86code **emitptr, UINT32 op, UINT8 op64)
	1160	INLINE void emit_op_simple(x86code **emitptr, UINT32 op, UINT8 opsize)
1133	1161	{
1134		emit_op(emitptr, op, op64, 0, 0, 0);
	1162	emit_op(emitptr, op, opsize, 0, 0, 0);
1135	1163	}
1136	1164
1137	1165
1138	1166	/*-------------------------------------------------
	1167	emit_op_reg - emit a simple opcode that has
	1168	a register parameter
	1169	-------------------------------------------------*/
	1170
	1171	INLINE void emit_op_reg(x86code **emitptr, UINT32 op, UINT8 opsize, UINT8 reg)
	1172	{
	1173	emit_op(emitptr, op, opsize, 0, 0, reg);
	1174	}
	1175
	1176
	1177	/*-------------------------------------------------
1139	1178	emit_op_modrm_reg - emit an opcode with a
1140	1179	register modrm byte
1141	1180	-------------------------------------------------*/
1142	1181
1143		INLINE void emit_op_modrm_reg(x86code **emitptr, UINT32 op, UINT8 op64, UINT8 reg, UINT8 rm)
	1182	INLINE void emit_op_modrm_reg(x86code **emitptr, UINT32 op, UINT8 opsize, UINT8 reg, UINT8 rm)
1144	1183	{
1145	1184	assert(reg < REG_MAX);
1146	1185	assert(rm < REG_MAX);
1147	1186
1148		emit_op(emitptr, op, op64, reg, 0, rm);
	1187	emit_op(emitptr, op, opsize, reg, 0, rm);
1149	1188	emit_byte(emitptr, make_modrm(3, reg, rm));
1150	1189	}
1151	1190
r949	r950
1155	1194	memory modrm byte
1156	1195	-------------------------------------------------*/
1157	1196
1158		INLINE void emit_op_modrm_mem(x86code **emitptr, UINT32 op, UINT8 op~~64, UINT8 reg, UINT8 ba~~s~~e, UINT8~~ index, UINT8 ~~scal~~e, ~~INT32 disp~~)
	1197	INLINE void emit_op_modrm_mem(x86code **emitptr, UINT32 op, UINT8 opsize, UINT8 reg, DECLARE_MEMPARAMS)
1159	1198	{
1160	1199	assert(reg < REG_MAX);
1161	1200	assert(base < REG_MAX \|\| base == REG_NONE);
r949	r950
1168	1207	if (base == REG_NONE && index == REG_NONE)
1169	1208	{
1170	1209	#ifndef PTR64
1171		emit_op(emitptr, op, op64, reg, 0, 5);
	1210	emit_op(emitptr, op, opsize, reg, 0, 5);
1172	1211	emit_byte(emitptr, make_modrm(0, reg, 5));
1173	1212	emit_dword(emitptr, disp);
1174	1213	#else
r949	r950
1179	1218	/* base only case */
1180	1219	else if (index == REG_NONE && base != REG_ESP)
1181	1220	{
1182		emit_op(emitptr, op, op64, reg, 0, base);
	1221	emit_op(emitptr, op, opsize, reg, 0, base);
1183	1222
1184	1223	/* mode 0 for no offset */
1185	1224	if (disp == 0 && base != REG_EBP)
r949	r950
1204	1243	else
1205	1244	{
1206	1245	assert(index != REG_ESP);
1207		emit_op(emitptr, op, op64, reg, index, base);
	1246	emit_op(emitptr, op, opsize, reg, index, base);
1208	1247
1209	1248	/* a "none" index == REG_ESP */
1210	1249	if (index == REG_NONE)
1211	1250	index = REG_ESP;
1212	1251
	1252	/* no base is a special case */
	1253	if (base == REG_NONE)
	1254	{
	1255	emit_byte(emitptr, make_modrm(0, reg, 4));
	1256	emit_byte(emitptr, make_sib(scale, index, REG_EBP));
	1257	emit_dword(emitptr, disp);
	1258	}
	1259
1213	1260	/* mode 0 for no offset */
1214		if (disp == 0 && base != REG_EBP)
	1261	else if (disp == 0 && base != REG_EBP)
1215	1262	{
1216	1263	emit_byte(emitptr, make_modrm(0, reg, 4));
1217		emit_byte(emitptr, make_sib(scale, index, (base == REG_NONE) ? REG_EBP : base));
1218		if (base == REG_NONE)
1219		emit_dword(emitptr, disp);
	1264	emit_byte(emitptr, make_sib(scale, index, base));
1220	1265	}
1221	1266
1222	1267	/* mode 1 for 1-byte offset */
r949	r950
1240	1285
1241	1286
1242	1287	/***************************************************************************
1243		~~SIMPL~~E OPCODE EMITTERS
	1288	GENERIC OPCODE + IMMEDIATE EMITTERS
1244	1289	***************************************************************************/
1245	1290
1246		INLINE void emit_nop(x86code **emitptr)
1247		{
1248		emit_byte(emitptr, OP_NOP);
1249		}
1250
1251		INLINE void emit_int_3(x86code **emitptr)
1252		{
1253		emit_byte(emitptr, OP_INT_3);
1254		}
1255
1256		INLINE void emit_ret(x86code **emitptr)
1257		{
1258		emit_byte(emitptr, OP_RETN);
1259		}
1260
1261		INLINE void emit_cdq(x86code **emitptr)
1262		{
1263		emit_byte(emitptr, OP_CDQ);
1264		}
1265
1266		#ifdef PTR64
1267		INLINE void emit_cqo(x86code **emitptr)
1268		{
1269		emit_byte(emitptr, OP_REX_W);
1270		emit_byte(emitptr, OP_CQO);
1271		}
1272		#endif
1273
1274
1275
1276		/***************************************************************************
1277		CALL/JUMP EMITTERS
1278		***************************************************************************/
1279
1280	1291	/*-------------------------------------------------
1281		resolve_link - resolve a link in a jump
1282		instruction
	1292	emit_op_modrm_reg_imm8 - emit an opcode with a
	1293	register modrm byte and an 8-bit immediate
1283	1294	-------------------------------------------------*/
1284	1295
1285		INLINE void resolve_link(x86code *destptr, const em~~it_link~~ li~~nkinfo~~)
	1296	INLINE void emit_op_modrm_reg_imm8(x86code **emitptr, UINT32 op, UINT8 opsize, UINT8 reg, UINT8 rm, UINT8 imm)
1286	1297	{
1287		INT64 delta = *destptr - linkinfo->target;
1288		if (linkinfo->size == 1)
1289		{
1290		assert((INT8)delta == delta);
1291		((INT8 *)linkinfo->target)[-1] = (INT8)delta;
1292		}
1293		else if (linkinfo->size == 2)
1294		{
1295		assert((INT16)delta == delta);
1296		((INT16 *)linkinfo->target)[-1] = (INT16)delta;
1297		}
1298		else
1299		{
1300		assert((INT32)delta == delta);
1301		((INT32 *)linkinfo->target)[-1] = (INT32)delta;
1302		}
1303		}
1304
1305
1306		/*------------------------------------------------------------------
1307		emit_call_*
1308		------------------------------------------------------------------*/
1309
1310		INLINE void emit_call_link(x86code *emitptr, emit_link linkinfo)
1311		{
1312		emit_op_simple(emitptr, OP_CALL_Jz, OP_32BIT);
1313		emit_dword(emitptr, 0);
1314		linkinfo->target = *emitptr;
1315		linkinfo->size = 4;
1316		}
1317
1318		INLINE void emit_call(x86code *emitptr, x86code target)
1319		{
1320		emit_link link;
1321
1322		emit_call_link(emitptr, &link);
1323		resolve_link(&target, &link);
1324		}
1325
1326
1327		/*------------------------------------------------------------------
1328		emit_call_r32_*
1329		------------------------------------------------------------------*/
1330
1331		#ifndef PTR64
1332
1333		INLINE void emit_call_r32(x86code **emitptr, UINT8 dreg)
1334		{
1335		emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 2, dreg);
1336		}
1337
1338		INLINE void emit_call_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1339		{
1340		emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 2, base, index, scale, disp);
1341		}
1342
1343		#define emit_call_m32abs(e, addr) emit_call_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
1344		#define emit_call_m32bd(e, base, disp) emit_call_m32bisd(e, (base), REG_NONE, 1, (disp))
1345		#define emit_call_m32isd(e, index, scale, disp) emit_call_m32bisd(e, REG_NONE, (index), (scale), (disp))
1346
1347		#endif
1348
1349
1350		/*------------------------------------------------------------------
1351		emit_call_r64_*
1352		------------------------------------------------------------------*/
1353
1354		#ifdef PTR64
1355
1356		INLINE void emit_call_r64(x86code **emitptr, UINT8 dreg)
1357		{
1358		emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 2, dreg);
1359		}
1360
1361		INLINE void emit_call_m64bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1362		{
1363		emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 2, base, index, scale, disp);
1364		}
1365
1366		#define emit_call_m64abs(e, addr) emit_call_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
1367		#define emit_call_m64bd(e, base, disp) emit_call_m64bisd(e, (base), REG_NONE, 1, (disp))
1368		#define emit_call_m64isd(e, index, scale, disp) emit_call_m64bisd(e, REG_NONE, (index), (scale), (disp))
1369
1370		#endif
1371
1372
1373		/*------------------------------------------------------------------
1374		emit_jmp_*
1375		------------------------------------------------------------------*/
1376
1377		INLINE void emit_jmp_short_link(x86code *emitptr, emit_link linkinfo)
1378		{
1379		emit_op_simple(emitptr, OP_JMP_Jb, OP_32BIT);
1380		emit_byte(emitptr, 0);
1381		linkinfo->target = *emitptr;
1382		linkinfo->size = 1;
1383		}
1384
1385		INLINE void emit_jmp_near_link(x86code *emitptr, emit_link linkinfo)
1386		{
1387		emit_op_simple(emitptr, OP_JMP_Jz, OP_32BIT);
1388		emit_dword(emitptr, 0);
1389		linkinfo->target = *emitptr;
1390		linkinfo->size = 4;
1391		}
1392
1393		INLINE void emit_jmp(x86code *emitptr, x86code target)
1394		{
1395		INT32 delta = target - (*emitptr + 2);
1396		emit_link link;
1397
1398		if ((INT8)delta == delta)
1399		emit_jmp_short_link(emitptr, &link);
1400		else
1401		emit_jmp_near_link(emitptr, &link);
1402		resolve_link(&target, &link);
1403		}
1404
1405
1406		/*------------------------------------------------------------------
1407		emit_jcc_*
1408		------------------------------------------------------------------*/
1409
1410		INLINE void emit_jcc_short_link(x86code *emitptr, UINT8 condition, emit_link linkinfo)
1411		{
1412		emit_op_simple(emitptr, OP_JCC_O_Jb + condition, OP_32BIT);
1413		emit_byte(emitptr, 0);
1414		linkinfo->target = *emitptr;
1415		linkinfo->size = 1;
1416		}
1417
1418		INLINE void emit_jcc_near_link(x86code *emitptr, UINT8 condition, emit_link linkinfo)
1419		{
1420		emit_op_simple(emitptr, OP_JCC_O_Jv + condition, OP_32BIT);
1421		emit_dword(emitptr, 0);
1422		linkinfo->target = *emitptr;
1423		linkinfo->size = 4;
1424		}
1425
1426		INLINE void emit_jcc(x86code *emitptr, UINT8 condition, x86code target)
1427		{
1428		INT32 delta = *emitptr + 2 - target;
1429		emit_link link;
1430
1431		if ((INT8)delta == delta)
1432		emit_jcc_short_link(emitptr, condition, &link);
1433		else
1434		emit_jcc_near_link(emitptr, condition, &link);
1435		resolve_link(&target, &link);
1436		}
1437
1438
1439		/*------------------------------------------------------------------
1440		emit_jmp_r32_*
1441		------------------------------------------------------------------*/
1442
1443		#ifndef PTR64
1444
1445		INLINE void emit_jmp_r32(x86code **emitptr, UINT8 dreg)
1446		{
1447		emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 4, dreg);
1448		}
1449
1450		INLINE void emit_jmp_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1451		{
1452		emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 4, base, index, scale, disp);
1453		}
1454
1455		#define emit_jmp_m32abs(e, addr) emit_jmp_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
1456		#define emit_jmp_m32bd(e, base, disp) emit_jmp_m32bisd(e, (base), REG_NONE, 1, (disp))
1457		#define emit_jmp_m32isd(e, index, scale, disp) emit_jmp_m32bisd(e, REG_NONE, (index), (scale), (disp))
1458
1459		#endif
1460
1461
1462		/*------------------------------------------------------------------
1463		emit_jmp_r64_*
1464		------------------------------------------------------------------*/
1465
1466		#ifdef PTR64
1467
1468		INLINE void emit_jmp_r64(x86code **emitptr, UINT8 dreg)
1469		{
1470		emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 4, dreg);
1471		}
1472
1473		INLINE void emit_jmp_m64bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1474		{
1475		emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 4, base, index, scale, disp);
1476		}
1477
1478		#define emit_jmp_m64abs(e, addr) emit_jmp_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
1479		#define emit_jmp_m64bd(e, base, disp) emit_jmp_m64bisd(e, (base), REG_NONE, 1, (disp))
1480		#define emit_jmp_m64isd(e, index, scale, disp) emit_jmp_m64bisd(e, REG_NONE, (index), (scale), (disp))
1481
1482		#endif
1483
1484
1485
1486		/***************************************************************************
1487		MOVE EMITTERS
1488		***************************************************************************/
1489
1490		/*------------------------------------------------------------------
1491		emit_mov_r8_*
1492		------------------------------------------------------------------*/
1493
1494		INLINE void emit_mov_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm)
1495		{
1496		emit_op(emitptr, OP_MOV_AL_Ib \| (dreg & 7), OP_32BIT, 0, 0, dreg);
	1298	emit_op_modrm_reg(emitptr, op, opsize, reg, rm);
1497	1299	emit_byte(emitptr, imm);
1498	1300	}
1499	1301
1500		INLINE void emit_mov_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1501		{
1502		emit_op_modrm_reg(emitptr, OP_MOV_Gb_Eb, OP_32BIT, dreg, sreg);
1503		}
1504	1302
1505		INLINE void emit_mov_r8_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1506		{
1507		emit_op_modrm_mem(emitptr, OP_MOV_Gb_Eb, OP_32BIT, dreg, base, index, scale, disp);
1508		}
	1303	/*-------------------------------------------------
	1304	emit_op_modrm_mem_imm8 - emit an opcode with a
	1305	memory modrm byte and an 8-bit immediate
	1306	-------------------------------------------------*/
1509	1307
1510		INLINE void emit_mov_m~~8bis~~d_imm(x86code **emitptr, UINT8 ~~base~~, UINT8 index, UINT8 ~~scal~~e, ~~INT32 disp~~, UINT8 imm)
	1308	INLINE void emit_op_modrm_mem_imm8(x86code **emitptr, UINT32 op, UINT8 opsize, UINT8 reg, DECLARE_MEMPARAMS, UINT8 imm)
1511	1309	{
1512		emit_op_modrm_mem(emitptr, ~~OP_G11_Eb_Ib~~, ~~OP_32BIT, 0, ba~~se, index, ~~scal~~e, ~~disp~~);
	1310	emit_op_modrm_mem(emitptr, op, opsize, reg, MEMPARAMS);
1513	1311	emit_byte(emitptr, imm);
1514	1312	}
1515	1313
1516		INLINE void emit_mov_m8bisd_r8(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
1517		{
1518		emit_op_modrm_mem(emitptr, OP_MOV_Eb_Gb, OP_32BIT, sreg, base, index, scale, disp);
1519		}
1520	1314
1521		#define emit_mov_r8_m8abs(e, dreg, addr) emit_mov_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1522		#define emit_mov_r8_m8bd(e, dreg, base, disp) emit_mov_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
1523		#define emit_mov_r8_m8isd(e, dreg, index, scale, disp) emit_mov_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1315	/*-------------------------------------------------
	1316	emit_op_modrm_reg_imm16 - emit an opcode with a
	1317	register modrm byte and a 16-bit immediate
	1318	-------------------------------------------------*/
1524	1319
1525		#define emit_mov_m8abs_r8(e, addr, sreg) emit_mov_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
1526		#define emit_mov_m8bd_r8(e, base, disp, sreg) emit_mov_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
1527		#define emit_mov_m8isd_r8(e, index, scale, disp, sreg) emit_mov_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
1528
1529		#define emit_mov_m8abs_imm(e, addr, imm) emit_mov_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
1530		#define emit_mov_m8bd_imm(e, base, disp, imm) emit_mov_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
1531		#define emit_mov_m8isd_imm(e, index, scale, disp, imm) emit_mov_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
1532
1533
1534		/*------------------------------------------------------------------
1535		emit_mov_r16_*
1536		------------------------------------------------------------------*/
1537
1538		INLINE void emit_mov_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm)
	1320	INLINE void emit_op_modrm_reg_imm16(x86code **emitptr, UINT32 op, UINT8 opsize, UINT8 reg, UINT8 rm, UINT16 imm)
1539	1321	{
1540		emit_byte(emitptr, PREFIX_OPSIZE);
1541		emit_op(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_32BIT, 0, 0, dreg);
	1322	emit_op_modrm_reg(emitptr, op, opsize, reg, rm);
1542	1323	emit_word(emitptr, imm);
1543	1324	}
1544	1325
1545		INLINE void emit_mov_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1546		{
1547		emit_byte(emitptr, PREFIX_OPSIZE);
1548		emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, sreg);
1549		}
1550	1326
1551		INLINE void emit_mov_r16_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1552		{
1553		emit_byte(emitptr, PREFIX_OPSIZE);
1554		emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, base, index, scale, disp);
1555		}
	1327	/*-------------------------------------------------
	1328	emit_op_modrm_mem_imm16 - emit an opcode with a
	1329	memory modrm byte and a 16-bit immediate
	1330	-------------------------------------------------*/
1556	1331
1557		INLINE void emit_mov_m~~16bis~~d_imm(x86code **emitptr, UINT8 ~~base~~, UINT8 index, UINT8 ~~scal~~e, ~~INT32 disp~~, UINT16 imm)
	1332	INLINE void emit_op_modrm_mem_imm16(x86code **emitptr, UINT32 op, UINT8 opsize, UINT8 reg, DECLARE_MEMPARAMS, UINT16 imm)
1558	1333	{
1559		emit_byte(emitptr, PREFIX_OPSIZE);
1560		emit_op_modrm_mem(emitptr, OP_G11_Ev_Iz, OP_32BIT, 0, base, index, scale, disp);
	1334	emit_op_modrm_mem(emitptr, op, opsize, reg, MEMPARAMS);
1561	1335	emit_word(emitptr, imm);
1562	1336	}
1563	1337
1564		INLINE void emit_mov_m16bisd_r16(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
1565		{
1566		emit_byte(emitptr, PREFIX_OPSIZE);
1567		emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
1568		}
1569	1338
1570		INLINE void emit_cmovcc_r16_r16(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 sreg)
1571		{
1572		emit_byte(emitptr, PREFIX_OPSIZE);
1573		emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, sreg);
1574		}
	1339	/*-------------------------------------------------
	1340	emit_op_modrm_reg_imm816 - emit an opcode with
	1341	a register modrm byte and an 8-bit or 16-bit
	1342	immediate
	1343	-------------------------------------------------*/
1575	1344
1576		INLINE void emit_cmo~~vcc~~_r16_m16~~bisd~~(x86code **emitptr, UINT8 co~~ndition~~, UINT8 ~~dreg~~, UINT8 base, UINT8 ~~ind~~ex, UINT8 ~~scale~~, INT32 disp)
	1345	INLINE void emit_op_modrm_reg_imm816(x86code **emitptr, UINT32 op8, UINT32 op16, UINT8 opsize, UINT8 reg, UINT8 rm, UINT16 imm)
1577	1346	{
1578		emit_byte(emitptr, PREFIX_OPSIZE);
1579		emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, base, index, scale, disp);
1580		}
1581
1582		#define emit_mov_r16_m16abs(e, dreg, addr) emit_mov_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1583		#define emit_mov_r16_m16bd(e, dreg, base, disp) emit_mov_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
1584		#define emit_mov_r16_m16isd(e, dreg, index, scale, disp) emit_mov_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1585
1586		#define emit_mov_m16abs_r16(e, addr, sreg) emit_mov_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
1587		#define emit_mov_m16bd_r16(e, base, disp, sreg) emit_mov_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
1588		#define emit_mov_m16isd_r16(e, index, scale, disp, sreg) emit_mov_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
1589
1590		#define emit_mov_m16abs_imm(e, addr, imm) emit_mov_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
1591		#define emit_mov_m16bd_imm(e, base, disp, imm) emit_mov_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
1592		#define emit_mov_m16isd_imm(e, index, scale, disp, imm) emit_mov_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
1593
1594		#define emit_cmovcc_r16_m16abs(e, cond, dreg, addr) emit_cmovcc_r16_m16bisd(e, cond, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1595		#define emit_cmovcc_r16_m16bd(e, cond, dreg, base, disp) emit_cmovcc_r16_m16bisd(e, cond, dreg, (base), REG_NONE, 1, (disp))
1596		#define emit_cmovcc_r16_m16isd(e, cond, dreg, index, scale, disp) emit_cmovcc_r16_m16bisd(e, cond, dreg, REG_NONE, (index), (scale), (disp))
1597
1598
1599		/*------------------------------------------------------------------
1600		emit_mov_r32_*
1601		------------------------------------------------------------------*/
1602
1603		INLINE void emit_mov_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm)
1604		{
1605		emit_op(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_32BIT, 0, 0, dreg);
1606		emit_dword(emitptr, imm);
1607		}
1608
1609		INLINE void emit_mov_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1610		{
1611		emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, sreg);
1612		}
1613
1614		INLINE void emit_mov_r32_m32bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1615		{
1616		emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, base, index, scale, disp);
1617		}
1618
1619		INLINE void emit_mov_m32bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
1620		{
1621		emit_op_modrm_mem(emitptr, OP_G11_Ev_Iz, OP_32BIT, 0, base, index, scale, disp);
1622		emit_dword(emitptr, imm);
1623		}
1624
1625		INLINE void emit_mov_m32bisd_r32(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
1626		{
1627		emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
1628		}
1629
1630		INLINE void emit_cmovcc_r32_r32(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 sreg)
1631		{
1632		emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, sreg);
1633		}
1634
1635		INLINE void emit_cmovcc_r32_m32bisd(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1636		{
1637		emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, base, index, scale, disp);
1638		}
1639
1640		#define emit_mov_r32_m32abs(e, dreg, addr) emit_mov_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1641		#define emit_mov_r32_m32bd(e, dreg, base, disp) emit_mov_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
1642		#define emit_mov_r32_m32isd(e, dreg, index, scale, disp) emit_mov_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1643
1644		#define emit_mov_m32abs_r32(e, addr, sreg) emit_mov_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
1645		#define emit_mov_m32bd_r32(e, base, disp, sreg) emit_mov_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
1646		#define emit_mov_m32isd_r32(e, index, scale, disp, sreg) emit_mov_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
1647
1648		#define emit_mov_m32abs_imm(e, addr, imm) emit_mov_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
1649		#define emit_mov_m32bd_imm(e, base, disp, imm) emit_mov_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
1650		#define emit_mov_m32isd_imm(e, index, scale, disp, imm) emit_mov_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
1651
1652		#define emit_cmovcc_r32_m32abs(e, cond, dreg, addr) emit_cmovcc_r32_m32bisd(e, cond, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1653		#define emit_cmovcc_r32_m32bd(e, cond, dreg, base, disp) emit_cmovcc_r32_m32bisd(e, cond, dreg, (base), REG_NONE, 1, (disp))
1654		#define emit_cmovcc_r32_m32isd(e, cond, dreg, index, scale, disp) emit_cmovcc_r32_m32bisd(e, cond, dreg, REG_NONE, (index), (scale), (disp))
1655
1656
1657		/*------------------------------------------------------------------
1658		emit_mov_r64_*
1659		------------------------------------------------------------------*/
1660
1661		#ifdef PTR64
1662
1663		INLINE void emit_mov_r64_imm(x86code **emitptr, UINT8 dreg, UINT64 imm)
1664		{
1665		emit_op(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_64BIT, 0, 0, dreg);
1666		emit_qword(emitptr, imm);
1667		}
1668
1669		INLINE void emit_mov_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1670		{
1671		emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_64BIT, dreg, sreg);
1672		}
1673
1674		INLINE void emit_mov_r64_m64bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1675		{
1676		emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_64BIT, dreg, base, index, scale, disp);
1677		}
1678
1679		INLINE void emit_mov_m64bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT64 imm)
1680		{
1681		assert((INT32)imm == (INT64)imm);
1682		emit_op_modrm_mem(emitptr, OP_G11_Ev_Iz, OP_64BIT, 0, base, index, scale, disp);
1683		emit_dword(emitptr, (INT32)imm);
1684		}
1685
1686		INLINE void emit_mov_m64bisd_r64(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
1687		{
1688		emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_64BIT, sreg, base, index, scale, disp);
1689		}
1690
1691		INLINE void emit_cmovcc_r64_r64(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 sreg)
1692		{
1693		emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_64BIT, dreg, sreg);
1694		}
1695
1696		INLINE void emit_cmovcc_r64_m64bisd(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1697		{
1698		emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_64BIT, dreg, base, index, scale, disp);
1699		}
1700
1701		#define emit_mov_r64_m64abs(e, dreg, addr) emit_mov_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1702		#define emit_mov_r64_m64bd(e, dreg, base, disp) emit_mov_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
1703		#define emit_mov_r64_m64isd(e, dreg, index, scale, disp) emit_mov_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1704
1705		#define emit_mov_m64abs_r64(e, addr, sreg) emit_mov_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
1706		#define emit_mov_m64bd_r64(e, base, disp, sreg) emit_mov_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
1707		#define emit_mov_m64isd_r64(e, index, scale, disp, sreg) emit_mov_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
1708
1709		#define emit_mov_m64abs_imm(e, addr, imm) emit_mov_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
1710		#define emit_mov_m64bd_imm(e, base, disp, imm) emit_mov_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
1711		#define emit_mov_m64isd_imm(e, index, scale, disp, imm) emit_mov_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
1712
1713		#define emit_cmovcc_r64_m64abs(e, cond, dreg, addr) emit_cmovcc_r64_m64bisd(e, cond, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1714		#define emit_cmovcc_r64_m64bd(e, cond, dreg, base, disp) emit_cmovcc_r64_m64bisd(e, cond, dreg, (base), REG_NONE, 1, (disp))
1715		#define emit_cmovcc_r64_m64isd(e, cond, dreg, index, scale, disp) emit_cmovcc_r64_m64bisd(e, cond, dreg, REG_NONE, (index), (scale), (disp))
1716
1717		#endif
1718
1719
1720
1721		/***************************************************************************
1722		MOVE EXTENDED EMITTERS
1723		***************************************************************************/
1724
1725		/*------------------------------------------------------------------
1726		emit_movsx_r16_*
1727		------------------------------------------------------------------*/
1728
1729		INLINE void emit_movsx_r16_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1730		{
1731		emit_byte(emitptr, PREFIX_OPSIZE);
1732		emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, sreg);
1733		}
1734
1735		INLINE void emit_movsx_r16_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1736		{
1737		emit_byte(emitptr, PREFIX_OPSIZE);
1738		emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
1739		}
1740
1741		#define emit_movsx_r16_m8abs(e, dreg, addr) emit_movsx_r16_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1742		#define emit_movsx_r16_m8bd(e, dreg, base, disp) emit_movsx_r16_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
1743		#define emit_movsx_r16_m8isd(e, dreg, index, scale, disp) emit_movsx_r16_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1744
1745
1746		/*------------------------------------------------------------------
1747		emit_movzx_r16_*
1748		------------------------------------------------------------------*/
1749
1750		INLINE void emit_movzx_r16_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1751		{
1752		emit_byte(emitptr, PREFIX_OPSIZE);
1753		emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, sreg);
1754		}
1755
1756		INLINE void emit_movzx_r16_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1757		{
1758		emit_byte(emitptr, PREFIX_OPSIZE);
1759		emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
1760		}
1761
1762		#define emit_movzx_r16_m8abs(e, dreg, addr) emit_movzx_r16_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1763		#define emit_movzx_r16_m8bd(e, dreg, base, disp) emit_movzx_r16_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
1764		#define emit_movzx_r16_m8isd(e, dreg, index, scale, disp) emit_movzx_r16_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1765
1766
1767		/*------------------------------------------------------------------
1768		emit_movsx_r32_*
1769		------------------------------------------------------------------*/
1770
1771		INLINE void emit_movsx_r32_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1772		{
1773		emit_byte(emitptr, PREFIX_OPSIZE);
1774		emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, sreg);
1775		}
1776
1777		INLINE void emit_movsx_r32_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1778		{
1779		emit_byte(emitptr, PREFIX_OPSIZE);
1780		emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
1781		}
1782
1783		INLINE void emit_movsx_r32_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1784		{
1785		emit_byte(emitptr, PREFIX_OPSIZE);
1786		emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Ew, OP_32BIT, dreg, sreg);
1787		}
1788
1789		INLINE void emit_movsx_r32_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1790		{
1791		emit_byte(emitptr, PREFIX_OPSIZE);
1792		emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Ew, OP_32BIT, dreg, base, index, scale, disp);
1793		}
1794
1795		#define emit_movsx_r32_m8abs(e, dreg, addr) emit_movsx_r32_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1796		#define emit_movsx_r32_m8bd(e, dreg, base, disp) emit_movsx_r32_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
1797		#define emit_movsx_r32_m8isd(e, dreg, index, scale, disp) emit_movsx_r32_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1798
1799		#define emit_movsx_r32_m16abs(e, dreg, addr) emit_movsx_r32_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1800		#define emit_movsx_r32_m16bd(e, dreg, base, disp) emit_movsx_r32_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
1801		#define emit_movsx_r32_m16isd(e, dreg, index, scale, disp) emit_movsx_r32_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1802
1803
1804		/*------------------------------------------------------------------
1805		emit_movzx_r32_*
1806		------------------------------------------------------------------*/
1807
1808		INLINE void emit_movzx_r32_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1809		{
1810		emit_byte(emitptr, PREFIX_OPSIZE);
1811		emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, sreg);
1812		}
1813
1814		INLINE void emit_movzx_r32_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1815		{
1816		emit_byte(emitptr, PREFIX_OPSIZE);
1817		emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
1818		}
1819
1820		INLINE void emit_movzx_r32_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1821		{
1822		emit_byte(emitptr, PREFIX_OPSIZE);
1823		emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Ew, OP_32BIT, dreg, sreg);
1824		}
1825
1826		INLINE void emit_movzx_r32_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1827		{
1828		emit_byte(emitptr, PREFIX_OPSIZE);
1829		emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Ew, OP_32BIT, dreg, base, index, scale, disp);
1830		}
1831
1832		#define emit_movzx_r32_m8abs(e, dreg, addr) emit_movzx_r32_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1833		#define emit_movzx_r32_m8bd(e, dreg, base, disp) emit_movzx_r32_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
1834		#define emit_movzx_r32_m8isd(e, dreg, index, scale, disp) emit_movzx_r32_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1835
1836		#define emit_movzx_r32_m16abs(e, dreg, addr) emit_movzx_r32_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1837		#define emit_movzx_r32_m16bd(e, dreg, base, disp) emit_movzx_r32_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
1838		#define emit_movzx_r32_m16isd(e, dreg, index, scale, disp) emit_movzx_r32_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1839
1840
1841		/*------------------------------------------------------------------
1842		emit_movsx_r64_*
1843		------------------------------------------------------------------*/
1844
1845		#ifdef PTR64
1846
1847		INLINE void emit_movsx_r64_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1848		{
1849		emit_byte(emitptr, PREFIX_OPSIZE);
1850		emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_64BIT, dreg, sreg);
1851		}
1852
1853		INLINE void emit_movsx_r64_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1854		{
1855		emit_byte(emitptr, PREFIX_OPSIZE);
1856		emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_64BIT, dreg, base, index, scale, disp);
1857		}
1858
1859		INLINE void emit_movsx_r64_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1860		{
1861		emit_byte(emitptr, PREFIX_OPSIZE);
1862		emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Ew, OP_64BIT, dreg, sreg);
1863		}
1864
1865		INLINE void emit_movsx_r64_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1866		{
1867		emit_byte(emitptr, PREFIX_OPSIZE);
1868		emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Ew, OP_64BIT, dreg, base, index, scale, disp);
1869		}
1870
1871		INLINE void emit_movsxd_r64_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1872		{
1873		emit_byte(emitptr, PREFIX_OPSIZE);
1874		emit_op_modrm_reg(emitptr, OP_MOVSXD_Gv_Ev, OP_64BIT, dreg, sreg);
1875		}
1876
1877		INLINE void emit_movsxd_r64_m32bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1878		{
1879		emit_byte(emitptr, PREFIX_OPSIZE);
1880		emit_op_modrm_mem(emitptr, OP_MOVSXD_Gv_Ev, OP_64BIT, dreg, base, index, scale, disp);
1881		}
1882
1883		#define emit_movsx_r64_m8abs(e, dreg, addr) emit_movsx_r64_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1884		#define emit_movsx_r64_m8bd(e, dreg, base, disp) emit_movsx_r64_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
1885		#define emit_movsx_r64_m8isd(e, dreg, index, scale, disp) emit_movsx_r64_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1886
1887		#define emit_movsx_r64_m16abs(e, dreg, addr) emit_movsx_r64_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1888		#define emit_movsx_r64_m16bd(e, dreg, base, disp) emit_movsx_r64_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
1889		#define emit_movsx_r64_m16isd(e, dreg, index, scale, disp) emit_movsx_r64_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1890
1891		#define emit_movsxd_r64_m32abs(e, dreg, addr) emit_movsxd_r64_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1892		#define emit_movsxd_r64_m32bd(e, dreg, base, disp) emit_movsxd_r64_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
1893		#define emit_movsxd_r64_m32isd(e, dreg, index, scale, disp) emit_movsxd_r64_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1894
1895		#endif
1896
1897
1898		/*------------------------------------------------------------------
1899		emit_movzx_r64_*
1900		------------------------------------------------------------------*/
1901
1902		#ifdef PTR64
1903
1904		INLINE void emit_movzx_r64_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1905		{
1906		emit_byte(emitptr, PREFIX_OPSIZE);
1907		emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_64BIT, dreg, sreg);
1908		}
1909
1910		INLINE void emit_movzx_r64_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1911		{
1912		emit_byte(emitptr, PREFIX_OPSIZE);
1913		emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_64BIT, dreg, base, index, scale, disp);
1914		}
1915
1916		INLINE void emit_movzx_r64_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1917		{
1918		emit_byte(emitptr, PREFIX_OPSIZE);
1919		emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Ew, OP_64BIT, dreg, sreg);
1920		}
1921
1922		INLINE void emit_movzx_r64_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
1923		{
1924		emit_byte(emitptr, PREFIX_OPSIZE);
1925		emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Ew, OP_64BIT, dreg, base, index, scale, disp);
1926		}
1927
1928		#define emit_movzx_r64_m8abs(e, dreg, addr) emit_movzx_r64_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1929		#define emit_movzx_r64_m8bd(e, dreg, base, disp) emit_movzx_r64_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
1930		#define emit_movzx_r64_m8isd(e, dreg, index, scale, disp) emit_movzx_r64_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1931
1932		#define emit_movzx_r64_m16abs(e, dreg, addr) emit_movzx_r64_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
1933		#define emit_movzx_r64_m16bd(e, dreg, base, disp) emit_movzx_r64_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
1934		#define emit_movzx_r64_m16isd(e, dreg, index, scale, disp) emit_movzx_r64_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
1935
1936		#endif
1937
1938
1939
1940		/***************************************************************************
1941		TEST EMITTERS
1942		***************************************************************************/
1943
1944		/*------------------------------------------------------------------
1945		emit_test_r8_*
1946		------------------------------------------------------------------*/
1947
1948		INLINE void emit_test_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm)
1949		{
1950		emit_op_modrm_reg(emitptr, OP_G3_Eb, OP_32BIT, 0, dreg);
1951		emit_byte(emitptr, imm);
1952		}
1953
1954		INLINE void emit_test_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1955		{
1956		emit_op_modrm_reg(emitptr, OP_TEST_Eb_Gb, OP_32BIT, sreg, dreg);
1957		}
1958
1959		INLINE void emit_test_m8bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
1960		{
1961		emit_op_modrm_mem(emitptr, OP_G3_Eb, OP_32BIT, 0, base, index, scale, disp);
1962		emit_byte(emitptr, imm);
1963		}
1964
1965		INLINE void emit_test_m8bisd_r8(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
1966		{
1967		emit_op_modrm_mem(emitptr, OP_TEST_Eb_Gb, OP_32BIT, sreg, base, index, scale, disp);
1968		}
1969
1970		#define emit_test_m8abs_imm(e, addr, imm) emit_test_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
1971		#define emit_test_m8bd_imm(e, base, disp, imm) emit_test_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
1972		#define emit_test_m8isd_imm(e, index, scale, disp, imm) emit_test_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
1973
1974		#define emit_test_m8abs_r8(e, addr, sreg) emit_test_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
1975		#define emit_test_m8bd_r8(e, base, disp, sreg) emit_test_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
1976		#define emit_test_m8isd_r8(e, index, scale, disp, sreg) emit_test_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
1977
1978
1979		/*------------------------------------------------------------------
1980		emit_test_r16_*
1981		------------------------------------------------------------------*/
1982
1983		INLINE void emit_test_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm)
1984		{
1985		emit_byte(emitptr, PREFIX_OPSIZE);
1986		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 0, dreg);
1987		emit_word(emitptr, imm);
1988		}
1989
1990		INLINE void emit_test_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
1991		{
1992		emit_byte(emitptr, PREFIX_OPSIZE);
1993		emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, dreg);
1994		}
1995
1996		INLINE void emit_test_m16bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT16 imm)
1997		{
1998		emit_byte(emitptr, PREFIX_OPSIZE);
1999		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 0, base, index, scale, disp);
2000		emit_word(emitptr, imm);
2001		}
2002
2003		INLINE void emit_test_m16bisd_r16(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
2004		{
2005		emit_byte(emitptr, PREFIX_OPSIZE);
2006		emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
2007		}
2008
2009		#define emit_test_m16abs_imm(e, addr, imm) emit_test_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2010		#define emit_test_m16bd_imm(e, base, disp, imm) emit_test_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2011		#define emit_test_m16isd_imm(e, index, scale, disp, imm) emit_test_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2012
2013		#define emit_test_m16abs_r16(e, addr, sreg) emit_test_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2014		#define emit_test_m16bd_r16(e, base, disp, sreg) emit_test_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
2015		#define emit_test_m16isd_r16(e, index, scale, disp, sreg) emit_test_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
2016
2017
2018		/*------------------------------------------------------------------
2019		emit_test_r32_*
2020		------------------------------------------------------------------*/
2021
2022		INLINE void emit_test_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm)
2023		{
2024		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 0, dreg);
2025		emit_dword(emitptr, imm);
2026		}
2027
2028		INLINE void emit_test_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg)
2029		{
2030		emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, dreg);
2031		}
2032
2033		INLINE void emit_test_m32bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
2034		{
2035		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 0, base, index, scale, disp);
2036		emit_dword(emitptr, imm);
2037		}
2038
2039		INLINE void emit_test_m32bisd_r32(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
2040		{
2041		emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
2042		}
2043
2044		#define emit_test_m32abs_imm(e, addr, imm) emit_test_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2045		#define emit_test_m32bd_imm(e, base, disp, imm) emit_test_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2046		#define emit_test_m32isd_imm(e, index, scale, disp, imm) emit_test_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2047
2048		#define emit_test_m32abs_r32(e, addr, sreg) emit_test_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2049		#define emit_test_m32bd_r32(e, base, disp, sreg) emit_test_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
2050		#define emit_test_m32isd_r32(e, index, scale, disp, sreg) emit_test_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
2051
2052
2053		/*------------------------------------------------------------------
2054		emit_test_r64_*
2055		------------------------------------------------------------------*/
2056
2057		#ifdef PTR64
2058
2059		INLINE void emit_test_r64_imm(x86code **emitptr, UINT8 dreg, UINT64 imm)
2060		{
2061		assert((INT32)imm == (INT64)imm);
2062		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, 0, dreg);
2063		emit_dword(emitptr, imm);
2064		}
2065
2066		INLINE void emit_test_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg)
2067		{
2068		emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_64BIT, sreg, dreg);
2069		}
2070
2071		INLINE void emit_test_m64bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT64 imm)
2072		{
2073		assert((INT32)imm == (INT64)imm);
2074		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, 0, base, index, scale, disp);
2075		emit_dword(emitptr, (INT32)imm);
2076		}
2077
2078		INLINE void emit_test_m64bisd_r64(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
2079		{
2080		emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_64BIT, sreg, base, index, scale, disp);
2081		}
2082
2083		#define emit_test_m64abs_imm(e, addr, imm) emit_test_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2084		#define emit_test_m64bd_imm(e, base, disp, imm) emit_test_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2085		#define emit_test_m64isd_imm(e, index, scale, disp, imm) emit_test_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2086
2087		#define emit_test_m64abs_r64(e, addr, sreg) emit_test_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2088		#define emit_test_m64bd_r64(e, base, disp, sreg) emit_test_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
2089		#define emit_test_m64isd_r64(e, index, scale, disp, sreg) emit_test_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
2090
2091		#endif
2092
2093
2094
2095		/***************************************************************************
2096		8-BIT ARITHMETIC EMITTERS
2097		***************************************************************************/
2098
2099		/*
2100		Note that the following code relies on this:
2101
2102		00-05 or /0 = ADD
2103		08-0d or /1 = OR
2104		10-15 or /2 = ADC
2105		18-1d or /3 = SBB
2106		20-25 or /4 = AND
2107		28-2d or /5 = SUB
2108		30-35 or /6 = XOR
2109		38-3d or /7 = CMP
2110		*/
2111
2112		/*------------------------------------------------------------------
2113		emit_arith_r8_*
2114		------------------------------------------------------------------*/
2115
2116		INLINE void emit_arith_r8_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
2117		{
2118		emit_op_modrm_reg(emitptr, OP_G1_Eb_Ib, OP_32BIT, opindex, dreg);
2119		emit_byte(emitptr, imm);
2120		}
2121
2122		INLINE void emit_arith_m8bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
2123		{
2124		emit_op_modrm_mem(emitptr, OP_G1_Eb_Ib, OP_32BIT, opindex, base, index, scale, disp);
2125		emit_byte(emitptr, imm);
2126		}
2127
2128		INLINE void emit_arith_r8_r8(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
2129		{
2130		emit_op_modrm_reg(emitptr, OP_ADD_Eb_Gb + 8 * opindex, OP_32BIT, dreg, sreg);
2131		}
2132
2133		INLINE void emit_arith_r8_m8bisd(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
2134		{
2135		emit_op_modrm_mem(emitptr, OP_ADD_Eb_Gb + 8 * opindex, OP_32BIT, dreg, base, index, scale, disp);
2136		}
2137
2138		INLINE void emit_arith_m8bisd_r8(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
2139		{
2140		emit_op_modrm_mem(emitptr, OP_ADD_Gb_Eb + 8 * opindex, OP_32BIT, sreg, base, index, scale, disp);
2141		}
2142
2143
2144		/*------------------------------------------------------------------
2145		emit_add_r8_*
2146		------------------------------------------------------------------*/
2147
2148		#define emit_add_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 0, dreg, imm)
2149		#define emit_add_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 0, base, index, scale, disp, imm)
2150		#define emit_add_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 0, dreg, sreg)
2151		#define emit_add_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 0, dreg, base, index, scale, disp)
2152		#define emit_add_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 0, base, index, scale, disp, sreg)
2153
2154		#define emit_add_m8abs_imm(e, addr, imm) emit_add_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2155		#define emit_add_m8bd_imm(e, base, disp, imm) emit_add_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2156		#define emit_add_m8isd_imm(e, index, scale, disp, imm) emit_add_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2157
2158		#define emit_add_r8_m8abs(e, dreg, addr) emit_add_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2159		#define emit_add_r8_m8bd(e, dreg, base, disp) emit_add_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
2160		#define emit_add_r8_m8isd(e, dreg, index, scale, disp) emit_add_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2161
2162		#define emit_add_m8abs_r8(e, addr, sreg) emit_add_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2163		#define emit_add_m8bd_r8(e, base, disp, sreg) emit_add_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
2164		#define emit_add_m8isd_r8(e, index, scale, disp, sreg) emit_add_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
2165
2166
2167		/*------------------------------------------------------------------
2168		emit_or_r8_*
2169		------------------------------------------------------------------*/
2170
2171		#define emit_or_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 1, dreg, imm)
2172		#define emit_or_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 1, base, index, scale, disp, imm)
2173		#define emit_or_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 1, dreg, sreg)
2174		#define emit_or_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 1, dreg, base, index, scale, disp)
2175		#define emit_or_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 1, base, index, scale, disp, sreg)
2176
2177		#define emit_or_m8abs_imm(e, addr, imm) emit_or_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2178		#define emit_or_m8bd_imm(e, base, disp, imm) emit_or_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2179		#define emit_or_m8isd_imm(e, index, scale, disp, imm) emit_or_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2180
2181		#define emit_or_r8_m8abs(e, dreg, addr) emit_or_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2182		#define emit_or_r8_m8bd(e, dreg, base, disp) emit_or_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
2183		#define emit_or_r8_m8isd(e, dreg, index, scale, disp) emit_or_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2184
2185		#define emit_or_m8abs_r8(e, addr, sreg) emit_or_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2186		#define emit_or_m8bd_r8(e, base, disp, sreg) emit_or_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
2187		#define emit_or_m8isd_r8(e, index, scale, disp, sreg) emit_or_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
2188
2189
2190		/*------------------------------------------------------------------
2191		emit_adc_r8_*
2192		------------------------------------------------------------------*/
2193
2194		#define emit_adc_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 2, dreg, imm)
2195		#define emit_adc_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 2, base, index, scale, disp, imm)
2196		#define emit_adc_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 2, dreg, sreg)
2197		#define emit_adc_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 2, dreg, base, index, scale, disp)
2198		#define emit_adc_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 2, base, index, scale, disp, sreg)
2199
2200		#define emit_adc_m8abs_imm(e, addr, imm) emit_adc_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2201		#define emit_adc_m8bd_imm(e, base, disp, imm) emit_adc_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2202		#define emit_adc_m8isd_imm(e, index, scale, disp, imm) emit_adc_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2203
2204		#define emit_adc_r8_m8abs(e, dreg, addr) emit_adc_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2205		#define emit_adc_r8_m8bd(e, dreg, base, disp) emit_adc_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
2206		#define emit_adc_r8_m8isd(e, dreg, index, scale, disp) emit_adc_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2207
2208		#define emit_adc_m8abs_r8(e, addr, sreg) emit_adc_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2209		#define emit_adc_m8bd_r8(e, base, disp, sreg) emit_adc_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
2210		#define emit_adc_m8isd_r8(e, index, scale, disp, sreg) emit_adc_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
2211
2212
2213		/*------------------------------------------------------------------
2214		emit_sbb_r8_*
2215		------------------------------------------------------------------*/
2216
2217		#define emit_sbb_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 3, dreg, imm)
2218		#define emit_sbb_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 3, base, index, scale, disp, imm)
2219		#define emit_sbb_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 3, dreg, sreg)
2220		#define emit_sbb_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 3, dreg, base, index, scale, disp)
2221		#define emit_sbb_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 3, base, index, scale, disp, sreg)
2222
2223		#define emit_sbb_m8abs_imm(e, addr, imm) emit_sbb_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2224		#define emit_sbb_m8bd_imm(e, base, disp, imm) emit_sbb_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2225		#define emit_sbb_m8isd_imm(e, index, scale, disp, imm) emit_sbb_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2226
2227		#define emit_sbb_r8_m8abs(e, dreg, addr) emit_sbb_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2228		#define emit_sbb_r8_m8bd(e, dreg, base, disp) emit_sbb_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
2229		#define emit_sbb_r8_m8isd(e, dreg, index, scale, disp) emit_sbb_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2230
2231		#define emit_sbb_m8abs_r8(e, addr, sreg) emit_sbb_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2232		#define emit_sbb_m8bd_r8(e, base, disp, sreg) emit_sbb_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
2233		#define emit_sbb_m8isd_r8(e, index, scale, disp, sreg) emit_sbb_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
2234
2235
2236		/*------------------------------------------------------------------
2237		emit_and_r8_*
2238		------------------------------------------------------------------*/
2239
2240		#define emit_and_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 4, dreg, imm)
2241		#define emit_and_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 4, base, index, scale, disp, imm)
2242		#define emit_and_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 4, dreg, sreg)
2243		#define emit_and_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 4, dreg, base, index, scale, disp)
2244		#define emit_and_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 4, base, index, scale, disp, sreg)
2245
2246		#define emit_and_m8abs_imm(e, addr, imm) emit_and_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2247		#define emit_and_m8bd_imm(e, base, disp, imm) emit_and_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2248		#define emit_and_m8isd_imm(e, index, scale, disp, imm) emit_and_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2249
2250		#define emit_and_r8_m8abs(e, dreg, addr) emit_and_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2251		#define emit_and_r8_m8bd(e, dreg, base, disp) emit_and_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
2252		#define emit_and_r8_m8isd(e, dreg, index, scale, disp) emit_and_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2253
2254		#define emit_and_m8abs_r8(e, addr, sreg) emit_and_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2255		#define emit_and_m8bd_r8(e, base, disp, sreg) emit_and_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
2256		#define emit_and_m8isd_r8(e, index, scale, disp, sreg) emit_and_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
2257
2258
2259		/*------------------------------------------------------------------
2260		emit_sub_r8_*
2261		------------------------------------------------------------------*/
2262
2263		#define emit_sub_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 5, dreg, imm)
2264		#define emit_sub_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 5, base, index, scale, disp, imm)
2265		#define emit_sub_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 5, dreg, sreg)
2266		#define emit_sub_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 5, dreg, base, index, scale, disp)
2267		#define emit_sub_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 5, base, index, scale, disp, sreg)
2268
2269		#define emit_sub_m8abs_imm(e, addr, imm) emit_sub_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2270		#define emit_sub_m8bd_imm(e, base, disp, imm) emit_sub_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2271		#define emit_sub_m8isd_imm(e, index, scale, disp, imm) emit_sub_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2272
2273		#define emit_sub_r8_m8abs(e, dreg, addr) emit_sub_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2274		#define emit_sub_r8_m8bd(e, dreg, base, disp) emit_sub_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
2275		#define emit_sub_r8_m8isd(e, dreg, index, scale, disp) emit_sub_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2276
2277		#define emit_sub_m8abs_r8(e, addr, sreg) emit_sub_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2278		#define emit_sub_m8bd_r8(e, base, disp, sreg) emit_sub_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
2279		#define emit_sub_m8isd_r8(e, index, scale, disp, sreg) emit_sub_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
2280
2281
2282		/*------------------------------------------------------------------
2283		emit_xor_r8_*
2284		------------------------------------------------------------------*/
2285
2286		#define emit_xor_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 6, dreg, imm)
2287		#define emit_xor_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 6, base, index, scale, disp, imm)
2288		#define emit_xor_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 6, dreg, sreg)
2289		#define emit_xor_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 6, dreg, base, index, scale, disp)
2290		#define emit_xor_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 6, base, index, scale, disp, sreg)
2291
2292		#define emit_xor_m8abs_imm(e, addr, imm) emit_xor_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2293		#define emit_xor_m8bd_imm(e, base, disp, imm) emit_xor_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2294		#define emit_xor_m8isd_imm(e, index, scale, disp, imm) emit_xor_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2295
2296		#define emit_xor_r8_m8abs(e, dreg, addr) emit_xor_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2297		#define emit_xor_r8_m8bd(e, dreg, base, disp) emit_xor_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
2298		#define emit_xor_r8_m8isd(e, dreg, index, scale, disp) emit_xor_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2299
2300		#define emit_xor_m8abs_r8(e, addr, sreg) emit_xor_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2301		#define emit_xor_m8bd_r8(e, base, disp, sreg) emit_xor_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
2302		#define emit_xor_m8isd_r8(e, index, scale, disp, sreg) emit_xor_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
2303
2304
2305		/*------------------------------------------------------------------
2306		emit_cmp_r8_*
2307		------------------------------------------------------------------*/
2308
2309		#define emit_cmp_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 7, dreg, imm)
2310		#define emit_cmp_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 7, base, index, scale, disp, imm)
2311		#define emit_cmp_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 7, dreg, sreg)
2312		#define emit_cmp_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 7, dreg, base, index, scale, disp)
2313		#define emit_cmp_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 7, base, index, scale, disp, sreg)
2314
2315		#define emit_cmp_m8abs_imm(e, addr, imm) emit_cmp_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2316		#define emit_cmp_m8bd_imm(e, base, disp, imm) emit_cmp_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2317		#define emit_cmp_m8isd_imm(e, index, scale, disp, imm) emit_cmp_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2318
2319		#define emit_cmp_r8_m8abs(e, dreg, addr) emit_cmp_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2320		#define emit_cmp_r8_m8bd(e, dreg, base, disp) emit_cmp_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
2321		#define emit_cmp_r8_m8isd(e, dreg, index, scale, disp) emit_cmp_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2322
2323		#define emit_cmp_m8abs_r8(e, addr, sreg) emit_cmp_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2324		#define emit_cmp_m8bd_r8(e, base, disp, sreg) emit_cmp_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
2325		#define emit_cmp_m8isd_r8(e, index, scale, disp, sreg) emit_cmp_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
2326
2327
2328
2329		/***************************************************************************
2330		16-BIT ARITHMETIC EMITTERS
2331		***************************************************************************/
2332
2333		/*
2334		Note that the following code relies on this:
2335
2336		00-05 or /0 = ADD
2337		08-0d or /1 = OR
2338		10-15 or /2 = ADC
2339		18-1d or /3 = SBB
2340		20-25 or /4 = AND
2341		28-2d or /5 = SUB
2342		30-35 or /6 = XOR
2343		38-3d or /7 = CMP
2344		*/
2345
2346		INLINE void emit_arith_r16_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT16 imm)
2347		{
2348		emit_byte(emitptr, PREFIX_OPSIZE);
2349	1347	if ((INT8)imm == (INT16)imm)
2350	1348	{
2351		emit_op_modrm_reg(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, dreg);
2352		emit_byte(emitptr, (INT8)imm);
	1349	emit_op_modrm_reg(emitptr, op8, opsize, reg, rm);
	1350	emit_byte(emitptr, imm);
2353	1351	}
2354	1352	else
2355	1353	{
2356		emit_op_modrm_reg(emitptr, ~~OP_G~~1~~_Ev_Iz~~, ~~OP_32BIT,~~ opindex, dreg);
	1354	emit_op_modrm_reg(emitptr, op16, opsize, reg, rm);
2357	1355	emit_word(emitptr, imm);
2358	1356	}
2359	1357	}
2360	1358
2361		INLINE void emit_arith_m16bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT16 imm)
	1359
	1360	/*-------------------------------------------------
	1361	emit_op_modrm_mem_imm816 - emit an opcode with
	1362	a memory modrm byte and an 8-bit or 16-bit
	1363	immediate
	1364	-------------------------------------------------*/
	1365
	1366	INLINE void emit_op_modrm_mem_imm816(x86code **emitptr, UINT32 op8, UINT32 op16, UINT8 opsize, UINT8 reg, DECLARE_MEMPARAMS, UINT16 imm)
2362	1367	{
2363		emit_byte(emitptr, PREFIX_OPSIZE);
2364	1368	if ((INT8)imm == (INT16)imm)
2365	1369	{
2366		emit_op_modrm_mem(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
2367		emit_byte(emitptr, (INT8)imm);
	1370	emit_op_modrm_mem(emitptr, op8, opsize, reg, MEMPARAMS);
	1371	emit_byte(emitptr, imm);
2368	1372	}
2369	1373	else
2370	1374	{
2371		emit_op_modrm_mem(emitptr, ~~OP_G~~1~~_Ev_Iz~~, ~~OP_32BIT,~~ op~~index, ba~~se, index, ~~scal~~e, ~~disp~~);
	1375	emit_op_modrm_mem(emitptr, op16, opsize, reg, MEMPARAMS);
2372	1376	emit_word(emitptr, imm);
2373	1377	}
2374	1378	}
2375	1379
2376		INLINE void emit_arith_r16_r16(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
2377		{
2378		emit_byte(emitptr, PREFIX_OPSIZE);
2379		emit_op_modrm_reg(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_32BIT, dreg, sreg);
2380		}
2381	1380
2382		INLINE void emit_arith_r16_m16bisd(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
2383		{
2384		emit_byte(emitptr, PREFIX_OPSIZE);
2385		emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_32BIT, dreg, base, index, scale, disp);
2386		}
	1381	/*-------------------------------------------------
	1382	emit_op_modrm_reg_imm32 - emit an opcode with a
	1383	register modrm byte and a 32-bit immediate
	1384	-------------------------------------------------*/
2387	1385
2388		INLINE void emit_~~arith~~_m~~16bis~~d_r16(x86code **emitptr, UINT8 op~~index~~, UINT8 base, UINT8 ~~ind~~ex, UINT8 ~~scale~~, INT32 di~~sp, UINT8 sreg~~)
	1386	INLINE void emit_op_modrm_reg_imm32(x86code **emitptr, UINT32 op, UINT8 opsize, UINT8 reg, UINT8 rm, UINT32 imm)
2389	1387	{
2390		emit_byte(emitptr, PREFIX_OPSIZE);
2391		emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_32BIT, sreg, base, index, scale, disp);
	1388	emit_op_modrm_reg(emitptr, op, opsize, reg, rm);
	1389	emit_dword(emitptr, imm);
2392	1390	}
2393	1391
2394	1392
2395		/*------------------------------------------------------------------
2396		emit_add_r16_*
2397		------------------------------------------------------------------*/
	1393	/*-------------------------------------------------
	1394	emit_op_modrm_mem_imm32 - emit an opcode with a
	1395	memory modrm byte and a 32-bit immediate
	1396	-------------------------------------------------*/
2398	1397
2399		#define emit_add_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 0, dreg, imm)
2400		#define emit_add_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 0, base, index, scale, disp, imm)
2401		#define emit_add_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 0, dreg, sreg)
2402		#define emit_add_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 0, dreg, base, index, scale, disp)
2403		#define emit_add_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 0, base, index, scale, disp, sreg)
2404
2405		#define emit_add_m16abs_imm(e, addr, imm) emit_add_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2406		#define emit_add_m16bd_imm(e, base, disp, imm) emit_add_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2407		#define emit_add_m16isd_imm(e, index, scale, disp, imm) emit_add_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2408
2409		#define emit_add_r16_m16abs(e, dreg, addr) emit_add_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2410		#define emit_add_r16_m16bd(e, dreg, base, disp) emit_add_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
2411		#define emit_add_r16_m16isd(e, dreg, index, scale, disp) emit_add_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2412
2413		#define emit_add_m16abs_r16(e, addr, sreg) emit_add_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2414		#define emit_add_m16bd_r16(e, base, disp, sreg) emit_add_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
2415		#define emit_add_m16isd_r16(e, index, scale, disp, sreg) emit_add_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
2416
2417
2418		/*------------------------------------------------------------------
2419		emit_or_r16_*
2420		------------------------------------------------------------------*/
2421
2422		#define emit_or_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 1, dreg, imm)
2423		#define emit_or_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 1, base, index, scale, disp, imm)
2424		#define emit_or_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 1, dreg, sreg)
2425		#define emit_or_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 1, dreg, base, index, scale, disp)
2426		#define emit_or_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 1, base, index, scale, disp, sreg)
2427
2428		#define emit_or_m16abs_imm(e, addr, imm) emit_or_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2429		#define emit_or_m16bd_imm(e, base, disp, imm) emit_or_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2430		#define emit_or_m16isd_imm(e, index, scale, disp, imm) emit_or_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2431
2432		#define emit_or_r16_m16abs(e, dreg, addr) emit_or_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2433		#define emit_or_r16_m16bd(e, dreg, base, disp) emit_or_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
2434		#define emit_or_r16_m16isd(e, dreg, index, scale, disp) emit_or_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2435
2436		#define emit_or_m16abs_r16(e, addr, sreg) emit_or_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2437		#define emit_or_m16bd_r16(e, base, disp, sreg) emit_or_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
2438		#define emit_or_m16isd_r16(e, index, scale, disp, sreg) emit_or_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
2439
2440
2441		/*------------------------------------------------------------------
2442		emit_adc_r16_*
2443		------------------------------------------------------------------*/
2444
2445		#define emit_adc_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 2, dreg, imm)
2446		#define emit_adc_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 2, base, index, scale, disp, imm)
2447		#define emit_adc_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 2, dreg, sreg)
2448		#define emit_adc_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 2, dreg, base, index, scale, disp)
2449		#define emit_adc_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 2, base, index, scale, disp, sreg)
2450
2451		#define emit_adc_m16abs_imm(e, addr, imm) emit_adc_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2452		#define emit_adc_m16bd_imm(e, base, disp, imm) emit_adc_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2453		#define emit_adc_m16isd_imm(e, index, scale, disp, imm) emit_adc_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2454
2455		#define emit_adc_r16_m16abs(e, dreg, addr) emit_adc_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2456		#define emit_adc_r16_m16bd(e, dreg, base, disp) emit_adc_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
2457		#define emit_adc_r16_m16isd(e, dreg, index, scale, disp) emit_adc_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2458
2459		#define emit_adc_m16abs_r16(e, addr, sreg) emit_adc_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2460		#define emit_adc_m16bd_r16(e, base, disp, sreg) emit_adc_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
2461		#define emit_adc_m16isd_r16(e, index, scale, disp, sreg) emit_adc_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
2462
2463
2464		/*------------------------------------------------------------------
2465		emit_sbb_r16_*
2466		------------------------------------------------------------------*/
2467
2468		#define emit_sbb_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 3, dreg, imm)
2469		#define emit_sbb_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 3, base, index, scale, disp, imm)
2470		#define emit_sbb_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 3, dreg, sreg)
2471		#define emit_sbb_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 3, dreg, base, index, scale, disp)
2472		#define emit_sbb_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 3, base, index, scale, disp, sreg)
2473
2474		#define emit_sbb_m16abs_imm(e, addr, imm) emit_sbb_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2475		#define emit_sbb_m16bd_imm(e, base, disp, imm) emit_sbb_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2476		#define emit_sbb_m16isd_imm(e, index, scale, disp, imm) emit_sbb_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2477
2478		#define emit_sbb_r16_m16abs(e, dreg, addr) emit_sbb_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2479		#define emit_sbb_r16_m16bd(e, dreg, base, disp) emit_sbb_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
2480		#define emit_sbb_r16_m16isd(e, dreg, index, scale, disp) emit_sbb_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2481
2482		#define emit_sbb_m16abs_r16(e, addr, sreg) emit_sbb_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2483		#define emit_sbb_m16bd_r16(e, base, disp, sreg) emit_sbb_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
2484		#define emit_sbb_m16isd_r16(e, index, scale, disp, sreg) emit_sbb_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
2485
2486
2487		/*------------------------------------------------------------------
2488		emit_and_r16_*
2489		------------------------------------------------------------------*/
2490
2491		#define emit_and_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 4, dreg, imm)
2492		#define emit_and_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 4, base, index, scale, disp, imm)
2493		#define emit_and_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 4, dreg, sreg)
2494		#define emit_and_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 4, dreg, base, index, scale, disp)
2495		#define emit_and_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 4, base, index, scale, disp, sreg)
2496
2497		#define emit_and_m16abs_imm(e, addr, imm) emit_and_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2498		#define emit_and_m16bd_imm(e, base, disp, imm) emit_and_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2499		#define emit_and_m16isd_imm(e, index, scale, disp, imm) emit_and_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2500
2501		#define emit_and_r16_m16abs(e, dreg, addr) emit_and_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2502		#define emit_and_r16_m16bd(e, dreg, base, disp) emit_and_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
2503		#define emit_and_r16_m16isd(e, dreg, index, scale, disp) emit_and_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2504
2505		#define emit_and_m16abs_r16(e, addr, sreg) emit_and_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2506		#define emit_and_m16bd_r16(e, base, disp, sreg) emit_and_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
2507		#define emit_and_m16isd_r16(e, index, scale, disp, sreg) emit_and_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
2508
2509
2510		/*------------------------------------------------------------------
2511		emit_sub_r16_*
2512		------------------------------------------------------------------*/
2513
2514		#define emit_sub_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 5, dreg, imm)
2515		#define emit_sub_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 5, base, index, scale, disp, imm)
2516		#define emit_sub_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 5, dreg, sreg)
2517		#define emit_sub_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 5, dreg, base, index, scale, disp)
2518		#define emit_sub_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 5, base, index, scale, disp, sreg)
2519
2520		#define emit_sub_m16abs_imm(e, addr, imm) emit_sub_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2521		#define emit_sub_m16bd_imm(e, base, disp, imm) emit_sub_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2522		#define emit_sub_m16isd_imm(e, index, scale, disp, imm) emit_sub_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2523
2524		#define emit_sub_r16_m16abs(e, dreg, addr) emit_sub_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2525		#define emit_sub_r16_m16bd(e, dreg, base, disp) emit_sub_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
2526		#define emit_sub_r16_m16isd(e, dreg, index, scale, disp) emit_sub_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2527
2528		#define emit_sub_m16abs_r16(e, addr, sreg) emit_sub_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2529		#define emit_sub_m16bd_r16(e, base, disp, sreg) emit_sub_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
2530		#define emit_sub_m16isd_r16(e, index, scale, disp, sreg) emit_sub_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
2531
2532
2533		/*------------------------------------------------------------------
2534		emit_xor_r16_*
2535		------------------------------------------------------------------*/
2536
2537		#define emit_xor_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 6, dreg, imm)
2538		#define emit_xor_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 6, base, index, scale, disp, imm)
2539		#define emit_xor_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 6, dreg, sreg)
2540		#define emit_xor_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 6, dreg, base, index, scale, disp)
2541		#define emit_xor_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 6, base, index, scale, disp, sreg)
2542
2543		#define emit_xor_m16abs_imm(e, addr, imm) emit_xor_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2544		#define emit_xor_m16bd_imm(e, base, disp, imm) emit_xor_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2545		#define emit_xor_m16isd_imm(e, index, scale, disp, imm) emit_xor_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2546
2547		#define emit_xor_r16_m16abs(e, dreg, addr) emit_xor_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2548		#define emit_xor_r16_m16bd(e, dreg, base, disp) emit_xor_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
2549		#define emit_xor_r16_m16isd(e, dreg, index, scale, disp) emit_xor_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2550
2551		#define emit_xor_m16abs_r16(e, addr, sreg) emit_xor_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2552		#define emit_xor_m16bd_r16(e, base, disp, sreg) emit_xor_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
2553		#define emit_xor_m16isd_r16(e, index, scale, disp, sreg) emit_xor_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
2554
2555
2556		/*------------------------------------------------------------------
2557		emit_cmp_r16_*
2558		------------------------------------------------------------------*/
2559
2560		#define emit_cmp_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 7, dreg, imm)
2561		#define emit_cmp_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 7, base, index, scale, disp, imm)
2562		#define emit_cmp_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 7, dreg, sreg)
2563		#define emit_cmp_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 7, dreg, base, index, scale, disp)
2564		#define emit_cmp_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 7, base, index, scale, disp, sreg)
2565
2566		#define emit_cmp_m16abs_imm(e, addr, imm) emit_cmp_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2567		#define emit_cmp_m16bd_imm(e, base, disp, imm) emit_cmp_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2568		#define emit_cmp_m16isd_imm(e, index, scale, disp, imm) emit_cmp_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2569
2570		#define emit_cmp_r16_m16abs(e, dreg, addr) emit_cmp_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2571		#define emit_cmp_r16_m16bd(e, dreg, base, disp) emit_cmp_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
2572		#define emit_cmp_r16_m16isd(e, dreg, index, scale, disp) emit_cmp_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2573
2574		#define emit_cmp_m16abs_r16(e, addr, sreg) emit_cmp_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2575		#define emit_cmp_m16bd_r16(e, base, disp, sreg) emit_cmp_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
2576		#define emit_cmp_m16isd_r16(e, index, scale, disp, sreg) emit_cmp_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
2577
2578
2579
2580		/***************************************************************************
2581		32-BIT ARITHMETIC EMITTERS
2582		***************************************************************************/
2583
2584		/*
2585		Note that the following code relies on this:
2586
2587		00-05 or /0 = ADD
2588		08-0d or /1 = OR
2589		10-15 or /2 = ADC
2590		18-1d or /3 = SBB
2591		20-25 or /4 = AND
2592		28-2d or /5 = SUB
2593		30-35 or /6 = XOR
2594		38-3d or /7 = CMP
2595		*/
2596
2597		INLINE void emit_arith_r32_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT32 imm)
	1398	INLINE void emit_op_modrm_mem_imm32(x86code **emitptr, UINT32 op, UINT8 opsize, UINT8 reg, DECLARE_MEMPARAMS, UINT32 imm)
2598	1399	{
2599		if ((INT8)imm == (INT32)imm)
2600		{
2601		emit_op_modrm_reg(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, dreg);
2602		emit_byte(emitptr, (INT8)imm);
2603		}
2604		else
2605		{
2606		emit_op_modrm_reg(emitptr, OP_G1_Ev_Iz, OP_32BIT, opindex, dreg);
2607		emit_dword(emitptr, imm);
2608		}
	1400	emit_op_modrm_mem(emitptr, op, opsize, reg, MEMPARAMS);
	1401	emit_dword(emitptr, imm);
2609	1402	}
2610	1403
2611		INLINE void emit_arith_m32bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
2612		{
2613		if ((INT8)imm == (INT32)imm)
2614		{
2615		emit_op_modrm_mem(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
2616		emit_byte(emitptr, (INT8)imm);
2617		}
2618		else
2619		{
2620		emit_op_modrm_mem(emitptr, OP_G1_Ev_Iz, OP_32BIT, opindex, base, index, scale, disp);
2621		emit_dword(emitptr, imm);
2622		}
2623		}
2624	1404
2625		INLINE void emit_arith_r32_r32(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
2626		{
2627		emit_op_modrm_reg(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_32BIT, dreg, sreg);
2628		}
	1405	/*-------------------------------------------------
	1406	emit_op_modrm_reg_imm832 - emit an opcode with
	1407	a register modrm byte and an 8-bit or 32-bit
	1408	immediate
	1409	-------------------------------------------------*/
2629	1410
2630		INLINE void emit_ar~~ith~~_r32_m32~~bisd~~(x86code **emitptr, UINT8 op~~index~~, UINT8 ~~dreg~~, UINT8 base, UINT8 ~~ind~~ex, UINT8 ~~scale~~, INT32 disp)
	1411	INLINE void emit_op_modrm_reg_imm832(x86code **emitptr, UINT32 op8, UINT32 op32, UINT8 opsize, UINT8 reg, UINT8 rm, UINT32 imm)
2631	1412	{
2632		emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_32BIT, dreg, base, index, scale, disp);
2633		}
2634
2635		INLINE void emit_arith_m32bisd_r32(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
2636		{
2637		emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_32BIT, sreg, base, index, scale, disp);
2638		}
2639
2640
2641		/*------------------------------------------------------------------
2642		emit_add_r32_*
2643		------------------------------------------------------------------*/
2644
2645		#define emit_add_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 0, dreg, imm)
2646		#define emit_add_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 0, base, index, scale, disp, imm)
2647		#define emit_add_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 0, dreg, sreg)
2648		#define emit_add_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 0, dreg, base, index, scale, disp)
2649		#define emit_add_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 0, base, index, scale, disp, sreg)
2650
2651		#define emit_add_m32abs_imm(e, addr, imm) emit_add_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2652		#define emit_add_m32bd_imm(e, base, disp, imm) emit_add_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2653		#define emit_add_m32isd_imm(e, index, scale, disp, imm) emit_add_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2654
2655		#define emit_add_r32_m32abs(e, dreg, addr) emit_add_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2656		#define emit_add_r32_m32bd(e, dreg, base, disp) emit_add_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
2657		#define emit_add_r32_m32isd(e, dreg, index, scale, disp) emit_add_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2658
2659		#define emit_add_m32abs_r32(e, addr, sreg) emit_add_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2660		#define emit_add_m32bd_r32(e, base, disp, sreg) emit_add_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
2661		#define emit_add_m32isd_r32(e, index, scale, disp, sreg) emit_add_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
2662
2663
2664		/*------------------------------------------------------------------
2665		emit_or_r32_*
2666		------------------------------------------------------------------*/
2667
2668		#define emit_or_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 1, dreg, imm)
2669		#define emit_or_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 1, base, index, scale, disp, imm)
2670		#define emit_or_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 1, dreg, sreg)
2671		#define emit_or_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 1, dreg, base, index, scale, disp)
2672		#define emit_or_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 1, base, index, scale, disp, sreg)
2673
2674		#define emit_or_m32abs_imm(e, addr, imm) emit_or_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2675		#define emit_or_m32bd_imm(e, base, disp, imm) emit_or_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2676		#define emit_or_m32isd_imm(e, index, scale, disp, imm) emit_or_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2677
2678		#define emit_or_r32_m32abs(e, dreg, addr) emit_or_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2679		#define emit_or_r32_m32bd(e, dreg, base, disp) emit_or_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
2680		#define emit_or_r32_m32isd(e, dreg, index, scale, disp) emit_or_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2681
2682		#define emit_or_m32abs_r32(e, addr, sreg) emit_or_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2683		#define emit_or_m32bd_r32(e, base, disp, sreg) emit_or_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
2684		#define emit_or_m32isd_r32(e, index, scale, disp, sreg) emit_or_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
2685
2686
2687		/*------------------------------------------------------------------
2688		emit_adc_r32_*
2689		------------------------------------------------------------------*/
2690
2691		#define emit_adc_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 2, dreg, imm)
2692		#define emit_adc_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 2, base, index, scale, disp, imm)
2693		#define emit_adc_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 2, dreg, sreg)
2694		#define emit_adc_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 2, dreg, base, index, scale, disp)
2695		#define emit_adc_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 2, base, index, scale, disp, sreg)
2696
2697		#define emit_adc_m32abs_imm(e, addr, imm) emit_adc_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2698		#define emit_adc_m32bd_imm(e, base, disp, imm) emit_adc_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2699		#define emit_adc_m32isd_imm(e, index, scale, disp, imm) emit_adc_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2700
2701		#define emit_adc_r32_m32abs(e, dreg, addr) emit_adc_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2702		#define emit_adc_r32_m32bd(e, dreg, base, disp) emit_adc_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
2703		#define emit_adc_r32_m32isd(e, dreg, index, scale, disp) emit_adc_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2704
2705		#define emit_adc_m32abs_r32(e, addr, sreg) emit_adc_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2706		#define emit_adc_m32bd_r32(e, base, disp, sreg) emit_adc_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
2707		#define emit_adc_m32isd_r32(e, index, scale, disp, sreg) emit_adc_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
2708
2709
2710		/*------------------------------------------------------------------
2711		emit_sbb_r32_*
2712		------------------------------------------------------------------*/
2713
2714		#define emit_sbb_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 3, dreg, imm)
2715		#define emit_sbb_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 3, base, index, scale, disp, imm)
2716		#define emit_sbb_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 3, dreg, sreg)
2717		#define emit_sbb_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 3, dreg, base, index, scale, disp)
2718		#define emit_sbb_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 3, base, index, scale, disp, sreg)
2719
2720		#define emit_sbb_m32abs_imm(e, addr, imm) emit_sbb_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2721		#define emit_sbb_m32bd_imm(e, base, disp, imm) emit_sbb_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2722		#define emit_sbb_m32isd_imm(e, index, scale, disp, imm) emit_sbb_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2723
2724		#define emit_sbb_r32_m32abs(e, dreg, addr) emit_sbb_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2725		#define emit_sbb_r32_m32bd(e, dreg, base, disp) emit_sbb_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
2726		#define emit_sbb_r32_m32isd(e, dreg, index, scale, disp) emit_sbb_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2727
2728		#define emit_sbb_m32abs_r32(e, addr, sreg) emit_sbb_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2729		#define emit_sbb_m32bd_r32(e, base, disp, sreg) emit_sbb_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
2730		#define emit_sbb_m32isd_r32(e, index, scale, disp, sreg) emit_sbb_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
2731
2732
2733		/*------------------------------------------------------------------
2734		emit_and_r32_*
2735		------------------------------------------------------------------*/
2736
2737		#define emit_and_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 4, dreg, imm)
2738		#define emit_and_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 4, base, index, scale, disp, imm)
2739		#define emit_and_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 4, dreg, sreg)
2740		#define emit_and_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 4, dreg, base, index, scale, disp)
2741		#define emit_and_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 4, base, index, scale, disp, sreg)
2742
2743		#define emit_and_m32abs_imm(e, addr, imm) emit_and_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2744		#define emit_and_m32bd_imm(e, base, disp, imm) emit_and_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2745		#define emit_and_m32isd_imm(e, index, scale, disp, imm) emit_and_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2746
2747		#define emit_and_r32_m32abs(e, dreg, addr) emit_and_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2748		#define emit_and_r32_m32bd(e, dreg, base, disp) emit_and_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
2749		#define emit_and_r32_m32isd(e, dreg, index, scale, disp) emit_and_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2750
2751		#define emit_and_m32abs_r32(e, addr, sreg) emit_and_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2752		#define emit_and_m32bd_r32(e, base, disp, sreg) emit_and_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
2753		#define emit_and_m32isd_r32(e, index, scale, disp, sreg) emit_and_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
2754
2755
2756		/*------------------------------------------------------------------
2757		emit_sub_r32_*
2758		------------------------------------------------------------------*/
2759
2760		#define emit_sub_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 5, dreg, imm)
2761		#define emit_sub_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 5, base, index, scale, disp, imm)
2762		#define emit_sub_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 5, dreg, sreg)
2763		#define emit_sub_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 5, dreg, base, index, scale, disp)
2764		#define emit_sub_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 5, base, index, scale, disp, sreg)
2765
2766		#define emit_sub_m32abs_imm(e, addr, imm) emit_sub_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2767		#define emit_sub_m32bd_imm(e, base, disp, imm) emit_sub_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2768		#define emit_sub_m32isd_imm(e, index, scale, disp, imm) emit_sub_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2769
2770		#define emit_sub_r32_m32abs(e, dreg, addr) emit_sub_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2771		#define emit_sub_r32_m32bd(e, dreg, base, disp) emit_sub_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
2772		#define emit_sub_r32_m32isd(e, dreg, index, scale, disp) emit_sub_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2773
2774		#define emit_sub_m32abs_r32(e, addr, sreg) emit_sub_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2775		#define emit_sub_m32bd_r32(e, base, disp, sreg) emit_sub_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
2776		#define emit_sub_m32isd_r32(e, index, scale, disp, sreg) emit_sub_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
2777
2778
2779		/*------------------------------------------------------------------
2780		emit_xor_r32_*
2781		------------------------------------------------------------------*/
2782
2783		#define emit_xor_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 6, dreg, imm)
2784		#define emit_xor_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 6, base, index, scale, disp, imm)
2785		#define emit_xor_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 6, dreg, sreg)
2786		#define emit_xor_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 6, dreg, base, index, scale, disp)
2787		#define emit_xor_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 6, base, index, scale, disp, sreg)
2788
2789		#define emit_xor_m32abs_imm(e, addr, imm) emit_xor_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2790		#define emit_xor_m32bd_imm(e, base, disp, imm) emit_xor_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2791		#define emit_xor_m32isd_imm(e, index, scale, disp, imm) emit_xor_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2792
2793		#define emit_xor_r32_m32abs(e, dreg, addr) emit_xor_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2794		#define emit_xor_r32_m32bd(e, dreg, base, disp) emit_xor_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
2795		#define emit_xor_r32_m32isd(e, dreg, index, scale, disp) emit_xor_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2796
2797		#define emit_xor_m32abs_r32(e, addr, sreg) emit_xor_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2798		#define emit_xor_m32bd_r32(e, base, disp, sreg) emit_xor_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
2799		#define emit_xor_m32isd_r32(e, index, scale, disp, sreg) emit_xor_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
2800
2801
2802		/*------------------------------------------------------------------
2803		emit_cmp_r32_*
2804		------------------------------------------------------------------*/
2805
2806		#define emit_cmp_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 7, dreg, imm)
2807		#define emit_cmp_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 7, base, index, scale, disp, imm)
2808		#define emit_cmp_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 7, dreg, sreg)
2809		#define emit_cmp_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 7, dreg, base, index, scale, disp)
2810		#define emit_cmp_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 7, base, index, scale, disp, sreg)
2811
2812		#define emit_cmp_m32abs_imm(e, addr, imm) emit_cmp_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2813		#define emit_cmp_m32bd_imm(e, base, disp, imm) emit_cmp_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2814		#define emit_cmp_m32isd_imm(e, index, scale, disp, imm) emit_cmp_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2815
2816		#define emit_cmp_r32_m32abs(e, dreg, addr) emit_cmp_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2817		#define emit_cmp_r32_m32bd(e, dreg, base, disp) emit_cmp_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
2818		#define emit_cmp_r32_m32isd(e, dreg, index, scale, disp) emit_cmp_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2819
2820		#define emit_cmp_m32abs_r32(e, addr, sreg) emit_cmp_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2821		#define emit_cmp_m32bd_r32(e, base, disp, sreg) emit_cmp_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
2822		#define emit_cmp_m32isd_r32(e, index, scale, disp, sreg) emit_cmp_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
2823
2824
2825
2826		/***************************************************************************
2827		64-BIT ARITHMETIC EMITTERS
2828		***************************************************************************/
2829
2830		#ifdef PTR64
2831		/*
2832		Note that the following code relies on this:
2833
2834		00-05 or /0 = ADD
2835		08-0d or /1 = OR
2836		10-15 or /2 = ADC
2837		18-1d or /3 = SBB
2838		20-25 or /4 = AND
2839		28-2d or /5 = SUB
2840		30-35 or /6 = XOR
2841		38-3d or /7 = CMP
2842		*/
2843
2844		INLINE void emit_arith_r64_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT32 imm)
2845		{
2846	1413	if ((INT8)imm == (INT32)imm)
2847	1414	{
2848		emit_op_modrm_reg(emitptr, OP_G1_Ev_Ib, OP_64BIT, opindex, dreg);
2849		emit_byte(emitptr, (INT8)imm);
	1415	emit_op_modrm_reg(emitptr, op8, opsize, reg, rm);
	1416	emit_byte(emitptr, imm);
2850	1417	}
2851	1418	else
2852	1419	{
2853		emit_op_modrm_reg(emitptr, ~~OP_G1_Ev_Iz~~, ~~OP_64BIT,~~ opindex, dreg);
	1420	emit_op_modrm_reg(emitptr, op32, opsize, reg, rm);
2854	1421	emit_dword(emitptr, imm);
2855	1422	}
2856	1423	}
2857	1424
2858		INLINE void emit_arith_m64bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
2859		{
2860		if ((INT8)imm == (INT32)imm)
2861		{
2862		emit_op_modrm_mem(emitptr, OP_G1_Ev_Ib, OP_64BIT, opindex, base, index, scale, disp);
2863		emit_byte(emitptr, (INT8)imm);
2864		}
2865		else
2866		{
2867		emit_op_modrm_mem(emitptr, OP_G1_Ev_Iz, OP_64BIT, opindex, base, index, scale, disp);
2868		emit_dword(emitptr, imm);
2869		}
2870		}
2871	1425
2872		INLINE void emit_arith_r64_r64(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
2873		{
2874		emit_op_modrm_reg(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_64BIT, dreg, sreg);
2875		}
	1426	/*-------------------------------------------------
	1427	emit_op_modrm_mem_imm832 - emit an opcode with
	1428	a memory modrm byte and an 8-bit or 32-bit
	1429	immediate
	1430	-------------------------------------------------*/
2876	1431
2877		INLINE void emit_~~arith~~_r64_m~~64b~~isd(x86code **emitptr, UINT8 op~~index~~, UINT8 ~~dreg~~, UINT8 base, UINT8 ~~ind~~ex, ~~UINT8 scale~~, INT32 disp)
	1432	INLINE void emit_op_modrm_mem_imm832(x86code **emitptr, UINT32 op8, UINT32 op32, UINT8 opsize, UINT8 reg, DECLARE_MEMPARAMS, UINT32 imm)
2878	1433	{
2879		emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_64BIT, dreg, base, index, scale, disp);
2880		}
2881
2882		INLINE void emit_arith_m64bisd_r64(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
2883		{
2884		emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_64BIT, sreg, base, index, scale, disp);
2885		}
2886
2887
2888		/*------------------------------------------------------------------
2889		emit_add_r64_*
2890		------------------------------------------------------------------*/
2891
2892		#define emit_add_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 0, dreg, imm)
2893		#define emit_add_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 0, base, index, scale, disp, imm)
2894		#define emit_add_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 0, dreg, sreg)
2895		#define emit_add_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 0, dreg, base, index, scale, disp)
2896		#define emit_add_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 0, base, index, scale, disp, sreg)
2897
2898		#define emit_add_m64abs_imm(e, addr, imm) emit_add_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2899		#define emit_add_m64bd_imm(e, base, disp, imm) emit_add_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2900		#define emit_add_m64isd_imm(e, index, scale, disp, imm) emit_add_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2901
2902		#define emit_add_r64_m64abs(e, dreg, addr) emit_add_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2903		#define emit_add_r64_m64bd(e, dreg, base, disp) emit_add_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
2904		#define emit_add_r64_m64isd(e, dreg, index, scale, disp) emit_add_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2905
2906		#define emit_add_m64abs_r64(e, addr, sreg) emit_add_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2907		#define emit_add_m64bd_r64(e, base, disp, sreg) emit_add_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
2908		#define emit_add_m64isd_r64(e, index, scale, disp, sreg) emit_add_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
2909
2910
2911		/*------------------------------------------------------------------
2912		emit_or_r64_*
2913		------------------------------------------------------------------*/
2914
2915		#define emit_or_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 1, dreg, imm)
2916		#define emit_or_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 1, base, index, scale, disp, imm)
2917		#define emit_or_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 1, dreg, sreg)
2918		#define emit_or_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 1, dreg, base, index, scale, disp)
2919		#define emit_or_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 1, base, index, scale, disp, sreg)
2920
2921		#define emit_or_m64abs_imm(e, addr, imm) emit_or_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2922		#define emit_or_m64bd_imm(e, base, disp, imm) emit_or_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2923		#define emit_or_m64isd_imm(e, index, scale, disp, imm) emit_or_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2924
2925		#define emit_or_r64_m64abs(e, dreg, addr) emit_or_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2926		#define emit_or_r64_m64bd(e, dreg, base, disp) emit_or_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
2927		#define emit_or_r64_m64isd(e, dreg, index, scale, disp) emit_or_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2928
2929		#define emit_or_m64abs_r64(e, addr, sreg) emit_or_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2930		#define emit_or_m64bd_r64(e, base, disp, sreg) emit_or_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
2931		#define emit_or_m64isd_r64(e, index, scale, disp, sreg) emit_or_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
2932
2933
2934		/*------------------------------------------------------------------
2935		emit_adc_r64_*
2936		------------------------------------------------------------------*/
2937
2938		#define emit_adc_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 2, dreg, imm)
2939		#define emit_adc_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 2, base, index, scale, disp, imm)
2940		#define emit_adc_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 2, dreg, sreg)
2941		#define emit_adc_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 2, dreg, base, index, scale, disp)
2942		#define emit_adc_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 2, base, index, scale, disp, sreg)
2943
2944		#define emit_adc_m64abs_imm(e, addr, imm) emit_adc_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2945		#define emit_adc_m64bd_imm(e, base, disp, imm) emit_adc_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2946		#define emit_adc_m64isd_imm(e, index, scale, disp, imm) emit_adc_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2947
2948		#define emit_adc_r64_m64abs(e, dreg, addr) emit_adc_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2949		#define emit_adc_r64_m64bd(e, dreg, base, disp) emit_adc_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
2950		#define emit_adc_r64_m64isd(e, dreg, index, scale, disp) emit_adc_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2951
2952		#define emit_adc_m64abs_r64(e, addr, sreg) emit_adc_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2953		#define emit_adc_m64bd_r64(e, base, disp, sreg) emit_adc_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
2954		#define emit_adc_m64isd_r64(e, index, scale, disp, sreg) emit_adc_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
2955
2956
2957		/*------------------------------------------------------------------
2958		emit_sbb_r64_*
2959		------------------------------------------------------------------*/
2960
2961		#define emit_sbb_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 3, dreg, imm)
2962		#define emit_sbb_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 3, base, index, scale, disp, imm)
2963		#define emit_sbb_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 3, dreg, sreg)
2964		#define emit_sbb_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 3, dreg, base, index, scale, disp)
2965		#define emit_sbb_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 3, base, index, scale, disp, sreg)
2966
2967		#define emit_sbb_m64abs_imm(e, addr, imm) emit_sbb_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2968		#define emit_sbb_m64bd_imm(e, base, disp, imm) emit_sbb_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2969		#define emit_sbb_m64isd_imm(e, index, scale, disp, imm) emit_sbb_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2970
2971		#define emit_sbb_r64_m64abs(e, dreg, addr) emit_sbb_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2972		#define emit_sbb_r64_m64bd(e, dreg, base, disp) emit_sbb_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
2973		#define emit_sbb_r64_m64isd(e, dreg, index, scale, disp) emit_sbb_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2974
2975		#define emit_sbb_m64abs_r64(e, addr, sreg) emit_sbb_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2976		#define emit_sbb_m64bd_r64(e, base, disp, sreg) emit_sbb_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
2977		#define emit_sbb_m64isd_r64(e, index, scale, disp, sreg) emit_sbb_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
2978
2979
2980		/*------------------------------------------------------------------
2981		emit_and_r64_*
2982		------------------------------------------------------------------*/
2983
2984		#define emit_and_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 4, dreg, imm)
2985		#define emit_and_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 4, base, index, scale, disp, imm)
2986		#define emit_and_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 4, dreg, sreg)
2987		#define emit_and_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 4, dreg, base, index, scale, disp)
2988		#define emit_and_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 4, base, index, scale, disp, sreg)
2989
2990		#define emit_and_m64abs_imm(e, addr, imm) emit_and_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
2991		#define emit_and_m64bd_imm(e, base, disp, imm) emit_and_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
2992		#define emit_and_m64isd_imm(e, index, scale, disp, imm) emit_and_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
2993
2994		#define emit_and_r64_m64abs(e, dreg, addr) emit_and_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
2995		#define emit_and_r64_m64bd(e, dreg, base, disp) emit_and_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
2996		#define emit_and_r64_m64isd(e, dreg, index, scale, disp) emit_and_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
2997
2998		#define emit_and_m64abs_r64(e, addr, sreg) emit_and_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
2999		#define emit_and_m64bd_r64(e, base, disp, sreg) emit_and_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
3000		#define emit_and_m64isd_r64(e, index, scale, disp, sreg) emit_and_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
3001
3002
3003		/*------------------------------------------------------------------
3004		emit_sub_r64_*
3005		------------------------------------------------------------------*/
3006
3007		#define emit_sub_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 5, dreg, imm)
3008		#define emit_sub_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 5, base, index, scale, disp, imm)
3009		#define emit_sub_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 5, dreg, sreg)
3010		#define emit_sub_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 5, dreg, base, index, scale, disp)
3011		#define emit_sub_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 5, base, index, scale, disp, sreg)
3012
3013		#define emit_sub_m64abs_imm(e, addr, imm) emit_sub_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3014		#define emit_sub_m64bd_imm(e, base, disp, imm) emit_sub_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3015		#define emit_sub_m64isd_imm(e, index, scale, disp, imm) emit_sub_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3016
3017		#define emit_sub_r64_m64abs(e, dreg, addr) emit_sub_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
3018		#define emit_sub_r64_m64bd(e, dreg, base, disp) emit_sub_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
3019		#define emit_sub_r64_m64isd(e, dreg, index, scale, disp) emit_sub_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
3020
3021		#define emit_sub_m64abs_r64(e, addr, sreg) emit_sub_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
3022		#define emit_sub_m64bd_r64(e, base, disp, sreg) emit_sub_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
3023		#define emit_sub_m64isd_r64(e, index, scale, disp, sreg) emit_sub_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
3024
3025
3026		/*------------------------------------------------------------------
3027		emit_xor_r64_*
3028		------------------------------------------------------------------*/
3029
3030		#define emit_xor_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 6, dreg, imm)
3031		#define emit_xor_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 6, base, index, scale, disp, imm)
3032		#define emit_xor_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 6, dreg, sreg)
3033		#define emit_xor_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 6, dreg, base, index, scale, disp)
3034		#define emit_xor_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 6, base, index, scale, disp, sreg)
3035
3036		#define emit_xor_m64abs_imm(e, addr, imm) emit_xor_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3037		#define emit_xor_m64bd_imm(e, base, disp, imm) emit_xor_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3038		#define emit_xor_m64isd_imm(e, index, scale, disp, imm) emit_xor_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3039
3040		#define emit_xor_r64_m64abs(e, dreg, addr) emit_xor_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
3041		#define emit_xor_r64_m64bd(e, dreg, base, disp) emit_xor_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
3042		#define emit_xor_r64_m64isd(e, dreg, index, scale, disp) emit_xor_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
3043
3044		#define emit_xor_m64abs_r64(e, addr, sreg) emit_xor_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
3045		#define emit_xor_m64bd_r64(e, base, disp, sreg) emit_xor_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
3046		#define emit_xor_m64isd_r64(e, index, scale, disp, sreg) emit_xor_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
3047
3048
3049		/*------------------------------------------------------------------
3050		emit_cmp_r64_*
3051		------------------------------------------------------------------*/
3052
3053		#define emit_cmp_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 7, dreg, imm)
3054		#define emit_cmp_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 7, base, index, scale, disp, imm)
3055		#define emit_cmp_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 7, dreg, sreg)
3056		#define emit_cmp_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 7, dreg, base, index, scale, disp)
3057		#define emit_cmp_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 7, base, index, scale, disp, sreg)
3058
3059		#define emit_cmp_m64abs_imm(e, addr, imm) emit_cmp_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3060		#define emit_cmp_m64bd_imm(e, base, disp, imm) emit_cmp_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3061		#define emit_cmp_m64isd_imm(e, index, scale, disp, imm) emit_cmp_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3062
3063		#define emit_cmp_r64_m64abs(e, dreg, addr) emit_cmp_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
3064		#define emit_cmp_r64_m64bd(e, dreg, base, disp) emit_cmp_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
3065		#define emit_cmp_r64_m64isd(e, dreg, index, scale, disp) emit_cmp_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
3066
3067		#define emit_cmp_m64abs_r64(e, addr, sreg) emit_cmp_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
3068		#define emit_cmp_m64bd_r64(e, base, disp, sreg) emit_cmp_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
3069		#define emit_cmp_m64isd_r64(e, index, scale, disp, sreg) emit_cmp_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
3070
3071		#endif
3072
3073
3074
3075		/***************************************************************************
3076		8-BIT SHIFT EMITTERS
3077		***************************************************************************/
3078
3079		/*
3080		Note that the following code relies on this:
3081
3082		/0 = ROL
3083		/1 = ROR
3084		/2 = RCL
3085		/3 = RCR
3086		/4 = SHL
3087		/5 = SHR
3088		/7 = SAR
3089		*/
3090
3091		/*------------------------------------------------------------------
3092		emit_shift_r8_*
3093		------------------------------------------------------------------*/
3094
3095		INLINE void emit_shift_r8_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
3096		{
3097		if (imm == 1)
3098		emit_op_modrm_reg(emitptr, OP_G2_Eb_1, OP_32BIT, opindex, dreg);
3099		else
	1434	if ((INT8)imm == (INT32)imm)
3100	1435	{
3101		emit_op_modrm_reg(emitptr, ~~OP_G2_Eb_Ib~~, ~~OP_32BIT,~~ opindex, dreg);
	1436	emit_op_modrm_mem(emitptr, op8, opsize, reg, MEMPARAMS);
3102	1437	emit_byte(emitptr, imm);
3103	1438	}
3104		}
3105
3106		INLINE void emit_shift_m8bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
3107		{
3108		if (imm == 1)
3109		emit_op_modrm_mem(emitptr, OP_G2_Eb_1, OP_32BIT, opindex, base, index, scale, disp);
3110	1439	else
3111	1440	{
3112		emit_op_modrm_mem(emitptr, OP_G2_Eb_Ib, OP_32BIT, opindex, base, index, scale, disp);
3113		emit_byte(emitptr, imm);
	1441	emit_op_modrm_mem(emitptr, op32, opsize, reg, MEMPARAMS);
	1442	emit_dword(emitptr, imm);
3114	1443	}
3115	1444	}
3116	1445
3117		INLINE void emit_shift_r8_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
3118		{
3119		emit_op_modrm_reg(emitptr, OP_G2_Eb_CL, OP_32BIT, opindex, dreg);
3120		}
3121	1446
3122		INLINE void emit_shift_m8bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
3123		{
3124		emit_op_modrm_mem(emitptr, OP_G2_Eb_CL, OP_32BIT, opindex, base, index, scale, disp);
3125		}
3126	1447
3127
3128		/*------------------------------------------------------------------
3129		emit_rol_r8_*
3130		------------------------------------------------------------------*/
3131
3132		#define emit_rol_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 0, dreg, imm)
3133		#define emit_rol_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 0, base, index, scale, disp, imm)
3134		#define emit_rol_r8_cl(e, dreg) emit_shift_r8_cl(e, 0, dreg)
3135		#define emit_rol_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 0, base, index, scale, disp)
3136
3137		#define emit_rol_m8abs_imm(e, addr, imm) emit_rol_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3138		#define emit_rol_m8bd_imm(e, base, disp, imm) emit_rol_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3139		#define emit_rol_m8isd_imm(e, index, scale, disp, imm) emit_rol_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3140
3141		#define emit_rol_m8abs_cl(e, addr) emit_rol_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3142		#define emit_rol_m8bd_cl(e, base, disp) emit_rol_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
3143		#define emit_rol_m8isd_cl(e, index, scale, disp) emit_rol_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
3144
3145
3146		/*------------------------------------------------------------------
3147		emit_ror_r8_*
3148		------------------------------------------------------------------*/
3149
3150		#define emit_ror_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 1, dreg, imm)
3151		#define emit_ror_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 1, base, index, scale, disp, imm)
3152		#define emit_ror_r8_cl(e, dreg) emit_shift_r8_cl(e, 1, dreg)
3153		#define emit_ror_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 1, base, index, scale, disp)
3154
3155		#define emit_ror_m8abs_imm(e, addr, imm) emit_ror_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3156		#define emit_ror_m8bd_imm(e, base, disp, imm) emit_ror_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3157		#define emit_ror_m8isd_imm(e, index, scale, disp, imm) emit_ror_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3158
3159		#define emit_ror_m8abs_cl(e, addr) emit_ror_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3160		#define emit_ror_m8bd_cl(e, base, disp) emit_ror_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
3161		#define emit_ror_m8isd_cl(e, index, scale, disp) emit_ror_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
3162
3163
3164		/*------------------------------------------------------------------
3165		emit_rcl_r8_*
3166		------------------------------------------------------------------*/
3167
3168		#define emit_rcl_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 2, dreg, imm)
3169		#define emit_rcl_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 2, base, index, scale, disp, imm)
3170		#define emit_rcl_r8_cl(e, dreg) emit_shift_r8_cl(e, 2, dreg)
3171		#define emit_rcl_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 2, base, index, scale, disp)
3172
3173		#define emit_rcl_m8abs_imm(e, addr, imm) emit_rcl_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3174		#define emit_rcl_m8bd_imm(e, base, disp, imm) emit_rcl_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3175		#define emit_rcl_m8isd_imm(e, index, scale, disp, imm) emit_rcl_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3176
3177		#define emit_rcl_m8abs_cl(e, addr) emit_rcl_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3178		#define emit_rcl_m8bd_cl(e, base, disp) emit_rcl_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
3179		#define emit_rcl_m8isd_cl(e, index, scale, disp) emit_rcl_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
3180
3181
3182		/*------------------------------------------------------------------
3183		emit_rcr_r8_*
3184		------------------------------------------------------------------*/
3185
3186		#define emit_rcr_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 3, dreg, imm)
3187		#define emit_rcr_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 3, base, index, scale, disp, imm)
3188		#define emit_rcr_r8_cl(e, dreg) emit_shift_r8_cl(e, 3, dreg)
3189		#define emit_rcr_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 3, base, index, scale, disp)
3190
3191		#define emit_rcr_m8abs_imm(e, addr, imm) emit_rcr_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3192		#define emit_rcr_m8bd_imm(e, base, disp, imm) emit_rcr_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3193		#define emit_rcr_m8isd_imm(e, index, scale, disp, imm) emit_rcr_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3194
3195		#define emit_rcr_m8abs_cl(e, addr) emit_rcr_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3196		#define emit_rcr_m8bd_cl(e, base, disp) emit_rcr_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
3197		#define emit_rcr_m8isd_cl(e, index, scale, disp) emit_rcr_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
3198
3199
3200		/*------------------------------------------------------------------
3201		emit_shl_r8_*
3202		------------------------------------------------------------------*/
3203
3204		#define emit_shl_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 4, dreg, imm)
3205		#define emit_shl_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 4, base, index, scale, disp, imm)
3206		#define emit_shl_r8_cl(e, dreg) emit_shift_r8_cl(e, 4, dreg)
3207		#define emit_shl_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 4, base, index, scale, disp)
3208
3209		#define emit_shl_m8abs_imm(e, addr, imm) emit_shl_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3210		#define emit_shl_m8bd_imm(e, base, disp, imm) emit_shl_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3211		#define emit_shl_m8isd_imm(e, index, scale, disp, imm) emit_shl_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3212
3213		#define emit_shl_m8abs_cl(e, addr) emit_shl_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3214		#define emit_shl_m8bd_cl(e, base, disp) emit_shl_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
3215		#define emit_shl_m8isd_cl(e, index, scale, disp) emit_shl_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
3216
3217
3218		/*------------------------------------------------------------------
3219		emit_shr_r8_*
3220		------------------------------------------------------------------*/
3221
3222		#define emit_shr_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 5, dreg, imm)
3223		#define emit_shr_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 5, base, index, scale, disp, imm)
3224		#define emit_shr_r8_cl(e, dreg) emit_shift_r8_cl(e, 5, dreg)
3225		#define emit_shr_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 5, base, index, scale, disp)
3226
3227		#define emit_shr_m8abs_imm(e, addr, imm) emit_shr_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3228		#define emit_shr_m8bd_imm(e, base, disp, imm) emit_shr_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3229		#define emit_shr_m8isd_imm(e, index, scale, disp, imm) emit_shr_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3230
3231		#define emit_shr_m8abs_cl(e, addr) emit_shr_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3232		#define emit_shr_m8bd_cl(e, base, disp) emit_shr_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
3233		#define emit_shr_m8isd_cl(e, index, scale, disp) emit_shr_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
3234
3235
3236		/*------------------------------------------------------------------
3237		emit_sar_r8_*
3238		------------------------------------------------------------------*/
3239
3240		#define emit_sar_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 7, dreg, imm)
3241		#define emit_sar_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 7, base, index, scale, disp, imm)
3242		#define emit_sar_r8_cl(e, dreg) emit_shift_r8_cl(e, 7, dreg)
3243		#define emit_sar_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 7, base, index, scale, disp)
3244
3245		#define emit_sar_m8abs_imm(e, addr, imm) emit_sar_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3246		#define emit_sar_m8bd_imm(e, base, disp, imm) emit_sar_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3247		#define emit_sar_m8isd_imm(e, index, scale, disp, imm) emit_sar_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3248
3249		#define emit_sar_m8abs_cl(e, addr) emit_sar_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3250		#define emit_sar_m8bd_cl(e, base, disp) emit_sar_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
3251		#define emit_sar_m8isd_cl(e, index, scale, disp) emit_sar_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
3252
3253
3254
3255	1448	/***************************************************************************
3256		~~16-BIT~~ SHIFT EMITTERS
	1449	SIMPLE OPCODE EMITTERS
3257	1450	***************************************************************************/
3258	1451
3259		/*
3260		Note that the following code relies on this:
	1452	INLINE void emit_nop(x86code **emitptr) { emit_op_simple(emitptr, OP_NOP, OP_32BIT); }
	1453	INLINE void emit_int_3(x86code **emitptr) { emit_op_simple(emitptr, OP_INT_3, OP_32BIT); }
	1454	INLINE void emit_ret(x86code **emitptr) { emit_op_simple(emitptr, OP_RETN, OP_32BIT); }
	1455	INLINE void emit_cdq(x86code **emitptr) { emit_op_simple(emitptr, OP_CDQ, OP_32BIT); }
	1456	INLINE void emit_cmc(x86code **emitptr) { emit_op_simple(emitptr, OP_CMC, OP_32BIT); }
3261	1457
3262		/0 = ROL
3263		/1 = ROR
3264		/2 = RCL
3265		/3 = RCR
3266		/4 = SHL
3267		/5 = SHR
3268		/7 = SAR
3269		*/
3270
3271		/*------------------------------------------------------------------
3272		emit_shift_r16_*
3273		------------------------------------------------------------------*/
3274
3275		INLINE void emit_shift_r16_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
3276		{
3277		emit_byte(emitptr, PREFIX_OPSIZE);
3278		if (imm == 1)
3279		emit_op_modrm_reg(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, dreg);
3280		else
3281		{
3282		emit_op_modrm_reg(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, dreg);
3283		emit_byte(emitptr, imm);
3284		}
3285		}
3286
3287		INLINE void emit_shift_m16bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
3288		{
3289		emit_byte(emitptr, PREFIX_OPSIZE);
3290		if (imm == 1)
3291		emit_op_modrm_mem(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, base, index, scale, disp);
3292		else
3293		{
3294		emit_op_modrm_mem(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
3295		emit_byte(emitptr, imm);
3296		}
3297		}
3298
3299		INLINE void emit_shift_r16_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
3300		{
3301		emit_byte(emitptr, PREFIX_OPSIZE);
3302		emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, dreg);
3303		}
3304
3305		INLINE void emit_shift_m16bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
3306		{
3307		emit_byte(emitptr, PREFIX_OPSIZE);
3308		emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, base, index, scale, disp);
3309		}
3310
3311
3312		/*------------------------------------------------------------------
3313		emit_rol_r16_*
3314		------------------------------------------------------------------*/
3315
3316		#define emit_rol_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 0, dreg, imm)
3317		#define emit_rol_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 0, base, index, scale, disp, imm)
3318		#define emit_rol_r16_cl(e, dreg) emit_shift_r16_cl(e, 0, dreg)
3319		#define emit_rol_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 0, base, index, scale, disp)
3320
3321		#define emit_rol_m16abs_imm(e, addr, imm) emit_rol_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3322		#define emit_rol_m16bd_imm(e, base, disp, imm) emit_rol_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3323		#define emit_rol_m16isd_imm(e, index, scale, disp, imm) emit_rol_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3324
3325		#define emit_rol_m16abs_cl(e, addr) emit_rol_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3326		#define emit_rol_m16bd_cl(e, base, disp) emit_rol_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
3327		#define emit_rol_m16isd_cl(e, index, scale, disp) emit_rol_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
3328
3329
3330		/*------------------------------------------------------------------
3331		emit_ror_r16_*
3332		------------------------------------------------------------------*/
3333
3334		#define emit_ror_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 1, dreg, imm)
3335		#define emit_ror_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 1, base, index, scale, disp, imm)
3336		#define emit_ror_r16_cl(e, dreg) emit_shift_r16_cl(e, 1, dreg)
3337		#define emit_ror_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 1, base, index, scale, disp)
3338
3339		#define emit_ror_m16abs_imm(e, addr, imm) emit_ror_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3340		#define emit_ror_m16bd_imm(e, base, disp, imm) emit_ror_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3341		#define emit_ror_m16isd_imm(e, index, scale, disp, imm) emit_ror_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3342
3343		#define emit_ror_m16abs_cl(e, addr) emit_ror_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3344		#define emit_ror_m16bd_cl(e, base, disp) emit_ror_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
3345		#define emit_ror_m16isd_cl(e, index, scale, disp) emit_ror_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
3346
3347
3348		/*------------------------------------------------------------------
3349		emit_rcl_r16_*
3350		------------------------------------------------------------------*/
3351
3352		#define emit_rcl_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 2, dreg, imm)
3353		#define emit_rcl_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 2, base, index, scale, disp, imm)
3354		#define emit_rcl_r16_cl(e, dreg) emit_shift_r16_cl(e, 2, dreg)
3355		#define emit_rcl_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 2, base, index, scale, disp)
3356
3357		#define emit_rcl_m16abs_imm(e, addr, imm) emit_rcl_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3358		#define emit_rcl_m16bd_imm(e, base, disp, imm) emit_rcl_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3359		#define emit_rcl_m16isd_imm(e, index, scale, disp, imm) emit_rcl_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3360
3361		#define emit_rcl_m16abs_cl(e, addr) emit_rcl_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3362		#define emit_rcl_m16bd_cl(e, base, disp) emit_rcl_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
3363		#define emit_rcl_m16isd_cl(e, index, scale, disp) emit_rcl_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
3364
3365
3366		/*------------------------------------------------------------------
3367		emit_rcr_r16_*
3368		------------------------------------------------------------------*/
3369
3370		#define emit_rcr_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 3, dreg, imm)
3371		#define emit_rcr_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 31, base, index, scale, disp, imm)
3372		#define emit_rcr_r16_cl(e, dreg) emit_shift_r16_cl(e, 3, dreg)
3373		#define emit_rcr_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 3, base, index, scale, disp)
3374
3375		#define emit_rcr_m16abs_imm(e, addr, imm) emit_rcr_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3376		#define emit_rcr_m16bd_imm(e, base, disp, imm) emit_rcr_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3377		#define emit_rcr_m16isd_imm(e, index, scale, disp, imm) emit_rcr_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3378
3379		#define emit_rcr_m16abs_cl(e, addr) emit_rcr_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3380		#define emit_rcr_m16bd_cl(e, base, disp) emit_rcr_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
3381		#define emit_rcr_m16isd_cl(e, index, scale, disp) emit_rcr_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
3382
3383
3384		/*------------------------------------------------------------------
3385		emit_shl_r16_*
3386		------------------------------------------------------------------*/
3387
3388		#define emit_shl_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 4, dreg, imm)
3389		#define emit_shl_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 4, base, index, scale, disp, imm)
3390		#define emit_shl_r16_cl(e, dreg) emit_shift_r16_cl(e, 4, dreg)
3391		#define emit_shl_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 4, base, index, scale, disp)
3392
3393		#define emit_shl_m16abs_imm(e, addr, imm) emit_shl_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3394		#define emit_shl_m16bd_imm(e, base, disp, imm) emit_shl_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3395		#define emit_shl_m16isd_imm(e, index, scale, disp, imm) emit_shl_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3396
3397		#define emit_shl_m16abs_cl(e, addr) emit_shl_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3398		#define emit_shl_m16bd_cl(e, base, disp) emit_shl_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
3399		#define emit_shl_m16isd_cl(e, index, scale, disp) emit_shl_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
3400
3401
3402		/*------------------------------------------------------------------
3403		emit_shr_r16_*
3404		------------------------------------------------------------------*/
3405
3406		#define emit_shr_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 5, dreg, imm)
3407		#define emit_shr_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 5, base, index, scale, disp, imm)
3408		#define emit_shr_r16_cl(e, dreg) emit_shift_r16_cl(e, 5, dreg)
3409		#define emit_shr_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 5, base, index, scale, disp)
3410
3411		#define emit_shr_m16abs_imm(e, addr, imm) emit_shr_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3412		#define emit_shr_m16bd_imm(e, base, disp, imm) emit_shr_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3413		#define emit_shr_m16isd_imm(e, index, scale, disp, imm) emit_shr_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3414
3415		#define emit_shr_m16abs_cl(e, addr) emit_shr_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3416		#define emit_shr_m16bd_cl(e, base, disp) emit_shr_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
3417		#define emit_shr_m16isd_cl(e, index, scale, disp) emit_shr_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
3418
3419
3420		/*------------------------------------------------------------------
3421		emit_sar_r16_*
3422		------------------------------------------------------------------*/
3423
3424		#define emit_sar_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 7, dreg, imm)
3425		#define emit_sar_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 7, base, index, scale, disp, imm)
3426		#define emit_sar_r16_cl(e, dreg) emit_shift_r16_cl(e, 7, dreg)
3427		#define emit_sar_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 7, base, index, scale, disp)
3428
3429		#define emit_sar_m16abs_imm(e, addr, imm) emit_sar_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3430		#define emit_sar_m16bd_imm(e, base, disp, imm) emit_sar_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3431		#define emit_sar_m16isd_imm(e, index, scale, disp, imm) emit_sar_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3432
3433		#define emit_sar_m16abs_cl(e, addr) emit_sar_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3434		#define emit_sar_m16bd_cl(e, base, disp) emit_sar_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
3435		#define emit_sar_m16isd_cl(e, index, scale, disp) emit_sar_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
3436
3437
3438
3439		/***************************************************************************
3440		32-BIT SHIFT EMITTERS
3441		***************************************************************************/
3442
3443		/*
3444		Note that the following code relies on this:
3445
3446		/0 = ROL
3447		/1 = ROR
3448		/2 = RCL
3449		/3 = RCR
3450		/4 = SHL
3451		/5 = SHR
3452		/7 = SAR
3453		*/
3454
3455		/*------------------------------------------------------------------
3456		emit_shift_r32_*
3457		------------------------------------------------------------------*/
3458
3459		INLINE void emit_shift_r32_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
3460		{
3461		if (imm == 1)
3462		emit_op_modrm_reg(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, dreg);
3463		else
3464		{
3465		emit_op_modrm_reg(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, dreg);
3466		emit_byte(emitptr, imm);
3467		}
3468		}
3469
3470		INLINE void emit_shift_m32bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
3471		{
3472		if (imm == 1)
3473		emit_op_modrm_mem(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, base, index, scale, disp);
3474		else
3475		{
3476		emit_op_modrm_mem(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
3477		emit_byte(emitptr, imm);
3478		}
3479		}
3480
3481		INLINE void emit_shift_r32_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
3482		{
3483		emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, dreg);
3484		}
3485
3486		INLINE void emit_shift_m32bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
3487		{
3488		emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, base, index, scale, disp);
3489		}
3490
3491
3492		/*------------------------------------------------------------------
3493		emit_rol_r32_*
3494		------------------------------------------------------------------*/
3495
3496		#define emit_rol_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 0, dreg, imm)
3497		#define emit_rol_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 0, base, index, scale, disp, imm)
3498		#define emit_rol_r32_cl(e, dreg) emit_shift_r32_cl(e, 0, dreg)
3499		#define emit_rol_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 0, base, index, scale, disp)
3500
3501		#define emit_rol_m32abs_imm(e, addr, imm) emit_rol_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3502		#define emit_rol_m32bd_imm(e, base, disp, imm) emit_rol_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3503		#define emit_rol_m32isd_imm(e, index, scale, disp, imm) emit_rol_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3504
3505		#define emit_rol_m32abs_cl(e, addr) emit_rol_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3506		#define emit_rol_m32bd_cl(e, base, disp) emit_rol_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
3507		#define emit_rol_m32isd_cl(e, index, scale, disp) emit_rol_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
3508
3509
3510		/*------------------------------------------------------------------
3511		emit_ror_r32_*
3512		------------------------------------------------------------------*/
3513
3514		#define emit_ror_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 1, dreg, imm)
3515		#define emit_ror_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 1, base, index, scale, disp, imm)
3516		#define emit_ror_r32_cl(e, dreg) emit_shift_r32_cl(e, 1, dreg)
3517		#define emit_ror_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 1, base, index, scale, disp)
3518
3519		#define emit_ror_m32abs_imm(e, addr, imm) emit_ror_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3520		#define emit_ror_m32bd_imm(e, base, disp, imm) emit_ror_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3521		#define emit_ror_m32isd_imm(e, index, scale, disp, imm) emit_ror_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3522
3523		#define emit_ror_m32abs_cl(e, addr) emit_ror_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3524		#define emit_ror_m32bd_cl(e, base, disp) emit_ror_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
3525		#define emit_ror_m32isd_cl(e, index, scale, disp) emit_ror_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
3526
3527
3528		/*------------------------------------------------------------------
3529		emit_rcl_r32_*
3530		------------------------------------------------------------------*/
3531
3532		#define emit_rcl_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 2, dreg, imm)
3533		#define emit_rcl_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 2, base, index, scale, disp, imm)
3534		#define emit_rcl_r32_cl(e, dreg) emit_shift_r32_cl(e, 2, dreg)
3535		#define emit_rcl_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 2, base, index, scale, disp)
3536
3537		#define emit_rcl_m32abs_imm(e, addr, imm) emit_rcl_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3538		#define emit_rcl_m32bd_imm(e, base, disp, imm) emit_rcl_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3539		#define emit_rcl_m32isd_imm(e, index, scale, disp, imm) emit_rcl_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3540
3541		#define emit_rcl_m32abs_cl(e, addr) emit_rcl_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3542		#define emit_rcl_m32bd_cl(e, base, disp) emit_rcl_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
3543		#define emit_rcl_m32isd_cl(e, index, scale, disp) emit_rcl_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
3544
3545
3546		/*------------------------------------------------------------------
3547		emit_rcr_r32_*
3548		------------------------------------------------------------------*/
3549
3550		#define emit_rcr_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 3, dreg, imm)
3551		#define emit_rcr_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 3, base, index, scale, disp, imm)
3552		#define emit_rcr_r32_cl(e, dreg) emit_shift_r32_cl(e, 3, dreg)
3553		#define emit_rcr_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 3, base, index, scale, disp)
3554
3555		#define emit_rcr_m32abs_imm(e, addr, imm) emit_rcr_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3556		#define emit_rcr_m32bd_imm(e, base, disp, imm) emit_rcr_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3557		#define emit_rcr_m32isd_imm(e, index, scale, disp, imm) emit_rcr_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3558
3559		#define emit_rcr_m32abs_cl(e, addr) emit_rcr_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3560		#define emit_rcr_m32bd_cl(e, base, disp) emit_rcr_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
3561		#define emit_rcr_m32isd_cl(e, index, scale, disp) emit_rcr_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
3562
3563
3564		/*------------------------------------------------------------------
3565		emit_shl_r32_*
3566		------------------------------------------------------------------*/
3567
3568		#define emit_shl_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 4, dreg, imm)
3569		#define emit_shl_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 4, base, index, scale, disp, imm)
3570		#define emit_shl_r32_cl(e, dreg) emit_shift_r32_cl(e, 4, dreg)
3571		#define emit_shl_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 4, base, index, scale, disp)
3572
3573		#define emit_shl_m32abs_imm(e, addr, imm) emit_shl_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3574		#define emit_shl_m32bd_imm(e, base, disp, imm) emit_shl_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3575		#define emit_shl_m32isd_imm(e, index, scale, disp, imm) emit_shl_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3576
3577		#define emit_shl_m32abs_cl(e, addr) emit_shl_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3578		#define emit_shl_m32bd_cl(e, base, disp) emit_shl_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
3579		#define emit_shl_m32isd_cl(e, index, scale, disp) emit_shl_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
3580
3581
3582		/*------------------------------------------------------------------
3583		emit_shr_r32_*
3584		------------------------------------------------------------------*/
3585
3586		#define emit_shr_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 5, dreg, imm)
3587		#define emit_shr_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 5, base, index, scale, disp, imm)
3588		#define emit_shr_r32_cl(e, dreg) emit_shift_r32_cl(e, 5, dreg)
3589		#define emit_shr_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 5, base, index, scale, disp)
3590
3591		#define emit_shr_m32abs_imm(e, addr, imm) emit_shr_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3592		#define emit_shr_m32bd_imm(e, base, disp, imm) emit_shr_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3593		#define emit_shr_m32isd_imm(e, index, scale, disp, imm) emit_shr_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3594
3595		#define emit_shr_m32abs_cl(e, addr) emit_shr_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3596		#define emit_shr_m32bd_cl(e, base, disp) emit_shr_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
3597		#define emit_shr_m32isd_cl(e, index, scale, disp) emit_shr_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
3598
3599
3600		/*------------------------------------------------------------------
3601		emit_sar_r32_*
3602		------------------------------------------------------------------*/
3603
3604		#define emit_sar_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 7, dreg, imm)
3605		#define emit_sar_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 7, base, index, scale, disp, imm)
3606		#define emit_sar_r32_cl(e, dreg) emit_shift_r32_cl(e, 7, dreg)
3607		#define emit_sar_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 7, base, index, scale, disp)
3608
3609		#define emit_sar_m32abs_imm(e, addr, imm) emit_sar_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3610		#define emit_sar_m32bd_imm(e, base, disp, imm) emit_sar_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3611		#define emit_sar_m32isd_imm(e, index, scale, disp, imm) emit_sar_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3612
3613		#define emit_sar_m32abs_cl(e, addr) emit_sar_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3614		#define emit_sar_m32bd_cl(e, base, disp) emit_sar_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
3615		#define emit_sar_m32isd_cl(e, index, scale, disp) emit_sar_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
3616
3617
3618
3619		/***************************************************************************
3620		64-BIT SHIFT EMITTERS
3621		***************************************************************************/
3622
3623		#ifdef PTR64
3624		/*
3625		Note that the following code relies on this:
3626
3627		/0 = ROL
3628		/1 = ROR
3629		/2 = RCL
3630		/3 = RCR
3631		/4 = SHL
3632		/5 = SHR
3633		/7 = SAR
3634		*/
3635
3636		/*------------------------------------------------------------------
3637		emit_shift_r64_*
3638		------------------------------------------------------------------*/
3639
3640		INLINE void emit_shift_r64_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
3641		{
3642		if (imm == 1)
3643		emit_op_modrm_reg(emitptr, OP_G2_Ev_1, OP_64BIT, opindex, dreg);
3644		else
3645		{
3646		emit_op_modrm_reg(emitptr, OP_G2_Ev_Ib, OP_64BIT, opindex, dreg);
3647		emit_byte(emitptr, imm);
3648		}
3649		}
3650
3651		INLINE void emit_shift_m64bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
3652		{
3653		if (imm == 1)
3654		emit_op_modrm_mem(emitptr, OP_G2_Ev_1, OP_64BIT, opindex, base, index, scale, disp);
3655		else
3656		{
3657		emit_op_modrm_mem(emitptr, OP_G2_Ev_Ib, OP_64BIT, opindex, base, index, scale, disp);
3658		emit_byte(emitptr, imm);
3659		}
3660		}
3661
3662		INLINE void emit_shift_r64_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
3663		{
3664		emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_64BIT, opindex, dreg);
3665		}
3666
3667		INLINE void emit_shift_m64bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
3668		{
3669		emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_64BIT, opindex, base, index, scale, disp);
3670		}
3671
3672
3673		/*------------------------------------------------------------------
3674		emit_rol_r64_*
3675		------------------------------------------------------------------*/
3676
3677		#define emit_rol_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 0, dreg, imm)
3678		#define emit_rol_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 0, base, index, scale, disp, imm)
3679		#define emit_rol_r64_cl(e, dreg) emit_shift_r64_cl(e, 0, dreg)
3680		#define emit_rol_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 0, base, index, scale, disp)
3681
3682		#define emit_rol_m64abs_imm(e, addr, imm) emit_rol_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3683		#define emit_rol_m64bd_imm(e, base, disp, imm) emit_rol_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3684		#define emit_rol_m64isd_imm(e, index, scale, disp, imm) emit_rol_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3685
3686		#define emit_rol_m64abs_cl(e, addr) emit_rol_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3687		#define emit_rol_m64bd_cl(e, base, disp) emit_rol_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
3688		#define emit_rol_m64isd_cl(e, index, scale, disp) emit_rol_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
3689
3690
3691		/*------------------------------------------------------------------
3692		emit_ror_r64_*
3693		------------------------------------------------------------------*/
3694
3695		#define emit_ror_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 1, dreg, imm)
3696		#define emit_ror_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 1, base, index, scale, disp, imm)
3697		#define emit_ror_r64_cl(e, dreg) emit_shift_r64_cl(e, 1, dreg)
3698		#define emit_ror_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 1, base, index, scale, disp)
3699
3700		#define emit_ror_m64abs_imm(e, addr, imm) emit_ror_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3701		#define emit_ror_m64bd_imm(e, base, disp, imm) emit_ror_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3702		#define emit_ror_m64isd_imm(e, index, scale, disp, imm) emit_ror_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3703
3704		#define emit_ror_m64abs_cl(e, addr) emit_ror_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3705		#define emit_ror_m64bd_cl(e, base, disp) emit_ror_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
3706		#define emit_ror_m64isd_cl(e, index, scale, disp) emit_ror_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
3707
3708
3709		/*------------------------------------------------------------------
3710		emit_rcl_r64_*
3711		------------------------------------------------------------------*/
3712
3713		#define emit_rcl_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 2, dreg, imm)
3714		#define emit_rcl_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 2, base, index, scale, disp, imm)
3715		#define emit_rcl_r64_cl(e, dreg) emit_shift_r64_cl(e, 2, dreg)
3716		#define emit_rcl_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 2, base, index, scale, disp)
3717
3718		#define emit_rcl_m64abs_imm(e, addr, imm) emit_rcl_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3719		#define emit_rcl_m64bd_imm(e, base, disp, imm) emit_rcl_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3720		#define emit_rcl_m64isd_imm(e, index, scale, disp, imm) emit_rcl_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3721
3722		#define emit_rcl_m64abs_cl(e, addr) emit_rcl_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3723		#define emit_rcl_m64bd_cl(e, base, disp) emit_rcl_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
3724		#define emit_rcl_m64isd_cl(e, index, scale, disp) emit_rcl_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
3725
3726
3727		/*------------------------------------------------------------------
3728		emit_rcr_r64_*
3729		------------------------------------------------------------------*/
3730
3731		#define emit_rcr_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 3, dreg, imm)
3732		#define emit_rcr_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 3, base, index, scale, disp, imm)
3733		#define emit_rcr_r64_cl(e, dreg) emit_shift_r64_cl(e, 3, dreg)
3734		#define emit_rcr_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 3, base, index, scale, disp)
3735
3736		#define emit_rcr_m64abs_imm(e, addr, imm) emit_rcr_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3737		#define emit_rcr_m64bd_imm(e, base, disp, imm) emit_rcr_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3738		#define emit_rcr_m64isd_imm(e, index, scale, disp, imm) emit_rcr_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3739
3740		#define emit_rcr_m64abs_cl(e, addr) emit_rcr_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3741		#define emit_rcr_m64bd_cl(e, base, disp) emit_rcr_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
3742		#define emit_rcr_m64isd_cl(e, index, scale, disp) emit_rcr_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
3743
3744
3745		/*------------------------------------------------------------------
3746		emit_shl_r64_*
3747		------------------------------------------------------------------*/
3748
3749		#define emit_shl_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 4, dreg, imm)
3750		#define emit_shl_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 4, base, index, scale, disp, imm)
3751		#define emit_shl_r64_cl(e, dreg) emit_shift_r64_cl(e, 4, dreg)
3752		#define emit_shl_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 4, base, index, scale, disp)
3753
3754		#define emit_shl_m64abs_imm(e, addr, imm) emit_shl_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3755		#define emit_shl_m64bd_imm(e, base, disp, imm) emit_shl_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3756		#define emit_shl_m64isd_imm(e, index, scale, disp, imm) emit_shl_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3757
3758		#define emit_shl_m64abs_cl(e, addr) emit_shl_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3759		#define emit_shl_m64bd_cl(e, base, disp) emit_shl_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
3760		#define emit_shl_m64isd_cl(e, index, scale, disp) emit_shl_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
3761
3762
3763		/*------------------------------------------------------------------
3764		emit_shr_r64_*
3765		------------------------------------------------------------------*/
3766
3767		#define emit_shr_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 5, dreg, imm)
3768		#define emit_shr_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 5, base, index, scale, disp, imm)
3769		#define emit_shr_r64_cl(e, dreg) emit_shift_r64_cl(e, 5, dreg)
3770		#define emit_shr_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 5, base, index, scale, disp)
3771
3772		#define emit_shr_m64abs_imm(e, addr, imm) emit_shr_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3773		#define emit_shr_m64bd_imm(e, base, disp, imm) emit_shr_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3774		#define emit_shr_m64isd_imm(e, index, scale, disp, imm) emit_shr_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3775
3776		#define emit_shr_m64abs_cl(e, addr) emit_shr_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3777		#define emit_shr_m64bd_cl(e, base, disp) emit_shr_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
3778		#define emit_shr_m64isd_cl(e, index, scale, disp) emit_shr_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
3779
3780
3781		/*------------------------------------------------------------------
3782		emit_sar_r64_*
3783		------------------------------------------------------------------*/
3784
3785		#define emit_sar_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 7, dreg, imm)
3786		#define emit_sar_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 7, base, index, scale, disp, imm)
3787		#define emit_sar_r64_cl(e, dreg) emit_shift_r64_cl(e, 7, dreg)
3788		#define emit_sar_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 7, base, index, scale, disp)
3789
3790		#define emit_sar_m64abs_imm(e, addr, imm) emit_sar_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
3791		#define emit_sar_m64bd_imm(e, base, disp, imm) emit_sar_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
3792		#define emit_sar_m64isd_imm(e, index, scale, disp, imm) emit_sar_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
3793
3794		#define emit_sar_m64abs_cl(e, addr) emit_sar_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3795		#define emit_sar_m64bd_cl(e, base, disp) emit_sar_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
3796		#define emit_sar_m64isd_cl(e, index, scale, disp) emit_sar_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
3797
3798		#endif
3799
3800
3801
3802		/***************************************************************************
3803		8-BIT GROUP3 EMITTERS
3804		***************************************************************************/
3805
3806		/*
3807		Note that the following code relies on this:
3808
3809		/2 = NOT
3810		/3 = NEG
3811		/4 = MUL
3812		/5 = IMUL
3813		/6 = DIV
3814		/7 = IDIV
3815		*/
3816
3817		/*------------------------------------------------------------------
3818		emit_group3_r8_*
3819		------------------------------------------------------------------*/
3820
3821		INLINE void emit_group3_r8(x86code **emitptr, UINT8 opindex, UINT8 dreg)
3822		{
3823		emit_op_modrm_reg(emitptr, OP_G3_Eb, OP_32BIT, opindex, dreg);
3824		}
3825
3826		INLINE void emit_group3_m8bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
3827		{
3828		emit_op_modrm_mem(emitptr, OP_G3_Eb, OP_32BIT, opindex, base, index, scale, disp);
3829		}
3830
3831
3832		/*------------------------------------------------------------------
3833		emit_not_r8_*
3834		------------------------------------------------------------------*/
3835
3836		#define emit_not_r8(e, dreg) emit_group3_r8(e, 2, dreg)
3837		#define emit_not_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 2, base, index, scale, disp)
3838
3839		#define emit_not_m8abs(e, addr) emit_not_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3840		#define emit_not_m8bd(e, base, disp) emit_not_m8bisd(e, (base), REG_NONE, 1, (disp))
3841		#define emit_not_m8isd(e, index, scale, disp) emit_not_m8bisd(e, REG_NONE, (index), (scale), (disp))
3842
3843
3844		/*------------------------------------------------------------------
3845		emit_neg_r8_*
3846		------------------------------------------------------------------*/
3847
3848		#define emit_neg_r8(e, dreg) emit_group3_r8(e, 3, dreg)
3849		#define emit_neg_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 3, base, index, scale, disp)
3850
3851		#define emit_neg_m8abs(e, addr) emit_neg_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3852		#define emit_neg_m8bd(e, base, disp) emit_neg_m8bisd(e, (base), REG_NONE, 1, (disp))
3853		#define emit_neg_m8isd(e, index, scale, disp) emit_neg_m8bisd(e, REG_NONE, (index), (scale), (disp))
3854
3855
3856		/*------------------------------------------------------------------
3857		emit_mul_r8_*
3858		------------------------------------------------------------------*/
3859
3860		#define emit_mul_r8(e, dreg) emit_group3_r8(e, 4, dreg)
3861		#define emit_mul_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 4, base, index, scale, disp)
3862
3863		#define emit_mul_m8abs(e, addr) emit_mul_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3864		#define emit_mul_m8bd(e, base, disp) emit_mul_m8bisd(e, (base), REG_NONE, 1, (disp))
3865		#define emit_mul_m8isd(e, index, scale, disp) emit_mul_m8bisd(e, REG_NONE, (index), (scale), (disp))
3866
3867
3868		/*------------------------------------------------------------------
3869		emit_imul_r8_*
3870		------------------------------------------------------------------*/
3871
3872		#define emit_imul_r8(e, dreg) emit_group3_r8(e, 5, dreg)
3873		#define emit_imul_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 5, base, index, scale, disp)
3874
3875		#define emit_imul_m8abs(e, addr) emit_imul_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3876		#define emit_imul_m8bd(e, base, disp) emit_imul_m8bisd(e, (base), REG_NONE, 1, (disp))
3877		#define emit_imul_m8isd(e, index, scale, disp) emit_imul_m8bisd(e, REG_NONE, (index), (scale), (disp))
3878
3879
3880		/*------------------------------------------------------------------
3881		emit_div_r8_*
3882		------------------------------------------------------------------*/
3883
3884		#define emit_div_r8(e, dreg) emit_group3_r8(e, 6, dreg)
3885		#define emit_div_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 6, base, index, scale, disp)
3886
3887		#define emit_div_m8abs(e, addr) emit_div_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3888		#define emit_div_m8bd(e, base, disp) emit_div_m8bisd(e, (base), REG_NONE, 1, (disp))
3889		#define emit_div_m8isd(e, index, scale, disp) emit_div_m8bisd(e, REG_NONE, (index), (scale), (disp))
3890
3891
3892		/*------------------------------------------------------------------
3893		emit_idiv_r8_*
3894		------------------------------------------------------------------*/
3895
3896		#define emit_idiv_r8(e, dreg) emit_group3_r8(e, 7, dreg)
3897		#define emit_idiv_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 7, base, index, scale, disp)
3898
3899		#define emit_idiv_m8abs(e, addr) emit_idiv_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3900		#define emit_idiv_m8bd(e, base, disp) emit_idiv_m8bisd(e, (base), REG_NONE, 1, (disp))
3901		#define emit_idiv_m8isd(e, index, scale, disp) emit_idiv_m8bisd(e, REG_NONE, (index), (scale), (disp))
3902
3903
3904
3905		/***************************************************************************
3906		16-BIT GROUP3 EMITTERS
3907		***************************************************************************/
3908
3909		/*
3910		Note that the following code relies on this:
3911
3912		/0 = ROL
3913		/1 = ROR
3914		/2 = RCL
3915		/3 = RCR
3916		/4 = SHL
3917		/5 = SHR
3918		/7 = SAR
3919		*/
3920
3921		/*------------------------------------------------------------------
3922		emit_group3_r16_*
3923		------------------------------------------------------------------*/
3924
3925		INLINE void emit_group3_r16(x86code **emitptr, UINT8 opindex, UINT8 dreg)
3926		{
3927		emit_byte(emitptr, PREFIX_OPSIZE);
3928		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, opindex, dreg);
3929		}
3930
3931		INLINE void emit_group3_m16bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
3932		{
3933		emit_byte(emitptr, PREFIX_OPSIZE);
3934		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, opindex, base, index, scale, disp);
3935		}
3936
3937
3938		/*------------------------------------------------------------------
3939		emit_not_r16_*
3940		------------------------------------------------------------------*/
3941
3942		#define emit_not_r16(e, dreg) emit_group3_r16(e, 2, dreg)
3943		#define emit_not_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 2, base, index, scale, disp)
3944
3945		#define emit_not_m16abs(e, addr) emit_not_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3946		#define emit_not_m16bd(e, base, disp) emit_not_m16bisd(e, (base), REG_NONE, 1, (disp))
3947		#define emit_not_m16isd(e, index, scale, disp) emit_not_m16bisd(e, REG_NONE, (index), (scale), (disp))
3948
3949
3950		/*------------------------------------------------------------------
3951		emit_neg_r16_*
3952		------------------------------------------------------------------*/
3953
3954		#define emit_neg_r16(e, dreg) emit_group3_r16(e, 3, dreg)
3955		#define emit_neg_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 3, base, index, scale, disp)
3956
3957		#define emit_neg_m16abs(e, addr) emit_neg_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3958		#define emit_neg_m16bd(e, base, disp) emit_neg_m16bisd(e, (base), REG_NONE, 1, (disp))
3959		#define emit_neg_m16isd(e, index, scale, disp) emit_neg_m16bisd(e, REG_NONE, (index), (scale), (disp))
3960
3961
3962		/*------------------------------------------------------------------
3963		emit_mul_r16_*
3964		------------------------------------------------------------------*/
3965
3966		#define emit_mul_r16(e, dreg) emit_group3_r16(e, 4, dreg)
3967		#define emit_mul_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 4, base, index, scale, disp)
3968
3969		#define emit_mul_m16abs(e, addr) emit_mul_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3970		#define emit_mul_m16bd(e, base, disp) emit_mul_m16bisd(e, (base), REG_NONE, 1, (disp))
3971		#define emit_mul_m16isd(e, index, scale, disp) emit_mul_m16bisd(e, REG_NONE, (index), (scale), (disp))
3972
3973
3974		/*------------------------------------------------------------------
3975		emit_imul_r16_*
3976		------------------------------------------------------------------*/
3977
3978		#define emit_imul_r16(e, dreg) emit_group3_r16(e, 5, dreg)
3979		#define emit_imul_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 5, base, index, scale, disp)
3980
3981		#define emit_imul_m16abs(e, addr) emit_imul_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3982		#define emit_imul_m16bd(e, base, disp) emit_imul_m16bisd(e, (base), REG_NONE, 1, (disp))
3983		#define emit_imul_m16isd(e, index, scale, disp) emit_imul_m16bisd(e, REG_NONE, (index), (scale), (disp))
3984
3985
3986		/*------------------------------------------------------------------
3987		emit_div_r16_*
3988		------------------------------------------------------------------*/
3989
3990		#define emit_div_r16(e, dreg) emit_group3_r16(e, 6, dreg)
3991		#define emit_div_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 6, base, index, scale, disp)
3992
3993		#define emit_div_m16abs(e, addr) emit_div_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
3994		#define emit_div_m16bd(e, base, disp) emit_div_m16bisd(e, (base), REG_NONE, 1, (disp))
3995		#define emit_div_m16isd(e, index, scale, disp) emit_div_m16bisd(e, REG_NONE, (index), (scale), (disp))
3996
3997
3998		/*------------------------------------------------------------------
3999		emit_idiv_r16_*
4000		------------------------------------------------------------------*/
4001
4002		#define emit_idiv_r16(e, dreg) emit_group3_r16(e, 7, dreg)
4003		#define emit_idiv_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 7, base, index, scale, disp)
4004
4005		#define emit_idiv_m16abs(e, addr) emit_idiv_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4006		#define emit_idiv_m16bd(e, base, disp) emit_idiv_m16bisd(e, (base), REG_NONE, 1, (disp))
4007		#define emit_idiv_m16isd(e, index, scale, disp) emit_idiv_m16bisd(e, REG_NONE, (index), (scale), (disp))
4008
4009
4010
4011		/***************************************************************************
4012		32-BIT GROUP3 EMITTERS
4013		***************************************************************************/
4014
4015		/*
4016		Note that the following code relies on this:
4017
4018		/0 = ROL
4019		/1 = ROR
4020		/2 = RCL
4021		/3 = RCR
4022		/4 = SHL
4023		/5 = SHR
4024		/7 = SAR
4025		*/
4026
4027		/*------------------------------------------------------------------
4028		emit_group3_r32_*
4029		------------------------------------------------------------------*/
4030
4031		INLINE void emit_group3_r32(x86code **emitptr, UINT8 opindex, UINT8 dreg)
4032		{
4033		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, opindex, dreg);
4034		}
4035
4036		INLINE void emit_group3_m32bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
4037		{
4038		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, opindex, base, index, scale, disp);
4039		}
4040
4041
4042		/*------------------------------------------------------------------
4043		emit_not_r32_*
4044		------------------------------------------------------------------*/
4045
4046		#define emit_not_r32(e, dreg) emit_group3_r32(e, 2, dreg)
4047		#define emit_not_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 2, base, index, scale, disp)
4048
4049		#define emit_not_m32abs(e, addr) emit_not_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4050		#define emit_not_m32bd(e, base, disp) emit_not_m32bisd(e, (base), REG_NONE, 1, (disp))
4051		#define emit_not_m32isd(e, index, scale, disp) emit_not_m32bisd(e, REG_NONE, (index), (scale), (disp))
4052
4053
4054		/*------------------------------------------------------------------
4055		emit_neg_r32_*
4056		------------------------------------------------------------------*/
4057
4058		#define emit_neg_r32(e, dreg) emit_group3_r32(e, 3, dreg)
4059		#define emit_neg_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 3, base, index, scale, disp)
4060
4061		#define emit_neg_m32abs(e, addr) emit_neg_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4062		#define emit_neg_m32bd(e, base, disp) emit_neg_m32bisd(e, (base), REG_NONE, 1, (disp))
4063		#define emit_neg_m32isd(e, index, scale, disp) emit_neg_m32bisd(e, REG_NONE, (index), (scale), (disp))
4064
4065
4066		/*------------------------------------------------------------------
4067		emit_mul_r32_*
4068		------------------------------------------------------------------*/
4069
4070		#define emit_mul_r32(e, dreg) emit_group3_r32(e, 4, dreg)
4071		#define emit_mul_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 4, base, index, scale, disp)
4072
4073		#define emit_mul_m32abs(e, addr) emit_mul_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4074		#define emit_mul_m32bd(e, base, disp) emit_mul_m32bisd(e, (base), REG_NONE, 1, (disp))
4075		#define emit_mul_m32isd(e, index, scale, disp) emit_mul_m32bisd(e, REG_NONE, (index), (scale), (disp))
4076
4077
4078		/*------------------------------------------------------------------
4079		emit_imul_r32_*
4080		------------------------------------------------------------------*/
4081
4082		#define emit_imul_r32(e, dreg) emit_group3_r32(e, 5, dreg)
4083		#define emit_imul_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 5, base, index, scale, disp)
4084
4085		#define emit_imul_m32abs(e, addr) emit_imul_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4086		#define emit_imul_m32bd(e, base, disp) emit_imul_m32bisd(e, (base), REG_NONE, 1, (disp))
4087		#define emit_imul_m32isd(e, index, scale, disp) emit_imul_m32bisd(e, REG_NONE, (index), (scale), (disp))
4088
4089
4090		/*------------------------------------------------------------------
4091		emit_div_r32_*
4092		------------------------------------------------------------------*/
4093
4094		#define emit_div_r32(e, dreg) emit_group3_r32(e, 6, dreg)
4095		#define emit_div_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 6, base, index, scale, disp)
4096
4097		#define emit_div_m32abs(e, addr) emit_div_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4098		#define emit_div_m32bd(e, base, disp) emit_div_m32bisd(e, (base), REG_NONE, 1, (disp))
4099		#define emit_div_m32isd(e, index, scale, disp) emit_div_m32bisd(e, REG_NONE, (index), (scale), (disp))
4100
4101
4102		/*------------------------------------------------------------------
4103		emit_idiv_r32_*
4104		------------------------------------------------------------------*/
4105
4106		#define emit_idiv_r32(e, dreg) emit_group3_r32(e, 7, dreg)
4107		#define emit_idiv_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 7, base, index, scale, disp)
4108
4109		#define emit_idiv_m32abs(e, addr) emit_idiv_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4110		#define emit_idiv_m32bd(e, base, disp) emit_idiv_m32bisd(e, (base), REG_NONE, 1, (disp))
4111		#define emit_idiv_m32isd(e, index, scale, disp) emit_idiv_m32bisd(e, REG_NONE, (index), (scale), (disp))
4112
4113
4114
4115		/***************************************************************************
4116		64-BIT GROUP3 EMITTERS
4117		***************************************************************************/
4118
4119		#ifdef PTR64
4120		/*
4121		Note that the following code relies on this:
4122
4123		/0 = ROL
4124		/1 = ROR
4125		/2 = RCL
4126		/3 = RCR
4127		/4 = SHL
4128		/5 = SHR
4129		/7 = SAR
4130		*/
4131
4132		/*------------------------------------------------------------------
4133		emit_group3_r64_*
4134		------------------------------------------------------------------*/
4135
4136		INLINE void emit_group3_r64(x86code **emitptr, UINT8 opindex, UINT8 dreg)
4137		{
4138		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, opindex, dreg);
4139		}
4140
4141		INLINE void emit_group3_m64bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
4142		{
4143		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, opindex, base, index, scale, disp);
4144		}
4145
4146
4147		/*------------------------------------------------------------------
4148		emit_not_r64_*
4149		------------------------------------------------------------------*/
4150
4151		#define emit_not_r64(e, dreg) emit_group3_r64(e, 2, dreg)
4152		#define emit_not_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 2, base, index, scale, disp)
4153
4154		#define emit_not_m64abs(e, addr) emit_not_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4155		#define emit_not_m64bd(e, base, disp) emit_not_m64bisd(e, (base), REG_NONE, 1, (disp))
4156		#define emit_not_m64isd(e, index, scale, disp) emit_not_m64bisd(e, REG_NONE, (index), (scale), (disp))
4157
4158
4159		/*------------------------------------------------------------------
4160		emit_neg_r64_*
4161		------------------------------------------------------------------*/
4162
4163		#define emit_neg_r64(e, dreg) emit_group3_r64(e, 3, dreg)
4164		#define emit_neg_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 3, base, index, scale, disp)
4165
4166		#define emit_neg_m64abs(e, addr) emit_neg_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4167		#define emit_neg_m64bd(e, base, disp) emit_neg_m64bisd(e, (base), REG_NONE, 1, (disp))
4168		#define emit_neg_m64isd(e, index, scale, disp) emit_neg_m64bisd(e, REG_NONE, (index), (scale), (disp))
4169
4170
4171		/*------------------------------------------------------------------
4172		emit_mul_r64_*
4173		------------------------------------------------------------------*/
4174
4175		#define emit_mul_r64(e, dreg) emit_group3_r64(e, 4, dreg)
4176		#define emit_mul_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 4, base, index, scale, disp)
4177
4178		#define emit_mul_m64abs(e, addr) emit_mul_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4179		#define emit_mul_m64bd(e, base, disp) emit_mul_m64bisd(e, (base), REG_NONE, 1, (disp))
4180		#define emit_mul_m64isd(e, index, scale, disp) emit_mul_m64bisd(e, REG_NONE, (index), (scale), (disp))
4181
4182
4183		/*------------------------------------------------------------------
4184		emit_imul_r64_*
4185		------------------------------------------------------------------*/
4186
4187		#define emit_imul_r64(e, dreg) emit_group3_r64(e, 5, dreg)
4188		#define emit_imul_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 5, base, index, scale, disp)
4189
4190		#define emit_imul_m64abs(e, addr) emit_imul_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4191		#define emit_imul_m64bd(e, base, disp) emit_imul_m64bisd(e, (base), REG_NONE, 1, (disp))
4192		#define emit_imul_m64isd(e, index, scale, disp) emit_imul_m64bisd(e, REG_NONE, (index), (scale), (disp))
4193
4194
4195		/*------------------------------------------------------------------
4196		emit_div_r64_*
4197		------------------------------------------------------------------*/
4198
4199		#define emit_div_r64(e, dreg) emit_group3_r64(e, 6, dreg)
4200		#define emit_div_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 6, base, index, scale, disp)
4201
4202		#define emit_div_m64abs(e, addr) emit_div_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4203		#define emit_div_m64bd(e, base, disp) emit_div_m64bisd(e, (base), REG_NONE, 1, (disp))
4204		#define emit_div_m64isd(e, index, scale, disp) emit_div_m64bisd(e, REG_NONE, (index), (scale), (disp))
4205
4206
4207		/*------------------------------------------------------------------
4208		emit_idiv_r64_*
4209		------------------------------------------------------------------*/
4210
4211		#define emit_idiv_r64(e, dreg) emit_group3_r64(e, 7, dreg)
4212		#define emit_idiv_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 7, base, index, scale, disp)
4213
4214		#define emit_idiv_m64abs(e, addr) emit_idiv_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4215		#define emit_idiv_m64bd(e, base, disp) emit_idiv_m64bisd(e, (base), REG_NONE, 1, (disp))
4216		#define emit_idiv_m64isd(e, index, scale, disp) emit_idiv_m64bisd(e, REG_NONE, (index), (scale), (disp))
4217
4218		#endif
4219
4220
4221
4222		/***************************************************************************
4223		LEA EMITTERS
4224		***************************************************************************/
4225
4226		/*------------------------------------------------------------------
4227		emit_lea_r32_*
4228		------------------------------------------------------------------*/
4229
4230		INLINE void emit_lea_r32_m32bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
4231		{
4232		emit_op_modrm_mem(emitptr, OP_LEA_Gv_M, OP_32BIT, dreg, base, index, scale, disp);
4233		}
4234
4235		#define emit_lea_r32_m32abs(e, dreg, addr) emit_lea_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4236		#define emit_lea_r32_m32bd(e, dreg, base, disp) emit_lea_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
4237		#define emit_lea_r32_m32isd(e, dreg, index, scale, disp) emit_lea_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
4238
4239
4240		/*------------------------------------------------------------------
4241		emit_lea_r64_*
4242		------------------------------------------------------------------*/
4243
4244		#ifdef PTR64
4245		INLINE void emit_lea_r64_m64bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
4246		{
4247		emit_op_modrm_mem(emitptr, OP_LEA_Gv_M, OP_64BIT, dreg, base, index, scale, disp);
4248		}
4249
4250		#define emit_lea_r64_m64abs(e, dreg, addr) emit_lea_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4251		#define emit_lea_r64_m64bd(e, dreg, base, disp) emit_lea_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
4252		#define emit_lea_r64_m64isd(e, dreg, index, scale, disp) emit_lea_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
4253		#endif
4254
4255
4256
4257		/***************************************************************************
4258		PUSH/POP EMITTERS
4259		***************************************************************************/
4260
4261		/*------------------------------------------------------------------
4262		emit_push_*
4263		------------------------------------------------------------------*/
4264
4265	1458	#ifndef PTR64
4266		INLINE void emit_push_r32(x86code **emitptr, UINT8 reg)
4267		{
4268		emit_op(emitptr, OP_PUSH_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
4269		}
	1459	INLINE void emit_pushad(x86code **emitptr) { emit_op_simple(emitptr, OP_PUSHA, OP_32BIT); }
	1460	INLINE void emit_popad(x86code **emitptr) { emit_op_simple(emitptr, OP_POPA, OP_32BIT); }
	1461	INLINE void emit_lahf(x86code **emitptr) { emit_op_simple(emitptr, OP_LAHF, OP_32BIT); }
	1462	INLINE void emit_sahf(x86code **emitptr) { emit_op_simple(emitptr, OP_SAHF, OP_32BIT); }
4270	1463	#endif
4271	1464
4272	1465	#ifdef PTR64
4273		INLINE void emit_push_r64(x86code **emitptr, UINT8 reg)
4274		{
4275		emit_op(emitptr, OP_PUSH_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
4276		}
	1466	INLINE void emit_cqo(x86code **emitptr) { emit_op_simple(emitptr, OP_CQO, OP_64BIT); }
4277	1467	#endif
4278	1468
4279	1469
4280		/*------------------------------------------------------------------
4281		emit_pop_*
4282		------------------------------------------------------------------*/
4283	1470
4284		#ifndef PTR64
4285		INLINE void emit_pop_r32(x86code **emitptr, UINT8 reg)
4286		{
4287		emit_op(emitptr, OP_POP_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
4288		}
4289		#endif
4290
4291		#ifdef PTR64
4292		INLINE void emit_pop_r64(x86code **emitptr, UINT8 reg)
4293		{
4294		emit_op(emitptr, OP_POP_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
4295		}
4296		#endif
4297
4298
4299
4300	1471	/***************************************************************************
4301		SET EMITTERS
4302		***************************************************************************/
4303
4304		/*------------------------------------------------------------------
4305		emit_setcc_*
4306		------------------------------------------------------------------*/
4307
4308		INLINE void emit_setcc_r8(x86code **emitptr, UINT8 condition, UINT8 dreg)
4309		{
4310		emit_op_modrm_reg(emitptr, OP_SETCC_O_Eb + condition, OP_32BIT, 0, dreg);
4311		}
4312
4313		INLINE void emit_setcc_m8bisd(x86code **emitptr, UINT8 condition, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
4314		{
4315		emit_op_modrm_mem(emitptr, OP_SETCC_O_Eb + condition, OP_32BIT, 0, base, index, scale, disp);
4316		}
4317
4318		#define emit_setcc_m8abs(e, cond, addr) emit_setcc_m8bisd(e, cond, REG_NONE, REG_NONE, 1, (INT32)(addr))
4319		#define emit_setcc_m8bd(e, cond, base, disp) emit_setcc_m8bisd(e, cond, (base), REG_NONE, 1, (disp))
4320		#define emit_setcc_m8isd(e, cond, index, scale, disp) emit_setcc_m8bisd(e, cond, REG_NONE, (index), (scale), (disp))
4321
4322
4323
4324		/***************************************************************************
4325		FPU EMITTERS
4326		***************************************************************************/
4327
4328		#ifndef PTR64
4329		INLINE void emit_fp_simple(x86code **emitptr, UINT8 op)
4330		{
4331		emit_op_simple(emitptr, op, OP_32BIT);
4332		}
4333
4334		INLINE void emit_fp_reg(x86code **emitptr, UINT8 op, UINT8 reg)
4335		{
4336		emit_op_simple(emitptr, op + reg, OP_32BIT);
4337		}
4338
4339		INLINE void emit_fp_modrm(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
4340		{
4341		emit_op_modrm_mem(emitptr, op, OP_32BIT, dreg, base, index, scale, disp);
4342		}
4343
4344
4345
4346		/***************************************************************************
4347		SIMPLE FPU EMITTERS
4348		***************************************************************************/
4349
4350		#define emit_fnop(e) emit_fp_simple(e, OP_FNOP)
4351		#define emit_fchs(e) emit_fp_simple(e, OP_FCHS)
4352		#define emit_fabs(e) emit_fp_simple(e, OP_FABS)
4353		#define emit_ftst(e) emit_fp_simple(e, OP_FTST)
4354		#define emit_fxam(e) emit_fp_simple(e, OP_FXAM)
4355		#define emit_fld1(e) emit_fp_simple(e, OP_FLD1)
4356		#define emit_fldl2t(e) emit_fp_simple(e, OP_FLDL2T)
4357		#define emit_fldl2e(e) emit_fp_simple(e, OP_FLDL2E)
4358		#define emit_fldpi(e) emit_fp_simple(e, OP_FLDPI)
4359		#define emit_fldlg2(e) emit_fp_simple(e, OP_FLDLG2)
4360		#define emit_fldln2(e) emit_fp_simple(e, OP_FLDLN2)
4361		#define emit_fldz(e) emit_fp_simple(e, OP_FLDZ)
4362		#define emit_f2xm1(e) emit_fp_simple(e, OP_F2XM1)
4363		#define emit_fyl2x(e) emit_fp_simple(e, OP_FYL2X)
4364		#define emit_fptan(e) emit_fp_simple(e, OP_FPTAN)
4365		#define emit_fpatan(e) emit_fp_simple(e, OP_FPATAN)
4366		#define emit_fxtract(e) emit_fp_simple(e, OP_FXTRACT)
4367		#define emit_fprem1(e) emit_fp_simple(e, OP_FPREM1)
4368		#define emit_fdecstp(e) emit_fp_simple(e, OP_FDECSTP)
4369		#define emit_fincstp(e) emit_fp_simple(e, OP_FINCSTP)
4370		#define emit_fprem(e) emit_fp_simple(e, OP_FPREM)
4371		#define emit_fyl2xp1(e) emit_fp_simple(e, OP_FYl2XP1)
4372		#define emit_fsqrt(e) emit_fp_simple(e, OP_FSQRT)
4373		#define emit_fsincos(e) emit_fp_simple(e, OP_FSINCOS)
4374		#define emit_frndint(e) emit_fp_simple(e, OP_FRNDINT)
4375		#define emit_fscale(e) emit_fp_simple(e, OP_FSCALE)
4376		#define emit_fsin(e) emit_fp_simple(e, OP_FSIN)
4377		#define emit_fcos(e) emit_fp_simple(e, OP_FCOS)
4378		#define emit_fucompp(e) emit_fp_simple(e, OP_FUCOMPP)
4379		#define emit_fclex(e) emit_fp_simple(e, OP_FCLEX)
4380		#define emit_finit(e) emit_fp_simple(e, OP_FINIT)
4381		#define emit_fcompp(e) emit_fp_simple(e, OP_FCOMPP)
4382		#define emit_fstsw_ax(e) emit_fp_simple(e, OP_FSTSW_AX)
4383
4384
4385
4386		/***************************************************************************
4387		REGISTER-BASED FPU EMITTERS
4388		***************************************************************************/
4389
4390		#define emit_ffree_stn(e, reg) emit_fp_reg(e, OP_FFREE_STn, reg)
4391		#define emit_fst_stn(e, reg) emit_fp_reg(e, OP_FST_STn, reg)
4392		#define emit_fstp_stn(e, reg) emit_fp_reg(e, OP_FSTP_STn, reg)
4393		#define emit_fucomp_stn(e, reg) emit_fp_reg(e, OP_FUCOMP_STn, reg)
4394
4395		#define emit_fadd_st0_stn(e, reg) emit_fp_reg(e, OP_FADD_ST0_STn, reg)
4396		#define emit_fmul_st0_stn(e, reg) emit_fp_reg(e, OP_FMUL_ST0_STn, reg)
4397		#define emit_fcom_st0_stn(e, reg) emit_fp_reg(e, OP_FCOM_ST0_STn, reg)
4398		#define emit_fcomp_st0_stn(e, reg) emit_fp_reg(e, OP_FCOMP_ST0_STn, reg)
4399		#define emit_fsub_st0_stn(e, reg) emit_fp_reg(e, OP_FSUB_ST0_STn, reg)
4400		#define emit_fsubr_st0_stn(e, reg) emit_fp_reg(e, OP_FSUBR_ST0_STn, reg)
4401		#define emit_fdiv_st0_stn(e, reg) emit_fp_reg(e, OP_FDIV_ST0_STn, reg)
4402		#define emit_fdivr_st0_stn(e, reg) emit_fp_reg(e, OP_FDIVR_ST0_STn, reg)
4403		#define emit_fld_st0_stn(e, reg) emit_fp_reg(e, OP_FLD_ST0_STn, reg)
4404		#define emit_fxch_st0_stn(e, reg) emit_fp_reg(e, OP_FXCH_ST0_STn, reg)
4405		#define emit_fcmovb_st0_stn(e, reg) emit_fp_reg(e, OP_FCMOVB_ST0_STn, reg)
4406		#define emit_fcmove_st0_stn(e, reg) emit_fp_reg(e, OP_FCMOVE_ST0_STn, reg)
4407		#define emit_fcmovbe_st0_stn(e, reg) emit_fp_reg(e, OP_FCMOVBE_ST0_STn, reg)
4408		#define emit_fcmovu_st0_stn(e, reg) emit_fp_reg(e, OP_FCMOVU_ST0_STn, reg)
4409		#define emit_fcmovnb_st0_stn(e, reg) emit_fp_reg(e, OP_FCMOVNB_ST0_STn, reg)
4410		#define emit_fcmovne_st0_stn(e, reg) emit_fp_reg(e, OP_FCMOVNE_ST0_STn, reg)
4411		#define emit_fcmovnbe_st0_stn(e, reg) emit_fp_reg(e, OP_FCMOVNBE_ST0_STn, reg)
4412		#define emit_fcmovnu_st0_stn(e, reg) emit_fp_reg(e, OP_FCMOVNU_ST0_STn, reg)
4413		#define emit_fucomi_st0_stn(e, reg) emit_fp_reg(e, OP_FUCOMI_ST0_STn, reg)
4414		#define emit_fcomi_st0_stn(e, reg) emit_fp_reg(e, OP_FCOMI_ST0_STn, reg)
4415		#define emit_fcomip_st0_stn(e, reg) emit_fp_reg(e, OP_FCOMIP_ST0_STn, reg)
4416
4417		#define emit_fadd_stn_st0(e, reg) emit_fp_reg(e, OP_FADD_STn_ST0, reg)
4418		#define emit_fmul_stn_st0(e, reg) emit_fp_reg(e, OP_FMUL_STn_ST0, reg)
4419		#define emit_fsubr_stn_st0(e, reg) emit_fp_reg(e, OP_FSUBR_STn_ST0, reg)
4420		#define emit_fsub_stn_st0(e, reg) emit_fp_reg(e, OP_FSUB_STn_ST0, reg)
4421		#define emit_fdivr_stn_st0(e, reg) emit_fp_reg(e, OP_FDIVR_STn_ST0, reg)
4422		#define emit_fdiv_stn_st0(e, reg) emit_fp_reg(e, OP_FDIV_STn_ST0, reg)
4423		#define emit_fucom_stn_st0(e, reg) emit_fp_reg(e, OP_FUCOM_STn_ST0, reg)
4424		#define emit_faddp_stn_st0(e, reg) emit_fp_reg(e, OP_FADDP_STn_ST0, reg)
4425		#define emit_fmulp_stn_st0(e, reg) emit_fp_reg(e, OP_FMULP_STn_ST0, reg)
4426		#define emit_fsubrp_stn_st0(e, reg) emit_fp_reg(e, OP_FSUBRP_STn_ST0, reg)
4427		#define emit_fsubp_stn_st0(e, reg) emit_fp_reg(e, OP_FSUBP_STn_ST0, reg)
4428		#define emit_fdivrp_stn_st0(e, reg) emit_fp_reg(e, OP_FDIVRP_STn_ST0, reg)
4429		#define emit_fdivp_stn_st0(e, reg) emit_fp_reg(e, OP_FDIVP_STn_ST0, reg)
4430
4431
4432
4433		/***************************************************************************
4434		MEMORY FPU EMITTERS
4435		***************************************************************************/
4436
4437		#define emit_fadd_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_D8, 0, REG_NONE, REG_NONE, 1, (INT32)(addr))
4438		#define emit_fadd_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D8, 0, (base), REG_NONE, 1, (disp))
4439		#define emit_fadd_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 0, REG_NONE, (index), (scale), (disp))
4440		#define emit_fadd_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 0, (base), (index), (scale), (disp))
4441
4442		#define emit_fmul_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_D8, 1, REG_NONE, REG_NONE, 1, (INT32)(addr))
4443		#define emit_fmul_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D8, 1, (base), REG_NONE, 1, (disp))
4444		#define emit_fmul_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 1, REG_NONE, (index), (scale), (disp))
4445		#define emit_fmul_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 1, (base), (index), (scale), (disp))
4446
4447		#define emit_fcom_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_D8, 2, REG_NONE, REG_NONE, 1, (INT32)(addr))
4448		#define emit_fcom_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D8, 2, (base), REG_NONE, 1, (disp))
4449		#define emit_fcom_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 2, REG_NONE, (index), (scale), (disp))
4450		#define emit_fcom_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 2, (base), (index), (scale), (disp))
4451
4452		#define emit_fcomp_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_D8, 3, REG_NONE, REG_NONE, 1, (INT32)(addr))
4453		#define emit_fcomp_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D8, 3, (base), REG_NONE, 1, (disp))
4454		#define emit_fcomp_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 3, REG_NONE, (index), (scale), (disp))
4455		#define emit_fcomp_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 3, (base), (index), (scale), (disp))
4456
4457		#define emit_fsub_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_D8, 4, REG_NONE, REG_NONE, 1, (INT32)(addr))
4458		#define emit_fsub_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D8, 4, (base), REG_NONE, 1, (disp))
4459		#define emit_fsub_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 4, REG_NONE, (index), (scale), (disp))
4460		#define emit_fsub_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 4, (base), (index), (scale), (disp))
4461
4462		#define emit_fsubr_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_D8, 5, REG_NONE, REG_NONE, 1, (INT32)(addr))
4463		#define emit_fsubr_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D8, 5, (base), REG_NONE, 1, (disp))
4464		#define emit_fsubr_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 5, REG_NONE, (index), (scale), (disp))
4465		#define emit_fsubr_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 5, (base), (index), (scale), (disp))
4466
4467		#define emit_fdiv_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_D8, 6, REG_NONE, REG_NONE, 1, (INT32)(addr))
4468		#define emit_fdiv_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D8, 6, (base), REG_NONE, 1, (disp))
4469		#define emit_fdiv_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 6, REG_NONE, (index), (scale), (disp))
4470		#define emit_fdiv_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 6, (base), (index), (scale), (disp))
4471
4472		#define emit_fdivr_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_D8, 7, REG_NONE, REG_NONE, 1, (INT32)(addr))
4473		#define emit_fdivr_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D8, 7, (base), REG_NONE, 1, (disp))
4474		#define emit_fdivr_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 7, REG_NONE, (index), (scale), (disp))
4475		#define emit_fdivr_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D8, 7, (base), (index), (scale), (disp))
4476
4477
4478		#define emit_fld_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_D9, 0, REG_NONE, REG_NONE, 1, (INT32)(addr))
4479		#define emit_fld_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D9, 0, (base), REG_NONE, 1, (disp))
4480		#define emit_fld_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 0, REG_NONE, (index), (scale), (disp))
4481		#define emit_fld_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 0, (base), (index), (scale), (disp))
4482
4483		#define emit_fst_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_D9, 2, REG_NONE, REG_NONE, 1, (INT32)(addr))
4484		#define emit_fst_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D9, 2, (base), REG_NONE, 1, (disp))
4485		#define emit_fst_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 2, REG_NONE, (index), (scale), (disp))
4486		#define emit_fst_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 2, (base), (index), (scale), (disp))
4487
4488		#define emit_fstp_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_D9, 3, REG_NONE, REG_NONE, 1, (INT32)(addr))
4489		#define emit_fstp_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D9, 3, (base), REG_NONE, 1, (disp))
4490		#define emit_fstp_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 3, REG_NONE, (index), (scale), (disp))
4491		#define emit_fstp_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 3, (base), (index), (scale), (disp))
4492
4493		#define emit_fldenv_mabs(e, addr) emit_fp_modrm(e, OP_ESC_D9, 4, REG_NONE, REG_NONE, 1, (INT32)(addr))
4494		#define emit_fldenv_mbd(e, base, disp) emit_fp_modrm(e, OP_ESC_D9, 4, (base), REG_NONE, 1, (disp))
4495		#define emit_fldenv_misd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 4, REG_NONE, (index), (scale), (disp))
4496		#define emit_fldenv_mbisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 4, (base), (index), (scale), (disp))
4497
4498		#define emit_fldcw_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_D9, 5, REG_NONE, REG_NONE, 1, (INT32)(addr))
4499		#define emit_fldcw_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D9, 5, (base), REG_NONE, 1, (disp))
4500		#define emit_fldcw_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 5, REG_NONE, (index), (scale), (disp))
4501		#define emit_fldcw_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 5, (base), (index), (scale), (disp))
4502
4503		#define emit_fstenv_mabs(e, addr) emit_fp_modrm(e, OP_ESC_D9, 6, REG_NONE, REG_NONE, 1, (INT32)(addr))
4504		#define emit_fstenv_mbd(e, base, disp) emit_fp_modrm(e, OP_ESC_D9, 6, (base), REG_NONE, 1, (disp))
4505		#define emit_fstenv_misd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 6, REG_NONE, (index), (scale), (disp))
4506		#define emit_fstenv_mbisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 6, (base), (index), (scale), (disp))
4507
4508		#define emit_fstcw_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_D9, 7, REG_NONE, REG_NONE, 1, (INT32)(addr))
4509		#define emit_fstcw_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_D9, 7, (base), REG_NONE, 1, (disp))
4510		#define emit_fstcw_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 7, REG_NONE, (index), (scale), (disp))
4511		#define emit_fstcw_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_D9, 7, (base), (index), (scale), (disp))
4512
4513
4514		#define emit_fiadd_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DA, 0, REG_NONE, REG_NONE, 1, (INT32)(addr))
4515		#define emit_fiadd_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DA, 0, (base), REG_NONE, 1, (disp))
4516		#define emit_fiadd_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 0, REG_NONE, (index), (scale), (disp))
4517		#define emit_fiadd_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 0, (base), (index), (scale), (disp))
4518
4519		#define emit_fimul_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DA, 1, REG_NONE, REG_NONE, 1, (INT32)(addr))
4520		#define emit_fimul_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DA, 1, (base), REG_NONE, 1, (disp))
4521		#define emit_fimul_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 1, REG_NONE, (index), (scale), (disp))
4522		#define emit_fimul_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 1, (base), (index), (scale), (disp))
4523
4524		#define emit_ficom_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DA, 2, REG_NONE, REG_NONE, 1, (INT32)(addr))
4525		#define emit_ficom_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DA, 2, (base), REG_NONE, 1, (disp))
4526		#define emit_ficom_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 2, REG_NONE, (index), (scale), (disp))
4527		#define emit_ficom_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 2, (base), (index), (scale), (disp))
4528
4529		#define emit_ficomp_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DA, 3, REG_NONE, REG_NONE, 1, (INT32)(addr))
4530		#define emit_ficomp_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DA, 3, (base), REG_NONE, 1, (disp))
4531		#define emit_ficomp_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 3, REG_NONE, (index), (scale), (disp))
4532		#define emit_ficomp_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 3, (base), (index), (scale), (disp))
4533
4534		#define emit_fisub_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DA, 4, REG_NONE, REG_NONE, 1, (INT32)(addr))
4535		#define emit_fisub_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DA, 4, (base), REG_NONE, 1, (disp))
4536		#define emit_fisub_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 4, REG_NONE, (index), (scale), (disp))
4537		#define emit_fisub_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 4, (base), (index), (scale), (disp))
4538
4539		#define emit_fisubr_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DA, 5, REG_NONE, REG_NONE, 1, (INT32)(addr))
4540		#define emit_fisubr_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DA, 5, (base), REG_NONE, 1, (disp))
4541		#define emit_fisubr_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 5, REG_NONE, (index), (scale), (disp))
4542		#define emit_fisubr_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 5, (base), (index), (scale), (disp))
4543
4544		#define emit_fidiv_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DA, 6, REG_NONE, REG_NONE, 1, (INT32)(addr))
4545		#define emit_fidiv_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DA, 6, (base), REG_NONE, 1, (disp))
4546		#define emit_fidiv_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 6, REG_NONE, (index), (scale), (disp))
4547		#define emit_fidiv_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 6, (base), (index), (scale), (disp))
4548
4549		#define emit_fidivr_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DA, 7, REG_NONE, REG_NONE, 1, (INT32)(addr))
4550		#define emit_fidivr_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DA, 7, (base), REG_NONE, 1, (disp))
4551		#define emit_fidivr_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 7, REG_NONE, (index), (scale), (disp))
4552		#define emit_fidivr_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DA, 7, (base), (index), (scale), (disp))
4553
4554
4555		#define emit_fild_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DB, 0, REG_NONE, REG_NONE, 1, (INT32)(addr))
4556		#define emit_fild_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DB, 0, (base), REG_NONE, 1, (disp))
4557		#define emit_fild_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 0, REG_NONE, (index), (scale), (disp))
4558		#define emit_fild_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 0, (base), (index), (scale), (disp))
4559
4560		#define emit_fisttp_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DB, 1, REG_NONE, REG_NONE, 1, (INT32)(addr))
4561		#define emit_fisttp_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DB, 1, (base), REG_NONE, 1, (disp))
4562		#define emit_fisttp_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 1, REG_NONE, (index), (scale), (disp))
4563		#define emit_fisttp_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 1, (base), (index), (scale), (disp))
4564
4565		#define emit_fist_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DB, 2, REG_NONE, REG_NONE, 1, (INT32)(addr))
4566		#define emit_fist_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DB, 2, (base), REG_NONE, 1, (disp))
4567		#define emit_fist_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 2, REG_NONE, (index), (scale), (disp))
4568		#define emit_fist_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 2, (base), (index), (scale), (disp))
4569
4570		#define emit_fistp_m32abs(e, addr) emit_fp_modrm(e, OP_ESC_DB, 3, REG_NONE, REG_NONE, 1, (INT32)(addr))
4571		#define emit_fistp_m32bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DB, 3, (base), REG_NONE, 1, (disp))
4572		#define emit_fistp_m32isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 3, REG_NONE, (index), (scale), (disp))
4573		#define emit_fistp_m32bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 3, (base), (index), (scale), (disp))
4574
4575		#define emit_fld_m80abs(e, addr) emit_fp_modrm(e, OP_ESC_DB, 5, REG_NONE, REG_NONE, 1, (INT32)(addr))
4576		#define emit_fld_m80bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DB, 5, (base), REG_NONE, 1, (disp))
4577		#define emit_fld_m80isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 5, REG_NONE, (index), (scale), (disp))
4578		#define emit_fld_m80bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 5, (base), (index), (scale), (disp))
4579
4580		#define emit_fstp_m80abs(e, addr) emit_fp_modrm(e, OP_ESC_DB, 7, REG_NONE, REG_NONE, 1, (INT32)(addr))
4581		#define emit_fstp_m80bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DB, 7, (base), REG_NONE, 1, (disp))
4582		#define emit_fstp_m80isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 7, REG_NONE, (index), (scale), (disp))
4583		#define emit_fstp_m80bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DB, 7, (base), (index), (scale), (disp))
4584
4585
4586		#define emit_fadd_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DC, 0, REG_NONE, REG_NONE, 1, (INT32)(addr))
4587		#define emit_fadd_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DC, 0, (base), REG_NONE, 1, (disp))
4588		#define emit_fadd_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 0, REG_NONE, (index), (scale), (disp))
4589		#define emit_fadd_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 0, (base), (index), (scale), (disp))
4590
4591		#define emit_fmul_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DC, 1, REG_NONE, REG_NONE, 1, (INT32)(addr))
4592		#define emit_fmul_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DC, 1, (base), REG_NONE, 1, (disp))
4593		#define emit_fmul_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 1, REG_NONE, (index), (scale), (disp))
4594		#define emit_fmul_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 1, (base), (index), (scale), (disp))
4595
4596		#define emit_fcom_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DC, 2, REG_NONE, REG_NONE, 1, (INT32)(addr))
4597		#define emit_fcom_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DC, 2, (base), REG_NONE, 1, (disp))
4598		#define emit_fcom_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 2, REG_NONE, (index), (scale), (disp))
4599		#define emit_fcom_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 2, (base), (index), (scale), (disp))
4600
4601		#define emit_fcomp_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DC, 3, REG_NONE, REG_NONE, 1, (INT32)(addr))
4602		#define emit_fcomp_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DC, 3, (base), REG_NONE, 1, (disp))
4603		#define emit_fcomp_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 3, REG_NONE, (index), (scale), (disp))
4604		#define emit_fcomp_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 3, (base), (index), (scale), (disp))
4605
4606		#define emit_fsub_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DC, 4, REG_NONE, REG_NONE, 1, (INT32)(addr))
4607		#define emit_fsub_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DC, 4, (base), REG_NONE, 1, (disp))
4608		#define emit_fsub_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 4, REG_NONE, (index), (scale), (disp))
4609		#define emit_fsub_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 4, (base), (index), (scale), (disp))
4610
4611		#define emit_fsubr_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DC, 5, REG_NONE, REG_NONE, 1, (INT32)(addr))
4612		#define emit_fsubr_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DC, 5, (base), REG_NONE, 1, (disp))
4613		#define emit_fsubr_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 5, REG_NONE, (index), (scale), (disp))
4614		#define emit_fsubr_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 5, (base), (index), (scale), (disp))
4615
4616		#define emit_fdiv_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DC, 6, REG_NONE, REG_NONE, 1, (INT32)(addr))
4617		#define emit_fdiv_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DC, 6, (base), REG_NONE, 1, (disp))
4618		#define emit_fdiv_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 6, REG_NONE, (index), (scale), (disp))
4619		#define emit_fdiv_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 6, (base), (index), (scale), (disp))
4620
4621		#define emit_fdivr_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DC, 7, REG_NONE, REG_NONE, 1, (INT32)(addr))
4622		#define emit_fdivr_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DC, 7, (base), REG_NONE, 1, (disp))
4623		#define emit_fdivr_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 7, REG_NONE, (index), (scale), (disp))
4624		#define emit_fdivr_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DC, 7, (base), (index), (scale), (disp))
4625
4626
4627		#define emit_fld_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DD, 0, REG_NONE, REG_NONE, 1, (INT32)(addr))
4628		#define emit_fld_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DD, 0, (base), REG_NONE, 1, (disp))
4629		#define emit_fld_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 0, REG_NONE, (index), (scale), (disp))
4630		#define emit_fld_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 0, (base), (index), (scale), (disp))
4631
4632		#define emit_fisttp_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DD, 1, REG_NONE, REG_NONE, 1, (INT32)(addr))
4633		#define emit_fisttp_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DD, 1, (base), REG_NONE, 1, (disp))
4634		#define emit_fisttp_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 1, REG_NONE, (index), (scale), (disp))
4635		#define emit_fisttp_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 1, (base), (index), (scale), (disp))
4636
4637		#define emit_fst_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DD, 2, REG_NONE, REG_NONE, 1, (INT32)(addr))
4638		#define emit_fst_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DD, 2, (base), REG_NONE, 1, (disp))
4639		#define emit_fst_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 2, REG_NONE, (index), (scale), (disp))
4640		#define emit_fst_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 2, (base), (index), (scale), (disp))
4641
4642		#define emit_fstp_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DD, 3, REG_NONE, REG_NONE, 1, (INT32)(addr))
4643		#define emit_fstp_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DD, 3, (base), REG_NONE, 1, (disp))
4644		#define emit_fstp_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 3, REG_NONE, (index), (scale), (disp))
4645		#define emit_fstp_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 3, (base), (index), (scale), (disp))
4646
4647		#define emit_frstor_mabs(e, addr) emit_fp_modrm(e, OP_ESC_DD, 4, REG_NONE, REG_NONE, 1, (INT32)(addr))
4648		#define emit_frstor_mbd(e, base, disp) emit_fp_modrm(e, OP_ESC_DD, 4, (base), REG_NONE, 1, (disp))
4649		#define emit_frstor_misd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 4, REG_NONE, (index), (scale), (disp))
4650		#define emit_frstor_mbisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 4, (base), (index), (scale), (disp))
4651
4652		#define emit_fsave_mabs(e, addr) emit_fp_modrm(e, OP_ESC_DD, 6, REG_NONE, REG_NONE, 1, (INT32)(addr))
4653		#define emit_fsave_mbd(e, base, disp) emit_fp_modrm(e, OP_ESC_DD, 6, (base), REG_NONE, 1, (disp))
4654		#define emit_fsave_misd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 6, REG_NONE, (index), (scale), (disp))
4655		#define emit_fsave_mbisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 6, (base), (index), (scale), (disp))
4656
4657		#define emit_fstsw_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DD, 7, REG_NONE, REG_NONE, 1, (INT32)(addr))
4658		#define emit_fstsw_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DD, 7, (base), REG_NONE, 1, (disp))
4659		#define emit_fstsw_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 7, REG_NONE, (index), (scale), (disp))
4660		#define emit_fstsw_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DD, 7, (base), (index), (scale), (disp))
4661
4662
4663		#define emit_fiadd_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DE, 0, REG_NONE, REG_NONE, 1, (INT32)(addr))
4664		#define emit_fiadd_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DE, 0, (base), REG_NONE, 1, (disp))
4665		#define emit_fiadd_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 0, REG_NONE, (index), (scale), (disp))
4666		#define emit_fiadd_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 0, (base), (index), (scale), (disp))
4667
4668		#define emit_fimul_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DE, 1, REG_NONE, REG_NONE, 1, (INT32)(addr))
4669		#define emit_fimul_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DE, 1, (base), REG_NONE, 1, (disp))
4670		#define emit_fimul_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 1, REG_NONE, (index), (scale), (disp))
4671		#define emit_fimul_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 1, (base), (index), (scale), (disp))
4672
4673		#define emit_ficom_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DE, 2, REG_NONE, REG_NONE, 1, (INT32)(addr))
4674		#define emit_ficom_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DE, 2, (base), REG_NONE, 1, (disp))
4675		#define emit_ficom_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 2, REG_NONE, (index), (scale), (disp))
4676		#define emit_ficom_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 2, (base), (index), (scale), (disp))
4677
4678		#define emit_ficomp_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DE, 3, REG_NONE, REG_NONE, 1, (INT32)(addr))
4679		#define emit_ficomp_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DE, 3, (base), REG_NONE, 1, (disp))
4680		#define emit_ficomp_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 3, REG_NONE, (index), (scale), (disp))
4681		#define emit_ficomp_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 3, (base), (index), (scale), (disp))
4682
4683		#define emit_fisub_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DE, 4, REG_NONE, REG_NONE, 1, (INT32)(addr))
4684		#define emit_fisub_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DE, 4, (base), REG_NONE, 1, (disp))
4685		#define emit_fisub_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 4, REG_NONE, (index), (scale), (disp))
4686		#define emit_fisub_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 4, (base), (index), (scale), (disp))
4687
4688		#define emit_fisubr_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DE, 5, REG_NONE, REG_NONE, 1, (INT32)(addr))
4689		#define emit_fisubr_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DE, 5, (base), REG_NONE, 1, (disp))
4690		#define emit_fisubr_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 5, REG_NONE, (index), (scale), (disp))
4691		#define emit_fisubr_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 5, (base), (index), (scale), (disp))
4692
4693		#define emit_fidiv_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DE, 6, REG_NONE, REG_NONE, 1, (INT32)(addr))
4694		#define emit_fidiv_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DE, 6, (base), REG_NONE, 1, (disp))
4695		#define emit_fidiv_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 6, REG_NONE, (index), (scale), (disp))
4696		#define emit_fidiv_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 6, (base), (index), (scale), (disp))
4697
4698		#define emit_fidivr_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DE, 7, REG_NONE, REG_NONE, 1, (INT32)(addr))
4699		#define emit_fidivr_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DE, 7, (base), REG_NONE, 1, (disp))
4700		#define emit_fidivr_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 7, REG_NONE, (index), (scale), (disp))
4701		#define emit_fidivr_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DE, 7, (base), (index), (scale), (disp))
4702
4703
4704		#define emit_fild_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DF, 0, REG_NONE, REG_NONE, 1, (INT32)(addr))
4705		#define emit_fild_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DF, 0, (base), REG_NONE, 1, (disp))
4706		#define emit_fild_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 0, REG_NONE, (index), (scale), (disp))
4707		#define emit_fild_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 0, (base), (index), (scale), (disp))
4708
4709		#define emit_fisttp_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DF, 1, REG_NONE, REG_NONE, 1, (INT32)(addr))
4710		#define emit_fisttp_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DF, 1, (base), REG_NONE, 1, (disp))
4711		#define emit_fisttp_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 1, REG_NONE, (index), (scale), (disp))
4712		#define emit_fisttp_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 1, (base), (index), (scale), (disp))
4713
4714		#define emit_fist_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DF, 2, REG_NONE, REG_NONE, 1, (INT32)(addr))
4715		#define emit_fist_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DF, 2, (base), REG_NONE, 1, (disp))
4716		#define emit_fist_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 2, REG_NONE, (index), (scale), (disp))
4717		#define emit_fist_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 2, (base), (index), (scale), (disp))
4718
4719		#define emit_fistp_m16abs(e, addr) emit_fp_modrm(e, OP_ESC_DF, 3, REG_NONE, REG_NONE, 1, (INT32)(addr))
4720		#define emit_fistp_m16bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DF, 3, (base), REG_NONE, 1, (disp))
4721		#define emit_fistp_m16isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 3, REG_NONE, (index), (scale), (disp))
4722		#define emit_fistp_m16bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 3, (base), (index), (scale), (disp))
4723
4724		#define emit_fbld_m80abs(e, addr) emit_fp_modrm(e, OP_ESC_DF, 4, REG_NONE, REG_NONE, 1, (INT32)(addr))
4725		#define emit_fbld_m80bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DF, 4, (base), REG_NONE, 1, (disp))
4726		#define emit_fbld_m80isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 4, REG_NONE, (index), (scale), (disp))
4727		#define emit_fbld_m80bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 4, (base), (index), (scale), (disp))
4728
4729		#define emit_fild_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DF, 5, REG_NONE, REG_NONE, 1, (INT32)(addr))
4730		#define emit_fild_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DF, 5, (base), REG_NONE, 1, (disp))
4731		#define emit_fild_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 5, REG_NONE, (index), (scale), (disp))
4732		#define emit_fild_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 5, (base), (index), (scale), (disp))
4733
4734		#define emit_fbstp_m80abs(e, addr) emit_fp_modrm(e, OP_ESC_DF, 6, REG_NONE, REG_NONE, 1, (INT32)(addr))
4735		#define emit_fbstp_m80bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DF, 6, (base), REG_NONE, 1, (disp))
4736		#define emit_fbstp_m80isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 6, REG_NONE, (index), (scale), (disp))
4737		#define emit_fbstp_m80bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 6, (base), (index), (scale), (disp))
4738
4739		#define emit_fistp_m64abs(e, addr) emit_fp_modrm(e, OP_ESC_DF, 7, REG_NONE, REG_NONE, 1, (INT32)(addr))
4740		#define emit_fistp_m64bd(e, base, disp) emit_fp_modrm(e, OP_ESC_DF, 7, (base), REG_NONE, 1, (disp))
4741		#define emit_fistp_m64isd(e, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 7, REG_NONE, (index), (scale), (disp))
4742		#define emit_fistp_m64bisd(e, base, index, scale, disp) emit_fp_modrm(e, OP_ESC_DF, 7, (base), (index), (scale), (disp))
4743
4744		#endif
4745
4746
4747
4748		/***************************************************************************
4749		GROUP16 EMITTERS
4750		***************************************************************************/
4751
4752		/*------------------------------------------------------------------
4753		emit_ldmxcsr_*
4754		------------------------------------------------------------------*/
4755
4756		INLINE void emit_ldmxcsr_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
4757		{
4758		emit_op_modrm_mem(emitptr, OP_G16, OP_32BIT, 2, base, index, scale, disp);
4759		}
4760
4761		#define emit_ldmxcsr_m32abs(e, addr) emit_ldmxcsr_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4762		#define emit_ldmxcsr_m32bd(e, base, disp) emit_ldmxcsr_m32bisd(e, (base), REG_NONE, 1, (disp))
4763		#define emit_ldmxcsr_m32isd(e, index, scale, disp) emit_ldmxcsr_m32bisd(e, REG_NONE, (index), (scale), (disp))
4764
4765
4766		/*------------------------------------------------------------------
4767		emit_stmxcsr_*
4768		------------------------------------------------------------------*/
4769
4770		INLINE void emit_stmxcsr_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
4771		{
4772		emit_op_modrm_mem(emitptr, OP_G16, OP_32BIT, 3, base, index, scale, disp);
4773		}
4774
4775		#define emit_stmxcsr_m32abs(e, addr) emit_stmxcsr_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
4776		#define emit_stmxcsr_m32bd(e, base, disp) emit_stmxcsr_m32bisd(e, (base), REG_NONE, 1, (disp))
4777		#define emit_stmxcsr_m32isd(e, index, scale, disp) emit_stmxcsr_m32bisd(e, REG_NONE, (index), (scale), (disp))
4778
4779
4780
4781		/***************************************************************************
4782		SSE EMITTERS
4783		***************************************************************************/
4784
4785		INLINE void emit_sse_r128_r128(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 sreg)
4786		{
4787		emit_op_modrm_reg(emitptr, op, OP_32BIT, dreg, sreg);
4788		}
4789
4790		INLINE void emit_sse_r128_mbisd(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
4791		{
4792		emit_op_modrm_mem(emitptr, op, OP_32BIT, dreg, base, index, scale, disp);
4793		}
4794
4795		INLINE void emit_sse_r128_r128_rex(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 sreg)
4796		{
4797		emit_op_modrm_reg(emitptr, op, OP_64BIT, dreg, sreg);
4798		}
4799
4800		INLINE void emit_sse_r128_mbisd_rex(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
4801		{
4802		emit_op_modrm_mem(emitptr, op, OP_64BIT, dreg, base, index, scale, disp);
4803		}
4804
4805
4806
4807		/***************************************************************************
4808		SSE SCALAR SINGLE EMITTERS
4809		***************************************************************************/
4810
4811		#define emit_movss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVSS_Vss_Wss, dreg, sreg)
4812		#define emit_movss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4813		#define emit_movss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
4814		#define emit_movss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
4815		#define emit_movss_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVSS_Vss_Wss, dreg, (base), (index), (scale), (disp))
4816
4817		#define emit_movss_m32abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVSS_Wss_Vss, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4818		#define emit_movss_m32bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSS_Wss_Vss, sreg, (base), REG_NONE, 1, (disp))
4819		#define emit_movss_m32isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSS_Wss_Vss, sreg, REG_NONE, (index), (scale), (disp))
4820		#define emit_movss_m32bisd_r128(e, base, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSS_Wss_Vss, sreg, (base), (index), (scale), (disp))
4821
4822		#define emit_addss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDSS_Vss_Wss, dreg, sreg)
4823		#define emit_addss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4824		#define emit_addss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
4825		#define emit_addss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
4826		#define emit_addss_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDSS_Vss_Wss, dreg, (base), (index), (scale), (disp))
4827
4828		#define emit_subss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBSS_Vss_Wss, dreg, sreg)
4829		#define emit_subss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4830		#define emit_subss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
4831		#define emit_subss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
4832		#define emit_subss_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBSS_Vss_Wss, dreg, (base), (index), (scale), (disp))
4833
4834		#define emit_mulss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULSS_Vss_Wss, dreg, sreg)
4835		#define emit_mulss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4836		#define emit_mulss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
4837		#define emit_mulss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
4838		#define emit_mulss_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULSS_Vss_Wss, dreg, (base), (index), (scale), (disp))
4839
4840		#define emit_divss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVSS_Vss_Wss, dreg, sreg)
4841		#define emit_divss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4842		#define emit_divss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
4843		#define emit_divss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
4844		#define emit_divss_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVSS_Vss_Wss, dreg, (base), (index), (scale), (disp))
4845
4846		#define emit_rcpss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RCPSS_Vss_Wss, dreg, sreg)
4847		#define emit_rcpss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RCPSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4848		#define emit_rcpss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RCPSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
4849		#define emit_rcpss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RCPSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
4850		#define emit_rcpss_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_RCPSS_Vss_Wss, dreg, (base), (index), (scale), (disp))
4851
4852		#define emit_sqrtss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTSS_Vss_Wss, dreg, sreg)
4853		#define emit_sqrtss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4854		#define emit_sqrtss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
4855		#define emit_sqrtss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
4856		#define emit_sqrtss_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTSS_Vss_Wss, dreg, (base), (index), (scale), (disp))
4857
4858		#define emit_rsqrtss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RSQRTSS_Vss_Wss, dreg, sreg)
4859		#define emit_rsqrtss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RSQRTSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4860		#define emit_rsqrtss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RSQRTSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
4861		#define emit_rsqrtss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RSQRTSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
4862		#define emit_rsqrtss_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_RSQRTSS_Vss_Wss, dreg, (base), (index), (scale), (disp))
4863
4864		#define emit_comiss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_COMISS_Vss_Wss, dreg, sreg)
4865		#define emit_comiss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_COMISS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4866		#define emit_comiss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_COMISS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
4867		#define emit_comiss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_COMISS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
4868		#define emit_comiss_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_COMISS_Vss_Wss, dreg, (base), (index), (scale), (disp))
4869
4870		#define emit_ucomiss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_UCOMISS_Vss_Wss, dreg, sreg)
4871		#define emit_ucomiss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_UCOMISS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4872		#define emit_ucomiss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_UCOMISS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
4873		#define emit_ucomiss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_UCOMISS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
4874		#define emit_ucomiss_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_UCOMISS_Vss_Wss, dreg, (base), (index), (scale), (disp))
4875
4876		#define emit_cvtsi2ss_r128_r32(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSI2SS_Vss_Ed, dreg, sreg)
4877		#define emit_cvtsi2ss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4878		#define emit_cvtsi2ss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SS_Vss_Ed, dreg, (base), REG_NONE, 1, (disp))
4879		#define emit_cvtsi2ss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, (index), (scale), (disp))
4880		#define emit_cvtsi2ss_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SS_Vss_Ed, dreg, (base), (index), (scale), (disp))
4881
4882		#ifdef PTR64
4883		#define emit_cvtsi2ss_r128_r64(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, sreg)
4884		#define emit_cvtsi2ss_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4885		#define emit_cvtsi2ss_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, (base), REG_NONE, 1, (disp))
4886		#define emit_cvtsi2ss_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, (index), (scale), (disp))
4887		#define emit_cvtsi2ss_r128_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, (base), (index), (scale), (disp))
4888		#endif
4889
4890		#define emit_cvtsd2ss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSD2SS_Vss_Wsd, dreg, sreg)
4891		#define emit_cvtsd2ss_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSD2SS_Vss_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4892		#define emit_cvtsd2ss_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SS_Vss_Wsd, dreg, (base), REG_NONE, 1, (disp))
4893		#define emit_cvtsd2ss_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SS_Vss_Wsd, dreg, REG_NONE, (index), (scale), (disp))
4894		#define emit_cvtsd2ss_r128_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SS_Vss_Wsd, dreg, (base), (index), (scale), (disp))
4895
4896		#define emit_cvtss2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSS2SI_Gd_Wss, dreg, sreg)
4897		#define emit_cvtss2si_r32_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4898		#define emit_cvtss2si_r32_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
4899		#define emit_cvtss2si_r32_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
4900		#define emit_cvtss2si_r32_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SI_Gd_Wss, dreg, (base), (index), (scale), (disp))
4901
4902		#ifdef PTR64
4903		#define emit_cvtss2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, sreg)
4904		#define emit_cvtss2si_r64_m32abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4905		#define emit_cvtss2si_r64_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
4906		#define emit_cvtss2si_r64_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
4907		#define emit_cvtss2si_r64_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, (base), (index), (scale), (disp))
4908		#endif
4909
4910		#define emit_cvttss2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTSS2SI_Gd_Wss, dreg, sreg)
4911		#define emit_cvttss2si_r32_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4912		#define emit_cvttss2si_r32_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
4913		#define emit_cvttss2si_r32_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
4914		#define emit_cvttss2si_r32_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTSS2SI_Gd_Wss, dreg, (base), (index), (scale), (disp))
4915
4916		#ifdef PTR64
4917		#define emit_cvttss2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, sreg)
4918		#define emit_cvttss2si_r64_m32abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4919		#define emit_cvttss2si_r64_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
4920		#define emit_cvttss2si_r64_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
4921		#define emit_cvttss2si_r64_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, (base), (index), (scale), (disp))
4922		#endif
4923
4924
4925
4926		/***************************************************************************
4927		SSE PACKED SINGLE EMITTERS
4928		***************************************************************************/
4929
4930		#define emit_movps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVPS_Vps_Wps, dreg, sreg)
4931		#define emit_movps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4932		#define emit_movps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
4933		#define emit_movps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
4934		#define emit_movps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
4935
4936		#define emit_movps_m128abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVPS_Wps_Vps, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4937		#define emit_movps_m128bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPS_Wps_Vps, sreg, (base), REG_NONE, 1, (disp))
4938		#define emit_movps_m128isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPS_Wps_Vps, sreg, REG_NONE, (index), (scale), (disp))
4939		#define emit_movps_m128bisd_r128(e, base, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPS_Wps_Vps, sreg, (base), (index), (scale), (disp))
4940
4941		#define emit_addps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDPS_Vps_Wps, dreg, sreg)
4942		#define emit_addps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4943		#define emit_addps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
4944		#define emit_addps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
4945		#define emit_addps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
4946
4947		#define emit_subps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBPS_Vps_Wps, dreg, sreg)
4948		#define emit_subps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4949		#define emit_subps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
4950		#define emit_subps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
4951		#define emit_subps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
4952
4953		#define emit_mulps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULPS_Vps_Wps, dreg, sreg)
4954		#define emit_mulps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4955		#define emit_mulps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
4956		#define emit_mulps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
4957		#define emit_mulps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
4958
4959		#define emit_divps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVPS_Vps_Wps, dreg, sreg)
4960		#define emit_divps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4961		#define emit_divps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
4962		#define emit_divps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
4963		#define emit_divps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
4964
4965		#define emit_rcpps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RCPPS_Vps_Wps, dreg, sreg)
4966		#define emit_rcpps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RCPPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4967		#define emit_rcpps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RCPPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
4968		#define emit_rcpps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RCPPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
4969		#define emit_rcpps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_RCPPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
4970
4971		#define emit_sqrtps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTPS_Vps_Wps, dreg, sreg)
4972		#define emit_sqrtps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4973		#define emit_sqrtps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
4974		#define emit_sqrtps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
4975		#define emit_sqrtps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
4976
4977		#define emit_rsqrtps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RSQRTPS_Vps_Wps, dreg, sreg)
4978		#define emit_rsqrtps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RSQRTPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4979		#define emit_rsqrtps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RSQRTPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
4980		#define emit_rsqrtps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RSQRTPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
4981		#define emit_rsqrtps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_RSQRTPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
4982
4983		#define emit_andps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDPS_Vps_Wps, dreg, sreg)
4984		#define emit_andps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4985		#define emit_andps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
4986		#define emit_andps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
4987		#define emit_andps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
4988
4989		#define emit_andnps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDNPS_Vps_Wps, dreg, sreg)
4990		#define emit_andnps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDNPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4991		#define emit_andnps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDNPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
4992		#define emit_andnps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDNPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
4993		#define emit_andnps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDNPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
4994
4995		#define emit_orps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ORPS_Vps_Wps, dreg, sreg)
4996		#define emit_orps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ORPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
4997		#define emit_orps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ORPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
4998		#define emit_orps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ORPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
4999		#define emit_orps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_ORPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
5000
5001		#define emit_xorps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_XORPS_Vps_Wps, dreg, sreg)
5002		#define emit_xorps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_XORPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5003		#define emit_xorps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_XORPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
5004		#define emit_xorps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_XORPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
5005		#define emit_xorps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_XORPS_Vps_Wps, dreg, (base), (index), (scale), (disp))
5006
5007		#define emit_cvtdq2ps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTDQ2PS_Vps_Wdq, dreg, sreg)
5008		#define emit_cvtdq2ps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTDQ2PS_Vps_Wdq, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5009		#define emit_cvtdq2ps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PS_Vps_Wdq, dreg, (base), REG_NONE, 1, (disp))
5010		#define emit_cvtdq2ps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PS_Vps_Wdq, dreg, REG_NONE, (index), (scale), (disp))
5011		#define emit_cvtdq2ps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PS_Vps_Wdq, dreg, (base), (index), (scale), (disp))
5012
5013		#define emit_cvtpd2ps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPD2PS_Vps_Wpd, dreg, sreg)
5014		#define emit_cvtpd2ps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPD2PS_Vps_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5015		#define emit_cvtpd2ps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPD2PS_Vps_Wpd, dreg, (base), REG_NONE, 1, (disp))
5016		#define emit_cvtpd2ps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPD2PS_Vps_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5017		#define emit_cvtpd2ps_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPD2PS_Vps_Wpd, dreg, (base), (index), (scale), (disp))
5018
5019		#define emit_cvtps2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPS2DQ_Vdq_Wps, dreg, sreg)
5020		#define emit_cvtps2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPS2DQ_Vdq_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5021		#define emit_cvtps2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPS2DQ_Vdq_Wps, dreg, (base), REG_NONE, 1, (disp))
5022		#define emit_cvtps2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPS2DQ_Vdq_Wps, dreg, REG_NONE, (index), (scale), (disp))
5023		#define emit_cvtps2dq_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPS2DQ_Vdq_Wps, dreg, (base), (index), (scale), (disp))
5024
5025		#define emit_cvttps2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, sreg)
5026		#define emit_cvttps2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5027		#define emit_cvttps2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, (base), REG_NONE, 1, (disp))
5028		#define emit_cvttps2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, REG_NONE, (index), (scale), (disp))
5029		#define emit_cvttps2dq_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, (base), (index), (scale), (disp))
5030
5031
5032
5033		/***************************************************************************
5034		SSE SCALAR DOUBLE EMITTERS
5035		***************************************************************************/
5036
5037		#define emit_movsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVSD_Vsd_Wsd, dreg, sreg)
5038		#define emit_movsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5039		#define emit_movsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5040		#define emit_movsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5041		#define emit_movsd_r128_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVSD_Vsd_Wsd, dreg, (base), (index), (scale), (disp))
5042
5043		#define emit_movsd_m64abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVSD_Wsd_Vsd, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5044		#define emit_movsd_m64bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSD_Wsd_Vsd, sreg, (base), REG_NONE, 1, (disp))
5045		#define emit_movsd_m64isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSD_Wsd_Vsd, sreg, REG_NONE, (index), (scale), (disp))
5046		#define emit_movsd_m64bisd_r128(e, base, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSD_Wsd_Vsd, sreg, (base), (index), (scale), (disp))
5047
5048		#define emit_addsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDSD_Vsd_Wsd, dreg, sreg)
5049		#define emit_addsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5050		#define emit_addsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5051		#define emit_addsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5052		#define emit_addsd_r128_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDSD_Vsd_Wsd, dreg, (base), (index), (scale), (disp))
5053
5054		#define emit_subsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBSD_Vsd_Wsd, dreg, sreg)
5055		#define emit_subsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5056		#define emit_subsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5057		#define emit_subsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5058		#define emit_subsd_r128_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBSD_Vsd_Wsd, dreg, (base), (index), (scale), (disp))
5059
5060		#define emit_mulsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULSD_Vsd_Wsd, dreg, sreg)
5061		#define emit_mulsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5062		#define emit_mulsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5063		#define emit_mulsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5064		#define emit_mulsd_r128_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULSD_Vsd_Wsd, dreg, (base), (index), (scale), (disp))
5065
5066		#define emit_divsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVSD_Vsd_Wsd, dreg, sreg)
5067		#define emit_divsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5068		#define emit_divsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5069		#define emit_divsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5070		#define emit_divsd_r128_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVSD_Vsd_Wsd, dreg, (base), (index), (scale), (disp))
5071
5072		#define emit_sqrtsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTSD_Vsd_Wsd, dreg, sreg)
5073		#define emit_sqrtsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5074		#define emit_sqrtsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5075		#define emit_sqrtsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5076		#define emit_sqrtsd_r128_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTSD_Vsd_Wsd, dreg, (base), (index), (scale), (disp))
5077
5078		#define emit_comisd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_COMISD_Vsd_Wsd, dreg, sreg)
5079		#define emit_comisd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_COMISD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5080		#define emit_comisd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_COMISD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5081		#define emit_comisd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_COMISD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5082		#define emit_comisd_r128_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_COMISD_Vsd_Wsd, dreg, (base), (index), (scale), (disp))
5083
5084		#define emit_ucomisd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_UCOMISD_Vsd_Wsd, dreg, sreg)
5085		#define emit_ucomisd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_UCOMISD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5086		#define emit_ucomisd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_UCOMISD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5087		#define emit_ucomisd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_UCOMISD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5088		#define emit_ucomisd_r128_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_UCOMISD_Vsd_Wsd, dreg, (base), (index), (scale), (disp))
5089
5090		#define emit_cvtsi2sd_r128_r32(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSI2SD_Vsd_Ed, dreg, sreg)
5091		#define emit_cvtsi2sd_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5092		#define emit_cvtsi2sd_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SD_Vsd_Ed, dreg, (base), REG_NONE, 1, (disp))
5093		#define emit_cvtsi2sd_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, (index), (scale), (disp))
5094		#define emit_cvtsi2sd_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SD_Vsd_Ed, dreg, (base), (index), (scale), (disp))
5095
5096		#ifdef PTR64
5097		#define emit_cvtsi2sd_r128_r64(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, sreg)
5098		#define emit_cvtsi2sd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5099		#define emit_cvtsi2sd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, (base), REG_NONE, 1, (disp))
5100		#define emit_cvtsi2sd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, (index), (scale), (disp))
5101		#define emit_cvtsi2sd_r128_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, (base), (index), (scale), (disp))
5102		#endif
5103
5104		#define emit_cvtss2sd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSS2SD_Vsd_Wss, dreg, sreg)
5105		#define emit_cvtss2sd_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSS2SD_Vsd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5106		#define emit_cvtss2sd_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SD_Vsd_Wss, dreg, (base), REG_NONE, 1, (disp))
5107		#define emit_cvtss2sd_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SD_Vsd_Wss, dreg, REG_NONE, (index), (scale), (disp))
5108		#define emit_cvtss2sd_r128_m32bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SD_Vsd_Wss, dreg, (base), (index), (scale), (disp))
5109
5110		#define emit_cvtsd2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSD2SI_Gd_Wsd, dreg, sreg)
5111		#define emit_cvtsd2si_r32_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5112		#define emit_cvtsd2si_r32_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5113		#define emit_cvtsd2si_r32_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5114		#define emit_cvtsd2si_r32_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SI_Gd_Wsd, dreg, (base), (index), (scale), (disp))
5115
5116		#ifdef PTR64
5117		#define emit_cvtsd2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, sreg)
5118		#define emit_cvtsd2si_r64_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5119		#define emit_cvtsd2si_r64_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5120		#define emit_cvtsd2si_r64_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5121		#define emit_cvtsd2si_r64_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, (base), (index), (scale), (disp))
5122		#endif
5123
5124		#define emit_cvttsd2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTSD2SI_Gd_Wsd, dreg, sreg)
5125		#define emit_cvttsd2si_r32_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5126		#define emit_cvttsd2si_r32_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5127		#define emit_cvttsd2si_r32_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5128		#define emit_cvttsd2si_r32_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTSD2SI_Gd_Wsd, dreg, (base), (index), (scale), (disp))
5129
5130		#ifdef PTR64
5131		#define emit_cvttsd2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, sreg)
5132		#define emit_cvttsd2si_r64_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5133		#define emit_cvttsd2si_r64_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
5134		#define emit_cvttsd2si_r64_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
5135		#define emit_cvttsd2si_r64_m64bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, (base), (index), (scale), (disp))
5136		#endif
5137
5138
5139
5140		/***************************************************************************
5141		SSE PACKED DOUBLE EMITTERS
5142		***************************************************************************/
5143
5144		#define emit_movpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVPD_Vpd_Wpd, dreg, sreg)
5145		#define emit_movpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5146		#define emit_movpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
5147		#define emit_movpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5148
5149		#define emit_movpd_m128abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVPD_Wpd_Vpd, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5150		#define emit_movpd_m128bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPD_Wpd_Vpd, sreg, (base), REG_NONE, 1, (disp))
5151		#define emit_movpd_m128isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPD_Wpd_Vpd, sreg, REG_NONE, (index), (scale), (disp))
5152
5153		#define emit_addpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDPD_Vpd_Wpd, dreg, sreg)
5154		#define emit_addpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5155		#define emit_addpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
5156		#define emit_addpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5157
5158		#define emit_subpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBPD_Vpd_Wpd, dreg, sreg)
5159		#define emit_subpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5160		#define emit_subpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
5161		#define emit_subpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5162
5163		#define emit_mulpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULPD_Vpd_Wpd, dreg, sreg)
5164		#define emit_mulpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5165		#define emit_mulpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
5166		#define emit_mulpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5167
5168		#define emit_divpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVPD_Vpd_Wpd, dreg, sreg)
5169		#define emit_divpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5170		#define emit_divpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
5171		#define emit_divpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5172
5173		#define emit_sqrtpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTPD_Vpd_Wpd, dreg, sreg)
5174		#define emit_sqrtpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5175		#define emit_sqrtpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
5176		#define emit_sqrtpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5177
5178		#define emit_andpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDPD_Vpd_Wpd, dreg, sreg)
5179		#define emit_andpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5180		#define emit_andpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
5181		#define emit_andpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5182
5183		#define emit_andnpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDNPD_Vpd_Wpd, dreg, sreg)
5184		#define emit_andnpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDNPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5185		#define emit_andnpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDNPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
5186		#define emit_andnpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDNPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5187
5188		#define emit_orpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ORPD_Vpd_Wpd, dreg, sreg)
5189		#define emit_orpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ORPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5190		#define emit_orpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ORPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
5191		#define emit_orpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ORPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5192
5193		#define emit_xorpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_XORPD_Vpd_Wpd, dreg, sreg)
5194		#define emit_xorpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_XORPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5195		#define emit_xorpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_XORPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
5196		#define emit_xorpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_XORPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5197
5198		#define emit_cvtdq2pd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTDQ2PD_Vpd_Wq, dreg, sreg)
5199		#define emit_cvtdq2pd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTDQ2PD_Vpd_Wq, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5200		#define emit_cvtdq2pd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PD_Vpd_Wq, dreg, (base), REG_NONE, 1, (disp))
5201		#define emit_cvtdq2pd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PD_Vpd_Wq, dreg, REG_NONE, (index), (scale), (disp))
5202
5203		#define emit_cvtps2pd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPS2PD_Vpd_Wq, dreg, sreg)
5204		#define emit_cvtps2pd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPS2PD_Vpd_Wq, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5205		#define emit_cvtps2pd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPS2PD_Vpd_Wq, dreg, (base), REG_NONE, 1, (disp))
5206		#define emit_cvtps2pd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPS2PD_Vpd_Wq, dreg, REG_NONE, (index), (scale), (disp))
5207
5208		#define emit_cvtpd2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, sreg)
5209		#define emit_cvtpd2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5210		#define emit_cvtpd2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, (base), REG_NONE, 1, (disp))
5211		#define emit_cvtpd2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5212
5213		#define emit_cvttpd2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, sreg)
5214		#define emit_cvttpd2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
5215		#define emit_cvttpd2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, (base), REG_NONE, 1, (disp))
5216		#define emit_cvttpd2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, REG_NONE, (index), (scale), (disp))
5217		/***************************************************************************
5218
5219		x86emit.h
5220
5221		Generic x86/x64 code emitters.
5222
5223		Copyright (c) 1996-2007, Nicola Salmoria and the MAME Team.
5224		Visit http://mamedev.org for licensing and usage restrictions.
5225
5226		****************************************************************************
5227
5228		Important note:
5229
5230		It is assumed in 64-bit mode that all byte register accesses are
5231		intended to be to the low 8 bits (SPL,BPL,SIL,DIL) and not to the
5232		upper half (AH,CH,DH,BH).
5233
5234		***************************************************************************/
5235
5236
5237		/***************************************************************************
5238		CONSTANTS
5239		***************************************************************************/
5240
5241		/* 32-bit versus 64-bit opcode flag */
5242		#define OP_32BIT 0
5243		#define OP_64BIT 8
5244
5245
5246		/* 16 registers on x64, only 8 on x86 */
5247		#ifdef PTR64
5248		#define REG_MAX 16
5249		#else
5250		#define REG_MAX 8
5251		#endif
5252
5253
5254		/* invalid register index for "none" */
5255		#define REG_NONE REG_MAX
5256
5257
5258		/* 64-bit registers */
5259		#ifdef PTR64
5260		#define REG_RAX 0
5261		#define REG_RCX 1
5262		#define REG_RDX 2
5263		#define REG_RBX 3
5264		#define REG_RSP 4
5265		#define REG_RBP 5
5266		#define REG_RSI 6
5267		#define REG_RDI 7
5268		#define REG_R8 8
5269		#define REG_R9 9
5270		#define REG_R10 10
5271		#define REG_R11 11
5272		#define REG_R12 12
5273		#define REG_R13 13
5274		#define REG_R14 14
5275		#define REG_R15 15
5276		#endif
5277
5278		/* 32-bit registers */
5279		#define REG_EAX 0
5280		#define REG_ECX 1
5281		#define REG_EDX 2
5282		#define REG_EBX 3
5283		#define REG_ESP 4
5284		#define REG_EBP 5
5285		#define REG_ESI 6
5286		#define REG_EDI 7
5287		#ifdef PTR64
5288		#define REG_R8D 8
5289		#define REG_R9D 9
5290		#define REG_R10D 10
5291		#define REG_R11D 11
5292		#define REG_R12D 12
5293		#define REG_R13D 13
5294		#define REG_R14D 14
5295		#define REG_R15D 15
5296		#endif
5297
5298		/* 16-bit registers */
5299		#define REG_AX 0
5300		#define REG_CX 1
5301		#define REG_DX 2
5302		#define REG_BX 3
5303		#define REG_SP 4
5304		#define REG_BP 5
5305		#define REG_SI 6
5306		#define REG_DI 7
5307		#ifdef PTR64
5308		#define REG_R8W 8
5309		#define REG_R9W 9
5310		#define REG_R10W 10
5311		#define REG_R11W 11
5312		#define REG_R12W 12
5313		#define REG_R13W 13
5314		#define REG_R14W 14
5315		#define REG_R15W 15
5316		#endif
5317
5318		/* 8-bit registers */
5319		#define REG_AL 0
5320		#define REG_CL 1
5321		#define REG_DL 2
5322		#define REG_BL 3
5323		#ifndef PTR64
5324		#define REG_AH 4
5325		#define REG_CH 5
5326		#define REG_DH 6
5327		#define REG_BH 7
5328		#else
5329		#define REG_SPL 4
5330		#define REG_BPL 5
5331		#define REG_SIL 6
5332		#define REG_DIL 7
5333		#define REG_R8L 8
5334		#define REG_R9L 9
5335		#define REG_R10L 10
5336		#define REG_R11L 11
5337		#define REG_R12L 12
5338		#define REG_R13L 13
5339		#define REG_R14L 14
5340		#define REG_R15L 15
5341		#endif
5342
5343		/* 64-bit MMX registers */
5344		#define REG_MM0 0
5345		#define REG_MM1 1
5346		#define REG_MM2 2
5347		#define REG_MM3 3
5348		#define REG_MM4 4
5349		#define REG_MM5 5
5350		#define REG_MM6 6
5351		#define REG_MM7 7
5352		#ifdef PTR64
5353		#define REG_MM8 8
5354		#define REG_MM9 9
5355		#define REG_MM10 10
5356		#define REG_MM11 11
5357		#define REG_MM12 12
5358		#define REG_MM13 13
5359		#define REG_MM14 14
5360		#define REG_MM15 15
5361		#endif
5362
5363		/* 128-bit XMM registers */
5364		#define REG_XMM0 0
5365		#define REG_XMM1 1
5366		#define REG_XMM2 2
5367		#define REG_XMM3 3
5368		#define REG_XMM4 4
5369		#define REG_XMM5 5
5370		#define REG_XMM6 6
5371		#define REG_XMM7 7
5372		#ifdef PTR64
5373		#define REG_XMM8 8
5374		#define REG_XMM9 9
5375		#define REG_XMM10 10
5376		#define REG_XMM11 11
5377		#define REG_XMM12 12
5378		#define REG_XMM13 13
5379		#define REG_XMM14 14
5380		#define REG_XMM15 15
5381		#endif
5382
5383
5384		/* conditions */
5385		#define COND_A 7
5386		#define COND_AE 3
5387		#define COND_B 2
5388		#define COND_BE 6
5389		#define COND_C 2
5390		#define COND_E 4
5391		#define COND_Z 4
5392		#define COND_G 15
5393		#define COND_GE 13
5394		#define COND_L 12
5395		#define COND_LE 14
5396		#define COND_NA 6
5397		#define COND_NAE 2
5398		#define COND_NB 3
5399		#define COND_NBE 7
5400		#define COND_NC 3
5401		#define COND_NE 5
5402		#define COND_NG 14
5403		#define COND_NGE 12
5404		#define COND_NL 13
5405		#define COND_NLE 15
5406		#define COND_NO 1
5407		#define COND_NP 11
5408		#define COND_NS 9
5409		#define COND_NZ 5
5410		#define COND_O 0
5411		#define COND_P 10
5412		#define COND_PE 10
5413		#define COND_PO 11
5414		#define COND_S 8
5415		#define COND_Z 4
5416
5417
5418		/* floating point rounding modes */
5419		#define FPRND_NEAR 0
5420		#define FPRND_DOWN 1
5421		#define FPRND_UP 2
5422		#define FPRND_CHOP 3
5423
5424
5425		/* opcode flags (in upper 8 bits of opcode) */
5426		#define OPFLAG_8BITREG (1 << 24)
5427		#define OPFLAG_8BITRM (1 << 25)
5428
5429
5430		/* single byte opcodes */
5431		#define OP_ADD_Eb_Gb 0x00 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5432		#define OP_ADD_Ev_Gv 0x01
5433		#define OP_ADD_Gb_Eb 0x02 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5434		#define OP_ADD_Gv_Ev 0x03
5435		#define OP_ADD_AL_Ib 0x04
5436		#define OP_ADD_rAX_Iz 0x05
5437		#define OP_PUSH_ES 0x06
5438		#define OP_POP_ES 0x07
5439		#define OP_OR_Eb_Gb 0x08 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5440		#define OP_OR_Ev_Gv 0x09
5441		#define OP_OR_Gb_Eb 0x0a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5442		#define OP_OR_Gv_Ev 0x0b
5443		#define OP_OR_AL_Ib 0x0c
5444		#define OP_OR_eAX_Iv 0x0d
5445		#define OP_PUSH_CS 0x0e
5446		#define OP_EXTENDED 0x0f
5447
5448		#define OP_ADC_Eb_Gb 0x10 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5449		#define OP_ADC_Ev_Gv 0x11
5450		#define OP_ADC_Gb_Eb 0x12 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5451		#define OP_ADC_Gv_Ev 0x13
5452		#define OP_ADC_AL_Ib 0x14
5453		#define OP_ADC_rAX_Iz 0x15
5454		#define OP_PUSH_SS 0x16
5455		#define OP_POP_SS 0x17
5456		#define OP_SBB_Eb_Gb 0x18 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5457		#define OP_SBB_Ev_Gv 0x19
5458		#define OP_SBB_Gb_Eb 0x1a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5459		#define OP_SBB_Gv_Ev 0x1b
5460		#define OP_SBB_AL_Ib 0x1c
5461		#define OP_SBB_eAX_Iv 0x1d
5462		#define OP_PUSH_DS 0x1e
5463		#define OP_POP_DS 0x1f
5464
5465		#define OP_AND_Eb_Gb 0x20 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5466		#define OP_AND_Ev_Gv 0x21
5467		#define OP_AND_Gb_Eb 0x22 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5468		#define OP_AND_Gv_Ev 0x23
5469		#define OP_AND_AL_Ib 0x24
5470		#define OP_AND_rAX_Iz 0x25
5471		#define PREFIX_ES 0x26
5472		#define OP_DAA 0x27
5473		#define OP_SUB_Eb_Gb 0x28 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5474		#define OP_SUB_Ev_Gv 0x29
5475		#define OP_SUB_Gb_Eb 0x2a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5476		#define OP_SUB_Gv_Ev 0x2b
5477		#define OP_SUB_AL_Ib 0x2c
5478		#define OP_SUB_eAX_Iv 0x2d
5479		#define PREFIX_CS 0x2e
5480		#define OP_DAS 0x2f
5481
5482		#define OP_XOR_Eb_Gb 0x30 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5483		#define OP_XOR_Ev_Gv 0x31
5484		#define OP_XOR_Gb_Eb 0x32 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5485		#define OP_XOR_Gv_Ev 0x33
5486		#define OP_XOR_AL_Ib 0x34
5487		#define OP_XOR_rAX_Iz 0x35
5488		#define PREFIX_SS 0x36
5489		#define OP_AAA 0x37
5490		#define OP_CMP_Eb_Gb 0x38 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5491		#define OP_CMP_Ev_Gv 0x39
5492		#define OP_CMP_Gb_Eb 0x3a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5493		#define OP_CMP_Gv_Ev 0x3b
5494		#define OP_CMP_AL_Ib 0x3c
5495		#define OP_CMP_eAX_Iv 0x3d
5496		#define PREFIX_DS 0x3e
5497		#define OP_AAS 0x3f
5498
5499		#define OP_REX 0x40
5500		#define OP_REX_B 0x41
5501		#define OP_REX_X 0x42
5502		#define OP_REX_XB 0x43
5503		#define OP_REX_R 0x44
5504		#define OP_REX_RB 0x45
5505		#define OP_REX_RX 0x46
5506		#define OP_REX_RXB 0x47
5507		#define OP_REX_W 0x48
5508		#define OP_REX_WB 0x49
5509		#define OP_REX_WX 0x4a
5510		#define OP_REX_WXB 0x4b
5511		#define OP_REX_WR 0x4c
5512		#define OP_REX_WRB 0x4d
5513		#define OP_REX_WRX 0x4e
5514		#define OP_REX_WRXB 0x4f
5515
5516		#define OP_PUSH_rAX 0x50
5517		#define OP_PUSH_rCX 0x51
5518		#define OP_PUSH_rDX 0x52
5519		#define OP_PUSH_rBX 0x53
5520		#define OP_PUSH_rSP 0x54
5521		#define OP_PUSH_rBP 0x55
5522		#define OP_PUSH_rSI 0x56
5523		#define OP_PUSH_rDI 0x57
5524		#define OP_POP_rAX 0x58
5525		#define OP_POP_rCX 0x59
5526		#define OP_POP_rDX 0x5a
5527		#define OP_POP_rBX 0x5b
5528		#define OP_POP_rSP 0x5c
5529		#define OP_POP_rBP 0x5d
5530		#define OP_POP_rSI 0x5e
5531		#define OP_POP_rDI 0x5f
5532
5533		#define OP_PUSHA 0x60
5534		#define OP_POPA 0x61
5535		#define OP_BOUND_Gv_Ma 0x62
5536		#define OP_ARPL_Ew_Gw 0x63
5537		#define OP_MOVSXD_Gv_Ev 0x63
5538		#define PREFIX_FS 0x64
5539		#define PREFIX_GS 0x65
5540		#define PREFIX_OPSIZE 0x66
5541		#define PREFIX_ADSIZE 0x67
5542		#define OP_PUSH_Iz 0x68
5543		#define OP_IMUL_Gv_Ev_Iz 0x69
5544		#define OP_PUSH_Ib 0x6a
5545		#define OP_IMUL_Gv_Ev_Ib 0x6b
5546		#define OP_INS_Yb_DX 0x6c
5547		#define OP_INS_Yz_DX 0x6d
5548		#define OP_OUTS_DX_Xb 0x6e
5549		#define OP_OUTS_DX_Xz 0x6f
5550
5551		#define OP_JCC_O_Jb 0x70
5552		#define OP_JCC_NO_Jb 0x71
5553		#define OP_JCC_B_Jb 0x72
5554		#define OP_JCC_C_Jb 0x72
5555		#define OP_JCC_NAE_Jb 0x72
5556		#define OP_JCC_AE_Jb 0x73
5557		#define OP_JCC_NB_Jb 0x73
5558		#define OP_JCC_NC_Jb 0x73
5559		#define OP_JCC_E_Jb 0x74
5560		#define OP_JCC_Z_Jb 0x74
5561		#define OP_JCC_NE_Jb 0x75
5562		#define OP_JCC_NZ_Jb 0x75
5563		#define OP_JCC_BE_Jb 0x76
5564		#define OP_JCC_NA_Jb 0x76
5565		#define OP_JCC_A_Jb 0x77
5566		#define OP_JCC_NBE_Jb 0x77
5567		#define OP_JCC_S_Jb 0x78
5568		#define OP_JCC_NS_Jb 0x79
5569		#define OP_JCC_P_Jb 0x7a
5570		#define OP_JCC_PE_Jb 0x7a
5571		#define OP_JCC_NP_Jb 0x7b
5572		#define OP_JCC_PO_Jb 0x7b
5573		#define OP_JCC_L_Jb 0x7c
5574		#define OP_JCC_NGE_Jb 0x7c
5575		#define OP_JCC_NL_Jb 0x7d
5576		#define OP_JCC_GE_Jb 0x7d
5577		#define OP_JCC_LE_Jb 0x7e
5578		#define OP_JCC_NG_Jb 0x7e
5579		#define OP_JCC_NLE_Jb 0x7f
5580		#define OP_JCC_G_Jb 0x7f
5581
5582		#define OP_G1_Eb_Ib 0x80 \| OPFLAG_8BITRM
5583		#define OP_G1_Ev_Iz 0x81
5584		#define OP_G1_Eb_Ibx 0x82 \| OPFLAG_8BITRM
5585		#define OP_G1_Ev_Ib 0x83
5586		#define OP_TEST_Eb_Gb 0x84 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5587		#define OP_TEST_Ev_Gv 0x85
5588		#define OP_XCHG_Eb_Gb 0x86 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5589		#define OP_XCHG_Ev_Gv 0x87
5590		#define OP_MOV_Eb_Gb 0x88 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5591		#define OP_MOV_Ev_Gv 0x89
5592		#define OP_MOV_Gb_Eb 0x8a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
5593		#define OP_MOV_Gv_Ev 0x8b
5594		#define OP_MOV_Ev_Sw 0x8c
5595		#define OP_LEA_Gv_M 0x8d
5596		#define OP_MOV_Sw_Ew 0x8e
5597		#define OP_G1A_Ev 0x8f
5598
5599		#define OP_NOP 0x90
5600		#define OP_PAUSE 0x90
5601		#define OP_XCHG_rCX 0x91
5602		#define OP_XCHG_rDX 0x92
5603		#define OP_XCHG_rBX 0x93
5604		#define OP_XCHG_rSP 0x94
5605		#define OP_XCHG_rBP 0x95
5606		#define OP_XCHG_rSI 0x96
5607		#define OP_XCHG_rDI 0x97
5608		#define OP_CBW 0x98
5609		#define OP_CWDE 0x98
5610		#define OP_CDQE 0x98
5611		#define OP_CWD 0x99
5612		#define OP_CDQ 0x99
5613		#define OP_CQO 0x99
5614		#define OP_CALLF_Ap 0x9a
5615		#define OP_FWAIT 0x9b
5616		#define OP_PUSHF_Fv 0x9c
5617		#define OP_POPF_Fv 0x9d
5618		#define OP_SAHF 0x9e
5619		#define OP_LAHF 0x9f
5620
5621		#define OP_MOV_AL_Ob 0xa0
5622		#define OP_MOV_rAX_Ov 0xa1
5623		#define OP_MOV_Ob_AL 0xa2
5624		#define OP_MOV_Ov_rAX 0xa3
5625		#define OP_MOVS_Xb_Yb 0xa4
5626		#define OP_MOVS_Xv_Yv 0xa5
5627		#define OP_CMPS_Xb_Yb 0xa6
5628		#define OP_CMPS_Xv_Yv 0xa7
5629		#define OP_TEST_AL_Ib 0xa8
5630		#define OP_TEST_rAX_Iz 0xa9
5631		#define OP_STOS_Yb_AL 0xaa
5632		#define OP_STOS_Yv_rAX 0xab
5633		#define OP_LODS_AL_Xb 0xac
5634		#define OP_LODS_rAX_Xv 0xad
5635		#define OP_SCAS_AL_Yb 0xae
5636		#define OP_SCAC_rAX_Yv 0xaf
5637
5638		#define OP_MOV_AL_Ib 0xb0
5639		#define OP_MOV_CL_Ib 0xb1
5640		#define OP_MOV_DL_Ib 0xb2
5641		#define OP_MOV_BL_Ib 0xb3
5642		#define OP_MOV_AH_Ib 0xb4
5643		#define OP_MOV_CH_Ib 0xb5
5644		#define OP_MOV_DH_Ib 0xb6
5645		#define OP_MOV_BH_Ib 0xb7
5646		#define OP_MOV_rAX_Iv 0xb8
5647		#define OP_MOV_rCX_Iv 0xb9
5648		#define OP_MOV_rDX_Iv 0xba
5649		#define OP_MOV_rBX_Iv 0xbb
5650		#define OP_MOV_rSP_Iv 0xbc
5651		#define OP_MOV_rBP_Iv 0xbd
5652		#define OP_MOV_rSI_Iv 0xbe
5653		#define OP_MOV_rDI_Iv 0xbf
5654
5655		#define OP_G2_Eb_Ib 0xc0 \| OPFLAG_8BITRM
5656		#define OP_G2_Ev_Ib 0xc1
5657		#define OP_RETN_Iw 0xc2
5658		#define OP_RETN 0xc3
5659		#define OP_LES_Gz_Mp 0xc4
5660		#define OP_LDS_Gz_Mp 0xc5
5661		#define OP_G11_Eb_Ib 0xc6 \| OPFLAG_8BITRM
5662		#define OP_G11_Ev_Iz 0xc7
5663		#define OP_ENTER_Iw_Ib 0xc8
5664		#define OP_LEAVE 0xc9
5665		#define OP_RETF_Iw 0xca
5666		#define OP_RETF 0xcb
5667		#define OP_INT_3 0xcc
5668		#define OP_INT_Ib 0xcd
5669		#define OP_INTO 0xce
5670		#define OP_IRET 0xcf
5671
5672		#define OP_G2_Eb_1 0xd0 \| OPFLAG_8BITRM
5673		#define OP_G2_Ev_1 0xd1
5674		#define OP_G2_Eb_CL 0xd2 \| OPFLAG_8BITRM
5675		#define OP_G2_Ev_CL 0xd3
5676		#define OP_AAM 0xd4
5677		#define OP_AAD 0xd5
5678		#define OP_XLAT 0xd7
5679		#define OP_ESC_D8 0xd8
5680		#define OP_ESC_D9 0xd9
5681		#define OP_ESC_DA 0xda
5682		#define OP_ESC_DB 0xdb
5683		#define OP_ESC_DC 0xdc
5684		#define OP_ESC_DD 0xdd
5685		#define OP_ESC_DE 0xde
5686		#define OP_ESC_DF 0xdf
5687
5688		#define OP_LOOPNE_Jb 0xe0
5689		#define OP_LOOPE_Jb 0xe1
5690		#define OP_LOOP_Jb 0xe2
5691		#define OP_JrCXZ_Jb 0xe3
5692		#define OP_IN_AL_Ib 0xe4
5693		#define OP_IN_eAX_Ib 0xe5
5694		#define OP_OUT_Ib_AL 0xe6
5695		#define OP_OUT_Ib_eAX 0xe7
5696		#define OP_CALL_Jz 0xe8
5697		#define OP_JMP_Jz 0xe9
5698		#define OP_JMPF_AP 0xea
5699		#define OP_JMP_Jb 0xeb
5700		#define OP_IN_AL_DX 0xec
5701		#define OP_IN_eAX_D 0xed
5702		#define OP_OUT_DX_AL 0xee
5703		#define OP_OUT_DX_eAX 0xef
5704
5705		#define PREFIX_LOCK 0xf0
5706		#define PREFIX_REPNE 0xf2
5707		#define PREFIX_REPE 0xf3
5708		#define OP_HLT 0xf4
5709		#define OP_CMC 0xf5
5710		#define OP_G3_Eb 0xf6 \| OPFLAG_8BITRM
5711		#define OP_G3_Ev 0xf7
5712		#define OP_CLC 0xf8
5713		#define OP_STC 0xf9
5714		#define OP_CLI 0xfa
5715		#define OP_STI 0xfb
5716		#define OP_CLD 0xfc
5717		#define OP_STD 0xfd
5718		#define OP_G4 0xfe
5719		#define OP_G5 0xff
5720
5721
5722		/* double byte opcodes */
5723		#define OP_G6 0x0f00
5724		#define OP_G7 0x0f01
5725		#define OP_LAR_Gv_Ew 0x0f02
5726		#define OP_LSL_Gv_Ew 0x0f03
5727		#define OP_SYSCALL 0x0f05
5728		#define OP_CLTS 0x0f06
5729		#define OP_SYSRET 0x0f07
5730		#define OP_INVD 0x0f08
5731		#define OP_WBINVD 0x0f09
5732		#define OP_UD2 0x0f0b
5733
5734		#define OP_MOVUPS_Vps_Wps 0x0f10
5735		#define OP_MOVSS_Vss_Wss 0xf30f10
5736		#define OP_MOVUPD_Vpd_Wpd 0x660f10
5737		#define OP_MOVSD_Vsd_Wsd 0xf20f10
5738		#define OP_MOVUPS_Wps_Vps 0x0f11
5739		#define OP_MOVSS_Wss_Vss 0xf30f11
5740		#define OP_MOVUPD_Wpd_Vpd 0x660f11
5741		#define OP_MOVSD_Wsd_Vsd 0xf20f11
5742		#define OP_MOVLPS_Vq_Mq 0x0f12
5743		#define OP_MOVLPD_Vq_Mq 0x660f12
5744		#define OP_MOVHLPS_Vq_Uq 0x0f12
5745		#define OP_MOVDDUP_Vq_Wq 0xf20f12
5746		#define OP_MOVSLDUP_Vq_Wq 0xf30f12
5747		#define OP_MOVLPS_Mq_Vq 0x0f13
5748		#define OP_MOVLPD_Mq_Vq 0x660f13
5749		#define OP_UNPCKLPS_Vps_Wq 0x0f14
5750		#define OP_UNPCKLPD_Vpd_Wq 0x660f14
5751		#define OP_UNPCKHPS_Vps_Wq 0x0f15
5752		#define OP_UNPCKHPD_Vpd_Wq 0x660f15
5753		#define OP_MOVHPS_Vq_Mq 0x0f16
5754		#define OP_MOVHPD_Vq_Mq 0x660f16
5755		#define OP_MOVLHPS_Vq_Uq 0x0f16
5756		#define OP_MOVSHDUP_Vq_Wq 0xf30f16
5757		#define OP_MOVHPS_Mq_Vq 0x0f17
5758		#define OP_MOVHPD_Mq_Vq 0x660f17
5759		#define OP_PREFETCH_G16 0x0f18
5760
5761		#define OP_MOV_Rd_Cd 0x0f20
5762		#define OP_MOV_Rd_Dd 0x0f21
5763		#define OP_MOV_Cd_Rd 0x0f22
5764		#define OP_MOV_Dd_Rd 0x0f23
5765		#define OP_MOVAPS_Vps_Wps 0x0f28
5766		#define OP_MOVAPD_Vpd_Wpd 0x660f28
5767		#define OP_MOVAPS_Wps_Vps 0x0f29
5768		#define OP_MOVAPD_Wpd_Vpd 0x660f29
5769		#define OP_CVTPI2PS_Vps_Qq 0x0f2a
5770		#define OP_CVTSI2SS_Vss_Ed 0xf30f2a
5771		#define OP_CVTPI2PD_Vpd_Qq 0x660f2a
5772		#define OP_CVTSI2SD_Vsd_Ed 0xf20f2a
5773		#define OP_MOVNTPS_Mps_Vps 0x0f2b
5774		#define OP_MOVNTPD_Mpd_Vpd 0x660f2b
5775		#define OP_CVTTPS2PI_Pq_Wq 0x0f2c
5776		#define OP_CVTTSS2SI_Gd_Wss 0xf30f2c
5777		#define OP_CVTTPD2PI_Pq_Wpd 0x660f2c
5778		#define OP_CVTTSD2SI_Gd_Wsd 0xf20f2c
5779		#define OP_CVTPS2PI_Pq_Wq 0x0f2d
5780		#define OP_CVTSS2SI_Gd_Wss 0xf30f2d
5781		#define OP_CVTPD2PI_Pq_Wpd 0x660f2d
5782		#define OP_CVTSD2SI_Gd_Wsd 0xf20f2d
5783		#define OP_UCOMISS_Vss_Wss 0x0f2e
5784		#define OP_UCOMISD_Vsd_Wsd 0x660f2e
5785		#define OP_COMISS_Vss_Wss 0x0f2f
5786		#define OP_COMISD_Vsd_Wsd 0x660f2f
5787
5788		#define OP_WRMSR 0x0f30
5789		#define OP_RDTSC 0x0f31
5790		#define OP_RDMSR 0x0f32
5791		#define OP_RDPMC 0x0f33
5792		#define OP_SYSENTER 0x0f34
5793		#define OP_SYSEXIT 0x0f35
5794
5795		#define OP_CMOV_O_Gv_Ev 0x0f40
5796		#define OP_CMOV_NO_Gv_Ev 0x0f41
5797		#define OP_CMOV_B_Gv_Ev 0x0f42
5798		#define OP_CMOV_C_Gv_Ev 0x0f42
5799		#define OP_CMOV_AE_Gv_Ev 0x0f43
5800		#define OP_CMOV_NC_Gv_Ev 0x0f43
5801		#define OP_CMOV_E_Gv_Ev 0x0f44
5802		#define OP_CMOV_Z_Gv_Ev 0x0f44
5803		#define OP_CMOV_NE_Gv_Ev 0x0f45
5804		#define OP_CMOV_NZ_Gv_Ev 0x0f45
5805		#define OP_CMOV_BE_Gv_Ev 0x0f46
5806		#define OP_CMOV_A_Gv_Ev 0x0f47
5807		#define OP_CMOV_S_Gv_Ev 0x0f48
5808		#define OP_CMOV_NS_Gv_Ev 0x0f49
5809		#define OP_CMOV_P_Gv_Ev 0x0f4a
5810		#define OP_CMOV_PE_Gv_Ev 0x0f4a
5811		#define OP_CMOV_NP_Gv_Ev 0x0f4b
5812		#define OP_CMOV_PO_Gv_Ev 0x0f4b
5813		#define OP_CMOV_L_Gv_Ev 0x0f4c
5814		#define OP_CMOV_NGE_Gv_Ev 0x0f4c
5815		#define OP_CMOV_NL_Gv_Ev 0x0f4d
5816		#define OP_CMOV_GE_Gv_Ev 0x0f4d
5817		#define OP_CMOV_LE_Gv_Ev 0x0f4e
5818		#define OP_CMOV_NG_Gv_Ev 0x0f4e
5819		#define OP_CMOV_NLE_Gv_Ev 0x0f4f
5820		#define OP_CMOV_G_Gv_Ev 0x0f4f
5821
5822		#define OP_MOVMSKPS_Gd_Ups 0x0f50
5823		#define OP_MOVMSKPD_Gd_Upd 0x660f50
5824		#define OP_SQRTPS_Vps_Wps 0x0f51
5825		#define OP_SQRTSS_Vss_Wss 0xf30f51
5826		#define OP_SQRTPD_Vpd_Wpd 0x660f51
5827		#define OP_SQRTSD_Vsd_Wsd 0xf20f51
5828		#define OP_RSQRTPS_Vps_Wps 0x0f52
5829		#define OP_RSQRTSS_Vss_Wss 0xf30f52
5830		#define OP_RCPPS_Vps_Wps 0x0f53
5831		#define OP_RCPSS_Vss_Wss 0xf30f53
5832		#define OP_ANDPS_Vps_Wps 0x0f54
5833		#define OP_ANDPD_Vpd_Wpd 0x660f54
5834		#define OP_ANDNPS_Vps_Wps 0x0f55
5835		#define OP_ANDNPD_Vpd_Wpd 0x660f55
5836		#define OP_ORPS_Vps_Wps 0x0f56
5837		#define OP_ORPD_Vpd_Wpd 0x660f56
5838		#define OP_XORPS_Vps_Wps 0x0f57
5839		#define OP_XORPD_Vpd_Wpd 0x660f57
5840		#define OP_ADDPS_Vps_Wps 0x0f58
5841		#define OP_ADDSS_Vss_Wss 0xf30f58
5842		#define OP_ADDPD_Vpd_Wpd 0x660f58
5843		#define OP_ADDSD_Vsd_Wsd 0xf20f58
5844		#define OP_MULPS_Vps_Wps 0x0f59
5845		#define OP_MULSS_Vss_Wss 0xf30f59
5846		#define OP_MULPD_Vpd_Wpd 0x660f59
5847		#define OP_MULSD_Vsd_Wsd 0xf20f59
5848		#define OP_CVTPS2PD_Vpd_Wq 0x0f5a
5849		#define OP_CVTSS2SD_Vsd_Wss 0xf30f5a
5850		#define OP_CVTPD2PS_Vps_Wpd 0x660f5a
5851		#define OP_CVTSD2SS_Vss_Wsd 0xf20f5a
5852		#define OP_CVTDQ2PS_Vps_Wdq 0x0f5b
5853		#define OP_CVTPS2DQ_Vdq_Wps 0x660f5b
5854		#define OP_CVTTPS2DQ_Vdq_Wps 0xf30f5b
5855		#define OP_SUBPS_Vps_Wps 0x0f5c
5856		#define OP_SUBSS_Vss_Wss 0xf30f5c
5857		#define OP_SUBPD_Vpd_Wpd 0x660f5c
5858		#define OP_SUBSD_Vsd_Wsd 0xf20f5c
5859		#define OP_MINPS_Vps_Wps 0x0f5d
5860		#define OP_MINSS_Vss_Wss 0xf30f5d
5861		#define OP_MINPD_Vpd_Wpd 0x660f5d
5862		#define OP_MINSD_Vsd_Wsd 0xf20f5d
5863		#define OP_DIVPS_Vps_Wps 0x0f5e
5864		#define OP_DIVSS_Vss_Wss 0xf30f5e
5865		#define OP_DIVPD_Vpd_Wpd 0x660f5e
5866		#define OP_DIVSD_Vsd_Wsd 0xf20f5e
5867		#define OP_MAXPS_Vps_Wps 0x0f5f
5868		#define OP_MAXSS_Vss_Wss 0xf30f5f
5869		#define OP_MAXPD_Vpd_Wpd 0x660f5f
5870		#define OP_MAXSD_Vsd_Wsd 0xf20f5f
5871
5872		#define OP_PUNPCKLBW_Pq_Qd 0x0f60
5873		#define OP_PUNPCKLBW_Vdq_Wdq 0x660f60
5874		#define OP_PUNPCKLWD_Pq_Qd 0x0f61
5875		#define OP_PUNPCKLWD_Vdq_Wdq 0x660f61
5876		#define OP_PUNPCKLDQ_Pq_Qd 0x0f62
5877		#define OP_PUNPCKLDQ_Vdq_Wdq 0x660f62
5878		#define OP_PACKSSWB_Pq_Qq 0x0f63
5879		#define OP_PACKSSWB_Vdq_Wdq 0x660f63
5880		#define OP_PCMPGTB_Pq_Qq 0x0f64
5881		#define OP_PCMPGTB_Vdq_Wdq 0x660f64
5882		#define OP_PCMPGTW_Pq_Qq 0x0f65
5883		#define OP_PCMPGTW_Vdq_Wdq 0x660f65
5884		#define OP_PCMPGTD_Pq_Qq 0x0f66
5885		#define OP_PCMPGTD_Vdq_Wdq 0x660f66
5886		#define OP_PACKUSWB_Pq_Qq 0x0f67
5887		#define OP_PACKUSWB_Vdq_Wdq 0x660f67
5888		#define OP_PUNPCKHBW_Pq_Qq 0x0f68
5889		#define OP_PUNPCKHBW_Vdq_Qdq 0x660f68
5890		#define OP_PUNPCKHWD_Pq_Qq 0x0f69
5891		#define OP_PUNPCKHWD_Vdq_Qdq 0x660f69
5892		#define OP_PUNPCKHDQ_Pq_Qq 0x0f6a
5893		#define OP_PUNPCKHDQ_Vdq_Qdq 0x660f6a
5894		#define OP_PACKSSDW_Pq_Qq 0x0f6b
5895		#define OP_PACKSSDW_Vdq_Qdq 0x660f6b
5896		#define OP_PUNPCKLQDQ_Vdq_Wdq 0x660f6c
5897		#define OP_PUNPCKHQDQ_Vdq_Wdq 0x660f6d
5898		#define OP_MOVD_Pd_Ed 0x0f6e
5899		#define OP_MOVD_Vd_Ed 0x660f6e
5900		#define OP_MOVQ_Pq_Qq 0x0f6f
5901		#define OP_MOVDQA_Vdq_Wdq 0x660f6f
5902		#define OP_MOVDQU_Vdq_Wdq 0xf30f6f
5903
5904		#define OP_PSHUFW_Pq_Qq_Ib 0x0f70
5905		#define OP_PSHUFD_Vdq_Wdq_Ib 0x660f70
5906		#define OP_PSHUFHW_Vdq_Wdq_Ib 0xf30f70
5907		#define OP_PSHUFLW_Vdq_Wdq_Ib 0xf20f70
5908		#define OP_G12 0x0f71
5909		#define OP_G13 0x0f72
5910		#define OP_G14 0x0f73
5911		#define OP_PCMPEQB_Pq_Qq 0x0f74
5912		#define OP_PCMPEQB_Vdq_Wdq 0x660f74
5913		#define OP_PCMPEQW_Pq_Qq 0x0f75
5914		#define OP_PCMPEQW_Vdq_Wdq 0x660f75
5915		#define OP_PCMPEQD_Pq_Qq 0x0f76
5916		#define OP_PCMPEQD_Vdq_Wdq 0x660f76
5917		#define OP_EMMS 0x0f77
5918		#define OP_HADDPD_Vpd_Wpd 0x660f7c
5919		#define OP_HADDPS_Vps_Wps 0xf20f7c
5920		#define OP_HSUBPD_Vpd_Wpd 0x660f7d
5921		#define OP_HSUBPS_Vps_Wps 0xf20f7d
5922		#define OP_MOVD_Ed_Pd 0x0f7e
5923		#define OP_MOVD_Ed_Vd 0x660f7e
5924		#define OP_MOVQ_Vq_Wq 0xf30f7e
5925		#define OP_MOVQ_Qq_Pq 0x0f7f
5926		#define OP_MOVDQA_Wdq_Vdq 0x660f7f
5927		#define OP_MOVDQU_Wdq_Vdq 0xf30f7f
5928
5929		#define OP_JCC_O_Jv 0x0f80
5930		#define OP_JCC_NO_Jv 0x0f81
5931		#define OP_JCC_B_Jv 0x0f82
5932		#define OP_JCC_C_Jv 0x0f82
5933		#define OP_JCC_NAE_Jv 0x0f82
5934		#define OP_JCC_AE_Jv 0x0f83
5935		#define OP_JCC_NB_Jv 0x0f83
5936		#define OP_JCC_NC_Jv 0x0f83
5937		#define OP_JCC_E_Jv 0x0f84
5938		#define OP_JCC_Z_Jv 0x0f84
5939		#define OP_JCC_NE_Jv 0x0f85
5940		#define OP_JCC_NZ_Jv 0x0f85
5941		#define OP_JCC_BE_Jv 0x0f86
5942		#define OP_JCC_NA_Jv 0x0f86
5943		#define OP_JCC_A_Jv 0x0f87
5944		#define OP_JCC_NBE_Jv 0x0f87
5945		#define OP_JCC_S_Jv 0x0f88
5946		#define OP_JCC_NS_Jv 0x0f89
5947		#define OP_JCC_P_Jv 0x0f8a
5948		#define OP_JCC_PE_Jv 0x0f8a
5949		#define OP_JCC_NP_Jv 0x0f8b
5950		#define OP_JCC_PO_Jv 0x0f8b
5951		#define OP_JCC_L_Jv 0x0f8c
5952		#define OP_JCC_NGE_Jv 0x0f8c
5953		#define OP_JCC_NL_Jv 0x0f8d
5954		#define OP_JCC_GE_Jv 0x0f8d
5955		#define OP_JCC_LE_Jv 0x0f8e
5956		#define OP_JCC_NG_Jv 0x0f8e
5957		#define OP_JCC_NLE_Jv 0x0f8f
5958		#define OP_JCC_G_Jv 0x0f8f
5959
5960		#define OP_SETCC_O_Eb 0x0f90 \| OPFLAG_8BITRM
5961		#define OP_SETCC_NO_Eb 0x0f91 \| OPFLAG_8BITRM
5962		#define OP_SETCC_B_Eb 0x0f92 \| OPFLAG_8BITRM
5963		#define OP_SETCC_C_Eb 0x0f92 \| OPFLAG_8BITRM
5964		#define OP_SETCC_NAE_Eb 0x0f92 \| OPFLAG_8BITRM
5965		#define OP_SETCC_AE_Eb 0x0f93 \| OPFLAG_8BITRM
5966		#define OP_SETCC_NB_Eb 0x0f93 \| OPFLAG_8BITRM
5967		#define OP_SETCC_NC_Eb 0x0f93 \| OPFLAG_8BITRM
5968		#define OP_SETCC_E_Eb 0x0f94 \| OPFLAG_8BITRM
5969		#define OP_SETCC_Z_Eb 0x0f94 \| OPFLAG_8BITRM
5970		#define OP_SETCC_NE_Eb 0x0f95 \| OPFLAG_8BITRM
5971		#define OP_SETCC_NZ_Eb 0x0f95 \| OPFLAG_8BITRM
5972		#define OP_SETCC_BE_Eb 0x0f96 \| OPFLAG_8BITRM
5973		#define OP_SETCC_NA_Eb 0x0f96 \| OPFLAG_8BITRM
5974		#define OP_SETCC_A_Eb 0x0f97 \| OPFLAG_8BITRM
5975		#define OP_SETCC_NBE_Eb 0x0f97 \| OPFLAG_8BITRM
5976		#define OP_SETCC_S_Eb 0x0f98 \| OPFLAG_8BITRM
5977		#define OP_SETCC_NS_Eb 0x0f99 \| OPFLAG_8BITRM
5978		#define OP_SETCC_P_Eb 0x0f9a \| OPFLAG_8BITRM
5979		#define OP_SETCC_PE_Eb 0x0f9a \| OPFLAG_8BITRM
5980		#define OP_SETCC_NP_Eb 0x0f9b \| OPFLAG_8BITRM
5981		#define OP_SETCC_PO_Eb 0x0f9b \| OPFLAG_8BITRM
5982		#define OP_SETCC_L_Eb 0x0f9c \| OPFLAG_8BITRM
5983		#define OP_SETCC_NGE_Eb 0x0f9c \| OPFLAG_8BITRM
5984		#define OP_SETCC_NL_Eb 0x0f9d \| OPFLAG_8BITRM
5985		#define OP_SETCC_GE_Eb 0x0f9d \| OPFLAG_8BITRM
5986		#define OP_SETCC_LE_Eb 0x0f9e \| OPFLAG_8BITRM
5987		#define OP_SETCC_NG_Eb 0x0f9e \| OPFLAG_8BITRM
5988		#define OP_SETCC_NLE_Eb 0x0f9f \| OPFLAG_8BITRM
5989		#define OP_SETCC_G_Eb 0x0f9f \| OPFLAG_8BITRM
5990
5991		#define OP_PUSH_FS 0x0fa0
5992		#define OP_POP_FS 0x0fa1
5993		#define OP_CPUID 0x0fa2
5994		#define OP_BT_Ev_Gv 0x0fa3
5995		#define OP_SHLD_Ev_Gv_Ib 0x0fa4
5996		#define OP_SHLD_Ev_Gv_CL 0x0fa5
5997		#define OP_PUSH_GS 0x0fa8
5998		#define OP_POP_GS 0x0fa9
5999		#define OP_RSM 0x0faa
6000		#define OP_BTS_Ev_Gv 0x0fab
6001		#define OP_SHRD_Ev_Gv_Ib 0x0fac
6002		#define OP_SHRD_Ev_Gv_CL 0x0fad
6003		#define OP_G16 0x0fae
6004		#define OP_IMUL_Gv_Ev 0x0faf
6005
6006		#define OP_CMPXCHG_Eb_Gb 0x0fb0 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
6007		#define OP_CMPXCHG_Ev_Gv 0x0fb1
6008		#define OP_LSS_Mp 0x0fb2
6009		#define OP_BTR_Ev_Gv 0x0fb3
6010		#define OP_LFS_Mp 0x0fb4
6011		#define OP_LGS_Mp 0x0fb5
6012		#define OP_MOVZX_Gv_Eb 0x0fb6 \| OPFLAG_8BITRM
6013		#define OP_MOVZX_Gv_Ew 0x0fb7
6014		#define OP_G10_INVALID 0x0fb9
6015		#define OP_G8_Ev_Ib 0x0fba
6016		#define OP_BTC_Ev_Gv 0x0fbb
6017		#define OP_BSF_Gv_Ev 0x0fbc
6018		#define OP_BSR_Gv_Ev 0x0fbd
6019		#define OP_MOVSX_Gv_Eb 0x0fbe \| OPFLAG_8BITRM
6020		#define OP_MOVSX_Gv_Ew 0x0fbf
6021
6022		#define OP_XADD_Eb_Gb 0x0fc0 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
6023		#define OP_XADD_Ev_Gv 0x0fc1
6024		#define OP_CMPPS_Vps_Wps_Ib 0x0fc2
6025		#define OP_CMPSS_Vss_Wss_Ib 0xf30fc2
6026		#define OP_CMPPD_Vpd_Wpd_Ib 0x660fc2
6027		#define OP_CMPSD_Vsd_Wsd_Ib 0xf20fc2
6028		#define OP_MOVNTI_Md_Gd 0x0fc3
6029		#define OP_PINSRW_Pw_Ew_Ib 0x0fc4
6030		#define OP_PINSRW_Vw_Ew_Ib 0x660fc4
6031		#define OP_PEXTRW_Gw_Pw_Ib 0x0fc5
6032		#define OP_PEXTRW_Gw_Vw_Ib 0x660fc5
6033		#define OP_SHUFPS_Vps_Wps_Ib 0x0fc6
6034		#define OP_SHUFPD_Vpd_Wpd_Ib 0x660fc6
6035		#define OP_G9 0x0fc7
6036		#define OP_BSWAP_EAX 0x0fc8
6037		#define OP_BSWAP_ECX 0x0fc9
6038		#define OP_BSWAP_EDX 0x0fca
6039		#define OP_BSWAP_EBX 0x0fcb
6040		#define OP_BSWAP_ESP 0x0fcc
6041		#define OP_BSWAP_EBP 0x0fcd
6042		#define OP_BSWAP_ESI 0x0fce
6043		#define OP_BSWAP_EDI 0x0fcf
6044
6045		#define OP_ADDSUBPD_Vpd_Wpd 0x0fd0
6046		#define OP_ADDSUBPS_Vps_Wps 0xf20fd0
6047		#define OP_PSRLW_Pq_Qq 0x0fd1
6048		#define OP_PSRLW_Vdq_Wdq 0x660fd1
6049		#define OP_PSRLD_Pq_Qq 0x0fd2
6050		#define OP_PSRLD_Vdq_Wdq 0x660fd2
6051		#define OP_PSRLQ_Pq_Qq 0x0fd3
6052		#define OP_PSRLQ_Vdq_Wdq 0x660fd3
6053		#define OP_PADDQ_Pq_Qq 0x0fd4
6054		#define OP_PADDQ_Vdq_Wdq 0x660fd4
6055		#define OP_PMULLW_Pq_Qq 0x0fd5
6056		#define OP_PMULLW_Vdq_Wdq 0x660fd5
6057		#define OP_MOVQ_Wq_Vq 0x0fd6
6058		#define OP_MOVQ2DQ_Vdq_Qq 0xf30fd6
6059		#define OP_MOVDQ2Q_Pq_Vq 0xf20fd6
6060		#define OP_PMOVMSKB_Gd_Pq 0x0fd7
6061		#define OP_PMOVMSKB_Gd_Vdq 0x660fd7
6062		#define OP_PSUBUSB_Pq_Qq 0x0fd8
6063		#define OP_PSUBUSB_Vdq_Wdq 0x660fd8
6064		#define OP_PSUBUSW_Pq_Qq 0x0fd9
6065		#define OP_PSUBUSW_Vdq_Wdq 0x660fd9
6066		#define OP_PMINUB_Pq_Qq 0x0fda
6067		#define OP_PMINUB_Vdq_Wdq 0x660fda
6068		#define OP_PAND_Pq_Qq 0x0fdb
6069		#define OP_PAND_Vdq_Wdq 0x660fdb
6070		#define OP_PADDUSB_Pq_Qq 0x0fdc
6071		#define OP_PADDUSB_Vdq_Wdq 0x660fdc
6072		#define OP_PADDUSW_Pq_Qq 0x0fdd
6073		#define OP_PADDUSW_Vdq_Wdq 0x660fdd
6074		#define OP_PMAXUB_Pq_Qq 0x0fde
6075		#define OP_PMAXUB_Vdq_Wdq 0x660fde
6076		#define OP_PANDN_Pq_Qq 0x0fdf
6077		#define OP_PANDN_Vdq_Wdq 0x660fdf
6078
6079		#define OP_PAVGB_Pq_Qq 0x0fe0
6080		#define OP_PAVGB_Vdq_Wdq 0x660fe0
6081		#define OP_PSRAW_Pq_Qq 0x0fe1
6082		#define OP_PSRAW_Vdq_Wdq 0x660fe1
6083		#define OP_PSRAD_Pq_Qq 0x0fe2
6084		#define OP_PSRAD_Vdq_Wdq 0x660fe2
6085		#define OP_PAVGW_Pq_Qq 0x0fe3
6086		#define OP_PAVGW_Vdq_Wdq 0x660fe3
6087		#define OP_PMULHUW_Pq_Qq 0x0fe4
6088		#define OP_PMULHUW_Vdq_Wdq 0x660fe4
6089		#define OP_PMULHW_Pq_Qq 0x0fe5
6090		#define OP_PMULHW_Vdq_Wdq 0x660fe5
6091		#define OP_CVTPD2DQ_Vdq_Wpd 0xf20fe6
6092		#define OP_CVTTPD2DQ_Vdq_Wpd 0x660fe6
6093		#define OP_CVTDQ2PD_Vpd_Wq 0xf30fe6
6094		#define OP_MOVNTQ_Mq_Vq 0x0fe7
6095		#define OP_MOVNTDQ_Mdq_Vdq 0x660fe7
6096		#define OP_PSUBSB_Pq_Qq 0x0fe8
6097		#define OP_PSUBSB_Vdq_Wdq 0x660fe8
6098		#define OP_PSUBSW_Pq_Qq 0x0fe9
6099		#define OP_PSUBSW_Vdq_Wdq 0x660fe9
6100		#define OP_PMINSW_Pq_Qq 0x0fea
6101		#define OP_PMINSW_Vdq_Wdq 0x660fea
6102		#define OP_POR_Pq_Qq 0x0feb
6103		#define OP_POR_Vdq_Wdq 0x660feb
6104		#define OP_PADDSB_Pq_Qq 0x0fec
6105		#define OP_PADDSB_Vdq_Wdq 0x660fec
6106		#define OP_PADDSW_Pq_Qq 0x0fed
6107		#define OP_PADDSW_Vdq_Wdq 0x660fed
6108		#define OP_PMAXSW_Pq_Qq 0x0fee
6109		#define OP_PMAXSW_Vdq_Wdq 0x660fee
6110		#define OP_PXOR_Pq_Qq 0x0fef
6111		#define OP_PXOR_Vdq_Wdq 0x660fef
6112
6113		#define OP_LDDQU_Vdq_Mdq 0xf20ff0
6114		#define OP_PSLLW_Pq_Qq 0x0ff1
6115		#define OP_PSLLW_Vdq_Wdq 0x660ff1
6116		#define OP_PSLLD_Pq_Qq 0x0ff2
6117		#define OP_PSLLD_Vdq_Wdq 0x660ff2
6118		#define OP_PSLLQ_Pq_Qq 0x0ff3
6119		#define OP_PSLLQ_Vdq_Wdq 0x660ff3
6120		#define OP_PMULUDQ_Pq_Qq 0x0ff4
6121		#define OP_PMULUDQ_Vdq_Wdq 0x660ff4
6122		#define OP_PMADDWD_Pq_Qq 0x0ff5
6123		#define OP_PMADDWD_Vdq_Wdq 0x660ff5
6124		#define OP_PSADBW_Pq_Qq 0x0ff6
6125		#define OP_PSADBW_Vdq_Wdq 0x660ff6
6126		#define OP_MASKMOVQ_Pq_Qq 0x0ff7
6127		#define OP_MASKMOVDQU_Vdq_Wdq 0x660ff7
6128		#define OP_PSUBB_Pq_Qq 0x0ff8
6129		#define OP_PSUBB_Vdq_Wdq 0x660ff8
6130		#define OP_PSUBW_Pq_Qq 0x0ff9
6131		#define OP_PSUBW_Vdq_Wdq 0x660ff9
6132		#define OP_PSUBD_Pq_Qq 0x0ffa
6133		#define OP_PSUBD_Vdq_Wdq 0x660ffa
6134		#define OP_PSUBQ_Pq_Qq 0x0ffb
6135		#define OP_PSUBQ_Vdq_Wdq 0x660ffb
6136		#define OP_PADDB_Pq_Qq 0x0ffc
6137		#define OP_PADDB_Vdq_Wdq 0x660ffc
6138		#define OP_PADDW_Pq_Qq 0x0ffd
6139		#define OP_PADDW_Vdq_Wdq 0x660ffd
6140		#define OP_PADDD_Pq_Qq 0x0ffe
6141		#define OP_PADDD_Vdq_Wdq 0x660ffe
6142
6143
6144
6145		/***************************************************************************
6146		TYPE DEFINITIONS
6147		***************************************************************************/
6148
6149		typedef UINT8 x86code;
6150
6151
6152		typedef struct _emit_link emit_link;
6153		struct _emit_link
6154		{
6155		x86code * target;
6156		UINT8 size;
6157		};
6158
6159
6160
6161		/***************************************************************************
6162		CORE FUNCTIONS
6163		***************************************************************************/
6164
6165		/*-------------------------------------------------
6166		make_modrm - assemble a modrm byte from the
6167		three components
6168		-------------------------------------------------*/
6169
6170		INLINE UINT8 make_modrm(UINT8 mode, UINT8 reg, UINT8 rm)
6171		{
6172		assert(mode < 4);
6173		assert(reg < REG_MAX);
6174		assert(rm < REG_MAX);
6175		return (mode << 6) \| ((reg & 7) << 3) \| (rm & 7);
6176		}
6177
6178
6179		/*-------------------------------------------------
6180		make_sib - assemble an sib byte from the
6181		three components
6182		-------------------------------------------------*/
6183
6184		INLINE UINT8 make_sib(UINT8 scale, UINT8 index, UINT8 base)
6185		{
6186		static const UINT8 scale_lookup[9] = { 0<<6, 0<<6, 1<<6, 0<<6, 2<<6, 0<<6, 0<<6, 0<<6, 3<<6 };
6187		assert(scale == 1 \|\| scale == 2 \|\| scale == 4 \|\| scale == 8);
6188		assert(index < REG_MAX);
6189		assert(base < REG_MAX);
6190		return scale_lookup[scale] \| ((index & 7) << 3) \| (base & 7);
6191		}
6192
6193
6194		/*-------------------------------------------------
6195		emit_byte - emit a byte
6196		-------------------------------------------------*/
6197
6198		INLINE void emit_byte(x86code **emitptr, UINT8 byte)
6199		{
6200		((UINT8 )*emitptr) = byte;
6201		*emitptr += 1;
6202		}
6203
6204
6205		/*-------------------------------------------------
6206		emit_word - emit a word
6207		-------------------------------------------------*/
6208
6209		INLINE void emit_word(x86code **emitptr, UINT16 word)
6210		{
6211		((UINT16 )*emitptr) = word;
6212		*emitptr += 2;
6213		}
6214
6215
6216		/*-------------------------------------------------
6217		emit_dword - emit a dword
6218		-------------------------------------------------*/
6219
6220		INLINE void emit_dword(x86code **emitptr, UINT32 dword)
6221		{
6222		((UINT32 )*emitptr) = dword;
6223		*emitptr += 4;
6224		}
6225
6226
6227		/*-------------------------------------------------
6228		emit_qword - emit a dword
6229		-------------------------------------------------*/
6230
6231		INLINE void emit_qword(x86code **emitptr, UINT64 qword)
6232		{
6233		((UINT64 )*emitptr) = qword;
6234		*emitptr += 8;
6235		}
6236
6237
6238
6239		/***************************************************************************
6240		GENERIC OPCODE EMITTERS
6241		***************************************************************************/
6242
6243		/*-------------------------------------------------
6244		emit_op - emit a 1, 2, or 3-byte opcode,
6245		along with any necessary REX prefixes for x64
6246		-------------------------------------------------*/
6247
6248		INLINE void emit_op(x86code **emitptr, UINT32 op, UINT8 op64, UINT8 reg, UINT8 sib, UINT8 rm)
6249		{
6250		#ifdef PTR64
6251		UINT8 rex;
6252
6253		assert(op64 == OP_32BIT \|\| op64 == OP_64BIT);
6254
6255		rex = op64 \| ((reg & 8) >> 1) \| ((sib & 8) >> 2) \| ((rm & 8) >> 3);
6256		if (rex != 0 \|\| ((op & OPFLAG_8BITREG) && reg >= 4) \|\| ((op & OPFLAG_8BITRM) && rm >= 4))
6257		emit_byte(emitptr, rex \| 0x40);
6258		#else
6259		assert(op64 == OP_32BIT);
6260		#endif
6261
6262		if ((op & 0xff0000) != 0)
6263		emit_byte(emitptr, op >> 16);
6264		if ((op & 0xff00) != 0)
6265		emit_byte(emitptr, op >> 8);
6266		emit_byte(emitptr, op);
6267		}
6268
6269
6270		/*-------------------------------------------------
6271		emit_op_simple - emit a simple opcode
6272		-------------------------------------------------*/
6273
6274		INLINE void emit_op_simple(x86code **emitptr, UINT32 op, UINT8 op64)
6275		{
6276		emit_op(emitptr, op, op64, 0, 0, 0);
6277		}
6278
6279
6280		/*-------------------------------------------------
6281		emit_op_modrm_reg - emit an opcode with a
6282		register modrm byte
6283		-------------------------------------------------*/
6284
6285		INLINE void emit_op_modrm_reg(x86code **emitptr, UINT32 op, UINT8 op64, UINT8 reg, UINT8 rm)
6286		{
6287		assert(reg < REG_MAX);
6288		assert(rm < REG_MAX);
6289
6290		emit_op(emitptr, op, op64, reg, 0, rm);
6291		emit_byte(emitptr, make_modrm(3, reg, rm));
6292		}
6293
6294
6295		/*-------------------------------------------------
6296		emit_op_modrm_mem - emit an opcode with a
6297		memory modrm byte
6298		-------------------------------------------------*/
6299
6300		INLINE void emit_op_modrm_mem(x86code **emitptr, UINT32 op, UINT8 op64, UINT8 reg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6301		{
6302		assert(reg < REG_MAX);
6303		assert(base < REG_MAX \|\| base == REG_NONE);
6304		assert(index < REG_MAX \|\| index == REG_NONE);
6305
6306		/* turn off the OPFLAG_8BITRM flag since it only applies to register operands */
6307		op &= ~OPFLAG_8BITRM;
6308
6309		/* displacement only case */
6310		if (base == REG_NONE && index == REG_NONE)
6311		{
6312		#ifndef PTR64
6313		emit_op(emitptr, op, op64, reg, 0, rm);
6314		emit_byte(emitptr, make_modrm(0, reg, 5));
6315		emit_dword(emitptr, disp);
6316		#else
6317		fatalerror("Invalid absolute mode in 64-bits!\n");
6318		#endif
6319		}
6320
6321		/* base only case */
6322		else if (index == REG_NONE && base != REG_ESP)
6323		{
6324		emit_op(emitptr, op, op64, reg, 0, base);
6325
6326		/* mode 0 for no offset */
6327		if (disp == 0 && base != REG_EBP)
6328		emit_byte(emitptr, make_modrm(0, reg, base));
6329
6330		/* mode 1 for 1-byte offset */
6331		else if ((INT8)disp == disp)
6332		{
6333		emit_byte(emitptr, make_modrm(1, reg, base));
6334		emit_byte(emitptr, (INT8)disp);
6335		}
6336
6337		/* mode 2 for 4-byte offset */
6338		else
6339		{
6340		emit_byte(emitptr, make_modrm(2, reg, base));
6341		emit_dword(emitptr, disp);
6342		}
6343		}
6344
6345		/* full BISD case */
6346		else
6347		{
6348		assert(index != REG_ESP);
6349		emit_op(emitptr, op, op64, reg, index, base);
6350
6351		/* a "none" index == REG_ESP */
6352		if (index == REG_NONE)
6353		index = REG_ESP;
6354
6355		/* mode 0 for no offset */
6356		if (disp == 0 && base != REG_EBP)
6357		{
6358		emit_byte(emitptr, make_modrm(0, reg, 4));
6359		emit_byte(emitptr, make_sib(scale, index, (base == REG_NONE) ? REG_EBP : base));
6360		if (base == REG_NONE)
6361		emit_dword(emitptr, disp);
6362		}
6363
6364		/* mode 1 for 1-byte offset */
6365		else if ((INT8)disp == disp)
6366		{
6367		emit_byte(emitptr, make_modrm(1, reg, 4));
6368		emit_byte(emitptr, make_sib(scale, index, base));
6369		emit_byte(emitptr, (INT8)disp);
6370		}
6371
6372		/* mode 2 for 4-byte offset */
6373		else
6374		{
6375		emit_byte(emitptr, make_modrm(2, reg, 4));
6376		emit_byte(emitptr, make_sib(scale, index, base));
6377		emit_dword(emitptr, disp);
6378		}
6379		}
6380		}
6381
6382
6383
6384		/***************************************************************************
6385		SIMPLE OPCODE EMITTERS
6386		***************************************************************************/
6387
6388		INLINE void emit_nop(x86code **emitptr)
6389		{
6390		emit_byte(emitptr, OP_NOP);
6391		}
6392
6393		INLINE void emit_int_3(x86code **emitptr)
6394		{
6395		emit_byte(emitptr, OP_INT_3);
6396		}
6397
6398		INLINE void emit_ret(x86code **emitptr)
6399		{
6400		emit_byte(emitptr, OP_RETN);
6401		}
6402
6403		INLINE void emit_cdq(x86code **emitptr)
6404		{
6405		emit_byte(emitptr, OP_CDQ);
6406		}
6407
6408		#ifdef PTR64
6409		INLINE void emit_cqo(x86code **emitptr)
6410		{
6411		emit_byte(emitptr, OP_REX_W);
6412		emit_byte(emitptr, OP_CQO);
6413		}
6414		#endif
6415
6416
6417
6418		/***************************************************************************
6419	1472	CALL/JUMP EMITTERS
6420	1473	***************************************************************************/
6421	1474
r949	r950
6445	1498	}
6446	1499
6447	1500
6448		/*-------------------------------------------------~~-----------------~~
	1501	/*-------------------------------------------------
6449	1502	emit_call_*
6450		-------------------------------------------------~~-----------------~~*/
	1503	-------------------------------------------------*/
6451	1504
6452	1505	INLINE void emit_call_link(x86code *emitptr, emit_link linkinfo)
6453	1506	{
r949	r950
6460	1513	INLINE void emit_call(x86code *emitptr, x86code target)
6461	1514	{
6462	1515	emit_link link;
6463
6464	1516	emit_call_link(emitptr, &link);
6465	1517	resolve_link(&target, &link);
6466	1518	}
6467	1519
6468	1520
6469		/*------------------------------------------------------------------
6470		emit_call_r32_*
6471		------------------------------------------------------------------*/
6472
6473		#ifndef PTR64
6474
6475		INLINE void emit_call_r32(x86code **emitptr, UINT8 dreg)
6476		{
6477		emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 2, dreg);
6478		}
6479
6480		INLINE void emit_call_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6481		{
6482		emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 2, base, index, scale, disp);
6483		}
6484
6485		#define emit_call_m32abs(e, addr) emit_call_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
6486		#define emit_call_m32bd(e, base, disp) emit_call_m32bisd(e, (base), REG_NONE, 1, (disp))
6487		#define emit_call_m32isd(e, index, scale, disp) emit_call_m32bisd(e, REG_NONE, (index), (scale), (disp))
6488
6489		#endif
6490
6491
6492		/*------------------------------------------------------------------
6493		emit_call_r64_*
6494		------------------------------------------------------------------*/
6495
6496		#ifdef PTR64
6497
6498		INLINE void emit_call_r64(x86code **emitptr, UINT8 dreg)
6499		{
6500		emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 2, dreg);
6501		}
6502
6503		INLINE void emit_call_m64bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6504		{
6505		emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 2, base, index, scale, disp);
6506		}
6507
6508		#define emit_call_m64abs(e, addr) emit_call_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
6509		#define emit_call_m64bd(e, base, disp) emit_call_m64bisd(e, (base), REG_NONE, 1, (disp))
6510		#define emit_call_m64isd(e, index, scale, disp) emit_call_m64bisd(e, REG_NONE, (index), (scale), (disp))
6511
6512		#endif
6513
6514
6515		/*------------------------------------------------------------------
	1521	/*-------------------------------------------------
6516	1522	emit_jmp_*
6517		-------------------------------------------------~~-----------------~~*/
	1523	-------------------------------------------------*/
6518	1524
6519	1525	INLINE void emit_jmp_short_link(x86code *emitptr, emit_link linkinfo)
6520	1526	{
r949	r950
6545	1551	}
6546	1552
6547	1553
6548		/*-------------------------------------------------~~-----------------~~
	1554	/*-------------------------------------------------
6549	1555	emit_jcc_*
6550		-------------------------------------------------~~-----------------~~*/
	1556	-------------------------------------------------*/
6551	1557
6552		INLINE void emit_jcc_short_link(x86code *emitptr, UINT8 cond~~ition~~, emit_link linkinfo)
	1558	INLINE void emit_jcc_short_link(x86code *emitptr, UINT8 cond, emit_link linkinfo)
6553	1559	{
6554		emit_op_simple(emitptr, OP_JCC_O_Jb + cond~~ition~~, OP_32BIT);
	1560	emit_op_simple(emitptr, OP_JCC_O_Jb + cond, OP_32BIT);
6555	1561	emit_byte(emitptr, 0);
6556	1562	linkinfo->target = *emitptr;
6557	1563	linkinfo->size = 1;
6558	1564	}
6559	1565
6560		INLINE void emit_jcc_near_link(x86code *emitptr, UINT8 cond~~ition~~, emit_link linkinfo)
	1566	INLINE void emit_jcc_near_link(x86code *emitptr, UINT8 cond, emit_link linkinfo)
6561	1567	{
6562		emit_op_simple(emitptr, OP_JCC_O_Jv + cond~~ition~~, OP_32BIT);
	1568	emit_op_simple(emitptr, OP_JCC_O_Jv + cond, OP_32BIT);
6563	1569	emit_dword(emitptr, 0);
6564	1570	linkinfo->target = *emitptr;
6565	1571	linkinfo->size = 4;
6566	1572	}
6567	1573
6568		INLINE void emit_jcc(x86code *emitptr, UINT8 cond~~ition~~, x86code target)
	1574	INLINE void emit_jcc(x86code *emitptr, UINT8 cond, x86code target)
6569	1575	{
6570	1576	INT32 delta = *emitptr + 2 - target;
6571	1577	emit_link link;
6572	1578
6573	1579	if ((INT8)delta == delta)
6574		emit_jcc_short_link(emitptr, cond~~ition~~, &link);
	1580	emit_jcc_short_link(emitptr, cond, &link);
6575	1581	else
6576		emit_jcc_near_link(emitptr, cond~~ition~~, &link);
	1582	emit_jcc_near_link(emitptr, cond, &link);
6577	1583	resolve_link(&target, &link);
6578	1584	}
6579	1585
6580	1586
6581		/*------------------------------------------------------------------
6582		emit_jmp_r32_*
6583		------------------------------------------------------------------*/
	1587	/*-------------------------------------------------
	1588	emit_call/jmp_*
	1589	-------------------------------------------------*/
6584	1590
6585	1591	#ifndef PTR64
6586
6587		INLINE void emit_jmp_r32(x86code **emitptr, UINT8 dreg)
6588		{
6589		emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 4, dreg);
6590		}
6591
6592		INLINE void emit_jmp_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6593		{
6594		emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 4, base, index, scale, disp);
6595		}
6596
6597		#define emit_jmp_m32abs(e, addr) emit_jmp_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
6598		#define emit_jmp_m32bd(e, base, disp) emit_jmp_m32bisd(e, (base), REG_NONE, 1, (disp))
6599		#define emit_jmp_m32isd(e, index, scale, disp) emit_jmp_m32bisd(e, REG_NONE, (index), (scale), (disp))
6600
	1592	INLINE void emit_call_r32(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 2, dreg); }
	1593	INLINE void emit_call_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 2, MEMPARAMS); }
	1594	INLINE void emit_jmp_r32(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 4, dreg); }
	1595	INLINE void emit_jmp_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 4, MEMPARAMS); }
	1596	#else
	1597	INLINE void emit_call_r64(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 2, dreg); }
	1598	INLINE void emit_call_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 2, MEMPARAMS); }
	1599	INLINE void emit_jmp_r64(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 4, dreg); }
	1600	INLINE void emit_jmp_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 4, MEMPARAMS); }
6601	1601	#endif
6602	1602
6603	1603
6604		/*------------------------------------------------------------------
6605		emit_jmp_r64_*
6606		------------------------------------------------------------------*/
6607	1604
6608		#ifdef PTR64
	1605	/***************************************************************************
	1606	PUSH/POP EMITTERS
	1607	***************************************************************************/
6609	1608
6610		INLINE void emit_jmp_~~r64~~(x86code **emitptr, UINT8 ~~dreg~~)
	1609	INLINE void emit_push_imm(x86code **emitptr, INT32 imm)
6611	1610	{
6612		emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 4, dreg);
	1611	if ((INT8)imm == imm)
	1612	{
	1613	emit_op_simple(emitptr, OP_PUSH_Ib, OP_32BIT);
	1614	emit_byte(emitptr, (INT8)imm);
	1615	}
	1616	else
	1617	{
	1618	emit_op_simple(emitptr, OP_PUSH_Iz, OP_32BIT);
	1619	emit_dword(emitptr, imm);
	1620	}
6613	1621	}
6614	1622
6615		INLINE void emit_jmp_m64bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6616		{
6617		emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 4, base, index, scale, disp);
6618		}
	1623	#ifndef PTR64
6619	1624
6620		#define emit_jmp_m64abs(e, addr) emit_jmp_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
6621		#define emit_jmp_m64bd(e, base, disp) emit_jmp_m64bisd(e, (base), REG_NONE, 1, (disp))
6622		#define emit_jmp_m64isd(e, index, scale, disp) emit_jmp_m64bisd(e, REG_NONE, (index), (scale), (disp))
	1625	INLINE void emit_push_r32(x86code **emitptr, UINT8 reg) { emit_op_reg(emitptr, OP_PUSH_rAX + (reg & 7), OP_32BIT, reg); }
	1626	INLINE void emit_push_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 6, MEMPARAMS); }
	1627	INLINE void emit_pop_r32(x86code **emitptr, UINT8 reg) { emit_op_reg(emitptr, OP_POP_rAX + (reg & 7), OP_32BIT, reg); }
	1628	INLINE void emit_pop_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G1A_Ev, OP_32BIT, 0, MEMPARAMS); }
6623	1629
	1630	#else
	1631
	1632	INLINE void emit_push_r64(x86code **emitptr, UINT8 reg) { emit_op_reg(emitptr, OP_PUSH_rAX + (reg & 7), OP_32BIT, reg); }
	1633	INLINE void emit_push_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 6, MEMPARAMS); }
	1634	INLINE void emit_pop_r64(x86code **emitptr, UINT8 reg) { emit_op_reg(emitptr, OP_POP_rAX + (reg & 7), OP_32BIT, reg); }
	1635	INLINE void emit_pop_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G1A_Ev, OP_32BIT, 0, MEMPARAMS); }
	1636
6624	1637	#endif
6625	1638
6626	1639
r949	r950
6629	1642	MOVE EMITTERS
6630	1643	***************************************************************************/
6631	1644
6632		/*-------------------------------------------------~~-----------------~~
	1645	/*-------------------------------------------------
6633	1646	emit_mov_r8_*
6634		-------------------------------------------------~~-----------------~~*/
	1647	-------------------------------------------------*/
6635	1648
6636	1649	INLINE void emit_mov_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm)
6637	1650	{
6638		emit_op(emitptr, OP_MOV_AL_Ib \| (dreg & 7), OP_32BIT~~, 0, 0~~, dreg);
	1651	emit_op_reg(emitptr, OP_MOV_AL_Ib \| (dreg & 7), OP_32BIT, dreg);
6639	1652	emit_byte(emitptr, imm);
6640	1653	}
6641	1654
6642		INLINE void emit_mov_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
6643		{
6644		emit_op_modrm_reg(emitptr, OP_MOV_Gb_Eb, OP_32BIT, dreg, sreg);
6645		}
	1655	INLINE void emit_mov_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOV_Gb_Eb, OP_32BIT, dreg, sreg); }
	1656	INLINE void emit_mov_r8_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOV_Gb_Eb, OP_32BIT, dreg, MEMPARAMS); }
	1657	INLINE void emit_mov_m8_r8(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_MOV_Eb_Gb, OP_32BIT, sreg, MEMPARAMS); }
	1658	INLINE void emit_mov_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G11_Eb_Ib, OP_32BIT, 0, MEMPARAMS, imm); }
6646	1659
6647		INLINE void emit_mov_r8_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6648		{
6649		emit_op_modrm_mem(emitptr, OP_MOV_Gb_Eb, OP_32BIT, dreg, base, index, scale, disp);
6650		}
6651	1660
6652		INLINE void emit_mov_m8bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
6653		{
6654		emit_op_modrm_mem(emitptr, OP_G11_Eb_Ib, OP_32BIT, 0, base, index, scale, disp);
6655		emit_byte(emitptr, imm);
6656		}
6657
6658		INLINE void emit_mov_m8bisd_r8(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
6659		{
6660		emit_op_modrm_mem(emitptr, OP_MOV_Eb_Gb, OP_32BIT, sreg, base, index, scale, disp);
6661		}
6662
6663		#define emit_mov_r8_m8abs(e, dreg, addr) emit_mov_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6664		#define emit_mov_r8_m8bd(e, dreg, base, disp) emit_mov_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
6665		#define emit_mov_r8_m8isd(e, dreg, index, scale, disp) emit_mov_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
6666
6667		#define emit_mov_m8abs_r8(e, addr, sreg) emit_mov_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
6668		#define emit_mov_m8bd_r8(e, base, disp, sreg) emit_mov_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
6669		#define emit_mov_m8isd_r8(e, index, scale, disp, sreg) emit_mov_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
6670
6671		#define emit_mov_m8abs_imm(e, addr, imm) emit_mov_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
6672		#define emit_mov_m8bd_imm(e, base, disp, imm) emit_mov_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
6673		#define emit_mov_m8isd_imm(e, index, scale, disp, imm) emit_mov_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
6674
6675
6676		/*------------------------------------------------------------------
	1661	/*-------------------------------------------------
6677	1662	emit_mov_r16_*
6678		-------------------------------------------------~~-----------------~~*/
	1663	-------------------------------------------------*/
6679	1664
6680	1665	INLINE void emit_mov_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm)
6681	1666	{
6682		emit_byte(emitptr, PREFIX_OPSIZE);
6683		emit_op(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_32BIT, 0, 0, dreg);
	1667	emit_op_reg(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_16BIT, dreg);
6684	1668	emit_word(emitptr, imm);
6685	1669	}
6686	1670
6687		INLINE void emit_mov_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
6688		{
6689		emit_byte(emitptr, PREFIX_OPSIZE);
6690		emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, sreg);
6691		}
	1671	INLINE void emit_mov_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_16BIT, dreg, sreg); }
	1672	INLINE void emit_mov_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
	1673	INLINE void emit_mov_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT16 imm) { emit_op_modrm_mem_imm16(emitptr, OP_G11_Ev_Iz, OP_16BIT, 0, MEMPARAMS, imm); }
	1674	INLINE void emit_mov_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
	1675	INLINE void emit_movsx_r16_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_16BIT, dreg, sreg); }
	1676	INLINE void emit_movsx_r16_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_16BIT, dreg, MEMPARAMS); }
	1677	INLINE void emit_movzx_r16_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_16BIT, dreg, sreg); }
	1678	INLINE void emit_movzx_r16_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_16BIT, dreg, MEMPARAMS); }
	1679	INLINE void emit_cmovcc_r16_r16(x86code **emitptr, UINT8 cond, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + cond, OP_16BIT, dreg, sreg); }
	1680	INLINE void emit_cmovcc_r16_m16(x86code **emitptr, UINT8 cond, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + cond, OP_16BIT, dreg, MEMPARAMS); }
6692	1681
6693		INLINE void emit_mov_r16_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6694		{
6695		emit_byte(emitptr, PREFIX_OPSIZE);
6696		emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, base, index, scale, disp);
6697		}
6698	1682
6699		INLINE void emit_mov_m16bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT16 imm)
6700		{
6701		emit_byte(emitptr, PREFIX_OPSIZE);
6702		emit_op_modrm_mem(emitptr, OP_G11_Ev_Iz, OP_32BIT, 0, base, index, scale, disp);
6703		emit_word(emitptr, imm);
6704		}
6705
6706		INLINE void emit_mov_m16bisd_r16(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
6707		{
6708		emit_byte(emitptr, PREFIX_OPSIZE);
6709		emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
6710		}
6711
6712		INLINE void emit_cmovcc_r16_r16(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 sreg)
6713		{
6714		emit_byte(emitptr, PREFIX_OPSIZE);
6715		emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, sreg);
6716		}
6717
6718		INLINE void emit_cmovcc_r16_m16bisd(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6719		{
6720		emit_byte(emitptr, PREFIX_OPSIZE);
6721		emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, base, index, scale, disp);
6722		}
6723
6724		#define emit_mov_r16_m16abs(e, dreg, addr) emit_mov_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6725		#define emit_mov_r16_m16bd(e, dreg, base, disp) emit_mov_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
6726		#define emit_mov_r16_m16isd(e, dreg, index, scale, disp) emit_mov_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
6727
6728		#define emit_mov_m16abs_r16(e, addr, sreg) emit_mov_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
6729		#define emit_mov_m16bd_r16(e, base, disp, sreg) emit_mov_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
6730		#define emit_mov_m16isd_r16(e, index, scale, disp, sreg) emit_mov_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
6731
6732		#define emit_mov_m16abs_imm(e, addr, imm) emit_mov_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
6733		#define emit_mov_m16bd_imm(e, base, disp, imm) emit_mov_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
6734		#define emit_mov_m16isd_imm(e, index, scale, disp, imm) emit_mov_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
6735
6736		#define emit_cmovcc_r16_m16abs(e, cond, dreg, addr) emit_cmovcc_r16_m16bisd(e, cond, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6737		#define emit_cmovcc_r16_m16bd(e, cond, dreg, base, disp) emit_cmovcc_r16_m16bisd(e, cond, dreg, (base), REG_NONE, 1, (disp))
6738		#define emit_cmovcc_r16_m16isd(e, cond, dreg, index, scale, disp) emit_cmovcc_r16_m16bisd(e, cond, dreg, REG_NONE, (index), (scale), (disp))
6739
6740
6741		/*------------------------------------------------------------------
	1683	/*-------------------------------------------------
6742	1684	emit_mov_r32_*
6743		-------------------------------------------------~~-----------------~~*/
	1685	-------------------------------------------------*/
6744	1686
6745	1687	INLINE void emit_mov_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm)
6746	1688	{
6747		emit_op(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_32BIT~~, 0, 0~~, dreg);
	1689	emit_op_reg(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_32BIT, dreg);
6748	1690	emit_dword(emitptr, imm);
6749	1691	}
6750	1692
6751		INLINE void emit_mov_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg)
6752		{
6753		emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, sreg);
6754		}
	1693	INLINE void emit_mov_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, sreg); }
	1694	INLINE void emit_mov_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
	1695	INLINE void emit_mov_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm32(emitptr, OP_G11_Ev_Iz, OP_32BIT, 0, MEMPARAMS, imm); }
	1696	INLINE void emit_mov_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
	1697	INLINE void emit_movsx_r32_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, sreg); }
	1698	INLINE void emit_movsx_r32_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, MEMPARAMS); }
	1699	INLINE void emit_movsx_r32_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Ew, OP_32BIT, dreg, sreg); }
	1700	INLINE void emit_movsx_r32_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Ew, OP_32BIT, dreg, MEMPARAMS); }
	1701	INLINE void emit_movzx_r32_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, sreg); }
	1702	INLINE void emit_movzx_r32_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, MEMPARAMS); }
	1703	INLINE void emit_movzx_r32_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Ew, OP_32BIT, dreg, sreg); }
	1704	INLINE void emit_movzx_r32_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Ew, OP_32BIT, dreg, MEMPARAMS); }
	1705	INLINE void emit_cmovcc_r32_r32(x86code **emitptr, UINT8 cond, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + cond, OP_32BIT, dreg, sreg); }
	1706	INLINE void emit_cmovcc_r32_m32(x86code **emitptr, UINT8 cond, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + cond, OP_32BIT, dreg, MEMPARAMS); }
6755	1707
6756		INLINE void emit_mov_r32_m32bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6757		{
6758		emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, base, index, scale, disp);
6759		}
6760	1708
6761		INLINE void emit_mov_m32bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
6762		{
6763		emit_op_modrm_mem(emitptr, OP_G11_Ev_Iz, OP_32BIT, 0, base, index, scale, disp);
6764		emit_dword(emitptr, imm);
6765		}
6766
6767		INLINE void emit_mov_m32bisd_r32(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
6768		{
6769		emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
6770		}
6771
6772		INLINE void emit_cmovcc_r32_r32(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 sreg)
6773		{
6774		emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, sreg);
6775		}
6776
6777		INLINE void emit_cmovcc_r32_m32bisd(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6778		{
6779		emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, base, index, scale, disp);
6780		}
6781
6782		#define emit_mov_r32_m32abs(e, dreg, addr) emit_mov_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6783		#define emit_mov_r32_m32bd(e, dreg, base, disp) emit_mov_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
6784		#define emit_mov_r32_m32isd(e, dreg, index, scale, disp) emit_mov_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
6785
6786		#define emit_mov_m32abs_r32(e, addr, sreg) emit_mov_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
6787		#define emit_mov_m32bd_r32(e, base, disp, sreg) emit_mov_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
6788		#define emit_mov_m32isd_r32(e, index, scale, disp, sreg) emit_mov_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
6789
6790		#define emit_mov_m32abs_imm(e, addr, imm) emit_mov_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
6791		#define emit_mov_m32bd_imm(e, base, disp, imm) emit_mov_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
6792		#define emit_mov_m32isd_imm(e, index, scale, disp, imm) emit_mov_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
6793
6794		#define emit_cmovcc_r32_m32abs(e, cond, dreg, addr) emit_cmovcc_r32_m32bisd(e, cond, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6795		#define emit_cmovcc_r32_m32bd(e, cond, dreg, base, disp) emit_cmovcc_r32_m32bisd(e, cond, dreg, (base), REG_NONE, 1, (disp))
6796		#define emit_cmovcc_r32_m32isd(e, cond, dreg, index, scale, disp) emit_cmovcc_r32_m32bisd(e, cond, dreg, REG_NONE, (index), (scale), (disp))
6797
6798
6799		/*------------------------------------------------------------------
	1709	/*-------------------------------------------------
6800	1710	emit_mov_r64_*
6801		-------------------------------------------------~~-----------------~~*/
	1711	-------------------------------------------------*/
6802	1712
6803	1713	#ifdef PTR64
6804	1714
6805	1715	INLINE void emit_mov_r64_imm(x86code **emitptr, UINT8 dreg, UINT64 imm)
6806	1716	{
6807		emit_op(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_64BIT, 0, 0, dreg);
6808		emit_qword(emitptr, imm);
6809		}
6810
6811		INLINE void emit_mov_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg)
6812		{
6813		emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_64BIT, dreg, sreg);
6814		}
6815
6816		INLINE void emit_mov_r64_m64bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6817		{
6818		emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_64BIT, dreg, base, index, scale, disp);
6819		}
6820
6821		INLINE void emit_mov_m64bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT64 imm)
6822		{
6823		assert((INT32)imm == (INT64)imm);
6824		emit_op_modrm_mem(emitptr, OP_G11_Ev_Iz, OP_64BIT, 0, base, index, scale, disp);
6825		emit_dword(emitptr, (INT32)imm);
6826		}
6827
6828		INLINE void emit_mov_m64bisd_r64(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
6829		{
6830		emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_64BIT, sreg, base, index, scale, disp);
6831		}
6832
6833		INLINE void emit_cmovcc_r64_r64(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 sreg)
6834		{
6835		emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_64BIT, dreg, sreg);
6836		}
6837
6838		INLINE void emit_cmovcc_r64_m64bisd(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6839		{
6840		emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_64BIT, dreg, base, index, scale, disp);
6841		}
6842
6843		#define emit_mov_r64_m64abs(e, dreg, addr) emit_mov_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6844		#define emit_mov_r64_m64bd(e, dreg, base, disp) emit_mov_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
6845		#define emit_mov_r64_m64isd(e, dreg, index, scale, disp) emit_mov_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
6846
6847		#define emit_mov_m64abs_r64(e, addr, sreg) emit_mov_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
6848		#define emit_mov_m64bd_r64(e, base, disp, sreg) emit_mov_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
6849		#define emit_mov_m64isd_r64(e, index, scale, disp, sreg) emit_mov_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
6850
6851		#define emit_mov_m64abs_imm(e, addr, imm) emit_mov_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
6852		#define emit_mov_m64bd_imm(e, base, disp, imm) emit_mov_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
6853		#define emit_mov_m64isd_imm(e, index, scale, disp, imm) emit_mov_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
6854
6855		#define emit_cmovcc_r64_m64abs(e, cond, dreg, addr) emit_cmovcc_r64_m64bisd(e, cond, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6856		#define emit_cmovcc_r64_m64bd(e, cond, dreg, base, disp) emit_cmovcc_r64_m64bisd(e, cond, dreg, (base), REG_NONE, 1, (disp))
6857		#define emit_cmovcc_r64_m64isd(e, cond, dreg, index, scale, disp) emit_cmovcc_r64_m64bisd(e, cond, dreg, REG_NONE, (index), (scale), (disp))
6858
6859		#endif
6860
6861
6862
6863		/***************************************************************************
6864		MOVE EXTENDED EMITTERS
6865		***************************************************************************/
6866
6867		/*------------------------------------------------------------------
6868		emit_movsx_r16_*
6869		------------------------------------------------------------------*/
6870
6871		INLINE void emit_movsx_r16_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
6872		{
6873		emit_byte(emitptr, PREFIX_OPSIZE);
6874		emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, sreg);
6875		}
6876
6877		INLINE void emit_movsx_r16_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6878		{
6879		emit_byte(emitptr, PREFIX_OPSIZE);
6880		emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
6881		}
6882
6883		#define emit_movsx_r16_m8abs(e, dreg, addr) emit_movsx_r16_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6884		#define emit_movsx_r16_m8bd(e, dreg, base, disp) emit_movsx_r16_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
6885		#define emit_movsx_r16_m8isd(e, dreg, index, scale, disp) emit_movsx_r16_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
6886
6887
6888		/*------------------------------------------------------------------
6889		emit_movzx_r16_*
6890		------------------------------------------------------------------*/
6891
6892		INLINE void emit_movzx_r16_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
6893		{
6894		emit_byte(emitptr, PREFIX_OPSIZE);
6895		emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, sreg);
6896		}
6897
6898		INLINE void emit_movzx_r16_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6899		{
6900		emit_byte(emitptr, PREFIX_OPSIZE);
6901		emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
6902		}
6903
6904		#define emit_movzx_r16_m8abs(e, dreg, addr) emit_movzx_r16_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6905		#define emit_movzx_r16_m8bd(e, dreg, base, disp) emit_movzx_r16_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
6906		#define emit_movzx_r16_m8isd(e, dreg, index, scale, disp) emit_movzx_r16_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
6907
6908
6909		/*------------------------------------------------------------------
6910		emit_movsx_r32_*
6911		------------------------------------------------------------------*/
6912
6913		INLINE void emit_movsx_r32_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
6914		{
6915		emit_byte(emitptr, PREFIX_OPSIZE);
6916		emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, sreg);
6917		}
6918
6919		INLINE void emit_movsx_r32_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6920		{
6921		emit_byte(emitptr, PREFIX_OPSIZE);
6922		emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
6923		}
6924
6925		INLINE void emit_movsx_r32_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
6926		{
6927		emit_byte(emitptr, PREFIX_OPSIZE);
6928		emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Ew, OP_32BIT, dreg, sreg);
6929		}
6930
6931		INLINE void emit_movsx_r32_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6932		{
6933		emit_byte(emitptr, PREFIX_OPSIZE);
6934		emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Ew, OP_32BIT, dreg, base, index, scale, disp);
6935		}
6936
6937		#define emit_movsx_r32_m8abs(e, dreg, addr) emit_movsx_r32_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6938		#define emit_movsx_r32_m8bd(e, dreg, base, disp) emit_movsx_r32_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
6939		#define emit_movsx_r32_m8isd(e, dreg, index, scale, disp) emit_movsx_r32_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
6940
6941		#define emit_movsx_r32_m16abs(e, dreg, addr) emit_movsx_r32_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6942		#define emit_movsx_r32_m16bd(e, dreg, base, disp) emit_movsx_r32_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
6943		#define emit_movsx_r32_m16isd(e, dreg, index, scale, disp) emit_movsx_r32_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
6944
6945
6946		/*------------------------------------------------------------------
6947		emit_movzx_r32_*
6948		------------------------------------------------------------------*/
6949
6950		INLINE void emit_movzx_r32_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
6951		{
6952		emit_byte(emitptr, PREFIX_OPSIZE);
6953		emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, sreg);
6954		}
6955
6956		INLINE void emit_movzx_r32_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6957		{
6958		emit_byte(emitptr, PREFIX_OPSIZE);
6959		emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
6960		}
6961
6962		INLINE void emit_movzx_r32_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
6963		{
6964		emit_byte(emitptr, PREFIX_OPSIZE);
6965		emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Ew, OP_32BIT, dreg, sreg);
6966		}
6967
6968		INLINE void emit_movzx_r32_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6969		{
6970		emit_byte(emitptr, PREFIX_OPSIZE);
6971		emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Ew, OP_32BIT, dreg, base, index, scale, disp);
6972		}
6973
6974		#define emit_movzx_r32_m8abs(e, dreg, addr) emit_movzx_r32_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6975		#define emit_movzx_r32_m8bd(e, dreg, base, disp) emit_movzx_r32_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
6976		#define emit_movzx_r32_m8isd(e, dreg, index, scale, disp) emit_movzx_r32_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
6977
6978		#define emit_movzx_r32_m16abs(e, dreg, addr) emit_movzx_r32_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
6979		#define emit_movzx_r32_m16bd(e, dreg, base, disp) emit_movzx_r32_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
6980		#define emit_movzx_r32_m16isd(e, dreg, index, scale, disp) emit_movzx_r32_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
6981
6982
6983		/*------------------------------------------------------------------
6984		emit_movsx_r64_*
6985		------------------------------------------------------------------*/
6986
6987		#ifdef PTR64
6988
6989		INLINE void emit_movsx_r64_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
6990		{
6991		emit_byte(emitptr, PREFIX_OPSIZE);
6992		emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_64BIT, dreg, sreg);
6993		}
6994
6995		INLINE void emit_movsx_r64_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
6996		{
6997		emit_byte(emitptr, PREFIX_OPSIZE);
6998		emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_64BIT, dreg, base, index, scale, disp);
6999		}
7000
7001		INLINE void emit_movsx_r64_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
7002		{
7003		emit_byte(emitptr, PREFIX_OPSIZE);
7004		emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Ew, OP_64BIT, dreg, sreg);
7005		}
7006
7007		INLINE void emit_movsx_r64_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
7008		{
7009		emit_byte(emitptr, PREFIX_OPSIZE);
7010		emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Ew, OP_64BIT, dreg, base, index, scale, disp);
7011		}
7012
7013		INLINE void emit_movsxd_r64_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg)
7014		{
7015		emit_byte(emitptr, PREFIX_OPSIZE);
7016		emit_op_modrm_reg(emitptr, OP_MOVSXD_Gv_Ev, OP_64BIT, dreg, sreg);
7017		}
7018
7019		INLINE void emit_movsxd_r64_m32bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
7020		{
7021		emit_byte(emitptr, PREFIX_OPSIZE);
7022		emit_op_modrm_mem(emitptr, OP_MOVSXD_Gv_Ev, OP_64BIT, dreg, base, index, scale, disp);
7023		}
7024
7025		#define emit_movsx_r64_m8abs(e, dreg, addr) emit_movsx_r64_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7026		#define emit_movsx_r64_m8bd(e, dreg, base, disp) emit_movsx_r64_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
7027		#define emit_movsx_r64_m8isd(e, dreg, index, scale, disp) emit_movsx_r64_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7028
7029		#define emit_movsx_r64_m16abs(e, dreg, addr) emit_movsx_r64_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7030		#define emit_movsx_r64_m16bd(e, dreg, base, disp) emit_movsx_r64_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
7031		#define emit_movsx_r64_m16isd(e, dreg, index, scale, disp) emit_movsx_r64_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7032
7033		#define emit_movsxd_r64_m32abs(e, dreg, addr) emit_movsxd_r64_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7034		#define emit_movsxd_r64_m32bd(e, dreg, base, disp) emit_movsxd_r64_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
7035		#define emit_movsxd_r64_m32isd(e, dreg, index, scale, disp) emit_movsxd_r64_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7036
7037		#endif
7038
7039
7040		/*------------------------------------------------------------------
7041		emit_movzx_r64_*
7042		------------------------------------------------------------------*/
7043
7044		#ifdef PTR64
7045
7046		INLINE void emit_movzx_r64_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
7047		{
7048		emit_byte(emitptr, PREFIX_OPSIZE);
7049		emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_64BIT, dreg, sreg);
7050		}
7051
7052		INLINE void emit_movzx_r64_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
7053		{
7054		emit_byte(emitptr, PREFIX_OPSIZE);
7055		emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_64BIT, dreg, base, index, scale, disp);
7056		}
7057
7058		INLINE void emit_movzx_r64_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
7059		{
7060		emit_byte(emitptr, PREFIX_OPSIZE);
7061		emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Ew, OP_64BIT, dreg, sreg);
7062		}
7063
7064		INLINE void emit_movzx_r64_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
7065		{
7066		emit_byte(emitptr, PREFIX_OPSIZE);
7067		emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Ew, OP_64BIT, dreg, base, index, scale, disp);
7068		}
7069
7070		#define emit_movzx_r64_m8abs(e, dreg, addr) emit_movzx_r64_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7071		#define emit_movzx_r64_m8bd(e, dreg, base, disp) emit_movzx_r64_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
7072		#define emit_movzx_r64_m8isd(e, dreg, index, scale, disp) emit_movzx_r64_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7073
7074		#define emit_movzx_r64_m16abs(e, dreg, addr) emit_movzx_r64_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7075		#define emit_movzx_r64_m16bd(e, dreg, base, disp) emit_movzx_r64_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
7076		#define emit_movzx_r64_m16isd(e, dreg, index, scale, disp) emit_movzx_r64_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7077
7078		#endif
7079
7080
7081
7082		/***************************************************************************
7083		TEST EMITTERS
7084		***************************************************************************/
7085
7086		/*------------------------------------------------------------------
7087		emit_test_r8_*
7088		------------------------------------------------------------------*/
7089
7090		INLINE void emit_test_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm)
7091		{
7092		emit_op_modrm_reg(emitptr, OP_G3_Eb, OP_32BIT, 0, dreg);
7093		emit_byte(emitptr, imm);
7094		}
7095
7096		INLINE void emit_test_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
7097		{
7098		emit_op_modrm_reg(emitptr, OP_TEST_Eb_Gb, OP_32BIT, sreg, dreg);
7099		}
7100
7101		INLINE void emit_test_m8bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
7102		{
7103		emit_op_modrm_mem(emitptr, OP_G3_Eb, OP_32BIT, 0, base, index, scale, disp);
7104		emit_byte(emitptr, imm);
7105		}
7106
7107		INLINE void emit_test_m8bisd_r8(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
7108		{
7109		emit_op_modrm_mem(emitptr, OP_TEST_Eb_Gb, OP_32BIT, sreg, base, index, scale, disp);
7110		}
7111
7112		#define emit_test_m8abs_imm(e, addr, imm) emit_test_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7113		#define emit_test_m8bd_imm(e, base, disp, imm) emit_test_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7114		#define emit_test_m8isd_imm(e, index, scale, disp, imm) emit_test_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7115
7116		#define emit_test_m8abs_r8(e, addr, sreg) emit_test_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7117		#define emit_test_m8bd_r8(e, base, disp, sreg) emit_test_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
7118		#define emit_test_m8isd_r8(e, index, scale, disp, sreg) emit_test_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
7119
7120
7121		/*------------------------------------------------------------------
7122		emit_test_r16_*
7123		------------------------------------------------------------------*/
7124
7125		INLINE void emit_test_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm)
7126		{
7127		emit_byte(emitptr, PREFIX_OPSIZE);
7128		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 0, dreg);
7129		emit_word(emitptr, imm);
7130		}
7131
7132		INLINE void emit_test_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
7133		{
7134		emit_byte(emitptr, PREFIX_OPSIZE);
7135		emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, dreg);
7136		}
7137
7138		INLINE void emit_test_m16bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT16 imm)
7139		{
7140		emit_byte(emitptr, PREFIX_OPSIZE);
7141		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 0, base, index, scale, disp);
7142		emit_word(emitptr, imm);
7143		}
7144
7145		INLINE void emit_test_m16bisd_r16(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
7146		{
7147		emit_byte(emitptr, PREFIX_OPSIZE);
7148		emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
7149		}
7150
7151		#define emit_test_m16abs_imm(e, addr, imm) emit_test_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7152		#define emit_test_m16bd_imm(e, base, disp, imm) emit_test_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7153		#define emit_test_m16isd_imm(e, index, scale, disp, imm) emit_test_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7154
7155		#define emit_test_m16abs_r16(e, addr, sreg) emit_test_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7156		#define emit_test_m16bd_r16(e, base, disp, sreg) emit_test_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
7157		#define emit_test_m16isd_r16(e, index, scale, disp, sreg) emit_test_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
7158
7159
7160		/*------------------------------------------------------------------
7161		emit_test_r32_*
7162		------------------------------------------------------------------*/
7163
7164		INLINE void emit_test_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm)
7165		{
7166		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 0, dreg);
7167		emit_dword(emitptr, imm);
7168		}
7169
7170		INLINE void emit_test_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg)
7171		{
7172		emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, dreg);
7173		}
7174
7175		INLINE void emit_test_m32bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
7176		{
7177		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 0, base, index, scale, disp);
7178		emit_dword(emitptr, imm);
7179		}
7180
7181		INLINE void emit_test_m32bisd_r32(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
7182		{
7183		emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
7184		}
7185
7186		#define emit_test_m32abs_imm(e, addr, imm) emit_test_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7187		#define emit_test_m32bd_imm(e, base, disp, imm) emit_test_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7188		#define emit_test_m32isd_imm(e, index, scale, disp, imm) emit_test_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7189
7190		#define emit_test_m32abs_r32(e, addr, sreg) emit_test_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7191		#define emit_test_m32bd_r32(e, base, disp, sreg) emit_test_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
7192		#define emit_test_m32isd_r32(e, index, scale, disp, sreg) emit_test_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
7193
7194
7195		/*------------------------------------------------------------------
7196		emit_test_r64_*
7197		------------------------------------------------------------------*/
7198
7199		#ifdef PTR64
7200
7201		INLINE void emit_test_r64_imm(x86code **emitptr, UINT8 dreg, UINT64 imm)
7202		{
7203		assert((INT32)imm == (INT64)imm);
7204		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, 0, dreg);
7205		emit_dword(emitptr, imm);
7206		}
7207
7208		INLINE void emit_test_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg)
7209		{
7210		emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_64BIT, sreg, dreg);
7211		}
7212
7213		INLINE void emit_test_m64bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT64 imm)
7214		{
7215		assert((INT32)imm == (INT64)imm);
7216		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, 0, base, index, scale, disp);
7217		emit_dword(emitptr, (INT32)imm);
7218		}
7219
7220		INLINE void emit_test_m64bisd_r64(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
7221		{
7222		emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_64BIT, sreg, base, index, scale, disp);
7223		}
7224
7225		#define emit_test_m64abs_imm(e, addr, imm) emit_test_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7226		#define emit_test_m64bd_imm(e, base, disp, imm) emit_test_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7227		#define emit_test_m64isd_imm(e, index, scale, disp, imm) emit_test_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7228
7229		#define emit_test_m64abs_r64(e, addr, sreg) emit_test_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7230		#define emit_test_m64bd_r64(e, base, disp, sreg) emit_test_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
7231		#define emit_test_m64isd_r64(e, index, scale, disp, sreg) emit_test_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
7232
7233		#endif
7234
7235
7236
7237		/***************************************************************************
7238		8-BIT ARITHMETIC EMITTERS
7239		***************************************************************************/
7240
7241		/*
7242		Note that the following code relies on this:
7243
7244		00-05 or /0 = ADD
7245		08-0d or /1 = OR
7246		10-15 or /2 = ADC
7247		18-1d or /3 = SBB
7248		20-25 or /4 = AND
7249		28-2d or /5 = SUB
7250		30-35 or /6 = XOR
7251		38-3d or /7 = CMP
7252		*/
7253
7254		/*------------------------------------------------------------------
7255		emit_arith_r8_*
7256		------------------------------------------------------------------*/
7257
7258		INLINE void emit_arith_r8_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
7259		{
7260		emit_op_modrm_reg(emitptr, OP_G1_Eb_Ib, OP_32BIT, opindex, dreg);
7261		emit_byte(emitptr, imm);
7262		}
7263
7264		INLINE void emit_arith_m8bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
7265		{
7266		emit_op_modrm_mem(emitptr, OP_G1_Eb_Ib, OP_32BIT, opindex, base, index, scale, disp);
7267		emit_byte(emitptr, imm);
7268		}
7269
7270		INLINE void emit_arith_r8_r8(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
7271		{
7272		emit_op_modrm_reg(emitptr, OP_ADD_Eb_Gb + 8 * opindex, OP_32BIT, dreg, sreg);
7273		}
7274
7275		INLINE void emit_arith_r8_m8bisd(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
7276		{
7277		emit_op_modrm_mem(emitptr, OP_ADD_Eb_Gb + 8 * opindex, OP_32BIT, dreg, base, index, scale, disp);
7278		}
7279
7280		INLINE void emit_arith_m8bisd_r8(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
7281		{
7282		emit_op_modrm_mem(emitptr, OP_ADD_Gb_Eb + 8 * opindex, OP_32BIT, sreg, base, index, scale, disp);
7283		}
7284
7285
7286		/*------------------------------------------------------------------
7287		emit_add_r8_*
7288		------------------------------------------------------------------*/
7289
7290		#define emit_add_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 0, dreg, imm)
7291		#define emit_add_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 0, base, index, scale, disp, imm)
7292		#define emit_add_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 0, dreg, sreg)
7293		#define emit_add_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 0, dreg, base, index, scale, disp)
7294		#define emit_add_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 0, base, index, scale, disp, sreg)
7295
7296		#define emit_add_m8abs_imm(e, addr, imm) emit_add_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7297		#define emit_add_m8bd_imm(e, base, disp, imm) emit_add_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7298		#define emit_add_m8isd_imm(e, index, scale, disp, imm) emit_add_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7299
7300		#define emit_add_r8_m8abs(e, dreg, addr) emit_add_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7301		#define emit_add_r8_m8bd(e, dreg, base, disp) emit_add_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
7302		#define emit_add_r8_m8isd(e, dreg, index, scale, disp) emit_add_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7303
7304		#define emit_add_m8abs_r8(e, addr, sreg) emit_add_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7305		#define emit_add_m8bd_r8(e, base, disp, sreg) emit_add_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
7306		#define emit_add_m8isd_r8(e, index, scale, disp, sreg) emit_add_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
7307
7308
7309		/*------------------------------------------------------------------
7310		emit_or_r8_*
7311		------------------------------------------------------------------*/
7312
7313		#define emit_or_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 1, dreg, imm)
7314		#define emit_or_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 1, base, index, scale, disp, imm)
7315		#define emit_or_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 1, dreg, sreg)
7316		#define emit_or_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 1, dreg, base, index, scale, disp)
7317		#define emit_or_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 1, base, index, scale, disp, sreg)
7318
7319		#define emit_or_m8abs_imm(e, addr, imm) emit_or_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7320		#define emit_or_m8bd_imm(e, base, disp, imm) emit_or_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7321		#define emit_or_m8isd_imm(e, index, scale, disp, imm) emit_or_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7322
7323		#define emit_or_r8_m8abs(e, dreg, addr) emit_or_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7324		#define emit_or_r8_m8bd(e, dreg, base, disp) emit_or_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
7325		#define emit_or_r8_m8isd(e, dreg, index, scale, disp) emit_or_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7326
7327		#define emit_or_m8abs_r8(e, addr, sreg) emit_or_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7328		#define emit_or_m8bd_r8(e, base, disp, sreg) emit_or_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
7329		#define emit_or_m8isd_r8(e, index, scale, disp, sreg) emit_or_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
7330
7331
7332		/*------------------------------------------------------------------
7333		emit_adc_r8_*
7334		------------------------------------------------------------------*/
7335
7336		#define emit_adc_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 2, dreg, imm)
7337		#define emit_adc_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 2, base, index, scale, disp, imm)
7338		#define emit_adc_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 2, dreg, sreg)
7339		#define emit_adc_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 2, dreg, base, index, scale, disp)
7340		#define emit_adc_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 2, base, index, scale, disp, sreg)
7341
7342		#define emit_adc_m8abs_imm(e, addr, imm) emit_adc_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7343		#define emit_adc_m8bd_imm(e, base, disp, imm) emit_adc_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7344		#define emit_adc_m8isd_imm(e, index, scale, disp, imm) emit_adc_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7345
7346		#define emit_adc_r8_m8abs(e, dreg, addr) emit_adc_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7347		#define emit_adc_r8_m8bd(e, dreg, base, disp) emit_adc_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
7348		#define emit_adc_r8_m8isd(e, dreg, index, scale, disp) emit_adc_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7349
7350		#define emit_adc_m8abs_r8(e, addr, sreg) emit_adc_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7351		#define emit_adc_m8bd_r8(e, base, disp, sreg) emit_adc_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
7352		#define emit_adc_m8isd_r8(e, index, scale, disp, sreg) emit_adc_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
7353
7354
7355		/*------------------------------------------------------------------
7356		emit_sbb_r8_*
7357		------------------------------------------------------------------*/
7358
7359		#define emit_sbb_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 3, dreg, imm)
7360		#define emit_sbb_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 3, base, index, scale, disp, imm)
7361		#define emit_sbb_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 3, dreg, sreg)
7362		#define emit_sbb_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 3, dreg, base, index, scale, disp)
7363		#define emit_sbb_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 3, base, index, scale, disp, sreg)
7364
7365		#define emit_sbb_m8abs_imm(e, addr, imm) emit_sbb_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7366		#define emit_sbb_m8bd_imm(e, base, disp, imm) emit_sbb_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7367		#define emit_sbb_m8isd_imm(e, index, scale, disp, imm) emit_sbb_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7368
7369		#define emit_sbb_r8_m8abs(e, dreg, addr) emit_sbb_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7370		#define emit_sbb_r8_m8bd(e, dreg, base, disp) emit_sbb_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
7371		#define emit_sbb_r8_m8isd(e, dreg, index, scale, disp) emit_sbb_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7372
7373		#define emit_sbb_m8abs_r8(e, addr, sreg) emit_sbb_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7374		#define emit_sbb_m8bd_r8(e, base, disp, sreg) emit_sbb_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
7375		#define emit_sbb_m8isd_r8(e, index, scale, disp, sreg) emit_sbb_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
7376
7377
7378		/*------------------------------------------------------------------
7379		emit_and_r8_*
7380		------------------------------------------------------------------*/
7381
7382		#define emit_and_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 4, dreg, imm)
7383		#define emit_and_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 4, base, index, scale, disp, imm)
7384		#define emit_and_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 4, dreg, sreg)
7385		#define emit_and_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 4, dreg, base, index, scale, disp)
7386		#define emit_and_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 4, base, index, scale, disp, sreg)
7387
7388		#define emit_and_m8abs_imm(e, addr, imm) emit_and_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7389		#define emit_and_m8bd_imm(e, base, disp, imm) emit_and_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7390		#define emit_and_m8isd_imm(e, index, scale, disp, imm) emit_and_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7391
7392		#define emit_and_r8_m8abs(e, dreg, addr) emit_and_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7393		#define emit_and_r8_m8bd(e, dreg, base, disp) emit_and_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
7394		#define emit_and_r8_m8isd(e, dreg, index, scale, disp) emit_and_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7395
7396		#define emit_and_m8abs_r8(e, addr, sreg) emit_and_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7397		#define emit_and_m8bd_r8(e, base, disp, sreg) emit_and_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
7398		#define emit_and_m8isd_r8(e, index, scale, disp, sreg) emit_and_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
7399
7400
7401		/*------------------------------------------------------------------
7402		emit_sub_r8_*
7403		------------------------------------------------------------------*/
7404
7405		#define emit_sub_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 5, dreg, imm)
7406		#define emit_sub_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 5, base, index, scale, disp, imm)
7407		#define emit_sub_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 5, dreg, sreg)
7408		#define emit_sub_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 5, dreg, base, index, scale, disp)
7409		#define emit_sub_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 5, base, index, scale, disp, sreg)
7410
7411		#define emit_sub_m8abs_imm(e, addr, imm) emit_sub_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7412		#define emit_sub_m8bd_imm(e, base, disp, imm) emit_sub_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7413		#define emit_sub_m8isd_imm(e, index, scale, disp, imm) emit_sub_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7414
7415		#define emit_sub_r8_m8abs(e, dreg, addr) emit_sub_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7416		#define emit_sub_r8_m8bd(e, dreg, base, disp) emit_sub_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
7417		#define emit_sub_r8_m8isd(e, dreg, index, scale, disp) emit_sub_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7418
7419		#define emit_sub_m8abs_r8(e, addr, sreg) emit_sub_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7420		#define emit_sub_m8bd_r8(e, base, disp, sreg) emit_sub_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
7421		#define emit_sub_m8isd_r8(e, index, scale, disp, sreg) emit_sub_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
7422
7423
7424		/*------------------------------------------------------------------
7425		emit_xor_r8_*
7426		------------------------------------------------------------------*/
7427
7428		#define emit_xor_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 6, dreg, imm)
7429		#define emit_xor_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 6, base, index, scale, disp, imm)
7430		#define emit_xor_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 6, dreg, sreg)
7431		#define emit_xor_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 6, dreg, base, index, scale, disp)
7432		#define emit_xor_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 6, base, index, scale, disp, sreg)
7433
7434		#define emit_xor_m8abs_imm(e, addr, imm) emit_xor_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7435		#define emit_xor_m8bd_imm(e, base, disp, imm) emit_xor_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7436		#define emit_xor_m8isd_imm(e, index, scale, disp, imm) emit_xor_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7437
7438		#define emit_xor_r8_m8abs(e, dreg, addr) emit_xor_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7439		#define emit_xor_r8_m8bd(e, dreg, base, disp) emit_xor_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
7440		#define emit_xor_r8_m8isd(e, dreg, index, scale, disp) emit_xor_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7441
7442		#define emit_xor_m8abs_r8(e, addr, sreg) emit_xor_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7443		#define emit_xor_m8bd_r8(e, base, disp, sreg) emit_xor_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
7444		#define emit_xor_m8isd_r8(e, index, scale, disp, sreg) emit_xor_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
7445
7446
7447		/*------------------------------------------------------------------
7448		emit_cmp_r8_*
7449		------------------------------------------------------------------*/
7450
7451		#define emit_cmp_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 7, dreg, imm)
7452		#define emit_cmp_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 7, base, index, scale, disp, imm)
7453		#define emit_cmp_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 7, dreg, sreg)
7454		#define emit_cmp_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 7, dreg, base, index, scale, disp)
7455		#define emit_cmp_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 7, base, index, scale, disp, sreg)
7456
7457		#define emit_cmp_m8abs_imm(e, addr, imm) emit_cmp_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7458		#define emit_cmp_m8bd_imm(e, base, disp, imm) emit_cmp_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7459		#define emit_cmp_m8isd_imm(e, index, scale, disp, imm) emit_cmp_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7460
7461		#define emit_cmp_r8_m8abs(e, dreg, addr) emit_cmp_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7462		#define emit_cmp_r8_m8bd(e, dreg, base, disp) emit_cmp_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
7463		#define emit_cmp_r8_m8isd(e, dreg, index, scale, disp) emit_cmp_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7464
7465		#define emit_cmp_m8abs_r8(e, addr, sreg) emit_cmp_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7466		#define emit_cmp_m8bd_r8(e, base, disp, sreg) emit_cmp_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
7467		#define emit_cmp_m8isd_r8(e, index, scale, disp, sreg) emit_cmp_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
7468
7469
7470
7471		/***************************************************************************
7472		16-BIT ARITHMETIC EMITTERS
7473		***************************************************************************/
7474
7475		/*
7476		Note that the following code relies on this:
7477
7478		00-05 or /0 = ADD
7479		08-0d or /1 = OR
7480		10-15 or /2 = ADC
7481		18-1d or /3 = SBB
7482		20-25 or /4 = AND
7483		28-2d or /5 = SUB
7484		30-35 or /6 = XOR
7485		38-3d or /7 = CMP
7486		*/
7487
7488		INLINE void emit_arith_r16_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT16 imm)
7489		{
7490		emit_byte(emitptr, PREFIX_OPSIZE);
7491		if ((INT8)imm == (INT16)imm)
7492		{
7493		emit_op_modrm_reg(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, dreg);
7494		emit_byte(emitptr, (INT8)imm);
7495		}
	1717	if ((INT32)imm == (INT64)imm)
	1718	emit_op_modrm_reg_imm32(emitptr, OP_G11_Ev_Iz, OP_64BIT, 0, dreg, imm);
7496	1719	else
7497	1720	{
7498		emit_op_modrm_reg(emitptr, OP_G1_Ev_Iz, OP_32BIT, opindex, dreg);
7499		emit_word(emitptr, imm);
	1721	emit_op_reg(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_64BIT, dreg);
	1722	emit_qword(emitptr, imm);
7500	1723	}
7501	1724	}
7502	1725
7503		INLINE void emit_arith_m16bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT16 imm)
7504		{
7505		emit_byte(emitptr, PREFIX_OPSIZE);
7506		if ((INT8)imm == (INT16)imm)
7507		{
7508		emit_op_modrm_mem(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
7509		emit_byte(emitptr, (INT8)imm);
7510		}
7511		else
7512		{
7513		emit_op_modrm_mem(emitptr, OP_G1_Ev_Iz, OP_32BIT, opindex, base, index, scale, disp);
7514		emit_word(emitptr, imm);
7515		}
7516		}
	1726	INLINE void emit_mov_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_64BIT, dreg, sreg); }
	1727	INLINE void emit_mov_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	1728	INLINE void emit_mov_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm32(emitptr, OP_G11_Ev_Iz, OP_64BIT, 0, MEMPARAMS, imm); }
	1729	INLINE void emit_mov_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
	1730	INLINE void emit_movsx_r64_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_64BIT, dreg, sreg); }
	1731	INLINE void emit_movsx_r64_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_64BIT, dreg, MEMPARAMS); }
	1732	INLINE void emit_movsx_r64_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Ew, OP_64BIT, dreg, sreg); }
	1733	INLINE void emit_movsx_r64_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Ew, OP_64BIT, dreg, MEMPARAMS); }
	1734	INLINE void emit_movsxd_r64_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVSXD_Gv_Ev, OP_64BIT, dreg, sreg); }
	1735	INLINE void emit_movsxd_r64_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVSXD_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	1736	INLINE void emit_movzx_r64_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_64BIT, dreg, sreg); }
	1737	INLINE void emit_movzx_r64_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_64BIT, dreg, MEMPARAMS); }
	1738	INLINE void emit_movzx_r64_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Ew, OP_64BIT, dreg, sreg); }
	1739	INLINE void emit_movzx_r64_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Ew, OP_64BIT, dreg, MEMPARAMS); }
	1740	INLINE void emit_cmovcc_r64_r64(x86code **emitptr, UINT8 cond, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + cond, OP_64BIT, dreg, sreg); }
	1741	INLINE void emit_cmovcc_r64_m64(x86code **emitptr, UINT8 cond, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + cond, OP_64BIT, dreg, MEMPARAMS); }
7517	1742
7518		INLINE void emit_arith_r16_r16(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
7519		{
7520		emit_byte(emitptr, PREFIX_OPSIZE);
7521		emit_op_modrm_reg(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_32BIT, dreg, sreg);
7522		}
	1743	#endif
7523	1744
7524		INLINE void emit_arith_r16_m16bisd(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
7525		{
7526		emit_byte(emitptr, PREFIX_OPSIZE);
7527		emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_32BIT, dreg, base, index, scale, disp);
7528		}
7529	1745
7530		INLINE void emit_arith_m16bisd_r16(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
7531		{
7532		emit_byte(emitptr, PREFIX_OPSIZE);
7533		emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_32BIT, sreg, base, index, scale, disp);
7534		}
7535	1746
7536
7537		/*------------------------------------------------------------------
7538		emit_add_r16_*
7539		------------------------------------------------------------------*/
7540
7541		#define emit_add_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 0, dreg, imm)
7542		#define emit_add_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 0, base, index, scale, disp, imm)
7543		#define emit_add_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 0, dreg, sreg)
7544		#define emit_add_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 0, dreg, base, index, scale, disp)
7545		#define emit_add_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 0, base, index, scale, disp, sreg)
7546
7547		#define emit_add_m16abs_imm(e, addr, imm) emit_add_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7548		#define emit_add_m16bd_imm(e, base, disp, imm) emit_add_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7549		#define emit_add_m16isd_imm(e, index, scale, disp, imm) emit_add_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7550
7551		#define emit_add_r16_m16abs(e, dreg, addr) emit_add_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7552		#define emit_add_r16_m16bd(e, dreg, base, disp) emit_add_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
7553		#define emit_add_r16_m16isd(e, dreg, index, scale, disp) emit_add_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7554
7555		#define emit_add_m16abs_r16(e, addr, sreg) emit_add_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7556		#define emit_add_m16bd_r16(e, base, disp, sreg) emit_add_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
7557		#define emit_add_m16isd_r16(e, index, scale, disp, sreg) emit_add_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
7558
7559
7560		/*------------------------------------------------------------------
7561		emit_or_r16_*
7562		------------------------------------------------------------------*/
7563
7564		#define emit_or_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 1, dreg, imm)
7565		#define emit_or_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 1, base, index, scale, disp, imm)
7566		#define emit_or_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 1, dreg, sreg)
7567		#define emit_or_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 1, dreg, base, index, scale, disp)
7568		#define emit_or_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 1, base, index, scale, disp, sreg)
7569
7570		#define emit_or_m16abs_imm(e, addr, imm) emit_or_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7571		#define emit_or_m16bd_imm(e, base, disp, imm) emit_or_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7572		#define emit_or_m16isd_imm(e, index, scale, disp, imm) emit_or_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7573
7574		#define emit_or_r16_m16abs(e, dreg, addr) emit_or_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7575		#define emit_or_r16_m16bd(e, dreg, base, disp) emit_or_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
7576		#define emit_or_r16_m16isd(e, dreg, index, scale, disp) emit_or_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7577
7578		#define emit_or_m16abs_r16(e, addr, sreg) emit_or_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7579		#define emit_or_m16bd_r16(e, base, disp, sreg) emit_or_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
7580		#define emit_or_m16isd_r16(e, index, scale, disp, sreg) emit_or_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
7581
7582
7583		/*------------------------------------------------------------------
7584		emit_adc_r16_*
7585		------------------------------------------------------------------*/
7586
7587		#define emit_adc_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 2, dreg, imm)
7588		#define emit_adc_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 2, base, index, scale, disp, imm)
7589		#define emit_adc_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 2, dreg, sreg)
7590		#define emit_adc_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 2, dreg, base, index, scale, disp)
7591		#define emit_adc_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 2, base, index, scale, disp, sreg)
7592
7593		#define emit_adc_m16abs_imm(e, addr, imm) emit_adc_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7594		#define emit_adc_m16bd_imm(e, base, disp, imm) emit_adc_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7595		#define emit_adc_m16isd_imm(e, index, scale, disp, imm) emit_adc_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7596
7597		#define emit_adc_r16_m16abs(e, dreg, addr) emit_adc_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7598		#define emit_adc_r16_m16bd(e, dreg, base, disp) emit_adc_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
7599		#define emit_adc_r16_m16isd(e, dreg, index, scale, disp) emit_adc_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7600
7601		#define emit_adc_m16abs_r16(e, addr, sreg) emit_adc_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7602		#define emit_adc_m16bd_r16(e, base, disp, sreg) emit_adc_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
7603		#define emit_adc_m16isd_r16(e, index, scale, disp, sreg) emit_adc_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
7604
7605
7606		/*------------------------------------------------------------------
7607		emit_sbb_r16_*
7608		------------------------------------------------------------------*/
7609
7610		#define emit_sbb_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 3, dreg, imm)
7611		#define emit_sbb_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 3, base, index, scale, disp, imm)
7612		#define emit_sbb_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 3, dreg, sreg)
7613		#define emit_sbb_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 3, dreg, base, index, scale, disp)
7614		#define emit_sbb_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 3, base, index, scale, disp, sreg)
7615
7616		#define emit_sbb_m16abs_imm(e, addr, imm) emit_sbb_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7617		#define emit_sbb_m16bd_imm(e, base, disp, imm) emit_sbb_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7618		#define emit_sbb_m16isd_imm(e, index, scale, disp, imm) emit_sbb_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7619
7620		#define emit_sbb_r16_m16abs(e, dreg, addr) emit_sbb_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7621		#define emit_sbb_r16_m16bd(e, dreg, base, disp) emit_sbb_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
7622		#define emit_sbb_r16_m16isd(e, dreg, index, scale, disp) emit_sbb_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7623
7624		#define emit_sbb_m16abs_r16(e, addr, sreg) emit_sbb_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7625		#define emit_sbb_m16bd_r16(e, base, disp, sreg) emit_sbb_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
7626		#define emit_sbb_m16isd_r16(e, index, scale, disp, sreg) emit_sbb_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
7627
7628
7629		/*------------------------------------------------------------------
7630		emit_and_r16_*
7631		------------------------------------------------------------------*/
7632
7633		#define emit_and_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 4, dreg, imm)
7634		#define emit_and_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 4, base, index, scale, disp, imm)
7635		#define emit_and_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 4, dreg, sreg)
7636		#define emit_and_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 4, dreg, base, index, scale, disp)
7637		#define emit_and_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 4, base, index, scale, disp, sreg)
7638
7639		#define emit_and_m16abs_imm(e, addr, imm) emit_and_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7640		#define emit_and_m16bd_imm(e, base, disp, imm) emit_and_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7641		#define emit_and_m16isd_imm(e, index, scale, disp, imm) emit_and_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7642
7643		#define emit_and_r16_m16abs(e, dreg, addr) emit_and_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7644		#define emit_and_r16_m16bd(e, dreg, base, disp) emit_and_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
7645		#define emit_and_r16_m16isd(e, dreg, index, scale, disp) emit_and_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7646
7647		#define emit_and_m16abs_r16(e, addr, sreg) emit_and_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7648		#define emit_and_m16bd_r16(e, base, disp, sreg) emit_and_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
7649		#define emit_and_m16isd_r16(e, index, scale, disp, sreg) emit_and_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
7650
7651
7652		/*------------------------------------------------------------------
7653		emit_sub_r16_*
7654		------------------------------------------------------------------*/
7655
7656		#define emit_sub_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 5, dreg, imm)
7657		#define emit_sub_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 5, base, index, scale, disp, imm)
7658		#define emit_sub_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 5, dreg, sreg)
7659		#define emit_sub_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 5, dreg, base, index, scale, disp)
7660		#define emit_sub_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 5, base, index, scale, disp, sreg)
7661
7662		#define emit_sub_m16abs_imm(e, addr, imm) emit_sub_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7663		#define emit_sub_m16bd_imm(e, base, disp, imm) emit_sub_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7664		#define emit_sub_m16isd_imm(e, index, scale, disp, imm) emit_sub_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7665
7666		#define emit_sub_r16_m16abs(e, dreg, addr) emit_sub_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7667		#define emit_sub_r16_m16bd(e, dreg, base, disp) emit_sub_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
7668		#define emit_sub_r16_m16isd(e, dreg, index, scale, disp) emit_sub_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7669
7670		#define emit_sub_m16abs_r16(e, addr, sreg) emit_sub_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7671		#define emit_sub_m16bd_r16(e, base, disp, sreg) emit_sub_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
7672		#define emit_sub_m16isd_r16(e, index, scale, disp, sreg) emit_sub_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
7673
7674
7675		/*------------------------------------------------------------------
7676		emit_xor_r16_*
7677		------------------------------------------------------------------*/
7678
7679		#define emit_xor_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 6, dreg, imm)
7680		#define emit_xor_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 6, base, index, scale, disp, imm)
7681		#define emit_xor_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 6, dreg, sreg)
7682		#define emit_xor_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 6, dreg, base, index, scale, disp)
7683		#define emit_xor_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 6, base, index, scale, disp, sreg)
7684
7685		#define emit_xor_m16abs_imm(e, addr, imm) emit_xor_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7686		#define emit_xor_m16bd_imm(e, base, disp, imm) emit_xor_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7687		#define emit_xor_m16isd_imm(e, index, scale, disp, imm) emit_xor_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7688
7689		#define emit_xor_r16_m16abs(e, dreg, addr) emit_xor_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7690		#define emit_xor_r16_m16bd(e, dreg, base, disp) emit_xor_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
7691		#define emit_xor_r16_m16isd(e, dreg, index, scale, disp) emit_xor_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7692
7693		#define emit_xor_m16abs_r16(e, addr, sreg) emit_xor_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7694		#define emit_xor_m16bd_r16(e, base, disp, sreg) emit_xor_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
7695		#define emit_xor_m16isd_r16(e, index, scale, disp, sreg) emit_xor_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
7696
7697
7698		/*------------------------------------------------------------------
7699		emit_cmp_r16_*
7700		------------------------------------------------------------------*/
7701
7702		#define emit_cmp_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 7, dreg, imm)
7703		#define emit_cmp_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 7, base, index, scale, disp, imm)
7704		#define emit_cmp_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 7, dreg, sreg)
7705		#define emit_cmp_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 7, dreg, base, index, scale, disp)
7706		#define emit_cmp_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 7, base, index, scale, disp, sreg)
7707
7708		#define emit_cmp_m16abs_imm(e, addr, imm) emit_cmp_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7709		#define emit_cmp_m16bd_imm(e, base, disp, imm) emit_cmp_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7710		#define emit_cmp_m16isd_imm(e, index, scale, disp, imm) emit_cmp_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7711
7712		#define emit_cmp_r16_m16abs(e, dreg, addr) emit_cmp_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7713		#define emit_cmp_r16_m16bd(e, dreg, base, disp) emit_cmp_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
7714		#define emit_cmp_r16_m16isd(e, dreg, index, scale, disp) emit_cmp_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7715
7716		#define emit_cmp_m16abs_r16(e, addr, sreg) emit_cmp_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7717		#define emit_cmp_m16bd_r16(e, base, disp, sreg) emit_cmp_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
7718		#define emit_cmp_m16isd_r16(e, index, scale, disp, sreg) emit_cmp_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
7719
7720
7721
7722	1747	/***************************************************************************
7723		~~32-BIT~~ ARITHMETIC EMITTERS
	1748	ARITHMETIC EMITTERS
7724	1749	***************************************************************************/
7725	1750
7726		/*
7727		Note that the following code relies on this:
	1751	/*-------------------------------------------------
	1752	emit_arith_r8_*
	1753	-------------------------------------------------*/
7728	1754
7729		00-05 or /0 = ADD
7730		08-0d or /1 = OR
7731		10-15 or /2 = ADC
7732		18-1d or /3 = SBB
7733		20-25 or /4 = AND
7734		28-2d or /5 = SUB
7735		30-35 or /6 = XOR
7736		38-3d or /7 = CMP
7737		*/
	1755	INLINE void emit_add_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 0, dreg, imm); }
	1756	INLINE void emit_add_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 0, MEMPARAMS, imm); }
	1757	INLINE void emit_add_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADD_Gb_Eb, OP_32BIT, dreg, sreg); }
	1758	INLINE void emit_add_r8_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADD_Gb_Eb, OP_32BIT, dreg, MEMPARAMS); }
	1759	INLINE void emit_add_m8_r8(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_ADD_Eb_Gb, OP_32BIT, sreg, MEMPARAMS); }
7738	1760
7739		INLINE void emit_arith_r32_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT32 imm)
7740		{
7741		if ((INT8)imm == (INT32)imm)
7742		{
7743		emit_op_modrm_reg(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, dreg);
7744		emit_byte(emitptr, (INT8)imm);
7745		}
7746		else
7747		{
7748		emit_op_modrm_reg(emitptr, OP_G1_Ev_Iz, OP_32BIT, opindex, dreg);
7749		emit_dword(emitptr, imm);
7750		}
7751		}
	1761	INLINE void emit_or_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 1, dreg, imm); }
	1762	INLINE void emit_or_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 1, MEMPARAMS, imm); }
	1763	INLINE void emit_or_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_OR_Gb_Eb, OP_32BIT, dreg, sreg); }
	1764	INLINE void emit_or_r8_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_OR_Gb_Eb, OP_32BIT, dreg, MEMPARAMS); }
	1765	INLINE void emit_or_m8_r8(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_OR_Eb_Gb, OP_32BIT, sreg, MEMPARAMS); }
7752	1766
7753		INLINE void emit_arith_m32bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
7754		{
7755		if ((INT8)imm == (INT32)imm)
7756		{
7757		emit_op_modrm_mem(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
7758		emit_byte(emitptr, (INT8)imm);
7759		}
7760		else
7761		{
7762		emit_op_modrm_mem(emitptr, OP_G1_Ev_Iz, OP_32BIT, opindex, base, index, scale, disp);
7763		emit_dword(emitptr, imm);
7764		}
7765		}
	1767	INLINE void emit_adc_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 2, dreg, imm); }
	1768	INLINE void emit_adc_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 2, MEMPARAMS, imm); }
	1769	INLINE void emit_adc_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADC_Gb_Eb, OP_32BIT, dreg, sreg); }
	1770	INLINE void emit_adc_r8_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADC_Gb_Eb, OP_32BIT, dreg, MEMPARAMS); }
	1771	INLINE void emit_adc_m8_r8(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_ADC_Eb_Gb, OP_32BIT, sreg, MEMPARAMS); }
7766	1772
7767		INLINE void emit_arith_r32_r32(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
7768		{
7769		emit_op_modrm_reg(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_32BIT, dreg, sreg);
7770		}
	1773	INLINE void emit_sbb_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 3, dreg, imm); }
	1774	INLINE void emit_sbb_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 3, MEMPARAMS, imm); }
	1775	INLINE void emit_sbb_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SBB_Gb_Eb, OP_32BIT, dreg, sreg); }
	1776	INLINE void emit_sbb_r8_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SBB_Gb_Eb, OP_32BIT, dreg, MEMPARAMS); }
	1777	INLINE void emit_sbb_m8_r8(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SBB_Eb_Gb, OP_32BIT, sreg, MEMPARAMS); }
7771	1778
7772		INLINE void emit_arith_r32_m32bisd(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
7773		{
7774		emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_32BIT, dreg, base, index, scale, disp);
7775		}
	1779	INLINE void emit_and_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 4, dreg, imm); }
	1780	INLINE void emit_and_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 4, MEMPARAMS, imm); }
	1781	INLINE void emit_and_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_AND_Gb_Eb, OP_32BIT, dreg, sreg); }
	1782	INLINE void emit_and_r8_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_AND_Gb_Eb, OP_32BIT, dreg, MEMPARAMS); }
	1783	INLINE void emit_and_m8_r8(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_AND_Eb_Gb, OP_32BIT, sreg, MEMPARAMS); }
7776	1784
7777		INLINE void emit_arith_m32bisd_r32(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
7778		{
7779		emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_32BIT, sreg, base, index, scale, disp);
7780		}
	1785	INLINE void emit_sub_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 5, dreg, imm); }
	1786	INLINE void emit_sub_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 5, MEMPARAMS, imm); }
	1787	INLINE void emit_sub_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SUB_Gb_Eb, OP_32BIT, dreg, sreg); }
	1788	INLINE void emit_sub_r8_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SUB_Gb_Eb, OP_32BIT, dreg, MEMPARAMS); }
	1789	INLINE void emit_sub_m8_r8(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SUB_Eb_Gb, OP_32BIT, sreg, MEMPARAMS); }
7781	1790
	1791	INLINE void emit_xor_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 6, dreg, imm); }
	1792	INLINE void emit_xor_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 6, MEMPARAMS, imm); }
	1793	INLINE void emit_xor_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_XOR_Gb_Eb, OP_32BIT, dreg, sreg); }
	1794	INLINE void emit_xor_r8_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_XOR_Gb_Eb, OP_32BIT, dreg, MEMPARAMS); }
	1795	INLINE void emit_xor_m8_r8(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_XOR_Eb_Gb, OP_32BIT, sreg, MEMPARAMS); }
7782	1796
7783		/*------------------------------------------------------------------
7784		emit_add_r32_*
7785		------------------------------------------------------------------*/
	1797	INLINE void emit_cmp_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 7, dreg, imm); }
	1798	INLINE void emit_cmp_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G1_Eb_Ib, OP_32BIT, 7, MEMPARAMS, imm); }
	1799	INLINE void emit_cmp_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CMP_Gb_Eb, OP_32BIT, dreg, sreg); }
	1800	INLINE void emit_cmp_r8_m8(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CMP_Gb_Eb, OP_32BIT, dreg, MEMPARAMS); }
	1801	INLINE void emit_cmp_m8_r8(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_CMP_Eb_Gb, OP_32BIT, sreg, MEMPARAMS); }
7786	1802
7787		#define emit_add_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 0, dreg, imm)
7788		#define emit_add_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 0, base, index, scale, disp, imm)
7789		#define emit_add_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 0, dreg, sreg)
7790		#define emit_add_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 0, dreg, base, index, scale, disp)
7791		#define emit_add_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 0, base, index, scale, disp, sreg)
	1803	INLINE void emit_test_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G3_Eb, OP_32BIT, 0, dreg, imm); }
	1804	INLINE void emit_test_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G3_Eb, OP_32BIT, 0, MEMPARAMS, imm); }
	1805	INLINE void emit_test_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_TEST_Eb_Gb, OP_32BIT, sreg, dreg); }
	1806	INLINE void emit_test_m8_r8(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_TEST_Eb_Gb, OP_32BIT, sreg, MEMPARAMS); }
7792	1807
7793		#define emit_add_m32abs_imm(e, addr, imm) emit_add_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7794		#define emit_add_m32bd_imm(e, base, disp, imm) emit_add_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7795		#define emit_add_m32isd_imm(e, index, scale, disp, imm) emit_add_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7796	1808
7797		#define emit_add_r32_m32abs(e, dreg, addr) emit_add_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7798		#define emit_add_r32_m32bd(e, dreg, base, disp) emit_add_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
7799		#define emit_add_r32_m32isd(e, dreg, index, scale, disp) emit_add_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1809	/*-------------------------------------------------
	1810	emit_arith_r16_*
	1811	-------------------------------------------------*/
7800	1812
7801		#define emit_add_m32abs_r32(e, addr, sreg) emit_add_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7802		#define emit_add_m32bd_r32(e, base, disp, sreg) emit_add_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
7803		#define emit_add_m32isd_r32(e, index, scale, disp, sreg) emit_add_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	1813	INLINE void emit_add_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm) { emit_op_modrm_reg_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 0, dreg, imm); }
	1814	INLINE void emit_add_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT16 imm) { emit_op_modrm_mem_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 0, MEMPARAMS, imm); }
	1815	INLINE void emit_add_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADD_Gv_Ev, OP_16BIT, dreg, sreg); }
	1816	INLINE void emit_add_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
	1817	INLINE void emit_add_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
7804	1818
	1819	INLINE void emit_or_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm) { emit_op_modrm_reg_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 1, dreg, imm); }
	1820	INLINE void emit_or_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT16 imm) { emit_op_modrm_mem_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 1, MEMPARAMS, imm); }
	1821	INLINE void emit_or_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_OR_Gv_Ev, OP_16BIT, dreg, sreg); }
	1822	INLINE void emit_or_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_OR_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
	1823	INLINE void emit_or_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_OR_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
7805	1824
7806		/*------------------------------------------------------------------
7807		emit_or_r32_*
7808		------------------------------------------------------------------*/
	1825	INLINE void emit_adc_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm) { emit_op_modrm_reg_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 2, dreg, imm); }
	1826	INLINE void emit_adc_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT16 imm) { emit_op_modrm_mem_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 2, MEMPARAMS, imm); }
	1827	INLINE void emit_adc_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADC_Gv_Ev, OP_16BIT, dreg, sreg); }
	1828	INLINE void emit_adc_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADC_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
	1829	INLINE void emit_adc_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_ADC_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
7809	1830
7810		#define emit_or_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 1, dreg, imm)
7811		#define emit_or_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 1, base, index, scale, disp, imm)
7812		#define emit_or_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 1, dreg, sreg)
7813		#define emit_or_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 1, dreg, base, index, scale, disp)
7814		#define emit_or_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 1, base, index, scale, disp, sreg)
	1831	INLINE void emit_sbb_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm) { emit_op_modrm_reg_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 3, dreg, imm); }
	1832	INLINE void emit_sbb_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT16 imm) { emit_op_modrm_mem_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 3, MEMPARAMS, imm); }
	1833	INLINE void emit_sbb_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SBB_Gv_Ev, OP_16BIT, dreg, sreg); }
	1834	INLINE void emit_sbb_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SBB_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
	1835	INLINE void emit_sbb_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SBB_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
7815	1836
7816		#define emit_or_m32abs_imm(e, addr, imm) emit_or_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7817		#define emit_or_m32bd_imm(e, base, disp, imm) emit_or_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7818		#define emit_or_m32isd_imm(e, index, scale, disp, imm) emit_or_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	1837	INLINE void emit_and_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm) { emit_op_modrm_reg_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 4, dreg, imm); }
	1838	INLINE void emit_and_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT16 imm) { emit_op_modrm_mem_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 4, MEMPARAMS, imm); }
	1839	INLINE void emit_and_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_AND_Gv_Ev, OP_16BIT, dreg, sreg); }
	1840	INLINE void emit_and_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_AND_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
	1841	INLINE void emit_and_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_AND_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
7819	1842
7820		#define emit_or_r32_m32abs(e, dreg, addr) emit_or_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7821		#define emit_or_r32_m32bd(e, dreg, base, disp) emit_or_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
7822		#define emit_or_r32_m32isd(e, dreg, index, scale, disp) emit_or_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1843	INLINE void emit_sub_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm) { emit_op_modrm_reg_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 5, dreg, imm); }
	1844	INLINE void emit_sub_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT16 imm) { emit_op_modrm_mem_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 5, MEMPARAMS, imm); }
	1845	INLINE void emit_sub_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SUB_Gv_Ev, OP_16BIT, dreg, sreg); }
	1846	INLINE void emit_sub_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SUB_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
	1847	INLINE void emit_sub_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SUB_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
7823	1848
7824		#define emit_or_m32abs_r32(e, addr, sreg) emit_or_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7825		#define emit_or_m32bd_r32(e, base, disp, sreg) emit_or_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
7826		#define emit_or_m32isd_r32(e, index, scale, disp, sreg) emit_or_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	1849	INLINE void emit_xor_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm) { emit_op_modrm_reg_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 6, dreg, imm); }
	1850	INLINE void emit_xor_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT16 imm) { emit_op_modrm_mem_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 6, MEMPARAMS, imm); }
	1851	INLINE void emit_xor_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_XOR_Gv_Ev, OP_16BIT, dreg, sreg); }
	1852	INLINE void emit_xor_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_XOR_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
	1853	INLINE void emit_xor_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_XOR_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
7827	1854
	1855	INLINE void emit_cmp_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm) { emit_op_modrm_reg_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 7, dreg, imm); }
	1856	INLINE void emit_cmp_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT16 imm) { emit_op_modrm_mem_imm816(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_16BIT, 7, MEMPARAMS, imm); }
	1857	INLINE void emit_cmp_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CMP_Gv_Ev, OP_16BIT, dreg, sreg); }
	1858	INLINE void emit_cmp_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CMP_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
	1859	INLINE void emit_cmp_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_CMP_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
7828	1860
7829		/*------------------------------------------------------------------
7830		emit_adc_r32_*
7831		------------------------------------------------------------------*/
	1861	INLINE void emit_test_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm) { emit_op_modrm_reg_imm16(emitptr, OP_G3_Ev, OP_16BIT, 0, dreg, imm); }
	1862	INLINE void emit_test_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT16 imm) { emit_op_modrm_mem_imm16(emitptr, OP_G3_Ev, OP_16BIT, 0, MEMPARAMS, imm); }
	1863	INLINE void emit_test_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_16BIT, sreg, dreg); }
	1864	INLINE void emit_test_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
7832	1865
7833		#define emit_adc_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 2, dreg, imm)
7834		#define emit_adc_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 2, base, index, scale, disp, imm)
7835		#define emit_adc_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 2, dreg, sreg)
7836		#define emit_adc_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 2, dreg, base, index, scale, disp)
7837		#define emit_adc_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 2, base, index, scale, disp, sreg)
7838	1866
7839		#define emit_adc_m32abs_imm(e, addr, imm) emit_adc_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7840		#define emit_adc_m32bd_imm(e, base, disp, imm) emit_adc_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7841		#define emit_adc_m32isd_imm(e, index, scale, disp, imm) emit_adc_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	1867	/*-------------------------------------------------
	1868	emit_arith_r32_*
	1869	-------------------------------------------------*/
7842	1870
7843		#define emit_adc_r32_m32abs(e, dreg, addr) emit_adc_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7844		#define emit_adc_r32_m32bd(e, dreg, base, disp) emit_adc_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
7845		#define emit_adc_r32_m32isd(e, dreg, index, scale, disp) emit_adc_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1871	INLINE void emit_add_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 0, dreg, imm); }
	1872	INLINE void emit_add_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 0, MEMPARAMS, imm); }
	1873	INLINE void emit_add_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADD_Gv_Ev, OP_32BIT, dreg, sreg); }
	1874	INLINE void emit_add_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
	1875	INLINE void emit_add_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
7846	1876
7847		#define emit_adc_m32abs_r32(e, addr, sreg) emit_adc_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7848		#define emit_adc_m32bd_r32(e, base, disp, sreg) emit_adc_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
7849		#define emit_adc_m32isd_r32(e, index, scale, disp, sreg) emit_adc_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	1877	INLINE void emit_or_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 1, dreg, imm); }
	1878	INLINE void emit_or_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 1, MEMPARAMS, imm); }
	1879	INLINE void emit_or_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_OR_Gv_Ev, OP_32BIT, dreg, sreg); }
	1880	INLINE void emit_or_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_OR_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
	1881	INLINE void emit_or_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_OR_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
7850	1882
	1883	INLINE void emit_adc_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 2, dreg, imm); }
	1884	INLINE void emit_adc_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 2, MEMPARAMS, imm); }
	1885	INLINE void emit_adc_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADC_Gv_Ev, OP_32BIT, dreg, sreg); }
	1886	INLINE void emit_adc_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADC_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
	1887	INLINE void emit_adc_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_ADC_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
7851	1888
7852		/*------------------------------------------------------------------
7853		emit_sbb_r32_*
7854		------------------------------------------------------------------*/
	1889	INLINE void emit_sbb_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 3, dreg, imm); }
	1890	INLINE void emit_sbb_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 3, MEMPARAMS, imm); }
	1891	INLINE void emit_sbb_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SBB_Gv_Ev, OP_32BIT, dreg, sreg); }
	1892	INLINE void emit_sbb_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SBB_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
	1893	INLINE void emit_sbb_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SBB_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
7855	1894
7856		#define emit_sbb_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 3, dreg, imm)
7857		#define emit_sbb_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 3, base, index, scale, disp, imm)
7858		#define emit_sbb_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 3, dreg, sreg)
7859		#define emit_sbb_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 3, dreg, base, index, scale, disp)
7860		#define emit_sbb_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 3, base, index, scale, disp, sreg)
	1895	INLINE void emit_and_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 4, dreg, imm); }
	1896	INLINE void emit_and_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 4, MEMPARAMS, imm); }
	1897	INLINE void emit_and_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_AND_Gv_Ev, OP_32BIT, dreg, sreg); }
	1898	INLINE void emit_and_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_AND_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
	1899	INLINE void emit_and_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_AND_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
7861	1900
7862		#define emit_sbb_m32abs_imm(e, addr, imm) emit_sbb_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7863		#define emit_sbb_m32bd_imm(e, base, disp, imm) emit_sbb_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7864		#define emit_sbb_m32isd_imm(e, index, scale, disp, imm) emit_sbb_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	1901	INLINE void emit_sub_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 5, dreg, imm); }
	1902	INLINE void emit_sub_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 5, MEMPARAMS, imm); }
	1903	INLINE void emit_sub_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SUB_Gv_Ev, OP_32BIT, dreg, sreg); }
	1904	INLINE void emit_sub_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SUB_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
	1905	INLINE void emit_sub_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SUB_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
7865	1906
7866		#define emit_sbb_r32_m32abs(e, dreg, addr) emit_sbb_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7867		#define emit_sbb_r32_m32bd(e, dreg, base, disp) emit_sbb_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
7868		#define emit_sbb_r32_m32isd(e, dreg, index, scale, disp) emit_sbb_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1907	INLINE void emit_xor_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 6, dreg, imm); }
	1908	INLINE void emit_xor_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 6, MEMPARAMS, imm); }
	1909	INLINE void emit_xor_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_XOR_Gv_Ev, OP_32BIT, dreg, sreg); }
	1910	INLINE void emit_xor_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_XOR_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
	1911	INLINE void emit_xor_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_XOR_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
7869	1912
7870		#define emit_sbb_m32abs_r32(e, addr, sreg) emit_sbb_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7871		#define emit_sbb_m32bd_r32(e, base, disp, sreg) emit_sbb_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
7872		#define emit_sbb_m32isd_r32(e, index, scale, disp, sreg) emit_sbb_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	1913	INLINE void emit_cmp_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 7, dreg, imm); }
	1914	INLINE void emit_cmp_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_32BIT, 7, MEMPARAMS, imm); }
	1915	INLINE void emit_cmp_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CMP_Gv_Ev, OP_32BIT, dreg, sreg); }
	1916	INLINE void emit_cmp_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CMP_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
	1917	INLINE void emit_cmp_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_CMP_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
7873	1918
	1919	INLINE void emit_test_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm32(emitptr, OP_G3_Ev, OP_32BIT, 0, dreg, imm); }
	1920	INLINE void emit_test_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm32(emitptr, OP_G3_Ev, OP_32BIT, 0, MEMPARAMS, imm); }
	1921	INLINE void emit_test_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, dreg); }
	1922	INLINE void emit_test_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
7874	1923
7875		/*------------------------------------------------------------------
7876		emit_and_r32_*
7877		------------------------------------------------------------------*/
7878	1924
7879		#define emit_and_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 4, dreg, imm)
7880		#define emit_and_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 4, base, index, scale, disp, imm)
7881		#define emit_and_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 4, dreg, sreg)
7882		#define emit_and_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 4, dreg, base, index, scale, disp)
7883		#define emit_and_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 4, base, index, scale, disp, sreg)
	1925	/*-------------------------------------------------
	1926	emit_arith_r64_*
	1927	-------------------------------------------------*/
7884	1928
7885		#define emit_and_m32abs_imm(e, addr, imm) emit_and_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7886		#define emit_and_m32bd_imm(e, base, disp, imm) emit_and_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7887		#define emit_and_m32isd_imm(e, index, scale, disp, imm) emit_and_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7888
7889		#define emit_and_r32_m32abs(e, dreg, addr) emit_and_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7890		#define emit_and_r32_m32bd(e, dreg, base, disp) emit_and_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
7891		#define emit_and_r32_m32isd(e, dreg, index, scale, disp) emit_and_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7892
7893		#define emit_and_m32abs_r32(e, addr, sreg) emit_and_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7894		#define emit_and_m32bd_r32(e, base, disp, sreg) emit_and_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
7895		#define emit_and_m32isd_r32(e, index, scale, disp, sreg) emit_and_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
7896
7897
7898		/*------------------------------------------------------------------
7899		emit_sub_r32_*
7900		------------------------------------------------------------------*/
7901
7902		#define emit_sub_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 5, dreg, imm)
7903		#define emit_sub_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 5, base, index, scale, disp, imm)
7904		#define emit_sub_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 5, dreg, sreg)
7905		#define emit_sub_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 5, dreg, base, index, scale, disp)
7906		#define emit_sub_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 5, base, index, scale, disp, sreg)
7907
7908		#define emit_sub_m32abs_imm(e, addr, imm) emit_sub_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7909		#define emit_sub_m32bd_imm(e, base, disp, imm) emit_sub_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7910		#define emit_sub_m32isd_imm(e, index, scale, disp, imm) emit_sub_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7911
7912		#define emit_sub_r32_m32abs(e, dreg, addr) emit_sub_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7913		#define emit_sub_r32_m32bd(e, dreg, base, disp) emit_sub_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
7914		#define emit_sub_r32_m32isd(e, dreg, index, scale, disp) emit_sub_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7915
7916		#define emit_sub_m32abs_r32(e, addr, sreg) emit_sub_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7917		#define emit_sub_m32bd_r32(e, base, disp, sreg) emit_sub_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
7918		#define emit_sub_m32isd_r32(e, index, scale, disp, sreg) emit_sub_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
7919
7920
7921		/*------------------------------------------------------------------
7922		emit_xor_r32_*
7923		------------------------------------------------------------------*/
7924
7925		#define emit_xor_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 6, dreg, imm)
7926		#define emit_xor_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 6, base, index, scale, disp, imm)
7927		#define emit_xor_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 6, dreg, sreg)
7928		#define emit_xor_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 6, dreg, base, index, scale, disp)
7929		#define emit_xor_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 6, base, index, scale, disp, sreg)
7930
7931		#define emit_xor_m32abs_imm(e, addr, imm) emit_xor_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7932		#define emit_xor_m32bd_imm(e, base, disp, imm) emit_xor_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7933		#define emit_xor_m32isd_imm(e, index, scale, disp, imm) emit_xor_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7934
7935		#define emit_xor_r32_m32abs(e, dreg, addr) emit_xor_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7936		#define emit_xor_r32_m32bd(e, dreg, base, disp) emit_xor_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
7937		#define emit_xor_r32_m32isd(e, dreg, index, scale, disp) emit_xor_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7938
7939		#define emit_xor_m32abs_r32(e, addr, sreg) emit_xor_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7940		#define emit_xor_m32bd_r32(e, base, disp, sreg) emit_xor_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
7941		#define emit_xor_m32isd_r32(e, index, scale, disp, sreg) emit_xor_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
7942
7943
7944		/*------------------------------------------------------------------
7945		emit_cmp_r32_*
7946		------------------------------------------------------------------*/
7947
7948		#define emit_cmp_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 7, dreg, imm)
7949		#define emit_cmp_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 7, base, index, scale, disp, imm)
7950		#define emit_cmp_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 7, dreg, sreg)
7951		#define emit_cmp_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 7, dreg, base, index, scale, disp)
7952		#define emit_cmp_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 7, base, index, scale, disp, sreg)
7953
7954		#define emit_cmp_m32abs_imm(e, addr, imm) emit_cmp_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
7955		#define emit_cmp_m32bd_imm(e, base, disp, imm) emit_cmp_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
7956		#define emit_cmp_m32isd_imm(e, index, scale, disp, imm) emit_cmp_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
7957
7958		#define emit_cmp_r32_m32abs(e, dreg, addr) emit_cmp_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
7959		#define emit_cmp_r32_m32bd(e, dreg, base, disp) emit_cmp_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
7960		#define emit_cmp_r32_m32isd(e, dreg, index, scale, disp) emit_cmp_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
7961
7962		#define emit_cmp_m32abs_r32(e, addr, sreg) emit_cmp_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
7963		#define emit_cmp_m32bd_r32(e, base, disp, sreg) emit_cmp_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
7964		#define emit_cmp_m32isd_r32(e, index, scale, disp, sreg) emit_cmp_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
7965
7966
7967
7968		/***************************************************************************
7969		64-BIT ARITHMETIC EMITTERS
7970		***************************************************************************/
7971
7972	1929	#ifdef PTR64
7973		/*
7974		Note that the following code relies on this:
7975	1930
7976		00-05 or /0 = ADD
7977		08-0d or /1 = OR
7978		10-15 or /2 = ADC
7979		18-1d or /3 = SBB
7980		20-25 or /4 = AND
7981		28-2d or /5 = SUB
7982		30-35 or /6 = XOR
7983		38-3d or /7 = CMP
7984		*/
	1931	INLINE void emit_add_r64_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 0, dreg, imm); }
	1932	INLINE void emit_add_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 0, MEMPARAMS, imm); }
	1933	INLINE void emit_add_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADD_Gv_Ev, OP_64BIT, dreg, sreg); }
	1934	INLINE void emit_add_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	1935	INLINE void emit_add_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
7985	1936
7986		INLINE void emit_arith_r64_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT32 imm)
7987		{
7988		if ((INT8)imm == (INT32)imm)
7989		{
7990		emit_op_modrm_reg(emitptr, OP_G1_Ev_Ib, OP_64BIT, opindex, dreg);
7991		emit_byte(emitptr, (INT8)imm);
7992		}
7993		else
7994		{
7995		emit_op_modrm_reg(emitptr, OP_G1_Ev_Iz, OP_64BIT, opindex, dreg);
7996		emit_dword(emitptr, imm);
7997		}
7998		}
	1937	INLINE void emit_or_r64_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 1, dreg, imm); }
	1938	INLINE void emit_or_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 1, MEMPARAMS, imm); }
	1939	INLINE void emit_or_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_OR_Gv_Ev, OP_64BIT, dreg, sreg); }
	1940	INLINE void emit_or_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_OR_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	1941	INLINE void emit_or_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_OR_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
7999	1942
8000		INLINE void emit_arith_m64bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
8001		{
8002		if ((INT8)imm == (INT32)imm)
8003		{
8004		emit_op_modrm_mem(emitptr, OP_G1_Ev_Ib, OP_64BIT, opindex, base, index, scale, disp);
8005		emit_byte(emitptr, (INT8)imm);
8006		}
8007		else
8008		{
8009		emit_op_modrm_mem(emitptr, OP_G1_Ev_Iz, OP_64BIT, opindex, base, index, scale, disp);
8010		emit_dword(emitptr, imm);
8011		}
8012		}
	1943	INLINE void emit_adc_r64_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 2, dreg, imm); }
	1944	INLINE void emit_adc_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 2, MEMPARAMS, imm); }
	1945	INLINE void emit_adc_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADC_Gv_Ev, OP_64BIT, dreg, sreg); }
	1946	INLINE void emit_adc_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADC_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	1947	INLINE void emit_adc_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_ADC_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
8013	1948
8014		INLINE void emit_arith_r64_r64(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
8015		{
8016		emit_op_modrm_reg(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_64BIT, dreg, sreg);
8017		}
	1949	INLINE void emit_sbb_r64_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 3, dreg, imm); }
	1950	INLINE void emit_sbb_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 3, MEMPARAMS, imm); }
	1951	INLINE void emit_sbb_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SBB_Gv_Ev, OP_64BIT, dreg, sreg); }
	1952	INLINE void emit_sbb_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SBB_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	1953	INLINE void emit_sbb_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SBB_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
8018	1954
8019		INLINE void emit_arith_r64_m64bisd(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
8020		{
8021		emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_64BIT, dreg, base, index, scale, disp);
8022		}
	1955	INLINE void emit_and_r64_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 4, dreg, imm); }
	1956	INLINE void emit_and_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 4, MEMPARAMS, imm); }
	1957	INLINE void emit_and_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_AND_Gv_Ev, OP_64BIT, dreg, sreg); }
	1958	INLINE void emit_and_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_AND_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	1959	INLINE void emit_and_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_AND_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
8023	1960
8024		INLINE void emit_arith_m64bisd_r64(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
8025		{
8026		emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_64BIT, sreg, base, index, scale, disp);
8027		}
	1961	INLINE void emit_sub_r64_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 5, dreg, imm); }
	1962	INLINE void emit_sub_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 5, MEMPARAMS, imm); }
	1963	INLINE void emit_sub_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SUB_Gv_Ev, OP_64BIT, dreg, sreg); }
	1964	INLINE void emit_sub_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SUB_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	1965	INLINE void emit_sub_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SUB_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
8028	1966
	1967	INLINE void emit_xor_r64_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 6, dreg, imm); }
	1968	INLINE void emit_xor_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 6, MEMPARAMS, imm); }
	1969	INLINE void emit_xor_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_XOR_Gv_Ev, OP_64BIT, dreg, sreg); }
	1970	INLINE void emit_xor_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_XOR_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	1971	INLINE void emit_xor_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_XOR_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
8029	1972
8030		/*------------------------------------------------------------------
8031		emit_add_r64_*
8032		------------------------------------------------------------------*/
	1973	INLINE void emit_cmp_r64_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 7, dreg, imm); }
	1974	INLINE void emit_cmp_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_G1_Ev_Ib, OP_G1_Ev_Iz, OP_64BIT, 7, MEMPARAMS, imm); }
	1975	INLINE void emit_cmp_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CMP_Gv_Ev, OP_64BIT, dreg, sreg); }
	1976	INLINE void emit_cmp_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CMP_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	1977	INLINE void emit_cmp_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_CMP_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
8033	1978
8034		#define emit_add_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 0, dreg, imm)
8035		#define emit_add_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 0, base, index, scale, disp, imm)
8036		#define emit_add_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 0, dreg, sreg)
8037		#define emit_add_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 0, dreg, base, index, scale, disp)
8038		#define emit_add_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 0, base, index, scale, disp, sreg)
	1979	INLINE void emit_test_r64_imm(x86code **emitptr, UINT8 dreg, UINT32 imm) { emit_op_modrm_reg_imm32(emitptr, OP_G3_Ev, OP_64BIT, 0, dreg, imm); }
	1980	INLINE void emit_test_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT32 imm) { emit_op_modrm_mem_imm32(emitptr, OP_G3_Ev, OP_64BIT, 0, MEMPARAMS, imm); }
	1981	INLINE void emit_test_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_64BIT, sreg, dreg); }
	1982	INLINE void emit_test_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
8039	1983
8040		#define emit_add_m64abs_imm(e, addr, imm) emit_add_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8041		#define emit_add_m64bd_imm(e, base, disp, imm) emit_add_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8042		#define emit_add_m64isd_imm(e, index, scale, disp, imm) emit_add_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8043
8044		#define emit_add_r64_m64abs(e, dreg, addr) emit_add_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
8045		#define emit_add_r64_m64bd(e, dreg, base, disp) emit_add_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
8046		#define emit_add_r64_m64isd(e, dreg, index, scale, disp) emit_add_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
8047
8048		#define emit_add_m64abs_r64(e, addr, sreg) emit_add_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
8049		#define emit_add_m64bd_r64(e, base, disp, sreg) emit_add_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
8050		#define emit_add_m64isd_r64(e, index, scale, disp, sreg) emit_add_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
8051
8052
8053		/*------------------------------------------------------------------
8054		emit_or_r64_*
8055		------------------------------------------------------------------*/
8056
8057		#define emit_or_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 1, dreg, imm)
8058		#define emit_or_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 1, base, index, scale, disp, imm)
8059		#define emit_or_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 1, dreg, sreg)
8060		#define emit_or_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 1, dreg, base, index, scale, disp)
8061		#define emit_or_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 1, base, index, scale, disp, sreg)
8062
8063		#define emit_or_m64abs_imm(e, addr, imm) emit_or_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8064		#define emit_or_m64bd_imm(e, base, disp, imm) emit_or_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8065		#define emit_or_m64isd_imm(e, index, scale, disp, imm) emit_or_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8066
8067		#define emit_or_r64_m64abs(e, dreg, addr) emit_or_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
8068		#define emit_or_r64_m64bd(e, dreg, base, disp) emit_or_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
8069		#define emit_or_r64_m64isd(e, dreg, index, scale, disp) emit_or_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
8070
8071		#define emit_or_m64abs_r64(e, addr, sreg) emit_or_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
8072		#define emit_or_m64bd_r64(e, base, disp, sreg) emit_or_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
8073		#define emit_or_m64isd_r64(e, index, scale, disp, sreg) emit_or_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
8074
8075
8076		/*------------------------------------------------------------------
8077		emit_adc_r64_*
8078		------------------------------------------------------------------*/
8079
8080		#define emit_adc_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 2, dreg, imm)
8081		#define emit_adc_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 2, base, index, scale, disp, imm)
8082		#define emit_adc_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 2, dreg, sreg)
8083		#define emit_adc_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 2, dreg, base, index, scale, disp)
8084		#define emit_adc_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 2, base, index, scale, disp, sreg)
8085
8086		#define emit_adc_m64abs_imm(e, addr, imm) emit_adc_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8087		#define emit_adc_m64bd_imm(e, base, disp, imm) emit_adc_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8088		#define emit_adc_m64isd_imm(e, index, scale, disp, imm) emit_adc_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8089
8090		#define emit_adc_r64_m64abs(e, dreg, addr) emit_adc_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
8091		#define emit_adc_r64_m64bd(e, dreg, base, disp) emit_adc_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
8092		#define emit_adc_r64_m64isd(e, dreg, index, scale, disp) emit_adc_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
8093
8094		#define emit_adc_m64abs_r64(e, addr, sreg) emit_adc_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
8095		#define emit_adc_m64bd_r64(e, base, disp, sreg) emit_adc_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
8096		#define emit_adc_m64isd_r64(e, index, scale, disp, sreg) emit_adc_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
8097
8098
8099		/*------------------------------------------------------------------
8100		emit_sbb_r64_*
8101		------------------------------------------------------------------*/
8102
8103		#define emit_sbb_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 3, dreg, imm)
8104		#define emit_sbb_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 3, base, index, scale, disp, imm)
8105		#define emit_sbb_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 3, dreg, sreg)
8106		#define emit_sbb_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 3, dreg, base, index, scale, disp)
8107		#define emit_sbb_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 3, base, index, scale, disp, sreg)
8108
8109		#define emit_sbb_m64abs_imm(e, addr, imm) emit_sbb_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8110		#define emit_sbb_m64bd_imm(e, base, disp, imm) emit_sbb_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8111		#define emit_sbb_m64isd_imm(e, index, scale, disp, imm) emit_sbb_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8112
8113		#define emit_sbb_r64_m64abs(e, dreg, addr) emit_sbb_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
8114		#define emit_sbb_r64_m64bd(e, dreg, base, disp) emit_sbb_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
8115		#define emit_sbb_r64_m64isd(e, dreg, index, scale, disp) emit_sbb_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
8116
8117		#define emit_sbb_m64abs_r64(e, addr, sreg) emit_sbb_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
8118		#define emit_sbb_m64bd_r64(e, base, disp, sreg) emit_sbb_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
8119		#define emit_sbb_m64isd_r64(e, index, scale, disp, sreg) emit_sbb_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
8120
8121
8122		/*------------------------------------------------------------------
8123		emit_and_r64_*
8124		------------------------------------------------------------------*/
8125
8126		#define emit_and_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 4, dreg, imm)
8127		#define emit_and_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 4, base, index, scale, disp, imm)
8128		#define emit_and_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 4, dreg, sreg)
8129		#define emit_and_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 4, dreg, base, index, scale, disp)
8130		#define emit_and_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 4, base, index, scale, disp, sreg)
8131
8132		#define emit_and_m64abs_imm(e, addr, imm) emit_and_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8133		#define emit_and_m64bd_imm(e, base, disp, imm) emit_and_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8134		#define emit_and_m64isd_imm(e, index, scale, disp, imm) emit_and_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8135
8136		#define emit_and_r64_m64abs(e, dreg, addr) emit_and_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
8137		#define emit_and_r64_m64bd(e, dreg, base, disp) emit_and_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
8138		#define emit_and_r64_m64isd(e, dreg, index, scale, disp) emit_and_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
8139
8140		#define emit_and_m64abs_r64(e, addr, sreg) emit_and_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
8141		#define emit_and_m64bd_r64(e, base, disp, sreg) emit_and_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
8142		#define emit_and_m64isd_r64(e, index, scale, disp, sreg) emit_and_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
8143
8144
8145		/*------------------------------------------------------------------
8146		emit_sub_r64_*
8147		------------------------------------------------------------------*/
8148
8149		#define emit_sub_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 5, dreg, imm)
8150		#define emit_sub_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 5, base, index, scale, disp, imm)
8151		#define emit_sub_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 5, dreg, sreg)
8152		#define emit_sub_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 5, dreg, base, index, scale, disp)
8153		#define emit_sub_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 5, base, index, scale, disp, sreg)
8154
8155		#define emit_sub_m64abs_imm(e, addr, imm) emit_sub_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8156		#define emit_sub_m64bd_imm(e, base, disp, imm) emit_sub_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8157		#define emit_sub_m64isd_imm(e, index, scale, disp, imm) emit_sub_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8158
8159		#define emit_sub_r64_m64abs(e, dreg, addr) emit_sub_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
8160		#define emit_sub_r64_m64bd(e, dreg, base, disp) emit_sub_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
8161		#define emit_sub_r64_m64isd(e, dreg, index, scale, disp) emit_sub_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
8162
8163		#define emit_sub_m64abs_r64(e, addr, sreg) emit_sub_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
8164		#define emit_sub_m64bd_r64(e, base, disp, sreg) emit_sub_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
8165		#define emit_sub_m64isd_r64(e, index, scale, disp, sreg) emit_sub_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
8166
8167
8168		/*------------------------------------------------------------------
8169		emit_xor_r64_*
8170		------------------------------------------------------------------*/
8171
8172		#define emit_xor_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 6, dreg, imm)
8173		#define emit_xor_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 6, base, index, scale, disp, imm)
8174		#define emit_xor_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 6, dreg, sreg)
8175		#define emit_xor_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 6, dreg, base, index, scale, disp)
8176		#define emit_xor_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 6, base, index, scale, disp, sreg)
8177
8178		#define emit_xor_m64abs_imm(e, addr, imm) emit_xor_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8179		#define emit_xor_m64bd_imm(e, base, disp, imm) emit_xor_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8180		#define emit_xor_m64isd_imm(e, index, scale, disp, imm) emit_xor_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8181
8182		#define emit_xor_r64_m64abs(e, dreg, addr) emit_xor_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
8183		#define emit_xor_r64_m64bd(e, dreg, base, disp) emit_xor_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
8184		#define emit_xor_r64_m64isd(e, dreg, index, scale, disp) emit_xor_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
8185
8186		#define emit_xor_m64abs_r64(e, addr, sreg) emit_xor_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
8187		#define emit_xor_m64bd_r64(e, base, disp, sreg) emit_xor_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
8188		#define emit_xor_m64isd_r64(e, index, scale, disp, sreg) emit_xor_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
8189
8190
8191		/*------------------------------------------------------------------
8192		emit_cmp_r64_*
8193		------------------------------------------------------------------*/
8194
8195		#define emit_cmp_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 7, dreg, imm)
8196		#define emit_cmp_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 7, base, index, scale, disp, imm)
8197		#define emit_cmp_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 7, dreg, sreg)
8198		#define emit_cmp_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 7, dreg, base, index, scale, disp)
8199		#define emit_cmp_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 7, base, index, scale, disp, sreg)
8200
8201		#define emit_cmp_m64abs_imm(e, addr, imm) emit_cmp_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8202		#define emit_cmp_m64bd_imm(e, base, disp, imm) emit_cmp_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8203		#define emit_cmp_m64isd_imm(e, index, scale, disp, imm) emit_cmp_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8204
8205		#define emit_cmp_r64_m64abs(e, dreg, addr) emit_cmp_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
8206		#define emit_cmp_r64_m64bd(e, dreg, base, disp) emit_cmp_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
8207		#define emit_cmp_r64_m64isd(e, dreg, index, scale, disp) emit_cmp_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
8208
8209		#define emit_cmp_m64abs_r64(e, addr, sreg) emit_cmp_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
8210		#define emit_cmp_m64bd_r64(e, base, disp, sreg) emit_cmp_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
8211		#define emit_cmp_m64isd_r64(e, index, scale, disp, sreg) emit_cmp_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
8212
8213	1984	#endif
8214	1985
8215	1986
8216	1987
8217	1988	/***************************************************************************
8218		~~8-BIT~~ SHIFT EMITTERS
	1989	SHIFT EMITTERS
8219	1990	***************************************************************************/
8220	1991
8221		/*
8222		Note that the following code relies on this:
	1992	/*-------------------------------------------------
	1993	emit_shift_reg_imm
	1994	-------------------------------------------------*/
8223	1995
8224		/0 = ROL
8225		/1 = ROR
8226		/2 = RCL
8227		/3 = RCR
8228		/4 = SHL
8229		/5 = SHR
8230		/7 = SAR
8231		*/
8232
8233		/*------------------------------------------------------------------
8234		emit_shift_r8_*
8235		------------------------------------------------------------------*/
8236
8237		INLINE void emit_shift_r8_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
	1996	INLINE void emit_shift_reg_imm(x86code **emitptr, UINT32 op1, UINT32 opn, UINT8 opsize, UINT8 opindex, UINT8 dreg, UINT8 imm)
8238	1997	{
8239	1998	if (imm == 1)
8240		emit_op_modrm_reg(emitptr, ~~OP_G2_Eb_~~1, OP_32BIT, opindex, dreg);
	1999	emit_op_modrm_reg(emitptr, op1, OP_32BIT, opindex, dreg);
8241	2000	else
8242		{
8243		emit_op_modrm_reg(emitptr, OP_G2_Eb_Ib, OP_32BIT, opindex, dreg);
8244		emit_byte(emitptr, imm);
8245		}
	2001	emit_op_modrm_reg_imm8(emitptr, opn, OP_32BIT, opindex, dreg, imm);
8246	2002	}
8247	2003
8248		INLINE void emit_shift_m~~8bisd~~_imm(x86code **emitptr, UINT8 op~~index~~, UINT8 ~~base~~, UINT8 index, UINT8 ~~scal~~e, ~~INT32 disp~~, UINT8 imm)
	2004	INLINE void emit_shift_mem_imm(x86code **emitptr, UINT32 op1, UINT32 opn, UINT8 opsize, UINT8 opindex, DECLARE_MEMPARAMS, UINT8 imm)
8249	2005	{
8250	2006	if (imm == 1)
8251		emit_op_modrm_mem(emitptr, ~~OP_G2_Eb_~~1, OP_32BIT, opindex, ~~base, index, scale, disp~~);
	2007	emit_op_modrm_mem(emitptr, op1, OP_32BIT, opindex, MEMPARAMS);
8252	2008	else
8253		{
8254		emit_op_modrm_mem(emitptr, OP_G2_Eb_Ib, OP_32BIT, opindex, base, index, scale, disp);
8255		emit_byte(emitptr, imm);
8256		}
	2009	emit_op_modrm_mem_imm8(emitptr, opn, OP_32BIT, opindex, MEMPARAMS, imm);
8257	2010	}
8258	2011
8259		INLINE void emit_shift_r8_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
8260		{
8261		emit_op_modrm_reg(emitptr, OP_G2_Eb_CL, OP_32BIT, opindex, dreg);
8262		}
8263	2012
8264		INLINE void emit_shift_m8bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
8265		{
8266		emit_op_modrm_mem(emitptr, OP_G2_Eb_CL, OP_32BIT, opindex, base, index, scale, disp);
8267		}
	2013	/*-------------------------------------------------
	2014	emit_shift_r8_*
	2015	-------------------------------------------------*/
8268	2016
	2017	INLINE void emit_rol_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 0, dreg, imm); }
	2018	INLINE void emit_rol_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 0, MEMPARAMS, imm); }
	2019	INLINE void emit_rol_r8_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Eb_CL, OP_32BIT, 0, dreg); }
	2020	INLINE void emit_rol_m8_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Eb_CL, OP_32BIT, 0, MEMPARAMS); }
8269	2021
8270		/*------------------------------------------------------------------
8271		emit_rol_r8_*
8272		------------------------------------------------------------------*/
	2022	INLINE void emit_ror_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 1, dreg, imm); }
	2023	INLINE void emit_ror_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 1, MEMPARAMS, imm); }
	2024	INLINE void emit_ror_r8_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Eb_CL, OP_32BIT, 1, dreg); }
	2025	INLINE void emit_ror_m8_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Eb_CL, OP_32BIT, 1, MEMPARAMS); }
8273	2026
8274		#define emit_rol_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 0, dreg, imm)
8275		#define emit_rol_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 0, base, index, scale, disp, imm)
8276		#define emit_rol_r8_cl(e, dreg) emit_shift_r8_cl(e, 0, dreg)
8277		#define emit_rol_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 0, base, index, scale, disp)
	2027	INLINE void emit_rcl_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 2, dreg, imm); }
	2028	INLINE void emit_rcl_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 2, MEMPARAMS, imm); }
	2029	INLINE void emit_rcl_r8_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Eb_CL, OP_32BIT, 2, dreg); }
	2030	INLINE void emit_rcl_m8_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Eb_CL, OP_32BIT, 2, MEMPARAMS); }
8278	2031
8279		#define emit_rol_m8abs_imm(e, addr, imm) emit_rol_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8280		#define emit_rol_m8bd_imm(e, base, disp, imm) emit_rol_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8281		#define emit_rol_m8isd_imm(e, index, scale, disp, imm) emit_rol_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2032	INLINE void emit_rcr_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 3, dreg, imm); }
	2033	INLINE void emit_rcr_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 3, MEMPARAMS, imm); }
	2034	INLINE void emit_rcr_r8_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Eb_CL, OP_32BIT, 3, dreg); }
	2035	INLINE void emit_rcr_m8_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Eb_CL, OP_32BIT, 3, MEMPARAMS); }
8282	2036
8283		#define emit_rol_m8abs_cl(e, addr) emit_rol_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8284		#define emit_rol_m8bd_cl(e, base, disp) emit_rol_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
8285		#define emit_rol_m8isd_cl(e, index, scale, disp) emit_rol_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
	2037	INLINE void emit_shl_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 4, dreg, imm); }
	2038	INLINE void emit_shl_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 4, MEMPARAMS, imm); }
	2039	INLINE void emit_shl_r8_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Eb_CL, OP_32BIT, 4, dreg); }
	2040	INLINE void emit_shl_m8_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Eb_CL, OP_32BIT, 4, MEMPARAMS); }
8286	2041
	2042	INLINE void emit_shr_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 5, dreg, imm); }
	2043	INLINE void emit_shr_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 5, MEMPARAMS, imm); }
	2044	INLINE void emit_shr_r8_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Eb_CL, OP_32BIT, 5, dreg); }
	2045	INLINE void emit_shr_m8_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Eb_CL, OP_32BIT, 5, MEMPARAMS); }
8287	2046
8288		/*------------------------------------------------------------------
8289		emit_ror_r8_*
8290		------------------------------------------------------------------*/
	2047	INLINE void emit_sar_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 7, dreg, imm); }
	2048	INLINE void emit_sar_m8_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Eb_1, OP_G2_Eb_Ib, OP_32BIT, 7, MEMPARAMS, imm); }
	2049	INLINE void emit_sar_r8_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Eb_CL, OP_32BIT, 7, dreg); }
	2050	INLINE void emit_sar_m8_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Eb_CL, OP_32BIT, 7, MEMPARAMS); }
8291	2051
8292		#define emit_ror_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 1, dreg, imm)
8293		#define emit_ror_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 1, base, index, scale, disp, imm)
8294		#define emit_ror_r8_cl(e, dreg) emit_shift_r8_cl(e, 1, dreg)
8295		#define emit_ror_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 1, base, index, scale, disp)
8296	2052
8297		#define emit_ror_m8abs_imm(e, addr, imm) emit_ror_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8298		#define emit_ror_m8bd_imm(e, base, disp, imm) emit_ror_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8299		#define emit_ror_m8isd_imm(e, index, scale, disp, imm) emit_ror_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8300
8301		#define emit_ror_m8abs_cl(e, addr) emit_ror_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8302		#define emit_ror_m8bd_cl(e, base, disp) emit_ror_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
8303		#define emit_ror_m8isd_cl(e, index, scale, disp) emit_ror_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
8304
8305
8306		/*------------------------------------------------------------------
8307		emit_rcl_r8_*
8308		------------------------------------------------------------------*/
8309
8310		#define emit_rcl_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 2, dreg, imm)
8311		#define emit_rcl_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 2, base, index, scale, disp, imm)
8312		#define emit_rcl_r8_cl(e, dreg) emit_shift_r8_cl(e, 2, dreg)
8313		#define emit_rcl_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 2, base, index, scale, disp)
8314
8315		#define emit_rcl_m8abs_imm(e, addr, imm) emit_rcl_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8316		#define emit_rcl_m8bd_imm(e, base, disp, imm) emit_rcl_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8317		#define emit_rcl_m8isd_imm(e, index, scale, disp, imm) emit_rcl_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8318
8319		#define emit_rcl_m8abs_cl(e, addr) emit_rcl_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8320		#define emit_rcl_m8bd_cl(e, base, disp) emit_rcl_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
8321		#define emit_rcl_m8isd_cl(e, index, scale, disp) emit_rcl_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
8322
8323
8324		/*------------------------------------------------------------------
8325		emit_rcr_r8_*
8326		------------------------------------------------------------------*/
8327
8328		#define emit_rcr_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 3, dreg, imm)
8329		#define emit_rcr_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 3, base, index, scale, disp, imm)
8330		#define emit_rcr_r8_cl(e, dreg) emit_shift_r8_cl(e, 3, dreg)
8331		#define emit_rcr_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 3, base, index, scale, disp)
8332
8333		#define emit_rcr_m8abs_imm(e, addr, imm) emit_rcr_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8334		#define emit_rcr_m8bd_imm(e, base, disp, imm) emit_rcr_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8335		#define emit_rcr_m8isd_imm(e, index, scale, disp, imm) emit_rcr_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8336
8337		#define emit_rcr_m8abs_cl(e, addr) emit_rcr_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8338		#define emit_rcr_m8bd_cl(e, base, disp) emit_rcr_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
8339		#define emit_rcr_m8isd_cl(e, index, scale, disp) emit_rcr_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
8340
8341
8342		/*------------------------------------------------------------------
8343		emit_shl_r8_*
8344		------------------------------------------------------------------*/
8345
8346		#define emit_shl_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 4, dreg, imm)
8347		#define emit_shl_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 4, base, index, scale, disp, imm)
8348		#define emit_shl_r8_cl(e, dreg) emit_shift_r8_cl(e, 4, dreg)
8349		#define emit_shl_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 4, base, index, scale, disp)
8350
8351		#define emit_shl_m8abs_imm(e, addr, imm) emit_shl_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8352		#define emit_shl_m8bd_imm(e, base, disp, imm) emit_shl_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8353		#define emit_shl_m8isd_imm(e, index, scale, disp, imm) emit_shl_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8354
8355		#define emit_shl_m8abs_cl(e, addr) emit_shl_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8356		#define emit_shl_m8bd_cl(e, base, disp) emit_shl_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
8357		#define emit_shl_m8isd_cl(e, index, scale, disp) emit_shl_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
8358
8359
8360		/*------------------------------------------------------------------
8361		emit_shr_r8_*
8362		------------------------------------------------------------------*/
8363
8364		#define emit_shr_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 5, dreg, imm)
8365		#define emit_shr_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 5, base, index, scale, disp, imm)
8366		#define emit_shr_r8_cl(e, dreg) emit_shift_r8_cl(e, 5, dreg)
8367		#define emit_shr_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 5, base, index, scale, disp)
8368
8369		#define emit_shr_m8abs_imm(e, addr, imm) emit_shr_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8370		#define emit_shr_m8bd_imm(e, base, disp, imm) emit_shr_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8371		#define emit_shr_m8isd_imm(e, index, scale, disp, imm) emit_shr_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8372
8373		#define emit_shr_m8abs_cl(e, addr) emit_shr_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8374		#define emit_shr_m8bd_cl(e, base, disp) emit_shr_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
8375		#define emit_shr_m8isd_cl(e, index, scale, disp) emit_shr_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
8376
8377
8378		/*------------------------------------------------------------------
8379		emit_sar_r8_*
8380		------------------------------------------------------------------*/
8381
8382		#define emit_sar_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 7, dreg, imm)
8383		#define emit_sar_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 7, base, index, scale, disp, imm)
8384		#define emit_sar_r8_cl(e, dreg) emit_shift_r8_cl(e, 7, dreg)
8385		#define emit_sar_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 7, base, index, scale, disp)
8386
8387		#define emit_sar_m8abs_imm(e, addr, imm) emit_sar_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8388		#define emit_sar_m8bd_imm(e, base, disp, imm) emit_sar_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8389		#define emit_sar_m8isd_imm(e, index, scale, disp, imm) emit_sar_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8390
8391		#define emit_sar_m8abs_cl(e, addr) emit_sar_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8392		#define emit_sar_m8bd_cl(e, base, disp) emit_sar_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
8393		#define emit_sar_m8isd_cl(e, index, scale, disp) emit_sar_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
8394
8395
8396
8397		/***************************************************************************
8398		16-BIT SHIFT EMITTERS
8399		***************************************************************************/
8400
8401		/*
8402		Note that the following code relies on this:
8403
8404		/0 = ROL
8405		/1 = ROR
8406		/2 = RCL
8407		/3 = RCR
8408		/4 = SHL
8409		/5 = SHR
8410		/7 = SAR
8411		*/
8412
8413		/*------------------------------------------------------------------
	2053	/*-------------------------------------------------
8414	2054	emit_shift_r16_*
8415		-------------------------------------------------~~-----------------~~*/
	2055	-------------------------------------------------*/
8416	2056
8417		INLINE void emit_shift_r16_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
8418		{
8419		emit_byte(emitptr, PREFIX_OPSIZE);
8420		if (imm == 1)
8421		emit_op_modrm_reg(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, dreg);
8422		else
8423		{
8424		emit_op_modrm_reg(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, dreg);
8425		emit_byte(emitptr, imm);
8426		}
8427		}
	2057	INLINE void emit_rol_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 0, dreg, imm); }
	2058	INLINE void emit_rol_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 0, MEMPARAMS, imm); }
	2059	INLINE void emit_rol_r16_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_16BIT, 0, dreg); }
	2060	INLINE void emit_rol_m16_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_16BIT, 0, MEMPARAMS); }
8428	2061
8429		INLINE void emit_shift_m16bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
8430		{
8431		emit_byte(emitptr, PREFIX_OPSIZE);
8432		if (imm == 1)
8433		emit_op_modrm_mem(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, base, index, scale, disp);
8434		else
8435		{
8436		emit_op_modrm_mem(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
8437		emit_byte(emitptr, imm);
8438		}
8439		}
	2062	INLINE void emit_ror_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 1, dreg, imm); }
	2063	INLINE void emit_ror_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 1, MEMPARAMS, imm); }
	2064	INLINE void emit_ror_r16_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_16BIT, 1, dreg); }
	2065	INLINE void emit_ror_m16_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_16BIT, 1, MEMPARAMS); }
8440	2066
8441		INLINE void emit_shift_r16_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
8442		{
8443		emit_byte(emitptr, PREFIX_OPSIZE);
8444		emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, dreg);
8445		}
	2067	INLINE void emit_rcl_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 2, dreg, imm); }
	2068	INLINE void emit_rcl_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 2, MEMPARAMS, imm); }
	2069	INLINE void emit_rcl_r16_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_16BIT, 2, dreg); }
	2070	INLINE void emit_rcl_m16_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_16BIT, 2, MEMPARAMS); }
8446	2071
8447		INLINE void emit_shift_m16bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
8448		{
8449		emit_byte(emitptr, PREFIX_OPSIZE);
8450		emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, base, index, scale, disp);
8451		}
	2072	INLINE void emit_rcr_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 3, dreg, imm); }
	2073	INLINE void emit_rcr_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 3, MEMPARAMS, imm); }
	2074	INLINE void emit_rcr_r16_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_16BIT, 3, dreg); }
	2075	INLINE void emit_rcr_m16_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_16BIT, 3, MEMPARAMS); }
8452	2076
	2077	INLINE void emit_shl_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 4, dreg, imm); }
	2078	INLINE void emit_shl_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 4, MEMPARAMS, imm); }
	2079	INLINE void emit_shl_r16_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_16BIT, 4, dreg); }
	2080	INLINE void emit_shl_m16_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_16BIT, 4, MEMPARAMS); }
8453	2081
8454		/*------------------------------------------------------------------
8455		emit_rol_r16_*
8456		------------------------------------------------------------------*/
	2082	INLINE void emit_shr_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 5, dreg, imm); }
	2083	INLINE void emit_shr_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 5, MEMPARAMS, imm); }
	2084	INLINE void emit_shr_r16_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_16BIT, 5, dreg); }
	2085	INLINE void emit_shr_m16_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_16BIT, 5, MEMPARAMS); }
8457	2086
8458		#define emit_rol_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 0, dreg, imm)
8459		#define emit_rol_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 0, base, index, scale, disp, imm)
8460		#define emit_rol_r16_cl(e, dreg) emit_shift_r16_cl(e, 0, dreg)
8461		#define emit_rol_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 0, base, index, scale, disp)
	2087	INLINE void emit_sar_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 7, dreg, imm); }
	2088	INLINE void emit_sar_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_16BIT, 7, MEMPARAMS, imm); }
	2089	INLINE void emit_sar_r16_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_16BIT, 7, dreg); }
	2090	INLINE void emit_sar_m16_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_16BIT, 7, MEMPARAMS); }
8462	2091
8463		#define emit_rol_m16abs_imm(e, addr, imm) emit_rol_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8464		#define emit_rol_m16bd_imm(e, base, disp, imm) emit_rol_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8465		#define emit_rol_m16isd_imm(e, index, scale, disp, imm) emit_rol_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8466	2092
8467		#define emit_rol_m16abs_cl(e, addr) emit_rol_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8468		#define emit_rol_m16bd_cl(e, base, disp) emit_rol_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
8469		#define emit_rol_m16isd_cl(e, index, scale, disp) emit_rol_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
	2093	/*-------------------------------------------------
	2094	emit_shift_r32_*
	2095	-------------------------------------------------*/
8470	2096
	2097	INLINE void emit_rol_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 0, dreg, imm); }
	2098	INLINE void emit_rol_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 0, MEMPARAMS, imm); }
	2099	INLINE void emit_rol_r32_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, 0, dreg); }
	2100	INLINE void emit_rol_m32_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, 0, MEMPARAMS); }
8471	2101
8472		/*------------------------------------------------------------------
8473		emit_ror_r16_*
8474		------------------------------------------------------------------*/
	2102	INLINE void emit_ror_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 1, dreg, imm); }
	2103	INLINE void emit_ror_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 1, MEMPARAMS, imm); }
	2104	INLINE void emit_ror_r32_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, 1, dreg); }
	2105	INLINE void emit_ror_m32_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, 1, MEMPARAMS); }
8475	2106
8476		#define emit_ror_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 1, dreg, imm)
8477		#define emit_ror_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 1, base, index, scale, disp, imm)
8478		#define emit_ror_r16_cl(e, dreg) emit_shift_r16_cl(e, 1, dreg)
8479		#define emit_ror_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 1, base, index, scale, disp)
	2107	INLINE void emit_rcl_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 2, dreg, imm); }
	2108	INLINE void emit_rcl_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 2, MEMPARAMS, imm); }
	2109	INLINE void emit_rcl_r32_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, 2, dreg); }
	2110	INLINE void emit_rcl_m32_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, 2, MEMPARAMS); }
8480	2111
8481		#define emit_ror_m16abs_imm(e, addr, imm) emit_ror_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8482		#define emit_ror_m16bd_imm(e, base, disp, imm) emit_ror_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8483		#define emit_ror_m16isd_imm(e, index, scale, disp, imm) emit_ror_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2112	INLINE void emit_rcr_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 3, dreg, imm); }
	2113	INLINE void emit_rcr_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 3, MEMPARAMS, imm); }
	2114	INLINE void emit_rcr_r32_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, 3, dreg); }
	2115	INLINE void emit_rcr_m32_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, 3, MEMPARAMS); }
8484	2116
8485		#define emit_ror_m16abs_cl(e, addr) emit_ror_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8486		#define emit_ror_m16bd_cl(e, base, disp) emit_ror_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
8487		#define emit_ror_m16isd_cl(e, index, scale, disp) emit_ror_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
	2117	INLINE void emit_shl_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 4, dreg, imm); }
	2118	INLINE void emit_shl_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 4, MEMPARAMS, imm); }
	2119	INLINE void emit_shl_r32_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, 4, dreg); }
	2120	INLINE void emit_shl_m32_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, 4, MEMPARAMS); }
8488	2121
	2122	INLINE void emit_shr_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 5, dreg, imm); }
	2123	INLINE void emit_shr_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 5, MEMPARAMS, imm); }
	2124	INLINE void emit_shr_r32_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, 5, dreg); }
	2125	INLINE void emit_shr_m32_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, 5, MEMPARAMS); }
8489	2126
8490		/*------------------------------------------------------------------
8491		emit_rcl_r16_*
8492		------------------------------------------------------------------*/
	2127	INLINE void emit_sar_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 7, dreg, imm); }
	2128	INLINE void emit_sar_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_32BIT, 7, MEMPARAMS, imm); }
	2129	INLINE void emit_sar_r32_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, 7, dreg); }
	2130	INLINE void emit_sar_m32_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, 7, MEMPARAMS); }
8493	2131
8494		#define emit_rcl_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 2, dreg, imm)
8495		#define emit_rcl_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 2, base, index, scale, disp, imm)
8496		#define emit_rcl_r16_cl(e, dreg) emit_shift_r16_cl(e, 2, dreg)
8497		#define emit_rcl_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 2, base, index, scale, disp)
	2132	INLINE void emit_shld_r32_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 sreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_SHLD_Ev_Gv_Ib, OP_32BIT, sreg, dreg, imm); }
	2133	INLINE void emit_shld_m32_r32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_SHLD_Ev_Gv_Ib, OP_32BIT, sreg, MEMPARAMS, imm); }
	2134	INLINE void emit_shld_r32_r32_cl(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SHLD_Ev_Gv_CL, OP_32BIT, sreg, dreg); }
	2135	INLINE void emit_shld_m32_r32_cl(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SHLD_Ev_Gv_CL, OP_32BIT, sreg, MEMPARAMS); }
8498	2136
8499		#define emit_rcl_m16abs_imm(e, addr, imm) emit_rcl_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8500		#define emit_rcl_m16bd_imm(e, base, disp, imm) emit_rcl_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8501		#define emit_rcl_m16isd_imm(e, index, scale, disp, imm) emit_rcl_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2137	INLINE void emit_shrd_r32_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 sreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_SHRD_Ev_Gv_Ib, OP_32BIT, sreg, dreg, imm); }
	2138	INLINE void emit_shrd_m32_r32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_SHRD_Ev_Gv_Ib, OP_32BIT, sreg, MEMPARAMS, imm); }
	2139	INLINE void emit_shrd_r32_r32_cl(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SHRD_Ev_Gv_CL, OP_32BIT, sreg, dreg); }
	2140	INLINE void emit_shrd_m32_r32_cl(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SHRD_Ev_Gv_CL, OP_32BIT, sreg, MEMPARAMS); }
8502	2141
8503		#define emit_rcl_m16abs_cl(e, addr) emit_rcl_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8504		#define emit_rcl_m16bd_cl(e, base, disp) emit_rcl_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
8505		#define emit_rcl_m16isd_cl(e, index, scale, disp) emit_rcl_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
8506	2142
	2143	/*-------------------------------------------------
	2144	emit_shift_r64_*
	2145	-------------------------------------------------*/
8507	2146
8508		/*------------------------------------------------------------------
8509		emit_rcr_r16_*
8510		------------------------------------------------------------------*/
	2147	#ifdef PTR64
8511	2148
8512		#define emit_rcr_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 3, dreg, imm)
8513		#define emit_rcr_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 31, base, index, scale, disp, imm)
8514		#define emit_rcr_r16_cl(e, dreg) emit_shift_r16_cl(e, 3, dreg)
8515		#define emit_rcr_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 3, base, index, scale, disp)
	2149	INLINE void emit_rol_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 0, dreg, imm); }
	2150	INLINE void emit_rol_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 0, MEMPARAMS, imm); }
	2151	INLINE void emit_rol_r64_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_64BIT, 0, dreg); }
	2152	INLINE void emit_rol_m64_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_64BIT, 0, MEMPARAMS); }
8516	2153
8517		#define emit_rcr_m16abs_imm(e, addr, imm) emit_rcr_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8518		#define emit_rcr_m16bd_imm(e, base, disp, imm) emit_rcr_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8519		#define emit_rcr_m16isd_imm(e, index, scale, disp, imm) emit_rcr_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2154	INLINE void emit_ror_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 1, dreg, imm); }
	2155	INLINE void emit_ror_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 1, MEMPARAMS, imm); }
	2156	INLINE void emit_ror_r64_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_64BIT, 1, dreg); }
	2157	INLINE void emit_ror_m64_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_64BIT, 1, MEMPARAMS); }
8520	2158
8521		#define emit_rcr_m16abs_cl(e, addr) emit_rcr_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8522		#define emit_rcr_m16bd_cl(e, base, disp) emit_rcr_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
8523		#define emit_rcr_m16isd_cl(e, index, scale, disp) emit_rcr_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
	2159	INLINE void emit_rcl_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 2, dreg, imm); }
	2160	INLINE void emit_rcl_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 2, MEMPARAMS, imm); }
	2161	INLINE void emit_rcl_r64_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_64BIT, 2, dreg); }
	2162	INLINE void emit_rcl_m64_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_64BIT, 2, MEMPARAMS); }
8524	2163
	2164	INLINE void emit_rcr_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 3, dreg, imm); }
	2165	INLINE void emit_rcr_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 3, MEMPARAMS, imm); }
	2166	INLINE void emit_rcr_r64_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_64BIT, 3, dreg); }
	2167	INLINE void emit_rcr_m64_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_64BIT, 3, MEMPARAMS); }
8525	2168
8526		/*------------------------------------------------------------------
8527		emit_shl_r16_*
8528		------------------------------------------------------------------*/
	2169	INLINE void emit_shl_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 4, dreg, imm); }
	2170	INLINE void emit_shl_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 4, MEMPARAMS, imm); }
	2171	INLINE void emit_shl_r64_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_64BIT, 4, dreg); }
	2172	INLINE void emit_shl_m64_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_64BIT, 4, MEMPARAMS); }
8529	2173
8530		#define emit_shl_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 4, dreg, imm)
8531		#define emit_shl_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 4, base, index, scale, disp, imm)
8532		#define emit_shl_r16_cl(e, dreg) emit_shift_r16_cl(e, 4, dreg)
8533		#define emit_shl_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 4, base, index, scale, disp)
	2174	INLINE void emit_shr_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 5, dreg, imm); }
	2175	INLINE void emit_shr_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 5, MEMPARAMS, imm); }
	2176	INLINE void emit_shr_r64_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_64BIT, 5, dreg); }
	2177	INLINE void emit_shr_m64_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_64BIT, 5, MEMPARAMS); }
8534	2178
8535		#define emit_shl_m16abs_imm(e, addr, imm) emit_shl_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8536		#define emit_shl_m16bd_imm(e, base, disp, imm) emit_shl_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8537		#define emit_shl_m16isd_imm(e, index, scale, disp, imm) emit_shl_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2179	INLINE void emit_sar_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_shift_reg_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 7, dreg, imm); }
	2180	INLINE void emit_sar_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_shift_mem_imm(emitptr, OP_G2_Ev_1, OP_G2_Ev_Ib, OP_64BIT, 7, MEMPARAMS, imm); }
	2181	INLINE void emit_sar_r64_cl(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_64BIT, 7, dreg); }
	2182	INLINE void emit_sar_m64_cl(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_64BIT, 7, MEMPARAMS); }
8538	2183
8539		#define emit_shl_m16abs_cl(e, addr) emit_shl_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8540		#define emit_shl_m16bd_cl(e, base, disp) emit_shl_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
8541		#define emit_shl_m16isd_cl(e, index, scale, disp) emit_shl_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
	2184	INLINE void emit_shld_r64_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 sreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_SHLD_Ev_Gv_Ib, OP_64BIT, sreg, dreg, imm); }
	2185	INLINE void emit_shld_m64_r64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_SHLD_Ev_Gv_Ib, OP_64BIT, sreg, MEMPARAMS, imm); }
	2186	INLINE void emit_shld_r64_r64_cl(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SHLD_Ev_Gv_CL, OP_64BIT, sreg, dreg); }
	2187	INLINE void emit_shld_m64_r64_cl(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SHLD_Ev_Gv_CL, OP_64BIT, sreg, MEMPARAMS); }
8542	2188
	2189	INLINE void emit_shrd_r64_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 sreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_SHRD_Ev_Gv_Ib, OP_64BIT, sreg, dreg, imm); }
	2190	INLINE void emit_shrd_m64_r64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_SHRD_Ev_Gv_Ib, OP_64BIT, sreg, MEMPARAMS, imm); }
	2191	INLINE void emit_shrd_r64_r64_cl(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SHRD_Ev_Gv_CL, OP_64BIT, sreg, dreg); }
	2192	INLINE void emit_shrd_m64_r64_cl(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_SHRD_Ev_Gv_CL, OP_64BIT, sreg, MEMPARAMS); }
8543	2193
8544		/*------------------------------------------------------------------
8545		emit_shr_r16_*
8546		------------------------------------------------------------------*/
	2194	#endif
8547	2195
8548		#define emit_shr_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 5, dreg, imm)
8549		#define emit_shr_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 5, base, index, scale, disp, imm)
8550		#define emit_shr_r16_cl(e, dreg) emit_shift_r16_cl(e, 5, dreg)
8551		#define emit_shr_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 5, base, index, scale, disp)
8552	2196
8553		#define emit_shr_m16abs_imm(e, addr, imm) emit_shr_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8554		#define emit_shr_m16bd_imm(e, base, disp, imm) emit_shr_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8555		#define emit_shr_m16isd_imm(e, index, scale, disp, imm) emit_shr_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8556	2197
8557		#define emit_shr_m16abs_cl(e, addr) emit_shr_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8558		#define emit_shr_m16bd_cl(e, base, disp) emit_shr_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
8559		#define emit_shr_m16isd_cl(e, index, scale, disp) emit_shr_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
8560
8561
8562		/*------------------------------------------------------------------
8563		emit_sar_r16_*
8564		------------------------------------------------------------------*/
8565
8566		#define emit_sar_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 7, dreg, imm)
8567		#define emit_sar_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 7, base, index, scale, disp, imm)
8568		#define emit_sar_r16_cl(e, dreg) emit_shift_r16_cl(e, 7, dreg)
8569		#define emit_sar_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 7, base, index, scale, disp)
8570
8571		#define emit_sar_m16abs_imm(e, addr, imm) emit_sar_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8572		#define emit_sar_m16bd_imm(e, base, disp, imm) emit_sar_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8573		#define emit_sar_m16isd_imm(e, index, scale, disp, imm) emit_sar_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8574
8575		#define emit_sar_m16abs_cl(e, addr) emit_sar_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8576		#define emit_sar_m16bd_cl(e, base, disp) emit_sar_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
8577		#define emit_sar_m16isd_cl(e, index, scale, disp) emit_sar_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
8578
8579
8580
8581	2198	/***************************************************************************
8582		3~~2-BIT SHIFT~~ EMITTERS
	2199	GROUP3 EMITTERS
8583	2200	***************************************************************************/
8584	2201
8585		/*
8586		Note that the following code relies on this:
	2202	/*-------------------------------------------------
	2203	emit_group3_r8_*
	2204	-------------------------------------------------*/
8587	2205
8588		/0 = ROL
8589		/1 = ROR
8590		/2 = RCL
8591		/3 = RCR
8592		/4 = SHL
8593		/5 = SHR
8594		/7 = SAR
8595		*/
	2206	INLINE void emit_not_r8(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 2, dreg); }
	2207	INLINE void emit_not_m8(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 2, MEMPARAMS); }
8596	2208
8597		/*------------------------------------------------------------------
8598		emit_shift_r32_*
8599		------------------------------------------------------------------*/
	2209	INLINE void emit_neg_r8(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 3, dreg); }
	2210	INLINE void emit_neg_m8(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 3, MEMPARAMS); }
8600	2211
8601		INLINE void emit_shift_r32_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
8602		{
8603		if (imm == 1)
8604		emit_op_modrm_reg(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, dreg);
8605		else
8606		{
8607		emit_op_modrm_reg(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, dreg);
8608		emit_byte(emitptr, imm);
8609		}
8610		}
	2212	INLINE void emit_mul_r8(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 4, dreg); }
	2213	INLINE void emit_mul_m8(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 4, MEMPARAMS); }
8611	2214
8612		INLINE void emit_shift_m32bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
8613		{
8614		if (imm == 1)
8615		emit_op_modrm_mem(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, base, index, scale, disp);
8616		else
8617		{
8618		emit_op_modrm_mem(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
8619		emit_byte(emitptr, imm);
8620		}
8621		}
	2215	INLINE void emit_imul_r8(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 5, dreg); }
	2216	INLINE void emit_imul_m8(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 5, MEMPARAMS); }
8622	2217
8623		INLINE void emit_shift_r32_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
8624		{
8625		emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, dreg);
8626		}
	2218	INLINE void emit_div_r8(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 6, dreg); }
	2219	INLINE void emit_div_m8(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 6, MEMPARAMS); }
8627	2220
8628		INLINE void emit_shift_m32bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
8629		{
8630		emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, base, index, scale, disp);
8631		}
	2221	INLINE void emit_idiv_r8(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 7, dreg); }
	2222	INLINE void emit_idiv_m8(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 7, MEMPARAMS); }
8632	2223
8633	2224
8634		/*------------------------------------------------------------------
8635		emit_rol_r32_*
8636		------------------------------------------------------------------*/
	2225	/*-------------------------------------------------
	2226	emit_group3_r16_*
	2227	-------------------------------------------------*/
8637	2228
8638		#define emit_rol_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 0, dreg, imm)
8639		#define emit_rol_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 0, base, index, scale, disp, imm)
8640		#define emit_rol_r32_cl(e, dreg) emit_shift_r32_cl(e, 0, dreg)
8641		#define emit_rol_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 0, base, index, scale, disp)
	2229	INLINE void emit_not_r16(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_16BIT, 2, dreg); }
	2230	INLINE void emit_not_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_16BIT, 2, MEMPARAMS); }
8642	2231
8643		#define emit_rol_m32abs_imm(e, addr, imm) emit_rol_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8644		#define emit_rol_m32bd_imm(e, base, disp, imm) emit_rol_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8645		#define emit_rol_m32isd_imm(e, index, scale, disp, imm) emit_rol_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2232	INLINE void emit_neg_r16(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_16BIT, 3, dreg); }
	2233	INLINE void emit_neg_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_16BIT, 3, MEMPARAMS); }
8646	2234
8647		#define emit_rol_m32abs_cl(e, addr) emit_rol_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8648		#define emit_rol_m32bd_cl(e, base, disp) emit_rol_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
8649		#define emit_rol_m32isd_cl(e, index, scale, disp) emit_rol_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	2235	INLINE void emit_mul_r16(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_16BIT, 4, dreg); }
	2236	INLINE void emit_mul_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_16BIT, 4, MEMPARAMS); }
8650	2237
	2238	INLINE void emit_imul_r16(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_16BIT, 5, dreg); }
	2239	INLINE void emit_imul_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_16BIT, 5, MEMPARAMS); }
8651	2240
8652		/*------------------------------------------------------------------
8653		emit_ror_r32_*
8654		------------------------------------------------------------------*/
	2241	INLINE void emit_div_r16(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_16BIT, 6, dreg); }
	2242	INLINE void emit_div_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_16BIT, 6, MEMPARAMS); }
8655	2243
8656		#define emit_ror_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 1, dreg, imm)
8657		#define emit_ror_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 1, base, index, scale, disp, imm)
8658		#define emit_ror_r32_cl(e, dreg) emit_shift_r32_cl(e, 1, dreg)
8659		#define emit_ror_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 1, base, index, scale, disp)
	2244	INLINE void emit_idiv_r16(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_16BIT, 7, dreg); }
	2245	INLINE void emit_idiv_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_16BIT, 7, MEMPARAMS); }
8660	2246
8661		#define emit_ror_m32abs_imm(e, addr, imm) emit_ror_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8662		#define emit_ror_m32bd_imm(e, base, disp, imm) emit_ror_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8663		#define emit_ror_m32isd_imm(e, index, scale, disp, imm) emit_ror_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8664	2247
8665		#define emit_ror_m32abs_cl(e, addr) emit_ror_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8666		#define emit_ror_m32bd_cl(e, base, disp) emit_ror_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
8667		#define emit_ror_m32isd_cl(e, index, scale, disp) emit_ror_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	2248	/*-------------------------------------------------
	2249	emit_group3_r32_*
	2250	-------------------------------------------------*/
8668	2251
	2252	INLINE void emit_not_r32(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 2, dreg); }
	2253	INLINE void emit_not_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 2, MEMPARAMS); }
8669	2254
8670		/*------------------------------------------------------------------
8671		emit_rcl_r32_*
8672		------------------------------------------------------------------*/
	2255	INLINE void emit_neg_r32(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 3, dreg); }
	2256	INLINE void emit_neg_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 3, MEMPARAMS); }
8673	2257
8674		#define emit_rcl_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 2, dreg, imm)
8675		#define emit_rcl_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 2, base, index, scale, disp, imm)
8676		#define emit_rcl_r32_cl(e, dreg) emit_shift_r32_cl(e, 2, dreg)
8677		#define emit_rcl_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 2, base, index, scale, disp)
	2258	INLINE void emit_mul_r32(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 4, dreg); }
	2259	INLINE void emit_mul_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 4, MEMPARAMS); }
8678	2260
8679		#define emit_rcl_m32abs_imm(e, addr, imm) emit_rcl_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8680		#define emit_rcl_m32bd_imm(e, base, disp, imm) emit_rcl_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8681		#define emit_rcl_m32isd_imm(e, index, scale, disp, imm) emit_rcl_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2261	INLINE void emit_imul_r32(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 5, dreg); }
	2262	INLINE void emit_imul_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 5, MEMPARAMS); }
8682	2263
8683		#define emit_rcl_m32abs_cl(e, addr) emit_rcl_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8684		#define emit_rcl_m32bd_cl(e, base, disp) emit_rcl_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
8685		#define emit_rcl_m32isd_cl(e, index, scale, disp) emit_rcl_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	2264	INLINE void emit_div_r32(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 6, dreg); }
	2265	INLINE void emit_div_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 6, MEMPARAMS); }
8686	2266
	2267	INLINE void emit_idiv_r32(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 7, dreg); }
	2268	INLINE void emit_idiv_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 7, MEMPARAMS); }
8687	2269
8688		/*------------------------------------------------------------------
8689		emit_rcr_r32_*
8690		------------------------------------------------------------------*/
8691	2270
8692		#define emit_rcr_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 3, dreg, imm)
8693		#define emit_rcr_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 3, base, index, scale, disp, imm)
8694		#define emit_rcr_r32_cl(e, dreg) emit_shift_r32_cl(e, 3, dreg)
8695		#define emit_rcr_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 3, base, index, scale, disp)
	2271	/*-------------------------------------------------
	2272	emit_group3_r64_*
	2273	-------------------------------------------------*/
8696	2274
8697		#define emit_rcr_m32abs_imm(e, addr, imm) emit_rcr_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8698		#define emit_rcr_m32bd_imm(e, base, disp, imm) emit_rcr_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8699		#define emit_rcr_m32isd_imm(e, index, scale, disp, imm) emit_rcr_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2275	#ifdef PTR64
8700	2276
8701		#define emit_rcr_m32abs_cl(e, addr) emit_rcr_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8702		#define emit_rcr_m32bd_cl(e, base, disp) emit_rcr_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
8703		#define emit_rcr_m32isd_cl(e, index, scale, disp) emit_rcr_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	2277	INLINE void emit_not_r64(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, 2, dreg); }
	2278	INLINE void emit_not_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, 2, MEMPARAMS); }
8704	2279
	2280	INLINE void emit_neg_r64(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, 3, dreg); }
	2281	INLINE void emit_neg_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, 3, MEMPARAMS); }
8705	2282
8706		/*------------------------------------------------------------------
8707		emit_shl_r32_*
8708		------------------------------------------------------------------*/
	2283	INLINE void emit_mul_r64(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, 4, dreg); }
	2284	INLINE void emit_mul_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, 4, MEMPARAMS); }
8709	2285
8710		#define emit_shl_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 4, dreg, imm)
8711		#define emit_shl_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 4, base, index, scale, disp, imm)
8712		#define emit_shl_r32_cl(e, dreg) emit_shift_r32_cl(e, 4, dreg)
8713		#define emit_shl_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 4, base, index, scale, disp)
	2286	INLINE void emit_imul_r64(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, 5, dreg); }
	2287	INLINE void emit_imul_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, 5, MEMPARAMS); }
8714	2288
8715		#define emit_shl_m32abs_imm(e, addr, imm) emit_shl_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8716		#define emit_shl_m32bd_imm(e, base, disp, imm) emit_shl_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8717		#define emit_shl_m32isd_imm(e, index, scale, disp, imm) emit_shl_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2289	INLINE void emit_div_r64(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, 6, dreg); }
	2290	INLINE void emit_div_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, 6, MEMPARAMS); }
8718	2291
8719		#define emit_shl_m32abs_cl(e, addr) emit_shl_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8720		#define emit_shl_m32bd_cl(e, base, disp) emit_shl_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
8721		#define emit_shl_m32isd_cl(e, index, scale, disp) emit_shl_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	2292	INLINE void emit_idiv_r64(x86code **emitptr, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, 7, dreg); }
	2293	INLINE void emit_idiv_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, 7, MEMPARAMS); }
8722	2294
	2295	#endif
8723	2296
8724		/*------------------------------------------------------------------
8725		emit_shr_r32_*
8726		------------------------------------------------------------------*/
8727	2297
8728		#define emit_shr_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 5, dreg, imm)
8729		#define emit_shr_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 5, base, index, scale, disp, imm)
8730		#define emit_shr_r32_cl(e, dreg) emit_shift_r32_cl(e, 5, dreg)
8731		#define emit_shr_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 5, base, index, scale, disp)
8732	2298
8733		#define emit_shr_m32abs_imm(e, addr, imm) emit_shr_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8734		#define emit_shr_m32bd_imm(e, base, disp, imm) emit_shr_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8735		#define emit_shr_m32isd_imm(e, index, scale, disp, imm) emit_shr_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8736
8737		#define emit_shr_m32abs_cl(e, addr) emit_shr_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8738		#define emit_shr_m32bd_cl(e, base, disp) emit_shr_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
8739		#define emit_shr_m32isd_cl(e, index, scale, disp) emit_shr_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
8740
8741
8742		/*------------------------------------------------------------------
8743		emit_sar_r32_*
8744		------------------------------------------------------------------*/
8745
8746		#define emit_sar_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 7, dreg, imm)
8747		#define emit_sar_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 7, base, index, scale, disp, imm)
8748		#define emit_sar_r32_cl(e, dreg) emit_shift_r32_cl(e, 7, dreg)
8749		#define emit_sar_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 7, base, index, scale, disp)
8750
8751		#define emit_sar_m32abs_imm(e, addr, imm) emit_sar_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8752		#define emit_sar_m32bd_imm(e, base, disp, imm) emit_sar_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8753		#define emit_sar_m32isd_imm(e, index, scale, disp, imm) emit_sar_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8754
8755		#define emit_sar_m32abs_cl(e, addr) emit_sar_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8756		#define emit_sar_m32bd_cl(e, base, disp) emit_sar_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
8757		#define emit_sar_m32isd_cl(e, index, scale, disp) emit_sar_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
8758
8759
8760
8761	2299	/***************************************************************************
8762		~~64-B~~I~~T SHIFT~~ EMITTERS
	2300	IMUL EMITTERS
8763	2301	***************************************************************************/
8764	2302
8765		#ifdef PTR64
8766		/*
8767		Note that the following code relies on this:
	2303	/*-------------------------------------------------
	2304	emit_imul_r16_*
	2305	-------------------------------------------------*/
8768	2306
8769		/0 = ROL
8770		/1 = ROR
8771		/2 = RCL
8772		/3 = RCR
8773		/4 = SHL
8774		/5 = SHR
8775		/7 = SAR
8776		*/
	2307	INLINE void emit_imul_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_IMUL_Gv_Ev, OP_16BIT, dreg, sreg); }
	2308	INLINE void emit_imul_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_IMUL_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
	2309	INLINE void emit_imul_r16_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 sreg, INT16 imm) { emit_op_modrm_reg_imm816(emitptr, OP_IMUL_Gv_Ev_Ib, OP_IMUL_Gv_Ev_Iz, OP_16BIT, dreg, sreg, imm); }
	2310	INLINE void emit_imul_r16_m16_imm(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS, INT16 imm) { emit_op_modrm_mem_imm816(emitptr, OP_IMUL_Gv_Ev_Ib, OP_IMUL_Gv_Ev_Iz, OP_16BIT, dreg, MEMPARAMS, imm); }
8777	2311
8778		/*------------------------------------------------------------------
8779		emit_shift_r64_*
8780		------------------------------------------------------------------*/
	2312	INLINE void emit_imul_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_IMUL_Gv_Ev, OP_32BIT, dreg, sreg); }
	2313	INLINE void emit_imul_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_IMUL_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
	2314	INLINE void emit_imul_r32_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 sreg, INT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_IMUL_Gv_Ev_Ib, OP_IMUL_Gv_Ev_Iz, OP_32BIT, dreg, sreg, imm); }
	2315	INLINE void emit_imul_r32_m32_imm(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS, INT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_IMUL_Gv_Ev_Ib, OP_IMUL_Gv_Ev_Iz, OP_32BIT, dreg, MEMPARAMS, imm); }
8781	2316
8782		INLINE void emit_shift_r64_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
8783		{
8784		if (imm == 1)
8785		emit_op_modrm_reg(emitptr, OP_G2_Ev_1, OP_64BIT, opindex, dreg);
8786		else
8787		{
8788		emit_op_modrm_reg(emitptr, OP_G2_Ev_Ib, OP_64BIT, opindex, dreg);
8789		emit_byte(emitptr, imm);
8790		}
8791		}
	2317	#ifdef PTR64
8792	2318
8793		INLINE void emit_shift_m64bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
8794		{
8795		if (imm == 1)
8796		emit_op_modrm_mem(emitptr, OP_G2_Ev_1, OP_64BIT, opindex, base, index, scale, disp);
8797		else
8798		{
8799		emit_op_modrm_mem(emitptr, OP_G2_Ev_Ib, OP_64BIT, opindex, base, index, scale, disp);
8800		emit_byte(emitptr, imm);
8801		}
8802		}
	2319	INLINE void emit_imul_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_IMUL_Gv_Ev, OP_64BIT, dreg, sreg); }
	2320	INLINE void emit_imul_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_IMUL_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	2321	INLINE void emit_imul_r64_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 sreg, INT32 imm) { emit_op_modrm_reg_imm832(emitptr, OP_IMUL_Gv_Ev_Ib, OP_IMUL_Gv_Ev_Iz, OP_64BIT, dreg, sreg, imm); }
	2322	INLINE void emit_imul_r64_m64_imm(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS, INT32 imm) { emit_op_modrm_mem_imm832(emitptr, OP_IMUL_Gv_Ev_Ib, OP_IMUL_Gv_Ev_Iz, OP_64BIT, dreg, MEMPARAMS, imm); }
8803	2323
8804		INLINE void emit_shift_r64_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
8805		{
8806		emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_64BIT, opindex, dreg);
8807		}
8808
8809		INLINE void emit_shift_m64bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
8810		{
8811		emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_64BIT, opindex, base, index, scale, disp);
8812		}
8813
8814
8815		/*------------------------------------------------------------------
8816		emit_rol_r64_*
8817		------------------------------------------------------------------*/
8818
8819		#define emit_rol_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 0, dreg, imm)
8820		#define emit_rol_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 0, base, index, scale, disp, imm)
8821		#define emit_rol_r64_cl(e, dreg) emit_shift_r64_cl(e, 0, dreg)
8822		#define emit_rol_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 0, base, index, scale, disp)
8823
8824		#define emit_rol_m64abs_imm(e, addr, imm) emit_rol_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8825		#define emit_rol_m64bd_imm(e, base, disp, imm) emit_rol_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8826		#define emit_rol_m64isd_imm(e, index, scale, disp, imm) emit_rol_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8827
8828		#define emit_rol_m64abs_cl(e, addr) emit_rol_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8829		#define emit_rol_m64bd_cl(e, base, disp) emit_rol_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
8830		#define emit_rol_m64isd_cl(e, index, scale, disp) emit_rol_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
8831
8832
8833		/*------------------------------------------------------------------
8834		emit_ror_r64_*
8835		------------------------------------------------------------------*/
8836
8837		#define emit_ror_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 1, dreg, imm)
8838		#define emit_ror_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 1, base, index, scale, disp, imm)
8839		#define emit_ror_r64_cl(e, dreg) emit_shift_r64_cl(e, 1, dreg)
8840		#define emit_ror_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 1, base, index, scale, disp)
8841
8842		#define emit_ror_m64abs_imm(e, addr, imm) emit_ror_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8843		#define emit_ror_m64bd_imm(e, base, disp, imm) emit_ror_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8844		#define emit_ror_m64isd_imm(e, index, scale, disp, imm) emit_ror_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8845
8846		#define emit_ror_m64abs_cl(e, addr) emit_ror_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8847		#define emit_ror_m64bd_cl(e, base, disp) emit_ror_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
8848		#define emit_ror_m64isd_cl(e, index, scale, disp) emit_ror_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
8849
8850
8851		/*------------------------------------------------------------------
8852		emit_rcl_r64_*
8853		------------------------------------------------------------------*/
8854
8855		#define emit_rcl_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 2, dreg, imm)
8856		#define emit_rcl_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 2, base, index, scale, disp, imm)
8857		#define emit_rcl_r64_cl(e, dreg) emit_shift_r64_cl(e, 2, dreg)
8858		#define emit_rcl_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 2, base, index, scale, disp)
8859
8860		#define emit_rcl_m64abs_imm(e, addr, imm) emit_rcl_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8861		#define emit_rcl_m64bd_imm(e, base, disp, imm) emit_rcl_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8862		#define emit_rcl_m64isd_imm(e, index, scale, disp, imm) emit_rcl_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8863
8864		#define emit_rcl_m64abs_cl(e, addr) emit_rcl_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8865		#define emit_rcl_m64bd_cl(e, base, disp) emit_rcl_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
8866		#define emit_rcl_m64isd_cl(e, index, scale, disp) emit_rcl_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
8867
8868
8869		/*------------------------------------------------------------------
8870		emit_rcr_r64_*
8871		------------------------------------------------------------------*/
8872
8873		#define emit_rcr_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 3, dreg, imm)
8874		#define emit_rcr_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 3, base, index, scale, disp, imm)
8875		#define emit_rcr_r64_cl(e, dreg) emit_shift_r64_cl(e, 3, dreg)
8876		#define emit_rcr_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 3, base, index, scale, disp)
8877
8878		#define emit_rcr_m64abs_imm(e, addr, imm) emit_rcr_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8879		#define emit_rcr_m64bd_imm(e, base, disp, imm) emit_rcr_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8880		#define emit_rcr_m64isd_imm(e, index, scale, disp, imm) emit_rcr_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8881
8882		#define emit_rcr_m64abs_cl(e, addr) emit_rcr_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8883		#define emit_rcr_m64bd_cl(e, base, disp) emit_rcr_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
8884		#define emit_rcr_m64isd_cl(e, index, scale, disp) emit_rcr_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
8885
8886
8887		/*------------------------------------------------------------------
8888		emit_shl_r64_*
8889		------------------------------------------------------------------*/
8890
8891		#define emit_shl_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 4, dreg, imm)
8892		#define emit_shl_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 4, base, index, scale, disp, imm)
8893		#define emit_shl_r64_cl(e, dreg) emit_shift_r64_cl(e, 4, dreg)
8894		#define emit_shl_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 4, base, index, scale, disp)
8895
8896		#define emit_shl_m64abs_imm(e, addr, imm) emit_shl_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8897		#define emit_shl_m64bd_imm(e, base, disp, imm) emit_shl_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8898		#define emit_shl_m64isd_imm(e, index, scale, disp, imm) emit_shl_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8899
8900		#define emit_shl_m64abs_cl(e, addr) emit_shl_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8901		#define emit_shl_m64bd_cl(e, base, disp) emit_shl_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
8902		#define emit_shl_m64isd_cl(e, index, scale, disp) emit_shl_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
8903
8904
8905		/*------------------------------------------------------------------
8906		emit_shr_r64_*
8907		------------------------------------------------------------------*/
8908
8909		#define emit_shr_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 5, dreg, imm)
8910		#define emit_shr_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 5, base, index, scale, disp, imm)
8911		#define emit_shr_r64_cl(e, dreg) emit_shift_r64_cl(e, 5, dreg)
8912		#define emit_shr_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 5, base, index, scale, disp)
8913
8914		#define emit_shr_m64abs_imm(e, addr, imm) emit_shr_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8915		#define emit_shr_m64bd_imm(e, base, disp, imm) emit_shr_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8916		#define emit_shr_m64isd_imm(e, index, scale, disp, imm) emit_shr_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8917
8918		#define emit_shr_m64abs_cl(e, addr) emit_shr_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8919		#define emit_shr_m64bd_cl(e, base, disp) emit_shr_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
8920		#define emit_shr_m64isd_cl(e, index, scale, disp) emit_shr_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
8921
8922
8923		/*------------------------------------------------------------------
8924		emit_sar_r64_*
8925		------------------------------------------------------------------*/
8926
8927		#define emit_sar_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 7, dreg, imm)
8928		#define emit_sar_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 7, base, index, scale, disp, imm)
8929		#define emit_sar_r64_cl(e, dreg) emit_shift_r64_cl(e, 7, dreg)
8930		#define emit_sar_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 7, base, index, scale, disp)
8931
8932		#define emit_sar_m64abs_imm(e, addr, imm) emit_sar_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
8933		#define emit_sar_m64bd_imm(e, base, disp, imm) emit_sar_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
8934		#define emit_sar_m64isd_imm(e, index, scale, disp, imm) emit_sar_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
8935
8936		#define emit_sar_m64abs_cl(e, addr) emit_sar_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8937		#define emit_sar_m64bd_cl(e, base, disp) emit_sar_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
8938		#define emit_sar_m64isd_cl(e, index, scale, disp) emit_sar_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
8939
8940	2324	#endif
8941	2325
8942	2326
8943	2327
8944	2328	/***************************************************************************
8945		8-BIT GROUP3 EMITTERS
	2329	BIT OPERATION EMITTERS
8946	2330	***************************************************************************/
8947	2331
8948		/*
8949		Note that the following code relies on this:
	2332	/*-------------------------------------------------
	2333	emit_bswap_*
	2334	-------------------------------------------------*/
8950	2335
8951		/2 = NOT
8952		/3 = NEG
8953		/4 = MUL
8954		/5 = IMUL
8955		/6 = DIV
8956		/7 = IDIV
8957		*/
	2336	INLINE void emit_bswap_r32(x86code **emitptr, UINT8 dreg) { emit_op_reg(emitptr, OP_BSWAP_EAX + (dreg & 7), OP_32BIT, dreg); }
	2337	INLINE void emit_bswap_r64(x86code **emitptr, UINT8 dreg) { emit_op_reg(emitptr, OP_BSWAP_EAX + (dreg & 7), OP_64BIT, dreg); }
8958	2338
8959		/*------------------------------------------------------------------
8960		emit_group3_r8_*
8961		------------------------------------------------------------------*/
8962	2339
8963		INLINE void emit_group3_r8(x86code **emitptr, UINT8 opindex, UINT8 dreg)
8964		{
8965		emit_op_modrm_reg(emitptr, OP_G3_Eb, OP_32BIT, opindex, dreg);
8966		}
	2340	/*-------------------------------------------------
	2341	emit_bsr/bsf_r16_*
	2342	-------------------------------------------------*/
8967	2343
8968		INLINE void emit_group3_m8bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
8969		{
8970		emit_op_modrm_mem(emitptr, OP_G3_Eb, OP_32BIT, opindex, base, index, scale, disp);
8971		}
	2344	INLINE void emit_bsf_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BSF_Gv_Ev, OP_16BIT, dreg, sreg); }
	2345	INLINE void emit_bsf_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_BSF_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
	2346	INLINE void emit_bsr_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BSR_Gv_Ev, OP_16BIT, dreg, sreg); }
	2347	INLINE void emit_bsr_r16_m16(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_BSR_Gv_Ev, OP_16BIT, dreg, MEMPARAMS); }
8972	2348
	2349	INLINE void emit_bsf_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BSF_Gv_Ev, OP_32BIT, dreg, sreg); }
	2350	INLINE void emit_bsf_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_BSF_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
	2351	INLINE void emit_bsr_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BSR_Gv_Ev, OP_32BIT, dreg, sreg); }
	2352	INLINE void emit_bsr_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_BSR_Gv_Ev, OP_32BIT, dreg, MEMPARAMS); }
8973	2353
8974		/*------------------------------------------------------------------
8975		emit_not_r8_*
8976		------------------------------------------------------------------*/
	2354	#ifdef PTR64
	2355	INLINE void emit_bsf_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BSF_Gv_Ev, OP_64BIT, dreg, sreg); }
	2356	INLINE void emit_bsf_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_BSF_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	2357	INLINE void emit_bsr_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BSR_Gv_Ev, OP_64BIT, dreg, sreg); }
	2358	INLINE void emit_bsr_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_BSR_Gv_Ev, OP_64BIT, dreg, MEMPARAMS); }
	2359	#endif
8977	2360
8978		#define emit_not_r8(e, dreg) emit_group3_r8(e, 2, dreg)
8979		#define emit_not_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 2, base, index, scale, disp)
8980	2361
8981		#define emit_not_m8abs(e, addr) emit_not_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8982		#define emit_not_m8bd(e, base, disp) emit_not_m8bisd(e, (base), REG_NONE, 1, (disp))
8983		#define emit_not_m8isd(e, index, scale, disp) emit_not_m8bisd(e, REG_NONE, (index), (scale), (disp))
	2362	/*-------------------------------------------------
	2363	emit_bit_r16_*
	2364	-------------------------------------------------*/
8984	2365
	2366	INLINE void emit_bt_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BT_Ev_Gv, OP_16BIT, sreg, dreg); }
	2367	INLINE void emit_bt_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BT_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
	2368	INLINE void emit_bt_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_16BIT, 4, dreg, imm); }
	2369	INLINE void emit_bt_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_16BIT, 4, MEMPARAMS, imm); }
8985	2370
8986		/*------------------------------------------------------------------
8987		emit_neg_r8_*
8988		------------------------------------------------------------------*/
	2371	INLINE void emit_bts_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BTS_Ev_Gv, OP_16BIT, sreg, dreg); }
	2372	INLINE void emit_bts_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BTS_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
	2373	INLINE void emit_bts_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_16BIT, 5, dreg, imm); }
	2374	INLINE void emit_bts_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_16BIT, 5, MEMPARAMS, imm); }
8989	2375
8990		#define emit_neg_r8(e, dreg) emit_group3_r8(e, 3, dreg)
8991		#define emit_neg_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 3, base, index, scale, disp)
	2376	INLINE void emit_btr_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BTR_Ev_Gv, OP_16BIT, sreg, dreg); }
	2377	INLINE void emit_btr_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BTR_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
	2378	INLINE void emit_btr_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_16BIT, 6, dreg, imm); }
	2379	INLINE void emit_btr_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_16BIT, 6, MEMPARAMS, imm); }
8992	2380
8993		#define emit_neg_m8abs(e, addr) emit_neg_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
8994		#define emit_neg_m8bd(e, base, disp) emit_neg_m8bisd(e, (base), REG_NONE, 1, (disp))
8995		#define emit_neg_m8isd(e, index, scale, disp) emit_neg_m8bisd(e, REG_NONE, (index), (scale), (disp))
	2381	INLINE void emit_btc_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BTC_Ev_Gv, OP_16BIT, sreg, dreg); }
	2382	INLINE void emit_btc_m16_r16(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BTC_Ev_Gv, OP_16BIT, sreg, MEMPARAMS); }
	2383	INLINE void emit_btc_r16_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_16BIT, 7, dreg, imm); }
	2384	INLINE void emit_btc_m16_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_16BIT, 7, MEMPARAMS, imm); }
8996	2385
8997	2386
8998		/*------------------------------------------------------------------
8999		emit_mul_r8_*
9000		------------------------------------------------------------------*/
	2387	/*-------------------------------------------------
	2388	emit_bit_r32_*
	2389	-------------------------------------------------*/
9001	2390
9002		#define emit_mul_r8(e, dreg) emit_group3_r8(e, 4, dreg)
9003		#define emit_mul_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 4, base, index, scale, disp)
	2391	INLINE void emit_bt_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BT_Ev_Gv, OP_32BIT, sreg, dreg); }
	2392	INLINE void emit_bt_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BT_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
	2393	INLINE void emit_bt_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_32BIT, 4, dreg, imm); }
	2394	INLINE void emit_bt_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_32BIT, 4, MEMPARAMS, imm); }
9004	2395
9005		#define emit_mul_m8abs(e, addr) emit_mul_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9006		#define emit_mul_m8bd(e, base, disp) emit_mul_m8bisd(e, (base), REG_NONE, 1, (disp))
9007		#define emit_mul_m8isd(e, index, scale, disp) emit_mul_m8bisd(e, REG_NONE, (index), (scale), (disp))
	2396	INLINE void emit_bts_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BTS_Ev_Gv, OP_32BIT, sreg, dreg); }
	2397	INLINE void emit_bts_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BTS_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
	2398	INLINE void emit_bts_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_32BIT, 5, dreg, imm); }
	2399	INLINE void emit_bts_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_32BIT, 5, MEMPARAMS, imm); }
9008	2400
	2401	INLINE void emit_btr_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BTR_Ev_Gv, OP_32BIT, sreg, dreg); }
	2402	INLINE void emit_btr_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BTR_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
	2403	INLINE void emit_btr_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_32BIT, 6, dreg, imm); }
	2404	INLINE void emit_btr_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_32BIT, 6, MEMPARAMS, imm); }
9009	2405
9010		/*------------------------------------------------------------------
9011		emit_imul_r8_*
9012		------------------------------------------------------------------*/
	2406	INLINE void emit_btc_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BTC_Ev_Gv, OP_32BIT, sreg, dreg); }
	2407	INLINE void emit_btc_m32_r32(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BTC_Ev_Gv, OP_32BIT, sreg, MEMPARAMS); }
	2408	INLINE void emit_btc_r32_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_32BIT, 7, dreg, imm); }
	2409	INLINE void emit_btc_m32_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_32BIT, 7, MEMPARAMS, imm); }
9013	2410
9014		#define emit_imul_r8(e, dreg) emit_group3_r8(e, 5, dreg)
9015		#define emit_imul_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 5, base, index, scale, disp)
9016	2411
9017		#define emit_imul_m8abs(e, addr) emit_imul_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9018		#define emit_imul_m8bd(e, base, disp) emit_imul_m8bisd(e, (base), REG_NONE, 1, (disp))
9019		#define emit_imul_m8isd(e, index, scale, disp) emit_imul_m8bisd(e, REG_NONE, (index), (scale), (disp))
	2412	/*-------------------------------------------------
	2413	emit_bit_r64_*
	2414	-------------------------------------------------*/
9020	2415
	2416	#ifdef PTR64
9021	2417
9022		/*------------------------------------------------------------------
9023		emit_div_r8_*
9024		------------------------------------------------------------------*/
	2418	INLINE void emit_bt_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BT_Ev_Gv, OP_64BIT, sreg, dreg); }
	2419	INLINE void emit_bt_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BT_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
	2420	INLINE void emit_bt_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_64BIT, 4, dreg, imm); }
	2421	INLINE void emit_bt_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_64BIT, 4, MEMPARAMS, imm); }
9025	2422
9026		#define emit_div_r8(e, dreg) emit_group3_r8(e, 6, dreg)
9027		#define emit_div_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 6, base, index, scale, disp)
	2423	INLINE void emit_bts_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BTS_Ev_Gv, OP_64BIT, sreg, dreg); }
	2424	INLINE void emit_bts_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BTS_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
	2425	INLINE void emit_bts_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_64BIT, 5, dreg, imm); }
	2426	INLINE void emit_bts_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_64BIT, 5, MEMPARAMS, imm); }
9028	2427
9029		#define emit_div_m8abs(e, addr) emit_div_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9030		#define emit_div_m8bd(e, base, disp) emit_div_m8bisd(e, (base), REG_NONE, 1, (disp))
9031		#define emit_div_m8isd(e, index, scale, disp) emit_div_m8bisd(e, REG_NONE, (index), (scale), (disp))
	2428	INLINE void emit_btr_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BTR_Ev_Gv, OP_64BIT, sreg, dreg); }
	2429	INLINE void emit_btr_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BTR_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
	2430	INLINE void emit_btr_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_64BIT, 6, dreg, imm); }
	2431	INLINE void emit_btr_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_64BIT, 6, MEMPARAMS, imm); }
9032	2432
	2433	INLINE void emit_btc_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_BTC_Ev_Gv, OP_64BIT, sreg, dreg); }
	2434	INLINE void emit_btc_m64_r64(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_BTC_Ev_Gv, OP_64BIT, sreg, MEMPARAMS); }
	2435	INLINE void emit_btc_r64_imm(x86code **emitptr, UINT8 dreg, UINT8 imm) { emit_op_modrm_reg_imm8(emitptr, OP_G8_Ev_Ib, OP_64BIT, 7, dreg, imm); }
	2436	INLINE void emit_btc_m64_imm(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 imm) { emit_op_modrm_mem_imm8(emitptr, OP_G8_Ev_Ib, OP_64BIT, 7, MEMPARAMS, imm); }
9033	2437
9034		/*------------------------------------------------------------------
9035		emit_idiv_r8_*
9036		------------------------------------------------------------------*/
	2438	#endif
9037	2439
9038		#define emit_idiv_r8(e, dreg) emit_group3_r8(e, 7, dreg)
9039		#define emit_idiv_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 7, base, index, scale, disp)
9040	2440
9041		#define emit_idiv_m8abs(e, addr) emit_idiv_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9042		#define emit_idiv_m8bd(e, base, disp) emit_idiv_m8bisd(e, (base), REG_NONE, 1, (disp))
9043		#define emit_idiv_m8isd(e, index, scale, disp) emit_idiv_m8bisd(e, REG_NONE, (index), (scale), (disp))
9044	2441
9045
9046
9047	2442	/***************************************************************************
9048		~~16-BIT GROUP3~~ EMITTERS
	2443	LEA EMITTERS
9049	2444	***************************************************************************/
9050	2445
9051		/*
9052		Note that the following code relies on this:
	2446	INLINE void emit_lea_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_LEA_Gv_M, OP_32BIT, dreg, MEMPARAMS); }
9053	2447
9054		/0 = ROL
9055		/1 = ROR
9056		/2 = RCL
9057		/3 = RCR
9058		/4 = SHL
9059		/5 = SHR
9060		/7 = SAR
9061		*/
	2448	#ifdef PTR64
	2449	INLINE void emit_lea_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_LEA_Gv_M, OP_64BIT, dreg, MEMPARAMS); }
	2450	#endif
9062	2451
9063		/*------------------------------------------------------------------
9064		emit_group3_r16_*
9065		------------------------------------------------------------------*/
9066	2452
9067		INLINE void emit_group3_r16(x86code **emitptr, UINT8 opindex, UINT8 dreg)
9068		{
9069		emit_byte(emitptr, PREFIX_OPSIZE);
9070		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, opindex, dreg);
9071		}
9072	2453
9073		INLINE void emit_group3_m16bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
9074		{
9075		emit_byte(emitptr, PREFIX_OPSIZE);
9076		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, opindex, base, index, scale, disp);
9077		}
9078
9079
9080		/*------------------------------------------------------------------
9081		emit_not_r16_*
9082		------------------------------------------------------------------*/
9083
9084		#define emit_not_r16(e, dreg) emit_group3_r16(e, 2, dreg)
9085		#define emit_not_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 2, base, index, scale, disp)
9086
9087		#define emit_not_m16abs(e, addr) emit_not_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9088		#define emit_not_m16bd(e, base, disp) emit_not_m16bisd(e, (base), REG_NONE, 1, (disp))
9089		#define emit_not_m16isd(e, index, scale, disp) emit_not_m16bisd(e, REG_NONE, (index), (scale), (disp))
9090
9091
9092		/*------------------------------------------------------------------
9093		emit_neg_r16_*
9094		------------------------------------------------------------------*/
9095
9096		#define emit_neg_r16(e, dreg) emit_group3_r16(e, 3, dreg)
9097		#define emit_neg_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 3, base, index, scale, disp)
9098
9099		#define emit_neg_m16abs(e, addr) emit_neg_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9100		#define emit_neg_m16bd(e, base, disp) emit_neg_m16bisd(e, (base), REG_NONE, 1, (disp))
9101		#define emit_neg_m16isd(e, index, scale, disp) emit_neg_m16bisd(e, REG_NONE, (index), (scale), (disp))
9102
9103
9104		/*------------------------------------------------------------------
9105		emit_mul_r16_*
9106		------------------------------------------------------------------*/
9107
9108		#define emit_mul_r16(e, dreg) emit_group3_r16(e, 4, dreg)
9109		#define emit_mul_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 4, base, index, scale, disp)
9110
9111		#define emit_mul_m16abs(e, addr) emit_mul_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9112		#define emit_mul_m16bd(e, base, disp) emit_mul_m16bisd(e, (base), REG_NONE, 1, (disp))
9113		#define emit_mul_m16isd(e, index, scale, disp) emit_mul_m16bisd(e, REG_NONE, (index), (scale), (disp))
9114
9115
9116		/*------------------------------------------------------------------
9117		emit_imul_r16_*
9118		------------------------------------------------------------------*/
9119
9120		#define emit_imul_r16(e, dreg) emit_group3_r16(e, 5, dreg)
9121		#define emit_imul_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 5, base, index, scale, disp)
9122
9123		#define emit_imul_m16abs(e, addr) emit_imul_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9124		#define emit_imul_m16bd(e, base, disp) emit_imul_m16bisd(e, (base), REG_NONE, 1, (disp))
9125		#define emit_imul_m16isd(e, index, scale, disp) emit_imul_m16bisd(e, REG_NONE, (index), (scale), (disp))
9126
9127
9128		/*------------------------------------------------------------------
9129		emit_div_r16_*
9130		------------------------------------------------------------------*/
9131
9132		#define emit_div_r16(e, dreg) emit_group3_r16(e, 6, dreg)
9133		#define emit_div_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 6, base, index, scale, disp)
9134
9135		#define emit_div_m16abs(e, addr) emit_div_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9136		#define emit_div_m16bd(e, base, disp) emit_div_m16bisd(e, (base), REG_NONE, 1, (disp))
9137		#define emit_div_m16isd(e, index, scale, disp) emit_div_m16bisd(e, REG_NONE, (index), (scale), (disp))
9138
9139
9140		/*------------------------------------------------------------------
9141		emit_idiv_r16_*
9142		------------------------------------------------------------------*/
9143
9144		#define emit_idiv_r16(e, dreg) emit_group3_r16(e, 7, dreg)
9145		#define emit_idiv_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 7, base, index, scale, disp)
9146
9147		#define emit_idiv_m16abs(e, addr) emit_idiv_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9148		#define emit_idiv_m16bd(e, base, disp) emit_idiv_m16bisd(e, (base), REG_NONE, 1, (disp))
9149		#define emit_idiv_m16isd(e, index, scale, disp) emit_idiv_m16bisd(e, REG_NONE, (index), (scale), (disp))
9150
9151
9152
9153	2454	/***************************************************************************
9154		~~32-BI~~T ~~GROUP3~~ EMITTERS
	2455	SET EMITTERS
9155	2456	***************************************************************************/
9156	2457
9157		/*
9158		Note that the following code relies on this:
	2458	/*-------------------------------------------------
	2459	emit_setcc_*
	2460	-------------------------------------------------*/
9159	2461
9160		/0 = ROL
9161		/1 = ROR
9162		/2 = RCL
9163		/3 = RCR
9164		/4 = SHL
9165		/5 = SHR
9166		/7 = SAR
9167		*/
	2462	INLINE void emit_setcc_r8(x86code **emitptr, UINT8 cond, UINT8 dreg) { emit_op_modrm_reg(emitptr, OP_SETCC_O_Eb + cond, OP_32BIT, 0, dreg); }
	2463	INLINE void emit_setcc_m8(x86code **emitptr, UINT8 cond, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SETCC_O_Eb + cond, OP_32BIT, 0, MEMPARAMS); }
9168	2464
9169		/*------------------------------------------------------------------
9170		emit_group3_r32_*
9171		------------------------------------------------------------------*/
9172	2465
9173		INLINE void emit_group3_r32(x86code **emitptr, UINT8 opindex, UINT8 dreg)
9174		{
9175		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, opindex, dreg);
9176		}
9177	2466
9178		INLINE void emit_group3_m32bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
9179		{
9180		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, opindex, base, index, scale, disp);
9181		}
9182
9183
9184		/*------------------------------------------------------------------
9185		emit_not_r32_*
9186		------------------------------------------------------------------*/
9187
9188		#define emit_not_r32(e, dreg) emit_group3_r32(e, 2, dreg)
9189		#define emit_not_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 2, base, index, scale, disp)
9190
9191		#define emit_not_m32abs(e, addr) emit_not_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9192		#define emit_not_m32bd(e, base, disp) emit_not_m32bisd(e, (base), REG_NONE, 1, (disp))
9193		#define emit_not_m32isd(e, index, scale, disp) emit_not_m32bisd(e, REG_NONE, (index), (scale), (disp))
9194
9195
9196		/*------------------------------------------------------------------
9197		emit_neg_r32_*
9198		------------------------------------------------------------------*/
9199
9200		#define emit_neg_r32(e, dreg) emit_group3_r32(e, 3, dreg)
9201		#define emit_neg_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 3, base, index, scale, disp)
9202
9203		#define emit_neg_m32abs(e, addr) emit_neg_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9204		#define emit_neg_m32bd(e, base, disp) emit_neg_m32bisd(e, (base), REG_NONE, 1, (disp))
9205		#define emit_neg_m32isd(e, index, scale, disp) emit_neg_m32bisd(e, REG_NONE, (index), (scale), (disp))
9206
9207
9208		/*------------------------------------------------------------------
9209		emit_mul_r32_*
9210		------------------------------------------------------------------*/
9211
9212		#define emit_mul_r32(e, dreg) emit_group3_r32(e, 4, dreg)
9213		#define emit_mul_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 4, base, index, scale, disp)
9214
9215		#define emit_mul_m32abs(e, addr) emit_mul_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9216		#define emit_mul_m32bd(e, base, disp) emit_mul_m32bisd(e, (base), REG_NONE, 1, (disp))
9217		#define emit_mul_m32isd(e, index, scale, disp) emit_mul_m32bisd(e, REG_NONE, (index), (scale), (disp))
9218
9219
9220		/*------------------------------------------------------------------
9221		emit_imul_r32_*
9222		------------------------------------------------------------------*/
9223
9224		#define emit_imul_r32(e, dreg) emit_group3_r32(e, 5, dreg)
9225		#define emit_imul_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 5, base, index, scale, disp)
9226
9227		#define emit_imul_m32abs(e, addr) emit_imul_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9228		#define emit_imul_m32bd(e, base, disp) emit_imul_m32bisd(e, (base), REG_NONE, 1, (disp))
9229		#define emit_imul_m32isd(e, index, scale, disp) emit_imul_m32bisd(e, REG_NONE, (index), (scale), (disp))
9230
9231
9232		/*------------------------------------------------------------------
9233		emit_div_r32_*
9234		------------------------------------------------------------------*/
9235
9236		#define emit_div_r32(e, dreg) emit_group3_r32(e, 6, dreg)
9237		#define emit_div_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 6, base, index, scale, disp)
9238
9239		#define emit_div_m32abs(e, addr) emit_div_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9240		#define emit_div_m32bd(e, base, disp) emit_div_m32bisd(e, (base), REG_NONE, 1, (disp))
9241		#define emit_div_m32isd(e, index, scale, disp) emit_div_m32bisd(e, REG_NONE, (index), (scale), (disp))
9242
9243
9244		/*------------------------------------------------------------------
9245		emit_idiv_r32_*
9246		------------------------------------------------------------------*/
9247
9248		#define emit_idiv_r32(e, dreg) emit_group3_r32(e, 7, dreg)
9249		#define emit_idiv_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 7, base, index, scale, disp)
9250
9251		#define emit_idiv_m32abs(e, addr) emit_idiv_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9252		#define emit_idiv_m32bd(e, base, disp) emit_idiv_m32bisd(e, (base), REG_NONE, 1, (disp))
9253		#define emit_idiv_m32isd(e, index, scale, disp) emit_idiv_m32bisd(e, REG_NONE, (index), (scale), (disp))
9254
9255
9256
9257	2467	/***************************************************************************
9258		~~64-B~~IT ~~GROU~~P3 EMITTERS
	2468	SIMPLE FPU EMITTERS
9259	2469	***************************************************************************/
9260	2470
9261		#ifdef PTR64
9262		/*
9263		Note that the following code relies on this:
	2471	#ifndef PTR64
9264	2472
9265		/0 = ROL
9266		/1 = ROR
9267		/2 = RCL
9268		/3 = RCR
9269		/4 = SHL
9270		/5 = SHR
9271		/7 = SAR
9272		*/
	2473	INLINE void emit_fnop(x86code **emitptr) { emit_op_simple(emitptr, OP_FNOP, OP_32BIT); }
	2474	INLINE void emit_fchs(x86code **emitptr) { emit_op_simple(emitptr, OP_FCHS, OP_32BIT); }
	2475	INLINE void emit_fabs(x86code **emitptr) { emit_op_simple(emitptr, OP_FABS, OP_32BIT); }
	2476	INLINE void emit_ftst(x86code **emitptr) { emit_op_simple(emitptr, OP_FTST, OP_32BIT); }
	2477	INLINE void emit_fxam(x86code **emitptr) { emit_op_simple(emitptr, OP_FXAM, OP_32BIT); }
	2478	INLINE void emit_fld1(x86code **emitptr) { emit_op_simple(emitptr, OP_FLD1, OP_32BIT); }
	2479	INLINE void emit_fldl2t(x86code **emitptr) { emit_op_simple(emitptr, OP_FLDL2T, OP_32BIT); }
	2480	INLINE void emit_fldl2e(x86code **emitptr) { emit_op_simple(emitptr, OP_FLDL2E, OP_32BIT); }
	2481	INLINE void emit_fldpi(x86code **emitptr) { emit_op_simple(emitptr, OP_FLDPI, OP_32BIT); }
	2482	INLINE void emit_fldlg2(x86code **emitptr) { emit_op_simple(emitptr, OP_FLDLG2, OP_32BIT); }
	2483	INLINE void emit_fldln2(x86code **emitptr) { emit_op_simple(emitptr, OP_FLDLN2, OP_32BIT); }
	2484	INLINE void emit_fldz(x86code **emitptr) { emit_op_simple(emitptr, OP_FLDZ, OP_32BIT); }
	2485	INLINE void emit_f2xm1(x86code **emitptr) { emit_op_simple(emitptr, OP_F2XM1, OP_32BIT); }
	2486	INLINE void emit_fyl2x(x86code **emitptr) { emit_op_simple(emitptr, OP_FYL2X, OP_32BIT); }
	2487	INLINE void emit_fptan(x86code **emitptr) { emit_op_simple(emitptr, OP_FPTAN, OP_32BIT); }
	2488	INLINE void emit_fpatan(x86code **emitptr) { emit_op_simple(emitptr, OP_FPATAN, OP_32BIT); }
	2489	INLINE void emit_fxtract(x86code **emitptr) { emit_op_simple(emitptr, OP_FXTRACT, OP_32BIT); }
	2490	INLINE void emit_fprem1(x86code **emitptr) { emit_op_simple(emitptr, OP_FPREM1, OP_32BIT); }
	2491	INLINE void emit_fdecstp(x86code **emitptr) { emit_op_simple(emitptr, OP_FDECSTP, OP_32BIT); }
	2492	INLINE void emit_fincstp(x86code **emitptr) { emit_op_simple(emitptr, OP_FINCSTP, OP_32BIT); }
	2493	INLINE void emit_fprem(x86code **emitptr) { emit_op_simple(emitptr, OP_FPREM, OP_32BIT); }
	2494	INLINE void emit_fyl2xp1(x86code **emitptr) { emit_op_simple(emitptr, OP_FYL2XP1, OP_32BIT); }
	2495	INLINE void emit_fsqrt(x86code **emitptr) { emit_op_simple(emitptr, OP_FSQRT, OP_32BIT); }
	2496	INLINE void emit_fsincos(x86code **emitptr) { emit_op_simple(emitptr, OP_FSINCOS, OP_32BIT); }
	2497	INLINE void emit_frndint(x86code **emitptr) { emit_op_simple(emitptr, OP_FRNDINT, OP_32BIT); }
	2498	INLINE void emit_fscale(x86code **emitptr) { emit_op_simple(emitptr, OP_FSCALE, OP_32BIT); }
	2499	INLINE void emit_fsin(x86code **emitptr) { emit_op_simple(emitptr, OP_FSIN, OP_32BIT); }
	2500	INLINE void emit_fcos(x86code **emitptr) { emit_op_simple(emitptr, OP_FCOS, OP_32BIT); }
	2501	INLINE void emit_fucompp(x86code **emitptr) { emit_op_simple(emitptr, OP_FUCOMPP, OP_32BIT); }
	2502	INLINE void emit_fclex(x86code **emitptr) { emit_op_simple(emitptr, OP_FCLEX, OP_32BIT); }
	2503	INLINE void emit_finit(x86code **emitptr) { emit_op_simple(emitptr, OP_FINIT, OP_32BIT); }
	2504	INLINE void emit_fcompp(x86code **emitptr) { emit_op_simple(emitptr, OP_FCOMPP, OP_32BIT); }
	2505	INLINE void emit_fstsw_ax(x86code **emitptr) { emit_op_simple(emitptr, OP_FSTSW_AX, OP_32BIT); }
9273	2506
9274		/*------------------------------------------------------------------
9275		emit_group3_r64_*
9276		------------------------------------------------------------------*/
9277
9278		INLINE void emit_group3_r64(x86code **emitptr, UINT8 opindex, UINT8 dreg)
9279		{
9280		emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, opindex, dreg);
9281		}
9282
9283		INLINE void emit_group3_m64bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
9284		{
9285		emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, opindex, base, index, scale, disp);
9286		}
9287
9288
9289		/*------------------------------------------------------------------
9290		emit_not_r64_*
9291		------------------------------------------------------------------*/
9292
9293		#define emit_not_r64(e, dreg) emit_group3_r64(e, 2, dreg)
9294		#define emit_not_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 2, base, index, scale, disp)
9295
9296		#define emit_not_m64abs(e, addr) emit_not_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9297		#define emit_not_m64bd(e, base, disp) emit_not_m64bisd(e, (base), REG_NONE, 1, (disp))
9298		#define emit_not_m64isd(e, index, scale, disp) emit_not_m64bisd(e, REG_NONE, (index), (scale), (disp))
9299
9300
9301		/*------------------------------------------------------------------
9302		emit_neg_r64_*
9303		------------------------------------------------------------------*/
9304
9305		#define emit_neg_r64(e, dreg) emit_group3_r64(e, 3, dreg)
9306		#define emit_neg_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 3, base, index, scale, disp)
9307
9308		#define emit_neg_m64abs(e, addr) emit_neg_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9309		#define emit_neg_m64bd(e, base, disp) emit_neg_m64bisd(e, (base), REG_NONE, 1, (disp))
9310		#define emit_neg_m64isd(e, index, scale, disp) emit_neg_m64bisd(e, REG_NONE, (index), (scale), (disp))
9311
9312
9313		/*------------------------------------------------------------------
9314		emit_mul_r64_*
9315		------------------------------------------------------------------*/
9316
9317		#define emit_mul_r64(e, dreg) emit_group3_r64(e, 4, dreg)
9318		#define emit_mul_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 4, base, index, scale, disp)
9319
9320		#define emit_mul_m64abs(e, addr) emit_mul_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9321		#define emit_mul_m64bd(e, base, disp) emit_mul_m64bisd(e, (base), REG_NONE, 1, (disp))
9322		#define emit_mul_m64isd(e, index, scale, disp) emit_mul_m64bisd(e, REG_NONE, (index), (scale), (disp))
9323
9324
9325		/*------------------------------------------------------------------
9326		emit_imul_r64_*
9327		------------------------------------------------------------------*/
9328
9329		#define emit_imul_r64(e, dreg) emit_group3_r64(e, 5, dreg)
9330		#define emit_imul_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 5, base, index, scale, disp)
9331
9332		#define emit_imul_m64abs(e, addr) emit_imul_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9333		#define emit_imul_m64bd(e, base, disp) emit_imul_m64bisd(e, (base), REG_NONE, 1, (disp))
9334		#define emit_imul_m64isd(e, index, scale, disp) emit_imul_m64bisd(e, REG_NONE, (index), (scale), (disp))
9335
9336
9337		/*------------------------------------------------------------------
9338		emit_div_r64_*
9339		------------------------------------------------------------------*/
9340
9341		#define emit_div_r64(e, dreg) emit_group3_r64(e, 6, dreg)
9342		#define emit_div_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 6, base, index, scale, disp)
9343
9344		#define emit_div_m64abs(e, addr) emit_div_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9345		#define emit_div_m64bd(e, base, disp) emit_div_m64bisd(e, (base), REG_NONE, 1, (disp))
9346		#define emit_div_m64isd(e, index, scale, disp) emit_div_m64bisd(e, REG_NONE, (index), (scale), (disp))
9347
9348
9349		/*------------------------------------------------------------------
9350		emit_idiv_r64_*
9351		------------------------------------------------------------------*/
9352
9353		#define emit_idiv_r64(e, dreg) emit_group3_r64(e, 7, dreg)
9354		#define emit_idiv_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 7, base, index, scale, disp)
9355
9356		#define emit_idiv_m64abs(e, addr) emit_idiv_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9357		#define emit_idiv_m64bd(e, base, disp) emit_idiv_m64bisd(e, (base), REG_NONE, 1, (disp))
9358		#define emit_idiv_m64isd(e, index, scale, disp) emit_idiv_m64bisd(e, REG_NONE, (index), (scale), (disp))
9359
9360	2507	#endif
9361	2508
9362	2509
9363	2510
9364	2511	/***************************************************************************
9365		LEA EMITTERS
	2512	REGISTER-BASED FPU EMITTERS
9366	2513	***************************************************************************/
9367	2514
9368		/*------------------------------------------------------------------
9369		emit_lea_r32_*
9370		------------------------------------------------------------------*/
	2515	#ifndef PTR64
9371	2516
9372		INLINE void emit_lea_r32_m32bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
9373		{
9374		emit_op_modrm_mem(emitptr, OP_LEA_Gv_M, OP_32BIT, dreg, base, index, scale, disp);
9375		}
	2517	INLINE void emit_ffree_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FFREE_STn + reg, OP_32BIT); }
	2518	INLINE void emit_fst_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FST_STn + reg, OP_32BIT); }
	2519	INLINE void emit_fstp_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FSTP_STn + reg, OP_32BIT); }
	2520	INLINE void emit_fucomp_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FUCOMP_STn + reg, OP_32BIT); }
9376	2521
9377		#define emit_lea_r32_m32abs(e, dreg, addr) emit_lea_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9378		#define emit_lea_r32_m32bd(e, dreg, base, disp) emit_lea_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
9379		#define emit_lea_r32_m32isd(e, dreg, index, scale, disp) emit_lea_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2522	INLINE void emit_fadd_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FADD_ST0_STn + reg, OP_32BIT); }
	2523	INLINE void emit_fmul_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FMUL_ST0_STn + reg, OP_32BIT); }
	2524	INLINE void emit_fcom_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCOM_ST0_STn + reg, OP_32BIT); }
	2525	INLINE void emit_fcomp_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCOMP_ST0_STn + reg, OP_32BIT); }
	2526	INLINE void emit_fsub_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FSUB_ST0_STn + reg, OP_32BIT); }
	2527	INLINE void emit_fsubr_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FSUBR_ST0_STn + reg, OP_32BIT); }
	2528	INLINE void emit_fdiv_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FDIV_ST0_STn + reg, OP_32BIT); }
	2529	INLINE void emit_fdivr_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FDIVR_ST0_STn + reg, OP_32BIT); }
	2530	INLINE void emit_fld_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FLD_ST0_STn + reg, OP_32BIT); }
	2531	INLINE void emit_fxch_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FXCH_ST0_STn + reg, OP_32BIT); }
	2532	INLINE void emit_fcmovb_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCMOVB_ST0_STn + reg, OP_32BIT); }
	2533	INLINE void emit_fcmove_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCMOVE_ST0_STn + reg, OP_32BIT); }
	2534	INLINE void emit_fcmovbe_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCMOVBE_ST0_STn + reg, OP_32BIT); }
	2535	INLINE void emit_fcmovu_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCMOVU_ST0_STn + reg, OP_32BIT); }
	2536	INLINE void emit_fcmovnb_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCMOVNB_ST0_STn + reg, OP_32BIT); }
	2537	INLINE void emit_fcmovne_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCMOVNE_ST0_STn + reg, OP_32BIT); }
	2538	INLINE void emit_fcmovnbe_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCMOVNBE_ST0_STn + reg, OP_32BIT); }
	2539	INLINE void emit_fcmovnu_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCMOVNU_ST0_STn + reg, OP_32BIT); }
	2540	INLINE void emit_fucomi_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FUCOMI_ST0_STn + reg, OP_32BIT); }
	2541	INLINE void emit_fcomi_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCOMI_ST0_STn + reg, OP_32BIT); }
	2542	INLINE void emit_fcomip_st0_stn(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FCOMIP_ST0_STn + reg, OP_32BIT); }
9380	2543
	2544	INLINE void emit_fadd_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FADD_STn_ST0 + reg, OP_32BIT); }
	2545	INLINE void emit_fmul_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FMUL_STn_ST0 + reg, OP_32BIT); }
	2546	INLINE void emit_fsubr_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FSUBR_STn_ST0 + reg, OP_32BIT); }
	2547	INLINE void emit_fsub_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FSUB_STn_ST0 + reg, OP_32BIT); }
	2548	INLINE void emit_fdivr_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FDIVR_STn_ST0 + reg, OP_32BIT); }
	2549	INLINE void emit_fdiv_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FDIV_STn_ST0 + reg, OP_32BIT); }
	2550	INLINE void emit_fucom_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FUCOM_STn_ST0 + reg, OP_32BIT); }
	2551	INLINE void emit_faddp_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FADDP_STn_ST0 + reg, OP_32BIT); }
	2552	INLINE void emit_fmulp_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FMULP_STn_ST0 + reg, OP_32BIT); }
	2553	INLINE void emit_fsubrp_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FSUBRP_STn_ST0 + reg, OP_32BIT); }
	2554	INLINE void emit_fsubp_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FSUBP_STn_ST0 + reg, OP_32BIT); }
	2555	INLINE void emit_fdivrp_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FDIVRP_STn_ST0 + reg, OP_32BIT); }
	2556	INLINE void emit_fdivp_stn_st0(x86code **emitptr, UINT8 reg) { emit_op_simple(emitptr, OP_FDIVP_STn_ST0 + reg, OP_32BIT); }
9381	2557
9382		/*------------------------------------------------------------------
9383		emit_lea_r64_*
9384		------------------------------------------------------------------*/
	2558	INLINE void emit_faddp(x86code **emitptr) { emit_faddp_stn_st0(emitptr, 1); }
	2559	INLINE void emit_fmulp(x86code **emitptr) { emit_fmulp_stn_st0(emitptr, 1); }
	2560	INLINE void emit_fsubrp(x86code **emitptr) { emit_fsubrp_stn_st0(emitptr, 1); }
	2561	INLINE void emit_fsubp(x86code **emitptr) { emit_fsubp_stn_st0(emitptr, 1); }
	2562	INLINE void emit_fdivrp(x86code **emitptr) { emit_fdivrp_stn_st0(emitptr, 1); }
	2563	INLINE void emit_fdivp(x86code **emitptr) { emit_fdivp_stn_st0(emitptr, 1); }
9385	2564
9386		#ifdef PTR64
9387		INLINE void emit_lea_r64_m64bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
9388		{
9389		emit_op_modrm_mem(emitptr, OP_LEA_Gv_M, OP_64BIT, dreg, base, index, scale, disp);
9390		}
9391
9392		#define emit_lea_r64_m64abs(e, dreg, addr) emit_lea_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9393		#define emit_lea_r64_m64bd(e, dreg, base, disp) emit_lea_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
9394		#define emit_lea_r64_m64isd(e, dreg, index, scale, disp) emit_lea_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
9395	2565	#endif
9396	2566
9397	2567
9398	2568
9399	2569	/***************************************************************************
9400		~~PUSH/P~~OP EMITTERS
	2570	MEMORY FPU EMITTERS
9401	2571	***************************************************************************/
9402	2572
9403		/*------------------------------------------------------------------
9404		emit_push_*
9405		------------------------------------------------------------------*/
9406
9407	2573	#ifndef PTR64
9408		INLINE void emit_push_r32(x86code **emitptr, UINT8 reg)
9409		{
9410		emit_op(emitptr, OP_PUSH_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
9411		}
9412		#endif
9413	2574
9414		#ifdef PTR64
9415		INLINE void emit_push_r64(x86code **emitptr, UINT8 reg)
9416		{
9417		emit_op(emitptr, OP_PUSH_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
9418		}
9419		#endif
	2575	INLINE void emit_fadd_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D8, OP_32BIT, 0, MEMPARAMS); }
	2576	INLINE void emit_fmul_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D8, OP_32BIT, 1, MEMPARAMS); }
	2577	INLINE void emit_fcom_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D8, OP_32BIT, 2, MEMPARAMS); }
	2578	INLINE void emit_fcomp_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D8, OP_32BIT, 3, MEMPARAMS); }
	2579	INLINE void emit_fsub_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D8, OP_32BIT, 4, MEMPARAMS); }
	2580	INLINE void emit_fsubr_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D8, OP_32BIT, 5, MEMPARAMS); }
	2581	INLINE void emit_fdiv_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D8, OP_32BIT, 6, MEMPARAMS); }
	2582	INLINE void emit_fdivr_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D8, OP_32BIT, 7, MEMPARAMS); }
9420	2583
	2584	INLINE void emit_fld_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D9, OP_32BIT, 0, MEMPARAMS); }
	2585	INLINE void emit_fst_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D9, OP_32BIT, 2, MEMPARAMS); }
	2586	INLINE void emit_fstp_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D9, OP_32BIT, 3, MEMPARAMS); }
	2587	INLINE void emit_fldenv_m(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D9, OP_32BIT, 4, MEMPARAMS); }
	2588	INLINE void emit_fldcw_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D9, OP_32BIT, 5, MEMPARAMS); }
	2589	INLINE void emit_fstenv_m(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D9, OP_32BIT, 6, MEMPARAMS); }
	2590	INLINE void emit_fstcw_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_D9, OP_32BIT, 7, MEMPARAMS); }
9421	2591
9422		/*------------------------------------------------------------------
9423		emit_pop_*
9424		------------------------------------------------------------------*/
	2592	INLINE void emit_fiadd_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DA, OP_32BIT, 0, MEMPARAMS); }
	2593	INLINE void emit_fimul_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DA, OP_32BIT, 1, MEMPARAMS); }
	2594	INLINE void emit_ficom_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DA, OP_32BIT, 2, MEMPARAMS); }
	2595	INLINE void emit_ficomp_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DA, OP_32BIT, 3, MEMPARAMS); }
	2596	INLINE void emit_fisub_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DA, OP_32BIT, 4, MEMPARAMS); }
	2597	INLINE void emit_fisubr_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DA, OP_32BIT, 5, MEMPARAMS); }
	2598	INLINE void emit_fidiv_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DA, OP_32BIT, 6, MEMPARAMS); }
	2599	INLINE void emit_fidivr_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DA, OP_32BIT, 7, MEMPARAMS); }
9425	2600
9426		#ifndef PTR64
9427		INLINE void emit_pop_r32(x86code **emitptr, UINT8 reg)
9428		{
9429		emit_op(emitptr, OP_POP_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
9430		}
9431		#endif
	2601	INLINE void emit_fild_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DB, OP_32BIT, 0, MEMPARAMS); }
	2602	INLINE void emit_fisttp_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DB, OP_32BIT, 1, MEMPARAMS); }
	2603	INLINE void emit_fist_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DB, OP_32BIT, 2, MEMPARAMS); }
	2604	INLINE void emit_fistp_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DB, OP_32BIT, 3, MEMPARAMS); }
	2605	INLINE void emit_fld_m80(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DB, OP_32BIT, 5, MEMPARAMS); }
	2606	INLINE void emit_fstp_m80(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DB, OP_32BIT, 7, MEMPARAMS); }
9432	2607
9433		#ifdef PTR64
9434		INLINE void emit_pop_r64(x86code **emitptr, UINT8 reg)
9435		{
9436		emit_op(emitptr, OP_POP_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
9437		}
9438		#endif
	2608	INLINE void emit_fadd_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DC, OP_32BIT, 0, MEMPARAMS); }
	2609	INLINE void emit_fmul_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DC, OP_32BIT, 1, MEMPARAMS); }
	2610	INLINE void emit_fcom_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DC, OP_32BIT, 2, MEMPARAMS); }
	2611	INLINE void emit_fcomp_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DC, OP_32BIT, 3, MEMPARAMS); }
	2612	INLINE void emit_fsub_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DC, OP_32BIT, 4, MEMPARAMS); }
	2613	INLINE void emit_fsubr_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DC, OP_32BIT, 5, MEMPARAMS); }
	2614	INLINE void emit_fdiv_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DC, OP_32BIT, 6, MEMPARAMS); }
	2615	INLINE void emit_fdivr_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DC, OP_32BIT, 7, MEMPARAMS); }
9439	2616
	2617	INLINE void emit_fld_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DD, OP_32BIT, 0, MEMPARAMS); }
	2618	INLINE void emit_fisttp_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DD, OP_32BIT, 1, MEMPARAMS); }
	2619	INLINE void emit_fst_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DD, OP_32BIT, 2, MEMPARAMS); }
	2620	INLINE void emit_fstp_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DD, OP_32BIT, 3, MEMPARAMS); }
	2621	INLINE void emit_frstor_m(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DD, OP_32BIT, 4, MEMPARAMS); }
	2622	INLINE void emit_fsave_m(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DD, OP_32BIT, 6, MEMPARAMS); }
	2623	INLINE void emit_fstsw_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DD, OP_32BIT, 7, MEMPARAMS); }
9440	2624
	2625	INLINE void emit_fiadd_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DE, OP_32BIT, 0, MEMPARAMS); }
	2626	INLINE void emit_fimul_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DE, OP_32BIT, 1, MEMPARAMS); }
	2627	INLINE void emit_ficom_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DE, OP_32BIT, 2, MEMPARAMS); }
	2628	INLINE void emit_ficomp_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DE, OP_32BIT, 3, MEMPARAMS); }
	2629	INLINE void emit_fisub_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DE, OP_32BIT, 4, MEMPARAMS); }
	2630	INLINE void emit_fisubr_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DE, OP_32BIT, 5, MEMPARAMS); }
	2631	INLINE void emit_fidiv_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DE, OP_32BIT, 6, MEMPARAMS); }
	2632	INLINE void emit_fidivr_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DE, OP_32BIT, 7, MEMPARAMS); }
9441	2633
9442		/***************************************************************************
9443		SET EMITTERS
9444		***************************************************************************/
	2634	INLINE void emit_fild_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DF, OP_32BIT, 0, MEMPARAMS); }
	2635	INLINE void emit_fisttp_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DF, OP_32BIT, 1, MEMPARAMS); }
	2636	INLINE void emit_fist_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DF, OP_32BIT, 2, MEMPARAMS); }
	2637	INLINE void emit_fistp_m16(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DF, OP_32BIT, 3, MEMPARAMS); }
	2638	INLINE void emit_fbld_m80(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DF, OP_32BIT, 4, MEMPARAMS); }
	2639	INLINE void emit_fild_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DF, OP_32BIT, 5, MEMPARAMS); }
	2640	INLINE void emit_fbstp_m80(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DF, OP_32BIT, 6, MEMPARAMS); }
	2641	INLINE void emit_fistp_m64(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ESC_DF, OP_32BIT, 7, MEMPARAMS); }
9445	2642
9446		/*------------------------------------------------------------------
9447		emit_setcc_*
9448		------------------------------------------------------------------*/
	2643	#endif
9449	2644
9450		INLINE void emit_setcc_r8(x86code **emitptr, UINT8 condition, UINT8 dreg)
9451		{
9452		emit_op_modrm_reg(emitptr, OP_SETCC_O_Eb + condition, OP_32BIT, 0, dreg);
9453		}
9454	2645
9455		INLINE void emit_setcc_m8bisd(x86code **emitptr, UINT8 condition, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
9456		{
9457		emit_op_modrm_mem(emitptr, OP_SETCC_O_Eb + condition, OP_32BIT, 0, base, index, scale, disp);
9458		}
9459	2646
9460		#define emit_setcc_m8abs(e, cond, addr) emit_setcc_m8bisd(e, cond, REG_NONE, REG_NONE, 1, (INT32)(addr))
9461		#define emit_setcc_m8bd(e, cond, base, disp) emit_setcc_m8bisd(e, cond, (base), REG_NONE, 1, (disp))
9462		#define emit_setcc_m8isd(e, cond, index, scale, disp) emit_setcc_m8bisd(e, cond, REG_NONE, (index), (scale), (disp))
9463
9464
9465
9466	2647	/***************************************************************************
9467	2648	GROUP16 EMITTERS
9468	2649	***************************************************************************/
9469	2650
9470		/*------------------------------------------------------------------
9471		emit_ldmxcsr_*
9472		------------------------------------------------------------------*/
	2651	INLINE void emit_ldmxcsr_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G16, OP_32BIT, 2, MEMPARAMS); }
	2652	INLINE void emit_stmxcsr_m32(x86code **emitptr, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_G16, OP_32BIT, 3, MEMPARAMS); }
9473	2653
9474		INLINE void emit_ldmxcsr_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
9475		{
9476		emit_op_modrm_mem(emitptr, OP_G16, OP_32BIT, 2, base, index, scale, disp);
9477		}
9478	2654
9479		#define emit_ldmxcsr_m32abs(e, addr) emit_ldmxcsr_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9480		#define emit_ldmxcsr_m32bd(e, base, disp) emit_ldmxcsr_m32bisd(e, (base), REG_NONE, 1, (disp))
9481		#define emit_ldmxcsr_m32isd(e, index, scale, disp) emit_ldmxcsr_m32bisd(e, REG_NONE, (index), (scale), (disp))
9482	2655
9483
9484		/*------------------------------------------------------------------
9485		emit_stmxcsr_*
9486		------------------------------------------------------------------*/
9487
9488		INLINE void emit_stmxcsr_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
9489		{
9490		emit_op_modrm_mem(emitptr, OP_G16, OP_32BIT, 3, base, index, scale, disp);
9491		}
9492
9493		#define emit_stmxcsr_m32abs(e, addr) emit_stmxcsr_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
9494		#define emit_stmxcsr_m32bd(e, base, disp) emit_stmxcsr_m32bisd(e, (base), REG_NONE, 1, (disp))
9495		#define emit_stmxcsr_m32isd(e, index, scale, disp) emit_stmxcsr_m32bisd(e, REG_NONE, (index), (scale), (disp))
9496
9497
9498
9499	2656	/***************************************************************************
9500		SSE EMITTERS
9501		***************************************************************************/
9502
9503		INLINE void emit_sse_r128_r128(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 sreg)
9504		{
9505		emit_op_modrm_reg(emitptr, op, OP_32BIT, dreg, sreg);
9506		}
9507
9508		INLINE void emit_sse_r128_mbisd(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
9509		{
9510		emit_op_modrm_mem(emitptr, op, OP_32BIT, dreg, base, index, scale, disp);
9511		}
9512
9513		INLINE void emit_sse_r128_r128_rex(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 sreg)
9514		{
9515		emit_op_modrm_reg(emitptr, op, OP_64BIT, dreg, sreg);
9516		}
9517
9518		INLINE void emit_sse_r128_mbisd_rex(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
9519		{
9520		emit_op_modrm_mem(emitptr, op, OP_64BIT, dreg, base, index, scale, disp);
9521		}
9522
9523
9524
9525		/***************************************************************************
9526	2657	SSE SCALAR SINGLE EMITTERS
9527	2658	***************************************************************************/
9528	2659
9529		#define emit_movss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVSS_Vss_Wss, dreg, sreg)
9530		#define emit_movss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9531		#define emit_movss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
9532		#define emit_movss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2660	INLINE void emit_movss_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVSS_Vss_Wss, OP_32BIT, dreg, sreg); }
	2661	INLINE void emit_movss_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVSS_Vss_Wss, OP_32BIT, dreg, MEMPARAMS); }
	2662	INLINE void emit_movss_m32_r128(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_MOVSS_Wss_Vss, OP_32BIT, sreg, MEMPARAMS); }
9533	2663
9534		#define emit_movss_m32abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVSS_Wss_Vss, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9535		#define emit_movss_m32bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSS_Wss_Vss, sreg, (base), REG_NONE, 1, (disp))
9536		#define emit_movss_m32isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSS_Wss_Vss, sreg, REG_NONE, (index), (scale), (disp))
	2664	INLINE void emit_addss_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADDSS_Vss_Wss, OP_32BIT, dreg, sreg); }
	2665	INLINE void emit_addss_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADDSS_Vss_Wss, OP_32BIT, dreg, MEMPARAMS); }
9537	2666
9538		#define emit_addss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDSS_Vss_Wss, dreg, sreg)
9539		#define emit_addss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9540		#define emit_addss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
9541		#define emit_addss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2667	INLINE void emit_subss_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SUBSS_Vss_Wss, OP_32BIT, dreg, sreg); }
	2668	INLINE void emit_subss_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SUBSS_Vss_Wss, OP_32BIT, dreg, MEMPARAMS); }
9542	2669
9543		#define emit_subss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBSS_Vss_Wss, dreg, sreg)
9544		#define emit_subss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9545		#define emit_subss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
9546		#define emit_subss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2670	INLINE void emit_mulss_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MULSS_Vss_Wss, OP_32BIT, dreg, sreg); }
	2671	INLINE void emit_mulss_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MULSS_Vss_Wss, OP_32BIT, dreg, MEMPARAMS); }
9547	2672
9548		#define emit_mulss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULSS_Vss_Wss, dreg, sreg)
9549		#define emit_mulss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9550		#define emit_mulss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
9551		#define emit_mulss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2673	INLINE void emit_divss_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_DIVSS_Vss_Wss, OP_32BIT, dreg, sreg); }
	2674	INLINE void emit_divss_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_DIVSS_Vss_Wss, OP_32BIT, dreg, MEMPARAMS); }
9552	2675
9553		#define emit_divss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVSS_Vss_Wss, dreg, sreg)
9554		#define emit_divss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9555		#define emit_divss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
9556		#define emit_divss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2676	INLINE void emit_rcpss_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_RCPSS_Vss_Wss, OP_32BIT, dreg, sreg); }
	2677	INLINE void emit_rcpss_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_RCPSS_Vss_Wss, OP_32BIT, dreg, MEMPARAMS); }
9557	2678
9558		#define emit_rcpss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RCPSS_Vss_Wss, dreg, sreg)
9559		#define emit_rcpss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RCPSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9560		#define emit_rcpss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RCPSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
9561		#define emit_rcpss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RCPSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2679	INLINE void emit_sqrtss_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SQRTSS_Vss_Wss, OP_32BIT, dreg, sreg); }
	2680	INLINE void emit_sqrtss_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SQRTSS_Vss_Wss, OP_32BIT, dreg, MEMPARAMS); }
9562	2681
9563		#define emit_sqrtss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTSS_Vss_Wss, dreg, sreg)
9564		#define emit_sqrtss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9565		#define emit_sqrtss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
9566		#define emit_sqrtss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2682	INLINE void emit_rsqrtss_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_RSQRTSS_Vss_Wss, OP_32BIT, dreg, sreg); }
	2683	INLINE void emit_rsqrtss_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_RSQRTSS_Vss_Wss, OP_32BIT, dreg, MEMPARAMS); }
9567	2684
9568		#define emit_rsqrtss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RSQRTSS_Vss_Wss, dreg, sreg)
9569		#define emit_rsqrtss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RSQRTSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9570		#define emit_rsqrtss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RSQRTSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
9571		#define emit_rsqrtss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RSQRTSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2685	INLINE void emit_comiss_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_COMISS_Vss_Wss, OP_32BIT, dreg, sreg); }
	2686	INLINE void emit_comiss_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_COMISS_Vss_Wss, OP_32BIT, dreg, MEMPARAMS); }
9572	2687
9573		#define emit_comiss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_COMISS_Vss_Wss, dreg, sreg)
9574		#define emit_comiss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_COMISS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9575		#define emit_comiss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_COMISS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
9576		#define emit_comiss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_COMISS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2688	INLINE void emit_ucomiss_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_UCOMISS_Vss_Wss, OP_32BIT, dreg, sreg); }
	2689	INLINE void emit_ucomiss_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_UCOMISS_Vss_Wss, OP_32BIT, dreg, MEMPARAMS); }
9577	2690
9578		#define emit_ucomiss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_UCOMISS_Vss_Wss, dreg, sreg)
9579		#define emit_ucomiss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_UCOMISS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9580		#define emit_ucomiss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_UCOMISS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
9581		#define emit_ucomiss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_UCOMISS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2691	INLINE void emit_cvtsi2ss_r128_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTSI2SS_Vss_Ed, OP_32BIT, dreg, sreg); }
	2692	INLINE void emit_cvtsi2ss_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTSI2SS_Vss_Ed, OP_32BIT, dreg, MEMPARAMS); }
9582	2693
9583		#define emit_cvtsi2ss_r128_r32(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSI2SS_Vss_Ed, dreg, sreg)
9584		#define emit_cvtsi2ss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9585		#define emit_cvtsi2ss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SS_Vss_Ed, dreg, (base), REG_NONE, 1, (disp))
9586		#define emit_cvtsi2ss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, (index), (scale), (disp))
9587
9588	2694	#ifdef PTR64
9589		#define emit_cvtsi2ss_r128_r64(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, sreg)
9590		#define emit_cvtsi2ss_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9591		#define emit_cvtsi2ss_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, (base), REG_NONE, 1, (disp))
9592		#define emit_cvtsi2ss_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, (index), (scale), (disp))
	2695	INLINE void emit_cvtsi2ss_r128_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTSI2SS_Vss_Ed, OP_64BIT, dreg, sreg); }
	2696	INLINE void emit_cvtsi2ss_r128_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTSI2SS_Vss_Ed, OP_64BIT, dreg, MEMPARAMS); }
9593	2697	#endif
9594	2698
9595		#define emit_cvtsd2ss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSD2SS_Vss_Wsd, dreg, sreg)
9596		#define emit_cvtsd2ss_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSD2SS_Vss_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9597		#define emit_cvtsd2ss_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SS_Vss_Wsd, dreg, (base), REG_NONE, 1, (disp))
9598		#define emit_cvtsd2ss_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SS_Vss_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2699	INLINE void emit_cvtsd2ss_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTSD2SS_Vss_Wsd, OP_32BIT, dreg, sreg); }
	2700	INLINE void emit_cvtsd2ss_r128_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTSD2SS_Vss_Wsd, OP_32BIT, dreg, MEMPARAMS); }
9599	2701
9600		#define emit_cvtss2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSS2SI_Gd_Wss, dreg, sreg)
9601		#define emit_cvtss2si_r32_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9602		#define emit_cvtss2si_r32_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
9603		#define emit_cvtss2si_r32_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2702	INLINE void emit_cvtss2si_r32_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTSS2SI_Gd_Wss, OP_32BIT, dreg, sreg); }
	2703	INLINE void emit_cvtss2si_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTSS2SI_Gd_Wss, OP_32BIT, dreg, MEMPARAMS); }
9604	2704
9605	2705	#ifdef PTR64
9606		#define emit_cvtss2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, sreg)
9607		#define emit_cvtss2si_r64_m32abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9608		#define emit_cvtss2si_r64_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
9609		#define emit_cvtss2si_r64_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2706	INLINE void emit_cvtss2si_r64_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTSS2SI_Gd_Wss, OP_64BIT, dreg, sreg); }
	2707	INLINE void emit_cvtss2si_r64_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTSS2SI_Gd_Wss, OP_64BIT, dreg, MEMPARAMS); }
9610	2708	#endif
9611	2709
9612		#define emit_cvttss2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTSS2SI_Gd_Wss, dreg, sreg)
9613		#define emit_cvttss2si_r32_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9614		#define emit_cvttss2si_r32_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
9615		#define emit_cvttss2si_r32_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2710	INLINE void emit_cvttss2si_r32_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTTSS2SI_Gd_Wss, OP_32BIT, dreg, sreg); }
	2711	INLINE void emit_cvttss2si_r32_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTTSS2SI_Gd_Wss, OP_32BIT, dreg, MEMPARAMS); }
9616	2712
9617	2713	#ifdef PTR64
9618		#define emit_cvttss2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, sreg)
9619		#define emit_cvttss2si_r64_m32abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9620		#define emit_cvttss2si_r64_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
9621		#define emit_cvttss2si_r64_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2714	INLINE void emit_cvttss2si_r64_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTTSS2SI_Gd_Wss, OP_64BIT, dreg, sreg); }
	2715	INLINE void emit_cvttss2si_r64_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTTSS2SI_Gd_Wss, OP_64BIT, dreg, MEMPARAMS); }
9622	2716	#endif
9623	2717
9624	2718
r949	r950
9627	2721	SSE PACKED SINGLE EMITTERS
9628	2722	***************************************************************************/
9629	2723
9630		#define emit_movps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVPS_Vps_Wps, dreg, sreg)
9631		#define emit_movps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9632		#define emit_movps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9633		#define emit_movps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2724	INLINE void emit_movps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVAPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2725	INLINE void emit_movps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVAPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
	2726	INLINE void emit_movps_m128_r128(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_MOVAPS_Wps_Vps, OP_32BIT, sreg, MEMPARAMS); }
9634	2727
9635		#define emit_movps_m128abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVPS_Wps_Vps, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9636		#define emit_movps_m128bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPS_Wps_Vps, sreg, (base), REG_NONE, 1, (disp))
9637		#define emit_movps_m128isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPS_Wps_Vps, sreg, REG_NONE, (index), (scale), (disp))
	2728	INLINE void emit_addps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADDPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2729	INLINE void emit_addps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADDPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
9638	2730
9639		#define emit_addps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDPS_Vps_Wps, dreg, sreg)
9640		#define emit_addps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9641		#define emit_addps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9642		#define emit_addps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2731	INLINE void emit_subps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SUBPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2732	INLINE void emit_subps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SUBPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
9643	2733
9644		#define emit_subps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBPS_Vps_Wps, dreg, sreg)
9645		#define emit_subps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9646		#define emit_subps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9647		#define emit_subps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2734	INLINE void emit_mulps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MULPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2735	INLINE void emit_mulps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MULPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
9648	2736
9649		#define emit_mulps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULPS_Vps_Wps, dreg, sreg)
9650		#define emit_mulps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9651		#define emit_mulps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9652		#define emit_mulps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2737	INLINE void emit_divps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_DIVPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2738	INLINE void emit_divps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_DIVPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
9653	2739
9654		#define emit_divps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVPS_Vps_Wps, dreg, sreg)
9655		#define emit_divps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9656		#define emit_divps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9657		#define emit_divps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2740	INLINE void emit_rcpps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_RCPPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2741	INLINE void emit_rcpps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_RCPPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
9658	2742
9659		#define emit_rcpps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RCPPS_Vps_Wps, dreg, sreg)
9660		#define emit_rcpps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RCPPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9661		#define emit_rcpps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RCPPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9662		#define emit_rcpps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RCPPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2743	INLINE void emit_sqrtps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SQRTPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2744	INLINE void emit_sqrtps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SQRTPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
9663	2745
9664		#define emit_sqrtps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTPS_Vps_Wps, dreg, sreg)
9665		#define emit_sqrtps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9666		#define emit_sqrtps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9667		#define emit_sqrtps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2746	INLINE void emit_rsqrtps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_RSQRTPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2747	INLINE void emit_rsqrtps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_RSQRTPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
9668	2748
9669		#define emit_rsqrtps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RSQRTPS_Vps_Wps, dreg, sreg)
9670		#define emit_rsqrtps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RSQRTPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9671		#define emit_rsqrtps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RSQRTPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9672		#define emit_rsqrtps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RSQRTPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2749	INLINE void emit_andps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ANDPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2750	INLINE void emit_andps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ANDPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
9673	2751
9674		#define emit_andps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDPS_Vps_Wps, dreg, sreg)
9675		#define emit_andps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9676		#define emit_andps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9677		#define emit_andps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2752	INLINE void emit_andnps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ANDNPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2753	INLINE void emit_andnps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ANDNPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
9678	2754
9679		#define emit_andnps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDNPS_Vps_Wps, dreg, sreg)
9680		#define emit_andnps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDNPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9681		#define emit_andnps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDNPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9682		#define emit_andnps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDNPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2755	INLINE void emit_orps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ORPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2756	INLINE void emit_orps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ORPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
9683	2757
9684		#define emit_orps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ORPS_Vps_Wps, dreg, sreg)
9685		#define emit_orps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ORPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9686		#define emit_orps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ORPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9687		#define emit_orps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ORPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2758	INLINE void emit_xorps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_XORPS_Vps_Wps, OP_32BIT, dreg, sreg); }
	2759	INLINE void emit_xorps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_XORPS_Vps_Wps, OP_32BIT, dreg, MEMPARAMS); }
9688	2760
9689		#define emit_xorps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_XORPS_Vps_Wps, dreg, sreg)
9690		#define emit_xorps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_XORPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9691		#define emit_xorps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_XORPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
9692		#define emit_xorps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_XORPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2761	INLINE void emit_cvtdq2ps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTDQ2PS_Vps_Wdq, OP_32BIT, dreg, sreg); }
	2762	INLINE void emit_cvtdq2ps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTDQ2PS_Vps_Wdq, OP_32BIT, dreg, MEMPARAMS); }
9693	2763
9694		#define emit_cvtdq2ps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTDQ2PS_Vps_Wdq, dreg, sreg)
9695		#define emit_cvtdq2ps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTDQ2PS_Vps_Wdq, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9696		#define emit_cvtdq2ps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PS_Vps_Wdq, dreg, (base), REG_NONE, 1, (disp))
9697		#define emit_cvtdq2ps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PS_Vps_Wdq, dreg, REG_NONE, (index), (scale), (disp))
	2764	INLINE void emit_cvtpd2ps_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTPD2PS_Vps_Wpd, OP_32BIT, dreg, sreg); }
	2765	INLINE void emit_cvtpd2ps_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTPD2PS_Vps_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9698	2766
9699		#define emit_cvtpd2ps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPD2PS_Vps_Wpd, dreg, sreg)
9700		#define emit_cvtpd2ps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPD2PS_Vps_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9701		#define emit_cvtpd2ps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPD2PS_Vps_Wpd, dreg, (base), REG_NONE, 1, (disp))
9702		#define emit_cvtpd2ps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPD2PS_Vps_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	2767	INLINE void emit_cvtps2dq_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTPS2DQ_Vdq_Wps, OP_32BIT, dreg, sreg); }
	2768	INLINE void emit_cvtps2dq_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTPS2DQ_Vdq_Wps, OP_32BIT, dreg, MEMPARAMS); }
9703	2769
9704		#define emit_cvtps2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPS2DQ_Vdq_Wps, dreg, sreg)
9705		#define emit_cvtps2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPS2DQ_Vdq_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9706		#define emit_cvtps2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPS2DQ_Vdq_Wps, dreg, (base), REG_NONE, 1, (disp))
9707		#define emit_cvtps2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPS2DQ_Vdq_Wps, dreg, REG_NONE, (index), (scale), (disp))
	2770	INLINE void emit_cvttps2dq_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTTPS2DQ_Vdq_Wps, OP_32BIT, dreg, sreg); }
	2771	INLINE void emit_cvttps2dq_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTTPS2DQ_Vdq_Wps, OP_32BIT, dreg, MEMPARAMS); }
9708	2772
9709		#define emit_cvttps2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, sreg)
9710		#define emit_cvttps2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9711		#define emit_cvttps2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, (base), REG_NONE, 1, (disp))
9712		#define emit_cvttps2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, REG_NONE, (index), (scale), (disp))
9713	2773
9714	2774
9715
9716	2775	/***************************************************************************
9717	2776	SSE SCALAR DOUBLE EMITTERS
9718	2777	***************************************************************************/
9719	2778
9720		#define emit_movsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVSD_Vsd_Wsd, dreg, sreg)
9721		#define emit_movsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9722		#define emit_movsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9723		#define emit_movsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2779	INLINE void emit_movsd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVSD_Vsd_Wsd, OP_32BIT, dreg, sreg); }
	2780	INLINE void emit_movsd_r128_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVSD_Vsd_Wsd, OP_32BIT, dreg, MEMPARAMS); }
	2781	INLINE void emit_movsd_m64_r128(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_MOVSD_Wsd_Vsd, OP_32BIT, sreg, MEMPARAMS); }
9724	2782
9725		#define emit_movsd_m64abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVSD_Wsd_Vsd, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9726		#define emit_movsd_m64bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSD_Wsd_Vsd, sreg, (base), REG_NONE, 1, (disp))
9727		#define emit_movsd_m64isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSD_Wsd_Vsd, sreg, REG_NONE, (index), (scale), (disp))
	2783	INLINE void emit_addsd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADDSD_Vsd_Wsd, OP_32BIT, dreg, sreg); }
	2784	INLINE void emit_addsd_r128_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADDSD_Vsd_Wsd, OP_32BIT, dreg, MEMPARAMS); }
9728	2785
9729		#define emit_addsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDSD_Vsd_Wsd, dreg, sreg)
9730		#define emit_addsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9731		#define emit_addsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9732		#define emit_addsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2786	INLINE void emit_subsd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SUBSD_Vsd_Wsd, OP_32BIT, dreg, sreg); }
	2787	INLINE void emit_subsd_r128_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SUBSD_Vsd_Wsd, OP_32BIT, dreg, MEMPARAMS); }
9733	2788
9734		#define emit_subsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBSD_Vsd_Wsd, dreg, sreg)
9735		#define emit_subsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9736		#define emit_subsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9737		#define emit_subsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2789	INLINE void emit_mulsd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MULSD_Vsd_Wsd, OP_32BIT, dreg, sreg); }
	2790	INLINE void emit_mulsd_r128_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MULSD_Vsd_Wsd, OP_32BIT, dreg, MEMPARAMS); }
9738	2791
9739		#define emit_mulsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULSD_Vsd_Wsd, dreg, sreg)
9740		#define emit_mulsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9741		#define emit_mulsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9742		#define emit_mulsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2792	INLINE void emit_divsd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_DIVSD_Vsd_Wsd, OP_32BIT, dreg, sreg); }
	2793	INLINE void emit_divsd_r128_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_DIVSD_Vsd_Wsd, OP_32BIT, dreg, MEMPARAMS); }
9743	2794
9744		#define emit_divsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVSD_Vsd_Wsd, dreg, sreg)
9745		#define emit_divsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9746		#define emit_divsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9747		#define emit_divsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2795	INLINE void emit_sqrtsd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SQRTSD_Vsd_Wsd, OP_32BIT, dreg, sreg); }
	2796	INLINE void emit_sqrtsd_r128_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SQRTSD_Vsd_Wsd, OP_32BIT, dreg, MEMPARAMS); }
9748	2797
9749		#define emit_sqrtsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTSD_Vsd_Wsd, dreg, sreg)
9750		#define emit_sqrtsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9751		#define emit_sqrtsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9752		#define emit_sqrtsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2798	INLINE void emit_comisd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_COMISD_Vsd_Wsd, OP_32BIT, dreg, sreg); }
	2799	INLINE void emit_comisd_r128_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_COMISD_Vsd_Wsd, OP_32BIT, dreg, MEMPARAMS); }
9753	2800
9754		#define emit_comisd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_COMISD_Vsd_Wsd, dreg, sreg)
9755		#define emit_comisd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_COMISD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9756		#define emit_comisd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_COMISD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9757		#define emit_comisd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_COMISD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2801	INLINE void emit_ucomisd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_UCOMISD_Vsd_Wsd, OP_32BIT, dreg, sreg); }
	2802	INLINE void emit_ucomisd_r128_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_UCOMISD_Vsd_Wsd, OP_32BIT, dreg, MEMPARAMS); }
9758	2803
9759		#define emit_ucomisd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_UCOMISD_Vsd_Wsd, dreg, sreg)
9760		#define emit_ucomisd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_UCOMISD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9761		#define emit_ucomisd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_UCOMISD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9762		#define emit_ucomisd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_UCOMISD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2804	INLINE void emit_cvtsi2sd_r128_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTSI2SD_Vsd_Ed, OP_32BIT, dreg, sreg); }
	2805	INLINE void emit_cvtsi2sd_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTSI2SD_Vsd_Ed, OP_32BIT, dreg, MEMPARAMS); }
9763	2806
9764		#define emit_cvtsi2sd_r128_r32(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSI2SD_Vsd_Ed, dreg, sreg)
9765		#define emit_cvtsi2sd_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9766		#define emit_cvtsi2sd_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SD_Vsd_Ed, dreg, (base), REG_NONE, 1, (disp))
9767		#define emit_cvtsi2sd_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, (index), (scale), (disp))
9768
9769	2807	#ifdef PTR64
9770		#define emit_cvtsi2sd_r128_r64(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, sreg)
9771		#define emit_cvtsi2sd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9772		#define emit_cvtsi2sd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, (base), REG_NONE, 1, (disp))
9773		#define emit_cvtsi2sd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, (index), (scale), (disp))
	2808	INLINE void emit_cvtsi2sd_r128_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTSI2SD_Vsd_Ed, OP_64BIT, dreg, sreg); }
	2809	INLINE void emit_cvtsi2sd_r128_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTSI2SD_Vsd_Ed, OP_64BIT, dreg, MEMPARAMS); }
9774	2810	#endif
9775	2811
9776		#define emit_cvtss2sd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSS2SD_Vsd_Wss, dreg, sreg)
9777		#define emit_cvtss2sd_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSS2SD_Vsd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9778		#define emit_cvtss2sd_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SD_Vsd_Wss, dreg, (base), REG_NONE, 1, (disp))
9779		#define emit_cvtss2sd_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SD_Vsd_Wss, dreg, REG_NONE, (index), (scale), (disp))
	2812	INLINE void emit_cvtss2sd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTSS2SD_Vsd_Wss, OP_32BIT, dreg, sreg); }
	2813	INLINE void emit_cvtss2sd_r128_m32(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTSS2SD_Vsd_Wss, OP_32BIT, dreg, MEMPARAMS); }
9780	2814
9781		#define emit_cvtsd2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSD2SI_Gd_Wsd, dreg, sreg)
9782		#define emit_cvtsd2si_r32_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9783		#define emit_cvtsd2si_r32_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9784		#define emit_cvtsd2si_r32_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2815	INLINE void emit_cvtsd2si_r32_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTSD2SI_Gd_Wsd, OP_32BIT, dreg, sreg); }
	2816	INLINE void emit_cvtsd2si_r32_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTSD2SI_Gd_Wsd, OP_32BIT, dreg, MEMPARAMS); }
9785	2817
9786	2818	#ifdef PTR64
9787		#define emit_cvtsd2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, sreg)
9788		#define emit_cvtsd2si_r64_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9789		#define emit_cvtsd2si_r64_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9790		#define emit_cvtsd2si_r64_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2819	INLINE void emit_cvtsd2si_r64_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTSD2SI_Gd_Wsd, OP_64BIT, dreg, sreg); }
	2820	INLINE void emit_cvtsd2si_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTSD2SI_Gd_Wsd, OP_64BIT, dreg, MEMPARAMS); }
9791	2821	#endif
9792	2822
9793		#define emit_cvttsd2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTSD2SI_Gd_Wsd, dreg, sreg)
9794		#define emit_cvttsd2si_r32_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9795		#define emit_cvttsd2si_r32_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9796		#define emit_cvttsd2si_r32_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2823	INLINE void emit_cvttsd2si_r32_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTTSD2SI_Gd_Wsd, OP_32BIT, dreg, sreg); }
	2824	INLINE void emit_cvttsd2si_r32_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTTSD2SI_Gd_Wsd, OP_32BIT, dreg, MEMPARAMS); }
9797	2825
9798	2826	#ifdef PTR64
9799		#define emit_cvttsd2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, sreg)
9800		#define emit_cvttsd2si_r64_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9801		#define emit_cvttsd2si_r64_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
9802		#define emit_cvttsd2si_r64_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	2827	INLINE void emit_cvttsd2si_r64_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTTSD2SI_Gd_Wsd, OP_64BIT, dreg, sreg); }
	2828	INLINE void emit_cvttsd2si_r64_m64(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTTSD2SI_Gd_Wsd, OP_64BIT, dreg, MEMPARAMS); }
9803	2829	#endif
9804	2830
9805	2831
r949	r950
9808	2834	SSE PACKED DOUBLE EMITTERS
9809	2835	***************************************************************************/
9810	2836
9811		#define emit_movpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVPD_Vpd_Wpd, dreg, sreg)
9812		#define emit_movpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9813		#define emit_movpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
9814		#define emit_movpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9815		#define emit_movpd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVPD_Vpd_Wpd, dreg, (base), (index), (scale), (disp))
	2837	INLINE void emit_movpd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MOVAPD_Vpd_Wpd, OP_32BIT, dreg, sreg); }
	2838	INLINE void emit_movpd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MOVAPD_Vpd_Wpd, OP_32BIT, dreg, MEMPARAMS); }
	2839	INLINE void emit_movpd_m128_r128(x86code **emitptr, DECLARE_MEMPARAMS, UINT8 sreg) { emit_op_modrm_mem(emitptr, OP_MOVAPD_Wpd_Vpd, OP_32BIT, sreg, MEMPARAMS); }
9816	2840
9817		#define emit_movpd_m128abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVPD_Wpd_Vpd, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9818		#define emit_movpd_m128bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPD_Wpd_Vpd, sreg, (base), REG_NONE, 1, (disp))
9819		#define emit_movpd_m128isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPD_Wpd_Vpd, sreg, REG_NONE, (index), (scale), (disp))
9820		#define emit_movpd_m128bisd_r128(e, base, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPD_Wpd_Vpd, sreg, (base), (index), (scale), (disp))
	2841	INLINE void emit_addpd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ADDPD_Vpd_Wpd, OP_32BIT, dreg, sreg); }
	2842	INLINE void emit_addpd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ADDPD_Vpd_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9821	2843
9822		#define emit_addpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDPD_Vpd_Wpd, dreg, sreg)
9823		#define emit_addpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9824		#define emit_addpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
9825		#define emit_addpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9826		#define emit_addpd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDPD_Vpd_Wpd, dreg, (base), (index), (scale), (disp))
	2844	INLINE void emit_subpd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SUBPD_Vpd_Wpd, OP_32BIT, dreg, sreg); }
	2845	INLINE void emit_subpd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SUBPD_Vpd_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9827	2846
9828		#define emit_subpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBPD_Vpd_Wpd, dreg, sreg)
9829		#define emit_subpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9830		#define emit_subpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
9831		#define emit_subpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9832		#define emit_subpd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBPD_Vpd_Wpd, dreg, (base), (index), (scale), (disp))
	2847	INLINE void emit_mulpd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_MULPD_Vpd_Wpd, OP_32BIT, dreg, sreg); }
	2848	INLINE void emit_mulpd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_MULPD_Vpd_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9833	2849
9834		#define emit_mulpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULPD_Vpd_Wpd, dreg, sreg)
9835		#define emit_mulpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9836		#define emit_mulpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
9837		#define emit_mulpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9838		#define emit_mulpd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULPD_Vpd_Wpd, dreg, (base), (index), (scale), (disp))
	2850	INLINE void emit_divpd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_DIVPD_Vpd_Wpd, OP_32BIT, dreg, sreg); }
	2851	INLINE void emit_divpd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_DIVPD_Vpd_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9839	2852
9840		#define emit_divpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVPD_Vpd_Wpd, dreg, sreg)
9841		#define emit_divpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9842		#define emit_divpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
9843		#define emit_divpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9844		#define emit_divpd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVPD_Vpd_Wpd, dreg, (base), (index), (scale), (disp))
	2853	INLINE void emit_sqrtpd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_SQRTPD_Vpd_Wpd, OP_32BIT, dreg, sreg); }
	2854	INLINE void emit_sqrtpd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_SQRTPD_Vpd_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9845	2855
9846		#define emit_sqrtpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTPD_Vpd_Wpd, dreg, sreg)
9847		#define emit_sqrtpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9848		#define emit_sqrtpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
9849		#define emit_sqrtpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9850		#define emit_sqrtpd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTPD_Vpd_Wpd, dreg, (base), (index), (scale), (disp))
	2856	INLINE void emit_andpd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ANDPD_Vpd_Wpd, OP_32BIT, dreg, sreg); }
	2857	INLINE void emit_andpd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ANDPD_Vpd_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9851	2858
9852		#define emit_andpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDPD_Vpd_Wpd, dreg, sreg)
9853		#define emit_andpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9854		#define emit_andpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
9855		#define emit_andpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9856		#define emit_andpd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDPD_Vpd_Wpd, dreg, (base), (index), (scale), (disp))
	2859	INLINE void emit_andnpd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ANDNPD_Vpd_Wpd, OP_32BIT, dreg, sreg); }
	2860	INLINE void emit_andnpd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ANDNPD_Vpd_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9857	2861
9858		#define emit_andnpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDNPD_Vpd_Wpd, dreg, sreg)
9859		#define emit_andnpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDNPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9860		#define emit_andnpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDNPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
9861		#define emit_andnpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDNPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9862		#define emit_andnpd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDNPD_Vpd_Wpd, dreg, (base), (index), (scale), (disp))
	2862	INLINE void emit_orpd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_ORPD_Vpd_Wpd, OP_32BIT, dreg, sreg); }
	2863	INLINE void emit_orpd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_ORPD_Vpd_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9863	2864
9864		#define emit_orpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ORPD_Vpd_Wpd, dreg, sreg)
9865		#define emit_orpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ORPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9866		#define emit_orpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ORPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
9867		#define emit_orpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ORPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9868		#define emit_orpd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_ORPD_Vpd_Wpd, dreg, (base), (index), (scale), (disp))
	2865	INLINE void emit_xorpd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_XORPD_Vpd_Wpd, OP_32BIT, dreg, sreg); }
	2866	INLINE void emit_xorpd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_XORPD_Vpd_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9869	2867
9870		#define emit_xorpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_XORPD_Vpd_Wpd, dreg, sreg)
9871		#define emit_xorpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_XORPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9872		#define emit_xorpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_XORPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
9873		#define emit_xorpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_XORPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9874		#define emit_xorpd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_XORPD_Vpd_Wpd, dreg, (base), (index), (scale), (disp))
	2868	INLINE void emit_cvtdq2pd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTDQ2PD_Vpd_Wq, OP_32BIT, dreg, sreg); }
	2869	INLINE void emit_cvtdq2pd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTDQ2PD_Vpd_Wq, OP_32BIT, dreg, MEMPARAMS); }
9875	2870
9876		#define emit_cvtdq2pd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTDQ2PD_Vpd_Wq, dreg, sreg)
9877		#define emit_cvtdq2pd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTDQ2PD_Vpd_Wq, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9878		#define emit_cvtdq2pd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PD_Vpd_Wq, dreg, (base), REG_NONE, 1, (disp))
9879		#define emit_cvtdq2pd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PD_Vpd_Wq, dreg, REG_NONE, (index), (scale), (disp))
9880		#define emit_cvtdq2pd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PD_Vpd_Wq, dreg, (base), (index), (scale), (disp))
	2871	INLINE void emit_cvtps2pd_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTPS2PD_Vpd_Wq, OP_32BIT, dreg, sreg); }
	2872	INLINE void emit_cvtps2pd_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTPS2PD_Vpd_Wq, OP_32BIT, dreg, MEMPARAMS); }
9881	2873
9882		#define emit_cvtps2pd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPS2PD_Vpd_Wq, dreg, sreg)
9883		#define emit_cvtps2pd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPS2PD_Vpd_Wq, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9884		#define emit_cvtps2pd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPS2PD_Vpd_Wq, dreg, (base), REG_NONE, 1, (disp))
9885		#define emit_cvtps2pd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPS2PD_Vpd_Wq, dreg, REG_NONE, (index), (scale), (disp))
9886		#define emit_cvtps2pd_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPS2PD_Vpd_Wq, dreg, (base), (index), (scale), (disp))
	2874	INLINE void emit_cvtpd2dq_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTPD2DQ_Vdq_Wpd, OP_32BIT, dreg, sreg); }
	2875	INLINE void emit_cvtpd2dq_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTPD2DQ_Vdq_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9887	2876
9888		#define emit_cvtpd2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, sreg)
9889		#define emit_cvtpd2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9890		#define emit_cvtpd2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, (base), REG_NONE, 1, (disp))
9891		#define emit_cvtpd2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9892		#define emit_cvtpd2dq_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, (base), (index), (scale), (disp))
	2877	INLINE void emit_cvttpd2dq_r128_r128(x86code **emitptr, UINT8 dreg, UINT8 sreg) { emit_op_modrm_reg(emitptr, OP_CVTTPD2DQ_Vdq_Wpd, OP_32BIT, dreg, sreg); }
	2878	INLINE void emit_cvttpd2dq_r128_m128(x86code **emitptr, UINT8 dreg, DECLARE_MEMPARAMS) { emit_op_modrm_mem(emitptr, OP_CVTTPD2DQ_Vdq_Wpd, OP_32BIT, dreg, MEMPARAMS); }
9893	2879
9894		#define emit_cvttpd2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, sreg)
9895		#define emit_cvttpd2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
9896		#define emit_cvttpd2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, (base), REG_NONE, 1, (disp))
9897		#define emit_cvttpd2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, REG_NONE, (index), (scale), (disp))
9898		#define emit_cvttpd2dq_r128_m128bisd(e, dreg, base, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, (base), (index), (scale), (disp))
	2880	#endif

src/emu/cpu/mb86233/mb86233.c
r949	r950
886	886	break;
887	887
888	888	case 0x0D:
889		GETA().u = GETARAM()[r1];
890		GETB().u = GETBRAM()[INDIRECT(r2\|2<<6,0)];
	889	GETA().u = GETARAM()[INDIRECT(r1,0)];
	890	GETB().u = GETBRAM()[INDIRECT(r2\|(2<<6),1)];
891	891	break;
892	892
893	893	case 0x0F:
r949	r950
898	898	case 0x10:
899	899	GETA().u = GETBRAM()[INDIRECT(r1,1)];
900	900	GETB().u = GETARAM()[r2];
	901
	902	case 0x11:
	903	GETA().u = GETBRAM()[INDIRECT(r1,1)];
	904	GETB().u = GETBRAM()[INDIRECT(r2\|(2<<6),0)];
901	905	break;
902	906
903	907	default:

src/emu/streams.c
r949	r950
550	550	void stream_set_sample_rate(sound_stream *stream, int sample_rate)
551	551	{
552	552	/* we will update this on the next global update */
553		if (sample_rate != stream->sample_rate && (stream->new_sample_rate == 0 \|\| sample_rate == stream->new_sample_rate))
	553	if ((stream->new_sample_rate == 0 && sample_rate != stream->sample_rate) \|\| (stream->new_sample_rate != 0 && sample_rate != stream->new_sample_rate))
554	554	stream->new_sample_rate = sample_rate;
555	555	}
556	556

src/emu/emuopts.c
r949	r950
160	160	{ NULL }
161	161	};
162	162
163		static core_options *mame_opts;
164	163
165	164
166
167	165	/***************************************************************************
168	166	CORE IMPLEMENTATION
169	167	***************************************************************************/
r949	r950
206	204	mame_options_init - create core MAME options
207	205	-------------------------------------------------*/
208	206
209		void mame_options_init(const options_entry *entries)
	207	core_options mame_options_init(const options_entry entries)
210	208	{
211	209	/* create MAME core options */
212	210	core_options *opts = options_create(memory_error);
r949	r950
220	218	if (entries != NULL)
221	219	options_add_entries(opts, entries);
222	220
223		mame_opts = opts;
224
225	221	#ifdef MESS
226		mess_options_init();
	222	mess_options_init(opts);
227	223	#endif /* MESS */
228		}
229	224
230
231
232		/*-------------------------------------------------
233		mame_options_exit - free core MAME options
234		-------------------------------------------------*/
235
236		void mame_options_exit(void)
237		{
238		if (mame_opts != NULL)
239		{
240		options_free(mame_opts);
241		mame_opts = NULL;
242		}
	225	return opts;
243	226	}
244
245
246
247		/*-------------------------------------------------
248		mame_options - accesses the options for the
249		currently running emulation
250		-------------------------------------------------*/
251
252		core_options *mame_options(void)
253		{
254		assert(mame_opts);
255		return mame_opts;
256		}

src/emu/emuopts.h
r949	r950
152	152	FUNCTION PROTOTYPES
153	153	***************************************************************************/
154	154
155		void mame_options_init(const options_entry *entries);
156		void mame_options_exit(void);
157		core_options *mame_options(void);
	155	core_options mame_options_init(const options_entry entries);
158	156
159	157	#endif /* __EMUOPTS_H__ */

src/emu/uimenu.c
r949	r950
1698	1698	int audit_result;
1699	1699
1700	1700	/* audit the game first to see if we're going to work */
1701		audit_records = audit_images(select_game_list[selected], AUDIT_VALIDATE_FAST, &audit);
	1701	audit_records = audit_images(mame_options(), select_game_list[selected], AUDIT_VALIDATE_FAST, &audit);
1702	1702	audit_result = audit_summary(select_game_list[selected], audit_records, audit, FALSE);
1703	1703	if (audit_records > 0)
1704	1704	free(audit);

src/emu/audit.c
r949	r950
22	22	FUNCTION PROTOTYPES
23	23	***************************************************************************/
24	24
25		static int audit_one_rom(const rom_entry rom, const game_driver gamedrv, UINT32 validation, audit_record *record);
26		static int audit_one_disk(const rom_entry rom, const game_driver gamedrv, UINT32 validation, audit_record *record);
	25	static int audit_one_rom(core_options options, const rom_entry rom, const game_driver gamedrv, UINT32 validation, audit_record record);
	26	static int audit_one_disk(core_options options, const rom_entry rom, const game_driver gamedrv, UINT32 validation, audit_record record);
27	27	static int rom_used_by_parent(const game_driver gamedrv, const rom_entry romentry, const game_driver **parent);
28	28
29	29
r949	r950
54	54	images for a game
55	55	-------------------------------------------------*/
56	56
57		int audit_images(const game_driver gamedrv, UINT32 validation, audit_record *audit)
	57	int audit_images(core_options options, const game_driver gamedrv, UINT32 validation, audit_record **audit)
58	58	{
59	59	const rom_entry region, rom;
60	60	audit_record *record;
r949	r950
89	89	/* audit a file */
90	90	if (ROMREGION_ISROMDATA(region))
91	91	{
92		if (audit_one_rom(rom, gamedrv, validation, record++) && (!shared \|\| allshared))
	92	if (audit_one_rom(options, rom, gamedrv, validation, record++) && (!shared \|\| allshared))
93	93	foundany = TRUE;
94	94	}
95	95
96	96	/* audit a disk */
97	97	else if (ROMREGION_ISDISKDATA(region))
98	98	{
99		if (audit_one_disk(rom, gamedrv, validation, record++) && (!shared \|\| allshared))
	99	if (audit_one_disk(options, rom, gamedrv, validation, record++) && (!shared \|\| allshared))
100	100	foundany = TRUE;
101	101	}
102	102	}
r949	r950
118	118	game
119	119	-------------------------------------------------*/
120	120
121		int audit_samples(const game_driver gamedrv, audit_record *audit)
	121	int audit_samples(core_options options, const game_driver gamedrv, audit_record **audit)
122	122	{
123	123	machine_config config;
124	124	audit_record *record;
r949	r950
173	173
174	174	/* attempt to access the file from the game driver name */
175	175	fname = astring_assemble_3(astring_alloc(), gamedrv->name, PATH_SEPARATOR, intf->samplenames[sampnum]);
176		filerr = mame_fopen(SEARCHPATH_SAMPLE, astring_c(fname), OPEN_FLAG_READ, &file);
	176	filerr = mame_fopen_options(options, SEARCHPATH_SAMPLE, astring_c(fname), OPEN_FLAG_READ, &file);
177	177
178	178	/* attempt to access the file from the shared driver name */
179	179	if (filerr != FILERR_NONE && sharedname != NULL)
180	180	{
181	181	astring_assemble_3(fname, sharedname, PATH_SEPARATOR, intf->samplenames[sampnum]);
182		filerr = mame_fopen(SEARCHPATH_SAMPLE, astring_c(fname), OPEN_FLAG_READ, &file);
	182	filerr = mame_fopen_options(options, SEARCHPATH_SAMPLE, astring_c(fname), OPEN_FLAG_READ, &file);
183	183	}
184	184	astring_free(fname);
185	185
r949	r950
309	309	audit_one_rom - validate a single ROM entry
310	310	-------------------------------------------------*/
311	311
312		static int audit_one_rom(const rom_entry rom, const game_driver gamedrv, UINT32 validation, audit_record *record)
	312	static int audit_one_rom(core_options options, const rom_entry rom, const game_driver gamedrv, UINT32 validation, audit_record record)
313	313	{
314	314	const game_driver *drv;
315	315	const rom_entry *chunk;
r949	r950
341	341	/* open the file if we can */
342	342	fname = astring_assemble_3(astring_alloc(), drv->name, PATH_SEPARATOR, ROM_GETNAME(rom));
343	343	if (has_crc)
344		filerr = mame_fopen_crc(SEARCHPATH_ROM, astring_c(fname), crc, OPEN_FLAG_READ, &file);
	344	filerr = mame_fopen_crc_options(options, SEARCHPATH_ROM, astring_c(fname), crc, OPEN_FLAG_READ, &file);
345	345	else
346		filerr = mame_fopen(SEARCHPATH_ROM, astring_c(fname), OPEN_FLAG_READ, &file);
	346	filerr = mame_fopen_options(options, SEARCHPATH_ROM, astring_c(fname), OPEN_FLAG_READ, &file);
347	347	astring_free(fname);
348	348
349	349	/* if we got it, extract the hash and length */
r949	r950
411	411	audit_one_disk - validate a single disk entry
412	412	-------------------------------------------------*/
413	413
414		static int audit_one_disk(const rom_entry rom, const game_driver gamedrv, UINT32 validation, audit_record *record)
	414	static int audit_one_disk(core_options options, const rom_entry rom, const game_driver gamedrv, UINT32 validation, audit_record record)
415	415	{
416	416	mame_file *source_file;
417	417	chd_file *source;
r949	r950
423	423	record->exphash = ROM_GETHASHDATA(rom);
424	424
425	425	/* open the disk */
426		err = open_disk_image(gamedrv, rom, &source_file, &source);
	426	err = open_disk_image_options(options, gamedrv, rom, &source_file, &source);
427	427
428	428	/* if we failed, report the error */
429	429	if (err != CHDERR_NONE)

src/emu/video.c
r949	r950
1521	1521	/* if we're throttling and autoframeskip is on, adjust */
1522	1522	if (effective_throttle() && effective_autoframeskip() && global.frameskip_counter == 0)
1523	1523	{
	1524	float speed = global.speed * 0.01;
	1525
1524	1526	/* if we're too fast, attempt to increase the frameskip */
1525		if (global.speed_percent >= 0.995)
	1527	if (global.speed_percent >= 0.995 * speed)
1526	1528	{
1527	1529	/* but only after 3 consecutive frames where we are too fast */
1528	1530	if (++global.frameskipadjust >= 3)
r949	r950
1537	1539	else
1538	1540	{
1539	1541	/* if below 80% speed, be more aggressive */
1540		if (global.speed_percent < 0.80)
1541		global.frameskipadjust -= (0.90 - global.speed_percent) / 0.05;
	1542	if (global.speed_percent < 0.80 * speed)
	1543	global.frameskipadjust -= (0.90 * speed - global.speed_percent) / 0.05;
1542	1544
1543	1545	/* if we're close, only force it up to frameskip 8 */
1544	1546	else if (global.frameskip_level < 8)

src/emu/memory.c
r949	r950
1420	1420	const address_map *map;
1421	1421
1422	1422	/* install the handlers, using the original, unadjusted memory map */
1423		if (space->map)
	1423	if (space->map != NULL)
1424	1424	{
1425	1425	/* first find the end */
1426	1426	for (map = space->map; !IS_AMENTRY_END(map); map++) ;
r949	r950
1431	1431	{
1432	1432	int ismatchmask = ((map->flags & AM_FLAGS_MATCH_MASK) != 0);
1433	1433	int isfixed = (map->memory != NULL) \|\| (map->share != 0);
1434		if (map->read.handler)
	1434	if (map->read.handler != NULL)
1435	1435	install_mem_handler(space, 0, space->dbits, ismatchmask, map->start, map->end, map->mask, map->mirror, map->read.handler, isfixed, map->read_name);
1436		if (map->write.handler)
	1436	if (map->write.handler != NULL)
1437	1437	install_mem_handler(space, 1, space->dbits, ismatchmask, map->start, map->end, map->mask, map->mirror, map->write.handler, isfixed, map->write_name);
1438	1438	}
1439	1439	}
r949	r950
1448	1448
1449	1449	static void install_mem_handler(addrspace_data space, int iswrite, int databits, int ismatchmask, offs_t start, offs_t end, offs_t mask, offs_t mirror, genf handler, int isfixed, const char *handler_name)
1450	1450	{
1451		offs_t lmirrorbit[LEVEL1_BITS], lmirrorbits, hmirrorbit[LEVEL2_BITS], hmirrorbits, lmirrorcount, hmirrorcount;
	1451	offs_t lmirrorbit[LEVEL2_BITS], lmirrorbits, hmirrorbit[32 - LEVEL2_BITS], hmirrorbits, lmirrorcount, hmirrorcount;
1452	1452	table_data *tabledata = iswrite ? &space->write : &space->read;
1453	1453	UINT8 idx, prev_entry = STATIC_INVALID;
1454	1454	int cur_index, prev_index = 0;
1455		~~offs_~~t ori~~ginal_~~mask = mask;
	1455	int ismasked = (mask != 0);
1456	1456	int i;
1457	1457
1458	1458	/* sanity check */
r949	r950
1499	1499	/* assign banks for RAM/ROM areas */
1500	1500	if (HANDLER_IS_RAM(handler))
1501	1501	{
1502		handler = (genf *)assign_dynamic_bank(space->cpunum, space->spacenum, start, end, mirror, isfixed, ori~~ginal_~~mask ~~!= 0~~);
	1502	handler = (genf *)assign_dynamic_bank(space->cpunum, space->spacenum, start, end, mirror, isfixed, ismasked);
1503	1503	if (!bank_ptr[HANDLER_TO_BANK(handler)])
1504	1504	bank_ptr[HANDLER_TO_BANK(handler)] = memory_find_base(space->cpunum, space->spacenum, iswrite, start);
1505	1505	}
r949	r950
2033	2033	/* make a first pass over the memory map and track blocks with hardcoded pointers */
2034	2034	/* we do this to make sure they are found by memory_find_base first */
2035	2035	for (map = space->adjmap; map && !IS_AMENTRY_END(map); map++)
2036		if (!IS_AMENTRY_EXTENDED(map) && map->memory)
	2036	if (!IS_AMENTRY_EXTENDED(map) && map->memory != NULL)
2037	2037	{
2038	2038	if (!IS_AMENTRY_MATCH_MASK(map))
2039	2039	allocate_memory_block(cpunum, spacenum, map->start, map->end, map->memory);
r949	r950
2070	2070
2071	2071	/* scan for unmapped blocks in the adjusted map */
2072	2072	for (map = space->adjmap; map && !IS_AMENTRY_END(map); map++)
2073		if (!IS_AMENTRY_EXTENDED(map) && !map->memory && map != unassigned && amentry_needs_backing_store(cpunum, spacenum, map))
	2073	if (!IS_AMENTRY_EXTENDED(map) && map->memory == NULL && map != unassigned && amentry_needs_backing_store(cpunum, spacenum, map))
2074	2074	{
2075	2075	offs_t blockstart, blockend;
2076	2076
r949	r950
2179	2179	if (!IS_AMENTRY_EXTENDED(map))
2180	2180	{
2181	2181	/* if we haven't assigned this block yet, do it against the last block */
2182		if (!map->memory)
	2182	if (map->memory == NULL)
2183	2183	{
2184	2184	/* inherit shared pointers first */
2185	2185	if (map->share && shared_ptr[map->share])
r949	r950
2211	2211	}
2212	2212
2213	2213	/* if we're the first match on a shared pointer, assign it now */
2214		if (map->memory && map->share && !shared_ptr[map->share])
	2214	if (map->memory != NULL && map->share && !shared_ptr[map->share])
2215	2215	shared_ptr[map->share] = map->memory;
2216	2216
2217	2217	/* keep track of the first unassigned entry */
2218		if (!map->memory && !unassigned && amentry_needs_backing_store(space->cpunum, space->spacenum, map))
	2218	if (map->memory == NULL && !unassigned && amentry_needs_backing_store(space->cpunum, space->spacenum, map))
2219	2219	unassigned = map;
2220	2220	}
2221	2221

src/emu/audit.h
r949	r950
82	82	FUNCTION PROTOTYPES
83	83	***************************************************************************/
84	84
85		int audit_images(const game_driver gamedrv, UINT32 validation, audit_record *audit);
86		int audit_samples(const game_driver gamedrv, audit_record *audit);
	85	int audit_images(core_options options, const game_driver gamedrv, UINT32 validation, audit_record **audit);
	86	int audit_samples(core_options options, const game_driver gamedrv, audit_record **audit);
87	87	int audit_summary(const game_driver gamedrv, int count, const audit_record records, int output);
88	88
89	89

src/emu/mame.c
r949	r950
178	178	/* the active machine */
179	179	running_machine *Machine;
180	180
	181	/* the current options */
	182	static core_options *mame_opts;
	183
181	184	/* started empty? */
182	185	static UINT8 started_empty;
183	186
r949	r950
244	247
245	248	extern int mame_validitychecks(const game_driver *driver);
246	249
247		static int parse_ini_file(const char *name);
	250	static int parse_ini_file(core_options options, const char name);
248	251
249	252	static running_machine create_machine(const game_driver driver);
250	253	static void reset_machine(running_machine *machine);
r949	r950
269	272	mame_execute - run the core emulation
270	273	-------------------------------------------------*/
271	274
272		int mame_execute(void)
	275	int mame_execute(core_options *options)
273	276	{
274	277	int exit_pending = FALSE;
275	278	int error = MAMERR_NONE;
r949	r950
285	288	callback_item *cb;
286	289	astring *gamename;
287	290
	291	/* specify the mame_options */
	292	mame_opts = options;
	293
288	294	/* convert the specified gamename to a driver */
289	295	gamename = core_filename_extract_base(astring_alloc(), options_get_string(mame_options(), OPTION_GAMENAME), TRUE);
290	296	driver = driver_get_name(astring_c(gamename));
r949	r950
421	427
422	428	/* destroy the machine */
423	429	destroy_machine(machine);
	430
	431	/* reset the options */
	432	mame_opts = NULL;
424	433	}
425	434
426	435	/* return an error */
r949	r950
429	438
430	439
431	440	/*-------------------------------------------------
	441	mame_options - accesses the options for the
	442	currently running emulation
	443	-------------------------------------------------*/
	444
	445	core_options *mame_options(void)
	446	{
	447	assert(mame_opts != NULL);
	448	return mame_opts;
	449	}
	450
	451
	452
	453	/*-------------------------------------------------
432	454	mame_get_phase - return the current program
433	455	phase
434	456	-------------------------------------------------*/
r949	r950
972	994	va_list argptr;
973	995
974	996	/* if we're not verbose, skip it */
975		if (!options_get_bool(mame_options(), OPTION_VERBOSE))
	997	if (mame_opts == NULL \|\| !options_get_bool(mame_options(), OPTION_VERBOSE))
976	998	return;
977	999
978	1000	/* by default, we go to stdout */
r949	r950
1232	1254	{
1233	1255	/* parse the INI file defined by the platform (e.g., "mame.ini") */
1234	1256	/* we do this twice so that the first file can change the INI path */
1235		parse_ini_file(CONFIGNAME);
1236		parse_ini_file(CONFIGNAME);
	1257	parse_ini_file(options, CONFIGNAME);
	1258	parse_ini_file(options, CONFIGNAME);
1237	1259
1238	1260	/* debug builds: parse "debug.ini" as well */
1239	1261	#ifdef MAME_DEBUG
1240		parse_ini_file("debug");
	1262	parse_ini_file(options, "debug");
1241	1263	#endif
1242	1264
1243	1265	/* if we have a valid game driver, parse game-specific INI files */
r949	r950
1253	1275
1254	1276	/* parse "vector.ini" for vector games */
1255	1277	if (drv.video_attributes & VIDEO_TYPE_VECTOR)
1256		parse_ini_file("vector");
	1278	parse_ini_file(options, "vector");
1257	1279
1258	1280	/* next parse "source/<sourcefile>.ini"; if that doesn't exist, try <sourcefile>.ini */
1259	1281	sourcename = core_filename_extract_base(astring_alloc(), driver->source_file, TRUE);
1260	1282	astring_insc(sourcename, 0, "source" PATH_SEPARATOR);
1261		if (!parse_ini_file(astring_c(sourcename)))
	1283	if (!parse_ini_file(options, astring_c(sourcename)))
1262	1284	{
1263	1285	core_filename_extract_base(sourcename, driver->source_file, TRUE);
1264		parse_ini_file(astring_c(sourcename));
	1286	parse_ini_file(options, astring_c(sourcename));
1265	1287	}
1266	1288	astring_free(sourcename);
1267	1289
1268	1290	/* then parent the grandparent, parent, and game-specific INIs */
1269	1291	if (gparent != NULL)
1270		parse_ini_file(gparent->name);
	1292	parse_ini_file(options, gparent->name);
1271	1293	if (parent != NULL)
1272		parse_ini_file(parent->name);
1273		parse_ini_file(driver->name);
	1294	parse_ini_file(options, parent->name);
	1295	parse_ini_file(options, driver->name);
1274	1296	}
1275	1297	}
1276	1298
r949	r950
1279	1301	parse_ini_file - parse a single INI file
1280	1302	-------------------------------------------------*/
1281	1303
1282		static int parse_ini_file(const char *name)
	1304	static int parse_ini_file(core_options options, const char name)
1283	1305	{
1284	1306	file_error filerr;
1285	1307	mame_file *file;
1286	1308	astring *fname;
1287	1309
1288	1310	/* don't parse if it has been disabled */
1289		if (!options_get_bool(~~mame_~~options(), OPTION_READCONFIG))
	1311	if (!options_get_bool(options, OPTION_READCONFIG))
1290	1312	return FALSE;
1291	1313
1292	1314	/* open the file; if we fail, that's ok */
1293	1315	fname = astring_assemble_2(astring_alloc(), name, ".ini");
1294		filerr = mame_fopen(SEARCHPATH_INI, astring_c(fname), OPEN_FLAG_READ, &file);
	1316	filerr = mame_fopen_options(options, SEARCHPATH_INI, astring_c(fname), OPEN_FLAG_READ, &file);
1295	1317	astring_free(fname);
1296	1318	if (filerr != FILERR_NONE)
1297	1319	return FALSE;
1298	1320
1299	1321	/* parse the file and close it */
1300	1322	mame_printf_verbose("Parsing %s.ini\n", name);
1301		options_parse_ini_file(~~mame_~~options(), mame_core_file(file), OPTION_PRIORITY_INI);
	1323	options_parse_ini_file(options, mame_core_file(file), OPTION_PRIORITY_INI);
1302	1324	mame_fclose(file);
1303	1325	return TRUE;
1304	1326	}

src/emu/mame.h
r949	r950
250	250
251	251	/* ----- core system management ----- */
252	252
253		/* execute as configured by the OPTION_GAMENAME option */
254		int mame_execute(void);
	253	/* execute as configured by the OPTION_GAMENAME option on the specified options */
	254	int mame_execute(core_options *options);
255	255
	256	/* accesses the core_options for the currently running emulation */
	257	core_options *mame_options(void);
	258
256	259	/* return the current phase */
257	260	int mame_get_phase(running_machine *machine);
258	261

src/emu/rendlay.c
r949	r950
692	692
693	693	/* draw line */
694	694	for (x = minx; x < maxx; x++)
695		{
696		UINT32 *d = BITMAP_ADDR32(dest, 0, x);
697		int step = (x - minx) * ratio;
	695	if (x >= 0 && x < dest->width)
	696	{
	697	UINT32 *d = BITMAP_ADDR32(dest, 0, x);
	698	int step = (x - minx) * ratio;
698	699
699		for (y = maxy - width - step; y < maxy - step; y++)
700		{
701		d[y * dest->rowpixels] = color;
	700	for (y = maxy - width - step; y < maxy - step; y++)
	701	if (y >= 0 && y < dest->height)
	702	{
	703	d[y * dest->rowpixels] = color;
	704	}
702	705	}
703		}
704	706	}
705	707
706	708
r949	r950
720	722
721	723	/* draw line */
722	724	for (x = minx; x < maxx; x++)
723		{
724		UINT32 *d = BITMAP_ADDR32(dest, 0, x);
725		int step = (x - minx) * ratio;
	725	if (x >= 0 && x < dest->width)
	726	{
	727	UINT32 *d = BITMAP_ADDR32(dest, 0, x);
	728	int step = (x - minx) * ratio;
726	729
727		for (y = miny + step; y < miny + step + width; y++)
728		{
729		d[y * dest->rowpixels] = color;
	730	for (y = miny + step; y < miny + step + width; y++)
	731	if (y >= 0 && y < dest->height)
	732	{
	733	d[y * dest->rowpixels] = color;
	734	}
730	735	}
731		}
732	736	}
733	737
734	738

src/emu/sound/tms5220r.c
r949	r950
99	99	0x00, 0x00, 0x00
100	100	};
101	101
102		/* interpolation coefficients */
	102	/* interpolation coefficients (in rightshifts, as in actual chip) */
103	103
104	104	static char interp_coeff[8] = {
105		8, 8, 8, 4, 4, 2, 2, 1
	105	3, 3, 3, 2, 2, 1, 1, 0
106	106	};
107	107

src/emu/sound/fm.c
r949	r950
1116	1116	}
1117	1117	}
1118	1118
1119		INLINE void advance_eg_channel(FM_OPN OPN, FM_SLOT SLOT)
	1119	/* changed from INLINE to static here to work around gcc 4.2.1 codegen bug */
	1120	static void advance_eg_channel(FM_OPN OPN, FM_SLOT SLOT)
1120	1121	{
1121	1122	unsigned int out;
1122	1123	unsigned int swap_flag = 0;

src/emu/sound/tms5220.c
r949	r950
128	128	an additional opcode (to select the data rate).
129	129	*/
130	130	tms5220_variant variant;
	131	/* The TMS52xx has two different ways of providing output data: the
	132	analog speaker pin (which was usually used) and the Digital I/O pin.
	133	The internal DAC used to feed the analog pin is only 8 bits, while the
	134	digital pin gives full 12? bit resolution to the output data.
	135	*/
	136	UINT8 digital_select;
131	137	};
132	138
133	139
r949	r950
195	201	state_save_register_item("tms5220", index, tms->schedule_dummy_read);
196	202	state_save_register_item("tms5220", index, tms->data_register);
197	203	state_save_register_item("tms5220", index, tms->RDB_flag);
	204	state_save_register_item("tms5220", index, tms->digital_select);
198	205
199	206	return tms;
200	207	}
r949	r950
625	632	/mame_printf_debug("\n");/
626	633
627	634	interp_period = tms->sample_count / 25;
628		tms->current_energy += (tms->target_energy - tms->current_energy) / interp_coeff[interp_period];
	635	tms->current_energy += ((tms->target_energy - tms->current_energy) >> interp_coeff[interp_period]);
629	636	if (tms->old_pitch != 0)
630		tms->current_pitch += (tms->target_pitch - tms->current_pitch) / interp_coeff[interp_period];
	637	tms->current_pitch += ((tms->target_pitch - tms->current_pitch) >> interp_coeff[interp_period]);
631	638
632	639	/mame_printf_debug("** Energy = %d\n",tms->current_energy);*/
633	640
634	641	for (i = 0; i < 10; i++)
635	642	{
636		tms->current_k[i] += (tms->target_k[i] - tms->current_k[i]) / interp_coeff[interp_period];
	643	tms->current_k[i] += ((tms->target_k[i] - tms->current_k[i]) >> interp_coeff[interp_period]);
637	644	}
638	645	}
639	646
r949	r950
666	673
667	674	buffer[buf_count] = clip_and_wrap(lattice_filter(tms)); /* execute lattice filter and clipping/wrapping */
668	675
	676	if (tms->digital_select == 0) /* if digital is NOT selected... */
	677	buffer[buf_count] &= 0xff00; /* mask out all but the 8 dac bits */
	678
669	679	/* Update all counts */
670	680
671	681	size--;

src/emu/profiler.c
r949	r950
149	149	"Idle ",
150	150	};
151	151	static int showdelay[PROFILER_TOTAL];
152		static char buf[30*20];
	152	static char buf[50*40];
153	153	char *bufptr = buf;
154	154
155	155

src/emu/drawgfx.c
r949	r950
240	240
241	241	/* copy the layout */
242	242	gfx->layout = *gl;
243		if (gl->extxoffs)
	243	if (gl->extxoffs != NULL)
244	244	{
245	245	UINT32 buffer = malloc_or_die(sizeof(buffer[0]) gl->width);
246	246	memcpy(buffer, gl->extxoffs, sizeof(gfx->layout.extxoffs[0]) * gl->width);
247	247	gfx->layout.extxoffs = buffer;
248	248	}
249		if (gl->extyoffs)
	249	if (gl->extyoffs != NULL)
250	250	{
251	251	UINT32 buffer = malloc_or_die(sizeof(buffer[0]) gl->height);
252	252	memcpy(buffer, gl->extyoffs, sizeof(gfx->layout.extyoffs[0]) * gl->height);
r949	r950
257	257	gfx->width = gl->width;
258	258	gfx->height = gl->height;
259	259	gfx->total_elements = gl->total;
	260	gfx->color_base = 0;
260	261	gfx->color_depth = 1 << gl->planes;
261	262	gfx->color_granularity = 1 << gl->planes;
262		if (gfx->color_~~granulari~~ty <= 32)
	263	if (gfx->color_depth <= 32)
263	264	gfx->pen_usage = malloc_or_die(gfx->total_elements * sizeof(*gfx->pen_usage));
264	265
265	266	/* raw graphics case */

src/emu/fileio.c
r949	r950
143	143
144	144	file_error mame_fopen_crc(const char searchpath, const char filename, UINT32 crc, UINT32 openflags, mame_file **file)
145	145	{
146		return fopen_in~~ternal~~(mame_options(), searchpath, filename, crc, openflags ~~\| OPEN_FLAG_HAS_CRC~~, file);
	146	return mame_fopen_crc_options(mame_options(), searchpath, filename, crc, openflags, file);
147	147	}
148	148
149	149
r949	r950
159	159
160	160
161	161	/*-------------------------------------------------
	162	mame_fopen_crc_options - open a file by name
	163	or CRC and return an error code
	164	-------------------------------------------------*/
	165
	166	file_error mame_fopen_crc_options(core_options opts, const char searchpath, const char filename, UINT32 crc, UINT32 openflags, mame_file *file)
	167	{
	168	return fopen_internal(opts, searchpath, filename, crc, openflags \| OPEN_FLAG_HAS_CRC, file);
	169	}
	170
	171
	172	/*-------------------------------------------------
162	173	mame_fopen_ram - open a "file" which is
163	174	actually just an array of data in RAM
164	175	-------------------------------------------------*/
r949	r950
568	579	static int mame_vfprintf(mame_file file, const char fmt, va_list va)
569	580	{
570	581	/* write the data if we can */
571		if (file->file != NULL)
572		{
573		char buf[1024];
574		vsnprintf(buf, sizeof(buf), fmt, va);
575		return core_fputs(file->file, buf);
576		}
577		return 0;
	582	return (file->file != NULL) ? core_vfprintf(file->file, fmt, va) : 0;
578	583	}
579	584
580	585

src/emu/fileio.h
r949	r950
89	89	/* open a file in the given search path with the specified filename, using the specified options */
90	90	file_error mame_fopen_options(core_options opts, const char searchpath, const char filename, UINT32 openflags, mame_file *file);
91	91
	92	/* open a file in the given search path with the specified filename or a matching CRC, using the specified options */
	93	file_error mame_fopen_crc_options(core_options opts, const char searchpath, const char filename, UINT32 crc, UINT32 openflags, mame_file *file);
	94
92	95	/* open a "file" which is actually data in RAM */
93	96	file_error mame_fopen_ram(const void data, UINT32 length, UINT32 openflags, mame_file *file);
94	97

src/emu/clifront.c
r949	r950
46	46	FUNCTION PROTOTYPES
47	47	***************************************************************************/
48	48
49		static int execute_simple_commands(const char *exename);
50		static int execute_commands(const char exename, const game_driver driver);
	49	static int execute_simple_commands(core_options options, const char exename);
	50	static int execute_commands(core_options options, const char exename, const game_driver *driver);
51	51	static void display_help(void);
52	52
53	53	/* informational functions */
54		static int info_verifyroms(const char *gamename);
55		static int info_verifysamples(const char *gamename);
56		static int info_romident(const char *gamename);
	54	static int info_verifyroms(core_options options, const char gamename);
	55	static int info_verifysamples(core_options options, const char gamename);
	56	static int info_romident(core_options options, const char gamename);
57	57
58	58	/* utilities */
59	59	static void romident(const char filename, romident_status status);
r949	r950
112	112
113	113	int cli_execute(int argc, char *argv, const options_entry osd_options)
114	114	{
	115	core_options *options;
115	116	astring *gamename = astring_alloc();
116	117	astring *exename = astring_alloc();
117	118	const game_driver *driver;
118	119	int result;
119	120
120	121	/* initialize the options manager and add the CLI-specific options */
121		mame_options_init(osd_options);
122		options_add_entries(mame_options(), cli_options);
	122	options = mame_options_init(osd_options);
	123	options_add_entries(options, cli_options);
123	124
124	125	/* parse the command line first; if we fail here, we're screwed */
125		if (options_parse_command_line(~~mame_~~options(), argc, argv, OPTION_PRIORITY_CMDLINE))
	126	if (options_parse_command_line(options, argc, argv, OPTION_PRIORITY_CMDLINE))
126	127	{
127	128	result = MAMERR_INVALID_CONFIG;
128	129	goto error;
r949	r950
130	131
131	132	/* parse the simple commmands before we go any further */
132	133	core_filename_extract_base(exename, argv[0], TRUE);
133		result = execute_simple_commands(astring_c(exename));
	134	result = execute_simple_commands(options, astring_c(exename));
134	135	if (result != -1)
135	136	goto error;
136	137
137	138	/* find out what game we might be referring to */
138		core_filename_extract_base(gamename, options_get_string(~~mame_~~options(), OPTION_GAMENAME), TRUE);
	139	core_filename_extract_base(gamename, options_get_string(options, OPTION_GAMENAME), TRUE);
139	140	driver = driver_get_name(astring_c(gamename));
140	141
141	142	/* execute any commands specified */
142		result = execute_commands(astring_c(exename), driver);
	143	result = execute_commands(options, astring_c(exename), driver);
143	144	if (result != -1)
144	145	goto error;
145	146
r949	r950
165	166	}
166	167
167	168	/* run the game */
168		result = mame_execute();
	169	result = mame_execute(options);
169	170
170	171	error:
171	172	/* free our options and exit */
172		~~mame_~~options_e~~xit~~();
	173	options_free(options);
173	174	astring_free(gamename);
174	175	astring_free(exename);
175	176	return result;
r949	r950
192	193	commands that don't require any context
193	194	-------------------------------------------------*/
194	195
195		static int execute_simple_commands(const char *exename)
	196	static int execute_simple_commands(core_options options, const char exename)
196	197	{
197	198	/* help? */
198		if (options_get_bool(~~mame_~~options(), CLIOPTION_HELP))
	199	if (options_get_bool(options, CLIOPTION_HELP))
199	200	{
200	201	display_help();
201	202	return MAMERR_NONE;
202	203	}
203	204
204	205	/* showusage? */
205		if (options_get_bool(~~mame_~~options(), CLIOPTION_SHOWUSAGE))
	206	if (options_get_bool(options, CLIOPTION_SHOWUSAGE))
206	207	{
207	208	mame_printf_info("Usage: %s [%s] [options]\n\nOptions:\n", exename, GAMENOUN);
208		options_output_help(~~mame_~~options(), help_output);
	209	options_output_help(options, help_output);
209	210	return MAMERR_NONE;
210	211	}
211	212
212	213	/* validate? */
213		if (options_get_bool(~~mame_~~options(), CLIOPTION_VALIDATE))
	214	if (options_get_bool(options, CLIOPTION_VALIDATE))
214	215	{
215	216	extern int mame_validitychecks(const game_driver *driver);
216	217	return mame_validitychecks(NULL);
r949	r950
225	226	commands
226	227	-------------------------------------------------*/
227	228
228		static int execute_commands(const char exename, const game_driver driver)
	229	static int execute_commands(core_options options, const char exename, const game_driver *driver)
229	230	{
230	231	static const struct
231	232	{
232	233	const char *option;
233		int (function)(const char gamename);
	234	int (function)(core_options options, const char *gamename);
234	235	} info_commands[] =
235	236	{
236	237	{ CLIOPTION_LISTXML, cli_info_listxml },
r949	r950
250	251	int i;
251	252
252	253	/* createconfig? */
253		if (options_get_bool(~~mame_~~options(), CLIOPTION_CREATECONFIG))
	254	if (options_get_bool(options, CLIOPTION_CREATECONFIG))
254	255	{
255	256	file_error filerr;
256	257	mame_file *file;
257	258
258	259	/* parse any relevant INI files before proceeding */
259		mame_parse_ini_files(~~mame_~~options(), driver);
	260	mame_parse_ini_files(options, driver);
260	261
261	262	/* make the output filename */
262	263	filerr = mame_fopen(NULL, CONFIGNAME ".ini", OPEN_FLAG_WRITE \| OPEN_FLAG_CREATE \| OPEN_FLAG_CREATE_PATHS, &file);
r949	r950
269	270	}
270	271
271	272	/* output the configuration and exit cleanly */
272		options_output_ini_file(~~mame_~~options(), mame_core_file(file));
	273	options_output_ini_file(options, mame_core_file(file));
273	274	mame_fclose(file);
274	275	return MAMERR_NONE;
275	276	}
276	277
277	278	/* showconfig? */
278		if (options_get_bool(~~mame_~~options(), CLIOPTION_SHOWCONFIG))
	279	if (options_get_bool(options, CLIOPTION_SHOWCONFIG))
279	280	{
280	281	/* parse any relevant INI files before proceeding */
281		mame_parse_ini_files(mame_options(), driver);
282		options_output_ini_stdfile(mame_options(), stdout);
	282	mame_parse_ini_files(options, driver);
	283	options_output_ini_stdfile(options, stdout);
283	284	return MAMERR_NONE;
284	285	}
285	286
286	287	/* informational commands? */
287	288	for (i = 0; i < ARRAY_LENGTH(info_commands); i++)
288		if (options_get_bool(~~mame_~~options(), info_commands[i].option))
	289	if (options_get_bool(options, info_commands[i].option))
289	290	{
290		const char *gamename = options_get_string(~~mame_~~options(), OPTION_GAMENAME);
	291	const char *gamename = options_get_string(options, OPTION_GAMENAME);
291	292
292	293	/* parse any relevant INI files before proceeding */
293		mame_parse_ini_files(mame_options(), driver);
294		return (info_commands[i].function)((gamename[0] == 0) ? "" : gamename);
	294	mame_parse_ini_files(options, driver);
	295	return (info_commands[i].function)(options, (gamename[0] == 0) ? "" : gamename);
295	296	}
296	297
297	298	return -1;
r949	r950
330	331	or more games
331	332	-------------------------------------------------*/
332	333
333		int cli_info_listxml(const char *gamename)
	334	int cli_info_listxml(core_options options, const char gamename)
334	335	{
335	336	/* since print_mame_xml expands the machine driver, we need to set things up */
336	337	init_resource_tracking();
r949	r950
350	351	of one or more games
351	352	-------------------------------------------------*/
352	353
353		int cli_info_listfull(const char *gamename)
	354	int cli_info_listfull(core_options options, const char gamename)
354	355	{
355	356	int drvindex, count = 0;
356	357
r949	r950
377	378	filename of one or more games
378	379	-------------------------------------------------*/
379	380
380		int cli_info_listsource(const char *gamename)
	381	int cli_info_listsource(core_options options, const char gamename)
381	382	{
382	383	astring *filename = astring_alloc();
383	384	int drvindex, count = 0;
r949	r950
402	403	filename of one or more games
403	404	-------------------------------------------------*/
404	405
405		int cli_info_listclones(const char *gamename)
	406	int cli_info_listclones(core_options options, const char gamename)
406	407	{
407	408	int drvindex, count = 0;
408	409
r949	r950
435	436	all ROMs referenced by MAME
436	437	-------------------------------------------------*/
437	438
438		int cli_info_listcrc(const char *gamename)
	439	int cli_info_listcrc(core_options options, const char gamename)
439	440	{
440	441	int drvindex, count = 0;
441	442
r949	r950
469	470	referenced by a given game or set of games
470	471	-------------------------------------------------*/
471	472
472		int cli_info_listroms(const char *gamename)
	473	int cli_info_listroms(core_options options, const char gamename)
473	474	{
474	475	int drvindex, count = 0;
475	476
r949	r950
539	540	referenced by a given game or set of games
540	541	-------------------------------------------------*/
541	542
542		int cli_info_listsamples(const char *gamename)
	543	int cli_info_listsamples(core_options options, const char gamename)
543	544	{
544	545	int count = 0;
545	546
r949	r950
592	593	one or more games
593	594	-------------------------------------------------*/
594	595
595		static int info_verifyroms(const char *gamename)
	596	static int info_verifyroms(core_options options, const char gamename)
596	597	{
597	598	int correct = 0;
598	599	int incorrect = 0;
r949	r950
608	609	int res;
609	610
610	611	/* audit the ROMs in this set */
611		audit_records = audit_images(drivers[drvindex], AUDIT_VALIDATE_FAST, &audit);
	612	audit_records = audit_images(options, drivers[drvindex], AUDIT_VALIDATE_FAST, &audit);
612	613	res = audit_summary(drivers[drvindex], audit_records, audit, TRUE);
613	614	if (audit_records > 0)
614	615	free(audit);
r949	r950
676	677	one or more games
677	678	-------------------------------------------------*/
678	679
679		static int info_verifysamples(const char *gamename)
	680	static int info_verifysamples(core_options options, const char gamename)
680	681	{
681	682	int correct = 0;
682	683	int incorrect = 0;
r949	r950
692	693	int res;
693	694
694	695	/* audit the samples in this set */
695		audit_records = audit_samples(drivers[drvindex], &audit);
	696	audit_records = audit_samples(options, drivers[drvindex], &audit);
696	697	res = audit_summary(drivers[drvindex], audit_records, audit, TRUE);
697	698	if (audit_records > 0)
698	699	free(audit);
r949	r950
753	754	matches in our internal database
754	755	-------------------------------------------------*/
755	756
756		static int info_romident(const char *gamename)
	757	static int info_romident(core_options options, const char gamename)
757	758	{
758	759	romident_status status;
759	760

src/emu/emupal.c
r949	r950
383	383	ctable->raw = auto_malloc(ctable->entries * sizeof(*ctable->raw));
384	384	for (index = 0; index < ctable->entries; index++)
385	385	ctable->raw[index] = index % ctable->palentries;
	386	state_save_register_global_pointer(ctable->raw, ctable->entries);
386	387
387	388	/* allocate the palette */
388	389	ctable->palette = auto_malloc(ctable->palentries * sizeof(*ctable->palette));
389	390	for (index = 0; index < ctable->palentries; index++)
390		ctable->palette[index] = RGB_BLACK;
	391	ctable->palette[index] = MAKE_ARGB(0x80,0xff,0xff,0xff);
	392	state_save_register_global_pointer(ctable->palette, ctable->palentries);
391	393
392	394	return ctable;
393	395	}
r949	r950
435	437	/* ensure values are within range */
436	438	assert(entry < ctable->palentries);
437	439
	440	/* alpha doesn't matter */
	441	color &= 0xffffff;
	442
438	443	/* update if it has changed */
439	444	if (ctable->palette[entry] != color)
440	445	{

src/emu/clifront.h
r949	r950
45	45	int cli_execute(int argc, char *argv, const options_entry osd_options);
46	46
47	47	/* informational functions */
48		int cli_info_listxml(const char *gamename);
49		int cli_info_listfull(const char *gamename);
50		int cli_info_listsource(const char *gamename);
51		int cli_info_listclones(const char *gamename);
52		int cli_info_listcrc(const char *gamename);
53		int cli_info_listroms(const char *gamename);
54		int cli_info_listsamples(const char *gamename);
	48	int cli_info_listxml(core_options options, const char gamename);
	49	int cli_info_listfull(core_options options, const char gamename);
	50	int cli_info_listsource(core_options options, const char gamename);
	51	int cli_info_listclones(core_options options, const char gamename);
	52	int cli_info_listcrc(core_options options, const char gamename);
	53	int cli_info_listroms(core_options options, const char gamename);
	54	int cli_info_listsamples(core_options options, const char gamename);
55	55
56	56	#endif /* __CLIFRONT_H__ */

src/emu/romload.c
r949	r950
63	63	{
64	64	open_chd *curdisk;
65	65	for (curdisk = chd_list; curdisk != NULL && diskindex-- != 0; curdisk = curdisk->next) ;
66		return (curdisk->diffchd != NULL) ? curdisk->diffchd : curdisk->origchd;
	66	if (curdisk != NULL)
	67	return (curdisk->diffchd != NULL) ? curdisk->diffchd : curdisk->origchd;
	68	return NULL;
67	69	}
68	70
69	71
r949	r950
816	818
817	819	chd_error open_disk_image(const game_driver gamedrv, const rom_entry romp, mame_file image_file, chd_file image_chd)
818	820	{
819		const game_driver *drv;
	821	return open_disk_image_options(mame_options(), gamedrv, romp, image_file, image_chd);
	822	}
	823
	824
	825	/*-------------------------------------------------
	826	open_disk_image_options - open a DISK image, searching
	827	up the parent and loading by checksum
	828	-------------------------------------------------*/
	829
	830	chd_error open_disk_image_options(core_options options, const game_driver gamedrv, const rom_entry romp, mame_file image_file, chd_file *image_chd)
	831	{
	832	const game_driver drv, searchdrv;
820	833	const rom_entry region, rom;
821		astring *fname;
822	834	file_error filerr;
823	835	chd_error err;
824	836
825	837	*image_file = NULL;
826	838	*image_chd = NULL;
827	839
828		/* attempt to open the properly named file */
829		fname = astring_assemble_4(astring_alloc(), gamedrv->name, PATH_SEPARATOR, ROM_GETNAME(romp), ".chd");
830		filerr = mame_fopen(SEARCHPATH_IMAGE, astring_c(fname), OPEN_FLAG_READ \| OPEN_FLAG_WRITE, image_file);
831		astring_free(fname);
	840	/* attempt to open the properly named file, scanning up through parent directories */
	841	filerr = FILERR_NOT_FOUND;
	842	for (searchdrv = gamedrv; searchdrv != NULL && filerr != FILERR_NONE; searchdrv = driver_get_clone(searchdrv))
	843	{
	844	astring *fname = astring_assemble_4(astring_alloc(), searchdrv->name, PATH_SEPARATOR, ROM_GETNAME(romp), ".chd");
	845	filerr = mame_fopen_options(options, SEARCHPATH_IMAGE, astring_c(fname), OPEN_FLAG_READ, image_file);
	846	astring_free(fname);
	847	}
832	848
833	849	/* did the file open succeed? */
834	850	if (filerr == FILERR_NONE)
r949	r950
856	872	if (strcmp(ROM_GETNAME(romp), ROM_GETNAME(rom)) != 0 &&
857	873	hash_data_is_equal(ROM_GETHASHDATA(romp), ROM_GETHASHDATA(rom), 0))
858	874	{
859		fname = astring_assemble_4(astring_alloc(), drv->name, PATH_SEPARATOR, ROM_GETNAME(rom), ".chd");
860		filerr = mame_fopen(SEARCHPATH_IMAGE, astring_c(fname), OPEN_FLAG_READ \| OPEN_FLAG_WRITE, image_file);
861		astring_free(fname);
	875	/* attempt to open the properly named file, scanning up through parent directories */
	876	filerr = FILERR_NOT_FOUND;
	877	for (searchdrv = drv; searchdrv != NULL && filerr != FILERR_NONE; searchdrv = driver_get_clone(searchdrv))
	878	{
	879	astring *fname = astring_assemble_4(astring_alloc(), searchdrv->name, PATH_SEPARATOR, ROM_GETNAME(rom), ".chd");
	880	filerr = mame_fopen_options(options, SEARCHPATH_IMAGE, astring_c(fname), OPEN_FLAG_READ, image_file);
	881	astring_free(fname);
	882	}
862	883
863	884	/* did the file open succeed? */
864	885	if (filerr == FILERR_NONE)

src/lib/util/bitmap.c
r949	r950
44	44	if (bpp == 0)
45	45	return NULL;
46	46
	47	/* allocate the bitmap itself */
	48	bitmap = malloc(sizeof(*bitmap));
	49	if (bitmap == NULL)
	50	return NULL;
	51	memset(bitmap, 0, sizeof(*bitmap));
	52
47	53	/* round the width to a multiple of 8 and add some padding */
48	54	rowpixels = (width + 2 * xslop + 7) & ~7;
49	55
50		/* allocate memory */
51		allocbytes = sizeof(bitmap) + rowpixels (height + 2 * yslop) * bpp / 8;
52		bitmap = malloc(allocbytes);
53		if (bitmap == NULL)
	56	/* allocate memory for the bitmap itself */
	57	allocbytes = rowpixels * (height + 2 * yslop) * bpp / 8;
	58	bitmap->alloc = malloc(allocbytes);
	59	if (bitmap->alloc == NULL)
	60	{
	61	free(bitmap);
54	62	return NULL;
	63	}
55	64
56	65	/* clear to 0 by default */
57		memset(bitmap, 0, allocbytes);
	66	memset(bitmap->alloc, 0, allocbytes);
58	67
59	68	/* fill in the data */
60	69	bitmap->format = format;
r949	r950
62	71	bitmap->height = height;
63	72	bitmap->bpp = bpp;
64	73	bitmap->rowpixels = rowpixels;
65		bitmap->base = (UINT8 )bitmap ~~+ sizeof(bitm~~ap) + rowpixels * yslop + (bpp / 8) * xslop;
	74	bitmap->base = (UINT8 )bitmap->alloc + (rowpixels yslop + xslop) * (bpp / 8);
66	75
67	76	return bitmap;
68	77	}
r949	r950
86	95	bitmap = malloc(sizeof(*bitmap));
87	96	if (bitmap == NULL)
88	97	return NULL;
	98	memset(bitmap, 0, sizeof(*bitmap));
89	99
90	100	/* fill in the data */
91	101	bitmap->format = format;
r949	r950
133	143	if (bitmap->palette != NULL)
134	144	palette_deref(bitmap->palette);
135	145
	146	/* free any allocated memory */
	147	if (bitmap->alloc != NULL)
	148	free(bitmap->alloc);
	149
136	150	/* free the bitmap */
137	151	free(bitmap);
138	152	}

src/lib/util/bitmap.h
r949	r950
53	53	typedef struct _bitmap_t bitmap_t;
54	54	struct _bitmap_t
55	55	{
	56	void * alloc; /* pointer to allocated pixel memory */
56	57	void * base; /* pointer to pixel (0,0) (adjusted for padding) */
57	58	int rowpixels; /* pixels per row (including padding) */
58	59	int width; /* width of the bitmap */

src/lib/util/corefile.c
r949	r950
631	631	core_vfprintf - vfprintf to a text file
632	632	-------------------------------------------------*/
633	633
634		~~static~~ int core_vfprintf(core_file f, const char fmt, va_list va)
	634	int core_vfprintf(core_file f, const char fmt, va_list va)
635	635	{
636	636	char buf[1024];
637	637	vsnprintf(buf, sizeof(buf), fmt, va);

src/lib/util/corefile.h
r949	r950
14	14	#ifndef __COREFILE_H__
15	15	#define __COREFILE_H__
16	16
	17	#include <stdarg.h>
17	18	#include "osdcore.h"
18	19	#include "astring.h"
19	20
r949	r950
98	99	int core_fputs(core_file f, const char s);
99	100
100	101	/* printf-style text write to a file */
	102	int core_vfprintf(core_file f, const char fmt, va_list va);
101	103	int CLIB_DECL core_fprintf(core_file f, const char fmt, ...);
102	104
103	105

src/mess/climess.c
r949	r950
41	41	info_listdevices - list all devices in MESS
42	42	-------------------------------------------------*/
43	43
44		int info_listdevices(const char *gamename)
	44	int info_listdevices(core_options opts, const char gamename)
45	45	{
46	46	int i, dev, id;
47	47	const struct IODevice *devices;

src/mess/climess.h
r949	r950
17	17	***************************************************************************/
18	18
19	19	void mess_display_help(void);
20		int info_listdevices(const char *gamename);
	20	int info_listdevices(core_options opts, const char gamename);
21	21
22	22
23	23	#endif /* __CLIMESS_H__ */

src/mess/mess.h
r949	r950
49	49
50	50	/***************************************************************************/
51	51
52		void mess_options_init(void);
	52	void mess_options_init(core_options *opts);
53	53
54	54	extern char mess_disclaimer[];
55	55

src/mess/tools/messtest/testmess.c
r949	r950
276	276	astring *fullpath = NULL;
277	277	const char *device_opt;
278	278	const char *fake_argv[2];
	279	core_options *opts;
279	280
280	281	/* lookup driver */
281	282	driver = driver_get_name(current_testcase.driver);
r949	r950
300	301	dirtybuffer = NULL;
301	302
302	303	/* set up options */
303		mame_options_init(win_mess_opts);
304		options_set_string(mame_options(), OPTION_GAMENAME, driver->name, OPTION_PRIORITY_CMDLINE);
305		options_set_bool(mame_options(), OPTION_SKIP_GAMEINFO, TRUE, OPTION_PRIORITY_CMDLINE);
306		options_set_bool(mame_options(), OPTION_THROTTLE, FALSE, OPTION_PRIORITY_CMDLINE);
307		options_set_bool(mame_options(), OPTION_SKIP_WARNINGS, TRUE, OPTION_PRIORITY_CMDLINE);
	304	opts = mame_options_init(win_mess_opts);
	305	options_set_string(opts, OPTION_GAMENAME, driver->name, OPTION_PRIORITY_CMDLINE);
	306	options_set_bool(opts, OPTION_SKIP_GAMEINFO, TRUE, OPTION_PRIORITY_CMDLINE);
	307	options_set_bool(opts, OPTION_THROTTLE, FALSE, OPTION_PRIORITY_CMDLINE);
	308	options_set_bool(opts, OPTION_SKIP_WARNINGS, TRUE, OPTION_PRIORITY_CMDLINE);
308	309	if (current_testcase.ram != 0)
309	310	{
310		options_set_int(~~mame_~~opt~~ion~~s(), OPTION_RAMSIZE, current_testcase.ram, OPTION_PRIORITY_CMDLINE);
	311	options_set_int(opts, OPTION_RAMSIZE, current_testcase.ram, OPTION_PRIORITY_CMDLINE);
311	312	}
312	313
313	314	/* ugh... hideous ugly fake arguments */
314	315	fake_argv[0] = "MESSTEST";
315	316	fake_argv[1] = driver->name;
316		options_parse_command_line(~~mame_~~opt~~ion~~s(), ARRAY_LENGTH(fake_argv), (char **) fake_argv, OPTION_PRIORITY_CMDLINE);
	317	options_parse_command_line(opts, ARRAY_LENGTH(fake_argv), (char **) fake_argv, OPTION_PRIORITY_CMDLINE);
317	318
318	319	/* preload any needed images */
319	320	while(current_command->command_type == MESSTEST_COMMAND_IMAGE_PRELOAD)
r949	r950
325	326	device_opt = device_typename(current_command->u.image_args.device_type);
326	327
327	328	/* set the option */
328		options_set_string(~~mame_~~opt~~ion~~s(), device_opt, astring_c(fullpath), OPTION_PRIORITY_CMDLINE);
	329	options_set_string(opts, device_opt, astring_c(fullpath), OPTION_PRIORITY_CMDLINE);
329	330
330	331	/* cleanup */
331	332	astring_free(fullpath);
r949	r950
343	344	mame_set_output_channel(OUTPUT_CHANNEL_INFO, mame_null_output_callback, NULL, NULL, NULL);
344	345	mame_set_output_channel(OUTPUT_CHANNEL_DEBUG, mame_null_output_callback, NULL, NULL, NULL);
345	346	mame_set_output_channel(OUTPUT_CHANNEL_LOG, mame_null_output_callback, NULL, NULL, NULL);
346		mame_execute();
	347	mame_execute(opts);
347	348	real_run_time = ((double) (clock() - begin_time)) / CLOCKS_PER_SEC;
348	349
349	350	/* what happened? */
r949	r950
382	383	results->runtime_hash = runtime_hash;
383	384	}
384	385
385		~~mame_~~options_e~~xit~~();
	386	options_free(opts);
386	387	return rc;
387	388	}
388	389

src/mess/tools/imgtool/windows/wmain.c
r949	r950
101	101	/* dummy */
102	102	return 0;
103	103	}
104
105
106
107		void mess_options_init(void)
108		{
109		/* dummy */
110		}

src/mess/tools/imgtool/main.c
r949	r950
995	995	imgtool_exit();
996	996	return result;
997	997	}
998
999		void mess_options_init(void)
1000		{
1001		/* dummy */
1002		}

src/mess/messopts.c
r949	r950
157	157	MESS specific options
158	158	-------------------------------------------------*/
159	159
160		void mess_options_init(void)
	160	void mess_options_init(core_options *opts)
161	161	{
162	162	/* add MESS-specific options */
163		options_add_entries(~~mame_~~opt~~ion~~s(), mess_core_options);
	163	options_add_entries(opts, mess_core_options);
164	164
165	165	/* add OSD-MESS specific options (hack!) */
166	166	osd_mess_options_init();
r949	r950
169	169	added_device_options = FALSE;
170	170
171	171	/* we need to dynamically add options when the device name is parsed */
172		options_set_option_callback(~~mame_~~opt~~ion~~s(), OPTION_GAMENAME, mess_driver_name_callback);
	172	options_set_option_callback(opts, OPTION_GAMENAME, mess_driver_name_callback);
173	173	}
174	174
175	175

src/mess/messopts.h
r949	r950
29	29	***************************************************************************/
30	30
31	31	/* initialize MESS specific options (called from MAME core) */
32		void mess_options_init(void);
	32	void mess_options_init(core_options *opts);
33	33
34	34	/* extract device options out of core into the options */
35	35	void mess_options_extract(void);

docs/messnew.txt
r949	r950
63	63
64	64	Source Changes:
65	65	----------------
66		- The core is based on MAME 0.118u5. This incorporates all features of the
	66	- The core is based on MAME 0.118u6. This incorporates all features of the
67	67	update to this core. [MAME team]
68	68
69	69

makefile
r949	r950
344	344	#CFLAGS += $(ARCH) -fno-strict-aliasing
345	345	endif
346	346
	347	# if symbols are on, make sure we have frame pointers
	348	ifdef SYMBOLS
	349	CFLAGS += -fno-omit-frame-pointer
	350	endif
347	351
348	352
	353
349	354	#-------------------------------------------------
350	355	# include paths
351	356	#-------------------------------------------------

15994 Revisions