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r9482 Sunday 31st October, 2010 at 11:36:58 UTC by Wilbert Pol
i286.c: Partially implemented protected mode. Fixed verw, verr, lar, lsl, and arpl instructions. [Wilbert Pol]
[src/emu/cpu/i86]ea.h i286.c i86.c i86priv.h instr286.c instr286.h instr86.c modrm286.h*

src/emu/cpu/i86/instr286.c
r9481r9482
1717   7 p present 0 gives trap when accessed
1818   UINT16 reserved (should be zero)
1919*/
20#define WRITEABLE(a) ((a&0xa)==2)
21#define READABLE(a) ( ((a&0xa)==0xa)|| ((a&8)==0) )
20#define IS_PRESENT(a)      ( ( (a) & 0x80 ) == 0x80 )
21#define IS_WRITEABLE(a)      ( ( (a) & 0xa ) == 2 )
22#define IS_READABLE(a)      ( ( ( (a) & 0xa ) == 0xa ) || ( ( (a) & 8 ) == 0 ) )
2223
2324static void i80286_trap2(i80286_state *cpustate,int number)
2425{
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205206         if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
206207         tmp=GetRMWord(ModRM);
207208         if (tmp&4) {
208            cpustate->ZeroVal=( ((tmp&~7)<cpustate->ldtr.limit)
209                     && READABLE( ReadByte(cpustate->ldtr.base+(tmp&~7)+5)) );
209            cpustate->ZeroVal=! ( ((tmp&~7)<cpustate->ldtr.limit)
210                     && IS_READABLE( ReadByte(cpustate->ldtr.base+(tmp&~7)+5)) );
210211         } else {
211            cpustate->ZeroVal=( ((tmp&~7)<cpustate->gdtr.limit)
212                     && READABLE( ReadByte(cpustate->gdtr.base+(tmp&~7)+5)) );
212            cpustate->ZeroVal=! ( ((tmp&~7)<cpustate->gdtr.limit)
213                     && IS_READABLE( ReadByte(cpustate->gdtr.base+(tmp&~7)+5)) );
213214         }
214215         break;
215216      case 0x28: /* verw */
216217         if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
217218         tmp=GetRMWord(ModRM);
218219         if (tmp&4) {
219            cpustate->ZeroVal=( ((tmp&~7)<cpustate->ldtr.limit)
220                     && WRITEABLE( ReadByte(cpustate->ldtr.base+(tmp&~7)+5)) );
220            cpustate->ZeroVal=! ( ((tmp&~7)<cpustate->ldtr.limit)
221                     && IS_WRITEABLE( ReadByte(cpustate->ldtr.base+(tmp&~7)+5)) );
221222         } else {
222            cpustate->ZeroVal=( ((tmp&~7)<cpustate->gdtr.limit)
223                     && WRITEABLE( ReadByte(cpustate->gdtr.base+(tmp&~7)+5)) );
223            cpustate->ZeroVal=! ( ((tmp&~7)<cpustate->gdtr.limit)
224                     && IS_WRITEABLE( ReadByte(cpustate->gdtr.base+(tmp&~7)+5)) );
224225         }
225226         break;
226227      default:
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268269   case 2: /* LAR */
269270      ModRM = FETCHOP;
270271      tmp=GetRMWord(ModRM);
271      cpustate->ZeroVal=i80286_selector_okay(cpustate,tmp);
272      if (cpustate->ZeroVal) {
273         RegWord(ModRM)=tmp;
272      if ( i80286_selector_okay(cpustate,tmp) )
273      {
274         cpustate->ZeroVal = 0;
275         RegWord(ModRM) = ReadByte( i80286_selector_to_address(cpustate,tmp) + 5 ) << 8;
274276      }
277      else
278      {
279         cpustate->ZeroVal = 1;
280      }
275281      break;
276282   case 3: /* LSL */
277283      if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
278284      ModRM = FETCHOP;
279285      tmp=GetRMWord(ModRM);
280      cpustate->ZeroVal=i80286_selector_okay(cpustate,tmp);
281      if (cpustate->ZeroVal) {
286      if ( i80286_selector_okay(cpustate,tmp) )
287      {
288         cpustate->ZeroVal = 0;
282289         addr=i80286_selector_to_address(cpustate,tmp);
283290         RegWord(ModRM)=ReadWord(addr);
284291      }
292      else
293      {
294         cpustate->ZeroVal = 1;
295      }
285296      break;
286297   case 6: /* clts */
287298      if (PM&&(CPL!=0)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
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295306
296307static void PREFIX286(_arpl)(i8086_state *cpustate) /* 0x63 */
297308{
298   if (PM) {
299      UINT16 ModRM=FETCHOP, tmp=GetRMWord(ModRM);
309   if (PM)
310   {
311      UINT16 ModRM=FETCHOP, tmp=GetRMWord(ModRM), source=RegWord(ModRM);
300312
301      cpustate->ZeroVal=i80286_selector_okay(cpustate,RegWord(ModRM))
302           &&i80286_selector_okay(cpustate,RegWord(ModRM))
303           &&((tmp&3)<(RegWord(ModRM)&3));
304      if (cpustate->ZeroVal) PutbackRMWord(ModRM, (tmp&~3)|(RegWord(ModRM)&3));
305   } else {
313      if ( i80286_selector_okay(cpustate,tmp) &&i80286_selector_okay(cpustate,source) &&((tmp&3)<(source&3)) )
314      {
315         cpustate->ZeroVal = 0;
316         PutbackRMWord(ModRM, (tmp&~3)|(source&3));
317      }
318      else
319      {
320         cpustate->ZeroVal = 1;
321      }
322   }
323   else
324   {
306325      i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
307326   }
308327}
328
329static void i80286_check_permission(i8086_state *cpustate, UINT8 check_seg, UINT16 offset, i80286_size size, i80286_operation operation)
330{
331   if (PM)
332   {
333      /* Is the segment physically present? */
334      if ( ! IS_PRESENT( cpustate->rights[check_seg] ) )
335         throw GENERAL_PROTECTION_FAULT;
336
337      /* Would we go past the segment boundary? */
338      if ( offset + size > cpustate->limit[check_seg] )
339      {
340         throw GENERAL_PROTECTION_FAULT;
341      }
342
343      switch(operation)
344      {
345      case I80286_READ:
346         /* Is the segment readable? */
347         if ( ! IS_READABLE( cpustate->rights[check_seg] ) )
348            throw GENERAL_PROTECTION_FAULT;
349         break;
350
351      case I80286_WRITE:
352         /* Is the segment writeable?  */
353         if ( ! IS_WRITEABLE( cpustate->rights[check_seg] ) )
354            throw GENERAL_PROTECTION_FAULT;
355         break;
356
357      case I80286_EXECUTE:
358         /* TODO */
359         break;
360      }
361      /* TODO: Mark segment as accessed? */
362   }
363}
364
src/emu/cpu/i86/instr286.h
r9481r9482
1111static void i80286_data_descriptor(i80286_state *cpustate,int reg, UINT16 selector);
1212static void PREFIX286(_0fpre)(i80286_state *cpustate);
1313static void PREFIX286(_arpl)(i80286_state *cpustate);
14
15enum i80286_size
16{
17   I80286_BYTE = 1,
18   I80286_WORD = 2
19};
20
21enum i80286_operation
22{
23   I80286_READ = 1,
24   I80286_WRITE,
25   I80286_EXECUTE
26};
27
28static void i80286_check_permission(i8086_state *cpustate, UINT8 check_seg, UINT16 offset, i80286_size size, i80286_operation operation);
src/emu/cpu/i86/i86.c
r9481r9482
6262   address_space *io;
6363   int icount;
6464
65   unsigned prefix_base;         /* base address of the latest prefix segment */
6665   char seg_prefix;               /* prefix segment indicator */
66   UINT8   prefix_seg;               /* The prefixed segment */
6767   unsigned ea;
6868   UINT16 eo; /* HJB 12/13/98 effective offset of the address (before segment is added) */
69   UINT8 ea_seg;   /* effective segment of the address */
6970
7071   devcb_resolved_write_line   out_tmrout0_func;
7172   devcb_resolved_write_line   out_tmrout1_func;
r9481r9482
556557      case CPUINFO_INT_CLOCK_MULTIPLIER:            info->i = 1;                     break;
557558      case CPUINFO_INT_CLOCK_DIVIDER:               info->i = 1;                     break;
558559      case CPUINFO_INT_MIN_INSTRUCTION_BYTES:         info->i = 1;                     break;
559      case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 8;                     break;
560      case CPUINFO_INT_MAX_INSTRUCTION_BYTES:         info->i = 16;                     break;
560561      case CPUINFO_INT_MIN_CYCLES:               info->i = 1;                     break;
561562      case CPUINFO_INT_MAX_CYCLES:               info->i = 50;                     break;
562563
src/emu/cpu/i86/i86priv.h
r9481r9482
9898
9999#define SegBase(Seg)         (cpustate->sregs[Seg] << 4)
100100
101#define DefaultBase(Seg)      ((cpustate->seg_prefix && (Seg == DS || Seg == SS)) ? cpustate->prefix_base : cpustate->base[Seg])
101#define DefaultSeg(Seg)         ((cpustate->seg_prefix && (Seg == DS || Seg == SS)) ? cpustate->prefix_seg : Seg)
102#define DefaultBase(Seg)      ((cpustate->seg_prefix && (Seg == DS || Seg == SS)) ? cpustate->base[cpustate->prefix_seg] : cpustate->base[Seg])
102103
103104#define GetMemB(Seg,Off)      (read_mem_byte((DefaultBase(Seg) + (Off)) & AMASK))
104105#define GetMemW(Seg,Off)      (read_mem_word((DefaultBase(Seg) + (Off)) & AMASK))
src/emu/cpu/i86/instr86.c
r9481r9482
391391    switch(next)
392392    {
393393   case 0x26:  /* ES: */
394      cpustate->seg_prefix=TRUE;
395      cpustate->prefix_base=cpustate->base[ES];
394      cpustate->seg_prefix = TRUE;
395      cpustate->prefix_seg = ES;
396396      if (!cpustate->rep_in_progress)
397397         ICOUNT -= timing.override;
398398      PREFIX(rep)(cpustate, flagval);
399399      break;
400400   case 0x2e:  /* CS: */
401      cpustate->seg_prefix=TRUE;
402      cpustate->prefix_base=cpustate->base[CS];
401      cpustate->seg_prefix = TRUE;
402      cpustate->prefix_seg = CS;
403403      if (!cpustate->rep_in_progress)
404404         ICOUNT -= timing.override;
405405      PREFIX(rep)(cpustate, flagval);
406406      break;
407407   case 0x36:  /* SS: */
408      cpustate->seg_prefix=TRUE;
409      cpustate->prefix_base=cpustate->base[SS];
408      cpustate->seg_prefix = TRUE;
409      cpustate->prefix_seg = SS;
410410      if (!cpustate->rep_in_progress)
411411         ICOUNT -= timing.override;
412412      PREFIX(rep)(cpustate, flagval);
413413      break;
414414   case 0x3e:  /* DS: */
415      cpustate->seg_prefix=TRUE;
416      cpustate->prefix_base=cpustate->base[DS];
415      cpustate->seg_prefix = TRUE;
416      cpustate->prefix_seg = DS;
417417      if (!cpustate->rep_in_progress)
418418         ICOUNT -= timing.override;
419419      PREFIX(rep)(cpustate, flagval);
r9481r9482
958958
959959static void PREFIX86(_es)(i8086_state *cpustate)    /* Opcode 0x26 */
960960{
961   cpustate->seg_prefix=TRUE;
962   cpustate->prefix_base=cpustate->base[ES];
961   cpustate->seg_prefix = TRUE;
962   cpustate->prefix_seg = ES;
963963   ICOUNT -= timing.override;
964964   PREFIX(_instruction)[FETCHOP](cpustate);
965965}
r9481r9482
10341034
10351035static void PREFIX86(_cs)(i8086_state *cpustate)    /* Opcode 0x2e */
10361036{
1037    cpustate->seg_prefix=TRUE;
1038   cpustate->prefix_base=cpustate->base[CS];
1037    cpustate->seg_prefix = TRUE;
1038   cpustate->prefix_seg = CS;
10391039   ICOUNT -= timing.override;
10401040   PREFIX(_instruction)[FETCHOP](cpustate);
10411041}
r9481r9482
11111111
11121112static void PREFIX86(_ss)(i8086_state *cpustate)    /* Opcode 0x36 */
11131113{
1114   cpustate->seg_prefix=TRUE;
1115   cpustate->prefix_base=cpustate->base[SS];
1114   cpustate->seg_prefix = TRUE;
1115   cpustate->prefix_seg = SS;
11161116   ICOUNT -= timing.override;
11171117   PREFIX(_instruction)[FETCHOP](cpustate);
11181118}
r9481r9482
11821182
11831183static void PREFIX86(_ds)(i8086_state *cpustate)    /* Opcode 0x3e */
11841184{
1185   cpustate->seg_prefix=TRUE;
1186   cpustate->prefix_base=cpustate->base[DS];
1185   cpustate->seg_prefix = TRUE;
1186   cpustate->prefix_seg = DS;
11871187   ICOUNT -= timing.override;
11881188   PREFIX(_instruction)[FETCHOP](cpustate);
11891189}
r9481r9482
31653165#ifdef I80286
31663166   i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
31673167#else
3168    /* makes the cpu loops forever until user resets it */
3169   /*{ debugger_break(Machine); } */
3170   logerror("illegal instruction %.2x at %.5x\n",PEEKBYTE(cpustate->pc), cpustate->pc);
3171   cpustate->pc--;
3168   /* i8086/i8088 ignore an invalid opcode. */
3169   /* i80186/i80188 probably also ignore an invalid opcode. */
3170   logerror("illegal instruction %.2x at %.5x\n",PEEKBYTE(cpustate->pc-1), cpustate->pc);
31723171   ICOUNT -= 10;
31733172#endif
31743173}
src/emu/cpu/i86/modrm286.h
r0r9482
1static struct
2{
3   struct
4   {
5      WREGS w[256];
6      BREGS b[256];
7   } reg;
8   struct
9   {
10      WREGS w[256];
11      BREGS b[256];
12   } RM;
13} Mod_RM;
14
15#define RegWord(ModRM) cpustate->regs.w[Mod_RM.reg.w[ModRM]]
16#define RegByte(ModRM) cpustate->regs.b[Mod_RM.reg.b[ModRM]]
17
18#define GetRMWord(ModRM) \
19   ((ModRM) >= 0xc0 ? cpustate->regs.w[Mod_RM.RM.w[ModRM]] : ( (*GetEA[ModRM])(cpustate), i80286_check_permission(cpustate, cpustate->ea_seg, cpustate->eo, I80286_WORD, I80286_READ), ReadWord( cpustate->ea ) ))
20
21#define PutbackRMWord(ModRM,val)                                                      \
22{                                                                              \
23   if (ModRM >= 0xc0) cpustate->regs.w[Mod_RM.RM.w[ModRM]]=val;                              \
24    else                                                                        \
25   {                                                                           \
26      i80286_check_permission(cpustate, cpustate->ea_seg, cpustate->eo, I80286_WORD, I80286_WRITE);   \
27      WriteWord(cpustate->ea,val);                                                   \
28   }                                                                           \
29}
30
31#define GetnextRMWord                                                                                       \
32   (                                                                                                   \
33   i80286_check_permission(cpustate, cpustate->ea_seg, cpustate->ea + 2 - cpustate->base[cpustate->ea_seg], I80286_WORD, I80286_READ),   \
34   ReadWord(cpustate->ea+2)                                                                                 \
35   )
36
37#define GetRMWordOffset(offs)                                                                  \
38      (                                                                                 \
39      i80286_check_permission(cpustate, cpustate->ea_seg, (UINT16)(cpustate->eo+offs), I80286_WORD, I80286_READ),   \
40      ReadWord(cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs))                                    \
41      )
42
43#define GetRMByteOffset(offs)                                                                  \
44      (                                                                                 \
45      i80286_check_permission(cpustate, cpustate->ea_seg, (UINT16)(cpustate->eo+offs), I80286_BYTE, I80286_READ),   \
46      ReadByte(cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs))                                    \
47      )
48
49#define PutRMWord(ModRM,val)                                                         \
50{                                                                              \
51   if (ModRM >= 0xc0)                                                               \
52      cpustate->regs.w[Mod_RM.RM.w[ModRM]]=val;                                          \
53   else {                                                                        \
54      (*GetEA[ModRM])(cpustate);                                                      \
55      i80286_check_permission(cpustate, cpustate->ea_seg, cpustate->eo, I80286_WORD, I80286_WRITE);   \
56      WriteWord( cpustate->ea ,val);                                                   \
57   }                                                                           \
58}
59
60#define PutRMWordOffset(offs, val)                                                                  \
61      i80286_check_permission(cpustate, cpustate->ea_seg, (UINT16)(cpustate->eo+offs), I80286_WORD, I80286_WRITE);   \
62      WriteWord( cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs), val)
63
64#define PutRMByteOffset(offs, val)                                                                  \
65      i80286_check_permission(cpustate, cpustate->ea_seg, (UINT16)(cpustate->eo+offs), I80286_BYTE, I80286_WRITE);   \
66      WriteByte( cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs), val)
67
68#define PutImmRMWord(ModRM)                                                          \
69{                                                                              \
70   WORD val;                                                                     \
71   if (ModRM >= 0xc0)                                                               \
72      FETCHWORD(cpustate->regs.w[Mod_RM.RM.w[ModRM]])                                       \
73   else {                                                                        \
74      (*GetEA[ModRM])(cpustate);                                                      \
75      i80286_check_permission(cpustate, cpustate->ea_seg, cpustate->eo, I80286_WORD, I80286_WRITE);   \
76      FETCHWORD(val)                                                               \
77      WriteWord( cpustate->ea , val);                                                   \
78   }                                                                           \
79}
80
81#define GetRMByte(ModRM) \
82   ((ModRM) >= 0xc0 ? cpustate->regs.b[Mod_RM.RM.b[ModRM]] : ( (*GetEA[ModRM])(cpustate), i80286_check_permission(cpustate, cpustate->ea_seg, cpustate->eo, I80286_BYTE, I80286_READ), ReadByte( cpustate->ea )) )
83
84#define PutRMByte(ModRM,val)                                                         \
85{                                                                              \
86   if (ModRM >= 0xc0)                                                               \
87      cpustate->regs.b[Mod_RM.RM.b[ModRM]]=val;                                          \
88   else                                                                        \
89   {                                                                           \
90      (*GetEA[ModRM])(cpustate);                                                      \
91      i80286_check_permission(cpustate, cpustate->ea_seg, cpustate->eo, I80286_BYTE, I80286_WRITE);   \
92      WriteByte( cpustate->ea,val);                                                   \
93   }                                                                           \
94}
95
96#define PutImmRMByte(ModRM)                                                          \
97{                                                                              \
98   if (ModRM >= 0xc0)                                                               \
99      cpustate->regs.b[Mod_RM.RM.b[ModRM]]=FETCH;                                          \
100   else {                                                                        \
101      (*GetEA[ModRM])(cpustate);                                                      \
102      i80286_check_permission(cpustate, cpustate->ea_seg, cpustate->eo, I80286_BYTE, I80286_WRITE);   \
103      WriteByte( cpustate->ea , FETCH );                                                \
104   }                                                                           \
105}
106
107#define PutbackRMByte(ModRM,val)                                                      \
108{                                                                              \
109   if (ModRM >= 0xc0)                                                               \
110      cpustate->regs.b[Mod_RM.RM.b[ModRM]]=val;                                          \
111   else                                                                        \
112   {                                                                           \
113      i80286_check_permission(cpustate, cpustate->ea_seg, cpustate->eo, I80286_BYTE, I80286_WRITE);   \
114      WriteByte(cpustate->ea,val);                                                   \
115   }                                                                           \
116}
117
118#define DEF_br8(dst,src)               \
119   unsigned ModRM = FETCHOP;            \
120   unsigned src = RegByte(ModRM);         \
121    unsigned dst = GetRMByte(ModRM)
122
123#define DEF_wr16(dst,src)               \
124   unsigned ModRM = FETCHOP;            \
125   unsigned src = RegWord(ModRM);         \
126    unsigned dst = GetRMWord(ModRM)
127
128#define DEF_r8b(dst,src)               \
129   unsigned ModRM = FETCHOP;            \
130   unsigned dst = RegByte(ModRM);         \
131    unsigned src = GetRMByte(ModRM)
132
133#define DEF_r16w(dst,src)               \
134   unsigned ModRM = FETCHOP;            \
135   unsigned dst = RegWord(ModRM);         \
136    unsigned src = GetRMWord(ModRM)
137
138#define DEF_ald8(dst,src)               \
139   unsigned src = FETCHOP;             \
140   unsigned dst = cpustate->regs.b[AL]
141
142#define DEF_axd16(dst,src)               \
143   unsigned src = FETCHOP;             \
144   unsigned dst = cpustate->regs.w[AX];   \
145    src += (FETCH << 8)
src/emu/cpu/i86/i286.c
r9481r9482
7575   int halted;         /* Is the CPU halted ? */
7676
7777   int icount;
78   unsigned prefix_base;
7978   char seg_prefix;
79   UINT8   prefix_seg;
8080   unsigned ea;
8181   UINT16 eo; /* HJB 12/13/98 effective offset of the address (before segment is added) */
82   UINT8 ea_seg;   /* effective segment of the address */
8283};
8384
8485INLINE i80286_state *get_safe_token(running_device *device)
r9481r9482
105106#define i8086_state i80286_state
106107
107108#include "ea.h"
108#include "modrm.h"
109#include "modrm286.h"
109110#include "instr86.h"
110111#include "instr186.h"
111112#include "instr286.h"
r9481r9482
226227      cpustate->seg_prefix=FALSE;
227228      cpustate->prevpc = cpustate->pc;
228229
229      TABLE286 // call instruction
230      try
231      {
232         TABLE286 // call instruction
233      }
234      catch (int e)
235      {
236         i80286_trap2(cpustate,e);
237      }
230238    }
231239
232240   /* adjust for any interrupts that came in */
src/emu/cpu/i86/ea.h
r9481r9482
1static unsigned EA_000(i8086_state *cpustate) { cpustate->icount-=7; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[SI]); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
2static unsigned EA_001(i8086_state *cpustate) { cpustate->icount-=8; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[DI]); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
3static unsigned EA_002(i8086_state *cpustate) { cpustate->icount-=8; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[SI]); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
4static unsigned EA_003(i8086_state *cpustate) { cpustate->icount-=7; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[DI]); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
5static unsigned EA_004(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[SI]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
6static unsigned EA_005(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[DI]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
7static unsigned EA_006(i8086_state *cpustate) { cpustate->icount-=6; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
8static unsigned EA_007(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[BX]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
1static unsigned EA_000(i8086_state *cpustate) { cpustate->icount-=7; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[SI]); cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
2static unsigned EA_001(i8086_state *cpustate) { cpustate->icount-=8; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[DI]); cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
3static unsigned EA_002(i8086_state *cpustate) { cpustate->icount-=8; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[SI]); cpustate->ea_seg=DefaultSeg(SS); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
4static unsigned EA_003(i8086_state *cpustate) { cpustate->icount-=7; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[DI]); cpustate->ea_seg=DefaultSeg(SS); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
5static unsigned EA_004(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[SI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
6static unsigned EA_005(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[DI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
7static unsigned EA_006(i8086_state *cpustate) { cpustate->icount-=6; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
8static unsigned EA_007(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[BX]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
99
10static unsigned EA_100(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
11static unsigned EA_101(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
12static unsigned EA_102(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
13static unsigned EA_103(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
14static unsigned EA_104(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
15static unsigned EA_105(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
16static unsigned EA_106(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[BP]+(INT8)FETCHOP); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
17static unsigned EA_107(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[BX]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
10static unsigned EA_100(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
11static unsigned EA_101(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
12static unsigned EA_102(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea_seg=DefaultSeg(SS); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
13static unsigned EA_103(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea_seg=DefaultSeg(SS); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
14static unsigned EA_104(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
15static unsigned EA_105(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
16static unsigned EA_106(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[BP]+(INT8)FETCHOP); cpustate->ea_seg=DefaultSeg(SS); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
17static unsigned EA_107(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[BX]+(INT8)FETCHOP); cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
1818
19static unsigned EA_200(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]+cpustate->regs.w[SI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
20static unsigned EA_201(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]+cpustate->regs.w[DI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
21static unsigned EA_202(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]+cpustate->regs.w[SI]; cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
22static unsigned EA_203(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]+cpustate->regs.w[DI]; cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
23static unsigned EA_204(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[SI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
24static unsigned EA_205(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[DI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
25static unsigned EA_206(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]; cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
26static unsigned EA_207(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
19static unsigned EA_200(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]+cpustate->regs.w[SI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
20static unsigned EA_201(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]+cpustate->regs.w[DI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
21static unsigned EA_202(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]+cpustate->regs.w[SI]; cpustate->ea_seg=DefaultSeg(SS); cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
22static unsigned EA_203(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]+cpustate->regs.w[DI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
23static unsigned EA_204(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[SI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
24static unsigned EA_205(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[DI]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
25static unsigned EA_206(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]; cpustate->ea_seg=DefaultSeg(SS); cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
26static unsigned EA_207(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]; cpustate->ea_seg=DefaultSeg(DS); cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
2727
2828static unsigned (*const GetEA[192])(i8086_state *cpustate)={
2929   EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,

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