src/mess/drivers/pc88va.c
| r9479 | r9480 | |
| 17 | 17 | //#include "cpu/z80/z80.h" |
| 18 | 18 | #include "machine/i8255a.h" |
| 19 | 19 | #include "machine/pic8259.h" |
| 20 | #include "machine/pc_fdc.h" |
| 21 | #include "machine/upd765.h" |
| 20 | 22 | |
| 21 | 23 | static UINT16 *palram; |
| 22 | 24 | static UINT16 bank_reg; |
| 25 | static UINT16 screen_ctrl_reg; |
| 23 | 26 | static struct |
| 24 | 27 | { |
| 25 | 28 | UINT16 tvram_vreg_offset; |
| r9479 | r9480 | |
| 513 | 516 | |
| 514 | 517 | sw1 = (input_port_read(space->machine, "DSW") & 1) ? 2 : 0; |
| 515 | 518 | |
| 516 | | return vrtc | sw1; |
| 519 | return vrtc | sw1 | 0xc0; |
| 517 | 520 | } |
| 518 | 521 | |
| 519 | 522 | static READ16_HANDLER( bios_bank_r ) |
| r9479 | r9480 | |
| 585 | 588 | return 0x20; |
| 586 | 589 | } |
| 587 | 590 | |
| 588 | | static READ8_HANDLER( fdc_r ) |
| 591 | static READ8_HANDLER( pc88va_fdc_r ) |
| 589 | 592 | { |
| 590 | | return mame_rand(space->machine); |
| 593 | switch(offset*2) |
| 594 | { |
| 595 | case 0x00: return 0; // FDC mode register |
| 596 | case 0x02: return 0; // FDC control port 0 |
| 597 | case 0x04: return 0; // FDC control port 1 |
| 598 | case 0x06: return 0; // FDC control port 2 |
| 599 | case 0x08: return upd765_status_r(space->machine->device("upd765"), 0); |
| 600 | case 0x0a: return upd765_data_r(space->machine->device("upd765"), 0); |
| 601 | } |
| 602 | |
| 603 | return 0xff; |
| 591 | 604 | } |
| 592 | 605 | |
| 606 | static WRITE8_HANDLER( pc88va_fdc_w ) |
| 607 | { |
| 608 | switch(offset*2) |
| 609 | { |
| 610 | case 0x00: break; // FDC mode register |
| 611 | case 0x02: break; // FDC control port 0 |
| 612 | case 0x04: break; // FDC control port 1 |
| 613 | case 0x06: break; // FDC control port 2 |
| 614 | case 0x08: break; // UPD765 status |
| 615 | case 0x0a: upd765_data_w(space->machine->device("upd765"), 0,data); break; |
| 616 | } |
| 617 | } |
| 618 | |
| 619 | |
| 593 | 620 | static READ16_HANDLER( sysop_r ) |
| 594 | 621 | { |
| 595 | 622 | static UINT8 sys_op; |
| r9479 | r9480 | |
| 599 | 626 | return 0xfffc | sys_op; // docs says all the other bits are high |
| 600 | 627 | } |
| 601 | 628 | |
| 629 | static READ16_HANDLER( screen_ctrl_r ) |
| 630 | { |
| 631 | return screen_ctrl_reg; |
| 632 | } |
| 633 | |
| 634 | static WRITE16_HANDLER( screen_ctrl_w ) |
| 635 | { |
| 636 | screen_ctrl_reg = data; |
| 637 | } |
| 638 | |
| 602 | 639 | static ADDRESS_MAP_START( pc88va_io_map, ADDRESS_SPACE_IO, 16 ) |
| 603 | 640 | AM_RANGE(0x0000, 0x000f) AM_READ8(key_r,0xffff) // Keyboard ROW reading |
| 604 | 641 | // AM_RANGE(0x0010, 0x0010) Printer / Calendar Clock Interface |
| 605 | | // AM_RANGE(0x0020, 0x0021) RS-232C |
| 642 | AM_RANGE(0x0020, 0x0021) AM_NOP // RS-232C |
| 606 | 643 | // AM_RANGE(0x0030, 0x0030) (R) DSW1 (W) Text Control Port 0 |
| 607 | 644 | // AM_RANGE(0x0031, 0x0031) (R) DSW2 (W) System Port 1 |
| 608 | 645 | // AM_RANGE(0x0032, 0x0032) (R) ? (W) System Port 2 |
| r9479 | r9480 | |
| 617 | 654 | // AM_RANGE(0x0071, 0x0071) Expansion ROM select (*) |
| 618 | 655 | // AM_RANGE(0x0078, 0x0078) Memory offset increment (*) |
| 619 | 656 | // AM_RANGE(0x0080, 0x0081) HDD related |
| 620 | | AM_RANGE(0x0082, 0x0083) AM_READ8(hdd_status_r,0xff)// HDD control, byte access 7-0 |
| 657 | AM_RANGE(0x0082, 0x0083) AM_READ8(hdd_status_r,0x00ff)// HDD control, byte access 7-0 |
| 621 | 658 | // AM_RANGE(0x00bc, 0x00bf) d8255 1 |
| 622 | 659 | // AM_RANGE(0x00e2, 0x00e3) Expansion RAM selection (*) |
| 623 | 660 | // AM_RANGE(0x00e4, 0x00e4) 8214 IRQ control (*) |
| r9479 | r9480 | |
| 626 | 663 | // AM_RANGE(0x00ec, 0x00ed) ? (*) |
| 627 | 664 | AM_RANGE(0x00fc, 0x00ff) AM_DEVREADWRITE8("d8255_2", i8255a_r,i8255a_w,0xffff) // d8255 2, FDD |
| 628 | 665 | |
| 629 | | // AM_RANGE(0x0100, 0x0101) Screen Control Register |
| 666 | AM_RANGE(0x0100, 0x0101) AM_READWRITE(screen_ctrl_r,screen_ctrl_w) // Screen Control Register |
| 630 | 667 | // AM_RANGE(0x0102, 0x0103) Graphic Screen Control Register |
| 631 | 668 | // AM_RANGE(0x0106, 0x0107) Palette Control Register |
| 632 | 669 | // AM_RANGE(0x0108, 0x0109) Direct Color Control Register |
| r9479 | r9480 | |
| 657 | 694 | AM_RANGE(0x019a, 0x019b) AM_WRITE(backupram_wp_0_w) //Backup RAM write permission |
| 658 | 695 | // AM_RANGE(0x01a0, 0x01a7) TCU (timer counter unit) |
| 659 | 696 | // AM_RANGE(0x01a8, 0x01a9) General-purpose timer 3 control port |
| 660 | | AM_RANGE(0x01b0, 0x01bb) AM_READ8(fdc_r,0xffff)// FDC related (765) |
| 697 | AM_RANGE(0x01b0, 0x01bb) AM_READWRITE8(pc88va_fdc_r,pc88va_fdc_w,0x00ff)// FDC related (765) |
| 661 | 698 | // AM_RANGE(0x01c0, 0x01c1) ? |
| 662 | 699 | AM_RANGE(0x01c6, 0x01c7) AM_WRITENOP // ??? |
| 663 | 700 | AM_RANGE(0x01c8, 0x01cf) AM_DEVREADWRITE8("d8255_3", i8255a_r,i8255a_w,0xff00) //i8255 3 (byte access) |
| 664 | 701 | // AM_RANGE(0x01d0, 0x01d1) Expansion RAM bank selection |
| 665 | | // AM_RANGE(0x0200, 0x021f) Frame buffer 0 control parameter |
| 666 | | // AM_RANGE(0x0220, 0x023f) Frame buffer 1 control parameter |
| 667 | | // AM_RANGE(0x0240, 0x025f) Frame buffer 2 control parameter |
| 668 | | // AM_RANGE(0x0260, 0x027f) Frame buffer 3 control parameter |
| 702 | AM_RANGE(0x0200, 0x021f) AM_RAM // Frame buffer 0 control parameter |
| 703 | AM_RANGE(0x0220, 0x023f) AM_RAM // Frame buffer 1 control parameter |
| 704 | AM_RANGE(0x0240, 0x025f) AM_RAM // Frame buffer 2 control parameter |
| 705 | AM_RANGE(0x0260, 0x027f) AM_RAM // Frame buffer 3 control parameter |
| 669 | 706 | AM_RANGE(0x0300, 0x033f) AM_RAM_WRITE(palette_ram_w) AM_BASE(&palram) // Palette RAM (xBBBBxRRRRxGGGG format) |
| 670 | 707 | |
| 671 | 708 | // AM_RANGE(0x0500, 0x05ff) GVRAM |
| r9479 | r9480 | |
| 1024 | 1061 | DEVCB_DEVICE_LINE("pic8259_master", pic8259_ir7_w) |
| 1025 | 1062 | }; |
| 1026 | 1063 | |
| 1064 | static void pc88va_fdc_interrupt(running_machine *machine, int state) |
| 1065 | { |
| 1066 | pic8259_ir3_w(machine->device( "pic8259_slave"), state); |
| 1067 | } |
| 1068 | |
| 1069 | |
| 1070 | static running_device *pc88va_get_device(running_machine *machine) |
| 1071 | { |
| 1072 | return machine->device("upd765"); |
| 1073 | } |
| 1074 | |
| 1075 | static const struct pc_fdc_interface pc88va_fdc_interface = |
| 1076 | { |
| 1077 | pc88va_fdc_interrupt, |
| 1078 | NULL, |
| 1079 | NULL, |
| 1080 | pc88va_get_device |
| 1081 | }; |
| 1082 | |
| 1027 | 1083 | static MACHINE_START( pc88va ) |
| 1028 | 1084 | { |
| 1029 | 1085 | cpu_set_irq_callback(machine->device("maincpu"), pc88va_irq_callback); |
| 1086 | |
| 1087 | pc_fdc_init(machine, &pc88va_fdc_interface); |
| 1030 | 1088 | } |
| 1031 | 1089 | |
| 1032 | 1090 | static MACHINE_RESET( pc88va ) |
| r9479 | r9480 | |
| 1053 | 1111 | pic8259_ir2_w(device->machine->device("pic8259_master"), 1); |
| 1054 | 1112 | } |
| 1055 | 1113 | |
| 1114 | /* TODO */ |
| 1115 | static const floppy_config pc88va_floppy_config = |
| 1116 | { |
| 1117 | DEVCB_NULL, |
| 1118 | DEVCB_NULL, |
| 1119 | DEVCB_NULL, |
| 1120 | DEVCB_NULL, |
| 1121 | DEVCB_NULL, |
| 1122 | FLOPPY_STANDARD_5_25_DSHD, |
| 1123 | FLOPPY_OPTIONS_NAME(default), |
| 1124 | NULL |
| 1125 | }; |
| 1126 | |
| 1127 | |
| 1056 | 1128 | static MACHINE_CONFIG_START( pc88va, driver_device ) |
| 1057 | 1129 | |
| 1058 | 1130 | MDRV_CPU_ADD("maincpu", V30, 8000000) /* 8 MHz */ |
| r9479 | r9480 | |
| 1087 | 1159 | MDRV_PIC8259_ADD( "pic8259_master", pc88va_pic8259_master_config ) |
| 1088 | 1160 | MDRV_PIC8259_ADD( "pic8259_slave", pc88va_pic8259_slave_config ) |
| 1089 | 1161 | |
| 1162 | MDRV_UPD765A_ADD("upd765", pc_fdc_upd765_connected_interface) |
| 1163 | MDRV_FLOPPY_2_DRIVES_ADD(pc88va_floppy_config) |
| 1164 | |
| 1090 | 1165 | MACHINE_CONFIG_END |
| 1091 | 1166 | |
| 1092 | 1167 | |