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r9409 Sunday 17th October, 2010 at 23:46:53 UTC by Angelo Salese
[Mega CD]: putted hock commands behind a timer, fixes an issue with stop all command
[src/mame/drivers]megadriv.c

src/mame/drivers/megadriv.c
r9408r9409
39963996
399739970 = Main CPU Accesses WordRam0 (1st Half of WordRAM)
39983998    Sub CPU  Accesses WordRam1 (2nd Half of WordRAM)
3999   
3999
400040001 = Main CPU Accesses WordRam1 (2nd Half of WordRAM)
40014001    Sub  CPU Accesses WordRam0 (1st Half of WordRAM)
4002   
4002
40034003DMNA
40044004
40054005Setting this bis sends a Swap request to the SUB-CPU (Main CPU access only?)
r9408r9409
40234023         //printf("dmna set (swap requested)\n"); // give ram to sub?
40244024
40254025         // this should take some time?
4026         
4026
40274027         //segacd_ret = 1;
40284028
4029         //printf("main cpu dmna set dmna: %d ret: %d\n", segacd_dmna, segacd_ret);
4029         //printf("main cpu dmna set dmna: %d ret: %d\n", segacd_dmna, segacd_ret);
40304030         if (segacd_ram_mode==0)
40314031         {
40324032            if (!timer_enabled(segacd_dmna_ret_timer))
r9408r9409
40914091      {
40924092         //printf("ret bit set\n");
40934093         //segacd_dmna = 0;
4094         
40954094
4096         //printf("sub cpu ret set dmna: %d ret: %d\n", segacd_dmna, segacd_ret);
40974095
4096         //printf("sub cpu ret set dmna: %d ret: %d\n", segacd_dmna, segacd_ret);
4097
40984098         if (segacd_ram_mode==0)
40994099         {
41004100            if (!timer_enabled(segacd_dmna_ret_timer))
r9408r9409
44484448      }
44494449      else
44504450      {
4451         printf("Unspported: segacd_main_dataram_part1_r (Cell rearranged RAM) in mode 1\n");
4451         printf("Unspported: segacd_main_dataram_part1_r (Cell rearranged RAM) in mode 1\n");
44524452         return 0x0000;
4453      }     
4453      }
44544454   }
44554455
44564456   return 0x0000;
r9408r9409
44704470      {
44714471         printf("Illegal: segacd_main_dataram_part1_w in mode 0 without permission\n");
44724472      }
4473   
4473
44744474   }
44754475   else if (segacd_ram_mode==1)
44764476   {
r9408r9409
44784478      {
44794479         //printf("Unspported: segacd_main_dataram_part1_w (word RAM) in mode 1\n");
44804480         // wordram accees
4481     
4481
44824482         // ret bit set by sub cpu determines which half of WorkRAM we have access to?
44834483         if (segacd_ret)
44844484         {
r9408r9409
44924492      else
44934493      {
44944494         printf("Unspported: segacd_main_dataram_part1_w (Cell rearranged RAM) in mode 1 (illega?)\n"); // is this legal??
4495      }     
4495      }
44964496   }
44974497}
44984498
r9408r9409
48574857{
48584858   const int tilesize = 4; // 0xf pixels
48594859   const int tilemapsize = 0x0f;
4860   
4860
48614861   int wraparound = segacd_stampsize&1;
4862   
4862
48634863   int xtile = xpos / (1<<tilesize);
48644864   int ytile = ypos / (1<<tilesize);
48654865
r9408r9409
48734873   {
48744874      if (xtile>tilemapsize) return 0;
48754875      if (xtile<0) return 0;
4876     
4876
48774877      if (ytile>tilemapsize) return 0;
48784878      if (ytile<0) return 0;
48794879   }
r9408r9409
48934893{
48944894   const int tilesize = 5; // 0x1f pixels
48954895   const int tilemapsize = 0x07;
4896   
4896
48974897   int wraparound = segacd_stampsize&1;
4898   
4898
48994899   int xtile = xpos / (1<<tilesize);
49004900   int ytile = ypos / (1<<tilesize);
49014901
r9408r9409
49094909   {
49104910      if (xtile>tilemapsize) return 0;
49114911      if (xtile<0) return 0;
4912     
4912
49134913      if (ytile>tilemapsize) return 0;
49144914      if (ytile<0) return 0;
49154915   }
4916   
4916
49174917   int tile_index = (ytile * (tilemapsize+1)) + xtile;
4918   
4918
49194919   int tile_region, tileno;
49204920   SCD_GET_TILE_INFO_32x32_1x1(tile_region,tileno,(int)tile_index);
49214921
r9408r9409
49294929{
49304930   const int tilesize = 4; // 0xf pixels
49314931   const int tilemapsize = 0xff;
4932   
4932
49334933   int wraparound = segacd_stampsize&1;
4934   
4934
49354935   int xtile = xpos / (1<<tilesize);
49364936   int ytile = ypos / (1<<tilesize);
49374937
r9408r9409
49454945   {
49464946      if (xtile>tilemapsize) return 0;
49474947      if (xtile<0) return 0;
4948     
4948
49494949      if (ytile>tilemapsize) return 0;
49504950      if (ytile<0) return 0;
49514951   }
r9408r9409
49654965{
49664966   const int tilesize = 5; // 0x1f pixels
49674967   const int tilemapsize = 0x7f;
4968   
4968
49694969   int wraparound = segacd_stampsize&1;
4970   
4970
49714971   int xtile = xpos / (1<<tilesize);
49724972   int ytile = ypos / (1<<tilesize);
49734973
r9408r9409
49814981   {
49824982      if (xtile>tilemapsize) return 0;
49834983      if (xtile<0) return 0;
4984     
4984
49854985      if (ytile>tilemapsize) return 0;
49864986      if (ytile<0) return 0;
49874987   }
4988   
4988
49894989   int tile_index = (ytile * (tilemapsize+1)) + xtile;
4990   
4990
49914991   int tile_region, tileno;
49924992   SCD_GET_TILE_INFO_32x32_16x16(tile_region,tileno,(int)tile_index);
49934993
r9408r9409
52595259   }
52605260}
52615261
5262static void cdd_hock_irq(running_machine *machine,UINT8 dir)
5262static TIMER_CALLBACK( execute_hock_irq )
52635263{
52645264   int i,cdd_crc;
52655265
5266   if((segacd_cdd.ctrl & 4 || dir) && segacd_irq_mask & 0x10) // export status, check if bit 2 (HOst ClocK) and irq is enabled
5267   {
5268      // TODO: this shouldn't be instant, CDD should first fill receive data.
5269      segacd_cdd.ctrl &= 0x103; // clear HOCK flag
5266   segacd_cdd.ctrl &= ~4; // clear HOCK flag
52705267
5271      segacd_cdd_rx[0] = (segacd_cdd.status & 0xf0) >> 4;
5272      segacd_cdd_rx[1] = (segacd_cdd.status & 0x0f) >> 0;
5273      segacd_cdd_rx[2] = (segacd_cdd.minute & 0xf0) >> 4;
5274      segacd_cdd_rx[3] = (segacd_cdd.minute & 0x0f) >> 0;
5275      segacd_cdd_rx[4] = (segacd_cdd.seconds & 0xf0) >> 4;
5276      segacd_cdd_rx[5] = (segacd_cdd.seconds & 0x0f) >> 0;
5277      segacd_cdd_rx[6] = (segacd_cdd.frame & 0xf0) >> 4;
5278      segacd_cdd_rx[7] = (segacd_cdd.frame & 0x0f) >> 0;
5279      segacd_cdd_rx[8] = (segacd_cdd.ext & 0x0f) >> 0;
5268   segacd_cdd_rx[0] = (segacd_cdd.status & 0xf0) >> 4;
5269   segacd_cdd_rx[1] = (segacd_cdd.status & 0x0f) >> 0;
5270   segacd_cdd_rx[2] = (segacd_cdd.minute & 0xf0) >> 4;
5271   segacd_cdd_rx[3] = (segacd_cdd.minute & 0x0f) >> 0;
5272   segacd_cdd_rx[4] = (segacd_cdd.seconds & 0xf0) >> 4;
5273   segacd_cdd_rx[5] = (segacd_cdd.seconds & 0x0f) >> 0;
5274   segacd_cdd_rx[6] = (segacd_cdd.frame & 0xf0) >> 4;
5275   segacd_cdd_rx[7] = (segacd_cdd.frame & 0x0f) >> 0;
5276   segacd_cdd_rx[8] = (segacd_cdd.ext & 0x0f) >> 0;
52805277
5281      /* Do checksum calculation of the above registers */
5282      cdd_crc = 0;
5283      for(i=0;i<9;i++)
5284         cdd_crc += segacd_cdd_rx[i];
5278   /* Do checksum calculation of the above registers */
5279   cdd_crc = 0;
5280   for(i=0;i<9;i++)
5281      cdd_crc += segacd_cdd_rx[i];
52855282
5286      segacd_cdd_rx[9] = ((cdd_crc & 0xf) ^ 0xf);
5283   segacd_cdd_rx[9] = ((cdd_crc & 0xf) ^ 0xf);
52875284
5288      cputag_set_input_line(machine, "segacd_68k", 4, HOLD_LINE);
5285   cputag_set_input_line(machine, "segacd_68k", 4, HOLD_LINE);
5286}
5287
5288static void cdd_hock_irq(running_machine *machine,UINT8 dir)
5289{
5290   if((segacd_cdd.ctrl & 4 || dir) && segacd_irq_mask & 0x10) // export status, check if bit 2 (HOst ClocK) and irq is enabled
5291   {
5292      segacd_cdd.ctrl |= 4; // enable Hock bit if it isn't already active
5293      timer_set(machine, ATTOTIME_IN_HZ(75), NULL,0, execute_hock_irq); // 1 / 75th of a second
52895294   }
52905295}
52915296
r9408r9409
53635368{
53645369   // ...
53655370
5366   /*segacd_cdd.status = 0;
5371   segacd_cdd.status = 0;
53675372   segacd_cdd.minute = 0;
53685373   segacd_cdd.seconds = 0;
53695374   segacd_cdd.frame = 0;
5370   segacd_cdd.ext = 0;*/
5375   segacd_cdd.ext = 0;
53715376
53725377   cdd_hock_irq(machine,1);
53735378}
r9408r9409
53825387   segacd_cdd.frame = 0;
53835388   segacd_cdd.ext = 0;
53845389
5385   //cdd_hock_irq(machine,1); // doesn't work?
5390   cdd_hock_irq(machine,1);
53865391}
53875392
53885393
r9408r9409
55205525
55215526   if (x >= srcbitmap->width) return 0;
55225527   if (y >= srcbitmap->height) return 0;
5523   
5528
55245529   UINT16* cacheptr = BITMAP_ADDR16( srcbitmap, y, x);
55255530
55265531   return cacheptr[0] & 0xf;
r9408r9409
55335538      case 0x02: return get_stampmap_16x16_16x16_tile_info_pixel( machine, x, y );
55345539      case 0x03: return get_stampmap_32x32_16x16_tile_info_pixel( machine, x, y );
55355540   }
5536   
5541
55375542   return 0;
55385543}
55395544
r9408r9409
55455550   UINT32 offset;
55465551
55475552   offset = bufferstart+(((segacd_imagebuffer_vcell_size+1)*0x10)*xpos);
5548   
5553
55495554   // lines of each output cell
55505555   offset+= (line*2);
5551         
5556
55525557   while (offset>=bufferend)
55535558      offset-= bufferend;
5554   
5555   
5559
5560
55565561   switch (segacd_memory_priority_mode)
55575562   {
55585563      case 0x00: // normal write, just write the data
55595564         segacd_dataram[offset] = pix >> 16;
55605565         segacd_dataram[offset+1] = pix & 0xffff;
55615566         break;
5562         
5567
55635568      case 0x01: // underwrite, only write if the existing data is 0
55645569         if ((segacd_dataram[offset]&0xf000) == 0x0000) segacd_dataram[offset] |= (pix>>16)&0xf000;
55655570         if ((segacd_dataram[offset]&0x0f00) == 0x0000) segacd_dataram[offset] |= (pix>>16)&0x0f00;
r9408r9409
55705575         if ((segacd_dataram[offset+1]&0x00f0) == 0x0000) segacd_dataram[offset+1] |= (pix)&0x00f0;
55715576         if ((segacd_dataram[offset+1]&0x000f) == 0x0000) segacd_dataram[offset+1] |= (pix)&0x000f;
55725577         break;
5573         
5578
55745579      case 0x02: // overwrite, only write non-zero data
55755580         if ((pix>>16)&0xf000) segacd_dataram[offset] = (segacd_dataram[offset] & 0x0fff) | ((pix>>16)&0xf000);
55765581         if ((pix>>16)&0x0f00) segacd_dataram[offset] = (segacd_dataram[offset] & 0xf0ff) | ((pix>>16)&0x0f00);
r9408r9409
55815586         if ((pix)&0x00f0) segacd_dataram[offset+1] = (segacd_dataram[offset+1] & 0xff0f) | ((pix)&0x00f0);
55825587         if ((pix)&0x000f) segacd_dataram[offset+1] = (segacd_dataram[offset+1] & 0xfff0) | ((pix)&0x000f);
55835588         break;
5584         
5589
55855590      default:
55865591      case 0x03: // invalid?
55875592         segacd_dataram[offset] = mame_rand(machine);
55885593         segacd_dataram[offset+1] = mame_rand(machine);
55895594         break;
5590   
5595
55915596   }
5592   
5597
55935598   segacd_mark_tiles_dirty(machine, offset);
55945599   segacd_mark_tiles_dirty(machine, offset+1);
55955600
r9408r9409
56265631      for (line=0;line<segacd_imagebuffer_vdot_size;line++)
56275632      {
56285633         int currbase = base + line * 0x8;
5629         
5634
56305635         // are the 256x256 tile modes using the same sign bits?
56315636         INT16 tilemapxoffs,tilemapyoffs;
56325637         INT16 deltax,deltay;
5633         
5638
56345639         tilemapxoffs = segacd_dataram[(currbase+0x0)>>1];
56355640         tilemapyoffs = segacd_dataram[(currbase+0x2)>>1];
56365641         deltax = segacd_dataram[(currbase+0x4)>>1]; // x-zoom
r9408r9409
56415646         int xbase = tilemapxoffs * 256;
56425647         int ybase = tilemapyoffs * 256;
56435648         int count;
5644                 
5649
56455650         for (count=0;count<(segacd_imagebuffer_hdot_size>>3);count++)
56465651         {
56475652            int i;
56485653            UINT32 pixblock = 0x00000000;
56495654            for (i=7*4;i>=0;i-=4)
5650            {   
5655            {
56515656               pixblock |= read_pixel_from_stampmap(space->machine, srcbitmap, xbase>>(3+8), ybase>>(3+8)) << (i);
5652               
5653               
5657
5658
56545659               xbase += deltax;
56555660               ybase += deltay;
5656               
5661
56575662               // clamp to 24-bits, seems to be required for all the intro effects to work
56585663               xbase &= 0xffffff;
56595664               ybase &= 0xffffff;
5660               
56615665
5666
56625667            }
5663           
5664           
5665           
5666           
5668
5669
5670
5671
56675672            write_pixel_to_imagebuffer(space->machine, pixblock, line, count);
56685673         }
56695674
r9408r9409
57775782{
57785783   if (segacd_irq_mask & 0x08)
57795784      cputag_set_input_line(machine, "segacd_68k", 3, HOLD_LINE);
5780     
5785
57815786   timer_adjust_oneshot(segacd_irq3_timer, SEGACD_IRQ3_TIMER_SPEED, 0);
57825787}
57835788
r9408r9409
57925797
57935798   AM_RANGE(0xff0000, 0xff001f) AM_DEVWRITE8("rfsnd", rf5c68_w, 0x00ff)  // PCM, RF5C164
57945799   AM_RANGE(0xff2000, 0xff3fff) AM_DEVREADWRITE8("rfsnd", rf5c68_mem_r, rf5c68_mem_w,0x00ff)  // PCM, RF5C164
5795   
5796   
5800
5801
57975802   AM_RANGE(0xff8000 ,0xff8001) AM_READWRITE(segacd_sub_led_ready_r, segacd_sub_led_ready_w)
57985803   AM_RANGE(0xff8002 ,0xff8003) AM_READWRITE(segacd_sub_memory_mode_r, segacd_sub_memory_mode_w)
57995804

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