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r9407 Sunday 17th October, 2010 at 20:03:03 UTC by Angelo Salese
[Mega CD]: Improved dmna / ret behaviour, you can now enter into the cd player menu [David Haywood]
[src/mame/drivers]megadriv.c

src/mame/drivers/megadriv.c
r9406r9407
343343/* SegaCD! */
344344static cpu_device *_segacd_68k_cpu;
345345static emu_timer *segacd_gfx_conversion_timer;
346static emu_timer *segacd_dmna_ret_timer;
346347static emu_timer *segacd_irq3_timer;
347348static int segacd_wordram_mapped = 0;
348349static TIMER_CALLBACK( segacd_irq3_timer_callback );
r9406r9407
39193920// so probably don't change instantly...
39203921//
39213922
3923int segacd_dmna = 0;
3924int segacd_ret = 0;
3925
3926static TIMER_CALLBACK( segacd_dmna_ret_timer_callback )
3927{
3928
3929   // this is the initial state, and the state after changing modes?
3930   if ((segacd_dmna==0) && (segacd_ret ==0))
3931   {
3932      //printf("aaa %d %d\n", segacd_dmna, segacd_ret);
3933      segacd_dmna = 0;
3934      segacd_ret = 1;
3935      //printf("bbb %d %d\n", segacd_dmna, segacd_ret);
3936   }
3937   else if ((segacd_dmna==1) && (segacd_ret == 1))
3938   {
3939      //printf("aaa %d %d\n", segacd_dmna, segacd_ret);
3940      segacd_dmna = 1;
3941      segacd_ret = 0;
3942      //printf("bbb %d %d\n", segacd_dmna, segacd_ret);
3943   }
3944   else if ((segacd_dmna==1) && (segacd_ret == 0))
3945   {
3946      //printf("aaa %d %d\n", segacd_dmna, segacd_ret);
3947      segacd_dmna = 0;
3948      segacd_ret = 1;
3949      //printf("bbb %d %d\n", segacd_dmna, segacd_ret);
3950   }
3951   else
3952   {
3953      printf("huh? %d %d\n", segacd_dmna, segacd_ret);
3954   }
3955}
3956
3957
39223958static UINT8 segacd_ram_writeprotect_bits;
39233959static int segacd_ram_mode;
3960static int segacd_ram_mode_old;
39243961
3925static int segacd_maincpu_has_ram_access = 0;
3962//static int segacd_maincpu_has_ram_access = 0;
39263963static int segacd_4meg_prgbank = 0; // which bank the MainCPU can see of the SubCPU PrgRAM
39273964static int segacd_memory_priority_mode = 0;
39283965static int segacd_stampsize;
r9406r9407
39333970   return (segacd_ram_writeprotect_bits << 8) |
39343971         (segacd_4meg_prgbank << 6) |
39353972         (segacd_ram_mode << 2) |
3936         ((segacd_maincpu_has_ram_access^1) << 1) |
3937         ((segacd_maincpu_has_ram_access) << 0);
3973         ((segacd_dmna) << 1) |
3974         ((segacd_ret) << 0);
39383975}
39393976
39403977
39413978/* I'm still not 100% clear how this works, the sources I have are a bit vague,
39423979   it might still be incorrect in both modes
3980
3981  for a simple way to swap blocks of ram between cpus this is stupidly convoluted
3982
39433983 */
39443984
39453985// DMNA = Decleration Mainram No Access (bit 0)
r9406r9407
39834023         //printf("dmna set (swap requested)\n"); // give ram to sub?
39844024
39854025         // this should take some time?
3986         segacd_maincpu_has_ram_access = 0;
4026         
4027         //segacd_ret = 1;
4028
4029         //printf("main cpu dmna set dmna: %d ret: %d\n", segacd_dmna, segacd_ret);
4030         if (segacd_ram_mode==0)
4031         {
4032            if (!timer_enabled(segacd_dmna_ret_timer))
4033            {
4034               if (!segacd_dmna)
4035               {
4036                  //printf("main dmna\n");
4037                  segacd_dmna = 1;
4038                  timer_adjust_oneshot(segacd_dmna_ret_timer, ATTOTIME_IN_USEC(100), 0);
4039               }
4040            }
4041         }
4042         else
4043         {
4044            printf("dmna bit in mode 1\n");
4045         }
39874046      }
39884047
39894048
r9406r9407
40184077        /*(segacd_4meg_prgbank << 6) | */
40194078         (segacd_memory_priority_mode << 3) |
40204079         (segacd_ram_mode << 2) |
4021         ((segacd_maincpu_has_ram_access^1) << 1) |
4022         ((segacd_maincpu_has_ram_access) << 0);
4080         ((segacd_dmna) << 1) |
4081         ((segacd_ret) << 0);
40234082}
40244083
40254084static WRITE16_HANDLER( segacd_sub_memory_mode_w )
r9406r9407
40314090      if (data&0x0001)
40324091      {
40334092         //printf("ret bit set\n");
4034         segacd_maincpu_has_ram_access = 1;
4093         //segacd_dmna = 0;
4094         
4095
4096         //printf("sub cpu ret set dmna: %d ret: %d\n", segacd_dmna, segacd_ret);
4097
4098         if (segacd_ram_mode==0)
4099         {
4100            if (!timer_enabled(segacd_dmna_ret_timer))
4101            {
4102               if (segacd_dmna)
4103               {
4104               //   printf("sub ret\n");
4105               //   segacd_ret = 1;
4106               //   segacd_dmna = 0;
4107                  timer_adjust_oneshot(segacd_dmna_ret_timer, ATTOTIME_IN_USEC(100), 0);
4108               }
4109            }
4110         }
4111         else
4112         {
4113            // in mode 1 this changes the word ram 1 to main cpu and word ram 0 to sub cpu?
4114            // but should be proceeded by a dmna request? is this only valid if dmna has been
4115            // set to 1 by the main CPU first?
4116            printf("ret bit in mode 1\n");
4117            segacd_ret = 1;
4118         }
40354119      }
4120      else
4121      {
4122         // in mode 1 this changes the word ram 0 to main cpu and word ram 1 to sub cpu?
4123         // but should be proceeded by a dmna request? is this only valid if dmna has been
4124         // set to 1 by the main CPU first?
4125         if (segacd_ram_mode==1)
4126         {
4127            segacd_ret = 0;
4128         }
4129      }
40364130
40374131
40384132      //if (data&0x0002) printf("dmna set (swap requested) (invalid, can't be set from sub68k?\n");
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40404134      //if (data&0x0004)
40414135      {
40424136         segacd_ram_mode = (data&0x0004)>>2;
4043         //printf("mode set %d\n", segacd_ram_mode);
4137         if (segacd_ram_mode!=segacd_ram_mode_old)
4138         {
4139            printf("mode set %d\n", segacd_ram_mode);
4140            segacd_ram_mode_old = segacd_ram_mode;
4141
4142            if (segacd_ram_mode==0)
4143            {
4144               // reset it flags etc.?
4145               segacd_ret = 0;
4146               segacd_dmna = 0;
4147               timer_adjust_oneshot(segacd_dmna_ret_timer, ATTOTIME_IN_USEC(100), 0);
4148            }
4149            else
4150            {
4151               segacd_ret = 0;
4152               segacd_dmna = 0;
4153
4154
4155            }
4156         }
40444157      }
40454158
40464159      //if (data&0x0018)
r9406r9407
43004413   if (segacd_ram_mode==0)
43014414   {
43024415      // is this correct?
4303      if (segacd_maincpu_has_ram_access)
4416      if (!segacd_dmna)
43044417      {
43054418         //printf("segacd_main_dataram_part1_r in mode 0 %08x %04x\n", offset*2, segacd_dataram[offset]);
43064419
43074420         return segacd_dataram[offset];
43084421
43094422      }
4423      /*
43104424      else
43114425      {
43124426         printf("Illegal: segacd_main_dataram_part1_r in mode 0 without permission\n");
43134427         return 0xffff;
43144428      }
4429      */
43154430   }
43164431   else if (segacd_ram_mode==1)
43174432   {
r9406r9407
43374452   if (segacd_ram_mode==0)
43384453   {
43394454      // is this correct?
4340      if (segacd_maincpu_has_ram_access)
4455      if (!segacd_dmna)
43414456      {
43424457         COMBINE_DATA(&segacd_dataram[offset]);
43434458         segacd_mark_tiles_dirty(space->machine, offset);
43444459      }
4460      /*
43454461      else
43464462      {
43474463         printf("Illegal: segacd_main_dataram_part1_w in mode 0 without permission\n");
43484464      }
4465      */
43494466   }
43504467   else if (segacd_ram_mode==1)
43514468   {
r9406r9407
49025019   segacd_gfx_conversion_timer = timer_alloc(machine, segacd_gfx_conversion_timer_callback, 0);
49035020   timer_adjust_oneshot(segacd_gfx_conversion_timer, attotime_never, 0);
49045021
5022   segacd_dmna_ret_timer = timer_alloc(machine, segacd_dmna_ret_timer_callback, 0);
5023   timer_adjust_oneshot(segacd_gfx_conversion_timer, attotime_never, 0);
5024
5025
49055026   segacd_irq3_timer = timer_alloc(machine, segacd_irq3_timer_callback, 0);
49065027   timer_adjust_oneshot(segacd_irq3_timer, attotime_never, 0);
49075028
r9406r9407
49755096      }
49765097   }
49775098   #endif
5099
5100   segacd_dmna = 0;
5101   segacd_ret = 0;
5102
5103   segacd_ram_mode = 0;
5104   segacd_ram_mode_old = 0;
5105
5106   timer_adjust_oneshot(segacd_dmna_ret_timer, attotime_zero, 0);
49785107}
49795108
49805109
r9406r9407
50275156   if (segacd_ram_mode==0)
50285157   {
50295158      // is this correct?
5030      if (!segacd_maincpu_has_ram_access)
5159      if (segacd_dmna)
50315160         return segacd_dataram[offset];
50325161      else
50335162      {
r9406r9407
50495178   if (segacd_ram_mode==0)
50505179   {
50515180      // is this correct?
5052      if (!segacd_maincpu_has_ram_access)
5181      if (segacd_dmna)
50535182      {
50545183         COMBINE_DATA(&segacd_dataram[offset]);
50555184         segacd_mark_tiles_dirty(space->machine, offset);
r9406r9407
54505579      segacd_conversion_active = 1;
54515580
54525581      // todo: proper time calculation
5453      timer_adjust_oneshot(segacd_gfx_conversion_timer, ATTOTIME_IN_HZ(1000), 0);
5582      timer_adjust_oneshot(segacd_gfx_conversion_timer, ATTOTIME_IN_HZ(500), 0);
54545583
54555584
54565585      int line;

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