src/mess/machine/mbee.c
| r9403 | r9404 | |
| 138 | 138 | wd17xx_set_drive(mbee_fdc, data & 3); |
| 139 | 139 | wd17xx_set_side(mbee_fdc, (data & 4) ? 1 : 0); |
| 140 | 140 | wd17xx_dden_w(mbee_fdc, !BIT(data, 3)); |
| 141 | /* no idea what turns the motors on & off, guessing it could be drive select |
| 142 | commented out because it prevents 128k and 256TC from booting up */ |
| 143 | //floppy_mon_w(floppy_get_device(space->machine, data & 3), CLEAR_LINE); // motor on |
| 141 | 144 | } |
| 142 | 145 | |
| 143 | 146 | /*********************************************************** |
| r9403 | r9404 | |
| 578 | 581 | // Due to the uncertainly and hackage here, this is commented out for now - Robbbert - 05-Oct-2010 |
| 579 | 582 | #if 0 |
| 580 | 583 | |
| 581 | | address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM); |
| 582 | | /* once per frame, pulse the PIO B bit 7 - it is in the schematic as an option, |
| 583 | | but need to find out what it does */ |
| 584 | | mbee_clock_pulse = 0x80; |
| 585 | | |
| 584 | //address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM); |
| 586 | 585 | /* The printer status connects to the pio ASTB pin, and the printer changing to not |
| 587 | 586 | busy should signal an interrupt routine at B61C, (next line) but this doesn't work. |
| 588 | 587 | The line below does what the interrupt should be doing. */ |
| 589 | 588 | /* But it would break any program loaded to that area of memory, such as CP/M programs */ |
| 590 | 589 | |
| 591 | | z80pio_astb_w( mbee_z80pio, centronics_busy_r(mbee_printer)); /* signal int when not busy (L->H) */ |
| 590 | //z80pio_astb_w( mbee_z80pio, centronics_busy_r(mbee_printer)); /* signal int when not busy (L->H) */ |
| 591 | //space->write_byte(0x109, centronics_busy_r(mbee_printer)); |
| 592 | 592 | |
| 593 | | space->write_byte(0x109, centronics_busy_r(mbee_printer)); |
| 593 | |
| 594 | /* once per frame, pulse the PIO B bit 7 - it is in the schematic as an option, |
| 595 | but need to find out what it does */ |
| 596 | mbee_clock_pulse = 0x80; |
| 597 | irq0_line_hold(device); |
| 598 | |
| 594 | 599 | #endif |
| 595 | 600 | } |
| 596 | 601 | |
| 597 | 602 | DRIVER_INIT( mbee ) |
| 598 | 603 | { |
| 599 | 604 | UINT8 *RAM = memory_region(machine, "maincpu"); |
| 600 | | memory_configure_bank(machine, "boot", 0, 2, &RAM[0x0000], 0x8000); |
| 605 | memory_configure_bank(machine, "boot", 0, 2, &RAM[0x0000], 0x8000); |
| 601 | 606 | mbee_size = 0x4000; |
| 602 | 607 | } |
| 603 | 608 | |
| 604 | 609 | DRIVER_INIT( mbeeic ) |
| 605 | 610 | { |
| 606 | 611 | UINT8 *RAM = memory_region(machine, "maincpu"); |
| 607 | | memory_configure_bank(machine, "boot", 0, 2, &RAM[0x0000], 0x8000); |
| 612 | memory_configure_bank(machine, "boot", 0, 2, &RAM[0x0000], 0x8000); |
| 608 | 613 | |
| 609 | 614 | RAM = memory_region(machine, "pakrom"); |
| 610 | 615 | memory_configure_bank(machine, "pak", 0, 16, &RAM[0x0000], 0x2000); |
| r9403 | r9404 | |
| 616 | 621 | DRIVER_INIT( mbeepc ) |
| 617 | 622 | { |
| 618 | 623 | UINT8 *RAM = memory_region(machine, "maincpu"); |
| 619 | | memory_configure_bank(machine, "boot", 0, 2, &RAM[0x0000], 0x8000); |
| 624 | memory_configure_bank(machine, "boot", 0, 2, &RAM[0x0000], 0x8000); |
| 620 | 625 | |
| 621 | 626 | RAM = memory_region(machine, "telcomrom"); |
| 622 | 627 | memory_configure_bank(machine, "telcom", 0, 2, &RAM[0x0000], 0x1000); |
| r9403 | r9404 | |
| 632 | 637 | DRIVER_INIT( mbeepc85 ) |
| 633 | 638 | { |
| 634 | 639 | UINT8 *RAM = memory_region(machine, "maincpu"); |
| 635 | | memory_configure_bank(machine, "boot", 0, 2, &RAM[0x0000], 0x8000); |
| 640 | memory_configure_bank(machine, "boot", 0, 2, &RAM[0x0000], 0x8000); |
| 636 | 641 | |
| 637 | 642 | RAM = memory_region(machine, "telcomrom"); |
| 638 | 643 | memory_configure_bank(machine, "telcom", 0, 2, &RAM[0x0000], 0x1000); |
| r9403 | r9404 | |
| 669 | 674 | DRIVER_INIT( mbee56 ) |
| 670 | 675 | { |
| 671 | 676 | UINT8 *RAM = memory_region(machine, "maincpu"); |
| 672 | | memory_configure_bank(machine, "boot", 0, 2, &RAM[0x0000], 0xe000); |
| 677 | memory_configure_bank(machine, "boot", 0, 2, &RAM[0x0000], 0xe000); |
| 673 | 678 | mbee_size = 0xe000; |
| 674 | 679 | } |
| 675 | 680 | |
| 676 | 681 | DRIVER_INIT( mbee64 ) |
| 677 | 682 | { |
| 678 | 683 | UINT8 *RAM = memory_region(machine, "maincpu"); |
| 679 | | memory_configure_bank(machine, "boot", 0, 1, &RAM[0x0000], 0x0000); |
| 680 | | memory_configure_bank(machine, "bankl", 0, 1, &RAM[0x1000], 0x0000); |
| 681 | | memory_configure_bank(machine, "bankl", 1, 1, &RAM[0x9000], 0x0000); |
| 682 | | memory_configure_bank(machine, "bankh", 0, 1, &RAM[0x8000], 0x0000); |
| 684 | memory_configure_bank(machine, "boot", 0, 1, &RAM[0x0000], 0x0000); |
| 685 | memory_configure_bank(machine, "bankl", 0, 1, &RAM[0x1000], 0x0000); |
| 686 | memory_configure_bank(machine, "bankl", 1, 1, &RAM[0x9000], 0x0000); |
| 687 | memory_configure_bank(machine, "bankh", 0, 1, &RAM[0x8000], 0x0000); |
| 683 | 688 | |
| 684 | 689 | RAM = memory_region(machine, "bootrom"); |
| 685 | 690 | memory_configure_bank(machine, "bankh", 1, 1, &RAM[0x0000], 0x0000); |
| r9403 | r9404 | |
| 691 | 696 | DRIVER_INIT( mbee128 ) |
| 692 | 697 | { |
| 693 | 698 | UINT8 *RAM = memory_region(machine, "maincpu"); |
| 694 | | memory_configure_bank(machine, "boot", 0, 4, &RAM[0x0000], 0x8000); // standard banks 0000 |
| 695 | | memory_configure_bank(machine, "bank1", 0, 4, &RAM[0x1000], 0x8000); // standard banks 1000 |
| 696 | | memory_configure_bank(machine, "bank8l", 1, 1, &RAM[0x0000], 0x0000); // shadow ram |
| 697 | | memory_configure_bank(machine, "bank8h", 1, 1, &RAM[0x0800], 0x0000); // shadow ram |
| 698 | | memory_configure_bank(machine, "bank9", 1, 1, &RAM[0x1000], 0x0000); // shadow ram |
| 699 | | memory_configure_bank(machine, "bankfl", 0, 1, &RAM[0xf000], 0x0000); // shadow ram |
| 700 | | memory_configure_bank(machine, "bankfh", 0, 1, &RAM[0xf800], 0x0000); // shadow ram |
| 699 | memory_configure_bank(machine, "boot", 0, 4, &RAM[0x0000], 0x8000); // standard banks 0000 |
| 700 | memory_configure_bank(machine, "bank1", 0, 4, &RAM[0x1000], 0x8000); // standard banks 1000 |
| 701 | memory_configure_bank(machine, "bank8l", 1, 1, &RAM[0x0000], 0x0000); // shadow ram |
| 702 | memory_configure_bank(machine, "bank8h", 1, 1, &RAM[0x0800], 0x0000); // shadow ram |
| 703 | memory_configure_bank(machine, "bank9", 1, 1, &RAM[0x1000], 0x0000); // shadow ram |
| 704 | memory_configure_bank(machine, "bankfl", 0, 1, &RAM[0xf000], 0x0000); // shadow ram |
| 705 | memory_configure_bank(machine, "bankfh", 0, 1, &RAM[0xf800], 0x0000); // shadow ram |
| 701 | 706 | |
| 702 | 707 | RAM = memory_region(machine, "bootrom"); |
| 703 | 708 | memory_configure_bank(machine, "bank9", 0, 1, &RAM[0x1000], 0x0000); // rom |
| 704 | 709 | memory_configure_bank(machine, "boot", 4, 1, &RAM[0x0000], 0x0000); // rom at boot for 4usec |
| 705 | | memory_configure_bank(machine, "bank8l", 0, 1, &RAM[0x0000], 0x0000); // rom |
| 706 | | memory_configure_bank(machine, "bank8h", 0, 1, &RAM[0x0800], 0x0000); // rom |
| 710 | memory_configure_bank(machine, "bank8l", 0, 1, &RAM[0x0000], 0x0000); // rom |
| 711 | memory_configure_bank(machine, "bank8h", 0, 1, &RAM[0x0800], 0x0000); // rom |
| 707 | 712 | |
| 708 | 713 | mbee_size = 0x8000; |
| 709 | 714 | } |
| r9403 | r9404 | |
| 711 | 716 | DRIVER_INIT( mbee256 ) |
| 712 | 717 | { |
| 713 | 718 | UINT8 *RAM = memory_region(machine, "maincpu"); |
| 714 | | memory_configure_bank(machine, "boot", 0, 8, &RAM[0x0000], 0x8000); // standard banks 0000 |
| 715 | | memory_configure_bank(machine, "bank1", 0, 8, &RAM[0x1000], 0x8000); // standard banks 1000 |
| 716 | | memory_configure_bank(machine, "bank8l", 1, 1, &RAM[0x0000], 0x0000); // shadow ram |
| 717 | | memory_configure_bank(machine, "bank8h", 1, 1, &RAM[0x0800], 0x0000); // shadow ram |
| 718 | | memory_configure_bank(machine, "bank9", 1, 1, &RAM[0x1000], 0x0000); // shadow ram |
| 719 | | memory_configure_bank(machine, "bankfl", 0, 1, &RAM[0xf000], 0x0000); // shadow ram |
| 720 | | memory_configure_bank(machine, "bankfh", 0, 1, &RAM[0xf800], 0x0000); // shadow ram |
| 719 | memory_configure_bank(machine, "boot", 0, 8, &RAM[0x0000], 0x8000); // standard banks 0000 |
| 720 | memory_configure_bank(machine, "bank1", 0, 8, &RAM[0x1000], 0x8000); // standard banks 1000 |
| 721 | memory_configure_bank(machine, "bank8l", 1, 1, &RAM[0x0000], 0x0000); // shadow ram |
| 722 | memory_configure_bank(machine, "bank8h", 1, 1, &RAM[0x0800], 0x0000); // shadow ram |
| 723 | memory_configure_bank(machine, "bank9", 1, 1, &RAM[0x1000], 0x0000); // shadow ram |
| 724 | memory_configure_bank(machine, "bankfl", 0, 1, &RAM[0xf000], 0x0000); // shadow ram |
| 725 | memory_configure_bank(machine, "bankfh", 0, 1, &RAM[0xf800], 0x0000); // shadow ram |
| 721 | 726 | |
| 722 | 727 | RAM = memory_region(machine, "bootrom"); |
| 723 | 728 | memory_configure_bank(machine, "bank9", 0, 1, &RAM[0x1000], 0x0000); // rom |
| 724 | 729 | memory_configure_bank(machine, "boot", 8, 1, &RAM[0x0000], 0x0000); // rom at boot for 4usec |
| 725 | | memory_configure_bank(machine, "bank8l", 0, 1, &RAM[0x0000], 0x0000); // rom |
| 726 | | memory_configure_bank(machine, "bank8h", 0, 1, &RAM[0x0800], 0x0000); // rom |
| 730 | memory_configure_bank(machine, "bank8l", 0, 1, &RAM[0x0000], 0x0000); // rom |
| 731 | memory_configure_bank(machine, "bank8h", 0, 1, &RAM[0x0800], 0x0000); // rom |
| 727 | 732 | |
| 728 | 733 | timer_pulse(machine, ATTOTIME_IN_HZ(1),NULL,0,mbee_rtc_irq); /* timer for rtc */ |
| 729 | 734 | timer_pulse(machine, ATTOTIME_IN_HZ(25),NULL,0,mbee256_kbd); /* timer for kbd */ |