src/mame/drivers/megadriv.c
| r9293 | r9294 | |
|---|
| 3687 | 3687 | *************************************************************************************************/ |
| 3688 | 3688 | |
| 3689 | 3689 | static UINT16* segacd_4meg_prgram; // pointer to SubCPU PrgRAM |
| 3690 | |
| 3691 | |
| 3692 | static UINT16 a12000_halt_reset_reg = 0x0000; |
| 3693 | |
| 3694 | static WRITE16_HANDLER( scd_a12000_halt_reset_w ) |
| 3695 | { |
| 3696 | COMBINE_DATA(&a12000_halt_reset_reg); |
| 3697 | |
| 3698 | if (ACCESSING_BITS_0_7) |
| 3699 | { |
| 3700 | // reset line |
| 3701 | if (a12000_halt_reset_reg&0x0001) |
| 3702 | cputag_set_input_line(space->machine, "segacd_68k", INPUT_LINE_RESET, CLEAR_LINE); |
| 3703 | else |
| 3704 | cputag_set_input_line(space->machine, "segacd_68k", INPUT_LINE_RESET, ASSERT_LINE); |
| 3705 | |
| 3706 | // request BUS |
| 3707 | if (a12000_halt_reset_reg&0x0002) |
| 3708 | cputag_set_input_line(space->machine, "segacd_68k", INPUT_LINE_HALT, ASSERT_LINE); |
| 3709 | else |
| 3710 | cputag_set_input_line(space->machine, "segacd_68k", INPUT_LINE_HALT, CLEAR_LINE); |
| 3711 | } |
| 3712 | |
| 3713 | if (ACCESSING_BITS_8_15) |
| 3714 | { |
| 3715 | if (a12000_halt_reset_reg&0x0100) |
| 3716 | { |
| 3717 | // check if it's masked! (irq check function?) |
| 3718 | cputag_set_input_line(space->machine, "segacd_68k", 2, ASSERT_LINE); |
| 3719 | } |
| 3720 | |
| 3721 | if (a12000_halt_reset_reg&0x8000) |
| 3722 | { |
| 3723 | printf("a12000_halt_reset_reg & 0x8000 set\n"); // irq2 mask? |
| 3724 | } |
| 3725 | |
| 3726 | |
| 3727 | } |
| 3728 | } |
| 3729 | |
| 3730 | static READ16_HANDLER( scd_a12000_halt_reset_r ) |
| 3731 | { |
| 3732 | return a12000_halt_reset_reg; |
| 3733 | } |
| 3734 | |
| 3735 | |
| 3736 | /******************************************************************************** |
| 3737 | MEMORY MODE CONTROL |
| 3738 | - main / sub sides differ! |
| 3739 | ********************************************************************************/ |
| 3740 | |
| 3741 | // |
| 3742 | // we might need a delay on the segacd_maincpu_has_ram_access registers, as they actually indicate requests being made |
| 3743 | // so probably don't change instantly... |
| 3744 | // |
| 3745 | |
| 3746 | static UINT8 segacd_ram_writeprotect_bits; |
| 3747 | static int segacd_ram_mode; |
| 3748 | |
| 3749 | static int segacd_maincpu_has_ram_access = 0; |
| 3690 | 3750 | static int segacd_4meg_prgbank = 0; // which bank the MainCPU can see of the SubCPU PrgRAM |
| 3751 | static int segacd_memory_priority_mode = 0; |
| 3691 | 3752 | |
| 3692 | 3753 | |
| 3754 | static READ16_HANDLER( scd_a12002_memory_mode_r ) |
| 3755 | { |
| 3756 | return (segacd_ram_writeprotect_bits << 8) | |
| 3757 | (segacd_4meg_prgbank << 6) | |
| 3758 | (segacd_ram_mode << 2) | |
| 3759 | ((segacd_maincpu_has_ram_access^1) << 1) | |
| 3760 | ((segacd_maincpu_has_ram_access) << 0); |
| 3761 | } |
| 3762 | |
| 3763 | static WRITE16_HANDLER( scd_a12002_memory_mode_w ) |
| 3764 | { |
| 3765 | printf("scd_a12002_memory_mode_w %04x %04x\n", data, mem_mask); |
| 3766 | |
| 3767 | if (ACCESSING_BITS_0_7) |
| 3768 | { |
| 3769 | |
| 3770 | if (data&0x0001) printf("ret bit set (invalid? can't set from main68k?)\n"); |
| 3771 | if (data&0x0002) |
| 3772 | { |
| 3773 | printf("dmn set (swap requested)\n"); // give ram to sub? |
| 3774 | |
| 3775 | // this should take some time? |
| 3776 | segacd_maincpu_has_ram_access = 0; |
| 3777 | } |
| 3778 | |
| 3779 | |
| 3780 | if (data&0x0004) printf("mode set (invalid? can't set from main68k?)\n"); |
| 3781 | if (data&0x0038) printf("unknown bits set\n"); |
| 3782 | |
| 3783 | //if (data&0x00c0) |
| 3784 | { |
| 3785 | printf("bank set to %02x\n", (data&0x00c0)>>6); |
| 3786 | segacd_4meg_prgbank = (data&0x00c0)>>6; |
| 3787 | |
| 3788 | } |
| 3789 | |
| 3790 | } |
| 3791 | |
| 3792 | if (ACCESSING_BITS_8_15) |
| 3793 | { |
| 3794 | if (data & 0xff00) |
| 3795 | { |
| 3796 | printf("write protect bits set %02x\n", data >> 8); |
| 3797 | } |
| 3798 | |
| 3799 | segacd_ram_writeprotect_bits = data >> 8; |
| 3800 | } |
| 3801 | |
| 3802 | } |
| 3803 | |
| 3804 | // can't read the bank? |
| 3805 | static READ16_HANDLER( segacd_sub_memory_mode_r ) |
| 3806 | { |
| 3807 | return (segacd_ram_writeprotect_bits << 8) | |
| 3808 | /*(segacd_4meg_prgbank << 6) | */ |
| 3809 | (segacd_memory_priority_mode << 3) | |
| 3810 | (segacd_ram_mode << 2) | |
| 3811 | ((segacd_maincpu_has_ram_access^1) << 1) | |
| 3812 | ((segacd_maincpu_has_ram_access) << 0); |
| 3813 | } |
| 3814 | |
| 3815 | static WRITE16_HANDLER( segacd_sub_memory_mode_w ) |
| 3816 | { |
| 3817 | printf("segacd_sub_memory_mode_w %04x %04x\n", data, mem_mask); |
| 3818 | |
| 3819 | if (ACCESSING_BITS_0_7) |
| 3820 | { |
| 3821 | if (data&0x0001) |
| 3822 | { |
| 3823 | printf("ret bit set\n"); |
| 3824 | segacd_maincpu_has_ram_access = 1; |
| 3825 | } |
| 3826 | |
| 3827 | |
| 3828 | if (data&0x0002) printf("dmn set (swap requested) (invalid, can't be set from sub68k?\n"); |
| 3829 | |
| 3830 | //if (data&0x0004) |
| 3831 | { |
| 3832 | segacd_ram_mode = (data&0x0004)>>2; |
| 3833 | printf("mode set %d\n", segacd_ram_mode); |
| 3834 | } |
| 3835 | |
| 3836 | //if (data&0x0018) |
| 3837 | { |
| 3838 | |
| 3839 | segacd_memory_priority_mode = (data&0x0018)>>3; |
| 3840 | printf("priority mode bits set to %d\n", segacd_memory_priority_mode); |
| 3841 | |
| 3842 | } |
| 3843 | |
| 3844 | if (data&0x00e0) printf("unknown bits set\n"); |
| 3845 | } |
| 3846 | |
| 3847 | if (ACCESSING_BITS_8_15) |
| 3848 | { |
| 3849 | if (data & 0xff00) |
| 3850 | { |
| 3851 | printf("write protect bits set %02x (invalid, can only be set by main68k)\n", data >> 8); |
| 3852 | } |
| 3853 | } |
| 3854 | |
| 3855 | } |
| 3856 | |
| 3857 | |
| 3858 | /******************************************************************************** |
| 3859 | END MEMORY MODE CONTROL |
| 3860 | ********************************************************************************/ |
| 3861 | |
| 3862 | |
| 3693 | 3863 | static WRITE16_HANDLER( scd_4m_prgbank_ram_w ) |
| 3694 | 3864 | { |
| 3695 | 3865 | UINT16 realoffset = ((segacd_4meg_prgbank * 0x20000)/2) + offset; |
| r9293 | r9294 | |
|---|
| 3701 | 3871 | |
| 3702 | 3872 | } |
| 3703 | 3873 | |
| 3874 | |
| 3875 | /* Callback when the genesis enters interrupt code */ |
| 3876 | static IRQ_CALLBACK(segacd_sub_int_callback) |
| 3877 | { |
| 3878 | if (irqline==2) |
| 3879 | { |
| 3880 | // clear this bit |
| 3881 | a12000_halt_reset_reg &= ~0x0100; |
| 3882 | cputag_set_input_line(device->machine, "segacd_68k", 2, CLEAR_LINE); |
| 3883 | } |
| 3884 | |
| 3885 | return (0x60+irqline*4)/4; // vector address |
| 3886 | } |
| 3887 | |
| 3888 | |
| 3704 | 3889 | /* main CPU map set up in INIT */ |
| 3705 | 3890 | void segacd_init_main_cpu( running_machine* machine ) |
| 3706 | 3891 | { |
| r9293 | r9294 | |
|---|
| 3712 | 3897 | memory_set_bankptr(space->machine, "scd_4m_prgbank", segacd_4meg_prgram + segacd_4meg_prgbank * 0x20000 ); |
| 3713 | 3898 | memory_install_write16_handler (space, 0x0020000, 0x003ffff, 0, 0, scd_4m_prgbank_ram_w ); |
| 3714 | 3899 | |
| 3900 | memory_install_readwrite16_handler(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa12000, 0xa12001, 0, 0, scd_a12000_halt_reset_r, scd_a12000_halt_reset_w); // sub-cpu control |
| 3901 | memory_install_readwrite16_handler(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa12002, 0xa12003, 0, 0, scd_a12002_memory_mode_r, scd_a12002_memory_mode_w); // memory mode / write protect |
| 3715 | 3902 | |
| 3903 | cpu_set_irq_callback(machine->device("segacd_68k"), segacd_sub_int_callback); |
| 3904 | |
| 3716 | 3905 | } |
| 3717 | 3906 | |
| 3718 | 3907 | static MACHINE_RESET( segacd ) |
| r9293 | r9294 | |
|---|
| 3722 | 3911 | } |
| 3723 | 3912 | |
| 3724 | 3913 | |
| 3914 | static int segacd_redled = 0; |
| 3915 | static int segacd_greenled = 0; |
| 3916 | static int segacd_ready = 1; // actually set 100ms after startup? |
| 3917 | |
| 3918 | static READ16_HANDLER( segacd_sub_led_ready_r ) |
| 3919 | { |
| 3920 | UINT16 retdata = 0x0000; |
| 3921 | |
| 3922 | if (ACCESSING_BITS_0_7) |
| 3923 | { |
| 3924 | retdata |= segacd_ready; |
| 3925 | } |
| 3926 | |
| 3927 | if (ACCESSING_BITS_8_15) |
| 3928 | { |
| 3929 | retdata |= segacd_redled << 8; |
| 3930 | retdata |= segacd_greenled << 9; |
| 3931 | } |
| 3932 | |
| 3933 | return retdata; |
| 3934 | } |
| 3935 | |
| 3936 | static WRITE16_HANDLER( segacd_sub_led_ready_w ) |
| 3937 | { |
| 3938 | if (ACCESSING_BITS_0_7) |
| 3939 | { |
| 3940 | if ((data&0x01) == 0x00) |
| 3941 | { |
| 3942 | // reset CD unit |
| 3943 | } |
| 3944 | } |
| 3945 | |
| 3946 | if (ACCESSING_BITS_8_15) |
| 3947 | { |
| 3948 | segacd_redled = (data >> 8)&1; |
| 3949 | segacd_greenled = (data >> 9)&1; |
| 3950 | } |
| 3951 | |
| 3952 | } |
| 3953 | |
| 3954 | |
| 3725 | 3955 | static ADDRESS_MAP_START( segacd_map, ADDRESS_SPACE_PROGRAM, 16 ) |
| 3726 | 3956 | AM_RANGE(0x0000000, 0x007ffff) AM_RAM AM_BASE(&segacd_4meg_prgram) |
| 3957 | |
| 3958 | AM_RANGE(0x0ff8000 ,0x0ff8001) AM_READWRITE(segacd_sub_led_ready_r, segacd_sub_led_ready_w) |
| 3959 | AM_RANGE(0x0ff8002 ,0x0ff8003) AM_READWRITE(segacd_sub_memory_mode_r, segacd_sub_memory_mode_w) |
| 3960 | |
| 3961 | |
| 3727 | 3962 | ADDRESS_MAP_END |
| 3728 | 3963 | |
| 3729 | 3964 | |