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r9285 Thursday 30th September, 2010 at 00:10:14 UTC by Angelo Salese
[32x]: basic refactoring of PWM registers
[src/mame/drivers]megadriv.c

src/mame/drivers/megadriv.c
r9284r9285
27802780{
27812781   // ...
27822782
2783   /* disabled, we need PWM FIFO support first! */
2784//   if(sh2_master_pwmint_enable) { cpu_set_input_line(_32x_master_cpu, SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
2783   if(sh2_master_pwmint_enable) { cpu_set_input_line(_32x_master_cpu, SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
27852784
2786//   if(sh2_slave_pwmint_enable) { cpu_set_input_line(_32x_slave_cpu, SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
2785   if(sh2_slave_pwmint_enable) { cpu_set_input_line(_32x_slave_cpu, SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
27872786
27882787   timer_adjust_oneshot(_32x_pwm_timer, ATTOTIME_IN_HZ(((MASTER_CLOCK_NTSC*3 / 7) / (pwm_cycle - 1)) * pwm_tm_reg), 0);
27892788}
27902789
2791static READ16_HANDLER( _32x_68k_pwm_control_reg_r )
2790static READ16_HANDLER( _32x_pwm_r )
27922791{
2793   return pwm_ctrl;
2794}
2792   switch(offset)
2793   {
2794      case 0/2: return pwm_ctrl; //control register
2795      case 2/2: return pwm_cycle_reg; // cycle register
2796      case 4/2: return mame_rand(space->machine) & 0xc000; // l ch TODO
2797      case 6/2: return mame_rand(space->machine) & 0xc000; // r ch TODO
2798      case 8/2: return mame_rand(space->machine) & 0xc000; // mono ch TODO
2799   }
27952800
2796static WRITE16_HANDLER( _32x_68k_pwm_control_reg_w )
2797{
2798   pwm_ctrl = (data & 0x7f) | (pwm_ctrl & 0xff80);
2799
2800   calculate_pwm_timer();
2801   printf("Read at undefined PWM register %02x\n",offset);
2802   return 0xffff;
28012803}
28022804
2803static WRITE16_HANDLER( _32x_sh2_pwm_control_reg_w )
2805static WRITE16_HANDLER( _32x_pwm_w )
28042806{
2805   pwm_ctrl = data & 0xffff;
2806
2807   pwm_tm_reg = (pwm_ctrl & 0xf00) >> 8;
2808
2809   calculate_pwm_timer();
2807   switch(offset)
2808   {
2809      case 0/2:
2810         pwm_ctrl = data & 0xffff;
2811         pwm_tm_reg = (pwm_ctrl & 0xf00) >> 8;
2812         calculate_pwm_timer();
2813         break;
2814      case 2/2:
2815         pwm_cycle = pwm_cycle_reg = data & 0xfff;
2816         calculate_pwm_timer();
2817         break;
2818      case 4/2:
2819         // l ch TODO
2820         break;
2821      case 6/2:
2822         // r ch TODO
2823         break;
2824      case 8/2:
2825         // mono TODO
2826         break;
2827      default:
2828         printf("Write at undefined PWM register %02x %04x\n",offset,data);
2829         break;
2830   }
28102831}
28112832
2812static READ16_HANDLER( _32x_68k_pwm_cycle_reg_r )
2833static WRITE16_HANDLER( _32x_68k_pwm_w )
28132834{
2814   return pwm_cycle_reg;
2835   if(offset == 0/2)
2836      _32x_pwm_w(space,offset,(data & 0x7f) | (pwm_ctrl & 0xff80),mem_mask);
2837   else
2838      _32x_pwm_w(space,offset,data,mem_mask);
28152839}
28162840
2817static WRITE16_HANDLER( _32x_68k_pwm_cycle_reg_w )
2818{
2819   pwm_cycle = pwm_cycle_reg = data & 0xfff;
2820
2821   calculate_pwm_timer();
2822}
2823
28242841/**********************************************************************************************/
28252842// 68k side a15180
28262843// framebuffer control
r9284r9285
32253242// PWM Control Register
32263243/**********************************************************************************************/
32273244
3228static READ16_HANDLER( _32x_sh2_pwm_control_reg_r ) { return _32x_68k_pwm_control_reg_r(space, offset, mem_mask); }
3229//static WRITE16_HANDLER( _32x_sh2_pwm_control_reg_w ) { _32x_sh2_pwm_control_reg_w(space, offset, data, mem_mask); }
3230
32313245/**********************************************************************************************/
32323246// SH2 side 4032
32333247// Cycle Register
32343248/**********************************************************************************************/
32353249
3236static READ16_HANDLER( _32x_sh2_pwm_cycle_reg_r ) { return _32x_68k_pwm_cycle_reg_r(space, offset, mem_mask); }
3237static WRITE16_HANDLER( _32x_sh2_pwm_cycle_reg_w ) { _32x_68k_pwm_cycle_reg_w(space, offset, data, mem_mask); }
32383250
3239
32403251/**********************************************************************************************/
32413252// SH2 side 4034
32423253// LCH Pulse Width Register
r9284r9285
33823393_32X_MAP_RAM_READHANDLERS(commsram) // _32x_sh2_commsram_r
33833394_32X_MAP_RAM_WRITEHANDLERS(commsram) // _32x_sh2_commsram_w
33843395
3385_32X_MAP_READHANDLERS(pwm_control_reg,pwm_cycle_reg)
3386_32X_MAP_WRITEHANDLERS(pwm_control_reg,pwm_cycle_reg)
3387
3388
33893396_32X_MAP_RAM_READHANDLERS(framebuffer_dram) // _32x_sh2_framebuffer_dram_r
33903397_32X_MAP_RAM_WRITEHANDLERS(framebuffer_dram) // _32x_sh2_framebuffer_dram_w
33913398
r9284r9285
34133420   AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE( _32x_sh2_master_401c_master_401e_w ) // IRQ clear
34143421
34153422   AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE( _32x_sh2_commsram_r, _32x_sh2_commsram_w )
3416   AM_RANGE(0x00004030, 0x00004033) AM_READWRITE( _32x_sh2_pwm_control_reg_pwm_cycle_reg_r, _32x_sh2_pwm_control_reg_pwm_cycle_reg_w )
3417   AM_RANGE(0x00004034, 0x0000403f) AM_NOP
3423   AM_RANGE(0x00004030, 0x0000403f) AM_READWRITE16( _32x_pwm_r, _32x_pwm_w, 0xffffffff )
34183424
34193425   AM_RANGE(0x00004100, 0x0000410b) AM_READWRITE16( _32x_common_vdp_regs_r, _32x_common_vdp_regs_w , 0xffffffff)
34203426   AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE( _32x_sh2_paletteram_r, _32x_sh2_paletteram_w)
r9284r9285
34433449   AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE( _32x_sh2_slave_401c_slave_401e_w ) // IRQ clear
34443450
34453451   AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE( _32x_sh2_commsram_r, _32x_sh2_commsram_w )
3446   AM_RANGE(0x00004030, 0x00004033) AM_READWRITE( _32x_sh2_pwm_control_reg_pwm_cycle_reg_r, _32x_sh2_pwm_control_reg_pwm_cycle_reg_w )
3447   AM_RANGE(0x00004034, 0x0000403f) AM_NOP
3452   AM_RANGE(0x00004030, 0x0000403f) AM_READWRITE16( _32x_pwm_r, _32x_pwm_w, 0xffffffff )
34483453
34493454   AM_RANGE(0x00004100, 0x0000410b) AM_READWRITE16( _32x_common_vdp_regs_r, _32x_common_vdp_regs_w , 0xffffffff)
34503455   AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE(_32x_sh2_paletteram_r, _32x_sh2_paletteram_w)
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65986603   memory_install_readwrite16_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa1511a, 0xa1511b, 0, 0, _32x_68k_a1511a_r, _32x_68k_a1511a_w); // SEGA TV
65996604
66006605   memory_install_readwrite16_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa15120, 0xa1512f, 0, 0, _32x_68k_commsram_r, _32x_68k_commsram_w); // comms reg 0-7
6601   memory_install_readwrite16_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa15130, 0xa15131, 0, 0, _32x_68k_pwm_control_reg_r, _32x_68k_pwm_control_reg_w);
6602   memory_install_readwrite16_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa15132, 0xa15133, 0, 0, _32x_68k_pwm_cycle_reg_r, _32x_68k_pwm_cycle_reg_w);
6606   memory_install_readwrite16_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa15130, 0xa1513f, 0, 0, _32x_pwm_r, _32x_68k_pwm_w);
66036607
66046608   memory_install_read16_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0a130ec, 0x0a130ef, 0, 0, _32x_68k_MARS_r); // system ID
66056609

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