src/mame/drivers/megadriv.c
| r9257 | r9258 | |
|---|
| 2446 | 2446 | { |
| 2447 | 2447 | dreq_src_addr[offset] = (offset == 0) ? (data & 0xff) : (data & 0xfffe); |
| 2448 | 2448 | |
| 2449 | | printf("DREQ set SRC = %08x\n",dreq_src_addr[0]<<16|dreq_src_addr[1]); |
| 2449 | if((dreq_src_addr[0]<<16)|dreq_src_addr[1]) |
| 2450 | printf("DREQ set SRC = %08x\n",(dreq_src_addr[0]<<16)|dreq_src_addr[1]); |
| 2450 | 2451 | } |
| 2451 | 2452 | |
| 2452 | 2453 | static READ16_HANDLER( _32x_68k_a1510c_r ) |
| r9257 | r9258 | |
|---|
| 2458 | 2459 | { |
| 2459 | 2460 | dreq_dst_addr[offset] = (offset == 0) ? (data & 0xff) : (data & 0xffff); |
| 2460 | 2461 | |
| 2461 | | printf("DREQ set DST = %08x\n",(dreq_dst_addr[0]<<16)|dreq_dst_addr[1]); |
| 2462 | if((dreq_dst_addr[0]<<16)|dreq_dst_addr[1]) |
| 2463 | printf("DREQ set DST = %08x\n",(dreq_dst_addr[0]<<16)|dreq_dst_addr[1]); |
| 2462 | 2464 | } |
| 2463 | 2465 | |
| 2464 | 2466 | static READ16_HANDLER( _32x_68k_a15110_r ) |
| r9257 | r9258 | |
|---|
| 2470 | 2472 | { |
| 2471 | 2473 | dreq_size = data & 0xfffc; |
| 2472 | 2474 | |
| 2473 | | printf("DREQ set SIZE = %04x\n",dreq_size); |
| 2475 | // if(dreq_size) |
| 2476 | // printf("DREQ set SIZE = %04x\n",dreq_size); |
| 2474 | 2477 | } |
| 2475 | 2478 | |
| 2476 | 2479 | /* |
| r9257 | r9258 | |
|---|
| 2918 | 2921 | |
| 2919 | 2922 | if (megadrive_hblank_flag) retdata |= 0x4000; |
| 2920 | 2923 | |
| 2924 | if (megadrive_vblank_flag && _32x_access_auth) { retdata |= 2; } // framebuffer approval (TODO: condition is unknown at current time) |
| 2925 | |
| 2921 | 2926 | if (megadrive_hblank_flag && megadrive_vblank_flag) { retdata |= 0x2000; } // palette approval (TODO: active high or low?) |
| 2922 | 2927 | |
| 2923 | 2928 | return retdata; |
| r9257 | r9258 | |
|---|
| 3489 | 3494 | |
| 3490 | 3495 | AM_RANGE(0x00004010, 0x00004013) AM_READ( _32x_sh2_common_4010_common_4012_r ) |
| 3491 | 3496 | |
| 3492 | | AM_RANGE(0x00004014, 0x00004017) AM_WRITE( _32x_sh2_master_4014_master_4016_w ) // IRQ clear |
| 3493 | | AM_RANGE(0x00004018, 0x0000401b) AM_WRITE( _32x_sh2_master_4018_master_401a_w ) // IRQ clear |
| 3494 | | AM_RANGE(0x0000401c, 0x0000401f) AM_WRITE( _32x_sh2_master_401c_master_401e_w ) // IRQ clear |
| 3497 | AM_RANGE(0x00004014, 0x00004017) AM_READNOP AM_WRITE( _32x_sh2_master_4014_master_4016_w ) // IRQ clear |
| 3498 | AM_RANGE(0x00004018, 0x0000401b) AM_READNOP AM_WRITE( _32x_sh2_master_4018_master_401a_w ) // IRQ clear |
| 3499 | AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE( _32x_sh2_master_401c_master_401e_w ) // IRQ clear |
| 3495 | 3500 | |
| 3496 | 3501 | AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE( _32x_sh2_commsram_r, _32x_sh2_commsram_w ) |
| 3497 | 3502 | AM_RANGE(0x00004030, 0x00004033) AM_READWRITE( _32x_sh2_pwm_control_reg_pwm_cycle_reg_r, _32x_sh2_pwm_control_reg_pwm_cycle_reg_w ) |