MESS SVN History

15994 Revisions

r9082 Friday 10th September, 2010 at 07:29:51 UTC by Miodrag Milanović
Partial sync with MAME (no removal of generic videoram)

[src/emu]	devintrf.c devintrf.h disound.c disound.h sound.c
[src/emu/cpu/adsp2100]	2100ops.c adsp2100.c adsp2100.h
[src/emu/cpu/asap]	asap.c asap.h asapdasm.c
[src/emu/video]	pc_video.c pc_video.h
[src/tools]	chdcd.c chdcd.h chdman.c

src/tools/chdcd.c
r9081	r9082
232	232	}
233	233
234	234	/*-------------------------------------------------
235		chdcd_tracksize_helper - fixes up track sizes
236		for bin/cue images
	235	chdcd_parse_toc - parse a CDRWin format CUE file
237	236	-------------------------------------------------*/
238	237
239		~~stati~~c ~~voi~~d chdcd_tracksize_he~~lper~~(int trknum, cdrom_toc outtoc, chdcd_track_input_info outinfo)
	238	chd_error chdcd_parse_cue(const char tocfname, cdrom_toc outtoc, chdcd_track_input_info *outinfo)
240	239	{
241		if (outtoc->tracks[trknum].frames == 0)
	240	FILE *infile;
	241	int i, trknum;
	242	static char token[128];
	243	static char lastfname[128];
	244
	245	infile = fopen(tocfname, "rt");
	246
	247	if (infile == (FILE *)NULL)
242	248	{
	249	return CHDERR_FILE_NOT_FOUND;
	250	}
	251
	252	/* clear structures */
	253	memset(outtoc, 0, sizeof(cdrom_toc));
	254	memset(outinfo, 0, sizeof(chdcd_track_input_info));
	255
	256	trknum = -1;
	257
	258	while (!feof(infile))
	259	{
	260	/* get the next line */
	261	fgets(linebuffer, 511, infile);
	262
	263	/* if EOF didn't hit, keep going */
	264	if (!feof(infile))
	265	{
	266	i = 0;
	267
	268	TOKENIZE
	269
	270	if (!strcmp(token, "FILE"))
	271	{
	272	/* found the data file for a track */
	273	TOKENIZE
	274
	275	/* keep the filename */
	276	strncpy(&outinfo->fname[trknum][0], token, strlen(token));
	277	strncpy(lastfname, token, 128);
	278
	279	/* get the file type */
	280	TOKENIZE
	281
	282	if (!strcmp(token, "BINARY"))
	283	{
	284	outinfo->swap[trknum] = 0;
	285	}
	286	else if (!strcmp(token, "MOTOROLA"))
	287	{
	288	outinfo->swap[trknum] = 1;
	289	}
	290	else
	291	{
	292	printf("ERROR: Unhandled track type %s\n", token);
	293	return CHDERR_FILE_NOT_FOUND;
	294	}
	295	}
	296	else if (!strcmp(token, "TRACK"))
	297	{
	298	/* get the track number */
	299	TOKENIZE
	300	trknum = strtoul(token, NULL, 10) - 1;
	301
	302	/* next token on the line is the track type */
	303	TOKENIZE
	304
	305	outtoc->tracks[trknum].trktype = CD_TRACK_MODE1;
	306	outtoc->tracks[trknum].datasize = 0;
	307	outtoc->tracks[trknum].subtype = CD_SUB_NONE;
	308	outtoc->tracks[trknum].subsize = 0;
	309	outtoc->tracks[trknum].pregap = 0;
	310	outinfo->idx0offs[trknum] = -1;
	311	outinfo->idx1offs[trknum] = 0;
	312	strcpy(&outinfo->fname[trknum][0], lastfname); // default filename to the last one
	313	// printf("trk %d: fname %s\n", trknum+1, &outinfo->fname[trknum][0]);
	314
	315	cdrom_convert_type_string_to_track_info(token, &outtoc->tracks[trknum]);
	316	if (outtoc->tracks[trknum].datasize == 0)
	317	{
	318	printf("ERROR: Unknown track type [%s]. Contact MAMEDEV.\n", token);
	319	return CHDERR_FILE_NOT_FOUND;
	320	}
	321	else if (outtoc->tracks[trknum].trktype != CD_TRACK_MODE1_RAW &&
	322	outtoc->tracks[trknum].trktype != CD_TRACK_MODE2_RAW &&
	323	outtoc->tracks[trknum].trktype != CD_TRACK_AUDIO)
	324	{
	325	printf("Note: MAME prefers and can accept RAW format images.\n");
	326	printf("At least one track of this rip is not either RAW or AUDIO.\n");
	327	}
	328
	329	/* next (optional) token on the line is the subcode type */
	330	TOKENIZE
	331
	332	cdrom_convert_subtype_string_to_track_info(token, &outtoc->tracks[trknum]);
	333	}
	334	else if (!strcmp(token, "INDEX")) /* only in bin/cue files */
	335	{
	336	int idx, frames;
	337
	338	/* get index number */
	339	TOKENIZE
	340	idx = strtoul(token, NULL, 10);
	341
	342	/* get index */
	343	TOKENIZE
	344	frames = msf_to_frames( token );
	345
	346	if (idx == 0)
	347	{
	348	outinfo->idx0offs[trknum] = frames;
	349	}
	350	else if (idx == 1)
	351	{
	352	outinfo->idx1offs[trknum] = frames;
	353	if ((outtoc->tracks[trknum].pregap == 0) && (outinfo->idx0offs[trknum] != -1))
	354	{
	355	outtoc->tracks[trknum].pregap = frames - outinfo->idx0offs[trknum];
	356	}
	357	}
	358	}
	359	else if (!strcmp(token, "PREGAP"))
	360	{
	361	int frames;
	362
	363	/* get index */
	364	TOKENIZE
	365	frames = msf_to_frames( token );
	366
	367	outtoc->tracks[trknum].pregap = frames;
	368	}
	369	else if (!strcmp(token, "POSTGAP"))
	370	{
	371	int frames;
	372
	373	/* get index */
	374	TOKENIZE
	375	frames = msf_to_frames( token );
	376
	377	outtoc->tracks[trknum].postgap = frames;
	378	}
	379	}
	380	}
	381
	382	/* close the input CUE */
	383	fclose(infile);
	384
	385	/* store the number of tracks found */
	386	outtoc->numtrks = trknum + 1;
	387
	388	/* now go over the files again and set the lengths */
	389	for (trknum = 0; trknum < outtoc->numtrks; trknum++)
	390	{
243	391	UINT64 tlen;
244	392
245		tlen = get_file_size(outinfo->fname[trknum]) - outinfo->offset[trknum];
246		tlen /= (outtoc->tracks[trknum].datasize + outtoc->tracks[trknum].subsize);
	393	if (outtoc->tracks[trknum].trktype == CD_TRACK_AUDIO)
	394	{
	395	outinfo->swap[trknum] = 1;
	396	}
247	397
248		outtoc->tracks[trknum].frames = tlen;
	398	// is this the last track?
	399	if (trknum == (outtoc->numtrks-1))
	400	{
	401	/* if we have the same filename as the last track, do it that way */
	402	if (!strcmp(&outinfo->fname[trknum][0], &outinfo->fname[trknum-1][0]))
	403	{
	404	tlen = get_file_size(outinfo->fname[trknum]);
	405	outinfo->offset[trknum] = outinfo->offset[trknum-1] + outtoc->tracks[trknum-1].frames * (outtoc->tracks[trknum-1].datasize + outtoc->tracks[trknum-1].subsize);
	406	outtoc->tracks[trknum].frames = (tlen - outinfo->offset[trknum]) / (outtoc->tracks[trknum].datasize + outtoc->tracks[trknum].subsize);
	407	}
	408	else /* data files are different */
	409	{
	410	tlen = get_file_size(outinfo->fname[trknum]);
	411	tlen /= (outtoc->tracks[trknum].datasize + outtoc->tracks[trknum].subsize);
	412	outtoc->tracks[trknum].frames = tlen;
	413	outinfo->offset[trknum] = 0;
	414	}
	415	}
	416	else
	417	{
	418	/* if we have the same filename as the next track, do it that way */
	419	if (!strcmp(&outinfo->fname[trknum][0], &outinfo->fname[trknum+1][0]))
	420	{
	421	outtoc->tracks[trknum].frames = outinfo->idx1offs[trknum+1] - outinfo->idx1offs[trknum];
	422
	423	if (trknum == 0) // track 0 offset is 0
	424	{
	425	outinfo->offset[trknum] = 0;
	426	}
	427	else
	428	{
	429	outinfo->offset[trknum] = outinfo->offset[trknum-1] + outtoc->tracks[trknum-1].frames * (outtoc->tracks[trknum-1].datasize + outtoc->tracks[trknum-1].subsize);
	430	}
	431
	432	if (!outtoc->tracks[trknum].frames)
	433	{
	434	printf("ERROR: unable to determine size of track %d, missing INDEX 01 markers?\n", trknum+1);
	435	return CHDERR_FILE_NOT_FOUND;
	436	}
	437	}
	438	else /* data files are different */
	439	{
	440	tlen = get_file_size(outinfo->fname[trknum]);
	441	tlen /= (outtoc->tracks[trknum].datasize + outtoc->tracks[trknum].subsize);
	442	outtoc->tracks[trknum].frames = tlen;
	443	outinfo->offset[trknum] = 0;
	444	}
	445	}
	446	// printf("trk %d: %d frames @ offset %d\n", trknum+1, outtoc->tracks[trknum].frames, outinfo->offset[trknum]);
249	447	}
250	448
251		~~// p~~r~~intf("track %d: %d fram~~e~~s\n",~~ t~~rkn~~u~~m, outtoc->t~~r~~acks[trk~~n~~um].frames)~~;
	449	return CHDERR_NONE;
252	450	}
253	451
254	452	/*-------------------------------------------------
r9081	r9082
258	456	chd_error chdcd_parse_toc(const char tocfname, cdrom_toc outtoc, chdcd_track_input_info *outinfo)
259	457	{
260	458	FILE *infile;
261		int i, trknum~~, cuemode = 0~~;
	459	int i, trknum;
262	460	static char token[128];
263	461
264	462	if (strstr(tocfname,".gdi"))
r9081	r9082
268	466
269	467	if (strstr(tocfname,".cue"))
270	468	{
271		cuemode = 1;
	469	return chdcd_parse_cue(tocfname, outtoc, outinfo);
272	470	}
273	471
274	472	infile = fopen(tocfname, "rt");
r9081	r9082
300	498	{
301	499	int f;
302	500
303		/* for bin/cue, this is where you increment the track # */
304		if (cuemode)
305		{
306		/* make sure we have a size for the current track before moving on */
307		if (trknum > -1)
308		{
309		chdcd_tracksize_helper(trknum, outtoc, outinfo);
310		}
311		trknum++;
312		}
313
314	501	/* found the data file for a track */
315	502	TOKENIZE
316	503
r9081	r9082
386	573	}
387	574	else if (!strcmp(token, "TRACK"))
388	575	{
389		/* found a new track if CDRDAO .toc, not if .cue */
390		if (!cuemode)
391		{
392		trknum++;
393		}
	576	trknum++;
394	577
395	578	/* next token on the line is the track type */
396	579	TOKENIZE
397	580
398		/* for bin/cue skip the track number */
399		if (cuemode)
400		{
401		TOKENIZE
402		}
403
404	581	outtoc->tracks[trknum].trktype = CD_TRACK_MODE1;
405	582	outtoc->tracks[trknum].datasize = 0;
406	583	outtoc->tracks[trknum].subtype = CD_SUB_NONE;
r9081	r9082
410	587	if (outtoc->tracks[trknum].datasize == 0)
411	588	{
412	589	printf("ERROR: Unknown track type [%s]. Contact MAMEDEV.\n", token);
	590	return CHDERR_FILE_NOT_FOUND;
413	591	}
414	592	else if (outtoc->tracks[trknum].trktype != CD_TRACK_MODE1_RAW &&
415	593	outtoc->tracks[trknum].trktype != CD_TRACK_MODE2_RAW &&
r9081	r9082
424	602
425	603	cdrom_convert_subtype_string_to_track_info(token, &outtoc->tracks[trknum]);
426	604	}
427		else if (!strcmp(token, "~~INDEX~~")) ~~/* only in bin/cue files */~~
	605	else if (!strcmp(token, "START"))
428	606	{
429		int idx, frames;
430
431		/* get index number */
432		TOKENIZE
433		idx = strtoul(token, NULL, 10);
434
435		/* get index */
436		TOKENIZE
437		frames = msf_to_frames( token );
438
439		if (idx == 1)
440		{
441		outtoc->tracks[trknum].pregap = frames;
442		}
443		}
444		else if ((!strcmp(token, "START")) \|\| (!strcmp(token, "PREGAP"))) /* START for CDRDAO, PREGAP for CDRWIN */
445		{
446	607	int frames;
447	608
448	609	/* get index */
r9081	r9082
451	612
452	613	outtoc->tracks[trknum].pregap = frames;
453	614	}
454		else if (!strcmp(token, "POSTGAP")) /* only in CDRWIN files */
455		{
456		int frames;
457
458		/* get index */
459		TOKENIZE
460		frames = msf_to_frames( token );
461
462		outtoc->tracks[trknum].postgap = frames;
463		}
464	615	}
465	616	}
466	617
467		if (cuemode)
468		{
469		/* make sure we have a size for the last track before moving on */
470		chdcd_tracksize_helper(trknum, outtoc, outinfo);
471		}
472
473	618	/* close the input TOC */
474	619	fclose(infile);
475	620

src/tools/chdcd.h
r9081	r9082
20	20	char fname[CD_MAX_TRACKS][256]; /* filename for each track */
21	21	UINT32 offset[CD_MAX_TRACKS]; /* offset in the data file for each track */
22	22	int swap[CD_MAX_TRACKS]; /* data needs to be byte swapped */
	23	UINT32 idx0offs[CD_MAX_TRACKS];
	24	UINT32 idx1offs[CD_MAX_TRACKS];
23	25	};
24	26
25	27

src/tools/chdman.c
r9081	r9082
776	776	goto cleanup;
777	777	}
778	778
779		printf("Track %d/%d (%s:%d,%d frames,%d hunks,swap %d,pregap %d,postgap %d)\n", i+1, toc.numtrks, track_info.fname[i], track_info.offset[i], toc.tracks[i].frames, trackhunks, track_info.swap[i], toc.tracks[i].pregap, toc.tracks[i].postgap);
	779	printf("Track %02d/%02d (%s:%d,%d frames,%d hunks,swap %d,pregap %d,postgap %d)\n", i+1, toc.numtrks, track_info.fname[i], track_info.offset[i], toc.tracks[i].frames, trackhunks, track_info.swap[i], toc.tracks[i].pregap, toc.tracks[i].postgap);
780	780
781	781	/* loop over hunks */
782	782	for (curhunk = 0; curhunk < trackhunks; curhunk++, totalhunks++)

src/emu/cpu/adsp2100/adsp2100.h
r9081	r9082
1	1	/***************************************************************************
2	2
3		ADSP2100.h
4		Interface file for the portable Analog ADSP-2100 emulator.
5		Written by Aaron Giles
	3	adsp2100.h
6	4
	5	ADSP-21xx series emulator.
	6
	7	****************************************************************************
	8
	9	Copyright Aaron Giles
	10	All rights reserved.
	11
	12	Redistribution and use in source and binary forms, with or without
	13	modification, are permitted provided that the following conditions are
	14	met:
	15
	16	* Redistributions of source code must retain the above copyright
	17	notice, this list of conditions and the following disclaimer.
	18	* Redistributions in binary form must reproduce the above copyright
	19	notice, this list of conditions and the following disclaimer in
	20	the documentation and/or other materials provided with the
	21	distribution.
	22	* Neither the name 'MAME' nor the names of its contributors may be
	23	used to endorse or promote products derived from this software
	24	without specific prior written permission.
	25
	26	THIS SOFTWARE IS PROVIDED BY AARON GILES ''AS IS'' AND ANY EXPRESS OR
	27	IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	28	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	29	DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT,
	30	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	31	(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	32	SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	33	HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
	34	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
	35	IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	36	POSSIBILITY OF SUCH DAMAGE.
	37
7	38	***************************************************************************/
8	39
9	40	#pragma once
r9081	r9082
12	43	#define __ADSP2100_H__
13	44
14	45
15		/***************************************************************************
16		TYPE DEFINITIONS
17		***************************************************************************/
	46	//**************************************************************************
	47	// DEBUGGING
	48	//**************************************************************************
18	49
19		DECLARE_LEGACY_CPU_DEVICE(ADSP2100, adsp2100);
20		DECLARE_LEGACY_CPU_DEVICE(ADSP2101, adsp2101);
21		DECLARE_LEGACY_CPU_DEVICE(ADSP2104, adsp2104);
22		DECLARE_LEGACY_CPU_DEVICE(ADSP2105, adsp2105);
23		DECLARE_LEGACY_CPU_DEVICE(ADSP2115, adsp2115);
24		DECLARE_LEGACY_CPU_DEVICE(ADSP2181, adsp2181);
	50	#define ADSP_TRACK_HOTSPOTS 0
25	51
26		/* transmit and receive data callbacks types */
27		typedef INT32 (*adsp21xx_rx_func)(cpu_device &device, int port);
28		typedef void (*adsp21xx_tx_func)(cpu_device &device, int port, INT32 data);
29		typedef void (*adsp21xx_timer_func)(cpu_device &device, int enable);
30	52
	53
	54	//**************************************************************************
	55	// INTERFACE CONFIGURATION MACROS
	56	//**************************************************************************
	57
	58	#define MDRV_ADSP21XX_CONFIG(_config) \
	59	adsp21xx_device_config::static_set_config(device, _config); \
	60
	61
	62
	63	//**************************************************************************
	64	// GLOBAL VARIABLES
	65	//**************************************************************************
	66
	67	// device type definition
	68	extern const device_type ADSP2100;
	69	extern const device_type ADSP2101;
	70	extern const device_type ADSP2104;
	71	extern const device_type ADSP2105;
	72	extern const device_type ADSP2115;
	73	extern const device_type ADSP2181;
	74
	75
	76
	77	//**************************************************************************
	78	// TYPE DEFINITIONS
	79	//**************************************************************************
	80
	81	class adsp21xx_device;
	82	class adsp2100_device;
	83	class adsp2101_device;
	84	class adsp2181_device;
	85
	86	// transmit and receive data callbacks types
	87	typedef INT32 (*adsp21xx_rx_func)(adsp21xx_device &device, int port);
	88	typedef void (*adsp21xx_tx_func)(adsp21xx_device &device, int port, INT32 data);
	89	typedef void (*adsp21xx_timer_func)(adsp21xx_device &device, int enable);
	90
	91
	92	// ======================> adsp21xx_config
	93
31	94	struct adsp21xx_config
32	95	{
33		adsp21xx_rx_func rx; /* callback for serial receive */
34		adsp21xx_tx_func tx; /* callback for serial transmit */
35		adsp21xx_timer_func timer; /* callback for timer fired */
	96	adsp21xx_rx_func m_sport_rx_callback; // callback for serial receive
	97	adsp21xx_tx_func m_sport_tx_callback; // callback for serial transmit
	98	adsp21xx_timer_func m_timer_fired; // callback for timer fired
36	99	};
37	100
38	101
39	102
	103	// ======================> adsp21xx_device_config
	104
	105	class adsp21xx_device_config : public cpu_device_config,
	106	public adsp21xx_config
	107	{
	108	friend class adsp21xx_device;
	109
	110	protected:
	111	enum
	112	{
	113	CHIP_TYPE_ADSP2100,
	114	CHIP_TYPE_ADSP2101,
	115	CHIP_TYPE_ADSP2104,
	116	CHIP_TYPE_ADSP2105,
	117	CHIP_TYPE_ADSP2115,
	118	CHIP_TYPE_ADSP2181,
	119	};
	120
	121	// construction/destruction
	122	adsp21xx_device_config(const machine_config &mconfig, device_type type, const char name, const char tag, const device_config *owner, UINT32 clock, UINT32 chiptype);
	123
	124	public:
	125	// inline configuration helpers
	126	static void static_set_config(device_config *device, const adsp21xx_config &config);
	127
	128	protected:
	129	// device_config_execute_interface overrides
	130	virtual UINT32 execute_min_cycles() const;
	131	virtual UINT32 execute_max_cycles() const;
	132
	133	// device_config_disasm_interface overrides
	134	virtual UINT32 disasm_min_opcode_bytes() const;
	135	virtual UINT32 disasm_max_opcode_bytes() const;
	136
	137	// address spaces
	138	const address_space_config m_program_config;
	139	const address_space_config m_data_config;
	140
	141	// internal state
	142	UINT32 m_chip_type;
	143	};
	144
	145
	146
	147	// ======================> adsp21xx_device
	148
	149	class adsp21xx_device : public cpu_device
	150	{
	151	friend class adsp21xx_device_config;
	152
	153	protected:
	154	// construction/destruction
	155	adsp21xx_device(running_machine &_machine, const adsp21xx_device_config &config);
	156	virtual ~adsp21xx_device();
	157
	158	public:
	159	// public interfaces
	160	void load_boot_data(UINT8 srcdata, UINT32 dstdata);
	161
	162	protected:
	163	// device-level overrides
	164	virtual void device_start();
	165	virtual void device_reset();
	166
	167	// device_execute_interface overrides
	168	virtual void execute_run();
	169	virtual void execute_set_input(int inputnum, int state);
	170
	171	// device_state_interface overrides
	172	virtual void state_import(const device_state_entry &entry);
	173	virtual void state_string_export(const device_state_entry &entry, astring &string);
	174
	175	// device_disasm_interface overrides
	176	virtual offs_t disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options);
	177
	178	// helpers
	179	void create_tables();
	180	inline void update_mstat();
	181	inline UINT32 pc_stack_top();
	182	inline void set_pc_stack_top(UINT32 top);
	183	inline void pc_stack_push();
	184	inline void pc_stack_push_val(UINT32 val);
	185	inline void pc_stack_pop();
	186	inline UINT32 pc_stack_pop_val();
	187	inline UINT32 cntr_stack_top();
	188	inline void cntr_stack_push();
	189	inline void cntr_stack_pop();
	190	inline UINT32 loop_stack_top();
	191	inline void loop_stack_push(UINT32 value);
	192	inline void loop_stack_pop();
	193	inline void stat_stack_push();
	194	inline void stat_stack_pop();
	195	// inline int condition(int c);
	196	int slow_condition();
	197	inline void modify_address(UINT32 ireg, UINT32 mreg);
	198	inline void data_write_dag1(UINT32 op, INT32 val);
	199	inline UINT32 data_read_dag1(UINT32 op);
	200	inline void data_write_dag2(UINT32 op, INT32 val);
	201	inline UINT32 data_read_dag2(UINT32 op);
	202	inline void pgm_write_dag2(UINT32 op, INT32 val);
	203	inline UINT32 pgm_read_dag2(UINT32 op);
	204	void alu_op_ar(int op);
	205	void alu_op_ar_const(int op);
	206	void alu_op_af(int op);
	207	void alu_op_af_const(int op);
	208	void alu_op_none(int op);
	209	void mac_op_mr(int op);
	210	void mac_op_mr_xop(int op);
	211	void mac_op_mf(int op);
	212	void mac_op_mf_xop(int op);
	213	void shift_op(int op);
	214	void shift_op_imm(int op);
	215
	216	// memory access
	217	inline UINT16 data_read(UINT32 addr);
	218	inline void data_write(UINT32 addr, UINT16 data);
	219	inline UINT16 io_read(UINT32 addr);
	220	inline void io_write(UINT32 addr, UINT16 data);
	221	inline UINT32 program_read(UINT32 addr);
	222	inline void program_write(UINT32 addr, UINT32 data);
	223	inline UINT32 opcode_read();
	224
	225	// register read/write
	226	inline void update_i(int which);
	227	inline void update_l(int which);
	228	inline void write_reg0(int regnum, INT32 val);
	229	inline void write_reg1(int regnum, INT32 val);
	230	inline void write_reg2(int regnum, INT32 val);
	231	inline void write_reg3(int regnum, INT32 val);
	232	inline INT32 read_reg0(int regnum);
	233	inline INT32 read_reg1(int regnum);
	234	inline INT32 read_reg2(int regnum);
	235	inline INT32 read_reg3(int regnum);
	236
	237	// interrupts
	238	virtual bool generate_irq(int which, int indx = 0) = 0;
	239	virtual void check_irqs() = 0;
	240
	241	// internal state
	242	static const int PC_STACK_DEPTH = 16;
	243	static const int CNTR_STACK_DEPTH = 4;
	244	static const int STAT_STACK_DEPTH = 4;
	245	static const int LOOP_STACK_DEPTH = 4;
	246
	247	// 16-bit registers that can be loaded signed or unsigned
	248	union adsp_reg16
	249	{
	250	UINT16 u;
	251	INT16 s;
	252	};
	253
	254	// the SHIFT result register is 32 bits
	255	union adsp_shift
	256	{
	257	#ifdef LSB_FIRST
	258	struct { adsp_reg16 sr0, sr1; } srx;
	259	#else
	260	struct { adsp_reg16 sr1, sr0; } srx;
	261	#endif
	262	UINT32 sr;
	263	};
	264
	265	// the MAC result register is 40 bits
	266	union adsp_mac
	267	{
	268	#ifdef LSB_FIRST
	269	struct { adsp_reg16 mr0, mr1, mr2, mrzero; } mrx;
	270	struct { UINT32 mr0, mr1; } mry;
	271	#else
	272	struct { adsp_reg16 mrzero, mr2, mr1, mr0; } mrx;
	273	struct { UINT32 mr1, mr0; } mry;
	274	#endif
	275	UINT64 mr;
	276	};
	277
	278	// core registers which are replicated
	279	struct adsp_core
	280	{
	281	// ALU registers
	282	adsp_reg16 ax0, ax1;
	283	adsp_reg16 ay0, ay1;
	284	adsp_reg16 ar;
	285	adsp_reg16 af;
	286
	287	// MAC registers
	288	adsp_reg16 mx0, mx1;
	289	adsp_reg16 my0, my1;
	290	adsp_mac mr;
	291	adsp_reg16 mf;
	292
	293	// SHIFT registers
	294	adsp_reg16 si;
	295	adsp_reg16 se;
	296	adsp_reg16 sb;
	297	adsp_shift sr;
	298
	299	// dummy registers
	300	adsp_reg16 zero;
	301	};
	302
	303	// configuration
	304	const adsp21xx_device_config &m_config;
	305
	306	// other CPU registers
	307	UINT32 m_pc;
	308	UINT32 m_ppc;
	309	UINT32 m_loop;
	310	UINT32 m_loop_condition;
	311	UINT32 m_cntr;
	312
	313	// status registers
	314	UINT32 m_astat;
	315	UINT32 m_sstat;
	316	UINT32 m_mstat;
	317	UINT32 m_mstat_prev;
	318	UINT32 m_astat_clear;
	319	UINT32 m_idle;
	320
	321	// live set of core registers
	322	adsp_core m_core;
	323
	324	// memory addressing registers
	325	UINT32 m_i[8];
	326	INT32 m_m[8];
	327	UINT32 m_l[8];
	328	UINT32 m_lmask[8];
	329	UINT32 m_base[8];
	330	UINT8 m_px;
	331
	332	// stacks
	333	UINT32 m_loop_stack[LOOP_STACK_DEPTH];
	334	UINT32 m_cntr_stack[CNTR_STACK_DEPTH];
	335	UINT32 m_pc_stack[PC_STACK_DEPTH];
	336	UINT16 m_stat_stack[STAT_STACK_DEPTH][3];
	337	INT32 m_pc_sp;
	338	INT32 m_cntr_sp;
	339	INT32 m_stat_sp;
	340	INT32 m_loop_sp;
	341
	342	// external I/O
	343	UINT8 m_flagout;
	344	UINT8 m_flagin;
	345	UINT8 m_fl0;
	346	UINT8 m_fl1;
	347	UINT8 m_fl2;
	348	UINT16 m_idma_addr;
	349	UINT16 m_idma_cache;
	350	UINT8 m_idma_offs;
	351
	352	// interrupt handling
	353	UINT16 m_imask;
	354	UINT8 m_icntl;
	355	UINT16 m_ifc;
	356	UINT8 m_irq_state[9];
	357	UINT8 m_irq_latch[9];
	358
	359	// other internal states
	360	int m_icount;
	361	int m_mstat_mask;
	362	int m_imask_mask;
	363
	364	// register maps
	365	INT16 * m_read0_ptr[16];
	366	UINT32 * m_read1_ptr[16];
	367	UINT32 * m_read2_ptr[16];
	368	void * m_alu_xregs[8];
	369	void * m_alu_yregs[4];
	370	void * m_mac_xregs[8];
	371	void * m_mac_yregs[4];
	372	void * m_shift_xregs[8];
	373
	374	// alternate core registers (at end for performance)
	375	adsp_core m_alt;
	376
	377	// address spaces
	378	address_space * m_program;
	379	address_space * m_data;
	380	address_space * m_io;
	381	direct_read_data * m_direct;
	382
	383	// tables
	384	UINT8 m_condition_table[0x1000];
	385	UINT16 m_mask_table[0x4000];
	386	UINT16 m_reverse_table[0x4000];
	387
	388	// debugging
	389	#if ADSP_TRACK_HOTSPOTS
	390	UINT32 m_pcbucket[0x4000];
	391	#endif
	392
	393	// flag definitions
	394	static const int SSFLAG = 0x80;
	395	static const int MVFLAG = 0x40;
	396	static const int QFLAG = 0x20;
	397	static const int SFLAG = 0x10;
	398	static const int CFLAG = 0x08;
	399	static const int VFLAG = 0x04;
	400	static const int NFLAG = 0x02;
	401	static const int ZFLAG = 0x01;
	402	};
	403
	404
	405	// ======================> adsp2100_device_config
	406
	407	class adsp2100_device_config : public adsp21xx_device_config
	408	{
	409	friend class adsp2100_device;
	410
	411	// construction/destruction
	412	adsp2100_device_config(const machine_config &mconfig, const char tag, const device_config owner, UINT32 clock);
	413
	414	public:
	415	// allocators
	416	static device_config static_alloc_device_config(const machine_config &mconfig, const char tag, const device_config *owner, UINT32 clock);
	417	virtual device_t *alloc_device(running_machine &machine) const;
	418
	419	protected:
	420	// device_config_execute_interface overrides
	421	virtual UINT32 execute_input_lines() const;
	422
	423	// device_config_memory_interface overrides
	424	virtual const address_space_config *memory_space_config(int spacenum = 0) const;
	425	};
	426
	427
	428	// ======================> adsp2100_device
	429
	430	class adsp2100_device : public adsp21xx_device
	431	{
	432	friend class adsp2100_device_config;
	433
	434	// construction/destruction
	435	adsp2100_device(running_machine &_machine, const adsp2100_device_config &config);
	436
	437	// interrupts
	438	virtual bool generate_irq(int which, int indx);
	439	virtual void check_irqs();
	440	};
	441
	442
	443	// ======================> adsp2101_device_config
	444
	445	class adsp2101_device_config : public adsp21xx_device_config
	446	{
	447	friend class adsp2101_device;
	448
	449	protected:
	450	// construction/destruction
	451	adsp2101_device_config(const machine_config &mconfig, device_type type, const char name, const char tag, const device_config *owner, UINT32 clock, UINT32 chiptype);
	452
	453	public:
	454	// allocators
	455	static device_config static_alloc_device_config(const machine_config &mconfig, const char tag, const device_config *owner, UINT32 clock);
	456	virtual device_t *alloc_device(running_machine &machine) const;
	457
	458	protected:
	459	// device_config_execute_interface overrides
	460	virtual UINT32 execute_input_lines() const;
	461
	462	// device_config_memory_interface overrides
	463	virtual const address_space_config *memory_space_config(int spacenum = 0) const;
	464	};
	465
	466
	467	// ======================> adsp2101_device
	468
	469	class adsp2101_device : public adsp21xx_device
	470	{
	471	friend class adsp2101_device_config;
	472	friend class adsp2104_device_config;
	473	friend class adsp2105_device_config;
	474	friend class adsp2115_device_config;
	475
	476	protected:
	477	// construction/destruction
	478	adsp2101_device(running_machine &_machine, const adsp2101_device_config &config);
	479
	480	// interrupts
	481	virtual bool generate_irq(int which, int indx);
	482	virtual void check_irqs();
	483	};
	484
	485
	486	// ======================> adsp2181_device_config
	487
	488	class adsp2181_device_config : public adsp21xx_device_config
	489	{
	490	friend class adsp2181_device;
	491
	492	// construction/destruction
	493	adsp2181_device_config(const machine_config &mconfig, const char tag, const device_config owner, UINT32 clock);
	494
	495	public:
	496	// allocators
	497	static device_config static_alloc_device_config(const machine_config &mconfig, const char tag, const device_config *owner, UINT32 clock);
	498	virtual device_t *alloc_device(running_machine &machine) const;
	499
	500	protected:
	501	// device_config_execute_interface overrides
	502	virtual UINT32 execute_input_lines() const;
	503
	504	// device_config_memory_interface overrides
	505	virtual const address_space_config *memory_space_config(int spacenum = 0) const;
	506
	507	// address spaces
	508	const address_space_config m_io_config;
	509	};
	510
	511
	512	// ======================> adsp2181_device
	513
	514	class adsp2181_device : public adsp21xx_device
	515	{
	516	friend class adsp2181_device_config;
	517
	518	// construction/destruction
	519	adsp2181_device(running_machine &_machine, const adsp2181_device_config &config);
	520
	521	// interrupts
	522	virtual bool generate_irq(int which, int indx);
	523	virtual void check_irqs();
	524
	525	public:
	526	// public interfaces
	527	void idma_addr_w(UINT16 data);
	528	UINT16 idma_addr_r();
	529	void idma_data_w(UINT16 data);
	530	UINT16 idma_data_r();
	531	};
	532
	533
	534	// ======================> trivial variants
	535
	536	DECLARE_TRIVIAL_DERIVED_DEVICE(adsp2104_device_config, adsp2101_device_config, adsp2104_device, adsp2101_device)
	537	DECLARE_TRIVIAL_DERIVED_DEVICE(adsp2105_device_config, adsp2101_device_config, adsp2105_device, adsp2101_device)
	538	DECLARE_TRIVIAL_DERIVED_DEVICE(adsp2115_device_config, adsp2101_device_config, adsp2115_device, adsp2101_device)
	539
	540
	541
40	542	/***************************************************************************
41	543	REGISTER ENUMERATION
42	544	***************************************************************************/
r9081	r9082
69	571	PUBLIC FUNCTIONS
70	572	***************************************************************************/
71	573
72		#define ADSP2100_IRQ0 0 /* IRQ0 */
73		#define ADSP2100_SPORT1_RX 0 /* SPORT1 receive IRQ */
74		#define ADSP2100_IRQ1 1 /* IRQ1 */
75		#define ADSP2100_SPORT1_TX 1 /* SPORT1 transmit IRQ */
76		#define ADSP2100_IRQ2 2 /* IRQ2 */
77		#define ADSP2100_IRQ3 3 /* IRQ3 */
	574	#define ADSP2100_IRQ0 0 // IRQ0
	575	#define ADSP2100_SPORT1_RX 0 // SPORT1 receive IRQ
	576	#define ADSP2100_IRQ1 1 // IRQ1
	577	#define ADSP2100_SPORT1_TX 1 // SPORT1 transmit IRQ
	578	#define ADSP2100_IRQ2 2 // IRQ2
	579	#define ADSP2100_IRQ3 3 // IRQ3
78	580
79	581
80	582	/**************************************************************************
81	583	* ADSP2101 section
82	584	**************************************************************************/
83	585
84		#define ADSP2101_IRQ0 0 /* IRQ0 */
85		#define ADSP2101_SPORT1_RX 0 /* SPORT1 receive IRQ */
86		#define ADSP2101_IRQ1 1 /* IRQ1 */
87		#define ADSP2101_SPORT1_TX 1 /* SPORT1 transmit IRQ */
88		#define ADSP2101_IRQ2 2 /* IRQ2 */
89		#define ADSP2101_SPORT0_RX 3 /* SPORT0 receive IRQ */
90		#define ADSP2101_SPORT0_TX 4 /* SPORT0 transmit IRQ */
91		#define ADSP2101_TIMER 5 /* internal timer IRQ */
	586	#define ADSP2101_IRQ0 0 // IRQ0
	587	#define ADSP2101_SPORT1_RX 0 // SPORT1 receive IRQ
	588	#define ADSP2101_IRQ1 1 // IRQ1
	589	#define ADSP2101_SPORT1_TX 1 // SPORT1 transmit IRQ
	590	#define ADSP2101_IRQ2 2 // IRQ2
	591	#define ADSP2101_SPORT0_RX 3 // SPORT0 receive IRQ
	592	#define ADSP2101_SPORT0_TX 4 // SPORT0 transmit IRQ
	593	#define ADSP2101_TIMER 5 // internal timer IRQ
92	594
93	595
94	596	/**************************************************************************
95	597	* ADSP2104 section
96	598	**************************************************************************/
97	599
98		#define ADSP2104_IRQ0 0 /* IRQ0 */
99		#define ADSP2104_SPORT1_RX 0 /* SPORT1 receive IRQ */
100		#define ADSP2104_IRQ1 1 /* IRQ1 */
101		#define ADSP2104_SPORT1_TX 1 /* SPORT1 transmit IRQ */
102		#define ADSP2104_IRQ2 2 /* IRQ2 */
103		#define ADSP2104_SPORT0_RX 3 /* SPORT0 receive IRQ */
104		#define ADSP2104_SPORT0_TX 4 /* SPORT0 transmit IRQ */
105		#define ADSP2104_TIMER 5 /* internal timer IRQ */
	600	#define ADSP2104_IRQ0 0 // IRQ0
	601	#define ADSP2104_SPORT1_RX 0 // SPORT1 receive IRQ
	602	#define ADSP2104_IRQ1 1 // IRQ1
	603	#define ADSP2104_SPORT1_TX 1 // SPORT1 transmit IRQ
	604	#define ADSP2104_IRQ2 2 // IRQ2
	605	#define ADSP2104_SPORT0_RX 3 // SPORT0 receive IRQ
	606	#define ADSP2104_SPORT0_TX 4 // SPORT0 transmit IRQ
	607	#define ADSP2104_TIMER 5 // internal timer IRQ
106	608
107	609	void adsp2104_load_boot_data(UINT8 srcdata, UINT32 dstdata);
108	610
r9081	r9082
111	613	* ADSP2105 section
112	614	**************************************************************************/
113	615
114		#define ADSP2105_IRQ0 0 /* IRQ0 */
115		#define ADSP2105_SPORT1_RX 0 /* SPORT1 receive IRQ */
116		#define ADSP2105_IRQ1 1 /* IRQ1 */
117		#define ADSP2105_SPORT1_TX 1 /* SPORT1 transmit IRQ */
118		#define ADSP2105_IRQ2 2 /* IRQ2 */
119		#define ADSP2105_TIMER 5 /* internal timer IRQ */
	616	#define ADSP2105_IRQ0 0 // IRQ0
	617	#define ADSP2105_SPORT1_RX 0 // SPORT1 receive IRQ
	618	#define ADSP2105_IRQ1 1 // IRQ1
	619	#define ADSP2105_SPORT1_TX 1 // SPORT1 transmit IRQ
	620	#define ADSP2105_IRQ2 2 // IRQ2
	621	#define ADSP2105_TIMER 5 // internal timer IRQ
120	622
121	623	void adsp2105_load_boot_data(UINT8 srcdata, UINT32 dstdata);
122	624
r9081	r9082
125	627	* ADSP2115 section
126	628	**************************************************************************/
127	629
128		#define ADSP2115_IRQ0 0 /* IRQ0 */
129		#define ADSP2115_SPORT1_RX 0 /* SPORT1 receive IRQ */
130		#define ADSP2115_IRQ1 1 /* IRQ1 */
131		#define ADSP2115_SPORT1_TX 1 /* SPORT1 transmit IRQ */
132		#define ADSP2115_IRQ2 2 /* IRQ2 */
133		#define ADSP2115_SPORT0_RX 3 /* SPORT0 receive IRQ */
134		#define ADSP2115_SPORT0_TX 4 /* SPORT0 transmit IRQ */
135		#define ADSP2115_TIMER 5 /* internal timer IRQ */
	630	#define ADSP2115_IRQ0 0 // IRQ0
	631	#define ADSP2115_SPORT1_RX 0 // SPORT1 receive IRQ
	632	#define ADSP2115_IRQ1 1 // IRQ1
	633	#define ADSP2115_SPORT1_TX 1 // SPORT1 transmit IRQ
	634	#define ADSP2115_IRQ2 2 // IRQ2
	635	#define ADSP2115_SPORT0_RX 3 // SPORT0 receive IRQ
	636	#define ADSP2115_SPORT0_TX 4 // SPORT0 transmit IRQ
	637	#define ADSP2115_TIMER 5 // internal timer IRQ
136	638
137	639	void adsp2115_load_boot_data(UINT8 srcdata, UINT32 dstdata);
138	640
r9081	r9082
141	643	* ADSP2181 section
142	644	**************************************************************************/
143	645
144		#define ADSP2181_IRQ0 0 /* IRQ0 */
145		#define ADSP2181_SPORT1_RX 0 /* SPORT1 receive IRQ */
146		#define ADSP2181_IRQ1 1 /* IRQ1 */
147		#define ADSP2181_SPORT1_TX 1 /* SPORT1 transmit IRQ */
148		#define ADSP2181_IRQ2 2 /* IRQ2 */
149		#define ADSP2181_SPORT0_RX 3 /* SPORT0 receive IRQ */
150		#define ADSP2181_SPORT0_TX 4 /* SPORT0 transmit IRQ */
151		#define ADSP2181_TIMER 5 /* internal timer IRQ */
152		#define ADSP2181_IRQE 6 /* IRQE */
153		#define ADSP2181_IRQL1 7 /* IRQL1 */
154		#define ADSP2181_IRQL2 8 /* IRQL2 */
	646	#define ADSP2181_IRQ0 0 // IRQ0
	647	#define ADSP2181_SPORT1_RX 0 // SPORT1 receive IRQ
	648	#define ADSP2181_IRQ1 1 // IRQ1
	649	#define ADSP2181_SPORT1_TX 1 // SPORT1 transmit IRQ
	650	#define ADSP2181_IRQ2 2 // IRQ2
	651	#define ADSP2181_SPORT0_RX 3 // SPORT0 receive IRQ
	652	#define ADSP2181_SPORT0_TX 4 // SPORT0 transmit IRQ
	653	#define ADSP2181_TIMER 5 // internal timer IRQ
	654	#define ADSP2181_IRQE 6 // IRQE
	655	#define ADSP2181_IRQL1 7 // IRQL1
	656	#define ADSP2181_IRQL2 8 // IRQL2
155	657
156		void adsp2181_load_boot_data(UINT8 srcdata, UINT32 dstdata);
157		void adsp2181_idma_addr_w(running_device *device, UINT16 data);
158		UINT16 adsp2181_idma_addr_r(running_device *device);
159		void adsp2181_idma_data_w(running_device *device, UINT16 data);
160		UINT16 adsp2181_idma_data_r(running_device *device);
161
162
163	658	#endif /* __ADSP2100_H__ */

src/emu/cpu/adsp2100/2100ops.c
r9081	r9082
2	2	ASTAT -- ALU/MAC status register
3	3	===========================================================================*/
4	4
5		/* flag definitions */
6		#define SSFLAG 0x80
7		#define MVFLAG 0x40
8		#define QFLAG 0x20
9		#define SFLAG 0x10
10		#define CFLAG 0x08
11		#define VFLAG 0x04
12		#define NFLAG 0x02
13		#define ZFLAG 0x01
14
15	5	/* extracts flags */
16		#define GET_SS (adsp->astat & SSFLAG)
17		#define GET_MV (adsp->astat & MVFLAG)
18		#define GET_Q (adsp->astat & QFLAG)
19		#define GET_S (adsp->astat & SFLAG)
20		#define GET_C (adsp->astat & CFLAG)
21		#define GET_V (adsp->astat & VFLAG)
22		#define GET_N (adsp->astat & NFLAG)
23		#define GET_Z (adsp->astat & ZFLAG)
	6	#define GET_SS (m_astat & SSFLAG)
	7	#define GET_MV (m_astat & MVFLAG)
	8	#define GET_Q (m_astat & QFLAG)
	9	#define GET_S (m_astat & SFLAG)
	10	#define GET_C (m_astat & CFLAG)
	11	#define GET_V (m_astat & VFLAG)
	12	#define GET_N (m_astat & NFLAG)
	13	#define GET_Z (m_astat & ZFLAG)
24	14
25	15	/* clears flags */
26		#define CLR_SS (adsp->astat &= ~SSFLAG)
27		#define CLR_MV (adsp->astat &= ~MVFLAG)
28		#define CLR_Q (adsp->astat &= ~QFLAG)
29		#define CLR_S (adsp->astat &= ~SFLAG)
30		#define CLR_C (adsp->astat &= ~CFLAG)
31		#define CLR_V (adsp->astat &= ~VFLAG)
32		#define CLR_N (adsp->astat &= ~NFLAG)
33		#define CLR_Z (adsp->astat &= ~ZFLAG)
	16	#define CLR_SS (m_astat &= ~SSFLAG)
	17	#define CLR_MV (m_astat &= ~MVFLAG)
	18	#define CLR_Q (m_astat &= ~QFLAG)
	19	#define CLR_S (m_astat &= ~SFLAG)
	20	#define CLR_C (m_astat &= ~CFLAG)
	21	#define CLR_V (m_astat &= ~VFLAG)
	22	#define CLR_N (m_astat &= ~NFLAG)
	23	#define CLR_Z (m_astat &= ~ZFLAG)
34	24
35	25	/* sets flags */
36		#define SET_SS (adsp->astat \|= SSFLAG)
37		#define SET_MV (adsp->astat \|= MVFLAG)
38		#define SET_Q (adsp->astat \|= QFLAG)
39		#define SET_S (adsp->astat \|= SFLAG)
40		#define SET_C (adsp->astat \|= CFLAG)
41		#define SET_V (adsp->astat \|= VFLAG)
42		#define SET_Z (adsp->astat \|= ZFLAG)
43		#define SET_N (adsp->astat \|= NFLAG)
	26	#define SET_SS (m_astat \|= SSFLAG)
	27	#define SET_MV (m_astat \|= MVFLAG)
	28	#define SET_Q (m_astat \|= QFLAG)
	29	#define SET_S (m_astat \|= SFLAG)
	30	#define SET_C (m_astat \|= CFLAG)
	31	#define SET_V (m_astat \|= VFLAG)
	32	#define SET_Z (m_astat \|= ZFLAG)
	33	#define SET_N (m_astat \|= NFLAG)
44	34
45	35	/* flag clearing; must be done before setting */
46		#define CLR_FLAGS (ads~~p->as~~tat &= ~~adsp->~~astat_clear)
	36	#define CLR_FLAGS (m_astat &= m_astat_clear)
47	37
48	38	/* compute flags */
49		#define CALC_Z(r) (adsp->astat \|= ((r & 0xffff) == 0))
50		#define CALC_N(r) (adsp->astat \|= (r >> 14) & 0x02)
51		#define CALC_V(s,d,r) (adsp->astat \|= ((s ^ d ^ r ^ (r >> 1)) >> 13) & 0x04)
52		#define CALC_C(r) (adsp->astat \|= (r >> 13) & 0x08)
53		#define CALC_C_SUB(r) (adsp->astat \|= (~r >> 13) & 0x08)
	39	#define CALC_Z(r) (m_astat \|= ((r & 0xffff) == 0))
	40	#define CALC_N(r) (m_astat \|= (r >> 14) & 0x02)
	41	#define CALC_V(s,d,r) (m_astat \|= ((s ^ d ^ r ^ (r >> 1)) >> 13) & 0x04)
	42	#define CALC_C(r) (m_astat \|= (r >> 13) & 0x08)
	43	#define CALC_C_SUB(r) (m_astat \|= (~r >> 13) & 0x08)
54	44	#define CALC_NZ(r) CLR_FLAGS; CALC_N(r); CALC_Z(r)
55	45	#define CALC_NZV(s,d,r) CLR_FLAGS; CALC_N(r); CALC_Z(r); CALC_V(s,d,r)
56	46	#define CALC_NZVC(s,d,r) CLR_FLAGS; CALC_N(r); CALC_Z(r); CALC_V(s,d,r); CALC_C(r)
r9081	r9082
81	71	#define MSTAT_GOMODE 0x40 /* go mode enable */
82	72
83	73	/* you must call this in order to change MSTAT */
84		~~INLINE~~ void update_mstat(~~adsp2100_state *adsp~~)
	74	inline void adsp21xx_device::update_mstat()
85	75	{
86		if ((~~adsp->~~mstat ^ ~~adsp->~~mstat_prev) & MSTAT_BANK)
	76	if ((m_mstat ^ m_mstat_prev) & MSTAT_BANK)
87	77	{
88		ADSPCORE temp = adsp->core;
89		adsp->core = adsp->alt;
90		adsp->alt = temp;
	78	adsp_core temp = m_core;
	79	m_core = m_alt;
	80	m_alt = temp;
91	81	}
92		if ((adsp->mstat ^ adsp->mstat_prev) & MSTAT_TIMER)
93		if (adsp->timer_fired != NULL)
94		(adsp->timer_fired)(adsp->device, (adsp->mstat & MSTAT_TIMER) != 0);
95		if (adsp->mstat & MSTAT_STICKYV)
96		adsp->astat_clear = ~(CFLAG \| NFLAG \| ZFLAG);
	82	if ((m_mstat ^ m_mstat_prev) & MSTAT_TIMER)
	83	if (m_config.m_timer_fired != NULL)
	84	(m_config.m_timer_fired)(this, (m_mstat & MSTAT_TIMER) != 0);
	85	if (m_mstat & MSTAT_STICKYV)
	86	m_astat_clear = ~(CFLAG \| NFLAG \| ZFLAG);
97	87	else
98		adsp->astat_clear = ~(CFLAG \| VFLAG \| NFLAG \| ZFLAG);
99		adsp->mstat_prev = adsp->mstat;
	88	m_astat_clear = ~(CFLAG \| VFLAG \| NFLAG \| ZFLAG);
	89	m_mstat_prev = m_mstat;
100	90	}
101	91
102	92
r9081	r9082
120	110	PC stack handlers
121	111	===========================================================================*/
122	112
123		~~INLINE~~ UINT32 pc_stack_top(~~adsp2100_state *adsp~~)
	113	inline UINT32 adsp21xx_device::pc_stack_top()
124	114	{
125		if (adsp->pc_sp > 0)
126		return adsp->pc_stack[adsp->pc_sp - 1];
	115	if (m_pc_sp > 0)
	116	return m_pc_stack[m_pc_sp - 1];
127	117	else
128		return ~~adsp->~~pc_stack[0];
	118	return m_pc_stack[0];
129	119	}
130	120
131		~~INLINE~~ void set_pc_stack_top(~~adsp2100_state *adsp,~~ UINT32 top)
	121	inline void adsp21xx_device::set_pc_stack_top(UINT32 top)
132	122	{
133		if (adsp->pc_sp > 0)
134		adsp->pc_stack[adsp->pc_sp - 1] = top;
	123	if (m_pc_sp > 0)
	124	m_pc_stack[m_pc_sp - 1] = top;
135	125	else
136		~~adsp->~~pc_stack[0] = top;
	126	m_pc_stack[0] = top;
137	127	}
138	128
139		~~INLINE~~ void pc_stack_push(~~adsp2100_state *adsp~~)
	129	inline void adsp21xx_device::pc_stack_push()
140	130	{
141		if (~~adsp->~~pc_sp < PC_STACK_DEPTH)
	131	if (m_pc_sp < PC_STACK_DEPTH)
142	132	{
143		adsp->pc_stack[adsp->pc_sp] = adsp->pc;
144		adsp->pc_sp++;
145		adsp->sstat &= ~PC_EMPTY;
	133	m_pc_stack[m_pc_sp] = m_pc;
	134	m_pc_sp++;
	135	m_sstat &= ~PC_EMPTY;
146	136	}
147	137	else
148		~~adsp->~~sstat \|= PC_OVER;
	138	m_sstat \|= PC_OVER;
149	139	}
150	140
151		~~INLINE~~ void pc_stack_push_val(~~adsp2100_state *adsp,~~ UINT32 val)
	141	inline void adsp21xx_device::pc_stack_push_val(UINT32 val)
152	142	{
153		if (~~adsp->~~pc_sp < PC_STACK_DEPTH)
	143	if (m_pc_sp < PC_STACK_DEPTH)
154	144	{
155		adsp->pc_stack[adsp->pc_sp] = val;
156		adsp->pc_sp++;
157		adsp->sstat &= ~PC_EMPTY;
	145	m_pc_stack[m_pc_sp] = val;
	146	m_pc_sp++;
	147	m_sstat &= ~PC_EMPTY;
158	148	}
159	149	else
160		~~adsp->~~sstat \|= PC_OVER;
	150	m_sstat \|= PC_OVER;
161	151	}
162	152
163		~~INLINE~~ void pc_stack_pop(~~adsp2100_state *adsp~~)
	153	inline void adsp21xx_device::pc_stack_pop()
164	154	{
165		if (~~adsp->~~pc_sp > 0)
	155	if (m_pc_sp > 0)
166	156	{
167		adsp->pc_sp--;
168		if (adsp->pc_sp == 0)
169		adsp->sstat \|= PC_EMPTY;
	157	m_pc_sp--;
	158	if (m_pc_sp == 0)
	159	m_sstat \|= PC_EMPTY;
170	160	}
171		~~ads~~p~~->p~~c = ~~ads~~p~~->p~~c_stack[~~adsp->~~pc_sp];
	161	m_pc = m_pc_stack[m_pc_sp];
172	162	}
173	163
174		~~INLINE~~ UINT32 pc_stack_pop_val(~~adsp2100_state *adsp~~)
	164	inline UINT32 adsp21xx_device::pc_stack_pop_val()
175	165	{
176		if (~~adsp->~~pc_sp > 0)
	166	if (m_pc_sp > 0)
177	167	{
178		adsp->pc_sp--;
179		if (adsp->pc_sp == 0)
180		adsp->sstat \|= PC_EMPTY;
	168	m_pc_sp--;
	169	if (m_pc_sp == 0)
	170	m_sstat \|= PC_EMPTY;
181	171	}
182		return ~~ads~~p~~->p~~c_stack[~~adsp->~~pc_sp];
	172	return m_pc_stack[m_pc_sp];
183	173	}
184	174
185	175
r9081	r9082
187	177	CNTR stack handlers
188	178	===========================================================================*/
189	179
190		~~INLINE~~ UINT32 cntr_stack_top(~~adsp2100_state *adsp~~)
	180	inline UINT32 adsp21xx_device::cntr_stack_top()
191	181	{
192		if (adsp->cntr_sp > 0)
193		return adsp->cntr_stack[adsp->cntr_sp - 1];
	182	if (m_cntr_sp > 0)
	183	return m_cntr_stack[m_cntr_sp - 1];
194	184	else
195		return ~~adsp->~~cntr_stack[0];
	185	return m_cntr_stack[0];
196	186	}
197	187
198		~~INLINE~~ void cntr_stack_push(~~adsp2100_state *adsp~~)
	188	inline void adsp21xx_device::cntr_stack_push()
199	189	{
200		if (~~adsp->~~cntr_sp < CNTR_STACK_DEPTH)
	190	if (m_cntr_sp < CNTR_STACK_DEPTH)
201	191	{
202		adsp->cntr_stack[adsp->cntr_sp] = adsp->cntr;
203		adsp->cntr_sp++;
204		adsp->sstat &= ~COUNT_EMPTY;
	192	m_cntr_stack[m_cntr_sp] = m_cntr;
	193	m_cntr_sp++;
	194	m_sstat &= ~COUNT_EMPTY;
205	195	}
206	196	else
207		~~adsp->~~sstat \|= COUNT_OVER;
	197	m_sstat \|= COUNT_OVER;
208	198	}
209	199
210		~~INLINE~~ void cntr_stack_pop(~~adsp2100_state *adsp~~)
	200	inline void adsp21xx_device::cntr_stack_pop()
211	201	{
212		if (~~adsp->~~cntr_sp > 0)
	202	if (m_cntr_sp > 0)
213	203	{
214		adsp->cntr_sp--;
215		if (adsp->cntr_sp == 0)
216		adsp->sstat \|= COUNT_EMPTY;
	204	m_cntr_sp--;
	205	if (m_cntr_sp == 0)
	206	m_sstat \|= COUNT_EMPTY;
217	207	}
218		~~adsp->~~cntr = ~~adsp->~~cntr_stack[~~adsp->~~cntr_sp];
	208	m_cntr = m_cntr_stack[m_cntr_sp];
219	209	}
220	210
221	211
r9081	r9082
223	213	LOOP stack handlers
224	214	===========================================================================*/
225	215
226		~~INLINE~~ UINT32 loop_stack_top(~~adsp2100_state *adsp~~)
	216	inline UINT32 adsp21xx_device::loop_stack_top()
227	217	{
228		if (adsp->loop_sp > 0)
229		return adsp->loop_stack[adsp->loop_sp - 1];
	218	if (m_loop_sp > 0)
	219	return m_loop_stack[m_loop_sp - 1];
230	220	else
231		return ~~adsp->~~loop_stack[0];
	221	return m_loop_stack[0];
232	222	}
233	223
234		~~INLINE~~ void loop_stack_push(~~adsp2100_state *adsp,~~ UINT32 value)
	224	inline void adsp21xx_device::loop_stack_push(UINT32 value)
235	225	{
236		if (~~adsp->~~loop_sp < LOOP_STACK_DEPTH)
	226	if (m_loop_sp < LOOP_STACK_DEPTH)
237	227	{
238		adsp->loop_stack[adsp->loop_sp] = value;
239		adsp->loop_sp++;
240		adsp->loop = value >> 4;
241		adsp->loop_condition = value & 15;
242		adsp->sstat &= ~LOOP_EMPTY;
	228	m_loop_stack[m_loop_sp] = value;
	229	m_loop_sp++;
	230	m_loop = value >> 4;
	231	m_loop_condition = value & 15;
	232	m_sstat &= ~LOOP_EMPTY;
243	233	}
244	234	else
245		~~adsp->~~sstat \|= LOOP_OVER;
	235	m_sstat \|= LOOP_OVER;
246	236	}
247	237
248		~~INLINE~~ void loop_stack_pop(~~adsp2100_state *adsp~~)
	238	inline void adsp21xx_device::loop_stack_pop()
249	239	{
250		if (~~adsp->~~loop_sp > 0)
	240	if (m_loop_sp > 0)
251	241	{
252		adsp->loop_sp--;
253		if (adsp->loop_sp == 0)
	242	m_loop_sp--;
	243	if (m_loop_sp == 0)
254	244	{
255		adsp->loop = 0xffff;
256		adsp->loop_condition = 0;
257		adsp->sstat \|= LOOP_EMPTY;
	245	m_loop = 0xffff;
	246	m_loop_condition = 0;
	247	m_sstat \|= LOOP_EMPTY;
258	248	}
259	249	else
260	250	{
261		adsp->loop = adsp->loop_stack[adsp->loop_sp -1] >> 4;
262		adsp->loop_condition = adsp->loop_stack[adsp->loop_sp - 1] & 15;
	251	m_loop = m_loop_stack[m_loop_sp -1] >> 4;
	252	m_loop_condition = m_loop_stack[m_loop_sp - 1] & 15;
263	253	}
264	254	}
265	255	}
r9081	r9082
269	259	STAT stack handlers
270	260	===========================================================================*/
271	261
272		~~INLINE~~ void stat_stack_push(~~adsp2100_state *adsp~~)
	262	inline void adsp21xx_device::stat_stack_push()
273	263	{
274		if (~~adsp->~~stat_sp < STAT_STACK_DEPTH)
	264	if (m_stat_sp < STAT_STACK_DEPTH)
275	265	{
276		adsp->stat_stack[adsp->stat_sp][0] = adsp->mstat;
277		adsp->stat_stack[adsp->stat_sp][1] = adsp->imask;
278		adsp->stat_stack[adsp->stat_sp][2] = adsp->astat;
279		adsp->stat_sp++;
280		adsp->sstat &= ~STATUS_EMPTY;
	266	m_stat_stack[m_stat_sp][0] = m_mstat;
	267	m_stat_stack[m_stat_sp][1] = m_imask;
	268	m_stat_stack[m_stat_sp][2] = m_astat;
	269	m_stat_sp++;
	270	m_sstat &= ~STATUS_EMPTY;
281	271	}
282	272	else
283		~~adsp->~~sstat \|= STATUS_OVER;
	273	m_sstat \|= STATUS_OVER;
284	274	}
285	275
286		~~INLINE~~ void stat_stack_pop(~~adsp2100_state *adsp~~)
	276	inline void adsp21xx_device::stat_stack_pop()
287	277	{
288		if (~~adsp->~~stat_sp > 0)
	278	if (m_stat_sp > 0)
289	279	{
290		adsp->stat_sp--;
291		if (adsp->stat_sp == 0)
292		adsp->sstat \|= STATUS_EMPTY;
	280	m_stat_sp--;
	281	if (m_stat_sp == 0)
	282	m_sstat \|= STATUS_EMPTY;
293	283	}
294		adsp->mstat = adsp->stat_stack[adsp->stat_sp][0];
295		update_mstat(adsp);
296		adsp->imask = adsp->stat_stack[adsp->stat_sp][1];
297		adsp->astat = adsp->stat_stack[adsp->stat_sp][2];
298		check_irqs(adsp);
	284	m_mstat = m_stat_stack[m_stat_sp][0];
	285	update_mstat();
	286	m_imask = m_stat_stack[m_stat_sp][1];
	287	m_astat = m_stat_stack[m_stat_sp][2];
	288	check_irqs();
299	289	}
300	290
301	291
r9081	r9082
304	294	condition code checking
305	295	===========================================================================*/
306	296
307		INLINE int CONDITION(adsp2100_state *adsp, int c)
	297	// gcc doesn't want to inline this, so we use a macro
	298	#define condition(c) (((c) != 14) ? (m_condition_table[((c) << 8) \| m_astat]) : slow_condition())
	299
	300	/*
	301	inline int adsp21xx_device::condition(int c)
308	302	{
309	303	if (c != 14)
310		return condition_table[((c) << 8) \| adsp->astat];
311		else if ((INT32)--adsp->cntr > 0)
	304	return m_condition_table[((c) << 8) \| m_astat];
	305	else
	306	return slow_condition(c);
	307	}
	308	*/
	309
	310	int adsp21xx_device::slow_condition()
	311	{
	312	if ((INT32)--m_cntr > 0)
312	313	return 1;
313	314	else
314	315	{
315		cntr_stack_pop(~~adsp~~);
	316	cntr_stack_pop();
316	317	return 0;
317	318	}
318	319	}
r9081	r9082
323	324	register writing
324	325	===========================================================================*/
325	326
326		~~INLINE~~ void ~~upd~~a~~te_i(a~~dsp2100_state *adsp, int which)
	327	inline void adsp21xx_device::update_i(int which)
327	328	{
328		~~adsp->~~base[which] = ~~adsp->~~i[which] & ~~adsp->~~lmask[which];
	329	m_base[which] = m_i[which] & m_lmask[which];
329	330	}
330	331
331		~~INLINE~~ void ~~upd~~a~~te_l(a~~dsp2100_state *adsp, int which)
	332	inline void adsp21xx_device::update_l(int which)
332	333	{
333		adsp->lmask[which] = mask_table[adsp->l[which] & 0x3fff];
334		adsp->base[which] = adsp->i[which] & adsp->lmask[which];
	334	m_lmask[which] = m_mask_table[m_l[which] & 0x3fff];
	335	m_base[which] = m_i[which] & m_lmask[which];
335	336	}
336	337
337		static void wr_inval(adsp2100_state *adsp, INT32 val) { logerror( "ADSP %04x: Writing to an invalid register!\n", adsp->ppc ); }
338		static void wr_ax0(adsp2100_state *adsp, INT32 val) { adsp->core.ax0.s = val; }
339		static void wr_ax1(adsp2100_state *adsp, INT32 val) { adsp->core.ax1.s = val; }
340		static void wr_mx0(adsp2100_state *adsp, INT32 val) { adsp->core.mx0.s = val; }
341		static void wr_mx1(adsp2100_state *adsp, INT32 val) { adsp->core.mx1.s = val; }
342		static void wr_ay0(adsp2100_state *adsp, INT32 val) { adsp->core.ay0.s = val; }
343		static void wr_ay1(adsp2100_state *adsp, INT32 val) { adsp->core.ay1.s = val; }
344		static void wr_my0(adsp2100_state *adsp, INT32 val) { adsp->core.my0.s = val; }
345		static void wr_my1(adsp2100_state *adsp, INT32 val) { adsp->core.my1.s = val; }
346		static void wr_si(adsp2100_state *adsp, INT32 val) { adsp->core.si.s = val; }
347		static void wr_se(adsp2100_state *adsp, INT32 val) { adsp->core.se.s = (INT8)val; }
348		static void wr_ar(adsp2100_state *adsp, INT32 val) { adsp->core.ar.s = val; }
349		static void wr_mr0(adsp2100_state *adsp, INT32 val) { adsp->core.mr.mrx.mr0.s = val; }
350		static void wr_mr1(adsp2100_state *adsp, INT32 val) { adsp->core.mr.mrx.mr1.s = val; adsp->core.mr.mrx.mr2.s = (INT16)val >> 15; }
351		static void wr_mr2(adsp2100_state *adsp, INT32 val) { adsp->core.mr.mrx.mr2.s = (INT8)val; }
352		static void wr_sr0(adsp2100_state *adsp, INT32 val) { adsp->core.sr.srx.sr0.s = val; }
353		static void wr_sr1(adsp2100_state *adsp, INT32 val) { adsp->core.sr.srx.sr1.s = val; }
354		static void wr_i0(adsp2100_state *adsp, INT32 val) { adsp->i[0] = val & 0x3fff; update_i(adsp, 0); }
355		static void wr_i1(adsp2100_state *adsp, INT32 val) { adsp->i[1] = val & 0x3fff; update_i(adsp, 1); }
356		static void wr_i2(adsp2100_state *adsp, INT32 val) { adsp->i[2] = val & 0x3fff; update_i(adsp, 2); }
357		static void wr_i3(adsp2100_state *adsp, INT32 val) { adsp->i[3] = val & 0x3fff; update_i(adsp, 3); }
358		static void wr_i4(adsp2100_state *adsp, INT32 val) { adsp->i[4] = val & 0x3fff; update_i(adsp, 4); }
359		static void wr_i5(adsp2100_state *adsp, INT32 val) { adsp->i[5] = val & 0x3fff; update_i(adsp, 5); }
360		static void wr_i6(adsp2100_state *adsp, INT32 val) { adsp->i[6] = val & 0x3fff; update_i(adsp, 6); }
361		static void wr_i7(adsp2100_state *adsp, INT32 val) { adsp->i[7] = val & 0x3fff; update_i(adsp, 7); }
362		static void wr_m0(adsp2100_state *adsp, INT32 val) { adsp->m[0] = (INT32)(val << 18) >> 18; }
363		static void wr_m1(adsp2100_state *adsp, INT32 val) { adsp->m[1] = (INT32)(val << 18) >> 18; }
364		static void wr_m2(adsp2100_state *adsp, INT32 val) { adsp->m[2] = (INT32)(val << 18) >> 18; }
365		static void wr_m3(adsp2100_state *adsp, INT32 val) { adsp->m[3] = (INT32)(val << 18) >> 18; }
366		static void wr_m4(adsp2100_state *adsp, INT32 val) { adsp->m[4] = (INT32)(val << 18) >> 18; }
367		static void wr_m5(adsp2100_state *adsp, INT32 val) { adsp->m[5] = (INT32)(val << 18) >> 18; }
368		static void wr_m6(adsp2100_state *adsp, INT32 val) { adsp->m[6] = (INT32)(val << 18) >> 18; }
369		static void wr_m7(adsp2100_state *adsp, INT32 val) { adsp->m[7] = (INT32)(val << 18) >> 18; }
370		static void wr_l0(adsp2100_state *adsp, INT32 val) { adsp->l[0] = val & 0x3fff; update_l(adsp, 0); }
371		static void wr_l1(adsp2100_state *adsp, INT32 val) { adsp->l[1] = val & 0x3fff; update_l(adsp, 1); }
372		static void wr_l2(adsp2100_state *adsp, INT32 val) { adsp->l[2] = val & 0x3fff; update_l(adsp, 2); }
373		static void wr_l3(adsp2100_state *adsp, INT32 val) { adsp->l[3] = val & 0x3fff; update_l(adsp, 3); }
374		static void wr_l4(adsp2100_state *adsp, INT32 val) { adsp->l[4] = val & 0x3fff; update_l(adsp, 4); }
375		static void wr_l5(adsp2100_state *adsp, INT32 val) { adsp->l[5] = val & 0x3fff; update_l(adsp, 5); }
376		static void wr_l6(adsp2100_state *adsp, INT32 val) { adsp->l[6] = val & 0x3fff; update_l(adsp, 6); }
377		static void wr_l7(adsp2100_state *adsp, INT32 val) { adsp->l[7] = val & 0x3fff; update_l(adsp, 7); }
378		static void wr_astat(adsp2100_state *adsp, INT32 val) { adsp->astat = val & 0x00ff; }
379		static void wr_mstat(adsp2100_state *adsp, INT32 val) { adsp->mstat = val & adsp->mstat_mask; update_mstat(adsp); }
380		static void wr_imask(adsp2100_state *adsp, INT32 val) { adsp->imask = val & adsp->imask_mask; check_irqs(adsp); }
381		static void wr_icntl(adsp2100_state *adsp, INT32 val) { adsp->icntl = val & 0x001f; check_irqs(adsp); }
382		static void wr_cntr(adsp2100_state *adsp, INT32 val) { cntr_stack_push(adsp); adsp->cntr = val & 0x3fff; }
383		static void wr_sb(adsp2100_state *adsp, INT32 val) { adsp->core.sb.s = (INT32)(val << 27) >> 27; }
384		static void wr_px(adsp2100_state *adsp, INT32 val) { adsp->px = val; }
385		static void wr_ifc(adsp2100_state *adsp, INT32 val)
	338	void adsp21xx_device::write_reg0(int regnum, INT32 val)
386	339	{
387		adsp->ifc = val;
388		if (adsp->chip_type >= CHIP_TYPE_ADSP2181)
	340	switch (regnum)
389	341	{
390		/* clear timer */
391		if (val & 0x0002) adsp->irq_latch[ADSP2181_IRQ0] = 0;
392		if (val & 0x0004) adsp->irq_latch[ADSP2181_IRQ1] = 0;
393		/* clear BDMA */
394		if (val & 0x0010) adsp->irq_latch[ADSP2181_IRQE] = 0;
395		if (val & 0x0020) adsp->irq_latch[ADSP2181_SPORT0_RX] = 0;
396		if (val & 0x0040) adsp->irq_latch[ADSP2181_SPORT0_TX] = 0;
397		if (val & 0x0080) adsp->irq_latch[ADSP2181_IRQ2] = 0;
398		/* force timer */
399		if (val & 0x0200) adsp->irq_latch[ADSP2181_IRQ0] = 1;
400		if (val & 0x0400) adsp->irq_latch[ADSP2181_IRQ1] = 1;
401		/* force BDMA */
402		if (val & 0x1000) adsp->irq_latch[ADSP2181_IRQE] = 1;
403		if (val & 0x2000) adsp->irq_latch[ADSP2181_SPORT0_RX] = 1;
404		if (val & 0x4000) adsp->irq_latch[ADSP2181_SPORT0_TX] = 1;
405		if (val & 0x8000) adsp->irq_latch[ADSP2181_IRQ2] = 1;
	342	case 0x00: m_core.ax0.s = val; break;
	343	case 0x01: m_core.ax1.s = val; break;
	344	case 0x02: m_core.mx0.s = val; break;
	345	case 0x03: m_core.mx1.s = val; break;
	346	case 0x04: m_core.ay0.s = val; break;
	347	case 0x05: m_core.ay1.s = val; break;
	348	case 0x06: m_core.my0.s = val; break;
	349	case 0x07: m_core.my1.s = val; break;
	350	case 0x08: m_core.si.s = val; break;
	351	case 0x09: m_core.se.s = (INT8)val; break;
	352	case 0x0a: m_core.ar.s = val; break;
	353	case 0x0b: m_core.mr.mrx.mr0.s = val; break;
	354	case 0x0c: m_core.mr.mrx.mr1.s = val; m_core.mr.mrx.mr2.s = (INT16)val >> 15; break;
	355	case 0x0d: m_core.mr.mrx.mr2.s = (INT8)val; break;
	356	case 0x0e: m_core.sr.srx.sr0.s = val; break;
	357	case 0x0f: m_core.sr.srx.sr1.s = val; break;
406	358	}
407		else
	359	}
	360
	361	void adsp21xx_device::write_reg1(int regnum, INT32 val)
	362	{
	363	int index = regnum & 3;
	364	switch (regnum >> 2)
408	365	{
409		/* clear timer */
410		if (val & 0x002) adsp->irq_latch[ADSP2101_IRQ0] = 0;
411		if (val & 0x004) adsp->irq_latch[ADSP2101_IRQ1] = 0;
412		if (val & 0x008) adsp->irq_latch[ADSP2101_SPORT0_RX] = 0;
413		if (val & 0x010) adsp->irq_latch[ADSP2101_SPORT0_TX] = 0;
414		if (val & 0x020) adsp->irq_latch[ADSP2101_IRQ2] = 0;
415		/* set timer */
416		if (val & 0x080) adsp->irq_latch[ADSP2101_IRQ0] = 1;
417		if (val & 0x100) adsp->irq_latch[ADSP2101_IRQ1] = 1;
418		if (val & 0x200) adsp->irq_latch[ADSP2101_SPORT0_RX] = 1;
419		if (val & 0x400) adsp->irq_latch[ADSP2101_SPORT0_TX] = 1;
420		if (val & 0x800) adsp->irq_latch[ADSP2101_IRQ2] = 1;
	366	case 0:
	367	m_i[index] = val & 0x3fff;
	368	update_i(index);
	369	break;
	370
	371	case 1:
	372	m_m[index] = (INT32)(val << 18) >> 18;
	373	break;
	374
	375	case 2:
	376	m_l[index] = val & 0x3fff;
	377	update_l(index);
	378	break;
	379
	380	case 3:
	381	logerror("ADSP %04x: Writing to an invalid register!\n", m_ppc);
	382	break;
421	383	}
422		check_irqs(adsp);
423	384	}
424		static void wr_tx0(adsp2100_state adsp, INT32 val) { if (adsp->sport_tx_callback) (adsp->sport_tx_callback)(*adsp->device, 0, val); }
425		static void wr_tx1(adsp2100_state adsp, INT32 val) { if (adsp->sport_tx_callback) (adsp->sport_tx_callback)(*adsp->device, 1, val); }
426		static void wr_owrctr(adsp2100_state *adsp, INT32 val) { adsp->cntr = val & 0x3fff; }
427		static void wr_topstack(adsp2100_state *adsp, INT32 val) { pc_stack_push_val(adsp, val & 0x3fff); }
	385
	386	void adsp21xx_device::write_reg2(int regnum, INT32 val)
	387	{
	388	int index = 4 + (regnum & 3);
	389	switch (regnum >> 2)
	390	{
	391	case 0:
	392	m_i[index] = val & 0x3fff;
	393	update_i(index);
	394	break;
	395
	396	case 1:
	397	m_m[index] = (INT32)(val << 18) >> 18;
	398	break;
	399
	400	case 2:
	401	m_l[index] = val & 0x3fff;
	402	update_l(index);
	403	break;
	404
	405	case 3:
	406	logerror("ADSP %04x: Writing to an invalid register!\n", m_ppc);
	407	break;
	408	}
	409	}
428	410
429		#define WRITE_REG(adsp,grp,reg,val) ((*wr_reg[grp][reg])(adsp,val))
430
431		static void (const wr_reg[4][16])(adsp2100_state, INT32) =
	411	void adsp21xx_device::write_reg3(int regnum, INT32 val)
432	412	{
	413	switch (regnum)
433	414	{
434		wr_ax0, wr_ax1, wr_mx0, wr_mx1, wr_ay0, wr_ay1, wr_my0, wr_my1,
435		wr_si, wr_se, wr_ar, wr_mr0, wr_mr1, wr_mr2, wr_sr0, wr_sr1
436		},
437		{
438		wr_i0, wr_i1, wr_i2, wr_i3, wr_m0, wr_m1, wr_m2, wr_m3,
439		wr_l0, wr_l1, wr_l2, wr_l3, wr_inval, wr_inval, wr_inval, wr_inval
440		},
441		{
442		wr_i4, wr_i5, wr_i6, wr_i7, wr_m4, wr_m5, wr_m6, wr_m7,
443		wr_l4, wr_l5, wr_l6, wr_l7, wr_inval, wr_inval, wr_inval, wr_inval
444		},
445		{
446		wr_astat, wr_mstat, wr_inval, wr_imask, wr_icntl, wr_cntr, wr_sb, wr_px,
447		wr_inval, wr_tx0, wr_inval, wr_tx1, wr_ifc, wr_owrctr, wr_inval, wr_topstack
	415	case 0x00: m_astat = val & 0x00ff; break;
	416	case 0x01: m_mstat = val & m_mstat_mask; update_mstat(); break;
	417	case 0x03: m_imask = val & m_imask_mask; check_irqs(); break;
	418	case 0x04: m_icntl = val & 0x001f; check_irqs(); break;
	419	case 0x05: cntr_stack_push(); m_cntr = val & 0x3fff; break;
	420	case 0x06: m_core.sb.s = (INT32)(val << 27) >> 27; break;
	421	case 0x07: m_px = val; break;
	422	case 0x09: if (m_config.m_sport_tx_callback != NULL) (m_config.m_sport_tx_callback)(this, 0, val); break;
	423	case 0x0b: if (m_config.m_sport_tx_callback != NULL) (m_config.m_sport_tx_callback)(this, 1, val); break;
	424	case 0x0c:
	425	m_ifc = val;
	426	if (m_config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2181)
	427	{
	428	/* clear timer */
	429	if (val & 0x0002) m_irq_latch[ADSP2181_IRQ0] = 0;
	430	if (val & 0x0004) m_irq_latch[ADSP2181_IRQ1] = 0;
	431	/* clear BDMA */
	432	if (val & 0x0010) m_irq_latch[ADSP2181_IRQE] = 0;
	433	if (val & 0x0020) m_irq_latch[ADSP2181_SPORT0_RX] = 0;
	434	if (val & 0x0040) m_irq_latch[ADSP2181_SPORT0_TX] = 0;
	435	if (val & 0x0080) m_irq_latch[ADSP2181_IRQ2] = 0;
	436	/* force timer */
	437	if (val & 0x0200) m_irq_latch[ADSP2181_IRQ0] = 1;
	438	if (val & 0x0400) m_irq_latch[ADSP2181_IRQ1] = 1;
	439	/* force BDMA */
	440	if (val & 0x1000) m_irq_latch[ADSP2181_IRQE] = 1;
	441	if (val & 0x2000) m_irq_latch[ADSP2181_SPORT0_RX] = 1;
	442	if (val & 0x4000) m_irq_latch[ADSP2181_SPORT0_TX] = 1;
	443	if (val & 0x8000) m_irq_latch[ADSP2181_IRQ2] = 1;
	444	}
	445	else
	446	{
	447	/* clear timer */
	448	if (val & 0x002) m_irq_latch[ADSP2101_IRQ0] = 0;
	449	if (val & 0x004) m_irq_latch[ADSP2101_IRQ1] = 0;
	450	if (val & 0x008) m_irq_latch[ADSP2101_SPORT0_RX] = 0;
	451	if (val & 0x010) m_irq_latch[ADSP2101_SPORT0_TX] = 0;
	452	if (val & 0x020) m_irq_latch[ADSP2101_IRQ2] = 0;
	453	/* set timer */
	454	if (val & 0x080) m_irq_latch[ADSP2101_IRQ0] = 1;
	455	if (val & 0x100) m_irq_latch[ADSP2101_IRQ1] = 1;
	456	if (val & 0x200) m_irq_latch[ADSP2101_SPORT0_RX] = 1;
	457	if (val & 0x400) m_irq_latch[ADSP2101_SPORT0_TX] = 1;
	458	if (val & 0x800) m_irq_latch[ADSP2101_IRQ2] = 1;
	459	}
	460	check_irqs();
	461	break;
	462	case 0x0d: m_cntr = val & 0x3fff; break;
	463	case 0x0f: pc_stack_push_val(val & 0x3fff); break;
	464	default: logerror("ADSP %04x: Writing to an invalid register!\n", m_ppc); break;
448	465	}
449		};
	466	}
	467
	468	#define WRITE_REG(adsp,grp,reg,val) ((this->*wr_reg[grp][reg])(val))
450	469
451	470
452	471
r9081	r9082
454	473	register reading
455	474	===========================================================================*/
456	475
457		static INT32 rd_inval(adsp2100_state *adsp) { logerror( "ADSP %04x: Writing to an invalid register!\n", adsp->ppc ); return 0; }
458		static INT32 rd_ax0(adsp2100_state *adsp) { return adsp->core.ax0.s; }
459		static INT32 rd_ax1(adsp2100_state *adsp) { return adsp->core.ax1.s; }
460		static INT32 rd_mx0(adsp2100_state *adsp) { return adsp->core.mx0.s; }
461		static INT32 rd_mx1(adsp2100_state *adsp) { return adsp->core.mx1.s; }
462		static INT32 rd_ay0(adsp2100_state *adsp) { return adsp->core.ay0.s; }
463		static INT32 rd_ay1(adsp2100_state *adsp) { return adsp->core.ay1.s; }
464		static INT32 rd_my0(adsp2100_state *adsp) { return adsp->core.my0.s; }
465		static INT32 rd_my1(adsp2100_state *adsp) { return adsp->core.my1.s; }
466		static INT32 rd_si(adsp2100_state *adsp) { return adsp->core.si.s; }
467		static INT32 rd_se(adsp2100_state *adsp) { return adsp->core.se.s; }
468		static INT32 rd_ar(adsp2100_state *adsp) { return adsp->core.ar.s; }
469		static INT32 rd_mr0(adsp2100_state *adsp) { return adsp->core.mr.mrx.mr0.s; }
470		static INT32 rd_mr1(adsp2100_state *adsp) { return adsp->core.mr.mrx.mr1.s; }
471		static INT32 rd_mr2(adsp2100_state *adsp) { return adsp->core.mr.mrx.mr2.s; }
472		static INT32 rd_sr0(adsp2100_state *adsp) { return adsp->core.sr.srx.sr0.s; }
473		static INT32 rd_sr1(adsp2100_state *adsp) { return adsp->core.sr.srx.sr1.s; }
474		static INT32 rd_i0(adsp2100_state *adsp) { return adsp->i[0]; }
475		static INT32 rd_i1(adsp2100_state *adsp) { return adsp->i[1]; }
476		static INT32 rd_i2(adsp2100_state *adsp) { return adsp->i[2]; }
477		static INT32 rd_i3(adsp2100_state *adsp) { return adsp->i[3]; }
478		static INT32 rd_i4(adsp2100_state *adsp) { return adsp->i[4]; }
479		static INT32 rd_i5(adsp2100_state *adsp) { return adsp->i[5]; }
480		static INT32 rd_i6(adsp2100_state *adsp) { return adsp->i[6]; }
481		static INT32 rd_i7(adsp2100_state *adsp) { return adsp->i[7]; }
482		static INT32 rd_m0(adsp2100_state *adsp) { return adsp->m[0]; }
483		static INT32 rd_m1(adsp2100_state *adsp) { return adsp->m[1]; }
484		static INT32 rd_m2(adsp2100_state *adsp) { return adsp->m[2]; }
485		static INT32 rd_m3(adsp2100_state *adsp) { return adsp->m[3]; }
486		static INT32 rd_m4(adsp2100_state *adsp) { return adsp->m[4]; }
487		static INT32 rd_m5(adsp2100_state *adsp) { return adsp->m[5]; }
488		static INT32 rd_m6(adsp2100_state *adsp) { return adsp->m[6]; }
489		static INT32 rd_m7(adsp2100_state *adsp) { return adsp->m[7]; }
490		static INT32 rd_l0(adsp2100_state *adsp) { return adsp->l[0]; }
491		static INT32 rd_l1(adsp2100_state *adsp) { return adsp->l[1]; }
492		static INT32 rd_l2(adsp2100_state *adsp) { return adsp->l[2]; }
493		static INT32 rd_l3(adsp2100_state *adsp) { return adsp->l[3]; }
494		static INT32 rd_l4(adsp2100_state *adsp) { return adsp->l[4]; }
495		static INT32 rd_l5(adsp2100_state *adsp) { return adsp->l[5]; }
496		static INT32 rd_l6(adsp2100_state *adsp) { return adsp->l[6]; }
497		static INT32 rd_l7(adsp2100_state *adsp) { return adsp->l[7]; }
498		static INT32 rd_astat(adsp2100_state *adsp) { return adsp->astat; }
499		static INT32 rd_mstat(adsp2100_state *adsp) { return adsp->mstat; }
500		static INT32 rd_sstat(adsp2100_state *adsp) { return adsp->sstat; }
501		static INT32 rd_imask(adsp2100_state *adsp) { return adsp->imask; }
502		static INT32 rd_icntl(adsp2100_state *adsp) { return adsp->icntl; }
503		static INT32 rd_cntr(adsp2100_state *adsp) { return adsp->cntr; }
504		static INT32 rd_sb(adsp2100_state *adsp) { return adsp->core.sb.s; }
505		static INT32 rd_px(adsp2100_state *adsp) { return adsp->px; }
506		static INT32 rd_rx0(adsp2100_state adsp) { if (adsp->sport_rx_callback) return (adsp->sport_rx_callback)(*adsp->device, 0); else return 0; }
507		static INT32 rd_rx1(adsp2100_state adsp) { if (adsp->sport_rx_callback) return (adsp->sport_rx_callback)(*adsp->device, 1); else return 0; }
508		static INT32 rd_stacktop(adsp2100_state *adsp) { return pc_stack_pop_val(adsp); }
	476	INT32 adsp21xx_device::read_reg0(int regnum)
	477	{
	478	return *m_read0_ptr[regnum];
	479	}
509	480
510		#define READ_REG(adsp,grp,reg) ((*rd_reg[grp][reg])(adsp))
	481	INT32 adsp21xx_device::read_reg1(int regnum)
	482	{
	483	return *m_read1_ptr[regnum];
	484	}
511	485
512		~~static~~ INT32 ~~(const rd_reg[4][16])(~~adsp2100_~~stat~~e ad~~sp)~~ =
	486	INT32 adsp21xx_device::read_reg2(int regnum)
513	487	{
	488	return *m_read2_ptr[regnum];
	489	}
	490
	491	INT32 adsp21xx_device::read_reg3(int regnum)
	492	{
	493	switch (regnum)
514	494	{
515		rd_ax0, rd_ax1, rd_mx0, rd_mx1, rd_ay0, rd_ay1, rd_my0, rd_my1,
516		rd_si, rd_se, rd_ar, rd_mr0, rd_mr1, rd_mr2, rd_sr0, rd_sr1
517		},
518		{
519		rd_i0, rd_i1, rd_i2, rd_i3, rd_m0, rd_m1, rd_m2, rd_m3,
520		rd_l0, rd_l1, rd_l2, rd_l3, rd_inval, rd_inval, rd_inval, rd_inval
521		},
522		{
523		rd_i4, rd_i5, rd_i6, rd_i7, rd_m4, rd_m5, rd_m6, rd_m7,
524		rd_l4, rd_l5, rd_l6, rd_l7, rd_inval, rd_inval, rd_inval, rd_inval
525		},
526		{
527		rd_astat, rd_mstat, rd_sstat, rd_imask, rd_icntl, rd_cntr, rd_sb, rd_px,
528		rd_rx0, rd_inval, rd_rx1, rd_inval, rd_inval, rd_inval, rd_inval, rd_stacktop
	495	case 0x00: return m_astat;
	496	case 0x01: return m_mstat;
	497	case 0x02: return m_sstat;
	498	case 0x03: return m_imask;
	499	case 0x04: return m_icntl;
	500	case 0x05: return m_cntr;
	501	case 0x06: return m_core.sb.s;
	502	case 0x07: return m_px;
	503	case 0x08: if (m_config.m_sport_rx_callback) return (m_config.m_sport_rx_callback)(this, 0); else return 0;
	504	case 0x0a: if (m_config.m_sport_rx_callback) return (m_config.m_sport_rx_callback)(this, 1); else return 0;
	505	case 0x0f: return pc_stack_pop_val();
	506	default: logerror("ADSP %04x: Reading from an invalid register!\n", m_ppc); return 0;
529	507	}
530		};
	508	}
531	509
532	510
533	511
r9081	r9082
535	513	Modulus addressing logic
536	514	===========================================================================*/
537	515
538		~~INLINE~~ void modify_address(~~adsp2100_state *adsp,~~ UINT32 ireg, UINT32 mreg)
	516	inline void adsp21xx_device::modify_address(UINT32 ireg, UINT32 mreg)
539	517	{
540		UINT32 base = adsp->base[ireg];
541		UINT32 i = adsp->i[ireg];
542		UINT32 l = adsp->l[ireg];
	518	UINT32 base = m_base[ireg];
	519	UINT32 i = m_i[ireg];
	520	UINT32 l = m_l[ireg];
543	521
544		i += ~~adsp->~~m[mreg];
	522	i += m_m[mreg];
545	523	if (i < base) i += l;
546	524	else if (i >= base + l) i -= l;
547		~~adsp->~~i[ireg] = i;
	525	m_i[ireg] = i;
548	526	}
549	527
550	528
r9081	r9082
553	531	Data memory accessors
554	532	===========================================================================*/
555	533
556		~~INLINE~~ void data_write_dag1(~~adsp2100_state *adsp,~~ UINT32 op, INT32 val)
	534	inline void adsp21xx_device::data_write_dag1(UINT32 op, INT32 val)
557	535	{
558	536	UINT32 ireg = (op >> 2) & 3;
559	537	UINT32 mreg = op & 3;
560		UINT32 base = adsp->base[ireg];
561		UINT32 i = adsp->i[ireg];
562		UINT32 l = adsp->l[ireg];
	538	UINT32 base = m_base[ireg];
	539	UINT32 i = m_i[ireg];
	540	UINT32 l = m_l[ireg];
563	541
564		if ( ~~adsp->~~mstat & MSTAT_REVERSE )
	542	if ( m_mstat & MSTAT_REVERSE )
565	543	{
566		UINT32 ir = reverse_table[ i & 0x3fff ];
567		WWORD_DATA(adsp, ir, val);
	544	UINT32 ir = m_reverse_table[ i & 0x3fff ];
	545	data_write(ir, val);
568	546	}
569	547	else
570		~~WWORD~~_~~DATA~~(~~adsp,~~ i, val);
	548	data_write(i, val);
571	549
572		i += ~~adsp->~~m[mreg];
	550	i += m_m[mreg];
573	551	if (i < base) i += l;
574	552	else if (i >= base + l) i -= l;
575		~~adsp->~~i[ireg] = i;
	553	m_i[ireg] = i;
576	554	}
577	555
578	556
579		~~INLINE~~ UINT32 data_read_dag1(~~adsp2100_state *adsp,~~ UINT32 op)
	557	inline UINT32 adsp21xx_device::data_read_dag1(UINT32 op)
580	558	{
581	559	UINT32 ireg = (op >> 2) & 3;
582	560	UINT32 mreg = op & 3;
583		UINT32 base = adsp->base[ireg];
584		UINT32 i = adsp->i[ireg];
585		UINT32 l = adsp->l[ireg];
	561	UINT32 base = m_base[ireg];
	562	UINT32 i = m_i[ireg];
	563	UINT32 l = m_l[ireg];
586	564	UINT32 res;
587	565
588		if (~~adsp->~~mstat & MSTAT_REVERSE)
	566	if (m_mstat & MSTAT_REVERSE)
589	567	{
590		UINT32 ir = reverse_table[i & 0x3fff];
591		res = RWORD_DATA(adsp, ir);
	568	UINT32 ir = m_reverse_table[i & 0x3fff];
	569	res = data_read(ir);
592	570	}
593	571	else
594		res = ~~RWORD~~_~~DATA(~~ad~~sp,~~ i);
	572	res = data_read(i);
595	573
596		i += ~~adsp->~~m[mreg];
	574	i += m_m[mreg];
597	575	if (i < base) i += l;
598	576	else if (i >= base + l) i -= l;
599		~~adsp->~~i[ireg] = i;
	577	m_i[ireg] = i;
600	578
601	579	return res;
602	580	}
603	581
604		~~INLINE~~ void data_write_dag2(~~adsp2100_state *adsp,~~ UINT32 op, INT32 val)
	582	inline void adsp21xx_device::data_write_dag2(UINT32 op, INT32 val)
605	583	{
606	584	UINT32 ireg = 4 + ((op >> 2) & 3);
607	585	UINT32 mreg = 4 + (op & 3);
608		UINT32 base = adsp->base[ireg];
609		UINT32 i = adsp->i[ireg];
610		UINT32 l = adsp->l[ireg];
	586	UINT32 base = m_base[ireg];
	587	UINT32 i = m_i[ireg];
	588	UINT32 l = m_l[ireg];
611	589
612		~~WWORD~~_~~DATA~~(~~adsp,~~ i, val);
	590	data_write(i, val);
613	591
614		i += ~~adsp->~~m[mreg];
	592	i += m_m[mreg];
615	593	if (i < base) i += l;
616	594	else if (i >= base + l) i -= l;
617		~~adsp->~~i[ireg] = i;
	595	m_i[ireg] = i;
618	596	}
619	597
620	598
621		~~INLINE~~ UINT32 data_read_dag2(~~adsp2100_state *adsp,~~ UINT32 op)
	599	inline UINT32 adsp21xx_device::data_read_dag2(UINT32 op)
622	600	{
623	601	UINT32 ireg = 4 + ((op >> 2) & 3);
624	602	UINT32 mreg = 4 + (op & 3);
625		UINT32 base = adsp->base[ireg];
626		UINT32 i = adsp->i[ireg];
627		UINT32 l = adsp->l[ireg];
	603	UINT32 base = m_base[ireg];
	604	UINT32 i = m_i[ireg];
	605	UINT32 l = m_l[ireg];
628	606
629		UINT32 res = ~~RWORD~~_~~DATA(~~ad~~sp,~~ i);
	607	UINT32 res = data_read(i);
630	608
631		i += ~~adsp->~~m[mreg];
	609	i += m_m[mreg];
632	610	if (i < base) i += l;
633	611	else if (i >= base + l) i -= l;
634		~~adsp->~~i[ireg] = i;
	612	m_i[ireg] = i;
635	613
636	614	return res;
637	615	}
r9081	r9082
640	618	Program memory accessors
641	619	===========================================================================*/
642	620
643		~~INLINE~~ void pgm_write_dag2(~~adsp2100_state *adsp,~~ UINT32 op, INT32 val)
	621	inline void adsp21xx_device::pgm_write_dag2(UINT32 op, INT32 val)
644	622	{
645	623	UINT32 ireg = 4 + ((op >> 2) & 3);
646	624	UINT32 mreg = 4 + (op & 3);
647		UINT32 base = adsp->base[ireg];
648		UINT32 i = adsp->i[ireg];
649		UINT32 l = adsp->l[ireg];
	625	UINT32 base = m_base[ireg];
	626	UINT32 i = m_i[ireg];
	627	UINT32 l = m_l[ireg];
650	628
651		~~WWORD~~_~~PGM~~(~~adsp,~~ i, (val << 8) \| ~~adsp->~~px);
	629	program_write(i, (val << 8) \| m_px);
652	630
653		i += ~~adsp->~~m[mreg];
	631	i += m_m[mreg];
654	632	if (i < base) i += l;
655	633	else if (i >= base + l) i -= l;
656		~~adsp->~~i[ireg] = i;
	634	m_i[ireg] = i;
657	635	}
658	636
659	637
660		~~INLINE~~ UINT32 pgm_read_dag2(~~adsp2100_state *adsp,~~ UINT32 op)
	638	inline UINT32 adsp21xx_device::pgm_read_dag2(UINT32 op)
661	639	{
662	640	UINT32 ireg = 4 + ((op >> 2) & 3);
663	641	UINT32 mreg = 4 + (op & 3);
664		UINT32 base = adsp->base[ireg];
665		UINT32 i = adsp->i[ireg];
666		UINT32 l = adsp->l[ireg];
	642	UINT32 base = m_base[ireg];
	643	UINT32 i = m_i[ireg];
	644	UINT32 l = m_l[ireg];
667	645	UINT32 res;
668	646
669		res = RWORD_PGM(adsp, i);
670		adsp->px = res;
	647	res = program_read(i);
	648	m_px = res;
671	649	res >>= 8;
672	650
673		i += ~~adsp->~~m[mreg];
	651	i += m_m[mreg];
674	652	if (i < base) i += l;
675	653	else if (i >= base + l) i -= l;
676		~~adsp->~~i[ireg] = i;
	654	m_i[ireg] = i;
677	655
678	656	return res;
679	657	}
r9081	r9082
684	662	register reading
685	663	===========================================================================*/
686	664
687		#define ALU_GETXREG_UNSIGNED(a,x) ((UINT16 )(a)->alu_xregs[x])
688		#define ALU_GETYREG_UNSIGNED(a,y) ((UINT16 )(a)->alu_yregs[y])
	665	#define ALU_GETXREG_UNSIGNED(x) ((UINT16 )m_alu_xregs[x])
	666	#define ALU_GETYREG_UNSIGNED(y) ((UINT16 )m_alu_yregs[y])
689	667
690		#define MAC_GETXREG_UNSIGNED(a,x) ((UINT16 )(a)->mac_xregs[x])
691		#define MAC_GETXREG_SIGNED(a,x) (( INT16 )(a)->mac_xregs[x])
692		#define MAC_GETYREG_UNSIGNED(a,y) ((UINT16 )(a)->mac_yregs[y])
693		#define MAC_GETYREG_SIGNED(a,y) (( INT16 )(a)->mac_yregs[y])
	668	#define MAC_GETXREG_UNSIGNED(x) ((UINT16 )m_mac_xregs[x])
	669	#define MAC_GETXREG_SIGNED(x) (( INT16 )m_mac_xregs[x])
	670	#define MAC_GETYREG_UNSIGNED(y) ((UINT16 )m_mac_yregs[y])
	671	#define MAC_GETYREG_SIGNED(y) (( INT16 )m_mac_yregs[y])
694	672
695		#define SHIFT_GETXREG_UNSIGNED(a,x) ((UINT16 )(a)->shift_xregs[x])
696		#define SHIFT_GETXREG_SIGNED(a,x) (( INT16 )(a)->shift_xregs[x])
	673	#define SHIFT_GETXREG_UNSIGNED(x) ((UINT16 )m_shift_xregs[x])
	674	#define SHIFT_GETXREG_SIGNED(x) (( INT16 )m_shift_xregs[x])
697	675
698	676
699	677
r9081	r9082
701	679	ALU operations (result in AR)
702	680	===========================================================================*/
703	681
704		~~static~~ void a~~lu_op_ar(a~~dsp2100_~~stat~~e *adsp, int op)
	682	void adsp21xx_device::alu_op_ar(int op)
705	683	{
706	684	INT32 xop = (op >> 8) & 7;
707	685	INT32 yop = (op >> 11) & 3;
r9081	r9082
711	689	{
712	690	case 0x00<<13:
713	691	/* Y Clear when y = 0 */
714		res = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	692	res = ALU_GETYREG_UNSIGNED(yop);
715	693	CALC_NZ(res);
716	694	break;
717	695	case 0x01<<13:
718	696	/* Y + 1 PASS 1 when y = 0 */
719		yop = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	697	yop = ALU_GETYREG_UNSIGNED(yop);
720	698	res = yop + 1;
721	699	CALC_NZ(res);
722	700	if (yop == 0x7fff) SET_V;
r9081	r9082
724	702	break;
725	703	case 0x02<<13:
726	704	/* X + Y + C */
727		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
728		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	705	xop = ALU_GETXREG_UNSIGNED(xop);
	706	yop = ALU_GETYREG_UNSIGNED(yop);
729	707	yop += GET_C >> 3;
730	708	res = xop + yop;
731	709	CALC_NZVC(xop, yop, res);
732	710	break;
733	711	case 0x03<<13:
734	712	/* X + Y X when y = 0 */
735		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
736		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	713	xop = ALU_GETXREG_UNSIGNED(xop);
	714	yop = ALU_GETYREG_UNSIGNED(yop);
737	715	res = xop + yop;
738	716	CALC_NZVC(xop, yop, res);
739	717	break;
740	718	case 0x04<<13:
741	719	/* NOT Y */
742		res = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop) ^ 0xffff;
	720	res = ALU_GETYREG_UNSIGNED(yop) ^ 0xffff;
743	721	CALC_NZ(res);
744	722	break;
745	723	case 0x05<<13:
746	724	/* -Y */
747		yop = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	725	yop = ALU_GETYREG_UNSIGNED(yop);
748	726	res = -yop;
749	727	CALC_NZ(res);
750	728	if (yop == 0x8000) SET_V;
r9081	r9082
752	730	break;
753	731	case 0x06<<13:
754	732	/* X - Y + C - 1 X + C - 1 when y = 0 */
755		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
756		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	733	xop = ALU_GETXREG_UNSIGNED(xop);
	734	yop = ALU_GETYREG_UNSIGNED(yop);
757	735	res = xop - yop + (GET_C >> 3) - 1;
758	736	CALC_NZVC_SUB(xop, yop, res);
759	737	break;
760	738	case 0x07<<13:
761	739	/* X - Y */
762		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
763		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	740	xop = ALU_GETXREG_UNSIGNED(xop);
	741	yop = ALU_GETYREG_UNSIGNED(yop);
764	742	res = xop - yop;
765	743	CALC_NZVC_SUB(xop, yop, res);
766	744	break;
767	745	case 0x08<<13:
768	746	/* Y - 1 PASS -1 when y = 0 */
769		yop = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	747	yop = ALU_GETYREG_UNSIGNED(yop);
770	748	res = yop - 1;
771	749	CALC_NZ(res);
772	750	if (yop == 0x8000) SET_V;
r9081	r9082
774	752	break;
775	753	case 0x09<<13:
776	754	/* Y - X -X when y = 0 */
777		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
778		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	755	xop = ALU_GETXREG_UNSIGNED(xop);
	756	yop = ALU_GETYREG_UNSIGNED(yop);
779	757	res = yop - xop;
780	758	CALC_NZVC_SUB(yop, xop, res);
781	759	break;
782	760	case 0x0a<<13:
783	761	/* Y - X + C - 1 -X + C - 1 when y = 0 */
784		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
785		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	762	xop = ALU_GETXREG_UNSIGNED(xop);
	763	yop = ALU_GETYREG_UNSIGNED(yop);
786	764	res = yop - xop + (GET_C >> 3) - 1;
787	765	CALC_NZVC_SUB(yop, xop, res);
788	766	break;
789	767	case 0x0b<<13:
790	768	/* NOT X */
791		res = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop) ^ 0xffff;
	769	res = ALU_GETXREG_UNSIGNED(xop) ^ 0xffff;
792	770	CALC_NZ(res);
793	771	break;
794	772	case 0x0c<<13:
795	773	/* X AND Y */
796		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
797		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	774	xop = ALU_GETXREG_UNSIGNED(xop);
	775	yop = ALU_GETYREG_UNSIGNED(yop);
798	776	res = xop & yop;
799	777	CALC_NZ(res);
800	778	break;
801	779	case 0x0d<<13:
802	780	/* X OR Y */
803		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
804		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	781	xop = ALU_GETXREG_UNSIGNED(xop);
	782	yop = ALU_GETYREG_UNSIGNED(yop);
805	783	res = xop \| yop;
806	784	CALC_NZ(res);
807	785	break;
808	786	case 0x0e<<13:
809	787	/* X XOR Y */
810		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
811		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	788	xop = ALU_GETXREG_UNSIGNED(xop);
	789	yop = ALU_GETYREG_UNSIGNED(yop);
812	790	res = xop ^ yop;
813	791	CALC_NZ(res);
814	792	break;
815	793	case 0x0f<<13:
816	794	/* ABS X */
817		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	795	xop = ALU_GETXREG_UNSIGNED(xop);
818	796	res = (xop & 0x8000) ? -xop : xop;
819	797	if (xop == 0) SET_Z;
820	798	if (xop == 0x8000) SET_N, SET_V;
r9081	r9082
827	805	}
828	806
829	807	/* saturate */
830		if ((~~adsp->~~mstat & MSTAT_SATURATE) && GET_V) res = GET_C ? -32768 : 32767;
	808	if ((m_mstat & MSTAT_SATURATE) && GET_V) res = GET_C ? -32768 : 32767;
831	809
832	810	/* set the final value */
833		~~adsp->~~core.ar.u = res;
	811	m_core.ar.u = res;
834	812	}
835	813
836	814
r9081	r9082
839	817	ALU operations (result in AR, constant yop)
840	818	===========================================================================*/
841	819
842		~~static~~ void alu_op_ar_const(~~adsp2100_state *adsp,~~ int op)
	820	void adsp21xx_device::alu_op_ar_const(int op)
843	821	{
844	822	INT32 xop = (op >> 8) & 7;
845	823	INT32 yop = constants[((op >> 5) & 0x07) \| ((op >> 8) & 0x18)];
r9081	r9082
861	839	break;
862	840	case 0x02<<13:
863	841	/* X + Y + C */
864		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	842	xop = ALU_GETXREG_UNSIGNED(xop);
865	843	yop += GET_C >> 3;
866	844	res = xop + yop;
867	845	CALC_NZVC(xop, yop, res);
868	846	break;
869	847	case 0x03<<13:
870	848	/* X + Y X when y = 0 */
871		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	849	xop = ALU_GETXREG_UNSIGNED(xop);
872	850	res = xop + yop;
873	851	CALC_NZVC(xop, yop, res);
874	852	break;
r9081	r9082
886	864	break;
887	865	case 0x06<<13:
888	866	/* X - Y + C - 1 X + C - 1 when y = 0 */
889		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	867	xop = ALU_GETXREG_UNSIGNED(xop);
890	868	res = xop - yop + (GET_C >> 3) - 1;
891	869	CALC_NZVC_SUB(xop, yop, res);
892	870	break;
893	871	case 0x07<<13:
894	872	/* X - Y */
895		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	873	xop = ALU_GETXREG_UNSIGNED(xop);
896	874	res = xop - yop;
897	875	CALC_NZVC_SUB(xop, yop, res);
898	876	break;
r9081	r9082
905	883	break;
906	884	case 0x09<<13:
907	885	/* Y - X -X when y = 0 */
908		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	886	xop = ALU_GETXREG_UNSIGNED(xop);
909	887	res = yop - xop;
910	888	CALC_NZVC_SUB(yop, xop, res);
911	889	break;
912	890	case 0x0a<<13:
913	891	/* Y - X + C - 1 -X + C - 1 when y = 0 */
914		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	892	xop = ALU_GETXREG_UNSIGNED(xop);
915	893	res = yop - xop + (GET_C >> 3) - 1;
916	894	CALC_NZVC_SUB(yop, xop, res);
917	895	break;
918	896	case 0x0b<<13:
919	897	/* NOT X */
920		res = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop) ^ 0xffff;
	898	res = ALU_GETXREG_UNSIGNED(xop) ^ 0xffff;
921	899	CALC_NZ(res);
922	900	break;
923	901	case 0x0c<<13:
924	902	/* X AND Y */
925		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	903	xop = ALU_GETXREG_UNSIGNED(xop);
926	904	res = xop & yop;
927	905	CALC_NZ(res);
928	906	break;
929	907	case 0x0d<<13:
930	908	/* X OR Y */
931		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	909	xop = ALU_GETXREG_UNSIGNED(xop);
932	910	res = xop \| yop;
933	911	CALC_NZ(res);
934	912	break;
935	913	case 0x0e<<13:
936	914	/* X XOR Y */
937		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	915	xop = ALU_GETXREG_UNSIGNED(xop);
938	916	res = xop ^ yop;
939	917	CALC_NZ(res);
940	918	break;
941	919	case 0x0f<<13:
942	920	/* ABS X */
943		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	921	xop = ALU_GETXREG_UNSIGNED(xop);
944	922	res = (xop & 0x8000) ? -xop : xop;
945	923	if (xop == 0) SET_Z;
946	924	if (xop == 0x8000) SET_N, SET_V;
r9081	r9082
953	931	}
954	932
955	933	/* saturate */
956		if ((~~adsp->~~mstat & MSTAT_SATURATE) && GET_V) res = GET_C ? -32768 : 32767;
	934	if ((m_mstat & MSTAT_SATURATE) && GET_V) res = GET_C ? -32768 : 32767;
957	935
958	936	/* set the final value */
959		~~adsp->~~core.ar.u = res;
	937	m_core.ar.u = res;
960	938	}
961	939
962	940
r9081	r9082
965	943	ALU operations (result in AF)
966	944	===========================================================================*/
967	945
968		~~static~~ void a~~lu_op_af(a~~dsp2100_~~stat~~e *adsp, int op)
	946	void adsp21xx_device::alu_op_af(int op)
969	947	{
970	948	INT32 xop = (op >> 8) & 7;
971	949	INT32 yop = (op >> 11) & 3;
r9081	r9082
975	953	{
976	954	case 0x00<<13:
977	955	/* Y Clear when y = 0 */
978		res = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	956	res = ALU_GETYREG_UNSIGNED(yop);
979	957	CALC_NZ(res);
980	958	break;
981	959	case 0x01<<13:
982	960	/* Y + 1 PASS 1 when y = 0 */
983		yop = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	961	yop = ALU_GETYREG_UNSIGNED(yop);
984	962	res = yop + 1;
985	963	CALC_NZ(res);
986	964	if (yop == 0x7fff) SET_V;
r9081	r9082
988	966	break;
989	967	case 0x02<<13:
990	968	/* X + Y + C */
991		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
992		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	969	xop = ALU_GETXREG_UNSIGNED(xop);
	970	yop = ALU_GETYREG_UNSIGNED(yop);
993	971	yop += GET_C >> 3;
994	972	res = xop + yop;
995	973	CALC_NZVC(xop, yop, res);
996	974	break;
997	975	case 0x03<<13:
998	976	/* X + Y X when y = 0 */
999		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1000		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	977	xop = ALU_GETXREG_UNSIGNED(xop);
	978	yop = ALU_GETYREG_UNSIGNED(yop);
1001	979	res = xop + yop;
1002	980	CALC_NZVC(xop, yop, res);
1003	981	break;
1004	982	case 0x04<<13:
1005	983	/* NOT Y */
1006		res = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop) ^ 0xffff;
	984	res = ALU_GETYREG_UNSIGNED(yop) ^ 0xffff;
1007	985	CALC_NZ(res);
1008	986	break;
1009	987	case 0x05<<13:
1010	988	/* -Y */
1011		yop = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	989	yop = ALU_GETYREG_UNSIGNED(yop);
1012	990	res = -yop;
1013	991	CALC_NZ(res);
1014	992	if (yop == 0x8000) SET_V;
r9081	r9082
1016	994	break;
1017	995	case 0x06<<13:
1018	996	/* X - Y + C - 1 X + C - 1 when y = 0 */
1019		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1020		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	997	xop = ALU_GETXREG_UNSIGNED(xop);
	998	yop = ALU_GETYREG_UNSIGNED(yop);
1021	999	res = xop - yop + (GET_C >> 3) - 1;
1022	1000	CALC_NZVC_SUB(xop, yop, res);
1023	1001	break;
1024	1002	case 0x07<<13:
1025	1003	/* X - Y */
1026		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1027		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1004	xop = ALU_GETXREG_UNSIGNED(xop);
	1005	yop = ALU_GETYREG_UNSIGNED(yop);
1028	1006	res = xop - yop;
1029	1007	CALC_NZVC_SUB(xop, yop, res);
1030	1008	break;
1031	1009	case 0x08<<13:
1032	1010	/* Y - 1 PASS -1 when y = 0 */
1033		yop = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	1011	yop = ALU_GETYREG_UNSIGNED(yop);
1034	1012	res = yop - 1;
1035	1013	CALC_NZ(res);
1036	1014	if (yop == 0x8000) SET_V;
r9081	r9082
1038	1016	break;
1039	1017	case 0x09<<13:
1040	1018	/* Y - X -X when y = 0 */
1041		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1042		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1019	xop = ALU_GETXREG_UNSIGNED(xop);
	1020	yop = ALU_GETYREG_UNSIGNED(yop);
1043	1021	res = yop - xop;
1044	1022	CALC_NZVC_SUB(yop, xop, res);
1045	1023	break;
1046	1024	case 0x0a<<13:
1047	1025	/* Y - X + C - 1 -X + C - 1 when y = 0 */
1048		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1049		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1026	xop = ALU_GETXREG_UNSIGNED(xop);
	1027	yop = ALU_GETYREG_UNSIGNED(yop);
1050	1028	res = yop - xop + (GET_C >> 3) - 1;
1051	1029	CALC_NZVC_SUB(yop, xop, res);
1052	1030	break;
1053	1031	case 0x0b<<13:
1054	1032	/* NOT X */
1055		res = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop) ^ 0xffff;
	1033	res = ALU_GETXREG_UNSIGNED(xop) ^ 0xffff;
1056	1034	CALC_NZ(res);
1057	1035	break;
1058	1036	case 0x0c<<13:
1059	1037	/* X AND Y */
1060		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1061		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1038	xop = ALU_GETXREG_UNSIGNED(xop);
	1039	yop = ALU_GETYREG_UNSIGNED(yop);
1062	1040	res = xop & yop;
1063	1041	CALC_NZ(res);
1064	1042	break;
1065	1043	case 0x0d<<13:
1066	1044	/* X OR Y */
1067		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1068		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1045	xop = ALU_GETXREG_UNSIGNED(xop);
	1046	yop = ALU_GETYREG_UNSIGNED(yop);
1069	1047	res = xop \| yop;
1070	1048	CALC_NZ(res);
1071	1049	break;
1072	1050	case 0x0e<<13:
1073	1051	/* X XOR Y */
1074		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1075		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1052	xop = ALU_GETXREG_UNSIGNED(xop);
	1053	yop = ALU_GETYREG_UNSIGNED(yop);
1076	1054	res = xop ^ yop;
1077	1055	CALC_NZ(res);
1078	1056	break;
1079	1057	case 0x0f<<13:
1080	1058	/* ABS X */
1081		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1059	xop = ALU_GETXREG_UNSIGNED(xop);
1082	1060	res = (xop & 0x8000) ? -xop : xop;
1083	1061	if (xop == 0) SET_Z;
1084	1062	if (xop == 0x8000) SET_N, SET_V;
r9081	r9082
1091	1069	}
1092	1070
1093	1071	/* set the final value */
1094		~~adsp->~~core.af.u = res;
	1072	m_core.af.u = res;
1095	1073	}
1096	1074
1097	1075
r9081	r9082
1100	1078	ALU operations (result in AF, constant yop)
1101	1079	===========================================================================*/
1102	1080
1103		~~static~~ void alu_op_af_const(~~adsp2100_state *adsp,~~ int op)
	1081	void adsp21xx_device::alu_op_af_const(int op)
1104	1082	{
1105	1083	INT32 xop = (op >> 8) & 7;
1106	1084	INT32 yop = constants[((op >> 5) & 0x07) \| ((op >> 8) & 0x18)];
r9081	r9082
1122	1100	break;
1123	1101	case 0x02<<13:
1124	1102	/* X + Y + C */
1125		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1103	xop = ALU_GETXREG_UNSIGNED(xop);
1126	1104	yop += GET_C >> 3;
1127	1105	res = xop + yop;
1128	1106	CALC_NZVC(xop, yop, res);
1129	1107	break;
1130	1108	case 0x03<<13:
1131	1109	/* X + Y X when y = 0 */
1132		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1110	xop = ALU_GETXREG_UNSIGNED(xop);
1133	1111	res = xop + yop;
1134	1112	CALC_NZVC(xop, yop, res);
1135	1113	break;
r9081	r9082
1147	1125	break;
1148	1126	case 0x06<<13:
1149	1127	/* X - Y + C - 1 X + C - 1 when y = 0 */
1150		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1128	xop = ALU_GETXREG_UNSIGNED(xop);
1151	1129	res = xop - yop + (GET_C >> 3) - 1;
1152	1130	CALC_NZVC_SUB(xop, yop, res);
1153	1131	break;
1154	1132	case 0x07<<13:
1155	1133	/* X - Y */
1156		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1134	xop = ALU_GETXREG_UNSIGNED(xop);
1157	1135	res = xop - yop;
1158	1136	CALC_NZVC_SUB(xop, yop, res);
1159	1137	break;
r9081	r9082
1166	1144	break;
1167	1145	case 0x09<<13:
1168	1146	/* Y - X -X when y = 0 */
1169		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1147	xop = ALU_GETXREG_UNSIGNED(xop);
1170	1148	res = yop - xop;
1171	1149	CALC_NZVC_SUB(yop, xop, res);
1172	1150	break;
1173	1151	case 0x0a<<13:
1174	1152	/* Y - X + C - 1 -X + C - 1 when y = 0 */
1175		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1153	xop = ALU_GETXREG_UNSIGNED(xop);
1176	1154	res = yop - xop + (GET_C >> 3) - 1;
1177	1155	CALC_NZVC_SUB(yop, xop, res);
1178	1156	break;
1179	1157	case 0x0b<<13:
1180	1158	/* NOT X */
1181		res = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop) ^ 0xffff;
	1159	res = ALU_GETXREG_UNSIGNED(xop) ^ 0xffff;
1182	1160	CALC_NZ(res);
1183	1161	break;
1184	1162	case 0x0c<<13:
1185	1163	/* X AND Y */
1186		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1164	xop = ALU_GETXREG_UNSIGNED(xop);
1187	1165	res = xop & yop;
1188	1166	CALC_NZ(res);
1189	1167	break;
1190	1168	case 0x0d<<13:
1191	1169	/* X OR Y */
1192		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1170	xop = ALU_GETXREG_UNSIGNED(xop);
1193	1171	res = xop \| yop;
1194	1172	CALC_NZ(res);
1195	1173	break;
1196	1174	case 0x0e<<13:
1197	1175	/* X XOR Y */
1198		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1176	xop = ALU_GETXREG_UNSIGNED(xop);
1199	1177	res = xop ^ yop;
1200	1178	CALC_NZ(res);
1201	1179	break;
1202	1180	case 0x0f<<13:
1203	1181	/* ABS X */
1204		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1182	xop = ALU_GETXREG_UNSIGNED(xop);
1205	1183	res = (xop & 0x8000) ? -xop : xop;
1206	1184	if (xop == 0) SET_Z;
1207	1185	if (xop == 0x8000) SET_N, SET_V;
r9081	r9082
1214	1192	}
1215	1193
1216	1194	/* set the final value */
1217		~~adsp->~~core.af.u = res;
	1195	m_core.af.u = res;
1218	1196	}
1219	1197
1220	1198
r9081	r9082
1223	1201	ALU operations (no result)
1224	1202	===========================================================================*/
1225	1203
1226		~~static~~ void alu_op_none(~~adsp2100_state *adsp,~~ int op)
	1204	void adsp21xx_device::alu_op_none(int op)
1227	1205	{
1228	1206	INT32 xop = (op >> 8) & 7;
1229	1207	INT32 yop = (op >> 11) & 3;
r9081	r9082
1233	1211	{
1234	1212	case 0x00<<13:
1235	1213	/* Y Clear when y = 0 */
1236		res = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	1214	res = ALU_GETYREG_UNSIGNED(yop);
1237	1215	CALC_NZ(res);
1238	1216	break;
1239	1217	case 0x01<<13:
1240	1218	/* Y + 1 PASS 1 when y = 0 */
1241		yop = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	1219	yop = ALU_GETYREG_UNSIGNED(yop);
1242	1220	res = yop + 1;
1243	1221	CALC_NZ(res);
1244	1222	if (yop == 0x7fff) SET_V;
r9081	r9082
1246	1224	break;
1247	1225	case 0x02<<13:
1248	1226	/* X + Y + C */
1249		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1250		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1227	xop = ALU_GETXREG_UNSIGNED(xop);
	1228	yop = ALU_GETYREG_UNSIGNED(yop);
1251	1229	yop += GET_C >> 3;
1252	1230	res = xop + yop;
1253	1231	CALC_NZVC(xop, yop, res);
1254	1232	break;
1255	1233	case 0x03<<13:
1256	1234	/* X + Y X when y = 0 */
1257		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1258		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1235	xop = ALU_GETXREG_UNSIGNED(xop);
	1236	yop = ALU_GETYREG_UNSIGNED(yop);
1259	1237	res = xop + yop;
1260	1238	CALC_NZVC(xop, yop, res);
1261	1239	break;
1262	1240	case 0x04<<13:
1263	1241	/* NOT Y */
1264		res = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop) ^ 0xffff;
	1242	res = ALU_GETYREG_UNSIGNED(yop) ^ 0xffff;
1265	1243	CALC_NZ(res);
1266	1244	break;
1267	1245	case 0x05<<13:
1268	1246	/* -Y */
1269		yop = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	1247	yop = ALU_GETYREG_UNSIGNED(yop);
1270	1248	res = -yop;
1271	1249	CALC_NZ(res);
1272	1250	if (yop == 0x8000) SET_V;
r9081	r9082
1274	1252	break;
1275	1253	case 0x06<<13:
1276	1254	/* X - Y + C - 1 X + C - 1 when y = 0 */
1277		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1278		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1255	xop = ALU_GETXREG_UNSIGNED(xop);
	1256	yop = ALU_GETYREG_UNSIGNED(yop);
1279	1257	res = xop - yop + (GET_C >> 3) - 1;
1280	1258	CALC_NZVC_SUB(xop, yop, res);
1281	1259	break;
1282	1260	case 0x07<<13:
1283	1261	/* X - Y */
1284		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1285		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1262	xop = ALU_GETXREG_UNSIGNED(xop);
	1263	yop = ALU_GETYREG_UNSIGNED(yop);
1286	1264	res = xop - yop;
1287	1265	CALC_NZVC_SUB(xop, yop, res);
1288	1266	break;
1289	1267	case 0x08<<13:
1290	1268	/* Y - 1 PASS -1 when y = 0 */
1291		yop = ALU_GETYREG_UNSIGNED(~~adsp,~~ yop);
	1269	yop = ALU_GETYREG_UNSIGNED(yop);
1292	1270	res = yop - 1;
1293	1271	CALC_NZ(res);
1294	1272	if (yop == 0x8000) SET_V;
r9081	r9082
1296	1274	break;
1297	1275	case 0x09<<13:
1298	1276	/* Y - X -X when y = 0 */
1299		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1300		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1277	xop = ALU_GETXREG_UNSIGNED(xop);
	1278	yop = ALU_GETYREG_UNSIGNED(yop);
1301	1279	res = yop - xop;
1302	1280	CALC_NZVC_SUB(yop, xop, res);
1303	1281	break;
1304	1282	case 0x0a<<13:
1305	1283	/* Y - X + C - 1 -X + C - 1 when y = 0 */
1306		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1307		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1284	xop = ALU_GETXREG_UNSIGNED(xop);
	1285	yop = ALU_GETYREG_UNSIGNED(yop);
1308	1286	res = yop - xop + (GET_C >> 3) - 1;
1309	1287	CALC_NZVC_SUB(yop, xop, res);
1310	1288	break;
1311	1289	case 0x0b<<13:
1312	1290	/* NOT X */
1313		res = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop) ^ 0xffff;
	1291	res = ALU_GETXREG_UNSIGNED(xop) ^ 0xffff;
1314	1292	CALC_NZ(res);
1315	1293	break;
1316	1294	case 0x0c<<13:
1317	1295	/* X AND Y */
1318		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1319		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1296	xop = ALU_GETXREG_UNSIGNED(xop);
	1297	yop = ALU_GETYREG_UNSIGNED(yop);
1320	1298	res = xop & yop;
1321	1299	CALC_NZ(res);
1322	1300	break;
1323	1301	case 0x0d<<13:
1324	1302	/* X OR Y */
1325		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1326		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1303	xop = ALU_GETXREG_UNSIGNED(xop);
	1304	yop = ALU_GETYREG_UNSIGNED(yop);
1327	1305	res = xop \| yop;
1328	1306	CALC_NZ(res);
1329	1307	break;
1330	1308	case 0x0e<<13:
1331	1309	/* X XOR Y */
1332		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1333		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1310	xop = ALU_GETXREG_UNSIGNED(xop);
	1311	yop = ALU_GETYREG_UNSIGNED(yop);
1334	1312	res = xop ^ yop;
1335	1313	CALC_NZ(res);
1336	1314	break;
1337	1315	case 0x0f<<13:
1338	1316	/* ABS X */
1339		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1317	xop = ALU_GETXREG_UNSIGNED(xop);
1340	1318	res = (xop & 0x8000) ? -xop : xop;
1341	1319	if (xop == 0) SET_Z;
1342	1320	if (xop == 0x8000) SET_N, SET_V;
r9081	r9082
1352	1330	MAC operations (result in MR)
1353	1331	===========================================================================*/
1354	1332
1355		~~static~~ void ma~~c_op_mr(a~~dsp2100_~~stat~~e *adsp, int op)
	1333	void adsp21xx_device::mac_op_mr(int op)
1356	1334	{
1357		INT8 shift = ((~~adsp->~~mstat & MSTAT_INTEGER) >> 4) ^ 1;
	1335	INT8 shift = ((m_mstat & MSTAT_INTEGER) >> 4) ^ 1;
1358	1336	INT32 xop = (op >> 8) & 7;
1359	1337	INT32 yop = (op >> 11) & 3;
1360	1338	INT32 temp;
r9081	r9082
1367	1345	return;
1368	1346	case 0x01<<13:
1369	1347	/* X * Y (RND) */
1370		xop = MAC_GETXREG_SIGNED(adsp, xop);
1371		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1348	xop = MAC_GETXREG_SIGNED(xop);
	1349	yop = MAC_GETYREG_SIGNED(yop);
1372	1350	temp = (xop * yop) << shift;
1373	1351	res = (INT64)temp;
1374	1352	#if 0
r9081	r9082
1383	1361	break;
1384	1362	case 0x02<<13:
1385	1363	/* MR + X * Y (RND) */
1386		xop = MAC_GETXREG_SIGNED(adsp, xop);
1387		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1364	xop = MAC_GETXREG_SIGNED(xop);
	1365	yop = MAC_GETYREG_SIGNED(yop);
1388	1366	temp = (xop * yop) << shift;
1389		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1367	res = m_core.mr.mr + (INT64)temp;
1390	1368	#if 0
1391	1369	if ((res & 0xffff) == 0x8000) res &= ~((UINT64)0x10000);
1392	1370	else res += (res & 0x8000) << 1;
r9081	r9082
1399	1377	break;
1400	1378	case 0x03<<13:
1401	1379	/* MR - X * Y (RND) */
1402		xop = MAC_GETXREG_SIGNED(adsp, xop);
1403		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1380	xop = MAC_GETXREG_SIGNED(xop);
	1381	yop = MAC_GETYREG_SIGNED(yop);
1404	1382	temp = (xop * yop) << shift;
1405		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1383	res = m_core.mr.mr - (INT64)temp;
1406	1384	#if 0
1407	1385	if ((res & 0xffff) == 0x8000) res &= ~((UINT64)0x10000);
1408	1386	else res += (res & 0x8000) << 1;
r9081	r9082
1415	1393	break;
1416	1394	case 0x04<<13:
1417	1395	/* X * Y (SS) Clear when y = 0 */
1418		xop = MAC_GETXREG_SIGNED(adsp, xop);
1419		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1396	xop = MAC_GETXREG_SIGNED(xop);
	1397	yop = MAC_GETYREG_SIGNED(yop);
1420	1398	temp = (xop * yop) << shift;
1421	1399	res = (INT64)temp;
1422	1400	break;
1423	1401	case 0x05<<13:
1424	1402	/* X * Y (SU) */
1425		xop = MAC_GETXREG_SIGNED(adsp, xop);
1426		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1403	xop = MAC_GETXREG_SIGNED(xop);
	1404	yop = MAC_GETYREG_UNSIGNED(yop);
1427	1405	temp = (xop * yop) << shift;
1428	1406	res = (INT64)temp;
1429	1407	break;
1430	1408	case 0x06<<13:
1431	1409	/* X * Y (US) */
1432		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1433		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1410	xop = MAC_GETXREG_UNSIGNED(xop);
	1411	yop = MAC_GETYREG_SIGNED(yop);
1434	1412	temp = (xop * yop) << shift;
1435	1413	res = (INT64)temp;
1436	1414	break;
1437	1415	case 0x07<<13:
1438	1416	/* X * Y (UU) */
1439		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1440		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1417	xop = MAC_GETXREG_UNSIGNED(xop);
	1418	yop = MAC_GETYREG_UNSIGNED(yop);
1441	1419	temp = (xop * yop) << shift;
1442	1420	res = (INT64)temp;
1443	1421	break;
1444	1422	case 0x08<<13:
1445	1423	/* MR + X * Y (SS) */
1446		xop = MAC_GETXREG_SIGNED(adsp, xop);
1447		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1424	xop = MAC_GETXREG_SIGNED(xop);
	1425	yop = MAC_GETYREG_SIGNED(yop);
1448	1426	temp = (xop * yop) << shift;
1449		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1427	res = m_core.mr.mr + (INT64)temp;
1450	1428	break;
1451	1429	case 0x09<<13:
1452	1430	/* MR + X * Y (SU) */
1453		xop = MAC_GETXREG_SIGNED(adsp, xop);
1454		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1431	xop = MAC_GETXREG_SIGNED(xop);
	1432	yop = MAC_GETYREG_UNSIGNED(yop);
1455	1433	temp = (xop * yop) << shift;
1456		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1434	res = m_core.mr.mr + (INT64)temp;
1457	1435	break;
1458	1436	case 0x0a<<13:
1459	1437	/* MR + X * Y (US) */
1460		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1461		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1438	xop = MAC_GETXREG_UNSIGNED(xop);
	1439	yop = MAC_GETYREG_SIGNED(yop);
1462	1440	temp = (xop * yop) << shift;
1463		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1441	res = m_core.mr.mr + (INT64)temp;
1464	1442	break;
1465	1443	case 0x0b<<13:
1466	1444	/* MR + X * Y (UU) */
1467		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1468		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1445	xop = MAC_GETXREG_UNSIGNED(xop);
	1446	yop = MAC_GETYREG_UNSIGNED(yop);
1469	1447	temp = (xop * yop) << shift;
1470		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1448	res = m_core.mr.mr + (INT64)temp;
1471	1449	break;
1472	1450	case 0x0c<<13:
1473	1451	/* MR - X * Y (SS) */
1474		xop = MAC_GETXREG_SIGNED(adsp, xop);
1475		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1452	xop = MAC_GETXREG_SIGNED(xop);
	1453	yop = MAC_GETYREG_SIGNED(yop);
1476	1454	temp = (xop * yop) << shift;
1477		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1455	res = m_core.mr.mr - (INT64)temp;
1478	1456	break;
1479	1457	case 0x0d<<13:
1480	1458	/* MR - X * Y (SU) */
1481		xop = MAC_GETXREG_SIGNED(adsp, xop);
1482		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1459	xop = MAC_GETXREG_SIGNED(xop);
	1460	yop = MAC_GETYREG_UNSIGNED(yop);
1483	1461	temp = (xop * yop) << shift;
1484		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1462	res = m_core.mr.mr - (INT64)temp;
1485	1463	break;
1486	1464	case 0x0e<<13:
1487	1465	/* MR - X * Y (US) */
1488		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1489		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1466	xop = MAC_GETXREG_UNSIGNED(xop);
	1467	yop = MAC_GETYREG_SIGNED(yop);
1490	1468	temp = (xop * yop) << shift;
1491		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1469	res = m_core.mr.mr - (INT64)temp;
1492	1470	break;
1493	1471	case 0x0f<<13:
1494	1472	/* MR - X * Y (UU) */
1495		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1496		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1473	xop = MAC_GETXREG_UNSIGNED(xop);
	1474	yop = MAC_GETYREG_UNSIGNED(yop);
1497	1475	temp = (xop * yop) << shift;
1498		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1476	res = m_core.mr.mr - (INT64)temp;
1499	1477	break;
1500	1478	default:
1501	1479	res = 0; /* just to keep the compiler happy */
r9081	r9082
1506	1484	temp = (res >> 31) & 0x1ff;
1507	1485	CLR_MV;
1508	1486	if (temp != 0x000 && temp != 0x1ff) SET_MV;
1509		~~adsp->~~core.mr.mr = res;
	1487	m_core.mr.mr = res;
1510	1488	}
1511	1489
1512	1490
r9081	r9082
1515	1493	MAC operations (result in MR, yop == xop)
1516	1494	===========================================================================*/
1517	1495
1518		~~static~~ void mac_op_mr_xop(~~adsp2100_state *adsp,~~ int op)
	1496	void adsp21xx_device::mac_op_mr_xop(int op)
1519	1497	{
1520		INT8 shift = ((~~adsp->~~mstat & MSTAT_INTEGER) >> 4) ^ 1;
	1498	INT8 shift = ((m_mstat & MSTAT_INTEGER) >> 4) ^ 1;
1521	1499	INT32 xop = (op >> 8) & 7;
1522	1500	INT32 temp;
1523	1501	INT64 res;
r9081	r9082
1529	1507	return;
1530	1508	case 0x01<<13:
1531	1509	/* X * Y (RND) */
1532		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1510	xop = MAC_GETXREG_SIGNED(xop);
1533	1511	temp = (xop * xop) << shift;
1534	1512	res = (INT64)temp;
1535	1513	#if 0
r9081	r9082
1544	1522	break;
1545	1523	case 0x02<<13:
1546	1524	/* MR + X * Y (RND) */
1547		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1525	xop = MAC_GETXREG_SIGNED(xop);
1548	1526	temp = (xop * xop) << shift;
1549		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1527	res = m_core.mr.mr + (INT64)temp;
1550	1528	#if 0
1551	1529	if ((res & 0xffff) == 0x8000) res &= ~((UINT64)0x10000);
1552	1530	else res += (res & 0x8000) << 1;
r9081	r9082
1559	1537	break;
1560	1538	case 0x03<<13:
1561	1539	/* MR - X * Y (RND) */
1562		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1540	xop = MAC_GETXREG_SIGNED(xop);
1563	1541	temp = (xop * xop) << shift;
1564		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1542	res = m_core.mr.mr - (INT64)temp;
1565	1543	#if 0
1566	1544	if ((res & 0xffff) == 0x8000) res &= ~((UINT64)0x10000);
1567	1545	else res += (res & 0x8000) << 1;
r9081	r9082
1574	1552	break;
1575	1553	case 0x04<<13:
1576	1554	/* X * Y (SS) Clear when y = 0 */
1577		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1555	xop = MAC_GETXREG_SIGNED(xop);
1578	1556	temp = (xop * xop) << shift;
1579	1557	res = (INT64)temp;
1580	1558	break;
1581	1559	case 0x05<<13:
1582	1560	/* X * Y (SU) */
1583		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1561	xop = MAC_GETXREG_SIGNED(xop);
1584	1562	temp = (xop * xop) << shift;
1585	1563	res = (INT64)temp;
1586	1564	break;
1587	1565	case 0x06<<13:
1588	1566	/* X * Y (US) */
1589		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1567	xop = MAC_GETXREG_UNSIGNED(xop);
1590	1568	temp = (xop * xop) << shift;
1591	1569	res = (INT64)temp;
1592	1570	break;
1593	1571	case 0x07<<13:
1594	1572	/* X * Y (UU) */
1595		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1573	xop = MAC_GETXREG_UNSIGNED(xop);
1596	1574	temp = (xop * xop) << shift;
1597	1575	res = (INT64)temp;
1598	1576	break;
1599	1577	case 0x08<<13:
1600	1578	/* MR + X * Y (SS) */
1601		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1579	xop = MAC_GETXREG_SIGNED(xop);
1602	1580	temp = (xop * xop) << shift;
1603		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1581	res = m_core.mr.mr + (INT64)temp;
1604	1582	break;
1605	1583	case 0x09<<13:
1606	1584	/* MR + X * Y (SU) */
1607		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1585	xop = MAC_GETXREG_SIGNED(xop);
1608	1586	temp = (xop * xop) << shift;
1609		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1587	res = m_core.mr.mr + (INT64)temp;
1610	1588	break;
1611	1589	case 0x0a<<13:
1612	1590	/* MR + X * Y (US) */
1613		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1591	xop = MAC_GETXREG_UNSIGNED(xop);
1614	1592	temp = (xop * xop) << shift;
1615		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1593	res = m_core.mr.mr + (INT64)temp;
1616	1594	break;
1617	1595	case 0x0b<<13:
1618	1596	/* MR + X * Y (UU) */
1619		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1597	xop = MAC_GETXREG_UNSIGNED(xop);
1620	1598	temp = (xop * xop) << shift;
1621		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1599	res = m_core.mr.mr + (INT64)temp;
1622	1600	break;
1623	1601	case 0x0c<<13:
1624	1602	/* MR - X * Y (SS) */
1625		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1603	xop = MAC_GETXREG_SIGNED(xop);
1626	1604	temp = (xop * xop) << shift;
1627		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1605	res = m_core.mr.mr - (INT64)temp;
1628	1606	break;
1629	1607	case 0x0d<<13:
1630	1608	/* MR - X * Y (SU) */
1631		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1609	xop = MAC_GETXREG_SIGNED(xop);
1632	1610	temp = (xop * xop) << shift;
1633		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1611	res = m_core.mr.mr - (INT64)temp;
1634	1612	break;
1635	1613	case 0x0e<<13:
1636	1614	/* MR - X * Y (US) */
1637		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1615	xop = MAC_GETXREG_UNSIGNED(xop);
1638	1616	temp = (xop * xop) << shift;
1639		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1617	res = m_core.mr.mr - (INT64)temp;
1640	1618	break;
1641	1619	case 0x0f<<13:
1642	1620	/* MR - X * Y (UU) */
1643		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1621	xop = MAC_GETXREG_UNSIGNED(xop);
1644	1622	temp = (xop * xop) << shift;
1645		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1623	res = m_core.mr.mr - (INT64)temp;
1646	1624	break;
1647	1625	default:
1648	1626	res = 0; /* just to keep the compiler happy */
r9081	r9082
1653	1631	temp = (res >> 31) & 0x1ff;
1654	1632	CLR_MV;
1655	1633	if (temp != 0x000 && temp != 0x1ff) SET_MV;
1656		~~adsp->~~core.mr.mr = res;
	1634	m_core.mr.mr = res;
1657	1635	}
1658	1636
1659	1637
r9081	r9082
1662	1640	MAC operations (result in MF)
1663	1641	===========================================================================*/
1664	1642
1665		~~static~~ void ma~~c_op_mf(a~~dsp2100_~~stat~~e *adsp, int op)
	1643	void adsp21xx_device::mac_op_mf(int op)
1666	1644	{
1667		INT8 shift = ((~~adsp->~~mstat & MSTAT_INTEGER) >> 4) ^ 1;
	1645	INT8 shift = ((m_mstat & MSTAT_INTEGER) >> 4) ^ 1;
1668	1646	INT32 xop = (op >> 8) & 7;
1669	1647	INT32 yop = (op >> 11) & 3;
1670	1648	INT32 temp;
r9081	r9082
1677	1655	return;
1678	1656	case 0x01<<13:
1679	1657	/* X * Y (RND) */
1680		xop = MAC_GETXREG_SIGNED(adsp, xop);
1681		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1658	xop = MAC_GETXREG_SIGNED(xop);
	1659	yop = MAC_GETYREG_SIGNED(yop);
1682	1660	temp = (xop * yop) << shift;
1683	1661	res = (INT64)temp;
1684	1662	#if 0
r9081	r9082
1693	1671	break;
1694	1672	case 0x02<<13:
1695	1673	/* MR + X * Y (RND) */
1696		xop = MAC_GETXREG_SIGNED(adsp, xop);
1697		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1674	xop = MAC_GETXREG_SIGNED(xop);
	1675	yop = MAC_GETYREG_SIGNED(yop);
1698	1676	temp = (xop * yop) << shift;
1699		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1677	res = m_core.mr.mr + (INT64)temp;
1700	1678	#if 0
1701	1679	if ((res & 0xffff) == 0x8000) res &= ~((UINT64)0x10000);
1702	1680	else res += (res & 0x8000) << 1;
r9081	r9082
1709	1687	break;
1710	1688	case 0x03<<13:
1711	1689	/* MR - X * Y (RND) */
1712		xop = MAC_GETXREG_SIGNED(adsp, xop);
1713		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1690	xop = MAC_GETXREG_SIGNED(xop);
	1691	yop = MAC_GETYREG_SIGNED(yop);
1714	1692	temp = (xop * yop) << shift;
1715		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1693	res = m_core.mr.mr - (INT64)temp;
1716	1694	#if 0
1717	1695	if ((res & 0xffff) == 0x8000) res &= ~((UINT64)0x10000);
1718	1696	else res += (res & 0x8000) << 1;
r9081	r9082
1725	1703	break;
1726	1704	case 0x04<<13:
1727	1705	/* X * Y (SS) Clear when y = 0 */
1728		xop = MAC_GETXREG_SIGNED(adsp, xop);
1729		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1706	xop = MAC_GETXREG_SIGNED(xop);
	1707	yop = MAC_GETYREG_SIGNED(yop);
1730	1708	temp = (xop * yop) << shift;
1731	1709	res = (INT64)temp;
1732	1710	break;
1733	1711	case 0x05<<13:
1734	1712	/* X * Y (SU) */
1735		xop = MAC_GETXREG_SIGNED(adsp, xop);
1736		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1713	xop = MAC_GETXREG_SIGNED(xop);
	1714	yop = MAC_GETYREG_UNSIGNED(yop);
1737	1715	temp = (xop * yop) << shift;
1738	1716	res = (INT64)temp;
1739	1717	break;
1740	1718	case 0x06<<13:
1741	1719	/* X * Y (US) */
1742		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1743		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1720	xop = MAC_GETXREG_UNSIGNED(xop);
	1721	yop = MAC_GETYREG_SIGNED(yop);
1744	1722	temp = (xop * yop) << shift;
1745	1723	res = (INT64)temp;
1746	1724	break;
1747	1725	case 0x07<<13:
1748	1726	/* X * Y (UU) */
1749		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1750		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1727	xop = MAC_GETXREG_UNSIGNED(xop);
	1728	yop = MAC_GETYREG_UNSIGNED(yop);
1751	1729	temp = (xop * yop) << shift;
1752	1730	res = (INT64)temp;
1753	1731	break;
1754	1732	case 0x08<<13:
1755	1733	/* MR + X * Y (SS) */
1756		xop = MAC_GETXREG_SIGNED(adsp, xop);
1757		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1734	xop = MAC_GETXREG_SIGNED(xop);
	1735	yop = MAC_GETYREG_SIGNED(yop);
1758	1736	temp = (xop * yop) << shift;
1759		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1737	res = m_core.mr.mr + (INT64)temp;
1760	1738	break;
1761	1739	case 0x09<<13:
1762	1740	/* MR + X * Y (SU) */
1763		xop = MAC_GETXREG_SIGNED(adsp, xop);
1764		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1741	xop = MAC_GETXREG_SIGNED(xop);
	1742	yop = MAC_GETYREG_UNSIGNED(yop);
1765	1743	temp = (xop * yop) << shift;
1766		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1744	res = m_core.mr.mr + (INT64)temp;
1767	1745	break;
1768	1746	case 0x0a<<13:
1769	1747	/* MR + X * Y (US) */
1770		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1771		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1748	xop = MAC_GETXREG_UNSIGNED(xop);
	1749	yop = MAC_GETYREG_SIGNED(yop);
1772	1750	temp = (xop * yop) << shift;
1773		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1751	res = m_core.mr.mr + (INT64)temp;
1774	1752	break;
1775	1753	case 0x0b<<13:
1776	1754	/* MR + X * Y (UU) */
1777		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1778		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1755	xop = MAC_GETXREG_UNSIGNED(xop);
	1756	yop = MAC_GETYREG_UNSIGNED(yop);
1779	1757	temp = (xop * yop) << shift;
1780		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1758	res = m_core.mr.mr + (INT64)temp;
1781	1759	break;
1782	1760	case 0x0c<<13:
1783	1761	/* MR - X * Y (SS) */
1784		xop = MAC_GETXREG_SIGNED(adsp, xop);
1785		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1762	xop = MAC_GETXREG_SIGNED(xop);
	1763	yop = MAC_GETYREG_SIGNED(yop);
1786	1764	temp = (xop * yop) << shift;
1787		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1765	res = m_core.mr.mr - (INT64)temp;
1788	1766	break;
1789	1767	case 0x0d<<13:
1790	1768	/* MR - X * Y (SU) */
1791		xop = MAC_GETXREG_SIGNED(adsp, xop);
1792		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1769	xop = MAC_GETXREG_SIGNED(xop);
	1770	yop = MAC_GETYREG_UNSIGNED(yop);
1793	1771	temp = (xop * yop) << shift;
1794		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1772	res = m_core.mr.mr - (INT64)temp;
1795	1773	break;
1796	1774	case 0x0e<<13:
1797	1775	/* MR - X * Y (US) */
1798		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1799		yop = MAC_GETYREG_SIGNED(adsp, yop);
	1776	xop = MAC_GETXREG_UNSIGNED(xop);
	1777	yop = MAC_GETYREG_SIGNED(yop);
1800	1778	temp = (xop * yop) << shift;
1801		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1779	res = m_core.mr.mr - (INT64)temp;
1802	1780	break;
1803	1781	case 0x0f<<13:
1804	1782	/* MR - X * Y (UU) */
1805		xop = MAC_GETXREG_UNSIGNED(adsp, xop);
1806		yop = MAC_GETYREG_UNSIGNED(adsp, yop);
	1783	xop = MAC_GETXREG_UNSIGNED(xop);
	1784	yop = MAC_GETYREG_UNSIGNED(yop);
1807	1785	temp = (xop * yop) << shift;
1808		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1786	res = m_core.mr.mr - (INT64)temp;
1809	1787	break;
1810	1788	default:
1811	1789	res = 0; /* just to keep the compiler happy */
r9081	r9082
1813	1791	}
1814	1792
1815	1793	/* set the final value */
1816		~~adsp->~~core.mf.u = (UINT32)res >> 16;
	1794	m_core.mf.u = (UINT32)res >> 16;
1817	1795	}
1818	1796
1819	1797
r9081	r9082
1822	1800	MAC operations (result in MF, yop == xop)
1823	1801	===========================================================================*/
1824	1802
1825		~~static~~ void mac_op_mf_xop(~~adsp2100_state *adsp,~~ int op)
	1803	void adsp21xx_device::mac_op_mf_xop(int op)
1826	1804	{
1827		INT8 shift = ((~~adsp->~~mstat & MSTAT_INTEGER) >> 4) ^ 1;
	1805	INT8 shift = ((m_mstat & MSTAT_INTEGER) >> 4) ^ 1;
1828	1806	INT32 xop = (op >> 8) & 7;
1829	1807	INT32 temp;
1830	1808	INT64 res;
r9081	r9082
1836	1814	return;
1837	1815	case 0x01<<13:
1838	1816	/* X * Y (RND) */
1839		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1817	xop = MAC_GETXREG_SIGNED(xop);
1840	1818	temp = (xop * xop) << shift;
1841	1819	res = (INT64)temp;
1842	1820	#if 0
r9081	r9082
1851	1829	break;
1852	1830	case 0x02<<13:
1853	1831	/* MR + X * Y (RND) */
1854		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1832	xop = MAC_GETXREG_SIGNED(xop);
1855	1833	temp = (xop * xop) << shift;
1856		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1834	res = m_core.mr.mr + (INT64)temp;
1857	1835	#if 0
1858	1836	if ((res & 0xffff) == 0x8000) res &= ~((UINT64)0x10000);
1859	1837	else res += (res & 0x8000) << 1;
r9081	r9082
1866	1844	break;
1867	1845	case 0x03<<13:
1868	1846	/* MR - X * Y (RND) */
1869		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1847	xop = MAC_GETXREG_SIGNED(xop);
1870	1848	temp = (xop * xop) << shift;
1871		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1849	res = m_core.mr.mr - (INT64)temp;
1872	1850	#if 0
1873	1851	if ((res & 0xffff) == 0x8000) res &= ~((UINT64)0x10000);
1874	1852	else res += (res & 0x8000) << 1;
r9081	r9082
1881	1859	break;
1882	1860	case 0x04<<13:
1883	1861	/* X * Y (SS) Clear when y = 0 */
1884		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1862	xop = MAC_GETXREG_SIGNED(xop);
1885	1863	temp = (xop * xop) << shift;
1886	1864	res = (INT64)temp;
1887	1865	break;
1888	1866	case 0x05<<13:
1889	1867	/* X * Y (SU) */
1890		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1868	xop = MAC_GETXREG_SIGNED(xop);
1891	1869	temp = (xop * xop) << shift;
1892	1870	res = (INT64)temp;
1893	1871	break;
1894	1872	case 0x06<<13:
1895	1873	/* X * Y (US) */
1896		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1874	xop = MAC_GETXREG_UNSIGNED(xop);
1897	1875	temp = (xop * xop) << shift;
1898	1876	res = (INT64)temp;
1899	1877	break;
1900	1878	case 0x07<<13:
1901	1879	/* X * Y (UU) */
1902		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1880	xop = MAC_GETXREG_UNSIGNED(xop);
1903	1881	temp = (xop * xop) << shift;
1904	1882	res = (INT64)temp;
1905	1883	break;
1906	1884	case 0x08<<13:
1907	1885	/* MR + X * Y (SS) */
1908		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1886	xop = MAC_GETXREG_SIGNED(xop);
1909	1887	temp = (xop * xop) << shift;
1910		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1888	res = m_core.mr.mr + (INT64)temp;
1911	1889	break;
1912	1890	case 0x09<<13:
1913	1891	/* MR + X * Y (SU) */
1914		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1892	xop = MAC_GETXREG_SIGNED(xop);
1915	1893	temp = (xop * xop) << shift;
1916		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1894	res = m_core.mr.mr + (INT64)temp;
1917	1895	break;
1918	1896	case 0x0a<<13:
1919	1897	/* MR + X * Y (US) */
1920		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1898	xop = MAC_GETXREG_UNSIGNED(xop);
1921	1899	temp = (xop * xop) << shift;
1922		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1900	res = m_core.mr.mr + (INT64)temp;
1923	1901	break;
1924	1902	case 0x0b<<13:
1925	1903	/* MR + X * Y (UU) */
1926		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1904	xop = MAC_GETXREG_UNSIGNED(xop);
1927	1905	temp = (xop * xop) << shift;
1928		res = ~~adsp->~~core.mr.mr + (INT64)temp;
	1906	res = m_core.mr.mr + (INT64)temp;
1929	1907	break;
1930	1908	case 0x0c<<13:
1931	1909	/* MR - X * Y (SS) */
1932		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1910	xop = MAC_GETXREG_SIGNED(xop);
1933	1911	temp = (xop * xop) << shift;
1934		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1912	res = m_core.mr.mr - (INT64)temp;
1935	1913	break;
1936	1914	case 0x0d<<13:
1937	1915	/* MR - X * Y (SU) */
1938		xop = MAC_GETXREG_SIGNED(~~adsp,~~ xop);
	1916	xop = MAC_GETXREG_SIGNED(xop);
1939	1917	temp = (xop * xop) << shift;
1940		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1918	res = m_core.mr.mr - (INT64)temp;
1941	1919	break;
1942	1920	case 0x0e<<13:
1943	1921	/* MR - X * Y (US) */
1944		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1922	xop = MAC_GETXREG_UNSIGNED(xop);
1945	1923	temp = (xop * xop) << shift;
1946		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1924	res = m_core.mr.mr - (INT64)temp;
1947	1925	break;
1948	1926	case 0x0f<<13:
1949	1927	/* MR - X * Y (UU) */
1950		xop = MAC_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1928	xop = MAC_GETXREG_UNSIGNED(xop);
1951	1929	temp = (xop * xop) << shift;
1952		res = ~~adsp->~~core.mr.mr - (INT64)temp;
	1930	res = m_core.mr.mr - (INT64)temp;
1953	1931	break;
1954	1932	default:
1955	1933	res = 0; /* just to keep the compiler happy */
r9081	r9082
1957	1935	}
1958	1936
1959	1937	/* set the final value */
1960		~~adsp->~~core.mf.u = (UINT32)res >> 16;
	1938	m_core.mf.u = (UINT32)res >> 16;
1961	1939	}
1962	1940
1963	1941
r9081	r9082
1966	1944	SHIFT operations (result in SR/SE/SB)
1967	1945	===========================================================================*/
1968	1946
1969		~~static~~ void ~~shift_op(~~adsp2100_~~state *a~~dsp, int op)
	1947	void adsp21xx_device::shift_op(int op)
1970	1948	{
1971		INT8 sc = ~~adsp->~~core.se.s;
	1949	INT8 sc = m_core.se.s;
1972	1950	INT32 xop = (op >> 8) & 7;
1973	1951	UINT32 res;
1974	1952
r9081	r9082
1976	1954	{
1977	1955	case 0x00<<11:
1978	1956	/* LSHIFT (HI) */
1979		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop) << 16;
	1957	xop = SHIFT_GETXREG_UNSIGNED(xop) << 16;
1980	1958	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
1981	1959	else res = (sc > -32) ? ((UINT32)xop >> -sc) : 0;
1982		~~adsp->~~core.sr.sr = res;
	1960	m_core.sr.sr = res;
1983	1961	break;
1984	1962	case 0x01<<11:
1985	1963	/* LSHIFT (HI, OR) */
1986		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop) << 16;
	1964	xop = SHIFT_GETXREG_UNSIGNED(xop) << 16;
1987	1965	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
1988	1966	else res = (sc > -32) ? ((UINT32)xop >> -sc) : 0;
1989		~~adsp->~~core.sr.sr \|= res;
	1967	m_core.sr.sr \|= res;
1990	1968	break;
1991	1969	case 0x02<<11:
1992	1970	/* LSHIFT (LO) */
1993		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1971	xop = SHIFT_GETXREG_UNSIGNED(xop);
1994	1972	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
1995	1973	else res = (sc > -32) ? (xop >> -sc) : 0;
1996		~~adsp->~~core.sr.sr = res;
	1974	m_core.sr.sr = res;
1997	1975	break;
1998	1976	case 0x03<<11:
1999	1977	/* LSHIFT (LO, OR) */
2000		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1978	xop = SHIFT_GETXREG_UNSIGNED(xop);
2001	1979	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2002	1980	else res = (sc > -32) ? (xop >> -sc) : 0;
2003		~~adsp->~~core.sr.sr \|= res;
	1981	m_core.sr.sr \|= res;
2004	1982	break;
2005	1983	case 0x04<<11:
2006	1984	/* ASHIFT (HI) */
2007		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop) << 16;
	1985	xop = SHIFT_GETXREG_SIGNED(xop) << 16;
2008	1986	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2009	1987	else res = (sc > -32) ? (xop >> -sc) : (xop >> 31);
2010		~~adsp->~~core.sr.sr = res;
	1988	m_core.sr.sr = res;
2011	1989	break;
2012	1990	case 0x05<<11:
2013	1991	/* ASHIFT (HI, OR) */
2014		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop) << 16;
	1992	xop = SHIFT_GETXREG_SIGNED(xop) << 16;
2015	1993	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2016	1994	else res = (sc > -32) ? (xop >> -sc) : (xop >> 31);
2017		~~adsp->~~core.sr.sr \|= res;
	1995	m_core.sr.sr \|= res;
2018	1996	break;
2019	1997	case 0x06<<11:
2020	1998	/* ASHIFT (LO) */
2021		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop);
	1999	xop = SHIFT_GETXREG_SIGNED(xop);
2022	2000	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2023	2001	else res = (sc > -32) ? (xop >> -sc) : (xop >> 31);
2024		~~adsp->~~core.sr.sr = res;
	2002	m_core.sr.sr = res;
2025	2003	break;
2026	2004	case 0x07<<11:
2027	2005	/* ASHIFT (LO, OR) */
2028		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop);
	2006	xop = SHIFT_GETXREG_SIGNED(xop);
2029	2007	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2030	2008	else res = (sc > -32) ? (xop >> -sc) : (xop >> 31);
2031		~~adsp->~~core.sr.sr \|= res;
	2009	m_core.sr.sr \|= res;
2032	2010	break;
2033	2011	case 0x08<<11:
2034	2012	/* NORM (HI) */
2035		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop) << 16;
	2013	xop = SHIFT_GETXREG_SIGNED(xop) << 16;
2036	2014	if (sc > 0)
2037	2015	{
2038		xop = ((UINT32)xop >> 1) \| ((~~adsp->~~astat & CFLAG) << 28);
	2016	xop = ((UINT32)xop >> 1) \| ((m_astat & CFLAG) << 28);
2039	2017	res = xop >> (sc - 1);
2040	2018	}
2041	2019	else res = (sc > -32) ? (xop << -sc) : 0;
2042		~~adsp->~~core.sr.sr = res;
	2020	m_core.sr.sr = res;
2043	2021	break;
2044	2022	case 0x09<<11:
2045	2023	/* NORM (HI, OR) */
2046		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop) << 16;
	2024	xop = SHIFT_GETXREG_SIGNED(xop) << 16;
2047	2025	if (sc > 0)
2048	2026	{
2049		xop = ((UINT32)xop >> 1) \| ((~~adsp->~~astat & CFLAG) << 28);
	2027	xop = ((UINT32)xop >> 1) \| ((m_astat & CFLAG) << 28);
2050	2028	res = xop >> (sc - 1);
2051	2029	}
2052	2030	else res = (sc > -32) ? (xop << -sc) : 0;
2053		~~adsp->~~core.sr.sr \|= res;
	2031	m_core.sr.sr \|= res;
2054	2032	break;
2055	2033	case 0x0a<<11:
2056	2034	/* NORM (LO) */
2057		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop);
	2035	xop = SHIFT_GETXREG_UNSIGNED(xop);
2058	2036	if (sc > 0) res = (sc < 32) ? (xop >> sc) : 0;
2059	2037	else res = (sc > -32) ? (xop << -sc) : 0;
2060		~~adsp->~~core.sr.sr = res;
	2038	m_core.sr.sr = res;
2061	2039	break;
2062	2040	case 0x0b<<11:
2063	2041	/* NORM (LO, OR) */
2064		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop);
	2042	xop = SHIFT_GETXREG_UNSIGNED(xop);
2065	2043	if (sc > 0) res = (sc < 32) ? (xop >> sc) : 0;
2066	2044	else res = (sc > -32) ? (xop << -sc) : 0;
2067		~~adsp->~~core.sr.sr \|= res;
	2045	m_core.sr.sr \|= res;
2068	2046	break;
2069	2047	case 0x0c<<11:
2070	2048	/* EXP (HI) */
2071		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop) << 16;
	2049	xop = SHIFT_GETXREG_SIGNED(xop) << 16;
2072	2050	res = 0;
2073	2051	if (xop < 0)
2074	2052	{
r9081	r9082
2081	2059	xop \|= 0x8000;
2082	2060	while ((xop & 0x40000000) == 0) res++, xop <<= 1;
2083	2061	}
2084		~~adsp->~~core.se.s = -res;
	2062	m_core.se.s = -res;
2085	2063	break;
2086	2064	case 0x0d<<11:
2087	2065	/* EXP (HIX) */
2088		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop) << 16;
	2066	xop = SHIFT_GETXREG_SIGNED(xop) << 16;
2089	2067	if (GET_V)
2090	2068	{
2091		~~adsp->~~core.se.s = 1;
	2069	m_core.se.s = 1;
2092	2070	if (xop < 0) CLR_SS;
2093	2071	else SET_SS;
2094	2072	}
r9081	r9082
2106	2084	xop \|= 0x8000;
2107	2085	while ((xop & 0x40000000) == 0) res++, xop <<= 1;
2108	2086	}
2109		~~adsp->~~core.se.s = -res;
	2087	m_core.se.s = -res;
2110	2088	}
2111	2089	break;
2112	2090	case 0x0e<<11:
2113	2091	/* EXP (LO) */
2114		if (~~adsp->~~core.se.s == -15)
	2092	if (m_core.se.s == -15)
2115	2093	{
2116		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop);
	2094	xop = SHIFT_GETXREG_SIGNED(xop);
2117	2095	res = 15;
2118	2096	if (GET_SS)
2119	2097	while ((xop & 0x8000) != 0) res++, xop <<= 1;
r9081	r9082
2122	2100	xop = (xop << 1) \| 1;
2123	2101	while ((xop & 0x10000) == 0) res++, xop <<= 1;
2124	2102	}
2125		~~adsp->~~core.se.s = -res;
	2103	m_core.se.s = -res;
2126	2104	}
2127	2105	break;
2128	2106	case 0x0f<<11:
2129	2107	/* EXPADJ */
2130		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop) << 16;
	2108	xop = SHIFT_GETXREG_SIGNED(xop) << 16;
2131	2109	res = 0;
2132	2110	if (xop < 0)
2133	2111	while ((xop & 0x40000000) != 0) res++, xop <<= 1;
r9081	r9082
2136	2114	xop \|= 0x8000;
2137	2115	while ((xop & 0x40000000) == 0) res++, xop <<= 1;
2138	2116	}
2139		if (res < -adsp->core.sb.s)
2140		adsp->core.sb.s = -res;
	2117	if (res < -m_core.sb.s)
	2118	m_core.sb.s = -res;
2141	2119	break;
2142	2120	}
2143	2121	}
r9081	r9082
2148	2126	Immediate SHIFT operations (result in SR/SE/SB)
2149	2127	===========================================================================*/
2150	2128
2151		~~static~~ void shift_op_imm(~~adsp2100_state *adsp,~~ int op)
	2129	void adsp21xx_device::shift_op_imm(int op)
2152	2130	{
2153	2131	INT8 sc = (INT8)op;
2154	2132	INT32 xop = (op >> 8) & 7;
r9081	r9082
2158	2136	{
2159	2137	case 0x00<<11:
2160	2138	/* LSHIFT (HI) */
2161		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop) << 16;
	2139	xop = SHIFT_GETXREG_UNSIGNED(xop) << 16;
2162	2140	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2163	2141	else res = (sc > -32) ? ((UINT32)xop >> -sc) : 0;
2164		~~adsp->~~core.sr.sr = res;
	2142	m_core.sr.sr = res;
2165	2143	break;
2166	2144	case 0x01<<11:
2167	2145	/* LSHIFT (HI, OR) */
2168		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop) << 16;
	2146	xop = SHIFT_GETXREG_UNSIGNED(xop) << 16;
2169	2147	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2170	2148	else res = (sc > -32) ? ((UINT32)xop >> -sc) : 0;
2171		~~adsp->~~core.sr.sr \|= res;
	2149	m_core.sr.sr \|= res;
2172	2150	break;
2173	2151	case 0x02<<11:
2174	2152	/* LSHIFT (LO) */
2175		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop);
	2153	xop = SHIFT_GETXREG_UNSIGNED(xop);
2176	2154	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2177	2155	else res = (sc > -32) ? (xop >> -sc) : 0;
2178		~~adsp->~~core.sr.sr = res;
	2156	m_core.sr.sr = res;
2179	2157	break;
2180	2158	case 0x03<<11:
2181	2159	/* LSHIFT (LO, OR) */
2182		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop);
	2160	xop = SHIFT_GETXREG_UNSIGNED(xop);
2183	2161	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2184	2162	else res = (sc > -32) ? (xop >> -sc) : 0;
2185		~~adsp->~~core.sr.sr \|= res;
	2163	m_core.sr.sr \|= res;
2186	2164	break;
2187	2165	case 0x04<<11:
2188	2166	/* ASHIFT (HI) */
2189		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop) << 16;
	2167	xop = SHIFT_GETXREG_SIGNED(xop) << 16;
2190	2168	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2191	2169	else res = (sc > -32) ? (xop >> -sc) : (xop >> 31);
2192		~~adsp->~~core.sr.sr = res;
	2170	m_core.sr.sr = res;
2193	2171	break;
2194	2172	case 0x05<<11:
2195	2173	/* ASHIFT (HI, OR) */
2196		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop) << 16;
	2174	xop = SHIFT_GETXREG_SIGNED(xop) << 16;
2197	2175	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2198	2176	else res = (sc > -32) ? (xop >> -sc) : (xop >> 31);
2199		~~adsp->~~core.sr.sr \|= res;
	2177	m_core.sr.sr \|= res;
2200	2178	break;
2201	2179	case 0x06<<11:
2202	2180	/* ASHIFT (LO) */
2203		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop);
	2181	xop = SHIFT_GETXREG_SIGNED(xop);
2204	2182	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2205	2183	else res = (sc > -32) ? (xop >> -sc) : (xop >> 31);
2206		~~adsp->~~core.sr.sr = res;
	2184	m_core.sr.sr = res;
2207	2185	break;
2208	2186	case 0x07<<11:
2209	2187	/* ASHIFT (LO, OR) */
2210		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop);
	2188	xop = SHIFT_GETXREG_SIGNED(xop);
2211	2189	if (sc > 0) res = (sc < 32) ? (xop << sc) : 0;
2212	2190	else res = (sc > -32) ? (xop >> -sc) : (xop >> 31);
2213		~~adsp->~~core.sr.sr \|= res;
	2191	m_core.sr.sr \|= res;
2214	2192	break;
2215	2193	case 0x08<<11:
2216	2194	/* NORM (HI) */
2217		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop) << 16;
	2195	xop = SHIFT_GETXREG_SIGNED(xop) << 16;
2218	2196	if (sc > 0)
2219	2197	{
2220		xop = ((UINT32)xop >> 1) \| ((~~adsp->~~astat & CFLAG) << 28);
	2198	xop = ((UINT32)xop >> 1) \| ((m_astat & CFLAG) << 28);
2221	2199	res = xop >> (sc - 1);
2222	2200	}
2223	2201	else res = (sc > -32) ? (xop << -sc) : 0;
2224		~~adsp->~~core.sr.sr = res;
	2202	m_core.sr.sr = res;
2225	2203	break;
2226	2204	case 0x09<<11:
2227	2205	/* NORM (HI, OR) */
2228		xop = SHIFT_GETXREG_SIGNED(~~adsp,~~ xop) << 16;
	2206	xop = SHIFT_GETXREG_SIGNED(xop) << 16;
2229	2207	if (sc > 0)
2230	2208	{
2231		xop = ((UINT32)xop >> 1) \| ((~~adsp->~~astat & CFLAG) << 28);
	2209	xop = ((UINT32)xop >> 1) \| ((m_astat & CFLAG) << 28);
2232	2210	res = xop >> (sc - 1);
2233	2211	}
2234	2212	else res = (sc > -32) ? (xop << -sc) : 0;
2235		~~adsp->~~core.sr.sr \|= res;
	2213	m_core.sr.sr \|= res;
2236	2214	break;
2237	2215	case 0x0a<<11:
2238	2216	/* NORM (LO) */
2239		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop);
	2217	xop = SHIFT_GETXREG_UNSIGNED(xop);
2240	2218	if (sc > 0) res = (sc < 32) ? (xop >> sc) : 0;
2241	2219	else res = (sc > -32) ? (xop << -sc) : 0;
2242		~~adsp->~~core.sr.sr = res;
	2220	m_core.sr.sr = res;
2243	2221	break;
2244	2222	case 0x0b<<11:
2245	2223	/* NORM (LO, OR) */
2246		xop = SHIFT_GETXREG_UNSIGNED(~~adsp,~~ xop);
	2224	xop = SHIFT_GETXREG_UNSIGNED(xop);
2247	2225	if (sc > 0) res = (sc < 32) ? (xop >> sc) : 0;
2248	2226	else res = (sc > -32) ? (xop << -sc) : 0;
2249		~~adsp->~~core.sr.sr \|= res;
	2227	m_core.sr.sr \|= res;
2250	2228	break;
2251	2229	}
2252	2230	}

src/emu/cpu/adsp2100/adsp2100.c
r9081	r9082
1	1	/***************************************************************************
2	2
3		ADSP2100.c
4		Core implementation for the portable Analog ADSP-2100 emulator.
5		Written by Aaron Giles
	3	ADSP2100.c
6	4
	5	ADSP-21xx series emulator.
	6
7	7	****************************************************************************
8	8
	9	Copyright Aaron Giles
	10	All rights reserved.
	11
	12	Redistribution and use in source and binary forms, with or without
	13	modification, are permitted provided that the following conditions are
	14	met:
	15
	16	* Redistributions of source code must retain the above copyright
	17	notice, this list of conditions and the following disclaimer.
	18	* Redistributions in binary form must reproduce the above copyright
	19	notice, this list of conditions and the following disclaimer in
	20	the documentation and/or other materials provided with the
	21	distribution.
	22	* Neither the name 'MAME' nor the names of its contributors may be
	23	used to endorse or promote products derived from this software
	24	without specific prior written permission.
	25
	26	THIS SOFTWARE IS PROVIDED BY AARON GILES ''AS IS'' AND ANY EXPRESS OR
	27	IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	28	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	29	DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT,
	30	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	31	(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
	32	SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	33	HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
	34	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
	35	IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	36	POSSIBILITY OF SUCH DAMAGE.
	37
	38	****************************************************************************
	39
9	40	For ADSP-2101, ADSP-2111
10	41	------------------------
11	42
r9081	r9082
100	131	#include "adsp2100.h"
101	132
102	133
103		/***************************************************************************
104		CONSTANTS
105		***************************************************************************/
	134	//**************************************************************************
	135	// DEVICE DEFINITIONS
	136	//**************************************************************************
106	137
107		#define TRACK_HOTSPOTS 0
	138	const device_type ADSP2100 = adsp2100_device_config::static_alloc_device_config;
	139	const device_type ADSP2101 = adsp2101_device_config::static_alloc_device_config;
	140	const device_type ADSP2104 = adsp2104_device_config::static_alloc_device_config;
	141	const device_type ADSP2105 = adsp2105_device_config::static_alloc_device_config;
	142	const device_type ADSP2115 = adsp2115_device_config::static_alloc_device_config;
	143	const device_type ADSP2181 = adsp2181_device_config::static_alloc_device_config;
108	144
109		/* stack depths */
110		#define PC_STACK_DEPTH 16
111		#define CNTR_STACK_DEPTH 4
112		#define STAT_STACK_DEPTH 4
113		#define LOOP_STACK_DEPTH 4
114	145
115		/* chip types */
116		#define CHIP_TYPE_ADSP2100 0
117		#define CHIP_TYPE_ADSP2101 1
118		#define CHIP_TYPE_ADSP2104 2
119		#define CHIP_TYPE_ADSP2105 3
120		#define CHIP_TYPE_ADSP2115 4
121		#define CHIP_TYPE_ADSP2181 5
122	146
	147	//**************************************************************************
	148	// TRIVIAL IMPLEMENTATIONS
	149	//**************************************************************************
123	150
	151	DEFINE_TRIVIAL_DERIVED_DEVICE(adsp2104_device_config, adsp2101_device_config, adsp2104_device, adsp2101_device, "ADSP-2104", CHIP_TYPE_ADSP2104)
	152	DEFINE_TRIVIAL_DERIVED_DEVICE(adsp2105_device_config, adsp2101_device_config, adsp2105_device, adsp2101_device, "ADSP-2105", CHIP_TYPE_ADSP2105)
	153	DEFINE_TRIVIAL_DERIVED_DEVICE(adsp2115_device_config, adsp2101_device_config, adsp2115_device, adsp2101_device, "ADSP-2115", CHIP_TYPE_ADSP2115)
124	154
125		/***************************************************************************
126		STRUCTURES & TYPEDEFS
127		***************************************************************************/
128	155
129		/* 16-bit registers that can be loaded signed or unsigned */
130		typedef union
	156
	157	//**************************************************************************
	158	// ADSP21XX DEVICE CONFIG
	159	//**************************************************************************
	160
	161	//-------------------------------------------------
	162	// adsp21xx_device_config - constructor
	163	//-------------------------------------------------
	164
	165	adsp21xx_device_config::adsp21xx_device_config(const machine_config &mconfig, device_type type, const char name, const char tag, const device_config *owner, UINT32 clock, UINT32 chiptype)
	166	: cpu_device_config(mconfig, type, name, tag, owner, clock),
	167	m_program_config("program", ENDIANNESS_LITTLE, 32, 14, -2),
	168	m_data_config("data", ENDIANNESS_LITTLE, 16, 14, -1),
	169	m_chip_type(chiptype)
131	170	{
132		UINT16 u;
133		INT16 s;
134		} ADSPREG16;
	171	}
135	172
	173	adsp2100_device_config::adsp2100_device_config(const machine_config &mconfig, const char tag, const device_config owner, UINT32 clock)
	174	: adsp21xx_device_config(mconfig, static_alloc_device_config, "ADSP-2100", tag, owner, clock, CHIP_TYPE_ADSP2100) { }
136	175
137		/* the SHIFT result register is 32 bits */
138		typedef union
	176	adsp2101_device_config::adsp2101_device_config(const machine_config &mconfig, device_type type, const char name, const char tag, const device_config *owner, UINT32 clock, UINT32 chiptype)
	177	: adsp21xx_device_config(mconfig, type, name, tag, owner, clock, chiptype) { }
	178
	179	adsp2181_device_config::adsp2181_device_config(const machine_config &mconfig, const char tag, const device_config owner, UINT32 clock)
	180	: adsp21xx_device_config(mconfig, static_alloc_device_config, "ADSP-2181", tag, owner, clock, CHIP_TYPE_ADSP2181),
	181	m_io_config("I/O", ENDIANNESS_LITTLE, 16, 11, -1) { }
	182
	183
	184	//-------------------------------------------------
	185	// static_alloc_device_config - allocate a new
	186	// configuration object
	187	//-------------------------------------------------
	188
	189	device_config adsp2100_device_config::static_alloc_device_config(const machine_config &mconfig, const char tag, const device_config *owner, UINT32 clock)
139	190	{
140		#ifdef LSB_FIRST
141		struct { ADSPREG16 sr0, sr1; } srx;
142		#else
143		struct { ADSPREG16 sr1, sr0; } srx;
144		#endif
145		UINT32 sr;
146		} SHIFTRESULT;
	191	return global_alloc(adsp2100_device_config(mconfig, tag, owner, clock));
	192	}
	193
	194	device_config adsp2101_device_config::static_alloc_device_config(const machine_config &mconfig, const char tag, const device_config *owner, UINT32 clock)
	195	{
	196	return global_alloc(adsp2101_device_config(mconfig, static_alloc_device_config, "ADSP-2101", tag, owner, clock, CHIP_TYPE_ADSP2101));
	197	}
	198
	199	device_config adsp2181_device_config::static_alloc_device_config(const machine_config &mconfig, const char tag, const device_config *owner, UINT32 clock)
	200	{
	201	return global_alloc(adsp2181_device_config(mconfig, tag, owner, clock));
	202	}
147	203
148	204
149		/* the MAC result register is 40 bits */
150		typedef union
	205	//-------------------------------------------------
	206	// alloc_device - allocate a new device object
	207	//-------------------------------------------------
	208
	209	device_t *adsp2100_device_config::alloc_device(running_machine &machine) const
151	210	{
152		#ifdef LSB_FIRST
153		struct { ADSPREG16 mr0, mr1, mr2, mrzero; } mrx;
154		struct { UINT32 mr0, mr1; } mry;
155		#else
156		struct { ADSPREG16 mrzero, mr2, mr1, mr0; } mrx;
157		struct { UINT32 mr1, mr0; } mry;
158		#endif
159		UINT64 mr;
160		} MACRESULT;
	211	return auto_alloc(&machine, adsp2100_device(machine, *this));
	212	}
161	213
162		/* there are two banks of "core" registers */
163		typedef struct ADSPCORE
	214	device_t *adsp2101_device_config::alloc_device(running_machine &machine) const
164	215	{
165		/* ALU registers */
166		ADSPREG16 ax0, ax1;
167		ADSPREG16 ay0, ay1;
168		ADSPREG16 ar;
169		ADSPREG16 af;
	216	return auto_alloc(&machine, adsp2101_device(machine, *this));
	217	}
170	218
171		/* MAC registers */
172		ADSPREG16 mx0, mx1;
173		ADSPREG16 my0, my1;
174		MACRESULT mr;
175		ADSPREG16 mf;
	219	device_t *adsp2181_device_config::alloc_device(running_machine &machine) const
	220	{
	221	return auto_alloc(&machine, adsp2181_device(machine, *this));
	222	}
176	223
177		/* SHIFT registers */
178		ADSPREG16 si;
179		ADSPREG16 se;
180		ADSPREG16 sb;
181		SHIFTRESULT sr;
182	224
183		/* dummy registers */
184		ADSPREG16 zero;
185		} ADSPCORE;
	225	//-------------------------------------------------
	226	// static_set_config - set the configuration
	227	// structure
	228	//-------------------------------------------------
186	229
	230	void adsp21xx_device_config::static_set_config(device_config *device, const adsp21xx_config &config)
	231	{
	232	adsp21xx_device_config adsp = downcast<adsp21xx_device_config >(device);
	233	static_cast<adsp21xx_config >(adsp) = config;
	234	}
187	235
188		/* ADSP-2100 Registers */
189		typedef struct
	236
	237	//-------------------------------------------------
	238	// execute_min_cycles - return minimum number of
	239	// cycles it takes for one instruction to execute
	240	//-------------------------------------------------
	241
	242	UINT32 adsp21xx_device_config::execute_min_cycles() const
190	243	{
191		/* Core registers, 2 banks */
192		ADSPCORE core;
193		ADSPCORE alt;
	244	return 1;
	245	}
194	246
195		/* Memory addressing registers */
196		UINT32 i[8];
197		INT32 m[8];
198		UINT32 l[8];
199		UINT32 lmask[8];
200		UINT32 base[8];
201		UINT8 px;
202	247
203		/* other CPU registers */
204		UINT32 pc;
205		UINT32 ppc;
206		UINT32 loop;
207		UINT32 loop_condition;
208		UINT32 cntr;
	248	//-------------------------------------------------
	249	// execute_max_cycles - return maximum number of
	250	// cycles it takes for one instruction to execute
	251	//-------------------------------------------------
209	252
210		/* status registers */
211		UINT32 astat;
212		UINT32 sstat;
213		UINT32 mstat;
214		UINT32 mstat_prev;
215		UINT32 astat_clear;
216		UINT32 idle;
	253	UINT32 adsp21xx_device_config::execute_max_cycles() const
	254	{
	255	return 1;
	256	}
217	257
218		/* stacks */
219		UINT32 loop_stack[LOOP_STACK_DEPTH];
220		UINT32 cntr_stack[CNTR_STACK_DEPTH];
221		UINT32 pc_stack[PC_STACK_DEPTH];
222		UINT16 stat_stack[STAT_STACK_DEPTH][3];
223		INT32 pc_sp;
224		INT32 cntr_sp;
225		INT32 stat_sp;
226		INT32 loop_sp;
227	258
228		/* external I/O */
229		UINT8 flagout;
230		UINT8 flagin;
231		UINT8 fl0;
232		UINT8 fl1;
233		UINT8 fl2;
234		UINT16 idma_addr;
235		UINT16 idma_cache;
236		UINT8 idma_offs;
	259	//-------------------------------------------------
	260	// execute_input_lines - return the number of
	261	// input/interrupt lines
	262	//-------------------------------------------------
237	263
238		/* interrupt handling */
239		UINT16 imask;
240		UINT8 icntl;
241		UINT16 ifc;
242		UINT8 irq_state[9];
243		UINT8 irq_latch[9];
244		device_irq_callback irq_callback;
245		legacy_cpu_device *device;
	264	UINT32 adsp2100_device_config::execute_input_lines() const
	265	{
	266	return 4;
	267	}
246	268
247		/* other internal states */
248		int icount;
249		int chip_type;
250		int mstat_mask;
251		int imask_mask;
	269	UINT32 adsp2101_device_config::execute_input_lines() const
	270	{
	271	return 5;
	272	}
252	273
253		/* register maps */
254		void * alu_xregs[8];
255		void * alu_yregs[4];
256		void * mac_xregs[8];
257		void * mac_yregs[4];
258		void * shift_xregs[8];
	274	UINT32 adsp2181_device_config::execute_input_lines() const
	275	{
	276	return 9;
	277	}
259	278
260		/* other callbacks */
261		adsp21xx_rx_func sport_rx_callback;
262		adsp21xx_tx_func sport_tx_callback;
263		adsp21xx_timer_func timer_fired;
264	279
265		/* memory spaces */
266		address_space *program;
267		direct_read_data *direct;
268		address_space *data;
269		address_space *io;
	280	//-------------------------------------------------
	281	// memory_space_config - return the configuration
	282	// of the specified address space, or NULL if
	283	// the space doesn't exist
	284	//-------------------------------------------------
270	285
271		} adsp2100_state;
	286	const address_space_config *adsp2100_device_config::memory_space_config(int spacenum) const
	287	{
	288	return (spacenum == AS_PROGRAM) ? &m_program_config :
	289	(spacenum == AS_DATA) ? &m_data_config :
	290	NULL;
	291	}
272	292
	293	const address_space_config *adsp2101_device_config::memory_space_config(int spacenum) const
	294	{
	295	return (spacenum == AS_PROGRAM) ? &m_program_config :
	296	(spacenum == AS_DATA) ? &m_data_config :
	297	NULL;
	298	}
273	299
	300	const address_space_config *adsp2181_device_config::memory_space_config(int spacenum) const
	301	{
	302	return (spacenum == AS_PROGRAM) ? &m_program_config :
	303	(spacenum == AS_DATA) ? &m_data_config :
	304	(spacenum == AS_IO) ? &m_io_config :
	305	NULL;
	306	}
274	307
275		/***************************************************************************
276		PRIVATE GLOBAL VARIABLES
277		***************************************************************************/
278	308
279		static UINT16 *reverse_table = 0;
280		static UINT16 *mask_table = 0;
281		static UINT8 *condition_table = 0;
	309	//-------------------------------------------------
	310	// disasm_min_opcode_bytes - return the length
	311	// of the shortest instruction, in bytes
	312	//-------------------------------------------------
282	313
283		#if TRACK_HOTSPOTS
284		static UINT32 pcbucket[0x4000];
285		#endif
	314	UINT32 adsp21xx_device_config::disasm_min_opcode_bytes() const
	315	{
	316	return 4;
	317	}
286	318
287	319
	320	//-------------------------------------------------
	321	// disasm_max_opcode_bytes - return the length
	322	// of the longest instruction, in bytes
	323	//-------------------------------------------------
288	324
289		/***************************************************************************
290		PRIVATE FUNCTION PROTOTYPES
291		***************************************************************************/
	325	UINT32 adsp21xx_device_config::disasm_max_opcode_bytes() const
	326	{
	327	return 4;
	328	}
292	329
293		static int create_tables(void);
294		static void check_irqs(adsp2100_state *adsp);
295	330
296	331
	332	//**************************************************************************
	333	// DEVICE INTERFACE
	334	//**************************************************************************
297	335
298		/***************************************************************************
299		STATE ACCESSORS
300		***************************************************************************/
	336	//-------------------------------------------------
	337	// adsp21xx_device - constructor
	338	//-------------------------------------------------
301	339
302		INLINE adsp2100_state get_safe_token(running_device device)
	340	adsp21xx_device::adsp21xx_device(running_machine &_machine, const adsp21xx_device_config &config)
	341	: cpu_device(_machine, config),
	342	m_config(config),
	343	m_pc(0),
	344	m_ppc(0),
	345	m_loop(0),
	346	m_loop_condition(0),
	347	m_cntr(0),
	348	m_astat(0),
	349	m_sstat(0),
	350	m_mstat(0),
	351	m_mstat_prev(0),
	352	m_astat_clear(0),
	353	m_idle(0),
	354	m_px(0),
	355	m_pc_sp(0),
	356	m_cntr_sp(0),
	357	m_stat_sp(0),
	358	m_loop_sp(0),
	359	m_flagout(0),
	360	m_flagin(0),
	361	m_fl0(0),
	362	m_fl1(0),
	363	m_fl2(0),
	364	m_idma_addr(0),
	365	m_idma_cache(0),
	366	m_idma_offs(0),
	367	m_imask(0),
	368	m_icntl(0),
	369	m_ifc(0),
	370	m_icount(0),
	371	m_mstat_mask((config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2101) ? 0x7f : 0x0f),
	372	m_imask_mask((config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2181) ? 0x3ff :
	373	(config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2101) ? 0x3f : 0x0f)
303	374	{
304		assert(device != NULL);
305		assert(device->type() == ADSP2100 \|\|
306		device->type() == ADSP2101 \|\|
307		device->type() == ADSP2104 \|\|
308		device->type() == ADSP2105 \|\|
309		device->type() == ADSP2115 \|\|
310		device->type() == ADSP2181);
311		return (adsp2100_state )downcast<legacy_cpu_device >(device)->token();
	375	// initialize remaining state
	376	memset(&m_core, 0, sizeof(m_core));
	377	memset(&m_alt, 0, sizeof(m_alt));
	378	memset(&m_i, 0, sizeof(m_i));
	379	memset(&m_m, 0, sizeof(m_m));
	380	memset(&m_l, 0, sizeof(m_l));
	381	memset(&m_lmask, 0, sizeof(m_lmask));
	382	memset(&m_base, 0, sizeof(m_base));
	383	memset(&m_loop_stack, 0, sizeof(m_loop_stack));
	384	memset(&m_cntr_stack, 0, sizeof(m_cntr_stack));
	385	memset(&m_pc_stack, 0, sizeof(m_pc_stack));
	386	memset(&m_stat_stack, 0, sizeof(m_stat_stack));
	387	memset(&m_irq_state, 0, sizeof(m_irq_state));
	388	memset(&m_irq_latch, 0, sizeof(m_irq_latch));
	389
	390	// create the tables
	391	create_tables();
	392
	393	// set up read register group 0 pointers
	394	m_read0_ptr[0x00] = &m_core.ax0.s;
	395	m_read0_ptr[0x01] = &m_core.ax1.s;
	396	m_read0_ptr[0x02] = &m_core.mx0.s;
	397	m_read0_ptr[0x03] = &m_core.mx1.s;
	398	m_read0_ptr[0x04] = &m_core.ay0.s;
	399	m_read0_ptr[0x05] = &m_core.ay1.s;
	400	m_read0_ptr[0x06] = &m_core.my0.s;
	401	m_read0_ptr[0x07] = &m_core.my1.s;
	402	m_read0_ptr[0x08] = &m_core.si.s;
	403	m_read0_ptr[0x09] = &m_core.se.s;
	404	m_read0_ptr[0x0a] = &m_core.ar.s;
	405	m_read0_ptr[0x0b] = &m_core.mr.mrx.mr0.s;
	406	m_read0_ptr[0x0c] = &m_core.mr.mrx.mr1.s;
	407	m_read0_ptr[0x0d] = &m_core.mr.mrx.mr2.s;
	408	m_read0_ptr[0x0e] = &m_core.sr.srx.sr0.s;
	409	m_read0_ptr[0x0f] = &m_core.sr.srx.sr1.s;
	410
	411	// set up read register group 1 + 2 pointers
	412	for (int index = 0; index < 4; index++)
	413	{
	414	m_read1_ptr[0x00 + index] = &m_i[0 + index];
	415	m_read1_ptr[0x04 + index] = (UINT32 *)&m_m[0 + index];
	416	m_read1_ptr[0x08 + index] = &m_l[0 + index];
	417	m_read1_ptr[0x0c + index] = &m_l[0 + index];
	418	m_read2_ptr[0x00 + index] = &m_i[4 + index];
	419	m_read2_ptr[0x04 + index] = (UINT32 *)&m_m[4 + index];
	420	m_read2_ptr[0x08 + index] = &m_l[4 + index];
	421	m_read2_ptr[0x0c + index] = &m_l[4 + index];
	422	}
	423
	424	// set up ALU register pointers
	425	m_alu_xregs[0] = &m_core.ax0;
	426	m_alu_xregs[1] = &m_core.ax1;
	427	m_alu_xregs[2] = &m_core.ar;
	428	m_alu_xregs[3] = &m_core.mr.mrx.mr0;
	429	m_alu_xregs[4] = &m_core.mr.mrx.mr1;
	430	m_alu_xregs[5] = &m_core.mr.mrx.mr2;
	431	m_alu_xregs[6] = &m_core.sr.srx.sr0;
	432	m_alu_xregs[7] = &m_core.sr.srx.sr1;
	433	m_alu_yregs[0] = &m_core.ay0;
	434	m_alu_yregs[1] = &m_core.ay1;
	435	m_alu_yregs[2] = &m_core.af;
	436	m_alu_yregs[3] = &m_core.zero;
	437
	438	// set up MAC register pointers
	439	m_mac_xregs[0] = &m_core.mx0;
	440	m_mac_xregs[1] = &m_core.mx1;
	441	m_mac_xregs[2] = &m_core.ar;
	442	m_mac_xregs[3] = &m_core.mr.mrx.mr0;
	443	m_mac_xregs[4] = &m_core.mr.mrx.mr1;
	444	m_mac_xregs[5] = &m_core.mr.mrx.mr2;
	445	m_mac_xregs[6] = &m_core.sr.srx.sr0;
	446	m_mac_xregs[7] = &m_core.sr.srx.sr1;
	447	m_mac_yregs[0] = &m_core.my0;
	448	m_mac_yregs[1] = &m_core.my1;
	449	m_mac_yregs[2] = &m_core.mf;
	450	m_mac_yregs[3] = &m_core.zero;
	451
	452	// set up shift register pointers
	453	m_shift_xregs[0] = &m_core.si;
	454	m_shift_xregs[1] = &m_core.si;
	455	m_shift_xregs[2] = &m_core.ar;
	456	m_shift_xregs[3] = &m_core.mr.mrx.mr0;
	457	m_shift_xregs[4] = &m_core.mr.mrx.mr1;
	458	m_shift_xregs[5] = &m_core.mr.mrx.mr2;
	459	m_shift_xregs[6] = &m_core.sr.srx.sr0;
	460	m_shift_xregs[7] = &m_core.sr.srx.sr1;
312	461	}
313	462
	463	adsp2100_device::adsp2100_device(running_machine &_machine, const adsp2100_device_config &config)
	464	: adsp21xx_device(_machine, config) { }
314	465
	466	adsp2101_device::adsp2101_device(running_machine &_machine, const adsp2101_device_config &config)
	467	: adsp21xx_device(_machine, config) { }
315	468
316		/***************************************************************************
317		MEMORY ACCESSORS
318		***************************************************************************/
	469	adsp2181_device::adsp2181_device(running_machine &_machine, const adsp2181_device_config &config)
	470	: adsp21xx_device(_machine, config) { }
319	471
320		INLINE UINT16 RWORD_DATA(adsp2100_state *adsp, UINT32 addr)
	472
	473	//-------------------------------------------------
	474	// ~adsp21xx_device - destructor
	475	//-------------------------------------------------
	476
	477	adsp21xx_device::~adsp21xx_device()
321	478	{
322		return adsp->data->read_word(addr << 1);
	479	#if ADSP_TRACK_HOTSPOTS
	480	FILE *log = fopen("adsp.hot", "w");
	481	while (1)
	482	{
	483	int maxindex = 0, i;
	484	for (i = 1; i < 0x4000; i++)
	485	if (m_pcbucket[i] > m_pcbucket[maxindex])
	486	maxindex = i;
	487	if (m_pcbucket[maxindex] == 0)
	488	break;
	489	fprintf(log, "PC=%04X (%10d hits)\n", maxindex, pcbucket[maxindex]);
	490	m_pcbucket[maxindex] = 0;
	491	}
	492	fclose(log);
	493	#endif
323	494	}
324	495
325		INLINE void WWORD_DATA(adsp2100_state *adsp, UINT32 addr, UINT16 data)
	496
	497	//-------------------------------------------------
	498	// load_boot_data - load the boot data from an
	499	// 8-bit ROM
	500	//-------------------------------------------------
	501
	502	void adsp21xx_device::load_boot_data(UINT8 srcdata, UINT32 dstdata)
326	503	{
327		adsp->data->write_word(addr << 1, data);
	504	// see how many words we need to copy
	505	int pagelen = (srcdata[3] + 1) * 8;
	506	for (int i = 0; i < pagelen; i++)
	507	{
	508	UINT32 opcode = (srcdata[i4+0] << 16) \| (srcdata[i4+1] << 8) \| srcdata[i*4+2];
	509	dstdata[i] = opcode;
	510	}
328	511	}
329	512
330		INLINE UINT16 RWORD_IO(adsp2100_state *adsp, UINT32 addr)
	513
	514	//-------------------------------------------------
	515	// idma_addr_w - write the IDMA address register
	516	//-------------------------------------------------
	517
	518	void adsp2181_device::idma_addr_w(UINT16 data)
331	519	{
332		return adsp->io->read_word(addr << 1);
	520	m_idma_addr = data;
	521	m_idma_offs = 0;
333	522	}
334	523
335		INLINE void WWORD_IO(adsp2100_state *adsp, UINT32 addr, UINT16 data)
	524
	525	//-------------------------------------------------
	526	// idma_addr_r - read the IDMA address register
	527	//-------------------------------------------------
	528
	529	UINT16 adsp2181_device::idma_addr_r()
336	530	{
337		~~adsp->io->w~~rite~~_wo~~rd(addr ~~<< 1, data)~~;
	531	return m_idma_addr;
338	532	}
339	533
340		INLINE UINT32 RWORD_PGM(adsp2100_state *adsp, UINT32 addr)
	534
	535	//-------------------------------------------------
	536	// idma_data_w - write the IDMA data register
	537	//-------------------------------------------------
	538
	539	void adsp2181_device::idma_data_w(UINT16 data)
341	540	{
342		return adsp->program->read_dword(addr << 2);
	541	// program memory?
	542	if (!(m_idma_addr & 0x4000))
	543	{
	544	// upper 16 bits
	545	if (m_idma_offs == 0)
	546	{
	547	m_idma_cache = data;
	548	m_idma_offs = 1;
	549	}
	550
	551	// lower 8 bits
	552	else
	553	{
	554	program_write(m_idma_addr++ & 0x3fff, (m_idma_cache << 8) \| (data & 0xff));
	555	m_idma_offs = 0;
	556	}
	557	}
	558
	559	// data memory
	560	else
	561	data_write(m_idma_addr++ & 0x3fff, data);
343	562	}
344	563
345		INLINE void WWORD_PGM(adsp2100_state *adsp, UINT32 addr, UINT32 data)
	564
	565	//-------------------------------------------------
	566	// idma_data_r - read the IDMA data register
	567	//-------------------------------------------------
	568
	569	UINT16 adsp2181_device::idma_data_r()
346	570	{
347		adsp->program->write_dword(addr << 2, data & 0xffffff);
	571	UINT16 result = 0xffff;
	572
	573	// program memory?
	574	if (!(m_idma_addr & 0x4000))
	575	{
	576	// upper 16 bits
	577	if (m_idma_offs == 0)
	578	{
	579	result = program_read(m_idma_addr & 0x3fff) >> 8;
	580	m_idma_offs = 1;
	581	}
	582
	583	// lower 8 bits
	584	else
	585	{
	586	result = program_read(m_idma_addr++ & 0x3fff) & 0xff;
	587	m_idma_offs = 0;
	588	}
	589	}
	590
	591	// data memory
	592	else
	593	result = data_read(m_idma_addr++ & 0x3fff);
	594
	595	return result;
348	596	}
349	597
350		#define ROPCODE(a) (a)->direct->read_decrypted_dword((a)->pc << 2)
351	598
	599	//-------------------------------------------------
	600	// device_start - start up the device
	601	//-------------------------------------------------
352	602
353		/***************************************************************************
354		IMPORT CORE UTILITIES
355		***************************************************************************/
	603	void adsp21xx_device::device_start()
	604	{
	605	// get our address spaces
	606	m_program = space(AS_PROGRAM);
	607	m_direct = &m_program->direct();
	608	m_data = space(AS_DATA);
	609	m_io = space(AS_IO);
356	610
357		#include "2100ops.c"
	611	// "core"
	612	state_save_register_device_item(this, 0, m_core.ax0.u);
	613	state_save_register_device_item(this, 0, m_core.ax1.u);
	614	state_save_register_device_item(this, 0, m_core.ay0.u);
	615	state_save_register_device_item(this, 0, m_core.ay1.u);
	616	state_save_register_device_item(this, 0, m_core.ar.u);
	617	state_save_register_device_item(this, 0, m_core.af.u);
	618	state_save_register_device_item(this, 0, m_core.mx0.u);
	619	state_save_register_device_item(this, 0, m_core.mx1.u);
	620	state_save_register_device_item(this, 0, m_core.my0.u);
	621	state_save_register_device_item(this, 0, m_core.my1.u);
	622	state_save_register_device_item(this, 0, m_core.mr.mr);
	623	state_save_register_device_item(this, 0, m_core.mf.u);
	624	state_save_register_device_item(this, 0, m_core.si.u);
	625	state_save_register_device_item(this, 0, m_core.se.u);
	626	state_save_register_device_item(this, 0, m_core.sb.u);
	627	state_save_register_device_item(this, 0, m_core.sr.sr);
	628	state_save_register_device_item(this, 0, m_core.zero.u);
358	629
	630	// "alt"
	631	state_save_register_device_item(this, 0, m_alt.ax0.u);
	632	state_save_register_device_item(this, 0, m_alt.ax1.u);
	633	state_save_register_device_item(this, 0, m_alt.ay0.u);
	634	state_save_register_device_item(this, 0, m_alt.ay1.u);
	635	state_save_register_device_item(this, 0, m_alt.ar.u);
	636	state_save_register_device_item(this, 0, m_alt.af.u);
	637	state_save_register_device_item(this, 0, m_alt.mx0.u);
	638	state_save_register_device_item(this, 0, m_alt.mx1.u);
	639	state_save_register_device_item(this, 0, m_alt.my0.u);
	640	state_save_register_device_item(this, 0, m_alt.my1.u);
	641	state_save_register_device_item(this, 0, m_alt.mr.mr);
	642	state_save_register_device_item(this, 0, m_alt.mf.u);
	643	state_save_register_device_item(this, 0, m_alt.si.u);
	644	state_save_register_device_item(this, 0, m_alt.se.u);
	645	state_save_register_device_item(this, 0, m_alt.sb.u);
	646	state_save_register_device_item(this, 0, m_alt.sr.sr);
	647	state_save_register_device_item(this, 0, m_alt.zero.u);
359	648
	649	state_save_register_device_item_array(this, 0, m_i);
	650	state_save_register_device_item_array(this, 0, m_m);
	651	state_save_register_device_item_array(this, 0, m_l);
	652	state_save_register_device_item_array(this, 0, m_lmask);
	653	state_save_register_device_item_array(this, 0, m_base);
	654	state_save_register_device_item(this, 0, m_px);
360	655
361		/***************************************************************************
362		IRQ HANDLING
363		***************************************************************************/
	656	state_save_register_device_item(this, 0, m_pc);
	657	state_save_register_device_item(this, 0, m_ppc);
	658	state_save_register_device_item(this, 0, m_loop);
	659	state_save_register_device_item(this, 0, m_loop_condition);
	660	state_save_register_device_item(this, 0, m_cntr);
	661	state_save_register_device_item(this, 0, m_astat);
	662	state_save_register_device_item(this, 0, m_sstat);
	663	state_save_register_device_item(this, 0, m_mstat);
	664	state_save_register_device_item(this, 0, m_mstat_prev);
	665	state_save_register_device_item(this, 0, m_astat_clear);
	666	state_save_register_device_item(this, 0, m_idle);
364	667
365		INLINE int adsp2100_generate_irq(adsp2100_state *adsp, int which)
366		{
367		/* skip if masked */
368		if (!(adsp->imask & (1 << which)))
369		return 0;
	668	state_save_register_device_item_array(this, 0, m_loop_stack);
	669	state_save_register_device_item_array(this, 0, m_cntr_stack);
	670	state_save_register_device_item_array(this, 0, m_pc_stack);
	671	state_save_register_device_item_2d_array(this, 0, m_stat_stack);
370	672
371		/* clear the latch */
372		adsp->irq_latch[which] = 0;
	673	state_save_register_device_item(this, 0, m_pc_sp);
	674	state_save_register_device_item(this, 0, m_cntr_sp);
	675	state_save_register_device_item(this, 0, m_stat_sp);
	676	state_save_register_device_item(this, 0, m_loop_sp);
373	677
374		/* push the PC and the status */
375		pc_stack_push(adsp);
376		stat_stack_push(adsp);
	678	state_save_register_device_item(this, 0, m_flagout);
	679	state_save_register_device_item(this, 0, m_flagin);
	680	state_save_register_device_item(this, 0, m_fl0);
	681	state_save_register_device_item(this, 0, m_fl1);
	682	state_save_register_device_item(this, 0, m_fl2);
	683	state_save_register_device_item(this, 0, m_idma_addr);
	684	state_save_register_device_item(this, 0, m_idma_cache);
	685	state_save_register_device_item(this, 0, m_idma_offs);
377	686
378		/* vector to location & stop idling */
379		adsp->pc = which;
380		adsp->idle = 0;
	687	state_save_register_device_item(this, 0, m_imask);
	688	state_save_register_device_item(this, 0, m_icntl);
	689	state_save_register_device_item(this, 0, m_ifc);
	690	state_save_register_device_item_array(this, 0, m_irq_state);
	691	state_save_register_device_item_array(this, 0, m_irq_latch);
381	692
382		/* mask other interrupts based on the nesting bit */
383		if (adsp->icntl & 0x10) adsp->imask &= ~((2 << which) - 1);
384		else adsp->imask &= ~0xf;
	693	// register state with the debugger
	694	state_add(ADSP2100_PC, "PC", m_pc);
	695	state_add(STATE_GENPC, "GENPC", m_pc).noshow();
	696	state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc).noshow();
	697	state_add(STATE_GENFLAGS, "GENFLAGS", m_astat).mask(0xff).noshow().formatstr("%8s");
385	698
386		return 1;
387		}
	699	state_add(ADSP2100_AX0, "AX0", m_core.ax0.u);
	700	state_add(ADSP2100_AX1, "AX1", m_core.ax1.u);
	701	state_add(ADSP2100_AY0, "AY0", m_core.ay0.u);
	702	state_add(ADSP2100_AY1, "AY1", m_core.ay1.u);
	703	state_add(ADSP2100_AR, "AR", m_core.ar.u);
	704	state_add(ADSP2100_AF, "AF", m_core.af.u);
388	705
	706	state_add(ADSP2100_MX0, "MX0", m_core.mx0.u);
	707	state_add(ADSP2100_MX1, "MX1", m_core.mx1.u);
	708	state_add(ADSP2100_MY0, "MY0", m_core.my0.u);
	709	state_add(ADSP2100_MY1, "MY1", m_core.my1.u);
	710	state_add(ADSP2100_MR0, "MR0", m_core.mr.mrx.mr0.u);
	711	state_add(ADSP2100_MR1, "MR1", m_core.mr.mrx.mr1.u);
	712	state_add(ADSP2100_MR2, "MR2", m_core.mr.mrx.mr2.u).signed_mask(0xff);
	713	state_add(ADSP2100_MF, "MF", m_core.mf.u);
389	714
390		INLINE int adsp2101_generate_irq(adsp2100_state *adsp, int which, int indx)
391		{
392		/* skip if masked */
393		if (!(adsp->imask & (0x20 >> indx)))
394		return 0;
	715	state_add(ADSP2100_SI, "SI", m_core.si.u);
	716	state_add(ADSP2100_SE, "SE", m_core.se.u).signed_mask(0xff);
	717	state_add(ADSP2100_SB, "SB", m_core.sb.u).signed_mask(0x1f);
	718	state_add(ADSP2100_SR0, "SR0", m_core.sr.srx.sr0.u);
	719	state_add(ADSP2100_SR1, "SR1", m_core.sr.srx.sr1.u);
395	720
396		/* clear the latch */
397		adsp->irq_latch[which] = 0;
	721	state_add(ADSP2100_AX0_SEC, "AX0_SEC", m_alt.ax0.u);
	722	state_add(ADSP2100_AX1_SEC, "AX1_SEC", m_alt.ax1.u);
	723	state_add(ADSP2100_AY0_SEC, "AY0_SEC", m_alt.ay0.u);
	724	state_add(ADSP2100_AY1_SEC, "AY1_SEC", m_alt.ay1.u);
	725	state_add(ADSP2100_AR_SEC, "AR_SEC", m_alt.ar.u);
	726	state_add(ADSP2100_AF_SEC, "AF_SEC", m_alt.af.u);
398	727
399		/* push the PC and the status */
400		pc_stack_push(adsp);
401		stat_stack_push(adsp);
	728	state_add(ADSP2100_MX0_SEC, "MX0_SEC", m_alt.mx0.u);
	729	state_add(ADSP2100_MX1_SEC, "MX1_SEC", m_alt.mx1.u);
	730	state_add(ADSP2100_MY0_SEC, "MY0_SEC", m_alt.my0.u);
	731	state_add(ADSP2100_MY1_SEC, "MY1_SEC", m_alt.my1.u);
	732	state_add(ADSP2100_MR0_SEC, "MR0_SEC", m_alt.mr.mrx.mr0.u);
	733	state_add(ADSP2100_MR1_SEC, "MR1_SEC", m_alt.mr.mrx.mr1.u);
	734	state_add(ADSP2100_MR2_SEC, "MR2_SEC", m_alt.mr.mrx.mr2.u).signed_mask(0xff);
	735	state_add(ADSP2100_MF_SEC, "MF_SEC", m_alt.mf.u);
402	736
403		/* vector to location & stop idling */
404		adsp->pc = 0x04 + indx * 4;
405		adsp->idle = 0;
	737	state_add(ADSP2100_SI_SEC, "SI_SEC", m_alt.si.u);
	738	state_add(ADSP2100_SE_SEC, "SE_SEC", m_alt.se.u).signed_mask(0xff);
	739	state_add(ADSP2100_SB_SEC, "SB_SEC", m_alt.sb.u).signed_mask(0x1f);
	740	state_add(ADSP2100_SR0_SEC, "SR0_SEC", m_alt.sr.srx.sr0.u);
	741	state_add(ADSP2100_SR1_SEC, "SR1_SEC", m_alt.sr.srx.sr1.u);
406	742
407		/* mask other interrupts based on the nesting bit */
408		if (adsp->icntl & 0x10) adsp->imask &= ~(0x3f >> indx);
409		else adsp->imask &= ~0x3f;
	743	astring tempstring;
	744	for (int ireg = 0; ireg < 8; ireg++)
	745	state_add(ADSP2100_I0 + ireg, tempstring.format("I%d", ireg), m_i[ireg]).mask(0x3fff).callimport();
410	746
411		return 1;
	747	for (int lreg = 0; lreg < 8; lreg++)
	748	state_add(ADSP2100_L0 + lreg, tempstring.format("L%d", lreg), m_l[lreg]).mask(0x3fff).callimport();
	749
	750	for (int mreg = 0; mreg < 8; mreg++)
	751	state_add(ADSP2100_M0 + mreg, tempstring.format("M%d", mreg), m_m[mreg]).signed_mask(0x3fff);
	752
	753	state_add(ADSP2100_PX, "PX", m_px);
	754	state_add(ADSP2100_CNTR, "CNTR", m_cntr).mask(0x3fff);
	755	state_add(ADSP2100_ASTAT, "ASTAT", m_astat).mask(0xff);
	756	state_add(ADSP2100_SSTAT, "SSTAT", m_sstat).mask(0xff);
	757	state_add(ADSP2100_MSTAT, "MSTAT", m_mstat).mask((m_config.m_chip_type == adsp21xx_device_config::CHIP_TYPE_ADSP2100) ? 0x0f : 0x7f).callimport();
	758
	759	state_add(ADSP2100_PCSP, "PCSP", m_pc_sp).mask(0xff);
	760	state_add(STATE_GENSP, "GENSP", m_pc_sp).mask(0xff).noshow();
	761	state_add(ADSP2100_CNTRSP, "CNTRSP", m_cntr_sp).mask(0xf);
	762	state_add(ADSP2100_STATSP, "STATSP", m_stat_sp).mask(0xf);
	763	state_add(ADSP2100_LOOPSP, "LOOPSP", m_loop_sp).mask(0xf);
	764
	765	state_add(ADSP2100_IMASK, "IMASK", m_imask).mask((m_config.m_chip_type == adsp21xx_device_config::CHIP_TYPE_ADSP2100) ? 0x00f : (m_config.m_chip_type == adsp21xx_device_config::CHIP_TYPE_ADSP2181) ? 0x3ff : 0x07f).callimport();
	766	state_add(ADSP2100_ICNTL, "ICNTL", m_icntl).mask(0x1f).callimport();
	767
	768	for (int irqnum = 0; irqnum < 4; irqnum++)
	769	if (irqnum < 4 \|\| m_config.m_chip_type == adsp21xx_device_config::CHIP_TYPE_ADSP2100)
	770	state_add(ADSP2100_IRQSTATE0 + irqnum, tempstring.format("IRQ%d", irqnum), m_irq_state[irqnum]).mask(1).callimport();
	771
	772	state_add(ADSP2100_FLAGIN, "FLAGIN", m_flagin).mask(1);
	773	state_add(ADSP2100_FLAGOUT, "FLAGOUT", m_flagout).mask(1);
	774	state_add(ADSP2100_FL0, "FL0", m_fl0).mask(1);
	775	state_add(ADSP2100_FL1, "FL1", m_fl1).mask(1);
	776	state_add(ADSP2100_FL2, "FL2", m_fl2).mask(1);
	777
	778	// set our instruction counter
	779	m_icountptr = &m_icount;
412	780	}
413	781
414	782
415		INLINE int adsp2181_generate_irq(adsp2100_state *adsp, int which, int indx)
	783	//-------------------------------------------------
	784	// device_reset - reset the device
	785	//-------------------------------------------------
	786
	787	void adsp21xx_device::device_reset()
416	788	{
417		/* skip if masked */
418		if (!(adsp->imask & (0x200 >> indx)))
419		return 0;
	789	// ensure that zero is zero
	790	m_core.zero.u = m_alt.zero.u = 0;
420	791
421		/* clear the latch */
422		adsp->irq_latch[which] = 0;
	792	// recompute the memory registers with their current values
	793	write_reg1(0x08, m_l[0]); write_reg1(0x00, m_i[0]);
	794	write_reg1(0x09, m_l[1]); write_reg1(0x01, m_i[1]);
	795	write_reg1(0x0a, m_l[2]); write_reg1(0x02, m_i[2]);
	796	write_reg1(0x0b, m_l[3]); write_reg1(0x03, m_i[3]);
	797	write_reg2(0x08, m_l[4]); write_reg2(0x00, m_i[4]);
	798	write_reg2(0x09, m_l[5]); write_reg2(0x01, m_i[5]);
	799	write_reg2(0x0a, m_l[6]); write_reg2(0x02, m_i[6]);
	800	write_reg2(0x0b, m_l[7]); write_reg2(0x03, m_i[7]);
423	801
424		/* push the PC and the status */
425		pc_stack_push(adsp);
426		stat_stack_push(adsp);
	802	// reset PC and loops
	803	m_pc = (m_config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2101) ? 0 : 4;
	804	m_ppc = -1;
	805	m_loop = 0xffff;
	806	m_loop_condition = 0;
427	807
428		/* vector to location & stop idling */
429		adsp->pc = 0x04 + indx * 4;
430		adsp->idle = 0;
	808	// reset status registers
	809	m_astat_clear = ~(CFLAG \| VFLAG \| NFLAG \| ZFLAG);
	810	m_mstat = 0;
	811	m_sstat = 0x55;
	812	m_idle = 0;
	813	update_mstat();
431	814
432		/* mask other interrupts based on the nesting bit */
433		if (adsp->icntl & 0x10) adsp->imask &= ~(0x3ff >> indx);
434		else adsp->imask &= ~0x3ff;
	815	// reset stacks
	816	m_pc_sp = 0;
	817	m_cntr_sp = 0;
	818	m_stat_sp = 0;
	819	m_loop_sp = 0;
435	820
436		return 1;
	821	// reset external I/O
	822	m_flagout = 0;
	823	m_flagin = 0;
	824	m_fl0 = 0;
	825	m_fl1 = 0;
	826	m_fl2 = 0;
	827
	828	// reset interrupts
	829	m_imask = 0;
	830	for (int irq = 0; irq < 8; irq++)
	831	m_irq_state[irq] = m_irq_latch[irq] = CLEAR_LINE;
437	832	}
438	833
439	834
440		static void check_irqs(adsp2100_state *adsp)
441		{
442		UINT8 check;
	835	//-------------------------------------------------
	836	// state_import - import state into the device,
	837	// after it has been set
	838	//-------------------------------------------------
443	839
444		if (adsp->chip_type >= CHIP_TYPE_ADSP2181)
	840	void adsp21xx_device::state_import(const device_state_entry &entry)
	841	{
	842	switch (entry.index())
445	843	{
446		/* check IRQ2 */
447		check = (adsp->icntl & 4) ? adsp->irq_latch[ADSP2181_IRQ2] : adsp->irq_state[ADSP2181_IRQ2];
448		if (check && adsp2181_generate_irq(adsp, ADSP2181_IRQ2, 0))
449		return;
	844	case ADSP2100_MSTAT:
	845	update_mstat();
	846	break;
450	847
451		/* check IRQL1 */
452		check = adsp->irq_state[ADSP2181_IRQL1];
453		if (check && adsp2181_generate_irq(adsp, ADSP2181_IRQL1, 1))
454		return;
	848	case ADSP2100_IMASK:
	849	case ADSP2100_ICNTL:
	850	case ADSP2100_IRQSTATE0:
	851	case ADSP2100_IRQSTATE1:
	852	case ADSP2100_IRQSTATE2:
	853	case ADSP2100_IRQSTATE3:
	854	check_irqs();
	855	break;
455	856
456		/* check IRQL2 */
457		check = adsp->irq_state[ADSP2181_IRQL2];
458		if (check && adsp2181_generate_irq(adsp, ADSP2181_IRQL2, 2))
459		return;
	857	case ADSP2100_I0:
	858	case ADSP2100_I1:
	859	case ADSP2100_I2:
	860	case ADSP2100_I3:
	861	case ADSP2100_I4:
	862	case ADSP2100_I5:
	863	case ADSP2100_I6:
	864	case ADSP2100_I7:
	865	update_i(entry.index() - ADSP2100_I0);
	866	break;
460	867
461		/* check SPORT0 transmit */
462		check = adsp->irq_latch[ADSP2181_SPORT0_TX];
463		if (check && adsp2181_generate_irq(adsp, ADSP2181_SPORT0_TX, 3))
464		return;
	868	case ADSP2100_L0:
	869	case ADSP2100_L1:
	870	case ADSP2100_L2:
	871	case ADSP2100_L3:
	872	case ADSP2100_L4:
	873	case ADSP2100_L5:
	874	case ADSP2100_L6:
	875	case ADSP2100_L7:
	876	update_l(entry.index() - ADSP2100_L0);
	877	break;
465	878
466		/* check SPORT0 receive */
467		check = adsp->irq_latch[ADSP2181_SPORT0_RX];
468		if (check && adsp2181_generate_irq(adsp, ADSP2181_SPORT0_RX, 4))
469		return;
	879	default:
	880	fatalerror("CPU_IMPORT_STATE(adsp21xx) called for unexpected value\n");
	881	break;
	882	}
	883	}
470	884
471		/* check IRQE */
472		check = adsp->irq_latch[ADSP2181_IRQE];
473		if (check && adsp2181_generate_irq(adsp, ADSP2181_IRQE, 5))
474		return;
475	885
476		/* check BDMA interrupt */
	886	//-------------------------------------------------
	887	// state_string_export - export state as a string
	888	// for the debugger
	889	//-------------------------------------------------
477	890
478		/* check IRQ1/SPORT1 transmit */
479		check = (adsp->icntl & 2) ? adsp->irq_latch[ADSP2181_IRQ1] : adsp->irq_state[ADSP2181_IRQ1];
480		if (check && adsp2181_generate_irq(adsp, ADSP2181_IRQ1, 7))
481		return;
	891	void adsp21xx_device::state_string_export(const device_state_entry &entry, astring &string)
	892	{
	893	switch (entry.index())
	894	{
	895	case STATE_GENFLAGS:
	896	string.printf("%c%c%c%c%c%c%c%c",
	897	m_astat & 0x80 ? 'X':'.',
	898	m_astat & 0x40 ? 'M':'.',
	899	m_astat & 0x20 ? 'Q':'.',
	900	m_astat & 0x10 ? 'S':'.',
	901	m_astat & 0x08 ? 'C':'.',
	902	m_astat & 0x04 ? 'V':'.',
	903	m_astat & 0x02 ? 'N':'.',
	904	m_astat & 0x01 ? 'Z':'.');
	905	break;
	906	}
	907	}
482	908
483		/* check IRQ0/SPORT1 receive */
484		check = (adsp->icntl & 1) ? adsp->irq_latch[ADSP2181_IRQ0] : adsp->irq_state[ADSP2181_IRQ0];
485		if (check && adsp2181_generate_irq(adsp, ADSP2181_IRQ0, 8))
486		return;
487	909
488		/* check timer */
489		check = adsp->irq_latch[ADSP2181_TIMER];
490		if (check && adsp2181_generate_irq(adsp, ADSP2181_TIMER, 9))
491		return;
492		}
493		else if (adsp->chip_type >= CHIP_TYPE_ADSP2101)
494		{
495		/* check IRQ2 */
496		check = (adsp->icntl & 4) ? adsp->irq_latch[ADSP2101_IRQ2] : adsp->irq_state[ADSP2101_IRQ2];
497		if (check && adsp2101_generate_irq(adsp, ADSP2101_IRQ2, 0))
498		return;
	910	//-------------------------------------------------
	911	// disasm_disassemble - call the disassembly
	912	// helper function
	913	//-------------------------------------------------
499	914
500		/* check SPORT0 transmit */
501		check = adsp->irq_latch[ADSP2101_SPORT0_TX];
502		if (check && adsp2101_generate_irq(adsp, ADSP2101_SPORT0_TX, 1))
503		return;
	915	offs_t adsp21xx_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
	916	{
	917	extern CPU_DISASSEMBLE( adsp21xx );
	918	return CPU_DISASSEMBLE_NAME(adsp21xx)(NULL, buffer, pc, oprom, opram, 0);
	919	}
504	920
505		/* check SPORT0 receive */
506		check = adsp->irq_latch[ADSP2101_SPORT0_RX];
507		if (check && adsp2101_generate_irq(adsp, ADSP2101_SPORT0_RX, 2))
508		return;
509	921
510		/* check IRQ1/SPORT1 transmit */
511		check = (adsp->icntl & 2) ? adsp->irq_latch[ADSP2101_IRQ1] : adsp->irq_state[ADSP2101_IRQ1];
512		if (check && adsp2101_generate_irq(adsp, ADSP2101_IRQ1, 3))
513		return;
514	922
515		/* check IRQ0/SPORT1 receive */
516		check = (adsp->icntl & 1) ? adsp->irq_latch[ADSP2101_IRQ0] : adsp->irq_state[ADSP2101_IRQ0];
517		if (check && adsp2101_generate_irq(adsp, ADSP2101_IRQ0, 4))
518		return;
519	923
520		/* check timer */
521		check = adsp->irq_latch[ADSP2101_TIMER];
522		if (check && adsp2101_generate_irq(adsp, ADSP2101_TIMER, 5))
523		return;
524		}
525		else
526		{
527		/* check IRQ3 */
528		check = (adsp->icntl & 8) ? adsp->irq_latch[ADSP2100_IRQ3] : adsp->irq_state[ADSP2100_IRQ3];
529		if (check && adsp2100_generate_irq(adsp, ADSP2100_IRQ3))
530		return;
	924	/***************************************************************************
	925	MEMORY ACCESSORS
	926	***************************************************************************/
531	927
532		/* check IRQ2 */
533		check = (adsp->icntl & 4) ? adsp->irq_latch[ADSP2100_IRQ2] : adsp->irq_state[ADSP2100_IRQ2];
534		if (check && adsp2100_generate_irq(adsp, ADSP2100_IRQ2))
535		return;
	928	inline UINT16 adsp21xx_device::data_read(UINT32 addr)
	929	{
	930	return m_data->read_word(addr << 1);
	931	}
536	932
537		/* check IRQ1 */
538		check = (adsp->icntl & 2) ? adsp->irq_latch[ADSP2100_IRQ1] : adsp->irq_state[ADSP2100_IRQ1];
539		if (check && adsp2100_generate_irq(adsp, ADSP2100_IRQ1))
540		return;
	933	inline void adsp21xx_device::data_write(UINT32 addr, UINT16 data)
	934	{
	935	m_data->write_word(addr << 1, data);
	936	}
541	937
542		/* check IRQ0 */
543		check = (adsp->icntl & 1) ? adsp->irq_latch[ADSP2100_IRQ0] : adsp->irq_state[ADSP2100_IRQ0];
544		if (check && adsp2100_generate_irq(adsp, ADSP2100_IRQ0))
545		return;
546		}
	938	inline UINT16 adsp21xx_device::io_read(UINT32 addr)
	939	{
	940	return m_io->read_word(addr << 1);
547	941	}
548	942
	943	inline void adsp21xx_device::io_write(UINT32 addr, UINT16 data)
	944	{
	945	m_io->write_word(addr << 1, data);
	946	}
549	947
550		~~stat~~i~~c void set_irq_~~line(adsp2100_state *ad~~sp,~~ ~~int irqline, int st~~ate)
	948	inline UINT32 adsp21xx_device::program_read(UINT32 addr)
551	949	{
552		/* update the latched state */
553		if (state != CLEAR_LINE && adsp->irq_state[irqline] == CLEAR_LINE)
554		adsp->irq_latch[irqline] = 1;
	950	return m_program->read_dword(addr << 2);
	951	}
555	952
556		/* update the absolute state */
557		adsp->irq_state[irqline] = state;
	953	inline void adsp21xx_device::program_write(UINT32 addr, UINT32 data)
	954	{
	955	m_program->write_dword(addr << 2, data & 0xffffff);
558	956	}
559	957
	958	inline UINT32 adsp21xx_device::opcode_read()
	959	{
	960	return m_direct->read_decrypted_dword(m_pc << 2);
	961	}
560	962
561	963
562	964	/***************************************************************************
563		INITIALIZATI~~ON AND~~ S~~HUTDOWN~~
	965	IMPORT CORE UTILITIES
564	966	***************************************************************************/
565	967
566		static adsp2100_state adsp21xx_init(legacy_cpu_device device, device_irq_callback irqcallback, int chiptype)
	968	#include "2100ops.c"
	969
	970
	971
	972	/***************************************************************************
	973	IRQ HANDLING
	974	***************************************************************************/
	975
	976	bool adsp2100_device::generate_irq(int which, int indx)
567	977	{
568		const adsp21xx_config config = (const adsp21xx_config )device->baseconfig().static_config();
569		adsp2100_state *adsp = get_safe_token(device);
	978	// skip if masked
	979	if (!(m_imask & (1 << which)))
	980	return false;
570	981
571		/* create the tables */
572		if (!create_tables())
573		fatalerror("creating adsp2100 tables failed");
	982	// clear the latch
	983	m_irq_latch[which] = 0;
574	984
575		/* set the IRQ callback */
576		adsp->chip_type = chiptype;
577		adsp->irq_callback = irqcallback;
	985	// push the PC and the status
	986	pc_stack_push();
	987	stat_stack_push();
578	988
579		/* fetch device parameters */
580		adsp->device = device;
581		adsp->program = device->space(AS_PROGRAM);
582		adsp->direct = &adsp->program->direct();
583		adsp->data = device->space(AS_DATA);
584		adsp->io = device->space(AS_IO);
	989	// vector to location & stop idling
	990	m_pc = indx;
	991	m_idle = 0;
585	992
586		/* copy function pointers from the config */
587		if (config != NULL)
588		{
589		adsp->sport_rx_callback = config->rx;
590		adsp->sport_tx_callback = config->tx;
591		adsp->timer_fired = config->timer;
592		}
	993	// mask other interrupts based on the nesting bit
	994	if (m_icntl & 0x10) m_imask &= ~((2 << which) - 1);
	995	else m_imask &= ~0xf;
593	996
594		/* set up ALU register pointers */
595		adsp->alu_xregs[0] = &adsp->core.ax0;
596		adsp->alu_xregs[1] = &adsp->core.ax1;
597		adsp->alu_xregs[2] = &adsp->core.ar;
598		adsp->alu_xregs[3] = &adsp->core.mr.mrx.mr0;
599		adsp->alu_xregs[4] = &adsp->core.mr.mrx.mr1;
600		adsp->alu_xregs[5] = &adsp->core.mr.mrx.mr2;
601		adsp->alu_xregs[6] = &adsp->core.sr.srx.sr0;
602		adsp->alu_xregs[7] = &adsp->core.sr.srx.sr1;
603		adsp->alu_yregs[0] = &adsp->core.ay0;
604		adsp->alu_yregs[1] = &adsp->core.ay1;
605		adsp->alu_yregs[2] = &adsp->core.af;
606		adsp->alu_yregs[3] = &adsp->core.zero;
	997	return true;
	998	}
607	999
608		/* set up MAC register pointers */
609		adsp->mac_xregs[0] = &adsp->core.mx0;
610		adsp->mac_xregs[1] = &adsp->core.mx1;
611		adsp->mac_xregs[2] = &adsp->core.ar;
612		adsp->mac_xregs[3] = &adsp->core.mr.mrx.mr0;
613		adsp->mac_xregs[4] = &adsp->core.mr.mrx.mr1;
614		adsp->mac_xregs[5] = &adsp->core.mr.mrx.mr2;
615		adsp->mac_xregs[6] = &adsp->core.sr.srx.sr0;
616		adsp->mac_xregs[7] = &adsp->core.sr.srx.sr1;
617		adsp->mac_yregs[0] = &adsp->core.my0;
618		adsp->mac_yregs[1] = &adsp->core.my1;
619		adsp->mac_yregs[2] = &adsp->core.mf;
620		adsp->mac_yregs[3] = &adsp->core.zero;
621	1000
622		/* set up shift register pointers */
623		adsp->shift_xregs[0] = &adsp->core.si;
624		adsp->shift_xregs[1] = &adsp->core.si;
625		adsp->shift_xregs[2] = &adsp->core.ar;
626		adsp->shift_xregs[3] = &adsp->core.mr.mrx.mr0;
627		adsp->shift_xregs[4] = &adsp->core.mr.mrx.mr1;
628		adsp->shift_xregs[5] = &adsp->core.mr.mrx.mr2;
629		adsp->shift_xregs[6] = &adsp->core.sr.srx.sr0;
630		adsp->shift_xregs[7] = &adsp->core.sr.srx.sr1;
	1001	bool adsp2101_device::generate_irq(int which, int indx)
	1002	{
	1003	// skip if masked
	1004	if (!(m_imask & (0x20 >> indx)))
	1005	return false;
631	1006
632		/* "core" */
633		state_save_register_device_item(device, 0, adsp->core.ax0.u);
634		state_save_register_device_item(device, 0, adsp->core.ax1.u);
635		state_save_register_device_item(device, 0, adsp->core.ay0.u);
636		state_save_register_device_item(device, 0, adsp->core.ay1.u);
637		state_save_register_device_item(device, 0, adsp->core.ar.u);
638		state_save_register_device_item(device, 0, adsp->core.af.u);
639		state_save_register_device_item(device, 0, adsp->core.mx0.u);
640		state_save_register_device_item(device, 0, adsp->core.mx1.u);
641		state_save_register_device_item(device, 0, adsp->core.my0.u);
642		state_save_register_device_item(device, 0, adsp->core.my1.u);
643		state_save_register_device_item(device, 0, adsp->core.mr.mr);
644		state_save_register_device_item(device, 0, adsp->core.mf.u);
645		state_save_register_device_item(device, 0, adsp->core.si.u);
646		state_save_register_device_item(device, 0, adsp->core.se.u);
647		state_save_register_device_item(device, 0, adsp->core.sb.u);
648		state_save_register_device_item(device, 0, adsp->core.sr.sr);
649		state_save_register_device_item(device, 0, adsp->core.zero.u);
	1007	// clear the latch
	1008	m_irq_latch[which] = 0;
650	1009
651		/* "alt" */
652		state_save_register_device_item(device, 0, adsp->alt.ax0.u);
653		state_save_register_device_item(device, 0, adsp->alt.ax1.u);
654		state_save_register_device_item(device, 0, adsp->alt.ay0.u);
655		state_save_register_device_item(device, 0, adsp->alt.ay1.u);
656		state_save_register_device_item(device, 0, adsp->alt.ar.u);
657		state_save_register_device_item(device, 0, adsp->alt.af.u);
658		state_save_register_device_item(device, 0, adsp->alt.mx0.u);
659		state_save_register_device_item(device, 0, adsp->alt.mx1.u);
660		state_save_register_device_item(device, 0, adsp->alt.my0.u);
661		state_save_register_device_item(device, 0, adsp->alt.my1.u);
662		state_save_register_device_item(device, 0, adsp->alt.mr.mr);
663		state_save_register_device_item(device, 0, adsp->alt.mf.u);
664		state_save_register_device_item(device, 0, adsp->alt.si.u);
665		state_save_register_device_item(device, 0, adsp->alt.se.u);
666		state_save_register_device_item(device, 0, adsp->alt.sb.u);
667		state_save_register_device_item(device, 0, adsp->alt.sr.sr);
668		state_save_register_device_item(device, 0, adsp->alt.zero.u);
	1010	// push the PC and the status
	1011	pc_stack_push();
	1012	stat_stack_push();
669	1013
670		state_save_register_device_item_array(device, 0, adsp->i);
671		state_save_register_device_item_array(device, 0, adsp->m);
672		state_save_register_device_item_array(device, 0, adsp->l);
673		state_save_register_device_item_array(device, 0, adsp->lmask);
674		state_save_register_device_item_array(device, 0, adsp->base);
675		state_save_register_device_item(device, 0, adsp->px);
	1014	// vector to location & stop idling
	1015	m_pc = 0x04 + indx * 4;
	1016	m_idle = 0;
676	1017
677		state_save_register_device_item(device, 0, adsp->pc);
678		state_save_register_device_item(device, 0, adsp->ppc);
679		state_save_register_device_item(device, 0, adsp->loop);
680		state_save_register_device_item(device, 0, adsp->loop_condition);
681		state_save_register_device_item(device, 0, adsp->cntr);
682		state_save_register_device_item(device, 0, adsp->astat);
683		state_save_register_device_item(device, 0, adsp->sstat);
684		state_save_register_device_item(device, 0, adsp->mstat);
685		state_save_register_device_item(device, 0, adsp->mstat_prev);
686		state_save_register_device_item(device, 0, adsp->astat_clear);
687		state_save_register_device_item(device, 0, adsp->idle);
	1018	// mask other interrupts based on the nesting bit
	1019	if (m_icntl & 0x10) m_imask &= ~(0x3f >> indx);
	1020	else m_imask &= ~0x3f;
688	1021
689		state_save_register_device_item_array(device, 0, adsp->loop_stack);
690		state_save_register_device_item_array(device, 0, adsp->cntr_stack);
691		state_save_register_device_item_array(device, 0, adsp->pc_stack);
692		state_save_register_device_item_2d_array(device, 0, adsp->stat_stack);
	1022	return true;
	1023	}
693	1024
694		state_save_register_device_item(device, 0, adsp->pc_sp);
695		state_save_register_device_item(device, 0, adsp->cntr_sp);
696		state_save_register_device_item(device, 0, adsp->stat_sp);
697		state_save_register_device_item(device, 0, adsp->loop_sp);
698	1025
699		state_save_register_device_item(device, 0, adsp->flagout);
700		state_save_register_device_item(device, 0, adsp->flagin);
701		state_save_register_device_item(device, 0, adsp->fl0);
702		state_save_register_device_item(device, 0, adsp->fl1);
703		state_save_register_device_item(device, 0, adsp->fl2);
704		state_save_register_device_item(device, 0, adsp->idma_addr);
705		state_save_register_device_item(device, 0, adsp->idma_cache);
706		state_save_register_device_item(device, 0, adsp->idma_offs);
	1026	bool adsp2181_device::generate_irq(int which, int indx)
	1027	{
	1028	// skip if masked
	1029	if (!(m_imask & (0x200 >> indx)))
	1030	return false;
707	1031
708		state_save_register_device_item(device, 0, adsp->imask);
709		state_save_register_device_item(device, 0, adsp->icntl);
710		state_save_register_device_item(device, 0, adsp->ifc);
711		state_save_register_device_item_array(device, 0, adsp->irq_state);
712		state_save_register_device_item_array(device, 0, adsp->irq_latch);
	1032	// clear the latch
	1033	m_irq_latch[which] = 0;
713	1034
714		// eventually this will be built-in
715		device_state_interface *state;
716		device->interface(state);
717		state->state_add(ADSP2100_PC, "PC", adsp->pc);
718		state->state_add(STATE_GENPC, "GENPC", adsp->pc).noshow();
719		state->state_add(STATE_GENPCBASE, "GENPCBASE", adsp->ppc).noshow();
720		state->state_add(STATE_GENFLAGS, "GENFLAGS", adsp->astat).mask(0xff).noshow().formatstr("%8s");
	1035	// push the PC and the status
	1036	pc_stack_push();
	1037	stat_stack_push();
721	1038
722		state->state_add(ADSP2100_AX0, "AX0", adsp->core.ax0.u);
723		state->state_add(ADSP2100_AX1, "AX1", adsp->core.ax1.u);
724		state->state_add(ADSP2100_AY0, "AY0", adsp->core.ay0.u);
725		state->state_add(ADSP2100_AY1, "AY1", adsp->core.ay1.u);
726		state->state_add(ADSP2100_AR, "AR", adsp->core.ar.u);
727		state->state_add(ADSP2100_AF, "AF", adsp->core.af.u);
	1039	// vector to location & stop idling
	1040	m_pc = 0x04 + indx * 4;
	1041	m_idle = 0;
728	1042
729		state->state_add(ADSP2100_MX0, "MX0", adsp->core.mx0.u);
730		state->state_add(ADSP2100_MX1, "MX1", adsp->core.mx1.u);
731		state->state_add(ADSP2100_MY0, "MY0", adsp->core.my0.u);
732		state->state_add(ADSP2100_MY1, "MY1", adsp->core.my1.u);
733		state->state_add(ADSP2100_MR0, "MR0", adsp->core.mr.mrx.mr0.u);
734		state->state_add(ADSP2100_MR1, "MR1", adsp->core.mr.mrx.mr1.u);
735		state->state_add(ADSP2100_MR2, "MR2", adsp->core.mr.mrx.mr2.u).signed_mask(0xff);
736		state->state_add(ADSP2100_MF, "MF", adsp->core.mf.u);
	1043	// mask other interrupts based on the nesting bit
	1044	if (m_icntl & 0x10) m_imask &= ~(0x3ff >> indx);
	1045	else m_imask &= ~0x3ff;
737	1046
738		state->state_add(ADSP2100_SI, "SI", adsp->core.si.u);
739		state->state_add(ADSP2100_SE, "SE", adsp->core.se.u).signed_mask(0xff);
740		state->state_add(ADSP2100_SB, "SB", adsp->core.sb.u).signed_mask(0x1f);
741		state->state_add(ADSP2100_SR0, "SR0", adsp->core.sr.srx.sr0.u);
742		state->state_add(ADSP2100_SR1, "SR1", adsp->core.sr.srx.sr1.u);
	1047	return true;
	1048	}
743	1049
744		state->state_add(ADSP2100_AX0_SEC, "AX0_SEC", adsp->alt.ax0.u);
745		state->state_add(ADSP2100_AX1_SEC, "AX1_SEC", adsp->alt.ax1.u);
746		state->state_add(ADSP2100_AY0_SEC, "AY0_SEC", adsp->alt.ay0.u);
747		state->state_add(ADSP2100_AY1_SEC, "AY1_SEC", adsp->alt.ay1.u);
748		state->state_add(ADSP2100_AR_SEC, "AR_SEC", adsp->alt.ar.u);
749		state->state_add(ADSP2100_AF_SEC, "AF_SEC", adsp->alt.af.u);
750	1050
751		state->state_add(ADSP2100_MX0_SEC, "MX0_SEC", adsp->alt.mx0.u);
752		state->state_add(ADSP2100_MX1_SEC, "MX1_SEC", adsp->alt.mx1.u);
753		state->state_add(ADSP2100_MY0_SEC, "MY0_SEC", adsp->alt.my0.u);
754		state->state_add(ADSP2100_MY1_SEC, "MY1_SEC", adsp->alt.my1.u);
755		state->state_add(ADSP2100_MR0_SEC, "MR0_SEC", adsp->alt.mr.mrx.mr0.u);
756		state->state_add(ADSP2100_MR1_SEC, "MR1_SEC", adsp->alt.mr.mrx.mr1.u);
757		state->state_add(ADSP2100_MR2_SEC, "MR2_SEC", adsp->alt.mr.mrx.mr2.u).signed_mask(0xff);
758		state->state_add(ADSP2100_MF_SEC, "MF_SEC", adsp->alt.mf.u);
	1051	void adsp2100_device::check_irqs()
	1052	{
	1053	UINT8 check;
759	1054
760		state->state_add(ADSP2100_SI_SEC, "SI_SEC", adsp->alt.si.u);
761		state->state_add(ADSP2100_SE_SEC, "SE_SEC", adsp->alt.se.u).signed_mask(0xff);
762		state->state_add(ADSP2100_SB_SEC, "SB_SEC", adsp->alt.sb.u).signed_mask(0x1f);
763		state->state_add(ADSP2100_SR0_SEC, "SR0_SEC", adsp->alt.sr.srx.sr0.u);
764		state->state_add(ADSP2100_SR1_SEC, "SR1_SEC", adsp->alt.sr.srx.sr1.u);
	1055	// check IRQ3
	1056	check = (m_icntl & 8) ? m_irq_latch[ADSP2100_IRQ3] : m_irq_state[ADSP2100_IRQ3];
	1057	if (check && generate_irq(ADSP2100_IRQ3, 3))
	1058	return;
765	1059
766		astring tempstring;
767		for (int ireg = 0; ireg < 8; ireg++)
768		state->state_add(ADSP2100_I0 + ireg, tempstring.format("I%d", ireg), adsp->i[ireg]).mask(0x3fff).callimport();
	1060	// check IRQ2
	1061	check = (m_icntl & 4) ? m_irq_latch[ADSP2100_IRQ2] : m_irq_state[ADSP2100_IRQ2];
	1062	if (check && generate_irq(ADSP2100_IRQ2, 2))
	1063	return;
769	1064
770		for (int lreg = 0; lreg < 8; lreg++)
771		state->state_add(ADSP2100_L0 + lreg, tempstring.format("L%d", lreg), adsp->l[lreg]).mask(0x3fff).callimport();
	1065	// check IRQ1
	1066	check = (m_icntl & 2) ? m_irq_latch[ADSP2100_IRQ1] : m_irq_state[ADSP2100_IRQ1];
	1067	if (check && generate_irq(ADSP2100_IRQ1, 1))
	1068	return;
772	1069
773		for (int mreg = 0; mreg < 8; mreg++)
774		state->state_add(ADSP2100_M0 + mreg, tempstring.format("M%d", mreg), adsp->m[mreg]).signed_mask(0x3fff);
	1070	// check IRQ0
	1071	check = (m_icntl & 1) ? m_irq_latch[ADSP2100_IRQ0] : m_irq_state[ADSP2100_IRQ0];
	1072	if (check && generate_irq(ADSP2100_IRQ0, 0))
	1073	return;
	1074	}
775	1075
776		state->state_add(ADSP2100_PX, "PX", adsp->px);
777		state->state_add(ADSP2100_CNTR, "CNTR", adsp->cntr).mask(0x3fff);
778		state->state_add(ADSP2100_ASTAT, "ASTAT", adsp->astat).mask(0xff);
779		state->state_add(ADSP2100_SSTAT, "SSTAT", adsp->sstat).mask(0xff);
780		state->state_add(ADSP2100_MSTAT, "MSTAT", adsp->mstat).mask((chiptype == CHIP_TYPE_ADSP2100) ? 0x0f : 0x7f).callimport();
781	1076
782		state->state_add(ADSP2100_PCSP, "PCSP", adsp->pc_sp).mask(0xff);
783		state->state_add(STATE_GENSP, "GENSP", adsp->pc_sp).mask(0xff).noshow();
784		state->state_add(ADSP2100_CNTRSP, "CNTRSP", adsp->cntr_sp).mask(0xf);
785		state->state_add(ADSP2100_STATSP, "STATSP", adsp->stat_sp).mask(0xf);
786		state->state_add(ADSP2100_LOOPSP, "LOOPSP", adsp->loop_sp).mask(0xf);
	1077	void adsp2101_device::check_irqs()
	1078	{
	1079	UINT8 check;
787	1080
788		state->state_add(ADSP2100_IMASK, "IMASK", adsp->imask).mask((chiptype == CHIP_TYPE_ADSP2100) ? 0x00f : (chiptype == CHIP_TYPE_ADSP2181) ? 0x3ff : 0x07f).callimport();
789		state->state_add(ADSP2100_ICNTL, "ICNTL", adsp->icntl).mask(0x1f).callimport();
	1081	// check IRQ2
	1082	check = (m_icntl & 4) ? m_irq_latch[ADSP2101_IRQ2] : m_irq_state[ADSP2101_IRQ2];
	1083	if (check && generate_irq(ADSP2101_IRQ2, 0))
	1084	return;
790	1085
791		for (int irqnum = 0; irqnum < 4; irqnum++)
792		if (irqnum < 4 \|\| chiptype == CHIP_TYPE_ADSP2100)
793		state->state_add(ADSP2100_IRQSTATE0 + irqnum, tempstring.format("IRQ%d", irqnum), adsp->irq_state[irqnum]).mask(1).callimport();
	1086	// check SPORT0 transmit
	1087	check = m_irq_latch[ADSP2101_SPORT0_TX];
	1088	if (check && generate_irq(ADSP2101_SPORT0_TX, 1))
	1089	return;
794	1090
795		state->state_add(ADSP2100_FLAGIN, "FLAGIN", adsp->flagin).mask(1);
796		state->state_add(ADSP2100_FLAGOUT, "FLAGOUT", adsp->flagout).mask(1);
797		state->state_add(ADSP2100_FL0, "FL0", adsp->fl0).mask(1);
798		state->state_add(ADSP2100_FL1, "FL1", adsp->fl1).mask(1);
799		state->state_add(ADSP2100_FL2, "FL2", adsp->fl2).mask(1);
	1091	// check SPORT0 receive
	1092	check = m_irq_latch[ADSP2101_SPORT0_RX];
	1093	if (check && generate_irq(ADSP2101_SPORT0_RX, 2))
	1094	return;
800	1095
801		return adsp;
	1096	// check IRQ1/SPORT1 transmit
	1097	check = (m_icntl & 2) ? m_irq_latch[ADSP2101_IRQ1] : m_irq_state[ADSP2101_IRQ1];
	1098	if (check && generate_irq(ADSP2101_IRQ1, 3))
	1099	return;
	1100
	1101	// check IRQ0/SPORT1 receive
	1102	check = (m_icntl & 1) ? m_irq_latch[ADSP2101_IRQ0] : m_irq_state[ADSP2101_IRQ0];
	1103	if (check && generate_irq(ADSP2101_IRQ0, 4))
	1104	return;
	1105
	1106	// check timer
	1107	check = m_irq_latch[ADSP2101_TIMER];
	1108	if (check && generate_irq(ADSP2101_TIMER, 5))
	1109	return;
802	1110	}
803	1111
804	1112
805		~~stat~~ic ~~CPU_RESET(~~ adsp21xx )
	1113	void adsp2181_device::check_irqs()
806	1114	{
807		adsp2100_state *adsp = get_safe_token(device);
808		int irq;
	1115	UINT8 check;
809	1116
810		/* ensure that zero is zero */
811		adsp->core.zero.u = adsp->alt.zero.u = 0;
	1117	// check IRQ2
	1118	check = (m_icntl & 4) ? m_irq_latch[ADSP2181_IRQ2] : m_irq_state[ADSP2181_IRQ2];
	1119	if (check && generate_irq(ADSP2181_IRQ2, 0))
	1120	return;
812	1121
813		/* recompute the memory registers with their current values */
814		wr_l0(adsp, adsp->l[0]); wr_i0(adsp, adsp->i[0]);
815		wr_l1(adsp, adsp->l[1]); wr_i1(adsp, adsp->i[1]);
816		wr_l2(adsp, adsp->l[2]); wr_i2(adsp, adsp->i[2]);
817		wr_l3(adsp, adsp->l[3]); wr_i3(adsp, adsp->i[3]);
818		wr_l4(adsp, adsp->l[4]); wr_i4(adsp, adsp->i[4]);
819		wr_l5(adsp, adsp->l[5]); wr_i5(adsp, adsp->i[5]);
820		wr_l6(adsp, adsp->l[6]); wr_i6(adsp, adsp->i[6]);
821		wr_l7(adsp, adsp->l[7]); wr_i7(adsp, adsp->i[7]);
	1122	// check IRQL1
	1123	check = m_irq_state[ADSP2181_IRQL1];
	1124	if (check && generate_irq(ADSP2181_IRQL1, 1))
	1125	return;
822	1126
823		/* reset PC and loops */
824		switch (adsp->chip_type)
825		{
826		case CHIP_TYPE_ADSP2100:
827		adsp->pc = 4;
828		break;
	1127	// check IRQL2
	1128	check = m_irq_state[ADSP2181_IRQL2];
	1129	if (check && generate_irq(ADSP2181_IRQL2, 2))
	1130	return;
829	1131
830		case CHIP_TYPE_ADSP2101:
831		case CHIP_TYPE_ADSP2104:
832		case CHIP_TYPE_ADSP2105:
833		case CHIP_TYPE_ADSP2115:
834		case CHIP_TYPE_ADSP2181:
835		adsp->pc = 0;
836		break;
	1132	// check SPORT0 transmit
	1133	check = m_irq_latch[ADSP2181_SPORT0_TX];
	1134	if (check && generate_irq(ADSP2181_SPORT0_TX, 3))
	1135	return;
837	1136
838		default:
839		logerror( "ADSP2100 core: Unknown chip type!. Defaulting to adsp->\n" );
840		adsp->pc = 4;
841		adsp->chip_type = CHIP_TYPE_ADSP2100;
842		break;
843		}
	1137	// check SPORT0 receive
	1138	check = m_irq_latch[ADSP2181_SPORT0_RX];
	1139	if (check && generate_irq(ADSP2181_SPORT0_RX, 4))
	1140	return;
844	1141
845		adsp->ppc = -1;
846		adsp->loop = 0xffff;
847		adsp->loop_condition = 0;
	1142	// check IRQE
	1143	check = m_irq_latch[ADSP2181_IRQE];
	1144	if (check && generate_irq(ADSP2181_IRQE, 5))
	1145	return;
848	1146
849		/* reset status registers */
850		adsp->astat_clear = ~(CFLAG \| VFLAG \| NFLAG \| ZFLAG);
851		adsp->mstat = 0;
852		adsp->sstat = 0x55;
853		adsp->idle = 0;
854		update_mstat(adsp);
	1147	// check BDMA interrupt
855	1148
856		/* reset stacks */
857		adsp->pc_sp = 0;
858		adsp->cntr_sp = 0;
859		adsp->stat_sp = 0;
860		adsp->loop_sp = 0;
	1149	// check IRQ1/SPORT1 transmit
	1150	check = (m_icntl & 2) ? m_irq_latch[ADSP2181_IRQ1] : m_irq_state[ADSP2181_IRQ1];
	1151	if (check && generate_irq(ADSP2181_IRQ1, 7))
	1152	return;
861	1153
862		/* reset external I/O */
863		adsp->flagout = 0;
864		adsp->flagin = 0;
865		adsp->fl0 = 0;
866		adsp->fl1 = 0;
867		adsp->fl2 = 0;
	1154	// check IRQ0/SPORT1 receive
	1155	check = (m_icntl & 1) ? m_irq_latch[ADSP2181_IRQ0] : m_irq_state[ADSP2181_IRQ0];
	1156	if (check && generate_irq(ADSP2181_IRQ0, 8))
	1157	return;
868	1158
869		/* reset interrupts */
870		adsp->imask = 0;
871		for (irq = 0; irq < 8; irq++)
872		adsp->irq_state[irq] = adsp->irq_latch[irq] = CLEAR_LINE;
	1159	// check timer
	1160	check = m_irq_latch[ADSP2181_TIMER];
	1161	if (check && generate_irq(ADSP2181_TIMER, 9))
	1162	return;
873	1163	}
874	1164
875	1165
876		static int create_tables(void)
877		{
878		int i;
879	1166
880		/* allocate the tables */
881		if (!reverse_table)
882		reverse_table = global_alloc_array(UINT16, 0x4000);
883		if (!mask_table)
884		mask_table = global_alloc_array(UINT16, 0x4000);
885		if (!condition_table)
886		condition_table = global_alloc_array(UINT8, 0x1000);
	1167	/***************************************************************************
	1168	INITIALIZATION AND SHUTDOWN
	1169	***************************************************************************/
887	1170
888		/* handle errors */
889		if (reverse_table == NULL \|\| mask_table == NULL \|\| condition_table == NULL)
890		return 0;
891
892		/* initialize the bit reversing table */
893		for (i = 0; i < 0x4000; i++)
	1171	void adsp21xx_device::create_tables()
	1172	{
	1173	// initialize the bit reversing table
	1174	for (int i = 0; i < 0x4000; i++)
894	1175	{
895	1176	UINT16 data = 0;
896	1177
r9081	r9082
909	1190	data \|= (i << 11) & 0x1000;
910	1191	data \|= (i << 13) & 0x2000;
911	1192
912		reverse_table[i] = data;
	1193	m_reverse_table[i] = data;
913	1194	}
914	1195
915		/* initialize the mask table */
916		for (i = 0; i < 0x4000; i++)
	1196	// initialize the mask table
	1197	for (int i = 0; i < 0x4000; i++)
917	1198	{
918		if (i > 0x2000) mask_table[i] = 0x0000;
919		else if (i > 0x1000) mask_table[i] = 0x2000;
920		else if (i > 0x0800) mask_table[i] = 0x3000;
921		else if (i > 0x0400) mask_table[i] = 0x3800;
922		else if (i > 0x0200) mask_table[i] = 0x3c00;
923		else if (i > 0x0100) mask_table[i] = 0x3e00;
924		else if (i > 0x0080) mask_table[i] = 0x3f00;
925		else if (i > 0x0040) mask_table[i] = 0x3f80;
926		else if (i > 0x0020) mask_table[i] = 0x3fc0;
927		else if (i > 0x0010) mask_table[i] = 0x3fe0;
928		else if (i > 0x0008) mask_table[i] = 0x3ff0;
929		else if (i > 0x0004) mask_table[i] = 0x3ff8;
930		else if (i > 0x0002) mask_table[i] = 0x3ffc;
931		else if (i > 0x0001) mask_table[i] = 0x3ffe;
932		else mask_table[i] = 0x3fff;
	1199	if (i > 0x2000) m_mask_table[i] = 0x0000;
	1200	else if (i > 0x1000) m_mask_table[i] = 0x2000;
	1201	else if (i > 0x0800) m_mask_table[i] = 0x3000;
	1202	else if (i > 0x0400) m_mask_table[i] = 0x3800;
	1203	else if (i > 0x0200) m_mask_table[i] = 0x3c00;
	1204	else if (i > 0x0100) m_mask_table[i] = 0x3e00;
	1205	else if (i > 0x0080) m_mask_table[i] = 0x3f00;
	1206	else if (i > 0x0040) m_mask_table[i] = 0x3f80;
	1207	else if (i > 0x0020) m_mask_table[i] = 0x3fc0;
	1208	else if (i > 0x0010) m_mask_table[i] = 0x3fe0;
	1209	else if (i > 0x0008) m_mask_table[i] = 0x3ff0;
	1210	else if (i > 0x0004) m_mask_table[i] = 0x3ff8;
	1211	else if (i > 0x0002) m_mask_table[i] = 0x3ffc;
	1212	else if (i > 0x0001) m_mask_table[i] = 0x3ffe;
	1213	else m_mask_table[i] = 0x3fff;
933	1214	}
934	1215
935		/* initialize the condition table */
936		for (i = 0; i < 0x100; i++)
	1216	// initialize the condition table
	1217	for (int i = 0; i < 0x100; i++)
937	1218	{
938	1219	int az = ((i & ZFLAG) != 0);
939	1220	int an = ((i & NFLAG) != 0);
r9081	r9082
942	1223	int mv = ((i & MVFLAG) != 0);
943	1224	int as = ((i & SFLAG) != 0);
944	1225
945		condition_table[i \| 0x000] = az;
946		condition_table[i \| 0x100] = !az;
947		condition_table[i \| 0x200] = !((an ^ av) \| az);
948		condition_table[i \| 0x300] = (an ^ av) \| az;
949		condition_table[i \| 0x400] = an ^ av;
950		condition_table[i \| 0x500] = !(an ^ av);
951		condition_table[i \| 0x600] = av;
952		condition_table[i \| 0x700] = !av;
953		condition_table[i \| 0x800] = ac;
954		condition_table[i \| 0x900] = !ac;
955		condition_table[i \| 0xa00] = as;
956		condition_table[i \| 0xb00] = !as;
957		condition_table[i \| 0xc00] = mv;
958		condition_table[i \| 0xd00] = !mv;
959		condition_table[i \| 0xf00] = 1;
	1226	m_condition_table[i \| 0x000] = az;
	1227	m_condition_table[i \| 0x100] = !az;
	1228	m_condition_table[i \| 0x200] = !((an ^ av) \| az);
	1229	m_condition_table[i \| 0x300] = (an ^ av) \| az;
	1230	m_condition_table[i \| 0x400] = an ^ av;
	1231	m_condition_table[i \| 0x500] = !(an ^ av);
	1232	m_condition_table[i \| 0x600] = av;
	1233	m_condition_table[i \| 0x700] = !av;
	1234	m_condition_table[i \| 0x800] = ac;
	1235	m_condition_table[i \| 0x900] = !ac;
	1236	m_condition_table[i \| 0xa00] = as;
	1237	m_condition_table[i \| 0xb00] = !as;
	1238	m_condition_table[i \| 0xc00] = mv;
	1239	m_condition_table[i \| 0xd00] = !mv;
	1240	m_condition_table[i \| 0xf00] = 1;
960	1241	}
961		return 1;
962	1242	}
963	1243
964	1244
965		static CPU_EXIT( adsp21xx )
966		{
967		if (reverse_table != NULL)
968		global_free(reverse_table);
969		reverse_table = NULL;
970	1245
971		if (mask_table != NULL)
972		global_free(mask_table);
973		mask_table = NULL;
	1246	/***************************************************************************
	1247	CORE EXECUTION LOOP
	1248	***************************************************************************/
974	1249
975		if (condition_table != NULL)
976		global_free(condition_table);
977		condition_table = NULL;
	1250	void adsp21xx_device::execute_set_input(int inputnum, int state)
	1251	{
	1252	// update the latched state
	1253	if (state != CLEAR_LINE && m_irq_state[inputnum] == CLEAR_LINE)
	1254	m_irq_latch[inputnum] = 1;
978	1255
979		#if TRACK_HOTSPOTS
980		{
981		FILE *log = fopen("adsp.hot", "w");
982		while (1)
983		{
984		int maxindex = 0, i;
985		for (i = 1; i < 0x4000; i++)
986		if (pcbucket[i] > pcbucket[maxindex])
987		maxindex = i;
988		if (pcbucket[maxindex] == 0)
989		break;
990		fprintf(log, "PC=%04X (%10d hits)\n", maxindex, pcbucket[maxindex]);
991		pcbucket[maxindex] = 0;
992		}
993		fclose(log);
994		}
995		#endif
996
	1256	// update the absolute state
	1257	m_irq_state[inputnum] = state;
997	1258	}
998	1259
999	1260
1000
1001		/***************************************************************************
1002		CORE EXECUTION LOOP
1003		***************************************************************************/
1004
1005		/* execute instructions on this CPU until icount expires */
1006		static CPU_EXECUTE( adsp21xx )
	1261	void adsp21xx_device::execute_run()
1007	1262	{
1008		int check_debugger = ((device->machine->debug_flags & DEBUG_FLAG_ENABLED) != 0);
1009		adsp2100_state *adsp = get_safe_token(device);
	1263	bool check_debugger = ((device_t::m_machine.debug_flags & DEBUG_FLAG_ENABLED) != 0);
1010	1264
1011		check_irqs(~~adsp~~);
	1265	check_irqs();
1012	1266
1013	1267	do
1014	1268	{
1015		UINT32 temp;
1016		UINT32 op;
1017
1018		/* debugging */
1019		adsp->ppc = adsp->pc; /* copy PC to previous PC */
	1269	// debugging
	1270	m_ppc = m_pc; // copy PC to previous PC
1020	1271	if (check_debugger)
1021		debugger_instruction_hook(~~dev~~ice, ~~adsp->~~pc);
	1272	debugger_instruction_hook(*this, m_pc);
1022	1273
1023		#if TRACK_HOTSPOTS
1024		pcbucket[adsp->pc & 0x3fff]++;
	1274	#if ADSP_TRACK_HOTSPOTS
	1275	m_pcbucket[m_pc & 0x3fff]++;
1025	1276	#endif
1026	1277
1027		/* instruction fetch */
1028		op = ROPCODE(adsp);
	1278	// instruction fetch
	1279	UINT32 op = opcode_read();
1029	1280
1030		/* advance to the next instruction */
1031		if (adsp->pc != adsp->loop)
1032		adsp->pc++;
	1281	// advance to the next instruction
	1282	if (m_pc != m_loop)
	1283	m_pc++;
1033	1284
1034		/* handle looping */
	1285	// handle looping
1035	1286	else
1036	1287	{
1037		/* condition not met, keep looping */
1038		if (CONDITION(adsp, adsp->loop_condition))
1039		adsp->pc = pc_stack_top(adsp);
	1288	// condition not met, keep looping
	1289	if (condition(m_loop_condition))
	1290	m_pc = pc_stack_top();
1040	1291
1041		/* condition met; pop the PC and loop stacks and fall through */
	1292	// condition met; pop the PC and loop stacks and fall through
1042	1293	else
1043	1294	{
1044		loop_stack_pop(adsp);
1045		pc_stack_pop_val(adsp);
1046		adsp->pc++;
	1295	loop_stack_pop();
	1296	pc_stack_pop_val();
	1297	m_pc++;
1047	1298	}
1048	1299	}
1049	1300
1050		/* parse the instruction */
1051		switch (op >> 16)
	1301	// parse the instruction
	1302	UINT32 temp;
	1303	switch ((op >> 16) & 0xff)
1052	1304	{
1053	1305	case 0x00:
1054		/* 00000000 00000000 00000000 NOP */
	1306	// 00000000 00000000 00000000 NOP
1055	1307	break;
1056	1308	case 0x01:
1057		/* 00000001 0xxxxxxx xxxxxxxx dst = IO(x) */
1058		/* 00000001 1xxxxxxx xxxxxxxx IO(x) = dst */
1059		/* ADSP-218x only */
1060		if (adsp->chip_type >= CHIP_TYPE_ADSP2181)
	1309	// 00000001 0xxxxxxx xxxxxxxx dst = IO(x)
	1310	// 00000001 1xxxxxxx xxxxxxxx IO(x) = dst
	1311	// ADSP-218x only
	1312	if (m_config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2181)
1061	1313	{
1062	1314	if ((op & 0x008000) == 0x000000)
1063		~~WRITE~~_~~REG(adsp,~~ 0, op & 15, ~~RWORD~~_~~IO(~~ad~~sp,~~ (op >> 4) & 0x7ff));
	1315	write_reg0(op & 15, io_read((op >> 4) & 0x7ff));
1064	1316	else
1065		~~WWORD~~_IO(~~adsp,~~ (op >> 4) & 0x7ff, ~~READ_REG(~~ad~~sp,~~ 0, op & 15));
	1317	io_write((op >> 4) & 0x7ff, read_reg0(op & 15));
1066	1318	}
1067	1319	break;
1068	1320	case 0x02:
1069		/* 00000010 0000xxxx xxxxxxxx modify flag out */
1070		/* 00000010 10000000 00000000 idle */
1071		/* 00000010 10000000 0000xxxx idle (n) */
	1321	// 00000010 0000xxxx xxxxxxxx modify flag out
	1322	// 00000010 10000000 00000000 idle
	1323	// 00000010 10000000 0000xxxx idle (n)
1072	1324	if (op & 0x008000)
1073	1325	{
1074		adsp->idle = 1;
1075		adsp->icount = 0;
	1326	m_idle = 1;
	1327	m_icount = 0;
1076	1328	}
1077	1329	else
1078	1330	{
1079		if (~~CONDITION(a~~d~~sp,~~ op & 15))
	1331	if (condition(op & 15))
1080	1332	{
1081		if (op & 0x020) adsp->flagout = 0;
1082		if (op & 0x010) adsp->flagout ^= 1;
1083		if (adsp->chip_type >= CHIP_TYPE_ADSP2101)
	1333	if (op & 0x020) m_flagout = 0;
	1334	if (op & 0x010) m_flagout ^= 1;
	1335	if (m_config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2101)
1084	1336	{
1085		if (op & 0x080) adsp->fl0 = 0;
1086		if (op & 0x040) adsp->fl0 ^= 1;
1087		if (op & 0x200) adsp->fl1 = 0;
1088		if (op & 0x100) adsp->fl1 ^= 1;
1089		if (op & 0x800) adsp->fl2 = 0;
1090		if (op & 0x400) adsp->fl2 ^= 1;
	1337	if (op & 0x080) m_fl0 = 0;
	1338	if (op & 0x040) m_fl0 ^= 1;
	1339	if (op & 0x200) m_fl1 = 0;
	1340	if (op & 0x100) m_fl1 ^= 1;
	1341	if (op & 0x800) m_fl2 = 0;
	1342	if (op & 0x400) m_fl2 ^= 1;
1091	1343	}
1092	1344	}
1093	1345	}
1094	1346	break;
1095	1347	case 0x03:
1096		/* 00000011 xxxxxxxx xxxxxxxx call or jump on flag in */
	1348	// 00000011 xxxxxxxx xxxxxxxx call or jump on flag in
1097	1349	if (op & 0x000002)
1098	1350	{
1099		if (~~adsp->~~flagin)
	1351	if (m_flagin)
1100	1352	{
1101	1353	if (op & 0x000001)
1102		pc_stack_push(adsp);
1103		adsp->pc = ((op >> 4) & 0x0fff) \| ((op << 10) & 0x3000);
	1354	pc_stack_push();
	1355	m_pc = ((op >> 4) & 0x0fff) \| ((op << 10) & 0x3000);
1104	1356	}
1105	1357	}
1106	1358	else
1107	1359	{
1108		if (!~~adsp->~~flagin)
	1360	if (!m_flagin)
1109	1361	{
1110	1362	if (op & 0x000001)
1111		pc_stack_push(adsp);
1112		adsp->pc = ((op >> 4) & 0x0fff) \| ((op << 10) & 0x3000);
	1363	pc_stack_push();
	1364	m_pc = ((op >> 4) & 0x0fff) \| ((op << 10) & 0x3000);
1113	1365	}
1114	1366	}
1115	1367	break;
1116	1368	case 0x04:
1117		/* 00000100 00000000 000xxxxx stack control */
1118		if (op & 0x000010) pc_stack_pop_val(adsp);
1119		if (op & 0x000008) loop_stack_pop(adsp);
1120		if (op & 0x000004) cntr_stack_pop(adsp);
	1369	// 00000100 00000000 000xxxxx stack control
	1370	if (op & 0x000010) pc_stack_pop_val();
	1371	if (op & 0x000008) loop_stack_pop();
	1372	if (op & 0x000004) cntr_stack_pop();
1121	1373	if (op & 0x000002)
1122	1374	{
1123		if (op & 0x000001) stat_stack_pop(adsp);
1124		else stat_stack_push(adsp);
	1375	if (op & 0x000001) stat_stack_pop();
	1376	else stat_stack_push();
1125	1377	}
1126	1378	break;
1127	1379	case 0x05:
1128		/* 00000101 00000000 00000000 saturate MR */
	1380	// 00000101 00000000 00000000 saturate MR
1129	1381	if (GET_MV)
1130	1382	{
1131		if (adsp->core.mr.mrx.mr2.u & 0x80)
1132		adsp->core.mr.mrx.mr2.u = 0xffff, adsp->core.mr.mrx.mr1.u = 0x8000, adsp->core.mr.mrx.mr0.u = 0x0000;
	1383	if (m_core.mr.mrx.mr2.u & 0x80)
	1384	m_core.mr.mrx.mr2.u = 0xffff, m_core.mr.mrx.mr1.u = 0x8000, m_core.mr.mrx.mr0.u = 0x0000;
1133	1385	else
1134		~~adsp->~~core.mr.mrx.mr2.u = 0x0000, ~~adsp->~~core.mr.mrx.mr1.u = 0x7fff, ~~adsp->~~core.mr.mrx.mr0.u = 0xffff;
	1386	m_core.mr.mrx.mr2.u = 0x0000, m_core.mr.mrx.mr1.u = 0x7fff, m_core.mr.mrx.mr0.u = 0xffff;
1135	1387	}
1136	1388	break;
1137	1389	case 0x06:
1138		/* 00000110 000xxxxx 00000000 DIVS */
	1390	// 00000110 000xxxxx 00000000 DIVS
1139	1391	{
1140	1392	int xop = (op >> 8) & 7;
1141	1393	int yop = (op >> 11) & 3;
1142	1394
1143		xop = ALU_GETXREG_UNSIGNED(adsp, xop);
1144		yop = ALU_GETYREG_UNSIGNED(adsp, yop);
	1395	xop = ALU_GETXREG_UNSIGNED(xop);
	1396	yop = ALU_GETYREG_UNSIGNED(yop);
1145	1397
1146	1398	temp = xop ^ yop;
1147		adsp->astat = (adsp->astat & ~QFLAG) \| ((temp >> 10) & QFLAG);
1148		adsp->core.af.u = (yop << 1) \| (adsp->core.ay0.u >> 15);
1149		adsp->core.ay0.u = (adsp->core.ay0.u << 1) \| (temp >> 15);
	1399	m_astat = (m_astat & ~QFLAG) \| ((temp >> 10) & QFLAG);
	1400	m_core.af.u = (yop << 1) \| (m_core.ay0.u >> 15);
	1401	m_core.ay0.u = (m_core.ay0.u << 1) \| (temp >> 15);
1150	1402	}
1151	1403	break;
1152	1404	case 0x07:
1153		/* 00000111 00010xxx 00000000 DIVQ */
	1405	// 00000111 00010xxx 00000000 DIVQ
1154	1406	{
1155	1407	int xop = (op >> 8) & 7;
1156	1408	int res;
1157	1409
1158		xop = ALU_GETXREG_UNSIGNED(~~adsp,~~ xop);
	1410	xop = ALU_GETXREG_UNSIGNED(xop);
1159	1411
1160	1412	if (GET_Q)
1161		res = ~~adsp->~~core.af.u + xop;
	1413	res = m_core.af.u + xop;
1162	1414	else
1163		res = ~~adsp->~~core.af.u - xop;
	1415	res = m_core.af.u - xop;
1164	1416
1165	1417	temp = res ^ xop;
1166		adsp->astat = (adsp->astat & ~QFLAG) \| ((temp >> 10) & QFLAG);
1167		adsp->core.af.u = (res << 1) \| (adsp->core.ay0.u >> 15);
1168		adsp->core.ay0.u = (adsp->core.ay0.u << 1) \| ((~temp >> 15) & 0x0001);
	1418	m_astat = (m_astat & ~QFLAG) \| ((temp >> 10) & QFLAG);
	1419	m_core.af.u = (res << 1) \| (m_core.ay0.u >> 15);
	1420	m_core.ay0.u = (m_core.ay0.u << 1) \| ((~temp >> 15) & 0x0001);
1169	1421	}
1170	1422	break;
1171	1423	case 0x08:
1172		/* 00001000 00000000 0000xxxx reserved */
	1424	// 00001000 00000000 0000xxxx reserved
1173	1425	break;
1174	1426	case 0x09:
1175		/* 00001001 00000000 000xxxxx modify address register */
	1427	// 00001001 00000000 000xxxxx modify address register
1176	1428	temp = (op >> 2) & 4;
1177		modify_address(~~adsp,~~ temp + ((op >> 2) & 3), temp + (op & 3));
	1429	modify_address(temp + ((op >> 2) & 3), temp + (op & 3));
1178	1430	break;
1179	1431	case 0x0a:
1180		/* 00001010 00000000 000xxxxx conditional return */
1181		if (CONDITION(adsp, op & 15))
	1432	// 00001010 00000000 000xxxxx conditional return
	1433	if (condition(op & 15))
1182	1434	{
1183		pc_stack_pop(~~adsp~~);
	1435	pc_stack_pop();
1184	1436
1185		/* RTI case */
	1437	// RTI case
1186	1438	if (op & 0x000010)
1187		stat_stack_pop(~~adsp~~);
	1439	stat_stack_pop();
1188	1440	}
1189	1441	break;
1190	1442	case 0x0b:
1191		/* 00001011 00000000 xxxxxxxx conditional jump (indirect address) */
1192		if (CONDITION(adsp, op & 15))
	1443	// 00001011 00000000 xxxxxxxx conditional jump (indirect address)
	1444	if (condition(op & 15))
1193	1445	{
1194	1446	if (op & 0x000010)
1195		pc_stack_push(adsp);
1196		adsp->pc = adsp->i[4 + ((op >> 6) & 3)] & 0x3fff;
	1447	pc_stack_push();
	1448	m_pc = m_i[4 + ((op >> 6) & 3)] & 0x3fff;
1197	1449	}
1198	1450	break;
1199	1451	case 0x0c:
1200		/* 00001100 xxxxxxxx xxxxxxxx mode control */
1201		if (adsp->chip_type >= CHIP_TYPE_ADSP2101)
	1452	// 00001100 xxxxxxxx xxxxxxxx mode control
	1453	if (m_config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2101)
1202	1454	{
1203		if (op & 0x000008) adsp->mstat = (adsp->mstat & ~MSTAT_GOMODE) \| ((op << 5) & MSTAT_GOMODE);
1204		if (op & 0x002000) adsp->mstat = (adsp->mstat & ~MSTAT_INTEGER) \| ((op >> 8) & MSTAT_INTEGER);
1205		if (op & 0x008000) adsp->mstat = (adsp->mstat & ~MSTAT_TIMER) \| ((op >> 9) & MSTAT_TIMER);
	1455	if (op & 0x000008) m_mstat = (m_mstat & ~MSTAT_GOMODE) \| ((op << 5) & MSTAT_GOMODE);
	1456	if (op & 0x002000) m_mstat = (m_mstat & ~MSTAT_INTEGER) \| ((op >> 8) & MSTAT_INTEGER);
	1457	if (op & 0x008000) m_mstat = (m_mstat & ~MSTAT_TIMER) \| ((op >> 9) & MSTAT_TIMER);
1206	1458	}
1207		if (op & 0x000020) adsp->mstat = (adsp->mstat & ~MSTAT_BANK) \| ((op >> 4) & MSTAT_BANK);
1208		if (op & 0x000080) adsp->mstat = (adsp->mstat & ~MSTAT_REVERSE) \| ((op >> 5) & MSTAT_REVERSE);
1209		if (op & 0x000200) adsp->mstat = (adsp->mstat & ~MSTAT_STICKYV) \| ((op >> 6) & MSTAT_STICKYV);
1210		if (op & 0x000800) adsp->mstat = (adsp->mstat & ~MSTAT_SATURATE) \| ((op >> 7) & MSTAT_SATURATE);
1211		update_mstat(adsp);
	1459	if (op & 0x000020) m_mstat = (m_mstat & ~MSTAT_BANK) \| ((op >> 4) & MSTAT_BANK);
	1460	if (op & 0x000080) m_mstat = (m_mstat & ~MSTAT_REVERSE) \| ((op >> 5) & MSTAT_REVERSE);
	1461	if (op & 0x000200) m_mstat = (m_mstat & ~MSTAT_STICKYV) \| ((op >> 6) & MSTAT_STICKYV);
	1462	if (op & 0x000800) m_mstat = (m_mstat & ~MSTAT_SATURATE) \| ((op >> 7) & MSTAT_SATURATE);
	1463	update_mstat();
1212	1464	break;
1213	1465	case 0x0d:
1214		/* 00001101 0000xxxx xxxxxxxx internal data move */
1215		WRITE_REG(adsp, (op >> 10) & 3, (op >> 4) & 15, READ_REG(adsp, (op >> 8) & 3, op & 15));
	1466	// 00001101 0000xxxx xxxxxxxx internal data move
	1467	switch ((op >> 8) & 15)
	1468	{
	1469	case 0x00: write_reg0((op >> 4) & 15, read_reg0(op & 15)); break;
	1470	case 0x01: write_reg0((op >> 4) & 15, read_reg1(op & 15)); break;
	1471	case 0x02: write_reg0((op >> 4) & 15, read_reg2(op & 15)); break;
	1472	case 0x03: write_reg0((op >> 4) & 15, read_reg3(op & 15)); break;
	1473	case 0x04: write_reg1((op >> 4) & 15, read_reg0(op & 15)); break;
	1474	case 0x05: write_reg1((op >> 4) & 15, read_reg1(op & 15)); break;
	1475	case 0x06: write_reg1((op >> 4) & 15, read_reg2(op & 15)); break;
	1476	case 0x07: write_reg1((op >> 4) & 15, read_reg3(op & 15)); break;
	1477	case 0x08: write_reg2((op >> 4) & 15, read_reg0(op & 15)); break;
	1478	case 0x09: write_reg2((op >> 4) & 15, read_reg1(op & 15)); break;
	1479	case 0x0a: write_reg2((op >> 4) & 15, read_reg2(op & 15)); break;
	1480	case 0x0b: write_reg2((op >> 4) & 15, read_reg3(op & 15)); break;
	1481	case 0x0c: write_reg3((op >> 4) & 15, read_reg0(op & 15)); break;
	1482	case 0x0d: write_reg3((op >> 4) & 15, read_reg1(op & 15)); break;
	1483	case 0x0e: write_reg3((op >> 4) & 15, read_reg2(op & 15)); break;
	1484	case 0x0f: write_reg3((op >> 4) & 15, read_reg3(op & 15)); break;
	1485	}
1216	1486	break;
1217	1487	case 0x0e:
1218		/* 00001110 0xxxxxxx xxxxxxxx conditional shift */
1219		if (CONDITION(adsp, op & 15)) shift_op(adsp, op);
	1488	// 00001110 0xxxxxxx xxxxxxxx conditional shift
	1489	if (condition(op & 15)) shift_op(op);
1220	1490	break;
1221	1491	case 0x0f:
1222		/* 00001111 0xxxxxxx xxxxxxxx shift immediate */
1223		shift_op_imm(adsp, op);
	1492	// 00001111 0xxxxxxx xxxxxxxx shift immediate
	1493	shift_op_imm(op);
1224	1494	break;
1225	1495	case 0x10:
1226		/* 00010000 0xxxxxxx xxxxxxxx shift with internal data register move */
1227		shift_op(adsp, op);
1228		temp = READ_REG(adsp, 0, op & 15);
1229		WRITE_REG(adsp, 0, (op >> 4) & 15, temp);
	1496	// 00010000 0xxxxxxx xxxxxxxx shift with internal data register move
	1497	shift_op(op);
	1498	temp = read_reg0(op & 15);
	1499	write_reg0((op >> 4) & 15, temp);
1230	1500	break;
1231	1501	case 0x11:
1232		/* 00010001 xxxxxxxx xxxxxxxx shift with pgm memory read/write */
	1502	// 00010001 xxxxxxxx xxxxxxxx shift with pgm memory read/write
1233	1503	if (op & 0x8000)
1234	1504	{
1235		pgm_write_dag2(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1236		shift_op(adsp, op);
	1505	pgm_write_dag2(op, read_reg0((op >> 4) & 15));
	1506	shift_op(op);
1237	1507	}
1238	1508	else
1239	1509	{
1240		shift_op(adsp, op);
1241		WRITE_REG(adsp, 0, (op >> 4) & 15, pgm_read_dag2(adsp, op));
	1510	shift_op(op);
	1511	write_reg0((op >> 4) & 15, pgm_read_dag2(op));
1242	1512	}
1243	1513	break;
1244	1514	case 0x12:
1245		/* 00010010 xxxxxxxx xxxxxxxx shift with data memory read/write DAG1 */
	1515	// 00010010 xxxxxxxx xxxxxxxx shift with data memory read/write DAG1
1246	1516	if (op & 0x8000)
1247	1517	{
1248		data_write_dag1(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1249		shift_op(adsp, op);
	1518	data_write_dag1(op, read_reg0((op >> 4) & 15));
	1519	shift_op(op);
1250	1520	}
1251	1521	else
1252	1522	{
1253		shift_op(adsp, op);
1254		WRITE_REG(adsp, 0, (op >> 4) & 15, data_read_dag1(adsp, op));
	1523	shift_op(op);
	1524	write_reg0((op >> 4) & 15, data_read_dag1(op));
1255	1525	}
1256	1526	break;
1257	1527	case 0x13:
1258		/* 00010011 xxxxxxxx xxxxxxxx shift with data memory read/write DAG2 */
	1528	// 00010011 xxxxxxxx xxxxxxxx shift with data memory read/write DAG2
1259	1529	if (op & 0x8000)
1260	1530	{
1261		data_write_dag2(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1262		shift_op(adsp, op);
	1531	data_write_dag2(op, read_reg0((op >> 4) & 15));
	1532	shift_op(op);
1263	1533	}
1264	1534	else
1265	1535	{
1266		shift_op(adsp, op);
1267		WRITE_REG(adsp, 0, (op >> 4) & 15, data_read_dag2(adsp, op));
	1536	shift_op(op);
	1537	write_reg0((op >> 4) & 15, data_read_dag2(op));
1268	1538	}
1269	1539	break;
1270	1540	case 0x14: case 0x15: case 0x16: case 0x17:
1271		/* 000101xx xxxxxxxx xxxxxxxx do until */
1272		loop_stack_push(adsp, op & 0x3ffff);
1273		pc_stack_push(adsp);
	1541	// 000101xx xxxxxxxx xxxxxxxx do until
	1542	loop_stack_push(op & 0x3ffff);
	1543	pc_stack_push();
1274	1544	break;
1275	1545	case 0x18: case 0x19: case 0x1a: case 0x1b:
1276		/* 000110xx xxxxxxxx xxxxxxxx conditional jump (immediate addr) */
1277		if (CONDITION(adsp, op & 15))
	1546	// 000110xx xxxxxxxx xxxxxxxx conditional jump (immediate addr)
	1547	if (condition(op & 15))
1278	1548	{
1279		adsp->pc = (op >> 4) & 0x3fff;
1280		/* check for a busy loop */
1281		if (adsp->pc == adsp->ppc)
1282		adsp->icount = 0;
	1549	m_pc = (op >> 4) & 0x3fff;
	1550	// check for a busy loop
	1551	if (m_pc == m_ppc)
	1552	m_icount = 0;
1283	1553	}
1284	1554	break;
1285	1555	case 0x1c: case 0x1d: case 0x1e: case 0x1f:
1286		/* 000111xx xxxxxxxx xxxxxxxx conditional call (immediate addr) */
1287		if (CONDITION(adsp, op & 15))
	1556	// 000111xx xxxxxxxx xxxxxxxx conditional call (immediate addr)
	1557	if (condition(op & 15))
1288	1558	{
1289		pc_stack_push(adsp);
1290		adsp->pc = (op >> 4) & 0x3fff;
	1559	pc_stack_push();
	1560	m_pc = (op >> 4) & 0x3fff;
1291	1561	}
1292	1562	break;
1293	1563	case 0x20: case 0x21:
1294		/* 0010000x xxxxxxxx xxxxxxxx conditional MAC to MR */
1295		if (CONDITION(adsp, op & 15))
	1564	// 0010000x xxxxxxxx xxxxxxxx conditional MAC to MR
	1565	if (condition(op & 15))
1296	1566	{
1297		if (adsp->chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010)
1298		mac_op_mr_xop(adsp, op);
	1567	if (m_config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010)
	1568	mac_op_mr_xop(op);
1299	1569	else
1300		mac_op_mr(~~adsp,~~ op);
	1570	mac_op_mr(op);
1301	1571	}
1302	1572	break;
1303	1573	case 0x22: case 0x23:
1304		/* 0010001x xxxxxxxx xxxxxxxx conditional ALU to AR */
1305		if (CONDITION(adsp, op & 15))
	1574	// 0010001x xxxxxxxx xxxxxxxx conditional ALU to AR
	1575	if (condition(op & 15))
1306	1576	{
1307		if (adsp->chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010)
1308		alu_op_ar_const(adsp, op);
	1577	if (m_config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010)
	1578	alu_op_ar_const(op);
1309	1579	else
1310		alu_op_ar(~~adsp,~~ op);
	1580	alu_op_ar(op);
1311	1581	}
1312	1582	break;
1313	1583	case 0x24: case 0x25:
1314		/* 0010010x xxxxxxxx xxxxxxxx conditional MAC to MF */
1315		if (CONDITION(adsp, op & 15))
	1584	// 0010010x xxxxxxxx xxxxxxxx conditional MAC to MF
	1585	if (condition(op & 15))
1316	1586	{
1317		if (adsp->chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010)
1318		mac_op_mf_xop(adsp, op);
	1587	if (m_config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010)
	1588	mac_op_mf_xop(op);
1319	1589	else
1320		mac_op_mf(~~adsp,~~ op);
	1590	mac_op_mf(op);
1321	1591	}
1322	1592	break;
1323	1593	case 0x26: case 0x27:
1324		/* 0010011x xxxxxxxx xxxxxxxx conditional ALU to AF */
1325		if (CONDITION(adsp, op & 15))
	1594	// 0010011x xxxxxxxx xxxxxxxx conditional ALU to AF
	1595	if (condition(op & 15))
1326	1596	{
1327		if (adsp->chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010)
1328		alu_op_af_const(adsp, op);
	1597	if (m_config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010)
	1598	alu_op_af_const(op);
1329	1599	else
1330		alu_op_af(~~adsp,~~ op);
	1600	alu_op_af(op);
1331	1601	}
1332	1602	break;
1333	1603	case 0x28: case 0x29:
1334		/* 0010100x xxxxxxxx xxxxxxxx MAC to MR with internal data register move */
1335		temp = READ_REG(adsp, 0, op & 15);
1336		mac_op_mr(adsp, op);
1337		WRITE_REG(adsp, 0, (op >> 4) & 15, temp);
	1604	// 0010100x xxxxxxxx xxxxxxxx MAC to MR with internal data register move
	1605	temp = read_reg0(op & 15);
	1606	mac_op_mr(op);
	1607	write_reg0((op >> 4) & 15, temp);
1338	1608	break;
1339	1609	case 0x2a: case 0x2b:
1340		/* 0010101x xxxxxxxx xxxxxxxx ALU to AR with internal data register move */
1341		if (adsp->chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0000ff) == 0x0000aa)
1342		alu_op_none(adsp, op);
	1610	// 0010101x xxxxxxxx xxxxxxxx ALU to AR with internal data register move
	1611	if (m_config.m_chip_type >= adsp21xx_device_config::CHIP_TYPE_ADSP2181 && (op & 0x0000ff) == 0x0000aa)
	1612	alu_op_none(op);
1343	1613	else
1344	1614	{
1345		temp = READ_REG(adsp, 0, op & 15);
1346		alu_op_ar(adsp, op);
1347		WRITE_REG(adsp, 0, (op >> 4) & 15, temp);
	1615	temp = read_reg0(op & 15);
	1616	alu_op_ar(op);
	1617	write_reg0((op >> 4) & 15, temp);
1348	1618	}
1349	1619	break;
1350	1620	case 0x2c: case 0x2d:
1351		/* 0010110x xxxxxxxx xxxxxxxx MAC to MF with internal data register move */
1352		temp = READ_REG(adsp, 0, op & 15);
1353		mac_op_mf(adsp, op);
1354		WRITE_REG(adsp, 0, (op >> 4) & 15, temp);
	1621	// 0010110x xxxxxxxx xxxxxxxx MAC to MF with internal data register move
	1622	temp = read_reg0(op & 15);
	1623	mac_op_mf(op);
	1624	write_reg0((op >> 4) & 15, temp);
1355	1625	break;
1356	1626	case 0x2e: case 0x2f:
1357		/* 0010111x xxxxxxxx xxxxxxxx ALU to AF with internal data register move */
1358		temp = READ_REG(adsp, 0, op & 15);
1359		alu_op_af(adsp, op);
1360		WRITE_REG(adsp, 0, (op >> 4) & 15, temp);
	1627	// 0010111x xxxxxxxx xxxxxxxx ALU to AF with internal data register move
	1628	temp = read_reg0(op & 15);
	1629	alu_op_af(op);
	1630	write_reg0((op >> 4) & 15, temp);
1361	1631	break;
1362	1632	case 0x30: case 0x31: case 0x32: case 0x33:
1363		/* 001100xx xxxxxxxx xxxxxxxx load non-data register immediate (group 0) */
1364		WRITE_REG(adsp, 0, op & 15, (INT32)(op << 14) >> 18);
	1633	// 001100xx xxxxxxxx xxxxxxxx load non-data register immediate (group 0)
	1634	write_reg0(op & 15, (INT32)(op << 14) >> 18);
1365	1635	break;
1366	1636	case 0x34: case 0x35: case 0x36: case 0x37:
1367		/* 001101xx xxxxxxxx xxxxxxxx load non-data register immediate (group 1) */
1368		WRITE_REG(adsp, 1, op & 15, (INT32)(op << 14) >> 18);
	1637	// 001101xx xxxxxxxx xxxxxxxx load non-data register immediate (group 1)
	1638	write_reg1(op & 15, (INT32)(op << 14) >> 18);
1369	1639	break;
1370	1640	case 0x38: case 0x39: case 0x3a: case 0x3b:
1371		/* 001110xx xxxxxxxx xxxxxxxx load non-data register immediate (group 2) */
1372		WRITE_REG(adsp, 2, op & 15, (INT32)(op << 14) >> 18);
	1641	// 001110xx xxxxxxxx xxxxxxxx load non-data register immediate (group 2)
	1642	write_reg2(op & 15, (INT32)(op << 14) >> 18);
1373	1643	break;
1374	1644	case 0x3c: case 0x3d: case 0x3e: case 0x3f:
1375		/* 001111xx xxxxxxxx xxxxxxxx load non-data register immediate (group 3) */
1376		WRITE_REG(adsp, 3, op & 15, (INT32)(op << 14) >> 18);
	1645	// 001111xx xxxxxxxx xxxxxxxx load non-data register immediate (group 3)
	1646	write_reg3(op & 15, (INT32)(op << 14) >> 18);
1377	1647	break;
1378	1648	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
1379	1649	case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
1380		/* 0100xxxx xxxxxxxx xxxxxxxx load data register immediate */
1381		WRITE_REG(adsp, 0, op & 15, (op >> 4) & 0xffff);
	1650	// 0100xxxx xxxxxxxx xxxxxxxx load data register immediate
	1651	write_reg0(op & 15, (op >> 4) & 0xffff);
1382	1652	break;
1383	1653	case 0x50: case 0x51:
1384		/* 0101000x xxxxxxxx xxxxxxxx MAC to MR with pgm memory read */
1385		mac_op_mr(adsp, op);
1386		WRITE_REG(adsp, 0, (op >> 4) & 15, pgm_read_dag2(adsp, op));
	1654	// 0101000x xxxxxxxx xxxxxxxx MAC to MR with pgm memory read
	1655	mac_op_mr(op);
	1656	write_reg0((op >> 4) & 15, pgm_read_dag2(op));
1387	1657	break;
1388	1658	case 0x52: case 0x53:
1389		/* 0101001x xxxxxxxx xxxxxxxx ALU to AR with pgm memory read */
1390		alu_op_ar(adsp, op);
1391		WRITE_REG(adsp, 0, (op >> 4) & 15, pgm_read_dag2(adsp, op));
	1659	// 0101001x xxxxxxxx xxxxxxxx ALU to AR with pgm memory read
	1660	alu_op_ar(op);
	1661	write_reg0((op >> 4) & 15, pgm_read_dag2(op));
1392	1662	break;
1393	1663	case 0x54: case 0x55:
1394		/* 0101010x xxxxxxxx xxxxxxxx MAC to MF with pgm memory read */
1395		mac_op_mf(adsp, op);
1396		WRITE_REG(adsp, 0, (op >> 4) & 15, pgm_read_dag2(adsp, op));
	1664	// 0101010x xxxxxxxx xxxxxxxx MAC to MF with pgm memory read
	1665	mac_op_mf(op);
	1666	write_reg0((op >> 4) & 15, pgm_read_dag2(op));
1397	1667	break;
1398	1668	case 0x56: case 0x57:
1399		/* 0101011x xxxxxxxx xxxxxxxx ALU to AF with pgm memory read */
1400		alu_op_af(adsp, op);
1401		WRITE_REG(adsp, 0, (op >> 4) & 15, pgm_read_dag2(adsp, op));
	1669	// 0101011x xxxxxxxx xxxxxxxx ALU to AF with pgm memory read
	1670	alu_op_af(op);
	1671	write_reg0((op >> 4) & 15, pgm_read_dag2(op));
1402	1672	break;
1403	1673	case 0x58: case 0x59:
1404		/* 0101100x xxxxxxxx xxxxxxxx MAC to MR with pgm memory write */
1405		pgm_write_dag2(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1406		mac_op_mr(adsp, op);
	1674	// 0101100x xxxxxxxx xxxxxxxx MAC to MR with pgm memory write
	1675	pgm_write_dag2(op, read_reg0((op >> 4) & 15));
	1676	mac_op_mr(op);
1407	1677	break;
1408	1678	case 0x5a: case 0x5b:
1409		/* 0101101x xxxxxxxx xxxxxxxx ALU to AR with pgm memory write */
1410		pgm_write_dag2(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1411		alu_op_ar(adsp, op);
	1679	// 0101101x xxxxxxxx xxxxxxxx ALU to AR with pgm memory write
	1680	pgm_write_dag2(op, read_reg0((op >> 4) & 15));
	1681	alu_op_ar(op);
1412	1682	break;
1413	1683	case 0x5c: case 0x5d:
1414		/* 0101110x xxxxxxxx xxxxxxxx ALU to MR with pgm memory write */
1415		pgm_write_dag2(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1416		mac_op_mf(adsp, op);
	1684	// 0101110x xxxxxxxx xxxxxxxx ALU to MR with pgm memory write
	1685	pgm_write_dag2(op, read_reg0((op >> 4) & 15));
	1686	mac_op_mf(op);
1417	1687	break;
1418	1688	case 0x5e: case 0x5f:
1419		/* 0101111x xxxxxxxx xxxxxxxx ALU to MF with pgm memory write */
1420		pgm_write_dag2(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1421		alu_op_af(adsp, op);
	1689	// 0101111x xxxxxxxx xxxxxxxx ALU to MF with pgm memory write
	1690	pgm_write_dag2(op, read_reg0((op >> 4) & 15));
	1691	alu_op_af(op);
1422	1692	break;
1423	1693	case 0x60: case 0x61:
1424		/* 0110000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG1 */
1425		mac_op_mr(adsp, op);
1426		WRITE_REG(adsp, 0, (op >> 4) & 15, data_read_dag1(adsp, op));
	1694	// 0110000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG1
	1695	mac_op_mr(op);
	1696	write_reg0((op >> 4) & 15, data_read_dag1(op));
1427	1697	break;
1428	1698	case 0x62: case 0x63:
1429		/* 0110001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG1 */
1430		alu_op_ar(adsp, op);
1431		WRITE_REG(adsp, 0, (op >> 4) & 15, data_read_dag1(adsp, op));
	1699	// 0110001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG1
	1700	alu_op_ar(op);
	1701	write_reg0((op >> 4) & 15, data_read_dag1(op));
1432	1702	break;
1433	1703	case 0x64: case 0x65:
1434		/* 0110010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG1 */
1435		mac_op_mf(adsp, op);
1436		WRITE_REG(adsp, 0, (op >> 4) & 15, data_read_dag1(adsp, op));
	1704	// 0110010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG1
	1705	mac_op_mf(op);
	1706	write_reg0((op >> 4) & 15, data_read_dag1(op));
1437	1707	break;
1438	1708	case 0x66: case 0x67:
1439		/* 0110011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG1 */
1440		alu_op_af(adsp, op);
1441		WRITE_REG(adsp, 0, (op >> 4) & 15, data_read_dag1(adsp, op));
	1709	// 0110011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG1
	1710	alu_op_af(op);
	1711	write_reg0((op >> 4) & 15, data_read_dag1(op));
1442	1712	break;
1443	1713	case 0x68: case 0x69:
1444		/* 0110100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG1 */
1445		data_write_dag1(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1446		mac_op_mr(adsp, op);
	1714	// 0110100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG1
	1715	data_write_dag1(op, read_reg0((op >> 4) & 15));
	1716	mac_op_mr(op);
1447	1717	break;
1448	1718	case 0x6a: case 0x6b:
1449		/* 0110101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG1 */
1450		data_write_dag1(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1451		alu_op_ar(adsp, op);
	1719	// 0110101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG1
	1720	data_write_dag1(op, read_reg0((op >> 4) & 15));
	1721	alu_op_ar(op);
1452	1722	break;
1453	1723	case 0x6c: case 0x6d:
1454		/* 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG1 */
1455		data_write_dag1(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1456		mac_op_mf(adsp, op);
	1724	// 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG1
	1725	data_write_dag1(op, read_reg0((op >> 4) & 15));
	1726	mac_op_mf(op);
1457	1727	break;
1458	1728	case 0x6e: case 0x6f:
1459		/* 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG1 */
1460		data_write_dag1(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1461		alu_op_af(adsp, op);
	1729	// 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG1
	1730	data_write_dag1(op, read_reg0((op >> 4) & 15));
	1731	alu_op_af(op);
1462	1732	break;
1463	1733	case 0x70: case 0x71:
1464		/* 0111000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG2 */
1465		mac_op_mr(adsp, op);
1466		WRITE_REG(adsp, 0, (op >> 4) & 15, data_read_dag2(adsp, op));
	1734	// 0111000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG2
	1735	mac_op_mr(op);
	1736	write_reg0((op >> 4) & 15, data_read_dag2(op));
1467	1737	break;
1468	1738	case 0x72: case 0x73:
1469		/* 0111001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG2 */
1470		alu_op_ar(adsp, op);
1471		WRITE_REG(adsp, 0, (op >> 4) & 15, data_read_dag2(adsp, op));
	1739	// 0111001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG2
	1740	alu_op_ar(op);
	1741	write_reg0((op >> 4) & 15, data_read_dag2(op));
1472	1742	break;
1473	1743	case 0x74: case 0x75:
1474		/* 0111010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG2 */
1475		mac_op_mf(adsp, op);
1476		WRITE_REG(adsp, 0, (op >> 4) & 15, data_read_dag2(adsp, op));
	1744	// 0111010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG2
	1745	mac_op_mf(op);
	1746	write_reg0((op >> 4) & 15, data_read_dag2(op));
1477	1747	break;
1478	1748	case 0x76: case 0x77:
1479		/* 0111011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG2 */
1480		alu_op_af(adsp, op);
1481		WRITE_REG(adsp, 0, (op >> 4) & 15, data_read_dag2(adsp, op));
	1749	// 0111011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG2
	1750	alu_op_af(op);
	1751	write_reg0((op >> 4) & 15, data_read_dag2(op));
1482	1752	break;
1483	1753	case 0x78: case 0x79:
1484		/* 0111100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG2 */
1485		data_write_dag2(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1486		mac_op_mr(adsp, op);
	1754	// 0111100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG2
	1755	data_write_dag2(op, read_reg0((op >> 4) & 15));
	1756	mac_op_mr(op);
1487	1757	break;
1488	1758	case 0x7a: case 0x7b:
1489		/* 0111101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG2 */
1490		data_write_dag2(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1491		alu_op_ar(adsp, op);
	1759	// 0111101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG2
	1760	data_write_dag2(op, read_reg0((op >> 4) & 15));
	1761	alu_op_ar(op);
1492	1762	break;
1493	1763	case 0x7c: case 0x7d:
1494		/* 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG2 */
1495		data_write_dag2(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1496		mac_op_mf(adsp, op);
	1764	// 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG2
	1765	data_write_dag2(op, read_reg0((op >> 4) & 15));
	1766	mac_op_mf(op);
1497	1767	break;
1498	1768	case 0x7e: case 0x7f:
1499		/* 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG2 */
1500		data_write_dag2(adsp, op, READ_REG(adsp, 0, (op >> 4) & 15));
1501		alu_op_af(adsp, op);
	1769	// 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG2
	1770	data_write_dag2(op, read_reg0((op >> 4) & 15));
	1771	alu_op_af(op);
1502	1772	break;
1503	1773	case 0x80: case 0x81: case 0x82: case 0x83:
1504		/* 100000xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 0 */
1505		WRITE_REG(adsp, 0, op & 15, RWORD_DATA(adsp, (op >> 4) & 0x3fff));
	1774	// 100000xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 0
	1775	write_reg0(op & 15, data_read((op >> 4) & 0x3fff));
1506	1776	break;
1507	1777	case 0x84: case 0x85: case 0x86: case 0x87:
1508		/* 100001xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 1 */
1509		WRITE_REG(adsp, 1, op & 15, RWORD_DATA(adsp, (op >> 4) & 0x3fff));
	1778	// 100001xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 1
	1779	write_reg1(op & 15, data_read((op >> 4) & 0x3fff));
1510	1780	break;
1511	1781	case 0x88: case 0x89: case 0x8a: case 0x8b:
1512		/* 100010xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 2 */
1513		WRITE_REG(adsp, 2, op & 15, RWORD_DATA(adsp, (op >> 4) & 0x3fff));
	1782	// 100010xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 2
	1783	write_reg2(op & 15, data_read((op >> 4) & 0x3fff));
1514	1784	break;
1515	1785	case 0x8c: case 0x8d: case 0x8e: case 0x8f:
1516		/* 100011xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 3 */
1517		WRITE_REG(adsp, 3, op & 15, RWORD_DATA(adsp, (op >> 4) & 0x3fff));
	1786	// 100011xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 3
	1787	write_reg3(op & 15, data_read((op >> 4) & 0x3fff));
1518	1788	break;
1519	1789	case 0x90: case 0x91: case 0x92: case 0x93:
1520		/* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 0 */
1521		WWORD_DATA(adsp, (op >> 4) & 0x3fff, READ_REG(adsp, 0, op & 15));
	1790	// 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 0
	1791	data_write((op >> 4) & 0x3fff, read_reg0(op & 15));
1522	1792	break;
1523	1793	case 0x94: case 0x95: case 0x96: case 0x97:
1524		/* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 1 */
1525		WWORD_DATA(adsp, (op >> 4) & 0x3fff, READ_REG(adsp, 1, op & 15));
	1794	// 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 1
	1795	data_write((op >> 4) & 0x3fff, read_reg1(op & 15));
1526	1796	break;
1527	1797	case 0x98: case 0x99: case 0x9a: case 0x9b:
1528		/* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 2 */
1529		WWORD_DATA(adsp, (op >> 4) & 0x3fff, READ_REG(adsp, 2, op & 15));
	1798	// 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 2
	1799	data_write((op >> 4) & 0x3fff, read_reg2(op & 15));
1530	1800	break;
1531	1801	case 0x9c: case 0x9d: case 0x9e: case 0x9f:
1532		/* 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 3 */
1533		WWORD_DATA(adsp, (op >> 4) & 0x3fff, READ_REG(adsp, 3, op & 15));
	1802	// 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 3
	1803	data_write((op >> 4) & 0x3fff, read_reg3(op & 15));
1534	1804	break;
1535	1805	case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
1536	1806	case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
1537		/* 1010xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG1 */
1538		data_write_dag1(adsp, op, (op >> 4) & 0xffff);
	1807	// 1010xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG1
	1808	data_write_dag1(op, (op >> 4) & 0xffff);
1539	1809	break;
1540	1810	case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
1541	1811	case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
1542		/* 1011xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG2 */
1543		data_write_dag2(adsp, op, (op >> 4) & 0xffff);
	1812	// 1011xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG2
	1813	data_write_dag2(op, (op >> 4) & 0xffff);
1544	1814	break;
1545	1815	case 0xc0: case 0xc1:
1546		/* 1100000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to AY0 */
1547		mac_op_mr(adsp, op);
1548		adsp->core.ax0.u = data_read_dag1(adsp, op);
1549		adsp->core.ay0.u = pgm_read_dag2(adsp, op >> 4);
	1816	// 1100000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to AY0
	1817	mac_op_mr(op);
	1818	m_core.ax0.u = data_read_dag1(op);
	1819	m_core.ay0.u = pgm_read_dag2(op >> 4);
1550	1820	break;
1551	1821	case 0xc2: case 0xc3:
1552		/* 1100001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to AY0 */
1553		alu_op_ar(adsp, op);
1554		adsp->core.ax0.u = data_read_dag1(adsp, op);
1555		adsp->core.ay0.u = pgm_read_dag2(adsp, op >> 4);
	1822	// 1100001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to AY0
	1823	alu_op_ar(op);
	1824	m_core.ax0.u = data_read_dag1(op);
	1825	m_core.ay0.u = pgm_read_dag2(op >> 4);
1556	1826	break;
1557	1827	case 0xc4: case 0xc5:
1558		/* 1100010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to AY0 */
1559		mac_op_mr(adsp, op);
1560		adsp->core.ax1.u = data_read_dag1(adsp, op);
1561		adsp->core.ay0.u = pgm_read_dag2(adsp, op >> 4);
	1828	// 1100010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to AY0
	1829	mac_op_mr(op);
	1830	m_core.ax1.u = data_read_dag1(op);
	1831	m_core.ay0.u = pgm_read_dag2(op >> 4);
1562	1832	break;
1563	1833	case 0xc6: case 0xc7:
1564		/* 1100011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to AY0 */
1565		alu_op_ar(adsp, op);
1566		adsp->core.ax1.u = data_read_dag1(adsp, op);
1567		adsp->core.ay0.u = pgm_read_dag2(adsp, op >> 4);
	1834	// 1100011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to AY0
	1835	alu_op_ar(op);
	1836	m_core.ax1.u = data_read_dag1(op);
	1837	m_core.ay0.u = pgm_read_dag2(op >> 4);
1568	1838	break;
1569	1839	case 0xc8: case 0xc9:
1570		/* 1100100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to AY0 */
1571		mac_op_mr(adsp, op);
1572		adsp->core.mx0.u = data_read_dag1(adsp, op);
1573		adsp->core.ay0.u = pgm_read_dag2(adsp, op >> 4);
	1840	// 1100100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to AY0
	1841	mac_op_mr(op);
	1842	m_core.mx0.u = data_read_dag1(op);
	1843	m_core.ay0.u = pgm_read_dag2(op >> 4);
1574	1844	break;
1575	1845	case 0xca: case 0xcb:
1576		/* 1100101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to AY0 */
1577		alu_op_ar(adsp, op);
1578		adsp->core.mx0.u = data_read_dag1(adsp, op);
1579		adsp->core.ay0.u = pgm_read_dag2(adsp, op >> 4);
	1846	// 1100101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to AY0
	1847	alu_op_ar(op);
	1848	m_core.mx0.u = data_read_dag1(op);
	1849	m_core.ay0.u = pgm_read_dag2(op >> 4);
1580	1850	break;
1581	1851	case 0xcc: case 0xcd:
1582		/* 1100110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to AY0 */
1583		mac_op_mr(adsp, op);
1584		adsp->core.mx1.u = data_read_dag1(adsp, op);
1585		adsp->core.ay0.u = pgm_read_dag2(adsp, op >> 4);
	1852	// 1100110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to AY0
	1853	mac_op_mr(op);
	1854	m_core.mx1.u = data_read_dag1(op);
	1855	m_core.ay0.u = pgm_read_dag2(op >> 4);
1586	1856	break;
1587	1857	case 0xce: case 0xcf:
1588		/* 1100111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to AY0 */
1589		alu_op_ar(adsp, op);
1590		adsp->core.mx1.u = data_read_dag1(adsp, op);
1591		adsp->core.ay0.u = pgm_read_dag2(adsp, op >> 4);
	1858	// 1100111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to AY0
	1859	alu_op_ar(op);
	1860	m_core.mx1.u = data_read_dag1(op);
	1861	m_core.ay0.u = pgm_read_dag2(op >> 4);
1592	1862	break;
1593	1863	case 0xd0: case 0xd1:
1594		/* 1101000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to AY1 */
1595		mac_op_mr(adsp, op);
1596		adsp->core.ax0.u = data_read_dag1(adsp, op);
1597		adsp->core.ay1.u = pgm_read_dag2(adsp, op >> 4);
	1864	// 1101000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to AY1
	1865	mac_op_mr(op);
	1866	m_core.ax0.u = data_read_dag1(op);
	1867	m_core.ay1.u = pgm_read_dag2(op >> 4);
1598	1868	break;
1599	1869	case 0xd2: case 0xd3:
1600		/* 1101001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to AY1 */
1601		alu_op_ar(adsp, op);
1602		adsp->core.ax0.u = data_read_dag1(adsp, op);
1603		adsp->core.ay1.u = pgm_read_dag2(adsp, op >> 4);
	1870	// 1101001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to AY1
	1871	alu_op_ar(op);
	1872	m_core.ax0.u = data_read_dag1(op);
	1873	m_core.ay1.u = pgm_read_dag2(op >> 4);
1604	1874	break;
1605	1875	case 0xd4: case 0xd5:
1606		/* 1101010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to AY1 */
1607		mac_op_mr(adsp, op);
1608		adsp->core.ax1.u = data_read_dag1(adsp, op);
1609		adsp->core.ay1.u = pgm_read_dag2(adsp, op >> 4);
	1876	// 1101010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to AY1
	1877	mac_op_mr(op);
	1878	m_core.ax1.u = data_read_dag1(op);
	1879	m_core.ay1.u = pgm_read_dag2(op >> 4);
1610	1880	break;
1611	1881	case 0xd6: case 0xd7:
1612		/* 1101011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to AY1 */
1613		alu_op_ar(adsp, op);
1614		adsp->core.ax1.u = data_read_dag1(adsp, op);
1615		adsp->core.ay1.u = pgm_read_dag2(adsp, op >> 4);
	1882	// 1101011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to AY1
	1883	alu_op_ar(op);
	1884	m_core.ax1.u = data_read_dag1(op);
	1885	m_core.ay1.u = pgm_read_dag2(op >> 4);
1616	1886	break;
1617	1887	case 0xd8: case 0xd9:
1618		/* 1101100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to AY1 */
1619		mac_op_mr(adsp, op);
1620		adsp->core.mx0.u = data_read_dag1(adsp, op);
1621		adsp->core.ay1.u = pgm_read_dag2(adsp, op >> 4);
	1888	// 1101100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to AY1
	1889	mac_op_mr(op);
	1890	m_core.mx0.u = data_read_dag1(op);
	1891	m_core.ay1.u = pgm_read_dag2(op >> 4);
1622	1892	break;
1623	1893	case 0xda: case 0xdb:
1624		/* 1101101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to AY1 */
1625		alu_op_ar(adsp, op);
1626		adsp->core.mx0.u = data_read_dag1(adsp, op);
1627		adsp->core.ay1.u = pgm_read_dag2(adsp, op >> 4);
	1894	// 1101101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to AY1
	1895	alu_op_ar(op);
	1896	m_core.mx0.u = data_read_dag1(op);
	1897	m_core.ay1.u = pgm_read_dag2(op >> 4);
1628	1898	break;
1629	1899	case 0xdc: case 0xdd:
1630		/* 1101110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to AY1 */
1631		mac_op_mr(adsp, op);
1632		adsp->core.mx1.u = data_read_dag1(adsp, op);
1633		adsp->core.ay1.u = pgm_read_dag2(adsp, op >> 4);
	1900	// 1101110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to AY1
	1901	mac_op_mr(op);
	1902	m_core.mx1.u = data_read_dag1(op);
	1903	m_core.ay1.u = pgm_read_dag2(op >> 4);
1634	1904	break;
1635	1905	case 0xde: case 0xdf:
1636		/* 1101111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to AY1 */
1637		alu_op_ar(adsp, op);
1638		adsp->core.mx1.u = data_read_dag1(adsp, op);
1639		adsp->core.ay1.u = pgm_read_dag2(adsp, op >> 4);
	1906	// 1101111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to AY1
	1907	alu_op_ar(op);
	1908	m_core.mx1.u = data_read_dag1(op);
	1909	m_core.ay1.u = pgm_read_dag2(op >> 4);
1640	1910	break;
1641	1911	case 0xe0: case 0xe1:
1642		/* 1110000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to MY0 */
1643		mac_op_mr(adsp, op);
1644		adsp->core.ax0.u = data_read_dag1(adsp, op);
1645		adsp->core.my0.u = pgm_read_dag2(adsp, op >> 4);
	1912	// 1110000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to MY0
	1913	mac_op_mr(op);
	1914	m_core.ax0.u = data_read_dag1(op);
	1915	m_core.my0.u = pgm_read_dag2(op >> 4);
1646	1916	break;
1647	1917	case 0xe2: case 0xe3:
1648		/* 1110001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to MY0 */
1649		alu_op_ar(adsp, op);
1650		adsp->core.ax0.u = data_read_dag1(adsp, op);
1651		adsp->core.my0.u = pgm_read_dag2(adsp, op >> 4);
	1918	// 1110001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to MY0
	1919	alu_op_ar(op);
	1920	m_core.ax0.u = data_read_dag1(op);
	1921	m_core.my0.u = pgm_read_dag2(op >> 4);
1652	1922	break;
1653	1923	case 0xe4: case 0xe5:
1654		/* 1110010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to MY0 */
1655		mac_op_mr(adsp, op);
1656		adsp->core.ax1.u = data_read_dag1(adsp, op);
1657		adsp->core.my0.u = pgm_read_dag2(adsp, op >> 4);
	1924	// 1110010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to MY0
	1925	mac_op_mr(op);
	1926	m_core.ax1.u = data_read_dag1(op);
	1927	m_core.my0.u = pgm_read_dag2(op >> 4);
1658	1928	break;
1659	1929	case 0xe6: case 0xe7:
1660		/* 1110011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to MY0 */
1661		alu_op_ar(adsp, op);
1662		adsp->core.ax1.u = data_read_dag1(adsp, op);
1663		adsp->core.my0.u = pgm_read_dag2(adsp, op >> 4);
	1930	// 1110011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to MY0
	1931	alu_op_ar(op);
	1932	m_core.ax1.u = data_read_dag1(op);
	1933	m_core.my0.u = pgm_read_dag2(op >> 4);
1664	1934	break;
1665	1935	case 0xe8: case 0xe9:
1666		/* 1110100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to MY0 */
1667		mac_op_mr(adsp, op);
1668		adsp->core.mx0.u = data_read_dag1(adsp, op);
1669		adsp->core.my0.u = pgm_read_dag2(adsp, op >> 4);
	1936	// 1110100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to MY0
	1937	mac_op_mr(op);
	1938	m_core.mx0.u = data_read_dag1(op);
	1939	m_core.my0.u = pgm_read_dag2(op >> 4);
1670	1940	break;
1671	1941	case 0xea: case 0xeb:
1672		/* 1110101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to MY0 */
1673		alu_op_ar(adsp, op);
1674		adsp->core.mx0.u = data_read_dag1(adsp, op);
1675		adsp->core.my0.u = pgm_read_dag2(adsp, op >> 4);
	1942	// 1110101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to MY0
	1943	alu_op_ar(op);
	1944	m_core.mx0.u = data_read_dag1(op);
	1945	m_core.my0.u = pgm_read_dag2(op >> 4);
1676	1946	break;
1677	1947	case 0xec: case 0xed:
1678		/* 1110110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to MY0 */
1679		mac_op_mr(adsp, op);
1680		adsp->core.mx1.u = data_read_dag1(adsp, op);
1681		adsp->core.my0.u = pgm_read_dag2(adsp, op >> 4);
	1948	// 1110110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to MY0
	1949	mac_op_mr(op);
	1950	m_core.mx1.u = data_read_dag1(op);
	1951	m_core.my0.u = pgm_read_dag2(op >> 4);
1682	1952	break;
1683	1953	case 0xee: case 0xef:
1684		/* 1110111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to MY0 */
1685		alu_op_ar(adsp, op);
1686		adsp->core.mx1.u = data_read_dag1(adsp, op);
1687		adsp->core.my0.u = pgm_read_dag2(adsp, op >> 4);
	1954	// 1110111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to MY0
	1955	alu_op_ar(op);
	1956	m_core.mx1.u = data_read_dag1(op);
	1957	m_core.my0.u = pgm_read_dag2(op >> 4);
1688	1958	break;
1689	1959	case 0xf0: case 0xf1:
1690		/* 1111000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to MY1 */
1691		mac_op_mr(adsp, op);
1692		adsp->core.ax0.u = data_read_dag1(adsp, op);
1693		adsp->core.my1.u = pgm_read_dag2(adsp, op >> 4);
	1960	// 1111000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to MY1
	1961	mac_op_mr(op);
	1962	m_core.ax0.u = data_read_dag1(op);
	1963	m_core.my1.u = pgm_read_dag2(op >> 4);
1694	1964	break;
1695	1965	case 0xf2: case 0xf3:
1696		/* 1111001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to MY1 */
1697		alu_op_ar(adsp, op);
1698		adsp->core.ax0.u = data_read_dag1(adsp, op);
1699		adsp->core.my1.u = pgm_read_dag2(adsp, op >> 4);
	1966	// 1111001x xxxxxxxx xxxxxxxx ALU to AR with data read to AX0 & pgm read to MY1
	1967	alu_op_ar(op);
	1968	m_core.ax0.u = data_read_dag1(op);
	1969	m_core.my1.u = pgm_read_dag2(op >> 4);
1700	1970	break;
1701	1971	case 0xf4: case 0xf5:
1702		/* 1111010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to MY1 */
1703		mac_op_mr(adsp, op);
1704		adsp->core.ax1.u = data_read_dag1(adsp, op);
1705		adsp->core.my1.u = pgm_read_dag2(adsp, op >> 4);
	1972	// 1111010x xxxxxxxx xxxxxxxx MAC to MR with data read to AX1 & pgm read to MY1
	1973	mac_op_mr(op);
	1974	m_core.ax1.u = data_read_dag1(op);
	1975	m_core.my1.u = pgm_read_dag2(op >> 4);
1706	1976	break;
1707	1977	case 0xf6: case 0xf7:
1708		/* 1111011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to MY1 */
1709		alu_op_ar(adsp, op);
1710		adsp->core.ax1.u = data_read_dag1(adsp, op);
1711		adsp->core.my1.u = pgm_read_dag2(adsp, op >> 4);
	1978	// 1111011x xxxxxxxx xxxxxxxx ALU to AR with data read to AX1 & pgm read to MY1
	1979	alu_op_ar(op);
	1980	m_core.ax1.u = data_read_dag1(op);
	1981	m_core.my1.u = pgm_read_dag2(op >> 4);
1712	1982	break;
1713	1983	case 0xf8: case 0xf9:
1714		/* 1111100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to MY1 */
1715		mac_op_mr(adsp, op);
1716		adsp->core.mx0.u = data_read_dag1(adsp, op);
1717		adsp->core.my1.u = pgm_read_dag2(adsp, op >> 4);
	1984	// 1111100x xxxxxxxx xxxxxxxx MAC to MR with data read to MX0 & pgm read to MY1
	1985	mac_op_mr(op);
	1986	m_core.mx0.u = data_read_dag1(op);
	1987	m_core.my1.u = pgm_read_dag2(op >> 4);
1718	1988	break;
1719	1989	case 0xfa: case 0xfb:
1720		/* 1111101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to MY1 */
1721		alu_op_ar(adsp, op);
1722		adsp->core.mx0.u = data_read_dag1(adsp, op);
1723		adsp->core.my1.u = pgm_read_dag2(adsp, op >> 4);
	1990	// 1111101x xxxxxxxx xxxxxxxx ALU to AR with data read to MX0 & pgm read to MY1
	1991	alu_op_ar(op);
	1992	m_core.mx0.u = data_read_dag1(op);
	1993	m_core.my1.u = pgm_read_dag2(op >> 4);
1724	1994	break;
1725	1995	case 0xfc: case 0xfd:
1726		/* 1111110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to MY1 */
1727		mac_op_mr(adsp, op);
1728		adsp->core.mx1.u = data_read_dag1(adsp, op);
1729		adsp->core.my1.u = pgm_read_dag2(adsp, op >> 4);
	1996	// 1111110x xxxxxxxx xxxxxxxx MAC to MR with data read to MX1 & pgm read to MY1
	1997	mac_op_mr(op);
	1998	m_core.mx1.u = data_read_dag1(op);
	1999	m_core.my1.u = pgm_read_dag2(op >> 4);
1730	2000	break;
1731	2001	case 0xfe: case 0xff:
1732		/* 1111111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to MY1 */
1733		alu_op_ar(adsp, op);
1734		adsp->core.mx1.u = data_read_dag1(adsp, op);
1735		adsp->core.my1.u = pgm_read_dag2(adsp, op >> 4);
	2002	// 1111111x xxxxxxxx xxxxxxxx ALU to AR with data read to MX1 & pgm read to MY1
	2003	alu_op_ar(op);
	2004	m_core.mx1.u = data_read_dag1(op);
	2005	m_core.my1.u = pgm_read_dag2(op >> 4);
1736	2006	break;
1737	2007	}
1738	2008
1739		adsp->icount--;
1740		} while (adsp->icount > 0);
	2009	m_icount--;
	2010	} while (m_icount > 0);
1741	2011	}
1742
1743
1744
1745		/***************************************************************************
1746		DEBUGGER DEFINITIONS
1747		***************************************************************************/
1748
1749		extern CPU_DISASSEMBLE( adsp21xx );
1750
1751
1752
1753		/***************************************************************************
1754		STATE HANDLING CALLBACKS
1755		***************************************************************************/
1756
1757		static CPU_IMPORT_STATE( adsp21xx )
1758		{
1759		adsp2100_state *adsp = get_safe_token(device);
1760		switch (entry.index())
1761		{
1762		case ADSP2100_MSTAT:
1763		update_mstat(adsp);
1764		break;
1765
1766		case ADSP2100_IMASK:
1767		case ADSP2100_ICNTL:
1768		case ADSP2100_IRQSTATE0:
1769		case ADSP2100_IRQSTATE1:
1770		case ADSP2100_IRQSTATE2:
1771		case ADSP2100_IRQSTATE3:
1772		check_irqs(adsp);
1773		break;
1774
1775		case ADSP2100_I0:
1776		case ADSP2100_I1:
1777		case ADSP2100_I2:
1778		case ADSP2100_I3:
1779		case ADSP2100_I4:
1780		case ADSP2100_I5:
1781		case ADSP2100_I6:
1782		case ADSP2100_I7:
1783		update_i(adsp, entry.index() - ADSP2100_I0);
1784		break;
1785
1786		case ADSP2100_L0:
1787		case ADSP2100_L1:
1788		case ADSP2100_L2:
1789		case ADSP2100_L3:
1790		case ADSP2100_L4:
1791		case ADSP2100_L5:
1792		case ADSP2100_L6:
1793		case ADSP2100_L7:
1794		update_l(adsp, entry.index() - ADSP2100_L0);
1795		break;
1796
1797		default:
1798		fatalerror("CPU_IMPORT_STATE(adsp21xx) called for unexpected value\n");
1799		break;
1800		}
1801		}
1802
1803
1804		static CPU_EXPORT_STRING( adsp21xx )
1805		{
1806		adsp2100_state *adsp = get_safe_token(device);
1807
1808		switch (entry.index())
1809		{
1810		case STATE_GENFLAGS:
1811		string.printf("%c%c%c%c%c%c%c%c",
1812		adsp->astat & 0x80 ? 'X':'.',
1813		adsp->astat & 0x40 ? 'M':'.',
1814		adsp->astat & 0x20 ? 'Q':'.',
1815		adsp->astat & 0x10 ? 'S':'.',
1816		adsp->astat & 0x08 ? 'C':'.',
1817		adsp->astat & 0x04 ? 'V':'.',
1818		adsp->astat & 0x02 ? 'N':'.',
1819		adsp->astat & 0x01 ? 'Z':'.');
1820		break;
1821		}
1822		}
1823
1824
1825
1826
1827		/**************************************************************************
1828		* Generic set_info
1829		**************************************************************************/
1830
1831		static CPU_SET_INFO( adsp21xx )
1832		{
1833		adsp2100_state *adsp = get_safe_token(device);
1834		switch (state)
1835		{
1836		/* --- the following bits of info are set as 64-bit signed integers --- */
1837		case CPUINFO_INT_INPUT_STATE + 0:
1838		case CPUINFO_INT_INPUT_STATE + 1:
1839		case CPUINFO_INT_INPUT_STATE + 2:
1840		case CPUINFO_INT_INPUT_STATE + 3:
1841		case CPUINFO_INT_INPUT_STATE + 4:
1842		case CPUINFO_INT_INPUT_STATE + 5:
1843		case CPUINFO_INT_INPUT_STATE + 6:
1844		case CPUINFO_INT_INPUT_STATE + 7:
1845		case CPUINFO_INT_INPUT_STATE + 8:
1846		case CPUINFO_INT_INPUT_STATE + 9:
1847		set_irq_line(adsp, state - CPUINFO_INT_INPUT_STATE, info->i);
1848		break;
1849		}
1850		}
1851
1852
1853
1854		/**************************************************************************
1855		* Generic get_info
1856		**************************************************************************/
1857
1858		static CPU_GET_INFO( adsp21xx )
1859		{
1860		adsp2100_state *adsp = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
1861		switch (state)
1862		{
1863		/* --- the following bits of info are returned as 64-bit signed integers --- */
1864		case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(adsp2100_state); break;
1865		case CPUINFO_INT_INPUT_LINES: /* set per CPU */ break;
1866		case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
1867		case DEVINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
1868		case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
1869		case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
1870		case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break;
1871		case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
1872		case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
1873		case CPUINFO_INT_MAX_CYCLES: info->i = 1; break;
1874
1875		case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break;
1876		case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 14; break;
1877		case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = -2; break;
1878		case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 16; break;
1879		case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 14; break;
1880		case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = -1; break;
1881
1882		case CPUINFO_INT_INPUT_STATE + 0:
1883		case CPUINFO_INT_INPUT_STATE + 1:
1884		case CPUINFO_INT_INPUT_STATE + 2:
1885		case CPUINFO_INT_INPUT_STATE + 3:
1886		case CPUINFO_INT_INPUT_STATE + 4:
1887		case CPUINFO_INT_INPUT_STATE + 5:
1888		case CPUINFO_INT_INPUT_STATE + 6:
1889		case CPUINFO_INT_INPUT_STATE + 7:
1890		case CPUINFO_INT_INPUT_STATE + 8:
1891		case CPUINFO_INT_INPUT_STATE + 9:
1892		info->i = adsp->irq_state[state - CPUINFO_INT_INPUT_STATE];
1893		break;
1894
1895		/* --- the following bits of info are returned as pointers to functions --- */
1896		case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(adsp21xx); break;
1897		case CPUINFO_FCT_INIT: /* set per CPU */ break;
1898		case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(adsp21xx); break;
1899		case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(adsp21xx); break;
1900		case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(adsp21xx); break;
1901		case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(adsp21xx); break;
1902		case CPUINFO_FCT_IMPORT_STATE: info->import_state = CPU_IMPORT_STATE_NAME(adsp21xx); break;
1903		case CPUINFO_FCT_EXPORT_STRING: info->export_string = CPU_EXPORT_STRING_NAME(adsp21xx); break;
1904
1905		/* --- the following bits of info are returned as pointers --- */
1906		case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &adsp->icount; break;
1907
1908		/* --- the following bits of info are returned as NULL-terminated strings --- */
1909		case DEVINFO_STR_NAME: /* set per CPU */ break;
1910		case DEVINFO_STR_FAMILY: strcpy(info->s, "ADSP21xx"); break;
1911		case DEVINFO_STR_VERSION: strcpy(info->s, "2.0"); break;
1912		case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
1913		case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright Aaron Giles"); break;
1914		}
1915		}
1916
1917		static void adsp21xx_load_boot_data(UINT8 srcdata, UINT32 dstdata)
1918		{
1919		/* see how many words we need to copy */
1920		int pagelen = (srcdata[(3)] + 1) * 8;
1921		int i;
1922		for (i = 0; i < pagelen; i++)
1923		{
1924		UINT32 opcode = (srcdata[(i4+0)] << 16) \| (srcdata[(i4+1)] << 8) \| srcdata[(i*4+2)];
1925		dstdata[i] = opcode;
1926		}
1927		}
1928
1929
1930		/**************************************************************************
1931		* ADSP2100 section
1932		**************************************************************************/
1933
1934		static CPU_INIT( adsp2100 )
1935		{
1936		adsp2100_state *adsp = adsp21xx_init(device, irqcallback, CHIP_TYPE_ADSP2100);
1937		adsp->mstat_mask = 0x0f;
1938		adsp->imask_mask = 0x0f;
1939		}
1940
1941		CPU_GET_INFO( adsp2100 )
1942		{
1943		switch (state)
1944		{
1945		/* --- the following bits of info are returned as 64-bit signed integers --- */
1946		case CPUINFO_INT_INPUT_LINES: info->i = 4; break;
1947
1948		/* --- the following bits of info are returned as pointers to data or functions --- */
1949		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(adsp2100); break;
1950
1951		/* --- the following bits of info are returned as NULL-terminated strings --- */
1952		case DEVINFO_STR_NAME: strcpy(info->s, "ADSP2100"); break;
1953
1954		default:
1955		CPU_GET_INFO_CALL(adsp21xx);
1956		break;
1957		}
1958		}
1959
1960		/**************************************************************************
1961		* ADSP2101 section
1962		**************************************************************************/
1963
1964		static CPU_INIT( adsp2101 )
1965		{
1966		adsp2100_state *adsp = adsp21xx_init(device, irqcallback, CHIP_TYPE_ADSP2101);
1967		adsp->mstat_mask = 0x7f;
1968		adsp->imask_mask = 0x3f;
1969		}
1970
1971		CPU_GET_INFO( adsp2101 )
1972		{
1973		switch (state)
1974		{
1975		/* --- the following bits of info are returned as 64-bit signed integers --- */
1976		case CPUINFO_INT_INPUT_LINES: info->i = 5; break;
1977
1978		/* --- the following bits of info are returned as pointers to data or functions --- */
1979		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(adsp2101); break;
1980
1981		/* --- the following bits of info are returned as NULL-terminated strings --- */
1982		case DEVINFO_STR_NAME: strcpy(info->s, "ADSP2101"); break;
1983
1984		default:
1985		CPU_GET_INFO_CALL(adsp21xx);
1986		break;
1987		}
1988		}
1989
1990		/**************************************************************************
1991		* ADSP2104 section
1992		**************************************************************************/
1993
1994		static CPU_INIT( adsp2104 )
1995		{
1996		adsp2100_state *adsp = adsp21xx_init(device, irqcallback, CHIP_TYPE_ADSP2104);
1997		adsp->mstat_mask = 0x7f;
1998		adsp->imask_mask = 0x3f;
1999		}
2000
2001		void adsp2104_load_boot_data(UINT8 srcdata, UINT32 dstdata)
2002		{
2003		adsp21xx_load_boot_data(srcdata, dstdata);
2004		}
2005
2006		CPU_GET_INFO( adsp2104 )
2007		{
2008		switch (state)
2009		{
2010		/* --- the following bits of info are returned as 64-bit signed integers --- */
2011		case CPUINFO_INT_INPUT_LINES: info->i = 6; break;
2012
2013		/* --- the following bits of info are returned as pointers to data or functions --- */
2014		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(adsp2104); break;
2015
2016		/* --- the following bits of info are returned as NULL-terminated strings --- */
2017		case DEVINFO_STR_NAME: strcpy(info->s, "ADSP2104"); break;
2018
2019		default:
2020		CPU_GET_INFO_CALL(adsp21xx);
2021		break;
2022		}
2023		}
2024
2025		/**************************************************************************
2026		* ADSP2105 section
2027		**************************************************************************/
2028
2029		static CPU_INIT( adsp2105 )
2030		{
2031		adsp2100_state *adsp = adsp21xx_init(device, irqcallback, CHIP_TYPE_ADSP2105);
2032		adsp->mstat_mask = 0x7f;
2033		adsp->imask_mask = 0x3f;
2034		}
2035
2036		void adsp2105_load_boot_data(UINT8 srcdata, UINT32 dstdata)
2037		{
2038		adsp21xx_load_boot_data(srcdata, dstdata);
2039		}
2040
2041		CPU_GET_INFO( adsp2105 )
2042		{
2043		switch (state)
2044		{
2045		/* --- the following bits of info are returned as 64-bit signed integers --- */
2046		case CPUINFO_INT_INPUT_LINES: info->i = 3; break;
2047
2048		/* --- the following bits of info are returned as pointers to data or functions --- */
2049		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(adsp2105); break;
2050
2051		/* --- the following bits of info are returned as NULL-terminated strings --- */
2052		case DEVINFO_STR_NAME: strcpy(info->s, "ADSP2105"); break;
2053
2054		default:
2055		CPU_GET_INFO_CALL(adsp21xx);
2056		break;
2057		}
2058		}
2059
2060		/**************************************************************************
2061		* ADSP2115 section
2062		**************************************************************************/
2063
2064		static CPU_INIT( adsp2115 )
2065		{
2066		adsp2100_state *adsp = adsp21xx_init(device, irqcallback, CHIP_TYPE_ADSP2115);
2067		adsp->mstat_mask = 0x7f;
2068		adsp->imask_mask = 0x3f;
2069		}
2070
2071		void adsp2115_load_boot_data(UINT8 srcdata, UINT32 dstdata)
2072		{
2073		adsp21xx_load_boot_data(srcdata, dstdata);
2074		}
2075
2076		CPU_GET_INFO( adsp2115 )
2077		{
2078		switch (state)
2079		{
2080		/* --- the following bits of info are returned as 64-bit signed integers --- */
2081		case CPUINFO_INT_INPUT_LINES: info->i = 6; break;
2082
2083		/* --- the following bits of info are returned as pointers to data or functions --- */
2084		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(adsp2115); break;
2085
2086		/* --- the following bits of info are returned as NULL-terminated strings --- */
2087		case DEVINFO_STR_NAME: strcpy(info->s, "ADSP2115"); break;
2088
2089		default:
2090		CPU_GET_INFO_CALL(adsp21xx);
2091		break;
2092		}
2093		}
2094
2095		/**************************************************************************
2096		* ADSP2181 section
2097		**************************************************************************/
2098
2099		static CPU_INIT( adsp2181 )
2100		{
2101		adsp2100_state *adsp = adsp21xx_init(device, irqcallback, CHIP_TYPE_ADSP2181);
2102		adsp->mstat_mask = 0x7f;
2103		adsp->imask_mask = 0x3ff;
2104		}
2105
2106		void adsp2181_load_boot_data(UINT8 srcdata, UINT32 dstdata)
2107		{
2108		adsp21xx_load_boot_data(srcdata, dstdata);
2109		}
2110
2111		CPU_GET_INFO( adsp2181 )
2112		{
2113		switch (state)
2114		{
2115		/* --- the following bits of info are returned as 64-bit signed integers --- */
2116		case CPUINFO_INT_INPUT_LINES: info->i = 9; break;
2117
2118		case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 16; break;
2119		case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 11; break;
2120		case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = -1; break;
2121
2122		/* --- the following bits of info are returned as pointers to data or functions --- */
2123		case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(adsp2181); break;
2124
2125		/* --- the following bits of info are returned as NULL-terminated strings --- */
2126		case DEVINFO_STR_NAME: strcpy(info->s, "ADSP2181"); break;
2127
2128		default:
2129		CPU_GET_INFO_CALL(adsp21xx);
2130		break;
2131		}
2132		}
2133
2134		void adsp2181_idma_addr_w(running_device *device, UINT16 data)
2135		{
2136		adsp2100_state *adsp = get_safe_token(device);
2137		adsp->idma_addr = data;
2138		adsp->idma_offs = 0;
2139		}
2140
2141		UINT16 adsp2181_idma_addr_r(running_device *device)
2142		{
2143		adsp2100_state *adsp = get_safe_token(device);
2144		return adsp->idma_addr;
2145		}
2146
2147		void adsp2181_idma_data_w(running_device *device, UINT16 data)
2148		{
2149		adsp2100_state *adsp = get_safe_token(device);
2150
2151		/* program memory? */
2152		if (!(adsp->idma_addr & 0x4000))
2153		{
2154		/* upper 16 bits */
2155		if (adsp->idma_offs == 0)
2156		{
2157		adsp->idma_cache = data;
2158		adsp->idma_offs = 1;
2159		}
2160
2161		/* lower 8 bits */
2162		else
2163		{
2164		WWORD_PGM(adsp, adsp->idma_addr++ & 0x3fff, (adsp->idma_cache << 8) \| (data & 0xff));
2165		adsp->idma_offs = 0;
2166		}
2167		}
2168
2169		/* data memory */
2170		else
2171		WWORD_DATA(adsp, adsp->idma_addr++ & 0x3fff, data);
2172		}
2173
2174		UINT16 adsp2181_idma_data_r(running_device *device)
2175		{
2176		adsp2100_state *adsp = get_safe_token(device);
2177		UINT16 result = 0xffff;
2178
2179		/* program memory? */
2180		if (!(adsp->idma_addr & 0x4000))
2181		{
2182		/* upper 16 bits */
2183		if (adsp->idma_offs == 0)
2184		{
2185		result = RWORD_PGM(adsp, adsp->idma_addr & 0x3fff) >> 8;
2186		adsp->idma_offs = 1;
2187		}
2188
2189		/* lower 8 bits */
2190		else
2191		{
2192		result = RWORD_PGM(adsp, adsp->idma_addr++ & 0x3fff) & 0xff;
2193		adsp->idma_offs = 0;
2194		}
2195		}
2196
2197		/* data memory */
2198		else
2199		result = RWORD_DATA(adsp, adsp->idma_addr++ & 0x3fff);
2200
2201		return result;
2202		}
2203
2204		DEFINE_LEGACY_CPU_DEVICE(ADSP2100, adsp2100);
2205		DEFINE_LEGACY_CPU_DEVICE(ADSP2101, adsp2101);
2206		DEFINE_LEGACY_CPU_DEVICE(ADSP2104, adsp2104);
2207		DEFINE_LEGACY_CPU_DEVICE(ADSP2105, adsp2105);
2208		DEFINE_LEGACY_CPU_DEVICE(ADSP2115, adsp2115);
2209		DEFINE_LEGACY_CPU_DEVICE(ADSP2181, adsp2181);

src/emu/cpu/asap/asap.c
r9081	r9082
189	189	return auto_alloc(&machine, asap_device(machine, *this));
190	190	}
191	191
	192
192	193	//-------------------------------------------------
193	194	// execute_min_cycles - return minimum number of
194	195	// cycles it takes for one instruction to execute
r9081	r9082
421	422
422	423	offs_t asap_device::disasm_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 options)
423	424	{
424		extern offs_t asap_disassemble(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram);
425		return asap_disassemble(buffer, pc, oprom, opram);
	425	extern CPU_DISASSEMBLE( asap );
	426	return CPU_DISASSEMBLE_NAME(asap)(NULL, buffer, pc, oprom, opram, 0);
426	427	}
427	428
428	429

src/emu/cpu/asap/asap.h
r9081	r9082
63	63	static device_config static_alloc_device_config(const machine_config &mconfig, const char tag, const device_config *owner, UINT32 clock);
64	64	virtual device_t *alloc_device(running_machine &machine) const;
65	65
66		// inline configuration helpers
67		static void static_set_pin7(device_config *device, int pin7);
68
69	66	protected:
70	67	// device_config_execute_interface overrides
71	68	virtual UINT32 execute_min_cycles() const;

src/emu/cpu/asap/asapdasm.c
r9081	r9082
43	43	return temp;
44	44	}
45	45
46		~~offs~~_t asap~~_disassemble(char~~ buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram)
	46	CPU_DISASSEMBLE( asap )
47	47	{
48	48	UINT32 op = oprom[0] \| (oprom[1] << 8) \| (oprom[2] << 16) \| (oprom[3] << 24);
49	49	int opcode = op >> 27;

src/emu/video/pc_video.c
r9081	r9082
48	48	pc_current_width = -1;
49	49	machine->generic.tmpbitmap = NULL;
50	50
51		machine->generic.videoram_size = vramsize;
52
53		if (machine->generic.videoram_size)
	51	if (vramsize)
54	52	{
55	53	video_start_generic_bitmapped(machine);
56	54	}
r9081	r9082
102	100	}
103	101	return rc;
104	102	}
105
106
107
108		WRITE8_HANDLER ( pc_video_videoram_w )
109		{
110		if (space->machine->generic.videoram.u8 && space->machine->generic.videoram.u8[offset] != data)
111		{
112		space->machine->generic.videoram.u8[offset] = data;
113		pc_anythingdirty = 1;
114		}
115		}
116
117
118		WRITE16_HANDLER( pc_video_videoram16le_w ) { write16le_with_write8_handler(pc_video_videoram_w, space, offset, data, mem_mask); }
119
120		WRITE32_HANDLER( pc_video_videoram32_w )
121		{
122		COMBINE_DATA(space->machine->generic.videoram.u32 + offset);
123		pc_anythingdirty = 1;
124		}

src/emu/video/pc_video.h
r9081	r9082
17	17
18	18	VIDEO_UPDATE( pc_video );
19	19
20		WRITE8_HANDLER( pc_video_videoram_w );
21		WRITE16_HANDLER( pc_video_videoram16le_w );
22		WRITE32_HANDLER( pc_video_videoram32_w );
23
24	20	#endif /* PC_VIDEO_H */

src/emu/devintrf.c
r9081	r9082
285	285	// device configuration
286	286	//-------------------------------------------------
287	287
288		device_config::device_config(const machine_config &mconfig, device_type type, const char name, const char tag, const device_config *owner, UINT32 clock)
	288	device_config::device_config(const machine_config &mconfig, device_type type, const char name, const char tag, const device_config *owner, UINT32 clock, UINT32 param)
289	289	: m_next(NULL),
290	290	m_owner(const_cast<device_config *>(owner)),
291	291	m_interface_list(NULL),

src/emu/devintrf.h
r9081	r9082
58	58	// shorthand for accessing devices by machine/type/tag
59	59	#define devtag_reset(mach,tag) (mach)->device(tag)->reset()
60	60
	61	// often derived devices need only a different name and a simple parameter to differentiate them
	62	// these are provided as macros because you can't pass string literals to templates, annoyingly enough
	63	// use this to declare the existence of a derived device in the header file
	64	#define DECLARE_TRIVIAL_DERIVED_DEVICE(_ConfigClass, _ConfigBase, _DeviceClass, _DeviceBase) \
	65	typedef _DeviceBase _DeviceClass; \
	66	class _ConfigClass; \
	67	\
	68	class _ConfigClass : public _ConfigBase \
	69	{ \
	70	protected: \
	71	_ConfigClass(const machine_config &mconfig, const char tag, const device_config owner, UINT32 clock, UINT32 param = 0); \
	72	\
	73	public: \
	74	static device_config static_alloc_device_config(const machine_config &mconfig, const char tag, const device_config *owner, UINT32 clock); \
	75	virtual device_t *alloc_device(running_machine &machine) const; \
	76	}; \
61	77
	78	// use this macro to define the actual implementation in the source file
	79	#define DEFINE_TRIVIAL_DERIVED_DEVICE(_ConfigClass, _ConfigBase, _DeviceClass, _DeviceBase, _Name, _Param) \
	80	_ConfigClass::_ConfigClass(const machine_config &mconfig, const char tag, const device_config owner, UINT32 clock, UINT32 param) \
	81	: _ConfigBase(mconfig, static_alloc_device_config, _Name, tag, owner, clock, param) \
	82	{ \
	83	} \
	84	\
	85	device_config _ConfigClass::static_alloc_device_config(const machine_config &mconfig, const char tag, const device_config *owner, UINT32 clock) \
	86	{ \
	87	return global_alloc(_ConfigClass(mconfig, tag, owner, clock, _Param)); \
	88	} \
	89	\
	90	device_t *_ConfigClass::alloc_device(running_machine &machine) const \
	91	{ \
	92	return auto_alloc(&machine, _DeviceClass(machine, *this)); \
	93	} \
62	94
	95
	96
63	97	//**************************************************************************
64	98	// DEVICE CONFIGURATION MACROS
65	99	//**************************************************************************
r9081	r9082
218	252
219	253	protected:
220	254	// construction/destruction
221		device_config(const machine_config &mconfig, device_type type, const char name, const char tag, const device_config *owner, UINT32 clock);
	255	device_config(const machine_config &mconfig, device_type type, const char name, const char tag, const device_config *owner, UINT32 clock, UINT32 param = 0);
222	256	virtual ~device_config();
223	257
224	258	public:

src/emu/disound.c
r9081	r9082
190	190
191	191
192	192	//-------------------------------------------------
	193	// interface_pre_start - make sure all our input
	194	// devices are started
	195	//-------------------------------------------------
	196
	197	void device_sound_interface::interface_pre_start()
	198	{
	199	// scan all the sound devices
	200	device_sound_interface *sound = NULL;
	201	for (bool gotone = m_device.machine->m_devicelist.first(sound); gotone; gotone = sound->next(sound))
	202	{
	203	// scan each route on the device
	204	for (const device_config_sound_interface::sound_route *route = sound->sound_config().m_route_list; route != NULL; route = route->m_next)
	205	{
	206	// if we are the target of this route but the source hasn't yet started, defer our start for later
	207	device_t *target_device = m_device.machine->device(route->m_target);
	208	if (target_device == &m_device && !sound->device().started())
	209	throw device_missing_dependencies();
	210	}
	211	}
	212	}
	213
	214
	215	//-------------------------------------------------
193	216	// interface_post_start - verify that state was
194	217	// properly set up
195	218	//-------------------------------------------------
r9081	r9082
216	239	output->output = curoutput;
217	240	}
218	241	}
	242
	243	// iterate over all the sound devices
	244	device_sound_interface *sound = NULL;
	245	for (bool gotone = m_device.machine->m_devicelist.first(sound); gotone; gotone = sound->next(sound))
	246	{
	247	// scan each route on the device
	248	for (const device_config_sound_interface::sound_route *route = sound->sound_config().m_route_list; route != NULL; route = route->m_next)
	249	{
	250	// if we are the target of this route, hook it up
	251	device_t *target_device = m_device.machine->device(route->m_target);
	252	if (target_device == &m_device)
	253	{
	254	// iterate over all outputs, matching any that apply
	255	int inputnum = route->m_input;
	256	int numoutputs = stream_get_device_outputs(*sound);
	257	for (int outputnum = 0; outputnum < numoutputs; outputnum++)
	258	if (route->m_output == outputnum \|\| route->m_output == ALL_OUTPUTS)
	259	{
	260	sound_stream inputstream, stream;
	261	int streaminput, streamoutput;
	262
	263	// get the input and output streams and wire them together
	264	if (stream_device_input_to_stream_input(target_device, inputnum++, &inputstream, &streaminput))
	265	if (stream_device_output_to_stream_output(*sound, outputnum, &stream, &streamoutput))
	266	stream_set_input(inputstream, streaminput, stream, streamoutput, route->m_gain);
	267	}
	268	}
	269	}
	270	}
219	271	}

src/emu/disound.h
r9081	r9082
144	144
145	145	protected:
146	146	// optional operation overrides
	147	virtual void interface_pre_start();
147	148	virtual void interface_post_start();
148	149
149	150	struct sound_output

src/emu/sound.c
r9081	r9082
73	73	static void sound_load(running_machine machine, int config_type, xml_data_node parentnode);
74	74	static void sound_save(running_machine machine, int config_type, xml_data_node parentnode);
75	75	static TIMER_CALLBACK( sound_update );
76		static void route_sound(running_machine *machine);
77	76
78	77
79	78
r9081	r9082
137	136	global->update_timer = timer_alloc(machine, sound_update, NULL);
138	137	timer_adjust_periodic(global->update_timer, STREAMS_UPDATE_ATTOTIME, 0, STREAMS_UPDATE_ATTOTIME);
139	138
140		/* finally, do all the routing */
141		VPRINTF(("route_sound\n"));
142		route_sound(machine);
143
144	139	/* open the output WAV file if specified */
145	140	filename = options_get_string(machine->options(), OPTION_WAVWRITE);
146	141	if (filename[0] != 0)
r9081	r9082
180	175
181	176
182	177	/***************************************************************************
183		INITIALIZATION HELPERS
184		***************************************************************************/
185
186		/*-------------------------------------------------
187		route_sound - route sound outputs to target
188		inputs
189		-------------------------------------------------*/
190
191		static void route_sound(running_machine *machine)
192		{
193		/* iterate again over all the sound chips */
194		device_sound_interface *sound = NULL;
195		for (bool gotone = machine->m_devicelist.first(sound); gotone; gotone = sound->next(sound))
196		{
197		int numoutputs = stream_get_device_outputs(*sound);
198
199		/* iterate over all routes */
200		for (const device_config_sound_interface::sound_route *route = sound->sound_config().m_route_list; route != NULL; route = route->m_next)
201		{
202		device_t *target_device = machine->device(route->m_target);
203		if (target_device->type() == SPEAKER)
204		continue;
205
206		int inputnum = route->m_input;
207
208		/* iterate over all outputs, matching any that apply */
209		for (int outputnum = 0; outputnum < numoutputs; outputnum++)
210		if (route->m_output == outputnum \|\| route->m_output == ALL_OUTPUTS)
211		{
212		sound_stream inputstream, stream;
213		int streaminput, streamoutput;
214
215		if (stream_device_input_to_stream_input(target_device, inputnum++, &inputstream, &streaminput))
216		if (stream_device_output_to_stream_output(*sound, outputnum, &stream, &streamoutput))
217		stream_set_input(inputstream, streaminput, stream, streamoutput, route->m_gain);
218		}
219		}
220		}
221		}
222
223
224
225		/***************************************************************************
226	178	GLOBAL STATE MANAGEMENT
227	179	***************************************************************************/
228	180

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