MESS SVN History

15994 Revisions

r895 Thursday 30th August, 2007 at 23:44:41 UTC by Nathan Woods
Updated to MAME 0.118u4 core

[docs]	messnew.txt
[src/emu]	cpuintrf.c memory.c memory.h
[src/emu/cpu]	cpu.mak x86drc.c x86drc.h x86emit.h*
[src/emu/cpu/i386]	i386dasm.c
[src/emu/cpu/mips]	mdrcold.c mips3.c mips3.h mips3com.c mips3com.h mips3drc.c mips3dsm.c
[src/lib/util]	cdrom.h
[src/mame]	mame.mak mamedriv.c
[src/mame/drivers]	aerofgt.c arcadia.c asuka.c cps1.c cubocd32.c dec8.c galaga.c istellar.c* kinst.c m92.c mcr.c mquake.c ninjaw.c plygonet.c spaceg.c superdq.c taito_h.c taito_x.c taitoair.c thayers.c topspeed.c upscope.c warriorb.c
[src/mame/includes]	amiga.h taitoipt.h
[src/mame/machine]	amiga.c cchip.c decocass.c
[src/mame/video]	cps1.c
[src/mess]	mess.mak
[src/osd/windows]	verinfo.c
[src/tools]	chdcd.c chdcd.h chdman.c

src/mame/machine/amiga.c
r894	r895
178	178	static TIMER_CALLBACK( amiga_irq_proc );
179	179	static TIMER_CALLBACK( amiga_blitter_proc );
180	180
	181
	182
181	183	/*************************************
182	184	*
183	185	* Chipmem 16/32 bit access
184	186	*
185	187	*************************************/
186
	188
187	189	UINT16 (*amiga_chip_ram_r)(offs_t offset);
188	190	void (*amiga_chip_ram_w)(offs_t offset, UINT16 data);
189	191
r894	r895
202	204	if ( offset < amiga_chip_ram_size )
203	205	{
204	206	UINT32 dat = amiga_chip_ram32[offset / 4];
205
	207
206	208	if ( offset & 2 )
207	209	return (dat & 0xffff);
208
	210
209	211	return (dat >> 16);
210	212	}
211
	213
212	214	return 0xffff;
213	215	}
214	216
r894	r895
216	218	{
217	219	extern const amiga_machine_interface *amiga_intf;
218	220	offset &= amiga_intf->chip_ram_mask;
219
	221
220	222	if (offset < amiga_chip_ram_size)
221	223	amiga_chip_ram[offset/2] = data;
222	224	}
r894	r895
225	227	{
226	228	extern const amiga_machine_interface *amiga_intf;
227	229	offset &= amiga_intf->chip_ram_mask;
228
	230
229	231	if ( offset < amiga_chip_ram_size )
230	232	{
231	233	UINT32 dat = amiga_chip_ram32[offset / 4];
232
	234
233	235	if ( offset & 2 )
234	236	{
235	237	dat &= 0xffff0000;
r894	r895
240	242	dat &= 0x0000ffff;
241	243	dat \|= ((UINT32)data) << 16;
242	244	}
243
	245
244	246	amiga_chip_ram32[offset / 4] = dat;
245	247	}
246	248	}
r894	r895
257	259	cia6526_interface cia_intf[2];
258	260
259	261	amiga_intf = intf;
260
	262
261	263	/* setup chipmem handlers */
262	264	if ( IS_AGA(intf) )
263	265	{
r894	r895
1314	1316	blitter_setup();
1315	1317	}
1316	1318	break;
1317
	1319
1318	1320	case REG_BLTCON0L: /* ECS-AGA only */
1319	1321	if ( IS_ECS_OR_AGA(amiga_intf) )
1320	1322	{

src/mame/machine/decocass.c
r894	r895
27	27	static UINT8 tape_crc16_lsb[256];
28	28	static UINT8 tape_crc16_msb[256];
29	29
30		static UINT8 (*decocass_dongle_r)(offs_t offset);
31		static void (*decocass_dongle_w)(offs_t offset, UINT8 data);
	30	static read8_handler decocass_dongle_r;
	31	static write8_handler decocass_dongle_w;
32	32
33	33	static UINT8 decocass_reset;
34	34	static UINT8 i8041_p1;

src/mame/machine/cchip.c
r894	r895
69	69	state_save_register_global(cc_port);
70	70	}
71	71
72		WRITE16_HANDLER( cchip1_word_w )
	72	/*************************************
	73	*
	74	* Writes to C-Chip - Important Bits
	75	*
	76	*************************************/
	77
	78	WRITE16_HANDLER( cchip1_ctrl_w )
73	79	{
74		if (offset == 0x600)
	80	/* value 2 is written here */
	81	}
	82
	83	WRITE16_HANDLER( cchip1_bank_w )
	84	{
	85	current_bank = data & 7;
	86	}
	87
	88	WRITE16_HANDLER( cchip1_ram_w )
	89	{
	90	if (current_bank == 0 && offset == 0x03)
75	91	{
76		current_bank = data;
77		}
78		else if (current_bank == 0 && offset == 0x003)
79		{
80	92	cc_port = data;
81	93
82	94	coin_lockout_w(1, data & 0x08);
r894	r895
90	102	}
91	103	}
92	104
93		READ16_HANDLER( cchip1_word_r )
	105
	106	/*************************************
	107	*
	108	* Reads from C-Chip
	109	*
	110	*************************************/
	111
	112	READ16_HANDLER( cchip1_ctrl_r )
94	113	{
95		/* C-Chip ID */
	114	/*
	115	Bit 2 = Error signal
	116	Bit 0 = Ready signal
	117	*/
	118	return 0x01; /* Return 0x05 for C-Chip error */
	119	}
96	120
97		if (offset == 0x401)
98		{
99		return 0x01;
100		}
101
	121	READ16_HANDLER( cchip1_ram_r )
	122	{
102	123	/* Check for input ports */
103
104	124	if (current_bank == 0)
105	125	{
106	126	switch (offset)
107	127	{
108		case 0x000: return readinputport(2);
109		case 0x001: return readinputport(3);
110		case 0x002: return readinputport(4);
111		case 0x003: return cc_port;
	128	case 0x00: return readinputportbytag("IN0"); /* Player 1 controls + START1 */
	129	case 0x01: return readinputportbytag("IN1"); /* Player 2 controls + START2 */
	130	case 0x02: return readinputportbytag("IN2"); /* COINn + SERVICE1 + TILT */
	131	case 0x03: return cc_port;
112	132	}
113	133	}
114	134

src/mame/mamedriv.c
r894	r895
1418	1418	DRIVER( lethalth ) /* (c) 1991 Irem (World) */
1419	1419	DRIVER( thndblst ) /* (c) 1991 Irem (Japan) */
1420	1420	DRIVER( uccops ) /* (c) 1992 Irem (World) */
	1421	DRIVER( uccopsar ) /* (c) 1992 Irem (World) */
1421	1422	DRIVER( uccopsj ) /* (c) 1992 Irem (Japan) */
1422	1423	DRIVER( mysticri ) /* (c) 1992 Irem (World) */
1423	1424	DRIVER( gunhohki ) /* (c) 1992 Irem (Japan) */
r894	r895
2332	2333	DRIVER( ffight ) /* 12/1989 (c) (World) */
2333	2334	DRIVER( ffightu ) /* 12/1989 (c) (US) */
2334	2335	DRIVER( ffightua ) /* 12/1989 (c) (US) */
	2336	DRIVER( ffightub ) /* 12/1989 (c) (US) */
2335	2337	DRIVER( ffightj ) /* 12/1989 (c) (Japan) */
2336	2338	DRIVER( ffightj1 ) /* 12/1989 (c) (Japan) */
2337	2339	DRIVER( 1941 ) /* 2/1990 (c) 1990 (World) */
r894	r895
7692	7694	DRIVER( kingpinm ) /* (c) 1983 American Communications Laboratories Inc. */
7693	7695	DRIVER( thayers ) /* (c) 1983 RDI Video Systems */
7694	7696	DRIVER( thayersa ) /* (c) 1983 RDI Video Systems */
	7697	DRIVER( istellar ) /* (c) 1983 Funai / Gakken */
7695	7698
7696	7699	#endif /* DRIVER_RECURSIVE */

src/mame/includes/taitoipt.h
r894	r895
271	271	PORT_BIT( 0x40, STATE, IPT_##BUTTON_C ) PORT_PLAYER(PL)
272	272	/* DO NOT fill bit 7 as it may be defined as START button ! */
273	273
	274	#define TAITO_GENERIC_1_BUTTON(PL) \
	275	TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, IP_ACTIVE_LOW, BUTTON1, UNKNOWN, UNKNOWN) \
	276	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	277
274	278	#define TAITO_GENERIC_2_BUTTONS(PL) \
275	279	TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, IP_ACTIVE_LOW, BUTTON1, BUTTON2, UNKNOWN) \
276	280	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
r894	r895
279	283	TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, IP_ACTIVE_LOW, BUTTON1, BUTTON2, BUTTON3) \
280	284	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
281	285
	286	#define TAITO_GENERIC_1_BUTTON_START(PL) \
	287	TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, IP_ACTIVE_LOW, BUTTON1, UNKNOWN, UNKNOWN) \
	288	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START##PL )
	289
282	290	#define TAITO_GENERIC_2_BUTTONS_START(PL) \
283	291	TAITO_GENERIC_BUTTONS_HIGH_NIBBLE(PL, IP_ACTIVE_LOW, BUTTON1, BUTTON2, UNKNOWN) \
284	292	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START##PL )
r894	r895
289	297
290	298
291	299	/* Taito games (more might be needed) */
	300	#define TAITO_JOY_UDLR_1_BUTTON(PL) \
	301	TAITO_GENERIC_JOY_MONO_UDLR(PL) \
	302	TAITO_GENERIC_1_BUTTON(PL)
	303
292	304	#define TAITO_JOY_UDLR_2_BUTTONS(PL) \
293	305	TAITO_GENERIC_JOY_MONO_UDLR(PL) \
294	306	TAITO_GENERIC_2_BUTTONS(PL)
r894	r895
297	309	TAITO_GENERIC_JOY_MONO_UDLR(PL) \
298	310	TAITO_GENERIC_3_BUTTONS(PL)
299	311
	312	#define TAITO_JOY_UDRL_1_BUTTON(PL) \
	313	TAITO_GENERIC_JOY_MONO_UDRL(PL) \
	314	TAITO_GENERIC_1_BUTTON(PL)
	315
300	316	#define TAITO_JOY_UDRL_2_BUTTONS(PL) \
301	317	TAITO_GENERIC_JOY_MONO_UDRL(PL) \
302	318	TAITO_GENERIC_2_BUTTONS(PL)
r894	r895
305	321	TAITO_GENERIC_JOY_MONO_UDRL(PL) \
306	322	TAITO_GENERIC_3_BUTTONS(PL)
307	323
	324	#define TAITO_JOY_LRUD_1_BUTTON(PL) \
	325	TAITO_GENERIC_JOY_MONO_LRUD(PL) \
	326	TAITO_GENERIC_1_BUTTON(PL)
	327
308	328	#define TAITO_JOY_LRUD_2_BUTTONS(PL) \
309	329	TAITO_GENERIC_JOY_MONO_LRUD(PL) \
310	330	TAITO_GENERIC_2_BUTTONS(PL)
r894	r895
314	334	TAITO_GENERIC_3_BUTTONS(PL)
315	335
316	336
	337	#define TAITO_JOY_UDLR_1_BUTTON_START(PL) \
	338	TAITO_GENERIC_JOY_MONO_UDLR(PL) \
	339	TAITO_GENERIC_1_BUTTON_START(PL)
	340
317	341	#define TAITO_JOY_UDLR_2_BUTTONS_START(PL) \
318	342	TAITO_GENERIC_JOY_MONO_UDLR(PL) \
319	343	TAITO_GENERIC_2_BUTTONS_START(PL)
r894	r895
322	346	TAITO_GENERIC_JOY_MONO_UDLR(PL) \
323	347	TAITO_GENERIC_3_BUTTONS_START(PL)
324	348
	349	#define TAITO_JOY_UDRL_1_BUTTON_START(PL) \
	350	TAITO_GENERIC_JOY_MONO_UDRL(PL) \
	351	TAITO_GENERIC_1_BUTTONS_START(PL)
	352
325	353	#define TAITO_JOY_UDRL_2_BUTTONS_START(PL) \
326	354	TAITO_GENERIC_JOY_MONO_UDRL(PL) \
327	355	TAITO_GENERIC_2_BUTTONS_START(PL)
r894	r895
330	358	TAITO_GENERIC_JOY_MONO_UDRL(PL) \
331	359	TAITO_GENERIC_3_BUTTONS_START(PL)
332	360
	361	#define TAITO_JOY_LRUD_1_BUTTON_START(PL) \
	362	TAITO_GENERIC_JOY_MONO_LRUD(PL) \
	363	TAITO_GENERIC_1_BUTTON_START(PL)
	364
333	365	#define TAITO_JOY_LRUD_2_BUTTONS_START(PL) \
334	366	TAITO_GENERIC_JOY_MONO_LRUD(PL) \
335	367	TAITO_GENERIC_2_BUTTONS_START(PL)

src/mame/includes/amiga.h
r894	r895
307	307	struct _amiga_machine_interface
308	308	{
309	309	UINT32 chip_ram_mask;
310
	310
311	311	UINT8 (*cia_0_portA_r)(void);
312	312	UINT8 (*cia_0_portB_r)(void);
313	313	void (*cia_0_portA_w)(UINT8 data);
r894	r895
330	330	void (*scanline0_callback)(void);
331	331	void (*reset_callback)(void);
332	332	void (*nmi_callback)(void);
333
	333
334	334	UINT32 flags;
335	335	};
336	336

src/mame/mame.mak
r894	r895
1568	1568	$(DRIVERS)/hotblock.o \
1569	1569	$(DRIVERS)/imolagp.o \
1570	1570	$(DRIVERS)/intrscti.o \
	1571	$(DRIVERS)/istellar.o \
1571	1572	$(DRIVERS)/jackpool.o \
1572	1573	$(DRIVERS)/jpmimpct.o $(VIDEO)/jpmimpct.o \
1573	1574	$(DRIVERS)/kingpin.o \

src/mame/video/cps1.c
r894	r895
280	280	{"willowj", CPS_B_03, 0,1,0, 0x0000,0xffff,0x0000,0xffff },
281	281	{"willowje",CPS_B_03, 0,1,0, 0x0000,0xffff,0x0000,0xffff },
282	282	{"ffight", CPS_B_04, 0,0,0, 0x0001,0xffff,0x0001,0xffff },
283		{"ffightu", CPS_B_01, 0,0,0, 0x0001,0xffff,0x0001,0xffff },
284		{"ffightua",CPS_B_05, 0,0,0, 0x0001,0xffff,0x0001,0xffff }, // I think
	283	{"ffightu", CPS_B_04, 0,0,0, 0x0001,0xffff,0x0001,0xffff },
	284	{"ffightua",CPS_B_01, 0,0,0, 0x0001,0xffff,0x0001,0xffff },
	285	{"ffightub",CPS_B_05, 0,0,0, 0x0001,0xffff,0x0001,0xffff }, // I think
285	286	{"ffightj", CPS_B_04, 0,0,0, 0x0001,0xffff,0x0001,0xffff },
286	287	{"ffightj1",CPS_B_02, 0,0,0, 0x0001,0xffff,0x0001,0xffff },
287	288	{"1941", CPS_B_05, 0,0,0, 0x0000,0xffff,0x0400,0x07ff },

src/mame/drivers/aerofgt.c
r894	r895
45	45	register 00 could be screen width / 4 (hblank start?)
46	46	register 08 could be screen height / 2 (vblank start?)
47	47
	48
	49	2007.08.25: Small note regarding DipSwitches. Locations and values have been verified for:
	50
	51	- svolly91 (PCB Infos from the dumper),
	52	- aerofgt (manual),
	53	- karatblz (US manual),
	54	- spinlbrk (US manual),
	55	- turbofrc (US manual)
	56
	57	Verification still needed for the other PCBs.
	58
48	59	***************************************************************************/
49	60
50	61	#include "driver.h"
r894	r895
554	565	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
555	566
556	567	PORT_START_TAG("DSW")
557		PORT_DIPNAME( 0x0003, 0x0003, DEF_STR( Coin_A ) )
	568	PORT_DIPNAME( 0x0003, 0x0003, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:1,2")
558	569	PORT_DIPSETTING( 0x0001, DEF_STR( 3C_1C ) )
559	570	PORT_DIPSETTING( 0x0002, DEF_STR( 2C_1C ) )
560	571	PORT_DIPSETTING( 0x0003, DEF_STR( 1C_1C ) )
561	572	PORT_DIPSETTING( 0x0000, DEF_STR( 1C_2C ) )
562		PORT_DIPNAME( 0x000c, 0x000c, DEF_STR( Coin_B ) )
	573	PORT_DIPNAME( 0x000c, 0x000c, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:3,4")
563	574	PORT_DIPSETTING( 0x0004, DEF_STR( 3C_1C ) )
564	575	PORT_DIPSETTING( 0x0008, DEF_STR( 2C_1C ) )
565	576	PORT_DIPSETTING( 0x000c, DEF_STR( 1C_1C ) )
566	577	PORT_DIPSETTING( 0x0000, DEF_STR( 1C_2C ) )
567		/* the following two select country in the Chinese version (ROMs not available) */
568		PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
569		PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
570		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
571		PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
572		PORT_DIPSETTING( 0x0020, DEF_STR( Off ) )
573		PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
574		PORT_DIPNAME( 0x0040, 0x0000, DEF_STR( Demo_Sounds ) )
	578	/* The following two select country in the Chinese version (ROMs not available)
	579	Based on Super Volley '91 PCB Infos, the settings are:
	580	China \|off\|off\|
	581	Taiwan \|on \|off\|
	582	HongKong \|off\|on \| */
	583	PORT_DIPNAME( 0x0030, 0x0030, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:5,6")
	584	PORT_DIPSETTING( 0x0030, "Off - Off" )
	585	PORT_DIPSETTING( 0x0020, "Off - On" )
	586	PORT_DIPSETTING( 0x0010, "On - Off" )
	587	PORT_DIPSETTING( 0x0000, "On - On" )
	588	PORT_DIPNAME( 0x0040, 0x0000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:7")
575	589	PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
576	590	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
577		PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) )
	591	PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:8")
578	592	PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
579	593	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
580		PORT_SERVICE( 0x0100, IP_ACTIVE_LOW )
581		PORT_DIPNAME( 0x0600, 0x0600, "1 Player Starting Score" )
	594	/* According to Super Volley '91 PCB Infos, here DSW2 starts */
	595	PORT_SERVICE_DIPLOC( 0x0100, IP_ACTIVE_LOW, "SW2:1" )
	596	PORT_DIPNAME( 0x0600, 0x0600, "1 Player Starting Score" ) PORT_DIPLOCATION("SW2:2,3")
582	597	PORT_DIPSETTING( 0x0600, "12-12" )
583	598	PORT_DIPSETTING( 0x0400, "11-11" )
584	599	PORT_DIPSETTING( 0x0200, "11-12" )
585	600	PORT_DIPSETTING( 0x0000, "10-12" )
586		PORT_DIPNAME( 0x1800, 0x1800, "2 Players Starting Score" )
	601	PORT_DIPNAME( 0x1800, 0x1800, "2 Players Starting Score" ) PORT_DIPLOCATION("SW2:4,5")
587	602	PORT_DIPSETTING( 0x1800, "9-9" )
588	603	PORT_DIPSETTING( 0x1000, "7-7" )
589	604	PORT_DIPSETTING( 0x0800, "5-5" )
590	605	PORT_DIPSETTING( 0x0000, "0-0" )
591		PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Difficulty ) )
	606	PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:6")
592	607	PORT_DIPSETTING( 0x2000, DEF_STR( Normal ) )
593	608	PORT_DIPSETTING( 0x0000, DEF_STR( Hard ) )
594		PORT_DIPNAME( 0x4000, 0x4000, "2 Players Time per Credit" )
	609	/* When the players continue, only half of the time in SW2:7 is added */
	610	PORT_DIPNAME( 0x4000, 0x4000, "2 Players Time per Credit" ) PORT_DIPLOCATION("SW2:7")
595	611	PORT_DIPSETTING( 0x4000, "3 min" )
596	612	PORT_DIPSETTING( 0x0000, "2 min" )
597		PORT_DIPNAME( 0x8000, 0x8000, "Debug" )
	613	/* The next one is reported as 'Must be off' in Super Volley '91 PCB Infos */
	614	PORT_DIPNAME( 0x8000, 0x8000, "Debug" ) PORT_DIPLOCATION("SW2:8")
598	615	PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
599	616	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
600	617	INPUT_PORTS_END
r894	r895
734	751	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(4)
735	752
736	753	PORT_START_TAG("DSW")
737		PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) /* Coins 1, 2, 3 & 4 */
	754	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3") /* It affects Coin 1, 2, 3 and 4 */
738	755	PORT_DIPSETTING( 0x0004, DEF_STR( 4C_1C ) )
739	756	PORT_DIPSETTING( 0x0005, DEF_STR( 3C_1C ) )
740	757	PORT_DIPSETTING( 0x0006, DEF_STR( 2C_1C ) )
r894	r895
743	760	PORT_DIPSETTING( 0x0002, DEF_STR( 1C_3C ) )
744	761	PORT_DIPSETTING( 0x0001, DEF_STR( 1C_5C ) )
745	762	PORT_DIPSETTING( 0x0000, DEF_STR( 1C_6C ) )
746		PORT_DIPNAME( 0x0008, 0x0008, "2 Coins to Start, 1 to Continue" )
	763	PORT_DIPNAME( 0x0008, 0x0008, "2 Coins to Start, 1 to Continue" ) PORT_DIPLOCATION("SW1:4")
747	764	PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
748	765	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
749		PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Lives ) )
	766	PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW1:5")
750	767	PORT_DIPSETTING( 0x0000, "1" )
751	768	PORT_DIPSETTING( 0x0010, "2" )
752		PORT_DIPNAME( 0x0060, 0x0060, DEF_STR( Cabinet ) ) /* Game Type */
	769	PORT_DIPNAME( 0x0060, 0x0060, DEF_STR( Cabinet ) ) /* Game Type */ PORT_DIPLOCATION("SW1:6,7")
753	770	PORT_DIPSETTING( 0x0060, "2 Players" ) /* 1 Unit / 2 Players */
754	771	PORT_DIPSETTING( 0x0040, "3 Players" ) /* 1 Unit / 3 Players */
755	772	PORT_DIPSETTING( 0x0020, "4 Players" ) /* 1 Unit / 4 Players */
r894	r895
758	775	Coin A & B credit together for use by _only_ player 1 or player 2
759	776	Coin C & D credit together for use by _only_ player 3 or player 4
760	777	Otherwise with Individual selected, everyone is seperate */
761		PORT_DIPNAME( 0x0080, 0x0080, "Coin Slot" )
	778	PORT_DIPNAME( 0x0080, 0x0080, "Coin Slot" ) PORT_DIPLOCATION("SW1:8")
762	779	PORT_DIPSETTING( 0x0080, "Same" )
763	780	PORT_DIPSETTING( 0x0000, "Individual" )
764		PORT_SERVICE( 0x0100, IP_ACTIVE_LOW )
765		PORT_DIPNAME( 0x0600, 0x0200, "Number of Enemies" ) /* Default is DEF_STR( Hard ) */
	781	/* According to Turbo Force manual, here DSW2 starts */
	782	PORT_SERVICE_DIPLOC( 0x0100, IP_ACTIVE_LOW, "SW2:1" )
	783	/* Default is DEF_STR( Hard ) */
	784	PORT_DIPNAME( 0x0600, 0x0200, "Number of Enemies" ) PORT_DIPLOCATION("SW2:2,3")
766	785	PORT_DIPSETTING( 0x0400, DEF_STR( Easy ) )
767	786	PORT_DIPSETTING( 0x0600, DEF_STR( Normal ) )
768	787	PORT_DIPSETTING( 0x0200, DEF_STR( Hard ) )
769	788	PORT_DIPSETTING( 0x0000, DEF_STR( Hardest ) )
770		PORT_DIPNAME( 0x1800, 0x0800, "Strength of Enemies" ) /* Default is DEF_STR( Hard ) */
	789	/* Default is DEF_STR( Hard ) */
	790	PORT_DIPNAME( 0x1800, 0x0800, "Strength of Enemies" ) PORT_DIPLOCATION("SW2:4,5")
771	791	PORT_DIPSETTING( 0x1000, DEF_STR( Easy ) )
772	792	PORT_DIPSETTING( 0x1800, DEF_STR( Normal ) )
773	793	PORT_DIPSETTING( 0x0800, DEF_STR( Hard ) )
774	794	PORT_DIPSETTING( 0x0000, DEF_STR( Hardest ) )
775		PORT_DIPNAME( 0x2000, 0x2000, "Freeze" ) /* Listed in manual as N.C. (aka No Connection) */
	795	/* Listed in manual as N.C. (aka No Connection) */
	796	PORT_DIPNAME( 0x2000, 0x2000, "Freeze" ) PORT_DIPLOCATION("SW2:6")
776	797	PORT_DIPSETTING( 0x2000, DEF_STR( Off ) )
777	798	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
778		PORT_DIPNAME( 0x4000, 0x0000, DEF_STR( Demo_Sounds ) )
	799	PORT_DIPNAME( 0x4000, 0x0000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:7")
779	800	PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
780	801	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
781		PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Flip_Screen ) )
	802	PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:8")
782	803	PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
783	804	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
784	805	INPUT_PORTS_END
r894	r895
813	834	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
814	835
815	836	PORT_START_TAG("DSW")
816		PORT_DIPNAME( 0x000f, 0x000f, DEF_STR( Coin_A ) )
	837	PORT_DIPNAME( 0x000f, 0x000f, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:1,2,3,4")
817	838	PORT_DIPSETTING( 0x000f, "1 Credit 1 Health Pack" ) /* I chose "Health Packs" as the actual value can change */
818	839	PORT_DIPSETTING( 0x000e, "1 Credit 2 Health Packs" ) /* via dipswitch 2-7 (0x4000) see below */
819	840	PORT_DIPSETTING( 0x000d, "1 Credit 3 Health Packs" )
r894	r895
830	851	PORT_DIPSETTING( 0x0002, "1-1-1-1-1C 1-1-1-1-2 HPs" )
831	852	PORT_DIPSETTING( 0x0001, "1-1-1-1C 1-1-1-2 HPs" )
832	853	PORT_DIPSETTING( 0x0000, "1-1C 1-2 HPs" )
833		/* The last 5 Coin/Credit selections are cycles:
834		Example: 0x0004 = 2-1-1C 1-1-1 HPs:
835		2 Credits for the 1st Health Pack, 1 Credit for the 2nd Health Pack, 1 Credit
836		for the 3rd Health Pack... Then back to 2 Credits agian for 1 HP, then 1 credit
837		and 1 credit.... on and on. With all Coin/Credit dips set to on, it's 1 Health
838		Pack for odd credits, 2 Health Packs for even credits :p
839		*/
840		PORT_DIPNAME( 0x00f0, 0x00f0, DEF_STR( Coin_B ) )
	854	/* The last 5 Coin/Credit selections are cycles:
	855	Example: 0x0004 = 2-1-1C 1-1-1 HPs:
	856	2 Credits for the 1st Health Pack, 1 Credit for the 2nd Health Pack, 1 Credit
	857	for the 3rd Health Pack... Then back to 2 Credits again for 1 HP, then 1 credit
	858	and 1 credit.... on and on. With all Coin/Credit dips set to on, it's 1 Health
	859	Pack for odd credits, 2 Health Packs for even credits :p
	860	*/
	861	PORT_DIPNAME( 0x00f0, 0x00f0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:5,6,7,8")
841	862	PORT_DIPSETTING( 0x00f0, "1 Credit 1 Health Pack" )
842	863	PORT_DIPSETTING( 0x00e0, "1 Credit 2 Health Packs" )
843	864	PORT_DIPSETTING( 0x00d0, "1 Credit 3 Health Packs" )
r894	r895
854	875	PORT_DIPSETTING( 0x0020, "1-1-1-1-1C 1-1-1-1-2 HPs" )
855	876	PORT_DIPSETTING( 0x0010, "1-1-1-1C 1-1-1-2 HPs" )
856	877	PORT_DIPSETTING( 0x0000, "1-1C 1-2 HPs" )
857		PORT_DIPNAME( 0x0300, 0x0300, DEF_STR( Difficulty ) )
	878	/* According to Spinal Breakers manual, here DSW2 starts */
	879	/* Default in US manual is DEF_STR( Hardest ) */
	880	PORT_DIPNAME( 0x0300, 0x0000, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
858	881	PORT_DIPSETTING( 0x0300, DEF_STR( Normal ) )
859	882	PORT_DIPSETTING( 0x0200, DEF_STR( Easy ) )
860	883	PORT_DIPSETTING( 0x0100, DEF_STR( Hard ) )
861	884	PORT_DIPSETTING( 0x0000, DEF_STR( Hardest ) )
862		PORT_DIPNAME( 0x0400, 0x0400, "Coin Slot" )
	885	PORT_DIPNAME( 0x0400, 0x0400, "Coin Slot" ) PORT_DIPLOCATION("SW2:3")
863	886	PORT_DIPSETTING( 0x0000, "Same" )
864	887	PORT_DIPSETTING( 0x0400, "Individual" )
865		PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Flip_Screen ) )
	888	PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:4")
866	889	PORT_DIPSETTING( 0x0800, DEF_STR( Off ) )
867	890	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
868		PORT_DIPNAME( 0x1000, 0x1000, "Lever Type" )
	891	PORT_DIPNAME( 0x1000, 0x1000, "Lever Type" ) PORT_DIPLOCATION("SW2:5")
869	892	PORT_DIPSETTING( 0x1000, "Digital" )
870	893	PORT_DIPSETTING( 0x0000, "Analog" ) /* This setting causes lever error??? */
871		PORT_SERVICE( 0x2000, IP_ACTIVE_LOW )
872		PORT_DIPNAME( 0x4000, 0x4000, "Health Pack" )
	894	PORT_SERVICE_DIPLOC( 0x2000, IP_ACTIVE_LOW, "SW2:6" )
	895	PORT_DIPNAME( 0x4000, 0x4000, "Health Pack" ) PORT_DIPLOCATION("SW2:7")
873	896	PORT_DIPSETTING( 0x4000, "32 Hitpoints" )
874	897	PORT_DIPSETTING( 0x0000, "40 Hitpoints" )
875		PORT_DIPNAME( 0x8000, 0x8000, "Life Restoration" )
	898	/* Default in US manual is "5 points" */
	899	PORT_DIPNAME( 0x8000, 0x0000, "Life Restoration" ) PORT_DIPLOCATION("SW2:8")
876	900	PORT_DIPSETTING( 0x8000, "10 Points" )
877	901	PORT_DIPSETTING( 0x0000, "5 Points" )
878	902	INPUT_PORTS_END
r894	r895
881	905	PORT_INCLUDE(spinlbrk)
882	906
883	907	PORT_MODIFY("DSW")
884		PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Allow_Continue ) )
	908	PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Allow_Continue ) ) PORT_DIPLOCATION("SW2:7")
885	909	PORT_DIPSETTING( 0x0400, "Unlimited" )
886	910	PORT_DIPSETTING( 0x0000, "6 Times" )
887	911	INPUT_PORTS_END
r894	r895
890	914	PORT_INCLUDE(spinlbrk)
891	915
892	916	PORT_MODIFY("DSW")
893		PORT_DIPNAME( 0x4000, 0x4000, "Health Pack" )
	917	PORT_DIPNAME( 0x4000, 0x4000, "Health Pack" ) PORT_DIPLOCATION("SW2:7")
894	918	PORT_DIPSETTING( 0x4000, "20 Hitpoints" )
895	919	PORT_DIPSETTING( 0x0000, "32 Hitpoints" )
896	920	INPUT_PORTS_END
r894	r895
925	949	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )//START1 )
926	950
927	951	PORT_START_TAG("DSW")
928		PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) /* Coins 1, 2 & 3 */
	952	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2,3") /* It affects Coin 1, 2 and 3 */
929	953	PORT_DIPSETTING( 0x0004, DEF_STR( 4C_1C ) )
930	954	PORT_DIPSETTING( 0x0005, DEF_STR( 3C_1C ) )
931	955	PORT_DIPSETTING( 0x0006, DEF_STR( 2C_1C ) )
r894	r895
934	958	PORT_DIPSETTING( 0x0002, DEF_STR( 1C_3C ) )
935	959	PORT_DIPSETTING( 0x0001, DEF_STR( 1C_5C ) )
936	960	PORT_DIPSETTING( 0x0000, DEF_STR( 1C_6C ) )
937		PORT_DIPNAME( 0x0008, 0x0008, "2 Coins to Start, 1 to Continue" )
	961	PORT_DIPNAME( 0x0008, 0x0008, "2 Coins to Start, 1 to Continue" ) PORT_DIPLOCATION("SW1:4")
938	962	PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
939	963	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
940		PORT_DIPNAME( 0x0010, 0x0000, "Coin Slot" )
	964	PORT_DIPNAME( 0x0010, 0x0000, "Coin Slot" ) PORT_DIPLOCATION("SW1:5")
941	965	PORT_DIPSETTING( 0x0010, "Same" )
942	966	PORT_DIPSETTING( 0x0000, "Individual" )
943		PORT_DIPNAME( 0x0020, 0x0000, "Play Mode" )
	967	PORT_DIPNAME( 0x0020, 0x0000, "Play Mode" ) PORT_DIPLOCATION("SW1:6")
944	968	PORT_DIPSETTING( 0x0020, "2 Players" )
945	969	PORT_DIPSETTING( 0x0000, "3 Players" )
946		PORT_DIPNAME( 0x0040, 0x0000, DEF_STR( Demo_Sounds ) )
	970	PORT_DIPNAME( 0x0040, 0x0000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:7")
947	971	PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
948	972	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
949		PORT_SERVICE( 0x0080, IP_ACTIVE_LOW )
950		PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Flip_Screen ) )
	973	PORT_SERVICE_DIPLOC( 0x0080, IP_ACTIVE_LOW, "SW1:8" )
	974	/* According to Turbo Force manual, here DSW2 starts */
	975	PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:1")
951	976	PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
952	977	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
953		PORT_DIPNAME( 0x0e00, 0x0800, DEF_STR( Difficulty ) )
	978	PORT_DIPNAME( 0x0e00, 0x0800, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:2,3,4")
954	979	PORT_DIPSETTING( 0x0e00, "1 (Easiest)")
955	980	PORT_DIPSETTING( 0x0c00, "2" )
956	981	PORT_DIPSETTING( 0x0a00, "3" )
r894	r895
959	984	PORT_DIPSETTING( 0x0400, "6" )
960	985	PORT_DIPSETTING( 0x0200, "7" )
961	986	PORT_DIPSETTING( 0x0000, "8 (Hardest)" )
962		PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Lives ) )
	987	PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:5")
963	988	PORT_DIPSETTING( 0x0000, "2" )
964	989	PORT_DIPSETTING( 0x1000, "3" )
965		PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Bonus_Life ) )
	990	PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:6")
966	991	PORT_DIPSETTING( 0x2000, "200000" )
967	992	PORT_DIPSETTING( 0x0000, "300000" )
	993	/* The following 2 are listed in Turbo Force manual as N.C. (aka No Connection) and "Should be kept on OFF" */
	994	PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:7")
	995	PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
	996	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
	997	PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:8")
	998	PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
	999	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
968	1000
	1001
969	1002	PORT_START_TAG("IN2")
970	1003	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
971	1004	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
r894	r895
1092	1125	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
1093	1126
1094	1127	PORT_START_TAG("DSW1")
1095		PORT_DIPNAME( 0x0001, 0x0001, "Coin Slot" )
	1128	PORT_DIPNAME( 0x0001, 0x0001, "Coin Slot" ) PORT_DIPLOCATION("SW1:1")
1096	1129	PORT_DIPSETTING( 0x0001, "Same" )
1097	1130	PORT_DIPSETTING( 0x0000, "Individual" )
1098		PORT_DIPNAME( 0x000e, 0x000e, DEF_STR( Coin_A ) )
	1131	PORT_DIPNAME( 0x000e, 0x000e, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:2,3,4")
1099	1132	PORT_DIPSETTING( 0x000a, DEF_STR( 3C_1C ) )
1100	1133	PORT_DIPSETTING( 0x000c, DEF_STR( 2C_1C ) )
1101	1134	PORT_DIPSETTING( 0x000e, DEF_STR( 1C_1C ) )
r894	r895
1104	1137	PORT_DIPSETTING( 0x0004, DEF_STR( 1C_4C ) )
1105	1138	PORT_DIPSETTING( 0x0002, DEF_STR( 1C_5C ) )
1106	1139	PORT_DIPSETTING( 0x0000, DEF_STR( 1C_6C ) )
1107		PORT_DIPNAME( 0x0070, 0x0070, DEF_STR( Coin_B ) )
	1140	PORT_DIPNAME( 0x0070, 0x0070, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:5,6,7")
1108	1141	PORT_DIPSETTING( 0x0050, DEF_STR( 3C_1C ) )
1109	1142	PORT_DIPSETTING( 0x0060, DEF_STR( 2C_1C ) )
1110	1143	PORT_DIPSETTING( 0x0070, DEF_STR( 1C_1C ) )
r894	r895
1113	1146	PORT_DIPSETTING( 0x0020, DEF_STR( 1C_4C ) )
1114	1147	PORT_DIPSETTING( 0x0010, DEF_STR( 1C_5C ) )
1115	1148	PORT_DIPSETTING( 0x0000, DEF_STR( 1C_6C ) )
1116		PORT_DIPNAME( 0x0080, 0x0080, "2 Coins to Start, 1 to Continue" )
	1149	PORT_DIPNAME( 0x0080, 0x0080, "2 Coins to Start, 1 to Continue" ) PORT_DIPLOCATION("SW1:8")
1117	1150	PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
1118	1151	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
1119	1152
1120	1153	PORT_START_TAG("DSW2")
1121		PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Flip_Screen ) )
	1154	PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:1")
1122	1155	PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
1123	1156	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
1124		PORT_DIPNAME( 0x0002, 0x0000, DEF_STR( Demo_Sounds ) )
	1157	PORT_DIPNAME( 0x0002, 0x0000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:2")
1125	1158	PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
1126	1159	PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
1127		PORT_DIPNAME( 0x000c, 0x000c, DEF_STR( Difficulty ) )
	1160	PORT_DIPNAME( 0x000c, 0x000c, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:3,4")
1128	1161	PORT_DIPSETTING( 0x0008, DEF_STR( Easy ) )
1129	1162	PORT_DIPSETTING( 0x000c, DEF_STR( Normal ) )
1130	1163	PORT_DIPSETTING( 0x0004, DEF_STR( Hard ) )
1131	1164	PORT_DIPSETTING( 0x0000, DEF_STR( Hardest ) )
1132		PORT_DIPNAME( 0x0030, 0x0030, DEF_STR( Lives ) )
	1165	PORT_DIPNAME( 0x0030, 0x0030, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW2:5,6")
1133	1166	PORT_DIPSETTING( 0x0020, "1" )
1134	1167	PORT_DIPSETTING( 0x0010, "2" )
1135	1168	PORT_DIPSETTING( 0x0030, "3" )
1136	1169	PORT_DIPSETTING( 0x0000, "4" )
1137		PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Bonus_Life ) )
	1170	PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:7")
1138	1171	PORT_DIPSETTING( 0x0040, "200000" )
1139	1172	PORT_DIPSETTING( 0x0000, "300000" )
1140		PORT_SERVICE( 0x0080, IP_ACTIVE_LOW )
	1173	PORT_SERVICE_DIPLOC( 0x0080, IP_ACTIVE_LOW, "SW2:8" )
1141	1174
	1175	/* This DSW3 is not documented in the Aero Fighters manual */
1142	1176	PORT_START_TAG("DSW3")
1143	1177	PORT_DIPNAME( 0x000f, 0x0000, "Country" )
1144	1178	PORT_DIPSETTING( 0x0000, "Any" )

src/mame/drivers/superdq.c
r894	r895
361	361	/* sound hardware */
362	362	MDRV_SPEAKER_STANDARD_STEREO("left", "right")
363	363
364		MDRV_SOUND_ADD(SN76496, MASTER_CLOCK/2)
	364	MDRV_SOUND_ADD(SN76496, MASTER_CLOCK/8)
365	365	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "left", 0.8)
366	366
367	367	MDRV_SOUND_ADD(CUSTOM, 0)

src/mame/drivers/cps1.c
r894	r895
4575	4575
4576	4576	ROM_START( ffightu )
4577	4577	ROM_REGION( CODE_SIZE, REGION_CPU1, 0 ) /* 68000 code */
	4578	ROM_LOAD16_BYTE( "ff30-36.bin", 0x00000, 0x20000, CRC(f9a5ce83) SHA1(0756ae576a1f6d5b8b22f8630dca40ef38567ea6) )
	4579	ROM_LOAD16_BYTE( "ff35-42.bin", 0x00001, 0x20000, CRC(65f11215) SHA1(5045a467f3e228c02b4a355b52f58263ffa90113) )
	4580	ROM_LOAD16_BYTE( "ff31-37.bin", 0x40000, 0x20000, CRC(e1033784) SHA1(38f44434c8befd623953ae23d6e5ff4e201d6627) )
	4581	ROM_LOAD16_BYTE( "ff43.rom", 0x40001, 0x20000, CRC(4ca65947) SHA1(74ffe00df96273770a24d9a46f13e53ea8812670) )
	4582	ROM_LOAD16_WORD_SWAP( "ff32-32m.bin", 0x80000, 0x80000, CRC(c747696e) SHA1(d3362dadded31ccb7eaf71ef282d698d18edd722) )
	4583
	4584	ROM_REGION( 0x200000, REGION_GFX1, 0 )
	4585	ROMX_LOAD( "ff05-05m.bin", 0x000000, 0x80000, CRC(9c284108) SHA1(7868f5801347340867720255f8380548ad1a65a7) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4586	ROMX_LOAD( "ff07-07m.bin", 0x000002, 0x80000, CRC(a7584dfb) SHA1(f7b00a3ca8cb85264ab293089f9f540a8292b49c) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4587	ROMX_LOAD( "ff01-01m.bin", 0x000004, 0x80000, CRC(0b605e44) SHA1(5ce16af72858a57aefbf6efed820c2c51935882a) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4588	ROMX_LOAD( "ff03-03m.bin", 0x000006, 0x80000, CRC(52291cd2) SHA1(df5f3d3aa96a7a33ff22f2a31382942c4c4f1111) , ROM_GROUPWORD \| ROM_SKIP(6) )
	4589
	4590	ROM_REGION( 0x8000, REGION_GFX2, 0 )
	4591	ROM_COPY( REGION_GFX1, 0x000000, 0x000000, 0x8000 ) /* stars */
	4592
	4593	ROM_REGION( 0x18000, REGION_CPU2, 0 ) /* 64k for the audio CPU (+banks) */
	4594	ROM_LOAD( "ff09-09.bin", 0x00000, 0x08000, CRC(b8367eb5) SHA1(ec3db29fdd6200e9a8f4f8073a7e34aef731354f) )
	4595	ROM_CONTINUE( 0x10000, 0x08000 )
	4596
	4597	ROM_REGION( 0x40000, REGION_SOUND1, 0 ) /* Samples */
	4598	ROM_LOAD( "ff18-18.bin", 0x00000, 0x20000, CRC(375c66e7) SHA1(36189e23209ce4ae5d9cbabd1574540d0591e7b3) )
	4599	ROM_LOAD( "ff19-19.bin", 0x20000, 0x20000, CRC(1ef137f9) SHA1(974b5e72aa28b87ebfa7438efbdfeda769dedf5e) )
	4600	ROM_END
	4601
	4602	ROM_START( ffightua )
	4603	ROM_REGION( CODE_SIZE, REGION_CPU1, 0 ) /* 68000 code */
4578	4604	ROM_LOAD16_BYTE( "36", 0x00000, 0x20000, CRC(e2a48af9) SHA1(11e06f95bdf575af396dded2b84d858f6c7388f1) )
4579	4605	ROM_LOAD16_BYTE( "42", 0x00001, 0x20000, CRC(f4bb480e) SHA1(32114df1d2f4f98a4a2280a330c7b6af8ab4d862) )
4580	4606	ROM_LOAD16_BYTE( "37", 0x40000, 0x20000, CRC(c371c667) SHA1(633977c91a8ff09b7fe83128eced7c4dee9aee1d) )
r894	r895
4602	4628	ROM_LOAD( "ff19-19.bin", 0x20000, 0x20000, CRC(1ef137f9) SHA1(974b5e72aa28b87ebfa7438efbdfeda769dedf5e) )
4603	4629	ROM_END
4604	4630
4605		ROM_START( ffightua )
	4631	ROM_START( ffightub )
4606	4632	ROM_REGION( CODE_SIZE, REGION_CPU1, 0 ) /* 68000 code */
4607	4633	ROM_LOAD16_BYTE( "30_2da0.010", 0x00000, 0x20000, CRC(ed988977) SHA1(c718e989206bd2b68832c8fcb5667397d500ebac) )
4608	4634	ROM_LOAD16_BYTE( "35_46ff.010", 0x00001, 0x20000, CRC(07bf1c21) SHA1(f21a939fd92607c7f54816dedbcb3c5818cf4183) )
r894	r895
7780	7806	GAME( 1989, unsquad, 0, cps1, unsquad, cps1, ROT0, "Capcom", "U.N. Squadron (US)", 0 )
7781	7807	GAME( 1989, area88, unsquad, cps1, unsquad, cps1, ROT0, "Capcom", "Area 88 (Japan)", 0 )
7782	7808	GAME( 1989, ffight, 0, cps1, ffight, cps1, ROT0, "Capcom", "Final Fight (World)", 0 )
7783		GAME( 1989, ffightu, ffight, cps1, ffight, cps1, ROT0, "Capcom", "Final Fight (US 900112)", 0 )
7784		GAME( 1989, ffightua, ffight, cps1, ffight, cps1, ROT0, "Capcom", "Final Fight (US 900613)", 0 )
	7809	GAME( 1989, ffightu, ffight, cps1, ffight, cps1, ROT0, "Capcom", "Final Fight (US)", 0 )
	7810	GAME( 1989, ffightua, ffight, cps1, ffight, cps1, ROT0, "Capcom", "Final Fight (US 900112)", 0 )
	7811	GAME( 1989, ffightub, ffight, cps1, ffight, cps1, ROT0, "Capcom", "Final Fight (US 900613)", 0 )
7785	7812	GAME( 1989, ffightj, ffight, cps1, ffight, cps1, ROT0, "Capcom", "Final Fight (Japan)", 0 )
7786	7813	GAME( 1989, ffightj1, ffight, cps1, ffight, cps1, ROT0, "Capcom", "Final Fight (Japan 900305)", 0 )
7787	7814	GAME( 1990, 1941, 0, cps1, 1941, cps1, ROT270, "Capcom", "1941 - Counter Attack (World)", 0 )

src/mame/drivers/kinst.c
r894	r895
149	149
150	150	/*************************************
151	151	*
152		* Machine ~~ini~~t
	152	* Machine start
153	153	*
154	154	*************************************/
155	155
156		static MACHINE_RESET( kinst )
	156	static MACHINE_START( kinst )
157	157	{
158	158	/* set the fastest DRC options */
159	159	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS);
r894	r895
176	176	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
177	177	cpunum_set_info_ptr(0, CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
178	178	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
	179	}
179	180
	181
	182
	183	/*************************************
	184	*
	185	* Machine init
	186	*
	187	*************************************/
	188
	189	static MACHINE_RESET( kinst )
	190	{
180	191	/* keep the DCS held in reset at startup */
181	192	dcs_reset_w(1);
182	193
r894	r895
405	416	AM_RANGE(0x10000100, 0x1000013f) AM_READWRITE(ide_controller_r, ide_controller_w)
406	417	AM_RANGE(0x10000170, 0x10000173) AM_READWRITE(ide_controller_extra_r, ide_controller_extra_w)
407	418	AM_RANGE(0x1fc00000, 0x1fc7ffff) AM_ROM AM_REGION(REGION_USER1, 0) AM_BASE(&rombase)
408
409	419	ADDRESS_MAP_END
410	420
411	421
r894	r895
651	661	MDRV_SCREEN_REFRESH_RATE(60)
652	662	MDRV_SCREEN_VBLANK_TIME(DEFAULT_REAL_60HZ_VBLANK_DURATION)
653	663
	664	MDRV_MACHINE_START(kinst)
654	665	MDRV_MACHINE_RESET(kinst)
655	666
656	667	/* video hardware */

src/mame/drivers/taitoair.c
r894	r895
90	90	- Sprite zoom is a bit wrong.
91	91
92	92
	93	Stephh's notes (based on the game M68000 code and some tests) :
	94
	95	1) 'topland'
	96
	97	- Region stored at 0x03fffe.w
	98	- Sets :
	99	* 'topland' : region = 0x0002
	100	- Coinage relies on the region (code at 0x0016e8) :
	101	* 0x0000 (Japan) and 0x0001 (US) use TAITO_COINAGE_JAPAN_OLD
	102	* 0x0002 (World) uses TAITO_COINAGE_WORLD
	103	- Notice screen only if region = 0x0000
	104
	105
	106	2) 'ainferno'
	107
	108	- Region stored at 0x07fffe.w
	109	- Sets :
	110	* 'ainferno' : region = 0x0002
	111	- Coinage relies on the region (code at 0x000cec) :
	112	* 0x0001 (Japan) uses TAITO_COINAGE_JAPAN_OLD
	113	* 0x0002 (US) uses TAITO_COINAGE_US
	114	* 0x0003 (World) uses TAITO_COINAGE_WORLD
	115	- Notice screen only if region = 0x0001 or region = 0x0002
	116	- FBI logo only if region = 0x0002
	117
	118
	119
93	120	TODO (TC0080VCO issues shared with TaitoH driver)
94	121	----
95	122
r894	r895
189	216	****************************************************************************/
190	217
191	218	#include "driver.h"
	219	#include "taitoipt.h"
192	220	#include "audio/taitosnd.h"
193	221	#include "video/taitoic.h"
194	222	#include "cpu/tms32025/tms32025.h"
r894	r895
274	302	INPUTS
275	303	***********************************************************/
276	304
	305	#define STICK1_PORT_TAG "STICK1"
	306	#define STICK2_PORT_TAG "STICK2"
	307	#define STICK3_PORT_TAG "STICK3"
	308
277	309	static READ16_HANDLER( stick_input_r )
278	310	{
279	311	switch( offset )
280	312	{
281	313	case 0x00: /* "counter 1" lo */
282		return input_port_4_~~word_r(0,0~~);
	314	return readinputportbytag(STICK1_PORT_TAG);
283	315
284	316	case 0x01: /* "counter 2" lo */
285		return input_port_5_~~word_r(0,0~~);
	317	return readinputportbytag(STICK2_PORT_TAG);
286	318
287	319	case 0x02: /* "counter 1" hi */
288		return (input_port_4_~~word_r(0,0~~) &0xff00) >> 8;
	320	return (readinputportbytag(STICK1_PORT_TAG) & 0xff00) >> 8;
289	321
290	322	case 0x03: /* "counter 2" hi */
291		return (input_port_5_~~word_r(0,0~~) &0xff00) >> 8;
	323	return (readinputportbytag(STICK2_PORT_TAG) & 0xff00) >> 8;
292	324	}
293	325
294	326	return 0;
r894	r895
299	331	switch( offset )
300	332	{
301	333	case 0x00: /* "counter 3" lo */
302		return input_port_6_~~word_r(0,0~~);
	334	return readinputportbytag(STICK3_PORT_TAG);
303	335
304	336	case 0x02: /* "counter 3" hi */
305		return (input_port_6_~~word_r(0,0~~) &0xff00) >> 8;
	337	return (readinputportbytag(STICK3_PORT_TAG) & 0xff00) >> 8;
306	338	}
307	339
308	340	return 0;
r894	r895
393	425	INPUT PORTS & DIPS
394	426	************************************************************/
395	427
396		#define TAITO_COINAGE_JAPAN_8 \
397		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SWA:5,6") \
398		PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) ) \
399		PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) ) \
400		PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) ) \
401		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
402		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SWA:7,8") \
403		PORT_DIPSETTING( 0xc0, DEF_STR( 1C_2C ) ) \
404		PORT_DIPSETTING( 0x80, DEF_STR( 1C_3C ) ) \
405		PORT_DIPSETTING( 0x40, DEF_STR( 1C_4C ) ) \
406		PORT_DIPSETTING( 0x00, DEF_STR( 1C_6C ) )
407
408		#define TAITO_COINAGE_US_8 \
409		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:5,6") \
410		PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) ) \
411		PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) ) \
412		PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) ) \
413		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
414		PORT_DIPNAME( 0xc0, 0xc0, "Price to Continue" ) PORT_DIPLOCATION("SWA:7,8") \
415		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) \
416		PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
417		PORT_DIPSETTING( 0x80, DEF_STR( 1C_1C ) ) \
418		PORT_DIPSETTING( 0xc0, "Same as Start" )
419
420		#define TAITO_DIFFICULTY_8 \
421		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWB:1,2") \
422		PORT_DIPSETTING( 0x02, DEF_STR( Easy ) ) \
423		PORT_DIPSETTING( 0x03, DEF_STR( Medium ) ) \
424		PORT_DIPSETTING( 0x01, DEF_STR( Hard ) ) \
425		PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
426
427	428	INPUT_PORTS_START( topland )
428		PORT_START /* DSWA */
	429	/* 0xa00200 -> 0x0c0d7c (-$7285,A5) */
	430	PORT_START_TAG("DSWA")
429	431	PORT_DIPUNUSED_DIPLOC( 0x01, IP_ACTIVE_LOW, "SWA:1" )
430	432	PORT_DIPUNUSED_DIPLOC( 0x02, IP_ACTIVE_LOW, "SWA:2" )
431		PORT_SERVICE_DIPLOC( 0x04, IP_ACTIVE_LOW, "SWA:3" )
432		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SWA:4")
433		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
434		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
435		TAITO_COINAGE_JAPAN_8
	433	TAITO_DSWA_BITS_2_TO_3_LOC(SWA)
	434	TAITO_COINAGE_WORLD_LOC(SWA)
436	435
437		PORT_START /* DSWB */
438		TAITO_DIFFICULTY_8
	436	/* 0xa00202 -> 0x0c0d7e (-$7283,A5) */
	437	PORT_START_TAG("DSWA")
	438	TAITO_DIFFICULTY_LOC(SWA)
439	439	PORT_DIPUNUSED_DIPLOC( 0x04, IP_ACTIVE_LOW, "SWB:3" )
440	440	PORT_DIPUNUSED_DIPLOC( 0x08, IP_ACTIVE_LOW, "SWB:4" )
441	441	PORT_DIPUNUSED_DIPLOC( 0x10, IP_ACTIVE_LOW, "SWB:5" )
r894	r895
443	443	PORT_DIPUNUSED_DIPLOC( 0x40, IP_ACTIVE_LOW, "SWB:7" )
444	444	PORT_DIPUNUSED_DIPLOC( 0x80, IP_ACTIVE_LOW, "SWB:8" )
445	445
446		PORT_START /* IN0 */
	446	PORT_START_TAG("IN0")
447	447	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
448	448	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
449	449	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN1 )
r894	r895
453	453	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
454	454	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) /* "door" (!) */
455	455
456		PORT_START /* IN1 */
	456	PORT_START_TAG("IN1")
457	457	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) /* slot down */
458	458	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1) /* slot up */
459	459	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1) /* handle */
460	460	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
461	461	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
462	462	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
463		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_~~BUTT~~ON4 ) PORT_PLAYER(~~1) /* f~~reeze ~~??? */~~
	463	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Freeze") PORT_CODE(KEYCODE_F1)
464	464	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
465	465
466	466	/* The range of these sticks reflects the range test mode displays.
r894	r895
468	468	in the stick_r routines. And fake DSW with self-centering option
469	469	to make keyboard control feasible! */
470	470
471		PORT_START /* S~~tick~~ 1 (4) */
	471	PORT_START_TAG(STICK1_PORT_TAG)
472	472	PORT_BIT( 0xffff, 0x0000, IPT_AD_STICK_X ) PORT_MINMAX(0xf800,0x7ff) PORT_SENSITIVITY(30) PORT_KEYDELTA(40) PORT_PLAYER(1)
473	473
474		PORT_START /* S~~tick~~ 2 (5) */
	474	PORT_START_TAG(STICK2_PORT_TAG)
475	475	PORT_BIT( 0xffff, 0x0000, IPT_AD_STICK_Y ) PORT_MINMAX(0xf800,0x7ff) PORT_SENSITIVITY(30) PORT_KEYDELTA(40) PORT_PLAYER(1)
476	476
477		PORT_START /* S~~tick~~ 3 (6) */
	477	PORT_START_TAG(STICK3_PORT_TAG)
478	478	PORT_BIT( 0xffff, 0x0000, IPT_AD_STICK_Y ) PORT_MINMAX(0xf800,0x7ff) PORT_SENSITIVITY(30) PORT_KEYDELTA(40) PORT_PLAYER(2)
479	479	INPUT_PORTS_END
480	480
481	481	INPUT_PORTS_START( ainferno )
482		PORT_START /* DSWA */
	482	/* 0xa00200 -> 0x0c0003.b (-$7ffd,A5) */
	483	PORT_START_TAG("DSWA")
483	484	PORT_DIPNAME( 0x01, 0x01, "Moving Control" ) PORT_DIPLOCATION("SWA:1")
484	485	PORT_DIPSETTING( 0x01, "Upright/Cockpit" )
485	486	PORT_DIPSETTING( 0x00, "DX Moving Only" )
486	487	PORT_DIPNAME( 0x02, 0x02, "Motion Test Mode" ) PORT_DIPLOCATION("SWA:2")
487	488	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
488	489	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
489		PORT_SERVICE_DIPLOC( 0x04, IP_ACTIVE_LOW, "SWA:3" )
490		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SWA:4")
491		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
492		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
493		TAITO_COINAGE_US_8 // according to the manual this should be the same as COINAGE_JAPAN_8, but it's not!
	490	TAITO_DSWA_BITS_2_TO_3_LOC(SWA)
	491	TAITO_COINAGE_US_LOC(SWA)
494	492
495		PORT_START /* DSWB */
496		TAITO_DIFFICULTY_8
	493	/* 0xa00202 -> 0x0c0004.b (-$7ffc,A5) */
	494	PORT_START_TAG("DSWB")
	495	TAITO_DIFFICULTY_LOC(SWA)
497	496	PORT_DIPNAME( 0x0c, 0x0c, "Timer Length" ) PORT_DIPLOCATION("SWB:3,4")
498	497	PORT_DIPSETTING( 0x08, DEF_STR( Easy ) )
499	498	PORT_DIPSETTING( 0x0c, DEF_STR( Medium ) )
r894	r895
506	505	PORT_DIPUNUSED_DIPLOC( 0x40, IP_ACTIVE_LOW, "SWB:7" )
507	506	PORT_DIPUNUSED_DIPLOC( 0x80, IP_ACTIVE_LOW, "SWB:8" )
508	507
509		PORT_START /* IN0 */
	508	PORT_START_TAG("IN0")
510	509	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
511	510	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
512	511	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN1 )
r894	r895
516	515	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
517	516	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
518	517
519		PORT_START /* IN1 */
	518	PORT_START_TAG("IN1")
520	519	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) /* lever */
521	520	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1) /* handle x */
522	521	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) /* handle y */
523	522	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1) /* fire */
524	523	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_PLAYER(1) /* pedal r */
525	524	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_PLAYER(1) /* pedal l */
526		PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_~~BUTT~~ON7 ) PORT_PLAYER(~~1) /* f~~reeze (~~code at $7d6 hangs~~) */
	525	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Freeze") PORT_CODE(KEYCODE_F1)
527	526	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
528	527
529	528	/* The range of these sticks reflects the range test mode displays.
r894	r895
531	530	in the stick_r routines. And fake DSW with self-centering option
532	531	to make keyboard control feasible! */
533	532
534		PORT_START /* S~~tick~~ 1 (4) */
	533	PORT_START_TAG(STICK1_PORT_TAG)
535	534	PORT_BIT( 0xffff, 0x0000, IPT_AD_STICK_X ) PORT_MINMAX(0xf800,0x7ff) PORT_SENSITIVITY(30) PORT_KEYDELTA(40) PORT_PLAYER(1)
536	535
537		PORT_START /* S~~tick~~ 2 (5) */
	536	PORT_START_TAG(STICK2_PORT_TAG)
538	537	PORT_BIT( 0xffff, 0x0000, IPT_AD_STICK_Y ) PORT_MINMAX(0xf800,0x7ff) PORT_SENSITIVITY(30) PORT_KEYDELTA(40) PORT_PLAYER(1)
539	538
540		PORT_START /* S~~tick~~ 3 (6) */
	539	PORT_START_TAG(STICK3_PORT_TAG)
541	540	PORT_BIT( 0xffff, 0x0000, IPT_AD_STICK_Y ) PORT_MINMAX(0xf800,0x7ff) PORT_SENSITIVITY(30) PORT_KEYDELTA(40) PORT_PLAYER(2)
542	541	INPUT_PORTS_END
543	542

src/mame/drivers/cubocd32.c
r894	r895
45	45	*/
46	46
47	47	#include "driver.h"
	48	#include "sound/custom.h"
	49	#include "includes/amiga.h"
	50	#include "cdrom.h"
	51	#include "sound/cdda.h"
48	52
49		VIDEO_START(cd32)
	53	/*
	54
	55	Akiko custom chip emulation
	56
	57	The Akiko chip has:
	58	- built in 1KB NVRAM
	59	- chunky to planar converter
	60	- custom CDROM controller
	61
	62	CDROM Commands:
	63	len does not include checksum byte,
	64	resp len does include checksum byte
	65
	66	x0: len = 0x01, resp len = 0x01
	67	x1: len = 0x02, resp len = 0x03
	68	x2: len = 0x01, resp len = 0x03 - Pause CD Audio
	69	x3: len = 0x01, resp len = 0x03 - Unpause CD Audio
	70	x4: len = 0x0C, resp len = 0x03 - CD Audio Play/Read CD Data/Seek
	71	x5: len = 0x02, resp len = 0x10 - Read TOC
	72	x6: len = 0x01, resp len = 0x10 - Get Next TOC entry
	73	x7: len = 0x01, resp len = 0x15 - Door Status
	74	x8: len = 0x04, resp len = 0x03
	75	x9: len = 0x01, resp len = 0x01
	76	xA: len = 0x00, resp len = 0x03 - Media Status: Response = 0A NN CK where NN = 0: no disk and NN = 1: disk inserted
	77	xB: len = 0x00, resp len = 0x01
	78	xC: len = 0x00, resp len = 0x01
	79	xD: len = 0x00, resp len = 0x01
	80	xE: len = 0x00, resp len = 0x01
	81	xF: len = 0x00, resp len = 0x01
	82	*/
	83
	84	#define LOG_AKIKO 0
	85	#define LOG_AKIKO_I2C 0
	86
	87	enum {
	88	I2C_WAIT = 0,
	89	I2C_DEVICEADDR,
	90	I2C_WORDADDR,
	91	I2C_DATA
	92	};
	93
	94	#define NVRAM_SIZE 1024
	95	/* max size of one write request */
	96	#define NVRAM_PAGE_SIZE 16
	97
	98	struct akiko_def
50	99	{
	100	/* chunky to planar converter */
	101	UINT32 c2p_input_buffer[8];
	102	UINT32 c2p_output_buffer[8];
	103	UINT32 c2p_input_index;
	104	UINT32 c2p_output_index;
	105
	106	/* i2c bus */
	107	int i2c_state;
	108	int i2c_bitcounter;
	109	int i2c_direction;
	110	int i2c_sda_dir_nvram;
	111	int i2c_scl_out;
	112	int i2c_scl_in;
	113	int i2c_scl_dir;
	114	int i2c_oscl;
	115	int i2c_sda_out;
	116	int i2c_sda_in;
	117	int i2c_sda_dir;
	118	int i2c_osda;
	119
	120	/* nvram */
	121	UINT8 nvram[NVRAM_SIZE];
	122	UINT8 nvram_writetmp[NVRAM_PAGE_SIZE];
	123	int nvram_address;
	124	int nvram_writeaddr;
	125	int nvram_rw;
	126	UINT8 nvram_byte;
	127
	128	/* cdrom */
	129	UINT32 cdrom_status[2];
	130	UINT32 cdrom_address[2];
	131	UINT8 cdrom_cmd_start;
	132	UINT8 cdrom_cmd_end;
	133	UINT8 cdrom_cmd_resp;
	134	cdrom_file *cdrom;
	135	} akiko;
	136
	137	void init_akiko(void)
	138	{
	139	akiko.c2p_input_index = 0;
	140	akiko.c2p_output_index = 0;
	141
	142	akiko.i2c_state = I2C_WAIT;
	143	akiko.i2c_bitcounter = -1;
	144	akiko.i2c_direction = -1;
	145	akiko.i2c_sda_dir_nvram = 0;
	146	akiko.i2c_scl_out = 0;
	147	akiko.i2c_scl_in = 0;
	148	akiko.i2c_scl_dir = 0;
	149	akiko.i2c_oscl = 0;
	150	akiko.i2c_sda_out = 0;
	151	akiko.i2c_sda_in = 0;
	152	akiko.i2c_sda_dir = 0;
	153	akiko.i2c_osda = 0;
	154
	155	akiko.nvram_address = 0;
	156	akiko.nvram_writeaddr = 0;
	157	akiko.nvram_rw = 0;
	158	akiko.nvram_byte = 0;
	159	memset( akiko.nvram, 0, NVRAM_SIZE );
	160
	161	akiko.cdrom_status[0] = akiko.cdrom_status[1] = 0;
	162	akiko.cdrom_address[0] = akiko.cdrom_address[1] = 0;
	163	akiko.cdrom_cmd_start = akiko.cdrom_cmd_end = akiko.cdrom_cmd_resp = 0;
	164	akiko.cdrom = cdrom_open(get_disk_handle(0));
51	165	}
52	166
53		~~VIDEO~~_U~~PDA~~T~~E(cd~~32)
	167	void akiko_c2p_write(UINT32 data)
54	168	{
	169	akiko.c2p_input_buffer[akiko.c2p_input_index] = data;
	170	akiko.c2p_input_index++;
	171	akiko.c2p_input_index &= 7;
	172	akiko.c2p_output_index = 0;
	173	}
	174
	175	UINT32 akiko_c2p_read(void)
	176	{
	177	UINT32 val;
	178
	179	if ( akiko.c2p_output_index == 0 )
	180	{
	181	int i;
	182
	183	for ( i = 0; i < 8; i++ )
	184	akiko.c2p_output_buffer[i] = 0;
	185
	186	for (i = 0; i < 8 * 32; i++) {
	187	if (akiko.c2p_input_buffer[7 - (i >> 5)] & (1 << (i & 31)))
	188	akiko.c2p_output_buffer[i & 7] \|= 1 << (i >> 3);
	189	}
	190	}
	191	akiko.c2p_input_index = 0;
	192	val = akiko.c2p_output_buffer[akiko.c2p_output_index];
	193	akiko.c2p_output_index++;
	194	akiko.c2p_output_index &= 7;
	195	return val;
	196	}
	197
	198	static void akiko_i2c( void )
	199	{
	200	akiko.i2c_sda_in = 1;
	201
	202	if ( !akiko.i2c_sda_dir_nvram && akiko.i2c_scl_out && akiko.i2c_oscl )
	203	{
	204	if ( !akiko.i2c_sda_out && akiko.i2c_osda ) /* START-condition? */
	205	{
	206	akiko.i2c_state = I2C_DEVICEADDR;
	207	akiko.i2c_bitcounter = 0;
	208	akiko.i2c_direction = -1;
	209	#if LOG_AKIKO_I2C
	210	logerror("START\n");
	211	#endif
	212	return;
	213	}
	214	else if ( akiko.i2c_sda_out && !akiko.i2c_osda ) /* STOP-condition? */
	215	{
	216	akiko.i2c_state = I2C_WAIT;
	217	akiko.i2c_bitcounter = -1;
	218	#if LOG_AKIKO_I2C
	219	logerror("STOP\n");
	220	#endif
	221	if ( akiko.i2c_direction > 0 )
	222	{
	223	memcpy( akiko.nvram + ( akiko.nvram_address & ~(NVRAM_PAGE_SIZE - 1) ), akiko.nvram_writetmp, NVRAM_PAGE_SIZE );
	224	akiko.i2c_direction = -1;
	225	#if LOG_AKIKO_I2C
	226	{
	227	int i;
	228
	229	logerror("NVRAM write address %04X:", akiko.nvram_address & ~(NVRAM_PAGE_SIZE - 1));
	230	for (i = 0; i < NVRAM_PAGE_SIZE; i++)
	231	logerror("%02X", akiko.nvram_writetmp[i]);
	232	logerror("\n");
	233	}
	234	#endif
	235	}
	236	return;
	237	}
	238	}
	239
	240	if ( akiko.i2c_bitcounter >= 0 )
	241	{
	242	if ( akiko.i2c_direction )
	243	{
	244	/* Amiga -> NVRAM */
	245	if ( akiko.i2c_scl_out && !akiko.i2c_oscl )
	246	{
	247	if ( akiko.i2c_bitcounter == 8 )
	248	{
	249	akiko.i2c_sda_in = 0; /* ACK */
	250
	251	if ( akiko.i2c_direction > 0 )
	252	{
	253	akiko.nvram_writetmp[akiko.nvram_writeaddr++] = akiko.nvram_byte;
	254	akiko.nvram_writeaddr &= (NVRAM_PAGE_SIZE - 1);
	255	akiko.i2c_bitcounter = 0;
	256	}
	257	else
	258	{
	259	akiko.i2c_bitcounter = -1;
	260	}
	261	}
	262	else
	263	{
	264	akiko.nvram_byte <<= 1;
	265	akiko.nvram_byte \|= akiko.i2c_sda_out;
	266	akiko.i2c_bitcounter++;
	267	}
	268	}
	269	}
	270	else
	271	{
	272	/* NVRAM -> Amiga */
	273	if ( akiko.i2c_scl_out && !akiko.i2c_oscl && akiko.i2c_bitcounter < 8 )
	274	{
	275	if ( akiko.i2c_bitcounter == 0 )
	276	akiko.nvram_byte = akiko.nvram[akiko.nvram_address];
	277
	278	akiko.i2c_sda_dir_nvram = 1;
	279	akiko.i2c_sda_in = (akiko.nvram_byte & 0x80) ? 1 : 0;
	280	akiko.nvram_byte <<= 1;
	281	akiko.i2c_bitcounter++;
	282
	283	if ( akiko.i2c_bitcounter == 8 )
	284	{
	285	#if LOG_AKIKO_I2C
	286	logerror("NVRAM sent byte %02X address %04X\n", akiko.nvram[akiko.nvram_address], akiko.nvram_address);
	287	#endif
	288	akiko.nvram_address++;
	289	akiko.nvram_address &= NVRAM_SIZE - 1;
	290	akiko.i2c_sda_dir_nvram = 0;
	291	}
	292	}
	293
	294	if ( !akiko.i2c_sda_out && akiko.i2c_sda_dir && !akiko.i2c_scl_out ) /* ACK from Amiga */
	295	akiko.i2c_bitcounter = 0;
	296	}
	297
	298	if ( akiko.i2c_bitcounter >= 0 )
	299	return;
	300	}
	301
	302	switch( akiko.i2c_state )
	303	{
	304	case I2C_DEVICEADDR:
	305	if ( ( akiko.nvram_byte & 0xf0 ) != 0xa0 )
	306	{
	307	#if LOG_AKIKO_I2C
	308	logerror("WARNING: I2C_DEVICEADDR: device address != 0xA0\n");
	309	#endif
	310	akiko.i2c_state = I2C_WAIT;
	311	return;
	312	}
	313
	314	akiko.nvram_rw = (akiko.nvram_byte & 1) ? 0 : 1;
	315
	316	if ( akiko.nvram_rw )
	317	{
	318	/* 2 high address bits, only fetched if WRITE = 1 */
	319	akiko.nvram_address &= 0xff;
	320	akiko.nvram_address \|= ((akiko.nvram_byte >> 1) & 3) << 8;
	321	akiko.i2c_state = I2C_WORDADDR;
	322	akiko.i2c_direction = -1;
	323	}
	324	else
	325	{
	326	akiko.i2c_state = I2C_DATA;
	327	akiko.i2c_direction = 0;
	328	akiko.i2c_sda_dir_nvram = 1;
	329	}
	330
	331	akiko.i2c_bitcounter = 0;
	332	#if LOG_AKIKO_I2C
	333	logerror("I2C_DEVICEADDR: rw %d, address %02Xxx\n", akiko.nvram_rw, akiko.nvram_address >> 8);
	334	#endif
	335	break;
	336
	337	case I2C_WORDADDR:
	338	akiko.nvram_address &= 0x300;
	339	akiko.nvram_address \|= akiko.nvram_byte;
	340
	341	#if LOG_AKIKO_I2C
	342	logerror("I2C_WORDADDR: address %04X\n", akiko.nvram_address);
	343	#endif
	344	if ( akiko.i2c_direction < 0 )
	345	{
	346	memcpy( akiko.nvram_writetmp, akiko.nvram + (akiko.nvram_address & ~(NVRAM_PAGE_SIZE - 1)), NVRAM_PAGE_SIZE);
	347	akiko.nvram_writeaddr = akiko.nvram_address & (NVRAM_PAGE_SIZE - 1);
	348	}
	349
	350	akiko.i2c_state = I2C_DATA;
	351	akiko.i2c_bitcounter = 0;
	352	akiko.i2c_direction = 1;
	353	break;
	354	}
	355	}
	356
	357	void akiko_nvram_write(UINT32 data)
	358	{
	359	int sda;
	360
	361	akiko.i2c_oscl = akiko.i2c_scl_out;
	362	akiko.i2c_scl_out = BIT(data,31);
	363	akiko.i2c_osda = akiko.i2c_sda_out;
	364	akiko.i2c_sda_out = BIT(data,30);
	365	akiko.i2c_scl_dir = BIT(data,15);
	366	akiko.i2c_sda_dir = BIT(data,14);
	367
	368	sda = akiko.i2c_sda_out;
	369	if ( akiko.i2c_oscl != akiko.i2c_scl_out \|\| akiko.i2c_osda != sda )
	370	{
	371	akiko_i2c();
	372	akiko.i2c_oscl = akiko.i2c_scl_out;
	373	akiko.i2c_osda = sda;
	374	}
	375	}
	376
	377	UINT32 akiko_nvram_read(void)
	378	{
	379	UINT32 v = 0;
	380
	381	if ( !akiko.i2c_scl_dir )
	382	v \|= akiko.i2c_scl_in ? (1<<31) : 0x00;
	383	else
	384	v \|= akiko.i2c_scl_out ? (1<<31) : 0x00;
	385
	386	if ( !akiko.i2c_sda_dir )
	387	v \|= akiko.i2c_sda_in ? (1<<30) : 0x00;
	388	else
	389	v \|= akiko.i2c_sda_out ? (1<<30) : 0x00;
	390
	391	v \|= akiko.i2c_scl_dir ? (1<<15) : 0x00;
	392	v \|= akiko.i2c_sda_dir ? (1<<14) : 0x00;
	393
	394	return v;
	395	}
	396
	397	static const char* akiko_reg_names[] =
	398	{
	399	/0/ "ID",
	400	/1/ "CDROM STATUS 1",
	401	/2/ "CDROM_STATUS 2",
	402	/3/ "???",
	403	/4/ "CDROM ADDRESS 1",
	404	/5/ "CDROM ADDRESS 2",
	405	/6/ "CDROM COMMAND 1",
	406	/7/ "CDROM COMMAND 2",
	407	/8/ "CDROM READMASK",
	408	/9/ "CDROM LONGMASK",
	409	/A/ "???",
	410	/B/ "???",
	411	/C/ "NVRAM",
	412	/D/ "???",
	413	/E/ "C2P"
	414	};
	415
	416	const char* get_akiko_reg_name(int reg)
	417	{
	418	if (reg < 0xf )
	419	{
	420	return akiko_reg_names[reg];
	421	}
	422	else
	423	{
	424	return "???";
	425	}
	426	}
	427
	428	static void akiko_setup_response( int len, int r0, UINT8 *r1 )
	429	{
	430	int resp_addr = akiko.cdrom_address[1];
	431	UINT8 resp_csum = 0xff;
	432	UINT8 resp_buffer[32];
	433	int i;
	434
	435	memset( resp_buffer, 0, sizeof( resp_buffer ) );
	436
	437	resp_buffer[0] = r0;
	438
	439	for( i = 0; i < len; i++ )
	440	{
	441	resp_buffer[i+1] = r1[i];
	442	resp_csum -= resp_buffer[i];
	443	}
	444
	445	resp_buffer[len] = resp_csum;
	446	len++;
	447
	448	for( i = 0; i < len; i++ )
	449	{
	450	program_write_byte( resp_addr + ((akiko.cdrom_cmd_resp + i) & 0xff), resp_buffer[i] );
	451	}
	452
	453	akiko.cdrom_cmd_resp = (akiko.cdrom_cmd_resp+len) & 0xff;
	454
	455	akiko.cdrom_status[0] \|= 0x10000000; /* new data available */
	456	}
	457
	458	static TIMER_CALLBACK( akiko_cd_delayed_cmd )
	459	{
	460	UINT8 resp[32];
	461
	462	memset( resp, 0, sizeof( resp ) );
	463
	464	if ( param == 0x05 )
	465	{
	466	logerror( "AKIKO: Completing Command %d\n", param );
	467
	468	if ( akiko.cdrom == NULL \|\| cdrom_get_last_track(akiko.cdrom) == 0 )
	469	{
	470	resp[0] = 0x80;
	471	akiko_setup_response( 2, param, resp );
	472	}
	473	else
	474	{
	475	int addrctrl = cdrom_get_adr_control( akiko.cdrom, 0 );
	476	UINT32 trackstart = lba_to_msf(cdrom_get_track_start( akiko.cdrom, 0 ));
	477
	478	resp[0] = 0x00;
	479	resp[1] = ((addrctrl & 0x0f) << 4) \| ((addrctrl & 0xf0) >> 4);
	480	/* 2-3: track number in BCD format */
	481	/* 4-7: ??? */
	482	resp[8] = (trackstart >> 16) & 0xff;
	483	resp[9] = (trackstart >> 8) & 0xff;
	484	resp[10] = trackstart & 0xff;
	485
	486	akiko_setup_response( 15, param, resp );
	487	}
	488	}
	489	}
	490
	491	static void akiko_update_cdrom( void )
	492	{
	493	UINT8 resp[32];
	494
	495	if ( akiko.cdrom_status[0] & 0x10000000 )
	496	return;
	497
	498	while ( akiko.cdrom_cmd_start < akiko.cdrom_cmd_end )
	499	{
	500	int cmd_addr = akiko.cdrom_address[1] + 0x200 + akiko.cdrom_cmd_start;
	501	int cmd = program_read_byte( cmd_addr );
	502
	503	cmd &= 0x0f;
	504
	505	logerror( "CDROM command: %02X\n", cmd );
	506
	507	memset( resp, 0, sizeof( resp ) );
	508
	509	if ( cmd == 0x05 ) /* read toc */
	510	{
	511	akiko.cdrom_cmd_start = (akiko.cdrom_cmd_start+3) & 0xff;
	512
	513	mame_timer_set( MAME_TIME_IN_MSEC(500), cmd, akiko_cd_delayed_cmd );
	514
	515	break;
	516	}
	517	else if ( cmd == 0x07 ) /* check door status */
	518	{
	519	resp[0] = 0x01;
	520
	521	akiko.cdrom_cmd_start = (akiko.cdrom_cmd_start+2) & 0xff;
	522
	523	if ( akiko.cdrom == NULL \|\| cdrom_get_last_track(akiko.cdrom) == 0 )
	524	resp[0] = 0x80;
	525
	526	akiko_setup_response( 20, cmd, resp );
	527	break;
	528	}
	529	else
	530	{
	531	break;
	532	}
	533	}
	534	}
	535
	536	READ32_HANDLER(amiga_akiko32_r)
	537	{
	538	UINT32 retval;
	539	if ( offset < (0x30/4) )
	540	{
	541	if ( LOG_AKIKO ) logerror( "Reading AKIKO reg %0x [%s] at PC=%06x\n", offset, get_akiko_reg_name(offset), activecpu_get_pc() );
	542	}
	543
	544	switch( offset )
	545	{
	546	case 0x00/4: /* ID */
	547	init_akiko();
	548	return 0x0000cafe;
	549
	550	case 0x04/4: /* CDROM STATUS 1 */
	551	return akiko.cdrom_status[0];
	552
	553	case 0x08/4: /* CDROM STATUS 2 */
	554	return akiko.cdrom_status[1];
	555
	556	case 0x10/4: /* CDROM ADDRESS 1 */
	557	return akiko.cdrom_address[0];
	558
	559	case 0x14/4: /* CDROM ADDRESS 2 */
	560	return akiko.cdrom_address[1];
	561
	562	case 0x18/4: /* CDROM COMMAND 1 */
	563	akiko_update_cdrom();
	564	retval = akiko.cdrom_cmd_start;
	565	retval <<= 8;
	566	retval \|= akiko.cdrom_cmd_resp;
	567	retval <<= 8;
	568	return retval;
	569
	570	case 0x1C/4: /* CDROM COMMAND 2 */
	571	akiko_update_cdrom();
	572	retval = akiko.cdrom_cmd_end;
	573	retval <<= 16;
	574	return retval;
	575
	576	case 0x30/4: /* NVRAM */
	577	return akiko_nvram_read();
	578
	579	case 0x38/4: /* C2P */
	580	return akiko_c2p_read();
	581
	582	default:
	583	break;
	584	}
	585
55	586	return 0;
56	587	}
57	588
	589	WRITE32_HANDLER(amiga_akiko32_w)
	590	{
	591	if ( offset < (0x30/4) )
	592	{
	593	if ( LOG_AKIKO ) logerror( "Writing AKIKO reg %0x [%s] with %08x at PC=%06x\n", offset, get_akiko_reg_name(offset), data, activecpu_get_pc() );
	594	}
	595
	596	switch( offset )
	597	{
	598	case 0x04/4: /* CDROM STATUS 1 */
	599	akiko.cdrom_status[0] = data;
	600	break;
	601
	602	case 0x08/4: /* CDROM STATUS 2 */
	603	akiko.cdrom_status[1] = data;
	604	akiko.cdrom_status[0] &= data;
	605	break;
	606
	607	case 0x10/4: /* CDROM ADDRESS 1 */
	608	akiko.cdrom_address[0] = data;
	609	break;
	610
	611	case 0x14/4: /* CDROM ADDRESS 2 */
	612	akiko.cdrom_address[1] = data;
	613	break;
	614
	615	case 0x18/4: /* CDROM COMMAND 1 */
	616	if ( ( mem_mask & 0x00ff0000 ) == 0 )
	617	akiko.cdrom_cmd_start = ( data >> 16 ) & 0xff;
	618
	619	if ( ( mem_mask & 0x0000ff00 ) == 0 )
	620	akiko.cdrom_cmd_resp = ( data >> 8 ) & 0xff;
	621
	622	akiko_update_cdrom();
	623	break;
	624
	625	case 0x1C/4: /* CDROM COMMAND 2 */
	626	if ( ( mem_mask & 0x00ff0000 ) == 0 )
	627	akiko.cdrom_cmd_end = ( data >> 16 ) & 0xff;
	628
	629	akiko_update_cdrom();
	630	break;
	631
	632	case 0x30/4:
	633	akiko_nvram_write(data);
	634	break;
	635
	636	case 0x38/4:
	637	akiko_c2p_write(data);
	638	break;
	639
	640	default:
	641	break;
	642	}
	643	}
	644
	645	static READ32_HANDLER(amiga_cia32_r)
	646	{
	647	UINT32 retval = 0;
	648
	649	#if 0
	650	if ( (mem_mask & 0xffff) != 0xffff)
	651	retval \|= (amiga_cia_r(offset*2, mem_mask & 0xffff) );
	652
	653	if ( ((mem_mask >> 16) & 0xffff) != 0xffff)
	654	retval \|= (amiga_cia_r(offset*2 + 1, mem_mask >> 16) << 16);
	655	#else
	656	if ( ((mem_mask >> 16) & 0xffff) != 0xffff)
	657	{
	658	retval \|= amiga_cia_r(offset*2, (mem_mask >> 16) & 0xffff);
	659	retval <<= 16;
	660	}
	661
	662	if ( (mem_mask & 0xffff) != 0xffff )
	663	retval \|= amiga_cia_r(offset*2 + 1, mem_mask & 0xffff);
	664
	665	return retval;
	666	#endif
	667
	668	return retval;
	669	}
	670
	671	static WRITE32_HANDLER(amiga_cia32_w)
	672	{
	673	// amiga_cia_w(offset*2, data >> 16, mem_mask >> 16 );
	674	if ( ((mem_mask >> 16) & 0xffff) != 0xffff)
	675	amiga_cia_w(offset*2, data >> 16, mem_mask >> 16 );
	676
	677	if ( (mem_mask & 0xffff) != 0xffff )
	678	amiga_cia_w(offset*2 + 1, data & 0xffff, mem_mask & 0xffff );
	679	}
	680
	681	static READ32_HANDLER(amiga_custom32_r)
	682	{
	683	UINT32 retval = 0;
	684
	685	if ( ((mem_mask >> 16) & 0xffff) != 0xffff)
	686	{
	687	retval \|= amiga_custom_r(offset*2, (mem_mask >> 16) & 0xffff);
	688	retval <<= 16;
	689	}
	690
	691	if ( (mem_mask & 0xffff) != 0xffff )
	692	retval \|= amiga_custom_r(offset*2 + 1, mem_mask & 0xffff);
	693
	694	return retval;
	695	}
	696
	697	static WRITE32_HANDLER(amiga_custom32_w)
	698	{
	699	if ( ((mem_mask >> 16) & 0xffff) != 0xffff)
	700	amiga_custom_w(offset*2, data >> 16, mem_mask >> 16 );
	701
	702	if ( (mem_mask & 0xffff) != 0xffff )
	703	amiga_custom_w(offset*2 + 1, data & 0xffff, mem_mask & 0xffff );
	704	}
	705
	706	/*************************************
	707	*
	708	* CIA-A port A access:
	709	*
	710	* PA7 = game port 1, pin 6 (fire)
	711	* PA6 = game port 0, pin 6 (fire)
	712	* PA5 = /RDY (disk ready)
	713	* PA4 = /TK0 (disk track 00)
	714	* PA3 = /WPRO (disk write protect)
	715	* PA2 = /CHNG (disk change)
	716	* PA1 = /LED (LED, 0=bright / audio filter control)
	717	* PA0 = OVL (ROM/RAM overlay bit)
	718	*
	719	*************************************/
	720
	721	static UINT8 cd32_cia_0_porta_r(void)
	722	{
	723	return readinputportbytag("CIA0PORTA");
	724	}
	725
	726	static void cd32_cia_0_porta_w(UINT8 data)
	727	{
	728	/* switch banks as appropriate */
	729	memory_set_bank(1, data & 1);
	730
	731	/* swap the write handlers between ROM and bank 1 based on the bit */
	732	if ((data & 1) == 0)
	733	/* overlay disabled, map RAM on 0x000000 */
	734	memory_install_write32_handler(0, ADDRESS_SPACE_PROGRAM, 0x000000, 0x1fffff, 0, 0, MWA32_BANK1);
	735
	736	else
	737	/* overlay enabled, map Amiga system ROM on 0x000000 */
	738	memory_install_write32_handler(0, ADDRESS_SPACE_PROGRAM, 0x000000, 0x1fffff, 0, 0, MWA32_ROM);
	739
	740	/* bit 2 = Power Led on Amiga */
	741	set_led_status(0, (data & 2) ? 0 : 1);
	742	}
	743
	744	/*************************************
	745	*
	746	* CIA-A port B access:
	747	*
	748	* PB7 = parallel data 7
	749	* PB6 = parallel data 6
	750	* PB5 = parallel data 5
	751	* PB4 = parallel data 4
	752	* PB3 = parallel data 3
	753	* PB2 = parallel data 2
	754	* PB1 = parallel data 1
	755	* PB0 = parallel data 0
	756	*
	757	*************************************/
	758
	759	static UINT8 cd32_cia_0_portb_r(void)
	760	{
	761	/* parallel port */
	762	logerror("%06x:CIA0_portb_r\n", activecpu_get_pc());
	763	return 0xff;
	764	}
	765
	766	static void cd32_cia_0_portb_w(UINT8 data)
	767	{
	768	/* parallel port */
	769	logerror("%06x:CIA0_portb_w(%02x)\n", activecpu_get_pc(), data);
	770	}
	771
	772	static NVRAM_HANDLER( cd32 )
	773	{
	774	if (read_or_write)
	775	/* save the SRAM settings */
	776	mame_fwrite(file, akiko.nvram, NVRAM_SIZE);
	777	else
	778	{
	779	/* load the SRAM settings */
	780	if (file)
	781	mame_fread(file, akiko.nvram, NVRAM_SIZE);
	782	else
	783	memset(akiko.nvram, 0, NVRAM_SIZE);
	784	}
	785	}
	786
58	787	static ADDRESS_MAP_START( cd32_map, ADDRESS_SPACE_PROGRAM, 32 )
59	788	ADDRESS_MAP_FLAGS( AMEF_UNMAP(1) )
	789	AM_RANGE(0x000000, 0x1fffff) AM_RAMBANK(1) AM_BASE(&amiga_chip_ram32) AM_SIZE(&amiga_chip_ram_size)
	790	AM_RANGE(0xb80000, 0xb8003f) AM_READWRITE(amiga_akiko32_r, amiga_akiko32_w)
	791	AM_RANGE(0xbfd000, 0xbfefff) AM_READWRITE(amiga_cia32_r, amiga_cia32_w)
	792	AM_RANGE(0xc00000, 0xdfffff) AM_READWRITE(amiga_custom32_r, amiga_custom32_w) AM_BASE((UINT32**)&amiga_custom_regs)
	793	AM_RANGE(0xe00000, 0xe7ffff) AM_ROM AM_REGION(REGION_USER1, 0x80000) /* CD32 Extended ROM */
	794	AM_RANGE(0xa00000, 0xf7ffff) AM_NOP
	795	AM_RANGE(0xf80000, 0xffffff) AM_ROM AM_REGION(REGION_USER1, 0x0) /* Kickstart */
60	796	ADDRESS_MAP_END
61	797
62	798
63	799
64	800	INPUT_PORTS_START( cd32 )
	801	PORT_START_TAG("CIA0PORTA")
	802	PORT_BIT( 0x3f, IP_ACTIVE_LOW, IPT_SPECIAL )
	803	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 )
	804	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
	805
	806	PORT_START_TAG("CIA0PORTB")
	807	PORT_DIPNAME( 0x01, 0x01, "DSW1 1" )
	808	PORT_DIPSETTING( 0x01, "Reset" )
	809	PORT_DIPSETTING( 0x00, "Set" )
	810	PORT_SERVICE_NO_TOGGLE( 0x02, IP_ACTIVE_LOW )
	811	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START2 )
	812	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
	813
	814	PORT_START_TAG("JOY0DAT")
	815	PORT_BIT( 0x0303, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(amiga_joystick_convert, "P1JOY")
	816	PORT_BIT( 0xfcfc, IP_ACTIVE_HIGH, IPT_UNUSED )
	817
	818	PORT_START_TAG("JOY1DAT")
	819	PORT_BIT( 0x0303, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(amiga_joystick_convert, "P2JOY")
	820	PORT_BIT( 0xfcfc, IP_ACTIVE_HIGH, IPT_UNUSED )
	821
	822	PORT_START_TAG("POTGO")
	823	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNUSED )
	824	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON2 )
	825	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_UNUSED )
	826	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
	827	PORT_BIT( 0xaaff, IP_ACTIVE_HIGH, IPT_UNUSED )
	828
	829	PORT_START_TAG("P1JOY")
	830	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
	831	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
	832	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
	833	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
	834
	835	PORT_START_TAG("P2JOY")
	836	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
	837	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
	838	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
	839	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
	840
	841	PORT_START_TAG("COINS")
	842	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )
	843	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )
65	844	INPUT_PORTS_END
66	845
	846	/*************************************
	847	*
	848	* Sound definitions
	849	*
	850	*************************************/
67	851
	852	static struct CustomSound_interface amiga_custom_interface =
	853	{
	854	amiga_sh_start
	855	};
	856
	857
68	858	static MACHINE_DRIVER_START( cd32 )
69	859
70	860	/* basic machine hardware */
71		MDRV_CPU_ADD(M68EC020, ~~1431~~818) /* 14.3 Mhz */
	861	MDRV_CPU_ADD(M68EC020, AMIGA_68EC020_NTSC_CLOCK) /* 14.3 Mhz */
72	862	MDRV_CPU_PROGRAM_MAP(cd32_map,0)
73		//MDRV_CPU_VBLANK_INT(amiga_scanline_callback, 262)
	863	MDRV_CPU_VBLANK_INT(amiga_scanline_callback, 262)
74	864
75	865	MDRV_SCREEN_REFRESH_RATE(59.997)
76	866	MDRV_SCREEN_VBLANK_TIME(USEC_TO_SUBSECONDS(0))
77	867
78		//MDRV_MACHINE_RESET(amiga)
79		//MDRV_NVRAM_HANDLER(generic_0fill)
	868	MDRV_MACHINE_RESET(amiga)
	869	MDRV_NVRAM_HANDLER(cd32)
80	870
81	871	/* video hardware */
82	872	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER \| VIDEO_UPDATE_BEFORE_VBLANK)
r894	r895
84	874	MDRV_SCREEN_SIZE(512*2, 262)
85	875	MDRV_SCREEN_VISIBLE_AREA((129-8)2, (449+8-1)2, 44-8, 244+8-1)
86	876	MDRV_PALETTE_LENGTH(4096)
87		//MDRV_PALETTE_INIT(amiga)
	877	MDRV_PALETTE_INIT(amiga)
88	878
89		MDRV_VIDEO_START(cd32)
90		MDRV_VIDEO_UPDATE(cd32)
	879	MDRV_VIDEO_START(amiga)
	880	MDRV_VIDEO_UPDATE(generic_bitmapped)
91	881
92	882	/* sound hardware */
93		/*
94	883	MDRV_SPEAKER_STANDARD_STEREO("left", "right")
95	884
96	885	MDRV_SOUND_ADD(CUSTOM, 3579545)
r894	r895
99	888	MDRV_SOUND_ROUTE(1, "right", 0.50)
100	889	MDRV_SOUND_ROUTE(2, "right", 0.50)
101	890	MDRV_SOUND_ROUTE(3, "left", 0.50)
102		*/
103	891	MACHINE_DRIVER_END
104	892
105	893
r894	r895
107	895	#define ROM_LOAD16_WORD_BIOS(bios,name,offset,length,hash) ROMX_LOAD(name, offset, length, hash, ROM_BIOS(bios+1))
108	896
109	897	#define CD32_BIOS \
110		ROM_REGION16_BE(0x100000, REGION_USER1, 0 ) \
	898	ROM_REGION32_BE(0x100000, REGION_USER1, 0 ) \
111	899	ROM_SYSTEM_BIOS(0, "cd32", "Kickstart v3.1 rev 40.60 with CD32 Extended-ROM" ) \
112	900	ROM_LOAD16_WORD_BIOS(0, "391640-03.u6a", 0x000000, 0x100000, CRC(d3837ae4) SHA1(06807db3181637455f4d46582d9972afec8956d9) ) \
113	901
r894	r895
158	946	DISK_IMAGE_READONLY( "lasstixx", 0, SHA1(29c2525d43a696da54648caffac9952cec85fd37) MD5(6242dd8a3c0b15ef9eafb930b7a7e87f) )
159	947	ROM_END
160	948
	949	/***************************************************************************************************/
	950
	951	static DRIVER_INIT( cd32 )
	952	{
	953	static const amiga_machine_interface cubocd32_intf =
	954	{
	955	AGA_CHIP_RAM_MASK,
	956	cd32_cia_0_porta_r, cd32_cia_0_portb_r,
	957	cd32_cia_0_porta_w, cd32_cia_0_portb_w,
	958	NULL, NULL,
	959	NULL, NULL,
	960	NULL, NULL, NULL,
	961	NULL, NULL, NULL,
	962	NULL, NULL,
	963	NULL,
	964	FLAGS_AGA_CHIPSET
	965	};
	966
	967	/* configure our Amiga setup */
	968	amiga_machine_config(&cubocd32_intf);
	969
	970	/* set up memory */
	971	memory_configure_bank(1, 0, 1, amiga_chip_ram32, 0);
	972	memory_configure_bank(1, 1, 1, memory_region(REGION_USER1), 0);
	973	}
	974
	975	/***************************************************************************************************/
	976
161	977	/* BIOS */
162		GAMEB( 1993, cd32, 0, cd32, cd32, cd32, 0, ROT0, "Commodore", "Amiga CD32 Bios", GAME_IS_BIOS_ROOT )
	978	GAMEB( 1993, cd32, 0, cd32, cd32, cd32, cd32, ROT0, "Commodore", "Amiga CD32 Bios", GAME_IS_BIOS_ROOT )
163	979
164		GAMEB( 1995, cndypuzl, cd32, cd32, cd32, cd32, 0, ROT0, "CD Express", "Candy Puzzle (v1.0)", GAME_NOT_WORKING\|GAME_NO_SOUND )
165		GAMEB( 1995, haremchl, cd32, cd32, cd32, cd32, 0, ROT0, "CD Express", "Harem Challenge", GAME_NOT_WORKING\|GAME_NO_SOUND )
166		GAMEB( 1995, lsrquiz, cd32, cd32, cd32, cd32, 0, ROT0, "CD Express", "Laser Quiz", GAME_NOT_WORKING\|GAME_NO_SOUND )
167		GAMEB( 1995, lsrquiz2, cd32, cd32, cd32, cd32, 0, ROT0, "CD Express", "Laser Quiz '2' Italy (v1.0)", GAME_NOT_WORKING\|GAME_NO_SOUND )
168		GAMEB( 1996, mgprem11, cd32, cd32, cd32, cd32, 0, ROT0, "CD Express", "Magic Premium (v1.1)", GAME_NOT_WORKING\|GAME_NO_SOUND )
169		GAMEB( 1995, lasstixx, cd32, cd32, cd32, cd32, 0, ROT0, "CD Express", "Laser Strixx", GAME_NOT_WORKING\|GAME_NO_SOUND )
	980	GAMEB( 1995, cndypuzl, cd32, cd32, cd32, cd32, cd32, ROT0, "CD Express", "Candy Puzzle (v1.0)", GAME_NOT_WORKING\|GAME_NO_SOUND )
	981	GAMEB( 1995, haremchl, cd32, cd32, cd32, cd32, cd32, ROT0, "CD Express", "Harem Challenge", GAME_NOT_WORKING\|GAME_NO_SOUND )
	982	GAMEB( 1995, lsrquiz, cd32, cd32, cd32, cd32, cd32, ROT0, "CD Express", "Laser Quiz", GAME_NOT_WORKING\|GAME_NO_SOUND )
	983	GAMEB( 1995, lsrquiz2, cd32, cd32, cd32, cd32, cd32, ROT0, "CD Express", "Laser Quiz '2' Italy (v1.0)", GAME_NOT_WORKING\|GAME_NO_SOUND )
	984	GAMEB( 1996, mgprem11, cd32, cd32, cd32, cd32, cd32, ROT0, "CD Express", "Magic Premium (v1.1)", GAME_NOT_WORKING\|GAME_NO_SOUND )
	985	GAMEB( 1995, lasstixx, cd32, cd32, cd32, cd32, cd32, ROT0, "CD Express", "Laser Strixx", GAME_NOT_WORKING\|GAME_NO_SOUND )

src/mame/drivers/plygonet.c
r894	r895
16	16	TTL text plane similar to Run and Gun.
17	17	Konami K054009(x2) + K054010(x2) (polygon rasterizers)
18	18	Konami K053936 "PSAC2" (3d roz plane, used for backgrounds)
	19	24.0 MHz crystal to drive the video hardware
19	20
20	21	Driver includes:
21	22	- 68020 memory map
r894	r895
687	688	MDRV_CPU_PROGRAM_MAP(polygonet_map, 0)
688	689	MDRV_CPU_VBLANK_INT(polygonet_interrupt, 2)
689	690
690		MDRV_CPU_ADD(DSP56156, 10000000) /* no idea */
	691	MDRV_CPU_ADD(DSP56156, 10000000) /* should be 40.0 MHz */
691	692	MDRV_CPU_FLAGS(CPU_DISABLE)
692	693	MDRV_CPU_PROGRAM_MAP(dsp56156_p_map, 0)
693	694	MDRV_CPU_DATA_MAP(dsp56156_d_map, 0)
r894	r895
798	799	ROM_START( plygonet )
799	800	/* main program */
800	801	ROM_REGION( 0x200000, REGION_CPU1, 0)
801		ROM_LOAD32_BYTE( "305a01.bin", 0x000003, 512*1024, CRC(8bdb6c95) SHA1(e981833842f8fd89b9726901fbe2058444204792) )
802		ROM_LOAD32_BYTE( "305a02.bin", 0x000002, 512*1024, CRC(4d7e32b3) SHA1(25731526535036972577637d186f02ae467296bd) )
803		ROM_LOAD32_BYTE( "305a03.bin", 0x000001, 512*1024, CRC(36e4e3fe) SHA1(e8fcad4f196c9b225a0fbe70791493ff07c648a9) )
804		ROM_LOAD32_BYTE( "305a04.bin", 0x000000, 512*1024, CRC(d8394e72) SHA1(eb6bcf8aedb9ba5843204ab8aacb735cbaafb74d) )
	802	ROM_LOAD32_BYTE( "305a01.4k", 0x000003, 512*1024, CRC(8bdb6c95) SHA1(e981833842f8fd89b9726901fbe2058444204792) )
	803	ROM_LOAD32_BYTE( "305a02.2k", 0x000002, 512*1024, CRC(4d7e32b3) SHA1(25731526535036972577637d186f02ae467296bd) )
	804	ROM_LOAD32_BYTE( "305a03.2h", 0x000001, 512*1024, CRC(36e4e3fe) SHA1(e8fcad4f196c9b225a0fbe70791493ff07c648a9) )
	805	ROM_LOAD32_BYTE( "305a04.4h", 0x000000, 512*1024, CRC(d8394e72) SHA1(eb6bcf8aedb9ba5843204ab8aacb735cbaafb74d) )
805	806
806	807	/* Z80 sound program */
807	808	ROM_REGION( 0x30000, REGION_CPU3, 0 )
808		ROM_LOAD("305b05.bin", 0x000000, 0x20000, CRC(2d3d9654) SHA1(784a409df47cee877e507b8bbd3610d161d63753) )
	809	ROM_LOAD("305b05.7b", 0x000000, 0x20000, CRC(2d3d9654) SHA1(784a409df47cee877e507b8bbd3610d161d63753) )
809	810	ROM_RELOAD( 0x10000, 0x20000)
810	811
811	812	/* TTL text plane tiles */
812	813	ROM_REGION( 0x20000, REGION_GFX1, 0 )
813		ROM_LOAD( "305b06.~~bin~~", 0x000000, 0x20000, CRC(decd6e42) SHA1(4c23dcb1d68132d3381007096e014ee4b6007086) )
	814	ROM_LOAD( "305b06.18g", 0x000000, 0x20000, CRC(decd6e42) SHA1(4c23dcb1d68132d3381007096e014ee4b6007086) )
814	815
815	816	/* '936 tiles */
816	817	ROM_REGION( 0x40000, REGION_GFX2, 0 )
817		ROM_LOAD( "305b07.~~bin~~", 0x000000, 0x40000, CRC(e4320bc3) SHA1(b0bb2dac40d42f97da94516d4ebe29b1c3d77c37) )
	818	ROM_LOAD( "305b07.20d", 0x000000, 0x40000, CRC(e4320bc3) SHA1(b0bb2dac40d42f97da94516d4ebe29b1c3d77c37) )
818	819
819	820	/* sound data */
820	821	ROM_REGION( 0x200000, REGION_SOUND1, 0 )
821		ROM_LOAD( "305b08.~~bin~~", 0x000000, 0x200000, CRC(874607df) SHA1(763b44a80abfbc355bcb9be8bf44373254976019) )
	822	ROM_LOAD( "305b08.2e", 0x000000, 0x200000, CRC(874607df) SHA1(763b44a80abfbc355bcb9be8bf44373254976019) )
822	823	ROM_END
823	824
824	825	/* ROM parent machine inp init */

src/mame/drivers/warriorb.c
r894	r895
112	112	- Sets :
113	113	* 'warriorb' : region = 0x0001
114	114	- Coinage relies on the region (code at 0x002614) :
115		* 0x000~~0 (?), 0x000~~1 (Japan) use TAITO_COINAGE_JAPAN_NEW
	115	* 0x0001 (Japan) uses TAITO_COINAGE_JAPAN_NEW
116	116	* 0x0002 (US) uses TAITO_COINAGE_US
117	117	* 0x0003 (World) uses TAITO_COINAGE_WORLD
118	118	- Additional Japanese text when region = 0x0001

src/mame/drivers/arcadia.c
r894	r895
289	289	static MACHINE_DRIVER_START( arcadia )
290	290
291	291	/* basic machine hardware */
292		MDRV_CPU_ADD(M68000, ~~7159~~090~~) /* 7.159~~0~~9 Mhz (~~NTSC) */
	292	MDRV_CPU_ADD(M68000, AMIGA_68000_NTSC_CLOCK)
293	293	MDRV_CPU_PROGRAM_MAP(amiga_map,0)
294	294	MDRV_CPU_VBLANK_INT(amiga_scanline_callback, 262)
295	295

src/mame/drivers/galaga.c
r894	r895
631	631	custom chips.
632	632
633	633	- differences between versions of digdug:
634		- the background graphics are slightly different in the Atari version, the earth is
	634	- the background graphics are slightly different in the Atari versions; the earth is
635	635	less regular.
636	636
637		- "digdugb" a~~nd "digduga~~1" ~~are~~ identical, apart from the gfx and copyright notices
	637	- "digduga1" is identical to "digdugb", apart from the gfx and copyright notices
638	638	changed from "NAMCO LTD." to "ATARI INC.".
639	639
640		- "digdug" is almost identical to "digdugat" (apart from the above changes), but
641		there are three more instructions in the latter that change the code alignment.
	640	- "digdug" fixes two bugs that were present in "digdugb": First, as monster speed
	641	increased in later rounds it could eventually roll over to 0, causing the monsters
	642	to stop moving altogether. Second, "double-killing" a monster by bursting it and
	643	immediately dropping a rock on the corpse could result in the round not ending
	644	even after all monsters were killed.
	645	This set also has the code to save high scores to EEPROM rewritten, though the
	646	reason for the changes is unclear.
642	647
	648	- "digdugat" is almost identical to "digdug" (apart from the Atari gfx/copyright
	649	changes), but there are three added instructions in the CPU0 program that change
	650	the code alignment. The change eliminates the "kill screen" at round 256 by
	651	making the round number roll over to 156, and hides the rollover from the player
	652	by only ever displaying the lower two digits of the round number. Interestingly,
	653	"digdug" actually contains all the code to implement the rollover (at $0018-$0026)
	654	but just doesn't call it, implying that Namco deliberately chose to keep the kill
	655	screen in this version.
	656
	657	- "digsid" is intermediate between "digdugb" and "digdug"; it has the changed EEPROM
	658	handling, but not the gameplay bug fixes. It has some unique changes as well:
	659	the initial high scores are 25000 instead of 10000, and the game begins on the
	660	screen that is round 4 in the other sets, skipping the first three screens.
	661	The latter change seems likely to have been done by Namco themselves and not by
	662	Sidam, as it involves insertion of code right in the middle of the CPU0 program
	663	and realignment of all the code after the insertion.
	664
643	665	- "dzigzag" and "digdugb" are identical, apart from the hacked gfx and the copyright
644		notices changed from "NAMCO LTD." to "1 9 8 2". It's a bottleg of "digdugb", and
	666	notices changed from "NAMCO LTD." to "1 9 8 2". It's a bootleg of "digdugb", and
645	667	not of "digduga1", because the hidden "NAMCO" string at offset 0x1eea of CPU2 is
646	668	still present, while it is replaced by "ATARI" in digduga1.
647	669	The only interesting thing about the bootleg is the 4th Z80, used to simulate
r894	r895
698	720	{
699	721	int bit0,bit1;
700	722
701		bit0 = (readinputport(3) >> offset) & 1;
702		bit1 = (readinputport(2) >> offset) & 1;
	723	bit0 = (readinputportbytag("DSWB") >> offset) & 1;
	724	bit1 = (readinputportbytag("DSWA") >> offset) & 1;
703	725
704	726	return bit0 \| (bit1 << 1);
705	727	}
r894	r895
753	775	}
754	776
755	777
756		static READ8_HANDLER( in0_l ) { return readinputport(0); } // fire and start buttons
757		static READ8_HANDLER( in0_h ) { return readinputport(0) >> 4; } // coins
758		static READ8_HANDLER( in1_l ) { return readinputport(1); } // P1 joystick
759		static READ8_HANDLER( in1_h ) { return readinputport(1) >> 4; } // P2 joystick
760		static READ8_HANDLER( dipA_l ) { return readinputport(2); } // dips A
761		static READ8_HANDLER( dipA_h ) { return readinputport(2) >> 4; } // dips A
762		static READ8_HANDLER( dipB_l ) { return readinputport(3); } // dips B
763		static READ8_HANDLER( dipB_h ) { return readinputport(3) >> 4; } // dips B
	778	static READ8_HANDLER( in0_l ) { return readinputportbytag("IN0"); } // fire and start buttons
	779	static READ8_HANDLER( in0_h ) { return readinputportbytag("IN0") >> 4; } // coins
	780	static READ8_HANDLER( in1_l ) { return readinputportbytag("IN1"); } // P1 joystick
	781	static READ8_HANDLER( in1_h ) { return readinputportbytag("IN1") >> 4; } // P2 joystick
	782	static READ8_HANDLER( dipA_l ) { return readinputportbytag("DSWA"); } // dips A
	783	static READ8_HANDLER( dipA_h ) { return readinputportbytag("DSWA") >> 4; } // dips A
	784	static READ8_HANDLER( dipB_l ) { return readinputportbytag("DSWB"); } // dips B
	785	static READ8_HANDLER( dipB_h ) { return readinputportbytag("DSWB") >> 4; } // dips B
764	786	static WRITE8_HANDLER( out_0 )
765	787	{
766	788	set_led_status(1,data & 1);
r894	r895
988	1010
989	1011
990	1012	INPUT_PORTS_START( bosco )
991		PORT_START
	1013	PORT_START_TAG("IN0")
992	1014	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
993	1015	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
994	1016	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r894	r895
998	1020	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
999	1021	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1000	1022
1001		PORT_START
	1023	PORT_START_TAG("IN1")
1002	1024	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
1003	1025	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
1004	1026	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
r894	r895
1008	1030	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
1009	1031	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
1010	1032
1011		PORT_START /* DSW A */
	1033	PORT_START_TAG("DSWA")
1012	1034	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
1013	1035	PORT_DIPSETTING( 0x01, DEF_STR( Easy ) )
1014	1036	PORT_DIPSETTING( 0x03, DEF_STR( Medium ) )
r894	r895
1033	1055	PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
1034	1056	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
1035	1057
1036		PORT_START /* DSW B */
	1058	PORT_START_TAG("DSWB")
1037	1059	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
1038	1060	PORT_DIPSETTING( 0x01, DEF_STR( 4C_1C ) )
1039	1061	PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
r894	r895
1061	1083	INPUT_PORTS_END
1062	1084
1063	1085	INPUT_PORTS_START( boscomd )
1064		PORT_START
1065		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
1066		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
1067		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
1068		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
1069		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
1070		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
1071		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1072		PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
	1086	PORT_INCLUDE( bosco )
1073	1087
1074		PORT_START
1075		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
1076		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
1077		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
1078		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
1079		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
1080		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
1081		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
1082		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
1083
1084		PORT_START /* DSW A */
	1088	PORT_MODIFY("DSWA")
1085	1089	PORT_DIPNAME( 0x01, 0x01, "2 Credits Game" )
1086	1090	PORT_DIPSETTING( 0x00, "1 Player" )
1087	1091	PORT_DIPSETTING( 0x01, "2 Players" )
r894	r895
1105	1109	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Cabinet ) )
1106	1110	PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
1107	1111	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
1108
1109		PORT_START /* DSW B */
1110		PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
1111		PORT_DIPSETTING( 0x01, DEF_STR( 4C_1C ) )
1112		PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
1113		PORT_DIPSETTING( 0x03, DEF_STR( 2C_1C ) )
1114		PORT_DIPSETTING( 0x07, DEF_STR( 1C_1C ) )
1115		PORT_DIPSETTING( 0x04, DEF_STR( 2C_3C ) )
1116		PORT_DIPSETTING( 0x06, DEF_STR( 1C_2C ) )
1117		PORT_DIPSETTING( 0x05, DEF_STR( 1C_3C ) )
1118		PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
1119		/* TODO: bonus scores are different for 5 lives */
1120		PORT_DIPNAME( 0x38, 0x08, "Bonus Fighter" )
1121		PORT_DIPSETTING( 0x30, "15K 50K" )
1122		PORT_DIPSETTING( 0x38, "20K 70K" )
1123		PORT_DIPSETTING( 0x08, "10K 50K 50K" )
1124		PORT_DIPSETTING( 0x10, "15K 50K 50K" )
1125		PORT_DIPSETTING( 0x18, "15K 70K 70K" )
1126		PORT_DIPSETTING( 0x20, "20K 70K 70K" )
1127		PORT_DIPSETTING( 0x28, "30K 100K 100K" )
1128		PORT_DIPSETTING( 0x00, DEF_STR( None ) )
1129		PORT_DIPNAME( 0xc0, 0x80, DEF_STR( Lives ) )
1130		PORT_DIPSETTING( 0x00, "1" )
1131		PORT_DIPSETTING( 0x40, "2" )
1132		PORT_DIPSETTING( 0x80, "3" )
1133		PORT_DIPSETTING( 0xc0, "5" )
1134	1112	INPUT_PORTS_END
1135	1113
1136	1114
1137	1115	INPUT_PORTS_START( galaga )
1138		PORT_START
	1116	PORT_START_TAG("IN0")
1139	1117	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
1140	1118	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
1141	1119	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r894	r895
1155	1133	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
1156	1134	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_2WAY PORT_COCKTAIL
1157	1135
1158		PORT_START /* DSW A */
	1136	PORT_START_TAG("DSWA")
1159	1137	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
1160	1138	PORT_DIPSETTING( 0x03, DEF_STR( Easy ) )
1161	1139	PORT_DIPSETTING( 0x00, DEF_STR( Medium ) )
r894	r895
1180	1158	PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
1181	1159	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
1182	1160
1183		PORT_START /* DSW B */
	1161	PORT_START_TAG("DSWB")
1184	1162	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
1185	1163	PORT_DIPSETTING( 0x04, DEF_STR( 4C_1C ) )
1186	1164	PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
r894	r895
1207	1185	PORT_DIPSETTING( 0xc0, "5" )
1208	1186	INPUT_PORTS_END
1209	1187
1210		/* dip switches are slightly different */
1211	1188	INPUT_PORTS_START( galagamw )
1212		PORT_START
1213		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
1214		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
1215		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
1216		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
1217		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
1218		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
1219		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1220		PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
	1189	PORT_INCLUDE( galaga )
1221	1190
1222		PORT_START
1223		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
1224		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_2WAY
1225		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
1226		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_2WAY
1227		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
1228		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_2WAY PORT_COCKTAIL
1229		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED )
1230		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_2WAY PORT_COCKTAIL
1231
1232		PORT_START /* DSW A */
	1191	PORT_MODIFY("DSWA")
1233	1192	PORT_DIPNAME( 0x01, 0x01, "2 Credits Game" )
1234	1193	PORT_DIPSETTING( 0x00, "1 Player" )
1235	1194	PORT_DIPSETTING( 0x01, "2 Players" )
r894	r895
1253	1212	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Cabinet ) )
1254	1213	PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
1255	1214	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
1256
1257		PORT_START /* DSW B */
1258		PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coinage ) )
1259		PORT_DIPSETTING( 0x04, DEF_STR( 4C_1C ) )
1260		PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
1261		PORT_DIPSETTING( 0x06, DEF_STR( 2C_1C ) )
1262		PORT_DIPSETTING( 0x07, DEF_STR( 1C_1C ) )
1263		PORT_DIPSETTING( 0x01, DEF_STR( 2C_3C ) )
1264		PORT_DIPSETTING( 0x03, DEF_STR( 1C_2C ) )
1265		PORT_DIPSETTING( 0x05, DEF_STR( 1C_3C ) )
1266		PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
1267		/* TODO: bonus scores are different for 5 lives */
1268		PORT_DIPNAME( 0x38, 0x10, DEF_STR( Bonus_Life ) )
1269		PORT_DIPSETTING( 0x20, "20K 60K 60K" )
1270		PORT_DIPSETTING( 0x18, "20K 60K" )
1271		PORT_DIPSETTING( 0x10, "20K 70K 70K" )
1272		PORT_DIPSETTING( 0x30, "20K 80K 80K" )
1273		PORT_DIPSETTING( 0x38, "30K 80K" )
1274		PORT_DIPSETTING( 0x08, "30K 100K 100K" )
1275		PORT_DIPSETTING( 0x28, "30K 120K 120K" )
1276		PORT_DIPSETTING( 0x00, DEF_STR( None ) )
1277		PORT_DIPNAME( 0xc0, 0x80, DEF_STR( Lives ) )
1278		PORT_DIPSETTING( 0x00, "2" )
1279		PORT_DIPSETTING( 0x80, "3" )
1280		PORT_DIPSETTING( 0x40, "4" )
1281		PORT_DIPSETTING( 0xc0, "5" )
1282	1215	INPUT_PORTS_END
1283	1216
1284
1285	1217	/* the same as galaga but with vertical movement */
1286	1218	INPUT_PORTS_START( gatsbee )
1287	1219	PORT_INCLUDE( galaga )
r894	r895
1299	1231
1300	1232
1301	1233	INPUT_PORTS_START( xevious )
1302		PORT_START
	1234	PORT_START_TAG("IN0")
1303	1235	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
1304	1236	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
1305	1237	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r894	r895
1309	1241	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1310	1242	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1311	1243
1312		PORT_START
	1244	PORT_START_TAG("IN1")
1313	1245	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
1314	1246	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
1315	1247	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
r894	r895
1319	1251	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
1320	1252	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
1321	1253
1322		PORT_START /* DSW A */
	1254	PORT_START_TAG("DSWA")
1323	1255	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
1324	1256	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
1325	1257	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
1326	1258	PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
1327	1259	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
1328		/* TODO: bonus scores are different for 5 lives */
1329	1260	PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Bonus_Life ) )
1330		PORT_DIPSETTING( 0x18, "10K 40K 40K" )
1331		PORT_DIPSETTING( 0x14, "10K 50K 50K" )
1332		PORT_DIPSETTING( 0x10, "20K 50K 50K" )
1333		PORT_DIPSETTING( 0x1c, "20K 60K 60K" )
1334		PORT_DIPSETTING( 0x0c, "20K 70K 70K" )
1335		PORT_DIPSETTING( 0x08, "20K 80K 80K" )
1336		PORT_DIPSETTING( 0x04, "20K 60K" )
1337		PORT_DIPSETTING( 0x00, DEF_STR( None ) )
1338		/* Bonus scores for 5 lives
1339		PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Bonus_Life ) )
1340		PORT_DIPSETTING( 0x18, "10K 50K 50K" )
1341		PORT_DIPSETTING( 0x14, "20K 50K 50K" )
1342		PORT_DIPSETTING( 0x10, "20K 60K 60K" )
1343		PORT_DIPSETTING( 0x1c, "20K 70K 70K" )
1344		PORT_DIPSETTING( 0x0c, "20K 80K 80K" )
1345		PORT_DIPSETTING( 0x08, "30K 100K 100K" )
1346		PORT_DIPSETTING( 0x04, "20K 80K" )
1347		PORT_DIPSETTING( 0x00, DEF_STR( None ) )
1348		*/
	1261	PORT_DIPSETTING( 0x18, "10K 40K 40K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_NOTEQUALS,0x00)
	1262	PORT_DIPSETTING( 0x14, "10K 50K 50K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_NOTEQUALS,0x00)
	1263	PORT_DIPSETTING( 0x10, "20K 50K 50K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_NOTEQUALS,0x00)
	1264	PORT_DIPSETTING( 0x1c, "20K 60K 60K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_NOTEQUALS,0x00)
	1265	PORT_DIPSETTING( 0x0c, "20K 70K 70K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_NOTEQUALS,0x00)
	1266	PORT_DIPSETTING( 0x08, "20K 80K 80K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_NOTEQUALS,0x00)
	1267	PORT_DIPSETTING( 0x04, "20K 60K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_NOTEQUALS,0x00)
	1268	PORT_DIPSETTING( 0x00, DEF_STR( None ) ) PORT_CONDITION("DSWA",0x60,PORTCOND_NOTEQUALS,0x00)
	1269	PORT_DIPSETTING( 0x18, "10K 50K 50K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_EQUALS,0x00)
	1270	PORT_DIPSETTING( 0x14, "20K 50K 50K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_EQUALS,0x00)
	1271	PORT_DIPSETTING( 0x10, "20K 60K 60K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_EQUALS,0x00)
	1272	PORT_DIPSETTING( 0x1c, "20K 70K 70K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_EQUALS,0x00)
	1273	PORT_DIPSETTING( 0x0c, "20K 80K 80K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_EQUALS,0x00)
	1274	PORT_DIPSETTING( 0x08, "30K 100K 100K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_EQUALS,0x00)
	1275	PORT_DIPSETTING( 0x04, "20K 80K" ) PORT_CONDITION("DSWA",0x60,PORTCOND_EQUALS,0x00)
	1276	PORT_DIPSETTING( 0x00, DEF_STR( None ) ) PORT_CONDITION("DSWA",0x60,PORTCOND_EQUALS,0x00)
1349	1277	PORT_DIPNAME( 0x60, 0x60, DEF_STR( Lives ) )
1350	1278	PORT_DIPSETTING( 0x40, "1" )
1351	1279	PORT_DIPSETTING( 0x20, "2" )
r894	r895
1355	1283	PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
1356	1284	PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
1357	1285
1358		PORT_START /* DSW B */
	1286	PORT_START_TAG("DSWB")
1359	1287	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON2 )
1360	1288	PORT_DIPNAME( 0x02, 0x02, "Flags Award Bonus Life" )
1361	1289	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
r894	r895
1378	1306
1379	1307	/* same as xevious but different "Coin B" Dip Switch and "Copyright" Dip Switch instead of "Freeze" */
1380	1308	INPUT_PORTS_START( xeviousa )
1381		PORT_START
1382		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
1383		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
1384		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
1385		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
1386		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
1387		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
1388		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1389		PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
	1309	PORT_INCLUDE( xevious )
1390	1310
1391		PORT_START
1392		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
1393		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
1394		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
1395		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
1396		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
1397		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
1398		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
1399		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
1400
1401		PORT_START /* DSW A */
1402		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
1403		PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
1404		PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
1405		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
1406		PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
1407		/* TODO: bonus scores are different for 5 lives */
1408		PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Bonus_Life ) )
1409		PORT_DIPSETTING( 0x18, "10K 40K 40K" )
1410		PORT_DIPSETTING( 0x14, "10K 50K 50K" )
1411		PORT_DIPSETTING( 0x10, "20K 50K 50K" )
1412		PORT_DIPSETTING( 0x1c, "20K 60K 60K" )
1413		PORT_DIPSETTING( 0x0c, "20K 70K 70K" )
1414		PORT_DIPSETTING( 0x08, "20K 80K 80K" )
1415		PORT_DIPSETTING( 0x04, "20K 60K" )
1416		PORT_DIPSETTING( 0x00, DEF_STR( None ) )
1417		/* Bonus scores for 5 lives
1418		PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Bonus_Life ) )
1419		PORT_DIPSETTING( 0x18, "10K 50K 50K" )
1420		PORT_DIPSETTING( 0x14, "20K 50K 50K" )
1421		PORT_DIPSETTING( 0x10, "20K 60K 60K" )
1422		PORT_DIPSETTING( 0x1c, "20K 70K 70K" )
1423		PORT_DIPSETTING( 0x0c, "20K 80K 80K" )
1424		PORT_DIPSETTING( 0x08, "30K 100K 100K" )
1425		PORT_DIPSETTING( 0x04, "20K 80K" )
1426		PORT_DIPSETTING( 0x00, DEF_STR( None ) )
1427		*/
1428		PORT_DIPNAME( 0x60, 0x60, DEF_STR( Lives ) )
1429		PORT_DIPSETTING( 0x40, "1" )
1430		PORT_DIPSETTING( 0x20, "2" )
1431		PORT_DIPSETTING( 0x60, "3" )
1432		PORT_DIPSETTING( 0x00, "5" )
1433		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Cabinet ) )
1434		PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
1435		PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
1436
1437		PORT_START /* DSW B */
	1311	PORT_MODIFY("DSWB")
1438	1312	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON2 )
1439	1313	PORT_DIPNAME( 0x02, 0x02, "Flags Award Bonus Life" )
1440	1314	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
r894	r895
1458	1332
1459	1333	/* same as xevious but "Copyright" Dip Switch instead of "Freeze" */
1460	1334	INPUT_PORTS_START( xeviousb )
1461		PORT_START
1462		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
1463		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
1464		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
1465		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
1466		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
1467		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
1468		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1469		PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
	1335	PORT_INCLUDE( xevious )
1470	1336
1471		PORT_START
1472		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
1473		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
1474		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
1475		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
1476		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
1477		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
1478		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
1479		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
1480
1481		PORT_START /* DSW A */
1482		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
1483		PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
1484		PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
1485		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
1486		PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
1487		/* TODO: bonus scores are different for 5 lives */
1488		PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Bonus_Life ) )
1489		PORT_DIPSETTING( 0x18, "10K 40K 40K" )
1490		PORT_DIPSETTING( 0x14, "10K 50K 50K" )
1491		PORT_DIPSETTING( 0x10, "20K 50K 50K" )
1492		PORT_DIPSETTING( 0x1c, "20K 60K 60K" )
1493		PORT_DIPSETTING( 0x0c, "20K 70K 70K" )
1494		PORT_DIPSETTING( 0x08, "20K 80K 80K" )
1495		PORT_DIPSETTING( 0x04, "20K 60K" )
1496		PORT_DIPSETTING( 0x00, DEF_STR( None ) )
1497		/* Bonus scores for 5 lives
1498		PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Bonus_Life ) )
1499		PORT_DIPSETTING( 0x18, "10K 50K 50K" )
1500		PORT_DIPSETTING( 0x14, "20K 50K 50K" )
1501		PORT_DIPSETTING( 0x10, "20K 60K 60K" )
1502		PORT_DIPSETTING( 0x1c, "20K 70K 70K" )
1503		PORT_DIPSETTING( 0x0c, "20K 80K 80K" )
1504		PORT_DIPSETTING( 0x08, "30K 100K 100K" )
1505		PORT_DIPSETTING( 0x04, "20K 80K" )
1506		PORT_DIPSETTING( 0x00, DEF_STR( None ) )
1507		*/
1508		PORT_DIPNAME( 0x60, 0x60, DEF_STR( Lives ) )
1509		PORT_DIPSETTING( 0x40, "1" )
1510		PORT_DIPSETTING( 0x20, "2" )
1511		PORT_DIPSETTING( 0x60, "3" )
1512		PORT_DIPSETTING( 0x00, "5" )
1513		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Cabinet ) )
1514		PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
1515		PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
1516
1517		PORT_START /* DSW B */
	1337	PORT_MODIFY("DSWB")
1518	1338	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON2 )
1519	1339	PORT_DIPNAME( 0x02, 0x02, "Flags Award Bonus Life" )
1520	1340	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
r894	r895
1538	1358
1539	1359	/* same as xevious but different "Coin B" Dip Switch and inverted "Freeze" Dip Switch */
1540	1360	INPUT_PORTS_START( sxevious )
1541		PORT_START
1542		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
1543		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
1544		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
1545		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
1546		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
1547		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
1548		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1549		PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
	1361	PORT_INCLUDE( xevious )
1550	1362
1551		PORT_START
1552		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
1553		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
1554		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
1555		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
1556		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
1557		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
1558		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
1559		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
1560
1561		PORT_START /* DSW A */
1562		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
1563		PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
1564		PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
1565		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
1566		PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
1567		/* TODO: bonus scores are different for 5 lives */
1568		PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Bonus_Life ) )
1569		PORT_DIPSETTING( 0x18, "10K 40K 40K" )
1570		PORT_DIPSETTING( 0x14, "10K 50K 50K" )
1571		PORT_DIPSETTING( 0x10, "20K 50K 50K" )
1572		PORT_DIPSETTING( 0x1c, "20K 60K 60K" )
1573		PORT_DIPSETTING( 0x0c, "20K 70K 70K" )
1574		PORT_DIPSETTING( 0x08, "20K 80K 80K" )
1575		PORT_DIPSETTING( 0x04, "20K 60K" )
1576		PORT_DIPSETTING( 0x00, DEF_STR( None ) )
1577		/* Bonus scores for 5 lives
1578		PORT_DIPNAME( 0x1c, 0x1c, DEF_STR( Bonus_Life ) )
1579		PORT_DIPSETTING( 0x18, "10K 50K 50K" )
1580		PORT_DIPSETTING( 0x14, "20K 50K 50K" )
1581		PORT_DIPSETTING( 0x10, "20K 60K 60K" )
1582		PORT_DIPSETTING( 0x1c, "20K 70K 70K" )
1583		PORT_DIPSETTING( 0x0c, "20K 80K 80K" )
1584		PORT_DIPSETTING( 0x08, "30K 100K 100K" )
1585		PORT_DIPSETTING( 0x04, "20K 80K" )
1586		PORT_DIPSETTING( 0x00, DEF_STR( None ) )
1587		*/
1588		PORT_DIPNAME( 0x60, 0x60, DEF_STR( Lives ) )
1589		PORT_DIPSETTING( 0x40, "1" )
1590		PORT_DIPSETTING( 0x20, "2" )
1591		PORT_DIPSETTING( 0x60, "3" )
1592		PORT_DIPSETTING( 0x00, "5" )
1593		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Cabinet ) )
1594		PORT_DIPSETTING( 0x80, DEF_STR( Upright ) )
1595		PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
1596
1597		PORT_START /* DSW B */
	1363	PORT_MODIFY("DSWB")
1598	1364	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON2 )
1599	1365	PORT_DIPNAME( 0x02, 0x02, "Flags Award Bonus Life" )
1600	1366	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
r894	r895
1617	1383
1618	1384
1619	1385	INPUT_PORTS_START( digdug )
1620		PORT_START
	1386	PORT_START_TAG("IN0")
1621	1387	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
1622	1388	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
1623	1389	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
r894	r895
1627	1393	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
1628	1394	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
1629	1395
1630		PORT_START
	1396	PORT_START_TAG("IN1")
1631	1397	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY
1632	1398	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY
1633	1399	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY
r894	r895
1637	1403	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_COCKTAIL
1638	1404	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_COCKTAIL
1639	1405
1640		PORT_START /* DSW A */
	1406	PORT_START_TAG("DSWA")
1641	1407	PORT_DIPNAME( 0x07, 0x01, DEF_STR( Coin_B ) )
1642	1408	PORT_DIPSETTING( 0x07, DEF_STR( 3C_1C ) )
1643	1409	PORT_DIPSETTING( 0x03, DEF_STR( 2C_1C ) )
r894	r895
1647	1413	PORT_DIPSETTING( 0x02, DEF_STR( 1C_3C ) )
1648	1414	PORT_DIPSETTING( 0x04, DEF_STR( 1C_6C ) )
1649	1415	PORT_DIPSETTING( 0x00, DEF_STR( 1C_7C ) )
1650		/* TODO: bonus scores are different for 5 lives */
1651	1416	PORT_DIPNAME( 0x38, 0x18, DEF_STR( Bonus_Life ) )
1652		PORT_DIPSETTING( 0x20, "10k 40k 40k" )
1653		PORT_DIPSETTING( 0x10, "10k 50k 50k" )
1654		PORT_DIPSETTING( 0x30, "20k 60k 60k" )
1655		PORT_DIPSETTING( 0x08, "20k 70k 70k" )
1656		PORT_DIPSETTING( 0x28, "10k 40k" )
1657		PORT_DIPSETTING( 0x18, "20k 60k" )
1658		PORT_DIPSETTING( 0x38, "10k" )
1659		PORT_DIPSETTING( 0x00, DEF_STR( None ) )
	1417	PORT_DIPSETTING( 0x20, "10K 40K 40K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_NOTEQUALS,0xc0)
	1418	PORT_DIPSETTING( 0x10, "10K 50K 50K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_NOTEQUALS,0xc0)
	1419	PORT_DIPSETTING( 0x30, "20K 60K 60K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_NOTEQUALS,0xc0)
	1420	PORT_DIPSETTING( 0x08, "20K 70K 70K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_NOTEQUALS,0xc0)
	1421	PORT_DIPSETTING( 0x28, "10K 40K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_NOTEQUALS,0xc0)
	1422	PORT_DIPSETTING( 0x18, "20K 60K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_NOTEQUALS,0xc0)
	1423	PORT_DIPSETTING( 0x38, "10K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_NOTEQUALS,0xc0)
	1424	PORT_DIPSETTING( 0x00, DEF_STR( None ) ) PORT_CONDITION("DSWA",0xc0,PORTCOND_NOTEQUALS,0xc0)
	1425	PORT_DIPSETTING( 0x20, "20K 60K 60K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_EQUALS,0xc0)
	1426	PORT_DIPSETTING( 0x10, "30K 80K 80K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_EQUALS,0xc0)
	1427	PORT_DIPSETTING( 0x30, "20K 50K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_EQUALS,0xc0)
	1428	PORT_DIPSETTING( 0x08, "20K 60K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_EQUALS,0xc0)
	1429	PORT_DIPSETTING( 0x28, "30K 70K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_EQUALS,0xc0)
	1430	PORT_DIPSETTING( 0x18, "20K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_EQUALS,0xc0)
	1431	PORT_DIPSETTING( 0x38, "30K" ) PORT_CONDITION("DSWA",0xc0,PORTCOND_EQUALS,0xc0)
	1432	PORT_DIPSETTING( 0x00, DEF_STR( None ) ) PORT_CONDITION("DSWA",0xc0,PORTCOND_EQUALS,0xc0)
1660	1433	PORT_DIPNAME( 0xc0, 0x80, DEF_STR( Lives ) )
1661	1434	PORT_DIPSETTING( 0x00, "1" )
1662	1435	PORT_DIPSETTING( 0x40, "2" )
1663	1436	PORT_DIPSETTING( 0x80, "3" )
1664	1437	PORT_DIPSETTING( 0xc0, "5" )
1665	1438
1666		PORT_START /* DSW B */
	1439	PORT_START_TAG("DSWB")
1667	1440	PORT_DIPNAME( 0xc0, 0x00, DEF_STR( Coin_A ) )
1668	1441	PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) )
1669	1442	PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )

src/mame/drivers/istellar.c
r0	r895
	1	/*
	2	Funai / Gakken Interstellar Laser Fantasy laserdisc hardware
	3	Driver by Andrew Gardner with help from Daphne Source
	4
	5	Notes:
	6	Holding down the TEST switch (T) while hitting reset will bring up the Self Test.
	7	Hit T twice more for color and monitor calibration.
	8	This is somewhat strange hardware : More z80's than necessary
	9	3 bpp sprites
	10	6-pin dip switches with odd handling
	11	inverted DIP logic?
	12	CPU2 maps RAM over where its ROM lives
	13	The DIP switch settings seem to be inverted (or the test mode shows 1 for open and 0 for closed). This is fine, but
	14	the DIPLOC stuff displays the switches off when they should be on and vice-versa. Maybe a fix the DIPlOCc code is needed?
	15
	16	Todo:
	17	How does one best make one DIP switch bit from address 0x02 tie to two bits from address 0x03?
	18	Get real ROM labels! The current labels are unfortunately a bit odd.
	19	Add sprite drawing.
	20	Convert to tilemaps.
	21	Make it work - this one should be close right now :/.
	22	*/
	23
	24	#include "driver.h"
	25	#include "render.h"
	26	#include "machine/laserdsc.h"
	27
	28	/* There is only 1 crystal on the stack of 3 boards - speed is unknown, the following is Daphne's guess */
	29	#define GUESSED_CLOCK (3072000)
	30
	31
	32	/* Misc variables */
	33	static laserdisc_info *discinfo;
	34
	35	static UINT8 *tile_ram;
	36	static UINT8 *tile_control_ram;
	37	static UINT8 *sprite_ram;
	38
	39	static UINT8 ldp_latch1;
	40	static UINT8 ldp_latch2;
	41
	42	static UINT8 z80_2_nmi_enable;
	43
	44	/* VIDEO GOODS */
	45	VIDEO_UPDATE( istellar )
	46	{
	47	int charx, chary;
	48
	49	/* clear */
	50	fillbitmap(bitmap, 0, cliprect);
	51
	52	/* display disc information */
	53	if (discinfo != NULL)
	54	popmessage("%s", laserdisc_describe_state(discinfo));
	55
	56	/* DEBUG */
	57	/*
	58	for (charx = 0; charx < 0x400; charx ++)
	59	{
	60	printf ("%x ", sprite_ram[charx]) ;
	61	}
	62	printf("\n\n\n");
	63	*/
	64
	65	/* Draw tiles */
	66	for (charx = 0; charx < 32; charx++)
	67	{
	68	for (chary = 0; chary < 32; chary++)
	69	{
	70	int current_screen_character = (chary*32) + charx;
	71
	72	drawgfx(bitmap, machine->gfx[0],
	73	tile_ram[current_screen_character],
	74	(tile_control_ram[current_screen_character] & 0x0f),
	75	0, 0, charx8, chary8, cliprect, TRANSPARENCY_PEN, 0);
	76	}
	77	}
	78
	79
	80	/* Draw sprites */
	81
	82	return 0;
	83	}
	84
	85
	86
	87	/* MEMORY HANDLERS */
	88	/* Z80 0 R/W */
	89	READ8_HANDLER(z80_0_latch1_read)
	90	{
	91	/logerror("CPU0 : reading LDP status latch (%x)\n", ldp_latch1);/
	92	return ldp_latch1;
	93	}
	94
	95	WRITE8_HANDLER(z80_0_latch2_write)
	96	{
	97	/logerror("CPU0 : writing cpu_latch2 (%x). Potentially followed by an IRQ.\n", data);/
	98	ldp_latch2 = data;
	99
	100	/* A CPU2 NMI */
	101	if (z80_2_nmi_enable)
	102	{
	103	logerror("Executing an NMI on CPU2\n");
	104	cpunum_set_input_line(2, INPUT_LINE_NMI, PULSE_LINE); /* Maybe this is a ASSERT_LINE, CLEAR_LINE combo? */
	105	z80_2_nmi_enable = 0;
	106	}
	107	}
	108
	109
	110	/* Z80 1 R/W */
	111
	112
	113	/* Z80 2 R/W */
	114	READ8_HANDLER(z80_2_ldp_read)
	115	{
	116	UINT8 readResult = laserdisc_data_r(discinfo);
	117	logerror("CPU2 : reading LDP : %x\n", readResult);
	118	return readResult;
	119	}
	120
	121	READ8_HANDLER(z80_2_latch2_read)
	122	{
	123	logerror("CPU2 : reading latch2 (%x)\n", ldp_latch2);
	124	return ldp_latch2;
	125	}
	126
	127	READ8_HANDLER(z80_2_nmienable)
	128	{
	129	logerror("CPU2 : ENABLING NMI\n");
	130	z80_2_nmi_enable = 1;
	131	return 0x00;
	132	}
	133
	134	READ8_HANDLER(z80_2_unknown_read)
	135	{
	136	logerror("CPU2 : c000!\n");
	137	return 0x00;
	138	}
	139
	140	WRITE8_HANDLER(z80_2_latch1_write)
	141	{
	142	logerror("CPU2 : writing latch1 (%x)\n", data);
	143	ldp_latch1 = data;
	144	}
	145
	146	WRITE8_HANDLER(z80_2_ldp_write)
	147	{
	148	logerror("CPU2 : writing LDP : 0x%x\n", data);
	149	laserdisc_data_w(discinfo,data);
	150	}
	151
	152
	153
	154	/* PROGRAM MAPS */
	155	static ADDRESS_MAP_START( z80_0_mem, ADDRESS_SPACE_PROGRAM, 8 )
	156	AM_RANGE(0x0000,0x9fff) AM_ROM
	157	AM_RANGE(0xa000,0xa7ff) AM_RAM
	158	AM_RANGE(0xa800,0xabff) AM_RAM AM_BASE(&tile_ram)
	159	AM_RANGE(0xac00,0xafff) AM_RAM AM_BASE(&tile_control_ram)
	160	AM_RANGE(0xb000,0xb3ff) AM_RAM AM_BASE(&sprite_ram)
	161	ADDRESS_MAP_END
	162
	163	static ADDRESS_MAP_START( z80_1_mem, ADDRESS_SPACE_PROGRAM, 8 )
	164	AM_RANGE(0x0000,0x1fff) AM_ROM
	165	AM_RANGE(0x4000,0x47ff) AM_RAM
	166	ADDRESS_MAP_END
	167
	168	static ADDRESS_MAP_START( z80_2_mem, ADDRESS_SPACE_PROGRAM, 8 )
	169	AM_RANGE(0x0000,0x17ff) AM_ROM
	170	AM_RANGE(0x1800,0x1fff) AM_RAM
	171	AM_RANGE(0xc000,0xc000) AM_READ(z80_2_unknown_read) /* Seems to be thrown away every time it's read - maybe interrupt related? */
	172	ADDRESS_MAP_END
	173
	174
	175	/* IO MAPS */
	176	static ADDRESS_MAP_START( z80_0_io, ADDRESS_SPACE_IO, 8 )
	177	ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
	178	AM_RANGE(0x00,0x00) AM_READ_PORT("IN0")
	179	AM_RANGE(0x02,0x02) AM_READ_PORT("DSW1")
	180	AM_RANGE(0x03,0x03) AM_READ_PORT("DSW2")
	181	/AM_RANGE(0x04,0x04) AM_WRITE(volatile_palette_write)/
	182	AM_RANGE(0x05,0x05) AM_READWRITE(z80_0_latch1_read,z80_0_latch2_write)
	183	ADDRESS_MAP_END
	184
	185	static ADDRESS_MAP_START( z80_1_io, ADDRESS_SPACE_IO, 8 )
	186	ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
	187	AM_RANGE(0x00,0x00) AM_NOP /AM_READWRITE(z80_1_slatch_read,z80_1_slatch_write)/
	188	AM_RANGE(0x01,0x01) AM_NOP /AM_READWRITE(z80_1_nmienable,z80_1_soundwrite_front)/
	189	AM_RANGE(0x02,0x02) AM_NOP /AM_WRITE(z80_1_soundwrite_rear)/
	190	ADDRESS_MAP_END
	191
	192	static ADDRESS_MAP_START( z80_2_io, ADDRESS_SPACE_IO, 8 )
	193	ADDRESS_MAP_FLAGS( AMEF_ABITS(8) )
	194	AM_RANGE(0x00,0x00) AM_READWRITE(z80_2_ldp_read,z80_2_ldp_write)
	195	AM_RANGE(0x01,0x01) AM_READWRITE(z80_2_latch2_read,z80_2_latch1_write)
	196	AM_RANGE(0x02,0x02) AM_READ(z80_2_nmienable)
	197	/* AM_RANGE(0x03,0x03) AM_WRITE(z80_2_ldtrans_write)*/
	198	ADDRESS_MAP_END
	199
	200
	201	/* PORTS */
	202	INPUT_PORTS_START( istellar )
	203	/* TEST MODE might display a 0 for a short and a 1 for an open circuit? If so, everything below is inverted. */
	204	PORT_START_TAG("DSW1")
	205	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:1")
	206	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	207	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
	208	PORT_DIPNAME( 0x0e, 0x00, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:2,3,4")
	209	PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
	210	PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
	211	PORT_DIPSETTING( 0x06, DEF_STR( 2C_3C ) )
	212	PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
	213	PORT_DIPSETTING( 0x04, DEF_STR( 1C_3C ) )
	214	PORT_DIPSETTING( 0x0c, DEF_STR( 1C_6C ) )
	215	PORT_DIPNAME( 0x30, 0x00, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW1:5,6")
	216	PORT_DIPSETTING( 0x00, "3" )
	217	PORT_DIPSETTING( 0x10, "4" )
	218	PORT_DIPSETTING( 0x20, "5" )
	219	PORT_DIPSETTING( 0x30, "10" )
	220	PORT_DIPNAME( 0x40, 0x00, "Barrier UFO" ) PORT_DIPLOCATION("SW2:1")
	221	PORT_DIPSETTING( 0x40, DEF_STR( No ) )
	222	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
	223	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unused ) ) PORT_DIPLOCATION("SW2:2")
	224	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
	225	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	226
	227	/* NOTE - bit 0x80 in the above read is combined with bits 0x03 in the below read to form the Coin_B
	228	settings. I'm unaware of what mechanism MAME will use to make this work right? */
	229
	230	/* "In case of inter-stellar upright type the coin switch 2 is not used." Quoth the manual. */
	231	PORT_START_TAG("DSW2")
	232	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unused ) ) PORT_DIPLOCATION("SW2:3")
	233	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	234	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	235	PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unused ) ) PORT_DIPLOCATION("SW2:4")
	236	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	237	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	238	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unused ) ) PORT_DIPLOCATION("SW2:5") /* Maybe SERVICE? */
	239	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	240	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	241	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME( "TEST" ) PORT_CODE( KEYCODE_T )
	242	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN2 )
	243	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
	244	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_START2 )
	245	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_START1 )
	246
	247	PORT_START_TAG("IN0")
	248	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_4WAY
	249	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_4WAY
	250	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_4WAY
	251	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_4WAY
	252	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON1 )
	253	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 )
	254	/* SERVICE might be hanging out back here */
	255	INPUT_PORTS_END
	256
	257	PALETTE_INIT( istellar )
	258	{
	259	int i;
	260
	261	/* Oddly enough, the top 4 bits of each byte is 0 */
	262	for (i = 0; i < machine->drv->total_colors; i++)
	263	{
	264	int r,g,b;
	265	int bit0,bit1,bit2,bit3;
	266
	267	/* Daphne says "TODO: get the real interstellar resistor values" */
	268
	269	/* red component */
	270	bit0 = (color_prom[i+0x000] >> 0) & 0x01;
	271	bit1 = (color_prom[i+0x000] >> 1) & 0x01;
	272	bit2 = (color_prom[i+0x000] >> 2) & 0x01;
	273	bit3 = (color_prom[i+0x000] >> 3) & 0x01;
	274	r = (0x8f * bit3) + (0x43 * bit2) + (0x1f * bit1) + (0x0e * bit0);
	275
	276	/* green component */
	277	bit0 = (color_prom[i+0x100] >> 0) & 0x01;
	278	bit1 = (color_prom[i+0x100] >> 1) & 0x01;
	279	bit2 = (color_prom[i+0x100] >> 2) & 0x01;
	280	bit3 = (color_prom[i+0x100] >> 3) & 0x01;
	281	g = (0x8f * bit3) + (0x43 * bit2) + (0x1f * bit1) + (0x0e * bit0);
	282
	283	/* blue component */
	284	bit0 = (color_prom[i+0x200] >> 0) & 0x01;
	285	bit1 = (color_prom[i+0x200] >> 1) & 0x01;
	286	bit2 = (color_prom[i+0x200] >> 2) & 0x01;
	287	bit3 = (color_prom[i+0x200] >> 3) & 0x01;
	288	b = (0x8f * bit3) + (0x43 * bit2) + (0x1f * bit1) + (0x0e * bit0);
	289
	290	palette_set_color(machine,i,MAKE_RGB(r,g,b));
	291	}
	292	}
	293
	294	static const gfx_layout istellar_gfx_layout =
	295	{
	296	8,8,
	297	0x2000/8,
	298	3,
	299	{ 0, 0x20008, 0x40008 },
	300	{ 0,1,2,3,4,5,6,7 },
	301	{ 08, 18, 28, 38, 48, 58, 68, 78 },
	302	8*8
	303	};
	304
	305	static const gfx_decode gfxdecodeinfo[] =
	306	{
	307	{ REGION_GFX1, 0, &istellar_gfx_layout, 0x0, 0x100 },
	308	{ -1 }
	309	};
	310
	311	static MACHINE_START( istellar )
	312	{
	313	discinfo = laserdisc_init(LASERDISC_TYPE_LDV1000, get_disk_handle(0), 0);
	314	return;
	315	}
	316
	317	static INTERRUPT_GEN( vblank_callback_istellar )
	318	{
	319	/* Interrupt presumably comes from VBlank */
	320	cpunum_set_input_line(0, 0, ASSERT_LINE);
	321
	322	/* Interrupt presumably comes from the LDP's status strobe */
	323	cpunum_set_input_line(2, 0, ASSERT_LINE);
	324
	325	/* Only do the LDP's sync once */
	326	if (cpu_getactivecpu() == 0)
	327	laserdisc_vsync(discinfo);
	328	}
	329
	330
	331	/* DRIVER */
	332	static MACHINE_DRIVER_START( istellar )
	333	/* main cpu */
	334	MDRV_CPU_ADD(Z80, GUESSED_CLOCK)
	335	MDRV_CPU_PROGRAM_MAP(z80_0_mem,0)
	336	MDRV_CPU_IO_MAP(z80_0_io,0)
	337	MDRV_CPU_VBLANK_INT(vblank_callback_istellar, 1)
	338
	339	/* sound cpu */
	340	MDRV_CPU_ADD(Z80, GUESSED_CLOCK)
	341	MDRV_CPU_PROGRAM_MAP(z80_1_mem,0)
	342	MDRV_CPU_IO_MAP(z80_1_io,0)
	343
	344	/* ldp comm cpu */
	345	MDRV_CPU_ADD(Z80, GUESSED_CLOCK)
	346	MDRV_CPU_PROGRAM_MAP(z80_2_mem,0)
	347	MDRV_CPU_IO_MAP(z80_2_io,0)
	348
	349	MDRV_MACHINE_START(istellar)
	350
	351	/* video */
	352	MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
	353
	354	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
	355	MDRV_SCREEN_REFRESH_RATE(60)
	356	MDRV_SCREEN_VBLANK_TIME(DEFAULT_60HZ_VBLANK_DURATION)
	357	MDRV_SCREEN_SIZE(328, 328)
	358	MDRV_SCREEN_VISIBLE_AREA(08, 328-1, 08, 328-1)
	359
	360	MDRV_PALETTE_LENGTH(256)
	361	MDRV_PALETTE_INIT(istellar)
	362
	363	MDRV_GFXDECODE(gfxdecodeinfo)
	364	MDRV_VIDEO_UPDATE(istellar)
	365
	366	/* sound */
	367	MACHINE_DRIVER_END
	368
	369
	370	/* There is a photo of the PCB with blurry IC locations and labels. Comments reflect what I can (barely) see. */
	371	ROM_START( istellar )
	372	/* Main program CPU */
	373	ROM_REGION( 0xa000, REGION_CPU1, 0 )
	374	ROM_LOAD( "rom2.top", 0x0000, 0x2000, CRC(5d643381) SHA1(75ca52c28a52f534eda00c18b0db97e9923ff670) ) /* At IC location C63 (top board) - label ? */
	375	ROM_LOAD( "rom3.top", 0x2000, 0x2000, CRC(ce5a2b09) SHA1(2de6a6e993c3411577ac0c834db8aaf16fb007ed) ) /* At IC location C64 (top board) - label ? */
	376	ROM_LOAD( "rom4.top", 0x4000, 0x2000, CRC(7c2cb1f1) SHA1(ffd92510c03c2d35a59d233883c2b9f57394a51c) ) /* At IC location C65 (top board) - label ? */
	377	ROM_LOAD( "rom5.top", 0x6000, 0x2000, CRC(354377f6) SHA1(bcf95b7ee1b47854e10baf24b0d8af3d56738b99) ) /* At IC location C66 (top board) - label ? */
	378	ROM_LOAD( "rom6.top", 0x8000, 0x2000, CRC(0319bf40) SHA1(f324626e457c3eb7d6b74bc6afbfcc3aab2b3c72) ) /* At IC location C67 (top board) - label ? */
	379
	380	/* Sound CPU */
	381	ROM_REGION( 0x2000, REGION_CPU2, 0 )
	382	ROM_LOAD( "rom1.top", 0x0000, 0x2000, CRC(4f34fb1d) SHA1(56ca19344c84c5989d0be797e2759f84760310be) ) /* At IC location C62 (top board) - label ? */
	383
	384	/* LDP Communications CPU */
	385	ROM_REGION( 0x2000, REGION_CPU3, 0 )
	386	ROM_LOAD( "rom11.bot", 0x0000, 0x2000, CRC(165cbc57) SHA1(39463888f22ec3125f0686066d923a9aae79a8f7) ) /* At IC location C12 (bottom board) - label IS11 */
	387
	388	/* Tiles */
	389	ROM_REGION( 0x6000, REGION_GFX1, ROMREGION_DISPOSE )
	390	ROM_LOAD( "rom9.bot", 0x0000, 0x2000, CRC(9d79acb6) SHA1(72af972695face0016afce8a26c629d963e86d48) ) /* At IC location C47? (bottom board) - label ? */
	391	ROM_LOAD( "rom8.bot", 0x2000, 0x2000, CRC(e9c9e490) SHA1(79aa35552b984018bc723adece5c40a0833a313c) ) /* At IC location C48? (bottom board) - label ? */
	392	ROM_LOAD( "rom7.bot", 0x4000, 0x2000, CRC(1447ce3a) SHA1(8545cec108df6adab303802b1407c89b2dceba21) ) /* At IC location C49? (bottom board) - label ? */
	393
	394	/* Color PROMs */
	395	ROM_REGION( 0x300, REGION_PROMS, 0 )
	396	ROM_LOAD( "red6b.bot", 0x000, 0x100, CRC(5c52f844) SHA1(a8a3d91f3247ad13c805d8d8288b07f3cdaf1189) ) /* At IC location C63? (bottom board) - label ? */
	397	ROM_LOAD( "green6c.bot", 0x100, 0x100, CRC(7d8c845c) SHA1(04ae2ca0cc6679e21346ce34e9e01aa5bf4e2067) ) /* At IC location C62? (bottom board) - label ? */
	398	ROM_LOAD( "blue6d.bot", 0x200, 0x100, CRC(5ebb81f9) SHA1(285d60f2894c524ca80fc68ad7c2dfd9093a67ea) ) /* At IC location C61? (bottom board) - label ? */
	399	ROM_END
	400
	401
	402	static DRIVER_INIT( istellar )
	403	{
	404	z80_2_nmi_enable = 0;
	405	}
	406
	407	/* YEAR NAME PARENT MACHINE INPUT INIT MONITOR COMPANY FULLNAME FLAGS) */
	408	GAME( 1983, istellar, 0, istellar, istellar, istellar, ROT0, "Funai/Gakken", "Interstellar Laser Fantasy", GAME_NOT_WORKING\|GAME_NO_SOUND)

src/mame/drivers/taito_h.c
r894	r895
49	49	- Title screen of dynamite league is wrong a bit, which is mentioned by
50	50	Yasuhiro Ogawa.
51	51
	52
	53	Stephh's notes (based on the game M68000 code and some tests) :
	54
	55	1) 'syvalion'
	56
	57	- Region stored at 0x07fffe.w
	58	- Sets :
	59	* 'syvalion' : region = 0x0000
	60	- Coinage relies on the region (code at 0x003640) :
	61	* 0x0000 (Japan), 0x0001 (US), 0x0003 (US, Romstar licence) and
	62	0x0004 (licenced to PHOENIX ELECTRONICS CO.) use TAITO_COINAGE_JAPAN_OLD
	63	* 0x0002 (World) uses TAITO_COINAGE_WORLD
	64	- Notice screen only if region = 0x0000
	65	- Text is always in Japanese regardless of the region !
	66	- DSW bit 6 has an unknown effect because of a write to unmapped 0x430000.w
	67	(see code at 0x002af8). Another write to this address is done at 0x002a96.
	68
	69
	70	2) 'recordbr'
	71
	72	- Region stored at 0x07fffe.w
	73	- Sets :
	74	* 'recordbr' : region = 0x0003
	75	- Coinage relies on the region (code at 0x00144a) :
	76	* 0x0001 (Japan), 0x0002 (US), 0x0005 (US, Romstar licence) use TAITO_COINAGE_JAPAN_OLD
	77	* 0x0003 (World), 0x0004 (licenced to xxx) and
	78	0x0007 (licenced to PHOENIX ELECTRONICS CO.) use TAITO_COINAGE_WORLD
	79	- Notice screen only if region = 0x0001
	80
	81
	82	3) 'dleague'
	83
	84	- Region stored at 0x05fffe.w
	85	- Sets :
	86	* 'dleague' : region = 0x0000
	87	- Coinage relies on the region (code at 0x0017be) :
	88	* 0x0000 (Japan) uses TAITO_COINAGE_JAPAN_OLD
	89	* 0x0001 (US) uses TAITO_COINAGE_US
	90	* 0x0002 (World) uses TAITO_COINAGE_WORLD
	91	- Notice screen only if region = 0x0000
	92	- FBI logo only if region = 0x0001
	93	- DSWA bit 0 determines if difficulty is constant or if it is based on the inning
	94	(code at 0x010964 and 0x0109ce + tables at 0x010afe and 0x010b18)
	95	- When region != 0, DSWB bit 0 has multiple effects
	96	(code at 0x001208 with $1206,A5 initialised via code at 0x00ae2c);
	97	here is what I found so far :
	98	* OFF : you can select your team, you starting pitcher and your batting order pattern,
	99	but there won't be additional messages ingame
	100	* ON : you can't select your team, you starting pitcher and your batting order pattern,
	101	but there will be additional messages ingame
	102	- Regardless of the "Extra Credit Needed" settings, additional credit will be needed after 9th inning
	103	if there is a draw; the game will end if there is still a draw after 12th inning
	104	- The game will end if computer scores 10 points more than your score ("called game")
	105	- When you are playing, if you don't touch any joystick nor player button
	106	for 90 consecutive seconds, the game will end without any warning !
	107	See BTANB page on MAME Testers site for full report and more details
	108
	109
52	110	TODO :
53	111	========
54		- Make dipswitches clear.
55	112	- Implemented BG1 : sprite priority. Currently it is not brought out priority
56	113	bit.
57	114	- Fix sprite coordinates.
r894	r895
71	128
72	129
73	130	#include "driver.h"
	131	#include "taitoipt.h"
74	132	#include "audio/taitosnd.h"
75	133	#include "video/taitoic.h"
76	134	#include "sound/2610intf.h"
r894	r895
132	190	return taitoh_68000_mainram[offset];
133	191	}
134	192
	193	#define P1TRACKX_PORT_TAG "P1X"
	194	#define P1TRACKY_PORT_TAG "P1Y"
	195	#define P2TRACKX_PORT_TAG "P2X"
	196	#define P2TRACKY_PORT_TAG "P2Y"
	197
135	198	static READ16_HANDLER( syvalion_input_bypass_r )
136	199	{
137	200	/* Bypass TC0220IOC controller for analog input */
r894	r895
141	204	switch( port )
142	205	{
143	206	case 0x08: /* trackball y coords bottom 8 bits for 2nd player */
144		return input_port_7_~~r(0~~);
	207	return readinputportbytag(P2TRACKY_PORT_TAG);
145	208
146	209	case 0x09: /* trackball y coords top 8 bits for 2nd player */
147		if (input_port_7_~~r(0~~) & 0x80) /* y- direction (negative value) */
	210	if (readinputportbytag(P2TRACKY_PORT_TAG) & 0x80) /* y- direction (negative value) */
148	211	return 0xff;
149		else /* y+ direction (positive value) */
	212	else /* y+ direction (positive value) */
150	213	return 0x00;
151	214
152	215	case 0x0a: /* trackball x coords bottom 8 bits for 2nd player */
153		return input_port_6_~~r(0~~);
	216	return readinputportbytag(P2TRACKX_PORT_TAG);
154	217
155	218	case 0x0b: /* trackball x coords top 8 bits for 2nd player */
156		if (input_port_6_~~r(0~~) & 0x80) /* x- direction (negative value) */
	219	if (readinputportbytag(P2TRACKX_PORT_TAG) & 0x80) /* x- direction (negative value) */
157	220	return 0xff;
158		else /* x+ direction (positive value) */
	221	else /* x+ direction (positive value) */
159	222	return 0x00;
160	223
161		case 0x0c: /* trackball y coords bottom 8 bits for 2nd player */
162		return input_port_5_r(0);
	224	case 0x0c: /* trackball y coords bottom 8 bits for 1st player */
	225	return readinputportbytag(P1TRACKY_PORT_TAG);
163	226
164	227	case 0x0d: /* trackball y coords top 8 bits for 1st player */
165		if (input_port_5_~~r(0~~) & 0x80) /* y- direction (negative value) */
	228	if (readinputportbytag(P1TRACKY_PORT_TAG) & 0x80) /* y- direction (negative value) */
166	229	return 0xff;
167		else /* y+ direction (positive value) */
	230	else /* y+ direction (positive value) */
168	231	return 0x00;
169	232
170	233	case 0x0e: /* trackball x coords bottom 8 bits for 1st player */
171		return input_port_4_~~r(0~~);
	234	return readinputportbytag(P1TRACKX_PORT_TAG);
172	235
173	236	case 0x0f: /* trackball x coords top 8 bits for 1st player */
174		if (input_port_4_~~r(0~~) & 0x80) /* x- direction (negative value) */
	237	if (readinputportbytag(P1TRACKX_PORT_TAG) & 0x80) /* x- direction (negative value) */
175	238	return 0xff;
176		else /* x+ direction (positive value) */
	239	else /* x+ direction (positive value) */
177	240	return 0x00;
178	241
179	242	default:
r894	r895
305	368
306	369	***************************************************************************/
307	370
308		#define TAITO_COINAGE_JAPAN_8 \
309		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) \
310		PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) ) \
311		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
312		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) ) \
313		PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) ) \
314		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) \
315		PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
316		PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) ) \
317		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) ) \
318		PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )
319
320		#define TAITO_DIFFICULTY_8 \
321		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) \
322		PORT_DIPSETTING( 0x02, DEF_STR( Easy ) ) \
323		PORT_DIPSETTING( 0x03, DEF_STR( Medium ) ) \
324		PORT_DIPSETTING( 0x01, DEF_STR( Hard ) ) \
325		PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
326
327	371	INPUT_PORTS_START( syvalion )
328		PORT_START /* DSW1 (0) */
329		PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) )
330		PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
331		PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
332		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) )
333		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
334		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
335		PORT_SERVICE( 0x04, IP_ACTIVE_LOW )
336		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )
337		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
338		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
339		TAITO_COINAGE_JAPAN_8
	372	/* 0x200000 (port 0) -> 0x102842.b (-$57be,A5) */
	373	PORT_START_TAG("DSWA")
	374	TAITO_MACHINE_COCKTAIL
	375	TAITO_COINAGE_JAPAN_OLD
340	376
341		PORT_START /* DSW2 (1) */
342		TAITO_DIFFICULTY_8
	377	/* 0x200000 (port 1) -> 0x102843.b (-$57bd,A5) */
	378	PORT_START_TAG("DSWB")
	379	TAITO_DIFFICULTY
343	380	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )
344		PORT_DIPSETTING( 0x08, "1000k only" )
345		PORT_DIPSETTING( 0x0c, "1500k only" )
346		PORT_DIPSETTING( 0x04, "2000k only" )
	381	PORT_DIPSETTING( 0x08, "1000k" )
	382	PORT_DIPSETTING( 0x0c, "1500k" )
	383	PORT_DIPSETTING( 0x04, "2000k" )
347	384	PORT_DIPSETTING( 0x00, DEF_STR( None ) )
348	385	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )
349	386	PORT_DIPSETTING( 0x00, "2" )
350	387	PORT_DIPSETTING( 0x30, "3" )
351	388	PORT_DIPSETTING( 0x20, "4" )
352	389	PORT_DIPSETTING( 0x10, "5" )
353		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Un~~used~~ ) )
	390	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) /* code at 0x002af8 - see notes */
354	391	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
355	392	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
356		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unused ) )
357		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
358		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	393	PORT_DIPUNUSED( 0x80, IP_ACTIVE_LOW )
359	394
360		PORT_START /* IN0 (2) */
	395	PORT_START_TAG("IN0")
361	396	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
362	397	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
363	398	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN1 )
r894	r895
367	402	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
368	403	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
369	404
370		PORT_START /* IN1 (3) */
	405	PORT_START_TAG("IN1")
371	406	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
372		PORT_BIT( 0x0e, IP_ACTIVE_LOW, IPT_UNKNOWN )
	407	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
	408	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
	409	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
373	410	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
374		PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNKNOWN )
	411	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	412	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	413	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
375	414
376		PORT_START /* TRACK~~BALL1~~ X (4) */
	415	PORT_START_TAG(P1TRACKX_PORT_TAG)
377	416	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(30) PORT_KEYDELTA(30) PORT_RESET PORT_PLAYER(1)
378	417
379		PORT_START /* TRACK~~BALL1~~ Y (5) */
	418	PORT_START_TAG(P1TRACKY_PORT_TAG)
380	419	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(30) PORT_KEYDELTA(30) PORT_RESET PORT_REVERSE PORT_PLAYER(1)
381	420
382		PORT_START /* TRACK~~BALL2~~ X (6) */
	421	PORT_START_TAG(P2TRACKX_PORT_TAG)
383	422	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(30) PORT_KEYDELTA(30) PORT_RESET PORT_PLAYER(2)
384	423
385		PORT_START /* TRACK~~BALL2~~ Y (7) */
	424	PORT_START_TAG(P2TRACKY_PORT_TAG)
386	425	PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(30) PORT_KEYDELTA(30) PORT_RESET PORT_REVERSE PORT_PLAYER(2)
387	426	INPUT_PORTS_END
388	427
389	428	INPUT_PORTS_START( recordbr )
390		PORT_START /* DSW1 (0) */
391		PORT_DIPNAME( 0x00, 0x01, DEF_STR( Unknown ) )
392		PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
393		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
394		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) )
395		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
396		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
397		PORT_SERVICE( 0x04, IP_ACTIVE_LOW )
398		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )
399		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
400		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
401		TAITO_COINAGE_JAPAN_8
	429	/* 0x200000 (port 0) -> 0x1022e6.b (-$5d1a,A5) */
	430	PORT_START_TAG("DSWA")
	431	TAITO_MACHINE_NO_COCKTAIL
	432	TAITO_COINAGE_WORLD
402	433
403		PORT_START /* DSW2 (1) */
404		TAITO_DIFFICULTY_8
405		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
406		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
407		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
408		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
409		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
410		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
411		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
412		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
413		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
414		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
415		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
416		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
417		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
418		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
419		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
420		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
421		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
422		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	434	PORT_START_TAG("DSWB")
	435	/* 0x200000 (port 1) -> 0x1022e7.b (-$5d19,A5) */
	436	TAITO_DIFFICULTY
	437	PORT_DIPUNUSED( 0x04, IP_ACTIVE_LOW )
	438	PORT_DIPUNUSED( 0x08, IP_ACTIVE_LOW )
	439	PORT_DIPUNUSED( 0x10, IP_ACTIVE_LOW )
	440	PORT_DIPUNUSED( 0x20, IP_ACTIVE_LOW )
	441	PORT_DIPUNUSED( 0x40, IP_ACTIVE_LOW )
	442	PORT_DIPUNUSED( 0x80, IP_ACTIVE_LOW )
423	443
424		PORT_START /* IN0 (2) */
	444	PORT_START_TAG("IN0")
425	445	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
426	446	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
427	447	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN1 )
r894	r895
431	451	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
432	452	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
433	453
434		PORT_START /* IN1 (3) */
	454	PORT_START_TAG("IN1")
435	455	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
436	456	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
437		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START3 )
438		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START4 )
439		PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNKNOWN )
	457	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* IPT_START3 in service mode */
	458	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* IPT_START4 in service mode */
	459	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	460	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	461	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	462	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
440	463
441		PORT_START /* IN2 (4) */
	464	PORT_START_TAG("IN2")
442	465	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
443	466	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
444	467	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
445		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PL~~AYER(~~1)
	468	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* IPT_BUTTON4 (PL1) in service mode */
446	469	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
447	470	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
448	471	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
449		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PL~~AYER(~~2)
	472	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* IPT_BUTTON4 (PL2) in service mode */
450	473	INPUT_PORTS_END
451	474
452	475	INPUT_PORTS_START( dleague )
453		PORT_START /* DSW1 (0) */
454		PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
455		PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
456		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
457		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) )
458		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
459		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
460		PORT_SERVICE( 0x04, IP_ACTIVE_LOW )
461		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )
462		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
463		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
464		TAITO_COINAGE_JAPAN_8
	476	/* 0x200000 -> 0x100526.b ($526,A5) */
	477	PORT_START_TAG("DSWA")
	478	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Difficulty ) ) /* see notes */
	479	PORT_DIPSETTING( 0x01, "Constant" )
	480	PORT_DIPSETTING( 0x00, "Based on Inning" )
	481	TAITO_DSWA_BITS_1_TO_3
	482	TAITO_COINAGE_JAPAN_OLD
465	483
466		PORT_START /* DSW2 (1) */
467		PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unused ) )
468		PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
469		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
470		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unused ) )
471		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
472		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
473		PORT_DIPNAME( 0x0c, 0x0c, "Innings per credit" )
474		PORT_DIPSETTING( 0x0c, "3-3-3" )
475		PORT_DIPSETTING( 0x08, "6-3" )
476		PORT_DIPSETTING( 0x04, "3-2-2-2" )
477		PORT_DIPSETTING( 0x00, "5-2-2" )
478		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unused ) )
479		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
480		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
481		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unused ) )
482		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
483		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
484		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unused ) )
485		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
486		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
487		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unused ) )
488		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
489		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	484	/* 0x200002 -> 0x100527.b ($527,A5) */
	485	PORT_START_TAG("DSWB")
	486	PORT_DIPUNUSED( 0x01, IP_ACTIVE_LOW ) /* see notes */
	487	PORT_DIPUNUSED( 0x02, IP_ACTIVE_LOW )
	488	PORT_DIPNAME( 0x0c, 0x0c, "Extra Credit Needed" ) /* see notes */
	489	PORT_DIPSETTING( 0x08, "After Inning 6" )
	490	PORT_DIPSETTING( 0x00, "After Innings 5 and 7" )
	491	PORT_DIPSETTING( 0x0c, "After Innings 3 and 6" )
	492	PORT_DIPSETTING( 0x04, "After Innings 3, 5 and 7" )
	493	PORT_DIPUNUSED( 0x10, IP_ACTIVE_LOW )
	494	PORT_DIPUNUSED( 0x20, IP_ACTIVE_LOW )
	495	PORT_DIPUNUSED( 0x40, IP_ACTIVE_LOW )
	496	PORT_DIPUNUSED( 0x80, IP_ACTIVE_LOW )
490	497
491		PORT_START /* IN0 (2) */
	498	PORT_START_TAG("IN0")
492	499	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 )
493	500	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_TILT )
494	501	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 )
r894	r895
498	505	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
499	506	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
500	507
501		PORT_START /* IN1 (3) */
502		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
503		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
504		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
505		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
506		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
507		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
508		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
509		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
	508	PORT_START_TAG("IN1")
	509	TAITO_JOY_DUAL_UDLR( 1, 2 )
510	510
511		PORT_START /* IN2 (4) */
	511	PORT_START_TAG("IN2")
512	512	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
513	513	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
514		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
515		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
516		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
517		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
518		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
	514	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
	515	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
	516	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	517	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	518	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
519	519	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
520	520	INPUT_PORTS_END
521	521

src/mame/drivers/taito_x.c
r894	r895
16	16	Twin Hawk (World) Taito Corp. Japan 1988
17	17	Twin Hawk (US) Taito America Corp. 1988
18	18	Daisenpu (Japan) Taito Corp. 1988
19		Balloon Brothers East Technology Corp. 1990
20	19	Gigandes East Technology Corp. 1989
21	20	Last Striker East Technology Corp. 1989
	21	Balloon Brothers East Technology Corp. 199?
22	22
23	23	Please tell me the games worked on this board.
24	24
r894	r895
221	221	appears to use a simple input device with coin counter and lockout in
222	222	its place. The East Technology games on this hardware follow Daisenpu.
223	223
	224
	225	Stephh's notes (based on the game M68000 code and some tests) :
	226
	227	1) 'superman' and 'suprmanj'
	228
	229	- Region stored at 0x07fffe.w
	230	- Sets :
	231	* 'superman' : region = 0x0002
	232	* 'suprmanj' : region = 0x0000
	233	- These 2 games are 100% the same, only region differs !
	234	- Coinage relies on the region (code at 0x003b8a) :
	235	* 0x0000 (Japan) uses TAITO_COINAGE_JAPAN_OLD
	236	* 0x0001 (US) uses TAITO_COINAGE_US
	237	* 0x0002 (World) uses TAITO_COINAGE_WORLD
	238	- Notice screen only if region = 0x0001
	239	- I can't tell if it's an ingame bug or an emulation bug,
	240	but boss are far much harder when "Difficulty" Dip Swicth
	241	is set to "Easy" : put a watch on 0xf00a76.w for level 1 boss
	242	and you'll notice that MSB is set to 0x01 instead of 0x00
	243
	244
	245	2) 'twinhawk'
	246
	247	- No region
	248	- Hard coded coinage table at 0x00b01c and is the same as TAITO_COINAGE_WORLD
	249	- 2 simultaneous players game (player 1 is blue and player 2 is red)
	250	- BUTTON3 is only tested in "Test Mode", not when you are playing
	251
	252
	253	3) 'twinhwku'
	254
	255	- No region
	256	- Hard coded coinage table at 0x00b02a and is different from TAITO_COINAGE_US :
	257	* 2 coins slots with their own coinage
	258	* possible coinage settings : 4C_1C / 3C_1C / 2C_1C / 1C_1C
	259	- Same other notes as for 'twinhawk'
	260
	261
	262	4) 'daisenpu'
	263
	264	- No region
	265	- Hard coded coinage table at 0x00a44a and is the same as TAITO_COINAGE_JAPAN_OLD
	266	- Differences with 'twinhawk' :
	267	* notice screen
	268	* 2 alternate players game (players 1 and 2 are green)
	269	* additional "Cabinet" Dip Switch
	270	* different "Bonus Life" settings
	271	- Same other notes as for 'twinhawk'
	272
	273
	274	5) 'gigandes' and 'gigandsj'
	275
	276	- No region (not a Taito game anyway)
	277	- No notice screen
	278	- Constant bonus life at 50k, 250k then every 200k
	279	- Bogus "Test Mode" in 'gigandes' (while it is correct for 'gigandsj') :
	280	* screen is flipped while it shouldn't and it isn't flipped while it should
	281	* displays cabinet type instead of number of controls
	282	- DSWA bit 4 effect remains unknown but it MUST remain OFF !
	283	All I know is that this bit is tested in multiple places in the code
	284	and that it hangs the game when you are hit (music continues playing though)
	285	- DSWA bit 7 (called "Free Play" in "Test Mode") gives you infinite lives
	286	but you will still need to insert coins as a standard game.
	287	In a 2 players game, when this Dip Switch is ON, player doesn't change when it,
	288	so player 2 will have to wait that player 1 has ended the game to start.
	289
	290
	291	6) 'kyustrkr'
	292
	293	- No region (not a Taito game anyway)
	294	- No notice screen
	295	- DSWA bit 7 (called "Free Play" in "Test Mode") has the following effects :
	296	* in a game versus CPU, player(s) will always win regardless of the score
	297	* in a 1UP versus 2UP game, both players will play 6 matches regardless of the score
	298	- "Language" Dip Switch also affects game title
	299
	300
	301	7) 'ballbros'
	302
	303	- No region (not a Taito game anyway)
	304	- No notice screen
	305	- Do NOT trust the test mode which has nothing to do with the game !
	306	- "Difficulty" settings need to be confirmed as I'm not good enough
	307	at playing this game to see any visible difference :(
	308	They are based on the ones for other East Technology games though.
	309
	310
224	311	***************************************************************************/
225	312
226	313	#include "driver.h"
	314	#include "taitoipt.h"
227	315	#include "audio/taitosnd.h"
228	316	#include "seta.h"
229	317	#include "sound/2610intf.h"
230	318	#include "sound/2151intf.h"
231	319
232	320	MACHINE_RESET( cchip1 );
233		READ16_HANDLER ( cchip1_word_r );
234		WRITE16_HANDLER( cchip1_word_w );
	321	READ16_HANDLER( cchip1_ctrl_r );
	322	READ16_HANDLER( cchip1_ram_r );
	323	WRITE16_HANDLER( cchip1_ctrl_w );
	324	WRITE16_HANDLER( cchip1_bank_w );
	325	WRITE16_HANDLER( cchip1_ram_w );
235	326
236	327
237	328
r894	r895
240	331	switch (offset)
241	332	{
242	333	case 0x00:
243		return readinputport (0) & 0x0f;
	334	return readinputportbytag("DSWA") & 0x0f;
244	335	case 0x01:
245		return (readinputport (0) & 0xf0) >> 4;
	336	return (readinputportbytag("DSWA") & 0xf0) >> 4;
246	337	case 0x02:
247		return readinputport (1) & 0x0f;
	338	return readinputportbytag("DSWB") & 0x0f;
248	339	case 0x03:
249		return (readinputport (1) & 0xf0) >> 4;
	340	return (readinputportbytag("DSWB") & 0xf0) >> 4;
250	341	default:
251	342	logerror("taitox unknown dsw read offset: %04x\n", offset);
252	343	return 0x00;
r894	r895
258	349	switch (offset)
259	350	{
260	351	case 0x00:
261		return readinputport(2);
	352	return readinputportbytag("IN0"); /* Player 1 controls + START1 */
262	353	case 0x01:
263		return readinputport(3);
	354	return readinputportbytag("IN1"); /* Player 2 controls + START2 */
264	355	case 0x02:
265		return readinputport(4);
	356	return readinputportbytag("IN2"); /* COINn + SERVICE1 + TILT */
266	357
267	358	default:
268	359	logerror("taitox unknown input read offset: %04x\n", offset);
r894	r895
329	420	AM_RANGE(0x500000, 0x500007) AM_READ(superman_dsw_input_r)
330	421	AM_RANGE(0x800000, 0x800001) AM_READ(MRA16_NOP)
331	422	AM_RANGE(0x800002, 0x800003) AM_READ(taitosound_comm16_lsb_r)
332		AM_RANGE(0x900000, 0x900fff) AM_READ(cchip1_word_r)
	423	AM_RANGE(0x900000, 0x9007ff) AM_READ(cchip1_ram_r)
	424	AM_RANGE(0x900802, 0x900803) AM_READ(cchip1_ctrl_r)
333	425	AM_RANGE(0xb00000, 0xb00fff) AM_READ(paletteram16_word_r)
334	426	AM_RANGE(0xd00000, 0xd007ff) AM_READ(MRA16_RAM) /* video attribute ram */
335	427	AM_RANGE(0xe00000, 0xe03fff) AM_READ(MRA16_RAM) /* object ram */
r894	r895
343	435	AM_RANGE(0x600000, 0x600001) AM_WRITE(MWA16_NOP) /* written each frame at $3ab0, mostly 0x10 */
344	436	AM_RANGE(0x800000, 0x800001) AM_WRITE(taitosound_port16_lsb_w)
345	437	AM_RANGE(0x800002, 0x800003) AM_WRITE(taitosound_comm16_lsb_w)
346		AM_RANGE(0x900000, 0x900fff) AM_WRITE(cchip1_word_w)
	438	AM_RANGE(0x900000, 0x9007ff) AM_WRITE(cchip1_ram_w)
	439	AM_RANGE(0x900802, 0x900803) AM_WRITE(cchip1_ctrl_w)
	440	AM_RANGE(0x900c00, 0x900c01) AM_WRITE(cchip1_bank_w)
347	441	AM_RANGE(0xb00000, 0xb00fff) AM_WRITE(paletteram16_xRRRRRGGGGGBBBBB_word_w) AM_BASE(&paletteram16)
348	442	AM_RANGE(0xd00000, 0xd007ff) AM_WRITE(MWA16_RAM) AM_BASE(&spriteram16 ) // Sprites Y
349	443	AM_RANGE(0xe00000, 0xe03fff) AM_WRITE(MWA16_RAM) AM_BASE(&spriteram16_2 ) // Sprites Code + X + Attr
r894	r895
510	604
511	605	/**************************************************************************/
512	606
513		#define TAITO_COINAGE_JAPAN_8 \
514		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SWA:5,6") \
515		PORT_DIPSETTING( 0x10, DEF_STR( 2C_1C ) ) \
516		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
517		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) ) \
518		PORT_DIPSETTING( 0x20, DEF_STR( 1C_2C ) ) \
519		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SWA:7,8") \
520		PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
521		PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) ) \
522		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) ) \
523		PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )
524
525		#define TAITO_COINAGE_WORLD_8 \
526		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SWA:5,6") \
527		PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) ) \
528		PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) ) \
529		PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) ) \
530		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
531		PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SWA:7,8") \
532		PORT_DIPSETTING( 0xc0, DEF_STR( 1C_2C ) ) \
533		PORT_DIPSETTING( 0x80, DEF_STR( 1C_3C ) ) \
534		PORT_DIPSETTING( 0x40, DEF_STR( 1C_4C ) ) \
535		PORT_DIPSETTING( 0x00, DEF_STR( 1C_6C ) )
536
537		#define TAITO_COINAGE_US_8 \
538		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SWA:5,6") \
539		PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) ) \
540		PORT_DIPSETTING( 0x10, DEF_STR( 3C_1C ) ) \
541		PORT_DIPSETTING( 0x20, DEF_STR( 2C_1C ) ) \
542		PORT_DIPSETTING( 0x30, DEF_STR( 1C_1C ) ) \
543		PORT_DIPNAME( 0xc0, 0xc0, "Price to Continue" ) PORT_DIPLOCATION("SWA:7,8") \
544		PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) \
545		PORT_DIPSETTING( 0x40, DEF_STR( 2C_1C ) ) \
546		PORT_DIPSETTING( 0x80, DEF_STR( 1C_1C ) ) \
547		PORT_DIPSETTING( 0xc0, "Same as Start" )
548
549		INPUT_PORTS_START( taitox )
	607	INPUT_PORTS_START( taitox_generic )
	608	/* The Dip Switches will be filled for each game */
550	609	PORT_START_TAG("DSWA")
551		PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) ~~PORT_DIPLOCATION("SWA:1")~~
	610	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
552	611	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
553	612	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
554		PORT_DIPNAME( 0x02, 0x02, DEF_STR( ~~Flip_Scree~~n ) ~~) PORT_DIPLOCATION("SWA:2"~~)
	613	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
555	614	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
556	615	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
557		PORT_SERVICE( 0x04, IP_ACTIVE_LOW ) // PORT_DIPLOCATION("SWA:3")
558		PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SWA:4")
	616	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
	617	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	618	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	619	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
559	620	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
560	621	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
561		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) ~~PORT_DIPLOCATION("SWA:5")~~
	622	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
562	623	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
563	624	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
564		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) ~~PORT_DIPLOCATION("SWA:6")~~
	625	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
565	626	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
566	627	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
567		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) ~~PORT_DIPLOCATION("SWA:7")~~
	628	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
568	629	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
569	630	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
570		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) ~~PORT_DIPLOCATION("SWA:8")~~
	631	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
571	632	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
572	633	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
573	634
574	635	PORT_START_TAG("DSWB")
575		PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SWB:1,2")
576		PORT_DIPSETTING( 0x02, DEF_STR( Easy ) )
577		PORT_DIPSETTING( 0x03, DEF_STR( Normal ) )
578		PORT_DIPSETTING( 0x01, DEF_STR( Hard ) )
579		PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
580		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SWB:3")
	636	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
	637	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	638	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	639	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
	640	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	641	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	642	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
581	643	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
582	644	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
583		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) ~~PORT_DIPLOCATION("SWB:4")~~
	645	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
584	646	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
585	647	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
586		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) ~~PORT_DIPLOCATION("SWB:5")~~
	648	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
587	649	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
588	650	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
589		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) ~~PORT_DIPLOCATION("SWB:6")~~
	651	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
590	652	PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
591	653	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
592		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) ~~PORT_DIPLOCATION("SWB:7")~~
	654	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
593	655	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
594	656	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
595		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) ~~PORT_DIPLOCATION("SWB:8")~~
	657	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
596	658	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
597	659	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
598	660
599	661	PORT_START_TAG("IN0")
600		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1) PORT_8WAY
601		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1) PORT_8WAY
602		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1) PORT_8WAY
603		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1) PORT_8WAY
604		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
605		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
606		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
607		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
	662	TAITO_JOY_UDLR_3_BUTTONS_START( 1 )
608	663
609	664	PORT_START_TAG("IN1")
610		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2) PORT_8WAY
611		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) PORT_8WAY
612		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2) PORT_8WAY
613		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2) PORT_8WAY
614		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
615		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
616		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
617		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
	665	TAITO_JOY_UDLR_3_BUTTONS_START( 2 )
618	666
619		PORT_START /* IN2 */
	667	PORT_START_TAG("IN2")
620	668	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
621	669	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
622	670	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE1 )
623	671	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_TILT )
624		PORT_BIT( 0xF0, IP_ACTIVE_LOW, IPT_UNKNOWN )
	672	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	673	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	674	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	675	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
625	676	INPUT_PORTS_END
626	677
627	678	INPUT_PORTS_START( superman )
628		PORT_INCLUDE( taitox )
	679	PORT_INCLUDE( taitox_generic )
	680
	681	/* 0x500000 (low) and 0x500002 (high) -> 0xf01c4a ($1c4a,A5) */
629	682	PORT_MODIFY("DSWA")
630		PORT_DIPNAME( 0x08, 0x00, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SWA:4")
631		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
632		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
633		TAITO_COINAGE_WORLD_8
	683	TAITO_MACHINE_NO_COCKTAIL_LOC(SWA)
	684	TAITO_COINAGE_WORLD_LOC(SWA)
634	685
	686	/* 0x500004 (low) and 0x500006 (high) -> 0xf01c4c ($1c4c,A5) */
635	687	PORT_MODIFY("DSWB")
636		// It seems that there are no Bonus_Life dips
637		// You get always bonus at 50k, 150k, 300k,
638		// 450k and 600k, no matter the values of bit 2 and 3
	688	TAITO_DIFFICULTY_LOC(SWB)
	689	PORT_DIPUNUSED_DIPLOC( 0x04, IP_ACTIVE_LOW, "SWB:3" )
	690	PORT_DIPUNUSED_DIPLOC( 0x08, IP_ACTIVE_LOW, "SWB:4" )
639	691	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) ) PORT_DIPLOCATION("SWB:5,6")
640	692	PORT_DIPSETTING( 0x20, "2" )
641	693	PORT_DIPSETTING( 0x30, "3" )
642	694	PORT_DIPSETTING( 0x10, "4" )
643	695	PORT_DIPSETTING( 0x00, "5" )
	696	PORT_DIPUNUSED_DIPLOC( 0x40, IP_ACTIVE_LOW, "SWB:7" )
	697	PORT_DIPUNUSED_DIPLOC( 0x80, IP_ACTIVE_LOW, "SWB:8" )
644	698
645	699	PORT_MODIFY("IN0")
646		~~POR~~T_BIT~~( 0x40, IP~~_~~ACTIVE~~_L~~OW, IPT~~_UNUSED ~~) //~~ ~~only two buttons~~
	700	TAITO_JOY_UDLR_2_BUTTONS_START( 1 )
647	701
648	702	PORT_MODIFY("IN1")
649		~~POR~~T_BIT~~( 0x40, IP~~_~~ACTIVE~~_L~~OW, IPT~~_UNUSED ~~) //~~ ~~only two buttons~~
	703	TAITO_JOY_UDLR_2_BUTTONS_START( 2 )
650	704	INPUT_PORTS_END
651	705
652	706	INPUT_PORTS_START( suprmanj )
653	707	PORT_INCLUDE( superman )
654	708
655	709	PORT_MODIFY("DSWA")
656		TAITO_COINAGE_JAPAN_8
	710	TAITO_COINAGE_JAPAN_OLD_LOC(SWA)
657	711	INPUT_PORTS_END
658	712
659	713	INPUT_PORTS_START( twinhawk )
660		PORT_INCLUDE( taitox )
	714	PORT_INCLUDE( taitox_generic )
661	715
	716	/* 0x500000 (low) and 0x500002 (high) -> 0xf001b8 */
662	717	PORT_MODIFY("DSWA")
663		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SWA:4")
664		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
665		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
666		TAITO_COINAGE_WORLD_8
	718	TAITO_MACHINE_NO_COCKTAIL_LOC(SWA)
	719	TAITO_COINAGE_WORLD_LOC(SWA)
667	720
	721	/* 0x500004 (low) and 0x500006 (high) -> 0xf001ba */
668	722	PORT_MODIFY("DSWB")
	723	TAITO_DIFFICULTY_LOC(SWB)
669	724	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SWB:3,4")
670	725	PORT_DIPSETTING( 0x0c, "50k and every 150k" )
671	726	PORT_DIPSETTING( 0x08, "70k and every 200k" )
672	727	PORT_DIPSETTING( 0x04, "50k only" )
673		PORT_DIPSETTING( 0x00, ~~DEF_STR(~~ Non~~e )~~ )
	728	PORT_DIPSETTING( 0x00, "100k only" )
674	729	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) ) PORT_DIPLOCATION("SWB:5,6")
675	730	PORT_DIPSETTING( 0x00, "2" )
676	731	PORT_DIPSETTING( 0x30, "3" )
677	732	PORT_DIPSETTING( 0x10, "4" )
678	733	PORT_DIPSETTING( 0x20, "5" )
	734	PORT_DIPUNUSED_DIPLOC( 0x40, IP_ACTIVE_LOW, "SWB:7" )
679	735	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Allow_Continue ) ) PORT_DIPLOCATION("SWB:8")
680	736	PORT_DIPSETTING( 0x80, DEF_STR( No ) )
681	737	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
	738
	739	PORT_MODIFY("IN0")
	740	TAITO_JOY_UDLR_2_BUTTONS_START( 1 )
	741
	742	PORT_MODIFY("IN1")
	743	TAITO_JOY_UDLR_2_BUTTONS_START( 2 )
682	744	INPUT_PORTS_END
683	745
684	746	INPUT_PORTS_START( twinhwku )
685	747	PORT_INCLUDE( twinhawk )
686	748
687	749	PORT_MODIFY("DSWA")
688		TAITO_COINAGE_US_8
	750	PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SWA:7,8")
	751	PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) )
	752	PORT_DIPSETTING( 0x40, DEF_STR( 3C_1C ) )
	753	PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) )
	754	PORT_DIPSETTING( 0xc0, DEF_STR( 1C_1C ) )
689	755	INPUT_PORTS_END
690	756
691	757	INPUT_PORTS_START( daisenpu )
692		PORT_INCLUDE( tai~~tox~~ )
	758	PORT_INCLUDE( twinhawk )
693	759
	760	/* 0x500000 (low) and 0x500002 (high) -> 0xf001a4 */
694	761	PORT_MODIFY("DSWA")
695		PORT_DIPNAME( 0x01, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SWA:1")
696		PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
697		PORT_DIPSETTING( 0x01, DEF_STR( Cocktail ) )
698		PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SWA:2")
699		PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
700		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
701		PORT_SERVICE( 0x04, IP_ACTIVE_LOW ) // PORT_DIPLOCATION("SWA:3")
702		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SWA:4")
703		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
704		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
705		TAITO_COINAGE_JAPAN_8
	762	TAITO_MACHINE_COCKTAIL_LOC(SWA)
	763	TAITO_COINAGE_JAPAN_OLD_LOC(SWA)
706	764
	765	/* 0x500004 (low) and 0x500006 (high) -> 0xf001a6 */
707	766	PORT_MODIFY("DSWB")
708	767	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SWB:3,4")
709	768	PORT_DIPSETTING( 0x08, "50k and every 150k" )
710	769	PORT_DIPSETTING( 0x0c, "70k and every 200k" )
711	770	PORT_DIPSETTING( 0x04, "100k only" )
712	771	PORT_DIPSETTING( 0x00, DEF_STR( None ) )
713		PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) ) PORT_DIPLOCATION("SWB:5,6")
714		PORT_DIPSETTING( 0x00, "2" )
715		PORT_DIPSETTING( 0x30, "3" )
716		PORT_DIPSETTING( 0x10, "4" )
717		PORT_DIPSETTING( 0x20, "5" )
718		PORT_DIPNAME( 0x80, 0x00, DEF_STR( Allow_Continue ) ) PORT_DIPLOCATION("SWB:8")
719		PORT_DIPSETTING( 0x80, DEF_STR( No ) )
720		PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
721	772	INPUT_PORTS_END
722	773
723		INPUT_PORTS_START( easttech )
724		PORT_INCLUDE( taitox )
	774	INPUT_PORTS_START( gigandes )
	775	PORT_INCLUDE( taitox_generic )
725	776
726		// ~~dips~~ ~~are tota~~lly ~~differe~~nt ~~from~~ th~~e Ta~~ito ga~~mes~~
	777	/* 0x500000 (low) and 0x500002 (high) -> 0xf00a3c */
727	778	PORT_MODIFY("DSWA")
728	779	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
729		PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ))
730		PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ))
731		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ))
732		PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ))
	780	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
	781	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
	782	PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
	783	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
733	784	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Coin_B ) )
734		PORT_DIPSETTING( 0x04, DEF_STR( 2C_1C ))
735		PORT_DIPSETTING( 0x0c, DEF_STR( 1C_1C ))
736		PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ))
737		PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ))
738		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
	785	PORT_DIPSETTING( 0x04, DEF_STR( 2C_1C ) )
	786	PORT_DIPSETTING( 0x0c, DEF_STR( 1C_1C ) )
	787	PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
	788	PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
	789	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) /* MUST REMAIN OFF ! see notes */
739	790	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
740	791	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
741	792	PORT_DIPNAME( 0x60, 0x40, DEF_STR( Difficulty ) )
742	793	PORT_DIPSETTING( 0x60, DEF_STR( Easy ) )
743		PORT_DIPSETTING( 0x40, DEF_STR( ~~Nor~~mal ) )
	794	PORT_DIPSETTING( 0x40, DEF_STR( Medium ) )
744	795	PORT_DIPSETTING( 0x20, DEF_STR( Hard ) )
745	796	PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
746		PORT_DIPNAME( 0x80, 0x80, D~~EF_STR(~~ ~~Unkn~~own ) )
	797	PORT_DIPNAME( 0x80, 0x80, "Debug Mode" ) /* see notes */
747	798	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
748	799	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
749	800
	801	/* 0x500004 (low) and 0x500006 (high) -> 0xf00a3e */
750	802	PORT_MODIFY("DSWB")
751	803	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
752	804	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
r894	r895
755	807	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
756	808	PORT_DIPSETTING( 0x02, DEF_STR( On ) )
757	809	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Allow_Continue ) )
758		PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
759		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
760		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
761		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
762		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
763		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
764		PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
765		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
766		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
767		PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
768		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
769		PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
770		PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
771		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	810	PORT_DIPSETTING( 0x04, DEF_STR( No ) )
	811	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
	812	PORT_DIPNAME( 0x18, 0x18, DEF_STR( Lives ) )
	813	PORT_DIPSETTING( 0x18, "3" )
	814	PORT_DIPSETTING( 0x10, "4" )
	815	PORT_DIPSETTING( 0x08, "5" )
	816	PORT_DIPSETTING( 0x00, "6" )
	817	PORT_DIPNAME( 0x20, 0x00, DEF_STR( Controls ) )
	818	PORT_DIPSETTING( 0x20, DEF_STR( Single ) )
	819	PORT_DIPSETTING( 0x00, DEF_STR( Dual ) )
	820	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Language ) )
	821	PORT_DIPSETTING( 0x00, DEF_STR( English ) )
	822	PORT_DIPSETTING( 0x40, DEF_STR( Japanese ) )
772	823	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
	824
	825	PORT_MODIFY("IN0")
	826	TAITO_JOY_UDLR_2_BUTTONS_START( 1 )
	827
	828	PORT_MODIFY("IN1")
	829	TAITO_JOY_UDLR_2_BUTTONS_START( 2 )
773	830	INPUT_PORTS_END
774	831
775		INPUT_PORTS_START( gigandes )
776		PORT_INCLUDE( easttech )
	832	INPUT_PORTS_START( kyustrkr )
	833	PORT_INCLUDE( taitox_generic )
777	834
	835	/* 0x500000 (low) and 0x500002 (high) -> 0xf028fe */
778	836	PORT_MODIFY("DSWA")
779		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Free_Play ) )
	837	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
	838	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
	839	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
	840	PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
	841	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
	842	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Coin_B ) )
	843	PORT_DIPSETTING( 0x04, DEF_STR( 2C_1C ) )
	844	PORT_DIPSETTING( 0x0c, DEF_STR( 1C_1C ) )
	845	PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
	846	PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
	847	PORT_DIPUNUSED( 0x10, IP_ACTIVE_LOW )
	848	PORT_DIPNAME( 0x60, 0x40, DEF_STR( Difficulty ) )
	849	PORT_DIPSETTING( 0x60, DEF_STR( Easy ) )
	850	PORT_DIPSETTING( 0x40, DEF_STR( Normal ) )
	851	PORT_DIPSETTING( 0x20, DEF_STR( Hard ) )
	852	PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
	853	PORT_DIPNAME( 0x80, 0x80, "Debug Mode" ) /* see notes */
780	854	PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
781	855	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
782	856
	857	/* 0x500004 (low) and 0x500006 (high) -> 0xf02900 */
783	858	PORT_MODIFY("DSWB")
784		PORT_DIPNAME( 0x18, 0x18, DEF_STR( Lives ) )
785		PORT_DIPSETTING( 0x18, "3" )
786		PORT_DIPSETTING( 0x10, "4" )
787		PORT_DIPSETTING( 0x08, "5" )
788		PORT_DIPSETTING( 0x00, "6" )
789		PORT_DIPNAME( 0x20, 0x00, DEF_STR( Cabinet ) )
790		PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
791		PORT_DIPSETTING( 0x20, DEF_STR( Cocktail ) )
	859	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
	860	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	861	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	862	PORT_DIPNAME( 0x02, 0x00, DEF_STR( Flip_Screen ) )
	863	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	864	PORT_DIPSETTING( 0x02, DEF_STR( On ) )
	865	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Allow_Continue ) )
	866	PORT_DIPSETTING( 0x04, DEF_STR( No ) )
	867	PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
	868	PORT_DIPUNUSED( 0x08, IP_ACTIVE_LOW )
	869	PORT_DIPUNUSED( 0x10, IP_ACTIVE_LOW )
	870	PORT_DIPUNUSED( 0x20, IP_ACTIVE_LOW )
792	871	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Language ) )
793	872	PORT_DIPSETTING( 0x00, DEF_STR( English ) )
794	873	PORT_DIPSETTING( 0x40, DEF_STR( Japanese ) )
	874	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
795	875	INPUT_PORTS_END
796	876
797	877	INPUT_PORTS_START( ballbros )
798		PORT_INCLUDE( easttech )
	878	PORT_INCLUDE( taitox_generic )
799	879
	880	/* 0x500000 (low) and 0x500002 (high) -> 0xf028fe */
800	881	PORT_MODIFY("DSWA")
801		PORT_DIPNAME( 0x04, 0x04, DEF_STR( Coin_B ) )
802		PORT_DIPSETTING( 0x04, DEF_STR( 1C_1C ))
803		PORT_DIPSETTING( 0x00, DEF_STR( 1C_2C ))
804		PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unused ) )
805		PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
806		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	882	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
	883	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
	884	PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
	885	PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
	886	PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
	887	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Coin_B ) )
	888	PORT_DIPSETTING( 0x04, DEF_STR( 2C_1C ) )
	889	PORT_DIPSETTING( 0x0c, DEF_STR( 1C_1C ) )
	890	PORT_DIPSETTING( 0x00, DEF_STR( 2C_3C ) )
	891	PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
	892	PORT_DIPUNUSED( 0x10, IP_ACTIVE_LOW )
	893	PORT_DIPNAME( 0x60, 0x40, DEF_STR( Difficulty ) ) /* to be confirmed */
	894	PORT_DIPSETTING( 0x60, DEF_STR( Easy ) )
	895	PORT_DIPSETTING( 0x40, DEF_STR( Medium ) )
	896	PORT_DIPSETTING( 0x20, DEF_STR( Hard ) )
	897	PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
	898	PORT_DIPUNUSED( 0x80, IP_ACTIVE_LOW )
807	899
	900	/* 0x500004 (low) and 0x500006 (high) -> 0xf02900 */
808	901	PORT_MODIFY("DSWB")
	902	PORT_DIPNAME( 0x01, 0x00, DEF_STR( Demo_Sounds ) )
	903	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	904	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
809	905	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) )
810	906	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
811	907	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	908	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Allow_Continue ) )
	909	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	910	PORT_DIPSETTING( 0x04, DEF_STR( Yes ) )
	911	PORT_DIPUNUSED( 0x08, IP_ACTIVE_LOW )
	912	PORT_DIPUNUSED( 0x10, IP_ACTIVE_LOW )
812	913	PORT_DIPNAME( 0x20, 0x00, DEF_STR( Language ) )
813	914	PORT_DIPSETTING( 0x00, DEF_STR( English ) )
814	915	PORT_DIPSETTING( 0x20, DEF_STR( Japanese ) )
815		INPUT_PORTS_END
	916	PORT_DIPNAME( 0x40, 0x00, "Color Change" )
	917	PORT_DIPSETTING( 0x00, "Less" ) /* each pattern */
	918	PORT_DIPSETTING( 0x40, "More" ) /* every 3 times */
	919	PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
816	920
817		INPUT_PORTS_START( kyustrkr )
818		PORT_INCLUDE( easttech )
	921	PORT_MODIFY("IN0")
	922	TAITO_JOY_UDLR_1_BUTTON_START( 1 )
819	923
820		PORT_MODIFY("DSWA")
821		PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) // Free play in test mode, does not work
822		PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
823		PORT_DIPSETTING( 0x00, DEF_STR( On ) )
824
825		PORT_MODIFY("DSWB")
826		PORT_DIPNAME( 0x40, 0x00, DEF_STR( Language ) )
827		PORT_DIPSETTING( 0x00, DEF_STR( English ) )
828		PORT_DIPSETTING( 0x40, DEF_STR( Japanese ) )
	924	PORT_MODIFY("IN1")
	925	TAITO_JOY_UDLR_1_BUTTON_START( 2 )
829	926	INPUT_PORTS_END
830	927
831	928
r894	r895
1207	1304	ROM_LOAD( "east-10.16e", 0x00000, 0x80000, CRC(ca0ac419) SHA1(b29f30a8ff1286c65b741353b6551918a45bcafe) )
1208	1305	ROM_END
1209	1306
	1307	ROM_START( kyustrkr )
	1308	ROM_REGION( 0x40000, REGION_CPU1, 0 ) /* 512k for 68000 code */
	1309	ROM_LOAD16_BYTE( "pe.9a", 0x00000, 0x20000, CRC(082b5f96) SHA1(97c08b506b2a07d63f3323359b8564aa3621f483) )
	1310	ROM_LOAD16_BYTE( "po.4a", 0x00001, 0x20000, CRC(0100361e) SHA1(45791f697c86309c459d0d8c3d3e967a3ece3ede) )
	1311
	1312	ROM_REGION( 0x1c000, REGION_CPU2, 0 ) /* 64k for Z80 code */
	1313	ROM_LOAD( "ic.18d", 0x00000, 0x4000, CRC(92cfb788) SHA1(41cd5433584df05652bd0ce8c5a35dc38262d6f2) )
	1314	ROM_CONTINUE( 0x10000, 0xc000 ) /* banked stuff */
	1315
	1316	ROM_REGION( 0x80000, REGION_GFX1, ROMREGION_DISPOSE )
	1317	ROM_LOAD( "m-8-3.u3", 0x00000, 0x20000, CRC(1c4084e6) SHA1(addea2ba07bddb41fbe7f0fc859e744990bb9ff5) )
	1318	ROM_LOAD( "m-8-2.u4", 0x20000, 0x20000, CRC(ada21c4d) SHA1(a683c8d798370c50d9bd5e67e91d7ed0f1659c20) )
	1319	ROM_LOAD( "m-8-1.u5", 0x40000, 0x20000, CRC(9d95aad6) SHA1(3391b14196fea12223ab247d909791bc68fc8d56) )
	1320	ROM_LOAD( "m-8-0.u6", 0x60000, 0x20000, CRC(0dfb6ed3) SHA1(0937614c8f97040d0216363bfb2bc21161128a3c) )
	1321
	1322	ROM_REGION( 0x80000, REGION_SOUND1, 0 ) /* ADPCM samples */
	1323	ROM_LOAD( "m-8-5.u2", 0x00000, 0x20000, CRC(d9d90e0a) SHA1(1011548b4fb5f1a194c93ded512e74cda2c06ceb) )
	1324
	1325	ROM_REGION( 0x80000, REGION_SOUND2, 0 ) /* Delta-T samples */
	1326	ROM_LOAD( "m-8-4.u1", 0x00000, 0x20000, CRC(d3f6047a) SHA1(0db6d762bbe2d68cddf30e06125b904e1021b96d) )
	1327	ROM_END
	1328
1210	1329	ROM_START( ballbros )
1211	1330	ROM_REGION( 0x40000, REGION_CPU1, 0 ) /* 256k for 68000 code */
1212	1331	ROM_LOAD16_BYTE( "10a", 0x00000, 0x20000, CRC(4af0e858) SHA1(817817169aee075d52411bdbe568514511760386) )
r894	r895
1229	1348	ROM_LOAD( "east-10", 0x00000, 0x80000, CRC(ca0ac419) SHA1(b29f30a8ff1286c65b741353b6551918a45bcafe) )
1230	1349	ROM_END
1231	1350
1232		ROM_START( kyustrkr )
1233		ROM_REGION( 0x40000, REGION_CPU1, 0 ) /* 512k for 68000 code */
1234		ROM_LOAD16_BYTE( "pe.9a", 0x00000, 0x20000, CRC(082b5f96) SHA1(97c08b506b2a07d63f3323359b8564aa3621f483) )
1235		ROM_LOAD16_BYTE( "po.4a", 0x00001, 0x20000, CRC(0100361e) SHA1(45791f697c86309c459d0d8c3d3e967a3ece3ede) )
1236	1351
1237		ROM_REGION( 0x1c000, REGION_CPU2, 0 ) /* 64k for Z80 code */
1238		ROM_LOAD( "ic.18d", 0x00000, 0x4000, CRC(92cfb788) SHA1(41cd5433584df05652bd0ce8c5a35dc38262d6f2) )
1239		ROM_CONTINUE( 0x10000, 0xc000 ) /* banked stuff */
1240
1241		ROM_REGION( 0x80000, REGION_GFX1, ROMREGION_DISPOSE )
1242		ROM_LOAD( "m-8-3.u3", 0x00000, 0x20000, CRC(1c4084e6) SHA1(addea2ba07bddb41fbe7f0fc859e744990bb9ff5) )
1243		ROM_LOAD( "m-8-2.u4", 0x20000, 0x20000, CRC(ada21c4d) SHA1(a683c8d798370c50d9bd5e67e91d7ed0f1659c20) )
1244		ROM_LOAD( "m-8-1.u5", 0x40000, 0x20000, CRC(9d95aad6) SHA1(3391b14196fea12223ab247d909791bc68fc8d56) )
1245		ROM_LOAD( "m-8-0.u6", 0x60000, 0x20000, CRC(0dfb6ed3) SHA1(0937614c8f97040d0216363bfb2bc21161128a3c) )
1246
1247		ROM_REGION( 0x80000, REGION_SOUND1, 0 ) /* ADPCM samples */
1248		ROM_LOAD( "m-8-5.u2", 0x00000, 0x20000, CRC(d9d90e0a) SHA1(1011548b4fb5f1a194c93ded512e74cda2c06ceb) )
1249
1250		ROM_REGION( 0x80000, REGION_SOUND2, 0 ) /* Delta-T samples */
1251		ROM_LOAD( "m-8-4.u1", 0x00000, 0x20000, CRC(d3f6047a) SHA1(0db6d762bbe2d68cddf30e06125b904e1021b96d) )
1252		ROM_END
1253
1254	1352	DRIVER_INIT( kyustrkr )
1255	1353	{
1256	1354	memory_install_write16_handler(0, ADDRESS_SPACE_PROGRAM, 0x900000, 0x90000f, 0, 0, kyustrkr_input_w);
1257	1355	}
1258	1356
	1357
1259	1358	GAME( 1988, superman, 0, superman, superman, 0, ROT0, "Taito Corporation", "Superman", 0 )
1260	1359	GAME( 1988, suprmanj, superman, superman, suprmanj, 0, ROT0, "Taito Corporation", "Superman (Japan)", 0 )
1261	1360	GAME( 1989, twinhawk, 0, daisenpu, twinhawk, 0, ROT270, "Taito Corporation Japan", "Twin Hawk (World)", 0 )

src/mame/drivers/thayers.c
r894	r895
7	7	a COP404L - A ROMless COP420 with 1k of RAM. I wonder which one is correct?
8	8
9	9	Todo:
10		Add ~~the counter and~~ SIO to the cop420 core.
	10	Add SIO to the cop420 core.
11	11	Fix up my poor interpretation of the hard-to-read schematics.
12	12	Write a real SC-01 (SSI-263) emulator for MAME.
	13	Convert to tilemaps.
13	14	*/
14	15
15	16	#include "driver.h"
r894	r895
325	326	AM_RANGE(0xa0,0xa0) AM_WRITE(timer_int_w)
326	327	AM_RANGE(0xc0,0xc0) AM_WRITE(data_ready_int_w)
327	328
328		/* AM_RANGE(0xf0,0xf0) / / Laserdisc data read */
329		AM_RANGE(0xf1,0xf1) AM_READ(port_tag_to_handler8("DSWB")) /* 4 dips, 2 coins, Laserdisc 'ready' and 'enter' pins */
330		AM_RANGE(0xf2,0xf2) AM_READ(port_tag_to_handler8("DSWA")) /* 8 dips */
331		AM_RANGE(0xf3,0xf3) AM_WRITE(intrq_w) /* goes to !INTRQ */
332		/* AM_RANGE(0xf4,0xf4) / / Laserdisc data write */
333		/* AM_RANGE(0xf5,0xf5) / / Coin counter, 0xf4 write enable, DIP-controlled (SWB-6) LDV1000 'enter' line, and LDV1000 INT/!EXT line */
334		/* AM_RANGE(0xf6,0xf6) / / Scoreboard DEN1 */
335		/* AM_RANGE(0xf7,0xf7) / / Scoreboard DEN2 */
	329	/* AM_RANGE(0xf0,0xf0) / / Laserdisc data read */
	330	AM_RANGE(0xf1,0xf1) AM_READ_PORT("DSWB") /* 4 dips, 2 coins, Laserdisc 'ready' and 'enter' pins */
	331	AM_RANGE(0xf2,0xf2) AM_READ_PORT("DSWA") /* 8 dips */
	332	AM_RANGE(0xf3,0xf3) AM_WRITE(intrq_w) /* goes to /INTRQ */
	333	/* AM_RANGE(0xf4,0xf4) / / Laserdisc data write */
	334	/* AM_RANGE(0xf5,0xf5) / / Coin counter, 0xf4 write enable, DIP-controlled (SWB-6) LDV1000 'enter' line, and LDV1000 INT/!EXT line */
	335	/* AM_RANGE(0xf6,0xf6) / / Scoreboard DEN1 */
	336	/* AM_RANGE(0xf7,0xf7) / / Scoreboard DEN2 */
336	337	ADDRESS_MAP_END
337	338
338	339	static ADDRESS_MAP_START( copio, ADDRESS_SPACE_IO, 8 )

src/mame/drivers/topspeed.c
r894	r895
201	201	* 'topspedu' : region = 0x0004
202	202	- Coinage relies on the region (code at 0x00dd10) :
203	203	* 0x0001 (Japan), 0x0002 (US) and 0x0004 (US, Romstar licence) use TAITO_COINAGE_JAPAN_OLD
204		* 0x0003 (US) use TAITO_COINAGE_WORLD
	204	* 0x0003 (World) uses TAITO_COINAGE_WORLD
205	205	- Notice screen only if region = 0x0001
206	206	- Game name : "Top Speed"
207	207	- It's only possible to continue a game when you reach at least level 2

src/mame/drivers/spaceg.c
r894	r895
469	469	ROM_END
470	470
471	471
472		GAME( 1979, spaceg, 0, spaceg, spaceg, 0, ROT90, "Omori", "Space Guerilla", GAME_IMPERFECT_GRAPHICS \| GAME_NO_SOUND)
	472	GAME( 1979, spaceg, 0, spaceg, spaceg, 0, ROT90, "Omori", "Space Guerrilla", GAME_IMPERFECT_GRAPHICS \| GAME_NO_SOUND)

src/mame/drivers/upscope.c
r894	r895
288	288	static MACHINE_DRIVER_START( upscope )
289	289
290	290	/* basic machine hardware */
291		MDRV_CPU_ADD(M68000, ~~7159~~090~~) /* 7.159~~0~~9 Mhz (~~NTSC) */
	291	MDRV_CPU_ADD(M68000, AMIGA_68000_NTSC_CLOCK)
292	292	MDRV_CPU_PROGRAM_MAP(main_map,0)
293	293	MDRV_CPU_VBLANK_INT(amiga_scanline_callback, 262)
294	294

src/mame/drivers/m92.c
r894	r895
1592	1592	ROM_LOAD( "uc_w42.rom", 0x000000, 0x080000, CRC(d17d3fd6) SHA1(b02da0d01c41c7bf50cd35d6c75bacc3e3e0b85a) )
1593	1593	ROM_END
1594	1594
	1595	ROM_START( uccopsar ) /* Alpha Renewal Version */
	1596	ROM_REGION( 0x100000, REGION_CPU1, 0 )
	1597	ROM_LOAD16_BYTE( "uc_h0_a.ic28", 0x000001, 0x040000, CRC(9e17cada) SHA1(086bb9c1ab851cab3734c2f9188d8ff3c5f98913) )
	1598	ROM_LOAD16_BYTE( "uc_l0_a.ic39", 0x000000, 0x040000, CRC(4a4e3208) SHA1(d61c74d46584e2c15e70f7a17b598e51981da9e8) )
	1599	ROM_LOAD16_BYTE( "uc_h1.ic27", 0x080001, 0x020000, CRC(79d79742) SHA1(f9c03c4d42b5b3d0f0185462868b04f1bb679f90) )
	1600	ROM_LOAD16_BYTE( "uc_l1.ic38", 0x080000, 0x020000, CRC(37211581) SHA1(b8fdff96b2c7d5cf2975dcf81c00581ccb595c15) )
	1601
	1602	ROM_REGION( 0x100000, REGION_CPU2, 0 ) /* 1MB for the audio CPU - encrypted V30 = NANAO custom D80001 (?) */
	1603	ROM_LOAD16_BYTE( "uc_sh0.ic30", 0x000001, 0x010000, CRC(f0ca1b03) SHA1(07154a2c747091f8be23587c109d91ed1672da6e) )
	1604	ROM_LOAD16_BYTE( "uc_sl0.ic31", 0x000000, 0x010000, CRC(d1661723) SHA1(bdc00196aa2074e7b21e5949f73e9f2b93d76fd9) )
	1605
	1606	ROM_REGION( 0x200000, REGION_GFX1, ROMREGION_DISPOSE ) /* Tiles */
	1607	ROM_LOAD( "uc_c0.ic26", 0x000000, 0x080000, CRC(6a419a36) SHA1(1907d15fcc4a8bf875d19768667ee4de4702cc2a) )
	1608	ROM_LOAD( "uc_c1.ic25", 0x080000, 0x080000, CRC(d703ecc7) SHA1(9716a8fde668e63cf3060450eb32ea43edf143d8) )
	1609	ROM_LOAD( "uc_c2.ic24", 0x100000, 0x080000, CRC(96397ac6) SHA1(6dfe507bd9f41b5d46d85ef5f46a368745593b52) )
	1610	ROM_LOAD( "uc_c3.ic23", 0x180000, 0x080000, CRC(5d07d10d) SHA1(ee1a928b37043c476346f189f75d2bfcc44bffe6) )
	1611
	1612	ROM_REGION( 0x400000, REGION_GFX2, ROMREGION_DISPOSE ) /* Sprites */
	1613	ROM_LOAD( "uc_030.ic37", 0x000000, 0x100000, CRC(97f7775e) SHA1(5cd147fd940b1ab6eba8e6c6f803bdcc5da5a563) )
	1614	ROM_LOAD( "uc_020.ic36", 0x100000, 0x100000, CRC(5e0b1d65) SHA1(9e45753d10b2d7b580cd11cef74181209a424189) )
	1615	ROM_LOAD( "uc_010.ic35", 0x200000, 0x100000, CRC(bdc224b3) SHA1(09477ec39890d954fac6ff653b9f46c9adea56b6) )
	1616	ROM_LOAD( "uc_000.ic34", 0x300000, 0x100000, CRC(7526daec) SHA1(79431d711deb6ed09dc52be753b7b0f2c5588dc3) )
	1617
	1618	ROM_REGION( 0x80000, REGION_SOUND1, 0 )
	1619	ROM_LOAD( "uc_da.bin", 0x000000, 0x080000, CRC(0b2855e9) SHA1(70f9decd78eab679a2ccad69e01cb303b61e0d38) )
	1620	ROM_END
	1621
1595	1622	ROM_START( uccopsj )
1596	1623	ROM_REGION( 0x100000, REGION_CPU1, 0 )
1597		ROM_LOAD16_BYTE( "uca-h0.bin", 0x000001, 0x040000, CRC(9e17cada) SHA1(086bb9c1ab851cab3734c2f9188d8ff3c5f98913) )
1598		ROM_LOAD16_BYTE( "uca-l0.bin", 0x000000, 0x040000, CRC(4a4e3208) SHA1(d61c74d46584e2c15e70f7a17b598e51981da9e8) )
1599		ROM_LOAD16_BYTE( "uca-h1.bin", 0x080001, 0x020000, CRC(83f78dea) SHA1(6d197c3ea76beac31c3ea6e54a3ffea9d6c0c653) )
1600		ROM_LOAD16_BYTE( "uca-l1.bin", 0x080000, 0x020000, CRC(19628280) SHA1(e6c06cb7c37e46a7db3b4f318e836aa5a2390eda) )
	1624	ROM_LOAD16_BYTE( "uc_h0_a.ic28", 0x000001, 0x040000, CRC(9e17cada) SHA1(086bb9c1ab851cab3734c2f9188d8ff3c5f98913) )
	1625	ROM_LOAD16_BYTE( "uc_l0_a.ic39", 0x000000, 0x040000, CRC(4a4e3208) SHA1(d61c74d46584e2c15e70f7a17b598e51981da9e8) )
	1626	ROM_LOAD16_BYTE( "uc_h1_a.ic27", 0x080001, 0x020000, CRC(83f78dea) SHA1(6d197c3ea76beac31c3ea6e54a3ffea9d6c0c653) )
	1627	ROM_LOAD16_BYTE( "uc_l1_a.ic38", 0x080000, 0x020000, CRC(19628280) SHA1(e6c06cb7c37e46a7db3b4f318e836aa5a2390eda) )
1601	1628
1602	1629	ROM_REGION( 0x100000, REGION_CPU2, 0 ) /* 1MB for the audio CPU - encrypted V30 = NANAO custom D80001 (?) */
1603		ROM_LOAD16_BYTE( "uca-sh0.bin", 0x000001, 0x010000, CRC(f0ca1b03) SHA1(07154a2c747091f8be23587c109d91ed1672da6e) )
1604		ROM_LOAD16_BYTE( "uca-sl0.bin", 0x000000, 0x010000, CRC(d1661723) SHA1(bdc00196aa2074e7b21e5949f73e9f2b93d76fd9) )
	1630	ROM_LOAD16_BYTE( "uc_sh0.ic30", 0x000001, 0x010000, CRC(f0ca1b03) SHA1(07154a2c747091f8be23587c109d91ed1672da6e) )
	1631	ROM_LOAD16_BYTE( "uc_sl0.ic31", 0x000000, 0x010000, CRC(d1661723) SHA1(bdc00196aa2074e7b21e5949f73e9f2b93d76fd9) )
1605	1632
1606	1633	ROM_REGION( 0x200000, REGION_GFX1, ROMREGION_DISPOSE ) /* Tiles */
1607		ROM_LOAD( "uca-c0.bin", 0x000000, 0x080000, CRC(6a419a36) SHA1(1907d15fcc4a8bf875d19768667ee4de4702cc2a) )
1608		ROM_LOAD( "uca-c1.bin", 0x080000, 0x080000, CRC(d703ecc7) SHA1(9716a8fde668e63cf3060450eb32ea43edf143d8) )
1609		ROM_LOAD( "uca-c2.bin", 0x100000, 0x080000, CRC(96397ac6) SHA1(6dfe507bd9f41b5d46d85ef5f46a368745593b52) )
1610		ROM_LOAD( "uca-c3.bin", 0x180000, 0x080000, CRC(5d07d10d) SHA1(ee1a928b37043c476346f189f75d2bfcc44bffe6) )
	1634	ROM_LOAD( "uc_c0.ic26", 0x000000, 0x080000, CRC(6a419a36) SHA1(1907d15fcc4a8bf875d19768667ee4de4702cc2a) )
	1635	ROM_LOAD( "uc_c1.ic25", 0x080000, 0x080000, CRC(d703ecc7) SHA1(9716a8fde668e63cf3060450eb32ea43edf143d8) )
	1636	ROM_LOAD( "uc_c2.ic24", 0x100000, 0x080000, CRC(96397ac6) SHA1(6dfe507bd9f41b5d46d85ef5f46a368745593b52) )
	1637	ROM_LOAD( "uc_c3.ic23", 0x180000, 0x080000, CRC(5d07d10d) SHA1(ee1a928b37043c476346f189f75d2bfcc44bffe6) )
1611	1638
1612	1639	ROM_REGION( 0x400000, REGION_GFX2, ROMREGION_DISPOSE ) /* Sprites */
1613		ROM_LOAD( "uca-o3.bin", 0x000000, 0x100000, CRC(97f7775e) SHA1(5cd147fd940b1ab6eba8e6c6f803bdcc5da5a563) )
1614		ROM_LOAD( "uca-o2.bin", 0x100000, 0x100000, CRC(5e0b1d65) SHA1(9e45753d10b2d7b580cd11cef74181209a424189) )
1615		ROM_LOAD( "uca-o1.bin", 0x200000, 0x100000, CRC(bdc224b3) SHA1(09477ec39890d954fac6ff653b9f46c9adea56b6) )
1616		ROM_LOAD( "uca-o0.bin", 0x300000, 0x100000, CRC(7526daec) SHA1(79431d711deb6ed09dc52be753b7b0f2c5588dc3) )
	1640	ROM_LOAD( "uc_030.ic37", 0x000000, 0x100000, CRC(97f7775e) SHA1(5cd147fd940b1ab6eba8e6c6f803bdcc5da5a563) )
	1641	ROM_LOAD( "uc_020.ic36", 0x100000, 0x100000, CRC(5e0b1d65) SHA1(9e45753d10b2d7b580cd11cef74181209a424189) )
	1642	ROM_LOAD( "uc_010.ic35", 0x200000, 0x100000, CRC(bdc224b3) SHA1(09477ec39890d954fac6ff653b9f46c9adea56b6) )
	1643	ROM_LOAD( "uc_000.ic34", 0x300000, 0x100000, CRC(7526daec) SHA1(79431d711deb6ed09dc52be753b7b0f2c5588dc3) )
1617	1644
1618	1645	ROM_REGION( 0x80000, REGION_SOUND1, 0 )
1619		ROM_LOAD( "uca-da.bin", 0x000000, 0x080000, CRC(0b2855e9) SHA1(70f9decd78eab679a2ccad69e01cb303b61e0d38) )
	1646	ROM_LOAD( "uc_da.bin", 0x000000, 0x080000, CRC(0b2855e9) SHA1(70f9decd78eab679a2ccad69e01cb303b61e0d38) )
1620	1647	ROM_END
1621	1648
1622	1649	ROM_START( lethalth )
r894	r895
2016	2043	GAME( 1991, lethalth, 0, lethalth, lethalth, lethalth, ROT270, "Irem", "Lethal Thunder (World)", 0 )
2017	2044	GAME( 1991, thndblst, lethalth, lethalth, lethalth, lethalth, ROT270, "Irem", "Thunder Blaster (Japan)", 0 )
2018	2045	GAME( 1992, uccops, 0, m92, uccops, uccops, ROT0, "Irem", "Undercover Cops (World)", 0 )
	2046	GAME( 1992, uccopsar, uccops, m92, uccops, uccops, ROT0, "Irem", "Undercover Cops (Alpha Renewal Version)", 0 )
2019	2047	GAME( 1992, uccopsj, uccops, m92, uccops, uccops, ROT0, "Irem", "Undercover Cops (Japan)", 0 )
2020	2048	GAME( 1992, mysticri, 0, m92, mysticri, mysticri, ROT0, "Irem", "Mystic Riders (World)", 0 )
2021	2049	GAME( 1992, gunhohki, mysticri, m92, mysticri, mysticri, ROT0, "Irem", "Gun Hohki (Japan)", 0 )

src/mame/drivers/mcr.c
r894	r895
2543	2543	GAME( 1981, solarfox, 0, mcr_90009, solarfox, solarfox, ROT90 ^ ORIENTATION_FLIP_Y, "Bally Midway", "Solar Fox (upright)", GAME_SUPPORTS_SAVE )
2544	2544	GAME( 1981, kick, 0, mcr_90009, kick, kick, ORIENTATION_SWAP_XY, "Midway", "Kick (upright)", GAME_SUPPORTS_SAVE )
2545	2545	GAME( 1981, kickman, kick, mcr_90009, kick, kick, ORIENTATION_SWAP_XY, "Midway", "Kickman (upright)", GAME_SUPPORTS_SAVE )
2546		GAME( 1981, kickc, kick, mcr_90009, kickc, kick, ROT90, "Midway", "Kick (cocktail", GAME_SUPPORTS_SAVE )
	2546	GAME( 1981, kickc, kick, mcr_90009, kickc, kick, ROT90, "Midway", "Kick (cocktail)", GAME_SUPPORTS_SAVE )
2547	2547
2548	2548	/* 90010 CPU board + 91399 video gen + 90913 sound I/O */
2549	2549	GAME( 1981, shollow, 0, mcr_90010, shollow, mcr_90010, ROT90, "Bally Midway", "Satan's Hollow (set 1)", GAME_SUPPORTS_SAVE )

src/mame/drivers/ninjaw.c
r894	r895
128	128	* 'ninjawj' : region = 0x0000
129	129	- Coinage relies on the region (code at 0x0013bc) :
130	130	* 0x0000 (Japan), 0x0001 (?) and 0x0002 (US) use TAITO_COINAGE_JAPAN_OLD
131		* 0x0003 (World) and 0x0004 ~~to 0x0007~~ (licenced to xxx) use TAITO_COINAGE_WORLD
	131	* 0x0003 (World) and 0x0004 (licenced to xxx) use TAITO_COINAGE_WORLD
132	132	- Notice screen only if region = 0x0000
133	133	- According to the manual, DSWB bit 6 determines continue pricing :
134	134
r894	r895
154	154	* 0x0000 (?), 0x0001 (Japan) and 0x0002 (US) use TAITO_COINAGE_JAPAN_OLD
155	155	* 0x0002 (US, licenced to ROMSTAR) uses slighlty different TAITO_COINAGE_US :
156	156	4C_3C instead of 4C_1C, same other settings otherwise
157		* 0x0003 (World) ~~and 0x0004 to 0x0007 (?)~~ use TAITO_COINAGE_WORLD
	157	* 0x0003 (World) uses TAITO_COINAGE_WORLD
158	158	- Texts and game name rely on the region :
159	159	* 0x0001 : some texts in Japanese - game name is "Darius II"
160	160	* other : all texts in English - game name is "Sagaia"

src/mame/drivers/dec8.c
r894	r895
1481	1481	PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
1482	1482	INPUT_PORTS_END
1483	1483
	1484	INPUT_PORTS_START( oscarj0 )
	1485	PORT_START_TAG("IN0")
	1486	PLAYER1_JOYSTICK
	1487	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
	1488	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
	1489	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
	1490	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 )
	1491
	1492	PORT_START_TAG("IN1")
	1493	PLAYER2_JOYSTICK
	1494	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
	1495	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
	1496	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_COCKTAIL
	1497	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
	1498
	1499	PORT_START_TAG("IN2")
	1500	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
	1501	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
	1502	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
	1503	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1504	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1505	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1506	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1507	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_VBLANK )
	1508
	1509	PORT_START_TAG("DSW0")
	1510	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) )
	1511	PORT_DIPSETTING( 0x03, DEF_STR( 1C_2C ) )
	1512	PORT_DIPSETTING( 0x02, DEF_STR( 1C_3C ) )
	1513	PORT_DIPSETTING( 0x01, DEF_STR( 1C_4C ) )
	1514	PORT_DIPSETTING( 0x00, DEF_STR( 1C_6C ) )
	1515	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Coin_B ) )
	1516	PORT_DIPSETTING( 0x00, DEF_STR( 4C_1C ) )
	1517	PORT_DIPSETTING( 0x04, DEF_STR( 3C_1C ) )
	1518	PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
	1519	PORT_DIPSETTING( 0x0c, DEF_STR( 1C_1C ) )
	1520	PORT_DIPNAME( 0x10, 0x10, "Freeze Mode" )
	1521	PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
	1522	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1523	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) )
	1524	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	1525	PORT_DIPSETTING( 0x20, DEF_STR( On ) )
	1526	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Flip_Screen ) )
	1527	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	1528	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1529	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Cabinet ) )
	1530	PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
	1531	PORT_DIPSETTING( 0x80, DEF_STR( Cocktail ) )
	1532
	1533	PORT_START_TAG("DSW1")
	1534	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) )
	1535	PORT_DIPSETTING( 0x01, "1" )
	1536	PORT_DIPSETTING( 0x03, "3" )
	1537	PORT_DIPSETTING( 0x02, "5" )
	1538	PORT_DIPSETTING( 0x00, "Infinite (Cheat)")
	1539	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Difficulty ) )
	1540	PORT_DIPSETTING( 0x04, DEF_STR( Easy ) )
	1541	PORT_DIPSETTING( 0x0c, DEF_STR( Normal ) )
	1542	PORT_DIPSETTING( 0x08, DEF_STR( Hard ) )
	1543	PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )
	1544	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Bonus_Life ) )
	1545	PORT_DIPSETTING( 0x30, "Every 40000" )
	1546	PORT_DIPSETTING( 0x20, "Every 60000" )
	1547	PORT_DIPSETTING( 0x10, "Every 90000" )
	1548	PORT_DIPSETTING( 0x00, "50000 only" )
	1549	PORT_DIPNAME( 0x40, 0x40, "Invulnerability (Cheat)")
	1550	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	1551	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1552	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Allow_Continue ) )
	1553	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
	1554	PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
	1555	INPUT_PORTS_END
	1556
1484	1557	INPUT_PORTS_START( lastmisn )
1485	1558	PORT_START_TAG("IN0")
1486	1559	PLAYER1_JOYSTICK
r894	r895
3421	3494	GAME( 1988, oscar, 0, oscar, oscar, deco222, ROT0, "Data East USA", "Psycho-Nics Oscar (US)", 0 )
3422	3495	GAME( 1987, oscarj, oscar, oscar, oscar, deco222, ROT0, "Data East Corporation", "Psycho-Nics Oscar (Japan revision 2)", 0 )
3423	3496	GAME( 1987, oscarj1, oscar, oscar, oscar, deco222, ROT0, "Data East Corporation", "Psycho-Nics Oscar (Japan revision 1)", 0 )
3424		GAME( 1987, oscarj0, oscar, oscar, oscar, deco222, ROT0, "Data East Corporation", "Psycho-Nics Oscar (Japan revision 0)", 0 )
	3497	GAME( 1987, oscarj0, oscar, oscar, oscarj0, deco222, ROT0, "Data East Corporation", "Psycho-Nics Oscar (Japan revision 0)", 0 )
3425	3498	GAME( 1986, lastmisn, 0, lastmiss, lastmisn, 0, ROT270, "Data East USA", "Last Mission (US revision 6)", 0 )
3426	3499	GAME( 1986, lastmsno, lastmisn, lastmiss, lastmisn, 0, ROT270, "Data East USA", "Last Mission (US revision 5)", 0 )
3427	3500	GAME( 1986, lastmsnj, lastmisn, lastmiss, lastmsnj, 0, ROT270, "Data East Corporation", "Last Mission (Japan)", 0 )

src/mame/drivers/asuka.c
r894	r895
88	88	* 0x0000 (Japan) and 0x0001 (US) use TAITO_COINAGE_JAPAN_OLD
89	89	* 0x0002 (World) uses TAITO_COINAGE_WORLD
90	90	- Notice screen only if region = 0x0000
91		- Most texts in Japanese and alternate title screen only if region = 0x0000
	91	- Texts and game name rely on the region :
	92	* 0x0000 : most texts in Japanese - game name is "Jigoku Meguri"
	93	* other : all texts in English - game name is "Bonze Adventure"
92	94	- Bonus lives aren't awarded correctly due to bogus code at 0x00961e :
93	95
94	96	00961E: 302D 0B7E move.w ($b7e,A5), D0
r894	r895
152	154	However each version requires its specific texts
153	155	- Coinage relies on the region (code at 0x0013d6) :
154	156	* 0x0001 (Japan) uses TAITO_COINAGE_JAPAN_OLD
155		* 0x0002 (US) uses TAITO_COINAGE_~~JAPAN_OLD~~
	157	* 0x0002 (US) uses TAITO_COINAGE_US
156	158	* 0x0003 (World) uses TAITO_COINAGE_WORLD
157	159	- Notice screen only if region = 0x0001 or region = 0x0002
158	160	- FBI logo only if region = 0x0002

src/mame/drivers/mquake.c
r894	r895
350	350	static MACHINE_DRIVER_START( mquake )
351	351
352	352	/* basic machine hardware */
353		MDRV_CPU_ADD(M68000, ~~7159~~090~~) /* 7.159~~0~~9 Mhz (~~NTSC) */
	353	MDRV_CPU_ADD(M68000, AMIGA_68000_NTSC_CLOCK)
354	354	MDRV_CPU_PROGRAM_MAP(main_map,0)
355	355	MDRV_CPU_VBLANK_INT(amiga_scanline_callback, 262)
356	356

src/tools/chdcd.c
r894	r895
9	9
10	10	#include "osdcore.h"
11	11	#include "chd.h"
12		#include "cd~~rom~~.h"
	12	#include "chdcd.h"
13	13	#include <stdio.h>
14	14	#include <string.h>
15	15	#include <ctype.h>
r894	r895
20	20	CONSTANTS & DEFINES
21	21	***************************************************************************/
22	22
23		#define EATWHITESPACE \
24		while ((linebuffer[i] == ' ' \|\| linebuffer[i] == 0x09 \|\| linebuffer[i] == '\r') && (i < 512)) \
25		{ \
26		i++; \
27		}
	23	#define TOKENIZE i = tokenize( linebuffer, i, sizeof(linebuffer), token, sizeof(token) );
28	24
29		#define EATQUOTE \
30		while ((linebuffer[i] == '"' \|\| linebuffer[i] == '\'') && (i < 512)) \
31		{ \
32		i++; \
33		}
34	25
35		#define TOKENIZE \
36		j = 0; \
37		while (!isspace(linebuffer[i]) && (i < 512) && (j < 128)) \
38		{ \
39		token[j] = linebuffer[i]; \
40		i++; \
41		j++; \
42		} \
43		token[j] = '\0';
44	26
45
46
47	27	/***************************************************************************
48	28	GLOBAL VARIABLES
49	29	***************************************************************************/
r894	r895
74	54
75	55
76	56	/*-------------------------------------------------
77		~~cdrom_parse_~~toc - ~~pars~~e a ~~CDRDAO~~ format ~~TOC~~ file
	57	tokenize - get a token from the line buffer
78	58	-------------------------------------------------*/
79	59
80		static void sh~~ow_r~~a~~w_m~~essage(void)
	60	static int tokenize( const char linebuffer, int i, int linebuffersize, char token, int tokensize )
81	61	{
82		printf("Note: MAME now prefers and can accept RAW format images.\n");
83		printf("At least one track of this CDRDAO rip is not either RAW or AUDIO.\n");
	62	int j = 0;
	63	int singlequote = 0;
	64	int doublequote = 0;
	65
	66	while ((i < linebuffersize) && isspace(linebuffer[i]))
	67	{
	68	i++;
	69	}
	70
	71	while ((i < linebuffersize) && (j < tokensize))
	72	{
	73	if (!singlequote && linebuffer[i] == '"' )
	74	{
	75	doublequote = !doublequote;
	76	}
	77	else if (!doublequote && linebuffer[i] == '\'')
	78	{
	79	singlequote = !singlequote;
	80	}
	81	else if (!singlequote && !doublequote && isspace(linebuffer[i]))
	82	{
	83	break;
	84	}
	85	else
	86	{
	87	token[j] = linebuffer[i];
	88	j++;
	89	}
	90
	91	i++;
	92	}
	93
	94	token[j] = '\0';
	95
	96	return i;
84	97	}
85	98
86		chd_error cdrom_parse_toc(const char tocfname, cdrom_toc outtoc, cdrom_track_input_info *outinfo)
	99
	100	/*-------------------------------------------------
	101	msf_to_frames - convert m:s:f into a number of frames
	102	-------------------------------------------------*/
	103
	104	static int msf_to_frames( char *token )
87	105	{
	106	int m = 0;
	107	int s = 0;
	108	int f = 0;
	109
	110	if( sscanf( token, "%d:%d:%d", &m, &s, &f ) == 1 )
	111	{
	112	f = m;
	113	}
	114	else
	115	{
	116	/* convert to just frames */
	117	s += (m * 60);
	118	f += (s * 75);
	119	}
	120
	121	return f;
	122	}
	123
	124
	125	/*-------------------------------------------------
	126	chdcd_parse_toc - parse a CDRDAO format TOC file
	127	-------------------------------------------------*/
	128
	129	chd_error chdcd_parse_toc(const char tocfname, cdrom_toc outtoc, chdcd_track_input_info *outinfo)
	130	{
88	131	FILE *infile;
89		int i, j, trknum~~, m, s, f~~;
	132	int i, trknum;
90	133	static char token[128];
91	134
92	135	infile = fopen(tocfname, "rt");
r894	r895
98	141
99	142	/* clear structures */
100	143	memset(outtoc, 0, sizeof(cdrom_toc));
101		memset(outinfo, 0, sizeof(cd~~rom~~_track_input_info));
	144	memset(outinfo, 0, sizeof(chdcd_track_input_info));
102	145
103	146	trknum = -1;
104	147
r894	r895
111	154	if (!feof(infile))
112	155	{
113	156	i = 0;
114		~~EATWHITESPACE~~
	157
115	158	TOKENIZE
116	159
117	160	if ((!strcmp(token, "DATAFILE")) \|\| (!strcmp(token, "AUDIOFILE")) \|\| (!strcmp(token, "FILE")))
118	161	{
	162	int f;
	163
119	164	/* found the data file for a track */
120		EATWHITESPACE
121		EATQUOTE
122	165	TOKENIZE
123	166
124		/* remove trailing quote if any */
125		if (token[strlen(token)-1] == '"')
126		{
127		token[strlen(token)-1] = '\0';
128		}
129
130	167	/* keep the filename */
131	168	strncpy(&outinfo->fname[trknum][0], token, strlen(token));
132	169
133	170	/* get either the offset or the length */
134		EATWHITESPACE
135	171	TOKENIZE
136	172
137		m = 0;
138		s = 0;
139		f = 0;
	173	if (!strcmp(token, "SWAP"))
	174	{
	175	TOKENIZE
140	176
	177	outinfo->swap[trknum] = 1;
	178	}
	179	else
	180	{
	181	outinfo->swap[trknum] = 0;
	182	}
	183
141	184	if (token[0] == '#')
142	185	{
143	186	/* it's a decimal offset, use it */
r894	r895
145	188	}
146	189	else if (isdigit(token[0]))
147	190	{
148		sscanf( token, "%d:%d:%d", &m, &s, &f );
	191	/* convert the time to an offset */
	192	f = msf_to_frames( token );
149	193
150		/* convert to just frames */
151		s += (m * 60);
152		f += (s * 75);
153
154	194	f *= (outtoc->tracks[trknum].datasize + outtoc->tracks[trknum].subsize);
155	195	}
	196	else
	197	{
	198	f = 0;
	199	}
156	200
157	201	outinfo->offset[trknum] = f;
158	202
159		EATWHITESPACE
160	203	TOKENIZE
161	204
162		m = 0;
163		s = 0;
164		f = 0;
165
166	205	if (isdigit(token[0]))
167	206	{
168		if( sscanf( token, "%d:%d:%d", &m, &s, &f ) == 1 )
	207	// this could be the length or an offset from the previous field.
	208	f = msf_to_frames( token );
	209
	210	TOKENIZE
	211
	212	if (isdigit(token[0]))
169	213	{
170		f = m;
	214	// it was an offset.
	215	f *= (outtoc->tracks[trknum].datasize + outtoc->tracks[trknum].subsize);
	216
	217	outinfo->offset[trknum] += f;
	218
	219	// this is the length.
	220	f = msf_to_frames( token );
171	221	}
172		else
173		{
174		/* convert to just frames */
175		s += (m * 60);
176		f += (s * 75);
177		}
178	222	}
179	223	else if( trknum == 0 && outinfo->offset[trknum] != 0 )
180	224	{
r894	r895
203	247	trknum++;
204	248
205	249	/* next token on the line is the track type */
206		EATWHITESPACE
207	250	TOKENIZE
208	251
209	252	outtoc->tracks[trknum].trktype = CD_TRACK_MODE1;
r894	r895
213	256
214	257	cdrom_convert_type_string_to_track_info(token, &outtoc->tracks[trknum]);
215	258	if (outtoc->tracks[trknum].datasize == 0)
	259	{
216	260	printf("ERROR: Unknown track type [%s]. Contact MAMEDEV.\n", token);
	261	}
217	262	else if (outtoc->tracks[trknum].trktype != CD_TRACK_MODE1_RAW &&
218		outtoc->tracks[trknum].trktype != CD_TRACK_MODE2_RAW &&
219		outtoc->tracks[trknum].trktype != CD_TRACK_AUDIO)
220		show_raw_message();
	263	outtoc->tracks[trknum].trktype != CD_TRACK_MODE2_RAW &&
	264	outtoc->tracks[trknum].trktype != CD_TRACK_AUDIO)
	265	{
	266	printf("Note: MAME now prefers and can accept RAW format images.\n");
	267	printf("At least one track of this CDRDAO rip is not either RAW or AUDIO.\n");
	268	}
221	269
222	270	/* next (optional) token on the line is the subcode type */
223		EATWHITESPACE
224	271	TOKENIZE
225	272
226	273	cdrom_convert_subtype_string_to_track_info(token, &outtoc->tracks[trknum]);

src/tools/chdcd.h
r894	r895
14	14
15	15	#include "cdrom.h"
16	16
17		chd_error cdrom_parse_toc(const char tocfname, cdrom_toc outtoc, cdrom_track_input_info *outinfo);
	17	typedef struct _chdcd_track_input_info chdcd_track_input_info;
	18	struct _chdcd_track_input_info /* used only at compression time */
	19	{
	20	char fname[CD_MAX_TRACKS][256]; /* filename for each track */
	21	UINT32 offset[CD_MAX_TRACKS]; /* offset in the data file for each track */
	22	int swap[CD_MAX_TRACKS]; /* data needs to be byte swapped */
	23	};
18	24
	25
	26	chd_error chdcd_parse_toc(const char tocfname, cdrom_toc outtoc, chdcd_track_input_info *outinfo);
	27
19	28	#endif /* __CHDCD_H__ */

src/tools/chdman.c
r894	r895
451	451
452	452	static int do_createcd(int argc, char *argv[], int param)
453	453	{
454		static cd~~rom~~_track_input_info track_info;
	454	static chdcd_track_input_info track_info;
455	455	static cdrom_toc toc;
456	456	UINT32 hunksize = CD_FRAME_SIZE * CD_FRAMES_PER_HUNK;
457	457	UINT32 sectorsize = CD_FRAME_SIZE;
r894	r895
484	484	}
485	485
486	486	/* setup the CDROM module and get the disc info */
487		err = cd~~rom~~_parse_toc(inputfile, &toc, &track_info);
	487	err = chdcd_parse_toc(inputfile, &toc, &track_info);
488	488	if (err != CHDERR_NONE)
489	489	{
490	490	fprintf(stderr, "Error reading input file: %s\n", error_string(err));
r894	r895
550	550	totalhunks = 0;
551	551	for (i = 0; i < toc.numtrks; i++)
552	552	{
	553	int frames = 0;
553	554	int bytespersector = toc.tracks[i].datasize + toc.tracks[i].subsize;
554	555	int trackhunks = (toc.tracks[i].frames + toc.tracks[i].extraframes) / CD_FRAMES_PER_HUNK;
555	556	UINT64 sourcefileoffset = track_info.offset[i];
r894	r895
564	565	goto cleanup;
565	566	}
566	567
567		printf("~~Comp~~r~~essing tr~~ack %d / %d (~~file~~ %s:%d, %d frames, %d hunks)\n", i+1, toc.numtrks, track_info.fname[i], track_info.offset[i], toc.tracks[i].frames, trackhunks);
	568	printf("Track %d/%d (%s:%d,%d frames,%d hunks,swap %d)\n", i+1, toc.numtrks, track_info.fname[i], track_info.offset[i], toc.tracks[i].frames, trackhunks, track_info.swap[i]);
568	569
569	570	/* loop over hunks */
570	571	for (curhunk = 0; curhunk < trackhunks; curhunk++, totalhunks++)
r894	r895
579	580	memset(cache, 0, hunksize);
580	581	for (secnum = 0; secnum < CD_FRAMES_PER_HUNK; secnum++)
581	582	{
582		chdman_read(srcfile, sourcefileoffset, bytespersector, &cache[secnum * CD_FRAME_SIZE]);
	583	if (frames < toc.tracks[i].frames)
	584	{
	585	chdman_read(srcfile, sourcefileoffset, bytespersector, &cache[secnum * CD_FRAME_SIZE]);
	586
	587	if (track_info.swap[i])
	588	{
	589	int swapindex;
	590
	591	for (swapindex = 0; swapindex < 2352; swapindex += 2 )
	592	{
	593	int swapoffset = ( secnum * CD_FRAME_SIZE ) + swapindex;
	594
	595	int swaptemp = cache[ swapoffset ];
	596	cache[ swapoffset ] = cache[ swapoffset + 1 ];
	597	cache[ swapoffset + 1 ] = swaptemp;
	598	}
	599	}
	600	}
	601
583	602	sourcefileoffset += bytespersector;
	603	frames++;
584	604	}
585	605
586	606	/* compress the current hunk */

src/osd/windows/verinfo.c
r894	r895
7	7	//
8	8	//============================================================
9	9
	10	#include <stdio.h>
10	11	#include <ctype.h>
11		#include <stdio.h>
12	12
13	13	#include "osdcore.h"
14	14
15	15
16		extern char build_version[];
17
18
19
20	16	//============================================================
21	17	// TYPE DEFINITIONS
22	18	//============================================================
r894	r895
28	24	int version_minor;
29	25	int version_build;
30	26	int version_subbuild;
	27	const char *version_string;
31	28	const char *author;
32	29	const char *comments;
33	30	const char *company_name;
r894	r895
90	87	printf("\t\t\tVALUE \"OriginalFilename\", \"%s\\0\"\n", v->original_filename);
91	88	if (v->product_name != NULL)
92	89	printf("\t\t\tVALUE \"ProductName\", \"%s\\0\"\n", v->product_name);
93		printf("\t\t\tVALUE \"ProductVersion\", \"%s\\0\"\n", ~~build_~~version);
	90	printf("\t\t\tVALUE \"ProductVersion\", \"%s\\0\"\n", v->version_string);
94	91	printf("\t\tEND\n");
95	92	printf("\tEND\n");
96	93	printf("\tBLOCK \"VarFileInfo\"\n");
r894	r895
114	111	{
115	112	int value = 0;
116	113
117		while(str[position] && !isspace(str[position]) && !isdigit(str[*position]))
118		{
	114	while (str[position] != 0 && !isspace(str[position]) && !isdigit(str[*position]))
119	115	(*position)++;
120		}
121		if (str[position] && isdigit(str[position]))
	116
	117	if (str[position] != 0 && isdigit(str[position]))
122	118	{
123	119	sscanf(&str[*position], "%d", &value);
124		while(isdigit(str[*position]))
	120	while (isdigit(str[*position]))
125	121	(*position)++;
126	122	}
127	123	return value;
r894	r895
133	129	// parse_version
134	130	//============================================================
135	131
136		static void parse_version(const char str, int version_major, int *version_minor,
137		int version_micro, int year)
	132	static int parse_version(char str, int version_major, int version_minor, int version_micro, int year, const char *version_string)
138	133	{
	134	char *copyright;
	135	char *version;
139	136	int position = 0;
140		int day = 0;
141		char month[3];
142	137
143		*version_major = parse_version_digit(str, &position);
144		*version_minor = parse_version_digit(str, &position);
145		*version_micro = parse_version_digit(str, &position);
	138	// find the version string
	139	version = strstr(str, "build_version");
	140	if (version != NULL)
	141	version = strchr(version, '"');
	142	if (version == NULL)
	143	{
	144	fprintf(stderr, "Unable to find build_version string\n");
	145	return 1;
	146	}
	147	version++;
	148	*strchr(version, ' ') = 0;
146	149
	150	*version_string = version;
	151	*version_major = parse_version_digit(version, &position);
	152	*version_minor = parse_version_digit(version, &position);
	153	*version_micro = parse_version_digit(version, &position);
	154
	155	// find the copyright string
	156	copyright = strstr(str, "(c)");
	157	if (copyright != NULL)
	158	copyright = strchr(copyright, '-');
	159	if (copyright == NULL)
	160	{
	161	fprintf(stderr, "Unable to find copyright string\n");
	162	return 1;
	163	}
	164	copyright++;
	165
147	166	*year = 0;
148		sscanf(&str[position], " (%c%c%c %d %d)", &month[0], &month[1], &month[2], &day, year);
	167	sscanf(copyright, "%d", year);
	168	return 0;
149	169	}
150	170
151	171
r894	r895
154	174	// main
155	175	//============================================================
156	176
157		int ~~CLIB_DECL~~ main(int argc, char **argv)
	177	int main(int argc, char *argv[])
158	178	{
159	179	version_info v;
160	180	int begin_year, current_year;
161	181	char legal_copyright[512];
	182	char *buffer;
	183	size_t size;
	184	FILE *f;
162	185
163	186	memset(&v, 0, sizeof(v));
164	187
	188	// validate parameters
	189	if (argc < 2)
	190	{
	191	printf("Usage: %s <filename>\n", argv[0]);
	192	return 0;
	193	}
	194
	195	// open the file
	196	f = fopen(argv[1], "rb");
	197	if (f == NULL)
	198	{
	199	fprintf(stderr, "Error opening file %s\n", argv[1]);
	200	return 1;
	201	}
	202
	203	// get the file size
	204	fseek(f, 0, SEEK_END);
	205	size = ftell(f);
	206	fseek(f, 0, SEEK_SET);
	207
	208	// allocate a buffer
	209	buffer = malloc(size + 1);
	210	if (buffer == NULL)
	211	{
	212	fclose(f);
	213	fprintf(stderr, "Error allocating %d bytes\n", size + 1);
	214	return 1;
	215	}
	216
	217	// read the file contents and NULL-terminate
	218	fread(buffer, 1, size, f);
	219	fclose(f);
	220	buffer[size] = 0;
	221
165	222	// parse out version string
166		parse_version(build_version, &v.version_major, &v.version_minor, &v.version_build, &current_year);
	223	if (parse_version(buffer, &v.version_major, &v.version_minor, &v.version_build, &current_year, &v.version_string))
	224	return 1;
167	225
168	226	#ifdef MESS
169	227	// MESS
r894	r895
203	261
204	262	// emit the info
205	263	emit_version_info(&v);
	264
	265	free(buffer);
206	266	return 0;
207	267	}

src/emu/cpu/cpu.mak
r894	r895
15	15
16	16
17	17	#-------------------------------------------------
	18	# Dynamic recompiler objects
	19	#-------------------------------------------------
	20
	21	DRCOBJ = $(CPUOBJ)/x86drc.o
	22
	23	DRCDEPS = $(CPUSRC)/x86drc.c \
	24	$(CPUSRC)/x86drc.h \
	25
	26	$(DRCOBJ): $(DRCDEPS)
	27
	28
	29
	30	#-------------------------------------------------
18	31	# Acorn ARM series
19	32	#-------------------------------------------------
20	33
r894	r895
764	777	DBGOBJS += $(CPUOBJ)/mips/mips3dsm.o
765	778
766	779	ifdef X86_MIPS3_DRC
767		CPUOBJS += $(CPUOBJ)/mips/mips3drc.o $(CPUOBJ)~~/x86drc.o~~
	780	CPUOBJS += $(CPUOBJ)/mips/mips3drc.o $(DRCOBJ)
768	781	else
769	782	CPUOBJS += $(CPUOBJ)/mips/mips3.o
770	783	endif
r894	r895
778	791	$(CPUSRC)/mips/mdrcold.c \
779	792	$(CPUSRC)/mips/mips3.h \
780	793	$(CPUSRC)/mips/mips3com.h \
781		$(CPUSRC)/x86drc.c \
782		$(CPUSRC)/x86drc.h
	794	$(DRCDEPS)
783	795
784	796
785	797
r894	r895
1058	1070
1059	1071	ifneq ($(filter PPC403 PPC602 PPC603 MPC8240,$(CPUS)),)
1060	1072	OBJDIRS += $(CPUOBJ)/powerpc
	1073	DBGOBJS += $(CPUOBJ)/powerpc/ppc_dasm.o
	1074
1061	1075	ifdef X86_PPC_DRC
1062		CPUOBJS += $(CPUOBJ)/powerpc/ppcdrc.o $(CPUOBJ)~~/x86drc.o~~
	1076	CPUOBJS += $(CPUOBJ)/powerpc/ppcdrc.o $(DRCOBJ)
1063	1077	else
1064	1078	CPUOBJS += $(CPUOBJ)/powerpc/ppc.o
1065	1079	endif
1066		DBGOBJS += $(CPUOBJ)/powerpc/ppc_dasm.o
1067	1080	endif
1068	1081
1069	1082	$(CPUOBJ)/powerpc/ppc.o: $(CPUSRC)/powerpc/ppc.c \
r894	r895
1083	1096	$(CPUSRC)/powerpc/ppc403.c \
1084	1097	$(CPUSRC)/powerpc/ppc602.c \
1085	1098	$(CPUSRC)/powerpc/ppc603.c \
1086		$(CPUSRC)/x86drc.c \
1087		$(CPUSRC)/x86drc.h
	1099	$(DRCDEPS)
1088	1100
1089	1101
1090	1102

src/emu/cpu/i386/i386dasm.c
r894	r895
10	10	PARAM_REG = 1, /* 16 or 32-bit register */
11	11	PARAM_REG8, /* 8-bit register */
12	12	PARAM_REG16, /* 16-bit register */
	13	PARAM_REG32, /* 32-bit register */
	14	PARAM_REG3264, /* 32-bit or 64-bit register */
13	15	PARAM_REG2_32, /* 32-bit register */
14	16	PARAM_MMX, /* MMX register */
	17	PARAM_XMM, /* XMM register */
15	18	PARAM_RM, /* 16 or 32-bit memory or register */
16	19	PARAM_RM8, /* 8-bit memory or register */
17	20	PARAM_RM16, /* 16-bit memory or register */
	21	PARAM_RM32, /* 32-bit memory or register */
	22	PARAM_RMPTR, /* 16 or 32-bit memory or register */
	23	PARAM_RMPTR8, /* 8-bit memory or register */
	24	PARAM_RMPTR16, /* 16-bit memory or register */
	25	PARAM_RMPTR32, /* 32-bit memory or register */
	26	PARAM_RMXMM, /* 32 or 64-bit memory or register */
	27	PARAM_REGORXMM, /* 32 or 64-bit register or XMM register */
18	28	PARAM_M64, /* 64-bit memory */
	29	PARAM_M64PTR, /* 64-bit memory */
19	30	PARAM_MMXM, /* 64-bit memory or MMX register */
	31	PARAM_XMMM, /* 128-bit memory or XMM register */
20	32	PARAM_I4, /* 4-bit signed immediate */
21	33	PARAM_I8, /* 8-bit signed immediate */
22	34	PARAM_I16, /* 16-bit signed immediate */
23	35	PARAM_UI8, /* 8-bit unsigned immediate */
24	36	PARAM_UI16, /* 16-bit unsigned immediate */
25	37	PARAM_IMM, /* 16 or 32-bit immediate */
	38	PARAM_IMM64, /* 16, 32 or 64-bit immediate */
26	39	PARAM_ADDR, /* 16:16 or 16:32 address */
27	40	PARAM_REL, /* 16 or 32-bit PC-relative displacement */
28	41	PARAM_REL8, /* 8-bit PC-relative displacement */
r894	r895
52	65	PARAM_EDI, /* EDI or DI */
53	66	};
54	67
55		enum {
	68	enum
	69	{
56	70	MODRM = 1,
57	71	GROUP,
58	72	FPU,
59		VAR_NAME,
60	73	OP_SIZE,
61	74	ADDR_SIZE,
62	75	TWO_BYTE,
r894	r895
67	80	SEG_FS,
68	81	SEG_GS,
69	82	SEG_SS,
70		~~ALWAY~~S64
	83	ISREX
71	84	};
72	85
	86	#define FLAGS_MASK 0x0ff
	87	#define VAR_NAME 0x100
	88	#define VAR_NAME4 0x200
	89	#define ALWAYS64 0x400
	90	#define SPECIAL64 0x800
	91	#define SPECIAL64_ENT(x) (SPECIAL64 \| ((x) << 24))
	92
73	93	typedef struct {
74		char mnemonic~~[32]~~;
	94	const char *mnemonic;
75	95	UINT32 flags;
76	96	UINT32 param1;
77	97	UINT32 param2;
r894	r895
158	178	{"seg_ds", SEG_DS, 0, 0, 0 },
159	179	{"aas", 0, 0, 0, 0 },
160	180	// 0x40
161		{"inc", 0, PARAM_EAX, 0, 0 },
162		{"inc", 0, PARAM_ECX, 0, 0 },
163		{"inc", 0, PARAM_EDX, 0, 0 },
164		{"inc", 0, PARAM_EBX, 0, 0 },
165		{"inc", 0, PARAM_ESP, 0, 0 },
166		{"inc", 0, PARAM_EBP, 0, 0 },
167		{"inc", 0, PARAM_ESI, 0, 0 },
168		{"inc", 0, PARAM_EDI, 0, 0 },
169		{"dec", 0, PARAM_EAX, 0, 0 },
170		{"dec", 0, PARAM_ECX, 0, 0 },
171		{"dec", 0, PARAM_EDX, 0, 0 },
172		{"dec", 0, PARAM_EBX, 0, 0 },
173		{"dec", 0, PARAM_ESP, 0, 0 },
174		{"dec", 0, PARAM_EBP, 0, 0 },
175		{"dec", 0, PARAM_ESI, 0, 0 },
176		{"dec", 0, PARAM_EDI, 0, 0 },
	181	{"inc", ISREX, PARAM_EAX, 0, 0 },
	182	{"inc", ISREX, PARAM_ECX, 0, 0 },
	183	{"inc", ISREX, PARAM_EDX, 0, 0 },
	184	{"inc", ISREX, PARAM_EBX, 0, 0 },
	185	{"inc", ISREX, PARAM_ESP, 0, 0 },
	186	{"inc", ISREX, PARAM_EBP, 0, 0 },
	187	{"inc", ISREX, PARAM_ESI, 0, 0 },
	188	{"inc", ISREX, PARAM_EDI, 0, 0 },
	189	{"dec", ISREX, PARAM_EAX, 0, 0 },
	190	{"dec", ISREX, PARAM_ECX, 0, 0 },
	191	{"dec", ISREX, PARAM_EDX, 0, 0 },
	192	{"dec", ISREX, PARAM_EBX, 0, 0 },
	193	{"dec", ISREX, PARAM_ESP, 0, 0 },
	194	{"dec", ISREX, PARAM_EBP, 0, 0 },
	195	{"dec", ISREX, PARAM_ESI, 0, 0 },
	196	{"dec", ISREX, PARAM_EDI, 0, 0 },
177	197	// 0x50
178	198	{"push", ALWAYS64, PARAM_EAX, 0, 0 },
179	199	{"push", ALWAYS64, PARAM_ECX, 0, 0 },
r894	r895
192	212	{"pop", ALWAYS64, PARAM_ESI, 0, 0 },
193	213	{"pop", ALWAYS64, PARAM_EDI, 0, 0 },
194	214	// 0x60
195		{"pusha\0pushad", VAR_NAME, 0, 0, 0 },
196		{"popa\0popad", VAR_NAME, 0, 0, 0 },
	215	{"pusha\0pushad\0<invalid>",VAR_NAME,0, 0, 0 },
	216	{"popa\0popad\0<invalid>", VAR_NAME,0, 0, 0 },
197	217	{"bound", MODRM, PARAM_REG, PARAM_RM, 0 },
198		{"arpl", MODRM, PARAM_RM, PARAM_REG16, 0 },
	218	{"arpl", MODRM \| SPECIAL64_ENT(0),PARAM_RM, PARAM_REG16, 0 },
199	219	{"seg_fs", SEG_FS, 0, 0, 0 },
200	220	{"seg_gs", SEG_GS, 0, 0, 0 },
201	221	{"op_size", OP_SIZE, 0, 0, 0 },
r894	r895
205	225	{"push", 0, PARAM_I8, 0, 0 },
206	226	{"imul", MODRM, PARAM_REG, PARAM_RM, PARAM_I8 },
207	227	{"insb", 0, 0, 0, 0 },
208		{"insw\0insd", VAR_NAME, 0, 0, 0 },
	228	{"insw\0insd\0insd",VAR_NAME, 0, 0, 0 },
209	229	{"outsb", 0, 0, 0, 0 },
210		{"outsw\0outsd", VAR_NAME, 0, 0, 0 },
	230	{"outsw\0outsd\0outsd",VAR_NAME, 0, 0, 0 },
211	231	// 0x70
212	232	{"jo", 0, PARAM_REL8, 0, 0 },
213	233	{"jno", 0, PARAM_REL8, 0, 0 },
r894	r895
251	271	{"xchg", 0, PARAM_EAX, PARAM_EBP, 0 },
252	272	{"xchg", 0, PARAM_EAX, PARAM_ESI, 0 },
253	273	{"xchg", 0, PARAM_EAX, PARAM_EDI, 0 },
254		{"cbw\0cwde", VAR_NAME, 0, 0, 0 },
255		{"cwd\0cdq", VAR_NAME, 0, 0, 0 },
256		{"call", 0, PARAM_ADDR, 0, 0, DASMFLAG_STEP_OVER},
	274	{"cbw\0cwde\0cdqe", VAR_NAME, 0, 0, 0 },
	275	{"cwd\0cdq\0cqo", VAR_NAME, 0, 0, 0 },
	276	{"call", ALWAYS64, PARAM_ADDR, 0, 0, DASMFLAG_STEP_OVER},
257	277	{"wait", 0, 0, 0, 0 },
258		{"pushf\0pushfd", VAR_NAME, 0, 0, 0 },
259		{"popf\0popfd", VAR_NAME, 0, 0, 0 },
	278	{"pushf\0pushfd\0pushfq",VAR_NAME, 0, 0, 0 },
	279	{"popf\0popfd\0popfq",VAR_NAME, 0, 0, 0 },
260	280	{"sahf", 0, 0, 0, 0 },
261	281	{"lahf", 0, 0, 0, 0 },
262	282	// 0xa0
r894	r895
265	285	{"mov", 0, PARAM_MEM_OFFS_V, PARAM_AL, 0 },
266	286	{"mov", 0, PARAM_MEM_OFFS_V, PARAM_EAX, 0 },
267	287	{"movsb", 0, 0, 0, 0 },
268		{"movsw\0movsd", VAR_NAME, 0, 0, 0 },
	288	{"movsw\0movsd\0movsq",VAR_NAME, 0, 0, 0 },
269	289	{"cmpsb", 0, 0, 0, 0 },
270		{"cmpsw\0cmpsd", VAR_NAME, 0, 0, 0 },
	290	{"cmpsw\0cmpsd\0cmpsq",VAR_NAME, 0, 0, 0 },
271	291	{"test", 0, PARAM_AL, PARAM_UI8, 0 },
272	292	{"test", 0, PARAM_EAX, PARAM_IMM, 0 },
273	293	{"stosb", 0, 0, 0, 0 },
274		{"stosw\0stosd", VAR_NAME, 0, 0, 0 },
	294	{"stosw\0stosd\0stosq",VAR_NAME, 0, 0, 0 },
275	295	{"lodsb", 0, 0, 0, 0 },
276		{"lodsw\0lodsd", VAR_NAME, 0, 0, 0 },
	296	{"lodsw\0lodsd\0lodsq",VAR_NAME, 0, 0, 0 },
277	297	{"scasb", 0, 0, 0, 0 },
278		{"scasw\0scasd", VAR_NAME, 0, 0, 0 },
	298	{"scasw\0scasd\0scasq",VAR_NAME, 0, 0, 0 },
279	299	// 0xb0
280	300	{"mov", 0, PARAM_AL, PARAM_UI8, 0 },
281	301	{"mov", 0, PARAM_CL, PARAM_UI8, 0 },
r894	r895
285	305	{"mov", 0, PARAM_CH, PARAM_UI8, 0 },
286	306	{"mov", 0, PARAM_DH, PARAM_UI8, 0 },
287	307	{"mov", 0, PARAM_BH, PARAM_UI8, 0 },
288		{"mov", 0, PARAM_EAX, PARAM_IMM, 0 },
289		{"mov", 0, PARAM_ECX, PARAM_IMM, 0 },
290		{"mov", 0, PARAM_EDX, PARAM_IMM, 0 },
291		{"mov", 0, PARAM_EBX, PARAM_IMM, 0 },
292		{"mov", 0, PARAM_ESP, PARAM_IMM, 0 },
293		{"mov", 0, PARAM_EBP, PARAM_IMM, 0 },
294		{"mov", 0, PARAM_ESI, PARAM_IMM, 0 },
295		{"mov", 0, PARAM_EDI, PARAM_IMM, 0 },
	308	{"mov", 0, PARAM_EAX, PARAM_IMM64, 0 },
	309	{"mov", 0, PARAM_ECX, PARAM_IMM64, 0 },
	310	{"mov", 0, PARAM_EDX, PARAM_IMM64, 0 },
	311	{"mov", 0, PARAM_EBX, PARAM_IMM64, 0 },
	312	{"mov", 0, PARAM_ESP, PARAM_IMM64, 0 },
	313	{"mov", 0, PARAM_EBP, PARAM_IMM64, 0 },
	314	{"mov", 0, PARAM_ESI, PARAM_IMM64, 0 },
	315	{"mov", 0, PARAM_EDI, PARAM_IMM64, 0 },
296	316	// 0xc0
297	317	{"groupC0", GROUP, 0, 0, 0 },
298	318	{"groupC1", GROUP, 0, 0, 0 },
r894	r895
300	320	{"ret", 0, 0, 0, 0, DASMFLAG_STEP_OUT},
301	321	{"les", MODRM, PARAM_REG, PARAM_RM, 0 },
302	322	{"lds", MODRM, PARAM_REG, PARAM_RM, 0 },
303		{"mov", MODRM, PARAM_RM8, PARAM_UI8, 0 },
304		{"mov", MODRM, PARAM_RM, PARAM_IMM, 0 },
	323	{"mov", MODRM, PARAM_RMPTR8, PARAM_UI8, 0 },
	324	{"mov", MODRM, PARAM_RMPTR, PARAM_IMM, 0 },
305	325	{"enter", 0, PARAM_I16, PARAM_UI8, 0 },
306	326	{"leave", 0, 0, 0, 0 },
307	327	{"retf", 0, PARAM_I16, 0, 0, DASMFLAG_STEP_OUT},
r894	r895
331	351	{"loopne", 0, PARAM_REL8, 0, 0, DASMFLAG_STEP_OVER},
332	352	{"loopz", 0, PARAM_REL8, 0, 0, DASMFLAG_STEP_OVER},
333	353	{"loop", 0, PARAM_REL8, 0, 0, DASMFLAG_STEP_OVER},
334		{"jcxz\0jecxz", VAR_NAME, PARAM_REL8, 0, 0 },
	354	{"jcxz\0jecxz\0jrcxz",VAR_NAME, PARAM_REL8, 0, 0 },
335	355	{"in", 0, PARAM_AL, PARAM_UI8, 0 },
336	356	{"in", 0, PARAM_EAX, PARAM_UI8, 0 },
337	357	{"out", 0, PARAM_UI8, PARAM_AL, 0 },
r894	r895
363	383	{"groupFF", GROUP, 0, 0, 0 }
364	384	};
365	385
	386	static const I386_OPCODE x64_opcode_alt[] =
	387	{
	388	{"movsxd", MODRM \| ALWAYS64,PARAM_REG, PARAM_RMPTR32, 0 },
	389	};
	390
366	391	static const I386_OPCODE i386_opcode_table2[256] =
367	392	{
368	393	// 0x00
r894	r895
371	396	{"lar", MODRM, PARAM_REG, PARAM_RM, 0 },
372	397	{"lsl", MODRM, PARAM_REG, PARAM_RM, 0 },
373	398	{"???", 0, 0, 0, 0 },
374		{"~~???~~", 0, 0, 0, 0 },
	399	{"syscall", 0, 0, 0, 0 },
375	400	{"clts", 0, 0, 0, 0 },
376		{"~~???~~", 0, 0, 0, 0 },
	401	{"sysret", 0, 0, 0, 0 },
377	402	{"invd", 0, 0, 0, 0 },
378	403	{"wbinvd", 0, 0, 0, 0 },
379	404	{"???", 0, 0, 0, 0 },
r894	r895
383	408	{"???", 0, 0, 0, 0 },
384	409	{"???", 0, 0, 0, 0 },
385	410	// 0x10
386		{"???", 0, 0, 0, 0 },
387		{"???", 0, 0, 0, 0 },
388		{"???", 0, 0, 0, 0 },
389		{"???", 0, 0, 0, 0 },
390		{"???", 0, 0, 0, 0 },
391		{"???", 0, 0, 0, 0 },
392		{"???", 0, 0, 0, 0 },
393		{"???", 0, 0, 0, 0 },
	411	{"movups\0"
	412	"movupd\0"
	413	"movsd\0"
	414	"movss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	415	{"movups\0"
	416	"movupd\0"
	417	"movsd\0"
	418	"movss", MODRM\|VAR_NAME4,PARAM_XMMM, PARAM_XMM, 0 },
	419	{"movlps\0"
	420	"movlpd\0"
	421	"movddup\0"
	422	"movsldup", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	423	{"movlps\0"
	424	"movlpd\0"
	425	"???\0"
	426	"???", MODRM\|VAR_NAME4,PARAM_XMMM, PARAM_XMM, 0 },
	427	{"unpcklps\0"
	428	"unpcklpd\0"
	429	"???\0"
	430	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	431	{"unpckhps\0"
	432	"unpckhpd\0"
	433	"???\0"
	434	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	435	{"movhps\0"
	436	"movhpd\0"
	437	"???\0"
	438	"movshdup", MODRM\|VAR_NAME4,PARAM_XMMM, PARAM_XMM, 0 },
	439	{"movhps\0"
	440	"movhpd\0"
	441	"???\0"
	442	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
394	443	{"group0F18", GROUP, 0, 0, 0 },
395	444	{"???", 0, 0, 0, 0 },
396	445	{"???", 0, 0, 0, 0 },
r894	r895
408	457	{"???", 0, 0, 0, 0 },
409	458	{"mov", MODRM, PARAM_TREG, PARAM_REG2_32, 0 },
410	459	{"???", 0, 0, 0, 0 },
411		{"???", 0, 0, 0, 0 },
412		{"???", 0, 0, 0, 0 },
413		{"???", 0, 0, 0, 0 },
414		{"???", 0, 0, 0, 0 },
415		{"???", 0, 0, 0, 0 },
416		{"???", 0, 0, 0, 0 },
417		{"???", 0, 0, 0, 0 },
418		{"???", 0, 0, 0, 0 },
	460	{"movaps\0"
	461	"movapd\0"
	462	"???\0"
	463	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	464	{"movaps\0"
	465	"movapd\0"
	466	"???\0"
	467	"???", MODRM\|VAR_NAME4,PARAM_XMMM, PARAM_XMM, 0 },
	468	{"cvtpi2ps\0"
	469	"cvtpi2pd\0"
	470	"cvtsi2sd\0"
	471	"cvtsi2ss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_RMXMM, 0 },
	472	{"movntps\0"
	473	"movntpd\0"
	474	"???\0"
	475	"???", MODRM\|VAR_NAME4,PARAM_XMMM, PARAM_XMM, 0 },
	476	{"cvttps2pi\0"
	477	"cvttpd2pi\0"
	478	"cvttsd2si\0"
	479	"cvttss2si", MODRM\|VAR_NAME4,PARAM_REGORXMM, PARAM_XMMM, 0 },
	480	{"cvtps2pi\0"
	481	"cvtpd2pi\0"
	482	"cvtsd2si\0"
	483	"cvtss2si", MODRM\|VAR_NAME4,PARAM_REGORXMM, PARAM_XMMM, 0 },
	484	{"ucomiss\0"
	485	"ucomisd\0"
	486	"???\0"
	487	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	488	{"comiss\0"
	489	"comisd\0"
	490	"???\0"
	491	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
419	492	// 0x30
420	493	{"wrmsr", 0, 0, 0, 0 },
421		{"~~???~~", 0, 0, 0, 0 },
	494	{"rdtsc", 0, 0, 0, 0 },
422	495	{"rdmsr", 0, 0, 0, 0 },
	496	{"rdpmc", 0, 0, 0, 0 },
	497	{"sysenter", 0, 0, 0, 0 },
	498	{"sysexit", 0, 0, 0, 0 },
423	499	{"???", 0, 0, 0, 0 },
424	500	{"???", 0, 0, 0, 0 },
425	501	{"???", 0, 0, 0, 0 },
r894	r895
430	506	{"???", 0, 0, 0, 0 },
431	507	{"???", 0, 0, 0, 0 },
432	508	{"???", 0, 0, 0, 0 },
433		{"???", 0, 0, 0, 0 },
434		{"???", 0, 0, 0, 0 },
435		{"???", 0, 0, 0, 0 },
436	509	// 0x40
437		{"???", 0, 0, 0, 0 },
438		{"???", 0, 0, 0, 0 },
439		{"???", 0, 0, 0, 0 },
440		{"???", 0, 0, 0, 0 },
441		{"???", 0, 0, 0, 0 },
442		{"???", 0, 0, 0, 0 },
443		{"???", 0, 0, 0, 0 },
444		{"???", 0, 0, 0, 0 },
445		{"???", 0, 0, 0, 0 },
446		{"???", 0, 0, 0, 0 },
447		{"???", 0, 0, 0, 0 },
448		{"???", 0, 0, 0, 0 },
449		{"???", 0, 0, 0, 0 },
450		{"???", 0, 0, 0, 0 },
451		{"???", 0, 0, 0, 0 },
452		{"???", 0, 0, 0, 0 },
	510	{"cmovo", MODRM, PARAM_REG, PARAM_RM, 0 },
	511	{"cmovno", MODRM, PARAM_REG, PARAM_RM, 0 },
	512	{"cmovb", MODRM, PARAM_REG, PARAM_RM, 0 },
	513	{"cmovae", MODRM, PARAM_REG, PARAM_RM, 0 },
	514	{"cmove", MODRM, PARAM_REG, PARAM_RM, 0 },
	515	{"cmovne", MODRM, PARAM_REG, PARAM_RM, 0 },
	516	{"cmovbe", MODRM, PARAM_REG, PARAM_RM, 0 },
	517	{"cmova", MODRM, PARAM_REG, PARAM_RM, 0 },
	518	{"cmovs", MODRM, PARAM_REG, PARAM_RM, 0 },
	519	{"cmovns", MODRM, PARAM_REG, PARAM_RM, 0 },
	520	{"cmovpe", MODRM, PARAM_REG, PARAM_RM, 0 },
	521	{"cmovpo", MODRM, PARAM_REG, PARAM_RM, 0 },
	522	{"cmovl", MODRM, PARAM_REG, PARAM_RM, 0 },
	523	{"cmovge", MODRM, PARAM_REG, PARAM_RM, 0 },
	524	{"cmovle", MODRM, PARAM_REG, PARAM_RM, 0 },
	525	{"cmovg", MODRM, PARAM_REG, PARAM_RM, 0 },
453	526	// 0x50
454		{"???", 0, 0, 0, 0 },
455		{"???", 0, 0, 0, 0 },
456		{"???", 0, 0, 0, 0 },
457		{"???", 0, 0, 0, 0 },
458		{"???", 0, 0, 0, 0 },
459		{"???", 0, 0, 0, 0 },
460		{"???", 0, 0, 0, 0 },
461		{"???", 0, 0, 0, 0 },
462		{"???", 0, 0, 0, 0 },
463		{"???", 0, 0, 0, 0 },
464		{"???", 0, 0, 0, 0 },
465		{"???", 0, 0, 0, 0 },
466		{"???", 0, 0, 0, 0 },
467		{"???", 0, 0, 0, 0 },
468		{"???", 0, 0, 0, 0 },
469		{"???", 0, 0, 0, 0 },
	527	{"movmskps\0"
	528	"movmskpd\0"
	529	"???\0"
	530	"???", MODRM\|VAR_NAME4,PARAM_REG3264, PARAM_XMMM, 0 },
	531	{"sqrtps\0"
	532	"sqrtpd\0"
	533	"sqrtsd\0"
	534	"sqrtss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	535	{"rsqrtps\0"
	536	"???\0"
	537	"???\0"
	538	"rsqrtss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	539	{"rcpps\0"
	540	"???\0"
	541	"???\0"
	542	"rcpss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	543	{"andps\0"
	544	"andpd\0"
	545	"???\0"
	546	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	547	{"andnps\0"
	548	"andnpd\0"
	549	"???\0"
	550	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	551	{"orps\0"
	552	"orpd\0"
	553	"???\0"
	554	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	555	{"xorps\0"
	556	"xorpd\0"
	557	"???\0"
	558	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	559	{"addps\0"
	560	"addpd\0"
	561	"addsd\0"
	562	"addss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	563	{"mulps\0"
	564	"mulpd\0"
	565	"mulsd\0"
	566	"mulss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	567	{"cvtps2pd\0"
	568	"cvtpd2ps\0"
	569	"cvtsd2ss\0"
	570	"cvtss2sd", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	571	{"cvtdq2ps\0"
	572	"cvtps2dq\0"
	573	"???\0"
	574	"cvttps2dq", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	575	{"subps\0"
	576	"subpd\0"
	577	"subsd\0"
	578	"subss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	579	{"minps\0"
	580	"minpd\0"
	581	"minsd\0"
	582	"minss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	583	{"divps\0"
	584	"divpd\0"
	585	"divsd\0"
	586	"divss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	587	{"maxps\0"
	588	"maxpd\0"
	589	"maxsd\0"
	590	"maxss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
470	591	// 0x60
471	592	{"punpcklbw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
472	593	{"punpcklwd", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
r894	r895
480	601	{"punpckhwd", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
481	602	{"punpckhdq", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
482	603	{"packssdw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
483		{"???", 0, 0, 0, 0 },
484		{"???", 0, 0, 0, 0 },
	604	{"punpcklqdq", MODRM, PARAM_XMM, PARAM_XMMM, 0 },
	605	{"punpckhqdq", MODRM, PARAM_XMM, PARAM_XMMM, 0 },
485	606	{"movd", MODRM, PARAM_MMX, PARAM_RM, 0 },
486		{"movq", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
	607	{"movq\0"
	608	"movdqa\0"
	609	"???\0"
	610	"movdqu", MODRM\|VAR_NAME4,PARAM_MMX, PARAM_MMXM, 0 },
487	611	// 0x70
488		{"pshufw", MODRM, PARAM_MMX, PARAM_MMXM, PARAM_I8 },
489		{"???", 0, 0, 0, 0 },
	612	{"pshufw\0"
	613	"pshufd\0"
	614	"pshuflw\0"
	615	"pshufhw", MODRM\|VAR_NAME4,PARAM_MMX, PARAM_MMXM, PARAM_I8 },
	616	{"group0F71", GROUP, 0, 0, 0 },
490	617	{"group0F72", GROUP, 0, 0, 0 },
491		{"~~???~~", 0, 0, 0, 0 },
	618	{"group0F73", GROUP, 0, 0, 0 },
492	619	{"pcmpeqb", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
493	620	{"pcmpeqw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
494	621	{"pcmpeqd", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
495	622	{"emms", 0, 0, 0, 0 },
496	623	{"???", 0, 0, 0, 0 },
497	624	{"???", 0, 0, 0, 0 },
498		{"pcmpeqb", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
499		{"pcmpeqw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
500		{"pcmpeqd", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
501		{"emms", 0, 0, 0, 0 },
502		{"movd", MODRM, PARAM_RM, PARAM_MMX, 0 },
503		{"movq", MODRM, PARAM_MMXM, PARAM_MMX, 0 },
	625	{"???", 0, 0, 0, 0 },
	626	{"???", 0, 0, 0, 0 },
	627	{"???\0"
	628	"haddpd\0"
	629	"haddps\0"
	630	"???", MODRM\|VAR_NAME4,PARAM_MMX, PARAM_MMXM, 0 },
	631	{"???\0"
	632	"hsubpd\0"
	633	"hsubps\0"
	634	"???", MODRM\|VAR_NAME4,PARAM_MMX, PARAM_MMXM, 0 },
	635	{"movd\0"
	636	"movd\0"
	637	"???\0"
	638	"movq", MODRM\|VAR_NAME4,PARAM_RM, PARAM_MMX, 0 },
	639	{"movq\0"
	640	"movdqa\0"
	641	"???\0"
	642	"movdqu", MODRM\|VAR_NAME4,PARAM_MMXM, PARAM_MMX, 0 },
504	643	// 0x80
505	644	{"jo", 0, PARAM_REL, 0, 0 },
506	645	{"jno", 0, PARAM_REL, 0, 0 },
r894	r895
519	658	{"jle", 0, PARAM_REL, 0, 0 },
520	659	{"jg", 0, PARAM_REL, 0, 0 },
521	660	// 0x90
522		{"seto", MODRM, PARAM_RM8, 0, 0 },
523		{"setno", MODRM, PARAM_RM8, 0, 0 },
524		{"setb", MODRM, PARAM_RM8, 0, 0 },
525		{"setae", MODRM, PARAM_RM8, 0, 0 },
526		{"sete", MODRM, PARAM_RM8, 0, 0 },
527		{"setne", MODRM, PARAM_RM8, 0, 0 },
528		{"setbe", MODRM, PARAM_RM8, 0, 0 },
529		{"seta", MODRM, PARAM_RM8, 0, 0 },
530		{"sets", MODRM, PARAM_RM8, 0, 0 },
531		{"setns", MODRM, PARAM_RM8, 0, 0 },
532		{"setp", MODRM, PARAM_RM8, 0, 0 },
533		{"setnp", MODRM, PARAM_RM8, 0, 0 },
534		{"setl", MODRM, PARAM_RM8, 0, 0 },
535		{"setge", MODRM, PARAM_RM8, 0, 0 },
536		{"setle", MODRM, PARAM_RM8, 0, 0 },
537		{"setg", MODRM, PARAM_RM8, 0, 0 },
	661	{"seto", MODRM, PARAM_RMPTR8, 0, 0 },
	662	{"setno", MODRM, PARAM_RMPTR8, 0, 0 },
	663	{"setb", MODRM, PARAM_RMPTR8, 0, 0 },
	664	{"setae", MODRM, PARAM_RMPTR8, 0, 0 },
	665	{"sete", MODRM, PARAM_RMPTR8, 0, 0 },
	666	{"setne", MODRM, PARAM_RMPTR8, 0, 0 },
	667	{"setbe", MODRM, PARAM_RMPTR8, 0, 0 },
	668	{"seta", MODRM, PARAM_RMPTR8, 0, 0 },
	669	{"sets", MODRM, PARAM_RMPTR8, 0, 0 },
	670	{"setns", MODRM, PARAM_RMPTR8, 0, 0 },
	671	{"setp", MODRM, PARAM_RMPTR8, 0, 0 },
	672	{"setnp", MODRM, PARAM_RMPTR8, 0, 0 },
	673	{"setl", MODRM, PARAM_RMPTR8, 0, 0 },
	674	{"setge", MODRM, PARAM_RMPTR8, 0, 0 },
	675	{"setle", MODRM, PARAM_RMPTR8, 0, 0 },
	676	{"setg", MODRM, PARAM_RMPTR8, 0, 0 },
538	677	// 0xa0
539	678	{"push fs", 0, 0, 0, 0 },
540	679	{"pop fs", 0, 0, 0, 0 },
r894	r895
546	685	{"???", 0, 0, 0, 0 },
547	686	{"push gs", 0, 0, 0, 0 },
548	687	{"pop gs", 0, 0, 0, 0 },
549		{"~~???~~", 0, 0, 0, 0 },
	688	{"rsm", 0, 0, 0, 0 },
550	689	{"bts", MODRM, PARAM_RM, PARAM_REG, 0 },
551	690	{"shrd", MODRM, PARAM_RM, PARAM_REG, PARAM_I8 },
552	691	{"shrd", MODRM, PARAM_RM, PARAM_REG, PARAM_CL },
r894	r895
559	698	{"btr", MODRM, PARAM_RM, PARAM_REG, 0 },
560	699	{"lfs", MODRM, PARAM_REG, PARAM_RM, 0 },
561	700	{"lgs", MODRM, PARAM_REG, PARAM_RM, 0 },
562		{"movzx", MODRM, PARAM_REG, PARAM_RM8, 0 },
563		{"movzx", MODRM, PARAM_REG, PARAM_RM16, 0 },
	701	{"movzx", MODRM, PARAM_REG, PARAM_RMPTR8, 0 },
	702	{"movzx", MODRM, PARAM_REG, PARAM_RMPTR16, 0 },
564	703	{"???", 0, 0, 0, 0 },
565	704	{"???", 0, 0, 0, 0 },
566	705	{"group0FBA", GROUP, 0, 0, 0 },
567	706	{"btc", MODRM, PARAM_RM, PARAM_REG, 0 },
568	707	{"bsf", MODRM, PARAM_REG, PARAM_RM, 0 },
569	708	{"bsr", MODRM, PARAM_REG, PARAM_RM, 0, DASMFLAG_STEP_OVER},
570		{"movsx", MODRM, PARAM_REG, PARAM_RM8, 0 },
571		{"movsx", MODRM, PARAM_REG, PARAM_RM16, 0 },
	709	{"movsx", MODRM, PARAM_REG, PARAM_RMPTR8, 0 },
	710	{"movsx", MODRM, PARAM_REG, PARAM_RMPTR16, 0 },
572	711	// 0xc0
573	712	{"xadd", MODRM, PARAM_RM8, PARAM_REG, 0 },
574	713	{"xadd", MODRM, PARAM_RM, PARAM_REG, 0 },
575		{"???", 0, 0, 0, 0 },
	714	{"cmpps\0"
	715	"cmppd\0"
	716	"cmpsd\0"
	717	"cmpss", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
576	718	{"movnti", MODRM, PARAM_RM, PARAM_REG, 0 },
577		{"???", 0, 0, 0, 0 },
578		{"???", 0, 0, 0, 0 },
579		{"???", 0, 0, 0, 0 },
580		{"cmpxchg8b", MODRM, PARAM_M64, 0, 0 },
581		{"???", 0, 0, 0, 0 },
582		{"???", 0, 0, 0, 0 },
583		{"???", 0, 0, 0, 0 },
584		{"???", 0, 0, 0, 0 },
585		{"???", 0, 0, 0, 0 },
586		{"???", 0, 0, 0, 0 },
587		{"???", 0, 0, 0, 0 },
588		{"???", 0, 0, 0, 0 },
	719	{"pinsrw", MODRM, PARAM_MMX, PARAM_MMXM, PARAM_I8 },
	720	{"pextrw", MODRM, PARAM_MMX, PARAM_MMXM, PARAM_I8 },
	721	{"shufps\0"
	722	"shufpd\0"
	723	"???\0"
	724	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, PARAM_I8 },
	725	{"cmpxchg8b", MODRM, PARAM_M64PTR, 0, 0 },
	726	{"bswap", 0, PARAM_EAX, 0, 0 },
	727	{"bswap", 0, PARAM_ECX, 0, 0 },
	728	{"bswap", 0, PARAM_EDX, 0, 0 },
	729	{"bswap", 0, PARAM_EBX, 0, 0 },
	730	{"bswap", 0, PARAM_ESP, 0, 0 },
	731	{"bswap", 0, PARAM_EBP, 0, 0 },
	732	{"bswap", 0, PARAM_ESI, 0, 0 },
	733	{"bswap", 0, PARAM_EDI, 0, 0 },
589	734	// 0xd0
590		{"???", 0, 0, 0, 0 },
591		{"???", 0, 0, 0, 0 },
592		{"???", 0, 0, 0, 0 },
593		{"???", 0, 0, 0, 0 },
	735	{"addsubpd\0"
	736	"???\0"
	737	"addsubps\0"
	738	"???\0", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
	739	{"psrlw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
	740	{"psrld", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
	741	{"psrlq", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
594	742	{"paddq", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
595	743	{"pmullw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
596		{"???", 0, 0, 0, 0 },
597		{"???", 0, 0, 0, 0 },
	744	{"movq\0"
	745	"???\0"
	746	"movdq2q\0"
	747	"movq2dq", MODRM\|VAR_NAME4,PARAM_MMX, PARAM_MMXM, 0 },
	748	{"pmovmskb", MODRM, PARAM_REG3264, PARAM_MMXM, 0 },
598	749	{"psubusb", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
599	750	{"psubusw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
600	751	{"pminub", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
r894	r895
610	761	{"pavgw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
611	762	{"pmulhuw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
612	763	{"pmulhw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
613		{"???", 0, 0, 0, 0 },
	764	{"???\0"
	765	"cvttpd2dq\0"
	766	"cvtpd2dq\0"
	767	"cvtdq2pd", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
614	768	{"movntq", MODRM, PARAM_M64, PARAM_MMX, 0 },
615	769	{"psubsb", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
616	770	{"psubsw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
r894	r895
621	775	{"pmaxsw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
622	776	{"pxor", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
623	777	// 0xf0
624		{"???", 0, 0, 0, 0 },
	778	{"???\0"
	779	"???\0"
	780	"lddqu\0"
	781	"???", MODRM\|VAR_NAME4,PARAM_XMM, PARAM_XMMM, 0 },
625	782	{"psllw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
626	783	{"pslld", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
627	784	{"psllq", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
628	785	{"pmuludq", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
629	786	{"pmaddwd", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
630	787	{"psadbw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
631		{"???", 0, 0, 0, 0 },
	788	{"maskmovq\0"
	789	"maskmovdqu\0"
	790	"???\0"
	791	"???", MODRM\|VAR_NAME4,PARAM_MMX, PARAM_MMXM, 0 },
632	792	{"psubb", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
633	793	{"psubw", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
634	794	{"psubd", MODRM, PARAM_MMX, PARAM_MMXM, 0 },
r894	r895
641	801
642	802	static const I386_OPCODE group80_table[8] =
643	803	{
644		{"add", 0, PARAM_RM8, PARAM_I8, 0 },
645		{"or", 0, PARAM_RM8, PARAM_I8, 0 },
646		{"adc", 0, PARAM_RM8, PARAM_I8, 0 },
647		{"sbb", 0, PARAM_RM8, PARAM_I8, 0 },
648		{"and", 0, PARAM_RM8, PARAM_I8, 0 },
649		{"sub", 0, PARAM_RM8, PARAM_I8, 0 },
650		{"xor", 0, PARAM_RM8, PARAM_I8, 0 },
651		{"cmp", 0, PARAM_RM8, PARAM_I8, 0 }
	804	{"add", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	805	{"or", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	806	{"adc", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	807	{"sbb", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	808	{"and", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	809	{"sub", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	810	{"xor", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	811	{"cmp", 0, PARAM_RMPTR8, PARAM_I8, 0 }
652	812	};
653	813
654	814	static const I386_OPCODE group81_table[8] =
655	815	{
656		{"add", 0, PARAM_RM, PARAM_IMM, 0 },
657		{"or", 0, PARAM_RM, PARAM_IMM, 0 },
658		{"adc", 0, PARAM_RM, PARAM_IMM, 0 },
659		{"sbb", 0, PARAM_RM, PARAM_IMM, 0 },
660		{"and", 0, PARAM_RM, PARAM_IMM, 0 },
661		{"sub", 0, PARAM_RM, PARAM_IMM, 0 },
662		{"xor", 0, PARAM_RM, PARAM_IMM, 0 },
663		{"cmp", 0, PARAM_RM, PARAM_IMM, 0 }
	816	{"add", 0, PARAM_RMPTR, PARAM_IMM, 0 },
	817	{"or", 0, PARAM_RMPTR, PARAM_IMM, 0 },
	818	{"adc", 0, PARAM_RMPTR, PARAM_IMM, 0 },
	819	{"sbb", 0, PARAM_RMPTR, PARAM_IMM, 0 },
	820	{"and", 0, PARAM_RMPTR, PARAM_IMM, 0 },
	821	{"sub", 0, PARAM_RMPTR, PARAM_IMM, 0 },
	822	{"xor", 0, PARAM_RMPTR, PARAM_IMM, 0 },
	823	{"cmp", 0, PARAM_RMPTR, PARAM_IMM, 0 }
664	824	};
665	825
666	826	static const I386_OPCODE group83_table[8] =
667	827	{
668		{"add", 0, PARAM_RM, PARAM_I8, 0 },
669		{"or", 0, PARAM_RM, PARAM_I8, 0 },
670		{"adc", 0, PARAM_RM, PARAM_I8, 0 },
671		{"sbb", 0, PARAM_RM, PARAM_I8, 0 },
672		{"and", 0, PARAM_RM, PARAM_I8, 0 },
673		{"sub", 0, PARAM_RM, PARAM_I8, 0 },
674		{"xor", 0, PARAM_RM, PARAM_I8, 0 },
675		{"cmp", 0, PARAM_RM, PARAM_I8, 0 }
	828	{"add", 0, PARAM_RMPTR, PARAM_I8, 0 },
	829	{"or", 0, PARAM_RMPTR, PARAM_I8, 0 },
	830	{"adc", 0, PARAM_RMPTR, PARAM_I8, 0 },
	831	{"sbb", 0, PARAM_RMPTR, PARAM_I8, 0 },
	832	{"and", 0, PARAM_RMPTR, PARAM_I8, 0 },
	833	{"sub", 0, PARAM_RMPTR, PARAM_I8, 0 },
	834	{"xor", 0, PARAM_RMPTR, PARAM_I8, 0 },
	835	{"cmp", 0, PARAM_RMPTR, PARAM_I8, 0 }
676	836	};
677	837
678	838	static const I386_OPCODE groupC0_table[8] =
679	839	{
680		{"rol", 0, PARAM_RM8, PARAM_I8, 0 },
681		{"ror", 0, PARAM_RM8, PARAM_I8, 0 },
682		{"rcl", 0, PARAM_RM8, PARAM_I8, 0 },
683		{"rcr", 0, PARAM_RM8, PARAM_I8, 0 },
684		{"shl", 0, PARAM_RM8, PARAM_I8, 0 },
685		{"shr", 0, PARAM_RM8, PARAM_I8, 0 },
686		{"sal", 0, PARAM_RM8, PARAM_I8, 0 },
687		{"sar", 0, PARAM_RM8, PARAM_I8, 0 }
	840	{"rol", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	841	{"ror", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	842	{"rcl", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	843	{"rcr", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	844	{"shl", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	845	{"shr", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	846	{"sal", 0, PARAM_RMPTR8, PARAM_I8, 0 },
	847	{"sar", 0, PARAM_RMPTR8, PARAM_I8, 0 }
688	848	};
689	849
690	850	static const I386_OPCODE groupC1_table[8] =
691	851	{
692		{"rol", 0, PARAM_RM, PARAM_I8, 0 },
693		{"ror", 0, PARAM_RM, PARAM_I8, 0 },
694		{"rcl", 0, PARAM_RM, PARAM_I8, 0 },
695		{"rcr", 0, PARAM_RM, PARAM_I8, 0 },
696		{"shl", 0, PARAM_RM, PARAM_I8, 0 },
697		{"shr", 0, PARAM_RM, PARAM_I8, 0 },
698		{"sal", 0, PARAM_RM, PARAM_I8, 0 },
699		{"sar", 0, PARAM_RM, PARAM_I8, 0 }
	852	{"rol", 0, PARAM_RMPTR, PARAM_I8, 0 },
	853	{"ror", 0, PARAM_RMPTR, PARAM_I8, 0 },
	854	{"rcl", 0, PARAM_RMPTR, PARAM_I8, 0 },
	855	{"rcr", 0, PARAM_RMPTR, PARAM_I8, 0 },
	856	{"shl", 0, PARAM_RMPTR, PARAM_I8, 0 },
	857	{"shr", 0, PARAM_RMPTR, PARAM_I8, 0 },
	858	{"sal", 0, PARAM_RMPTR, PARAM_I8, 0 },
	859	{"sar", 0, PARAM_RMPTR, PARAM_I8, 0 }
700	860	};
701	861
702	862	static const I386_OPCODE groupD0_table[8] =
703	863	{
704		{"rol", 0, PARAM_RM8, PARAM_1, 0 },
705		{"ror", 0, PARAM_RM8, PARAM_1, 0 },
706		{"rcl", 0, PARAM_RM8, PARAM_1, 0 },
707		{"rcr", 0, PARAM_RM8, PARAM_1, 0 },
708		{"shl", 0, PARAM_RM8, PARAM_1, 0 },
709		{"shr", 0, PARAM_RM8, PARAM_1, 0 },
710		{"sal", 0, PARAM_RM8, PARAM_1, 0 },
711		{"sar", 0, PARAM_RM8, PARAM_1, 0 }
	864	{"rol", 0, PARAM_RMPTR8, PARAM_1, 0 },
	865	{"ror", 0, PARAM_RMPTR8, PARAM_1, 0 },
	866	{"rcl", 0, PARAM_RMPTR8, PARAM_1, 0 },
	867	{"rcr", 0, PARAM_RMPTR8, PARAM_1, 0 },
	868	{"shl", 0, PARAM_RMPTR8, PARAM_1, 0 },
	869	{"shr", 0, PARAM_RMPTR8, PARAM_1, 0 },
	870	{"sal", 0, PARAM_RMPTR8, PARAM_1, 0 },
	871	{"sar", 0, PARAM_RMPTR8, PARAM_1, 0 }
712	872	};
713	873
714	874	static const I386_OPCODE groupD1_table[8] =
715	875	{
716		{"rol", 0, PARAM_RM, PARAM_1, 0 },
717		{"ror", 0, PARAM_RM, PARAM_1, 0 },
718		{"rcl", 0, PARAM_RM, PARAM_1, 0 },
719		{"rcr", 0, PARAM_RM, PARAM_1, 0 },
720		{"shl", 0, PARAM_RM, PARAM_1, 0 },
721		{"shr", 0, PARAM_RM, PARAM_1, 0 },
722		{"sal", 0, PARAM_RM, PARAM_1, 0 },
723		{"sar", 0, PARAM_RM, PARAM_1, 0 }
	876	{"rol", 0, PARAM_RMPTR, PARAM_1, 0 },
	877	{"ror", 0, PARAM_RMPTR, PARAM_1, 0 },
	878	{"rcl", 0, PARAM_RMPTR, PARAM_1, 0 },
	879	{"rcr", 0, PARAM_RMPTR, PARAM_1, 0 },
	880	{"shl", 0, PARAM_RMPTR, PARAM_1, 0 },
	881	{"shr", 0, PARAM_RMPTR, PARAM_1, 0 },
	882	{"sal", 0, PARAM_RMPTR, PARAM_1, 0 },
	883	{"sar", 0, PARAM_RMPTR, PARAM_1, 0 }
724	884	};
725	885
726	886	static const I386_OPCODE groupD2_table[8] =
727	887	{
728		{"rol", 0, PARAM_RM8, PARAM_CL, 0 },
729		{"ror", 0, PARAM_RM8, PARAM_CL, 0 },
730		{"rcl", 0, PARAM_RM8, PARAM_CL, 0 },
731		{"rcr", 0, PARAM_RM8, PARAM_CL, 0 },
732		{"shl", 0, PARAM_RM8, PARAM_CL, 0 },
733		{"shr", 0, PARAM_RM8, PARAM_CL, 0 },
734		{"sal", 0, PARAM_RM8, PARAM_CL, 0 },
735		{"sar", 0, PARAM_RM8, PARAM_CL, 0 }
	888	{"rol", 0, PARAM_RMPTR8, PARAM_CL, 0 },
	889	{"ror", 0, PARAM_RMPTR8, PARAM_CL, 0 },
	890	{"rcl", 0, PARAM_RMPTR8, PARAM_CL, 0 },
	891	{"rcr", 0, PARAM_RMPTR8, PARAM_CL, 0 },
	892	{"shl", 0, PARAM_RMPTR8, PARAM_CL, 0 },
	893	{"shr", 0, PARAM_RMPTR8, PARAM_CL, 0 },
	894	{"sal", 0, PARAM_RMPTR8, PARAM_CL, 0 },
	895	{"sar", 0, PARAM_RMPTR8, PARAM_CL, 0 }
736	896	};
737	897
738	898	static const I386_OPCODE groupD3_table[8] =
739	899	{
740		{"rol", 0, PARAM_RM, PARAM_CL, 0 },
741		{"ror", 0, PARAM_RM, PARAM_CL, 0 },
742		{"rcl", 0, PARAM_RM, PARAM_CL, 0 },
743		{"rcr", 0, PARAM_RM, PARAM_CL, 0 },
744		{"shl", 0, PARAM_RM, PARAM_CL, 0 },
745		{"shr", 0, PARAM_RM, PARAM_CL, 0 },
746		{"sal", 0, PARAM_RM, PARAM_CL, 0 },
747		{"sar", 0, PARAM_RM, PARAM_CL, 0 }
	900	{"rol", 0, PARAM_RMPTR, PARAM_CL, 0 },
	901	{"ror", 0, PARAM_RMPTR, PARAM_CL, 0 },
	902	{"rcl", 0, PARAM_RMPTR, PARAM_CL, 0 },
	903	{"rcr", 0, PARAM_RMPTR, PARAM_CL, 0 },
	904	{"shl", 0, PARAM_RMPTR, PARAM_CL, 0 },
	905	{"shr", 0, PARAM_RMPTR, PARAM_CL, 0 },
	906	{"sal", 0, PARAM_RMPTR, PARAM_CL, 0 },
	907	{"sar", 0, PARAM_RMPTR, PARAM_CL, 0 }
748	908	};
749	909
750	910	static const I386_OPCODE groupF6_table[8] =
751	911	{
752		{"test", 0, PARAM_RM8, PARAM_I8, 0 },
	912	{"test", 0, PARAM_RMPTR8, PARAM_I8, 0 },
753	913	{"???", 0, 0, 0, 0 },
754		{"not", 0, PARAM_RM8, 0, 0 },
755		{"neg", 0, PARAM_RM8, 0, 0 },
756		{"mul", 0, PARAM_RM8, 0, 0 },
757		{"imul", 0, PARAM_RM8, 0, 0 },
758		{"div", 0, PARAM_RM8, 0, 0 },
759		{"idiv", 0, PARAM_RM8, 0, 0 }
	914	{"not", 0, PARAM_RMPTR8, 0, 0 },
	915	{"neg", 0, PARAM_RMPTR8, 0, 0 },
	916	{"mul", 0, PARAM_RMPTR8, 0, 0 },
	917	{"imul", 0, PARAM_RMPTR8, 0, 0 },
	918	{"div", 0, PARAM_RMPTR8, 0, 0 },
	919	{"idiv", 0, PARAM_RMPTR8, 0, 0 }
760	920	};
761	921
762	922	static const I386_OPCODE groupF7_table[8] =
763	923	{
764		{"test", 0, PARAM_RM, PARAM_IMM, 0 },
	924	{"test", 0, PARAM_RMPTR, PARAM_IMM, 0 },
765	925	{"???", 0, 0, 0, 0 },
766		{"not", 0, PARAM_RM, 0, 0 },
767		{"neg", 0, PARAM_RM, 0, 0 },
768		{"mul", 0, PARAM_RM, 0, 0 },
769		{"imul", 0, PARAM_RM, 0, 0 },
770		{"div", 0, PARAM_RM, 0, 0 },
771		{"idiv", 0, PARAM_RM, 0, 0 }
	926	{"not", 0, PARAM_RMPTR, 0, 0 },
	927	{"neg", 0, PARAM_RMPTR, 0, 0 },
	928	{"mul", 0, PARAM_RMPTR, 0, 0 },
	929	{"imul", 0, PARAM_RMPTR, 0, 0 },
	930	{"div", 0, PARAM_RMPTR, 0, 0 },
	931	{"idiv", 0, PARAM_RMPTR, 0, 0 }
772	932	};
773	933
774	934	static const I386_OPCODE groupFE_table[8] =
775	935	{
776		{"inc", 0, PARAM_RM8, 0, 0 },
777		{"dec", 0, PARAM_RM8, 0, 0 },
	936	{"inc", 0, PARAM_RMPTR8, 0, 0 },
	937	{"dec", 0, PARAM_RMPTR8, 0, 0 },
778	938	{"???", 0, 0, 0, 0 },
779	939	{"???", 0, 0, 0, 0 },
780	940	{"???", 0, 0, 0, 0 },
r894	r895
785	945
786	946	static const I386_OPCODE groupFF_table[8] =
787	947	{
788		{"inc", 0, PARAM_RM, 0, 0 },
789		{"dec", 0, PARAM_RM, 0, 0 },
790		{"call", 0, PARAM_RM, 0, 0, DASMFLAG_STEP_OVER},
	948	{"inc", 0, PARAM_RMPTR, 0, 0 },
	949	{"dec", 0, PARAM_RMPTR, 0, 0 },
	950	{"call", ALWAYS64, PARAM_RMPTR, 0, 0, DASMFLAG_STEP_OVER},
791	951	{"call far ptr ",0, PARAM_RM, 0, 0, DASMFLAG_STEP_OVER},
792		{"jmp", 0, PARAM_RM, 0, 0 },
	952	{"jmp", ALWAYS64, PARAM_RMPTR, 0, 0 },
793	953	{"jmp far ptr ",0, PARAM_RM, 0, 0 },
794		{"push", 0, PARAM_RM, 0, 0 },
	954	{"push", 0, PARAM_RMPTR, 0, 0 },
795	955	{"???", 0, 0, 0, 0 }
796	956	};
797	957
r894	r895
831	991	{"???", 0, 0, 0, 0 }
832	992	};
833	993
	994	static const I386_OPCODE group0F71_table[8] =
	995	{
	996	{"???", 0, 0, 0, 0 },
	997	{"???", 0, 0, 0, 0 },
	998	{"psrlw", 0, PARAM_MMX, PARAM_I8, 0 },
	999	{"???", 0, 0, 0, 0 },
	1000	{"psraw", 0, PARAM_MMX, PARAM_I8, 0 },
	1001	{"???", 0, 0, 0, 0 },
	1002	{"psllw", 0, PARAM_MMX, PARAM_I8, 0 },
	1003	{"???", 0, 0, 0, 0 }
	1004	};
	1005
834	1006	static const I386_OPCODE group0F72_table[8] =
835	1007	{
836	1008	{"???", 0, 0, 0, 0 },
837	1009	{"???", 0, 0, 0, 0 },
838	1010	{"psrld", 0, PARAM_MMX, PARAM_I8, 0 },
	1011	{"psrldq", 0, PARAM_MMX, PARAM_I8, 0 },
839	1012	{"???", 0, 0, 0, 0 },
840	1013	{"???", 0, 0, 0, 0 },
841		{"???", 0, 0, 0, 0 },
842	1014	{"pslld", 0, PARAM_MMX, PARAM_I8, 0 },
843		{"~~???~~", 0, 0, 0, 0 }
	1015	{"pslldq", 0, PARAM_MMX, PARAM_I8, 0 },
844	1016	};
845	1017
846		static const I386_OPCODE group0FAE_table[8] =
	1018	static const I386_OPCODE group0F73_table[8] =
847	1019	{
848	1020	{"???", 0, 0, 0, 0 },
849	1021	{"???", 0, 0, 0, 0 },
	1022	{"psrlq", 0, PARAM_MMX, PARAM_I8, 0 },
850	1023	{"???", 0, 0, 0, 0 },
	1024	{"psraq", 0, PARAM_MMX, PARAM_I8, 0 },
851	1025	{"???", 0, 0, 0, 0 },
	1026	{"psllq", 0, PARAM_MMX, PARAM_I8, 0 },
	1027	{"???", 0, 0, 0, 0 }
	1028	};
	1029
	1030	static const I386_OPCODE group0FAE_table[8] =
	1031	{
	1032	{"fxsave", 0, PARAM_RM, 0, 0 },
	1033	{"fxrstor", 0, PARAM_RM, 0, 0 },
	1034	{"ldmxcsr", 0, PARAM_RM, 0, 0 },
	1035	{"stmxscr", 0, PARAM_RM, 0, 0 },
852	1036	{"???", 0, 0, 0, 0 },
853		{"~~???~~", 0, 0, 0, 0 },
	1037	{"lfence", 0, 0, 0, 0 },
854	1038	{"mfence", 0, 0, 0, 0 },
855	1039	{"sfence", 0, 0, 0, 0 }
856	1040	};
r894	r895
886	1070	{ "group0F00", group0F00_table },
887	1071	{ "group0F01", group0F01_table },
888	1072	{ "group0F18", group0F18_table },
	1073	{ "group0F71", group0F71_table },
889	1074	{ "group0F72", group0F72_table },
	1075	{ "group0F73", group0F73_table },
890	1076	{ "group0FAE", group0FAE_table },
891	1077	{ "group0FBA", group0FBA_table }
892	1078	};
r894	r895
901	1087	};
902	1088
903	1089	static const char *i386_reg8[8] = {"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"};
904		//static const char *i386_reg8rex[16] = {"al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l"};
	1090	static const char *i386_reg8rex[16] = {"al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l"};
905	1091	static const char *i386_sreg[8] = {"es", "cs", "ss", "ds", "fs", "gs", "???", "???"};
906	1092
907	1093	static int address_size;
r894	r895
912	1098	static offs_t dasm_flags;
913	1099	static char modrm_string[256];
914	1100	static UINT8 rex, regex, sibex, rmex;
	1101	static UINT8 pre0f;
915	1102	static UINT8 curmode;
916	1103
917	1104	#define MODRM_REG1 ((modrm >> 3) & 0x7)
r894	r895
988	1175	return (buffer[1] >= '0' && buffer[1] <= '9') ? &buffer[1] : &buffer[0];
989	1176	}
990	1177
	1178	static char *hexstring64(UINT32 lo, UINT32 hi)
	1179	{
	1180	static char buffer[40];
	1181	buffer[0] = '0';
	1182	if (hi != 0)
	1183	sprintf(&buffer[1], "%X%08Xh", hi, lo);
	1184	else
	1185	sprintf(&buffer[1], "%Xh", lo);
	1186	return (buffer[1] >= '0' && buffer[1] <= '9') ? &buffer[1] : &buffer[0];
	1187	}
	1188
991	1189	static char *shexstring(UINT32 value, int digits, int always)
992	1190	{
993	1191	static char buffer[20];
r894	r895
1050	1248
1051	1249	s += sprintf( s, "[" );
1052	1250	if( address_size == 2 ) {
1053		if (rm == 4)
	1251	if ((rm & 7) == 4)
1054	1252	s = handle_sib_byte( s, mod );
1055	1253	else if (rm == 5 && mod == 0) {
1056	1254	disp32 = FETCHD32();
r894	r895
1059	1257	s += sprintf( s, "%s", i386_reg[2][rm]);
1060	1258	if( mod == 1 ) {
1061	1259	disp8 = FETCHD();
1062		s += sprintf( s, "%s", shexstring((INT32)disp8, 0, TRUE) );
	1260	if (disp8 != 0)
	1261	s += sprintf( s, "%s", shexstring((INT32)disp8, 0, TRUE) );
1063	1262	} else if( mod == 2 ) {
1064	1263	disp32 = FETCHD32();
1065		s += sprintf( s, "%s", shexstring(disp32, 0, TRUE) );
	1264	if (disp32 != 0)
	1265	s += sprintf( s, "%s", shexstring(disp32, 0, TRUE) );
1066	1266	}
1067	1267	} else if (address_size == 1) {
1068		if (rm == 4)
	1268	if ((rm & 7) == 4)
1069	1269	s = handle_sib_byte( s, mod );
1070	1270	else if (rm == 5 && mod == 0) {
1071	1271	disp32 = FETCHD32();
r894	r895
1077	1277	s += sprintf( s, "%s", i386_reg[1][rm]);
1078	1278	if( mod == 1 ) {
1079	1279	disp8 = FETCHD();
1080		s += sprintf( s, "%s", shexstring((INT32)disp8, 0, TRUE) );
	1280	if (disp8 != 0)
	1281	s += sprintf( s, "%s", shexstring((INT32)disp8, 0, TRUE) );
1081	1282	} else if( mod == 2 ) {
1082	1283	disp32 = FETCHD32();
1083		s += sprintf( s, "%s", shexstring(disp32, 0, TRUE) );
	1284	if (disp32 != 0)
	1285	s += sprintf( s, "%s", shexstring(disp32, 0, TRUE) );
1084	1286	}
1085	1287	} else {
1086	1288	switch( rm )
r894	r895
1103	1305	}
1104	1306	if( mod == 1 ) {
1105	1307	disp8 = FETCHD();
1106		s += sprintf( s, "%s", shexstring((INT32)disp8, 0, TRUE) );
	1308	if (disp8 != 0)
	1309	s += sprintf( s, "%s", shexstring((INT32)disp8, 0, TRUE) );
1107	1310	} else if( mod == 2 ) {
1108	1311	disp16 = FETCHD16();
1109		s += sprintf( s, "%s", shexstring((INT32)disp16, 0, TRUE) );
	1312	if (disp16 != 0)
	1313	s += sprintf( s, "%s", shexstring((INT32)disp16, 0, TRUE) );
1110	1314	}
1111	1315	}
1112	1316	s += sprintf( s, "]" );
r894	r895
1130	1334	break;
1131	1335
1132	1336	case PARAM_REG8:
1133		s += sprintf( s, "%s", i386_reg8[MODRM_REG1 \| regex] );
	1337	s += sprintf( s, "%s", (rex ? i386_reg8rex : i386_reg8)[MODRM_REG1 \| regex] );
1134	1338	break;
1135	1339
1136	1340	case PARAM_REG16:
1137	1341	s += sprintf( s, "%s", i386_reg[0][MODRM_REG1 \| regex] );
1138	1342	break;
1139	1343
	1344	case PARAM_REG32:
	1345	s += sprintf( s, "%s", i386_reg[1][MODRM_REG1 \| regex] );
	1346	break;
	1347
	1348	case PARAM_REG3264:
	1349	s += sprintf( s, "%s", i386_reg[(operand_size == 2) ? 2 : 1][MODRM_REG1 \| regex] );
	1350	break;
	1351
1140	1352	case PARAM_MMX:
1141		s += sprintf( s, "mm%d", MODRM_REG1 \| regex );
	1353	if (pre0f == 0x66 \|\| pre0f == 0xf2 \|\| pre0f == 0xf3)
	1354	s += sprintf( s, "xmm%d", MODRM_REG1 \| regex );
	1355	else
	1356	s += sprintf( s, "mm%d", MODRM_REG1 \| regex );
1142	1357	break;
1143	1358
	1359	case PARAM_XMM:
	1360	s += sprintf( s, "xmm%d", MODRM_REG1 \| regex );
	1361	break;
	1362
	1363	case PARAM_REGORXMM:
	1364	if (pre0f != 0xf2 && pre0f != 0xf3)
	1365	s += sprintf( s, "xmm%d", MODRM_REG1 \| regex );
	1366	else
	1367	s += sprintf( s, "%s", i386_reg[(operand_size == 2) ? 2 : 1][MODRM_REG1 \| regex] );
	1368	break;
	1369
1144	1370	case PARAM_REG2_32:
1145	1371	s += sprintf( s, "%s", i386_reg[1][MODRM_REG2 \| rmex] );
1146	1372	break;
1147	1373
1148	1374	case PARAM_RM:
	1375	case PARAM_RMPTR:
1149	1376	if( modrm >= 0xc0 ) {
1150	1377	s += sprintf( s, "%s", i386_reg[operand_size][MODRM_REG2 \| rmex] );
1151	1378	} else {
1152		if( operand_size )
1153		s += sprintf( s, "dword ptr " );
1154		else
1155		s += sprintf( s, "word ptr " );
	1379	if (param == PARAM_RMPTR)
	1380	{
	1381	if( operand_size == 2 )
	1382	s += sprintf( s, "qword ptr " );
	1383	else if (operand_size == 1)
	1384	s += sprintf( s, "dword ptr " );
	1385	else
	1386	s += sprintf( s, "word ptr " );
	1387	}
1156	1388	s += sprintf( s, "%s", modrm_string );
1157	1389	}
1158	1390	break;
1159	1391
1160	1392	case PARAM_RM8:
	1393	case PARAM_RMPTR8:
1161	1394	if( modrm >= 0xc0 ) {
1162		s += sprintf( s, "%s", i386_reg8[MODRM_REG2 \| rmex] );
	1395	s += sprintf( s, "%s", (rex ? i386_reg8rex : i386_reg8)[MODRM_REG2 \| rmex] );
1163	1396	} else {
1164		s += sprintf( s, "byte ptr " );
	1397	if (param == PARAM_RMPTR8)
	1398	s += sprintf( s, "byte ptr " );
1165	1399	s += sprintf( s, "%s", modrm_string );
1166	1400	}
1167	1401	break;
1168	1402
1169	1403	case PARAM_RM16:
	1404	case PARAM_RMPTR16:
1170	1405	if( modrm >= 0xc0 ) {
1171	1406	s += sprintf( s, "%s", i386_reg[0][MODRM_REG2 \| rmex] );
1172	1407	} else {
1173		s += sprintf( s, "word ptr " );
	1408	if (param == PARAM_RMPTR16)
	1409	s += sprintf( s, "word ptr " );
1174	1410	s += sprintf( s, "%s", modrm_string );
1175	1411	}
1176	1412	break;
1177	1413
	1414	case PARAM_RM32:
	1415	case PARAM_RMPTR32:
	1416	if( modrm >= 0xc0 ) {
	1417	s += sprintf( s, "%s", i386_reg[1][MODRM_REG2 \| rmex] );
	1418	} else {
	1419	if (param == PARAM_RMPTR32)
	1420	s += sprintf( s, "dword ptr " );
	1421	s += sprintf( s, "%s", modrm_string );
	1422	}
	1423	break;
	1424
	1425	case PARAM_RMXMM:
	1426	if( modrm >= 0xc0 ) {
	1427	if (pre0f != 0xf2 && pre0f != 0xf3)
	1428	s += sprintf( s, "xmm%d", MODRM_REG2 \| rmex );
	1429	else
	1430	s += sprintf( s, "%s", i386_reg[(operand_size == 2) ? 2 : 1][MODRM_REG2 \| rmex] );
	1431	} else {
	1432	if (param == PARAM_RMPTR32)
	1433	s += sprintf( s, "dword ptr " );
	1434	s += sprintf( s, "%s", modrm_string );
	1435	}
	1436	break;
	1437
1178	1438	case PARAM_M64:
	1439	case PARAM_M64PTR:
1179	1440	if( modrm >= 0xc0 ) {
1180	1441	s += sprintf( s, "???" );
1181	1442	} else {
1182		s += sprintf( s, "qword ptr " );
	1443	if (param == PARAM_M64PTR)
	1444	s += sprintf( s, "qword ptr " );
1183	1445	s += sprintf( s, "%s", modrm_string );
1184	1446	}
1185	1447	break;
1186	1448
1187	1449	case PARAM_MMXM:
1188	1450	if( modrm >= 0xc0 ) {
1189		s += sprintf( s, "mm%d", MODRM_REG2 \| rmex );
	1451	if (pre0f == 0x66 \|\| pre0f == 0xf2 \|\| pre0f == 0xf3)
	1452	s += sprintf( s, "xmm%d", MODRM_REG2 \| rmex );
	1453	else
	1454	s += sprintf( s, "mm%d", MODRM_REG2 \| rmex );
1190	1455	} else {
1191		s += sprintf( s, "~~qword ptr~~ %s", modrm_string );
	1456	s += sprintf( s, "%s", modrm_string );
1192	1457	}
1193	1458	break;
1194	1459
	1460	case PARAM_XMMM:
	1461	if( modrm >= 0xc0 ) {
	1462	s += sprintf( s, "xmm%d", MODRM_REG2 \| rmex );
	1463	} else {
	1464	s += sprintf( s, "%s", modrm_string );
	1465	}
	1466	break;
	1467
1195	1468	case PARAM_I4:
1196	1469	i8 = FETCHD();
1197	1470	s += sprintf( s, "%d", i8 & 0x0f );
r894	r895
1217	1490	s += sprintf( s, "%s", shexstring((UINT16)i16, 0, FALSE) );
1218	1491	break;
1219	1492
	1493	case PARAM_IMM64:
	1494	if (operand_size == 2) {
	1495	UINT32 lo32 = FETCHD32();
	1496	i32 = FETCHD32();
	1497	s += sprintf( s, "%s", hexstring64(lo32, i32) );
	1498	} else if( operand_size ) {
	1499	i32 = FETCHD32();
	1500	s += sprintf( s, "%s", hexstring(i32, 0) );
	1501	} else {
	1502	i16 = FETCHD16();
	1503	s += sprintf( s, "%s", hexstring(i16, 0) );
	1504	}
	1505	break;
	1506
1220	1507	case PARAM_IMM:
1221	1508	if( operand_size ) {
1222	1509	i32 = FETCHD32();
r894	r895
1693	1980	int i;
1694	1981	UINT8 op2;
1695	1982
1696		if (operand_size == 2 && op1 >= 0x40 && op1 < 0x50)
	1983	if (op->flags & SPECIAL64)
	1984	op = &x64_opcode_alt[op->flags >> 24];
	1985
	1986	switch( op->flags & FLAGS_MASK )
1697	1987	{
1698		rex = op1;
1699		operand_size = (op1 & 8) ? 2 : 1;
1700		regex = (op1 << 1) & 8;
1701		sibex = (op1 << 2) & 8;
1702		rmex = (op1 << 3) & 8;
1703		op2 = FETCH();
1704		decode_opcode( s, &i386_opcode_table1[op2], op1 );
1705		return;
1706		}
	1988	case ISREX:
	1989	if (curmode == 64)
	1990	{
	1991	rex = op1;
	1992	operand_size = (op1 & 8) ? 2 : 1;
	1993	regex = (op1 << 1) & 8;
	1994	sibex = (op1 << 2) & 8;
	1995	rmex = (op1 << 3) & 8;
	1996	op2 = FETCH();
	1997	decode_opcode( s, &i386_opcode_table1[op2], op1 );
	1998	return;
	1999	}
	2000	break;
1707	2001
1708		switch( op->flags )
1709		{
1710	2002	case OP_SIZE:
1711	2003	if (operand_size < 2)
1712	2004	operand_size ^= 1;
1713	2005	op2 = FETCH();
1714		decode_opcode( s, &i386_opcode_table1[op2], op1 );
	2006	decode_opcode( s, &i386_opcode_table1[op2], op2 );
1715	2007	return;
1716	2008
1717	2009	case ADDR_SIZE:
r894	r895
1720	2012	else
1721	2013	address_size ^= 3;
1722	2014	op2 = FETCH();
1723		decode_opcode( s, &i386_opcode_table1[op2], op1 );
	2015	decode_opcode( s, &i386_opcode_table1[op2], op2 );
1724	2016	return;
1725	2017
1726	2018	case TWO_BYTE:
	2019	if (&opcode_ptr[-2] >= opcode_ptr_base)
	2020	pre0f = opcode_ptr[-2];
1727	2021	op2 = FETCHD();
1728	2022	decode_opcode( s, &i386_opcode_table2[op2], op1 );
1729	2023	return;
r894	r895
1736	2030	case SEG_SS:
1737	2031	segment = op->flags;
1738	2032	op2 = FETCH();
1739		decode_opcode( s, &i386_opcode_table1[op2], op1 );
	2033	decode_opcode( s, &i386_opcode_table1[op2], op2 );
1740	2034	return;
1741	2035
1742	2036	case PREFIX:
1743		s += sprintf( s, "%-8s", op->mnemonic );
1744	2037	op2 = FETCH();
1745		decode_opcode( s, &i386_opcode_table1[op2], op1 );
	2038	if (op2 != 0x0f)
	2039	s += sprintf( s, "%-7s ", op->mnemonic );
	2040	decode_opcode( s, &i386_opcode_table1[op2], op2 );
1746	2041	return;
1747	2042
1748		case VAR_NAME:
1749		if( operand_size ) {
1750		int p=0;
1751		while(op->mnemonic[p] != 0)
1752		{
1753		p++;
1754		};
1755		s += sprintf( s, "%-8s", &op->mnemonic[p+1] );
1756		} else {
1757		s += sprintf( s, "%-8s", op->mnemonic );
1758		}
1759		goto handle_params;
1760
1761	2043	case GROUP:
1762	2044	handle_modrm( modrm_string );
1763	2045	for( i=0; i < ARRAY_LENGTH(group_op_table); i++ ) {
r894	r895
1776	2058	case MODRM:
1777	2059	handle_modrm( modrm_string );
1778	2060	break;
	2061	}
1779	2062
1780		case ALWAYS64:
1781		if (curmode == 64)
1782		operand_size = 2;
1783		break;
	2063	if ((op->flags & ALWAYS64) && curmode == 64)
	2064	operand_size = 2;
	2065
	2066	if ((op->flags & VAR_NAME) && operand_size > 0)
	2067	{
	2068	const char *mnemonic = op->mnemonic + strlen(op->mnemonic) + 1;
	2069	if (operand_size == 2)
	2070	mnemonic += strlen(mnemonic) + 1;
	2071	s += sprintf( s, "%-7s ", mnemonic );
1784	2072	}
1785
1786		s += sprintf( s, "%-8s", op->mnemonic );
	2073	else if (op->flags & VAR_NAME4)
	2074	{
	2075	const char *mnemonic = op->mnemonic;
	2076	int which = (pre0f == 0xf3) ? 3 : (pre0f == 0xf2) ? 2 : (pre0f == 0x66) ? 1 : 0;
	2077	while (which--)
	2078	mnemonic += strlen(mnemonic) + 1;
	2079	s += sprintf( s, "%-7s ", mnemonic );
	2080	}
	2081	else
	2082	s += sprintf( s, "%-7s ", op->mnemonic );
1787	2083	dasm_flags = op->dasm_flags;
1788	2084
1789		handle_params:
1790	2085	if( op->param1 != 0 ) {
1791	2086	s = handle_param( s, op->param1 );
1792	2087	}
r894	r895
1817	2112	dasm_flags = 0;
1818	2113	segment = 0;
1819	2114	curmode = mode;
	2115	pre0f = 0;
1820	2116	rex = regex = sibex = rmex = 0;
1821	2117
1822	2118	op = FETCH();

src/emu/cpu/x86drc.c
r894	r895
13	13	#include "x86drc.h"
14	14	#include "debugger.h"
15	15
16		#define LOG_DISPATCHES 0
	16	#define LOG_DISPATCHES 0
	17	#define BREAK_ON_MODIFIED_CODE 0
17	18
18	19
19	20
r894	r895
34	35	#endif
35	36
36	37
	38
37	39	/***************************************************************************
38	40	EXTERNAL INTERFACES
39	41	***************************************************************************/
40	42
41		/*------------------------------------------------------------------
42		drc_init
43		------------------------------------------------------------------*/
	43	/*-------------------------------------------------
	44	drc_init - initialize the DRC core
	45	-------------------------------------------------*/
44	46
45	47	drc_core drc_init(UINT8 cpunum, drc_config config)
46	48	{
47	49	int address_bits = config->address_bits;
48	50	int effective_address_bits = address_bits - config->lsbs_to_ignore;
49		drc_core *drc;
	51	UINT8 cache_allocated = FALSE;
	52	drc_core *drc = NULL;
50	53
51	54	/* allocate memory */
52		drc = malloc(sizeof(*drc));
53		if (!drc)
54		return NULL;
	55	if (config->cache_base == NULL)
	56	{
	57	config->cache_base = osd_alloc_executable(config->cache_size);
	58	if (config->cache_base == NULL)
	59	goto error;
	60	cache_allocated = TRUE;
	61	}
	62
	63	/* the drc structure lives at the start of the cache */
	64	drc = (drc_core *)config->cache_base;
55	65	memset(drc, 0, sizeof(*drc));
56	66
57	67	/* copy in relevant data from the config */
r894	r895
68	78	drc->fpcw_curr = fp_control[0];
69	79	drc->mxcsr_curr = sse_control[0];
70	80
71		/* allocate cache */
72		drc->cache_size = config->cache_size;
73		drc->cache_base = osd_alloc_executable(drc->cache_size);
74		if (!drc->cache_base)
75		return NULL;
	81	/* configure cache */
	82	drc->cache_base = (UINT8 )config->cache_base + sizeof(drc);
	83	drc->cache_size = config->cache_size - sizeof(*drc);
76	84	drc->cache_end = drc->cache_base + drc->cache_size;
77	85	drc->cache_danger = drc->cache_end - 65536;
	86	drc->cache_allocated = drc->cache_allocated;
78	87
79	88	/* compute shifts and masks */
80	89	drc->l1bits = effective_address_bits/2;
r894	r895
86	95	/* allocate lookup tables */
87	96	drc->lookup_l1 = malloc(sizeof(drc->lookup_l1) (1 << drc->l1bits));
88	97	drc->lookup_l2_recompile = malloc(sizeof(drc->lookup_l2_recompile) (1 << drc->l2bits));
89		if (!drc->lookup_l1 \|\| !drc->lookup_l2_recompile)
90		return NULL;
	98	if (drc->lookup_l1 == NULL \|\| drc->lookup_l2_recompile == NULL)
	99	goto error;
91	100	memset(drc->lookup_l1, 0, sizeof(drc->lookup_l1) (1 << drc->l1bits));
92	101	memset(drc->lookup_l2_recompile, 0, sizeof(drc->lookup_l2_recompile) (1 << drc->l2bits));
93	102
94	103	/* allocate the sequence and tentative lists */
95	104	drc->sequence_count_max = config->max_instructions;
96	105	drc->sequence_list = malloc(drc->sequence_count_max * sizeof(*drc->sequence_list));
97		if (!drc->sequence_list)
	106	if (drc->sequence_list == NULL)
	107	goto error;
	108
	109	drc->tentative_count_max = config->max_instructions;
	110	drc->tentative_list = malloc(drc->tentative_count_max * sizeof(*drc->tentative_list));
	111	if (!drc->tentative_list)
98	112	return NULL;
99		drc->tentative_count_max = config->max_instructions;
100		if (drc->tentative_count_max)
101		{
102		drc->tentative_list = malloc(drc->tentative_count_max * sizeof(*drc->tentative_list));
103		if (!drc->tentative_list)
104		return NULL;
105		}
106	113
107	114	/* seed the cache */
108		drc_cache_reset(drc);
	115	// drc_cache_reset(drc);
109	116	return drc;
	117
	118	error:
	119	if (drc != NULL)
	120	drc_exit(drc);
	121	return NULL;
110	122	}
111	123
112	124
113		/*------------------------------------------------------------------
114		drc_cache_reset
115		------------------------------------------------------------------*/
	125	/*-------------------------------------------------
	126	drc_alloc - allocate memory from the top of
	127	the DRC cache
	128	-------------------------------------------------*/
116	129
	130	void drc_alloc(drc_core drc, size_t amount)
	131	{
	132	/* if we don't have enough space, reset the cache */
	133	if (drc->cache_top >= drc->cache_danger - amount)
	134	drc_cache_reset(drc);
	135
	136	/* if we still don't have enough space, fail */
	137	if (drc->cache_top >= drc->cache_danger - amount)
	138	return NULL;
	139
	140	/* adjust the end and danger values downward */
	141	drc->cache_end -= amount;
	142	drc->cache_danger -= amount;
	143	return drc->cache_end;
	144	}
	145
	146
	147	/*-------------------------------------------------
	148	drc_cache_reset - reset the DRC cache
	149	-------------------------------------------------*/
	150
117	151	void drc_cache_reset(drc_core *drc)
118	152	{
119	153	int i;
r894	r895
126	160	append_entry_point(drc);
127	161	drc->out_of_cycles = drc->cache_top;
128	162	append_out_of_cycles(drc);
	163
	164	/* append an INT 3 before the recompile so that BREAK_ON_MODIFIED_CODE works */
	165	_int(3);
129	166	drc->recompile = drc->cache_top;
130	167	append_recompile(drc);
131	168	drc->dispatch = drc->cache_top;
r894	r895
173	210	{
174	211	int i;
175	212
176		/* free the cache */
177		if (drc->cache_base)
178		osd_free_executable(drc->cache_base, drc->cache_size);
179
180	213	/* free all the l2 tables allocated */
181	214	for (i = 0; i < (1 << drc->l1bits); i++)
182	215	if (drc->lookup_l1[i] != drc->lookup_l2_recompile)
r894	r895
197	230	free(drc->tentative_list);
198	231
199	232	/* and the drc itself */
200		free(drc);
	233	if (drc->cache_allocated)
	234	osd_free_executable(drc, drc->cache_size + sizeof(*drc));
201	235	}
202	236
203	237
r894	r895
291	325
292	326	void drc_append_verify_code(drc_core drc, void code, UINT8 length)
293	327	{
	328	#if BREAK_ON_MODIFIED_CODE
	329	void recompile = (UINT8 )drc->recompile - 1;
	330	#else
	331	void *recompile = drc->recompile;
	332	#endif
	333
294	334	if (length > 8)
295	335	{
296	336	UINT32 *codeptr = code, sum = 0;
r894	r895
313	353	_lea_r32_m32bd(REG_EBX, REG_EBX, 4); // lea ebx,[ebx+4]
314	354	_jcc(COND_NZ, target); // jnz target
315	355	_cmp_r32_imm(REG_EAX, sum); // cmp eax,sum
316		_jcc(COND_NE, dr~~c->r~~ecompile); // jne recompile
	356	_jcc(COND_NE, recompile); // jne recompile
317	357	}
318	358	else if (length >= 12)
319	359	{
320	360	_cmp_m32abs_imm(code, (UINT32 )code); // cmp [pc],opcode
321		_jcc(COND_NE, dr~~c->r~~ecompile); // jne recompile
	361	_jcc(COND_NE, recompile); // jne recompile
322	362	_cmp_m32abs_imm((UINT8 )code + 4, ((UINT32 )code)[1]); // cmp [pc+4],opcode+4
323		_jcc(COND_NE, dr~~c->r~~ecompile); // jne recompile
	363	_jcc(COND_NE, recompile); // jne recompile
324	364	_cmp_m32abs_imm((UINT8 )code + 8, ((UINT32 )code)[2]); // cmp [pc+8],opcode+8
325		_jcc(COND_NE, dr~~c->r~~ecompile); // jne recompile
	365	_jcc(COND_NE, recompile); // jne recompile
326	366	}
327	367	else if (length >= 8)
328	368	{
329	369	_cmp_m32abs_imm(code, (UINT32 )code); // cmp [pc],opcode
330		_jcc(COND_NE, dr~~c->r~~ecompile); // jne recompile
	370	_jcc(COND_NE, recompile); // jne recompile
331	371	_cmp_m32abs_imm((UINT8 )code + 4, ((UINT32 )code)[1]); // cmp [pc+4],opcode+4
332		_jcc(COND_NE, dr~~c->r~~ecompile); // jne recompile
	372	_jcc(COND_NE, recompile); // jne recompile
333	373	}
334	374	else if (length >= 4)
335	375	{
336	376	_cmp_m32abs_imm(code, (UINT32 )code); // cmp [pc],opcode
337		_jcc(COND_NE, dr~~c->r~~ecompile); // jne recompile
	377	_jcc(COND_NE, recompile); // jne recompile
338	378	}
339	379	else if (length >= 2)
340	380	{
341	381	_cmp_m16abs_imm(code, (UINT16 )code); // cmp [pc],opcode
342		_jcc(COND_NE, dr~~c->r~~ecompile); // jne recompile
	382	_jcc(COND_NE, recompile); // jne recompile
343	383	}
344	384	else
345	385	{
346	386	_cmp_m8abs_imm(code, (UINT8 )code); // cmp [pc],opcode
347		_jcc(COND_NE, dr~~c->r~~ecompile); // jne recompile
	387	_jcc(COND_NE, recompile); // jne recompile
348	388	}
349	389	}
350	390

src/emu/cpu/x86drc.h
r894	r895
37	37	UINT8 * cache_danger; /* high water mark for the end */
38	38	UINT8 * cache_end; /* end of cache memory */
39	39	size_t cache_size; /* cache allocated size */
	40	UINT8 cache_allocated; /* did the DRC core allocate the cache? */
40	41
41	42	void *** lookup_l1; /* level 1 lookup */
42	43	void ** lookup_l2_recompile; /* level 2 lookup populated with recompile pointers */
r894	r895
81	82	/* configuration structure for the drc common code */
82	83	struct _drc_config
83	84	{
	85	UINT8 * cache_base; /* base pointer to the compiler cache */
84	86	UINT32 cache_size; /* size of cache to allocate */
85	87	UINT32 max_instructions; /* maximum instructions per sequence */
86	88	UINT8 address_bits; /* number of live address bits in the PC */
r894	r895
293	295	{ \
294	296	OP1(0x04 \| (((reg) & 7) << 3)); \
295	297	OP1((scale_lookup[scale] << 6) \| (((indx) & 7) << 3) \| ((base) & 7));\
296		if ((UINT32)(disp) != 0) OP4(disp); \
	298	if ((UINT32)(disp) != 0 \|\| (base) == NO_BASE) OP4(disp);\
297	299	} \
298	300	else if ((INT8)(INT32)(disp) == (INT32)(disp)) \
299	301	{ \
r894	r895
1936	1938
1937	1939	/* init/shutdown */
1938	1940	drc_core drc_init(UINT8 cpunum, drc_config config);
	1941	void drc_alloc(drc_core drc, size_t amount);
1939	1942	void drc_cache_reset(drc_core *drc);
1940	1943	void drc_execute(drc_core *drc);
1941	1944	void drc_exit(drc_core *drc);

src/emu/cpu/mips/mips3com.h
r894	r895
6	6
7	7	***************************************************************************/
8	8
	9	#ifndef __MIPS3COM_H__
	10	#define __MIPS3COM_H__
	11
9	12	#include "cpuintrf.h"
10	13	#include "mips3.h"
11	14
r894	r895
141	144	UINT8 (*readbyte)(offs_t);
142	145	UINT16 (*readword)(offs_t);
143	146	UINT32 (*readlong)(offs_t);
	147	UINT32 (*readlong_masked)(offs_t, UINT32);
144	148	UINT64 (*readdouble)(offs_t);
	149	UINT64 (*readdouble_masked)(offs_t, UINT64);
145	150	void (*writebyte)(offs_t, UINT8);
146	151	void (*writeword)(offs_t, UINT16);
147	152	void (*writelong)(offs_t, UINT32);
	153	void (*writelong_masked)(offs_t, UINT32, UINT32);
148	154	void (*writedouble)(offs_t, UINT64);
	155	void (*writedouble_masked)(offs_t, UINT64, UINT64);
149	156	};
150	157
151	158
r894	r895
168	175	UINT64 hi;
169	176	UINT64 lo;
170	177	UINT64 r[32];
	178	int icount;
171	179
172	180	/* COP registers */
173	181	UINT64 cpr[3][32];
r894	r895
200	208
201	209
202	210	/***************************************************************************
203		GLOBAL VARIABLES
204		***************************************************************************/
205
206		extern int mips3_icount;
207
208
209
210		/***************************************************************************
211	211	FUNCTION PROTOTYPES
212	212	***************************************************************************/
213	213
r894	r895
248	248	else
249	249	mips->cpr[0][COP0_Cause] &= ~(0x400 << irqline);
250	250	}
	251
	252	#endif

src/emu/cpu/mips/mips3dsm.c
r894	r895
185	185	case 0x01: sprintf(buffer, "sub.%s %s,%s,%s", fmt, cpreg[1][fd], cpreg[1][fs], cpreg[1][ft]); break;
186	186	case 0x02: sprintf(buffer, "mul.%s %s,%s,%s", fmt, cpreg[1][fd], cpreg[1][fs], cpreg[1][ft]); break;
187	187	case 0x03: sprintf(buffer, "div.%s %s,%s,%s", fmt, cpreg[1][fd], cpreg[1][fs], cpreg[1][ft]); break;
188		case 0x04: sprintf(buffer, "sqrt.%s %s,%s~~,%s~~", fmt, cpreg[1][fd], cpreg[1][fs]~~, cpreg[1][ft]~~); break;
	188	case 0x04: sprintf(buffer, "sqrt.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
189	189	case 0x05: sprintf(buffer, "abs.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
190	190	case 0x06: sprintf(buffer, "mov.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
191	191	case 0x07: sprintf(buffer, "neg.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;

src/emu/cpu/mips/mips3.h
r894	r895
6	6
7	7	***************************************************************************/
8	8
9		#ifndef _MIPS3_H
10		#define _MIPS3_H
	9	#ifndef __MIPS3_H__
	10	#define __MIPS3_H__
11	11
12	12	#include "cpuintrf.h"
13	13
r894	r895
196	196
197	197
198	198
199		#endif /* _MIPS3_H */
	199	#endif /* __MIPS3_H__ */

src/emu/cpu/mips/mdrcold.c
r894	r895
1		#include "cpu/x86drc.h"
2	1
3	2
4	3	/***************************************************************************
r894	r895
7	6
8	7	#define STRIP_NOPS 1 /* 1 is faster */
9	8	#define USE_SSE 0 /* can't tell any speed difference here */
10		#define CACHE_SIZE (16 * 1024 * 1024)
11	9
12	10
13	11
r894	r895
25	23	#define RECOMPILE_CHECK_SW_INTERRUPTS 0x0010
26	24	#define RECOMPILE_ADD_DISPATCH 0x0020
27	25
	26	/* append_readwrite flags */
	27	#define ARW_READ 0x0000
	28	#define ARW_WRITE 0x0001
	29	#define ARW_UNSIGNED 0x0000
	30	#define ARW_SIGNED 0x0002
	31	#define ARW_MASKED 0x0004
28	32
29	33
	34
30	35	/***************************************************************************
31	36	TYPEDEFS
32	37	***************************************************************************/
33	38
34	39	struct _mips3drc_data
35	40	{
36		drc_core * core;
37
38	41	void * generate_interrupt_exception;
39	42	void * generate_cop_exception;
40	43	void * generate_overflow_exception;
r894	r895
50	53	void * read_and_translate_word_signed;
51	54	void * read_and_translate_word_unsigned;
52	55	void * read_and_translate_long;
	56	void * read_and_translate_long_masked;
53	57	void * read_and_translate_double;
	58	void * read_and_translate_double_masked;
54	59	void * write_and_translate_byte;
55	60	void * write_and_translate_word;
56	61	void * write_and_translate_long;
	62	void * write_and_translate_long_masked;
57	63	void * write_and_translate_double;
58		void * write_back_long;
59		void * write_back_double;
	64	void * write_and_translate_double_masked;
60	65	};
61	66
62	67
r894	r895
72	77	static UINT32 compile_one(drc_core *drc, UINT32 pc, UINT32 physpc);
73	78
74	79	static void append_generate_exception(drc_core *drc, UINT8 exception);
75		static void append_readwrite_and_translate(drc_core *drc, int is~~_wr~~i~~te, int si~~ze, ~~int~~ ~~is_signed, int do_trans~~late);
	80	static void append_readwrite_and_translate(drc_core *drc, int size, UINT8 flags);
76	81	static void append_tlb_verify(drc_core drc, UINT32 pc, void target);
77	82	static void append_update_cycle_counting(drc_core *drc);
78	83	static void append_check_interrupts(drc_core *drc, int inline_generate);
r894	r895
113	118	{
114	119	drc_config drconfig;
115	120
116		/* allocate our data */
117		mips3.drc = auto_malloc(sizeof(*mips3.drc));
118		memset(mips3.drc, 0, sizeof(*mips3.drc));
119
120	121	/* fill in the config */
121	122	memset(&drconfig, 0, sizeof(drconfig));
	123	drconfig.cache_base = mips3.cache;
122	124	drconfig.cache_size = CACHE_SIZE;
123	125	drconfig.max_instructions = MAX_INSTRUCTIONS;
124	126	drconfig.address_bits = 32;
r894	r895
127	129	drconfig.uses_sse = USE_SSE;
128	130	drconfig.pc_in_memory = 0;
129	131	drconfig.icount_in_memory = 0;
130		drconfig.pcptr = (UINT32 *)&mips3.core.pc;
131		drconfig.icountptr = (UINT32 *)&mips3_icount;
	132	drconfig.pcptr = (UINT32 *)&mips3.core->pc;
	133	drconfig.icountptr = (UINT32 *)&mips3.core->icount;
132	134	drconfig.esiptr = NULL;
133	135	drconfig.cb_reset = drc_reset_callback;
134	136	drconfig.cb_recompile = drc_recompile_callback;
135	137	drconfig.cb_entrygen = drc_entrygen_callback;
136	138
137	139	/* initialize the compiler */
138		mips3.drc~~->core~~ = drc_init(cpu_getactivecpu(), &drconfig);
	140	mips3.drc = drc_init(cpu_getactivecpu(), &drconfig);
139	141	mips3.drcoptions = MIPS3DRC_FASTEST_OPTIONS;
140		}
141	142
142
143		/*-------------------------------------------------
144		mips3drc_reset - reset the drc-specific state
145		-------------------------------------------------*/
146
147		static void mips3drc_reset(void)
148		{
149		/* reset the cache */
150		drc_cache_reset(mips3.drc->core);
	143	/* allocate our data out of the cache */
	144	mips3.drcdata = drc_alloc(mips3.drc, sizeof(*mips3.drcdata));
	145	memset(mips3.drcdata, 0, sizeof(*mips3.drcdata));
151	146	}
152	147
153	148
154	149	/*-------------------------------------------------
155		mips3drc_execute - execute the code
156		-------------------------------------------------*/
157
158		static void mips3drc_execute(void)
159		{
160		drc_execute(mips3.drc->core);
161		}
162
163
164		/*-------------------------------------------------
165	150	mips3drc_exit - clean up the drc-specific
166	151	state
167	152	-------------------------------------------------*/
168	153
169	154	static void mips3drc_exit(void)
170	155	{
171		drc_exit(mips3.drc->core);
172	156	}
173	157
174	158
r894	r895
185	169	{
186	170	code_log_reset();
187	171
188		mips3.drc->generate_interrupt_exception = drc->cache_top;
	172	mips3.drcdata->generate_interrupt_exception = drc->cache_top;
189	173	append_generate_exception(drc, EXCEPTION_INTERRUPT);
190		code_log("generate_interrupt_exception:", mips3.drc->generate_interrupt_exception, drc->cache_top);
	174	code_log("generate_interrupt_exception:", mips3.drcdata->generate_interrupt_exception, drc->cache_top);
191	175
192		mips3.drc->generate_cop_exception = drc->cache_top;
	176	mips3.drcdata->generate_cop_exception = drc->cache_top;
193	177	append_generate_exception(drc, EXCEPTION_BADCOP);
194		code_log("generate_cop_exception:", mips3.drc->generate_cop_exception, drc->cache_top);
	178	code_log("generate_cop_exception:", mips3.drcdata->generate_cop_exception, drc->cache_top);
195	179
196		mips3.drc->generate_overflow_exception = drc->cache_top;
	180	mips3.drcdata->generate_overflow_exception = drc->cache_top;
197	181	append_generate_exception(drc, EXCEPTION_OVERFLOW);
198		code_log("generate_overflow_exception:", mips3.drc->generate_overflow_exception, drc->cache_top);
	182	code_log("generate_overflow_exception:", mips3.drcdata->generate_overflow_exception, drc->cache_top);
199	183
200		mips3.drc->generate_invalidop_exception = drc->cache_top;
	184	mips3.drcdata->generate_invalidop_exception = drc->cache_top;
201	185	append_generate_exception(drc, EXCEPTION_INVALIDOP);
202		code_log("generate_invalidop_exception:", mips3.drc->generate_invalidop_exception, drc->cache_top);
	186	code_log("generate_invalidop_exception:", mips3.drcdata->generate_invalidop_exception, drc->cache_top);
203	187
204		mips3.drc->generate_syscall_exception = drc->cache_top;
	188	mips3.drcdata->generate_syscall_exception = drc->cache_top;
205	189	append_generate_exception(drc, EXCEPTION_SYSCALL);
206		code_log("generate_syscall_exception:", mips3.drc->generate_syscall_exception, drc->cache_top);
	190	code_log("generate_syscall_exception:", mips3.drcdata->generate_syscall_exception, drc->cache_top);
207	191
208		mips3.drc->generate_break_exception = drc->cache_top;
	192	mips3.drcdata->generate_break_exception = drc->cache_top;
209	193	append_generate_exception(drc, EXCEPTION_BREAK);
210		code_log("generate_break_exception:", mips3.drc->generate_break_exception, drc->cache_top);
	194	code_log("generate_break_exception:", mips3.drcdata->generate_break_exception, drc->cache_top);
211	195
212		mips3.drc->generate_trap_exception = drc->cache_top;
	196	mips3.drcdata->generate_trap_exception = drc->cache_top;
213	197	append_generate_exception(drc, EXCEPTION_TRAP);
214		code_log("generate_trap_exception:", mips3.drc->generate_trap_exception, drc->cache_top);
	198	code_log("generate_trap_exception:", mips3.drcdata->generate_trap_exception, drc->cache_top);
215	199
216		mips3.drc->generate_tlbload_exception = drc->cache_top;
	200	mips3.drcdata->generate_tlbload_exception = drc->cache_top;
217	201	append_generate_exception(drc, EXCEPTION_TLBLOAD);
218		code_log("generate_tlbload_exception:", mips3.drc->generate_tlbload_exception, drc->cache_top);
	202	code_log("generate_tlbload_exception:", mips3.drcdata->generate_tlbload_exception, drc->cache_top);
219	203
220		mips3.drc->generate_tlbstore_exception = drc->cache_top;
	204	mips3.drcdata->generate_tlbstore_exception = drc->cache_top;
221	205	append_generate_exception(drc, EXCEPTION_TLBSTORE);
222		code_log("generate_tlbstore_exception:", mips3.drc->generate_tlbstore_exception, drc->cache_top);
	206	code_log("generate_tlbstore_exception:", mips3.drcdata->generate_tlbstore_exception, drc->cache_top);
223	207
224		mips3.drc->handle_pc_tlb_mismatch = drc->cache_top;
	208	mips3.drcdata->handle_pc_tlb_mismatch = drc->cache_top;
225	209	_mov_r32_r32(REG_EAX, REG_EDI); // mov eax,edi
226	210	_shr_r32_imm(REG_EAX, 12); // shr eax,12
227		_mov_r32_m32isd(REG_EBX, REG_EAX, 4, &mips3.core.tlb_table); // mov ebx,tlb_table[eax*4]
	211	_mov_r32_m32isd(REG_EBX, REG_EAX, 4, mips3.core->tlb_table); // mov ebx,tlb_table[eax*4]
228	212	_test_r32_imm(REG_EBX, 2); // test ebx,2
229	213	_mov_r32_r32(REG_EAX, REG_EDI); // mov eax,edi
230		_jcc(COND_NZ, mips3.drc->generate_tlbload_exception); // jnz generate_tlbload_exception
	214	_jcc(COND_NZ, mips3.drcdata->generate_tlbload_exception); // jnz generate_tlbload_exception
231	215	_mov_m32abs_r32(drc->pcptr, REG_EDI); // mov [pcptr],edi
232	216	_jmp(drc->recompile); // call recompile
233		code_log("handle_pc_tlb_mismatch:", mips3.drc->handle_pc_tlb_mismatch, drc->cache_top);
	217	code_log("handle_pc_tlb_mismatch:", mips3.drcdata->handle_pc_tlb_mismatch, drc->cache_top);
234	218
235		mips3.drc->read_and_translate_byte_signed = drc->cache_top;
236		append_readwrite_and_translate(drc, FALSE, 1, TRUE, TRUE);
237		code_log("read_and_translate_byte_signed:", mips3.drc->read_and_translate_byte_signed, drc->cache_top);
	219	mips3.drcdata->read_and_translate_byte_signed = drc->cache_top;
	220	append_readwrite_and_translate(drc, 1, ARW_READ \| ARW_SIGNED);
	221	code_log("read_and_translate_byte_signed:", mips3.drcdata->read_and_translate_byte_signed, drc->cache_top);
238	222
239		mips3.drc->read_and_translate_byte_unsigned = drc->cache_top;
240		append_readwrite_and_translate(drc, FALSE, 1, FALSE, TRUE);
241		code_log("read_and_translate_byte_unsigned:", mips3.drc->read_and_translate_byte_unsigned, drc->cache_top);
	223	mips3.drcdata->read_and_translate_byte_unsigned = drc->cache_top;
	224	append_readwrite_and_translate(drc, 1, ARW_READ \| ARW_UNSIGNED);
	225	code_log("read_and_translate_byte_unsigned:", mips3.drcdata->read_and_translate_byte_unsigned, drc->cache_top);
242	226
243		mips3.drc->read_and_translate_word_signed = drc->cache_top;
244		append_readwrite_and_translate(drc, FALSE, 2, TRUE, TRUE);
245		code_log("read_and_translate_word_signed:", mips3.drc->read_and_translate_word_signed, drc->cache_top);
	227	mips3.drcdata->read_and_translate_word_signed = drc->cache_top;
	228	append_readwrite_and_translate(drc, 2, ARW_READ \| ARW_SIGNED);
	229	code_log("read_and_translate_word_signed:", mips3.drcdata->read_and_translate_word_signed, drc->cache_top);
246	230
247		mips3.drc->read_and_translate_word_unsigned = drc->cache_top;
248		append_readwrite_and_translate(drc, FALSE, 2, FALSE, TRUE);
249		code_log("read_and_translate_word_unsigned:", mips3.drc->read_and_translate_word_unsigned, drc->cache_top);
	231	mips3.drcdata->read_and_translate_word_unsigned = drc->cache_top;
	232	append_readwrite_and_translate(drc, 2, ARW_READ \| ARW_UNSIGNED);
	233	code_log("read_and_translate_word_unsigned:", mips3.drcdata->read_and_translate_word_unsigned, drc->cache_top);
250	234
251		mips3.drc->read_and_translate_long = drc->cache_top;
252		append_readwrite_and_translate(drc, FALSE, 4, FALSE, TRUE);
253		code_log("read_and_translate_long:", mips3.drc->read_and_translate_long, drc->cache_top);
	235	mips3.drcdata->read_and_translate_long = drc->cache_top;
	236	append_readwrite_and_translate(drc, 4, ARW_READ);
	237	code_log("read_and_translate_long:", mips3.drcdata->read_and_translate_long, drc->cache_top);
254	238
255		mips3.drc->read_and_translate_double = drc->cache_top;
256		append_readwrite_and_translate(drc, FALSE, 8, FALSE, TRUE);
257		code_log("read_and_translate_double:", mips3.drc->read_and_translate_double, drc->cache_top);
	239	mips3.drcdata->read_and_translate_long_masked = drc->cache_top;
	240	append_readwrite_and_translate(drc, 4, ARW_READ \| ARW_MASKED);
	241	code_log("read_and_translate_long_masked:", mips3.drcdata->read_and_translate_long_masked, drc->cache_top);
258	242
259		mips3.drc->write_and_translate_byte = drc->cache_top;
260		append_readwrite_and_translate(drc, TRUE, 1, FALSE, TRUE);
261		code_log("write_and_translate_byte:", mips3.drc->write_and_translate_byte, drc->cache_top);
	243	mips3.drcdata->read_and_translate_double = drc->cache_top;
	244	append_readwrite_and_translate(drc, 8, ARW_READ);
	245	code_log("read_and_translate_double:", mips3.drcdata->read_and_translate_double, drc->cache_top);
262	246
263		mips3.drc->write_and_translate_word = drc->cache_top;
264		append_readwrite_and_translate(drc, TRUE, 2, FALSE, TRUE);
265		code_log("write_and_translate_word:", mips3.drc->write_and_translate_word, drc->cache_top);
	247	mips3.drcdata->read_and_translate_double_masked = drc->cache_top;
	248	append_readwrite_and_translate(drc, 8, ARW_READ \| ARW_MASKED);
	249	code_log("read_and_translate_double_masked:", mips3.drcdata->read_and_translate_double_masked, drc->cache_top);
266	250
267		mips3.drc->write_and_translate_long = drc->cache_top;
268		append_readwrite_and_translate(drc, TRUE, 4, FALSE, TRUE);
269		code_log("write_and_translate_long:", mips3.drc->write_and_translate_long, drc->cache_top);
	251	mips3.drcdata->write_and_translate_byte = drc->cache_top;
	252	append_readwrite_and_translate(drc, 1, ARW_WRITE);
	253	code_log("write_and_translate_byte:", mips3.drcdata->write_and_translate_byte, drc->cache_top);
270	254
271		mips3.drc->write_and_translate_double = drc->cache_top;
272		append_readwrite_and_translate(drc, TRUE, 8, FALSE, TRUE);
273		code_log("write_and_translate_double:", mips3.drc->write_and_translate_double, drc->cache_top);
	255	mips3.drcdata->write_and_translate_word = drc->cache_top;
	256	append_readwrite_and_translate(drc, 2, ARW_WRITE);
	257	code_log("write_and_translate_word:", mips3.drcdata->write_and_translate_word, drc->cache_top);
274	258
275		mips3.drc->write_back_long = drc->cache_top;
276		append_readwrite_and_translate(drc, TRUE, 4, FALSE, FALSE);
277		code_log("write_back_long:", mips3.drc->write_back_long, drc->cache_top);
	259	mips3.drcdata->write_and_translate_long = drc->cache_top;
	260	append_readwrite_and_translate(drc, 4, ARW_WRITE);
	261	code_log("write_and_translate_long:", mips3.drcdata->write_and_translate_long, drc->cache_top);
278	262
279		mips3.drc->write_back_double = drc->cache_top;
280		append_readwrite_and_translate(drc, TRUE, 8, FALSE, FALSE);
281		code_log("write_back_double:", mips3.drc->write_back_double, drc->cache_top);
	263	mips3.drcdata->write_and_translate_long_masked = drc->cache_top;
	264	append_readwrite_and_translate(drc, 4, ARW_WRITE \| ARW_MASKED);
	265	code_log("write_and_translate_long_masked:", mips3.drcdata->write_and_translate_long_masked, drc->cache_top);
	266
	267	mips3.drcdata->write_and_translate_double = drc->cache_top;
	268	append_readwrite_and_translate(drc, 8, ARW_WRITE);
	269	code_log("write_and_translate_double:", mips3.drcdata->write_and_translate_double, drc->cache_top);
	270
	271	mips3.drcdata->write_and_translate_double_masked = drc->cache_top;
	272	append_readwrite_and_translate(drc, 8, ARW_WRITE \| ARW_MASKED);
	273	code_log("write_and_translate_double_masked:", mips3.drcdata->write_and_translate_double_masked, drc->cache_top);
282	274	}
283	275
284	276
r894	r895
290	282	{
291	283	int remaining = MAX_INSTRUCTIONS;
292	284	void *start = drc->cache_top;
293		UINT32 pc = mips3.core.pc;
	285	UINT32 pc = mips3.core->pc;
294	286	UINT32 lastpc = pc;
295	287	UINT32 physpc;
296	288
r894	r895
301	293	code_log_reset();
302	294
303	295	/* make sure our FR flag matches the last time */
304		_test_m32abs_imm(&mips3.core.cpr[0][COP0_Status], SR_FR); // test [COP0_Status],SR_FR
	296	_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_FR); // test [COP0_Status],SR_FR
305	297	_jcc(IS_FR0 ? COND_NZ : COND_Z, drc->recompile); // jnz/z recompile
306	298
307	299	/* ensure that we are still mapped */
308		append_tlb_verify(drc, pc, mips3.drc->handle_pc_tlb_mismatch);
	300	append_tlb_verify(drc, pc, mips3.drcdata->handle_pc_tlb_mismatch);
309	301	physpc = pc;
310		if (!mips3com_translate_address(&mips3.core, ADDRESS_SPACE_PROGRAM, &physpc))
	302	if (!mips3com_translate_address(mips3.core, ADDRESS_SPACE_PROGRAM, &physpc))
311	303	{
312	304	_mov_r32_r32(REG_EAX, REG_EDI); // mov eax,edi
313		_jmp(mips3.drc->generate_tlbload_exception); // jmp tlbload_exception
	305	_jmp(mips3.drcdata->generate_tlbload_exception); // jmp tlbload_exception
314	306	goto exit;
315	307	}
316	308	change_pc(physpc);
r894	r895
328	320	if ((pc ^ lastpc) & 0xfffff000)
329	321	{
330	322	physpc = pc;
331		if (!mips3com_translate_address(&mips3.core, ADDRESS_SPACE_PROGRAM, &physpc))
	323	if (!mips3com_translate_address(mips3.core, ADDRESS_SPACE_PROGRAM, &physpc))
332	324	break;
333	325	append_tlb_verify(drc, pc, drc->dispatch);
334	326	change_pc(physpc);
r894	r895
354	346	#if LOG_CODE
355	347	{
356	348	char label[40];
357		physpc = mips3.core.pc;
358		mips3com_translate_address(&mips3.core, ADDRESS_SPACE_PROGRAM, &physpc);
359		sprintf(label, "Code @ %08X (%08X physical)", mips3.core.pc, physpc);
	349	physpc = mips3.core->pc;
	350	mips3com_translate_address(mips3.core, ADDRESS_SPACE_PROGRAM, &physpc);
	351	sprintf(label, "Code @ %08X (%08X physical)", mips3.core->pc, physpc);
360	352	code_log(label, start, drc->cache_top);
361	353	}
362	354	#endif
r894	r895
369	361
370	362	static void drc_entrygen_callback(drc_core *drc)
371	363	{
372		_mov_r32_imm(REG_ESI, &mips3.core.r[17]);
	364	_mov_r32_imm(REG_ESI, &mips3.core->r[17]);
373	365	append_check_interrupts(drc, 1);
374	366	}
375	367
r894	r895
461	453	/* assumes address is in EAX */
462	454	if (exception == EXCEPTION_TLBLOAD \|\| exception == EXCEPTION_TLBSTORE)
463	455	{
464		_mov_m32abs_r32(&mips3.core.cpr[0][COP0_BadVAddr], REG_EAX); // mov [mips3.core.cpr[0][BadVAddr]],eax
465		_and_m32abs_imm(&mips3.core.cpr[0][COP0_EntryHi], 0x000000ff); // and [mips3.core.cpr[0][EntryHi]],0x000000ff
	456	_mov_m32abs_r32(&mips3.core->cpr[0][COP0_BadVAddr], REG_EAX); // mov [mips3.core->cpr[0][BadVAddr]],eax
	457	_and_m32abs_imm(&mips3.core->cpr[0][COP0_EntryHi], 0x000000ff); // and [mips3.core->cpr[0][EntryHi]],0x000000ff
466	458	_and_r32_imm(REG_EAX, 0xffffe000); // and eax,0xffffe000
467		_or_m32abs_r32(&mips3.core.cpr[0][COP0_EntryHi], REG_EAX); // or [mips3.core.cpr[0][EntryHi]],eax
468		_and_m32abs_imm(&mips3.core.cpr[0][COP0_Context], 0xff800000); // and [mips3.core.cpr[0][Context]],0xff800000
	459	_or_m32abs_r32(&mips3.core->cpr[0][COP0_EntryHi], REG_EAX); // or [mips3.core->cpr[0][EntryHi]],eax
	460	_and_m32abs_imm(&mips3.core->cpr[0][COP0_Context], 0xff800000); // and [mips3.core->cpr[0][Context]],0xff800000
469	461	_shr_r32_imm(REG_EAX, 9); // shr eax,9
470		_or_m32abs_r32(&mips3.core.cpr[0][COP0_Context], REG_EAX); // or [mips3.core.cpr[0][Context]],eax
	462	_or_m32abs_r32(&mips3.core->cpr[0][COP0_Context], REG_EAX); // or [mips3.core->cpr[0][Context]],eax
471	463	}
472	464
473		_mov_m32abs_r32(&mips3.core.cpr[0][COP0_EPC], REG_EDI); // mov [mips3.core.cpr[0][COP0_EPC]],edi
474		_mov_r32_m32abs(REG_EAX, &mips3.core.cpr[0][COP0_Cause]); // mov eax,[mips3.core.cpr[0][COP0_Cause]]
	465	_mov_m32abs_r32(&mips3.core->cpr[0][COP0_EPC], REG_EDI); // mov [mips3.core->cpr[0][COP0_EPC]],edi
	466	_mov_r32_m32abs(REG_EAX, &mips3.core->cpr[0][COP0_Cause]); // mov eax,[mips3.core->cpr[0][COP0_Cause]]
475	467	_and_r32_imm(REG_EAX, ~0x800000ff); // and eax,~0x800000ff
476	468	if (exception)
477	469	_or_r32_imm(REG_EAX, exception << 2); // or eax,exception << 2
478	470	_cmp_m32abs_imm(&mips3.nextpc, ~0); // cmp [mips3.nextpc],~0
479	471	_jcc_short_link(COND_E, &link1); // je skip
480	472	_mov_m32abs_imm(&mips3.nextpc, ~0); // mov [mips3.nextpc],~0
481		_sub_m32abs_imm(&mips3.core.cpr[0][COP0_EPC], 4); // sub [mips3.core.cpr[0][COP0_EPC]],4
	473	_sub_m32abs_imm(&mips3.core->cpr[0][COP0_EPC], 4); // sub [mips3.core->cpr[0][COP0_EPC]],4
482	474	_or_r32_imm(REG_EAX, 0x80000000); // or eax,0x80000000
483	475	_resolve_link(&link1); // skip:
484		_mov_m32abs_r32(&mips3.core.cpr[0][COP0_Cause], REG_EAX); // mov [mips3.core.cpr[0][COP0_Cause]],eax
485		_mov_r32_m32abs(REG_EAX, &mips3.core.cpr[0][COP0_Status]); // mov eax,[[mips3.core.cpr[0][COP0_Status]]
	476	_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Cause], REG_EAX); // mov [mips3.core->cpr[0][COP0_Cause]],eax
	477	_mov_r32_m32abs(REG_EAX, &mips3.core->cpr[0][COP0_Status]); // mov eax,[[mips3.core->cpr[0][COP0_Status]]
486	478	_or_r32_imm(REG_EAX, SR_EXL); // or eax,SR_EXL
487	479	_test_r32_imm(REG_EAX, SR_BEV); // test eax,SR_BEV
488		_mov_m32abs_r32(&mips3.core.cpr[0][COP0_Status], REG_EAX); // mov [[mips3.core.cpr[0][COP0_Status]],eax
	480	_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Status], REG_EAX); // mov [[mips3.core->cpr[0][COP0_Status]],eax
489	481	_mov_r32_imm(REG_EDI, 0xbfc00200 + offset); // mov edi,0xbfc00200+offset
490	482	_jcc_short_link(COND_NZ, &link2); // jnz skip2
491	483	_mov_r32_imm(REG_EDI, 0x80000000 + offset); // mov edi,0x80000000+offset
r894	r895
498	490	append_readwrite_and_translate
499	491	------------------------------------------------------------------*/
500	492
501		static void append_readwrite_and_translate(drc_core *drc, int is~~_wr~~i~~te, int si~~ze, ~~int~~ ~~is_signed, int do_trans~~late)
	493	static void append_readwrite_and_translate(drc_core *drc, int size, UINT8 flags)
502	494	{
503	495	link_info link1 = { 0 }, link2 = { 0 }, link3 = { 0 };
504	496	int ramnum;
505	497
506		if (do_translate)
507		{
508		_mov_r32_m32bd(REG_EAX, REG_ESP, 4); // mov eax,[esp+4]
509		_mov_r32_r32(REG_EBX, REG_EAX); // mov ebx,eax
510		_shr_r32_imm(REG_EBX, 12); // shr ebx,12
511		_mov_r32_m32isd(REG_EBX, REG_EBX, 4, mips3.core.tlb_table); // mov ebx,tlb_table[ebx*4]
512		_and_r32_imm(REG_EAX, 0xfff); // and eax,0xfff
513		_shr_r32_imm(REG_EBX, (is_write ? 1 : 2)); // shr ebx,2/1 (read/write)
514		_lea_r32_m32bisd(REG_EBX, REG_EAX, REG_EBX, (is_write ? 2 : 4), 0); // lea ebx,[eax+ebx*4/2] (read/write)
515		_jcc_short_link(COND_C, &link1); // jc error
516		}
	498	_mov_r32_m32bd(REG_EAX, REG_ESP, 4); // mov eax,[esp+4]
	499	_mov_r32_r32(REG_EBX, REG_EAX); // mov ebx,eax
	500	_shr_r32_imm(REG_EBX, 12); // shr ebx,12
	501	_mov_r32_m32isd(REG_EBX, REG_EBX, 4, mips3.core->tlb_table); // mov ebx,tlb_table[ebx*4]
	502	_and_r32_imm(REG_EAX, 0xfff); // and eax,0xfff
	503	_shr_r32_imm(REG_EBX, ((flags & ARW_WRITE) ? 1 : 2)); // shr ebx,2/1 (read/write)
	504	_lea_r32_m32bisd(REG_EBX, REG_EAX, REG_EBX, ((flags & ARW_WRITE) ? 2 : 4), 0); // lea ebx,[eax+ebx*4/2] (read/write)
	505	_jcc_near_link(COND_C, &link1); // jc error
517	506	for (ramnum = 0; ramnum < MIPS3_MAX_FASTRAM; ramnum++)
518		if (!Machine->debug_mode && mips3.fastram[ramnum].base && (!is_~~write~~ \|\| !mips3.fastram[ramnum].readonly))
	507	if (!Machine->debug_mode && mips3.fastram[ramnum].base && (!(flags & ARW_WRITE) \|\| !mips3.fastram[ramnum].readonly))
519	508	{
520	509	UINT32 fastbase = (UINT32)((UINT8 *)mips3.fastram[ramnum].base - mips3.fastram[ramnum].start);
521	510	if (mips3.fastram[ramnum].end != 0xffffffff)
r894	r895
529	518	_jcc_short_link(COND_B, &link3); // jb notram
530	519	}
531	520
532		if (!is_~~write~~)
	521	if (!(flags & ARW_WRITE))
533	522	{
534	523	if (size == 1)
535	524	{
536		if (mips3.core.bigendian)
	525	if (mips3.core->bigendian)
537	526	_xor_r32_imm(REG_EBX, 3); // xor ebx,3
538		if (is_~~signed~~)
	527	if (flags & ARW_SIGNED)
539	528	_movsx_r32_m8bd(REG_EAX, REG_EBX, fastbase); // movsx eax,byte ptr [ebx+fastbase]
540	529	else
541	530	_movzx_r32_m8bd(REG_EAX, REG_EBX, fastbase); // movzx eax,byte ptr [ebx+fastbase]
542	531	}
543	532	else if (size == 2)
544	533	{
545		if (mips3.core.bigendian)
	534	if (mips3.core->bigendian)
546	535	_xor_r32_imm(REG_EBX, 2); // xor ebx,2
547		if (is_~~signed~~)
	536	if (flags & ARW_SIGNED)
548	537	_movsx_r32_m16bd(REG_EAX, REG_EBX, fastbase); // movsx eax,word ptr [ebx+fastbase]
549	538	else
550	539	_movzx_r32_m16bd(REG_EAX, REG_EBX, fastbase); // movzx eax,word ptr [ebx+fastbase]
r894	r895
553	542	_mov_r32_m32bd(REG_EAX, REG_EBX, fastbase); // mov eax,[ebx+fastbase]
554	543	else if (size == 8)
555	544	{
556		if (mips3.core.bigendian)
	545	if (mips3.core->bigendian)
557	546	_mov_r64_m64bd(REG_EAX, REG_EDX, REG_EBX, fastbase); // mov eax:edx,[ebx+fastbase]
558	547	else
559	548	_mov_r64_m64bd(REG_EDX, REG_EAX, REG_EBX, fastbase); // mov edx:eax,[ebx+fastbase]
r894	r895
565	554	if (size == 1)
566	555	{
567	556	_mov_r8_m8bd(REG_AL, REG_ESP, 8); // mov al,[esp+8]
568		if (mips3.core.bigendian)
	557	if (mips3.core->bigendian)
569	558	_xor_r32_imm(REG_EBX, 3); // xor ebx,3
570	559	_mov_m8bd_r8(REG_EBX, fastbase, REG_AL); // mov [ebx+fastbase],al
571	560	}
572	561	else if (size == 2)
573	562	{
574	563	_mov_r16_m16bd(REG_AX, REG_ESP, 8); // mov ax,[esp+8]
575		if (mips3.core.bigendian)
	564	if (mips3.core->bigendian)
576	565	_xor_r32_imm(REG_EBX, 2); // xor ebx,2
577	566	_mov_m16bd_r16(REG_EBX, fastbase, REG_AX); // mov [ebx+fastbase],ax
578	567	}
579	568	else if (size == 4)
580	569	{
581		_mov_r32_m32bd(REG_EAX, REG_ESP, 8); // mov eax,[esp+8]
582		_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
583		}
584		else if (size == 8)
585		{
586		if (mips3.core.bigendian)
	570	if (!(flags & ARW_MASKED))
587	571	{
588	572	_mov_r32_m32bd(REG_EAX, REG_ESP, 8); // mov eax,[esp+8]
589		_mov_m32bd_r32(REG_EBX, fastbase+4, REG_EAX); // mov [ebx+fastbase+4],eax
590		_mov_r32_m32bd(REG_EAX, REG_ESP, 12); // mov eax,[esp+12]
591	573	_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
592	574	}
593	575	else
594	576	{
595		_mov_r32_m32bd(REG_EAX, REG_ESP, 8); // mov eax,[esp+8]
	577	_mov_r32_m32bd(REG_ECX, REG_ESP, 12); // mov ecx,[esp+12]
	578	_mov_r32_r32(REG_EAX, REG_ECX); // mov eax,ecx
	579	_and_r32_m32bd(REG_ECX, REG_EBX, fastbase); // and ecx,[ebx+fastbase]
	580	_not_r32(REG_EAX); // not eax
	581	_and_r32_m32bd(REG_EAX, REG_ESP, 8); // and eax,[esp+8]
	582	_or_r32_r32(REG_EAX, REG_ECX); // or eax,ecx
596	583	_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
597		_mov_r32_m32bd(REG_EAX, REG_ESP, 12); // mov eax,[esp+12]
598		_mov_m32bd_r32(REG_EBX, fastbase+4, REG_EAX); // mov [ebx+fastbase+4],eax
599	584	}
600	585	}
	586	else if (size == 8)
	587	{
	588	if (!(flags & ARW_MASKED))
	589	{
	590	if (mips3.core->bigendian)
	591	{
	592	_mov_r32_m32bd(REG_EAX, REG_ESP, 8); // mov eax,[esp+8]
	593	_mov_m32bd_r32(REG_EBX, fastbase+4, REG_EAX); // mov [ebx+fastbase+4],eax
	594	_mov_r32_m32bd(REG_EAX, REG_ESP, 12); // mov eax,[esp+12]
	595	_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
	596	}
	597	else
	598	{
	599	_mov_r32_m32bd(REG_EAX, REG_ESP, 8); // mov eax,[esp+8]
	600	_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
	601	_mov_r32_m32bd(REG_EAX, REG_ESP, 12); // mov eax,[esp+12]
	602	_mov_m32bd_r32(REG_EBX, fastbase+4, REG_EAX); // mov [ebx+fastbase+4],eax
	603	}
	604	}
	605	else
	606	{
	607	if (mips3.core->bigendian)
	608	{
	609	_mov_r32_m32bd(REG_ECX, REG_ESP, 16); // mov ecx,[esp+16]
	610	_mov_r32_r32(REG_EAX, REG_ECX); // mov eax,ecx
	611	_and_r32_m32bd(REG_ECX, REG_EBX, fastbase+4); // and ecx,[ebx+fastbase+4]
	612	_not_r32(REG_EAX); // not eax
	613	_and_r32_m32bd(REG_EAX, REG_ESP, 8); // and eax,[esp+8]
	614	_or_r32_r32(REG_EAX, REG_ECX); // or eax,ecx
	615	_mov_m32bd_r32(REG_EBX, fastbase+4, REG_EAX); // mov [ebx+fastbase+4],eax
	616	_mov_r32_m32bd(REG_ECX, REG_ESP, 20); // mov ecx,[esp+20]
	617	_mov_r32_r32(REG_EAX, REG_ECX); // mov eax,ecx
	618	_and_r32_m32bd(REG_ECX, REG_EBX, fastbase); // and ecx,[ebx+fastbase]
	619	_not_r32(REG_EAX); // not eax
	620	_and_r32_m32bd(REG_EAX, REG_ESP, 12); // and eax,[esp+12]
	621	_or_r32_r32(REG_EAX, REG_ECX); // or eax,ecx
	622	_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
	623	}
	624	else
	625	{
	626	_mov_r32_m32bd(REG_ECX, REG_ESP, 16); // mov ecx,[esp+16]
	627	_mov_r32_r32(REG_EAX, REG_ECX); // mov eax,ecx
	628	_and_r32_m32bd(REG_ECX, REG_EBX, fastbase); // and ecx,[ebx+fastbase]
	629	_not_r32(REG_EAX); // not eax
	630	_and_r32_m32bd(REG_EAX, REG_ESP, 8); // and eax,[esp+8]
	631	_or_r32_r32(REG_EAX, REG_ECX); // or eax,ecx
	632	_mov_m32bd_r32(REG_EBX, fastbase, REG_EAX); // mov [ebx+fastbase],eax
	633	_mov_r32_m32bd(REG_ECX, REG_ESP, 20); // mov ecx,[esp+20]
	634	_mov_r32_r32(REG_EAX, REG_ECX); // mov eax,ecx
	635	_and_r32_m32bd(REG_ECX, REG_EBX, fastbase+4); // and ecx,[ebx+fastbase+4]
	636	_not_r32(REG_EAX); // not eax
	637	_and_r32_m32bd(REG_EAX, REG_ESP, 12); // and eax,[esp+12]
	638	_or_r32_r32(REG_EAX, REG_ECX); // or eax,ecx
	639	_mov_m32bd_r32(REG_EBX, fastbase+4, REG_EAX); // mov [ebx+fastbase+4],eax
	640	}
	641	}
	642	}
601	643	_ret(); // ret
602	644	}
603	645
r894	r895
607	649	_resolve_link(&link3);
608	650	}
609	651
610		if (is_~~write~~)
	652	if (flags & ARW_WRITE)
611	653	{
612		if (size != 8)
	654	_mov_m32bd_r32(REG_ESP, 4, REG_EBX); // mov [esp+4],ebx
	655	if (size == 1)
	656	_jmp(mips3.core->memory.writebyte); // jmp writebyte
	657	else if (size == 2)
	658	_jmp(mips3.core->memory.writeword); // jmp writeword
	659	else if (size == 4)
613	660	{
614		_mov_m32bd_r32(REG_ESP, 4, REG_EBX); // mov [esp+4],ebx
615		if (size == 1)
616		_jmp(mips3.core.memory.writebyte); // jmp writebyte
617		else if (size == 2)
618		_jmp(mips3.core.memory.writeword); // jmp writeword
	661	if (!(flags & ARW_MASKED))
	662	_jmp(mips3.core->memory.writelong); // jmp writelong
619	663	else
620		_jmp(mips3.core.memory.writelong); // jmp writelong
	664	_jmp(mips3.core->memory.writelong_masked); // jmp writelong_masked
621	665	}
622	666	else
623	667	{
624		_sub_r32_imm(REG_ESP, 4); // sub esp,4
625		_push_m32bd(REG_ESP, mips3.core.bigendian ? 16 : 12); // push [esp+12/16]
626		_push_r32(REG_EBX); // push ebx
627		_call(mips3.core.memory.writelong); // call writelong
628		_add_r32_imm(REG_EBX, 4); // add ebx,4
629		_sub_r32_imm(REG_ESP, 8); // sub esp,8
630		_push_m32bd(REG_ESP, mips3.core.bigendian ? (12+16) : (16+16)); // push [esp+16+12/16]
631		_push_r32(REG_EBX); // push ebx
632		_call(mips3.core.memory.writelong); // call writelong
633		_sub_r32_imm(REG_EBX, 4); // sub ebx,4
634		_add_r32_imm(REG_ESP, 28); // add esp,28
635		_ret(); // ret
	668	if (!(flags & ARW_MASKED))
	669	_jmp(mips3.core->memory.writedouble); // jmp writedouble
	670	else
	671	_jmp(mips3.core->memory.writedouble_masked); // jmp writedouble_masked
636	672	}
637	673	}
638	674	else
r894	r895
641	677	{
642	678	_sub_r32_imm(REG_ESP, 8); // sub esp,8
643	679	_push_r32(REG_EBX); // push ebx
644		_call(mips3.core.memory.readbyte); // call readbyte
645		if (is_signed)
	680	_call(mips3.core->memory.readbyte); // call readbyte
	681	if (flags & ARW_SIGNED)
646	682	_movsx_r32_r8(REG_EAX, REG_AL); // movsx eax,al
647	683	else
648	684	_movzx_r32_r8(REG_EAX, REG_AL); // movzx eax,al
r894	r895
653	689	{
654	690	_sub_r32_imm(REG_ESP, 8); // sub esp,8
655	691	_push_r32(REG_EBX); // push ebx
656		_call(mips3.core.memory.readword); // call readword
657		if (is_signed)
	692	_call(mips3.core->memory.readword); // call readword
	693	if (flags & ARW_SIGNED)
658	694	_movsx_r32_r16(REG_EAX, REG_AX); // movsx eax,ax
659	695	else
660	696	_movzx_r32_r16(REG_EAX, REG_AX); // movzx eax,ax
r894	r895
664	700	else if (size == 4)
665	701	{
666	702	_mov_m32bd_r32(REG_ESP, 4, REG_EBX); // mov [esp+4],ebx
667		_jmp(mips3.core.memory.readlong); // jmp readlong
	703	if (!(flags & ARW_MASKED))
	704	_jmp(mips3.core->memory.readlong); // jmp readlong
	705	else
	706	_jmp(mips3.core->memory.readlong_masked); // jmp readlong_masked
668	707	}
669	708	else
670	709	{
671		_sub_r32_imm(REG_ESP, 8); // sub esp,8
672		_push_r32(REG_EBX); // push ebx
673		_call(mips3.core.memory.readlong); // call readlong
674		_add_r32_imm(REG_EBX, 4); // add ebx,4
675		_mov_m32bd_r32(REG_ESP, 4, REG_EAX); // mov [esp+4],eax
676		_mov_m32bd_r32(REG_ESP, 0, REG_EBX); // mov [esp],ebx
677		_call(mips3.core.memory.readlong); // call readlong
678		_add_r32_imm(REG_ESP, 4); // add esp,4
679		if (mips3.core.bigendian)
680		_pop_r32(REG_EDX); // pop edx
	710	_mov_m32bd_r32(REG_ESP, 4, REG_EBX); // mov [esp+4],ebx
	711	if (!(flags & ARW_MASKED))
	712	_jmp(mips3.core->memory.readdouble); // jmp readdouble
681	713	else
682		{
683		_mov_r32_r32(REG_EDX, REG_EAX); // mov edx,eax
684		_pop_r32(REG_EAX); // pop eax
685		}
686		_sub_r32_imm(REG_EBX, 4); // sub ebx,4
687		_add_r32_imm(REG_ESP, 4); // add esp,4
688		_ret(); // ret
	714	_jmp(mips3.core->memory.readdouble_masked); // jmp readdouble_masked
689	715	}
690	716	}
691		if (do_translate)
692	717	{
	718	int valuebytes = (size == 8) ? 8 : 4;
	719	int stackbytes = 4 + ((flags & ARW_WRITE) ? 4 + valuebytes : 4) + ((flags & ARW_MASKED) ? valuebytes : 0);
693	720	_resolve_link(&link1); // error:
694	721	_mov_r32_m32bd(REG_EAX, REG_ESP, 4); // mov eax,[esp+4]
695		_add_r32_imm(REG_ESP, is_write ? (8+4) : (4+4)); // add esp,stack_bytes
696		_jmp(is_write ? mips3.drc->generate_tlbstore_exception : mips3.drc->generate_tlbload_exception);// jmp generate_exception
	722	_add_r32_imm(REG_ESP, stackbytes); // add esp,stack_bytes
	723	_jmp((flags & ARW_WRITE) ? mips3.drcdata->generate_tlbstore_exception : mips3.drcdata->generate_tlbload_exception);// jmp generate_exception
697	724	}
698	725	}
699	726
r894	r895
707	734	/* addresses 0x80000000-0xbfffffff are direct-mapped; no checking needed */
708	735	if (pc < 0x80000000 \|\| pc >= 0xc0000000)
709	736	{
710		_cmp_m32abs_imm(&mips3.core.tlb_table[pc >> 12], mips3.core.tlb_table[pc >> 12]);// cmp tlbtable[pc >> 12],physpc & 0xfffff000
	737	_cmp_m32abs_imm(&mips3.core->tlb_table[pc >> 12], mips3.core->tlb_table[pc >> 12]);// cmp tlbtable[pc >> 12],physpc & 0xfffff000
711	738	_jcc(COND_NE, target); // jne handle_pc_tlb_mismatch
712	739	}
713	740	}
r894	r895
720	747	static void append_update_cycle_counting(drc_core *drc)
721	748	{
722	749	_sub_r32_imm(REG_ESP, 8);
723		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
724		_push_imm(&mips3.core); // sub esp,12
	750	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
	751	_push_imm(mips3.core); // sub esp,12
725	752	_call((genf *)mips3com_update_cycle_counting); // call update_cycle_counting
726	753	_add_r32_imm(REG_ESP, 12); // add esp,12
727		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	754	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
728	755	}
729	756
730	757
r894	r895
735	762	static void append_check_interrupts(drc_core *drc, int inline_generate)
736	763	{
737	764	link_info link1, link2, link3;
738		_mov_r32_m32abs(REG_EAX, &mips3.core.cpr[0][COP0_Cause]); // mov eax,[mips3.core.cpr[0][COP0_Cause]]
739		_and_r32_m32abs(REG_EAX, &mips3.core.cpr[0][COP0_Status]); // and eax,[mips3.core.cpr[0][COP0_Status]]
	765	_mov_r32_m32abs(REG_EAX, &mips3.core->cpr[0][COP0_Cause]); // mov eax,[mips3.core->cpr[0][COP0_Cause]]
	766	_and_r32_m32abs(REG_EAX, &mips3.core->cpr[0][COP0_Status]); // and eax,[mips3.core->cpr[0][COP0_Status]]
740	767	_and_r32_imm(REG_EAX, 0xfc00); // and eax,0xfc00
741	768	if (!inline_generate)
742	769	_jcc_short_link(COND_Z, &link1); // jz skip
743	770	else
744	771	_jcc_near_link(COND_Z, &link1); // jz skip
745		_test_m32abs_imm(&mips3.core.cpr[0][COP0_Status], SR_IE); // test [mips3.core.cpr[0][COP0_Status],SR_IE
	772	_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_IE); // test [mips3.core->cpr[0][COP0_Status],SR_IE
746	773	if (!inline_generate)
747	774	_jcc_short_link(COND_Z, &link2); // jz skip
748	775	else
749	776	_jcc_near_link(COND_Z, &link2); // jz skip
750		_test_m32abs_imm(&mips3.core.cpr[0][COP0_Status], SR_EXL \| SR_ERL); // test [mips3.core.cpr[0][COP0_Status],SR_EXL \| SR_ERL
	777	_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_EXL \| SR_ERL); // test [mips3.core->cpr[0][COP0_Status],SR_EXL \| SR_ERL
751	778	if (!inline_generate)
752		_jcc(COND_Z, mips3.drc->generate_interrupt_exception); // jz generate_interrupt_exception
	779	_jcc(COND_Z, mips3.drcdata->generate_interrupt_exception); // jz generate_interrupt_exception
753	780	else
754	781	{
755	782	_jcc_near_link(COND_NZ, &link3); // jnz skip
r894	r895
767	794
768	795	static void append_check_sw_interrupts(drc_core *drc, int inline_generate)
769	796	{
770		_test_m32abs_imm(&mips3.core.cpr[0][COP0_Cause], 0x300); // test [mips3.core.cpr[0][COP0_Cause]],0x300
771		_jcc(COND_NZ, mips3.drc->generate_interrupt_exception); // jnz generate_interrupt_exception
	797	_test_m32abs_imm(&mips3.core->cpr[0][COP0_Cause], 0x300); // test [mips3.core->cpr[0][COP0_Cause]],0x300
	798	_jcc(COND_NZ, mips3.drcdata->generate_interrupt_exception); // jnz generate_interrupt_exception
772	799	}
773	800
774	801
r894	r895
794	821	USEFUL PRIMITIVES
795	822	***************************************************************************/
796	823
797		#define REGDISP(reg) offsetof(mips3_~~reg~~s, cor~~e.r~~[reg]) - offsetof(mips3_~~reg~~s, ~~core.~~r[17])
	824	#define REGDISP(reg) offsetof(mips3_state, r[reg]) - offsetof(mips3_state, r[17])
798	825
799	826	#define _zero_m64abs(addr) \
800	827	do { \
r894	r895
881	908	} while (0)
882	909
883	910	#define FPR32(x) \
884		(IS_FR0 ? &((float *)&mips3.core.cpr[1][0])[x] :\
885		(float *)&mips3.core.cpr[1][x]) \
	911	(IS_FR0 ? &((float *)&mips3.core->cpr[1][0])[x] :\
	912	(float *)&mips3.core->cpr[1][x]) \
886	913
887	914	#define FPR64(x) \
888		(IS_FR0 ? (double *)&mips3.core.cpr[1][(x)/2] : \
889		(double *)&mips3.core.cpr[1][x]) \
	915	(IS_FR0 ? (double *)&mips3.core->cpr[1][(x)/2] : \
	916	(double *)&mips3.core->cpr[1][x]) \
890	917
891	918
892	919	/***************************************************************************
r894	r895
897	924	{
898	925	if (*rt)
899	926	{
900		mips3.core.lo = rs / rt;
901		mips3.core.hi = rs % rt;
	927	mips3.core->lo = rs / rt;
	928	mips3.core->hi = rs % rt;
902	929	}
903	930	}
904	931
r894	r895
906	933	{
907	934	if (*rt)
908	935	{
909		mips3.core.lo = rs / rt;
910		mips3.core.hi = rs % rt;
	936	mips3.core->lo = rs / rt;
	937	mips3.core->hi = rs % rt;
911	938	}
912	939	}
913	940
r894	r895
936	963	/* recompile the instruction as-is */
937	964	in_delay_slot = 1;
938	965	physpc = pc;
939		mips3com_translate_address(&mips3.core, ADDRESS_SPACE_PROGRAM, &physpc);
	966	mips3com_translate_address(mips3.core, ADDRESS_SPACE_PROGRAM, &physpc);
940	967	result = recompile_instruction(drc, pc, physpc); // <next instruction>
941	968	in_delay_slot = 0;
942	969
r894	r895
959	986
960	987	static UINT32 recompile_instruction(drc_core *drc, UINT32 pc, UINT32 physpc)
961	988	{
962		static UINT32 ldl_mask[] =
963		{
964		0x00000000,0x00000000,
965		0x00000000,0x000000ff,
966		0x00000000,0x0000ffff,
967		0x00000000,0x00ffffff,
968		0x00000000,0xffffffff,
969		0x000000ff,0xffffffff,
970		0x0000ffff,0xffffffff,
971		0x00ffffff,0xffffffff
972		};
973		static UINT32 ldr_mask[] =
974		{
975		0x00000000,0x00000000,
976		0xff000000,0x00000000,
977		0xffff0000,0x00000000,
978		0xffffff00,0x00000000,
979		0xffffffff,0x00000000,
980		0xffffffff,0xff000000,
981		0xffffffff,0xffff0000,
982		0xffffffff,0xffffff00
983		};
984		static UINT32 sdl_mask[] =
985		{
986		0x00000000,0x00000000,
987		0xff000000,0x00000000,
988		0xffff0000,0x00000000,
989		0xffffff00,0x00000000,
990		0xffffffff,0x00000000,
991		0xffffffff,0xff000000,
992		0xffffffff,0xffff0000,
993		0xffffffff,0xffffff00
994		};
995		static UINT32 sdr_mask[] =
996		{
997		0x00000000,0x00000000,
998		0x00000000,0x000000ff,
999		0x00000000,0x0000ffff,
1000		0x00000000,0x00ffffff,
1001		0x00000000,0xffffffff,
1002		0x000000ff,0xffffffff,
1003		0x0000ffff,0xffffffff,
1004		0x00ffffff,0xffffffff
1005		};
1006	989	link_info link1, link2 = { 0 }, link3;
1007	990	UINT32 op = cpu_readop32(physpc);
1008	991	int cycles;
r894	r895
1140	1123	{
1141	1124	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1142	1125	_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1143		_jcc(COND_O, mips3.drc->generate_overflow_exception); // jo generate_overflow_exception
	1126	_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
1144	1127	if (RTREG != 0)
1145	1128	{
1146	1129	_cdq(); // cdq
r894	r895
1276	1259	return recompile_cop1(drc, pc, op) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
1277	1260
1278	1261	case 0x12: /* COP2 */
1279		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	1262	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
1280	1263	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
1281	1264
1282	1265	case 0x13: /* COP1X - R5000 */
1283		if (mips3.core.flavor < MIPS3_TYPE_MIPS_IV)
	1266	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
1284	1267	{
1285		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	1268	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
1286	1269	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
1287	1270	}
1288	1271	return recompile_cop1x(drc, pc, op) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
r894	r895
1400	1383	_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
1401	1384	_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1402	1385	_adc_r32_imm(REG_EDX, (SIMMVAL < 0) ? -1 : 0); // adc edx,signext(SIMMVAL)
1403		_jcc(COND_O, mips3.drc->generate_overflow_exception); // jo generate_overflow_exception
	1386	_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
1404	1387	if (RTREG != 0)
1405	1388	_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1406	1389	}
r894	r895
1424	1407	return RECOMPILE_SUCCESSFUL_CP(1,4);
1425	1408
1426	1409	case 0x1a: /* LDL */
1427		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1410	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1428	1411	_save_pc_before_call(); // save pc
1429		_sub_r32_imm(REG_ESP, 4); // sub esp,4
1430	1412	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1431	1413	if (SIMMVAL)
1432	1414	_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1433		_~~push~~_r32(REG_EAX); // ~~push~~ eax
	1415	_lea_r32_m32isd(REG_ECX, REG_EAX, 4, 0); // lea ecx,[eax*4]
1434	1416	_and_r32_imm(REG_EAX, ~7); // and eax,~7
	1417	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1418	_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
	1419	if (!mips3.core->bigendian)
	1420	_xor_r32_imm(REG_ECX, 0x1c); // xor ecx,0x1c
	1421	_shr_r32_cl(REG_EBP); // shr ebp,cl
	1422	_shrd_r32_r32_cl(REG_EBX, REG_EBP); // shrd ebx,ebp,cl
	1423	_shr_r32_cl(REG_EBP); // shr ebp,cl
	1424	_not_r32(REG_EBX); // not ebx
	1425	_not_r32(REG_EBP); // not ebp
	1426	_push_r32(REG_ECX); // push ecx
	1427	_push_r32(REG_EBP); // push ebp
	1428	_push_r32(REG_EBX); // push ebx
1435	1429	_push_r32(REG_EAX); // push eax
1436		_call((genf *)mips3.drc->read_and_translate_double); // call read_and_translate_double
1437		_add_r32_imm(REG_ESP, 4); // add esp,4
	1430	_call((genf *)mips3.drcdata->read_and_translate_double_masked); // call read_and_translate_double_masked
	1431	_add_r32_imm(REG_ESP, 12); // add esp,12
1438	1432	_pop_r32(REG_ECX); // pop ecx
1439		_add_r32_imm(REG_ESP, 4); // add esp,4
1440	1433
1441	1434	if (RTREG != 0)
1442	1435	{
1443		_and_r32_imm(REG_ECX, 7); // and ecx,7
1444		_shl_r32_imm(REG_ECX, 3); // shl ecx,3
1445		if (!mips3.core.bigendian)
1446		_xor_r32_imm(REG_ECX, 0x38); // xor ecx,0x38
1447		_test_r32_imm(REG_ECX, 0x20); // test ecx,0x20
1448		_jcc_short_link(COND_Z, &link1); // jz skip
1449		_mov_r32_r32(REG_EDX, REG_EAX); // mov edx,eax
1450		_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
1451		_resolve_link(&link1); // skip:
	1436	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1437	_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
	1438	_shl_r32_cl(REG_EBX); // shl ebx,cl
	1439	_shld_r32_r32_cl(REG_EBP, REG_EBX); // shld ebp,ebx,cl
	1440	_shl_r32_cl(REG_EBX); // shl ebx,cl
	1441	_not_r32(REG_EBX); // not ebx
	1442	_not_r32(REG_EBP); // not ebp
1452	1443	_shld_r32_r32_cl(REG_EDX, REG_EAX); // shld edx,eax,cl
1453	1444	_shl_r32_cl(REG_EAX); // shl eax,cl
1454		_mov_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // mov ebx,[rtreg].lo
1455		_and_r32_m32bd(REG_EBX, REG_ECX, ldl_mask + 1); // and ebx,[ldl_mask + ecx + 4]
	1445	_shld_r32_r32_cl(REG_EDX, REG_EAX); // shld edx,eax,cl
	1446	_shl_r32_cl(REG_EAX); // shl eax,cl
	1447	_and_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // and ebx,[rtreg].lo
	1448	_and_r32_m32bd(REG_EBP, REG_ESI, REGDISP(RTREG)+4); // and ebp,[rtreg].hi
1456	1449	_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
1457		_mov_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)+4); // mov ebx,[rtreg].hi
1458		_and_r32_m32bd(REG_EBX, REG_ECX, ldl_mask); // and ebx,[ldl_mask + ecx]
1459		_or_r32_r32(REG_EDX, REG_EBX); // or edx,ebx
	1450	_or_r32_r32(REG_EDX, REG_EBP); // or edx,ebp
1460	1451	_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1461	1452	}
1462		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1453	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1463	1454	return RECOMPILE_SUCCESSFUL_CP(1,4);
1464	1455
1465	1456	case 0x1b: /* LDR */
1466		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1457	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1467	1458	_save_pc_before_call(); // save pc
1468		_sub_r32_imm(REG_ESP, 4); // sub esp,4
1469	1459	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1470	1460	if (SIMMVAL)
1471	1461	_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1472		_~~push~~_r32(REG_EAX); // ~~push~~ eax
	1462	_lea_r32_m32isd(REG_ECX, REG_EAX, 4, 0); // lea ecx,[eax*4]
1473	1463	_and_r32_imm(REG_EAX, ~7); // and eax,~7
	1464	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1465	_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
	1466	if (mips3.core->bigendian)
	1467	_xor_r32_imm(REG_ECX, 0x1c); // xor ecx,0x1c
	1468	_shl_r32_cl(REG_EBX); // shl ebx,cl
	1469	_shld_r32_r32_cl(REG_EBP, REG_EBX); // shld ebp,ebx,cl
	1470	_shl_r32_cl(REG_EBX); // shl ebx,cl
	1471	_not_r32(REG_EBX); // not ebx
	1472	_not_r32(REG_EBP); // not ebp
	1473	_push_r32(REG_ECX); // push ecx
	1474	_push_r32(REG_EBP); // push ebp
	1475	_push_r32(REG_EBX); // push ebx
1474	1476	_push_r32(REG_EAX); // push eax
1475		_call((genf *)mips3.drc->read_and_translate_double); // call read_and_translate_double
1476		_add_r32_imm(REG_ESP, 4); // add esp,4
	1477	_call((genf *)mips3.drcdata->read_and_translate_double_masked); // call read_and_translate_double_masked
	1478	_add_r32_imm(REG_ESP, 12); // add esp,12
1477	1479	_pop_r32(REG_ECX); // pop ecx
1478		_add_r32_imm(REG_ESP, 4); // add esp,4
1479	1480
1480	1481	if (RTREG != 0)
1481	1482	{
1482		_and_r32_imm(REG_ECX, 7); // and ecx,7
1483		_shl_r32_imm(REG_ECX, 3); // shl ecx,3
1484		if (mips3.core.bigendian)
1485		_xor_r32_imm(REG_ECX, 0x38); // xor ecx,0x38
1486		_test_r32_imm(REG_ECX, 0x20); // test ecx,0x20
1487		_jcc_short_link(COND_Z, &link1); // jz skip
1488		_mov_r32_r32(REG_EAX, REG_EDX); // mov eax,edx
1489		_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
1490		_resolve_link(&link1); // skip:
1491		_shrd_r32_r32_cl(REG_EAX, REG_EDX); // shrd eax,edx,cl
1492		_shr_r32_cl(REG_EDX); // shr edx,cl
1493		_mov_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // mov ebx,[rtreg].lo
1494		_and_r32_m32bd(REG_EBX, REG_ECX, ldr_mask + 1); // and ebx,[ldr_mask + ecx + 4]
	1483	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1484	_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
	1485	_shr_r32_cl(REG_EBP); // shr ebp,cl
	1486	_shrd_r32_r32_cl(REG_EBX, REG_EBP); // shrd ebx,ebp,cl
	1487	_shr_r32_cl(REG_EBP); // shr ebp,cl
	1488	_not_r32(REG_EBX); // not ebx
	1489	_not_r32(REG_EBP); // not ebp
	1490	_shrd_r32_r32_cl(REG_EAX, REG_EDX); // shld eax,edx,cl
	1491	_shr_r32_cl(REG_EDX); // shl edx,cl
	1492	_shrd_r32_r32_cl(REG_EAX, REG_EDX); // shld eax,edx,cl
	1493	_shr_r32_cl(REG_EDX); // shl edx,cl
	1494	_and_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // and ebx,[rtreg].lo
	1495	_and_r32_m32bd(REG_EBP, REG_ESI, REGDISP(RTREG)+4); // and ebp,[rtreg].hi
1495	1496	_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
1496		_mov_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)+4); // mov ebx,[rtreg].hi
1497		_and_r32_m32bd(REG_EBX, REG_ECX, ldr_mask); // and ebx,[ldr_mask + ecx]
1498		_or_r32_r32(REG_EDX, REG_EBX); // or edx,ebx
	1497	_or_r32_r32(REG_EDX, REG_EBP); // or edx,ebp
1499	1498	_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1500	1499	}
1501		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1500	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1502	1501	return RECOMPILE_SUCCESSFUL_CP(1,4);
1503	1502
1504	1503	case 0x1c: /* IDT-specific opcodes: mad/madu/mul on R4640/4650, msub on RC32364 */
r894	r895
1510	1509	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1511	1510	_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)); // mov edx,[rtreg]
1512	1511	_imul_r32(REG_EDX); // imul edx
1513		_add_r32_m32abs(REG_EAX, &mips3.core.lo); // add eax,[lo]
1514		_adc_r32_m32abs(REG_EDX, &mips3.core.hi); // adc edx,[hi]
	1512	_add_r32_m32abs(REG_EAX, &mips3.core->lo); // add eax,[lo]
	1513	_adc_r32_m32abs(REG_EDX, &mips3.core->hi); // adc edx,[hi]
1515	1514	_mov_r32_r32(REG_EBX, REG_EDX); // mov ebx,edx
1516	1515	_cdq(); // cdq
1517		_mov_m64abs_r64(&mips3.core.lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
	1516	_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
1518	1517	_mov_r32_r32(REG_EAX, REG_EBX); // mov eax,ebx
1519	1518	_cdq(); // cdq
1520		_mov_m64abs_r64(&mips3.core.hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
	1519	_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
1521	1520	}
1522	1521	return RECOMPILE_SUCCESSFUL_CP(3,4);
1523	1522
r894	r895
1527	1526	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1528	1527	_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)); // mov edx,[rtreg]
1529	1528	_mul_r32(REG_EDX); // mul edx
1530		_add_r32_m32abs(REG_EAX, &mips3.core.lo); // add eax,[lo]
1531		_adc_r32_m32abs(REG_EDX, &mips3.core.hi); // adc edx,[hi]
	1529	_add_r32_m32abs(REG_EAX, &mips3.core->lo); // add eax,[lo]
	1530	_adc_r32_m32abs(REG_EDX, &mips3.core->hi); // adc edx,[hi]
1532	1531	_mov_r32_r32(REG_EBX, REG_EDX); // mov ebx,edx
1533	1532	_cdq(); // cdq
1534		_mov_m64abs_r64(&mips3.core.lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
	1533	_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
1535	1534	_mov_r32_r32(REG_EAX, REG_EBX); // mov eax,ebx
1536	1535	_cdq(); // cdq
1537		_mov_m64abs_r64(&mips3.core.hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
	1536	_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
1538	1537	}
1539	1538	return RECOMPILE_SUCCESSFUL_CP(3,4);
1540	1539
r894	r895
1556	1555	break;
1557	1556
1558	1557	case 0x20: /* LB */
1559		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1558	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1560	1559	_save_pc_before_call(); // save pc
1561	1560	_sub_r32_imm(REG_ESP, 8); // sub esp,8
1562	1561	if (RSREG != 0 && SIMMVAL != 0)
r894	r895
1569	1568	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
1570	1569	else
1571	1570	_push_imm(SIMMVAL); // push SIMMVAL
1572		_call(mips3.drc->read_and_translate_byte_signed); // call read_and_translate_byte_signed
	1571	_call(mips3.drcdata->read_and_translate_byte_signed); // call read_and_translate_byte_signed
1573	1572	_add_r32_imm(REG_ESP, 12); // add esp,12
1574	1573	if (RTREG != 0)
1575	1574	{
1576	1575	_cdq(); // cdq
1577	1576	_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1578	1577	}
1579		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1578	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1580	1579	return RECOMPILE_SUCCESSFUL_CP(1,4);
1581	1580
1582	1581	case 0x21: /* LH */
1583		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1582	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1584	1583	_save_pc_before_call(); // save pc
1585	1584	_sub_r32_imm(REG_ESP, 8); // sub esp,8
1586	1585	if (RSREG != 0 && SIMMVAL != 0)
r894	r895
1593	1592	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
1594	1593	else
1595	1594	_push_imm(SIMMVAL); // push SIMMVAL
1596		_call(mips3.drc->read_and_translate_word_signed); // call read_and_translate_word_signed
	1595	_call(mips3.drcdata->read_and_translate_word_signed); // call read_and_translate_word_signed
1597	1596	_add_r32_imm(REG_ESP, 12); // add esp,12
1598	1597	if (RTREG != 0)
1599	1598	{
1600	1599	_cdq(); // cdq
1601	1600	_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1602	1601	}
1603		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1602	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1604	1603	return RECOMPILE_SUCCESSFUL_CP(1,4);
1605	1604
1606	1605	case 0x22: /* LWL */
1607		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1606	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1608	1607	_save_pc_before_call(); // save pc
1609	1608	_sub_r32_imm(REG_ESP, 4); // sub esp,4
1610	1609	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1611	1610	if (SIMMVAL)
1612	1611	_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1613		_~~push~~_r32(REG_EAX); // ~~push~~ eax
	1612	_lea_r32_m32isd(REG_ECX, REG_EAX, 8, 0); // lea ecx,[eax*8]
1614	1613	_and_r32_imm(REG_EAX, ~3); // and eax,~3
	1614	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1615	if (!mips3.core->bigendian)
	1616	_xor_r32_imm(REG_ECX, 0x18); // xor ecx,0x18
	1617	_shr_r32_cl(REG_EBX); // shr ebx,cl
	1618	_not_r32(REG_EBX); // not ebx
	1619	_push_r32(REG_ECX); // push ecx
	1620	_push_r32(REG_EBX); // push ebx
1615	1621	_push_r32(REG_EAX); // push eax
1616		_call((genf *)mips3.drc->read_and_translate_long); // call read_and_translate_long
1617		_add_r32_imm(REG_ESP, 4); // add esp,4
	1622	_call((genf *)mips3.drcdata->read_and_translate_long_masked); // call read_and_translate_long_masked
	1623	_add_r32_imm(REG_ESP, 8); // add esp,8
1618	1624	_pop_r32(REG_ECX); // pop ecx
1619		_add_r32_imm(REG_ESP, 4); // add esp,4
1620	1625
1621	1626	if (RTREG != 0)
1622	1627	{
1623		_and_r32_imm(REG_ECX, 3); // and ecx,3
1624		_shl_r32_imm(REG_ECX, 3); // shl ecx,3
1625		if (!mips3.core.bigendian)
1626		_xor_r32_imm(REG_ECX, 0x18); // xor ecx,0x18
	1628	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1629	_shl_r32_cl(REG_EBX); // shl ebx,cl
	1630	_not_r32(REG_EBX); // not ebx
1627	1631	_shl_r32_cl(REG_EAX); // shl eax,cl
1628		_mov_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // mov ebx,[rtreg].lo
1629		_and_r32_m32bd(REG_EBX, REG_ECX, ldl_mask + 1); // and ebx,[ldl_mask + ecx + 4]
	1632	_and_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // and ebx,[rtreg].lo
1630	1633	_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
1631	1634	_cdq(); // cdq
1632	1635	_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1633	1636	}
1634		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1637	_add_r32_imm(REG_ESP, 4); // add esp,4
	1638	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1635	1639	return RECOMPILE_SUCCESSFUL_CP(1,4);
1636	1640
1637	1641	case 0x23: /* LW */
1638		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1642	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1639	1643	_save_pc_before_call(); // save pc
1640	1644	_sub_r32_imm(REG_ESP, 8); // sub esp,8
1641	1645	if (RSREG != 0 && SIMMVAL != 0)
r894	r895
1648	1652	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
1649	1653	else
1650	1654	_push_imm(SIMMVAL); // push SIMMVAL
1651		_call(mips3.drc->read_and_translate_long); // call read_and_translate_long
	1655	_call(mips3.drcdata->read_and_translate_long); // call read_and_translate_long
1652	1656	_add_r32_imm(REG_ESP, 12); // add esp,12
1653	1657	if (RTREG != 0)
1654	1658	{
1655	1659	_cdq(); // cdq
1656	1660	_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1657	1661	}
1658		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1662	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1659	1663	return RECOMPILE_SUCCESSFUL_CP(1,4);
1660	1664
1661	1665	case 0x24: /* LBU */
1662		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1666	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1663	1667	_save_pc_before_call(); // save pc
1664	1668	_sub_r32_imm(REG_ESP, 8); // sub esp,8
1665	1669	if (RSREG != 0 && SIMMVAL != 0)
r894	r895
1672	1676	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
1673	1677	else
1674	1678	_push_imm(SIMMVAL); // push SIMMVAL
1675		_call(mips3.drc->read_and_translate_byte_unsigned); // call read_and_translate_byte_unsigned
	1679	_call(mips3.drcdata->read_and_translate_byte_unsigned); // call read_and_translate_byte_unsigned
1676	1680	_add_r32_imm(REG_ESP, 12); // add esp,12
1677	1681	if (RTREG != 0)
1678	1682	{
1679	1683	_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,0
1680	1684	_mov_m32bd_r32(REG_ESI, REGDISP(RTREG), REG_EAX); // mov [rtreg].lo,eax
1681	1685	}
1682		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1686	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1683	1687	return RECOMPILE_SUCCESSFUL_CP(1,4);
1684	1688
1685	1689	case 0x25: /* LHU */
1686		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1690	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1687	1691	_save_pc_before_call(); // save pc
1688	1692	_sub_r32_imm(REG_ESP, 8); // sub esp,8
1689	1693	if (RSREG != 0 && SIMMVAL != 0)
r894	r895
1696	1700	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
1697	1701	else
1698	1702	_push_imm(SIMMVAL); // push SIMMVAL
1699		_call(mips3.drc->read_and_translate_word_unsigned); // call read_and_translate_word_unsigned
	1703	_call(mips3.drcdata->read_and_translate_word_unsigned); // call read_and_translate_word_unsigned
1700	1704	_add_r32_imm(REG_ESP, 12); // add esp,12
1701	1705	if (RTREG != 0)
1702	1706	{
1703	1707	_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,0
1704	1708	_mov_m32bd_r32(REG_ESI, REGDISP(RTREG), REG_EAX); // mov [rtreg].lo,eax
1705	1709	}
1706		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1710	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1707	1711	return RECOMPILE_SUCCESSFUL_CP(1,4);
1708	1712
1709	1713	case 0x26: /* LWR */
1710		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1714	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1711	1715	_save_pc_before_call(); // save pc
1712	1716	_sub_r32_imm(REG_ESP, 4); // sub esp,4
1713	1717	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1714	1718	if (SIMMVAL)
1715	1719	_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1716		_~~push~~_r32(REG_EAX); // ~~push~~ eax
	1720	_lea_r32_m32isd(REG_ECX, REG_EAX, 8, 0); // lea ecx,[eax*8]
1717	1721	_and_r32_imm(REG_EAX, ~3); // and eax,~3
	1722	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1723	if (mips3.core->bigendian)
	1724	_xor_r32_imm(REG_ECX, 0x18); // xor ecx,0x18
	1725	_shl_r32_cl(REG_EBX); // shl ebx,cl
	1726	_not_r32(REG_EBX); // not ebx
	1727	_push_r32(REG_ECX); // push ecx
	1728	_push_r32(REG_EBX); // push ebx
1718	1729	_push_r32(REG_EAX); // push eax
1719		_call((genf *)mips3.drc->read_and_translate_long); // call read_and_translate_long
1720		_add_r32_imm(REG_ESP, 4); // add esp,4
	1730	_call((genf *)mips3.drcdata->read_and_translate_long_masked); // call read_and_translate_long_masked
	1731	_add_r32_imm(REG_ESP, 8); // add esp,8
1721	1732	_pop_r32(REG_ECX); // pop ecx
1722		_add_r32_imm(REG_ESP, 4); // add esp,4
1723	1733
1724	1734	if (RTREG != 0)
1725	1735	{
1726		_and_r32_imm(REG_ECX, 3); // and ecx,3
1727		_shl_r32_imm(REG_ECX, 3); // shl ecx,3
1728		if (mips3.core.bigendian)
1729		_xor_r32_imm(REG_ECX, 0x18); // xor ecx,0x18
	1736	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1737	_shr_r32_cl(REG_EBX); // shr ebx,cl
	1738	_not_r32(REG_EBX); // not ebx
1730	1739	_shr_r32_cl(REG_EAX); // shr eax,cl
1731		_mov_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // mov ebx,[rtreg].lo
1732		_and_r32_m32bd(REG_EBX, REG_ECX, ldr_mask); // and ebx,[ldr_mask + ecx]
	1740	_and_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // and ebx,[rtreg].lo
1733	1741	_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
1734	1742	_cdq(); // cdq
1735	1743	_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
1736	1744	}
1737		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1745	_add_r32_imm(REG_ESP, 4); // add esp,4
	1746	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1738	1747	return RECOMPILE_SUCCESSFUL_CP(1,4);
1739	1748
1740	1749	case 0x27: /* LWU */
1741		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1750	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1742	1751	_save_pc_before_call(); // save pc
1743	1752	_sub_r32_imm(REG_ESP, 8); // sub esp,8
1744	1753	if (RSREG != 0 && SIMMVAL != 0)
r894	r895
1751	1760	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
1752	1761	else
1753	1762	_push_imm(SIMMVAL); // push SIMMVAL
1754		_call(mips3.drc->read_and_translate_long); // call read_and_translate_long
	1763	_call(mips3.drcdata->read_and_translate_long); // call read_and_translate_long
1755	1764	_add_r32_imm(REG_ESP, 12); // add esp,12
1756	1765	if (RTREG != 0)
1757	1766	{
1758	1767	_mov_m32bd_imm(REG_ESI, REGDISP(RTREG)+4, 0); // mov [rtreg].hi,0
1759	1768	_mov_m32bd_r32(REG_ESI, REGDISP(RTREG), REG_EAX); // mov [rtreg].lo,eax
1760	1769	}
1761		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1770	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1762	1771	return RECOMPILE_SUCCESSFUL_CP(1,4);
1763	1772
1764	1773	case 0x28: /* SB */
1765		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1774	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1766	1775	_save_pc_before_call(); // save pc
1767	1776	_sub_r32_imm(REG_ESP, 4); // sub esp,4
1768	1777	if (RTREG != 0)
r894	r895
1779	1788	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
1780	1789	else
1781	1790	_push_imm(SIMMVAL); // push SIMMVAL
1782		_call(mips3.drc->write_and_translate_byte); // call writebyte
	1791	_call(mips3.drcdata->write_and_translate_byte); // call writebyte
1783	1792	_add_r32_imm(REG_ESP, 12); // add esp,12
1784		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1793	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1785	1794	return RECOMPILE_SUCCESSFUL_CP(1,4);
1786	1795
1787	1796	case 0x29: /* SH */
1788		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1797	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1789	1798	_save_pc_before_call(); // save pc
1790	1799	_sub_r32_imm(REG_ESP, 4); // sub esp,4
1791	1800	if (RTREG != 0)
r894	r895
1802	1811	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
1803	1812	else
1804	1813	_push_imm(SIMMVAL); // push SIMMVAL
1805		_call(mips3.drc->write_and_translate_word); // call writeword
	1814	_call(mips3.drcdata->write_and_translate_word); // call writeword
1806	1815	_add_r32_imm(REG_ESP, 12); // add esp,12
1807		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1816	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1808	1817	return RECOMPILE_SUCCESSFUL_CP(1,4);
1809	1818
1810	1819	case 0x2a: /* SWL */
1811		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1820	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1812	1821	_save_pc_before_call(); // save pc
1813	1822	_sub_r32_imm(REG_ESP, 4); // sub esp,4
1814	1823	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1815	1824	if (SIMMVAL)
1816	1825	_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1817		_~~push~~_r32(REG_EAX); // ~~push~~ eax
	1826	_lea_r32_m32isd(REG_ECX, REG_EAX, 8, 0); // lea ecx,[eax*8]
1818	1827	_and_r32_imm(REG_EAX, ~3); // and eax,~3
1819		_push_r32(REG_EAX); // push eax
1820		_call((genf *)mips3.drc->read_and_translate_long); // call read_and_translate_long
1821		_mov_r32_m32bd(REG_ECX, REG_ESP, 4); // mov ecx,[esp+4]
1822		_add_r32_imm(REG_ESP, 8); // add esp,8
1823
1824		_and_r32_imm(REG_ECX, 3); // and ecx,3
1825		_shl_r32_imm(REG_ECX, 3); // shl ecx,3
1826		if (!mips3.core.bigendian)
	1828	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1829	if (!mips3.core->bigendian)
1827	1830	_xor_r32_imm(REG_ECX, 0x18); // xor ecx,0x18
1828
1829		_and_r32_m32bd(REG_EAX, REG_ECX, sdl_mask); // and eax,[sdl_mask + ecx]
1830
	1831	_shr_r32_cl(REG_EBX); // shr ebx,cl
	1832	_not_r32(REG_EBX); // not ebx
	1833	_push_r32(REG_EBX); // push ebx
1831	1834	if (RTREG != 0)
1832	1835	{
1833	1836	_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)); // mov edx,[rtreg]
1834	1837	_shr_r32_cl(REG_EDX); // shr edx,cl
1835		_or_r32~~_r32~~(REG_E~~AX, REG_E~~DX); // or ~~eax,~~edx
	1838	_push_r32(REG_EDX); // push edx
1836	1839	}
1837
	1840	else
	1841	_push_imm(0); // push 0
1838	1842	_push_r32(REG_EAX); // push eax
1839		_push_r32(REG_EBX); // push ebx
1840		_call((genf *)mips3.drc->write_back_long); // call writelong
1841		_add_r32_imm(REG_ESP, 12); // add esp,12
1842
1843		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1843	_call((genf *)mips3.drcdata->write_and_translate_long_masked); // call write_and_translate_long_masked
	1844	_add_r32_imm(REG_ESP, 16); // add esp,16
	1845	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1844	1846	return RECOMPILE_SUCCESSFUL_CP(1,4);
1845	1847
1846	1848	case 0x2b: /* SW */
1847		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1849	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1848	1850	_save_pc_before_call(); // save pc
1849	1851	_sub_r32_imm(REG_ESP, 4); // sub esp,4
1850	1852	if (RTREG != 0)
r894	r895
1861	1863	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
1862	1864	else
1863	1865	_push_imm(SIMMVAL); // push SIMMVAL
1864		_call(mips3.drc->write_and_translate_long); // call write_and_translate_long
	1866	_call(mips3.drcdata->write_and_translate_long); // call write_and_translate_long
1865	1867	_add_r32_imm(REG_ESP, 12); // add esp,12
1866		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1868	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1867	1869	return RECOMPILE_SUCCESSFUL_CP(1,4);
1868	1870
1869	1871	case 0x2c: /* SDL */
1870		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1872	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1871	1873	_save_pc_before_call(); // save pc
1872		_sub_r32_imm(REG_ESP, 4); // sub esp,4
	1874	_sub_r32_imm(REG_ESP, 12); // sub esp,12
1873	1875	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1874	1876	if (SIMMVAL)
1875	1877	_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1876		_~~push~~_r32(REG_EAX); // ~~push~~ eax
	1878	_lea_r32_m32isd(REG_ECX, REG_EAX, 4, 0); // lea ecx,[eax*4]
1877	1879	_and_r32_imm(REG_EAX, ~7); // and eax,~7
1878		_push_r32(REG_EAX); // push eax
1879		_call((genf *)mips3.drc->read_and_translate_double); // call read_and_translate_double
1880		_add_r32_imm(REG_ESP, 4); // add esp,4
1881		_pop_r32(REG_ECX); // pop ecx
1882		_add_r32_imm(REG_ESP, 4); // add esp,4
1883
1884		_and_r32_imm(REG_ECX, 7); // and ecx,7
1885		_shl_r32_imm(REG_ECX, 3); // shl ecx,3
1886		if (!mips3.core.bigendian)
1887		_xor_r32_imm(REG_ECX, 0x38); // xor ecx,0x38
1888
1889		_and_r32_m32bd(REG_EAX, REG_ECX, sdl_mask + 1); // and eax,[sdl_mask + ecx + 4]
1890		_and_r32_m32bd(REG_EDX, REG_ECX, sdl_mask); // and eax,[sdl_mask + ecx]
1891
	1880	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1881	_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
	1882	if (!mips3.core->bigendian)
	1883	_xor_r32_imm(REG_ECX, 0x1c); // xor ecx,0x1c
	1884	_shr_r32_cl(REG_EBP); // shr ebp,cl
	1885	_shrd_r32_r32_cl(REG_EBX, REG_EBP); // shrd ebx,ebp,cl
	1886	_shr_r32_cl(REG_EBP); // shr ebp,cl
	1887	_not_r32(REG_EBP); // not ebp
	1888	_not_r32(REG_EBX); // not ebx
	1889	_push_r32(REG_EBP); // push ebp
	1890	_push_r32(REG_EBX); // push ebx
1892	1891	if (RTREG != 0)
1893	1892	{
	1893	_mov_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // mov ebx,[rtreg].lo
	1894	_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // mov edx,[rtreg].hi
	1895	_shrd_r32_r32_cl(REG_EBX, REG_EDX); // shrd ebx,edx,cl
	1896	_shr_r32_cl(REG_EDX); // shr edx,cl
	1897	_shrd_r32_r32_cl(REG_EBX, REG_EDX); // shrd ebx,edx,cl
	1898	_shr_r32_cl(REG_EDX); // shr edx,cl
	1899	_push_r32(REG_EDX); // push edx
1894	1900	_push_r32(REG_EBX); // push ebx
1895		_push_r32(REG_ESI); // push esi
1896		_test_r32_imm(REG_ECX, 0x20); // test ecx,0x20
1897		_mov_r64_m64abs(REG_ESI, REG_EBX, &mips3.core.r[RTREG]); // mov esi:ebx,[rtreg]
1898		_jcc_short_link(COND_Z, &link1); // jz skip
1899		_mov_r32_r32(REG_EBX, REG_ESI); // mov ebx,esi
1900		_xor_r32_r32(REG_ESI, REG_ESI); // xor esi,esi
1901		_resolve_link(&link1); // skip:
1902		_shrd_r32_r32_cl(REG_EBX, REG_ESI); // shrd ebx,esi,cl
1903		_shr_r32_cl(REG_ESI); // shr esi,cl
1904		_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
1905		_or_r32_r32(REG_EDX, REG_ESI); // or edx,esi
1906		_pop_r32(REG_ESI); // pop esi
1907		_pop_r32(REG_EBX); // pop ebx
1908	1901	}
1909
1910		_push_r32(REG_EDX); // push edx
	1902	else
	1903	{
	1904	_push_imm(0); // push 0
	1905	_push_imm(0); // push 0
	1906	}
1911	1907	_push_r32(REG_EAX); // push eax
1912		_push_r32(REG_EBX); // push ebx
1913		_call((genf *)mips3.drc->write_back_double); // call write_back_double
1914		_add_r32_imm(REG_ESP, 12); // add esp,12
1915
1916		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1908	_call((genf *)mips3.drcdata->write_and_translate_double_masked); // call write_and_translate_double_masked
	1909	_add_r32_imm(REG_ESP, 32); // add esp,32
	1910	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1917	1911	return RECOMPILE_SUCCESSFUL_CP(1,4);
1918	1912
1919	1913	case 0x2d: /* SDR */
1920		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1914	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1921	1915	_save_pc_before_call(); // save pc
1922		_sub_r32_imm(REG_ESP, 4); // sub esp,4
	1916	_sub_r32_imm(REG_ESP, 12); // sub esp,12
1923	1917	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1924	1918	if (SIMMVAL)
1925	1919	_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1926		_~~push~~_r32(REG_EAX); // ~~push~~ eax
	1920	_lea_r32_m32isd(REG_ECX, REG_EAX, 4, 0); // lea ecx,[eax*4]
1927	1921	_and_r32_imm(REG_EAX, ~7); // and eax,~7
1928		_push_r32(REG_EAX); // push eax
1929		_call((genf *)mips3.drc->read_and_translate_double); // call read_and_translate_double
1930		_add_r32_imm(REG_ESP, 4); // add esp,4
1931		_pop_r32(REG_ECX); // pop ecx
1932		_add_r32_imm(REG_ESP, 4); // add esp,4
1933
1934		_and_r32_imm(REG_ECX, 7); // and ecx,7
1935		_shl_r32_imm(REG_ECX, 3); // shl ecx,3
1936		if (mips3.core.bigendian)
1937		_xor_r32_imm(REG_ECX, 0x38); // xor ecx,0x38
1938
1939		_and_r32_m32bd(REG_EAX, REG_ECX, sdr_mask + 1); // and eax,[sdr_mask + ecx + 4]
1940		_and_r32_m32bd(REG_EDX, REG_ECX, sdr_mask); // and eax,[sdr_mask + ecx]
1941
	1922	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1923	_mov_r32_imm(REG_EBP, -1); // mov ebp,-1
	1924	if (mips3.core->bigendian)
	1925	_xor_r32_imm(REG_ECX, 0x1c); // xor ecx,0x1c
	1926	_shl_r32_cl(REG_EBX); // shl ebx,cl
	1927	_shld_r32_r32_cl(REG_EBP, REG_EBX); // shld ebp,ebx,cl
	1928	_shl_r32_cl(REG_EBX); // shl ebx,cl
	1929	_not_r32(REG_EBP); // not ebp
	1930	_not_r32(REG_EBX); // not ebx
	1931	_push_r32(REG_EBP); // push ebp
	1932	_push_r32(REG_EBX); // push ebx
1942	1933	if (RTREG != 0)
1943	1934	{
1944		_push_r32(REG_EBX); // push ebx
1945		_push_r32(REG_ESI); // push esi
1946		_test_r32_imm(REG_ECX, 0x20); // test ecx,0x20
1947		_mov_r64_m64abs(REG_ESI, REG_EBX, &mips3.core.r[RTREG]); // mov esi:ebx,[rtreg]
1948		_jcc_short_link(COND_Z, &link1); // jz skip
1949		_mov_r32_r32(REG_ESI, REG_EBX); // mov esi,ebx
1950		_xor_r32_r32(REG_EBX, REG_EBX); // xor ebx,ebx
1951		_resolve_link(&link1); // skip:
1952		_shld_r32_r32_cl(REG_ESI, REG_EBX); // shld esi,ebx,cl
	1935	_mov_r32_m32bd(REG_EBX, REG_ESI, REGDISP(RTREG)); // mov ebx,[rtreg].lo
	1936	_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // mov edx,[rtreg].hi
	1937	_shld_r32_r32_cl(REG_EDX, REG_EBX); // shld edx,ebx,cl
1953	1938	_shl_r32_cl(REG_EBX); // shl ebx,cl
1954		_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
1955		_or_r32_r32(REG_EDX, REG_ESI); // or edx,esi
1956		_pop_r32(REG_ESI); // pop esi
1957		_pop_r32(REG_EBX); // pop ebx
	1939	_shld_r32_r32_cl(REG_EDX, REG_EBX); // shld edx,ebx,cl
	1940	_shl_r32_cl(REG_EBX); // shl ebx,cl
	1941	_push_r32(REG_EDX); // push edx
	1942	_push_r32(REG_EBX); // push ebx
1958	1943	}
1959
1960		_push_r32(REG_EDX); // push edx
	1944	else
	1945	{
	1946	_push_imm(0); // push 0
	1947	_push_imm(0); // push 0
	1948	}
1961	1949	_push_r32(REG_EAX); // push eax
1962		_push_r32(REG_EBX); // push ebx
1963		_call((genf *)mips3.drc->write_back_double); // call write_back_double
1964		_add_r32_imm(REG_ESP, 12); // add esp,12
1965
1966		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1950	_call((genf *)mips3.drcdata->write_and_translate_double_masked); // call write_and_translate_double_masked
	1951	_add_r32_imm(REG_ESP, 32); // add esp,32
	1952	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
1967	1953	return RECOMPILE_SUCCESSFUL_CP(1,4);
1968	1954
1969	1955	case 0x2e: /* SWR */
1970		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1956	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
1971	1957	_save_pc_before_call(); // save pc
1972		_sub_r32_imm(REG_ESP, 4); // ~~add~~ esp,4
	1958	_sub_r32_imm(REG_ESP, 4); // sub esp,4
1973	1959	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
1974	1960	if (SIMMVAL)
1975	1961	_add_r32_imm(REG_EAX, SIMMVAL); // add eax,SIMMVAL
1976		_~~push~~_r32(REG_EAX); // ~~push~~ eax
	1962	_lea_r32_m32isd(REG_ECX, REG_EAX, 8, 0); // lea ecx,[eax*8]
1977	1963	_and_r32_imm(REG_EAX, ~3); // and eax,~3
1978		_push_r32(REG_EAX); // push eax
1979		_call((genf *)mips3.drc->read_and_translate_long); // call read_and_translate_long
1980		_mov_r32_m32bd(REG_ECX, REG_ESP, 4); // mov ecx,[esp+4]
1981		_add_r32_imm(REG_ESP, 8); // add esp,8
1982
1983		_and_r32_imm(REG_ECX, 3); // and ecx,3
1984		_shl_r32_imm(REG_ECX, 3); // shl ecx,3
1985		if (mips3.core.bigendian)
	1964	_mov_r32_imm(REG_EBX, -1); // mov ebx,-1
	1965	if (mips3.core->bigendian)
1986	1966	_xor_r32_imm(REG_ECX, 0x18); // xor ecx,0x18
1987
1988		_and_r32_m32bd(REG_EAX, REG_ECX, sdr_mask + 1); // and eax,[sdr_mask + ecx + 4]
1989
	1967	_shl_r32_cl(REG_EBX); // shl ebx,cl
	1968	_not_r32(REG_EBX); // not ebx
	1969	_push_r32(REG_EBX); // push ebx
1990	1970	if (RTREG != 0)
1991	1971	{
1992	1972	_mov_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)); // mov edx,[rtreg]
1993	1973	_shl_r32_cl(REG_EDX); // shl edx,cl
1994		_or_r32~~_r32~~(REG_E~~AX, REG_E~~DX); // or ~~eax,~~edx
	1974	_push_r32(REG_EDX); // push edx
1995	1975	}
1996
	1976	else
	1977	_push_imm(0); // push 0
1997	1978	_push_r32(REG_EAX); // push eax
1998		_push_r32(REG_EBX); // push ebx
1999		_call((genf *)mips3.drc->write_back_long); // call write_back_long
2000		_add_r32_imm(REG_ESP, 12); // add esp,12
2001
2002		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	1979	_call((genf *)mips3.drcdata->write_and_translate_long_masked); // call write_and_translate_long_masked
	1980	_add_r32_imm(REG_ESP, 16); // add esp,16
	1981	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
2003	1982	return RECOMPILE_SUCCESSFUL_CP(1,4);
2004	1983
2005	1984	case 0x2f: /* CACHE */
r894	r895
2008	1987	// case 0x30: /* LL */ logerror("mips3 Unhandled op: LL\n"); break;
2009	1988
2010	1989	case 0x31: /* LWC1 */
2011		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	1990	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2012	1991	_save_pc_before_call(); // save pc
2013	1992	_sub_r32_imm(REG_ESP, 8); // sub esp,8
2014	1993	if (RSREG != 0 && SIMMVAL != 0)
r894	r895
2021	2000	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
2022	2001	else
2023	2002	_push_imm(SIMMVAL); // push SIMMVAL
2024		_call(mips3.drc->read_and_translate_long); // call read_and_translate_long
	2003	_call(mips3.drcdata->read_and_translate_long); // call read_and_translate_long
2025	2004	_add_r32_imm(REG_ESP, 12); // add esp,12
2026	2005	_mov_m32abs_r32(FPR32(RTREG), REG_EAX); // mov [rtreg],eax
2027		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	2006	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
2028	2007	return RECOMPILE_SUCCESSFUL_CP(1,4);
2029	2008
2030	2009	case 0x32: /* LWC2 */
2031		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	2010	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2032	2011	_save_pc_before_call(); // save pc
2033	2012	_sub_r32_imm(REG_ESP, 8); // sub esp,8
2034	2013	if (RSREG != 0 && SIMMVAL != 0)
r894	r895
2041	2020	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
2042	2021	else
2043	2022	_push_imm(SIMMVAL); // push SIMMVAL
2044		_call(mips3.drc->read_and_translate_long); // call read_and_translate_long
	2023	_call(mips3.drcdata->read_and_translate_long); // call read_and_translate_long
2045	2024	_add_r32_imm(REG_ESP, 12); // add esp,12
2046		_mov_m32abs_r32(&mips3.core.cpr[2][RTREG], REG_EAX); // mov [rtreg],eax
2047		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	2025	_mov_m32abs_r32(&mips3.core->cpr[2][RTREG], REG_EAX); // mov [rtreg],eax
	2026	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
2048	2027	return RECOMPILE_SUCCESSFUL_CP(1,4);
2049	2028
2050	2029	case 0x33: /* PREF */
2051		if (mips3.core.flavor >= MIPS3_TYPE_MIPS_IV)
	2030	if (mips3.core->flavor >= MIPS3_TYPE_MIPS_IV)
2052	2031	return RECOMPILE_SUCCESSFUL_CP(1,4);
2053	2032	else
2054	2033	{
2055		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	2034	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
2056	2035	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2057	2036	}
2058	2037
2059	2038	// case 0x34: /* LLD */ logerror("mips3 Unhandled op: LLD\n"); break;
2060	2039
2061	2040	case 0x35: /* LDC1 */
2062		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	2041	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2063	2042	_save_pc_before_call(); // save pc
2064	2043	_sub_r32_imm(REG_ESP, 8); // sub esp,8
2065	2044	if (RSREG != 0 && SIMMVAL != 0)
r894	r895
2072	2051	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
2073	2052	else
2074	2053	_push_imm(SIMMVAL); // push SIMMVAL
2075		_call((genf *)mips3.drc->read_and_translate_double); // call read_and_translate_double
	2054	_call((genf *)mips3.drcdata->read_and_translate_double); // call read_and_translate_double
2076	2055	_mov_m32abs_r32(LO(FPR64(RTREG)), REG_EAX); // mov [rtreg].lo,eax
2077	2056	_mov_m32abs_r32(HI(FPR64(RTREG)), REG_EDX); // mov [rtreg].hi,edx
2078	2057	_add_r32_imm(REG_ESP, 12); // add esp,12
2079		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	2058	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
2080	2059	return RECOMPILE_SUCCESSFUL_CP(1,4);
2081	2060
2082	2061	case 0x36: /* LDC2 */
2083		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	2062	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2084	2063	_save_pc_before_call(); // save pc
2085	2064	_sub_r32_imm(REG_ESP, 8); // sub esp,8
2086	2065	if (RSREG != 0 && SIMMVAL != 0)
r894	r895
2093	2072	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
2094	2073	else
2095	2074	_push_imm(SIMMVAL); // push SIMMVAL
2096		_call((genf *)mips3.drc->read_and_translate_double); // call read_and_translate_long
2097		_mov_m32abs_r32(LO(&mips3.core.cpr[2][RTREG]), REG_EAX); // mov [rtreg].lo,eax
2098		_mov_m32abs_r32(HI(&mips3.core.cpr[2][RTREG]), REG_EDX); // mov [rtreg].hi,edx
	2075	_call((genf *)mips3.drcdata->read_and_translate_double); // call read_and_translate_long
	2076	_mov_m32abs_r32(LO(&mips3.core->cpr[2][RTREG]), REG_EAX); // mov [rtreg].lo,eax
	2077	_mov_m32abs_r32(HI(&mips3.core->cpr[2][RTREG]), REG_EDX); // mov [rtreg].hi,edx
2099	2078	_add_r32_imm(REG_ESP, 12); // add esp,12
2100		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	2079	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
2101	2080	return RECOMPILE_SUCCESSFUL_CP(1,4);
2102	2081
2103	2082	case 0x37: /* LD */
2104		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	2083	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2105	2084	_save_pc_before_call(); // save pc
2106	2085	_sub_r32_imm(REG_ESP, 8); // sub esp,8
2107	2086	if (RSREG != 0 && SIMMVAL != 0)
r894	r895
2114	2093	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
2115	2094	else
2116	2095	_push_imm(SIMMVAL); // push SIMMVAL
2117		_call((genf *)mips3.drc->read_and_translate_double); // call read_and_translate_double
	2096	_call((genf *)mips3.drcdata->read_and_translate_double); // call read_and_translate_double
2118	2097	if (RTREG != 0)
2119	2098	{
2120	2099	_mov_m32bd_r32(REG_ESI, REGDISP(RTREG), REG_EAX); // mov [rtreg].lo,eax
r894	r895
2122	2101	}
2123	2102
2124	2103	_add_r32_imm(REG_ESP, 12); // add esp,12
2125		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	2104	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
2126	2105	return RECOMPILE_SUCCESSFUL_CP(1,4);
2127	2106
2128	2107	// case 0x38: /* SC */ logerror("mips3 Unhandled op: SC\n"); break;
2129	2108
2130	2109	case 0x39: /* SWC1 */
2131		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	2110	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2132	2111	_save_pc_before_call(); // save pc
2133	2112	_sub_r32_imm(REG_ESP, 4); // sub esp,4
2134	2113	_push_m32abs(FPR32(RTREG)); // push dword [rtreg]
r894	r895
2142	2121	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
2143	2122	else
2144	2123	_push_imm(SIMMVAL); // push SIMMVAL
2145		_call(mips3.drc->write_and_translate_long); // call write_and_translate_long
	2124	_call(mips3.drcdata->write_and_translate_long); // call write_and_translate_long
2146	2125	_add_r32_imm(REG_ESP, 12); // add esp,12
2147		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	2126	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
2148	2127	return RECOMPILE_SUCCESSFUL_CP(1,4);
2149	2128
2150	2129	case 0x3a: /* SWC2 */
2151		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	2130	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2152	2131	_save_pc_before_call(); // save pc
2153	2132	_sub_r32_imm(REG_ESP, 4); // sub esp,4
2154		_push_m32abs(&mips3.core.cpr[2][RTREG]); // push dword [rtreg]
	2133	_push_m32abs(&mips3.core->cpr[2][RTREG]); // push dword [rtreg]
2155	2134	if (RSREG != 0 && SIMMVAL != 0)
2156	2135	{
2157	2136	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
r894	r895
2162	2141	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
2163	2142	else
2164	2143	_push_imm(SIMMVAL); // push SIMMVAL
2165		_call(mips3.drc->write_and_translate_long); // call write_and_translate_long
	2144	_call(mips3.drcdata->write_and_translate_long); // call write_and_translate_long
2166	2145	_add_r32_imm(REG_ESP, 12); // add esp,12
2167		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	2146	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
2168	2147	return RECOMPILE_SUCCESSFUL_CP(1,4);
2169	2148
2170	2149	// case 0x3b: /* SWC3 */ invalid_instruction(op); break;
2171	2150	// case 0x3c: /* SCD */ logerror("mips3 Unhandled op: SCD\n"); break;
2172	2151
2173	2152	case 0x3d: /* SDC1 */
2174		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	2153	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2175	2154	_save_pc_before_call(); // save pc
2176	2155	_push_m32abs(HI(FPR64(RTREG))); // push dword [rtreg].hi
2177	2156	_push_m32abs(LO(FPR64(RTREG))); // push dword [rtreg].lo
r894	r895
2185	2164	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
2186	2165	else
2187	2166	_push_imm(SIMMVAL); // push SIMMVAL
2188		_call((genf *)mips3.drc->write_and_translate_double); // call write_and_translate_double
	2167	_call((genf *)mips3.drcdata->write_and_translate_double); // call write_and_translate_double
2189	2168	_add_r32_imm(REG_ESP, 12); // add esp,12
2190		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	2169	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
2191	2170	return RECOMPILE_SUCCESSFUL_CP(1,4);
2192	2171
2193	2172	case 0x3e: /* SDC2 */
2194		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	2173	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2195	2174	_save_pc_before_call(); // save pc
2196		_push_m32abs(HI(&mips3.core.cpr[2][RTREG])); // push dword [rtreg].hi
2197		_push_m32abs(LO(&mips3.core.cpr[2][RTREG])); // push dword [rtreg].lo
	2175	_push_m32abs(HI(&mips3.core->cpr[2][RTREG])); // push dword [rtreg].hi
	2176	_push_m32abs(LO(&mips3.core->cpr[2][RTREG])); // push dword [rtreg].lo
2198	2177	if (RSREG != 0 && SIMMVAL != 0)
2199	2178	{
2200	2179	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
r894	r895
2205	2184	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
2206	2185	else
2207	2186	_push_imm(SIMMVAL); // push SIMMVAL
2208		_call((genf *)mips3.drc->write_and_translate_double); // call write_and_translate_double
	2187	_call((genf *)mips3.drcdata->write_and_translate_double); // call write_and_translate_double
2209	2188	_add_r32_imm(REG_ESP, 12); // add esp,12
2210		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	2189	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
2211	2190	return RECOMPILE_SUCCESSFUL_CP(1,4);
2212	2191
2213	2192	case 0x3f: /* SD */
2214		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	2193	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
2215	2194	_save_pc_before_call(); // save pc
2216	2195	if (RTREG != 0)
2217	2196	{
r894	r895
2233	2212	_push_m32bd(REG_ESI, REGDISP(RSREG)); // push [rsreg]
2234	2213	else
2235	2214	_push_imm(SIMMVAL); // push SIMMVAL
2236		_call((genf *)mips3.drc->write_and_translate_double); // call write_and_translate_double
	2215	_call((genf *)mips3.drcdata->write_and_translate_double); // call write_and_translate_double
2237	2216	_add_r32_imm(REG_ESP, 12); // add esp,12
2238		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	2217	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
2239	2218	return RECOMPILE_SUCCESSFUL_CP(1,4);
2240	2219
2241	2220	// default: /* ??? */ invalid_instruction(op); break;
r894	r895
2272	2251	return RECOMPILE_SUCCESSFUL_CP(1,4);
2273	2252
2274	2253	case 0x01: /* MOVF - R5000*/
2275		if (mips3.core.flavor < MIPS3_TYPE_MIPS_IV)
	2254	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
2276	2255	{
2277		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	2256	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
2278	2257	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2279	2258	}
2280		_cmp_m8abs_imm(&mips3.core.cf[1][(op >> 18) & 7], 0); // cmp [cf[x]],0
	2259	_cmp_m8abs_imm(&mips3.core->cf[1][(op >> 18) & 7], 0); // cmp [cf[x]],0
2281	2260	_jcc_short_link(((op >> 16) & 1) ? COND_Z : COND_NZ, &link1); // jz/nz skip
2282	2261	_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
2283	2262	_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
r894	r895
2388	2367	return RECOMPILE_SUCCESSFUL_CP(1+cycles,0) \| RECOMPILE_END_OF_STRING \| RECOMPILE_ADD_DISPATCH;
2389	2368
2390	2369	case 0x0a: /* MOVZ - R5000 */
2391		if (mips3.core.flavor < MIPS3_TYPE_MIPS_IV)
	2370	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
2392	2371	{
2393		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	2372	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
2394	2373	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2395	2374	}
2396	2375	if (RDREG != 0)
r894	r895
2404	2383	return RECOMPILE_SUCCESSFUL_CP(1,4);
2405	2384
2406	2385	case 0x0b: /* MOVN - R5000 */
2407		if (mips3.core.flavor < MIPS3_TYPE_MIPS_IV)
	2386	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
2408	2387	{
2409		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	2388	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
2410	2389	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2411	2390	}
2412	2391	if (RDREG != 0)
r894	r895
2420	2399	return RECOMPILE_SUCCESSFUL_CP(1,4);
2421	2400
2422	2401	case 0x0c: /* SYSCALL */
2423		_jmp((void *)mips3.drc->generate_syscall_exception); // jmp generate_syscall_exception
	2402	_jmp((void *)mips3.drcdata->generate_syscall_exception); // jmp generate_syscall_exception
2424	2403	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2425	2404
2426	2405	case 0x0d: /* BREAK */
2427		_jmp((void *)mips3.drc->generate_break_exception); // jmp generate_break_exception
	2406	_jmp((void *)mips3.drcdata->generate_break_exception); // jmp generate_break_exception
2428	2407	return RECOMPILE_SUCCESSFUL \| RECOMPILE_MAY_CAUSE_EXCEPTION \| RECOMPILE_END_OF_STRING;
2429	2408
2430	2409	case 0x0f: /* SYNC */
r894	r895
2432	2411
2433	2412	case 0x10: /* MFHI */
2434	2413	if (RDREG != 0)
2435		_mov_m64bd_m64abs(REG_ESI, REGDISP(RDREG), &mips3.core.hi); // mov [rdreg],[hi]
	2414	_mov_m64bd_m64abs(REG_ESI, REGDISP(RDREG), &mips3.core->hi); // mov [rdreg],[hi]
2436	2415	return RECOMPILE_SUCCESSFUL_CP(1,4);
2437	2416
2438	2417	case 0x11: /* MTHI */
2439		_mov_m64abs_m64bd(&mips3.core.hi, REG_ESI, REGDISP(RSREG)); // mov [hi],[rsreg]
	2418	_mov_m64abs_m64bd(&mips3.core->hi, REG_ESI, REGDISP(RSREG)); // mov [hi],[rsreg]
2440	2419	return RECOMPILE_SUCCESSFUL_CP(1,4);
2441	2420
2442	2421	case 0x12: /* MFLO */
2443	2422	if (RDREG != 0)
2444		_mov_m64bd_m64abs(REG_ESI, REGDISP(RDREG), &mips3.core.lo); // mov [rdreg],[lo]
	2423	_mov_m64bd_m64abs(REG_ESI, REGDISP(RDREG), &mips3.core->lo); // mov [rdreg],[lo]
2445	2424	return RECOMPILE_SUCCESSFUL_CP(1,4);
2446	2425
2447	2426	case 0x13: /* MTLO */
2448		_mov_m64abs_m64bd(&mips3.core.lo, REG_ESI, REGDISP(RSREG)); // mov [lo],[rsreg]
	2427	_mov_m64abs_m64bd(&mips3.core->lo, REG_ESI, REGDISP(RSREG)); // mov [lo],[rsreg]
2449	2428	return RECOMPILE_SUCCESSFUL_CP(1,4);
2450	2429
2451	2430	case 0x14: /* DSLLV */
r894	r895
2526	2505	_imul_r32(REG_ECX); // imul ecx
2527	2506	_push_r32(REG_EDX); // push edx
2528	2507	_cdq(); // cdq
2529		_mov_m64abs_r64(&mips3.core.lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
	2508	_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
2530	2509	_pop_r32(REG_EAX); // pop eax
2531	2510	_cdq(); // cdq
2532		_mov_m64abs_r64(&mips3.core.hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
	2511	_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
2533	2512	return RECOMPILE_SUCCESSFUL_CP(4,4);
2534	2513
2535	2514	case 0x19: /* MULTU */
r894	r895
2538	2517	_mul_r32(REG_ECX); // mul ecx
2539	2518	_push_r32(REG_EDX); // push edx
2540	2519	_cdq(); // cdq
2541		_mov_m64abs_r64(&mips3.core.lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
	2520	_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
2542	2521	_pop_r32(REG_EAX); // pop eax
2543	2522	_cdq(); // cdq
2544		_mov_m64abs_r64(&mips3.core.hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
	2523	_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
2545	2524	return RECOMPILE_SUCCESSFUL_CP(4,4);
2546	2525
2547	2526	case 0x1a: /* DIV */
r894	r895
2555	2534	_idiv_r32(REG_ECX); // idiv ecx
2556	2535	_push_r32(REG_EDX); // push edx
2557	2536	_cdq(); // cdq
2558		_mov_m64abs_r64(&mips3.core.lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
	2537	_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
2559	2538	_pop_r32(REG_EAX); // pop eax
2560	2539	_cdq(); // cdq
2561		_mov_m64abs_r64(&mips3.core.hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
	2540	_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
2562	2541	_resolve_link(&link1); // skip:
2563	2542	}
2564	2543	return RECOMPILE_SUCCESSFUL_CP(36,4);
r894	r895
2574	2553	_div_r32(REG_ECX); // div ecx
2575	2554	_push_r32(REG_EDX); // push edx
2576	2555	_cdq(); // cdq
2577		_mov_m64abs_r64(&mips3.core.lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
	2556	_mov_m64abs_r64(&mips3.core->lo, REG_EDX, REG_EAX); // mov [lo],edx:eax
2578	2557	_pop_r32(REG_EAX); // pop eax
2579	2558	_cdq(); // cdq
2580		_mov_m64abs_r64(&mips3.core.hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
	2559	_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_EAX); // mov [hi],edx:eax
2581	2560	_resolve_link(&link1); // skip:
2582	2561	}
2583	2562	return RECOMPILE_SUCCESSFUL_CP(36,4);
r894	r895
2607	2586	_mul_m32abs(LO(&dmult_temp2)); // mul [dmult_temp2].lo
2608	2587	_mov_r32_r32(REG_ECX, REG_EDX); // mov ecx,edx
2609	2588	_xor_r32_r32(REG_EBX, REG_EBX); // xor ebx,ebx
2610		_mov_m32abs_r32(LO(&mips3.core.lo), REG_EAX); // mov [lo].lo,eax
	2589	_mov_m32abs_r32(LO(&mips3.core->lo), REG_EAX); // mov [lo].lo,eax
2611	2590
2612	2591	_mov_r32_m32abs(REG_EAX, HI(&dmult_temp1)); // mov eax,[dmult_temp1].hi
2613	2592	_mul_m32abs(LO(&dmult_temp2)); // mul [dmult_temp2].lo
r894	r895
2618	2597	_mul_m32abs(HI(&dmult_temp2)); // mul [dmult_temp2].hi
2619	2598	_add_r32_r32(REG_ECX, REG_EAX); // add ecx,eax
2620	2599	_adc_r32_r32(REG_EBX, REG_EDX); // adc ebx,edx
2621		_mov_m32abs_r32(HI(&mips3.core.lo), REG_ECX); // mov [lo].hi,ecx
	2600	_mov_m32abs_r32(HI(&mips3.core->lo), REG_ECX); // mov [lo].hi,ecx
2622	2601
2623	2602	_mov_r32_m32abs(REG_EAX, HI(&dmult_temp1)); // mov eax,[dmult_temp1].hi
2624	2603	_mul_m32abs(HI(&dmult_temp2)); // mul [dmult_temp2].hi
2625	2604	_add_r32_r32(REG_EBX, REG_EAX); // add ebx,eax
2626	2605	_adc_r32_imm(REG_EDX, 0); // adc edx,0
2627		_mov_m32abs_r32(LO(&mips3.core.hi), REG_EBX); // mov [hi].lo,ebx
2628		_mov_m32abs_r32(HI(&mips3.core.hi), REG_EDX); // mov [hi].hi,edx
	2606	_mov_m32abs_r32(LO(&mips3.core->hi), REG_EBX); // mov [hi].lo,ebx
	2607	_mov_m32abs_r32(HI(&mips3.core->hi), REG_EDX); // mov [hi].hi,edx
2629	2608
2630	2609	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
2631	2610	_xor_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // xor eax,[rtreg].hi
r894	r895
2634	2613	_xor_r32_r32(REG_EBX, REG_EBX); // xor ebx,ebx
2635	2614	_xor_r32_r32(REG_ECX, REG_ECX); // xor ecx,ecx
2636	2615	_xor_r32_r32(REG_EDX, REG_EDX); // xor edx,edx
2637		_sub_r32_m32abs(REG_EAX, LO(&mips3.core.lo)); // sub eax,[lo].lo
2638		_sbb_r32_m32abs(REG_EBX, HI(&mips3.core.lo)); // sbb ebx,[lo].hi
2639		_sbb_r32_m32abs(REG_ECX, LO(&mips3.core.hi)); // sbb ecx,[hi].lo
2640		_sbb_r32_m32abs(REG_EDX, HI(&mips3.core.hi)); // sbb edx,[hi].hi
2641		_mov_m64abs_r64(&mips3.core.lo, REG_EBX, REG_EAX); // mov [lo],ebx:eax
2642		_mov_m64abs_r64(&mips3.core.hi, REG_EDX, REG_ECX); // mov [lo],edx:ecx
	2616	_sub_r32_m32abs(REG_EAX, LO(&mips3.core->lo)); // sub eax,[lo].lo
	2617	_sbb_r32_m32abs(REG_EBX, HI(&mips3.core->lo)); // sbb ebx,[lo].hi
	2618	_sbb_r32_m32abs(REG_ECX, LO(&mips3.core->hi)); // sbb ecx,[hi].lo
	2619	_sbb_r32_m32abs(REG_EDX, HI(&mips3.core->hi)); // sbb edx,[hi].hi
	2620	_mov_m64abs_r64(&mips3.core->lo, REG_EBX, REG_EAX); // mov [lo],ebx:eax
	2621	_mov_m64abs_r64(&mips3.core->hi, REG_EDX, REG_ECX); // mov [lo],edx:ecx
2643	2622	_resolve_link(&link3); // noflip:
2644	2623	return RECOMPILE_SUCCESSFUL_CP(8,4);
2645	2624
r894	r895
2648	2627	_mul_m32bd(REG_ESI, REGDISP(RTREG)); // mul [rtreg].lo
2649	2628	_mov_r32_r32(REG_ECX, REG_EDX); // mov ecx,edx
2650	2629	_xor_r32_r32(REG_EBX, REG_EBX); // xor ebx,ebx
2651		_mov_m32abs_r32(LO(&mips3.core.lo), REG_EAX); // mov [lo].lo,eax
	2630	_mov_m32abs_r32(LO(&mips3.core->lo), REG_EAX); // mov [lo].lo,eax
2652	2631
2653	2632	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
2654	2633	_mul_m32bd(REG_ESI, REGDISP(RTREG)); // mul [rtreg].lo
r894	r895
2659	2638	_mul_m32bd(REG_ESI, REGDISP(RTREG)+4); // mul [rtreg].hi
2660	2639	_add_r32_r32(REG_ECX, REG_EAX); // add ecx,eax
2661	2640	_adc_r32_r32(REG_EBX, REG_EDX); // adc ebx,edx
2662		_mov_m32abs_r32(HI(&mips3.core.lo), REG_ECX); // mov [lo].hi,ecx
	2641	_mov_m32abs_r32(HI(&mips3.core->lo), REG_ECX); // mov [lo].hi,ecx
2663	2642
2664	2643	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
2665	2644	_mul_m32bd(REG_ESI, REGDISP(RTREG)+4); // mul [rtreg].hi
2666	2645	_add_r32_r32(REG_EBX, REG_EAX); // add ebx,eax
2667	2646	_adc_r32_imm(REG_EDX, 0); // adc edx,0
2668		_mov_m32abs_r32(LO(&mips3.core.hi), REG_EBX); // mov [hi].lo,ebx
2669		_mov_m32abs_r32(HI(&mips3.core.hi), REG_EDX); // mov [hi].hi,edx
	2647	_mov_m32abs_r32(LO(&mips3.core->hi), REG_EBX); // mov [hi].lo,ebx
	2648	_mov_m32abs_r32(HI(&mips3.core->hi), REG_EDX); // mov [hi].hi,edx
2670	2649	return RECOMPILE_SUCCESSFUL_CP(8,4);
2671	2650
2672	2651	case 0x1e: /* DDIV */
2673	2652	_sub_r32_imm(REG_ESP, 4); // sub esp,4
2674		_push_imm(&mips3.core.r[RTREG]); // push [rtreg]
2675		_push_imm(&mips3.core.r[RSREG]); // push [rsreg]
	2653	_push_imm(&mips3.core->r[RTREG]); // push [rtreg]
	2654	_push_imm(&mips3.core->r[RSREG]); // push [rsreg]
2676	2655	_call((genf *)ddiv); // call ddiv
2677	2656	_add_r32_imm(REG_ESP, 12); // add esp,12
2678	2657	return RECOMPILE_SUCCESSFUL_CP(68,4);
2679	2658
2680	2659	case 0x1f: /* DDIVU */
2681	2660	_sub_r32_imm(REG_ESP, 4); // sub esp,4
2682		_push_imm(&mips3.core.r[RTREG]); // push [rtreg]
2683		_push_imm(&mips3.core.r[RSREG]); // push [rsreg]
	2661	_push_imm(&mips3.core->r[RTREG]); // push [rtreg]
	2662	_push_imm(&mips3.core->r[RSREG]); // push [rsreg]
2684	2663	_call((genf *)ddivu); // call ddivu
2685	2664	_add_r32_imm(REG_ESP, 12); // add esp,12
2686	2665	return RECOMPILE_SUCCESSFUL_CP(68,4);
2687	2666	}
2688	2667
2689		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	2668	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
2690	2669	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
2691	2670	}
2692	2671
r894	r895
2701	2680	{
2702	2681	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2703	2682	_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg]
2704		_jcc(COND_O, mips3.drc->generate_overflow_exception); // jo generate_overflow_exception
	2683	_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
2705	2684	if (RDREG != 0)
2706	2685	{
2707	2686	_cdq(); // cdq
r894	r895
2759	2738	{
2760	2739	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
2761	2740	_sub_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // sub eax,[rtreg]
2762		_jcc(COND_O, mips3.drc->generate_overflow_exception); // jo generate_overflow_exception
	2741	_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
2763	2742	if (RDREG != 0)
2764	2743	{
2765	2744	_cdq(); // cdq
r894	r895
2978	2957	_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
2979	2958	_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg].lo
2980	2959	_adc_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // adc edx,[rtreg].hi
2981		_jcc(COND_O, mips3.drc->generate_overflow_exception); // jo generate_overflow_exception
	2960	_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
2982	2961	if (RDREG != 0)
2983	2962	_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
2984	2963	}
r894	r895
3028	3007	_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
3029	3008	_sub_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // sub eax,[rtreg].lo
3030	3009	_sbb_r32_m32bd(REG_EDX, REG_ESI, REGDISP(RTREG)+4); // sbb edx,[rtreg].hi
3031		_jcc(COND_O, mips3.drc->generate_overflow_exception); // jo generate_overflow_exception
	3010	_jcc(COND_O, mips3.drcdata->generate_overflow_exception); // jo generate_overflow_exception
3032	3011	if (RDREG != 0)
3033	3012	_mov_m64bd_r64(REG_ESI, REGDISP(RDREG), REG_EDX, REG_EAX); // mov [rdreg],edx:eax
3034	3013	}
r894	r895
3119	3098	}
3120	3099	else
3121	3100	_cmp_r32_imm(REG_EDX, 0); // cmp edx,0
3122		_jcc(COND_GE, mips3.drc->generate_trap_exception); // jge generate_trap_exception
	3101	_jcc(COND_GE, mips3.drcdata->generate_trap_exception); // jge generate_trap_exception
3123	3102	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3124	3103
3125	3104	case 0x31: /* TGEU */
3126	3105	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
3127	3106	_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // cmp eax,[rtreg].hi
3128		_jcc(COND_A, mips3.drc->generate_trap_exception); // ja generate_trap_exception
	3107	_jcc(COND_A, mips3.drcdata->generate_trap_exception); // ja generate_trap_exception
3129	3108	_jcc_short_link(COND_B, &link1); // jb skipit
3130	3109	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
3131	3110	_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
3132		_jcc(COND_AE, mips3.drc->generate_trap_exception); // jae generate_trap_exception
	3111	_jcc(COND_AE, mips3.drcdata->generate_trap_exception); // jae generate_trap_exception
3133	3112	_resolve_link(&link1); // skipit:
3134	3113	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3135	3114
r894	r895
3148	3127	}
3149	3128	else
3150	3129	_cmp_r32_imm(REG_EDX, 0); // cmp edx,0
3151		_jcc(COND_L, mips3.drc->generate_trap_exception); // jl generate_trap_exception
	3130	_jcc(COND_L, mips3.drcdata->generate_trap_exception); // jl generate_trap_exception
3152	3131	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3153	3132
3154	3133	case 0x33: /* TLTU */
3155	3134	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)+4); // mov eax,[rsreg].hi
3156	3135	_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)+4); // cmp eax,[rtreg].hi
3157		_jcc(COND_B, mips3.drc->generate_trap_exception); // jb generate_trap_exception
	3136	_jcc(COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
3158	3137	_jcc_short_link(COND_A, &link1); // ja skipit
3159	3138	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
3160	3139	_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
3161		_jcc(COND_B, mips3.drc->generate_trap_exception); // jb generate_trap_exception
	3140	_jcc(COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
3162	3141	_resolve_link(&link1); // skipit:
3163	3142	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3164	3143
r894	r895
3168	3147	_jcc_short_link(COND_NE, &link1); // jne skipit
3169	3148	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
3170	3149	_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
3171		_jcc(COND_E, mips3.drc->generate_trap_exception); // je generate_trap_exception
	3150	_jcc(COND_E, mips3.drcdata->generate_trap_exception); // je generate_trap_exception
3172	3151	_resolve_link(&link1); // skipit:
3173	3152	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3174	3153
r894	r895
3178	3157	_jcc_short_link(COND_E, &link1); // je skipit
3179	3158	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg].lo
3180	3159	_cmp_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // cmp eax,[rtreg].lo
3181		_jcc(COND_NE, mips3.drc->generate_trap_exception); // jne generate_trap_exception
	3160	_jcc(COND_NE, mips3.drcdata->generate_trap_exception); // jne generate_trap_exception
3182	3161	_resolve_link(&link1); // skipit:
3183	3162	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3184	3163
r894	r895
3323	3302	return RECOMPILE_SUCCESSFUL_CP(1,4);
3324	3303	}
3325	3304
3326		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	3305	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
3327	3306	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
3328	3307	}
3329	3308
r894	r895
3418	3397	_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
3419	3398	_sub_r32_imm(REG_EAX, SIMMVAL); // sub eax,[rtreg].lo
3420	3399	_sbb_r32_imm(REG_EDX, ((INT32)SIMMVAL >> 31)); // sbb edx,[rtreg].lo
3421		_jcc(COND_GE, mips3.drc->generate_trap_exception); // jge generate_trap_exception
	3400	_jcc(COND_GE, mips3.drcdata->generate_trap_exception); // jge generate_trap_exception
3422	3401	}
3423	3402	else
3424	3403	{
3425	3404	if (0 >= SIMMVAL)
3426		_jmp(mips3.drc->generate_trap_exception); // jmp generate_trap_exception
	3405	_jmp(mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
3427	3406	}
3428	3407	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3429	3408
r894	r895
3431	3410	if (RSREG != 0)
3432	3411	{
3433	3412	_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, ((INT32)SIMMVAL >> 31)); // cmp [rsreg].hi,upper
3434		_jcc(COND_A, mips3.drc->generate_trap_exception); // ja generate_trap_exception
	3413	_jcc(COND_A, mips3.drcdata->generate_trap_exception); // ja generate_trap_exception
3435	3414	_jcc_short_link(COND_B, &link1); // jb skip
3436	3415	_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
3437		_jcc(COND_AE, mips3.drc->generate_trap_exception); // jae generate_trap_exception
	3416	_jcc(COND_AE, mips3.drcdata->generate_trap_exception); // jae generate_trap_exception
3438	3417	_resolve_link(&link1); // skip:
3439	3418	}
3440	3419	else
3441	3420	{
3442	3421	if (0 >= SIMMVAL)
3443		_jmp(mips3.drc->generate_trap_exception); // jmp generate_trap_exception
	3422	_jmp(mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
3444	3423	}
3445	3424	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3446	3425
r894	r895
3450	3429	_mov_r64_m64bd(REG_EDX, REG_EAX, REG_ESI, REGDISP(RSREG)); // mov edx:eax,[rsreg]
3451	3430	_sub_r32_imm(REG_EAX, SIMMVAL); // sub eax,[rtreg].lo
3452	3431	_sbb_r32_imm(REG_EDX, ((INT32)SIMMVAL >> 31)); // sbb edx,[rtreg].lo
3453		_jcc(COND_L, mips3.drc->generate_trap_exception); // jl generate_trap_exception
	3432	_jcc(COND_L, mips3.drcdata->generate_trap_exception); // jl generate_trap_exception
3454	3433	}
3455	3434	else
3456	3435	{
3457	3436	if (0 < SIMMVAL)
3458		_jmp(mips3.drc->generate_trap_exception); // jmp generate_trap_exception
	3437	_jmp(mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
3459	3438	}
3460	3439	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3461	3440
r894	r895
3463	3442	if (RSREG != 0)
3464	3443	{
3465	3444	_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, ((INT32)SIMMVAL >> 31)); // cmp [rsreg].hi,upper
3466		_jcc(COND_B, mips3.drc->generate_trap_exception); // jb generate_trap_exception
	3445	_jcc(COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
3467	3446	_jcc_short_link(COND_A, &link1); // ja skip
3468	3447	_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
3469		_jcc(COND_B, mips3.drc->generate_trap_exception); // jb generate_trap_exception
	3448	_jcc(COND_B, mips3.drcdata->generate_trap_exception); // jb generate_trap_exception
3470	3449	_resolve_link(&link1); // skip:
3471	3450	}
3472	3451	else
r894	r895
3482	3461	_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, ((INT32)SIMMVAL >> 31)); // cmp [rsreg].hi,upper
3483	3462	_jcc_short_link(COND_NE, &link1); // jne skip
3484	3463	_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
3485		_jcc(COND_E, mips3.drc->generate_trap_exception); // je generate_trap_exception
	3464	_jcc(COND_E, mips3.drcdata->generate_trap_exception); // je generate_trap_exception
3486	3465	_resolve_link(&link1); // skip:
3487	3466	}
3488	3467	else
3489	3468	{
3490	3469	if (0 == SIMMVAL)
3491		_jmp(mips3.drc->generate_trap_exception); // jmp generate_trap_exception
	3470	_jmp(mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
3492	3471	}
3493	3472	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3494	3473
r894	r895
3498	3477	_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG)+4, ((INT32)SIMMVAL >> 31)); // cmp [rsreg].hi,upper
3499	3478	_jcc_short_link(COND_E, &link1); // je skip
3500	3479	_cmp_m32bd_imm(REG_ESI, REGDISP(RSREG), SIMMVAL); // cmp [rsreg].lo,lower
3501		_jcc(COND_NE, mips3.drc->generate_trap_exception); // jne generate_trap_exception
	3480	_jcc(COND_NE, mips3.drcdata->generate_trap_exception); // jne generate_trap_exception
3502	3481	_resolve_link(&link1); // skip:
3503	3482	}
3504	3483	else
3505	3484	{
3506	3485	if (0 != SIMMVAL)
3507		_jmp(mips3.drc->generate_trap_exception); // jmp generate_trap_exception
	3486	_jmp(mips3.drcdata->generate_trap_exception); // jmp generate_trap_exception
3508	3487	}
3509	3488	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_MAY_CAUSE_EXCEPTION;
3510	3489
r894	r895
3518	3497	}
3519	3498
3520	3499	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3521		_mov_m64abs_imm32(&mips3.core.r[31], pc + 8); // mov [31],pc + 8
	3500	_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3522	3501	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3523	3502	_resolve_link(&link1); // skip:
3524	3503	return RECOMPILE_SUCCESSFUL_CP(1,4);
r894	r895
3527	3506	if (RSREG == 0)
3528	3507	{
3529	3508	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3530		_mov_m64abs_imm32(&mips3.core.r[31], pc + 8); // mov [31],pc + 8
	3509	_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3531	3510	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3532	3511	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
3533	3512	}
r894	r895
3538	3517	}
3539	3518
3540	3519	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3541		_mov_m64abs_imm32(&mips3.core.r[31], pc + 8); // mov [31],pc + 8
	3520	_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3542	3521	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3543	3522	_resolve_link(&link1); // skip:
3544	3523	return RECOMPILE_SUCCESSFUL_CP(1,4);
r894	r895
3553	3532	}
3554	3533
3555	3534	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3556		_mov_m64abs_imm32(&mips3.core.r[31], pc + 8); // mov [31],pc + 8
	3535	_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3557	3536	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3558	3537	_resolve_link(&link1); // skip:
3559	3538	return RECOMPILE_SUCCESSFUL_CP(1,8);
r894	r895
3562	3541	if (RSREG == 0)
3563	3542	{
3564	3543	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3565		_mov_m64abs_imm32(&mips3.core.r[31], pc + 8); // mov [31],pc + 8
	3544	_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3566	3545	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3567	3546	return RECOMPILE_SUCCESSFUL_CP(0,0) \| RECOMPILE_END_OF_STRING;
3568	3547	}
r894	r895
3573	3552	}
3574	3553
3575	3554	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3576		_mov_m64abs_imm32(&mips3.core.r[31], pc + 8); // mov [31],pc + 8
	3555	_mov_m64abs_imm32(&mips3.core->r[31], pc + 8); // mov [31],pc + 8
3577	3556	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles); // <branch or dispatch>
3578	3557	_resolve_link(&link1); // skip:
3579	3558	return RECOMPILE_SUCCESSFUL_CP(1,8);
3580	3559	}
3581	3560
3582		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	3561	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
3583	3562	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
3584	3563	}
3585	3564
r894	r895
3600	3579	switch (reg)
3601	3580	{
3602	3581	case COP0_Cause:
3603		_mov_r32_m32abs(REG_EBX, &mips3.core.cpr[0][COP0_Cause]); // mov ebx,[mips3.core.cpr[0][COP0_Cause]]
	3582	_mov_r32_m32abs(REG_EBX, &mips3.core->cpr[0][COP0_Cause]); // mov ebx,[mips3.core->cpr[0][COP0_Cause]]
3604	3583	_and_r32_imm(REG_EAX, ~0xfc00); // and eax,~0xfc00
3605	3584	_and_r32_imm(REG_EBX, 0xfc00); // and ebx,0xfc00
3606	3585	_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
3607		_mov_m32abs_r32(&mips3.core.cpr[0][COP0_Cause], REG_EAX); // mov [mips3.core.cpr[0][COP0_Cause]],eax
3608		_and_r32_m32abs(REG_EAX, &mips3.core.cpr[0][COP0_Status]); // and eax,[mips3.core.cpr[0][COP0_Status]]
	3586	_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Cause], REG_EAX); // mov [mips3.core->cpr[0][COP0_Cause]],eax
	3587	_and_r32_m32abs(REG_EAX, &mips3.core->cpr[0][COP0_Status]); // and eax,[mips3.core->cpr[0][COP0_Status]]
3609	3588	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_CHECK_SW_INTERRUPTS;
3610	3589
3611	3590	case COP0_Status:
3612		_mov_r32_m32abs(REG_EBX, &mips3.core.cpr[0][COP0_Status]); // mov ebx,[mips3.core.cpr[0][COP0_Status]]
3613		_mov_m32abs_r32(&mips3.core.cpr[0][COP0_Status], REG_EAX); // mov [mips3.core.cpr[0][COP0_Status]],eax
	3591	_mov_r32_m32abs(REG_EBX, &mips3.core->cpr[0][COP0_Status]); // mov ebx,[mips3.core->cpr[0][COP0_Status]]
	3592	_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Status], REG_EAX); // mov [mips3.core->cpr[0][COP0_Status]],eax
3614	3593	_xor_r32_r32(REG_EBX, REG_EAX); // xor ebx,eax
3615	3594	/*
3616	3595	#ifdef MAME_DEBUG
r894	r895
3632	3611	return RECOMPILE_SUCCESSFUL_CP(1,4) \| RECOMPILE_CHECK_INTERRUPTS \| RECOMPILE_END_OF_STRING \| RECOMPILE_ADD_DISPATCH;
3633	3612
3634	3613	case COP0_Count:
3635		_mov_m32abs_r32(&mips3.core.cpr[0][COP0_Count], REG_EAX); // mov [mips3.core.cpr[0][COP0_Count]],eax
3636		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	3614	_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Count], REG_EAX); // mov [mips3.core->cpr[0][COP0_Count]],eax
	3615	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
3637	3616	_sub_r32_imm(REG_ESP, 8); // sub esp,8
3638	3617	_push_r32(REG_EAX); // push eax
3639	3618	_call((genf *)activecpu_gettotalcycles64); // call activecpu_gettotalcycles64
r894	r895
3643	3622	_sbb_r32_imm(REG_EDX, 0); // sbb edx,0
3644	3623	_sub_r32_r32(REG_EAX, REG_EBX); // sub eax,ebx
3645	3624	_sbb_r32_imm(REG_EDX, 0); // sbb edx,0
3646		_mov_m64abs_r64(&mips3.core.count_zero_time, REG_EDX, REG_EAX); // mov [mips3.core.count_zero_time],edx:eax
	3625	_mov_m64abs_r64(&mips3.core->count_zero_time, REG_EDX, REG_EAX); // mov [mips3.core->count_zero_time],edx:eax
3647	3626	append_update_cycle_counting(drc); // update cycle counting
3648	3627	return RECOMPILE_SUCCESSFUL_CP(1,4);
3649	3628
3650	3629	case COP0_Compare:
3651		_mov_m32abs_r32(&mips3.core.cpr[0][COP0_Compare], REG_EAX); // mov [mips3.core.cpr[0][COP0_Compare]],eax
3652		_and_m32abs_imm(&mips3.core.cpr[0][COP0_Cause], ~0x8000); // and [mips3.core.cpr[0][COP0_Cause]],~0x8000
	3630	_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Compare], REG_EAX); // mov [mips3.core->cpr[0][COP0_Compare]],eax
	3631	_and_m32abs_imm(&mips3.core->cpr[0][COP0_Cause], ~0x8000); // and [mips3.core->cpr[0][COP0_Cause]],~0x8000
3653	3632	append_update_cycle_counting(drc); // update cycle counting
3654	3633	return RECOMPILE_SUCCESSFUL_CP(1,4);
3655	3634
r894	r895
3657	3636	return RECOMPILE_SUCCESSFUL_CP(1,4);
3658	3637
3659	3638	case COP0_Config:
3660		_mov_r32_m32abs(REG_EBX, &mips3.core.cpr[0][COP0_Config]); // mov ebx,[mips3.core.cpr[0][COP0_Cause]]
	3639	_mov_r32_m32abs(REG_EBX, &mips3.core->cpr[0][COP0_Config]); // mov ebx,[mips3.core->cpr[0][COP0_Cause]]
3661	3640	_and_r32_imm(REG_EAX, 0x0007); // and eax,0x0007
3662	3641	_and_r32_imm(REG_EBX, ~0x0007); // and ebx,~0x0007
3663	3642	_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
3664		_mov_m32abs_r32(&mips3.core.cpr[0][COP0_Config], REG_EAX); // mov [mips3.core.cpr[0][COP0_Cause]],eax
	3643	_mov_m32abs_r32(&mips3.core->cpr[0][COP0_Config], REG_EAX); // mov [mips3.core->cpr[0][COP0_Cause]],eax
3665	3644	return RECOMPILE_SUCCESSFUL_CP(1,4);
3666	3645
3667	3646	default:
3668		_mov_m32abs_r32(&mips3.core.cpr[0][reg], REG_EAX); // mov [mips3.core.cpr[0][reg]],eax
	3647	_mov_m32abs_r32(&mips3.core->cpr[0][reg], REG_EAX); // mov [mips3.core->cpr[0][reg]],eax
3669	3648	return RECOMPILE_SUCCESSFUL_CP(1,4);
3670	3649	}
3671	3650	return RECOMPILE_UNIMPLEMENTED;
r894	r895
3687	3666	_jcc_short_link(COND_NS, &link1); // jns notneg
3688	3667	_xor_r32_r32(REG_EBP, REG_EBP); // xor ebp,ebp
3689	3668	_resolve_link(&link1); // notneg:
3690		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	3669	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
3691	3670	_sub_r32_imm(REG_ESP, 12); // sub esp,12
3692	3671	_call((genf *)activecpu_gettotalcycles64); // call activecpu_gettotalcycles64
3693	3672	_add_r32_imm(REG_ESP, 12); // add esp,12
3694		_sub_r32_m32abs(REG_EAX, LO(&mips3.core.count_zero_time)); // sub eax,[mips3.core.count_zero_time+0]
3695		_sbb_r32_m32abs(REG_EDX, HI(&mips3.core.count_zero_time)); // sbb edx,[mips3.core.count_zero_time+4]
	3673	_sub_r32_m32abs(REG_EAX, LO(&mips3.core->count_zero_time)); // sub eax,[mips3.core->count_zero_time+0]
	3674	_sbb_r32_m32abs(REG_EDX, HI(&mips3.core->count_zero_time)); // sbb edx,[mips3.core->count_zero_time+4]
3696	3675	_shrd_r32_r32_imm(REG_EAX, REG_EDX, 1); // shrd eax,edx,1
3697	3676	return RECOMPILE_SUCCESSFUL_CP(1,4);
3698	3677
r894	r895
3701	3680	_jcc_short_link(COND_NS, &link1); // jns notneg
3702	3681	_xor_r32_r32(REG_EBP, REG_EBP); // xor ebp,ebp
3703	3682	_resolve_link(&link1); // notneg:
3704		_mov_r32_m32abs(REG_EAX, &mips3.core.cpr[0][reg]); // mov eax,[mips3.core.cpr[0][reg]]
	3683	_mov_r32_m32abs(REG_EAX, &mips3.core->cpr[0][reg]); // mov eax,[mips3.core->cpr[0][reg]]
3705	3684	return RECOMPILE_SUCCESSFUL_CP(1,4);
3706	3685
3707	3686	default:
3708		_mov_r32_m32abs(REG_EAX, &mips3.core.cpr[0][reg]); // mov eax,[mips3.core.cpr[0][reg]]
	3687	_mov_r32_m32abs(REG_EAX, &mips3.core->cpr[0][reg]); // mov eax,[mips3.core->cpr[0][reg]]
3709	3688	return RECOMPILE_SUCCESSFUL_CP(1,4);
3710	3689	}
3711	3690	return RECOMPILE_UNIMPLEMENTED;
r894	r895
3723	3702
3724	3703	if (mips3.drcoptions & MIPS3DRC_STRICT_COP0)
3725	3704	{
3726		_test_m32abs_imm(&mips3.core.cpr[0][COP0_Status], SR_KSU_MASK); // test [mips3.core.cpr[0][COP0_Status]],SR_KSU_MASK
	3705	_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_KSU_MASK); // test [mips3.core->cpr[0][COP0_Status]],SR_KSU_MASK
3727	3706	_jcc_short_link(COND_Z, &checklink); // jz okay
3728		_test_m32abs_imm(&mips3.core.cpr[0][COP0_Status], SR_COP0); // test [mips3.core.cpr[0][COP0_Status]],SR_COP0
3729		_jcc(COND_Z, mips3.drc->generate_cop_exception); // jz generate_cop_exception
	3707	_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_COP0); // test [mips3.core->cpr[0][COP0_Status]],SR_COP0
	3708	_jcc(COND_Z, mips3.drcdata->generate_cop_exception); // jz generate_cop_exception
3730	3709	_resolve_link(&checklink); // okay:
3731	3710	}
3732	3711
r894	r895
3755	3734	case 0x02: /* CFCz */
3756	3735	if (RTREG != 0)
3757	3736	{
3758		_mov_r32_m32abs(REG_EAX, &mips3.core.ccr[0][RDREG]); // mov eax,[mips3.core.ccr[0][rdreg]]
	3737	_mov_r32_m32abs(REG_EAX, &mips3.core->ccr[0][RDREG]); // mov eax,[mips3.core->ccr[0][rdreg]]
3759	3738	_cdq(); // cdq
3760	3739	_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [rtreg],edx:eax
3761	3740	}
r894	r895
3763	3742
3764	3743	case 0x04: /* MTCz */
3765	3744	if (RTREG != 0)
3766		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core.r[RTREG]]
	3745	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core->r[RTREG]]
3767	3746	else
3768	3747	_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
3769	3748	result = recompile_set_cop0_reg(drc, RDREG); // write cop0 reg
r894	r895
3771	3750
3772	3751	case 0x05: /* DMTCz */
3773	3752	if (RTREG != 0)
3774		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core.r[RTREG]]
	3753	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core->r[RTREG]]
3775	3754	else
3776	3755	_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
3777	3756	result = recompile_set_cop0_reg(drc, RDREG); // write cop0 reg
r894	r895
3779	3758
3780	3759	case 0x06: /* CTCz */
3781	3760	if (RTREG != 0)
3782		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core.r[RTREG]]
	3761	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core->r[RTREG]]
3783	3762	else
3784	3763	_xor_r32_r32(REG_EAX, REG_EAX); // xor eax,eax
3785		_mov_m32abs_r32(&mips3.core.ccr[0][RDREG], REG_EAX); // mov [mips3.core.ccr[0][RDREG]],eax
	3764	_mov_m32abs_r32(&mips3.core->ccr[0][RDREG], REG_EAX); // mov [mips3.core->ccr[0][RDREG]],eax
3786	3765	return RECOMPILE_SUCCESSFUL_CP(1,4);
3787	3766
3788	3767	// case 0x08: /* BC */
3789	3768	// switch (RTREG)
3790	3769	// {
3791		// case 0x00: /* BCzF */ if (!mips3.core.cf[0][0]) ADDPC(SIMMVAL); break;
3792		// case 0x01: /* BCzF */ if (mips3.core.cf[0][0]) ADDPC(SIMMVAL); break;
	3770	// case 0x00: /* BCzF */ if (!mips3.core->cf[0][0]) ADDPC(SIMMVAL); break;
	3771	// case 0x01: /* BCzF */ if (mips3.core->cf[0][0]) ADDPC(SIMMVAL); break;
3793	3772	// case 0x02: /* BCzFL */ invalid_instruction(op); break;
3794	3773	// case 0x03: /* BCzTL */ invalid_instruction(op); break;
3795	3774	// default: invalid_instruction(op); break;
r894	r895
3816	3795	{
3817	3796	case 0x01: /* TLBR */
3818	3797	_sub_r32_imm(REG_ESP, 8);
3819		_push_imm(&mips3.core);
	3798	_push_imm(mips3.core);
3820	3799	drc_append_save_call_restore(drc, (genf *)mips3com_tlbr, 12);
3821	3800	return RECOMPILE_SUCCESSFUL_CP(1,4);
3822	3801
3823	3802	case 0x02: /* TLBWI */
3824	3803	_sub_r32_imm(REG_ESP, 8);
3825		_push_imm(&mips3.core);
	3804	_push_imm(mips3.core);
3826	3805	drc_append_save_call_restore(drc, (genf *)mips3com_tlbwi, 12);
3827	3806	return RECOMPILE_SUCCESSFUL_CP(1,4);
3828	3807
3829	3808	case 0x06: /* TLBWR */
3830	3809	_sub_r32_imm(REG_ESP, 8);
3831		_push_imm(&mips3.core);
	3810	_push_imm(mips3.core);
3832	3811	drc_append_save_call_restore(drc, (genf *)mips3com_tlbwr, 12);
3833	3812	return RECOMPILE_SUCCESSFUL_CP(1,4);
3834	3813
3835	3814	case 0x08: /* TLBP */
3836	3815	_sub_r32_imm(REG_ESP, 8);
3837		_push_imm(&mips3.core);
	3816	_push_imm(mips3.core);
3838	3817	drc_append_save_call_restore(drc, (genf *)mips3com_tlbp, 12);
3839	3818	return RECOMPILE_SUCCESSFUL_CP(1,4);
3840	3819
3841	3820	case 0x10: /* RFE */
3842		_jmp(mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	3821	_jmp(mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
3843	3822	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
3844	3823
3845	3824	case 0x18: /* ERET */
3846		_mov_r32_m32abs(REG_EDI, &mips3.core.cpr[0][COP0_EPC]); // mov edi,[mips3.core.cpr[0][COP0_EPC]]
3847		_and_m32abs_imm(&mips3.core.cpr[0][COP0_Status], ~SR_EXL); // and [mips3.core.cpr[0][COP0_Status]],~SR_EXL
	3825	_mov_r32_m32abs(REG_EDI, &mips3.core->cpr[0][COP0_EPC]); // mov edi,[mips3.core->cpr[0][COP0_EPC]]
	3826	_and_m32abs_imm(&mips3.core->cpr[0][COP0_Status], ~SR_EXL); // and [mips3.core->cpr[0][COP0_Status]],~SR_EXL
3848	3827	return RECOMPILE_SUCCESSFUL_CP(1,0) \| RECOMPILE_CHECK_INTERRUPTS \| RECOMPILE_END_OF_STRING \| RECOMPILE_ADD_DISPATCH;
3849	3828
3850	3829	default:
3851		_jmp(mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	3830	_jmp(mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
3852	3831	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
3853	3832	}
3854	3833	break;
3855	3834
3856	3835	// default:
3857		// _jmp(mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	3836	// _jmp(mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
3858	3837	// return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
3859	3838	}
3860	3839	return RECOMPILE_UNIMPLEMENTED;
r894	r895
3877	3856
3878	3857	if (mips3.drcoptions & MIPS3DRC_STRICT_COP1)
3879	3858	{
3880		_test_m32abs_imm(&mips3.core.cpr[0][COP0_Status], SR_COP1); // test [mips3.core.cpr[0][COP0_Status]],SR_COP1
3881		_jcc(COND_Z, mips3.drc->generate_cop_exception); // jz generate_cop_exception
	3859	_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_COP1); // test [mips3.core->cpr[0][COP0_Status]],SR_COP1
	3860	_jcc(COND_Z, mips3.drcdata->generate_cop_exception); // jz generate_cop_exception
3882	3861	}
3883	3862
3884	3863	switch (RSREG)
r894	r895
3886	3865	case 0x00: /* MFCz */
3887	3866	if (RTREG != 0)
3888	3867	{
3889		_mov_r32_m32abs(REG_EAX, FPR32(RDREG)); // mov eax,[mips3.core.cpr[1][RDREG]]
	3868	_mov_r32_m32abs(REG_EAX, FPR32(RDREG)); // mov eax,[mips3.core->cpr[1][RDREG]]
3890	3869	_cdq(); // cdq
3891		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [mips3.core.r[RTREG]],edx:eax
	3870	_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [mips3.core->r[RTREG]],edx:eax
3892	3871	}
3893	3872	return RECOMPILE_SUCCESSFUL_CP(1,4);
3894	3873
r894	r895
3900	3879	case 0x02: /* CFCz */
3901	3880	if (RTREG != 0)
3902	3881	{
3903		_mov_r32_m32abs(REG_EAX, &mips3.core.ccr[1][RDREG]); // mov eax,[mips3.core.ccr[1][RDREG]]
	3882	_mov_r32_m32abs(REG_EAX, &mips3.core->ccr[1][RDREG]); // mov eax,[mips3.core->ccr[1][RDREG]]
3904	3883	if (RDREG == 31)
3905	3884	{
3906	3885	_and_r32_imm(REG_EAX, ~0xfe800000); // and eax,~0xfe800000
3907	3886	_xor_r32_r32(REG_EBX, REG_EBX); // xor ebx,ebx
3908		_cmp_m8abs_imm(&mips3.core.cf[1][0], 0); // cmp [cf[0]],0
	3887	_cmp_m8abs_imm(&mips3.core->cf[1][0], 0); // cmp [cf[0]],0
3909	3888	_setcc_r8(COND_NZ, REG_BL); // setnz bl
3910	3889	_shl_r32_imm(REG_EBX, 23); // shl ebx,23
3911	3890	_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
3912		if (mips3.core.flavor >= MIPS3_TYPE_MIPS_IV)
	3891	if (mips3.core->flavor >= MIPS3_TYPE_MIPS_IV)
3913	3892	for (i = 1; i <= 7; i++)
3914	3893	{
3915		_cmp_m8abs_imm(&mips3.core.cf[1][i], 0); // cmp [cf[i]],0
	3894	_cmp_m8abs_imm(&mips3.core->cf[1][i], 0); // cmp [cf[i]],0
3916	3895	_setcc_r8(COND_NZ, REG_BL); // setnz bl
3917	3896	_shl_r32_imm(REG_EBX, 24+i); // shl ebx,24+i
3918	3897	_or_r32_r32(REG_EAX, REG_EBX); // or eax,ebx
3919	3898	}
3920	3899	}
3921	3900	_cdq(); // cdq
3922		_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [mips3.core.r[RTREG]],edx:eax
	3901	_mov_m64bd_r64(REG_ESI, REGDISP(RTREG), REG_EDX, REG_EAX); // mov [mips3.core->r[RTREG]],edx:eax
3923	3902	}
3924	3903	return RECOMPILE_SUCCESSFUL_CP(1,4);
3925	3904
3926	3905	case 0x04: /* MTCz */
3927	3906	if (RTREG != 0)
3928	3907	{
3929		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core.r[RTREG]]
3930		_mov_m32abs_r32(FPR32(RDREG), REG_EAX); // mov [mips3.core.cpr[1][RDREG]],eax
	3908	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core->r[RTREG]]
	3909	_mov_m32abs_r32(FPR32(RDREG), REG_EAX); // mov [mips3.core->cpr[1][RDREG]],eax
3931	3910	}
3932	3911	else
3933		_mov_m32abs_imm(FPR32(RDREG), 0); // mov [mips3.core.cpr[1][RDREG]],0
	3912	_mov_m32abs_imm(FPR32(RDREG), 0); // mov [mips3.core->cpr[1][RDREG]],0
3934	3913	return RECOMPILE_SUCCESSFUL_CP(1,4);
3935	3914
3936	3915	case 0x05: /* DMTCz */
3937	3916	if (RTREG != 0)
3938	3917	_mov_m64abs_m64bd(FPR64(RDREG), REG_ESI, REGDISP(RTREG));
3939	3918	else
3940		_zero_m64abs(FPR64(RDREG)); // mov [mips3.core.cpr[1][RDREG]],0
	3919	_zero_m64abs(FPR64(RDREG)); // mov [mips3.core->cpr[1][RDREG]],0
3941	3920	return RECOMPILE_SUCCESSFUL_CP(1,4);
3942	3921
3943	3922	case 0x06: /* CTCz */
3944	3923	if (RTREG != 0)
3945	3924	{
3946		_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core.r[RTREG]]
3947		_mov_m32abs_r32(&mips3.core.ccr[1][RDREG], REG_EAX); // mov [mips3.core.ccr[1][RDREG]],eax
	3925	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[mips3.core->r[RTREG]]
	3926	_mov_m32abs_r32(&mips3.core->ccr[1][RDREG], REG_EAX); // mov [mips3.core->ccr[1][RDREG]],eax
3948	3927	}
3949	3928	else
3950		_mov_m32abs_imm(&mips3.core.ccr[1][RDREG], 0); // mov [mips3.core.ccr[1][RDREG]],0
	3929	_mov_m32abs_imm(&mips3.core->ccr[1][RDREG], 0); // mov [mips3.core->ccr[1][RDREG]],0
3951	3930	if (RDREG == 31)
3952	3931	{
3953		_mov_r32_m32abs(REG_EAX, LO(&mips3.core.ccr[1][RDREG])); // mov eax,[mips3.core.ccr[1][RDREG]]
	3932	_mov_r32_m32abs(REG_EAX, LO(&mips3.core->ccr[1][RDREG])); // mov eax,[mips3.core->ccr[1][RDREG]]
3954	3933	_test_r32_imm(REG_EAX, 1 << 23); // test eax,1<<23
3955		_setcc_m8abs(COND_NZ, &mips3.core.cf[1][0]); // setnz [cf[0]]
3956		if (mips3.core.flavor >= MIPS3_TYPE_MIPS_IV)
	3934	_setcc_m8abs(COND_NZ, &mips3.core->cf[1][0]); // setnz [cf[0]]
	3935	if (mips3.core->flavor >= MIPS3_TYPE_MIPS_IV)
3957	3936	for (i = 1; i <= 7; i++)
3958	3937	{
3959	3938	_test_r32_imm(REG_EAX, 1 << (24+i)); // test eax,1<<(24+i)
3960		_setcc_m8abs(COND_NZ, &mips3.core.cf[1][i]); // setnz [cf[i]]
	3939	_setcc_m8abs(COND_NZ, &mips3.core->cf[1][i]); // setnz [cf[i]]
3961	3940	}
3962	3941	_and_r32_imm(REG_EAX, 3); // and eax,3
3963	3942	_test_r32_imm(REG_EAX, 1); // test eax,1
r894	r895
3972	3951	switch ((op >> 16) & 3)
3973	3952	{
3974	3953	case 0x00: /* BCzF */
3975		_cmp_m8abs_imm(&mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
	3954	_cmp_m8abs_imm(&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
3976	3955	_jcc_near_link(COND_NZ, &link1); // jnz link1
3977	3956	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3978	3957	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles);// <branch or dispatch>
r894	r895
3980	3959	return RECOMPILE_SUCCESSFUL_CP(1,4);
3981	3960
3982	3961	case 0x01: /* BCzT */
3983		_cmp_m8abs_imm(&mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
	3962	_cmp_m8abs_imm(&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
3984	3963	_jcc_near_link(COND_Z, &link1); // jz link1
3985	3964	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3986	3965	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles);// <branch or dispatch>
r894	r895
3988	3967	return RECOMPILE_SUCCESSFUL_CP(1,4);
3989	3968
3990	3969	case 0x02: /* BCzFL */
3991		_cmp_m8abs_imm(&mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
	3970	_cmp_m8abs_imm(&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
3992	3971	_jcc_near_link(COND_NZ, &link1); // jnz link1
3993	3972	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
3994	3973	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles);// <branch or dispatch>
r894	r895
3996	3975	return RECOMPILE_SUCCESSFUL_CP(1,8);
3997	3976
3998	3977	case 0x03: /* BCzTL */
3999		_cmp_m8abs_imm(&mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
	3978	_cmp_m8abs_imm(&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 18) & 7) : 0], 0); // cmp [cf[x]],0
4000	3979	_jcc_near_link(COND_Z, &link1); // jz link1
4001	3980	cycles = recompile_delay_slot(drc, pc + 4); // <next instruction>
4002	3981	append_branch_or_dispatch(drc, pc + 4 + (SIMMVAL << 2), 1+cycles);// <branch or dispatch>
r894	r895
4300	4279	return RECOMPILE_SUCCESSFUL_CP(1,4);
4301	4280
4302	4281	case 0x11: /* R5000 */
4303		if (mips3.core.flavor < MIPS3_TYPE_MIPS_IV)
	4282	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
4304	4283	{
4305		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	4284	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
4306	4285	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4307	4286	}
4308		_cmp_m8abs_imm(&mips3.core.cf[1][(op >> 18) & 7], 0); // cmp [cf[x]],0
	4287	_cmp_m8abs_imm(&mips3.core->cf[1][(op >> 18) & 7], 0); // cmp [cf[x]],0
4309	4288	_jcc_short_link(((op >> 16) & 1) ? COND_Z : COND_NZ, &link1); // jz/nz skip
4310	4289	if (IS_SINGLE(op)) /* MOVT/F.S */
4311	4290	{
r894	r895
4318	4297	return RECOMPILE_SUCCESSFUL_CP(1,4);
4319	4298
4320	4299	case 0x12: /* R5000 */
4321		if (mips3.core.flavor < MIPS3_TYPE_MIPS_IV)
	4300	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
4322	4301	{
4323		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	4302	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
4324	4303	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4325	4304	}
4326	4305	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg].lo
r894	r895
4337	4316	return RECOMPILE_SUCCESSFUL_CP(1,4);
4338	4317
4339	4318	case 0x13: /* R5000 */
4340		if (mips3.core.flavor < MIPS3_TYPE_MIPS_IV)
	4319	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
4341	4320	{
4342		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	4321	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
4343	4322	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4344	4323	}
4345	4324	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // mov eax,[rtreg].lo
r894	r895
4356	4335	return RECOMPILE_SUCCESSFUL_CP(1,4);
4357	4336
4358	4337	case 0x15: /* R5000 */
4359		if (mips3.core.flavor < MIPS3_TYPE_MIPS_IV)
	4338	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
4360	4339	{
4361		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	4340	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
4362	4341	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4363	4342	}
4364	4343	_fld1(); // fld1
r894	r895
4377	4356	return RECOMPILE_SUCCESSFUL_CP(1,4);
4378	4357
4379	4358	case 0x16: /* R5000 */
4380		if (mips3.core.flavor < MIPS3_TYPE_MIPS_IV)
	4359	if (mips3.core->flavor < MIPS3_TYPE_MIPS_IV)
4381	4360	{
4382		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	4361	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
4383	4362	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4384	4363	}
4385	4364	_fld1(); // fld1
r894	r895
4443	4422
4444	4423	case 0x30:
4445	4424	case 0x38:
4446		_mov_m8abs_imm(&mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0], 0); /* C.F.S/D */
	4425	_mov_m8abs_imm(&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0], 0); /* C.F.S/D */
4447	4426	return RECOMPILE_SUCCESSFUL_CP(1,4);
4448	4427
4449	4428	case 0x31:
4450	4429	case 0x39:
4451		_mov_m8abs_imm(&mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0], 0); /* C.UN.S/D */
	4430	_mov_m8abs_imm(&mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0], 0); /* C.UN.S/D */
4452	4431	return RECOMPILE_SUCCESSFUL_CP(1,4);
4453	4432
4454	4433	case 0x32:
r894	r895
4465	4444	_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4466	4445	_comisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // comisd xmm0,[ftreg]
4467	4446	}
4468		_setcc_m8abs(COND_E, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // sete [cf[x]]
	4447	_setcc_m8abs(COND_E, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // sete [cf[x]]
4469	4448	}
4470	4449	else
4471	4450	{
r894	r895
4482	4461	_fcompp(); // fcompp
4483	4462	_fnstsw_ax(); // fnstsw ax
4484	4463	_sahf(); // sahf
4485		_setcc_m8abs(COND_E, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // sete [cf[x]]
	4464	_setcc_m8abs(COND_E, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // sete [cf[x]]
4486	4465	}
4487	4466	return RECOMPILE_SUCCESSFUL_CP(1,4);
4488	4467
r894	r895
4500	4479	_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4501	4480	_ucomisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // ucomisd xmm0,[ftreg]
4502	4481	}
4503		_setcc_m8abs(COND_E, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // sete [cf[x]]
	4482	_setcc_m8abs(COND_E, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // sete [cf[x]]
4504	4483	}
4505	4484	else
4506	4485	{
r894	r895
4517	4496	_fucompp(); // fucompp
4518	4497	_fnstsw_ax(); // fnstsw ax
4519	4498	_sahf(); // sahf
4520		_setcc_m8abs(COND_E, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // sete [cf[x]]
	4499	_setcc_m8abs(COND_E, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // sete [cf[x]]
4521	4500	}
4522	4501	return RECOMPILE_SUCCESSFUL_CP(1,4);
4523	4502
r894	r895
4535	4514	_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4536	4515	_comisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // comisd xmm0,[ftreg]
4537	4516	}
4538		_setcc_m8abs(COND_B, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setb [cf[x]]
	4517	_setcc_m8abs(COND_B, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setb [cf[x]]
4539	4518	}
4540	4519	else
4541	4520	{
r894	r895
4552	4531	_fcompp(); // fcompp
4553	4532	_fnstsw_ax(); // fnstsw ax
4554	4533	_sahf(); // sahf
4555		_setcc_m8abs(COND_B, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setb [cf[x]]
	4534	_setcc_m8abs(COND_B, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setb [cf[x]]
4556	4535	}
4557	4536	return RECOMPILE_SUCCESSFUL_CP(1,4);
4558	4537
r894	r895
4570	4549	_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4571	4550	_ucomisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // ucomisd xmm0,[ftreg]
4572	4551	}
4573		_setcc_m8abs(COND_B, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setb [cf[x]]
	4552	_setcc_m8abs(COND_B, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setb [cf[x]]
4574	4553	}
4575	4554	else
4576	4555	{
r894	r895
4587	4566	_fucompp(); // fucompp
4588	4567	_fnstsw_ax(); // fnstsw ax
4589	4568	_sahf(); // sahf
4590		_setcc_m8abs(COND_B, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setb [cf[x]]
	4569	_setcc_m8abs(COND_B, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setb [cf[x]]
4591	4570	}
4592	4571	return RECOMPILE_SUCCESSFUL_CP(1,4);
4593	4572
r894	r895
4605	4584	_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4606	4585	_comisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // comisd xmm0,[ftreg]
4607	4586	}
4608		_setcc_m8abs(COND_BE, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setle [cf[x]]
	4587	_setcc_m8abs(COND_BE, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setle [cf[x]]
4609	4588	}
4610	4589	else
4611	4590	{
r894	r895
4622	4601	_fcompp(); // fcompp
4623	4602	_fnstsw_ax(); // fnstsw ax
4624	4603	_sahf(); // sahf
4625		_setcc_m8abs(COND_BE, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setbe [cf[x]]
	4604	_setcc_m8abs(COND_BE, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setbe [cf[x]]
4626	4605	}
4627	4606	return RECOMPILE_SUCCESSFUL_CP(1,4);
4628	4607
r894	r895
4640	4619	_movsd_r128_m64abs(REG_XMM0, FPR64(FSREG)); // movsd xmm0,[fsreg]
4641	4620	_ucomisd_r128_m64abs(REG_XMM0, FPR64(FTREG)); // ucomisd xmm0,[ftreg]
4642	4621	}
4643		_setcc_m8abs(COND_BE, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setl [cf[x]]
	4622	_setcc_m8abs(COND_BE, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setl [cf[x]]
4644	4623	}
4645	4624	else
4646	4625	{
r894	r895
4657	4636	_fucompp(); // fucompp
4658	4637	_fnstsw_ax(); // fnstsw ax
4659	4638	_sahf(); // sahf
4660		_setcc_m8abs(COND_BE, &mips3.core.cf[1][(mips3.core.flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setbe [cf[x]]
	4639	_setcc_m8abs(COND_BE, &mips3.core->cf[1][(mips3.core->flavor >= MIPS3_TYPE_MIPS_IV) ? ((op >> 8) & 7) : 0]); // setbe [cf[x]]
4661	4640	}
4662	4641	return RECOMPILE_SUCCESSFUL_CP(1,4);
4663	4642	}
4664	4643	break;
4665	4644	}
4666		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	4645	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
4667	4646	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4668	4647	}
4669	4648
r894	r895
4681	4660	{
4682	4661	if (mips3.drcoptions & MIPS3DRC_STRICT_COP1)
4683	4662	{
4684		_test_m32abs_imm(&mips3.core.cpr[0][COP0_Status], SR_COP1); // test [mips3.core.cpr[0][COP0_Status]],SR_COP1
4685		_jcc(COND_Z, mips3.drc->generate_cop_exception); // jz generate_cop_exception
	4663	_test_m32abs_imm(&mips3.core->cpr[0][COP0_Status], SR_COP1); // test [mips3.core->cpr[0][COP0_Status]],SR_COP1
	4664	_jcc(COND_Z, mips3.drcdata->generate_cop_exception); // jz generate_cop_exception
4686	4665	}
4687	4666
4688	4667	switch (op & 0x3f)
4689	4668	{
4690	4669	case 0x00: /* LWXC1 */
4691		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	4670	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
4692	4671	_save_pc_before_call(); // save pc
4693	4672	_sub_r32_imm(REG_ESP, 8); // sub esp,8
4694	4673	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
4695	4674	_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg]
4696	4675	_push_r32(REG_EAX); // push eax
4697		_call(mips3.drc->read_and_translate_long); // call read_and_translate_long
	4676	_call(mips3.drcdata->read_and_translate_long); // call read_and_translate_long
4698	4677	_add_r32_imm(REG_ESP, 12); // add esp,12
4699	4678	_mov_m32abs_r32(FPR32(FDREG), REG_EAX); // mov [fdreg],eax
4700		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	4679	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
4701	4680	return RECOMPILE_SUCCESSFUL_CP(1,4);
4702	4681
4703	4682	case 0x01: /* LDXC1 */
4704		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	4683	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
4705	4684	_save_pc_before_call(); // save pc
4706	4685	_sub_r32_imm(REG_ESP, 8); // sub esp,8
4707	4686	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
4708	4687	_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg]
4709	4688	_push_r32(REG_EAX); // push eax
4710		_call(mips3.drc->read_and_translate_double); // call read_and_translate_double
	4689	_call(mips3.drcdata->read_and_translate_double); // call read_and_translate_double
4711	4690	_mov_m32abs_r32(LO(FPR64(FDREG)), REG_EAX); // mov [fdreg].lo,eax
4712	4691	_mov_m32abs_r32(HI(FPR64(FDREG)), REG_EDX); // mov [fdreg].hi,edx
4713	4692	_add_r32_imm(REG_ESP, 12); // add esp,12
4714		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	4693	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
4715	4694	return RECOMPILE_SUCCESSFUL_CP(1,4);
4716	4695
4717	4696	case 0x08: /* SWXC1 */
4718		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	4697	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
4719	4698	_save_pc_before_call(); // save pc
4720	4699	_sub_r32_imm(REG_ESP, 4); // sub esp,4
4721	4700	_push_m32abs(FPR32(FSREG)); // push [fsreg]
4722	4701	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
4723	4702	_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg]
4724	4703	_push_r32(REG_EAX); // push eax
4725		_call(mips3.drc->write_and_translate_long); // call write_and_translate_long
	4704	_call(mips3.drcdata->write_and_translate_long); // call write_and_translate_long
4726	4705	_add_r32_imm(REG_ESP, 12); // add esp,8
4727		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	4706	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
4728	4707	return RECOMPILE_SUCCESSFUL_CP(1,4);
4729	4708
4730	4709	case 0x09: /* SDXC1 */
4731	4710	// REVISIT: does this actually work?
4732	4711	// Two 32-bit words are pushed, before the call, but three are popped afterwards!
4733	4712	// This, as far as I can see, will kill off the return address.
4734		// All other calls to mips3.drc->write_and_translate_double take three 32-bit words as arguments.
	4713	// All other calls to mips3.drcdata->write_and_translate_double take three 32-bit words as arguments.
4735	4714	// So is one argument too few being pushed, or is one too many being popped?
4736		_mov_m32abs_r32(&mips3_icount, REG_EBP); // mov [mips3_icount],ebp
	4715	_mov_m32abs_r32(&mips3.core->icount, REG_EBP); // mov [mips3.core->icount],ebp
4737	4716	_save_pc_before_call(); // save pc
4738	4717	_push_m32abs(HI(FPR64(FSREG))); // push [fsreg].hi
4739	4718	_push_m32abs(LO(FPR64(FSREG))); // push [fsreg].lo
4740	4719	_mov_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RSREG)); // mov eax,[rsreg]
4741	4720	_add_r32_m32bd(REG_EAX, REG_ESI, REGDISP(RTREG)); // add eax,[rtreg]
4742		_call(mips3.drc->write_and_translate_double); // call write_and_translate_double
	4721	_call(mips3.drcdata->write_and_translate_double); // call write_and_translate_double
4743	4722	_add_r32_imm(REG_ESP, 12); // add esp,12
4744		_mov_r32_m32abs(REG_EBP, &mips3_icount); // mov ebp,[mips3_icount]
	4723	_mov_r32_m32abs(REG_EBP, &mips3.core->icount); // mov ebp,[mips3.core->icount]
4745	4724	return RECOMPILE_SUCCESSFUL_CP(1,4);
4746	4725
4747	4726	case 0x0f: /* PREFX */
r894	r895
4919	4898	fprintf(stderr, "cop1x %X\n", op);
4920	4899	break;
4921	4900	}
4922		_jmp((void *)mips3.drc->generate_invalidop_exception); // jmp generate_invalidop_exception
	4901	_jmp((void *)mips3.drcdata->generate_invalidop_exception); // jmp generate_invalidop_exception
4923	4902	return RECOMPILE_SUCCESSFUL \| RECOMPILE_END_OF_STRING;
4924	4903	}

src/emu/cpu/mips/mips3drc.c
r894	r895
16	16	#include "debugger.h"
17	17	#include "mips3com.h"
18	18
	19	#ifdef PTR64
	20	#include "cpu/x64drc.h"
	21	#include "mips3fe.h"
	22	#else
	23	#include "cpu/x86drc.h"
	24	#endif
19	25
20	26
	27
21	28	/***************************************************************************
22	29	DEBUGGING
23	30	***************************************************************************/
r894	r895
31	38	***************************************************************************/
32	39
33	40	#define MAX_INSTRUCTIONS 512
	41	#define CACHE_SIZE (32 * 1024 * 1024)
34	42
35	43
36	44
r894	r895
38	46	MACROS
39	47	***************************************************************************/
40	48
41		#define SR mips3.core.cpr[0][COP0_Status]
	49	#define SR mips3.core->cpr[0][COP0_Status]
42	50	#define IS_FR0 (!(SR & SR_FR))
43	51	#define IS_FR1 (SR & SR_FR)
44	52
r894	r895
88	96	struct _mips3_regs
89	97	{
90	98	/* core state */
91		mips3_state core;
92		mips3drc_data * drc;
93		UINT32 drcoptions;
	99	UINT8 * cache; /* base of the cache */
	100	mips3_state * core; /* pointer to the core MIPS3 state */
	101	drc_core * drc; /* pointer to the DRC core */
	102	mips3drc_data * drcdata; /* pointer to the DRC-specific data */
	103	UINT32 drcoptions; /* configurable DRC options */
94	104
95	105	/* internal stuff */
96	106	UINT32 nextpc;
	107	UINT8 cache_dirty;
97	108
98	109	/* fast RAM */
99	110	UINT32 fastram_select;
r894	r895
111	122	***************************************************************************/
112	123
113	124	static void mips3drc_init(void);
114		static void mips3drc_reset(void);
115		static void mips3drc_execute(void);
116	125	static void mips3drc_exit(void);
117	126
118	127
r894	r895
130	139	***************************************************************************/
131	140
132	141	/*-------------------------------------------------
	142	mips3_init - initialize the processor
	143	-------------------------------------------------*/
	144
	145	void mips3_init(mips3_state mips, mips3_flavor flavor, int bigendian, int index, int clock, const struct mips3_config config, int (*irqcallback)(int))
	146	{
	147	/* allocate a cache and memory for the core data in a single block */
	148	mips3.core = osd_alloc_executable(CACHE_SIZE + sizeof(*mips3.core));
	149	if (mips3.core == NULL)
	150	fatalerror("Unable to allocate cache of size %d\n", CACHE_SIZE);
	151	mips3.cache = (UINT8 *)(mips3.core + 1);
	152
	153	/* initialize the core */
	154	mips3com_init(mips3.core, flavor, bigendian, index, clock, config, irqcallback);
	155
	156	/* initialize the DRC to use the cache */
	157	mips3drc_init();
	158	}
	159
	160
	161	/*-------------------------------------------------
133	162	mips3_reset - reset the processor
134	163	-------------------------------------------------*/
135	164
136	165	static void mips3_reset(void)
137	166	{
138		mips3com_reset(&mips3.core);
139		mips3drc_reset();
	167	/* reset the common code and flush the cache */
	168	mips3com_reset(mips3.core);
	169	drc_cache_reset(mips3.drc);
140	170	}
141	171
142	172
r894	r895
147	177
148	178	static int mips3_execute(int cycles)
149	179	{
	180	/* reset the cache if dirty */
	181	if (mips3.cache_dirty)
	182	drc_cache_reset(mips3.drc);
	183	mips3.cache_dirty = FALSE;
	184
150	185	/* update the cycle timing */
151		mips3com_update_cycle_counting(&mips3.core);
	186	mips3com_update_cycle_counting(mips3.core);
152	187
153	188	/* execute */
154		mips3_icount = cycles;
155		mips3drc_execute();
156		return cycles - mips3_icount;
	189	mips3.core->icount = cycles;
	190	drc_execute(mips3.drc);
	191	return cycles - mips3.core->icount;
157	192	}
158	193
159	194
r894	r895
164	199	static void mips3_exit(void)
165	200	{
166	201	mips3drc_exit();
	202
	203	/* clean up the DRC */
	204	drc_exit(mips3.drc);
	205
	206	/* free the cache */
	207	osd_free_executable(mips3.core, CACHE_SIZE + sizeof(*mips3.core));
167	208	}
168	209
169	210
r894	r895
198	239
199	240	static int mips3_translate(int space, offs_t *address)
200	241	{
201		return mips3com_translate_address(&mips3.core, space, address);
	242	return mips3com_translate_address(mips3.core, space, address);
202	243	}
203	244
204	245
r894	r895
209	250	#ifdef MAME_DEBUG
210	251	static offs_t mips3_dasm(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram)
211	252	{
212		return mips3com_dasm(&mips3.core, buffer, pc, oprom, opram);
	253	return mips3com_dasm(mips3.core, buffer, pc, oprom, opram);
213	254	}
214	255	#endif /* MAME_DEBUG */
215	256
r894	r895
223	264
224	265	static code_log_entry code_log_buffer[MAX_INSTRUCTIONS*2];
225	266	static int code_log_index;
	267	static FILE *logfile;
226	268
	269
	270	/*-------------------------------------------------
	271	open_logfile - open the log file if it is
	272	not already opened
	273	-------------------------------------------------*/
	274
	275	INLINE int open_logfile(void)
	276	{
	277	if (logfile == NULL)
	278	logfile = fopen("mips3drc.asm", "w");
	279	return (logfile != NULL);
	280	}
	281
	282
	283	/*-------------------------------------------------
	284	code_log_reset - reset the logging index
	285	-------------------------------------------------*/
	286
227	287	INLINE void code_log_reset(void)
228	288	{
229	289	code_log_index = 0;
230	290	}
231	291
	292
	293	/*-------------------------------------------------
	294	code_log_add_entry - add an entry to the log
	295	-------------------------------------------------*/
	296
232	297	INLINE void code_log_add_entry(UINT32 pc, UINT32 op, void *base)
233	298	{
234	299	code_log_buffer[code_log_index].pc = pc;
r894	r895
237	302	code_log_index++;
238	303	}
239	304
	305
	306	/*-------------------------------------------------
	307	code_log - actually log some code
	308	-------------------------------------------------*/
	309
240	310	static void code_log(const char label, void start, void *stop)
241	311	{
242	312	extern int i386_dasm_one(char buffer, UINT32 eip, UINT8 oprom, int mode);
243	313	extern unsigned dasmmips3(char *buffer, unsigned pc, UINT32 op);
244	314	UINT8 *cur = start;
245		static FILE *f;
246	315
247	316	/* open the file, creating it if necessary */
248		if (!f)
249		f = fopen("mips3drc.asm", "w");
250		if (!f)
	317	if (!open_logfile())
251	318	return;
252		fprintf(f, "\n%s\n", label);
	319	fprintf(logfile, "\n%s\n", label);
253	320
254	321	/* loop from the start until the cache top */
255	322	while (cur < (UINT8 *)stop)
r894	r895
258	325	int bytes;
259	326	int op;
260	327
	328	/* skip filler opcodes */
	329	if (*cur == 0xcc)
	330	{
	331	cur++;
	332	continue;
	333	}
	334
261	335	/* disassemble this instruction */
262	336	#ifdef PTR64
263		bytes = i386_dasm_one(buffer, (UINT32)cur, cur, 64) & DASMFLAG_LENGTHMASK;
	337	bytes = i386_dasm_one(buffer, (UINT32)(FPTR)cur, cur, 64) & DASMFLAG_LENGTHMASK;
264	338	#else
265	339	bytes = i386_dasm_one(buffer, (UINT32)cur, cur, 32) & DASMFLAG_LENGTHMASK;
266	340	#endif
r894	r895
272	346
273	347	/* if no match, just output the current instruction */
274	348	if (op == code_log_index)
275		fprintf(f, "%p: %s\n", cur, buffer);
	349	fprintf(logfile, "%p: %s\n", cur, buffer);
276	350
277	351	/* otherwise, output with the original instruction to the right */
278	352	else
279	353	{
280	354	char buffer2[100];
281	355	dasmmips3(buffer2, code_log_buffer[op].pc, code_log_buffer[op].op);
282		fprintf(f, "%p: %-50s %08X: %s\n", cur, buffer, code_log_buffer[op].pc, buffer2);
	356	fprintf(logfile, "%p: %-50s %08X: %s\n", cur, buffer, code_log_buffer[op].pc, buffer2);
283	357	}
284	358
285	359	/* advance past this instruction */
r894	r895
287	361	}
288	362
289	363	/* flush the file */
290		fflush(f);
	364	fflush(logfile);
291	365	}
292	366
	367
	368	#ifdef PTR64
	369
	370	/*-------------------------------------------------
	371	desc_flags_log - generate a string
	372	representing the instruction description
	373	flags
	374	-------------------------------------------------*/
	375
	376	static const char *desc_flags_log(UINT32 flags)
	377	{
	378	static char tempbuf[30];
	379	char *dest = tempbuf;
	380
	381	/* branches */
	382	if (flags & IDESC_IS_UNCONDITIONAL_BRANCH)
	383	*dest++ = 'U';
	384	else if (flags & IDESC_IS_CONDITIONAL_BRANCH)
	385	*dest++ = 'C';
	386	else
	387	*dest++ = '.';
	388
	389	/* intrablock branches */
	390	*dest++ = (flags & IDESC_INTRABLOCK_BRANCH) ? 'i' : '.';
	391
	392	/* branch targets */
	393	*dest++ = (flags & IDESC_IS_BRANCH_TARGET) ? 'B' : '.';
	394
	395	/* delay slots */
	396	*dest++ = (flags & IDESC_IN_DELAY_SLOT) ? 'D' : '.';
	397
	398	/* exceptions */
	399	if (flags & IDESC_WILL_CAUSE_EXCEPTION)
	400	*dest++ = 'E';
	401	else if (flags & IDESC_CAN_CAUSE_EXCEPTION)
	402	*dest++ = 'e';
	403	else
	404	*dest++ = '.';
	405
	406	/* read/write */
	407	if (flags & IDESC_READS_MEMORY)
	408	*dest++ = 'R';
	409	else if (flags & IDESC_WRITES_MEMORY)
	410	*dest++ = 'W';
	411	else
	412	*dest++ = '.';
	413
	414	/* TLB validation */
	415	*dest++ = (flags & IDESC_VALIDATE_TLB) ? 'V' : '.';
	416
	417	/* TLB modification */
	418	*dest++ = (flags & IDESC_MODIFIES_TRANSLATION) ? 'T' : '.';
	419
	420	/* redispatch */
	421	*dest++ = (flags & IDESC_REDISPATCH) ? 'R' : '.';
	422	return tempbuf;
	423	}
	424
	425
	426	/*-------------------------------------------------
	427	desc_log - log a list of descriptions
	428	-------------------------------------------------*/
	429
	430	static void desc_log(const mips3_opcode_desc *desclist, int indent)
	431	{
	432	/* open the file, creating it if necessary */
	433	if (!open_logfile())
	434	return;
	435	if (indent == 0)
	436	fprintf(logfile, "\nDescriptor list @ %08X\n", desclist->pc);
	437
	438	/* output each descriptor */
	439	while (desclist != NULL)
	440	{
	441	char buffer[100];
	442	dasmmips3(buffer, desclist->pc, *desclist->opptr);
	443	fprintf(logfile, "%08X [%08X] t:%08X f:%s: %-30s\n", desclist->pc, desclist->physpc, desclist->targetpc, desc_flags_log(desclist->flags), buffer);
	444	if (desclist->delay)
	445	desc_log(desclist->delay, indent + 1);
	446	if (desclist->flags & IDESC_END_SEQUENCE)
	447	fprintf(logfile, "-----\n");
	448	desclist = desclist->next;
	449	}
	450	}
	451	#endif
	452
293	453	#else
294	454
295	455	#define code_log_reset()
296	456	#define code_log_add_entry(a,b,c)
297	457	#define code_log(a,b,c)
	458	#define desc_log(a)
298	459
299	460	#endif
300	461
r894	r895
323	484	/* --- the following bits of info are set as 64-bit signed integers --- */
324	485	case CPUINFO_INT_MIPS3_DRC_OPTIONS: mips3.drcoptions = info->i; break;
325	486
326		case CPUINFO_INT_MIPS3_FASTRAM_SELECT: if (info->i >= 0 && info->i < MIPS3_MAX_FASTRAM) mips3.fastram_select = info->i; break;
327		case CPUINFO_INT_MIPS3_FASTRAM_START: mips3.fastram[mips3.fastram_select].start = info->i; break;
328		case CPUINFO_INT_MIPS3_FASTRAM_END: mips3.fastram[mips3.fastram_select].end = info->i; break;
329		case CPUINFO_INT_MIPS3_FASTRAM_READONLY: mips3.fastram[mips3.fastram_select].readonly = info->i; break;
	487	case CPUINFO_INT_MIPS3_FASTRAM_SELECT: if (info->i >= 0 && info->i < MIPS3_MAX_FASTRAM) mips3.fastram_select = info->i; mips3.cache_dirty = TRUE; break;
	488	case CPUINFO_INT_MIPS3_FASTRAM_START: mips3.fastram[mips3.fastram_select].start = info->i; mips3.cache_dirty = TRUE; break;
	489	case CPUINFO_INT_MIPS3_FASTRAM_END: mips3.fastram[mips3.fastram_select].end = info->i; mips3.cache_dirty = TRUE; break;
	490	case CPUINFO_INT_MIPS3_FASTRAM_READONLY: mips3.fastram[mips3.fastram_select].readonly = info->i; mips3.cache_dirty = TRUE; break;
330	491
331		case CPUINFO_INT_MIPS3_HOTSPOT_SELECT: if (info->i >= 0 && info->i < MIPS3_MAX_HOTSPOTS) mips3.hotspot_select = info->i; break;
332		case CPUINFO_INT_MIPS3_HOTSPOT_PC: mips3.hotspot[mips3.hotspot_select].pc = info->i; break;
333		case CPUINFO_INT_MIPS3_HOTSPOT_OPCODE: mips3.hotspot[mips3.hotspot_select].opcode = info->i; break;
334		case CPUINFO_INT_MIPS3_HOTSPOT_CYCLES: mips3.hotspot[mips3.hotspot_select].cycles = info->i; break;
	492	case CPUINFO_INT_MIPS3_HOTSPOT_SELECT: if (info->i >= 0 && info->i < MIPS3_MAX_HOTSPOTS) mips3.hotspot_select = info->i; mips3.cache_dirty = TRUE; break;
	493	case CPUINFO_INT_MIPS3_HOTSPOT_PC: mips3.hotspot[mips3.hotspot_select].pc = info->i; mips3.cache_dirty = TRUE; break;
	494	case CPUINFO_INT_MIPS3_HOTSPOT_OPCODE: mips3.hotspot[mips3.hotspot_select].opcode = info->i; mips3.cache_dirty = TRUE; break;
	495	case CPUINFO_INT_MIPS3_HOTSPOT_CYCLES: mips3.hotspot[mips3.hotspot_select].cycles = info->i; mips3.cache_dirty = TRUE; break;
335	496
336	497	/* --- the following bits of info are set as pointers to data or functions --- */
337	498	case CPUINFO_PTR_MIPS3_FASTRAM_BASE: mips3.fastram[mips3.fastram_select].base = info->p; break;
338	499
339	500	/* --- everything else is handled generically --- */
340		default: mips3com_set_info(&mips3.core, state, info); break;
	501	default: mips3com_set_info(mips3.core, state, info); break;
341	502	}
342	503	}
343	504
r894	r895
367	528	case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
368	529
369	530	/* --- everything else is handled generically --- */
370		default: mips3com_get_info(&mips3.core, state, info); break;
	531	default: mips3com_get_info(mips3.core, state, info); break;
371	532	}
372	533	}
373	534
r894	r895
380	541	#if (HAS_R4600)
381	542	static void r4600be_init(int index, int clock, const void config, int (irqcallback)(int))
382	543	{
383		mips3com_init(&mips3.core, MIPS3_TYPE_R4600, TRUE, index, clock, config, irqcallback);
384		mips3drc_init();
	544	mips3_init(mips3.core, MIPS3_TYPE_R4600, TRUE, index, clock, config, irqcallback);
385	545	}
386	546
387	547	static void r4600le_init(int index, int clock, const void config, int (irqcallback)(int))
388	548	{
389		mips3com_init(&mips3.core, MIPS3_TYPE_R4600, FALSE, index, clock, config, irqcallback);
390		mips3drc_init();
	549	mips3_init(mips3.core, MIPS3_TYPE_R4600, FALSE, index, clock, config, irqcallback);
391	550	}
392	551
393	552	void r4600be_get_info(UINT32 state, cpuinfo *info)
r894	r895
436	595	#if (HAS_R4650)
437	596	static void r4650be_init(int index, int clock, const void config, int (irqcallback)(int))
438	597	{
439		mips3com_init(&mips3.core, MIPS3_TYPE_R4650, TRUE, index, clock, config, irqcallback);
440		mips3drc_init();
	598	mips3_init(mips3.core, MIPS3_TYPE_R4650, TRUE, index, clock, config, irqcallback);
441	599	}
442	600
443	601	static void r4650le_init(int index, int clock, const void config, int (irqcallback)(int))
444	602	{
445		mips3com_init(&mips3.core, MIPS3_TYPE_R4650, FALSE, index, clock, config, irqcallback);
446		mips3drc_init();
	603	mips3_init(mips3.core, MIPS3_TYPE_R4650, FALSE, index, clock, config, irqcallback);
447	604	}
448	605
449	606	void r4650be_get_info(UINT32 state, cpuinfo *info)
r894	r895
492	649	#if (HAS_R4700)
493	650	static void r4700be_init(int index, int clock, const void config, int (irqcallback)(int))
494	651	{
495		mips3com_init(&mips3.core, MIPS3_TYPE_R4700, TRUE, index, clock, config, irqcallback);
496		mips3drc_init();
	652	mips3_init(mips3.core, MIPS3_TYPE_R4700, TRUE, index, clock, config, irqcallback);
497	653	}
498	654
499	655	static void r4700le_init(int index, int clock, const void config, int (irqcallback)(int))
500	656	{
501		mips3com_init(&mips3.core, MIPS3_TYPE_R4700, FALSE, index, clock, config, irqcallback);
502		mips3drc_init();
	657	mips3_init(mips3.core, MIPS3_TYPE_R4700, FALSE, index, clock, config, irqcallback);
503	658	}
504	659
505	660	void r4700be_get_info(UINT32 state, cpuinfo *info)
r894	r895
549	704	#if (HAS_R5000)
550	705	static void r5000be_init(int index, int clock, const void config, int (irqcallback)(int))
551	706	{
552		mips3com_init(&mips3.core, MIPS3_TYPE_R5000, TRUE, index, clock, config, irqcallback);
553		mips3drc_init();
	707	mips3_init(mips3.core, MIPS3_TYPE_R5000, TRUE, index, clock, config, irqcallback);
554	708	}
555	709
556	710	static void r5000le_init(int index, int clock, const void config, int (irqcallback)(int))
557	711	{
558		mips3com_init(&mips3.core, MIPS3_TYPE_R5000, FALSE, index, clock, config, irqcallback);
559		mips3drc_init();
	712	mips3_init(mips3.core, MIPS3_TYPE_R5000, FALSE, index, clock, config, irqcallback);
560	713	}
561	714
562	715	void r5000be_get_info(UINT32 state, cpuinfo *info)
r894	r895
605	758	#if (HAS_QED5271)
606	759	static void qed5271be_init(int index, int clock, const void config, int (irqcallback)(int))
607	760	{
608		mips3com_init(&mips3.core, MIPS3_TYPE_QED5271, TRUE, index, clock, config, irqcallback);
609		mips3drc_init();
	761	mips3_init(mips3.core, MIPS3_TYPE_QED5271, TRUE, index, clock, config, irqcallback);
610	762	}
611	763
612	764	static void qed5271le_init(int index, int clock, const void config, int (irqcallback)(int))
613	765	{
614		mips3com_init(&mips3.core, MIPS3_TYPE_QED5271, FALSE, index, clock, config, irqcallback);
615		mips3drc_init();
	766	mips3_init(mips3.core, MIPS3_TYPE_QED5271, FALSE, index, clock, config, irqcallback);
616	767	}
617	768
618	769	void qed5271be_get_info(UINT32 state, cpuinfo *info)
r894	r895
661	812	#if (HAS_RM7000)
662	813	static void rm7000be_init(int index, int clock, const void config, int (irqcallback)(int))
663	814	{
664		mips3com_init(&mips3.core, MIPS3_TYPE_RM7000, TRUE, index, clock, config, irqcallback);
665		mips3drc_init();
	815	mips3_init(mips3.core, MIPS3_TYPE_RM7000, TRUE, index, clock, config, irqcallback);
666	816	}
667	817
668	818	static void rm7000le_init(int index, int clock, const void config, int (irqcallback)(int))
669	819	{
670		mips3com_init(&mips3.core, MIPS3_TYPE_RM7000, FALSE, index, clock, config, irqcallback);
671		mips3drc_init();
	820	mips3_init(mips3.core, MIPS3_TYPE_RM7000, FALSE, index, clock, config, irqcallback);
672	821	}
673	822
674	823	void rm7000be_get_info(UINT32 state, cpuinfo *info)

src/emu/cpu/mips/mips3com.c
r894	r895
30	30	static void tlb_entry_log_half(mips3_tlb_entry *tlbent, int index, int which);
31	31
32	32	static UINT64 program_read_qword_32be(offs_t offset);
33		static UINT64 program_read_qword_32le(offs_t offset);
	33	static UINT64 program_read_qword_masked_32be(offs_t offset, UINT64 mem_mask);
	34
34	35	static void program_write_qword_32be(offs_t offset, UINT64 data);
35		static void program_write_qword_32le(offs_t offset, UINT64 data);
	36	static void program_write_qword_masked_32be(offs_t offset, UINT64 data, UINT64 mem_mask);
36	37
	38	static UINT64 program_read_qword_32le(offs_t offset);
	39	static UINT64 program_read_qword_masked_32le(offs_t offset, UINT64 mem_mask);
37	40
	41	static void program_write_qword_32le(offs_t offset, UINT64 data);
	42	static void program_write_qword_masked_32le(offs_t offset, UINT64 data, UINT64 mem_mask);
38	43
39		/***************************************************************************
40		GLOBAL VARIABLES
41		***************************************************************************/
42	44
43		int mips3_icount;
44	45
45
46
47	46	/***************************************************************************
48	47	PRIVATE GLOBAL VARIABLES
49	48	***************************************************************************/
50	49
51	50	static const memory_handlers be_memory =
52	51	{
53		program_read_byte_32be, program_read_word_32be, program_read_dword_32be, program_read_qword_32be,
54		program_write_byte_32be, program_write_word_32be, program_write_dword_32be, program_write_qword_32be
	52	program_read_byte_32be,
	53	program_read_word_32be,
	54	program_read_dword_32be,
	55	program_read_masked_32be,
	56	program_read_qword_32be,
	57	program_read_qword_masked_32be,
	58
	59	program_write_byte_32be,
	60	program_write_word_32be,
	61	program_write_dword_32be,
	62	program_write_masked_32be,
	63	program_write_qword_32be,
	64	program_write_qword_masked_32be
55	65	};
56	66
57	67	static const memory_handlers le_memory =
58	68	{
59		program_read_byte_32le, program_read_word_32le, program_read_dword_32le, program_read_qword_32le,
60		program_write_byte_32le, program_write_word_32le, program_write_dword_32le, program_write_qword_32le
	69	program_read_byte_32le,
	70	program_read_word_32le,
	71	program_read_dword_32le,
	72	program_read_masked_32le,
	73	program_read_qword_32le,
	74	program_read_qword_masked_32le,
	75
	76	program_write_byte_32le,
	77	program_write_word_32le,
	78	program_write_dword_32le,
	79	program_write_masked_32le,
	80	program_write_qword_32le,
	81	program_write_qword_masked_32le
61	82	};
62	83
63	84
r894	r895
591	612	case CPUINFO_PTR_EXECUTE: /* provided by core */ break;
592	613	case CPUINFO_PTR_TRANSLATE: /* provided by core */ break;
593	614	case CPUINFO_PTR_DISASSEMBLE: /* provided by core */ break;
594		case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mips3_icount; break;
	615	case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mips->icount; break;
595	616
596	617	/* --- the following bits of info are returned as NULL-terminated strings --- */
597	618	case CPUINFO_STR_NAME: strcpy(info->s, "MIPS III"); break;
r894	r895
862	883
863	884
864	885	/*-------------------------------------------------
	886	program_read_qword_masked_32be - read a 64-bit
	887	big-endian value with explicit masking
	888	-------------------------------------------------*/
	889
	890	static UINT64 program_read_qword_masked_32be(offs_t offset, UINT64 mem_mask)
	891	{
	892	UINT64 result = 0;
	893	if ((mem_mask & U64(0xffffffff00000000)) != U64(0xffffffff00000000))
	894	result \|= (UINT64)program_read_masked_32be(offset, mem_mask >> 32) << 32;
	895	if ((mem_mask & U64(0x00000000ffffffff)) != U64(0x00000000ffffffff))
	896	result \|= program_read_masked_32be(offset + 4, mem_mask);
	897	return result;
	898	}
	899
	900
	901	/*-------------------------------------------------
865	902	program_read_qword_32le - read a 64-bit
866	903	little-endian value
867	904	-------------------------------------------------*/
r894	r895
874	911
875	912
876	913	/*-------------------------------------------------
	914	program_read_qword_masked_32le - read a 64-bit
	915	little-endian value with explicit masking
	916	-------------------------------------------------*/
	917
	918	static UINT64 program_read_qword_masked_32le(offs_t offset, UINT64 mem_mask)
	919	{
	920	UINT64 result = 0;
	921	if ((mem_mask & U64(0x00000000ffffffff)) != U64(0x00000000ffffffff))
	922	result \|= program_read_masked_32le(offset, mem_mask);
	923	if ((mem_mask & U64(0xffffffff00000000)) != U64(0xffffffff00000000))
	924	result \|= (UINT64)program_read_masked_32le(offset + 4, mem_mask >> 32) << 32;
	925	return result;
	926	}
	927
	928
	929	/*-------------------------------------------------
877	930	program_write_qword_32be - write a 64-bit
878	931	big-endian value
879	932	-------------------------------------------------*/
r894	r895
886	939
887	940
888	941	/*-------------------------------------------------
	942	program_write_qword_masked_32be - write a
	943	64-bit big-endian value with explicit masking
	944	-------------------------------------------------*/
	945
	946	static void program_write_qword_masked_32be(offs_t offset, UINT64 data, UINT64 mem_mask)
	947	{
	948	if ((mem_mask & U64(0xffffffff00000000)) != U64(0xffffffff00000000))
	949	program_write_masked_32be(offset, data >> 32, mem_mask >> 32);
	950	if ((mem_mask & U64(0x00000000ffffffff)) != U64(0x00000000ffffffff))
	951	program_write_masked_32be(offset + 4, data, mem_mask);
	952	}
	953
	954
	955	/*-------------------------------------------------
889	956	program_write_qword_32le - write a 64-bit
890	957	little-endian value
891	958	-------------------------------------------------*/
r894	r895
895	962	program_write_dword_32le(offset, data);
896	963	program_write_dword_32le(offset + 4, data >> 32);
897	964	}
	965
	966
	967	/*-------------------------------------------------
	968	program_write_qword_masked_32le - write a
	969	64-bit little-endian value with explicit masking
	970	-------------------------------------------------*/
	971
	972	static void program_write_qword_masked_32le(offs_t offset, UINT64 data, UINT64 mem_mask)
	973	{
	974	if ((mem_mask & U64(0x00000000ffffffff)) != U64(0x00000000ffffffff))
	975	program_write_masked_32le(offset, data, mem_mask);
	976	if ((mem_mask & U64(0xffffffff00000000)) != U64(0xffffffff00000000))
	977	program_write_masked_32le(offset + 4, data >> 32, mem_mask >> 32);
	978	}

src/emu/cpu/mips/mips3.c
r894	r895
264	264	{
265	265	/* common reset */
266	266	mips3com_reset(&mips3.core);
	267	mips3.nextpc = ~0;
267	268
268	269	/* set up the endianness */
269	270	if (mips3.core.bigendian)
r894	r895
365	366	}
366	367
367	368
	369	INLINE int RLONG_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask)
	370	{
	371	UINT32 tlbval = mips3.core.tlb_table[address >> 12];
	372	if (tlbval == 0xffffffff)
	373	{
	374	generate_tlb_exception(EXCEPTION_TLBLOAD, address);
	375	return 0;
	376	}
	377	result = (mips3.core.memory.readlong_masked)((tlbval & ~0xfff) \| (address & 0xfff), mem_mask);
	378	return 1;
	379	}
	380
	381
368	382	INLINE int RDOUBLE(offs_t address, UINT64 *result)
369	383	{
370	384	UINT32 tlbval = mips3.core.tlb_table[address >> 12];
r894	r895
378	392	}
379	393
380	394
	395	INLINE int RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask)
	396	{
	397	UINT32 tlbval = mips3.core.tlb_table[address >> 12];
	398	if (tlbval == 0xffffffff)
	399	{
	400	generate_tlb_exception(EXCEPTION_TLBLOAD, address);
	401	return 0;
	402	}
	403	result = (mips3.core.memory.readdouble_masked)((tlbval & ~0xfff) \| (address & 0xfff), mem_mask);
	404	return 1;
	405	}
	406
	407
381	408	INLINE void WBYTE(offs_t address, UINT8 data)
382	409	{
383	410	UINT32 tlbval = mips3.core.tlb_table[address >> 12];
r894	r895
408	435	}
409	436
410	437
	438	INLINE void WLONG_MASKED(offs_t address, UINT32 data, UINT32 mem_mask)
	439	{
	440	UINT32 tlbval = mips3.core.tlb_table[address >> 12];
	441	if (tlbval & 1)
	442	generate_tlb_exception(EXCEPTION_TLBSTORE, address);
	443	else
	444	(*mips3.core.memory.writelong_masked)(tlbval \| (address & 0xfff), data, mem_mask);
	445	}
	446
	447
411	448	INLINE void WDOUBLE(offs_t address, UINT64 data)
412	449	{
413	450	UINT32 tlbval = mips3.core.tlb_table[address >> 12];
r894	r895
418	455	}
419	456
420	457
	458	INLINE void WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask)
	459	{
	460	UINT32 tlbval = mips3.core.tlb_table[address >> 12];
	461	if (tlbval & 1)
	462	generate_tlb_exception(EXCEPTION_TLBSTORE, address);
	463	else
	464	(*mips3.core.memory.writedouble_masked)(tlbval \| (address & 0xfff), data, mem_mask);
	465	}
421	466
	467
	468
422	469	/***************************************************************************
423	470	COP0 (SYSTEM) EXECUTION HANDLING
424	471	***************************************************************************/
r894	r895
429	476	{
430	477	/* it doesn't really take 250 cycles to read this register, but it helps speed */
431	478	/* up loops that hammer on it */
432		if (mips3_icount >= 250)
433		mips3_icount -= 250;
	479	if (mips3.core.icount >= 250)
	480	mips3.core.icount -= 250;
434	481	else
435		mips3_icount = 0;
	482	mips3.core.icount = 0;
436	483	return (UINT32)((activecpu_gettotalcycles64() - mips3.core.count_zero_time) / 2);
437	484	}
438	485	else if (idx == COP0_Cause)
439	486	{
440	487	/* it doesn't really take 250 cycles to read this register, but it helps speed */
441	488	/* up loops that hammer on it */
442		if (mips3_icount >= 250)
443		mips3_icount -= 250;
	489	if (mips3.core.icount >= 250)
	490	mips3.core.icount -= 250;
444	491	else
445		mips3_icount = 0;
	492	mips3.core.icount = 0;
446	493	}
447	494	else if (idx == COP0_Random)
448	495	{
r894	r895
591	638
592	639	case 0x10: /* RFE */ invalid_instruction(op); break;
593	640	case 0x18: /* ERET */ logerror("ERET\n"); mips3.core.pc = mips3.core.cpr[0][COP0_EPC]; SR &= ~SR_EXL; check_irqs(); mips3.lld_value ^= 0xffffffff; mips3.ll_value ^= 0xffffffff; break;
	641	case 0x20: /* WAIT */ break;
594	642	default: invalid_instruction(op); break;
595	643	}
596	644	break;
r894	r895
1592	1640	int mips3_execute(int cycles)
1593	1641	{
1594	1642	/* count cycles and interrupt cycles */
1595		mips3_icount = cycles;
1596		mips3_icount -= mips3.interrupt_cycles;
	1643	mips3.core.icount = cycles;
	1644	mips3.core.icount -= mips3.interrupt_cycles;
1597	1645	mips3.interrupt_cycles = 0;
1598	1646
1599	1647	/* update timers & such */
r894	r895
1661	1709	temp64 = (INT64)(INT32)RSVAL32 * (INT64)(INT32)RTVAL32;
1662	1710	LOVAL64 = (INT32)temp64;
1663	1711	HIVAL64 = (INT32)(temp64 >> 32);
1664		mips3_icount -= 3;
	1712	mips3.core.icount -= 3;
1665	1713	break;
1666	1714	case 0x19: /* MULTU */
1667	1715	temp64 = (UINT64)RSVAL32 * (UINT64)RTVAL32;
1668	1716	LOVAL64 = (INT32)temp64;
1669	1717	HIVAL64 = (INT32)(temp64 >> 32);
1670		mips3_icount -= 3;
	1718	mips3.core.icount -= 3;
1671	1719	break;
1672	1720	case 0x1a: /* DIV */
1673	1721	if (RTVAL32)
r894	r895
1675	1723	LOVAL64 = (INT32)((INT32)RSVAL32 / (INT32)RTVAL32);
1676	1724	HIVAL64 = (INT32)((INT32)RSVAL32 % (INT32)RTVAL32);
1677	1725	}
1678		mips3_icount -= 35;
	1726	mips3.core.icount -= 35;
1679	1727	break;
1680	1728	case 0x1b: /* DIVU */
1681	1729	if (RTVAL32)
r894	r895
1683	1731	LOVAL64 = (INT32)(RSVAL32 / RTVAL32);
1684	1732	HIVAL64 = (INT32)(RSVAL32 % RTVAL32);
1685	1733	}
1686		mips3_icount -= 35;
	1734	mips3.core.icount -= 35;
1687	1735	break;
1688	1736	case 0x1c: /* DMULT */
1689	1737	temp64 = (INT64)RSVAL64 * (INT64)RTVAL64;
1690	1738	LOVAL64 = temp64;
1691	1739	HIVAL64 = (INT64)temp64 >> 63;
1692		mips3_icount -= 7;
	1740	mips3.core.icount -= 7;
1693	1741	break;
1694	1742	case 0x1d: /* DMULTU */
1695	1743	temp64 = (UINT64)RSVAL64 * (UINT64)RTVAL64;
1696	1744	LOVAL64 = temp64;
1697	1745	HIVAL64 = 0;
1698		mips3_icount -= 7;
	1746	mips3.core.icount -= 7;
1699	1747	break;
1700	1748	case 0x1e: /* DDIV */
1701	1749	if (RTVAL64)
r894	r895
1703	1751	LOVAL64 = (INT64)RSVAL64 / (INT64)RTVAL64;
1704	1752	HIVAL64 = (INT64)RSVAL64 % (INT64)RTVAL64;
1705	1753	}
1706		mips3_icount -= 67;
	1754	mips3.core.icount -= 67;
1707	1755	break;
1708	1756	case 0x1f: /* DDIVU */
1709	1757	if (RTVAL64)
r894	r895
1711	1759	LOVAL64 = RSVAL64 / RTVAL64;
1712	1760	HIVAL64 = RSVAL64 % RTVAL64;
1713	1761	}
1714		mips3_icount -= 67;
	1762	mips3.core.icount -= 67;
1715	1763	break;
1716	1764	case 0x20: /* ADD */
1717	1765	if (ENABLE_OVERFLOWS && RSVAL32 > ~RTVAL32) generate_exception(EXCEPTION_OVERFLOW, 1);
r894	r895
1813	1861	{
1814	1862	case 2: /* MUL */
1815	1863	RDVAL64 = (INT32)((INT32)RSVAL32 * (INT32)RTVAL32);
1816		mips3_icount -= 3;
	1864	mips3.core.icount -= 3;
1817	1865	break;
1818	1866	default: invalid_instruction(op);
1819	1867	}
r894	r895
1876	1924	case 0x3f: /* SD */ WDOUBLE(SIMMVAL+RSVAL32, RTVAL64); break;
1877	1925	default: /* ??? */ invalid_instruction(op); break;
1878	1926	}
1879		mips3_icount--;
	1927	mips3.core.icount--;
1880	1928
1881		} while (mips3_icount > 0 \|\| mips3.nextpc != ~0);
	1929	} while (mips3.core.icount > 0 \|\| mips3.nextpc != ~0);
1882	1930
1883		mips3_icount -= mips3.interrupt_cycles;
	1931	mips3.core.icount -= mips3.interrupt_cycles;
1884	1932	mips3.interrupt_cycles = 0;
1885		return cycles - mips3_icount;
	1933	return cycles - mips3.core.icount;
1886	1934	}
1887	1935
1888	1936
r894	r895
1894	1942	static void lwl_be(UINT32 op)
1895	1943	{
1896	1944	offs_t offs = SIMMVAL + RSVAL32;
	1945	int shift = 8 * (offs & 3);
	1946	UINT32 mask = 0xffffffffUL << shift;
1897	1947	UINT32 temp;
1898		if (RLONG(offs & ~3, &temp) && RTREG)
1899		{
1900		if (!(offs & 3)) RTVAL64 = (INT32)temp;
1901		else
1902		{
1903		int shift = 8 * (offs & 3);
1904		RTVAL64 = (INT32)((RTVAL32 & (0x00ffffff >> (24 - shift))) \| (temp << shift));
1905		}
1906		}
	1948
	1949	if (RLONG_MASKED(offs & ~3, &temp, ~(mask >> shift)) && RTREG)
	1950	RTVAL64 = (INT32)((RTVAL32 & ~mask) \| (temp << shift));
1907	1951	}
1908	1952
1909	1953	static void lwr_be(UINT32 op)
1910	1954	{
1911	1955	offs_t offs = SIMMVAL + RSVAL32;
	1956	int shift = 8 * (~offs & 3);
	1957	UINT32 mask = 0xffffffffUL >> shift;
1912	1958	UINT32 temp;
1913		if (RLONG(offs & ~3, &temp) && RTREG)
1914		{
1915		if ((offs & 3) == 3) RTVAL64 = (INT32)temp;
1916		else
1917		{
1918		int shift = 8 * (offs & 3);
1919		RTVAL64 = (INT32)((RTVAL32 & (0xffffff00 << shift)) \| (temp >> (24 - shift)));
1920		}
1921		}
	1959
	1960	if (RLONG_MASKED(offs & ~3, &temp, ~(mask << shift)) && RTREG)
	1961	RTVAL64 = (INT32)((RTVAL32 & ~mask) \| (temp >> shift));
1922	1962	}
1923	1963
1924	1964	static void ldl_be(UINT32 op)
1925	1965	{
1926	1966	offs_t offs = SIMMVAL + RSVAL32;
	1967	int shift = 8 * (offs & 7);
	1968	UINT64 mask = U64(0xffffffffffffffff) << shift;
1927	1969	UINT64 temp;
1928		if (RDOUBLE(offs & ~7, &temp) && RTREG)
1929		{
1930		if (!(offs & 7)) RTVAL64 = temp;
1931		else
1932		{
1933		UINT64 mask = ~((UINT64)0xff << 56);
1934		int shift = 8 * (offs & 7);
1935		RTVAL64 = (RTVAL64 & (mask >> (56 - shift))) \| (temp << shift);
1936		}
1937		}
	1970
	1971	if (RDOUBLE_MASKED(offs & ~7, &temp, ~(mask >> shift)) && RTREG)
	1972	RTVAL64 = (RTVAL64 & ~mask) \| (temp << shift);
1938	1973	}
1939	1974
1940	1975	static void ldr_be(UINT32 op)
1941	1976	{
1942	1977	offs_t offs = SIMMVAL + RSVAL32;
	1978	int shift = 8 * (~offs & 7);
	1979	UINT64 mask = U64(0xffffffffffffffff) >> shift;
1943	1980	UINT64 temp;
1944		if (RDOUBLE(offs & ~7, &temp) && RTREG)
1945		{
1946		if ((offs & 7) == 7) RTVAL64 = temp;
1947		else
1948		{
1949		UINT64 mask = ~((UINT64)0xff);
1950		int shift = 8 * (offs & 7);
1951		RTVAL64 = (RTVAL64 & (mask << shift)) \| (temp >> (56 - shift));
1952		}
1953		}
	1981
	1982	if (RDOUBLE_MASKED(offs & ~7, &temp, ~(mask << shift)) && RTREG)
	1983	RTVAL64 = (RTVAL64 & ~mask) \| (temp >> shift);
1954	1984	}
1955	1985
1956	1986	static void swl_be(UINT32 op)
1957	1987	{
1958	1988	offs_t offs = SIMMVAL + RSVAL32;
1959		if (!(offs & 3)) WLONG(offs, RTVAL32);
1960		else
1961		{
1962		UINT32 temp;
1963		int shift = 8 * (offs & 3);
1964		if (RLONG(offs & ~3, &temp))
1965		WLONG(offs & ~3, (temp & (0xffffff00 << (24 - shift))) \| (RTVAL32 >> shift));
1966		}
	1989	int shift = 8 * (offs & 3);
	1990	UINT32 mask = ~(0xffffffffUL >> shift);
	1991	WLONG_MASKED(offs & ~3, RTVAL32 >> shift, mask);
1967	1992	}
1968	1993
1969
1970	1994	static void swr_be(UINT32 op)
1971	1995	{
1972	1996	offs_t offs = SIMMVAL + RSVAL32;
1973		if ((offs & 3) == 3) WLONG(offs & ~3, RTVAL32);
1974		else
1975		{
1976		UINT32 temp;
1977		int shift = 8 * (offs & 3);
1978		if (RLONG(offs & ~3, &temp))
1979		WLONG(offs & ~3, (temp & (0x00ffffff >> shift)) \| (RTVAL32 << (24 - shift)));
1980		}
	1997	int shift = 8 * (~offs & 3);
	1998	UINT32 mask = ~(0xffffffffUL << shift);
	1999	WLONG_MASKED(offs & ~3, RTVAL32 << shift, mask);
1981	2000	}
1982	2001
1983	2002	static void sdl_be(UINT32 op)
1984	2003	{
1985	2004	offs_t offs = SIMMVAL + RSVAL32;
1986		if (!(offs & 7)) WDOUBLE(offs, RTVAL64);
1987		else
1988		{
1989		UINT64 temp;
1990		UINT64 mask = ~((UINT64)0xff);
1991		int shift = 8 * (offs & 7);
1992		if (RDOUBLE(offs & ~7, &temp))
1993		WDOUBLE(offs & ~7, (temp & (mask << (56 - shift))) \| (RTVAL64 >> shift));
1994		}
	2005	int shift = 8 * (offs & 7);
	2006	UINT64 mask = ~(U64(0xffffffffffffffff) >> shift);
	2007	WDOUBLE_MASKED(offs & ~7, RTVAL64 >> shift, mask);
1995	2008	}
1996	2009
1997	2010	static void sdr_be(UINT32 op)
1998	2011	{
1999	2012	offs_t offs = SIMMVAL + RSVAL32;
2000		if ((offs & 7) == 7) WDOUBLE(offs & ~7, RTVAL64);
2001		else
2002		{
2003		UINT64 temp;
2004		UINT64 mask = ~((UINT64)0xff << 56);
2005		int shift = 8 * (offs & 7);
2006		if (RDOUBLE(offs & ~7, &temp))
2007		WDOUBLE(offs & ~7, (temp & (mask >> shift)) \| (RTVAL64 << (56 - shift)));
2008		}
	2013	int shift = 8 * (~offs & 7);
	2014	UINT64 mask = ~(U64(0xffffffffffffffff) << shift);
	2015	WDOUBLE_MASKED(offs & ~7, RTVAL64 << shift, mask);
2009	2016	}
2010	2017
2011	2018
r894	r895
2013	2020	static void lwl_le(UINT32 op)
2014	2021	{
2015	2022	offs_t offs = SIMMVAL + RSVAL32;
	2023	int shift = 8 * (~offs & 3);
	2024	UINT32 mask = 0xffffffffUL << shift;
2016	2025	UINT32 temp;
2017		if (RLONG(offs & ~3, &temp) && RTREG)
2018		{
2019		if ((offs & 3) == 3) RTVAL64 = (INT32)temp;
2020		else
2021		{
2022		int shift = 8 * (offs & 3);
2023		RTVAL64 = (INT32)((RTVAL32 & (0x00ffffff >> shift)) \| (temp << (24 - shift)));
2024		}
2025		}
	2026
	2027	if (RLONG_MASKED(offs & ~3, &temp, ~(mask >> shift)) && RTREG)
	2028	RTVAL64 = (INT32)((RTVAL32 & ~mask) \| (temp << shift));
2026	2029	}
2027	2030
2028	2031	static void lwr_le(UINT32 op)
2029	2032	{
2030	2033	offs_t offs = SIMMVAL + RSVAL32;
	2034	int shift = 8 * (offs & 3);
	2035	UINT32 mask = 0xffffffffUL >> shift;
2031	2036	UINT32 temp;
2032		if (RLONG(offs & ~3, &temp) && RTREG)
2033		{
2034		if (!(offs & 3)) RTVAL64 = (INT32)temp;
2035		else
2036		{
2037		int shift = 8 * (offs & 3);
2038		RTVAL64 = (INT32)((RTVAL32 & (0xffffff00 << (24 - shift))) \| (temp >> shift));
2039		}
2040		}
	2037
	2038	if (RLONG_MASKED(offs & ~3, &temp, ~(mask << shift)) && RTREG)
	2039	RTVAL64 = (INT32)((RTVAL32 & ~mask) \| (temp >> shift));
2041	2040	}
2042	2041
2043	2042	static void ldl_le(UINT32 op)
2044	2043	{
2045	2044	offs_t offs = SIMMVAL + RSVAL32;
	2045	int shift = 8 * (~offs & 7);
	2046	UINT64 mask = U64(0xffffffffffffffff) << shift;
2046	2047	UINT64 temp;
2047		if (RDOUBLE(offs & ~7, &temp) && RTREG)
2048		{
2049		if ((offs & 7) == 7) RTVAL64 = temp;
2050		else
2051		{
2052		UINT64 mask = ~((UINT64)0xff << 56);
2053		int shift = 8 * (offs & 7);
2054		RTVAL64 = (RTVAL64 & (mask >> shift)) \| (temp << (56 - shift));
2055		}
2056		}
	2048
	2049	if (RDOUBLE_MASKED(offs & ~7, &temp, ~(mask >> shift)) && RTREG)
	2050	RTVAL64 = (RTVAL64 & ~mask) \| (temp << shift);
2057	2051	}
2058	2052
2059	2053	static void ldr_le(UINT32 op)
2060	2054	{
2061	2055	offs_t offs = SIMMVAL + RSVAL32;
	2056	int shift = 8 * (offs & 7);
	2057	UINT64 mask = U64(0xffffffffffffffff) >> shift;
2062	2058	UINT64 temp;
2063		if (RDOUBLE(offs & ~7, &temp) && RTREG)
2064		{
2065		if (!(offs & 7)) RTVAL64 = temp;
2066		else
2067		{
2068		UINT64 mask = ~((UINT64)0xff);
2069		int shift = 8 * (offs & 7);
2070		RTVAL64 = (RTVAL64 & (mask << (56 - shift))) \| (temp >> shift);
2071		}
2072		}
	2059
	2060	if (RDOUBLE_MASKED(offs & ~7, &temp, ~(mask << shift)) && RTREG)
	2061	RTVAL64 = (RTVAL64 & ~mask) \| (temp >> shift);
2073	2062	}
2074	2063
2075	2064	static void swl_le(UINT32 op)
2076	2065	{
2077	2066	offs_t offs = SIMMVAL + RSVAL32;
2078		if ((offs & 3) == 3) WLONG(offs & ~3, RTVAL32);
2079		else
2080		{
2081		UINT32 temp;
2082		int shift = 8 * (offs & 3);
2083		if (RLONG(offs & ~3, &temp))
2084		WLONG(offs & ~3, (temp & (0xffffff00 << shift)) \| (RTVAL32 >> (24 - shift)));
2085		}
	2067	int shift = 8 * (~offs & 3);
	2068	UINT32 mask = ~(0xffffffffUL >> shift);
	2069	WLONG_MASKED(offs & ~3, RTVAL32 >> shift, mask);
2086	2070	}
2087	2071
2088	2072	static void swr_le(UINT32 op)
2089	2073	{
2090	2074	offs_t offs = SIMMVAL + RSVAL32;
2091		if (!(offs & 3)) WLONG(offs, RTVAL32);
2092		else
2093		{
2094		UINT32 temp;
2095		int shift = 8 * (offs & 3);
2096		if (RLONG(offs & ~3, &temp))
2097		WLONG(offs & ~3, (temp & (0x00ffffff >> (24 - shift))) \| (RTVAL32 << shift));
2098		}
	2075	int shift = 8 * (offs & 3);
	2076	UINT32 mask = ~(0xffffffffUL << shift);
	2077	WLONG_MASKED(offs & ~3, RTVAL32 << shift, mask);
2099	2078	}
2100	2079
2101	2080	static void sdl_le(UINT32 op)
2102	2081	{
2103	2082	offs_t offs = SIMMVAL + RSVAL32;
2104		if ((offs & 7) == 7) WDOUBLE(offs & ~7, RTVAL64);
2105		else
2106		{
2107		UINT64 temp;
2108		UINT64 mask = ~((UINT64)0xff);
2109		int shift = 8 * (offs & 7);
2110		if (RDOUBLE(offs & ~7, &temp))
2111		WDOUBLE(offs & ~7, (temp & (mask << shift)) \| (RTVAL64 >> (56 - shift)));
2112		}
	2083	int shift = 8 * (~offs & 7);
	2084	UINT64 mask = ~(U64(0xffffffffffffffff) >> shift);
	2085	WDOUBLE_MASKED(offs & ~7, RTVAL64 >> shift, mask);
2113	2086	}
2114	2087
2115	2088	static void sdr_le(UINT32 op)
2116	2089	{
2117	2090	offs_t offs = SIMMVAL + RSVAL32;
2118		if (!(offs & 7)) WDOUBLE(offs, RTVAL64);
2119		else
2120		{
2121		UINT64 temp;
2122		UINT64 mask = ~((UINT64)0xff << 56);
2123		int shift = 8 * (offs & 7);
2124		if (RDOUBLE(offs & ~7, &temp))
2125		WDOUBLE(offs & ~7, (temp & (mask >> (56 - shift))) \| (RTVAL64 << shift));
2126		}
	2091	int shift = 8 * (offs & 7);
	2092	UINT64 mask = ~(U64(0xffffffffffffffff) << shift);
	2093	WDOUBLE_MASKED(offs & ~7, RTVAL64 << shift, mask);
2127	2094	}
2128	2095
2129	2096

src/emu/cpu/x86emit.h
r0	r895
	1	/***************************************************************************
	2
	3	x86emit.h
	4
	5	Generic x86/x64 code emitters.
	6
	7	Copyright (c) 1996-2007, Nicola Salmoria and the MAME Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	****************************************************************************
	11
	12	Important note:
	13
	14	It is assumed in 64-bit mode that all byte register accesses are
	15	intended to be to the low 8 bits (SPL,BPL,SIL,DIL) and not to the
	16	upper half (AH,CH,DH,BH).
	17
	18	***************************************************************************/
	19
	20
	21	/***************************************************************************
	22	CONSTANTS
	23	***************************************************************************/
	24
	25	/* 32-bit versus 64-bit opcode flag */
	26	#define OP_32BIT 0
	27	#define OP_64BIT 8
	28
	29
	30	/* 16 registers on x64, only 8 on x86 */
	31	#ifdef PTR64
	32	#define REG_MAX 16
	33	#else
	34	#define REG_MAX 8
	35	#endif
	36
	37
	38	/* invalid register index for "none" */
	39	#define REG_NONE REG_MAX
	40
	41
	42	/* 64-bit registers */
	43	#ifdef PTR64
	44	#define REG_RAX 0
	45	#define REG_RCX 1
	46	#define REG_RDX 2
	47	#define REG_RBX 3
	48	#define REG_RSP 4
	49	#define REG_RBP 5
	50	#define REG_RSI 6
	51	#define REG_RDI 7
	52	#define REG_R8 8
	53	#define REG_R9 9
	54	#define REG_R10 10
	55	#define REG_R11 11
	56	#define REG_R12 12
	57	#define REG_R13 13
	58	#define REG_R14 14
	59	#define REG_R15 15
	60	#endif
	61
	62	/* 32-bit registers */
	63	#define REG_EAX 0
	64	#define REG_ECX 1
	65	#define REG_EDX 2
	66	#define REG_EBX 3
	67	#define REG_ESP 4
	68	#define REG_EBP 5
	69	#define REG_ESI 6
	70	#define REG_EDI 7
	71	#ifdef PTR64
	72	#define REG_R8D 8
	73	#define REG_R9D 9
	74	#define REG_R10D 10
	75	#define REG_R11D 11
	76	#define REG_R12D 12
	77	#define REG_R13D 13
	78	#define REG_R14D 14
	79	#define REG_R15D 15
	80	#endif
	81
	82	/* 16-bit registers */
	83	#define REG_AX 0
	84	#define REG_CX 1
	85	#define REG_DX 2
	86	#define REG_BX 3
	87	#define REG_SP 4
	88	#define REG_BP 5
	89	#define REG_SI 6
	90	#define REG_DI 7
	91	#ifdef PTR64
	92	#define REG_R8W 8
	93	#define REG_R9W 9
	94	#define REG_R10W 10
	95	#define REG_R11W 11
	96	#define REG_R12W 12
	97	#define REG_R13W 13
	98	#define REG_R14W 14
	99	#define REG_R15W 15
	100	#endif
	101
	102	/* 8-bit registers */
	103	#define REG_AL 0
	104	#define REG_CL 1
	105	#define REG_DL 2
	106	#define REG_BL 3
	107	#ifndef PTR64
	108	#define REG_AH 4
	109	#define REG_CH 5
	110	#define REG_DH 6
	111	#define REG_BH 7
	112	#else
	113	#define REG_SPL 4
	114	#define REG_BPL 5
	115	#define REG_SIL 6
	116	#define REG_DIL 7
	117	#define REG_R8L 8
	118	#define REG_R9L 9
	119	#define REG_R10L 10
	120	#define REG_R11L 11
	121	#define REG_R12L 12
	122	#define REG_R13L 13
	123	#define REG_R14L 14
	124	#define REG_R15L 15
	125	#endif
	126
	127	/* 64-bit MMX registers */
	128	#define REG_MM0 0
	129	#define REG_MM1 1
	130	#define REG_MM2 2
	131	#define REG_MM3 3
	132	#define REG_MM4 4
	133	#define REG_MM5 5
	134	#define REG_MM6 6
	135	#define REG_MM7 7
	136	#ifdef PTR64
	137	#define REG_MM8 8
	138	#define REG_MM9 9
	139	#define REG_MM10 10
	140	#define REG_MM11 11
	141	#define REG_MM12 12
	142	#define REG_MM13 13
	143	#define REG_MM14 14
	144	#define REG_MM15 15
	145	#endif
	146
	147	/* 128-bit XMM registers */
	148	#define REG_XMM0 0
	149	#define REG_XMM1 1
	150	#define REG_XMM2 2
	151	#define REG_XMM3 3
	152	#define REG_XMM4 4
	153	#define REG_XMM5 5
	154	#define REG_XMM6 6
	155	#define REG_XMM7 7
	156	#ifdef PTR64
	157	#define REG_XMM8 8
	158	#define REG_XMM9 9
	159	#define REG_XMM10 10
	160	#define REG_XMM11 11
	161	#define REG_XMM12 12
	162	#define REG_XMM13 13
	163	#define REG_XMM14 14
	164	#define REG_XMM15 15
	165	#endif
	166
	167
	168	/* conditions */
	169	#define COND_A 7
	170	#define COND_AE 3
	171	#define COND_B 2
	172	#define COND_BE 6
	173	#define COND_C 2
	174	#define COND_E 4
	175	#define COND_Z 4
	176	#define COND_G 15
	177	#define COND_GE 13
	178	#define COND_L 12
	179	#define COND_LE 14
	180	#define COND_NA 6
	181	#define COND_NAE 2
	182	#define COND_NB 3
	183	#define COND_NBE 7
	184	#define COND_NC 3
	185	#define COND_NE 5
	186	#define COND_NG 14
	187	#define COND_NGE 12
	188	#define COND_NL 13
	189	#define COND_NLE 15
	190	#define COND_NO 1
	191	#define COND_NP 11
	192	#define COND_NS 9
	193	#define COND_NZ 5
	194	#define COND_O 0
	195	#define COND_P 10
	196	#define COND_PE 10
	197	#define COND_PO 11
	198	#define COND_S 8
	199	#define COND_Z 4
	200
	201
	202	/* floating point rounding modes */
	203	#define FPRND_NEAR 0
	204	#define FPRND_DOWN 1
	205	#define FPRND_UP 2
	206	#define FPRND_CHOP 3
	207
	208
	209	/* opcode flags (in upper 8 bits of opcode) */
	210	#define OPFLAG_8BITREG (1 << 24)
	211	#define OPFLAG_8BITRM (1 << 25)
	212
	213
	214	/* single byte opcodes */
	215	#define OP_ADD_Eb_Gb 0x00 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	216	#define OP_ADD_Ev_Gv 0x01
	217	#define OP_ADD_Gb_Eb 0x02 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	218	#define OP_ADD_Gv_Ev 0x03
	219	#define OP_ADD_AL_Ib 0x04
	220	#define OP_ADD_rAX_Iz 0x05
	221	#define OP_PUSH_ES 0x06
	222	#define OP_POP_ES 0x07
	223	#define OP_OR_Eb_Gb 0x08 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	224	#define OP_OR_Ev_Gv 0x09
	225	#define OP_OR_Gb_Eb 0x0a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	226	#define OP_OR_Gv_Ev 0x0b
	227	#define OP_OR_AL_Ib 0x0c
	228	#define OP_OR_eAX_Iv 0x0d
	229	#define OP_PUSH_CS 0x0e
	230	#define OP_EXTENDED 0x0f
	231
	232	#define OP_ADC_Eb_Gb 0x10 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	233	#define OP_ADC_Ev_Gv 0x11
	234	#define OP_ADC_Gb_Eb 0x12 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	235	#define OP_ADC_Gv_Ev 0x13
	236	#define OP_ADC_AL_Ib 0x14
	237	#define OP_ADC_rAX_Iz 0x15
	238	#define OP_PUSH_SS 0x16
	239	#define OP_POP_SS 0x17
	240	#define OP_SBB_Eb_Gb 0x18 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	241	#define OP_SBB_Ev_Gv 0x19
	242	#define OP_SBB_Gb_Eb 0x1a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	243	#define OP_SBB_Gv_Ev 0x1b
	244	#define OP_SBB_AL_Ib 0x1c
	245	#define OP_SBB_eAX_Iv 0x1d
	246	#define OP_PUSH_DS 0x1e
	247	#define OP_POP_DS 0x1f
	248
	249	#define OP_AND_Eb_Gb 0x20 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	250	#define OP_AND_Ev_Gv 0x21
	251	#define OP_AND_Gb_Eb 0x22 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	252	#define OP_AND_Gv_Ev 0x23
	253	#define OP_AND_AL_Ib 0x24
	254	#define OP_AND_rAX_Iz 0x25
	255	#define PREFIX_ES 0x26
	256	#define OP_DAA 0x27
	257	#define OP_SUB_Eb_Gb 0x28 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	258	#define OP_SUB_Ev_Gv 0x29
	259	#define OP_SUB_Gb_Eb 0x2a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	260	#define OP_SUB_Gv_Ev 0x2b
	261	#define OP_SUB_AL_Ib 0x2c
	262	#define OP_SUB_eAX_Iv 0x2d
	263	#define PREFIX_CS 0x2e
	264	#define OP_DAS 0x2f
	265
	266	#define OP_XOR_Eb_Gb 0x30 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	267	#define OP_XOR_Ev_Gv 0x31
	268	#define OP_XOR_Gb_Eb 0x32 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	269	#define OP_XOR_Gv_Ev 0x33
	270	#define OP_XOR_AL_Ib 0x34
	271	#define OP_XOR_rAX_Iz 0x35
	272	#define PREFIX_SS 0x36
	273	#define OP_AAA 0x37
	274	#define OP_CMP_Eb_Gb 0x38 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	275	#define OP_CMP_Ev_Gv 0x39
	276	#define OP_CMP_Gb_Eb 0x3a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	277	#define OP_CMP_Gv_Ev 0x3b
	278	#define OP_CMP_AL_Ib 0x3c
	279	#define OP_CMP_eAX_Iv 0x3d
	280	#define PREFIX_DS 0x3e
	281	#define OP_AAS 0x3f
	282
	283	#define OP_REX 0x40
	284	#define OP_REX_B 0x41
	285	#define OP_REX_X 0x42
	286	#define OP_REX_XB 0x43
	287	#define OP_REX_R 0x44
	288	#define OP_REX_RB 0x45
	289	#define OP_REX_RX 0x46
	290	#define OP_REX_RXB 0x47
	291	#define OP_REX_W 0x48
	292	#define OP_REX_WB 0x49
	293	#define OP_REX_WX 0x4a
	294	#define OP_REX_WXB 0x4b
	295	#define OP_REX_WR 0x4c
	296	#define OP_REX_WRB 0x4d
	297	#define OP_REX_WRX 0x4e
	298	#define OP_REX_WRXB 0x4f
	299
	300	#define OP_PUSH_rAX 0x50
	301	#define OP_PUSH_rCX 0x51
	302	#define OP_PUSH_rDX 0x52
	303	#define OP_PUSH_rBX 0x53
	304	#define OP_PUSH_rSP 0x54
	305	#define OP_PUSH_rBP 0x55
	306	#define OP_PUSH_rSI 0x56
	307	#define OP_PUSH_rDI 0x57
	308	#define OP_POP_rAX 0x58
	309	#define OP_POP_rCX 0x59
	310	#define OP_POP_rDX 0x5a
	311	#define OP_POP_rBX 0x5b
	312	#define OP_POP_rSP 0x5c
	313	#define OP_POP_rBP 0x5d
	314	#define OP_POP_rSI 0x5e
	315	#define OP_POP_rDI 0x5f
	316
	317	#define OP_PUSHA 0x60
	318	#define OP_POPA 0x61
	319	#define OP_BOUND_Gv_Ma 0x62
	320	#define OP_ARPL_Ew_Gw 0x63
	321	#define OP_MOVSXD_Gv_Ev 0x63
	322	#define PREFIX_FS 0x64
	323	#define PREFIX_GS 0x65
	324	#define PREFIX_OPSIZE 0x66
	325	#define PREFIX_ADSIZE 0x67
	326	#define OP_PUSH_Iz 0x68
	327	#define OP_IMUL_Gv_Ev_Iz 0x69
	328	#define OP_PUSH_Ib 0x6a
	329	#define OP_IMUL_Gv_Ev_Ib 0x6b
	330	#define OP_INS_Yb_DX 0x6c
	331	#define OP_INS_Yz_DX 0x6d
	332	#define OP_OUTS_DX_Xb 0x6e
	333	#define OP_OUTS_DX_Xz 0x6f
	334
	335	#define OP_JCC_O_Jb 0x70
	336	#define OP_JCC_NO_Jb 0x71
	337	#define OP_JCC_B_Jb 0x72
	338	#define OP_JCC_C_Jb 0x72
	339	#define OP_JCC_NAE_Jb 0x72
	340	#define OP_JCC_AE_Jb 0x73
	341	#define OP_JCC_NB_Jb 0x73
	342	#define OP_JCC_NC_Jb 0x73
	343	#define OP_JCC_E_Jb 0x74
	344	#define OP_JCC_Z_Jb 0x74
	345	#define OP_JCC_NE_Jb 0x75
	346	#define OP_JCC_NZ_Jb 0x75
	347	#define OP_JCC_BE_Jb 0x76
	348	#define OP_JCC_NA_Jb 0x76
	349	#define OP_JCC_A_Jb 0x77
	350	#define OP_JCC_NBE_Jb 0x77
	351	#define OP_JCC_S_Jb 0x78
	352	#define OP_JCC_NS_Jb 0x79
	353	#define OP_JCC_P_Jb 0x7a
	354	#define OP_JCC_PE_Jb 0x7a
	355	#define OP_JCC_NP_Jb 0x7b
	356	#define OP_JCC_PO_Jb 0x7b
	357	#define OP_JCC_L_Jb 0x7c
	358	#define OP_JCC_NGE_Jb 0x7c
	359	#define OP_JCC_NL_Jb 0x7d
	360	#define OP_JCC_GE_Jb 0x7d
	361	#define OP_JCC_LE_Jb 0x7e
	362	#define OP_JCC_NG_Jb 0x7e
	363	#define OP_JCC_NLE_Jb 0x7f
	364	#define OP_JCC_G_Jb 0x7f
	365
	366	#define OP_G1_Eb_Ib 0x80 \| OPFLAG_8BITRM
	367	#define OP_G1_Ev_Iz 0x81
	368	#define OP_G1_Eb_Ibx 0x82 \| OPFLAG_8BITRM
	369	#define OP_G1_Ev_Ib 0x83
	370	#define OP_TEST_Eb_Gb 0x84 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	371	#define OP_TEST_Ev_Gv 0x85
	372	#define OP_XCHG_Eb_Gb 0x86 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	373	#define OP_XCHG_Ev_Gv 0x87
	374	#define OP_MOV_Eb_Gb 0x88 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	375	#define OP_MOV_Ev_Gv 0x89
	376	#define OP_MOV_Gb_Eb 0x8a \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	377	#define OP_MOV_Gv_Ev 0x8b
	378	#define OP_MOV_Ev_Sw 0x8c
	379	#define OP_LEA_Gv_M 0x8d
	380	#define OP_MOV_Sw_Ew 0x8e
	381	#define OP_G1A_Ev 0x8f
	382
	383	#define OP_NOP 0x90
	384	#define OP_PAUSE 0x90
	385	#define OP_XCHG_rCX 0x91
	386	#define OP_XCHG_rDX 0x92
	387	#define OP_XCHG_rBX 0x93
	388	#define OP_XCHG_rSP 0x94
	389	#define OP_XCHG_rBP 0x95
	390	#define OP_XCHG_rSI 0x96
	391	#define OP_XCHG_rDI 0x97
	392	#define OP_CBW 0x98
	393	#define OP_CWDE 0x98
	394	#define OP_CDQE 0x98
	395	#define OP_CWD 0x99
	396	#define OP_CDQ 0x99
	397	#define OP_CQO 0x99
	398	#define OP_CALLF_Ap 0x9a
	399	#define OP_FWAIT 0x9b
	400	#define OP_PUSHF_Fv 0x9c
	401	#define OP_POPF_Fv 0x9d
	402	#define OP_SAHF 0x9e
	403	#define OP_LAHF 0x9f
	404
	405	#define OP_MOV_AL_Ob 0xa0
	406	#define OP_MOV_rAX_Ov 0xa1
	407	#define OP_MOV_Ob_AL 0xa2
	408	#define OP_MOV_Ov_rAX 0xa3
	409	#define OP_MOVS_Xb_Yb 0xa4
	410	#define OP_MOVS_Xv_Yv 0xa5
	411	#define OP_CMPS_Xb_Yb 0xa6
	412	#define OP_CMPS_Xv_Yv 0xa7
	413	#define OP_TEST_AL_Ib 0xa8
	414	#define OP_TEST_rAX_Iz 0xa9
	415	#define OP_STOS_Yb_AL 0xaa
	416	#define OP_STOS_Yv_rAX 0xab
	417	#define OP_LODS_AL_Xb 0xac
	418	#define OP_LODS_rAX_Xv 0xad
	419	#define OP_SCAS_AL_Yb 0xae
	420	#define OP_SCAC_rAX_Yv 0xaf
	421
	422	#define OP_MOV_AL_Ib 0xb0
	423	#define OP_MOV_CL_Ib 0xb1
	424	#define OP_MOV_DL_Ib 0xb2
	425	#define OP_MOV_BL_Ib 0xb3
	426	#define OP_MOV_AH_Ib 0xb4
	427	#define OP_MOV_CH_Ib 0xb5
	428	#define OP_MOV_DH_Ib 0xb6
	429	#define OP_MOV_BH_Ib 0xb7
	430	#define OP_MOV_rAX_Iv 0xb8
	431	#define OP_MOV_rCX_Iv 0xb9
	432	#define OP_MOV_rDX_Iv 0xba
	433	#define OP_MOV_rBX_Iv 0xbb
	434	#define OP_MOV_rSP_Iv 0xbc
	435	#define OP_MOV_rBP_Iv 0xbd
	436	#define OP_MOV_rSI_Iv 0xbe
	437	#define OP_MOV_rDI_Iv 0xbf
	438
	439	#define OP_G2_Eb_Ib 0xc0 \| OPFLAG_8BITRM
	440	#define OP_G2_Ev_Ib 0xc1
	441	#define OP_RETN_Iw 0xc2
	442	#define OP_RETN 0xc3
	443	#define OP_LES_Gz_Mp 0xc4
	444	#define OP_LDS_Gz_Mp 0xc5
	445	#define OP_G11_Eb_Ib 0xc6 \| OPFLAG_8BITRM
	446	#define OP_G11_Ev_Iz 0xc7
	447	#define OP_ENTER_Iw_Ib 0xc8
	448	#define OP_LEAVE 0xc9
	449	#define OP_RETF_Iw 0xca
	450	#define OP_RETF 0xcb
	451	#define OP_INT_3 0xcc
	452	#define OP_INT_Ib 0xcd
	453	#define OP_INTO 0xce
	454	#define OP_IRET 0xcf
	455
	456	#define OP_G2_Eb_1 0xd0 \| OPFLAG_8BITRM
	457	#define OP_G2_Ev_1 0xd1
	458	#define OP_G2_Eb_CL 0xd2 \| OPFLAG_8BITRM
	459	#define OP_G2_Ev_CL 0xd3
	460	#define OP_AAM 0xd4
	461	#define OP_AAD 0xd5
	462	#define OP_XLAT 0xd7
	463	#define OP_ESC_D8 0xd8
	464	#define OP_ESC_D9 0xd9
	465	#define OP_ESC_DA 0xda
	466	#define OP_ESC_DB 0xdb
	467	#define OP_ESC_DC 0xdc
	468	#define OP_ESC_DD 0xdd
	469	#define OP_ESC_DE 0xde
	470	#define OP_ESC_DF 0xdf
	471
	472	#define OP_LOOPNE_Jb 0xe0
	473	#define OP_LOOPE_Jb 0xe1
	474	#define OP_LOOP_Jb 0xe2
	475	#define OP_JrCXZ_Jb 0xe3
	476	#define OP_IN_AL_Ib 0xe4
	477	#define OP_IN_eAX_Ib 0xe5
	478	#define OP_OUT_Ib_AL 0xe6
	479	#define OP_OUT_Ib_eAX 0xe7
	480	#define OP_CALL_Jz 0xe8
	481	#define OP_JMP_Jz 0xe9
	482	#define OP_JMPF_AP 0xea
	483	#define OP_JMP_Jb 0xeb
	484	#define OP_IN_AL_DX 0xec
	485	#define OP_IN_eAX_D 0xed
	486	#define OP_OUT_DX_AL 0xee
	487	#define OP_OUT_DX_eAX 0xef
	488
	489	#define PREFIX_LOCK 0xf0
	490	#define PREFIX_REPNE 0xf2
	491	#define PREFIX_REPE 0xf3
	492	#define OP_HLT 0xf4
	493	#define OP_CMC 0xf5
	494	#define OP_G3_Eb 0xf6 \| OPFLAG_8BITRM
	495	#define OP_G3_Ev 0xf7
	496	#define OP_CLC 0xf8
	497	#define OP_STC 0xf9
	498	#define OP_CLI 0xfa
	499	#define OP_STI 0xfb
	500	#define OP_CLD 0xfc
	501	#define OP_STD 0xfd
	502	#define OP_G4 0xfe
	503	#define OP_G5 0xff
	504
	505
	506	/* double byte opcodes */
	507	#define OP_G6 0x0f00
	508	#define OP_G7 0x0f01
	509	#define OP_LAR_Gv_Ew 0x0f02
	510	#define OP_LSL_Gv_Ew 0x0f03
	511	#define OP_SYSCALL 0x0f05
	512	#define OP_CLTS 0x0f06
	513	#define OP_SYSRET 0x0f07
	514	#define OP_INVD 0x0f08
	515	#define OP_WBINVD 0x0f09
	516	#define OP_UD2 0x0f0b
	517
	518	#define OP_MOVUPS_Vps_Wps 0x0f10
	519	#define OP_MOVSS_Vss_Wss 0xf30f10
	520	#define OP_MOVUPD_Vpd_Wpd 0x660f10
	521	#define OP_MOVSD_Vsd_Wsd 0xf20f10
	522	#define OP_MOVUPS_Wps_Vps 0x0f11
	523	#define OP_MOVSS_Wss_Vss 0xf30f11
	524	#define OP_MOVUPD_Wpd_Vpd 0x660f11
	525	#define OP_MOVSD_Wsd_Vsd 0xf20f11
	526	#define OP_MOVLPS_Vq_Mq 0x0f12
	527	#define OP_MOVLPD_Vq_Mq 0x660f12
	528	#define OP_MOVHLPS_Vq_Uq 0x0f12
	529	#define OP_MOVDDUP_Vq_Wq 0xf20f12
	530	#define OP_MOVSLDUP_Vq_Wq 0xf30f12
	531	#define OP_MOVLPS_Mq_Vq 0x0f13
	532	#define OP_MOVLPD_Mq_Vq 0x660f13
	533	#define OP_UNPCKLPS_Vps_Wq 0x0f14
	534	#define OP_UNPCKLPD_Vpd_Wq 0x660f14
	535	#define OP_UNPCKHPS_Vps_Wq 0x0f15
	536	#define OP_UNPCKHPD_Vpd_Wq 0x660f15
	537	#define OP_MOVHPS_Vq_Mq 0x0f16
	538	#define OP_MOVHPD_Vq_Mq 0x660f16
	539	#define OP_MOVLHPS_Vq_Uq 0x0f16
	540	#define OP_MOVSHDUP_Vq_Wq 0xf30f16
	541	#define OP_MOVHPS_Mq_Vq 0x0f17
	542	#define OP_MOVHPD_Mq_Vq 0x660f17
	543	#define OP_PREFETCH_G16 0x0f18
	544
	545	#define OP_MOV_Rd_Cd 0x0f20
	546	#define OP_MOV_Rd_Dd 0x0f21
	547	#define OP_MOV_Cd_Rd 0x0f22
	548	#define OP_MOV_Dd_Rd 0x0f23
	549	#define OP_MOVAPS_Vps_Wps 0x0f28
	550	#define OP_MOVAPD_Vpd_Wpd 0x660f28
	551	#define OP_MOVAPS_Wps_Vps 0x0f29
	552	#define OP_MOVAPD_Wpd_Vpd 0x660f29
	553	#define OP_CVTPI2PS_Vps_Qq 0x0f2a
	554	#define OP_CVTSI2SS_Vss_Ed 0xf30f2a
	555	#define OP_CVTPI2PD_Vpd_Qq 0x660f2a
	556	#define OP_CVTSI2SD_Vsd_Ed 0xf20f2a
	557	#define OP_MOVNTPS_Mps_Vps 0x0f2b
	558	#define OP_MOVNTPD_Mpd_Vpd 0x660f2b
	559	#define OP_CVTTPS2PI_Pq_Wq 0x0f2c
	560	#define OP_CVTTSS2SI_Gd_Wss 0xf30f2c
	561	#define OP_CVTTPD2PI_Pq_Wpd 0x660f2c
	562	#define OP_CVTTSD2SI_Gd_Wsd 0xf20f2c
	563	#define OP_CVTPS2PI_Pq_Wq 0x0f2d
	564	#define OP_CVTSS2SI_Gd_Wss 0xf30f2d
	565	#define OP_CVTPD2PI_Pq_Wpd 0x660f2d
	566	#define OP_CVTSD2SI_Gd_Wsd 0xf20f2d
	567	#define OP_UCOMISS_Vss_Wss 0x0f2e
	568	#define OP_UCOMISD_Vsd_Wsd 0x660f2e
	569	#define OP_COMISS_Vss_Wss 0x0f2f
	570	#define OP_COMISD_Vsd_Wsd 0x660f2f
	571
	572	#define OP_WRMSR 0x0f30
	573	#define OP_RDTSC 0x0f31
	574	#define OP_RDMSR 0x0f32
	575	#define OP_RDPMC 0x0f33
	576	#define OP_SYSENTER 0x0f34
	577	#define OP_SYSEXIT 0x0f35
	578
	579	#define OP_CMOV_O_Gv_Ev 0x0f40
	580	#define OP_CMOV_NO_Gv_Ev 0x0f41
	581	#define OP_CMOV_B_Gv_Ev 0x0f42
	582	#define OP_CMOV_C_Gv_Ev 0x0f42
	583	#define OP_CMOV_AE_Gv_Ev 0x0f43
	584	#define OP_CMOV_NC_Gv_Ev 0x0f43
	585	#define OP_CMOV_E_Gv_Ev 0x0f44
	586	#define OP_CMOV_Z_Gv_Ev 0x0f44
	587	#define OP_CMOV_NE_Gv_Ev 0x0f45
	588	#define OP_CMOV_NZ_Gv_Ev 0x0f45
	589	#define OP_CMOV_BE_Gv_Ev 0x0f46
	590	#define OP_CMOV_A_Gv_Ev 0x0f47
	591	#define OP_CMOV_S_Gv_Ev 0x0f48
	592	#define OP_CMOV_NS_Gv_Ev 0x0f49
	593	#define OP_CMOV_P_Gv_Ev 0x0f4a
	594	#define OP_CMOV_PE_Gv_Ev 0x0f4a
	595	#define OP_CMOV_NP_Gv_Ev 0x0f4b
	596	#define OP_CMOV_PO_Gv_Ev 0x0f4b
	597	#define OP_CMOV_L_Gv_Ev 0x0f4c
	598	#define OP_CMOV_NGE_Gv_Ev 0x0f4c
	599	#define OP_CMOV_NL_Gv_Ev 0x0f4d
	600	#define OP_CMOV_GE_Gv_Ev 0x0f4d
	601	#define OP_CMOV_LE_Gv_Ev 0x0f4e
	602	#define OP_CMOV_NG_Gv_Ev 0x0f4e
	603	#define OP_CMOV_NLE_Gv_Ev 0x0f4f
	604	#define OP_CMOV_G_Gv_Ev 0x0f4f
	605
	606	#define OP_MOVMSKPS_Gd_Ups 0x0f50
	607	#define OP_MOVMSKPD_Gd_Upd 0x660f50
	608	#define OP_SQRTPS_Vps_Wps 0x0f51
	609	#define OP_SQRTSS_Vss_Wss 0xf30f51
	610	#define OP_SQRTPD_Vpd_Wpd 0x660f51
	611	#define OP_SQRTSD_Vsd_Wsd 0xf20f51
	612	#define OP_RSQRTPS_Vps_Wps 0x0f52
	613	#define OP_RSQRTSS_Vss_Wss 0xf30f52
	614	#define OP_RCPPS_Vps_Wps 0x0f53
	615	#define OP_RCPSS_Vss_Wss 0xf30f53
	616	#define OP_ANDPS_Vps_Wps 0x0f54
	617	#define OP_ANDPD_Vpd_Wpd 0x660f54
	618	#define OP_ANDNPS_Vps_Wps 0x0f55
	619	#define OP_ANDNPD_Vpd_Wpd 0x660f55
	620	#define OP_ORPS_Vps_Wps 0x0f56
	621	#define OP_ORPD_Vpd_Wpd 0x660f56
	622	#define OP_XORPS_Vps_Wps 0x0f57
	623	#define OP_XORPD_Vpd_Wpd 0x660f57
	624	#define OP_ADDPS_Vps_Wps 0x0f58
	625	#define OP_ADDSS_Vss_Wss 0xf30f58
	626	#define OP_ADDPD_Vpd_Wpd 0x660f58
	627	#define OP_ADDSD_Vsd_Wsd 0xf20f58
	628	#define OP_MULPS_Vps_Wps 0x0f59
	629	#define OP_MULSS_Vss_Wss 0xf30f59
	630	#define OP_MULPD_Vpd_Wpd 0x660f59
	631	#define OP_MULSD_Vsd_Wsd 0xf20f59
	632	#define OP_CVTPS2PD_Vpd_Wq 0x0f5a
	633	#define OP_CVTSS2SD_Vsd_Wss 0xf30f5a
	634	#define OP_CVTPD2PS_Vps_Wpd 0x660f5a
	635	#define OP_CVTSD2SS_Vss_Wsd 0xf20f5a
	636	#define OP_CVTDQ2PS_Vps_Wdq 0x0f5b
	637	#define OP_CVTPS2DQ_Vdq_Wps 0x660f5b
	638	#define OP_CVTTPS2DQ_Vdq_Wps 0xf30f5b
	639	#define OP_SUBPS_Vps_Wps 0x0f5c
	640	#define OP_SUBSS_Vss_Wss 0xf30f5c
	641	#define OP_SUBPD_Vpd_Wpd 0x660f5c
	642	#define OP_SUBSD_Vsd_Wsd 0xf20f5c
	643	#define OP_MINPS_Vps_Wps 0x0f5d
	644	#define OP_MINSS_Vss_Wss 0xf30f5d
	645	#define OP_MINPD_Vpd_Wpd 0x660f5d
	646	#define OP_MINSD_Vsd_Wsd 0xf20f5d
	647	#define OP_DIVPS_Vps_Wps 0x0f5e
	648	#define OP_DIVSS_Vss_Wss 0xf30f5e
	649	#define OP_DIVPD_Vpd_Wpd 0x660f5e
	650	#define OP_DIVSD_Vsd_Wsd 0xf20f5e
	651	#define OP_MAXPS_Vps_Wps 0x0f5f
	652	#define OP_MAXSS_Vss_Wss 0xf30f5f
	653	#define OP_MAXPD_Vpd_Wpd 0x660f5f
	654	#define OP_MAXSD_Vsd_Wsd 0xf20f5f
	655
	656	#define OP_PUNPCKLBW_Pq_Qd 0x0f60
	657	#define OP_PUNPCKLBW_Vdq_Wdq 0x660f60
	658	#define OP_PUNPCKLWD_Pq_Qd 0x0f61
	659	#define OP_PUNPCKLWD_Vdq_Wdq 0x660f61
	660	#define OP_PUNPCKLDQ_Pq_Qd 0x0f62
	661	#define OP_PUNPCKLDQ_Vdq_Wdq 0x660f62
	662	#define OP_PACKSSWB_Pq_Qq 0x0f63
	663	#define OP_PACKSSWB_Vdq_Wdq 0x660f63
	664	#define OP_PCMPGTB_Pq_Qq 0x0f64
	665	#define OP_PCMPGTB_Vdq_Wdq 0x660f64
	666	#define OP_PCMPGTW_Pq_Qq 0x0f65
	667	#define OP_PCMPGTW_Vdq_Wdq 0x660f65
	668	#define OP_PCMPGTD_Pq_Qq 0x0f66
	669	#define OP_PCMPGTD_Vdq_Wdq 0x660f66
	670	#define OP_PACKUSWB_Pq_Qq 0x0f67
	671	#define OP_PACKUSWB_Vdq_Wdq 0x660f67
	672	#define OP_PUNPCKHBW_Pq_Qq 0x0f68
	673	#define OP_PUNPCKHBW_Vdq_Qdq 0x660f68
	674	#define OP_PUNPCKHWD_Pq_Qq 0x0f69
	675	#define OP_PUNPCKHWD_Vdq_Qdq 0x660f69
	676	#define OP_PUNPCKHDQ_Pq_Qq 0x0f6a
	677	#define OP_PUNPCKHDQ_Vdq_Qdq 0x660f6a
	678	#define OP_PACKSSDW_Pq_Qq 0x0f6b
	679	#define OP_PACKSSDW_Vdq_Qdq 0x660f6b
	680	#define OP_PUNPCKLQDQ_Vdq_Wdq 0x660f6c
	681	#define OP_PUNPCKHQDQ_Vdq_Wdq 0x660f6d
	682	#define OP_MOVD_Pd_Ed 0x0f6e
	683	#define OP_MOVD_Vd_Ed 0x660f6e
	684	#define OP_MOVQ_Pq_Qq 0x0f6f
	685	#define OP_MOVDQA_Vdq_Wdq 0x660f6f
	686	#define OP_MOVDQU_Vdq_Wdq 0xf30f6f
	687
	688	#define OP_PSHUFW_Pq_Qq_Ib 0x0f70
	689	#define OP_PSHUFD_Vdq_Wdq_Ib 0x660f70
	690	#define OP_PSHUFHW_Vdq_Wdq_Ib 0xf30f70
	691	#define OP_PSHUFLW_Vdq_Wdq_Ib 0xf20f70
	692	#define OP_G12 0x0f71
	693	#define OP_G13 0x0f72
	694	#define OP_G14 0x0f73
	695	#define OP_PCMPEQB_Pq_Qq 0x0f74
	696	#define OP_PCMPEQB_Vdq_Wdq 0x660f74
	697	#define OP_PCMPEQW_Pq_Qq 0x0f75
	698	#define OP_PCMPEQW_Vdq_Wdq 0x660f75
	699	#define OP_PCMPEQD_Pq_Qq 0x0f76
	700	#define OP_PCMPEQD_Vdq_Wdq 0x660f76
	701	#define OP_EMMS 0x0f77
	702	#define OP_HADDPD_Vpd_Wpd 0x660f7c
	703	#define OP_HADDPS_Vps_Wps 0xf20f7c
	704	#define OP_HSUBPD_Vpd_Wpd 0x660f7d
	705	#define OP_HSUBPS_Vps_Wps 0xf20f7d
	706	#define OP_MOVD_Ed_Pd 0x0f7e
	707	#define OP_MOVD_Ed_Vd 0x660f7e
	708	#define OP_MOVQ_Vq_Wq 0xf30f7e
	709	#define OP_MOVQ_Qq_Pq 0x0f7f
	710	#define OP_MOVDQA_Wdq_Vdq 0x660f7f
	711	#define OP_MOVDQU_Wdq_Vdq 0xf30f7f
	712
	713	#define OP_JCC_O_Jv 0x0f80
	714	#define OP_JCC_NO_Jv 0x0f81
	715	#define OP_JCC_B_Jv 0x0f82
	716	#define OP_JCC_C_Jv 0x0f82
	717	#define OP_JCC_NAE_Jv 0x0f82
	718	#define OP_JCC_AE_Jv 0x0f83
	719	#define OP_JCC_NB_Jv 0x0f83
	720	#define OP_JCC_NC_Jv 0x0f83
	721	#define OP_JCC_E_Jv 0x0f84
	722	#define OP_JCC_Z_Jv 0x0f84
	723	#define OP_JCC_NE_Jv 0x0f85
	724	#define OP_JCC_NZ_Jv 0x0f85
	725	#define OP_JCC_BE_Jv 0x0f86
	726	#define OP_JCC_NA_Jv 0x0f86
	727	#define OP_JCC_A_Jv 0x0f87
	728	#define OP_JCC_NBE_Jv 0x0f87
	729	#define OP_JCC_S_Jv 0x0f88
	730	#define OP_JCC_NS_Jv 0x0f89
	731	#define OP_JCC_P_Jv 0x0f8a
	732	#define OP_JCC_PE_Jv 0x0f8a
	733	#define OP_JCC_NP_Jv 0x0f8b
	734	#define OP_JCC_PO_Jv 0x0f8b
	735	#define OP_JCC_L_Jv 0x0f8c
	736	#define OP_JCC_NGE_Jv 0x0f8c
	737	#define OP_JCC_NL_Jv 0x0f8d
	738	#define OP_JCC_GE_Jv 0x0f8d
	739	#define OP_JCC_LE_Jv 0x0f8e
	740	#define OP_JCC_NG_Jv 0x0f8e
	741	#define OP_JCC_NLE_Jv 0x0f8f
	742	#define OP_JCC_G_Jv 0x0f8f
	743
	744	#define OP_SETCC_O_Eb 0x0f90 \| OPFLAG_8BITRM
	745	#define OP_SETCC_NO_Eb 0x0f91 \| OPFLAG_8BITRM
	746	#define OP_SETCC_B_Eb 0x0f92 \| OPFLAG_8BITRM
	747	#define OP_SETCC_C_Eb 0x0f92 \| OPFLAG_8BITRM
	748	#define OP_SETCC_NAE_Eb 0x0f92 \| OPFLAG_8BITRM
	749	#define OP_SETCC_AE_Eb 0x0f93 \| OPFLAG_8BITRM
	750	#define OP_SETCC_NB_Eb 0x0f93 \| OPFLAG_8BITRM
	751	#define OP_SETCC_NC_Eb 0x0f93 \| OPFLAG_8BITRM
	752	#define OP_SETCC_E_Eb 0x0f94 \| OPFLAG_8BITRM
	753	#define OP_SETCC_Z_Eb 0x0f94 \| OPFLAG_8BITRM
	754	#define OP_SETCC_NE_Eb 0x0f95 \| OPFLAG_8BITRM
	755	#define OP_SETCC_NZ_Eb 0x0f95 \| OPFLAG_8BITRM
	756	#define OP_SETCC_BE_Eb 0x0f96 \| OPFLAG_8BITRM
	757	#define OP_SETCC_NA_Eb 0x0f96 \| OPFLAG_8BITRM
	758	#define OP_SETCC_A_Eb 0x0f97 \| OPFLAG_8BITRM
	759	#define OP_SETCC_NBE_Eb 0x0f97 \| OPFLAG_8BITRM
	760	#define OP_SETCC_S_Eb 0x0f98 \| OPFLAG_8BITRM
	761	#define OP_SETCC_NS_Eb 0x0f99 \| OPFLAG_8BITRM
	762	#define OP_SETCC_P_Eb 0x0f9a \| OPFLAG_8BITRM
	763	#define OP_SETCC_PE_Eb 0x0f9a \| OPFLAG_8BITRM
	764	#define OP_SETCC_NP_Eb 0x0f9b \| OPFLAG_8BITRM
	765	#define OP_SETCC_PO_Eb 0x0f9b \| OPFLAG_8BITRM
	766	#define OP_SETCC_L_Eb 0x0f9c \| OPFLAG_8BITRM
	767	#define OP_SETCC_NGE_Eb 0x0f9c \| OPFLAG_8BITRM
	768	#define OP_SETCC_NL_Eb 0x0f9d \| OPFLAG_8BITRM
	769	#define OP_SETCC_GE_Eb 0x0f9d \| OPFLAG_8BITRM
	770	#define OP_SETCC_LE_Eb 0x0f9e \| OPFLAG_8BITRM
	771	#define OP_SETCC_NG_Eb 0x0f9e \| OPFLAG_8BITRM
	772	#define OP_SETCC_NLE_Eb 0x0f9f \| OPFLAG_8BITRM
	773	#define OP_SETCC_G_Eb 0x0f9f \| OPFLAG_8BITRM
	774
	775	#define OP_PUSH_FS 0x0fa0
	776	#define OP_POP_FS 0x0fa1
	777	#define OP_CPUID 0x0fa2
	778	#define OP_BT_Ev_Gv 0x0fa3
	779	#define OP_SHLD_Ev_Gv_Ib 0x0fa4
	780	#define OP_SHLD_Ev_Gv_CL 0x0fa5
	781	#define OP_PUSH_GS 0x0fa8
	782	#define OP_POP_GS 0x0fa9
	783	#define OP_RSM 0x0faa
	784	#define OP_BTS_Ev_Gv 0x0fab
	785	#define OP_SHRD_Ev_Gv_Ib 0x0fac
	786	#define OP_SHRD_Ev_Gv_CL 0x0fad
	787	#define OP_G16 0x0fae
	788	#define OP_IMUL_Gv_Ev 0x0faf
	789
	790	#define OP_CMPXCHG_Eb_Gb 0x0fb0 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	791	#define OP_CMPXCHG_Ev_Gv 0x0fb1
	792	#define OP_LSS_Mp 0x0fb2
	793	#define OP_BTR_Ev_Gv 0x0fb3
	794	#define OP_LFS_Mp 0x0fb4
	795	#define OP_LGS_Mp 0x0fb5
	796	#define OP_MOVZX_Gv_Eb 0x0fb6 \| OPFLAG_8BITRM
	797	#define OP_MOVZX_Gv_Ew 0x0fb7
	798	#define OP_G10_INVALID 0x0fb9
	799	#define OP_G8_Ev_Ib 0x0fba
	800	#define OP_BTC_Ev_Gv 0x0fbb
	801	#define OP_BSF_Gv_Ev 0x0fbc
	802	#define OP_BSR_Gv_Ev 0x0fbd
	803	#define OP_MOVSX_Gv_Eb 0x0fbe \| OPFLAG_8BITRM
	804	#define OP_MOVSX_Gv_Ew 0x0fbf
	805
	806	#define OP_XADD_Eb_Gb 0x0fc0 \| OPFLAG_8BITRM \| OPFLAG_8BITREG
	807	#define OP_XADD_Ev_Gv 0x0fc1
	808	#define OP_CMPPS_Vps_Wps_Ib 0x0fc2
	809	#define OP_CMPSS_Vss_Wss_Ib 0xf30fc2
	810	#define OP_CMPPD_Vpd_Wpd_Ib 0x660fc2
	811	#define OP_CMPSD_Vsd_Wsd_Ib 0xf20fc2
	812	#define OP_MOVNTI_Md_Gd 0x0fc3
	813	#define OP_PINSRW_Pw_Ew_Ib 0x0fc4
	814	#define OP_PINSRW_Vw_Ew_Ib 0x660fc4
	815	#define OP_PEXTRW_Gw_Pw_Ib 0x0fc5
	816	#define OP_PEXTRW_Gw_Vw_Ib 0x660fc5
	817	#define OP_SHUFPS_Vps_Wps_Ib 0x0fc6
	818	#define OP_SHUFPD_Vpd_Wpd_Ib 0x660fc6
	819	#define OP_G9 0x0fc7
	820	#define OP_BSWAP_EAX 0x0fc8
	821	#define OP_BSWAP_ECX 0x0fc9
	822	#define OP_BSWAP_EDX 0x0fca
	823	#define OP_BSWAP_EBX 0x0fcb
	824	#define OP_BSWAP_ESP 0x0fcc
	825	#define OP_BSWAP_EBP 0x0fcd
	826	#define OP_BSWAP_ESI 0x0fce
	827	#define OP_BSWAP_EDI 0x0fcf
	828
	829	#define OP_ADDSUBPD_Vpd_Wpd 0x0fd0
	830	#define OP_ADDSUBPS_Vps_Wps 0xf20fd0
	831	#define OP_PSRLW_Pq_Qq 0x0fd1
	832	#define OP_PSRLW_Vdq_Wdq 0x660fd1
	833	#define OP_PSRLD_Pq_Qq 0x0fd2
	834	#define OP_PSRLD_Vdq_Wdq 0x660fd2
	835	#define OP_PSRLQ_Pq_Qq 0x0fd3
	836	#define OP_PSRLQ_Vdq_Wdq 0x660fd3
	837	#define OP_PADDQ_Pq_Qq 0x0fd4
	838	#define OP_PADDQ_Vdq_Wdq 0x660fd4
	839	#define OP_PMULLW_Pq_Qq 0x0fd5
	840	#define OP_PMULLW_Vdq_Wdq 0x660fd5
	841	#define OP_MOVQ_Wq_Vq 0x0fd6
	842	#define OP_MOVQ2DQ_Vdq_Qq 0xf30fd6
	843	#define OP_MOVDQ2Q_Pq_Vq 0xf20fd6
	844	#define OP_PMOVMSKB_Gd_Pq 0x0fd7
	845	#define OP_PMOVMSKB_Gd_Vdq 0x660fd7
	846	#define OP_PSUBUSB_Pq_Qq 0x0fd8
	847	#define OP_PSUBUSB_Vdq_Wdq 0x660fd8
	848	#define OP_PSUBUSW_Pq_Qq 0x0fd9
	849	#define OP_PSUBUSW_Vdq_Wdq 0x660fd9
	850	#define OP_PMINUB_Pq_Qq 0x0fda
	851	#define OP_PMINUB_Vdq_Wdq 0x660fda
	852	#define OP_PAND_Pq_Qq 0x0fdb
	853	#define OP_PAND_Vdq_Wdq 0x660fdb
	854	#define OP_PADDUSB_Pq_Qq 0x0fdc
	855	#define OP_PADDUSB_Vdq_Wdq 0x660fdc
	856	#define OP_PADDUSW_Pq_Qq 0x0fdd
	857	#define OP_PADDUSW_Vdq_Wdq 0x660fdd
	858	#define OP_PMAXUB_Pq_Qq 0x0fde
	859	#define OP_PMAXUB_Vdq_Wdq 0x660fde
	860	#define OP_PANDN_Pq_Qq 0x0fdf
	861	#define OP_PANDN_Vdq_Wdq 0x660fdf
	862
	863	#define OP_PAVGB_Pq_Qq 0x0fe0
	864	#define OP_PAVGB_Vdq_Wdq 0x660fe0
	865	#define OP_PSRAW_Pq_Qq 0x0fe1
	866	#define OP_PSRAW_Vdq_Wdq 0x660fe1
	867	#define OP_PSRAD_Pq_Qq 0x0fe2
	868	#define OP_PSRAD_Vdq_Wdq 0x660fe2
	869	#define OP_PAVGW_Pq_Qq 0x0fe3
	870	#define OP_PAVGW_Vdq_Wdq 0x660fe3
	871	#define OP_PMULHUW_Pq_Qq 0x0fe4
	872	#define OP_PMULHUW_Vdq_Wdq 0x660fe4
	873	#define OP_PMULHW_Pq_Qq 0x0fe5
	874	#define OP_PMULHW_Vdq_Wdq 0x660fe5
	875	#define OP_CVTPD2DQ_Vdq_Wpd 0xf20fe6
	876	#define OP_CVTTPD2DQ_Vdq_Wpd 0x660fe6
	877	#define OP_CVTDQ2PD_Vpd_Wq 0xf30fe6
	878	#define OP_MOVNTQ_Mq_Vq 0x0fe7
	879	#define OP_MOVNTDQ_Mdq_Vdq 0x660fe7
	880	#define OP_PSUBSB_Pq_Qq 0x0fe8
	881	#define OP_PSUBSB_Vdq_Wdq 0x660fe8
	882	#define OP_PSUBSW_Pq_Qq 0x0fe9
	883	#define OP_PSUBSW_Vdq_Wdq 0x660fe9
	884	#define OP_PMINSW_Pq_Qq 0x0fea
	885	#define OP_PMINSW_Vdq_Wdq 0x660fea
	886	#define OP_POR_Pq_Qq 0x0feb
	887	#define OP_POR_Vdq_Wdq 0x660feb
	888	#define OP_PADDSB_Pq_Qq 0x0fec
	889	#define OP_PADDSB_Vdq_Wdq 0x660fec
	890	#define OP_PADDSW_Pq_Qq 0x0fed
	891	#define OP_PADDSW_Vdq_Wdq 0x660fed
	892	#define OP_PMAXSW_Pq_Qq 0x0fee
	893	#define OP_PMAXSW_Vdq_Wdq 0x660fee
	894	#define OP_PXOR_Pq_Qq 0x0fef
	895	#define OP_PXOR_Vdq_Wdq 0x660fef
	896
	897	#define OP_LDDQU_Vdq_Mdq 0xf20ff0
	898	#define OP_PSLLW_Pq_Qq 0x0ff1
	899	#define OP_PSLLW_Vdq_Wdq 0x660ff1
	900	#define OP_PSLLD_Pq_Qq 0x0ff2
	901	#define OP_PSLLD_Vdq_Wdq 0x660ff2
	902	#define OP_PSLLQ_Pq_Qq 0x0ff3
	903	#define OP_PSLLQ_Vdq_Wdq 0x660ff3
	904	#define OP_PMULUDQ_Pq_Qq 0x0ff4
	905	#define OP_PMULUDQ_Vdq_Wdq 0x660ff4
	906	#define OP_PMADDWD_Pq_Qq 0x0ff5
	907	#define OP_PMADDWD_Vdq_Wdq 0x660ff5
	908	#define OP_PSADBW_Pq_Qq 0x0ff6
	909	#define OP_PSADBW_Vdq_Wdq 0x660ff6
	910	#define OP_MASKMOVQ_Pq_Qq 0x0ff7
	911	#define OP_MASKMOVDQU_Vdq_Wdq 0x660ff7
	912	#define OP_PSUBB_Pq_Qq 0x0ff8
	913	#define OP_PSUBB_Vdq_Wdq 0x660ff8
	914	#define OP_PSUBW_Pq_Qq 0x0ff9
	915	#define OP_PSUBW_Vdq_Wdq 0x660ff9
	916	#define OP_PSUBD_Pq_Qq 0x0ffa
	917	#define OP_PSUBD_Vdq_Wdq 0x660ffa
	918	#define OP_PSUBQ_Pq_Qq 0x0ffb
	919	#define OP_PSUBQ_Vdq_Wdq 0x660ffb
	920	#define OP_PADDB_Pq_Qq 0x0ffc
	921	#define OP_PADDB_Vdq_Wdq 0x660ffc
	922	#define OP_PADDW_Pq_Qq 0x0ffd
	923	#define OP_PADDW_Vdq_Wdq 0x660ffd
	924	#define OP_PADDD_Pq_Qq 0x0ffe
	925	#define OP_PADDD_Vdq_Wdq 0x660ffe
	926
	927
	928
	929	/***************************************************************************
	930	TYPE DEFINITIONS
	931	***************************************************************************/
	932
	933	typedef UINT8 x86code;
	934
	935
	936	typedef struct _emit_link emit_link;
	937	struct _emit_link
	938	{
	939	x86code * target;
	940	UINT8 size;
	941	};
	942
	943
	944
	945	/***************************************************************************
	946	CORE FUNCTIONS
	947	***************************************************************************/
	948
	949	/*-------------------------------------------------
	950	make_modrm - assemble a modrm byte from the
	951	three components
	952	-------------------------------------------------*/
	953
	954	INLINE UINT8 make_modrm(UINT8 mode, UINT8 reg, UINT8 rm)
	955	{
	956	assert(mode < 4);
	957	assert(reg < REG_MAX);
	958	assert(rm < REG_MAX);
	959	return (mode << 6) \| ((reg & 7) << 3) \| (rm & 7);
	960	}
	961
	962
	963	/*-------------------------------------------------
	964	make_sib - assemble an sib byte from the
	965	three components
	966	-------------------------------------------------*/
	967
	968	INLINE UINT8 make_sib(UINT8 scale, UINT8 index, UINT8 base)
	969	{
	970	static const UINT8 scale_lookup[9] = { 0<<6, 0<<6, 1<<6, 0<<6, 2<<6, 0<<6, 0<<6, 0<<6, 3<<6 };
	971	assert(scale == 1 \|\| scale == 2 \|\| scale == 4 \|\| scale == 8);
	972	assert(index < REG_MAX);
	973	assert(base < REG_MAX);
	974	return scale_lookup[scale] \| ((index & 7) << 3) \| (base & 7);
	975	}
	976
	977
	978	/*-------------------------------------------------
	979	emit_byte - emit a byte
	980	-------------------------------------------------*/
	981
	982	INLINE void emit_byte(x86code **emitptr, UINT8 byte)
	983	{
	984	((UINT8 )*emitptr) = byte;
	985	*emitptr += 1;
	986	}
	987
	988
	989	/*-------------------------------------------------
	990	emit_word - emit a word
	991	-------------------------------------------------*/
	992
	993	INLINE void emit_word(x86code **emitptr, UINT16 word)
	994	{
	995	((UINT16 )*emitptr) = word;
	996	*emitptr += 2;
	997	}
	998
	999
	1000	/*-------------------------------------------------
	1001	emit_dword - emit a dword
	1002	-------------------------------------------------*/
	1003
	1004	INLINE void emit_dword(x86code **emitptr, UINT32 dword)
	1005	{
	1006	((UINT32 )*emitptr) = dword;
	1007	*emitptr += 4;
	1008	}
	1009
	1010
	1011	/*-------------------------------------------------
	1012	emit_qword - emit a dword
	1013	-------------------------------------------------*/
	1014
	1015	INLINE void emit_qword(x86code **emitptr, UINT64 qword)
	1016	{
	1017	((UINT64 )*emitptr) = qword;
	1018	*emitptr += 8;
	1019	}
	1020
	1021
	1022
	1023	/***************************************************************************
	1024	GENERIC OPCODE EMITTERS
	1025	***************************************************************************/
	1026
	1027	/*-------------------------------------------------
	1028	emit_op - emit a 1, 2, or 3-byte opcode,
	1029	along with any necessary REX prefixes for x64
	1030	-------------------------------------------------*/
	1031
	1032	INLINE void emit_op(x86code **emitptr, UINT32 op, UINT8 op64, UINT8 reg, UINT8 sib, UINT8 rm)
	1033	{
	1034	#ifdef PTR64
	1035	UINT8 rex;
	1036
	1037	assert(op64 == OP_32BIT \|\| op64 == OP_64BIT);
	1038
	1039	rex = op64 \| ((reg & 8) >> 1) \| ((sib & 8) >> 2) \| ((rm & 8) >> 3);
	1040	if (rex != 0 \|\| ((op & OPFLAG_8BITREG) && reg >= 4) \|\| ((op & OPFLAG_8BITRM) && rm >= 4))
	1041	emit_byte(emitptr, rex \| 0x40);
	1042	#else
	1043	assert(op64 == OP_32BIT);
	1044	#endif
	1045
	1046	if ((op & 0xff0000) != 0)
	1047	emit_byte(emitptr, op >> 16);
	1048	if ((op & 0xff00) != 0)
	1049	emit_byte(emitptr, op >> 8);
	1050	emit_byte(emitptr, op);
	1051	}
	1052
	1053
	1054	/*-------------------------------------------------
	1055	emit_op_simple - emit a simple opcode
	1056	-------------------------------------------------*/
	1057
	1058	INLINE void emit_op_simple(x86code **emitptr, UINT32 op, UINT8 op64)
	1059	{
	1060	emit_op(emitptr, op, op64, 0, 0, 0);
	1061	}
	1062
	1063
	1064	/*-------------------------------------------------
	1065	emit_op_modrm_reg - emit an opcode with a
	1066	register modrm byte
	1067	-------------------------------------------------*/
	1068
	1069	INLINE void emit_op_modrm_reg(x86code **emitptr, UINT32 op, UINT8 op64, UINT8 reg, UINT8 rm)
	1070	{
	1071	assert(reg < REG_MAX);
	1072	assert(rm < REG_MAX);
	1073
	1074	emit_op(emitptr, op, op64, reg, 0, rm);
	1075	emit_byte(emitptr, make_modrm(3, reg, rm));
	1076	}
	1077
	1078
	1079	/*-------------------------------------------------
	1080	emit_op_modrm_mem - emit an opcode with a
	1081	memory modrm byte
	1082	-------------------------------------------------*/
	1083
	1084	INLINE void emit_op_modrm_mem(x86code **emitptr, UINT32 op, UINT8 op64, UINT8 reg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1085	{
	1086	assert(reg < REG_MAX);
	1087	assert(base < REG_MAX \|\| base == REG_NONE);
	1088	assert(index < REG_MAX \|\| index == REG_NONE);
	1089
	1090	/* turn off the OPFLAG_8BITRM flag since it only applies to register operands */
	1091	op &= ~OPFLAG_8BITRM;
	1092
	1093	/* displacement only case */
	1094	if (base == REG_NONE && index == REG_NONE)
	1095	{
	1096	#ifndef PTR64
	1097	emit_op(emitptr, op, op64, reg, 0, rm);
	1098	emit_byte(emitptr, make_modrm(0, reg, 5));
	1099	emit_dword(emitptr, disp);
	1100	#else
	1101	fatalerror("Invalid absolute mode in 64-bits!\n");
	1102	#endif
	1103	}
	1104
	1105	/* base only case */
	1106	else if (index == REG_NONE && base != REG_ESP)
	1107	{
	1108	emit_op(emitptr, op, op64, reg, 0, base);
	1109
	1110	/* mode 0 for no offset */
	1111	if (disp == 0 && base != REG_EBP)
	1112	emit_byte(emitptr, make_modrm(0, reg, base));
	1113
	1114	/* mode 1 for 1-byte offset */
	1115	else if ((INT8)disp == disp)
	1116	{
	1117	emit_byte(emitptr, make_modrm(1, reg, base));
	1118	emit_byte(emitptr, (INT8)disp);
	1119	}
	1120
	1121	/* mode 2 for 4-byte offset */
	1122	else
	1123	{
	1124	emit_byte(emitptr, make_modrm(2, reg, base));
	1125	emit_dword(emitptr, disp);
	1126	}
	1127	}
	1128
	1129	/* full BISD case */
	1130	else
	1131	{
	1132	assert(index != REG_ESP);
	1133	emit_op(emitptr, op, op64, reg, index, base);
	1134
	1135	/* a "none" index == REG_ESP */
	1136	if (index == REG_NONE)
	1137	index = REG_ESP;
	1138
	1139	/* mode 0 for no offset */
	1140	if (disp == 0 && base != REG_EBP)
	1141	{
	1142	emit_byte(emitptr, make_modrm(0, reg, 4));
	1143	emit_byte(emitptr, make_sib(scale, index, (base == REG_NONE) ? REG_EBP : base));
	1144	if (base == REG_NONE)
	1145	emit_dword(emitptr, disp);
	1146	}
	1147
	1148	/* mode 1 for 1-byte offset */
	1149	else if ((INT8)disp == disp)
	1150	{
	1151	emit_byte(emitptr, make_modrm(1, reg, 4));
	1152	emit_byte(emitptr, make_sib(scale, index, base));
	1153	emit_byte(emitptr, (INT8)disp);
	1154	}
	1155
	1156	/* mode 2 for 4-byte offset */
	1157	else
	1158	{
	1159	emit_byte(emitptr, make_modrm(2, reg, 4));
	1160	emit_byte(emitptr, make_sib(scale, index, base));
	1161	emit_dword(emitptr, disp);
	1162	}
	1163	}
	1164	}
	1165
	1166
	1167
	1168	/***************************************************************************
	1169	SIMPLE OPCODE EMITTERS
	1170	***************************************************************************/
	1171
	1172	INLINE void emit_nop(x86code **emitptr)
	1173	{
	1174	emit_byte(emitptr, OP_NOP);
	1175	}
	1176
	1177	INLINE void emit_int_3(x86code **emitptr)
	1178	{
	1179	emit_byte(emitptr, OP_INT_3);
	1180	}
	1181
	1182	INLINE void emit_ret(x86code **emitptr)
	1183	{
	1184	emit_byte(emitptr, OP_RETN);
	1185	}
	1186
	1187	INLINE void emit_cdq(x86code **emitptr)
	1188	{
	1189	emit_byte(emitptr, OP_CDQ);
	1190	}
	1191
	1192	#ifdef PTR64
	1193	INLINE void emit_cqo(x86code **emitptr)
	1194	{
	1195	emit_byte(emitptr, OP_REX_W);
	1196	emit_byte(emitptr, OP_CQO);
	1197	}
	1198	#endif
	1199
	1200
	1201
	1202	/***************************************************************************
	1203	CALL/JUMP EMITTERS
	1204	***************************************************************************/
	1205
	1206	/*-------------------------------------------------
	1207	resolve_link - resolve a link in a jump
	1208	instruction
	1209	-------------------------------------------------*/
	1210
	1211	INLINE void resolve_link(x86code *destptr, const emit_link linkinfo)
	1212	{
	1213	INT64 delta = *destptr - linkinfo->target;
	1214	if (linkinfo->size == 1)
	1215	{
	1216	assert((INT8)delta == delta);
	1217	((INT8 *)linkinfo->target)[-1] = (INT8)delta;
	1218	}
	1219	else if (linkinfo->size == 2)
	1220	{
	1221	assert((INT16)delta == delta);
	1222	((INT16 *)linkinfo->target)[-1] = (INT16)delta;
	1223	}
	1224	else
	1225	{
	1226	assert((INT32)delta == delta);
	1227	((INT32 *)linkinfo->target)[-1] = (INT32)delta;
	1228	}
	1229	}
	1230
	1231
	1232	/*------------------------------------------------------------------
	1233	emit_call_*
	1234	------------------------------------------------------------------*/
	1235
	1236	INLINE void emit_call_link(x86code *emitptr, emit_link linkinfo)
	1237	{
	1238	emit_op_simple(emitptr, OP_CALL_Jz, OP_32BIT);
	1239	emit_dword(emitptr, 0);
	1240	linkinfo->target = *emitptr;
	1241	linkinfo->size = 4;
	1242	}
	1243
	1244	INLINE void emit_call(x86code *emitptr, x86code target)
	1245	{
	1246	emit_link link;
	1247
	1248	emit_call_link(emitptr, &link);
	1249	resolve_link(&target, &link);
	1250	}
	1251
	1252
	1253	/*------------------------------------------------------------------
	1254	emit_call_r32_*
	1255	------------------------------------------------------------------*/
	1256
	1257	#ifndef PTR64
	1258
	1259	INLINE void emit_call_r32(x86code **emitptr, UINT8 dreg)
	1260	{
	1261	emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 2, dreg);
	1262	}
	1263
	1264	INLINE void emit_call_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1265	{
	1266	emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 2, base, index, scale, disp);
	1267	}
	1268
	1269	#define emit_call_m32abs(e, addr) emit_call_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1270	#define emit_call_m32bd(e, base, disp) emit_call_m32bisd(e, (base), REG_NONE, 1, (disp))
	1271	#define emit_call_m32isd(e, index, scale, disp) emit_call_m32bisd(e, REG_NONE, (index), (scale), (disp))
	1272
	1273	#endif
	1274
	1275
	1276	/*------------------------------------------------------------------
	1277	emit_call_r64_*
	1278	------------------------------------------------------------------*/
	1279
	1280	#ifdef PTR64
	1281
	1282	INLINE void emit_call_r64(x86code **emitptr, UINT8 dreg)
	1283	{
	1284	emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 2, dreg);
	1285	}
	1286
	1287	INLINE void emit_call_m64bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1288	{
	1289	emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 2, base, index, scale, disp);
	1290	}
	1291
	1292	#define emit_call_m64abs(e, addr) emit_call_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1293	#define emit_call_m64bd(e, base, disp) emit_call_m64bisd(e, (base), REG_NONE, 1, (disp))
	1294	#define emit_call_m64isd(e, index, scale, disp) emit_call_m64bisd(e, REG_NONE, (index), (scale), (disp))
	1295
	1296	#endif
	1297
	1298
	1299	/*------------------------------------------------------------------
	1300	emit_jmp_*
	1301	------------------------------------------------------------------*/
	1302
	1303	INLINE void emit_jmp_short_link(x86code *emitptr, emit_link linkinfo)
	1304	{
	1305	emit_op_simple(emitptr, OP_JMP_Jb, OP_32BIT);
	1306	emit_byte(emitptr, 0);
	1307	linkinfo->target = *emitptr;
	1308	linkinfo->size = 1;
	1309	}
	1310
	1311	INLINE void emit_jmp_near_link(x86code *emitptr, emit_link linkinfo)
	1312	{
	1313	emit_op_simple(emitptr, OP_JMP_Jz, OP_32BIT);
	1314	emit_dword(emitptr, 0);
	1315	linkinfo->target = *emitptr;
	1316	linkinfo->size = 4;
	1317	}
	1318
	1319	INLINE void emit_jmp(x86code *emitptr, x86code target)
	1320	{
	1321	INT32 delta = target - (*emitptr + 2);
	1322	emit_link link;
	1323
	1324	if ((INT8)delta == delta)
	1325	emit_jmp_short_link(emitptr, &link);
	1326	else
	1327	emit_jmp_near_link(emitptr, &link);
	1328	resolve_link(&target, &link);
	1329	}
	1330
	1331
	1332	/*------------------------------------------------------------------
	1333	emit_jcc_*
	1334	------------------------------------------------------------------*/
	1335
	1336	INLINE void emit_jcc_short_link(x86code *emitptr, UINT8 condition, emit_link linkinfo)
	1337	{
	1338	emit_op_simple(emitptr, OP_JCC_O_Jb + condition, OP_32BIT);
	1339	emit_byte(emitptr, 0);
	1340	linkinfo->target = *emitptr;
	1341	linkinfo->size = 1;
	1342	}
	1343
	1344	INLINE void emit_jcc_near_link(x86code *emitptr, UINT8 condition, emit_link linkinfo)
	1345	{
	1346	emit_op_simple(emitptr, OP_JCC_O_Jv + condition, OP_32BIT);
	1347	emit_dword(emitptr, 0);
	1348	linkinfo->target = *emitptr;
	1349	linkinfo->size = 4;
	1350	}
	1351
	1352	INLINE void emit_jcc(x86code *emitptr, UINT8 condition, x86code target)
	1353	{
	1354	INT32 delta = *emitptr + 2 - target;
	1355	emit_link link;
	1356
	1357	if ((INT8)delta == delta)
	1358	emit_jcc_short_link(emitptr, condition, &link);
	1359	else
	1360	emit_jcc_near_link(emitptr, condition, &link);
	1361	resolve_link(&target, &link);
	1362	}
	1363
	1364
	1365	/*------------------------------------------------------------------
	1366	emit_jmp_r32_*
	1367	------------------------------------------------------------------*/
	1368
	1369	#ifndef PTR64
	1370
	1371	INLINE void emit_jmp_r32(x86code **emitptr, UINT8 dreg)
	1372	{
	1373	emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 4, dreg);
	1374	}
	1375
	1376	INLINE void emit_jmp_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1377	{
	1378	emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 4, base, index, scale, disp);
	1379	}
	1380
	1381	#define emit_jmp_m32abs(e, addr) emit_jmp_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1382	#define emit_jmp_m32bd(e, base, disp) emit_jmp_m32bisd(e, (base), REG_NONE, 1, (disp))
	1383	#define emit_jmp_m32isd(e, index, scale, disp) emit_jmp_m32bisd(e, REG_NONE, (index), (scale), (disp))
	1384
	1385	#endif
	1386
	1387
	1388	/*------------------------------------------------------------------
	1389	emit_jmp_r64_*
	1390	------------------------------------------------------------------*/
	1391
	1392	#ifdef PTR64
	1393
	1394	INLINE void emit_jmp_r64(x86code **emitptr, UINT8 dreg)
	1395	{
	1396	emit_op_modrm_reg(emitptr, OP_G5, OP_32BIT, 4, dreg);
	1397	}
	1398
	1399	INLINE void emit_jmp_m64bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1400	{
	1401	emit_op_modrm_mem(emitptr, OP_G5, OP_32BIT, 4, base, index, scale, disp);
	1402	}
	1403
	1404	#define emit_jmp_m64abs(e, addr) emit_jmp_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1405	#define emit_jmp_m64bd(e, base, disp) emit_jmp_m64bisd(e, (base), REG_NONE, 1, (disp))
	1406	#define emit_jmp_m64isd(e, index, scale, disp) emit_jmp_m64bisd(e, REG_NONE, (index), (scale), (disp))
	1407
	1408	#endif
	1409
	1410
	1411
	1412	/***************************************************************************
	1413	MOVE EMITTERS
	1414	***************************************************************************/
	1415
	1416	/*------------------------------------------------------------------
	1417	emit_mov_r8_*
	1418	------------------------------------------------------------------*/
	1419
	1420	INLINE void emit_mov_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm)
	1421	{
	1422	emit_op(emitptr, OP_MOV_AL_Ib \| (dreg & 7), OP_32BIT, 0, 0, dreg);
	1423	emit_byte(emitptr, imm);
	1424	}
	1425
	1426	INLINE void emit_mov_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1427	{
	1428	emit_op_modrm_reg(emitptr, OP_MOV_Gb_Eb, OP_32BIT, dreg, sreg);
	1429	}
	1430
	1431	INLINE void emit_mov_r8_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1432	{
	1433	emit_op_modrm_mem(emitptr, OP_MOV_Gb_Eb, OP_32BIT, dreg, base, index, scale, disp);
	1434	}
	1435
	1436	INLINE void emit_mov_m8bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
	1437	{
	1438	emit_op_modrm_mem(emitptr, OP_G11_Eb_Ib, OP_32BIT, 0, base, index, scale, disp);
	1439	emit_byte(emitptr, imm);
	1440	}
	1441
	1442	INLINE void emit_mov_m8bisd_r8(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	1443	{
	1444	emit_op_modrm_mem(emitptr, OP_MOV_Eb_Gb, OP_32BIT, sreg, base, index, scale, disp);
	1445	}
	1446
	1447	#define emit_mov_r8_m8abs(e, dreg, addr) emit_mov_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1448	#define emit_mov_r8_m8bd(e, dreg, base, disp) emit_mov_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1449	#define emit_mov_r8_m8isd(e, dreg, index, scale, disp) emit_mov_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1450
	1451	#define emit_mov_m8abs_r8(e, addr, sreg) emit_mov_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	1452	#define emit_mov_m8bd_r8(e, base, disp, sreg) emit_mov_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
	1453	#define emit_mov_m8isd_r8(e, index, scale, disp, sreg) emit_mov_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
	1454
	1455	#define emit_mov_m8abs_imm(e, addr, imm) emit_mov_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	1456	#define emit_mov_m8bd_imm(e, base, disp, imm) emit_mov_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	1457	#define emit_mov_m8isd_imm(e, index, scale, disp, imm) emit_mov_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	1458
	1459
	1460	/*------------------------------------------------------------------
	1461	emit_mov_r16_*
	1462	------------------------------------------------------------------*/
	1463
	1464	INLINE void emit_mov_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm)
	1465	{
	1466	emit_byte(emitptr, PREFIX_OPSIZE);
	1467	emit_op(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_32BIT, 0, 0, dreg);
	1468	emit_word(emitptr, imm);
	1469	}
	1470
	1471	INLINE void emit_mov_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1472	{
	1473	emit_byte(emitptr, PREFIX_OPSIZE);
	1474	emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, sreg);
	1475	}
	1476
	1477	INLINE void emit_mov_r16_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1478	{
	1479	emit_byte(emitptr, PREFIX_OPSIZE);
	1480	emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, base, index, scale, disp);
	1481	}
	1482
	1483	INLINE void emit_mov_m16bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT16 imm)
	1484	{
	1485	emit_byte(emitptr, PREFIX_OPSIZE);
	1486	emit_op_modrm_mem(emitptr, OP_G11_Ev_Iz, OP_32BIT, 0, base, index, scale, disp);
	1487	emit_word(emitptr, imm);
	1488	}
	1489
	1490	INLINE void emit_mov_m16bisd_r16(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	1491	{
	1492	emit_byte(emitptr, PREFIX_OPSIZE);
	1493	emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
	1494	}
	1495
	1496	INLINE void emit_cmovcc_r16_r16(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 sreg)
	1497	{
	1498	emit_byte(emitptr, PREFIX_OPSIZE);
	1499	emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, sreg);
	1500	}
	1501
	1502	INLINE void emit_cmovcc_r16_m16bisd(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1503	{
	1504	emit_byte(emitptr, PREFIX_OPSIZE);
	1505	emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, base, index, scale, disp);
	1506	}
	1507
	1508	#define emit_mov_r16_m16abs(e, dreg, addr) emit_mov_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1509	#define emit_mov_r16_m16bd(e, dreg, base, disp) emit_mov_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1510	#define emit_mov_r16_m16isd(e, dreg, index, scale, disp) emit_mov_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1511
	1512	#define emit_mov_m16abs_r16(e, addr, sreg) emit_mov_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	1513	#define emit_mov_m16bd_r16(e, base, disp, sreg) emit_mov_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
	1514	#define emit_mov_m16isd_r16(e, index, scale, disp, sreg) emit_mov_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
	1515
	1516	#define emit_mov_m16abs_imm(e, addr, imm) emit_mov_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	1517	#define emit_mov_m16bd_imm(e, base, disp, imm) emit_mov_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	1518	#define emit_mov_m16isd_imm(e, index, scale, disp, imm) emit_mov_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	1519
	1520	#define emit_cmovcc_r16_m16abs(e, cond, dreg, addr) emit_cmovcc_r16_m16bisd(e, cond, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1521	#define emit_cmovcc_r16_m16bd(e, cond, dreg, base, disp) emit_cmovcc_r16_m16bisd(e, cond, dreg, (base), REG_NONE, 1, (disp))
	1522	#define emit_cmovcc_r16_m16isd(e, cond, dreg, index, scale, disp) emit_cmovcc_r16_m16bisd(e, cond, dreg, REG_NONE, (index), (scale), (disp))
	1523
	1524
	1525	/*------------------------------------------------------------------
	1526	emit_mov_r32_*
	1527	------------------------------------------------------------------*/
	1528
	1529	INLINE void emit_mov_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm)
	1530	{
	1531	emit_op(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_32BIT, 0, 0, dreg);
	1532	emit_dword(emitptr, imm);
	1533	}
	1534
	1535	INLINE void emit_mov_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1536	{
	1537	emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, sreg);
	1538	}
	1539
	1540	INLINE void emit_mov_r32_m32bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1541	{
	1542	emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_32BIT, dreg, base, index, scale, disp);
	1543	}
	1544
	1545	INLINE void emit_mov_m32bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
	1546	{
	1547	emit_op_modrm_mem(emitptr, OP_G11_Ev_Iz, OP_32BIT, 0, base, index, scale, disp);
	1548	emit_dword(emitptr, imm);
	1549	}
	1550
	1551	INLINE void emit_mov_m32bisd_r32(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	1552	{
	1553	emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
	1554	}
	1555
	1556	INLINE void emit_cmovcc_r32_r32(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 sreg)
	1557	{
	1558	emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, sreg);
	1559	}
	1560
	1561	INLINE void emit_cmovcc_r32_m32bisd(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1562	{
	1563	emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_32BIT, dreg, base, index, scale, disp);
	1564	}
	1565
	1566	#define emit_mov_r32_m32abs(e, dreg, addr) emit_mov_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1567	#define emit_mov_r32_m32bd(e, dreg, base, disp) emit_mov_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1568	#define emit_mov_r32_m32isd(e, dreg, index, scale, disp) emit_mov_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1569
	1570	#define emit_mov_m32abs_r32(e, addr, sreg) emit_mov_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	1571	#define emit_mov_m32bd_r32(e, base, disp, sreg) emit_mov_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
	1572	#define emit_mov_m32isd_r32(e, index, scale, disp, sreg) emit_mov_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	1573
	1574	#define emit_mov_m32abs_imm(e, addr, imm) emit_mov_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	1575	#define emit_mov_m32bd_imm(e, base, disp, imm) emit_mov_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	1576	#define emit_mov_m32isd_imm(e, index, scale, disp, imm) emit_mov_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	1577
	1578	#define emit_cmovcc_r32_m32abs(e, cond, dreg, addr) emit_cmovcc_r32_m32bisd(e, cond, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1579	#define emit_cmovcc_r32_m32bd(e, cond, dreg, base, disp) emit_cmovcc_r32_m32bisd(e, cond, dreg, (base), REG_NONE, 1, (disp))
	1580	#define emit_cmovcc_r32_m32isd(e, cond, dreg, index, scale, disp) emit_cmovcc_r32_m32bisd(e, cond, dreg, REG_NONE, (index), (scale), (disp))
	1581
	1582
	1583	/*------------------------------------------------------------------
	1584	emit_mov_r64_*
	1585	------------------------------------------------------------------*/
	1586
	1587	#ifdef PTR64
	1588
	1589	INLINE void emit_mov_r64_imm(x86code **emitptr, UINT8 dreg, UINT64 imm)
	1590	{
	1591	emit_op(emitptr, OP_MOV_rAX_Iv \| (dreg & 7), OP_64BIT, 0, 0, dreg);
	1592	emit_qword(emitptr, imm);
	1593	}
	1594
	1595	INLINE void emit_mov_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1596	{
	1597	emit_op_modrm_reg(emitptr, OP_MOV_Gv_Ev, OP_64BIT, dreg, sreg);
	1598	}
	1599
	1600	INLINE void emit_mov_r64_m64bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1601	{
	1602	emit_op_modrm_mem(emitptr, OP_MOV_Gv_Ev, OP_64BIT, dreg, base, index, scale, disp);
	1603	}
	1604
	1605	INLINE void emit_mov_m64bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT64 imm)
	1606	{
	1607	assert((INT32)imm == (INT64)imm);
	1608	emit_op_modrm_mem(emitptr, OP_G11_Ev_Iz, OP_64BIT, 0, base, index, scale, disp);
	1609	emit_dword(emitptr, (INT32)imm);
	1610	}
	1611
	1612	INLINE void emit_mov_m64bisd_r64(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	1613	{
	1614	emit_op_modrm_mem(emitptr, OP_MOV_Ev_Gv, OP_64BIT, sreg, base, index, scale, disp);
	1615	}
	1616
	1617	INLINE void emit_cmovcc_r64_r64(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 sreg)
	1618	{
	1619	emit_op_modrm_reg(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_64BIT, dreg, sreg);
	1620	}
	1621
	1622	INLINE void emit_cmovcc_r64_m64bisd(x86code **emitptr, UINT8 condition, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1623	{
	1624	emit_op_modrm_mem(emitptr, OP_CMOV_O_Gv_Ev + condition, OP_64BIT, dreg, base, index, scale, disp);
	1625	}
	1626
	1627	#define emit_mov_r64_m64abs(e, dreg, addr) emit_mov_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1628	#define emit_mov_r64_m64bd(e, dreg, base, disp) emit_mov_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1629	#define emit_mov_r64_m64isd(e, dreg, index, scale, disp) emit_mov_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1630
	1631	#define emit_mov_m64abs_r64(e, addr, sreg) emit_mov_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	1632	#define emit_mov_m64bd_r64(e, base, disp, sreg) emit_mov_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
	1633	#define emit_mov_m64isd_r64(e, index, scale, disp, sreg) emit_mov_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
	1634
	1635	#define emit_mov_m64abs_imm(e, addr, imm) emit_mov_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	1636	#define emit_mov_m64bd_imm(e, base, disp, imm) emit_mov_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	1637	#define emit_mov_m64isd_imm(e, index, scale, disp, imm) emit_mov_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	1638
	1639	#define emit_cmovcc_r64_m64abs(e, cond, dreg, addr) emit_cmovcc_r64_m64bisd(e, cond, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1640	#define emit_cmovcc_r64_m64bd(e, cond, dreg, base, disp) emit_cmovcc_r64_m64bisd(e, cond, dreg, (base), REG_NONE, 1, (disp))
	1641	#define emit_cmovcc_r64_m64isd(e, cond, dreg, index, scale, disp) emit_cmovcc_r64_m64bisd(e, cond, dreg, REG_NONE, (index), (scale), (disp))
	1642
	1643	#endif
	1644
	1645
	1646
	1647	/***************************************************************************
	1648	MOVE EXTENDED EMITTERS
	1649	***************************************************************************/
	1650
	1651	/*------------------------------------------------------------------
	1652	emit_movsx_r16_*
	1653	------------------------------------------------------------------*/
	1654
	1655	INLINE void emit_movsx_r16_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1656	{
	1657	emit_byte(emitptr, PREFIX_OPSIZE);
	1658	emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, sreg);
	1659	}
	1660
	1661	INLINE void emit_movsx_r16_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1662	{
	1663	emit_byte(emitptr, PREFIX_OPSIZE);
	1664	emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
	1665	}
	1666
	1667	#define emit_movsx_r16_m8abs(e, dreg, addr) emit_movsx_r16_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1668	#define emit_movsx_r16_m8bd(e, dreg, base, disp) emit_movsx_r16_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1669	#define emit_movsx_r16_m8isd(e, dreg, index, scale, disp) emit_movsx_r16_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1670
	1671
	1672	/*------------------------------------------------------------------
	1673	emit_movzx_r16_*
	1674	------------------------------------------------------------------*/
	1675
	1676	INLINE void emit_movzx_r16_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1677	{
	1678	emit_byte(emitptr, PREFIX_OPSIZE);
	1679	emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, sreg);
	1680	}
	1681
	1682	INLINE void emit_movzx_r16_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1683	{
	1684	emit_byte(emitptr, PREFIX_OPSIZE);
	1685	emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
	1686	}
	1687
	1688	#define emit_movzx_r16_m8abs(e, dreg, addr) emit_movzx_r16_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1689	#define emit_movzx_r16_m8bd(e, dreg, base, disp) emit_movzx_r16_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1690	#define emit_movzx_r16_m8isd(e, dreg, index, scale, disp) emit_movzx_r16_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1691
	1692
	1693	/*------------------------------------------------------------------
	1694	emit_movsx_r32_*
	1695	------------------------------------------------------------------*/
	1696
	1697	INLINE void emit_movsx_r32_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1698	{
	1699	emit_byte(emitptr, PREFIX_OPSIZE);
	1700	emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, sreg);
	1701	}
	1702
	1703	INLINE void emit_movsx_r32_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1704	{
	1705	emit_byte(emitptr, PREFIX_OPSIZE);
	1706	emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
	1707	}
	1708
	1709	INLINE void emit_movsx_r32_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1710	{
	1711	emit_byte(emitptr, PREFIX_OPSIZE);
	1712	emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Ew, OP_32BIT, dreg, sreg);
	1713	}
	1714
	1715	INLINE void emit_movsx_r32_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1716	{
	1717	emit_byte(emitptr, PREFIX_OPSIZE);
	1718	emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Ew, OP_32BIT, dreg, base, index, scale, disp);
	1719	}
	1720
	1721	#define emit_movsx_r32_m8abs(e, dreg, addr) emit_movsx_r32_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1722	#define emit_movsx_r32_m8bd(e, dreg, base, disp) emit_movsx_r32_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1723	#define emit_movsx_r32_m8isd(e, dreg, index, scale, disp) emit_movsx_r32_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1724
	1725	#define emit_movsx_r32_m16abs(e, dreg, addr) emit_movsx_r32_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1726	#define emit_movsx_r32_m16bd(e, dreg, base, disp) emit_movsx_r32_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1727	#define emit_movsx_r32_m16isd(e, dreg, index, scale, disp) emit_movsx_r32_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1728
	1729
	1730	/*------------------------------------------------------------------
	1731	emit_movzx_r32_*
	1732	------------------------------------------------------------------*/
	1733
	1734	INLINE void emit_movzx_r32_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1735	{
	1736	emit_byte(emitptr, PREFIX_OPSIZE);
	1737	emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, sreg);
	1738	}
	1739
	1740	INLINE void emit_movzx_r32_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1741	{
	1742	emit_byte(emitptr, PREFIX_OPSIZE);
	1743	emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_32BIT, dreg, base, index, scale, disp);
	1744	}
	1745
	1746	INLINE void emit_movzx_r32_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1747	{
	1748	emit_byte(emitptr, PREFIX_OPSIZE);
	1749	emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Ew, OP_32BIT, dreg, sreg);
	1750	}
	1751
	1752	INLINE void emit_movzx_r32_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1753	{
	1754	emit_byte(emitptr, PREFIX_OPSIZE);
	1755	emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Ew, OP_32BIT, dreg, base, index, scale, disp);
	1756	}
	1757
	1758	#define emit_movzx_r32_m8abs(e, dreg, addr) emit_movzx_r32_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1759	#define emit_movzx_r32_m8bd(e, dreg, base, disp) emit_movzx_r32_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1760	#define emit_movzx_r32_m8isd(e, dreg, index, scale, disp) emit_movzx_r32_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1761
	1762	#define emit_movzx_r32_m16abs(e, dreg, addr) emit_movzx_r32_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1763	#define emit_movzx_r32_m16bd(e, dreg, base, disp) emit_movzx_r32_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1764	#define emit_movzx_r32_m16isd(e, dreg, index, scale, disp) emit_movzx_r32_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1765
	1766
	1767	/*------------------------------------------------------------------
	1768	emit_movsx_r64_*
	1769	------------------------------------------------------------------*/
	1770
	1771	#ifdef PTR64
	1772
	1773	INLINE void emit_movsx_r64_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1774	{
	1775	emit_byte(emitptr, PREFIX_OPSIZE);
	1776	emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Eb, OP_64BIT, dreg, sreg);
	1777	}
	1778
	1779	INLINE void emit_movsx_r64_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1780	{
	1781	emit_byte(emitptr, PREFIX_OPSIZE);
	1782	emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Eb, OP_64BIT, dreg, base, index, scale, disp);
	1783	}
	1784
	1785	INLINE void emit_movsx_r64_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1786	{
	1787	emit_byte(emitptr, PREFIX_OPSIZE);
	1788	emit_op_modrm_reg(emitptr, OP_MOVSX_Gv_Ew, OP_64BIT, dreg, sreg);
	1789	}
	1790
	1791	INLINE void emit_movsx_r64_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1792	{
	1793	emit_byte(emitptr, PREFIX_OPSIZE);
	1794	emit_op_modrm_mem(emitptr, OP_MOVSX_Gv_Ew, OP_64BIT, dreg, base, index, scale, disp);
	1795	}
	1796
	1797	INLINE void emit_movsxd_r64_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1798	{
	1799	emit_byte(emitptr, PREFIX_OPSIZE);
	1800	emit_op_modrm_reg(emitptr, OP_MOVSXD_Gv_Ev, OP_64BIT, dreg, sreg);
	1801	}
	1802
	1803	INLINE void emit_movsxd_r64_m32bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1804	{
	1805	emit_byte(emitptr, PREFIX_OPSIZE);
	1806	emit_op_modrm_mem(emitptr, OP_MOVSXD_Gv_Ev, OP_64BIT, dreg, base, index, scale, disp);
	1807	}
	1808
	1809	#define emit_movsx_r64_m8abs(e, dreg, addr) emit_movsx_r64_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1810	#define emit_movsx_r64_m8bd(e, dreg, base, disp) emit_movsx_r64_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1811	#define emit_movsx_r64_m8isd(e, dreg, index, scale, disp) emit_movsx_r64_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1812
	1813	#define emit_movsx_r64_m16abs(e, dreg, addr) emit_movsx_r64_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1814	#define emit_movsx_r64_m16bd(e, dreg, base, disp) emit_movsx_r64_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1815	#define emit_movsx_r64_m16isd(e, dreg, index, scale, disp) emit_movsx_r64_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1816
	1817	#define emit_movsxd_r64_m32abs(e, dreg, addr) emit_movsxd_r64_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1818	#define emit_movsxd_r64_m32bd(e, dreg, base, disp) emit_movsxd_r64_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1819	#define emit_movsxd_r64_m32isd(e, dreg, index, scale, disp) emit_movsxd_r64_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1820
	1821	#endif
	1822
	1823
	1824	/*------------------------------------------------------------------
	1825	emit_movzx_r64_*
	1826	------------------------------------------------------------------*/
	1827
	1828	#ifdef PTR64
	1829
	1830	INLINE void emit_movzx_r64_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1831	{
	1832	emit_byte(emitptr, PREFIX_OPSIZE);
	1833	emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Eb, OP_64BIT, dreg, sreg);
	1834	}
	1835
	1836	INLINE void emit_movzx_r64_m8bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1837	{
	1838	emit_byte(emitptr, PREFIX_OPSIZE);
	1839	emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Eb, OP_64BIT, dreg, base, index, scale, disp);
	1840	}
	1841
	1842	INLINE void emit_movzx_r64_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1843	{
	1844	emit_byte(emitptr, PREFIX_OPSIZE);
	1845	emit_op_modrm_reg(emitptr, OP_MOVZX_Gv_Ew, OP_64BIT, dreg, sreg);
	1846	}
	1847
	1848	INLINE void emit_movzx_r64_m16bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	1849	{
	1850	emit_byte(emitptr, PREFIX_OPSIZE);
	1851	emit_op_modrm_mem(emitptr, OP_MOVZX_Gv_Ew, OP_64BIT, dreg, base, index, scale, disp);
	1852	}
	1853
	1854	#define emit_movzx_r64_m8abs(e, dreg, addr) emit_movzx_r64_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1855	#define emit_movzx_r64_m8bd(e, dreg, base, disp) emit_movzx_r64_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1856	#define emit_movzx_r64_m8isd(e, dreg, index, scale, disp) emit_movzx_r64_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1857
	1858	#define emit_movzx_r64_m16abs(e, dreg, addr) emit_movzx_r64_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	1859	#define emit_movzx_r64_m16bd(e, dreg, base, disp) emit_movzx_r64_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	1860	#define emit_movzx_r64_m16isd(e, dreg, index, scale, disp) emit_movzx_r64_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	1861
	1862	#endif
	1863
	1864
	1865
	1866	/***************************************************************************
	1867	TEST EMITTERS
	1868	***************************************************************************/
	1869
	1870	/*------------------------------------------------------------------
	1871	emit_test_r8_*
	1872	------------------------------------------------------------------*/
	1873
	1874	INLINE void emit_test_r8_imm(x86code **emitptr, UINT8 dreg, UINT8 imm)
	1875	{
	1876	emit_op_modrm_reg(emitptr, OP_G3_Eb, OP_32BIT, 0, dreg);
	1877	emit_byte(emitptr, imm);
	1878	}
	1879
	1880	INLINE void emit_test_r8_r8(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1881	{
	1882	emit_op_modrm_reg(emitptr, OP_TEST_Eb_Gb, OP_32BIT, sreg, dreg);
	1883	}
	1884
	1885	INLINE void emit_test_m8bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
	1886	{
	1887	emit_op_modrm_mem(emitptr, OP_G3_Eb, OP_32BIT, 0, base, index, scale, disp);
	1888	emit_byte(emitptr, imm);
	1889	}
	1890
	1891	INLINE void emit_test_m8bisd_r8(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	1892	{
	1893	emit_op_modrm_mem(emitptr, OP_TEST_Eb_Gb, OP_32BIT, sreg, base, index, scale, disp);
	1894	}
	1895
	1896	#define emit_test_m8abs_imm(e, addr, imm) emit_test_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	1897	#define emit_test_m8bd_imm(e, base, disp, imm) emit_test_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	1898	#define emit_test_m8isd_imm(e, index, scale, disp, imm) emit_test_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	1899
	1900	#define emit_test_m8abs_r8(e, addr, sreg) emit_test_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	1901	#define emit_test_m8bd_r8(e, base, disp, sreg) emit_test_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
	1902	#define emit_test_m8isd_r8(e, index, scale, disp, sreg) emit_test_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
	1903
	1904
	1905	/*------------------------------------------------------------------
	1906	emit_test_r16_*
	1907	------------------------------------------------------------------*/
	1908
	1909	INLINE void emit_test_r16_imm(x86code **emitptr, UINT8 dreg, UINT16 imm)
	1910	{
	1911	emit_byte(emitptr, PREFIX_OPSIZE);
	1912	emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 0, dreg);
	1913	emit_word(emitptr, imm);
	1914	}
	1915
	1916	INLINE void emit_test_r16_r16(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1917	{
	1918	emit_byte(emitptr, PREFIX_OPSIZE);
	1919	emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, dreg);
	1920	}
	1921
	1922	INLINE void emit_test_m16bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT16 imm)
	1923	{
	1924	emit_byte(emitptr, PREFIX_OPSIZE);
	1925	emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 0, base, index, scale, disp);
	1926	emit_word(emitptr, imm);
	1927	}
	1928
	1929	INLINE void emit_test_m16bisd_r16(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	1930	{
	1931	emit_byte(emitptr, PREFIX_OPSIZE);
	1932	emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
	1933	}
	1934
	1935	#define emit_test_m16abs_imm(e, addr, imm) emit_test_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	1936	#define emit_test_m16bd_imm(e, base, disp, imm) emit_test_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	1937	#define emit_test_m16isd_imm(e, index, scale, disp, imm) emit_test_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	1938
	1939	#define emit_test_m16abs_r16(e, addr, sreg) emit_test_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	1940	#define emit_test_m16bd_r16(e, base, disp, sreg) emit_test_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
	1941	#define emit_test_m16isd_r16(e, index, scale, disp, sreg) emit_test_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
	1942
	1943
	1944	/*------------------------------------------------------------------
	1945	emit_test_r32_*
	1946	------------------------------------------------------------------*/
	1947
	1948	INLINE void emit_test_r32_imm(x86code **emitptr, UINT8 dreg, UINT32 imm)
	1949	{
	1950	emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, 0, dreg);
	1951	emit_dword(emitptr, imm);
	1952	}
	1953
	1954	INLINE void emit_test_r32_r32(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1955	{
	1956	emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, dreg);
	1957	}
	1958
	1959	INLINE void emit_test_m32bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
	1960	{
	1961	emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, 0, base, index, scale, disp);
	1962	emit_dword(emitptr, imm);
	1963	}
	1964
	1965	INLINE void emit_test_m32bisd_r32(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	1966	{
	1967	emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_32BIT, sreg, base, index, scale, disp);
	1968	}
	1969
	1970	#define emit_test_m32abs_imm(e, addr, imm) emit_test_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	1971	#define emit_test_m32bd_imm(e, base, disp, imm) emit_test_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	1972	#define emit_test_m32isd_imm(e, index, scale, disp, imm) emit_test_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	1973
	1974	#define emit_test_m32abs_r32(e, addr, sreg) emit_test_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	1975	#define emit_test_m32bd_r32(e, base, disp, sreg) emit_test_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
	1976	#define emit_test_m32isd_r32(e, index, scale, disp, sreg) emit_test_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	1977
	1978
	1979	/*------------------------------------------------------------------
	1980	emit_test_r64_*
	1981	------------------------------------------------------------------*/
	1982
	1983	#ifdef PTR64
	1984
	1985	INLINE void emit_test_r64_imm(x86code **emitptr, UINT8 dreg, UINT64 imm)
	1986	{
	1987	assert((INT32)imm == (INT64)imm);
	1988	emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, 0, dreg);
	1989	emit_dword(emitptr, imm);
	1990	}
	1991
	1992	INLINE void emit_test_r64_r64(x86code **emitptr, UINT8 dreg, UINT8 sreg)
	1993	{
	1994	emit_op_modrm_reg(emitptr, OP_TEST_Ev_Gv, OP_64BIT, sreg, dreg);
	1995	}
	1996
	1997	INLINE void emit_test_m64bisd_imm(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT64 imm)
	1998	{
	1999	assert((INT32)imm == (INT64)imm);
	2000	emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, 0, base, index, scale, disp);
	2001	emit_dword(emitptr, (INT32)imm);
	2002	}
	2003
	2004	INLINE void emit_test_m64bisd_r64(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	2005	{
	2006	emit_op_modrm_mem(emitptr, OP_TEST_Ev_Gv, OP_64BIT, sreg, base, index, scale, disp);
	2007	}
	2008
	2009	#define emit_test_m64abs_imm(e, addr, imm) emit_test_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2010	#define emit_test_m64bd_imm(e, base, disp, imm) emit_test_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2011	#define emit_test_m64isd_imm(e, index, scale, disp, imm) emit_test_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2012
	2013	#define emit_test_m64abs_r64(e, addr, sreg) emit_test_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2014	#define emit_test_m64bd_r64(e, base, disp, sreg) emit_test_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
	2015	#define emit_test_m64isd_r64(e, index, scale, disp, sreg) emit_test_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
	2016
	2017	#endif
	2018
	2019
	2020
	2021	/***************************************************************************
	2022	8-BIT ARITHMETIC EMITTERS
	2023	***************************************************************************/
	2024
	2025	/*
	2026	Note that the following code relies on this:
	2027
	2028	00-05 or /0 = ADD
	2029	08-0d or /1 = OR
	2030	10-15 or /2 = ADC
	2031	18-1d or /3 = SBB
	2032	20-25 or /4 = AND
	2033	28-2d or /5 = SUB
	2034	30-35 or /6 = XOR
	2035	38-3d or /7 = CMP
	2036	*/
	2037
	2038	/*------------------------------------------------------------------
	2039	emit_arith_r8_*
	2040	------------------------------------------------------------------*/
	2041
	2042	INLINE void emit_arith_r8_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
	2043	{
	2044	emit_op_modrm_reg(emitptr, OP_G1_Eb_Ib, OP_32BIT, opindex, dreg);
	2045	emit_byte(emitptr, imm);
	2046	}
	2047
	2048	INLINE void emit_arith_m8bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
	2049	{
	2050	emit_op_modrm_mem(emitptr, OP_G1_Eb_Ib, OP_32BIT, opindex, base, index, scale, disp);
	2051	emit_byte(emitptr, imm);
	2052	}
	2053
	2054	INLINE void emit_arith_r8_r8(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
	2055	{
	2056	emit_op_modrm_reg(emitptr, OP_ADD_Eb_Gb + 8 * opindex, OP_32BIT, dreg, sreg);
	2057	}
	2058
	2059	INLINE void emit_arith_r8_m8bisd(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	2060	{
	2061	emit_op_modrm_mem(emitptr, OP_ADD_Eb_Gb + 8 * opindex, OP_32BIT, dreg, base, index, scale, disp);
	2062	}
	2063
	2064	INLINE void emit_arith_m8bisd_r8(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	2065	{
	2066	emit_op_modrm_mem(emitptr, OP_ADD_Gb_Eb + 8 * opindex, OP_32BIT, sreg, base, index, scale, disp);
	2067	}
	2068
	2069
	2070	/*------------------------------------------------------------------
	2071	emit_add_r8_*
	2072	------------------------------------------------------------------*/
	2073
	2074	#define emit_add_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 0, dreg, imm)
	2075	#define emit_add_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 0, base, index, scale, disp, imm)
	2076	#define emit_add_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 0, dreg, sreg)
	2077	#define emit_add_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 0, dreg, base, index, scale, disp)
	2078	#define emit_add_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 0, base, index, scale, disp, sreg)
	2079
	2080	#define emit_add_m8abs_imm(e, addr, imm) emit_add_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2081	#define emit_add_m8bd_imm(e, base, disp, imm) emit_add_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2082	#define emit_add_m8isd_imm(e, index, scale, disp, imm) emit_add_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2083
	2084	#define emit_add_r8_m8abs(e, dreg, addr) emit_add_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2085	#define emit_add_r8_m8bd(e, dreg, base, disp) emit_add_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2086	#define emit_add_r8_m8isd(e, dreg, index, scale, disp) emit_add_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2087
	2088	#define emit_add_m8abs_r8(e, addr, sreg) emit_add_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2089	#define emit_add_m8bd_r8(e, base, disp, sreg) emit_add_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
	2090	#define emit_add_m8isd_r8(e, index, scale, disp, sreg) emit_add_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
	2091
	2092
	2093	/*------------------------------------------------------------------
	2094	emit_or_r8_*
	2095	------------------------------------------------------------------*/
	2096
	2097	#define emit_or_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 1, dreg, imm)
	2098	#define emit_or_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 1, base, index, scale, disp, imm)
	2099	#define emit_or_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 1, dreg, sreg)
	2100	#define emit_or_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 1, dreg, base, index, scale, disp)
	2101	#define emit_or_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 1, base, index, scale, disp, sreg)
	2102
	2103	#define emit_or_m8abs_imm(e, addr, imm) emit_or_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2104	#define emit_or_m8bd_imm(e, base, disp, imm) emit_or_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2105	#define emit_or_m8isd_imm(e, index, scale, disp, imm) emit_or_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2106
	2107	#define emit_or_r8_m8abs(e, dreg, addr) emit_or_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2108	#define emit_or_r8_m8bd(e, dreg, base, disp) emit_or_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2109	#define emit_or_r8_m8isd(e, dreg, index, scale, disp) emit_or_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2110
	2111	#define emit_or_m8abs_r8(e, addr, sreg) emit_or_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2112	#define emit_or_m8bd_r8(e, base, disp, sreg) emit_or_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
	2113	#define emit_or_m8isd_r8(e, index, scale, disp, sreg) emit_or_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
	2114
	2115
	2116	/*------------------------------------------------------------------
	2117	emit_adc_r8_*
	2118	------------------------------------------------------------------*/
	2119
	2120	#define emit_adc_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 2, dreg, imm)
	2121	#define emit_adc_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 2, base, index, scale, disp, imm)
	2122	#define emit_adc_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 2, dreg, sreg)
	2123	#define emit_adc_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 2, dreg, base, index, scale, disp)
	2124	#define emit_adc_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 2, base, index, scale, disp, sreg)
	2125
	2126	#define emit_adc_m8abs_imm(e, addr, imm) emit_adc_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2127	#define emit_adc_m8bd_imm(e, base, disp, imm) emit_adc_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2128	#define emit_adc_m8isd_imm(e, index, scale, disp, imm) emit_adc_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2129
	2130	#define emit_adc_r8_m8abs(e, dreg, addr) emit_adc_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2131	#define emit_adc_r8_m8bd(e, dreg, base, disp) emit_adc_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2132	#define emit_adc_r8_m8isd(e, dreg, index, scale, disp) emit_adc_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2133
	2134	#define emit_adc_m8abs_r8(e, addr, sreg) emit_adc_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2135	#define emit_adc_m8bd_r8(e, base, disp, sreg) emit_adc_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
	2136	#define emit_adc_m8isd_r8(e, index, scale, disp, sreg) emit_adc_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
	2137
	2138
	2139	/*------------------------------------------------------------------
	2140	emit_sbb_r8_*
	2141	------------------------------------------------------------------*/
	2142
	2143	#define emit_sbb_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 3, dreg, imm)
	2144	#define emit_sbb_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 3, base, index, scale, disp, imm)
	2145	#define emit_sbb_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 3, dreg, sreg)
	2146	#define emit_sbb_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 3, dreg, base, index, scale, disp)
	2147	#define emit_sbb_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 3, base, index, scale, disp, sreg)
	2148
	2149	#define emit_sbb_m8abs_imm(e, addr, imm) emit_sbb_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2150	#define emit_sbb_m8bd_imm(e, base, disp, imm) emit_sbb_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2151	#define emit_sbb_m8isd_imm(e, index, scale, disp, imm) emit_sbb_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2152
	2153	#define emit_sbb_r8_m8abs(e, dreg, addr) emit_sbb_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2154	#define emit_sbb_r8_m8bd(e, dreg, base, disp) emit_sbb_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2155	#define emit_sbb_r8_m8isd(e, dreg, index, scale, disp) emit_sbb_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2156
	2157	#define emit_sbb_m8abs_r8(e, addr, sreg) emit_sbb_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2158	#define emit_sbb_m8bd_r8(e, base, disp, sreg) emit_sbb_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
	2159	#define emit_sbb_m8isd_r8(e, index, scale, disp, sreg) emit_sbb_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
	2160
	2161
	2162	/*------------------------------------------------------------------
	2163	emit_and_r8_*
	2164	------------------------------------------------------------------*/
	2165
	2166	#define emit_and_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 4, dreg, imm)
	2167	#define emit_and_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 4, base, index, scale, disp, imm)
	2168	#define emit_and_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 4, dreg, sreg)
	2169	#define emit_and_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 4, dreg, base, index, scale, disp)
	2170	#define emit_and_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 4, base, index, scale, disp, sreg)
	2171
	2172	#define emit_and_m8abs_imm(e, addr, imm) emit_and_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2173	#define emit_and_m8bd_imm(e, base, disp, imm) emit_and_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2174	#define emit_and_m8isd_imm(e, index, scale, disp, imm) emit_and_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2175
	2176	#define emit_and_r8_m8abs(e, dreg, addr) emit_and_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2177	#define emit_and_r8_m8bd(e, dreg, base, disp) emit_and_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2178	#define emit_and_r8_m8isd(e, dreg, index, scale, disp) emit_and_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2179
	2180	#define emit_and_m8abs_r8(e, addr, sreg) emit_and_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2181	#define emit_and_m8bd_r8(e, base, disp, sreg) emit_and_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
	2182	#define emit_and_m8isd_r8(e, index, scale, disp, sreg) emit_and_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
	2183
	2184
	2185	/*------------------------------------------------------------------
	2186	emit_sub_r8_*
	2187	------------------------------------------------------------------*/
	2188
	2189	#define emit_sub_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 5, dreg, imm)
	2190	#define emit_sub_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 5, base, index, scale, disp, imm)
	2191	#define emit_sub_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 5, dreg, sreg)
	2192	#define emit_sub_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 5, dreg, base, index, scale, disp)
	2193	#define emit_sub_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 5, base, index, scale, disp, sreg)
	2194
	2195	#define emit_sub_m8abs_imm(e, addr, imm) emit_sub_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2196	#define emit_sub_m8bd_imm(e, base, disp, imm) emit_sub_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2197	#define emit_sub_m8isd_imm(e, index, scale, disp, imm) emit_sub_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2198
	2199	#define emit_sub_r8_m8abs(e, dreg, addr) emit_sub_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2200	#define emit_sub_r8_m8bd(e, dreg, base, disp) emit_sub_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2201	#define emit_sub_r8_m8isd(e, dreg, index, scale, disp) emit_sub_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2202
	2203	#define emit_sub_m8abs_r8(e, addr, sreg) emit_sub_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2204	#define emit_sub_m8bd_r8(e, base, disp, sreg) emit_sub_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
	2205	#define emit_sub_m8isd_r8(e, index, scale, disp, sreg) emit_sub_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
	2206
	2207
	2208	/*------------------------------------------------------------------
	2209	emit_xor_r8_*
	2210	------------------------------------------------------------------*/
	2211
	2212	#define emit_xor_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 6, dreg, imm)
	2213	#define emit_xor_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 6, base, index, scale, disp, imm)
	2214	#define emit_xor_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 6, dreg, sreg)
	2215	#define emit_xor_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 6, dreg, base, index, scale, disp)
	2216	#define emit_xor_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 6, base, index, scale, disp, sreg)
	2217
	2218	#define emit_xor_m8abs_imm(e, addr, imm) emit_xor_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2219	#define emit_xor_m8bd_imm(e, base, disp, imm) emit_xor_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2220	#define emit_xor_m8isd_imm(e, index, scale, disp, imm) emit_xor_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2221
	2222	#define emit_xor_r8_m8abs(e, dreg, addr) emit_xor_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2223	#define emit_xor_r8_m8bd(e, dreg, base, disp) emit_xor_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2224	#define emit_xor_r8_m8isd(e, dreg, index, scale, disp) emit_xor_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2225
	2226	#define emit_xor_m8abs_r8(e, addr, sreg) emit_xor_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2227	#define emit_xor_m8bd_r8(e, base, disp, sreg) emit_xor_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
	2228	#define emit_xor_m8isd_r8(e, index, scale, disp, sreg) emit_xor_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
	2229
	2230
	2231	/*------------------------------------------------------------------
	2232	emit_cmp_r8_*
	2233	------------------------------------------------------------------*/
	2234
	2235	#define emit_cmp_r8_imm(e, dreg, imm) emit_arith_r8_imm(e, 7, dreg, imm)
	2236	#define emit_cmp_m8bisd_imm(e, base, index, scale, disp, imm) emit_arith_m8bisd_imm(e, 7, base, index, scale, disp, imm)
	2237	#define emit_cmp_r8_r8(e, dreg, sreg) emit_arith_r8_r8(e, 7, dreg, sreg)
	2238	#define emit_cmp_r8_m8bisd(e, dreg, base, index, scale, disp) emit_arith_r8_m8bisd(e, 7, dreg, base, index, scale, disp)
	2239	#define emit_cmp_m8bisd_r8(e, base, index, scale, disp, sreg) emit_arith_m8bisd_r8(e, 7, base, index, scale, disp, sreg)
	2240
	2241	#define emit_cmp_m8abs_imm(e, addr, imm) emit_cmp_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2242	#define emit_cmp_m8bd_imm(e, base, disp, imm) emit_cmp_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2243	#define emit_cmp_m8isd_imm(e, index, scale, disp, imm) emit_cmp_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2244
	2245	#define emit_cmp_r8_m8abs(e, dreg, addr) emit_cmp_r8_m8bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2246	#define emit_cmp_r8_m8bd(e, dreg, base, disp) emit_cmp_r8_m8bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2247	#define emit_cmp_r8_m8isd(e, dreg, index, scale, disp) emit_cmp_r8_m8bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2248
	2249	#define emit_cmp_m8abs_r8(e, addr, sreg) emit_cmp_m8bisd_r8(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2250	#define emit_cmp_m8bd_r8(e, base, disp, sreg) emit_cmp_m8bisd_r8(e, (base), REG_NONE, 1, (disp), sreg)
	2251	#define emit_cmp_m8isd_r8(e, index, scale, disp, sreg) emit_cmp_m8bisd_r8(e, REG_NONE, (index), (scale), (disp), sreg)
	2252
	2253
	2254
	2255	/***************************************************************************
	2256	16-BIT ARITHMETIC EMITTERS
	2257	***************************************************************************/
	2258
	2259	/*
	2260	Note that the following code relies on this:
	2261
	2262	00-05 or /0 = ADD
	2263	08-0d or /1 = OR
	2264	10-15 or /2 = ADC
	2265	18-1d or /3 = SBB
	2266	20-25 or /4 = AND
	2267	28-2d or /5 = SUB
	2268	30-35 or /6 = XOR
	2269	38-3d or /7 = CMP
	2270	*/
	2271
	2272	INLINE void emit_arith_r16_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT16 imm)
	2273	{
	2274	emit_byte(emitptr, PREFIX_OPSIZE);
	2275	if ((INT8)imm == (INT16)imm)
	2276	{
	2277	emit_op_modrm_reg(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, dreg);
	2278	emit_byte(emitptr, (INT8)imm);
	2279	}
	2280	else
	2281	{
	2282	emit_op_modrm_reg(emitptr, OP_G1_Ev_Iz, OP_32BIT, opindex, dreg);
	2283	emit_word(emitptr, imm);
	2284	}
	2285	}
	2286
	2287	INLINE void emit_arith_m16bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT16 imm)
	2288	{
	2289	emit_byte(emitptr, PREFIX_OPSIZE);
	2290	if ((INT8)imm == (INT16)imm)
	2291	{
	2292	emit_op_modrm_mem(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
	2293	emit_byte(emitptr, (INT8)imm);
	2294	}
	2295	else
	2296	{
	2297	emit_op_modrm_mem(emitptr, OP_G1_Ev_Iz, OP_32BIT, opindex, base, index, scale, disp);
	2298	emit_word(emitptr, imm);
	2299	}
	2300	}
	2301
	2302	INLINE void emit_arith_r16_r16(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
	2303	{
	2304	emit_byte(emitptr, PREFIX_OPSIZE);
	2305	emit_op_modrm_reg(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_32BIT, dreg, sreg);
	2306	}
	2307
	2308	INLINE void emit_arith_r16_m16bisd(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	2309	{
	2310	emit_byte(emitptr, PREFIX_OPSIZE);
	2311	emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_32BIT, dreg, base, index, scale, disp);
	2312	}
	2313
	2314	INLINE void emit_arith_m16bisd_r16(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	2315	{
	2316	emit_byte(emitptr, PREFIX_OPSIZE);
	2317	emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_32BIT, sreg, base, index, scale, disp);
	2318	}
	2319
	2320
	2321	/*------------------------------------------------------------------
	2322	emit_add_r16_*
	2323	------------------------------------------------------------------*/
	2324
	2325	#define emit_add_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 0, dreg, imm)
	2326	#define emit_add_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 0, base, index, scale, disp, imm)
	2327	#define emit_add_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 0, dreg, sreg)
	2328	#define emit_add_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 0, dreg, base, index, scale, disp)
	2329	#define emit_add_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 0, base, index, scale, disp, sreg)
	2330
	2331	#define emit_add_m16abs_imm(e, addr, imm) emit_add_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2332	#define emit_add_m16bd_imm(e, base, disp, imm) emit_add_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2333	#define emit_add_m16isd_imm(e, index, scale, disp, imm) emit_add_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2334
	2335	#define emit_add_r16_m16abs(e, dreg, addr) emit_add_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2336	#define emit_add_r16_m16bd(e, dreg, base, disp) emit_add_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2337	#define emit_add_r16_m16isd(e, dreg, index, scale, disp) emit_add_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2338
	2339	#define emit_add_m16abs_r16(e, addr, sreg) emit_add_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2340	#define emit_add_m16bd_r16(e, base, disp, sreg) emit_add_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
	2341	#define emit_add_m16isd_r16(e, index, scale, disp, sreg) emit_add_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
	2342
	2343
	2344	/*------------------------------------------------------------------
	2345	emit_or_r16_*
	2346	------------------------------------------------------------------*/
	2347
	2348	#define emit_or_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 1, dreg, imm)
	2349	#define emit_or_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 1, base, index, scale, disp, imm)
	2350	#define emit_or_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 1, dreg, sreg)
	2351	#define emit_or_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 1, dreg, base, index, scale, disp)
	2352	#define emit_or_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 1, base, index, scale, disp, sreg)
	2353
	2354	#define emit_or_m16abs_imm(e, addr, imm) emit_or_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2355	#define emit_or_m16bd_imm(e, base, disp, imm) emit_or_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2356	#define emit_or_m16isd_imm(e, index, scale, disp, imm) emit_or_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2357
	2358	#define emit_or_r16_m16abs(e, dreg, addr) emit_or_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2359	#define emit_or_r16_m16bd(e, dreg, base, disp) emit_or_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2360	#define emit_or_r16_m16isd(e, dreg, index, scale, disp) emit_or_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2361
	2362	#define emit_or_m16abs_r16(e, addr, sreg) emit_or_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2363	#define emit_or_m16bd_r16(e, base, disp, sreg) emit_or_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
	2364	#define emit_or_m16isd_r16(e, index, scale, disp, sreg) emit_or_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
	2365
	2366
	2367	/*------------------------------------------------------------------
	2368	emit_adc_r16_*
	2369	------------------------------------------------------------------*/
	2370
	2371	#define emit_adc_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 2, dreg, imm)
	2372	#define emit_adc_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 2, base, index, scale, disp, imm)
	2373	#define emit_adc_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 2, dreg, sreg)
	2374	#define emit_adc_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 2, dreg, base, index, scale, disp)
	2375	#define emit_adc_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 2, base, index, scale, disp, sreg)
	2376
	2377	#define emit_adc_m16abs_imm(e, addr, imm) emit_adc_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2378	#define emit_adc_m16bd_imm(e, base, disp, imm) emit_adc_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2379	#define emit_adc_m16isd_imm(e, index, scale, disp, imm) emit_adc_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2380
	2381	#define emit_adc_r16_m16abs(e, dreg, addr) emit_adc_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2382	#define emit_adc_r16_m16bd(e, dreg, base, disp) emit_adc_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2383	#define emit_adc_r16_m16isd(e, dreg, index, scale, disp) emit_adc_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2384
	2385	#define emit_adc_m16abs_r16(e, addr, sreg) emit_adc_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2386	#define emit_adc_m16bd_r16(e, base, disp, sreg) emit_adc_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
	2387	#define emit_adc_m16isd_r16(e, index, scale, disp, sreg) emit_adc_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
	2388
	2389
	2390	/*------------------------------------------------------------------
	2391	emit_sbb_r16_*
	2392	------------------------------------------------------------------*/
	2393
	2394	#define emit_sbb_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 3, dreg, imm)
	2395	#define emit_sbb_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 3, base, index, scale, disp, imm)
	2396	#define emit_sbb_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 3, dreg, sreg)
	2397	#define emit_sbb_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 3, dreg, base, index, scale, disp)
	2398	#define emit_sbb_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 3, base, index, scale, disp, sreg)
	2399
	2400	#define emit_sbb_m16abs_imm(e, addr, imm) emit_sbb_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2401	#define emit_sbb_m16bd_imm(e, base, disp, imm) emit_sbb_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2402	#define emit_sbb_m16isd_imm(e, index, scale, disp, imm) emit_sbb_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2403
	2404	#define emit_sbb_r16_m16abs(e, dreg, addr) emit_sbb_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2405	#define emit_sbb_r16_m16bd(e, dreg, base, disp) emit_sbb_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2406	#define emit_sbb_r16_m16isd(e, dreg, index, scale, disp) emit_sbb_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2407
	2408	#define emit_sbb_m16abs_r16(e, addr, sreg) emit_sbb_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2409	#define emit_sbb_m16bd_r16(e, base, disp, sreg) emit_sbb_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
	2410	#define emit_sbb_m16isd_r16(e, index, scale, disp, sreg) emit_sbb_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
	2411
	2412
	2413	/*------------------------------------------------------------------
	2414	emit_and_r16_*
	2415	------------------------------------------------------------------*/
	2416
	2417	#define emit_and_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 4, dreg, imm)
	2418	#define emit_and_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 4, base, index, scale, disp, imm)
	2419	#define emit_and_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 4, dreg, sreg)
	2420	#define emit_and_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 4, dreg, base, index, scale, disp)
	2421	#define emit_and_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 4, base, index, scale, disp, sreg)
	2422
	2423	#define emit_and_m16abs_imm(e, addr, imm) emit_and_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2424	#define emit_and_m16bd_imm(e, base, disp, imm) emit_and_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2425	#define emit_and_m16isd_imm(e, index, scale, disp, imm) emit_and_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2426
	2427	#define emit_and_r16_m16abs(e, dreg, addr) emit_and_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2428	#define emit_and_r16_m16bd(e, dreg, base, disp) emit_and_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2429	#define emit_and_r16_m16isd(e, dreg, index, scale, disp) emit_and_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2430
	2431	#define emit_and_m16abs_r16(e, addr, sreg) emit_and_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2432	#define emit_and_m16bd_r16(e, base, disp, sreg) emit_and_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
	2433	#define emit_and_m16isd_r16(e, index, scale, disp, sreg) emit_and_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
	2434
	2435
	2436	/*------------------------------------------------------------------
	2437	emit_sub_r16_*
	2438	------------------------------------------------------------------*/
	2439
	2440	#define emit_sub_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 5, dreg, imm)
	2441	#define emit_sub_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 5, base, index, scale, disp, imm)
	2442	#define emit_sub_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 5, dreg, sreg)
	2443	#define emit_sub_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 5, dreg, base, index, scale, disp)
	2444	#define emit_sub_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 5, base, index, scale, disp, sreg)
	2445
	2446	#define emit_sub_m16abs_imm(e, addr, imm) emit_sub_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2447	#define emit_sub_m16bd_imm(e, base, disp, imm) emit_sub_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2448	#define emit_sub_m16isd_imm(e, index, scale, disp, imm) emit_sub_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2449
	2450	#define emit_sub_r16_m16abs(e, dreg, addr) emit_sub_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2451	#define emit_sub_r16_m16bd(e, dreg, base, disp) emit_sub_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2452	#define emit_sub_r16_m16isd(e, dreg, index, scale, disp) emit_sub_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2453
	2454	#define emit_sub_m16abs_r16(e, addr, sreg) emit_sub_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2455	#define emit_sub_m16bd_r16(e, base, disp, sreg) emit_sub_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
	2456	#define emit_sub_m16isd_r16(e, index, scale, disp, sreg) emit_sub_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
	2457
	2458
	2459	/*------------------------------------------------------------------
	2460	emit_xor_r16_*
	2461	------------------------------------------------------------------*/
	2462
	2463	#define emit_xor_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 6, dreg, imm)
	2464	#define emit_xor_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 6, base, index, scale, disp, imm)
	2465	#define emit_xor_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 6, dreg, sreg)
	2466	#define emit_xor_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 6, dreg, base, index, scale, disp)
	2467	#define emit_xor_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 6, base, index, scale, disp, sreg)
	2468
	2469	#define emit_xor_m16abs_imm(e, addr, imm) emit_xor_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2470	#define emit_xor_m16bd_imm(e, base, disp, imm) emit_xor_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2471	#define emit_xor_m16isd_imm(e, index, scale, disp, imm) emit_xor_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2472
	2473	#define emit_xor_r16_m16abs(e, dreg, addr) emit_xor_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2474	#define emit_xor_r16_m16bd(e, dreg, base, disp) emit_xor_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2475	#define emit_xor_r16_m16isd(e, dreg, index, scale, disp) emit_xor_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2476
	2477	#define emit_xor_m16abs_r16(e, addr, sreg) emit_xor_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2478	#define emit_xor_m16bd_r16(e, base, disp, sreg) emit_xor_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
	2479	#define emit_xor_m16isd_r16(e, index, scale, disp, sreg) emit_xor_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
	2480
	2481
	2482	/*------------------------------------------------------------------
	2483	emit_cmp_r16_*
	2484	------------------------------------------------------------------*/
	2485
	2486	#define emit_cmp_r16_imm(e, dreg, imm) emit_arith_r16_imm(e, 7, dreg, imm)
	2487	#define emit_cmp_m16bisd_imm(e, base, index, scale, disp, imm) emit_arith_m16bisd_imm(e, 7, base, index, scale, disp, imm)
	2488	#define emit_cmp_r16_r16(e, dreg, sreg) emit_arith_r16_r16(e, 7, dreg, sreg)
	2489	#define emit_cmp_r16_m16bisd(e, dreg, base, index, scale, disp) emit_arith_r16_m16bisd(e, 7, dreg, base, index, scale, disp)
	2490	#define emit_cmp_m16bisd_r16(e, base, index, scale, disp, sreg) emit_arith_m16bisd_r16(e, 7, base, index, scale, disp, sreg)
	2491
	2492	#define emit_cmp_m16abs_imm(e, addr, imm) emit_cmp_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2493	#define emit_cmp_m16bd_imm(e, base, disp, imm) emit_cmp_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2494	#define emit_cmp_m16isd_imm(e, index, scale, disp, imm) emit_cmp_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2495
	2496	#define emit_cmp_r16_m16abs(e, dreg, addr) emit_cmp_r16_m16bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2497	#define emit_cmp_r16_m16bd(e, dreg, base, disp) emit_cmp_r16_m16bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2498	#define emit_cmp_r16_m16isd(e, dreg, index, scale, disp) emit_cmp_r16_m16bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2499
	2500	#define emit_cmp_m16abs_r16(e, addr, sreg) emit_cmp_m16bisd_r16(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2501	#define emit_cmp_m16bd_r16(e, base, disp, sreg) emit_cmp_m16bisd_r16(e, (base), REG_NONE, 1, (disp), sreg)
	2502	#define emit_cmp_m16isd_r16(e, index, scale, disp, sreg) emit_cmp_m16bisd_r16(e, REG_NONE, (index), (scale), (disp), sreg)
	2503
	2504
	2505
	2506	/***************************************************************************
	2507	32-BIT ARITHMETIC EMITTERS
	2508	***************************************************************************/
	2509
	2510	/*
	2511	Note that the following code relies on this:
	2512
	2513	00-05 or /0 = ADD
	2514	08-0d or /1 = OR
	2515	10-15 or /2 = ADC
	2516	18-1d or /3 = SBB
	2517	20-25 or /4 = AND
	2518	28-2d or /5 = SUB
	2519	30-35 or /6 = XOR
	2520	38-3d or /7 = CMP
	2521	*/
	2522
	2523	INLINE void emit_arith_r32_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT32 imm)
	2524	{
	2525	if ((INT8)imm == (INT32)imm)
	2526	{
	2527	emit_op_modrm_reg(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, dreg);
	2528	emit_byte(emitptr, (INT8)imm);
	2529	}
	2530	else
	2531	{
	2532	emit_op_modrm_reg(emitptr, OP_G1_Ev_Iz, OP_32BIT, opindex, dreg);
	2533	emit_dword(emitptr, imm);
	2534	}
	2535	}
	2536
	2537	INLINE void emit_arith_m32bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
	2538	{
	2539	if ((INT8)imm == (INT32)imm)
	2540	{
	2541	emit_op_modrm_mem(emitptr, OP_G1_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
	2542	emit_byte(emitptr, (INT8)imm);
	2543	}
	2544	else
	2545	{
	2546	emit_op_modrm_mem(emitptr, OP_G1_Ev_Iz, OP_32BIT, opindex, base, index, scale, disp);
	2547	emit_dword(emitptr, imm);
	2548	}
	2549	}
	2550
	2551	INLINE void emit_arith_r32_r32(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
	2552	{
	2553	emit_op_modrm_reg(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_32BIT, dreg, sreg);
	2554	}
	2555
	2556	INLINE void emit_arith_r32_m32bisd(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	2557	{
	2558	emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_32BIT, dreg, base, index, scale, disp);
	2559	}
	2560
	2561	INLINE void emit_arith_m32bisd_r32(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	2562	{
	2563	emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_32BIT, sreg, base, index, scale, disp);
	2564	}
	2565
	2566
	2567	/*------------------------------------------------------------------
	2568	emit_add_r32_*
	2569	------------------------------------------------------------------*/
	2570
	2571	#define emit_add_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 0, dreg, imm)
	2572	#define emit_add_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 0, base, index, scale, disp, imm)
	2573	#define emit_add_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 0, dreg, sreg)
	2574	#define emit_add_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 0, dreg, base, index, scale, disp)
	2575	#define emit_add_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 0, base, index, scale, disp, sreg)
	2576
	2577	#define emit_add_m32abs_imm(e, addr, imm) emit_add_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2578	#define emit_add_m32bd_imm(e, base, disp, imm) emit_add_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2579	#define emit_add_m32isd_imm(e, index, scale, disp, imm) emit_add_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2580
	2581	#define emit_add_r32_m32abs(e, dreg, addr) emit_add_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2582	#define emit_add_r32_m32bd(e, dreg, base, disp) emit_add_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2583	#define emit_add_r32_m32isd(e, dreg, index, scale, disp) emit_add_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2584
	2585	#define emit_add_m32abs_r32(e, addr, sreg) emit_add_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2586	#define emit_add_m32bd_r32(e, base, disp, sreg) emit_add_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
	2587	#define emit_add_m32isd_r32(e, index, scale, disp, sreg) emit_add_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	2588
	2589
	2590	/*------------------------------------------------------------------
	2591	emit_or_r32_*
	2592	------------------------------------------------------------------*/
	2593
	2594	#define emit_or_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 1, dreg, imm)
	2595	#define emit_or_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 1, base, index, scale, disp, imm)
	2596	#define emit_or_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 1, dreg, sreg)
	2597	#define emit_or_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 1, dreg, base, index, scale, disp)
	2598	#define emit_or_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 1, base, index, scale, disp, sreg)
	2599
	2600	#define emit_or_m32abs_imm(e, addr, imm) emit_or_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2601	#define emit_or_m32bd_imm(e, base, disp, imm) emit_or_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2602	#define emit_or_m32isd_imm(e, index, scale, disp, imm) emit_or_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2603
	2604	#define emit_or_r32_m32abs(e, dreg, addr) emit_or_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2605	#define emit_or_r32_m32bd(e, dreg, base, disp) emit_or_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2606	#define emit_or_r32_m32isd(e, dreg, index, scale, disp) emit_or_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2607
	2608	#define emit_or_m32abs_r32(e, addr, sreg) emit_or_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2609	#define emit_or_m32bd_r32(e, base, disp, sreg) emit_or_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
	2610	#define emit_or_m32isd_r32(e, index, scale, disp, sreg) emit_or_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	2611
	2612
	2613	/*------------------------------------------------------------------
	2614	emit_adc_r32_*
	2615	------------------------------------------------------------------*/
	2616
	2617	#define emit_adc_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 2, dreg, imm)
	2618	#define emit_adc_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 2, base, index, scale, disp, imm)
	2619	#define emit_adc_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 2, dreg, sreg)
	2620	#define emit_adc_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 2, dreg, base, index, scale, disp)
	2621	#define emit_adc_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 2, base, index, scale, disp, sreg)
	2622
	2623	#define emit_adc_m32abs_imm(e, addr, imm) emit_adc_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2624	#define emit_adc_m32bd_imm(e, base, disp, imm) emit_adc_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2625	#define emit_adc_m32isd_imm(e, index, scale, disp, imm) emit_adc_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2626
	2627	#define emit_adc_r32_m32abs(e, dreg, addr) emit_adc_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2628	#define emit_adc_r32_m32bd(e, dreg, base, disp) emit_adc_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2629	#define emit_adc_r32_m32isd(e, dreg, index, scale, disp) emit_adc_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2630
	2631	#define emit_adc_m32abs_r32(e, addr, sreg) emit_adc_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2632	#define emit_adc_m32bd_r32(e, base, disp, sreg) emit_adc_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
	2633	#define emit_adc_m32isd_r32(e, index, scale, disp, sreg) emit_adc_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	2634
	2635
	2636	/*------------------------------------------------------------------
	2637	emit_sbb_r32_*
	2638	------------------------------------------------------------------*/
	2639
	2640	#define emit_sbb_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 3, dreg, imm)
	2641	#define emit_sbb_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 3, base, index, scale, disp, imm)
	2642	#define emit_sbb_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 3, dreg, sreg)
	2643	#define emit_sbb_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 3, dreg, base, index, scale, disp)
	2644	#define emit_sbb_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 3, base, index, scale, disp, sreg)
	2645
	2646	#define emit_sbb_m32abs_imm(e, addr, imm) emit_sbb_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2647	#define emit_sbb_m32bd_imm(e, base, disp, imm) emit_sbb_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2648	#define emit_sbb_m32isd_imm(e, index, scale, disp, imm) emit_sbb_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2649
	2650	#define emit_sbb_r32_m32abs(e, dreg, addr) emit_sbb_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2651	#define emit_sbb_r32_m32bd(e, dreg, base, disp) emit_sbb_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2652	#define emit_sbb_r32_m32isd(e, dreg, index, scale, disp) emit_sbb_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2653
	2654	#define emit_sbb_m32abs_r32(e, addr, sreg) emit_sbb_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2655	#define emit_sbb_m32bd_r32(e, base, disp, sreg) emit_sbb_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
	2656	#define emit_sbb_m32isd_r32(e, index, scale, disp, sreg) emit_sbb_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	2657
	2658
	2659	/*------------------------------------------------------------------
	2660	emit_and_r32_*
	2661	------------------------------------------------------------------*/
	2662
	2663	#define emit_and_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 4, dreg, imm)
	2664	#define emit_and_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 4, base, index, scale, disp, imm)
	2665	#define emit_and_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 4, dreg, sreg)
	2666	#define emit_and_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 4, dreg, base, index, scale, disp)
	2667	#define emit_and_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 4, base, index, scale, disp, sreg)
	2668
	2669	#define emit_and_m32abs_imm(e, addr, imm) emit_and_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2670	#define emit_and_m32bd_imm(e, base, disp, imm) emit_and_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2671	#define emit_and_m32isd_imm(e, index, scale, disp, imm) emit_and_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2672
	2673	#define emit_and_r32_m32abs(e, dreg, addr) emit_and_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2674	#define emit_and_r32_m32bd(e, dreg, base, disp) emit_and_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2675	#define emit_and_r32_m32isd(e, dreg, index, scale, disp) emit_and_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2676
	2677	#define emit_and_m32abs_r32(e, addr, sreg) emit_and_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2678	#define emit_and_m32bd_r32(e, base, disp, sreg) emit_and_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
	2679	#define emit_and_m32isd_r32(e, index, scale, disp, sreg) emit_and_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	2680
	2681
	2682	/*------------------------------------------------------------------
	2683	emit_sub_r32_*
	2684	------------------------------------------------------------------*/
	2685
	2686	#define emit_sub_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 5, dreg, imm)
	2687	#define emit_sub_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 5, base, index, scale, disp, imm)
	2688	#define emit_sub_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 5, dreg, sreg)
	2689	#define emit_sub_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 5, dreg, base, index, scale, disp)
	2690	#define emit_sub_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 5, base, index, scale, disp, sreg)
	2691
	2692	#define emit_sub_m32abs_imm(e, addr, imm) emit_sub_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2693	#define emit_sub_m32bd_imm(e, base, disp, imm) emit_sub_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2694	#define emit_sub_m32isd_imm(e, index, scale, disp, imm) emit_sub_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2695
	2696	#define emit_sub_r32_m32abs(e, dreg, addr) emit_sub_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2697	#define emit_sub_r32_m32bd(e, dreg, base, disp) emit_sub_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2698	#define emit_sub_r32_m32isd(e, dreg, index, scale, disp) emit_sub_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2699
	2700	#define emit_sub_m32abs_r32(e, addr, sreg) emit_sub_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2701	#define emit_sub_m32bd_r32(e, base, disp, sreg) emit_sub_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
	2702	#define emit_sub_m32isd_r32(e, index, scale, disp, sreg) emit_sub_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	2703
	2704
	2705	/*------------------------------------------------------------------
	2706	emit_xor_r32_*
	2707	------------------------------------------------------------------*/
	2708
	2709	#define emit_xor_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 6, dreg, imm)
	2710	#define emit_xor_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 6, base, index, scale, disp, imm)
	2711	#define emit_xor_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 6, dreg, sreg)
	2712	#define emit_xor_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 6, dreg, base, index, scale, disp)
	2713	#define emit_xor_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 6, base, index, scale, disp, sreg)
	2714
	2715	#define emit_xor_m32abs_imm(e, addr, imm) emit_xor_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2716	#define emit_xor_m32bd_imm(e, base, disp, imm) emit_xor_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2717	#define emit_xor_m32isd_imm(e, index, scale, disp, imm) emit_xor_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2718
	2719	#define emit_xor_r32_m32abs(e, dreg, addr) emit_xor_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2720	#define emit_xor_r32_m32bd(e, dreg, base, disp) emit_xor_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2721	#define emit_xor_r32_m32isd(e, dreg, index, scale, disp) emit_xor_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2722
	2723	#define emit_xor_m32abs_r32(e, addr, sreg) emit_xor_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2724	#define emit_xor_m32bd_r32(e, base, disp, sreg) emit_xor_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
	2725	#define emit_xor_m32isd_r32(e, index, scale, disp, sreg) emit_xor_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	2726
	2727
	2728	/*------------------------------------------------------------------
	2729	emit_cmp_r32_*
	2730	------------------------------------------------------------------*/
	2731
	2732	#define emit_cmp_r32_imm(e, dreg, imm) emit_arith_r32_imm(e, 7, dreg, imm)
	2733	#define emit_cmp_m32bisd_imm(e, base, index, scale, disp, imm) emit_arith_m32bisd_imm(e, 7, base, index, scale, disp, imm)
	2734	#define emit_cmp_r32_r32(e, dreg, sreg) emit_arith_r32_r32(e, 7, dreg, sreg)
	2735	#define emit_cmp_r32_m32bisd(e, dreg, base, index, scale, disp) emit_arith_r32_m32bisd(e, 7, dreg, base, index, scale, disp)
	2736	#define emit_cmp_m32bisd_r32(e, base, index, scale, disp, sreg) emit_arith_m32bisd_r32(e, 7, base, index, scale, disp, sreg)
	2737
	2738	#define emit_cmp_m32abs_imm(e, addr, imm) emit_cmp_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2739	#define emit_cmp_m32bd_imm(e, base, disp, imm) emit_cmp_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2740	#define emit_cmp_m32isd_imm(e, index, scale, disp, imm) emit_cmp_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2741
	2742	#define emit_cmp_r32_m32abs(e, dreg, addr) emit_cmp_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2743	#define emit_cmp_r32_m32bd(e, dreg, base, disp) emit_cmp_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2744	#define emit_cmp_r32_m32isd(e, dreg, index, scale, disp) emit_cmp_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2745
	2746	#define emit_cmp_m32abs_r32(e, addr, sreg) emit_cmp_m32bisd_r32(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2747	#define emit_cmp_m32bd_r32(e, base, disp, sreg) emit_cmp_m32bisd_r32(e, (base), REG_NONE, 1, (disp), sreg)
	2748	#define emit_cmp_m32isd_r32(e, index, scale, disp, sreg) emit_cmp_m32bisd_r32(e, REG_NONE, (index), (scale), (disp), sreg)
	2749
	2750
	2751
	2752	/***************************************************************************
	2753	64-BIT ARITHMETIC EMITTERS
	2754	***************************************************************************/
	2755
	2756	#ifdef PTR64
	2757	/*
	2758	Note that the following code relies on this:
	2759
	2760	00-05 or /0 = ADD
	2761	08-0d or /1 = OR
	2762	10-15 or /2 = ADC
	2763	18-1d or /3 = SBB
	2764	20-25 or /4 = AND
	2765	28-2d or /5 = SUB
	2766	30-35 or /6 = XOR
	2767	38-3d or /7 = CMP
	2768	*/
	2769
	2770	INLINE void emit_arith_r64_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT32 imm)
	2771	{
	2772	if ((INT8)imm == (INT32)imm)
	2773	{
	2774	emit_op_modrm_reg(emitptr, OP_G1_Ev_Ib, OP_64BIT, opindex, dreg);
	2775	emit_byte(emitptr, (INT8)imm);
	2776	}
	2777	else
	2778	{
	2779	emit_op_modrm_reg(emitptr, OP_G1_Ev_Iz, OP_64BIT, opindex, dreg);
	2780	emit_dword(emitptr, imm);
	2781	}
	2782	}
	2783
	2784	INLINE void emit_arith_m64bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT32 imm)
	2785	{
	2786	if ((INT8)imm == (INT32)imm)
	2787	{
	2788	emit_op_modrm_mem(emitptr, OP_G1_Ev_Ib, OP_64BIT, opindex, base, index, scale, disp);
	2789	emit_byte(emitptr, (INT8)imm);
	2790	}
	2791	else
	2792	{
	2793	emit_op_modrm_mem(emitptr, OP_G1_Ev_Iz, OP_64BIT, opindex, base, index, scale, disp);
	2794	emit_dword(emitptr, imm);
	2795	}
	2796	}
	2797
	2798	INLINE void emit_arith_r64_r64(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 sreg)
	2799	{
	2800	emit_op_modrm_reg(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_64BIT, dreg, sreg);
	2801	}
	2802
	2803	INLINE void emit_arith_r64_m64bisd(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	2804	{
	2805	emit_op_modrm_mem(emitptr, OP_ADD_Gv_Ev + 8 * opindex, OP_64BIT, dreg, base, index, scale, disp);
	2806	}
	2807
	2808	INLINE void emit_arith_m64bisd_r64(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 sreg)
	2809	{
	2810	emit_op_modrm_mem(emitptr, OP_ADD_Ev_Gv + 8 * opindex, OP_64BIT, sreg, base, index, scale, disp);
	2811	}
	2812
	2813
	2814	/*------------------------------------------------------------------
	2815	emit_add_r64_*
	2816	------------------------------------------------------------------*/
	2817
	2818	#define emit_add_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 0, dreg, imm)
	2819	#define emit_add_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 0, base, index, scale, disp, imm)
	2820	#define emit_add_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 0, dreg, sreg)
	2821	#define emit_add_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 0, dreg, base, index, scale, disp)
	2822	#define emit_add_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 0, base, index, scale, disp, sreg)
	2823
	2824	#define emit_add_m64abs_imm(e, addr, imm) emit_add_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2825	#define emit_add_m64bd_imm(e, base, disp, imm) emit_add_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2826	#define emit_add_m64isd_imm(e, index, scale, disp, imm) emit_add_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2827
	2828	#define emit_add_r64_m64abs(e, dreg, addr) emit_add_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2829	#define emit_add_r64_m64bd(e, dreg, base, disp) emit_add_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2830	#define emit_add_r64_m64isd(e, dreg, index, scale, disp) emit_add_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2831
	2832	#define emit_add_m64abs_r64(e, addr, sreg) emit_add_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2833	#define emit_add_m64bd_r64(e, base, disp, sreg) emit_add_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
	2834	#define emit_add_m64isd_r64(e, index, scale, disp, sreg) emit_add_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
	2835
	2836
	2837	/*------------------------------------------------------------------
	2838	emit_or_r64_*
	2839	------------------------------------------------------------------*/
	2840
	2841	#define emit_or_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 1, dreg, imm)
	2842	#define emit_or_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 1, base, index, scale, disp, imm)
	2843	#define emit_or_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 1, dreg, sreg)
	2844	#define emit_or_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 1, dreg, base, index, scale, disp)
	2845	#define emit_or_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 1, base, index, scale, disp, sreg)
	2846
	2847	#define emit_or_m64abs_imm(e, addr, imm) emit_or_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2848	#define emit_or_m64bd_imm(e, base, disp, imm) emit_or_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2849	#define emit_or_m64isd_imm(e, index, scale, disp, imm) emit_or_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2850
	2851	#define emit_or_r64_m64abs(e, dreg, addr) emit_or_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2852	#define emit_or_r64_m64bd(e, dreg, base, disp) emit_or_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2853	#define emit_or_r64_m64isd(e, dreg, index, scale, disp) emit_or_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2854
	2855	#define emit_or_m64abs_r64(e, addr, sreg) emit_or_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2856	#define emit_or_m64bd_r64(e, base, disp, sreg) emit_or_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
	2857	#define emit_or_m64isd_r64(e, index, scale, disp, sreg) emit_or_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
	2858
	2859
	2860	/*------------------------------------------------------------------
	2861	emit_adc_r64_*
	2862	------------------------------------------------------------------*/
	2863
	2864	#define emit_adc_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 2, dreg, imm)
	2865	#define emit_adc_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 2, base, index, scale, disp, imm)
	2866	#define emit_adc_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 2, dreg, sreg)
	2867	#define emit_adc_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 2, dreg, base, index, scale, disp)
	2868	#define emit_adc_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 2, base, index, scale, disp, sreg)
	2869
	2870	#define emit_adc_m64abs_imm(e, addr, imm) emit_adc_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2871	#define emit_adc_m64bd_imm(e, base, disp, imm) emit_adc_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2872	#define emit_adc_m64isd_imm(e, index, scale, disp, imm) emit_adc_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2873
	2874	#define emit_adc_r64_m64abs(e, dreg, addr) emit_adc_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2875	#define emit_adc_r64_m64bd(e, dreg, base, disp) emit_adc_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2876	#define emit_adc_r64_m64isd(e, dreg, index, scale, disp) emit_adc_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2877
	2878	#define emit_adc_m64abs_r64(e, addr, sreg) emit_adc_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2879	#define emit_adc_m64bd_r64(e, base, disp, sreg) emit_adc_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
	2880	#define emit_adc_m64isd_r64(e, index, scale, disp, sreg) emit_adc_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
	2881
	2882
	2883	/*------------------------------------------------------------------
	2884	emit_sbb_r64_*
	2885	------------------------------------------------------------------*/
	2886
	2887	#define emit_sbb_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 3, dreg, imm)
	2888	#define emit_sbb_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 3, base, index, scale, disp, imm)
	2889	#define emit_sbb_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 3, dreg, sreg)
	2890	#define emit_sbb_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 3, dreg, base, index, scale, disp)
	2891	#define emit_sbb_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 3, base, index, scale, disp, sreg)
	2892
	2893	#define emit_sbb_m64abs_imm(e, addr, imm) emit_sbb_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2894	#define emit_sbb_m64bd_imm(e, base, disp, imm) emit_sbb_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2895	#define emit_sbb_m64isd_imm(e, index, scale, disp, imm) emit_sbb_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2896
	2897	#define emit_sbb_r64_m64abs(e, dreg, addr) emit_sbb_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2898	#define emit_sbb_r64_m64bd(e, dreg, base, disp) emit_sbb_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2899	#define emit_sbb_r64_m64isd(e, dreg, index, scale, disp) emit_sbb_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2900
	2901	#define emit_sbb_m64abs_r64(e, addr, sreg) emit_sbb_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2902	#define emit_sbb_m64bd_r64(e, base, disp, sreg) emit_sbb_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
	2903	#define emit_sbb_m64isd_r64(e, index, scale, disp, sreg) emit_sbb_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
	2904
	2905
	2906	/*------------------------------------------------------------------
	2907	emit_and_r64_*
	2908	------------------------------------------------------------------*/
	2909
	2910	#define emit_and_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 4, dreg, imm)
	2911	#define emit_and_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 4, base, index, scale, disp, imm)
	2912	#define emit_and_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 4, dreg, sreg)
	2913	#define emit_and_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 4, dreg, base, index, scale, disp)
	2914	#define emit_and_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 4, base, index, scale, disp, sreg)
	2915
	2916	#define emit_and_m64abs_imm(e, addr, imm) emit_and_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2917	#define emit_and_m64bd_imm(e, base, disp, imm) emit_and_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2918	#define emit_and_m64isd_imm(e, index, scale, disp, imm) emit_and_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2919
	2920	#define emit_and_r64_m64abs(e, dreg, addr) emit_and_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2921	#define emit_and_r64_m64bd(e, dreg, base, disp) emit_and_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2922	#define emit_and_r64_m64isd(e, dreg, index, scale, disp) emit_and_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2923
	2924	#define emit_and_m64abs_r64(e, addr, sreg) emit_and_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2925	#define emit_and_m64bd_r64(e, base, disp, sreg) emit_and_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
	2926	#define emit_and_m64isd_r64(e, index, scale, disp, sreg) emit_and_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
	2927
	2928
	2929	/*------------------------------------------------------------------
	2930	emit_sub_r64_*
	2931	------------------------------------------------------------------*/
	2932
	2933	#define emit_sub_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 5, dreg, imm)
	2934	#define emit_sub_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 5, base, index, scale, disp, imm)
	2935	#define emit_sub_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 5, dreg, sreg)
	2936	#define emit_sub_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 5, dreg, base, index, scale, disp)
	2937	#define emit_sub_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 5, base, index, scale, disp, sreg)
	2938
	2939	#define emit_sub_m64abs_imm(e, addr, imm) emit_sub_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2940	#define emit_sub_m64bd_imm(e, base, disp, imm) emit_sub_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2941	#define emit_sub_m64isd_imm(e, index, scale, disp, imm) emit_sub_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2942
	2943	#define emit_sub_r64_m64abs(e, dreg, addr) emit_sub_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2944	#define emit_sub_r64_m64bd(e, dreg, base, disp) emit_sub_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2945	#define emit_sub_r64_m64isd(e, dreg, index, scale, disp) emit_sub_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2946
	2947	#define emit_sub_m64abs_r64(e, addr, sreg) emit_sub_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2948	#define emit_sub_m64bd_r64(e, base, disp, sreg) emit_sub_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
	2949	#define emit_sub_m64isd_r64(e, index, scale, disp, sreg) emit_sub_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
	2950
	2951
	2952	/*------------------------------------------------------------------
	2953	emit_xor_r64_*
	2954	------------------------------------------------------------------*/
	2955
	2956	#define emit_xor_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 6, dreg, imm)
	2957	#define emit_xor_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 6, base, index, scale, disp, imm)
	2958	#define emit_xor_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 6, dreg, sreg)
	2959	#define emit_xor_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 6, dreg, base, index, scale, disp)
	2960	#define emit_xor_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 6, base, index, scale, disp, sreg)
	2961
	2962	#define emit_xor_m64abs_imm(e, addr, imm) emit_xor_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2963	#define emit_xor_m64bd_imm(e, base, disp, imm) emit_xor_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2964	#define emit_xor_m64isd_imm(e, index, scale, disp, imm) emit_xor_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2965
	2966	#define emit_xor_r64_m64abs(e, dreg, addr) emit_xor_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2967	#define emit_xor_r64_m64bd(e, dreg, base, disp) emit_xor_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2968	#define emit_xor_r64_m64isd(e, dreg, index, scale, disp) emit_xor_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2969
	2970	#define emit_xor_m64abs_r64(e, addr, sreg) emit_xor_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2971	#define emit_xor_m64bd_r64(e, base, disp, sreg) emit_xor_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
	2972	#define emit_xor_m64isd_r64(e, index, scale, disp, sreg) emit_xor_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
	2973
	2974
	2975	/*------------------------------------------------------------------
	2976	emit_cmp_r64_*
	2977	------------------------------------------------------------------*/
	2978
	2979	#define emit_cmp_r64_imm(e, dreg, imm) emit_arith_r64_imm(e, 7, dreg, imm)
	2980	#define emit_cmp_m64bisd_imm(e, base, index, scale, disp, imm) emit_arith_m64bisd_imm(e, 7, base, index, scale, disp, imm)
	2981	#define emit_cmp_r64_r64(e, dreg, sreg) emit_arith_r64_r64(e, 7, dreg, sreg)
	2982	#define emit_cmp_r64_m64bisd(e, dreg, base, index, scale, disp) emit_arith_r64_m64bisd(e, 7, dreg, base, index, scale, disp)
	2983	#define emit_cmp_m64bisd_r64(e, base, index, scale, disp, sreg) emit_arith_m64bisd_r64(e, 7, base, index, scale, disp, sreg)
	2984
	2985	#define emit_cmp_m64abs_imm(e, addr, imm) emit_cmp_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	2986	#define emit_cmp_m64bd_imm(e, base, disp, imm) emit_cmp_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	2987	#define emit_cmp_m64isd_imm(e, index, scale, disp, imm) emit_cmp_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	2988
	2989	#define emit_cmp_r64_m64abs(e, dreg, addr) emit_cmp_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	2990	#define emit_cmp_r64_m64bd(e, dreg, base, disp) emit_cmp_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
	2991	#define emit_cmp_r64_m64isd(e, dreg, index, scale, disp) emit_cmp_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	2992
	2993	#define emit_cmp_m64abs_r64(e, addr, sreg) emit_cmp_m64bisd_r64(e, REG_NONE, REG_NONE, 1, (INT32)(addr), sreg)
	2994	#define emit_cmp_m64bd_r64(e, base, disp, sreg) emit_cmp_m64bisd_r64(e, (base), REG_NONE, 1, (disp), sreg)
	2995	#define emit_cmp_m64isd_r64(e, index, scale, disp, sreg) emit_cmp_m64bisd_r64(e, REG_NONE, (index), (scale), (disp), sreg)
	2996
	2997	#endif
	2998
	2999
	3000
	3001	/***************************************************************************
	3002	8-BIT SHIFT EMITTERS
	3003	***************************************************************************/
	3004
	3005	/*
	3006	Note that the following code relies on this:
	3007
	3008	/0 = ROL
	3009	/1 = ROR
	3010	/2 = RCL
	3011	/3 = RCR
	3012	/4 = SHL
	3013	/5 = SHR
	3014	/7 = SAR
	3015	*/
	3016
	3017	/*------------------------------------------------------------------
	3018	emit_shift_r8_*
	3019	------------------------------------------------------------------*/
	3020
	3021	INLINE void emit_shift_r8_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
	3022	{
	3023	if (imm == 1)
	3024	emit_op_modrm_reg(emitptr, OP_G2_Eb_1, OP_32BIT, opindex, dreg);
	3025	else
	3026	{
	3027	emit_op_modrm_reg(emitptr, OP_G2_Eb_Ib, OP_32BIT, opindex, dreg);
	3028	emit_byte(emitptr, imm);
	3029	}
	3030	}
	3031
	3032	INLINE void emit_shift_m8bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
	3033	{
	3034	if (imm == 1)
	3035	emit_op_modrm_mem(emitptr, OP_G2_Eb_1, OP_32BIT, opindex, base, index, scale, disp);
	3036	else
	3037	{
	3038	emit_op_modrm_mem(emitptr, OP_G2_Eb_Ib, OP_32BIT, opindex, base, index, scale, disp);
	3039	emit_byte(emitptr, imm);
	3040	}
	3041	}
	3042
	3043	INLINE void emit_shift_r8_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
	3044	{
	3045	emit_op_modrm_reg(emitptr, OP_G2_Eb_CL, OP_32BIT, opindex, dreg);
	3046	}
	3047
	3048	INLINE void emit_shift_m8bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	3049	{
	3050	emit_op_modrm_mem(emitptr, OP_G2_Eb_CL, OP_32BIT, opindex, base, index, scale, disp);
	3051	}
	3052
	3053
	3054	/*------------------------------------------------------------------
	3055	emit_rol_r8_*
	3056	------------------------------------------------------------------*/
	3057
	3058	#define emit_rol_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 0, dreg, imm)
	3059	#define emit_rol_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 0, base, index, scale, disp, imm)
	3060	#define emit_rol_r8_cl(e, dreg) emit_shift_r8_cl(e, 0, dreg)
	3061	#define emit_rol_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 0, base, index, scale, disp)
	3062
	3063	#define emit_rol_m8abs_imm(e, addr, imm) emit_rol_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3064	#define emit_rol_m8bd_imm(e, base, disp, imm) emit_rol_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3065	#define emit_rol_m8isd_imm(e, index, scale, disp, imm) emit_rol_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3066
	3067	#define emit_rol_m8abs_cl(e, addr) emit_rol_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3068	#define emit_rol_m8bd_cl(e, base, disp) emit_rol_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
	3069	#define emit_rol_m8isd_cl(e, index, scale, disp) emit_rol_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3070
	3071
	3072	/*------------------------------------------------------------------
	3073	emit_ror_r8_*
	3074	------------------------------------------------------------------*/
	3075
	3076	#define emit_ror_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 1, dreg, imm)
	3077	#define emit_ror_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 1, base, index, scale, disp, imm)
	3078	#define emit_ror_r8_cl(e, dreg) emit_shift_r8_cl(e, 1, dreg)
	3079	#define emit_ror_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 1, base, index, scale, disp)
	3080
	3081	#define emit_ror_m8abs_imm(e, addr, imm) emit_ror_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3082	#define emit_ror_m8bd_imm(e, base, disp, imm) emit_ror_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3083	#define emit_ror_m8isd_imm(e, index, scale, disp, imm) emit_ror_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3084
	3085	#define emit_ror_m8abs_cl(e, addr) emit_ror_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3086	#define emit_ror_m8bd_cl(e, base, disp) emit_ror_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
	3087	#define emit_ror_m8isd_cl(e, index, scale, disp) emit_ror_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3088
	3089
	3090	/*------------------------------------------------------------------
	3091	emit_rcl_r8_*
	3092	------------------------------------------------------------------*/
	3093
	3094	#define emit_rcl_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 2, dreg, imm)
	3095	#define emit_rcl_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 2, base, index, scale, disp, imm)
	3096	#define emit_rcl_r8_cl(e, dreg) emit_shift_r8_cl(e, 2, dreg)
	3097	#define emit_rcl_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 2, base, index, scale, disp)
	3098
	3099	#define emit_rcl_m8abs_imm(e, addr, imm) emit_rcl_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3100	#define emit_rcl_m8bd_imm(e, base, disp, imm) emit_rcl_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3101	#define emit_rcl_m8isd_imm(e, index, scale, disp, imm) emit_rcl_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3102
	3103	#define emit_rcl_m8abs_cl(e, addr) emit_rcl_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3104	#define emit_rcl_m8bd_cl(e, base, disp) emit_rcl_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
	3105	#define emit_rcl_m8isd_cl(e, index, scale, disp) emit_rcl_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3106
	3107
	3108	/*------------------------------------------------------------------
	3109	emit_rcr_r8_*
	3110	------------------------------------------------------------------*/
	3111
	3112	#define emit_rcr_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 3, dreg, imm)
	3113	#define emit_rcr_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 3, base, index, scale, disp, imm)
	3114	#define emit_rcr_r8_cl(e, dreg) emit_shift_r8_cl(e, 3, dreg)
	3115	#define emit_rcr_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 3, base, index, scale, disp)
	3116
	3117	#define emit_rcr_m8abs_imm(e, addr, imm) emit_rcr_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3118	#define emit_rcr_m8bd_imm(e, base, disp, imm) emit_rcr_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3119	#define emit_rcr_m8isd_imm(e, index, scale, disp, imm) emit_rcr_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3120
	3121	#define emit_rcr_m8abs_cl(e, addr) emit_rcr_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3122	#define emit_rcr_m8bd_cl(e, base, disp) emit_rcr_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
	3123	#define emit_rcr_m8isd_cl(e, index, scale, disp) emit_rcr_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3124
	3125
	3126	/*------------------------------------------------------------------
	3127	emit_shl_r8_*
	3128	------------------------------------------------------------------*/
	3129
	3130	#define emit_shl_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 4, dreg, imm)
	3131	#define emit_shl_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 4, base, index, scale, disp, imm)
	3132	#define emit_shl_r8_cl(e, dreg) emit_shift_r8_cl(e, 4, dreg)
	3133	#define emit_shl_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 4, base, index, scale, disp)
	3134
	3135	#define emit_shl_m8abs_imm(e, addr, imm) emit_shl_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3136	#define emit_shl_m8bd_imm(e, base, disp, imm) emit_shl_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3137	#define emit_shl_m8isd_imm(e, index, scale, disp, imm) emit_shl_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3138
	3139	#define emit_shl_m8abs_cl(e, addr) emit_shl_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3140	#define emit_shl_m8bd_cl(e, base, disp) emit_shl_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
	3141	#define emit_shl_m8isd_cl(e, index, scale, disp) emit_shl_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3142
	3143
	3144	/*------------------------------------------------------------------
	3145	emit_shr_r8_*
	3146	------------------------------------------------------------------*/
	3147
	3148	#define emit_shr_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 5, dreg, imm)
	3149	#define emit_shr_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 5, base, index, scale, disp, imm)
	3150	#define emit_shr_r8_cl(e, dreg) emit_shift_r8_cl(e, 5, dreg)
	3151	#define emit_shr_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 5, base, index, scale, disp)
	3152
	3153	#define emit_shr_m8abs_imm(e, addr, imm) emit_shr_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3154	#define emit_shr_m8bd_imm(e, base, disp, imm) emit_shr_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3155	#define emit_shr_m8isd_imm(e, index, scale, disp, imm) emit_shr_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3156
	3157	#define emit_shr_m8abs_cl(e, addr) emit_shr_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3158	#define emit_shr_m8bd_cl(e, base, disp) emit_shr_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
	3159	#define emit_shr_m8isd_cl(e, index, scale, disp) emit_shr_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3160
	3161
	3162	/*------------------------------------------------------------------
	3163	emit_sar_r8_*
	3164	------------------------------------------------------------------*/
	3165
	3166	#define emit_sar_r8_imm(e, dreg, imm) emit_shift_r8_imm(e, 7, dreg, imm)
	3167	#define emit_sar_m8bisd_imm(e, base, index, scale, disp, imm) emit_shift_m8bisd_imm(e, 7, base, index, scale, disp, imm)
	3168	#define emit_sar_r8_cl(e, dreg) emit_shift_r8_cl(e, 7, dreg)
	3169	#define emit_sar_m8bisd_cl(e, base, index, scale, disp) emit_shift_m8bisd_cl(e, 7, base, index, scale, disp)
	3170
	3171	#define emit_sar_m8abs_imm(e, addr, imm) emit_sar_m8bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3172	#define emit_sar_m8bd_imm(e, base, disp, imm) emit_sar_m8bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3173	#define emit_sar_m8isd_imm(e, index, scale, disp, imm) emit_sar_m8bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3174
	3175	#define emit_sar_m8abs_cl(e, addr) emit_sar_m8bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3176	#define emit_sar_m8bd_cl(e, base, disp) emit_sar_m8bisd_cl(e, (base), REG_NONE, 1, (disp))
	3177	#define emit_sar_m8isd_cl(e, index, scale, disp) emit_sar_m8bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3178
	3179
	3180
	3181	/***************************************************************************
	3182	16-BIT SHIFT EMITTERS
	3183	***************************************************************************/
	3184
	3185	/*
	3186	Note that the following code relies on this:
	3187
	3188	/0 = ROL
	3189	/1 = ROR
	3190	/2 = RCL
	3191	/3 = RCR
	3192	/4 = SHL
	3193	/5 = SHR
	3194	/7 = SAR
	3195	*/
	3196
	3197	/*------------------------------------------------------------------
	3198	emit_shift_r16_*
	3199	------------------------------------------------------------------*/
	3200
	3201	INLINE void emit_shift_r16_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
	3202	{
	3203	emit_byte(emitptr, PREFIX_OPSIZE);
	3204	if (imm == 1)
	3205	emit_op_modrm_reg(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, dreg);
	3206	else
	3207	{
	3208	emit_op_modrm_reg(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, dreg);
	3209	emit_byte(emitptr, imm);
	3210	}
	3211	}
	3212
	3213	INLINE void emit_shift_m16bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
	3214	{
	3215	emit_byte(emitptr, PREFIX_OPSIZE);
	3216	if (imm == 1)
	3217	emit_op_modrm_mem(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, base, index, scale, disp);
	3218	else
	3219	{
	3220	emit_op_modrm_mem(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
	3221	emit_byte(emitptr, imm);
	3222	}
	3223	}
	3224
	3225	INLINE void emit_shift_r16_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
	3226	{
	3227	emit_byte(emitptr, PREFIX_OPSIZE);
	3228	emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, dreg);
	3229	}
	3230
	3231	INLINE void emit_shift_m16bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	3232	{
	3233	emit_byte(emitptr, PREFIX_OPSIZE);
	3234	emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, base, index, scale, disp);
	3235	}
	3236
	3237
	3238	/*------------------------------------------------------------------
	3239	emit_rol_r16_*
	3240	------------------------------------------------------------------*/
	3241
	3242	#define emit_rol_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 0, dreg, imm)
	3243	#define emit_rol_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 0, base, index, scale, disp, imm)
	3244	#define emit_rol_r16_cl(e, dreg) emit_shift_r16_cl(e, 0, dreg)
	3245	#define emit_rol_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 0, base, index, scale, disp)
	3246
	3247	#define emit_rol_m16abs_imm(e, addr, imm) emit_rol_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3248	#define emit_rol_m16bd_imm(e, base, disp, imm) emit_rol_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3249	#define emit_rol_m16isd_imm(e, index, scale, disp, imm) emit_rol_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3250
	3251	#define emit_rol_m16abs_cl(e, addr) emit_rol_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3252	#define emit_rol_m16bd_cl(e, base, disp) emit_rol_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
	3253	#define emit_rol_m16isd_cl(e, index, scale, disp) emit_rol_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3254
	3255
	3256	/*------------------------------------------------------------------
	3257	emit_ror_r16_*
	3258	------------------------------------------------------------------*/
	3259
	3260	#define emit_ror_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 1, dreg, imm)
	3261	#define emit_ror_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 1, base, index, scale, disp, imm)
	3262	#define emit_ror_r16_cl(e, dreg) emit_shift_r16_cl(e, 1, dreg)
	3263	#define emit_ror_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 1, base, index, scale, disp)
	3264
	3265	#define emit_ror_m16abs_imm(e, addr, imm) emit_ror_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3266	#define emit_ror_m16bd_imm(e, base, disp, imm) emit_ror_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3267	#define emit_ror_m16isd_imm(e, index, scale, disp, imm) emit_ror_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3268
	3269	#define emit_ror_m16abs_cl(e, addr) emit_ror_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3270	#define emit_ror_m16bd_cl(e, base, disp) emit_ror_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
	3271	#define emit_ror_m16isd_cl(e, index, scale, disp) emit_ror_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3272
	3273
	3274	/*------------------------------------------------------------------
	3275	emit_rcl_r16_*
	3276	------------------------------------------------------------------*/
	3277
	3278	#define emit_rcl_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 2, dreg, imm)
	3279	#define emit_rcl_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 2, base, index, scale, disp, imm)
	3280	#define emit_rcl_r16_cl(e, dreg) emit_shift_r16_cl(e, 2, dreg)
	3281	#define emit_rcl_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 2, base, index, scale, disp)
	3282
	3283	#define emit_rcl_m16abs_imm(e, addr, imm) emit_rcl_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3284	#define emit_rcl_m16bd_imm(e, base, disp, imm) emit_rcl_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3285	#define emit_rcl_m16isd_imm(e, index, scale, disp, imm) emit_rcl_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3286
	3287	#define emit_rcl_m16abs_cl(e, addr) emit_rcl_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3288	#define emit_rcl_m16bd_cl(e, base, disp) emit_rcl_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
	3289	#define emit_rcl_m16isd_cl(e, index, scale, disp) emit_rcl_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3290
	3291
	3292	/*------------------------------------------------------------------
	3293	emit_rcr_r16_*
	3294	------------------------------------------------------------------*/
	3295
	3296	#define emit_rcr_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 3, dreg, imm)
	3297	#define emit_rcr_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 31, base, index, scale, disp, imm)
	3298	#define emit_rcr_r16_cl(e, dreg) emit_shift_r16_cl(e, 3, dreg)
	3299	#define emit_rcr_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 3, base, index, scale, disp)
	3300
	3301	#define emit_rcr_m16abs_imm(e, addr, imm) emit_rcr_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3302	#define emit_rcr_m16bd_imm(e, base, disp, imm) emit_rcr_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3303	#define emit_rcr_m16isd_imm(e, index, scale, disp, imm) emit_rcr_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3304
	3305	#define emit_rcr_m16abs_cl(e, addr) emit_rcr_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3306	#define emit_rcr_m16bd_cl(e, base, disp) emit_rcr_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
	3307	#define emit_rcr_m16isd_cl(e, index, scale, disp) emit_rcr_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3308
	3309
	3310	/*------------------------------------------------------------------
	3311	emit_shl_r16_*
	3312	------------------------------------------------------------------*/
	3313
	3314	#define emit_shl_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 4, dreg, imm)
	3315	#define emit_shl_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 4, base, index, scale, disp, imm)
	3316	#define emit_shl_r16_cl(e, dreg) emit_shift_r16_cl(e, 4, dreg)
	3317	#define emit_shl_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 4, base, index, scale, disp)
	3318
	3319	#define emit_shl_m16abs_imm(e, addr, imm) emit_shl_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3320	#define emit_shl_m16bd_imm(e, base, disp, imm) emit_shl_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3321	#define emit_shl_m16isd_imm(e, index, scale, disp, imm) emit_shl_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3322
	3323	#define emit_shl_m16abs_cl(e, addr) emit_shl_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3324	#define emit_shl_m16bd_cl(e, base, disp) emit_shl_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
	3325	#define emit_shl_m16isd_cl(e, index, scale, disp) emit_shl_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3326
	3327
	3328	/*------------------------------------------------------------------
	3329	emit_shr_r16_*
	3330	------------------------------------------------------------------*/
	3331
	3332	#define emit_shr_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 5, dreg, imm)
	3333	#define emit_shr_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 5, base, index, scale, disp, imm)
	3334	#define emit_shr_r16_cl(e, dreg) emit_shift_r16_cl(e, 5, dreg)
	3335	#define emit_shr_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 5, base, index, scale, disp)
	3336
	3337	#define emit_shr_m16abs_imm(e, addr, imm) emit_shr_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3338	#define emit_shr_m16bd_imm(e, base, disp, imm) emit_shr_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3339	#define emit_shr_m16isd_imm(e, index, scale, disp, imm) emit_shr_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3340
	3341	#define emit_shr_m16abs_cl(e, addr) emit_shr_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3342	#define emit_shr_m16bd_cl(e, base, disp) emit_shr_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
	3343	#define emit_shr_m16isd_cl(e, index, scale, disp) emit_shr_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3344
	3345
	3346	/*------------------------------------------------------------------
	3347	emit_sar_r16_*
	3348	------------------------------------------------------------------*/
	3349
	3350	#define emit_sar_r16_imm(e, dreg, imm) emit_shift_r16_imm(e, 7, dreg, imm)
	3351	#define emit_sar_m16bisd_imm(e, base, index, scale, disp, imm) emit_shift_m16bisd_imm(e, 7, base, index, scale, disp, imm)
	3352	#define emit_sar_r16_cl(e, dreg) emit_shift_r16_cl(e, 7, dreg)
	3353	#define emit_sar_m16bisd_cl(e, base, index, scale, disp) emit_shift_m16bisd_cl(e, 7, base, index, scale, disp)
	3354
	3355	#define emit_sar_m16abs_imm(e, addr, imm) emit_sar_m16bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3356	#define emit_sar_m16bd_imm(e, base, disp, imm) emit_sar_m16bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3357	#define emit_sar_m16isd_imm(e, index, scale, disp, imm) emit_sar_m16bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3358
	3359	#define emit_sar_m16abs_cl(e, addr) emit_sar_m16bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3360	#define emit_sar_m16bd_cl(e, base, disp) emit_sar_m16bisd_cl(e, (base), REG_NONE, 1, (disp))
	3361	#define emit_sar_m16isd_cl(e, index, scale, disp) emit_sar_m16bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3362
	3363
	3364
	3365	/***************************************************************************
	3366	32-BIT SHIFT EMITTERS
	3367	***************************************************************************/
	3368
	3369	/*
	3370	Note that the following code relies on this:
	3371
	3372	/0 = ROL
	3373	/1 = ROR
	3374	/2 = RCL
	3375	/3 = RCR
	3376	/4 = SHL
	3377	/5 = SHR
	3378	/7 = SAR
	3379	*/
	3380
	3381	/*------------------------------------------------------------------
	3382	emit_shift_r32_*
	3383	------------------------------------------------------------------*/
	3384
	3385	INLINE void emit_shift_r32_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
	3386	{
	3387	if (imm == 1)
	3388	emit_op_modrm_reg(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, dreg);
	3389	else
	3390	{
	3391	emit_op_modrm_reg(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, dreg);
	3392	emit_byte(emitptr, imm);
	3393	}
	3394	}
	3395
	3396	INLINE void emit_shift_m32bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
	3397	{
	3398	if (imm == 1)
	3399	emit_op_modrm_mem(emitptr, OP_G2_Ev_1, OP_32BIT, opindex, base, index, scale, disp);
	3400	else
	3401	{
	3402	emit_op_modrm_mem(emitptr, OP_G2_Ev_Ib, OP_32BIT, opindex, base, index, scale, disp);
	3403	emit_byte(emitptr, imm);
	3404	}
	3405	}
	3406
	3407	INLINE void emit_shift_r32_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
	3408	{
	3409	emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, dreg);
	3410	}
	3411
	3412	INLINE void emit_shift_m32bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	3413	{
	3414	emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_32BIT, opindex, base, index, scale, disp);
	3415	}
	3416
	3417
	3418	/*------------------------------------------------------------------
	3419	emit_rol_r32_*
	3420	------------------------------------------------------------------*/
	3421
	3422	#define emit_rol_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 0, dreg, imm)
	3423	#define emit_rol_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 0, base, index, scale, disp, imm)
	3424	#define emit_rol_r32_cl(e, dreg) emit_shift_r32_cl(e, 0, dreg)
	3425	#define emit_rol_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 0, base, index, scale, disp)
	3426
	3427	#define emit_rol_m32abs_imm(e, addr, imm) emit_rol_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3428	#define emit_rol_m32bd_imm(e, base, disp, imm) emit_rol_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3429	#define emit_rol_m32isd_imm(e, index, scale, disp, imm) emit_rol_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3430
	3431	#define emit_rol_m32abs_cl(e, addr) emit_rol_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3432	#define emit_rol_m32bd_cl(e, base, disp) emit_rol_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
	3433	#define emit_rol_m32isd_cl(e, index, scale, disp) emit_rol_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3434
	3435
	3436	/*------------------------------------------------------------------
	3437	emit_ror_r32_*
	3438	------------------------------------------------------------------*/
	3439
	3440	#define emit_ror_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 1, dreg, imm)
	3441	#define emit_ror_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 1, base, index, scale, disp, imm)
	3442	#define emit_ror_r32_cl(e, dreg) emit_shift_r32_cl(e, 1, dreg)
	3443	#define emit_ror_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 1, base, index, scale, disp)
	3444
	3445	#define emit_ror_m32abs_imm(e, addr, imm) emit_ror_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3446	#define emit_ror_m32bd_imm(e, base, disp, imm) emit_ror_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3447	#define emit_ror_m32isd_imm(e, index, scale, disp, imm) emit_ror_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3448
	3449	#define emit_ror_m32abs_cl(e, addr) emit_ror_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3450	#define emit_ror_m32bd_cl(e, base, disp) emit_ror_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
	3451	#define emit_ror_m32isd_cl(e, index, scale, disp) emit_ror_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3452
	3453
	3454	/*------------------------------------------------------------------
	3455	emit_rcl_r32_*
	3456	------------------------------------------------------------------*/
	3457
	3458	#define emit_rcl_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 2, dreg, imm)
	3459	#define emit_rcl_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 2, base, index, scale, disp, imm)
	3460	#define emit_rcl_r32_cl(e, dreg) emit_shift_r32_cl(e, 2, dreg)
	3461	#define emit_rcl_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 2, base, index, scale, disp)
	3462
	3463	#define emit_rcl_m32abs_imm(e, addr, imm) emit_rcl_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3464	#define emit_rcl_m32bd_imm(e, base, disp, imm) emit_rcl_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3465	#define emit_rcl_m32isd_imm(e, index, scale, disp, imm) emit_rcl_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3466
	3467	#define emit_rcl_m32abs_cl(e, addr) emit_rcl_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3468	#define emit_rcl_m32bd_cl(e, base, disp) emit_rcl_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
	3469	#define emit_rcl_m32isd_cl(e, index, scale, disp) emit_rcl_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3470
	3471
	3472	/*------------------------------------------------------------------
	3473	emit_rcr_r32_*
	3474	------------------------------------------------------------------*/
	3475
	3476	#define emit_rcr_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 3, dreg, imm)
	3477	#define emit_rcr_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 3, base, index, scale, disp, imm)
	3478	#define emit_rcr_r32_cl(e, dreg) emit_shift_r32_cl(e, 3, dreg)
	3479	#define emit_rcr_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 3, base, index, scale, disp)
	3480
	3481	#define emit_rcr_m32abs_imm(e, addr, imm) emit_rcr_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3482	#define emit_rcr_m32bd_imm(e, base, disp, imm) emit_rcr_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3483	#define emit_rcr_m32isd_imm(e, index, scale, disp, imm) emit_rcr_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3484
	3485	#define emit_rcr_m32abs_cl(e, addr) emit_rcr_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3486	#define emit_rcr_m32bd_cl(e, base, disp) emit_rcr_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
	3487	#define emit_rcr_m32isd_cl(e, index, scale, disp) emit_rcr_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3488
	3489
	3490	/*------------------------------------------------------------------
	3491	emit_shl_r32_*
	3492	------------------------------------------------------------------*/
	3493
	3494	#define emit_shl_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 4, dreg, imm)
	3495	#define emit_shl_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 4, base, index, scale, disp, imm)
	3496	#define emit_shl_r32_cl(e, dreg) emit_shift_r32_cl(e, 4, dreg)
	3497	#define emit_shl_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 4, base, index, scale, disp)
	3498
	3499	#define emit_shl_m32abs_imm(e, addr, imm) emit_shl_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3500	#define emit_shl_m32bd_imm(e, base, disp, imm) emit_shl_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3501	#define emit_shl_m32isd_imm(e, index, scale, disp, imm) emit_shl_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3502
	3503	#define emit_shl_m32abs_cl(e, addr) emit_shl_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3504	#define emit_shl_m32bd_cl(e, base, disp) emit_shl_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
	3505	#define emit_shl_m32isd_cl(e, index, scale, disp) emit_shl_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3506
	3507
	3508	/*------------------------------------------------------------------
	3509	emit_shr_r32_*
	3510	------------------------------------------------------------------*/
	3511
	3512	#define emit_shr_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 5, dreg, imm)
	3513	#define emit_shr_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 5, base, index, scale, disp, imm)
	3514	#define emit_shr_r32_cl(e, dreg) emit_shift_r32_cl(e, 5, dreg)
	3515	#define emit_shr_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 5, base, index, scale, disp)
	3516
	3517	#define emit_shr_m32abs_imm(e, addr, imm) emit_shr_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3518	#define emit_shr_m32bd_imm(e, base, disp, imm) emit_shr_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3519	#define emit_shr_m32isd_imm(e, index, scale, disp, imm) emit_shr_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3520
	3521	#define emit_shr_m32abs_cl(e, addr) emit_shr_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3522	#define emit_shr_m32bd_cl(e, base, disp) emit_shr_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
	3523	#define emit_shr_m32isd_cl(e, index, scale, disp) emit_shr_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3524
	3525
	3526	/*------------------------------------------------------------------
	3527	emit_sar_r32_*
	3528	------------------------------------------------------------------*/
	3529
	3530	#define emit_sar_r32_imm(e, dreg, imm) emit_shift_r32_imm(e, 7, dreg, imm)
	3531	#define emit_sar_m32bisd_imm(e, base, index, scale, disp, imm) emit_shift_m32bisd_imm(e, 7, base, index, scale, disp, imm)
	3532	#define emit_sar_r32_cl(e, dreg) emit_shift_r32_cl(e, 7, dreg)
	3533	#define emit_sar_m32bisd_cl(e, base, index, scale, disp) emit_shift_m32bisd_cl(e, 7, base, index, scale, disp)
	3534
	3535	#define emit_sar_m32abs_imm(e, addr, imm) emit_sar_m32bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3536	#define emit_sar_m32bd_imm(e, base, disp, imm) emit_sar_m32bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3537	#define emit_sar_m32isd_imm(e, index, scale, disp, imm) emit_sar_m32bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3538
	3539	#define emit_sar_m32abs_cl(e, addr) emit_sar_m32bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3540	#define emit_sar_m32bd_cl(e, base, disp) emit_sar_m32bisd_cl(e, (base), REG_NONE, 1, (disp))
	3541	#define emit_sar_m32isd_cl(e, index, scale, disp) emit_sar_m32bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3542
	3543
	3544
	3545	/***************************************************************************
	3546	64-BIT SHIFT EMITTERS
	3547	***************************************************************************/
	3548
	3549	#ifdef PTR64
	3550	/*
	3551	Note that the following code relies on this:
	3552
	3553	/0 = ROL
	3554	/1 = ROR
	3555	/2 = RCL
	3556	/3 = RCR
	3557	/4 = SHL
	3558	/5 = SHR
	3559	/7 = SAR
	3560	*/
	3561
	3562	/*------------------------------------------------------------------
	3563	emit_shift_r64_*
	3564	------------------------------------------------------------------*/
	3565
	3566	INLINE void emit_shift_r64_imm(x86code **emitptr, UINT8 opindex, UINT8 dreg, UINT8 imm)
	3567	{
	3568	if (imm == 1)
	3569	emit_op_modrm_reg(emitptr, OP_G2_Ev_1, OP_64BIT, opindex, dreg);
	3570	else
	3571	{
	3572	emit_op_modrm_reg(emitptr, OP_G2_Ev_Ib, OP_64BIT, opindex, dreg);
	3573	emit_byte(emitptr, imm);
	3574	}
	3575	}
	3576
	3577	INLINE void emit_shift_m64bisd_imm(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp, UINT8 imm)
	3578	{
	3579	if (imm == 1)
	3580	emit_op_modrm_mem(emitptr, OP_G2_Ev_1, OP_64BIT, opindex, base, index, scale, disp);
	3581	else
	3582	{
	3583	emit_op_modrm_mem(emitptr, OP_G2_Ev_Ib, OP_64BIT, opindex, base, index, scale, disp);
	3584	emit_byte(emitptr, imm);
	3585	}
	3586	}
	3587
	3588	INLINE void emit_shift_r64_cl(x86code **emitptr, UINT8 opindex, UINT8 dreg)
	3589	{
	3590	emit_op_modrm_reg(emitptr, OP_G2_Ev_CL, OP_64BIT, opindex, dreg);
	3591	}
	3592
	3593	INLINE void emit_shift_m64bisd_cl(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	3594	{
	3595	emit_op_modrm_mem(emitptr, OP_G2_Ev_CL, OP_64BIT, opindex, base, index, scale, disp);
	3596	}
	3597
	3598
	3599	/*------------------------------------------------------------------
	3600	emit_rol_r64_*
	3601	------------------------------------------------------------------*/
	3602
	3603	#define emit_rol_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 0, dreg, imm)
	3604	#define emit_rol_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 0, base, index, scale, disp, imm)
	3605	#define emit_rol_r64_cl(e, dreg) emit_shift_r64_cl(e, 0, dreg)
	3606	#define emit_rol_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 0, base, index, scale, disp)
	3607
	3608	#define emit_rol_m64abs_imm(e, addr, imm) emit_rol_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3609	#define emit_rol_m64bd_imm(e, base, disp, imm) emit_rol_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3610	#define emit_rol_m64isd_imm(e, index, scale, disp, imm) emit_rol_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3611
	3612	#define emit_rol_m64abs_cl(e, addr) emit_rol_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3613	#define emit_rol_m64bd_cl(e, base, disp) emit_rol_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
	3614	#define emit_rol_m64isd_cl(e, index, scale, disp) emit_rol_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3615
	3616
	3617	/*------------------------------------------------------------------
	3618	emit_ror_r64_*
	3619	------------------------------------------------------------------*/
	3620
	3621	#define emit_ror_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 1, dreg, imm)
	3622	#define emit_ror_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 1, base, index, scale, disp, imm)
	3623	#define emit_ror_r64_cl(e, dreg) emit_shift_r64_cl(e, 1, dreg)
	3624	#define emit_ror_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 1, base, index, scale, disp)
	3625
	3626	#define emit_ror_m64abs_imm(e, addr, imm) emit_ror_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3627	#define emit_ror_m64bd_imm(e, base, disp, imm) emit_ror_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3628	#define emit_ror_m64isd_imm(e, index, scale, disp, imm) emit_ror_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3629
	3630	#define emit_ror_m64abs_cl(e, addr) emit_ror_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3631	#define emit_ror_m64bd_cl(e, base, disp) emit_ror_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
	3632	#define emit_ror_m64isd_cl(e, index, scale, disp) emit_ror_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3633
	3634
	3635	/*------------------------------------------------------------------
	3636	emit_rcl_r64_*
	3637	------------------------------------------------------------------*/
	3638
	3639	#define emit_rcl_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 2, dreg, imm)
	3640	#define emit_rcl_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 2, base, index, scale, disp, imm)
	3641	#define emit_rcl_r64_cl(e, dreg) emit_shift_r64_cl(e, 2, dreg)
	3642	#define emit_rcl_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 2, base, index, scale, disp)
	3643
	3644	#define emit_rcl_m64abs_imm(e, addr, imm) emit_rcl_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3645	#define emit_rcl_m64bd_imm(e, base, disp, imm) emit_rcl_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3646	#define emit_rcl_m64isd_imm(e, index, scale, disp, imm) emit_rcl_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3647
	3648	#define emit_rcl_m64abs_cl(e, addr) emit_rcl_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3649	#define emit_rcl_m64bd_cl(e, base, disp) emit_rcl_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
	3650	#define emit_rcl_m64isd_cl(e, index, scale, disp) emit_rcl_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3651
	3652
	3653	/*------------------------------------------------------------------
	3654	emit_rcr_r64_*
	3655	------------------------------------------------------------------*/
	3656
	3657	#define emit_rcr_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 3, dreg, imm)
	3658	#define emit_rcr_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 3, base, index, scale, disp, imm)
	3659	#define emit_rcr_r64_cl(e, dreg) emit_shift_r64_cl(e, 3, dreg)
	3660	#define emit_rcr_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 3, base, index, scale, disp)
	3661
	3662	#define emit_rcr_m64abs_imm(e, addr, imm) emit_rcr_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3663	#define emit_rcr_m64bd_imm(e, base, disp, imm) emit_rcr_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3664	#define emit_rcr_m64isd_imm(e, index, scale, disp, imm) emit_rcr_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3665
	3666	#define emit_rcr_m64abs_cl(e, addr) emit_rcr_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3667	#define emit_rcr_m64bd_cl(e, base, disp) emit_rcr_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
	3668	#define emit_rcr_m64isd_cl(e, index, scale, disp) emit_rcr_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3669
	3670
	3671	/*------------------------------------------------------------------
	3672	emit_shl_r64_*
	3673	------------------------------------------------------------------*/
	3674
	3675	#define emit_shl_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 4, dreg, imm)
	3676	#define emit_shl_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 4, base, index, scale, disp, imm)
	3677	#define emit_shl_r64_cl(e, dreg) emit_shift_r64_cl(e, 4, dreg)
	3678	#define emit_shl_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 4, base, index, scale, disp)
	3679
	3680	#define emit_shl_m64abs_imm(e, addr, imm) emit_shl_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3681	#define emit_shl_m64bd_imm(e, base, disp, imm) emit_shl_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3682	#define emit_shl_m64isd_imm(e, index, scale, disp, imm) emit_shl_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3683
	3684	#define emit_shl_m64abs_cl(e, addr) emit_shl_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3685	#define emit_shl_m64bd_cl(e, base, disp) emit_shl_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
	3686	#define emit_shl_m64isd_cl(e, index, scale, disp) emit_shl_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3687
	3688
	3689	/*------------------------------------------------------------------
	3690	emit_shr_r64_*
	3691	------------------------------------------------------------------*/
	3692
	3693	#define emit_shr_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 5, dreg, imm)
	3694	#define emit_shr_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 5, base, index, scale, disp, imm)
	3695	#define emit_shr_r64_cl(e, dreg) emit_shift_r64_cl(e, 5, dreg)
	3696	#define emit_shr_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 5, base, index, scale, disp)
	3697
	3698	#define emit_shr_m64abs_imm(e, addr, imm) emit_shr_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3699	#define emit_shr_m64bd_imm(e, base, disp, imm) emit_shr_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3700	#define emit_shr_m64isd_imm(e, index, scale, disp, imm) emit_shr_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3701
	3702	#define emit_shr_m64abs_cl(e, addr) emit_shr_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3703	#define emit_shr_m64bd_cl(e, base, disp) emit_shr_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
	3704	#define emit_shr_m64isd_cl(e, index, scale, disp) emit_shr_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3705
	3706
	3707	/*------------------------------------------------------------------
	3708	emit_sar_r64_*
	3709	------------------------------------------------------------------*/
	3710
	3711	#define emit_sar_r64_imm(e, dreg, imm) emit_shift_r64_imm(e, 7, dreg, imm)
	3712	#define emit_sar_m64bisd_imm(e, base, index, scale, disp, imm) emit_shift_m64bisd_imm(e, 7, base, index, scale, disp, imm)
	3713	#define emit_sar_r64_cl(e, dreg) emit_shift_r64_cl(e, 7, dreg)
	3714	#define emit_sar_m64bisd_cl(e, base, index, scale, disp) emit_shift_m64bisd_cl(e, 7, base, index, scale, disp)
	3715
	3716	#define emit_sar_m64abs_imm(e, addr, imm) emit_sar_m64bisd_imm(e, REG_NONE, REG_NONE, 1, (INT32)(addr), imm)
	3717	#define emit_sar_m64bd_imm(e, base, disp, imm) emit_sar_m64bisd_imm(e, (base), REG_NONE, 1, (disp), imm)
	3718	#define emit_sar_m64isd_imm(e, index, scale, disp, imm) emit_sar_m64bisd_imm(e, REG_NONE, (index), (scale), (disp), imm)
	3719
	3720	#define emit_sar_m64abs_cl(e, addr) emit_sar_m64bisd_cl(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3721	#define emit_sar_m64bd_cl(e, base, disp) emit_sar_m64bisd_cl(e, (base), REG_NONE, 1, (disp))
	3722	#define emit_sar_m64isd_cl(e, index, scale, disp) emit_sar_m64bisd_cl(e, REG_NONE, (index), (scale), (disp))
	3723
	3724	#endif
	3725
	3726
	3727
	3728	/***************************************************************************
	3729	8-BIT GROUP3 EMITTERS
	3730	***************************************************************************/
	3731
	3732	/*
	3733	Note that the following code relies on this:
	3734
	3735	/2 = NOT
	3736	/3 = NEG
	3737	/4 = MUL
	3738	/5 = IMUL
	3739	/6 = DIV
	3740	/7 = IDIV
	3741	*/
	3742
	3743	/*------------------------------------------------------------------
	3744	emit_group3_r8_*
	3745	------------------------------------------------------------------*/
	3746
	3747	INLINE void emit_group3_r8(x86code **emitptr, UINT8 opindex, UINT8 dreg)
	3748	{
	3749	emit_op_modrm_reg(emitptr, OP_G3_Eb, OP_32BIT, opindex, dreg);
	3750	}
	3751
	3752	INLINE void emit_group3_m8bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	3753	{
	3754	emit_op_modrm_mem(emitptr, OP_G3_Eb, OP_32BIT, opindex, base, index, scale, disp);
	3755	}
	3756
	3757
	3758	/*------------------------------------------------------------------
	3759	emit_not_r8_*
	3760	------------------------------------------------------------------*/
	3761
	3762	#define emit_not_r8(e, dreg) emit_group3_r8(e, 2, dreg)
	3763	#define emit_not_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 2, base, index, scale, disp)
	3764
	3765	#define emit_not_m8abs(e, addr) emit_not_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3766	#define emit_not_m8bd(e, base, disp) emit_not_m8bisd(e, (base), REG_NONE, 1, (disp))
	3767	#define emit_not_m8isd(e, index, scale, disp) emit_not_m8bisd(e, REG_NONE, (index), (scale), (disp))
	3768
	3769
	3770	/*------------------------------------------------------------------
	3771	emit_neg_r8_*
	3772	------------------------------------------------------------------*/
	3773
	3774	#define emit_neg_r8(e, dreg) emit_group3_r8(e, 3, dreg)
	3775	#define emit_neg_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 3, base, index, scale, disp)
	3776
	3777	#define emit_neg_m8abs(e, addr) emit_neg_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3778	#define emit_neg_m8bd(e, base, disp) emit_neg_m8bisd(e, (base), REG_NONE, 1, (disp))
	3779	#define emit_neg_m8isd(e, index, scale, disp) emit_neg_m8bisd(e, REG_NONE, (index), (scale), (disp))
	3780
	3781
	3782	/*------------------------------------------------------------------
	3783	emit_mul_r8_*
	3784	------------------------------------------------------------------*/
	3785
	3786	#define emit_mul_r8(e, dreg) emit_group3_r8(e, 4, dreg)
	3787	#define emit_mul_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 4, base, index, scale, disp)
	3788
	3789	#define emit_mul_m8abs(e, addr) emit_mul_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3790	#define emit_mul_m8bd(e, base, disp) emit_mul_m8bisd(e, (base), REG_NONE, 1, (disp))
	3791	#define emit_mul_m8isd(e, index, scale, disp) emit_mul_m8bisd(e, REG_NONE, (index), (scale), (disp))
	3792
	3793
	3794	/*------------------------------------------------------------------
	3795	emit_imul_r8_*
	3796	------------------------------------------------------------------*/
	3797
	3798	#define emit_imul_r8(e, dreg) emit_group3_r8(e, 5, dreg)
	3799	#define emit_imul_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 5, base, index, scale, disp)
	3800
	3801	#define emit_imul_m8abs(e, addr) emit_imul_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3802	#define emit_imul_m8bd(e, base, disp) emit_imul_m8bisd(e, (base), REG_NONE, 1, (disp))
	3803	#define emit_imul_m8isd(e, index, scale, disp) emit_imul_m8bisd(e, REG_NONE, (index), (scale), (disp))
	3804
	3805
	3806	/*------------------------------------------------------------------
	3807	emit_div_r8_*
	3808	------------------------------------------------------------------*/
	3809
	3810	#define emit_div_r8(e, dreg) emit_group3_r8(e, 6, dreg)
	3811	#define emit_div_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 6, base, index, scale, disp)
	3812
	3813	#define emit_div_m8abs(e, addr) emit_div_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3814	#define emit_div_m8bd(e, base, disp) emit_div_m8bisd(e, (base), REG_NONE, 1, (disp))
	3815	#define emit_div_m8isd(e, index, scale, disp) emit_div_m8bisd(e, REG_NONE, (index), (scale), (disp))
	3816
	3817
	3818	/*------------------------------------------------------------------
	3819	emit_idiv_r8_*
	3820	------------------------------------------------------------------*/
	3821
	3822	#define emit_idiv_r8(e, dreg) emit_group3_r8(e, 7, dreg)
	3823	#define emit_idiv_m8bisd(e, base, index, scale, disp) emit_group3_m8bisd(e, 7, base, index, scale, disp)
	3824
	3825	#define emit_idiv_m8abs(e, addr) emit_idiv_m8bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3826	#define emit_idiv_m8bd(e, base, disp) emit_idiv_m8bisd(e, (base), REG_NONE, 1, (disp))
	3827	#define emit_idiv_m8isd(e, index, scale, disp) emit_idiv_m8bisd(e, REG_NONE, (index), (scale), (disp))
	3828
	3829
	3830
	3831	/***************************************************************************
	3832	16-BIT GROUP3 EMITTERS
	3833	***************************************************************************/
	3834
	3835	/*
	3836	Note that the following code relies on this:
	3837
	3838	/0 = ROL
	3839	/1 = ROR
	3840	/2 = RCL
	3841	/3 = RCR
	3842	/4 = SHL
	3843	/5 = SHR
	3844	/7 = SAR
	3845	*/
	3846
	3847	/*------------------------------------------------------------------
	3848	emit_group3_r16_*
	3849	------------------------------------------------------------------*/
	3850
	3851	INLINE void emit_group3_r16(x86code **emitptr, UINT8 opindex, UINT8 dreg)
	3852	{
	3853	emit_byte(emitptr, PREFIX_OPSIZE);
	3854	emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, opindex, dreg);
	3855	}
	3856
	3857	INLINE void emit_group3_m16bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	3858	{
	3859	emit_byte(emitptr, PREFIX_OPSIZE);
	3860	emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, opindex, base, index, scale, disp);
	3861	}
	3862
	3863
	3864	/*------------------------------------------------------------------
	3865	emit_not_r16_*
	3866	------------------------------------------------------------------*/
	3867
	3868	#define emit_not_r16(e, dreg) emit_group3_r16(e, 2, dreg)
	3869	#define emit_not_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 2, base, index, scale, disp)
	3870
	3871	#define emit_not_m16abs(e, addr) emit_not_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3872	#define emit_not_m16bd(e, base, disp) emit_not_m16bisd(e, (base), REG_NONE, 1, (disp))
	3873	#define emit_not_m16isd(e, index, scale, disp) emit_not_m16bisd(e, REG_NONE, (index), (scale), (disp))
	3874
	3875
	3876	/*------------------------------------------------------------------
	3877	emit_neg_r16_*
	3878	------------------------------------------------------------------*/
	3879
	3880	#define emit_neg_r16(e, dreg) emit_group3_r16(e, 3, dreg)
	3881	#define emit_neg_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 3, base, index, scale, disp)
	3882
	3883	#define emit_neg_m16abs(e, addr) emit_neg_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3884	#define emit_neg_m16bd(e, base, disp) emit_neg_m16bisd(e, (base), REG_NONE, 1, (disp))
	3885	#define emit_neg_m16isd(e, index, scale, disp) emit_neg_m16bisd(e, REG_NONE, (index), (scale), (disp))
	3886
	3887
	3888	/*------------------------------------------------------------------
	3889	emit_mul_r16_*
	3890	------------------------------------------------------------------*/
	3891
	3892	#define emit_mul_r16(e, dreg) emit_group3_r16(e, 4, dreg)
	3893	#define emit_mul_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 4, base, index, scale, disp)
	3894
	3895	#define emit_mul_m16abs(e, addr) emit_mul_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3896	#define emit_mul_m16bd(e, base, disp) emit_mul_m16bisd(e, (base), REG_NONE, 1, (disp))
	3897	#define emit_mul_m16isd(e, index, scale, disp) emit_mul_m16bisd(e, REG_NONE, (index), (scale), (disp))
	3898
	3899
	3900	/*------------------------------------------------------------------
	3901	emit_imul_r16_*
	3902	------------------------------------------------------------------*/
	3903
	3904	#define emit_imul_r16(e, dreg) emit_group3_r16(e, 5, dreg)
	3905	#define emit_imul_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 5, base, index, scale, disp)
	3906
	3907	#define emit_imul_m16abs(e, addr) emit_imul_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3908	#define emit_imul_m16bd(e, base, disp) emit_imul_m16bisd(e, (base), REG_NONE, 1, (disp))
	3909	#define emit_imul_m16isd(e, index, scale, disp) emit_imul_m16bisd(e, REG_NONE, (index), (scale), (disp))
	3910
	3911
	3912	/*------------------------------------------------------------------
	3913	emit_div_r16_*
	3914	------------------------------------------------------------------*/
	3915
	3916	#define emit_div_r16(e, dreg) emit_group3_r16(e, 6, dreg)
	3917	#define emit_div_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 6, base, index, scale, disp)
	3918
	3919	#define emit_div_m16abs(e, addr) emit_div_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3920	#define emit_div_m16bd(e, base, disp) emit_div_m16bisd(e, (base), REG_NONE, 1, (disp))
	3921	#define emit_div_m16isd(e, index, scale, disp) emit_div_m16bisd(e, REG_NONE, (index), (scale), (disp))
	3922
	3923
	3924	/*------------------------------------------------------------------
	3925	emit_idiv_r16_*
	3926	------------------------------------------------------------------*/
	3927
	3928	#define emit_idiv_r16(e, dreg) emit_group3_r16(e, 7, dreg)
	3929	#define emit_idiv_m16bisd(e, base, index, scale, disp) emit_group3_m16bisd(e, 7, base, index, scale, disp)
	3930
	3931	#define emit_idiv_m16abs(e, addr) emit_idiv_m16bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3932	#define emit_idiv_m16bd(e, base, disp) emit_idiv_m16bisd(e, (base), REG_NONE, 1, (disp))
	3933	#define emit_idiv_m16isd(e, index, scale, disp) emit_idiv_m16bisd(e, REG_NONE, (index), (scale), (disp))
	3934
	3935
	3936
	3937	/***************************************************************************
	3938	32-BIT GROUP3 EMITTERS
	3939	***************************************************************************/
	3940
	3941	/*
	3942	Note that the following code relies on this:
	3943
	3944	/0 = ROL
	3945	/1 = ROR
	3946	/2 = RCL
	3947	/3 = RCR
	3948	/4 = SHL
	3949	/5 = SHR
	3950	/7 = SAR
	3951	*/
	3952
	3953	/*------------------------------------------------------------------
	3954	emit_group3_r32_*
	3955	------------------------------------------------------------------*/
	3956
	3957	INLINE void emit_group3_r32(x86code **emitptr, UINT8 opindex, UINT8 dreg)
	3958	{
	3959	emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_32BIT, opindex, dreg);
	3960	}
	3961
	3962	INLINE void emit_group3_m32bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	3963	{
	3964	emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_32BIT, opindex, base, index, scale, disp);
	3965	}
	3966
	3967
	3968	/*------------------------------------------------------------------
	3969	emit_not_r32_*
	3970	------------------------------------------------------------------*/
	3971
	3972	#define emit_not_r32(e, dreg) emit_group3_r32(e, 2, dreg)
	3973	#define emit_not_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 2, base, index, scale, disp)
	3974
	3975	#define emit_not_m32abs(e, addr) emit_not_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3976	#define emit_not_m32bd(e, base, disp) emit_not_m32bisd(e, (base), REG_NONE, 1, (disp))
	3977	#define emit_not_m32isd(e, index, scale, disp) emit_not_m32bisd(e, REG_NONE, (index), (scale), (disp))
	3978
	3979
	3980	/*------------------------------------------------------------------
	3981	emit_neg_r32_*
	3982	------------------------------------------------------------------*/
	3983
	3984	#define emit_neg_r32(e, dreg) emit_group3_r32(e, 3, dreg)
	3985	#define emit_neg_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 3, base, index, scale, disp)
	3986
	3987	#define emit_neg_m32abs(e, addr) emit_neg_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	3988	#define emit_neg_m32bd(e, base, disp) emit_neg_m32bisd(e, (base), REG_NONE, 1, (disp))
	3989	#define emit_neg_m32isd(e, index, scale, disp) emit_neg_m32bisd(e, REG_NONE, (index), (scale), (disp))
	3990
	3991
	3992	/*------------------------------------------------------------------
	3993	emit_mul_r32_*
	3994	------------------------------------------------------------------*/
	3995
	3996	#define emit_mul_r32(e, dreg) emit_group3_r32(e, 4, dreg)
	3997	#define emit_mul_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 4, base, index, scale, disp)
	3998
	3999	#define emit_mul_m32abs(e, addr) emit_mul_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4000	#define emit_mul_m32bd(e, base, disp) emit_mul_m32bisd(e, (base), REG_NONE, 1, (disp))
	4001	#define emit_mul_m32isd(e, index, scale, disp) emit_mul_m32bisd(e, REG_NONE, (index), (scale), (disp))
	4002
	4003
	4004	/*------------------------------------------------------------------
	4005	emit_imul_r32_*
	4006	------------------------------------------------------------------*/
	4007
	4008	#define emit_imul_r32(e, dreg) emit_group3_r32(e, 5, dreg)
	4009	#define emit_imul_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 5, base, index, scale, disp)
	4010
	4011	#define emit_imul_m32abs(e, addr) emit_imul_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4012	#define emit_imul_m32bd(e, base, disp) emit_imul_m32bisd(e, (base), REG_NONE, 1, (disp))
	4013	#define emit_imul_m32isd(e, index, scale, disp) emit_imul_m32bisd(e, REG_NONE, (index), (scale), (disp))
	4014
	4015
	4016	/*------------------------------------------------------------------
	4017	emit_div_r32_*
	4018	------------------------------------------------------------------*/
	4019
	4020	#define emit_div_r32(e, dreg) emit_group3_r32(e, 6, dreg)
	4021	#define emit_div_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 6, base, index, scale, disp)
	4022
	4023	#define emit_div_m32abs(e, addr) emit_div_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4024	#define emit_div_m32bd(e, base, disp) emit_div_m32bisd(e, (base), REG_NONE, 1, (disp))
	4025	#define emit_div_m32isd(e, index, scale, disp) emit_div_m32bisd(e, REG_NONE, (index), (scale), (disp))
	4026
	4027
	4028	/*------------------------------------------------------------------
	4029	emit_idiv_r32_*
	4030	------------------------------------------------------------------*/
	4031
	4032	#define emit_idiv_r32(e, dreg) emit_group3_r32(e, 7, dreg)
	4033	#define emit_idiv_m32bisd(e, base, index, scale, disp) emit_group3_m32bisd(e, 7, base, index, scale, disp)
	4034
	4035	#define emit_idiv_m32abs(e, addr) emit_idiv_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4036	#define emit_idiv_m32bd(e, base, disp) emit_idiv_m32bisd(e, (base), REG_NONE, 1, (disp))
	4037	#define emit_idiv_m32isd(e, index, scale, disp) emit_idiv_m32bisd(e, REG_NONE, (index), (scale), (disp))
	4038
	4039
	4040
	4041	/***************************************************************************
	4042	64-BIT GROUP3 EMITTERS
	4043	***************************************************************************/
	4044
	4045	#ifdef PTR64
	4046	/*
	4047	Note that the following code relies on this:
	4048
	4049	/0 = ROL
	4050	/1 = ROR
	4051	/2 = RCL
	4052	/3 = RCR
	4053	/4 = SHL
	4054	/5 = SHR
	4055	/7 = SAR
	4056	*/
	4057
	4058	/*------------------------------------------------------------------
	4059	emit_group3_r64_*
	4060	------------------------------------------------------------------*/
	4061
	4062	INLINE void emit_group3_r64(x86code **emitptr, UINT8 opindex, UINT8 dreg)
	4063	{
	4064	emit_op_modrm_reg(emitptr, OP_G3_Ev, OP_64BIT, opindex, dreg);
	4065	}
	4066
	4067	INLINE void emit_group3_m64bisd(x86code **emitptr, UINT8 opindex, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	4068	{
	4069	emit_op_modrm_mem(emitptr, OP_G3_Ev, OP_64BIT, opindex, base, index, scale, disp);
	4070	}
	4071
	4072
	4073	/*------------------------------------------------------------------
	4074	emit_not_r64_*
	4075	------------------------------------------------------------------*/
	4076
	4077	#define emit_not_r64(e, dreg) emit_group3_r64(e, 2, dreg)
	4078	#define emit_not_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 2, base, index, scale, disp)
	4079
	4080	#define emit_not_m64abs(e, addr) emit_not_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4081	#define emit_not_m64bd(e, base, disp) emit_not_m64bisd(e, (base), REG_NONE, 1, (disp))
	4082	#define emit_not_m64isd(e, index, scale, disp) emit_not_m64bisd(e, REG_NONE, (index), (scale), (disp))
	4083
	4084
	4085	/*------------------------------------------------------------------
	4086	emit_neg_r64_*
	4087	------------------------------------------------------------------*/
	4088
	4089	#define emit_neg_r64(e, dreg) emit_group3_r64(e, 3, dreg)
	4090	#define emit_neg_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 3, base, index, scale, disp)
	4091
	4092	#define emit_neg_m64abs(e, addr) emit_neg_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4093	#define emit_neg_m64bd(e, base, disp) emit_neg_m64bisd(e, (base), REG_NONE, 1, (disp))
	4094	#define emit_neg_m64isd(e, index, scale, disp) emit_neg_m64bisd(e, REG_NONE, (index), (scale), (disp))
	4095
	4096
	4097	/*------------------------------------------------------------------
	4098	emit_mul_r64_*
	4099	------------------------------------------------------------------*/
	4100
	4101	#define emit_mul_r64(e, dreg) emit_group3_r64(e, 4, dreg)
	4102	#define emit_mul_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 4, base, index, scale, disp)
	4103
	4104	#define emit_mul_m64abs(e, addr) emit_mul_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4105	#define emit_mul_m64bd(e, base, disp) emit_mul_m64bisd(e, (base), REG_NONE, 1, (disp))
	4106	#define emit_mul_m64isd(e, index, scale, disp) emit_mul_m64bisd(e, REG_NONE, (index), (scale), (disp))
	4107
	4108
	4109	/*------------------------------------------------------------------
	4110	emit_imul_r64_*
	4111	------------------------------------------------------------------*/
	4112
	4113	#define emit_imul_r64(e, dreg) emit_group3_r64(e, 5, dreg)
	4114	#define emit_imul_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 5, base, index, scale, disp)
	4115
	4116	#define emit_imul_m64abs(e, addr) emit_imul_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4117	#define emit_imul_m64bd(e, base, disp) emit_imul_m64bisd(e, (base), REG_NONE, 1, (disp))
	4118	#define emit_imul_m64isd(e, index, scale, disp) emit_imul_m64bisd(e, REG_NONE, (index), (scale), (disp))
	4119
	4120
	4121	/*------------------------------------------------------------------
	4122	emit_div_r64_*
	4123	------------------------------------------------------------------*/
	4124
	4125	#define emit_div_r64(e, dreg) emit_group3_r64(e, 6, dreg)
	4126	#define emit_div_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 6, base, index, scale, disp)
	4127
	4128	#define emit_div_m64abs(e, addr) emit_div_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4129	#define emit_div_m64bd(e, base, disp) emit_div_m64bisd(e, (base), REG_NONE, 1, (disp))
	4130	#define emit_div_m64isd(e, index, scale, disp) emit_div_m64bisd(e, REG_NONE, (index), (scale), (disp))
	4131
	4132
	4133	/*------------------------------------------------------------------
	4134	emit_idiv_r64_*
	4135	------------------------------------------------------------------*/
	4136
	4137	#define emit_idiv_r64(e, dreg) emit_group3_r64(e, 7, dreg)
	4138	#define emit_idiv_m64bisd(e, base, index, scale, disp) emit_group3_m64bisd(e, 7, base, index, scale, disp)
	4139
	4140	#define emit_idiv_m64abs(e, addr) emit_idiv_m64bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4141	#define emit_idiv_m64bd(e, base, disp) emit_idiv_m64bisd(e, (base), REG_NONE, 1, (disp))
	4142	#define emit_idiv_m64isd(e, index, scale, disp) emit_idiv_m64bisd(e, REG_NONE, (index), (scale), (disp))
	4143
	4144	#endif
	4145
	4146
	4147
	4148	/***************************************************************************
	4149	LEA EMITTERS
	4150	***************************************************************************/
	4151
	4152	/*------------------------------------------------------------------
	4153	emit_lea_r32_*
	4154	------------------------------------------------------------------*/
	4155
	4156	INLINE void emit_lea_r32_m32bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	4157	{
	4158	emit_op_modrm_mem(emitptr, OP_LEA_Gv_M, OP_32BIT, dreg, base, index, scale, disp);
	4159	}
	4160
	4161	#define emit_lea_r32_m32abs(e, dreg, addr) emit_lea_r32_m32bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4162	#define emit_lea_r32_m32bd(e, dreg, base, disp) emit_lea_r32_m32bisd(e, dreg, (base), REG_NONE, 1, (disp))
	4163	#define emit_lea_r32_m32isd(e, dreg, index, scale, disp) emit_lea_r32_m32bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	4164
	4165
	4166	/*------------------------------------------------------------------
	4167	emit_lea_r64_*
	4168	------------------------------------------------------------------*/
	4169
	4170	#ifdef PTR64
	4171	INLINE void emit_lea_r64_m64bisd(x86code **emitptr, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	4172	{
	4173	emit_op_modrm_mem(emitptr, OP_LEA_Gv_M, OP_64BIT, dreg, base, index, scale, disp);
	4174	}
	4175
	4176	#define emit_lea_r64_m64abs(e, dreg, addr) emit_lea_r64_m64bisd(e, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4177	#define emit_lea_r64_m64bd(e, dreg, base, disp) emit_lea_r64_m64bisd(e, dreg, (base), REG_NONE, 1, (disp))
	4178	#define emit_lea_r64_m64isd(e, dreg, index, scale, disp) emit_lea_r64_m64bisd(e, dreg, REG_NONE, (index), (scale), (disp))
	4179	#endif
	4180
	4181
	4182
	4183	/***************************************************************************
	4184	PUSH/POP EMITTERS
	4185	***************************************************************************/
	4186
	4187	/*------------------------------------------------------------------
	4188	emit_push_*
	4189	------------------------------------------------------------------*/
	4190
	4191	#ifndef PTR64
	4192	INLINE void emit_push_r32(x86code **emitptr, UINT8 reg)
	4193	{
	4194	emit_op(emitptr, OP_PUSH_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
	4195	}
	4196	#endif
	4197
	4198	#ifdef PTR64
	4199	INLINE void emit_push_r64(x86code **emitptr, UINT8 reg)
	4200	{
	4201	emit_op(emitptr, OP_PUSH_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
	4202	}
	4203	#endif
	4204
	4205
	4206	/*------------------------------------------------------------------
	4207	emit_pop_*
	4208	------------------------------------------------------------------*/
	4209
	4210	#ifndef PTR64
	4211	INLINE void emit_pop_r32(x86code **emitptr, UINT8 reg)
	4212	{
	4213	emit_op(emitptr, OP_POP_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
	4214	}
	4215	#endif
	4216
	4217	#ifdef PTR64
	4218	INLINE void emit_pop_r64(x86code **emitptr, UINT8 reg)
	4219	{
	4220	emit_op(emitptr, OP_POP_rAX + (reg & 7), OP_32BIT, 0, 0, reg);
	4221	}
	4222	#endif
	4223
	4224
	4225
	4226	/***************************************************************************
	4227	SET EMITTERS
	4228	***************************************************************************/
	4229
	4230	/*------------------------------------------------------------------
	4231	emit_setcc_*
	4232	------------------------------------------------------------------*/
	4233
	4234	INLINE void emit_setcc_r8(x86code **emitptr, UINT8 condition, UINT8 dreg)
	4235	{
	4236	emit_op_modrm_reg(emitptr, OP_SETCC_O_Eb + condition, OP_32BIT, 0, dreg);
	4237	}
	4238
	4239	INLINE void emit_setcc_m8bisd(x86code **emitptr, UINT8 condition, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	4240	{
	4241	emit_op_modrm_mem(emitptr, OP_SETCC_O_Eb + condition, OP_32BIT, 0, base, index, scale, disp);
	4242	}
	4243
	4244	#define emit_setcc_m8abs(e, cond, addr) emit_setcc_m8bisd(e, cond, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4245	#define emit_setcc_m8bd(e, cond, base, disp) emit_setcc_m8bisd(e, cond, (base), REG_NONE, 1, (disp))
	4246	#define emit_setcc_m8isd(e, cond, index, scale, disp) emit_setcc_m8bisd(e, cond, REG_NONE, (index), (scale), (disp))
	4247
	4248
	4249
	4250	/***************************************************************************
	4251	GROUP16 EMITTERS
	4252	***************************************************************************/
	4253
	4254	/*------------------------------------------------------------------
	4255	emit_ldmxcsr_*
	4256	------------------------------------------------------------------*/
	4257
	4258	INLINE void emit_ldmxcsr_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	4259	{
	4260	emit_op_modrm_mem(emitptr, OP_G16, OP_32BIT, 2, base, index, scale, disp);
	4261	}
	4262
	4263	#define emit_ldmxcsr_m32abs(e, addr) emit_ldmxcsr_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4264	#define emit_ldmxcsr_m32bd(e, base, disp) emit_ldmxcsr_m32bisd(e, (base), REG_NONE, 1, (disp))
	4265	#define emit_ldmxcsr_m32isd(e, index, scale, disp) emit_ldmxcsr_m32bisd(e, REG_NONE, (index), (scale), (disp))
	4266
	4267
	4268	/*------------------------------------------------------------------
	4269	emit_stmxcsr_*
	4270	------------------------------------------------------------------*/
	4271
	4272	INLINE void emit_stmxcsr_m32bisd(x86code **emitptr, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	4273	{
	4274	emit_op_modrm_mem(emitptr, OP_G16, OP_32BIT, 3, base, index, scale, disp);
	4275	}
	4276
	4277	#define emit_stmxcsr_m32abs(e, addr) emit_stmxcsr_m32bisd(e, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4278	#define emit_stmxcsr_m32bd(e, base, disp) emit_stmxcsr_m32bisd(e, (base), REG_NONE, 1, (disp))
	4279	#define emit_stmxcsr_m32isd(e, index, scale, disp) emit_stmxcsr_m32bisd(e, REG_NONE, (index), (scale), (disp))
	4280
	4281
	4282
	4283	/***************************************************************************
	4284	SSE EMITTERS
	4285	***************************************************************************/
	4286
	4287	INLINE void emit_sse_r128_r128(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 sreg)
	4288	{
	4289	emit_op_modrm_reg(emitptr, op, OP_32BIT, dreg, sreg);
	4290	}
	4291
	4292	INLINE void emit_sse_r128_mbisd(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	4293	{
	4294	emit_op_modrm_mem(emitptr, op, OP_32BIT, dreg, base, index, scale, disp);
	4295	}
	4296
	4297	INLINE void emit_sse_r128_r128_rex(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 sreg)
	4298	{
	4299	emit_op_modrm_reg(emitptr, op, OP_64BIT, dreg, sreg);
	4300	}
	4301
	4302	INLINE void emit_sse_r128_mbisd_rex(x86code **emitptr, UINT32 op, UINT8 dreg, UINT8 base, UINT8 index, UINT8 scale, INT32 disp)
	4303	{
	4304	emit_op_modrm_mem(emitptr, op, OP_64BIT, dreg, base, index, scale, disp);
	4305	}
	4306
	4307
	4308
	4309	/***************************************************************************
	4310	SSE SCALAR SINGLE EMITTERS
	4311	***************************************************************************/
	4312
	4313	#define emit_movss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVSS_Vss_Wss, dreg, sreg)
	4314	#define emit_movss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4315	#define emit_movss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
	4316	#define emit_movss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4317
	4318	#define emit_movss_m32abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVSS_Wss_Vss, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4319	#define emit_movss_m32bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSS_Wss_Vss, sreg, (base), REG_NONE, 1, (disp))
	4320	#define emit_movss_m32isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSS_Wss_Vss, sreg, REG_NONE, (index), (scale), (disp))
	4321
	4322	#define emit_addss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDSS_Vss_Wss, dreg, sreg)
	4323	#define emit_addss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4324	#define emit_addss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
	4325	#define emit_addss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4326
	4327	#define emit_subss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBSS_Vss_Wss, dreg, sreg)
	4328	#define emit_subss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4329	#define emit_subss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
	4330	#define emit_subss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4331
	4332	#define emit_mulss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULSS_Vss_Wss, dreg, sreg)
	4333	#define emit_mulss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4334	#define emit_mulss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
	4335	#define emit_mulss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4336
	4337	#define emit_divss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVSS_Vss_Wss, dreg, sreg)
	4338	#define emit_divss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4339	#define emit_divss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
	4340	#define emit_divss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4341
	4342	#define emit_rcpss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RCPSS_Vss_Wss, dreg, sreg)
	4343	#define emit_rcpss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RCPSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4344	#define emit_rcpss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RCPSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
	4345	#define emit_rcpss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RCPSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4346
	4347	#define emit_sqrtss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTSS_Vss_Wss, dreg, sreg)
	4348	#define emit_sqrtss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4349	#define emit_sqrtss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
	4350	#define emit_sqrtss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4351
	4352	#define emit_rsqrtss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RSQRTSS_Vss_Wss, dreg, sreg)
	4353	#define emit_rsqrtss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RSQRTSS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4354	#define emit_rsqrtss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RSQRTSS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
	4355	#define emit_rsqrtss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RSQRTSS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4356
	4357	#define emit_comiss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_COMISS_Vss_Wss, dreg, sreg)
	4358	#define emit_comiss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_COMISS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4359	#define emit_comiss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_COMISS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
	4360	#define emit_comiss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_COMISS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4361
	4362	#define emit_ucomiss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_UCOMISS_Vss_Wss, dreg, sreg)
	4363	#define emit_ucomiss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_UCOMISS_Vss_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4364	#define emit_ucomiss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_UCOMISS_Vss_Wss, dreg, (base), REG_NONE, 1, (disp))
	4365	#define emit_ucomiss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_UCOMISS_Vss_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4366
	4367	#define emit_cvtsi2ss_r128_r32(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSI2SS_Vss_Ed, dreg, sreg)
	4368	#define emit_cvtsi2ss_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4369	#define emit_cvtsi2ss_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SS_Vss_Ed, dreg, (base), REG_NONE, 1, (disp))
	4370	#define emit_cvtsi2ss_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, (index), (scale), (disp))
	4371
	4372	#ifdef PTR64
	4373	#define emit_cvtsi2ss_r128_r64(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, sreg)
	4374	#define emit_cvtsi2ss_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4375	#define emit_cvtsi2ss_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, (base), REG_NONE, 1, (disp))
	4376	#define emit_cvtsi2ss_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SS_Vss_Ed, dreg, REG_NONE, (index), (scale), (disp))
	4377	#endif
	4378
	4379	#define emit_cvtsd2ss_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSD2SS_Vss_Wsd, dreg, sreg)
	4380	#define emit_cvtsd2ss_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSD2SS_Vss_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4381	#define emit_cvtsd2ss_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SS_Vss_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4382	#define emit_cvtsd2ss_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SS_Vss_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4383
	4384	#define emit_cvtss2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSS2SI_Gd_Wss, dreg, sreg)
	4385	#define emit_cvtss2si_r32_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4386	#define emit_cvtss2si_r32_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
	4387	#define emit_cvtss2si_r32_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4388
	4389	#ifdef PTR64
	4390	#define emit_cvtss2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, sreg)
	4391	#define emit_cvtss2si_r64_m32abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4392	#define emit_cvtss2si_r64_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
	4393	#define emit_cvtss2si_r64_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4394	#endif
	4395
	4396	#define emit_cvttss2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTSS2SI_Gd_Wss, dreg, sreg)
	4397	#define emit_cvttss2si_r32_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4398	#define emit_cvttss2si_r32_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
	4399	#define emit_cvttss2si_r32_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4400
	4401	#ifdef PTR64
	4402	#define emit_cvttss2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, sreg)
	4403	#define emit_cvttss2si_r64_m32abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4404	#define emit_cvttss2si_r64_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, (base), REG_NONE, 1, (disp))
	4405	#define emit_cvttss2si_r64_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSS2SI_Gd_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4406	#endif
	4407
	4408
	4409
	4410	/***************************************************************************
	4411	SSE PACKED SINGLE EMITTERS
	4412	***************************************************************************/
	4413
	4414	#define emit_movps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVPS_Vps_Wps, dreg, sreg)
	4415	#define emit_movps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4416	#define emit_movps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4417	#define emit_movps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4418
	4419	#define emit_movps_m128abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVPS_Wps_Vps, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4420	#define emit_movps_m128bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPS_Wps_Vps, sreg, (base), REG_NONE, 1, (disp))
	4421	#define emit_movps_m128isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPS_Wps_Vps, sreg, REG_NONE, (index), (scale), (disp))
	4422
	4423	#define emit_addps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDPS_Vps_Wps, dreg, sreg)
	4424	#define emit_addps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4425	#define emit_addps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4426	#define emit_addps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4427
	4428	#define emit_subps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBPS_Vps_Wps, dreg, sreg)
	4429	#define emit_subps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4430	#define emit_subps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4431	#define emit_subps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4432
	4433	#define emit_mulps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULPS_Vps_Wps, dreg, sreg)
	4434	#define emit_mulps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4435	#define emit_mulps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4436	#define emit_mulps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4437
	4438	#define emit_divps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVPS_Vps_Wps, dreg, sreg)
	4439	#define emit_divps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4440	#define emit_divps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4441	#define emit_divps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4442
	4443	#define emit_rcpps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RCPPS_Vps_Wps, dreg, sreg)
	4444	#define emit_rcpps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RCPPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4445	#define emit_rcpps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RCPPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4446	#define emit_rcpps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RCPPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4447
	4448	#define emit_sqrtps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTPS_Vps_Wps, dreg, sreg)
	4449	#define emit_sqrtps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4450	#define emit_sqrtps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4451	#define emit_sqrtps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4452
	4453	#define emit_rsqrtps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_RSQRTPS_Vps_Wps, dreg, sreg)
	4454	#define emit_rsqrtps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_RSQRTPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4455	#define emit_rsqrtps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_RSQRTPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4456	#define emit_rsqrtps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_RSQRTPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4457
	4458	#define emit_andps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDPS_Vps_Wps, dreg, sreg)
	4459	#define emit_andps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4460	#define emit_andps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4461	#define emit_andps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4462
	4463	#define emit_andnps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDNPS_Vps_Wps, dreg, sreg)
	4464	#define emit_andnps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDNPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4465	#define emit_andnps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDNPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4466	#define emit_andnps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDNPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4467
	4468	#define emit_orps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ORPS_Vps_Wps, dreg, sreg)
	4469	#define emit_orps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ORPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4470	#define emit_orps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ORPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4471	#define emit_orps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ORPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4472
	4473	#define emit_xorps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_XORPS_Vps_Wps, dreg, sreg)
	4474	#define emit_xorps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_XORPS_Vps_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4475	#define emit_xorps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_XORPS_Vps_Wps, dreg, (base), REG_NONE, 1, (disp))
	4476	#define emit_xorps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_XORPS_Vps_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4477
	4478	#define emit_cvtdq2ps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTDQ2PS_Vps_Wdq, dreg, sreg)
	4479	#define emit_cvtdq2ps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTDQ2PS_Vps_Wdq, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4480	#define emit_cvtdq2ps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PS_Vps_Wdq, dreg, (base), REG_NONE, 1, (disp))
	4481	#define emit_cvtdq2ps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PS_Vps_Wdq, dreg, REG_NONE, (index), (scale), (disp))
	4482
	4483	#define emit_cvtpd2ps_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPD2PS_Vps_Wpd, dreg, sreg)
	4484	#define emit_cvtpd2ps_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPD2PS_Vps_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4485	#define emit_cvtpd2ps_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPD2PS_Vps_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4486	#define emit_cvtpd2ps_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPD2PS_Vps_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4487
	4488	#define emit_cvtps2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPS2DQ_Vdq_Wps, dreg, sreg)
	4489	#define emit_cvtps2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPS2DQ_Vdq_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4490	#define emit_cvtps2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPS2DQ_Vdq_Wps, dreg, (base), REG_NONE, 1, (disp))
	4491	#define emit_cvtps2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPS2DQ_Vdq_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4492
	4493	#define emit_cvttps2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, sreg)
	4494	#define emit_cvttps2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4495	#define emit_cvttps2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, (base), REG_NONE, 1, (disp))
	4496	#define emit_cvttps2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTPS2DQ_Vdq_Wps, dreg, REG_NONE, (index), (scale), (disp))
	4497
	4498
	4499
	4500	/***************************************************************************
	4501	SSE SCALAR DOUBLE EMITTERS
	4502	***************************************************************************/
	4503
	4504	#define emit_movsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVSD_Vsd_Wsd, dreg, sreg)
	4505	#define emit_movsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4506	#define emit_movsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4507	#define emit_movsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4508
	4509	#define emit_movsd_m64abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVSD_Wsd_Vsd, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4510	#define emit_movsd_m64bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSD_Wsd_Vsd, sreg, (base), REG_NONE, 1, (disp))
	4511	#define emit_movsd_m64isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVSD_Wsd_Vsd, sreg, REG_NONE, (index), (scale), (disp))
	4512
	4513	#define emit_addsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDSD_Vsd_Wsd, dreg, sreg)
	4514	#define emit_addsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4515	#define emit_addsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4516	#define emit_addsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4517
	4518	#define emit_subsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBSD_Vsd_Wsd, dreg, sreg)
	4519	#define emit_subsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4520	#define emit_subsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4521	#define emit_subsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4522
	4523	#define emit_mulsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULSD_Vsd_Wsd, dreg, sreg)
	4524	#define emit_mulsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4525	#define emit_mulsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4526	#define emit_mulsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4527
	4528	#define emit_divsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVSD_Vsd_Wsd, dreg, sreg)
	4529	#define emit_divsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4530	#define emit_divsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4531	#define emit_divsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4532
	4533	#define emit_sqrtsd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTSD_Vsd_Wsd, dreg, sreg)
	4534	#define emit_sqrtsd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTSD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4535	#define emit_sqrtsd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTSD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4536	#define emit_sqrtsd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTSD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4537
	4538	#define emit_comisd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_COMISD_Vsd_Wsd, dreg, sreg)
	4539	#define emit_comisd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_COMISD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4540	#define emit_comisd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_COMISD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4541	#define emit_comisd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_COMISD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4542
	4543	#define emit_ucomisd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_UCOMISD_Vsd_Wsd, dreg, sreg)
	4544	#define emit_ucomisd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_UCOMISD_Vsd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4545	#define emit_ucomisd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_UCOMISD_Vsd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4546	#define emit_ucomisd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_UCOMISD_Vsd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4547
	4548	#define emit_cvtsi2sd_r128_r32(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSI2SD_Vsd_Ed, dreg, sreg)
	4549	#define emit_cvtsi2sd_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4550	#define emit_cvtsi2sd_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SD_Vsd_Ed, dreg, (base), REG_NONE, 1, (disp))
	4551	#define emit_cvtsi2sd_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, (index), (scale), (disp))
	4552
	4553	#ifdef PTR64
	4554	#define emit_cvtsi2sd_r128_r64(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, sreg)
	4555	#define emit_cvtsi2sd_r128_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4556	#define emit_cvtsi2sd_r128_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, (base), REG_NONE, 1, (disp))
	4557	#define emit_cvtsi2sd_r128_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSI2SD_Vsd_Ed, dreg, REG_NONE, (index), (scale), (disp))
	4558	#endif
	4559
	4560	#define emit_cvtss2sd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSS2SD_Vsd_Wss, dreg, sreg)
	4561	#define emit_cvtss2sd_r128_m32abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSS2SD_Vsd_Wss, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4562	#define emit_cvtss2sd_r128_m32bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SD_Vsd_Wss, dreg, (base), REG_NONE, 1, (disp))
	4563	#define emit_cvtss2sd_r128_m32isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSS2SD_Vsd_Wss, dreg, REG_NONE, (index), (scale), (disp))
	4564
	4565	#define emit_cvtsd2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTSD2SI_Gd_Wsd, dreg, sreg)
	4566	#define emit_cvtsd2si_r32_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4567	#define emit_cvtsd2si_r32_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4568	#define emit_cvtsd2si_r32_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4569
	4570	#ifdef PTR64
	4571	#define emit_cvtsd2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, sreg)
	4572	#define emit_cvtsd2si_r64_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4573	#define emit_cvtsd2si_r64_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4574	#define emit_cvtsd2si_r64_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4575	#endif
	4576
	4577	#define emit_cvttsd2si_r32_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTSD2SI_Gd_Wsd, dreg, sreg)
	4578	#define emit_cvttsd2si_r32_m64abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4579	#define emit_cvttsd2si_r32_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4580	#define emit_cvttsd2si_r32_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4581
	4582	#ifdef PTR64
	4583	#define emit_cvttsd2si_r64_r128(e, dreg, sreg) emit_sse_r128_r128_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, sreg)
	4584	#define emit_cvttsd2si_r64_m64abs(e, dreg, addr) emit_sse_r128_mbisd_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4585	#define emit_cvttsd2si_r64_m64bd(e, dreg, base, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, (base), REG_NONE, 1, (disp))
	4586	#define emit_cvttsd2si_r64_m64isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd_rex(e, OP_CVTTSD2SI_Gd_Wsd, dreg, REG_NONE, (index), (scale), (disp))
	4587	#endif
	4588
	4589
	4590
	4591	/***************************************************************************
	4592	SSE PACKED DOUBLE EMITTERS
	4593	***************************************************************************/
	4594
	4595	#define emit_movpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MOVPD_Vpd_Wpd, dreg, sreg)
	4596	#define emit_movpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MOVPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4597	#define emit_movpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MOVPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4598	#define emit_movpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MOVPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4599
	4600	#define emit_movpd_m128abs_r128(e, addr, sreg) emit_sse_r128_mbisd(e, OP_MOVPD_Wpd_Vpd, sreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4601	#define emit_movpd_m128bd_r128(e, base, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPD_Wpd_Vpd, sreg, (base), REG_NONE, 1, (disp))
	4602	#define emit_movpd_m128isd_r128(e, index, scale, disp, sreg) emit_sse_r128_mbisd(e, OP_MOVPD_Wpd_Vpd, sreg, REG_NONE, (index), (scale), (disp))
	4603
	4604	#define emit_addpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ADDPD_Vpd_Wpd, dreg, sreg)
	4605	#define emit_addpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ADDPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4606	#define emit_addpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ADDPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4607	#define emit_addpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ADDPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4608
	4609	#define emit_subpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SUBPD_Vpd_Wpd, dreg, sreg)
	4610	#define emit_subpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SUBPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4611	#define emit_subpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SUBPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4612	#define emit_subpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SUBPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4613
	4614	#define emit_mulpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_MULPD_Vpd_Wpd, dreg, sreg)
	4615	#define emit_mulpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_MULPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4616	#define emit_mulpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_MULPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4617	#define emit_mulpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_MULPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4618
	4619	#define emit_divpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_DIVPD_Vpd_Wpd, dreg, sreg)
	4620	#define emit_divpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_DIVPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4621	#define emit_divpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_DIVPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4622	#define emit_divpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_DIVPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4623
	4624	#define emit_sqrtpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_SQRTPD_Vpd_Wpd, dreg, sreg)
	4625	#define emit_sqrtpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_SQRTPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4626	#define emit_sqrtpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_SQRTPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4627	#define emit_sqrtpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_SQRTPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4628
	4629	#define emit_andpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDPD_Vpd_Wpd, dreg, sreg)
	4630	#define emit_andpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4631	#define emit_andpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4632	#define emit_andpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4633
	4634	#define emit_andnpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ANDNPD_Vpd_Wpd, dreg, sreg)
	4635	#define emit_andnpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ANDNPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4636	#define emit_andnpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ANDNPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4637	#define emit_andnpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ANDNPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4638
	4639	#define emit_orpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_ORPD_Vpd_Wpd, dreg, sreg)
	4640	#define emit_orpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_ORPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4641	#define emit_orpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_ORPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4642	#define emit_orpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_ORPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4643
	4644	#define emit_xorpd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_XORPD_Vpd_Wpd, dreg, sreg)
	4645	#define emit_xorpd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_XORPD_Vpd_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4646	#define emit_xorpd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_XORPD_Vpd_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4647	#define emit_xorpd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_XORPD_Vpd_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4648
	4649	#define emit_cvtdq2pd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTDQ2PD_Vpd_Wq, dreg, sreg)
	4650	#define emit_cvtdq2pd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTDQ2PD_Vpd_Wq, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4651	#define emit_cvtdq2pd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PD_Vpd_Wq, dreg, (base), REG_NONE, 1, (disp))
	4652	#define emit_cvtdq2pd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTDQ2PD_Vpd_Wq, dreg, REG_NONE, (index), (scale), (disp))
	4653
	4654	#define emit_cvtps2pd_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPS2PD_Vpd_Wq, dreg, sreg)
	4655	#define emit_cvtps2pd_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPS2PD_Vpd_Wq, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4656	#define emit_cvtps2pd_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPS2PD_Vpd_Wq, dreg, (base), REG_NONE, 1, (disp))
	4657	#define emit_cvtps2pd_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPS2PD_Vpd_Wq, dreg, REG_NONE, (index), (scale), (disp))
	4658
	4659	#define emit_cvtpd2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, sreg)
	4660	#define emit_cvtpd2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4661	#define emit_cvtpd2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4662	#define emit_cvtpd2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTPD2DQ_Vdq_Wpd, dreg, REG_NONE, (index), (scale), (disp))
	4663
	4664	#define emit_cvttpd2dq_r128_r128(e, dreg, sreg) emit_sse_r128_r128(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, sreg)
	4665	#define emit_cvttpd2dq_r128_m128abs(e, dreg, addr) emit_sse_r128_mbisd(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, REG_NONE, REG_NONE, 1, (INT32)(addr))
	4666	#define emit_cvttpd2dq_r128_m128bd(e, dreg, base, disp) emit_sse_r128_mbisd(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, (base), REG_NONE, 1, (disp))
	4667	#define emit_cvttpd2dq_r128_m128isd(e, dreg, index, scale, disp) emit_sse_r128_mbisd(e, OP_CVTTPD2DQ_Vdq_Wpd, dreg, REG_NONE, (index), (scale), (disp))

src/emu/memory.c
r894	r895
2493	2493	return 0; \
2494	2494	} \
2495	2495
	2496	#define READMASKED32(name,spacenum) \
	2497	UINT32 name(offs_t address, UINT32 mem_mask) \
	2498	{ \
	2499	UINT32 entry; \
	2500	MEMREADSTART(); \
	2501	PERFORM_LOOKUP(readlookup,active_address_space[spacenum],~3); \
	2502	DEBUG_HOOK_READ(spacenum, 4, address); \
	2503	\
	2504	/* handle banks inline */ \
	2505	address = (address - active_address_space[spacenum].readhandlers[entry].offset) & active_address_space[spacenum].readhandlers[entry].mask;\
	2506	if (entry < STATIC_RAM) \
	2507	MEMREADEND((UINT32 )&bank_ptr[entry][address]); \
	2508	\
	2509	/* fall back to the handler */ \
	2510	else \
	2511	MEMREADEND((*active_address_space[spacenum].readhandlers[entry].handler.read.handler32)(address >> 2, mem_mask));\
	2512	return 0; \
	2513	} \
	2514
2496	2515	#define READDWORD(name,spacenum,xormacro,handlertype,ignorebits,shiftbytes,masktype) \
2497	2516	UINT32 name(offs_t address) \
2498	2517	{ \
r894	r895
2543	2562	return 0; \
2544	2563	} \
2545	2564
	2565	#define READMASKED64(name,spacenum) \
	2566	UINT64 name(offs_t address, UINT64 mem_mask) \
	2567	{ \
	2568	UINT32 entry; \
	2569	MEMREADSTART(); \
	2570	PERFORM_LOOKUP(readlookup,active_address_space[spacenum],~7); \
	2571	DEBUG_HOOK_READ(spacenum, 8, address); \
	2572	\
	2573	/* handle banks inline */ \
	2574	address = (address - active_address_space[spacenum].readhandlers[entry].offset) & active_address_space[spacenum].readhandlers[entry].mask;\
	2575	if (entry < STATIC_RAM) \
	2576	MEMREADEND((UINT64 )&bank_ptr[entry][address]); \
	2577	\
	2578	/* fall back to the handler */ \
	2579	else \
	2580	MEMREADEND((*active_address_space[spacenum].readhandlers[entry].handler.read.handler64)(address >> 3, mem_mask));\
	2581	return 0; \
	2582	} \
2546	2583
	2584
2547	2585	/*-------------------------------------------------
2548	2586	WRITEBYTE - generic byte-sized write handler
2549	2587	-------------------------------------------------*/
r894	r895
2668	2706	MEMWRITEEND((*active_address_space[spacenum].writehandlers[entry].handler.write.handler32)(address >> 2, data, 0));\
2669	2707	} \
2670	2708
	2709	#define WRITEMASKED32(name,spacenum) \
	2710	void name(offs_t address, UINT32 data, UINT32 mem_mask) \
	2711	{ \
	2712	UINT32 entry; \
	2713	MEMWRITESTART(); \
	2714	PERFORM_LOOKUP(writelookup,active_address_space[spacenum],~3); \
	2715	DEBUG_HOOK_WRITE(spacenum, 4, address, data); \
	2716	\
	2717	/* handle banks inline */ \
	2718	address = (address - active_address_space[spacenum].writehandlers[entry].offset) & active_address_space[spacenum].writehandlers[entry].mask;\
	2719	if (entry < STATIC_RAM) \
	2720	{ \
	2721	UINT32 dest = (UINT32 )&bank_ptr[entry][address]; \
	2722	MEMWRITEEND(dest = (dest & mem_mask) \| (data & ~mem_mask)); \
	2723	} \
	2724	\
	2725	/* fall back to the handler */ \
	2726	else \
	2727	MEMWRITEEND((*active_address_space[spacenum].writehandlers[entry].handler.write.handler32)(address >> 2, data, mem_mask));\
	2728	} \
	2729
2671	2730	#define WRITEDWORD(name,spacenum,xormacro,handlertype,ignorebits,shiftbytes,masktype) \
2672	2731	void name(offs_t address, UINT32 data) \
2673	2732	{ \
r894	r895
2716	2775	MEMWRITEEND((*active_address_space[spacenum].writehandlers[entry].handler.write.handler64)(address >> 3, data, 0));\
2717	2776	} \
2718	2777
	2778	#define WRITEMASKED64(name,spacenum) \
	2779	void name(offs_t address, UINT64 data, UINT64 mem_mask) \
	2780	{ \
	2781	UINT32 entry; \
	2782	MEMWRITESTART(); \
	2783	PERFORM_LOOKUP(writelookup,active_address_space[spacenum],~7); \
	2784	DEBUG_HOOK_WRITE(spacenum, 8, address, data); \
	2785	\
	2786	/* handle banks inline */ \
	2787	address = (address - active_address_space[spacenum].writehandlers[entry].offset) & active_address_space[spacenum].writehandlers[entry].mask;\
	2788	if (entry < STATIC_RAM) \
	2789	{ \
	2790	UINT64 dest = (UINT64 )&bank_ptr[entry][address]; \
	2791	MEMWRITEEND(dest = (dest & mem_mask) \| (data & ~mem_mask)); \
	2792	} \
	2793	\
	2794	/* fall back to the handler */ \
	2795	else \
	2796	MEMWRITEEND((*active_address_space[spacenum].writehandlers[entry].handler.write.handler64)(address >> 3, data, mem_mask));\
	2797	} \
2719	2798
	2799
2720	2800	/*-------------------------------------------------
2721	2801	Program memory handlers
2722	2802	-------------------------------------------------*/
r894	r895
2737	2817	READBYTE32BE(program_read_byte_32be, ADDRESS_SPACE_PROGRAM)
2738	2818	READWORD32BE(program_read_word_32be, ADDRESS_SPACE_PROGRAM)
2739	2819	READDWORD32(program_read_dword_32be, ADDRESS_SPACE_PROGRAM)
	2820	READMASKED32(program_read_masked_32be, ADDRESS_SPACE_PROGRAM)
2740	2821	WRITEBYTE32BE(program_write_byte_32be, ADDRESS_SPACE_PROGRAM)
2741	2822	WRITEWORD32BE(program_write_word_32be, ADDRESS_SPACE_PROGRAM)
2742	2823	WRITEDWORD32(program_write_dword_32be, ADDRESS_SPACE_PROGRAM)
	2824	WRITEMASKED32(program_write_masked_32be,ADDRESS_SPACE_PROGRAM)
2743	2825
2744	2826	READBYTE32LE(program_read_byte_32le, ADDRESS_SPACE_PROGRAM)
2745	2827	READWORD32LE(program_read_word_32le, ADDRESS_SPACE_PROGRAM)
2746	2828	READDWORD32(program_read_dword_32le, ADDRESS_SPACE_PROGRAM)
	2829	READMASKED32(program_read_masked_32le, ADDRESS_SPACE_PROGRAM)
2747	2830	WRITEBYTE32LE(program_write_byte_32le, ADDRESS_SPACE_PROGRAM)
2748	2831	WRITEWORD32LE(program_write_word_32le, ADDRESS_SPACE_PROGRAM)
2749	2832	WRITEDWORD32(program_write_dword_32le, ADDRESS_SPACE_PROGRAM)
	2833	WRITEMASKED32(program_write_masked_32le,ADDRESS_SPACE_PROGRAM)
2750	2834
2751	2835	READBYTE64BE(program_read_byte_64be, ADDRESS_SPACE_PROGRAM)
2752	2836	READWORD64BE(program_read_word_64be, ADDRESS_SPACE_PROGRAM)
2753	2837	READDWORD64BE(program_read_dword_64be, ADDRESS_SPACE_PROGRAM)
2754	2838	READQWORD64(program_read_qword_64be, ADDRESS_SPACE_PROGRAM)
	2839	READMASKED64(program_read_masked_64be, ADDRESS_SPACE_PROGRAM)
2755	2840	WRITEBYTE64BE(program_write_byte_64be, ADDRESS_SPACE_PROGRAM)
2756	2841	WRITEWORD64BE(program_write_word_64be, ADDRESS_SPACE_PROGRAM)
2757	2842	WRITEDWORD64BE(program_write_dword_64be, ADDRESS_SPACE_PROGRAM)
2758	2843	WRITEQWORD64(program_write_qword_64be, ADDRESS_SPACE_PROGRAM)
	2844	WRITEMASKED64(program_write_masked_64be,ADDRESS_SPACE_PROGRAM)
2759	2845
2760	2846	READBYTE64LE(program_read_byte_64le, ADDRESS_SPACE_PROGRAM)
2761	2847	READWORD64LE(program_read_word_64le, ADDRESS_SPACE_PROGRAM)
2762	2848	READDWORD64LE(program_read_dword_64le, ADDRESS_SPACE_PROGRAM)
2763	2849	READQWORD64(program_read_qword_64le, ADDRESS_SPACE_PROGRAM)
	2850	READMASKED64(program_read_masked_64le, ADDRESS_SPACE_PROGRAM)
2764	2851	WRITEBYTE64LE(program_write_byte_64le, ADDRESS_SPACE_PROGRAM)
2765	2852	WRITEWORD64LE(program_write_word_64le, ADDRESS_SPACE_PROGRAM)
2766	2853	WRITEDWORD64LE(program_write_dword_64le, ADDRESS_SPACE_PROGRAM)
2767	2854	WRITEQWORD64(program_write_qword_64le, ADDRESS_SPACE_PROGRAM)
	2855	WRITEMASKED64(program_write_masked_64le,ADDRESS_SPACE_PROGRAM)
2768	2856
2769	2857
2770	2858	/*-------------------------------------------------
r894	r895
2787	2875	READBYTE32BE(data_read_byte_32be, ADDRESS_SPACE_DATA)
2788	2876	READWORD32BE(data_read_word_32be, ADDRESS_SPACE_DATA)
2789	2877	READDWORD32(data_read_dword_32be, ADDRESS_SPACE_DATA)
	2878	READMASKED32(data_read_masked_32be, ADDRESS_SPACE_DATA)
2790	2879	WRITEBYTE32BE(data_write_byte_32be, ADDRESS_SPACE_DATA)
2791	2880	WRITEWORD32BE(data_write_word_32be, ADDRESS_SPACE_DATA)
2792	2881	WRITEDWORD32(data_write_dword_32be, ADDRESS_SPACE_DATA)
	2882	WRITEMASKED32(data_write_masked_32be,ADDRESS_SPACE_DATA)
2793	2883
2794	2884	READBYTE32LE(data_read_byte_32le, ADDRESS_SPACE_DATA)
2795	2885	READWORD32LE(data_read_word_32le, ADDRESS_SPACE_DATA)
2796	2886	READDWORD32(data_read_dword_32le, ADDRESS_SPACE_DATA)
	2887	READMASKED32(data_read_masked_32le, ADDRESS_SPACE_DATA)
2797	2888	WRITEBYTE32LE(data_write_byte_32le, ADDRESS_SPACE_DATA)
2798	2889	WRITEWORD32LE(data_write_word_32le, ADDRESS_SPACE_DATA)
2799	2890	WRITEDWORD32(data_write_dword_32le, ADDRESS_SPACE_DATA)
	2891	WRITEMASKED32(data_write_masked_32le,ADDRESS_SPACE_DATA)
2800	2892
2801	2893	READBYTE64BE(data_read_byte_64be, ADDRESS_SPACE_DATA)
2802	2894	READWORD64BE(data_read_word_64be, ADDRESS_SPACE_DATA)
2803	2895	READDWORD64BE(data_read_dword_64be, ADDRESS_SPACE_DATA)
2804	2896	READQWORD64(data_read_qword_64be, ADDRESS_SPACE_DATA)
	2897	READMASKED64(data_read_masked_64be, ADDRESS_SPACE_DATA)
2805	2898	WRITEBYTE64BE(data_write_byte_64be, ADDRESS_SPACE_DATA)
2806	2899	WRITEWORD64BE(data_write_word_64be, ADDRESS_SPACE_DATA)
2807	2900	WRITEDWORD64BE(data_write_dword_64be, ADDRESS_SPACE_DATA)
2808	2901	WRITEQWORD64(data_write_qword_64be, ADDRESS_SPACE_DATA)
	2902	WRITEMASKED64(data_write_masked_64be,ADDRESS_SPACE_DATA)
2809	2903
2810	2904	READBYTE64LE(data_read_byte_64le, ADDRESS_SPACE_DATA)
2811	2905	READWORD64LE(data_read_word_64le, ADDRESS_SPACE_DATA)
2812	2906	READDWORD64LE(data_read_dword_64le, ADDRESS_SPACE_DATA)
2813	2907	READQWORD64(data_read_qword_64le, ADDRESS_SPACE_DATA)
	2908	READMASKED64(data_read_masked_64le, ADDRESS_SPACE_DATA)
2814	2909	WRITEBYTE64LE(data_write_byte_64le, ADDRESS_SPACE_DATA)
2815	2910	WRITEWORD64LE(data_write_word_64le, ADDRESS_SPACE_DATA)
2816	2911	WRITEDWORD64LE(data_write_dword_64le, ADDRESS_SPACE_DATA)
2817	2912	WRITEQWORD64(data_write_qword_64le, ADDRESS_SPACE_DATA)
	2913	WRITEMASKED64(data_write_masked_64le,ADDRESS_SPACE_DATA)
2818	2914
2819	2915
2820	2916	/*-------------------------------------------------
r894	r895
2837	2933	READBYTE32BE(io_read_byte_32be, ADDRESS_SPACE_IO)
2838	2934	READWORD32BE(io_read_word_32be, ADDRESS_SPACE_IO)
2839	2935	READDWORD32(io_read_dword_32be, ADDRESS_SPACE_IO)
	2936	READMASKED32(io_read_masked_32be, ADDRESS_SPACE_IO)
2840	2937	WRITEBYTE32BE(io_write_byte_32be, ADDRESS_SPACE_IO)
2841	2938	WRITEWORD32BE(io_write_word_32be, ADDRESS_SPACE_IO)
2842	2939	WRITEDWORD32(io_write_dword_32be, ADDRESS_SPACE_IO)
	2940	WRITEMASKED32(io_write_masked_32be,ADDRESS_SPACE_IO)
2843	2941
2844	2942	READBYTE32LE(io_read_byte_32le, ADDRESS_SPACE_IO)
2845	2943	READWORD32LE(io_read_word_32le, ADDRESS_SPACE_IO)
2846	2944	READDWORD32(io_read_dword_32le, ADDRESS_SPACE_IO)
	2945	READMASKED32(io_read_masked_32le, ADDRESS_SPACE_IO)
2847	2946	WRITEBYTE32LE(io_write_byte_32le, ADDRESS_SPACE_IO)
2848	2947	WRITEWORD32LE(io_write_word_32le, ADDRESS_SPACE_IO)
2849	2948	WRITEDWORD32(io_write_dword_32le, ADDRESS_SPACE_IO)
	2949	WRITEMASKED32(io_write_masked_32le,ADDRESS_SPACE_IO)
2850	2950
2851	2951	READBYTE64BE(io_read_byte_64be, ADDRESS_SPACE_IO)
2852	2952	READWORD64BE(io_read_word_64be, ADDRESS_SPACE_IO)
2853	2953	READDWORD64BE(io_read_dword_64be, ADDRESS_SPACE_IO)
2854	2954	READQWORD64(io_read_qword_64be, ADDRESS_SPACE_IO)
	2955	READMASKED64(io_read_masked_64be, ADDRESS_SPACE_IO)
2855	2956	WRITEBYTE64BE(io_write_byte_64be, ADDRESS_SPACE_IO)
2856	2957	WRITEWORD64BE(io_write_word_64be, ADDRESS_SPACE_IO)
2857	2958	WRITEDWORD64BE(io_write_dword_64be, ADDRESS_SPACE_IO)
2858	2959	WRITEQWORD64(io_write_qword_64be, ADDRESS_SPACE_IO)
	2960	WRITEMASKED64(io_write_masked_64be,ADDRESS_SPACE_IO)
2859	2961
2860	2962	READBYTE64LE(io_read_byte_64le, ADDRESS_SPACE_IO)
2861	2963	READWORD64LE(io_read_word_64le, ADDRESS_SPACE_IO)
2862	2964	READDWORD64LE(io_read_dword_64le, ADDRESS_SPACE_IO)
2863	2965	READQWORD64(io_read_qword_64le, ADDRESS_SPACE_IO)
	2966	READMASKED64(io_read_masked_64le, ADDRESS_SPACE_IO)
2864	2967	WRITEBYTE64LE(io_write_byte_64le, ADDRESS_SPACE_IO)
2865	2968	WRITEWORD64LE(io_write_word_64le, ADDRESS_SPACE_IO)
2866	2969	WRITEDWORD64LE(io_write_dword_64le, ADDRESS_SPACE_IO)
2867	2970	WRITEQWORD64(io_write_qword_64le, ADDRESS_SPACE_IO)
	2971	WRITEMASKED64(io_write_masked_64le,ADDRESS_SPACE_IO)
2868	2972
2869	2973
2870	2974	/*-------------------------------------------------

src/emu/memory.h
r894	r895
773	773	UINT8 program_read_byte_32be(offs_t address);
774	774	UINT16 program_read_word_32be(offs_t address);
775	775	UINT32 program_read_dword_32be(offs_t address);
	776	UINT32 program_read_masked_32be(offs_t address, UINT32 mem_mask);
776	777	void program_write_byte_32be(offs_t address, UINT8 data);
777	778	void program_write_word_32be(offs_t address, UINT16 data);
778	779	void program_write_dword_32be(offs_t address, UINT32 data);
	780	void program_write_masked_32be(offs_t address, UINT32 data, UINT32 mem_mask);
779	781
780	782	UINT8 program_read_byte_32le(offs_t address);
781	783	UINT16 program_read_word_32le(offs_t address);
782	784	UINT32 program_read_dword_32le(offs_t address);
	785	UINT32 program_read_masked_32le(offs_t address, UINT32 mem_mask);
783	786	void program_write_byte_32le(offs_t address, UINT8 data);
784	787	void program_write_word_32le(offs_t address, UINT16 data);
785	788	void program_write_dword_32le(offs_t address, UINT32 data);
	789	void program_write_masked_32le(offs_t address, UINT32 data, UINT32 mem_mask);
786	790
787	791	UINT8 program_read_byte_64be(offs_t address);
788	792	UINT16 program_read_word_64be(offs_t address);
789	793	UINT32 program_read_dword_64be(offs_t address);
790	794	UINT64 program_read_qword_64be(offs_t address);
	795	UINT64 program_read_masked_64be(offs_t address, UINT64 mem_mask);
791	796	void program_write_byte_64be(offs_t address, UINT8 data);
792	797	void program_write_word_64be(offs_t address, UINT16 data);
793	798	void program_write_dword_64be(offs_t address, UINT32 data);
794	799	void program_write_qword_64be(offs_t address, UINT64 data);
	800	void program_write_masked_64be(offs_t address, UINT64 data, UINT64 mem_mask);
795	801
796	802	UINT8 program_read_byte_64le(offs_t address);
797	803	UINT16 program_read_word_64le(offs_t address);
798	804	UINT32 program_read_dword_64le(offs_t address);
799	805	UINT64 program_read_qword_64le(offs_t address);
	806	UINT64 program_read_masked_64le(offs_t address, UINT64 mem_mask);
800	807	void program_write_byte_64le(offs_t address, UINT8 data);
801	808	void program_write_word_64le(offs_t address, UINT16 data);
802	809	void program_write_dword_64le(offs_t address, UINT32 data);
803	810	void program_write_qword_64le(offs_t address, UINT64 data);
	811	void program_write_masked_64le(offs_t address, UINT64 data, UINT64 mem_mask);
804	812
805	813	/* ----- declare data address space handlers ----- */
806	814	UINT8 data_read_byte_8(offs_t address);
r894	r895
819	827	UINT8 data_read_byte_32be(offs_t address);
820	828	UINT16 data_read_word_32be(offs_t address);
821	829	UINT32 data_read_dword_32be(offs_t address);
	830	UINT32 data_read_masked_32be(offs_t address, UINT32 mem_mask);
822	831	void data_write_byte_32be(offs_t address, UINT8 data);
823	832	void data_write_word_32be(offs_t address, UINT16 data);
824	833	void data_write_dword_32be(offs_t address, UINT32 data);
	834	void data_write_masked_32be(offs_t address, UINT32 data, UINT32 mem_mask);
825	835
826	836	UINT8 data_read_byte_32le(offs_t address);
827	837	UINT16 data_read_word_32le(offs_t address);
828	838	UINT32 data_read_dword_32le(offs_t address);
	839	UINT32 data_read_masked_32le(offs_t address, UINT32 mem_mask);
829	840	void data_write_byte_32le(offs_t address, UINT8 data);
830	841	void data_write_word_32le(offs_t address, UINT16 data);
831	842	void data_write_dword_32le(offs_t address, UINT32 data);
	843	void data_write_masked_32le(offs_t address, UINT32 data, UINT32 mem_mask);
832	844
833	845	UINT8 data_read_byte_64be(offs_t address);
834	846	UINT16 data_read_word_64be(offs_t address);
835	847	UINT32 data_read_dword_64be(offs_t address);
836	848	UINT64 data_read_qword_64be(offs_t address);
	849	UINT64 data_read_masked_64be(offs_t address, UINT64 mem_mask);
837	850	void data_write_byte_64be(offs_t address, UINT8 data);
838	851	void data_write_word_64be(offs_t address, UINT16 data);
839	852	void data_write_dword_64be(offs_t address, UINT32 data);
840	853	void data_write_qword_64be(offs_t address, UINT64 data);
	854	void data_write_masked_64be(offs_t address, UINT64 data, UINT64 mem_mask);
841	855
842	856	UINT8 data_read_byte_64le(offs_t address);
843	857	UINT16 data_read_word_64le(offs_t address);
844	858	UINT32 data_read_dword_64le(offs_t address);
845	859	UINT64 data_read_qword_64le(offs_t address);
	860	UINT64 data_read_masked_64le(offs_t address, UINT64 mem_mask);
846	861	void data_write_byte_64le(offs_t address, UINT8 data);
847	862	void data_write_word_64le(offs_t address, UINT16 data);
848	863	void data_write_dword_64le(offs_t address, UINT32 data);
849	864	void data_write_qword_64le(offs_t address, UINT64 data);
	865	void data_write_masked_64le(offs_t address, UINT64 data, UINT64 mem_mask);
850	866
851	867	/* ----- declare I/O address space handlers ----- */
852	868	UINT8 io_read_byte_8(offs_t address);
r894	r895
865	881	UINT8 io_read_byte_32be(offs_t address);
866	882	UINT16 io_read_word_32be(offs_t address);
867	883	UINT32 io_read_dword_32be(offs_t address);
	884	UINT32 io_read_masked_32be(offs_t address, UINT32 mem_mask);
868	885	void io_write_byte_32be(offs_t address, UINT8 data);
869	886	void io_write_word_32be(offs_t address, UINT16 data);
870	887	void io_write_dword_32be(offs_t address, UINT32 data);
	888	void io_write_masked_32be(offs_t address, UINT32 data, UINT32 mem_mask);
871	889
872	890	UINT8 io_read_byte_32le(offs_t address);
873	891	UINT16 io_read_word_32le(offs_t address);
874	892	UINT32 io_read_dword_32le(offs_t address);
	893	UINT32 io_read_masked_32le(offs_t address, UINT32 mem_mask);
875	894	void io_write_byte_32le(offs_t address, UINT8 data);
876	895	void io_write_word_32le(offs_t address, UINT16 data);
877	896	void io_write_dword_32le(offs_t address, UINT32 data);
	897	void io_write_masked_32le(offs_t address, UINT32 data, UINT32 mem_mask);
878	898
879	899	UINT8 io_read_byte_64be(offs_t address);
880	900	UINT16 io_read_word_64be(offs_t address);
881	901	UINT32 io_read_dword_64be(offs_t address);
882	902	UINT64 io_read_qword_64be(offs_t address);
	903	UINT64 io_read_masked_64be(offs_t address, UINT64 mem_mask);
883	904	void io_write_byte_64be(offs_t address, UINT8 data);
884	905	void io_write_word_64be(offs_t address, UINT16 data);
885	906	void io_write_dword_64be(offs_t address, UINT32 data);
886	907	void io_write_qword_64be(offs_t address, UINT64 data);
	908	void io_write_masked_64be(offs_t address, UINT64 data, UINT64 mem_mask);
887	909
888	910	UINT8 io_read_byte_64le(offs_t address);
889	911	UINT16 io_read_word_64le(offs_t address);
890	912	UINT32 io_read_dword_64le(offs_t address);
891	913	UINT64 io_read_qword_64le(offs_t address);
	914	UINT64 io_read_masked_64le(offs_t address, UINT64 mem_mask);
892	915	void io_write_byte_64le(offs_t address, UINT8 data);
893	916	void io_write_word_64le(offs_t address, UINT16 data);
894	917	void io_write_dword_64le(offs_t address, UINT32 data);
895	918	void io_write_qword_64le(offs_t address, UINT64 data);
	919	void io_write_masked_64le(offs_t address, UINT64 data, UINT64 mem_mask);
896	920
897	921
898	922

src/emu/cpuintrf.c
r894	r895
953	953	(*intf->get_info)(CPUINFO_PTR_TRANSLATE, &info);
954	954	intf->translate = info.translate;
955	955
956		/* get the instruction count pointer */
957		(*intf->get_info)(CPUINFO_PTR_INSTRUCTION_COUNTER, &info); intf->icount = info.icount;
958
959	956	/* get other miscellaneous stuff */
960	957	intf->context_size = cputype_context_size(cputype);
961	958	intf->address_shift = cputype_addrbus_shift(cputype, ADDRESS_SPACE_PROGRAM);
r894	r895
1036	1033
1037	1034	int cpuintrf_init_cpu(int cpunum, int cputype, int clock, const void config, int (irqcallback)(int))
1038	1035	{
	1036	cpuinfo info;
	1037
1039	1038	/* allocate a context buffer for the CPU */
1040	1039	cpu[cpunum].context = auto_malloc(cpu[cpunum].intf.context_size);
1041	1040	memset(cpu[cpunum].context, 0, cpu[cpunum].intf.context_size);
r894	r895
1046	1045	(*cpu[cpunum].intf.get_context)(cpu[cpunum].context);
1047	1046	activecpu = -1;
1048	1047
	1048	/* get the instruction count pointer */
	1049	info.icount = NULL;
	1050	(*cpu[cpunum].intf.get_info)(CPUINFO_PTR_INSTRUCTION_COUNTER, &info);
	1051	cpu[cpunum].intf.icount = info.icount;
	1052
1049	1053	/* clear out the registered CPU for this family */
1050	1054	cpu_active_context[cpu[cpunum].family] = -1;
1051	1055	return 0;

src/lib/util/cdrom.h
r894	r895
78	78	};
79	79
80	80
81		typedef struct _cdrom_track_input_info cdrom_track_input_info;
82		struct _cdrom_track_input_info /* used only at compression time */
83		{
84		char fname[CD_MAX_TRACKS][256]; /* filename for each track */
85		UINT32 offset[CD_MAX_TRACKS]; /* offset in the data file for each track */
86		};
87
88
89	81	typedef struct _cdrom_toc cdrom_toc;
90	82	struct _cdrom_toc
91	83	{

src/mess/mess.mak
r894	r895
64	64	#CPUS += DECO16
65	65	CPUS += M4510
66	66	CPUS += H6280
67		#CPUS += I8086
68		#CPUS += I8088
69		#CPUS += I80186
	67	CPUS += I8086
	68	CPUS += I8088
	69	CPUS += I80186
70	70	#CPUS += I80188
71		#CPUS += I80286
	71	CPUS += I80286
72	72	CPUS += V20
73	73	#CPUS += V25
74	74	#CPUS += V30
r894	r895
211	211	CPUS += TMS7000_EXL
212	212	CPUS += SM8500
213	213	CPUS += V30MZ
214		CPUS += I8086
215		CPUS += I8088
216		CPUS += I80186
217		#CPUS += I80188
218		CPUS += I80286
219	214	CPUS += M68008
220	215	#CPUS += TMS99000
221	216	CPUS += TMS99010

docs/messnew.txt
r894	r895
44	44
45	45	Source Changes:
46	46	----------------
47		- The core is based on MAME 0.118u3. This incorporates all features of the
	47	- The core is based on MAME 0.118u4. This incorporates all features of the
48	48	update to this core. [MAME team]
49	49
50	50

15994 Revisions