src/mess/drivers/pce.c
| r892 | r893 | |
|---|
| 110 | 110 | /* do VRAM > SATB DMA if the enable bit is set or the DVSSR reg. was written to */ |
| 111 | 111 | if((vdc.vdc_data[DCR].w & DCR_DSR) || vdc.dvssr_write) |
| 112 | 112 | { |
| 113 | int i; |
| 113 | 114 | if(vdc.dvssr_write) vdc.dvssr_write = 0; |
| 114 | | memcpy(&vdc.sprite_ram, &vdc.vram[vdc.vdc_data[DVSSR].w<<1], 512); |
| 115 | for( i = 0; i < 256; i++ ) { |
| 116 | vdc.sprite_ram[i] = ( vdc.vram[ ( vdc.vdc_data[DVSSR].w << 1 ) + i * 2 + 1 ] << 8 ) | vdc.vram[ ( vdc.vdc_data[DVSSR].w << 1 ) + i * 2 ]; |
| 117 | } |
| 115 | 118 | vdc.status |= VDC_DS; /* set satb done flag */ |
| 116 | 119 | |
| 117 | 120 | /* generate interrupt if needed */ |
| r892 | r893 | |
|---|
| 190 | 193 | /* do VRAM > SATB DMA if the enable bit is set or the DVSSR reg. was written to */ |
| 191 | 194 | if((vdc.vdc_data[DCR].w & DCR_DSR) || vdc.dvssr_write) |
| 192 | 195 | { |
| 196 | int i; |
| 193 | 197 | if(vdc.dvssr_write) vdc.dvssr_write = 0; |
| 194 | 198 | #ifdef MAME_DEBUG |
| 195 | 199 | assert(((vdc.vdc_data[DVSSR].w<<1) + 512) <= 0x10000); |
| 196 | 200 | #endif |
| 197 | | memcpy(&vdc.sprite_ram, &vdc.vram[vdc.vdc_data[DVSSR].w<<1], 512); |
| 201 | for( i = 0; i < 256; i++ ) { |
| 202 | vdc.sprite_ram[i] = ( vdc.vram[ ( vdc.vdc_data[DVSSR].w << 1 ) + i * 2 + 1 ] << 8 ) | vdc.vram[ ( vdc.vdc_data[DVSSR].w << 1 ) + i * 2 ]; |
| 203 | } |
| 204 | |
| 198 | 205 | vdc.status |= VDC_DS; /* set satb done flag */ |
| 199 | 206 | |
| 200 | 207 | /* generate interrupt if needed */ |