src/mame/machine/archimds.c
| r8794 | r8795 | |
|---|
| 53 | 53 | |
| 54 | 54 | #define CONTROL 0 |
| 55 | 55 | #define IRQ_STATUS_A 4 |
| 56 | #define IRQ_REQUEST_A 5 |
| 56 | 57 | #define IRQ_MASK_A 6 |
| 57 | 58 | #define IRQ_STATUS_B 8 |
| 59 | #define IRQ_REQUEST_B 9 |
| 58 | 60 | #define IRQ_MASK_B 10 |
| 59 | 61 | #define FIQ_STATUS 12 |
| 62 | #define FIQ_REQUEST 13 |
| 60 | 63 | #define FIQ_MASK 14 |
| 61 | 64 | |
| 62 | 65 | void archimedes_request_irq_a(running_machine *machine, int mask) |
| r8794 | r8795 | |
|---|
| 367 | 370 | case IRQ_STATUS_A: |
| 368 | 371 | return (ioc_regs[IRQ_STATUS_A] & 0x7f) | 0x80; // Force IRQ is always '1' |
| 369 | 372 | |
| 373 | case IRQ_REQUEST_A: |
| 374 | return (ioc_regs[IRQ_STATUS_A] & ioc_regs[IRQ_MASK_A]); |
| 375 | |
| 376 | case IRQ_MASK_A: |
| 377 | return (ioc_regs[IRQ_MASK_A]); |
| 378 | |
| 379 | case IRQ_STATUS_B: |
| 380 | return (ioc_regs[IRQ_STATUS_B]); |
| 381 | |
| 382 | case IRQ_REQUEST_B: |
| 383 | return (ioc_regs[IRQ_STATUS_B] & ioc_regs[IRQ_MASK_B]); |
| 384 | |
| 385 | case IRQ_MASK_B: |
| 386 | return (ioc_regs[IRQ_MASK_B]); |
| 387 | |
| 370 | 388 | case FIQ_STATUS: |
| 371 | 389 | return (ioc_regs[FIQ_STATUS] & 0x7f) | 0x80; // Force FIQ is always '1' |
| 372 | 390 | |
| 391 | case FIQ_REQUEST: |
| 392 | return (ioc_regs[FIQ_STATUS] & ioc_regs[FIQ_MASK]); |
| 393 | |
| 394 | case FIQ_MASK: |
| 395 | return (ioc_regs[FIQ_MASK]); |
| 396 | |
| 373 | 397 | case 16: // timer 0 read |
| 374 | 398 | return ioc_timerout[0]&0xff; |
| 375 | 399 | case 17: |
| r8794 | r8795 | |
|---|
| 598 | 622 | g = (val & 0x00f0) >> 4; |
| 599 | 623 | r = (val & 0x000f) >> 0; |
| 600 | 624 | |
| 625 | if(reg == 0x40 && val & 0xfff) |
| 626 | logerror("WARNING: border color write here!\n"); |
| 627 | |
| 601 | 628 | palette_set_color_rgb(space->machine, reg >> 2, pal4bit(r), pal4bit(g), pal4bit(b) ); |
| 602 | 629 | } |
| 603 | 630 | else if (reg >= 0x80 && reg <= 0xbc) |