src/mess/machine/3do.c
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| 37 | 37 | - init registers for entry to sherry |
| 38 | 38 | - jump to sherry |
| 39 | 39 | |
| 40 | - 00000934 check svf sport interface? |
| 41 | 000009cc |
| 42 | |
| 43 | svf |
| 44 | 6100 - 0110 0001 0000 0000 S = 0, A = 001 0000 0000 |
| 45 | 6900 - 0110 1001 0000 0000 |
| 46 | |
| 40 | 47 | */ |
| 41 | 48 | |
| 42 | 49 | #include "emu.h" |
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| 183 | 190 | } CLIO; |
| 184 | 191 | |
| 185 | 192 | |
| 193 | typedef struct { |
| 194 | UINT32 sport[512]; |
| 195 | UINT32 color; |
| 196 | } SVF; |
| 197 | |
| 198 | |
| 186 | 199 | static SLOW2 slow2; |
| 187 | 200 | static MADAM madam; |
| 188 | 201 | static CLIO clio; |
| 189 | | static UINT32 svf_color; |
| 202 | static SVF |
| 190 | 203 | |
| 191 | 204 | |
| 192 | 205 | READ32_HANDLER( _3do_nvarea_r ) { |
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| 270 | 283 | |
| 271 | 284 | READ32_HANDLER( _3do_svf_r ) |
| 272 | 285 | { |
| 286 | _3do_state *state = (_3do_state *)space->machine->driver_data; |
| 287 | UINT32 addr = ( offset & ( 0x07fc / 4 ) ) << 9; |
| 288 | UINT32 *p = ( addr & 0x200000 ) ? state->vram + ( addr & 0xfffff ) : state->dram + ( addr & 0xfffff ); |
| 289 | |
| 273 | 290 | logerror( "%08X: SVF read offset = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset*4 ); |
| 291 | |
| 274 | 292 | switch( offset & ( 0xE000 / 4 ) ) |
| 275 | 293 | { |
| 276 | 294 | case 0x0000/4: /* SPORT transfer */ |
| 295 | for ( int i = 0; i < 512; i++ ) |
| 296 | { |
| 297 | svf.sport[i] = p[i]; |
| 298 | } |
| 277 | 299 | break; |
| 278 | 300 | case 0x2000/4: /* Write to color register */ |
| 279 | | return svf_color; |
| 301 | return svf.color; |
| 280 | 302 | case 0x4000/4: /* Flash write */ |
| 281 | 303 | break; |
| 282 | 304 | case 0x6000/4: /* CAS before RAS refresh/reset (CBR). Used to initialize VRAM mode during boot. */ |
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| 287 | 309 | |
| 288 | 310 | WRITE32_HANDLER( _3do_svf_w ) |
| 289 | 311 | { |
| 312 | _3do_state *state = (_3do_state *)space->machine->driver_data; |
| 313 | /* Somehow we end up writing to the RAM locations for SPORT. This is probably not correct. Need to investigate the memory config setup routines */ |
| 314 | UINT32 addr = ( offset & ( 0x07fc / 4 ) ) << 9; |
| 315 | UINT32 *p = ( addr & 0x200000 ) ? state->vram + ( addr & 0xfffff ) : state->dram + ( addr & 0xfffff ); |
| 316 | |
| 290 | 317 | logerror( "%08X: SVF write offset = %08X, data = %08X, mask = %08X\n", cpu_get_pc(space->machine->device("maincpu")), offset*4, data, mem_mask ); |
| 318 | |
| 291 | 319 | switch( offset & ( 0xe000 / 4 ) ) |
| 292 | 320 | { |
| 293 | 321 | case 0x0000/4: /* SPORT transfer */ |
| 322 | for ( int i = 0; i < 512; i++ ) |
| 323 | { |
| 324 | p[i] = svf.sport[i]; |
| 325 | } |
| 294 | 326 | break; |
| 295 | 327 | case 0x2000/4: /* Write to color register */ |
| 296 | | svf_color = data; |
| 328 | svf.color = data; |
| 297 | 329 | break; |
| 298 | 330 | case 0x4000/4: /* Flash write */ |
| 331 | for ( int i = 0; i < 512; i++ ) |
| 332 | { |
| 333 | p[i] = svf.color; |
| 334 | } |
| 299 | 335 | break; |
| 300 | 336 | case 0x6000/4: /* CAS before RAS refresh/reset (CBR). Used to initialize VRAM mode during boot. */ |
| 301 | 337 | break; |
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| 645 | 681 | { |
| 646 | 682 | memset( &madam, 0, sizeof(MADAM) ); |
| 647 | 683 | madam.revision = 0x01020000; |
| 684 | madam.msysbits = 0x51; |
| 648 | 685 | } |
| 649 | 686 | |
| 650 | 687 | |
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| 665 | 702 | case 0x0030/4: |
| 666 | 703 | return clio.screen->hpos(); |
| 667 | 704 | case 0x0034/4: |
| 668 | | return clio.screen->vpos(); |
| 705 | /* This needs to moved to a proper timer callback function */ |
| 706 | if ( clio.screen->vpos() == 0 ) |
| 707 | { |
| 708 | clio.vcnt ^= 0x800; |
| 709 | } |
| 710 | return ( clio.vcnt & 0x800 ) | clio.screen->vpos(); |
| 669 | 711 | case 0x0038/4: |
| 670 | 712 | return clio.seed; |
| 671 | 713 | case 0x003c/4: |