src/mess/machine/3do.c
| r847 | r848 | |
|---|
| 2 | 2 | #include "driver.h" |
| 3 | 3 | #include "includes/3do.h" |
| 4 | 4 | |
| 5 | /* |
| 6 | registers to be located: |
| 7 | - SCOBCTL0 - Spryte engine control word |
| 8 | - REGCTL0 - Modulo for reading source frame buffer data and writing spryte image data |
| 9 | bit0 G1 = 32 for CFBD read buffer |
| 10 | bit1 Undefined, set to 0. |
| 11 | bit2 G1 = 256 for CFBD read buffer |
| 12 | bit3 G1 = 1024 for CFBD read buffer |
| 13 | bit4 G2 = 64 for CFBD read buffer |
| 14 | bit5 G2 = 128 for CFBD read buffer |
| 15 | bit6 G2 = 256 for CFBD read buffer |
| 16 | bit7 Undefined, set to 0. |
| 17 | bit8 G1 = 32 for destination buffer |
| 18 | bit9 Undefined, set to 0. |
| 19 | bit10 G1 = 256 for destination buffer |
| 20 | bit11 G1 = 1024 for destination buffer |
| 21 | bit12 G2 = 64 for destination buffer |
| 22 | bit13 G2 = 128 for destination buffer |
| 23 | bit14 G2 = 256 for destination buffer |
| 24 | bit15 Undefined, set to 0 |
| 25 | - REGCTL1 - X and Y clip values |
| 26 | bit26-16 - max Y |
| 27 | bit10-0 - max x |
| 28 | - REGCTL2 - Read base address. Address of the upper left corner pixel of the source frame buffer. |
| 29 | - REGCTL3 - Write base address. Address of the upper left corner pixel of the destination buffer. |
| 30 | - XYPOSH |
| 31 | - XYPOSL |
| 32 | - DXYH |
| 33 | - DXYL |
| 34 | - DDXYH |
| 35 | - DDXYL |
| 36 | - PPMPC |
| 37 | - pixel count register |
| 38 | |
| 39 | Spryte engine uses 8 DMA registers: |
| 40 | - 0 = current scob address |
| 41 | - 1 = next scob address |
| 42 | - 2 = pip address |
| 43 | - 3 = spryte base address |
| 44 | - 4 = engine a fetch address |
| 45 | - 5 = engine a length |
| 46 | - 6 = engine b fetch address |
| 47 | - 7 = engine b length |
| 48 | |
| 49 | Sprite engine registers: |
| 50 | - SPRSTRT - Start spryte engine (sets Spryte-ON flipflop) |
| 51 | - SPRSTOP - Stop spryte engine, everything gets reset. |
| 52 | - SPRPAUS - Pause spryte engine when it's done with the current spryte (sets pause flipflop). |
| 53 | - SPRCNTU - Continue after pause of spryte engine. |
| 54 | When interrupt is present, pause flipflop is set |
| 55 | */ |
| 56 | |
| 5 | 57 | typedef struct { |
| 6 | 58 | UINT32 revision; |
| 7 | 59 | UINT32 memory_configuration; |
| r847 | r848 | |
|---|
| 87 | 139 | } |
| 88 | 140 | |
| 89 | 141 | |
| 90 | | |
| 142 | /* |
| 143 | I think this is the spryte engine - WP |
| 144 | */ |
| 91 | 145 | READ32_HANDLER( vram_sport_r ) { |
| 92 | 146 | logerror( "%08X: VRAM SPORT read offset = %08X\n", activecpu_get_pc(), offset ); |
| 93 | 147 | switch( offset ) { |
src/mess/drivers/3do.c
| r847 | r848 | |
|---|
| 115 | 115 | AM_RANGE(0x03000000, 0x030FFFFF) AM_ROMBANK(1) /* BIOS */ |
| 116 | 116 | AM_RANGE(0x03140000, 0x0315FFFF) AM_READWRITE(nvarea_r, nvarea_w) /* NVRAM */ |
| 117 | 117 | AM_RANGE(0x03180000, 0x031FFFFF) AM_READWRITE(unk_318_r, unk_318_w) /* ???? */ |
| 118 | | AM_RANGE(0x03200000, 0x032FFFFF) AM_READWRITE(vram_sport_r, vram_sport_w) /* special vram access1 */ |
| 118 | AM_RANGE(0x03200000, 0x032FFFFF) AM_READWRITE(vram_sport_r, vram_sport_w) /* special vram access1/spryte engine? */ |
| 119 | 119 | AM_RANGE(0x03300000, 0x033FFFFF) AM_READWRITE(madam_r, madam_w) /* address decoder */ |
| 120 | 120 | AM_RANGE(0x03400000, 0x034FFFFF) AM_READWRITE(clio_r, clio_w) /* io controller */ |
| 121 | 121 | ADDRESS_MAP_END |