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r8360 Wednesday 30th June, 2010 at 19:28:57 UTC by Fabio Priuli
[NES] mapper code conversion, part 4 (last?): verified init routines and cleaned them up

[src/mess/machine]

nes_ines.c nes_mmc.c nes_pcb.c nes_unif.c

src/mess/machine/nes_pcb.c

r8359	r8360
11836	11836	int nes_pcb_reset( running_machine *machine )
11837	11837	{
11838	11838	nes_state *state = (nes_state *)machine->driver_data;
11839		int err = 0, i;
	11839	int err = 0;
11840	11840	const nes_pcb_intf *intf = nes_pcb_intf_lookup(state->pcb_id);
11841	11841
11842	11842	if (intf == NULL)
11843	11843	fatalerror("Missing PCB interface\n");
11844	11844
11845		if (state->chr_chunks == 0)
11846		chr8(machine, 0, CHRRAM);
11847		else
11848		chr8(machine, 0, CHRROM);
11849
11850		/* Here, we init a few helpers: 4 prg banks and 16 chr banks - some mappers use them */
11851		for (i = 0; i < 4; i++)
11852		state->mmc_prg_bank[i] = 0;
11853		for (i = 0; i < 16; i++)
11854		state->mmc_vrom_bank[i] = 0;
11855		for (i = 0; i < 16; i++)
11856		state->mmc_extra_bank[i] = 0;
11857
11858	11845	/* Set the mapper irq callback */
11859	11846	ppu2c0x_set_scanline_callback(state->ppu, intf ? intf->mmc_scanline : NULL);
11860	11847	ppu2c0x_set_hblank_callback(state->ppu, intf ? intf->mmc_hblank : NULL);
11861	11848
11862		/* Finally, we init IRQ-related quantities. */
11863		state->IRQ_enable = state->IRQ_enable_latch = 0;
11864		state->IRQ_count = state->IRQ_count_latch = 0;
11865		state->IRQ_toggle = 0;
11866
11867		err = unif_initialize(machine, state->pcb_id);
	11849	err = pcb_initialize(machine, state->pcb_id);
11868	11850
11869	11851	return err;
11870	11852	}

src/mess/machine/nes_unif.c

r8359	r8360
154	154	}
155	155
156	156	// WIP code
157		static int unif_initialize( running_machine *machine, int idx )
	157	static int pcb_initialize( running_machine *machine, int idx )
158	158	{
159	159	nes_state *state = (nes_state *)machine->driver_data;
160	160	int err = 0, i;
161	161
	162	/* basic PRG config */
	163	prg32(machine, 0);
	164
	165	/* some boards will not use this, but directly CHRROM (resp. CHRRAM) if the board only has VROM (resp. VRAM) */
	166	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	167	chr8(machine, 0, state->mmc_chr_source);
	168
	169	/* Here, we init a few helpers: 4 prg banks and 16 chr banks - some mappers use them */
	170	for (i = 0; i < 4; i++)
	171	state->mmc_prg_bank[i] = 0;
	172	for (i = 0; i < 16; i++)
	173	state->mmc_vrom_bank[i] = 0;
	174	for (i = 0; i < 16; i++)
	175	state->mmc_extra_bank[i] = 0;
	176
	177	state->mmc_latch1 = 0;
	178	state->mmc_latch2 = 0;
	179
	180	/* Finally, we init IRQ-related quantities. */
	181	state->IRQ_enable = state->IRQ_enable_latch = 0;
	182	state->IRQ_count = state->IRQ_count_latch = 0;
	183	state->IRQ_toggle = 0;
	184
162	185	switch (idx)
163	186	{
	187	/* many boards only needs PRG to point at first 32k and CHR at first 8k */
164	188	case STD_NROM:   // mapper 0
165	189	case HVC_FAMBASIC:
166	190	case GG_NROM:
167		prg32(machine, 0);
	191	case UXROM_CC:   // mapper 180
	192	case STD_CNROM:   // mapper 3, 185
	193	case BANDAI_PT554:
	194	case TENGEN_800008:
	195	case STD_BXROM:   // mapper 34
	196	case STD_GXROM:   // mapper 66
	197	case STD_MXROM:
	198	case BANDAI_OEKAKIDS:   // mapper 96
	199	case JALECO_JF11:   // mapper 140
	200	case JALECO_JF13:   // mapper 86
	201	case JALECO_JF19:   // mapper 92
	202	case DIS_74X377:   // mapper 11
	203	case DIS_74X161X138:   // mapper 38
	204	case CALTRON_6IN1:   // mapper 41
	205	case TXC_STRIKEWOLF:   // mapper 36
	206	case UNL_STUDYNGAME:   // mapper 39
	207	case RUMBLESTATION_BOARD:   // mapper 46
	208	case BMC_GKB:   // mapper 58
	209	case RCM_TETRISFAMILY:   // mapper 61
	210	case BMC_SUPER_700IN1:   // mapper 62
	211	case MAGICSERIES_MD:   // mapper 107
	212	case HES_BOARD:   // mapper 113
	213	case HES6IN1_BOARD:   // mapper 113
	214	case SACHEN_SA72008:   // mapper 133
	215	case SACHEN_TCU02:   // mapper 136
	216	case SACHEN_SA72007:   // mapper 145
	217	case SACHEN_TCU01:   // mapper 147
	218	case SACHEN_SA0037:   // mapper 148
	219	case SACHEN_SA0036:   // mapper 149
	220	case AGCI_50282:   // mapper 144
	221	case KAISER_KS7058:   // mapper 171
	222	case HENGEDIANZI_BOARD:   // mapper 177
	223	case WAIXING_SGZLZ:   // mapper 178
	224	case HENGEDIANZI_XJZB:   // mapper 179
	225	case BMC_21IN1:   // mapper 201
	226	case BMC_9999999IN1:   // mapper 213
	227	case RCM_GS2015:   // mapper 216
	228	case BMC_72IN1:   // mapper 225
	229	case BMC_76IN1:   // mapper 226
	230	case BMC_SUPER_42IN1:   // mapper 226
	231	case ACTENT_ACT52:   // mapper 228
	232	case CNE_SHLZ:   // mapper 240
	233	case TXC_MXMDHTWO:   // mapper 241
	234	case WAIXING_ZS:   // mapper 242
	235	case WAIXING_DQ8:   // mapper 242
	236	case CNE_DECATHLON:   // mapper 244
	237	case UNL_CC21:
	238	case BMC_VT5201:
	239	case BMC_WS:
	240	case UNL_EDU2K:
168	241	break;
	242
	243	/* other boards need additional initialization */
169	244	case STD_UXROM:   // mapper 2
170	245	case STD_UN1ROM:   // mapper 94
	246	case STD_JXROM:      // mapper 69
	247	case SUNSOFT_5B:
	248	case SUNSOFT_FME7:
	249	case NAMCOT_3425:   // mapper 95
	250	case DIS_74X139X74:   // mapper 87
	251	case DIS_74X161X161X32:   // mapper 152 & 70
	252	case BANDAI_LZ93:   // mapper 16, 157
	253	case BANDAI_LZ93EX:   // same + EEPROM
	254	case BANDAI_DATACH:
	255	case BANDAI_FCG:
	256	case IREM_HOLYDIV:   // mapper 78
	257	case IREM_G101:   // mapper 32
	258	case IREM_H3001:   // mapper 65
	259	case JALECO_SS88006:   // mapper 18
	260	case JALECO_JF16:   // mapper 78
	261	case JALECO_JF17:   // mapper 72
	262	case KONAMI_VRC1:   // mapper 75
	263	case KONAMI_VRC2:
	264	case KONAMI_VRC3:   // mapper 73
	265	case KONAMI_VRC4:
	266	case KONAMI_VRC6:
	267	case SUNSOFT_3:   // mapper 67
	268	case TAITO_TC0190FMC:   // mapper 33
	269	case TAITO_TC0190FMCP:   // mapper 48
	270	case TAITO_X1_005:   // mapper 80
	271	case TAITO_X1_005_A:   // mapper 207
	272	case TAITO_X1_017:   // mapper 82
	273	case NTDEC_ASDER:   // mapper 112
	274	case FUTUREMEDIA_BOARD:   // mapper 117
	275	case BTL_DRAGONNINJA:   // mapper 222
	276	case WAIXING_SGZ:   // mapper 252
	277	case UNL_T230:
	278	case BMC_NTD_03:
	279	case KAISER_KS7022:
	280	case UNL_SHJY3:
	281	case KAISER_KS7017:
	282	case KAISER_KS7032:
	283	case KAISER_KS202:
171	284	prg16_89ab(machine, 0);
172	285	prg16_cdef(machine, state->prg_chunks - 1);
173	286	break;
174		case UXROM_CC:   // mapper 180
175		prg32(machine, 0);
176		break;
177		case STD_CNROM:   // mapper 3, 185
178		case BANDAI_PT554:
179		case TENGEN_800008:
180		prg32(machine, 0);
181		break;
	287
182	288	case STD_CPROM:   // mapper 13
183	289	chr4_0(machine, 0, CHRRAM);
184	290	chr4_4(machine, 0, CHRRAM);
185		prg32(machine, 0);
186	291	break;
187	292	case STD_AXROM:   // mapper 7
188	293	set_nt_mirroring(machine, PPU_MIRROR_LOW);
189		prg32(machine, 0);
190	294	break;
191		case STD_BXROM:   // mapper 34
192		prg32(machine, 0);
193		break;
194		case STD_GXROM:   // mapper 66
195		case STD_MXROM:
196		prg32(machine, 0);
197		break;
198	295	case STD_SXROM:   // mapper 1, 155
199	296	case STD_SOROM:
200	297	case STD_SXROM_A:
201	298	case STD_SOROM_A:
202		state->mmc_latch1 = 0;
203	299	state->mmc_count = 0;
204	300	state->mmc_reg[0] = 0x0f;
205	301	state->mmc_reg[1] = state->mmc_reg[2] = state->mmc_reg[3] = 0;
206	302	state->mmc1_reg_write_enable = 1;
207	303	set_nt_mirroring(machine, PPU_MIRROR_HORZ);
208		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
209	304	mmc1_set_chr(machine);
210	305	mmc1_set_prg(machine);
211	306	wram_bank(machine, 0, (idx == STD_SOROM) ? NES_WRAM : NES_BATTERY);
r8359	r8360
255	350	state->mmc_latch2 = 0x80;
256	351	state->mmc_prg_base = state->mmc_chr_base = 0;
257	352	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;   // these could be init'ed as xxx_chunks-1 and they would work the same
258		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
259	353	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
260	354	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
261	355	break;
r8359	r8360
268	362	state->mmc_latch2 = 0;
269	363	state->mmc_prg_base = state->mmc_chr_base = 0;
270	364	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;   // these could be init'ed as xxx_chunks-1 and they would work the same
271		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
272	365	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
273	366	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
274	367	break;
r8359	r8360
281	374	state->mmc_prg_base = state->mmc_chr_base = 0;
282	375	state->mmc_prg_mask = 0x07;
283	376	state->mmc_chr_mask = 0x7f;
284		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
285	377	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
286	378	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
287	379	break;
r8359	r8360
294	386	state->mmc_prg_base = state->mmc_chr_base = 0;
295	387	state->mmc_prg_mask = 0x0f;
296	388	state->mmc_chr_mask = 0x7f;
297		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
298	389	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
299	390	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
300	391	break;
r8359	r8360
306	397	state->mmc5_vram_control = 0;
307	398	state->mmc5_split_scr = 0;
308	399	memset(state->MMC5_vrom_bank, 0, ARRAY_LENGTH(state->MMC5_vrom_bank));
309		state->mid_ram_enable = 0;
310	400	state->mmc5_prg_mode = 3;
311	401	state->mmc5_last_chr_a = 1;
312	402	state->mmc5_prg_regs[0] = 0xfc;
r8359	r8360
320	410	break;
321	411	case STD_NXROM:      // mapper 68
322	412	case SUNSOFT_DCS:      // mapper 68
323		state->mmc_reg[0] = state->mmc_latch1 = state->mmc_latch2 = 0;
	413	state->mmc_reg[0] = 0;
324	414	prg16_89ab(machine, 0);
325	415	prg16_cdef(machine, state->prg_chunks - 1);
326	416	break;
327		case STD_JXROM:      // mapper 69
328		case SUNSOFT_5B:
329		case SUNSOFT_FME7:
330		prg16_89ab(machine, 0);
331		prg16_cdef(machine, state->prg_chunks - 1);
332		break;
333	417	case NAMCOT_34X3:   // mapper 88
334	418	case STD_DXROM:   // mapper 206
335	419	case STD_DRROM:
r8359	r8360
352	436	chr2_2(machine, 1, CHRROM);
353	437	chr2_4(machine, 2, CHRROM);
354	438	chr2_6(machine, 3, CHRROM);
355		state->mmc_latch1 = 0;
356	439	break;
357		case NAMCOT_3425:   // mapper 95
358		prg16_89ab(machine, 0);
359		prg16_cdef(machine, state->prg_chunks - 1);
360		break;
361		case DIS_74X377:   // mapper 11
362		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;   // NINA-07 has no CHRROM
363		prg32(machine, 0);
364		break;
365		case DIS_74X139X74:   // mapper 87
366		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
367		prg16_89ab(machine, 0);
368		prg16_cdef(machine, state->prg_chunks - 1);
369		break;
370		case DIS_74X161X138:   // mapper 38
371		prg32(machine, 0);
372		break;
373		case DIS_74X161X161X32:   // mapper 152 & 70
374		prg16_89ab(machine, 0);
375		prg16_cdef(machine, state->prg_chunks - 1);
376		if (state->chr_chunks)
377		chr8(machine, 0, CHRROM);
378		break;
379		case BANDAI_LZ93:   // mapper 16, 157
380		case BANDAI_LZ93EX:   // same + EEPROM
381		case BANDAI_DATACH:
382		state->mmc_latch1 = 0;
383		prg16_89ab(machine, 0);
384		prg16_cdef(machine, state->prg_chunks - 1);
385		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
386		break;
387	440	case BANDAI_JUMP2:   // mapper 153
388	441	for (i = 0; i < 8; i++)
389	442	state->mmc_reg[i] = 0;
390		state->mmc_latch1 = 0;
391	443	prg16_89ab(machine, 0);
392	444	prg16_cdef(machine, state->prg_chunks - 1);
393		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
394	445	fjump2_set_prg(machine);
395	446	break;
396		case BANDAI_FCG:
397		state->mmc_latch1 = 0;
398		prg16_89ab(machine, 0);
399		prg16_cdef(machine, state->prg_chunks - 1);
400		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
401		break;
402		case BANDAI_OEKAKIDS:   // mapper 96
403		prg32(machine, 0);
404		break;
405	447	case BANDAI_KARAOKE:   // mapper 188
406	448	prg16_89ab(machine, 0);
407	449	prg16_cdef(machine, (state->prg_chunks - 1) ^ 0x08);
408	450	break;
409	451	case IREM_LROG017:   // mapper 77
410		prg32(machine, 0);
411	452	chr2_2(machine, 0, CHRROM);
412	453	chr2_4(machine, 1, CHRROM);
413	454	chr2_6(machine, 2, CHRROM);
414	455	break;
415		case IREM_HOLYDIV:   // mapper 78
416		prg16_89ab(machine, 0);
417		prg16_cdef(machine, state->prg_chunks - 1);
418		break;
419	456	case IREM_TAM_S1:   // mapper 97
420	457	prg16_89ab(machine, state->prg_chunks - 1);
421	458	prg16_cdef(machine, 0);
422	459	break;
423		case IREM_G101:
424		state->mmc_latch1 = 0;
425		prg16_89ab(machine, 0);
426		prg16_89ab(machine, 0);
427		prg16_cdef(machine, state->prg_chunks - 1);
428		break;
429		case IREM_H3001:   // mapper 65
430		prg16_89ab(machine, 0);
431		prg16_cdef(machine, state->prg_chunks - 1);
432		break;
433		case JALECO_SS88006:   // mapper 18
434		state->mmc_latch1 = 0;
435		prg16_89ab(machine, 0);
436		prg16_cdef(machine, state->prg_chunks - 1);
437		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
438		break;
439		case JALECO_JF11:   // mapper 140
440		case JALECO_JF13:   // mapper 86
441		case JALECO_JF19:   // mapper 92
442		prg32(machine, 0);
443		break;
444		case JALECO_JF16:   // mapper 78
445		case JALECO_JF17:   // mapper 72
446		prg16_89ab(machine, 0);
447		prg16_cdef(machine, state->prg_chunks - 1);
448		break;
449		case KONAMI_VRC1:   // mapper 75
450		case KONAMI_VRC2:
451		case KONAMI_VRC3:   // mapper 73
452		case KONAMI_VRC4:
453		case KONAMI_VRC6:
454		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
455		prg16_89ab(machine, 0);
456		prg16_cdef(machine, state->prg_chunks - 1);
457		break;
458	460	case KONAMI_VRC7:   // mapper 85
459		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
460	461	prg8_89(machine, 0);
461	462	prg8_ab(machine, 0);
462	463	prg8_cd(machine, 0);
463	464	prg8_ef(machine, 0xff);
464	465	break;
465	466	case NAMCOT_163:   // mapper 19
466		state->mmc_latch1 = 0;
467	467	prg16_89ab(machine, 0);
468	468	prg16_cdef(machine, state->prg_chunks - 1);
469		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
470	469	set_nt_mirroring(machine, PPU_MIRROR_VERT);
471	470	break;
472	471	case SUNSOFT_1:   // mapper 184
r8359	r8360
476	475	if (!state->hard_mirroring)
477	476	set_nt_mirroring(machine, PPU_MIRROR_LOW);
478	477	break;
479		case SUNSOFT_3:   // mapper 67
480		prg16_89ab(machine, 0);
481		prg16_cdef(machine, state->prg_chunks - 1);
482		break;
483		case TAITO_TC0190FMC:   // mapper 33
484		case TAITO_TC0190FMCP:   // mapper 48
485		case TAITO_X1_005:   // mapper 80
486		case TAITO_X1_005_A:   // mapper 207
487		case TAITO_X1_017:   // mapper 82
488		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
489		prg16_89ab(machine, 0);
490		prg16_cdef(machine, state->prg_chunks - 1);
491		break;
	478
492	479	// mapper 14
493	480	case REXSOFT_SL1632:
494	481	state->mmc_extra_bank[2] = 0xfe;
r8359	r8360
502	489	state->mmc_latch2 = 0x80;
503	490	state->mmc_prg_base = state->mmc_chr_base = 0;
504	491	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
505		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
506	492	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
507	493	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
508	494	break;
509	495	// mapper 15
510	496	case WAIXING_PS2:
511	497	set_nt_mirroring(machine, PPU_MIRROR_VERT);
512		prg32(machine, 0);
513	498	break;
514	499
515	500	// mapper 35
516	501	case UNL_SC127:
	502	// mapper 42
	503	case BTL_MARIOBABY:
	504	case BTL_AISENSHINICOL:
517	505	prg32(machine, 0xff);
518	506	break;
519	507
520		// mapper 36
521		case TXC_STRIKEWOLF:
522		break;
523	508	// mapper 40
524	509	case BTL_SMB2A:
525	510	prg8_67(machine, 0xfe);
r8359	r8360
528	513	prg8_cd(machine, 0xfe);
529	514	prg8_ef(machine, 0xff);
530	515	break;
531		// mapper 41
532		case CALTRON_6IN1:
533		state->mmc_latch1 = 0;
534		prg32(machine, 0);
535		break;
536		// mapper 42
537		case BTL_MARIOBABY:
538		case BTL_AISENSHINICOL:
539		prg32(machine, state->prg_chunks - 1);
540		break;
	516
541	517	// mapper 43
542	518	case UNL_SMB2J:
543		prg32(machine, 0);
544	519	if (state->battery)
545	520	memset(state->battery_ram, 0x2000, 0xff);
546	521	else if (state->prg_ram)
r8359	r8360
557	532	state->mmc_prg_base = state->mmc_chr_base = 0;
558	533	state->mmc_prg_mask = 0x0f;
559	534	state->mmc_chr_mask = 0x7f;
560		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
561	535	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
562	536	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
563	537	break;
r8359	r8360
567	541	state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
568	542	state->mmc_latch1 = 0;
569	543	state->mmc_latch2 = 0x80;
570		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
571	544	state->mapper45_reg[0] = state->mapper45_reg[1] = state->mapper45_reg[2] = state->mapper45_reg[3] = 0;
572	545	state->mmc_prg_base = 0;
573	546	state->mmc_prg_mask = 0x3f;
r8359	r8360
576	549	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
577	550	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
578	551	break;
579		// mapper 46
580		case RUMBLESTATION_BOARD:
581		prg32(machine, 0);
582		chr8(machine, 0, CHRROM);
583		break;
	552
	553	// mapper 50
584	554	case BTL_SMB2B:
585	555	prg8_67(machine, 0x0f);
586	556	prg8_89(machine, 0x08);
r8359	r8360
603	573	state->mmc_latch1 = 0;
604	574	state->mmc_latch2 = 0x80;
605	575	state->map52_reg_written = 0;
606		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
607	576	state->mmc_prg_base = 0;
608	577	state->mmc_prg_mask = 0x1f;
609	578	state->mmc_chr_base = 0;
r8359	r8360
613	582	break;
614	583	// mapper 54
615	584	case BMC_NOVELDIAMOND:
616		prg32(machine, 0);
617		chr8(machine, 0, CHRROM);
618	585	set_nt_mirroring(machine, PPU_MIRROR_VERT);
619	586	break;
620	587	// mapper 57
621	588	case BMC_GKA:
622		state->mmc_latch1 = 0x00;
623		state->mmc_latch2 = 0x00;
624	589	prg16_89ab(machine, 0);
625	590	prg16_cdef(machine, 0);
626		chr8(machine, 0, CHRROM);
627	591	break;
628		// mapper 58
629		case BMC_GKB:
630		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
631		prg32(machine, 0);
632		chr8(machine, 0, state->mmc_chr_source);
633		break;
634		// mapper 61
635		case RCM_TETRISFAMILY:
636		prg32(machine, 0);
637		break;
638		// mapper 62
639		case BMC_SUPER_700IN1:
640		prg32(machine, 0);
641		break;
	592
642	593	// mapper 64
643	594	case TENGEN_800032:
644	595	// mapper 158
645	596	case TENGEN_800037:
646		state->mmc_latch1 = 0;
647	597	prg16_89ab(machine, state->prg_chunks - 1);
648	598	prg16_cdef(machine, state->prg_chunks - 1);
649	599	break;
r8359	r8360
657	607	// mapper 79 (& 146)
658	608	case AVE_NINA06:
659	609	set_nt_mirroring(machine, PPU_MIRROR_HORZ);
660		chr8(machine, 0, CHRROM);
661		prg32(machine, 0);
662	610	break;
663	611
664	612	// mapper 83
665	613	case CONY_BOARD:
666		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
667	614	state->mapper83_reg[9] = 0x0f;
668	615	prg8_cd(machine, 0x1e);
669	616	prg8_ef(machine, 0x1f);
r8359	r8360
688	635	prg8_cd(machine, 0);
689	636	prg8_ef(machine, (state->prg_chunks << 1) - 1);
690	637	break;
691		// mapper 107
692		case MAGICSERIES_MD:
693		prg32(machine, 0);
694		break;
695		// mapper 112
696		case NTDEC_ASDER:
697		state->mmc_latch1 = 0;
698		prg16_89ab(machine, 0);
699		prg16_cdef(machine, state->prg_chunks - 1);
700		break;
701		// mapper 113
702		case HES_BOARD:
703		case HES6IN1_BOARD:
704		prg32(machine, 0);
705		break;
	638
706	639	// mapper 114
707	640	case SUPERGAME_LIONKING:
708	641	state->map114_reg = state->map114_reg_enabled = 0;
r8359	r8360
712	645	state->mmc_latch2 = 0x80;
713	646	state->mmc_prg_base = state->mmc_chr_base = 0;
714	647	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
715		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
716	648	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
717	649	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
718	650	break;
r8359	r8360
725	657	state->mmc_latch2 = 0x80;
726	658	state->mmc_prg_base = state->mmc_chr_base = 0;
727	659	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
728		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
729	660	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
730	661	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
731	662	break;
732	663	// mapper 116
733	664	//      case SOMERITEAM_SL12:
734		//          mapper_initialize(machine, 116);
735	665	//          break;
736		// mapper 117
737		case FUTUREMEDIA_BOARD:
738		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
739		prg16_89ab(machine, 0);
740		prg16_cdef(machine, state->prg_chunks - 1);
741		break;
	666
742	667	// mapper 121
743	668	case KAY_PANDAPRINCE:
744		#if 0
745	669	state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
746	670	state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
747	671	state->mapper121_reg[0] = state->mapper121_reg[1] = state->mapper121_reg[2] = 0;
748		state->mapper121_reg[3] = 0;
749		state->mapper121_reg[4] = state->mapper121_reg[5] = state->mapper121_reg[6] = 0;
750	672	state->mmc_latch1 = 0;
751	673	state->mmc_latch2 = 0x80;
752	674	state->mmc_prg_base = state->mmc_chr_base = 0;
753	675	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
754		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
755		kay_pp_update_reg(machine);
756		kay_pp_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
757		kay_pp_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
758		#endif
759		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
760		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
761		state->mapper121_reg[0] = state->mapper121_reg[1] = state->mapper121_reg[2] = 0;
762		state->mmc_latch1 = 0;
763		state->mmc_latch2 = 0x80;
764		state->mmc_prg_base = state->mmc_chr_base = 0;
765		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
766		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
767	676	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
768	677	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
769	678	break;
r8359	r8360
774	683	// mapper 173
775	684	case TXC_22211C:
776	685	state->txc_reg[0] = state->txc_reg[1] = state->txc_reg[2] = state->txc_reg[3] = 0;
777		prg32(machine, 0);
778	686	break;
779		// mapper 133
780		case SACHEN_SA72008:
781		// mapper 145
782		case SACHEN_SA72007:
783		// mapper 147
784		case SACHEN_TCU01:
785		// mapper 148
786		case SACHEN_SA0037:
787		// mapper 149
788		case SACHEN_SA0036:
789		prg32(machine, 0);
790		chr8(machine, 0, CHRROM);
791		break;
	687
792	688	// mapper 134
793	689	case BMC_FAMILY_4646B:
794	690	state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
r8359	r8360
798	694	state->mmc_prg_base = state->mmc_chr_base = 0;
799	695	state->mmc_prg_mask = 0x1f;
800	696	state->mmc_chr_mask = 0xff;
801		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
802	697	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
803	698	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
804	699	break;
805		// mapper 136
806		case SACHEN_TCU02:
807		state->mmc_latch1 = 0;
808		prg32(machine, 0);
809		break;
	700
810	701	// mapper 137
811	702	case SACHEN_8259D:
812		state->mmc_latch1 = 0;
813		prg32(machine, 0);
814	703	chr8(machine, state->chr_chunks - 1, CHRROM);
815	704	set_nt_mirroring(machine, PPU_MIRROR_VERT);
816	705	break;
r8359	r8360
820	709	case SACHEN_8259C:
821	710	// mapper 141
822	711	case SACHEN_8259A:
823		state->mmc_latch1 = 0;
824		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
825		prg32(machine, 0);
826		chr8(machine, 0, state->mmc_chr_source);
	712	// mapper 150
	713	case SACHEN_74LS374:
827	714	set_nt_mirroring(machine, PPU_MIRROR_VERT);
828	715	break;
829	716	// mapper 143
830	717	case SACHEN_TCA01:
831	718	prg16_89ab(machine, 0);
832	719	prg16_cdef(machine, 1);
833		chr8(machine, 0, CHRROM);
834	720	break;
835		// mapper 144
836		case AGCI_50282:
837		prg32(machine, 0);
838		break;
839		// mapper 150
840		case SACHEN_74LS374:
841		state->mmc_latch1 = 0;
842		prg32(machine, 0);
843		chr8(machine, 0, CHRROM);
844		set_nt_mirroring(machine, PPU_MIRROR_VERT);
845		break;
	721
846	722	// mapper 156
847	723	case OPENCORP_DAOU306:
848	724	prg16_89ab(machine, state->prg_chunks - 2);
r8359	r8360
854	730	state->mmc_count = 0xff;
855	731	state->mmc_reg[0] = 0xff;
856	732	state->mmc_reg[1] = 0;
857		state->mmc_latch1 = 0;
858		state->mmc_latch2 = 0;
859	733	prg16_89ab(machine, state->prg_chunks - 2);
860	734	prg16_cdef(machine, state->prg_chunks - 1);
861	735	break;
862	736	// mapper 164
863	737	case WAIXING_FFV:
864	738	prg32(machine, 0xff);
865		state->mid_ram_enable = 1;
866	739	break;
867	740	// mapper 166
868	741	case SUBOR_TYPE1:
r8359	r8360
876	749	prg16_89ab(machine, 0);
877	750	prg16_cdef(machine, 0x20);
878	751	break;
879		// mapper 171
880		case KAISER_KS7058:
881		prg32(machine, 0);
882		chr8(machine, 0, CHRROM);
883		break;
	752
884	753	// mapper 176
885	754	case UNL_XZY:
886		prg32(machine, (state->prg_chunks - 1) >> 1);
887		break;
888		// mapper 177
889		case HENGEDIANZI_BOARD:
890		prg32(machine, 0);
891		break;
892		// mapper 178
893		case WAIXING_SGZLZ:
894		state->mmc_latch1 = 0;
895		prg32(machine, 0);
896		break;
897		// mapper 179
898		case HENGEDIANZI_XJZB:
899		prg32(machine, 0);
900		break;
901	755	// mapper 182
902	756	case HOSENKAN_BOARD:
903	757	prg32(machine, (state->prg_chunks - 1) >> 1);
r8359	r8360
912	766	state->mmc_latch2 = 0x80;
913	767	state->mmc_prg_base = state->mmc_chr_base = 0;
914	768	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
915		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
916	769	kof96_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
917	770	kof96_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
918	771	break;
r8359	r8360
922	775	state->mmc_latch2 = 0x80;
923	776	state->mmc_chr_base = 0;
924	777	state->mmc_chr_mask = 0xff;
925		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
926		prg32(machine, 0);
927	778	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
928	779	break;
929	780	// mapper 193
r8359	r8360
939	790	state->mmc_latch2 = 0x80;
940	791	state->mmc_prg_base = state->mmc_chr_base = 0;
941	792	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
942		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
943	793	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
944	794	unl_sf3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
945	795	break;
r8359	r8360
953	803	state->mmc_latch2 = 0x80;
954	804	state->mmc_prg_base = state->mmc_chr_base = 0;
955	805	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
956		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
957	806	waixing_f_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
958	807	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
959	808	break;
r8359	r8360
967	816	state->mmc_latch2 = 0x80;
968	817	state->mmc_prg_base = state->mmc_chr_base = 0;
969	818	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
970		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
971	819	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
972	820	waixing_g_set_chr(machine, state->mmc_chr_base, state->mmc_chr_mask);
973	821	break;
r8359	r8360
976	824	prg16_89ab(machine, state->prg_chunks - 1);
977	825	prg16_cdef(machine, state->prg_chunks - 1);
978	826	break;
979		// mapper 201
980		case BMC_21IN1:
981		prg32(machine, 0);
982		chr8(machine, 0, CHRROM);
983		break;
	827
984	828	// mapper 202
985	829	case BMC_150IN1:
986	830	// mapper 203
r8359	r8360
991	835	case BMC_SUPERGUN_20IN1:
992	836	prg16_89ab(machine, 0);
993	837	prg16_cdef(machine, 0);
994		chr8(machine, 0, CHRROM);
995	838	break;
996	839	// mapper 205
997	840	case BMC_15IN1:
r8359	r8360
1003	846	state->mmc_prg_mask = 0x1f;
1004	847	state->mmc_chr_base = 0;
1005	848	state->mmc_chr_mask = 0xff;
1006		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1007	849	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1008	850	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1009	851	break;
r8359	r8360
1017	859	state->mmc_latch2 = 0x80;
1018	860	state->mmc_prg_base = state->mmc_chr_base = 0;
1019	861	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
1020		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1021	862	mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1022	863	mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1023	864	break;
r8359	r8360
1026	867	chr8(machine, 0xff, CHRROM);
1027	868	prg32(machine, 0xff);
1028	869	break;
1029		// mapper 213
1030		case BMC_9999999IN1:
1031		prg32(machine, 0);
1032		chr8(machine, 0, CHRROM);
1033		break;
	870
1034	871	// mapper 215
1035	872	case SUPERGAME_BOOGERMAN:
1036	873	state->mmc_prg_bank[0] = 0x00;
r8359	r8360
1045	882	state->map215_reg[3] = 0;
1046	883	state->mmc_prg_base = 0;
1047	884	state->mmc_prg_mask = 0x1f;
1048		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1049	885	sgame_boog_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1050	886	sgame_boog_set_chr(machine, state->mmc_chr_source);
1051	887	break;
1052		// mapper 216
1053		case RCM_GS2015:
1054		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1055		prg32(machine, 0);
1056		chr8(machine, 0, state->mmc_chr_source);
1057		break;
	888
1058	889	// mapper 217
1059	890	case BMC_GOLDENCARD_6IN1:
1060	891	state->map217_reg[0] = 0x00;
r8359	r8360
1067	898	state->mmc_latch2 = 0x80;
1068	899	state->mmc_prg_base = state->mmc_chr_base = 0;
1069	900	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
1070		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1071	901	bmc_gc6in1_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1072	902	bmc_gc6in1_set_chr(machine, state->mmc_chr_source);
1073	903	break;
1074	904	// mapper 221
1075	905	case UNL_N625092:
1076		state->mmc_latch1 = 0;
1077		state->mmc_latch2 = 0;
1078	906	prg16_89ab(machine, 0);
1079	907	prg16_cdef(machine, 0);
1080	908	break;
1081		// mapper 222
1082		case BTL_DRAGONNINJA:
1083		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1084		prg16_89ab(machine, 0);
1085		prg16_cdef(machine, state->prg_chunks - 1);
1086		break;
1087		// mapper 225
1088		case BMC_72IN1:
1089		prg32(machine, 0);
1090		break;
1091		// mapper 226
1092		case BMC_76IN1:
1093		case BMC_SUPER_42IN1:
1094		state->mmc_latch1 = 0;
1095		state->mmc_latch2 = 0;
1096		prg32(machine, 0);
1097		break;
	909
1098	910	// mapper 227
1099	911	case BMC_1200IN1:
1100	912	prg16_89ab(machine, 0);
1101	913	prg16_cdef(machine, 0);
1102	914	break;
1103		// mapper 228
1104		case ACTENT_ACT52:
1105		chr8(machine, 0, CHRROM);
1106		prg32(machine, 0);
1107		break;
	915
1108	916	// mapper 229
1109	917	case BMC_31IN1:
1110	918	prg16_89ab(machine, 0);
1111	919	prg16_cdef(machine, 1);
1112		chr8(machine, 0, CHRROM);
1113	920	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1114	921	break;
1115	922	// mapper 230
r8359	r8360
1129	936	state->mmc_latch2 = 0x00;
1130	937	bf9096_set_prg(machine);
1131	938	break;
1132		// mapper 240
1133		case CNE_SHLZ:
1134		prg32(machine, 0);
1135		break;
1136		// mapper 241
1137		case TXC_MXMDHTWO:
1138		prg32(machine, 0);
1139		break;
1140		// mapper 242
1141		case WAIXING_ZS:
1142		case WAIXING_DQ8:
1143		prg32(machine, 0);
1144		break;
	939
1145	940	// mapper 243
1146	941	case SACHEN_74LS374_A:
1147	942	state->mmc_vrom_bank[0] = 3;
1148		state->mmc_latch1 = 0;
1149	943	chr8(machine, 3, CHRROM);
1150		prg32(machine, 0);
1151	944	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1152	945	break;
1153		// mapper 244
1154		case CNE_DECATHLON:
1155		prg32(machine, 0);
1156		break;
	946
1157	947	// mapper 246
1158	948	case CNE_FSB:
1159	949	prg32(machine, 0xff);
r8359	r8360
1167	957	state->map249_reg = 0;
1168	958	state->mmc_prg_base = state->mmc_chr_base = 0;
1169	959	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
1170		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1171	960	waixing_sec_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1172	961	waixing_sec_set_chr(machine, state->mmc_chr_base, state->mmc_chr_mask);
1173	962	break;
1174		// mapper 252
1175		case WAIXING_SGZ:
1176		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1177		prg16_89ab(machine, 0);
1178		prg16_cdef(machine, state->prg_chunks - 1);
1179		break;
	963
1180	964	// mapper 255
1181	965	case BMC_110IN1:
1182	966	prg16_89ab(machine, 0);
1183	967	prg16_cdef(machine, 1);
1184		chr8(machine, 0, CHRROM);
1185	968	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1186	969	break;
1187	970
r8359	r8360
1192	975	state->bmc_64in1nr_reg[2] = state->bmc_64in1nr_reg[3] = 0;
1193	976	bmc_64in1nr_set_prg(machine);
1194	977	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1195		chr8(machine, 0, CHRROM);
1196	978	break;
1197	979	case BMC_190IN1:
1198	980	prg16_89ab(machine, 0);
1199	981	prg16_cdef(machine, 0);
1200		chr8(machine, 0, CHRROM);
1201	982	break;
1202	983	case BMC_A65AS:
1203	984	prg16_89ab(machine, 0);
r8359	r8360
1207	988	case BMC_GS2004:
1208	989	case BMC_GS2013:
1209	990	prg32(machine, 0xff);
1210		chr8(machine, 0, CHRRAM);
1211	991	break;
1212	992	case BMC_S24IN1SC03:
1213	993	state->bmc_s24in1sc03_reg[0] = 0x24;
r8359	r8360
1228	1008	prg16_89ab(machine, 0);
1229	1009	prg16_cdef(machine, 7);
1230	1010	break;
1231		case BMC_WS:
1232		state->mmc_latch1 = 0;
1233		prg32(machine, 0);
1234		break;
1235	1011	case DREAMTECH_BOARD:
1236	1012	prg16_89ab(machine, 0);
1237	1013	prg16_cdef(machine, 8);
1238		chr8(machine, 0, CHRRAM);
1239	1014	break;
1240	1015	case UNL_8237:
1241	1016	state->unl_8237_reg[0] = state->unl_8237_reg[1] = state->unl_8237_reg[2] = 0;
r8359	r8360
1256	1031	prg8_cd(machine, 0xfe);
1257	1032	prg8_ef(machine, 0xff);
1258	1033	break;
1259		case UNL_CC21:
1260		prg32(machine, 0);
1261		chr8(machine, 0, CHRROM);
1262		break;
1263		case UNL_T230:
1264		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1265		prg16_89ab(machine, 0);
1266		prg16_cdef(machine, state->prg_chunks - 1);
1267		break;
1268	1034	case UNL_RACERMATE:
1269		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1270	1035	chr4_0(machine, 0, state->mmc_chr_source);
1271	1036	chr4_4(machine, 0, state->mmc_chr_source);
1272	1037	prg16_89ab(machine, 0);
1273	1038	prg16_cdef(machine, state->prg_chunks - 1);
1274	1039	break;
1275	1040
1276		case BMC_VT5201:
1277		prg32(machine, 0);
1278		chr8(machine, 0, CHRROM);
1279		break;
1280
1281	1041	case BMC_BENSHENG_BS5:
1282	1042	state->mmc_prg_bank[0] = 0xff;
1283	1043	state->mmc_prg_bank[1] = 0xff;
r8359	r8360
1289	1049	case BMC_810544:
1290	1050	prg16_89ab(machine, 0);
1291	1051	prg16_cdef(machine, 0);
1292		chr8(machine, 0, CHRROM);
1293	1052	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1294	1053	break;
1295	1054
1296		case BMC_NTD_03:
1297		prg16_89ab(machine, 0);
1298		prg16_cdef(machine, state->prg_chunks - 1);
1299		chr8(machine, 0, CHRROM);
1300		break;
1301
1302		case UNL_EDU2K:
1303		break;
1304
1305		case KAISER_KS7022:
1306		prg16_89ab(machine, 0);
1307		prg16_cdef(machine, state->prg_chunks - 1);
1308		break;
1309
1310	1055	case BMC_G63IN1:
1311	1056	bmc_gb63_update(machine);
1312	1057	break;
1313	1058
1314		case UNL_SHJY3:
	1059	case FFE_MAPPER6:
1315	1060	prg16_89ab(machine, 0);
1316		prg16_cdef(machine, state->prg_chunks - 1);
	1061	prg16_cdef(machine, 7);
1317	1062	break;
1318
1319		case KAISER_KS7017:
1320		prg16_89ab(machine, 0);
1321		prg16_cdef(machine, state->prg_chunks - 1);
	1063	case FFE_MAPPER8:
	1064	prg32(machine, 0);
1322	1065	break;
1323
1324		case KAISER_KS7032:
1325		case KAISER_KS202:
	1066	case FFE_MAPPER17:
1326	1067	prg16_89ab(machine, 0);
1327	1068	prg16_cdef(machine, state->prg_chunks - 1);
1328		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1329		chr8(machine, 0, state->mmc_chr_source);
1330	1069	break;
1331
	1070
1332	1071	case UNSUPPORTED_BOARD:
1333	1072	default:
1334	1073	/* Mapper not supported */

src/mess/machine/nes_mmc.c

r8359	r8360
137	137	#define LOG_MMC(x) do { if (VERBOSE) logerror x; } while (0)
138	138	#define LOG_FDS(x) do { if (VERBOSE) logerror x; } while (0)
139	139
140		static int unif_initialize( running_machine *machine, int idx );
	140	static int pcb_initialize( running_machine *machine, int idx );
141	141
142	142	static void ffe_irq( running_device *device, int scanline, int vblank, int blanked );
143	143	static WRITE8_HANDLER( mapper6_l_w );

src/mess/machine/nes_ines.c

r8359	r8360
54	54	switch (offset)
55	55	{
56	56	case 0x1fe:
57		state->mmc_cmd1 = data & 0x80;
	57	state->mmc_latch1 = data & 0x80;
58	58	set_nt_mirroring(space->machine, BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
59	59	break;
60	60	case 0x1ff:
r8359	r8360
79	79	nes_state *state = (nes_state *)space->machine->driver_data;
80	80	LOG_MMC(("mapper6_w, offset: %04x, data: %02x\n", offset, data));
81	81
82		if (!state->mmc_cmd1)   // when in "FFE mode" we are forced to use CHRRAM/EXRAM bank?
	82	if (!state->mmc_latch1)   // when in "FFE mode" we are forced to use CHRRAM/EXRAM bank?
83	83	{
84	84	prg16_89ab(space->machine, data >> 2);
85	85	// chr8(space->machine, data & 0x03, ???);
86		// due to lack of info on the exact behavior, we simply act as if mmc_cmd=1
	86	// due to lack of info on the exact behavior, we simply act as if mmc_latch1=1
87	87	if (state->mmc_chr_source == CHRROM)
88	88	chr8(space->machine, data & 0x03, CHRROM);
89	89	}
r8359	r8360
1308	1308
1309	1309	return mmc->pcb_id;
1310	1310	}
1311
1312		/*************************************************************
1313
1314		mapper_initialize
1315
1316		Initialize various constants needed by mappers, depending
1317		on the mapper number. As long as the code is mainly iNES
1318		centric, also UNIF images will call this function to
1319		initialize their bankswitch and registers.
1320
1321		*************************************************************/
1322		#if 0
1323		static int mapper_initialize( running_machine *machine, int mmc_num )
1324		{
1325		nes_state *state = (nes_state *)machine->driver_data;
1326		int err = 0, i;
1327
1328		switch (mmc_num)
1329		{
1330		case 0:
1331		err = 1; /* No mapper found */
1332		prg32(machine, 0);
1333		break;
1334		case 1:
1335		case 155:
1336		state->mmc_cmd1 = 0;
1337		state->mmc_count = 0;
1338		state->MMC1_regs[0] = 0x0f;
1339		state->MMC1_regs[1] = state->MMC1_regs[2] = state->MMC1_regs[3] = 0;
1340		set_nt_mirroring(machine, PPU_MIRROR_HORZ);
1341		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1342		mmc1_set_chr(machine);
1343		mmc1_set_prg(machine);
1344		break;
1345		case 2:
1346		/* These games don't switch VROM, but some ROMs incorrectly have CHR chunks */
1347		state->chr_chunks = 0;
1348		prg16_89ab(machine, 0);
1349		prg16_cdef(machine, state->prg_chunks - 1);
1350		break;
1351		case 13:
1352		chr4_0(machine, 0, CHRRAM);
1353		prg32(machine, 0);
1354		break;
1355		case 3:
1356		case 185:
1357		prg32(machine, 0);
1358		break;
1359		case 4:
1360		case 206:
1361		/* Only MMC3 and clones seem to use 4-screen! */
1362		/* hardware uses an 8K RAM chip, but can't address the high 4K! */
1363		/* that much is documented for Nintendo Gauntlet boards */
1364		if (state->four_screen_vram)
1365		{
1366		set_nt_page(machine, 0, CART_NTRAM, 0, 1);
1367		set_nt_page(machine, 1, CART_NTRAM, 1, 1);
1368		set_nt_page(machine, 2, CART_NTRAM, 2, 1);
1369		set_nt_page(machine, 3, CART_NTRAM, 3, 1);
1370		}
1371		case 12:
1372		case 74:
1373		case 118:
1374		case 119:
1375		case 191:
1376		case 192:
1377		case 194:
1378		case 195:
1379		case 196:
1380		case 245:
1381		case 250:
1382		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;   // prg_bank[2] & prg_bank[3] remain always the same in most MMC3 variants
1383		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;   // but some pirate clone mappers change them after writing certain registers
1384		state->mmc_cmd1 = 0;
1385		state->mmc_cmd2 = 0x80;
1386		state->mmc_prg_base = state->mmc_chr_base = 0;
1387		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;   // these could be init'ed as xxx_chunks-1 and they would work the same
1388		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1389		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1390		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1391		break;
1392		case 5:
1393		/* Can switch 8k prg banks, but they are saved as 16k in size */
1394		state->MMC5_rom_bank_mode = 3;
1395		state->MMC5_vrom_bank_mode = 0;
1396		state->MMC5_vram_protect = 0;
1397		state->mmc5_high_chr = 0;
1398		state->mmc5_vram_control = 0;
1399		state->mmc5_split_scr = 0;
1400		memset(state->MMC5_vrom_bank, 0, ARRAY_LENGTH(state->MMC5_vrom_bank));
1401		state->mid_ram_enable = 0;
1402		prg16_89ab(machine, state->prg_chunks - 2);
1403		prg16_cdef(machine, state->prg_chunks - 1);
1404		break;
1405		case 6:
1406		state->mmc_cmd1 = 0;
1407		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1408		prg16_89ab(machine, 0);
1409		prg16_cdef(machine, 7);
1410		break;
1411		case 7:
1412		/* Bankswitches 32k at a time */
1413		set_nt_mirroring(machine, PPU_MIRROR_LOW);
1414		prg16_89ab(machine, 0);
1415		prg16_cdef(machine, state->prg_chunks - 1);
1416		break;
1417		case 8:
1418		case 96:
1419		prg32(machine, 0);
1420		break;
1421		case 9:
1422		state->MMC2_regs[0] = state->MMC2_regs[2] = 0;
1423		state->MMC2_regs[1] = state->MMC2_regs[3] = 0;
1424		state->mmc_cmd1 = state->mmc_cmd2 = 0xfe;
1425		prg8_89(machine, 0);
1426		//ugly hack to deal with iNES header usage of chunk count.
1427		prg8_ab(machine, (state->prg_chunks << 1) - 3);
1428		prg8_cd(machine, (state->prg_chunks << 1) - 2);
1429		prg8_ef(machine, (state->prg_chunks << 1) - 1);
1430		break;
1431		case 10:
1432		/* Reset VROM latches */
1433		state->MMC2_regs[0] = state->MMC2_regs[2] = 0;
1434		state->MMC2_regs[1] = state->MMC2_regs[3] = 0;
1435		state->mmc_cmd1 = state->mmc_cmd2 = 0xfe;
1436		prg16_89ab(machine, 0);
1437		prg16_cdef(machine, state->prg_chunks - 1);
1438		break;
1439		case 11:
1440		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;   // NINA-07 has no CHRROM
1441		prg32(machine, 0);
1442		break;
1443		case 14:
1444		state->mmc_extra_bank[2] = 0xfe;
1445		state->mmc_extra_bank[3] = 0xff;
1446		state->mmc_extra_bank[0] = state->mmc_extra_bank[1] = state->mmc_extra_bank[4] = state->mmc_extra_bank[5] = state->mmc_extra_bank[6] = 0;
1447		state->mmc_extra_bank[7] = state->mmc_extra_bank[8] = state->mmc_extra_bank[9] = state->mmc_extra_bank[0xa] = state->mmc_extra_bank[0xb] = 0;
1448		state->map14_reg[0] = state->map14_reg[1] = 0;
1449		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1450		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
1451		state->mmc_cmd1 = 0;
1452		state->mmc_cmd2 = 0x80;
1453		state->mmc_prg_base = state->mmc_chr_base = 0;
1454		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
1455		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1456		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1457		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1458		break;
1459		case 15:
1460		set_nt_mirroring(machine, PPU_MIRROR_VERT);
1461		prg32(machine, 0);
1462		break;
1463		case 16:
1464		case 17:
1465		case 18:
1466		case 157:
1467		case 159:
1468		state->mmc_cmd1 = 0;
1469		prg16_89ab(machine, 0);
1470		prg16_cdef(machine, state->prg_chunks - 1);
1471		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1472		break;
1473		case 19:
1474		state->mmc_cmd1 = 0;
1475		prg16_89ab(machine, 0);
1476		prg16_cdef(machine, state->prg_chunks - 1);
1477		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1478		set_nt_mirroring(machine, PPU_MIRROR_VERT);
1479		break;
1480		case 21:
1481		case 22:
1482		case 23:
1483		case 24:
1484		case 25:
1485		case 26:
1486		case 33:
1487		case 48:
1488		case 73:
1489		case 75:
1490		case 80:
1491		case 82:
1492		case 85:
1493		case 87:
1494		case 117:
1495		case 207:
1496		case 222:
1497		case 252:
1498		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1499		prg16_89ab(machine, 0);
1500		prg16_cdef(machine, state->prg_chunks - 1);
1501		break;
1502		case 32:
1503		state->mmc_cmd1 = 0;
1504		prg16_89ab(machine, 0);
1505		prg16_cdef(machine, state->prg_chunks - 1);
1506		if (state->crc_hack)
1507		set_nt_mirroring(machine, PPU_MIRROR_HIGH);  // needed by Major League
1508		break;
1509		case 34:
1510		prg32(machine, 0);
1511		break;
1512		case 35:
1513		prg32(machine, 0xff);
1514		break;
1515		case 37:
1516		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1517		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
1518		state->mmc_cmd1 = 0;
1519		state->mmc_cmd2 = 0x80;
1520		state->mmc_prg_base = state->mmc_chr_base = 0;
1521		state->mmc_prg_mask = 0x07;
1522		state->mmc_chr_mask = 0x7f;
1523		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1524		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1525		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1526		break;
1527		case 40:
1528		prg8_67(machine, 0xfe);
1529		prg8_89(machine, 0xfc);
1530		prg8_ab(machine, 0xfd);
1531		prg8_cd(machine, 0xfe);
1532		prg8_ef(machine, 0xff);
1533		break;
1534		case 41:
1535		state->mmc_cmd1 = 0;
1536		prg32(machine, 0);
1537		break;
1538		case 42:
1539		prg32(machine, state->prg_chunks - 1);
1540		break;
1541		case 43:
1542		prg32(machine, 0);
1543		if (state->battery)
1544		memset(state->battery_ram, 0x2000, 0xff);
1545		else if (state->prg_ram)
1546		memset(state->wram, 0x2000, 0xff);
1547		break;
1548		case 44:
1549		case 47:
1550		case 49:
1551		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1552		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
1553		state->mmc_cmd1 = 0;
1554		state->mmc_cmd2 = 0x80;
1555		state->mmc_prg_base = state->mmc_chr_base = 0;
1556		state->mmc_prg_mask = 0x0f;
1557		state->mmc_chr_mask = 0x7f;
1558		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1559		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1560		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1561		break;
1562		case 45:
1563		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1564		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
1565		state->mmc_cmd1 = 0;
1566		state->mmc_cmd2 = 0x80;
1567		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1568		state->mapper45_reg[0] = state->mapper45_reg[1] = state->mapper45_reg[2] = state->mapper45_reg[3] = 0;
1569		state->mmc_prg_base = 0x30;
1570		state->mmc_prg_mask = 0x3f;
1571		state->mmc_chr_base = 0;
1572		state->mmc_chr_mask = 0x7f;
1573		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1574		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1575		//          memory_set_bankptr(machine, "bank5", state->wram);
1576		break;
1577		case 46:
1578		prg32(machine, 0);
1579		chr8(machine, 0, CHRROM);
1580		break;
1581		case 54:
1582		prg32(machine, 0);
1583		chr8(machine, 0, CHRROM);
1584		set_nt_mirroring(machine, PPU_MIRROR_VERT);
1585		break;
1586		case 50:
1587		prg8_67(machine, 0x0f);
1588		prg8_89(machine, 0x08);
1589		prg8_ab(machine, 0x09);
1590		prg8_cd(machine, 0);
1591		prg8_ef(machine, 0x0b);
1592		break;
1593		case 51:
1594		state->mapper51_reg[0] = 0x01;
1595		state->mapper51_reg[1] = 0x00;
1596		bmc_ball11_set_banks(machine);
1597		break;
1598		case 52:
1599		state->mmc_prg_bank[0] = 0xfe;
1600		state->mmc_prg_bank[2] = 0xfe;
1601		state->mmc_prg_bank[1] = 0xff;
1602		state->mmc_prg_bank[3] = 0xff;
1603		state->mmc_cmd1 = 0;
1604		state->mmc_cmd2 = 0x80;
1605		state->map52_reg_written = 0;
1606		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1607		state->mmc_prg_base = 0;
1608		state->mmc_prg_mask = 0x1f;
1609		state->mmc_chr_base = 0;
1610		state->mmc_chr_mask = 0xff;
1611		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1612		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1613		//          memory_set_bankptr(machine, "bank5", state->wram);
1614		break;
1615		case 57:
1616		state->mmc_cmd1 = 0x00;
1617		state->mmc_cmd2 = 0x00;
1618		prg16_89ab(machine, 0);
1619		prg16_cdef(machine, 0);
1620		chr8(machine, 0, CHRROM);
1621		break;
1622		case 58:
1623		prg32(machine, 0);
1624		chr8(machine, 0, CHRROM);
1625		break;
1626		case 61:
1627		case 62:
1628		case 86:
1629		prg32(machine, 0);
1630		break;
1631		case 64:
1632		case 158:
1633		state->mmc_cmd1 = 0;
1634		prg16_89ab(machine, state->prg_chunks - 1);
1635		prg16_cdef(machine, state->prg_chunks - 1);
1636		break;
1637		case 65:
1638		case 67:
1639		case 69:
1640		case 72:
1641		case 78:
1642		case 92:
1643		prg16_89ab(machine, 0);
1644		prg16_cdef(machine, state->prg_chunks - 1);
1645		break;
1646		case 68:
1647		state->m68_mirror = state->m0 = state->m1 = 0;
1648		prg16_89ab(machine, 0);
1649		prg16_cdef(machine, state->prg_chunks - 1);
1650		break;
1651		case 70:
1652		prg16_89ab(machine, state->prg_chunks - 2);
1653		prg16_cdef(machine, state->prg_chunks - 1);
1654		break;
1655		case 71:
1656		set_nt_mirroring(machine, PPU_MIRROR_HORZ);
1657		prg16_89ab(machine, 0);
1658		prg16_cdef(machine, state->prg_chunks - 1);
1659		break;
1660		case 76:
1661		prg8_89(machine, 0);
1662		prg8_ab(machine, 1);
1663		//cd is bankable, but this should init all banks just fine.
1664		prg16_cdef(machine, state->prg_chunks - 1);
1665		chr2_0(machine, 0, CHRROM);
1666		chr2_2(machine, 1, CHRROM);
1667		chr2_4(machine, 2, CHRROM);
1668		chr2_6(machine, 3, CHRROM);
1669		state->mmc_cmd1 = 0;
1670		break;
1671		case 77:
1672		prg32(machine, 0);
1673		chr2_2(machine, 0, CHRROM);
1674		chr2_4(machine, 1, CHRROM);
1675		chr2_6(machine, 2, CHRROM);
1676		break;
1677		case 79:
1678		case 146:
1679		/* Mirroring always horizontal...? */
1680		//          Mirroring = 1;
1681		set_nt_mirroring(machine, PPU_MIRROR_HORZ);
1682		chr8(machine, 0, CHRROM);
1683		prg32(machine, 0);
1684		break;
1685		case 228:
1686		chr8(machine, 0, CHRROM);
1687		prg32(machine, 0);
1688		break;
1689		case 83:
1690		state->mapper83_reg[9] = 0x0f;
1691		prg8_cd(machine, 0x1e);
1692		prg8_ef(machine, 0x1f);
1693		break;
1694		case 88:
1695		prg8_89(machine, 0xc);
1696		prg8_ab(machine, 0xd);
1697		prg8_cd(machine, 0xe);
1698		prg8_ef(machine, 0xf);
1699		break;
1700		case 89:
1701		prg16_89ab(machine, 0);
1702		prg16_cdef(machine, state->prg_chunks - 1);
1703		set_nt_mirroring(machine, PPU_MIRROR_LOW);
1704		break;
1705		case 91:
1706		set_nt_mirroring(machine, PPU_MIRROR_VERT);
1707		prg16_89ab(machine, state->prg_chunks - 1);
1708		prg16_cdef(machine, state->prg_chunks - 1);
1709		break;
1710		case 93:
1711		case 94:
1712		case 95:
1713		case 101:
1714		prg16_89ab(machine, 0);
1715		prg16_cdef(machine, state->prg_chunks - 1);
1716		break;
1717		case 97:
1718		prg16_89ab(machine, state->prg_chunks - 1);
1719		prg16_cdef(machine, state->prg_chunks - 1);
1720		break;
1721		case 112:
1722		state->mmc_cmd1 = 0;
1723		prg16_89ab(machine, 0);
1724		prg16_cdef(machine, state->prg_chunks - 1);
1725		break;
1726		case 36:
1727		case 38:
1728		case 39:
1729		case 66:
1730		case 107:
1731		case 113:
1732		case 177:
1733		case 179:
1734		case 184:
1735		case 140:
1736		case 144:
1737		case 240:
1738		case 241:
1739		case 242:
1740		case 244:
1741		prg32(machine, 0);
1742		break;
1743		case 104:
1744		prg16_89ab(machine, 0x00);
1745		prg16_cdef(machine, 0x0f);
1746		break;
1747		case 106:
1748		prg8_89(machine, (state->prg_chunks << 1) - 1);
1749		prg8_ab(machine, 0);
1750		prg8_cd(machine, 0);
1751		prg8_ef(machine, (state->prg_chunks << 1) - 1);
1752		break;
1753		case 114:
1754		state->map114_reg = state->map114_reg_enabled = 0;
1755		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1756		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
1757		state->mmc_cmd1 = 0;
1758		state->mmc_cmd2 = 0x80;
1759		state->mmc_prg_base = state->mmc_chr_base = 0;
1760		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
1761		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1762		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1763		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1764		break;
1765		case 115:
1766		state->mapper115_reg[0] = 0;
1767		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1768		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
1769		state->mmc_cmd1 = 0;
1770		state->mmc_cmd2 = 0x80;
1771		state->mmc_prg_base = state->mmc_chr_base = 0;
1772		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
1773		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1774		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1775		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1776		break;
1777		case 121:
1778		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1779		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
1780		state->mapper121_reg[0] = state->mapper121_reg[1] = state->mapper121_reg[2] = 0;
1781		state->mmc_cmd1 = 0;
1782		state->mmc_cmd2 = 0x80;
1783		state->mmc_prg_base = state->mmc_chr_base = 0;
1784		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
1785		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1786		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1787		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1788		break;
1789		case 132:
1790		case 172:
1791		case 173:
1792		state->txc_reg[0] = state->txc_reg[1] = state->txc_reg[2] = state->txc_reg[3] = 0;
1793		prg32(machine, 0);
1794		break;
1795		case 134:
1796		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1797		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
1798		state->mmc_cmd1 = 0;
1799		state->mmc_cmd2 = 0x80;
1800		state->mmc_prg_base = state->mmc_chr_base = 0;
1801		state->mmc_prg_mask = 0x1f;
1802		state->mmc_chr_mask = 0xff;
1803		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1804		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1805		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1806		break;
1807		case 166:
1808		state->subor_reg[0] = state->subor_reg[1] = state->subor_reg[2] = state->subor_reg[3] = 0;
1809		prg16_89ab(machine, 0);
1810		prg16_cdef(machine, 0x07);
1811		break;
1812		case 167:
1813		state->subor_reg[0] = state->subor_reg[1] = state->subor_reg[2] = state->subor_reg[3] = 0;
1814		prg16_89ab(machine, 0);
1815		prg16_cdef(machine, 0x20);
1816		break;
1817		case 136:
1818		state->mmc_cmd1 = 0;
1819		prg32(machine, 0);
1820		break;
1821		case 137:
1822		state->mmc_cmd1 = 0;
1823		prg32(machine, 0);
1824		chr8(machine, state->chr_chunks - 1, CHRROM);
1825		set_nt_mirroring(machine, PPU_MIRROR_VERT);
1826		break;
1827		case 138:
1828		case 139:
1829		case 141:
1830		state->mmc_cmd1 = 0;
1831		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1832		prg32(machine, 0);
1833		chr8(machine, 0, state->mmc_chr_source);
1834		set_nt_mirroring(machine, PPU_MIRROR_VERT);
1835		break;
1836		case 143:
1837		prg16_89ab(machine, 0);
1838		prg16_cdef(machine, 1);
1839		chr8(machine, 0, CHRROM);
1840		break;
1841		case 133:
1842		case 145:
1843		case 147:
1844		case 148:
1845		case 149:
1846		case 171:
1847		prg32(machine, 0);
1848		chr8(machine, 0, CHRROM);
1849		break;
1850		case 150:
1851		state->mmc_cmd1 = 0;
1852		prg32(machine, 0);
1853		chr8(machine, 0, CHRROM);
1854		set_nt_mirroring(machine, PPU_MIRROR_VERT);
1855		break;
1856		case 152:
1857		prg16_89ab(machine, 0);
1858		prg16_cdef(machine, state->prg_chunks - 1);
1859		chr8(machine, 0, CHRROM);
1860		break;
1861		case 153:
1862		state->mmc_cmd1 = 0;
1863		prg16_89ab(machine, 0);
1864		prg16_cdef(machine, state->prg_chunks - 1);
1865		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1866		// Famicom Jump II needs also the following!
1867		for (i = 0; i < 8; i++)
1868		state->map153_reg[i] = 0;
1869
1870		state->map153_bank_latch = 0;
1871		if (state->crc_hack)
1872		fjump2_set_prg(machine);
1873		break;
1874		case 154:
1875		prg16_89ab(machine, state->prg_chunks - 2);
1876		prg16_cdef(machine, state->prg_chunks - 1);
1877		break;
1878		case 156:
1879		prg16_89ab(machine, state->prg_chunks - 2);
1880		prg16_cdef(machine, state->prg_chunks - 1);
1881		set_nt_mirroring(machine, PPU_MIRROR_LOW);
1882		break;
1883		case 164:
1884		prg32(machine, 0xff);
1885		state->mid_ram_enable = 1;
1886		break;
1887		case 176:
1888		prg32(machine, (state->prg_chunks - 1) >> 1);
1889		break;
1890		case 178:
1891		state->mmc_cmd1 = 0;
1892		prg32(machine, 0);
1893		break;
1894		case 180:
1895		prg16_89ab(machine, 0);
1896		prg16_cdef(machine, 0);
1897		break;
1898		case 182:
1899		prg32(machine, (state->prg_chunks - 1) >> 1);
1900		break;
1901		case 188:
1902		prg16_89ab(machine, 0);
1903		prg16_cdef(machine, (state->prg_chunks - 1) ^ 0x08);
1904		break;
1905		case 187:
1906		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1907		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
1908		state->mapper187_reg[0] = state->mapper187_reg[1] = state->mapper187_reg[2] = state->mapper187_reg[3] = 0;
1909		state->mmc_cmd1 = 0;
1910		state->mmc_cmd2 = 0x80;
1911		state->mmc_prg_base = state->mmc_chr_base = 0;
1912		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
1913		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1914		kof96_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1915		kof96_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1916		break;
1917		case 189:
1918		state->mmc_cmd1 = 0;
1919		state->mmc_cmd2 = 0x80;
1920		state->mmc_chr_base = 0;
1921		state->mmc_chr_mask = 0xff;
1922		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1923		prg32(machine, 0);
1924		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1925		break;
1926		case 193:
1927		prg32(machine, (state->prg_chunks - 1) >> 1);
1928		set_nt_mirroring(machine, PPU_MIRROR_VERT);
1929		break;
1930		case 197:
1931		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1932		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
1933		state->mmc_cmd1 = 0;
1934		state->mmc_cmd2 = 0x80;
1935		state->mmc_prg_base = state->mmc_chr_base = 0;
1936		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
1937		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1938		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1939		unl_sf3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1940		break;
1941		case 198:
1942		state->mmc_prg_bank[0] = 0x00;
1943		state->mmc_prg_bank[1] = 0x01;
1944		state->mmc_prg_bank[2] = 0x4e;
1945		state->mmc_prg_bank[3] = 0x4f;
1946		state->mmc_cmd1 = 0;
1947		state->mmc_cmd2 = 0x80;
1948		state->mmc_prg_base = state->mmc_chr_base = 0;
1949		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
1950		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1951		waixing_f_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1952		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1953		break;
1954		case 199:
1955		state->mmc_prg_bank[0] = 0x00;
1956		state->mmc_prg_bank[1] = 0x01;
1957		state->mmc_prg_bank[2] = 0x3e;
1958		state->mmc_prg_bank[3] = 0x3f;
1959		state->mmc_cmd1 = 0;
1960		state->mmc_cmd2 = 0x80;
1961		state->mmc_prg_base = state->mmc_chr_base = 0;
1962		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
1963		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1964		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1965		waixing_g_set_chr(machine, state->mmc_chr_base, state->mmc_chr_mask);
1966		break;
1967		case 200:
1968		prg16_89ab(machine, state->prg_chunks - 1);
1969		prg16_cdef(machine, state->prg_chunks - 1);
1970		break;
1971		case 201:
1972		case 213:
1973		prg32(machine, 0);
1974		chr8(machine, 0, CHRROM);
1975		break;
1976		case 202:
1977		case 203:
1978		case 204:
1979		case 214:
1980		prg16_89ab(machine, 0);
1981		prg16_cdef(machine, 0);
1982		chr8(machine, 0, CHRROM);
1983		break;
1984		case 205:
1985		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1986		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
1987		state->mmc_cmd1 = 0;
1988		state->mmc_cmd2 = 0x80;
1989		state->mmc_prg_base = 0x10;
1990		state->mmc_prg_mask = 0x1f;
1991		state->mmc_chr_base = 0;
1992		state->mmc_chr_mask = 0xff;
1993		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1994		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
1995		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1996		break;
1997		case 208:
1998		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
1999		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
2000		state->map208_reg[0] = state->map208_reg[1] = state->map208_reg[2] = state->map208_reg[3] = state->map208_reg[4] = 0;
2001		state->mmc_cmd1 = 0;
2002		state->mmc_cmd2 = 0x80;
2003		state->mmc_prg_base = state->mmc_chr_base = 0;
2004		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
2005		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
2006		mmc3_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
2007		mmc3_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
2008		break;
2009		case 212:
2010		chr8(machine, 0xff, CHRROM);
2011		prg32(machine, 0xff);
2012		break;
2013		case 215:
2014		state->mmc_prg_bank[0] = 0x00;
2015		state->mmc_prg_bank[2] = 0xfe;
2016		state->mmc_prg_bank[1] = 0x01;
2017		state->mmc_prg_bank[3] = 0xff;
2018		state->mmc_cmd1 = 0;
2019		state->mmc_cmd2 = 0x80;
2020		state->map215_reg[0] = 0x00;
2021		state->map215_reg[1] = 0xff;
2022		state->map215_reg[2] = 0x04;
2023		state->map215_reg[3] = 0;
2024		state->mmc_prg_base = 0;
2025		state->mmc_prg_mask = 0x1f;
2026		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
2027		sgame_boog_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
2028		sgame_boog_set_chr(machine, state->mmc_chr_source);
2029		break;
2030		case 216:
2031		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
2032		prg32(machine, 0);
2033		chr8(machine, 0, state->mmc_chr_source);
2034		break;
2035		case 217:
2036		state->map217_reg[0] = 0x00;
2037		state->map217_reg[1] = 0xff;
2038		state->map217_reg[2] = 0x03;
2039		state->map217_reg[3] = 0;
2040		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
2041		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
2042		state->mmc_cmd1 = 0;
2043		state->mmc_cmd2 = 0x80;
2044		state->mmc_prg_base = state->mmc_chr_base = 0;
2045		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
2046		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
2047		bmc_gc6in1_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
2048		bmc_gc6in1_set_chr(machine, state->mmc_chr_source);
2049		break;
2050		case 221:
2051		state->mmc_cmd1 = 0;
2052		state->mmc_cmd2 = 0;
2053		prg16_89ab(machine, 0);
2054		prg16_cdef(machine, 0);
2055		break;
2056		case 225:
2057		prg32(machine, 0);
2058		break;
2059		case 226:
2060		state->mmc_cmd1 = 0;
2061		state->mmc_cmd2 = 0;
2062		prg32(machine, 0);
2063		break;
2064		case 227:
2065		prg16_89ab(machine, 0);
2066		prg16_cdef(machine, 0);
2067		break;
2068		case 229:
2069		case 255:
2070		prg16_89ab(machine, 0);
2071		prg16_cdef(machine, 1);
2072		chr8(machine, 0, CHRROM);
2073		set_nt_mirroring(machine, PPU_MIRROR_VERT);
2074		break;
2075		case 230:
2076		prg16_89ab(machine, 0);
2077		prg16_cdef(machine, 7);
2078		break;
2079		case 231:
2080		prg16_89ab(machine, 0);
2081		prg16_cdef(machine, state->prg_chunks - 1);
2082		set_nt_mirroring(machine, PPU_MIRROR_VERT);
2083		break;
2084		case 232:
2085		state->mmc_cmd1 = 0x18;
2086		state->mmc_cmd2 = 0x00;
2087		bf9096_set_prg(machine);
2088		break;
2089		case 243:
2090		state->mmc_vrom_bank[0] = 3;
2091		state->mmc_cmd1 = 0;
2092		chr8(machine, 3, CHRROM);
2093		prg32(machine, 0);
2094		set_nt_mirroring(machine, PPU_MIRROR_VERT);
2095		break;
2096		case 246:
2097		prg32(machine, 0xff);
2098		break;
2099		case 249:
2100		state->mmc_prg_bank[0] = state->mmc_prg_bank[2] = 0xfe;
2101		state->mmc_prg_bank[1] = state->mmc_prg_bank[3] = 0xff;
2102		state->mmc_cmd1 = 0;
2103		state->mmc_cmd2 = 0x80;
2104		state->map249_reg = 0;
2105		state->mmc_prg_base = state->mmc_chr_base = 0;
2106		state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
2107		state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
2108		waixing_sec_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
2109		waixing_sec_set_chr(machine, state->mmc_chr_base, state->mmc_chr_mask);
2110		break;
2111		default:
2112		/* Mapper not supported */
2113		err = 2;
2114		break;
2115		}
2116
2117		return err;
2118		}
2119		#endif

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