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r8331 Sunday 27th June, 2010 at 11:59:24 UTC by Fabio Priuli
[NES] added preliminary emulation of some more board (e.g. NTD-03 used by the recently ASDER 20-in-1 dump)
[src/mame/video]ppu2c0x.c ppu2c0x.h
[src/mess/includes]nes.h
[src/mess/machine]nes.c nes_mmc.h nes_pcb.c nes_unif.c

src/mame/video/ppu2c0x.c
r8330r8331
12371237   return ppu2c0x->scanline;
12381238}
12391239
1240// MMC5 has to be able to check this
1241int ppu2c0x_is_sprite_8x16( running_device *device )
1242{
1243   ppu2c0x_state *ppu2c0x = get_token(device);
1244   return BIT(ppu2c0x->regs[0], 5);
1245}
1246
12401247void ppu2c0x_set_scanline_callback( running_device *device, ppu2c0x_scanline_cb cb )
12411248{
12421249   ppu2c0x_state *ppu2c0x = get_token(device);
src/mame/video/ppu2c0x.h
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113113int ppu2c0x_get_pixel( running_device *device, int x, int y ) ATTR_NONNULL(1);
114114int ppu2c0x_get_colorbase( running_device *device ) ATTR_NONNULL(1);
115115int ppu2c0x_get_current_scanline( running_device *device ) ATTR_NONNULL(1);
116int ppu2c0x_is_sprite_8x16( running_device *device ) ATTR_NONNULL(1);
116117void ppu2c0x_set_scanline_callback( running_device *device, ppu2c0x_scanline_cb cb ) ATTR_NONNULL(1);
117118void ppu2c0x_set_hblank_callback( running_device *device, ppu2c0x_scanline_cb cb ) ATTR_NONNULL(1);
118119void ppu2c0x_set_vidaccess_callback( running_device *device, ppu2c0x_vidaccess_cb cb ) ATTR_NONNULL(1);
src/mess/machine/nes_pcb.c
r8330r8331
494494   { "WHIRLWIND-2706",   UNSUPPORTED_BOARD },
495495   { "UNL-H2288",        UNSUPPORTED_BOARD },   // mapper 123
496496   { "UNL-DANCE",        UNSUPPORTED_BOARD },
497   { "UNL-EDU2000",      UNSUPPORTED_BOARD /*UNL_EDU2K*/ },
497   { "UNL-EDU2000",      UNL_EDU2K },
498498   { "UNL-SHERO",        UNSUPPORTED_BOARD /*SACHEN_SHERO*/ },
499499   { "UNL-TF1201",       UNSUPPORTED_BOARD /*UNL_TF1201*/ },
500500   { "RUMBLESTATION",    RUMBLESTATION_BOARD },   // mapper 46
r8330r8331
574574   { "BMC-411120-C",        UNSUPPORTED_BOARD },
575575   { "BMC-830118C",         UNSUPPORTED_BOARD },
576576   { "BMC-12-IN-1",         UNSUPPORTED_BOARD },
577   { "BMC-NTD-03",          UNSUPPORTED_BOARD },
577   { "BMC-NTD-03",          BMC_NTD_03 },
578578   { "BMC-8157",            UNSUPPORTED_BOARD /*BMC_8157*/ },
579579   { "BMC-BS-5",            BMC_BENSHENG_BS5 },
580580   { "BMC-FK23C",           UNSUPPORTED_BOARD /*BMC_FK23C*/ },
581581   { "BMC-FK23CA",          UNSUPPORTED_BOARD /*BMC_FK23C*/ },   // diff reg init
582   { "BMC-GHOSTBUSTERS63IN1", UNSUPPORTED_BOARD /*BMC_G63IN1*/ },
582   { "BMC-GHOSTBUSTERS63IN1", BMC_G63IN1 },
583583   { "BMC-SUPERVISION16IN1", UNSUPPORTED_BOARD },   // mapper 53
584584   { "BMC-RESETBASED-4IN1", UNSUPPORTED_BOARD },// mapper 60 with 64k prg and 32k chr
585585   { "BMC-VT5201",          BMC_VT5201 },// mapper 60 otherwise
r8330r8331
638638
639639************************************************/
640640
641// helper function for the few mappers reading from 0x8000-0xffff for protection
642INLINE UINT8 mmc_hi_access_rom( running_machine *machine, UINT32 offset )
643{
644   nes_state *state = (nes_state *)machine->driver_data;
641645
646   // usual ROM access
647   switch (offset & 0x6000)
648   {
649      case 0x0000:
650         return state->rom[0x10000 + state->prg_bank[0] * 0x2000 + (offset & 0x1fff)];
651      case 0x2000:
652         return state->rom[0x10000 + state->prg_bank[1] * 0x2000 + (offset & 0x1fff)];
653      case 0x4000:
654         return state->rom[0x10000 + state->prg_bank[2] * 0x2000 + (offset & 0x1fff)];
655      case 0x6000:
656         return state->rom[0x10000 + state->prg_bank[3] * 0x2000 + (offset & 0x1fff)];
657   }
658   return 0;
659}
660
642661/*************************************************************
643662
644663 UxROM board emulation
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15751594
15761595 *************************************************************/
15771596
1597#if 0
1598static void mmc5_update_chr_a( running_machine *machine )
1599{
1600   nes_state *state = (nes_state *)machine->driver_data;
1601   switch (state->mmc5_chr_mode)
1602   {
1603      case 0:   // 8k banks
1604         chr8(machine, state->mmc5_vrom_regA[7] & 0xff, CHRROM);
1605         break;
1606         
1607      case 1:   // 4k banks
1608         chr4_0(machine, state->mmc5_vrom_regA[3] & 0xff, CHRROM);
1609         chr4_4(machine, state->mmc5_vrom_regA[7] & 0xff, CHRROM);
1610         break;
1611         
1612      case 2:   // 2k banks
1613         chr2_0(machine, state->mmc5_vrom_regA[1], CHRROM);
1614         chr2_2(machine, state->mmc5_vrom_regA[3], CHRROM);
1615         chr2_4(machine, state->mmc5_vrom_regA[5], CHRROM);
1616         chr2_6(machine, state->mmc5_vrom_regA[7], CHRROM);
1617         break;
1618         
1619      case 3:   // 1k banks
1620         chr1_0(machine, state->mmc5_vrom_regA[0], CHRROM);
1621         chr1_1(machine, state->mmc5_vrom_regA[1], CHRROM);
1622         chr1_2(machine, state->mmc5_vrom_regA[2], CHRROM);
1623         chr1_3(machine, state->mmc5_vrom_regA[3], CHRROM);
1624         chr1_4(machine, state->mmc5_vrom_regA[4], CHRROM);
1625         chr1_5(machine, state->mmc5_vrom_regA[5], CHRROM);
1626         chr1_6(machine, state->mmc5_vrom_regA[6], CHRROM);
1627         chr1_7(machine, state->mmc5_vrom_regA[7], CHRROM);
1628         break;
1629   }
1630}
1631
1632static void mmc5_update_chr_b( running_machine *machine )
1633{
1634   nes_state *state = (nes_state *)machine->driver_data;
1635   switch (state->mmc5_chr_mode)
1636   {
1637      case 0:   // 8k banks
1638         chr8(machine, state->mmc5_vrom_regB[3] & 0xff, CHRROM);
1639         break;
1640         
1641      case 1:   // 4k banks
1642         chr4_0(machine, state->mmc5_vrom_regB[3] & 0xff, CHRROM);
1643         chr4_4(machine, state->mmc5_vrom_regB[3] & 0xff, CHRROM);
1644         break;
1645         
1646      case 2:   // 2k banks
1647         chr2_0(machine, state->mmc5_vrom_regB[1], CHRROM);
1648         chr2_2(machine, state->mmc5_vrom_regB[3], CHRROM);
1649         chr2_4(machine, state->mmc5_vrom_regB[1], CHRROM);
1650         chr2_6(machine, state->mmc5_vrom_regB[3], CHRROM);
1651         break;
1652         
1653      case 3:   // 1k banks
1654         chr1_0(machine, state->mmc5_vrom_regB[0], CHRROM);
1655         chr1_1(machine, state->mmc5_vrom_regB[1], CHRROM);
1656         chr1_2(machine, state->mmc5_vrom_regB[2], CHRROM);
1657         chr1_3(machine, state->mmc5_vrom_regB[3], CHRROM);
1658         chr1_4(machine, state->mmc5_vrom_regB[0], CHRROM);
1659         chr1_5(machine, state->mmc5_vrom_regB[1], CHRROM);
1660         chr1_6(machine, state->mmc5_vrom_regB[2], CHRROM);
1661         chr1_7(machine, state->mmc5_vrom_regB[3], CHRROM);
1662         break;
1663   }
1664}
1665#endif
1666
1667static void mmc5_update_prg( running_machine *machine )
1668{
1669   nes_state *state = (nes_state *)machine->driver_data;
1670   int bank1, bank2, bank3;
1671   
1672   switch (state->mmc5_prg_mode)
1673   {
1674      case 0:   // 32k banks
1675         prg32(machine, state->mmc5_prg_regs[3] >> 2);
1676         break;
1677         
1678      case 1:   // 16k banks
1679         //          printf("problema 1: %x\n", state->mmc5_prg_regs[1]);
1680         bank1 = state->mmc5_prg_regs[1];
1681         
1682         if (!BIT(bank1, 7))
1683         {
1684            state->prg_bank[0] = state->prg_chunks + (bank1 & 0x06);
1685            state->prg_bank[1] = state->prg_chunks + (bank1 & 0x06) + 1;
1686            memory_set_bank(machine, "bank1", state->prg_bank[0]);
1687            memory_set_bank(machine, "bank2", state->prg_bank[1]);
1688         }
1689         else
1690            prg16_89ab(machine, bank1 >> 1);
1691         
1692         prg16_cdef(machine, state->mmc5_prg_regs[3] >> 1);
1693         break;
1694         
1695      case 2:   // 16k-8k banks
1696         //          printf("problema 2: %x %x\n", state->mmc5_prg_regs[1], state->mmc5_prg_regs[2]);
1697         bank1 = state->mmc5_prg_regs[1];
1698         bank3 = state->mmc5_prg_regs[2];
1699         
1700         if (!BIT(bank1, 7))
1701         {
1702            state->prg_bank[0] = state->prg_chunks + (bank1 & 0x06);
1703            state->prg_bank[1] = state->prg_chunks + (bank1 & 0x06) + 1;
1704            memory_set_bank(machine, "bank1", state->prg_bank[0]);
1705            memory_set_bank(machine, "bank2", state->prg_bank[1]);
1706         }
1707         else
1708            prg16_89ab(machine, (bank1 & 0x7f) >> 1);
1709         
1710         if (!BIT(bank3, 7))
1711         {
1712            state->prg_bank[2] = state->prg_chunks + (bank3 & 0x07);
1713            memory_set_bank(machine, "bank3", state->prg_bank[2]);
1714         }
1715         else
1716            prg8_cd(machine, bank3 & 0x7f);
1717         
1718         prg8_ef(machine, state->mmc5_prg_regs[3]);
1719         break;
1720         
1721      case 3:   // 8k banks
1722         //          printf("problema 3: %x %x %x\n", state->mmc5_prg_regs[0], state->mmc5_prg_regs[1], state->mmc5_prg_regs[2]);
1723         bank1 = state->mmc5_prg_regs[0];
1724         bank2 = state->mmc5_prg_regs[1];
1725         bank3 = state->mmc5_prg_regs[2];
1726         
1727         if (!BIT(bank1, 7))
1728         {
1729            state->prg_bank[0] = state->prg_chunks + (bank1 & 0x07);
1730            memory_set_bank(machine, "bank1", state->prg_bank[0]);
1731         }
1732         else
1733            prg8_89(machine, bank1 & 0x7f);
1734         
1735         if (!BIT(bank2, 7))
1736         {
1737            state->prg_bank[1] = state->prg_chunks + (bank2 & 0x07);
1738            memory_set_bank(machine, "bank2", state->prg_bank[1]);
1739         }
1740         else
1741            prg8_ab(machine, bank2 & 0x7f);
1742         
1743         if (!BIT(bank3, 7))
1744         {
1745            state->prg_bank[2] = state->prg_chunks + (bank3 & 0x07);
1746            memory_set_bank(machine, "bank3", state->prg_bank[2]);
1747         }
1748         else
1749            prg8_cd(machine, bank3 & 0x7f);
1750         
1751         prg8_ef(machine, state->mmc5_prg_regs[3]);
1752         break;
1753   }
1754}
1755
1756static void mmc5_update_render_mode( running_machine *machine )
1757{
1758}
1759
15781760static void mmc5_irq( running_device *device, int scanline, int vblank, int blanked )
15791761{
15801762   nes_state *state = (nes_state *)device->machine->driver_data;
1581
1763   
15821764#if 1
15831765   if (scanline == 0)
15841766      state->IRQ_status |= 0x40;
15851767   else if (scanline > PPU_BOTTOM_VISIBLE_SCANLINE)
15861768      state->IRQ_status &= ~0x40;
15871769#endif
1588
1770   
15891771   if (scanline == state->IRQ_count)
15901772   {
15911773      if (state->IRQ_enable)
15921774         cpu_set_input_line(state->maincpu, M6502_IRQ_LINE, HOLD_LINE);
1593
1775     
15941776      state->IRQ_status = 0xff;
15951777   }
1778   
1779   /* FIXME: this is ok, but then we would need to update them again when we have the BG Hblank
1780     I leave it commented out until the PPU is updated for this */
1781   //  if (ppu2c0x_is_sprite_8x16(state->ppu) || state->mmc5_last_chr_a)
1782   //      mmc5_update_chr_a(device->machine);
1783   //  else
1784   //      mmc5_update_chr_b(device->machine);
15961785}
15971786
15981787static void mmc5_ppu_mirror( running_machine *machine, int page, int src )
r8330r8331
16211810{
16221811   nes_state *state = (nes_state *)space->machine->driver_data;
16231812   int retVal;
1624
1813   
16251814   /* $5c00 - $5fff: extended videoram attributes */
16261815   if ((offset >= 0x1b00) && (offset <= 0x1eff))
16271816   {
16281817      return state->mmc5_vram[offset - 0x1b00];
16291818   }
1630
1819   
16311820   switch (offset)
16321821   {
16331822      case 0x1104: /* $5204 */
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16411830         state->IRQ_status &= ~0x80;
16421831         return retVal;
16431832#endif
1644
1833         
16451834      case 0x1105: /* $5205 */
16461835         return (state->mult1 * state->mult2) & 0xff;
16471836      case 0x1106: /* $5206 */
16481837         return ((state->mult1 * state->mult2) & 0xff00) >> 8;
1649
1838         
16501839      default:
16511840         logerror("** MMC5 uncaught read, offset: %04x\n", offset + 0x4100);
16521841         return 0x00;
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16571846static WRITE8_HANDLER( exrom_l_w )
16581847{
16591848   nes_state *state = (nes_state *)space->machine->driver_data;
1660
1849   
16611850   //  LOG_MMC(("Mapper 5 write, offset: %04x, data: %02x\n", offset + 0x4100, data));
16621851   /* Send $5000-$5015 to the sound chip */
16631852   if ((offset >= 0xf00) && (offset <= 0xf15))
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16651854      nes_psg_w(state->sound, offset & 0x1f, data);
16661855      return;
16671856   }
1668
1857   
16691858   /* $5c00 - $5fff: extended videoram attributes */
16701859   if ((offset >= 0x1b00) && (offset <= 0x1eff))
16711860   {
r8330r8331
16731862         state->mmc5_vram[offset - 0x1b00] = data;
16741863      return;
16751864   }
1676
1865   
16771866   switch (offset)
16781867   {
16791868      case 0x1000: /* $5100 */
1680         state->MMC5_rom_bank_mode = data & 0x03;
1869         state->mmc5_prg_mode = data & 0x03;
1870         //          mmc5_update_prg(space->machine);
16811871         LOG_MMC(("MMC5 rom bank mode: %02x\n", data));
16821872         break;
1683
1873         
16841874      case 0x1001: /* $5101 */
1685         state->MMC5_vrom_bank_mode = data & 0x03;
1875         state->mmc5_chr_mode = data & 0x03;
1876         // update chr
16861877         LOG_MMC(("MMC5 vrom bank mode: %02x\n", data));
16871878         break;
1688
1879         
16891880      case 0x1002: /* $5102 */
16901881         if (data == 0x02)
16911882            state->MMC5_vram_protect |= 1;
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17001891            state->MMC5_vram_protect = 0;
17011892         LOG_MMC(("MMC5 vram protect 2: %02x\n", data));
17021893         break;
1703
1894         
17041895      case 0x1004: /* $5104 - Extra VRAM (EXRAM) control */
17051896         state->mmc5_vram_control = data & 0x03;
1897         // update render
1898         mmc5_update_render_mode(space->machine);
17061899         LOG_MMC(("MMC5 exram control: %02x\n", data));
17071900         break;
1708
1901         
17091902      case 0x1005: /* $5105 */
17101903         mmc5_ppu_mirror(space->machine, 0, data & 0x03);
17111904         mmc5_ppu_mirror(space->machine, 1, (data & 0x0c) >> 2);
17121905         mmc5_ppu_mirror(space->machine, 2, (data & 0x30) >> 4);
17131906         mmc5_ppu_mirror(space->machine, 3, (data & 0xc0) >> 6);
1907         // update render
1908         mmc5_update_render_mode(space->machine);
17141909         break;
1715
1910         
17161911         /* tile data for MMC5 flood-fill NT mode */
17171912      case 0x1006:
17181913         state->MMC5_floodtile = data;
17191914         break;
1720
1915         
17211916         /* attr data for MMC5 flood-fill NT mode */
17221917      case 0x1007:
17231918         switch (data & 3)
1724         {
1919      {
17251920         default:
17261921         case 0: state->MMC5_floodattr = 0x00; break;
17271922         case 1: state->MMC5_floodattr = 0x55; break;
17281923         case 2: state->MMC5_floodattr = 0xaa; break;
17291924         case 3: state->MMC5_floodattr = 0xff; break;
1730         }
1925      }
17311926         break;
1732
1927         
17331928      case 0x1013: /* $5113 */
17341929         LOG_MMC(("MMC5 mid RAM bank select: %02x\n", data & 0x07));
17351930         // FIXME: a few Koei games have both WRAM & BWRAM but here we don't support this (yet)
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17381933         else
17391934            wram_bank(space->machine, data, NES_WRAM);
17401935         break;
1741
1936         
1937         
17421938      case 0x1014: /* $5114 */
1743         LOG_MMC(("MMC5 $5114 bank select: %02x (mode: %d)\n", data, state->MMC5_rom_bank_mode));
1744         switch (state->MMC5_rom_bank_mode)
1745         {
1746         case 0x03:
1747            /* 8k switch */
1748            if (data & 0x80)
1749            {
1750               /* ROM */
1751               LOG_MMC(("\tROM bank select (8k, $8000): %02x\n", data & 0x7f));
1752               prg8_89(space->machine, data & 0x7f);
1753            }
1754            else
1755            {
1756               /* RAM */
1757               LOG_MMC(("\tRAM bank select (8k, $8000): %02x\n", data & 0x07));
1758               state->prg_bank[0] = state->prg_chunks + (data & 0x07);
1759               memory_set_bank(space->machine, "bank1", state->prg_bank[0]);
1760            }
1761            break;
1762         }
1763         break;
17641939      case 0x1015: /* $5115 */
1765         LOG_MMC(("MMC5 $5115 bank select: %02x (mode: %d)\n", data, state->MMC5_rom_bank_mode));
1766         switch (state->MMC5_rom_bank_mode)
1767         {
1768         case 0x01:
1769         case 0x02:
1770            if (data & 0x80)
1771            {
1772               /* 16k switch - ROM only */
1773               LOG_MMC(("\tROM bank select (16k, $8000): %02x\n", (data & 0x7f) >> 1));
1774               prg16_89ab(space->machine, (data & 0x7f) >> 1);
1775            }
1776            else
1777            {
1778               /* RAM */
1779               LOG_MMC(("\tRAM bank select (16k, $8000): %02x\n", (data & 0x07) >> 1));
1780               state->prg_bank[0] = state->prg_chunks + (data & 0x06);
1781               state->prg_bank[1] = state->prg_chunks + (data & 0x06) + 1;
1782               memory_set_bank(space->machine, "bank1", state->prg_bank[0]);
1783               memory_set_bank(space->machine, "bank2", state->prg_bank[1]);
1784            }
1785            break;
1786         case 0x03:
1787            /* 8k switch */
1788            if (data & 0x80)
1789            {
1790               /* ROM */
1791               LOG_MMC(("\tROM bank select (8k, $a000): %02x\n", data & 0x7f));
1792               prg8_ab(space->machine, data & 0x7f);
1793            }
1794            else
1795            {
1796               /* RAM */
1797               LOG_MMC(("\tRAM bank select (8k, $a000): %02x\n", data & 0x07));
1798               state->prg_bank[1] = state->prg_chunks + (data & 0x07);
1799               memory_set_bank(space->machine, "bank2", state->prg_bank[1]);
1800            }
1801            break;
1802         }
1940      case 0x1016: /* $5116 */
1941      case 0x1017: /* $5117 */
1942         state->mmc5_prg_regs[offset & 3] = data;
1943         mmc5_update_prg(space->machine);
18031944         break;
1804      case 0x1016: /* $5116 */
1805         LOG_MMC(("MMC5 $5116 bank select: %02x (mode: %d)\n", data, state->MMC5_rom_bank_mode));
1806         switch (state->MMC5_rom_bank_mode)
1945         
1946#if 0
1947      // these do not work as expected... I guess we definitely need the bank update at proper times (with BG vs. sprite timing)
1948      case 0x1020: /* $5120 */
1949      case 0x1021: /* $5121 */
1950      case 0x1022: /* $5122 */
1951      case 0x1023: /* $5123 */
1952      case 0x1024: /* $5124 */
1953      case 0x1025: /* $5125 */
1954      case 0x1026: /* $5126 */
1955      case 0x1027: /* $5127 */
1956         data |= (state->mmc5_chr_high << 8);
1957         if (!state->mmc5_last_chr_a)
18071958         {
1808         case 0x02:
1809         case 0x03:
1810            /* 8k switch */
1811            if (data & 0x80)
1812            {
1813               /* ROM */
1814               LOG_MMC(("\tROM bank select (8k, $c000): %02x\n", data & 0x7f));
1815               prg8_cd(space->machine, data & 0x7f);
1816            }
1817            else
1818            {
1819               /* RAM */
1820               LOG_MMC(("\tRAM bank select (8k, $c000): %02x\n", data & 0x07));
1821               state->prg_bank[2] = state->prg_chunks + (data & 0x07);
1822               memory_set_bank(space->machine, "bank3", state->prg_bank[2]);
1823            }
1824            break;
1959            state->mmc5_vrom_regA[offset & 0x07] = data;
1960            state->mmc5_last_chr_a = 1;
1961            if (ppu2c0x_get_current_scanline(state->ppu) == 240 || !ppu2c0x_is_sprite_8x16(state->ppu))
1962               mmc5_update_chr_a(space->machine);
18251963         }
18261964         break;
1827      case 0x1017: /* $5117 */
1828         LOG_MMC(("MMC5 $5117 bank select: %02x (mode: %d)\n", data, state->MMC5_rom_bank_mode));
1829         switch (state->MMC5_rom_bank_mode)
1965         
1966         
1967      case 0x1028: /* $5128 */
1968      case 0x1029: /* $5129 */
1969      case 0x102a: /* $512a */
1970      case 0x102b: /* $512b */
1971         data |= (state->mmc5_chr_high << 8);
1972         state->mmc5_vrom_regB[offset & 0x03] = data;
1973         state->mmc5_last_chr_a = 0;
1974         if (ppu2c0x_get_current_scanline(state->ppu) == 240 || !ppu2c0x_is_sprite_8x16(state->ppu))
1975            mmc5_update_chr_b(space->machine);
1976         break;
1977
1978      case 0x1030: /* $5130 */
1979         state->mmc5_chr_high = data & 0x03;
1980         if (state->mmc5_vram_control == 1)
18301981         {
1831         case 0x00:
1832            /* 32k switch - ROM only */
1833            LOG_MMC(("\tROM bank select (32k, $8000): %02x\n", (data & 0x7f) >> 2));
1834            prg32(space->machine, data >> 2);
1835            break;
1836         case 0x01:
1837            /* 16k switch - ROM only */
1838            LOG_MMC(("\tROM bank select (16k, $c000): %02x\n", (data & 0x7f) >> 1));
1839            prg16_cdef(space->machine, data >> 1);
1840            break;
1841         case 0x02:
1842         case 0x03:
1843            /* 8k switch */
1844            LOG_MMC(("\tROM bank select (8k, $e000): %02x\n", data & 0x7f));
1845            prg8_ef(space->machine, data & 0x7f);
1846            break;
1982            // in this case state->mmc5_chr_high selects which 256KB of CHR ROM
1983            // is to be used for all background tiles on the screen.
18471984         }
18481985         break;
1986         
1987#endif
1988         
18491989      case 0x1020: /* $5120 */
1850         LOG_MMC(("MMC5 $5120 vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
1851         switch (state->MMC5_vrom_bank_mode)
1852         {
1990         LOG_MMC(("MMC5 $5120 vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
1991         switch (state->mmc5_chr_mode)
1992      {
18531993         case 0x03:
18541994            /* 1k switch */
18551995            state->MMC5_vrom_bank[0] = data | (state->mmc5_high_chr << 8);
r8330r8331
18602000            //                  vrom_page_a = 1;
18612001            //                  vrom_page_b = 0;
18622002            break;
1863         }
2003      }
18642004         break;
18652005      case 0x1021: /* $5121 */
1866         LOG_MMC(("MMC5 $5121 vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
1867         switch (state->MMC5_vrom_bank_mode)
1868         {
2006         LOG_MMC(("MMC5 $5121 vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
2007         switch (state->mmc5_chr_mode)
2008      {
18692009         case 0x02:
18702010            /* 2k switch */
18712011            chr2_0(space->machine, data | (state->mmc5_high_chr << 8), CHRROM);
r8330r8331
18802020            //                  vrom_page_a = 1;
18812021            //                  vrom_page_b = 0;
18822022            break;
1883         }
2023      }
18842024         break;
18852025      case 0x1022: /* $5122 */
1886         LOG_MMC(("MMC5 $5122 vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
1887         switch (state->MMC5_vrom_bank_mode)
1888         {
2026         LOG_MMC(("MMC5 $5122 vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
2027         switch (state->mmc5_chr_mode)
2028      {
18892029         case 0x03:
18902030            /* 1k switch */
18912031            state->MMC5_vrom_bank[2] = data | (state->mmc5_high_chr << 8);
r8330r8331
18962036            //                  vrom_page_a = 1;
18972037            //                  vrom_page_b = 0;
18982038            break;
1899         }
2039      }
19002040         break;
19012041      case 0x1023: /* $5123 */
1902         LOG_MMC(("MMC5 $5123 vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
1903         switch (state->MMC5_vrom_bank_mode)
1904         {
2042         LOG_MMC(("MMC5 $5123 vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
2043         switch (state->mmc5_chr_mode)
2044      {
19052045         case 0x01:
19062046            chr4_0(space->machine, data, CHRROM);
19072047            break;
r8330r8331
19192059            //                  vrom_page_a = 1;
19202060            //                  vrom_page_b = 0;
19212061            break;
1922         }
2062      }
19232063         break;
19242064      case 0x1024: /* $5124 */
1925         LOG_MMC(("MMC5 $5124 vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
1926         switch (state->MMC5_vrom_bank_mode)
1927         {
2065         LOG_MMC(("MMC5 $5124 vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
2066         switch (state->mmc5_chr_mode)
2067      {
19282068         case 0x03:
19292069            /* 1k switch */
19302070            state->MMC5_vrom_bank[4] = data | (state->mmc5_high_chr << 8);
r8330r8331
19352075            //                  vrom_page_a = 0;
19362076            //                  vrom_page_b = 0;
19372077            break;
1938         }
2078      }
19392079         break;
19402080      case 0x1025: /* $5125 */
1941         LOG_MMC(("MMC5 $5125 vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
1942         switch (state->MMC5_vrom_bank_mode)
1943         {
2081         LOG_MMC(("MMC5 $5125 vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
2082         switch (state->mmc5_chr_mode)
2083      {
19442084         case 0x02:
19452085            /* 2k switch */
19462086            chr2_4(space->machine, data | (state->mmc5_high_chr << 8), CHRROM);
r8330r8331
19552095            //                  vrom_page_a = 0;
19562096            //                  vrom_page_b = 0;
19572097            break;
1958         }
2098      }
19592099         break;
19602100      case 0x1026: /* $5126 */
1961         LOG_MMC(("MMC5 $5126 vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
1962         switch (state->MMC5_vrom_bank_mode)
1963         {
2101         LOG_MMC(("MMC5 $5126 vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
2102         switch (state->mmc5_chr_mode)
2103      {
19642104         case 0x03:
19652105            /* 1k switch */
19662106            state->MMC5_vrom_bank[6] = data | (state->mmc5_high_chr << 8);
r8330r8331
19712111            //                  vrom_page_a = 0;
19722112            //                  vrom_page_b = 0;
19732113            break;
1974         }
2114      }
19752115         break;
19762116      case 0x1027: /* $5127 */
1977         LOG_MMC(("MMC5 $5127 vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
1978         switch (state->MMC5_vrom_bank_mode)
1979         {
2117         LOG_MMC(("MMC5 $5127 vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
2118         switch (state->mmc5_chr_mode)
2119      {
19802120         case 0x00:
19812121            /* 8k switch */
19822122            chr8(space->machine, data, CHRROM);
r8330r8331
19992139            //                  vrom_page_a = 0;
20002140            //                  vrom_page_b = 0;
20012141            break;
2002         }
2142      }
20032143         break;
20042144      case 0x1028: /* $5128 */
2005         LOG_MMC(("MMC5 $5128 vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
2006         switch (state->MMC5_vrom_bank_mode)
2007         {
2145         LOG_MMC(("MMC5 $5128 vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
2146         switch (state->mmc5_chr_mode)
2147      {
20082148         case 0x03:
20092149            /* 1k switch */
20102150            state->MMC5_vrom_bank[8] = data | (state->mmc5_high_chr << 8);
r8330r8331
20192159               state->vrom_page_b = 1;
20202160            }
20212161            break;
2022         }
2162      }
20232163         break;
20242164      case 0x1029: /* $5129 */
2025         LOG_MMC(("MMC5 $5129 vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
2026         switch (state->MMC5_vrom_bank_mode)
2027         {
2165         LOG_MMC(("MMC5 $5129 vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
2166         switch (state->mmc5_chr_mode)
2167      {
20282168         case 0x02:
20292169            /* 2k switch */
20302170            chr2_0(space->machine, data | (state->mmc5_high_chr << 8), CHRROM);
r8330r8331
20442184               state->vrom_page_b = 1;
20452185            }
20462186            break;
2047         }
2187      }
20482188         break;
20492189      case 0x102a: /* $512a */
2050         LOG_MMC(("MMC5 $512a vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
2051         switch (state->MMC5_vrom_bank_mode)
2052         {
2190         LOG_MMC(("MMC5 $512a vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
2191         switch (state->mmc5_chr_mode)
2192      {
20532193         case 0x03:
20542194            /* 1k switch */
20552195            state->MMC5_vrom_bank[10] = data | (state->mmc5_high_chr << 8);
r8330r8331
20642204               state->vrom_page_b = 1;
20652205            }
20662206            break;
2067         }
2207      }
20682208         break;
20692209      case 0x102b: /* $512b */
2070         LOG_MMC(("MMC5 $512b vrom select: %02x (mode: %d)\n", data, state->MMC5_vrom_bank_mode));
2071         switch (state->MMC5_vrom_bank_mode)
2072         {
2210         LOG_MMC(("MMC5 $512b vrom select: %02x (mode: %d)\n", data, state->mmc5_chr_mode));
2211         switch (state->mmc5_chr_mode)
2212      {
20732213         case 0x00:
20742214            /* 8k switch */
20752215            /* switches in first half of an 8K bank!) */
r8330r8331
21002240               state->vrom_page_b = 1;
21012241            }
21022242            break;
2103         }
2243      }
21042244         break;
2105
2245         
21062246      case 0x1030: /* $5130 */
21072247         state->mmc5_high_chr = data & 0x03;
21082248         if (state->mmc5_vram_control == 1)
r8330r8331
21112251            // is to be used for all background tiles on the screen.
21122252         }
21132253         break;
2114
2115
2254         
2255         
21162256      case 0x1100: /* $5200 */
21172257         state->mmc5_split_scr = data;
21182258         // in EX2 and EX3 modes, no split screen
21192259         if (state->mmc5_vram_control & 0x02)
21202260            state->mmc5_split_scr &= 0x7f;
2261         state->mmc5_split_ctrl = data;
21212262         break;
2122
2263         
2264      case 0x1101: /* $5201 */
2265         state->mmc5_split_yst = (data >= 240) ? data - 16 : data;
2266         break;
2267         
2268      case 0x1102: /* $5202 */
2269         state->mmc5_split_bank = data;
2270         break;
2271         
21232272      case 0x1103: /* $5203 */
21242273         state->IRQ_count = data;
21252274         state->MMC5_scanline = data;
r8330r8331
21352284      case 0x1106: /* $5206 */
21362285         state->mult2 = data;
21372286         break;
2138
2287         
21392288      default:
21402289         logerror("** MMC5 uncaught write, offset: %04x, data: %02x\n", offset + 0x4100, data);
21412290         break;
r8330r8331
93569505   LOG_MMC(("bmc_190in1_w offset: %04x, data: %02x\n", offset, data));
93579506
93589507   set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9359   data >>= 2;
9360   prg16_89ab(space->machine, data);
9361   prg16_cdef(space->machine, data);
9362   chr8(space->machine, data, CHRROM);
9508   offset >>= 2;
9509   prg16_89ab(space->machine, offset);
9510   prg16_cdef(space->machine, offset);
9511   chr8(space->machine, offset, CHRROM);
93639512}
93649513
93659514/*************************************************************
r8330r8331
1066310812   if (state->mmc_latch1)
1066410813      return state->mmc_dipsetting; // cart mode, depending on the Dip Switches (always zero atm, given we have no way to add cart-based DIPs)
1066510814   else
10666   {   // usual ROM access
10667      switch (offset & 0x6000)
10668      {
10669         case 0x0000:
10670            return state->rom[0x10000 + state->prg_bank[0] * 0x2000 + (offset & 0x1fff)];
10671         case 0x2000:
10672            return state->rom[0x10000 + state->prg_bank[1] * 0x2000 + (offset & 0x1fff)];
10673         case 0x4000:
10674            return state->rom[0x10000 + state->prg_bank[2] * 0x2000 + (offset & 0x1fff)];
10675         case 0x6000:
10676            return state->rom[0x10000 + state->prg_bank[3] * 0x2000 + (offset & 0x1fff)];
10677      }
10678      return 0;
10679   }
10815      return mmc_hi_access_rom(space->machine, offset);
1068010816}
1068110817
1068210818/*************************************************************
r8330r8331
1074710883   chr8(space->machine, offset & 0x0f, CHRROM);
1074810884}
1074910885
10886/*************************************************************
1075010887
10888 BMC-NTD-03
1075110889
10890 *************************************************************/
10891
10892static WRITE8_HANDLER( bmc_ntd03_w )
10893{
10894   UINT8 pbank, cbank;
10895   LOG_MMC(("bmc_ntd03_w, offset: %04x, data: %02x\n", offset, data));
10896
10897   pbank = (offset >> 10) & 0x1e;
10898   cbank = ((offset & 0x300) >> 5) | (offset & 0x07);
10899
10900   if (BIT(offset, 7))
10901   {
10902      prg16_89ab(space->machine, pbank | BIT(offset, 6));
10903      prg16_cdef(space->machine, pbank | BIT(offset, 6));
10904   }
10905   else
10906      prg32(space->machine, pbank >> 1);
10907
10908   set_nt_mirroring(space->machine, BIT(data, 10) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10909
10910   chr8(space->machine, cbank, CHRROM);
10911}
10912
10913/*************************************************************
10914
10915 BMC-GHOSTBUSTERS63IN1
10916
10917 in MESS: only preliminar support
10918
10919 *************************************************************/
10920
10921static void bmc_gb63_update( running_machine *machine )
10922{
10923   nes_state *state = (nes_state *)machine->driver_data;
10924
10925   set_nt_mirroring(machine, BIT(state->mmc_reg[0], 6) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
10926
10927   if (BIT(state->mmc_reg[0], 5))
10928   {
10929      prg16_89ab(machine, state->mmc_reg[0] & 0x1f);   // FIXME: here probably we could also have PRGRAM, depending on mmc_latch1!
10930      prg16_cdef(machine, state->mmc_reg[0] & 0x1f);   // FIXME: here probably we could also have PRGRAM, depending on mmc_latch1!
10931   }
10932   else
10933      prg32(machine, (state->mmc_reg[0] & 0x1f) >> 1);   // FIXME: here probably we could also have PRGRAM, depending on mmc_latch1!
10934
10935   if (BIT(state->mmc_reg[1], 2))
10936      chr8(machine, 0, CHRRAM);
10937//  else
10938//      chr8(machine, 0, CHRROM);
10939}
10940
10941static WRITE8_HANDLER( bmc_gb63_w )
10942{
10943   nes_state *state = (nes_state *)space->machine->driver_data;
10944   LOG_MMC(("bmc_gb63_w, offset: %04x, data: %02x\n", offset, data));
10945
10946   state->mmc_reg[offset & 1] = data;
10947   state->mmc_latch1 = BIT(state->mmc_reg[0], 7) | (BIT(state->mmc_reg[1], 0) << 1);
10948
10949}
10950
10951static READ8_HANDLER( bmc_gb63_r )
10952{
10953   nes_state *state = (nes_state *)space->machine->driver_data;
10954   LOG_MMC(("bmc_gb63_r, offset: %04x\n", offset));
10955   //  state->mmc_dipsetting = input_port_read(space->machine, "CARTDIPS");
10956
10957   if (state->mmc_latch1 == 1)
10958      return 0xff;   // open bus
10959   else
10960      return mmc_hi_access_rom(space->machine, offset);
10961}
10962
10963/*************************************************************
10964
10965 UNL-EDU2000
10966
10967 *************************************************************/
10968
10969static WRITE8_HANDLER( edu2k_w )
10970{
10971   LOG_MMC(("edu2k_w, offset: %04x, data: %02x\n", offset, data));
10972
10973   prg32(space->machine, data & 0x1f);
10974   wram_bank(space->machine, (data & 0xc0) >> 6, NES_WRAM);
10975}
10976
10977
10978
1075210979typedef void (*nes_ppu_latch)(running_device *device, offs_t offset);
1075310980
1075410981struct nes_memory_accessor
r8330r8331
1100611233   { BMC_VT5201,           NES_NOACCESS, NES_NOACCESS, {bmc_vt5201_w, bmc_vt5201_r},         NULL, NULL, NULL },
1100711234   { BMC_BENSHENG_BS5,     NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_bs5_w),             NULL, NULL, NULL },
1100811235   { BMC_810544,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_810544_w),          NULL, NULL, NULL },
11236   { BMC_NTD_03,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(bmc_ntd03_w),           NULL, NULL, NULL },
11237   { BMC_G63IN1,           NES_NOACCESS, NES_NOACCESS, {bmc_gb63_w, bmc_gb63_r},             NULL, NULL, NULL },
11238   { UNL_EDU2K,           NES_NOACCESS, NES_NOACCESS, NES_WRITEONLY(edu2k_w),                NULL, NULL, NULL },
1100911239   { UNSUPPORTED_BOARD,    NES_NOACCESS, NES_NOACCESS, NES_NOACCESS,                         NULL, NULL, NULL },
1101011240   //
1101111241};
src/mess/machine/nes.c
r8330r8331
694694               state->prg_chunks = mapint3;
695695               state->chr_chunks = mapint4;
696696               logerror("NES.HSI info: %d %d %d %d\n", mapint1, mapint2, mapint3, mapint4);
697//               printf("NES.HSI info: %d %d %d %d\n", mapint1, mapint2, mapint3, mapint4);
697698               goodcrcinfo = 1;
698699               state->ines20 = 0;
699700            }
r8330r8331
708709         }
709710
710711         state->hard_mirroring = (local_options & 0x01) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ;
712//         printf("%s\n", state->hard_mirroring & 0x01 ? "Vertical" : "Horizontal");
711713         state->battery = local_options & 0x02;
712714         state->trainer = local_options & 0x04;
713715         state->four_screen_vram = local_options & 0x08;
r8330r8331
12851287
12861288#if 0
12871289      if (state->pcb_id == UNSUPPORTED_BOARD)
1288         printf("This board (%s) is currently not supported by MESS\n", image_get_feature(image, "pcb"));
1290         printf("This board (%s) is currently not supported by MESS\n", image.get_feature("pcb"));
12891291      printf("PCB Feature: %s\n", image.get_feature("pcb"));
12901292      printf("PRG chunks: %d\n", state->prg_chunks);
12911293      printf("CHR chunks: %d\n", state->chr_chunks);
src/mess/machine/nes_unif.c
r8330r8331
128128   { "BMC-FK23C",                  0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD /*BMC_FK23C*/},
129129   { "BMC-FK23CA",                 0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD /*BMC_FK23C*/},   // diff reg init
130130   { "BMC-GHOSTBUSTERS63IN1",      0,    0, CHRRAM_8,  NT_HORZ, UNSUPPORTED_BOARD /*BMC_G63IN1*/},
131   { "BMC-BS-5",                   0,    0, CHRRAM_0,  NT_VERT, UNSUPPORTED_BOARD /*BENSHENG_BS5*/},
132   { "BMC-810544-C-A1",            0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD},
131   { "BMC-BS-5",                   0,    0, CHRRAM_0,  NT_VERT, BMC_BENSHENG_BS5},
132   { "BMC-810544-C-A1",            0,    0, CHRRAM_0,  NT_X,  BMC_810544},
133133   { "BMC-411120-C",               0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD},
134134   { "BMC-8157",                   0,    0, CHRRAM_8,  NT_VERT, UNSUPPORTED_BOARD /*BMC_8157*/},
135135   { "BMC-42IN1RESETSWITCH",       0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD},   // mapper 60?
136136   { "BMC-830118C",                0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD},
137   { "BMC-D1038",                  0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD}, // mapper 60?
137   { "BMC-D1038",                  0,    0, CHRRAM_0,  NT_X,  BMC_VT5201}, // mapper 60?
138138   { "BMC-12-IN-1",                0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD},
139139   { "BMC-70IN1",                  0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD},   // mapper 236?
140140   { "BMC-70IN1B",                 0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD},   // mapper 236?
141141   { "BMC-SUPERVISION16IN1",       0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD},   // mapper 53
142   { "BMC-NTD-03",                 0,    0, CHRRAM_0,  NT_X,  UNSUPPORTED_BOARD}
142   { "BMC-NTD-03",                 0,    0, CHRRAM_0,  NT_X,  BMC_NTD_03}
143143};
144144
145145const unif *nes_unif_lookup( const char *board )
r8330r8331
307307         state->mmc5_split_scr = 0;
308308         memset(state->MMC5_vrom_bank, 0, ARRAY_LENGTH(state->MMC5_vrom_bank));
309309         state->mid_ram_enable = 0;
310         state->mmc5_prg_mode = 3;
311         state->mmc5_last_chr_a = 1;
312         state->mmc5_prg_regs[0] = 0xfc;
313         state->mmc5_prg_regs[1] = 0xfd;
314         state->mmc5_prg_regs[2] = 0xfe;
315         state->mmc5_prg_regs[3] = 0xff;
316         memset(state->mmc5_vrom_regA, ~0, ARRAY_LENGTH(state->mmc5_vrom_regA));
317         memset(state->mmc5_vrom_regB, ~0, ARRAY_LENGTH(state->mmc5_vrom_regB));
310318         prg16_89ab(machine, state->prg_chunks - 2);
311319         prg16_cdef(machine, state->prg_chunks - 1);
312320         break;
r8330r8331
12851293         set_nt_mirroring(machine, PPU_MIRROR_VERT);
12861294         break;
12871295
1296      case BMC_NTD_03:
1297         prg16_89ab(machine, 0);
1298         prg16_cdef(machine, state->prg_chunks - 1);
1299         chr8(machine, 0, CHRROM);
1300         break;
1301
1302      case UNL_EDU2K:
1303         break;
1304
1305      case BMC_G63IN1:
1306         bmc_gb63_update(machine);
1307         break;
1308
12881309      case UNSUPPORTED_BOARD:
12891310      default:
12901311         /* Mapper not supported */
src/mess/machine/nes_mmc.h
r8330r8331
7676   BMC_GOLDENCARD_6IN1, BMC_72IN1, BMC_SUPER_42IN1, BMC_76IN1,
7777   BMC_1200IN1, BMC_31IN1, BMC_22GAMES, BMC_20IN1, BMC_110IN1,
7878   BMC_GKA, BMC_GKB, BMC_VT5201, BMC_BENSHENG_BS5, BMC_810544,
79   BMC_NTD_03, BMC_G63IN1,
7980   /* Unlicensed */
8081   UNL_8237, UNL_CC21, UNL_AX5705, UNL_KOF97,
8182   UNL_N625092, UNL_SC127, UNL_SMB2J, UNL_T230,
8283   UNL_UXROM, UNL_MK2, UNL_XZY, UNL_KOF96,
83   UNL_SUPERFIGHTER3, UNL_RACERMATE,
84   UNL_SUPERFIGHTER3, UNL_RACERMATE, UNL_EDU2K,
8485   /* Bootleg boards */
8586   BTL_SMB2A, BTL_MARIOBABY, BTL_AISENSHINICOL,
8687   BTL_SMB2B, BTL_SMB3, BTL_SUPERBROS11, BTL_DRAGONNINJA,
src/mess/includes/nes.h
r8330r8331
9090   UINT8 mmc5_high_chr;
9191   UINT8 mmc5_split_scr;
9292   UINT8 *extended_ntram;
93   
94   UINT8 mmc5_last_chr_a;
95   UINT16 mmc5_vrom_regA[8];
96   UINT16 mmc5_vrom_regB[4];
97   UINT8 mmc5_prg_regs[4];
98   UINT8 mmc5_bank_security;
99   UINT8 mmc5_prg_mode;
100   UINT8 mmc5_chr_mode;
101   UINT8 mmc5_chr_high;
102   UINT8 mmc5_split_ctrl;
103   UINT8 mmc5_split_yst;
104   UINT8 mmc5_split_bank;
93105
94106   /* video-related */
95107   int nes_vram_sprite[8]; /* Used only by mmc5 for now */

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