src/mess/drivers/a2600.c
| r799 | r800 | |
| 39 | 39 | modeSS, |
| 40 | 40 | modeFV, |
| 41 | 41 | modeDPC, |
| 42 | | mode32in1 |
| 42 | mode32in1, |
| 43 | modeJVP |
| 43 | 44 | }; |
| 44 | 45 | |
| 45 | 46 | struct DPC_DF { |
| r799 | r800 | |
| 83 | 84 | static unsigned modeSS_diff_adjust; |
| 84 | 85 | static unsigned FVlocked; |
| 85 | 86 | |
| 87 | static UINT16 current_screen_height; |
| 88 | static const UINT16 supported_screen_heights[4] = { 262, 312, 328, 342 }; |
| 89 | |
| 86 | 90 | // try to detect 2600 controller setup. returns 32bits with left/right controller info |
| 87 | 91 | |
| 88 | 92 | static unsigned long detect_2600controllers(void) |
| r799 | r800 | |
| 563 | 567 | void modeFV_switch(UINT16 offset, UINT8 data) |
| 564 | 568 | { |
| 565 | 569 | //printf("ModeFV %04x\n",offset); |
| 566 | | if (!FVlocked) { |
| 570 | if (!FVlocked && ( activecpu_get_pc() & 0x1F00 ) == 0x1F00 ) { |
| 567 | 571 | FVlocked = 1; |
| 568 | 572 | current_bank = current_bank ^ 0x01; |
| 569 | 573 | bank_base[1] = CART + 0x1000 * current_bank; |
| 570 | 574 | memory_set_bankptr(1, bank_base[1]); |
| 571 | 575 | } |
| 572 | 576 | } |
| 577 | void modeJVP_switch(UINT16 offset, UINT8 data) |
| 578 | { |
| 579 | switch( offset ) { |
| 580 | case 0x00: |
| 581 | case 0x20: |
| 582 | current_bank ^= 1; |
| 583 | break; |
| 584 | default: |
| 585 | printf("%04X: write to unknown mapper address %02X\n", activecpu_get_pc(), 0xfa0 + offset ); |
| 586 | break; |
| 587 | } |
| 588 | bank_base[1] = CART + 0x1000 * current_bank; |
| 589 | memory_set_bankptr( 1, bank_base[1] ); |
| 590 | } |
| 573 | 591 | |
| 574 | 592 | |
| 575 | 593 | /* These read handlers will return the byte from the new bank */ |
| r799 | r800 | |
| 583 | 601 | static READ8_HANDLER(modeUA_switch_r) { modeUA_switch(offset, 0); return 0; } |
| 584 | 602 | static READ8_HANDLER(modeDC_switch_r) { modeDC_switch(offset, 0); return bank_base[1][0xff0 + offset]; } |
| 585 | 603 | static READ8_HANDLER(modeFV_switch_r) { modeFV_switch(offset, 0); return bank_base[1][0xfd0 + offset]; } |
| 604 | static READ8_HANDLER(modeJVP_switch_r) { modeJVP_switch(offset, 0); return riot_ram[ 0x20 + offset ]; } |
| 586 | 605 | |
| 587 | 606 | |
| 588 | 607 | static WRITE8_HANDLER(mode8K_switch_w) { mode8K_switch(offset, data); } |
| r799 | r800 | |
| 603 | 622 | } |
| 604 | 623 | } |
| 605 | 624 | static WRITE8_HANDLER(modeFV_switch_w) { modeFV_switch(offset, data); } |
| 625 | static WRITE8_HANDLER(modeJVP_switch_w) { modeJVP_switch(offset, data); riot_ram[ 0x20 + offset ] = data; } |
| 606 | 626 | |
| 607 | 627 | |
| 608 | 628 | OPBASE_HANDLER( modeSS_opbase ) |
| r799 | r800 | |
| 1011 | 1031 | return val; |
| 1012 | 1032 | } |
| 1013 | 1033 | |
| 1034 | static WRITE8_HANDLER( switch_B_w ) { |
| 1035 | } |
| 1014 | 1036 | |
| 1037 | static void irq_callback(int state) { |
| 1038 | } |
| 1039 | |
| 1015 | 1040 | static const struct riot6532_interface r6532_interface = |
| 1016 | 1041 | { |
| 1017 | 1042 | switch_A_r, |
| 1018 | 1043 | input_port_8_r, |
| 1019 | 1044 | switch_A_w, |
| 1020 | | NULL, |
| 1021 | | NULL |
| 1045 | switch_B_w, |
| 1046 | irq_callback |
| 1022 | 1047 | }; |
| 1023 | 1048 | |
| 1024 | 1049 | |
| r799 | r800 | |
| 1224 | 1249 | return last_byte; |
| 1225 | 1250 | } |
| 1226 | 1251 | |
| 1252 | static const rectangle visarea[4] = { |
| 1253 | { 26, 26 + 160 + 16, 24, 24 + 192 + 31 }, /* 262 */ |
| 1254 | { 26, 26 + 160 + 16, 32, 32 + 228 + 31 }, /* 312 */ |
| 1255 | { 26, 26 + 160 + 16, 45, 45 + 240 + 31 }, /* 328 */ |
| 1256 | { 26, 26 + 160 + 16, 48, 48 + 240 + 31 } /* 342 */ |
| 1257 | }; |
| 1258 | |
| 1259 | static WRITE16_HANDLER( a2600_tia_vsync_callback ) { |
| 1260 | int i; |
| 1261 | |
| 1262 | for ( i = 0; i < sizeof( supported_screen_heights ) / sizeof( supported_screen_heights[0] ); i++ ) { |
| 1263 | if ( data >= supported_screen_heights[i] - 3 && data <= supported_screen_heights[i] + 3 ) { |
| 1264 | if ( supported_screen_heights[i] != current_screen_height ) { |
| 1265 | current_screen_height = supported_screen_heights[i]; |
| 1266 | // video_screen_configure( 0, 228, current_screen_height, &visarea[i], HZ_TO_SUBSECONDS( MASTER_CLOCK_NTSC ) * 228 * current_screen_height ); |
| 1267 | } |
| 1268 | } |
| 1269 | } |
| 1270 | } |
| 1271 | |
| 1272 | static WRITE16_HANDLER( a2600_tia_vsync_callback_pal ) { |
| 1273 | int i; |
| 1274 | |
| 1275 | for ( i = 0; i < sizeof( supported_screen_heights ) / sizeof( supported_screen_heights[0] ); i++ ) { |
| 1276 | if ( data >= supported_screen_heights[i] - 3 && data <= supported_screen_heights[i] + 3 ) { |
| 1277 | if ( supported_screen_heights[i] != current_screen_height ) { |
| 1278 | current_screen_height = supported_screen_heights[i]; |
| 1279 | // video_screen_configure( 0, 228, current_screen_height, &visarea[i], HZ_TO_SUBSECONDS( MASTER_CLOCK_PAL ) * 228 * current_screen_height ); |
| 1280 | } |
| 1281 | } |
| 1282 | } |
| 1283 | } |
| 1284 | |
| 1227 | 1285 | static struct tia_interface tia_interface = |
| 1228 | 1286 | { |
| 1229 | 1287 | a2600_read_input_port, |
| 1230 | | a2600_get_databus_contents |
| 1288 | a2600_get_databus_contents, |
| 1289 | a2600_tia_vsync_callback |
| 1231 | 1290 | }; |
| 1232 | 1291 | |
| 1292 | static struct tia_interface tia_interface_pal = |
| 1293 | { |
| 1294 | a2600_read_input_port, |
| 1295 | a2600_get_databus_contents, |
| 1296 | a2600_tia_vsync_callback_pal |
| 1297 | }; |
| 1298 | |
| 1233 | 1299 | static MACHINE_START( a2600 ) |
| 1234 | 1300 | { |
| 1301 | current_screen_height = machine->screen[0].height; |
| 1235 | 1302 | extra_RAM = new_memory_region( machine, REGION_USER2, 0x8600, ROM_REQUIRED ); |
| 1236 | 1303 | tia_init( &tia_interface ); |
| 1237 | 1304 | r6532_config( 0, &r6532_interface ); |
| r799 | r800 | |
| 1243 | 1310 | |
| 1244 | 1311 | static MACHINE_START( a2600p ) |
| 1245 | 1312 | { |
| 1313 | current_screen_height = machine->screen[0].height; |
| 1246 | 1314 | extra_RAM = new_memory_region( machine, REGION_USER2, 0x8600, ROM_REQUIRED ); |
| 1247 | | tia_init( &tia_interface ); |
| 1315 | tia_init( &tia_interface_pal ); |
| 1248 | 1316 | r6532_config( 0, &r6532_interface ); |
| 1249 | 1317 | r6532_set_clock( 0, MASTER_CLOCK_PAL / 3 ); |
| 1250 | 1318 | r6532_reset(0); |
| r799 | r800 | |
| 1415 | 1483 | install_banks(2, 0x0000); |
| 1416 | 1484 | current_32in1_bank = ( current_32in1_bank + 1 ) & 0x1F; |
| 1417 | 1485 | break; |
| 1486 | |
| 1487 | case modeJVP: |
| 1488 | install_banks(1, 0x0000); |
| 1489 | current_bank = 0; |
| 1490 | break; |
| 1418 | 1491 | } |
| 1419 | 1492 | |
| 1420 | 1493 | /* set up bank counter */ |
| r799 | r800 | |
| 1528 | 1601 | memory_set_bankptr( 1, CART + current_32in1_bank * 0x800 ); |
| 1529 | 1602 | memory_set_bankptr( 2, CART + current_32in1_bank * 0x800 ); |
| 1530 | 1603 | break; |
| 1604 | |
| 1605 | case modeJVP: |
| 1606 | memory_install_read8_handler(0, ADDRESS_SPACE_PROGRAM, 0x0FA0, 0x0FFF, 0, 0, modeJVP_switch_r); |
| 1607 | memory_install_write8_handler(0, ADDRESS_SPACE_PROGRAM, 0x0FA0, 0x0FFF, 0, 0, modeJVP_switch_w); |
| 1608 | break; |
| 1531 | 1609 | } |
| 1532 | 1610 | |
| 1533 | 1611 | /* set up extra RAM */ |