src/emu/cpu/m6800/m6800.h
| r795 | r796 | |
|---|
| 90 | 90 | |
| 91 | 91 | #define M6803_DDR1 0x00 |
| 92 | 92 | #define M6803_DDR2 0x01 |
| 93 | #define M6803_DDR3 0x04 |
| 94 | #define M6803_DDR4 0x05 |
| 93 | 95 | |
| 94 | 96 | #define M6803_PORT1 0x100 |
| 95 | 97 | #define M6803_PORT2 0x101 |
| 98 | #define M6803_PORT3 0x102 |
| 99 | #define M6803_PORT4 0x103 |
| 96 | 100 | #endif |
| 97 | 101 | |
| 98 | 102 | /**************************************************************************** |
| r795 | r796 | |
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| 140 | 144 | |
| 141 | 145 | #define HD63701_DDR1 M6803_DDR1 |
| 142 | 146 | #define HD63701_DDR2 M6803_DDR2 |
| 147 | #define HD63701_DDR3 M6803_DDR3 |
| 148 | #define HD63701_DDR4 M6803_DDR4 |
| 143 | 149 | |
| 144 | 150 | #define HD63701_PORT1 M6803_PORT1 |
| 145 | 151 | #define HD63701_PORT2 M6803_PORT2 |
| 152 | #define HD63701_PORT3 M6803_PORT3 |
| 153 | #define HD63701_PORT4 M6803_PORT4 |
| 146 | 154 | |
| 147 | 155 | READ8_HANDLER( hd63701_internal_registers_r ); |
| 148 | 156 | WRITE8_HANDLER( hd63701_internal_registers_w ); |
src/emu/cpu/m6800/m6800.c
| r795 | r796 | |
|---|
| 98 | 98 | /* internal registers */ |
| 99 | 99 | UINT8 port1_ddr; |
| 100 | 100 | UINT8 port2_ddr; |
| 101 | UINT8 port3_ddr; |
| 102 | UINT8 port4_ddr; |
| 101 | 103 | UINT8 port1_data; |
| 102 | 104 | UINT8 port2_data; |
| 105 | UINT8 port3_data; |
| 106 | UINT8 port4_data; |
| 103 | 107 | UINT8 tcsr; /* Timer Control and Status Register */ |
| 104 | 108 | UINT8 pending_tcsr; /* pending IRQ flag for clear IRQflag process */ |
| 105 | 109 | UINT8 irq2; /* IRQ2 flags */ |
| r795 | r796 | |
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| 1997 | 2001 | return (io_read_byte_8(M6803_PORT2) & (m6800.port2_ddr ^ 0xff)) |
| 1998 | 2002 | | (m6800.port2_data & m6800.port2_ddr); |
| 1999 | 2003 | case 0x04: |
| 2000 | | case 0x05: |
| 2004 | return m6800.port3_ddr; |
| 2005 | case 0x05: |
| 2006 | return m6800.port4_ddr; |
| 2001 | 2007 | case 0x06: |
| 2008 | return (io_read_byte_8(M6803_PORT3) & (m6800.port3_ddr ^ 0xff)) |
| 2009 | | (m6800.port3_data & m6800.port3_ddr); |
| 2002 | 2010 | case 0x07: |
| 2003 | | logerror("CPU #%d PC %04x: warning - read from unsupported internal register %02x\n",cpu_getactivecpu(),activecpu_get_pc(),offset); |
| 2004 | | return 0; |
| 2011 | return (io_read_byte_8(M6803_PORT4) & (m6800.port4_ddr ^ 0xff)) |
| 2012 | | (m6800.port4_data & m6800.port4_ddr); |
| 2005 | 2013 | case 0x08: |
| 2006 | 2014 | m6800.pending_tcsr = 0; |
| 2007 | 2015 | //logerror("CPU #%d PC %04x: warning - read TCSR register\n",cpu_getactivecpu(),activecpu_get_pc()); |
| r795 | r796 | |
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| 2114 | 2122 | | (io_read_byte_8(M6803_PORT2) & (m6800.port2_ddr ^ 0xff))); |
| 2115 | 2123 | break; |
| 2116 | 2124 | case 0x04: |
| 2125 | if (m6800.port3_ddr != data) |
| 2126 | { |
| 2127 | m6800.port3_ddr = data; |
| 2128 | if(m6800.port3_ddr == 0xff) |
| 2129 | io_write_byte_8(M6803_PORT3,m6800.port3_data); |
| 2130 | else |
| 2131 | io_write_byte_8(M6803_PORT3,(m6800.port3_data & m6800.port3_ddr) |
| 2132 | | (io_read_byte_8(M6803_PORT3) & (m6800.port3_ddr ^ 0xff))); |
| 2133 | } |
| 2134 | break; |
| 2117 | 2135 | case 0x05: |
| 2136 | if (m6800.port4_ddr != data) |
| 2137 | { |
| 2138 | m6800.port4_ddr = data; |
| 2139 | if(m6800.port4_ddr == 0xff) |
| 2140 | io_write_byte_8(M6803_PORT4,m6800.port4_data); |
| 2141 | else |
| 2142 | io_write_byte_8(M6803_PORT4,(m6800.port4_data & m6800.port4_ddr) |
| 2143 | | (io_read_byte_8(M6803_PORT4) & (m6800.port4_ddr ^ 0xff))); |
| 2144 | } |
| 2145 | break; |
| 2118 | 2146 | case 0x06: |
| 2147 | m6800.port3_data = data; |
| 2148 | if(m6800.port3_ddr == 0xff) |
| 2149 | io_write_byte_8(M6803_PORT3,m6800.port3_data); |
| 2150 | else |
| 2151 | io_write_byte_8(M6803_PORT3,(m6800.port3_data & m6800.port3_ddr) |
| 2152 | | (io_read_byte_8(M6803_PORT3) & (m6800.port3_ddr ^ 0xff))); |
| 2153 | break; |
| 2119 | 2154 | case 0x07: |
| 2120 | | logerror("CPU #%d PC %04x: warning - write %02x to unsupported internal register %02x\n",cpu_getactivecpu(),activecpu_get_pc(),data,offset); |
| 2155 | m6800.port4_data = data; |
| 2156 | if(m6800.port4_ddr == 0xff) |
| 2157 | io_write_byte_8(M6803_PORT4,m6800.port4_data); |
| 2158 | else |
| 2159 | io_write_byte_8(M6803_PORT4,(m6800.port4_data & m6800.port4_ddr) |
| 2160 | | (io_read_byte_8(M6803_PORT4) & (m6800.port4_ddr ^ 0xff))); |
| 2121 | 2161 | break; |
| 2122 | 2162 | case 0x08: |
| 2123 | 2163 | m6800.tcsr = data; |