MESS SVN History

15994 Revisions

r7956 Saturday 1st May, 2010 at 12:58:44 UTC by Fabio Priuli
[NES] moved even more variables to driver data class and simplified handlers initialization

[src/mess/includes]	nes.h
[src/mess/machine]	nes.c nes_ines.c nes_mmc.c nes_mmc.h nes_unif.c

src/mess/includes/nes.h
r7955	r7956
30	30	UINT32 i0, i1, i2;
31	31	};
32	32
	33	/PPU fast banking constants and structures /
	34
	35	#define CHRROM 0
	36	#define CHRRAM 1
	37
	38	typedef struct
	39	{
	40	int source; //defines source of base pointer
	41	int origin; //defines offset of 0x400 byte segment at base pointer
	42	UINT8* access; //source translated + origin -> valid pointer!
	43	} chr_bank;
	44
	45	/PPU nametable fast banking constants and structures /
	46
	47	#define CIRAM 0
	48	#define ROM 1
	49	#define EXRAM 2
	50	#define MMC5FILL 3
	51	#define CART_NTRAM 4
	52
	53	typedef struct
	54	{
	55	int source; /* defines source of base pointer */
	56	int origin; /* defines offset of 0x400 byte segment at base pointer */
	57	int writable; /* ExRAM, at least, can be write-protected AND used as nametable */
	58	UINT8* access; /* direct access when possible */
	59	} name_table;
	60
	61
33	62	class nes_state
34	63	{
35	64	public:
r7955	r7956
40	69	/* input_related - this part has to be cleaned up (e.g. in_2 and in_3 are not really necessary here...) */
41	70	nes_input in_0, in_1, in_2, in_3;
42	71
	72	chr_bank chr_map[8]; //quick banking structure, because some of this changes multiple times per scanline!
	73	name_table nt_page[4]; //quick banking structure for a maximum of 4K of RAM/ROM/ExRAM
	74
	75	int MMC5_floodtile;
	76	int MMC5_floodattr;
	77	UINT8 mmc5_vram[0x400];
	78	int mmc5_vram_control;
	79	UINT8 *extended_ntram;
	80
43	81	/* video-related */
44	82	int nes_vram_sprite[8]; /* Used only by mmc5 for now */
45	83	int last_frame_flip;
r7955	r7956
52	90
53	91	/* misc region to be allocated at init */
54	92	// variables which don't change at run-time
55		UINT8 *rom;
56		UINT8 *vrom;
57		UINT8 *vram;
58		UINT8 *wram;
59		UINT8 *ciram; //PPU nametable RAM - external to PPU!
	93	UINT8 *rom;
	94	UINT8 *vrom;
	95	UINT8 *vram;
	96	UINT8 *wram;
	97	UINT8 *ciram; //PPU nametable RAM - external to PPU!
60	98	// Variables which can change
61		UINT8 mid_ram_enable;
	99	UINT8 mid_ram_enable;
62	100
63	101	/* SRAM-related (we have two elements due to the init order, but it would be better to verify they both are still needed) */
64		UINT8 *battery_ram;
65		UINT8 battery_data[NES_BATTERY_SIZE];
	102	UINT8 *battery_ram;
	103	UINT8 battery_data[NES_BATTERY_SIZE];
66	104
	105	/*** Mapper-related variables ***/
	106
	107	// common ones
	108	int IRQ_enable, IRQ_enable_latch;
	109	UINT16 IRQ_count, IRQ_count_latch;
	110	UINT8 IRQ_toggle;
	111	UINT8 IRQ_reset;
	112	UINT8 IRQ_status;
	113	UINT8 IRQ_mode;
	114	int mult1, mult2;
	115
	116	UINT8 mmc_chr_source; // This is set at init to CHRROM or CHRRAM. a few mappers can swap between
	117	// the two (this is done in the specific handlers).
	118
	119	UINT8 mmc_cmd1, mmc_cmd2; // These represent registers where the mapper writes important values
	120	UINT8 mmc_count; // This is used as counter in mappers like 1 and 45
	121
	122	int mmc_prg_base, mmc_prg_mask; // MMC3 based multigame carts select a block of banks by using these (and then act like normal MMC3),
	123	int mmc_chr_base, mmc_chr_mask; // while MMC3 and clones (mapper 118 & 119) simply set them as 0 and 0xff resp.
	124
	125	UINT8 prg_bank[4]; // Many mappers writes only some bits of the selected bank (for both PRG and CHR),
	126	UINT8 vrom_bank[16]; // hence these are handy to latch bank values.
	127
	128	UINT8 extra_bank[16]; // some MMC3 clone have 2 series of PRG/CHR banks...
	129	// we collect them all here: first 4 elements PRG banks, then 6/8 CHR banks
	130
67	131	/*** NES-cart related ***/
68	132
69	133	/* load-time cart variables which remain constant */
r7955	r7956
85	149
86	150	/*** FDS-floppy related ***/
87	151
88		UINT8 *fds_data;
89		UINT8 fds_sides;
90		UINT8 *fds_ram;
	152	UINT8 *fds_data;
	153	UINT8 fds_sides;
	154	UINT8 *fds_ram;
91	155
92	156	/* Variables which can change */
93		UINT8 fds_motor_on;
94		UINT8 fds_door_closed;
95		UINT8 fds_current_side;
96		UINT32 fds_head_position;
97		UINT8 fds_status0;
98		UINT8 fds_read_mode;
99		UINT8 fds_write_reg;
	157	UINT8 fds_motor_on;
	158	UINT8 fds_door_closed;
	159	UINT8 fds_current_side;
	160	UINT32 fds_head_position;
	161	UINT8 fds_status0;
	162	UINT8 fds_read_mode;
	163	UINT8 fds_write_reg;
	164
	165	/* these are used in the mapper 20 handlers */
	166	int fds_last_side;
	167	int fds_count;
	168
	169	// misc
	170	write8_space_func mmc_write_low;
	171	read8_space_func mmc_read_low;
	172	write8_space_func mmc_write_mid;
	173	write8_space_func mmc_write;
100	174	};
101	175
102	176
r7955	r7956
105	179	WRITE8_HANDLER ( nes_IN0_w );
106	180	WRITE8_HANDLER ( nes_IN1_w );
107	181
108		extern unsigned char *nes_battery_ram;
109
110	182	/* protos */
111	183
112	184	DEVICE_IMAGE_LOAD(nes_cart);

src/mess/machine/nes.c
r7955	r7956
1	1	#include "emu.h"
2	2	#include "crsshair.h"
	3	#include "hash.h"
3	4	#include "cpu/m6502/m6502.h"
4	5	#include "video/ppu2c0x.h"
5	6	#include "includes/nes.h"
6	7	#include "machine/nes_mmc.h"
7		#include "sound/nes_apu.h"
8	8	#include "devices/cartslot.h"
9	9	#include "devices/flopdrv.h"
10		#include "formats/flopimg.h"
11		#include "image.h"
12		#include "hash.h"
13	10
14
15	11	/***************************************************************************
16	12	CONSTANTS
17	13	***************************************************************************/
r7955	r7956
100	96	/* Set up the mapper callbacks */
101	97	if (state->format == 1)
102	98	{
103		mmc_intf intf = { 0 };
104		const mmc *mapper;
105
106		mapper = nes_mapper_lookup(state->mapper);
	99	const mmc *mapper = nes_mapper_lookup(state->mapper);
107	100	if (mapper)
108	101	{
109		intf.mmc_write_low = mapper->mmc_write_low;
110		intf.mmc_read_low = mapper->mmc_read_low;
111		intf.mmc_write_mid = mapper->mmc_write_mid;
112		intf.mmc_write = mapper->mmc_write;
113		nes_mapper_init(&intf);
	102	state->mmc_write_low = mapper->mmc_write_low;
	103	state->mmc_read_low = mapper->mmc_read_low;
	104	state->mmc_write_mid = mapper->mmc_write_mid;
	105	state->mmc_write = mapper->mmc_write;
114	106	ppu_latch = mapper->ppu_latch;
115	107	}
116	108	else
117	109	{
118	110	logerror("Mapper %d is not yet supported, defaulting to no mapper.\n",state->mapper);
119		nes_mapper_init(&intf);
	111	state->mmc_write_low = NULL;
	112	state->mmc_read_low = NULL;
	113	state->mmc_write_mid = NULL;
	114	state->mmc_write = NULL;
	115	ppu_latch = NULL;
120	116	}
121	117	}
122	118	else if (state->format == 2)
123	119	{
124		mmc_intf intf = { 0 };
125		const unif *board;
126
127		board = nes_unif_lookup(state->board);
	120	const unif *board = nes_unif_lookup(state->board);
128	121	if (board)
129	122	{
130		intf.mmc_write_low = board->mmc_write_low;
131		intf.mmc_read_low = board->mmc_read_low;
132		intf.mmc_write_mid = board->mmc_write_mid;
133		intf.mmc_write = board->mmc_write;
134		nes_mapper_init(&intf);
	123	state->mmc_write_low = board->mmc_write_low;
	124	state->mmc_read_low = board->mmc_read_low;
	125	state->mmc_write_mid = board->mmc_write_mid;
	126	state->mmc_write = board->mmc_write;
135	127	ppu_latch = board->ppu_latch;
136	128	}
137	129	else
138	130	{
139	131	logerror("Board %s is not yet supported, defaulting to no mapper.\n", state->board);
140		nes_mapper_init(&intf);
	132	state->mmc_write_low = NULL;
	133	state->mmc_read_low = NULL;
	134	state->mmc_write_mid = NULL;
	135	state->mmc_write = NULL;
141	136	ppu_latch = NULL;
142	137	}
143	138	}

src/mess/machine/nes_unif.c
r7955	r7956
168	168
169	169	static void bmc_s24in1sc03_set_prg( running_machine *machine )
170	170	{
	171	nes_state state = (nes_state )machine->driver_data;
171	172	static const UINT8 masks[8] = {0x3f, 0x1f, 0x0f, 0x01, 0x03, 0x00, 0x00, 0x00};
172		UINT8 prg_flip = (mmc_cmd1 & 0x40) ? 2 : 0;
	173	UINT8 prg_flip = (state->mmc_cmd1 & 0x40) ? 2 : 0;
173	174	int prg_base = bmc_s24in1sc03_reg[1] << 1;
174	175	int prg_mask = masks[bmc_s24in1sc03_reg[0] & 0x07];
175	176
176		prg8_89(machine, prg_base \| (prg_bank[0 ^ prg_flip] & prg_mask));
177		prg8_ab(machine, prg_base \| (prg_bank[1] & prg_mask));
178		prg8_cd(machine, prg_base \| (prg_bank[2 ^ prg_flip] & prg_mask));
179		prg8_ef(machine, prg_base \| (prg_bank[3] & prg_mask));
	177	prg8_89(machine, prg_base \| (state->prg_bank[0 ^ prg_flip] & prg_mask));
	178	prg8_ab(machine, prg_base \| (state->prg_bank[1] & prg_mask));
	179	prg8_cd(machine, prg_base \| (state->prg_bank[2 ^ prg_flip] & prg_mask));
	180	prg8_ef(machine, prg_base \| (state->prg_bank[3] & prg_mask));
180	181	}
181	182
182	183	static void bmc_s24in1sc03_set_chr( running_machine *machine )
183	184	{
184		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	185	nes_state state = (nes_state )machine->driver_data;
	186	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
185	187	UINT8 chr = (bmc_s24in1sc03_reg[0] & 0x20) ? CHRRAM : CHRROM;
186	188	int chr_base = (bmc_s24in1sc03_reg[2] << 3) & 0xf00;
187	189
188		chr1_x(machine, chr_page ^ 0, chr_base \| (vrom_bank[0] & ~0x01), chr);
189		chr1_x(machine, chr_page ^ 1, chr_base \| (vrom_bank[0] \| 0x01), chr);
190		chr1_x(machine, chr_page ^ 2, chr_base \| (vrom_bank[1] & ~0x01), chr);
191		chr1_x(machine, chr_page ^ 3, chr_base \| (vrom_bank[1] \| 0x01), chr);
192		chr1_x(machine, chr_page ^ 4, chr_base \| vrom_bank[2], chr);
193		chr1_x(machine, chr_page ^ 5, chr_base \| vrom_bank[3], chr);
194		chr1_x(machine, chr_page ^ 6, chr_base \| vrom_bank[4], chr);
195		chr1_x(machine, chr_page ^ 7, chr_base \| vrom_bank[5], chr);
	190	chr1_x(machine, chr_page ^ 0, chr_base \| (state->vrom_bank[0] & ~0x01), chr);
	191	chr1_x(machine, chr_page ^ 1, chr_base \| (state->vrom_bank[0] \| 0x01), chr);
	192	chr1_x(machine, chr_page ^ 2, chr_base \| (state->vrom_bank[1] & ~0x01), chr);
	193	chr1_x(machine, chr_page ^ 3, chr_base \| (state->vrom_bank[1] \| 0x01), chr);
	194	chr1_x(machine, chr_page ^ 4, chr_base \| state->vrom_bank[2], chr);
	195	chr1_x(machine, chr_page ^ 5, chr_base \| state->vrom_bank[3], chr);
	196	chr1_x(machine, chr_page ^ 6, chr_base \| state->vrom_bank[4], chr);
	197	chr1_x(machine, chr_page ^ 7, chr_base \| state->vrom_bank[5], chr);
196	198	}
197	199
198	200	static WRITE8_HANDLER( bmc_s24in1sc03_l_w )
r7955	r7956
222	224
223	225	static WRITE8_HANDLER( bmc_s24in1sc03_w )
224	226	{
	227	nes_state state = (nes_state )space->machine->driver_data;
225	228	UINT8 cmd, bmc_s24in1sc03_helper;
226	229	LOG_MMC(("bmc_s24in1sc03_w offset: %04x, data: %02x\n", offset, data));
227	230
228	231	switch (offset & 0x6001)
229	232	{
230	233	case 0x0000:
231		bmc_s24in1sc03_helper = mmc_cmd1 ^ data;
232		mmc_cmd1 = data;
	234	bmc_s24in1sc03_helper = state->mmc_cmd1 ^ data;
	235	state->mmc_cmd1 = data;
233	236
234	237	/* Has PRG Mode changed? */
235	238	if (bmc_s24in1sc03_helper & 0x40)
r7955	r7956
241	244	break;
242	245
243	246	case 0x0001:
244		cmd = mmc_cmd1 & 0x07;
	247	cmd = state->mmc_cmd1 & 0x07;
245	248	switch (cmd)
246	249	{
247	250	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
248	251	case 2: case 3: case 4: case 5:
249		vrom_bank[cmd] = data;
	252	state->vrom_bank[cmd] = data;
250	253	bmc_s24in1sc03_set_chr(space->machine);
251	254	break;
252	255	case 6:
253	256	case 7:
254		prg_bank[cmd - 6] = data;
	257	state->prg_bank[cmd - 6] = data;
255	258	bmc_s24in1sc03_set_prg(space->machine);
256	259	break;
257	260	}
r7955	r7956
275	278
276	279	static WRITE8_HANDLER( bmc_t262_w )
277	280	{
	281	nes_state state = (nes_state )space->machine->driver_data;
278	282	UINT8 mmc_helper;
279	283	LOG_MMC(("bmc_t262_w offset: %04x, data: %02x\n", offset, data));
280	284
281		if (mmc_cmd2 \|\| offset == 0)
	285	if (state->mmc_cmd2 \|\| offset == 0)
282	286	{
283		mmc_cmd1 = (mmc_cmd1 & 0x38) \| (data & 0x07);
284		prg16_89ab(space->machine, mmc_cmd1);
	287	state->mmc_cmd1 = (state->mmc_cmd1 & 0x38) \| (data & 0x07);
	288	prg16_89ab(space->machine, state->mmc_cmd1);
285	289	}
286	290	else
287	291	{
288		mmc_cmd2 = 1;
	292	state->mmc_cmd2 = 1;
289	293	set_nt_mirroring(space->machine, BIT(data, 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
290	294	mmc_helper = ((offset >> 3) & 0x20) \| ((offset >> 2) & 0x18);
291		mmc_cmd1 = mmc_helper \| (mmc_cmd1 & 0x07);
292		prg16_89ab(space->machine, mmc_cmd1);
	295	state->mmc_cmd1 = mmc_helper \| (state->mmc_cmd1 & 0x07);
	296	prg16_89ab(space->machine, state->mmc_cmd1);
293	297	prg16_cdef(space->machine, mmc_helper \| 0x07);
294	298	}
295	299	}
r7955	r7956
306	310
307	311	static WRITE8_HANDLER( bmc_ws_m_w )
308	312	{
	313	nes_state state = (nes_state )space->machine->driver_data;
309	314	UINT8 mmc_helper;
310	315	LOG_MMC(("bmc_ws_m_w offset: %04x, data: %02x\n", offset, data));
311	316
r7955	r7956
314	319	switch (offset & 0x01)
315	320	{
316	321	case 0:
317		if (!mmc_cmd1)
	322	if (!state->mmc_cmd1)
318	323	{
319		mmc_cmd1 = data & 0x20;
	324	state->mmc_cmd1 = data & 0x20;
320	325	set_nt_mirroring(space->machine, BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
321	326	mmc_helper = (~data & 0x08) >> 3;
322	327	prg16_89ab(space->machine, data & ~mmc_helper);
r7955	r7956
324	329	}
325	330	break;
326	331	case 1:
327		if (!mmc_cmd1)
	332	if (!state->mmc_cmd1)
328	333	{
329	334	chr8(space->machine, data, CHRROM);
330	335	}
r7955	r7956
366	371
367	372	static void unl_8237_set_prg( running_machine *machine )
368	373	{
369		UINT8 prg_flip = (mmc_cmd1 & 0x40) ? 2 : 0;
	374	nes_state state = (nes_state )machine->driver_data;
	375	UINT8 prg_flip = (state->mmc_cmd1 & 0x40) ? 2 : 0;
370	376
371	377	if (!(unl_8237_reg[0] & 0x80))
372	378	{
373		prg8_89(machine, prg_bank[0 ^ prg_flip]);
374		prg8_ab(machine, prg_bank[1]);
375		prg8_cd(machine, prg_bank[2 ^ prg_flip]);
376		prg8_ef(machine, prg_bank[3]);
	379	prg8_89(machine, state->prg_bank[0 ^ prg_flip]);
	380	prg8_ab(machine, state->prg_bank[1]);
	381	prg8_cd(machine, state->prg_bank[2 ^ prg_flip]);
	382	prg8_ef(machine, state->prg_bank[3]);
377	383	}
378	384	}
379	385
380	386	static void unl_8237_set_chr( running_machine *machine )
381	387	{
382		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	388	nes_state state = (nes_state )machine->driver_data;
	389	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
383	390	UINT8 bank[8];
384	391	int i;
385	392
386	393	for(i = 0; i < 6; i++)
387		bank[i] = vrom_bank[i] \| ((unl_8237_reg[1] << 6) & 0x100);
	394	bank[i] = state->vrom_bank[i] \| ((unl_8237_reg[1] << 6) & 0x100);
388	395
389	396	chr1_x(machine, chr_page ^ 0, (bank[0] & ~0x01), CHRROM);
390	397	chr1_x(machine, chr_page ^ 1, (bank[0] \| 0x01), CHRROM);
r7955	r7956
427	434
428	435	static WRITE8_HANDLER( unl_8237_w )
429	436	{
	437	nes_state state = (nes_state )space->machine->driver_data;
430	438	UINT8 unl_8237_helper, cmd;
431	439	static const UINT8 conv_table[8] = {0,2,6,1,7,3,4,5};
432	440	LOG_MMC(("unl_8237_w offset: %04x, data: %02x\n", offset, data));
r7955	r7956
437	445	case 0x3000:
438	446	unl_8237_reg[2] = 1;
439	447	data = (data & 0xc0) \| conv_table[data & 0x07];
440		unl_8237_helper = mmc_cmd1 ^ data;
441		mmc_cmd1 = data;
	448	unl_8237_helper = state->mmc_cmd1 ^ data;
	449	state->mmc_cmd1 = data;
442	450
443	451	/* Has PRG Mode changed? */
444	452	if (unl_8237_helper & 0x40)
r7955	r7956
454	462	if (unl_8237_reg[2])
455	463	{
456	464	unl_8237_reg[2] = 0;
457		cmd = mmc_cmd1 & 0x07;
	465	cmd = state->mmc_cmd1 & 0x07;
458	466	switch (cmd)
459	467	{
460	468	case 0: case 1:
461	469	case 2: case 3: case 4: case 5:
462		vrom_bank[cmd] = data;
	470	state->vrom_bank[cmd] = data;
463	471	unl_8237_set_chr(space->machine);
464	472	break;
465	473	case 6:
466	474	case 7:
467		prg_bank[cmd - 6] = data;
	475	state->prg_bank[cmd - 6] = data;
468	476	unl_8237_set_prg(space->machine);
469	477	break;
470	478	}
r7955	r7956
499	507
500	508	static void unl_ax5705_set_prg( running_machine *machine )
501	509	{
502		prg8_89(machine, prg_bank[0]);
503		prg8_ab(machine, prg_bank[1]);
	510	nes_state state = (nes_state )machine->driver_data;
	511	prg8_89(machine, state->prg_bank[0]);
	512	prg8_ab(machine, state->prg_bank[1]);
504	513	}
505	514
506	515	static WRITE8_HANDLER( unl_ax5705_w )
507	516	{
	517	nes_state state = (nes_state )space->machine->driver_data;
508	518	UINT8 bank;
509	519	LOG_MMC(("unl_ax5705_w offset: %04x, data: %02x\n", offset, data));
510	520
511	521	switch (offset & 0x700f)
512	522	{
513	523	case 0x0000:
514		prg_bank[0] = (data & 0x05) \| ((data & 0x08) >> 2) \| ((data & 0x02) << 2);
	524	state->prg_bank[0] = (data & 0x05) \| ((data & 0x08) >> 2) \| ((data & 0x02) << 2);
515	525	unl_ax5705_set_prg(space->machine);
516	526	break;
517	527	case 0x0008:
518	528	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
519	529	break;
520	530	case 0x2000:
521		prg_bank[1] = (data & 0x05) \| ((data & 0x08) >> 2) \| ((data & 0x02) << 2);
	531	state->prg_bank[1] = (data & 0x05) \| ((data & 0x08) >> 2) \| ((data & 0x02) << 2);
522	532	unl_ax5705_set_prg(space->machine);
523	533	break;
524	534	/* CHR banks 0, 1, 4, 5 */
r7955	r7956
527	537	case 0x4008:
528	538	case 0x400a:
529	539	bank = ((offset & 0x4000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
530		vrom_bank[bank] = (vrom_bank[bank] & 0xf0) \| (data & 0x0f);
531		chr1_x(space->machine, bank, vrom_bank[bank], CHRROM);
	540	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0xf0) \| (data & 0x0f);
	541	chr1_x(space->machine, bank, state->vrom_bank[bank], CHRROM);
532	542	break;
533	543	case 0x2009:
534	544	case 0x200b:
535	545	case 0x4009:
536	546	case 0x400b:
537	547	bank = ((offset & 0x4000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
538		vrom_bank[bank] = (vrom_bank[bank] & 0x0f) \| ((data & 0x04) << 3) \| ((data & 0x02) << 5) \| ((data & 0x09) << 4);
539		chr1_x(space->machine, bank, vrom_bank[bank], CHRROM);
	548	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0x0f) \| ((data & 0x04) << 3) \| ((data & 0x02) << 5) \| ((data & 0x09) << 4);
	549	chr1_x(space->machine, bank, state->vrom_bank[bank], CHRROM);
540	550	break;
541	551	/* CHR banks 2, 3, 6, 7 */
542	552	case 0x4000:
r7955	r7956
544	554	case 0x6000:
545	555	case 0x6002:
546	556	bank = 2 + ((offset & 0x2000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
547		vrom_bank[bank] = (vrom_bank[bank] & 0xf0) \| (data & 0x0f);
548		chr1_x(space->machine, bank, vrom_bank[bank], CHRROM);
	557	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0xf0) \| (data & 0x0f);
	558	chr1_x(space->machine, bank, state->vrom_bank[bank], CHRROM);
549	559	break;
550	560	case 0x4001:
551	561	case 0x4003:
552	562	case 0x6001:
553	563	case 0x6003:
554	564	bank = 2 + ((offset & 0x2000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
555		vrom_bank[bank] = (vrom_bank[bank] & 0x0f) \| ((data & 0x04) << 3) \| ((data & 0x02) << 5) \| ((data & 0x09) << 4);
556		chr1_x(space->machine, bank, vrom_bank[bank], CHRROM);
	565	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0x0f) \| ((data & 0x04) << 3) \| ((data & 0x02) << 5) \| ((data & 0x09) << 4);
	566	chr1_x(space->machine, bank, state->vrom_bank[bank], CHRROM);
557	567	break;
558	568	}
559	569	}

src/mess/machine/nes_mmc.c
r7955	r7956
136	136	#define LOG_MMC(x) do { if (VERBOSE) logerror x; } while (0)
137	137	#define LOG_FDS(x) do { if (VERBOSE) logerror x; } while (0)
138	138
139		/PPU fast banking constants and structures /
140	139
141		#define CHRROM 0
142		#define CHRRAM 1
143
144		typedef struct
145		{
146		int source; //defines source of base pointer
147		int origin; //defines offset of 0x400 byte segment at base pointer
148		UINT8* access; //source translated + origin -> valid pointer!
149		} chr_bank;
150
151		/PPU nametable fast banking constants and structures /
152
153		#define CIRAM 0
154		#define ROM 1
155		#define EXRAM 2
156		#define MMC5FILL 3
157		#define CART_NTRAM 4
158
159		typedef struct
160		{
161		int source; /* defines source of base pointer */
162		int origin; /* defines offset of 0x400 byte segment at base pointer */
163		int writable; /* ExRAM, at least, can be write-protected AND used as nametable */
164		UINT8* access; /* direct access when possible */
165		} name_table;
166
167		/* Global variables */
168		static chr_bank chr_map[8]; //quick banking structure, because some of this changes multiple times per scanline!
169		static name_table nt_page[4]; //quick banking structure for a maximum of 4K of RAM/ROM/ExRAM
170
171		static int IRQ_enable, IRQ_enable_latch;
172		static UINT16 IRQ_count, IRQ_count_latch;
173		static UINT8 IRQ_toggle;
174		static UINT8 IRQ_reset;
175		static UINT8 IRQ_status;
176		static UINT8 IRQ_mode;
177
178		//int MMC1_extended; /* 0 = normal MMC1 cart, 1 = 512k MMC1, 2 = 1024k MMC1 */
179
180		static write8_space_func mmc_write_low;
181		static read8_space_func mmc_read_low;
182		static write8_space_func mmc_write_mid;
183		static write8_space_func mmc_write;
184
185		static int mult1, mult2;
186
187		/* common local variables */
188		static UINT8 mmc_chr_source; // This is set at init to CHRROM or CHRRAM. a few mappers can swap between
189		// the two (this is done in the specific handlers).
190
191		static UINT8 mmc_cmd1, mmc_cmd2; // These represent registers where the mapper writes important values
192		static UINT8 mmc_count; // This is used as counter in mappers like 1 and 45
193
194		static int mmc_prg_base, mmc_prg_mask; // MMC3 based multigame carts select a block of banks by using these (and then act like normal MMC3),
195		static int mmc_chr_base, mmc_chr_mask; // while MMC3 and clones (mapper 118 & 119) simply set them as 0 and 0xff resp.
196
197		static UINT8 prg_bank[4]; // Many mappers writes only some bits of the selected bank (for both PRG and CHR),
198		static UINT8 vrom_bank[16]; // hence these are handy to latch bank values.
199
200
201	140	// FIXME: mapper specific variables should be unified as much as possible to make easier future implementation of save states
202	141	/* Local variables (a few more are defined just before handlers that use them...) */
203	142
r7955	r7956
205	144
206	145	static UINT8 MMC2_regs[4]; // these replace bank0/bank0_hi/bank1/bank1_hi
207	146
208		static UINT8* extended_ntram;
209
210
211	147	static int MMC5_rom_bank_mode;
212	148	static int MMC5_vrom_bank_mode;
213	149	static int MMC5_vram_protect;
214	150	static int MMC5_scanline;
215		static int MMC5_floodtile;
216		static int MMC5_floodattr;
217		UINT8 nes_mmc5_vram[0x400];
218		int nes_mmc5_vram_control;
219	151
220		// these might be unified in single mmc_reg[] array, together with mmc_cmd1 & mmc_cmd2
221		// but be careful that MMC3 clones often use mmc_cmd1/mmc_cmd2 (from base MMC3) AND additional regs below!
	152	// these might be unified in single mmc_reg[] array, together with state->mmc_cmd1 & state->mmc_cmd2
	153	// but be careful that MMC3 clones often use state->mmc_cmd1/state->mmc_cmd2 (from base MMC3) AND additional regs below!
222	154	static UINT8 mapper45_reg[4];
223	155	static UINT8 mapper51_reg[3];
224	156	static UINT8 mapper83_reg[10];
r7955	r7956
243	175	static UINT8 bmc_s24in1sc03_reg[3];
244	176
245	177
246		static UINT8 extra_bank[16]; // some MMC3 clone have 2 series of PRG/CHR banks...
247		// we collect them all here: first 4 elements PRG banks, then 6/8 CHR banks
248
249	178	// mapper 68 needs these for NT mirroring!
250	179	static int m68_mirror;
251	180	static int m0, m1;
252	181
253
254		// FDS / mapper 20 need these for disks (to be added to fds struct?)
255		static int fds_last_side;
256		static int fds_count;
257
258	182	// Famicom Jump II is identified as Mapper 153, but it works in a completely different way.
259	183	// in particular, it requires these (not needed by other Mapper 153 games)
260	184	static UINT8 map153_reg[8];
r7955	r7956
286	210
287	211	WRITE8_HANDLER( nes_chr_w )
288	212	{
	213	nes_state state = (nes_state )space->machine->driver_data;
289	214	int bank = offset >> 10;
290		if(chr_map[bank].source == CHRRAM)
	215
	216	if (state->chr_map[bank].source == CHRRAM)
291	217	{
292		chr_map[bank].access[offset & 0x3ff] = data;
	218	state->chr_map[bank].access[offset & 0x3ff] = data;
293	219	}
294	220	}
295	221
296	222	READ8_HANDLER( nes_chr_r )
297	223	{
	224	nes_state state = (nes_state )space->machine->driver_data;
298	225	int bank = offset >> 10;
299		return chr_map[bank].access[offset & 0x3ff];
	226
	227	return state->chr_map[bank].access[offset & 0x3ff];
300	228	}
301	229
302	230	WRITE8_HANDLER( nes_nt_w )
303	231	{
	232	nes_state state = (nes_state )space->machine->driver_data;
304	233	int page = ((offset & 0xc00) >> 10);
305	234
306		if (nt_page[page].writable == 0)
	235	if (state->nt_page[page].writable == 0)
307	236	return;
308	237
309		nt_page[page].access[offset & 0x3ff] = data;
	238	state->nt_page[page].access[offset & 0x3ff] = data;
310	239	}
311	240
312	241	READ8_HANDLER( nes_nt_r )
313	242	{
	243	nes_state state = (nes_state )space->machine->driver_data;
314	244	int page = ((offset & 0xc00) >> 10);
315		if (nt_page[page].source == MMC5FILL)
	245
	246	if (state->nt_page[page].source == MMC5FILL)
316	247	{
317	248	if ((offset & 0x3ff) >= 0x3c0)
318		return MMC5_floodattr;
	249	return state->MMC5_floodattr;
319	250
320		return MMC5_floodtile;
	251	return state->MMC5_floodtile;
321	252	}
322		return nt_page[page].access[offset & 0x3ff];
	253	return state->nt_page[page].access[offset & 0x3ff];
323	254	}
324	255
325	256	WRITE8_HANDLER( nes_low_mapper_w )
326	257	{
327		if (mmc_write_low)
328		(*mmc_write_low)(space, offset, data);
	258	nes_state state = (nes_state )space->machine->driver_data;
	259
	260	if (state->mmc_write_low)
	261	(*state->mmc_write_low)(space, offset, data);
329	262	else
330	263	{
331	264	logerror("Unimplemented LOW mapper write, offset: %04x, data: %02x\n", offset, data);
r7955	r7956
341	274
342	275	READ8_HANDLER( nes_low_mapper_r )
343	276	{
344		if (mmc_read_low)
345		return (*mmc_read_low)(space, offset);
	277	nes_state state = (nes_state )space->machine->driver_data;
	278
	279	if (state->mmc_read_low)
	280	return (*state->mmc_read_low)(space, offset);
346	281	else
347	282	logerror("low mapper area read, addr: %04x\n", offset + 0x4100);
348	283
r7955	r7956
353	288	{
354	289	nes_state state = (nes_state )space->machine->driver_data;
355	290
356		if (mmc_write_mid)
357		(*mmc_write_mid)(space, offset, data);
	291	if (state->mmc_write_mid)
	292	(*state->mmc_write_mid)(space, offset, data);
358	293	else if (state->mid_ram_enable)
359	294	state->battery_ram[offset] = data;
360	295	else
r7955	r7956
382	317
383	318	WRITE8_HANDLER( nes_mapper_w )
384	319	{
385		if (mmc_write)
386		(*mmc_write)(space, offset, data);
	320	nes_state state = (nes_state )space->machine->driver_data;
	321
	322	if (state->mmc_write)
	323	(*state->mmc_write)(space, offset, data);
387	324	else
388	325	{
389	326	logerror("Unimplemented mapper write, offset: %04x, data: %02x\n", offset, data);
r7955	r7956
523	460	bank &= (state->chr_chunks - 1);
524	461	for (i = 0; i < 8; i++)
525	462	{
526		chr_map[i].source = source;
527		chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
	463	state->chr_map[i].source = source;
	464	state->chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
528	465
529	466	if (source == CHRRAM)
530		chr_map[i].access = &state->vram[chr_map[i].origin];
	467	state->chr_map[i].access = &state->vram[state->chr_map[i].origin];
531	468	else
532		chr_map[i].access = &state->vrom[chr_map[i].origin];
	469	state->chr_map[i].access = &state->vrom[state->chr_map[i].origin];
533	470	}
534	471	}
535	472
r7955	r7956
541	478	bank &= ((state->chr_chunks << 1) - 1);
542	479	for (i = 0; i < 4; i++)
543	480	{
544		chr_map[i + start].source = source;
545		chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
	481	state->chr_map[i + start].source = source;
	482	state->chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
546	483
547	484	if (source == CHRRAM)
548		chr_map[i + start].access = &state->vram[chr_map[i + start].origin];
	485	state->chr_map[i + start].access = &state->vram[state->chr_map[i + start].origin];
549	486	else
550		chr_map[i + start].access = &state->vrom[chr_map[i + start].origin];
	487	state->chr_map[i + start].access = &state->vrom[state->chr_map[i + start].origin];
551	488	}
552	489	}
553	490
r7955	r7956
569	506	bank &= ((state->chr_chunks << 2) - 1);
570	507	for (i = 0; i < 2; i++)
571	508	{
572		chr_map[i + start].source = source;
573		chr_map[i + start].origin = (bank * 0x800) + (i * 0x400);
	509	state->chr_map[i + start].source = source;
	510	state->chr_map[i + start].origin = (bank * 0x800) + (i * 0x400);
574	511
575	512	if (source == CHRRAM)
576		chr_map[i + start].access = &state->vram[chr_map[i + start].origin];
	513	state->chr_map[i + start].access = &state->vram[state->chr_map[i + start].origin];
577	514	else
578		chr_map[i + start].access = &state->vrom[chr_map[i + start].origin];
	515	state->chr_map[i + start].access = &state->vrom[state->chr_map[i + start].origin];
579	516	}
580	517	}
581	518
r7955	r7956
603	540	{
604	541	nes_state state = (nes_state )machine->driver_data;
605	542
606		chr_map[start].source = source;
	543	state->chr_map[start].source = source;
607	544	bank &= ((state->chr_chunks << 3) - 1);
608		chr_map[start].origin = bank * 0x400;
	545	state->chr_map[start].origin = bank * 0x400;
609	546
610	547	if (source == CHRRAM)
611		chr_map[start].access = &state->vram[chr_map[start].origin];
	548	state->chr_map[start].access = &state->vram[state->chr_map[start].origin];
612	549	else
613		chr_map[start].access = &state->vrom[chr_map[start].origin];
	550	state->chr_map[start].access = &state->vrom[state->chr_map[start].origin];
614	551	}
615	552
616	553	static void chr1_0 (running_machine *machine, int bank, int source)
r7955	r7956
664	601	switch (source)
665	602	{
666	603	case CART_NTRAM:
667		base_ptr = extended_ntram;
	604	base_ptr = state->extended_ntram;
668	605	break;
669	606	case MMC5FILL:
670	607	base_ptr = NULL;
r7955	r7956
673	610	base_ptr = state->vrom;
674	611	break;
675	612	case EXRAM:
676		base_ptr = nes_mmc5_vram;
	613	base_ptr = state->mmc5_vram;
677	614	break;
678	615	case CIRAM:
679	616	default:
r7955	r7956
682	619	}
683	620
684	621	page &= 3; /* mask down to the 4 logical pages */
685		nt_page[page].source = source;
686		if (NULL != base_ptr)
	622	state->nt_page[page].source = source;
	623
	624	if (base_ptr != NULL)
687	625	{
688		nt_page[page].origin = bank * 0x400;
689		nt_page[page].access = base_ptr + nt_page[page].origin;
	626	state->nt_page[page].origin = bank * 0x400;
	627	state->nt_page[page].access = base_ptr + state->nt_page[page].origin;
690	628	}
691		nt_page[page].writable = writable;
	629
	630	state->nt_page[page].writable = writable;
692	631	}
693	632
694	633	void set_nt_mirroring( running_machine *machine, int mirroring )
r7955	r7956
778	717	break;
779	718	case 1:
780	719	case 155:
781		mmc_cmd1 = 0;
782		mmc_count = 0;
	720	state->mmc_cmd1 = 0;
	721	state->mmc_count = 0;
783	722	MMC1_regs[0] = 0x0f;
784	723	MMC1_regs[1] = MMC1_regs[2] = MMC1_regs[3] = 0;
785	724	set_nt_mirroring(machine, PPU_MIRROR_HORZ);
786		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	725	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
787	726	MMC1_set_chr(machine);
788	727	MMC1_set_prg(machine);
789	728	break;
r7955	r7956
806	745	/* Only MMC3 and clones seem to use 4-screen! */
807	746	/* hardware uses an 8K RAM chip, but can't address the high 4K! */
808	747	/* that much is documented for Nintendo Gauntlet boards */
809		if(state->four_screen_vram)
	748	if (state->four_screen_vram)
810	749	{
811		extended_ntram = auto_alloc_array(machine, UINT8, 0x2000);
	750	state->extended_ntram = auto_alloc_array(machine, UINT8, 0x2000);
812	751	set_nt_page(machine, 0, CART_NTRAM, 0, 1);
813	752	set_nt_page(machine, 1, CART_NTRAM, 1, 1);
814	753	set_nt_page(machine, 2, CART_NTRAM, 2, 1);
r7955	r7956
825	764	case 196:
826	765	case 245:
827	766	case 250:
828		prg_bank[0] = prg_bank[2] = 0xfe; // prg_bank[2] & prg_bank[3] remain always the same in most MMC3 variants
829		prg_bank[1] = prg_bank[3] = 0xff; // but some pirate clone mappers change them after writing certain registers
830		mmc_cmd1 = 0;
831		mmc_cmd2 = 0x80;
832		mmc_prg_base = mmc_chr_base = 0;
833		mmc_prg_mask = mmc_chr_mask = 0xff; // these could be init'ed as xxx_chunks-1 and they would work the same
834		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
835		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
836		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	767	state->prg_bank[0] = state->prg_bank[2] = 0xfe; // prg_bank[2] & prg_bank[3] remain always the same in most MMC3 variants
	768	state->prg_bank[1] = state->prg_bank[3] = 0xff; // but some pirate clone mappers change them after writing certain registers
	769	state->mmc_cmd1 = 0;
	770	state->mmc_cmd2 = 0x80;
	771	state->mmc_prg_base = state->mmc_chr_base = 0;
	772	state->mmc_prg_mask = state->mmc_chr_mask = 0xff; // these could be init'ed as xxx_chunks-1 and they would work the same
	773	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	774	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	775	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
837	776	break;
838	777	case 5:
839	778	/* Can switch 8k prg banks, but they are saved as 16k in size */
r7955	r7956
845	784	prg16_cdef(machine, state->prg_chunks - 1);
846	785	break;
847	786	case 6:
848		mmc_cmd1 = 0;
849		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	787	state->mmc_cmd1 = 0;
	788	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
850	789	prg16_89ab(machine, 0);
851	790	prg16_cdef(machine, 7);
852	791	break;
r7955	r7956
863	802	case 9:
864	803	MMC2_regs[0] = MMC2_regs[2] = 0;
865	804	MMC2_regs[1] = MMC2_regs[3] = 0;
866		mmc_cmd1 = mmc_cmd2 = 0xfe;
	805	state->mmc_cmd1 = state->mmc_cmd2 = 0xfe;
867	806	prg8_89(machine, 0);
868	807	//ugly hack to deal with iNES header usage of chunk count.
869	808	prg8_ab(machine, (state->prg_chunks << 1) - 3);
r7955	r7956
874	813	/* Reset VROM latches */
875	814	MMC2_regs[0] = MMC2_regs[2] = 0;
876	815	MMC2_regs[1] = MMC2_regs[3] = 0;
877		mmc_cmd1 = mmc_cmd2 = 0xfe;
	816	state->mmc_cmd1 = state->mmc_cmd2 = 0xfe;
878	817	prg16_89ab(machine, 0);
879	818	prg16_cdef(machine, state->prg_chunks - 1);
880	819	break;
881	820	case 11:
882		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM; // NINA-07 has no CHRROM
	821	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM; // NINA-07 has no CHRROM
883	822	prg32(machine, 0);
884	823	break;
885	824	case 14:
886		extra_bank[2] = 0xfe;
887		extra_bank[3] = 0xff;
888		extra_bank[0] = extra_bank[1] = extra_bank[4] = extra_bank[5] = extra_bank[6] = 0;
889		extra_bank[7] = extra_bank[8] = extra_bank[9] = extra_bank[0xa] = extra_bank[0xb] = 0;
	825	state->extra_bank[2] = 0xfe;
	826	state->extra_bank[3] = 0xff;
	827	state->extra_bank[0] = state->extra_bank[1] = state->extra_bank[4] = state->extra_bank[5] = state->extra_bank[6] = 0;
	828	state->extra_bank[7] = state->extra_bank[8] = state->extra_bank[9] = state->extra_bank[0xa] = state->extra_bank[0xb] = 0;
890	829	map14_reg[0] = map14_reg[1] = 0;
891		prg_bank[0] = prg_bank[2] = 0xfe;
892		prg_bank[1] = prg_bank[3] = 0xff;
893		mmc_cmd1 = 0;
894		mmc_cmd2 = 0x80;
895		mmc_prg_base = mmc_chr_base = 0;
896		mmc_prg_mask = mmc_chr_mask = 0xff;
897		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
898		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
899		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	830	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	831	state->prg_bank[1] = state->prg_bank[3] = 0xff;
	832	state->mmc_cmd1 = 0;
	833	state->mmc_cmd2 = 0x80;
	834	state->mmc_prg_base = state->mmc_chr_base = 0;
	835	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
	836	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	837	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	838	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
900	839	break;
901	840	case 15:
902	841	set_nt_mirroring(machine, PPU_MIRROR_VERT);
r7955	r7956
907	846	case 18:
908	847	case 157:
909	848	case 159:
910		mmc_cmd1 = 0;
	849	state->mmc_cmd1 = 0;
911	850	prg16_89ab(machine, 0);
912	851	prg16_cdef(machine, state->prg_chunks - 1);
913		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	852	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
914	853	break;
915	854	case 19:
916		mmc_cmd1 = 0;
	855	state->mmc_cmd1 = 0;
917	856	prg16_89ab(machine, 0);
918	857	prg16_cdef(machine, state->prg_chunks - 1);
919		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	858	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
920	859	set_nt_mirroring(machine, PPU_MIRROR_VERT);
921	860	break;
922	861	case 20:
923		fds_last_side = 0;
924		fds_count = 0;
	862	state->fds_last_side = 0;
	863	state->fds_count = 0;
925	864	state->fds_motor_on = 0;
926	865	state->fds_door_closed = 0;
927	866	state->fds_current_side = 1;
r7955	r7956
947	886	case 207:
948	887	case 222:
949	888	case 252:
950		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	889	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
951	890	prg16_89ab(machine, 0);
952	891	prg16_cdef(machine, state->prg_chunks - 1);
953	892	break;
954	893	case 32:
955		mmc_cmd1 = 0;
	894	state->mmc_cmd1 = 0;
956	895	prg16_89ab(machine, 0);
957	896	prg16_cdef(machine, state->prg_chunks - 1);
958	897	if (state->crc_hack)
r7955	r7956
965	904	prg32(machine, 0xff);
966	905	break;
967	906	case 37:
968		prg_bank[0] = prg_bank[2] = 0xfe;
969		prg_bank[1] = prg_bank[3] = 0xff;
970		mmc_cmd1 = 0;
971		mmc_cmd2 = 0x80;
972		mmc_prg_base = mmc_chr_base = 0;
973		mmc_prg_mask = 0x07;
974		mmc_chr_mask = 0x7f;
975		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
976		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
977		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	907	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	908	state->prg_bank[1] = state->prg_bank[3] = 0xff;
	909	state->mmc_cmd1 = 0;
	910	state->mmc_cmd2 = 0x80;
	911	state->mmc_prg_base = state->mmc_chr_base = 0;
	912	state->mmc_prg_mask = 0x07;
	913	state->mmc_chr_mask = 0x7f;
	914	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	915	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	916	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
978	917	break;
979	918	case 40:
980	919	prg8_67(machine, 0xfe);
r7955	r7956
984	923	prg8_ef(machine, 0xff);
985	924	break;
986	925	case 41:
987		mmc_cmd1 = 0;
	926	state->mmc_cmd1 = 0;
988	927	prg32(machine, 0);
989	928	break;
990	929	case 42:
r7955	r7956
997	936	case 44:
998	937	case 47:
999	938	case 49:
1000		prg_bank[0] = prg_bank[2] = 0xfe;
1001		prg_bank[1] = prg_bank[3] = 0xff;
1002		mmc_cmd1 = 0;
1003		mmc_cmd2 = 0x80;
1004		mmc_prg_base = mmc_chr_base = 0;
1005		mmc_prg_mask = 0x0f;
1006		mmc_chr_mask = 0x7f;
1007		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1008		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1009		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	939	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	940	state->prg_bank[1] = state->prg_bank[3] = 0xff;
	941	state->mmc_cmd1 = 0;
	942	state->mmc_cmd2 = 0x80;
	943	state->mmc_prg_base = state->mmc_chr_base = 0;
	944	state->mmc_prg_mask = 0x0f;
	945	state->mmc_chr_mask = 0x7f;
	946	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	947	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	948	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1010	949	break;
1011	950	case 45:
1012		prg_bank[0] = prg_bank[2] = 0xfe;
1013		prg_bank[1] = prg_bank[3] = 0xff;
1014		mmc_cmd1 = 0;
1015		mmc_cmd2 = 0x80;
1016		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	951	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	952	state->prg_bank[1] = state->prg_bank[3] = 0xff;
	953	state->mmc_cmd1 = 0;
	954	state->mmc_cmd2 = 0x80;
	955	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1017	956	mapper45_reg[0] = mapper45_reg[1] = mapper45_reg[2] = mapper45_reg[3] = 0;
1018		mmc_prg_base = 0x30;
1019		mmc_prg_mask = 0x3f;
1020		mmc_chr_base = 0;
1021		mmc_chr_mask = 0x7f;
1022		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1023		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	957	state->mmc_prg_base = 0x30;
	958	state->mmc_prg_mask = 0x3f;
	959	state->mmc_chr_base = 0;
	960	state->mmc_chr_mask = 0x7f;
	961	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	962	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1024	963	memory_set_bankptr(machine, "bank5", state->wram);
1025	964	break;
1026	965	case 46:
r7955	r7956
1045	984	mapper51_set_banks(machine);
1046	985	break;
1047	986	case 52:
1048		prg_bank[0] = 0xfe;
1049		prg_bank[2] = 0xfe;
1050		prg_bank[1] = 0xff;
1051		prg_bank[3] = 0xff;
1052		mmc_cmd1 = 0;
1053		mmc_cmd2 = 0x80;
	987	state->prg_bank[0] = 0xfe;
	988	state->prg_bank[2] = 0xfe;
	989	state->prg_bank[1] = 0xff;
	990	state->prg_bank[3] = 0xff;
	991	state->mmc_cmd1 = 0;
	992	state->mmc_cmd2 = 0x80;
1054	993	map52_reg_written = 0;
1055		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1056		mmc_prg_base = 0;
1057		mmc_prg_mask = 0x1f;
1058		mmc_chr_base = 0;
1059		mmc_chr_mask = 0xff;
1060		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1061		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	994	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	995	state->mmc_prg_base = 0;
	996	state->mmc_prg_mask = 0x1f;
	997	state->mmc_chr_base = 0;
	998	state->mmc_chr_mask = 0xff;
	999	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1000	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1062	1001	memory_set_bankptr(machine, "bank5", state->wram);
1063	1002	break;
1064	1003	case 57:
1065		mmc_cmd1 = 0x00;
1066		mmc_cmd2 = 0x00;
	1004	state->mmc_cmd1 = 0x00;
	1005	state->mmc_cmd2 = 0x00;
1067	1006	prg16_89ab(machine, 0);
1068	1007	prg16_cdef(machine, 0);
1069	1008	chr8(machine, 0, CHRROM);
r7955	r7956
1079	1018	break;
1080	1019	case 64:
1081	1020	case 158:
1082		mmc_cmd1 = 0;
	1021	state->mmc_cmd1 = 0;
1083	1022	prg16_89ab(machine, state->prg_chunks - 1);
1084	1023	prg16_cdef(machine, state->prg_chunks - 1);
1085	1024	break;
r7955	r7956
1115	1054	chr2_2(machine, 1, CHRROM);
1116	1055	chr2_4(machine, 2, CHRROM);
1117	1056	chr2_6(machine, 3, CHRROM);
1118		mmc_cmd1 = 0;
	1057	state->mmc_cmd1 = 0;
1119	1058	break;
1120	1059	case 77:
1121	1060	prg32(machine, 0);
r7955	r7956
1168	1107	prg16_cdef(machine, state->prg_chunks - 1);
1169	1108	break;
1170	1109	case 112:
1171		mmc_cmd1 = 0;
	1110	state->mmc_cmd1 = 0;
1172	1111	prg16_89ab(machine, 0);
1173	1112	prg16_cdef(machine, state->prg_chunks - 1);
1174	1113	break;
r7955	r7956
1201	1140	break;
1202	1141	case 114:
1203	1142	map114_reg = map114_reg_enabled = 0;
1204		prg_bank[0] = prg_bank[2] = 0xfe;
1205		prg_bank[1] = prg_bank[3] = 0xff;
1206		mmc_cmd1 = 0;
1207		mmc_cmd2 = 0x80;
1208		mmc_prg_base = mmc_chr_base = 0;
1209		mmc_prg_mask = mmc_chr_mask = 0xff;
1210		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1211		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1212		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1143	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	1144	state->prg_bank[1] = state->prg_bank[3] = 0xff;
	1145	state->mmc_cmd1 = 0;
	1146	state->mmc_cmd2 = 0x80;
	1147	state->mmc_prg_base = state->mmc_chr_base = 0;
	1148	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
	1149	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1150	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1151	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1213	1152	break;
1214	1153	case 115:
1215	1154	mapper115_reg[0] = 0;
1216		prg_bank[0] = prg_bank[2] = 0xfe;
1217		prg_bank[1] = prg_bank[3] = 0xff;
1218		mmc_cmd1 = 0;
1219		mmc_cmd2 = 0x80;
1220		mmc_prg_base = mmc_chr_base = 0;
1221		mmc_prg_mask = mmc_chr_mask = 0xff;
1222		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1223		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1224		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1155	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	1156	state->prg_bank[1] = state->prg_bank[3] = 0xff;
	1157	state->mmc_cmd1 = 0;
	1158	state->mmc_cmd2 = 0x80;
	1159	state->mmc_prg_base = state->mmc_chr_base = 0;
	1160	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
	1161	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1162	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1163	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1225	1164	break;
1226	1165	case 121:
1227		prg_bank[0] = prg_bank[2] = 0xfe;
1228		prg_bank[1] = prg_bank[3] = 0xff;
	1166	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	1167	state->prg_bank[1] = state->prg_bank[3] = 0xff;
1229	1168	mapper121_reg[0] = mapper121_reg[1] = mapper121_reg[2] = 0;
1230		mmc_cmd1 = 0;
1231		mmc_cmd2 = 0x80;
1232		mmc_prg_base = mmc_chr_base = 0;
1233		mmc_prg_mask = mmc_chr_mask = 0xff;
1234		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1235		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1236		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1169	state->mmc_cmd1 = 0;
	1170	state->mmc_cmd2 = 0x80;
	1171	state->mmc_prg_base = state->mmc_chr_base = 0;
	1172	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
	1173	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1174	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1175	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1237	1176	break;
1238	1177	case 132:
1239	1178	case 172:
r7955	r7956
1242	1181	prg32(machine, 0);
1243	1182	break;
1244	1183	case 134:
1245		prg_bank[0] = prg_bank[2] = 0xfe;
1246		prg_bank[1] = prg_bank[3] = 0xff;
1247		mmc_cmd1 = 0;
1248		mmc_cmd2 = 0x80;
1249		mmc_prg_base = mmc_chr_base = 0;
1250		mmc_prg_mask = 0x1f;
1251		mmc_chr_mask = 0xff;
1252		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1253		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1254		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1184	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	1185	state->prg_bank[1] = state->prg_bank[3] = 0xff;
	1186	state->mmc_cmd1 = 0;
	1187	state->mmc_cmd2 = 0x80;
	1188	state->mmc_prg_base = state->mmc_chr_base = 0;
	1189	state->mmc_prg_mask = 0x1f;
	1190	state->mmc_chr_mask = 0xff;
	1191	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1192	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1193	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1255	1194	break;
1256	1195	case 166:
1257	1196	subor_reg[0] = subor_reg[1] = subor_reg[2] = subor_reg[3] = 0;
r7955	r7956
1264	1203	prg16_cdef(machine, 0x20);
1265	1204	break;
1266	1205	case 136:
1267		mmc_cmd1 = 0;
	1206	state->mmc_cmd1 = 0;
1268	1207	prg32(machine, 0);
1269	1208	break;
1270	1209	case 137:
1271		mmc_cmd1 = 0;
	1210	state->mmc_cmd1 = 0;
1272	1211	prg32(machine, 0);
1273	1212	chr8(machine, state->chr_chunks - 1, CHRROM);
1274	1213	set_nt_mirroring(machine, PPU_MIRROR_VERT);
r7955	r7956
1276	1215	case 138:
1277	1216	case 139:
1278	1217	case 141:
1279		mmc_cmd1 = 0;
1280		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1218	state->mmc_cmd1 = 0;
	1219	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1281	1220	prg32(machine, 0);
1282		chr8(machine, 0, mmc_chr_source);
	1221	chr8(machine, 0, state->mmc_chr_source);
1283	1222	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1284	1223	break;
1285	1224	case 143:
r7955	r7956
1297	1236	chr8(machine, 0, CHRROM);
1298	1237	break;
1299	1238	case 150:
1300		mmc_cmd1 = 0;
	1239	state->mmc_cmd1 = 0;
1301	1240	prg32(machine, 0);
1302	1241	chr8(machine, 0, CHRROM);
1303	1242	set_nt_mirroring(machine, PPU_MIRROR_VERT);
r7955	r7956
1308	1247	chr8(machine, 0, CHRROM);
1309	1248	break;
1310	1249	case 153:
1311		mmc_cmd1 = 0;
	1250	state->mmc_cmd1 = 0;
1312	1251	prg16_89ab(machine, 0);
1313	1252	prg16_cdef(machine, state->prg_chunks - 1);
1314		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1253	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1315	1254	// Famicom Jump II needs also the following!
1316	1255	for (i = 0; i < 8; i++)
1317	1256	map153_reg[i] = 0;
r7955	r7956
1337	1276	prg32(machine, (state->prg_chunks - 1) >> 1);
1338	1277	break;
1339	1278	case 178:
1340		mmc_cmd1 = 0;
	1279	state->mmc_cmd1 = 0;
1341	1280	prg32(machine, 0);
1342	1281	break;
1343	1282	case 180:
r7955	r7956
1352	1291	prg16_cdef(machine, (state->prg_chunks - 1) ^ 0x08);
1353	1292	break;
1354	1293	case 187:
1355		prg_bank[0] = prg_bank[2] = 0xfe;
1356		prg_bank[1] = prg_bank[3] = 0xff;
	1294	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	1295	state->prg_bank[1] = state->prg_bank[3] = 0xff;
1357	1296	mapper187_reg[0] = mapper187_reg[1] = mapper187_reg[2] = mapper187_reg[3] = 0;
1358		mmc_cmd1 = 0;
1359		mmc_cmd2 = 0x80;
1360		mmc_prg_base = mmc_chr_base = 0;
1361		mmc_prg_mask = mmc_chr_mask = 0xff;
1362		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1363		mapper187_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1364		mapper187_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1297	state->mmc_cmd1 = 0;
	1298	state->mmc_cmd2 = 0x80;
	1299	state->mmc_prg_base = state->mmc_chr_base = 0;
	1300	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
	1301	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1302	mapper187_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1303	mapper187_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1365	1304	break;
1366	1305	case 189:
1367		mmc_cmd1 = 0;
1368		mmc_cmd2 = 0x80;
1369		mmc_chr_base = 0;
1370		mmc_chr_mask = 0xff;
1371		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1306	state->mmc_cmd1 = 0;
	1307	state->mmc_cmd2 = 0x80;
	1308	state->mmc_chr_base = 0;
	1309	state->mmc_chr_mask = 0xff;
	1310	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1372	1311	prg32(machine, 0);
1373		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1312	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1374	1313	break;
1375	1314	case 193:
1376	1315	prg32(machine, (state->prg_chunks - 1) >> 1);
1377	1316	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1378	1317	break;
1379	1318	case 197:
1380		prg_bank[0] = prg_bank[2] = 0xfe;
1381		prg_bank[1] = prg_bank[3] = 0xff;
1382		mmc_cmd1 = 0;
1383		mmc_cmd2 = 0x80;
1384		mmc_prg_base = mmc_chr_base = 0;
1385		mmc_prg_mask = mmc_chr_mask = 0xff;
1386		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1387		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1388		mapper197_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1319	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	1320	state->prg_bank[1] = state->prg_bank[3] = 0xff;
	1321	state->mmc_cmd1 = 0;
	1322	state->mmc_cmd2 = 0x80;
	1323	state->mmc_prg_base = state->mmc_chr_base = 0;
	1324	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
	1325	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1326	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1327	mapper197_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1389	1328	break;
1390	1329	case 198:
1391		prg_bank[0] = 0x00;
1392		prg_bank[1] = 0x01;
1393		prg_bank[2] = 0x4e;
1394		prg_bank[3] = 0x4f;
1395		mmc_cmd1 = 0;
1396		mmc_cmd2 = 0x80;
1397		mmc_prg_base = mmc_chr_base = 0;
1398		mmc_prg_mask = mmc_chr_mask = 0xff;
1399		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1400		mapper198_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1401		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1330	state->prg_bank[0] = 0x00;
	1331	state->prg_bank[1] = 0x01;
	1332	state->prg_bank[2] = 0x4e;
	1333	state->prg_bank[3] = 0x4f;
	1334	state->mmc_cmd1 = 0;
	1335	state->mmc_cmd2 = 0x80;
	1336	state->mmc_prg_base = state->mmc_chr_base = 0;
	1337	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
	1338	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1339	mapper198_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1340	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1402	1341	break;
1403	1342	case 199:
1404		prg_bank[0] = 0x00;
1405		prg_bank[1] = 0x01;
1406		prg_bank[2] = 0x3e;
1407		prg_bank[3] = 0x3f;
1408		mmc_cmd1 = 0;
1409		mmc_cmd2 = 0x80;
1410		mmc_prg_base = mmc_chr_base = 0;
1411		mmc_prg_mask = mmc_chr_mask = 0xff;
1412		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1413		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1414		mapper199_set_chr(machine, mmc_chr_base, mmc_chr_mask);
	1343	state->prg_bank[0] = 0x00;
	1344	state->prg_bank[1] = 0x01;
	1345	state->prg_bank[2] = 0x3e;
	1346	state->prg_bank[3] = 0x3f;
	1347	state->mmc_cmd1 = 0;
	1348	state->mmc_cmd2 = 0x80;
	1349	state->mmc_prg_base = state->mmc_chr_base = 0;
	1350	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
	1351	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1352	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1353	mapper199_set_chr(machine, state->mmc_chr_base, state->mmc_chr_mask);
1415	1354	break;
1416	1355	case 200:
1417	1356	prg16_89ab(machine, state->prg_chunks - 1);
r7955	r7956
1431	1370	chr8(machine, 0, CHRROM);
1432	1371	break;
1433	1372	case 205:
1434		prg_bank[0] = prg_bank[2] = 0xfe;
1435		prg_bank[1] = prg_bank[3] = 0xff;
1436		mmc_cmd1 = 0;
1437		mmc_cmd2 = 0x80;
1438		mmc_prg_base = 0x10;
1439		mmc_prg_mask = 0x1f;
1440		mmc_chr_base = 0;
1441		mmc_chr_mask = 0xff;
1442		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1443		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1444		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1373	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	1374	state->prg_bank[1] = state->prg_bank[3] = 0xff;
	1375	state->mmc_cmd1 = 0;
	1376	state->mmc_cmd2 = 0x80;
	1377	state->mmc_prg_base = 0x10;
	1378	state->mmc_prg_mask = 0x1f;
	1379	state->mmc_chr_base = 0;
	1380	state->mmc_chr_mask = 0xff;
	1381	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1382	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1383	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1445	1384	break;
1446	1385	case 208:
1447		prg_bank[0] = prg_bank[2] = 0xfe;
1448		prg_bank[1] = prg_bank[3] = 0xff;
	1386	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	1387	state->prg_bank[1] = state->prg_bank[3] = 0xff;
1449	1388	map208_reg[0] = map208_reg[1] = map208_reg[2] = map208_reg[3] = map208_reg[4] = 0;
1450		mmc_cmd1 = 0;
1451		mmc_cmd2 = 0x80;
1452		mmc_prg_base = mmc_chr_base = 0;
1453		mmc_prg_mask = mmc_chr_mask = 0xff;
1454		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1455		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1456		mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1389	state->mmc_cmd1 = 0;
	1390	state->mmc_cmd2 = 0x80;
	1391	state->mmc_prg_base = state->mmc_chr_base = 0;
	1392	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
	1393	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1394	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1395	mapper4_set_chr(machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1457	1396	break;
1458	1397	case 212:
1459	1398	chr8(machine, 0xff, CHRROM);
1460	1399	prg32(machine, 0xff);
1461	1400	break;
1462	1401	case 215:
1463		prg_bank[0] = 0x00;
1464		prg_bank[2] = 0xfe;
1465		prg_bank[1] = 0x01;
1466		prg_bank[3] = 0xff;
1467		mmc_cmd1 = 0;
1468		mmc_cmd2 = 0x80;
	1402	state->prg_bank[0] = 0x00;
	1403	state->prg_bank[2] = 0xfe;
	1404	state->prg_bank[1] = 0x01;
	1405	state->prg_bank[3] = 0xff;
	1406	state->mmc_cmd1 = 0;
	1407	state->mmc_cmd2 = 0x80;
1469	1408	map215_reg[0] = 0x00;
1470	1409	map215_reg[1] = 0xff;
1471	1410	map215_reg[2] = 0x04;
1472	1411	map215_reg[3] = 0;
1473		mmc_prg_base = 0;
1474		mmc_prg_mask = 0x1f;
1475		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1476		mapper215_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1477		mapper215_set_chr(machine, mmc_chr_source);
	1412	state->mmc_prg_base = 0;
	1413	state->mmc_prg_mask = 0x1f;
	1414	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1415	mapper215_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1416	mapper215_set_chr(machine, state->mmc_chr_source);
1478	1417	break;
1479	1418	case 216:
1480		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1419	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1481	1420	prg32(machine, 0);
1482		chr8(machine, 0, mmc_chr_source);
	1421	chr8(machine, 0, state->mmc_chr_source);
1483	1422	break;
1484	1423	case 217:
1485	1424	map217_reg[0] = 0x00;
1486	1425	map217_reg[1] = 0xff;
1487	1426	map217_reg[2] = 0x03;
1488	1427	map217_reg[3] = 0;
1489		prg_bank[0] = prg_bank[2] = 0xfe;
1490		prg_bank[1] = prg_bank[3] = 0xff;
1491		mmc_cmd1 = 0;
1492		mmc_cmd2 = 0x80;
1493		mmc_prg_base = mmc_chr_base = 0;
1494		mmc_prg_mask = mmc_chr_mask = 0xff;
1495		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1496		mapper217_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1497		mapper217_set_chr(machine, mmc_chr_source);
	1428	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	1429	state->prg_bank[1] = state->prg_bank[3] = 0xff;
	1430	state->mmc_cmd1 = 0;
	1431	state->mmc_cmd2 = 0x80;
	1432	state->mmc_prg_base = state->mmc_chr_base = 0;
	1433	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
	1434	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1435	mapper217_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1436	mapper217_set_chr(machine, state->mmc_chr_source);
1498	1437	break;
1499	1438	case 221:
1500		mmc_cmd1 = 0;
1501		mmc_cmd2 = 0;
	1439	state->mmc_cmd1 = 0;
	1440	state->mmc_cmd2 = 0;
1502	1441	prg16_89ab(machine, 0);
1503	1442	prg16_cdef(machine, 0);
1504	1443	break;
r7955	r7956
1506	1445	prg32(machine, 0);
1507	1446	break;
1508	1447	case 226:
1509		mmc_cmd1 = 0;
1510		mmc_cmd2 = 0;
	1448	state->mmc_cmd1 = 0;
	1449	state->mmc_cmd2 = 0;
1511	1450	prg32(machine, 0);
1512	1451	break;
1513	1452	case 227:
r7955	r7956
1531	1470	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1532	1471	break;
1533	1472	case 232:
1534		mmc_cmd1 = 0x18;
1535		mmc_cmd2 = 0x00;
	1473	state->mmc_cmd1 = 0x18;
	1474	state->mmc_cmd2 = 0x00;
1536	1475	mapper232_set_prg(machine);
1537	1476	break;
1538	1477	case 243:
1539		vrom_bank[0] = 3;
1540		mmc_cmd1 = 0;
	1478	state->vrom_bank[0] = 3;
	1479	state->mmc_cmd1 = 0;
1541	1480	chr8(machine, 3, CHRROM);
1542	1481	prg32(machine, 0);
1543	1482	set_nt_mirroring(machine, PPU_MIRROR_VERT);
r7955	r7956
1546	1485	prg32(machine, 0xff);
1547	1486	break;
1548	1487	case 249:
1549		prg_bank[0] = prg_bank[2] = 0xfe;
1550		prg_bank[1] = prg_bank[3] = 0xff;
1551		mmc_cmd1 = 0;
1552		mmc_cmd2 = 0x80;
	1488	state->prg_bank[0] = state->prg_bank[2] = 0xfe;
	1489	state->prg_bank[1] = state->prg_bank[3] = 0xff;
	1490	state->mmc_cmd1 = 0;
	1491	state->mmc_cmd2 = 0x80;
1553	1492	map249_reg = 0;
1554		mmc_prg_base = mmc_chr_base = 0;
1555		mmc_prg_mask = mmc_chr_mask = 0xff;
1556		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1557		mapper249_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1558		mapper249_set_chr(machine, mmc_chr_base, mmc_chr_mask);
	1493	state->mmc_prg_base = state->mmc_chr_base = 0;
	1494	state->mmc_prg_mask = state->mmc_chr_mask = 0xff;
	1495	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1496	mapper249_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
	1497	mapper249_set_chr(machine, state->mmc_chr_base, state->mmc_chr_mask);
1559	1498	break;
1560	1499	default:
1561	1500	/* Mapper not supported */
r7955	r7956
1604	1543
1605	1544	mapper_warning = 0;
1606	1545
1607		nes_mmc5_vram_control = 0;
	1546	state->mmc5_vram_control = 0;
1608	1547
1609	1548	/* Point the WRAM/battery area to the first RAM bank */
1610	1549	if (mmc_num != 20)
r7955	r7956
1612	1551
1613	1552	/* Here, we init a few helpers: 4 prg banks and 16 chr banks - some mappers use them */
1614	1553	for (i = 0; i < 4; i++)
1615		prg_bank[i] = 0;
	1554	state->prg_bank[i] = 0;
1616	1555	for (i = 0; i < 16; i++)
1617		vrom_bank[i] = 0;
	1556	state->vrom_bank[i] = 0;
1618	1557	for (i = 0; i < 16; i++)
1619		extra_bank[i] = 0;
	1558	state->extra_bank[i] = 0;
1620	1559
1621	1560	/* Finally, we init IRQ-related quantities. */
1622		IRQ_enable = IRQ_enable_latch = 0;
1623		IRQ_count = IRQ_count_latch = 0;
1624		IRQ_toggle = 0;
	1561	state->IRQ_enable = state->IRQ_enable_latch = 0;
	1562	state->IRQ_count = state->IRQ_count_latch = 0;
	1563	state->IRQ_toggle = 0;
1625	1564
1626	1565	err = mapper_initialize(machine, mmc_num);
1627	1566
1628	1567	return err;
1629	1568	}
1630	1569
1631		void nes_mapper_init(const mmc_intf *intf)
1632		{
1633		mmc_write_low = intf->mmc_write_low;
1634		mmc_read_low = intf->mmc_read_low;
1635		mmc_write_mid = intf->mmc_write_mid;
1636		mmc_write = intf->mmc_write;
1637		}
1638
1639	1570	/*************************************************************
1640	1571
1641	1572	Support for .unf Files
r7955	r7956
1699	1630	bmc_s24in1sc03_reg[0] = 0x24;
1700	1631	bmc_s24in1sc03_reg[1] = 0x9f;
1701	1632	bmc_s24in1sc03_reg[2] = 0;
1702		prg_bank[0] = 0xfe;
1703		prg_bank[1] = 0xff;
1704		prg_bank[2] = 0xfe;
1705		prg_bank[3] = 0xff;
1706		mmc_cmd1 = 0;
1707		mmc_cmd2 = 0x80;
	1633	state->prg_bank[0] = 0xfe;
	1634	state->prg_bank[1] = 0xff;
	1635	state->prg_bank[2] = 0xfe;
	1636	state->prg_bank[3] = 0xff;
	1637	state->mmc_cmd1 = 0;
	1638	state->mmc_cmd2 = 0x80;
1708	1639	bmc_s24in1sc03_set_prg(machine);
1709	1640	bmc_s24in1sc03_set_chr(machine);
1710	1641	break;
1711	1642	case BMC_T262:
1712		mmc_cmd1 = 0;
1713		mmc_cmd2 = 0;
	1643	state->mmc_cmd1 = 0;
	1644	state->mmc_cmd2 = 0;
1714	1645	prg16_89ab(machine, 0);
1715	1646	prg16_cdef(machine, 7);
1716	1647	break;
1717	1648	case BMC_WS:
1718		mmc_cmd1 = 0;
	1649	state->mmc_cmd1 = 0;
1719	1650	prg32(machine, 0);
1720	1651	break;
1721	1652	case DREAMTECH:
r7955	r7956
1725	1656	break;
1726	1657	case UNL_8237:
1727	1658	unl_8237_reg[0] = unl_8237_reg[1] = unl_8237_reg[2] = 0;
1728		prg_bank[0] = 0x00;
1729		prg_bank[1] = 0x01;
1730		prg_bank[2] = 0xfe;
1731		prg_bank[3] = 0xff;
1732		mmc_cmd1 = 0;
1733		mmc_cmd2 = 0x80;
	1659	state->prg_bank[0] = 0x00;
	1660	state->prg_bank[1] = 0x01;
	1661	state->prg_bank[2] = 0xfe;
	1662	state->prg_bank[3] = 0xff;
	1663	state->mmc_cmd1 = 0;
	1664	state->mmc_cmd2 = 0x80;
1734	1665	unl_8237_set_prg(machine);
1735	1666	unl_8237_set_chr(machine);
1736	1667	break;
1737	1668	case UNL_AX5705:
1738		prg_bank[0] = 0;
1739		prg_bank[1] = 1;
1740		prg8_89(machine, prg_bank[0]);
1741		prg8_ab(machine, prg_bank[1]);
	1669	state->prg_bank[0] = 0;
	1670	state->prg_bank[1] = 1;
	1671	prg8_89(machine, state->prg_bank[0]);
	1672	prg8_ab(machine, state->prg_bank[1]);
1742	1673	prg8_cd(machine, 0xfe);
1743	1674	prg8_ef(machine, 0xff);
1744	1675	break;
r7955	r7956
1750	1681	mapper_initialize(machine, 4);
1751	1682	break;
1752	1683	case UNL_T230:
1753		mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	1684	state->mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1754	1685	prg16_89ab(machine, 0);
1755	1686	prg16_cdef(machine, state->prg_chunks - 1);
1756	1687	break;

src/mess/machine/nes_mmc.h
r7955	r7956
52	52
53	53	#define MMC5_VRAM
54	54
55		extern UINT8 nes_mmc5_vram[0x400];
56		extern int nes_mmc5_vram_control;
57
58	55	void nes_mapper_init( const mmc_intf *intf );
59	56	int nes_mapper_reset( running_machine *machine, int mapperNum );
60	57	int nes_unif_reset( running_machine machine, const char board );

src/mess/machine/nes_ines.c
r7955	r7956
69	69
70	70	static void MMC1_set_chr( running_machine *machine )
71	71	{
	72	nes_state state = (nes_state )machine->driver_data;
72	73	UINT8 chr_mode = MMC1_regs[0] & 0x10;
73	74
74	75	if (chr_mode)
75	76	{
76		chr4_0(machine, MMC1_regs[1] & 0x1f, mmc_chr_source);
77		chr4_4(machine, MMC1_regs[2] & 0x1f, mmc_chr_source);
	77	chr4_0(machine, MMC1_regs[1] & 0x1f, state->mmc_chr_source);
	78	chr4_4(machine, MMC1_regs[2] & 0x1f, state->mmc_chr_source);
78	79	}
79	80	else
80		chr8(machine, (MMC1_regs[1] & 0x1f) >> 1, mmc_chr_source);
	81	chr8(machine, (MMC1_regs[1] & 0x1f) >> 1, state->mmc_chr_source);
81	82	}
82	83
83	84	static WRITE8_HANDLER( mapper1_w )
84	85	{
	86	nes_state state = (nes_state )space->machine->driver_data;
85	87	/* Note that there is only one latch and shift counter, shared amongst the 4 regs */
86	88	/* Space Shuttle will not work if they have independent variables. */
87	89	LOG_MMC(("mapper1_w offset: %04x, data: %02x\n", offset, data));
r7955	r7956
92	94	AD&D Hillsfar and Bill & Ted rely on this behavior!! */
93	95	if (data & 0x80)
94	96	{
95		mmc_count = 0;
96		mmc_cmd1 = 0;
	97	state->mmc_count = 0;
	98	state->mmc_cmd1 = 0;
97	99
98	100	/* Set reg at 0x8000 to size 16k and lower half swap - needed for Robocop 3, Dynowars */
99	101	MMC1_regs[0] \|= 0x0c;
r7955	r7956
103	105	return;
104	106	}
105	107
106		if (mmc_count < 5)
	108	if (state->mmc_count < 5)
107	109	{
108		if (mmc_count == 0) mmc_cmd1 = 0;
109		mmc_cmd1 >>= 1;
110		mmc_cmd1 \|= (data & 0x01) ? 0x10 : 0x00;
111		mmc_count++;
	110	if (state->mmc_count == 0) state->mmc_cmd1 = 0;
	111	state->mmc_cmd1 >>= 1;
	112	state->mmc_cmd1 \|= (data & 0x01) ? 0x10 : 0x00;
	113	state->mmc_count++;
112	114	}
113	115
114		if (mmc_count == 5)
	116	if (state->mmc_count == 5)
115	117	{
116	118	switch (offset & 0x6000) /* Which reg shall we write to? */
117	119	{
118	120	case 0x0000:
119		MMC1_regs[0] = mmc_cmd1;
	121	MMC1_regs[0] = state->mmc_cmd1;
120	122
121	123	switch (MMC1_regs[0] & 0x03)
122	124	{
r7955	r7956
129	131	MMC1_set_prg(space->machine);
130	132	break;
131	133	case 0x2000:
132		MMC1_regs[1] = mmc_cmd1;
	134	MMC1_regs[1] = state->mmc_cmd1;
133	135	MMC1_set_chr(space->machine);
134	136	MMC1_set_prg(space->machine);
135	137	break;
136	138	case 0x4000:
137		MMC1_regs[2] = mmc_cmd1;
	139	MMC1_regs[2] = state->mmc_cmd1;
138	140	MMC1_set_chr(space->machine);
139	141	break;
140	142	case 0x6000:
141		MMC1_regs[3] = mmc_cmd1;
	143	MMC1_regs[3] = state->mmc_cmd1;
142	144	MMC1_set_prg(space->machine);
143	145	break;
144	146	}
145	147
146		mmc_count = 0;
	148	state->mmc_count = 0;
147	149	}
148	150	}
149	151
r7955	r7956
213	215
214	216	static void mapper4_set_prg( running_machine *machine, int prg_base, int prg_mask )
215	217	{
216		UINT8 prg_flip = (mmc_cmd1 & 0x40) ? 2 : 0;
	218	nes_state state = (nes_state )machine->driver_data;
	219	UINT8 prg_flip = (state->mmc_cmd1 & 0x40) ? 2 : 0;
217	220
218		prg8_89(machine, prg_base \| (prg_bank[0 ^ prg_flip] & prg_mask));
219		prg8_ab(machine, prg_base \| (prg_bank[1] & prg_mask));
220		prg8_cd(machine, prg_base \| (prg_bank[2 ^ prg_flip] & prg_mask));
221		prg8_ef(machine, prg_base \| (prg_bank[3] & prg_mask));
	221	prg8_89(machine, prg_base \| (state->prg_bank[0 ^ prg_flip] & prg_mask));
	222	prg8_ab(machine, prg_base \| (state->prg_bank[1] & prg_mask));
	223	prg8_cd(machine, prg_base \| (state->prg_bank[2 ^ prg_flip] & prg_mask));
	224	prg8_ef(machine, prg_base \| (state->prg_bank[3] & prg_mask));
222	225	}
223	226
224	227	static void mapper4_set_chr( running_machine *machine, UINT8 chr, int chr_base, int chr_mask )
225	228	{
226		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	229	nes_state state = (nes_state )machine->driver_data;
	230	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
227	231
228		chr1_x(machine, chr_page ^ 0, chr_base \| ((vrom_bank[0] & ~0x01) & chr_mask), chr);
229		chr1_x(machine, chr_page ^ 1, chr_base \| ((vrom_bank[0] \| 0x01) & chr_mask), chr);
230		chr1_x(machine, chr_page ^ 2, chr_base \| ((vrom_bank[1] & ~0x01) & chr_mask), chr);
231		chr1_x(machine, chr_page ^ 3, chr_base \| ((vrom_bank[1] \| 0x01) & chr_mask), chr);
232		chr1_x(machine, chr_page ^ 4, chr_base \| (vrom_bank[2] & chr_mask), chr);
233		chr1_x(machine, chr_page ^ 5, chr_base \| (vrom_bank[3] & chr_mask), chr);
234		chr1_x(machine, chr_page ^ 6, chr_base \| (vrom_bank[4] & chr_mask), chr);
235		chr1_x(machine, chr_page ^ 7, chr_base \| (vrom_bank[5] & chr_mask), chr);
	232	chr1_x(machine, chr_page ^ 0, chr_base \| ((state->vrom_bank[0] & ~0x01) & chr_mask), chr);
	233	chr1_x(machine, chr_page ^ 1, chr_base \| ((state->vrom_bank[0] \| 0x01) & chr_mask), chr);
	234	chr1_x(machine, chr_page ^ 2, chr_base \| ((state->vrom_bank[1] & ~0x01) & chr_mask), chr);
	235	chr1_x(machine, chr_page ^ 3, chr_base \| ((state->vrom_bank[1] \| 0x01) & chr_mask), chr);
	236	chr1_x(machine, chr_page ^ 4, chr_base \| (state->vrom_bank[2] & chr_mask), chr);
	237	chr1_x(machine, chr_page ^ 5, chr_base \| (state->vrom_bank[3] & chr_mask), chr);
	238	chr1_x(machine, chr_page ^ 6, chr_base \| (state->vrom_bank[4] & chr_mask), chr);
	239	chr1_x(machine, chr_page ^ 7, chr_base \| (state->vrom_bank[5] & chr_mask), chr);
236	240	}
237	241
238	242	/* Here, IRQ counter decrements every scanline. */
239	243	static void mapper4_irq( running_device *device, int scanline, int vblank, int blanked )
240	244	{
	245	nes_state state = (nes_state )device->machine->driver_data;
	246
241	247	if (scanline < PPU_BOTTOM_VISIBLE_SCANLINE)
242	248	{
243		int priorCount = IRQ_count;
244		if ((IRQ_count == 0))
	249	int priorCount = state->IRQ_count;
	250	if ((state->IRQ_count == 0))
245	251	{
246		IRQ_count = IRQ_count_latch;
	252	state->IRQ_count = state->IRQ_count_latch;
247	253	}
248	254	else
249		IRQ_count--;
	255	state->IRQ_count--;
250	256
251		if (IRQ_enable && !blanked && (IRQ_count == 0) && priorCount)
	257	if (state->IRQ_enable && !blanked && (state->IRQ_count == 0) && priorCount)
252	258	{
253	259	LOG_MMC(("irq fired, scanline: %d (MAME %d, beam pos: %d)\n", scanline,
254	260	video_screen_get_vpos(device->machine->primary_screen), video_screen_get_hpos(device->machine->primary_screen)));
r7955	r7956
267	273	switch (offset & 0x6001)
268	274	{
269	275	case 0x0000:
270		MMC3_helper = mmc_cmd1 ^ data;
271		mmc_cmd1 = data;
	276	MMC3_helper = state->mmc_cmd1 ^ data;
	277	state->mmc_cmd1 = data;
272	278
273	279	/* Has PRG Mode changed? */
274	280	if (MMC3_helper & 0x40)
275		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	281	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
276	282
277	283	/* Has CHR Mode changed? */
278	284	if (MMC3_helper & 0x80)
279		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	285	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
280	286	break;
281	287
282	288	case 0x0001:
283		cmd = mmc_cmd1 & 0x07;
	289	cmd = state->mmc_cmd1 & 0x07;
284	290	switch (cmd)
285	291	{
286	292	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
287	293	case 2: case 3: case 4: case 5:
288		vrom_bank[cmd] = data;
289		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	294	state->vrom_bank[cmd] = data;
	295	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
290	296	break;
291	297	case 6:
292	298	case 7:
293		prg_bank[cmd - 6] = data;
294		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	299	state->prg_bank[cmd - 6] = data;
	300	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
295	301	break;
296	302	}
297	303	break;
r7955	r7956
301	307	break;
302	308
303	309	case 0x2001: /* extra RAM enable/disable */
304		mmc_cmd2 = data; /* This actually is made of two parts: data&0x80 = WRAM enabled and data&0x40 = WRAM readonly! */
305		/* We save this twice because we will need mmc_cmd2 in some clone mapper */
	310	state->mmc_cmd2 = data; /* This actually is made of two parts: data&0x80 = WRAM enabled and data&0x40 = WRAM readonly! */
	311	/* We save this twice because we will need state->mmc_cmd2 in some clone mapper */
306	312	state->mid_ram_enable = data;
307	313	break;
308	314
309	315	case 0x4000:
310		IRQ_count_latch = data;
	316	state->IRQ_count_latch = data;
311	317	break;
312	318
313		case 0x4001: /* some sources state that here we must have IRQ_count = IRQ_count_latch */
314		IRQ_count = 0;
	319	case 0x4001: /* some sources state that here we must have state->IRQ_count = state->IRQ_count_latch */
	320	state->IRQ_count = 0;
315	321	break;
316	322
317	323	case 0x6000:
318		IRQ_enable = 0;
	324	state->IRQ_enable = 0;
319	325	break;
320	326
321	327	case 0x6001:
322		IRQ_enable = 1;
	328	state->IRQ_enable = 1;
323	329	break;
324	330
325	331	default:
r7955	r7956
342	348
343	349	static void mapper5_irq( running_device *device, int scanline, int vblank, int blanked )
344	350	{
	351	nes_state state = (nes_state )device->machine->driver_data;
	352
345	353	#if 1
346	354	if (scanline == 0)
347		IRQ_status \|= 0x40;
	355	state->IRQ_status \|= 0x40;
348	356	else if (scanline > PPU_BOTTOM_VISIBLE_SCANLINE)
349		IRQ_status &= ~0x40;
	357	state->IRQ_status &= ~0x40;
350	358	#endif
351	359
352		if (scanline == IRQ_count)
	360	if (scanline == state->IRQ_count)
353	361	{
354		if (IRQ_enable)
	362	if (state->IRQ_enable)
355	363	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
356	364
357		IRQ_status = 0xff;
	365	state->IRQ_status = 0xff;
358	366	}
359	367	}
360	368
r7955	r7956
382	390
383	391	static READ8_HANDLER( mapper5_l_r )
384	392	{
	393	nes_state state = (nes_state )space->machine->driver_data;
385	394	int retVal;
386	395
387	396	/* $5c00 - $5fff: extended videoram attributes */
388	397	if ((offset >= 0x1b00) && (offset <= 0x1eff))
389	398	{
390		return nes_mmc5_vram[offset - 0x1b00];
	399	return state->mmc5_vram[offset - 0x1b00];
391	400	}
392	401
393	402	switch (offset)
r7955	r7956
399	408	else
400	409	return 0x00;
401	410	#else
402		retVal = IRQ_status;
403		IRQ_status &= ~0x80;
	411	retVal = state->IRQ_status;
	412	state->IRQ_status &= ~0x80;
404	413	return retVal;
405	414	#endif
406	415
407	416	case 0x1105: /* $5205 */
408		return (mult1 * mult2) & 0xff;
	417	return (state->mult1 * state->mult2) & 0xff;
409	418	case 0x1106: /* $5206 */
410		return ((mult1 * mult2) & 0xff00) >> 8;
	419	return ((state->mult1 * state->mult2) & 0xff00) >> 8;
411	420
412	421	default:
413	422	logerror("** MMC5 uncaught read, offset: %04x\n", offset + 0x4100);
r7955	r7956
420	429	// int i;
421	430	//
422	431	// for (i = 0; i < 8; i ++)
423		// nes_vram[i] = vrom_bank[0 + (mode * 8)] * 64;
	432	// nes_vram[i] = state->vrom_bank[0 + (mode * 8)] * 64;
424	433	//}
425	434
426	435	static WRITE8_HANDLER( mapper5_l_w )
r7955	r7956
443	452	if ((offset >= 0x1b00) && (offset <= 0x1eff))
444	453	{
445	454	if (MMC5_vram_protect == 0x03)
446		nes_mmc5_vram[offset - 0x1b00] = data;
	455	state->mmc5_vram[offset - 0x1b00] = data;
447	456	return;
448	457	}
449	458
r7955	r7956
475	484	break;
476	485
477	486	case 0x1004: /* $5104 - Extra VRAM (EXRAM) control */
478		nes_mmc5_vram_control = data;
	487	state->mmc5_vram_control = data;
479	488	LOG_MMC(("MMC5 exram control: %02x\n", data));
480	489	break;
481	490
r7955	r7956
488	497
489	498	/* tile data for MMC5 flood-fill NT mode */
490	499	case 0x1006:
491		MMC5_floodtile = data;
	500	state->MMC5_floodtile = data;
492	501	break;
493	502
494	503	/* attr data for MMC5 flood-fill NT mode */
r7955	r7956
496	505	switch (data & 3)
497	506	{
498	507	default:
499		case 0: MMC5_floodattr = 0x00; break;
500		case 1: MMC5_floodattr = 0x55; break;
501		case 2: MMC5_floodattr = 0xaa; break;
502		case 3: MMC5_floodattr = 0xff; break;
	508	case 0: state->MMC5_floodattr = 0x00; break;
	509	case 1: state->MMC5_floodattr = 0x55; break;
	510	case 2: state->MMC5_floodattr = 0xaa; break;
	511	case 3: state->MMC5_floodattr = 0xff; break;
503	512	}
504	513	break;
505	514
r7955	r7956
620	629	{
621	630	case 0x03:
622	631	/* 1k switch */
623		vrom_bank[0] = data;
	632	state->vrom_bank[0] = data;
624	633	// mapper5_sync_vrom(0);
625		chr1_0(space->machine, vrom_bank[0], CHRROM);
626		// state->nes_vram_sprite[0] = vrom_bank[0] * 64;
	634	chr1_0(space->machine, state->vrom_bank[0], CHRROM);
	635	// state->nes_vram_sprite[0] = state->vrom_bank[0] * 64;
627	636	// vrom_next[0] = 4;
628	637	// vrom_page_a = 1;
629	638	// vrom_page_b = 0;
r7955	r7956
640	649	break;
641	650	case 0x03:
642	651	/* 1k switch */
643		vrom_bank[1] = data;
	652	state->vrom_bank[1] = data;
644	653	// mapper5_sync_vrom(0);
645		chr1_1(space->machine, vrom_bank[1], CHRROM);
646		// state->nes_vram_sprite[1] = vrom_bank[0] * 64;
	654	chr1_1(space->machine, state->vrom_bank[1], CHRROM);
	655	// state->nes_vram_sprite[1] = state->vrom_bank[0] * 64;
647	656	// vrom_next[1] = 5;
648	657	// vrom_page_a = 1;
649	658	// vrom_page_b = 0;
r7955	r7956
656	665	{
657	666	case 0x03:
658	667	/* 1k switch */
659		vrom_bank[2] = data;
	668	state->vrom_bank[2] = data;
660	669	// mapper5_sync_vrom(0);
661		chr1_2(space->machine, vrom_bank[2], CHRROM);
662		// state->nes_vram_sprite[2] = vrom_bank[0] * 64;
	670	chr1_2(space->machine, state->vrom_bank[2], CHRROM);
	671	// state->nes_vram_sprite[2] = state->vrom_bank[0] * 64;
663	672	// vrom_next[2] = 6;
664	673	// vrom_page_a = 1;
665	674	// vrom_page_b = 0;
r7955	r7956
679	688	break;
680	689	case 0x03:
681	690	/* 1k switch */
682		vrom_bank[3] = data;
	691	state->vrom_bank[3] = data;
683	692	// mapper5_sync_vrom(0);
684		chr1_3(space->machine, vrom_bank[3], CHRROM);
685		// state->nes_vram_sprite[3] = vrom_bank[0] * 64;
	693	chr1_3(space->machine, state->vrom_bank[3], CHRROM);
	694	// state->nes_vram_sprite[3] = state->vrom_bank[0] * 64;
686	695	// vrom_next[3] = 7;
687	696	// vrom_page_a = 1;
688	697	// vrom_page_b = 0;
r7955	r7956
695	704	{
696	705	case 0x03:
697	706	/* 1k switch */
698		vrom_bank[4] = data;
	707	state->vrom_bank[4] = data;
699	708	// mapper5_sync_vrom(0);
700		chr1_4(space->machine, vrom_bank[4], CHRROM);
701		// state->nes_vram_sprite[4] = vrom_bank[0] * 64;
	709	chr1_4(space->machine, state->vrom_bank[4], CHRROM);
	710	// state->nes_vram_sprite[4] = state->vrom_bank[0] * 64;
702	711	// vrom_next[0] = 0;
703	712	// vrom_page_a = 0;
704	713	// vrom_page_b = 0;
r7955	r7956
715	724	break;
716	725	case 0x03:
717	726	/* 1k switch */
718		vrom_bank[5] = data;
	727	state->vrom_bank[5] = data;
719	728	// mapper5_sync_vrom(0);
720		chr1_5(space->machine, vrom_bank[5], CHRROM);
721		// state->nes_vram_sprite[5] = vrom_bank[0] * 64;
	729	chr1_5(space->machine, state->vrom_bank[5], CHRROM);
	730	// state->nes_vram_sprite[5] = state->vrom_bank[0] * 64;
722	731	// vrom_next[1] = 1;
723	732	// vrom_page_a = 0;
724	733	// vrom_page_b = 0;
r7955	r7956
731	740	{
732	741	case 0x03:
733	742	/* 1k switch */
734		vrom_bank[6] = data;
	743	state->vrom_bank[6] = data;
735	744	// mapper5_sync_vrom(0);
736		chr1_6(space->machine, vrom_bank[6], CHRROM);
737		// state->nes_vram_sprite[6] = vrom_bank[0] * 64;
	745	chr1_6(space->machine, state->vrom_bank[6], CHRROM);
	746	// state->nes_vram_sprite[6] = state->vrom_bank[0] * 64;
738	747	// vrom_next[2] = 2;
739	748	// vrom_page_a = 0;
740	749	// vrom_page_b = 0;
r7955	r7956
759	768	break;
760	769	case 0x03:
761	770	/* 1k switch */
762		vrom_bank[7] = data;
	771	state->vrom_bank[7] = data;
763	772	// mapper5_sync_vrom(0);
764		chr1_7(space->machine, vrom_bank[7], CHRROM);
765		// state->nes_vram_sprite[7] = vrom_bank[0] * 64;
	773	chr1_7(space->machine, state->vrom_bank[7], CHRROM);
	774	// state->nes_vram_sprite[7] = state->vrom_bank[0] * 64;
766	775	// vrom_next[3] = 3;
767	776	// vrom_page_a = 0;
768	777	// vrom_page_b = 0;
r7955	r7956
775	784	{
776	785	case 0x03:
777	786	/* 1k switch */
778		vrom_bank[8] = vrom_bank[12] = data;
	787	state->vrom_bank[8] = state->vrom_bank[12] = data;
779	788	// nes_vram[vrom_next[0]] = data * 64;
780	789	// nes_vram[0 + (vrom_page_a4)] = data 64;
781	790	// nes_vram[0] = data * 64;
r7955	r7956
800	809	break;
801	810	case 0x03:
802	811	/* 1k switch */
803		vrom_bank[9] = vrom_bank[13] = data;
	812	state->vrom_bank[9] = state->vrom_bank[13] = data;
804	813	// nes_vram[vrom_next[1]] = data * 64;
805	814	// nes_vram[1 + (vrom_page_a4)] = data 64;
806	815	// nes_vram[1] = data * 64;
r7955	r7956
820	829	{
821	830	case 0x03:
822	831	/* 1k switch */
823		vrom_bank[10] = vrom_bank[14] = data;
	832	state->vrom_bank[10] = state->vrom_bank[14] = data;
824	833	// nes_vram[vrom_next[2]] = data * 64;
825	834	// nes_vram[2 + (vrom_page_a4)] = data 64;
826	835	// nes_vram[2] = data * 64;
r7955	r7956
856	865	break;
857	866	case 0x03:
858	867	/* 1k switch */
859		vrom_bank[11] = vrom_bank[15] = data;
	868	state->vrom_bank[11] = state->vrom_bank[15] = data;
860	869	// nes_vram[vrom_next[3]] = data * 64;
861	870	// nes_vram[3 + (vrom_page_a4)] = data 64;
862	871	// nes_vram[3] = data * 64;
r7955	r7956
872	881	break;
873	882
874	883	case 0x1103: /* $5203 */
875		IRQ_count = data;
	884	state->IRQ_count = data;
876	885	MMC5_scanline = data;
877		LOG_MMC(("MMC5 irq scanline: %d\n", IRQ_count));
	886	LOG_MMC(("MMC5 irq scanline: %d\n", state->IRQ_count));
878	887	break;
879	888	case 0x1104: /* $5204 */
880		IRQ_enable = data & 0x80;
	889	state->IRQ_enable = data & 0x80;
881	890	LOG_MMC(("MMC5 irq enable: %02x\n", data));
882	891	break;
883	892	case 0x1105: /* $5205 */
884		mult1 = data;
	893	state->mult1 = data;
885	894	break;
886	895	case 0x1106: /* $5206 */
887		mult2 = data;
	896	state->mult2 = data;
888	897	break;
889	898
890	899	default:
r7955	r7956
915	924	there are 3 dots to every 1 CPU cycle, hence 114 is the number of cycles per scanline ) */
916	925	static void ffe_irq( running_device *device, int scanline, int vblank, int blanked )
917	926	{
	927	nes_state state = (nes_state )device->machine->driver_data;
	928
918	929	/* 114 is the number of cycles per scanline */
919	930	/* TODO: change to reflect the actual number of cycles spent */
920		if (IRQ_enable)
	931	if (state->IRQ_enable)
921	932	{
922		if ((0xffff - IRQ_count) < 114)
	933	if ((0xffff - state->IRQ_count) < 114)
923	934	{
924	935	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
925		IRQ_count = 0xffff;
926		IRQ_enable = 0;
	936	state->IRQ_count = 0xffff;
	937	state->IRQ_enable = 0;
927	938	}
928		IRQ_count -= 114;
	939	state->IRQ_count -= 114;
929	940	}
930	941	}
931	942
932	943	static WRITE8_HANDLER( mapper6_l_w )
933	944	{
	945	nes_state state = (nes_state )space->machine->driver_data;
934	946	LOG_MMC(("mapper6_l_w, offset: %04x, data: %02x\n", offset, data));
935	947
936	948	switch (offset)
937	949	{
938	950	case 0x1fe:
939		mmc_cmd1 = data & 0x80;
	951	state->mmc_cmd1 = data & 0x80;
940	952	set_nt_mirroring(space->machine, BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
941	953	break;
942	954	case 0x1ff:
r7955	r7956
944	956	break;
945	957
946	958	case 0x401:
947		IRQ_enable = data & 0x01;
	959	state->IRQ_enable = data & 0x01;
948	960	break;
949	961	case 0x402:
950		IRQ_count = (IRQ_count & 0xff00) \| data;
	962	state->IRQ_count = (state->IRQ_count & 0xff00) \| data;
951	963	break;
952	964	case 0x403:
953		IRQ_enable = 1;
954		IRQ_count = (IRQ_count & 0x00ff) \| (data << 8);
	965	state->IRQ_enable = 1;
	966	state->IRQ_count = (state->IRQ_count & 0x00ff) \| (data << 8);
955	967	break;
956	968	}
957	969	}
958	970
959	971	static WRITE8_HANDLER( mapper6_w )
960	972	{
	973	nes_state state = (nes_state )space->machine->driver_data;
961	974	LOG_MMC(("mapper6_w, offset: %04x, data: %02x\n", offset, data));
962	975
963		if (!mmc_cmd1) // when in "FFE mode" we are forced to use CHRRAM/EXRAM bank?
	976	if (!state->mmc_cmd1) // when in "FFE mode" we are forced to use CHRRAM/EXRAM bank?
964	977	{
965	978	prg16_89ab(space->machine, data >> 2);
966	979	// chr8(space->machine, data & 0x03, ???);
967	980	// due to lack of info on the exact behavior, we simply act as if mmc_cmd=1
968		if (mmc_chr_source == CHRROM)
	981	if (state->mmc_chr_source == CHRROM)
969	982	chr8(space->machine, data & 0x03, CHRROM);
970	983	}
971		else if (mmc_chr_source == CHRROM) // otherwise, we can use CHRROM (when present)
	984	else if (state->mmc_chr_source == CHRROM) // otherwise, we can use CHRROM (when present)
972	985	chr8(space->machine, data, CHRROM);
973	986	}
974	987
r7955	r7956
1024	1037
1025	1038	static void mapper9_latch (running_device *device, offs_t offset)
1026	1039	{
	1040	nes_state state = (nes_state )device->machine->driver_data;
1027	1041	if ((offset & 0x3ff0) == 0x0fd0)
1028	1042	{
1029	1043	LOG_MMC(("mapper9 vrom latch switch (bank 0 low): %02x\n", MMC2_regs[0]));
1030		mmc_cmd1 = 0xfd;
	1044	state->mmc_cmd1 = 0xfd;
1031	1045	chr4_0(device->machine, MMC2_regs[0], CHRROM);
1032	1046	}
1033	1047	else if ((offset & 0x3ff0) == 0x0fe0)
1034	1048	{
1035	1049	LOG_MMC(("mapper9 vrom latch switch (bank 0 high): %02x\n", MMC2_regs[1]));
1036		mmc_cmd1 = 0xfe;
	1050	state->mmc_cmd1 = 0xfe;
1037	1051	chr4_0(device->machine, MMC2_regs[1], CHRROM);
1038	1052	}
1039	1053	else if ((offset & 0x3ff0) == 0x1fd0)
1040	1054	{
1041	1055	LOG_MMC(("mapper9 vrom latch switch (bank 1 low): %02x\n", MMC2_regs[2]));
1042		mmc_cmd2 = 0xfd;
	1056	state->mmc_cmd2 = 0xfd;
1043	1057	chr4_4(device->machine, MMC2_regs[2], CHRROM);
1044	1058	}
1045	1059	else if ((offset & 0x3ff0) == 0x1fe0)
1046	1060	{
1047	1061	LOG_MMC(("mapper9 vrom latch switch (bank 0 high): %02x\n", MMC2_regs[3]));
1048		mmc_cmd2 = 0xfe;
	1062	state->mmc_cmd2 = 0xfe;
1049	1063	chr4_4(device->machine, MMC2_regs[3], CHRROM);
1050	1064	}
1051	1065	}
1052	1066
1053	1067	static WRITE8_HANDLER( mapper9_w )
1054	1068	{
	1069	nes_state state = (nes_state )space->machine->driver_data;
1055	1070	LOG_MMC(("mapper9_w, offset: %04x, data: %02x\n", offset, data));
1056	1071	switch (offset & 0x7000)
1057	1072	{
r7955	r7956
1060	1075	break;
1061	1076	case 0x3000:
1062	1077	MMC2_regs[0] = data;
1063		if (mmc_cmd1 == 0xfd)
	1078	if (state->mmc_cmd1 == 0xfd)
1064	1079	chr4_0(space->machine, MMC2_regs[0], CHRROM);
1065	1080	break;
1066	1081	case 0x4000:
1067	1082	MMC2_regs[1] = data;
1068		if (mmc_cmd1 == 0xfe)
	1083	if (state->mmc_cmd1 == 0xfe)
1069	1084	chr4_0(space->machine, MMC2_regs[1], CHRROM);
1070	1085	break;
1071	1086	case 0x5000:
1072	1087	MMC2_regs[2] = data;
1073		if (mmc_cmd2 == 0xfd)
	1088	if (state->mmc_cmd2 == 0xfd)
1074	1089	chr4_4(space->machine, MMC2_regs[2], CHRROM);
1075	1090	break;
1076	1091	case 0x6000:
1077	1092	MMC2_regs[3] = data;
1078		if (mmc_cmd2 == 0xfe)
	1093	if (state->mmc_cmd2 == 0xfe)
1079	1094	chr4_4(space->machine, MMC2_regs[3], CHRROM);
1080	1095	break;
1081	1096	case 0x7000:
r7955	r7956
1126	1141
1127	1142	static WRITE8_HANDLER( mapper11_w )
1128	1143	{
	1144	nes_state state = (nes_state )space->machine->driver_data;
1129	1145	LOG_MMC(("mapper11_w, offset: %04x, data: %02x\n", offset, data));
1130	1146
1131		chr8(space->machine, data >> 4, mmc_chr_source);
	1147	chr8(space->machine, data >> 4, state->mmc_chr_source);
1132	1148	prg32(space->machine, data & 0x0f);
1133	1149	}
1134	1150
r7955	r7956
1161	1177
1162	1178	static void mapper12_set_chr( running_machine *machine )
1163	1179	{
1164		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	1180	nes_state state = (nes_state )machine->driver_data;
	1181	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
1165	1182
1166		chr1_x(machine, chr_page ^ 0, ((mapper12_reg & 0x01) << 8) \| (vrom_bank[0] & ~0x01), CHRROM);
1167		chr1_x(machine, chr_page ^ 1, ((mapper12_reg & 0x01) << 8) \| (vrom_bank[0] \| 0x01), CHRROM);
1168		chr1_x(machine, chr_page ^ 2, ((mapper12_reg & 0x01) << 8) \| (vrom_bank[1] & ~0x01), CHRROM);
1169		chr1_x(machine, chr_page ^ 3, ((mapper12_reg & 0x01) << 8) \| (vrom_bank[1] \| 0x01), CHRROM);
1170		chr1_x(machine, chr_page ^ 4, ((mapper12_reg & 0x10) << 4) \| vrom_bank[2], CHRROM);
1171		chr1_x(machine, chr_page ^ 5, ((mapper12_reg & 0x10) << 4) \| vrom_bank[3], CHRROM);
1172		chr1_x(machine, chr_page ^ 6, ((mapper12_reg & 0x10) << 4) \| vrom_bank[4], CHRROM);
1173		chr1_x(machine, chr_page ^ 7, ((mapper12_reg & 0x10) << 4) \| vrom_bank[5], CHRROM);
	1183	chr1_x(machine, chr_page ^ 0, ((mapper12_reg & 0x01) << 8) \| (state->vrom_bank[0] & ~0x01), CHRROM);
	1184	chr1_x(machine, chr_page ^ 1, ((mapper12_reg & 0x01) << 8) \| (state->vrom_bank[0] \| 0x01), CHRROM);
	1185	chr1_x(machine, chr_page ^ 2, ((mapper12_reg & 0x01) << 8) \| (state->vrom_bank[1] & ~0x01), CHRROM);
	1186	chr1_x(machine, chr_page ^ 3, ((mapper12_reg & 0x01) << 8) \| (state->vrom_bank[1] \| 0x01), CHRROM);
	1187	chr1_x(machine, chr_page ^ 4, ((mapper12_reg & 0x10) << 4) \| state->vrom_bank[2], CHRROM);
	1188	chr1_x(machine, chr_page ^ 5, ((mapper12_reg & 0x10) << 4) \| state->vrom_bank[3], CHRROM);
	1189	chr1_x(machine, chr_page ^ 6, ((mapper12_reg & 0x10) << 4) \| state->vrom_bank[4], CHRROM);
	1190	chr1_x(machine, chr_page ^ 7, ((mapper12_reg & 0x10) << 4) \| state->vrom_bank[5], CHRROM);
1174	1191	}
1175	1192
1176	1193	static WRITE8_HANDLER( mapper12_w )
1177	1194	{
	1195	nes_state state = (nes_state )space->machine->driver_data;
1178	1196	UINT8 MMC3_helper, cmd;
1179	1197	LOG_MMC(("mapper12_w, offset: %04x, data: %02x\n", offset, data));
1180	1198
1181	1199	switch (offset & 0x6001)
1182	1200	{
1183	1201	case 0x0000:
1184		MMC3_helper = mmc_cmd1 ^ data;
1185		mmc_cmd1 = data;
	1202	MMC3_helper = state->mmc_cmd1 ^ data;
	1203	state->mmc_cmd1 = data;
1186	1204
1187	1205	/* Has PRG Mode changed? */
1188	1206	if (MMC3_helper & 0x40)
1189		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	1207	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
1190	1208
1191	1209	/* Has CHR Mode changed? */
1192	1210	if (MMC3_helper & 0x80)
r7955	r7956
1194	1212	break;
1195	1213
1196	1214	case 0x0001:
1197		cmd = mmc_cmd1 & 0x07;
	1215	cmd = state->mmc_cmd1 & 0x07;
1198	1216	switch (cmd)
1199	1217	{
1200	1218	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
1201	1219	case 2: case 3: case 4: case 5:
1202		vrom_bank[cmd] = data;
	1220	state->vrom_bank[cmd] = data;
1203	1221	mapper12_set_chr(space->machine);
1204	1222	break;
1205	1223	case 6:
1206	1224	case 7:
1207		prg_bank[cmd - 6] = data;
1208		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	1225	state->prg_bank[cmd - 6] = data;
	1226	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
1209	1227	break;
1210	1228	}
1211	1229	break;
r7955	r7956
1248	1266
1249	1267	static void mapper14_set_prg( running_machine *machine, int prg_base, int prg_mask )
1250	1268	{
	1269	nes_state state = (nes_state )machine->driver_data;
	1270
1251	1271	if (map14_reg[0] & 0x02)
1252	1272	{
1253	1273	mapper4_set_prg(machine, prg_base, prg_mask);
1254	1274	}
1255	1275	else
1256	1276	{
1257		prg8_89(machine, extra_bank[0]);
1258		prg8_ab(machine, extra_bank[1]);
1259		prg8_cd(machine, extra_bank[2]);
1260		prg8_ef(machine, extra_bank[3]);
	1277	prg8_89(machine, state->extra_bank[0]);
	1278	prg8_ab(machine, state->extra_bank[1]);
	1279	prg8_cd(machine, state->extra_bank[2]);
	1280	prg8_ef(machine, state->extra_bank[3]);
1261	1281	}
1262	1282	}
1263	1283
1264	1284	static void mapper14_set_chr( running_machine *machine, UINT8 chr, int chr_base, int chr_mask )
1265	1285	{
	1286	nes_state state = (nes_state )machine->driver_data;
1266	1287	static const UINT8 conv_table[8] = {5, 5, 5, 5, 3, 3, 1, 1};
1267		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	1288	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
1268	1289	UINT8 bank[8];
1269	1290	UINT8 chr_base2[8];
1270	1291	int i;
r7955	r7956
1273	1294	{
1274	1295	for(i = 0; i < 8; i++)
1275	1296	{
1276		bank[i] = vrom_bank[i];
	1297	bank[i] = state->vrom_bank[i];
1277	1298	chr_base2[i] = chr_base \| ((map14_reg[0] << conv_table[i]) & 0x100);
1278	1299	}
1279	1300	}
r7955	r7956
1281	1302	{
1282	1303	for(i = 0; i < 8; i++)
1283	1304	{
1284		bank[i] = extra_bank[i + 4]; // first 4 extra_banks are PRG
	1305	bank[i] = state->extra_bank[i + 4]; // first 4 state->extra_banks are PRG
1285	1306	chr_base2[i] = chr_base;
1286	1307	}
1287	1308	}
r7955	r7956
1298	1319
1299	1320	static WRITE8_HANDLER( mapper14_w )
1300	1321	{
	1322	nes_state state = (nes_state )space->machine->driver_data;
1301	1323	UINT8 map14_helper1, map14_helper2, MMC3_helper, cmd;
1302	1324	LOG_MMC(("mapper14_w, offset: %04x, data: %02x\n", offset, data));
1303	1325
1304	1326	if (offset == 0x2131)
1305	1327	{
1306	1328	map14_reg[0] = data;
1307		mapper14_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
1308		mapper14_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1329	mapper14_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
	1330	mapper14_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1309	1331
1310	1332	if (!(map14_reg[0] & 0x02))
1311	1333	set_nt_mirroring(space->machine, BIT(map14_reg[1], 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
r7955	r7956
1316	1338	switch (offset & 0x6001)
1317	1339	{
1318	1340	case 0x0000:
1319		MMC3_helper = mmc_cmd1 ^ data;
1320		mmc_cmd1 = data;
	1341	MMC3_helper = state->mmc_cmd1 ^ data;
	1342	state->mmc_cmd1 = data;
1321	1343
1322	1344	/* Has PRG Mode changed? */
1323	1345	if (MMC3_helper & 0x40)
1324		mapper14_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	1346	mapper14_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
1325	1347
1326	1348	/* Has CHR Mode changed? */
1327	1349	if (MMC3_helper & 0x80)
1328		mapper14_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1350	mapper14_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1329	1351	break;
1330	1352
1331	1353	case 0x0001:
1332		cmd = mmc_cmd1 & 0x07;
	1354	cmd = state->mmc_cmd1 & 0x07;
1333	1355	switch (cmd)
1334	1356	{
1335	1357	case 0: case 1: // these have to be changed due to the different way mapper14_set_chr works (it handles 1k banks)!
1336		vrom_bank[2 * cmd] = data;
1337		vrom_bank[2 * cmd + 1] = data;
1338		mapper14_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1358	state->vrom_bank[2 * cmd] = data;
	1359	state->vrom_bank[2 * cmd + 1] = data;
	1360	mapper14_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1339	1361	break;
1340	1362	case 2: case 3: case 4: case 5:
1341		vrom_bank[cmd + 2] = data;
1342		mapper14_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1363	state->vrom_bank[cmd + 2] = data;
	1364	mapper14_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1343	1365	break;
1344	1366	case 6:
1345	1367	case 7:
1346		prg_bank[cmd - 6] = data;
1347		mapper14_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	1368	state->prg_bank[cmd - 6] = data;
	1369	mapper14_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
1348	1370	break;
1349	1371	}
1350	1372	break;
r7955	r7956
1362	1384	{
1363	1385	map14_helper1 = (offset & 0x01) << 2;
1364	1386	offset = ((offset & 0x02) \| (offset >> 10)) >> 1;
1365		map14_helper2 = ((offset + 2) & 0x07) + 4; // '+4' because first 4 extra_banks are for PRG!
1366		extra_bank[map14_helper2] = (extra_bank[map14_helper2] & (0xf0 >> map14_helper1)) \| ((data & 0x0f) << map14_helper1);
1367		mapper14_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	1387	map14_helper2 = ((offset + 2) & 0x07) + 4; // '+4' because first 4 state->extra_banks are for PRG!
	1388	state->extra_bank[map14_helper2] = (state->extra_bank[map14_helper2] & (0xf0 >> map14_helper1)) \| ((data & 0x0f) << map14_helper1);
	1389	mapper14_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
1368	1390	}
1369	1391	else
1370	1392	{
r7955	r7956
1372	1394	{
1373	1395	case 0x0000:
1374	1396	case 0x2000:
1375		extra_bank[offset >> 13] = data;
1376		mapper14_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	1397	state->extra_bank[offset >> 13] = data;
	1398	mapper14_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
1377	1399	break;
1378	1400
1379	1401	case 0x1000:
r7955	r7956
1456	1478	there are 3 dots to every 1 CPU cycle, hence 114 is the number of cycles per scanline ) */
1457	1479	static void bandai_irq( running_device *device, int scanline, int vblank, int blanked )
1458	1480	{
	1481	nes_state state = (nes_state )device->machine->driver_data;
	1482
1459	1483	/* 114 is the number of cycles per scanline */
1460	1484	/* TODO: change to reflect the actual number of cycles spent */
1461		if (IRQ_enable)
	1485	if (state->IRQ_enable)
1462	1486	{
1463		if (IRQ_count <= 114)
	1487	if (state->IRQ_count <= 114)
1464	1488	{
1465	1489	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1466		IRQ_count = (0xffff - 114 + IRQ_count); // wrap around the 16 bits counter
	1490	state->IRQ_count = (0xffff - 114 + state->IRQ_count); // wrap around the 16 bits counter
1467	1491	}
1468		IRQ_count -= 114;
	1492	state->IRQ_count -= 114;
1469	1493	}
1470	1494	}
1471	1495
1472	1496	static WRITE8_HANDLER( mapper16_m_w )
1473	1497	{
	1498	nes_state state = (nes_state )space->machine->driver_data;
1474	1499	LOG_MMC(("mapper16_m_w, offset: %04x, data: %02x\n", offset, data));
1475	1500
1476	1501	switch (offset & 0x000f)
r7955	r7956
1479	1504	case 2: case 3:
1480	1505	case 4: case 5:
1481	1506	case 6: case 7:
1482		chr1_x(space->machine, offset & 0x07, data, mmc_chr_source);
	1507	chr1_x(space->machine, offset & 0x07, data, state->mmc_chr_source);
1483	1508	break;
1484	1509	case 8:
1485	1510	prg16_89ab(space->machine, data);
r7955	r7956
1494	1519	}
1495	1520	break;
1496	1521	case 0x0a:
1497		IRQ_enable = data & 0x01;
	1522	state->IRQ_enable = data & 0x01;
1498	1523	break;
1499	1524	case 0x0b:
1500		IRQ_count = (IRQ_count & 0xff00) \| data;
	1525	state->IRQ_count = (state->IRQ_count & 0xff00) \| data;
1501	1526	break;
1502	1527	case 0x0c:
1503		IRQ_count = (IRQ_count & 0x00ff) \| (data << 8);
	1528	state->IRQ_count = (state->IRQ_count & 0x00ff) \| (data << 8);
1504	1529	break;
1505	1530	default:
1506	1531	logerror("** uncaught mapper 16 write, offset: %04x, data: %02x\n", offset, data);
r7955	r7956
1529	1554
1530	1555	static WRITE8_HANDLER( mapper17_l_w )
1531	1556	{
	1557	nes_state state = (nes_state )space->machine->driver_data;
1532	1558	LOG_MMC(("mapper17_l_w, offset: %04x, data: %02x\n", offset, data));
1533	1559
1534	1560	switch (offset)
r7955	r7956
1541	1567	break;
1542	1568
1543	1569	case 0x401:
1544		IRQ_enable = data & 0x01;
	1570	state->IRQ_enable = data & 0x01;
1545	1571	break;
1546	1572	case 0x402:
1547		IRQ_count = (IRQ_count & 0xff00) \| data;
	1573	state->IRQ_count = (state->IRQ_count & 0xff00) \| data;
1548	1574	break;
1549	1575	case 0x403:
1550		IRQ_enable = 1;
1551		IRQ_count = (IRQ_count & 0x00ff) \| (data << 8);
	1576	state->IRQ_enable = 1;
	1577	state->IRQ_count = (state->IRQ_count & 0x00ff) \| (data << 8);
1552	1578	break;
1553	1579
1554	1580	case 0x404:
r7955	r7956
1594	1620	there are 3 dots to every 1 CPU cycle, hence 114 is the number of cycles per scanline ) */
1595	1621	static void jaleco_irq( running_device *device, int scanline, int vblank, int blanked )
1596	1622	{
	1623	nes_state state = (nes_state )device->machine->driver_data;
	1624
1597	1625	/* Increment & check the IRQ scanline counter */
1598		if (IRQ_enable)
	1626	if (state->IRQ_enable)
1599	1627	{
1600		LOG_MMC(("scanline: %d, irq count: %04x\n", scanline, IRQ_count));
1601		if (IRQ_mode & 0x08)
	1628	LOG_MMC(("scanline: %d, irq count: %04x\n", scanline, state->IRQ_count));
	1629	if (state->IRQ_mode & 0x08)
1602	1630	{
1603		if ((IRQ_count & 0x000f) < 114) // always true, but we only update the IRQ once per scanlines so we cannot be more precise :(
	1631	if ((state->IRQ_count & 0x000f) < 114) // always true, but we only update the IRQ once per scanlines so we cannot be more precise :(
1604	1632	{
1605	1633	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1606		IRQ_count = (IRQ_count & ~0x000f) \| (0x0f - (114 & 0x0f) + (IRQ_count & 0x000f)); // sort of wrap around the counter
	1634	state->IRQ_count = (state->IRQ_count & ~0x000f) \| (0x0f - (114 & 0x0f) + (state->IRQ_count & 0x000f)); // sort of wrap around the counter
1607	1635	}
1608	1636	// decrements should not affect upper bits, so we don't do anything here (114 > 0x0f)
1609	1637	}
1610		else if (IRQ_mode & 0x04)
	1638	else if (state->IRQ_mode & 0x04)
1611	1639	{
1612		if ((IRQ_count & 0x00ff) < 114)
	1640	if ((state->IRQ_count & 0x00ff) < 114)
1613	1641	{
1614	1642	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1615		IRQ_count = (IRQ_count & ~0x00ff) \| (0xff - 114 + (IRQ_count & 0x00ff)); // wrap around the 8 bits counter
	1643	state->IRQ_count = (state->IRQ_count & ~0x00ff) \| (0xff - 114 + (state->IRQ_count & 0x00ff)); // wrap around the 8 bits counter
1616	1644	}
1617	1645	else
1618		IRQ_count -= 114;
	1646	state->IRQ_count -= 114;
1619	1647	}
1620		else if (IRQ_mode & 0x02)
	1648	else if (state->IRQ_mode & 0x02)
1621	1649	{
1622		if ((IRQ_count & 0x0fff) < 114)
	1650	if ((state->IRQ_count & 0x0fff) < 114)
1623	1651	{
1624	1652	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1625		IRQ_count = (IRQ_count & ~0x0fff) \| (0xfff - 114 + (IRQ_count & 0x0fff)); // wrap around the 12 bits counter
	1653	state->IRQ_count = (state->IRQ_count & ~0x0fff) \| (0xfff - 114 + (state->IRQ_count & 0x0fff)); // wrap around the 12 bits counter
1626	1654	}
1627	1655	else
1628		IRQ_count -= 114;
	1656	state->IRQ_count -= 114;
1629	1657	}
1630		else if (IRQ_count < 114)
	1658	else if (state->IRQ_count < 114)
1631	1659	{
1632	1660	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1633		IRQ_count = (0xffff - 114 + IRQ_count); // wrap around the 16 bits counter
	1661	state->IRQ_count = (0xffff - 114 + state->IRQ_count); // wrap around the 16 bits counter
1634	1662	}
1635	1663	else
1636		IRQ_count -= 114;
	1664	state->IRQ_count -= 114;
1637	1665	}
1638	1666	}
1639	1667
1640	1668	static WRITE8_HANDLER( mapper18_w )
1641	1669	{
	1670	nes_state state = (nes_state )space->machine->driver_data;
1642	1671	UINT8 bank;
1643	1672	LOG_MMC(("mapper18_w, offset: %04x, data: %02x\n", offset, data));
1644	1673
1645	1674	switch (offset & 0x7003)
1646	1675	{
1647	1676	case 0x0000:
1648		prg_bank[0] = (prg_bank[0] & 0xf0) \| (data & 0x0f);
1649		prg8_89(space->machine, prg_bank[0]);
	1677	state->prg_bank[0] = (state->prg_bank[0] & 0xf0) \| (data & 0x0f);
	1678	prg8_89(space->machine, state->prg_bank[0]);
1650	1679	break;
1651	1680	case 0x0001:
1652		prg_bank[0] = (prg_bank[0] & 0x0f) \| (data << 4);
1653		prg8_89(space->machine, prg_bank[0]);
	1681	state->prg_bank[0] = (state->prg_bank[0] & 0x0f) \| (data << 4);
	1682	prg8_89(space->machine, state->prg_bank[0]);
1654	1683	break;
1655	1684	case 0x0002:
1656		prg_bank[1] = (prg_bank[1] & 0xf0) \| (data & 0x0f);
1657		prg8_ab(space->machine, prg_bank[1]);
	1685	state->prg_bank[1] = (state->prg_bank[1] & 0xf0) \| (data & 0x0f);
	1686	prg8_ab(space->machine, state->prg_bank[1]);
1658	1687	break;
1659	1688	case 0x0003:
1660		prg_bank[1] = (prg_bank[1] & 0x0f) \| (data << 4);
1661		prg8_ab(space->machine, prg_bank[1]);
	1689	state->prg_bank[1] = (state->prg_bank[1] & 0x0f) \| (data << 4);
	1690	prg8_ab(space->machine, state->prg_bank[1]);
1662	1691	break;
1663	1692	case 0x1000:
1664		prg_bank[2] = (prg_bank[2] & 0xf0) \| (data & 0x0f);
1665		prg8_cd(space->machine, prg_bank[2]);
	1693	state->prg_bank[2] = (state->prg_bank[2] & 0xf0) \| (data & 0x0f);
	1694	prg8_cd(space->machine, state->prg_bank[2]);
1666	1695	break;
1667	1696	case 0x1001:
1668		prg_bank[2] = (prg_bank[2] & 0x0f) \| (data << 4);
1669		prg8_cd(space->machine, prg_bank[2]);
	1697	state->prg_bank[2] = (state->prg_bank[2] & 0x0f) \| (data << 4);
	1698	prg8_cd(space->machine, state->prg_bank[2]);
1670	1699	break;
1671	1700
1672	1701	/* $9002, 3 (1002, 3) uncaught = Jaleco Baseball writes 0 */
r7955	r7956
1678	1707	case 0x5000: case 0x5001: case 0x5002: case 0x5003:
1679	1708	bank = ((offset & 0x7000) - 0x2000) / 0x0800 + ((offset & 0x0002) >> 1);
1680	1709	if (offset & 0x0001)
1681		vrom_bank[bank] = (vrom_bank[bank] & 0x0f) \| ((data & 0x0f)<< 4);
	1710	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0x0f) \| ((data & 0x0f)<< 4);
1682	1711	else
1683		vrom_bank[bank] = (vrom_bank[bank] & 0xf0) \| (data & 0x0f);
	1712	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0xf0) \| (data & 0x0f);
1684	1713
1685		chr1_x(space->machine, bank, vrom_bank[bank], CHRROM);
	1714	chr1_x(space->machine, bank, state->vrom_bank[bank], CHRROM);
1686	1715	break;
1687	1716
1688	1717	case 0x6000:
1689		IRQ_count_latch = (IRQ_count_latch & 0xfff0) \| (data & 0x0f);
	1718	state->IRQ_count_latch = (state->IRQ_count_latch & 0xfff0) \| (data & 0x0f);
1690	1719	break;
1691	1720	case 0x6001:
1692		IRQ_count_latch = (IRQ_count_latch & 0xff0f) \| ((data & 0x0f) << 4);
	1721	state->IRQ_count_latch = (state->IRQ_count_latch & 0xff0f) \| ((data & 0x0f) << 4);
1693	1722	break;
1694	1723	case 0x6002:
1695		IRQ_count_latch = (IRQ_count_latch & 0xf0ff) \| ((data & 0x0f) << 8);
	1724	state->IRQ_count_latch = (state->IRQ_count_latch & 0xf0ff) \| ((data & 0x0f) << 8);
1696	1725	break;
1697	1726	case 0x6003:
1698		IRQ_count_latch = (IRQ_count_latch & 0x0fff) \| ((data & 0x0f) << 12);
	1727	state->IRQ_count_latch = (state->IRQ_count_latch & 0x0fff) \| ((data & 0x0f) << 12);
1699	1728	break;
1700	1729
1701	1730	case 0x7000:
1702		IRQ_count = IRQ_count_latch;
	1731	state->IRQ_count = state->IRQ_count_latch;
1703	1732	break;
1704	1733	case 0x7001:
1705		IRQ_enable = data & 0x01;
1706		IRQ_mode = data & 0x0e;
	1734	state->IRQ_enable = data & 0x01;
	1735	state->IRQ_mode = data & 0x0e;
1707	1736	break;
1708	1737
1709	1738	case 0x7002:
r7955	r7956
1739	1768	there are 3 dots to every 1 CPU cycle, hence 114 is the number of cycles per scanline ) */
1740	1769	static void namcot_irq( running_device *device, int scanline, int vblank, int blanked )
1741	1770	{
1742		if (IRQ_enable)
	1771	nes_state state = (nes_state )device->machine->driver_data;
	1772
	1773	if (state->IRQ_enable)
1743	1774	{
1744		if (IRQ_count >= (0x7fff - 114))
	1775	if (state->IRQ_count >= (0x7fff - 114))
1745	1776	{
1746	1777	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1747		IRQ_count = 0;
	1778	state->IRQ_count = 0;
1748	1779	}
1749	1780	else
1750		IRQ_count += 114;
	1781	state->IRQ_count += 114;
1751	1782	}
1752	1783	}
1753	1784
1754	1785	static WRITE8_HANDLER( mapper19_l_w )
1755	1786	{
	1787	nes_state state = (nes_state )space->machine->driver_data;
1756	1788	LOG_MMC(("mapper19_l_w, offset: %04x, data: %02x\n", offset, data));
1757	1789	offset += 0x100;
1758	1790
r7955	r7956
1762	1794	LOG_MMC(("Mapper 19 sound port write, data: %02x\n", data));
1763	1795	break;
1764	1796	case 0x1000: /* low byte of IRQ */
1765		IRQ_count = (IRQ_count & 0x7f00) \| data;
	1797	state->IRQ_count = (state->IRQ_count & 0x7f00) \| data;
1766	1798	break;
1767	1799	case 0x1800: /* high byte of IRQ, IRQ enable in high bit */
1768		IRQ_count = (IRQ_count & 0xff) \| ((data & 0x7f) << 8);
1769		IRQ_enable = data & 0x80;
	1800	state->IRQ_count = (state->IRQ_count & 0xff) \| ((data & 0x7f) << 8);
	1801	state->IRQ_enable = data & 0x80;
1770	1802	break;
1771	1803	}
1772	1804	}
1773	1805
1774	1806	static READ8_HANDLER( mapper19_l_r )
1775	1807	{
	1808	nes_state state = (nes_state )space->machine->driver_data;
1776	1809	LOG_MMC(("mapper19_l_r, offset: %04x\n", offset));
1777	1810	offset += 0x100;
1778	1811
1779	1812	switch (offset & 0x1800)
1780	1813	{
1781	1814	case 0x1000:
1782		return IRQ_count & 0xff;
	1815	return state->IRQ_count & 0xff;
1783	1816	case 0x1800:
1784		return (IRQ_count >> 8) & 0xff;
	1817	return (state->IRQ_count >> 8) & 0xff;
1785	1818	default:
1786	1819	return 0x00;
1787	1820	}
r7955	r7956
1797	1830
1798	1831	static WRITE8_HANDLER( mapper19_w )
1799	1832	{
	1833	nes_state state = (nes_state )space->machine->driver_data;
1800	1834	LOG_MMC(("mapper19_w, offset: %04x, data: %02x\n", offset, data));
1801	1835	switch (offset & 0x7800)
1802	1836	{
r7955	r7956
1822	1856	prg8_89(space->machine, data & 0x3f);
1823	1857	break;
1824	1858	case 0x6800:
1825		mmc_cmd1 = data & 0xc0; // this should enable High CHRRAM, but we still have to properly implement it!
	1859	state->mmc_cmd1 = data & 0xc0; // this should enable High CHRRAM, but we still have to properly implement it!
1826	1860	prg8_ab(space->machine, data & 0x3f);
1827	1861	break;
1828	1862	case 0x7000:
r7955	r7956
1849	1883	{
1850	1884	nes_state state = (nes_state )device->machine->driver_data;
1851	1885
1852		if (IRQ_enable_latch)
	1886	if (state->IRQ_enable_latch)
1853	1887	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1854	1888
1855		if (IRQ_enable)
	1889	if (state->IRQ_enable)
1856	1890	{
1857		if (IRQ_count <= 114)
	1891	if (state->IRQ_count <= 114)
1858	1892	{
1859	1893	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1860		IRQ_enable = 0;
	1894	state->IRQ_enable = 0;
1861	1895	state->fds_status0 \|= 0x01;
1862	1896	}
1863	1897	else
1864		IRQ_count -= 114;
	1898	state->IRQ_count -= 114;
1865	1899	}
1866	1900	}
1867	1901
r7955	r7956
1891	1925	/* return "no disk" status if disk is unloaded */
1892	1926	if (state->fds_data == NULL)
1893	1927	ret = 1;
1894		else if (fds_last_side != state->fds_current_side)
	1928	else if (state->fds_last_side != state->fds_current_side)
1895	1929	{
1896	1930	/* If we've switched disks, report "no disk" for a few reads */
1897	1931	ret = 1;
1898		fds_count ++;
1899		if (fds_count == 50)
	1932	state->fds_count ++;
	1933	if (state->fds_count == 50)
1900	1934	{
1901		fds_last_side = state->fds_current_side;
1902		fds_count = 0;
	1935	state->fds_last_side = state->fds_current_side;
	1936	state->fds_count = 0;
1903	1937	}
1904	1938	}
1905	1939	else
r7955	r7956
1926	1960	switch (offset)
1927	1961	{
1928	1962	case 0x00:
1929		IRQ_count_latch = (IRQ_count_latch & 0xff00) \| data;
	1963	state->IRQ_count_latch = (state->IRQ_count_latch & 0xff00) \| data;
1930	1964	break;
1931	1965	case 0x01:
1932		IRQ_count_latch = (IRQ_count_latch & 0x00ff) \| (data << 8);
	1966	state->IRQ_count_latch = (state->IRQ_count_latch & 0x00ff) \| (data << 8);
1933	1967	break;
1934	1968	case 0x02:
1935		IRQ_count = IRQ_count_latch;
1936		IRQ_enable = data;
	1969	state->IRQ_count = state->IRQ_count_latch;
	1970	state->IRQ_enable = data;
1937	1971	break;
1938	1972	case 0x03:
1939	1973	// d0 = sound io (1 = enable)
r7955	r7956
1954	1988	if ((!(data & 0x40)) && (state->fds_write_reg & 0x40))
1955	1989	state->fds_head_position -= 2; // ???
1956	1990
1957		IRQ_enable_latch = BIT(data, 7);
	1991	state->IRQ_enable_latch = BIT(data, 7);
1958	1992	state->fds_write_reg = data;
1959	1993	break;
1960	1994	}
r7955	r7956
1976	2010
1977	2011	static void vrc4_set_prg( running_machine *machine )
1978	2012	{
1979		if (mmc_cmd1 & 0x02)
	2013	nes_state state = (nes_state )machine->driver_data;
	2014	if (state->mmc_cmd1 & 0x02)
1980	2015	{
1981	2016	prg8_89(machine, 0xfe);
1982		prg8_cd(machine, prg_bank[0]);
	2017	prg8_cd(machine, state->prg_bank[0]);
1983	2018	}
1984	2019	else
1985	2020	{
1986		prg8_89(machine, prg_bank[0]);
	2021	prg8_89(machine, state->prg_bank[0]);
1987	2022	prg8_cd(machine, 0xfe);
1988	2023	}
1989	2024	}
1990	2025
1991	2026	static void konami_irq( running_device *device, int scanline, int vblank, int blanked )
1992	2027	{
	2028	nes_state state = (nes_state )device->machine->driver_data;
1993	2029	/* Increment & check the IRQ scanline counter */
1994		if (IRQ_enable && (++IRQ_count == 0x100))
	2030	if (state->IRQ_enable && (++state->IRQ_count == 0x100))
1995	2031	{
1996		IRQ_count = IRQ_count_latch;
1997		IRQ_enable = IRQ_enable_latch;
	2032	state->IRQ_count = state->IRQ_count_latch;
	2033	state->IRQ_enable = state->IRQ_enable_latch;
1998	2034	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1999	2035	}
2000	2036	}
2001	2037
2002	2038	static WRITE8_HANDLER( konami_vrc4a_w )
2003	2039	{
	2040	nes_state state = (nes_state )space->machine->driver_data;
2004	2041	LOG_MMC(("konami_vrc4a_w, offset: %04x, data: %02x\n", offset, data));
2005	2042
2006	2043	switch (offset & 0x7fff)
r7955	r7956
2012	2049	case 0x0040:
2013	2050	case 0x0080:
2014	2051	case 0x00c0:
2015		prg_bank[0] = data;
	2052	state->prg_bank[0] = data;
2016	2053	vrc4_set_prg(space->machine);
2017	2054	break;
2018	2055
r7955	r7956
2032	2069	case 0x1006:
2033	2070	case 0x1080:
2034	2071	case 0x10c0:
2035		mmc_cmd1 = data & 0x02;
	2072	state->mmc_cmd1 = data & 0x02;
2036	2073	vrc4_set_prg(space->machine);
2037	2074	break;
2038	2075
r7955	r7956
2047	2084	break;
2048	2085
2049	2086	case 0x3000:
2050		vrom_bank[0] = (vrom_bank[0] & 0xf0) \| (data & 0x0f);
2051		chr1_0(space->machine, vrom_bank[0], CHRROM);
	2087	state->vrom_bank[0] = (state->vrom_bank[0] & 0xf0) \| (data & 0x0f);
	2088	chr1_0(space->machine, state->vrom_bank[0], CHRROM);
2052	2089	break;
2053	2090	case 0x3002:
2054	2091	case 0x3040:
2055		vrom_bank[0] = (vrom_bank[0] & 0x0f) \| (data << 4);
2056		chr1_0(space->machine, vrom_bank[0], CHRROM);
	2092	state->vrom_bank[0] = (state->vrom_bank[0] & 0x0f) \| (data << 4);
	2093	chr1_0(space->machine, state->vrom_bank[0], CHRROM);
2057	2094	break;
2058	2095	case 0x3004:
2059	2096	case 0x3080:
2060		vrom_bank[1] = (vrom_bank[1] & 0xf0) \| (data & 0x0f);
2061		chr1_1(space->machine, vrom_bank[1], CHRROM);
	2097	state->vrom_bank[1] = (state->vrom_bank[1] & 0xf0) \| (data & 0x0f);
	2098	chr1_1(space->machine, state->vrom_bank[1], CHRROM);
2062	2099	break;
2063	2100	case 0x3006:
2064	2101	case 0x30c0:
2065		vrom_bank[1] = (vrom_bank[1] & 0x0f) \| (data << 4);
2066		chr1_1(space->machine, vrom_bank[1], CHRROM);
	2102	state->vrom_bank[1] = (state->vrom_bank[1] & 0x0f) \| (data << 4);
	2103	chr1_1(space->machine, state->vrom_bank[1], CHRROM);
2067	2104	break;
2068	2105	case 0x4000:
2069		vrom_bank[2] = (vrom_bank[2] & 0xf0) \| (data & 0x0f);
2070		chr1_2(space->machine, vrom_bank[2], CHRROM);
	2106	state->vrom_bank[2] = (state->vrom_bank[2] & 0xf0) \| (data & 0x0f);
	2107	chr1_2(space->machine, state->vrom_bank[2], CHRROM);
2071	2108	break;
2072	2109	case 0x4002:
2073	2110	case 0x4040:
2074		vrom_bank[2] = (vrom_bank[2] & 0x0f) \| (data << 4);
2075		chr1_2(space->machine, vrom_bank[2], CHRROM);
	2111	state->vrom_bank[2] = (state->vrom_bank[2] & 0x0f) \| (data << 4);
	2112	chr1_2(space->machine, state->vrom_bank[2], CHRROM);
2076	2113	break;
2077	2114	case 0x4004:
2078	2115	case 0x4080:
2079		vrom_bank[3] = (vrom_bank[3] & 0xf0) \| (data & 0x0f);
2080		chr1_3(space->machine, vrom_bank[3], CHRROM);
	2116	state->vrom_bank[3] = (state->vrom_bank[3] & 0xf0) \| (data & 0x0f);
	2117	chr1_3(space->machine, state->vrom_bank[3], CHRROM);
2081	2118	break;
2082	2119	case 0x4006:
2083	2120	case 0x40c0:
2084		vrom_bank[3] = (vrom_bank[3] & 0x0f) \| (data << 4);
2085		chr1_3(space->machine, vrom_bank[3], CHRROM);
	2121	state->vrom_bank[3] = (state->vrom_bank[3] & 0x0f) \| (data << 4);
	2122	chr1_3(space->machine, state->vrom_bank[3], CHRROM);
2086	2123	break;
2087	2124	case 0x5000:
2088		vrom_bank[4] = (vrom_bank[4] & 0xf0) \| (data & 0x0f);
2089		chr1_4(space->machine, vrom_bank[4], CHRROM);
	2125	state->vrom_bank[4] = (state->vrom_bank[4] & 0xf0) \| (data & 0x0f);
	2126	chr1_4(space->machine, state->vrom_bank[4], CHRROM);
2090	2127	break;
2091	2128	case 0x5002:
2092	2129	case 0x5040:
2093		vrom_bank[4] = (vrom_bank[4] & 0x0f) \| (data << 4);
2094		chr1_4(space->machine, vrom_bank[4], CHRROM);
	2130	state->vrom_bank[4] = (state->vrom_bank[4] & 0x0f) \| (data << 4);
	2131	chr1_4(space->machine, state->vrom_bank[4], CHRROM);
2095	2132	break;
2096	2133	case 0x5004:
2097	2134	case 0x5080:
2098		vrom_bank[5] = (vrom_bank[5] & 0xf0) \| (data & 0x0f);
2099		chr1_5(space->machine, vrom_bank[5], CHRROM);
	2135	state->vrom_bank[5] = (state->vrom_bank[5] & 0xf0) \| (data & 0x0f);
	2136	chr1_5(space->machine, state->vrom_bank[5], CHRROM);
2100	2137	break;
2101	2138	case 0x5006:
2102	2139	case 0x50c0:
2103		vrom_bank[5] = (vrom_bank[5] & 0x0f) \| (data << 4);
2104		chr1_5(space->machine, vrom_bank[5], CHRROM);
	2140	state->vrom_bank[5] = (state->vrom_bank[5] & 0x0f) \| (data << 4);
	2141	chr1_5(space->machine, state->vrom_bank[5], CHRROM);
2105	2142	break;
2106	2143	case 0x6000:
2107		vrom_bank[6] = (vrom_bank[6] & 0xf0) \| (data & 0x0f);
2108		chr1_6(space->machine, vrom_bank[6], CHRROM);
	2144	state->vrom_bank[6] = (state->vrom_bank[6] & 0xf0) \| (data & 0x0f);
	2145	chr1_6(space->machine, state->vrom_bank[6], CHRROM);
2109	2146	break;
2110	2147	case 0x6002:
2111	2148	case 0x6040:
2112		vrom_bank[6] = (vrom_bank[6] & 0x0f) \| (data << 4);
2113		chr1_6(space->machine, vrom_bank[6], CHRROM);
	2149	state->vrom_bank[6] = (state->vrom_bank[6] & 0x0f) \| (data << 4);
	2150	chr1_6(space->machine, state->vrom_bank[6], CHRROM);
2114	2151	break;
2115	2152	case 0x6004:
2116	2153	case 0x6080:
2117		vrom_bank[7] = (vrom_bank[7] & 0xf0) \| (data & 0x0f);
2118		chr1_7(space->machine, vrom_bank[7], CHRROM);
	2154	state->vrom_bank[7] = (state->vrom_bank[7] & 0xf0) \| (data & 0x0f);
	2155	chr1_7(space->machine, state->vrom_bank[7], CHRROM);
2119	2156	break;
2120	2157	case 0x6006:
2121	2158	case 0x60c0:
2122		vrom_bank[7] = (vrom_bank[7] & 0x0f) \| (data << 4);
2123		chr1_7(space->machine, vrom_bank[7], CHRROM);
	2159	state->vrom_bank[7] = (state->vrom_bank[7] & 0x0f) \| (data << 4);
	2160	chr1_7(space->machine, state->vrom_bank[7], CHRROM);
2124	2161	break;
2125	2162
2126	2163	case 0x7000:
2127		IRQ_count_latch = (IRQ_count_latch & 0xf0) \| (data & 0x0f);
	2164	state->IRQ_count_latch = (state->IRQ_count_latch & 0xf0) \| (data & 0x0f);
2128	2165	break;
2129	2166	case 0x7002:
2130	2167	case 0x7040:
2131		IRQ_count_latch = (IRQ_count_latch & 0x0f) \| ((data & 0x0f) << 4 );
	2168	state->IRQ_count_latch = (state->IRQ_count_latch & 0x0f) \| ((data & 0x0f) << 4 );
2132	2169	break;
2133	2170	case 0x7004:
2134	2171	case 0x7080:
2135		IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
2136		IRQ_enable = data & 0x02;
2137		IRQ_enable_latch = data & 0x01;
	2172	state->IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
	2173	state->IRQ_enable = data & 0x02;
	2174	state->IRQ_enable_latch = data & 0x01;
2138	2175	if (data & 0x02)
2139		IRQ_count = IRQ_count_latch;
	2176	state->IRQ_count = state->IRQ_count_latch;
2140	2177	break;
2141	2178	case 0x7006:
2142	2179	case 0x70c0:
2143		IRQ_enable = IRQ_enable_latch;
	2180	state->IRQ_enable = state->IRQ_enable_latch;
2144	2181	break;
2145	2182	default:
2146	2183	LOG_MMC(("konami_vrc4a_w uncaught offset: %04x value: %02x\n", offset, data));
r7955	r7956
2150	2187
2151	2188	static WRITE8_HANDLER( konami_vrc4b_w )
2152	2189	{
	2190	nes_state state = (nes_state )space->machine->driver_data;
2153	2191	LOG_MMC(("konami_vrc4b_w, offset: %04x, data: %02x\n", offset, data));
2154	2192
2155	2193	switch (offset & 0x7fff)
r7955	r7956
2161	2199	case 0x0004:
2162	2200	case 0x0008:
2163	2201	case 0x000c:
2164		prg_bank[0] = data;
	2202	state->prg_bank[0] = data;
2165	2203	vrc4_set_prg(space->machine);
2166	2204	break;
2167	2205
r7955	r7956
2181	2219	case 0x1003:
2182	2220	case 0x1004:
2183	2221	case 0x100c:
2184		mmc_cmd1 = data & 0x02;
	2222	state->mmc_cmd1 = data & 0x02;
2185	2223	vrc4_set_prg(space->machine);
2186	2224	break;
2187	2225
r7955	r7956
2196	2234	break;
2197	2235
2198	2236	case 0x3000:
2199		vrom_bank[0] = (vrom_bank[0] & 0xf0) \| (data & 0x0f);
2200		chr1_0(space->machine, vrom_bank[0], CHRROM);
	2237	state->vrom_bank[0] = (state->vrom_bank[0] & 0xf0) \| (data & 0x0f);
	2238	chr1_0(space->machine, state->vrom_bank[0], CHRROM);
2201	2239	break;
2202	2240	case 0x3002:
2203	2241	case 0x3008:
2204		vrom_bank[0] = (vrom_bank[0] & 0x0f) \| (data << 4);
2205		chr1_0(space->machine, vrom_bank[0], CHRROM);
	2242	state->vrom_bank[0] = (state->vrom_bank[0] & 0x0f) \| (data << 4);
	2243	chr1_0(space->machine, state->vrom_bank[0], CHRROM);
2206	2244	break;
2207	2245	case 0x3001:
2208	2246	case 0x3004:
2209		vrom_bank[1] = (vrom_bank[1] & 0xf0) \| (data & 0x0f);
2210		chr1_1(space->machine, vrom_bank[1], CHRROM);
	2247	state->vrom_bank[1] = (state->vrom_bank[1] & 0xf0) \| (data & 0x0f);
	2248	chr1_1(space->machine, state->vrom_bank[1], CHRROM);
2211	2249	break;
2212	2250	case 0x3003:
2213	2251	case 0x300c:
2214		vrom_bank[1] = (vrom_bank[1] & 0x0f) \| (data << 4);
2215		chr1_1(space->machine, vrom_bank[1], CHRROM);
	2252	state->vrom_bank[1] = (state->vrom_bank[1] & 0x0f) \| (data << 4);
	2253	chr1_1(space->machine, state->vrom_bank[1], CHRROM);
2216	2254	break;
2217	2255	case 0x4000:
2218		vrom_bank[2] = (vrom_bank[2] & 0xf0) \| (data & 0x0f);
2219		chr1_2(space->machine, vrom_bank[2], CHRROM);
	2256	state->vrom_bank[2] = (state->vrom_bank[2] & 0xf0) \| (data & 0x0f);
	2257	chr1_2(space->machine, state->vrom_bank[2], CHRROM);
2220	2258	break;
2221	2259	case 0x4002:
2222	2260	case 0x4008:
2223		vrom_bank[2] = (vrom_bank[2] & 0x0f) \| (data << 4);
2224		chr1_2(space->machine, vrom_bank[2], CHRROM);
	2261	state->vrom_bank[2] = (state->vrom_bank[2] & 0x0f) \| (data << 4);
	2262	chr1_2(space->machine, state->vrom_bank[2], CHRROM);
2225	2263	break;
2226	2264	case 0x4001:
2227	2265	case 0x4004:
2228		vrom_bank[3] = (vrom_bank[3] & 0xf0) \| (data & 0x0f);
2229		chr1_3(space->machine, vrom_bank[3], CHRROM);
	2266	state->vrom_bank[3] = (state->vrom_bank[3] & 0xf0) \| (data & 0x0f);
	2267	chr1_3(space->machine, state->vrom_bank[3], CHRROM);
2230	2268	break;
2231	2269	case 0x4003:
2232	2270	case 0x400c:
2233		vrom_bank[3] = (vrom_bank[3] & 0x0f) \| (data << 4);
2234		chr1_3(space->machine, vrom_bank[3], CHRROM);
	2271	state->vrom_bank[3] = (state->vrom_bank[3] & 0x0f) \| (data << 4);
	2272	chr1_3(space->machine, state->vrom_bank[3], CHRROM);
2235	2273	break;
2236	2274	case 0x5000:
2237		vrom_bank[4] = (vrom_bank[4] & 0xf0) \| (data & 0x0f);
2238		chr1_4(space->machine, vrom_bank[4], CHRROM);
	2275	state->vrom_bank[4] = (state->vrom_bank[4] & 0xf0) \| (data & 0x0f);
	2276	chr1_4(space->machine, state->vrom_bank[4], CHRROM);
2239	2277	break;
2240	2278	case 0x5002:
2241	2279	case 0x5008:
2242		vrom_bank[4] = (vrom_bank[4] & 0x0f) \| (data << 4);
2243		chr1_4(space->machine, vrom_bank[4], CHRROM);
	2280	state->vrom_bank[4] = (state->vrom_bank[4] & 0x0f) \| (data << 4);
	2281	chr1_4(space->machine, state->vrom_bank[4], CHRROM);
2244	2282	break;
2245	2283	case 0x5001:
2246	2284	case 0x5004:
2247		vrom_bank[5] = (vrom_bank[5] & 0xf0) \| (data & 0x0f);
2248		chr1_5(space->machine, vrom_bank[5], CHRROM);
	2285	state->vrom_bank[5] = (state->vrom_bank[5] & 0xf0) \| (data & 0x0f);
	2286	chr1_5(space->machine, state->vrom_bank[5], CHRROM);
2249	2287	break;
2250	2288	case 0x5003:
2251	2289	case 0x500c:
2252		vrom_bank[5] = (vrom_bank[5] & 0x0f) \| (data << 4);
2253		chr1_5(space->machine, vrom_bank[5], CHRROM);
	2290	state->vrom_bank[5] = (state->vrom_bank[5] & 0x0f) \| (data << 4);
	2291	chr1_5(space->machine, state->vrom_bank[5], CHRROM);
2254	2292	break;
2255	2293	case 0x6000:
2256		vrom_bank[6] = (vrom_bank[6] & 0xf0) \| (data & 0x0f);
2257		chr1_6(space->machine, vrom_bank[6], CHRROM);
	2294	state->vrom_bank[6] = (state->vrom_bank[6] & 0xf0) \| (data & 0x0f);
	2295	chr1_6(space->machine, state->vrom_bank[6], CHRROM);
2258	2296	break;
2259	2297	case 0x6002:
2260	2298	case 0x6008:
2261		vrom_bank[6] = (vrom_bank[6] & 0x0f) \| (data << 4);
2262		chr1_6(space->machine, vrom_bank[6], CHRROM);
	2299	state->vrom_bank[6] = (state->vrom_bank[6] & 0x0f) \| (data << 4);
	2300	chr1_6(space->machine, state->vrom_bank[6], CHRROM);
2263	2301	break;
2264	2302	case 0x6001:
2265	2303	case 0x6004:
2266		vrom_bank[7] = (vrom_bank[7] & 0xf0) \| (data & 0x0f);
2267		chr1_7(space->machine, vrom_bank[7], CHRROM);
	2304	state->vrom_bank[7] = (state->vrom_bank[7] & 0xf0) \| (data & 0x0f);
	2305	chr1_7(space->machine, state->vrom_bank[7], CHRROM);
2268	2306	break;
2269	2307	case 0x6003:
2270	2308	case 0x600c:
2271		vrom_bank[7] = (vrom_bank[7] & 0x0f) \| (data << 4);
2272		chr1_7(space->machine, vrom_bank[7], CHRROM);
	2309	state->vrom_bank[7] = (state->vrom_bank[7] & 0x0f) \| (data << 4);
	2310	chr1_7(space->machine, state->vrom_bank[7], CHRROM);
2273	2311	break;
2274	2312
2275	2313	case 0x7000:
2276		IRQ_count_latch = (IRQ_count_latch & 0xf0) \| (data & 0x0f);
	2314	state->IRQ_count_latch = (state->IRQ_count_latch & 0xf0) \| (data & 0x0f);
2277	2315	break;
2278	2316	case 0x7002:
2279	2317	case 0x7008:
2280		IRQ_count_latch = (IRQ_count_latch & 0x0f) \| ((data & 0x0f) << 4 );
	2318	state->IRQ_count_latch = (state->IRQ_count_latch & 0x0f) \| ((data & 0x0f) << 4 );
2281	2319	break;
2282	2320	case 0x7001:
2283	2321	case 0x7004:
2284		IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
2285		IRQ_enable = data & 0x02;
2286		IRQ_enable_latch = data & 0x01;
	2322	state->IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
	2323	state->IRQ_enable = data & 0x02;
	2324	state->IRQ_enable_latch = data & 0x01;
2287	2325	if (data & 0x02)
2288		IRQ_count = IRQ_count_latch;
	2326	state->IRQ_count = state->IRQ_count_latch;
2289	2327	break;
2290	2328	case 0x7003:
2291	2329	case 0x700c:
2292		IRQ_enable = IRQ_enable_latch;
	2330	state->IRQ_enable = state->IRQ_enable_latch;
2293	2331	break;
2294	2332	default:
2295	2333	LOG_MMC(("konami_vrc4b_w uncaught offset: %04x value: %02x\n", offset, data));
r7955	r7956
2310	2348
2311	2349	static WRITE8_HANDLER( konami_vrc2a_w )
2312	2350	{
	2351	nes_state state = (nes_state )space->machine->driver_data;
2313	2352	UINT8 bank;
2314	2353	LOG_MMC(("konami_vrc2a_w, offset: %04x, data: %02x\n", offset, data));
2315	2354
r7955	r7956
2335	2374	case 0x5000:
2336	2375	case 0x6000:
2337	2376	bank = ((offset & 0x7000) - 0x3000) / 0x0800 + (offset & 0x0001);
2338		/* Notice that we store the banks as in other VRC, but then we take vrom_bank>>1 because it's VRC2A!*/
	2377	/* Notice that we store the banks as in other VRC, but then we take state->vrom_bank>>1 because it's VRC2A!*/
2339	2378	if (offset & 0x0002)
2340		vrom_bank[bank] = (vrom_bank[bank] & 0x0f) \| (data << 4);
	2379	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0x0f) \| (data << 4);
2341	2380	else
2342		vrom_bank[bank] = (vrom_bank[bank] & 0xf0) \| (data & 0x0f);
	2381	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0xf0) \| (data & 0x0f);
2343	2382
2344		chr1_x(space->machine, bank, vrom_bank[bank] >> 1, CHRROM);
	2383	chr1_x(space->machine, bank, state->vrom_bank[bank] >> 1, CHRROM);
2345	2384	break;
2346	2385
2347	2386	default:
r7955	r7956
2363	2402
2364	2403	static WRITE8_HANDLER( konami_vrc2b_w )
2365	2404	{
	2405	nes_state state = (nes_state )space->machine->driver_data;
2366	2406	UINT16 select;
2367	2407	UINT8 bank;
2368	2408
r7955	r7956
2417	2457	case 0x6003:
2418	2458	bank = ((select & 0x7000) - 0x3000) / 0x0800 + ((select & 0x0002) >> 1);
2419	2459	if (select & 0x0001)
2420		vrom_bank[bank] = (vrom_bank[bank] & 0x0f) \| (data << 4);
	2460	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0x0f) \| (data << 4);
2421	2461	else
2422		vrom_bank[bank] = (vrom_bank[bank] & 0xf0) \| (data & 0x0f);
	2462	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0xf0) \| (data & 0x0f);
2423	2463
2424		chr1_x(space->machine, bank, vrom_bank[bank], mmc_chr_source);
	2464	chr1_x(space->machine, bank, state->vrom_bank[bank], state->mmc_chr_source);
2425	2465	break;
2426	2466	case 0x7000:
2427		IRQ_count_latch &= ~0x0f;
2428		IRQ_count_latch \|= data & 0x0f;
	2467	state->IRQ_count_latch &= ~0x0f;
	2468	state->IRQ_count_latch \|= data & 0x0f;
2429	2469	break;
2430	2470	case 0x7001:
2431		IRQ_count_latch &= ~0xf0;
2432		IRQ_count_latch \|= (data << 4) & 0xf0;
	2471	state->IRQ_count_latch &= ~0xf0;
	2472	state->IRQ_count_latch \|= (data << 4) & 0xf0;
2433	2473	break;
2434	2474	case 0x7002:
2435		IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
2436		IRQ_enable = data & 0x02;
2437		IRQ_enable_latch = data & 0x01;
	2475	state->IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
	2476	state->IRQ_enable = data & 0x02;
	2477	state->IRQ_enable_latch = data & 0x01;
2438	2478	if (data & 0x02)
2439		IRQ_count = IRQ_count_latch;
	2479	state->IRQ_count = state->IRQ_count_latch;
2440	2480	break;
2441	2481
2442	2482	default:
r7955	r7956
2458	2498
2459	2499	static WRITE8_HANDLER( konami_vrc6a_w )
2460	2500	{
	2501	nes_state state = (nes_state )space->machine->driver_data;
2461	2502	UINT8 bank;
2462	2503	LOG_MMC(("konami_vrc6a_w, offset: %04x, data: %02x\n", offset, data));
2463	2504
r7955	r7956
2502	2543	break;
2503	2544
2504	2545	case 0x7000:
2505		IRQ_count_latch = data;
	2546	state->IRQ_count_latch = data;
2506	2547	break;
2507	2548	case 0x7001:
2508		IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
2509		IRQ_enable = data & 0x02;
2510		IRQ_enable_latch = data & 0x01;
	2549	state->IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
	2550	state->IRQ_enable = data & 0x02;
	2551	state->IRQ_enable_latch = data & 0x01;
2511	2552	if (data & 0x02)
2512		IRQ_count = IRQ_count_latch;
	2553	state->IRQ_count = state->IRQ_count_latch;
2513	2554	break;
2514	2555	case 0x7002:
2515		IRQ_enable = IRQ_enable_latch;
	2556	state->IRQ_enable = state->IRQ_enable_latch;
2516	2557	break;
2517	2558
2518	2559	default:
r7955	r7956
2534	2575
2535	2576	static WRITE8_HANDLER( konami_vrc6b_w )
2536	2577	{
	2578	nes_state state = (nes_state )space->machine->driver_data;
2537	2579	UINT8 bank;
2538	2580
2539	2581	LOG_MMC(("konami_vrc6b_w, offset: %04x, data: %02x\n", offset, data));
r7955	r7956
2572	2614	chr1_x(space->machine, bank, data, CHRROM);
2573	2615	break;
2574	2616	case 0x7000:
2575		IRQ_count_latch = data;
	2617	state->IRQ_count_latch = data;
2576	2618	break;
2577	2619	case 0x7001:
2578		IRQ_enable = IRQ_enable_latch;
	2620	state->IRQ_enable = state->IRQ_enable_latch;
2579	2621	break;
2580	2622	case 0x7002:
2581		IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
2582		IRQ_enable = data & 0x02;
2583		IRQ_enable_latch = data & 0x01;
	2623	state->IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
	2624	state->IRQ_enable = data & 0x02;
	2625	state->IRQ_enable_latch = data & 0x01;
2584	2626	if (data & 0x02)
2585		IRQ_count = IRQ_count_latch;
	2627	state->IRQ_count = state->IRQ_count_latch;
2586	2628	break;
2587	2629
2588	2630	default:
r7955	r7956
2669	2711	switch (offset & 0x7000)
2670	2712	{
2671	2713	case 0x0000:
2672		mmc_cmd1 ? prg8_cd(space->machine, data) : prg8_89(space->machine, data);
	2714	state->mmc_cmd1 ? prg8_cd(space->machine, data) : prg8_89(space->machine, data);
2673	2715	break;
2674	2716	case 0x1000:
2675		mmc_cmd1 = data & 0x02;
	2717	state->mmc_cmd1 = data & 0x02;
2676	2718	if (!state->crc_hack) // Major League has hardwired mirroring (it would have required a separate mapper)
2677	2719	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
2678	2720	break;
r7955	r7956
2798	2840
2799	2841	static void mapper35_irq( running_device *device, int scanline, int vblank, int blanked )
2800	2842	{
2801		if (scanline < PPU_BOTTOM_VISIBLE_SCANLINE && IRQ_enable)
	2843	nes_state state = (nes_state )device->machine->driver_data;
	2844
	2845	if (scanline < PPU_BOTTOM_VISIBLE_SCANLINE && state->IRQ_enable)
2802	2846	{
2803		IRQ_count--;
	2847	state->IRQ_count--;
2804	2848
2805		if (!blanked && (IRQ_count == 0))
	2849	if (!blanked && (state->IRQ_count == 0))
2806	2850	{
2807	2851	LOG_MMC(("irq fired, scanline: %d (MAME %d, beam pos: %d)\n", scanline,
2808	2852	video_screen_get_vpos(device->machine->primary_screen), video_screen_get_hpos(device->machine->primary_screen)));
2809	2853	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
2810		IRQ_enable = 0;
	2854	state->IRQ_enable = 0;
2811	2855	}
2812	2856	}
2813	2857	}
2814	2858
2815	2859	static WRITE8_HANDLER( mapper35_w )
2816	2860	{
	2861	nes_state state = (nes_state )space->machine->driver_data;
2817	2862	LOG_MMC(("mapper35_w, offset: %04x, data: %02x\n", offset, data));
2818	2863
2819	2864	switch (offset)
r7955	r7956
2825	2870	prg8_ab(space->machine, data);
2826	2871	break;
2827	2872	case 0x0002:
2828		// prg_bank[offset & 0x02] = data;
	2873	// state->prg_bank[offset & 0x02] = data;
2829	2874	prg8_cd(space->machine, data);
2830	2875	break;
2831	2876	case 0x1000:
r7955	r7956
2836	2881	case 0x1005:
2837	2882	case 0x1006:
2838	2883	case 0x1007:
2839		// vrom_bank[offset & 0x07] = data;
	2884	// state->vrom_bank[offset & 0x07] = data;
2840	2885	chr1_x(space->machine, offset & 0x07, data, CHRROM);
2841	2886	break;
2842	2887	case 0x4002:
2843		IRQ_enable = 0;
	2888	state->IRQ_enable = 0;
2844	2889	break;
2845	2890	case 0x4003:
2846		IRQ_enable = 1;
	2891	state->IRQ_enable = 1;
2847	2892	break;
2848	2893	case 0x4005:
2849		IRQ_count = data;
	2894	state->IRQ_count = data;
2850	2895	break;
2851	2896	case 0x5001:
2852	2897	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
r7955	r7956
2891	2936
2892	2937	static WRITE8_HANDLER( mapper37_m_w )
2893	2938	{
	2939	nes_state state = (nes_state )space->machine->driver_data;
2894	2940	UINT8 map37_helper;
2895	2941	LOG_MMC(("mapper37_m_w, offset: %04x, data: %02x\n", offset, data));
2896	2942
2897	2943	map37_helper = (data & 0x06) >> 1;
2898	2944
2899		mmc_prg_base = map37_helper << 3;
2900		mmc_prg_mask = (map37_helper == 2) ? 0x0f : 0x07;
2901		mmc_chr_base = map37_helper << 6;
2902		mmc_chr_mask = 0x7f;
2903		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
2904		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	2945	state->mmc_prg_base = map37_helper << 3;
	2946	state->mmc_prg_mask = (map37_helper == 2) ? 0x0f : 0x07;
	2947	state->mmc_chr_base = map37_helper << 6;
	2948	state->mmc_chr_mask = 0x7f;
	2949	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
	2950	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
2905	2951	}
2906	2952
2907	2953	/*************************************************************
r7955	r7956
2954	3000
2955	3001	static void mapper40_irq( running_device *device, int scanline, int vblank, int blanked )
2956	3002	{
2957		if (IRQ_enable)
	3003	nes_state state = (nes_state )device->machine->driver_data;
	3004
	3005	if (state->IRQ_enable)
2958	3006	{
2959		if ((0xfff - IRQ_count) <= 114)
	3007	if ((0xfff - state->IRQ_count) <= 114)
2960	3008	{
2961		IRQ_count = (IRQ_count + 1) & 0xfff;
2962		IRQ_enable = 0;
	3009	state->IRQ_count = (state->IRQ_count + 1) & 0xfff;
	3010	state->IRQ_enable = 0;
2963	3011	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
2964	3012	}
2965	3013	else
2966		IRQ_count += 114;
	3014	state->IRQ_count += 114;
2967	3015	}
2968	3016	}
2969	3017
2970	3018	static WRITE8_HANDLER( mapper40_w )
2971	3019	{
	3020	nes_state state = (nes_state )space->machine->driver_data;
2972	3021	LOG_MMC(("mapper40_w, offset: %04x, data: %02x\n", offset, data));
2973	3022
2974	3023	switch (offset & 0x6000)
2975	3024	{
2976	3025	case 0x0000:
2977		IRQ_enable = 0;
2978		IRQ_count = 0;
	3026	state->IRQ_enable = 0;
	3027	state->IRQ_count = 0;
2979	3028	break;
2980	3029	case 0x2000:
2981		IRQ_enable = 1;
	3030	state->IRQ_enable = 1;
2982	3031	break;
2983	3032	case 0x6000:
2984	3033	prg8_cd(space->machine, data);
r7955	r7956
2999	3048
3000	3049	static WRITE8_HANDLER( mapper41_m_w )
3001	3050	{
	3051	nes_state state = (nes_state )space->machine->driver_data;
3002	3052	LOG_MMC(("mapper41_m_w, offset: %04x, data: %02x\n", offset, data));
3003	3053
3004		mmc_cmd1 = offset & 0xff;
	3054	state->mmc_cmd1 = offset & 0xff;
3005	3055	set_nt_mirroring(space->machine, BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3006	3056	prg32(space->machine, offset & 0x07);
3007	3057	}
3008	3058
3009	3059	static WRITE8_HANDLER( mapper41_w )
3010	3060	{
	3061	nes_state state = (nes_state )space->machine->driver_data;
3011	3062	LOG_MMC(("mapper41_w, offset: %04x, data: %02x\n", offset, data));
3012	3063
3013		if (mmc_cmd1 & 0x04)
3014		chr8(space->machine, ((mmc_cmd1 & 0x18) >> 1) \| (data & 0x03), CHRROM);
	3064	if (state->mmc_cmd1 & 0x04)
	3065	chr8(space->machine, ((state->mmc_cmd1 & 0x18) >> 1) \| (data & 0x03), CHRROM);
3015	3066	}
3016	3067
3017	3068	/*************************************************************
r7955	r7956
3029	3080
3030	3081	static WRITE8_HANDLER( mapper42_w )
3031	3082	{
	3083	nes_state state = (nes_state )space->machine->driver_data;
3032	3084	LOG_MMC(("mapper42_w, offset: %04x, data: %02x\n", offset, data));
3033	3085
3034	3086	if (offset >= 0x7000)
r7955	r7956
3043	3095	break;
3044	3096	case 0x02:
3045	3097	/* Check if IRQ is being enabled */
3046		if (!IRQ_enable && (data & 0x02))
	3098	if (!state->IRQ_enable && (data & 0x02))
3047	3099	{
3048		IRQ_enable = 1;
	3100	state->IRQ_enable = 1;
3049	3101	timer_adjust_oneshot(nes_irq_timer, cputag_clocks_to_attotime(space->machine, "maincpu", 24576), 0);
3050	3102	}
3051	3103	if (!(data & 0x02))
3052	3104	{
3053		IRQ_enable = 0;
	3105	state->IRQ_enable = 0;
3054	3106	timer_adjust_oneshot(nes_irq_timer, attotime_never, 0);
3055	3107	}
3056	3108	break;
r7955	r7956
3138	3190
3139	3191	static WRITE8_HANDLER( mapper44_w )
3140	3192	{
	3193	nes_state state = (nes_state )space->machine->driver_data;
3141	3194	UINT8 page;
3142	3195	LOG_MMC(("mapper44_w offset: %04x, data: %02x\n", offset, data));
3143	3196
r7955	r7956
3148	3201	if (page > 6)
3149	3202	page = 6;
3150	3203
3151		mmc_prg_base = page << 4;
3152		mmc_prg_mask = (page > 5) ? 0x1f : 0x0f;
3153		mmc_chr_base = page << 7;
3154		mmc_chr_mask = (page > 5) ? 0xff : 0x7f;
3155		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
3156		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	3204	state->mmc_prg_base = page << 4;
	3205	state->mmc_prg_mask = (page > 5) ? 0x1f : 0x0f;
	3206	state->mmc_chr_base = page << 7;
	3207	state->mmc_chr_mask = (page > 5) ? 0xff : 0x7f;
	3208	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
	3209	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
3157	3210	break;
3158	3211
3159	3212	default:
r7955	r7956
3184	3237	state->wram[offset] = data;
3185	3238	else
3186	3239	{
3187		mapper45_reg[mmc_count] = data;
3188		mmc_count = (mmc_count + 1) & 0x03;
	3240	mapper45_reg[state->mmc_count] = data;
	3241	state->mmc_count = (state->mmc_count + 1) & 0x03;
3189	3242
3190		if (!mmc_count)
	3243	if (!state->mmc_count)
3191	3244	{
3192	3245	LOG_MMC(("mapper45_m_w, command completed %02x %02x %02x %02x\n", mapper45_reg[3],
3193	3246	mapper45_reg[2], mapper45_reg[1], mapper45_reg[0]));
3194	3247
3195		mmc_prg_base = mapper45_reg[1];
3196		mmc_prg_mask = 0x3f ^ (mapper45_reg[3] & 0x3f);
3197		mmc_chr_base = ((mapper45_reg[2] & 0xf0) << 4) + mapper45_reg[0];
3198		mmc_chr_mask = 0xff >> (~mapper45_reg[2] & 0x0f);
3199		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
3200		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	3248	state->mmc_prg_base = mapper45_reg[1];
	3249	state->mmc_prg_mask = 0x3f ^ (mapper45_reg[3] & 0x3f);
	3250	state->mmc_chr_base = ((mapper45_reg[2] & 0xf0) << 4) + mapper45_reg[0];
	3251	state->mmc_chr_mask = 0xff >> (~mapper45_reg[2] & 0x0f);
	3252	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
	3253	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
3201	3254	}
3202	3255	}
3203	3256	}
r7955	r7956
3215	3268
3216	3269	static WRITE8_HANDLER( mapper46_m_w )
3217	3270	{
	3271	nes_state state = (nes_state )space->machine->driver_data;
3218	3272	LOG_MMC(("mapper46_m_w, offset: %04x, data: %02x\n", offset, data));
3219	3273
3220		prg_bank[0] = (prg_bank[0] & 0x01) \| ((data & 0x0f) << 1);
3221		vrom_bank[0] = (vrom_bank[0] & 0x07) \| ((data & 0xf0) >> 1);
3222		prg32(space->machine, prg_bank[0]);
3223		chr8(space->machine, vrom_bank[0], CHRROM);
	3274	state->prg_bank[0] = (state->prg_bank[0] & 0x01) \| ((data & 0x0f) << 1);
	3275	state->vrom_bank[0] = (state->vrom_bank[0] & 0x07) \| ((data & 0xf0) >> 1);
	3276	prg32(space->machine, state->prg_bank[0]);
	3277	chr8(space->machine, state->vrom_bank[0], CHRROM);
3224	3278	}
3225	3279
3226	3280	static WRITE8_HANDLER( mapper46_w )
3227	3281	{
	3282	nes_state state = (nes_state )space->machine->driver_data;
3228	3283	LOG_MMC(("mapper46_w, offset: %04x, data: %02x\n", offset, data));
3229	3284
3230		prg_bank[0] = (prg_bank[0] & ~0x01) \| (data & 0x01);
3231		vrom_bank[0] = (vrom_bank[0] & ~0x07) \| ((data & 0x70) >> 4);
3232		prg32(space->machine, prg_bank[0]);
3233		chr8(space->machine, vrom_bank[0], CHRROM);
	3285	state->prg_bank[0] = (state->prg_bank[0] & ~0x01) \| (data & 0x01);
	3286	state->vrom_bank[0] = (state->vrom_bank[0] & ~0x07) \| ((data & 0x70) >> 4);
	3287	prg32(space->machine, state->prg_bank[0]);
	3288	chr8(space->machine, state->vrom_bank[0], CHRROM);
3234	3289	}
3235	3290
3236	3291	/*************************************************************
r7955	r7956
3246	3301
3247	3302	static WRITE8_HANDLER( mapper47_m_w )
3248	3303	{
	3304	nes_state state = (nes_state )space->machine->driver_data;
3249	3305	LOG_MMC(("mapper47_m_w, offset: %04x, data: %02x\n", offset, data));
3250	3306
3251		mmc_prg_base = (data & 0x01) << 4;
3252		mmc_prg_mask = 0x0f;
3253		mmc_chr_base = (data & 0x01) << 7;
3254		mmc_chr_mask = 0x7f;
3255		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
3256		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	3307	state->mmc_prg_base = (data & 0x01) << 4;
	3308	state->mmc_prg_mask = 0x0f;
	3309	state->mmc_chr_base = (data & 0x01) << 7;
	3310	state->mmc_chr_mask = 0x7f;
	3311	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
	3312	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
3257	3313	}
3258	3314
3259	3315	/*************************************************************
r7955	r7956
3276	3332
3277	3333	static WRITE8_HANDLER( mapper48_w )
3278	3334	{
	3335	nes_state state = (nes_state )space->machine->driver_data;
3279	3336	LOG_MMC(("mapper48_w, offset: %04x, data: %02x\n", offset, data));
3280	3337
3281	3338	switch (offset & 0x6003)
r7955	r7956
3305	3362	chr1_7(space->machine, data, CHRROM);
3306	3363	break;
3307	3364	case 0x4000:
3308		IRQ_count_latch = (0x100 - data) & 0xff;
	3365	state->IRQ_count_latch = (0x100 - data) & 0xff;
3309	3366	break;
3310	3367	case 0x4001:
3311		IRQ_count = IRQ_count_latch;
	3368	state->IRQ_count = state->IRQ_count_latch;
3312	3369	break;
3313	3370	case 0x4002:
3314		IRQ_enable = 1;
	3371	state->IRQ_enable = 1;
3315	3372	break;
3316	3373	case 0x4003:
3317		IRQ_enable = 0;
	3374	state->IRQ_enable = 0;
3318	3375	break;
3319	3376	case 0x6000:
3320	3377	set_nt_mirroring(space->machine, BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
r7955	r7956
3335	3392
3336	3393	static WRITE8_HANDLER( mapper49_m_w )
3337	3394	{
	3395	nes_state state = (nes_state )space->machine->driver_data;
3338	3396	LOG_MMC(("mapper49_m_w, offset: %04x, data: %02x\n", offset, data));
3339	3397
3340	3398	/* mid writes only work when WRAM is enabled. not sure if I should
3341		change the condition to mmc_cmd2==0x80 (i.e. what is the effect of
	3399	change the condition to state->mmc_cmd2==0x80 (i.e. what is the effect of
3342	3400	the read-only bit?) */
3343		if (mmc_cmd2 & 0x80)
	3401	if (state->mmc_cmd2 & 0x80)
3344	3402	{
3345	3403	if (data & 0x01) /* if this is 0, then we have 32k PRG blocks */
3346	3404	{
3347		mmc_prg_base = (data & 0xc0) >> 2;
3348		mmc_prg_mask = 0x0f;
3349		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	3405	state->mmc_prg_base = (data & 0xc0) >> 2;
	3406	state->mmc_prg_mask = 0x0f;
	3407	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
3350	3408	}
3351	3409	else
3352	3410	prg32(space->machine, (data & 0x30) >> 4);
3353	3411
3354		mmc_chr_base = (data & 0xc0) << 1;
3355		mmc_chr_mask = 0x7f;
3356		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	3412	state->mmc_chr_base = (data & 0xc0) << 1;
	3413	state->mmc_chr_mask = 0x7f;
	3414	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
3357	3415	}
3358	3416	}
3359	3417
r7955	r7956
3372	3430
3373	3431	static void mapper50_irq( running_device *device, int scanline, int vblank, int blanked )
3374	3432	{
3375		if (IRQ_enable)
	3433	nes_state state = (nes_state )device->machine->driver_data;
	3434	if (state->IRQ_enable)
3376	3435	{
3377		if (IRQ_count < 0x1000)
	3436	if (state->IRQ_count < 0x1000)
3378	3437	{
3379		if ((0x1000 - IRQ_count) <= 114)
	3438	if ((0x1000 - state->IRQ_count) <= 114)
3380	3439	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
3381	3440	else
3382		IRQ_count += 114;
	3441	state->IRQ_count += 114;
3383	3442	}
3384	3443	else
3385		IRQ_count += 114;
	3444	state->IRQ_count += 114;
3386	3445
3387		IRQ_count &= 0xffff; // according to docs is 16bit counter -> it wraps only after 0xffff
	3446	state->IRQ_count &= 0xffff; // according to docs is 16bit counter -> it wraps only after 0xffff
3388	3447	}
3389	3448	}
3390	3449
3391	3450	static WRITE8_HANDLER( mapper50_l_w )
3392	3451	{
	3452	nes_state state = (nes_state )space->machine->driver_data;
3393	3453	UINT8 prg;
3394	3454	LOG_MMC(("mapper50_l_w, offset: %04x, data: %02x\n", offset, data));
3395	3455	offset += 0x100;
r7955	r7956
3401	3461	prg8_cd(space->machine, prg);
3402	3462	break;
3403	3463	case 0x120:
3404		IRQ_enable = data & 0x01;
	3464	state->IRQ_enable = data & 0x01;
3405	3465	break;
3406	3466	}
3407	3467	}
r7955	r7956
3487	3547	LOG_MMC(("mapper52_m_w, offset: %04x, data: %02x\n", offset, data));
3488	3548
3489	3549	/* mid writes only work when WRAM is enabled. not sure if I should
3490		change the condition to mmc_cmd2==0x80 (i.e. what is the effect of
	3550	change the condition to state->mmc_cmd2==0x80 (i.e. what is the effect of
3491	3551	the read-only bit?) and it only can happen once! */
3492		if ((mmc_cmd2 & 0x80) && !map52_reg_written)
	3552	if ((state->mmc_cmd2 & 0x80) && !map52_reg_written)
3493	3553	{
3494	3554	map52_helper1 = (data & 0x08);
3495	3555	map52_helper2 = (data & 0x40);
3496	3556
3497		mmc_prg_base = map52_helper1 ? ((data & 0x07) << 4) : ((data & 0x06) << 4);
3498		mmc_prg_mask = map52_helper1 ? 0x0f : 0x1f;
3499		mmc_chr_base = ((data & 0x20) << 4) \| ((data & 0x04) << 6) \| (map52_helper2 ? ((data & 0x10) << 3) : 0);
3500		mmc_chr_mask = map52_helper2 ? 0x7f : 0xff;
3501		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
3502		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	3557	state->mmc_prg_base = map52_helper1 ? ((data & 0x07) << 4) : ((data & 0x06) << 4);
	3558	state->mmc_prg_mask = map52_helper1 ? 0x0f : 0x1f;
	3559	state->mmc_chr_base = ((data & 0x20) << 4) \| ((data & 0x04) << 6) \| (map52_helper2 ? ((data & 0x10) << 3) : 0);
	3560	state->mmc_chr_mask = map52_helper2 ? 0x7f : 0xff;
	3561	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
	3562	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
3503	3563
3504	3564	map52_reg_written = 1;
3505	3565	}
r7955	r7956
3575	3635
3576	3636	static WRITE8_HANDLER( mapper57_w )
3577	3637	{
	3638	nes_state state = (nes_state )space->machine->driver_data;
3578	3639	LOG_MMC(("mapper57_w, offset: %04x, data: %02x\n", offset, data));
3579	3640
3580	3641	if (offset & 0x0800)
3581		{
3582		mmc_cmd2 = data;
3583		}
	3642	state->mmc_cmd2 = data;
3584	3643	else
3585		{
3586		mmc_cmd1 = data;
3587		}
	3644	state->mmc_cmd1 = data;
3588	3645
3589		if (mmc_cmd2 & 0x80)
3590		{
3591		prg32(space->machine, 2 \| (mmc_cmd2 >> 6));
3592		}
	3646	if (state->mmc_cmd2 & 0x80)
	3647	prg32(space->machine, 2 \| (state->mmc_cmd2 >> 6));
3593	3648	else
3594	3649	{
3595		prg16_89ab(space->machine, (mmc_cmd2 >> 5) & 0x03);
3596		prg16_cdef(space->machine, (mmc_cmd2 >> 5) & 0x03);
	3650	prg16_89ab(space->machine, (state->mmc_cmd2 >> 5) & 0x03);
	3651	prg16_cdef(space->machine, (state->mmc_cmd2 >> 5) & 0x03);
3597	3652	}
3598	3653
3599		set_nt_mirroring(space->machine, (mmc_cmd2 & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3654	set_nt_mirroring(space->machine, (state->mmc_cmd2 & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3600	3655
3601		chr8(space->machine, (mmc_cmd1 & 0x03) \| (mmc_cmd2 & 0x07) \| ((mmc_cmd2 & 0x10) >> 1), CHRROM);
	3656	chr8(space->machine, (state->mmc_cmd1 & 0x03) \| (state->mmc_cmd2 & 0x07) \| ((state->mmc_cmd2 & 0x10) >> 1), CHRROM);
3602	3657	}
3603	3658
3604	3659	/*************************************************************
r7955	r7956
3736	3791
3737	3792	static void mapper64_irq( running_device *device, int scanline, int vblank, int blanked )
3738	3793	{
3739		if (!IRQ_mode) // we are in scanline mode!
	3794	nes_state state = (nes_state )device->machine->driver_data;
	3795	if (!state->IRQ_mode) // we are in scanline mode!
3740	3796	{
3741	3797	if (scanline < PPU_BOTTOM_VISIBLE_SCANLINE)
3742	3798	{
3743		if (!IRQ_reset)
	3799	if (!state->IRQ_reset)
3744	3800	{
3745		if (!IRQ_count)
3746		IRQ_count = IRQ_count_latch;
	3801	if (!state->IRQ_count)
	3802	state->IRQ_count = state->IRQ_count_latch;
3747	3803	else
3748	3804	{
3749		IRQ_count--;
3750		if (IRQ_enable && !blanked && !IRQ_count)
	3805	state->IRQ_count--;
	3806	if (state->IRQ_enable && !blanked && !state->IRQ_count)
3751	3807	{
3752	3808	LOG_MMC(("irq fired, scanline: %d (MAME %d, beam pos: %d)\n", scanline,
3753	3809	video_screen_get_vpos(device->machine->primary_screen), video_screen_get_hpos(device->machine->primary_screen)));
r7955	r7956
3757	3813	}
3758	3814	else
3759	3815	{
3760		IRQ_reset = 0;
3761		IRQ_count = IRQ_count_latch + 1;
	3816	state->IRQ_reset = 0;
	3817	state->IRQ_count = state->IRQ_count_latch + 1;
3762	3818	}
3763	3819	}
3764	3820	}
r7955	r7956
3767	3823	--> Skulls and Crossbones does not show anything!! */
3768	3824	else
3769	3825	{
3770		// if (!IRQ_reset)
	3826	// if (!state->IRQ_reset)
3771	3827	{
3772		if (IRQ_count <= 114)
3773		IRQ_count = IRQ_count_latch;
	3828	if (state->IRQ_count <= 114)
	3829	state->IRQ_count = state->IRQ_count_latch;
3774	3830	else
3775	3831	{
3776		IRQ_count -= 114;
3777		if (IRQ_enable && !blanked && (IRQ_count <= 114))
	3832	state->IRQ_count -= 114;
	3833	if (state->IRQ_enable && !blanked && (state->IRQ_count <= 114))
3778	3834	{
3779	3835	LOG_MMC(("irq fired, scanline: %d (MAME %d, beam pos: %d)\n", scanline,
3780	3836	video_screen_get_vpos(device->machine->primary_screen), video_screen_get_hpos(device->machine->primary_screen)));
r7955	r7956
3784	3840	}
3785	3841	// else
3786	3842	// {
3787		// IRQ_reset = 0;
3788		// IRQ_count = IRQ_count_latch + 1;
	3843	// state->IRQ_reset = 0;
	3844	// state->IRQ_count = state->IRQ_count_latch + 1;
3789	3845	// }
3790	3846	}
3791	3847	}
3792	3848
3793	3849	static void mapper64_set_prg( running_machine *machine )
3794	3850	{
3795		UINT8 prg_mode = mmc_cmd1 & 0x40;
	3851	nes_state state = (nes_state )machine->driver_data;
	3852	UINT8 prg_mode = state->mmc_cmd1 & 0x40;
3796	3853
3797		prg8_89(machine, prg_bank[prg_mode ? 2: 0]);
3798		prg8_ab(machine, prg_bank[prg_mode ? 0: 1]);
3799		prg8_cd(machine, prg_bank[prg_mode ? 1: 2]);
	3854	prg8_89(machine, state->prg_bank[prg_mode ? 2: 0]);
	3855	prg8_ab(machine, state->prg_bank[prg_mode ? 0: 1]);
	3856	prg8_cd(machine, state->prg_bank[prg_mode ? 1: 2]);
3800	3857	}
3801	3858
3802	3859	static void mapper64_set_chr( running_machine *machine )
3803	3860	{
3804		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	3861	nes_state state = (nes_state )machine->driver_data;
	3862	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
3805	3863
3806		if (mmc_cmd1 & 0x20)
	3864	if (state->mmc_cmd1 & 0x20)
3807	3865	{
3808		chr1_x(machine, 0 ^ chr_page, vrom_bank[0], CHRROM);
3809		chr1_x(machine, 1 ^ chr_page, vrom_bank[8], CHRROM);
3810		chr1_x(machine, 2 ^ chr_page, vrom_bank[1], CHRROM);
3811		chr1_x(machine, 3 ^ chr_page, vrom_bank[9], CHRROM);
	3866	chr1_x(machine, 0 ^ chr_page, state->vrom_bank[0], CHRROM);
	3867	chr1_x(machine, 1 ^ chr_page, state->vrom_bank[8], CHRROM);
	3868	chr1_x(machine, 2 ^ chr_page, state->vrom_bank[1], CHRROM);
	3869	chr1_x(machine, 3 ^ chr_page, state->vrom_bank[9], CHRROM);
3812	3870	}
3813	3871	else
3814	3872	{
3815		chr1_x(machine, 0 ^ chr_page, vrom_bank[0] & ~0x01, CHRROM);
3816		chr1_x(machine, 1 ^ chr_page, vrom_bank[0] \| 0x01, CHRROM);
3817		chr1_x(machine, 2 ^ chr_page, vrom_bank[1] & ~0x01, CHRROM);
3818		chr1_x(machine, 3 ^ chr_page, vrom_bank[1] \| 0x01, CHRROM);
	3873	chr1_x(machine, 0 ^ chr_page, state->vrom_bank[0] & ~0x01, CHRROM);
	3874	chr1_x(machine, 1 ^ chr_page, state->vrom_bank[0] \| 0x01, CHRROM);
	3875	chr1_x(machine, 2 ^ chr_page, state->vrom_bank[1] & ~0x01, CHRROM);
	3876	chr1_x(machine, 3 ^ chr_page, state->vrom_bank[1] \| 0x01, CHRROM);
3819	3877	}
3820	3878
3821		chr1_x(machine, 4 ^ chr_page, vrom_bank[2], CHRROM);
3822		chr1_x(machine, 5 ^ chr_page, vrom_bank[3], CHRROM);
3823		chr1_x(machine, 6 ^ chr_page, vrom_bank[4], CHRROM);
3824		chr1_x(machine, 7 ^ chr_page, vrom_bank[5], CHRROM);
	3879	chr1_x(machine, 4 ^ chr_page, state->vrom_bank[2], CHRROM);
	3880	chr1_x(machine, 5 ^ chr_page, state->vrom_bank[3], CHRROM);
	3881	chr1_x(machine, 6 ^ chr_page, state->vrom_bank[4], CHRROM);
	3882	chr1_x(machine, 7 ^ chr_page, state->vrom_bank[5], CHRROM);
3825	3883	}
3826	3884
3827	3885	static WRITE8_HANDLER( mapper64_w )
3828	3886	{
	3887	nes_state state = (nes_state )space->machine->driver_data;
3829	3888	UINT8 map64_helper, cmd;
3830	3889	LOG_MMC(("mapper64_w offset: %04x, data: %02x\n", offset, data));
3831	3890
3832	3891	switch (offset & 0x6001)
3833	3892	{
3834	3893	case 0x0000:
3835		map64_helper = mmc_cmd1 ^ data;
3836		mmc_cmd1 = data;
	3894	map64_helper = state->mmc_cmd1 ^ data;
	3895	state->mmc_cmd1 = data;
3837	3896
3838	3897	/* Has PRG Mode changed? */
3839	3898	if (map64_helper & 0x40)
r7955	r7956
3845	3904	break;
3846	3905
3847	3906	case 0x0001:
3848		cmd = mmc_cmd1 & 0x0f;
	3907	cmd = state->mmc_cmd1 & 0x0f;
3849	3908	switch (cmd)
3850	3909	{
3851	3910	case 0: case 1:
3852	3911	case 2: case 3:
3853	3912	case 4: case 5:
3854		vrom_bank[cmd] = data;
	3913	state->vrom_bank[cmd] = data;
3855	3914	mapper64_set_chr(space->machine);
3856	3915	break;
3857	3916	case 6: case 7:
3858		prg_bank[cmd - 6] = data;
	3917	state->prg_bank[cmd - 6] = data;
3859	3918	mapper64_set_prg(space->machine);
3860	3919	break;
3861	3920	case 8: case 9:
3862		vrom_bank[cmd - 2] = data;
	3921	state->vrom_bank[cmd - 2] = data;
3863	3922	mapper64_set_chr(space->machine);
3864	3923	break;
3865	3924	case 0x0f:
3866		prg_bank[2] = data;
	3925	state->prg_bank[2] = data;
3867	3926	mapper64_set_prg(space->machine);
3868	3927	break;
3869	3928	}
r7955	r7956
3874	3933	break;
3875	3934
3876	3935	case 0x4000:
3877		IRQ_count_latch = data;
	3936	state->IRQ_count_latch = data;
3878	3937	break;
3879	3938
3880	3939	case 0x4001: /* $c001 - IRQ scanline latch */
3881		IRQ_mode = data & 0x01;
3882		IRQ_reset = 1;
	3940	state->IRQ_mode = data & 0x01;
	3941	state->IRQ_reset = 1;
3883	3942	break;
3884	3943
3885	3944	case 0x6000:
3886		IRQ_enable = 0;
	3945	state->IRQ_enable = 0;
3887	3946	break;
3888	3947
3889	3948	case 0x6001:
3890		IRQ_enable = 1;
	3949	state->IRQ_enable = 1;
3891	3950	break;
3892	3951
3893	3952	default:
r7955	r7956
3913	3972	there are 3 dots to every 1 CPU cycle, hence 114 is the number of cycles per scanline ) */
3914	3973	static void irem_irq( running_device *device, int scanline, int vblank, int blanked )
3915	3974	{
3916		if (IRQ_enable)
	3975	nes_state state = (nes_state )device->machine->driver_data;
	3976	if (state->IRQ_enable)
3917	3977	{
3918		IRQ_count -= 114;
	3978	state->IRQ_count -= 114;
3919	3979
3920		if (IRQ_count <= 114)
	3980	if (state->IRQ_count <= 114)
3921	3981	{
3922		IRQ_enable = 0;
	3982	state->IRQ_enable = 0;
3923	3983	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
3924	3984	}
3925	3985	}
r7955	r7956
3927	3987
3928	3988	static WRITE8_HANDLER( mapper65_w )
3929	3989	{
	3990	nes_state state = (nes_state )space->machine->driver_data;
3930	3991	LOG_MMC(("mapper65_w, offset %04x, data: %02x\n", offset, data));
3931	3992
3932	3993	switch (offset & 0x7fff)
r7955	r7956
3940	4001	break;
3941	4002
3942	4003	case 0x1003:
3943		IRQ_enable = data & 0x80;
	4004	state->IRQ_enable = data & 0x80;
3944	4005	break;
3945	4006
3946	4007	case 0x1004:
3947		IRQ_count = IRQ_count_latch;
	4008	state->IRQ_count = state->IRQ_count_latch;
3948	4009	break;
3949	4010
3950	4011	case 0x1005:
3951		IRQ_count_latch = (IRQ_count_latch & 0x00ff) \| (data << 8);
	4012	state->IRQ_count_latch = (state->IRQ_count_latch & 0x00ff) \| (data << 8);
3952	4013	break;
3953	4014
3954	4015	case 0x1006:
3955		IRQ_count_latch = (IRQ_count_latch & 0xff00) \| data;
	4016	state->IRQ_count_latch = (state->IRQ_count_latch & 0xff00) \| data;
3956	4017	break;
3957	4018
3958	4019	case 0x2000:
r7955	r7956
4015	4076	there are 3 dots to every 1 CPU cycle, hence 114 is the number of cycles per scanline ) */
4016	4077	static void mapper67_irq( running_device *device, int scanline, int vblank, int blanked )
4017	4078	{
	4079	nes_state state = (nes_state )device->machine->driver_data;
	4080
4018	4081	/* TODO: change to reflect the actual number of cycles spent: both using 114 or cycling 114,114,113
4019	4082	produces a 1-line glitch in Fantasy Zone 2: it really requires the counter to be updated each CPU cycle! */
4020		if (IRQ_enable)
	4083	if (state->IRQ_enable)
4021	4084	{
4022		if (IRQ_count <= 114)
	4085	if (state->IRQ_count <= 114)
4023	4086	{
4024		IRQ_enable = 0;
4025		IRQ_count = 0xffff;
	4087	state->IRQ_enable = 0;
	4088	state->IRQ_count = 0xffff;
4026	4089	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
4027	4090	}
4028	4091	else
4029		IRQ_count -= 114;
	4092	state->IRQ_count -= 114;
4030	4093	}
4031	4094	}
4032	4095
4033	4096	static WRITE8_HANDLER( mapper67_w )
4034	4097	{
	4098	nes_state state = (nes_state )space->machine->driver_data;
4035	4099	LOG_MMC(("mapper67_w, offset %04x, data: %02x\n", offset, data));
	4100
4036	4101	switch (offset & 0x7800)
4037	4102	{
4038	4103	case 0x0800:
r7955	r7956
4049	4114	break;
4050	4115	case 0x4000:
4051	4116	case 0x4800:
4052		IRQ_toggle ^= 1;
4053		if (IRQ_toggle)
4054		IRQ_count = (IRQ_count & 0x00ff) \| (data << 8);
	4117	state->IRQ_toggle ^= 1;
	4118	if (state->IRQ_toggle)
	4119	state->IRQ_count = (state->IRQ_count & 0x00ff) \| (data << 8);
4055	4120	else
4056		IRQ_count = (IRQ_count & 0xff00) \| data;
	4121	state->IRQ_count = (state->IRQ_count & 0xff00) \| data;
4057	4122	break;
4058	4123	case 0x5800:
4059		IRQ_enable = data & 0x10;
4060		IRQ_toggle = 0;
	4124	state->IRQ_enable = data & 0x10;
	4125	state->IRQ_toggle = 0;
4061	4126	break;
4062	4127	case 0x6800:
4063	4128	switch (data & 3)
r7955	r7956
4187	4252	there are 3 dots to every 1 CPU cycle, hence 114 is the number of cycles per scanline ) */
4188	4253	static void mapper69_irq( running_device *device, int scanline, int vblank, int blanked )
4189	4254	{
	4255	nes_state state = (nes_state )device->machine->driver_data;
	4256
4190	4257	/* TODO: change to reflect the actual number of cycles spent */
4191		if ((IRQ_enable & 0x80) && (IRQ_enable & 0x01))
	4258	if ((state->IRQ_enable & 0x80) && (state->IRQ_enable & 0x01))
4192	4259	{
4193		if (IRQ_count <= 114)
	4260	if (state->IRQ_count <= 114)
4194	4261	{
4195		IRQ_count = 0xffff;
	4262	state->IRQ_count = 0xffff;
4196	4263	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
4197	4264	}
4198	4265	else
4199		IRQ_count -= 114;
	4266	state->IRQ_count -= 114;
4200	4267	}
4201		else if (IRQ_enable & 0x01) // if enable bit is not set, only decrement the counter!
	4268	else if (state->IRQ_enable & 0x01) // if enable bit is not set, only decrement the counter!
4202	4269	{
4203		if (IRQ_count <= 114)
4204		IRQ_count = 0xffff;
	4270	if (state->IRQ_count <= 114)
	4271	state->IRQ_count = 0xffff;
4205	4272	else
4206		IRQ_count -= 114;
	4273	state->IRQ_count -= 114;
4207	4274	}
4208	4275	}
4209	4276
r7955	r7956
4215	4282	switch (offset & 0x6000)
4216	4283	{
4217	4284	case 0x0000:
4218		mmc_cmd1 = data & 0x0f;
	4285	state->mmc_cmd1 = data & 0x0f;
4219	4286	break;
4220	4287
4221	4288	case 0x2000:
4222		switch (mmc_cmd1)
	4289	switch (state->mmc_cmd1)
4223	4290	{
4224	4291	case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
4225		chr1_x(space->machine, mmc_cmd1, data, CHRROM);
	4292	chr1_x(space->machine, state->mmc_cmd1, data, CHRROM);
4226	4293	break;
4227	4294
4228	4295	/* TODO: deal properly with bankswitching/write-protecting the mid-mapper area */
r7955	r7956
4252	4319	}
4253	4320	break;
4254	4321	case 0x0d:
4255		IRQ_enable = data;
	4322	state->IRQ_enable = data;
4256	4323	break;
4257	4324	case 0x0e:
4258		IRQ_count = (IRQ_count & 0xff00) \| data;
	4325	state->IRQ_count = (state->IRQ_count & 0xff00) \| data;
4259	4326	break;
4260	4327	case 0x0f:
4261		IRQ_count = (IRQ_count & 0x00ff) \| (data << 8);
	4328	state->IRQ_count = (state->IRQ_count & 0x00ff) \| (data << 8);
4262	4329	break;
4263	4330	}
4264	4331	break;
r7955	r7956
4370	4437
4371	4438	static WRITE8_HANDLER( mapper73_w )
4372	4439	{
	4440	nes_state state = (nes_state )space->machine->driver_data;
	4441
4373	4442	switch (offset & 0x7000)
4374	4443	{
4375	4444	case 0x0000:
4376	4445	case 0x1000:
4377	4446	/* dunno which address controls these */
4378		IRQ_count_latch = data;
4379		IRQ_enable_latch = data;
	4447	state->IRQ_count_latch = data;
	4448	state->IRQ_enable_latch = data;
4380	4449	break;
4381	4450	case 0x2000:
4382		IRQ_enable = data;
	4451	state->IRQ_enable = data;
4383	4452	break;
4384	4453	case 0x3000:
4385		IRQ_count &= ~0x0f;
4386		IRQ_count \|= data & 0x0f;
	4454	state->IRQ_count &= ~0x0f;
	4455	state->IRQ_count \|= data & 0x0f;
4387	4456	break;
4388	4457	case 0x4000:
4389		IRQ_count &= ~0xf0;
4390		IRQ_count \|= (data & 0x0f) << 4;
	4458	state->IRQ_count &= ~0xf0;
	4459	state->IRQ_count \|= (data & 0x0f) << 4;
4391	4460	break;
4392	4461	case 0x7000:
4393	4462	prg16_89ab(space->machine, data);
r7955	r7956
4438	4507
4439	4508	static void mapper74_set_chr( running_machine *machine, int chr_base, int chr_mask )
4440	4509	{
4441		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	4510	nes_state state = (nes_state )machine->driver_data;
	4511	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
4442	4512	UINT8 chr_src[6];
4443	4513	int i;
4444	4514
4445	4515	for (i = 0; i < 6; i++)
4446		chr_src[i] = ((vrom_bank[i] == 8) \|\| (vrom_bank[i] == 9)) ? CHRRAM : CHRROM;
	4516	chr_src[i] = ((state->vrom_bank[i] == 8) \|\| (state->vrom_bank[i] == 9)) ? CHRRAM : CHRROM;
4447	4517
4448		chr1_x(machine, chr_page ^ 0, chr_base \| ((vrom_bank[0] & ~0x01) & chr_mask), chr_src[0]);
4449		chr1_x(machine, chr_page ^ 1, chr_base \| ((vrom_bank[0] \| 0x01) & chr_mask), chr_src[0]);
4450		chr1_x(machine, chr_page ^ 2, chr_base \| ((vrom_bank[1] & ~0x01) & chr_mask), chr_src[1]);
4451		chr1_x(machine, chr_page ^ 3, chr_base \| ((vrom_bank[1] \| 0x01) & chr_mask), chr_src[1]);
4452		chr1_x(machine, chr_page ^ 4, chr_base \| (vrom_bank[2] & chr_mask), chr_src[2]);
4453		chr1_x(machine, chr_page ^ 5, chr_base \| (vrom_bank[3] & chr_mask), chr_src[3]);
4454		chr1_x(machine, chr_page ^ 6, chr_base \| (vrom_bank[4] & chr_mask), chr_src[4]);
4455		chr1_x(machine, chr_page ^ 7, chr_base \| (vrom_bank[5] & chr_mask), chr_src[5]);
	4518	chr1_x(machine, chr_page ^ 0, chr_base \| ((state->vrom_bank[0] & ~0x01) & chr_mask), chr_src[0]);
	4519	chr1_x(machine, chr_page ^ 1, chr_base \| ((state->vrom_bank[0] \| 0x01) & chr_mask), chr_src[0]);
	4520	chr1_x(machine, chr_page ^ 2, chr_base \| ((state->vrom_bank[1] & ~0x01) & chr_mask), chr_src[1]);
	4521	chr1_x(machine, chr_page ^ 3, chr_base \| ((state->vrom_bank[1] \| 0x01) & chr_mask), chr_src[1]);
	4522	chr1_x(machine, chr_page ^ 4, chr_base \| (state->vrom_bank[2] & chr_mask), chr_src[2]);
	4523	chr1_x(machine, chr_page ^ 5, chr_base \| (state->vrom_bank[3] & chr_mask), chr_src[3]);
	4524	chr1_x(machine, chr_page ^ 6, chr_base \| (state->vrom_bank[4] & chr_mask), chr_src[4]);
	4525	chr1_x(machine, chr_page ^ 7, chr_base \| (state->vrom_bank[5] & chr_mask), chr_src[5]);
4456	4526	}
4457	4527
4458	4528	static WRITE8_HANDLER( mapper74_w )
4459	4529	{
	4530	nes_state state = (nes_state )space->machine->driver_data;
4460	4531	UINT8 MMC3_helper, cmd;
4461	4532	LOG_MMC(("mapper74_w, offset: %04x, data: %02x\n", offset, data));
4462	4533
4463	4534	switch (offset & 0x6001)
4464	4535	{
4465	4536	case 0x0000:
4466		MMC3_helper = mmc_cmd1 ^ data;
4467		mmc_cmd1 = data;
	4537	MMC3_helper = state->mmc_cmd1 ^ data;
	4538	state->mmc_cmd1 = data;
4468	4539
4469	4540	/* Has PRG Mode changed? */
4470	4541	if (MMC3_helper & 0x40)
4471		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	4542	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
4472	4543
4473	4544	/* Has CHR Mode changed? */
4474	4545	if (MMC3_helper & 0x80)
4475		mapper74_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	4546	mapper74_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
4476	4547	break;
4477	4548
4478	4549	case 0x0001:
4479		cmd = mmc_cmd1 & 0x07;
	4550	cmd = state->mmc_cmd1 & 0x07;
4480	4551	switch (cmd)
4481	4552	{
4482	4553	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
4483	4554	case 2: case 3: case 4: case 5:
4484		vrom_bank[cmd] = data;
4485		mapper74_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	4555	state->vrom_bank[cmd] = data;
	4556	mapper74_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
4486	4557	break;
4487	4558	case 6:
4488	4559	case 7:
4489		prg_bank[cmd - 6] = data;
4490		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	4560	state->prg_bank[cmd - 6] = data;
	4561	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
4491	4562	break;
4492	4563	}
4493	4564	break;
r7955	r7956
4518	4589
4519	4590	static WRITE8_HANDLER( mapper75_w )
4520	4591	{
	4592	nes_state state = (nes_state )space->machine->driver_data;
4521	4593	LOG_MMC(("mapper75_w, offset: %04x, data: %02x\n", offset, data));
4522	4594
4523	4595	switch (offset & 0x7000)
r7955	r7956
4527	4599	break;
4528	4600	case 0x1000:
4529	4601	set_nt_mirroring(space->machine, (data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4530		vrom_bank[0] = (vrom_bank[0] & 0x0f) \| ((data & 0x02) << 3);
4531		vrom_bank[1] = (vrom_bank[1] & 0x0f) \| ((data & 0x04) << 2);
4532		chr4_0(space->machine, vrom_bank[0], CHRROM);
4533		chr4_4(space->machine, vrom_bank[1], CHRROM);
	4602	state->vrom_bank[0] = (state->vrom_bank[0] & 0x0f) \| ((data & 0x02) << 3);
	4603	state->vrom_bank[1] = (state->vrom_bank[1] & 0x0f) \| ((data & 0x04) << 2);
	4604	chr4_0(space->machine, state->vrom_bank[0], CHRROM);
	4605	chr4_4(space->machine, state->vrom_bank[1], CHRROM);
4534	4606	break;
4535	4607	case 0x2000:
4536	4608	prg8_ab(space->machine, data);
r7955	r7956
4539	4611	prg8_cd(space->machine, data);
4540	4612	break;
4541	4613	case 0x6000:
4542		vrom_bank[0] = (vrom_bank[0] & 0x10) \| (data & 0x0f);
4543		chr4_0(space->machine, vrom_bank[0], CHRROM);
	4614	state->vrom_bank[0] = (state->vrom_bank[0] & 0x10) \| (data & 0x0f);
	4615	chr4_0(space->machine, state->vrom_bank[0], CHRROM);
4544	4616	break;
4545	4617	case 0x7000:
4546		vrom_bank[1] = (vrom_bank[1] & 0x10) \| (data & 0x0f);
4547		chr4_4(space->machine, vrom_bank[1], CHRROM);
	4618	state->vrom_bank[1] = (state->vrom_bank[1] & 0x10) \| (data & 0x0f);
	4619	chr4_4(space->machine, state->vrom_bank[1], CHRROM);
4548	4620	break;
4549	4621	}
4550	4622	}
r7955	r7956
4562	4634
4563	4635	static WRITE8_HANDLER( mapper76_w )
4564	4636	{
	4637	nes_state state = (nes_state )space->machine->driver_data;
4565	4638	LOG_MMC(("mapper76_w, offset: %04x, data: %02x\n", offset, data));
4566	4639
4567	4640	switch (offset & 0x7001)
4568	4641	{
4569	4642	case 0:
4570		mmc_cmd1 = data;
	4643	state->mmc_cmd1 = data;
4571	4644	break;
4572	4645	case 1:
4573	4646	{
4574		switch (mmc_cmd1 & 0x07)
	4647	switch (state->mmc_cmd1 & 0x07)
4575	4648	{
4576	4649	case 2: chr2_0(space->machine, data, CHRROM); break;
4577	4650	case 3: chr2_2(space->machine, data, CHRROM); break;
4578	4651	case 4: chr2_4(space->machine, data, CHRROM); break;
4579	4652	case 5: chr2_6(space->machine, data, CHRROM); break;
4580	4653	case 6:
4581		(mmc_cmd1 & 0x40) ? prg8_cd(space->machine, data) : prg8_89(space->machine, data);
	4654	(state->mmc_cmd1 & 0x40) ? prg8_cd(space->machine, data) : prg8_89(space->machine, data);
4582	4655	break;
4583	4656	case 7: prg8_ab(space->machine, data); break;
4584		default: logerror("mapper76 unsupported command: %02x, data: %02x\n", mmc_cmd1, data); break;
	4657	default: logerror("mapper76 unsupported command: %02x, data: %02x\n", state->mmc_cmd1, data); break;
4585	4658	}
4586	4659	}
4587	4660	case 0x2000:
r7955	r7956
4750	4823
4751	4824	static WRITE8_HANDLER( mapper82_m_w )
4752	4825	{
	4826	nes_state state = (nes_state )space->machine->driver_data;
4753	4827	LOG_MMC(("mapper82_m_w, offset: %04x, data: %02x\n", offset, data));
4754	4828
4755	4829	switch (offset)
4756	4830	{
4757	4831	case 0x1ef0:
4758		if (mmc_cmd1)
	4832	if (state->mmc_cmd1)
4759	4833	chr2_4(space->machine, data >> 1, CHRROM);
4760	4834	else
4761	4835	chr2_0(space->machine, data >> 1, CHRROM);
4762	4836	break;
4763	4837	case 0x1ef1:
4764		if (mmc_cmd1)
	4838	if (state->mmc_cmd1)
4765	4839	chr2_6(space->machine, data, CHRROM);
4766	4840	else
4767	4841	chr2_2(space->machine, data, CHRROM);
4768	4842	break;
4769	4843	case 0x1ef2:
4770		chr1_x(space->machine, 4 ^ mmc_cmd1, data, CHRROM);
	4844	chr1_x(space->machine, 4 ^ state->mmc_cmd1, data, CHRROM);
4771	4845	break;
4772	4846	case 0x1ef3:
4773		chr1_x(space->machine, 5 ^ mmc_cmd1, data, CHRROM);
	4847	chr1_x(space->machine, 5 ^ state->mmc_cmd1, data, CHRROM);
4774	4848	break;
4775	4849	case 0x1ef4:
4776		chr1_x(space->machine, 6 ^ mmc_cmd1, data, CHRROM);
	4850	chr1_x(space->machine, 6 ^ state->mmc_cmd1, data, CHRROM);
4777	4851	break;
4778	4852	case 0x1ef5:
4779		chr1_x(space->machine, 7 ^ mmc_cmd1, data, CHRROM);
	4853	chr1_x(space->machine, 7 ^ state->mmc_cmd1, data, CHRROM);
4780	4854	break;
4781	4855	case 0x1ef6:
4782	4856	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
4783		mmc_cmd1 = ((data & 0x02) << 1);
	4857	state->mmc_cmd1 = ((data & 0x02) << 1);
4784	4858	break;
4785	4859
4786	4860	case 0x1efa:
r7955	r7956
4840	4914
4841	4915	static WRITE8_HANDLER( mapper83_w )
4842	4916	{
	4917	nes_state state = (nes_state )space->machine->driver_data;
4843	4918	LOG_MMC(("mapper83_w, offset: %04x, data: %02x\n", offset, data));
4844	4919
4845	4920	switch (offset)
r7955	r7956
4870	4945	}
4871	4946	break;
4872	4947	case 0x0200:
4873		IRQ_count = (IRQ_count & 0xff00) \| data;
	4948	state->IRQ_count = (state->IRQ_count & 0xff00) \| data;
4874	4949	break;
4875	4950	case 0x0201:
4876		IRQ_enable = 1;
4877		IRQ_count = (data << 8) \| (IRQ_count & 0xff);
	4951	state->IRQ_enable = 1;
	4952	state->IRQ_count = (data << 8) \| (state->IRQ_count & 0xff);
4878	4953	break;
4879	4954	case 0x0300:
4880	4955	prg8_89(space->machine, data);
r7955	r7956
4927	5002
4928	5003	static WRITE8_HANDLER( konami_vrc7_w )
4929	5004	{
	5005	nes_state state = (nes_state )space->machine->driver_data;
4930	5006	UINT8 bank;
4931	5007	LOG_MMC(("konami_vrc7_w, offset: %04x, data: %02x\n", offset, data));
4932	5008
r7955	r7956
4964	5040	case 0x5010:
4965	5041	case 0x5018:
4966	5042	bank = ((offset & 0x7000) - 0x2000) / 0x0800 + ((offset & 0x0018) ? 1 : 0);
4967		chr1_x(space->machine, bank, data, mmc_chr_source);
	5043	chr1_x(space->machine, bank, data, state->mmc_chr_source);
4968	5044	break;
4969	5045
4970	5046	case 0x6000:
r7955	r7956
4977	5053	}
4978	5054	break;
4979	5055	case 0x6008: case 0x6010: case 0x6018:
4980		IRQ_count_latch = data;
	5056	state->IRQ_count_latch = data;
4981	5057	break;
4982	5058	case 0x7000:
4983		IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
4984		IRQ_enable = data & 0x02;
4985		IRQ_enable_latch = data & 0x01;
	5059	state->IRQ_mode = data & 0x04; // currently not implemented: 0 = prescaler mode / 1 = CPU mode
	5060	state->IRQ_enable = data & 0x02;
	5061	state->IRQ_enable_latch = data & 0x01;
4986	5062	if (data & 0x02)
4987		IRQ_count = IRQ_count_latch;
	5063	state->IRQ_count = state->IRQ_count_latch;
4988	5064	break;
4989	5065	case 0x7008: case 0x7010: case 0x7018:
4990		IRQ_enable = IRQ_enable_latch;
	5066	state->IRQ_enable = state->IRQ_enable_latch;
4991	5067	break;
4992	5068
4993	5069	default:
r7955	r7956
5051	5127
5052	5128	static WRITE8_HANDLER( mapper88_w )
5053	5129	{
	5130	nes_state state = (nes_state )space->machine->driver_data;
5054	5131	LOG_MMC(("mapper88_w, offset: %04x, data: %02x\n", offset, data));
5055	5132
5056	5133	switch (offset & 1)
5057	5134	{
5058	5135	case 0:
5059		mmc_cmd1 = data & 7;
	5136	state->mmc_cmd1 = data & 7;
5060	5137	break;
5061	5138	case 1:
5062		switch (mmc_cmd1)
	5139	switch (state->mmc_cmd1)
5063	5140	{
5064	5141	case 0: chr2_0(space->machine, data >> 1, CHRROM); break;
5065	5142	case 1: chr2_2(space->machine, data >> 1, CHRROM); break;
r7955	r7956
5125	5202
5126	5203	static WRITE8_HANDLER( mapper91_m_w )
5127	5204	{
	5205	nes_state state = (nes_state )space->machine->driver_data;
5128	5206	LOG_MMC(("mapper91_m_w, offset: %04x, data: %02x\n", offset, data));
5129	5207
5130	5208	switch (offset & 0x1000)
r7955	r7956
5143	5221	{
5144	5222	case 0x00: prg8_89(space->machine, data); break;
5145	5223	case 0x01: prg8_ab(space->machine, data); break;
5146		case 0x02: IRQ_enable = 0; IRQ_count = 0; break;
5147		case 0x03: IRQ_enable = 1; IRQ_count = 7; break;
	5224	case 0x02: state->IRQ_enable = 0; state->IRQ_count = 0; break;
	5225	case 0x03: state->IRQ_enable = 1; state->IRQ_count = 7; break;
5148	5226	}
5149	5227	break;
5150	5228	default:
r7955	r7956
5232	5310
5233	5311	static WRITE8_HANDLER( mapper95_w )
5234	5312	{
	5313	nes_state state = (nes_state )space->machine->driver_data;
5235	5314	LOG_MMC(("mapper95_w, offset: %04x, data: %02x\n", offset, data));
5236	5315
5237	5316	switch (offset & 1)
5238	5317	{
5239	5318	case 0:
5240	5319	{
5241		mmc_cmd1 = data;
	5320	state->mmc_cmd1 = data;
5242	5321	break;
5243	5322	}
5244	5323	case 1:
5245	5324	{
5246		switch (mmc_cmd1 & 0x07)
	5325	switch (state->mmc_cmd1 & 0x07)
5247	5326	{
5248	5327	case 0:
5249	5328	case 1:
5250		chr2_x(space->machine, mmc_cmd1 ? 2 : 0, (data >> 1) & 0x1f, CHRROM);
	5329	chr2_x(space->machine, state->mmc_cmd1 ? 2 : 0, (data >> 1) & 0x1f, CHRROM);
5251	5330	break;
5252	5331	case 2:
5253	5332	case 3:
5254	5333	case 4:
5255	5334	case 5:
5256		chr1_x(space->machine, 2 + mmc_cmd1, data & 0x1f, CHRROM);
5257		mapper95_reg[mmc_cmd1 - 2] = data & 0x20;
5258		if (!(mmc_cmd1 & 0x80))
	5335	chr1_x(space->machine, 2 + state->mmc_cmd1, data & 0x1f, CHRROM);
	5336	mapper95_reg[state->mmc_cmd1 - 2] = data & 0x20;
	5337	if (!(state->mmc_cmd1 & 0x80))
5259	5338	{
5260	5339	set_nt_page(space->machine, 0, CIRAM, mapper95_reg[0] ? 1 : 0, 1);
5261	5340	set_nt_page(space->machine, 1, CIRAM, mapper95_reg[1] ? 1 : 0, 1);
r7955	r7956
5411	5490
5412	5491	static WRITE8_HANDLER( mapper104_w )
5413	5492	{
	5493	nes_state state = (nes_state )space->machine->driver_data;
5414	5494	LOG_MMC(("mapper104_w, offset: %04x, data: %02x\n", offset, data));
5415	5495
5416	5496	if (offset < 0x4000)
5417	5497	{
5418	5498	if (data & 0x08)
5419	5499	{
5420		prg_bank[0] = ((data & 0x07) << 4) \| (prg_bank[0] & 0x0f);
5421		prg16_89ab(space->machine, prg_bank[0]);
	5500	state->prg_bank[0] = ((data & 0x07) << 4) \| (state->prg_bank[0] & 0x0f);
	5501	prg16_89ab(space->machine, state->prg_bank[0]);
5422	5502	prg16_cdef(space->machine, ((data & 0x07) << 4) \| 0x0f);
5423	5503	}
5424	5504
5425	5505	}
5426	5506	else
5427	5507	{
5428		prg_bank[0] = (prg_bank[0] & 0x70) \| (data & 0x0f);
5429		prg16_89ab(space->machine, prg_bank[0]);
	5508	state->prg_bank[0] = (state->prg_bank[0] & 0x70) \| (data & 0x0f);
	5509	prg16_89ab(space->machine, state->prg_bank[0]);
5430	5510	}
5431	5511	}
5432	5512
r7955	r7956
5454	5534
5455	5535	static void mapper106_irq( running_device *device, int scanline, int vblank, int blanked )
5456	5536	{
5457		if (IRQ_enable)
	5537	nes_state state = (nes_state )device->machine->driver_data;
	5538
	5539	if (state->IRQ_enable)
5458	5540	{
5459		if ((0xffff - IRQ_count) < 114)
	5541	if ((0xffff - state->IRQ_count) < 114)
5460	5542	{
5461	5543	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
5462		IRQ_enable = 0;
	5544	state->IRQ_enable = 0;
5463	5545	}
5464	5546
5465		IRQ_count = (IRQ_count + 114) & 0xffff;
	5547	state->IRQ_count = (state->IRQ_count + 114) & 0xffff;
5466	5548	}
5467	5549	}
5468	5550
5469	5551	static WRITE8_HANDLER( mapper106_w )
5470	5552	{
	5553	nes_state state = (nes_state )space->machine->driver_data;
5471	5554	LOG_MMC(("mapper106_w, offset: %04x, data: %02x\n", offset, data));
5472	5555	switch (offset & 0x0f)
5473	5556	{
r7955	r7956
5499	5582	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5500	5583	break;
5501	5584	case 0x0d:
5502		IRQ_count = 0;
5503		IRQ_enable = 0;
	5585	state->IRQ_count = 0;
	5586	state->IRQ_enable = 0;
5504	5587	break;
5505	5588	case 0x0e:
5506		IRQ_count = (IRQ_count & 0xff00) \| data;
	5589	state->IRQ_count = (state->IRQ_count & 0xff00) \| data;
5507	5590	break;
5508	5591	case 0x0f:
5509		IRQ_count = (IRQ_count & 0x00ff) \| (data << 8);
5510		IRQ_enable = 1;
	5592	state->IRQ_count = (state->IRQ_count & 0x00ff) \| (data << 8);
	5593	state->IRQ_enable = 1;
5511	5594	break;
5512	5595	}
5513	5596	}
r7955	r7956
5597	5680
5598	5681	static WRITE8_HANDLER( mapper112_w )
5599	5682	{
	5683	nes_state state = (nes_state )space->machine->driver_data;
5600	5684	LOG_MMC(("mapper112_w, offset: %04x, data: %02x\n", offset, data));
5601	5685
5602	5686	switch (offset)
5603	5687	{
5604	5688	case 0x0000:
5605		mmc_cmd1 = data & 0x07;
	5689	state->mmc_cmd1 = data & 0x07;
5606	5690	break;
5607	5691	case 0x2000:
5608		switch (mmc_cmd1)
	5692	switch (state->mmc_cmd1)
5609	5693	{
5610	5694	case 0:
5611	5695	prg8_89(space->machine, data);
r7955	r7956
5684	5768
5685	5769	static WRITE8_HANDLER( mapper114_m_w )
5686	5770	{
	5771	nes_state state = (nes_state )space->machine->driver_data;
5687	5772	LOG_MMC(("mapper114_m_w, offset: %04x, data: %02x\n", offset, data));
5688	5773
5689	5774	map114_reg = data;
r7955	r7956
5694	5779	prg16_cdef(space->machine, data & 0x1f);
5695	5780	}
5696	5781	else
5697		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	5782	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
5698	5783
5699	5784	}
5700	5785
r7955	r7956
5764	5849
5765	5850	static WRITE8_HANDLER( mapper115_m_w )
5766	5851	{
	5852	nes_state state = (nes_state )space->machine->driver_data;
5767	5853	LOG_MMC(("mapper115_m_w, offset: %04x, data: %02x\n", offset, data));
5768	5854
5769	5855	switch (offset & 0x01)
5770	5856	{
5771	5857	case 0x00:
5772	5858	mapper115_reg[0] = data;
5773		mapper115_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	5859	mapper115_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
5774	5860	break;
5775	5861	case 0x01:
5776		mmc_chr_base = (data & 0x01) ? 0x100 : 0x000;
5777		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	5862	state->mmc_chr_base = (data & 0x01) ? 0x100 : 0x000;
	5863	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
5778	5864	break;
5779	5865	}
5780	5866	}
5781	5867
5782	5868	static WRITE8_HANDLER( mapper115_w )
5783	5869	{
	5870	nes_state state = (nes_state )space->machine->driver_data;
5784	5871	UINT8 map115_helper, cmd;
5785	5872	LOG_MMC(("mapper115_w, offset: %04x, data: %02x\n", offset, data));
5786	5873
5787	5874	switch (offset & 0x6001)
5788	5875	{
5789	5876	case 0x0000:
5790		map115_helper = mmc_cmd1 ^ data;
5791		mmc_cmd1 = data;
	5877	map115_helper = state->mmc_cmd1 ^ data;
	5878	state->mmc_cmd1 = data;
5792	5879
5793	5880	/* Has PRG Mode changed? */
5794	5881	if (map115_helper & 0x40)
5795		mapper115_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	5882	mapper115_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
5796	5883
5797	5884	/* Has CHR Mode changed? */
5798	5885	if (map115_helper & 0x80)
5799		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	5886	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
5800	5887	break;
5801	5888
5802	5889	case 0x0001:
5803		cmd = mmc_cmd1 & 0x07;
	5890	cmd = state->mmc_cmd1 & 0x07;
5804	5891	switch (cmd)
5805	5892	{
5806	5893	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
5807	5894	case 2: case 3: case 4: case 5:
5808		vrom_bank[cmd] = data;
5809		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	5895	state->vrom_bank[cmd] = data;
	5896	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
5810	5897	break;
5811	5898	case 6:
5812	5899	case 7:
5813		prg_bank[cmd - 6] = data;
5814		mapper115_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	5900	state->prg_bank[cmd - 6] = data;
	5901	mapper115_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
5815	5902	break;
5816	5903	}
5817	5904	break;
r7955	r7956
5846	5933
5847	5934	static void mapper117_irq( running_device *device, int scanline, int vblank, int blanked )
5848	5935	{
	5936	nes_state state = (nes_state )device->machine->driver_data;
5849	5937	// if (scanline < PPU_BOTTOM_VISIBLE_SCANLINE)
5850	5938	{
5851		if (IRQ_enable && IRQ_count)
	5939	if (state->IRQ_enable && state->IRQ_count)
5852	5940	{
5853		IRQ_count--;
5854		if (!IRQ_count)
	5941	state->IRQ_count--;
	5942	if (!state->IRQ_count)
5855	5943	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
5856	5944	}
5857	5945	}
r7955	r7956
5859	5947
5860	5948	static WRITE8_HANDLER( mapper117_w )
5861	5949	{
	5950	nes_state state = (nes_state )space->machine->driver_data;
5862	5951	LOG_MMC(("mapper117_w, offset: %04x, data: %02x\n", offset, data));
5863	5952
5864	5953	switch (offset)
r7955	r7956
5891	5980	break;
5892	5981
5893	5982	case 0x4001:
5894		IRQ_count_latch = data;
	5983	state->IRQ_count_latch = data;
5895	5984	break;
5896	5985	case 0x4002:
5897	5986	// IRQ cleared
5898	5987	break;
5899	5988	case 0x4003:
5900		IRQ_count = IRQ_count_latch;
	5989	state->IRQ_count = state->IRQ_count_latch;
5901	5990	break;
5902	5991	case 0x6000:
5903		IRQ_enable = data & 0x01;
	5992	state->IRQ_enable = data & 0x01;
5904	5993	break;
5905	5994	}
5906	5995	}
r7955	r7956
5919	6008
5920	6009	static void mapper118_set_mirror( running_machine *machine )
5921	6010	{
5922		if (mmc_cmd1 & 0x80)
	6011	nes_state state = (nes_state )machine->driver_data;
	6012	if (state->mmc_cmd1 & 0x80)
5923	6013	{
5924		set_nt_page(machine, 0, CIRAM, (vrom_bank[2] & 0x80) >> 7, 1);
5925		set_nt_page(machine, 1, CIRAM, (vrom_bank[3] & 0x80) >> 7, 1);
5926		set_nt_page(machine, 2, CIRAM, (vrom_bank[4] & 0x80) >> 7, 1);
5927		set_nt_page(machine, 3, CIRAM, (vrom_bank[5] & 0x80) >> 7, 1);
	6014	set_nt_page(machine, 0, CIRAM, (state->vrom_bank[2] & 0x80) >> 7, 1);
	6015	set_nt_page(machine, 1, CIRAM, (state->vrom_bank[3] & 0x80) >> 7, 1);
	6016	set_nt_page(machine, 2, CIRAM, (state->vrom_bank[4] & 0x80) >> 7, 1);
	6017	set_nt_page(machine, 3, CIRAM, (state->vrom_bank[5] & 0x80) >> 7, 1);
5928	6018	}
5929	6019	else
5930	6020	{
5931		set_nt_page(machine, 0, CIRAM, (vrom_bank[0] & 0x80) >> 7, 1);
5932		set_nt_page(machine, 1, CIRAM, (vrom_bank[0] & 0x80) >> 7, 1);
5933		set_nt_page(machine, 2, CIRAM, (vrom_bank[1] & 0x80) >> 7, 1);
5934		set_nt_page(machine, 3, CIRAM, (vrom_bank[1] & 0x80) >> 7, 1);
	6021	set_nt_page(machine, 0, CIRAM, (state->vrom_bank[0] & 0x80) >> 7, 1);
	6022	set_nt_page(machine, 1, CIRAM, (state->vrom_bank[0] & 0x80) >> 7, 1);
	6023	set_nt_page(machine, 2, CIRAM, (state->vrom_bank[1] & 0x80) >> 7, 1);
	6024	set_nt_page(machine, 3, CIRAM, (state->vrom_bank[1] & 0x80) >> 7, 1);
5935	6025	}
5936	6026	}
5937	6027
5938	6028	static WRITE8_HANDLER( mapper118_w )
5939	6029	{
	6030	nes_state state = (nes_state )space->machine->driver_data;
5940	6031	UINT8 MMC3_helper, cmd;
5941	6032	LOG_MMC(("mapper118_w, offset: %04x, data: %02x\n", offset, data));
5942	6033
5943	6034	switch (offset & 0x6001)
5944	6035	{
5945	6036	case 0x0000:
5946		MMC3_helper = mmc_cmd1 ^ data;
5947		mmc_cmd1 = data;
	6037	MMC3_helper = state->mmc_cmd1 ^ data;
	6038	state->mmc_cmd1 = data;
5948	6039
5949	6040	/* Has PRG Mode changed? */
5950	6041	if (MMC3_helper & 0x40)
5951		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	6042	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
5952	6043
5953	6044	/* Has CHR Mode changed? */
5954	6045	if (MMC3_helper & 0x80)
5955	6046	{
5956	6047	mapper118_set_mirror(space->machine);
5957		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	6048	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
5958	6049	}
5959	6050	break;
5960	6051
5961	6052	case 0x0001:
5962		cmd = mmc_cmd1 & 0x07;
	6053	cmd = state->mmc_cmd1 & 0x07;
5963	6054	switch (cmd)
5964	6055	{
5965	6056	case 0: case 1:
5966	6057	case 2: case 3: case 4: case 5:
5967		vrom_bank[cmd] = data;
	6058	state->vrom_bank[cmd] = data;
5968	6059	mapper118_set_mirror(space->machine);
5969		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	6060	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
5970	6061	break;
5971	6062	case 6:
5972	6063	case 7:
5973		prg_bank[cmd - 6] = data;
5974		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	6064	state->prg_bank[cmd - 6] = data;
	6065	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
5975	6066	break;
5976	6067	}
5977	6068	break;
r7955	r7956
5998	6089
5999	6090	static void mapper119_set_chr( running_machine *machine )
6000	6091	{
6001		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	6092	nes_state state = (nes_state )machine->driver_data;
	6093	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
6002	6094	UINT8 chr_src[6], chr_mask[6];
6003	6095	int i;
6004	6096
6005	6097	for (i = 0; i < 6; i++)
6006	6098	{
6007		chr_src[i] = (vrom_bank[i] & 0x40) ? CHRRAM : CHRROM;
6008		chr_mask[i] = (vrom_bank[i] & 0x40) ? 0x07 : 0x3f;
	6099	chr_src[i] = (state->vrom_bank[i] & 0x40) ? CHRRAM : CHRROM;
	6100	chr_mask[i] = (state->vrom_bank[i] & 0x40) ? 0x07 : 0x3f;
6009	6101	}
6010	6102
6011		chr1_x(machine, chr_page ^ 0, ((vrom_bank[0] & ~0x01) & chr_mask[0]), chr_src[0]);
6012		chr1_x(machine, chr_page ^ 1, ((vrom_bank[0] \| 0x01) & chr_mask[0]), chr_src[0]);
6013		chr1_x(machine, chr_page ^ 2, ((vrom_bank[1] & ~0x01) & chr_mask[1]), chr_src[1]);
6014		chr1_x(machine, chr_page ^ 3, ((vrom_bank[1] \| 0x01) & chr_mask[1]), chr_src[1]);
6015		chr1_x(machine, chr_page ^ 4, (vrom_bank[2] & chr_mask[2]), chr_src[2]);
6016		chr1_x(machine, chr_page ^ 5, (vrom_bank[3] & chr_mask[3]), chr_src[3]);
6017		chr1_x(machine, chr_page ^ 6, (vrom_bank[4] & chr_mask[4]), chr_src[4]);
6018		chr1_x(machine, chr_page ^ 7, (vrom_bank[5] & chr_mask[5]), chr_src[5]);
	6103	chr1_x(machine, chr_page ^ 0, ((state->vrom_bank[0] & ~0x01) & chr_mask[0]), chr_src[0]);
	6104	chr1_x(machine, chr_page ^ 1, ((state->vrom_bank[0] \| 0x01) & chr_mask[0]), chr_src[0]);
	6105	chr1_x(machine, chr_page ^ 2, ((state->vrom_bank[1] & ~0x01) & chr_mask[1]), chr_src[1]);
	6106	chr1_x(machine, chr_page ^ 3, ((state->vrom_bank[1] \| 0x01) & chr_mask[1]), chr_src[1]);
	6107	chr1_x(machine, chr_page ^ 4, (state->vrom_bank[2] & chr_mask[2]), chr_src[2]);
	6108	chr1_x(machine, chr_page ^ 5, (state->vrom_bank[3] & chr_mask[3]), chr_src[3]);
	6109	chr1_x(machine, chr_page ^ 6, (state->vrom_bank[4] & chr_mask[4]), chr_src[4]);
	6110	chr1_x(machine, chr_page ^ 7, (state->vrom_bank[5] & chr_mask[5]), chr_src[5]);
6019	6111	}
6020	6112
6021	6113	static WRITE8_HANDLER( mapper119_w )
6022	6114	{
	6115	nes_state state = (nes_state )space->machine->driver_data;
6023	6116	UINT8 MMC3_helper, cmd;
6024	6117	LOG_MMC(("mapper119_w, offset: %04x, data: %02x\n", offset, data));
6025	6118
6026	6119	switch (offset & 0x6001)
6027	6120	{
6028	6121	case 0x0000:
6029		MMC3_helper = mmc_cmd1 ^ data;
6030		mmc_cmd1 = data;
	6122	MMC3_helper = state->mmc_cmd1 ^ data;
	6123	state->mmc_cmd1 = data;
6031	6124
6032	6125	/* Has PRG Mode changed? */
6033	6126	if (MMC3_helper & 0x40)
6034		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	6127	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
6035	6128
6036	6129	/* Has CHR Mode changed? */
6037	6130	if (MMC3_helper & 0x80)
6038	6131	mapper119_set_chr(space->machine);
6039	6132	break;
6040	6133	case 0x0001: /* $8001 */
6041		cmd = mmc_cmd1 & 0x07;
	6134	cmd = state->mmc_cmd1 & 0x07;
6042	6135	switch (cmd)
6043	6136	{
6044	6137	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
6045	6138	case 2: case 3: case 4: case 5:
6046		vrom_bank[cmd] = data;
	6139	state->vrom_bank[cmd] = data;
6047	6140	mapper119_set_chr(space->machine);
6048	6141	break;
6049	6142	case 6:
6050	6143	case 7:
6051		prg_bank[cmd - 6] = data;
6052		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	6144	state->prg_bank[cmd - 6] = data;
	6145	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
6053	6146	break;
6054	6147	}
6055	6148	break;
r7955	r7956
6120	6213
6121	6214	static void mapper121_set_prg( running_machine *machine, int prg_base, int prg_mask )
6122	6215	{
6123		UINT8 prg_flip = (mmc_cmd1 & 0x40) ? 2 : 0;
	6216	nes_state state = (nes_state )machine->driver_data;
	6217	UINT8 prg_flip = (state->mmc_cmd1 & 0x40) ? 2 : 0;
6124	6218	UINT8 new_bank2, new_bank3;
6125	6219
6126		new_bank2 = mapper121_reg[0] ? mapper121_reg[0] : prg_bank[2 ^ prg_flip];
6127		new_bank3 = mapper121_reg[1] ? mapper121_reg[1] : prg_bank[3];
	6220	new_bank2 = mapper121_reg[0] ? mapper121_reg[0] : state->prg_bank[2 ^ prg_flip];
	6221	new_bank3 = mapper121_reg[1] ? mapper121_reg[1] : state->prg_bank[3];
6128	6222
6129		prg8_89(machine, prg_base \| (prg_bank[0 ^ prg_flip] & prg_mask));
6130		prg8_ab(machine, prg_base \| (prg_bank[1] & prg_mask));
	6223	prg8_89(machine, prg_base \| (state->prg_bank[0 ^ prg_flip] & prg_mask));
	6224	prg8_ab(machine, prg_base \| (state->prg_bank[1] & prg_mask));
6131	6225	prg8_cd(machine, prg_base \| (new_bank2 & prg_mask));
6132	6226	prg8_ef(machine, prg_base \| (new_bank3 & prg_mask));
6133	6227	}
6134	6228
6135	6229	static WRITE8_HANDLER( mapper121_w )
6136	6230	{
	6231	nes_state state = (nes_state )space->machine->driver_data;
6137	6232	UINT8 MMC3_helper, cmd;
6138	6233	LOG_MMC(("mapper121_w, offset: %04x, data: %02x\n", offset, data));
6139	6234
r7955	r7956
6174	6269	switch (offset & 0x6001)
6175	6270	{
6176	6271	case 0x0000:
6177		MMC3_helper = mmc_cmd1 ^ data;
6178		mmc_cmd1 = data;
	6272	MMC3_helper = state->mmc_cmd1 ^ data;
	6273	state->mmc_cmd1 = data;
6179	6274
6180	6275	/* Has PRG Mode changed? */
6181	6276	if (MMC3_helper & 0x40)
6182		mapper121_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	6277	mapper121_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
6183	6278
6184	6279	/* Has CHR Mode changed? */
6185	6280	if (MMC3_helper & 0x80)
6186		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	6281	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
6187	6282	break;
6188	6283
6189	6284	case 0x0001:
6190		cmd = mmc_cmd1 & 0x07;
	6285	cmd = state->mmc_cmd1 & 0x07;
6191	6286	switch (cmd)
6192	6287	{
6193	6288	case 0: case 1:
6194	6289	case 2: case 3: case 4: case 5:
6195		vrom_bank[cmd] = data;
6196		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	6290	state->vrom_bank[cmd] = data;
	6291	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
6197	6292	break;
6198	6293	case 6:
6199	6294	case 7:
6200		prg_bank[cmd - 6] = data;
6201		mapper121_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	6295	state->prg_bank[cmd - 6] = data;
	6296	mapper121_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
6202	6297	break;
6203	6298	}
6204	6299	break;
r7955	r7956
6208	6303	break;
6209	6304	}
6210	6305	}
6211		mapper121_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	6306	mapper121_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
6212	6307	}
6213	6308
6214	6309	/*************************************************************
r7955	r7956
6403	6498
6404	6499	static WRITE8_HANDLER( mapper134_m_w )
6405	6500	{
	6501	nes_state state = (nes_state )space->machine->driver_data;
6406	6502	LOG_MMC(("mapper134_m_w, offset: %04x, data: %02x\n", offset, data));
6407	6503
6408	6504	if (offset == 0x01)
6409	6505	{
6410		mmc_prg_base = (data & 0x02) << 4;
6411		mmc_prg_mask = 0x1f;
6412		mmc_chr_base = (data & 0x20) << 3;
6413		mmc_chr_mask = 0xff;
6414		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
6415		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	6506	state->mmc_prg_base = (data & 0x02) << 4;
	6507	state->mmc_prg_mask = 0x1f;
	6508	state->mmc_chr_base = (data & 0x20) << 3;
	6509	state->mmc_chr_mask = 0xff;
	6510	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
	6511	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
6416	6512	}
6417	6513	}
6418	6514
r7955	r7956
6440	6536
6441	6537	static WRITE8_HANDLER( mapper136_l_w )
6442	6538	{
	6539	nes_state state = (nes_state )space->machine->driver_data;
6443	6540	LOG_MMC(("mapper136_l_w, offset: %04x, data: %02x\n", offset, data));
6444	6541
6445	6542	if ((offset & 0x103) == 0x002)
6446	6543	{
6447		mmc_cmd1 = (data & 0x30) \| ((data + 3) & 0x0f);
6448		chr8(space->machine, mmc_cmd1, CHRROM);
	6544	state->mmc_cmd1 = (data & 0x30) \| ((data + 3) & 0x0f);
	6545	chr8(space->machine, state->mmc_cmd1, CHRROM);
6449	6546	}
6450	6547	}
6451	6548
6452	6549	static READ8_HANDLER( mapper136_l_r )
6453	6550	{
	6551	nes_state state = (nes_state )space->machine->driver_data;
6454	6552	LOG_MMC(("mapper136_l_r, offset: %04x\n", offset));
6455	6553
6456	6554	if ((offset & 0x103) == 0x000)
6457		return mmc_cmd1 \| 0x40;
	6555	return state->mmc_cmd1 \| 0x40;
6458	6556	else
6459	6557	return 0x00;
6460	6558	}
r7955	r7956
6495	6593
6496	6594	static WRITE8_HANDLER( mapper137_l_w )
6497	6595	{
	6596	nes_state state = (nes_state )space->machine->driver_data;
6498	6597	LOG_MMC(("mapper137_l_w, offset: %04x, data: %02x\n", offset, data));
6499	6598
6500	6599	/* write happens only if we are at 0x4100 + k * 0x200, but 0x4100 is offset = 0 */
6501	6600	if (!(offset & 0x100))
6502	6601	{
6503	6602	if (!(offset & 0x01))
6504		mmc_cmd1 = data & 0x07;
	6603	state->mmc_cmd1 = data & 0x07;
6505	6604	else
6506	6605	{
6507		sachen_reg[mmc_cmd1] = data;
	6606	sachen_reg[state->mmc_cmd1] = data;
6508	6607
6509		switch (mmc_cmd1)
	6608	switch (state->mmc_cmd1)
6510	6609	{
6511	6610	case 0x05:
6512	6611	prg32(space->machine, data);
r7955	r7956
6515	6614	sachen_set_mirror(space->machine, BIT(data, 0) ? 0 : (data >> 1) & 0x03);
6516	6615	break;
6517	6616	default:
6518		if (mmc_chr_source == CHRROM)
	6617	if (state->mmc_chr_source == CHRROM)
6519	6618	{
6520	6619	chr1_0(space->machine, (sachen_reg[0] & 0x07), CHRROM);
6521	6620	chr1_1(space->machine, (sachen_reg[1] & 0x07) \| (sachen_reg[4] << 4 & 0x10), CHRROM);
r7955	r7956
6548	6647
6549	6648	static WRITE8_HANDLER( mapper138_l_w )
6550	6649	{
	6650	nes_state state = (nes_state )space->machine->driver_data;
6551	6651	UINT8 bank_helper1 = 0, bank_helper2 = 0;
6552	6652	LOG_MMC(("mapper138_l_w, offset: %04x, data: %02x\n", offset, data));
6553	6653
r7955	r7956
6555	6655	if (!(offset & 0x100))
6556	6656	{
6557	6657	if (!(offset & 0x01))
6558		mmc_cmd1 = data & 0x07;
	6658	state->mmc_cmd1 = data & 0x07;
6559	6659	else
6560	6660	{
6561		sachen_reg[mmc_cmd1] = data;
	6661	sachen_reg[state->mmc_cmd1] = data;
6562	6662
6563		switch (mmc_cmd1)
	6663	switch (state->mmc_cmd1)
6564	6664	{
6565	6665	case 0x05:
6566	6666	prg32(space->machine, data);
r7955	r7956
6569	6669	sachen_set_mirror(space->machine, BIT(data, 0) ? 0 : (data >> 1) & 0x03);
6570	6670	break;
6571	6671	default:
6572		if (mmc_chr_source == CHRROM)
	6672	if (state->mmc_chr_source == CHRROM)
6573	6673	{
6574	6674	bank_helper1 = sachen_reg[7] & 0x01;
6575	6675	bank_helper2 = (sachen_reg[4] & 0x07) << 3;
r7955	r7956
6604	6704
6605	6705	static WRITE8_HANDLER( mapper139_l_w )
6606	6706	{
	6707	nes_state state = (nes_state )space->machine->driver_data;
6607	6708	UINT8 bank_helper1 = 0, bank_helper2 = 0;
6608	6709	LOG_MMC(("mapper139_l_w, offset: %04x, data: %02x\n", offset, data));
6609	6710
r7955	r7956
6611	6712	if (!(offset & 0x100))
6612	6713	{
6613	6714	if (!(offset & 0x01))
6614		mmc_cmd1 = data & 0x07;
	6715	state->mmc_cmd1 = data & 0x07;
6615	6716	else
6616	6717	{
6617		sachen_reg[mmc_cmd1] = data;
	6718	sachen_reg[state->mmc_cmd1] = data;
6618	6719
6619		switch (mmc_cmd1)
	6720	switch (state->mmc_cmd1)
6620	6721	{
6621	6722	case 0x05:
6622	6723	prg32(space->machine, data);
r7955	r7956
6625	6726	sachen_set_mirror(space->machine, BIT(data, 0) ? 0 : (data >> 1) & 0x03);
6626	6727	break;
6627	6728	default:
6628		if (mmc_chr_source == CHRROM)
	6729	if (state->mmc_chr_source == CHRROM)
6629	6730	{
6630	6731	bank_helper1 = sachen_reg[7] & 0x01;
6631	6732	bank_helper2 = (sachen_reg[4] & 0x07) << 3;
r7955	r7956
6680	6781
6681	6782	static WRITE8_HANDLER( mapper141_l_w )
6682	6783	{
	6784	nes_state state = (nes_state )space->machine->driver_data;
6683	6785	UINT8 bank_helper1 = 0, bank_helper2 = 0;
6684	6786	LOG_MMC(("mapper141_l_w, offset: %04x, data: %02x\n", offset, data));
6685	6787
r7955	r7956
6687	6789	if (!(offset & 0x100))
6688	6790	{
6689	6791	if (!(offset & 0x01))
6690		mmc_cmd1 = data & 0x07;
	6792	state->mmc_cmd1 = data & 0x07;
6691	6793	else
6692	6794	{
6693		sachen_reg[mmc_cmd1] = data;
	6795	sachen_reg[state->mmc_cmd1] = data;
6694	6796
6695		switch (mmc_cmd1)
	6797	switch (state->mmc_cmd1)
6696	6798	{
6697	6799	case 0x05:
6698	6800	prg32(space->machine, data);
r7955	r7956
6701	6803	sachen_set_mirror(space->machine, BIT(data, 0) ? 0 : (data >> 1) & 0x03);
6702	6804	break;
6703	6805	default:
6704		if (mmc_chr_source == CHRROM)
	6806	if (state->mmc_chr_source == CHRROM)
6705	6807	{
6706	6808	bank_helper1 = sachen_reg[7] & 0x01;
6707	6809	bank_helper2 = (sachen_reg[4] & 0x07) << 3;
6708		chr2_0(space->machine, ((sachen_reg[bank_helper1 ? 0 : 0] & 0x07) \| bank_helper2) << 1, mmc_chr_source);
6709		chr2_2(space->machine, ((sachen_reg[bank_helper1 ? 0 : 1] & 0x07) \| bank_helper2) << 1 \| 0x01, mmc_chr_source);
6710		chr2_4(space->machine, ((sachen_reg[bank_helper1 ? 0 : 2] & 0x07) \| bank_helper2) << 1, mmc_chr_source);
6711		chr2_6(space->machine, ((sachen_reg[bank_helper1 ? 0 : 3] & 0x07) \| bank_helper2) << 1 \| 0x01, mmc_chr_source);
	6810	chr2_0(space->machine, ((sachen_reg[bank_helper1 ? 0 : 0] & 0x07) \| bank_helper2) << 1, state->mmc_chr_source);
	6811	chr2_2(space->machine, ((sachen_reg[bank_helper1 ? 0 : 1] & 0x07) \| bank_helper2) << 1 \| 0x01, state->mmc_chr_source);
	6812	chr2_4(space->machine, ((sachen_reg[bank_helper1 ? 0 : 2] & 0x07) \| bank_helper2) << 1, state->mmc_chr_source);
	6813	chr2_6(space->machine, ((sachen_reg[bank_helper1 ? 0 : 3] & 0x07) \| bank_helper2) << 1 \| 0x01, state->mmc_chr_source);
6712	6814	}
6713	6815	break;
6714	6816	}
r7955	r7956
6913	7015
6914	7016	static WRITE8_HANDLER( mapper150_l_w )
6915	7017	{
	7018	nes_state state = (nes_state )space->machine->driver_data;
6916	7019	LOG_MMC(("mapper150_l_w, offset: %04x, data: %02x\n", offset, data));
6917	7020
6918	7021	/* write happens only if we are at 0x4100 + k * 0x200, but 0x4100 is offset = 0 */
6919	7022	if (!(offset & 0x100))
6920	7023	{
6921	7024	if (!(offset & 0x01))
6922		mmc_cmd1 = data & 0x07;
	7025	state->mmc_cmd1 = data & 0x07;
6923	7026	else
6924	7027	{
6925		switch (mmc_cmd1)
	7028	switch (state->mmc_cmd1)
6926	7029	{
6927	7030	case 0x02:
6928		vrom_bank[0] = (vrom_bank[0] & ~0x08) \| ((data << 3) & 0x08);
6929		chr8(space->machine, vrom_bank[0], CHRROM);
	7031	state->vrom_bank[0] = (state->vrom_bank[0] & ~0x08) \| ((data << 3) & 0x08);
	7032	chr8(space->machine, state->vrom_bank[0], CHRROM);
6930	7033	prg32(space->machine, data & 0x01);
6931	7034	break;
6932	7035	case 0x04:
6933		vrom_bank[0] = (vrom_bank[0] & ~0x04) \| ((data << 2) & 0x04);
6934		chr8(space->machine, vrom_bank[0], CHRROM);
	7036	state->vrom_bank[0] = (state->vrom_bank[0] & ~0x04) \| ((data << 2) & 0x04);
	7037	chr8(space->machine, state->vrom_bank[0], CHRROM);
6935	7038	break;
6936	7039	case 0x05:
6937	7040	prg32(space->machine, data & 0x07);
6938	7041	break;
6939	7042	case 0x06:
6940		vrom_bank[0] = (vrom_bank[0] & ~0x03) \| (data << 0 & 0x03);
6941		chr8(space->machine, vrom_bank[0], CHRROM);
	7043	state->vrom_bank[0] = (state->vrom_bank[0] & ~0x03) \| (data << 0 & 0x03);
	7044	chr8(space->machine, state->vrom_bank[0], CHRROM);
6942	7045	break;
6943	7046	case 0x07:
6944	7047	sachen_set_mirror(space->machine, (data >> 1) & 0x03);
r7955	r7956
6952	7055
6953	7056	static READ8_HANDLER( mapper150_l_r )
6954	7057	{
	7058	nes_state state = (nes_state )space->machine->driver_data;
6955	7059	LOG_MMC(("mapper150_l_r, offset: %04x", offset));
6956	7060
6957	7061	/* read happens only if we are at 0x4100 + k * 0x200, but 0x4100 is offset = 0 */
6958	7062	if (!(offset & 0x100))
6959		return (~mmc_cmd1 & 0x3f) /* ^ dips*/; // we would need to check the Dips here
	7063	return (~state->mmc_cmd1 & 0x3f) /* ^ dips*/; // we would need to check the Dips here
6960	7064	else
6961	7065	return 0;
6962	7066	}
r7955	r7956
7084	7188
7085	7189	static WRITE8_HANDLER( mapper154_w )
7086	7190	{
	7191	nes_state state = (nes_state )space->machine->driver_data;
7087	7192	LOG_MMC(("mapper154_w, offset: %04x, data: %02x\n", offset, data));
7088	7193	switch (offset & 1)
7089	7194	{
7090	7195	case 0:
7091	7196	set_nt_mirroring(space->machine, BIT(data, 6) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
7092		mmc_cmd1 = data & 7;
	7197	state->mmc_cmd1 = data & 7;
7093	7198	break;
7094	7199	case 1:
7095		switch (mmc_cmd1)
	7200	switch (state->mmc_cmd1)
7096	7201	{
7097	7202	case 0: chr2_0(space->machine, data >> 1, CHRROM); break;
7098	7203	case 1: chr2_2(space->machine, data >> 1, CHRROM); break;
r7955	r7956
7198	7303	// probably wrong...
7199	7304	static void mapper158_set_mirror( running_machine *machine )
7200	7305	{
7201		UINT8 nt_mode = mmc_cmd1 & 0x80;
	7306	nes_state state = (nes_state )machine->driver_data;
	7307	UINT8 nt_mode = state->mmc_cmd1 & 0x80;
7202	7308
7203		set_nt_page(machine, 0, ROM, vrom_bank[nt_mode ? 2 : 0], 0);
7204		set_nt_page(machine, 1, ROM, vrom_bank[nt_mode ? 3 : 0], 0);
7205		set_nt_page(machine, 2, ROM, vrom_bank[nt_mode ? 4 : 1], 0);
7206		set_nt_page(machine, 3, ROM, vrom_bank[nt_mode ? 5 : 1], 0);
	7309	set_nt_page(machine, 0, ROM, state->vrom_bank[nt_mode ? 2 : 0], 0);
	7310	set_nt_page(machine, 1, ROM, state->vrom_bank[nt_mode ? 3 : 0], 0);
	7311	set_nt_page(machine, 2, ROM, state->vrom_bank[nt_mode ? 4 : 1], 0);
	7312	set_nt_page(machine, 3, ROM, state->vrom_bank[nt_mode ? 5 : 1], 0);
7207	7313	}
7208	7314
7209	7315	static WRITE8_HANDLER( mapper158_w )
7210	7316	{
	7317	nes_state state = (nes_state )space->machine->driver_data;
7211	7318	UINT8 map158_helper, cmd;
7212	7319	LOG_MMC(("mapper158_w offset: %04x, data: %02x\n", offset, data));
7213	7320
7214	7321	switch (offset & 0x6001)
7215	7322	{
7216	7323	case 0x0000:
7217		map158_helper = mmc_cmd1 ^ data;
7218		mmc_cmd1 = data;
	7324	map158_helper = state->mmc_cmd1 ^ data;
	7325	state->mmc_cmd1 = data;
7219	7326
7220	7327	/* Has PRG Mode changed? */
7221	7328	if (map158_helper & 0x40)
r7955	r7956
7230	7337	break;
7231	7338
7232	7339	case 0x0001:
7233		cmd = mmc_cmd1 & 0x0f;
	7340	cmd = state->mmc_cmd1 & 0x0f;
7234	7341	switch (cmd)
7235	7342	{
7236	7343	case 0: case 1:
7237	7344	case 2: case 3:
7238	7345	case 4: case 5:
7239		vrom_bank[cmd] = data;
	7346	state->vrom_bank[cmd] = data;
7240	7347	mapper64_set_chr(space->machine);
7241	7348	mapper158_set_mirror(space->machine);
7242	7349	break;
7243	7350	case 6: case 7:
7244		prg_bank[cmd - 6] = data;
	7351	state->prg_bank[cmd - 6] = data;
7245	7352	mapper64_set_prg(space->machine);
7246	7353	break;
7247	7354	case 8: case 9:
7248		vrom_bank[cmd - 2] = data;
	7355	state->vrom_bank[cmd - 2] = data;
7249	7356	mapper64_set_chr(space->machine);
7250	7357	mapper158_set_mirror(space->machine);
7251	7358	break;
7252	7359	case 0x0f:
7253		prg_bank[2] = data;
	7360	state->prg_bank[2] = data;
7254	7361	mapper64_set_prg(space->machine);
7255	7362	break;
7256	7363	}
r7955	r7956
7652	7759
7653	7760	static WRITE8_HANDLER( mapper178_l_w )
7654	7761	{
	7762	nes_state state = (nes_state )space->machine->driver_data;
7655	7763	LOG_MMC(("mapper178_l_w, offset: %04x, data: %02x\n", offset, data));
7656	7764
7657	7765	switch (offset)
r7955	r7956
7660	7768	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7661	7769	break;
7662	7770	case 0x701:
7663		mmc_cmd1 = (mmc_cmd1 & 0x0c) \| ((data >> 1) & 0x03);
7664		prg32(space->machine, mmc_cmd1);
	7771	state->mmc_cmd1 = (state->mmc_cmd1 & 0x0c) \| ((data >> 1) & 0x03);
	7772	prg32(space->machine, state->mmc_cmd1);
7665	7773	break;
7666	7774	case 0x702:
7667		mmc_cmd1 = (mmc_cmd1 & 0x03) \| ((data << 2) & 0x0c);
	7775	state->mmc_cmd1 = (state->mmc_cmd1 & 0x03) \| ((data << 2) & 0x0c);
7668	7776	break;
7669	7777	}
7670	7778	}
r7955	r7956
7745	7853
7746	7854	static WRITE8_HANDLER( mapper182_w )
7747	7855	{
	7856	nes_state state = (nes_state )space->machine->driver_data;
7748	7857	LOG_MMC(("mapper182_w, offset: %04x, data: %02x\n", offset, data));
7749	7858
7750	7859	switch (offset & 0x7003)
r7955	r7956
7753	7862	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7754	7863	break;
7755	7864	case 0x2000:
7756		mmc_cmd1 = data;
	7865	state->mmc_cmd1 = data;
7757	7866	break;
7758	7867	case 0x4000:
7759		switch (mmc_cmd1)
	7868	switch (state->mmc_cmd1)
7760	7869	{
7761	7870	case 0:
7762	7871	chr2_0(space->machine, data >> 1, CHRROM);
r7955	r7956
7787	7896	case 0x6003:
7788	7897	if (data)
7789	7898	{
7790		IRQ_count = data;
7791		IRQ_enable = 1;
	7899	state->IRQ_count = data;
	7900	state->IRQ_enable = 1;
7792	7901	}
7793	7902	else
7794		IRQ_enable = 0;
	7903	state->IRQ_enable = 0;
7795	7904	break;
7796	7905	}
7797	7906	}
r7955	r7956
7876	7985
7877	7986	static void mapper187_set_prg( running_machine *machine, int prg_base, int prg_mask )
7878	7987	{
7879		UINT8 prg_flip = (mmc_cmd1 & 0x40) ? 2 : 0;
	7988	nes_state state = (nes_state )machine->driver_data;
	7989	UINT8 prg_flip = (state->mmc_cmd1 & 0x40) ? 2 : 0;
7880	7990
7881	7991	if (!(mapper187_reg[0] & 0x80))
7882	7992	{
7883		prg8_89(machine, prg_base \| (prg_bank[0 ^ prg_flip] & prg_mask));
7884		prg8_ab(machine, prg_base \| (prg_bank[1] & prg_mask));
7885		prg8_cd(machine, prg_base \| (prg_bank[2 ^ prg_flip] & prg_mask));
7886		prg8_ef(machine, prg_base \| (prg_bank[3] & prg_mask));
	7993	prg8_89(machine, prg_base \| (state->prg_bank[0 ^ prg_flip] & prg_mask));
	7994	prg8_ab(machine, prg_base \| (state->prg_bank[1] & prg_mask));
	7995	prg8_cd(machine, prg_base \| (state->prg_bank[2 ^ prg_flip] & prg_mask));
	7996	prg8_ef(machine, prg_base \| (state->prg_bank[3] & prg_mask));
7887	7997	}
7888	7998	}
7889	7999
7890	8000	static void mapper187_set_chr( running_machine *machine, UINT8 chr, int chr_base, int chr_mask )
7891	8001	{
7892		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	8002	nes_state state = (nes_state )machine->driver_data;
	8003	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
7893	8004	UINT8 new_base[8];
7894	8005	int i;
7895	8006
7896	8007	for (i = 0; i < 8; i++)
7897	8008	new_base[i] = ((i & 0x04) == chr_page)? (chr_base \| 0x100) : chr_base;
7898	8009
7899		chr1_x(machine, chr_page ^ 0, new_base[0] \| ((vrom_bank[0] & ~0x01) & chr_mask), chr);
7900		chr1_x(machine, chr_page ^ 1, new_base[1] \| ((vrom_bank[0] \| 0x01) & chr_mask), chr);
7901		chr1_x(machine, chr_page ^ 2, new_base[2] \| ((vrom_bank[1] & ~0x01) & chr_mask), chr);
7902		chr1_x(machine, chr_page ^ 3, new_base[3] \| ((vrom_bank[1] \| 0x01) & chr_mask), chr);
7903		chr1_x(machine, chr_page ^ 4, new_base[4] \| (vrom_bank[2] & chr_mask), chr);
7904		chr1_x(machine, chr_page ^ 5, new_base[5] \| (vrom_bank[3] & chr_mask), chr);
7905		chr1_x(machine, chr_page ^ 6, new_base[6] \| (vrom_bank[4] & chr_mask), chr);
7906		chr1_x(machine, chr_page ^ 7, new_base[7] \| (vrom_bank[5] & chr_mask), chr);
	8010	chr1_x(machine, chr_page ^ 0, new_base[0] \| ((state->vrom_bank[0] & ~0x01) & chr_mask), chr);
	8011	chr1_x(machine, chr_page ^ 1, new_base[1] \| ((state->vrom_bank[0] \| 0x01) & chr_mask), chr);
	8012	chr1_x(machine, chr_page ^ 2, new_base[2] \| ((state->vrom_bank[1] & ~0x01) & chr_mask), chr);
	8013	chr1_x(machine, chr_page ^ 3, new_base[3] \| ((state->vrom_bank[1] \| 0x01) & chr_mask), chr);
	8014	chr1_x(machine, chr_page ^ 4, new_base[4] \| (state->vrom_bank[2] & chr_mask), chr);
	8015	chr1_x(machine, chr_page ^ 5, new_base[5] \| (state->vrom_bank[3] & chr_mask), chr);
	8016	chr1_x(machine, chr_page ^ 6, new_base[6] \| (state->vrom_bank[4] & chr_mask), chr);
	8017	chr1_x(machine, chr_page ^ 7, new_base[7] \| (state->vrom_bank[5] & chr_mask), chr);
7907	8018	}
7908	8019
7909	8020	static WRITE8_HANDLER( mapper187_l_w )
7910	8021	{
	8022	nes_state state = (nes_state )space->machine->driver_data;
7911	8023	UINT8 new_bank;
7912	8024	LOG_MMC(("mapper187_l_w, offset: %04x, data: %02x\n", offset, data));
7913	8025	offset += 0x100;
r7955	r7956
7946	8058	}
7947	8059	}
7948	8060	else
7949		mapper187_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8061	mapper187_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
7950	8062	}
7951	8063	}
7952	8064
r7955	r7956
7963	8075
7964	8076	static WRITE8_HANDLER( mapper187_w )
7965	8077	{
	8078	nes_state state = (nes_state )space->machine->driver_data;
7966	8079	UINT8 MMC3_helper, cmd;
7967	8080	LOG_MMC(("mapper187_w, offset: %04x, data: %02x\n", offset, data));
7968	8081
r7955	r7956
7970	8083	{
7971	8084	case 0x0000:
7972	8085	mapper187_reg[2] = 1;
7973		MMC3_helper = mmc_cmd1 ^ data;
7974		mmc_cmd1 = data;
	8086	MMC3_helper = state->mmc_cmd1 ^ data;
	8087	state->mmc_cmd1 = data;
7975	8088
7976	8089	/* Has PRG Mode changed? */
7977	8090	if (MMC3_helper & 0x40)
7978		mapper187_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8091	mapper187_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
7979	8092
7980	8093	/* Has CHR Mode changed? */
7981	8094	if (MMC3_helper & 0x80)
7982		mapper187_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	8095	mapper187_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
7983	8096	break;
7984	8097
7985	8098	case 0x0001:
7986	8099	if (mapper187_reg[2])
7987	8100	{
7988		cmd = mmc_cmd1 & 0x07;
	8101	cmd = state->mmc_cmd1 & 0x07;
7989	8102	switch (cmd)
7990	8103	{
7991	8104	case 0: case 1:
7992	8105	case 2: case 3: case 4: case 5:
7993		vrom_bank[cmd] = data;
7994		mapper187_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	8106	state->vrom_bank[cmd] = data;
	8107	mapper187_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
7995	8108	break;
7996	8109	case 6:
7997	8110	case 7:
7998		prg_bank[cmd - 6] = data;
7999		mapper187_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8111	state->prg_bank[cmd - 6] = data;
	8112	mapper187_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8000	8113	break;
8001	8114	}
8002	8115	}
r7955	r7956
8068	8181	/* This is like mapper4 but with no PRG bankswitch (beacuse it is handled by low writes) */
8069	8182	static WRITE8_HANDLER( mapper189_w )
8070	8183	{
	8184	nes_state state = (nes_state )space->machine->driver_data;
8071	8185	UINT8 MMC3_helper, cmd;
8072	8186	LOG_MMC(("mapper189_w, offset: %04x, data: %02x\n", offset, data));
8073	8187
8074	8188	switch (offset & 0x6001)
8075	8189	{
8076	8190	case 0x0000:
8077		MMC3_helper = mmc_cmd1 ^ data;
8078		mmc_cmd1 = data;
	8191	MMC3_helper = state->mmc_cmd1 ^ data;
	8192	state->mmc_cmd1 = data;
8079	8193
8080	8194	/* Has CHR Mode changed? */
8081	8195	if (MMC3_helper & 0x80)
8082		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	8196	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
8083	8197	break;
8084	8198
8085	8199	case 0x0001:
8086		cmd = mmc_cmd1 & 0x07;
	8200	cmd = state->mmc_cmd1 & 0x07;
8087	8201	switch (cmd)
8088	8202	{
8089	8203	case 0: case 1:
8090	8204	case 2: case 3: case 4: case 5:
8091		vrom_bank[cmd] = data;
8092		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	8205	state->vrom_bank[cmd] = data;
	8206	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
8093	8207	break;
8094	8208	}
8095	8209	break;
r7955	r7956
8128	8242
8129	8243	static void mapper191_set_chr( running_machine *machine, int chr_base, int chr_mask )
8130	8244	{
8131		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	8245	nes_state state = (nes_state )machine->driver_data;
	8246	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
8132	8247	UINT8 chr_src[6];
8133	8248	int i;
8134	8249
8135	8250	for (i = 0; i < 6; i++)
8136		chr_src[i] = (vrom_bank[i] & 0x80) ? CHRRAM : CHRROM;
	8251	chr_src[i] = (state->vrom_bank[i] & 0x80) ? CHRRAM : CHRROM;
8137	8252
8138		chr1_x(machine, chr_page ^ 0, chr_base \| ((vrom_bank[0] & ~0x01) & chr_mask), chr_src[0]);
8139		chr1_x(machine, chr_page ^ 1, chr_base \| ((vrom_bank[0] \| 0x01) & chr_mask), chr_src[0]);
8140		chr1_x(machine, chr_page ^ 2, chr_base \| ((vrom_bank[1] & ~0x01) & chr_mask), chr_src[1]);
8141		chr1_x(machine, chr_page ^ 3, chr_base \| ((vrom_bank[1] \| 0x01) & chr_mask), chr_src[1]);
8142		chr1_x(machine, chr_page ^ 4, chr_base \| (vrom_bank[2] & chr_mask), chr_src[2]);
8143		chr1_x(machine, chr_page ^ 5, chr_base \| (vrom_bank[3] & chr_mask), chr_src[3]);
8144		chr1_x(machine, chr_page ^ 6, chr_base \| (vrom_bank[4] & chr_mask), chr_src[4]);
8145		chr1_x(machine, chr_page ^ 7, chr_base \| (vrom_bank[5] & chr_mask), chr_src[5]);
	8253	chr1_x(machine, chr_page ^ 0, chr_base \| ((state->vrom_bank[0] & ~0x01) & chr_mask), chr_src[0]);
	8254	chr1_x(machine, chr_page ^ 1, chr_base \| ((state->vrom_bank[0] \| 0x01) & chr_mask), chr_src[0]);
	8255	chr1_x(machine, chr_page ^ 2, chr_base \| ((state->vrom_bank[1] & ~0x01) & chr_mask), chr_src[1]);
	8256	chr1_x(machine, chr_page ^ 3, chr_base \| ((state->vrom_bank[1] \| 0x01) & chr_mask), chr_src[1]);
	8257	chr1_x(machine, chr_page ^ 4, chr_base \| (state->vrom_bank[2] & chr_mask), chr_src[2]);
	8258	chr1_x(machine, chr_page ^ 5, chr_base \| (state->vrom_bank[3] & chr_mask), chr_src[3]);
	8259	chr1_x(machine, chr_page ^ 6, chr_base \| (state->vrom_bank[4] & chr_mask), chr_src[4]);
	8260	chr1_x(machine, chr_page ^ 7, chr_base \| (state->vrom_bank[5] & chr_mask), chr_src[5]);
8146	8261	}
8147	8262
8148	8263	static WRITE8_HANDLER( mapper191_w )
8149	8264	{
	8265	nes_state state = (nes_state )space->machine->driver_data;
8150	8266	UINT8 MMC3_helper, cmd;
8151	8267	LOG_MMC(("mapper191_w, offset: %04x, data: %02x\n", offset, data));
8152	8268
8153	8269	switch (offset & 0x6001)
8154	8270	{
8155	8271	case 0x0000:
8156		MMC3_helper = mmc_cmd1 ^ data;
8157		mmc_cmd1 = data;
	8272	MMC3_helper = state->mmc_cmd1 ^ data;
	8273	state->mmc_cmd1 = data;
8158	8274
8159	8275	/* Has PRG Mode changed? */
8160	8276	if (MMC3_helper & 0x40)
8161		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8277	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8162	8278
8163	8279	/* Has CHR Mode changed? */
8164	8280	if (MMC3_helper & 0x80)
8165		mapper191_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	8281	mapper191_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
8166	8282	break;
8167	8283
8168	8284	case 0x0001:
8169		cmd = mmc_cmd1 & 0x07;
	8285	cmd = state->mmc_cmd1 & 0x07;
8170	8286	switch (cmd)
8171	8287	{
8172	8288	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
8173	8289	case 2: case 3: case 4: case 5:
8174		vrom_bank[cmd] = data;
8175		mapper191_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	8290	state->vrom_bank[cmd] = data;
	8291	mapper191_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
8176	8292	break;
8177	8293	case 6:
8178	8294	case 7:
8179		prg_bank[cmd - 6] = data;
8180		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8295	state->prg_bank[cmd - 6] = data;
	8296	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8181	8297	break;
8182	8298	}
8183	8299	break;
r7955	r7956
8205	8321
8206	8322	static void mapper192_set_chr( running_machine *machine, int chr_base, int chr_mask )
8207	8323	{
8208		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	8324	nes_state state = (nes_state )machine->driver_data;
	8325	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
8209	8326	UINT8 chr_src[6];
8210	8327	int i;
8211	8328
8212	8329	for (i = 0; i < 6; i++)
8213		chr_src[i] = ((vrom_bank[i] == 0x08) \|\| (vrom_bank[i] == 0x09) \|\| (vrom_bank[i] == 0x0a) \|\| (vrom_bank[i] == 0x0b)) ? CHRRAM : CHRROM;
	8330	chr_src[i] = ((state->vrom_bank[i] == 0x08) \|\| (state->vrom_bank[i] == 0x09) \|\| (state->vrom_bank[i] == 0x0a) \|\| (state->vrom_bank[i] == 0x0b)) ? CHRRAM : CHRROM;
8214	8331
8215		chr1_x(machine, chr_page ^ 0, chr_base \| ((vrom_bank[0] & ~0x01) & chr_mask), chr_src[0]);
8216		chr1_x(machine, chr_page ^ 1, chr_base \| ((vrom_bank[0] \| 0x01) & chr_mask), chr_src[0]);
8217		chr1_x(machine, chr_page ^ 2, chr_base \| ((vrom_bank[1] & ~0x01) & chr_mask), chr_src[1]);
8218		chr1_x(machine, chr_page ^ 3, chr_base \| ((vrom_bank[1] \| 0x01) & chr_mask), chr_src[1]);
8219		chr1_x(machine, chr_page ^ 4, chr_base \| (vrom_bank[2] & chr_mask), chr_src[2]);
8220		chr1_x(machine, chr_page ^ 5, chr_base \| (vrom_bank[3] & chr_mask), chr_src[3]);
8221		chr1_x(machine, chr_page ^ 6, chr_base \| (vrom_bank[4] & chr_mask), chr_src[4]);
8222		chr1_x(machine, chr_page ^ 7, chr_base \| (vrom_bank[5] & chr_mask), chr_src[5]);
	8332	chr1_x(machine, chr_page ^ 0, chr_base \| ((state->vrom_bank[0] & ~0x01) & chr_mask), chr_src[0]);
	8333	chr1_x(machine, chr_page ^ 1, chr_base \| ((state->vrom_bank[0] \| 0x01) & chr_mask), chr_src[0]);
	8334	chr1_x(machine, chr_page ^ 2, chr_base \| ((state->vrom_bank[1] & ~0x01) & chr_mask), chr_src[1]);
	8335	chr1_x(machine, chr_page ^ 3, chr_base \| ((state->vrom_bank[1] \| 0x01) & chr_mask), chr_src[1]);
	8336	chr1_x(machine, chr_page ^ 4, chr_base \| (state->vrom_bank[2] & chr_mask), chr_src[2]);
	8337	chr1_x(machine, chr_page ^ 5, chr_base \| (state->vrom_bank[3] & chr_mask), chr_src[3]);
	8338	chr1_x(machine, chr_page ^ 6, chr_base \| (state->vrom_bank[4] & chr_mask), chr_src[4]);
	8339	chr1_x(machine, chr_page ^ 7, chr_base \| (state->vrom_bank[5] & chr_mask), chr_src[5]);
8223	8340	}
8224	8341
8225	8342	static WRITE8_HANDLER( mapper192_w )
8226	8343	{
	8344	nes_state state = (nes_state )space->machine->driver_data;
8227	8345	UINT8 MMC3_helper, cmd;
8228	8346	LOG_MMC(("mapper192_w, offset: %04x, data: %02x\n", offset, data));
8229	8347
8230	8348	switch (offset & 0x6001)
8231	8349	{
8232	8350	case 0x0000:
8233		MMC3_helper = mmc_cmd1 ^ data;
8234		mmc_cmd1 = data;
	8351	MMC3_helper = state->mmc_cmd1 ^ data;
	8352	state->mmc_cmd1 = data;
8235	8353
8236	8354	/* Has PRG Mode changed? */
8237	8355	if (MMC3_helper & 0x40)
8238		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8356	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8239	8357
8240	8358	/* Has CHR Mode changed? */
8241	8359	if (MMC3_helper & 0x80)
8242		mapper192_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	8360	mapper192_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
8243	8361	break;
8244	8362
8245	8363	case 0x0001:
8246		cmd = mmc_cmd1 & 0x07;
	8364	cmd = state->mmc_cmd1 & 0x07;
8247	8365	switch (cmd)
8248	8366	{
8249	8367	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
8250	8368	case 2: case 3: case 4: case 5:
8251		vrom_bank[cmd] = data;
8252		mapper192_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	8369	state->vrom_bank[cmd] = data;
	8370	mapper192_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
8253	8371	break;
8254	8372	case 6:
8255	8373	case 7:
8256		prg_bank[cmd - 6] = data;
8257		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8374	state->prg_bank[cmd - 6] = data;
	8375	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8258	8376	break;
8259	8377	}
8260	8378	break;
r7955	r7956
8317	8435
8318	8436	static void mapper194_set_chr( running_machine *machine, int chr_base, int chr_mask )
8319	8437	{
8320		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	8438	nes_state state = (nes_state )machine->driver_data;
	8439	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
8321	8440	UINT8 chr_src[6];
8322	8441	int i;
8323	8442
8324	8443	for (i = 0; i < 6; i++)
8325		chr_src[i] = (vrom_bank[i] < 0x02) ? CHRRAM : CHRROM;
	8444	chr_src[i] = (state->vrom_bank[i] < 0x02) ? CHRRAM : CHRROM;
8326	8445
8327		chr1_x(machine, chr_page ^ 0, chr_base \| ((vrom_bank[0] & ~0x01) & chr_mask), chr_src[0]);
8328		chr1_x(machine, chr_page ^ 1, chr_base \| ((vrom_bank[0] \| 0x01) & chr_mask), chr_src[0]);
8329		chr1_x(machine, chr_page ^ 2, chr_base \| ((vrom_bank[1] & ~0x01) & chr_mask), chr_src[1]);
8330		chr1_x(machine, chr_page ^ 3, chr_base \| ((vrom_bank[1] \| 0x01) & chr_mask), chr_src[1]);
8331		chr1_x(machine, chr_page ^ 4, chr_base \| (vrom_bank[2] & chr_mask), chr_src[2]);
8332		chr1_x(machine, chr_page ^ 5, chr_base \| (vrom_bank[3] & chr_mask), chr_src[3]);
8333		chr1_x(machine, chr_page ^ 6, chr_base \| (vrom_bank[4] & chr_mask), chr_src[4]);
8334		chr1_x(machine, chr_page ^ 7, chr_base \| (vrom_bank[5] & chr_mask), chr_src[5]);
	8446	chr1_x(machine, chr_page ^ 0, chr_base \| ((state->vrom_bank[0] & ~0x01) & chr_mask), chr_src[0]);
	8447	chr1_x(machine, chr_page ^ 1, chr_base \| ((state->vrom_bank[0] \| 0x01) & chr_mask), chr_src[0]);
	8448	chr1_x(machine, chr_page ^ 2, chr_base \| ((state->vrom_bank[1] & ~0x01) & chr_mask), chr_src[1]);
	8449	chr1_x(machine, chr_page ^ 3, chr_base \| ((state->vrom_bank[1] \| 0x01) & chr_mask), chr_src[1]);
	8450	chr1_x(machine, chr_page ^ 4, chr_base \| (state->vrom_bank[2] & chr_mask), chr_src[2]);
	8451	chr1_x(machine, chr_page ^ 5, chr_base \| (state->vrom_bank[3] & chr_mask), chr_src[3]);
	8452	chr1_x(machine, chr_page ^ 6, chr_base \| (state->vrom_bank[4] & chr_mask), chr_src[4]);
	8453	chr1_x(machine, chr_page ^ 7, chr_base \| (state->vrom_bank[5] & chr_mask), chr_src[5]);
8335	8454	}
8336	8455
8337	8456	static WRITE8_HANDLER( mapper194_w )
8338	8457	{
	8458	nes_state state = (nes_state )space->machine->driver_data;
8339	8459	UINT8 MMC3_helper, cmd;
8340	8460	LOG_MMC(("mapper194_w, offset: %04x, data: %02x\n", offset, data));
8341	8461
8342	8462	switch (offset & 0x6001)
8343	8463	{
8344	8464	case 0x0000:
8345		MMC3_helper = mmc_cmd1 ^ data;
8346		mmc_cmd1 = data;
	8465	MMC3_helper = state->mmc_cmd1 ^ data;
	8466	state->mmc_cmd1 = data;
8347	8467
8348	8468	/* Has PRG Mode changed? */
8349	8469	if (MMC3_helper & 0x40)
8350		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8470	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8351	8471
8352	8472	/* Has CHR Mode changed? */
8353	8473	if (MMC3_helper & 0x80)
8354		mapper194_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	8474	mapper194_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
8355	8475	break;
8356	8476
8357	8477	case 0x0001:
8358		cmd = mmc_cmd1 & 0x07;
	8478	cmd = state->mmc_cmd1 & 0x07;
8359	8479	switch (cmd)
8360	8480	{
8361	8481	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
8362	8482	case 2: case 3: case 4: case 5:
8363		vrom_bank[cmd] = data;
8364		mapper194_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	8483	state->vrom_bank[cmd] = data;
	8484	mapper194_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
8365	8485	break;
8366	8486	case 6:
8367	8487	case 7:
8368		prg_bank[cmd - 6] = data;
8369		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8488	state->prg_bank[cmd - 6] = data;
	8489	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8370	8490	break;
8371	8491	}
8372	8492	break;
r7955	r7956
8395	8515
8396	8516	static void mapper195_set_chr( running_machine *machine, int chr_base, int chr_mask )
8397	8517	{
8398		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	8518	nes_state state = (nes_state )machine->driver_data;
	8519	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
8399	8520	UINT8 chr_src[6];
8400	8521	int i;
8401	8522
8402	8523	for (i = 0; i < 6; i++)
8403		chr_src[i] = (vrom_bank[i] < 0x04) ? CHRRAM : CHRROM;
	8524	chr_src[i] = (state->vrom_bank[i] < 0x04) ? CHRRAM : CHRROM;
8404	8525
8405		chr1_x(machine, chr_page ^ 0, chr_base \| ((vrom_bank[0] & ~0x01) & chr_mask), chr_src[0]);
8406		chr1_x(machine, chr_page ^ 1, chr_base \| ((vrom_bank[0] \| 0x01) & chr_mask), chr_src[0]);
8407		chr1_x(machine, chr_page ^ 2, chr_base \| ((vrom_bank[1] & ~0x01) & chr_mask), chr_src[1]);
8408		chr1_x(machine, chr_page ^ 3, chr_base \| ((vrom_bank[1] \| 0x01) & chr_mask), chr_src[1]);
8409		chr1_x(machine, chr_page ^ 4, chr_base \| (vrom_bank[2] & chr_mask), chr_src[2]);
8410		chr1_x(machine, chr_page ^ 5, chr_base \| (vrom_bank[3] & chr_mask), chr_src[3]);
8411		chr1_x(machine, chr_page ^ 6, chr_base \| (vrom_bank[4] & chr_mask), chr_src[4]);
8412		chr1_x(machine, chr_page ^ 7, chr_base \| (vrom_bank[5] & chr_mask), chr_src[5]);
	8526	chr1_x(machine, chr_page ^ 0, chr_base \| ((state->vrom_bank[0] & ~0x01) & chr_mask), chr_src[0]);
	8527	chr1_x(machine, chr_page ^ 1, chr_base \| ((state->vrom_bank[0] \| 0x01) & chr_mask), chr_src[0]);
	8528	chr1_x(machine, chr_page ^ 2, chr_base \| ((state->vrom_bank[1] & ~0x01) & chr_mask), chr_src[1]);
	8529	chr1_x(machine, chr_page ^ 3, chr_base \| ((state->vrom_bank[1] \| 0x01) & chr_mask), chr_src[1]);
	8530	chr1_x(machine, chr_page ^ 4, chr_base \| (state->vrom_bank[2] & chr_mask), chr_src[2]);
	8531	chr1_x(machine, chr_page ^ 5, chr_base \| (state->vrom_bank[3] & chr_mask), chr_src[3]);
	8532	chr1_x(machine, chr_page ^ 6, chr_base \| (state->vrom_bank[4] & chr_mask), chr_src[4]);
	8533	chr1_x(machine, chr_page ^ 7, chr_base \| (state->vrom_bank[5] & chr_mask), chr_src[5]);
8413	8534	}
8414	8535
8415	8536	static WRITE8_HANDLER( mapper195_w )
8416	8537	{
	8538	nes_state state = (nes_state )space->machine->driver_data;
8417	8539	UINT8 MMC3_helper, cmd;
8418	8540	LOG_MMC(("mapper195_w, offset: %04x, data: %02x\n", offset, data));
8419	8541
8420	8542	switch (offset & 0x6001)
8421	8543	{
8422	8544	case 0x0000:
8423		MMC3_helper = mmc_cmd1 ^ data;
8424		mmc_cmd1 = data;
	8545	MMC3_helper = state->mmc_cmd1 ^ data;
	8546	state->mmc_cmd1 = data;
8425	8547
8426	8548	/* Has PRG Mode changed? */
8427	8549	if (MMC3_helper & 0x40)
8428		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8550	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8429	8551
8430	8552	/* Has CHR Mode changed? */
8431	8553	if (MMC3_helper & 0x80)
8432		mapper195_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	8554	mapper195_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
8433	8555	break;
8434	8556
8435	8557	case 0x0001:
8436		cmd = mmc_cmd1 & 0x07;
	8558	cmd = state->mmc_cmd1 & 0x07;
8437	8559	switch (cmd)
8438	8560	{
8439	8561	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
8440	8562	case 2: case 3: case 4: case 5:
8441		vrom_bank[cmd] = data;
8442		mapper195_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	8563	state->vrom_bank[cmd] = data;
	8564	mapper195_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
8443	8565	break;
8444	8566	case 6:
8445	8567	case 7:
8446		prg_bank[cmd - 6] = data;
8447		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8568	state->prg_bank[cmd - 6] = data;
	8569	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8448	8570	break;
8449	8571	}
8450	8572	break;
r7955	r7956
8491	8613
8492	8614	static void mapper197_set_chr( running_machine *machine, UINT8 chr_source, int chr_base, int chr_mask )
8493	8615	{
8494		chr4_0(machine, chr_base \| ((vrom_bank[0] >> 1) & chr_mask), chr_source);
8495		chr2_4(machine, chr_base \| (vrom_bank[1] & chr_mask), chr_source);
8496		chr2_6(machine, chr_base \| (vrom_bank[2] & chr_mask), chr_source);
	8616	nes_state state = (nes_state )machine->driver_data;
	8617	chr4_0(machine, chr_base \| ((state->vrom_bank[0] >> 1) & chr_mask), chr_source);
	8618	chr2_4(machine, chr_base \| (state->vrom_bank[1] & chr_mask), chr_source);
	8619	chr2_6(machine, chr_base \| (state->vrom_bank[2] & chr_mask), chr_source);
8497	8620	}
8498	8621
8499	8622	static WRITE8_HANDLER( mapper197_w )
8500	8623	{
	8624	nes_state state = (nes_state )space->machine->driver_data;
8501	8625	UINT8 MMC3_helper, cmd;
8502	8626	LOG_MMC(("mapper197_w, offset: %04x, data: %02x\n", offset, data));
8503	8627
8504	8628	switch (offset & 0x6001)
8505	8629	{
8506	8630	case 0x0000:
8507		MMC3_helper = mmc_cmd1 ^ data;
8508		mmc_cmd1 = data;
	8631	MMC3_helper = state->mmc_cmd1 ^ data;
	8632	state->mmc_cmd1 = data;
8509	8633
8510	8634	/* Has PRG Mode changed? */
8511	8635	if (MMC3_helper & 0x40)
8512		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8636	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8513	8637
8514	8638	/* Has CHR Mode changed? */
8515	8639	if (MMC3_helper & 0x80)
8516		mapper197_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	8640	mapper197_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
8517	8641	break;
8518	8642
8519	8643	case 0x0001:
8520		cmd = mmc_cmd1 & 0x0f;
	8644	cmd = state->mmc_cmd1 & 0x0f;
8521	8645	switch (cmd)
8522	8646	{
8523	8647	case 0: case 2: case 4:
8524		vrom_bank[cmd >> 1] = data;
8525		mapper197_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	8648	state->vrom_bank[cmd >> 1] = data;
	8649	mapper197_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
8526	8650	break;
8527	8651	case 6:
8528	8652	case 7:
8529		prg_bank[cmd - 6] = data;
8530		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8653	state->prg_bank[cmd - 6] = data;
	8654	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8531	8655	break;
8532	8656	}
8533	8657	break;
r7955	r7956
8553	8677
8554	8678	static void mapper198_set_prg( running_machine *machine, int prg_base, int prg_mask )
8555	8679	{
8556		UINT8 prg_flip = (mmc_cmd1 & 0x40) ? 2 : 0;
	8680	nes_state state = (nes_state )machine->driver_data;
	8681	UINT8 prg_flip = (state->mmc_cmd1 & 0x40) ? 2 : 0;
8557	8682
8558		prg8_89(machine, prg_base \| (prg_bank[0 ^ prg_flip] & prg_mask));
8559		prg8_ab(machine, prg_base \| (prg_bank[1] & prg_mask));
8560		prg8_cd(machine, prg_base \| (prg_bank[2 ^ prg_flip] & prg_mask));
8561		prg8_ef(machine, prg_base \| (prg_bank[3] & prg_mask));
	8683	prg8_89(machine, prg_base \| (state->prg_bank[0 ^ prg_flip] & prg_mask));
	8684	prg8_ab(machine, prg_base \| (state->prg_bank[1] & prg_mask));
	8685	prg8_cd(machine, prg_base \| (state->prg_bank[2 ^ prg_flip] & prg_mask));
	8686	prg8_ef(machine, prg_base \| (state->prg_bank[3] & prg_mask));
8562	8687	}
8563	8688
8564	8689	static WRITE8_HANDLER( mapper198_w )
8565	8690	{
	8691	nes_state state = (nes_state )space->machine->driver_data;
8566	8692	UINT8 MMC3_helper, cmd;
8567	8693	LOG_MMC(("mapper198_w, offset: %04x, data: %02x\n", offset, data));
8568	8694
8569	8695	switch (offset & 0x6001)
8570	8696	{
8571	8697	case 0x0000:
8572		MMC3_helper = mmc_cmd1 ^ data;
8573		mmc_cmd1 = data;
	8698	MMC3_helper = state->mmc_cmd1 ^ data;
	8699	state->mmc_cmd1 = data;
8574	8700
8575	8701	/* Has PRG Mode changed? */
8576	8702	if (MMC3_helper & 0x40)
8577		mapper198_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8703	mapper198_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8578	8704
8579	8705	/* Has CHR Mode changed? */
8580	8706	if (MMC3_helper & 0x80)
8581		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	8707	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
8582	8708	break;
8583	8709
8584	8710	case 0x0001:
8585		cmd = mmc_cmd1 & 0x07;
	8711	cmd = state->mmc_cmd1 & 0x07;
8586	8712	switch (cmd)
8587	8713	{
8588	8714	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
8589	8715	case 2: case 3: case 4: case 5:
8590		vrom_bank[cmd] = data;
8591		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	8716	state->vrom_bank[cmd] = data;
	8717	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
8592	8718	break;
8593	8719	case 6:
8594	8720	case 7:
8595		prg_bank[cmd - 6] = data & ((data > 0x3f) ? 0x4f : 0x3f);
8596		mapper198_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8721	state->prg_bank[cmd - 6] = data & ((data > 0x3f) ? 0x4f : 0x3f);
	8722	mapper198_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8597	8723	break;
8598	8724	}
8599	8725	break;
r7955	r7956
8620	8746
8621	8747	static void mapper199_set_chr( running_machine *machine, int chr_base, int chr_mask )
8622	8748	{
8623		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	8749	nes_state state = (nes_state )machine->driver_data;
	8750	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
8624	8751	UINT8 chr_src[8];
8625	8752	int i;
8626	8753
8627	8754	for (i = 0; i < 8; i++)
8628		chr_src[i] = (vrom_bank[i] < 0x08) ? CHRRAM : CHRROM;
	8755	chr_src[i] = (state->vrom_bank[i] < 0x08) ? CHRRAM : CHRROM;
8629	8756
8630		chr1_x(machine, chr_page ^ 0, chr_base \| (vrom_bank[0] & chr_mask), chr_src[0]);
8631		chr1_x(machine, chr_page ^ 1, chr_base \| (vrom_bank[6] & chr_mask), chr_src[6]);
8632		chr1_x(machine, chr_page ^ 2, chr_base \| (vrom_bank[1] & chr_mask), chr_src[1]);
8633		chr1_x(machine, chr_page ^ 3, chr_base \| (vrom_bank[7] & chr_mask), chr_src[7]);
8634		chr1_x(machine, chr_page ^ 4, chr_base \| (vrom_bank[2] & chr_mask), chr_src[2]);
8635		chr1_x(machine, chr_page ^ 5, chr_base \| (vrom_bank[3] & chr_mask), chr_src[3]);
8636		chr1_x(machine, chr_page ^ 6, chr_base \| (vrom_bank[4] & chr_mask), chr_src[4]);
8637		chr1_x(machine, chr_page ^ 7, chr_base \| (vrom_bank[5] & chr_mask), chr_src[5]);
	8757	chr1_x(machine, chr_page ^ 0, chr_base \| (state->vrom_bank[0] & chr_mask), chr_src[0]);
	8758	chr1_x(machine, chr_page ^ 1, chr_base \| (state->vrom_bank[6] & chr_mask), chr_src[6]);
	8759	chr1_x(machine, chr_page ^ 2, chr_base \| (state->vrom_bank[1] & chr_mask), chr_src[1]);
	8760	chr1_x(machine, chr_page ^ 3, chr_base \| (state->vrom_bank[7] & chr_mask), chr_src[7]);
	8761	chr1_x(machine, chr_page ^ 4, chr_base \| (state->vrom_bank[2] & chr_mask), chr_src[2]);
	8762	chr1_x(machine, chr_page ^ 5, chr_base \| (state->vrom_bank[3] & chr_mask), chr_src[3]);
	8763	chr1_x(machine, chr_page ^ 6, chr_base \| (state->vrom_bank[4] & chr_mask), chr_src[4]);
	8764	chr1_x(machine, chr_page ^ 7, chr_base \| (state->vrom_bank[5] & chr_mask), chr_src[5]);
8638	8765	}
8639	8766
8640	8767	static WRITE8_HANDLER( mapper199_w )
8641	8768	{
	8769	nes_state state = (nes_state )space->machine->driver_data;
8642	8770	UINT8 MMC3_helper, cmd;
8643	8771	LOG_MMC(("mapper199_w, offset: %04x, data: %02x\n", offset, data));
8644	8772
8645	8773	switch (offset & 0x6001)
8646	8774	{
8647	8775	case 0x0000:
8648		MMC3_helper = mmc_cmd1 ^ data;
8649		mmc_cmd1 = data;
	8776	MMC3_helper = state->mmc_cmd1 ^ data;
	8777	state->mmc_cmd1 = data;
8650	8778
8651	8779	/* Has PRG Mode changed? */
8652	8780	if (MMC3_helper & 0x40)
8653		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8781	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8654	8782
8655	8783	/* Has CHR Mode changed? */
8656	8784	if (MMC3_helper & 0x80)
8657		mapper199_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	8785	mapper199_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
8658	8786	break;
8659	8787
8660	8788	case 0x0001:
8661		cmd = mmc_cmd1 & 0x0f;
	8789	cmd = state->mmc_cmd1 & 0x0f;
8662	8790	switch (cmd)
8663	8791	{
8664	8792	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
8665	8793	case 2: case 3: case 4: case 5:
8666		vrom_bank[cmd] = data;
8667		mapper199_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	8794	state->vrom_bank[cmd] = data;
	8795	mapper199_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
8668	8796	break;
8669	8797	case 6:
8670	8798	case 7:
8671	8799	case 8:
8672	8800	case 9:
8673		prg_bank[cmd - 6] = data;
8674		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	8801	state->prg_bank[cmd - 6] = data;
	8802	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
8675	8803	break;
8676	8804	case 0x0a: case 0x0b:
8677		vrom_bank[cmd - 4] = data;
8678		mapper199_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	8805	state->vrom_bank[cmd - 4] = data;
	8806	mapper199_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
8679	8807	break;
8680	8808	}
8681	8809	break;
r7955	r7956
8810	8938
8811	8939	static WRITE8_HANDLER( mapper205_m_w )
8812	8940	{
	8941	nes_state state = (nes_state )space->machine->driver_data;
8813	8942	LOG_MMC(("mapper205_m_w, offset: %04x, data: %02x\n", offset, data));
8814	8943
8815	8944	if (offset & 0x0800)
8816	8945	{
8817		mmc_prg_base = (data & 0x03) << 4;
8818		mmc_prg_mask = (data & 0x02) ? 0x0f : 0x1f;
8819		mmc_chr_base = (data & 0x03) << 7;
8820		mmc_chr_mask = (data & 0x02) ? 0x7f : 0xff;
8821		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
8822		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	8946	state->mmc_prg_base = (data & 0x03) << 4;
	8947	state->mmc_prg_mask = (data & 0x02) ? 0x0f : 0x1f;
	8948	state->mmc_chr_base = (data & 0x03) << 7;
	8949	state->mmc_chr_mask = (data & 0x02) ? 0x7f : 0xff;
	8950	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
	8951	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
8823	8952	}
8824	8953	}
8825	8954
r7955	r7956
8973	9102	// replace with map189_w... they are the same!!
8974	9103	static WRITE8_HANDLER( mapper208_w )
8975	9104	{
	9105	nes_state state = (nes_state )space->machine->driver_data;
8976	9106	UINT8 MMC3_helper, cmd;
8977	9107	LOG_MMC(("mapper208_w, offset: %04x, data: %02x\n", offset, data));
8978	9108
8979	9109	switch (offset & 0x6001)
8980	9110	{
8981	9111	case 0x0000:
8982		MMC3_helper = mmc_cmd1 ^ data;
8983		mmc_cmd1 = data;
	9112	MMC3_helper = state->mmc_cmd1 ^ data;
	9113	state->mmc_cmd1 = data;
8984	9114
8985	9115	/* Has CHR Mode changed? */
8986	9116	if (MMC3_helper & 0x80)
8987		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	9117	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
8988	9118	break;
8989	9119
8990	9120	case 0x0001:
8991		cmd = mmc_cmd1 & 0x07;
	9121	cmd = state->mmc_cmd1 & 0x07;
8992	9122	switch (cmd)
8993	9123	{
8994	9124	case 0: case 1:
8995	9125	case 2: case 3: case 4: case 5:
8996		vrom_bank[cmd] = data;
8997		mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
	9126	state->vrom_bank[cmd] = data;
	9127	mapper4_set_chr(space->machine, state->mmc_chr_source, state->mmc_chr_base, state->mmc_chr_mask);
8998	9128	break;
8999	9129	}
9000	9130	break;
r7955	r7956
9131	9261	// remove mask & base parameters!
9132	9262	static void mapper215_set_prg( running_machine *machine, int prg_base, int prg_mask )
9133	9263	{
	9264	nes_state state = (nes_state )machine->driver_data;
9134	9265	if (map215_reg[0] & 0x80)
9135	9266	{
9136	9267	prg16_89ab(machine, (map215_reg[0] & 0xf0) \| (map215_reg[1] & 0x10));
r7955	r7956
9138	9269	}
9139	9270	else
9140	9271	{
9141		mmc_prg_base = (map215_reg[1] & 0x08) ? 0x20 : (map215_reg[1] & 0x10);
9142		mmc_prg_mask = (map215_reg[1] & 0x08) ? 0x1f : 0x0f;
	9272	state->mmc_prg_base = (map215_reg[1] & 0x08) ? 0x20 : (map215_reg[1] & 0x10);
	9273	state->mmc_prg_mask = (map215_reg[1] & 0x08) ? 0x1f : 0x0f;
9143	9274
9144		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
	9275	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
9145	9276	}
9146	9277	}
9147	9278
9148	9279	static void mapper215_set_chr( running_machine *machine, UINT8 chr )
9149	9280	{
9150		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	9281	nes_state state = (nes_state )machine->driver_data;
	9282	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
9151	9283	int chr_base = (map215_reg[1] & 0x04) ? 0x100 : ((map215_reg[1] & 0x10) << 3);
9152	9284	int chr_mask = (map215_reg[1] & 0x04) ? 0xff : 0x7f;
9153	9285
9154		chr1_x(machine, chr_page ^ 0, chr_base \| ((vrom_bank[0] & ~0x01) & chr_mask), chr);
9155		chr1_x(machine, chr_page ^ 1, chr_base \| ((vrom_bank[0] \| 0x01) & chr_mask), chr);
9156		chr1_x(machine, chr_page ^ 2, chr_base \| ((vrom_bank[1] & ~0x01) & chr_mask), chr);
9157		chr1_x(machine, chr_page ^ 3, chr_base \| ((vrom_bank[1] \| 0x01) & chr_mask), chr);
9158		chr1_x(machine, chr_page ^ 4, chr_base \| (vrom_bank[2] & chr_mask), chr);
9159		chr1_x(machine, chr_page ^ 5, chr_base \| (vrom_bank[3] & chr_mask), chr);
9160		chr1_x(machine, chr_page ^ 6, chr_base \| (vrom_bank[4] & chr_mask), chr);
9161		chr1_x(machine, chr_page ^ 7, chr_base \| (vrom_bank[5] & chr_mask), chr);
	9286	chr1_x(machine, chr_page ^ 0, chr_base \| ((state->vrom_bank[0] & ~0x01) & chr_mask), chr);
	9287	chr1_x(machine, chr_page ^ 1, chr_base \| ((state->vrom_bank[0] \| 0x01) & chr_mask), chr);
	9288	chr1_x(machine, chr_page ^ 2, chr_base \| ((state->vrom_bank[1] & ~0x01) & chr_mask), chr);
	9289	chr1_x(machine, chr_page ^ 3, chr_base \| ((state->vrom_bank[1] \| 0x01) & chr_mask), chr);
	9290	chr1_x(machine, chr_page ^ 4, chr_base \| (state->vrom_bank[2] & chr_mask), chr);
	9291	chr1_x(machine, chr_page ^ 5, chr_base \| (state->vrom_bank[3] & chr_mask), chr);
	9292	chr1_x(machine, chr_page ^ 6, chr_base \| (state->vrom_bank[4] & chr_mask), chr);
	9293	chr1_x(machine, chr_page ^ 7, chr_base \| (state->vrom_bank[5] & chr_mask), chr);
9162	9294	}
9163	9295
9164	9296	static WRITE8_HANDLER( mapper215_l_w )
9165	9297	{
	9298	nes_state state = (nes_state )space->machine->driver_data;
9166	9299	LOG_MMC(("mapper215_l_w, offset: %04x, data: %02x\n", offset, data));
9167	9300	offset += 0x100;
9168	9301
9169	9302	if (offset == 0x1000)
9170	9303	{
9171	9304	map215_reg[0] = data;
9172		mapper215_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	9305	mapper215_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
9173	9306	}
9174	9307	else if (offset == 0x1001)
9175	9308	{
9176	9309	map215_reg[1] = data;
9177		mapper215_set_chr(space->machine, mmc_chr_source);
	9310	mapper215_set_chr(space->machine, state->mmc_chr_source);
9178	9311	}
9179	9312	else if (offset == 0x1007)
9180	9313	{
9181		mmc_cmd1 = 0;
	9314	state->mmc_cmd1 = 0;
9182	9315	map215_reg[2] = data;
9183		mapper215_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
9184		mapper215_set_chr(space->machine, mmc_chr_source);
	9316	mapper215_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
	9317	mapper215_set_chr(space->machine, state->mmc_chr_source);
9185	9318	}
9186	9319	}
9187	9320
9188	9321	static WRITE8_HANDLER( mapper215_w )
9189	9322	{
	9323	nes_state state = (nes_state )space->machine->driver_data;
9190	9324	UINT8 MMC3_helper, cmd;
9191	9325	static const UINT8 conv_table[8] = {0,2,5,3,6,1,7,4};
9192	9326	LOG_MMC(("mapper215_w, offset: %04x, data: %02x\n", offset, data));
r7955	r7956
9196	9330	switch (offset & 0x6001)
9197	9331	{
9198	9332	case 0x0000:
9199		MMC3_helper = mmc_cmd1 ^ data;
9200		mmc_cmd1 = data;
	9333	MMC3_helper = state->mmc_cmd1 ^ data;
	9334	state->mmc_cmd1 = data;
9201	9335
9202	9336	/* Has PRG Mode changed? */
9203	9337	if (MMC3_helper & 0x40)
9204		mapper215_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	9338	mapper215_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
9205	9339
9206	9340	/* Has CHR Mode changed? */
9207	9341	if (MMC3_helper & 0x80)
9208		mapper215_set_chr(space->machine, mmc_chr_source);
	9342	mapper215_set_chr(space->machine, state->mmc_chr_source);
9209	9343	break;
9210	9344
9211	9345	case 0x0001:
9212		cmd = mmc_cmd1 & 0x07;
	9346	cmd = state->mmc_cmd1 & 0x07;
9213	9347	switch (cmd)
9214	9348	{
9215	9349	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
9216	9350	case 2: case 3: case 4: case 5:
9217		vrom_bank[cmd] = data;
9218		mapper215_set_chr(space->machine, mmc_chr_source);
	9351	state->vrom_bank[cmd] = data;
	9352	mapper215_set_chr(space->machine, state->mmc_chr_source);
9219	9353	break;
9220	9354	case 6:
9221	9355	case 7:
9222		prg_bank[cmd - 6] = data;
9223		mapper215_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	9356	state->prg_bank[cmd - 6] = data;
	9357	mapper215_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
9224	9358	break;
9225	9359	}
9226	9360	break;
r7955	r7956
9238	9372	break;
9239	9373
9240	9374	case 0x0001:
9241		cmd = mmc_cmd1 & 0x07;
	9375	cmd = state->mmc_cmd1 & 0x07;
9242	9376	if (map215_reg[3] && ((map215_reg[0] & 0x80) == 0 \|\| cmd < 6)) // if we use the prg16 banks and cmd=6,7 DON'T enter!
9243	9377	{
9244	9378	map215_reg[3] = 0;
r7955	r7956
9246	9380	{
9247	9381	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
9248	9382	case 2: case 3: case 4: case 5:
9249		vrom_bank[cmd] = data;
9250		mapper215_set_chr(space->machine, mmc_chr_source);
	9383	state->vrom_bank[cmd] = data;
	9384	mapper215_set_chr(space->machine, state->mmc_chr_source);
9251	9385	break;
9252	9386	case 6:
9253	9387	case 7:
9254		prg_bank[cmd - 6] = data;
9255		mapper215_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	9388	state->prg_bank[cmd - 6] = data;
	9389	mapper215_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
9256	9390	break;
9257	9391	}
9258	9392	}
r7955	r7956
9260	9394
9261	9395	case 0x2000:
9262	9396	data = (data & 0xc0) \| conv_table[data & 0x07];
9263		MMC3_helper = mmc_cmd1 ^ data;
9264		mmc_cmd1 = data;
	9397	MMC3_helper = state->mmc_cmd1 ^ data;
	9398	state->mmc_cmd1 = data;
9265	9399
9266	9400	/* Has PRG Mode changed? */
9267	9401	if (MMC3_helper & 0x40)
9268		mapper215_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	9402	mapper215_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
9269	9403
9270	9404	/* Has CHR Mode changed? */
9271	9405	if (MMC3_helper & 0x80)
9272		mapper215_set_chr(space->machine, mmc_chr_source);
	9406	mapper215_set_chr(space->machine, state->mmc_chr_source);
9273	9407
9274	9408	map215_reg[3] = 1;
9275	9409	break;
r7955	r7956
9318	9452
9319	9453	static WRITE8_HANDLER( mapper216_w )
9320	9454	{
	9455	nes_state state = (nes_state )space->machine->driver_data;
9321	9456	LOG_MMC(("mapper216_w, offset: %04x, data: %02x\n", offset, data));
9322	9457
9323	9458	prg32(space->machine, offset);
9324		chr8(space->machine, offset >> 1, mmc_chr_source);
	9459	chr8(space->machine, offset >> 1, state->mmc_chr_source);
9325	9460	}
9326	9461
9327	9462	/*************************************************************
r7955	r7956
9340	9475	// remove mask & base parameters!
9341	9476	static void mapper217_set_prg( running_machine *machine, int prg_base, int prg_mask )
9342	9477	{
9343		mmc_prg_base = (map217_reg[1] & 0x08) ? 0 : (map217_reg[1] & 0x10);
9344		mmc_prg_mask = (map217_reg[1] & 0x08) ? 0x1f : 0x0f;
	9478	nes_state state = (nes_state )machine->driver_data;
	9479	state->mmc_prg_base = (map217_reg[1] & 0x08) ? 0 : (map217_reg[1] & 0x10);
	9480	state->mmc_prg_mask = (map217_reg[1] & 0x08) ? 0x1f : 0x0f;
9345	9481
9346		mmc_prg_base \|= ((map217_reg[1] & 0x03) << 5);
	9482	state->mmc_prg_base \|= ((map217_reg[1] & 0x03) << 5);
9347	9483
9348		mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
	9484	mapper4_set_prg(machine, state->mmc_prg_base, state->mmc_prg_mask);
9349	9485	}
9350	9486
9351	9487	static void mapper217_set_chr( running_machine *machine, UINT8 chr )
9352	9488	{
9353		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	9489	nes_state state = (nes_state )machine->driver_data;
	9490	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
9354	9491	int chr_base = (map217_reg[1] & 0x08) ? 0x00 : ((map217_reg[1] & 0x10) << 3);
9355	9492	int chr_mask = (map217_reg[1] & 0x08) ? 0xff : 0x7f;
9356	9493
9357	9494	chr_base \|= ((map217_reg[1] & 0x03) << 8);
9358	9495
9359		chr1_x(machine, chr_page ^ 0, chr_base \| ((vrom_bank[0] & ~0x01) & chr_mask), chr);
9360		chr1_x(machine, chr_page ^ 1, chr_base \| ((vrom_bank[0] \| 0x01) & chr_mask), chr);
9361		chr1_x(machine, chr_page ^ 2, chr_base \| ((vrom_bank[1] & ~0x01) & chr_mask), chr);
9362		chr1_x(machine, chr_page ^ 3, chr_base \| ((vrom_bank[1] \| 0x01) & chr_mask), chr);
9363		chr1_x(machine, chr_page ^ 4, chr_base \| (vrom_bank[2] & chr_mask), chr);
9364		chr1_x(machine, chr_page ^ 5, chr_base \| (vrom_bank[3] & chr_mask), chr);
9365		chr1_x(machine, chr_page ^ 6, chr_base \| (vrom_bank[4] & chr_mask), chr);
9366		chr1_x(machine, chr_page ^ 7, chr_base \| (vrom_bank[5] & chr_mask), chr);
	9496	chr1_x(machine, chr_page ^ 0, chr_base \| ((state->vrom_bank[0] & ~0x01) & chr_mask), chr);
	9497	chr1_x(machine, chr_page ^ 1, chr_base \| ((state->vrom_bank[0] \| 0x01) & chr_mask), chr);
	9498	chr1_x(machine, chr_page ^ 2, chr_base \| ((state->vrom_bank[1] & ~0x01) & chr_mask), chr);
	9499	chr1_x(machine, chr_page ^ 3, chr_base \| ((state->vrom_bank[1] \| 0x01) & chr_mask), chr);
	9500	chr1_x(machine, chr_page ^ 4, chr_base \| (state->vrom_bank[2] & chr_mask), chr);
	9501	chr1_x(machine, chr_page ^ 5, chr_base \| (state->vrom_bank[3] & chr_mask), chr);
	9502	chr1_x(machine, chr_page ^ 6, chr_base \| (state->vrom_bank[4] & chr_mask), chr);
	9503	chr1_x(machine, chr_page ^ 7, chr_base \| (state->vrom_bank[5] & chr_mask), chr);
9367	9504	}
9368	9505
9369	9506	static WRITE8_HANDLER( mapper217_l_w )
9370	9507	{
	9508	nes_state state = (nes_state )space->machine->driver_data;
9371	9509	UINT8 bank;
9372	9510	LOG_MMC(("mapper217_l_w, offset: %04x, data: %02x\n", offset, data));
9373	9511	offset += 0x100;
r7955	r7956
9382	9520	prg16_cdef(space->machine, bank);
9383	9521	}
9384	9522	else
9385		mapper217_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	9523	mapper217_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
9386	9524	}
9387	9525	else if (offset == 0x1001)
9388	9526	{
9389	9527	map217_reg[1] = data;
9390		mapper217_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	9528	mapper217_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
9391	9529	}
9392	9530	else if (offset == 0x1007)
9393	9531	{
r7955	r7956
9397	9535
9398	9536	static WRITE8_HANDLER( mapper217_w )
9399	9537	{
	9538	nes_state state = (nes_state )space->machine->driver_data;
9400	9539	UINT8 MMC3_helper, cmd;
9401	9540	static const UINT8 conv_table[8] = {0, 6, 3, 7, 5, 2, 4, 1};
9402	9541	LOG_MMC(("mapper217_w, offset: %04x, data: %02x\n", offset, data));
r7955	r7956
9406	9545	switch (offset & 0x6001)
9407	9546	{
9408	9547	case 0x0000:
9409		MMC3_helper = mmc_cmd1 ^ data;
9410		mmc_cmd1 = data;
	9548	MMC3_helper = state->mmc_cmd1 ^ data;
	9549	state->mmc_cmd1 = data;
9411	9550
9412	9551	/* Has PRG Mode changed? */
9413	9552	if (MMC3_helper & 0x40)
9414		mapper217_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	9553	mapper217_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
9415	9554
9416	9555	/* Has CHR Mode changed? */
9417	9556	if (MMC3_helper & 0x80)
9418		mapper217_set_chr(space->machine, mmc_chr_source);
	9557	mapper217_set_chr(space->machine, state->mmc_chr_source);
9419	9558	break;
9420	9559
9421	9560	case 0x0001:
9422		cmd = mmc_cmd1 & 0x07;
	9561	cmd = state->mmc_cmd1 & 0x07;
9423	9562	switch (cmd)
9424	9563	{
9425	9564	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
9426	9565	case 2: case 3: case 4: case 5:
9427		vrom_bank[cmd] = data;
9428		mapper217_set_chr(space->machine, mmc_chr_source);
	9566	state->vrom_bank[cmd] = data;
	9567	mapper217_set_chr(space->machine, state->mmc_chr_source);
9429	9568	break;
9430	9569	case 6:
9431	9570	case 7:
9432		prg_bank[cmd - 6] = data;
9433		mapper217_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	9571	state->prg_bank[cmd - 6] = data;
	9572	mapper217_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
9434	9573	break;
9435	9574	}
9436	9575	break;
r7955	r7956
9450	9589
9451	9590	case 0x0001:
9452	9591	data = (data & 0xc0) \| conv_table[data & 0x07];
9453		MMC3_helper = mmc_cmd1 ^ data;
9454		mmc_cmd1 = data;
	9592	MMC3_helper = state->mmc_cmd1 ^ data;
	9593	state->mmc_cmd1 = data;
9455	9594
9456	9595	/* Has PRG Mode changed? */
9457	9596	if (MMC3_helper & 0x40)
9458		mapper217_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	9597	mapper217_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
9459	9598
9460	9599	/* Has CHR Mode changed? */
9461	9600	if (MMC3_helper & 0x80)
9462		mapper217_set_chr(space->machine, mmc_chr_source);
	9601	mapper217_set_chr(space->machine, state->mmc_chr_source);
9463	9602
9464	9603	map217_reg[3] = 1;
9465	9604	break;
9466	9605
9467	9606	case 0x2000:
9468		cmd = mmc_cmd1 & 0x07;
	9607	cmd = state->mmc_cmd1 & 0x07;
9469	9608	if (map217_reg[3])
9470	9609	{
9471	9610	map217_reg[3] = 0;
r7955	r7956
9473	9612	{
9474	9613	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
9475	9614	case 2: case 3: case 4: case 5:
9476		vrom_bank[cmd] = data;
9477		mapper217_set_chr(space->machine, mmc_chr_source);
	9615	state->vrom_bank[cmd] = data;
	9616	mapper217_set_chr(space->machine, state->mmc_chr_source);
9478	9617	break;
9479	9618	case 6:
9480	9619	case 7:
9481		prg_bank[cmd - 6] = data;
9482		mapper217_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	9620	state->prg_bank[cmd - 6] = data;
	9621	mapper217_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
9483	9622	break;
9484	9623	}
9485	9624	}
r7955	r7956
9558	9697
9559	9698	static WRITE8_HANDLER( mapper221_w )
9560	9699	{
	9700	nes_state state = (nes_state )space->machine->driver_data;
9561	9701	LOG_MMC(("mapper221_w, offset: %04x, data: %02x\n", offset, data));
9562	9702
9563	9703	if (offset < 0x4000)
r7955	r7956
9565	9705	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9566	9706	offset = (offset >> 1) & 0xff;
9567	9707
9568		if (mmc_cmd1 != offset)
	9708	if (state->mmc_cmd1 != offset)
9569	9709	{
9570		mmc_cmd1 = offset;
9571		mapper221_set_prg(space->machine, mmc_cmd1, mmc_cmd2);
	9710	state->mmc_cmd1 = offset;
	9711	mapper221_set_prg(space->machine, state->mmc_cmd1, state->mmc_cmd2);
9572	9712	}
9573	9713	}
9574	9714	else
9575	9715	{
9576	9716	offset &= 0x07;
9577	9717
9578		if (mmc_cmd2 != offset)
	9718	if (state->mmc_cmd2 != offset)
9579	9719	{
9580		mmc_cmd2 = offset;
9581		mapper221_set_prg(space->machine, mmc_cmd1, mmc_cmd2);
	9720	state->mmc_cmd2 = offset;
	9721	mapper221_set_prg(space->machine, state->mmc_cmd1, state->mmc_cmd2);
9582	9722	}
9583	9723	}
9584	9724	}
r7955	r7956
9597	9737	/* Scanline based IRQ ? */
9598	9738	static void mapper222_irq( running_device *device, int scanline, int vblank, int blanked )
9599	9739	{
	9740	nes_state state = (nes_state )device->machine->driver_data;
9600	9741	if (scanline < PPU_BOTTOM_VISIBLE_SCANLINE)
9601	9742	{
9602		if (!IRQ_count \|\| ++IRQ_count < 240)
	9743	if (!state->IRQ_count \|\| ++state->IRQ_count < 240)
9603	9744	return;
9604	9745
9605		IRQ_count = 0;
	9746	state->IRQ_count = 0;
9606	9747	LOG_MMC(("irq fired, scanline: %d (MAME %d, beam pos: %d)\n", scanline,
9607	9748	video_screen_get_vpos(device->machine->primary_screen), video_screen_get_hpos(device->machine->primary_screen)));
9608	9749	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
r7955	r7956
9611	9752
9612	9753	static WRITE8_HANDLER( mapper222_w )
9613	9754	{
	9755	nes_state state = (nes_state )space->machine->driver_data;
9614	9756	UINT8 bank;
9615	9757	LOG_MMC(("mapper222_w, offset: %04x, data: %02x\n", offset, data));
9616	9758
r7955	r7956
9637	9779	chr1_x(space->machine, bank, data, CHRROM);
9638	9780	break;
9639	9781	case 0x7000:
9640		IRQ_count = data;
	9782	state->IRQ_count = data;
9641	9783	break;
9642	9784	}
9643	9785	}
r7955	r7956
9719	9861
9720	9862	static WRITE8_HANDLER( mapper226_w )
9721	9863	{
	9864	nes_state state = (nes_state )space->machine->driver_data;
9722	9865	int hi_bank;
9723	9866	int size_16;
9724	9867	int bank;
r7955	r7956
9726	9869	LOG_MMC(("mapper226_w, offset: %04x, data: %02x\n", offset, data));
9727	9870
9728	9871	if (offset & 0x01)
9729		{
9730		mmc_cmd2 = data;
9731		}
	9872	state->mmc_cmd2 = data;
9732	9873	else
9733		{
9734		mmc_cmd1 = data;
9735		}
	9874	state->mmc_cmd1 = data;
9736	9875
9737		set_nt_mirroring(space->machine, BIT(mmc_cmd1, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9876	set_nt_mirroring(space->machine, BIT(state->mmc_cmd1, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9738	9877
9739		hi_bank = mmc_cmd1 & 0x01;
9740		size_16 = mmc_cmd1 & 0x20;
9741		bank = ((mmc_cmd1 & 0x1e) >> 1) \| ((mmc_cmd1 & 0x80) >> 3) \| ((mmc_cmd2 & 0x01) << 5);
	9878	hi_bank = state->mmc_cmd1 & 0x01;
	9879	size_16 = state->mmc_cmd1 & 0x20;
	9880	bank = ((state->mmc_cmd1 & 0x1e) >> 1) \| ((state->mmc_cmd1 & 0x80) >> 3) \| ((state->mmc_cmd2 & 0x01) << 5);
9742	9881
9743	9882	if (size_16)
9744	9883	{
r7955	r7956
9947	10086
9948	10087	static void mapper232_set_prg( running_machine *machine )
9949	10088	{
9950		prg16_89ab(machine, (mmc_cmd2 & 0x03) \| ((mmc_cmd1 & 0x18) >> 1));
9951		prg16_cdef(machine, 0x03 \| ((mmc_cmd1 & 0x18) >> 1));
	10089	nes_state state = (nes_state )machine->driver_data;
	10090	prg16_89ab(machine, (state->mmc_cmd2 & 0x03) \| ((state->mmc_cmd1 & 0x18) >> 1));
	10091	prg16_cdef(machine, 0x03 \| ((state->mmc_cmd1 & 0x18) >> 1));
9952	10092	}
9953	10093
9954	10094	static WRITE8_HANDLER( mapper232_w )
9955	10095	{
	10096	nes_state state = (nes_state )space->machine->driver_data;
9956	10097	LOG_MMC(("mapper232_w, offset: %04x, data: %02x\n", offset, data));
9957	10098
9958	10099	if (offset < 0x2000)
9959		mmc_cmd1 = data;
	10100	state->mmc_cmd1 = data;
9960	10101	else
9961		mmc_cmd2 = data;
	10102	state->mmc_cmd2 = data;
9962	10103
9963	10104	mapper232_set_prg(space->machine);
9964	10105	}
r7955	r7956
10150	10291
10151	10292	static WRITE8_HANDLER( mapper243_l_w )
10152	10293	{
	10294	nes_state state = (nes_state )space->machine->driver_data;
10153	10295	LOG_MMC(("mapper243_l_w, offset: %04x, data: %02x\n", offset, data));
10154	10296
10155	10297	/* write happens only if we are at 0x4100 + k * 0x200, but 0x4100 is offset = 0 */
10156	10298	if (!(offset & 0x100))
10157	10299	{
10158	10300	if (!(offset & 0x01))
10159		mmc_cmd1 = data;
	10301	state->mmc_cmd1 = data;
10160	10302	else
10161	10303	{
10162		switch (mmc_cmd1 & 0x07)
	10304	switch (state->mmc_cmd1 & 0x07)
10163	10305	{
10164	10306	case 0x00:
10165	10307	prg32(space->machine, 0);
10166	10308	chr8(space->machine, 3, CHRROM);
10167	10309	break;
10168	10310	case 0x02:
10169		vrom_bank[0] = (vrom_bank[0] & ~0x08) \| (data << 3 & 0x08);
10170		chr8(space->machine, vrom_bank[0], CHRROM);
	10311	state->vrom_bank[0] = (state->vrom_bank[0] & ~0x08) \| (data << 3 & 0x08);
	10312	chr8(space->machine, state->vrom_bank[0], CHRROM);
10171	10313	break;
10172	10314	case 0x04:
10173		vrom_bank[0] = (vrom_bank[0] & ~0x01) \| (data << 0 & 0x01);
10174		chr8(space->machine, vrom_bank[0], CHRROM);
	10315	state->vrom_bank[0] = (state->vrom_bank[0] & ~0x01) \| (data << 0 & 0x01);
	10316	chr8(space->machine, state->vrom_bank[0], CHRROM);
10175	10317	break;
10176	10318	case 0x05:
10177	10319	prg32(space->machine, data & 0x01);
10178	10320	break;
10179	10321	case 0x06:
10180		vrom_bank[0] = (vrom_bank[0] & ~0x06) \| (data << 1 & 0x06);
10181		chr8(space->machine, vrom_bank[0], CHRROM);
	10322	state->vrom_bank[0] = (state->vrom_bank[0] & ~0x06) \| (data << 1 & 0x06);
	10323	chr8(space->machine, state->vrom_bank[0], CHRROM);
10182	10324	break;
10183	10325	case 0x07:
10184	10326	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
r7955	r7956
10244	10386	switch (offset & 0x6001)
10245	10387	{
10246	10388	case 0x0001:
10247		cmd = mmc_cmd1 & 0x0f;
	10389	cmd = state->mmc_cmd1 & 0x0f;
10248	10390	switch (cmd)
10249	10391	{
10250		case 0: // in this case we set prg_base in addition to vrom_bank!
10251		mmc_prg_base = (data << 5) & 0x40;
10252		mmc_prg_mask = 0x3f;
10253		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	10392	case 0: // in this case we set prg_base in addition to state->vrom_bank!
	10393	state->mmc_prg_base = (data << 5) & 0x40;
	10394	state->mmc_prg_mask = 0x3f;
	10395	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
10254	10396	case 1: case 2: case 3: case 4: case 5:
10255		vrom_bank[cmd] = data;
	10397	state->vrom_bank[cmd] = data;
10256	10398	if (state->chr_chunks > 0)
10257		mapper4_set_chr(space->machine, CHRROM, mmc_chr_base, mmc_chr_mask);
10258		else // according to Disch's docs, mmc_cmd1&0x80 swaps 4k CHRRAM banks
	10399	mapper4_set_chr(space->machine, CHRROM, state->mmc_chr_base, state->mmc_chr_mask);
	10400	else // according to Disch's docs, state->mmc_cmd1&0x80 swaps 4k CHRRAM banks
10259	10401	{
10260		map245_helper = /(mmc_cmd1 & 0x80) ? 1 : /0;
	10402	map245_helper = /(state->mmc_cmd1 & 0x80) ? 1 : /0;
10261	10403	chr4_0(space->machine, 0 ^ map245_helper, CHRRAM);
10262	10404	chr4_4(space->machine, 1 ^ map245_helper, CHRRAM);
10263	10405	}
10264	10406	break;
10265	10407	case 6:
10266	10408	case 7:
10267		prg_bank[cmd - 6] = data;
10268		mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	10409	state->prg_bank[cmd - 6] = data;
	10410	mapper4_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
10269	10411	break;
10270	10412	}
10271	10413	break;
r7955	r7956
10372	10514
10373	10515	static void mapper249_set_prg( running_machine *machine, int prg_base, int prg_mask )
10374	10516	{
	10517	nes_state state = (nes_state )machine->driver_data;
10375	10518	int i;
10376	10519
10377	10520	if (map249_reg)
10378	10521	{
10379	10522	for (i = 0; i < 4; i ++) // should this apply only to bank[0],bank[1]?
10380	10523	{
10381		prg_bank[i] = ((prg_bank[i] & 0x01)) \| ((prg_bank[i] >> 3) & 0x02) \|
10382		((prg_bank[i] >> 1) & 0x04) \| ((prg_bank[i] << 2) & 0x18);
	10524	state->prg_bank[i] = ((state->prg_bank[i] & 0x01)) \| ((state->prg_bank[i] >> 3) & 0x02) \|
	10525	((state->prg_bank[i] >> 1) & 0x04) \| ((state->prg_bank[i] << 2) & 0x18);
10383	10526	}
10384	10527	}
10385	10528
r7955	r7956
10388	10531
10389	10532	static void mapper249_set_chr( running_machine *machine, int chr_base, int chr_mask )
10390	10533	{
10391		UINT8 chr_page = (mmc_cmd1 & 0x80) >> 5;
	10534	nes_state state = (nes_state )machine->driver_data;
	10535	UINT8 chr_page = (state->mmc_cmd1 & 0x80) >> 5;
10392	10536	int i;
10393	10537
10394	10538	if (map249_reg)
10395	10539	{
10396	10540	for (i = 0; i < 6; i ++)
10397	10541	{
10398		vrom_bank[i] = ((vrom_bank[i] & 0x03)) \| ((vrom_bank[i] >> 1) & 0x04) \|
10399		((vrom_bank[i] >> 4) & 0x08) \| ((vrom_bank[i] >> 2) & 0x10) \|
10400		((vrom_bank[i] << 3) & 0x20) \| ((vrom_bank[i] << 2) & 0xc0);
	10542	state->vrom_bank[i] = ((state->vrom_bank[i] & 0x03)) \| ((state->vrom_bank[i] >> 1) & 0x04) \|
	10543	((state->vrom_bank[i] >> 4) & 0x08) \| ((state->vrom_bank[i] >> 2) & 0x10) \|
	10544	((state->vrom_bank[i] << 3) & 0x20) \| ((state->vrom_bank[i] << 2) & 0xc0);
10401	10545	}
10402	10546	}
10403	10547
10404		chr1_x(machine, chr_page ^ 0, chr_base \| ((vrom_bank[0] & ~0x01) & chr_mask), mmc_chr_source);
10405		chr1_x(machine, chr_page ^ 1, chr_base \| ((vrom_bank[0] \| 0x01) & chr_mask), mmc_chr_source);
10406		chr1_x(machine, chr_page ^ 2, chr_base \| ((vrom_bank[1] & ~0x01) & chr_mask), mmc_chr_source);
10407		chr1_x(machine, chr_page ^ 3, chr_base \| ((vrom_bank[1] \| 0x01) & chr_mask), mmc_chr_source);
10408		chr1_x(machine, chr_page ^ 4, chr_base \| (vrom_bank[2] & chr_mask), mmc_chr_source);
10409		chr1_x(machine, chr_page ^ 5, chr_base \| (vrom_bank[3] & chr_mask), mmc_chr_source);
10410		chr1_x(machine, chr_page ^ 6, chr_base \| (vrom_bank[4] & chr_mask), mmc_chr_source);
10411		chr1_x(machine, chr_page ^ 7, chr_base \| (vrom_bank[5] & chr_mask), mmc_chr_source);
	10548	chr1_x(machine, chr_page ^ 0, chr_base \| ((state->vrom_bank[0] & ~0x01) & chr_mask), state->mmc_chr_source);
	10549	chr1_x(machine, chr_page ^ 1, chr_base \| ((state->vrom_bank[0] \| 0x01) & chr_mask), state->mmc_chr_source);
	10550	chr1_x(machine, chr_page ^ 2, chr_base \| ((state->vrom_bank[1] & ~0x01) & chr_mask), state->mmc_chr_source);
	10551	chr1_x(machine, chr_page ^ 3, chr_base \| ((state->vrom_bank[1] \| 0x01) & chr_mask), state->mmc_chr_source);
	10552	chr1_x(machine, chr_page ^ 4, chr_base \| (state->vrom_bank[2] & chr_mask), state->mmc_chr_source);
	10553	chr1_x(machine, chr_page ^ 5, chr_base \| (state->vrom_bank[3] & chr_mask), state->mmc_chr_source);
	10554	chr1_x(machine, chr_page ^ 6, chr_base \| (state->vrom_bank[4] & chr_mask), state->mmc_chr_source);
	10555	chr1_x(machine, chr_page ^ 7, chr_base \| (state->vrom_bank[5] & chr_mask), state->mmc_chr_source);
10412	10556	}
10413	10557
10414	10558	static WRITE8_HANDLER( mapper249_l_w )
10415	10559	{
	10560	nes_state state = (nes_state )space->machine->driver_data;
10416	10561	LOG_MMC(("mapper249_l_w, offset: %04x, data: %02x\n", offset, data));
10417	10562
10418	10563	offset += 0x100;
r7955	r7956
10420	10565	if (offset == 0x1000)
10421	10566	{
10422	10567	map249_reg = data & 0x02;
10423		mapper249_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
10424		mapper249_set_chr(space->machine, mmc_prg_base, mmc_prg_mask);
	10568	mapper249_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
	10569	mapper249_set_chr(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
10425	10570	}
10426	10571	}
10427	10572
10428	10573	static WRITE8_HANDLER( mapper249_w )
10429	10574	{
	10575	nes_state state = (nes_state )space->machine->driver_data;
10430	10576	UINT8 MMC3_helper, cmd;
10431	10577	LOG_MMC(("mapper249_w, offset: %04x, data: %02x\n", offset, data));
10432	10578
10433	10579	switch (offset & 0x6001)
10434	10580	{
10435	10581	case 0x0000:
10436		MMC3_helper = mmc_cmd1 ^ data;
10437		mmc_cmd1 = data;
	10582	MMC3_helper = state->mmc_cmd1 ^ data;
	10583	state->mmc_cmd1 = data;
10438	10584
10439	10585	/* Has PRG Mode changed? */
10440	10586	if (MMC3_helper & 0x40)
10441		mapper249_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	10587	mapper249_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
10442	10588
10443	10589	/* Has CHR Mode changed? */
10444	10590	if (MMC3_helper & 0x80)
10445		mapper249_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	10591	mapper249_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
10446	10592	break;
10447	10593
10448	10594	case 0x0001:
10449		cmd = mmc_cmd1 & 0x07;
	10595	cmd = state->mmc_cmd1 & 0x07;
10450	10596	switch (cmd)
10451	10597	{
10452	10598	case 0: case 1: // these do not need to be separated: we take care of them in set_chr!
10453	10599	case 2: case 3: case 4: case 5:
10454		vrom_bank[cmd] = data;
10455		mapper249_set_chr(space->machine, mmc_chr_base, mmc_chr_mask);
	10600	state->vrom_bank[cmd] = data;
	10601	mapper249_set_chr(space->machine, state->mmc_chr_base, state->mmc_chr_mask);
10456	10602	break;
10457	10603	case 6:
10458	10604	case 7:
10459		prg_bank[cmd - 6] = data;
10460		mapper249_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
	10605	state->prg_bank[cmd - 6] = data;
	10606	mapper249_set_prg(space->machine, state->mmc_prg_base, state->mmc_prg_mask);
10461	10607	break;
10462	10608	}
10463	10609	break;
r7955	r7956
10515	10661
10516	10662	static WRITE8_HANDLER( mapper252_w )
10517	10663	{
	10664	nes_state state = (nes_state )space->machine->driver_data;
10518	10665	UINT8 mmc_helper, bank;
10519	10666	LOG_MMC(("mapper252_w, offset: %04x, data: %02x\n", offset, data));
10520	10667
r7955	r7956
10533	10680	bank = ((offset & 0x7000) - 0x3000) / 0x0800 + ((offset & 0x0008) >> 3);
10534	10681	mmc_helper = offset & 0x04;
10535	10682	if (mmc_helper)
10536		vrom_bank[bank] = (vrom_bank[bank] & 0x0f) \| ((data & 0x0f) << 4);
	10683	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0x0f) \| ((data & 0x0f) << 4);
10537	10684	else
10538		vrom_bank[bank] = (vrom_bank[bank] & 0xf0) \| (data & 0x0f);
10539		chr1_x(space->machine, bank, vrom_bank[bank], CHRROM);
	10685	state->vrom_bank[bank] = (state->vrom_bank[bank] & 0xf0) \| (data & 0x0f);
	10686	chr1_x(space->machine, bank, state->vrom_bank[bank], CHRROM);
10540	10687	break;
10541	10688	case 0x7000:
10542	10689	switch (offset & 0x0c)
10543	10690	{
10544	10691	case 0x00:
10545		IRQ_count_latch = (IRQ_count_latch & 0xf0) \| (data & 0x0f);
	10692	state->IRQ_count_latch = (state->IRQ_count_latch & 0xf0) \| (data & 0x0f);
10546	10693	break;
10547	10694	case 0x04:
10548		IRQ_count_latch = (IRQ_count_latch & 0x0f) \| ((data & 0x0f) << 4);
	10695	state->IRQ_count_latch = (state->IRQ_count_latch & 0x0f) \| ((data & 0x0f) << 4);
10549	10696	break;
10550	10697	case 0x08:
10551		IRQ_enable = data & 0x02;
10552		IRQ_enable_latch = data & 0x01;
	10698	state->IRQ_enable = data & 0x02;
	10699	state->IRQ_enable_latch = data & 0x01;
10553	10700	if (data & 0x02)
10554		IRQ_count = IRQ_count_latch;
	10701	state->IRQ_count = state->IRQ_count_latch;
10555	10702	break;
10556	10703	case 0x0c:
10557		IRQ_enable = IRQ_enable_latch;
	10704	state->IRQ_enable = state->IRQ_enable_latch;
10558	10705	break;
10559	10706	}
10560	10707	break;

15994 Revisions