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r7953 Saturday 1st May, 2010 at 09:32:53 UTC by Fabio Priuli
[NES] moved some variables to driver data class, plus some small cleanup

[src/mess/includes]	nes.h
[src/mess/machine]	nes.c nes_ines.c nes_mmc.c nes_mmc.h nes_unif.c
[src/mess/video]	nes.c

src/mess/video/nes.c

r7952	r7953
15	15	static int last_frame_flip = 0;
16	16	static double nes_scanlines_per_frame;
17	17
18		static void nes_vh_reset(running_machine *machine)
	18	static void nes_vh_reset( running_machine *machine )
19	19	{
	20	nes_state *state = (nes_state *)machine->driver_data;
20	21	ppu2c0x_set_vidaccess_callback(devtag_get_device(machine,"ppu"), nes_ppu_vidaccess);
21	22	ppu2c0x_set_scanlines_per_frame(devtag_get_device(machine,"ppu"), ceil(nes_scanlines_per_frame));
22	23
23		if (nes.four_screen_vram)
24		{
25		set_nt_mirroring(PPU_MIRROR_4SCREEN);
26		}
	24	if (state->four_screen_vram)
	25	set_nt_mirroring(machine, PPU_MIRROR_4SCREEN);
27	26	else
28	27	{
29		switch(nes.hard_mirroring)
	28	switch(state->hard_mirroring)
30	29	{
31	30	case 0:
32		set_nt_mirroring(PPU_MIRROR_HORZ);
	31	set_nt_mirroring(machine, PPU_MIRROR_HORZ);
33	32	break;
34	33	case 1:
35		set_nt_mirroring(PPU_MIRROR_VERT);
	34	set_nt_mirroring(machine, PPU_MIRROR_VERT);
36	35	break;
37	36	default:
38		set_nt_mirroring(PPU_MIRROR_NONE );
	37	set_nt_mirroring(machine, PPU_MIRROR_NONE);
39	38	break;
40	39	}
41	40	}
r7952	r7953
78	77	nes_state *state = (nes_state *)screen->machine->driver_data;
79	78
80	79	/* render the ppu */
81		ppu2c0x_render( state->ppu, bitmap, 0, 0, 0, 0 );
	80	ppu2c0x_render(state->ppu, bitmap, 0, 0, 0, 0);
82	81
83	82	/* if this is a disk system game, check for the flip-disk key */
84		if (nes.mapper == 20)
	83	if (state->mapper == 20)
85	84	{
86	85	// latch this input so it doesn't go at warp speed
87	86	if ((input_port_read(screen->machine, "FLIPDISK") & 0x01) && (!last_frame_flip))
88	87	{
89	88	last_frame_flip = 1;
90		nes_fds.current_side++;
91		if (nes_fds.current_side > nes_fds.sides)
92		nes_fds.current_side = 0;
	89	state->fds_current_side++;
	90	if (state->fds_current_side > state->fds_sides)
	91	state->fds_current_side = 0;
93	92
94		if (nes_fds.current_side == 0)
95		{
	93	if (state->fds_current_side == 0)
96	94	popmessage("No disk inserted.");
97		}
98	95	else
99		{
100		popmessage("Disk set to side %d", nes_fds.current_side);
101		}
	96	popmessage("Disk set to side %d", state->fds_current_side);
102	97	}
103	98
104	99	if (!(input_port_read(screen->machine, "FLIPDISK") & 0x01))
105		{
106	100	last_frame_flip = 0;
107		}
108	101	}
109	102	return 0;
110	103	}

src/mess/includes/nes.h

r7952	r7953
29	29
30	30	nes_state(running_machine &machine) { }
31	31
	32	/* devices */
32	33	running_device *ppu;
33	34	running_device *sound;
34	35	running_device *cart;
35		};
	36
	37	/***** NES-related *****/
36	38
37
38		/*----------- defined in machine/nes.c -----------*/
39
40		WRITE8_HANDLER ( nes_IN0_w );
41		WRITE8_HANDLER ( nes_IN1_w );
42
43		extern unsigned char *nes_battery_ram;
44
45		struct nes_struct
46		{
47	39	/* load-time cart variables which remain constant */
48	40	UINT8 trainer;
49	41	UINT8 battery;
50	42	UINT16 prg_chunks;   // a recently dumped multigame cart has 256 chunks of both PRG & CHR!
51	43	UINT16 chr_chunks;
52
	44
53	45	UINT8 format;   // 1 = iNES, 2 = UNIF
54
	46
55	47	/* system variables which don't change at run-time */
56	48	UINT16 mapper;      // for iNES
57	49	const char *board;   // for UNIF
r7952	r7953
59	51	UINT8 hard_mirroring;
60	52	UINT8 slow_banking;
61	53	UINT8 crc_hack;   // this is needed to detect different boards sharing the same Mappers (shame on .nes format)
62
	54
63	55	UINT8 *rom;
64	56	UINT8 *vrom;
65	57	UINT8 *vram;
66	58	UINT8 *wram;
67	59	UINT8 *ciram; //PPU nametable RAM - external to PPU!
68
	60
69	61	/* Variables which can change */
70	62	UINT8 mid_ram_enable;
	63
	64
	65
	66	/***** FDS-related *****/
	67
	68	UINT8 *fds_data;
	69	UINT8 fds_sides;
	70	UINT8 *fds_ram;
	71
	72	/* Variables which can change */
	73	UINT8 fds_motor_on;
	74	UINT8 fds_door_closed;
	75	UINT8 fds_current_side;
	76	UINT32 fds_head_position;
	77	UINT8 fds_status0;
	78	UINT8 fds_read_mode;
	79	UINT8 fds_write_reg;
71	80	};
72	81
73		extern struct nes_struct nes;
74	82
75		struct fds_struct
76		{
77		UINT8 *data;
78		UINT8 sides;
79		UINT8 *ram;
	83	/*----------- defined in machine/nes.c -----------*/
80	84
81		/* Variables which can change */
82		UINT8 motor_on;
83		UINT8 door_closed;
84		UINT8 current_side;
85		UINT32 head_position;
86		UINT8 status0;
87		UINT8 read_mode;
88		UINT8 write_reg;
89		};
	85	WRITE8_HANDLER ( nes_IN0_w );
	86	WRITE8_HANDLER ( nes_IN1_w );
90	87
91		extern struct fds_struct nes_fds;
	88	extern unsigned char *nes_battery_ram;
92	89
93	90	/* protos */
94	91
r7952	r7953
107	104
108	105	int nes_ppu_vidaccess( running_device *device, int address, int data );
109	106
110		void nes_partialhash(char *dest, const unsigned char *data,
111		unsigned long length, unsigned int functions);
	107	void nes_partialhash(char *dest, const unsigned char *data, unsigned long length, unsigned int functions);
112	108
113	109	/*----------- defined in video/nes.c -----------*/
114	110

src/mess/machine/nes.c

r7952	r7953
43	43	unsigned char *nes_battery_ram;
44	44	static UINT8 battery_data[BATTERY_SIZE];
45	45
46		struct nes_struct nes;
47		struct fds_struct nes_fds;
48
49	46	static nes_input in_0;
50	47	static nes_input in_1;
51	48
r7952	r7953
60	57	FUNCTIONS
61	58	***************************************************************************/
62	59
63		static running_device *cartslot_image( running_machine *machine )
	60	static void init_nes_core( running_machine *machine )
64	61	{
65	62	nes_state *state = (nes_state *)machine->driver_data;
66		return state->cart;
67		}
68
69		static void init_nes_core( running_machine *machine )
70		{
71	63	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
72	64
73	65	/* We set these here in case they weren't set in the cart loader */
74		nes.rom = memory_region(machine, "maincpu");
75		nes.vrom = memory_region(machine, "gfx1");
76		nes.vram = memory_region(machine, "gfx2");
77		nes.ciram = memory_region(machine, "gfx3");
78		nes.wram = memory_region(machine, "user1");
	66	state->rom = memory_region(machine, "maincpu");
	67	state->vrom = memory_region(machine, "gfx1");
	68	state->vram = memory_region(machine, "gfx2");
	69	state->ciram = memory_region(machine, "gfx3");
	70	state->wram = memory_region(machine, "user1");
79	71
80		/* Brutal hack put in as a consequence of the new memory system; we really
81		need to fix the NES code */
	72	/* Brutal hack put in as a consequence of the new memory system; we really need to fix the NES code */
82	73	memory_install_readwrite_bank(space, 0x0000, 0x07ff, 0, 0x1800, "bank10");
83	74
84	75	memory_install_readwrite8_handler(cpu_get_address_space(devtag_get_device(machine, "ppu"), ADDRESS_SPACE_PROGRAM), 0, 0x1fff, 0, 0, nes_chr_r, nes_chr_w);
85	76	memory_install_readwrite8_handler(cpu_get_address_space(devtag_get_device(machine, "ppu"), ADDRESS_SPACE_PROGRAM), 0x2000, 0x3eff, 0, 0, nes_nt_r, nes_nt_w);
86	77
87		memory_set_bankptr(machine, "bank10", nes.rom);
	78	memory_set_bankptr(machine, "bank10", state->rom);
88	79
89		nes_battery_ram = nes.wram;
	80	nes_battery_ram = state->wram;
90	81
91	82	/* Set up the memory handlers for the mapper */
92		switch (nes.mapper)
	83	switch (state->mapper)
93	84	{
94	85	case 20:
95		nes.slow_banking = 0;
96		/* If we are loading a disk we have already filled nes_fds.data and we don't want to overwrite it,
	86	state->slow_banking = 0;
	87	/* If we are loading a disk we have already filled state->fds_data and we don't want to overwrite it,
97	88	if we are loading a cart image identified as mapper 20 (probably wrong mapper...) we need to alloc
98	89	memory for the bank 2 pointer */
99		if (nes_fds.data == NULL)
100		nes_fds.data = auto_alloc_array(machine, UINT8, 0x8000 );
	90	if (state->fds_data == NULL)
	91	state->fds_data = auto_alloc_array(machine, UINT8, 0x8000);
101	92	memory_install_read8_handler(space, 0x4030, 0x403f, 0, 0, nes_fds_r);
102	93	memory_install_read_bank(space, 0x6000, 0xdfff, 0, 0, "bank2");
103	94	memory_install_read_bank(space, 0xe000, 0xffff, 0, 0, "bank1");
r7952	r7953
105	96	memory_install_write8_handler(space, 0x4020, 0x402f, 0, 0, nes_fds_w);
106	97	memory_install_write_bank(space, 0x6000, 0xdfff, 0, 0, "bank2");
107	98
108		memory_set_bankptr(machine, "bank1", &nes.rom[0xe000]);
109		memory_set_bankptr(machine, "bank2", nes_fds.data );
	99	memory_set_bankptr(machine, "bank1", &state->rom[0xe000]);
	100	memory_set_bankptr(machine, "bank2", state->fds_data);
110	101	break;
111	102	case 50:
112	103	memory_install_write8_handler(space, 0x4020, 0x403f, 0, 0, nes_mapper50_add_w);
113	104	memory_install_write8_handler(space, 0x40a0, 0x40bf, 0, 0, nes_mapper50_add_w);
114	105	default:
115		nes.slow_banking = 0;
	106	state->slow_banking = 0;
116	107	memory_install_read_bank(space, 0x6000, 0x7fff, 0, 0, "bank5");
117	108	memory_install_read_bank(space, 0x8000, 0x9fff, 0, 0, "bank1");
118	109	memory_install_read_bank(space, 0xa000, 0xbfff, 0, 0, "bank2");
r7952	r7953
130	121	}
131	122
132	123	/* Set up the mapper callbacks */
133		if (nes.format == 1)
	124	if (state->format == 1)
134	125	{
135	126	mmc_intf intf = { 0 };
136	127	const mmc *mapper;
137	128
138		mapper = nes_mapper_lookup(nes.mapper);
	129	mapper = nes_mapper_lookup(state->mapper);
139	130	if (mapper)
140	131	{
141	132	intf.mmc_write_low = mapper->mmc_write_low;
r7952	r7953
147	138	}
148	139	else
149	140	{
150		logerror("Mapper %d is not yet supported, defaulting to no mapper.\n",nes.mapper);
	141	logerror("Mapper %d is not yet supported, defaulting to no mapper.\n",state->mapper);
151	142	nes_mapper_init(&intf);
152	143	}
153	144	}
154		else if (nes.format == 2)
	145	else if (state->format == 2)
155	146	{
156	147	mmc_intf intf = { 0 };
157	148	const unif *board;
158	149
159		board = nes_unif_lookup(nes.board);
	150	board = nes_unif_lookup(state->board);
160	151	if (board)
161	152	{
162	153	intf.mmc_write_low = board->mmc_write_low;
r7952	r7953
168	159	}
169	160	else
170	161	{
171		logerror("Board %s is not yet supported, defaulting to no mapper.\n", nes.board);
	162	logerror("Board %s is not yet supported, defaulting to no mapper.\n", state->board);
172	163	nes_mapper_init(&intf);
173	164	ppu_latch = NULL;
174	165	}
r7952	r7953
176	167
177	168	/* Load a battery file, but only if there's no trainer since they share */
178	169	/* overlapping memory. */
179		if (nes.trainer)
	170	if (state->trainer)
180	171	return;
181	172
182	173	/* We need this because battery ram is loaded before the */
r7952	r7953
188	179
189	180	int nes_ppu_vidaccess( running_device *device, int address, int data )
190	181	{
	182	nes_state *state = (nes_state *)device->machine->driver_data;
	183
191	184	/* TODO: this is a bit of a hack, needed to get Argus, ASO, etc to work */
192	185	/* but, B-Wings, submath (j) seem to use this location differently... */
193		if (nes.chr_chunks && (address & 0x3fff) < 0x2000)
	186	if (state->chr_chunks && (address & 0x3fff) < 0x2000)
194	187	{
195	188	//      int vrom_loc;
196	189	//      vrom_loc = (nes_vram[(address & 0x1fff) >> 10] * 16) + (address & 0x3ff);
197		//      data = nes.vrom [vrom_loc];
	190	//      data = state->vrom [vrom_loc];
198	191	}
199	192	return data;
200	193	}
r7952	r7953
208	201	state->cart = devtag_get_device(machine, "cart");
209	202
210	203	/* Some carts have extra RAM and require it on at startup, e.g. Metroid */
211		nes.mid_ram_enable = 1;
	204	state->mid_ram_enable = 1;
212	205
213	206	/* Reset the mapper variables. Will also mark the char-gen ram as dirty */
214		if (nes.format == 1)
215		nes_mapper_reset(machine, nes.mapper);
	207	if (state->format == 1)
	208	nes_mapper_reset(machine, state->mapper);
216	209
217		if (nes.format == 2)
218		nes_unif_reset(machine, nes.board);
	210	if (state->format == 2)
	211	nes_unif_reset(machine, state->board);
219	212
220	213	/* Reset the serial input ports */
221	214	in_0.shift = 0;
r7952	r7953
242	235
243	236	static void nes_machine_stop( running_machine *machine )
244	237	{
	238	nes_state *state = (nes_state *)machine->driver_data;
	239
245	240	/* Write out the battery file if necessary */
246		if (nes.battery)
247		image_battery_save(cartslot_image(machine), nes_battery_ram, BATTERY_SIZE);
	241	if (state->battery)
	242	image_battery_save(state->cart, nes_battery_ram, BATTERY_SIZE);
248	243	}
249	244
250	245
r7952	r7953
462	457
463	458	DEVICE_IMAGE_LOAD( nes_cart )
464	459	{
	460	nes_state *state = (nes_state *)image->machine->driver_data;
465	461	const char *mapinfo;
466	462	int mapint1 = 0, mapint2 = 0, mapint3 = 0, mapint4 = 0, goodcrcinfo = 0;
467	463	char magic[4];
r7952	r7953
477	473
478	474	if ((magic[0] == 'N') && (magic[1] == 'E') && (magic[2] == 'S'))   /* If header starts with 'NES' it is iNES */
479	475	{
480		nes.format = 1;   // we use this to select between mapper_reset / unif_reset
	476	state->format = 1;   // we use this to select between mapper_reset / unif_reset
481	477
482	478	mapinfo = image_extrainfo(image);
483	479
r7952	r7953
485	481	{
486	482	if (4 == sscanf(mapinfo,"%d %d %d %d", &mapint1, &mapint2, &mapint3, &mapint4))
487	483	{
488		nes.mapper = mapint1;
	484	state->mapper = mapint1;
489	485	local_options = mapint2 & 0x0f;
490		nes.crc_hack = mapint2 & 0xf0;   // this is used to differentiate among variants of the same Mapper (see nes_mmc.c)
491		nes.prg_chunks = mapint3;
492		nes.chr_chunks = mapint4;
	486	state->crc_hack = mapint2 & 0xf0;   // this is used to differentiate among variants of the same Mapper (see nes_mmc.c)
	487	state->prg_chunks = mapint3;
	488	state->chr_chunks = mapint4;
493	489	logerror("NES.HSI info: %d %d %d %d\n", mapint1, mapint2, mapint3, mapint4);
494	490	goodcrcinfo = 1;
495	491	}
r7952	r7953
509	505	// Let's skip past the magic header once again.
510	506	image_fseek(image, 4, SEEK_SET);
511	507
512		image_fread(image, &nes.prg_chunks, 1);
513		image_fread(image, &nes.chr_chunks, 1);
	508	image_fread(image, &state->prg_chunks, 1);
	509	image_fread(image, &state->chr_chunks, 1);
514	510	/* Read the first ROM option byte (offset 6) */
515	511	image_fread(image, &m, 1);
516	512
517	513	/* Interpret the iNES header flags */
518		nes.mapper = (m & 0xf0) >> 4;
	514	state->mapper = (m & 0xf0) >> 4;
519	515	local_options = m & 0x0f;
520	516
521	517	/* Read the second ROM option byte (offset 7) */
r7952	r7953
536	532	}
537	533	logerror("\n");
538	534
539		nes.mapper = nes.mapper | (m & 0xf0);
	535	state->mapper = state->mapper | (m & 0xf0);
540	536	}
541	537
542		nes.hard_mirroring = local_options & 0x01;
543		nes.battery = local_options & 0x02;
544		nes.trainer = local_options & 0x04;
545		nes.four_screen_vram = local_options & 0x08;
	538	state->hard_mirroring = local_options & 0x01;
	539	state->battery = local_options & 0x02;
	540	state->trainer = local_options & 0x04;
	541	state->four_screen_vram = local_options & 0x08;
546	542
547		if (nes.battery)
	543	if (state->battery)
548	544	logerror("-- Battery found\n");
549	545
550		if (nes.trainer)
	546	if (state->trainer)
551	547	logerror("-- Trainer found\n");
552	548
553		if (nes.four_screen_vram)
	549	if (state->four_screen_vram)
554	550	logerror("-- 4-screen VRAM\n");
555	551
556	552	/* Free the regions that were allocated by the ROM loader */
r7952	r7953
558	554	memory_region_free(image->machine, "gfx1");
559	555
560	556	/* Allocate them again with the proper size */
561		memory_region_alloc(image->machine, "maincpu", 0x10000 + (nes.prg_chunks + 1) * 0x4000,0);
562		if (nes.chr_chunks)
563		memory_region_alloc(image->machine, "gfx1", nes.chr_chunks * 0x2000,0);
	557	memory_region_alloc(image->machine, "maincpu", 0x10000 + (state->prg_chunks + 1) * 0x4000,0);
	558	if (state->chr_chunks)
	559	memory_region_alloc(image->machine, "gfx1", state->chr_chunks * 0x2000,0);
564	560
565		nes.rom = memory_region(image->machine, "maincpu");
566		nes.vrom = memory_region(image->machine, "gfx1");
567		nes.vram = memory_region(image->machine, "gfx2");
568		nes.wram = memory_region(image->machine, "user1");
	561	state->rom = memory_region(image->machine, "maincpu");
	562	state->vrom = memory_region(image->machine, "gfx1");
	563	state->vram = memory_region(image->machine, "gfx2");
	564	state->wram = memory_region(image->machine, "user1");
569	565
570	566	/* Position past the header */
571	567	image_fseek(image, 16, SEEK_SET);
572	568
573	569	/* Load the 0x200 byte trainer at 0x7000 if it exists */
574		if (nes.trainer)
575		image_fread(image, &nes.wram[0x1000], 0x200);
	570	if (state->trainer)
	571	image_fread(image, &state->wram[0x1000], 0x200);
576	572
577	573	/* Read in the program chunks */
578		if (nes.prg_chunks == 1)
	574	if (state->prg_chunks == 1)
579	575	{
580		image_fread(image, &nes.rom[0x14000], 0x4000);
	576	image_fread(image, &state->rom[0x14000], 0x4000);
581	577	/* Mirror this bank into $8000 */
582		memcpy(&nes.rom[0x10000], &nes.rom [0x14000], 0x4000);
	578	memcpy(&state->rom[0x10000], &state->rom [0x14000], 0x4000);
583	579	}
584	580	else
585		image_fread(image, &nes.rom[0x10000], 0x4000 * nes.prg_chunks);
	581	image_fread(image, &state->rom[0x10000], 0x4000 * state->prg_chunks);
586	582
587	583	#if SPLIT_PRG
588	584	{
589	585	FILE *prgout;
590	586	char outname[255];
591	587
592		for (i = 0; i < nes.prg_chunks; i ++)
	588	for (i = 0; i < state->prg_chunks; i ++)
593	589	{
594	590	sprintf(outname, "%s.p%d", image_filename(image), i);
595	591	prgout = fopen(outname, "wb");
596	592	if (prgout)
597	593	{
598		fwrite(&nes.rom[0x10000 + 0x4000 * i], 1, 0x4000, prgout);
	594	fwrite(&state->rom[0x10000 + 0x4000 * i], 1, 0x4000, prgout);
599	595	fclose(prgout);
600	596	}
601	597	}
r7952	r7953
603	599	#endif /* SPLIT_PRG */
604	600
605	601	logerror("**\n");
606		logerror("Mapper: %d\n", nes.mapper);
607		logerror("PRG chunks: %02x, size: %06x\n", nes.prg_chunks, 0x4000 * nes.prg_chunks);
608		//      printf("Mapper: %d\n", nes.mapper);
609		//      printf("PRG chunks: %02x, size: %06x\n", nes.prg_chunks, 0x4000 * nes.prg_chunks);
	602	logerror("Mapper: %d\n", state->mapper);
	603	logerror("PRG chunks: %02x, size: %06x\n", state->prg_chunks, 0x4000 * state->prg_chunks);
	604	//      printf("Mapper: %d\n", state->mapper);
	605	//      printf("PRG chunks: %02x, size: %06x\n", state->prg_chunks, 0x4000 * state->prg_chunks);
610	606
611	607	/* Read in any chr chunks */
612		if (nes.chr_chunks > 0)
	608	if (state->chr_chunks > 0)
613	609	{
614		image_fread(image, nes.vrom, nes.chr_chunks * 0x2000);
615		if (nes.mapper == 2)
	610	image_fread(image, state->vrom, state->chr_chunks * 0x2000);
	611	if (state->mapper == 2)
616	612	logerror("Warning: VROM has been found in VRAM-based mapper. Either the mapper is set wrong or the ROM image is incorrect.\n");
617	613	}
618	614
r7952	r7953
621	617	FILE *chrout;
622	618	char outname[255];
623	619
624		for (i = 0; i < nes.chr_chunks; i ++)
	620	for (i = 0; i < state->chr_chunks; i ++)
625	621	{
626	622	sprintf(outname, "%s.c%d", image_filename(image), i);
627	623	chrout= fopen(outname, "wb");
628	624	if (chrout)
629	625	{
630		fwrite(&nes.rom[0x10000 + 0x2000 * i], 1, 0x2000, chrout);
	626	fwrite(&state->rom[0x10000 + 0x2000 * i], 1, 0x2000, chrout);
631	627	fclose(chrout);
632	628	}
633	629	}
634	630	}
635	631	#endif /* SPLIT_CHR */
636	632
637		logerror("CHR chunks: %02x, size: %06x\n", nes.chr_chunks, 0x4000 * nes.chr_chunks);
	633	logerror("CHR chunks: %02x, size: %06x\n", state->chr_chunks, 0x4000 * state->chr_chunks);
638	634	logerror("**\n");
639		//      printf("CHR chunks: %02x, size: %06x\n", nes.chr_chunks, 0x4000 * nes.chr_chunks);
	635	//      printf("CHR chunks: %02x, size: %06x\n", state->chr_chunks, 0x4000 * state->chr_chunks);
640	636	//      printf("**\n");
641	637
642	638	/* Attempt to load a battery file for this ROM. If successful, we */
643	639	/* must wait until later to move it to the system memory. */
644		if (nes.battery)
	640	if (state->battery)
645	641	image_battery_load(image, battery_data, BATTERY_SIZE, 0x00);
646	642
647	643	}
r7952	r7953
658	654	const unif *unif_board;
659	655	int mapr_chunk_found = 0;
660	656
661		nes.format = 2;   // we use this to select between mapper_reset / unif_reset
	657	state->format = 2;   // we use this to select between mapper_reset / unif_reset
662	658
663	659	image_fread(image, &buffer, 4);
664	660	unif_ver = buffer[0] | (buffer[1] << 8) | (buffer[2] << 16) | (buffer[3] << 24);
r7952	r7953
711	707	//                            logerror("Unsupported UNIF board %s.\n", unif_mapr);
712	708	}
713	709
714		nes.mapper = 0;   // this allows us to set up memory handlers without duplicating code (for the moment)
715		nes.board = unif_board->board;
716		nes.prg_chunks = unif_board->prgrom;
717		nes.chr_chunks = unif_board->chrrom;
718		nes.battery = unif_board->wram;   // we should implement WRAM banks...
719		//                  nes.hard_mirroring = unif_board->nt;
720		//                      nes.four_screen_vram = ;
	710	state->mapper = 0;   // this allows us to set up memory handlers without duplicating code (for the moment)
	711	state->board = unif_board->board;
	712	state->prg_chunks = unif_board->prgrom;
	713	state->chr_chunks = unif_board->chrrom;
	714	state->battery = unif_board->wram;   // we should implement WRAM banks...
	715	//                  state->hard_mirroring = unif_board->nt;
	716	//                      state->four_screen_vram = ;
721	717
722	718	/* Free the regions that were allocated by the ROM loader */
723	719	memory_region_free(image->machine, "maincpu");
724	720	memory_region_free(image->machine, "gfx1");
725	721
726	722	/* Allocate them again with the proper size */
727		memory_region_alloc(image->machine, "maincpu", 0x10000 + (nes.prg_chunks + 1) * 0x4000, 0);
728		if (nes.chr_chunks)
729		memory_region_alloc(image->machine, "gfx1", nes.chr_chunks * 0x2000, 0);
	723	memory_region_alloc(image->machine, "maincpu", 0x10000 + (state->prg_chunks + 1) * 0x4000, 0);
	724	if (state->chr_chunks)
	725	memory_region_alloc(image->machine, "gfx1", state->chr_chunks * 0x2000, 0);
730	726
731		nes.rom = memory_region(image->machine, "maincpu");
732		nes.vrom = memory_region(image->machine, "gfx1");
733		nes.vram = memory_region(image->machine, "gfx2");
734		nes.wram = memory_region(image->machine, "user1");
	727	state->rom = memory_region(image->machine, "maincpu");
	728	state->vrom = memory_region(image->machine, "gfx1");
	729	state->vram = memory_region(image->machine, "gfx2");
	730	state->wram = memory_region(image->machine, "user1");
735	731
736	732	/* for validation purposes */
737	733	prg_left = unif_board->prgrom * 0x4000;
r7952	r7953
864	860	fatalerror("PRG chunks larger than expected by board %s!\n", unif_mapr);
865	861
866	862	/* Read in the program chunks */
867		if (nes.prg_chunks == 1)
	863	if (state->prg_chunks == 1)
868	864	{
869		image_fread(image, &nes.rom[0x14000], chunk_length);
	865	image_fread(image, &state->rom[0x14000], chunk_length);
870	866	/* Mirror the only bank into $8000 */
871		memcpy(&nes.rom[0x10000], &nes.rom[0x14000], chunk_length);
	867	memcpy(&state->rom[0x10000], &state->rom[0x14000], chunk_length);
872	868	}
873	869	else
874		image_fread(image, &nes.rom[0x10000 + prg_start], chunk_length);
	870	image_fread(image, &state->rom[0x10000 + prg_start], chunk_length);
875	871
876	872	prg_start += chunk_length;
877	873	read_length += (chunk_length + 8);
r7952	r7953
889	885	fatalerror("CHR chunks larger than expected by board %s!\n", unif_mapr);
890	886
891	887	/* Read in the vrom chunks */
892		image_fread(image, nes.vrom + chr_start, chunk_length);
	888	image_fread(image, state->vrom + chr_start, chunk_length);
893	889
894	890	chr_start += chunk_length;
895	891	read_length += (chunk_length + 8);
r7952	r7953
926	922	}
927	923
928	924
929		static void nes_load_proc(running_device *image)
	925	static void nes_load_proc( running_device *image )
930	926	{
	927	nes_state *state = (nes_state *)image->machine->driver_data;
931	928	int header = 0;
932		nes_fds.sides = 0;
	929	state->fds_sides = 0;
933	930
934	931	if (image_length(image) % 65500)
935	932	header = 0x10;
936	933
937	934	image_fseek(image, 0, SEEK_END);
938		nes_fds.sides = (image_ftell(image) - header) / 65500;
939		nes_fds.data = (UINT8*)image_malloc(image, nes_fds.sides * 65500);
	935	state->fds_sides = (image_ftell(image) - header) / 65500;
	936	state->fds_data = (UINT8*)image_malloc(image, state->fds_sides * 65500);
940	937
941	938	/* if there is an header, skip it */
942	939	image_fseek(image, header, SEEK_SET);
943	940
944		image_fread(image, nes_fds.data, 65500 * nes_fds.sides);
	941	image_fread(image, state->fds_data, 65500 * state->fds_sides);
945	942	return;
946	943	}
947	944
948		static void nes_unload_proc(running_device *image)
	945	static void nes_unload_proc( running_device *image )
949	946	{
	947	nes_state *state = (nes_state *)image->machine->driver_data;
	948
950	949	/* TODO: should write out changes here as well */
951		nes_fds.sides =  0;
	950	state->fds_sides =  0;
952	951	}
953	952
954	953	DRIVER_INIT( famicom )
955	954	{
	955	nes_state *state = (nes_state *)machine->driver_data;
	956
956	957	/* clear some of the cart variables we don't use */
957		nes.trainer = 0;
958		nes.battery = 0;
959		nes.prg_chunks = nes.chr_chunks = 0;
	958	state->trainer = 0;
	959	state->battery = 0;
	960	state->prg_chunks = state->chr_chunks = 0;
960	961
961	962	/* initialize the system as if using a mapper 20 cart */
962		nes.format = 1;
963		nes.mapper = 20;
964		nes.four_screen_vram = 0;
965		nes.hard_mirroring = 0;
	963	state->format = 1;
	964	state->mapper = 20;
	965	state->four_screen_vram = 0;
	966	state->hard_mirroring = 0;
966	967
967		nes_fds.sides = 0;
968		nes_fds.data = NULL;
	968	state->fds_sides = 0;
	969	state->fds_data = NULL;
969	970
970	971	floppy_install_load_proc(floppy_get_device(machine,0), nes_load_proc);
971	972	floppy_install_unload_proc(floppy_get_device(machine,0), nes_unload_proc);

src/mess/machine/nes_unif.c

r7952	r7953
57	57	break;
58	58	}
59	59	if (offset == 0x1000)   /* reg[0] also sets mirroring */
60		set_nt_mirroring((data & 0x20) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	60	set_nt_mirroring(space->machine, BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
61	61	}
62	62
63	63	static WRITE8_HANDLER( bmc_64in1nr_w )
r7952	r7953
81	81	{
82	82	LOG_MMC(("bmc_190in1_w offset: %04x, data: %02x\n", offset, data));
83	83
84		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	84	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
85	85	data >>= 2;
86	86	prg16_89ab(space->machine, data);
87	87	prg16_cdef(space->machine, data);
r7952	r7953
104	104	LOG_MMC(("bmc_a65as_w offset: %04x, data: %02x\n", offset, data));
105	105
106	106	if (data & 0x80)
107		set_nt_mirroring((data & 0x20) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	107	set_nt_mirroring(space->machine, BIT(data, 5) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
108	108	else
109		set_nt_mirroring((data & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	109	set_nt_mirroring(space->machine, BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
110	110
111	111	if (data & 0x40)
112	112	prg32(space->machine, data >> 1);
r7952	r7953
286	286	else
287	287	{
288	288	mmc_cmd2 = 1;
289		set_nt_mirroring((offset & 0x02) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	289	set_nt_mirroring(space->machine, BIT(data, 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
290	290	mmc_helper = ((offset >> 3) & 0x20) | ((offset >> 2) & 0x18);
291	291	mmc_cmd1 = mmc_helper | (mmc_cmd1 & 0x07);
292	292	prg16_89ab(space->machine, mmc_cmd1);
r7952	r7953
317	317	if (!mmc_cmd1)
318	318	{
319	319	mmc_cmd1 = data & 0x20;
320		set_nt_mirroring((data & 0x10) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	320	set_nt_mirroring(space->machine, BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
321	321	mmc_helper = (~data & 0x08) >> 3;
322	322	prg16_89ab(space->machine, data & ~mmc_helper);
323	323	prg16_cdef(space->machine, data |  mmc_helper);
r7952	r7953
473	473
474	474	case 0x0000:
475	475	case 0x1000:
476		set_nt_mirroring((data | (data >> 7)) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	476	set_nt_mirroring(space->machine, (data | (data >> 7)) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
477	477	break;
478	478
479	479	case 0x6000:
r7952	r7953
515	515	unl_ax5705_set_prg(space->machine);
516	516	break;
517	517	case 0x0008:
518		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	518	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
519	519	break;
520	520	case 0x2000:
521	521	prg_bank[1] = (data & 0x05) | ((data & 0x08) >> 2) | ((data & 0x02) << 2);
r7952	r7953
572	572	{
573	573	LOG_MMC(("unl_cc21_w offset: %04x, data: %02x\n", offset, data));
574	574
575		set_nt_mirroring((offset & 0x02) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	575	set_nt_mirroring(space->machine, BIT(data, 1) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
576	576	chr8(space->machine, (offset & 0x01), CHRROM);
577	577	}
578	578

src/mess/machine/nes_mmc.c

r7952	r7953
351	351
352	352	WRITE8_HANDLER( nes_mid_mapper_w )
353	353	{
	354	nes_state *state = (nes_state *)space->machine->driver_data;
	355
354	356	if (mmc_write_mid)
355	357	(*mmc_write_mid)(space, offset, data);
356		else if (nes.mid_ram_enable)
	358	else if (state->mid_ram_enable)
357	359	nes_battery_ram[offset] = data;
358	360	else
359	361	{
r7952	r7953
370	372
371	373	READ8_HANDLER( nes_mid_mapper_r )
372	374	{
373		if ((nes.mid_ram_enable) || (nes.mapper == 5))
	375	nes_state *state = (nes_state *)space->machine->driver_data;
	376
	377	if ((state->mid_ram_enable) || (state->mapper == 5))
374	378	return nes_battery_ram[offset];
375	379	else
376	380	return 0;
r7952	r7953
404	408
405	409	static void prg32( running_machine *machine, int bank )
406	410	{
	411	nes_state *state = (nes_state *)machine->driver_data;
	412
407	413	/* assumes that bank references a 32k chunk */
408		bank &= ((nes.prg_chunks >> 1) - 1);
409		if (nes.slow_banking)
410		memcpy(&nes.rom[0x8000], &nes.rom[bank * 0x8000 + 0x10000], 0x8000);
	414	bank &= ((state->prg_chunks >> 1) - 1);
	415	if (state->slow_banking)
	416	memcpy(&state->rom[0x8000], &state->rom[bank * 0x8000 + 0x10000], 0x8000);
411	417	else
412	418	{
413		memory_set_bankptr(machine, "bank1", &nes.rom[bank * 0x8000 + 0x10000]);
414		memory_set_bankptr(machine, "bank2", &nes.rom[bank * 0x8000 + 0x12000]);
415		memory_set_bankptr(machine, "bank3", &nes.rom[bank * 0x8000 + 0x14000]);
416		memory_set_bankptr(machine, "bank4", &nes.rom[bank * 0x8000 + 0x16000]);
	419	memory_set_bankptr(machine, "bank1", &state->rom[bank * 0x8000 + 0x10000]);
	420	memory_set_bankptr(machine, "bank2", &state->rom[bank * 0x8000 + 0x12000]);
	421	memory_set_bankptr(machine, "bank3", &state->rom[bank * 0x8000 + 0x14000]);
	422	memory_set_bankptr(machine, "bank4", &state->rom[bank * 0x8000 + 0x16000]);
417	423	}
418	424	}
419	425
420	426	static void prg16_89ab( running_machine *machine, int bank )
421	427	{
	428	nes_state *state = (nes_state *)machine->driver_data;
	429
422	430	/* assumes that bank references a 16k chunk */
423		bank &= (nes.prg_chunks - 1);
424		if (nes.slow_banking)
425		memcpy(&nes.rom[0x8000], &nes.rom[bank * 0x4000 + 0x10000], 0x4000);
	431	bank &= (state->prg_chunks - 1);
	432	if (state->slow_banking)
	433	memcpy(&state->rom[0x8000], &state->rom[bank * 0x4000 + 0x10000], 0x4000);
426	434	else
427	435	{
428		memory_set_bankptr(machine, "bank1", &nes.rom[bank * 0x4000 + 0x10000]);
429		memory_set_bankptr(machine, "bank2", &nes.rom[bank * 0x4000 + 0x12000]);
	436	memory_set_bankptr(machine, "bank1", &state->rom[bank * 0x4000 + 0x10000]);
	437	memory_set_bankptr(machine, "bank2", &state->rom[bank * 0x4000 + 0x12000]);
430	438	}
431	439	}
432	440
433	441	static void prg16_cdef( running_machine *machine, int bank )
434	442	{
	443	nes_state *state = (nes_state *)machine->driver_data;
	444
435	445	/* assumes that bank references a 16k chunk */
436		bank &= (nes.prg_chunks - 1);
437		if (nes.slow_banking)
438		memcpy(&nes.rom[0xc000], &nes.rom[bank * 0x4000 + 0x10000], 0x4000);
	446	bank &= (state->prg_chunks - 1);
	447	if (state->slow_banking)
	448	memcpy(&state->rom[0xc000], &state->rom[bank * 0x4000 + 0x10000], 0x4000);
439	449	else
440	450	{
441		memory_set_bankptr(machine, "bank3", &nes.rom[bank * 0x4000 + 0x10000]);
442		memory_set_bankptr(machine, "bank4", &nes.rom[bank * 0x4000 + 0x12000]);
	451	memory_set_bankptr(machine, "bank3", &state->rom[bank * 0x4000 + 0x10000]);
	452	memory_set_bankptr(machine, "bank4", &state->rom[bank * 0x4000 + 0x12000]);
443	453	}
444	454	}
445	455
446	456	static void prg8_89( running_machine *machine, int bank )
447	457	{
	458	nes_state *state = (nes_state *)machine->driver_data;
	459
448	460	/* assumes that bank references an 8k chunk */
449		bank &= ((nes.prg_chunks << 1) - 1);
450		if (nes.slow_banking)
451		memcpy(&nes.rom[0x8000], &nes.rom[bank * 0x2000 + 0x10000], 0x2000);
	461	bank &= ((state->prg_chunks << 1) - 1);
	462	if (state->slow_banking)
	463	memcpy(&state->rom[0x8000], &state->rom[bank * 0x2000 + 0x10000], 0x2000);
452	464	else
453		memory_set_bankptr(machine, "bank1", &nes.rom[bank * 0x2000 + 0x10000]);
	465	memory_set_bankptr(machine, "bank1", &state->rom[bank * 0x2000 + 0x10000]);
454	466	}
455	467
456	468	static void prg8_ab( running_machine *machine, int bank )
457	469	{
	470	nes_state *state = (nes_state *)machine->driver_data;
	471
458	472	/* assumes that bank references an 8k chunk */
459		bank &= ((nes.prg_chunks << 1) - 1);
460		if (nes.slow_banking)
461		memcpy(&nes.rom[0xa000], &nes.rom[bank * 0x2000 + 0x10000], 0x2000);
	473	bank &= ((state->prg_chunks << 1) - 1);
	474	if (state->slow_banking)
	475	memcpy(&state->rom[0xa000], &state->rom[bank * 0x2000 + 0x10000], 0x2000);
462	476	else
463		memory_set_bankptr(machine, "bank2", &nes.rom[bank * 0x2000 + 0x10000]);
	477	memory_set_bankptr(machine, "bank2", &state->rom[bank * 0x2000 + 0x10000]);
464	478	}
465	479
466	480	static void prg8_cd( running_machine *machine, int bank )
467	481	{
	482	nes_state *state = (nes_state *)machine->driver_data;
	483
468	484	/* assumes that bank references an 8k chunk */
469		bank &= ((nes.prg_chunks << 1) - 1);
470		if (nes.slow_banking)
471		memcpy(&nes.rom[0xc000], &nes.rom[bank * 0x2000 + 0x10000], 0x2000);
	485	bank &= ((state->prg_chunks << 1) - 1);
	486	if (state->slow_banking)
	487	memcpy(&state->rom[0xc000], &state->rom[bank * 0x2000 + 0x10000], 0x2000);
472	488	else
473		memory_set_bankptr(machine, "bank3", &nes.rom[bank * 0x2000 + 0x10000]);
	489	memory_set_bankptr(machine, "bank3", &state->rom[bank * 0x2000 + 0x10000]);
474	490	}
475	491
476	492	static void prg8_ef( running_machine *machine, int bank )
477	493	{
	494	nes_state *state = (nes_state *)machine->driver_data;
	495
478	496	/* assumes that bank references an 8k chunk */
479		bank &= ((nes.prg_chunks << 1) - 1);
480		if (nes.slow_banking)
481		memcpy(&nes.rom[0xe000], &nes.rom[bank * 0x2000 + 0x10000], 0x2000);
	497	bank &= ((state->prg_chunks << 1) - 1);
	498	if (state->slow_banking)
	499	memcpy(&state->rom[0xe000], &state->rom[bank * 0x2000 + 0x10000], 0x2000);
482	500	else
483		memory_set_bankptr(machine, "bank4", &nes.rom[bank * 0x2000 + 0x10000]);
	501	memory_set_bankptr(machine, "bank4", &state->rom[bank * 0x2000 + 0x10000]);
484	502	}
485	503
486	504	/* We define an additional helper to map PRG-ROM to 0x6000-0x7000 */
r7952	r7953
488	506
489	507	static void prg8_67( running_machine *machine, int bank )
490	508	{
	509	nes_state *state = (nes_state *)machine->driver_data;
	510
491	511	/* assumes that bank references an 8k chunk */
492		bank &= ((nes.prg_chunks << 1) - 1);
493		memory_set_bankptr(machine, "bank5", &nes.rom[bank * 0x2000 + 0x10000]);
	512	bank &= ((state->prg_chunks << 1) - 1);
	513	memory_set_bankptr(machine, "bank5", &state->rom[bank * 0x2000 + 0x10000]);
494	514	}
495	515
496	516	/* CHR ROM in 1K, 2K, 4K or 8K blocks */
497	517
498	518	static void chr8( running_machine *machine, int bank, int source )
499	519	{
	520	nes_state *state = (nes_state *)machine->driver_data;
500	521	int i;
501	522
502		bank &= (nes.chr_chunks - 1);
	523	bank &= (state->chr_chunks - 1);
503	524	for (i = 0; i < 8; i++)
504	525	{
505	526	chr_map[i].source = source;
506	527	chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
507	528
508	529	if (source == CHRRAM)
509		chr_map[i].access = &nes.vram[chr_map[i].origin];
	530	chr_map[i].access = &state->vram[chr_map[i].origin];
510	531	else
511		chr_map[i].access = &nes.vrom[chr_map[i].origin];
	532	chr_map[i].access = &state->vrom[chr_map[i].origin];
512	533	}
513	534	}
514	535
515	536	static void chr4_x( running_machine *machine, int start, int bank, int source )
516	537	{
	538	nes_state *state = (nes_state *)machine->driver_data;
517	539	int i;
518	540
519		bank &= ((nes.chr_chunks << 1) - 1);
	541	bank &= ((state->chr_chunks << 1) - 1);
520	542	for (i = 0; i < 4; i++)
521	543	{
522	544	chr_map[i + start].source = source;
523	545	chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
524	546
525	547	if (source == CHRRAM)
526		chr_map[i+start].access = &nes.vram[chr_map[i + start].origin];
	548	chr_map[i + start].access = &state->vram[chr_map[i + start].origin];
527	549	else
528		chr_map[i+start].access = &nes.vrom[chr_map[i + start].origin];
	550	chr_map[i + start].access = &state->vrom[chr_map[i + start].origin];
529	551	}
530	552	}
531	553
r7952	r7953
541	563
542	564	static void chr2_x( running_machine *machine, int start, int bank, int source )
543	565	{
	566	nes_state *state = (nes_state *)machine->driver_data;
544	567	int i;
545	568
546		bank &= ((nes.chr_chunks << 2) - 1);
	569	bank &= ((state->chr_chunks << 2) - 1);
547	570	for (i = 0; i < 2; i++)
548	571	{
549	572	chr_map[i + start].source = source;
550	573	chr_map[i + start].origin = (bank * 0x800) + (i * 0x400);
551	574
552	575	if (source == CHRRAM)
553		chr_map[i + start].access = &nes.vram[chr_map[i + start].origin];
	576	chr_map[i + start].access = &state->vram[chr_map[i + start].origin];
554	577	else
555		chr_map[i + start].access = &nes.vrom[chr_map[i + start].origin];
	578	chr_map[i + start].access = &state->vrom[chr_map[i + start].origin];
556	579	}
557	580	}
558	581
r7952	r7953
578	601
579	602	static void chr1_x( running_machine *machine, int start, int bank, int source )
580	603	{
	604	nes_state *state = (nes_state *)machine->driver_data;
	605
581	606	chr_map[start].source = source;
582		bank &= ((nes.chr_chunks << 3) - 1);
	607	bank &= ((state->chr_chunks << 3) - 1);
583	608	chr_map[start].origin = bank * 0x400;
584	609
585	610	if (source == CHRRAM)
586		chr_map[start].access = &nes.vram[chr_map[start].origin];
	611	chr_map[start].access = &state->vram[chr_map[start].origin];
587	612	else
588		chr_map[start].access = &nes.vrom[chr_map[start].origin];
	613	chr_map[start].access = &state->vrom[chr_map[start].origin];
589	614	}
590	615
591	616	static void chr1_0 (running_machine *machine, int bank, int source)
r7952	r7953
631	656
632	657	/* NameTable paging and mirroring */
633	658
634		static void set_nt_page( int page, int source, int bank, int writable )
	659	static void set_nt_page( running_machine *machine, int page, int source, int bank, int writable )
635	660	{
	661	nes_state *state = (nes_state *)machine->driver_data;
636	662	UINT8* base_ptr;
637	663
638	664	switch (source)
r7952	r7953
644	670	base_ptr = NULL;
645	671	break;
646	672	case ROM:
647		base_ptr = nes.vrom;
	673	base_ptr = state->vrom;
648	674	break;
649	675	case EXRAM:
650	676	base_ptr = nes_mmc5_vram;
651	677	break;
652	678	case CIRAM:
653	679	default:
654		base_ptr = nes.ciram;
	680	base_ptr = state->ciram;
655	681	break;
656	682	}
657	683
r7952	r7953
665	691	nt_page[page].writable = writable;
666	692	}
667	693
668		void set_nt_mirroring( int mirroring )
	694	void set_nt_mirroring( running_machine *machine, int mirroring )
669	695	{
670	696	/* setup our videomem handlers based on mirroring */
671	697	switch (mirroring)
672	698	{
673	699	case PPU_MIRROR_VERT:
674		set_nt_page(0, CIRAM, 0, 1);
675		set_nt_page(1, CIRAM, 1, 1);
676		set_nt_page(2, CIRAM, 0, 1);
677		set_nt_page(3, CIRAM, 1, 1);
	700	set_nt_page(machine, 0, CIRAM, 0, 1);
	701	set_nt_page(machine, 1, CIRAM, 1, 1);
	702	set_nt_page(machine, 2, CIRAM, 0, 1);
	703	set_nt_page(machine, 3, CIRAM, 1, 1);
678	704	break;
679	705
680	706	case PPU_MIRROR_HORZ:
681		set_nt_page(0, CIRAM, 0, 1);
682		set_nt_page(1, CIRAM, 0, 1);
683		set_nt_page(2, CIRAM, 1, 1);
684		set_nt_page(3, CIRAM, 1, 1);
	707	set_nt_page(machine, 0, CIRAM, 0, 1);
	708	set_nt_page(machine, 1, CIRAM, 0, 1);
	709	set_nt_page(machine, 2, CIRAM, 1, 1);
	710	set_nt_page(machine, 3, CIRAM, 1, 1);
685	711	break;
686	712
687	713	case PPU_MIRROR_HIGH:
688		set_nt_page(0, CIRAM, 1, 1);
689		set_nt_page(1, CIRAM, 1, 1);
690		set_nt_page(2, CIRAM, 1, 1);
691		set_nt_page(3, CIRAM, 1, 1);
	714	set_nt_page(machine, 0, CIRAM, 1, 1);
	715	set_nt_page(machine, 1, CIRAM, 1, 1);
	716	set_nt_page(machine, 2, CIRAM, 1, 1);
	717	set_nt_page(machine, 3, CIRAM, 1, 1);
692	718	break;
693	719
694	720	case PPU_MIRROR_LOW:
695		set_nt_page(0, CIRAM, 0, 1);
696		set_nt_page(1, CIRAM, 0, 1);
697		set_nt_page(2, CIRAM, 0, 1);
698		set_nt_page(3, CIRAM, 0, 1);
	721	set_nt_page(machine, 0, CIRAM, 0, 1);
	722	set_nt_page(machine, 1, CIRAM, 0, 1);
	723	set_nt_page(machine, 2, CIRAM, 0, 1);
	724	set_nt_page(machine, 3, CIRAM, 0, 1);
699	725	break;
700	726
701	727	case PPU_MIRROR_NONE:
r7952	r7953
707	733
708	734	logerror("Mapper set 4-screen mirroring without supplying external nametable memory!\n");
709	735
710		set_nt_page(0, CIRAM, 0, 1);
711		set_nt_page(1, CIRAM, 0, 1);
712		set_nt_page(2, CIRAM, 1, 1);
713		set_nt_page(3, CIRAM, 1, 1);
	736	set_nt_page(machine, 0, CIRAM, 0, 1);
	737	set_nt_page(machine, 1, CIRAM, 0, 1);
	738	set_nt_page(machine, 2, CIRAM, 1, 1);
	739	set_nt_page(machine, 3, CIRAM, 1, 1);
714	740	break;
715	741	}
716	742	}
r7952	r7953
741	767
742	768	static int mapper_initialize( running_machine *machine, int mmc_num )
743	769	{
	770	nes_state *state = (nes_state *)machine->driver_data;
744	771	int err = 0, i;
745	772
746	773	switch (mmc_num)
r7952	r7953
755	782	mmc_count = 0;
756	783	MMC1_regs[0] = 0x0f;
757	784	MMC1_regs[1] = MMC1_regs[2] = MMC1_regs[3] = 0;
758		set_nt_mirroring(PPU_MIRROR_HORZ);
759		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	785	set_nt_mirroring(machine, PPU_MIRROR_HORZ);
	786	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
760	787	MMC1_set_chr(machine);
761	788	MMC1_set_prg(machine);
762	789	break;
763	790	case 2:
764	791	/* These games don't switch VROM, but some ROMs incorrectly have CHR chunks */
765		nes.chr_chunks = 0;
	792	state->chr_chunks = 0;
766	793	prg16_89ab(machine, 0);
767		prg16_cdef(machine, nes.prg_chunks - 1);
	794	prg16_cdef(machine, state->prg_chunks - 1);
768	795	break;
769	796	case 13:
770	797	chr4_0(machine, 0, CHRRAM);
r7952	r7953
779	806	/* Only MMC3 and clones seem to use 4-screen! */
780	807	/* hardware uses an 8K RAM chip, but can't address the high 4K! */
781	808	/* that much is documented for Nintendo Gauntlet boards */
782		if(nes.four_screen_vram)
	809	if(state->four_screen_vram)
783	810	{
784		extended_ntram=auto_alloc_array(machine, UINT8, 0x2000);
785		set_nt_page(0, CART_NTRAM, 0, 1);
786		set_nt_page(1, CART_NTRAM, 1, 1);
787		set_nt_page(2, CART_NTRAM, 2, 1);
788		set_nt_page(3, CART_NTRAM, 3, 1);
	811	extended_ntram = auto_alloc_array(machine, UINT8, 0x2000);
	812	set_nt_page(machine, 0, CART_NTRAM, 0, 1);
	813	set_nt_page(machine, 1, CART_NTRAM, 1, 1);
	814	set_nt_page(machine, 2, CART_NTRAM, 2, 1);
	815	set_nt_page(machine, 3, CART_NTRAM, 3, 1);
789	816	}
790	817	case 12:
791	818	case 74:
r7952	r7953
804	831	mmc_cmd2 = 0x80;
805	832	mmc_prg_base = mmc_chr_base = 0;
806	833	mmc_prg_mask = mmc_chr_mask = 0xff;   // these could be init'ed as xxx_chunks-1 and they would work the same
807		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	834	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
808	835	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
809	836	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
810	837	break;
r7952	r7953
813	840	MMC5_rom_bank_mode = 3;
814	841	MMC5_vrom_bank_mode = 0;
815	842	MMC5_vram_protect = 0;
816		nes.mid_ram_enable = 0;
817		prg16_89ab(machine, nes.prg_chunks - 2);
818		prg16_cdef(machine, nes.prg_chunks - 1);
	843	state->mid_ram_enable = 0;
	844	prg16_89ab(machine, state->prg_chunks - 2);
	845	prg16_cdef(machine, state->prg_chunks - 1);
819	846	break;
820	847	case 6:
821	848	mmc_cmd1 = 0;
822		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	849	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
823	850	prg16_89ab(machine, 0);
824	851	prg16_cdef(machine, 7);
825	852	break;
826	853	case 7:
827	854	/* Bankswitches 32k at a time */
828		set_nt_mirroring(PPU_MIRROR_LOW);
	855	set_nt_mirroring(machine, PPU_MIRROR_LOW);
829	856	prg16_89ab(machine, 0);
830		prg16_cdef(machine, nes.prg_chunks - 1);
	857	prg16_cdef(machine, state->prg_chunks - 1);
831	858	break;
832	859	case 8:
833	860	case 96:
r7952	r7953
839	866	mmc_cmd1 = mmc_cmd2 = 0xfe;
840	867	prg8_89(machine, 0);
841	868	//ugly hack to deal with iNES header usage of chunk count.
842		prg8_ab(machine, (nes.prg_chunks << 1) - 3);
843		prg8_cd(machine, (nes.prg_chunks << 1) - 2);
844		prg8_ef(machine, (nes.prg_chunks << 1) - 1);
	869	prg8_ab(machine, (state->prg_chunks << 1) - 3);
	870	prg8_cd(machine, (state->prg_chunks << 1) - 2);
	871	prg8_ef(machine, (state->prg_chunks << 1) - 1);
845	872	break;
846	873	case 10:
847	874	/* Reset VROM latches */
r7952	r7953
849	876	MMC2_regs[1] = MMC2_regs[3] = 0;
850	877	mmc_cmd1 = mmc_cmd2 = 0xfe;
851	878	prg16_89ab(machine, 0);
852		prg16_cdef(machine, nes.prg_chunks - 1);
	879	prg16_cdef(machine, state->prg_chunks - 1);
853	880	break;
854	881	case 11:
855		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;   // NINA-07 has no CHRROM
	882	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;   // NINA-07 has no CHRROM
856	883	prg32(machine, 0);
857	884	break;
858	885	case 14:
r7952	r7953
867	894	mmc_cmd2 = 0x80;
868	895	mmc_prg_base = mmc_chr_base = 0;
869	896	mmc_prg_mask = mmc_chr_mask = 0xff;
870		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	897	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
871	898	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
872	899	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
873	900	break;
874	901	case 15:
875		set_nt_mirroring(PPU_MIRROR_VERT);
	902	set_nt_mirroring(machine, PPU_MIRROR_VERT);
876	903	prg32(machine, 0);
877	904	break;
878	905	case 16:
r7952	r7953
882	909	case 159:
883	910	mmc_cmd1 = 0;
884	911	prg16_89ab(machine, 0);
885		prg16_cdef(machine, nes.prg_chunks - 1);
886		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	912	prg16_cdef(machine, state->prg_chunks - 1);
	913	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
887	914	break;
888	915	case 19:
889	916	mmc_cmd1 = 0;
890	917	prg16_89ab(machine, 0);
891		prg16_cdef(machine, nes.prg_chunks - 1);
892		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
893		set_nt_mirroring(PPU_MIRROR_VERT);
	918	prg16_cdef(machine, state->prg_chunks - 1);
	919	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
	920	set_nt_mirroring(machine, PPU_MIRROR_VERT);
894	921	break;
895	922	case 20:
896	923	fds_last_side = 0;
897	924	fds_count = 0;
898		nes_fds.motor_on = 0;
899		nes_fds.door_closed = 0;
900		nes_fds.current_side = 1;
901		nes_fds.head_position = 0;
902		nes_fds.status0 = 0;
903		nes_fds.read_mode = nes_fds.write_reg = 0;
	925	state->fds_motor_on = 0;
	926	state->fds_door_closed = 0;
	927	state->fds_current_side = 1;
	928	state->fds_head_position = 0;
	929	state->fds_status0 = 0;
	930	state->fds_read_mode = state->fds_write_reg = 0;
904	931	break;
905	932	case 21:
906	933	case 22:
r7952	r7953
920	947	case 207:
921	948	case 222:
922	949	case 252:
923		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	950	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
924	951	prg16_89ab(machine, 0);
925		prg16_cdef(machine, nes.prg_chunks - 1);
	952	prg16_cdef(machine, state->prg_chunks - 1);
926	953	break;
927	954	case 32:
928	955	mmc_cmd1 = 0;
929	956	prg16_89ab(machine, 0);
930		prg16_cdef(machine, nes.prg_chunks - 1);
931		if (nes.crc_hack)
932		set_nt_mirroring(PPU_MIRROR_HIGH);  // needed by Major League
	957	prg16_cdef(machine, state->prg_chunks - 1);
	958	if (state->crc_hack)
	959	set_nt_mirroring(machine, PPU_MIRROR_HIGH);  // needed by Major League
933	960	break;
934	961	case 34:
935	962	prg32(machine, 0);
r7952	r7953
945	972	mmc_prg_base = mmc_chr_base = 0;
946	973	mmc_prg_mask = 0x07;
947	974	mmc_chr_mask = 0x7f;
948		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	975	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
949	976	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
950	977	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
951	978	break;
r7952	r7953
961	988	prg32(machine, 0);
962	989	break;
963	990	case 42:
964		prg32(machine, nes.prg_chunks - 1);
	991	prg32(machine, state->prg_chunks - 1);
965	992	break;
966	993	case 43:
967	994	prg32(machine, 0);
968		memset(nes.wram, 0x2000, 0xff);
	995	memset(state->wram, 0x2000, 0xff);
969	996	break;
970	997	case 44:
971	998	case 47:
r7952	r7953
977	1004	mmc_prg_base = mmc_chr_base = 0;
978	1005	mmc_prg_mask = 0x0f;
979	1006	mmc_chr_mask = 0x7f;
980		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1007	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
981	1008	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
982	1009	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
983	1010	break;
r7952	r7953
986	1013	prg_bank[1] = prg_bank[3] = 0xff;
987	1014	mmc_cmd1 = 0;
988	1015	mmc_cmd2 = 0x80;
989		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1016	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
990	1017	mapper45_reg[0] = mapper45_reg[1] = mapper45_reg[2] = mapper45_reg[3] = 0;
991	1018	mmc_prg_base = 0x30;
992	1019	mmc_prg_mask = 0x3f;
r7952	r7953
994	1021	mmc_chr_mask = 0x7f;
995	1022	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
996	1023	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
997		memory_set_bankptr(machine, "bank5", nes.wram);
	1024	memory_set_bankptr(machine, "bank5", state->wram);
998	1025	break;
999	1026	case 46:
1000	1027	prg32(machine, 0);
r7952	r7953
1003	1030	case 54:
1004	1031	prg32(machine, 0);
1005	1032	chr8(machine, 0, CHRROM);
1006		set_nt_mirroring(PPU_MIRROR_VERT);
	1033	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1007	1034	break;
1008	1035	case 50:
1009	1036	prg8_67(machine, 0x0f);
r7952	r7953
1025	1052	mmc_cmd1 = 0;
1026	1053	mmc_cmd2 = 0x80;
1027	1054	map52_reg_written = 0;
1028		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1055	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1029	1056	mmc_prg_base = 0;
1030	1057	mmc_prg_mask = 0x1f;
1031	1058	mmc_chr_base = 0;
1032	1059	mmc_chr_mask = 0xff;
1033	1060	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1034	1061	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1035		memory_set_bankptr(machine, "bank5", nes.wram);
	1062	memory_set_bankptr(machine, "bank5", state->wram);
1036	1063	break;
1037	1064	case 57:
1038	1065	mmc_cmd1 = 0x00;
r7952	r7953
1053	1080	case 64:
1054	1081	case 158:
1055	1082	mmc_cmd1 = 0;
1056		prg16_89ab(machine, nes.prg_chunks - 1);
1057		prg16_cdef(machine, nes.prg_chunks - 1);
	1083	prg16_89ab(machine, state->prg_chunks - 1);
	1084	prg16_cdef(machine, state->prg_chunks - 1);
1058	1085	break;
1059	1086	case 65:
1060	1087	case 67:
r7952	r7953
1063	1090	case 78:
1064	1091	case 92:
1065	1092	prg16_89ab(machine, 0);
1066		prg16_cdef(machine, nes.prg_chunks - 1);
	1093	prg16_cdef(machine, state->prg_chunks - 1);
1067	1094	break;
1068	1095	case 68:
1069	1096	m68_mirror = m0 = m1 = 0;
1070	1097	prg16_89ab(machine, 0);
1071		prg16_cdef(machine, nes.prg_chunks - 1);
	1098	prg16_cdef(machine, state->prg_chunks - 1);
1072	1099	break;
1073	1100	case 70:
1074		prg16_89ab(machine, nes.prg_chunks - 2);
1075		prg16_cdef(machine, nes.prg_chunks - 1);
	1101	prg16_89ab(machine, state->prg_chunks - 2);
	1102	prg16_cdef(machine, state->prg_chunks - 1);
1076	1103	break;
1077	1104	case 71:
1078		set_nt_mirroring(PPU_MIRROR_HORZ);
	1105	set_nt_mirroring(machine, PPU_MIRROR_HORZ);
1079	1106	prg16_89ab(machine, 0);
1080		prg16_cdef(machine, nes.prg_chunks - 1);
	1107	prg16_cdef(machine, state->prg_chunks - 1);
1081	1108	break;
1082	1109	case 76:
1083	1110	prg8_89(machine, 0);
1084	1111	prg8_ab(machine, 1);
1085	1112	//cd is bankable, but this should init all banks just fine.
1086		prg16_cdef(machine, nes.prg_chunks - 1);
	1113	prg16_cdef(machine, state->prg_chunks - 1);
1087	1114	chr2_0(machine, 0, CHRROM);
1088	1115	chr2_2(machine, 1, CHRROM);
1089	1116	chr2_4(machine, 2, CHRROM);
r7952	r7953
1100	1127	case 146:
1101	1128	/* Mirroring always horizontal...? */
1102	1129	//          Mirroring = 1;
1103		set_nt_mirroring(PPU_MIRROR_HORZ);
	1130	set_nt_mirroring(machine, PPU_MIRROR_HORZ);
1104	1131	chr8(machine, 0, CHRROM);
1105	1132	prg32(machine, 0);
1106	1133	break;
r7952	r7953
1121	1148	break;
1122	1149	case 89:
1123	1150	prg16_89ab(machine, 0);
1124		prg16_cdef(machine, nes.prg_chunks - 1);
1125		set_nt_mirroring(PPU_MIRROR_LOW);
	1151	prg16_cdef(machine, state->prg_chunks - 1);
	1152	set_nt_mirroring(machine, PPU_MIRROR_LOW);
1126	1153	break;
1127	1154	case 91:
1128		set_nt_mirroring(PPU_MIRROR_VERT);
1129		prg16_89ab(machine, nes.prg_chunks - 1);
1130		prg16_cdef(machine, nes.prg_chunks - 1);
	1155	set_nt_mirroring(machine, PPU_MIRROR_VERT);
	1156	prg16_89ab(machine, state->prg_chunks - 1);
	1157	prg16_cdef(machine, state->prg_chunks - 1);
1131	1158	break;
1132	1159	case 93:
1133	1160	case 94:
1134	1161	case 95:
1135	1162	case 101:
1136	1163	prg16_89ab(machine, 0);
1137		prg16_cdef(machine, nes.prg_chunks - 1);
	1164	prg16_cdef(machine, state->prg_chunks - 1);
1138	1165	break;
1139	1166	case 97:
1140		prg16_89ab(machine, nes.prg_chunks - 1);
1141		prg16_cdef(machine, nes.prg_chunks - 1);
	1167	prg16_89ab(machine, state->prg_chunks - 1);
	1168	prg16_cdef(machine, state->prg_chunks - 1);
1142	1169	break;
1143	1170	case 112:
1144	1171	mmc_cmd1 = 0;
1145	1172	prg16_89ab(machine, 0);
1146		prg16_cdef(machine, nes.prg_chunks - 1);
	1173	prg16_cdef(machine, state->prg_chunks - 1);
1147	1174	break;
1148	1175	case 36:
1149	1176	case 38:
r7952	r7953
1167	1194	prg16_cdef(machine, 0x0f);
1168	1195	break;
1169	1196	case 106:
1170		prg8_89(machine, (nes.prg_chunks << 1) - 1);
	1197	prg8_89(machine, (state->prg_chunks << 1) - 1);
1171	1198	prg8_ab(machine, 0);
1172	1199	prg8_cd(machine, 0);
1173		prg8_ef(machine, (nes.prg_chunks << 1) - 1);
	1200	prg8_ef(machine, (state->prg_chunks << 1) - 1);
1174	1201	break;
1175	1202	case 114:
1176	1203	map114_reg = map114_reg_enabled = 0;
r7952	r7953
1180	1207	mmc_cmd2 = 0x80;
1181	1208	mmc_prg_base = mmc_chr_base = 0;
1182	1209	mmc_prg_mask = mmc_chr_mask = 0xff;
1183		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1210	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1184	1211	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1185	1212	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1186	1213	break;
r7952	r7953
1192	1219	mmc_cmd2 = 0x80;
1193	1220	mmc_prg_base = mmc_chr_base = 0;
1194	1221	mmc_prg_mask = mmc_chr_mask = 0xff;
1195		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1222	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1196	1223	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1197	1224	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1198	1225	break;
r7952	r7953
1204	1231	mmc_cmd2 = 0x80;
1205	1232	mmc_prg_base = mmc_chr_base = 0;
1206	1233	mmc_prg_mask = mmc_chr_mask = 0xff;
1207		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1234	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1208	1235	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1209	1236	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1210	1237	break;
r7952	r7953
1222	1249	mmc_prg_base = mmc_chr_base = 0;
1223	1250	mmc_prg_mask = 0x1f;
1224	1251	mmc_chr_mask = 0xff;
1225		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1252	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1226	1253	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1227	1254	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1228	1255	break;
r7952	r7953
1243	1270	case 137:
1244	1271	mmc_cmd1 = 0;
1245	1272	prg32(machine, 0);
1246		chr8(machine, nes.chr_chunks - 1, CHRROM);
1247		set_nt_mirroring(PPU_MIRROR_VERT);
	1273	chr8(machine, state->chr_chunks - 1, CHRROM);
	1274	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1248	1275	break;
1249	1276	case 138:
1250	1277	case 139:
1251	1278	case 141:
1252	1279	mmc_cmd1 = 0;
1253		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1280	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1254	1281	prg32(machine, 0);
1255	1282	chr8(machine, 0, mmc_chr_source);
1256		set_nt_mirroring(PPU_MIRROR_VERT);
	1283	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1257	1284	break;
1258	1285	case 143:
1259	1286	prg16_89ab(machine, 0);
r7952	r7953
1273	1300	mmc_cmd1 = 0;
1274	1301	prg32(machine, 0);
1275	1302	chr8(machine, 0, CHRROM);
1276		set_nt_mirroring(PPU_MIRROR_VERT);
	1303	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1277	1304	break;
1278	1305	case 152:
1279	1306	prg16_89ab(machine, 0);
1280		prg16_cdef(machine, nes.prg_chunks - 1);
	1307	prg16_cdef(machine, state->prg_chunks - 1);
1281	1308	chr8(machine, 0, CHRROM);
1282	1309	break;
1283	1310	case 153:
1284	1311	mmc_cmd1 = 0;
1285	1312	prg16_89ab(machine, 0);
1286		prg16_cdef(machine, nes.prg_chunks - 1);
1287		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1313	prg16_cdef(machine, state->prg_chunks - 1);
	1314	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1288	1315	// Famicom Jump II needs also the following!
1289	1316	for (i = 0; i < 8; i++)
1290	1317	map153_reg[i] = 0;
1291	1318
1292	1319	map153_bank_latch = 0;
1293		if (nes.crc_hack)
	1320	if (state->crc_hack)
1294	1321	mapper153_set_prg(machine);
1295	1322	break;
1296	1323	case 154:
1297		prg16_89ab(machine, nes.prg_chunks - 2);
1298		prg16_cdef(machine, nes.prg_chunks - 1);
	1324	prg16_89ab(machine, state->prg_chunks - 2);
	1325	prg16_cdef(machine, state->prg_chunks - 1);
1299	1326	break;
1300	1327	case 156:
1301		prg16_89ab(machine, nes.prg_chunks - 2);
1302		prg16_cdef(machine, nes.prg_chunks - 1);
1303		set_nt_mirroring(PPU_MIRROR_LOW);
	1328	prg16_89ab(machine, state->prg_chunks - 2);
	1329	prg16_cdef(machine, state->prg_chunks - 1);
	1330	set_nt_mirroring(machine, PPU_MIRROR_LOW);
1304	1331	break;
1305	1332	case 164:
1306	1333	prg32(machine, 0xff);
1307		nes.mid_ram_enable = 1;
	1334	state->mid_ram_enable = 1;
1308	1335	break;
1309	1336	case 176:
1310		prg32(machine, (nes.prg_chunks - 1) >> 1);
	1337	prg32(machine, (state->prg_chunks - 1) >> 1);
1311	1338	break;
1312	1339	case 178:
1313	1340	mmc_cmd1 = 0;
r7952	r7953
1318	1345	prg16_cdef(machine, 0);
1319	1346	break;
1320	1347	case 182:
1321		prg32(machine, (nes.prg_chunks - 1) >> 1);
	1348	prg32(machine, (state->prg_chunks - 1) >> 1);
1322	1349	break;
1323	1350	case 188:
1324	1351	prg16_89ab(machine, 0);
1325		prg16_cdef(machine, (nes.prg_chunks - 1) ^ 0x08);
	1352	prg16_cdef(machine, (state->prg_chunks - 1) ^ 0x08);
1326	1353	break;
1327	1354	case 187:
1328	1355	prg_bank[0] = prg_bank[2] = 0xfe;
r7952	r7953
1332	1359	mmc_cmd2 = 0x80;
1333	1360	mmc_prg_base = mmc_chr_base = 0;
1334	1361	mmc_prg_mask = mmc_chr_mask = 0xff;
1335		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1362	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1336	1363	mapper187_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1337	1364	mapper187_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1338	1365	break;
r7952	r7953
1341	1368	mmc_cmd2 = 0x80;
1342	1369	mmc_chr_base = 0;
1343	1370	mmc_chr_mask = 0xff;
1344		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1371	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1345	1372	prg32(machine, 0);
1346	1373	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1347	1374	break;
1348	1375	case 193:
1349		prg32(machine, (nes.prg_chunks - 1) >> 1);
1350		set_nt_mirroring(PPU_MIRROR_VERT);
	1376	prg32(machine, (state->prg_chunks - 1) >> 1);
	1377	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1351	1378	break;
1352	1379	case 197:
1353	1380	prg_bank[0] = prg_bank[2] = 0xfe;
r7952	r7953
1356	1383	mmc_cmd2 = 0x80;
1357	1384	mmc_prg_base = mmc_chr_base = 0;
1358	1385	mmc_prg_mask = mmc_chr_mask = 0xff;
1359		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1386	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1360	1387	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1361	1388	mapper197_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1362	1389	break;
r7952	r7953
1369	1396	mmc_cmd2 = 0x80;
1370	1397	mmc_prg_base = mmc_chr_base = 0;
1371	1398	mmc_prg_mask = mmc_chr_mask = 0xff;
1372		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1399	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1373	1400	mapper198_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1374	1401	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1375	1402	break;
r7952	r7953
1382	1409	mmc_cmd2 = 0x80;
1383	1410	mmc_prg_base = mmc_chr_base = 0;
1384	1411	mmc_prg_mask = mmc_chr_mask = 0xff;
1385		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1412	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1386	1413	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1387	1414	mapper199_set_chr(machine, mmc_chr_base, mmc_chr_mask);
1388	1415	break;
1389	1416	case 200:
1390		prg16_89ab(machine, nes.prg_chunks - 1);
1391		prg16_cdef(machine, nes.prg_chunks - 1);
	1417	prg16_89ab(machine, state->prg_chunks - 1);
	1418	prg16_cdef(machine, state->prg_chunks - 1);
1392	1419	break;
1393	1420	case 201:
1394	1421	case 213:
r7952	r7953
1412	1439	mmc_prg_mask = 0x1f;
1413	1440	mmc_chr_base = 0;
1414	1441	mmc_chr_mask = 0xff;
1415		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1442	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1416	1443	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1417	1444	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1418	1445	break;
r7952	r7953
1424	1451	mmc_cmd2 = 0x80;
1425	1452	mmc_prg_base = mmc_chr_base = 0;
1426	1453	mmc_prg_mask = mmc_chr_mask = 0xff;
1427		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1454	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1428	1455	mapper4_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1429	1456	mapper4_set_chr(machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1430	1457	break;
r7952	r7953
1445	1472	map215_reg[3] = 0;
1446	1473	mmc_prg_base = 0;
1447	1474	mmc_prg_mask = 0x1f;
1448		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1475	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1449	1476	mapper215_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1450	1477	mapper215_set_chr(machine, mmc_chr_source);
1451	1478	break;
1452	1479	case 216:
1453		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1480	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1454	1481	prg32(machine, 0);
1455	1482	chr8(machine, 0, mmc_chr_source);
1456	1483	break;
r7952	r7953
1465	1492	mmc_cmd2 = 0x80;
1466	1493	mmc_prg_base = mmc_chr_base = 0;
1467	1494	mmc_prg_mask = mmc_chr_mask = 0xff;
1468		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1495	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1469	1496	mapper217_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1470	1497	mapper217_set_chr(machine, mmc_chr_source);
1471	1498	break;
r7952	r7953
1492	1519	prg16_89ab(machine, 0);
1493	1520	prg16_cdef(machine, 1);
1494	1521	chr8(machine, 0, CHRROM);
1495		set_nt_mirroring(PPU_MIRROR_VERT);
	1522	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1496	1523	break;
1497	1524	case 230:
1498	1525	prg16_89ab(machine, 0);
r7952	r7953
1500	1527	break;
1501	1528	case 231:
1502	1529	prg16_89ab(machine, 0);
1503		prg16_cdef(machine, nes.prg_chunks - 1);
1504		set_nt_mirroring(PPU_MIRROR_VERT);
	1530	prg16_cdef(machine, state->prg_chunks - 1);
	1531	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1505	1532	break;
1506	1533	case 232:
1507	1534	mmc_cmd1 = 0x18;
r7952	r7953
1513	1540	mmc_cmd1 = 0;
1514	1541	chr8(machine, 3, CHRROM);
1515	1542	prg32(machine, 0);
1516		set_nt_mirroring(PPU_MIRROR_VERT);
	1543	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1517	1544	break;
1518	1545	case 246:
1519	1546	prg32(machine, 0xff);
r7952	r7953
1526	1553	map249_reg = 0;
1527	1554	mmc_prg_base = mmc_chr_base = 0;
1528	1555	mmc_prg_mask = mmc_chr_mask = 0xff;
1529		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1556	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1530	1557	mapper249_set_prg(machine, mmc_prg_base, mmc_prg_mask);
1531	1558	mapper249_set_chr(machine, mmc_chr_base, mmc_chr_mask);
1532	1559	break;
r7952	r7953
1559	1586	int err = 0, i;
1560	1587	const mmc *mapper;
1561	1588
1562		if (nes.chr_chunks == 0)
	1589	if (state->chr_chunks == 0)
1563	1590	chr8(machine, 0,CHRRAM);
1564	1591	else
1565	1592	chr8(machine, 0,CHRROM);
r7952	r7953
1581	1608
1582	1609	/* Point the WRAM/battery area to the first RAM bank */
1583	1610	if (mmc_num != 20)
1584		memory_set_bankptr(machine, "bank5", &nes.wram[0x0000]);
	1611	memory_set_bankptr(machine, "bank5", &state->wram[0x0000]);
1585	1612
1586	1613	/* Here, we init a few helpers: 4 prg banks and 16 chr banks - some mappers use them */
1587	1614	for (i = 0; i < 4; i++)
r7952	r7953
1625	1652	int err = 0;
1626	1653	const unif *unif_board;
1627	1654
1628		if (nes.chr_chunks == 0)
	1655	if (state->chr_chunks == 0)
1629	1656	chr8(machine, 0,CHRRAM);
1630	1657	else
1631	1658	chr8(machine, 0,CHRROM);
r7952	r7953
1641	1668
1642	1669
1643	1670	/* Point the WRAM/battery area to the first RAM bank */
1644		memory_set_bankptr(machine, "bank5", &nes.wram[0x0000]);
	1671	memory_set_bankptr(machine, "bank5", &state->wram[0x0000]);
1645	1672
1646	1673	switch (unif_board->board_idx)
1647	1674	{
r7952	r7953
1650	1677	bmc_64in1nr_reg[1] = 0x43;
1651	1678	bmc_64in1nr_reg[2] = bmc_64in1nr_reg[3] = 0;
1652	1679	bmc_64in1nr_set_prg(machine);
1653		set_nt_mirroring(PPU_MIRROR_VERT);
	1680	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1654	1681	chr8(machine, 0, CHRROM);
1655	1682	break;
1656	1683	case BMC_190IN1:
r7952	r7953
1661	1688	case BMC_A65AS:
1662	1689	prg16_89ab(machine, 0);
1663	1690	prg16_cdef(machine, 7);
1664		set_nt_mirroring(PPU_MIRROR_VERT);
	1691	set_nt_mirroring(machine, PPU_MIRROR_VERT);
1665	1692	break;
1666	1693	case BMC_GS2004:
1667	1694	case BMC_GS2013:
r7952	r7953
1723	1750	mapper_initialize(machine, 4);
1724	1751	break;
1725	1752	case UNL_T230:
1726		mmc_chr_source = nes.chr_chunks ? CHRROM : CHRRAM;
	1753	mmc_chr_source = state->chr_chunks ? CHRROM : CHRRAM;
1727	1754	prg16_89ab(machine, 0);
1728		prg16_cdef(machine, nes.prg_chunks - 1);
	1755	prg16_cdef(machine, state->prg_chunks - 1);
1729	1756	break;
1730	1757	/* For the Boards corresponding to a Mapper, fall back to the mapper init */
1731	1758	case STD_NROM:
r7952	r7953
1902	1929	mapper_initialize(machine, 71);
1903	1930	break;
1904	1931	case CAMERICA_9097:
1905		nes.crc_hack = 0xf0;
	1932	state->crc_hack = 0xf0;
1906	1933	mapper_initialize(machine, 71);
1907	1934	break;
1908	1935	case JALECO_JF17:

src/mess/machine/nes_mmc.h

r7952	r7953
83	83	#define PPU_MIRROR_LOW      4
84	84	#define PPU_MIRROR_4SCREEN   5   // Same effect as NONE, but signals that we should never mirror
85	85
86		void set_nt_mirroring(int mirroring);
	86	void set_nt_mirroring(running_machine *machine, int mirroring);
87	87
88	88
89	89	#endif

src/mess/machine/nes_ines.c

r7952	r7953
120	120
121	121	switch (MMC1_regs[0] & 0x03)
122	122	{
123		case 0: set_nt_mirroring(PPU_MIRROR_LOW); break;
124		case 1: set_nt_mirroring(PPU_MIRROR_HIGH); break;
125		case 2: set_nt_mirroring(PPU_MIRROR_VERT); break;
126		case 3: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	123	case 0: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	124	case 1: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
	125	case 2: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	126	case 3: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
127	127	}
128	128	MMC1_set_chr(space->machine);
129	129	MMC1_set_prg(space->machine);
r7952	r7953
259	259
260	260	static WRITE8_HANDLER( mapper4_w )
261	261	{
	262	nes_state *state = (nes_state *)space->machine->driver_data;
262	263	UINT8 MMC3_helper, cmd;
263	264
264	265	LOG_MMC(("mapper4_w offset: %04x, data: %02x\n", offset, data));
r7952	r7953
296	297	break;
297	298
298	299	case 0x2000:
299		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	300	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
300	301	break;
301	302
302	303	case 0x2001: /* extra RAM enable/disable */
303	304	mmc_cmd2 = data;   /* This actually is made of two parts: data&0x80 = WRAM enabled and data&0x40 = WRAM readonly!  */
304	305	/* We save this twice because we will need mmc_cmd2 in some clone mapper */
305		nes.mid_ram_enable = data;
	306	state->mid_ram_enable = data;
306	307	break;
307	308
308	309	case 0x4000:
r7952	r7953
357	358	}
358	359	}
359	360
360		static void ppu_mirror_MMC5( int page, int src )
	361	static void ppu_mirror_MMC5( running_machine *machine, int page, int src )
361	362	{
362	363	switch (src)
363	364	{
364	365	case 0:   /* CIRAM0 */
365		set_nt_page(page, CIRAM, 0, 1);
	366	set_nt_page(machine, page, CIRAM, 0, 1);
366	367	break;
367	368	case 1:   /* CIRAM1 */
368		set_nt_page(page, CIRAM, 1, 1);
	369	set_nt_page(machine, page, CIRAM, 1, 1);
369	370	break;
370	371	case 2:   /* ExRAM */
371		set_nt_page(page, EXRAM, 0, 1);   // actually only works during rendering.
	372	set_nt_page(machine, page, EXRAM, 0, 1);   // actually only works during rendering.
372	373	break;
373	374	case 3: /* Fill Registers */
374		set_nt_page(page, MMC5FILL, 0, 0);
	375	set_nt_page(machine, page, MMC5FILL, 0, 0);
375	376	break;
376	377	default:
377	378	fatalerror("This should never happen");
r7952	r7953
479	480	break;
480	481
481	482	case 0x1005: /* $5105 */
482		ppu_mirror_MMC5(0, data & 0x03);
483		ppu_mirror_MMC5(1, (data & 0x0c) >> 2);
484		ppu_mirror_MMC5(2, (data & 0x30) >> 4);
485		ppu_mirror_MMC5(3, (data & 0xc0) >> 6);
	483	ppu_mirror_MMC5(space->machine, 0, data & 0x03);
	484	ppu_mirror_MMC5(space->machine, 1, (data & 0x0c) >> 2);
	485	ppu_mirror_MMC5(space->machine, 2, (data & 0x30) >> 4);
	486	ppu_mirror_MMC5(space->machine, 3, (data & 0xc0) >> 6);
486	487	break;
487	488
488	489	/* tile data for MMC5 flood-fill NT mode */
r7952	r7953
504	505
505	506	case 0x1013: /* $5113 */
506	507	LOG_MMC(("MMC5 mid RAM bank select: %02x\n", data & 0x07));
507		memory_set_bankptr(space->machine, "bank5", &nes.wram[data * 0x2000]);
	508	memory_set_bankptr(space->machine, "bank5", &state->wram[data * 0x2000]);
508	509	/* The & 4 is a hack that'll tide us over for now */
509		nes_battery_ram = &nes.wram[(data & 4) * 0x2000];
	510	nes_battery_ram = &state->wram[(data & 4) * 0x2000];
510	511	break;
511	512
512	513	case 0x1014: /* $5114 */
r7952	r7953
519	520	{
520	521	/* ROM */
521	522	LOG_MMC(("\tROM bank select (8k, $8000): %02x\n", data));
522		data &= ((nes.prg_chunks << 1) - 1);
523		memory_set_bankptr(space->machine, "bank1", &nes.rom[data * 0x2000 + 0x10000]);
	523	data &= ((state->prg_chunks << 1) - 1);
	524	memory_set_bankptr(space->machine, "bank1", &state->rom[data * 0x2000 + 0x10000]);
524	525	}
525	526	else
526	527	{
527	528	/* RAM */
528	529	LOG_MMC(("\tRAM bank select (8k, $8000): %02x\n", data & 0x07));
529	530	/* The & 4 is a hack that'll tide us over for now */
530		memory_set_bankptr(space->machine, "bank1", &nes.wram[(data & 4) * 0x2000]);
	531	memory_set_bankptr(space->machine, "bank1", &state->wram[(data & 4) * 0x2000]);
531	532	}
532	533	break;
533	534	}
r7952	r7953
548	549	/* RAM */
549	550	LOG_MMC(("\tRAM bank select (16k, $8000): %02x\n", data & 0x07));
550	551	/* The & 4 is a hack that'll tide us over for now */
551		memory_set_bankptr(space->machine, "bank1", &nes.wram[((data & 4) >> 1) * 0x4000]);
552		memory_set_bankptr(space->machine, "bank2", &nes.wram[((data & 4) >> 1) * 0x4000 + 0x2000]);
	552	memory_set_bankptr(space->machine, "bank1", &state->wram[((data & 4) >> 1) * 0x4000]);
	553	memory_set_bankptr(space->machine, "bank2", &state->wram[((data & 4) >> 1) * 0x4000 + 0x2000]);
553	554	}
554	555	break;
555	556	case 0x03:
r7952	r7953
557	558	if (data & 0x80)
558	559	{
559	560	/* ROM */
560		data &= ((nes.prg_chunks << 1) - 1);
561		memory_set_bankptr(space->machine, "bank2", &nes.rom[data * 0x2000 + 0x10000]);
	561	data &= ((state->prg_chunks << 1) - 1);
	562	memory_set_bankptr(space->machine, "bank2", &state->rom[data * 0x2000 + 0x10000]);
562	563	}
563	564	else
564	565	{
565	566	/* RAM */
566	567	LOG_MMC(("\tRAM bank select (8k, $a000): %02x\n", data & 0x07));
567	568	/* The & 4 is a hack that'll tide us over for now */
568		memory_set_bankptr(space->machine, "bank2", &nes.wram[(data & 4) * 0x2000]);
	569	memory_set_bankptr(space->machine, "bank2", &state->wram[(data & 4) * 0x2000]);
569	570	}
570	571	break;
571	572	}
r7952	r7953
580	581	if (data & 0x80)
581	582	{
582	583	/* ROM */
583		data &= ((nes.prg_chunks << 1) - 1);
584		memory_set_bankptr(space->machine, "bank3", &nes.rom[data * 0x2000 + 0x10000]);
	584	data &= ((state->prg_chunks << 1) - 1);
	585	memory_set_bankptr(space->machine, "bank3", &state->rom[data * 0x2000 + 0x10000]);
585	586	}
586	587	else
587	588	{
588	589	/* RAM */
589	590	LOG_MMC(("\tRAM bank select (8k, $c000): %02x\n", data & 0x07));
590	591	/* The & 4 is a hack that'll tide us over for now */
591		memory_set_bankptr(space->machine, "bank3", &nes.wram[(data & 4)* 0x2000]);
	592	memory_set_bankptr(space->machine, "bank3", &state->wram[(data & 4)* 0x2000]);
592	593	}
593	594	break;
594	595	}
r7952	r7953
608	609	case 0x02:
609	610	case 0x03:
610	611	/* 8k switch */
611		data &= ((nes.prg_chunks << 1) - 1);
612		memory_set_bankptr(space->machine, "bank4", &nes.rom[data * 0x2000 + 0x10000]);
	612	data &= ((state->prg_chunks << 1) - 1);
	613	memory_set_bankptr(space->machine, "bank4", &state->rom[data * 0x2000 + 0x10000]);
613	614	break;
614	615	}
615	616	break;
r7952	r7953
936	937	{
937	938	case 0x1fe:
938	939	mmc_cmd1 = data & 0x80;
939		set_nt_mirroring((data & 0x10) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	940	set_nt_mirroring(space->machine, BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
940	941	break;
941	942	case 0x1ff:
942		set_nt_mirroring((data & 0x10) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	943	set_nt_mirroring(space->machine, BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
943	944	break;
944	945
945	946	case 0x401:
r7952	r7953
987	988	{
988	989	LOG_MMC(("mapper7_w, offset: %04x, data: %02x\n", offset, data));
989	990
990		set_nt_mirroring((data & 0x10) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	991	set_nt_mirroring(space->machine, BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
991	992	prg32(space->machine, data);
992	993	}
993	994
r7952	r7953
1078	1079	chr4_4(space->machine, MMC2_regs[3], CHRROM);
1079	1080	break;
1080	1081	case 0x7000:
1081		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1082	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1082	1083	break;
1083	1084	default:
1084	1085	LOG_MMC(("MMC2 uncaught w: %04x:%02x\n", offset, data));
r7952	r7953
1307	1308	mapper14_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
1308	1309
1309	1310	if (!(map14_reg[0] & 0x02))
1310		set_nt_mirroring(map14_reg[1] & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1311	set_nt_mirroring(space->machine, BIT(map14_reg[1], 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1311	1312	}
1312	1313
1313	1314	if (map14_reg[0] & 0x02)
r7952	r7953
1349	1350	break;
1350	1351
1351	1352	case 0x2000:
1352		set_nt_mirroring(map14_reg[1] & 0x01 ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	1353	set_nt_mirroring(space->machine, BIT(map14_reg[1], 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
1353	1354	break;
1354	1355
1355	1356	default:
r7952	r7953
1377	1378
1378	1379	case 0x1000:
1379	1380	map14_reg[1] = data;
1380		set_nt_mirroring(map14_reg[1] & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1381	set_nt_mirroring(space->machine, BIT(map14_reg[1], 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1381	1382	break;
1382	1383	}
1383	1384	}
r7952	r7953
1401	1402
1402	1403	LOG_MMC(("mapper15_w, offset: %04x, data: %02x\n", offset, data));
1403	1404
1404		set_nt_mirroring((data & 0x40) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1405	set_nt_mirroring(space->machine, BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1405	1406
1406	1407	switch (offset & 0x0fff)
1407	1408	{
r7952	r7953
1486	1487	case 9:
1487	1488	switch (data & 0x03)
1488	1489	{
1489		case 0: set_nt_mirroring(PPU_MIRROR_VERT); break;
1490		case 1: set_nt_mirroring(PPU_MIRROR_HORZ); break;
1491		case 2: set_nt_mirroring(PPU_MIRROR_LOW); break;
1492		case 3: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	1490	case 0: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	1491	case 1: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	1492	case 2: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	1493	case 3: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
1493	1494	}
1494	1495	break;
1495	1496	case 0x0a:
r7952	r7953
1533	1534	switch (offset)
1534	1535	{
1535	1536	case 0x1fe:
1536		set_nt_mirroring((data & 0x10) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	1537	set_nt_mirroring(space->machine, BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
1537	1538	break;
1538	1539	case 0x1ff:
1539		set_nt_mirroring((data & 0x10) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1540	set_nt_mirroring(space->machine, BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1540	1541	break;
1541	1542
1542	1543	case 0x401:
r7952	r7953
1708	1709	case 0x7002:
1709	1710	switch (data & 0x03)
1710	1711	{
1711		case 0: set_nt_mirroring(PPU_MIRROR_HORZ); break;
1712		case 1: set_nt_mirroring(PPU_MIRROR_VERT); break;
1713		case 2: set_nt_mirroring(PPU_MIRROR_LOW); break;
1714		case 3: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	1712	case 0: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	1713	case 1: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	1714	case 2: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	1715	case 3: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
1715	1716	}
1716	1717	break;
1717	1718
r7952	r7953
1786	1787	}
1787	1788	}
1788	1789
1789		static void mapper19_set_mirror( UINT8 page, UINT8 data )
	1790	static void mapper19_set_mirror( running_machine *machine, UINT8 page, UINT8 data )
1790	1791	{
1791	1792	if (!(data < 0xe0))
1792		set_nt_page(page, CIRAM, data & 0x01, 1);
	1793	set_nt_page(machine, page, CIRAM, data & 0x01, 1);
1793	1794	else
1794		set_nt_page(page, ROM, data, 0);
	1795	set_nt_page(machine, page, ROM, data, 0);
1795	1796	}
1796	1797
1797	1798	static WRITE8_HANDLER( mapper19_w )
r7952	r7953
1806	1807	chr1_x(space->machine, offset / 0x800, data, CHRROM);
1807	1808	break;
1808	1809	case 0x4000:
1809		mapper19_set_mirror(0, data);
	1810	mapper19_set_mirror(space->machine, 0, data);
1810	1811	break;
1811	1812	case 0x4800:
1812		mapper19_set_mirror(1, data);
	1813	mapper19_set_mirror(space->machine, 1, data);
1813	1814	break;
1814	1815	case 0x5000:
1815		mapper19_set_mirror(2, data);
	1816	mapper19_set_mirror(space->machine, 2, data);
1816	1817	break;
1817	1818	case 0x5800:
1818		mapper19_set_mirror(3, data);
	1819	mapper19_set_mirror(space->machine, 3, data);
1819	1820	break;
1820	1821	case 0x6000:
1821	1822	prg8_89(space->machine, data & 0x3f);
r7952	r7953
1846	1847
1847	1848	static void fds_irq( running_device *device, int scanline, int vblank, int blanked )
1848	1849	{
	1850	nes_state *state = (nes_state *)device->machine->driver_data;
	1851
1849	1852	if (IRQ_enable_latch)
1850	1853	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1851	1854
r7952	r7953
1855	1858	{
1856	1859	cputag_set_input_line(device->machine, "maincpu", M6502_IRQ_LINE, HOLD_LINE);
1857	1860	IRQ_enable = 0;
1858		nes_fds.status0 |= 0x01;
	1861	state->fds_status0 |= 0x01;
1859	1862	}
1860	1863	else
1861	1864	IRQ_count -= 114;
r7952	r7953
1864	1867
1865	1868	READ8_HANDLER( nes_fds_r )
1866	1869	{
	1870	nes_state *state = (nes_state *)space->machine->driver_data;
1867	1871	UINT8 ret = 0x00;
1868	1872	LOG_MMC(("fds_r, offset: %04x\n", offset));
1869	1873
1870	1874	switch (offset)
1871	1875	{
1872	1876	case 0x00: /* $4030 - disk status 0 */
1873		ret = nes_fds.status0;
	1877	ret = state->fds_status0;
1874	1878	/* clear the disk IRQ detect flag */
1875		nes_fds.status0 &= ~0x01;
	1879	state->fds_status0 &= ~0x01;
1876	1880	break;
1877	1881	case 0x01: /* $4031 - data latch */
1878	1882	/* don't read data if disk is unloaded */
1879		if (nes_fds.data == NULL)
	1883	if (state->fds_data == NULL)
1880	1884	ret = 0;
1881		else if (nes_fds.current_side)
1882		ret = nes_fds.data[(nes_fds.current_side-1) * 65500 + nes_fds.head_position++];
	1885	else if (state->fds_current_side)
	1886	ret = state->fds_data[(state->fds_current_side - 1) * 65500 + state->fds_head_position++];
1883	1887	else
1884	1888	ret = 0;
1885	1889	break;
1886	1890	case 0x02: /* $4032 - disk status 1 */
1887	1891	/* return "no disk" status if disk is unloaded */
1888		if (nes_fds.data == NULL)
	1892	if (state->fds_data == NULL)
1889	1893	ret = 1;
1890		else if (fds_last_side != nes_fds.current_side)
	1894	else if (fds_last_side != state->fds_current_side)
1891	1895	{
1892	1896	/* If we've switched disks, report "no disk" for a few reads */
1893	1897	ret = 1;
1894	1898	fds_count ++;
1895	1899	if (fds_count == 50)
1896	1900	{
1897		fds_last_side = nes_fds.current_side;
	1901	fds_last_side = state->fds_current_side;
1898	1902	fds_count = 0;
1899	1903	}
1900	1904	}
1901	1905	else
1902		ret = (nes_fds.current_side == 0); /* 0 if a disk is inserted */
	1906	ret = (state->fds_current_side == 0); /* 0 if a disk is inserted */
1903	1907	break;
1904	1908	case 0x03: /* $4033 */
1905	1909	ret = 0x80;
r7952	r7953
1916	1920
1917	1921	WRITE8_HANDLER( nes_fds_w )
1918	1922	{
	1923	nes_state *state = (nes_state *)space->machine->driver_data;
1919	1924	LOG_MMC(("fds_w, offset: %04x, data: %02x\n", offset, data));
1920	1925
1921	1926	switch (offset)
r7952	r7953
1938	1943	/* write data out to disk */
1939	1944	break;
1940	1945	case 0x05:
1941		nes_fds.motor_on = data & 0x01;
	1946	state->fds_motor_on = BIT(data, 0);
1942	1947
1943		if (data & 0x02)
1944		nes_fds.head_position = 0;
	1948	if (BIT(data, 1))
	1949	state->fds_head_position = 0;
1945	1950
1946		nes_fds.read_mode = data & 0x04;
1947		set_nt_mirroring((data & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1951	state->fds_read_mode = BIT(data, 2);
	1952	set_nt_mirroring(space->machine, BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1948	1953
1949		if ((!(data & 0x40)) && (nes_fds.write_reg & 0x40))
1950		nes_fds.head_position -= 2; // ???
	1954	if ((!(data & 0x40)) && (state->fds_write_reg & 0x40))
	1955	state->fds_head_position -= 2; // ???
1951	1956
1952		IRQ_enable_latch = data & 0x80;
1953		nes_fds.write_reg = data;
	1957	IRQ_enable_latch = BIT(data, 7);
	1958	state->fds_write_reg = data;
1954	1959	break;
1955	1960	}
1956	1961
r7952	r7953
2016	2021	case 0x1040:
2017	2022	switch (data & 0x03)
2018	2023	{
2019		case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
2020		case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
2021		case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
2022		case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	2024	case 0x00: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	2025	case 0x01: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	2026	case 0x02: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	2027	case 0x03: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
2023	2028	}
2024	2029	break;
2025	2030
r7952	r7953
2165	2170	case 0x1008:
2166	2171	switch (data & 0x03)
2167	2172	{
2168		case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
2169		case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
2170		case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
2171		case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	2173	case 0x00: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	2174	case 0x01: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	2175	case 0x02: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	2176	case 0x03: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
2172	2177	}
2173	2178	break;
2174	2179
r7952	r7953
2316	2321	case 0x1000:
2317	2322	switch (data & 0x03)
2318	2323	{
2319		case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
2320		case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
2321		case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
2322		case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	2324	case 0x00: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	2325	case 0x01: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	2326	case 0x02: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	2327	case 0x03: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
2323	2328	}
2324	2329	break;
2325	2330	case 0x2000:
r7952	r7953
2373	2378	case 0x1000:
2374	2379	switch (data & 0x03)
2375	2380	{
2376		case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
2377		case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
2378		case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
2379		case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	2381	case 0x00: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	2382	case 0x01: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	2383	case 0x02: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	2384	case 0x03: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
2380	2385	}
2381	2386	break;
2382	2387	case 0x2000:
r7952	r7953
2472	2477	case 0x3003:
2473	2478	switch (data & 0x0c)
2474	2479	{
2475		case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
2476		case 0x04: set_nt_mirroring(PPU_MIRROR_HORZ); break;
2477		case 0x08: set_nt_mirroring(PPU_MIRROR_LOW); break;
2478		case 0x0c: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	2480	case 0x00: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	2481	case 0x04: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	2482	case 0x08: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	2483	case 0x0c: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
2479	2484	}
2480	2485	break;
2481	2486	case 0x4000:
r7952	r7953
2546	2551	case 0x3003:
2547	2552	switch (data & 0x0c)
2548	2553	{
2549		case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
2550		case 0x04: set_nt_mirroring(PPU_MIRROR_HORZ); break;
2551		case 0x08: set_nt_mirroring(PPU_MIRROR_LOW); break;
2552		case 0x0c: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	2554	case 0x00: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	2555	case 0x04: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	2556	case 0x08: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	2557	case 0x0c: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
2553	2558	}
2554	2559	break;
2555	2560	case 0x4000: case 0x4001: case 0x4002: case 0x4003:
r7952	r7953
2658	2663
2659	2664	static WRITE8_HANDLER( mapper32_w )
2660	2665	{
	2666	nes_state *state = (nes_state *)space->machine->driver_data;
2661	2667	LOG_MMC(("mapper32_w, offset: %04x, data: %02x\n", offset, data));
2662	2668
2663	2669	switch (offset & 0x7000)
r7952	r7953
2667	2673	break;
2668	2674	case 0x1000:
2669	2675	mmc_cmd1 = data & 0x02;
2670		if (!nes.crc_hack)   // Major League has hardwired mirroring (it would have required a separate mapper)
2671		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	2676	if (!state->crc_hack)   // Major League has hardwired mirroring (it would have required a separate mapper)
	2677	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
2672	2678	break;
2673	2679	case 0x2000:
2674	2680	prg8_ab(space->machine, data);
r7952	r7953
2702	2708	switch (offset & 0x6003)
2703	2709	{
2704	2710	case 0x0000:
2705		set_nt_mirroring((data & 0x40) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	2711	set_nt_mirroring(space->machine, BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
2706	2712	prg8_89(space->machine, data);
2707	2713	break;
2708	2714	case 0x0001:
r7952	r7953
2748	2754
2749	2755	static WRITE8_HANDLER( mapper34_m_w )
2750	2756	{
	2757	nes_state *state = (nes_state *)space->machine->driver_data;
2751	2758	LOG_MMC(("mapper34_m_w, offset: %04x, data: %02x\n", offset, data));
2752	2759
2753		if (nes.crc_hack)   // is it AVE Nina-01?
	2760	if (state->crc_hack)   // is it AVE Nina-01?
2754	2761	{
2755	2762	switch (offset)
2756	2763	{
r7952	r7953
2771	2778	{
2772	2779	/* This portion of the mapper is nearly identical to Mapper 7, except no one-screen mirroring */
2773	2780	/* Deadly Towers is really a Mapper 34 game - the demo screens look wrong using mapper 7. */
	2781	nes_state *state = (nes_state *)space->machine->driver_data;
2774	2782	LOG_MMC(("mapper34_w, offset: %04x, data: %02x\n", offset, data));
2775	2783
2776		if (!nes.crc_hack)   // is it plain BxROM?
	2784	if (!state->crc_hack)   // is it plain BxROM?
2777	2785	prg32(space->machine, data);
2778	2786	}
2779	2787
r7952	r7953
2841	2849	IRQ_count = data;
2842	2850	break;
2843	2851	case 0x5001:
2844		set_nt_mirroring(data & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	2852	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
2845	2853	break;
2846	2854	}
2847	2855	}
r7952	r7953
2994	3002	LOG_MMC(("mapper41_m_w, offset: %04x, data: %02x\n", offset, data));
2995	3003
2996	3004	mmc_cmd1 = offset & 0xff;
2997		set_nt_mirroring((offset & 0x20) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3005	set_nt_mirroring(space->machine, BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
2998	3006	prg32(space->machine, offset & 0x07);
2999	3007	}
3000	3008
r7952	r7953
3031	3039	prg8_67(space->machine, data);
3032	3040	break;
3033	3041	case 0x01:
3034		set_nt_mirroring((data & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3042	set_nt_mirroring(space->machine, BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3035	3043	break;
3036	3044	case 0x02:
3037	3045	/* Check if IRQ is being enabled */
r7952	r7953
3064	3072
3065	3073	static WRITE8_HANDLER( mapper43_w )
3066	3074	{
	3075	nes_state *state = (nes_state *)space->machine->driver_data;
3067	3076	int bank = (((offset >> 8) & 0x03) * 0x20) + (offset & 0x1f);
3068	3077
3069	3078	LOG_MMC(("mapper43_w, offset: %04x, data: %02x\n", offset, data));
3070	3079
3071		set_nt_mirroring((offset& 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3080	set_nt_mirroring(space->machine, (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3072	3081
3073	3082	if (offset & 0x0800)
3074	3083	{
3075	3084	if (offset & 0x1000)
3076	3085	{
3077		if (bank * 2 >= nes.prg_chunks)
	3086	if (bank * 2 >= state->prg_chunks)
3078	3087	{
3079		memory_set_bankptr(space->machine, "bank3", nes.wram);
3080		memory_set_bankptr(space->machine, "bank4", nes.wram);
	3088	memory_set_bankptr(space->machine, "bank3", state->wram);
	3089	memory_set_bankptr(space->machine, "bank4", state->wram);
3081	3090	}
3082	3091	else
3083	3092	{
r7952	r7953
3087	3096	}
3088	3097	else
3089	3098	{
3090		if (bank * 2 >= nes.prg_chunks)
	3099	if (bank * 2 >= state->prg_chunks)
3091	3100	{
3092		memory_set_bankptr(space->machine, "bank1", nes.wram);
3093		memory_set_bankptr(space->machine, "bank2", nes.wram);
	3101	memory_set_bankptr(space->machine, "bank1", state->wram);
	3102	memory_set_bankptr(space->machine, "bank2", state->wram);
3094	3103	}
3095	3104	else
3096	3105	{
r7952	r7953
3101	3110	}
3102	3111	else
3103	3112	{
3104		if (bank * 2 >= nes.prg_chunks)
	3113	if (bank * 2 >= state->prg_chunks)
3105	3114	{
3106		memory_set_bankptr(space->machine, "bank1", nes.wram);
3107		memory_set_bankptr(space->machine, "bank2", nes.wram);
3108		memory_set_bankptr(space->machine, "bank3", nes.wram);
3109		memory_set_bankptr(space->machine, "bank4", nes.wram);
	3115	memory_set_bankptr(space->machine, "bank1", state->wram);
	3116	memory_set_bankptr(space->machine, "bank2", state->wram);
	3117	memory_set_bankptr(space->machine, "bank3", state->wram);
	3118	memory_set_bankptr(space->machine, "bank4", state->wram);
3110	3119	}
3111	3120	else
3112	3121	{
r7952	r7953
3166	3175
3167	3176	static WRITE8_HANDLER( mapper45_m_w )
3168	3177	{
	3178	nes_state *state = (nes_state *)space->machine->driver_data;
3169	3179	LOG_MMC(("mapper45_m_w, offset: %04x, data: %02x\n", offset, data));
3170	3180
3171	3181	/* This bit is the "register lock". Once register are locked, writes go to WRAM
3172	3182	and there is no way to unlock them (except by resetting the machine) */
3173	3183	if (mapper45_reg[3] & 0x40)
3174		nes.wram[offset] = data;
	3184	state->wram[offset] = data;
3175	3185	else
3176	3186	{
3177	3187	mapper45_reg[mmc_count] = data;
r7952	r7953
3307	3317	IRQ_enable = 0;
3308	3318	break;
3309	3319	case 0x6000:
3310		set_nt_mirroring((data & 0x40) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3320	set_nt_mirroring(space->machine, BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3311	3321	break;
3312	3322	}
3313	3323	}
r7952	r7953
3419	3429
3420	3430	static void mapper51_set_banks( running_machine *machine )
3421	3431	{
3422		set_nt_mirroring((mapper51_reg[0] == 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3432	set_nt_mirroring(machine, (mapper51_reg[0] == 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3423	3433
3424	3434	if (mapper51_reg[0] & 0x01)
3425	3435	{
r7952	r7953
3472	3482
3473	3483	static WRITE8_HANDLER( mapper52_m_w )
3474	3484	{
	3485	nes_state *state = (nes_state *)space->machine->driver_data;
3475	3486	UINT8 map52_helper1, map52_helper2;
3476	3487	LOG_MMC(("mapper52_m_w, offset: %04x, data: %02x\n", offset, data));
3477	3488
r7952	r7953
3493	3504	map52_reg_written = 1;
3494	3505	}
3495	3506	else
3496		nes.wram[offset] = data;
	3507	state->wram[offset] = data;
3497	3508	}
3498	3509
3499	3510	/*************************************************************
r7952	r7953
3585	3596	prg16_cdef(space->machine, (mmc_cmd2 >> 5) & 0x03);
3586	3597	}
3587	3598
3588		set_nt_mirroring((mmc_cmd2 & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3599	set_nt_mirroring(space->machine, (mmc_cmd2 & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3589	3600
3590	3601	chr8(space->machine, (mmc_cmd1 & 0x03) | (mmc_cmd2 & 0x07) | ((mmc_cmd2 & 0x10) >> 1), CHRROM);
3591	3602	}
r7952	r7953
3609	3620	prg16_89ab(space->machine, offset & ~bank);
3610	3621	prg16_cdef(space->machine, offset | bank);
3611	3622	chr8(space->machine, offset >> 3, CHRROM);
3612		set_nt_mirroring((data & 0x80) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3623	set_nt_mirroring(space->machine, BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3613	3624	}
3614	3625
3615	3626	/*************************************************************
r7952	r7953
3667	3678	prg16_cdef(space->machine, ((offset & 0x0f) << 1) | ((offset & 0x20) >> 4));
3668	3679	break;
3669	3680	}
3670		set_nt_mirroring((offset & 0x80) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3681	set_nt_mirroring(space->machine, BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3671	3682	}
3672	3683
3673	3684	/*************************************************************
r7952	r7953
3697	3708	prg32(space->machine, ((offset & 0x40) | ((offset >> 8) & 0x3f)) >> 1);
3698	3709	}
3699	3710
3700		set_nt_mirroring((offset & 0x80) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3711	set_nt_mirroring(space->machine, BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3701	3712	}
3702	3713
3703	3714	/*************************************************************
r7952	r7953
3859	3870	break;
3860	3871
3861	3872	case 0x2000:
3862		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3873	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3863	3874	break;
3864	3875
3865	3876	case 0x4000:
r7952	r7953
3925	3936	break;
3926	3937
3927	3938	case 0x1001:
3928		set_nt_mirroring((data & 0x80) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3939	set_nt_mirroring(space->machine, BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3929	3940	break;
3930	3941
3931	3942	case 0x1003:
r7952	r7953
4051	4062	case 0x6800:
4052	4063	switch (data & 3)
4053	4064	{
4054		case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
4055		case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
4056		case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
4057		case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	4065	case 0x00: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	4066	case 0x01: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	4067	case 0x02: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	4068	case 0x03: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
4058	4069	}
4059	4070	break;
4060	4071	case 0x7800:
r7952	r7953
4082	4093	switch (mirror)
4083	4094	{
4084	4095	case 0x00:
4085		set_nt_mirroring(PPU_MIRROR_HORZ);
	4096	set_nt_mirroring(machine, PPU_MIRROR_HORZ);
4086	4097	break;
4087	4098	case 0x01:
4088		set_nt_mirroring(PPU_MIRROR_VERT);
	4099	set_nt_mirroring(machine, PPU_MIRROR_VERT);
4089	4100	break;
4090	4101	case 0x02:
4091		set_nt_mirroring(PPU_MIRROR_LOW);
	4102	set_nt_mirroring(machine, PPU_MIRROR_LOW);
4092	4103	break;
4093	4104	case 0x03:
4094		set_nt_mirroring(PPU_MIRROR_HIGH);
	4105	set_nt_mirroring(machine, PPU_MIRROR_HIGH);
4095	4106	break;
4096	4107	case 0x10:
4097		set_nt_page(0, ROM, mirr0 | 0x80, 0);
4098		set_nt_page(1, ROM, mirr1 | 0x80, 0);
4099		set_nt_page(2, ROM, mirr0 | 0x80, 0);
4100		set_nt_page(3, ROM, mirr1 | 0x80, 0);
	4108	set_nt_page(machine, 0, ROM, mirr0 | 0x80, 0);
	4109	set_nt_page(machine, 1, ROM, mirr1 | 0x80, 0);
	4110	set_nt_page(machine, 2, ROM, mirr0 | 0x80, 0);
	4111	set_nt_page(machine, 3, ROM, mirr1 | 0x80, 0);
4101	4112	break;
4102	4113	case 0x11:
4103		set_nt_page(0, ROM, mirr0 | 0x80, 0);
4104		set_nt_page(1, ROM, mirr0 | 0x80, 0);
4105		set_nt_page(2, ROM, mirr1 | 0x80, 0);
4106		set_nt_page(3, ROM, mirr1 | 0x80, 0);
	4114	set_nt_page(machine, 0, ROM, mirr0 | 0x80, 0);
	4115	set_nt_page(machine, 1, ROM, mirr0 | 0x80, 0);
	4116	set_nt_page(machine, 2, ROM, mirr1 | 0x80, 0);
	4117	set_nt_page(machine, 3, ROM, mirr1 | 0x80, 0);
4107	4118	break;
4108	4119	case 0x12:
4109		set_nt_page(0, ROM, mirr0 | 0x80, 0);
4110		set_nt_page(1, ROM, mirr0 | 0x80, 0);
4111		set_nt_page(2, ROM, mirr0 | 0x80, 0);
4112		set_nt_page(3, ROM, mirr0 | 0x80, 0);
	4120	set_nt_page(machine, 0, ROM, mirr0 | 0x80, 0);
	4121	set_nt_page(machine, 1, ROM, mirr0 | 0x80, 0);
	4122	set_nt_page(machine, 2, ROM, mirr0 | 0x80, 0);
	4123	set_nt_page(machine, 3, ROM, mirr0 | 0x80, 0);
4113	4124	break;
4114	4125	case 0x13:
4115		set_nt_page(0, ROM, mirr1 | 0x80, 0);
4116		set_nt_page(1, ROM, mirr1 | 0x80, 0);
4117		set_nt_page(2, ROM, mirr1 | 0x80, 0);
4118		set_nt_page(3, ROM, mirr1 | 0x80, 0);
	4126	set_nt_page(machine, 0, ROM, mirr1 | 0x80, 0);
	4127	set_nt_page(machine, 1, ROM, mirr1 | 0x80, 0);
	4128	set_nt_page(machine, 2, ROM, mirr1 | 0x80, 0);
	4129	set_nt_page(machine, 3, ROM, mirr1 | 0x80, 0);
4119	4130	break;
4120	4131	}
4121	4132	}
r7952	r7953
4198	4209
4199	4210	static WRITE8_HANDLER( mapper69_w )
4200	4211	{
	4212	nes_state *state = (nes_state *)space->machine->driver_data;
4201	4213	LOG_MMC(("mapper69_w, offset %04x, data: %02x\n", offset, data));
4202	4214
4203	4215	switch (offset & 0x6000)
r7952	r7953
4218	4230	if (!(data & 0x40))
4219	4231	prg8_67(space->machine, data & 0x3f);
4220	4232	else if (data & 0x80)
4221		memory_set_bankptr(space->machine, "bank5", &nes.wram[(data & 0x3f) * 0x2000]);
	4233	memory_set_bankptr(space->machine, "bank5", &state->wram[(data & 0x3f) * 0x2000]);
4222	4234	break;
4223	4235
4224	4236	case 9:
r7952	r7953
4233	4245	case 0x0c:
4234	4246	switch (data & 0x03)
4235	4247	{
4236		case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
4237		case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
4238		case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
4239		case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	4248	case 0x00: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	4249	case 0x01: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	4250	case 0x02: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	4251	case 0x03: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
4240	4252	}
4241	4253	break;
4242	4254	case 0x0d:
r7952	r7953
4303	4315
4304	4316	static WRITE8_HANDLER( mapper71_w )
4305	4317	{
	4318	nes_state *state = (nes_state *)space->machine->driver_data;
4306	4319	LOG_MMC(("mapper71_w offset: %04x, data: %02x\n", offset, data));
4307	4320
4308	4321	switch (offset & 0x7000)
4309	4322	{
4310	4323	case 0x0000:
4311	4324	case 0x1000:
4312		if (nes.crc_hack)
4313		set_nt_mirroring((data & 0x10) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	4325	if (state->crc_hack)
	4326	set_nt_mirroring(space->machine, BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
4314	4327	break;
4315	4328	case 0x4000:
4316	4329	case 0x5000:
r7952	r7953
4403	4416	*************************************************************/
4404	4417
4405	4418	/* MIRROR_LOW and MIRROR_HIGH are swapped! */
4406		static void waixing_set_mirror( UINT8 nt )
	4419	static void waixing_set_mirror( running_machine *machine, UINT8 nt )
4407	4420	{
4408	4421	switch (nt)
4409	4422	{
4410	4423	case 0:
4411	4424	case 1:
4412		set_nt_mirroring(nt ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	4425	set_nt_mirroring(machine, nt ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4413	4426	break;
4414	4427	case 2:
4415		set_nt_mirroring(PPU_MIRROR_LOW);
	4428	set_nt_mirroring(machine, PPU_MIRROR_LOW);
4416	4429	break;
4417	4430	case 3:
4418		set_nt_mirroring(PPU_MIRROR_HIGH);
	4431	set_nt_mirroring(machine, PPU_MIRROR_HIGH);
4419	4432	break;
4420	4433	default:
4421	4434	LOG_MMC(("Mapper set NT to invalid value %02x", nt));
r7952	r7953
4480	4493	break;
4481	4494
4482	4495	case 0x2000:
4483		waixing_set_mirror(data);   //maybe data & 0x03?
	4496	waixing_set_mirror(space->machine, data);   //maybe data & 0x03?
4484	4497	break;
4485	4498
4486	4499	case 0x2001:
r7952	r7953
4513	4526	prg8_89(space->machine, data);
4514	4527	break;
4515	4528	case 0x1000:
4516		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	4529	set_nt_mirroring(space->machine, (data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4517	4530	vrom_bank[0] = (vrom_bank[0] & 0x0f) | ((data & 0x02) << 3);
4518	4531	vrom_bank[1] = (vrom_bank[1] & 0x0f) | ((data & 0x04) << 2);
4519	4532	chr4_0(space->machine, vrom_bank[0], CHRROM);
r7952	r7953
4572	4585	}
4573	4586	}
4574	4587	case 0x2000:
4575		set_nt_mirroring((data & 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	4588	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4576	4589	break;
4577	4590	default:
4578	4591	logerror("mapper76 unmapped write, offset: %04x, data: %02x\n", offset, data);
r7952	r7953
4616	4629
4617	4630	static WRITE8_HANDLER( mapper78_w )
4618	4631	{
	4632	nes_state *state = (nes_state *)space->machine->driver_data;
4619	4633	LOG_MMC(("mapper78_w, offset: %04x, data: %02x\n", offset, data));
4620	4634
4621		if (nes.crc_hack)      // Jaleco JF16 board has different mirroring even if uses same mapper number :(
4622		set_nt_mirroring((data & 0x08) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	4635	if (state->crc_hack)      // Jaleco JF16 board has different mirroring even if uses same mapper number :(
	4636	set_nt_mirroring(space->machine, BIT(data, 3) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
4623	4637	else
4624		set_nt_mirroring((data & 0x08) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	4638	set_nt_mirroring(space->machine, BIT(data, 3) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
4625	4639
4626	4640	chr8(space->machine, (data & 0xf0) >> 4, CHRROM);
4627	4641	prg16_89ab(space->machine, data & 0x07);
r7952	r7953
4691	4705	chr1_7(space->machine, data, CHRROM);
4692	4706	break;
4693	4707	case 0x1ef6:
4694		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	4708	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
4695	4709	break;
4696	4710	case 0x1efa:
4697	4711	case 0x1efb:
r7952	r7953
4765	4779	chr1_x(space->machine, 7 ^ mmc_cmd1, data, CHRROM);
4766	4780	break;
4767	4781	case 0x1ef6:
4768		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	4782	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
4769	4783	mmc_cmd1 = ((data & 0x02) << 1);
4770	4784	break;
4771	4785
r7952	r7953
4842	4856	switch (data & 0x03)
4843	4857	{
4844	4858	case 0:
4845		set_nt_mirroring(PPU_MIRROR_VERT);
	4859	set_nt_mirroring(space->machine, PPU_MIRROR_VERT);
4846	4860	break;
4847	4861	case 1:
4848		set_nt_mirroring(PPU_MIRROR_HORZ);
	4862	set_nt_mirroring(space->machine, PPU_MIRROR_HORZ);
4849	4863	break;
4850	4864	case 2:
4851		set_nt_mirroring(PPU_MIRROR_LOW);
	4865	set_nt_mirroring(space->machine, PPU_MIRROR_LOW);
4852	4866	break;
4853	4867	case 3:
4854		set_nt_mirroring(PPU_MIRROR_HIGH);
	4868	set_nt_mirroring(space->machine, PPU_MIRROR_HIGH);
4855	4869	break;
4856	4870	}
4857	4871	break;
r7952	r7953
4956	4970	case 0x6000:
4957	4971	switch (data & 0x03)
4958	4972	{
4959		case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
4960		case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
4961		case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
4962		case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	4973	case 0x00: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	4974	case 0x01: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	4975	case 0x02: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	4976	case 0x03: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
4963	4977	}
4964	4978	break;
4965	4979	case 0x6008: case 0x6010: case 0x6018:
r7952	r7953
5080	5094
5081	5095	prg16_89ab(space->machine, (data >> 4) & 0x07);
5082	5096	chr8(space->machine, map89_helper, CHRROM);
5083		set_nt_mirroring((data & 0x08) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	5097	set_nt_mirroring(space->machine, BIT(data, 3) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
5084	5098	}
5085	5099
5086	5100	/*************************************************************
r7952	r7953
5243	5257	mapper95_reg[mmc_cmd1 - 2] = data & 0x20;
5244	5258	if (!(mmc_cmd1 & 0x80))
5245	5259	{
5246		set_nt_page(0, CIRAM, mapper95_reg[0] ? 1 : 0, 1);
5247		set_nt_page(1, CIRAM, mapper95_reg[1] ? 1 : 0, 1);
5248		set_nt_page(2, CIRAM, mapper95_reg[2] ? 1 : 0, 1);
5249		set_nt_page(3, CIRAM, mapper95_reg[3] ? 1 : 0, 1);
	5260	set_nt_page(space->machine, 0, CIRAM, mapper95_reg[0] ? 1 : 0, 1);
	5261	set_nt_page(space->machine, 1, CIRAM, mapper95_reg[1] ? 1 : 0, 1);
	5262	set_nt_page(space->machine, 2, CIRAM, mapper95_reg[2] ? 1 : 0, 1);
	5263	set_nt_page(space->machine, 3, CIRAM, mapper95_reg[3] ? 1 : 0, 1);
5250	5264	}
5251	5265	else
5252		set_nt_mirroring(PPU_MIRROR_HORZ);
	5266	set_nt_mirroring(space->machine, PPU_MIRROR_HORZ);
5253	5267	break;
5254	5268	case 6:
5255	5269	prg8_89(space->machine,data & 0x1f);
r7952	r7953
5299	5313
5300	5314	if (offset < 0x4000)
5301	5315	{
5302		set_nt_mirroring((data & 0x80) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	5316	set_nt_mirroring(space->machine, BIT(data, 7) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
5303	5317	prg16_cdef(space->machine, data & 0x0f);
5304	5318	}
5305	5319	}
r7952	r7953
5482	5496	prg8_ef(space->machine, data | 0x10);
5483	5497	break;
5484	5498	case 0x0c:
5485		set_nt_mirroring((data & 0x01) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5499	set_nt_mirroring(space->machine, BIT(data, 0) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5486	5500	break;
5487	5501	case 0x0d:
5488	5502	IRQ_count = 0;
r7952	r7953
5624	5638	}
5625	5639	break;
5626	5640	case 0x6000:
5627		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5641	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5628	5642	break;
5629	5643	}
5630	5644	}
r7952	r7953
5643	5657
5644	5658	static WRITE8_HANDLER( mapper113_l_w )
5645	5659	{
	5660	nes_state *state = (nes_state *)space->machine->driver_data;
5646	5661	LOG_MMC(("mapper113_w, offset: %04x, data: %02x\n", offset, data));
5647	5662
5648	5663	if (!(offset & 0x100))
5649	5664	{
5650	5665	prg32(space->machine, (data & 0x38) >> 3);
5651	5666	chr8(space->machine, (data & 0x07) | ((data & 0x40) >> 3), CHRROM);
5652		if (nes.crc_hack)   // this breaks AV Soccer but it is needed by HES 6-in-1!
5653		set_nt_mirroring((data & 0x80) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	5667	if (state->crc_hack)   // this breaks AV Soccer but it is needed by HES 6-in-1!
	5668	set_nt_mirroring(space->machine, BIT(data, 7) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
5654	5669	}
5655	5670	}
5656	5671
r7952	r7953
5693	5708	switch (offset & 0x6000)
5694	5709	{
5695	5710	case 0x0000:
5696		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5711	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5697	5712	break;
5698	5713	case 0x2000:
5699	5714	map114_reg_enabled = 1;
r7952	r7953
5872	5887	break;
5873	5888
5874	5889	case 0x5000:
5875		set_nt_mirroring((data & 0x01) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5890	set_nt_mirroring(space->machine, BIT(data, 0) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5876	5891	break;
5877	5892
5878	5893	case 0x4001:
r7952	r7953
5902	5917
5903	5918	*************************************************************/
5904	5919
5905		static void mapper118_set_mirror( void )
	5920	static void mapper118_set_mirror( running_machine *machine )
5906	5921	{
5907	5922	if (mmc_cmd1 & 0x80)
5908	5923	{
5909		set_nt_page(0, CIRAM, (vrom_bank[2] & 0x80) >> 7, 1);
5910		set_nt_page(1, CIRAM, (vrom_bank[3] & 0x80) >> 7, 1);
5911		set_nt_page(2, CIRAM, (vrom_bank[4] & 0x80) >> 7, 1);
5912		set_nt_page(3, CIRAM, (vrom_bank[5] & 0x80) >> 7, 1);
	5924	set_nt_page(machine, 0, CIRAM, (vrom_bank[2] & 0x80) >> 7, 1);
	5925	set_nt_page(machine, 1, CIRAM, (vrom_bank[3] & 0x80) >> 7, 1);
	5926	set_nt_page(machine, 2, CIRAM, (vrom_bank[4] & 0x80) >> 7, 1);
	5927	set_nt_page(machine, 3, CIRAM, (vrom_bank[5] & 0x80) >> 7, 1);
5913	5928	}
5914	5929	else
5915	5930	{
5916		set_nt_page(0, CIRAM, (vrom_bank[0] & 0x80) >> 7, 1);
5917		set_nt_page(1, CIRAM, (vrom_bank[0] & 0x80) >> 7, 1);
5918		set_nt_page(2, CIRAM, (vrom_bank[1] & 0x80) >> 7, 1);
5919		set_nt_page(3, CIRAM, (vrom_bank[1] & 0x80) >> 7, 1);
	5931	set_nt_page(machine, 0, CIRAM, (vrom_bank[0] & 0x80) >> 7, 1);
	5932	set_nt_page(machine, 1, CIRAM, (vrom_bank[0] & 0x80) >> 7, 1);
	5933	set_nt_page(machine, 2, CIRAM, (vrom_bank[1] & 0x80) >> 7, 1);
	5934	set_nt_page(machine, 3, CIRAM, (vrom_bank[1] & 0x80) >> 7, 1);
5920	5935	}
5921	5936	}
5922	5937
r7952	r7953
5938	5953	/* Has CHR Mode changed? */
5939	5954	if (MMC3_helper & 0x80)
5940	5955	{
5941		mapper118_set_mirror();
	5956	mapper118_set_mirror(space->machine);
5942	5957	mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
5943	5958	}
5944	5959	break;
r7952	r7953
5950	5965	case 0: case 1:
5951	5966	case 2: case 3: case 4: case 5:
5952	5967	vrom_bank[cmd] = data;
5953		mapper118_set_mirror();
	5968	mapper118_set_mirror(space->machine);
5954	5969	mapper4_set_chr(space->machine, mmc_chr_source, mmc_chr_base, mmc_chr_mask);
5955	5970	break;
5956	5971	case 6:
r7952	r7953
6212	6227	Mapper 123
6213	6228
6214	6229	Known Boards: Bootleg Board ???
6215		Games: [no games in nes.hsi]
	6230	Games: [no games in state->hsi]
6216	6231
6217	6232	In MESS: Unsupported.
6218	6233
r7952	r7953
6245	6260	Mapper 126
6246	6261
6247	6262	Known Boards: Unknown Multigame Bootleg Board
6248		Games: [no games in nes.hsi]
	6263	Games: [no games in state->hsi]
6249	6264
6250	6265	In MESS: Unsupported.
6251	6266
r7952	r7953
6455	6470
6456	6471	*************************************************************/
6457	6472
6458		static void sachen_set_mirror( UINT8 nt ) // used by mappers 137, 138, 139, 141
	6473	static void sachen_set_mirror( running_machine *machine, UINT8 nt ) // used by mappers 137, 138, 139, 141
6459	6474	{
6460	6475	switch (nt)
6461	6476	{
6462	6477	case 0:
6463	6478	case 1:
6464		set_nt_mirroring(nt ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	6479	set_nt_mirroring(machine, nt ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
6465	6480	break;
6466	6481	case 2:
6467		set_nt_page(0, CIRAM, 0, 1);
6468		set_nt_page(1, CIRAM, 1, 1);
6469		set_nt_page(2, CIRAM, 1, 1);
6470		set_nt_page(3, CIRAM, 1, 1);
	6482	set_nt_page(machine, 0, CIRAM, 0, 1);
	6483	set_nt_page(machine, 1, CIRAM, 1, 1);
	6484	set_nt_page(machine, 2, CIRAM, 1, 1);
	6485	set_nt_page(machine, 3, CIRAM, 1, 1);
6471	6486	break;
6472	6487	case 3:
6473		set_nt_mirroring(PPU_MIRROR_LOW);
	6488	set_nt_mirroring(machine, PPU_MIRROR_LOW);
6474	6489	break;
6475	6490	default:
6476	6491	LOG_MMC(("Mapper set NT to invalid value %02x", nt));
r7952	r7953
6497	6512	prg32(space->machine, data);
6498	6513	break;
6499	6514	case 0x07:
6500		sachen_set_mirror((data & 0x01) ? 0 : (data >> 1) & 0x03);
	6515	sachen_set_mirror(space->machine, BIT(data, 0) ? 0 : (data >> 1) & 0x03);
6501	6516	break;
6502	6517	default:
6503	6518	if (mmc_chr_source == CHRROM)
r7952	r7953
6551	6566	prg32(space->machine, data);
6552	6567	break;
6553	6568	case 0x07:
6554		sachen_set_mirror((data & 0x01) ? 0 : (data >> 1) & 0x03);
	6569	sachen_set_mirror(space->machine, BIT(data, 0) ? 0 : (data >> 1) & 0x03);
6555	6570	break;
6556	6571	default:
6557	6572	if (mmc_chr_source == CHRROM)
r7952	r7953
6607	6622	prg32(space->machine, data);
6608	6623	break;
6609	6624	case 0x07:
6610		sachen_set_mirror((data & 0x01) ? 0 : (data >> 1) & 0x03);
	6625	sachen_set_mirror(space->machine, BIT(data, 0) ? 0 : (data >> 1) & 0x03);
6611	6626	break;
6612	6627	default:
6613	6628	if (mmc_chr_source == CHRROM)
r7952	r7953
6683	6698	prg32(space->machine, data);
6684	6699	break;
6685	6700	case 0x07:
6686		sachen_set_mirror((data & 0x01) ? 0 : (data >> 1) & 0x03);
	6701	sachen_set_mirror(space->machine, BIT(data, 0) ? 0 : (data >> 1) & 0x03);
6687	6702	break;
6688	6703	default:
6689	6704	if (mmc_chr_source == CHRROM)
r7952	r7953
6926	6941	chr8(space->machine, vrom_bank[0], CHRROM);
6927	6942	break;
6928	6943	case 0x07:
6929		sachen_set_mirror((data >> 1) & 0x03);
	6944	sachen_set_mirror(space->machine, (data >> 1) & 0x03);
6930	6945	break;
6931	6946	default:
6932	6947	break;
r7952	r7953
6980	6995	LOG_MMC(("mapper152_w, offset: %04x, data: %02x\n", offset, data));
6981	6996
6982	6997	// we lack bus emulation
6983		set_nt_mirroring((data & 0x80) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	6998	set_nt_mirroring(space->machine, BIT(data, 7) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
6984	6999	prg16_89ab(space->machine, (data >> 4) & 0x07);
6985	7000	chr8(space->machine, data, CHRROM);
6986	7001	}
r7952	r7953
7020	7035
7021	7036	static WRITE8_HANDLER( mapper153_m_w )
7022	7037	{
	7038	nes_state *state = (nes_state *)space->machine->driver_data;
7023	7039	LOG_MMC(("mapper153_m_w, offset: %04x, data: %02x\n", offset, data));
7024	7040
7025		if (nes.crc_hack)      // Famicom Jump II uses a different board
	7041	if (state->crc_hack)      // Famicom Jump II uses a different board
7026	7042	{
7027	7043	switch (offset & 0x0f)   // there is no CHRROM and prg banking works differently
7028	7044	{
r7952	r7953
7072	7088	switch (offset & 1)
7073	7089	{
7074	7090	case 0:
7075		set_nt_mirroring((data & 0x40) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	7091	set_nt_mirroring(space->machine, BIT(data, 6) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
7076	7092	mmc_cmd1 = data & 7;
7077	7093	break;
7078	7094	case 1:
r7952	r7953
7184	7200	{
7185	7201	UINT8 nt_mode = mmc_cmd1 & 0x80;
7186	7202
7187		set_nt_page(0, ROM, vrom_bank[nt_mode ? 2 : 0], 0);
7188		set_nt_page(1, ROM, vrom_bank[nt_mode ? 3 : 0], 0);
7189		set_nt_page(2, ROM, vrom_bank[nt_mode ? 4 : 1], 0);
7190		set_nt_page(3, ROM, vrom_bank[nt_mode ? 5 : 1], 0);
	7203	set_nt_page(machine, 0, ROM, vrom_bank[nt_mode ? 2 : 0], 0);
	7204	set_nt_page(machine, 1, ROM, vrom_bank[nt_mode ? 3 : 0], 0);
	7205	set_nt_page(machine, 2, ROM, vrom_bank[nt_mode ? 4 : 1], 0);
	7206	set_nt_page(machine, 3, ROM, vrom_bank[nt_mode ? 5 : 1], 0);
7191	7207	}
7192	7208
7193	7209	static WRITE8_HANDLER( mapper158_w )
r7952	r7953
7619	7635	LOG_MMC(("mapper177_w, offset: %04x, data: %02x\n", offset, data));
7620	7636
7621	7637	prg32(space->machine, data);
7622		set_nt_mirroring(((data & 0x20) >> 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7638	set_nt_mirroring(space->machine, BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7623	7639	}
7624	7640
7625	7641	/*************************************************************
r7952	r7953
7641	7657	switch (offset)
7642	7658	{
7643	7659	case 0x700:
7644		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7660	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7645	7661	break;
7646	7662	case 0x701:
7647	7663	mmc_cmd1 = (mmc_cmd1 & 0x0c) | ((data >> 1) & 0x03);
r7952	r7953
7680	7696	{
7681	7697	LOG_MMC(("mapper179_w, offset: %04x, data: %02x\n", offset, data));
7682	7698
7683		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7699	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7684	7700	}
7685	7701
7686	7702	/*************************************************************
r7952	r7953
7734	7750	switch (offset & 0x7003)
7735	7751	{
7736	7752	case 0x0001:
7737		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7753	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7738	7754	break;
7739	7755	case 0x2000:
7740	7756	mmc_cmd1 = data;
r7952	r7953
8689	8705	prg16_cdef(space->machine, offset & 0x07);
8690	8706	chr8(space->machine, offset & 0x07, CHRROM);
8691	8707
8692		set_nt_mirroring((offset & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8708	set_nt_mirroring(space->machine, BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8693	8709	}
8694	8710
8695	8711	/*************************************************************
r7952	r7953
8732	8748	prg16_cdef(space->machine, bank + (((bank & 0x06) == 0x06) ? 1 : 0));
8733	8749	chr8(space->machine, bank, CHRROM);
8734	8750
8735		set_nt_mirroring((offset & 0x01) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
	8751	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
8736	8752	}
8737	8753
8738	8754	/*************************************************************
r7952	r7953
8776	8792	prg16_cdef(space->machine, offset | bank);
8777	8793	chr8(space->machine, offset & ~bank, CHRROM);
8778	8794
8779		set_nt_mirroring((offset & 0x10) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
	8795	set_nt_mirroring(space->machine, BIT(data, 4) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
8780	8796	}
8781	8797
8782	8798	/*************************************************************
r7952	r7953
8850	8866	switch (offset)
8851	8867	{
8852	8868	case 0x1ef0:
8853		set_nt_page(0, CIRAM, (data & 0x80) ? 1 : 0, 1);
8854		set_nt_page(1, CIRAM, (data & 0x80) ? 1 : 0, 1);
	8869	set_nt_page(space->machine, 0, CIRAM, (data & 0x80) ? 1 : 0, 1);
	8870	set_nt_page(space->machine, 1, CIRAM, (data & 0x80) ? 1 : 0, 1);
8855	8871	/* Switch 2k VROM at $0000 */
8856	8872	chr2_0(space->machine, (data & 0x7f) >> 1, CHRROM);
8857	8873	break;
8858	8874	case 0x1ef1:
8859		set_nt_page(2, CIRAM, (data & 0x80) ? 1 : 0, 1);
8860		set_nt_page(3, CIRAM, (data & 0x80) ? 1 : 0, 1);
	8875	set_nt_page(space->machine, 2, CIRAM, (data & 0x80) ? 1 : 0, 1);
	8876	set_nt_page(space->machine, 3, CIRAM, (data & 0x80) ? 1 : 0, 1);
8861	8877	/* Switch 2k VROM at $0000 */
8862	8878	chr2_2(space->machine, (data & 0x7f) >> 1, CHRROM);
8863	8879	break;
r7952	r7953
9047	9063	{
9048	9064	LOG_MMC(("mapper212_w, offset: %04x, data: %02x\n", offset, data));
9049	9065
9050		set_nt_mirroring((offset & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9066	set_nt_mirroring(space->machine, BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9051	9067	chr8(space->machine, offset, CHRROM);
9052	9068
9053	9069	if (offset < 0x4000)
r7952	r7953
9263	9279	//          break;
9264	9280
9265	9281	case 0x4000:
9266		set_nt_mirroring(((data >> 7) | data) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9282	set_nt_mirroring(space->machine, ((data >> 7) | data) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9267	9283	break;
9268	9284
9269	9285	case 0x4001:
r7952	r7953
9471	9487
9472	9488
9473	9489	case 0x2001:
9474		set_nt_mirroring(data & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9490	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9475	9491	break;
9476	9492
9477	9493	default:
r7952	r7953
9546	9562
9547	9563	if (offset < 0x4000)
9548	9564	{
9549		set_nt_mirroring(offset & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9565	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9550	9566	offset = (offset >> 1) & 0xff;
9551	9567
9552	9568	if (mmc_cmd1 != offset)
r7952	r7953
9604	9620	prg8_89(space->machine, data);
9605	9621	break;
9606	9622	case 0x1000:
9607		set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9623	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9608	9624	break;
9609	9625	case 0x2000:
9610	9626	prg8_ab(space->machine, data);
r7952	r7953
9672	9688	LOG_MMC(("mapper225_w, offset: %04x, data: %02x\n", offset, data));
9673	9689
9674	9690	chr8(space->machine, offset, CHRROM);
9675		set_nt_mirroring((offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9691	set_nt_mirroring(space->machine, (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9676	9692
9677	9693	hi_bank = offset & 0x40;
9678	9694	size_16 = offset & 0x1000;
r7952	r7953
9718	9734	mmc_cmd1 = data;
9719	9735	}
9720	9736
9721		set_nt_mirroring((mmc_cmd1 & 0x40) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9737	set_nt_mirroring(space->machine, BIT(mmc_cmd1, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9722	9738
9723	9739	hi_bank = mmc_cmd1 & 0x01;
9724	9740	size_16 = mmc_cmd1 & 0x20;
r7952	r7953
9779	9795	prg16_cdef(space->machine, ((bank << 1) & 0x38));
9780	9796	}
9781	9797
9782		set_nt_mirroring((offset & 0x02) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9798	set_nt_mirroring(space->machine, BIT(data, 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9783	9799	}
9784	9800
9785	9801	/*************************************************************
r7952	r7953
9799	9815	UINT8 pmode;
9800	9816	LOG_MMC(("mapper228_w, offset: %04x, data: %02x\n", offset, data));
9801	9817
9802		set_nt_mirroring((offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9818	set_nt_mirroring(space->machine, (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9803	9819
9804	9820	cbank = (data & 0x03) | ((offset & 0x0f) << 2);
9805	9821	chr8(space->machine, cbank, CHRROM);
r7952	r7953
9840	9856	{
9841	9857	LOG_MMC(("mapper229_w, offset: %04x, data: %02x\n", offset, data));
9842	9858
9843		set_nt_mirroring((offset & 0x20) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9859	set_nt_mirroring(space->machine, BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9844	9860	chr8(space->machine, offset, CHRROM);
9845	9861
9846	9862	if ((offset & 0x1e) == 0)
r7952	r7953
9887	9903	prg16_89ab(space->machine, (data & 0x1f) + 8);
9888	9904	prg16_cdef(space->machine, (data & 0x1f) + 9);
9889	9905	}
9890		set_nt_mirroring((data & 0x40) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	9906	set_nt_mirroring(space->machine, BIT(data, 6) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
9891	9907	}
9892	9908	}
9893	9909
r7952	r7953
9906	9922	{
9907	9923	LOG_MMC(("mapper231_w, offset: %04x, data: %02x\n", offset, data));
9908	9924
9909		set_nt_mirroring((offset & 0x80) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9925	set_nt_mirroring(space->machine, BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9910	9926
9911	9927	prg16_89ab(space->machine, (offset & 0x1e));
9912	9928	prg16_cdef(space->machine, (offset & 0x1e) | ((offset & 0x20) ? 1 : 0));
r7952	r7953
10102	10118
10103	10119	static WRITE8_HANDLER( mapper242_w )
10104	10120	{
	10121	nes_state *state = (nes_state *)space->machine->driver_data;
10105	10122	LOG_MMC(("mapper242_w, offset: %04x, data: %02x\n", offset, data));
10106	10123
10107	10124	prg32(space->machine, offset >> 3);
10108	10125
10109		if (!nes.crc_hack)   // DQ8 board does not have this / Zan Shi does
	10126	if (!state->crc_hack)   // DQ8 board does not have this / Zan Shi does
10110	10127	{
10111	10128	switch (data & 0x03)
10112	10129	{
10113		case 0: set_nt_mirroring(PPU_MIRROR_VERT); break;
10114		case 1: set_nt_mirroring(PPU_MIRROR_HORZ); break;
10115		case 2: set_nt_mirroring(PPU_MIRROR_LOW); break;
10116		case 3: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	10130	case 0: set_nt_mirroring(space->machine, PPU_MIRROR_VERT); break;
	10131	case 1: set_nt_mirroring(space->machine, PPU_MIRROR_HORZ); break;
	10132	case 2: set_nt_mirroring(space->machine, PPU_MIRROR_LOW); break;
	10133	case 3: set_nt_mirroring(space->machine, PPU_MIRROR_HIGH); break;
10117	10134	}
10118	10135	}
10119	10136	}
r7952	r7953
10164	10181	chr8(space->machine, vrom_bank[0], CHRROM);
10165	10182	break;
10166	10183	case 0x07:
10167		set_nt_mirroring(data & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10184	set_nt_mirroring(space->machine, BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10168	10185	break;
10169	10186	default:
10170	10187	break;
r7952	r7953
10220	10237
10221	10238	static WRITE8_HANDLER( mapper245_w )
10222	10239	{
	10240	nes_state *state = (nes_state *)space->machine->driver_data;
10223	10241	UINT8 cmd, map245_helper;
10224	10242	LOG_MMC(("mapper245_w, offset: %04x, data: %02x\n", offset, data));
10225	10243
r7952	r7953
10235	10253	mapper4_set_prg(space->machine, mmc_prg_base, mmc_prg_mask);
10236	10254	case 1: case 2: case 3: case 4: case 5:
10237	10255	vrom_bank[cmd] = data;
10238		if (nes.chr_chunks > 0)
	10256	if (state->chr_chunks > 0)
10239	10257	mapper4_set_chr(space->machine, CHRROM, mmc_chr_base, mmc_chr_mask);
10240	10258	else   // according to Disch's docs, mmc_cmd1&0x80 swaps 4k CHRRAM banks
10241	10259	{
r7952	r7953
10279	10297
10280	10298	static WRITE8_HANDLER( mapper246_m_w )
10281	10299	{
	10300	nes_state *state = (nes_state *)space->machine->driver_data;
10282	10301	LOG_MMC(("mapper246_m_w, offset: %04x, data: %02x\n", offset, data));
10283	10302
10284	10303	if (offset < 0x0800)
r7952	r7953
10312	10331	}
10313	10332	}
10314	10333	else
10315		nes.wram[offset] = data;
	10334	state->wram[offset] = data;
10316	10335	}
10317	10336
10318	10337	/*************************************************************
r7952	r7953
10585	10604
10586	10605	LOG_MMC(("mapper255_w, offset: %04x, data: %02x\n", offset, data));
10587	10606
10588		set_nt_mirroring((offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10607	set_nt_mirroring(space->machine, (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10589	10608	prg16_89ab(space->machine, map255_helper1 & ~map255_helper2);
10590	10609	prg16_cdef(space->machine, map255_helper1 | map255_helper2);
10591	10610	chr8(space->machine, ((offset >> 8) & 0x40) | (offset & 0x3f), CHRROM);
r7952	r7953
10855	10874	const mmc *nes_mapper_lookup( int mapper )
10856	10875	{
10857	10876	int i;
	10877
10858	10878	for (i = 0; i < ARRAY_LENGTH(mmc_list); i++)
10859	10879	{
10860		if (mmc_list[i].iNesMapper == nes.mapper)
	10880	if (mmc_list[i].iNesMapper == mapper)
10861	10881	return &mmc_list[i];
10862	10882	}
	10883
10863	10884	return NULL;
10864	10885	}

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