src/mess/drivers/px8.c
| r7807 | r7808 | |
| 38 | 38 | #include "machine/pf10.h" |
| 39 | 39 | #include "sound/wave.h" |
| 40 | 40 | #include "video/sed1330.h" |
| 41 | #include "px8.lh" |
| 41 | 42 | |
| 42 | 43 | /*************************************************************************** |
| 43 | 44 | CONSTANTS |
| r7807 | r7808 | |
| 56 | 57 | |
| 57 | 58 | enum |
| 58 | 59 | { |
| 59 | | GAH40_CTLR1 = 0, |
| 60 | | GAH40_CMDR, |
| 61 | | GAH40_CTLR2, |
| 62 | | GAH40_IER = 4, |
| 60 | GAH40M_CTLR1 = 0, |
| 61 | GAH40M_CMDR, |
| 62 | GAH40M_CTLR2, |
| 63 | GAH40M_IER = 4, |
| 63 | 64 | }; |
| 64 | 65 | |
| 65 | 66 | enum |
| 66 | 67 | { |
| 67 | | GAH40_ICRL_C = 0, |
| 68 | | GAH40_ICRH_C, |
| 69 | | GAH40_ICRL_B, |
| 70 | | GAH40_ICRH_B, |
| 71 | | GAH40_ISR, |
| 72 | | GAH40_STR, |
| 73 | | GAH40_SIOR, |
| 74 | | GAH40_IVR |
| 68 | GAH40M_ICRL_C = 0, |
| 69 | GAH40M_ICRH_C, |
| 70 | GAH40M_ICRL_B, |
| 71 | GAH40M_ICRH_B, |
| 72 | GAH40M_ISR, |
| 73 | GAH40M_STR, |
| 74 | GAH40M_SIOR, |
| 75 | GAH40M_IVR |
| 75 | 76 | }; |
| 76 | 77 | |
| 77 | 78 | /*************************************************************************** |
| 78 | 79 | READ/WRITE HANDLERS |
| 79 | 80 | ***************************************************************************/ |
| 80 | 81 | |
| 82 | /*------------------------------------------------- |
| 83 | bankswitch - memory bankswitching |
| 84 | -------------------------------------------------*/ |
| 85 | |
| 81 | 86 | static void bankswitch(running_machine *machine) |
| 82 | 87 | { |
| 83 | 88 | px8_state *state = (px8_state *)machine->driver_data; |
| 84 | | int bank = (state->bk2 << 1) | state->bank0; |
| 89 | const address_space *program = cputag_get_address_space(machine, UPD70008_TAG, ADDRESS_SPACE_PROGRAM); |
| 90 | UINT8 *ram = messram_get_ptr(devtag_get_device(machine, "messram")); |
| 91 | UINT8 *ipl_rom = memory_region(machine, UPD70008_TAG); |
| 85 | 92 | |
| 86 | | memory_set_bank(machine, "bank0", bank); |
| 87 | | memory_set_bank(machine, "bank1", bank); |
| 93 | if (!state->bank0) |
| 94 | { |
| 95 | /* IPL ROM */ |
| 96 | memory_install_rom(program, 0x0000, 0x7fff, 0, 0, ipl_rom); |
| 97 | } |
| 98 | else |
| 99 | { |
| 100 | if (state->bk2) |
| 101 | { |
| 102 | /* D-RAM (L) */ |
| 103 | memory_install_ram(program, 0x0000, 0x7fff, 0, 0, ram); |
| 104 | } |
| 105 | else |
| 106 | { |
| 107 | /* OPTION ROM (L) */ |
| 108 | memory_unmap_readwrite(program, 0x0000, 0x7fff, 0, 0); |
| 109 | } |
| 110 | } |
| 111 | |
| 112 | if (state->bk2) |
| 113 | { |
| 114 | /* D-RAM (H) */ |
| 115 | memory_install_ram(program, 0x8000, 0xffff, 0, 0, ram + 0x8000); |
| 116 | } |
| 117 | else |
| 118 | { |
| 119 | /* OPTION ROM (H) */ |
| 120 | memory_unmap_readwrite(program, 0x8000, 0xffff, 0, 0); |
| 121 | } |
| 88 | 122 | } |
| 89 | 123 | |
| 124 | /*------------------------------------------------- |
| 125 | gah40m_r - GAH40M read |
| 126 | -------------------------------------------------*/ |
| 127 | |
| 90 | 128 | static READ8_HANDLER( gah40m_r ) |
| 91 | 129 | { |
| 92 | 130 | switch (offset) |
| 93 | 131 | { |
| 94 | | case GAH40_ICRL_C: |
| 132 | case GAH40M_ICRL_C: |
| 95 | 133 | /* |
| 96 | 134 | |
| 97 | 135 | bit signal description |
| r7807 | r7808 | |
| 108 | 146 | */ |
| 109 | 147 | break; |
| 110 | 148 | |
| 111 | | case GAH40_ICRH_C: |
| 149 | case GAH40M_ICRH_C: |
| 112 | 150 | /* |
| 113 | 151 | |
| 114 | 152 | bit signal description |
| r7807 | r7808 | |
| 125 | 163 | */ |
| 126 | 164 | break; |
| 127 | 165 | |
| 128 | | case GAH40_ICRL_B: |
| 166 | case GAH40M_ICRL_B: |
| 129 | 167 | /* |
| 130 | 168 | |
| 131 | 169 | bit signal description |
| r7807 | r7808 | |
| 142 | 180 | */ |
| 143 | 181 | break; |
| 144 | 182 | |
| 145 | | case GAH40_ICRH_B: |
| 183 | case GAH40M_ICRH_B: |
| 146 | 184 | /* |
| 147 | 185 | |
| 148 | 186 | bit signal description |
| r7807 | r7808 | |
| 159 | 197 | */ |
| 160 | 198 | break; |
| 161 | 199 | |
| 162 | | case GAH40_ISR: |
| 200 | case GAH40M_ISR: |
| 163 | 201 | /* |
| 164 | 202 | |
| 165 | 203 | bit signal description |
| r7807 | r7808 | |
| 176 | 214 | */ |
| 177 | 215 | break; |
| 178 | 216 | |
| 179 | | case GAH40_STR: |
| 217 | case GAH40M_STR: |
| 180 | 218 | /* |
| 181 | 219 | |
| 182 | 220 | bit signal description |
| r7807 | r7808 | |
| 193 | 231 | */ |
| 194 | 232 | break; |
| 195 | 233 | |
| 196 | | case GAH40_SIOR: |
| 234 | case GAH40M_SIOR: |
| 197 | 235 | /* |
| 198 | 236 | |
| 199 | 237 | bit signal description |
| r7807 | r7808 | |
| 210 | 248 | */ |
| 211 | 249 | break; |
| 212 | 250 | |
| 213 | | case GAH40_IVR: |
| 251 | case GAH40M_IVR: |
| 214 | 252 | /* |
| 215 | 253 | |
| 216 | 254 | bit description |
| r7807 | r7808 | |
| 231 | 269 | return 0xff; |
| 232 | 270 | } |
| 233 | 271 | |
| 272 | /*------------------------------------------------- |
| 273 | gah40m_w - GAH40M write |
| 274 | -------------------------------------------------*/ |
| 275 | |
| 234 | 276 | static WRITE8_HANDLER( gah40m_w ) |
| 235 | 277 | { |
| 236 | 278 | px8_state *state = (px8_state *)space->machine->driver_data; |
| 237 | 279 | |
| 238 | 280 | switch (offset) |
| 239 | 281 | { |
| 240 | | case GAH40_CTLR1: |
| 282 | case GAH40M_CTLR1: |
| 241 | 283 | /* |
| 242 | 284 | |
| 243 | 285 | bit signal description |
| r7807 | r7808 | |
| 257 | 299 | bankswitch(space->machine); |
| 258 | 300 | break; |
| 259 | 301 | |
| 260 | | case GAH40_CMDR: |
| 302 | case GAH40M_CMDR: |
| 261 | 303 | /* |
| 262 | 304 | |
| 263 | 305 | bit description |
| r7807 | r7808 | |
| 274 | 316 | */ |
| 275 | 317 | break; |
| 276 | 318 | |
| 277 | | case GAH40_CTLR2: |
| 319 | case GAH40M_CTLR2: |
| 278 | 320 | /* |
| 279 | 321 | |
| 280 | 322 | bit signal description |
| r7807 | r7808 | |
| 290 | 332 | |
| 291 | 333 | */ |
| 292 | 334 | |
| 293 | | /* output_set_value("led_0", BIT(data, 0)); |
| 335 | output_set_value("led_0", BIT(data, 0)); |
| 294 | 336 | output_set_value("led_1", BIT(data, 1)); |
| 295 | | output_set_value("led_2", BIT(data, 2));*/ |
| 337 | output_set_value("led_2", BIT(data, 2)); |
| 296 | 338 | break; |
| 297 | 339 | |
| 298 | | case GAH40_IER: |
| 340 | case GAH40M_IER: |
| 299 | 341 | /* |
| 300 | 342 | |
| 301 | 343 | bit signal description |
| r7807 | r7808 | |
| 314 | 356 | state->ier = data; |
| 315 | 357 | break; |
| 316 | 358 | |
| 317 | | case GAH40_SIOR: |
| 359 | case GAH40M_SIOR: |
| 318 | 360 | /* |
| 319 | 361 | |
| 320 | 362 | bit signal description |
| r7807 | r7808 | |
| 335 | 377 | } |
| 336 | 378 | } |
| 337 | 379 | |
| 380 | /*------------------------------------------------- |
| 381 | gah40s_r - GAH40S read |
| 382 | -------------------------------------------------*/ |
| 383 | |
| 338 | 384 | static READ8_HANDLER( gah40s_r ) |
| 339 | 385 | { |
| 386 | px8_state *state = (px8_state *)space->machine->driver_data; |
| 387 | UINT8 data = 0xff; |
| 388 | |
| 340 | 389 | switch (offset) |
| 341 | 390 | { |
| 342 | | case 0: |
| 391 | case 0: /* counter (upper byte) input */ |
| 392 | data = (state->cnt >> 8) & 0x1f; |
| 343 | 393 | break; |
| 344 | 394 | |
| 345 | | case 1: |
| 395 | case 1: /* counter (lower byte) */ |
| 396 | data = state->cnt & 0xff; |
| 346 | 397 | break; |
| 347 | 398 | |
| 348 | | case 2: |
| 399 | case 3: /* P-ROM read data */ |
| 400 | data = state->prd; |
| 349 | 401 | break; |
| 350 | | |
| 351 | | case 3: |
| 352 | | break; |
| 353 | 402 | } |
| 354 | 403 | |
| 355 | | return 0xff; |
| 404 | return data; |
| 356 | 405 | } |
| 357 | 406 | |
| 407 | /*------------------------------------------------- |
| 408 | gah40s_w - GAH40S write |
| 409 | -------------------------------------------------*/ |
| 410 | |
| 358 | 411 | static WRITE8_HANDLER( gah40s_w ) |
| 359 | 412 | { |
| 413 | px8_state *state = (px8_state *)space->machine->driver_data; |
| 414 | |
| 360 | 415 | switch (offset) |
| 361 | 416 | { |
| 362 | | case 0: |
| 417 | case 0: /* counter reset */ |
| 418 | state->cnt = 0; |
| 363 | 419 | break; |
| 364 | 420 | |
| 365 | | case 1: |
| 421 | case 1: /* command register */ |
| 422 | /* |
| 423 | |
| 424 | bit signal description |
| 425 | |
| 426 | 0 SW PR PROM power switch |
| 427 | 1 SW MCT microcassette power switch |
| 428 | 2 MTA microcassette drive motor control signal A |
| 429 | 3 MTB microcassette drive motor control signal B |
| 430 | 4 MTC microcassette drive motor control signal C |
| 431 | 5 |
| 432 | 6 _FAST |
| 433 | 7 _STOP CNT |
| 434 | |
| 435 | */ |
| 436 | |
| 437 | state->swpr = BIT(data, 0); |
| 366 | 438 | break; |
| 367 | 439 | |
| 368 | | case 2: |
| 440 | case 2: /* P-ROM address (upper 8 byte) */ |
| 441 | state->pra = (data << 8) | (state->pra & 0xff); |
| 442 | state->prd = 0; // TODO read prom! |
| 369 | 443 | break; |
| 370 | 444 | |
| 371 | | case 3: |
| 445 | case 3: /* P-ROM address (lower 8 byte) */ |
| 446 | state->pra = (state->pra & 0xff00) | data; |
| 447 | state->prd = 0; // TODO read prom! |
| 372 | 448 | break; |
| 373 | 449 | } |
| 374 | 450 | } |
| 375 | 451 | |
| 452 | /*------------------------------------------------- |
| 453 | gah40s_ier_w - interrupt enable register write |
| 454 | -------------------------------------------------*/ |
| 455 | |
| 376 | 456 | static WRITE8_HANDLER( gah40s_ier_w ) |
| 377 | 457 | { |
| 458 | px8_state *state = (px8_state *)space->machine->driver_data; |
| 459 | |
| 460 | state->ier = data; |
| 378 | 461 | } |
| 379 | 462 | |
| 380 | 463 | /*------------------------------------------------- |
| r7807 | r7808 | |
| 743 | 826 | state->sed1320 = devtag_get_device(machine, SED1320_TAG); |
| 744 | 827 | state->cassette = devtag_get_device(machine, CASSETTE_TAG); |
| 745 | 828 | |
| 746 | | /* setup memory banking */ |
| 747 | | UINT8 *ram = messram_get_ptr(devtag_get_device(machine, "messram")); |
| 748 | | UINT8 *ipl_rom = memory_region(machine, UPD70008_TAG); |
| 749 | | UINT8 *option_rom = NULL; // fixme |
| 750 | | |
| 751 | | memory_configure_bank(machine, "bank0", 0, 1, ipl_rom, 0); |
| 752 | | memory_configure_bank(machine, "bank0", 1, 1, option_rom, 0); |
| 753 | | memory_configure_bank(machine, "bank0", 2, 1, ipl_rom, 0); |
| 754 | | memory_configure_bank(machine, "bank0", 3, 1, ram, 0); |
| 755 | | |
| 756 | | memory_configure_bank(machine, "bank1", 0, 2, option_rom + 0x8000, 0); |
| 757 | | memory_configure_bank(machine, "bank1", 2, 2, ram + 0x8000, 0); |
| 758 | | |
| 759 | 829 | /* register for state saving */ |
| 760 | 830 | state_save_register_global(machine, state->ier); |
| 761 | 831 | state_save_register_global(machine, state->isr); |
| r7807 | r7808 | |
| 800 | 870 | MDRV_MACHINE_RESET(px8) |
| 801 | 871 | |
| 802 | 872 | /* video hardware */ |
| 873 | MDRV_DEFAULT_LAYOUT(layout_px8) |
| 874 | |
| 803 | 875 | MDRV_SCREEN_ADD(SCREEN_TAG, LCD) |
| 804 | 876 | MDRV_SCREEN_REFRESH_RATE(72) |
| 805 | 877 | MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16) |