MESS SVN History

15994 Revisions

r773 Wednesday 1st August, 2007 at 03:32:37 UTC by Dirk Best
Moved rriot.h to correct location.

[src/mess/includes]	~~rriot.h~~
[src/mess/machine]	rriot.h*

src/mess/includes/rriot.h
r772	r773
1		#ifndef RIOT_H
2		#define RIOT_H
3
4		/* mos rom ram io timer 6530 */
5
6		/* ram and rom areas are not handled in this rriot compoment */
7
8		/*
9		internal 64 byte ram
10		internal 1024 byte rom
11		inputs and output
12		timer
13		interrupt logic
14		logic to connect up to 7 6530 without additional address decoding logic
15
16		1kb rom selection
17		a0..a9,
18		rs0, cs1, cs2 mask programmed!
19
20		64byte ram selection
21		a0..a5
22		rs0, cs1, cs2, a6, a7, a8, a9 mask programmed!
23
24		io, timer selection
25		a0..a3 (a4,a5 don't care)
26		rs0, cs1, cs2, a6, a7, a8, a9 mask programmed!
27		(a2=0 io, a3 don't care)
28		a2=1 timer, a3 interrupt enable)
29
30		standard configurations! CS2(a12) CS1(a11) rs0(a10)
31		chip subtype 1: rom 0x0400, ram 0x000, io 0x200
32		chip subtype 2: rom 0x0800, ram 0x040, io 0x240
33		chip subtype 3: rom 0x0c00, ram 0x080, io 0x280
34		chip subtype 4: rom 0x1000, ram 0x0c0, io 0x2c0
35		chip subtype 5: rom 0x1400, ram 0x100, io 0x300
36		chip subtype 6: rom 0x1800, ram 0x140, io 0x340
37		chip subtype 7: rom 0x1c00, ram 0x180, io 0x380
38
39		5V 1 40 PA1
40		PA0 2 39 PA2
41		CLK 3 38 PA3
42		RS0 4 37 PA4
43		A9 5 36 PA5
44		A8 6 35 PA6
45		A7 7 34 PA7
46		A6 8 33 D0
47		R /W 9 32 D1
48		A5 10 31 D2
49		A4 11 30 D3
50		A3 12 29 D4
51		A2 13 28 D5
52		A1 14 27 D6
53		A0 15 26 D7
54		/RES 16 25 PB0
55		PB7 17 24 PB1
56		PB6 18 23 PB2
57		PB5 19 22 PB3
58		GND 20 21 PB4
59
60		D0..7 data bus
61		A0..9 address bus
62		R /W read or /write
63		RS0 rom select
64
65
66		/RES reset
67		CLK (phi2) clock for timer
68		PA0..7, PB0..8 input or output (software selectable)
69
70		PB7 could be configured as /IRQ line
71		PB6,PB5 could be configured as CS1,CS2 (mask programmed with the rom!)
72
73		dumping suggestions
74		wire an adapter for an 2764 eprom, so it is readable with many eprom burners
75		read the complete 8kbyte data
76		extract the positions from the dump
77
78		*/
79
80
81		/*
82		mos 6532
83		chip also contains 128 bytes ram (own chip select line)
84		no rom
85		separate irq output
86		some significant differences, so unique component
87		*/
88
89		#ifdef __cplusplus
90		extern "C" {
91		#endif
92
93		#define MAX_RRIOTS 4
94
95		typedef struct {
96		int baseclock;
97		struct {
98		int (*input)(int chip);
99		void (*output)(int chip, int value);
100		} port_a, port_b;
101		void (*irq_callback)(int chip, int level);
102		} RRIOT_CONFIG;
103
104		/* This has to be called from a driver at startup */
105		void rriot_init(int nr, RRIOT_CONFIG *riot);
106
107		int rriot_r(int chip, int offs);
108		void rriot_w(int chip, int offs, int data);
109
110		void rriot_reset(int nr);
111
112		READ8_HANDLER ( rriot_0_r );
113		WRITE8_HANDLER ( rriot_0_w );
114		READ8_HANDLER ( rriot_1_r );
115		WRITE8_HANDLER ( rriot_1_w );
116		READ8_HANDLER ( rriot_2_r );
117		WRITE8_HANDLER ( rriot_2_w );
118		READ8_HANDLER ( rriot_3_r );
119		WRITE8_HANDLER ( rriot_3_w );
120
121		READ8_HANDLER( rriot_0_a_r );
122		READ8_HANDLER( rriot_1_a_r );
123		READ8_HANDLER( rriot_2_a_r );
124		READ8_HANDLER( rriot_3_a_r );
125
126		WRITE8_HANDLER( rriot_0_a_w );
127		WRITE8_HANDLER( rriot_1_a_w );
128		WRITE8_HANDLER( rriot_2_a_w );
129		WRITE8_HANDLER( rriot_3_a_w );
130
131		READ8_HANDLER( rriot_0_b_r );
132		READ8_HANDLER( rriot_1_b_r );
133		READ8_HANDLER( rriot_2_b_r );
134		READ8_HANDLER( rriot_3_b_r );
135
136		WRITE8_HANDLER( rriot_0_b_w );
137		WRITE8_HANDLER( rriot_1_b_w );
138		WRITE8_HANDLER( rriot_2_b_w );
139		WRITE8_HANDLER( rriot_3_b_w );
140
141		#ifdef __cplusplus
142		}
143		#endif
144
145		#endif

src/mess/machine/rriot.h
r0	r773
	1	#ifndef RIOT_H
	2	#define RIOT_H
	3
	4	/* mos rom ram io timer 6530 */
	5
	6	/* ram and rom areas are not handled in this rriot compoment */
	7
	8	/*
	9	internal 64 byte ram
	10	internal 1024 byte rom
	11	inputs and output
	12	timer
	13	interrupt logic
	14	logic to connect up to 7 6530 without additional address decoding logic
	15
	16	1kb rom selection
	17	a0..a9,
	18	rs0, cs1, cs2 mask programmed!
	19
	20	64byte ram selection
	21	a0..a5
	22	rs0, cs1, cs2, a6, a7, a8, a9 mask programmed!
	23
	24	io, timer selection
	25	a0..a3 (a4,a5 don't care)
	26	rs0, cs1, cs2, a6, a7, a8, a9 mask programmed!
	27	(a2=0 io, a3 don't care)
	28	a2=1 timer, a3 interrupt enable)
	29
	30	standard configurations! CS2(a12) CS1(a11) rs0(a10)
	31	chip subtype 1: rom 0x0400, ram 0x000, io 0x200
	32	chip subtype 2: rom 0x0800, ram 0x040, io 0x240
	33	chip subtype 3: rom 0x0c00, ram 0x080, io 0x280
	34	chip subtype 4: rom 0x1000, ram 0x0c0, io 0x2c0
	35	chip subtype 5: rom 0x1400, ram 0x100, io 0x300
	36	chip subtype 6: rom 0x1800, ram 0x140, io 0x340
	37	chip subtype 7: rom 0x1c00, ram 0x180, io 0x380
	38
	39	5V 1 40 PA1
	40	PA0 2 39 PA2
	41	CLK 3 38 PA3
	42	RS0 4 37 PA4
	43	A9 5 36 PA5
	44	A8 6 35 PA6
	45	A7 7 34 PA7
	46	A6 8 33 D0
	47	R /W 9 32 D1
	48	A5 10 31 D2
	49	A4 11 30 D3
	50	A3 12 29 D4
	51	A2 13 28 D5
	52	A1 14 27 D6
	53	A0 15 26 D7
	54	/RES 16 25 PB0
	55	PB7 17 24 PB1
	56	PB6 18 23 PB2
	57	PB5 19 22 PB3
	58	GND 20 21 PB4
	59
	60	D0..7 data bus
	61	A0..9 address bus
	62	R /W read or /write
	63	RS0 rom select
	64
	65
	66	/RES reset
	67	CLK (phi2) clock for timer
	68	PA0..7, PB0..8 input or output (software selectable)
	69
	70	PB7 could be configured as /IRQ line
	71	PB6,PB5 could be configured as CS1,CS2 (mask programmed with the rom!)
	72
	73	dumping suggestions
	74	wire an adapter for an 2764 eprom, so it is readable with many eprom burners
	75	read the complete 8kbyte data
	76	extract the positions from the dump
	77
	78	*/
	79
	80
	81	/*
	82	mos 6532
	83	chip also contains 128 bytes ram (own chip select line)
	84	no rom
	85	separate irq output
	86	some significant differences, so unique component
	87	*/
	88
	89	#ifdef __cplusplus
	90	extern "C" {
	91	#endif
	92
	93	#define MAX_RRIOTS 4
	94
	95	typedef struct {
	96	int baseclock;
	97	struct {
	98	int (*input)(int chip);
	99	void (*output)(int chip, int value);
	100	} port_a, port_b;
	101	void (*irq_callback)(int chip, int level);
	102	} RRIOT_CONFIG;
	103
	104	/* This has to be called from a driver at startup */
	105	void rriot_init(int nr, RRIOT_CONFIG *riot);
	106
	107	int rriot_r(int chip, int offs);
	108	void rriot_w(int chip, int offs, int data);
	109
	110	void rriot_reset(int nr);
	111
	112	READ8_HANDLER ( rriot_0_r );
	113	WRITE8_HANDLER ( rriot_0_w );
	114	READ8_HANDLER ( rriot_1_r );
	115	WRITE8_HANDLER ( rriot_1_w );
	116	READ8_HANDLER ( rriot_2_r );
	117	WRITE8_HANDLER ( rriot_2_w );
	118	READ8_HANDLER ( rriot_3_r );
	119	WRITE8_HANDLER ( rriot_3_w );
	120
	121	READ8_HANDLER( rriot_0_a_r );
	122	READ8_HANDLER( rriot_1_a_r );
	123	READ8_HANDLER( rriot_2_a_r );
	124	READ8_HANDLER( rriot_3_a_r );
	125
	126	WRITE8_HANDLER( rriot_0_a_w );
	127	WRITE8_HANDLER( rriot_1_a_w );
	128	WRITE8_HANDLER( rriot_2_a_w );
	129	WRITE8_HANDLER( rriot_3_a_w );
	130
	131	READ8_HANDLER( rriot_0_b_r );
	132	READ8_HANDLER( rriot_1_b_r );
	133	READ8_HANDLER( rriot_2_b_r );
	134	READ8_HANDLER( rriot_3_b_r );
	135
	136	WRITE8_HANDLER( rriot_0_b_w );
	137	WRITE8_HANDLER( rriot_1_b_w );
	138	WRITE8_HANDLER( rriot_2_b_w );
	139	WRITE8_HANDLER( rriot_3_b_w );
	140
	141	#ifdef __cplusplus
	142	}
	143	#endif
	144
	145	#endif

15994 Revisions