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r7679 Friday 2nd April, 2010 at 17:51:05 UTC by Angelo Salese
[SNES]: Clear pending IRQ if the IRQ enable flag is disabled, fixes 3x3 Eyes - Seima Korin Den booting
[src/mame/machine]snes.c

src/mame/machine/snes.c
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412412      case DMAP4: case DMAP5: case DMAP6: case DMAP7:
413413         return state->dma_channel[(offset & 0x70) >> 4].dmap;
414414      case BBAD0: case BBAD1: case BBAD2: case BBAD3: /*0x43n1*/
415      case BBAD4: case BBAD5: case BBAD6: case BBAD7:
415      case BBAD4: case BBAD5: case BBAD6: case BBAD7:
416416         return state->dma_channel[(offset & 0x70) >> 4].dest_addr;
417417      case A1T0L: case A1T1L: case A1T2L: case A1T3L: /*0x43n2*/
418      case A1T4L: case A1T5L: case A1T6L: case A1T7L:
418      case A1T4L: case A1T5L: case A1T6L: case A1T7L:
419419         return state->dma_channel[(offset & 0x70) >> 4].src_addr & 0xff;
420420      case A1T0H: case A1T1H: case A1T2H: case A1T3H: /*0x43n3*/
421      case A1T4H: case A1T5H: case A1T6H: case A1T7H:
421      case A1T4H: case A1T5H: case A1T6H: case A1T7H:
422422         return (state->dma_channel[(offset & 0x70) >> 4].src_addr >> 8) & 0xff;
423423      case A1B0: case A1B1: case A1B2: case A1B3:     /*0x43n4*/
424      case A1B4: case A1B5: case A1B6: case A1B7:
424      case A1B4: case A1B5: case A1B6: case A1B7:
425425         return state->dma_channel[(offset & 0x70) >> 4].bank;
426      case DAS0L: case DAS1L: case DAS2L: case DAS3L: /*0x43n5*/
427      case DAS4L: case DAS5L: case DAS6L: case DAS7L:
426      case DAS0L: case DAS1L: case DAS2L: case DAS3L: /*0x43n5*/
427      case DAS4L: case DAS5L: case DAS6L: case DAS7L:
428428         return state->dma_channel[(offset & 0x70) >> 4].trans_size & 0xff;
429      case DAS0H: case DAS1H: case DAS2H: case DAS3H: /*0x43n6*/
430      case DAS4H: case DAS5H: case DAS6H: case DAS7H:
429      case DAS0H: case DAS1H: case DAS2H: case DAS3H: /*0x43n6*/
430      case DAS4H: case DAS5H: case DAS6H: case DAS7H:
431431         return (state->dma_channel[(offset & 0x70) >> 4].trans_size >> 8) & 0xff;
432      case DSAB0: case DSAB1: case DSAB2: case DSAB3: /*0x43n7*/
433      case DSAB4: case DSAB5: case DSAB6: case DSAB7:
432      case DSAB0: case DSAB1: case DSAB2: case DSAB3: /*0x43n7*/
433      case DSAB4: case DSAB5: case DSAB6: case DSAB7:
434434         return state->dma_channel[(offset & 0x70) >> 4].ibank;
435435      case A2A0L: case A2A1L: case A2A2L: case A2A3L: /*0x43n8*/
436      case A2A4L: case A2A5L: case A2A6L: case A2A7L:
436      case A2A4L: case A2A5L: case A2A6L: case A2A7L:
437437         return state->dma_channel[(offset & 0x70) >> 4].hdma_addr & 0xff;
438438      case A2A0H: case A2A1H: case A2A2H: case A2A3H: /*0x43n9*/
439      case A2A4H: case A2A5H: case A2A6H: case A2A7H:
439      case A2A4H: case A2A5H: case A2A6H: case A2A7H:
440440         return (state->dma_channel[(offset & 0x70) >> 4].hdma_addr >> 8) & 0xff;
441441      case NTRL0: case NTRL1: case NTRL2: case NTRL3: /*0x43na*/
442      case NTRL4: case NTRL5: case NTRL6: case NTRL7:
442      case NTRL4: case NTRL5: case NTRL6: case NTRL7:
443443         return state->dma_channel[(offset & 0x70) >> 4].hdma_line_counter;
444444      case 0x430b: case 0x431b: case 0x432b: case 0x433b: /* according to bsnes, this does not return open_bus (even if its precise effect is unknown) */
445      case 0x434b: case 0x435b: case 0x436b: case 0x437b:
445      case 0x434b: case 0x435b: case 0x436b: case 0x437b:
446446         return state->dma_channel[(offset & 0x70) >> 4].unk;
447447
448448#ifndef MESS
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556556         }
557557         break;
558558      case NMITIMEN:   /* Flag for v-blank, timer int. and joy read */
559         if((snes_ram[NMITIMEN] & 0x30) == 0x00)
560         {
561            cpu_set_input_line(state->maincpu, G65816_LINE_IRQ, CLEAR_LINE );
562            snes_ram[TIMEUP] = 0;   // flag is cleared on both read and write
563         }
564         break;
559565      case OLDJOY2:   /* Old NES joystick support */
560566         break;
561567      case WRIO:      /* Programmable I/O port - latches H/V counters on a 0->1 transition */
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666672         state->dma_channel[(offset & 0x70) >> 4].dmap = data;
667673         break;
668674      case BBAD0: case BBAD1: case BBAD2: case BBAD3: /*0x43n1*/
669      case BBAD4: case BBAD5: case BBAD6: case BBAD7:
675      case BBAD4: case BBAD5: case BBAD6: case BBAD7:
670676         state->dma_channel[(offset & 0x70) >> 4].dest_addr = data;
671677         break;
672678      case A1T0L: case A1T1L: case A1T2L: case A1T3L: /*0x43n2*/
673      case A1T4L: case A1T5L: case A1T6L: case A1T7L:
679      case A1T4L: case A1T5L: case A1T6L: case A1T7L:
674680         state->dma_channel[(offset & 0x70) >> 4].src_addr = (state->dma_channel[(offset & 0x70) >> 4].src_addr & 0xff00) | (data << 0);
675681         break;
676682      case A1T0H: case A1T1H: case A1T2H: case A1T3H: /*0x43n3*/
677      case A1T4H: case A1T5H: case A1T6H: case A1T7H:
683      case A1T4H: case A1T5H: case A1T6H: case A1T7H:
678684         state->dma_channel[(offset & 0x70) >> 4].src_addr = (state->dma_channel[(offset & 0x70) >> 4].src_addr & 0x00ff) | (data << 8);
679685         break;
680686      case A1B0: case A1B1: case A1B2: case A1B3:     /*0x43n4*/
681      case A1B4: case A1B5: case A1B6: case A1B7:
687      case A1B4: case A1B5: case A1B6: case A1B7:
682688         state->dma_channel[(offset & 0x70) >> 4].bank = data;
683689         break;
684      case DAS0L: case DAS1L: case DAS2L: case DAS3L: /*0x43n5*/
685      case DAS4L: case DAS5L: case DAS6L: case DAS7L:
690      case DAS0L: case DAS1L: case DAS2L: case DAS3L: /*0x43n5*/
691      case DAS4L: case DAS5L: case DAS6L: case DAS7L:
686692         state->dma_channel[(offset & 0x70) >> 4].trans_size = (state->dma_channel[(offset & 0x70) >> 4].trans_size & 0xff00) | (data << 0);
687693         break;
688      case DAS0H: case DAS1H: case DAS2H: case DAS3H: /*0x43n6*/
689      case DAS4H: case DAS5H: case DAS6H: case DAS7H:
694      case DAS0H: case DAS1H: case DAS2H: case DAS3H: /*0x43n6*/
695      case DAS4H: case DAS5H: case DAS6H: case DAS7H:
690696         state->dma_channel[(offset & 0x70) >> 4].trans_size = (state->dma_channel[(offset & 0x70) >> 4].trans_size & 0x00ff) | (data << 8);
691697         break;
692      case DSAB0: case DSAB1: case DSAB2: case DSAB3: /*0x43n7*/
693      case DSAB4: case DSAB5: case DSAB6: case DSAB7:
698      case DSAB0: case DSAB1: case DSAB2: case DSAB3: /*0x43n7*/
699      case DSAB4: case DSAB5: case DSAB6: case DSAB7:
694700         state->dma_channel[(offset & 0x70) >> 4].ibank = data;
695701         break;
696702      case A2A0L: case A2A1L: case A2A2L: case A2A3L: /*0x43n8*/
697      case A2A4L: case A2A5L: case A2A6L: case A2A7L:
703      case A2A4L: case A2A5L: case A2A6L: case A2A7L:
698704         state->dma_channel[(offset & 0x70) >> 4].hdma_addr = (state->dma_channel[(offset & 0x70) >> 4].hdma_addr & 0xff00) | (data << 0);
699705         break;
700706      case A2A0H: case A2A1H: case A2A2H: case A2A3H: /*0x43n9*/
701      case A2A4H: case A2A5H: case A2A6H: case A2A7H:
707      case A2A4H: case A2A5H: case A2A6H: case A2A7H:
702708         state->dma_channel[(offset & 0x70) >> 4].hdma_addr = (state->dma_channel[(offset & 0x70) >> 4].hdma_addr & 0x00ff) | (data << 8);
703709         break;
704710      case NTRL0: case NTRL1: case NTRL2: case NTRL3: /*0x43na*/
705      case NTRL4: case NTRL5: case NTRL6: case NTRL7:
711      case NTRL4: case NTRL5: case NTRL6: case NTRL7:
706712         state->dma_channel[(offset & 0x70) >> 4].hdma_line_counter = data;
707713         break;
708714      case 0x430b: case 0x431b: case 0x432b: case 0x433b:
709      case 0x434b: case 0x435b: case 0x436b: case 0x437b:
715      case 0x434b: case 0x435b: case 0x436b: case 0x437b:
710716         state->dma_channel[(offset & 0x70) >> 4].unk = data;
711717         break;
712718   }
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968974      }
969975   }
970976   else if (snes_cart.mode & 0x0a)               /* Mode 21 & 25 */
971      value = snes_ram[0x600000 + offset];   
977      value = snes_ram[0x600000 + offset];
972978
973979   return value;
974980}
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17721778         memory_write_byte(space, abus, 0x00);
17731779         return;
17741780      }
1775      else
1781      else
17761782      {
17771783         if (!dma_abus_valid(abus))
17781784            return;
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17901796         //read is irrelevent, as it cannot be observed by software
17911797         return;
17921798      }
1793      else
1799      else
17941800      {
17951801         memory_write_byte(space, bbus, snes_abus_read(space, abus));
17961802         return;
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18341840
18351841   state->dma_channel[dma].hdma_line_counter = snes_abus_read(space, abus);
18361842
1837   if (state->dma_channel[dma].dmap & 0x40)
1843   if (state->dma_channel[dma].dmap & 0x40)
18381844   {
1839      /* One oddity: if $43xA is 0 and this is the last active HDMA channel for this scanline, only load
1845      /* One oddity: if $43xA is 0 and this is the last active HDMA channel for this scanline, only load
18401846      one byte for Address, and use the $00 for the low byte. So Address ends up incremented one less than
18411847      otherwise expected */
18421848
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18851891   {
18861892      if (BIT(state->hdmaen, i))
18871893      {
1888         if (state->dma_channel[i].do_transfer)
1894         if (state->dma_channel[i].do_transfer)
18891895         {
18901896            /* Get transfer addresses */
18911897            if (state->dma_channel[i].dmap & 0x40)   /* Indirect */
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18931899            else                           /* Absolute */
18941900               abus = (state->dma_channel[i].bank << 16) + state->dma_channel[i].hdma_addr;
18951901
1896            bbus = state->dma_channel[i].dest_addr + 0x2100;   
1902            bbus = state->dma_channel[i].dest_addr + 0x2100;
18971903
18981904            switch (state->dma_channel[i].dmap & 0x07)
18991905            {

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