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r7614 Sunday 21st March, 2010 at 11:49:57 UTC by Nathan Woods
[TI99] Cleanups. [Michael Zapf]

[docs]	messnew.txt
[src/mess/devices]	ti99cart.c ti99cart.h
[src/mess/machine]	99_dsk.c ti99_4x.c ti99_4x.h ti99pcod.c

src/mess/devices/ti99cart.c

r7613	r7614
15	15
16	16	typedef int assmfct(running_device *);
17	17
	18	#define TI99_CARTRIDGE_PCB_NONE      DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_none)
	19	#define TI99_CARTRIDGE_PCB_STD      DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_std)
	20	#define TI99_CARTRIDGE_PCB_PAGED   DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_paged)
	21	#define TI99_CARTRIDGE_PCB_MINIMEM   DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_minimem)
	22	#define TI99_CARTRIDGE_PCB_SUPER   DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_super)
	23	#define TI99_CARTRIDGE_PCB_MBX      DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_mbx)
	24	#define TI99_CARTRIDGE_PCB_PAGED379I   DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_paged379i)
	25	#define TI99_CARTRIDGE_PCB_PAGEDCRU   DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_pagedcru)
	26
	27	/* Generic TI99 cartridge structure. */
	28	struct _cartridge_t
	29	{
	30	/* PCB device associated to this cartridge. If NULL, the slot is empty. */
	31	running_device *pcb;
	32
	33	/* GROM buffer size. */
	34	int grom_size;
	35
	36	/* ROM page. */
	37	int rom_page;
	38	/* RAM page. */
	39	int ram_page;
	40
	41	/* ROM buffer size. All banks have equal sizes. */
	42	int rom_size;
	43	/* RAM buffer size. All banks have equal sizes. */
	44	int ram_size;
	45
	46	/* pointer to GROM data. */
	47	UINT8 *grom_ptr;
	48
	49	/* GROM buffered data output. */
	50	/*        UINT8 grom_buffer; */ /* Now handled by the multicart system. */
	51
	52	/* ROM buffer. We are using this for both 16 bit (99/4a) and 8 bit
	53	(99/8) access. */
	54	void *rom_ptr;
	55
	56	/* ROM buffer for the second bank of paged cartridges. Other cartridges
	57	usually store their ROM in one large file. */
	58	void *rom2_ptr;
	59
	60	/* RAM buffer. The persistence service is done by the cartridge system.
	61	The RAM space is a consecutive space; all banks are in one buffer. */
	62	void *ram_ptr;
	63	};
	64	typedef struct _cartridge_t cartridge_t;
	65
18	66	enum
19	67	{
20	68	TI99CARTINFO_FCT_6000_R = DEVINFO_FCT_DEVICE_SPECIFIC,      /* read16_device_handler */
r7613	r7614
36	84	LEG_CART_MBX
37	85	} legacy_cart_t;
38	86
39		struct _ti99_multicart_t
	87	struct _ti99_multicart_state
40	88	{
41	89	/* Reserves space for all cartridges. This is also used in the legacy
42		cartridge system, but only for slot 0. */
	90	cartridge system, but only for slot 0. */
43	91	cartridge_t cartridge[NUMBER_OF_CARTRIDGE_SLOTS];
44
	92
45	93	/* Determines which slot is currently active. This value is changed when there
46		are accesses to other GROM base addresses. */
	94	are accesses to other GROM base addresses. */
47	95	int active_slot;
48
	96
49	97	/* Used in order to enforce a special slot. This value is retrieved
50		from the dipswitch setting. A value of -1 means automatic, that is,
51		the grom base switch is used. Values 0 .. max refer to the
52		respective slot. */
	98	from the dipswitch setting. A value of -1 means automatic, that is,
	99	the grom base switch is used. Values 0 .. max refer to the
	100	respective slot. */
53	101	int fixed_slot;
54
	102
55	103	/* Holds the highest index of a cartridge being plugged in plus one.
56		If we only have one cartridge inserted, we don't want to get a
57		selection option, so we just mirror the memory contents. */
	104	If we only have one cartridge inserted, we don't want to get a
	105	selection option, so we just mirror the memory contents. */
58	106	int next_free_slot;
59
	107
60	108	/* Counts the number of slots which currently contain legacy format
61		cartridge images. */
	109	cartridge images. */
62	110	int legacy_slots;
63
	111
64	112	/* Counts the number of slots which currently contain new format
65		cartridge images. */
	113	cartridge images. */
66	114	int multi_slots;
67
	115
68	116	/* Legacy mode. Stores the slot number where the cartridge part is mounted.
69		Index is from slotc_type_t. */
	117	Index is from slotc_type_t. */
70	118	int legacy_slotnumber[5];
	119
	120	/* current address pointer for the active GROM in port (16 bits) */
	121	UINT16 grom_address;
	122	/* GROM data buffer */
	123	UINT8 grom_buffer;
	124
	125	/* internal flip-flops that are set after the first access to the GROM
	126	address so that next access is mapped to the LSB, and cleared after each
	127	data access */
	128	char raddr_LSB, waddr_LSB;
71	129	};
72		typedef struct _ti99_multicart_t ti99_multicart_t;
	130	typedef struct _ti99_multicart_state ti99_multicart_state;
73	131
74	132	#define AUTO -1
75	133
r7613	r7614
84	142	} slotc_type_t;
85	143
86	144	/* Function declaration; the function itself is in the later part of this file. */
87		static UINT8 cartridge_grom_read_legacy(running_device *cartsys, int cart_offset);
	145	static UINT8 cartridge_grom_read_legacy(running_device *cartsys);
88	146	static void unload_legacy(running_device *image);
89	147	static int load_legacy(running_device *image);
90	148
r7613	r7614
122	180
123	181	static int in_legacy_mode(running_device *device)
124	182	{
125		ti99_multicart_t *cartslots = (ti99_multicart_t *)device->token;
	183	ti99_multicart_state *cartslots = (ti99_multicart_state *)device->token;
126	184	if ((cartslots->legacy_slots>0) &&  (cartslots->multi_slots==0))
127	185	return TRUE;
128	186	return FALSE;
r7613	r7614
164	222	Interestingly, cartridge subroutines are found nevertheless, even when
165	223	the cartridge is plugged into a higher slot.
166	224	*/
167		void ti99_cartridge_slot_set(running_device *cartsys, int slotnumber)
	225	static void cartridge_slot_set(running_device *cartsys, int slotnumber)
168	226	{
169		ti99_multicart_t *cartslots = (ti99_multicart_t *)cartsys->token;
	227	ti99_multicart_state *cartslots = (ti99_multicart_state *)cartsys->token;
170	228	assert(slotnumber>=0 && slotnumber<=255);
171	229	//  if (cartslots->active_slot != slotnumber) printf("Setting cartslot to %d\n", slotnumber);
172	230	if (cartslots->fixed_slot==AUTO)
r7613	r7614
175	233	cartslots->active_slot = cartslots->fixed_slot;
176	234	}
177	235
178		/*
179		Allows to manually lock the cartslot system to a specific slot.
180		Called from the machine driver, taking the dipswitch setting.
181		We take slot numbers from 0 (automatic mode) to the maximum.
182		*/
183		void ti99_lock_cartridge_slot(running_device *cartsys, int slotnumber)
184		{
185		ti99_multicart_t *cartslots = (ti99_multicart_t *)cartsys->token;
186		assert(slotnumber>=0 && slotnumber<=255);
187		cartslots->fixed_slot = slotnumber-1; /* auto = -1 */
188		}
189
190	236	static int slot_is_empty(running_device *cartsys, int slotnumber)
191	237	{
192	238	cartridge_t *cart;
193		ti99_multicart_t *cartslots = (ti99_multicart_t *)cartsys->token;
	239	ti99_multicart_state *cartslots = (ti99_multicart_state *)cartsys->token;
194	240
195	241	cart = &cartslots->cartridge[slotnumber];
196	242
r7613	r7614
202	248	static void clear_slot(running_device *cartsys, int slotnumber)
203	249	{
204	250	cartridge_t *cart;
205		ti99_multicart_t *cartslots = (ti99_multicart_t *)cartsys->token;
	251	ti99_multicart_state *cartslots = (ti99_multicart_state *)cartsys->token;
206	252
207	253	cart = &cartslots->cartridge[slotnumber];
208	254
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213	259	cart->grom_ptr = NULL;
214	260	}
215	261
	262	static void grom_write_address(ti99_multicart_state *cartslots, UINT8 data)
	263	{
	264	/* We are writing; the read states will automatically fall back to default. */
	265	cartslots->raddr_LSB = FALSE;
	266
	267	/* Fore more comments, see machine/ti99_4x.c */
	268	if (cartslots->waddr_LSB)
	269	{
	270	/* Accept low byte (2nd write) */
	271	cartslots->grom_address = (cartslots->grom_address & 0xff00) | (data & 0x00ff);
	272	cartslots->waddr_LSB = FALSE;
	273	}
	274	else
	275	{
	276	/* Accept high byte (1st write) */
	277	cartslots->grom_address = ((data<<8) & 0xff00) | (cartslots->grom_address & 0x00ff);
	278	cartslots->waddr_LSB = TRUE;
	279	}
	280	}
	281
216	282	/*
217		GROM access. Accesses the GROMs in the cartridge. GROM memory is
218		accessed serially via a set of ports. The GRMWA port (bank 0: 0x9c02)
219		takes two consecutive byte writes which represent the high and low byte
220		of the memory address in the GROM space. Once set, bytes can be read
221		by repeated read accesses on the GRMRD port (bank 0: 0x9800). The
222		address pointer advances on each read. The pointer wraps at the end
223		of each GROM chip memory space, i.e. every 8KiB.
224		This function takes the current GROM address minus 0x6000 which is the
225		lowest address for cartridge GROMs. Lower addresses access GROMs in the
226		console only, which appear in all banks.
227		Note that the GROM access mechanism is identical for all cartridge
228		types.
	283	Set the address pointer value or write to GRAM (if available).
229	284	*/
230		UINT8 ti99_cartridge_grom_read(running_device *device, int cart_offset)
	285	WRITE8_DEVICE_HANDLER(ti99_cartridge_grom_w)
231	286	{
	287	ti99_multicart_state *cartslots = (ti99_multicart_state *)device->token;
	288
	289	/* Set the cart slot. Note that the port must be adjusted for 16-bit
	290	systems, i.e. it should be shifted left by 1.
	291	// 1001 1wbb bbbb bbr0
	292	*/
	293	cartridge_slot_set(device, (offset>>2) & 0x00ff);
	294
	295	if (offset & 0x0002)
	296	grom_write_address(cartslots, data);
	297	else
	298	cartslots->raddr_LSB = cartslots->waddr_LSB = FALSE;
	299	/* TODO: write to GRAM */
	300	}
	301
	302	/*
	303	Deliver the local address pointer value. Note that this must be
	304	in sync with the console.
	305	*/
	306	static UINT8 grom_read_address(ti99_multicart_state *cartslots)
	307	{
	308	UINT8 reply;
	309	/* When reading, reset the hi/lo flag byte for writing.
	310	TODO: Verify this with a real machine. */
	311	cartslots->waddr_LSB = FALSE;
	312
	313	/* Address reading is done in two steps; first, the high byte
	314	is transferred, then the low byte. */
	315	if (cartslots->raddr_LSB)
	316	{
	317	/* second pass */
	318	reply = cartslots->grom_address & 0x00ff;
	319	cartslots->raddr_LSB = FALSE;
	320	}
	321	else
	322	{
	323	/* first pass */
	324	reply = (cartslots->grom_address>>8) & 0x00ff;
	325	cartslots->raddr_LSB = TRUE;
	326	}
	327	return reply;
	328	}
	329
	330	/*
	331	GROM access. Accesses the GROMs in the cartridge. GROM memory is
	332	accessed serially via a set of ports. The GRMWA port (bank 0: 0x9c02)
	333	takes two consecutive byte writes which represent the high and low byte
	334	of the memory address in the GROM space. Once set, bytes can be read
	335	by repeated read accesses on the GRMRD port (bank 0: 0x9800). The
	336	address pointer advances on each read. The pointer wraps at the end
	337	of each GROM chip memory space, i.e. every 8KiB.
	338	This function takes the current GROM address minus 0x6000 which is the
	339	lowest address for cartridge GROMs. Lower addresses access GROMs in the
	340	console only, which appear in all banks.
	341	Note that the GROM access mechanism is identical for all cartridge
	342	types.
	343	*/
	344	READ8_DEVICE_HANDLER(ti99_cartridge_grom_r)
	345	{
232	346	UINT8 value;
233	347	int slot;
234	348	cartridge_t *cartridge;
235		ti99_multicart_t *cartslots = (ti99_multicart_t *)device->token;
	349	ti99_multicart_state *cartslots = (ti99_multicart_state *)device->token;
236	350
	351	/* Set the cart slot. Note that the port must be adjusted for 16-bit
	352	systems, i.e. it should be shifted left by 1.
	353	1001 1wbb bbbb bbr0
	354	*/
	355	cartridge_slot_set(device, (offset>>2) & 0x00ff);
	356
	357	if (offset & 0x0002)
	358	return grom_read_address(cartslots);
	359
237	360	/* Handle the legacy mode. */
238	361	if (in_legacy_mode(device))
239		return cartridge_grom_read_legacy(device, cart_offset);
	362	return cartridge_grom_read_legacy(device);
240	363
241	364	slot = cartslots->active_slot;
242	365	/*
243		This fixes a minor issue: The selection mechanism of the console
244		concludes that there are multiple cartridges plugged in when it
245		checks the different GROM bases and finds different data. Empty
246		slots should return 0 at all addresses, but when we have only
247		one cartridge, this entails that the second cartridge is
248		different (all zeros), and so we get a meaningless selection
249		option between cartridge 1 and 1 and 1 ...
250
251		So if next_free_slot==1, we have one cartridge in slot 0.
252		In that case we trick the OS to believe that the addressed
253		cartridge appears at all locations which causes it to assume a
254		standard single cartslot.
255		*/
	366	This fixes a minor issue: The selection mechanism of the console
	367	concludes that there are multiple cartridges plugged in when it
	368	checks the different GROM bases and finds different data. Empty
	369	slots should return 0 at all addresses, but when we have only
	370	one cartridge, this entails that the second cartridge is
	371	different (all zeros), and so we get a meaningless selection
	372	option between cartridge 1 and 1 and 1 ...
	373
	374	So if next_free_slot==1, we have one cartridge in slot 0.
	375	In that case we trick the OS to believe that the addressed
	376	cartridge appears at all locations which causes it to assume a
	377	standard single cartslot.
	378	*/
256	379	if (cartslots->fixed_slot==AUTO && cartslots->next_free_slot==1)
257	380	slot=0;
258	381
r7613	r7614
261	384	else
262	385	{
263	386	cartridge = &cartslots->cartridge[slot];
264
265	387	if ((cartridge->grom_size>0) && (cartridge->pcb!=NULL))
266	388	{
267	389	/* This is the reason why we need the image size: Read
268		access beyond the image size must be detected. */
269		if (cart_offset > cartridge->grom_size)
270		return 0;
271
272		value = (UINT8)cartridge->grom_buffer;
273		/* read ahead */
274		cartridge->grom_buffer = cartridge->grom_ptr[cart_offset];
	390	access beyond the image size must be detected. */
	391	/* TODO: replace this using a bitmap of the available GROMs */
	392	if ((cartslots->grom_address < 0x6000) || (cartslots->grom_address > (cartridge->grom_size+0x6000)))
	393	value = 0;
	394	else
	395	{
	396	/* Buffered GROM access. We use a (virtual) common buffer to avoid implementing this for each cartridge. */
	397	value = (UINT8)cartslots->grom_buffer;
	398	/* read ahead */
	399	cartslots->grom_buffer = cartridge->grom_ptr[cartslots->grom_address-0x6000];
	400	}
275	401	}
276	402	else
277	403	{
278	404	/* We assume that empty sockets return 0 */
279	405	value = 0;
280		logerror("Empty socket at address G(%d)>%04x\n", slot, 0x6000 + cart_offset);
	406	//printf("Empty socket at address G(%d)>%04x\n", slot, cartslots->grom_address);
281	407	}
	408	//         printf("GROM address (cart) = %04x, reply = %02x\n", cartslots->grom_address, value);
	409	/* The program counter wraps at each GROM chip size (8K),
	410	so 0x5fff + 1 = 0x4000. */
	411	cartslots->grom_address = ((cartslots->grom_address + 1) & 0x1FFF) | (cartslots->grom_address & 0xE000);
	412
	413	/* Reset the read and write address flipflops. */
	414	cartslots->raddr_LSB = cartslots->waddr_LSB = FALSE;
282	415	}
283		//  printf("grom access(port = %x, address = %04x) = %02x\n", slot,  0x6000 + cart_offset*2, value);
284	416	return value;
285	417	}
286	418
287	419	/*
288		Find the index of the cartridge name. We assume the format
289		<name><number>, i.e. the number is the longest string from the right
290		which can be interpreted as a number.
	420	Find the index of the cartridge name. We assume the format
	421	<name><number>, i.e. the number is the longest string from the right
	422	which can be interpreted as a number.
291	423	*/
292	424	static int get_index_from_tagname(running_device *image)
293	425	{
r7613	r7614
301	433	}
302	434
303	435	/*
304		Common routine to assemble cartridges from resources.
	436	Common routine to assemble cartridges from resources.
305	437	*/
306	438	static cartridge_t *assemble_common(running_device *cartslot)
307	439	{
308	440	/* Pointer to the cartridge structure. */
309	441	cartridge_t *cartridge;
310	442	running_device *cartsys = cartslot->owner;
311		ti99_multicart_t *cartslots = (ti99_multicart_t *)cartsys->token;
312
	443	ti99_multicart_state *cartslots = (ti99_multicart_state *)cartsys->token;
	444
313	445	void *socketcont;
314	446	int reslength;
315	447	int i;
316
	448
317	449	int slotnumber = get_index_from_tagname(cartslot)-1;
318	450	assert(slotnumber>=0 && slotnumber<NUMBER_OF_CARTRIDGE_SLOTS);
319
	451
320	452	/* There is a cartridge in this slot, check the maximum slot number. */
321	453	if (cartslots->next_free_slot <= slotnumber)
322	454	{
323	455	cartslots->next_free_slot = slotnumber+1;
324	456	}
325	457	cartridge = &cartslots->cartridge[slotnumber];
326
	458
327	459	/* Get the socket which is retrieved by the multicart instance in
328		the state of the cartslot instance. */
	460	the state of the cartslot instance. */
329	461	socketcont = cartslot_get_socket(cartslot, "grom_socket");
330	462	reslength = cartslot_get_resource_length(cartslot, "grom_socket");
331	463	if (socketcont != NULL)
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333	465	cartridge->grom_ptr = (UINT8 *)socketcont;
334	466	cartridge->grom_size = reslength;
335	467	}
336
	468
337	469	socketcont = cartslot_get_socket(cartslot, "rom_socket");
338	470	reslength = cartslot_get_resource_length(cartslot, "rom_socket");
339	471	if (socketcont != NULL)
r7613	r7614
348	480	cont16b[i] = BIG_ENDIANIZE_INT16(cont16b[i]);
349	481	}
350	482	}
351
	483
352	484	socketcont = cartslot_get_socket(cartslot, "rom2_socket");
353	485	//  reslength = cartslot_get_resource_length(cartslot, "rom2_socket");  /* cannot differ from rom_socket */
354	486	if (socketcont != NULL)
r7613	r7614
384	516	static void set_pointers(running_device *pcb, int index)
385	517	{
386	518	running_device *cartsys = pcb->owner->owner;
387		ti99_multicart_t *cartslots = (ti99_multicart_t *)cartsys->token;
	519	ti99_multicart_state *cartslots = (ti99_multicart_state *)cartsys->token;
388	520	ti99_pcb_t *pcb_def = (ti99_pcb_t *)pcb->token;
389	521
390	522	pcb_def->read = (read16_device_func) pcb->get_config_fct(TI99CARTINFO_FCT_6000_R);
r7613	r7614
511	643	int i;
512	644	cartridge_t *cart;
513	645	running_device *cartsys = image->owner;
514		ti99_multicart_t *cartslots = (ti99_multicart_t *)cartsys->token;
	646	ti99_multicart_state *cartslots = (ti99_multicart_state *)cartsys->token;
515	647
516	648	slotnumber = get_index_from_tagname(image)-1;
517	649	//  printf("Disassemble cartridge %d\n", slotnumber);
r7613	r7614
1866	1998	{
1867	1999	running_device *pcbdev = cartslot_get_pcb(image);
1868	2000	running_device *cartsys = image->owner;
1869		ti99_multicart_t *cartslots = (ti99_multicart_t *)cartsys->token;
	2001	ti99_multicart_state *cartslots = (ti99_multicart_state *)cartsys->token;
1870	2002
1871	2003	int result;
1872	2004
r7613	r7614
1881	2013	/* If we are here, we have a multicart. */
1882	2014	ti99_pcb_t *pcb = (ti99_pcb_t *)pcbdev->token;
1883	2015	cartslot_t *cart = (cartslot_t *)image->token;
1884
	2016
1885	2017	/* try opening this as a multicart */
1886	2018	/* This line requires that cartslot_t be included in cartslot.h,
1887		otherwise one cannot make use of multicart handling within such a
1888		custom LOAD function. */
	2019	otherwise one cannot make use of multicart handling within such a
	2020	custom LOAD function. */
1889	2021	multicart_open_error me = multicart_open(image_filename(image), image->machine->gamedrv->name, MULTICART_FLAGS_LOAD_RESOURCES, &cart->mc);
1890
	2022
1891	2023	/* Now that we have loaded the image files, let the PCB put them all
1892		together. This means we put the images in a structure which allows
1893		for a quick access by the memory handlers. Every PCB defines an
1894		own assembly method. */
	2024	together. This means we put the images in a structure which allows
	2025	for a quick access by the memory handlers. Every PCB defines an
	2026	own assembly method. */
1895	2027	if (me == MCERR_NONE)
1896	2028	result = pcb->assemble(image);
1897	2029	else
1898	2030	fatalerror("Error loading multicart: %s\n", multicart_error_text(me));
1899
	2031
1900	2032	/* This is for legacy support. If we have no multicart left
1901		but there are still legacy dumps, we switch to legacy mode. */
	2033	but there are still legacy dumps, we switch to legacy mode. */
1902	2034	if (result != INIT_FAIL)
1903	2035	cartslots->multi_slots++;
1904	2036	}
r7613	r7614
1917	2049	static DEVICE_IMAGE_UNLOAD( ti99_cartridge )
1918	2050	{
1919	2051	running_device *pcbdev;
1920		ti99_multicart_t *cartslots = (ti99_multicart_t *)image->owner->token;
	2052	ti99_multicart_state *cartslots = (ti99_multicart_state *)image->owner->token;
1921	2053
1922	2054	if (image->token == NULL)
1923	2055	{
r7613	r7614
1977	2109	- Both modes may change on plugging and unplugging.
1978	2110	******************************************************************************/
1979	2111
1980		static UINT8 cartridge_grom_read_legacy(running_device *cartsys, int cart_offset)
	2112	static UINT8 cartridge_grom_read_legacy(running_device *cartsys)
1981	2113	{
1982	2114	int slot;
1983	2115	cartridge_t *cartridge;
1984		ti99_multicart_t *cartslots = (ti99_multicart_t *)cartsys->token;
	2116	ti99_multicart_state *cartslots = (ti99_multicart_state *)cartsys->token;
1985	2117
1986	2118	UINT8 value;
1987	2119
r7613	r7614
1996	2128	if (cartridge->grom_size>0)
1997	2129	{
1998	2130	/* This is the reason why we need the image size: Read
1999		access beyond the image size must be detected. */
2000		if (cart_offset > cartridge->grom_size)
	2131	access beyond the image size must be detected. */
	2132	if ((cartslots->grom_address < 0x6000) || (cartslots->grom_address > (cartridge->grom_size+0x6000)))
2001	2133	return 0;
2002
2003		value = (UINT8)cartridge->grom_buffer;
	2134
	2135	value =  (UINT8)cartslots->grom_buffer;
2004	2136	/* read ahead */
2005		cartridge->grom_buffer = cartridge->grom_ptr[cart_offset];
	2137	cartslots->grom_buffer = cartridge->grom_ptr[cartslots->grom_address-0x6000];
	2138	//  printf("GROM address = %04x, reply = %02x\n", console_GROMs.addr, reply>>8);
	2139	/* The program counter wraps at each GROM chip size (8K),
	2140	so 0x5fff + 1 = 0x4000. */
	2141	cartslots->grom_address = ((cartslots->grom_address + 1) & 0x1FFF) | (cartslots->grom_address & 0xE000);
	2142
	2143	/* Reset the read and write address flipflops. */
	2144	cartslots->raddr_LSB = cartslots->waddr_LSB = FALSE;
2006	2145	}
2007	2146	else
2008	2147	{
2009	2148	/* We assume that empty sockets return 0 */
2010	2149	value = 0;
2011		logerror("Empty socket at address G(%d)>%04x\n", slot, 0x6000 + cart_offset);
	2150	logerror("Empty socket at address G(%d)>%04x\n", slot, cartslots->grom_address);
2012	2151	}
2013
2014		//  printf("grom access(port = %x, address = %04x) = %02x\n", slot,  0x6000 + cart_offset*2, value);
2015	2152	return value;
2016	2153	}
2017	2154
2018	2155	static READ16_DEVICE_HANDLER( ti99_cart_r_legacy )
2019	2156	{
2020	2157	int slotmbx, slotmini, slotebr2, slotrom;
2021		ti99_multicart_t *cartslots = (ti99_multicart_t *)device->token;
	2158	ti99_multicart_state *cartslots = (ti99_multicart_state *)device->token;
2022	2159
2023	2160	#if 0
2024	2161	if (hsgpl_crdena)
r7613	r7614
2063	2200	static WRITE16_DEVICE_HANDLER( ti99_cart_w_legacy )
2064	2201	{
2065	2202	int slotmbx, slotmini, slotebr2, slotrom;
2066		ti99_multicart_t *cartslots = (ti99_multicart_t *)device->token;
	2203	ti99_multicart_state *cartslots = (ti99_multicart_state *)device->token;
2067	2204
2068	2205	#if 0
2069	2206	if (hsgpl_crdena)
r7613	r7614
2117	2254	static READ8_DEVICE_HANDLER( ti99_cart_r_legacy8 )
2118	2255	{
2119	2256	int slotmbx, slotmini, slotebr2, slotrom;
2120		ti99_multicart_t *cartslots = (ti99_multicart_t *)device->token;
	2257	ti99_multicart_state *cartslots = (ti99_multicart_state *)device->token;
2121	2258
2122	2259	#if 0
2123	2260	if (hsgpl_crdena)
r7613	r7614
2165	2302	static WRITE8_DEVICE_HANDLER( ti99_cart_w_legacy8 )
2166	2303	{
2167	2304	int slotmbx, slotmini, slotebr2, slotrom;
2168		ti99_multicart_t *cartslots = (ti99_multicart_t *)device->token;
	2305	ti99_multicart_state *cartslots = (ti99_multicart_state *)device->token;
2169	2306
2170	2307	#if 0
2171	2308	if (hsgpl_crdena)
r7613	r7614
2217	2354	static int load_legacy(running_device *image)
2218	2355	{
2219	2356	running_device *cartsys = image->owner;
2220		ti99_multicart_t *cartslots = (ti99_multicart_t *)cartsys->token;
	2357	ti99_multicart_state *cartslots = (ti99_multicart_state *)cartsys->token;
2221	2358
2222	2359	/* Some comments originally in machine/ti99_4x.c */
2223	2360
r7613	r7614
2437	2574	int i;
2438	2575	running_device *cartsys = image->owner;
2439	2576
2440		ti99_multicart_t *cartslots = (ti99_multicart_t *)cartsys->token;
	2577	ti99_multicart_state *cartslots = (ti99_multicart_state *)cartsys->token;
2441	2578
2442	2579	slotc_type_t type = SLOTC_EMPTY;
2443	2580	int slot = get_index_from_tagname(image)-1;
r7613	r7614
2534	2671	{
2535	2672	int i;
2536	2673	//  printf("DEVICE_START(ti99_multicart)\n");
2537		ti99_multicart_t *cartslots = (ti99_multicart_t *)device->token;
	2674	ti99_multicart_state *cartslots = (ti99_multicart_state *)device->token;
2538	2675
2539	2676	cartslots->active_slot = 0;
2540	2677	cartslots->next_free_slot = 0;
r7613	r7614
2567	2704	static DEVICE_RESET(ti99_multicart)
2568	2705	{
2569	2706	/* Consider to propagate RESET to cartridges.
2570		However, schematics do not reveal any pin for resetting a cartridge;
2571		the reset line is an input used when plugging in a cartridge. */
2572		//    printf("DEVICE_RESET(ti99_multicart)\n");
	2707	However, schematics do not reveal any pin for resetting a cartridge;
	2708	the reset line is an input used when plugging in a cartridge. */
	2709
	2710	/* Allows to manually lock the cartslot system to a specific slot.
	2711	We take slot numbers from 0 (automatic mode) to the maximum. */
	2712
	2713	ti99_multicart_state *cartslots = (ti99_multicart_state *)device->token;
	2714	int slotnumber = (input_port_read(device->machine, "CFG") >> config_cartslot_bit) & config_cartslot_mask;
	2715	assert(slotnumber>=0 && slotnumber<=255);
	2716	cartslots->fixed_slot = slotnumber-1; /* auto = -1 */
	2717	cartslots->grom_address = 0x0000;
	2718	cartslots->grom_buffer = 0x00;
	2719	cartslots->raddr_LSB = cartslots->waddr_LSB = FALSE;
2573	2720	}
2574	2721
2575	2722	/*
r7613	r7614
2584	2731	*/
2585	2732	READ16_DEVICE_HANDLER( ti99_multicart_r )
2586	2733	{
2587		ti99_multicart_t *cartslots = (ti99_multicart_t *) device->token;
	2734	ti99_multicart_state *cartslots = (ti99_multicart_state *) device->token;
2588	2735	int slot = cartslots->active_slot;
2589	2736	cartridge_t *cart;
2590
	2737
2591	2738	/* Sanity check. Higher slots are always empty. */
2592	2739	if (slot >= NUMBER_OF_CARTRIDGE_SLOTS)
2593	2740	return 0;
2594
	2741
2595	2742	/* Same as above (GROM read): If there is only one cartridge there
2596		is no use of trying other banks. There is one issue with the
2597		selection mechanism: When the console probes the GROM banks and
2598		we have a ROM-only cartridge plugged in, it checks bank 0 and bank 1,
2599		finds no GROM, and then fails to dummy-check bank 0 again which would
2600		have set our cartridge expander to slot 0. But in slot 1 there is no
2601		ROM cartridge, so nothing shows up in the selection list. We work
2602		around this with the following line. */
	2743	is no use of trying other banks. There is one issue with the
	2744	selection mechanism: When the console probes the GROM banks and
	2745	we have a ROM-only cartridge plugged in, it checks bank 0 and bank 1,
	2746	finds no GROM, and then fails to dummy-check bank 0 again which would
	2747	have set our cartridge expander to slot 0. But in slot 1 there is no
	2748	ROM cartridge, so nothing shows up in the selection list. We work
	2749	around this with the following line. */
2603	2750	if (cartslots->fixed_slot==AUTO && cartslots->next_free_slot==1)
2604	2751	slot=0;
2605
	2752
2606	2753	cart = &cartslots->cartridge[slot];
2607
	2754
2608	2755	/* Idle the CPU */
2609	2756	cpu_adjust_icount(devtag_get_device(device->machine, "maincpu"),-4);
2610
	2757
2611	2758	// Alternatively:
2612	2759	// cpu_spinuntil_time(device->machine->firstcpu, ATTOTIME_IN_USEC(6));
2613
2614		//  printf("rpk = %d, bin = %d\n", cartslots->multi_slots,cartslots->legacy_slots);
2615
	2760
	2761	//  printf("rpk = %d, bin = %d\n", cartslots->multi_slots,cartslots->legacy_slots);
	2762
2616	2763	/* Handle legacy mode. */
2617	2764	if (in_legacy_mode(device))
2618	2765	{
2619	2766	return ti99_cart_r_legacy(device, offset, mem_mask);
2620	2767	}
2621
	2768
2622	2769	if (!slot_is_empty(device, slot))
2623	2770	{
2624		//      printf("accessing cartridge in slot %d\n", slot);
	2771	//      printf("accessing cartridge in slot %d\n", slot);
2625	2772	ti99_pcb_t *pcbdef = (ti99_pcb_t *)cart->pcb->token;
2626		//      printf("address=%lx, offset=%lx\n", pcbdef, offset);
	2773	//      printf("address=%lx, offset=%lx\n", pcbdef, offset);
2627	2774	return (*pcbdef->read)(cart->pcb, offset, mem_mask);
2628	2775	}
2629	2776	else
2630	2777	{
2631		//      printf("No cartridge in slot %d\n", slot);
	2778	//      printf("No cartridge in slot %d\n", slot);
2632	2779	return 0;
2633	2780	}
2634	2781	}
2635	2782
2636	2783	/*
2637		Accesses the ROM regions of the cartridge for writing.
2638		This is the area from 0x6000 to 0x7fff. Each cartridge is reponsible
2639		for all kinds of magic which is done inside this area. Specifically,
2640		writing is often used to swap banks for subsequent reads. The actual
2641		effect of writing (beyond setting values in a RAM chip) are
2642		cartridge-specific and must be handled within the cartridge pcb.
2643		The currently set GROM bank determines which cartridge is actually
2644		accessed, also for ROM reads.
	2784	Accesses the ROM regions of the cartridge for writing.
	2785	This is the area from 0x6000 to 0x7fff. Each cartridge is reponsible
	2786	for all kinds of magic which is done inside this area. Specifically,
	2787	writing is often used to swap banks for subsequent reads. The actual
	2788	effect of writing (beyond setting values in a RAM chip) are
	2789	cartridge-specific and must be handled within the cartridge pcb.
	2790	The currently set GROM bank determines which cartridge is actually
	2791	accessed, also for ROM reads.
2645	2792	*/
2646	2793	WRITE16_DEVICE_HANDLER( ti99_multicart_w )
2647	2794	{
2648		ti99_multicart_t *cartslots = (ti99_multicart_t *) device->token;
	2795	ti99_multicart_state *cartslots = (ti99_multicart_state *) device->token;
2649	2796	int slot = cartslots->active_slot;
2650	2797	cartridge_t *cart;
2651	2798
r7613	r7614
2687	2834	*/
2688	2835	READ8_DEVICE_HANDLER( ti99_multicart_cru_r )
2689	2836	{
2690		ti99_multicart_t *cartslots = (ti99_multicart_t *) device->token;
	2837	ti99_multicart_state *cartslots = (ti99_multicart_state *) device->token;
2691	2838	cartridge_t *cart;
2692	2839
2693	2840	int slot = cartslots->active_slot;
r7613	r7614
2720	2867	*/
2721	2868	WRITE8_DEVICE_HANDLER( ti99_multicart_cru_w )
2722	2869	{
2723		ti99_multicart_t *cartslots = (ti99_multicart_t *) device->token;
	2870	ti99_multicart_state *cartslots = (ti99_multicart_state *) device->token;
2724	2871	cartridge_t *cart;
2725	2872
2726	2873	int slot = cartslots->active_slot;
r7613	r7614
2753	2900	*/
2754	2901	READ8_DEVICE_HANDLER(ti99_multicart8_r)
2755	2902	{
2756		ti99_multicart_t *cartslots = (ti99_multicart_t *) device->token;
	2903	ti99_multicart_state *cartslots = (ti99_multicart_state *) device->token;
2757	2904	cartridge_t *cart;
2758	2905
2759	2906	int slot = cartslots->active_slot;
r7613	r7614
2792	2939
2793	2940	WRITE8_DEVICE_HANDLER(ti99_multicart8_w)
2794	2941	{
2795		ti99_multicart_t *cartslots = (ti99_multicart_t *) device->token;
	2942	ti99_multicart_state *cartslots = (ti99_multicart_state *) device->token;
2796	2943	cartridge_t *cart;
2797	2944
2798	2945	int slot = cartslots->active_slot;
r7613	r7614
2824	2971	}
2825	2972	}
2826	2973	}
	2974	#define TI99_CARTRIDGE_SLOT(p)  MDRV_CARTSLOT_ADD(p) \
	2975	MDRV_CARTSLOT_EXTENSION_LIST("rpk,bin") \
	2976	MDRV_CARTSLOT_PCBTYPE(0, "none", TI99_CARTRIDGE_PCB_NONE) \
	2977	MDRV_CARTSLOT_PCBTYPE(1, "standard", TI99_CARTRIDGE_PCB_STD) \
	2978	MDRV_CARTSLOT_PCBTYPE(2, "paged", TI99_CARTRIDGE_PCB_PAGED) \
	2979	MDRV_CARTSLOT_PCBTYPE(3, "minimem", TI99_CARTRIDGE_PCB_MINIMEM) \
	2980	MDRV_CARTSLOT_PCBTYPE(4, "super", TI99_CARTRIDGE_PCB_SUPER) \
	2981	MDRV_CARTSLOT_PCBTYPE(5, "mbx", TI99_CARTRIDGE_PCB_MBX) \
	2982	MDRV_CARTSLOT_PCBTYPE(6, "paged379i", TI99_CARTRIDGE_PCB_PAGED379I) \
	2983	MDRV_CARTSLOT_PCBTYPE(7, "pagedcru", TI99_CARTRIDGE_PCB_PAGEDCRU) \
	2984	MDRV_CARTSLOT_START(ti99_cartridge) \
	2985	MDRV_CARTSLOT_LOAD(ti99_cartridge) \
	2986	MDRV_CARTSLOT_UNLOAD(ti99_cartridge)
2827	2987
2828	2988	static MACHINE_DRIVER_START(ti99_multicart)
2829		MDRV_CARTSLOT_ADD("cartridge1")
2830		MDRV_CARTSLOT_EXTENSION_LIST("rpk,bin")
2831		MDRV_CARTSLOT_PCBTYPE(0, "none", TI99_CARTRIDGE_PCB_NONE)
2832		MDRV_CARTSLOT_PCBTYPE(1, "standard", TI99_CARTRIDGE_PCB_STD)
2833		MDRV_CARTSLOT_PCBTYPE(2, "paged", TI99_CARTRIDGE_PCB_PAGED)
2834		MDRV_CARTSLOT_PCBTYPE(3, "minimem", TI99_CARTRIDGE_PCB_MINIMEM)
2835		MDRV_CARTSLOT_PCBTYPE(4, "super", TI99_CARTRIDGE_PCB_SUPER)
2836		MDRV_CARTSLOT_PCBTYPE(5, "mbx", TI99_CARTRIDGE_PCB_MBX)
2837		MDRV_CARTSLOT_PCBTYPE(6, "paged379i", TI99_CARTRIDGE_PCB_PAGED379I)
2838		MDRV_CARTSLOT_PCBTYPE(7, "pagedcru", TI99_CARTRIDGE_PCB_PAGEDCRU)
2839
2840		MDRV_CARTSLOT_START(ti99_cartridge)
2841		MDRV_CARTSLOT_LOAD(ti99_cartridge)
2842		MDRV_CARTSLOT_UNLOAD(ti99_cartridge)
2843
2844		MDRV_CARTSLOT_ADD("cartridge2")
2845		MDRV_CARTSLOT_EXTENSION_LIST("rpk,bin")
2846		MDRV_CARTSLOT_PCBTYPE(0, "none", TI99_CARTRIDGE_PCB_NONE)
2847		MDRV_CARTSLOT_PCBTYPE(1, "standard", TI99_CARTRIDGE_PCB_STD)
2848		MDRV_CARTSLOT_PCBTYPE(2, "paged", TI99_CARTRIDGE_PCB_PAGED)
2849		MDRV_CARTSLOT_PCBTYPE(3, "minimem", TI99_CARTRIDGE_PCB_MINIMEM)
2850		MDRV_CARTSLOT_PCBTYPE(4, "super", TI99_CARTRIDGE_PCB_SUPER)
2851		MDRV_CARTSLOT_PCBTYPE(5, "mbx", TI99_CARTRIDGE_PCB_MBX)
2852		MDRV_CARTSLOT_PCBTYPE(6, "paged379i", TI99_CARTRIDGE_PCB_PAGED379I)
2853		MDRV_CARTSLOT_PCBTYPE(7, "pagedcru", TI99_CARTRIDGE_PCB_PAGEDCRU)
2854
2855		MDRV_CARTSLOT_START(ti99_cartridge)
2856		MDRV_CARTSLOT_LOAD(ti99_cartridge)
2857		MDRV_CARTSLOT_UNLOAD(ti99_cartridge)
2858
2859		MDRV_CARTSLOT_ADD("cartridge3")
2860		MDRV_CARTSLOT_EXTENSION_LIST("rpk,bin")
2861		MDRV_CARTSLOT_PCBTYPE(0, "none", TI99_CARTRIDGE_PCB_NONE)
2862		MDRV_CARTSLOT_PCBTYPE(1, "standard", TI99_CARTRIDGE_PCB_STD)
2863		MDRV_CARTSLOT_PCBTYPE(2, "paged", TI99_CARTRIDGE_PCB_PAGED)
2864		MDRV_CARTSLOT_PCBTYPE(3, "minimem", TI99_CARTRIDGE_PCB_MINIMEM)
2865		MDRV_CARTSLOT_PCBTYPE(4, "super", TI99_CARTRIDGE_PCB_SUPER)
2866		MDRV_CARTSLOT_PCBTYPE(5, "mbx", TI99_CARTRIDGE_PCB_MBX)
2867		MDRV_CARTSLOT_PCBTYPE(6, "paged379i", TI99_CARTRIDGE_PCB_PAGED379I)
2868		MDRV_CARTSLOT_PCBTYPE(7, "pagedcru", TI99_CARTRIDGE_PCB_PAGEDCRU)
2869
2870		MDRV_CARTSLOT_START(ti99_cartridge)
2871		MDRV_CARTSLOT_LOAD(ti99_cartridge)
2872		MDRV_CARTSLOT_UNLOAD(ti99_cartridge)
2873
2874		MDRV_CARTSLOT_ADD("cartridge4")
2875		MDRV_CARTSLOT_EXTENSION_LIST("rpk,bin")
2876		MDRV_CARTSLOT_PCBTYPE(0, "none", TI99_CARTRIDGE_PCB_NONE)
2877		MDRV_CARTSLOT_PCBTYPE(1, "standard", TI99_CARTRIDGE_PCB_STD)
2878		MDRV_CARTSLOT_PCBTYPE(2, "paged", TI99_CARTRIDGE_PCB_PAGED)
2879		MDRV_CARTSLOT_PCBTYPE(3, "minimem", TI99_CARTRIDGE_PCB_MINIMEM)
2880		MDRV_CARTSLOT_PCBTYPE(4, "super", TI99_CARTRIDGE_PCB_SUPER)
2881		MDRV_CARTSLOT_PCBTYPE(5, "mbx", TI99_CARTRIDGE_PCB_MBX)
2882		MDRV_CARTSLOT_PCBTYPE(6, "paged379i", TI99_CARTRIDGE_PCB_PAGED379I)
2883		MDRV_CARTSLOT_PCBTYPE(7, "pagedcru", TI99_CARTRIDGE_PCB_PAGEDCRU)
2884
2885		MDRV_CARTSLOT_START(ti99_cartridge)
2886		MDRV_CARTSLOT_LOAD(ti99_cartridge)
2887		MDRV_CARTSLOT_UNLOAD(ti99_cartridge)
	2989	TI99_CARTRIDGE_SLOT("cartridge1")
	2990	TI99_CARTRIDGE_SLOT("cartridge2")
	2991	TI99_CARTRIDGE_SLOT("cartridge3")
	2992	TI99_CARTRIDGE_SLOT("cartridge4")
2888	2993	MACHINE_DRIVER_END
2889	2994
	2995	static const char DEVTEMPLATE_SOURCE[] = __FILE__;
2890	2996
2891		DEVICE_GET_INFO(ti99_multicart)
2892		{
2893		switch (state)
2894		{
2895		/* --- the following bits of info are returned as pointers to data --- */
2896		case DEVINFO_PTR_MACHINE_CONFIG:
2897		info->machine_config = MACHINE_DRIVER_NAME(ti99_multicart); break;
	2997	#define DEVTEMPLATE_ID(p,s)             p##ti99_multicart##s
	2998	#define DEVTEMPLATE_FEATURES            DT_HAS_START | DT_HAS_STOP | DT_HAS_RESET | DT_HAS_MACHINE_CONFIG
	2999	#define DEVTEMPLATE_NAME                "TI99 Multi-Cartridge Extender"
	3000	#define DEVTEMPLATE_FAMILY              "Multi-cartridge system"
	3001	#include "devtempl.h"
2898	3002
2899		/* --- the following bits of info are returned as NULL-terminated strings --- */
2900		case DEVINFO_STR_NAME:
2901		strcpy(info->s, "TI99 Multi-Cartridge Extender");
2902		break;
2903
2904		case DEVINFO_INT_TOKEN_BYTES: /* private storage, automatically allocated */
2905		info->i = sizeof(ti99_multicart_t);
2906		break;
2907		case DEVINFO_INT_CLASS:
2908		info->i = DEVICE_CLASS_PERIPHERAL;
2909		break;
2910
2911		case DEVINFO_STR_FAMILY:
2912		strcpy(info->s, "Multi-cartridge system");
2913		break;
2914		case DEVINFO_STR_VERSION:
2915		strcpy(info->s, "1.0");
2916		break;
2917		case DEVINFO_STR_SOURCE_FILE:
2918		strcpy(info->s, __FILE__);
2919		break;
2920		/* --- the following bits of info are returned as pointers to functions --- */
2921		case DEVINFO_FCT_START:
2922		info->start = DEVICE_START_NAME(ti99_multicart);
2923		break;
2924		case DEVINFO_FCT_STOP:
2925		info->stop = DEVICE_STOP_NAME(ti99_multicart);
2926		break;
2927		case DEVINFO_FCT_RESET:
2928		info->reset = DEVICE_RESET_NAME(ti99_multicart);
2929		break;
2930		}
2931		}
2932

src/mess/devices/ti99cart.h

r7613	r7614
9	9	#ifndef __TI99CART_H__
10	10	#define __TI99CART_H__
11	11
12		#include "image.h"
	12	#define TI99_MULTICART   DEVICE_GET_INFO_NAME(ti99_multicart)
13	13
14		#define TI99_MULTICART         DEVICE_GET_INFO_NAME(ti99_multicart)
15
16		#define TI99_CARTRIDGE_PCB_NONE      DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_none)
17		#define TI99_CARTRIDGE_PCB_STD      DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_std)
18		#define TI99_CARTRIDGE_PCB_PAGED   DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_paged)
19		#define TI99_CARTRIDGE_PCB_MINIMEM   DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_minimem)
20		#define TI99_CARTRIDGE_PCB_SUPER   DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_super)
21		#define TI99_CARTRIDGE_PCB_MBX      DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_mbx)
22		#define TI99_CARTRIDGE_PCB_PAGED379I   DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_paged379i)
23		#define TI99_CARTRIDGE_PCB_PAGEDCRU   DEVICE_GET_INFO_NAME(ti99_cartridge_pcb_pagedcru)
24
25	14	/* We set the number of slots to 8, although we may have up to 16. From a
26	15	logical point of view we could have 256, but the operating system only checks
27	16	the first 16 banks. */
28	17	#define NUMBER_OF_CARTRIDGE_SLOTS 8
29	18
30		/* GROM_port_t: descriptor for a port of 8 GROMs */
31		struct _GROM_port_t
32		{
33		/* pointer to GROM data */
34		UINT8 *data_ptr;
35		/* current address pointer for the active GROM in port (16 bits) */
36		unsigned int addr;
37		/* GROM data buffer */
38		UINT8 buf;
39		/* internal flip-flops that are set after the first access to the GROM
40		address so that next access is mapped to the LSB, and cleared after each
41		data access */
42		char raddr_LSB, waddr_LSB;
43		};
44		typedef struct _GROM_port_t GROM_port_t;
	19	READ8_DEVICE_HANDLER(ti99_cartridge_grom_r);
	20	WRITE8_DEVICE_HANDLER(ti99_cartridge_grom_w);
45	21
46		/* Generic TI99 cartridge structure. */
47		struct _cartridge_t
48		{
49		/* PCB device associated to this cartridge. If NULL, the slot is empty. */
50		running_device *pcb;
51
52		/* GROM buffer size. */
53		int grom_size;
54
55		/* ROM page. */
56		int rom_page;
57		/* RAM page. */
58		int ram_page;
59
60		/* ROM buffer size. All banks have equal sizes. */
61		int rom_size;
62		/* RAM buffer size. All banks have equal sizes. */
63		int ram_size;
64
65		/* pointer to GROM data. */
66		UINT8 *grom_ptr;
67
68		/* GROM buffered data output. */
69		UINT8 grom_buffer;
70
71		/* ROM buffer. We are using this for both 16 bit (99/4a) and 8 bit
72		(99/8) access. */
73		void *rom_ptr;
74
75		/* ROM buffer for the second bank of paged cartridges. Other cartridges
76		usually store their ROM in one large file. */
77		void *rom2_ptr;
78
79		/* RAM buffer. The persistence service is done by the cartridge system.
80		The RAM space is a consecutive space; all banks are in one buffer. */
81		void *ram_ptr;
82		};
83		typedef struct _cartridge_t cartridge_t;
84
85		/* Functions to be called from the console. */
86		void   ti99_cartridge_slot_set(running_device *cartsys, int slotnumber);
87		void   ti99_lock_cartridge_slot(running_device *cartsys, int slotnumber);
88		UINT8  ti99_cartridge_grom_read(running_device *cartsys, int offset);
89
90	22	DEVICE_GET_INFO(ti99_multicart);
91	23
92	24	READ16_DEVICE_HANDLER(ti99_multicart_r);

src/mess/machine/99_dsk.c

r7613	r7614
351	351	static  READ8_HANDLER(fdc_mem_r)
352	352	{
353	353	running_device *fdc = devtag_get_device(space->machine, "wd179x");
354
355		switch (offset)
356		{
357		case 0x1FF0:               /* Status register */
358		return (wd17xx_status_r(fdc, offset) ^ 0xFF);
359		case 0x1FF2:               /* Track register */
360		return wd17xx_track_r(fdc, offset) ^ 0xFF;
361		case 0x1FF4:               /* Sector register */
362		return wd17xx_sector_r(fdc, offset) ^ 0xFF;
363		case 0x1FF6:               /* Data register */
364		return wd17xx_data_r(fdc, offset) ^ 0xFF;
365		default:                  /* DSR ROM */
	354
	355	/* only use the even addresses from 1ff0 to 1ff6.
	356	Note that data is inverted. */
	357	if (offset >= 0x1ff0 && (offset & 0x09)==0)
	358	return wd17xx_r(fdc, (offset >> 1)&0x03) ^ 0xff;
	359	else
366	360	return ti99_disk_DSR[offset];
367		}
368	361	}
369	362
370	363	/*
r7613	r7614
374	367	{
375	368	running_device *fdc = devtag_get_device(space->machine, "wd179x");
376	369
377		data ^= 0xFF;   /* inverted data bus */
378
379		switch (offset)
380		{
381		case 0x1FF8:               /* Command register */
382		wd17xx_command_w(fdc, offset, data);
383		break;
384		case 0x1FFA:               /* Track register */
385		wd17xx_track_w(fdc, offset, data);
386		break;
387		case 0x1FFC:               /* Sector register */
388		wd17xx_sector_w(fdc, offset, data);
389		break;
390		case 0x1FFE:               /* Data register */
391		wd17xx_data_w(fdc, offset, data);
392		break;
393		}
	370	/* only use the even addresses from 1ff8 to 1ffe.
	371	Note that data is inverted. */
	372	if (offset >= 0x1ff0 && (offset & 0x09)==0x08)
	373	wd17xx_w(fdc, (offset >> 1)&0x03, data ^ 0xff);
394	374	}
395	375
396	376

src/mess/machine/ti99pcod.c

r7613	r7614
72	72	*/
73	73	#include "emu.h"
74	74	#include "99_peb.h"
75		#include "devices/ti99cart.h"
76	75	#include "ti99_4x.h"
77	76	#include "ti99pcod.h"
78	77
r7613	r7614
117	116	{
118	117	UINT8 reply;
119	118	/* GROMs are buffered. Data is retrieved from a buffer,
120		while the buffer is replaced with the next cell
121		content. */
	119	while the buffer is replaced with the next cell
	120	content. */
122	121	reply = pcode_GROMs.buf;
123
	122
124	123	/* Get next value, put it in buffer. Note that the
125		GROM wraps at 8K boundaries. */
	124	GROM wraps at 8K boundaries. */
126	125	pcode_GROMs.buf = pcode_GROMs.data_ptr[pcode_GROMs.addr];
127
	126
128	127	/* The program counter wraps at each GROM chip size (8K),
129		so 0x5fff + 1 = 0x4000. */
	128	so 0x5fff + 1 = 0x4000. */
130	129	pcode_GROMs.addr = ((pcode_GROMs.addr + 1) & 0x1FFF) | (pcode_GROMs.addr & 0xE000);
131
	130
132	131	/* Reset the read and write address flipflops. */
133	132	pcode_GROMs.raddr_LSB = pcode_GROMs.waddr_LSB = FALSE;
134
	133
135	134	return reply;
136	135	}
137	136
r7613	r7614
265	264	/* Check if we access the GROM port */
266	265	switch (offset)
267	266	{
268		/* GROMs only answer at even addresses. The odd addresses are
269		undefined, so we can as well just ignore these cases. */
	267	/* GROMs only answer at even addresses. The odd addresses are
	268	undefined, so we can as well just ignore these cases. */
270	269	case 0x1bfc:
271	270	case 0x1bfe:
272	271	reply = ti99_pcode_grom_r(space, offset);
r7613	r7614
278	277	break;
279	278	default:
280	279	/* Accesses ROM 4764 (2*4K)
281		We have two banks here which are activated according
282		to the setting of CRU bit 4
283		*/
	280	We have two banks here which are activated according
	281	to the setting of CRU bit 4
	282	*/
284	283	reply = (bank_select==0)? ti99_pcode_rom1[offset-0x1000] : ti99_pcode_rom2[offset-0x1000];
285	284	}
286	285	}

src/mess/machine/ti99_4x.c

r7613	r7614
425	425	{
426	426	if (gfxparm != 0)
427	427	TMS9928A_configure(gfxparm);
428
	428
429	429	/* Initialize all. Actually, at this point, we don't know
430		how the switches are set. Later we use the configuration switches to
431		determine which one to use. */
	430	how the switches are set. Later we use the configuration switches to
	431	determine which one to use. */
432	432	ti99_peb_init();
433	433	ti99_floppy_controllers_init_all(machine);
434	434	ti99_ide_init(machine);
435	435	ti99_hsgpl_init(machine);
436	436	ti99_usbsm_init(machine);
437
	437
438	438	/* Find the cartslot device and cache it. This is a string search,
439		and we don't want to repeat it on each memory access. */
	439	and we don't want to repeat it on each memory access. */
440	440	cartslots = devtag_get_device(machine, "ti99_multicart");
441	441	assert(cartslots != NULL);
442	442	}
r7613	r7614
542	542	memory_install_read16_handler(space, 0x9000, 0x93ff, 0, 0, ti99_nop_8_r);
543	543	memory_install_write16_handler(space, 0x9400, 0x97ff, 0, 0, ti99_nop_8_w);
544	544	}
545		/* Check whether we have locked the cartslot. This uses GROM, which the 4p doesn't have. */
546		if (ti99_model != model_99_4p)
547		ti99_lock_cartridge_slot(cartslots, (input_port_read(machine, "CFG") >> config_cartslot_bit) & config_cartslot_mask);
548	545
549	546	switch (xRAM_kind)
550	547	{
r7613	r7614
885	882	if (! tms5220_readyq_r())
886	883	{
887	884	/* Weirdly enough, we are always seeing some problems even though
888		everything is working fine. */
	885	everything is working fine. */
889	886	attotime time_to_ready = double_to_attotime(tms5220_time_to_ready());
890	887	logerror("ti99/4a speech says aaargh!\n");
891	888	logerror("(time to ready: %f -> %d)\n", time_to_ready, (int) ceil(3000000*time_to_ready));
r7613	r7614
900	897	static WRITE16_HANDLER ( ti99_wspeech_w )
901	898	{
902	899	cpu_adjust_icount(devtag_get_device(space->machine, "maincpu"),-(54+3));      /* this is just an approx. minimum, it can be much more */
903
904		#if 1
	900
	901	#if 1
905	902	/* the stupid design of the tms5220 core means that ready is cleared when
906		there are 15 bytes in FIFO.  It should be 16.  Of course, if it were the
907		case, we would need to store the value on the bus, which would be more
908		complex. */
	903	there are 15 bytes in FIFO.  It should be 16.  Of course, if it were the
	904	case, we would need to store the value on the bus, which would be more
	905	complex. */
909	906	if (! tms5220_readyq_r(devtag_get_device(space->machine, "tms5220")))
910	907	{
911	908	attotime time_to_ready = double_to_attotime(tms5220_time_to_ready(devtag_get_device(space->machine, "tms5220")));
912	909	int cycles_to_ready = cputag_attotime_to_clocks(space->machine, "maincpu", time_to_ready);
913
	910
914	911	logerror("time to ready: %f -> %d\n", attotime_to_double(time_to_ready), (int) cycles_to_ready);
915
	912
916	913	cpu_adjust_icount(devtag_get_device(space->machine, "maincpu"),-cycles_to_ready);
917	914	timer_set(space->machine, attotime_zero, NULL, 0, /*speech_kludge_callback*/NULL);
918	915	}
919		#endif
920
	916	#endif
	917
921	918	tms5220_data_w(devtag_get_device(space->machine, "tms5220"), offset, (data >> 8) & 0xff);
922	919	}
923	920
924		static UINT8 GROM_dataread(void)
	921	static UINT8 GROM_dataread(offs_t offset)
925	922	{
926		UINT8 reply;
927		if (console_GROMs.addr >= 0x6000)
	923	UINT8 reply = 0, replycart;
	924	int override_console = FALSE; /* for future extension */
	925
	926	if (console_GROMs.addr < 0x6000)
928	927	{
929		/* Pass the (one and only) program counter for GROMs. The
930		buffer is set and used in the cartridge chip. */
931		reply = ti99_cartridge_grom_read(cartslots, console_GROMs.addr-0x6000);
932		}
933		else
934		{
935	928	/* GROMs are buffered. Data is retrieved from a buffer,
936		while the buffer is replaced with the next cell
937		content. */
	929	while the buffer is replaced with the next cell
	930	content. */
938	931	reply = console_GROMs.buf;
939
	932
940	933	/* Get next value, put it in buffer. Note that the
941		GROM wraps at 8K boundaries. */
	934	GROM wraps at 8K boundaries. */
942	935	console_GROMs.buf = console_GROMs.data_ptr[console_GROMs.addr];
	936	//      printf("GROM address (cons) = %04x, offset = %04x, reply = %02x\n", console_GROMs.addr, offset, reply);
943	937	}
944	938
945		//  printf("GROM address = %04x, reply = %02x\n", console_GROMs.addr, reply>>8);
	939	/* The address pointer in the cartridge system is updated by this call.
	940	We pretend to do a data read, so we mask away the address bit in the
	941	offset. */
	942	replycart = ti99_cartridge_grom_r(cartslots, offset&0xfffc);
	943
	944	if (console_GROMs.addr >= 0x6000 || override_console)
	945	{
	946	reply = replycart;
	947	}
	948
	949	/* Each GROM chip has its own counter, so we update all of them even
	950	when we do not access them. */
946	951	/* The program counter wraps at each GROM chip size (8K),
947		so 0x5fff + 1 = 0x4000. */
	952	so 0x5fff + 1 = 0x4000. */
948	953	console_GROMs.addr = ((console_GROMs.addr + 1) & 0x1FFF) | (console_GROMs.addr & 0xE000);
949
	954
950	955	/* Reset the read and write address flipflops. */
951	956	console_GROMs.raddr_LSB = console_GROMs.waddr_LSB = FALSE;
952
	957
953	958	return reply;
954	959	}
955	960
r7613	r7614
958	963	*/
959	964	READ16_HANDLER ( ti99_grom_r )
960	965	{
961		UINT16 reply;
962
	966	UINT16 reply, replycart;
	967
963	968	cpu_adjust_icount(devtag_get_device(space->machine, "maincpu"),-4 /*20+3*/);      /* from 4 to 23? */
964		//  cpu_spinuntil_time(space->machine->firstcpu, ATTOTIME_IN_USEC(6));
965
	969	//  cpu_spinuntil_time(space->machine->firstcpu, ATTOTIME_IN_USEC(6));
	970
966	971	/* This implementation features a multislot cartridge system which
967		is based on multiple GROM base addresses. The standard base
968		is >9800 (slot 0). When we access the port >9804, we switch to
969		slot 1, >9808 is slot 2, ... >983C is slot 15. Although theoretically
970		we could address up to 256 banks, the TI operating system does not
971		check more than 16 banks.
972		Cartridges may also contain ROMs which need to be banked
973		simultaneously. We use the cartridge slot number to swap the ROM at
974		>6000, or RAM if available. I don't know whether this is the way
975		Texas Instruments envisaged it in the OS, but it is the only
976		plausible way to allow for GROM+ROM cartridges.
977		Note that some cartridges may have programming flaws which only
978		appear when the cartridge is used in a higher-numbered slot.
979		Parsec is one example which only runs in slot 0 as the
980		programmers hard-coded an access to GROM port 0. Note: This *may*
981		be worked around if we make sure that switching only occurs
982		when the address is set, not when data is read or written. But
983		it's not clear whether this has unwanted side effects.
984		*/
985
986		/* Activates a slot in the multi-cartridge extender. */
987		ti99_cartridge_slot_set(cartslots, (offset & 0x01fe)/2);
988
	972	is based on multiple GROM base addresses. The standard base
	973	is >9800 (slot 0). When we access the port >9804, we switch to
	974	slot 1, >9808 is slot 2, ... >983C is slot 15. Although theoretically
	975	we could address up to 256 banks, the TI operating system does not
	976	check more than 16 banks.
	977	Cartridges may also contain ROMs which need to be banked
	978	simultaneously. We use the cartridge slot number to swap the ROM at
	979	>6000, or RAM if available. I don't know whether this is the way
	980	Texas Instruments envisaged it in the OS, but it is the only
	981	plausible way to allow for GROM+ROM cartridges.
	982	Note that some cartridges may have programming flaws which only
	983	appear when the cartridge is used in a higher-numbered slot.
	984	Parsec is one example which only runs in slot 0 as the
	985	programmers hard-coded an access to GROM port 0. Note: This *may*
	986	be worked around if we make sure that switching only occurs
	987	when the address is set, not when data is read or written. But
	988	it's not clear whether this has unwanted side effects.
	989	*/
	990
989	991	if (offset & 1)
990	992	{   /* Read GROM address
991		We only have one GROM program counter for the console GROMs
992		and all cartridge GROMs in all banks(!). Hardware
993		implementations must take this into account as well. Thus,
994		we use a structure here in the console, rather than separate
995		counters in each GROM chip. */
	993	We only have one GROM program counter for the console GROMs
	994	and all cartridge GROMs in all banks(!). Hardware
	995	implementations must take this into account as well. Thus,
	996	we use a structure here in the console, rather than separate
	997	counters in each GROM chip. */
996	998
	999	/* We call the cartridge system here, but we ignore the
	1000	value. This is done to sync the flags. */
	1001	replycart = ti99_cartridge_grom_r(cartslots, (offset<<1))<<8;
	1002
997	1003	/* When reading, reset the hi/lo flag byte for writing.
998		TODO: Verify this with a real machine. */
	1004	TODO: Verify this with a real machine. */
999	1005	console_GROMs.waddr_LSB = FALSE;
1000
	1006
1001	1007	/* Address reading is done in two steps; first, the high byte
1002		is transferred, then the low byte. */
	1008	is transferred, then the low byte. */
1003	1009	if (console_GROMs.raddr_LSB)
1004	1010	{
1005	1011	/* second pass */
r7613	r7614
1012	1018	reply = console_GROMs.addr & 0xff00;
1013	1019	console_GROMs.raddr_LSB = TRUE;
1014	1020	}
	1021	/* GROM address values must be globally unique. */
	1022	assert (replycart == reply);
1015	1023	}
1016	1024	else
1017	1025	{
1018	1026	/* Read GROM data */
1019		reply = ((UINT16)GROM_dataread()) << 8;
	1027	/* Note that we shift the GROM port address to accomodate for
	1028	8-bit and 16-bit systems. */
	1029	reply = ((UINT16)GROM_dataread(offset<<1)) << 8;
1020	1030	}
1021
	1031
1022	1032	if (hsgpl_crdena)
1023	1033	/* hsgpl buffers are stronger than console GROM buffers */
1024	1034	reply = ti99_hsgpl_gpl_r(space, offset, mem_mask);
1025
	1035
1026	1036	return reply;
1027	1037	}
1028	1038
1029	1039	/*
1030		GPL write
	1040	GPL write
1031	1041	*/
1032	1042	WRITE16_HANDLER ( ti99_grom_w )
1033	1043	{
1034	1044	cpu_adjust_icount(devtag_get_device(space->machine, "maincpu"),-4/*20+3*/);      /* from 4 to 23? */
1035		//  cpu_spinuntil_time(space->machine->firstcpu, ATTOTIME_IN_USEC(6));
	1045	//  cpu_spinuntil_time(space->machine->firstcpu, ATTOTIME_IN_USEC(6));
	1046
	1047	if (offset & 1)
	1048	{
	1049	ti99_cartridge_grom_w(cartslots, (offset<<1), (data>>8)&0xff);
1036	1050
1037		/* Activates a slot in the multi-cartridge extender. */
1038		ti99_cartridge_slot_set(cartslots, (offset & 0x01fe)/2);
1039
1040		// 1001 1wbb bbbb bbr0
1041
1042		if (offset & 1)
1043		{   /* write GROM address */
	1051	/* write GROM address */
1044	1052	/* see comments above */
1045	1053	console_GROMs.raddr_LSB = FALSE;
1046
	1054
1047	1055	/* Implements the internal flipflop.
1048		The Editor/Assembler manuals says that the current address
1049		plus one is returned. This effect is properly emulated
1050		as we are using a read-ahead buffer.
1051		*/
	1056	The Editor/Assembler manuals says that the current address
	1057	plus one is returned. This effect is properly emulated
	1058	as we are using a read-ahead buffer.
	1059	*/
1052	1060	if (console_GROMs.waddr_LSB)
1053	1061	{
1054	1062	/* Accept low byte (2nd write) */
1055	1063	console_GROMs.addr = (console_GROMs.addr & 0xFF00) | ((data >> 8) & 0xFF);
1056
	1064
1057	1065	/* Setting the address causes a new read, putting the
1058		value into the buffer. We don't need the value here. */
1059		GROM_dataread();
	1066	value into the buffer. We don't need the value here. */
	1067	GROM_dataread(offset<<1);
1060	1068	console_GROMs.waddr_LSB = FALSE;
1061	1069	}
1062	1070	else
r7613	r7614
1065	1073	console_GROMs.addr = (data & 0xFF00) | (console_GROMs.addr & 0xFF);
1066	1074	console_GROMs.waddr_LSB = TRUE;
1067	1075	}
1068
1069	1076	}
1070	1077	else
1071	1078	{
1072	1079	/* write GROM data */
1073	1080	/* the console GROMs are always affected */
1074	1081	/* BTW, console GROMs are never GRAMs, therefore there is no
1075		need to actually write anything, so we just read ahead
1076		TODO: There could be cartridges with GRAM, so this must be
1077		fixed.
1078		*/
1079		GROM_dataread();
	1082	need to actually write anything, so we just read ahead
	1083	TODO: There could be cartridges with GRAM, so this must be
	1084	fixed.
	1085	*/
	1086	GROM_dataread(offset<<1);
1080	1087	console_GROMs.raddr_LSB = console_GROMs.waddr_LSB = FALSE;
1081	1088	}
1082
	1089
1083	1090	if (hsgpl_crdena)
1084	1091	ti99_hsgpl_gpl_w(space, offset, data, mem_mask);
1085	1092	}
r7613	r7614
1090	1097	*/
1091	1098	static READ8_HANDLER ( ti99_grom_r8 )
1092	1099	{
1093		UINT8 reply;
	1100	UINT8 reply, replycart;
1094	1101
1095	1102	cpu_adjust_icount(space->machine->firstcpu,-4);
1096	1103
1097		/* Activates a slot in the multi-cartridge extender. */
1098		// 1001 1wbb bbbb bbr0
1099		ti99_cartridge_slot_set(cartslots, (offset & 0x03fc)/4);
1100
1101	1104	if (offset & 2)
1102	1105	{
	1106	replycart = ti99_cartridge_grom_r(cartslots, offset);
1103	1107	console_GROMs.waddr_LSB = FALSE;
1104	1108
1105	1109	if (console_GROMs.raddr_LSB)
r7613	r7614
1112	1116	reply = (console_GROMs.addr>>8) & 0x00ff;
1113	1117	console_GROMs.raddr_LSB = TRUE;
1114	1118	}
	1119	/* GROM address values must be globally unique. */
	1120	assert (replycart == reply);
1115	1121	}
1116	1122	else
1117		reply = GROM_dataread();
	1123	reply = GROM_dataread(offset);
1118	1124
1119	1125	return reply;
1120	1126	}
r7613	r7614
1127	1133	{
1128	1134	cpu_adjust_icount(space->machine->firstcpu,-4/*20+3*/);      /* from 4 to 23? */
1129	1135
1130		/* Activates a slot in the multi-cartridge extender. */
1131		ti99_cartridge_slot_set(cartslots, (offset & 0x03fc)/4);
1132
1133	1136	if (offset & 2)
1134	1137	{
	1138	ti99_cartridge_grom_w(cartslots, offset, data);
1135	1139	console_GROMs.raddr_LSB = FALSE;
1136	1140	if (console_GROMs.waddr_LSB)
1137	1141	{
1138	1142	console_GROMs.addr = (console_GROMs.addr & 0xFF00) | (data & 0xFF);
1139	1143
1140		GROM_dataread();
	1144	GROM_dataread(offset);
1141	1145	console_GROMs.waddr_LSB = FALSE;
1142	1146	}
1143	1147	else
r7613	r7614
1149	1153	}
1150	1154	else
1151	1155	{
1152		GROM_dataread();
	1156	GROM_dataread(offset);
1153	1157	console_GROMs.raddr_LSB = console_GROMs.waddr_LSB = FALSE;
1154	1158	}
1155	1159	}
r7613	r7614
1161	1165	READ16_HANDLER ( ti99_4p_grom_r )
1162	1166	{
1163	1167	cpu_adjust_icount(devtag_get_device(space->machine, "maincpu"),-4);      /* HSGPL is located on 8-bit bus? */
1164		//  cpu_spinuntil_time(space->machine->firstcpu, ATTOTIME_IN_USEC(6));
1165
	1168	//  cpu_spinuntil_time(space->machine->firstcpu, ATTOTIME_IN_USEC(6));
	1169
1166	1170	return /*hsgpl_crdena ?*/ ti99_hsgpl_gpl_r(space, offset, mem_mask) /*: 0*/;
1167	1171	}
1168	1172
r7613	r7614
1172	1176	WRITE16_HANDLER ( ti99_4p_grom_w )
1173	1177	{
1174	1178	cpu_adjust_icount(devtag_get_device(space->machine, "maincpu"),-4);      /* HSGPL is located on 8-bit bus? */
1175		//  cpu_spinuntil_time(space->machine->firstcpu, ATTOTIME_IN_USEC(6));
1176
	1179	//  cpu_spinuntil_time(space->machine->firstcpu, ATTOTIME_IN_USEC(6));
	1180
1177	1181	/*if (hsgpl_crdena)*/
1178		ti99_hsgpl_gpl_w(space, offset, data, mem_mask);
	1182	ti99_hsgpl_gpl_w(space, offset, data, mem_mask);
1179	1183	}
1180	1184
1181	1185
r7613	r7614
1190	1194	int page = offset >> 12;
1191	1195	UINT32 mapper_reg;
1192	1196	UINT8 reply = 0;
1193
	1197
1194	1198	if (ti99_8_enable_rom_and_ports)
1195	1199	{
1196	1200	/* This is only important for address access 0000-1fff and
1197		8000-9fff. Outside, the mapper mode is used. */
	1201	8000-9fff. Outside, the mapper mode is used. */
1198	1202	if ((offset >= 0x0000) && (offset < 0x2000))
1199	1203	{
1200	1204	/* ROM */
r7613	r7614
1211	1215	/* RAM: >8000 - >83ff */
1212	1216	reply = sRAM_ptr_8[offset & 0x1fff];
1213	1217	break;
1214
	1218
1215	1219	case 1:
1216	1220	/* >8400 - >840f: sound (cannot read)
1217		>8410 - >87ff: SRAM */
	1221	>8410 - >87ff: SRAM */
1218	1222	if (offset >= 0x8410)
1219	1223	reply = sRAM_ptr_8[offset & 0x1fff];
1220	1224	break;
1221
	1225
1222	1226	case 2:
1223	1227	/* VDP read + mapper status */
1224	1228	if (offset < 0x8810)
r7613	r7614
1227	1231	{
1228	1232	if (offset & 2)
1229	1233	/* read VDP status >8802 */
1230		reply = TMS9928A_register_r(space, 0);
	1234	reply = TMS9928A_register_r(space, 0);
1231	1235	else
1232	1236	/* read VDP RAM >8800 */
1233		reply = TMS9928A_vram_r(space, 0);
	1237	reply = TMS9928A_vram_r(space, 0);
1234	1238	}
1235	1239	}
1236	1240	else
r7613	r7614
1240	1244	ti99_8_mapper_status = 0;
1241	1245	}
1242	1246	break;
1243
	1247
1244	1248	case 4:
1245	1249	/* speech read: >9000 */
1246	1250	if (! (offset & 1))
r7613	r7614
1249	1253	reply = tms5220_status_r(devtag_get_device(space->machine, "tms5220"), 0);
1250	1254	}
1251	1255	break;
1252
	1256
1253	1257	case 6:
1254	1258	/* GROM read: >9800 */
1255	1259	if (! (offset & 1))
1256	1260	reply = ti99_grom_r8(space, offset);
1257	1261	break;
1258
	1262
1259	1263	default:
1260	1264	logerror("unmapped read offs=%d\n", (int) offset);
1261	1265	break;
r7613	r7614
1263	1267	return reply;
1264	1268	}
1265	1269	}
1266
	1270
1267	1271	mapper_reg = ti99_8_mapper_regs[page];
1268	1272	offset = (mapper_reg + (offset & 0x0fff)) & 0x00ffffff;
1269
1270		#if 0
	1273
	1274	#if 0
1271	1275	/* test read protect */
1272	1276	if (mapper_reg & 0x20000000)
1273	1277	;
1274
	1278
1275	1279	/* test execute protect */
1276	1280	if (mapper_reg & 0x40000000)
1277	1281	;
1278		#endif
1279
	1282	#endif
	1283
1280	1284	if (offset < 0x010000)
1281		/* Read RAM */
1282		reply = xRAM_ptr_8[offset];
1283
	1285	/* Read RAM */
	1286	reply = xRAM_ptr_8[offset];
	1287
1284	1288	if (offset >= 0xff0000)
1285	1289	{
1286	1290	switch ((offset >> 13) & 7)
r7613	r7614
1297	1301	/* ffe000 - ffffff: ? */
1298	1302	logerror("unmapped read page=%d offs=%d\n", (int) page, (int) offset);
1299	1303	break;
1300
	1304
1301	1305	case 2:
1302	1306	/* ff4000 - ff5fff: DSR space */
1303	1307	reply = ti99_8_peb_r(space, offset & 0x1fff);
1304	1308	break;
1305
	1309
1306	1310	case 3:
1307	1311	/* ff6000 - ff7fff: cartridge ROM space */
1308	1312	offset &= 0x1fff;
1309
	1313
1310	1314	/* We do not support hsgpl here because it is a 16 bit
1311		system. Just check the cartridges.  */
	1315	system. Just check the cartridges.  */
1312	1316	reply = ti99_multicart8_r(multicart8, offset);
1313	1317	break;
1314
	1318
1315	1319	case 5:
1316	1320	/* ffa000 - ffbfff: >2000 ROM (ROM1) */
1317	1321	reply = ROM1_ptr_8[offset & 0x1fff];
1318	1322	break;
1319
	1323
1320	1324	case 6:
1321	1325	/* ffc000 - ffdfff: >6000 ROM */
1322	1326	reply = ROM3_ptr_8[offset & 0x1fff];
1323	1327	break;
1324	1328	}
1325	1329	}
1326
	1330
1327	1331	return reply;
1328	1332	}
1329	1333
r7613	r7614
1407	1411	if (! (offset & 1))
1408	1412	{
1409	1413	cpu_adjust_icount(devtag_get_device(space->machine, "maincpu"),-48*4);      /* this is just an approx. minimum, it can be much more */
1410
	1414
1411	1415	/* the stupid design of the tms5220 core means that ready is cleared when
1412		there are 15 bytes in FIFO.  It should be 16.  Of course, if it were the
1413		case, we would need to store the value on the bus, which would be more
1414		complex. */
	1416	there are 15 bytes in FIFO.  It should be 16.  Of course, if it were the
	1417	case, we would need to store the value on the bus, which would be more
	1418	complex. */
1415	1419	if (! tms5220_readyq_r(devtag_get_device(space->machine, "tms5220")))
1416	1420	{
1417	1421	attotime time_to_ready = double_to_attotime(tms5220_time_to_ready(devtag_get_device(space->machine, "tms5220")));
1418	1422	double d = cputag_attotime_to_clocks(space->machine, "maincpu", time_to_ready);
1419	1423	int cycles_to_ready = ((int) (d + 3)) & ~3;
1420
	1424
1421	1425	logerror("time to ready: %f -> %d\n", attotime_to_double(time_to_ready)
1422	1426	, (int) cycles_to_ready);
1423
	1427
1424	1428	cpu_adjust_icount(devtag_get_device(space->machine, "maincpu"),-cycles_to_ready);
1425	1429	timer_set(space->machine, attotime_zero, NULL, 0, /*speech_kludge_callback*/NULL);
1426	1430	}
1427
	1431
1428	1432	tms5220_data_w(devtag_get_device(space->machine, "tms5220"), offset, data);
1429	1433	}
1430	1434	break;
1431
	1435
1432	1436	case 7:
1433	1437	/* GPL write */
1434	1438	if (! (offset & 1))
1435	1439	ti99_grom_w8(space, offset, data);
1436	1440	break;
1437
	1441
1438	1442	default:
1439	1443	logerror("unmapped write offs=%d data=%d\n", (int) offset, (int) data);
1440	1444	break;
r7613	r7614
1552	1556	if (handset_buflen == 1)
1553	1557	{
1554	1558	/* Unless I am missing something, the third and last nybble of the
1555		message is not acknowledged by the DSR in any way, and the first nybble
1556		of next message is not requested for either, so we need to decide on
1557		our own when we can post a new event.  Currently, we wait for 1000us
1558		after the DSR acknowledges the second nybble. */
	1559	message is not acknowledged by the DSR in any way, and the first nybble
	1560	of next message is not requested for either, so we need to decide on
	1561	our own when we can post a new event.  Currently, we wait for 1000us
	1562	after the DSR acknowledges the second nybble. */
1559	1563	timer_set(machine, ATTOTIME_IN_USEC(1000), NULL, 0, ti99_handset_ack_callback);
1560	1564	}
1561	1565
r7613	r7614
1618	1622
1619	1623	/* read current key state */
1620	1624	key_buf = ( input_port_read(machine, keynames[num]) | (input_port_read(machine, keynames[num + 1]) << 16) ) >> (4*num);
1621
	1625
1622	1626	/* If a key was previously pressed, this key was not shift, and this key is
1623		still down, then don't change the current key press. */
	1627	still down, then don't change the current key press. */
1624	1628	if (previous_key[num] && (previous_key[num] != 0x24)
1625		&& (key_buf & (1 << (previous_key[num] & 0x1f))))
	1629	&& (key_buf & (1 << (previous_key[num] & 0x1f))))
1626	1630	{
1627	1631	/* check the shift modifier state */
1628	1632	if (((previous_key[num] & 0x20) != 0) == ((key_buf & 0x0008) != 0))
1629	1633	/* the shift modifier state has not changed */
1630		return FALSE;
	1634	return FALSE;
1631	1635	else
1632	1636	{
1633	1637	/* the shift modifier state has changed: we need to update the
1634		keyboard state */
	1638	keyboard state */
1635	1639	if (key_buf & 0x0008)
1636	1640	{   /* shift has been pressed down */
1637	1641	previous_key[num] = current_key = previous_key[num] | 0x20;
r7613	r7614
1642	1646	}
1643	1647	/* post message */
1644	1648	ti99_handset_post_message(machine, (((unsigned) current_key) << 4) | (num << 1));
1645
	1649
1646	1650	return TRUE;
1647	1651	}
1648
	1652
1649	1653	}
1650
	1654
1651	1655	current_key = 0;   /* default value if no key is down */
1652	1656	for (i=0; i<20; i++)
1653	1657	{
r7613	r7614
1659	1663
1660	1664	if (current_key != 0x24)
1661	1665	/* If this is the shift key, any other key we may find will
1662		have higher priority; otherwise, we may exit the loop and keep
1663		the key we have just found. */
	1666	have higher priority; otherwise, we may exit the loop and keep
	1667	the key we have just found. */
1664	1668	break;
1665	1669	}
1666	1670	}
1667
	1671
1668	1672	if (current_key != previous_key[num])
1669	1673	{
1670	1674	previous_key[num] = current_key;
r7613	r7614
1717	1721
1718	1722	/* set sign */
1719	1723	/* note that we set the sign if the joystick position is 0 to work
1720		around a bug in the ti99/4 ROMs */
	1724	around a bug in the ti99/4 ROMs */
1721	1725	if (current_joy_x <= 0)
1722	1726	{
1723	1727	message |= 0x040;
r7613	r7614
1796	1800	static void mecmouse_select(int selnow, int stick1, int stick2)
1797	1801	{
1798	1802	/* The Mechatronic mouse is connected to the joystick port and occupies
1799		both joystick select lines and the switch lines. From these five
1800		lines, left/right/down are used for the motion (i.e. 3 motion steps
1801		for positive and four for negative motion and one for rest),
1802		the fire line is used for the secondary mouse button, and the up
1803		line is used for the primary button.
1804		The mouse motion is delivered by the same lines for both directions;
1805		this requires swapping the axes. According to the source code of
1806		the accompanying mouse driver, the readout of the current axis is
1807		done by selecting joystick 1, then joystick 2. The axis swapping is
1808		achieved by selecting stick 1 again. When selecting stick 2, the
1809		second axis is seen on the input lines.
1810		Interrupting this sequence will lead to swapped axes. This is
1811		prevented by resetting the toggle when the mouse is deselected
1812		(neither 1 nor 2 are selected).
	1803	both joystick select lines and the switch lines. From these five
	1804	lines, left/right/down are used for the motion (i.e. 3 motion steps
	1805	for positive and four for negative motion and one for rest),
	1806	the fire line is used for the secondary mouse button, and the up
	1807	line is used for the primary button.
	1808	The mouse motion is delivered by the same lines for both directions;
	1809	this requires swapping the axes. According to the source code of
	1810	the accompanying mouse driver, the readout of the current axis is
	1811	done by selecting joystick 1, then joystick 2. The axis swapping is
	1812	achieved by selecting stick 1 again. When selecting stick 2, the
	1813	second axis is seen on the input lines.
	1814	Interrupting this sequence will lead to swapped axes. This is
	1815	prevented by resetting the toggle when the mouse is deselected
	1816	(neither 1 nor 2 are selected).
	1817
	1818	The joystick lines are selected as follows:
	1819	TI-99/4:  Stick 1: P4=1, P3=0, P2=1 (5)
	1820	Stick 2: P4=1, P3=1, P2=0 (6)
	1821
	1822	TI-99/4A: Stick 1: P4=1, P3=1, P2=0 (6)
	1823	Stick 2: P4=1, P3=1, P2=1 (7)
	1824
	1825	TI-99/8:  Stick 1: P3=1, P2=1, P1=1, P0=0 (14)
	1826	Stick 2: P3=1, P2=1, P1=1, P0=1 (15)
	1827
	1828	Geneve: n/a, has own mouse handling via v9938
	1829
	1830	As we can only deliver at max 3 steps positive and 4 steps negative,
	1831	we split the delta so that subsequent queries add up to the actual
	1832	delta. That is, one delta of +10 yields a 3+3+3+1.
	1833
	1834	mecmouse_x holds the current delta to be counted down for x
	1835	(y accordingly)
	1836
	1837	mecmouse_x_buf is the current step count reported to CRU
	1838
	1839	Michael Zapf, 2008-01-22
	1840	*/
1813	1841
1814		The joystick lines are selected as follows:
1815		TI-99/4:  Stick 1: P4=1, P3=0, P2=1 (5)
1816		Stick 2: P4=1, P3=1, P2=0 (6)
1817
1818		TI-99/4A: Stick 1: P4=1, P3=1, P2=0 (6)
1819		Stick 2: P4=1, P3=1, P2=1 (7)
1820
1821		TI-99/8:  Stick 1: P3=1, P2=1, P1=1, P0=0 (14)
1822		Stick 2: P3=1, P2=1, P1=1, P0=1 (15)
1823
1824		Geneve: n/a, has own mouse handling via v9938
1825
1826		As we can only deliver at max 3 steps positive and 4 steps negative,
1827		we split the delta so that subsequent queries add up to the actual
1828		delta. That is, one delta of +10 yields a 3+3+3+1.
1829
1830		mecmouse_x holds the current delta to be counted down for x
1831		(y accordingly)
1832
1833		mecmouse_x_buf is the current step count reported to CRU
1834
1835		Michael Zapf, 2008-01-22
1836		*/
1837
1838	1842	if (selnow==stick2) {
1839	1843	if (mecmouse_sel==stick1) {
1840	1844	if (! mecmouse_read_y)
r7613	r7614
1997	2001	if (intreq)
1998	2002	{
1999	2003	/* On TI99, TMS9900 IC0-3 lines are not connected to TMS9901,
2000		* but hard-wired to force level 1 interrupts */
	2004	* but hard-wired to force level 1 interrupts */
2001	2005	cputag_set_input_line_and_vector(device->machine, "maincpu", 0, ASSERT_LINE, 1);   /* interrupt it, baby */
2002	2006	}
2003	2007	else
r7613	r7614
2546	2550	}
2547	2551
2548	2552	/* write CRU bit:
2549		bit0: enable/disable mapper registers in DSR space,
2550		bit1: enable/disable address mapping */
	2553	bit0: enable/disable mapper registers in DSR space,
	2554	bit1: enable/disable address mapping */
2551	2555	static void sAMS_cru_w(running_machine *machine, int offset, int data)
2552	2556	{
2553	2557	if (offset == 1)
r7613	r7614
2570	2574	static READ16_HANDLER ( ti99_sAMSxramlow_r )
2571	2575	{
2572	2576	cpu_adjust_icount(devtag_get_device(space->machine, "maincpu"),-4);
2573		//  cpu_spinuntil_time(space->machine->firstcpu, ATTOTIME_IN_USEC(6));
2574
	2577	//  cpu_spinuntil_time(space->machine->firstcpu, ATTOTIME_IN_USEC(6));
	2578
2575	2579	if (sAMS_mapper_on)
2576	2580	return xRAM_ptr[(offset&0x7ff)+sAMSlookup[(0x1000+offset)>>11]];
2577	2581	else
r7613	r7614
2648	2652	/* Not required at run-time */
2649	2653	#if 0
2650	2654	memory_install_read16_handler(space, 0x2000, 0x2fff, SMH_BANK(3));
2651		memory_install_write16_handler(space, 0x2000, 0x2fff, SMH_BANK(3));
2652		memory_install_read16_handler(space, 0x3000, 0x3fff, SMH_BANK(4));
2653		memory_install_write16_handler(space, 0x3000, 0x3fff, SMH_BANK(4));
2654		memory_install_read16_handler(space, 0xa000, 0xafff, SMH_BANK(5));
2655		memory_install_write16_handler(space, 0xa000, 0xafff, SMH_BANK(5));
2656		memory_install_read16_handler(space, 0xb000, 0xbfff, SMH_BANK(6));
2657		memory_install_write16_handler(space, 0xb000, 0xbfff, SMH_BANK(6));
2658		memory_install_read16_handler(space, 0xc000, 0xcfff, SMH_BANK(7));
2659		memory_install_write16_handler(space, 0xc000, 0xcfff, SMH_BANK(7));
2660		memory_install_read16_handler(space, 0xd000, 0xdfff, SMH_BANK(8));
2661		memory_install_write16_handler(space, 0xd000, 0xdfff, SMH_BANK(8));
2662		memory_install_read16_handler(space, 0xe000, 0xefff, SMH_BANK(9));
2663		memory_install_write16_handler(space, 0xe000, 0xefff, SMH_BANK(9));
2664		memory_install_read16_handler(space, 0xf000, 0xffff, SMH_BANK(10));
2665		memory_install_write16_handler(space, 0xf000, 0xffff, SMH_BANK(10));
	2655	memory_install_write16_handler(space, 0x2000, 0x2fff, SMH_BANK(3));
	2656	memory_install_read16_handler(space, 0x3000, 0x3fff, SMH_BANK(4));
	2657	memory_install_write16_handler(space, 0x3000, 0x3fff, SMH_BANK(4));
	2658	memory_install_read16_handler(space, 0xa000, 0xafff, SMH_BANK(5));
	2659	memory_install_write16_handler(space, 0xa000, 0xafff, SMH_BANK(5));
	2660	memory_install_read16_handler(space, 0xb000, 0xbfff, SMH_BANK(6));
	2661	memory_install_write16_handler(space, 0xb000, 0xbfff, SMH_BANK(6));
	2662	memory_install_read16_handler(space, 0xc000, 0xcfff, SMH_BANK(7));
	2663	memory_install_write16_handler(space, 0xc000, 0xcfff, SMH_BANK(7));
	2664	memory_install_read16_handler(space, 0xd000, 0xdfff, SMH_BANK(8));
	2665	memory_install_write16_handler(space, 0xd000, 0xdfff, SMH_BANK(8));
	2666	memory_install_read16_handler(space, 0xe000, 0xefff, SMH_BANK(9));
	2667	memory_install_write16_handler(space, 0xe000, 0xefff, SMH_BANK(9));
	2668	memory_install_read16_handler(space, 0xf000, 0xffff, SMH_BANK(10));
	2669	memory_install_write16_handler(space, 0xf000, 0xffff, SMH_BANK(10));
2666	2670	#endif
2667	2671
2668	2672	ti99_peb_set_16bit_card_handlers(0x1e00, & ti99_4p_mapper_handlers);

src/mess/machine/ti99_4x.h

r7613	r7614
107	107	#endif
108	108	} fdc_kind_t;
109	109
	110	/* GROM_port_t: descriptor for a port of 8 GROMs. Required by ti99_4x, ti99pcod */
	111	struct _GROM_port_t
	112	{
	113	/* pointer to GROM data */
	114	UINT8 *data_ptr;
	115	/* current address pointer for the active GROM in port (16 bits) */
	116	unsigned int addr;
	117	/* GROM data buffer */
	118	UINT8 buf;
	119	/* internal flip-flops that are set after the first access to the GROM
	120	address so that next access is mapped to the LSB, and cleared after each
	121	data access */
	122	char raddr_LSB, waddr_LSB;
	123	};
	124	typedef struct _GROM_port_t GROM_port_t;
	125
	126
110	127	/* defines for input port "CFG" */
111	128	enum
112	129	{

docs/messnew.txt

r7613	r7614
19	19	- Scientific Atlanta PowerVu pv9234 STB
20	20	- Dream Multimedia Dreambox 7000/5620/500
21	21
	22
	23
22	24	System Driver Changes:
23	25	----------------------
24	26
r7613	r7614
28	30
29	31	- [TANDY2K] Implemented DMA mux register. [Curt Coder]
30	32
	33	- [TI99] Cleanups.  [Michael Zapf]
	34
31	35	- [VICTOR9K] Connected MC6852 device. [Curt Coder]
32	36
33	37

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