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r757 Sunday 29th July, 2007 at 18:00:44 UTC by Wilbert Pol
[3DO] Added some more small bits and pieces.

[src/mess/drivers]	3do.c
[src/mess/includes]	3do.h
[src/mess/machine]	3do.c

src/mess/includes/3do.h

r756	r757
4	4	READ32_HANDLER( nvarea_r );
5	5	WRITE32_HANDLER( nvarea_w );
6	6
	7	READ32_HANDLER( unk_318_r );
	8	WRITE32_HANDLER( unk_318_w );
	9
7	10	READ32_HANDLER( vram_sport_r );
8	11	WRITE32_HANDLER( vram_sport_w );
9	12
10	13	READ32_HANDLER( madam_r );
11	14	WRITE32_HANDLER( madam_w );
	15	void madam_init( void );
12	16
13	17	READ32_HANDLER( clio_r );
14	18	WRITE32_HANDLER( clio_w );
	19	void clio_init( void );
15	20
16	21	#endif /* REAL_3DO_H */

src/mess/machine/3do.c

r756	r757
2	2	#include "driver.h"
3	3	#include "includes/3do.h"
4	4
	5	typedef struct {
	6	UINT32   revision;
	7	UINT32   memory_configuration;
	8	} MADAM;
	9
	10	typedef struct {
	11	UINT32   dummy;
	12	} CLIO;
	13
	14	static UINT32   unk_318_data_0 = 0;
	15	static MADAM   madam;
	16	static CLIO      clio;
	17
	18
5	19	READ32_HANDLER( nvarea_r ) {
6		logerror( "%08X: NVRAM read offset = %08X, mask = %08X\n", activecpu_get_pc(), offset, mem_mask );
	20	logerror( "%08X: NVRAM read offset = %08X\n", activecpu_get_pc(), offset );
7	21	return 0;
8	22	}
9	23
r756	r757
11	25	logerror( "%08X: NVRAM write offset = %08X, data = %08X, mask = %08X\n", activecpu_get_pc(), offset, data, mem_mask );
12	26	}
13	27
	28
	29
	30	/*
	31	I have no idea what piece of hardware this is. Possibly some kind of communication hardware.
	32
	33	During booting the following things get written/read:
	34	write 03180000 to 03180000
	35	4 read actions from 03180000, if lower bit is 1 0 1 0 then
	36	write 02000000 to 03180000
	37	write 04000000 to 03180000
	38	write 08000000 to 03180000
	39	write 10000000 to 03180000
	40	write 20000000 to 03180000
	41	write 40000000 to 03180000
	42	write 80000000 to 03180000
	43	write 00000001 to 03180000
	44	write 00000002 to 03180000
	45	write 00000004 to 03180000
	46	write 00000008 to 03180000
	47	write 00000010 to 03180000
	48	write 00000020 to 03180000
	49	write 00000040 to 03180000
	50	write 00000080 to 03180000
	51	write 00000100 to 03180000
	52	read from 03180000
	53	write 04000000 to 03180000
	54	write 08000000 to 03180000
	55	write 10000000 to 03180000
	56	write 20000000 to 03180000
	57	write 40000000 to 03180000
	58	write 80000000 to 03180000
	59	write 00000001 to 03180000
	60	write 00000002 to 03180000
	61	write 00000004 to 03180000
	62	write 00000008 to 03180000
	63	write 00000010 to 03180000
	64	write 00000020 to 03180000
	65	write 00000040 to 03180000
	66	write 00000080 to 03180000
	67	write 00000100 to 03180000
	68	write 00002000 to 03180000
	69	several groups of 16 write actions or 16 read actions
	70	*/
	71	READ32_HANDLER( unk_318_r ) {
	72	logerror( "%08X: UNK_318 read offset = %08X\n", activecpu_get_pc(), offset );
	73	switch( offset ) {
	74	case 0:      /* Boot ROM checks here and expects to read 1, 0, 1, 0 in the lowest bit */
	75	unk_318_data_0 ^= 1;
	76	return unk_318_data_0;
	77	}
	78	return 0;
	79	}
	80
	81	WRITE32_HANDLER( unk_318_w ) {
	82	logerror( "%08X: UNK_318 write offset = %08X, data = %08X, mask = %08X\n", activecpu_get_pc(), offset, data, mem_mask );
	83	switch( offset ) {
	84	case 0:      /* Boot ROM writes 03180000 here and then starts reading some things */
	85	break;
	86	}
	87	}
	88
	89
	90
14	91	READ32_HANDLER( vram_sport_r ) {
15		logerror( "%08X: VRAM SPORT read offset = %08X, mask = %08X\n", activecpu_get_pc(), offset, mem_mask );
	92	logerror( "%08X: VRAM SPORT read offset = %08X\n", activecpu_get_pc(), offset );
	93	switch( offset ) {
	94	case 0x1840:   /* 03206100 - ?? */
	95	break;
	96	case 0x1A40:   /* 03206900 - ?? */
	97	break;
	98	}
16	99	return 0;
17	100	}
18	101
19	102	WRITE32_HANDLER( vram_sport_w ) {
20	103	logerror( "%08X: VRAM SPORT write offset = %08X, data = %08X, mask = %08X\n", activecpu_get_pc(), offset, data, mem_mask );
	104	switch( offset ) {
	105	case 0x0800:   /* 03202000 - ?? during boot 00190019 gets written */
	106	break;
	107	case 0x1180:   /* 03204600-0320472c - ?? during boot FFFFFFFF gets written to this block */
	108	break;
	109	}
21	110	}
22	111
	112
	113
23	114	READ32_HANDLER( madam_r ) {
24		logerror( "%08X: MADAM read offset = %08X, mask = %08X\n", activecpu_get_pc(), offset, mem_mask );
	115	logerror( "%08X: MADAM read offset = %08X\n", activecpu_get_pc(), offset );
	116	switch( offset ) {
	117	case 0:      /* 03300000 - Revision */
	118	return madam.revision;
	119	case 1:      /* 03300004 - Memory configuration */
	120	return madam.memory_configuration;
	121	}
25	122	return 0;
26	123	}
27	124
28	125	WRITE32_HANDLER( madam_w ) {
29	126	logerror( "%08X: MADAM write offset = %08X, data = %08X, mask = %08X\n", activecpu_get_pc(), offset, data, mem_mask );
	127	switch( offset ) {
	128	case 0x01:   /* 03300004 - Memory configuration 29 = 2MB DRAM, 1MB VRAM */
	129	madam.memory_configuration = data;
	130	break;
	131	case 0x03:   /* 0330000C - ?? during boot first value written is 00178906 */
	132	break;
	133	case 0x08:   /* 03300020 - ?? during boot 00000000 is written here */
	134	break;
	135	}
30	136	}
31	137
	138	void madam_init( void ) {
	139	memset( &madam, 0, sizeof(MADAM) );
	140	madam.revision = 0x00000001;
	141	}
	142
	143
32	144	READ32_HANDLER( clio_r ) {
33		logerror( "%08X: CLIO read offset = %08X, mask = %08X\n", activecpu_get_pc(), offset, mem_mask );
	145	logerror( "%08X: CLIO read offset = %08X\n", activecpu_get_pc(), offset );
34	146	return 0;
35	147	}
36	148
37	149	WRITE32_HANDLER( clio_w ) {
38	150	logerror( "%08X: CLIO write offset = %08X, data = %08X, mask = %08X\n", activecpu_get_pc(), offset, data, mem_mask );
	151	switch( offset ) {
	152	case 0x0A:   /* 03400028 - bits 0,1, and 6 are tested (irq sources?) */
	153	break;
	154	case 0x0B:   /* 0340002C - ?? during boot 0000000B is written here counter reload related?? */
	155	break;
	156	}
39	157	}
40	158
	159	void clio_init( void ) {
	160	memset( &clio, 0, sizeof(CLIO) );
	161	}
	162

src/mess/drivers/3do.c

r756	r757
114	114	AM_RANGE(0x00200000, 0x002FFFFF) AM_RAM   AM_BASE(&vram)                     /* VRAM */
115	115	AM_RANGE(0x03000000, 0x030FFFFF) AM_ROMBANK(1)                           /* BIOS */
116	116	AM_RANGE(0x03140000, 0x0315FFFF) AM_READWRITE(nvarea_r, nvarea_w)            /* NVRAM */
117		//   AM_RANGE(0x03180000, 0x031FFFFF) AM_NOP                                 /* ???? */
	117	AM_RANGE(0x03180000, 0x031FFFFF) AM_READWRITE(unk_318_r, unk_318_w)            /* ???? */
118	118	AM_RANGE(0x03200000, 0x032FFFFF) AM_READWRITE(vram_sport_r, vram_sport_w)      /* special vram access1 */
119	119	AM_RANGE(0x03300000, 0x033FFFFF) AM_READWRITE(madam_r, madam_w)               /* address decoder */
120	120	AM_RANGE(0x03400000, 0x034FFFFF) AM_READWRITE(clio_r, clio_w)               /* io controller */
r756	r757
127	127	memory_set_bankptr( 1, memory_region( REGION_USER1 ) );
128	128	/* Copy BIOS ROM data to DRAM */
129	129	memcpy( dram, memory_region( REGION_USER1 ), memory_region_length( REGION_USER1 ) );
	130	madam_init();
	131	clio_init();
130	132	}
131	133
132	134	static MACHINE_DRIVER_START( 3do )

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