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r7192 Thursday 28th January, 2010 at 22:02:23 UTC by Phill Harvey-Smith
Minor SCSIBUS changes. Main CPU to IO CPU communication now working, config rom will read. Added support for multiple bioses (1.31a, 1.32f, 1.40d). 1.40d has some issues as the hardware is slightly different.

[src/mess/drivers]	rmnimbus.c
[src/mess/includes]	rmnimbus.h
[src/mess/machine]	er59256.c er59256.h rmnimbus.c scsibus.c

src/mess/includes/rmnimbus.h

r7191	r7192
61	61
62	62	/* External int vectors for chained interupts */
63	63	#define EXTERNAL_INT_DISK       0x80
64		#define EXTERNAL_INT_PC8031     0x8c
	64	#define EXTERNAL_INT_PC8031_8C  0x8c
	65	#define EXTERNAL_INT_PC8031_8E  0x8E
	66	#define EXTERNAL_INT_PC8031_8F  0x8F
65	67	#define EXTERNAL_INT_Z80SIO     0x9C
66	68	#define EXTERNAL_INT_MSM5205    0x84
67	69
r7191	r7192
145	147
146	148	/* 8031/8051 Peripheral controler */
147	149
148		#define PC8031_RAMSIZE          0X004
	150	#define IPC_OUT_ADDR        0X01
	151	#define IPC_OUT_READ_PEND   0X02
	152	#define IPC_OUT_BYTE_AVAIL  0X04
149	153
	154	#define IPC_IN_ADDR         0X01
	155	#define IPC_IN_BYTE_AVAIL   0X02
	156	#define IPC_IN_READ_PEND    0X04
	157
150	158	READ8_HANDLER( pc8031_r );
151	159	WRITE8_HANDLER( pc8031_w );
152	160

src/mess/machine/scsibus.c

r7191	r7192
13	13
14	14	/* LOGLEVEL 0=no logging, 1=just commands and data, 2=everything ! */
15	15
16		#define LOGLEVEL         1
	16	#define LOGLEVEL         0
17	17
18	18	#define LOG(level,...)      if(LOGLEVEL>=level) logerror(__VA_ARGS__)
19	19
r7191	r7192
73	73	{
74	74	bus->data_last = (bus->bytes_left >= DATA_BUF_SIZE) ? DATA_BUF_SIZE : bus->bytes_left;
75	75
76		logerror("SCSIBUS:scsibus_read_data bus->bytes_left=%04X, bus->data_last=%04X, bus->xfer_count=%04X\n",bus->bytes_left,bus->data_last,bus->xfer_count);
	76	LOG(1,"SCSIBUS:scsibus_read_data bus->bytes_left=%04X, bus->data_last=%04X, bus->xfer_count=%04X\n",bus->bytes_left,bus->data_last,bus->xfer_count);
77	77
78	78	if (bus->data_last > 0)
79	79	{
r7191	r7192
106	106	case SCSI_PHASE_DATAIN :
107	107	result=bus->data[bus->data_idx++];
108	108
109		if (bus->command[0]==0x37) logerror("SCSIBUS:scsi_data_r: data_idx=%04X, bytes_left=%04X, data_last=%04X\n",bus->data_idx,bus->bytes_left,bus->data_last);
110	109	// check to see if we have reached the end of the block buffer
111	110	// and that there is more data to read from the scsi disk
112	111	if((bus->data_idx==DATA_BUF_SIZE) && (bus->bytes_left>0) && IS_READ_COMMAND())
r7191	r7192
265	264	int         command_local = 0;
266	265	int         newphase;
267	266
268		dump_command_bytes(bus);
	267	if(LOGLEVEL)
	268	dump_command_bytes(bus);
	269
269	270	bus->is_linked=bus->command[bus->cmd_idx-1] & 0x01;
270	271
271	272	// Check for locally executed commands, and if found execute them
r7191	r7192
273	274	{
274	275	// Format unit
275	276	case SCSI_CMD_FORMAT_UNIT :
276		logerror("SCSIBUS: format unit bus->command[1]=%02X & 0x10\n",(bus->command[1] & 0x10));
	277	LOG(1,"SCSIBUS: format unit bus->command[1]=%02X & 0x10\n",(bus->command[1] & 0x10));
277	278	command_local=1;
278	279	if((bus->command[1] & 0x10)==0x10)
279	280	SCSISetPhase(bus->devices[bus->last_id],SCSI_PHASE_DATAOUT);
r7191	r7192
286	287	break;
287	288
288	289	case SCSI_CMD_READ_DEFECT :
289		logerror("SCSIBUS: read defect list\n");
	290	LOG(1,"SCSIBUS: read defect list\n");
290	291	command_local=1;
291	292
292	293	bus->data[0] = 0x00;
r7191	r7192
302	303
303	304	// write buffer
304	305	case SCSI_CMD_BUFFER_WRITE :
305		logerror("SCSIBUS: write_buffer\n");
	306	LOG(1,"SCSIBUS: write_buffer\n");
306	307	command_local=1;
307	308	bus->xfer_count=(bus->command[7]<<8)+bus->command[8];
308	309	bus->data_last=bus->xfer_count;
r7191	r7192
312	313
313	314	// read buffer
314	315	case SCSI_CMD_BUFFER_READ   :
315		logerror("SCSIBUS: read_buffer\n");
	316	LOG(1,"SCSIBUS: read_buffer\n");
316	317	command_local=1;
317	318	bus->xfer_count=(bus->command[7]<<8)+bus->command[8];
318	319	bus->data_last=bus->xfer_count;
r7191	r7192
641	642	// try to open the devices
642	643	for (devno = 0; devno < scsidevs->devs_present; devno++)
643	644	{
644		logerror("init_scsibus devno=%d \n",devno);
	645	LOG(1,"init_scsibus devno=%d \n",devno);
645	646	SCSIAllocInstance( device->machine, scsidevs->devices[devno].scsiClass, &bus->devices[scsidevs->devices[devno].scsiID], scsidevs->devices[devno].diskregion );
646	647	}
647	648

src/mess/machine/er59256.c

r7191	r7192
12	12
13	13	/* LOGLEVEL 0=no logging, 1=just commands and data, 2=everything ! */
14	14
15		#define LOGLEVEL         1
	15	#define LOGLEVEL         0
16	16
17	17	#define LOG(level,...)      if(LOGLEVEL>=level) logerror(__VA_ARGS__)
18	18	#define LOG_BITS(bits)      logerror("CS=%d CK=%d DI=%d DO=%d", (bits&CS_MASK) ? 1 : 0, (bits&CK_MASK) ? 1 : 0, (bits&DI_MASK) ? 1 : 0, (bits&DO_MASK) ? 1 : 0)
r7191	r7192
69	69	IMPLEMENTATION
70	70	***************************************************************************/
71	71
	72	void preload_rom(const device_config *device, UINT16 *rom_data, int count)
	73	{
	74	er59256_t *er59256 = get_token(device);
	75	int WordNo;
	76
	77	logerror("Preloading %d words of data\n",count);
	78
	79	if(count>EEROM_WORDS)
	80	memcpy(&er59256->eerom,rom_data,count*2);
	81	else
	82	memcpy(&er59256->eerom,rom_data,EEROM_WORDS*2);
	83
	84	for(WordNo=0;WordNo<EEROM_WORDS;WordNo++)
	85	logerror("%04X ",er59256->eerom[WordNo]);
	86
	87	logerror("\n");
	88	}
	89
	90	UINT8 data_loaded(const device_config *device)
	91	{
	92	er59256_t *er59256 = get_token(device);
	93
	94	return (er59256->flags & FLAG_DATA_LOADED) ? 1 : 0;
	95	}
	96
72	97	/*-------------------------------------------------
73	98	DEVICE_START( er59256 )
74	99	-------------------------------------------------*/
r7191	r7192
83	108	memset(&er59256->eerom, 0xFF, EEROM_WORDS*2);
84	109
85	110	er59256->command=CMD_INVALID;
	111
	112	er59256->flags&= ~FLAG_DATA_LOADED;
86	113	}
87	114
88	115	static DEVICE_STOP( er59256 )
r7191	r7192
93	120	void er59256_set_iobits(const device_config *device, UINT8 newbits)
94	121	{
95	122	er59256_t *er59256 = get_token(device);
	123	//UINT32  bit;
96	124
97	125	// Make sure we only apply valid bits
98	126	newbits&=ALL_MASK;
99	127
100	128	if(LOGLEVEL>1)
101	129	{
102		logerror("en59256:newbits=%02X : ",newbits);
	130	logerror("er59256:newbits=%02X : ",newbits);
103	131	LOG_BITS(newbits);
104	132	logerror(" io_bits=%02X : ",er59256->io_bits);
105	133	LOG_BITS(er59256->io_bits);
r7191	r7192
110	138	// Only do anything if the inputs have changed
111	139	if((newbits&IN_MASK)!=(er59256->io_bits&IN_MASK))
112	140	{
113		// save the current state, then set the new one
	141	// save the current state, then set the new one, remembering to preserve data out
114	142	er59256->old_io_bits=er59256->io_bits;
115		er59256->io_bits=newbits;
	143	er59256->io_bits=(newbits & ~DO_MASK) | (er59256->old_io_bits&DO_MASK);
116	144
117	145	if(CS_RISE(er59256))
118	146	{
r7191	r7192
122	150
123	151	if(LOGLEVEL>1)
124	152	{
125		if(CK_RISE(er59256)) logerror("en59256:CK rise\n");
126		if(CS_RISE(er59256)) logerror("en59256:CS rise\n");
127		if(CK_FALL(er59256)) logerror("en59256:CK fall\n");
128		if(CS_FALL(er59256)) logerror("en59256:CS fall\n");
	153	if(CK_RISE(er59256)) logerror("er59256:CK rise\n");
	154	if(CS_RISE(er59256)) logerror("er59256:CS rise\n");
	155	if(CK_FALL(er59256)) logerror("er59256:CK fall\n");
	156	if(CS_FALL(er59256)) logerror("er59256:CS fall\n");
129	157	}
130	158
131	159	if(CK_RISE(er59256) && CS_VALID(er59256))
r7191	r7192
146	174	if((er59256->bitcount==WRITE_BITLEN) && ((er59256->command & CMD_MASK)==CMD_WRITE))
147	175	{
148	176	er59256->eerom[er59256->command & ADDR_MASK]=er59256->in_shifter;
149		LOG(1,"en59256:write[%02X]=%04X\n",(er59256->command & ADDR_MASK),er59256->in_shifter);
	177	LOG(1,"er59256:write[%02X]=%04X\n",(er59256->command & ADDR_MASK),er59256->in_shifter);
150	178	er59256->command=CMD_INVALID;
151	179	}
152		SHIFT_OUT(er59256);
	180	LOG(1,"out_shifter=%05X, io_bits=%02X\n",er59256->out_shifter,er59256->io_bits);
	181	SHIFT_OUT(er59256);
153	182	}
154	183
155	184	LOG(2,"io_bits:out=%02X\n",er59256->io_bits);
r7191	r7192
173	202	switch(er59256->command & CMD_MASK)
174	203	{
175	204	case CMD_READ   : er59256->out_shifter=er59256->eerom[er59256->command & ADDR_MASK];
176		LOG(1,"en59256:read[%02X]=%04X\n",(er59256->command&ADDR_MASK),er59256->eerom[er59256->command & ADDR_MASK]);
	205	LOG(1,"er59256:read[%02X]=%04X\n",(er59256->command&ADDR_MASK),er59256->eerom[er59256->command & ADDR_MASK]);
177	206	break;
178	207	case CMD_WRITE  : break;
179	208	case CMD_ERASE  : if (WRITE_ENABLED(er59256)) er59256->eerom[er59256->command & ADDR_MASK]=0xFF;
180		LOG(1,"en59256:erase[%02X]\n",(er59256->command&ADDR_MASK));
	209	LOG(1,"er59256:erase[%02X]\n",(er59256->command&ADDR_MASK));
181	210	break;
182	211	case CMD_EWEN   : er59256->flags|=FLAG_WRITE_EN;
183		LOG(1,"en59256:erase/write enabled\n");
	212	LOG(1,"er59256:erase/write enabled\n");
184	213	break;
185	214	case CMD_EWDS   : er59256->flags&=~FLAG_WRITE_EN;
186		LOG(1,"en59256:erase/write disabled\n");
	215	LOG(1,"er59256:erase/write disabled\n");
187	216	break;
188	217	case CMD_ERAL   : if (WRITE_ENABLED(er59256)) memset(&er59256->eerom, 0xFF, EEROM_WORDS*2);
189		LOG(1,"en59256:erase all\n");
	218	LOG(1,"er59256:erase all\n");
190	219	break;
191	220	}
192	221

src/mess/machine/er59256.h

r7191	r7192
25	25
26	26	#define EEROM_WORDS         0x10
27	27
28		#define CK_MASK             0x01
29		#define DI_MASK             0x02
30		#define DO_MASK             0x04
31		#define CS_MASK             0x08
32
33		#define ALL_MASK            (CK_MASK | DI_MASK | DO_MASK | CS_MASK)
34		#define IN_MASK             (CK_MASK | DI_MASK | CS_MASK)
35
36	28	#define CK_SHIFT            0x00
37	29	#define DI_SHIFT            0x01
38	30	#define DO_SHIFT            0x02
39	31	#define CS_SHIFT            0x03
40	32
	33	#define CK_MASK             (1<<CK_SHIFT)
	34	#define DI_MASK             (1<<DI_SHIFT)
	35	#define DO_MASK             (1<<DO_SHIFT)
	36	#define CS_MASK             (1<<CS_SHIFT)
	37
	38	#define ALL_MASK            (CK_MASK | DI_MASK | DO_MASK | CS_MASK)
	39	#define IN_MASK             (CK_MASK | DI_MASK | CS_MASK)
	40
41	41	#define GET_CK(eep)         ((eep->io_bits & CK_MASK) >> CK_SHIFT)
42	42	#define GET_DI(eep)         ((eep->io_bits & DI_MASK) >> DI_SHIFT)
43	43	#define GET_DO(eep)         ((eep->io_bits & DO_MASK) >> DO_SHIFT)
r7191	r7192
77	77
78	78	#define FLAG_WRITE_EN       0x01
79	79	#define FLAG_START_BIT      0x02
	80	#define FLAG_DATA_LOADED    0x04
80	81
81	82	#define WRITE_ENABLED(eep)  ((eep->flags & FLAG_WRITE_EN) ? 1 : 0)
82	83	#define STARTED(eep)        ((eep->flags & FLAG_START_BIT) ? 1 : 0)
r7191	r7192
87	88
88	89	void er59256_set_iobits(const device_config *device, UINT8 newbits);
89	90	UINT8 er59256_get_iobits(const device_config *device);
	91	void preload_rom(const device_config *device, UINT16 *rom_data, int count);
	92	UINT8 data_loaded(const device_config *device);
90	93	DEVICE_GET_INFO( er59256 );
91	94
92	95	#endif

src/mess/machine/rmnimbus.c

r7191	r7192
50	50	#define LOG_PC8031          0
51	51	#define LOG_PC8031_186      0
52	52	#define LOG_PC8031_PORT     0
53		#define LOG_IOU
	53	#define LOG_IOU             1
54	54	#define LOG_SOUND           0
55	55
56	56	/* 80186 internal stuff */
r7191	r7192
166	166	};
167	167
168	168	/* 8031 Peripheral controler */
	169	static struct _ipc_interface
	170	{
	171	UINT8   ipc_in;
	172	UINT8   ipc_out;
	173	UINT8   status_in;
	174	UINT8   status_out;
	175	UINT8   int_8c_pending;
	176	UINT8   int_8e_pending;
	177	UINT8   int_8f_pending;
	178	} ipc_interface;
169	179
170		UINT8 pcregs[PC8031_RAMSIZE];
171		UINT8 reg0C0_ptr;
172		UINT8 reg0C2_ptr;
	180	static UINT16 def_config[16] =
	181	{
	182	0x0280, 0x017F, 0xE822, 0x8129,
	183	0x0329, 0x0000, 0x0000, 0x0000,
	184	0x0000, 0x0000, 0x0000, 0x0000,
	185	0x0000, 0x8796, 0x2025, 0xB9E6
	186	};
173	187
174	188	/* IO Unit */
175
176	189	UINT8 iou_reg092;
177		UINT8 pc8031_int_pending;
178		UINT8 pc8031_inc_pending;
179	190
180	191	/* Sound */
181	192	UINT8 last_playmode;
r7191	r7192
202	213	static void keyboard_reset(void);
203	214	static TIMER_CALLBACK(keyscan_callback);
204	215
205		static void pc8031_reset(void);
	216	static void pc8031_reset(running_machine *machine);
206	217	static void iou_reset(void);
207	218	static void sound_reset(running_machine *machine);
208	219
r7191	r7192
1257	1268	fdc_reset();
1258	1269	hdc_reset(machine);
1259	1270	keyboard_reset();
1260		pc8031_reset();
	1271	pc8031_reset(machine);
1261	1272	sound_reset(machine);
1262	1273	}
1263	1274
r7191	r7192
2096	2107	// Nimbus FDC is hard wired for double density
2097	2108	wd17xx_set_density(fdc, DEN_MFM_LO);
2098	2109
2099		//logerror("nimbus_drives.reg400=%02X, data=%02X, drq_ff=%d\n",reg400_old,data,nimbus_drives.drq_ff);
2100
2101	2110	// if we enable hdc drq with a pending condition, act on it
2102	2111	if((data & HDC_DRQ_MASK) && (~reg400_old & HDC_DRQ_MASK))
2103	2112	hdc_drq(space->machine);
r7191	r7192
2199	2208
2200	2209	if(line==SCSI_LINE_REQ)
2201	2210	{
2202		//logerror("nimbus_scsi_linechange(%02X,%d), ~nimbus_drives.reg410_in=%02X, mask=%02X, (~reg410 & mask)=%02X, int_enabled=%d, int_enabled=%d\n",
2203		//         line,state,~nimbus_drives.reg410_in,HDC_INT_TRIGGER,(~nimbus_drives.reg410_in & HDC_INT_TRIGGER),HDC_IRQ_ENABLED(),HDC_DRQ_ENABLED());
2204	2211	if (state==0)
2205	2212	{
2206	2213	if(HDC_IRQ_ENABLED() && ((~nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
r7191	r7192
2219	2226
2220	2227	/* 8031/8051 Peripheral controler 80186 side */
2221	2228
2222		#define REG_0C2_INIT        1
2223		#define INC_REG0C2_PTR()    reg0C2_ptr++; if (reg0C2_ptr==PC8031_RAMSIZE) reg0C2_ptr=REG_0C2_INIT;
2224		#define CLEAR_PCREGS()      memset(&pcregs[1],0,PC8031_RAMSIZE-1);
	2229	static void pc8031_reset(running_machine *machine)
	2230	{
	2231	const device_config *er59256 = devtag_get_device(machine, ER59256_TAG);
2225	2232
2226		static void pc8031_reset(void)
2227		{
2228	2233	logerror("peripheral controler reset\n");
2229	2234
2230		memset(&pcregs,0,sizeof(pcregs));
2231		reg0C0_ptr=0;
2232		reg0C2_ptr=REG_0C2_INIT;
2233		pc8031_int_pending=0;
2234		pc8031_inc_pending=0;
	2235	memset(&ipc_interface,0,sizeof(ipc_interface));
	2236
	2237	if(!data_loaded(er59256))
	2238	preload_rom(er59256,def_config,ARRAY_LENGTH(def_config));
2235	2239	}
2236	2240
2237		static void dump_pcregs(void)
	2241
	2242	#if 0
	2243	static void ipc_dumpregs()
2238	2244	{
2239		int regno;
2240
2241		if(LOG_IOU)
2242		{
2243		logerror("pcregs: ");
2244		for(regno=0;regno<PC8031_RAMSIZE;regno++)
2245		logerror("%02X, ",pcregs[regno]);
2246
2247		logerror("\n");
2248		}
	2245	logerror("in_data=%02X, in_status=%02X, out_data=%02X, out_status=%02X\n",
	2246	ipc_interface.ipc_in, ipc_interface.status_in,
	2247	ipc_interface.ipc_out, ipc_interface.status_out);
	2248
2249	2249	}
	2250	#endif
2250	2251
2251	2252	READ8_HANDLER( pc8031_r )
2252	2253	{
r7191	r7192
2255	2256
2256	2257	switch(offset*2)
2257	2258	{
2258		case 0x00   : result=pcregs[reg0C0_ptr];
2259		reg0C2_ptr=REG_0C2_INIT;
2260		CLEAR_PCREGS();
	2259	case 0x00   : result=ipc_interface.ipc_out;
	2260	ipc_interface.status_in   &= ~IPC_IN_READ_PEND;
	2261	ipc_interface.status_out  &= ~IPC_OUT_BYTE_AVAIL;
2261	2262	break;
2262	2263
2263		case 0x02   : result=pcregs[reg0C2_ptr];
2264		INC_REG0C2_PTR();
	2264	case 0x02   : result=ipc_interface.status_out;
2265	2265	break;
2266	2266
2267	2267	default : result=0; break;
2268	2268	}
2269	2269
2270	2270	if(LOG_PC8031_186)
2271		logerror("Nimbus PCIOR %08X read of %04X returns %02X reg0C2_ptr=%02X\n",pc,(offset*2)+0xC0,result,reg0C2_ptr);
2272
2273		if(LOG_PC8031_186)
2274		dump_pcregs();
2275
	2271	logerror("Nimbus PCIOR %08X read of %04X returns %02X\n",pc,(offset*2)+0xC0,result);
	2272
2276	2273	return result;
2277	2274	}
2278	2275
r7191	r7192
2282	2279
2283	2280	switch(offset*2)
2284	2281	{
2285		case 0x00   : pcregs[reg0C0_ptr]=data;
2286		//reg0C2_ptr=REG_0C2_INIT;
2287		//CLEAR_PCREGS();
2288		pc8031_int_pending=1;
	2282	case 0x00   : ipc_interface.ipc_in=data;
	2283	ipc_interface.status_in   |= IPC_IN_BYTE_AVAIL;
	2284	ipc_interface.status_in   &= ~IPC_IN_ADDR;
	2285	ipc_interface.status_out  |= IPC_OUT_READ_PEND;
2289	2286	break;
2290	2287
2291		case 0x02   : pcregs[reg0C2_ptr]=data;
2292		//INC_REG0C2_PTR();
2293		pc8031_int_pending=1;
2294		pc8031_inc_pending=1;
	2288	case 0x02   : ipc_interface.ipc_in=data;
	2289	ipc_interface.status_in   |= IPC_IN_BYTE_AVAIL;
	2290	ipc_interface.status_in   |= IPC_IN_ADDR;
	2291	ipc_interface.status_out  |= IPC_OUT_READ_PEND;
2295	2292	break;
2296	2293	}
2297	2294
2298	2295	if(LOG_PC8031_186)
2299		logerror("Nimbus PCIOW %08X write of %02X to %04X, reg0C2_ptr=%02X,\n",pc,data,(offset*2)+0xC0,reg0C2_ptr);
	2296	logerror("Nimbus PCIOW %08X write of %02X to %04X\n",pc,data,(offset*2)+0xC0);
2300	2297
2301		dump_pcregs();
2302	2298	}
2303	2299
2304	2300	/* 8031/8051 Peripheral controler 8031/8051 side */
r7191	r7192
2307	2303	{
2308	2304	int pc=cpu_get_pc(space->cpu);
2309	2305	UINT8   result;
2310
2311		result=pcregs[offset%PC8031_RAMSIZE];
2312	2306
2313		if(LOG_PC8031)
2314		logerror("8031: PCIOR %04X read of %04X returns %02X\n",pc,offset,result);
2315
2316		//if(offset==0x00)
2317		//{
2318		//    reg0C2_ptr=REG_0C2_INIT;
2319		//    CLEAR_PCREGS();
2320		//}
2321
2322		if((offset==reg0C2_ptr) && pc8031_inc_pending)
	2307	switch (offset & 0x01)
2323	2308	{
2324		INC_REG0C2_PTR();
2325		pc8031_inc_pending=0;
	2309	case 0x00   : result=ipc_interface.ipc_in;
	2310	ipc_interface.status_out  &= ~IPC_OUT_READ_PEND;
	2311	ipc_interface.status_in   &= ~IPC_IN_BYTE_AVAIL;
	2312	break;
	2313
	2314	case 0x01   : result=ipc_interface.status_in;
	2315	break;
2326	2316	}
2327
2328		if((iou_reg092 & PC8031_INT_ENABLE) && pc8031_int_pending)
2329		{
2330		pc8031_int_pending=0x00;
2331		external_int(space->machine,0,EXTERNAL_INT_PC8031);
2332		}
	2317
	2318	if(((offset==2) || (offset==3)) && (iou_reg092 & PC8031_INT_ENABLE))
	2319	external_int(space->machine,0,EXTERNAL_INT_PC8031_8C);
2333	2320
	2321	if(LOG_PC8031)
	2322	logerror("8031: PCIOR %04X read of %04X returns %02X\n",pc,offset,result);
	2323
2334	2324	return result;
2335	2325	}
2336	2326
2337	2327	WRITE8_HANDLER( pc8031_iou_w )
2338	2328	{
2339		int pc=cpu_get_pc(space->cpu);
	2329	int pc=cpu_get_pc(space->cpu);
2340	2330
2341	2331	if(LOG_PC8031)
2342	2332	logerror("8031 PCIOW %04X write of %02X to %04X\n",pc,data,offset);
	2333
	2334	switch(offset & 0x03)
	2335	{
	2336	case 0x00   : ipc_interface.ipc_out=data;
	2337	ipc_interface.status_out  |= IPC_OUT_BYTE_AVAIL;
	2338	ipc_interface.status_out  &= ~IPC_OUT_ADDR;
	2339	ipc_interface.status_in   |= IPC_IN_READ_PEND;
	2340	break;
	2341
	2342	case 0x01   : ipc_interface.ipc_out=data;
	2343	ipc_interface.status_out   |= IPC_OUT_BYTE_AVAIL;
	2344	ipc_interface.status_out   |= IPC_OUT_ADDR;
	2345	ipc_interface.status_in    |= IPC_IN_READ_PEND;
	2346	break;
2343	2347
2344		pcregs[offset%PC8031_RAMSIZE]=data;
2345
2346		//    if(offset==0x00)
2347		//    {
2348		//        reg0C2_ptr=REG_0C2_INIT;
2349		//        CLEAR_PCREGS();
2350		//    }
	2348	case 0x02   : ipc_interface.ipc_out=data;
	2349	ipc_interface.status_out  |= IPC_OUT_BYTE_AVAIL;
	2350	ipc_interface.status_out  &= ~IPC_OUT_ADDR;
	2351	ipc_interface.status_in   |= IPC_IN_READ_PEND;
	2352	if(iou_reg092 & PC8031_INT_ENABLE)
	2353	external_int(space->machine,0,EXTERNAL_INT_PC8031_8F);
	2354	break;
	2355
	2356	case 0x03   : ipc_interface.ipc_out=data;
	2357	//ipc_interface.status_out   |= IPC_OUT_BYTE_AVAIL;
	2358	ipc_interface.status_out   |= IPC_OUT_ADDR;
	2359	ipc_interface.status_in    |= IPC_IN_READ_PEND;
	2360	if(iou_reg092 & PC8031_INT_ENABLE)
	2361	external_int(space->machine,0,EXTERNAL_INT_PC8031_8E);
	2362	break;
	2363	}
2351	2364	}
2352	2365
2353	2366	READ8_HANDLER( pc8031_port_r )
r7191	r7192
2418	2431	static void iou_reset(void)
2419	2432	{
2420	2433	iou_reg092=0x00;
2421		pc8031_int_pending=0;
2422	2434	}
2423	2435
2424	2436	/*

src/mess/drivers/rmnimbus.c

r7191	r7192
95	95
96	96	static ADDRESS_MAP_START(nimbus_mem, ADDRESS_SPACE_PROGRAM, 16)
97	97	AM_RANGE( 0x00000, 0xEFFFF ) AM_RAM
98		AM_RANGE( 0xF0000, 0xFFFFF ) AM_ROM
	98	AM_RANGE( 0xF0000, 0xFFFFF ) AM_ROM AM_REGION(MAINCPU_TAG, 0x0f0000)
99	99	ADDRESS_MAP_END
100	100
101	101	static ADDRESS_MAP_START(nimbus_io, ADDRESS_SPACE_IO, 16)
r7191	r7192
317	317	ROM_START( nimbus )
318	318	ROM_REGION( 0x100000, MAINCPU_TAG, 0 )
319	319
320		//  ROM_LOAD16_BYTE("sys1-1.31a-16128-1986-06-18.rom", 0x0001, 0x8000, CRC(6416eb05) SHA1(1b640163a7efbc24381c7b24976a8609c066959b))
321		//   ROM_RELOAD(0xf0001,0x8000)
322		//  ROM_LOAD16_BYTE("sys2-1.31a-16129-1986-06-18.rom", 0x0000, 0x8000, CRC(b224359d) SHA1(456bbe37afcd4429cca76ba2d6bd534dfda3fc9c))
323		//   ROM_RELOAD(0xf0000,0x8000)
	320	ROM_SYSTEM_BIOS(0, "v131a", "Nimbus BIOS v1.31a (1986-06-18)")
	321	ROMX_LOAD("sys1-1.31a-16128-1986-06-18.rom", 0xf0001, 0x8000, CRC(6416eb05) SHA1(1b640163a7efbc24381c7b24976a8609c066959b),ROM_SKIP(1) | ROM_BIOS(1)  )
	322	ROMX_LOAD("sys2-1.31a-16129-1986-06-18.rom", 0xf0000, 0x8000, CRC(b224359d) SHA1(456bbe37afcd4429cca76ba2d6bd534dfda3fc9c),ROM_SKIP(1) | ROM_BIOS(1)  )
324	323
325		ROM_LOAD16_BYTE("sys-1-1.32f-22779-1989-10-20.rom", 0x0001, 0x8000, CRC(786c31e8) SHA1(da7f828f7f96087518bea1a3d89fee59b283b4ba))
326		ROM_RELOAD(0xf0001,0x8000)
327		ROM_LOAD16_BYTE("sys-2-1.32f-22779-1989-10-20.rom", 0x0000, 0x8000, CRC(0be3db64) SHA1(af806405ec6fbc20385705f90d5059a47de17b08))
328		ROM_RELOAD(0xf0000,0x8000)
	324	ROM_SYSTEM_BIOS(1, "v132f", "Nimbus BIOS v1.32f (1989-10-20)")
	325	ROMX_LOAD("sys-1-1.32f-22779-1989-10-20.rom", 0xf0001, 0x8000, CRC(786c31e8) SHA1(da7f828f7f96087518bea1a3d89fee59b283b4ba),ROM_SKIP(1) | ROM_BIOS(2) )
	326	ROMX_LOAD("sys-2-1.32f-22779-1989-10-20.rom", 0xf0000, 0x8000, CRC(0be3db64) SHA1(af806405ec6fbc20385705f90d5059a47de17b08),ROM_SKIP(1) | ROM_BIOS(2) )
329	327
	328	ROM_SYSTEM_BIOS(2, "v140d", "Nimbus BIOS v1.40d (1990-xx-xx)")
	329	ROMX_LOAD("sys-1-1.40d.rom", 0xf0001, 0x8000, CRC(b8d3dc0b) SHA1(82e0dcdc6c7a83339af68d6cb61211fcb14bed88),ROM_SKIP(1) | ROM_BIOS(3) )
	330	ROMX_LOAD("sys-2-1.40d.rom", 0xf0000, 0x8000, CRC(b0826b0b) SHA1(3baa369a0e7ef138ca29aae0ee8a89ab670a02b9),ROM_SKIP(1) | ROM_BIOS(3) )
	331
330	332	ROM_REGION( 0x4000, IOCPU_TAG, 0 )
331	333	ROM_LOAD("hexec-v1.02u-13488-1985-10-29.rom", 0x0000, 0x1000, CRC(75c6adfd) SHA1(0f11e0b7386c6368d20e1fc7a6196d670f924825))
332	334	ROM_END

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