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r6582 Tuesday 8th December, 2009 at 14:32:10 UTC by Tim Schuerewegen
[GP32] Added NVRAM. It is now possible to load executables from SmartMedia cards that are encrypted with the GP32 unique ID.

[src/mess/drivers]

gp32.c

src/mess/drivers/gp32.c

r6581	r6582
26	26	#define BITS(x,m,n) (((x)>>(n))&((1<<((m)-(n)+1))-1))
27	27
28	28	static UINT32 *s3c240x_ram;
	29	static UINT8 *eeprom_data;
29	30
30	31	// LCD CONTROLLER
31	32
r6581	r6582
856	857
857	858	static emu_timer *s3c240x_iic_timer;
858	859	static UINT32 s3c240x_iic_regs[0x10/4];
	860	static UINT8 s3c240x_iic_data[3];
	861	static int s3c240x_iic_data_index = 0;
	862	static UINT16 s3c240x_iic_addr = 0;
859	863
860		static UINT8 iic_read( running_machine *machine, int last)
	864	/*
	865	static UINT8 i2cmem_read_byte( running_machine *machine, int last)
861	866	{
862	867	UINT8 data = 0;
863		/*
864	868	int i;
865	869	i2cmem_write( machine, 0, I2CMEM_SDA, 1);
866	870	for (i=0;i<8;i++)
r6581	r6582
872	876	i2cmem_write( machine, 0, I2CMEM_SDA, last);
873	877	i2cmem_write( machine, 0, I2CMEM_SCL, 1);
874	878	i2cmem_write( machine, 0, I2CMEM_SCL, 0);
875		*/
876	879	return data;
877	880	}
	881	*/
878	882
879		static void iic_write( running_machine *machine, UINT8 data)
	883	/*
	884	static void i2cmem_write_byte( running_machine *machine, UINT8 data)
880	885	{
881		/*
882	886	int i;
883	887	for (i=0;i<8;i++)
884	888	{
r6581	r6582
887	891	i2cmem_write( machine, 0, I2CMEM_SCL, 1);
888	892	i2cmem_write( machine, 0, I2CMEM_SCL, 0);
889	893	}
890		i2cmem_write( machine, 0, I2CMEM_SDA, 1);
	894	i2cmem_write( machine, 0, I2CMEM_SDA, 1); // ack bit
891	895	i2cmem_write( machine, 0, I2CMEM_SCL, 1);
892	896	i2cmem_write( machine, 0, I2CMEM_SCL, 0);
	897	}
893	898	*/
894		}
895	899
896		static void iic_start( running_machine *machine)
	900	/*
	901	static void i2cmem_start( running_machine *machine)
897	902	{
898		/*
899	903	i2cmem_write( machine, 0, I2CMEM_SDA, 1);
900	904	i2cmem_write( machine, 0, I2CMEM_SCL, 1);
901	905	i2cmem_write( machine, 0, I2CMEM_SDA, 0);
902	906	i2cmem_write( machine, 0, I2CMEM_SCL, 0);
	907	}
903	908	*/
904		}
905	909
906		static void iic_stop( running_machine *machine)
	910	/*
	911	static void i2cmem_stop( running_machine *machine)
907	912	{
908		/*
909	913	i2cmem_write( machine, 0, I2CMEM_SDA, 0);
910	914	i2cmem_write( machine, 0, I2CMEM_SCL, 1);
911	915	i2cmem_write( machine, 0, I2CMEM_SDA, 1);
912	916	i2cmem_write( machine, 0, I2CMEM_SCL, 0);
	917	}
913	918	*/
	919
	920	static void iic_start( running_machine *machine)
	921	{
	922	//   logerror( "IIC start\n");
	923	s3c240x_iic_data_index = 0;
	924	timer_adjust_oneshot( s3c240x_iic_timer, ATTOTIME_IN_MSEC( 1), 0);
914	925	}
915	926
	927	static void iic_stop( running_machine *machine)
	928	{
	929	//   logerror( "IIC stop\n");
	930	timer_adjust_oneshot( s3c240x_iic_timer, attotime_never, 0);
	931	}
	932
	933	static void iic_resume( running_machine *machine)
	934	{
	935	//   logerror( "IIC resume\n");
	936	timer_adjust_oneshot( s3c240x_iic_timer, ATTOTIME_IN_MSEC( 1), 0);
	937	}
	938
916	939	static READ32_HANDLER( s3c240x_iic_r )
917	940	{
918	941	UINT32 data = s3c240x_iic_regs[offset];
r6581	r6582
946	969	//         tx_clock_source_selection = (data >> 6) & 1;
947	970	//         enable_interrupt = (data >> 5) & 1;
948	971	//         clock = (double)(s3c240x_get_pclk( MPLLCON) / div_table[tx_clock_source_selection] / (transmit_clock_value + 1));
949		interrupt_pending_flag = (data >> 4) & 1;
	972	interrupt_pending_flag = BIT( data, 4);
950	973	if (interrupt_pending_flag == 0)
951	974	{
952	975	int start_stop_condition;
953		start_stop_condition = (s3c240x_iic_regs[1] >> 5) & 1;
	976	start_stop_condition = BIT( s3c240x_iic_regs[1], 5);
954	977	if (start_stop_condition != 0)
955	978	{
956		//               logerror( "IIC resume\n");
957		timer_adjust_oneshot( s3c240x_iic_timer, ATTOTIME_IN_MSEC( 10), 0);
	979	iic_resume( space->machine);
958	980	}
959	981	}
960	982	}
r6581	r6582
962	984	// IICSTAT
963	985	case 0x04 / 4 :
964	986	{
965		int start_stop_condition, mode_selection;
966		mode_selection = (data >> 6) & 3;
967		start_stop_condition = (data >> 5) & 1;
	987	int start_stop_condition;
	988	start_stop_condition = BIT( data, 5);
968	989	if (start_stop_condition != 0)
969	990	{
970		//            logerror( "IIC start (mode %d)\n", mode_selection);
971	991	iic_start( space->machine);
972		timer_adjust_oneshot( s3c240x_iic_timer, ATTOTIME_IN_MSEC( 10), 0);
973	992	}
974	993	else
975	994	{
976		//            logerror( "IIC stop\n");
977	995	iic_stop( space->machine);
978		timer_adjust_oneshot( s3c240x_iic_timer, attotime_never, 0);
979	996	}
980	997	}
981	998	break;
r6581	r6582
985	1002	static TIMER_CALLBACK( s3c240x_iic_timer_exp )
986	1003	{
987	1004	int enable_interrupt, mode_selection;
988		//   logerror( "s3c240x_iic_timer_exp\n");
989		mode_selection = (s3c240x_iic_regs[1] >> 6) & 3;
	1005	//   logerror( "IIC timer callback\n");
	1006	mode_selection = BITS( s3c240x_iic_regs[1], 7, 6);
990	1007	switch (mode_selection)
991	1008	{
992	1009	// master receive mode
993	1010	case 2 :
994	1011	{
995		UINT8 data_shift = iic_read( machine, 0);
996		//         logerror( "IIC READ %02X\n", data_shift);
997		s3c240x_iic_regs[3] = (s3c240x_iic_regs[3] & ~0xFF) | data_shift;
	1012	if (s3c240x_iic_data_index == 0)
	1013	{
	1014	//            UINT8 data_shift = s3c240x_iic_regs[3] & 0xFF;
	1015	//            logerror( "IIC write %02X\n", data_shift);
	1016	}
	1017	else
	1018	{
	1019	UINT8 data_shift = eeprom_data[s3c240x_iic_addr];
	1020	//            logerror( "IIC read %02X [%04X]\n", data_shift, s3c240x_iic_addr);
	1021	s3c240x_iic_regs[3] = (s3c240x_iic_regs[3] & ~0xFF) | data_shift;
	1022	}
	1023	s3c240x_iic_data_index++;
998	1024	}
999	1025	break;
1000	1026	// master transmit mode
1001	1027	case 3 :
1002	1028	{
1003	1029	UINT8 data_shift = s3c240x_iic_regs[3] & 0xFF;
1004		//         logerror( "IIC WRITE %02X\n", data_shift);
1005		iic_write( machine, data_shift);
	1030	//         logerror( "IIC write %02X\n", data_shift);
	1031	s3c240x_iic_data[s3c240x_iic_data_index++] = data_shift;
	1032	if (s3c240x_iic_data_index == 3)
	1033	{
	1034	s3c240x_iic_addr = (s3c240x_iic_data[1] << 8) | s3c240x_iic_data[2];
	1035	}
1006	1036	}
1007	1037	break;
1008	1038	}
1009		enable_interrupt = (s3c240x_iic_regs[0] >> 5) & 1;
	1039	enable_interrupt = BIT( s3c240x_iic_regs[0], 5);
1010	1040	if (enable_interrupt)
1011	1041	{
1012	1042	//      logerror( "IIC request irq\n");
r6581	r6582
1182	1212	s3c240x_pwm_timer[4] = timer_alloc(machine, s3c240x_pwm_timer_exp, (void *)(FPTR)4);
1183	1213	s3c240x_iic_timer = timer_alloc(machine, s3c240x_iic_timer_exp, (void *)(FPTR)0);
1184	1214	s3c240x_iis_timer = timer_alloc(machine, s3c240x_iis_timer_exp, (void *)(FPTR)0);
	1215	eeprom_data = auto_alloc_array( machine, UINT8, 0x2000);
1185	1216	smc_init( machine);
1186	1217	i2s_init( machine);
1187	1218	}
r6581	r6582
1192	1223	i2s_reset( machine);
1193	1224	}
1194	1225
	1226	static NVRAM_HANDLER( gp32 )
	1227	{
	1228	if (read_or_write)
	1229	{
	1230	if (file)
	1231	{
	1232	mame_fwrite( file, eeprom_data, 0x2000);
	1233	}
	1234	}
	1235	else
	1236	{
	1237	if (file)
	1238	{
	1239	mame_fread( file, eeprom_data, 0x2000);
	1240	}
	1241	else
	1242	{
	1243	memset( eeprom_data, 0, 0x2000);
	1244	}
	1245	}
	1246	}
	1247
1195	1248	static ADDRESS_MAP_START( gp32_map, ADDRESS_SPACE_PROGRAM, 32 )
1196	1249	AM_RANGE(0x00000000, 0x0007ffff) AM_ROM
1197	1250	AM_RANGE(0x0c000000, 0x0c7fffff) AM_RAM AM_BASE(&s3c240x_ram)
r6581	r6582
1267	1320	MDRV_SOUND_ADD("dac2", DMADAC, 0)
1268	1321	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
1269	1322
	1323	MDRV_NVRAM_HANDLER(gp32)
	1324
1270	1325	MDRV_SMARTMEDIA_ADD("smartmedia")
1271	1326	MACHINE_DRIVER_END
1272	1327

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