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r6534 Friday 4th December, 2009 at 22:02:00 UTC by Tim Schuerewegen
[GP32] Added very basic timer, interrupt, dma, button and smartmedia support.

[src/mess/drivers]	gp32.c
[src/mess/includes]	gp32.h*

src/mess/includes/gp32.h

r0	r6534
	1	#ifndef _GP32_H_
	2	#define _GP32_H_
	3
	4	#define INT_ADC       31
	5	#define INT_RTC       30
	6	#define INT_UTXD1     29
	7	#define INT_UTXD0     28
	8	#define INT_IIC       27
	9	#define INT_USBH      26
	10	#define INT_USBD      25
	11	#define INT_URXD1     24
	12	#define INT_URXD0     23
	13	#define INT_SPI       22
	14	#define INT_MMC       21
	15	#define INT_DMA3      20
	16	#define INT_DMA2      19
	17	#define INT_DMA1      18
	18	#define INT_DMA0      17
	19	#define INT_RESERVED  16
	20	#define INT_UERR      15
	21	#define INT_TIMER4    14
	22	#define INT_TIMER3    13
	23	#define INT_TIMER2    12
	24	#define INT_TIMER1    11
	25	#define INT_TIMER0    10
	26	#define INT_WDT        9
	27	#define INT_TICK       8
	28	#define INT_EINT7      7
	29	#define INT_EINT6      6
	30	#define INT_EINT5      5
	31	#define INT_EINT4      4
	32	#define INT_EINT3      3
	33	#define INT_EINT2      2
	34	#define INT_EINT1      1
	35	#define INT_EINT0      0
	36
	37	#endif

src/mess/drivers/gp32.c

r6533	r6534
17	17	#include "driver.h"
18	18	#include "video/generic.h"
19	19	#include "cpu/arm7/arm7.h"
	20	#include "cpu/arm7/arm7core.h"
	21	#include "machine/smartmed.h"
	22	#include "includes/gp32.h"
20	23
	24	static UINT32 *s3c240x_ram;
	25
	26	// LCD CONTROLLER
	27
21	28	static UINT32 s3c240x_vidregs[0x400/4];
22	29
23		static UINT32 *s3c240x_ram;
	30	#define BPPMODE_TFT_01   0x08
	31	#define BPPMODE_TFT_08   0x0B
	32	#define BPPMODE_TFT_16   0x0C
24	33
25	34	static VIDEO_UPDATE( gp32 )
26	35	{
27	36	if (s3c240x_vidregs[0] & 1)   // display enabled?
28	37	{
29		int x, y;
	38	int x, y, bppmode;
	39	//      int hwswp, tpal, offsize;
30	40	UINT8 *vram;
31		UINT32 vramaddr = s3c240x_vidregs[5];
	41	UINT32 vramaddr;
32	42
33		// get offset
34		vramaddr = (vramaddr & 0x1fffff);
35		vramaddr |= (s3c240x_vidregs[5]&0xffe00000)<<1;
	43	//      logerror("vramaddr 1 = %08X\n", s3c240x_vidregs[5] << 1);
	44	//      logerror("vramaddr 2 = %08X\n", ((s3c240x_vidregs[5] & 0xFFE00000) | s3c240x_vidregs[6]) << 1);
	45	vramaddr = s3c240x_vidregs[5] << 1;
36	46
37	47	vram = (UINT8 *)&s3c240x_ram[(vramaddr-0x0c000000)/4];
38	48
39		for (y = 0; y < 240; y++)
	49	bppmode = (s3c240x_vidregs[0] >> 1) & 0xF;
	50
	51	//      hwswp = (s3c240x_vidregs[4] >> 0) & 0x1;
	52	//      tpal = s3c240x_vidregs[20] & 0x0001FFFF;
	53	//      offsize = (s3c240x_vidregs[7] >> 11) & 0x7FF;
	54	//      logerror("bppmode %d hwswp %d tpal %05X offsize %03X\n", bppmode, hwswp, tpal, offsize);
	55
	56	switch (bppmode)
40	57	{
41		UINT16 *scanline = BITMAP_ADDR16(bitmap, y, 0);
42
43		for (x = 0; x < 320; x++)
	58	case BPPMODE_TFT_08 :
44	59	{
45		*scanline++ = vram[(160*y)+x];
	60	for (y = 0; y < 320; y++)
	61	{
	62	UINT16 *scanline = BITMAP_ADDR16( bitmap, y, 0);
	63	for (x = 0; x < 240; x++)
	64	{
	65	*scanline++ = vram[(240*y)+x];
	66	}
	67	}
46	68	}
	69	break;
47	70	}
48	71	}
49
50	72	return 0;
51	73	}
52	74
53		static READ32_HANDLER(s3c240x_vidregs_r)
	75	static READ32_HANDLER( s3c240x_vidregs_r )
54	76	{
55		// make sure line counter is going
56		s3c240x_vidregs[0] &= 0x3ffff;
57		s3c240x_vidregs[0] |= (240-video_screen_get_vpos(space->machine->primary_screen))<<18;
58
59		return s3c240x_vidregs[offset];
	77	UINT32 data = s3c240x_vidregs[offset];
	78	switch (offset)
	79	{
	80	// LCDCON1
	81	case 0x00 / 4 :
	82	{
	83	// make sure line counter is going
	84	data = (data & ~0xFFFC0000) | ((240 - video_screen_get_vpos( space->machine->primary_screen)) << 18);
	85	}
	86	break;
	87	}
	88	return data;
60	89	}
61	90
62		static WRITE32_HANDLER(s3c240x_vidregs_w)
	91	static WRITE32_HANDLER( s3c240x_vidregs_w )
63	92	{
	93	//   logerror( "(LCD) %08X <- %08X\n", 0x14A00000 + (offset << 2), data);
64	94	COMBINE_DATA(&s3c240x_vidregs[offset]);
65	95	}
66	96
67		static WRITE32_HANDLER(s3c240x_palette_w)
	97	static WRITE32_HANDLER( s3c240x_palette_w )
68	98	{
69	99	if (mem_mask != 0xffffffff)
70	100	{
71		printf("s3c240x_palette_w: unknown mask %08x\n", mem_mask);
	101	logerror("s3c240x_palette_w: unknown mask %08x\n", mem_mask);
72	102	}
73
74	103	palette_set_color_rgb(space->machine, offset, ((data>>11)&0x1f)<<3, ((data>>5)&0x3f)<<2, (data&0x1f)<<3);
75	104	}
76	105
	106	// CLOCK & POWER MANAGEMENT
	107
	108	static UINT32 s3c240x_clkpow_regs[0x18/4];
	109
	110	UINT32 cpu_get_fclk( int reg)
	111	{
	112	UINT32 data, mdiv, pdiv, sdiv;
	113	data = s3c240x_clkpow_regs[reg]; // MPLLCON or UPLLCON
	114	mdiv = (data >> 12) & 0xFF;
	115	pdiv = (data >>  4) & 0x3F;
	116	sdiv = (data >>  0) & 0x03;
	117	return (UINT32)((float)((mdiv + 8) * 12000000) / (float)((pdiv + 2) * (1 << sdiv)));
	118	}
	119
	120	UINT32 cpu_get_hclk( int reg)
	121	{
	122	switch (s3c240x_clkpow_regs[5] & 0x3) // CLKDIVN
	123	{
	124	case 0 : return cpu_get_fclk( reg) / 1;
	125	case 1 : return cpu_get_fclk( reg) / 1;
	126	case 2 : return cpu_get_fclk( reg) / 2;
	127	case 3 : return cpu_get_fclk( reg) / 2;
	128	}
	129	return 0;
	130	}
	131
	132	UINT32 cpu_get_pclk( int reg)
	133	{
	134	switch (s3c240x_clkpow_regs[5] & 0x3) // CLKDIVN
	135	{
	136	case 0 : return cpu_get_fclk( reg) / 1;
	137	case 1 : return cpu_get_fclk( reg) / 2;
	138	case 2 : return cpu_get_fclk( reg) / 2;
	139	case 3 : return cpu_get_fclk( reg) / 4;
	140	}
	141	return 0;
	142	}
	143
	144	static READ32_HANDLER( s3c240x_clkpow_r )
	145	{
	146	return s3c240x_clkpow_regs[offset];
	147	}
	148
	149	static WRITE32_HANDLER( s3c240x_clkpow_w )
	150	{
	151	//   logerror( "(CLKPOW) %08X <- %08X\n", 0x14800000 + (offset << 2), data);
	152	COMBINE_DATA(&s3c240x_clkpow_regs[offset]);
	153	}
	154
	155	// INTERRUPT CONTROLLER
	156
77	157	static UINT32 s3c240x_irq_regs[0x18/4];
78		static READ32_HANDLER(s3c240x_irq_r)
	158
	159	static READ32_HANDLER( s3c240x_irq_r )
79	160	{
80		return s3c240x_irq_regs[offset];
	161	UINT32 data = s3c240x_irq_regs[offset];
	162	//   logerror( "(IRQ) %08X -> %08X\n", 0x14400000 + (offset << 2), data);
	163	return data;
81	164	}
82	165
83		static WRITE32_HANDLER(s3c240x_irq_w)
	166	static WRITE32_HANDLER( s3c240x_irq_w )
84	167	{
85		//  printf("%08x to interrupt controller @ 0x144000%02x\n", data, offset<<2);
86
	168	//   logerror( "(IRQ) %08X <- %08X\n", 0x14400000 + (offset << 2), data);
87	169	COMBINE_DATA(&s3c240x_irq_regs[offset]);
88	170	}
89	171
	172	static void s3c240x_request_irq( running_machine *machine, UINT32 int_type)
	173	{
	174	//   logerror( "request irq %d\n", int_type);
	175	s3c240x_irq_regs[5] = int_type; // INTOFFSET
	176	cpu_set_input_line( cputag_get_cpu( machine, "maincpu"), ARM7_IRQ_LINE, ASSERT_LINE);
	177	cpu_set_input_line( cputag_get_cpu( machine, "maincpu"), ARM7_IRQ_LINE, CLEAR_LINE);
	178	}
	179
	180	// PWM TIMER
	181
90	182	#if 0
91	183	static const char *timer_reg_names[] =
92	184	{
r6533	r6534
113	205
114	206	static emu_timer *s3c240x_timers[5];
115	207	static UINT32 s3c240x_timer_regs[0x44/4];
116		static READ32_HANDLER(s3c240x_timer_r)
	208
	209	static READ32_HANDLER( s3c240x_timer_r )
117	210	{
118		return s3c240x_timer_regs[offset];
	211	UINT32 data = s3c240x_timer_regs[offset];
	212	//   logerror( "(TIMER) %08X -> %08X\n", 0x15100000 + (offset << 2), data);
	213	return data;
119	214	}
120	215
121		static void s3c240x_timer_recalc(running_machine *machine, int timer, UINT32 ctrl_bits, UINT32 count_reg)
	216	static void s3c240x_timer_recalc( running_machine *machine, int timer, UINT32 ctrl_bits, UINT32 count_reg)
122	217	{
	218	const int mux_table[] = { 2, 4, 8, 16};
	219	const int prescaler_shift[] = { 0, 0, 8, 8, 8};
	220	const int mux_shift[] = { 0, 4, 8, 12, 16};
123	221	if (ctrl_bits & 1)   // timer start?
124	222	{
125		//      printf("starting timer %d\n", timer);
	223	UINT32 prescaler, mux, freq, cnt, cmp, tps;
	224	logerror( "starting timer %d\n", timer);
	225	prescaler = (s3c240x_timer_regs[0] >> prescaler_shift[timer]) & 0xFF;
	226	mux = (s3c240x_timer_regs[1] >> mux_shift[timer]) & 0x0F;
	227	freq = cpu_get_pclk( 1) / (prescaler + 1) / mux_table[mux];
	228	cnt = s3c240x_timer_regs[count_reg+0] & 0xFFFF;
	229	if (timer != 4)
	230	cmp = s3c240x_timer_regs[count_reg+1] & 0xFFFF;
	231	else
	232	cmp = 0;
	233	tps = freq * (cnt - cmp + 1);
	234	//      logerror( "TIMER %d - FCLK=%d HCLK=%d PCLK=%d prescaler=%d div=%d freq=%d cnt=%d cmp=%d tps=%d\n", timer, cpu_get_fclk( 1), cpu_get_hclk( 1), cpu_get_pclk( 1), prescaler, mux_table[mux], freq, cnt, cmp, tps);
	235	if (ctrl_bits & 8) // auto reload
	236	{
	237	timer_adjust_periodic( s3c240x_timers[timer], ATTOTIME_IN_HZ( tps), timer, ATTOTIME_IN_HZ( tps));
	238	}
	239	else
	240	{
	241	timer_adjust_oneshot( s3c240x_timers[timer], ATTOTIME_IN_HZ( tps), timer);
	242	}
126	243	}
127	244	else   // stopping is easy
128	245	{
129		//      printf("stopping timer %d\n", timer);
130		timer_adjust_oneshot(s3c240x_timers[timer], attotime_never, 0);
	246	logerror( "stopping timer %d\n", timer);
	247	timer_adjust_oneshot( s3c240x_timers[timer], attotime_never, 0);
131	248	}
132	249	}
133	250
134		static WRITE32_HANDLER(s3c240x_timer_w)
	251	static WRITE32_HANDLER( s3c240x_timer_w )
135	252	{
136	253	UINT32 old_value = s3c240x_timer_regs[offset];
137
138		//  printf("%08x to timer @ 0x151000%02x (%s)\n", data, offset<<2, timer_reg_names[offset]);
139
	254	//   logerror( "(TIMER) %08X <- %08X\n", 0x15100000 + (offset << 2), data);
140	255	COMBINE_DATA(&s3c240x_timer_regs[offset]);
141
142	256	if (offset == 2)   // TCON
143	257	{
144	258	if ((data & 1) != (old_value & 1))   // timer 0 status change
145	259	{
146	260	s3c240x_timer_recalc(space->machine, 0, data&0xf, 0xc);
147	261	}
148
149	262	if ((data & 0x100) != (old_value & 0x100))   // timer 1 status change
150	263	{
151	264	s3c240x_timer_recalc(space->machine, 1, (data>>8)&0xf, 0x18);
152	265	}
153
154	266	if ((data & 0x1000) != (old_value & 0x1000))   // timer 2 status change
155	267	{
156	268	s3c240x_timer_recalc(space->machine, 2, (data>>12)&0xf, 0x24);
157	269	}
158
159	270	if ((data & 0x10000) != (old_value & 0x10000))   // timer 3 status change
160	271	{
161	272	s3c240x_timer_recalc(space->machine, 3, (data>>16)&0xf, 0x30);
162	273	}
163
164	274	if ((data & 0x100000) != (old_value & 0x100000))   // timer 4 status change
165	275	{
166	276	s3c240x_timer_recalc(space->machine, 4, (data>>20)&0xf, 0x3c);
r6533	r6534
171	281	static TIMER_CALLBACK( s3c240x_timer_exp )
172	282	{
173	283	int ch = param;
	284	static UINT32 ch_int[5] = { INT_TIMER0, INT_TIMER1, INT_TIMER2, INT_TIMER3, INT_TIMER4 };
	285	//   logerror( "timer %d callback\n", ch);
	286	//   timer_adjust_oneshot(s3c240x_timers[ch], attotime_never, 0);
	287	s3c240x_request_irq( machine, ch_int[ch]);
	288	}
174	289
175		timer_adjust_oneshot(s3c240x_timers[ch], attotime_never, 0);
	290	// DMA
	291
	292	static UINT32 s3c240x_dma_regs[0x7c/4];
	293
	294	static void s3c240x_dma_start( running_machine *machine, int dma)
	295	{
	296	UINT32 size, addr_src, addr_dst, reg = dma << 3;
	297	const address_space *space = cpu_get_address_space( cputag_get_cpu( machine, "maincpu"), ADDRESS_SPACE_PROGRAM);
	298	int i;
	299	addr_src = s3c240x_dma_regs[reg+0] & 0x1FFFFFFF;
	300	addr_dst = s3c240x_dma_regs[reg+1] & 0x1FFFFFFF;
	301	size = (s3c240x_dma_regs[reg+2] & 0x000FFFFF) << ((s3c240x_dma_regs[reg+2] >> 20) & 3);
	302	//   logerror( "DMA %d -> copy 0x%08X bytes from 0x%08X to 0x%08X\n", dma, size, addr_src, addr_dst);
	303	for (i=0;i<size;i++) memory_write_byte( space, addr_dst + i, memory_read_byte( space, addr_src + i));
176	304	}
177	305
178		static void s3c240x_machine_start(running_machine *machine)
	306	static READ32_HANDLER( s3c240x_dma_r )
179	307	{
180		s3c240x_timers[0] = timer_alloc(machine, s3c240x_timer_exp, (void *)(FPTR)0);
181		s3c240x_timers[1] = timer_alloc(machine, s3c240x_timer_exp, (void *)(FPTR)1);
182		s3c240x_timers[2] = timer_alloc(machine, s3c240x_timer_exp, (void *)(FPTR)2);
183		s3c240x_timers[3] = timer_alloc(machine, s3c240x_timer_exp, (void *)(FPTR)3);
184		s3c240x_timers[4] = timer_alloc(machine, s3c240x_timer_exp, (void *)(FPTR)4);
	308	UINT32 data = s3c240x_dma_regs[offset];
	309	//   logerror( "(DMA) %08X -> %08X\n", 0x14600000 + (offset << 2), data);
	310	return data;
185	311	}
186	312
	313	static WRITE32_HANDLER( s3c240x_dma_w )
	314	{
	315	//   logerror( "(DMA) %08X <- %08X\n", 0x14600000 + (offset << 2), data);
	316	COMBINE_DATA(&s3c240x_dma_regs[offset]);
	317	switch (offset)
	318	{
	319	// DMASKTRIG0
	320	case 0x18 / 4 :
	321	{
	322	if (data & 2) s3c240x_dma_start( space->machine, 0);
	323	}
	324	break;
	325	// DMASKTRIG1
	326	case 0x38 / 4 :
	327	{
	328	if (data & 2) s3c240x_dma_start( space->machine, 1);
	329	}
	330	break;
	331	// DMASKTRIG2
	332	case 0x58 / 4 :
	333	{
	334	if (data & 2) s3c240x_dma_start( space->machine, 2);
	335	}
	336	break;
	337	// DMASKTRIG3
	338	case 0x78 / 4 :
	339	{
	340	if (data & 2) s3c240x_dma_start( space->machine, 3);
	341	}
	342	break;
	343	}
	344	}
	345
	346	// SMARTMEDIA
	347
	348	static struct {
	349	int add_latch;
	350	int chip;
	351	int cmd_latch;
	352	int do_read;
	353	int do_write;
	354	int read;
	355	int wp;
	356	int busy;
	357	UINT8 datarx;
	358	UINT8 datatx;
	359	} smc;
	360
	361	void smc_reset(void)
	362	{
	363	//   logerror( "smc_reset\n");
	364	smc.add_latch = 0;
	365	smc.chip = 0;
	366	smc.cmd_latch = 0;
	367	smc.do_read = 0;
	368	smc.do_write = 0;
	369	smc.read = 0;
	370	smc.wp = 0;
	371	smc.busy = 0;
	372	}
	373
	374	UINT8 smc_read( running_machine *machine)
	375	{
	376	const device_config *smartmedia = devtag_get_device( machine, "smartmedia");
	377	UINT8 data;
	378	data = smartmedia_data_r( smartmedia);
	379	//   logerror( "smc_read %08X\n", data);
	380	return data;
	381	}
	382
	383	void smc_write( running_machine *machine, UINT8 data)
	384	{
	385	//   logerror( "smc_write %08X\n", data);
	386	if ((smc.chip) && (!smc.read))
	387	{
	388	const device_config *smartmedia = devtag_get_device( machine, "smartmedia");
	389	if (smc.cmd_latch)
	390	{
	391	//         logerror( "smartmedia_command_w %08X\n", data);
	392	smartmedia_command_w( smartmedia, data);
	393	}
	394	else if (smc.add_latch)
	395	{
	396	//         logerror( "smartmedia_address_w %08X\n", data);
	397	smartmedia_address_w( smartmedia, data);
	398	}
	399	else
	400	{
	401	//         logerror( "smartmedia_data_w %08X\n", data);
	402	smartmedia_data_w( smartmedia, data);
	403	}
	404	}
	405	}
	406
	407	void smc_update( running_machine *machine)
	408	{
	409	if (!smc.chip)
	410	{
	411	smc_reset();
	412	}
	413	else
	414	{
	415	if ((smc.do_write) && (!smc.read))
	416	{
	417	smc_write( machine, smc.datatx);
	418	}
	419	else if ((!smc.do_write) && (smc.do_read) && (smc.read) && (!smc.cmd_latch) && (!smc.add_latch))
	420	{
	421	smc.datarx = smc_read( machine);
	422	}
	423	}
	424	}
	425
	426	// I/O PORT
	427
187	428	static UINT32 s3c240x_gpio[0x60/4];
188	429
189	430	static READ32_HANDLER( s3c240x_gpio_r )
190	431	{
191		//  printf("read GPIO @ 0x156000%02x (PC %x)\n", offset*4, cpu_get_pc(space->cpu));
192
193		return s3c240x_gpio[offset];
	432	UINT32 data = s3c240x_gpio[offset];
	433	//   logerror("read GPIO @ 0x156000%02x (PC %x)\n", offset*4, cpu_get_pc(space->cpu));
	434	switch (offset)
	435	{
	436	// PBCON
	437	case 0x08 / 4 :
	438	{
	439	// smartmedia
	440	data = (data & ~0x00000001);
	441	if (!smc.read) data = data | 0x00000001;
	442	}
	443	break;
	444	// PBDAT
	445	case 0x0C / 4 :
	446	{
	447	// smartmedia
	448	data = (data & ~0x000000FF) | (smc.datarx & 0xFF);
	449	// buttons
	450	data = (data & ~0x0000FF00) | (input_port_read( space->machine, "IN0") & 0x0000FF00);
	451	}
	452	break;
	453	// PDDAT
	454	case 0x24 / 4 :
	455	{
	456	const device_config *smartmedia = devtag_get_device( space->machine, "smartmedia");
	457	// smartmedia
	458	data = (data & ~0x000003C0);
	459	if (!smc.busy) data = data | 0x00000200;
	460	if (!smc.do_read) data = data | 0x00000100;
	461	if (!smc.chip) data = data | 0x00000080;
	462	if (!smartmedia_protected( smartmedia)) data = data | 0x00000040;
	463	}
	464	break;
	465	// PEDAT
	466	case 0x30 / 4 :
	467	{
	468	const device_config *smartmedia = devtag_get_device( space->machine, "smartmedia");
	469	// smartmedia
	470	data = (data & ~0x0000003C);
	471	if (smc.cmd_latch) data = data | 0x00000020;
	472	if (smc.add_latch) data = data | 0x00000010;
	473	if (!smc.do_write) data = data | 0x00000008;
	474	if (!smartmedia_present( smartmedia)) data = data | 0x00000004;
	475	// buttons
	476	data = (data & ~0x000000C0) | (input_port_read( space->machine, "IN1") & 0x000000C0);
	477	}
	478	break;
	479	}
	480	return data;
194	481	}
195	482
196	483	static WRITE32_HANDLER( s3c240x_gpio_w )
197	484	{
	485	//   UINT32 old_value = s3c240x_timer_regs[offset];
198	486	COMBINE_DATA(&s3c240x_gpio[offset]);
	487	//   logerror("%08x to GPIO @ 0x156000%02x (PC %x)\n", data, offset*4, cpu_get_pc(space->cpu));
	488	//   if (offset == 0x30/4) logerror("[%08x] %s %s\n", data, (data & 0x200) ? "SCL" : "scl", (data & 0x400) ? "SDL" : "sdl");
	489	switch (offset)
	490	{
	491	// PBCON
	492	case 0x08 / 4 :
	493	{
	494	// smartmedia
	495	//if ((old_value & 0x00000001) != (data & 0x00000001))
	496	{
	497	smc.read = ((data & 0x00000001) == 0);
	498	smc_update( space->machine);
	499	}
	500	}
	501	break;
	502	// PBDAT
	503	case 0x0C / 4 :
	504	{
	505	// smartmedia
	506	smc.datatx = data & 0xFF;
	507	}
	508	break;
	509	// PDDAT
	510	case 0x24 / 4 :
	511	{
	512	// smartmedia
	513	//if ((old_value & 0x000001C0) != (data & 0x000001C0))
	514	{
	515	smc.do_read = ((data & 0x00000100) == 0);
	516	smc.chip = ((data & 0x00000080) == 0);
	517	smc.wp = ((data & 0x00000040) == 0);
	518	smc_update( space->machine);
	519	}
	520	}
	521	break;
	522	// PEDAT
	523	case 0x30 / 4 :
	524	{
	525	// smartmedia
	526	//if ((old_value & 0x00000038) != (data & 0x00000038))
	527	{
	528	smc.cmd_latch = ((data & 0x00000020) != 0);
	529	smc.add_latch = ((data & 0x00000010) != 0);
	530	smc.do_write  = ((data & 0x00000008) == 0);
	531	smc_update( space->machine);
	532	}
	533	}
	534	break;
	535	}
	536	}
199	537
200		// printf("%08x to GPIO @ 0x156000%02x (PC %x)\n", data, offset*4, cpu_get_pc(space->cpu));
	538	// MEMORY CONTROLLER
201	539
202		//  if (offset == 0x30/4) printf("[%08x] %s %s\n", data, (data & 0x200) ? "SCL" : "scl", (data & 0x400) ? "SDL" : "sdl");
	540	static UINT32 s3c240x_memcon_regs[0x34/4];
	541
	542	static READ32_HANDLER( s3c240x_memcon_r )
	543	{
	544	return s3c240x_memcon_regs[offset];
203	545	}
204	546
	547	static WRITE32_HANDLER( s3c240x_memcon_w )
	548	{
	549	//   logerror( "(MEMCON) %08X <- %08X\n", 0x14000000 + (offset << 2), data);
	550	COMBINE_DATA(&s3c240x_memcon_regs[offset]);
	551	}
	552
	553	// USB HOST CONTROLLER
	554
	555	static UINT32 s3c240x_usb_host_regs[0x5C/4];
	556
	557	static READ32_HANDLER( s3c240x_usb_host_r )
	558	{
	559	return s3c240x_usb_host_regs[offset];
	560	}
	561
	562	static WRITE32_HANDLER( s3c240x_usb_host_w )
	563	{
	564	//   logerror( "(USB H) %08X <- %08X\n", 0x14200000 + (offset << 2), data);
	565	COMBINE_DATA(&s3c240x_usb_host_regs[offset]);
	566	}
	567
	568	// UART 0
	569
	570	static UINT32 s3c240x_uart_0_regs[0x2C/4];
	571
	572	static READ32_HANDLER( s3c240x_uart_0_r )
	573	{
	574	UINT32 data = s3c240x_uart_0_regs[offset];
	575	switch (offset)
	576	{
	577	// UTRSTAT0
	578	case 0x10 / 4 :
	579	{
	580	data = (data & ~0x00000006) | 0x00000004 | 0x00000002;
	581	}
	582	break;
	583	}
	584	return data;
	585	}
	586
	587	static WRITE32_HANDLER( s3c240x_uart_0_w )
	588	{
	589	//   logerror( "(UART 0) %08X <- %08X\n", 0x15000000 + (offset << 2), data);
	590	COMBINE_DATA(&s3c240x_uart_0_regs[offset]);
	591	}
	592
	593	// UART 1
	594
	595	static UINT32 s3c240x_uart_1_regs[0x2C/4];
	596
	597	static READ32_HANDLER( s3c240x_uart_1_r )
	598	{
	599	return s3c240x_uart_1_regs[offset];
	600	}
	601
	602	static WRITE32_HANDLER( s3c240x_uart_1_w )
	603	{
	604	//   logerror( "(UART 1) %08X <- %08X\n", 0x15004000 + (offset << 2), data);
	605	COMBINE_DATA(&s3c240x_uart_1_regs[offset]);
	606	}
	607
	608	// USB DEVICE
	609
	610	static UINT32 s3c240x_usb_device_regs[0xBC/4];
	611
	612	static READ32_HANDLER( s3c240x_usb_device_r )
	613	{
	614	return s3c240x_usb_device_regs[offset];
	615	}
	616
	617	static WRITE32_HANDLER( s3c240x_usb_device_w )
	618	{
	619	//   logerror( "(USB D) %08X <- %08X\n", 0x15200140 + (offset << 2), data);
	620	COMBINE_DATA(&s3c240x_usb_device_regs[offset]);
	621	}
	622
	623	// WATCHDOG TIMER
	624
	625	static UINT32 s3c240x_watchdog_regs[0x0C/4];
	626
	627	static READ32_HANDLER( s3c240x_watchdog_r )
	628	{
	629	return s3c240x_watchdog_regs[offset];
	630	}
	631
	632	static WRITE32_HANDLER( s3c240x_watchdog_w )
	633	{
	634	//   logerror( "(WDOG) %08X <- %08X\n", 0x15300000 + (offset << 2), data);
	635	COMBINE_DATA(&s3c240x_watchdog_regs[offset]);
	636	}
	637
	638	// IIC
	639
	640	static UINT32 s3c240x_iic_regs[0x10/4];
	641
	642	static READ32_HANDLER( s3c240x_iic_r )
	643	{
	644	return s3c240x_iic_regs[offset];
	645	}
	646
	647	static WRITE32_HANDLER( s3c240x_iic_w )
	648	{
	649	//   logerror( "(IIC) %08X <- %08X\n", 0x15400000 + (offset << 2), data);
	650	COMBINE_DATA(&s3c240x_iic_regs[offset]);
	651	}
	652
	653	// IIS
	654
	655	static UINT32 s3c240x_iis_regs[0x14/4];
	656
	657	static READ32_HANDLER( s3c240x_iis_r )
	658	{
	659	UINT32 data = s3c240x_iis_regs[offset];
	660	//if (offset == 0) data = data & (~0x01); // mp3
	661	return data;
	662	}
	663
	664	static WRITE32_HANDLER( s3c240x_iis_w )
	665	{
	666	//   logerror( "(IIS) %08X <- %08X\n", 0x15508000 + (offset << 2), data);
	667	COMBINE_DATA(&s3c240x_iis_regs[offset]);
	668	}
	669
	670	// RTC
	671
	672	static UINT32 s3c240x_rtc_regs[0x4C/4];
	673
	674	static READ32_HANDLER( s3c240x_rtc_r )
	675	{
	676	return s3c240x_rtc_regs[offset];
	677	}
	678
	679	static WRITE32_HANDLER( s3c240x_rtc_w )
	680	{
	681	//   logerror( "(RTC) %08X <- %08X\n", 0x15700040 + (offset << 2), data);
	682	COMBINE_DATA(&s3c240x_rtc_regs[offset]);
	683	}
	684
	685	// A/D CONVERTER
	686
	687	static UINT32 s3c240x_adc_regs[0x08/4];
	688
	689	static READ32_HANDLER( s3c240x_adc_r )
	690	{
	691	return s3c240x_adc_regs[offset];
	692	}
	693
	694	static WRITE32_HANDLER( s3c240x_adc_w )
	695	{
	696	//   logerror( "(ADC) %08X <- %08X\n", 0x15800000 + (offset << 2), data);
	697	COMBINE_DATA(&s3c240x_adc_regs[offset]);
	698	}
	699
	700	// SPI
	701
	702	static UINT32 s3c240x_spi_regs[0x18/4];
	703
	704	static READ32_HANDLER( s3c240x_spi_r )
	705	{
	706	return s3c240x_spi_regs[offset];
	707	}
	708
	709	static WRITE32_HANDLER( s3c240x_spi_w )
	710	{
	711	//   logerror( "(SPI) %08X <- %08X\n", 0x15900000 + (offset << 2), data);
	712	COMBINE_DATA(&s3c240x_spi_regs[offset]);
	713	}
	714
	715	// MMC INTERFACE
	716
	717	static UINT32 s3c240x_mmc_regs[0x40/4];
	718
	719	static READ32_HANDLER( s3c240x_mmc_r )
	720	{
	721	return s3c240x_mmc_regs[offset];
	722	}
	723
	724	static WRITE32_HANDLER( s3c240x_mmc_w )
	725	{
	726	COMBINE_DATA(&s3c240x_mmc_regs[offset]);
	727	}
	728
	729	// ...
	730
	731	static void s3c240x_machine_start(running_machine *machine)
	732	{
	733	s3c240x_timers[0] = timer_alloc(machine, s3c240x_timer_exp, (void *)(FPTR)0);
	734	s3c240x_timers[1] = timer_alloc(machine, s3c240x_timer_exp, (void *)(FPTR)1);
	735	s3c240x_timers[2] = timer_alloc(machine, s3c240x_timer_exp, (void *)(FPTR)2);
	736	s3c240x_timers[3] = timer_alloc(machine, s3c240x_timer_exp, (void *)(FPTR)3);
	737	s3c240x_timers[4] = timer_alloc(machine, s3c240x_timer_exp, (void *)(FPTR)4);
	738	smc_reset();
	739	}
	740
	741	static void s3c240x_machine_reset(running_machine *machine)
	742	{
	743	smc_reset();
	744	}
	745
205	746	static ADDRESS_MAP_START( gp32_map, ADDRESS_SPACE_PROGRAM, 32 )
206	747	AM_RANGE(0x00000000, 0x0007ffff) AM_ROM
207	748	AM_RANGE(0x0c000000, 0x0c7fffff) AM_RAM AM_BASE(&s3c240x_ram)
	749	AM_RANGE(0x14000000, 0x1400003b) AM_READWRITE(s3c240x_memcon_r, s3c240x_memcon_w)
	750	AM_RANGE(0x14200000, 0x1420005b) AM_READWRITE(s3c240x_usb_host_r, s3c240x_usb_host_w)
208	751	AM_RANGE(0x14400000, 0x14400017) AM_READWRITE(s3c240x_irq_r, s3c240x_irq_w)
	752	AM_RANGE(0x14600000, 0x1460007b) AM_READWRITE(s3c240x_dma_r, s3c240x_dma_w)
	753	AM_RANGE(0x14800000, 0x14800017) AM_READWRITE(s3c240x_clkpow_r, s3c240x_clkpow_w)
209	754	AM_RANGE(0x14a00000, 0x14a003ff) AM_READWRITE(s3c240x_vidregs_r, s3c240x_vidregs_w)
210	755	AM_RANGE(0x14a00400, 0x14a007ff) AM_RAM AM_BASE_GENERIC(paletteram) AM_WRITE(s3c240x_palette_w)
	756	AM_RANGE(0x15000000, 0x1500002b) AM_READWRITE(s3c240x_uart_0_r, s3c240x_uart_0_w)
	757	AM_RANGE(0x15004000, 0x1500402b) AM_READWRITE(s3c240x_uart_1_r, s3c240x_uart_1_w)
211	758	AM_RANGE(0x15100000, 0x15100043) AM_READWRITE(s3c240x_timer_r, s3c240x_timer_w)
	759	AM_RANGE(0x15200140, 0x152001fb) AM_READWRITE(s3c240x_usb_device_r, s3c240x_usb_device_w)
	760	AM_RANGE(0x15300000, 0x1530000b) AM_READWRITE(s3c240x_watchdog_r, s3c240x_watchdog_w)
	761	AM_RANGE(0x15400000, 0x1540000f) AM_READWRITE(s3c240x_iic_r, s3c240x_iic_w)
	762	AM_RANGE(0x15508000, 0x15508013) AM_READWRITE(s3c240x_iis_r, s3c240x_iis_w)
212	763	AM_RANGE(0x15600000, 0x1560005b) AM_READWRITE(s3c240x_gpio_r, s3c240x_gpio_w)
	764	AM_RANGE(0x15700040, 0x1570008b) AM_READWRITE(s3c240x_rtc_r, s3c240x_rtc_w)
	765	AM_RANGE(0x15800000, 0x15800007) AM_READWRITE(s3c240x_adc_r, s3c240x_adc_w)
	766	AM_RANGE(0x15900000, 0x15900017) AM_READWRITE(s3c240x_spi_r, s3c240x_spi_w)
	767	AM_RANGE(0x15a00000, 0x15a0003f) AM_READWRITE(s3c240x_mmc_r, s3c240x_mmc_w)
213	768	ADDRESS_MAP_END
214	769
215	770	static INPUT_PORTS_START( gp32 )
	771	PORT_START("IN0")
	772	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("R") PORT_PLAYER(1)
	773	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("L") PORT_PLAYER(1)
	774	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
	775	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
	776	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
	777	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
	778	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("B") PORT_PLAYER(1)
	779	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("A") PORT_PLAYER(1)
	780	PORT_START("IN1")
	781	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_SELECT ) PORT_NAME("SELECT") PORT_PLAYER(1)
	782	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_START ) PORT_NAME("START") PORT_PLAYER(1)
216	783	INPUT_PORTS_END
217	784
218	785	static MACHINE_START( gp32 )
r6533	r6534
220	787	s3c240x_machine_start(machine);
221	788	}
222	789
	790	static MACHINE_RESET( gp32 )
	791	{
	792	s3c240x_machine_reset(machine);
	793	}
	794
223	795	static MACHINE_DRIVER_START( gp32 )
224	796	MDRV_CPU_ADD("maincpu", ARM9, 40000000)
225	797	MDRV_CPU_PROGRAM_MAP(gp32_map)
226	798
227	799	MDRV_PALETTE_LENGTH(32768)
228	800
229		MDRV_SCREEN_ADD("screen", RASTER)
	801	MDRV_SCREEN_ADD("screen", LCD)
230	802	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
231	803	MDRV_SCREEN_REFRESH_RATE(60)
232	804	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
233		MDRV_SCREEN_SIZE(320, 240)
234		MDRV_SCREEN_VISIBLE_AREA(0, 319, 0, 239)
	805	MDRV_SCREEN_SIZE(240, 320)
	806	MDRV_SCREEN_VISIBLE_AREA(0, 239, 0, 319)
	807	MDRV_DEFAULT_LAYOUT(layout_lcd)
235	808
236	809	MDRV_VIDEO_UPDATE(gp32)
237	810
238	811	MDRV_MACHINE_START(gp32)
	812	MDRV_MACHINE_RESET(gp32)
239	813
240	814	MDRV_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
	815
	816	MDRV_SMARTMEDIA_ADD("smartmedia")
241	817	MACHINE_DRIVER_END
242	818
243	819	ROM_START(gp32)
244	820	ROM_REGION( 0x80000, "maincpu", 0 )
245		ROM_LOAD( "gp32157e.bin", 0x000000, 0x080000, CRC(b1e35643) SHA1(1566bc2a27980602e9eb501cf8b2d62939bfd1e5) )
	821	ROM_SYSTEM_BIOS( 0, "157e", "GP32 Firmware 1.57 (English)" )
	822	ROMX_LOAD( "gp32157e.bin", 0x000000, 0x080000, CRC(b1e35643) SHA1(1566bc2a27980602e9eb501cf8b2d62939bfd1e5), ROM_BIOS(1) )
	823	ROM_SYSTEM_BIOS( 1, "100k", "GP32 Firmware 1.00 (Korean)" )
	824	ROMX_LOAD( "gp32100k.bin", 0x000000, 0x080000, CRC(d9925ac9) SHA1(3604d0d7210ed72eddd3e3e0c108f1102508423c), ROM_BIOS(2) )
	825	ROM_SYSTEM_BIOS( 2, "156k", "GP32 Firmware 1.56 (Korean)" )
	826	ROMX_LOAD( "gp32156k.bin", 0x000000, 0x080000, CRC(667fb1c8) SHA1(d179ab8e96411272b6a1d683e59da752067f9da8), ROM_BIOS(3) )
246	827	ROM_END
247	828
248	829	CONS(2001, gp32, 0, 0, gp32, gp32, 0, 0, "Game Park", "GP32", GAME_NOT_WORKING|GAME_NO_SOUND)
249

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