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r6489 Tuesday 1st December, 2009 at 06:37:25 UTC by Harmony
[IP6] Reformatted IP6 driver [Harmony] [IP2] Added SGI IRIS 3130 IP2 "meaty" skeleton driver [Harmony] - It will talk to you over the TTY and you can talk back, but it understands nothing.

[src/mess]	mess.mak messdriv.c
[src/mess/drivers]	ip22.c ip6.c sgi_ip2.c* sgi_ip6.c*

src/mess/messdriv.c

r6488	r6489
643	643	DRIVER( x68030 )    /* Sharp X68030 (1993)                              */
644	644
645	645	/* Silicon Graphics */
	646	DRIVER( sgi_ip2 )   /* IP2: IRIS 2x00, 68020, 16MHz                  */
646	647	DRIVER( sgi_ip6 )   /* IP6: 4D/PI, R2000, 20MHz                         */
647	648	DRIVER( ip204415 )  /* IP20: Indigo 1, R4400, 150MHz                    */
648	649	DRIVER( ip225015 )  /* IP22: Indy, R5000, 150MHz                  */
r6488	r6489
1522	1523	DRIVER( pda600 )
1523	1524	DRIVER( pce220 )
1524	1525	DRIVER( mod8 )
1525		DRIVER( k1003 )
	1526	DRIVER( k1003 )
1526	1527	DRIVER( mk14 )
1527	1528	DRIVER( elekscmp )
1528	1529	DRIVER( ht68k )

src/mess/mess.mak

r6488	r6489
1231	1231
1232	1232	$(MESSOBJ)/sgi.a:            \
1233	1233	$(MESS_MACHINE)/sgi.o      \
	1234	$(MESS_DRIVERS)/sgi_ip2.o   \
	1235	$(MESS_DRIVERS)/sgi_ip6.o   \
1234	1236	$(MESS_DRIVERS)/ip20.o      \
1235	1237	$(MESS_DRIVERS)/ip22.o      \
1236		$(MESS_DRIVERS)/ip6.o      \
1237	1238	$(MESS_VIDEO)/newport.o      \
1238	1239
1239	1240	$(MESSOBJ)/sharp.a:            \

src/mess/drivers/ip6.c

r6488	r6489
1		/*********************************************************************\
2		*
3		*   SGI IP6 4D/PI workstation
4		*
5		*   Skeleton driver by Harmony
6		*
7		*   Todo: Everything
8		*
9		*   Preliminary Memory map:
10		*
11		*    1fc00000 - 1fc3ffff      BIOS
12		*
13		\*********************************************************************/
14
15		#include "driver.h"
16		#include "cpu/mips/r3000.h"
17
18		#define VERBOSE_LEVEL ( 99 )
19
20		INLINE void ATTR_PRINTF(3,4) verboselog( running_machine *machine, int n_level, const char *s_fmt, ... )
21		{
22		if( VERBOSE_LEVEL >= n_level )
23		{
24		va_list v;
25		char buf[ 32768 ];
26		va_start( v, s_fmt );
27		vsprintf( buf, s_fmt, v );
28		va_end( v );
29		logerror("%08x: %s", cpu_get_pc(cputag_get_cpu(machine, "maincpu")), buf);
30		}
31		}
32
33		typedef struct
34		{
35		UINT16 unknown_half_0;
36		UINT8 unknown_byte_0;
37		UINT8 unknown_byte_1;
38		} ip6_regs_t;
39
40		static ip6_regs_t ip6_regs;
41
42		static READ32_HANDLER( ip6_unk1_r )
43		{
44		UINT32 ret = 0;
45		switch(offset)
46		{
47		case 0x0000/4:
48		if(ACCESSING_BITS_16_31)
49		{
50		verboselog(space->machine, 0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
51		}
52		if(ACCESSING_BITS_0_15)
53		{
54		verboselog(space->machine, 0, "ip6_unk1_r: Unknown Halfword 0: %08x & %08x\n", ip6_regs.unknown_half_0, mem_mask );
55		ret |= ip6_regs.unknown_half_0;
56		}
57		break;
58		default:
59		verboselog(space->machine, 0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
60		break;
61		}
62		return ret;
63		}
64
65		static WRITE32_HANDLER( ip6_unk1_w )
66		{
67		switch(offset)
68		{
69		case 0x0000/4:
70		if(ACCESSING_BITS_16_31)
71		{
72		verboselog(space->machine, 0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
73		}
74		if(ACCESSING_BITS_0_15)
75		{
76		verboselog(space->machine, 0, "ip6_unk1_w: Unknown Halfword 0 = %04x & %04x\n", data & 0x0000ffff, mem_mask & 0x0000ffff );
77		ip6_regs.unknown_half_0 = data & 0x0000ffff;
78		}
79		break;
80		default:
81		verboselog(space->machine, 0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
82		break;
83		}
84		}
85
86		static READ32_HANDLER( ip6_unk2_r )
87		{
88		UINT32 ret = 0;
89		switch(offset)
90		{
91		case 0x0000/4:
92		if(!ACCESSING_BITS_24_31)
93		{
94		verboselog(space->machine, 0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
95		}
96		if(ACCESSING_BITS_24_31)
97		{
98		verboselog(space->machine, 0, "ip6_unk2_r: Unknown Byte 0 = %02x & %02x\n", ip6_regs.unknown_byte_0, mem_mask >> 24 );
99		ret |= ip6_regs.unknown_byte_0 << 24;
100		}
101		break;
102		default:
103		verboselog(space->machine, 0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
104		break;
105		}
106		return ret;
107		}
108
109		static WRITE32_HANDLER( ip6_unk2_w )
110		{
111		switch(offset)
112		{
113		case 0x0000/4:
114		if(!ACCESSING_BITS_24_31)
115		{
116		verboselog(space->machine, 0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
117		}
118		if(ACCESSING_BITS_24_31)
119		{
120		verboselog(space->machine, 0, "ip6_unk2_w: Unknown Byte 0 = %02x & %02x\n", data >> 24, mem_mask >> 24 );
121		ip6_regs.unknown_byte_0 = (data & 0xff000000) >> 24;
122		}
123		break;
124		default:
125		verboselog(space->machine, 0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
126		break;
127		}
128		}
129
130		static READ32_HANDLER(ip6_unk3_r)
131		{
132		UINT32 ret = 0;
133		if(ACCESSING_BITS_16_23)
134		{
135		verboselog(space->machine, 0, "ip6_unk3_r: Unknown Byte 1: %02x & %02x\n", ip6_regs.unknown_byte_1, (mem_mask >> 16) & 0x000000ff);
136		ret |= ip6_regs.unknown_byte_1 << 16;
137		}
138		else
139		{
140		verboselog(space->machine, 0, "ip6_unk3_r: Unknown address: %08x & %08x\n", 0x1fb00000 + (offset << 2), mem_mask );
141		}
142		return ret;
143		}
144
145		static WRITE32_HANDLER(ip6_unk3_w)
146		{
147		verboselog(space->machine, 0, "ip6_unk3_w: Unknown address: %08x = %08x & %08x\n", 0x1fb00000 + (offset << 2), data, mem_mask );
148		}
149
150		static ADDRESS_MAP_START( sgi_ip6_map, ADDRESS_SPACE_PROGRAM, 32 )
151		AM_RANGE( 0x1f880000, 0x1f880003 ) AM_READWRITE(ip6_unk1_r, ip6_unk1_w)
152		AM_RANGE( 0x1fb00000, 0x1fb00003 ) AM_READWRITE(ip6_unk3_r, ip6_unk3_w)
153		AM_RANGE( 0x1fbc004c, 0x1fbc004f ) AM_READWRITE(ip6_unk2_r, ip6_unk2_w)
154		AM_RANGE( 0x1fc00000, 0x1fc3ffff ) AM_ROM AM_REGION( "user1", 0 )
155		ADDRESS_MAP_END
156
157		static MACHINE_START( sgi_ip6 )
158		{
159		}
160
161		static MACHINE_RESET( sgi_ip6 )
162		{
163		ip6_regs.unknown_byte_0 = 0x80;
164		ip6_regs.unknown_byte_1 = 0x80;
165		ip6_regs.unknown_half_0 = 0;
166		}
167
168		static DRIVER_INIT( sgi_ip6 )
169		{
170		}
171
172		static INPUT_PORTS_START( sgi_ip6 )
173		PORT_START("UNUSED") // unused IN0
174		PORT_BIT(0xffff, IP_ACTIVE_HIGH, IPT_UNUSED)
175		INPUT_PORTS_END
176
177		static INTERRUPT_GEN( sgi_ip6_vbl )
178		{
179		}
180
181		static const r3000_cpu_core config =
182		{
183		0,      /* 1 if we have an FPU, 0 otherwise */
184		4096,   /* code cache size */
185		4096   /* data cache size */
186		};
187
188		static MACHINE_DRIVER_START( sgi_ip6 )
189		MDRV_CPU_ADD( "maincpu", R3000BE, 20000000 ) // FIXME: Should be R2000
190		MDRV_CPU_CONFIG( config )
191		MDRV_CPU_PROGRAM_MAP( sgi_ip6_map )
192		MDRV_CPU_VBLANK_INT("screen", sgi_ip6_vbl)
193
194		MDRV_MACHINE_RESET( sgi_ip6 )
195
196		/* video hardware */
197		MDRV_SCREEN_ADD("screen", RASTER)
198		MDRV_SCREEN_REFRESH_RATE( 60 )
199		MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
200		MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
201		MDRV_SCREEN_SIZE(640, 480)
202		MDRV_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
203
204		MDRV_MACHINE_START( sgi_ip6 )
205
206		MDRV_VIDEO_START(generic_bitmapped)
207		MDRV_VIDEO_UPDATE(generic_bitmapped)
208		MACHINE_DRIVER_END
209
210		ROM_START( sgi_ip6 )
211		ROM_REGION32_BE( 0x40000, "user1", 0 )
212		ROM_LOAD( "4d202031.bin", 0x000000, 0x040000, CRC(065a290a) SHA1(6f5738e79643f94901e6efe3612468d14177f65b) )
213		ROM_END
214
215		/*     YEAR  NAME      PARENT    COMPAT    MACHINE   INPUT     INIT      CONFIG    COMPANY   FULLNAME */
216		COMP( 1988, sgi_ip6,  0,        0,        sgi_ip6,  sgi_ip6,  sgi_ip6,  0, "Silicon Graphics, Inc", "4D/PI (R2000, 20MHz)", GAME_NOT_WORKING )

src/mess/drivers/sgi_ip6.c

r0	r6489
	1	/****************************************************************************
	2
	3	drivers/sgi_ip6.c
	4	SGI 4D/PI IP6 family skeleton driver
	5
	6	by Harmony
	7
	8	0x1fc00000 - 0x1fc3ffff      ROM
	9
	10	Interrupts:
	11	R2000:
	12	NYI
	13
	14	****************************************************************************/
	15
	16	#include "driver.h"
	17	#include "cpu/mips/r3000.h"
	18
	19	#define VERBOSE_LEVEL ( 0 )
	20
	21	#define ENABLE_VERBOSE_LOG (1)
	22
	23	#if ENABLE_VERBOSE_LOG
	24	INLINE void ATTR_PRINTF(3,4) verboselog( running_machine *machine, int n_level, const char *s_fmt, ... )
	25	{
	26	if( VERBOSE_LEVEL >= n_level )
	27	{
	28	va_list v;
	29	char buf[ 32768 ];
	30	va_start( v, s_fmt );
	31	vsprintf( buf, s_fmt, v );
	32	va_end( v );
	33	logerror("%08x: %s", cpu_get_pc(cputag_get_cpu(machine, "maincpu")), buf);
	34	}
	35	}
	36	#else
	37	#define verboselog(x,y,z,...)
	38	#endif
	39
	40	/***************************************************************************
	41	VIDEO HARDWARE
	42	***************************************************************************/
	43
	44	static VIDEO_START( sgi_ip6 )
	45	{
	46	}
	47
	48	static VIDEO_UPDATE( sgi_ip6 )
	49	{
	50	return 0;
	51	}
	52
	53	/***************************************************************************
	54	MACHINE FUNCTIONS
	55	***************************************************************************/
	56
	57	typedef struct
	58	{
	59	UINT16 unknown_half_0;
	60	UINT8 unknown_byte_0;
	61	UINT8 unknown_byte_1;
	62	} ip6_regs_t;
	63
	64	static ip6_regs_t ip6_regs;
	65
	66	static READ32_HANDLER( ip6_unk1_r )
	67	{
	68	UINT32 ret = 0;
	69	switch(offset)
	70	{
	71	case 0x0000/4:
	72	if(ACCESSING_BITS_16_31)
	73	{
	74	verboselog(space->machine, 0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	75	}
	76	if(ACCESSING_BITS_0_15)
	77	{
	78	verboselog(space->machine, 0, "ip6_unk1_r: Unknown Halfword 0: %08x & %08x\n", ip6_regs.unknown_half_0, mem_mask );
	79	ret |= ip6_regs.unknown_half_0;
	80	}
	81	break;
	82	default:
	83	verboselog(space->machine, 0, "ip6_unk1_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	84	break;
	85	}
	86	return ret;
	87	}
	88
	89	static WRITE32_HANDLER( ip6_unk1_w )
	90	{
	91	switch(offset)
	92	{
	93	case 0x0000/4:
	94	if(ACCESSING_BITS_16_31)
	95	{
	96	verboselog(space->machine, 0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	97	}
	98	if(ACCESSING_BITS_0_15)
	99	{
	100	verboselog(space->machine, 0, "ip6_unk1_w: Unknown Halfword 0 = %04x & %04x\n", data & 0x0000ffff, mem_mask & 0x0000ffff );
	101	ip6_regs.unknown_half_0 = data & 0x0000ffff;
	102	}
	103	break;
	104	default:
	105	verboselog(space->machine, 0, "ip6_unk1_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	106	break;
	107	}
	108	}
	109
	110	static READ32_HANDLER( ip6_unk2_r )
	111	{
	112	UINT32 ret = 0;
	113	switch(offset)
	114	{
	115	case 0x0000/4:
	116	if(!ACCESSING_BITS_24_31)
	117	{
	118	verboselog(space->machine, 0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	119	}
	120	if(ACCESSING_BITS_24_31)
	121	{
	122	verboselog(space->machine, 0, "ip6_unk2_r: Unknown Byte 0 = %02x & %02x\n", ip6_regs.unknown_byte_0, mem_mask >> 24 );
	123	ret |= ip6_regs.unknown_byte_0 << 24;
	124	}
	125	break;
	126	default:
	127	verboselog(space->machine, 0, "ip6_unk2_r: Unknown address: %08x & %08x\n", 0x1f880000 + (offset << 2), mem_mask );
	128	break;
	129	}
	130	return ret;
	131	}
	132
	133	static WRITE32_HANDLER( ip6_unk2_w )
	134	{
	135	switch(offset)
	136	{
	137	case 0x0000/4:
	138	if(!ACCESSING_BITS_24_31)
	139	{
	140	verboselog(space->machine, 0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	141	}
	142	if(ACCESSING_BITS_24_31)
	143	{
	144	verboselog(space->machine, 0, "ip6_unk2_w: Unknown Byte 0 = %02x & %02x\n", data >> 24, mem_mask >> 24 );
	145	ip6_regs.unknown_byte_0 = (data & 0xff000000) >> 24;
	146	}
	147	break;
	148	default:
	149	verboselog(space->machine, 0, "ip6_unk2_w: Unknown address: %08x = %08x & %08x\n", 0x1f880000 + (offset << 2), data, mem_mask );
	150	break;
	151	}
	152	}
	153
	154	static READ32_HANDLER(ip6_unk3_r)
	155	{
	156	UINT32 ret = 0;
	157	if(ACCESSING_BITS_16_23)
	158	{
	159	verboselog(space->machine, 0, "ip6_unk3_r: Unknown Byte 1: %02x & %02x\n", ip6_regs.unknown_byte_1, (mem_mask >> 16) & 0x000000ff);
	160	ret |= ip6_regs.unknown_byte_1 << 16;
	161	}
	162	else
	163	{
	164	verboselog(space->machine, 0, "ip6_unk3_r: Unknown address: %08x & %08x\n", 0x1fb00000 + (offset << 2), mem_mask );
	165	}
	166	return ret;
	167	}
	168
	169	static WRITE32_HANDLER(ip6_unk3_w)
	170	{
	171	verboselog(space->machine, 0, "ip6_unk3_w: Unknown address: %08x = %08x & %08x\n", 0x1fb00000 + (offset << 2), data, mem_mask );
	172	}
	173
	174	static INTERRUPT_GEN( sgi_ip6_vbl )
	175	{
	176	}
	177
	178	static MACHINE_START( sgi_ip6 )
	179	{
	180	}
	181
	182	static MACHINE_RESET( sgi_ip6 )
	183	{
	184	ip6_regs.unknown_byte_0 = 0x80;
	185	ip6_regs.unknown_byte_1 = 0x80;
	186	ip6_regs.unknown_half_0 = 0;
	187	}
	188
	189	/***************************************************************************
	190	ADDRESS MAPS
	191	***************************************************************************/
	192
	193	static ADDRESS_MAP_START( sgi_ip6_map, ADDRESS_SPACE_PROGRAM, 32 )
	194	AM_RANGE( 0x1f880000, 0x1f880003 ) AM_READWRITE(ip6_unk1_r, ip6_unk1_w)
	195	AM_RANGE( 0x1fb00000, 0x1fb00003 ) AM_READWRITE(ip6_unk3_r, ip6_unk3_w)
	196	AM_RANGE( 0x1fbc004c, 0x1fbc004f ) AM_READWRITE(ip6_unk2_r, ip6_unk2_w)
	197	AM_RANGE( 0x1fc00000, 0x1fc3ffff ) AM_ROM AM_REGION( "user1", 0 )
	198	ADDRESS_MAP_END
	199
	200	/***************************************************************************
	201	MACHINE DRIVERS
	202	***************************************************************************/
	203
	204	static const r3000_cpu_core config =
	205	{
	206	0,      /* 1 if we have an FPU, 0 otherwise */
	207	4096,   /* code cache size */
	208	4096   /* data cache size */
	209	};
	210
	211	static MACHINE_DRIVER_START( sgi_ip6 )
	212	MDRV_CPU_ADD( "maincpu", R3000BE, 20000000 ) // FIXME: Should be R2000
	213	MDRV_CPU_CONFIG( config )
	214	MDRV_CPU_PROGRAM_MAP( sgi_ip6_map )
	215	MDRV_CPU_VBLANK_INT("screen", sgi_ip6_vbl)
	216
	217	MDRV_MACHINE_RESET( sgi_ip6 )
	218
	219	/* video hardware */
	220	MDRV_SCREEN_ADD("screen", RASTER)
	221	MDRV_SCREEN_REFRESH_RATE( 60 )
	222	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
	223	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
	224	MDRV_SCREEN_SIZE(640, 480)
	225	MDRV_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
	226
	227	MDRV_MACHINE_START( sgi_ip6 )
	228
	229	MDRV_VIDEO_START(sgi_ip6)
	230	MDRV_VIDEO_UPDATE(sgi_ip6)
	231	MACHINE_DRIVER_END
	232
	233	static INPUT_PORTS_START( sgi_ip6 )
	234	PORT_START("UNUSED") // unused IN0
	235	PORT_BIT(0xffff, IP_ACTIVE_HIGH, IPT_UNUSED)
	236	INPUT_PORTS_END
	237
	238	static DRIVER_INIT( sgi_ip6 )
	239	{
	240	}
	241
	242	/***************************************************************************
	243
	244	ROM definition(s)
	245
	246	***************************************************************************/
	247
	248	ROM_START( sgi_ip6 )
	249	ROM_REGION32_BE( 0x40000, "user1", 0 )
	250	ROM_LOAD( "4d202031.bin", 0x000000, 0x040000, CRC(065a290a) SHA1(6f5738e79643f94901e6efe3612468d14177f65b) )
	251	ROM_END
	252
	253	/*     YEAR  NAME      PARENT    COMPAT    MACHINE   INPUT     INIT      CONFIG    COMPANY   FULLNAME */
	254	COMP( 1988, sgi_ip6,  0,        0,        sgi_ip6,  sgi_ip6,  sgi_ip6,  0, "Silicon Graphics, Inc", "4D/PI (R2000, 20MHz)", GAME_NOT_WORKING )

src/mess/drivers/ip22.c

r6488	r6489
1197	1197
1198	1198	nPBUS_DMA_Active = 0;
1199	1199
1200		mips3drc_set_options(cputag_get_cpu(machine, "maincpu"), MIPS3DRC_COMPATIBLE_OPTIONS);
	1200	mips3drc_set_options(cputag_get_cpu(machine, "maincpu"), MIPS3DRC_COMPATIBLE_OPTIONS | MIPS3DRC_CHECK_OVERFLOWS);
1201	1201	}
1202	1202
1203	1203	static void dump_chain(const address_space *space, UINT32 ch_base)

src/mess/drivers/sgi_ip2.c

r0	r6489
	1	/****************************************************************************
	2
	3	drivers/sgi_ip2.c
	4	SGI IRIS 3130 skeleton driver with some meat on its bones
	5
	6	by Harmony
	7
	8	0x00000000 - ?            RAM (?)
	9	0x30000000 - 0x30017fff     ROM (3x32k)
	10	0x30800000 - 0x30800000      Mouse Buttons (1)
	11	0x31000000 - 0x31000001      Mouse Quadrature (2)
	12	0x32000000 - 0x3200000f      DUART0 (?)
	13	0x32800000 - 0x3280000f      DUART1 (?)
	14	0x33000000 - 0x330007ff      SRAM (2k)
	15	0x34000000 - 0x34000000      Clock Control (1)
	16	0x35000000 - 0x35000000      Clock Data (1)
	17	0x36000000 - 0x36000000      OS Base (1)
	18	0x38000000 - 0x38000001      Status Register (2)
	19	0x39000000 - 0x39000000      Parity control (1)
	20	0x3a000000 - 0x3a000000      Multibus Protection (1)
	21	0x3b000000 - 0x3b000003      Page Table Map Base (4)
	22	0x3c000000 - 0x3c000001      Text/Data Base (2)
	23	0x3d000000 - 0x3d000001      Text/Data Limit (2)
	24	0x3e000000 - 0x3e000001      Stack Base (2)
	25	0x3f000000 - 0x3f000001      Stack Limit (2)
	26
	27	TODO:
	28	Finish incomplete MC68681 DUART emulation
	29	Hook up keyboard
	30	Hook up mouse
	31	Hook up graphics
	32	Hook up mass storage
	33
	34	Interrupts:
	35	M68K:
	36	6 - DUART
	37
	38	It is unlikely that this driver will ever be fully brought to life, as
	39	it will require the M68020 core to be updated to support having opcodes
	40	paused and resumed mid-instruction in order to service exceptions.
	41
	42	****************************************************************************/
	43
	44	#include "driver.h"
	45	#include "sound/dac.h"
	46	#include "cpu/m68000/m68000.h"
	47	#include "machine/mc146818.h" /* TOD clock */
	48	#include "machine/68681.h" /* DUART0, DUART1 */
	49
	50	#define VERBOSE_LEVEL ( 0 )
	51
	52	#define ENABLE_VERBOSE_LOG (0)
	53
	54	#if ENABLE_VERBOSE_LOG
	55	INLINE void ATTR_PRINTF(3,4) verboselog( running_machine *machine, int n_level, const char *s_fmt, ... )
	56	{
	57	if( VERBOSE_LEVEL >= n_level )
	58	{
	59	va_list v;
	60	char buf[ 32768 ];
	61	va_start( v, s_fmt );
	62	vsprintf( buf, s_fmt, v );
	63	va_end( v );
	64	logerror("%08x: %s", cpu_get_pc(cputag_get_cpu(machine, "maincpu")), buf);
	65	}
	66	}
	67	#else
	68	#define verboselog(x,y,z,...)
	69	#endif
	70
	71	/***************************************************************************
	72	VIDEO HARDWARE
	73	***************************************************************************/
	74
	75	static VIDEO_START( sgi_ip2 )
	76	{
	77	}
	78
	79	static VIDEO_UPDATE( sgi_ip2 )
	80	{
	81	return 0;
	82	}
	83
	84	/***************************************************************************
	85	MACHINE FUNCTIONS
	86	***************************************************************************/
	87
	88	#define MBUT_RIGHT      0x01   /* Right button */
	89	#define MBUT_MIDDLE      0x02   /* Middle button */
	90	#define MBUT_LEFT      0x04   /* Left button */
	91	#define BOARD_REV1      0x60   /* Board revision - #1 */
	92	#define BOARD_REV2      0x50   /* Board revision - #2 */
	93
	94	static UINT8 sgi_ip2_mbut;
	95
	96	static READ8_HANDLER(sgi_ip2_m_but_r)
	97	{
	98	verboselog(space->machine, 0, "sgi_ip2_m_but_r: %02x\n", sgi_ip2_mbut | BOARD_REV1);
	99	return sgi_ip2_mbut | BOARD_REV1;
	100	}
	101
	102	static WRITE8_HANDLER(sgi_ip2_m_but_w)
	103	{
	104	verboselog(space->machine, 0, "sgi_ip2_m_but_w: %02x\n", data);
	105	sgi_ip2_mbut = data;
	106	}
	107
	108	#define MOUSE_XFIRE      0x01   /* X Quadrature Fired, active low */
	109	#define MOUSE_XCHANGE   0x02   /* MOUSE_XCHANGE ? x-- : x++ */
	110	#define MOUSE_YFIRE      0x04   /* Y Quadrature Fired, active low */
	111	#define MOUSE_YCHANGE   0x08   /* MOUSE_YCHANGE ? y-- : y++ */
	112
	113	static UINT16 sgi_ip2_mquad;
	114
	115	static READ16_HANDLER(sgi_ip2_m_quad_r)
	116	{
	117	verboselog(space->machine, 0, "sgi_ip2_m_quad_r: %04x\n", sgi_ip2_mquad);
	118	return sgi_ip2_mquad;
	119	}
	120
	121	static WRITE16_HANDLER(sgi_ip2_m_quad_w)
	122	{
	123	verboselog(space->machine, 0, "sgi_ip2_m_quad_w = %04x & %04x\n", data, mem_mask);
	124	COMBINE_DATA(&sgi_ip2_mquad);
	125	}
	126
	127	static READ16_HANDLER(sgi_ip2_swtch_r)
	128	{
	129	verboselog(space->machine, 0, "sgi_ip2_swtch_r: %04x\n", input_port_read(space->machine, "SWTCH"));
	130	return input_port_read(space->machine, "SWTCH");
	131	}
	132
	133	static READ8_HANDLER(sgi_ip2_clock_ctl_r)
	134	{
	135	UINT8 ret = mc146818_port_r(space, 1);
	136	verboselog(space->machine, 1, "sgi_ip2_clock_ctl_r: %02x\n", ret);
	137	return ret;
	138	}
	139
	140	static WRITE8_HANDLER(sgi_ip2_clock_ctl_w)
	141	{
	142	verboselog(space->machine, 1, "sgi_ip2_clock_ctl_w: %02x\n", data);
	143	mc146818_port_w(space, 1, data);
	144	}
	145
	146	static READ8_HANDLER(sgi_ip2_clock_data_r)
	147	{
	148	UINT8 ret = mc146818_port_r(space, 0);
	149	verboselog(space->machine, 1, "sgi_ip2_clock_data_r: %02x\n", ret);
	150	return ret;
	151	}
	152
	153	static WRITE8_HANDLER(sgi_ip2_clock_data_w)
	154	{
	155	verboselog(space->machine, 1, "sgi_ip2_clock_data_w: %02x\n", data);
	156	mc146818_port_w(space, 0, data);
	157	}
	158
	159
	160	static READ8_HANDLER(sgi_ip2_os_base_r)
	161	{
	162	switch(offset)
	163	{
	164	default:
	165	verboselog(space->machine, 0, "sgi_ip2_os_base_r: Unknown Register %08x\n", 0x36000000 + offset);
	166	break;
	167	}
	168	return 0;
	169	}
	170
	171	static WRITE8_HANDLER(sgi_ip2_os_base_w)
	172	{
	173	switch(offset)
	174	{
	175	default:
	176	verboselog(space->machine, 0, "sgi_ip2_os_base_w: Unknown Register %08x = %02x\n", 0x36000000 + offset, data);
	177	break;
	178	}
	179	}
	180
	181	static READ16_HANDLER(sgi_ip2_status_r)
	182	{
	183	switch(offset)
	184	{
	185	default:
	186	verboselog(space->machine, 0, "sgi_ip2_status_r: Unknown Register %08x & %04x\n", 0x38000000 + (offset << 1), mem_mask);
	187	break;
	188	}
	189	return 0;
	190	}
	191
	192	static WRITE16_HANDLER(sgi_ip2_status_w)
	193	{
	194	switch(offset)
	195	{
	196	default:
	197	verboselog(space->machine, 0, "sgi_ip2_status_w: Unknown Register %08x = %04x & %04x\n", 0x38000000 + (offset << 1), data, mem_mask);
	198	break;
	199	}
	200	}
	201
	202	#define PAR_UR      0x01   /* Check parity on user-mode reads */
	203	#define PAR_UW      0x02   /* Check parity on user-mode writes */
	204	#define PAR_KR      0x04   /* Check parity on kernel-mode reads */
	205	#define PAR_KW      0x08   /* Check parity on kernel-mode writes */
	206	#define PAR_DIS0   0x10   /* Disable access to DUART0 and LEDs */
	207	#define PAR_DIS1   0x20   /* Disable access to DUART1 */
	208	#define PAR_MBR      0x40   /* Check parity on multibus reads */
	209	#define PAR_MBW      0x80   /* Check parity on multibus writes */
	210
	211	UINT8 sgi_ip2_parctl;
	212
	213	static READ8_HANDLER(sgi_ip2_parctl_r)
	214	{
	215	verboselog(space->machine, 0, "sgi_ip2_parctl_r: %02x\n", sgi_ip2_parctl);
	216	return sgi_ip2_parctl;
	217	}
	218
	219	static WRITE8_HANDLER(sgi_ip2_parctl_w)
	220	{
	221	verboselog(space->machine, 0, "sgi_ip2_parctl_w: %02x\n", data);
	222	sgi_ip2_parctl = data;
	223	}
	224
	225	#define MBP_DCACC   0x01   /* Display controller access (I/O page 4) */
	226	#define MBP_UCACC   0x02   /* Update controller access (I/O page 3) */
	227	#define MBP_GFACC   0x04   /* Allow GF access (I/O page 1) */
	228	#define MBP_DMACC   0x08   /* Allow GL2 DMA access (0x8nnnnn - x0bnnnnn) */
	229	#define MBP_LIOACC   0x10   /* Allow lower I/O access (0x0nnnnn - 0x7nnnnn) */
	230	#define MBP_HIOACC   0x20   /* Allow upper I/O access (0x8nnnnn - 0xfnnnnn) */
	231	#define MBP_LMACC   0x40   /* Allow lower memory access (0x0nnnnn - 0x7nnnnn) */
	232	#define MBP_HMACC   0x80   /* Allow upper memory access (0x8nnnnn - 0xfnnnnn) */
	233
	234	UINT8 sgi_ip2_mbp;
	235
	236	static READ8_HANDLER(sgi_ip2_mbp_r)
	237	{
	238	verboselog(space->machine, 0, "sgi_ip2_mbp_r: %02x\n", sgi_ip2_mbp);
	239	return sgi_ip2_mbp;
	240	}
	241
	242	static WRITE8_HANDLER(sgi_ip2_mbp_w)
	243	{
	244	verboselog(space->machine, 0, "sgi_ip2_mbp_w: %02x\n", data);
	245	sgi_ip2_mbp = data;
	246	}
	247
	248	static UINT32 *sgi_ip2_ptmap;
	249
	250	static READ32_HANDLER(sgi_ip2_ptmap_r)
	251	{
	252	verboselog(space->machine, 0, "sgi_ip2_ptmap_r: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), sgi_ip2_ptmap[offset], mem_mask);
	253	return sgi_ip2_ptmap[offset];
	254	}
	255
	256	static WRITE32_HANDLER(sgi_ip2_ptmap_w)
	257	{
	258	verboselog(space->machine, 0, "sgi_ip2_ptmap_w: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), data, mem_mask);
	259	COMBINE_DATA(&sgi_ip2_ptmap[offset]);
	260	}
	261
	262	static UINT16 sgi_ip2_tdbase;
	263
	264	static READ16_HANDLER(sgi_ip2_tdbase_r)
	265	{
	266	verboselog(space->machine, 0, "sgi_ip2_tdbase_r: %04x\n", sgi_ip2_tdbase);
	267	return sgi_ip2_tdbase;
	268	}
	269
	270	static WRITE16_HANDLER(sgi_ip2_tdbase_w)
	271	{
	272	verboselog(space->machine, 0, "sgi_ip2_tdbase_w: %04x & %04x\n", data, mem_mask);
	273	COMBINE_DATA(&sgi_ip2_tdbase);
	274	}
	275
	276	static UINT16 sgi_ip2_tdlmt;
	277
	278	static READ16_HANDLER(sgi_ip2_tdlmt_r)
	279	{
	280	verboselog(space->machine, 0, "sgi_ip2_tdlmt_r: %04x\n", sgi_ip2_tdlmt);
	281	return sgi_ip2_tdlmt;
	282	}
	283
	284	static WRITE16_HANDLER(sgi_ip2_tdlmt_w)
	285	{
	286	verboselog(space->machine, 0, "sgi_ip2_tdlmt_w: %04x & %04x\n", data, mem_mask);
	287	COMBINE_DATA(&sgi_ip2_tdlmt);
	288	}
	289
	290	static UINT16 sgi_ip2_stkbase;
	291
	292	static READ16_HANDLER(sgi_ip2_stkbase_r)
	293	{
	294	verboselog(space->machine, 0, "sgi_ip2_stkbase_r: %04x\n", sgi_ip2_stkbase);
	295	return sgi_ip2_stkbase;
	296	}
	297
	298	static WRITE16_HANDLER(sgi_ip2_stkbase_w)
	299	{
	300	verboselog(space->machine, 0, "sgi_ip2_stkbase_w: %04x & %04x\n", data, mem_mask);
	301	COMBINE_DATA(&sgi_ip2_stkbase);
	302	}
	303
	304	static UINT16 sgi_ip2_stklmt;
	305
	306	static READ16_HANDLER(sgi_ip2_stklmt_r)
	307	{
	308	verboselog(space->machine, 0, "sgi_ip2_stklmt_r: %04x\n", sgi_ip2_stklmt);
	309	return sgi_ip2_stklmt;
	310	}
	311
	312	static WRITE16_HANDLER(sgi_ip2_stklmt_w)
	313	{
	314	verboselog(space->machine, 0, "sgi_ip2_stklmt_w: %04x & %04x\n", data, mem_mask);
	315	COMBINE_DATA(&sgi_ip2_stklmt);
	316	}
	317
	318	// Ugh, god, this is a horrible, HORRIBLE hack!
	319	static INPUT_CHANGED( sgi_ip2_serial_kbd_put )
	320	{
	321	if(input_port_read(field->port->machine, "KEYS0") ||
	322	input_port_read(field->port->machine, "KEYS1") ||
	323	input_port_read(field->port->machine, "KEYS2") ||
	324	input_port_read(field->port->machine, "KEYS3") ||
	325	input_port_read(field->port->machine, "KEYS4"))
	326	{
	327	duart68681_rx_data(devtag_get_device(field->port->machine, "duart68681a"), 1, (UINT8)(FPTR)param);
	328	}
	329	}
	330
	331	static INTERRUPT_GEN( sgi_ip2_vbl )
	332	{
	333	}
	334
	335	static MACHINE_START( sgi_ip2 )
	336	{
	337	}
	338
	339	static MACHINE_RESET( sgi_ip2 )
	340	{
	341	}
	342
	343	/***************************************************************************
	344	ADDRESS MAPS
	345	***************************************************************************/
	346
	347	static UINT32 *mainram;
	348
	349	static ADDRESS_MAP_START(sgi_ip2_map, ADDRESS_SPACE_PROGRAM, 32)
	350	AM_RANGE(0x00000000, 0x000fffff) AM_RAM AM_BASE(&mainram)
	351	AM_RANGE(0x30000000, 0x30017fff) AM_ROM AM_REGION("user1", 0)
	352	AM_RANGE(0x30800000, 0x30800003) AM_READWRITE8(sgi_ip2_m_but_r,       sgi_ip2_m_but_w,       0xffffffff)
	353	AM_RANGE(0x31000000, 0x31000003) AM_READWRITE16(sgi_ip2_m_quad_r,      sgi_ip2_m_quad_w,       0xffffffff)
	354	AM_RANGE(0x31800000, 0x31800003) AM_READ16(sgi_ip2_swtch_r,                              0xffffffff)
	355	AM_RANGE(0x32000000, 0x3200000f) AM_DEVREADWRITE8("duart68681a",       duart68681_r,       duart68681_w, 0xffffffff)
	356	AM_RANGE(0x32800000, 0x3280000f) AM_DEVREADWRITE8("duart68681b",       duart68681_r,       duart68681_w, 0xffffffff)
	357	AM_RANGE(0x33000000, 0x330007ff) AM_RAM
	358	AM_RANGE(0x34000000, 0x34000003) AM_READWRITE8(sgi_ip2_clock_ctl_r,    sgi_ip2_clock_ctl_w,   0xffffffff)
	359	AM_RANGE(0x35000000, 0x35000003) AM_READWRITE8(sgi_ip2_clock_data_r,   sgi_ip2_clock_data_w,   0xffffffff)
	360	AM_RANGE(0x36000000, 0x36000003) AM_READWRITE8(sgi_ip2_os_base_r,       sgi_ip2_os_base_w,       0xffffffff)
	361	AM_RANGE(0x38000000, 0x38000003) AM_READWRITE16(sgi_ip2_status_r,       sgi_ip2_status_w,       0xffffffff)
	362	AM_RANGE(0x39000000, 0x39000003) AM_READWRITE8(sgi_ip2_parctl_r,       sgi_ip2_parctl_w,       0xffffffff)
	363	AM_RANGE(0x3a000000, 0x3a000003) AM_READWRITE8(sgi_ip2_mbp_r,          sgi_ip2_mbp_w,          0xffffffff)
	364	AM_RANGE(0x3b000000, 0x3b003fff) AM_READWRITE(sgi_ip2_ptmap_r, sgi_ip2_ptmap_w) AM_BASE(&sgi_ip2_ptmap)
	365	AM_RANGE(0x3c000000, 0x3c000003) AM_READWRITE16(sgi_ip2_tdbase_r,       sgi_ip2_tdbase_w,       0xffffffff)
	366	AM_RANGE(0x3d000000, 0x3d000003) AM_READWRITE16(sgi_ip2_tdlmt_r,       sgi_ip2_tdlmt_w,       0xffffffff)
	367	AM_RANGE(0x3e000000, 0x3e000003) AM_READWRITE16(sgi_ip2_stkbase_r,       sgi_ip2_stkbase_w,       0xffffffff)
	368	AM_RANGE(0x3f000000, 0x3f000003) AM_READWRITE16(sgi_ip2_stklmt_r,       sgi_ip2_stklmt_w,       0xffffffff)
	369	ADDRESS_MAP_END
	370
	371	/***************************************************************************
	372	MACHINE DRIVERS
	373	***************************************************************************/
	374
	375	static void duarta_irq_handler(const device_config *device, UINT8 vector)
	376	{
	377	verboselog(device->machine, 0, "duarta_irq_handler\n");
	378	cputag_set_input_line_and_vector(device->machine, "maincpu", M68K_IRQ_6, HOLD_LINE, M68K_INT_ACK_AUTOVECTOR);
	379	};
	380
	381	static UINT8 duarta_input(const device_config *device)
	382	{
	383	verboselog(device->machine, 0, "duarta_input\n");
	384	return 0;
	385	}
	386
	387	static void duarta_output(const device_config *device, UINT8 data)
	388	{
	389	verboselog(device->machine, 0, "duarta_output: RTS: %d, DTR: %d\n", data & 1, (data & 4) >> 2);
	390	}
	391
	392	static void duarta_tx(const device_config *device, int channel, UINT8 data)
	393	{
	394	verboselog(device->machine, 0, "duarta_tx: %02x\n", data);
	395	printf( "%c", data );
	396	}
	397
	398	static const duart68681_config sgi_ip2_duart68681a_config =
	399	{
	400	duarta_irq_handler,
	401	duarta_tx,
	402	duarta_input,
	403	duarta_output
	404	};
	405
	406	static void duartb_irq_handler(const device_config *device, UINT8 vector)
	407	{
	408	verboselog(device->machine, 0, "duartb_irq_handler\n");
	409	cputag_set_input_line_and_vector(device->machine, "maincpu", M68K_IRQ_6, HOLD_LINE, M68K_INT_ACK_AUTOVECTOR);
	410	};
	411
	412	static UINT8 duartb_input(const device_config *device)
	413	{
	414	verboselog(device->machine, 0, "duartb_input\n");
	415	return 0;
	416	}
	417
	418	static void duartb_output(const device_config *device, UINT8 data)
	419	{
	420	verboselog(device->machine, 0, "duartb_output: RTS: %d, DTR: %d\n", data & 1, (data & 4) >> 2);
	421	}
	422
	423	static void duartb_tx(const device_config *device, int channel, UINT8 data)
	424	{
	425	verboselog(device->machine, 0, "duartb_tx: %02x\n", data);
	426	}
	427
	428	static const duart68681_config sgi_ip2_duart68681b_config =
	429	{
	430	duartb_irq_handler,
	431	duartb_tx,
	432	duartb_input,
	433	duartb_output
	434	};
	435
	436	static MACHINE_DRIVER_START( sgi_ip2 )
	437	/* basic machine hardware */
	438	MDRV_CPU_ADD("maincpu", M68020, 16000000)
	439	MDRV_CPU_PROGRAM_MAP(sgi_ip2_map)
	440	MDRV_CPU_VBLANK_INT("screen", sgi_ip2_vbl)
	441
	442	MDRV_MACHINE_START(sgi_ip2)
	443	MDRV_MACHINE_RESET(sgi_ip2)
	444
	445	MDRV_SCREEN_ADD("screen", RASTER)
	446	MDRV_SCREEN_REFRESH_RATE(60)
	447	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
	448	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
	449	MDRV_SCREEN_SIZE(256, 256) // No this is not true, it is all a lie.  Unfortunately, 1024x1024-pixel displays are SLOOOOW.
	450	MDRV_SCREEN_VISIBLE_AREA(0, 256-1, 0, 256-1)
	451	MDRV_PALETTE_LENGTH(256)
	452
	453	MDRV_VIDEO_START(sgi_ip2)
	454	MDRV_VIDEO_UPDATE(sgi_ip2)
	455
	456	MDRV_DUART68681_ADD( "duart68681a", XTAL_3_6864MHz, sgi_ip2_duart68681a_config ) /* Y3 3.6864MHz Xtal ??? copy-over from dectalk */
	457	MDRV_DUART68681_ADD( "duart68681b", XTAL_3_6864MHz, sgi_ip2_duart68681b_config ) /* Y3 3.6864MHz Xtal ??? copy-over from dectalk */
	458	MDRV_NVRAM_HANDLER(mc146818)
	459
	460	/* sound hardware */
	461	MDRV_SPEAKER_STANDARD_MONO("mono")
	462	MDRV_SOUND_ADD( "dac", DAC, 0 )
	463	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.5)
	464	MACHINE_DRIVER_END
	465
	466	static INPUT_PORTS_START( sgi_ip2 )
	467	PORT_START("SWTCH")
	468	PORT_DIPNAME( 0x8000, 0x8000, "Master/Slave" )
	469	PORT_DIPSETTING(   0x0000, "Slave" )
	470	PORT_DIPSETTING(   0x8000, "Master" )
	471	PORT_BIT( 0x6000, IP_ACTIVE_HIGH, IPT_UNUSED )
	472	PORT_DIPNAME( 0x1800, 0x1800, "RS232 Console Speed" )
	473	PORT_DIPSETTING(   0x0000, "9600 Baud" )
	474	PORT_DIPSETTING(   0x0800, "300 Baud" )
	475	PORT_DIPSETTING(   0x1000, "1200 Baud" )
	476	PORT_DIPSETTING(   0x1800, "19200 Baud" )
	477	PORT_DIPNAME( 0x0700, 0x0000, "Display Setting" )
	478	PORT_DIPSETTING(   0x0000, "60Hz Non-Interlaced / 60Hz Non-Interlaced" )
	479	PORT_DIPSETTING(   0x0100, "60Hz Non-Interlaced / 30Hz Interlaced" )
	480	PORT_DIPSETTING(   0x0200, "60Hz Non-Interlaced / NTSC RS 170A" )
	481	PORT_DIPSETTING(   0x0300, "60Hz Non-Interlaced / PAL" )
	482	PORT_DIPSETTING(   0x0400, "30Hz Interlaced / 60Hz Non-Interlaced" )
	483	PORT_DIPSETTING(   0x0500, "30Hz Interlaced / 30Hz Interlaced" )
	484	PORT_DIPSETTING(   0x0600, "30Hz Interlaced / NTSC RS 170A" )
	485	PORT_DIPSETTING(   0x0700, "30Hz Interlaced / PAL" )
	486	PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_UNUSED )
	487	PORT_DIPNAME( 0x0040, 0x0000, "Enable Dual-Head Display" )
	488	PORT_DIPSETTING(   0x0000, "Use Primary Display" )
	489	PORT_DIPSETTING(   0x0040, "Use Secondary Display" )
	490	PORT_DIPNAME( 0x0020, 0x0000, "Verbose Boot" )
	491	PORT_DIPSETTING(   0x0000, "Be Verbose" )
	492	PORT_DIPSETTING(   0x0020, "Be Quiet" )
	493	PORT_DIPNAME( 0x0010, 0x0000, "Auto-Boot" )
	494	PORT_DIPSETTING(   0x0000, "Enter PROM Monitor" )
	495	PORT_DIPSETTING(   0x0010, "Auto-Boot" )
	496	PORT_DIPNAME( 0x000f, 0x0005, "Boot Media" )
	497	PORT_DIPSETTING(   0x0000, "Hard Disk (IP, SD, MD)" )
	498	PORT_DIPSETTING(   0x0001, "Cartridge Tape" )
	499	PORT_DIPSETTING(   0x0002, "Floppy Disk (SF, MF)" )
	500	PORT_DIPSETTING(   0x0003, "Ethernet using XNS" )
	501	PORT_DIPSETTING(   0x0005, "Enter PROM Monitor" )
	502	PORT_DIPSETTING(   0x0006, "Boot from PROM Board" )
	503	PORT_DIPSETTING(   0x0007, "TCP/UDP Netboot" )
	504	PORT_DIPSETTING(   0x0009, "Interphase SMD Disk Boot" )
	505	PORT_DIPSETTING(   0x000a, "Storager Tape Boot (1)" )
	506	PORT_DIPSETTING(   0x000b, "Storager Tape Boot (2)" )
	507	PORT_DIPSETTING(   0x000c, "Stoarger Hard Disk Boot" )
	508	PORT_DIPSETTING(   0x000d, "DSD Tape Boot (1)" )
	509	PORT_DIPSETTING(   0x000e, "DSD Tape Boot (2)" )
	510	PORT_DIPSETTING(   0x000f, "DSD Hard Disk Boot" )
	511
	512	PORT_START("KEYS0")
	513	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'a')
	514	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'b')
	515	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'c')
	516	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'d')
	517	PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'e')
	518	PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'f')
	519	PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'g')
	520	PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'h')
	521
	522	PORT_START("KEYS1")
	523	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'i')
	524	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'j')
	525	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'k')
	526	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'l')
	527	PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'m')
	528	PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'n')
	529	PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'o')
	530	PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'p')
	531
	532	PORT_START("KEYS2")
	533	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'q')
	534	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'r')
	535	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'s')
	536	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'t')
	537	PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'u')
	538	PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'v')
	539	PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'w')
	540	PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'x')
	541
	542	PORT_START("KEYS3")
	543	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'y')
	544	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')   PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'z')
	545	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0')            PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'0')
	546	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1')            PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'1')
	547	PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2')            PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'2')
	548	PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3')            PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'3')
	549	PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4')            PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'4')
	550	PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5')            PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'5')
	551
	552	PORT_START("KEYS4")
	553	PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6')            PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'6')
	554	PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7')            PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'7')
	555	PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8')            PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'8')
	556	PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9')            PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'9')
	557	PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<') PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)',')
	558	PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>') PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)'.')
	559	PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')         PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)' ')
	560	PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(0x0d)         PORT_CHANGED(sgi_ip2_serial_kbd_put, (void*)0x0d)
	561	INPUT_PORTS_END
	562
	563	static DRIVER_INIT( sgi_ip2 )
	564	{
	565	UINT32 *src = (UINT32*)memory_region(machine, "user1");
	566	UINT32 *dst = mainram;
	567	memcpy(dst, src, 8);
	568
	569	device_reset(cputag_get_cpu(machine, "maincpu"));
	570
	571	mc146818_init(machine, MC146818_IGNORE_CENTURY);
	572	}
	573
	574	/***************************************************************************
	575
	576	ROM definition(s)
	577
	578	***************************************************************************/
	579
	580	ROM_START( sgi_ip2 )
	581	ROM_REGION32_BE(0x18000, "user1", 0)
	582	ROM_LOAD( "sgi-ip2-u91.nolabel.od",    0x00000, 0x8000, CRC(32e1f6b5) SHA1(2bd928c3fe2e364b9a38189158e9bad0e5271a59) )
	583	ROM_LOAD( "sgi-ip2-u92.nolabel.od",    0x08000, 0x8000, CRC(13dbfdb3) SHA1(3361fb62f7a8c429653700bccfc3e937f7508182) )
	584	ROM_LOAD( "sgi-ip2-u93.ip2.2-008.od",  0x10000, 0x8000, CRC(bf967590) SHA1(1aac48e4f5531a25c5482f64de5cd3c7a9931f11) )
	585	ROM_END
	586
	587	/*    YEAR  NAME      PARENT    COMPAT    MACHINE  INPUT     INIT     CONFIG   COMPANY                   FULLNAME */
	588	COMP( 1985, sgi_ip2,  0,        0,        sgi_ip2, sgi_ip2,  sgi_ip2, 0,        "Silicon Graphics, Inc.", "IRIS 3130 (IP2)", GAME_NOT_WORKING )

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