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r6433 Saturday 21st November, 2009 at 22:02:46 UTC by Curt Coder
[PC8001] Text is now visible, attributes are not supported yet.
[I8257] New implementation to allow use as a memory-mapped I/O device.
[src/mess]mess.mak
[src/mess/drivers]pc8001.c
[src/mess/includes]pc8001.h
[src/mess/machine]i8257.c* i8257.h*
[src/mess/video]upd3301.c

src/mess/video/upd3301.c
r6432r6433
2727    PARAMETERS
2828***************************************************************************/
2929 
30#define LOG 1
30#define LOG 0
3131 
3232#define UPD3301_COMMAND_MASK               0xe0
3333#define UPD3301_COMMAND_RESET               0x00
r6432r6433
515515{
516516   upd3301_t *upd3301 = get_safe_token(device);
517517 
518   if (upd3301->y >= (upd3301->l * upd3301->r))
519   {
520      return;
521   }
522 
518523   if (upd3301->data_fifo_pos < upd3301->h)
519524   {
520525      upd3301->data_fifo[upd3301->data_fifo_pos][upd3301->input_fifo] = data;
r6432r6433
532537      upd3301->data_fifo_pos = 0;
533538      upd3301->attr_fifo_pos = 0;
534539      draw_row(device, upd3301->bitmap);
535   }
536540 
537   if (upd3301->y == (upd3301->l * upd3301->r))
538   {
539      /* end DMA transfer */
540      set_drq(device, 0);
541      if (upd3301->y == (upd3301->l * upd3301->r))
542      {
543         /* end DMA transfer */
544         set_drq(device, 0);
545      }
541546   }
542547}
543548 
src/mess/includes/pc8001.h
r6432r6433
2323   int vrtc;
2424   int width80;
2525   int color;
26   int dack2;
2627 
2728   /* printer state */
2829   int ack;
src/mess/machine/i8257.c
r0r6433
1/***************************************************************************
2 
3    Intel 8257 Programmable DMA Controller emulation
4 
5    Copyright Nicola Salmoria and the MAME Team.
6    Visit http://mamedev.org for licensing and usage restrictions.
7 
8***************************************************************************/
9 
10#include "driver.h"
11#include "i8257.h"
12 
13/***************************************************************************
14    CONSTANTS
15***************************************************************************/
16 
17#define LOG 0
18 
19#define I8257_STATUS_TC0   0x01
20#define I8257_STATUS_TC1   0x02
21#define I8257_STATUS_TC2   0x04
22#define I8257_STATUS_TC3   0x08
23#define I8257_STATUS_UP      0x10
24 
25#define I8257_MODE_EN0      0x01
26#define I8257_MODE_EN1      0x02
27#define I8257_MODE_EN2      0x04
28#define I8257_MODE_EN3      0x08
29#define I8257_MODE_RP      0x10
30#define I8257_MODE_EW      0x20
31#define I8257_MODE_TCS      0x40
32#define I8257_MODE_AL      0x80
33 
34enum
35{
36   STATE_SI,
37   STATE_S0,
38   STATE_S1,
39   STATE_S2,
40   STATE_S3,
41   STATE_SW,
42   STATE_SU,
43   STATE_S4
44};
45 
46enum
47{
48   MODE_VERIFY = 0,
49   MODE_WRITE,
50   MODE_READ,
51   MODE_ILLEGAL
52};
53 
54/***************************************************************************
55    TYPE DEFINITIONS
56***************************************************************************/
57 
58typedef struct _dma8257_t i8257_t;
59struct _dma8257_t
60{
61   devcb_resolved_write_line   out_hrq_func;
62   devcb_resolved_write_line   out_tc_func;
63   devcb_resolved_write_line   out_mark_func;
64   devcb_resolved_read8      in_memr_func;
65   devcb_resolved_write8      out_memw_func;
66   devcb_resolved_read8      in_ior_func;
67   devcb_resolved_write8      out_iow_func;
68   devcb_resolved_write_line   out_dack_func[4];
69 
70   /* registers */
71   UINT8 mr;               /* mode register */
72   UINT8 sr;               /* status register */
73   UINT16 ar[4];            /* address register */
74   UINT16 cr[4];            /* count register */
75   int fl;                  /* first/last flip-flop */
76 
77   /* inputs */
78   int drq[4];               /* data request */
79   int hlda;               /* hold acknowledge */
80   int ready;               /* ready */
81 
82   /* outputs */
83   int tc;                  /* terminal count */
84   int mark;               /* mark */
85 
86   /* transfer */
87   int state;               /* DMA state */
88   int channel;            /* current channel being serviced */
89   int priority;            /* highest priority channel */
90   UINT8 data;               /* DMA data */
91   UINT16 address;            /* DMA address */
92   UINT16 count;            /* DMA counter */
93   int mode;               /* DMA transfer type */
94 
95   /* timers */
96   emu_timer *dma_timer;
97};
98 
99/***************************************************************************
100    INLINE FUNCTIONS
101***************************************************************************/
102 
103INLINE i8257_t *get_safe_token(const device_config *device)
104{
105   assert(device != NULL);
106   assert(device->token != NULL);
107   assert(device->type == I8257);
108   return (i8257_t *) device->token;
109}
110 
111INLINE const i8257_interface *get_interface(const device_config *device)
112{
113   assert(device != NULL);
114   assert((device->type == I8257));
115   return (const i8257_interface *) device->static_config;
116}
117 
118/***************************************************************************
119    IMPLEMENTATION
120***************************************************************************/
121 
122static void set_hrq(const device_config *device, int state)
123{
124   i8257_t *i8257 = get_safe_token(device);
125 
126   if (LOG) logerror("I8257 '%s' Hold Request: %u\n", device->tag, state);
127 
128   devcb_call_write_line(&i8257->out_hrq_func, state);
129}
130 
131static void set_tc(const device_config *device, int state)
132{
133   i8257_t *i8257 = get_safe_token(device);
134   
135   if (i8257->tc != state)
136   {
137      if (LOG) logerror("I8257 '%s' Terminal Count: %u\n", device->tag, state);
138      i8257->tc = state;
139      devcb_call_write_line(&i8257->out_tc_func, state);
140   }
141}
142 
143static void set_mark(const device_config *device, int state)
144{
145   i8257_t *i8257 = get_safe_token(device);
146 
147   if (i8257->mark != state)
148   {
149      if (LOG) logerror("I8257 '%s' Mark: %u\n", device->tag, state);
150      i8257->mark = state;
151      devcb_call_write_line(&i8257->out_mark_func, state);
152   }
153}
154 
155static void set_dack(const device_config *device, int active_channel)
156{
157   i8257_t *i8257 = get_safe_token(device);
158   int ch;
159 
160   for (ch = 0; ch < 4; ch++)
161   {
162      int state = (ch != active_channel);
163       
164      if (LOG) logerror("I8257 '%s' DMA Acknowledge %u: %u\n", device->tag, ch, state);
165       
166      devcb_call_write_line(&i8257->out_dack_func[ch], state);
167   }
168}
169 
170static int sample_drq(const device_config *device)
171{
172   i8257_t *i8257 = get_safe_token(device);
173   int ch;
174 
175   for (ch = 0; ch < 4; ch++)
176   {
177      if (i8257->drq[ch] && BIT(i8257->mr, ch))
178      {
179         return 1;
180      }
181   }
182 
183   return 0;
184}
185 
186static void resolve_priorities(const device_config *device)
187{
188   i8257_t *i8257 = get_safe_token(device);
189   int i;
190 
191   for (i = 0; i < 4; i++)
192   {
193      int ch = (i + i8257->priority) % 4;
194 
195      if (i8257->drq[ch] && BIT(i8257->mr, ch))
196      {
197         i8257->channel = ch;
198         i8257->address = i8257->ar[ch];
199         i8257->count = i8257->cr[ch] & 0x3fff;
200         i8257->mode = i8257->cr[ch] >> 14;
201         break;
202      }
203   }
204}
205 
206static void dma_read(const device_config *device)
207{
208   i8257_t *i8257 = get_safe_token(device);
209 
210   switch (i8257->mode)
211   {
212   case MODE_VERIFY:
213      break;
214 
215   case MODE_WRITE:
216      i8257->data = devcb_call_read8(&i8257->in_memr_func, i8257->address);
217      if (LOG) logerror("I8257 '%s' DMA Memory Read %04x: %02x\n", device->tag, i8257->address, i8257->data);
218      break;
219 
220   case MODE_READ:
221      i8257->data = devcb_call_read8(&i8257->in_ior_func, i8257->address);
222      if (LOG) logerror("I8257 '%s' DMA I/O Read %04x: %02x\n", device->tag, i8257->address, i8257->data);
223      break;
224 
225   case MODE_ILLEGAL:
226      break;
227   }
228}
229 
230static void dma_write(const device_config *device)
231{
232   i8257_t *i8257 = get_safe_token(device);
233 
234   switch (i8257->mode)
235   {
236   case MODE_VERIFY:
237      break;
238 
239   case MODE_WRITE:
240      devcb_call_write8(&i8257->out_iow_func, i8257->address, i8257->data);
241      if (LOG) logerror("I8257 '%s' DMA I/O Write %04x: %02x\n", device->tag, i8257->address, i8257->data);
242      break;
243 
244   case MODE_READ:
245      devcb_call_write8(&i8257->out_memw_func, i8257->address, i8257->data);
246      if (LOG) logerror("I8257 '%s' DMA Memory Write %04x: %02x\n", device->tag, i8257->address, i8257->data);
247      break;
248 
249   case MODE_ILLEGAL:
250      break;
251   }
252}
253 
254/*-------------------------------------------------
255    TIMER_CALLBACK( dma_tick )
256-------------------------------------------------*/
257 
258static TIMER_CALLBACK( dma_tick )
259{
260   const device_config *device = (const device_config *)ptr;
261   i8257_t *i8257 = get_safe_token(device);
262   int drq = 0;
263 
264   switch (i8257->state)
265   {
266   case STATE_SI:
267      /* sample DRQn lines */
268      drq = sample_drq(device);
269 
270      /* set HRQ if DRQn = 1 */
271      if (drq)
272      {
273         set_hrq(device, 1);
274         i8257->state = STATE_S0;
275      }
276      break;
277 
278   case STATE_S0:
279      /* sample HLDA */
280      if (i8257->hlda)
281      {
282         i8257->state = STATE_S1;
283      }
284 
285      /* resolve DRQ priorities */
286      resolve_priorities(device);
287      break;
288 
289   case STATE_S1:
290      /* present and data upper address */
291      /* present lower address */
292      i8257->state = STATE_S2;
293      break;
294 
295   case STATE_S2:
296      /* activate DACKn */
297      set_dack(device, i8257->channel);
298       
299      /* activate read command */
300      dma_read(device);
301 
302      /* advanced write command */
303      if (i8257->mr & I8257_MODE_EW)
304      {
305         dma_write(device);
306      }
307 
308      i8257->state = STATE_S3;
309      break;
310 
311   case STATE_S3:
312      /* activate write command */
313      dma_write(device);
314 
315      i8257->address++;
316      i8257->count--;
317 
318      /* activate MARK */
319      switch (i8257->count & 0xff)
320      {
321      case 0:   case 0x80:
322         set_mark(device, 1);
323         break;
324      }
325 
326      /* activate TC */
327      if (i8257->count == 0)
328      {
329         set_tc(device, 1);
330      }
331 
332      if (!i8257->ready)
333      {
334         i8257->state = STATE_SW;
335      } 
336      else if (i8257->tc && (i8257->channel == 2) && (i8257->mr & I8257_MODE_AL))
337      {
338         i8257->state = STATE_SU;
339      }
340      else
341      {
342         i8257->state = STATE_S4;
343      }
344      break;
345 
346   case STATE_SW:
347      /* sample READY line */
348      if (i8257->ready)
349      {
350         if (i8257->tc && (i8257->channel == 2) && (i8257->mr & I8257_MODE_AL))
351         {
352            i8257->state = STATE_SU;
353         }
354         else
355         {
356            i8257->state = STATE_S4;
357         }
358      }
359      break;
360 
361   case STATE_SU:
362      i8257->sr |= I8257_STATUS_UP;
363 
364      /* auto load channel 2 parameters */
365      i8257->ar[2] = i8257->ar[3];
366      i8257->cr[2] = i8257->cr[3];
367 
368      i8257->state = STATE_S4;
369      break;
370 
371   case STATE_S4:
372      i8257->sr &= ~I8257_STATUS_UP;
373 
374      if (i8257->tc)
375      {
376         /* reset enable for channel n if TC stop and TC are active */
377         if ((i8257->mr & I8257_MODE_TCS) && 
378            !((i8257->channel == 2) && (i8257->mr & I8257_MODE_AL)))
379         {
380            i8257->mr &= (1 << i8257->channel);
381         }
382 
383         if (i8257->mr & I8257_MODE_RP)
384         {
385            i8257->priority = (i8257->channel + 1) % 4;
386         }
387 
388         /* resolve DRQ priorities */
389         resolve_priorities(device);
390      }
391 
392      /* deactivate DACKn, MARK and TC */
393      set_dack(device, -1);
394      set_mark(device, 0);
395      set_tc(device, 0);
396 
397      /* sample DRQn */
398      drq = sample_drq(device);
399 
400      /* reset HRQ if HLDA = 0 or DRQ = 0 */
401      if (!i8257->hlda || !drq)
402      {
403         set_hrq(device, 0);
404         i8257->state = STATE_SI;
405         timer_enable(i8257->dma_timer, 0);
406      }
407      else
408      {
409         i8257->state = STATE_S1;
410      }
411      break;
412   }
413}
414 
415READ8_DEVICE_HANDLER( i8257_r )
416{
417   i8257_t *i8257 = get_safe_token(device);
418   UINT8 data = 0;
419   int ch;
420 
421   switch (offset & 0x0f)
422   {
423   case 0:
424   case 2:
425   case 4:
426   case 6:
427      ch = offset / 2;
428 
429      if (i8257->fl)
430      {
431         data = i8257->ar[ch] >> 8;
432      }
433      else
434      {
435         data = i8257->ar[ch] & 0xff;
436      }
437 
438      i8257->fl = !i8257->fl;
439      break;
440 
441   case 1:
442   case 3:
443   case 5:
444   case 7:
445      ch = (offset - 1) / 2;
446 
447      if (i8257->fl)
448      {
449         data = i8257->cr[ch] >> 8;
450      }
451      else
452      {
453         data = i8257->cr[ch] & 0xff;
454      }
455 
456      i8257->fl = !i8257->fl;
457      break;
458 
459   case 8:
460      data = i8257->sr;
461      i8257->sr &= ~(I8257_STATUS_TC3 | I8257_STATUS_TC2 | I8257_STATUS_TC1 | I8257_STATUS_TC0);
462      break;
463   }
464 
465   return data;
466}
467 
468WRITE8_DEVICE_HANDLER( i8257_w )
469{
470   i8257_t *i8257 = get_safe_token(device);
471   int ch;
472   
473   switch (offset & 0x0f)
474   {
475   case 0:
476   case 2:
477   case 4:
478   case 6:
479      ch = offset / 2;
480 
481      if (i8257->fl)
482      {
483         i8257->ar[ch] = (data << 8) | (i8257->ar[ch] & 0xff);
484         if (LOG) logerror("I8257 '%s' Address Register %u: %04x\n", device->tag, ch, i8257->ar[ch]);
485      }
486      else
487      {
488         i8257->ar[ch] = (i8257->ar[ch] & 0xff00) | data;
489      }
490 
491      if ((i8257->mr & I8257_MODE_AL) && (ch == 2))
492      {
493         i8257->ar[3] = i8257->ar[2];
494      }
495 
496      i8257->fl = !i8257->fl;
497      break;
498 
499   case 1:
500   case 3:
501   case 5:
502   case 7:
503      ch = (offset - 1) / 2;
504 
505      if (i8257->fl)
506      {
507         i8257->cr[ch] = (data << 8) | (i8257->cr[ch] & 0xff);
508         if (LOG) logerror("I8257 '%s' Count Register %u: %04x\n", device->tag, ch, i8257->cr[ch] & 0x3fff);
509         if (LOG) logerror("I8257 '%s' Mode: %u\n", device->tag, i8257->cr[ch] >> 14);
510      }
511      else
512      {
513         i8257->cr[ch] = (i8257->cr[ch] & 0xff00) | data;
514      }
515 
516      if ((i8257->mr & I8257_MODE_AL) && (ch == 2))
517      {
518         i8257->cr[3] = i8257->cr[2];
519      }
520 
521      i8257->fl = !i8257->fl;
522      break;
523 
524   case 8:
525      i8257->mr = data;
526      i8257->fl = 0;
527 
528      if (LOG)
529      {
530         logerror("I8257 '%s' DMA Channel 0: %s\n", device->tag, BIT(i8257->mr, 0) ? "enabled" : "disabled");
531         logerror("I8257 '%s' DMA Channel 1: %s\n", device->tag, BIT(i8257->mr, 1) ? "enabled" : "disabled");
532         logerror("I8257 '%s' DMA Channel 2: %s\n", device->tag, BIT(i8257->mr, 2) ? "enabled" : "disabled");
533         logerror("I8257 '%s' DMA Channel 3: %s\n", device->tag, BIT(i8257->mr, 3) ? "enabled" : "disabled");
534         if (BIT(i8257->mr, 4)) logerror("I8257 '%s' Rotating Priority\n", device->tag);
535         if (BIT(i8257->mr, 5)) logerror("I8257 '%s' Extended Write\n", device->tag);
536         if (BIT(i8257->mr, 6)) logerror("I8257 '%s' TC Stop\n", device->tag);
537         if (BIT(i8257->mr, 7)) logerror("I8257 '%s' Auto Load\n", device->tag);
538      }
539      break;
540   }
541}
542 
543WRITE_LINE_DEVICE_HANDLER( i8257_hlda_w )
544{
545   i8257_t *i8257 = get_safe_token(device);
546 
547   i8257->hlda = state;
548 
549   if (LOG) logerror("I8257 '%s' Hold Acknowledge: %u\n", device->tag, state);
550}
551 
552WRITE_LINE_DEVICE_HANDLER( i8257_ready_w )
553{
554   i8257_t *i8257 = get_safe_token(device);
555 
556   i8257->ready = state;
557 
558   if (LOG) logerror("I8257 '%s' Ready: %u\n", device->tag, state);
559}
560 
561static void drq_w(const device_config *device, int ch, int state)
562{
563   i8257_t *i8257 = get_safe_token(device);
564 
565   i8257->drq[ch] = state;
566 
567   if (LOG) logerror("I8257 '%s' Data Request %u: %u\n", device->tag, ch, state);
568 
569   if (state)
570   {
571      timer_enable(i8257->dma_timer, 1);
572   }
573}
574 
575WRITE_LINE_DEVICE_HANDLER( i8257_drq0_w ) { drq_w(device, 0, state); }
576WRITE_LINE_DEVICE_HANDLER( i8257_drq1_w ) { drq_w(device, 1, state); }
577WRITE_LINE_DEVICE_HANDLER( i8257_drq2_w ) { drq_w(device, 2, state); }
578WRITE_LINE_DEVICE_HANDLER( i8257_drq3_w ) { drq_w(device, 3, state); }
579 
580/*-------------------------------------------------
581    DEVICE_START( i8257 )
582-------------------------------------------------*/
583 
584static DEVICE_START( i8257 )
585{
586   i8257_t *i8257 = get_safe_token(device);
587   i8257_interface *intf = (i8257_interface *)device->static_config;
588 
589   /* resolve callbacks */
590   devcb_resolve_write_line(&i8257->out_hrq_func, &intf->out_hrq_func, device);
591   devcb_resolve_write_line(&i8257->out_tc_func, &intf->out_tc_func, device);
592   devcb_resolve_write_line(&i8257->out_mark_func, &intf->out_mark_func, device);
593   devcb_resolve_read8(&i8257->in_memr_func, &intf->in_memr_func, device);
594   devcb_resolve_write8(&i8257->out_memw_func, &intf->out_memw_func, device);
595   devcb_resolve_read8(&i8257->in_ior_func, &intf->in_ior_func, device);
596   devcb_resolve_write8(&i8257->out_iow_func, &intf->out_iow_func, device);
597   devcb_resolve_write_line(&i8257->out_dack_func[0], &intf->out_dack_func[0], device);
598   devcb_resolve_write_line(&i8257->out_dack_func[1], &intf->out_dack_func[1], device);
599   devcb_resolve_write_line(&i8257->out_dack_func[2], &intf->out_dack_func[2], device);
600   devcb_resolve_write_line(&i8257->out_dack_func[3], &intf->out_dack_func[3], device);
601 
602   /* create the DMA timer */
603   i8257->dma_timer = timer_alloc(device->machine, dma_tick, (void *)device);
604   timer_adjust_periodic(i8257->dma_timer, attotime_zero, 0, ATTOTIME_IN_HZ(device->clock));
605 
606   /* register for state saving */
607   state_save_register_device_item(device, 0, i8257->mr);
608   state_save_register_device_item(device, 0, i8257->sr);
609   state_save_register_device_item_array(device, 0, i8257->ar);
610   state_save_register_device_item_array(device, 0, i8257->cr);
611   state_save_register_device_item(device, 0, i8257->fl);
612   state_save_register_device_item_array(device, 0, i8257->drq);
613   state_save_register_device_item(device, 0, i8257->hlda);
614   state_save_register_device_item(device, 0, i8257->ready);
615   state_save_register_device_item(device, 0, i8257->tc);
616   state_save_register_device_item(device, 0, i8257->mark);
617   state_save_register_device_item(device, 0, i8257->state);
618   state_save_register_device_item(device, 0, i8257->channel);
619   state_save_register_device_item(device, 0, i8257->priority);
620   state_save_register_device_item(device, 0, i8257->data);
621   state_save_register_device_item(device, 0, i8257->address);
622   state_save_register_device_item(device, 0, i8257->count);
623   state_save_register_device_item(device, 0, i8257->mode);
624}
625 
626/*-------------------------------------------------
627    DEVICE_RESET( i8257 )
628-------------------------------------------------*/
629 
630static DEVICE_RESET( i8257 )
631{
632   i8257_t *i8257 = get_safe_token(device);
633 
634   i8257->fl = 0;
635   i8257->mr = 0;
636   i8257->sr = 0;
637   i8257->state = STATE_SI;
638   i8257->priority = 0;
639 
640   set_hrq(device, 0);
641   set_mark(device, 0);
642   set_tc(device, 0);
643   set_dack(device, -1);
644 
645   timer_enable(i8257->dma_timer, 0);
646}
647 
648/*-------------------------------------------------
649    DEVICE_GET_INFO( i8257 )
650-------------------------------------------------*/
651 
652DEVICE_GET_INFO( i8257 )
653{
654   switch (state)
655   {
656      /* --- the following bits of info are returned as 64-bit signed integers --- */
657      case DEVINFO_INT_TOKEN_BYTES:               info->i = sizeof(i8257_t);               break;
658      case DEVINFO_INT_INLINE_CONFIG_BYTES:         info->i = 0;                        break;
659      case DEVINFO_INT_CLASS:                     info->i = DEVICE_CLASS_PERIPHERAL;         break;
660 
661      /* --- the following bits of info are returned as pointers to data or functions --- */
662      case DEVINFO_FCT_START:                     info->start = DEVICE_START_NAME(i8257);      break;
663      case DEVINFO_FCT_STOP:                     /* Nothing */                        break;
664      case DEVINFO_FCT_RESET:                     info->reset = DEVICE_RESET_NAME(i8257);      break;
665 
666      /* --- the following bits of info are returned as NULL-terminated strings --- */
667      case DEVINFO_STR_NAME:                     strcpy(info->s, "Intel 8257");            break;
668      case DEVINFO_STR_FAMILY:                  strcpy(info->s, "Intel 8085");            break;
669      case DEVINFO_STR_VERSION:                  strcpy(info->s, "1.0");                  break;
670      case DEVINFO_STR_SOURCE_FILE:               strcpy(info->s, __FILE__);               break;
671      case DEVINFO_STR_CREDITS:                  strcpy(info->s, "Copyright MESS Team");      break;
672   }
673}
src/mess/machine/i8257.h
r0r6433
1/***************************************************************************
2 
3    Intel 8257 Programmable DMA Controller emulation
4 
5    Copyright Nicola Salmoria and the MAME Team.
6    Visit http://mamedev.org for licensing and usage restrictions.
7 
8****************************************************************************
9                            _____   _____
10                 _I/OR   1 |*    \_/     | 40  A7
11                 _I/OW   2 |             | 39  A6
12                 _MEMR   3 |             | 38  A5
13                 _MEMW   4 |             | 37  A4
14                  MARK   5 |             | 36  TC
15                 READY   6 |             | 35  A3
16                  HLDA   7 |             | 34  A2
17                 ADSTB   8 |             | 33  A1
18                   AEN   9 |             | 32  A0
19                   HRQ  10 |     8257    | 31  Vcc
20                   _CS  11 |             | 30  D0
21                   CLK  12 |             | 29  D1
22                 RESET  13 |             | 28  D2
23                _DACK2  14 |             | 27  D3
24                _DACK3  15 |             | 26  D4
25                  DRQ3  16 |             | 25  _DACK0
26                  DRQ2  17 |             | 24  _DACK1
27                  DRQ1  18 |             | 23  D5
28                  DRQ0  19 |             | 22  D6
29                   GND  20 |_____________| 21  D7
30 
31***************************************************************************/
32 
33#ifndef __I8257__
34#define __I8257__
35 
36#include "devcb.h"
37 
38/***************************************************************************
39    MACROS / CONSTANTS
40***************************************************************************/
41 
42#define I8257 DEVICE_GET_INFO_NAME(i8257)
43 
44#define MDRV_I8257_ADD(_tag, _clock, _config) \
45   MDRV_DEVICE_ADD(_tag, I8257, _clock) \
46   MDRV_DEVICE_CONFIG(_config)
47 
48#define I8257_INTERFACE(_name) \
49   const i8257_interface (_name) =
50 
51/***************************************************************************
52    TYPE DEFINITIONS
53***************************************************************************/
54 
55typedef struct _i8257_interface i8257_interface;
56struct _i8257_interface
57{
58   devcb_write_line   out_hrq_func;
59   devcb_write_line   out_tc_func;
60   devcb_write_line   out_mark_func;
61 
62   /* memory */
63   devcb_read8         in_memr_func;
64   devcb_write8      out_memw_func;
65 
66   /* I/O */
67   devcb_read8         in_ior_func;
68   devcb_write8      out_iow_func;
69 
70   /* DMA acknowledge */
71   devcb_write_line   out_dack_func[4];
72};
73 
74/***************************************************************************
75    PROTOTYPES
76***************************************************************************/
77 
78/* register access */
79READ8_DEVICE_HANDLER( i8257_r );
80WRITE8_DEVICE_HANDLER( i8257_w );
81 
82/* hold acknowledge */
83WRITE_LINE_DEVICE_HANDLER( i8257_hlda_w );
84 
85/* ready */
86WRITE_LINE_DEVICE_HANDLER( i8257_ready_w );
87 
88/* data request */
89WRITE_LINE_DEVICE_HANDLER( i8257_drq0_w );
90WRITE_LINE_DEVICE_HANDLER( i8257_drq1_w );
91WRITE_LINE_DEVICE_HANDLER( i8257_drq2_w );
92WRITE_LINE_DEVICE_HANDLER( i8257_drq3_w );
93 
94DEVICE_GET_INFO( i8257 );
95 
96#endif
src/mess/mess.mak
r6432r6433
10401040   $(MESS_VIDEO)/pc8401a.o      \
10411041   $(MESS_DRIVERS)/pc8001.o   \
10421042   $(MESS_VIDEO)/upd3301.o      \
1043   $(MESS_MACHINE)/i8257.o      \
10431044   $(MESS_DRIVERS)/pc8801.o   \
10441045   $(MESS_MACHINE)/pc8801.o   \
10451046   $(MESS_VIDEO)/pc8801.o      \
src/mess/drivers/pc8001.c
r6432r6433
2727#include "cpu/z80/z80.h"
2828#include "devices/cassette.h"
2929#include "devices/messram.h"
30#include "machine/8257dma.h"
30#include "machine/i8257.h"
3131#include "machine/ctronics.h"
3232#include "machine/i8214.h"
3333#include "machine/i8255a.h"
r6432r6433
464464
465465/* 8257 Interface */
466466
467static WRITE_LINE_DEVICE_HANDLER( hrq_w )
468{
469   /* HACK - this should be connected to the BUSREQ line of Z80 */
470   cputag_set_input_line(device->machine, Z80_TAG, INPUT_LINE_HALT, state);
471   
472   /* HACK - this should be connected to the BUSACK line of Z80 */
473   i8257_hlda_w(device, state);
474}
475
476static WRITE8_DEVICE_HANDLER( mem_w )
477{
478   pc8001_state *driver_state = device->machine->driver_data;
479
480   if (!driver_state->dack2)
481   {
482      upd3301_dack_w(driver_state->upd3301, 0, data);
483   }
484}
485
486static WRITE_LINE_DEVICE_HANDLER( dack2_w )
487{
488   pc8001_state *driver_state = device->machine->driver_data;
489
490   driver_state->dack2 = state;
491}
492
467493static I8257_INTERFACE( pc8001_8257_intf )
468494{
469   DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_HALT),
495   DEVCB_LINE(hrq_w),
470496   DEVCB_NULL,
471497   DEVCB_NULL,
498   DEVCB_NULL,
499   DEVCB_HANDLER(mem_w),
472500   DEVCB_MEMORY_HANDLER(Z80_TAG, PROGRAM, memory_read_byte),
473501   DEVCB_MEMORY_HANDLER(Z80_TAG, PROGRAM, memory_write_byte),
474   { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
475   { DEVCB_NULL, DEVCB_NULL, DEVCB_DEVICE_HANDLER(UPD3301_TAG, upd3301_dack_w), DEVCB_NULL }
502   { DEVCB_NULL, DEVCB_NULL, DEVCB_LINE(dack2_w), DEVCB_NULL }
476503};
477504
478505/* uPD1990A Interface */
r6432r6433
530557   upd1990a_cs_w(state->upd1990a, 1);
531558   upd1990a_oe_w(state->upd1990a, 1);
532559
560   /* initialize DMA */
561   i8257_ready_w(state->i8257, 1);
562
533563   /* setup memory banking */
534564   memory_configure_bank(machine, 1, 1, 1, memory_region(machine, "n80"), 0);
535565   memory_install_readwrite8_handler(program, 0x0000, 0x5fff, 0, 0, SMH_BANK(1), SMH_UNMAP);

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