src/emu/cpu/mips/mips3drc.c
| r6396 | r6397 | |
|---|
| 1157 | 1157 | |
| 1158 | 1158 | if (exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE) |
| 1159 | 1159 | { |
| 1160 | offset = 0x000; |
| 1160 | 1161 | /* set the upper bits of EntryHi and the lower bits of Context to the fault page */ |
| 1161 | 1162 | UML_ROLINS(block, CPR032(COP0_EntryHi), IREG(0), IMM(0), IMM(0xffffe000)); // rolins [EntryHi],i0,0,0xffffe000 |
| 1162 | | UML_ROLINS(block, CPR032(COP0_Context), IREG(0), IMM(32-9), IMM(0x7fffff)); // rolins [Context],i0,32-9,0x7fffff |
| 1163 | UML_ROLINS(block, CPR032(COP0_Context), IREG(0), IMM(32-9), IMM(0x7ffff0)); // rolins [Context],i0,32-9,0x7fffff |
| 1163 | 1164 | } |
| 1164 | 1165 | |
| 1165 | 1166 | /* set the EPC and Cause registers */ |