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r5664 Thursday 10th September, 2009 at 05:46:43 UTC by Jonathan Gevaryahu
[dectalk] update debug printfs further; update nvram initial image (still fails check due to missing checksum); add some more comments by leeeeee
[src/mess/drivers]dectalk.c

src/mess/drivers/dectalk.c
r5663r5664
1212*
1313*  TODO:
1414*  * DUART:
15*    * DUART needs to be reset on reset line activation. as is it works ok, but it should be done anyway.
1516*    * DUART needs its i/o pins connected as well:   
1617*    * pins IP0, IP2, and IP3 are connected to the primary serial port:
1718*      * IP0 is CTS
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7576   111              disconnecting (start of state 7)
7677*    Dectalk dtc-01 hardware and rom version history, from dtc-01 schematic at bitsavers and with additional info from
7778     http://americanhistory.si.edu/archives/speechsynthesis/ss_dec1.htm
78     August 1983: Hardware version A done
79     unknown date: Version 1.0 roms finalized
80     unknown date: Version 1.1 roms released to fix a bug with insufficient stack space, see ss_dec1 above
81     March 1984: Hardware version B done (integrates the output fifo sync error check onto the pcb; Version A units are retrofitted when sent in for firmware upgrades) (most of the schematics come from this time)
79*    August 1983: Hardware version A done
80*    unknown date: Version 1.0 roms finalized
81*    unknown date: Version 1.1 roms released to fix a bug with insufficient stack space, see ss_dec1 above
82*    March 1984: Hardware version B done (integrates the output fifo sync error check onto the pcb; Version A units are retrofitted when sent in for firmware upgrades) (most of the schematics come from this time)
8283     <there might be a v1.2 or v1.3 in this period>
83     July 02 1984: Second half of Version 2.0 rom finalized
84     July 23 1984: First half of Version 2.0 rom finalized
85     October 1984 (the rest of the schematics come from this time)
86     unknown date: version 2.1 rom finalized
87
84*    July 02 1984: Second half of Version 2.0 rom finalized
85*    July 23 1984: First half of Version 2.0 rom finalized
86*    October 1984 (the rest of the schematics come from this time)
87*    unknown date: version 2.1 rom finalized
88*
89* NVRAM related stuff found by leeeeee:
90* $10402 - nvram recall/reset based on byte on stack (0 = recall, 1 = write default to nvram)
91* $10f2E - nvram recall
92* $10f52 - entry point for nvram check routine
93* $11004(entry point)-$11030, $11032-$111B4 - nvram store routine
94* $1a7ae - default nvram image, without checksum (0x80 bytes)
8895*******************************************************************************/
8996/*the 68k memory map is such:
90970x000000-0x007fff: E22 low, E8 high
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117124*/
118125// USE_LOOSE_TIMING makes the cpu interleave much lower and boosts it on fifo and flag writes by the 68k and semaphore sets by the dsp
119126#define USE_LOOSE_TIMING 1
120#undef VERBOSE
127// generic logs like nvram store/recall flag messages and led state, and common writes for dsp and spc such as the speech int
128#undef VERBOSE
129// logs reads and writes to nvram
130#undef NVRAM_LOG
131// logs reads and writes to TLC regs
132#undef TLC_LOG
133// logs reads and writes to SPC regs, 68k side only
134#undef SPC_LOG_68K
135// logs reads and writes to SPC regs, dsp side only
136#undef SPC_LOG_DSP
137// logs txd and related serial lines to stderr
121138#undef SERIAL_TO_STDERR
122139
123140/* Core includes */
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227244   int i;
228245   for (i = 0; i < 256; i++)
229246   nvram[i] = dectalk.nvram_local[i];
247#ifdef VERBOSE
230248   logerror("nvram store done\n");
249#endif
231250}
232251
233252static void dectalk_x2212_recall( running_machine *machine )
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236255   int i;
237256   for (i = 0; i < 256; i++)
238257   dectalk.nvram_local[i] = nvram[i];
258#ifdef VERBOSE
239259   logerror("nvram recall done\n");
260#endif
240261}
241262
242263// helper for dsp infifo_semaphore flag to make dealing with interrupts easier
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268289   //return data; // not right but want to get it working first
269290}
270291
271/*
272static void dectalk_spcflags_write ( running_machine *machine, UINT16 data )
273{
274}
275
276static void dectalk_tlcflags_write ( running_machine *machine, UINT16 data )
277{
278}
279*/
280
281292/* Machine reset and friends: stuff that needs setting up which IS directly affected by reset */
282293static void dectalk_reset(const device_config *device)
283294{
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287298   dectalk_x2212_recall(device->machine); // nvram recall
288299   dectalk.m68k_spcflags_latch = 1; // initial status is speech reset(d0) active and spc int(d6) disabled
289300   dectalk.m68k_tlcflags_latch = 0; // initial status is tone detect int(d6) off, answer phone(d8) off, ring detect int(d14) off
290   // DUART is reset, write me "duart68681"
301   // TODO: DUART is reset, "duart68681"
291302   // stuff that is INDIRECTLY affected by the RESET line
292303   dectalk_clear_all_fifos(device->machine); // speech reset clears the fifos, though we have to do it explicitly here since we're not actually in the m68k_spcflags_w function.
293   dectalk_semaphore_w(device->machine, 0);
294   //dectalk.infifo_semaphore = 0; // on the original dectalk pcb revision, this is a semaphore for the INPUT fifo, later dec hacked on a check for the 3 output fifo chips to see if they're in sync, and set both of these latches if true.
304   dectalk_semaphore_w(device->machine, 0); // on the original dectalk pcb revision, this is a semaphore for the INPUT fifo, later dec hacked on a check for the 3 output fifo chips to see if they're in sync, and set both of these latches if true.
295305   dectalk.spc_error_latch = 0; // spc error latch is cleared on /reset
296306   cputag_set_input_line(device->machine, "dsp", INPUT_LINE_RESET, ASSERT_LINE); // speech reset forces the CLR line active on the tms32010
297307   dectalk.tlc_tonedetect = 0; // TODO, needed for selftest pass
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323333      dectalk_x2212_recall(space->machine);
324334   }
325335   */
326   data = dectalk.nvram_local[(offset>>1)&0xff]<<8; // TODO: should this be before or after a possible /RECALL? I'm guessing before.
336   data = dectalk.nvram_local[offset&0xff]<<8; // TODO: should this be before or after a possible /RECALL? I'm guessing before.
337#ifdef NVRAM_LOG
338      logerror("m68k: nvram read at %08X: %02X\n", offset, (data&0xfF00)>>8);
339#endif
327340   if (ACCESSING_BITS_8_15) // X2212 NVRAM chip
328341   {
329342      if (offset&0x200) // if a9 is set, do a /RECALL
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345358   }
346359   else if (ACCESSING_BITS_8_15) // X2212 NVRAM chip
347360   {
348      dectalk.nvram_local[(offset>>1)&0xff] = (UINT8)((data&0xF00)>>8); // TODO: should this be before or after a possible /STORE? I'm guessing before.
361#ifdef NVRAM_LOG
362      logerror("m68k: nvram write at %08X: %02X\n", offset, (data&0xFf00)>>8);
363#endif
364      dectalk.nvram_local[offset&0xff] = (UINT8)((data&0xF00)>>8); // TODO: should this be before or after a possible /STORE? I'm guessing before.
349365      if (offset&0x200) // if a9 is set, do a /STORE
350366      dectalk_x2212_store(space->machine);
351367   }
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356372#ifdef USE_LOOSE_TIMING
357373   cpuexec_boost_interleave(space->machine, attotime_zero, ATTOTIME_IN_USEC(25));
358374#endif
359#ifdef VERBOSE
375#ifdef SPC_LOG_68K
360376   logerror("m68k: SPC infifo written with data = %04X, fifo head was: %02X; fifo tail: %02X\n",data, dectalk.infifo_head_ptr, dectalk.infifo_tail_ptr);
361377#endif
362378   // if fifo is full (head ptr = tail ptr-1), do not increment the head ptr and do not store the data
363379   if (((dectalk.infifo_tail_ptr-1)&0x1F) == dectalk.infifo_head_ptr)
364380   {
365#ifdef VERBOSE
381#ifdef SPC_LOG_68K
366382      logerror("infifo was full, write ignored!\n");
367383#endif
368384      return;
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378394   data |= dectalk.m68k_spcflags_latch; // bits 0 and 6
379395   data |= dectalk.spc_error_latch<<5; // bit 5
380396   data |= dectalk.infifo_semaphore<<7; // bit 7
381#ifdef VERBOSE
397#ifdef SPC_LOG_68K
382398   logerror("m68k: SPC flags read, returning data = %04X\n",data);
383399#endif
384400   return data;
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389405#ifdef USE_LOOSE_TIMING
390406   cpuexec_boost_interleave(space->machine, attotime_zero, ATTOTIME_IN_USEC(25));
391407#endif
392#ifdef VERBOSE
408#ifdef SPC_LOG_68K
393409   logerror("m68k: SPC flags written with %04X, only storing %04X\n",data, data&0x41);
394410#endif
395411   dectalk.m68k_spcflags_latch = data&0x41; // ONLY store bits 6 and 0!
396412   // d0: initialize speech flag (reset tms32010 and clear infifo and outfifo if high)
397413   if ((data&0x1) == 0x1) // bit 0
398414   {
399#ifdef VERBOSE
415#ifdef SPC_LOG_68K
400416      logerror(" | 0x01: initialize speech: fifos reset, clear error+semaphore latches and dsp reset\n");
401417#endif
402418      dectalk_clear_all_fifos(space->machine);
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407423   }
408424   else // (data&0x1) == 0
409425   {
410#ifdef VERBOSE
426#ifdef SPC_LOG_68K
411427      logerror(" | 0x01 = 0: initialize speech off, dsp running\n");
412428#endif
413429      cputag_set_input_line(space->machine, "dsp", INPUT_LINE_RESET, CLEAR_LINE); // speech reset deassert clears the CLR line on the tms32010
414430   }
415431   if ((data&0x2) == 0x2) // bit 1 - clear error and semaphore latches
416432   {
417#ifdef VERBOSE
433#ifdef SPC_LOG_68K
418434      logerror(" | 0x02: clear error+semaphore latches\n");
419435#endif
420436      // clear the two speech side latches
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423439   }
424440   if ((data&0x40) == 0x40) // bit 6 - spc irq enable
425441   {
426#ifdef VERBOSE
442#ifdef SPC_LOG_68K
427443      logerror(" | 0x40: speech int enabled\n");
428444#endif
429445      if ((dectalk.infifo_semaphore == 1))
430446      {
431#ifdef VERBOSE
447#ifdef SPC_LOG_68K
432448         logerror("    speech int fired!\n");
433449#endif
434450         cputag_set_input_line_and_vector(space->machine, "maincpu", M68K_IRQ_5, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR); // set int because semaphore was set
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436452   }
437453   else // data&0x40 == 0
438454   {
439#ifdef VERBOSE
455#ifdef SPC_LOG_68K
440456      logerror(" | 0x40 = 0: speech int disabled\n");
441457#endif
442458      cputag_set_input_line_and_vector(space->machine, "maincpu", M68K_IRQ_5, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR); // clear int because int is now disabled
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449465   data |= dectalk.m68k_tlcflags_latch; // bits 6, 8, 14;
450466   data |= dectalk.tlc_tonedetect<<7; // bit 7 is tone detect
451467   data |= dectalk.tlc_ringdetect<<14; // bit 15 is ring detect
452#ifdef VERBOSE
468#ifdef TLC_LOG
453469   logerror("m68k: TLC flags read, returning data = %04X\n",data);
454470#endif
455471   return data;
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457473
458474WRITE16_HANDLER( m68k_tlcflags_w ) // dtmf flags write
459475{
460#ifdef VERBOSE
476#ifdef TLC_LOG
461477   logerror("m68k: TLC flags written with %04X, only storing %04X\n",data, data&0x4140);
462478#endif
463479   dectalk.m68k_tlcflags_latch = data&0x4140; // ONLY store bits 6 8 and 14!
464480   if ((data&0x40) == 0x40) // bit 6: tone detect interrupt enable
465481   {
466#ifdef VERBOSE
482#ifdef TLC_LOG
467483      logerror(" | 0x40: tone detect int enabled\n");
468484#endif
469485      if ((dectalk.tlc_tonedetect == 1))
470486      {
471#ifdef VERBOSE
487#ifdef TLC_LOG
472488         logerror("    TLC int fired!\n");
473489#endif
474490         cputag_set_input_line_and_vector(space->machine, "maincpu", M68K_IRQ_4, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR); // set int because tone detect was set
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476492   }
477493   else // data&0x40 == 0
478494   {
479#ifdef VERBOSE
495#ifdef TLC_LOG
480496      logerror(" | 0x40 = 0: tone detect int disabled\n");
481497#endif
482498   if (((data&0x4000)!=0x4000) || (dectalk.tlc_ringdetect == 0)) // check to be sure we don't disable int if both ints fired at once
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484500   }
485501   if ((data&0x100) == 0x100) // bit 8: answer phone relay enable
486502   {
487#ifdef VERBOSE
503#ifdef TLC_LOG
488504      logerror(" | 0x100: answer phone relay enabled\n");
489505#endif
490506   }
491507   else // data&0x100 == 0
492508   {
493#ifdef VERBOSE
509#ifdef TLC_LOG
494510      logerror(" | 0x100 = 0: answer phone relay disabled\n");
495511#endif
496512   }
497513   if ((data&0x4000) == 0x4000) // bit 14: ring int enable
498514   {
499#ifdef VERBOSE
515#ifdef TLC_LOG
500516      logerror(" | 0x4000: ring detect int enabled\n");
501517#endif
502518      if ((dectalk.tlc_ringdetect == 1))
503519      {
504#ifdef VERBOSE
520#ifdef TLC_LOG
505521         logerror("    TLC int fired!\n");
506522#endif
507523         cputag_set_input_line_and_vector(space->machine, "maincpu", M68K_IRQ_4, ASSERT_LINE, M68K_INT_ACK_AUTOVECTOR); // set int because tone detect was set
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509525   }
510526   else // data&0x4000 == 0
511527   {
512#ifdef VERBOSE
528#ifdef TLC_LOG
513529      logerror(" | 0x4000 = 0: ring detect int disabled\n");
514530#endif
515531   if (((data&0x40)!=0x40) || (dectalk.tlc_tonedetect == 0)) // check to be sure we don't disable int if both ints fired at once
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521537{
522538   UINT16 data = 0xFFFF;
523539   data = dectalk.tlc_dtmf&0xF;
524#ifdef VERBOSE
540#ifdef TLC_LOG
525541   logerror("m68k: TLC dtmf detector read, returning data = %02X", data);
526542#endif
527543   return 0;
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534550#ifdef USE_LOOSE_TIMING
535551   cpuexec_boost_interleave(space->machine, attotime_zero, ATTOTIME_IN_USEC(25));
536552#endif
537#ifdef VERBOSE
553#ifdef SPC_LOG_DSP
538554   logerror("dsp: set fifo semaphore and set error status = %01X\n",data&1);
539555#endif
540556   dectalk_semaphore_w(space->machine, (~dectalk.simulate_outfifo_error)&1); // always set to 1 here, unless outfifo error.
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545561{
546562   UINT16 data = 0xFFFF;
547563   data = dectalk.infifo[dectalk.infifo_tail_ptr];
548#ifdef VERBOSE
564#ifdef SPC_LOG_DSP
549565   logerror("dsp: SPC infifo read with data = %04X, fifo head: %02X; fifo tail was: %02X\n",data, dectalk.infifo_head_ptr, dectalk.infifo_tail_ptr);
550566#endif
551567   // if fifo is empty (tail ptr == head ptr), do not increment the tail ptr, otherwise do.
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558574WRITE16_HANDLER( spc_outfifo_data_w )
559575{
560576   // the low 4 data bits are thrown out on the real unit due to use of a 12 bit dac (and to save use of another 16x4 fifo chip), though technically they're probably valid, and with suitable hacking a dtc-01 could probably output full 16 bit samples at 10khz.
561#ifdef VERBOSE
577#ifdef SPC_LOG_DSP
562578   logerror("dsp: SPC outfifo write, data = %04X, fifo head was: %02X; fifo tail: %02X\n", data, dectalk.outfifo_head_ptr, dectalk.outfifo_tail_ptr);
563579#endif
564580   cputag_set_input_line(space->machine, "dsp", 0, CLEAR_LINE); //TMS32010 INT (cleared because LDCK inverts the IR line, clearing int on any outfifo write... for a moment at least.)
565581   // if fifo is full (head ptr = tail ptr-1), do not increment the head ptr and do not store the data
566582   if (((dectalk.outfifo_tail_ptr-1)&0xF) == dectalk.outfifo_head_ptr)
567583   {
568#ifdef VERBOSE
584#ifdef SPC_LOG_DSP
569585      logerror("outfifo was full, write ignored!\n");
570586#endif
571587      return;
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578594
579595READ16_HANDLER( spc_semaphore_r ) // Return state of d-latch 74ls74 @ E64 'lower half' in d0 which indicates whether infifo is readable
580596{
581#ifdef VERBOSE
597#ifdef SPC_LOG_DSP
582598   //logerror("dsp: read infifo semaphore, returned %d\n", dectalk.infifo_semaphore); // commented due to extreme annoyance factor
583599   if (!dectalk.infifo_semaphore) logerror("dsp: read infifo semaphore, returned %d\n", dectalk.infifo_semaphore);
584600#endif
r5663r5664
747763   ROM_LOAD16_BYTE("lm8506205f4.e70", 0x000, 0x800, CRC(ed76a3ad) SHA1(3136bae243ef48721e21c66fde70dab5fc3c21d0)) // Label: "LM8506205F4 // M1-76161-5" @ E70
748764   ROM_LOAD16_BYTE("lm8504204f4.e69", 0x001, 0x800, CRC(79bb54ff) SHA1(9409f90f7a397b041e4440341f2d7934cb479285)) // Label: "LM8504204F4 // 78S191" @ E69
749765
750   ROM_REGION(0x100,"nvram", 0)
751   ROM_FILL(0x00, 0x100, 0xa5) /* fill with crap for now */
766   ROM_REGION(0x100,"nvram", 0) // default nvram image is at 0x1A7AE in main rom, read lsn first so 0x0005 in rom becomes 0x50 0x00, etc for all words of main rom
767   ROM_FILL(0x00, 0x01, 0x50) // 0005
768   ROM_FILL(0x01, 0x01, 0x00)
769   ROM_FILL(0x02, 0x01, 0x00) // 0000
770   ROM_FILL(0x03, 0x01, 0x00)
771   ROM_FILL(0x04, 0x01, 0x60) // 0006
772   ROM_FILL(0x05, 0x01, 0x00)
773   ROM_FILL(0x06, 0x01, 0x10) // 0001
774   ROM_FILL(0x07, 0x01, 0x00)
775   ROM_FILL(0x08, 0x01, 0x60) // 0006
776   ROM_FILL(0x09, 0x01, 0x00)
777   ROM_FILL(0x0A, 0x01, 0xB0) // 000B
778   ROM_FILL(0x0B, 0x01, 0x00)
779   ROM_FILL(0x0C, 0x01, 0x20) // 0002
780   ROM_FILL(0x0D, 0x01, 0x00)
781   ROM_FILL(0x0E, 0x01, 0x20) // 0002
782   ROM_FILL(0x0F, 0x01, 0x00)
783   ROM_FILL(0x10, 0x01, 0x10) // 0001
784   ROM_FILL(0x11, 0x01, 0x00)
785   ROM_FILL(0x12, 0x01, 0x10) // 0001
786   ROM_FILL(0x13, 0x01, 0x00)
787   ROM_FILL(0x14, 0x01, 0x00) // 0000
788   ROM_FILL(0x15, 0x01, 0x00)
789   ROM_FILL(0x16, 0x01, 0x10) // 0001
790   ROM_FILL(0x17, 0x01, 0x00)
791   ROM_FILL(0x18, 0xE4, 0x00) // rest is 0s except for checksum
792   ROM_FILL(0xFE, 0x01, 0x00) // 0000 for now, probably wrong
793   ROM_FILL(0xFF, 0x01, 0x00)
752794
753795ROM_END
754796

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