MESS SVN History

15994 Revisions

r5535 Sunday 30th August, 2009 at 04:59:32 UTC by Nathan Woods
Updated to MAME 0.133u4 core

[ROOT]	makefile
[docs]	messnew.txt
[src/emu]	emu.mak inptport.h inpttype.h
[src/emu/cpu]	cpu.mak x86log.c
[src/emu/cpu/arm]	arm.c armdasm.c
[src/emu/cpu/arm7]	arm7.c arm7dasm.c
[src/emu/cpu/cubeqcpu]	cubedasm.c* cubeqcpu.c
[src/emu/cpu/dsp32]	dsp32.c dsp32dis.c
[src/emu/cpu/e132xs]	32xsdasm.c
[src/emu/cpu/esrip]	esrip.c esripdsm.c*
[src/emu/cpu/g65816]	g65816ds.c
[src/emu/cpu/h83002]	h8_16.c h8_8.c h8disasm.c
[src/emu/cpu/i386]	i386dasm.c
[src/emu/cpu/i8085]	i8085.c
[src/emu/cpu/i960]	i960.c i960dis.c
[src/emu/cpu/jaguar]	jagdasm.c jaguar.c
[src/emu/cpu/m37710]	m7700ds.c
[src/emu/cpu/m68000]	m68kdasm.c
[src/emu/cpu/mb86233]	mb86233.c mb86233d.c
[src/emu/cpu/mips]	mips3dsm.c psxdasm.c r3000.c r3kdasm.c
[src/emu/cpu/nec]	necdasm.c
[src/emu/cpu/powerpc]	ppc_dasm.c
[src/emu/cpu/rsp]	rsp.c rsp_dasm.c
[src/emu/cpu/sh2]	sh2.c sh2dasm.c sh2drc.c
[src/emu/cpu/sh4]	sh4.c sh4dasm.c
[src/emu/cpu/sharc]	sharc.c sharcdsm.c
[src/emu/cpu/ssem]	ssem.c ssemdasm.c
[src/emu/cpu/ssp1601]	ssp1601.c ssp1601d.c
[src/emu/cpu/superfx]	sfx_dasm.c* superfx.c* superfx.h*
[src/emu/cpu/tms32031]	dis32031.c tms32031.c
[src/emu/cpu/tms57002]	57002dsm.c* tms57002.c
[src/emu/cpu/v60]	v60.c v60d.c
[src/emu/cpu/z80]	z80.c
[src/emu/cpu/z8000]	8000dasm.c
[src/emu/sound]	disc_dev.c disc_flt.c disc_inp.c disc_mth.c disc_wav.c discrete.c discrete.h
[src/emu/video]	mc6845.c
[src/mame]	mame.mak mamedriv.c
[src/mame/audio]	bzone.c dkong.c galaxian.c mario.c redalert.c tank8.c
[src/mame/drivers]	ampoker2.c bzone.c dwarfd.c goindol.c hyhoo.c kaneko16.c m79amb.c megatech.c meritm.c midtunit.c midwunit.c n8080.c namcos22.c nbmj9195.c niyanpai.c norautp.c pgm.c phoenix.c sauro.c taito_f2.c taitogn.c tiamc1.c tmaster.c toypop.c
[src/mame/includes]	bzone.h kaneko16.h midtunit.h phoenix.h snes.h taito_f2.h
[src/mame/layout]	noraut11.lay* noraut12.lay*
[src/mame/machine]	archimds.c kaneko16.c leland.c midtunit.c
[src/mame/video]	jagobj.c jaguar.c kaneko16.c leland.c phoenix.c snes.c taito_f2.c thepit.c
[src/mess]	mess.mak
[src/mess/osd/windows]	windows.mak
[src/mess/tools/messtest]	messtest.mak
[src/osd]	osdcore.h
[src/osd/osdmini]	minimisc.c
[src/osd/windows]	winmisc.c
[src/tools]	tools.mak unidasm.c*

src/mame/audio/galaxian.c
r5534	r5535
35	35	#define SOUND_CLOCK (XTAL/6/2) /* 1.536 MHz */
36	36	#define RNG_RATE (XTAL/32) / RNG clock is XTAL/32 see Aaron's note in video/galaxian.c /
37	37
38		//#define DISCRETE_BITSET(_N, _N1, _B, _OV) DISCRETE_TRANSFORM4(_N, _N1, (1 << ((_B)-1)), 0, _OV, "01&2>3*")
39
40	38	/* 74LS259 */
41	39	#define GAL_INP_BG_DAC NODE_10 /* at 9M Q4 to Q7 in schematics */
42	40
r5534	r5535
270	268	/* Pitch */
271	269	DISCRETE_INPUT_DATA(GAL_INP_PITCH)
272	270
273		/************************************************/
274		/* Background */
275		/************************************************/
	271	/* Group Background and pitch */
	272	DISCRETE_TASK_START()
	273
	274	/************************************************/
	275	/* Background */
	276	/************************************************/
	277
	278	DISCRETE_DAC_R1(NODE_100, 1, GAL_INP_BG_DAC, TTL_OUT, &galaxian_bck_dac)
	279	DISCRETE_555_CC(NODE_105, 1, NODE_100, GAL_R21, GAL_C15, 0, 0, 0, &galaxian_bck_vco)
	280	// Next is mult/add opamp circuit
	281	DISCRETE_MULTADD(NODE_110, 1, NODE_105, GAL_R33/RES_3_PARALLEL(GAL_R31,GAL_R32,GAL_R33),
	282	-5.0*GAL_R33/GAL_R31)
	283	DISCRETE_CLAMP(NODE_111,1,NODE_110,0.0,5.0,0.0)
	284	// The three 555
	285	DISCRETE_555_ASTABLE_CV(NODE_115, GAL_INP_FS1, GAL_R22, GAL_R23, GAL_C17, NODE_111, &galaxian_555_vco_desc)
	286	DISCRETE_555_ASTABLE_CV(NODE_116, GAL_INP_FS2, GAL_R25, GAL_R26, GAL_C18, NODE_111, &galaxian_555_vco_desc)
	287	DISCRETE_555_ASTABLE_CV(NODE_117, GAL_INP_FS3, GAL_R28, GAL_R29, GAL_C19, NODE_111, &galaxian_555_vco_desc)
	288
	289	DISCRETE_MIXER3(NODE_120, 1, NODE_115, NODE_116, NODE_117, &galaxian_bck_mixer_desc)
	290
	291	/************************************************/
	292	/* PITCH */
	293	/************************************************/
	294
	295	/* two cascaded LS164 which are reset to pitch latch value,
	296	* thus generating SOUND_CLOCK / (256 - pitch_clock) signal
	297	*
	298	* One possibility to implement this is
	299	* DISCRETE_TRANSFORM3(NODE_130, SOUND_CLOCK, 256, GAL_INP_PITCH, "012-/")
	300	* DISCRETE_COUNTER(NODE_132, 1, 0, NODE_130, 15, DISC_COUNT_UP, 0, DISC_CLK_IS_FREQ)
	301	* but there is a native choice:
	302	*/
	303	DISCRETE_NOTE(NODE_132, 1, SOUND_CLOCK, GAL_INP_PITCH, 255, 15, DISC_CLK_IS_FREQ)
	304
	305	/* from the 74393 (counter 2 above) only QA, QC, QD are used.
	306	* We decode three here and use SUB_NODE(133,x) below to access.
	307	*/
	308	DISCRETE_BITS_DECODE(NODE_133, NODE_132, 0, 3, TTL_OUT) /* QA-QD 74393 */
276	309
277		DISCRETE_DAC_R1(NODE_100, 1, GAL_INP_BG_DAC, TTL_OUT, &galaxian_bck_dac)
278		DISCRETE_555_CC(NODE_105, 1, NODE_100, GAL_R21, GAL_C15, 0, 0, 0, &galaxian_bck_vco)
279		// Next is mult/add opamp circuit
280		DISCRETE_MULTADD(NODE_110, 1, NODE_105, GAL_R33/RES_3_PARALLEL(GAL_R31,GAL_R32,GAL_R33),
281		-5.0*GAL_R33/GAL_R31)
282		DISCRETE_CLAMP(NODE_111,1,NODE_110,0.0,5.0,0.0)
283		// The three 555
284		DISCRETE_555_ASTABLE_CV(NODE_115, GAL_INP_FS1, GAL_R22, GAL_R23, GAL_C17, NODE_111, &galaxian_555_vco_desc)
285		DISCRETE_555_ASTABLE_CV(NODE_116, GAL_INP_FS2, GAL_R25, GAL_R26, GAL_C18, NODE_111, &galaxian_555_vco_desc)
286		DISCRETE_555_ASTABLE_CV(NODE_117, GAL_INP_FS3, GAL_R28, GAL_R29, GAL_C19, NODE_111, &galaxian_555_vco_desc)
	310	/* End of this task */
	311	DISCRETE_TASK_END5(NODE_120, NODE_SUB(133,0),NODE_SUB(133,1),NODE_SUB(133,2),NODE_SUB(133,3))
	312
	313	/* Group Hit and Fire */
287	314
288		DISCRETE_~~MIXE~~R3(~~NODE_120, 1, NODE_115, NODE_116, NODE_117, &galaxian_bck_mixer_desc~~)
	315	DISCRETE_TASK_START()
289	316
290		/************************************************/
291		/* PITCH */
292		/************************************************/
	317	/************************************************/
	318	/* HIT */
	319	/************************************************/
293	320
294		/* two cascaded LS164 which are reset to pitch latch value,
295		* thus generating SOUND_CLOCK / (256 - pitch_clock) signal
296		*
297		* One possibility to implement this is
298		* DISCRETE_TRANSFORM3(NODE_130, SOUND_CLOCK, 256, GAL_INP_PITCH, "012-/")
299		* DISCRETE_COUNTER(NODE_132, 1, 0, NODE_130, 15, DISC_COUNT_UP, 0, DISC_CLK_IS_FREQ)
300		* but there is a native choice:
301		*/
302		DISCRETE_NOTE(NODE_132, 1, SOUND_CLOCK, GAL_INP_PITCH, 255, 15, DISC_CLK_IS_FREQ)
	321	/* NOISE */
	322	/* since only a sample of the LFSR is latched @V2 we let the lfsr
	323	* run at a lower speed
	324	*/
	325	DISCRETE_LFSR_NOISE(NODE_150, 1, 1, RNG_RATE/100, 1.0, 0, 0.5, &galaxian_lfsr)
	326	DISCRETE_SQUAREWFIX(NODE_151,1,60264/2,1.0,50,0.5,0) / 2V signal */
	327	DISCRETE_LOGIC_DFLIPFLOP(NODE_152,1,1,1,NODE_151,NODE_150)
303	328
304		/* from the 74393 (counter 2 above) only QA, QC, QD are used.
305		* We decode three here and use SUB_NODE(133,x) below to access.
306		*/
307		DISCRETE_BITS_DECODE(NODE_133, NODE_132, 0, 3, TTL_OUT) /* QA-QD 74393 */
	329
	330	/* Not 100% correct - switching causes high impedance input for node_157
	331	* this is not emulated */
	332	DISCRETE_RCDISC5(NODE_155, NODE_152, GAL_INP_HIT, (GAL_R35 + GAL_R36), GAL_C21)
	333	DISCRETE_OP_AMP_FILTER(NODE_157, 1, NODE_155, 0, DISC_OP_AMP_FILTER_IS_BAND_PASS_1M, &galaxian_bandpass_desc)
	334
	335	/************************************************/
	336	/* FIRE */
	337	/************************************************/
	338
	339	DISCRETE_LOGIC_INVERT(NODE_170, 1, GAL_INP_FIRE)
	340	DISCRETE_MULTIPLY(NODE_171, 1, TTL_OUT, GAL_INP_FIRE)
	341	DISCRETE_MULTIPLY(NODE_172, 1, TTL_OUT, NODE_170) // inverted
	342	DISCRETE_RCFILTER(NODE_173, 1, NODE_172, GAL_R47, GAL_C28)
	343	/* Mix noise and 163 */
	344	DISCRETE_TRANSFORM5(NODE_177, NODE_152, TTL_OUT, 1.0/GAL_R46, NODE_173, 1.0/GAL_R48,
	345	"01234*+" )
	346	//DISCRETE_MULTIPLY(NODE_174, 1, TTL_OUT, NODE_152)
	347	//DISCRETE_MULTIPLY(NODE_175, 1, 1.0/GAL_R46, NODE_174)
	348	//DISCRETE_MULTIPLY(NODE_176, 1, 1.0/GAL_R48, NODE_173)
	349	//DISCRETE_ADDER2(NODE_177, 1, NODE_175, NODE_176)
	350	DISCRETE_MULTIPLY(NODE_178, 1, RES_2_PARALLEL(GAL_R46, GAL_R48), NODE_177)
	351
	352	DISCRETE_555_ASTABLE_CV(NODE_181, 1, GAL_R44, GAL_R45, GAL_C27, NODE_178, &galaxian_555_fire_vco_desc)
	353
	354	/* 555 toggles discharge on rc discharge module */
	355	DISCRETE_RCDISC5(NODE_182, NODE_181, NODE_171, (GAL_R41), GAL_C25)
308	356
309		/************************************************/
310		/* HIT */
311		/************************************************/
	357	/* End of task */
	358	DISCRETE_TASK_END2(NODE_157, NODE_182)
312	359
313		/* NOISE */
314		/* since only a sample of the LFSR is latched @V2 we let the lfsr
315		* run at a lower speed
316		*/
317		DISCRETE_LFSR_NOISE(NODE_150, 1, 1, RNG_RATE/100, 1.0, 0, 0.5, &galaxian_lfsr)
318		DISCRETE_SQUAREWFIX(NODE_151,1,60264/2,1.0,50,0.5,0) / 2V signal */
319		DISCRETE_LOGIC_DFLIPFLOP(NODE_152,1,1,1,NODE_151,NODE_150)
320
321
322		/* Not 100% correct - switching causes high impedance input for node_157
323		* this is not emulated */
324		DISCRETE_RCDISC5(NODE_155, NODE_152, GAL_INP_HIT, (GAL_R35 + GAL_R36), GAL_C21)
325		DISCRETE_OP_AMP_FILTER(NODE_157, 1, NODE_155, 0, DISC_OP_AMP_FILTER_IS_BAND_PASS_1M, &galaxian_bandpass_desc)
326
327	360	/************************************************/
328		/* FIRE */
329		/************************************************/
330		DISCRETE_LOGIC_INVERT(NODE_160, 1, GAL_INP_FIRE)
331		DISCRETE_MULTIPLY(NODE_161, 1, TTL_OUT, GAL_INP_FIRE)
332		DISCRETE_MULTIPLY(NODE_162, 1, TTL_OUT, NODE_160) // inverted
333		DISCRETE_RCFILTER(NODE_163, 1, NODE_162, GAL_R47, GAL_C28)
334		/* Mix noise and 163 */
335		DISCRETE_TRANSFORM5(NODE_167, NODE_152, TTL_OUT, 1.0/GAL_R46, NODE_163, 1.0/GAL_R48,
336		"01234*+" )
337		//DISCRETE_MULTIPLY(NODE_164, 1, TTL_OUT, NODE_152)
338		//DISCRETE_MULTIPLY(NODE_165, 1, 1.0/GAL_R46, NODE_164)
339		//DISCRETE_MULTIPLY(NODE_166, 1, 1.0/GAL_R48, NODE_163)
340		//DISCRETE_ADDER2(NODE_167, 1, NODE_165, NODE_166)
341		DISCRETE_MULTIPLY(NODE_168, 1, RES_2_PARALLEL(GAL_R46, GAL_R48), NODE_167)
342
343		DISCRETE_555_ASTABLE_CV(NODE_171, 1, GAL_R44, GAL_R45, GAL_C27, NODE_168, &galaxian_555_fire_vco_desc)
344
345		/* 555 toggles discharge on rc discharge module */
346		DISCRETE_RCDISC5(NODE_172, NODE_171, NODE_161, (GAL_R41), GAL_C25)
347
348		/************************************************/
349	361	/* FINAL MIX */
350	362	/************************************************/
351	363
352	364	DISCRETE_MIXER5(NODE_279, 1, NODE_SUB(133,0), NODE_SUB(133,2), NODE_SUB(133,2), NODE_SUB(133,3), NODE_120, &galaxian_mixerpre_desc)
353		DISCRETE_MIXER3(NODE_280, 1, NODE_279, NODE_157, NODE_172, &galaxian_mixer_desc)
	365	DISCRETE_MIXER3(NODE_280, 1, NODE_279, NODE_157, NODE_182, &galaxian_mixer_desc)
354	366	DISCRETE_OUTPUT(NODE_280, 32767.0/5.0*5)
355	367
356	368	DISCRETE_SOUND_END
r5534	r5535
364	376	/************************************************/
365	377	DISCRETE_DELETE(NODE_279, NODE_279)
366	378	DISCRETE_REPLACE
367		DISCRETE_MIXER7(NODE_280, 1, NODE_SUB(133,0), NODE_SUB(133,2), NODE_SUB(133,2), NODE_SUB(133,3), NODE_120, NODE_157, NODE_172, &mooncrst_mixer_desc)
	379	DISCRETE_MIXER7(NODE_280, 1, NODE_SUB(133,0), NODE_SUB(133,2), NODE_SUB(133,2), NODE_SUB(133,3), NODE_120, NODE_157, NODE_182, &mooncrst_mixer_desc)
368	380	DISCRETE_SOUND_END
369	381
370	382	/*************************************

src/mame/audio/bzone.c
r5534	r5535
22	22	#include "streams.h"
23	23	#include "bzone.h"
24	24
	25	#if !BZONE_DISCRETE
25	26	#define OUTPUT_RATE (6000*4)
26	27
27	28
r5534	r5535
295	296	}
296	297	}
297	298
	299	#else
298	300
	301	#include "sound/discrete.h"
	302	#include "sound/pokey.h"
	303
	304	#define BZ_NOISE_CLOCK 12000 /* FIXME */
	305
	306	/*************************************
	307	*
	308	* Discrete Sound Defines
	309	*
	310	*************************************/
	311
	312	#define BZ_INPUT NODE_01 /* at M2 LS273 */
	313	#define BZ_INP_EXPLO NODE_SUB(10, 0)
	314	#define BZ_INP_EXPLOLS NODE_SUB(10, 1)
	315	#define BZ_INP_SHELL NODE_SUB(10, 2)
	316	#define BZ_INP_SHELLLS NODE_SUB(10, 3)
	317	#define BZ_INP_ENGREV NODE_SUB(10, 4)
	318	#define BZ_INP_SOUNDEN NODE_SUB(10, 5)
	319	#define BZ_INP_STARTLED NODE_SUB(10, 6)
	320	#define BZ_INP_MOTEN NODE_SUB(10, 7)
	321
	322	#define TTL_OUT 5
	323
	324	#define BZ_R5 RES_K(1)
	325	#define BZ_R6 RES_K(4.7)
	326	#define BZ_R7 RES_K(1)
	327	#define BZ_R8 RES_K(100)
	328	#define BZ_R9 RES_K(22)
	329
	330	//#define RT (1.0/BZ_R5 + 1.0/BZ_R6 * 1.0/BZ_R7)
	331
	332	#define BZ_R10 RES_K(100)
	333	#define BZ_R11 RES_K(250)
	334	#define BZ_R12 RES_K(33)
	335	#define BZ_R13 RES_K(10)
	336	#define BZ_R14 RES_K(22)
	337	#define BZ_R15 RES_K(1)
	338	#define BZ_R16 RES_K(1)
	339	#define BZ_R17 RES_K(22)
	340	#define BZ_R18 RES_K(10)
	341	#define BZ_R19 RES_K(33)
	342
	343	#define BZ_R20 RES_K(33)
	344	#define BZ_R21 RES_K(33)
	345	#define BZ_R25 RES_K(100)
	346	#define BZ_R26 RES_K(33)
	347	#define BZ_R27 RES_K(330)
	348	#define BZ_R28 RES_K(100)
	349	#define BZ_R29 RES_K(22)
	350
	351	#define BZ_R32 RES_K(330)
	352	#define BZ_R33 RES_K(330)
	353	#define BZ_R34 RES_K(33)
	354	#define BZ_R35 RES_K(33)
	355
	356	#define BZ_C9 CAP_U(4.7)
	357
	358	#define BZ_C11 CAP_U(0.015)
	359	#define BZ_C13 CAP_U(10)
	360	#define BZ_C14 CAP_U(10)
	361
	362	#define BZ_C21 CAP_U(0.0047)
	363	#define BZ_C22 CAP_U(0.0047)
	364	#define BZ_C29 CAP_U(0.47)
	365
	366	/*************************************
	367	*
	368	* Discrete Sound static structs
	369	*
	370	*************************************/
	371
	372
	373	static const discrete_lfsr_desc bzone_lfsr =
	374	{
	375	DISC_CLK_IS_FREQ,
	376	16, /* Bit Length */
	377	0, /* Reset Value */
	378	3, /* Use Bit 10 (QC of second LS164) as F0 input 0 */
	379	14, /* Use Bit 23 (QH of third LS164) as F0 input 1 */
	380	DISC_LFSR_XOR, /* F0 is XOR */
	381	DISC_LFSR_NOT_IN0, /* F1 is inverted F0*/
	382	DISC_LFSR_REPLACE, /* F2 replaces the shifted register contents */
	383	0x000001, /* Everything is shifted into the first bit only */
	384	DISC_LFSR_FLAG_OUTPUT_SR_SN1, /* output the complete shift register to sub node 1*/
	385	15 /* Output bit */
	386	};
	387
	388	static const discrete_op_amp_filt_info bzone_explo_0 =
	389	{
	390	BZ_R18 + BZ_R19, 0, 0, 0, /* r1, r2, r3, r4 */
	391	BZ_R33, /* rF */
	392	BZ_C22, 0, 0, /* c1, c2, c3 */
	393	0, /* vRef - not used */
	394	22, 0 /* vP, vN */
	395	};
	396
	397	static const discrete_op_amp_filt_info bzone_explo_1 =
	398	{
	399	BZ_R18, 0, 0, 0, /* r1, r2, r3, r4 */
	400	BZ_R33, /* rF */
	401	BZ_C22, 0, 0, /* c1, c2, c3 */
	402	0, /* vRef - not used */
	403	22, 0 /* vP, vN */
	404	};
	405
	406	static const discrete_op_amp_filt_info bzone_shell_0 =
	407	{
	408	BZ_R13 + BZ_R12, 0, 0, 0, /* r1, r2, r3, r4 */
	409	BZ_R32, /* rF */
	410	BZ_C21, 0, 0, /* c1, c2, c3 */
	411	0, /* vRef - not used */
	412	22, 0 /* vP, vN */
	413	};
	414
	415	static const discrete_op_amp_filt_info bzone_shell_1 =
	416	{
	417	BZ_R13, 0, 0, 0, /* r1, r2, r3, r4 */
	418	BZ_R32, /* rF */
	419	BZ_C21, 0, 0, /* c1, c2, c3 */
	420	0, /* vRef - not used */
	421	22, 0 /* vP, vN */
	422	};
	423
	424	static const discrete_555_desc bzone_vco_desc =
	425	{
	426	DISC_555_OUT_DC,
	427	5.0,
	428	DEFAULT_555_CHARGE,
	429	1.0 // Logic output
	430	};
	431
	432	static const discrete_mixer_desc bzone_eng_mixer_desc =
	433	{
	434	DISC_MIXER_IS_RESISTOR,
	435	{BZ_R20, BZ_R21, BZ_R34, BZ_R35},
	436	{0, 0, 0, 0},
	437	{0, 0, 0, 0},
	438	0, 0,
	439	BZ_C29,
	440	0, /* no out cap */
	441	0, TTL_OUT /* inputs are logic */
	442	};
	443
	444	static const discrete_mixer_desc bzone_final_mixer_desc =
	445	{
	446	DISC_MIXER_IS_RESISTOR,
	447	{BZ_R28, BZ_R25, BZ_R26, BZ_R27},
	448	{0, 0, 0, 0},
	449	{0, 0, 0, 0},
	450	0, BZ_R29,
	451	0,
	452	0, /* no out cap */
	453	0, 1
	454	};
	455
	456	/*************************************
	457	*
	458	* Discrete Sound Blocks
	459	*
	460	*************************************/
	461
	462	static DISCRETE_SOUND_START(bzone)
	463
	464	/************************************************/
	465	/* Input register mapping for galaxian */
	466	/************************************************/
	467	DISCRETE_INPUT_DATA(BZ_INPUT)
	468
	469	/* decode the bits */
	470	DISCRETE_BITS_DECODE(NODE_10, BZ_INPUT, 0, 7, 5.7)// TTL_OUT) /* QA-QD 74393 */
	471	DISCRETE_ADJUSTMENT_TAG(NODE_11, 0, RES_K(250), DISC_LINADJ, "R11")
	472
	473
	474	/************************************************/
	475	/* NOISE */
	476	/************************************************/
	477
	478	/* 12Khz clock is divided by two by B4 74LS109 */
	479	DISCRETE_LFSR_NOISE(NODE_30, 1, 1, BZ_NOISE_CLOCK / 2, 1.0, 0, 0.5, &bzone_lfsr)
	480
	481	/* divide by 2 */
	482	DISCRETE_COUNTER(NODE_31, 1, 0, NODE_30, 1, DISC_COUNT_UP, 0, DISC_CLK_ON_R_EDGE)
	483
	484	DISCRETE_BITS_DECODE(NODE_32, NODE_SUB(30,1), 11, 14, 1) /* to NAND LS20, J4 */
	485	/* 11-14 */
	486	DISCRETE_LOGIC_NAND4(NODE_33,1,NODE_SUB(32,0),NODE_SUB(32,1),NODE_SUB(32,2),NODE_SUB(32,3))
	487	/* divide by 2 */
	488	DISCRETE_COUNTER(NODE_34, 1, 0, NODE_33, 1, DISC_COUNT_UP, 0, DISC_CLK_ON_R_EDGE)
	489
	490	/************************************************/
	491	/* Explosion */
	492	/************************************************/
	493
	494	/* FIXME: +0.7 for diode */
	495	DISCRETE_RCDISC5(NODE_40, NODE_34, BZ_INP_EXPLO, BZ_R17 + BZ_R16, BZ_C14)
	496	DISCRETE_MULTIPLY(NODE_41, 1, BZ_R16 / (BZ_R17 + BZ_R16), NODE_40)
	497
	498	/* one of two filter configurations active */
	499	DISCRETE_LOGIC_INVERT(NODE_42, 1, BZ_INP_EXPLOLS)
	500	DISCRETE_OP_AMP_FILTER(NODE_43, BZ_INP_EXPLOLS, 0, NODE_41,
	501	DISC_OP_AMP_FILTER_IS_LOW_PASS_1M, &bzone_explo_1)
	502	DISCRETE_OP_AMP_FILTER(NODE_44, NODE_42, 0, NODE_41,
	503	DISC_OP_AMP_FILTER_IS_LOW_PASS_1M, &bzone_explo_0)
	504	DISCRETE_ADDER2(NODE_45, 1, NODE_43, NODE_44)
	505
	506	/************************************************/
	507	/* Shell */
	508	/************************************************/
	509	/* FIXME: +0.7 for diode */
	510	DISCRETE_RCDISC5(NODE_50, NODE_31, BZ_INP_SHELL, BZ_R14 + BZ_R15, BZ_C9)
	511	DISCRETE_MULTIPLY(NODE_51, 1, BZ_R15 / (BZ_R14 + BZ_R15), NODE_50)
	512
	513	/* one of two filter configurations active */
	514	DISCRETE_LOGIC_INVERT(NODE_52, 1, BZ_INP_SHELLLS)
	515	DISCRETE_OP_AMP_FILTER(NODE_53, BZ_INP_SHELLLS, 0, NODE_51,
	516	DISC_OP_AMP_FILTER_IS_LOW_PASS_1M, &bzone_shell_1)
	517	DISCRETE_OP_AMP_FILTER(NODE_54, NODE_52, 0, NODE_51,
	518	DISC_OP_AMP_FILTER_IS_LOW_PASS_1M, &bzone_shell_0)
	519	DISCRETE_ADDER2(NODE_55, 1, NODE_53, NODE_54)
	520
	521	/************************************************/
	522	/* Engine */
	523	/************************************************/
	524
	525
	526	DISCRETE_TRANSFORM2(NODE_60, BZ_INP_ENGREV, 0.0, "01=")
	527	// FIXME: from R5 .. R7
	528	DISCRETE_MULTIPLEX2(NODE_61, 1, NODE_60, 2.5, 4.2)
	529	DISCRETE_RCDISC3(NODE_62, 1, NODE_61, BZ_R8, BZ_R9, BZ_C13, -0.5)
	530
	531	/* R11 taken from adjuster port */
	532	DISCRETE_555_ASTABLE_CV(NODE_63, 1, BZ_R10, NODE_11, BZ_C11, NODE_62, &bzone_vco_desc)
	533
	534	/* two LS161, reset to 4 resp 6 counting up to 15, QD and ripple carry mixed */
	535	DISCRETE_COUNTER(NODE_65, BZ_INP_MOTEN, 0, NODE_63, 11, DISC_COUNT_UP, 0, DISC_CLK_ON_R_EDGE)
	536	DISCRETE_TRANSFORM2(NODE_66, NODE_65, 3, "01>") /* QD */
	537	DISCRETE_TRANSFORM2(NODE_67, NODE_65, 11, "01=") /* Ripple */
	538
	539	DISCRETE_COUNTER(NODE_68, BZ_INP_MOTEN, 0, NODE_63, 9, DISC_COUNT_UP, 0, DISC_CLK_ON_R_EDGE)
	540	DISCRETE_TRANSFORM2(NODE_69, NODE_68, 1, "01>") /* QD */
	541	DISCRETE_TRANSFORM2(NODE_70, NODE_68, 9, "01=") /* Ripple */
	542
	543	DISCRETE_MIXER4(NODE_75, 1, NODE_66, NODE_67, NODE_69, NODE_70, &bzone_eng_mixer_desc)
	544
	545	/************************************************/
	546	/* FINAL MIX */
	547	/************************************************/
	548
	549	/* not sure about pokey output levels - bleow is just a estimate */
	550	DISCRETE_INPUTX_STREAM(NODE_85, 0, 5.0/32767.0 * 4, 0)
	551
	552	DISCRETE_MIXER4(NODE_280, 1, NODE_45, NODE_55, NODE_75, NODE_85, &bzone_final_mixer_desc)
	553	DISCRETE_OUTPUT(NODE_280, 32767.0/5.0 * 2)
	554	//DISCRETE_WAVELOG1(NODE_55, 32767.0/22)
	555	//DISCRETE_WAVELOG2(NODE_30, 32767.0/5.0, NODE_31, 32767.0/5.0)
	556
	557	DISCRETE_SOUND_END
	558
	559	static const pokey_interface bzone_pokey_interface =
	560	{
	561	{ DEVCB_NULL },
	562	DEVCB_INPUT_PORT("IN3")
	563	};
	564
	565	WRITE8_DEVICE_HANDLER( bzone_sounds_w )
	566	{
	567	discrete_sound_w(device, BZ_INPUT, data);
	568
	569	output_set_value("startled", (data >> 6) & 1);
	570	sound_global_enable(data & 0x20);
	571	}
	572
	573
	574	MACHINE_DRIVER_START( bzone_audio )
	575
	576	MDRV_SPEAKER_STANDARD_MONO("mono")
	577
	578	MDRV_SOUND_ADD("pokey", POKEY, BZONE_MASTER_CLOCK / 8)
	579	MDRV_SOUND_CONFIG(bzone_pokey_interface)
	580	MDRV_SOUND_ROUTE_EX(0, "discrete", 1.0, 0)
	581
	582	MDRV_SOUND_ADD("discrete", DISCRETE, 0)
	583	MDRV_SOUND_CONFIG_DISCRETE(bzone)
	584
	585	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
	586	MACHINE_DRIVER_END
	587
	588	#endif

src/mame/audio/dkong.c
r5534	r5535
284	284	* Gnd Gnd
285	285	*
286	286	************************************************************************/
287		#define DKONG_CUSTOM_IN1 (*(node->input[0]))
288		#define DKONG_CUSTOM_IN2 (*(node->input[1]))
289		#define DKONG_CUSTOM_R1 (*(node->input[2]))
290		#define DKONG_CUSTOM_R2 (*(node->input[3]))
291		#define DKONG_CUSTOM_R3 (*(node->input[4]))
292		#define DKONG_CUSTOM_R4 (*(node->input[5]))
293		#define DKONG_CUSTOM_C (*(node->input[6]))
294		#define DKONG_CUSTOM_V (*(node->input[7]))
	287	#define DKONG_CUSTOM_IN1 DISCRETE_INPUT(0)
	288	#define DKONG_CUSTOM_IN2 DISCRETE_INPUT(1)
	289	#define DKONG_CUSTOM_R1 DISCRETE_INPUT(2)
	290	#define DKONG_CUSTOM_R2 DISCRETE_INPUT(3)
	291	#define DKONG_CUSTOM_R3 DISCRETE_INPUT(4)
	292	#define DKONG_CUSTOM_R4 DISCRETE_INPUT(5)
	293	#define DKONG_CUSTOM_C DISCRETE_INPUT(6)
	294	#define DKONG_CUSTOM_V DISCRETE_INPUT(7)
295	295
296	296	struct dkong_custom_mixer_context
297	297	{
r5534	r5535
343	343
344	344	static const discrete_custom_info dkong_custom_mixer_info =
345	345	{
346		DISCRETE_RESET_NAME( dkong_custom_mixer ),
347		DISCRETE_STEP_NAME( dkong_custom_mixer ),
348		sizeof(struct dkong_custom_mixer_context),
	346	DISCRETE_CUSTOM_MODULE( dkong_custom_mixer, struct dkong_custom_mixer_context),
349	347	NULL
350	348	};
351	349	#endif
352	350
	351
	352	static DISCRETE_SOUND_START(dkong2b_dac)
	353	DISCRETE_INPUT_DATA(DS_DAC)
	354	DISCRETE_OUTPUT(DS_DAC, 1)
	355	DISCRETE_SOUND_END
	356
353	357	static DISCRETE_SOUND_START(dkong2b)
354	358
355	359	/************************************************/
r5534	r5535
361	365	DISCRETE_INPUT_NOT(DS_SOUND1_INV) /* IC 6J, pin 12 */
362	366	DISCRETE_INPUT_NOT(DS_SOUND0_INV) /* IC 6J, pin 2 */
363	367	DISCRETE_INPUT_NOT(DS_DISCHARGE_INV)
364		DISCRETE_INPUT_DATA(DS_DAC)
	368	//DISCRETE_INPUT_DATA(DS_DAC)
	369
365	370	/* Mixing - DAC */
366	371	DISCRETE_ADJUSTMENT_TAG(DS_ADJ_DAC, 0, 1, DISC_LINADJ, "VR2")
367	372
r5534	r5535
369	374	/* Stomp */
370	375	/************************************************/
371	376	/* Noise */
	377	DISCRETE_TASK_START()
372	378	DISCRETE_LFSR_NOISE(NODE_11, 1, 1, CLOCK_2VF, 1.0, 0, 0.5, &dkong_lfsr)
373	379	DISCRETE_COUNTER(NODE_12, 1, 0, NODE_11, 7, DISC_COUNT_UP, 0, DISC_CLK_ON_R_EDGE) /* LS161, IC 3J */
374	380	DISCRETE_TRANSFORM3(NODE_13,NODE_12,3,DK_SUP_V,"01>2*")
r5534	r5535
384	390
385	391	DISCRETE_RCINTEGRATE(NODE_22,NODE_20,DK_R5, RES_2_PARALLEL(DK_R4+DK_R3,DK_R6),0,DK_C19,DK_SUP_V,DISC_RC_INTEGRATE_TYPE1)
386	392	DISCRETE_MULTIPLY(DS_OUT_SOUND0,1,NODE_22,DK_R3/R_SERIES(DK_R3,DK_R4))
	393	DISCRETE_TASK_END(DS_OUT_SOUND0)
387	394
388	395	/************************************************/
389	396	/* Jump */
390	397	/************************************************/
391		/* tt */
	398	/* tt */
392	399	/* 4049B Inverter Oscillator build from 3 inverters */
	400	DISCRETE_TASK_START()
393	401	DISCRETE_INVERTER_OSC(NODE_25,1,0,DK_R38,DK_R39,DK_C26,0,&dkong_inverter_osc_desc_jump)
394	402
395	403	#if DK_USE_CUSTOM
r5534	r5535
416	424
417	425	DISCRETE_RCINTEGRATE(NODE_39,NODE_38,DK_R27, RES_2_PARALLEL(DK_R28,DK_R26+DK_R25),0,DK_C16,DK_SUP_V,DISC_RC_INTEGRATE_TYPE1)
418	426	DISCRETE_MULTIPLY(DS_OUT_SOUND1,1,NODE_39,DK_R25/(DK_R26+DK_R25))
	427	DISCRETE_TASK_END(DS_OUT_SOUND1)
419	428
420	429	/************************************************/
421	430	/* Walk */
422	431	/************************************************/
	432	DISCRETE_TASK_START()
423	433	DISCRETE_INVERTER_OSC(NODE_51,1,0,DK_R47,DK_R48,DK_C30,0,&dkong_inverter_osc_desc_walk)
424	434
425	435	#if DK_USE_CUSTOM
r5534	r5535
440	450	/* Filter and divide - omitted C22 */
441	451	DISCRETE_CRFILTER(NODE_61, 1, NODE_60, DK_R15+DK_R16, DK_C23)
442	452	DISCRETE_MULTIPLY(DS_OUT_SOUND2, 1, NODE_61, DK_R15/(DK_R15+DK_R16))
	453	DISCRETE_TASK_END(DS_OUT_SOUND2)
443	454
444	455	/************************************************/
445	456	/* DAC */
446	457	/************************************************/
447	458
	459	DISCRETE_TASK_START()
	460	DISCRETE_INPUTX_STREAM(DS_DAC, 0, 1.0, 0)
448	461	/* Signal decay circuit Q7, R20, C32 */
449	462	DISCRETE_RCDISC(NODE_70, DS_DISCHARGE_INV, 1, DK_R20, DK_C32)
450	463	DISCRETE_TRANSFORM4(NODE_71, DS_DAC, DK_SUP_V/256.0, NODE_70, DS_DISCHARGE_INV, "013!2+")
r5534	r5535
465	478	#else
466	479	DISCRETE_MULTIPLY(DS_OUT_DAC, 1, NODE_73, DS_ADJ_DAC)
467	480	#endif
	481	DISCRETE_TASK_END(DS_OUT_DAC)
468	482
469	483	/************************************************/
470	484	/* Amplifier */
r5534	r5535
623	637	DISCRETE_INPUT_NOT(DS_SOUND6_INV)
624	638	DISCRETE_INPUT_NOT(DS_SOUND7_INV)
625	639	DISCRETE_INPUT_NOT(DS_DISCHARGE_INV)
626		DISCRETE_INPUT_DATA(DS_DAC)
627	640
	641	/* Must be in task if tasks added */
	642	DISCRETE_INPUTX_STREAM(DS_DAC, 0, 1.0, 0)
	643	//DISCRETE_INPUT_DATA(DS_DAC)
	644
628	645	/* Mixing - DAC */
629	646	DISCRETE_ADJUSTMENT_TAG(DS_ADJ_DAC, 0, 1, DISC_LINADJ, "VR2")
630	647
r5534	r5535
1154	1171	AM_WRITE(dkong_voice_w)
1155	1172	AM_RANGE(MCS48_PORT_BUS, MCS48_PORT_BUS) AM_DEVREAD("ls175.3d", dkong_tune_r)
1156	1173	AM_WRITE(dkong_voice_w)
1157		AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_DEVWRITE("disc~~rete~~", dkong_p1_w) /* only write to dac */
	1174	AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_DEVWRITE("discdac", dkong_p1_w) /* only write to dac */
1158	1175	AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_LATCH8_READWRITE("virtual_p2")
1159	1176	AM_RANGE(MCS48_PORT_T0, MCS48_PORT_T0) AM_LATCH8_READBIT("ls259.6h", 5)
1160	1177	AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_LATCH8_READBIT("ls259.6h", 4)
r5534	r5535
1170	1187
1171	1188	static ADDRESS_MAP_START( radarsc1_sound_io_map, ADDRESS_SPACE_IO, 8 )
1172	1189	AM_RANGE(0x00, 0x00) AM_MIRROR(0xff) AM_DEVREAD("ls175.3d", latch8_r)
1173		AM_RANGE(0x00, 0xff) AM_DEVWRITE("disc~~rete~~", dkong_p1_w) /* DAC here */
	1190	AM_RANGE(0x00, 0xff) AM_DEVWRITE("discdac", dkong_p1_w) /* DAC here */
1174	1191	AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_LATCH8_READ("virtual_p1")
1175	1192	AM_DEVWRITE("tms", M58817_command_w)
1176	1193	AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_LATCH8_WRITE("virtual_p2")
r5534	r5535
1245	1262	MDRV_CPU_IO_MAP(dkong_sound_io_map)
1246	1263
1247	1264	MDRV_SPEAKER_STANDARD_MONO("mono")
	1265
	1266	MDRV_SOUND_ADD("discdac", DISCRETE, 0)
	1267	MDRV_SOUND_CONFIG_DISCRETE(dkong2b_dac)
	1268	MDRV_SOUND_ROUTE_EX(0, "discrete", 1.0, 0)
	1269
1248	1270	MDRV_SOUND_ADD("discrete", DISCRETE, 0)
1249	1271	MDRV_SOUND_CONFIG_DISCRETE(dkong2b)
1250	1272	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)

src/mame/audio/redalert.c
r5534	r5535
168	168	}
169	169
170	170
171		static ~~void~~ sod_callback~~(const~~ ~~device_config *device, int data~~)
	171	static WRITE_LINE_DEVICE_HANDLER( sod_callback )
172	172	{
173		hc55516_digit_w(devtag_get_device(device->machine, "cvsd"), data);
	173	hc55516_digit_w(devtag_get_device(device->machine, "cvsd"), state);
174	174	}
175	175
176	176
177		static ~~int~~ sid_callback~~(const~~ ~~device_config *device~~)
	177	static READ_LINE_DEVICE_HANDLER( sid_callback )
178	178	{
179	179	return hc55516_clock_state_r(devtag_get_device(device->machine, "cvsd"));
180	180	}
181	181
182	182
183		static ~~const i~~8085_~~config~~ redalert_voice_i8085_config =
	183	static I8085_CONFIG( redalert_voice_i8085_config )
184	184	{
185		NULL, /* INTE changed callback */
186		NULL, /* STATUS changed callback */
187		sod_callback, /* SOD changed callback (8085A only) */
188		sid_callback /* SID changed callback (8085A only) */
	185	DEVCB_NULL, /* STATUS changed callback */
	186	DEVCB_NULL, /* INTE changed callback */
	187	DEVCB_LINE(sid_callback), /* SID changed callback (8085A only) */
	188	DEVCB_LINE(sod_callback) /* SOD changed callback (8085A only) */
189	189	};
190	190
191	191

src/mame/audio/mario.c
r5534	r5535
169	169	* -\|\|-
170	170	* C2
171	171	************************************************************************/
172		#define MARIO_CUSTOM_VOUT (*(node->input[0]))
173		#define MARIO_CUSTOM_IN1 (*(node->input[1]))
174		#define MARIO_CUSTOM_IN2 (*(node->input[2]))
175		#define MARIO_CUSTOM_C1 (*(node->input[3]))
176		#define MARIO_CUSTOM_C2 (*(node->input[4]))
177		#define MARIO_CUSTOM_R1 (*(node->input[5]))
178		#define MARIO_CUSTOM_C3 (*(node->input[6]))
	172	#define MARIO_CUSTOM_VOUT DISCRETE_INPUT(0)
	173	#define MARIO_CUSTOM_IN1 DISCRETE_INPUT(1)
	174	#define MARIO_CUSTOM_IN2 DISCRETE_INPUT(2)
	175	#define MARIO_CUSTOM_C1 DISCRETE_INPUT(3)
	176	#define MARIO_CUSTOM_C2 DISCRETE_INPUT(4)
	177	#define MARIO_CUSTOM_R1 DISCRETE_INPUT(5)
	178	#define MARIO_CUSTOM_C3 DISCRETE_INPUT(6)
179	179
180	180	struct mario_custom_run_context
181	181	{
r5534	r5535
192	192
193	193	double t1 = 0.5 / LS624_F(MARIO_CUSTOM_C1, MARIO_CUSTOM_IN1, RUN_VCO_VOLTAGE);
194	194	double t2 = 0.5 / LS624_F(MARIO_CUSTOM_C2, MARIO_CUSTOM_IN2, RUN_VCO_VOLTAGE);
195		double sample_t = d~~isc_~~info->sample_time;
	195	double sample_t = node->info->sample_time;
196	196	double vn, t;
197	197
198	198	//if (MARIO_CUSTOM_VOUT)
r5534	r5535
258	258
259	259	static const discrete_custom_info mario_custom_run_info =
260	260	{
261		DISCRETE_RESET_NAME( mario_custom_run ),
262		DISCRETE_STEP_NAME( mario_custom_run ),
263		sizeof(struct mario_custom_run_context),
	261	DISCRETE_CUSTOM_MODULE( mario_custom_run, struct mario_custom_run_context),
264	262	NULL
265	263	};
266	264

src/mame/audio/tank8.c
r5534	r5535
212	212	DISCRETE_DIVIDE(NODE_110,1,TANK8_BUGLE_DATA1,7875.0)
213	213	DISCRETE_DIVIDE(NODE_111,1,TANK8_BUGLE_DATA2,7875.0)
214	214	DISCRETE_SQUAREWAVE2(NODE_112,TANK8_BUGLE_EN,3.4, NODE_110, NODE_111,1.7,0)
215		DISCRETE_RCDISC3(NODE_113,1, NODE_112, RES_K(10),RES_K(1),CAP_U(0.1))
	215	DISCRETE_RCDISC3(NODE_113,1, NODE_112, RES_K(10),RES_K(1),CAP_U(0.1), 0.5)
216	216	DISCRETE_CRFILTER(TANK8_BUGLE, 1, NODE_113, RES_K(47), CAP_U(.01))
217	217
218	218	/************************************************/

src/mame/machine/leland.c
r5534	r5535
1380	1380
1381	1381	/* set the new value */
1382	1382	leland_gfx_control = data;
1383		leland_dac_control &= data & 3;
	1383	leland_dac_control = data & 3;
1384	1384
1385	1385	/* some bankswitching occurs here */
1386	1386	if (LOG_BANKSWITCHING_M)

src/mame/machine/midtunit.c
r5534	r5535
174	174
175	175	/*************************************
176	176	*
	177	* MK Turbo Ninja protection
	178	*
	179	*************************************/
	180
	181	static READ16_HANDLER( mkturbo_prot_r )
	182	{
	183	/* the security GAL overlays a counter of some sort at 0xfffff400 in ROM space.
	184	* A startup protection check expects to read back two different values in succession */
	185	return mame_rand(space->machine);
	186	}
	187
	188
	189
	190	/*************************************
	191	*
177	192	* Mortal Kombat 2 protection
178	193	*
179	194	*************************************/
r5534	r5535
454	469	memory_set_bankptr(machine, 9, auto_alloc_array(machine, UINT8, 0x80));
455	470	}
456	471
	472	DRIVER_INIT( mkturbo )
	473	{
	474	/* protection */
	475	memory_install_read16_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xfffff400, 0xfffff40f, 0, 0, mkturbo_prot_r);
	476
	477	DRIVER_INIT_CALL(mktunit);
	478	}
	479
	480
457	481	static void init_nbajam_common(running_machine *machine, int te_protection)
458	482	{
459	483	/* common init */

src/mame/machine/archimds.c
r5534	r5535
115	115	{
116	116	double freq;
117	117
118		if(~~(double)~~ioc_timercnt[tmr] != 0) // FIXME: dmdtouch does a divide by zero?
	118	if(ioc_timercnt[tmr] != 0) // FIXME: dmdtouch does a divide by zero?
119	119	{
120	120	freq = 2000000.0 / (double)ioc_timercnt[tmr];
121	121	// logerror("IOC: starting timer %d, %d ticks, freq %f Hz\n", tmr, ioc_timercnt[tmr], freq);

src/mame/machine/kaneko16.c
r5534	r5535
16	16	#include "includes/kaneko16.h"
17	17
18	18	#include "kanekotb.h" // TOYBOX MCU trojaning results
	19	#include "machine/eeprom.h"
19	20
	21
	22	#define CALC3_VERBOSE_OUTPUT 0
	23
20	24	#define MCU_RESPONSE(d) memcpy(&kaneko16_mcu_ram[mcu_offset], d, sizeof(d))
21	25
22	26	UINT16 *kaneko16_mcu_ram;
r5534	r5535
34	38	- bonkadv only uses Random Number, XY Overlap Collision bit and register '0x02'
35	39	*/
36	40
	41
37	42	static struct {
38	43	UINT16 x1p, y1p, x1s, y1s;
39	44	UINT16 x2p, y2p, x2s, y2s;
r5534	r5535
147	152	rect2 <-----> \| <-----------> \| <--->
148	153	result <----------> \| <--------> \| <---->
149	154	*/
	155
150	156	static INT16 calc_compute_x(void)
151	157	{
152	158	INT16 x_coll;
r5534	r5535
161	167
162	168	return x_coll;
163	169	}
	170
164	171	static INT16 calc_compute_y(void)
165	172	{
166	173	INT16 y_coll;
r5534	r5535
236	243	return 0;
237	244	}
238	245
	246	/*
	247	B Rap Boys
	248	Shogun Warriors
	249
	250	*/
	251
	252
	253	static struct {
	254	int x1p, y1p, z1p, x1s, y1s, z1s;
	255	int x2p, y2p, z2p, x2s, y2s, z2s;
	256
	257	int x1po, y1po, z1po, x1so, y1so, z1so;
	258	int x2po, y2po, z2po, x2so, y2so, z2so;
	259
	260	int x12, y12, z12, x21, y21, z21;
	261
	262	int x_coll, y_coll, z_coll;
	263
	264	int x1tox2, y1toy2, z1toz2;
	265
	266	UINT16 mult_a, mult_b;
	267
	268	UINT16 flags;
	269	UINT16 mode;
	270
	271	} shogwarr_hit;
	272
	273
	274	//calculate simple intersection of two segments
	275
	276	static int shogwarr_calc_compute(int x1, int w1, int x2, int w2)
	277	{
	278	int dist;
	279
	280	if(x2>=x1 && x2+w2<=(x1+w1))
	281	{
	282	//x2 inside x1
	283	dist=w2;
	284	}
	285	else
	286	{
	287	if(x1>=x2 && x1+w1<=(x2+w2))
	288	{
	289	//x1 inside x2
	290	dist=w1;
	291	}
	292	else
	293	{
	294	if(x2<x1)
	295	{
	296	//swap
	297	int tmp=x1;
	298	x1=x2;
	299	x2=tmp;
	300	tmp=w1;
	301	w1=w2;
	302	w2=tmp;
	303	}
	304	dist=x1+w1-x2;
	305	}
	306	}
	307	return dist;
	308	}
	309
	310	//calc segment coordinates
	311
	312	static void shogwarr_calc_org(int mode, int x0, int s0, int* x1, int* s1)
	313	{
	314	switch(mode)
	315	{
	316	case 0: x1=x0; s1=s0; break;
	317	case 1: x1=x0-s0/2; s1=s0; break;
	318	case 2: x1=x0-s0; s1=s0; break;
	319	case 3: x1=x0-s0; s1=2*s0; break;
	320	}
	321	//x1 is the left most coord, s1 = width
	322	}
	323
	324	static void shogwarr_recalc_collisions(void)
	325	{
	326	//calculate positions and sizes
	327
	328	int mode=shogwarr_hit.mode;
	329
	330	shogwarr_hit.flags=0;
	331
	332	shogwarr_calc_org(mode&3, shogwarr_hit.x1po, shogwarr_hit.x1so, &shogwarr_hit.x1p, &shogwarr_hit.x1s);
	333	mode>>=2;
	334	shogwarr_calc_org(mode&3, shogwarr_hit.y1po, shogwarr_hit.y1so, &shogwarr_hit.y1p, &shogwarr_hit.y1s);
	335	mode>>=2;
	336	shogwarr_calc_org(mode&3, shogwarr_hit.z1po, shogwarr_hit.z1so, &shogwarr_hit.z1p, &shogwarr_hit.z1s);
	337
	338	mode>>=4;
	339
	340	shogwarr_calc_org(mode&3, shogwarr_hit.x2po, shogwarr_hit.x2so, &shogwarr_hit.x2p, &shogwarr_hit.x2s);
	341	mode>>=2;
	342	shogwarr_calc_org(mode&3, shogwarr_hit.y2po, shogwarr_hit.y2so, &shogwarr_hit.y2p, &shogwarr_hit.y2s);
	343	mode>>=2;
	344	shogwarr_calc_org(mode&3, shogwarr_hit.z2po, shogwarr_hit.z2so, &shogwarr_hit.z2p, &shogwarr_hit.z2s);
	345
	346
	347	shogwarr_hit.x1tox2=abs(shogwarr_hit.x2po-shogwarr_hit.x1po);
	348	shogwarr_hit.y1toy2=abs(shogwarr_hit.y2po-shogwarr_hit.y1po);
	349	shogwarr_hit.z1toz2=abs(shogwarr_hit.z2po-shogwarr_hit.z1po);
	350
	351
	352	shogwarr_hit.x_coll = shogwarr_calc_compute(shogwarr_hit.x1p, shogwarr_hit.x1s, shogwarr_hit.x2p, shogwarr_hit.x2s);
	353	shogwarr_hit.y_coll = shogwarr_calc_compute(shogwarr_hit.y1p, shogwarr_hit.y1s, shogwarr_hit.y2p, shogwarr_hit.y2s);
	354	shogwarr_hit.z_coll = shogwarr_calc_compute(shogwarr_hit.z1p, shogwarr_hit.z1s, shogwarr_hit.z2p, shogwarr_hit.z2s);
	355
	356
	357	// 4th nibble: Y Absolute Collision -> possible values = 9,8,4,3,2
	358	if (shogwarr_hit.y1p > shogwarr_hit.y2p) shogwarr_hit.flags \|= 0x2000;
	359	else if (shogwarr_hit.y1p == shogwarr_hit.y2p) shogwarr_hit.flags \|= 0x4000;
	360	else if (shogwarr_hit.y1p < shogwarr_hit.y2p) shogwarr_hit.flags \|= 0x8000;
	361	if (shogwarr_hit.y_coll<0) shogwarr_hit.flags \|= 0x1000;
	362
	363	// 3rd nibble: X Absolute Collision -> possible values = 9,8,4,3,2
	364	if (shogwarr_hit.x1p > shogwarr_hit.x2p) shogwarr_hit.flags \|= 0x0200;
	365	else if (shogwarr_hit.x1p == shogwarr_hit.x2p) shogwarr_hit.flags \|= 0x0400;
	366	else if (shogwarr_hit.x1p < shogwarr_hit.x2p) shogwarr_hit.flags \|= 0x0800;
	367	if (shogwarr_hit.x_coll<0) shogwarr_hit.flags \|= 0x0100;
	368
	369	// 2nd nibble: Z Absolute Collision -> possible values = 9,8,4,3,2
	370	if (shogwarr_hit.z1p > shogwarr_hit.z2p) shogwarr_hit.flags \|= 0x0020;
	371	else if (shogwarr_hit.z1p == shogwarr_hit.z2p) shogwarr_hit.flags \|= 0x0040;
	372	else if (shogwarr_hit.z1p < shogwarr_hit.z2p) shogwarr_hit.flags \|= 0x0080;
	373	if (shogwarr_hit.z_coll<0) shogwarr_hit.flags \|= 0x0010;
	374
	375	// 1st nibble: XYZ Overlap Collision
	376	if ((shogwarr_hit.x_coll>=0)&&(shogwarr_hit.y_coll>=0)&&(shogwarr_hit.z_coll>=0)) shogwarr_hit.flags \|= 0x0008;
	377	if ((shogwarr_hit.x_coll>=0)&&(shogwarr_hit.z_coll>=0)) shogwarr_hit.flags \|= 0x0004;
	378	if ((shogwarr_hit.y_coll>=0)&&(shogwarr_hit.z_coll>=0)) shogwarr_hit.flags \|= 0x0002;
	379	if ((shogwarr_hit.x_coll>=0)&&(shogwarr_hit.y_coll>=0)) shogwarr_hit.flags \|= 0x0001;
	380	}
	381
	382
	383	WRITE16_HANDLER(shogwarr_calc_w)
	384	{
	385	int idx=offset*4;
	386	switch (idx)
	387	{
	388	// p is position, s is size
	389	case 0x00:
	390	case 0x28:
	391
	392	shogwarr_hit.x1po = data; break;
	393
	394	case 0x04:
	395	case 0x2c:
	396	shogwarr_hit.x1so = data; break;
	397
	398	case 0x08:
	399	case 0x30:
	400	shogwarr_hit.y1po = data; break;
	401
	402	case 0x0c:
	403	case 0x34:
	404	shogwarr_hit.y1so = data; break;
	405
	406	case 0x10:
	407	case 0x58:
	408	shogwarr_hit.x2po = data; break;
	409
	410	case 0x14:
	411	case 0x5c:
	412	shogwarr_hit.x2so = data; break;
	413
	414	case 0x18:
	415	case 0x60:
	416	shogwarr_hit.y2po = data; break;
	417
	418	case 0x1c:
	419	case 0x64:
	420	shogwarr_hit.y2so = data; break;
	421
	422	case 0x38:
	423	case 0x50:
	424	shogwarr_hit.z1po = data; break;
	425	case 0x3c:
	426	case 0x54:
	427	shogwarr_hit.z1so = data; break;
	428
	429	case 0x20:
	430	case 0x68:
	431	shogwarr_hit.z2po = data; break;
	432
	433	case 0x24:
	434	case 0x6c:
	435	shogwarr_hit.z2so = data; break;
	436
	437	case 0x70:
	438	shogwarr_hit.mode=data;break;
	439
	440	default:
	441	logerror("CPU #0 PC %06x: warning - write unmapped hit address %06x [ %06x] = %06x\n",cpu_get_pc(space->cpu),offset<<1, idx, data);
	442	}
	443
	444	shogwarr_recalc_collisions();
	445	}
	446
	447
	448	READ16_HANDLER(shogwarr_calc_r)
	449	{
	450
	451	int idx=offset*4;
	452
	453	switch (idx)
	454	{
	455	case 0x00: // X distance
	456	case 0x10:
	457	return shogwarr_hit.x_coll;
	458
	459	case 0x04: // Y distance
	460	case 0x14:
	461	return shogwarr_hit.y_coll;
	462
	463	case 0x18: // Z distance
	464	return shogwarr_hit.z_coll;
	465
	466	case 0x08:
	467	case 0x1c:
	468
	469	return shogwarr_hit.flags;
	470
	471	case 0x28:
	472	return (mame_rand(space->machine) & 0xffff);
	473
	474	case 0x40: return shogwarr_hit.x1po;
	475	case 0x44: return shogwarr_hit.x1so;
	476	case 0x48: return shogwarr_hit.y1po;
	477	case 0x4c: return shogwarr_hit.y1so;
	478	case 0x50: return shogwarr_hit.z1po;
	479	case 0x54: return shogwarr_hit.z1so;
	480
	481	case 0x58: return shogwarr_hit.x2po;
	482	case 0x5c: return shogwarr_hit.x2so;
	483	case 0x60: return shogwarr_hit.y2po;
	484	case 0x64: return shogwarr_hit.y2so;
	485	case 0x68: return shogwarr_hit.z2po;
	486	case 0x6c: return shogwarr_hit.z2so;
	487
	488	case 0x80: return shogwarr_hit.x1tox2;
	489	case 0x84: return shogwarr_hit.y1toy2;
	490	case 0x88: return shogwarr_hit.z1toz2;
	491
	492	default:
	493	logerror("CPU #0 PC %06x: warning - read unmapped calc address %06x [ %06x]\n",cpu_get_pc(space->cpu),offset<<1, idx);
	494	}
	495
	496	return 0;
	497	}
	498
239	499	/***************************************************************************
240	500	CALC3 MCU:
241	501
r5534	r5535
269	529	00207FE0 : base of 'stack' used when transfering tables out of MCU
270	530	*/
271	531
272		static void calc3_mcu_run(running_machine *machine);
273	532
274	533	static int calc3_mcu_status, calc3_mcu_command_offset;
275	534
r5534	r5535
280	539	calc3_mcu_command_offset = 0;
281	540	}
282	541
	542	void calc3_mcu_run(running_machine *machine);
	543
283	544	WRITE16_HANDLER( calc3_mcu_ram_w )
284	545	{
285	546	COMBINE_DATA(&kaneko16_mcu_ram[offset]);
286		calc3_mcu_run(space->machine);
	547	//calc3_mcu_run(space->machine);
287	548	}
288	549
289	550	#define CALC3_MCU_COM_W(_n_) \
r5534	r5535
291	552	{ \
292	553	logerror("calc3w %d %04x %04x\n",_n_, data,mem_mask); \
293	554	calc3_mcu_status \|= (1 << _n_); \
294		calc3_mcu_run(space->machine); \
295	555	}
296	556
297	557	CALC3_MCU_COM_W(0)
r5534	r5535
299	559	CALC3_MCU_COM_W(2)
300	560	CALC3_MCU_COM_W(3)
301	561
	562
302	563	/***************************************************************************
303	564	Shogun Warriors
304	565	***************************************************************************/
r5534	r5535
356	617	Status
357	618
358	619	Blocks marked ** are decrypted and verified
359		~~ means I have the data to study
	620	.. means I have the data to study
360	621
361	622	(Shogun Warriors)
362	623
r5534	r5535
409	670	** Block 15 Found Base 250f - Mode? 02 Unknown 3f Key 24 Length 03b8 \| shift 3 places + table, contains GAME OVER, CONTINUE
410	671	** Block 16 Found Base 28cd - Mode? 01 Unknown 03 Key 80 Length 018a
411	672	** Block 17 Found Base 2a5d - Mode? 01 Unknown 1f Key 15 Length 018a
412		-- Block 18 Found Base 2bed - Mode? 01 Unknown 44 Key 00 Length 0184
	673	** Block 18 Found Base 2bed - Mode? 01 Unknown 44 Key 00 Length 0184 \| 4 place shift
413	674	** Block 19 Found Base 2d77 - Mode? 01 Unknown 03 Key 19 Length 0184 \| just a table
414		Block 1a Found Base 2f01 - Inline Encryption (size 21) - Mode? 02 Unknown 3f Key (unused?) 61 Length 0a24
415		Block 1b Found Base 394c - Mode? 01 Unknown 5f Key 22 Length 0e02
416		Block 1c Found Base 4754 - Mode? 01 Unknown 1f Key 3f Length 0e02
417		Block 1d Found Base 555c - Mode? 01 Unknown 03 Key bf Length 0e02
418		Block 1e Found Base 6364 - Mode? 01 Unknown 01 Key 24 Length 0e02
	675	** Block 1a Found Base 2f01 - Inline Encryption (size 21) - Mode? 02 Unknown 3f Key (unused?) 61 Length 0a24
	676	** Block 1b Found Base 394c - Mode? 01 Unknown 5f Key 22 Length 0e02
	677	** Block 1c Found Base 4754 - Mode? 01 Unknown 1f Key 3f Length 0e02
	678	** Block 1d Found Base 555c - Mode? 01 Unknown 03 Key bf Length 0e02
	679	** Block 1e Found Base 6364 - Mode? 01 Unknown 01 Key 24 Length 0e02
419	680	** Block 1f Found Base 716c - Mode? 02 Unknown 1f Key 39 Length 02ac \| 1 place shift + table
420		Block 20 Found Base 741e - Mode? 03 Unknown 03 Key af Length 01a4
421		Block 21 Found Base 75c8 - Inline Encryption (size 3d) - Mode? 03 Unknown 2f Key (unused?) 7d Length 01fa
	681	** Block 20 Found Base 741e - Mode? 03 Unknown 03 Key af Length 01a4
	682	** Block 21 Found Base 75c8 - Inline Encryption (size 3d) - Mode? 03 Unknown 2f Key (unused?) 7d Length 01fa
422	683	** Block 22 Found Base 7805 - Mode? 03 Unknown 1f Key 17 Length 010c \| 1 place shift + table
423	684	** Block 23 Found Base 7917 - Mode? 03 Unknown 03 Key 89 Length 018c \| just a table
424		~~ Block 24 Found Base 7aa9 - Inline Encryption (size 03) - Mode? 03 Unknown 5f Key (unused?) 43 Length 0214
425		Block 25 Found Base 7cc6 - Inline Encryption (size 1d) - Mode? 03 Unknown 02 Key (unused?) 5d Length 0178
426		Block 26 Found Base 7e61 - Mode? 03 Unknown 03 Key 05 Length 04e2
427		Block 27 Found Base 8349 - Mode? 03 Unknown 3f Key a7 Length 00fa
428		Block 28 Found Base 8449 - Inline Encryption (size 23) - Mode? 03 Unknown 1f Key (unused?) 63 Length 015a
429		Block 29 Found Base 85cc - Mode? 03 Unknown 03 Key 15 Length 00d6
430		Block 2a Found Base 86a8 - Mode? 03 Unknown 3f Key a1 Length 00aa
431		Block 2b Found Base 8758 - Mode? 03 Unknown 2f Key 04 Length 01a2
432		Block 2c Found Base 8900 - Mode? 03 Unknown 2f Key 04 Length 04cc
433		Block 2d Found Base 8dd2 - Mode? 03 Unknown 03 Key 15 Length 0486
	685	** Block 24 Found Base 7aa9 - Inline Encryption (size 03) - Mode? 03 Unknown 5f Key (unused?) 43 Length 0214
	686	** Block 25 Found Base 7cc6 - Inline Encryption (size 1d) - Mode? 03 Unknown 02 Key (unused?) 5d Length 0178
	687	** Block 26 Found Base 7e61 - Mode? 03 Unknown 03 Key 05 Length 04e2
	688	** Block 27 Found Base 8349 - Mode? 03 Unknown 3f Key a7 Length 00fa
	689	** Block 28 Found Base 8449 - Inline Encryption (size 23) - Mode? 03 Unknown 1f Key (unused?) 63 Length 015a
	690	** Block 29 Found Base 85cc - Mode? 03 Unknown 03 Key 15 Length 00d6
	691	** Block 2a Found Base 86a8 - Mode? 03 Unknown 3f Key a1 Length 00aa
	692	** Block 2b Found Base 8758 - Mode? 03 Unknown 2f Key 04 Length 01a2
	693	** Block 2c Found Base 8900 - Mode? 03 Unknown 2f Key 04 Length 04cc
	694	** Block 2d Found Base 8dd2 - Mode? 03 Unknown 03 Key 15 Length 0486
434	695
	696
435	697	*/
436	698
437	699	UINT16 calc3_mcu_crc;
r5534	r5535
454	716	0xda,0x89,0x08,0x77,0xb1,0x81,0x6b,0x2d,0xb6,0xbc,0x99,0xc9,0x35,0x0a,0x0f,0x01
455	717	};
456	718
457		/* ok - shogwarr */
458		static UINT8 calc3_key15[64] = {
459		0x0C,0xEB,0x30,0x25,0xA8,0xED,0xE3,0x23,0xAC,0x2B,0x8D,0x34,0x88,0x9F,0x55,0xB5,
460		0xBF,0x15,0xE3,0x7C,0x54,0xD4,0x72,0xA9,0x7E,0x80,0x27,0x9F,0xA3,0x3F,0xA1,0x4D,
461		0x84,0x1B,0xD1,0xB2,0xB5,0xA7,0x0C,0xA0,0x51,0xE6,0x5E,0xC0,0xEB,0x68,0x22,0xD6,
462		0xC8,0xB6,0xCF,0x46,0x4B,0xF0,0x15,0xD7,0xB0,0xB5,0x29,0xB8,0xFD,0x43,0x5C,0xC0
463		};
464	719
465
466	720	/* ok - brapboys initial transfer */
467	721	static UINT8 calc3_key04[64] = {
468	722	0xff,0x4a,0x62,0xa3,0xf4,0xb4,0x8c,0x2d,0x84,0xbd,0x87,0x3a,0x9e,0xe9,0xd7,0x12,
r5534	r5535
471	725	0x43,0xbe,0x47,0x32,0x8f,0x0e,0xfd,0x64,0x42,0x59,0x2b,0xe5,0xde,0x6d,0x80,0x7a,
472	726	};
473	727
	728	static UINT8 calc3_key05[64] = {
	729	0x5e,0xd8,0xa6,0xd7,0x00,0x94,0x23,0x66,0xaf,0xea,0xbe,0x45,0x38,0x90,0x8e,0x8d,
	730	0x5b,0x14,0x2c,0xda,0x55,0x7e,0x9d,0x08,0x2d,0x31,0xfd,0x3a,0xbe,0x13,0xeb,0x21,
	731	0x87,0xee,0xb7,0x7b,0x34,0x15,0x4d,0xd9,0xeb,0x4a,0xde,0xa6,0x57,0xdf,0x53,0x65,
	732	0x75,0x1c,0x72,0x3a,0x20,0xe1,0xcd,0xac,0x5d,0x8c,0x6d,0xa9,0x66,0x1d,0x41,0xca,
	733	};
	734
	735	/* ok - shogwarr */
	736	static UINT8 calc3_key15[64] = {
	737	0x0C,0xEB,0x30,0x25,0xA8,0xED,0xE3,0x23,0xAC,0x2B,0x8D,0x34,0x88,0x9F,0x55,0xB5,
	738	0xBF,0x15,0xE3,0x7C,0x54,0xD4,0x72,0xA9,0x7E,0x80,0x27,0x9F,0xA3,0x3F,0xA1,0x4D,
	739	0x84,0x1B,0xD1,0xB2,0xB5,0xA7,0x0C,0xA0,0x51,0xE6,0x5E,0xC0,0xEB,0x68,0x22,0xD6,
	740	0xC8,0xB6,0xCF,0x46,0x4B,0xF0,0x15,0xD7,0xB0,0xB5,0x29,0xB8,0xFD,0x43,0x5C,0xC0
	741	};
	742
474	743	static UINT8 calc3_key17[64] = {
475	744	0x1b,0x48,0xa4,0xdd,0x2e,0x7a,0xe3,0xd1,0x6d,0x9e,0x49,0x31,0xdb,0x13,0xe6,0x00,
476	745	0xf1,0x8f,0xcb,0x3f,0x23,0xc1,0xf3,0xb4,0x30,0x35,0xf4,0xea,0x2c,0x77,0x65,0x79,
r5534	r5535
485	754	0x7f,0x5f,0xa6,0x1b,0x90,0x96,0x19,0x14,0x22,0x81,0x38,0xcd,0x20,0x2f,0x22,0x70,
486	755	};
487	756
	757	static UINT8 calc3_key22[64] = {
	758	0xfe,0xf7,0xc7,0x85,0xe4,0xd3,0x93,0xd0,0x36,0x61,0xc8,0x4d,0x0c,0x3e,0x2a,0x1c,
	759	0x32,0x1a,0xbf,0x1a,0xb0,0x60,0xb5,0xa8,0x1a,0x19,0x16,0xaf,0x96,0x0d,0x2d,0xe0,
	760	0xb1,0x2c,0xb6,0x41,0xe1,0x2d,0xc8,0xe5,0xd9,0x75,0x82,0xfa,0x90,0x3a,0x77,0x09,
	761	0x0e,0xe8,0xda,0x7a,0xfb,0xc4,0x68,0x57,0xe8,0xcf,0x18,0x51,0x5b,0xed,0x83,0x08,
	762	};
	763
488	764	static UINT8 calc3_key24[64] = {
489	765	0x75,0x49,0x7a,0xd6,0x84,0xbd,0x70,0xbe,0x10,0x19,0x6c,0xb2,0xa9,0x5f,0x6b,0x78,
490	766	0x14,0x29,0x2a,0x15,0xd0,0x4a,0x10,0x93,0x69,0xb2,0xdf,0x02,0x7f,0x92,0x19,0xbd,
r5534	r5535
506	782	0x26,0xf3,0x44,0x94,0xdb,0x15,0x76,0xcc,0x28,0x33,0x2d,0x4b,0x79,0xdb,0x06,0xbc
507	783	};
508	784
	785	static UINT8 calc3_key3f[64] = {
	786	0x27,0xb4,0xc1,0xba,0x5f,0xd4,0x47,0x04,0x1f,0xfe,0x42,0xa5,0xce,0xb5,0x23,0xbe,
	787	0x42,0xcc,0x59,0x71,0x51,0x13,0x41,0xa4,0x18,0x35,0xcf,0x02,0x0d,0xe1,0xfb,0x43,
	788	0xc5,0x28,0xed,0xae,0x84,0x27,0xe8,0xdc,0x89,0xe5,0xf6,0xbe,0x16,0x7e,0x57,0xe1,
	789	0x41,0x82,0xa9,0xf1,0x7c,0x98,0xd7,0x7c,0xe5,0x67,0xc2,0xf9,0x4d,0xb6,0xb0,0x09,
	790	};
	791
509	792	static UINT8 calc3_key80[64] = {
510	793	0x33,0x8e,0x6f,0x22,0xac,0x01,0x9f,0x7a,0xc7,0xca,0x23,0xc4,0xa4,0x9c,0x07,0xf8,
511	794	0x98,0xc1,0x17,0x4a,0xb2,0xbc,0xcc,0xf4,0x0e,0x2e,0xf6,0x35,0xdd,0xf6,0x29,0x9a,
r5534	r5535
520	803	0x67,0x47,0xee,0xa2,0x35,0xb3,0xff,0x76,0x57,0x4f,0x30,0x66,0xf8,0xe9,0xe0,0x5b,
521	804	};
522	805
	806	static UINT8 calc3_keya1[64] = {
	807	0x0f,0x35,0xa3,0x7c,0xf1,0x75,0xea,0x27,0x36,0x4d,0x4b,0x1a,0x3b,0x24,0xef,0x9d,
	808	0x4e,0x39,0x7e,0x7b,0x3d,0x42,0x0d,0xc2,0x9f,0x53,0xc7,0xc4,0xdf,0x02,0x5d,0x61,
	809	0x0c,0xc9,0x2d,0x89,0x63,0xab,0x34,0xfc,0x97,0x1b,0xb5,0x54,0xe6,0x19,0xa5,0x46,
	810	0xdc,0x9e,0xdc,0x25,0xe4,0x3a,0xfc,0xa7,0x93,0xfc,0x1f,0xec,0xb3,0x92,0x43,0xbc,
	811	};
	812
	813	static UINT8 calc3_keya7[64] = {
	814	0x5d,0xdd,0xd4,0xbe,0xc0,0xff,0xe1,0x1b,0x3a,0xd6,0x61,0xc8,0x90,0x02,0x23,0x08,
	815	0xfa,0x7a,0xfa,0x1d,0xab,0x2b,0xa0,0x0b,0x24,0xe1,0x6b,0x9e,0x38,0x6b,0xb2,0xae,
	816	0xdd,0xfa,0xfc,0xa2,0xb8,0xcb,0xed,0x33,0x66,0x06,0xef,0x72,0x8b,0xe5,0xa3,0x0d,
	817	0x9b,0x18,0x05,0xce,0x6a,0x69,0x61,0x64,0x74,0x9c,0xf9,0x66,0xec,0x99,0x72,0x95,
	818	};
	819
	820	static UINT8 calc3_keyaf[64] = {
	821	0x2c,0xf3,0x0d,0x50,0x30,0x77,0xc2,0x25,0x91,0x83,0x5f,0xac,0xf4,0x56,0x96,0xc8,
	822	0x70,0x86,0x16,0x5a,0x1b,0xa1,0x7d,0x08,0x53,0x15,0xfd,0x3c,0xcb,0x4d,0xd0,0x70,
	823	0x5c,0x1d,0x5c,0xaa,0x87,0x60,0x24,0x42,0xcc,0xe0,0x75,0xeb,0xae,0x75,0xcc,0xf1,
	824	0x81,0x71,0x09,0xc0,0xf8,0x3c,0x55,0xa6,0x71,0x3c,0xd2,0xda,0xfe,0xf8,0x07,0xbc,
	825	};
	826
523	827	static UINT8 calc3_keybc[64] = {
524	828	0xb8,0x8a,0xa5,0x8f,0x58,0x30,0xb0,0x38,0xa6,0x53,0x84,0x33,0xd4,0xd7,0xbd,0x26,
525	829	0x45,0x35,0xb7,0xf6,0x1a,0x20,0x7b,0x8d,0x7e,0x68,0x69,0xdb,0xb1,0x1e,0xa5,0x1a,
r5534	r5535
527	831	0xfa,0x8e,0x71,0x32,0xfa,0x42,0x69,0xec,0x5d,0x50,0x02,0x42,0xc2,0xe4,0xae,0x5a,
528	832	};
529	833
	834	static UINT8 calc3_keybf[64] = {
	835	0x9a,0x8e,0xcf,0x66,0xe0,0xd8,0xd4,0x2a,0x0f,0x4d,0xad,0x64,0x8c,0x6d,0xcb,0x37,
	836	0x2e,0x0e,0x9f,0xc4,0xca,0xff,0x85,0xf1,0x7f,0xec,0x71,0x69,0xc2,0x81,0x5c,0xe4,
	837	0x28,0xd2,0x6b,0xa9,0xf6,0xfb,0xe4,0x51,0x68,0x03,0xd0,0xcd,0xc3,0x07,0x6f,0xab,
	838	0x1c,0x94,0x5f,0x94,0xe6,0x54,0x8b,0x1a,0x3c,0xed,0xd4,0xb0,0xf3,0x26,0x81,0xfa,
	839	};
	840
530	841	// global so we can use them in the filename when we save out the data (debug..)
531	842	static UINT8 calc3_decryption_key_byte;
532	843	static UINT8 calc3_unknown;
	844	static UINT8 calc3_shift;
533	845	static UINT8 calc3_mode;
534	846	static UINT8 calc3_blocksize_offset;
535	847	static UINT16 calc3_dataend;
536	848	static UINT16 calc3_database;
537	849
	850	static int data_header[2];
	851
	852	UINT32 calc3_writeaddress;
	853	UINT32 calc3_writeaddress_current;
	854	UINT16 calc3_dsw_addr = 0x00;
	855	UINT16 calc3_eeprom_addr;
	856	UINT16 calc3_poll_addr;
	857	UINT16 cakc3_checkumaddress;
	858
	859	static UINT8 shift_bits(UINT8 dat, int bits)
	860	{
	861	bits &=0x7;
	862
	863	if (bits==0) return BITSWAP8(dat, 7,6,5,4,3,2,1,0);
	864	if (bits==1) return BITSWAP8(dat, 6,5,4,3,2,1,0,7);
	865	if (bits==2) return BITSWAP8(dat, 5,4,3,2,1,0,7,6);
	866	if (bits==3) return BITSWAP8(dat, 4,3,2,1,0,7,6,5);
	867	if (bits==4) return BITSWAP8(dat, 3,2,1,0,7,6,5,4);
	868	if (bits==5) return BITSWAP8(dat, 2,1,0,7,6,5,4,3);
	869	if (bits==6) return BITSWAP8(dat, 1,0,7,6,5,4,3,2);
	870	if (bits==7) return BITSWAP8(dat, 0,7,6,5,4,3,2,1);
	871
	872	return dat;
	873	}
	874
538	875	// endian safe? you're having a laugh
539	876	int calc3_decompress_table(running_machine* machine, int tabnum, UINT8* dstram, int dstoffset)
540	877	{
	878	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
541	879	UINT8* rom = memory_region(machine,"cpu1");
542	880	UINT8 numregions;
543	881	UINT16 length;
	882	int local_counter=0;
544	883	int x;
545	884	int offset = 0;
546	885	int isbrap = ( !strcmp(machine->gamedrv->name,"brapboysj") \|\| !strcmp(machine->gamedrv->name,"brapboys"));
r5534	r5535
572	911	calc3_blocksize_offset = rom[offset+0]; // location of the 'block length'
573	912	calc3_mode = rom[offset+1];
574	913	calc3_unknown = rom[offset+2];
	914	calc3_shift = (calc3_unknown &0xf0)>>4;
	915	calc3_unknown &= 0x0f;
575	916	calc3_decryption_key_byte = rom[offset+3];
576	917
577	918
r5534	r5535
587	928	length = rom[offset+0] \| (rom[offset+1]<<8);
588	929	offset+=2;
589	930
	931	#if CALC3_VERBOSE_OUTPUT
590	932	if (inline_table_size)
591	933	{
592		printf("Block %02x Found Base %04x - Inline Encryption (size %02x) - Mode? %02x Unk~~nown~~ %02x Key (unused?) %02x Length %04x\n", tabnum, calc3_database, inline_table_size, calc3_mode, calc3_unknown, calc3_decryption_key_byte, length);
	934	printf("Block %02x Found Base %04x - Inline Encryption (size %02x) - Mode? %02x Shift %01x Unk %01x Key (unused?) %02x Length %04x\n", tabnum, calc3_database, inline_table_size, calc3_shift, calc3_mode, calc3_unknown, calc3_decryption_key_byte, length);
593	935	}
594	936	else
595	937	{
596		printf("Block %02x Found Base %04x - Mode? %02x Unk~~nown~~ %02x Key %02x Length %04x\n", tabnum, calc3_database, calc3_mode, calc3_unknown, calc3_decryption_key_byte, length);
	938	printf("Block %02x Found Base %04x - Mode? %02x Shift %01x Unk %01x Key %02x Length %04x\n", tabnum, calc3_database, calc3_mode, calc3_shift, calc3_unknown, calc3_decryption_key_byte, length);
597	939	}
598
599
	940	#endif
600	941	// copy + decrypt the table to the specified memory area
601		if (dstram)
	942	//if (dstram)
602	943	{
603	944	int i;
604	945
r5534	r5535
607	948	// shogwarr does this with 'mode' as 0x08, which probably has some special meaning
608	949	//printf("CALC3: requested 0 length table!\n");
609	950	// -- seems to be 'reset stack' to default for the protection table writes
	951
	952	// except this will break shogun going into game, must be specific conditions for
	953	// this, or it can remember addresses and restore those
	954
	955	// hack, set it to a known address instead of trying to restore to anywhere specific..
	956	// might break at some point tho, eg if it doesn't write command 06 often enough because it trys to use another one like 07...
	957	// need to understand the meaning of this (test hw?)
	958
	959	// !dstram is used because we don't want to process these during our initial table scan, only when the game asks!
	960
	961	if (calc3_mode==0x06)
	962	{
	963	calc3_writeaddress_current = 0x202000;
	964	}
	965	else if (calc3_mode==0x07)
	966	{
	967	// also calls empty table with Mode? 07
	968	// maybe they reset to different points?
	969	}
	970	else if (calc3_mode==0x08 && !dstram)
	971	{
	972	//printf("save to eeprom\n");
	973
	974	{
	975	UINT32 length, size;
	976	UINT8 *dat;
	977
	978	dat = (UINT8 *)eeprom_get_data_pointer(&length, &size);
	979
	980	for (i=0;i<0x80;i++)
	981	{
	982	dat[i] = memory_read_byte(space, calc3_eeprom_addr+0x200000+i);
	983	}
	984
	985	}
	986
	987	}
	988	else if (!dstram)
	989	{
	990	printf("unknown blank table command\n");
	991	}
	992
	993	return 0;
610	994	}
611	995
612	996	if (inline_table_size)
613	997	{
	998	// these should be derived from the inline table somehow, probably just a +/- swap like the normal stuff.. maybe
	999	UINT8 extra[] = { 0x14,0xf0,0xf8,0xd2,0xbe,0xfc,0xac,0x86,0x64,0x08,0x0c,0x74,0xd6,0x6a,0x24,0x12,0x1a,0x72,0xba,0x48,0x76,0x66,0x4a,0x7c,0x5c,0x82,0x0a,0x86,0x82,0x02,0xe6 };
	1000	UINT8 extra2[] = { 0x2f,0x04,0xd1,0x69,0xad,0xeb,0x10,0x95,0xb0,0x2f,0x0a,0x83,0x7d,0x4e,0x2a,0x07,0x89,0x52,0xca,0x41,0xf1,0x4f,0xaf,0x1c,0x01,0xe9,0x89,0xd2,0xaf,0xcd };
	1001
	1002
614	1003	for (i=0;i<length;i++)
615	1004	{
616	1005	UINT8 dat=0;
	1006	int extrasign = -1;
617	1007
618		if (tabnum==0x11 && isbrap )
619		{
620	1008
621		// typed data.. to verify results, out decrypt works!
622		unsigned char rawData[252+2] = {
623		0x00,0x00, 0x42, 0x79, 0x00, 0x20, 0x08, 0x2E, 0x10, 0x39, 0x00, 0x20, 0x00, 0xC2,
624		0x02, 0x40, 0x00, 0x30, 0xE4, 0x48, 0x33, 0xFB, 0x00, 0x3C, 0x00, 0x10,
625		0x22, 0x42, 0x30, 0x3B, 0x00, 0x32, 0x43, 0xEE, 0x00, 0x0A, 0x41, 0xF9,
626		0x00, 0x20, 0x08, 0x30, 0x4A, 0x50, 0x67, 0x00, 0x00, 0x04, 0x4E, 0x75,
627		0x11, 0x40, 0x00, 0x02, 0x11, 0x7C, 0x00, 0xFC, 0x00, 0x03, 0x31, 0x49,
628		0x00, 0x04, 0x30, 0xBC, 0x00, 0x01, 0x42, 0x6E, 0xFF, 0xB0, 0x41, 0xFA,
629		0x00, 0x16, 0x2C, 0x88, 0x4E, 0x75, 0x00, 0x16, 0x00, 0x00, 0x00, 0x17,
630		0x00, 0x01, 0x00, 0x18, 0x00, 0x00, 0x00, 0x19, 0x00, 0x01, 0x33, 0xC0,
631		0x00, 0x2C, 0x00, 0x00, 0x30, 0x3C, 0x00, 0x14, 0x51, 0xC8, 0xFF, 0xFE,
632		0x33, 0xC0, 0x00, 0x2D, 0x00, 0x00, 0x42, 0x79, 0x00, 0x20, 0x08, 0x2E,
633		0x41, 0xF9, 0x00, 0x10, 0x78, 0xB6, 0x70, 0x07, 0x0C, 0x10, 0x00, 0x03,
634		0x66, 0x00, 0x00, 0x0E, 0x53, 0x68, 0x00, 0x0E, 0x66, 0x00, 0x00, 0x06,
635		0x10, 0xBC, 0x00, 0x04, 0x41, 0xE8, 0x00, 0x12, 0x51, 0xC8, 0xFF, 0xE6,
636		0x32, 0x39, 0x00, 0x10, 0x22, 0x46, 0x02, 0x41, 0xFF, 0xFC, 0x10, 0x39,
637		0x00, 0x20, 0x00, 0xC2, 0x02, 0x40, 0x00, 0x01, 0x82, 0x40, 0xE3, 0x48,
638		0x82, 0x40, 0x33, 0xC1, 0x00, 0x90, 0x00, 0x00, 0x33, 0xFB, 0x00, 0x2A,
639		0x00, 0x10, 0x20, 0x26, 0xE5, 0x48, 0x23, 0xFB, 0x00, 0x24, 0x00, 0x10,
640		0x20, 0x22, 0x33, 0xFB, 0x00, 0x20, 0x00, 0x90, 0x00, 0x02, 0x32, 0x39,
641		0x00, 0x10, 0x22, 0x48, 0x82, 0x7B, 0x00, 0x14, 0x33, 0xC1, 0x00, 0x80,
642		0x00, 0x08, 0x4E, 0x75, 0xFF, 0xFF, 0x00, 0x3F, 0xE8, 0xC0, 0x42, 0x00,
643		0x03, 0xC0, 0x00, 0x00, 0x57, 0x00, 0x7E, 0x00, 0xFC, 0x00, 0x03, 0x03
644		};
	1009	if (
	1010	(tabnum==0x11 && isbrap) \|\|
	1011	(tabnum==0x1a && isbrap) \|\|
	1012	(tabnum==0x21 && isbrap) \|\|
	1013	(tabnum==0x24 && isbrap) \|\|
	1014	(tabnum==0x28 && isbrap)
	1015	/(tabnum==0x40 && !isbrap)/
	1016	)
	1017	extrasign = 0;
645	1018
646		if ( ((i / 19)&1)==0)
	1019	if ((tabnum==0x25 && isbrap))
	1020	extrasign = 1;
	1021
	1022
	1023
	1024	if (extrasign !=-1)
	1025	{
	1026	if ( ((i / inline_table_size)&1)==0)
647	1027	{
648	1028	if (((i%inline_table_size)&1)==1)
649	1029	{
650	1030	UINT8 inlinet = rom[inline_table_base + (i%inline_table_size)];
651	1031	dat = rom[offset+i];
652		//printf("%02x, ",inlinet);
653	1032	dat -= inlinet;
654
655		dat = BITSWAP8(dat, 4,3,2,1,0,7,6,5);
656		if (dat != rawData[i]) printf("ERROR %d x %02x %02x\n", (i / 19)&1, dat, rawData[i]);
	1033	dat = shift_bits(dat, calc3_shift);
657	1034	}
658	1035	else
659	1036	{
660		~~UINT8 extra[] = { 0x14,0xf0,0xf8,0xd2,0xbe,0xfc,0xac,0x86,0x64,0x08,0x0c/,0x74,0xd6,0x6a,0x24,0x12,0x1a /};~~
	1037
661	1038	UINT8 inlinet = rom[inline_table_base + (i%inline_table_size)];
662	1039	dat = rom[offset+i];
663		dat -= inlinet;
664		dat -= extra[(i%inline_table_size)>>1];
665		dat = BITSWAP8(dat, 2,1,0,7,6,5,4,3);
666	1040
667		if (dat != rawData[i]) printf("ERROR %d y %02x %02x\n", (i / 19)&1, dat, rawData[i]);
	1041	if (extrasign==0)
	1042	{
	1043	dat -= inlinet;
	1044	dat -= extra[(i%inline_table_size)>>1];
	1045	}
	1046	else
	1047	{
	1048	dat += inlinet;
	1049	dat += extra[(i%inline_table_size)>>1];
	1050	}
668	1051
669		//dat = rawData[i];
670
	1052	dat = shift_bits(dat, 8-calc3_shift);
671	1053	}
672	1054	}
673	1055	else
r5534	r5535
677	1059	UINT8 inlinet = rom[inline_table_base + (i%inline_table_size)];
678	1060	dat = rom[offset+i];
679	1061	dat -= inlinet;
680
681		dat = BITSWAP8(dat, 4,3,2,1,0,7,6,5);
682		if (dat != rawData[i]) printf("ERROR %d x %02x %02x\n", (i / 19)&1, dat, rawData[i]);
	1062	dat = shift_bits(dat, calc3_shift);
683	1063	}
684	1064	else
685	1065	{
686		// shhould probably use the inline table somehow?
687
688		UINT8 extra[] = { 0x2f, 0x04, 0xd1, 0x69, 0xad, 0xeb, 0x10, 0x95,0xb0 };;
689	1066	dat = rom[offset+i];
690	1067
691		dat -= extra[(i%inline_table_size)>>1];
692		dat = BITSWAP8(dat, 2,1,0,7,6,5,4,3);
693
694		if (dat != rawData[i]) printf("ERROR %d y %02x %02x\n", (i / 19)&1, dat, rawData[i]);
	1068	if (extrasign==0)
	1069	{
	1070	dat -= extra2[(i%inline_table_size)>>1];
	1071	}
	1072	else
	1073	{
	1074	dat += extra2[(i%inline_table_size)>>1];
	1075	}
	1076	dat = shift_bits(dat, 8-calc3_shift);
695	1077	}
696	1078	}
697	1079	}
698		else if (tabnum==0x40) // fjbuster / shogun warriors japanese character select (what enables this extra?)
	1080	// the above rule doesn't work for this case... hmm ..
	1081	else if (tabnum==0x40 && !isbrap) // fjbuster / shogun warriors japanese character select (what enables this extra?)
699	1082	{
700	1083	UINT8 inlinet = rom[inline_table_base + (i%inline_table_size)];
701	1084	dat = rom[offset+i];
r5534	r5535
706	1089	// is relative to the start of the original table, and has a size of 0x11 (17) bytes which loop.
707	1090	if (((i%inline_table_size)&1)==0)
708	1091	{
709		// thie gets mapped over half the inline table?!.. (inline length is 0x22, this changes odd bytes)
710		// what specifies the additional overlay here?
711		UINT8 extra[0x11] = { 0x14,0xf0,0xf8,0xd2,0xbe,0xfc,0xac,0x86,0x64,0x08,0x0c,0x74,0xd6,0x6a,0x24,0x12,0x1a };
712	1092	dat -= extra[(i%inline_table_size)>>1];
	1093	}
	1094	}
	1095	else
	1096	{
	1097	if (i==1)
	1098	printf("unhandled inline case\n");
713	1099
	1100	}
	1101
	1102	if(local_counter>1)
	1103	{
	1104	if (space)
	1105	{
	1106	memory_write_byte(space, dstoffset+i, dat);
714	1107	}
715	1108
716
	1109	// debug, used to output tables at the start
	1110	if (dstram)
	1111	{
	1112	dstram[(dstoffset+i)^1] = dat;
	1113	}
717	1114	}
	1115	else
	1116	data_header[local_counter]=dat;
718	1117
719		~~dstr~~a~~m[(dst~~o~~ffse~~t~~+i)^1] = dat~~;
	1118	++local_counter;
720	1119	}
721	1120	}
722	1121	else
r5534	r5535
729	1128	// each key seems to relate directly to a 0x40 byte decryption table, only these ones handled so far
730	1129	if (calc3_decryption_key_byte == 0x01) key = calc3_key01;
731	1130	if (calc3_decryption_key_byte == 0x04) key = calc3_key04;
	1131	if (calc3_decryption_key_byte == 0x05) key = calc3_key05;
732	1132	if (calc3_decryption_key_byte == 0x15) key = calc3_key15;
733	1133	if (calc3_decryption_key_byte == 0x17) key = calc3_key17;
734	1134	if (calc3_decryption_key_byte == 0x19) key = calc3_key19;
	1135	if (calc3_decryption_key_byte == 0x22) key = calc3_key22;
735	1136	if (calc3_decryption_key_byte == 0x24) key = calc3_key24;
736	1137	if (calc3_decryption_key_byte == 0x31) key = calc3_key31;
737	1138	if (calc3_decryption_key_byte == 0x39) key = calc3_key39;
	1139	if (calc3_decryption_key_byte == 0x3f) key = calc3_key3f;
738	1140	if (calc3_decryption_key_byte == 0x80) key = calc3_key80;
739	1141	if (calc3_decryption_key_byte == 0x89) key = calc3_key89;
	1142	if (calc3_decryption_key_byte == 0xa1) key = calc3_keya1;
	1143	if (calc3_decryption_key_byte == 0xa7) key = calc3_keya7;
	1144	if (calc3_decryption_key_byte == 0xaf) key = calc3_keyaf;
740	1145	if (calc3_decryption_key_byte == 0xbc) key = calc3_keybc;
	1146	if (calc3_decryption_key_byte == 0xbf) key = calc3_keybf;
741	1147
742
743	1148	for (i=0;i<length;i++)
744	1149	{
745	1150
746	1151
747	1152	UINT8 dat = rom[offset+i];
748	1153
749		if (tabnum==0x12 && isbrap)
	1154	if ((tabnum==0x10 && isbrap) \|\|
	1155	(tabnum==0x13 && isbrap) \|\|
	1156	(tabnum==0x14 && isbrap) \|\|
	1157	(tabnum==0x15 && isbrap) \|\|
	1158	(tabnum==0x16 && isbrap) \|\|
	1159	(tabnum==0x18 && isbrap) \|\|
	1160	(tabnum==0x19 && isbrap) \|\|
	1161	(tabnum==0x1b && isbrap) \|\|
	1162	(tabnum==0x1c && isbrap) \|\|
	1163	(tabnum==0x1d && isbrap) \|\|
	1164	(tabnum==0x1f && isbrap) \|\|
	1165	(tabnum==0x20 && isbrap) \|\|
	1166	(tabnum==0x22 && isbrap) \|\|
	1167	(tabnum==0x23 && isbrap) \|\|
	1168	(tabnum==0x26 && isbrap) \|\|
	1169	(tabnum==0x27 && isbrap) \|\|
	1170	(tabnum==0x2a && isbrap) \|\|
	1171	(tabnum==0x41 && !isbrap))
750	1172	{
751		dat = BITSWAP8(dat, 4,3,2,1,0,7,6,5);
752		}
753		else if (tabnum==0x13 && isbrap)
754		{
755	1173	dat -= key[i&0x3f];
756	1174
757		if ((i&1)==0) dat = BITSWAP8(dat, 5,4,3,2,1,0,7,6);
758		else dat = BITSWAP8(dat, 1,0,7,6,5,4,3,2);
	1175	if ((i&1)==0) dat = shift_bits(dat, 8-calc3_shift);
	1176	else dat = shift_bits(dat, calc3_shift);
759	1177
760	1178	}
761		else if (tabnum==0x14 && isbrap)
	1179	else if ((tabnum==0x17 && isbrap) \|\|
	1180	(tabnum==0x29 && isbrap) \|\|
	1181	(tabnum==0x2b && isbrap) \|\|
	1182	(tabnum==0x2c && isbrap) \|\|
	1183	(tabnum==0x2d && isbrap))
762	1184	{
763		dat -= key[i&0x3f];
764		}
765		else if (tabnum==0x15 && isbrap)
766		{
767		dat -= key[i&0x3f];
	1185	if ((i&1)==0) dat += key[i&0x3f];
	1186	else dat -= key[i&0x3f];
768	1187
769		if ((i&1)==0) dat = BITSWAP8(dat, 2,1,0,7,6,5,4,3);
770		else dat = BITSWAP8(dat, 4,3,2,1,0,7,6,5);
771
772		//error 264 35 36 (typo, ignore)
	1188	if ((i&1)==0) dat = shift_bits(dat, 8-calc3_shift);
	1189	else dat = shift_bits(dat, calc3_shift);
773	1190	}
774		else if (tabnum==0x16 && isbrap)
	1191	else if ((tabnum==0x1e && isbrap) \|\|
	1192	(tabnum==0x80 && !isbrap))
775	1193	{
776		dat -= key[i&0x3f];
777		// error 1 02 should be 00 (the usual)
778		}
779		else if (tabnum==0x17 && isbrap)
780		{
781		// note we've seen this key (0x15) before, but again, here we have to add sometimes.. obviously a bit to control this..
782		if ((i&1)==0) dat += key[i&0x3f];
	1194	// note we've already seen this table, but like many others, it's + instead of - on some bytes..
	1195	if ((i&1)==1) dat += key[i&0x3f];
783	1196	else dat -= key[i&0x3f];
784	1197
785		if ((i&1)==0) dat = BITSWAP8(dat, 0,7,6,5,4,3,2,1);
786		else dat = BITSWAP8(dat, 6,5,4,3,2,1,0,7);
787
788		//error 1 02 should be 00 (the usual)
789		//error 390 02 should be 00 (typo, ignore)
790		//error 391 c6 should be 2c (typo, ignore)
791		//error 392 03 should be 60 (typo, ignore)
792		//error 393 60 should be 36 (typo, ignore)
	1198	if ((i&1)==0) dat = shift_bits(dat, 8-calc3_shift);
	1199	else dat = shift_bits(dat, calc3_shift);
793	1200	}
794		else if (tabnum==0x19 && isbrap)
	1201	else if (tabnum==0x12 && isbrap)
795	1202	{
796		dat -= key[i&0x3f];
797		// first 2 bytes were 00 in the returned data..
798		//if (i==1) dat=0x00;
	1203	// this one doesn't alternate the shifts... 'unknown' is 8
	1204	dat = BITSWAP8(dat, 4,3,2,1,0,7,6,5);
799	1205	}
800		else ~~if (tabnum==0x1f && isbrap)~~
	1206	else
801	1207	{
	1208	if (i==1) printf("unhandled non-inline case!\n");
	1209	// plain table case
802	1210	dat -= key[i&0x3f];
	1211	}
803	1212
804		if ((i&1)==0) dat = BITSWAP8(dat, 0,7,6,5,4,3,2,1);
805		else dat = BITSWAP8(dat, 6,5,4,3,2,1,0,7);
806		}
807		else if (tabnum==0x22 && isbrap)
	1213	if(local_counter>1)
808	1214	{
809
810		#if 0
	1215	if (space)
811	1216	{
812		UINT8 test;
813		UINT8 xxx;
814
815		if ((i&1)==1) xxx = BITSWAP8(rawData[i], 0,7,6,5,4,3,2,1);
816		else xxx = BITSWAP8(rawData[i], 6,5,4,3,2,1,0,7);
817
818		test= dat-xxx;
819
820		printf("%02x,%02x,%02x ",dat, rawData[i], test);
821
822		if ((i%0x40)==0x3f)
823		printf("\n");
824
825		//if (dat!=rawData[i]) printf("error %d %02x should be %02x\n",i, dat, rawData[i]);
	1217	memory_write_byte(space, dstoffset+i, dat);
826	1218	}
827		#endif
828		{
829		dat -= key[i&0x3f];
830	1219
831		if ((i&1)==0) dat = BITSWAP8(dat, 0,7,6,5,4,3,2,1);
832		else dat = BITSWAP8(dat, 6,5,4,3,2,1,0,7);
833		// first 2 bytes were 00 in the returned data..
834		//if (i==1) dat=0x00;
835		}
836
837
838		}
839		else if (tabnum==0x23 && isbrap)
840		{
841		dat -= key[i&0x3f];
842		// error 1 18 should be 00 (usual byte 1 'issue)
843		// error 384 98 should be 38 (typo, ignore)
844
845		}
846		else if (tabnum==0x80 && !isbrap) // shogwarr table 80 (irq code)
847		{
848		if ((i&1)==0)
	1220	// debug, used to output tables at the start
	1221	if (dstram)
849	1222	{
850		dat -= key[i&0x3f];
851		dat = BITSWAP8(dat,2,1,0,7,6,5,4,3);
	1223	dstram[(dstoffset+i)^1] = dat;
852	1224	}
853		else
854		{
855		// note + , not - (!!)
856		dat += key[i&0x3f];
857		dat = BITSWAP8(dat,4,3,2,1,0,7,6,5);
858		}
859	1225	}
860		else if (tabnum==0x41 && !isbrap) // shogwarr table 41 -- note fjbuster uses table 40, which looks like (almost) the same data but with better encryption...
861		{
862		// simple shifts... different direction for each alternating byte..
863		dat -= key[i&0x3f];
864
865		if ((i&1)==1) dat = BITSWAP8(dat,0,7,6,5,4,3,2,1);
866		else dat = BITSWAP8(dat,6,5,4,3,2,1,0,7);
867		}
868	1226	else
869		{
870		// plain table case
871		dat -= key[i&0x3f];
872		}
	1227	data_header[local_counter]=dat;
873	1228
	1229	++local_counter;
874	1230
875		dstram[(dstoffset+i)^1] = dat;
	1231	//dstram[(dstoffset+i)^1] = dat;
876	1232	}
877	1233	}
878	1234	}
r5534	r5535
886	1242
887	1243	}
888	1244
	1245
	1246
889	1247	DRIVER_INIT(calc3_scantables)
890	1248	{
891	1249	UINT8* rom = memory_region(machine,"cpu1");
r5534	r5535
898	1256	{
899	1257	calc3_mcu_crc+=rom[x];
900	1258	}
901		printf("crc %04x\n",calc3_mcu_crc);
	1259	//printf("crc %04x\n",calc3_mcu_crc);
902	1260	numregions = rom[0];
903	1261
904	1262	for (x=0;x<numregions;x++)
r5534	r5535
908	1266	memset(tmpdstram, 0x00,0x2000);
909	1267	length = calc3_decompress_table(machine, x, tmpdstram, 0);
910	1268
	1269	#if CALC3_VERBOSE_OUTPUT
911	1270	// dump to file
912	1271	if (length)
913	1272	{
r5534	r5535
934	1293	fclose(fp);
935	1294	}
936	1295	}
937
	1296	#endif
938	1297	free(tmpdstram);
939	1298	}
940	1299
r5534	r5535
943	1302	// to that extra block of data
944	1303
945	1304	// dump out the 0x1000 sized block at the end
	1305	#if CALC3_VERBOSE_OUTPUT
946	1306	{
947	1307	FILE *fp;
948	1308	char filename[256];
r5534	r5535
957	1317	fclose(fp);
958	1318	}
959	1319	}
	1320	#endif
960	1321	}
961	1322
962		UINT32 calc3_writeaddress;
963		UINT16 calc3_dsw_addr;
964		UINT16 calc3_eeprom_addr;
965		UINT16 calc3_poll_addr;
966		UINT16 cakc3_checkumaddress;
967	1323
	1324
968	1325	extern UINT16 calc3_mcu_crc;
969		extern UINT16* kaneko16_calc3_fakeram;
970		// from brap boys, might be polluted with shogun warriors values tho as was running shogun code at the time
971		static UINT16 kaneko16_eeprom_data[0x40] =
972		{
973		0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
974		0x0000, 0x0003, 0x0002, 0x1020, 0x0002, 0x6010, 0x0101, 0x0101,
975		0x0101, 0x0001, 0x0003, 0x0008, 0x4B41, 0x4E45, 0x4B4F, 0x2020,
976		0x4265, 0x2052, 0x6170, 0x2042, 0x6F79, 0x7300, 0x3030, 0x302E,
977		0x3038, 0x7FFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
978		0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
979		0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
980		0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x003B, 0xFFFF, 0xFFFF, 0xFFFF
981		};
982	1326
983		~~static~~ void calc3_mcu_run(running_machine *machine)
	1327	void calc3_mcu_run(running_machine *machine)
984	1328	{
985	1329	UINT16 mcu_command;
986	1330	int i;
	1331	const address_space *space = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
987	1332
988	1333	if ( calc3_mcu_status != (1\|2\|4\|8) ) return;
989	1334
	1335	if (calc3_dsw_addr) memory_write_byte(space, calc3_dsw_addr+0x200000, ( ~input_port_read(machine, "DSW1"))&0xff); // // DSW // dsw actually updates in realtime - mcu reads+writes it every frame
	1336
	1337
990	1338	//calc3_mcu_status = 0;
991	1339
992	1340	mcu_command = kaneko16_mcu_ram[calc3_mcu_command_offset/2 + 0];
r5534	r5535
1002	1350	/* 0xff is a special 'init' command */
1003	1351	if (mcu_command == 0xff)
1004	1352	{
	1353
1005	1354	// clear old command (handshake to main cpu)
1006	1355	kaneko16_mcu_ram[(calc3_mcu_command_offset>>1)+0] = 0x0000;
1007	1356
r5534	r5535
1014	1363	calc3_writeaddress = (kaneko16_mcu_ram[(0>>1) + 6] << 16) \|
1015	1364	(kaneko16_mcu_ram[(0>>1) + 7]);
1016	1365
	1366	// set our current write / stack pointer to the address specified
	1367	calc3_writeaddress_current = calc3_writeaddress;
	1368	#if CALC3_VERBOSE_OUTPUT
1017	1369	printf("Calc 3 Init Command - %04x DSW addr\n", calc3_dsw_addr);
1018	1370	printf("Calc 3 Init Command - %04x Eeprom Address\n", calc3_eeprom_addr);
1019	1371	printf("Calc 3 Init Command - %04x Future Commands Base\n", calc3_mcu_command_offset);
1020	1372	printf("Calc 3 Init Command - %04x Poll / Busy Address\n", calc3_poll_addr);
1021	1373	printf("Calc 3 Init Command - %04x ROM Checksum Address\n", cakc3_checkumaddress);
1022	1374	printf("Calc 3 Init Command - %08x Data Write Address\n", calc3_writeaddress);
	1375	#endif
	1376	// memory_write_byte(space, calc3_dsw_addr+0x200000, ( ~input_port_read(machine, "DSW1"))&0xff); // // DSW // dsw actually updates in realtime - mcu reads+writes it every frame
1023	1377
1024		kaneko16_mcu_ram[calc3_dsw_addr/2] = ~input_port_read(machine, "DSW1"); // DSW // dsw actually updates in realtime - mcu reads+writes it every frame
1025	1378	kaneko16_mcu_ram[cakc3_checkumaddress / 2] = calc3_mcu_crc; // MCU Rom Checksum!
1026	1379
1027		for (i=0;i<0x40;i++)
	1380	/*
	1381	for (i=0;i<0x40;i++)
	1382	{
	1383	kaneko16_mcu_ram[(calc3_eeprom_addr / 2)+i] = kaneko16_eeprom_data[i];//((eepromData[i]&0xff00)>>8) \| ((eepromData[i]&0x00ff)<<8);
	1384	}
	1385	*/
	1386
1028	1387	{
1029		kaneko16_mcu_ram[(calc3_eeprom_addr / 2)+i] = kaneko16_eeprom_data[i];//((eepromData[i]&0xff00)>>8) \| ((eepromData[i]&0x00ff)<<8);
	1388	UINT32 length, size;
	1389	UINT8 *dat;
	1390
	1391	dat = (UINT8 *)eeprom_get_data_pointer(&length, &size);
	1392
	1393	for (i=0;i<0x80;i++)
	1394	{
	1395	memory_write_byte(space, calc3_eeprom_addr+0x200000+i, dat[i]);
	1396	}
	1397
1030	1398	}
1031	1399
1032	1400	}
r5534	r5535
1046	1414	int param1 = kaneko16_mcu_ram[(calc3_mcu_command_offset>>1) + 1 + (2*i)];
1047	1415	int param2 = kaneko16_mcu_ram[(calc3_mcu_command_offset>>1) + 2 + (2*i)];
1048	1416	UINT8 commandtabl = (param1&0xff00) >> 8;
1049		UINT16 commandaddr = (param1&0x00ff) \| (param2&0xff00);
1050		UINT8 commandunk = (param2&0x00ff); // brap boys sets.. seems to cause further writebasck address displacement??
1051
1052		UINT32 fakeoffs;
1053
	1417	UINT16 commandaddr =param2;// (param1&0x00ff) \| (param2&0xff00);
	1418	UINT8 commandunk = (param1&0x00ff); // brap boys sets.. seems to cause further writebasck address displacement?? (when tested on hw it looked like a simple +, but that doesn't work for brapboys...)
	1419	#if CALC3_VERBOSE_OUTPUT
1054	1420	printf("transfer %d table %02x writeback address %04x unknown %02x\n", i, commandtabl, commandaddr, commandunk);
1055
1056		// the data SHOULD be written somewhere to main ram, probably related to the calc3_writeaddress set in command 0xff
1057		// but I'm not sure how, for now write it back to a FAKE region instead
1058		fakeoffs = 0x1e00*commandtabl;
1059		fakeoffs+=0xf00000;
1060
1061		// HACK HACK HACK, I don't know what commandunk does, but Brap Boys polls a table of addresses and doesn't do anything
1062		// more unless they change. The usual writeback address doesn't touch this table, so I think this unknown value must
1063		// cause an additional displacement to cause the writeback address to populate that table.. maybe
1064		if (commandunk == 0x30)
	1421	#endif
1065	1422	{
1066	1423	int length;
1067		commandaddr -= 0x60;
1068		length = calc3_decompress_table(machine, commandtabl, (UINT8*)kaneko16_mcu_ram, (calc3_writeaddress&0xffff)-2);
1069	1424
1070		printf("writing back address %08x to %08x\n", calc3_writeaddress, commandaddr);
1071		kaneko16_mcu_ram[(commandaddr>>1)+0] = (calc3_writeaddress>>16)&0xffff;
1072		kaneko16_mcu_ram[(commandaddr>>1)+1] = (calc3_writeaddress&0xffff);
1073		calc3_writeaddress += length;
	1425	length = calc3_decompress_table(machine, commandtabl, 0, calc3_writeaddress_current-2);
1074	1426
1075		}
1076		else if (commandunk == 0xa0)
1077		{
1078		int length;
1079		commandaddr -= 0x6d;
1080		length = calc3_decompress_table(machine, commandtabl, (UINT8*)kaneko16_mcu_ram, (calc3_writeaddress&0xffff)-2);
	1427	if (length)
	1428	{
	1429	int write=commandaddr;
	1430	#if CALC3_VERBOSE_OUTPUT
	1431	printf("writing back address %08x to %08x %08x\n", calc3_writeaddress_current, commandaddr,write);
	1432	#endif
1081	1433
1082		printf("writing back address %08x to %08x\n", calc3_writeaddress, commandaddr);
1083		kaneko16_mcu_ram[(commandaddr>>1)+0] = (calc3_writeaddress>>16)&0xffff;
1084		kaneko16_mcu_ram[(commandaddr>>1)+1] = (calc3_writeaddress&0xffff);
1085		calc3_writeaddress += length;
1086		}
1087		else if (commandunk == 0x98)
1088		{
1089		int length;
1090		commandaddr -= (0x6d+0xd);
1091		length = calc3_decompress_table(machine, commandtabl, (UINT8*)kaneko16_mcu_ram, (calc3_writeaddress&0xffff)-2);
	1434	//memory_write_byte(space,write+0x200001, data_header[0]); // maybe not.. check first boss brapboysj
	1435	memory_write_byte(space,write+0x200001, data_header[1]);
1092	1436
1093		printf("writing back address %08x to %08x\n", calc3_writeaddress, commandaddr);
1094		kaneko16_mcu_ram[(commandaddr>>1)+0] = (calc3_writeaddress>>16)&0xffff;
1095		kaneko16_mcu_ram[(commandaddr>>1)+1] = (calc3_writeaddress&0xffff);
1096		calc3_writeaddress += length;
1097		}
	1437	write=commandaddr+(char)commandunk;
	1438	memory_write_word(space,write+0x200000, (calc3_writeaddress_current>>16)&0xffff);
	1439	memory_write_word(space,write+0x200002, (calc3_writeaddress_current&0xffff));
	1440
	1441	calc3_writeaddress_current += ((length+3)&(~1));
	1442	}
1098	1443
1099
1100		else
1101		{
1102		calc3_decompress_table(machine, commandtabl, (UINT8*)kaneko16_calc3_fakeram, fakeoffs&0xfffff);
1103
1104		// write back WHERE we wrote the data to the address specified so that the code can jump to it etc.
1105		fakeoffs+=2;// the first 2 bytes don't seem to be the offset it expects to jump to..
1106
1107		printf("writing back fake address %08x to %08x\n", fakeoffs, commandaddr);
1108		kaneko16_mcu_ram[(commandaddr>>1)+0] = (fakeoffs>>16)&0xffff;
1109		kaneko16_mcu_ram[(commandaddr>>1)+1] = (fakeoffs&0xffff);
1110	1444	}
1111	1445	}
1112
1113
1114	1446	}
1115	1447	}
1116	1448	}

src/mame/mamedriv.c
r5534	r5535
3026	3026	DRIVER( shangtou ) /* 2002.02 Shanghai Sangokuhaitougi */
3027	3027	DRIVER( xiistag ) /* 2002.07 XII Stag (V2.01J) */
3028	3028	DRIVER( sianniv ) /* 2003.10 Space Invaders Anniversary (V2.02J) */
3029		DRIVER( kollon ) /* 2003.11 Kollon */
	3029	DRIVER( kollon ) /* 2003.11 Kollon (V2.04J) */
	3030	DRIVER( kollonc ) /* 2003.11 Kollon (V2.04JC, Compact Flash version) */
3030	3031	DRIVER( zooo ) /* 2004.05 Zooo */
3031	3032
3032	3033	/* Namco System 11 */
r5534	r5535
4263	4264	/* 16 */
4264	4265	/* 17 */
4265	4266	/* 18 */
4266		/* 19 */
	4267	DRIVER( mt_gfoot ) /* 19 */
4267	4268	DRIVER( mt_lastb ) /* 20 */
4268	4269	DRIVER( mt_wcsoc ) /* 21 */
4269	4270	DRIVER( mt_tetri ) /* 22 */
r5534	r5535
6733	6734	DRIVER( strkforc ) /* (c) 1991 Midway */
6734	6735	DRIVER( mk ) /* (c) 1992 Midway */
6735	6736	DRIVER( mkr4 ) /* (c) 1992 Midway */
	6737	DRIVER( mkturbo ) /* bootleg */
6736	6738	DRIVER( mkprot8 ) /* (c) 1992 Midway */
6737	6739	DRIVER( mkprot9 ) /* (c) 1992 Midway */
6738	6740	DRIVER( mkla1 ) /* (c) 1992 Midway */
r5534	r5535
6849	6851	DRIVER( tm7ka ) /* (c) 1999 Midway Games */
6850	6852	DRIVER( tm7keval ) /* (c) 1999 Midway Games */
6851	6853	DRIVER( tm8k ) /* (c) 2000 Midway Games */
6852		DRIVER( galgbios ) /* (c) 1998 Creative Electonics & Software (CES) */
	6854	DRIVER( galgbios ) /* (c) 1998 Creative Electronics & Software (CES) */
	6855	DRIVER( galgame2 ) /* (c) 1998 Creative Electronics & Software (CES) / Namco */
6853	6856
6854	6857	/* Cinematronics raster games */
6855	6858	DRIVER( embargo )
r5534	r5535
6918	6921	/* TIA-MC1 hardware games */
6919	6922	DRIVER( konek ) /* (c) 1988 Terminal */
6920	6923	DRIVER( sosterm ) /* (c) 1988 Terminal */
	6924	DRIVER( bilyard ) /* (c) 1988 Terminal */
6921	6925
6922	6926	/* Photon hardware games */
6923	6927	DRIVER( phtetris )
r5534	r5535
8737	8741	DRIVER( spitboss ) /* (c) 1988 Merit */
8738	8742	DRIVER( pitbosss ) /* (c) 1990 Merit */
8739	8743	DRIVER( pitbossm ) /* (c) 1994 Merit */
	8744	DRIVER( pitbossma ) /* (c) 1994 Merit */
8740	8745	DRIVER( pbst30 ) /* (c) 1994 Merit */
8741	8746	DRIVER( pbst30b ) /* (c) 1993 Merit */
8742	8747	DRIVER( megat3 ) /* (c) 1996 Merit */
r5534	r5535
9494	9499
9495	9500	/* Hi-Lo Poker-based */
9496	9501	DRIVER( gtipoker ) /* (c) 1983 GTI Inc */
9497		DRIVER( norautp ) /* (c) 1988? Noraut */
9498		DRIVER( norautjp ) /* (c) 1988? Noraut */
	9502	DRIVER( norautp ) /* (c) 1988? Noraut Ltd */
	9503	DRIVER( norautjp ) /* (c) 1988? Noraut Ltd */
	9504	DRIVER( norautrh ) /* (c) 1988? Noraut Ltd */
	9505	DRIVER( norautu ) /* (c) 1988? Noraut Ltd */
	9506	DRIVER( norautv3 ) /* (c) 1988? Noraut Ltd */
9499	9507	DRIVER( norautpn ) /* (c) 1990? unknown */
9500	9508
9501	9509	/* Sanki Denshi Kogyo */

src/mame/includes/bzone.h
r5534	r5535
4	4
5	5	*************************************************************************/
6	6
	7	#define BZONE_DISCRETE (1)
7	8
	9	#define BZONE_MASTER_CLOCK (XTAL_12_096MHz)
	10	#define BZONE_CLOCK_3KHZ (MASTER_CLOCK / 4096)
	11
8	12	/----------- defined in drivers/bzone.c -----------/
9	13
10	14	extern UINT8 rb_input_select;
r5534	r5535
12	16
13	17	/----------- defined in audio/bzone.c -----------/
14	18
	19	#if BZONE_DISCRETE
	20
	21	WRITE8_DEVICE_HANDLER( bzone_sounds_w );
	22
	23	MACHINE_DRIVER_EXTERN( bzone_audio );
	24	#else
15	25	WRITE8_HANDLER( bzone_sounds_w );
16	26
17	27	DEVICE_GET_INFO( bzone_sound );
18	28	#define SOUND_BZONE DEVICE_GET_INFO_NAME(bzone_sound)
	29	#endif
19	30
20
21	31	/----------- defined in audio/redbaron.c -----------/
22	32
23	33	WRITE8_HANDLER( redbaron_sounds_w );

src/mame/includes/midtunit.h
r5534	r5535
15	15	READ16_HANDLER( midtunit_input_r );
16	16
17	17	DRIVER_INIT( mktunit );
	18	DRIVER_INIT( mkturbo );
18	19	DRIVER_INIT( jdreddp );
19	20	DRIVER_INIT( nbajam );
20	21	DRIVER_INIT( nbajamte );

src/mame/includes/kaneko16.h
r5534	r5535
63	63	/* Sprites: */
64	64
65	65	extern int kaneko16_sprite_type;
	66	extern int kaneko16_sprite_fliptype;
66	67	extern UINT16 kaneko16_sprite_xoffs, kaneko16_sprite_flipx;
67	68	extern UINT16 kaneko16_sprite_yoffs, kaneko16_sprite_flipy;
68	69	extern UINT16 *kaneko16_sprites_regs;

src/mame/includes/phoenix.h
r5534	r5535
	1	#include "devcb.h"
1	2	#include "sound/discrete.h"
2	3
3	4
r5534	r5535
73	74	READ8_HANDLER( survival_input_port_0_r );
74	75	READ8_DEVICE_HANDLER( survival_protection_r );
75	76
76		~~int~~ survival_sid_callback~~( const device_config *device~~ );
	77	READ_LINE_DEVICE_HANDLER( survival_sid_callback );
77	78

src/mame/includes/taito_f2.h
r5534	r5535
36	36	VIDEO_UPDATE( taitof2 );
37	37	VIDEO_UPDATE( taitof2_pri );
38	38	VIDEO_UPDATE( taitof2_pri_roz );
39		VIDEO_UPDATE( ssi );
40		VIDEO_UPDATE( thundfox );
41		VIDEO_UPDATE( deadconx );
42		VIDEO_UPDATE( metalb );
43		VIDEO_UPDATE( yesnoj );
	39	VIDEO_UPDATE( taitof2_driftout );
	40	VIDEO_UPDATE( taitof2_ssi );
	41	VIDEO_UPDATE( taitof2_thundfox );
	42	VIDEO_UPDATE( taitof2_deadconx );
	43	VIDEO_UPDATE( taitof2_metalb );
	44	VIDEO_UPDATE( taitof2_yesnoj );
44	45
45	46	WRITE16_HANDLER( taitof2_spritebank_w );
46	47	READ16_HANDLER ( koshien_spritebank_r );
47	48	WRITE16_HANDLER( koshien_spritebank_w );
48	49	WRITE16_HANDLER( taitof2_sprite_extension_w );
	50	WRITE16_HANDLER( taitof2_palette_w );

src/mame/includes/snes.h
r5534	r5535
371	371	HAS_ST018,
372	372	HAS_SPC7110,
373	373	HAS_SPC7110_RTC,
	374	HAS_CX4,
374	375	HAS_UNK
375	376	};
376	377

src/mame/mame.mak
r5534	r5535
114	114	CPUS += AVR8
115	115	CPUS += TMS0980
116	116	CPUS += I4004
	117	CPUS += SUPERFX
117	118
118	119
119	120	#-------------------------------------------------
r5534	r5535
1749	1750
1750	1751	$(DRIVERS)/neogeo.o: $(LAYOUT)/neogeo.lh
1751	1752
	1753	$(DRIVERS)/norautp.o: $(LAYOUT)/noraut11.lh \
	1754	$(LAYOUT)/noraut12.lh
	1755
1752	1756	$(DRIVERS)/overdriv.o: $(LAYOUT)/overdriv.lh
1753	1757
1754	1758	$(DRIVERS)/peplus.o: $(LAYOUT)/peplus.lh \
r5534	r5535
1841	1845	$(DRIVERS)/galaxian.o: $(MAMESRC)/drivers/galdrvr.c
1842	1846	$(DRIVERS)/mpu4.o: $(MAMESRC)/drivers/mpu4drvr.c
1843	1847	$(DRIVERS)/neogeo.o: $(MAMESRC)/drivers/neodrvr.c
	1848	$(MACHINE)/snes.o: $(MAMESRC)/machine/snesdsp1.c \
	1849	$(MAMESRC)/machine/snesdsp2.c \
	1850	$(MAMESRC)/machine/snesobc1.c

src/mame/video/kaneko16.c
r5534	r5535
49	49	UINT16* galsnew_fg_pixram;
50	50
51	51	int kaneko16_sprite_type;
	52	int kaneko16_sprite_fliptype;
52	53	static int kaneko16_keep_sprites = 0; // default disabled for games not using it
53	54	UINT16 kaneko16_sprite_xoffs, kaneko16_sprite_flipx;
54	55	UINT16 kaneko16_sprite_yoffs, kaneko16_sprite_flipy;
r5534	r5535
579	580	else
580	581	code = s->code; // .. or latch this value
581	582
	583
582	584	if (flags & USE_LATCHED_COLOR)
583	585	{
584	586	s->color = color;
585	587	s->priority = priority;
586	588	s->xoffs = xoffs;
587	589	s->yoffs = yoffs;
588		s->flipx = flipx;
589		s->flipy = flipy;
	590
	591	if (kaneko16_sprite_fliptype==0)
	592	{
	593	s->flipx = flipx;
	594	s->flipy = flipy;
	595	}
590	596	}
591	597	else
592	598	{
r5534	r5535
594	600	priority = s->priority;
595	601	xoffs = s->xoffs;
596	602	yoffs = s->yoffs;
	603
	604	if (kaneko16_sprite_fliptype==0)
	605	{
	606	flipx = s->flipx;
	607	flipy = s->flipy;
	608	}
	609	}
	610
	611	// brap boys explicitly doesn't want the flip to be latched, maybe there is a different bit to enable that behavior?
	612	if (kaneko16_sprite_fliptype==1)
	613	{
597	614	flipx = s->flipx;
598	615	flipy = s->flipy;
599	616	}

src/mame/video/leland.c
r5534	r5535
55	55	int scanline = param;
56	56
57	57	/* update the DACs */
58
59	58	if (!(leland_dac_control & 0x01))
60	59	leland_dac_update(0, leland_video_ram[(last_scanline) * 256 + 160]);
61	60
r5534	r5535
66	65
67	66	scanline = (scanline+1) % 256;
68	67
69		if (scanline == 0)
70		{
71		/* turn off the DACs at the start of the frame */
72		leland_dac_control = 3;
73		}
74
75	68	/* come back at the next appropriate scanline */
76	69	timer_adjust_oneshot(scanline_timer, video_screen_get_time_until_pos(machine->primary_screen, scanline, 0), scanline);
77	70	}

src/mame/video/jagobj.c
r5534	r5535
80	80	{
81	81	if (firstpix & 7)
82	82	{
83		UINT32 pixsrc = src[firstpix >> 3];
	83	UINT32 pixsrc = src[firstpix / 8];
84	84	while (firstpix & 7)
85	85	{
86		int pix = (pixsrc >> ((~firstpix & 7) ~~<< 2~~)) & 0x0f;
	86	int pix = (pixsrc >> (4 * (~firstpix & 7))) & 0x0f;
87	87	if ((!(flags & 4) \|\| pix) && (UINT32)xpos < 760)
88	88	{
89	89	if (!(flags & 2))
r5534	r5535
96	96	}
97	97	}
98	98
99		firstpix >>= 3;
100		iwidth >>= 3;
	99	firstpix /= 8;
	100	iwidth /= 8;
101	101	iwidth -= firstpix;
102	102
103	103	while (iwidth-- > 0)
r5534	r5535
178	178	xpos += dxpos;
179	179	}
180	180	else
181		xpos += dxpos ~~<< 3~~;
	181	xpos += 8 * dxpos;
182	182	}
183	183	}
184	184
r5534	r5535
246	246	{
247	247	if (firstpix & 3)
248	248	{
249		UINT32 pixsrc = src[firstpix >> 2];
	249	UINT32 pixsrc = src[firstpix / 4];
250	250	while (firstpix & 3)
251	251	{
252		UINT8 pix = pixsrc >> ((~firstpix & 3) ~~<< 3~~);
	252	UINT8 pix = pixsrc >> (8 * (~firstpix & 3));
253	253	if ((!(flags & 4) \|\| pix) && (UINT32)xpos < 760)
254	254	{
255	255	if (!(flags & 2))
r5534	r5535
262	262	}
263	263	}
264	264
265		firstpix >>= 2;
266		iwidth >>= 2;
	265	firstpix /= 4;
	266	iwidth /= 4;
267	267	iwidth -= firstpix;
268	268
269	269	while (iwidth-- > 0)
r5534	r5535
308	308	xpos += dxpos;
309	309	}
310	310	else
311		xpos += dxpos ~~<< 2~~;
	311	xpos += 4 * dxpos;
312	312	}
313	313	}
314	314
r5534	r5535
376	376	{
377	377	if (firstpix & 1)
378	378	{
379		UINT16 pix = src[firstpix >> 1];
	379	UINT16 pix = src[firstpix / 2];
380	380	if ((!(flags & 4) \|\| pix) && (UINT32)xpos < 760)
381	381	{
382	382	if (!(flags & 2))
r5534	r5535
387	387	xpos += dxpos;
388	388	}
389	389
390		firstpix >>= 1;
391		iwidth >>= 1;
	390	firstpix /= 2;
	391	iwidth /= 2;
392	392	iwidth -= firstpix;
393	393
394	394	while (iwidth-- > 0)
r5534	r5535
415	415	xpos += dxpos;
416	416	}
417	417	else
418		xpos += dxpos ~~<< 1~~;
	418	xpos += 2 * dxpos;
419	419	}
420	420	}
421	421
r5534	r5535
473	473
474	474
475	475
476
477
478		/*************************************
479		*
480		* 32bpp bitmap renderers - needs to be verified
481		*
482		*************************************/
483
484		INLINE void bitmap_32_draw(INT32 firstpix, INT32 iwidth, UINT32 *src, INT32 xpos, UINT8 flags, INT32 dxpos)
485		{
486		iwidth -= firstpix;
487
488		while (iwidth-- > 0)
489		{
490		UINT32 pix = src[firstpix++];
491
492		if (xpos < 760)
493		{
494		scanline[xpos++] = (pix&0xffff0000)>>16;
495		scanline[xpos++] = pix&0xffff;
496		}
497		}
498		}
499
500		static void bitmap_32_0(INT32 firstpix, INT32 iwidth, UINT32 *src, INT32 xpos)
501		{
502		bitmap_32_draw(firstpix, iwidth, src, xpos, 0, 1);
503		}
504
505		static void bitmap_32_1(INT32 firstpix, INT32 iwidth, UINT32 *src, INT32 xpos)
506		{
507		bitmap_32_draw(firstpix, iwidth, src, xpos, 1, -1);
508		}
509
510		static void bitmap_32_2(INT32 firstpix, INT32 iwidth, UINT32 *src, INT32 xpos)
511		{
512		bitmap_32_draw(firstpix, iwidth, src, xpos, 2, 1);
513		}
514
515		static void bitmap_32_3(INT32 firstpix, INT32 iwidth, UINT32 *src, INT32 xpos)
516		{
517		bitmap_32_draw(firstpix, iwidth, src, xpos, 3, -1);
518		}
519
520		static void bitmap_32_4(INT32 firstpix, INT32 iwidth, UINT32 *src, INT32 xpos)
521		{
522		bitmap_32_draw(firstpix, iwidth, src, xpos, 4, 1);
523		}
524
525		static void bitmap_32_5(INT32 firstpix, INT32 iwidth, UINT32 *src, INT32 xpos)
526		{
527		bitmap_32_draw(firstpix, iwidth, src, xpos, 5, -1);
528		}
529
530		static void bitmap_32_6(INT32 firstpix, INT32 iwidth, UINT32 *src, INT32 xpos)
531		{
532		bitmap_32_draw(firstpix, iwidth, src, xpos, 6, 1);
533		}
534
535		static void bitmap_32_7(INT32 firstpix, INT32 iwidth, UINT32 *src, INT32 xpos)
536		{
537		bitmap_32_draw(firstpix, iwidth, src, xpos, 7, -1);
538		}
539
540		static void (const bitmap32[8])(INT32, INT32, UINT32 , INT32) =
541		{
542		bitmap_32_0,
543		bitmap_32_1,
544		bitmap_32_2,
545		bitmap_32_3,
546		bitmap_32_4,
547		bitmap_32_5,
548		bitmap_32_6,
549		bitmap_32_7
550		};
551
552
553
554	476	INLINE UINT8 lookup_pixel(const UINT32 *src, int i, int pitch, int depth)
555	477	{
556		int ppl = 32 / depth;
557		UINT32 data = src[((i & ppl) / ppl) + ((i / (ppl<<1)) * (pitch<<1))];
558		UINT8 pix = (data >> ((~i & (ppl-1)) * depth)) & ((1 << depth) - 1);
	478	int ppl = 32 / depth;
	479	UINT32 data = src[((i & ppl) / ppl) + ((i / (ppl2)) 2 * pitch)];
	480	UINT8 pix = (data >> ((~i & (ppl-1)) * depth)) & ((1 << depth) - 1);
559	481	return pix;
560	482	}
561	483
r5534	r5535
612	534	UINT32 dwidth = (lower2 >> 18) & 0x3ff;
613	535	UINT32 iwidth = ((lower2 >> 28) \| ((upper2 & 0x3f) << 4)) << (6 - depthlog);
614	536	UINT8 _index = (upper2 >> 5) & 0xfe;
615		UINT8 flags = (upper2 >> 13) & 0x07;
616		UINT8 firstpix = ((upper2 >> 17) & 0x3f) >> depthlog;
	537	UINT8 flags = (upper2 >> 13) & 0x0f;
	538	UINT8 firstpix = ((upper2 >> 17) & 0x1f) >> depthlog;
617	539	int i, dxpos = (flags & 1) ? -1 : 1;
618	540
619	541	/* preadjust for firstpix */
r5534	r5535
625	547	/* 1bpp case */
626	548	case 0:
627	549	{
628		UINT16 clut = (UINT16 )jaguar_gpu_clut + _index;
	550	UINT16 clut = (UINT16 )jaguar_gpu_clut;
	551	clut += _index & 0xfe;
629	552
630	553	/* non-blending */
631	554	if (!(flags & 2))
r5534	r5535
658	581	/* 2bpp case */
659	582	case 1:
660	583	{
661		UINT16 clut = (UINT16 )jaguar_gpu_clut + (_index & 0xfc);
	584	UINT16 clut = (UINT16 )jaguar_gpu_clut;
	585	clut += _index & 0xfc;
662	586
663	587	/* non-blending */
664	588	if (!(flags & 2))
r5534	r5535
694	618	if (pitch != 1)
695	619	logerror("Unhandled pitch = %d\n", pitch);
696	620
697		clutbase = (UINT16 *)jaguar_gpu_clut + (_index & 0xf8);
698		(*bitmap4[flags])(firstpix, iwidth, src, xpos);
	621	clutbase = (UINT16 *)jaguar_gpu_clut + (_index & 0xf0);
	622	(*bitmap4[flags & 7])(firstpix, iwidth, src, xpos);
699	623	break;
700	624
701	625	/* 8bpp case */
r5534	r5535
705	629	logerror("Unhandled pitch = %d\n", pitch);
706	630
707	631	clutbase = (UINT16 *)jaguar_gpu_clut;
708		(*bitmap8[flags])(firstpix, iwidth, src, xpos);
	632	(*bitmap8[flags & 7])(firstpix, iwidth, src, xpos);
709	633	break;
710	634
711	635	/* 16bpp case */
r5534	r5535
714	638	if (pitch != 1)
715	639	logerror("Unhandled pitch = %d\n", pitch);
716	640
717		(*bitmap16[flags])(firstpix, iwidth, src, xpos);
	641	(*bitmap16[flags & 7])(firstpix, iwidth, src, xpos);
718	642	break;
719	643
720		/* 32bpp case */
721		case 5:
722		/* only handle pitch=1 for now */
723		if (pitch != 1)
724		logerror("Unhandled pitch = %d\n", pitch);
725
726		(*bitmap32[flags])(firstpix, iwidth, src, xpos);
727		break;
728
729	644	default:
730	645	fprintf(stderr, "Unhandled bitmap source depth = %d\n", depthlog);
731	646	break;
r5534	r5535
800	715	UINT32 dwidth = (lower2 >> 18) & 0x3ff;
801	716	INT32 iwidth = ((lower2 >> 28) \| ((upper2 & 0x3f) << 4)) << (6 - depthlog);
802	717	UINT8 _index = (upper2 >> 5) & 0xfe;
803		UINT8 flags = (upper2 >> 13) & 0x07;
804		UINT8 firstpix = ((upper2 >> 17) & 0x3f) >> depthlog;
	718	UINT8 flags = (upper2 >> 13) & 0x0f;
	719	UINT8 firstpix = ((upper2 >> 17) & 0x1f) >> depthlog;
805	720
806	721	INT32 hscale = lower3 & 0xff;
807	722	INT32 vscale = (lower3 >> 8) & 0xff;
r5534	r5535
809	724	int dxpos = (flags & 1) ? -1 : 1;
810	725	int xpix = firstpix, yinc;
811	726
812		/* only handle pitch=~~1 (sequential data)~~ for now */
	727	/* only handle pitch=0 for now */
813	728	if (pitch != 1)
814	729	logerror("Unhandled pitch = %d\n", pitch);
815	730	if (flags & 2)
r5534	r5535
827	742	/* switch off the depth */
828	743	switch (depthlog)
829	744	{
830		case 0:
831		{
832		UINT16 clut = (UINT16 )jaguar_gpu_clut + _index;
833
834		/* render in phrases */
835		while (xpix < iwidth)
836		{
837		UINT16 pix = (src[xpix >> 5] >> (~xpix & 31)) & 0x01;
838
839		while (xleft > 0)
840		{
841		if (xpos >= 0 && xpos < 760 && (pix \|\| !(flags & 4)))
842		scanline[xpos] = clut[BYTE_XOR_BE(pix)];
843		xpos += dxpos;
844		xleft -= 0x20;
845		}
846		while (xleft <= 0)
847		xleft += hscale, xpix++;
848		}
849		break;
850		}
851
852		case 1:
853		{
854		UINT16 clut = (UINT16 )jaguar_gpu_clut + (_index & 0xfc);
855
856		/* render in phrases */
857		while (xpix < iwidth)
858		{
859		UINT16 pix = (src[xpix >> 4] >> ((~xpix & 15) << 1)) & 0x03;
860
861		while (xleft > 0)
862		{
863		if (xpos >= 0 && xpos < 760 && (pix \|\| !(flags & 4)))
864		scanline[xpos] = clut[BYTE_XOR_BE(pix)];
865		xpos += dxpos;
866		xleft -= 0x20;
867		}
868		while (xleft <= 0)
869		xleft += hscale, xpix++;
870		}
871		break;
872		}
873
874	745	case 2:
875	746	{
876		UINT16 clut = (UINT16 )jaguar_gpu_clut + (_index & 0xf8);
	747	UINT16 clut = (UINT16 )jaguar_gpu_clut;
	748	clut += _index & 0xf0;
877	749
878	750	/* render in phrases */
879	751	while (xpix < iwidth)
880	752	{
881		UINT16 pix = (src[xpix >> 3] >> ((~xpix & 7) << 2)) & 0x0f;
	753	UINT16 pix = (src[xpix / 8] >> ((~xpix & 7) * 4)) & 0x0f;
882	754
883	755	while (xleft > 0)
884	756	{
r5534	r5535
900	772	/* render in phrases */
901	773	while (xpix < iwidth)
902	774	{
903		UINT16 pix = (src[xpix >> 2] >> ((~xpix & 3) << 3)) & 0xff;
	775	UINT16 pix = (src[xpix / 4] >> ((~xpix & 3) * 8)) & 0xff;
904	776
905	777	while (xleft > 0)
906	778	{
r5534	r5535
918	790	case 4:
919	791	while (xpix < iwidth)
920	792	{
921		UINT16 pix = src[xpix >> 1] >> ((~xpix & 1) << 4);
	793	UINT16 pix = src[xpix / 2] >> ((~xpix & 1) * 16);
922	794
923	795	while (xleft > 0)
924	796	{
r5534	r5535
1065	937
1066	938	/* GPU interrupt */
1067	939	case 2:
1068		gpu_regs[OB_HH]=(objdata[1]&0xffff0000)>>16;
1069		gpu_regs[OB_HL]=objdata[1]&0xffff;
1070		gpu_regs[OB_LH]=(objdata[0]&0xffff0000)>>16;
1071		gpu_regs[OB_LL]=objdata[0]&0xffff;
	940	gpu_regs[OB_HH]=objdata[1];
	941	gpu_regs[OB_HL]=objdata[2];
	942	gpu_regs[OB_LH]=objdata[3];
	943	gpu_regs[OB_LL]=objdata[4];
1072	944	cpu_irq_state \|= 2;
1073	945	update_cpu_irq(machine);
1074	946	done=1;

src/mame/video/snes.c
r5534	r5535
167	167	b = ((*colour & 0x7c00) >> 10) + ((scanlines[SUBSCREEN].buffer[offset] & 0x7c00) >> 10);
168	168
169	169	/* don't halve for the back colour */
170		if( (snes_ram[CGADSUB] & 0x40) && (scanlines[SUBSCREEN].zbuf[offset] \|\| scanlines[SUBSCREEN].buffer[offset]) )
	170	if( (snes_ram[CGADSUB] & 0x40) && (scanlines[SUBSCREEN].zbuf[offset] \|\| scanlines[SUBSCREEN].buffer[offset] != snes_cgram[FIXED_COLOUR]) )
171	171	{
172	172	r >>= 1;
173	173	g >>= 1;
r5534	r5535
181	181	b = ((*colour & 0x7c00) >> 10) + ((snes_cgram[FIXED_COLOUR] & 0x7c00) >> 10);
182	182
183	183	/* don't halve for the back colour */
184		if( (snes_ram[CGADSUB] & 0x40) && (scanlines[SUBSCREEN].zbuf[offset] \|\| scanlines[SUBSCREEN].buffer[offset]) )
	184	if( (snes_ram[CGADSUB] & 0x40) && (scanlines[SUBSCREEN].zbuf[offset] \|\| scanlines[SUBSCREEN].buffer[offset] != snes_cgram[FIXED_COLOUR]) )
185	185	{
186	186	r >>= 1;
187	187	g >>= 1;
r5534	r5535
205	205	if( b > 0x1f ) b = 0;
206	206
207	207	/* don't halve for the back colour */
208		if( (snes_ram[CGADSUB] & 0x40) && (scanlines[SUBSCREEN].zbuf[offset] \|\| scanlines[SUBSCREEN].buffer[offset]) )
	208	if( (snes_ram[CGADSUB] & 0x40) && (scanlines[SUBSCREEN].zbuf[offset] \|\| scanlines[SUBSCREEN].buffer[offset] != snes_cgram[FIXED_COLOUR]) )
209	209	{
210	210	r >>= 1;
211	211	g >>= 1;
r5534	r5535
222	222	if( b > 0x1f ) b = 0;
223	223
224	224	/* don't halve for the back colour */
225		if( (snes_ram[CGADSUB] & 0x40) && (scanlines[SUBSCREEN].zbuf[offset] \|\| scanlines[SUBSCREEN].buffer[offset]) )
	225	if( (snes_ram[CGADSUB] & 0x40) && (scanlines[SUBSCREEN].zbuf[offset] \|\| scanlines[SUBSCREEN].buffer[offset] != snes_cgram[FIXED_COLOUR]) )
226	226	{
227	227	r >>= 1;
228	228	g >>= 1;

src/mame/video/jaguar.c
r5534	r5535
424	424	{
425	425	/* YCC full */
426	426	case 0x000:
427		/* RGB24 */
428		case 0x002:
429	427	for (i = 0; i < 65536; i++)
430	428	{
431	429	UINT8 r = (red_lookup[i >> 8] * (i & 0xff)) >> 8;
r5534	r5535
467	465	/* others */
468	466	default:
469	467	logerror("Can't handle mode %X\n", vmode);
470		fprintf(stderr, "Can't handle mode %X\n", vmode);
471	468	break;
472	469	}
473	470	}
r5534	r5535
598	595	switch (offset)
599	596	{
600	597	case B_CMD: /* B_CMD */
601		return 1;
	598	return 0x00000001;
602	599
603	600	default:
604	601	logerror("%08X:Blitter read register @ F022%02X\n", cpu_get_previouspc(space->cpu), offset * 4);
r5534	r5535
646	643	return gpu_regs[offset];
647	644	}
648	645
649		static TIMER_CALLBACK( jaguar_pit )
650		{
651		attotime sample_period;
652		cpu_irq_state \|= 8;
653		update_cpu_irq(machine);
654	646
655		if (gpu_regs[PIT0])
656		{
657		sample_period = ATTOTIME_IN_NSEC(cpu_get_clock(cputag_get_cpu(machine,"gpu")) / (1+gpu_regs[PIT0]) / (1+gpu_regs[PIT1]));
658		// timer_set(machine, sample_period, NULL, 0, jaguar_pit);
659		}
660		}
661
662	647	WRITE16_HANDLER( jaguar_tom_regs_w )
663	648	{
664	649	UINT32 reg_store = gpu_regs[offset];
665		~~attotime sample_period;~~
	650
666	651	if (offset < GPU_REGS)
667	652	{
668	653	COMBINE_DATA(&gpu_regs[offset]);
669	654
670	655	switch (offset)
671	656	{
672		case PIT1:
673		if (gpu_regs[PIT0])
674		{
675		sample_period = ATTOTIME_IN_NSEC(cpu_get_clock(cputag_get_cpu(space->machine,"gpu")) / (1+gpu_regs[PIT0]) / (1+gpu_regs[PIT1]));
676		timer_set(space->machine, sample_period, NULL, 0, jaguar_pit);
677		}
678		break;
679	657	case INT1:
680	658	cpu_irq_state &= ~(gpu_regs[INT1] >> 8);
681	659	update_cpu_irq(space->machine);
r5534	r5535
709	687	int hbend = effective_hvalue(ENABLE_BORDERS ? gpu_regs[HBE] : MIN(gpu_regs[HDB1], gpu_regs[HDB2]));
710	688	int hbstart = effective_hvalue(gpu_regs[ENABLE_BORDERS ? HBB : HDE]);
711	689	int vperiod = (gpu_regs[VP] & 0x7ff) + 1;
712		int vbend = ~~MAX(~~gpu_regs[VBE]~~,gpu_regs[VDB])~~ & 0x7ff;
	690	int vbend = gpu_regs[VBE] & 0x7ff;
713	691	int vbstart = gpu_regs[VBB] & 0x7ff;
714	692
715	693	/* adjust for the half-lines */
r5534	r5535
796	774	/* only run if video is enabled and we are past the "display begin" */
797	775	if ((gpu_regs[VMODE] & 1) && vc >= (gpu_regs[VDB] & 0x7ff))
798	776	{
799		UINT32 *dest = BITMAP_ADDR32(screen_bitmap, vc >> 1, 0);
	777	UINT32 *dest = BITMAP_ADDR32(screen_bitmap, vc / 2, 0);
800	778	int maxx = visarea->max_x;
801		int hde = effective_hvalue(gpu_regs[HDE]) >> 1;
	779	int hde = effective_hvalue(gpu_regs[HDE]) / 2;
802	780	UINT16 x,scanline[760];
803	781	UINT8 y,pixel_width = ((gpu_regs[VMODE]>>10)&3)+1;
804	782
r5534	r5535
814	792	process_object_list(machine, vc, scanline);
815	793
816	794	/* copy the data to the target, clipping */
817		if ((gpu_regs[VMODE] & 0x106) == 0x002) /* RGB24 */
818		{
819		for (x = 0; x < 760 && hdb <= maxx && hdb < hde; x+=2)
820		for (y = 0; y < pixel_width; y++)
821		{
822		UINT8 r = pen_table[(scanline[x]&0xff)\|256];
823		UINT8 g = pen_table[(scanline[x]>>8)\|512];
824		UINT8 b = pen_table[scanline[x+1]&0xff];
825		dest[hdb++] = MAKE_RGB(r, g, b);
826		}
827		}
828		else
829		{
830		for (x = 0; x < 760 && hdb <= maxx && hdb < hde; x++)
831		for (y = 0; y < pixel_width; y++)
832		dest[hdb++] = pen_table[scanline[x]];
833		}
	795	for (x = 0; x < 760 && hdb <= maxx && hdb < hde; x++)
	796	for (y = 0; y < pixel_width; y++)
	797	dest[hdb++] = pen_table[scanline[x]];
834	798	}
835	799
836	800	/* adjust the timer in a loop, to handle missed cases */

src/mame/video/phoenix.c
r5534	r5535
435	435	return survival_protection_value;
436	436	}
437	437
438		~~int~~ survival_sid_callback~~( const device_config *device~~ )
	438	READ_LINE_DEVICE_HANDLER( survival_sid_callback )
439	439	{
440	440	return survival_sid_value;
441	441	}

src/mame/video/taito_f2.c
r5534	r5535
73	73	static UINT8 f2_spritepri[6]; // todo - move into taitoic.c
74	74	static UINT8 f2_spriteblendmode; // todo - move into taitoic.c
75	75
	76	static UINT16 *paletteram_buffer;
	77
76	78	enum
77	79	{
78	80	FOOTCHMP = 1
r5534	r5535
295	297	f2_pivot_xdisp = -16;
296	298	f2_pivot_ydisp = 16;
297	299	taitof2_core_vh_start(machine, 0,3,3,0,0,0,0,0,0);
	300
	301	paletteram_buffer = auto_alloc_array(machine, UINT16, 4096);
	302	memset(paletteram_buffer, 0, 4096*sizeof(UINT16));
	303	state_save_register_global_pointer(machine, paletteram_buffer, 4096);
298	304	}
299	305
	306	WRITE16_HANDLER( taitof2_palette_w )
	307	{
	308	COMBINE_DATA(&paletteram_buffer[offset]);
	309	}
300	310
	311
301	312	/********************************************************
302	313	SPRITE READ AND WRITE HANDLERS
303	314
r5534	r5535
964	975	}
965	976	}
966	977
	978
967	979	VIDEO_EOF( taitof2_no_buffer )
968	980	{
969	981	taitof2_update_sprites_active_area();
r5534	r5535
1039	1051
1040	1052
1041	1053	/* SSI */
1042		VIDEO_UPDATE( ssi )
	1054	VIDEO_UPDATE( taitof2_ssi )
1043	1055	{
1044	1056	taitof2_handle_sprite_buffering();
1045	1057
r5534	r5535
1052	1064	}
1053	1065
1054	1066
1055		VIDEO_UPDATE( yesnoj )
	1067	VIDEO_UPDATE( taitof2_yesnoj )
1056	1068	{
1057	1069	taitof2_handle_sprite_buffering();
1058	1070
r5534	r5535
1193	1205	return 0;
1194	1206	}
1195	1207
	1208	VIDEO_UPDATE( taitof2_driftout )
	1209	{
	1210	UINT16 pen;
1196	1211
	1212	/* send palette, workaround for bug http://www.mametesters.org/view.php?id=3356 (just for this game)
	1213	driftout writes twice per frame to the palette, this causes glitches on some setups due to
	1214	VIDEO_UPDATE not being synced to renderer update when multithreading is on. */
	1215	for (pen=0;pen<4096;pen++)
	1216	palette_set_color_rgb(screen->machine, pen, pal5bit(paletteram_buffer[pen] >> 10), pal5bit(paletteram_buffer[pen] >> 5), pal5bit(paletteram_buffer[pen] >> 0));
1197	1217
	1218	return VIDEO_UPDATE_CALL( taitof2_pri_roz );
	1219	}
	1220
	1221
	1222
1198	1223	/* Thunderfox */
1199		VIDEO_UPDATE( thundfox )
	1224	VIDEO_UPDATE( taitof2_thundfox )
1200	1225	{
1201	1226	int tilepri[2][3];
1202	1227	int spritepri[4];
r5534	r5535
1326	1351
1327	1352	********************************************************************/
1328	1353
1329		VIDEO_UPDATE( metalb )
	1354	VIDEO_UPDATE( taitof2_metalb )
1330	1355	{
1331	1356	UINT8 layer[5], invlayer[4];
1332	1357	UINT16 priority;
r5534	r5535
1376	1401
1377	1402
1378	1403	/* Deadconx, Footchmp */
1379		VIDEO_UPDATE( deadconx )
	1404	VIDEO_UPDATE( taitof2_deadconx )
1380	1405	{
1381	1406	UINT8 layer[5];
1382	1407	UINT8 tilepri[5];

src/mame/video/thepit.c
r5534	r5535
99	99
100	100	for (i = 0; i < 32; i++)
101	101	{
102		UINT8 r = ((color_prom[i + 0x20] >> 6) \| (color_prom[i + 0x00] << 2)) & 0x1f;
103		UINT8 g = BITSWAP8(color_prom[i + 0x20], 7, 6, 0, 1, 2, 3, 4, 5) & 0x1f;
104		UINT8 b = BITSWAP8(color_prom[i + 0x00], 0, 1, 2, 3, 4, 5, 6, 7) & 0x1f;
	102	UINT8 b = BITSWAP8(color_prom[i + 0x00], 0, 1, 2, 3, 4, 5, 6, 7);
	103	UINT8 g = BITSWAP8(color_prom[i + 0x20], 0, 1, 2, 3, 4, 5, 6, 7);
	104	UINT8 r = (b>>5&7)<<2 \| (g>>6&3);
105	105
106		palette_set_color_rgb(machine, i, pal5bit(r), pal5bit(g), pal5bit(b));
	106	palette_set_color_rgb(machine, i, pal5bit(r), pal5bit(g), pal4bit(b));
107	107	}
108	108
109	109	/* allocate primary colors for the background and foreground

src/mame/layout/noraut11.lay
r0	r5535
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3	<element name="L0" defstate="1">
	4	<rect state="1">
	5	<color red="1.0" green="0.5" blue="0.0" />
	6	</rect>
	7	<rect state="0">
	8	<color red="0.35" green="0.2" blue="0.0" />
	9	</rect>
	10	<text string="CHANGE">
	11	<color red="0.0" green="0.0" blue="0.0" />
	12	<bounds x="0" y="0.1" width="1" height="0.4" />
	13	</text>
	14	<text string="CARD">
	15	<color red="0.0" green="0.0" blue="0.0" />
	16	<bounds x="0" y="0.5" width="1" height="0.4" />
	17	</text>
	18	</element>
	19
	20	<element name="L1" defstate="1">
	21	<rect state="1">
	22	<color red="1.0" green="0.5" blue="0.0" />
	23	</rect>
	24	<rect state="0">
	25	<color red="0.35" green="0.2" blue="0.0" />
	26	</rect>
	27	<text string="HALF">
	28	<color red="0.0" green="0.0" blue="0.0" />
	29	<bounds x="0" y="0.1" width="1" height="0.4" />
	30	</text>
	31	<text string="GAMBLE">
	32	<color red="0.0" green="0.0" blue="0.0" />
	33	<bounds x="0" y="0.5" width="1" height="0.4" />
	34	</text>
	35	</element>
	36
	37	<element name="L2" defstate="1">
	38	<rect state="1">
	39	<color red="1.0" green="0.0" blue="0.0" />
	40	</rect>
	41	<rect state="0">
	42	<color red="0.4" green="0.0" blue="0.0" />
	43	</rect>
	44	<text string="HOLD 1">
	45	<color red="0.0" green="0.0" blue="0.0" />
	46	<bounds x="0" y="0.3" width="1" height="0.2" />
	47	</text>
	48	<text string="CANCEL">
	49	<color red="0.0" green="0.0" blue="0.0" />
	50	<bounds x="0" y="0.5" width="1" height="0.2" />
	51	</text>
	52	</element>
	53
	54	<element name="L3" defstate="1">
	55	<rect state="1">
	56	<color red="1.0" green="0.0" blue="0.0" />
	57	</rect>
	58	<rect state="0">
	59	<color red="0.4" green="0.0" blue="0.0" />
	60	</rect>
	61	<text string="HOLD 2">
	62	<color red="0.0" green="0.0" blue="0.0" />
	63	<bounds x="0" y="0.3" width="1" height="0.2" />
	64	</text>
	65	<text string="CANCEL">
	66	<color red="0.0" green="0.0" blue="0.0" />
	67	<bounds x="0" y="0.5" width="1" height="0.2" />
	68	</text>
	69	</element>
	70
	71	<element name="L4" defstate="1">
	72	<rect state="1">
	73	<color red="1.0" green="0.0" blue="0.0" />
	74	</rect>
	75	<rect state="0">
	76	<color red="0.4" green="0.0" blue="0.0" />
	77	</rect>
	78	<text string="HOLD 3">
	79	<color red="0.0" green="0.0" blue="0.0" />
	80	<bounds x="0" y="0.3" width="1" height="0.2" />
	81	</text>
	82	<text string="CANCEL">
	83	<color red="0.0" green="0.0" blue="0.0" />
	84	<bounds x="0" y="0.5" width="1" height="0.2" />
	85	</text>
	86	</element>
	87
	88	<element name="L5" defstate="1">
	89	<rect state="1">
	90	<color red="1.0" green="0.0" blue="0.0" />
	91	</rect>
	92	<rect state="0">
	93	<color red="0.4" green="0.0" blue="0.0" />
	94	</rect>
	95	<text string="HOLD 4">
	96	<color red="0.0" green="0.0" blue="0.0" />
	97	<bounds x="0" y="0.3" width="1" height="0.2" />
	98	</text>
	99	<text string="CANCEL">
	100	<color red="0.0" green="0.0" blue="0.0" />
	101	<bounds x="0" y="0.5" width="1" height="0.2" />
	102	</text>
	103	</element>
	104
	105	<element name="L6" defstate="1">
	106	<rect state="1">
	107	<color red="1.0" green="0.0" blue="0.0" />
	108	</rect>
	109	<rect state="0">
	110	<color red="0.4" green="0.0" blue="0.0" />
	111	</rect>
	112	<text string="HOLD 5">
	113	<color red="0.0" green="0.0" blue="0.0" />
	114	<bounds x="0" y="0.3" width="1" height="0.2" />
	115	</text>
	116	<text string="CANCEL">
	117	<color red="0.0" green="0.0" blue="0.0" />
	118	<bounds x="0" y="0.5" width="1" height="0.2" />
	119	</text>
	120	</element>
	121
	122
	123	<element name="L8" defstate="1">
	124	<rect state="1">
	125	<color red="1.0" green="1.0" blue="0.0" />
	126	</rect>
	127	<rect state="0">
	128	<color red="0.3" green="0.3" blue="0.0" />
	129	</rect>
	130	<text string="DEAL">
	131	<color red="0.0" green="0.0" blue="0.0" />
	132	<bounds x="0" y="0.1" width="1" height="0.4" />
	133	</text>
	134	<text string="DRAW">
	135	<color red="0.0" green="0.0" blue="0.0" />
	136	<bounds x="0" y="0.5" width="1" height="0.4" />
	137	</text>
	138	</element>
	139
	140	<element name="L9" defstate="1">
	141	<rect state="1">
	142	<color red="1.0" green="1.0" blue="0.0" />
	143	</rect>
	144	<rect state="0">
	145	<color red="0.3" green="0.3" blue="0.0" />
	146	</rect>
	147	<text string="BET">
	148	<color red="0.0" green="0.0" blue="0.0" />
	149	<bounds x="0" y="0.1" width="1" height="0.4" />
	150	</text>
	151	<text string="COLLECT">
	152	<color red="0.0" green="0.0" blue="0.0" />
	153	<bounds x="0" y="0.5" width="1" height="0.4" />
	154	</text>
	155	</element>
	156
	157	<element name="L10" defstate="1">
	158	<rect state="1">
	159	<color red="1.0" green="1.0" blue="0.0" />
	160	</rect>
	161	<rect state="0">
	162	<color red="0.3" green="0.3" blue="0.0" />
	163	</rect>
	164	<text string="HI">
	165	<color red="0.0" green="0.0" blue="0.0" />
	166	<bounds x="0" y="0.25" width="1" height="0.5" />
	167	</text>
	168	</element>
	169
	170	<element name="L11" defstate="1">
	171	<rect state="1">
	172	<color red="1.0" green="1.0" blue="0.0" />
	173	</rect>
	174	<rect state="0">
	175	<color red="0.3" green="0.3" blue="0.0" />
	176	</rect>
	177	<text string="LO">
	178	<color red="0.0" green="0.0" blue="0.0" />
	179	<bounds x="0" y="0.25" width="1" height="0.5" />
	180	</text>
	181	</element>
	182
	183
	184
	185	<view name="Button Lamps">
	186	<screen index="0">
	187	<bounds left="0" top="0" right="4" bottom="3" />
	188	</screen>
	189
	190	<bezel name="lamp0" element="L0">
	191	<bounds x="3.05" y="3.28" width="0.40" height="0.20" />
	192	</bezel>
	193	<bezel name="lamp1" element="L1">
	194	<bounds x="3.05" y="3.03" width="0.40" height="0.20" />
	195	</bezel>
	196
	197	<bezel name="lamp2" element="L2">
	198	<bounds x="0.05" y="3.05" width="0.40" height="0.40" />
	199	</bezel>
	200	<bezel name="lamp3" element="L3">
	201	<bounds x="0.55" y="3.05" width="0.40" height="0.40" />
	202	</bezel>
	203	<bezel name="lamp4" element="L4">
	204	<bounds x="1.05" y="3.05" width="0.40" height="0.40" />
	205	</bezel>
	206	<bezel name="lamp5" element="L5">
	207	<bounds x="1.55" y="3.05" width="0.40" height="0.40" />
	208	</bezel>
	209	<bezel name="lamp6" element="L6">
	210	<bounds x="2.05" y="3.05" width="0.40" height="0.40" />
	211	</bezel>
	212
	213
	214	<bezel name="lamp8" element="L8">
	215	<bounds x="2.55" y="3.28" width="0.40" height="0.20" />
	216	</bezel>
	217	<bezel name="lamp9" element="L9">
	218	<bounds x="2.55" y="3.03" width="0.40" height="0.20" />
	219	</bezel>
	220
	221	<bezel name="lamp10" element="L10">
	222	<bounds x="3.55" y="3.03" width="0.40" height="0.20" />
	223	</bezel>
	224	<bezel name="lamp11" element="L11">
	225	<bounds x="3.55" y="3.28" width="0.40" height="0.20" />
	226	</bezel>
	227
	228	</view>
	229	</mamelayout>

src/mame/layout/noraut12.lay
r0	r5535
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3	<element name="L0" defstate="1">
	4	<disk state="1">
	5	<color red="1.0" green="0.5" blue="0.0" />
	6	</disk>
	7	<disk state="0">
	8	<color red="0.35" green="0.2" blue="0.0" />
	9	</disk>
	10	<text string="STAND">
	11	<color red="0.0" green="0.0" blue="0.0" />
	12	<bounds x="0" y="0.3" width="1" height="0.4" />
	13	</text>
	14	</element>
	15
	16	<element name="L1" defstate="1">
	17	<disk state="1">
	18	<color red="0.0" green="1.0" blue="0.5" />
	19	</disk>
	20	<disk state="0">
	21	<color red="0.0" green="0.3" blue="0.15" />
	22	</disk>
	23	<text string="SAVE">
	24	<color red="0.0" green="0.0" blue="0.0" />
	25	<bounds x="0" y="0.3" width="1" height="0.4" />
	26	</text>
	27	</element>
	28
	29	<element name="L2" defstate="1">
	30	<disk state = "1">
	31	<color red="1.0" green="1.0" blue="0.0" />
	32	</disk>
	33	<disk state="0">
	34	<color red="0.3" green="0.3" blue="0.0" />
	35	</disk>
	36	<text string="HOLD1">
	37	<color red="0.0" green="0.0" blue="0.0" />
	38	<bounds x="0" y="0.3" width="1" height="0.4" />
	39	</text>
	40	</element>
	41
	42	<element name="L3" defstate="1">
	43	<disk state = "1">
	44	<color red="1.0" green="1.0" blue="0.0" />
	45	</disk>
	46	<disk state="0">
	47	<color red="0.3" green="0.3" blue="0.0" />
	48	</disk>
	49	<text string="HOLD2">
	50	<color red="0.0" green="0.0" blue="0.0" />
	51	<bounds x="0" y="0.3" width="1" height="0.4" />
	52	</text>
	53	</element>
	54
	55	<element name="L4" defstate="1">
	56	<disk state = "1">
	57	<color red="1.0" green="1.0" blue="0.0" />
	58	</disk>
	59	<disk state="0">
	60	<color red="0.3" green="0.3" blue="0.0" />
	61	</disk>
	62	<text string="HOLD3">
	63	<color red="0.0" green="0.0" blue="0.0" />
	64	<bounds x="0" y="0.3" width="1" height="0.4" />
	65	</text>
	66	</element>
	67
	68	<element name="L5" defstate="1">
	69	<disk state = "1">
	70	<color red="1.0" green="1.0" blue="0.0" />
	71	</disk>
	72	<disk state="0">
	73	<color red="0.3" green="0.3" blue="0.0" />
	74	</disk>
	75	<text string="HOLD4">
	76	<color red="0.0" green="0.0" blue="0.0" />
	77	<bounds x="0" y="0.3" width="1" height="0.4" />
	78	</text>
	79	</element>
	80
	81	<element name="L6" defstate="1">
	82	<disk state = "1">
	83	<color red="1.0" green="1.0" blue="0.0" />
	84	</disk>
	85	<disk state="0">
	86	<color red="0.3" green="0.3" blue="0.0" />
	87	</disk>
	88	<text string="HOLD5">
	89	<color red="0.0" green="0.0" blue="0.0" />
	90	<bounds x="0" y="0.3" width="1" height="0.4" />
	91	</text>
	92	</element>
	93
	94	<element name="L7" defstate="1">
	95	<disk state="1">
	96	<color red="1.0" green="1.0" blue="0.0" />
	97	</disk>
	98	<disk state="0">
	99	<color red="0.3" green="0.3" blue="0.0" />
	100	</disk>
	101	<text string="CANCEL">
	102	<color red="0.0" green="0.0" blue="0.0" />
	103	<bounds x="0" y="0.3" width="1" height="0.4" />
	104	</text>
	105	</element>
	106
	107
	108	<element name="L8" defstate="1">
	109	<disk state="1">
	110	<color red="1.0" green="0.5" blue="0.0" />
	111	</disk>
	112	<disk state="0">
	113	<color red="0.35" green="0.2" blue="0.0" />
	114	</disk>
	115	<text string="DEAL">
	116	<color red="0.0" green="0.0" blue="0.0" />
	117	<bounds x="0" y="0.3" width="1" height="0.4" />
	118	</text>
	119	</element>
	120
	121	<element name="L9" defstate="1">
	122	<disk state="1">
	123	<color red="1.0" green="0.0" blue="0.0" />
	124	</disk>
	125	<disk state="0">
	126	<color red="0.4" green="0.0" blue="0.0" />
	127	</disk>
	128	<text string="BET">
	129	<color red="0.0" green="0.0" blue="0.0" />
	130	<bounds x="0" y="0.3" width="1" height="0.4" />
	131	</text>
	132	</element>
	133
	134	<element name="L10" defstate="1">
	135	<rect state="1">
	136	<color red="1.0" green="1.0" blue="0.0" />
	137	</rect>
	138	<rect state="0">
	139	<color red="0.3" green="0.3" blue="0.0" />
	140	</rect>
	141	<text string="HIGH">
	142	<color red="0.0" green="0.0" blue="0.0" />
	143	<bounds x="0" y="0.25" width="1" height="0.5" />
	144	</text>
	145	</element>
	146
	147	<element name="L11" defstate="1">
	148	<rect state="1">
	149	<color red="1.0" green="1.0" blue="0.0" />
	150	</rect>
	151	<rect state="0">
	152	<color red="0.3" green="0.3" blue="0.0" />
	153	</rect>
	154	<text string="LOW">
	155	<color red="0.0" green="0.0" blue="0.0" />
	156	<bounds x="0" y="0.25" width="1" height="0.5" />
	157	</text>
	158	</element>
	159
	160
	161
	162	<view name="Button Lamps">
	163	<screen index="0">
	164	<bounds left="0" top="0" right="4" bottom="3" />
	165	</screen>
	166
	167	<bezel name="lamp2" element="L2">
	168	<bounds x="0.55" y="3.03" width="0.20" height="0.20" />
	169	</bezel>
	170	<bezel name="lamp3" element="L3">
	171	<bounds x="1.05" y="3.03" width="0.20" height="0.20" />
	172	</bezel>
	173	<bezel name="lamp4" element="L4">
	174	<bounds x="1.55" y="3.03" width="0.20" height="0.20" />
	175	</bezel>
	176	<bezel name="lamp5" element="L5">
	177	<bounds x="2.05" y="3.03" width="0.20" height="0.20" />
	178	</bezel>
	179	<bezel name="lamp6" element="L6">
	180	<bounds x="2.55" y="3.03" width="0.20" height="0.20" />
	181	</bezel>
	182
	183	<bezel name="lamp7" element="L7">
	184	<bounds x="0.55" y="3.28" width="0.20" height="0.20" />
	185	</bezel>
	186	<bezel name="lamp0" element="L0">
	187	<bounds x="1.05" y="3.28" width="0.20" height="0.20" />
	188	</bezel>
	189	<bezel name="lamp1" element="L1">
	190	<bounds x="1.55" y="3.28" width="0.20" height="0.20" />
	191	</bezel>
	192	<bezel name="lamp8" element="L8">
	193	<bounds x="2.05" y="3.28" width="0.20" height="0.20" />
	194	</bezel>
	195	<bezel name="lamp9" element="L9">
	196	<bounds x="2.55" y="3.28" width="0.20" height="0.20" />
	197	</bezel>
	198
	199	<bezel name="lamp10" element="L10">
	200	<bounds x="3.05" y="3.03" width="0.40" height="0.20" />
	201	</bezel>
	202	<bezel name="lamp11" element="L11">
	203	<bounds x="3.05" y="3.28" width="0.40" height="0.20" />
	204	</bezel>
	205
	206	</view>
	207	</mamelayout>

src/mame/drivers/nbmj9195.c
r5534	r5535
2931	2931	MDRV_CPU_IO_MAP(sailorws_io_map)
2932	2932	MDRV_CPU_VBLANK_INT("screen", ctc0_trg1) /* vblank is connect to ctc triggfer */
2933	2933
2934		MDRV_CPU_ADD("audiocpu", Z80, 8000000/1) /* TMPZ84C011, 8.00 MHz */
	2934	MDRV_CPU_ADD("audiocpu", Z80, 8000000) /* TMPZ84C011, 8.00 MHz */
2935	2935	MDRV_CPU_CONFIG(daisy_chain_sound)
2936	2936	MDRV_CPU_PROGRAM_MAP(sailorws_sound_map)
2937	2937	MDRV_CPU_IO_MAP(sailorws_sound_io_map)
2938	2938
2939	2939	MDRV_Z80CTC_ADD("main_ctc", 12000000/2 /* same as "maincpu" */, ctc_intf_main)
2940		MDRV_Z80CTC_ADD("audio_ctc", 8000000/1 /* same as "audiocpu" */, ctc_intf_audio)
	2940	MDRV_Z80CTC_ADD("audio_ctc", 8000000 /* same as "audiocpu" */, ctc_intf_audio)
2941	2941
2942	2942	MDRV_MACHINE_RESET(sailorws)
2943	2943

src/mame/drivers/norautp.c
r5534	r5535
1	1	/******************************************************************************
2	2
3		- NORAUT POKER -
4		------------------
	3	- NORAUT POKER -
	4	------------------
5	5
6		Driver by Roberto Fresca & Angelo Salese.
	6	Driver by Roberto Fresca & Angelo Salese.
7	7
8	8
9		Games running on this hardware:
	9	Games running on this hardware:
10	10
11		* Noraut Poker, 1988, Noraut Ltd.
12		* Noraut Joker Poker 1988, Noraut Ltd.
13		* GTI Poker 1983, GTI Inc.
14		* Poker, 198?, Unknown.
	11	* Noraut Poker, 1988, Noraut Ltd.
	12	* Noraut Joker Poker, 1988, Noraut Ltd.
	13	* Noraut Red Hot Joker Poker, 1988, Noraut Ltd.
	14	* Noraut Poker (NTX10A), 1988, Noraut Ltd.
	15	* Noraut Joker Poker (V3.010a), 1988, Noraut Ltd.
	16	* GTI Poker, 1983, GTI Inc.
	17	* Noraut Poker (bootleg), 198?, Unknown.
15	18
16	19
17	20	*******************************************************************************
18	21
19	22
20		Hardware Notes:
21		---------------
	23	HARDWARE NOTES:
	24	---------------
22	25
23		1x Z80
24		3x PPI 8255
25		2x 6116 SRAM
26		1x 3.6 Vcc Battery.
27		1x 18.432 MHz. Xtal.
	26	Hardware Layout (norautp):
28	27
29		1x 555 + unknown yellow resonator, near the edge connector.
30		1x 555 + resnet, near the battery.
	28	1x Z80
	29	3x PPI 8255
	30	2x 6116 SRAM
	31	1x 3.6 Vcc Battery.
	32	1x 18.432 MHz. Xtal.
31	33
32		2x 3pins jumpers (between the Z80 and ROM)
	34	1x 555 + unknown yellow resonator, near the edge connector.
	35	1x 555 + resnet, near the battery.
33	36
34		JP1 (ABC); JP2 (DEF)
	37	1x 10 DIP switches bank.
	38	2x 3pins jumpers (between the Z80 and ROM)
35	39
36		PCB silksceened: AB+DE=512 BC+DE=256
37		(CUT BC) EF=64/128
	40	JP1 (ABC); JP2 (DEF)
38	41
	42	PCB silksceened: AB+DE=512 BC+DE=256
	43	(CUT BC) EF=64/128
39	44
40		1x 10 DIP ~~switch~~es bank.
	45	PCB silksceened: SMART-BOARD 131191 ISS.E (Made in USA)
41	46
	47	-------------------------------------------------------------
42	48
43		PCB silksceened: SMART-BOARD 131191 ISS.E (Made in USA)
44	49
	50	Hardware Layout (norautjp):
45	51
	52	- CPU: 1x TMPZ84C00AP-8
	53	- RAM: 2x HM6116LP-4 CMOS Static Ram
	54	- I/O: 3x D8255AC-2 Peripeheral Interface Adapter
	55	- Prg ROMs: 1x 2764 Eprom
	56	- Gfx ROMs: 1x 2732 Eprom
	57	- Sound: Discrete
	58	- Battery: 1x 3.6v Ni-cd 65Mah
	59	- Crystal: 1x 18.432Mhz
	60	- Resistor Array: 4x 9 Pin SIP 472G
	61
	62
	63	PCB Layout (norautjp): Edge Connector 36x2
	64	______________________________________________________________________________________________
	65	\| _____ _________ _________ _____ ......... _________ \|
	66	\| \|D5555\| \|74LS174N \| \|74LS153N \| \|D5555\| ......... \|ULN2003A \| \|
	67	\| \|_____\| \|_________\| \|_________\| \|_____\| Resistor Array \|_________\| \|
	68	\| ___ \|
	69	\| \|VR1\| \|
	70	\| DIP SW x4 \|___\| \|
	71	\| ________ _______ \|
	72	\| \|Battery \| \|1\|2\|3\|4\| _________ _________ _________ _________ _________ \|
	73	\| \| 3.6v \| \|_\|_\|_\|_\| \|74LS157N \| \|74LS153N \| \|74LS161AP\| \|74LS86AN \| \|ULN2003A \| \|
	74	\| \|________\| \|_________\| \|_________\| \|_________\| \|_________\| \|_________\| \|
	75	\| \|
	76	\| \|
	77	\| \| 36
	78	\| _________ _________ _________ _________ _________ \|___
	79	\| \|HD74LS04P\| \|74LS166AP\| \|74LS161AN\| \|74LS153N \| \|ULN2003A \| ___\|
	80	\| \|_________\| \|_________\| \|_________\| \|_________\| \|_________\| ___\|
	81	\| ___\|
	82	\| DIP SW x 8 ________________ ___\|
	83	\| _____________ _______________ _________ _________ \| \| ___\|
	84	\| \| \| \|1\|2\|3\|4\|5\|6\|7\|8\| \|74LS161AN\| \|74LS157N \| \| D8255AC-2 \| ___\|
	85	\| \| 2732 \| \|_\|_\|_\|_\|_\|_\|_\|_\| \|_________\| \|_________\| \|________________\| ___\|
	86	\| \|_____________\| ___\|
	87	\| ___\|
	88	\| ________________ ___\|
	89	\| \| \| ___\|
	90	\| _____________ _____________ \| D8255AC-2 \| ___\|
	91	\| \| \| \| \| \|________________\| ___\|
	92	\| \| 6116 \| \| 6116 \| ___\|
	93	\| \|_____________\| \|_____________\| _________ _________ ___\|
	94	\| \|74LS161AN\| \|74LS157N \| ___\|
	95	\| \|_________\| \|_________\| ___\|
	96	\| ___\|
	97	\| ______________ ________________ ___\|
	98	\| \| \| \| \| _________ _________ ___\|
	99	\| \| 2764 \| \| D8255AC-2 \| \|74LS161AN\| \|74LS157N \| ......... ___\|
	100	\| \|______________\| \|________________\| \|_________\| \|_________\| ......... ___\|
	101	\| Resistor Array ___\|
	102	\| \|
	103	\| \| 1
	104	\| _________ _________ _________ _________ \|
	105	\| \| 74LS32N \| \|74LS161AN\| \| 74LS86P \| \| 74LS04N \| \|
	106	\| \|_________\| \|_________\| \|_________\| \|_________\| \|
	107	\| \|
	108	\| XTAL \|
	109	\| .----. \|
	110	\| ____________________ __________ _________ _________ _________ _________ \|
	111	\| \| \| \|PALce16v8H\| \| 74LS04N \| \|74LS157N \| \| 74LS11N \| \|74LS74AN \| \|
	112	\| \| TMPZ84C00AP-8 \| \|__________\| \|_________\| \|_________\| \|_________\| \|_________\| \|
	113	\| \|____________________\| \|
	114	\| \|
	115	\|_______________________________________________________________________________________________\|
	116
	117
	118
46	119	*******************************************************************************
47	120
48	121
49		Noraut Edge Connector (pinouts)
50		--------------------------------
51		Component PN Solder Side
52		--------------------------------
53		GND 01 GND
54		5v DC 02 5v DC
55		03
56		12v DC 04 12v DC
57		05
58		06
59		07
60		0v 08 Readout Switch
61		0v 09 Low level hopper
62		0v 10 50p in
63		0v 11 pound in
64		0v 12 Bet switch
65		0v 13 Deal switch
66		0v 14 Hold 1 switch
67		0v 15 Half Gamble switch
68		0v 16 Change Card switch
69		Refil 17 Coin count/sense from hopper
70		Low Switch 18 High swicth
71		Hold 3 Switch 19 Hold 2 switch
72		Hold 5 Switch 20 Hold 4 switch
73		10p coin 21 Deflect
74		22 50p in meter
75		23 Hopper Motor Drive (low volt switch line NOT 24v)
76		24
77		25 spk+
78		26 Panel lamps clock
79		Monitor sync 27 Hold 1 lamp
80		Bet lamp 28 Deal lamp
81		Change lamp 29 Hold 4 lamp
82		Hold 5 lamp 30 Panel lights reset
83		High lamp 31 Half Gamble lamp
84		Hold 2 lamp 32 Low lamp
85		10p Meter out 33 Meter refil
86		Video Green 34 Hold 3 lamp
87		Video Blue 35 10p in Meter
88		Video Red 36 Spark Detect (Not on all boards)
	122	Noraut Edge Connector (pinouts)
	123	--------------------------------
	124	Component PN Solder Side
	125	--------------------------------
	126	GND 01 GND
	127	5v DC 02 5v DC
	128	03
	129	12v DC 04 12v DC
	130	05
	131	06
	132	07
	133	0v 08 Readout Switch
	134	0v 09 Low level hopper
	135	0v 10 50p in
	136	0v 11 pound in
	137	0v 12 Bet switch
	138	0v 13 Deal switch
	139	0v 14 Hold 1 switch
	140	0v 15 Half Gamble switch
	141	0v 16 Change Card switch
	142	Refil 17 Coin count/sense from hopper
	143	Low Switch 18 High swicth
	144	Hold 3 Switch 19 Hold 2 switch
	145	Hold 5 Switch 20 Hold 4 switch
	146	10p coin 21 Deflect
	147	22 50p in meter
	148	23 Hopper Motor Drive (low volt switch line NOT 24v)
	149	24
	150	25 spk+
	151	26 Panel lamps clock
	152	Monitor sync 27 Hold 1 lamp
	153	Bet lamp 28 Deal lamp
	154	Change lamp 29 Hold 4 lamp
	155	Hold 5 lamp 30 Panel lights reset
	156	High lamp 31 Half Gamble lamp
	157	Hold 2 lamp 32 Low lamp
	158	10p Meter out 33 Meter refil
	159	Video Green 34 Hold 3 lamp
	160	Video Blue 35 10p in Meter
	161	Video Red 36 Spark Detect (Not on all boards)
89	162
	163	*******************************************************************************
90	164
	165	Control Panel
	166	-------------
	167
	168	There are 2 control panel schemes:
	169
	170	* The default one (11 button-lamps) for systems without CANCEL button.
	171
	172	.--------------------------------------------------------------------------.
	173	\| .-------. .------. .------. \|
	174	\| .------. .------. .------. .------. .------. \| BET \| \| HALF \| \| HI \| \|
	175	\| \| \| \| \| \| \| \| \| \| \| \|COLLECT\| \|GAMBLE\| \| \| \|
	176	\| \| HOLD \| \| HOLD \| \| HOLD \| \| HOLD \| \| HOLD \| '-------' '------' '------' \|
	177	\| \|CANCEL\| \|CANCEL\| \|CANCEL\| \|CANCEL\| \|CANCEL\| .-------. .------. .------. \|
	178	\| \| \| \| \| \| \| \| \| \| \| \| DEAL \| \|CHANGE\| \| LO \| \|
	179	\| '------' '------' '------' '------' '------' \| DRAW \| \| CARD \| \| \| \|
	180	\| '-------' '------' '------' \|
	181	'--------------------------------------------------------------------------'
	182
	183	HOLD buttons = red.
	184	BET, DEAL, HI & LO = yellow.
	185	HALF GAMBLE & CHANGE CARD = orange.
	186
	187
	188	* The alternate one (12 button-lamps) for systems with CANCEL button.
	189
	190	.-------------------------------------------------------------.
	191	\| .------. .------. .------. .------. .------. .----------. \|
	192	\| \| HOLD \| \| HOLD \| \| HOLD \| \| HOLD \| \| HOLD \| \| HIGH \| \|
	193	\| '------' '------' '------' '------' '------' '----------' \|
	194	\| .------. .------. .------. .------. .------. .----------. \|
	195	\| \|CANCEL\| \|STAND \| \| SAVE \| \| DEAL \| \| BET \| \| LOW \| \|
	196	\| '------' '------' '------' '------' '------' '----------' \|
	197	'-------------------------------------------------------------'
	198
	199	HOLD & CANCEL buttons = yellow (1).
	200	STAND & DEAL buttons = orange (1).
	201	SAVE (HALF GAMBLE) button = blued-green (1).
	202	BET button = red (1).
	203	HIGH & LOW buttons = yellow.
	204
	205	(1) Circular-shaped buttons.
	206
	207	Some lamps are wired in different way in this scheme.
	208
	209
91	210	*******************************************************************************
92	211
93	212
94		* Game Notes *
	213	Noraut Poker discrete audio circuitry
	214	-------------------------------------
95	215
96		Nothing, yet...
	216	3x ULN2003A (Darlington transistor array)
	217	1x D5555C (CMOS timer)
	218	1x KN2222A (Epitaxial planar general purpose NPN transistor)
	219	1x VR/POT
97	220
	221	.------. .------------. .-------.
	222	\| \| \| D5555C \| \|KN2222A\|
	223	\| \| 4\| \|3 R3 \| \| -->
	224	\| PC7\|------------------------------\|RST OUT\|-----ZZZZ------\|B E\|>----ZZZZZ-----> Audio Out.
	225	\| PC6\|----------. 6\| \|8 \| C \| VR1
	226	\| PC5\|-----. \|2-in .-----\|THR VCC\|-----------. '---+---' .----> Audio Out.
	227	\| PC4\|--. \| .-+------. \| 5\| \|7 \| \| \|
	228	\| \| \| \| \|ULN2003A\| \| .--\|CVOLT DISC\|--. \| \| \|
	229	\| \| \| \| '-+------' \| \| \| \| \| +-------' --+--
	230	\| \| \| \| \|2-out C1 \| \| \| GND \| \| \| GND
	231	\| 8255 \| \| \| '--------\|\|---+ \| '-----+------' \| \| -
	232	\| AP \| \| '--. \| \| \|1 \| \| '
	233	\| \| \| \|3-in \| \| \| \| \|
	234	'------' \| .--+-----. \| \| C5 \| \| \|
	235	\| \|ULN2003A\| \| '---\|\|---+ \| \| +5V
	236	\| '--+-----' \| \| \| \| -+-
	237	\| \|3-out C2 \| C4 \| \| C6 \| \|
	238	\| '----------\|\|---+------\|\|---+-------. \| .--\|\|--+-----'
	239	\|2-in \| \| \| \| \| \|
	240	.-+------. \| --+-- '-' \|
	241	\|ULN2003A\| \| GND \| \|
	242	'-+------' \| - \| \|
	243	\|2-out C3 \| R1 ' \| R2 \|
	244	'----------------\|\|---+----ZZZZ-------------+--ZZZZ--'
98	245
	246	VR1 = 100 ohms
	247
	248	R1 = 120 K ; Tolerance +/- 5%
	249	R2 = 2.2 K ; Tolerance +/- 5%
	250	R3 = 1 K ; Tolerance +/- 5%
	251
	252	C1 = 223J = 22000 pF = 22 nF = 0.022 uF ; Tolerance +/- 5%
	253	C2 = 103J = 10000 pF = 10 nF = 0.01 uF ; Tolerance +/- 5%
	254	C3 = 473J = 47000 pF = 47 nF = 0.047 uF ; Tolerance +/- 5%
	255	C4 = 103J = 10000 pF = 10 nF = 0.01 uF ; Tolerance +/- 5%
	256
	257	C5 = 103 = 10000 pF = 10 nF = 0.01 uF
	258	C6 = 104 = 100000 pF = 100 nF = 0.1 uF
	259
	260	- C1, C2, C3 & C4 are polyester film / mylar capacitors.
	261	- C5 & C6 are ceramic capacitors.
	262	- All Capacitors are non-polarised.
	263
	264
99	265	*******************************************************************************
100	266
101		--------------------
102		* Memory Map *
103		--------------------
104	267
105		0x0000 - 0x1FFF ; ROM space.
106		0x6000 - 0x63FF ; NVRAM.
	268	Narout System Ports Map
	269	-----------------------
107	270
108		0x60 - 0x63 ; PPI 8255 0 - DIP Switches.
109		0xA0 - 0xA3 ; PPI 8255 1 - Regular Inputs.
110		0xC0 - 0xC3 ; PPI 8255 2 - Video RAM.
	271	(*) Confirmed lines.
111	272
112	273
	274	PPI-0 (60h-63h); PortA IN.
	275	DIP Switches bank:
	276
	277	7654 3210
	278	---- ---x * DIP switch 8
	279	---- --x- * DIP switch 7
	280	---- -x-- * DIP switch 6
	281	---- x--- * DIP switch 5
	282	---x ---- * DIP switch 4
	283	--x- ---- * DIP switch 3
	284	-x-- ---- * DIP switch 2
	285	x--- ---- * DIP switch 1
	286
	287
	288	PPI-0 (60h-63h); PortB OUT.
	289	Lamps:
	290
	291	7654 3210
	292	---- ---x * CHANGE CARD lamp.
	293	---- --x- * SAVE / HALF GAMBLE lamp.
	294	---- -x-- * HOLD 1 lamp.
	295	---- x--- * HOLD 2 lamp.
	296	---x ---- * HOLD 3 lamp.
	297	--x- ---- * HOLD 4 lamp.
	298	-x-- ---- * HOLD 5 lamp.
	299	x--- ---- * CANCEL lamp.
	300
	301
	302	PPI-0 (60h-63h); PortC OUT.
	303	Lamps & Coin Counters:
	304
	305	7654 3210
	306	---- ---x * HI lamp.
	307	---- --x- * LO lamp.
	308	---- -x-- unknown.
	309	---- x--- * Payout pulse.
	310	---x ---- * Coin 2 counter.
	311	--x- ---- * Coin 1 counter.
	312	-x-- ---- unknown.
	313	x--- ---- unknown (always activated).
	314
	315
	316	-----------------------------------------------------------
	317
	318	PPI-1 (a0h-a3h); PortA IN.
	319	Regular Inputs:
	320
	321	7654 3210
	322	---- ---x * DEAL / DRAW button.
	323	---- --x- * BET / CHANGE CARD button.
	324	---- -x-- * COIN 1 mech.
	325	---- x--- * COIN 2 mech.
	326	---x ---- * READOUT button.
	327	--x- ---- * HI button.
	328	-x-- ---- * LO button.
	329	x--- ---- * PAYOUT button.
	330
	331
	332	PPI-1 (a0h-a3h); PortB IN.
	333	Regular Inputs:
	334
	335	7654 3210
	336	---- ---x * STAND / TAKE button.
	337	---- --x- * SAVE / HALF GAMBLE button.
	338	---- -x-- * HOLD 1 button.
	339	---- x--- * HOLD 2 button.
	340	---x ---- * HOLD 3 button.
	341	--x- ---- * HOLD 4 button.
	342	-x-- ---- * HOLD 5 button.
	343	x--- ---- * CANCEL button.
	344
	345
	346	PPI-1 (a0h-a3h); PortC OUT.
	347	Sound & Lamps:
	348
	349	7654 3210
	350	---- ---x * DEAL / DRAW Lamp.
	351	---- --x- * BET / COLLECT Lamp.
	352	---- -x-- unknown (always activated after initalize).
	353	---- x--- unknown.
	354	xxxx ---- * Discrete Sound Lines.
	355
	356
	357	-----------------------------------------------------------
	358
	359	PPI-2 (a0h-a3h); PortA IN/OUT
	360	VRAM Handlers:
	361
	362	7654 3210
	363	xxxx xxxx VRAM DATA.
	364
	365
	366	PPI-2 (a0h-a3h); PortB IN? (should be OUT)
	367	VRAM Handlers:
	368
	369	7654 3210
	370	xxxx xxxx VRAM ADDRESSING.
	371
	372
	373	PPI-2 (a0h-a3h); PortC (PortA handshake lines)
	374	VRAM Handlers:
	375
	376	7654 3210
	377	xxxx xxxx HANDSHAKE LINES.
	378
	379
113	380	*******************************************************************************
114	381
115	382
116		~~DRIVER~~ ~~UPDATES:~~
	383	* Game Notes *
117	384
118	385
119		[2009-01-27]
	386	- norautjp:
	387
	388	At the first start-up, the game will give you a very clever
	389	"FU" screen. Press the following buttons together on different times
	390	to get rid of it (and actually initialize the machine):
120	391
121		- Initial release.
122		- Defined ROM, RAM.
123		- Added 2x PPI 8255 for regular I/O.
124		- Added complete inputs and hooked DIP switches.
125		- Added video RAM support.
126		- Added NVRAM.
127		- Added lamps support.
128		- Added coin counters.
129		- Identified the sound writes.
130		- Added hardware description.
131		- Added pinout scheme.
132		- Added technical notes.
	392	* start + bet buttons (1+2);
	393	* Hold 3 + Hold 2 + Save (Half Gamble) + Change Card (C+X+F+D)
133	394
134		[2009-01-28]
	395	Also notice that you actually need to map the last four buttons on the
	396	same button / on a joypad since MAME's steady key doesn't seem to work on
	397	my end...
135	398
136		- Merged GTI Poker (gtipoker.c) with this driver.
137		- Added new memory map and machine driver for gtipoker.
138		- Hooked 2x PPI 8255 to gtipoker.
139		- Hooked the video RAM access ports to gtipoker.
140		- Changed norautpn description from Noraut Poker (No Payout),
141		to Noraut Poker (bootleg), since the game has payout system.
142		- Some clean-ups.
143	399
144		Notes:
145		- norautjp: at the first start-up, the game will give you a very clever
146		"FU" screen. Press the following buttons together on different times
147		to get rid of it (and actually initialize the machine):
148		* start + bet buttons (1+2);
149		* Hold 3 + Hold 2 + Save (Half Gamble) + Change Card (C+X+F+D)
150		Also notice that you actually need to map the last four buttons on the
151		same button / on a joypad since MAME's steady key doesn't seem to work on
152		my end...
	400	*******************************************************************************
153	401
	402	--------------------
	403	* Memory Map *
	404	--------------------
154	405
155		TODO:
	406	0x0000 - 0x1FFF ; ROM space.
	407	0x6000 - 0x63FF ; NVRAM.
156	408
157		- Analize the extra 8255 at 0xc0-0xc3 (full bidirectional port w/hshk)
158		- Video RAM (through 3rd PPI?).
159		- Find if wide chars are hardcoded or tied to a bit.
160		- Proper colors (missing PROM?)
161		- Lamps layout.
162		- Discrete sound.
	409	0x60 - 0x63 ; PPI 8255 0 - DIP Switches, lamps & counters.
	410	0xA0 - 0xA3 ; PPI 8255 1 - Regular Inputs, sound lines & remaining lamps.
	411	0xC0 - 0xC3 ; PPI 8255 2 - Video RAM access.
163	412
164	413
	414	*******************************************************************************
	415
	416
	417	DRIVER UPDATES:
	418
	419
	420	[2009-01-27]
	421
	422	- Initial release.
	423	- Defined ROM, RAM.
	424	- Added 2x PPI 8255 for regular I/O.
	425	- Added complete inputs and hooked DIP switches.
	426	- Added video RAM support.
	427	- Added NVRAM.
	428	- Added lamps support.
	429	- Added coin counters.
	430	- Identified the sound writes.
	431	- Added hardware description.
	432	- Added pinout scheme.
	433	- Added technical notes.
	434
	435
	436	[2009-01-28]
	437
	438	- Merged GTI Poker (gtipoker.c) with this driver.
	439	- Added new memory map and machine driver for gtipoker.
	440	- Hooked 2x PPI 8255 to gtipoker.
	441	- Hooked the video RAM access ports to gtipoker.
	442	- Changed norautpn description from Noraut Poker (No Payout),
	443	to Noraut Poker (bootleg), since the game has payout system.
	444	- Some clean-ups.
	445
	446
	447	[2009-08-21]
	448
	449	- Switched to pre-defined Xtal clock.
	450	- Changed the way how graphics are banked/accessed.
	451	- Fixed the graphics offset and number of tiles per bank.
	452	- Added new set: Noraut Red Hot Joker Poker.
	453	- Added new set: Noraut Poker (NTX10A).
	454	- Added new set: Noraut Joker Poker (V3.010a).
	455	- Fixed the tile size/decode for the first GFX bank.
	456	- Added proper norautrh inputs, including the readout button.
	457	- Added partial DIP switches to norautrh.
	458	- Added more technical notes.
	459
	460
	461	[2009-08-23/26]
	462
	463	- Added a default NVRAM to Noraut Joker Poker to bypass the 'F U' screen.
	464	This is due to the phisical keyboard limitation when needs to enter
	465	4 simultaneous inputs.
	466	- Executed a trojan on 2 noraut systems to confirm the way 16x32 tiles are decoded.
	467	- Fixed the x-offset for 32x32 tiles lines.
	468	- Fixed the screen aspect and visible area.
	469	- Confirmed correct colors. No bipolar PROM involved.
	470	- Added Noraut Joker Poker hardware and PCB layouts.
	471	- Documented the discrete audio circuitery. Added a full diagram.
	472
	473
	474	[2009-08-29]
	475
	476	- Fixed the coin counters.
	477	- Documented all the output ports.
	478	- Added a scheme with descriptions for every existent port.
	479	- Added full lamps support to naroutp, naroutjp, naroutrh and naroutpn.
	480	- Created lamps layouts for 11 and 12-lamps scheme.
	481	- Rerouted some inputs to mantain the inputs layout.
	482	- Renamed some inputs to match the text with the real cab buttons.
	483	- Removed the imperfect colors flag from the existent sets.
	484	- Added 2 different control panel layouts to the source.
	485	- Updated technical notes.
	486
	487
	488	TODO:
	489
	490	- Analize the third 8255 at 0xc0-0xc3 (full bidirectional port w/hshk lines)
	491	- Video RAM (through 3rd PPI?).
	492	- Find if wide chars are hardcoded or tied to a bit.
	493	- Discrete sound.
	494	- Save support.
	495
	496
165	497	*******************************************************************************/
166	498
167	499
r5534	r5535
172	504	#include "machine/8255ppi.h"
173	505	#include "sound/dac.h"
174	506
	507	#include "noraut11.lh"
	508	#include "noraut12.lh"
	509
175	510	static UINT16 *np_vram;
176	511	static UINT16 np_addr;
177	512
r5534	r5535
196	531
197	532	for(y = 0; y < 8; y++)
198	533	{
199		/Double width/
	534	/* Double width, displaced 8 pixels in X */
200	535	if(y == 2 \|\| (y >= 4 && y < 6))
201	536	{
202	537	for(x = 0; x < 16; x++)
r5534	r5535
204	539	int tile = np_vram[count] & 0x3f;
205	540	int colour = (np_vram[count] & 0xc0) >> 6;
206	541
207		drawgfx_opaque(bitmap,cliprect, screen->machine->gfx[1], tile, colour, 0, 0, x * 32, y * 32);
	542	drawgfx_opaque(bitmap,cliprect, screen->machine->gfx[1], tile, colour, 0, 0, (x * 32) + 8, y * 32);
208	543
209	544	count+=2;
210	545	}
r5534	r5535
245	580	* R/W Handlers *
246	581	*************************/
247	582
248		static WRITE8_DEVICE_HANDLER( lamps_w )
	583	static WRITE8_DEVICE_HANDLER( mainlamps_w )
249	584	{
250		/* LAMPS:
	585	/* PPI-0 (60h-63h); PortB OUT.
	586	Lamps:
251	587
252	588	7654 3210
253		---- ---x Change Card / (Save?)
254		---- --x- Hi/Lo
255		---- -x-- Hold 1
256		---- x--- Hold 2
257		---x ---- Hold 3
258		--x- ---- Hold 4
259		-x-- ---- Hold 5
260		x--- ---- Start (poker)
	589	---- ---x * CHANGE CARD lamp.
	590	---- --x- * SAVE / HALF GAMBLE lamp.
	591	---- -x-- * HOLD 1 lamp.
	592	---- x--- * HOLD 2 lamp.
	593	---x ---- * HOLD 3 lamp.
	594	--x- ---- * HOLD 4 lamp.
	595	-x-- ---- * HOLD 5 lamp.
	596	x--- ---- * CANCEL lamp.
261	597	*/
262
263		output_set_lamp_value(0, (data >> 0) & 1); /* Change */
264		output_set_lamp_value(1, (data >> 1) & 1); /* Hi/Lo */
265		output_set_lamp_value(2, (data >> 2) & 1); /* Hold 1 */
266		output_set_lamp_value(3, (data >> 3) & 1); /* Hold 2 */
267		output_set_lamp_value(4, (data >> 4) & 1); /* Hold 3 */
268		output_set_lamp_value(5, (data >> 5) & 1); /* Hold 4 */
269		output_set_lamp_value(6, (data >> 6) & 1); /* Hold 5 */
270		output_set_lamp_value(7, (data >> 7) & 1); /* Start */
	598	output_set_lamp_value(0, (data >> 0) & 1); /* CHANGE CARD lamp */
	599	output_set_lamp_value(1, (data >> 1) & 1); /* SAVE / HALF GAMBLE lamp */
	600	output_set_lamp_value(2, (data >> 2) & 1); /* HOLD 1 lamp */
	601	output_set_lamp_value(3, (data >> 3) & 1); /* HOLD 2 lamp */
	602	output_set_lamp_value(4, (data >> 4) & 1); /* HOLD 3 lamp */
	603	output_set_lamp_value(5, (data >> 5) & 1); /* HOLD 4 lamp */
	604	output_set_lamp_value(6, (data >> 6) & 1); /* HOLD 5 lamp */
	605	output_set_lamp_value(7, (data >> 7) & 1); /* CANCEL lamp */
271	606	}
272	607
273		static WRITE8_DEVICE_HANDLER( ccoun~~ter~~_w )
	608	static WRITE8_DEVICE_HANDLER( soundlamps_w )
274	609	{
275		coin_counter_w(0, data & 0x20); /* Coin1 */
276		coin_counter_w(1, data & 0x10); /* Coin2 */
277		coin_counter_w(2, data & 0x08); /* Payout */
	610	/* PPI-1 (a0h-a3h); PortC OUT.
	611	Sound & Lamps:
	612
	613	7654 3210
	614	---- ---x * DEAL / DRAW Lamp.
	615	---- --x- * BET / COLLECT Lamp.
	616	---- -x-- unknown (always activated after initalize).
	617	---- x--- unknown.
	618	xxxx ---- * Discrete Sound Lines.
	619	*/
	620	output_set_lamp_value(8, (data >> 0) & 1); /* DEAL / DRAW lamp */
	621	output_set_lamp_value(9, (data >> 1) & 1); /* BET / COLLECT lamp */
	622
	623	/* the 4 MSB are for discrete sound */
	624	dac_data_w(devtag_get_device(device->machine, "dac"), (data & 0xf0)); /* Discrete Sound */
278	625	}
279	626
280		static WRITE8_DEVICE_HANDLER( sndlamp_w )
	627	static WRITE8_DEVICE_HANDLER( counterlamps_w )
281	628	{
282		output_set_lamp_value(8, (data >> 0) & 1); /* Start? */
283		output_set_lamp_value(9, (data >> 1) & 1); /* Bet */
	629	/* PPI-0 (60h-63h); PortC OUT.
	630	Lamps & Coin Counters:
284	631
285		/* the 4 MSB are for discrete (or DAC) sound */
286		dac_data_w(devtag_get_device(device->machine, "dac"), (data & 0xf0)); /* Sound DAC? */
	632	7654 3210
	633	---- ---x * HI lamp.
	634	---- --x- * LO lamp.
	635	---- -x-- unknown.
	636	---- x--- * Payout pulse.
	637	---x ---- * Coin 2 counter.
	638	--x- ---- * Coin 1 counter.
	639	-x-- ---- unknown.
	640	x--- ---- unknown (always activated).
	641	*/
	642	output_set_lamp_value(10, (data >> 0) & 1); /* HI lamp */
	643	output_set_lamp_value(11, (data >> 1) & 1); /* LO lamp */
	644
	645	coin_counter_w(0, data & 0x10); /* Coin1/3 counter */
	646	coin_counter_w(1, data & 0x20); /* Coin2 counter */
	647	coin_counter_w(2, data & 0x08); /* Payout pulse */
287	648	}
288	649
289		/game waits for bit 7 (0x80) to be set./
	650
	651	/* game waits for bit 7 (0x80) to be set.*/
290	652	static READ8_HANDLER( test_r )
291	653	{
292	654	return 0xff;
293	655	}
294	656
	657	/* game waits for bit 4 (0x10) to be reset.*/
	658	static READ8_HANDLER( test2_r )
	659	{
	660	return 0x00;
	661	}
	662
295	663	static WRITE8_HANDLER( vram_data_w )
296	664	{
297	665	np_vram[np_addr] = data & 0xff;
r5534	r5535
330	698	c2 --> R ; status?
331	699	c3 --> W ; alternate 00 & 01 (in case of PPI, setting resetting bit 0 of handshaked port)
332	700
	701	The strange issue is that some sets just configure the PPI to mixed mode2 and mode0 input.
	702	it means that port A should be bidirectional and port B just as input. (port C as hshk regs).
	703	So... it doesn't match the addressing through c1.
333	704	*/
334	705
335	706	static ADDRESS_MAP_START( gtipoker_map, ADDRESS_SPACE_PROGRAM, 8 )
r5534	r5535
345	716	AM_RANGE(0xdd, 0xdd) AM_WRITE(vram_addr_w)
346	717	AM_RANGE(0xde, 0xde) AM_READ(test_r)
347	718	// AM_RANGE(0xdc, 0xdf) AM_DEVREADWRITE("ppi8255_2", ppi8255_r, ppi8255_w)
348		AM_RANGE(0xef, 0xef) AM_READ(test_r)
	719	AM_RANGE(0xef, 0xef) AM_READ(test2_r)
349	720	ADDRESS_MAP_END
350	721
351	722
r5534	r5535
355	726
356	727	static INPUT_PORTS_START( norautp )
357	728	PORT_START("IN0")
358		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_DEAL ) PORT_NAME("Deal / Start")
359		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_BET ) PORT_NAME("Bet / Take")
	729	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_DEAL ) PORT_NAME("Deal / Draw")
	730	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_BET ) PORT_NAME("Bet / Collect")
360	731	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2) /* Coin A */
361	732	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2) /* Coin B */
362		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_~~UNKN~~OWN )
	733	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Readout") PORT_CODE(KEYCODE_9)
363	734	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_HIGH ) PORT_NAME("Hi")
364		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_LOW ) PORT_NAME("Lo")
	735	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_LOW ) PORT_NAME("Lo")
365	736	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT )
366	737
367	738	PORT_START("IN1")
368		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Change Card")
369		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_HALF ) PORT_NAME("Save (Half Gamble)")
	739	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_CODE(KEYCODE_F) PORT_NAME("Change Card")
	740	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_HALF ) PORT_NAME("Half Gamble / Save")
370	741	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_HOLD1 )
371	742	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_POKER_HOLD2 )
372	743	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD3 )
r5534	r5535
401	772	PORT_DIPSETTING( 0x00, "10 Pence" )
402	773	INPUT_PORTS_END
403	774
404		static INPUT_PORTS_START( poker )
	775	static INPUT_PORTS_START( norautrh )
405	776	PORT_START("IN0")
	777	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_DEAL ) PORT_NAME("Deal / Draw")
	778	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_BET ) PORT_NAME("Bet / Change Card")
	779	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2) /* Coin A */
	780	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2) /* Coin B */
	781	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Readout") PORT_CODE(KEYCODE_9)
	782	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_HIGH ) PORT_NAME("Hi")
	783	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_LOW ) PORT_NAME("Lo")
	784	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT )
	785
	786	PORT_START("IN1")
	787	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE ) PORT_NAME("Stand / Take")
	788	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_HALF ) PORT_NAME("Save / Half Gamble")
	789	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_HOLD1 )
	790	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_POKER_HOLD2 )
	791	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD3 )
	792	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_POKER_HOLD4 )
	793	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_POKER_HOLD5 )
	794	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_POKER_CANCEL ) /* Coin C for other games */
	795
	796	PORT_START("DSW1")
	797	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:8")
	798	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	799	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	800	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:7")
	801	PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
	802	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	803	PORT_DIPNAME( 0x04, 0x04, "Bet Max" ) PORT_DIPLOCATION("DSW1:6")
	804	PORT_DIPSETTING( 0x04, "5" )
	805	PORT_DIPSETTING( 0x00, "25" )
	806	PORT_DIPNAME( 0x08, 0x08, "Raise Ante" ) PORT_DIPLOCATION("DSW1:5")
	807	PORT_DIPSETTING( 0x08, "Random" )
	808	PORT_DIPSETTING( 0x00, "Always" )
	809	PORT_DIPNAME( 0x10, 0x10, "Type of Game" ) PORT_DIPLOCATION("DSW1:4")
	810	PORT_DIPSETTING( 0x10, "Jacks Plus" )
	811	PORT_DIPSETTING( 0x00, "Joker Poker" )
	812	PORT_DIPNAME( 0xa0, 0x20, DEF_STR( Coinage ) ) PORT_DIPLOCATION("DSW1:3,1")
	813	PORT_DIPSETTING( 0x00, "A=1; B=5" )
	814	PORT_DIPSETTING( 0xa0, "A=5; B=25" )
	815	PORT_DIPSETTING( 0x20, "A=10; B=5" )
	816	PORT_DIPSETTING( 0x80, "A=50; B=25" )
	817	PORT_DIPNAME( 0x40, 0x00, "Show Bet") PORT_DIPLOCATION("DSW1:2")
	818	PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
	819	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	820	INPUT_PORTS_END
	821
	822	static INPUT_PORTS_START( naroutpn )
	823	PORT_START("IN0")
406	824	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_DEAL ) PORT_NAME("Deal / Start")
407		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_~~GAMBL~~E_BET ) PORT_NAME("Bet / Change Card")
	825	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_BET ) PORT_NAME("Bet / Change Card")
408	826	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2) /* Coin A */
409	827	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2) /* Coin B */
410		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_~~UNKN~~OWN )
	828	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Readout") PORT_CODE(KEYCODE_9)
411	829	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_HIGH ) PORT_NAME("Hi")
412		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_LOW ) PORT_NAME("Lo")
	830	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_LOW ) PORT_NAME("Lo")
413	831	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT )
414	832
415	833	PORT_START("IN1")
416		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE ) PORT_NAME("Stand (Take)")
417		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_HALF ) PORT_NAME("Save (Half Gamble)")
	834	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE ) PORT_NAME("Stand / Take")
	835	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_HALF ) PORT_NAME("Save / Half Gamble")
418	836	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_HOLD1 )
419	837	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_POKER_HOLD2 )
420	838	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD3 )
r5534	r5535
449	867	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
450	868	INPUT_PORTS_END
451	869
	870
452	871	/*************************
453	872	* Graphics Layouts *
454	873	*************************/
455	874
456	875	static const gfx_layout charlayout =
	876	/*
	877	Trojanned 2 Narout Poker PCBs to see how the hardware decodes
	878	the 16x32 tiles. The following GFX layout is 100% accurate.
	879	*/
457	880	{
458		16,32,
459		RGN_FRAC(1,1),
	881	16, 32,
	882	RGN_FRAC(1,2),
460	883	1,
461	884	{ 0 },
462	885	{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
463		{ 016, 016, 116, 116, 216, 216, 316, 316, 416, 416, 516, 516, 616, 616, 716, 716,
464		816, 816, 916, 916, 1016,1016,1116,1116,1216,1216,1316,1316,1416,1416,1516,1516 },
	886	{ 016, 016, 016, 016, 016, 016, 016, 016, 016, 116, 216, 316, 416, 516, 616, 716,
	887	816, 916, 1016, 1116, 1216, 1316, 1416, 1516, 016, 016, 016, 016, 016, 016, 016, 016, },
465	888	16*16
466	889	};
467	890
468	891	static const gfx_layout charlayout32x32 =
469	892	{
470	893	32,32,
471		RGN_FRAC(1,1),
	894	RGN_FRAC(1,2),
472	895	1,
473	896	{ 0 },
474	897	{ 0,0, 1,1, 2,2, 3,3, 4,4, 5,5, 6,6, 7,7, 8,8, 9,9, 10,10, 11,11, 12,12, 13,13, 14,14, 15,15 },
r5534	r5535
482	905	* Graphics Decode Information *
483	906	******************************/
484	907
	908	/* GFX are stored in the 2nd half... Maybe the HW could handle 2 bitplanes? */
485	909	static GFXDECODE_START( norautp )
486		GFXDECODE_ENTRY( "gfx", 0, charlayout, 0, 4 )
487		GFXDECODE_ENTRY( "gfx", 0, charlayout32x32, 0, 4 )
	910	GFXDECODE_ENTRY( "gfx", 0x800, charlayout, 0, 4 )
	911	GFXDECODE_ENTRY( "gfx", 0x800, charlayout32x32, 0, 4 )
488	912	GFXDECODE_END
489	913
490	914
r5534	r5535
495	919	static const ppi8255_interface ppi8255_intf[3] =
496	920	{
497	921	{ /* (60-63) Mode 0 - Port A set as input */
498		DEVCB_INPUT_PORT("DSW1"), /* Port A read */
499		DEVCB_NULL, /* Port B read */
500		DEVCB_NULL, /* Port C read */
501		DEVCB_NULL, /* Port A write */
502		DEVCB_HANDLER(lamps_w), /* Port B write */
503		DEVCB_HANDLER(ccounter_w) /* Port C write */
	922	DEVCB_INPUT_PORT("DSW1"), /* Port A read */
	923	DEVCB_NULL, /* Port B read */
	924	DEVCB_NULL, /* Port C read */
	925	DEVCB_NULL, /* Port A write */
	926	DEVCB_HANDLER(mainlamps_w), /* Port B write */
	927	DEVCB_HANDLER(counterlamps_w) /* Port C write */
504	928	},
505	929	{ /* (a0-a3) Mode 0 - Ports A & B set as input */
506		DEVCB_INPUT_PORT("IN0"), /* Port A read */
507		DEVCB_INPUT_PORT("IN1"), /* Port B read */
508		DEVCB_NULL, /* Port C read */
509		DEVCB_NULL, /* Port A write */
510		DEVCB_NULL, /* Port B write */
511		DEVCB_HANDLER(sndlamp_w) /* Port C write */
	930	DEVCB_INPUT_PORT("IN0"), /* Port A read */
	931	DEVCB_INPUT_PORT("IN1"), /* Port B read */
	932	DEVCB_NULL, /* Port C read */
	933	DEVCB_NULL, /* Port A write */
	934	DEVCB_NULL, /* Port B write */
	935	DEVCB_HANDLER(soundlamps_w) /* Port C write */
512	936	},
513	937	{ /* (c0-c3) Group A Mode 2 (5-handshacked bidirectional port) */
514		DEVCB_NULL, /* Port A read */
515		DEVCB_NULL, /* Port B read */
516		DEVCB_NULL, /* Port C read */
517		DEVCB_NULL, /* Port A write */
518		DEVCB_NULL, /* Port B write */
519		DEVCB_NULL /* Port C write */
	938	DEVCB_NULL, /* Port A read */
	939	DEVCB_NULL, /* Port B read */
	940	DEVCB_NULL, /* Port C read (should has test_r tied) */
	941	DEVCB_NULL, /* Port A write (should has vram_data_w tied) */
	942	DEVCB_NULL, /* Port B write (should has vram_addr_w tied) */
	943	DEVCB_NULL /* Port C write */
520	944	}
521	945	};
522	946
r5534	r5535
546	970	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
547	971	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
548	972	MDRV_SCREEN_SIZE(3216, 3216)
549		MDRV_SCREEN_VISIBLE_AREA(216, 3116-1, 016, 1616-1)
	973	MDRV_SCREEN_VISIBLE_AREA(316, 3116-1, (016) + 8, 1616-1) /* the hardware clips the top 8 pixels */
550	974
551	975	MDRV_GFXDECODE(norautp)
552	976
r5534	r5535
616	1040	ROM_LOAD( "char.bin", 0x0000, 0x1000, CRC(955eac6f) SHA1(470d8bad1a5d2a0a08dd129e6393c3c3a4ef2159) )
617	1041	ROM_END
618	1042
	1043	/*
	1044	Noraut Joker Poker
619	1045
	1046	Program:27C64
	1047	Marked:
	1048	"MX10A JOKER G.L
	1049	N.C.R C.C M.S"
	1050
	1051	Char:2732
	1052	Marked:
	1053	"N1-057-5"
	1054
	1055	CPU: TMPZ84C00AP-8
	1056	*/
	1057
620	1058	ROM_START( norautjp )
621	1059	ROM_REGION( 0x10000, "maincpu", 0 )
622	1060	ROM_LOAD( "2764-1prog.bin", 0x0000, 0x2000, CRC(5f776ce1) SHA1(673b8c67ebd5c1334187a9407b86a43150cbe67b) )
623	1061
624		ROM_REGION( 0x800, "gfx", 0 )
625		ROM_LOAD( "2732-1char.bin", 0x0000, 0x0800, CRC(d94be899) SHA1(b7212162324fa2d67383a475052e3b351bb1af5f) ) /* first half 0xff filled */
626		ROM_CONTINUE( 0x0000, 0x0800 )
	1062	ROM_REGION( 0x1000, "gfx", 0 )
	1063	ROM_FILL( 0x0000, 0x0800, 0xff )
	1064	ROM_LOAD( "2732-1char.bin", 0x0800, 0x0800, CRC(d94be899) SHA1(b7212162324fa2d67383a475052e3b351bb1af5f) ) /* first half 0xff filled */
	1065	ROM_CONTINUE( 0x0800, 0x0800 )
	1066
	1067	ROM_REGION( 0x400, "nvram", 0 )
	1068	ROM_LOAD( "norautjp_nv.bin", 0x0000, 0x0400, CRC(0a0614b2) SHA1(eb21b2723b41743daf787cfc379bc67cce2b8538) ) /* default NVRAM */
	1069
627	1070	ROM_END
628	1071
	1072	/*
	1073	Noraut Red Hot Joker Poker
	1074	Red hot joker poker scrolls across screen
	1075	and eprom has Red Hot on sticker
	1076	Char:
	1077	Handwritten sticker with "Club250 grapics" on it
	1078
	1079	Pressing the readout button brings you to a menu with RESET / READOUT
	1080	pressing on Readout brings you to "coins in" and "coins out" and "balance".
	1081
	1082	No date info on board or found in rom
	1083	*/
	1084
	1085	ROM_START( norautrh )
	1086	ROM_REGION( 0x10000, "maincpu", 0 )
	1087	ROM_LOAD( "norautrh.bin", 0x0000, 0x2000, CRC(f5447d1a) SHA1(75d6439481e469e82e5561146966c9c7b44f34fe) )
	1088
	1089	ROM_REGION( 0x1000, "gfx", 0 )
	1090	ROM_LOAD( "club250.bin", 0x0000, 0x1000, CRC(d94be899) SHA1(b7212162324fa2d67383a475052e3b351bb1af5f) )
	1091	ROM_END
	1092
	1093	/*
	1094	Unknown Noraut: "NTX10A V6"
	1095	None working old noraut board with daughter card upgrade
	1096	daughter card looks like an old upgrade PCB marked:
	1097	"Noraut LTD Game Module"
	1098	half of which is incased in epoxy resin.
	1099	only thing not visble on this board compared to others i have is the cpu
	1100	with is under the epoxy not sure what else is their.
	1101
	1102	D Card contains:
	1103	Backup Battery
	1104
	1105	Program Eprom:27C256
	1106	Marked: "NTX10A V6"
	1107	"C201"
	1108
	1109	CPU:
	1110	Unknown Incased in epoxy
	1111
	1112	NVRAM: HY6264A
	1113
	1114	PAL:
	1115	PAL16L8ACN
	1116
	1117	Charcter Eprom is mounted on main board
	1118	CHAR Eprom:2732
	1119	Marked: "GU27"
	1120
	1121	daughter card is connected on to another card containing only pcb tracks no components
	1122	This second board connects to main board with ribbon cable to the 40pin socket where
	1123	the original cpu would of been.
	1124
	1125	No date info on board or found in rom.
	1126	*/
	1127
	1128	ROM_START( norautu )
	1129	ROM_REGION( 0x10000, "maincpu", 0 )
	1130	ROM_LOAD( "2563.bin", 0x0000, 0x8000, CRC(6cbe68bd) SHA1(93201baaf03a9bba6c52c64cc26e8e445aa6454e) )
	1131
	1132	ROM_REGION( 0x1000, "gfx", 0 )
	1133	ROM_LOAD( "club250.bin", 0x0000, 0x1000, CRC(d94be899) SHA1(b7212162324fa2d67383a475052e3b351bb1af5f) )
	1134	ROM_END
	1135
	1136
	1137	/*NORAUT V3.010a:
	1138	Board upgraded with daughter card.
	1139	daughter card looks modern and is marked
	1140	"memory expansion module"
	1141	"Unique Ireland"
	1142
	1143	D Card contains:
	1144	Backup Battery
	1145
	1146	Program Eprom:27C512
	1147	Marked:
	1148	"G45P A V3.010a GU27
	1149	Euro 27C512 20MAR02"
	1150
	1151
	1152	PAL:PAL16l8ANC
	1153	Marked VER.2
	1154
	1155	CPU:
	1156	Zilog
	1157	Z8400APS
	1158	Z80 CPU
	1159
	1160	NVRAM: 6116
	1161
	1162	Two jumpers on card , game will not boot if these are removed or placed on other pins
	1163	cabinet beeps and shows grapics on screen. Removing while game is on cause game to freeze.
	1164	Unknown what their for.
	1165
	1166	Charcter Eprom is mounted on main board
	1167	CHAR Eprom:2716
	1168	Marked "GU27"
	1169
	1170	No date info found in rom, program eprom sticker "Euro 27C512 20MAR02"
	1171	This version contains a hidden menu with lots of differnt options
	1172	to access this menu you must hold the HI and LOW button and press the readout/test switch
	1173	the screen will go blank then you release the 3 buttons and the menu appears.
	1174
	1175	Pressing the readout button brings you to a menu with RESET / READOUT
	1176	pressing on Readout brings you to "coins in" and "coins out" and "balance".
	1177
	1178	The daughter card connects direct to main pcb through 40 pins into original cpu socket
	1179	and 12 pins to one side of original program eprom.
	1180	*/
	1181
	1182	ROM_START( norautv3 )
	1183	ROM_REGION( 0x10000, "maincpu", 0 )
	1184	ROM_LOAD( "g45pa.bin", 0x0000, 0x10000, CRC(f966f4d2) SHA1(99c21ceb59664f32fd1269351fa976370d486f2e) )
	1185
	1186	ROM_REGION( 0x1000, "gfx", 0 )
	1187	ROM_FILL( 0x0000, 0x0800, 0xff )
	1188	ROM_LOAD( "gu27.bin", 0x0800, 0x0800, CRC(174a5eec) SHA1(44d84a0cf29a0bf99674d95084c905d3bb0445ad) )
	1189	ROM_END
	1190
	1191
629	1192	/*************************
630	1193	* Game Drivers *
631	1194	*************************/
632	1195
633		/* YEAR NAME PARENT MACHINE INPUT INIT ROT COMPANY FULLNAME FLAGS */
634		GAME( 1988, norautp, 0, norautp, norautp, 0, ROT0, "Noraut Ltd.", "Noraut Poker", GAME_NO_SOUND \| GAME_IMPERFECT_COLORS )
635		GAME( 1988, norautjp, norautp, norautp, norautp, 0, ROT0, "Noraut Ltd.", "Noraut Joker Poker", GAME_NO_SOUND \| GAME_IMPERFECT_COLORS )
636		GAME( 1983, gtipoker, 0, gtipoker, norautp, 0, ROT0, "GTI Inc", "GTI Poker", GAME_NO_SOUND \| GAME_IMPERFECT_COLORS \| GAME_NOT_WORKING )
	1196	/* YEAR NAME PARENT MACHINE INPUT INIT ROT COMPANY FULLNAME FLAGS LAYOUT */
	1197	GAMEL( 1988, norautp, 0, norautp, norautp, 0, ROT0, "Noraut Ltd.", "Noraut Poker", GAME_NO_SOUND, layout_noraut11 )
	1198	GAMEL( 1988, norautjp, norautp, norautp, norautp, 0, ROT0, "Noraut Ltd.", "Noraut Joker Poker", GAME_NO_SOUND, layout_noraut11 )
	1199	GAMEL( 1988, norautrh, 0, norautp, norautrh, 0, ROT0, "Noraut Ltd.", "Noraut Red Hot Joker Poker", GAME_NO_SOUND, layout_noraut12 )
	1200	GAME( 1988, norautu, 0, norautp, norautp, 0, ROT0, "Noraut Ltd.", "Noraut Poker (NTX10A)", GAME_NO_SOUND \| GAME_NOT_WORKING )
	1201	GAME( 1988, norautv3, 0, norautp, norautp, 0, ROT0, "Noraut Ltd.", "Noraut Joker Poker (V3.010a)", GAME_NO_SOUND \| GAME_NOT_WORKING )
	1202	GAME( 1983, gtipoker, 0, gtipoker, norautp, 0, ROT0, "GTI Inc", "GTI Poker", GAME_NO_SOUND \| GAME_NOT_WORKING )
637	1203
638	1204	/The following has everything uncertain, seems a bootleg/hack and doesn't have any identification strings in program rom. /
639		GAME( 198?, norautpn, norautp, norautp, ~~poke~~r, 0, ROT0, "bootleg?", "Noraut Poker (bootleg)", GAME_NO_SOUND \| ~~GAME~~_~~IMPERFECT_COLORS~~ )
	1205	GAMEL( 198?, norautpn, norautp, norautp, naroutpn, 0, ROT0, "bootleg?", "Noraut Poker (bootleg)", GAME_NO_SOUND, layout_noraut12 )

src/mame/drivers/kaneko16.c
r5534	r5535
57	57	- Finish the Inputs (different wheels and pedals)
58	58	- Find infos about the communication stuff (even if it won't be supported)
59	59
	60	[brapboys / shogwarr]
	61
	62	- Verify collision protection on real hardware
	63	- Figure out how MCU resets writeback address (currently hacked)
	64	- Find relationship between Key tables and final datablock
	65	- Clean up debug code file writes etc. (when above are done only!)
	66	- Interrupt timing? (some sprites flicker)
	67	- Sprite buffering (2 frames?, or related to above)
	68
60	69	Dip locations verified from manual for:
61	70
62	71	- berlwall
r5534	r5535
68	77	- gtmr2
69	78	- shogwarr
70	79
	80
	81
71	82	***************************************************************************/
72	83
73	84	#include "driver.h"
r5534	r5535
80	91	#include "sound/2151intf.h"
81	92	#include "sound/okim6295.h"
82	93
83		UINT16* kaneko16_calc3_fakeram;
84	94	static UINT16* kaneko16_mainram;
85	95
86	96	/***************************************************************************
r5534	r5535
98	108	kaneko16_sprite_xoffs = 0;
99	109	kaneko16_sprite_yoffs = 0;
100	110
	111	kaneko16_sprite_fliptype = 0;
	112
101	113	/*
102	114	Sx = Sprites with priority x, x = tiles with priority x,
103	115	Sprites - Tiles Order (bottom -> top):
r5534	r5535
231	243
232	244	kaneko16_sprite_xoffs = 0xa00;
233	245
234		kaneko16_sprite_yoffs = 0x200;
	246	kaneko16_sprite_yoffs = -0x40;
235	247
	248	kaneko16_sprite_type = 0;
	249	kaneko16_sprite_fliptype = 1;
236	250
237		kaneko16_priority.sprite[0] = 2; // below all
	251	kaneko16_priority.sprite[0] = 1; // below all
238	252	kaneko16_priority.sprite[1] = 3; // above tile[0], below the others
239	253	kaneko16_priority.sprite[2] = 5; // above all
240	254	kaneko16_priority.sprite[3] = 7; // ""
r5534	r5535
791	805	Shogun Warriors
792	806	***************************************************************************/
793	807
794		/* Untested */
	808	/* Works for B-Rap Boys - untested with Shogun Warriors */
795	809	static WRITE16_HANDLER( shogwarr_oki_bank_w )
796	810	{
797	811	if (ACCESSING_BITS_0_7)
798	812	{
799		okim6295_set_bank_base(devtag_get_device(space->machine, "oki1"), 0x10000 * ((data >> 0) & 0x3) );
800		okim6295_set_bank_base(devtag_get_device(space->machine, "oki2"), 0x10000 * ((data >> 4) & 0x3) );
	813	okim6295_set_bank_base(devtag_get_device(space->machine, "oki1"), 0x40000 * ((data >> 4) & 0xf));
	814	okim6295_set_bank_base(devtag_get_device(space->machine, "oki2"), 0x40000 * (data & 0xf));
801	815	}
802	816	}
803	817
	818	extern void calc3_mcu_run(running_machine *machine);
	819
	820	WRITE16_HANDLER(shogwarr_calc_w);
	821	READ16_HANDLER(shogwarr_calc_r);
	822
	823
804	824	static ADDRESS_MAP_START( shogwarr, ADDRESS_SPACE_PROGRAM, 16 )
805	825	AM_RANGE(0x000000, 0x03ffff) AM_ROM // ROM
806	826	AM_RANGE(0x100000, 0x10ffff) AM_RAM AM_BASE(&kaneko16_mainram) // Work RAM
r5534	r5535
808	828	AM_RANGE(0x280000, 0x280001) AM_WRITE(calc3_mcu_com0_w)
809	829	AM_RANGE(0x290000, 0x290001) AM_WRITE(calc3_mcu_com1_w)
810	830	AM_RANGE(0x2b0000, 0x2b0001) AM_WRITE(calc3_mcu_com2_w)
	831	//AM_RANGE(0x2c0000, 0x2c0001) AM_WRITE(calc3_run) // guess, might be irqack
811	832	AM_RANGE(0x2d0000, 0x2d0001) AM_WRITE(calc3_mcu_com3_w)
812	833	AM_RANGE(0x380000, 0x380fff) AM_RAM_WRITE(paletteram16_xGGGGGRRRRRBBBBB_word_w) AM_BASE(&paletteram16) // Palette
813	834	AM_RANGE(0x400000, 0x400001) AM_DEVREADWRITE8("oki1", okim6295_r, okim6295_w, 0x00ff) // Samples
r5534	r5535
819	840	AM_RANGE(0x603000, 0x603fff) AM_RAM AM_BASE(&kaneko16_vscroll_0)
820	841	AM_RANGE(0x800000, 0x80000f) AM_RAM_WRITE(kaneko16_layers_0_regs_w) AM_BASE(&kaneko16_layers_0_regs) // Layers 0 Regs
821	842	AM_RANGE(0x900000, 0x90001f) AM_RAM_WRITE(kaneko16_sprites_regs_w) AM_BASE(&kaneko16_sprites_regs) // Sprites Regs
822		AM_RANGE(0xa00014, 0xa00015) AM_READ(~~kanek~~o~~16_~~rnd_r) // Random Number ?
	843	AM_RANGE(0xa00000, 0xa0007f) AM_READWRITE(shogwarr_calc_r, shogwarr_calc_w) // Random Number ?
823	844	AM_RANGE(0xa80000, 0xa80001) AM_READWRITE(watchdog_reset16_r, watchdog_reset16_w) // Watchdog
824	845	AM_RANGE(0xb80000, 0xb80001) AM_READ_PORT("P1")
825	846	AM_RANGE(0xb80002, 0xb80003) AM_READ_PORT("P2")
r5534	r5535
827	848	AM_RANGE(0xb80006, 0xb80007) AM_READ_PORT("UNK")
828	849	AM_RANGE(0xd00000, 0xd00001) AM_NOP // ? (bit 0)
829	850	AM_RANGE(0xe00000, 0xe00001) AM_WRITE(shogwarr_oki_bank_w) // Samples Bankswitching
830
831		AM_RANGE(0xf00000, 0xffffff) AM_RAM AM_BASE(&kaneko16_calc3_fakeram) // I copy protection data tables here because I don't know where they really go. NOT ON PCB
832	851	ADDRESS_MAP_END
833	852
834	853
r5534	r5535
1566	1585	INPUT_PORTS_END
1567	1586
1568	1587
	1588	static INPUT_PORTS_START( brapboys )
	1589	PORT_START("P1") /* b80000.w */
	1590	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
	1591	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
	1592	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
	1593	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
	1594	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
	1595	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
	1596	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_START1 )
	1597	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_COIN1 )
1569	1598
	1599	PORT_START("P2") /* b80002.w */
	1600	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
	1601	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
	1602	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
	1603	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
	1604	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
	1605	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
	1606	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_START2 )
	1607	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_COIN2 )
	1608
	1609	PORT_START("SYSTEM") /* b80004.w */
	1610	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
	1611	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
	1612	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
	1613	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
	1614	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
	1615	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
	1616	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_START3 )
	1617	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_COIN3 )
	1618
	1619	PORT_START("UNK") /* ? - b80006.w */
	1620	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1621	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1622	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1623	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1624	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1625	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1626	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1627	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
	1628
	1629	PORT_START("DSW1")
	1630	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:1")
	1631	PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
	1632	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1633	PORT_SERVICE_DIPLOC(0x02, IP_ACTIVE_LOW, "SW1:2" )
	1634	PORT_DIPNAME( 0x04, 0x04, "Switch Test" ) PORT_DIPLOCATION("SW1:3")
	1635	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
	1636	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
	1637	PORT_DIPUNUSED_DIPLOC(0x08, 0x08, "SW1:4" )
	1638	PORT_DIPNAME( 0x10, 0x10, "Coin Slots" ) PORT_DIPLOCATION("SW1:5")
	1639	PORT_DIPSETTING( 0x10, "Separate Coins" )
	1640	PORT_DIPSETTING( 0x00, "Shared Coins" )
	1641	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Players ) ) PORT_DIPLOCATION("SW1:6")
	1642	PORT_DIPSETTING( 0x20, "3" )
	1643	PORT_DIPSETTING( 0x00, "2" )
	1644	PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW1:7,8")
	1645	PORT_DIPSETTING( 0x80, DEF_STR( Easy ) )
	1646	PORT_DIPSETTING( 0xc0, DEF_STR( Normal ) )
	1647	PORT_DIPSETTING( 0x40, DEF_STR( Hard ) )
	1648	PORT_DIPSETTING( 0x00, DEF_STR( Very_Hard) )
	1649
	1650	/*****************************************************
	1651	Difficulty Lives Bonus Players Play Level
	1652	Easy 3 every 1000 / 2000 Level 2
	1653	Normal 2 every 2000 / 3000 Level 3
	1654	Hard 2 every 3000 / 4000 Level 4
	1655	Very Hard 1 --- NONE --- Level 6
	1656	******************************************************/
	1657
	1658	INPUT_PORTS_END
	1659
	1660
1570	1661	/***************************************************************************
1571	1662
1572	1663
r5534	r5535
1983	2074
1984	2075	other: busy loop
1985	2076	*/
	2077
1986	2078	#define SHOGWARR_INTERRUPTS_NUM 3
1987	2079	static INTERRUPT_GEN( shogwarr_interrupt )
1988	2080	{
r5534	r5535
1992	2084	case 1: cpu_set_input_line(device, 3, HOLD_LINE); break;
1993	2085
1994	2086	// the code for this interupt is provided by the MCU..
1995		case 0: cpu_set_input_line(device, 4, HOLD_LINE); break;
	2087	case 0: cpu_set_input_line(device, 4, HOLD_LINE);
	2088
	2089	calc3_mcu_run(device->machine);
	2090	break;
1996	2091	/*case 0:
1997	2092	{
1998	2093	// hack, clear this ram address to get into test mode (interrupt would clear it)
r5534	r5535
2005	2100	}
2006	2101	}
2007	2102
	2103	/*
	2104	unsigned char shogwarr_default_eeprom[128] = {
	2105	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	2106	0x4B, 0x41, 0x4E, 0x45, 0x4B, 0x4F, 0x2F, 0x41, 0x54, 0x4F, 0x50, 0x20, 0x31, 0x39, 0x39, 0x32,
	2107	0x46, 0x55, 0x4A, 0x49, 0xFF, 0xFF, 0x4D, 0x41, 0x20, 0x42, 0x55, 0x53, 0x54, 0x45, 0x52, 0x20,
	2108	0x20, 0x53, 0x48, 0x4F, 0xFF, 0xFF, 0x4E, 0x20, 0x57, 0x41, 0x52, 0x52, 0x49, 0x4F, 0x52, 0x53,
	2109	0xFF, 0xFF, 0x70, 0x79, 0x72, 0x69, 0xFF, 0xFF, 0x74, 0x20, 0x4B, 0x41, 0x4E, 0x45, 0x4B, 0x4F,
	2110	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	2111	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF,
	2112	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF
	2113	};
	2114	*/
	2115	// the above eeprom looks corrupt, some of the text is wrong, the game never writes this text tho.. maybe it should be as below
	2116	// leaving both here incase they relate to which tables get 'locked out' by the MCU somehow
	2117	UINT8 shogwarr_default_eeprom[128] = {
	2118	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	2119	0x4B, 0x41, 0x4E, 0x45, 0x4B, 0x4F, 0x2F, 0x41, 0x54, 0x4F, 0x50, 0x20, 0x31, 0x39, 0x39, 0x32,
	2120	0x46, 0x55, 0x4A, 0x49, 0x59, 0x41, 0x4D, 0x41, 0x20, 0x42, 0x55, 0x53, 0x54, 0x45, 0x52, 0x20,
	2121	0x20, 0x53, 0x48, 0x4F, 0x47, 0x55, 0x4E, 0x20, 0x57, 0x41, 0x52, 0x52, 0x49, 0x4F, 0x52, 0x53,
	2122	0x63, 0x6F, 0x70, 0x79, 0x72, 0x69, 0x67, 0x68, 0x74, 0x20, 0x4B, 0x41, 0x4E, 0x45, 0x4B, 0x4F,
	2123	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	2124	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF,
	2125	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF
	2126	};
	2127
	2128	UINT8 brapboys_default_eeprom[128] = {
	2129	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	2130	0x00, 0x00, 0x00, 0x05, 0x00, 0x06, 0x20, 0x30, 0x00, 0x03, 0x68, 0x18, 0x01, 0x01, 0x01, 0x01,
	2131	0x01, 0x01, 0x00, 0x01, 0x00, 0x04, 0x00, 0x08, 0x4B, 0x41, 0x4E, 0x45, 0x4B, 0x4F, 0x20, 0x20,
	2132	0x42, 0x65, 0x20, 0x52, 0x61, 0x70, 0x20, 0x42, 0x6F, 0x79, 0x73, 0x00, 0x30, 0x30, 0x30, 0x2E,
	2133	0x30, 0x38, 0x10, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
	2134	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
	2135	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
	2136	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x35, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
	2137	};
	2138
	2139	static NVRAM_HANDLER( shogwarr )
	2140	{
	2141	int isbrap = ( !strcmp(machine->gamedrv->name,"brapboysj") \|\| !strcmp(machine->gamedrv->name,"brapboys"));
	2142
	2143	if (read_or_write)
	2144	eeprom_save(file);
	2145	else
	2146	{
	2147	eeprom_init(machine, &eeprom_interface_93C46);
	2148
	2149	if (file) eeprom_load(file);
	2150	else
	2151	{
	2152	if (isbrap)
	2153	eeprom_set_data(brapboys_default_eeprom,128);
	2154	else
	2155	eeprom_set_data(shogwarr_default_eeprom,128);
	2156	}
	2157	}
	2158	}
	2159
2008	2160	static MACHINE_DRIVER_START( shogwarr )
2009	2161
2010	2162	/* basic machine hardware */
r5534	r5535
2020	2172	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
2021	2173	MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
2022	2174	MDRV_SCREEN_SIZE(320, 240)
2023		MDRV_SCREEN_VISIBLE_AREA(40, 296-1, 0, 240-1)
	2175	MDRV_SCREEN_VISIBLE_AREA(40, 296-1, 16, 240-1)
2024	2176
2025	2177	MDRV_GFXDECODE(1x4bit_1x4bit)
2026	2178	MDRV_PALETTE_LENGTH(2048)
r5534	r5535
2028	2180	MDRV_VIDEO_START(kaneko16_1xVIEW2)
2029	2181	MDRV_VIDEO_UPDATE(kaneko16)
2030	2182
	2183	MDRV_NVRAM_HANDLER(shogwarr)
	2184
2031	2185	/* sound hardware */
2032	2186	MDRV_SPEAKER_STANDARD_MONO("mono")
2033	2187
r5534	r5535
3470	3624	ROM_REGION( 0x020000, "cpu1", 0 ) /* MCU Code */
3471	3625	ROM_LOAD( "rb-040.u33", 0x000000, 0x020000, CRC(757c6e19) SHA1(0f1c37b1b1eb6b230c593e4648c4302f413a61f5) )
3472	3626
3473		ROM_REGION( 0x400000, "gfx1", 0 ) /* Sprites */
3474		/* order is probably wrong, but until it does more we can't tell */
3475		ROM_LOAD( "rb-020.u2", 0x000000, 0x080000, CRC(b038440e) SHA1(9e32cb62358ab846470d9a75d4dab771d608a3cf) )
3476		ROM_LOAD( "rb-025.u80", 0x080000, 0x040000, CRC(36cd6b90) SHA1(45c50f2652726ded67c9c24185a71a6367e09270) ) // Correct size for this set
3477		// ROM_LOAD( "rb-026.u5", 0x100000, 0x080000, CRC(bb7604d4) SHA1(57d51ce4ea2000f9a50bae326cfcb66ec494249f) ) // Not in World set
	3627	ROM_REGION( 0x800000, "gfx1", 0 ) /* Sprites */
	3628	ROM_LOAD( "rb-020.c2", 0x000000, 0x100000, CRC(ce220d38) SHA1(b88d7c89a3e1a826bf19a1fa692ec77c944596d9) )
	3629	ROM_LOAD( "rb-021.u76", 0x100000, 0x100000, CRC(74001407) SHA1(90002056ceb4e0401246950b8c3f996af0a2463c) )
	3630	ROM_LOAD( "rb-022.u77", 0x200000, 0x100000, CRC(cb3f42dc) SHA1(5415f15621924dd263b8fe7daaf3dc25d470b814) )
	3631	ROM_LOAD( "rb-023.u78", 0x300000, 0x100000, CRC(0e6530c5) SHA1(72bff46f0672927e540f4f3546ae533dd0a231e0) )
	3632	ROM_LOAD( "rb-024.u79", 0x400000, 0x080000, CRC(65fa6447) SHA1(551e540d7bf412753b4a7098e25e6f9d8774bcf4) ) // correct, both halves identical when dumped as larger
	3633	ROM_LOAD( "rb-025.u80", 0x500000, 0x040000, CRC(36cd6b90) SHA1(45c50f2652726ded67c9c24185a71a6367e09270) ) // eprom, contains title logo for this version
3478	3634
3479		ROM_LOAD( "rb-021.u76", 0x200000, 0x080000, CRC(b7e2d362) SHA1(7e98e5b3d1ee972fc4cf9bebd33a3ca96a77357c) )
3480		ROM_LOAD( "rb-022.u77", 0x280000, 0x080000, CRC(8d40c97a) SHA1(353b0a4a508f2fff8eeed680b1f685c7fdc29a7d) ) // right pos. (text)
3481		ROM_LOAD( "rb-023.u78", 0x300000, 0x080000, CRC(dcf11c8d) SHA1(eed801f7cca3d3a941b1a4e4815cac9d20d970f7) )
3482		ROM_LOAD( "rb-024.u79", 0x380000, 0x080000, CRC(65fa6447) SHA1(551e540d7bf412753b4a7098e25e6f9d8774bcf4) )
3483
3484	3635	ROM_REGION( 0x400000, "gfx2", 0 ) /* Tiles (scrambled) */
3485	3636	ROM_LOAD( "rb-010.u65", 0x000000, 0x100000, CRC(ffd73f87) SHA1(1a661f71976be61c22d9b962850e738ba17f1d45) )
3486	3637	ROM_LOAD( "rb-011.u66", 0x100000, 0x100000, CRC(d9325f78) SHA1(346832608664aa8f3ac9260a549903386b4125a8) )
3487	3638	ROM_LOAD( "rb-012.u67", 0x200000, 0x100000, CRC(bfdbe0d1) SHA1(3abc5398ee8ee1871b4d081f9b748539d69bcdba) )
3488	3639	ROM_LOAD( "rb-013.u68", 0x300000, 0x100000, CRC(28c37fe8) SHA1(e10dd1a810983077328b44e6e33ce2e899c506d2) )
3489	3640
3490		ROM_REGION( 0x100000, "oki1", 0 ) /* Samples */
3491		/* Upper 128kB of M6295 address region is bank-switched? */
	3641	ROM_REGION( 0x300000, "samples", 0 )
	3642	/* OKI 1 */
3492	3643	ROM_LOAD( "rb-000.u43", 0x000000, 0x080000, CRC(58ad1a62) SHA1(1d2643b5f6eac22682972a88d284e00de3e3b223) )
3493	3644	ROM_LOAD( "rb-003.101", 0x080000, 0x080000, CRC(2cac25d7) SHA1(0412c317bf650a93051b9304d23035efde0c026a) )
3494	3645
3495		ROM_REGION( 0x200000, "oki2", 0 ) /* Samples */
3496		/* Upper 128kB of M6295 address region is bank-switched? */
3497		ROM_LOAD( "rb-001.u44", 0x000000, 0x100000, CRC(7cf774b3) SHA1(3fb0a5096ce9480f97e311439042eb8cbc26efb4) )
3498		ROM_LOAD( "rb-002.u45", 0x100000, 0x100000, CRC(e4b30444) SHA1(be6756dce3721226e0b7f5d4d168008c31aeea8e) )
	3646	/* OKI 2 */
	3647	ROM_LOAD( "rb-001.u44", 0x100000, 0x100000, CRC(7cf774b3) SHA1(3fb0a5096ce9480f97e311439042eb8cbc26efb4) )
	3648	ROM_LOAD( "rb-002.u45", 0x200000, 0x100000, CRC(e4b30444) SHA1(be6756dce3721226e0b7f5d4d168008c31aeea8e) )
	3649
	3650	/* Sound data is copied here during driver init */
	3651	ROM_REGION( 0x400000*16, "oki1", 0 )
	3652	ROM_FILL( 0x00000, 0x400000*16, 0x00 )
	3653
	3654	ROM_REGION( 0x400000*16, "oki2", 0 )
	3655	ROM_FILL( 0x00000, 0x400000*16, 0x00 )
3499	3656	ROM_END
3500	3657
	3658
3501	3659	ROM_START( brapboysj ) /* The Japanese version has an extra rom??? and used a rom sub board */
3502	3660	ROM_REGION( 0x040000, "maincpu", 0 ) /* 68000 Code */
3503	3661	ROM_LOAD16_BYTE( "rb-004.u61", 0x000000, 0x020000, CRC(5432442c) SHA1(f0f7328ece96ef25e6d4fd1958d734f64a9ef371) )
r5534	r5535
3506	3664	ROM_REGION( 0x020000, "cpu1", 0 ) /* MCU Code */
3507	3665	ROM_LOAD( "rb-006.u33", 0x000000, 0x020000, CRC(f1d76b20) SHA1(c571b5f28e529589ee2d7697ef5d4b60ccb66e7a) )
3508	3666
3509		ROM_REGION( 0x400000, "gfx1", 0 ) /* Sprites */
3510		/* order is probably wrong, but until it does more we can't tell */
3511		ROM_LOAD( "rb-020.u2", 0x000000, 0x080000, CRC(b038440e) SHA1(9e32cb62358ab846470d9a75d4dab771d608a3cf) )
3512		ROM_LOAD( "rb-025.u4", 0x080000, 0x080000, CRC(aa795ba5) SHA1(c5256dcceded2e76f548b60c18e51d0dd0209d81) )
3513		ROM_LOAD( "rb-026.u5", 0x100000, 0x080000, CRC(bb7604d4) SHA1(57d51ce4ea2000f9a50bae326cfcb66ec494249f) )
	3667	ROM_REGION( 0x1000000, "gfx1", 0 ) /* Sprites */
	3668	/* prety sure all these are at least half size */
	3669	ROM_LOAD( "rb-020.c2", 0x000000, 0x100000, CRC(ce220d38) SHA1(b88d7c89a3e1a826bf19a1fa692ec77c944596d9) )
	3670	ROM_LOAD( "rb-021.u76", 0x100000, 0x100000, CRC(74001407) SHA1(90002056ceb4e0401246950b8c3f996af0a2463c) )
	3671	ROM_LOAD( "rb-022.u77", 0x200000, 0x100000, CRC(cb3f42dc) SHA1(5415f15621924dd263b8fe7daaf3dc25d470b814) )
	3672	ROM_LOAD( "rb-023.u78", 0x300000, 0x100000, CRC(0e6530c5) SHA1(72bff46f0672927e540f4f3546ae533dd0a231e0) )
	3673	ROM_LOAD( "rb-024.u79", 0x400000, 0x080000, CRC(65fa6447) SHA1(551e540d7bf412753b4a7098e25e6f9d8774bcf4) ) // correct, both halves identical when dumped as larger
	3674	ROM_LOAD( "rb-025.u4", 0x500000, 0x080000, CRC(aa795ba5) SHA1(c5256dcceded2e76f548b60c18e51d0dd0209d81) ) // eprom, special title screen
	3675	ROM_LOAD( "rb-026.u5", 0x580000, 0x080000, CRC(bb7604d4) SHA1(57d51ce4ea2000f9a50bae326cfcb66ec494249f) ) // eprom, logs that bounce past
3514	3676
3515		ROM_LOAD( "rb-021.u76", 0x200000, 0x080000, CRC(b7e2d362) SHA1(7e98e5b3d1ee972fc4cf9bebd33a3ca96a77357c) )
3516		ROM_LOAD( "rb-022.u77", 0x280000, 0x080000, CRC(8d40c97a) SHA1(353b0a4a508f2fff8eeed680b1f685c7fdc29a7d) ) // right pos. (text)
3517		ROM_LOAD( "rb-023.u78", 0x300000, 0x080000, CRC(dcf11c8d) SHA1(eed801f7cca3d3a941b1a4e4815cac9d20d970f7) )
3518		ROM_LOAD( "rb-024.u79", 0x380000, 0x080000, CRC(65fa6447) SHA1(551e540d7bf412753b4a7098e25e6f9d8774bcf4) )
3519	3677
3520	3678	ROM_REGION( 0x400000, "gfx2", 0 ) /* Tiles (scrambled) */
3521	3679	ROM_LOAD( "rb-010.u65", 0x000000, 0x100000, CRC(ffd73f87) SHA1(1a661f71976be61c22d9b962850e738ba17f1d45) )
r5534	r5535
3523	3681	ROM_LOAD( "rb-012.u67", 0x200000, 0x100000, CRC(bfdbe0d1) SHA1(3abc5398ee8ee1871b4d081f9b748539d69bcdba) )
3524	3682	ROM_LOAD( "rb-013.u68", 0x300000, 0x100000, CRC(28c37fe8) SHA1(e10dd1a810983077328b44e6e33ce2e899c506d2) )
3525	3683
3526		ROM_REGION( 0x100000, "oki1", 0 ) /* Samples */
3527		/* Upper 128kB of M6295 address region is bank-switched? */
	3684	ROM_REGION( 0x300000, "samples", 0 )
	3685	/* OKI 1 */
3528	3686	ROM_LOAD( "rb-000.u43", 0x000000, 0x080000, CRC(58ad1a62) SHA1(1d2643b5f6eac22682972a88d284e00de3e3b223) )
3529	3687	ROM_LOAD( "rb-003.101", 0x080000, 0x080000, CRC(2cac25d7) SHA1(0412c317bf650a93051b9304d23035efde0c026a) )
3530	3688
3531		ROM_REGION( 0x200000, "oki2", 0 ) /* Samples */
3532		/* Upper 128kB of M6295 address region is bank-switched? */
3533		ROM_LOAD( "rb-001.u44", 0x000000, 0x100000, CRC(7cf774b3) SHA1(3fb0a5096ce9480f97e311439042eb8cbc26efb4) )
3534		ROM_LOAD( "rb-002.u45", 0x100000, 0x100000, CRC(e4b30444) SHA1(be6756dce3721226e0b7f5d4d168008c31aeea8e) )
	3689	/* OKI 2 */
	3690	ROM_LOAD( "rb-001.u44", 0x100000, 0x100000, CRC(7cf774b3) SHA1(3fb0a5096ce9480f97e311439042eb8cbc26efb4) )
	3691	ROM_LOAD( "rb-002.u45", 0x200000, 0x100000, CRC(e4b30444) SHA1(be6756dce3721226e0b7f5d4d168008c31aeea8e) )
	3692
	3693	/* Sound data is copied here during driver init */
	3694	ROM_REGION( 0x400000*16, "oki1", 0 )
	3695	ROM_FILL( 0x00000, 0x400000*16, 0x00 )
	3696
	3697	ROM_REGION( 0x400000*16, "oki2", 0 )
	3698	ROM_FILL( 0x00000, 0x400000*16, 0x00 )
3535	3699	ROM_END
3536	3700
3537	3701	/**********************************************************************
r5534	r5535
3636	3800	// MCU is a 78K series III type CPU
3637	3801	}
3638	3802
	3803	static DRIVER_INIT( brapboys )
	3804	{
	3805	/*
	3806	Expand the OKI sample data
	3807
	3808	OKI 1:
	3809	Address space 0x00000-0x2ffff is fixed
	3810	Address space 0x30000-0x3ffff is banked (13 banks)
	3811
	3812	OKI 2:
	3813	Address space 0x00000-0x1ffff is fixed
	3814	Address space 0x20000-0x3ffff is banked (15 banks)
	3815
	3816	The current sound device implementation can't handle
	3817	the banking dynamically so we have to expand all the bank
	3818	combinations here and use use okim6295_set_bank_base().
	3819	*/
	3820	int bank;
	3821	UINT8 *src = memory_region(machine, "samples");
	3822	UINT8 *dst1 = memory_region(machine, "oki1");
	3823	UINT8 *dst2 = memory_region(machine, "oki2");
	3824
	3825	/* OKI 1 */
	3826	for (bank = 0; bank < 13; ++bank)
	3827	{
	3828	UINT8 *dst;
	3829	UINT8 *srcn;
	3830
	3831	dst = dst1 + 0x40000 * bank;
	3832	srcn = src + 0x30000 + (0x10000 * bank);
	3833	memcpy(dst, src, 0x30000);
	3834	memcpy(dst + 0x30000, srcn, 0x10000);
	3835	}
	3836
	3837	/* OKI 2 */
	3838	for (bank = 0; bank < 15; ++bank)
	3839	{
	3840	UINT8 *dst;
	3841	UINT8 *srcn;
	3842	dst = dst2 + 0x40000 * bank;
	3843	srcn = src + 0x120000 + (0x20000 * bank);
	3844	memcpy(dst, src + 0x100000, 0x20000);
	3845	memcpy(dst + 0x20000, srcn, 0x20000);
	3846	}
	3847
	3848	DRIVER_INIT_CALL(calc3);
	3849	}
	3850
	3851
3639	3852	/***************************************************************************
3640	3853
3641	3854
r5534	r5535
3662	3875	GAME( 1995, gtmr2, 0, gtmr2, gtmr2, gtmr2, ROT0, "Kaneko", "Mille Miglia 2: Great 1000 Miles Rally (95/05/24)", 0 )
3663	3876	GAME( 1995, gtmr2a, gtmr2, gtmr2, gtmr2, gtmr2, ROT0, "Kaneko", "Mille Miglia 2: Great 1000 Miles Rally (95/04/04)", 0 )
3664	3877	GAME( 1995, gtmr2u, gtmr2, gtmr2, gtmr2, gtmr2, ROT0, "Kaneko", "Great 1000 Miles Rally 2 USA (95/05/18)", 0 )
	3878	// some functionality of the protection chip still needs investigating on these, but they seem to be playable
	3879	GAME( 1992, brapboys, 0, shogwarr, brapboys, brapboys, ROT0, "Kaneko", "B.Rap Boys (World)", 0 )
	3880	GAME( 1992, brapboysj,brapboys, shogwarr, brapboys, brapboys, ROT0, "Kaneko", "B.Rap Boys Special (Japan)", 0 )
3665	3881
3666	3882	/* Non-working games (mainly due to protection) */
3667	3883
3668	3884	GAME( 1992, shogwarr, 0, shogwarr, shogwarr, calc3, ROT0, "Kaneko", "Shogun Warriors", GAME_NOT_WORKING )
3669	3885	GAME( 1992, shogwarre,shogwarr, shogwarr, shogwarr, calc3, ROT0, "Kaneko", "Shogun Warriors (Euro)", GAME_NOT_WORKING )
3670	3886	GAME( 1992, fjbuster, shogwarr, shogwarr, shogwarr, calc3, ROT0, "Kaneko", "Fujiyama Buster (Japan)", GAME_NOT_WORKING )
3671		GAME( 1992, brapboys, 0, shogwarr, shogwarr, calc3, ROT0, "Kaneko", "B.Rap Boys (World)", GAME_NOT_WORKING )
3672		GAME( 1992, brapboysj,brapboys, shogwarr, shogwarr, calc3, ROT0, "Kaneko", "B.Rap Boys Special (Japan)", GAME_NOT_WORKING )
	3887

src/mame/drivers/ampoker2.c
r5534	r5535
876	876	PORT_DIPNAME( 0x08, 0x08, "Rate Table SW1" ) PORT_DIPLOCATION("SW1:3") /* DSW3 (should be arranged with DSW4) */
877	877	PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
878	878	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
879		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD2 )
	879	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD3 )
880	880
881	881	PORT_START("IN6")
882	882	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )

src/mame/drivers/pgm.c
r5534	r5535
44	44	120x - 2001 - Knights of Valor 2 Plus (9 Dragons?)
45	45	130x - 2001 - DoDonpachi II
46	46
47		0450x - 2002 - Demon Front
	47	0450x - 2002 - Demon Front (also known to be produced / sold in a single PCB version)
48	48
49	49	---
50	50

src/mame/drivers/megatech.c
r5534	r5535
65	65	Out Run 171-5783 837-6963-06 610-0239-06 MPR-11078 (Mask) EPR-12368-06 (27256) n/a
66	66	Alien Syndrome 171-5783 837-6963-07 610-0239-07 MPR-11194 (232011) EPR-12368-07 (27256) n/a
67	67	Afterburner 171-5784 837-6963-10 610-0239-10 315-5235 (custom) MPR-11271-T (834000) EPR-12368-10 (27256)
	68	Great Football 171-5783 837-6963-19 610-0239-19 MPR-10576F (831000) EPR-12368-19 (27256) n/a
	69	World Championship Soccer 171-5782 837-6963-21 610-0239-21 MPR-126078 (uPD23C4000) EPR-12607B (27256) n/a
68	70	Tetris 171-5834 837-6963-22 610-0239-22 MPR-12356F (831000) MPR-12357F (831000) EPR-12368-22 (27256)
69		World Championship Soccer 171-5782 837-6963-21 610-0239-21 MPR-126078 (uPD23C4000) EPR-12607B (27256) n/a
70	71	Ghouls & Ghosts 171-5869A - 610-0239-23 MPR-12605 (40 pins) MPR-12606 (40 pins) EPR-12368-23 (27256)
71	72	Super Hang On 171-5782 837-6963-24 610-0239-24 MPR-12640 (234000) EPR-12368-24 (27256) n/a
72	73	Forgotten Worlds 171-5782 837-6963-26 610-0239-26 MPR-12672-H (Mask) EPR-12368-26 (27256) n/a
r5534	r5535
684	685	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
685	686	ROM_LOAD16_WORD_SWAP( "mp12538.ic1", 0x000000, 0x080000, CRC(3bea3dce) SHA1(ec72e4fde191dedeb3f148f132603ed3c23f0f86) ) \
686	687	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
687		ROM_LOAD( "12368-01.ic2", 0x000000, 0x08000, CRC(40cb0088) SHA1(e1711532c29f395a35a1cb34d789015881b5a1ed) ) \
	688	ROM_LOAD( "epr-12368-01.ic2", 0x000000, 0x08000, CRC(40cb0088) SHA1(e1711532c29f395a35a1cb34d789015881b5a1ed) ) \
688	689
689	690	ROM_START( mt_beast ) /* Altered Beast */
690	691	MEGATECH_BIOS
r5534	r5535
696	697	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
697	698	ROM_LOAD16_WORD_SWAP( "mp11934.ic1", 0x000000, 0x080000, CRC(932daa09) SHA1(a2d7a76f3604c6227d43229908bfbd02b0ef5fd9) ) \
698	699	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
699		ROM_LOAD( "12368-02.ic2", 0x000000, 0x08000, CRC(c129c66c) SHA1(e7c0c97db9df9eb04e2f9ff561b64305219b8f1f) ) \
	700	ROM_LOAD( "epr-12368-02.ic2", 0x000000, 0x08000, CRC(c129c66c) SHA1(e7c0c97db9df9eb04e2f9ff561b64305219b8f1f) ) \
700	701
701	702	ROM_START( mt_shar2 ) /* Space Harrier 2 */
702	703	MEGATECH_BIOS
r5534	r5535
708	709	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
709	710	ROM_LOAD16_WORD_SWAP( "mp11996f.ic1", 0x000000, 0x080000, CRC(9355c34e) SHA1(26ff91c2921408673c644b0b1c8931d98524bf63) ) \
710	711	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
711		ROM_LOAD( "12368-03.ic2", 0x000000, 0x08000, CRC(1ba4ac5d) SHA1(9bde57d70189d159ebdc537a9026001abfd0deae) ) \
	712	ROM_LOAD( "epr-12368-03.ic2", 0x000000, 0x08000, CRC(1ba4ac5d) SHA1(9bde57d70189d159ebdc537a9026001abfd0deae) ) \
712	713
713	714	ROM_START( mt_stbld ) /* Super Thunder Blade */
714	715	MEGATECH_BIOS
r5534	r5535
720	721	ROM_REGION( 0x300000, GAME_REGION, 0 ) \
721	722	ROM_LOAD( "mp11129f.ic1", 0x000000, 0x020000, CRC(c6611c84) SHA1(eab0eed872dd26b13bcf0b2dd74fcbbc078812c9) ) \
722	723	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_SMS ) \
723		ROM_LOAD( "12368-04.ic2", 0x000000, 0x08000, CRC(62e5579b) SHA1(e1f531be5c40a1216d4192baeda9352384444410) ) \
	724	ROM_LOAD( "epr-12368-04.ic2", 0x000000, 0x08000, CRC(62e5579b) SHA1(e1f531be5c40a1216d4192baeda9352384444410) ) \
724	725	/* Also known to have the ID# MPR-11128 instead of MPR-11129F, same contents */
725	726
726	727	ROM_START( mt_ggolf ) /* Great Golf */
r5534	r5535
733	734	ROM_REGION( 0x300000, GAME_REGION, 0 ) \
734	735	ROM_LOAD( "mp10747f.ic1", 0x000000, 0x020000, BAD_DUMP CRC(9cf53703) SHA1(c6b4d1de56bd5bf067ec7fc80449c07686d01337) ) \
735	736	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_SMS ) \
736		ROM_LOAD( "12368-05.ic2", 0x000000, 0x08000, CRC(bab91fcc) SHA1(a160c9d34b253e93ac54fdcef33f95f44d8fa90c) ) \
	737	ROM_LOAD( "epr-12368-05.ic2", 0x000000, 0x08000, CRC(bab91fcc) SHA1(a160c9d34b253e93ac54fdcef33f95f44d8fa90c) ) \
737	738
738	739	ROM_START( mt_gsocr ) /* Great Soccer */
739	740	MEGATECH_BIOS
r5534	r5535
769	770	ROM_REGION( 0x300000, GAME_REGION, 0 ) \
770	771	ROM_LOAD( "mp11706.ic1", 0x000000, 0x040000, CRC(0C6FAC4E) SHA1(7C0778C055DC9C2B0AAE1D166DBDB4734E55B9D1) ) \
771	772	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_SMS ) \
772		ROM_LOAD( "12368-08.ic2", 0x000000, 0x08000, CRC(103A0459) SHA1(D803DDF7926B83785E8503C985B8C78E7CCB5DAC) ) \
	773	ROM_LOAD( "epr-12368-08.ic2", 0x000000, 0x08000, CRC(103A0459) SHA1(D803DDF7926B83785E8503C985B8C78E7CCB5DAC) ) \
773	774
774	775	ROM_START( mt_shnbi ) /* Shinobi */
775	776	MEGATECH_BIOS
r5534	r5535
781	782	ROM_REGION( 0x300000, GAME_REGION, 0 ) \
782	783	ROM_LOAD( "mp11271.ic1", 0x000000, 0x080000, CRC(1C951F8E) SHA1(51531DF038783C84640A0CAB93122E0B59E3B69A) ) \
783	784	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_SMS ) \
784		ROM_LOAD( "12368-10.ic2", 0x000000, 0x08000, CRC(2A7CB590) SHA1(2236963BDDC89CA9045B530259CC7B5CCF889EAF) ) \
	785	ROM_LOAD( "epr-12368-10.ic2", 0x000000, 0x08000, CRC(2A7CB590) SHA1(2236963BDDC89CA9045B530259CC7B5CCF889EAF) ) \
785	786
786	787	ROM_START( mt_aftrb ) /* Afterburner */
787	788	MEGATECH_BIOS
r5534	r5535
793	794	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
794	795	ROM_LOAD16_WORD_SWAP( "mp12559.ic1", 0x000000, 0x080000, CRC(b093bee3) SHA1(0bf6194c3d228425f8cf1903ed70d8da1b027b6a) ) \
795	796	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
796		ROM_LOAD( "12368-11.ic2", 0x000000, 0x08000, CRC(f4f27e8d) SHA1(ae1a2823deb416c53838115966f1833d5dac72d4) ) \
	797	ROM_LOAD( "epr-12368-11.ic2", 0x000000, 0x08000, CRC(f4f27e8d) SHA1(ae1a2823deb416c53838115966f1833d5dac72d4) ) \
797	798
798	799	ROM_START( mt_tfor2 ) /* Thunder Force 2 */
799	800	MEGATECH_BIOS
r5534	r5535
805	806	ROM_REGION( 0x300000, GAME_REGION, 0 ) \
806	807	ROM_LOAD( "ep13817.ic2", 0x000000, 0x20000, CRC(299cbb74) SHA1(901697a3535ad70190647f34ad5b30b695d54542) ) \
807	808	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_SMS ) \
808		ROM_LOAD( "12368-13.ic1", 0x000000, 0x08000, CRC(4038cbd1) SHA1(696bc1efce45d9f0052b2cf0332a232687c8d6ab) ) \
	809	ROM_LOAD( "epr-12368-13.ic1", 0x000000, 0x08000, CRC(4038cbd1) SHA1(696bc1efce45d9f0052b2cf0332a232687c8d6ab) ) \
809	810
810	811	ROM_START( mt_astro ) /* Astro Warrior */
811	812	MEGATECH_BIOS
812	813	MEGATECH_GAME13("game0", "inst0")
813	814	ROM_END
814	815
	816	/* Game 19 - Great Football (SMS) */
	817	#define MEGATECH_GAME19(GAME_REGION, INSTRUCTION_REGION) \
	818	ROM_REGION( 0x300000, GAME_REGION, 0 ) \
	819	ROM_LOAD( "mpr-10576f.ic1", 0x000000, 0x020000, CRC(2055825f) SHA1(a768f44ce7e50083ffe8c4b5e3ac93ceb7bd3266) ) \
	820	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_SMS ) \
	821	ROM_LOAD( "epr-12368-19.ic2", 0x000000, 0x08000, CRC(e27cb37a) SHA1(2b6259957e86d033a5689fd716a9efcfeff7d5ba) ) \
	822
	823	ROM_START( mt_gfoot ) /* Great Football */
	824	MEGATECH_BIOS
	825	MEGATECH_GAME19("game0", "inst0")
	826	ROM_END
	827
815	828	/* Game 20 - Last Battle */
816	829	#define MEGATECH_GAME20(GAME_REGION, INSTRUCTION_REGION) \
817	830	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
818	831	ROM_LOAD16_WORD_SWAP( "mp12578f.ic1", 0x000000, 0x080000, CRC(531191a0) SHA1(f6bc26e975c01a3e10ab4033e4c5f494627a1e2f) ) \
819	832	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
820		ROM_LOAD( "12368-20.ic2", 0x000000, 0x08000, CRC(e1a71c91) SHA1(c250da18660d8aea86eb2abace41ba46130dabc8) ) \
	833	ROM_LOAD( "epr-12368-20.ic2", 0x000000, 0x08000, CRC(e1a71c91) SHA1(c250da18660d8aea86eb2abace41ba46130dabc8) ) \
821	834
822	835	ROM_START( mt_lastb ) /* Last Battle */
823	836	MEGATECH_BIOS
r5534	r5535
829	842	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
830	843	ROM_LOAD16_WORD_SWAP( "mp12607b.ic1", 0x000000, 0x080000, CRC(bc591b30) SHA1(55e8577171c0933eee53af1dabd0f4c6462d5fc8) ) \
831	844	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
832		ROM_LOAD( "12368-21.ic2", 0x000000, 0x08000, CRC(028ee46b) SHA1(cd8f81d66e5ae62107eb20e0ca5db4b66d4b2987) ) \
	845	ROM_LOAD( "epr-12368-21.ic2", 0x000000, 0x08000, CRC(028ee46b) SHA1(cd8f81d66e5ae62107eb20e0ca5db4b66d4b2987) ) \
833	846
834	847	ROM_START( mt_wcsoc ) /* World Championship Soccer */
835	848	MEGATECH_BIOS
r5534	r5535
842	855	ROM_LOAD16_BYTE( "mpr-12356f.ic1", 0x000001, 0x020000, CRC(1e71c1a0) SHA1(44b2312792e49d46d71e0417a7f022e5ffddbbfe) ) \
843	856	ROM_LOAD16_BYTE( "mpr-12357f.ic2", 0x000000, 0x020000, CRC(d52ca49c) SHA1(a9159892eee2c0cf28ebfcfa99f81f80781851c6) ) \
844	857	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
845		ROM_LOAD( "12368-22.ic3", 0x000000, 0x08000, CRC(1c1b6468) SHA1(568a38f4186167486e39ab4aa2c1ceffd0b81156) ) \
	858	ROM_LOAD( "epr-12368-22.ic3", 0x000000, 0x08000, CRC(1c1b6468) SHA1(568a38f4186167486e39ab4aa2c1ceffd0b81156) ) \
846	859
847	860	ROM_START( mt_tetri ) /* Tetris */
848	861	MEGATECH_BIOS
r5534	r5535
856	869	ROM_LOAD16_WORD_SWAP( "mpr12606.ic2", 0x080000, 0x020000, CRC(D0BE7777) SHA1(A44B2A3D427F6973B5C1A3DCD8D1776366ACB9F7) ) \
857	870	ROM_CONTINUE(0x020000,0x60000) \
858	871	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
859		ROM_LOAD( "12368-23.ic3", 0x000000, 0x08000, CRC(7ee58546) SHA1(ad5bb0934475eacdc5e354f67c96fe0d2512d33b) ) \
	872	ROM_LOAD( "epr-12368-23.ic3", 0x000000, 0x08000, CRC(7ee58546) SHA1(ad5bb0934475eacdc5e354f67c96fe0d2512d33b) ) \
860	873
861	874	ROM_START( mt_gng ) /* Ghouls and Ghosts */
862	875	MEGATECH_BIOS
r5534	r5535
880	893	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
881	894	ROM_LOAD16_WORD_SWAP( "12806.ic1", 0x000000, 0x080000, CRC(43456820) SHA1(2f7f1fcd979969ac99426f11ab99999a5494a121) ) \
882	895	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
883		ROM_LOAD( "12368-25.ic2", 0x000000, 0x08000, CRC(1f07ed28) SHA1(9d54192f4c6c1f8a51c38a835c1dd1e4e3e8279e) ) \
	896	ROM_LOAD( "epr-12368-25.ic2", 0x000000, 0x08000, CRC(1f07ed28) SHA1(9d54192f4c6c1f8a51c38a835c1dd1e4e3e8279e) ) \
884	897
885	898	ROM_START( mt_gaxe ) /* Golden Axe */
886	899	MEGATECH_BIOS
r5534	r5535
905	918	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
906	919	ROM_LOAD16_WORD_SWAP( "mp12707.1", 0x000000, 0x080000, CRC(4f2c513d) SHA1(f9bb548b3688170fe18bb3f1b5b54182354143cf) ) \
907	920	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
908		ROM_LOAD( "12368-27.ic2", 0x000000, 0x08000, CRC(caf46f78) SHA1(a9659e86a6a223646338cd8f29c346866e4406c7) ) \
	921	ROM_LOAD( "epr-12368-27.ic2", 0x000000, 0x08000, CRC(caf46f78) SHA1(a9659e86a6a223646338cd8f29c346866e4406c7) ) \
909	922
910	923	ROM_START( mt_mystd ) /* Mystic Defender */
911	924	MEGATECH_BIOS
r5534	r5535
917	930	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
918	931	ROM_LOAD16_WORD_SWAP( "mp12675.ic1", 0x000000, 0x080000, CRC(672A1D4D) SHA1(5FD0AF14C8F2CF8CEAB1AE61A5A19276D861289A) ) \
919	932	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
920		ROM_LOAD( "12368-28.ic2", 0x000000, 0x08000, CRC(0D30BEDE) SHA1(73A090D84B78A570E02FB54A33666DCADA52849B) ) \
	933	ROM_LOAD( "epr-12368-28.ic2", 0x000000, 0x08000, CRC(0D30BEDE) SHA1(73A090D84B78A570E02FB54A33666DCADA52849B) ) \
921	934
922	935	ROM_START( mt_revsh ) /* The Revenge Of Shinobi */
923	936	MEGATECH_BIOS
r5534	r5535
929	942	ROM_REGION( 0x300000, GAME_REGION, 0 ) \
930	943	ROM_LOAD( "mp11404.ic1", 0x000000, 0x020000, CRC(E030E66C) SHA1(06664DAF208F07CB00B603B12ECCFC3F01213A17) ) \
931	944	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_SMS ) \
932		ROM_LOAD( "12368-29.ic2", 0x000000, 0x08000, CRC(534151e8) SHA1(219238d90c1d3ac07ff64c9a2098b490fff68f04) ) \
	945	ROM_LOAD( "epr-12368-29.ic2", 0x000000, 0x08000, CRC(534151e8) SHA1(219238d90c1d3ac07ff64c9a2098b490fff68f04) ) \
933	946
934	947	ROM_START( mt_parlg ) /* Parlour Games */
935	948	MEGATECH_BIOS
r5534	r5535
941	954	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
942	955	ROM_LOAD16_WORD_SWAP( "mp12645f.ic1", 0x000000, 0x080000, CRC(c07ef8d2) SHA1(9d111fdc7bb92d52bfa048cd134aa488b4f475ef) ) \
943	956	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
944		ROM_LOAD( "12368-31.ic2", 0x000000, 0x08000, CRC(30af7e4a) SHA1(baf91d527393dc90aba9371abcb1e690bcc83c7e) ) \
	957	ROM_LOAD( "epr-12368-31.ic2", 0x000000, 0x08000, CRC(30af7e4a) SHA1(baf91d527393dc90aba9371abcb1e690bcc83c7e) ) \
945	958
946	959	ROM_START( mt_tgolf ) /* Arnold Palmer Tournament Golf */
947	960	MEGATECH_BIOS
r5534	r5535
966	979	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
967	980	ROM_LOAD16_WORD_SWAP( "mp12706.ic1", 0x000000, 0x080000, CRC(8901214f) SHA1(f5ec166be1cf9b86623b9d7a78ec903b899da32a) ) \
968	981	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
969		ROM_LOAD( "12368-35.ic2", 0x000000, 0x08000, CRC(67bbe482) SHA1(6fc283b22e68befabb44b2cc61a7f82a71d6f029) ) \
	982	ROM_LOAD( "epr-12368-35.ic2", 0x000000, 0x08000, CRC(67bbe482) SHA1(6fc283b22e68befabb44b2cc61a7f82a71d6f029) ) \
970	983
971	984	ROM_START( mt_tlbba ) /* Tommy Lasorda Baseball */
972	985	MEGATECH_BIOS
r5534	r5535
978	991	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
979	992	ROM_LOAD16_WORD_SWAP( "mp13193-t.ic1", 0x000000, 0x080000, CRC(8c770e2f) SHA1(02a3626025c511250a3f8fb3176eebccc646cda9) ) \
980	993	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
981		ROM_LOAD( "ep12368-36.ic3", 0x000000, 0x08000, CRC(a4b29bac) SHA1(c9be866ac96243897d09612fe17562e0481f66e3) ) \
	994	ROM_LOAD( "epr-12368-36.ic3", 0x000000, 0x08000, CRC(a4b29bac) SHA1(c9be866ac96243897d09612fe17562e0481f66e3) ) \
982	995
983	996	ROM_START( mt_cols ) /* Columns */
984	997	MEGATECH_BIOS
r5534	r5535
990	1003	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
991	1004	ROM_LOAD16_WORD_SWAP( "mp13192-h.ic1", 0x000000, 0x080000, CRC(82f458ef) SHA1(58444b783312def71ecffc4ad021b72a609685cb) ) \
992	1005	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
993		ROM_LOAD( "12368-38.ic2", 0x000000, 0x08000, CRC(43c5529b) SHA1(104f85adea6da1612c0aa96d553efcaa387d7aaf) ) \
	1006	ROM_LOAD( "epr-12368-38.ic2", 0x000000, 0x08000, CRC(43c5529b) SHA1(104f85adea6da1612c0aa96d553efcaa387d7aaf) ) \
994	1007
995	1008	ROM_START( mt_eswat ) /* ESWAT */
996	1009	MEGATECH_BIOS
r5534	r5535
1002	1015	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1003	1016	ROM_LOAD16_WORD_SWAP( "13250.ic1", 0x000000, 0x080000, CRC(189b885f) SHA1(31c06ffcb48b1604989a94e584261457de4f1f46) ) \
1004	1017	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1005		ROM_LOAD( "12368-39.ic2", 0x000000, 0x08000, CRC(64b3ce25) SHA1(83a9f2432d146a712b037f96f261742f7dc810bb) ) \
	1018	ROM_LOAD( "epr-12368-39.ic2", 0x000000, 0x08000, CRC(64b3ce25) SHA1(83a9f2432d146a712b037f96f261742f7dc810bb) ) \
1006	1019
1007	1020	ROM_START( mt_smgp ) /* Super Monaco Grand Prix */
1008	1021	MEGATECH_BIOS
r5534	r5535
1014	1027	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1015	1028	ROM_LOAD16_WORD_SWAP( "mp13285a.ic1", 0x000000, 0x080000, CRC(189516e4) SHA1(2a79e07da2e831832b8d448cae87a833c85e67c9) ) \
1016	1029	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1017		ROM_LOAD( "12368-40.ic2", 0x000000, 0x08000, CRC(0482378c) SHA1(734772f3ddb5ff82b76c3514d18a464b2bce8381) ) \
	1030	ROM_LOAD( "epr-12368-40.ic2", 0x000000, 0x08000, CRC(0482378c) SHA1(734772f3ddb5ff82b76c3514d18a464b2bce8381) ) \
1018	1031
1019	1032	ROM_START( mt_mwalk ) /* Moon Walker */
1020	1033	MEGATECH_BIOS
r5534	r5535
1026	1039	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1027	1040	ROM_LOAD16_WORD_SWAP( "mp13578a-s.ic1", 0x000000, 0x080000, CRC(23f19893) SHA1(09aca793871e2246af4dc24925bc1eda8ff34446) ) \
1028	1041	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1029		ROM_LOAD( "ep12368-41.ic2", 0x000000, 0x08000, CRC(3014acec) SHA1(07953e9ae5c23fc7e7d08993b215f4dfa88aa5d7) ) \
	1042	ROM_LOAD( "epr-12368-41.ic2", 0x000000, 0x08000, CRC(3014acec) SHA1(07953e9ae5c23fc7e7d08993b215f4dfa88aa5d7) ) \
1030	1043
1031	1044	ROM_START( mt_crack ) /* Crackdown */
1032	1045	MEGATECH_BIOS
r5534	r5535
1050	1063	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1051	1064	ROM_LOAD16_WORD_SWAP( "mpr13396h.ic1", 0x000000, 0x080000, CRC(091226e3) SHA1(cb15c6277314f3c4a86b5ae5823f72811d5d269d) ) \
1052	1065	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1053		ROM_LOAD( "epr12368-44.ic2", 0x000000, 0x08000, CRC(e653065d) SHA1(96b014fc4df8eb2188ac94ed0a778d974fe6dcad) ) \
	1066	ROM_LOAD( "epr-12368-44.ic2", 0x000000, 0x08000, CRC(e653065d) SHA1(96b014fc4df8eb2188ac94ed0a778d974fe6dcad) ) \
1054	1067
1055	1068	ROM_START( mt_arrow ) /* Arrow Flash */
1056	1069	MEGATECH_BIOS
r5534	r5535
1062	1075	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1063	1076	ROM_LOAD16_WORD_SWAP( "mp13941.ic1", 0x000000, 0x080000, CRC(D71B3EE6) SHA1(05F272DAD243D132D517C303388248DC4C0482ED) ) \
1064	1077	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1065		ROM_LOAD( "12368-47.ic2", 0x000000, 0x08000, CRC(31FB683D) SHA1(E356DA020BBF817B97FB10C27F75CF5931EDF4FC) ) \
	1078	ROM_LOAD( "epr-12368-47.ic2", 0x000000, 0x08000, CRC(31FB683D) SHA1(E356DA020BBF817B97FB10C27F75CF5931EDF4FC) ) \
1066	1079
1067	1080	ROM_START( mt_astrm ) /* Alien Storm */
1068	1081	MEGATECH_BIOS
r5534	r5535
1074	1087	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1075	1088	ROM_LOAD16_WORD_SWAP( "mpr-14025-f.ic1", 0x000000, 0x080000, CRC(26e899fe) SHA1(6d28e154ae2e4196097a2aa96c5acd5dfe7e3d2b) ) \
1076	1089	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1077		ROM_LOAD( "12368-48.ic2", 0x000000, 0x08000, CRC(25817bc2) SHA1(ba1bbb952aff12fb4d3ecfb10d82c54128439395) ) \
	1090	ROM_LOAD( "epr-12368-48.ic2", 0x000000, 0x08000, CRC(25817bc2) SHA1(ba1bbb952aff12fb4d3ecfb10d82c54128439395) ) \
1078	1091
1079	1092	ROM_START( mt_wwar ) /* Wrestle War */
1080	1093	MEGATECH_BIOS
r5534	r5535
1086	1099	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1087	1100	ROM_LOAD16_WORD_SWAP( "mp13905a.ic1", 0x000000, 0x100000, CRC(68a88d60) SHA1(2f56e8a2b0999de4fa0d14a1527f4e1df0f9c7a2) ) \
1088	1101	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1089		ROM_LOAD( "12368-49.ic2", 0x000000, 0x08000, CRC(c5101da2) SHA1(636f30043e2e9291e193ef9a2ead2e97a0bf7380) ) \
	1102	ROM_LOAD( "epr-12368-49.ic2", 0x000000, 0x08000, CRC(c5101da2) SHA1(636f30043e2e9291e193ef9a2ead2e97a0bf7380) ) \
1090	1103
1091	1104	ROM_START( mt_bbros ) /* Bonanza Bros. */
1092	1105	MEGATECH_BIOS
r5534	r5535
1110	1123	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1111	1124	ROM_LOAD16_WORD_SWAP( "mp13913.ic1", 0x000000, 0x080000, CRC(480b4b5c) SHA1(ab1dc1f738e3b2d0898a314b123fa71182bf572e) ) \
1112	1125	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1113		ROM_LOAD( "12368-52.ic2", 0x0000, 0x8000, CRC(6a69d20c) SHA1(e483b39ff6eca37dc192dc296d004049e220554a) ) \
	1126	ROM_LOAD( "epr-12368-52.ic2", 0x0000, 0x8000, CRC(6a69d20c) SHA1(e483b39ff6eca37dc192dc296d004049e220554a) ) \
1114	1127
1115	1128	ROM_START( mt_sonic ) /* Sonic The Hedgehog */
1116	1129	MEGATECH_BIOS
r5534	r5535
1121	1134	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1122	1135	ROM_LOAD16_WORD_SWAP( "mp13933.ic1", 0x000000, 0x080000, CRC(13775004) SHA1(5decfd35944a2d0e7b996b9a4a12b616a309fd5e) ) \
1123	1136	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1124		ROM_LOAD( "12368-52.ic2", 0x0000, 0x8000, CRC(6a69d20c) SHA1(e483b39ff6eca37dc192dc296d004049e220554a) ) \
	1137	ROM_LOAD( "epr-12368-52.ic2", 0x0000, 0x8000, CRC(6a69d20c) SHA1(e483b39ff6eca37dc192dc296d004049e220554a) ) \
1125	1138
1126	1139	ROM_START( mt_sonia ) /* Sonic (alt)*/
1127	1140	MEGATECH_BIOS
r5534	r5535
1133	1146	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1134	1147	ROM_LOAD16_WORD_SWAP( "mp14341.ic1", 0x000000, 0x080000, CRC(04d65ebc) SHA1(24338aecdc52b6f416548be722ca475c83dbae96) ) \
1135	1148	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1136		ROM_LOAD( "12368-53.ic2", 0x000000, 0x08000, CRC(4fa61044) SHA1(7810deea221c10b0b2f5233443d81f4f1998ee58) ) \
	1149	ROM_LOAD( "epr-12368-53.ic2", 0x000000, 0x08000, CRC(4fa61044) SHA1(7810deea221c10b0b2f5233443d81f4f1998ee58) ) \
1137	1150
1138	1151	/* alt version with these roms exists, but the content is the same */
1139	1152	/* (6a221fd6) ep14706.ic1 mp14341.ic1 [even] IDENTICAL */
r5534	r5535
1149	1162	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1150	1163	ROM_LOAD16_WORD_SWAP( "mp14272.ic1", 0x000000, 0x080000, CRC(d4784cae) SHA1(b6c286027d06fd850016a2a1ee1f1aeea080c3bb) ) \
1151	1164	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1152		ROM_LOAD( "12368-57.ic2", 0x000000, 0x08000, CRC(dc9b4433) SHA1(efd3a598569010cdc4bf38ecbf9ed1b4e14ffe36) ) \
	1165	ROM_LOAD( "epr-12368-57.ic2", 0x000000, 0x08000, CRC(dc9b4433) SHA1(efd3a598569010cdc4bf38ecbf9ed1b4e14ffe36) ) \
1153	1166
1154	1167	ROM_START( mt_gaxe2 ) /* Golden Axe 2 */
1155	1168	MEGATECH_BIOS
r5534	r5535
1161	1174	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1162	1175	ROM_LOAD16_WORD_SWAP( "mp14356a-f.ic1", 0x000000, 0x100000, CRC(20cf32f6) SHA1(752314346a7a98b3808b3814609e024dc0a4108c) ) \
1163	1176	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1164		ROM_LOAD( "ep12368-58.ic2", 0x000000, 0x08000, CRC(dce2708e) SHA1(fcebb1899ee11468f6bda705899f074e7de9d723) ) \
	1177	ROM_LOAD( "epr-12368-58.ic2", 0x000000, 0x08000, CRC(dce2708e) SHA1(fcebb1899ee11468f6bda705899f074e7de9d723) ) \
1165	1178
1166	1179	ROM_START( mt_stf ) /* Sports Talk Football */
1167	1180	MEGATECH_BIOS
r5534	r5535
1185	1198	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1186	1199	ROM_LOAD16_WORD_SWAP( "mp14557.ic1", 0x000000, 0x100000, CRC(e1a889a4) SHA1(a2768eacafc47d371e5276f0cce4b12b6041337a) ) \
1187	1200	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1188		ROM_LOAD( "12368-60.ic2", 0x000000, 0x08000, CRC(a8e4af18) SHA1(dfa49f6ec4047718f33dba1180f6204dbaff884c) ) \
	1201	ROM_LOAD( "epr-12368-60.ic2", 0x000000, 0x08000, CRC(a8e4af18) SHA1(dfa49f6ec4047718f33dba1180f6204dbaff884c) ) \
1189	1202
1190	1203	ROM_START( mt_kcham ) /* Kid Chameleon */
1191	1204	MEGATECH_BIOS
r5534	r5535
1197	1210	ROM_REGION16_BE( 0x300000, GAME_REGION, 0 ) \
1198	1211	ROM_LOAD16_WORD_SWAP( "mp15000a-f.ic1", 0x000000, 0x100000, CRC(679ebb49) SHA1(557482064677702454562f753460993067ef9e16) ) \
1199	1212	MEGATECH_INSTRUCTION_REGION( INSTRUCTION_REGION, MEGATECH_GAME_IS_GEN ) \
1200		ROM_LOAD( "ep12368-62.ic2", 0x000000, 0x08000, CRC(14a8566f) SHA1(d1d14162144bf068ddd19e9736477ff98fb43f9e) ) \
	1213	ROM_LOAD( "epr-12368-62.ic2", 0x000000, 0x08000, CRC(14a8566f) SHA1(d1d14162144bf068ddd19e9736477ff98fb43f9e) ) \
1201	1214
1202	1215	ROM_START( mt_soni2 ) /* Sonic The Hedgehog 2 */
1203	1216	MEGATECH_BIOS
r5534	r5535
1252	1265	/* 16 */ // unknown
1253	1266	/* 17 */ // unknown
1254	1267	/* 18 */ // unknown
1255		/* 19 */ // ~~unkn~~own
	1268	/* 19 / GAME( 1987, mt_gfoot, megatech, megatech, megatech, mtnew, ROT0, "Sega", "Great Football (Mega-Tech, SMS based)", GAME_NOT_WORKING ) / sms! */
1256	1269	/* 20 */ GAME( 1989, mt_lastb, megatech, megatech, megatech, mtnew, ROT0, "Sega", "Last Battle (Mega-Tech)", GAME_NOT_WORKING )
1257	1270	/* 21 */ GAME( 1989, mt_wcsoc, megatech, megatech, megatech, mtnew, ROT0, "Sega", "World Championship Soccer (Mega-Tech)", GAME_NOT_WORKING )
1258	1271	/* 22 */ GAME( 1989, mt_tetri, megatech, megatech, megatech, mtnew, ROT0, "Sega", "Tetris (Mega-Tech)", GAME_NOT_WORKING )
r5534	r5535
1295	1308	/* 58 */ GAME( 1991, mt_stf, megatech, megatech, megatech, mtnew, ROT0, "Sega", "Joe Montana II: Sports Talk Football (Mega-Tech)", GAME_NOT_WORKING )
1296	1309	/* 59 */ GAME( 1991, mt_mlh, megatech, megatech, megatech, mtnew, ROT0, "Sega", "Mario Lemieux Hockey (Mega-Tech)", GAME_NOT_WORKING )
1297	1310	/* 60 */ GAME( 1992, mt_kcham, megatech, megatech, megatech, mtnew, ROT0, "Sega", "Kid Chameleon (Mega-Tech)", GAME_NOT_WORKING )
1298		/* 61 */ // u~~nkn~~own
	1311	/* 61 */ // Turbo Outrun
1299	1312	/* 62 */ GAME( 1992, mt_soni2, megatech, megatech, megatech, mtnew, ROT0, "Sega", "Sonic The Hedgehog 2 (Mega-Tech)", GAME_NOT_WORKING )
1300	1313
1301	1314	/* more? */

src/mame/drivers/dwarfd.c
r5534	r5535
529	529	return 0;
530	530	}
531	531
532		static ~~void~~ dwarfd_sod_callback~~(const~~ ~~device_config *device, int nSO~~)
	532	static WRITE_LINE_DEVICE_HANDLER( dwarfd_sod_callback )
533	533	{
534		crt_access=~~nSO~~;
	534	crt_access = state;
535	535	}
536	536
537	537
538		static ~~const i~~8085_~~config~~ dwarfd_i8085_config =
	538	static I8085_CONFIG( dwarfd_i8085_config )
539	539	{
540		NULL, /* INTE changed callback */
541		NULL, /* STATUS changed callback */
542		dwarfd_sod_callback, /* SOD changed callback (8085A only) */
543		NULL /* SID changed callback (8085A only) */
	540	DEVCB_NULL, /* STATUS changed callback */
	541	DEVCB_NULL, /* INTE changed callback */
	542	DEVCB_NULL, /* SID changed callback (8085A only) */
	543	DEVCB_LINE(dwarfd_sod_callback) /* SOD changed callback (8085A only) */
544	544	};
545	545
546	546

src/mame/drivers/m79amb.c
r5534	r5535
48	48	8002 Sound Control (According to Manual)
49	49	8003 D0=SelfTest LED
50	50
	51
	52	The cabinet has backdrop artwork, a lightbulb for explosions,
	53	and two large (paddles pretending to be) guns.
	54
51	55	*/
52	56
53	57	#include "driver.h"
r5534	r5535
89	93	}
90	94
91	95
92		static const int ControllerTable[32] = {
93		0 , 1 , 3 , 2 , 6 , 7 , 5 , 4 ,
94		12 , 13 , 15 , 14 , 10 , 11 , 9 , 8 ,
95		24 , 25 , 27 , 26 , 30 , 31 , 29 , 28 ,
96		20 , 21 , 23 , 22 , 18 , 19 , 17 , 16
	96	/* grenade trajectory per gun position is inconsistent and sloppy in the game:
	97	0, 1, 3, 2, 6, 7, 5, 4 - gun position
	98	90.00, 90.00, 90.00, 90.00, 86.42, 86.42, 86.42, 86.42 - grenade trajectory (angle, est)
	99	18.0, 18.0, 18.0, 18.0, 27.2, 27.2, 27.2, 31.2 - crosses with y=28 (x, est)
	100
	101	12, 13, 15, 14, 10, 11, 9, 8,
	102	84.39, 84.39, 84.39, 80.87, 79.00, 80.87, 79.00, 79.00
	103	41.9, 48.9, 56.8, 75.8, 87.2, 88.8, 101.6, 107.6
	104
	105	24, 25, 27, 26, 30, 31, 29, 28,
	106	79.00, 79.00, 75.59, 75.59, 75.59, 73.72, 73.72, 73.72
	107	114.1, 121.5, 138.8, 146.0, 152.7, 162.6, 167.6, 172.7
	108
	109	20, 21, 23, 22, 18, 19, 17, 16
	110	73.72, 70.08, 70.08, 70.08, 67.97, 67.97, 64.34, 64.34
	111	181.6, 199.9, 205.4, 211.9, 223.5, 232.4, 254.0, 254.0
	112	*/
	113	static const UINT8 lut_cross[0x20] = {
	114	19, 20, 21, 23, 25, 27, 29, 37,
	115	45, 53, 66, 82, 88, 95, 105, 111,
	116	118, 130, 142, 149, 158, 165, 170, 177,
	117	191, 203, 209, 218, 228, 243, 249, 255,
97	118	};
	119	static const UINT8 lut_pos[0x20] = {
	120	0x1f, 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b,
	121	0x13, 0x12, 0x10, 0x11, 0x15, 0x14, 0x16, 0x17,
	122	0x07, 0x06, 0x04, 0x05, 0x01, 0x00, 0x02, 0x03,
	123	0x0b, 0x0a, 0x08, 0x09, 0x0d, 0x0c, 0x0e, 0x0f
	124	};
98	125
	126	static UINT8 lut_gun1[0x100];
	127	static UINT8 lut_gun2[0x100];
	128
99	129	static READ8_HANDLER( gray5bit_controller0_r )
100	130	{
101		int port_data = input_port_read(space->machine, "8004");
102		return (port_data & 0xe0) \| (~ControllerTable[port_data & 0x1f] & 0x1f);
	131	UINT8 port_data = input_port_read(space->machine, "8004");
	132	UINT8 gun_pos = input_port_read(space->machine, "GUN1");
	133	return (port_data & 0xe0) \| lut_gun1[gun_pos];
103	134	}
104	135
105	136	static READ8_HANDLER( gray5bit_controller1_r )
106	137	{
107		int port_data = input_port_read(space->machine, "8005");
108		return (port_data & 0xe0) \| (~ControllerTable[port_data & 0x1f] & 0x1f);
	138	UINT8 port_data = input_port_read(space->machine, "8005");
	139	UINT8 gun_pos = input_port_read(space->machine, "GUN2");
	140	return (port_data & 0xe0) \| lut_gun2[gun_pos];
109	141	}
110	142
111	143	static WRITE8_HANDLER( m79amb_8002_w )
r5534	r5535
118	150	static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 8 )
119	151	AM_RANGE(0x0000, 0x1fff) AM_ROM
120	152	AM_RANGE(0x4000, 0x5fff) AM_RAM_WRITE(ramtek_videoram_w) AM_BASE(&ramtek_videoram)
121		AM_RANGE(0x6000, 0x63ff) AM_RAM /* ?? */
	153	AM_RANGE(0x6000, 0x63ff) AM_RAM /* ?? */
122	154	AM_RANGE(0x8000, 0x8000) AM_READ_PORT("8000") AM_DEVWRITE("discrete", m79amb_8000_w)
123	155	AM_RANGE(0x8001, 0x8001) AM_WRITE(SMH_RAM) AM_BASE(&mask)
124	156	AM_RANGE(0x8002, 0x8002) AM_READ_PORT("8002") AM_WRITE(m79amb_8002_w)
r5534	r5535
161	193	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
162	194
163	195	PORT_START("8004")
164		PORT_BIT( 0x1f, ~~0x10,~~ IPT_PA~~DDLE ) POR~~T_MI~~NMAX(0,0x1f) PORT_SENSITI~~V~~ITY(25) PORT_K~~E~~YDE~~L~~TA(10)~~ PORT_CENTERD~~ELTA(0~~)
	196	PORT_BIT( 0x1f, IP_ACTIVE_LOW, IPT_UNUSED ) // gun 1 here
165	197	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 )
166	198	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
167	199	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
168	200
169	201	PORT_START("8005")
170		PORT_BIT( 0x1f, ~~0x10,~~ IPT_PA~~DDLE ) POR~~T_MI~~NMAX(0,0x1f) PORT_SENSITI~~V~~ITY(25) PORT_K~~E~~YDE~~L~~TA(10)~~ PORT_CENTERD~~ELTA(0~~) ~~PORT_PLAYER(~~2)
	202	PORT_BIT( 0x1f, IP_ACTIVE_LOW, IPT_UNUSED ) // gun 2 here
171	203	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
172	204	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
173	205	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	206
	207	// fake ports for the guns
	208	PORT_START("GUN1")
	209	PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_CROSSHAIR(X, (1.0-(19.0/256.0)), 19.0/256.0, 30.0/224.0) PORT_MINMAX(19,255) PORT_SENSITIVITY(50) PORT_KEYDELTA(5) PORT_CENTERDELTA(0) PORT_PLAYER(1)
	210
	211	PORT_START("GUN2")
	212	PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_CROSSHAIR(X, (1.0-(22.0/256.0)), 0.0, 30.0/224.0) PORT_MINMAX(0,234) PORT_SENSITIVITY(50) PORT_KEYDELTA(5) PORT_CENTERDELTA(0) PORT_PLAYER(2)
174	213	INPUT_PORTS_END
175	214
176	215
r5534	r5535
182	221	static DRIVER_INIT( m79amb )
183	222	{
184	223	UINT8 *rom = memory_region(machine, "maincpu");
185		int i;
	224	int i,j;
186	225
187	226	/* PROM data is active low */
188	227	for (i = 0;i < 0x2000;i++)
189	228	rom[i] = ~rom[i];
	229
	230	/* gun positions */
	231	for (i=0;i<0x100;i++) {
	232	/* gun 1, start at left 18 */
	233	for (j=0;j<0x20;j++) {
	234	if (i<=lut_cross[j]) {
	235	lut_gun1[i]=lut_pos[j];
	236	break;
	237	}
	238	}
	239
	240	/* gun 2, start at right 235 */
	241	for (j=0;j<0x20;j++) {
	242	if (i>=(253-lut_cross[j])) {
	243	lut_gun2[i]=lut_pos[j];
	244	break;
	245	}
	246	}
	247	}
190	248	}
191	249
192	250	static MACHINE_DRIVER_START( m79amb )

src/mame/drivers/meritm.c
r5534	r5535
10	10	Other: 2 Z80APIO (I/O and interrupt controllers)
11	11	1 8255 (I/O)
12	12
13		CRT 252: addon board for CRT 250, stores question roms
	13	CRT 256: addon board for CRT 250, stores question roms (aka Memory Expansion board)
14	14
15	15	CRT 258: addon board for CRT 250, contains UART and Microtouch touch screen controller
16	16
r5534	r5535
34	34	Pit Boss Superstar (c)1990
35	35	*Pit Boss Superstar 30 (c)1993
36	36	Pit Boss Megastar (c)1994
37		*Pit Boss Supertouch 30 (c)1993/4
	37	Pit Boss Supertouch 30 (c)1993/4
38	38
39	39	CRT 260:
40	40	*Megatouch Video (c)1994?
r5534	r5535
694	694	PORT_INCLUDE(meritm_crt250)
695	695
696	696	PORT_MODIFY("DSW")
697		PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unknown ) )
	697	PORT_DIPUNUSED_DIPLOC( 0x01, 0x00, "SW1:1" ) /* Unused */
	698	PORT_DIPNAME( 0x02, 0x02, "Solitaire Timer Mode" ) PORT_DIPLOCATION("SW1:2")
698	699	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
699		PORT_DIPSETTING( 0x01, DEF_STR( On ) )
700		PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
701		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
702	700	PORT_DIPSETTING( 0x02, DEF_STR( On ) )
703		PORT_DIPNAME( 0x04, 0x00, ~~DEF_~~STR( ~~Unknown~~ ) )
	701	PORT_DIPNAME( 0x04, 0x04, "Sex Trivia" ) PORT_DIPLOCATION("SW1:3")
704	702	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
705	703	PORT_DIPSETTING( 0x04, DEF_STR( On ) )
706		PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
707		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
708		PORT_DIPSETTING( 0x08, DEF_STR( On ) )
709		PORT_DIPNAME( 0x10, 0x10, "Run 21 and Trivia Whiz 2000: Coins to start" )
	704	PORT_DIPNAME( 0x08, 0x00, "Coin Limit" ) PORT_DIPLOCATION("SW1:4")
	705	PORT_DIPSETTING( 0x00, "No Coin Limit" )
	706	PORT_DIPSETTING( 0x08, "4 Coin Limit" ) /* With Lockout coil */
	707	PORT_DIPNAME( 0x10, 0x10, "Run 21 and Trivia Whiz 2000: Coins to start" ) PORT_DIPLOCATION("SW1:5")
710	708	PORT_DIPSETTING( 0x00, "2 Coins" )
711	709	PORT_DIPSETTING( 0x10, "1 Coin" )
712		PORT_DIPNAME( 0x20, 0x20, "Great Solitaire: Coins to start" )
713		PORT_DIPSETTING( 0x00, "4 Coins" )
714		PORT_DIPSETTING( 0x20, "2 Coins" )
715		PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
	710	PORT_DIPNAME( 0x20, 0x20, "Great Solitaire: Coins to start" ) PORT_DIPLOCATION("SW1:6")
	711	PORT_DIPSETTING( 0x00, "2 Coins" )
	712	PORT_DIPSETTING( 0x20, "1 Coin" )
	713	PORT_DIPNAME( 0x40, 0x00, "Sync Adjustment (Set by factory)" ) PORT_DIPLOCATION("SW1:7") /* Sync Adjustment (Set by factory) */
716	714	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
717	715	PORT_DIPSETTING( 0x40, DEF_STR( On ) )
718		PORT_DIPNAME( 0x80, 0x00, ~~DEF_~~STR( Unkn~~own~~ ) )
	716	PORT_DIPNAME( 0x80, 0x00, "Sync Adjustment (Set by factory)" ) PORT_DIPLOCATION("SW1:8") /* Sync Adjustment (Set by factory) */
719	717	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
720	718	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
721	719	INPUT_PORTS_END
722	720
	721	static INPUT_PORTS_START(pitbossa)
	722	PORT_INCLUDE(pitbossm)
	723
	724	PORT_MODIFY("DSW")
	725	PORT_DIPNAME( 0x20, 0x20, "Great Solitaire: Coins to start" ) PORT_DIPLOCATION("SW1:6")
	726	PORT_DIPSETTING( 0x00, "4 Coins" )
	727	PORT_DIPSETTING( 0x20, "2 Coins" )
	728	INPUT_PORTS_END
	729
723	730	static INPUT_PORTS_START(pbst30)
724	731	PORT_INCLUDE(meritm_crt260)
725	732
726	733	PORT_MODIFY("DSW")
727		PORT_DIPNAME( 0x01, 0x00, ~~DEF_S~~TR( Unknown ) )
	734	PORT_DIPNAME( 0x01, 0x00, "Invert Touch Screen Coordinates" ) PORT_DIPLOCATION("SW1:1") /* In case you installed the touch screen upside down??? */
728	735	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
729		PORT_DIPSETTING( 0x01, DEF_STR( On ) ) // when on, touch screen coordinates are mirrored?
730		PORT_DIPNAME( 0x02, 0x02, "Enable casino games" )
	736	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
	737	PORT_DIPNAME( 0x02, 0x02, "Enable Casino Games" ) PORT_DIPLOCATION("SW1:2")
731	738	PORT_DIPSETTING( 0x00, DEF_STR( No ) )
732	739	PORT_DIPSETTING( 0x02, DEF_STR( Yes ) )
733		PORT_DIPNAME( 0x04, 0x00, ~~DEF_~~STR( ~~Unkn~~own ) )
	740	PORT_DIPNAME( 0x04, 0x04, "Sexy Trivia Catagory" ) PORT_DIPLOCATION("SW1:3")
734	741	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
735	742	PORT_DIPSETTING( 0x04, DEF_STR( On ) )
736		PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
	743	PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:4") /* Likely Coin limit */
737	744	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
738	745	PORT_DIPSETTING( 0x08, DEF_STR( On ) )
739		PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) // off 1 coin 0.5 credit, on 1 coin 1 credit
	746	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:5")
	747	PORT_DIPSETTING( 0x00, DEF_STR( 2C_1C ) )
	748	PORT_DIPSETTING( 0x10, DEF_STR( 1C_1C ) )
	749	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:6")
740	750	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
741		PORT_DIPSETTING( 0x10, DEF_STR( On ) )
742		PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
743		PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
744	751	PORT_DIPSETTING( 0x20, DEF_STR( On ) )
745		PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
	752	PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:7")
746	753	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
747	754	PORT_DIPSETTING( 0x40, DEF_STR( On ) )
748		PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
	755	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:8")
749	756	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
750	757	PORT_DIPSETTING( 0x80, DEF_STR( On ) )
751	758	INPUT_PORTS_END
r5534	r5535
1098	1105	/*
1099	1106	Pit Boss Megastar - Merit Industries Inc. 1994
1100	1107
1101		Games are: Great Solitaire, Run 21 and Trivia Whiz 2000.
1102		-------------------------------------------------------
1103		Some of the pinouts probably flash lighted buttons as
1104		most Merit games have this feature.
1105		-------------------------------------------------------
	1108	Runs on standard Merit CRT-250 PCB with the following additions:
	1109	CRT-256 Memory Expansion board
	1110	CRT-254 Module (to connect the DS1204 to main board via connector J2)
	1111	CRT-243 Video Billboard board (Optional) with optional Video Billboard Keyboard
1106	1112
1107		EPROMS 1,2, and 3 are 27C2001's
1108		EPROMS 4 through 9 are 27C512's
	1113	From the "PIT BOSS MEGASTAR CHIP SET UPGRADE KIT" Program No. 9243-XX PM8938 Owner's Manual:
1109	1114
1110		One 8 bank dip switch.
	1115	This kit updates the Superstar 30 program (9233-xx) to the Megastar program. The new EPROM set consists of 3
	1116	EPROMS: 9243-xx-xx U9, U11, U15. EPROMs U10, U12 and U13 are unchanged and do not need to be replaced in a
	1117	field upgrade. U14 will be removed as it is no longer used.
1111	1118
1112		Two ~~YAMAHA V9938 Video~~ Processors.
	1119	Custom Program Versions:
1113	1120
1114		21.47727 MHz Crystal tied into pin 63 on both the V9938's
	1121	Program # Description Differences
	1122	9243-00-01 Standard Megastar Includes all Options / No Restrictions
	1123	9243-00-06 California Megastar Excludes Free Play Feature
	1124	9243-00-07 New Jersey Megastar Excludes Set Trivia and includes 4-coin limit with lockout coil
1115	1125
1116		CPU ~~Z80B~~
	1126	From ADDENDUM:
1117	1127
1118		Audio YM2149F
1119		Two Z80A-PIO
	1128	MANUAL: Megastar Owners Game Manual PM8939
	1129	DATE: 8/23/94
	1130	9244-00-01, 06, 07
1120	1131
1121		One Goldstar GM76C88L-15 (6264) SRAM
1122		Eight V53C464AP80 (41464) RAMS
	1132	Description of Changes:
1123	1133
1124		One PALCE16V8H-25PC/4
1125		One GAL22V10B
	1134	1- Great Draw Poker and 7 Stud Poker have been added to the program set
	1135	2- On page 3-1 legend artwork has changed. PASS has been replaced with
	1136	PASS/PLAY and COLLECT/QUIT has been replaced with COLLECT/QUIT/RAISE
	1137	3- An additional Solitaire Instruction decal has beed added to the kit.
	1138	This new Instruction decal is to be mounted in a visivle loction for
	1139	players use.
1126	1140
1127		chaneman Sept.23 2004
1128	1141	*/
1129	1142
1130		ROM_START( pitbossm )
	1143	ROM_START( pitbossm ) /* Dallas DS1204V security key attached to CRT-254 connected to J2 connector labeled 9244-00 U1-RO1 C1994 MII */
1131	1144	ROM_REGION( 0x80000, "maincpu", 0 )
1132		ROM_LOAD( "4", 0x00000, 0x10000, CRC(55e14fb1) SHA1(ec29764d1b63360f64b82452e0db8054b99fcca0) )
1133		ROM_LOAD( "5", 0x10000, 0x10000, CRC(853a1a99) SHA1(45e33442aa7e51c05c9ac8b8458937ee3ff4c21d) )
1134		ROM_LOAD( "6", 0x20000, 0x10000, CRC(47a9dfc7) SHA1(eca100003f5605bcf405f610a0458ccb67894d35) )
1135		ROM_LOAD( "7", 0x30000, 0x10000, CRC(b9fb4203) SHA1(84b514d9739d9c2ab1081cfc7cdedb41155ee038) )
1136		ROM_LOAD( "8", 0x40000, 0x10000, CRC(574fb3c7) SHA1(213741df3055b97ddd9889c2aa3d3e863e2c86d3) ) // == u16 on pitboss2/spitboss
1137		ROM_RELOAD( 0x50000, 0x10000)
1138		ROM_LOAD( "9", 0x60000, 0x10000, CRC(27034061) SHA1(cff6be592a4a3ab01c204b081470f224e6186c4d) )
	1145	ROM_LOAD( "9244-00-01_u9-r0", 0x00000, 0x10000, CRC(8317fea1) SHA1(eb84fdca7cd51883153561785571790d12d0d612) )
	1146	ROM_LOAD( "9244-00-01_u10-r0", 0x10000, 0x10000, CRC(853a1a99) SHA1(45e33442aa7e51c05c9ac8b8458937ee3ff4c21d) ) /* Could also be labeled 9234-00-01 U10-R0 */
	1147	ROM_LOAD( "9244-00-01_u11-r0", 0x20000, 0x10000, CRC(45223e0d) SHA1(45070e85d87aa67ecd6a1355212f1d24142fcbd0) )
	1148	ROM_LOAD( "9244-00-01_u12-r0", 0x30000, 0x10000, CRC(b9fb4203) SHA1(84b514d9739d9c2ab1081cfc7cdedb41155ee038) ) /* Could also be labeled 9234-00-01 U12-R0 */
	1149	ROM_LOAD( "9244-00-01_u13-r0", 0x40000, 0x10000, CRC(574fb3c7) SHA1(213741df3055b97ddd9889c2aa3d3e863e2c86d3) ) /* Could also be labeled 9234-00-01 U13-R0 */
	1150	ROM_LOAD( "9244-00-01_u14-r0", 0x50000, 0x10000, CRC(c0d18911) SHA1(def939c6bac1e3124197f3f783d06f3bef3d03e9) )
	1151	ROM_LOAD( "9244-00-01_u15-r0", 0x60000, 0x10000, CRC(740e3734) SHA1(6440d258af114f3820683b4e6fba5db6aea02231) )
1139	1152	ROM_RELOAD( 0x70000, 0x10000)
1140	1153
1141	1154
1142	1155	ROM_REGION( 0xc0000, "user1", 0 ) // extra data / extra banks?
1143		ROM_LOAD( "3", 0x00000, 0x40000, CRC(35f4ca46) SHA1(87917b3017f505fae65d6bfa2c7d6fb503c2da6a) )
1144		ROM_LOAD( "2", 0x40000, 0x40000, CRC(606f1656) SHA1(7f1e3a698a34d3c3b8f9f2cd8d5224b6c096e941) )
1145		ROM_LOAD( "1", 0x80000, 0x40000, CRC(590a1565) SHA1(b80ea967b6153847b2594e9c59bfe87559022b6c) )
	1156	ROM_LOAD( "qs9243-00-01_u7-r0", 0x00000, 0x40000, CRC(35f4ca46) SHA1(87917b3017f505fae65d6bfa2c7d6fb503c2da6a) ) /* These 3 roms are on CRT-256 sattalite PCB */
	1157	ROM_LOAD( "qs9243-00-01_u6-r0", 0x40000, 0x40000, CRC(606f1656) SHA1(7f1e3a698a34d3c3b8f9f2cd8d5224b6c096e941) )
	1158	ROM_LOAD( "qs9243-00-01_u5-r0", 0x80000, 0x40000, CRC(590a1565) SHA1(b80ea967b6153847b2594e9c59bfe87559022b6c) )
1146	1159	ROM_END
1147	1160
	1161	ROM_START( pitbossma ) /* Unprotected or patched?? The manual shows a DS1204 key for this set */
	1162	ROM_REGION( 0x80000, "maincpu", 0 )
	1163	ROM_LOAD( "9243-00-01_u9-r0", 0x00000, 0x10000, CRC(55e14fb1) SHA1(ec29764d1b63360f64b82452e0db8054b99fcca0) )
	1164	ROM_LOAD( "9243-00-01_u10-r0", 0x10000, 0x10000, CRC(853a1a99) SHA1(45e33442aa7e51c05c9ac8b8458937ee3ff4c21d) ) /* Could also be labeled 9234-00-01 U10-R0 */
	1165	ROM_LOAD( "9243-00-01_u11-r0", 0x20000, 0x10000, CRC(47a9dfc7) SHA1(eca100003f5605bcf405f610a0458ccb67894d35) )
	1166	ROM_LOAD( "9243-00-01_u12-r0", 0x30000, 0x10000, CRC(b9fb4203) SHA1(84b514d9739d9c2ab1081cfc7cdedb41155ee038) ) /* Could also be labeled 9234-00-01 U12-R0 */
	1167	ROM_LOAD( "9243-00-01_u13-r0", 0x40000, 0x10000, CRC(574fb3c7) SHA1(213741df3055b97ddd9889c2aa3d3e863e2c86d3) ) /* Could also be labeled 9234-00-01 U13-R0 */
	1168	ROM_RELOAD( 0x50000, 0x10000) /* U14 is unused for this set */
	1169	ROM_LOAD( "9243-00-01_u15-r0", 0x60000, 0x10000, CRC(27034061) SHA1(cff6be592a4a3ab01c204b081470f224e6186c4d) )
	1170	ROM_RELOAD( 0x70000, 0x10000)
1148	1171
1149		ROM_START( pbst30 ) /* Dallas DS1204V security key at U1 labeled 9234-10 U1-RO1 C1994 MII */
	1172
	1173	ROM_REGION( 0xc0000, "user1", 0 ) // extra data / extra banks?
	1174	ROM_LOAD( "qs9243-00-01_u7-r0", 0x00000, 0x40000, CRC(35f4ca46) SHA1(87917b3017f505fae65d6bfa2c7d6fb503c2da6a) ) /* These 3 roms are on CRT-256 sattalite PCB */
	1175	ROM_LOAD( "qs9243-00-01_u6-r0", 0x40000, 0x40000, CRC(606f1656) SHA1(7f1e3a698a34d3c3b8f9f2cd8d5224b6c096e941) )
	1176	ROM_LOAD( "qs9243-00-01_u5-r0", 0x80000, 0x40000, CRC(590a1565) SHA1(b80ea967b6153847b2594e9c59bfe87559022b6c) )
	1177	ROM_END
	1178
	1179	ROM_START( pbst30 ) /* Dallas DS1204V security key attached to CRT-254 connected to J2 connector labeled 9234-10 U1-RO1 C1994 MII */
1150	1180	ROM_REGION( 0x80000, "maincpu", 0 )
1151	1181	ROM_LOAD( "9234-10-01_u9-r0", 0x00000, 0x10000, CRC(96f39c9a) SHA1(df698e94a5204cf050ceadc5c257ca5f68171114) )
1152		ROM_LOAD( "5", 0x10000, 0x10000, BAD_DUMP CRC(853a1a99) SHA1(45e33442aa7e51c05c9ac8b8458937ee3ff4c21d) ) // taken from pitbossm
1153		ROM_LOAD( "9234-10-01_u11-r0", 0x20000, 0x10000, CRC(835fa041) SHA1(2ae754c5fcf50548eb214902409217d1643c6eaa) )
1154		ROM_LOAD( "7", 0x30000, 0x10000, BAD_DUMP CRC(b9fb4203) SHA1(84b514d9739d9c2ab1081cfc7cdedb41155ee038) ) // taken from pitbossm
1155		ROM_LOAD( "9234-10-01_u14-r0", 0x50000, 0x10000, CRC(9b0873a4) SHA1(7362c6220aa4bf1a9ab7c11cb8a51587a2a0a992) )
1156		ROM_LOAD( "9234-10-01_u15-r0", 0x60000, 0x10000, CRC(9fbd8582) SHA1(c0f68c8a7cdca34c8736cefc71767c421bcaba8a) )
	1182	ROM_LOAD( "9234-00-01_u10-r0", 0x10000, 0x10000, CRC(853a1a99) SHA1(45e33442aa7e51c05c9ac8b8458937ee3ff4c21d) )
	1183	ROM_LOAD( "9234-10-01_u11-r0", 0x20000, 0x10000, CRC(835fa041) SHA1(2ae754c5fcf50548eb214902409217d1643c6eaa) )
	1184	ROM_LOAD( "9234-00-01_u12-r0", 0x30000, 0x10000, CRC(b9fb4203) SHA1(84b514d9739d9c2ab1081cfc7cdedb41155ee038) )
	1185	ROM_LOAD( "9234-00-01_u13-r0", 0x40000, 0x10000, CRC(574fb3c7) SHA1(213741df3055b97ddd9889c2aa3d3e863e2c86d3) )
	1186	ROM_LOAD( "9234-10-01_u14-r0", 0x50000, 0x10000, CRC(9b0873a4) SHA1(7362c6220aa4bf1a9ab7c11cb8a51587a2a0a992) )
	1187	ROM_LOAD( "9234-10-01_u15-r0", 0x60000, 0x10000, CRC(9fbd8582) SHA1(c0f68c8a7cdca34c8736cefc71767c421bcaba8a) )
1157	1188
1158	1189
1159	1190	ROM_REGION( 0xc0000, "user1", 0 ) // extra data / extra banks?
1160		ROM_LOAD( "qs9234-01_u7-r0", 0x00000, 0x40000, CRC(c0534aaa) SHA1(4b3cbf03f29fd5b4b8fd423e73c0c8147692fa75) )
	1191	ROM_LOAD( "qs9234-01_u7-r0", 0x00000, 0x40000, CRC(c0534aaa) SHA1(4b3cbf03f29fd5b4b8fd423e73c0c8147692fa75) ) /* These 3 roms are on CRT-256 sattalite PCB */
1161	1192	ROM_LOAD( "qs9234-01_u6-r0", 0x40000, 0x40000, CRC(fe2cd934) SHA1(623011dc53ed6eefefa0725dba6fd1efee2077c1) )
1162	1193	ROM_LOAD( "qs9234-01_u5-r0", 0x80000, 0x40000, CRC(293fe305) SHA1(8a551ae8fb4fa4bf329128be1bfd6f1c3ff5a366) )
1163	1194	ROM_END
1164	1195
1165		ROM_START( pbst30b ) /* Dallas DS1204V security key at U1 labeled 9234-01 U1-RO1 C1993 MII */
	1196	ROM_START( pbst30b ) /* Dallas DS1204V security key attached to CRT-254 connected to J2 connector labeled 9234-01 U1-RO1 C1993 MII */
1166	1197	ROM_REGION( 0x80000, "maincpu", 0 )
1167	1198	ROM_LOAD( "9234-00-01_u9-r0a", 0x00000, 0x10000, CRC(5f058f95) SHA1(98382935340a076bdb1b20c7f16c25b6084599fe) )
1168		ROM_LOAD( "5", 0x10000, 0x10000, BAD_DUMP CRC(853a1a99) SHA1(45e33442aa7e51c05c9ac8b8458937ee3ff4c21d) ) // taken from pitbossm
1169		ROM_LOAD( "9234-00-01_u11-r0a", 0x20000, 0x10000, CRC(79125fb5) SHA1(6ca4f33c363cfb6f5c0f23b8fcc8cfcc076f68b1) )
1170		ROM_LOAD( "7", 0x30000, 0x10000, BAD_DUMP CRC(b9fb4203) SHA1(84b514d9739d9c2ab1081cfc7cdedb41155ee038) ) // taken from pitbossm
1171		ROM_LOAD( "9234-00-01_u14-r0a", 0x50000, 0x10000, CRC(e83f91d5) SHA1(1d64c943787b239763f44be412ee7f5ad13eb37d) )
1172		ROM_LOAD( "9234-00-01_u15-r0a", 0x60000, 0x10000, CRC(f10f0d39) SHA1(2b5d5a93adb5251e09160b10c067b6e70289f608) )
	1199	ROM_LOAD( "9234-00-01_u10-r0", 0x10000, 0x10000, CRC(853a1a99) SHA1(45e33442aa7e51c05c9ac8b8458937ee3ff4c21d) )
	1200	ROM_LOAD( "9234-00-01_u11-r0a", 0x20000, 0x10000, CRC(79125fb5) SHA1(6ca4f33c363cfb6f5c0f23b8fcc8cfcc076f68b1) )
	1201	ROM_LOAD( "9234-00-01_u12-r0", 0x30000, 0x10000, CRC(b9fb4203) SHA1(84b514d9739d9c2ab1081cfc7cdedb41155ee038) )
	1202	ROM_LOAD( "9234-00-01_u13-r0", 0x40000, 0x10000, CRC(574fb3c7) SHA1(213741df3055b97ddd9889c2aa3d3e863e2c86d3) )
	1203	ROM_LOAD( "9234-00-01_u14-r0a", 0x50000, 0x10000, CRC(e83f91d5) SHA1(1d64c943787b239763f44be412ee7f5ad13eb37d) )
	1204	ROM_LOAD( "9234-00-01_u15-r0a", 0x60000, 0x10000, CRC(f10f0d39) SHA1(2b5d5a93adb5251e09160b10c067b6e70289f608) )
1173	1205
1174	1206
1175	1207	ROM_REGION( 0xc0000, "user1", 0 ) // extra data / extra banks?
1176		ROM_LOAD( "qs9234-01_u7-r0", 0x00000, 0x40000, CRC(c0534aaa) SHA1(4b3cbf03f29fd5b4b8fd423e73c0c8147692fa75) )
	1208	ROM_LOAD( "qs9234-01_u7-r0", 0x00000, 0x40000, CRC(c0534aaa) SHA1(4b3cbf03f29fd5b4b8fd423e73c0c8147692fa75) ) /* These 3 roms are on CRT-256 sattalite PCB */
1177	1209	ROM_LOAD( "qs9234-01_u6-r0", 0x40000, 0x40000, CRC(fe2cd934) SHA1(623011dc53ed6eefefa0725dba6fd1efee2077c1) )
1178	1210	ROM_LOAD( "qs9234-01_u5-r0", 0x80000, 0x40000, CRC(293fe305) SHA1(8a551ae8fb4fa4bf329128be1bfd6f1c3ff5a366) )
1179	1211	ROM_END
r5534	r5535
1488	1520
1489	1521	ROM_START( megat6 ) /* Dallas DS1204V security key at U5 labeled 9255-80 U5-B-RO1 C1998 MII */
1490	1522	ROM_REGION( 0x400000, "maincpu", 0 )
1491		ROM_LOAD( "9255-80-01_u32-r0", 0x000000, 0x100000, CRC(f8f7f48e) SHA1(1bebe1f8898c60b795a0f794ca9b79e03d2744e4) ) /* Location U32 */
	1523	ROM_LOAD( "9255-60-01_u32-r0", 0x000000, 0x100000, CRC(f8f7f48e) SHA1(1bebe1f8898c60b795a0f794ca9b79e03d2744e4) ) /* Location U32 */
1492	1524	ROM_LOAD( "qs9255-08_u36-r0", 0x100000, 0x080000, CRC(800f5a1f) SHA1(4d3ee6fb896d6452aab1f279a3ee878284bd1acc) ) /* Location U36 */
1493	1525	ROM_RELOAD( 0x180000, 0x080000 )
1494	1526	ROM_LOAD( "qs9255-08_u37-r0", 0x200000, 0x100000, CRC(5ba01949) SHA1(1598949ea18d07bbc78af0ddd279a687173c1229) ) /* Location U37 */
r5534	r5535
1504	1536	ROM_LOAD( "sc3981-0a.u51", 0x000, 0x117, CRC(4fc750d0) SHA1(d09ff7a8c66aeb5c49e9fec84bd1521e3f5d8d0a) )
1505	1537	ROM_END
1506	1538
	1539	static DRIVER_INIT(pitbossm)
	1540	{
	1541	static const UINT8 pitbossm_ds1204_key[8] =
	1542	{ 0xf0, 0xaa, 0x0f, 0x0f, 0x55, 0x55, 0xff, 0xab };
	1543
	1544	static const UINT8 pitbossm_ds1204_nvram[16] =
	1545	{ 0x16, 0x90, 0xa0, 0x52, 0xd8, 0x6c, 0x12, 0xaf, 0x36, 0x22, 0x61, 0x35, 0x0d, 0x58, 0x0c, 0x00 };
	1546
	1547	ds1204_init(machine, pitbossm_ds1204_key, pitbossm_ds1204_nvram);
	1548
	1549	};
	1550
1507	1551	static DRIVER_INIT(pbst30)
1508	1552	{
1509	1553	static const UINT8 pbst30b_ds1204_key[8] =
r5534	r5535
1607	1651	GAME( 1988, spitboss, 0, meritm_crt250, meritm_crt250, 0, ROT0, "Merit", "Super Pit Boss", GAME_IMPERFECT_GRAPHICS )
1608	1652	GAME( 1990, pitbosss, 0, meritm_crt250, meritm_crt250, 0, ROT0, "Merit", "Pit Boss Superstar", GAME_IMPERFECT_GRAPHICS )
1609	1653
1610		/* CRT 250 + question roms */
1611		GAME( 1994, pitbossm, 0, meritm_crt250_questions, pitbossm, 0, ROT0, "Merit", "Pit Boss Megastar", GAME_IMPERFECT_GRAPHICS )
	1654	/* CRT 250 + CRT 254 + CRT 256 */
	1655	GAME( 1994, pbst30, 0, meritm_crt250_crt252_crt258, pbst30, pbst30, ROT0, "Merit", "Pit Boss Supertouch 30 (9234-10-01)", GAME_IMPERFECT_GRAPHICS )
	1656	GAME( 1993, pbst30b, pbst30, meritm_crt250_crt252_crt258, pbst30, pbst30b, ROT0, "Merit", "Pit Boss Supertouch 30 (9234-00-01)", GAME_IMPERFECT_GRAPHICS )
1612	1657
1613		/* CRT 250 + CRT 252 + CRT 258 */
1614		GAME( 1994, pbst30, 0, meritm_crt250_crt252_crt258, pbst30, pbst30, ROT0, "Merit", "Pit Boss Supertouch 30", GAME_IMPERFECT_GRAPHICS )
1615		GAME( 1993, pbst30b, 0, meritm_crt250_crt252_crt258, pbst30, pbst30b, ROT0, "Merit", "Pit Boss Supertouch 30 (set 2)", GAME_IMPERFECT_GRAPHICS )
	1658	/* CRT 250 + CRT 254 + CRT 256 */
	1659	GAME( 1994, pitbossm, 0, meritm_crt250_questions, pitbossm, pitbossm, ROT0, "Merit", "Pit Boss Megastar (9244-00-01)", GAME_IMPERFECT_GRAPHICS )
	1660	GAME( 1994, pitbossma, pitbossm, meritm_crt250_questions, pitbossa, 0, ROT0, "Merit", "Pit Boss Megastar (9243-00-01)", GAME_IMPERFECT_GRAPHICS )
1616	1661
1617	1662	/* CRT 260 */
1618	1663	GAME( 1996, megat3, 0, meritm_crt260, meritm_crt260, megat3, ROT0, "Merit", "Megatouch III (9255-20-01 RON, Standard version)", GAME_IMPERFECT_GRAPHICS )

src/mame/drivers/midwunit.c
r5534	r5535
664	664
665	665	ROM_START( mk3 )
666	666	ROM_REGION16_LE( 0x800000, "dcs", ROMREGION_ERASEFF ) /* sound data */
667		ROM_LOAD16_BYTE( "mk3-u2.bin", 0x000000, 0x100000, ~~BAD_DUMP~~ CRC(3838cfe5) SHA1(e3d2901~~f3b~~ae~~1362~~74~~2fc6~~e~~e0aa~~3~~1c9~~f63b4dfa3) )
	667	ROM_LOAD16_BYTE( "mk3-u2.bin", 0x000000, 0x100000, CRC(5273436f) SHA1(e1735842a0159eafe79d878d44e3828df9bfa5bb) )
668	668	ROM_LOAD16_BYTE( "mk3-u3.bin", 0x200000, 0x100000, CRC(856fe411) SHA1(6165ebecfce7500e948d84492ffa19eed7f47091) )
669	669	ROM_LOAD16_BYTE( "mk3-u4.bin", 0x400000, 0x100000, CRC(428a406f) SHA1(e70ec83cd054de0da1e178720ed0035b8887f797) )
670	670	ROM_LOAD16_BYTE( "mk3-u5.bin", 0x600000, 0x100000, CRC(3b98a09f) SHA1(edf1d02a56dcf3349e6b4bb4097acfe7592305f4) )
r5534	r5535
703	703
704	704	ROM_START( mk3r20 )
705	705	ROM_REGION16_LE( 0x800000, "dcs", ROMREGION_ERASEFF ) /* sound data */
706		ROM_LOAD16_BYTE( "mk3-u2.bin", 0x000000, 0x100000, ~~BAD_DUMP~~ CRC(3838cfe5) SHA1(e3d2901~~f3b~~ae~~1362~~74~~2fc6~~e~~e0aa~~3~~1c9~~f63b4dfa3) )
	706	ROM_LOAD16_BYTE( "mk3-u2.bin", 0x000000, 0x100000, CRC(5273436f) SHA1(e1735842a0159eafe79d878d44e3828df9bfa5bb) )
707	707	ROM_LOAD16_BYTE( "mk3-u3.bin", 0x200000, 0x100000, CRC(856fe411) SHA1(6165ebecfce7500e948d84492ffa19eed7f47091) )
708	708	ROM_LOAD16_BYTE( "mk3-u4.bin", 0x400000, 0x100000, CRC(428a406f) SHA1(e70ec83cd054de0da1e178720ed0035b8887f797) )
709	709	ROM_LOAD16_BYTE( "mk3-u5.bin", 0x600000, 0x100000, CRC(3b98a09f) SHA1(edf1d02a56dcf3349e6b4bb4097acfe7592305f4) )
r5534	r5535
742	742
743	743	ROM_START( mk3r10 )
744	744	ROM_REGION16_LE( 0x800000, "dcs", ROMREGION_ERASEFF ) /* sound data */
745		ROM_LOAD16_BYTE( "mk3-u2.bin", 0x000000, 0x100000, ~~BAD_DUMP~~ CRC(3838cfe5) SHA1(e3d2901~~f3b~~ae~~1362~~74~~2fc6~~e~~e0aa~~3~~1c9~~f63b4dfa3) )
	745	ROM_LOAD16_BYTE( "mk3-u2.bin", 0x000000, 0x100000, CRC(5273436f) SHA1(e1735842a0159eafe79d878d44e3828df9bfa5bb) )
746	746	ROM_LOAD16_BYTE( "mk3-u3.bin", 0x200000, 0x100000, CRC(856fe411) SHA1(6165ebecfce7500e948d84492ffa19eed7f47091) )
747	747	ROM_LOAD16_BYTE( "mk3-u4.bin", 0x400000, 0x100000, CRC(428a406f) SHA1(e70ec83cd054de0da1e178720ed0035b8887f797) )
748	748	ROM_LOAD16_BYTE( "mk3-u5.bin", 0x600000, 0x100000, CRC(3b98a09f) SHA1(edf1d02a56dcf3349e6b4bb4097acfe7592305f4) )
r5534	r5535
781	781
782	782	ROM_START( mk3p40 )
783	783	ROM_REGION16_LE( 0x800000, "dcs", ROMREGION_ERASEFF ) /* sound data */
784		ROM_LOAD16_BYTE( "mk3-u2.bin", 0x000000, 0x100000, ~~BAD_DUMP~~ CRC(3838cfe5) SHA1(e3d2901~~f3b~~ae~~1362~~74~~2fc6~~e~~e0aa~~3~~1c9~~f63b4dfa3) )
	784	ROM_LOAD16_BYTE( "mk3-u2.bin", 0x000000, 0x100000, CRC(5273436f) SHA1(e1735842a0159eafe79d878d44e3828df9bfa5bb) )
785	785	ROM_LOAD16_BYTE( "mk3-u3.bin", 0x200000, 0x100000, CRC(856fe411) SHA1(6165ebecfce7500e948d84492ffa19eed7f47091) )
786	786	ROM_LOAD16_BYTE( "mk3-u4.bin", 0x400000, 0x100000, CRC(428a406f) SHA1(e70ec83cd054de0da1e178720ed0035b8887f797) )
787	787	ROM_LOAD16_BYTE( "mk3-u5.bin", 0x600000, 0x100000, CRC(3b98a09f) SHA1(edf1d02a56dcf3349e6b4bb4097acfe7592305f4) )

src/mame/drivers/toypop.c
r5534	r5535
663	663	ROM_LOAD( "tp1-5.2p", 0x0400, 0x0200, CRC(4d77fa5a) SHA1(2438910314b23ecafb553230244f3931861ad2da) ) /* sprites */
664	664
665	665	ROM_REGION( 0x0100, "namco", 0 ) /* sound prom */
666		ROM_LOAD( "lr1-4.3d", 0x0000, 0x0100, CRC(16a9166a) SHA1(847cbaf7c88616576c410177e066ae1d792ac0ba) )
	666	ROM_LOAD( "tp1-6.3d", 0x0000, 0x0100, CRC(16a9166a) SHA1(847cbaf7c88616576c410177e066ae1d792ac0ba) )
667	667	ROM_END
668	668
669	669

src/mame/drivers/phoenix.c
r5534	r5535
513	513
514	514	/* Same as Phoenix, but uses an AY8910 and an extra visible line (column) */
515	515
516		static ~~const i~~8085_~~config~~ survival_i8085_config =
	516	static I8085_CONFIG( survival_i8085_config )
517	517	{
518		NULL, /* INTE changed callback */
519		NULL, /* STATUS changed callback */
520		NULL, /* SOD changed callback (8085A only) */
521		survival_sid_callback /* SID changed callback (8085A only) */
	518	DEVCB_NULL, /* STATUS changed callback */
	519	DEVCB_NULL, /* INTE changed callback */
	520	DEVCB_LINE(survival_sid_callback), /* SID changed callback (8085A only) */
	521	DEVCB_NULL /* SOD changed callback (8085A only) */
522	522	};
523	523
524	524	static MACHINE_DRIVER_START( survival )

src/mame/drivers/taito_f2.c
r5534	r5535
1132	1132	AM_RANGE(0x300000, 0x30ffff) AM_RAM
1133	1133	AM_RANGE(0x400000, 0x401fff) AM_READWRITE(TC0430GRW_word_r, TC0430GRW_word_w) /* ROZ tilemap */
1134	1134	AM_RANGE(0x402000, 0x40200f) AM_WRITE(TC0430GRW_ctrl_word_w)
1135		AM_RANGE(0x700000, 0x701fff) AM_RAM_WRITE(~~pale~~t~~ter~~a~~m16_xRRRRRGGGGGBBBBB_w~~ord_~~w) AM_BASE(&~~palette~~ram16~~)
	1135	AM_RANGE(0x700000, 0x701fff) AM_RAM_WRITE(taitof2_palette_w)
1136	1136	AM_RANGE(0x800000, 0x80ffff) AM_READWRITE(TC0100SCN_word_0_r, TC0100SCN_word_0_w) /* tilemaps */
1137	1137	AM_RANGE(0x820000, 0x82000f) AM_READWRITE(TC0100SCN_ctrl_word_0_r, TC0100SCN_ctrl_word_0_w)
1138	1138	AM_RANGE(0x900000, 0x90ffff) AM_RAM AM_BASE(&spriteram16) AM_SIZE(&spriteram_size)
r5534	r5535
3258	3258	MDRV_GFXDECODE(thundfox)
3259	3259	MDRV_VIDEO_START(taitof2_thundfox)
3260	3260	MDRV_VIDEO_EOF(taitof2_partial_buffer_delayed_thundfox)
3261		MDRV_VIDEO_UPDATE(thundfox)
	3261	MDRV_VIDEO_UPDATE(taitof2_thundfox)
3262	3262	MACHINE_DRIVER_END
3263	3263
3264	3264
r5534	r5535
3326	3326	/* video hardware */
3327	3327	MDRV_VIDEO_START(taitof2_ssi)
3328	3328	MDRV_VIDEO_EOF(taitof2_partial_buffer_delayed_thundfox) // buffer_delayed_thundfox instead of buffer_delayed fixes the butterfly powerup
3329		MDRV_VIDEO_UPDATE(ssi)
	3329	MDRV_VIDEO_UPDATE(taitof2_ssi)
3330	3330	MACHINE_DRIVER_END
3331	3331
3332	3332
r5534	r5535
3379	3379	MDRV_GFXDECODE(deadconx)
3380	3380	MDRV_VIDEO_START(taitof2_footchmp)
3381	3381	MDRV_VIDEO_EOF(taitof2_full_buffer_delayed)
3382		MDRV_VIDEO_UPDATE(deadconx)
	3382	MDRV_VIDEO_UPDATE(taitof2_deadconx)
3383	3383	MACHINE_DRIVER_END
3384	3384
3385	3385
r5534	r5535
3394	3394	MDRV_GFXDECODE(deadconx)
3395	3395	MDRV_VIDEO_START(taitof2_hthero)
3396	3396	MDRV_VIDEO_EOF(taitof2_full_buffer_delayed)
3397		MDRV_VIDEO_UPDATE(deadconx)
	3397	MDRV_VIDEO_UPDATE(taitof2_deadconx)
3398	3398	MACHINE_DRIVER_END
3399	3399
3400	3400
r5534	r5535
3421	3421	/* video hardware */
3422	3422	MDRV_GFXDECODE(yuyugogo)
3423	3423	MDRV_VIDEO_START(taitof2_yuyugogo)
3424		MDRV_VIDEO_UPDATE(yesnoj)
	3424	MDRV_VIDEO_UPDATE(taitof2_yesnoj)
3425	3425	MACHINE_DRIVER_END
3426	3426
3427	3427
r5534	r5535
3488	3488	MDRV_GFXDECODE(deadconx)
3489	3489	MDRV_PALETTE_LENGTH(8192)
3490	3490	MDRV_VIDEO_START(taitof2_metalb)
3491		MDRV_VIDEO_UPDATE(metalb)
	3491	MDRV_VIDEO_UPDATE(taitof2_metalb)
3492	3492	MACHINE_DRIVER_END
3493	3493
3494	3494
r5534	r5535
3515	3515	/* video hardware */
3516	3516	MDRV_GFXDECODE(yuyugogo)
3517	3517	MDRV_VIDEO_START(taitof2_yesnoj)
3518		MDRV_VIDEO_UPDATE(yesnoj)
	3518	MDRV_VIDEO_UPDATE(taitof2_yesnoj)
3519	3519	MACHINE_DRIVER_END
3520	3520
3521	3521
r5534	r5535
3529	3529	/* video hardware */
3530	3530	MDRV_GFXDECODE(deadconx)
3531	3531	MDRV_VIDEO_START(taitof2_deadconx)
3532		MDRV_VIDEO_UPDATE(deadconx)
	3532	MDRV_VIDEO_UPDATE(taitof2_deadconx)
3533	3533	MACHINE_DRIVER_END
3534	3534
3535	3535
r5534	r5535
3543	3543	/* video hardware */
3544	3544	MDRV_GFXDECODE(deadconx)
3545	3545	MDRV_VIDEO_START(taitof2_deadconxj)
3546		MDRV_VIDEO_UPDATE(deadconx)
	3546	MDRV_VIDEO_UPDATE(taitof2_deadconx)
3547	3547	MACHINE_DRIVER_END
3548	3548
3549	3549
r5534	r5535
3609	3609	/* video hardware */
3610	3610	MDRV_GFXDECODE(pivot)
3611	3611	MDRV_VIDEO_START(taitof2_driftout)
3612		MDRV_VIDEO_UPDATE(taitof2_pri_roz)
	3612	MDRV_VIDEO_UPDATE(taitof2_driftout)
3613	3613	MACHINE_DRIVER_END
3614	3614
3615	3615

src/mame/drivers/hyhoo.c
r5534	r5535
255	255	static MACHINE_DRIVER_START( hyhoo )
256	256
257	257	/* basic machine hardware */
258		MDRV_CPU_ADD("maincpu", Z80, 5000000/1) /* 5.00 MHz ?? */
	258	MDRV_CPU_ADD("maincpu", Z80, 5000000) /* 5.00 MHz ?? */
259	259	MDRV_CPU_PROGRAM_MAP(hyhoo_map)
260	260	MDRV_CPU_IO_MAP(hyhoo_io_map)
261	261	MDRV_CPU_VBLANK_INT("screen", nb1413m3_interrupt)

src/mame/drivers/bzone.c
r5534	r5535
206	206	#include "video/avgdvg.h"
207	207	#include "machine/mathbox.h"
208	208	#include "machine/atari_vg.h"
209		#include "sound/pokey.h"
210	209	#include "rendlay.h"
211	210	#include "bzone.h"
212	211
	212	#include "sound/pokey.h"
	213
213	214	#include "bzone.lh"
214	215
215		#define MASTER_CLOCK (XTAL_12_096MHz)
216		#define CLOCK_3KHZ (MASTER_CLOCK / 4096)
217	216
218
219	217	static UINT8 analog_data;
220	218
221	219	UINT8 rb_input_select;
r5534	r5535
308	306	AM_RANGE(0x1810, 0x1810) AM_DEVREAD("mathbox", mathbox_lo_r)
309	307	AM_RANGE(0x1818, 0x1818) AM_DEVREAD("mathbox", mathbox_hi_r)
310	308	AM_RANGE(0x1820, 0x182f) AM_DEVREADWRITE("pokey", pokey_r, pokey_w)
	309	#if BZONE_DISCRETE
	310	AM_RANGE(0x1840, 0x1840) AM_DEVWRITE("discrete", bzone_sounds_w)
	311	#else
311	312	AM_RANGE(0x1840, 0x1840) AM_WRITE(bzone_sounds_w)
	313	#endif
312	314	AM_RANGE(0x1860, 0x187f) AM_DEVWRITE("mathbox", mathbox_go_w)
313	315	AM_RANGE(0x2000, 0x2fff) AM_RAM AM_BASE(&vectorram) AM_SIZE(&vectorram_size) AM_REGION("maincpu", 0x2000)
314	316	AM_RANGE(0x3000, 0x7fff) AM_ROM
r5534	r5535
419	421	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_START1 )
420	422	PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_START2 )
421	423	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
	424
	425	#if BZONE_DISCRETE
	426	PORT_START("R11")
	427	PORT_ADJUSTER( 50, "Engine Frequency" )
	428	#endif
422	429	INPUT_PORTS_END
423	430
424	431
r5534	r5535
543	550	*
544	551	*************************************/
545	552
546		static MACHINE_DRIVER_START( bzone )
	553	static MACHINE_DRIVER_START( bzone_base )
547	554
548	555	/* basic machine hardware */
549		MDRV_CPU_ADD("maincpu", M6502, MASTER_CLOCK / 8)
	556	MDRV_CPU_ADD("maincpu", M6502, BZONE_MASTER_CLOCK / 8)
550	557	MDRV_CPU_PROGRAM_MAP(bzone_map)
551		MDRV_CPU_PERIODIC_INT(bzone_interrupt, (double)MASTER_CLOCK / 4096 / 12)
	558	MDRV_CPU_PERIODIC_INT(bzone_interrupt, (double)BZONE_MASTER_CLOCK / 4096 / 12)
552	559
553	560	MDRV_MACHINE_START(bzone)
554	561
r5534	r5535
564	571	/* Drivers */
565	572	MDRV_MATHBOX_ADD("mathbox")
566	573
	574	MACHINE_DRIVER_END
	575
	576	static MACHINE_DRIVER_START( bzone )
	577
	578	MDRV_IMPORT_FROM(bzone_base)
	579
567	580	/* sound hardware */
	581	#if BZONE_DISCRETE
	582	MDRV_IMPORT_FROM(bzone_audio)
	583	#else
568	584	MDRV_SPEAKER_STANDARD_MONO("mono")
569	585
570	586	MDRV_SOUND_ADD("pokey", POKEY, MASTER_CLOCK / 8)
r5534	r5535
573	589
574	590	MDRV_SOUND_ADD("custom", BZONE, 0)
575	591	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
	592	#endif
576	593	MACHINE_DRIVER_END
577	594
578	595
r5534	r5535
582	599	MDRV_IMPORT_FROM(bzone)
583	600
584	601	/* sound hardware */
585		MDRV_SOUND_REPLACE("pokey", POKEY, MASTER_CLOCK / 8)
	602	MDRV_SOUND_REPLACE("pokey", POKEY, BZONE_MASTER_CLOCK / 8)
586	603	MDRV_SOUND_CONFIG(bzone_pokey_interface)
587	604	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
588	605	MACHINE_DRIVER_END
r5534	r5535
591	608	static MACHINE_DRIVER_START( redbaron )
592	609
593	610	/* basic machine hardware */
594		MDRV_IMPORT_FROM(bzone)
	611	MDRV_IMPORT_FROM(bzone_base)
595	612	MDRV_CPU_MODIFY("maincpu")
596	613	MDRV_CPU_PROGRAM_MAP(redbaron_map)
597		MDRV_CPU_PERIODIC_INT(bzone_interrupt, (double)MASTER_CLOCK / 4096 / 12)
	614	MDRV_CPU_PERIODIC_INT(bzone_interrupt, (double)BZONE_MASTER_CLOCK / 4096 / 12)
598	615
599	616	MDRV_MACHINE_START(redbaron)
600	617
r5534	r5535
608	625	MDRV_VIDEO_START(avg_bzone)
609	626
610	627	/* sound hardware */
611		MDRV_SOUND_REPLACE("pokey", POKEY, 1500000)
	628	MDRV_SPEAKER_STANDARD_MONO("mono")
	629
	630	MDRV_SOUND_ADD("pokey", POKEY, 1500000)
612	631	MDRV_SOUND_CONFIG(redbaron_pokey_interface)
613	632	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
614	633
615		MDRV_SOUND_REPLACE("custom", REDBARON, 0)
	634	MDRV_SOUND_ADD("custom", REDBARON, 0)
	635
616	636	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
617	637	MACHINE_DRIVER_END
618	638

src/mame/drivers/sauro.c
r5534	r5535
11	11	Memory mapped:
12	12
13	13	0000-dfff ROM
14		e000-e7ff RAM
	14	e000-e7ff RAM, battery backed
15	15	e800-ebff Sprite RAM
16	16	f000-fbff Background Video RAM
17	17	f400-ffff Background Color RAM
r5534	r5535
136	136
137	137	static ADDRESS_MAP_START( sauro_map, ADDRESS_SPACE_PROGRAM, 8 )
138	138	AM_RANGE(0x0000, 0xdfff) AM_ROM
139		AM_RANGE(0xe000, 0xe7ff) AM_RAM
	139	AM_RANGE(0xe000, 0xe7ff) AM_RAM AM_BASE(&generic_nvram) AM_SIZE(&generic_nvram_size)
140	140	AM_RANGE(0xe800, 0xebff) AM_RAM AM_BASE(&spriteram) AM_SIZE(&spriteram_size)
141	141	AM_RANGE(0xf000, 0xf3ff) AM_RAM_WRITE(tecfri_videoram_w) AM_BASE(&tecfri_videoram)
142	142	AM_RANGE(0xf400, 0xf7ff) AM_RAM_WRITE(tecfri_colorram_w) AM_BASE(&tecfri_colorram)
r5534	r5535
182	182
183	183	static ADDRESS_MAP_START( trckydoc_map, ADDRESS_SPACE_PROGRAM, 8 )
184	184	AM_RANGE(0x0000, 0xdfff) AM_ROM
185		AM_RANGE(0xe000, 0xe7ff) AM_RAM
	185	AM_RANGE(0xe000, 0xe7ff) AM_RAM AM_BASE(&generic_nvram) AM_SIZE(&generic_nvram_size)
186	186	AM_RANGE(0xe800, 0xebff) AM_RAM AM_MIRROR(0x400) AM_BASE(&spriteram) AM_SIZE(&spriteram_size)
187	187	AM_RANGE(0xf000, 0xf3ff) AM_RAM_WRITE(tecfri_videoram_w) AM_BASE(&tecfri_videoram)
188	188	AM_RANGE(0xf400, 0xf7ff) AM_RAM_WRITE(tecfri_colorram_w) AM_BASE(&tecfri_colorram)
r5534	r5535
337	337	MDRV_CPU_ADD("maincpu", Z80, XTAL_20MHz/4) /* verified on pcb */
338	338	MDRV_CPU_VBLANK_INT("screen", irq0_line_hold)
339	339
	340	MDRV_NVRAM_HANDLER(generic_1fill)
	341
340	342	/* video hardware */
341	343	MDRV_SCREEN_ADD("screen", RASTER)
342	344	MDRV_SCREEN_REFRESH_RATE(55.72) /* verified on pcb */

src/mame/drivers/midtunit.c
r5534	r5535
711	711	ROM_END
712	712
713	713
	714	ROM_START( mkturbo )
	715	ROM_REGION( 0x50000, "adpcm", 0 ) /* sound CPU */
	716	ROM_LOAD( "mks-u3.rom", 0x10000, 0x40000, CRC(c615844c) SHA1(5732f9053a5f73b0cc3b0166d7dc4430829d5bc7) )
	717
	718	ROM_REGION( 0x200000, "oki", 0 ) /* ADPCM */
	719	ROM_LOAD( "mks-u12.rom", 0x00000, 0x40000, CRC(258bd7f9) SHA1(463890b23f17350fb9b8a85897b0777c45bc2d54) )
	720	ROM_RELOAD( 0x40000, 0x40000 )
	721	ROM_LOAD( "mks-u13.rom", 0x80000, 0x40000, CRC(7b7ec3b6) SHA1(6eec1b90d4a4855f34a7ebfbf93f3358d5627db4) )
	722	ROM_RELOAD( 0xc0000, 0x40000 )
	723
	724	/* A 'KOMBO BOARD' daughtercard holding a GAL16V8A-2SP, 27C040 EPROM and a 9.8304MHz XTAL plugs into the UG12 socket */
	725	ROM_REGION16_LE( 0x100000, "user1", 0 ) /* 34010 code */
	726	ROM_LOAD16_BYTE( "kombo-rom-uj-12.bin", 0x00000, 0x80000, CRC(7a441f2d) SHA1(3b731bcbd73721ea0cc20157ec5181d25922523c) )
	727	ROM_LOAD16_BYTE( "kombo-rom-ug-12.bin", 0x00001, 0x80000, CRC(45bed5a1) SHA1(dba2c21878925afdcaf61520c18ebefd5e9617db) )
	728
	729	ROM_REGION( 0xc00000, "gfx1", 0 )
	730	ROM_LOAD( "mkt-ug14.bin", 0x000000, 0x80000, CRC(9e00834e) SHA1(2b97b63f52ba1dba6af6ae56c223519a52b2ab9d) )
	731	ROM_LOAD( "mkt-ug16.bin", 0x080000, 0x80000, CRC(52c9d1e5) SHA1(7b1880fca0a11544782b70365c7dd96381ac48e7) )
	732	ROM_LOAD( "mkt-ug17.bin", 0x100000, 0x80000, CRC(e34fe253) SHA1(6b010bee795c1770297c9557ded1fe83425857f2) )
	733
	734	ROM_LOAD( "mkt-uj14.bin", 0x300000, 0x80000, CRC(f4b0aaa7) SHA1(4cc6ee34c89e3cde325ad24b29511f70ae6a5a72) )
	735	ROM_LOAD( "mkt-uj16.bin", 0x380000, 0x80000, CRC(c94c58cf) SHA1(974d75667eee779497325d5be8df937f15417edf) )
	736	ROM_LOAD( "mkt-uj17.bin", 0x400000, 0x80000, CRC(a56e12f5) SHA1(5db637c4710990cd06bb0069714b19621532e431) )
	737
	738	ROM_LOAD( "mkt-ug19.bin", 0x600000, 0x80000, CRC(2d8c7ba1) SHA1(f891d6eb618dbf3e77f02e0f93da216e20571905) )
	739	ROM_LOAD( "mkt-ug20.bin", 0x680000, 0x80000, CRC(2f7e55d3) SHA1(bda6892ee6fcb46959e4d0892bbe7d9fc6072dd3) )
	740	ROM_LOAD( "mkt-ug22.bin", 0x700000, 0x80000, CRC(b537bb4e) SHA1(05a447deee2e89b49bdb3ca2161a021d7ec5f11e) )
	741
	742	ROM_LOAD( "mkt-uj19.bin", 0x900000, 0x80000, CRC(33b9b7a4) SHA1(e8ceca4c049e1f55d480a03ff793b595bd04d344) )
	743	ROM_LOAD( "mkt-uj20.bin", 0x980000, 0x80000, CRC(eae96df0) SHA1(b40532312ba61e4065abfd733dd0c93eecad48e9) )
	744	ROM_LOAD( "mkt-uj22.bin", 0xa00000, 0x80000, CRC(5e12523b) SHA1(468f93ef9bb6addb45c1c939d24b6511f255426a) )
	745	ROM_END
	746
	747
714	748	ROM_START( mk2 )
715	749	ROM_REGION16_LE( 0xc00000, "dcs", ROMREGION_ERASEFF ) /* sound data */
716	750	ROM_LOAD16_BYTE( "su2.l1", 0x000000, 0x80000, CRC(5f23d71d) SHA1(54c2afef243759e0f3dbe2907edbc4302f5c8bad) )
r5534	r5535
1278	1312
1279	1313	GAME( 1992, mk, 0, tunit_adpcm, mk, mktunit, ROT0, "Midway", "Mortal Kombat (rev 5.0 T-Unit 03/19/93)", GAME_SUPPORTS_SAVE )
1280	1314	GAME( 1992, mkr4, mk, tunit_adpcm, mk, mktunit, ROT0, "Midway", "Mortal Kombat (rev 4.0 T-Unit 02/11/93)", GAME_SUPPORTS_SAVE )
	1315	GAME( 1992, mkturbo, mk, tunit_adpcm, mk, mkturbo, ROT0, "Midway", "Mortal Kombat Turbo Ninja (rev 3.1 T-Unit 03/19/93, hack)", GAME_SUPPORTS_SAVE )
1281	1316
1282	1317	GAME( 1993, mk2, 0, tunit_dcs, mk2, mk2, ROT0, "Midway", "Mortal Kombat II (rev L3.1)", GAME_SUPPORTS_SAVE )
1283	1318	GAME( 1993, mk2r32, mk2, tunit_dcs, mk2, mk2, ROT0, "Midway", "Mortal Kombat II (rev L3.2 (European))", GAME_SUPPORTS_SAVE )

src/mame/drivers/niyanpai.c
r5534	r5535
783	783	MDRV_CPU_PROGRAM_MAP(niyanpai_map)
784	784	MDRV_CPU_VBLANK_INT("screen", niyanpai_interrupt)
785	785
786		MDRV_CPU_ADD("audiocpu", Z80, 8000000/1) /* TMPZ84C011, 8.00 MHz */
	786	MDRV_CPU_ADD("audiocpu", Z80, 8000000) /* TMPZ84C011, 8.00 MHz */
787	787	MDRV_CPU_CONFIG(daisy_chain_sound)
788	788	MDRV_CPU_PROGRAM_MAP(niyanpai_sound_map)
789	789	MDRV_CPU_IO_MAP(niyanpai_sound_io_map)
790	790
791		MDRV_Z80CTC_ADD("ctc", 8000000/1 /* same as "audiocpu" */, ctc_intf)
	791	MDRV_Z80CTC_ADD("ctc", 8000000 /* same as "audiocpu" */, ctc_intf)
792	792
793	793	MDRV_MACHINE_RESET(niyanpai)
794	794	MDRV_NVRAM_HANDLER(generic_0fill)

src/mame/drivers/tiamc1.c
r5534	r5535
6	6	special thanks to Shiru for his standalone emulator and documentation
7	7
8	8	Games supported:
	9	* Billiard
9	10	* Konek-Gorbunok
	11	* Snezhnaja Koroleva
10	12	* S.O.S.
11	13
12	14	Other games known to exist on this hardware (interchangeable by the ROM swap):
13	15	* Avtogonki
14		* Billiard
15	16	* Istrebitel'
16	17	* Kot-Rybolov
17	18	* Kotigoroshko
18	19	* Ostrov Drakona
19	20	* Ostrov Sokrovisch
20	21	* Perehvatchik
21		* Snezhnaja Koroleva
22	22	* Zvezdnyj Rycar'
23	23
24	24	***************************************************************
r5534	r5535
312	312
313	313	ROM_END
314	314
	315	ROM_START( bilyard )
	316	ROM_REGION( 0x10000, "maincpu", 0 )
	317	ROM_LOAD( "04.1g", 0x00000, 0x2000, CRC(a44f913d) SHA1(f01a0e931fb0f719bc7b3f1ca7802dd747c8a56f) )
	318	ROM_LOAD( "05.2g", 0x02000, 0x2000, CRC(6e41219f) SHA1(b09a16c9bd48b503ec0f2c636f021199d7ac7924) )
	319	ROM_FILL( 0x04000, 0x2000, 0x00 ) /* 06.3g is unpopulated */
	320	ROM_FILL( 0x06000, 0x2000, 0x00 ) /* 07.4g is unpopulated */
	321	ROM_FILL( 0x08000, 0x2000, 0x00 ) /* 08.5g is unpopulated */
	322	ROM_FILL( 0x0a000, 0x2000, 0x00 ) /* 09.6g is unpopulated */
	323	ROM_LOAD( "10.7g", 0x0c000, 0x2000, CRC(173adb85) SHA1(53f27b45e61365907e8996c283ae70ca5b498129) )
	324
	325	ROM_REGION( 0x8000, "gfx1", 0 )
	326	ROM_LOAD( "00.2a", 0x00000, 0x2000, CRC(6f72e043) SHA1(a60f66326ff0a55e2624231efcbceff700d9ceee) )
	327	ROM_LOAD( "01.3a", 0x02000, 0x2000, CRC(daddbbb5) SHA1(1460aebcbb57180e05930845703ff6325d85702a) )
	328	ROM_LOAD( "02.5a", 0x04000, 0x2000, CRC(3d744d33) SHA1(f1375098e81986715d0497b09df0c6622bd75b9a) )
	329	ROM_LOAD( "03.6a", 0x06000, 0x2000, CRC(8bfc0b15) SHA1(221efdce516274d3b1d9009d11dc9ed6cd67ef12) )
	330	ROM_END
	331
315	332	GAME( 1988, konek, 0, tiamc1, tiamc1, 0, ROT0, "Terminal", "Konek-Gorbunok", GAME_IMPERFECT_GRAPHICS \| GAME_SUPPORTS_SAVE )
316	333	GAME( 1988, sosterm, 0, tiamc1, tiamc1, 0, ROT0, "Terminal", "S.O.S.", GAME_IMPERFECT_GRAPHICS \| GAME_SUPPORTS_SAVE )
317	334	GAME( 1988, koroleva, 0, tiamc1, tiamc1, 0, ROT0, "Terminal", "Snezhnaja Koroleva", GAME_IMPERFECT_GRAPHICS \| GAME_SUPPORTS_SAVE )
	335	GAME( 1988, bilyard, 0, tiamc1, tiamc1, 0, ROT0, "Terminal", "Billiard", GAME_IMPERFECT_GRAPHICS \| GAME_SUPPORTS_SAVE )

src/mame/drivers/tmaster.c
r5534	r5535
105	105	#include "cpu/m68000/m68000.h"
106	106	#include "deprecat.h"
107	107	#include "sound/okim6295.h"
108		#include "machine/eeprom.h"
	108	#include "machine/eepromdev.h"
109	109	#include "machine/microtch.h"
110	110	#include "machine/68681.h"
111	111
r5534	r5535
212	212	Video & Blitter
213	213
214	214
215		Offset: Bits: Value:
	215	Offset: Bits: Value:
216	216
217		02
218		fedc ba-- ---- ----
	217	00
	218
	219	02 fedc ba-- ---- ----
219	220	---- --9- ---- ---- Layer 1 Buffer To Display
220	221	---- ---8 ---- ---- Layer 0 Buffer To Display
221	222	---- ---- 7654 3210
r5534	r5535
239	240	---- ---- ---- --1- Flip Y
240	241	---- ---- ---- ---0 Flip X
241	242
242		12 fedc ba98 ---- ---- Solid Fill Pen
	243	Addr Register:
	244
	245	fedc ba98 ---- ---- Solid Fill Pen
243	246	---- ---- 7654 3210 Source Address (high)
244	247
245		A write to the source address (high) triggers the blit.
	248	Color Register:
	249
	250	fedc ba98 ---- ---- Source Pen (Pen Replacement Mode)
	251	---- ---- 7654 3210 Palette (0-f) / Destination Pen (Pen Replacement Mode)
	252
	253	A write to the source address (mid) triggers the blit.
246	254	A the end of the blit, a level 2 IRQ is issued.
247	255
248	256	***************************************************************************/
r5534	r5535
251	259	static UINT16 *tmaster_regs;
252	260	static UINT16 tmaster_color;
253	261	static UINT16 tmaster_addr;
	262	static UINT32 tmaster_gfx_offs, tmaster_gfx_size;
254	263	static int (*compute_addr) (UINT16 reg_low, UINT16 reg_mid, UINT16 reg_high);
255	264
256	265	static int tmaster_compute_addr(UINT16 reg_low, UINT16 reg_mid, UINT16 reg_high)
r5534	r5535
299	308	#endif
300	309
301	310
302		if (layers_ctrl & 1) copybitmap (bitmap,tmaster_bitmap[0][(tmaster_regs[0x02/2]>>8)&1],0,0,0,0,cliprect);
303		else bitmap_fill(bitmap,cliprect,get_black_pen(screen->machine));
	311	bitmap_fill(bitmap,cliprect,get_black_pen(screen->machine));
304	312
305		if (layers_ctrl & 2) copybitmap_trans (bitmap,tmaster_bitmap[1][(tmaster_regs[0x02/2]>>9)&1],0,0,0,0,cliprect,0xff);
	313	if (layers_ctrl & 1) copybitmap_trans(bitmap, tmaster_bitmap[0][(tmaster_regs[0x02/2]>>8)&1], 0,0,0,0, cliprect, 0xff);
	314	if (layers_ctrl & 2) copybitmap_trans(bitmap, tmaster_bitmap[1][(tmaster_regs[0x02/2]>>9)&1], 0,0,0,0, cliprect, 0xff);
306	315
307	316	return 0;
308	317	}
r5534	r5535
310	319	static WRITE16_HANDLER( tmaster_color_w )
311	320	{
312	321	COMBINE_DATA( &tmaster_color );
313		#if 0
314		if (tmaster_color & ~7)
315		logerror("%06x: color %04x\n", cpu_get_pc(space->cpu), tmaster_color);
316		#endif
317	322	}
318	323
319	324	static WRITE16_HANDLER( tmaster_addr_w )
r5534	r5535
325	330	{
326	331	int x,y,x0,x1,y0,y1,dx,dy,flipx,flipy,sx,sy,sw,sh, addr, mode, layer,buffer, color;
327	332
328		UINT8 *gfxdata = memory_region( machine, "gfx1" );
329		size_t size = memory_region_length( machine, "gfx1" );
	333	UINT8 *gfxdata = memory_region( machine, "blitter" ) + tmaster_gfx_offs;
330	334
331		UINT16 ~~data~~;
	335	UINT16 pen;
332	336
333	337	bitmap_t *bitmap;
334	338
r5534	r5535
348	352
349	353	addr <<= 1;
350	354
	355	#ifdef MAME_DEBUG
351	356	#if 0
352		logerror("%s: blit w %03x, h %02x, x %03x, y %02x, addr %06x, mode %02x\n", cpuexec_describe_context(machine),
353		sw,sh,sx,sy, addr, mode
	357	logerror("%s: blit w %03x, h %02x, x %03x, y %02x, src %06x, fill/addr %04x, repl/color %04x, mode %02x\n", cpuexec_describe_context(machine),
	358	sw,sh,sx,sy, addr, tmaster_addr, tmaster_color, mode
354	359	);
355	360	#endif
	361	#endif
356	362
357	363	flipx = mode & 1;
358	364	flipy = mode & 2;
r5534	r5535
366	372	sx = (sx & 0x7fff) - (sx & 0x8000);
367	373	sy = (sy & 0x7fff) - (sy & 0x8000);
368	374
369		color = (tmaster_color & 7) << 8;
	375	color = (tmaster_color & 0x0f) << 8;
370	376
371	377	switch (mode & 0x20)
372	378	{
373	379	case 0x00: // blit with transparency
374		if (addr > size - sw*sh)
	380	if (addr > tmaster_gfx_size - sw*sh)
375	381	{
376	382	logerror("%s: blit error, addr %06x out of bounds\n", cpuexec_describe_context(machine),addr);
377		addr = size - sw*sh;
	383	addr = tmaster_gfx_size - sw*sh;
378	384	}
379	385
380		for (y = y0; ~~y != y1; y += dy~~)
	386	if ( mode & 0x200 )
381	387	{
382		for (x = x0; x != x1; x += dx)
	388	// copy from ROM, replacing occurrences of src pen with dst pen
	389
	390	UINT8 dst_pen = (tmaster_color >> 8) & 0xff;
	391	UINT8 src_pen = (tmaster_color >> 0) & 0xff;
	392
	393	for (y = y0; y != y1; y += dy)
383	394	{
384		data = gfxdata[addr++];
	395	for (x = x0; x != x1; x += dx)
	396	{
	397	pen = gfxdata[addr++];
385	398
386		if ((data != 0xff) && (sx + x >= 0) && (sx + x < 400) && (sy + y >= 0) && (sy + y < 256))
387		*BITMAP_ADDR16(bitmap, sy + y, sx + x) = data + color;
	399	if (pen == src_pen)
	400	pen = dst_pen;
	401
	402	if ((pen != 0xff) && (sx + x >= 0) && (sx + x < 400) && (sy + y >= 0) && (sy + y < 256))
	403	*BITMAP_ADDR16(bitmap, sy + y, sx + x) = pen + color;
	404	}
388	405	}
389	406	}
	407	else
	408	{
	409	// copy from ROM as is
	410
	411	for (y = y0; y != y1; y += dy)
	412	{
	413	for (x = x0; x != x1; x += dx)
	414	{
	415	pen = gfxdata[addr++];
	416
	417	if ((pen != 0xff) && (sx + x >= 0) && (sx + x < 400) && (sy + y >= 0) && (sy + y < 256))
	418	*BITMAP_ADDR16(bitmap, sy + y, sx + x) = pen + color;
	419	}
	420	}
	421	}
390	422	break;
391	423
392	424	case 0x20: // solid fill
393		data = ((tmaster_addr >> 8) & 0xff) + color;
	425	pen = ((tmaster_addr >> 8) & 0xff) + color;
	426
	427	if ((pen & 0xff) == 0xff)
	428	pen = 0xff;
	429
394	430	for (y = y0; y != y1; y += dy)
395	431	{
396	432	for (x = x0; x != x1; x += dx)
397	433	{
398	434	if ((sx + x >= 0) && (sx + x < 400) && (sy + y >= 0) && (sy + y < 256))
399		*BITMAP_ADDR16(bitmap, sy + y, sx + x) = ~~data~~;
	435	*BITMAP_ADDR16(bitmap, sy + y, sx + x) = pen;
400	436	}
401	437	}
402	438	break;
r5534	r5535
455	491
456	492	AM_RANGE( 0x580000, 0x580001 ) AM_WRITENOP // often
457	493
458		AM_RANGE( 0x600000, 0x600fff ) AM_READWRITE( SMH_RAM, paletteram16_xBBBBBGGGGGRRRRR_word_w ) AM_BASE(&paletteram16) ~~// looks like palettes, maybe~~
	494	AM_RANGE( 0x600000, 0x601fff ) AM_READWRITE( SMH_RAM, paletteram16_xBBBBBGGGGGRRRRR_word_w ) AM_BASE(&paletteram16)
459	495
460	496	AM_RANGE( 0x800000, 0x800001 ) AM_DEVREADWRITE8( "oki", okim6295_r, okim6295_w, 0x00ff )
461	497
r5534	r5535
467	503	Galaxy Games
468	504	***************************************************************************/
469	505
470		// NVRAM
	506	// ROM/RAM Banking
471	507
	508	#define GALGAMES_BANK_000000_R 1
	509	#define GALGAMES_BANK_000000_W 2
	510	#define GALGAMES_BANK_200000_R 3
	511	#define GALGAMES_BANK_200000_W 4
	512	#define GALGAMES_BANK_240000_R 5
	513
	514	#define GALGAMES_RAM 0
	515	#define GALGAMES_ROM0 1
	516	#define GALGAMES_ROM1 2
	517	#define GALGAMES_ROM2 3
	518	#define GALGAMES_ROM3 4
	519
	520	static UINT16 *galgames_ram;
	521	static UINT16 galgames_cart;
	522
	523	// NVRAM (5 x EEPROM)
	524
472	525	static const eeprom_interface galgames_eeprom_interface =
473	526	{
474	527	10, // address bits 10
r5534	r5535
482	535	1 // reset_delay
483	536	};
484	537
	538	#define GALGAMES_EEPROM_BIOS "eeprom_bios"
	539	#define GALGAMES_EEPROM_CART1 "eeprom_cart1"
	540	#define GALGAMES_EEPROM_CART2 "eeprom_cart2"
	541	#define GALGAMES_EEPROM_CART3 "eeprom_cart3"
	542	#define GALGAMES_EEPROM_CART4 "eeprom_cart4"
	543
	544	const char const *galgames_eeprom_names[5] = { GALGAMES_EEPROM_BIOS, GALGAMES_EEPROM_CART1, GALGAMES_EEPROM_CART2, GALGAMES_EEPROM_CART3, GALGAMES_EEPROM_CART4 };
	545
485	546	static READ16_HANDLER( galgames_eeprom_r )
486	547	{
487		return eeprom_read_bit() ? 0x80 : 0x00;
	548	const device_config *eeprom = devtag_get_device(space->machine, galgames_eeprom_names[galgames_cart]);
	549
	550	return eepromdev_read_bit(eeprom) ? 0x80 : 0x00;
488	551	}
489	552
490	553	static WRITE16_HANDLER( galgames_eeprom_w )
r5534	r5535
494	557
495	558	if ( ACCESSING_BITS_0_7 )
496	559	{
	560	const device_config *eeprom = devtag_get_device(space->machine, galgames_eeprom_names[galgames_cart]);
	561
497	562	// latch the bit
498		eeprom_write_bit(data & 0x0001);
	563	eepromdev_write_bit(eeprom, data & 0x0001);
499	564
500	565	// clock line asserted: write latch or select next bit to read
501		eeprom_set_clock_line((data & 0x0002) ? ASSERT_LINE : CLEAR_LINE );
	566	eepromdev_set_clock_line(eeprom, (data & 0x0002) ? ASSERT_LINE : CLEAR_LINE );
502	567	}
503	568	}
504	569
505		static NVRAM_HANDLER( galgames )
506		{
507		if (read_or_write)
508		eeprom_save(file);
509		else
510		{
511		eeprom_init(machine, &galgames_eeprom_interface);
512		if (file) eeprom_load(file);
513		}
514		}
515
516	570	// BT481A Palette RAMDAC
517	571	static UINT32 palette_offset;
518	572	static UINT8 palette_index;
r5534	r5535
533	587	palette_data[palette_index] = data & 0xff;
534	588	if (++palette_index == 3)
535	589	{
536		palette_set_color(space->machine, palette_offset, MAKE_RGB(palette_data[0], palette_data[1], palette_data[2]));
	590	int palette_base;
	591	for (palette_base = 0; palette_base < 0x1000; palette_base += 0x100)
	592	palette_set_color(space->machine, palette_offset + palette_base, MAKE_RGB(palette_data[0], palette_data[1], palette_data[2]));
537	593	palette_index = 0;
538	594	palette_offset++;
539	595	}
r5534	r5535
551	607	memory_region(space->machine, "oki")[offset] = data & 0xff;
552	608	}
553	609
	610	// Carts (preliminary, PIC communication is not implemented)
554	611
555		// Carts communication (preliminary, no cart is dumped yet)
	612	static void galgames_update_rombank(running_machine *machine, UINT32 cart)
	613	{
	614	galgames_cart = cart;
556	615
	616	tmaster_gfx_offs = 0x200000 * cart;
	617
	618	if (memory_get_bank(machine, GALGAMES_BANK_000000_R) == GALGAMES_RAM)
	619	memory_set_bank(machine, GALGAMES_BANK_200000_R, GALGAMES_ROM0 + galgames_cart); // rom
	620
	621	memory_set_bank(machine, GALGAMES_BANK_240000_R, GALGAMES_ROM0 + galgames_cart); // rom
	622	}
	623
557	624	static WRITE16_HANDLER( galgames_cart_sel_w )
558	625	{
559	626	// cart selection (0 1 2 3 4 7)
560	627
561		// 7 resets the eeprom
562	628	if (ACCESSING_BITS_0_7)
563		eeprom_set_cs_line(((data&0xff) == 0x07) ? ASSERT_LINE : CLEAR_LINE);
	629	{
	630	int i;
	631
	632	switch( data & 0xff )
	633	{
	634	case 0x07: // 7 resets the eeprom
	635	for (i = 0; i < 5; i++)
	636	eepromdev_set_cs_line(devtag_get_device(space->machine, galgames_eeprom_names[i]), ASSERT_LINE);
	637	break;
	638
	639	case 0x00:
	640	case 0x01:
	641	case 0x02:
	642	case 0x03:
	643	case 0x04:
	644	eepromdev_set_cs_line(devtag_get_device(space->machine, galgames_eeprom_names[data & 0xff]), CLEAR_LINE);
	645	galgames_update_rombank(space->machine, data & 0xff);
	646	break;
	647
	648	default:
	649	eepromdev_set_cs_line(devtag_get_device(space->machine, galgames_eeprom_names[0]), CLEAR_LINE);
	650	galgames_update_rombank(space->machine, 0);
	651	logerror("%06x: unknown cart sel = %04x\n", cpu_get_pc(space->cpu), data);
	652	break;
	653	}
	654	}
564	655	}
565	656
566	657	static READ16_HANDLER( galgames_cart_clock_r )
r5534	r5535
577	668	// ROM/RAM banking
578	669	if ((data & 0xf7) == 0x05)
579	670	{
580		memory_set_bank(space->machine, 1, 1); // ram
581		memory_set_bank(space->machine, 3, 0); // rom
	671	memory_set_bank(space->machine, GALGAMES_BANK_000000_R, GALGAMES_RAM); // ram
	672	galgames_update_rombank(space->machine, galgames_cart);
582	673	logerror("%06x: romram bank = %04x\n", cpu_get_pc(space->cpu), data);
583	674	}
584	675	else
585	676	{
586		memory_set_bank(space->machine, 1, 0); // rom
	677	memory_set_bank(space->machine, GALGAMES_BANK_000000_R, GALGAMES_ROM0); // rom
	678	memory_set_bank(space->machine, GALGAMES_BANK_200000_R, GALGAMES_RAM); // ram
587	679	logerror("%06x: unknown romram bank = %04x\n", cpu_get_pc(space->cpu), data);
588	680	}
589	681	}
r5534	r5535
605	697
606	698	static ADDRESS_MAP_START( galgames_map, ADDRESS_SPACE_PROGRAM, 16 )
607	699
608		AM_RANGE( 0x000000, 0x03ffff ) AM_READWRITE(SMH_BANK(1), SMH_BANK(2))
609		AM_RANGE( 0x040000, 0x1fffff ) AM_ROM AM_REGION( "maincpu", 0 )
610		AM_RANGE( 0x200000, 0x23ffff ) AM_READWRITE(SMH_BANK(3), SMH_BANK(4))
611		AM_RANGE( 0x240000, 0x3fffff ) AM_ROM AM_REGION( "maincpu", 0 )
	700	AM_RANGE( 0x000000, 0x03ffff ) AM_READWRITE(SMH_BANK(GALGAMES_BANK_000000_R), SMH_BANK(GALGAMES_BANK_000000_W)) AM_BASE( &galgames_ram )
	701	AM_RANGE( 0x040000, 0x1fffff ) AM_ROM AM_REGION( "maincpu", 0x40000 )
	702	AM_RANGE( 0x200000, 0x23ffff ) AM_READWRITE(SMH_BANK(GALGAMES_BANK_200000_R), SMH_BANK(GALGAMES_BANK_200000_W))
	703	AM_RANGE( 0x240000, 0x3fffff ) AM_READ(SMH_BANK(GALGAMES_BANK_240000_R))
612	704
613	705	AM_RANGE( 0x400000, 0x400011 ) AM_WRITE( tmaster_blitter_w ) AM_BASE( &tmaster_regs )
614	706	AM_RANGE( 0x400012, 0x400013 ) AM_WRITE( tmaster_addr_w )
r5534	r5535
753	845
754	846	static MACHINE_RESET( tmaster )
755	847	{
	848	tmaster_gfx_offs = 0;
	849	tmaster_gfx_size = memory_region_length(machine, "blitter");
	850
756	851	tmaster_devices.duart68681 = devtag_get_device( machine, "duart68681" );
757	852	}
758	853
r5534	r5535
787	882
788	883	MDRV_NVRAM_HANDLER(generic_0fill)
789	884
790
791	885	MDRV_SCREEN_ADD("screen", RASTER)
792	886	MDRV_SCREEN_REFRESH_RATE(60)
793	887	MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
r5534	r5535
795	889	MDRV_SCREEN_SIZE(400, 256)
796	890	MDRV_SCREEN_VISIBLE_AREA(0, 400-1, 0, 256-1)
797	891
798		MDRV_PALETTE_LENGTH(0x800)
	892	MDRV_PALETTE_LENGTH(0x1000)
799	893
800	894	MDRV_VIDEO_START(tmaster)
801	895	MDRV_VIDEO_UPDATE(tmaster)
r5534	r5535
829	923
830	924	static MACHINE_RESET( galgames )
831	925	{
832		memory_set_bank(machine, 1, 0); // rom
833		memory_set_bank(machine, 3, 1); // ram
	926	tmaster_gfx_offs = 0;
	927	tmaster_gfx_size = 0x200000;
834	928
835		memory_set_bank(machine, 2, 0); // ram
836		memory_set_bank(machine, 4, 0); // ram
	929	memory_set_bank(machine, GALGAMES_BANK_000000_R, GALGAMES_ROM0); // rom
	930	memory_set_bank(machine, GALGAMES_BANK_000000_W, GALGAMES_RAM); // ram
837	931
	932	memory_set_bank(machine, GALGAMES_BANK_200000_R, GALGAMES_RAM); // ram
	933	memory_set_bank(machine, GALGAMES_BANK_200000_W, GALGAMES_RAM); // ram
	934
	935	memory_set_bank(machine, GALGAMES_BANK_240000_R, GALGAMES_ROM0); // rom
	936
	937	galgames_update_rombank(machine, 0);
	938
838	939	device_reset(cputag_get_cpu(machine, "maincpu"));
839	940	}
840	941
	942	UINT8 *galgames_eeprom_data = NULL;
	943
841	944	static MACHINE_DRIVER_START( galgames )
842	945	MDRV_CPU_ADD("maincpu", M68000, XTAL_24MHz / 2)
843	946	MDRV_CPU_PROGRAM_MAP(galgames_map)
844	947	MDRV_CPU_VBLANK_INT_HACK(galgames_interrupt, 1+20) // ??
845	948
846		MDRV_NVRAM_HANDLER( galgames )
	949	// 5 EEPROMs on the motherboard (for BIOS + 4 Carts)
	950	MDRV_EEPROM_ADD(GALGAMES_EEPROM_BIOS, galgames_eeprom_interface, 0, galgames_eeprom_data)
	951	MDRV_EEPROM_ADD(GALGAMES_EEPROM_CART1, galgames_eeprom_interface, 0, galgames_eeprom_data)
	952	MDRV_EEPROM_ADD(GALGAMES_EEPROM_CART2, galgames_eeprom_interface, 0, galgames_eeprom_data)
	953	MDRV_EEPROM_ADD(GALGAMES_EEPROM_CART3, galgames_eeprom_interface, 0, galgames_eeprom_data)
	954	MDRV_EEPROM_ADD(GALGAMES_EEPROM_CART4, galgames_eeprom_interface, 0, galgames_eeprom_data)
	955
847	956	MDRV_MACHINE_RESET( galgames )
848	957
849	958	/* video hardware */
r5534	r5535
854	963	MDRV_SCREEN_SIZE(400, 256)
855	964	MDRV_SCREEN_VISIBLE_AREA(0, 400-1, 0, 256-1)
856	965
857		MDRV_PALETTE_LENGTH(0x800) // only 0x100 used
	966	MDRV_PALETTE_LENGTH(0x1000) // only 0x100 used
858	967
859	968	MDRV_VIDEO_START(galgames)
860	969	MDRV_VIDEO_UPDATE(tmaster)
r5534	r5535
867	976	MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
868	977	MACHINE_DRIVER_END
869	978
	979	/*
	980	Each cartridge contains a PIC, that should provide, among other things, the following header:
	981
	982	4345 5331 3939 3700 0c10 ffb3 3c00 0000 "CES1997"
	983	fffe f2f7 8557 c119 0000 0000 2340 188e
	984	*/
	985	static MACHINE_DRIVER_START( galgame2 )
	986	MDRV_IMPORT_FROM(galgames)
	987	// MDRV_CPU_ADD("pic", PIC12C508, XTAL_24MHz / 2)
	988	MACHINE_DRIVER_END
	989
	990
870	991	/***************************************************************************
871	992
872	993	ROMs Loading
r5534	r5535
894	1015	ROM_LOAD16_BYTE( "tmaster.u51", 0x000000, 0x080000, CRC(edaa5874) SHA1(48b99bc7f5a6453def265967ca7d8eefdf9dc97b) ) /* Ver: 3.00 Euro 11-25-96 */
895	1016	ROM_LOAD16_BYTE( "tmaster.u52", 0x000001, 0x080000, CRC(e9fd30fc) SHA1(d91ea05d5f574603883336729fb9df705688945d) ) /* Ver: 3.00 Euro 11-25-96 */
896	1017
897		ROM_REGION( 0x400000, "~~gfx1~~", ROMREGION_ERASE ) // Blitter gfx
	1018	ROM_REGION( 0x400000, "blitter", ROMREGION_ERASE ) // Blitter gfx
898	1019	ROM_LOAD16_BYTE( "tmaster.u38", 0x100000, 0x080000, CRC(68885ef6) SHA1(010602b59c33c3e490491a296ddaf8952e315b83) )
899	1020	ROM_LOAD16_BYTE( "tmaster.u36", 0x100001, 0x080000, CRC(204096ec) SHA1(9239923b7eedb6003c63ef2e8ff224edee657bbc) )
900	1021	// unused gap
r5534	r5535
933	1054	ROM_LOAD16_BYTE( "tm2k_v402.u51", 0x000000, 0x100000, CRC(fa6d168c) SHA1(c458d1114c658ac963a22cdb74ee5ea489ddcbba) ) /* Ver: 4.02 Standard 5-30-97 */
934	1055	ROM_LOAD16_BYTE( "tm2k_v402.u52", 0x000001, 0x100000, CRC(4e9c2d42) SHA1(67e34778f21010c43c1247179faa3f7ede5ad8d0) ) /* Ver: 4.02 Standard 5-30-97 */
935	1056
936		ROM_REGION( 0x400000, "~~gfx1~~", ROMREGION_ERASE ) // Blitter gfx
	1057	ROM_REGION( 0x400000, "blitter", ROMREGION_ERASE ) // Blitter gfx
937	1058	ROM_LOAD16_BYTE( "tm2k_graphic.u38", 0x100000, 0x080000, CRC(22bb6cc5) SHA1(fc6cfd4e1e6e1455d648a7b63f2c8e37cdfe86d6) )
938	1059	ROM_LOAD16_BYTE( "tm2k_graphic.u36", 0x100001, 0x080000, CRC(7f0840ac) SHA1(1c3af419d571579a3f2c561617d55914d28ef22b) )
939	1060	ROM_LOAD16_BYTE( "tm2k_graphic.u39", 0x300000, 0x080000, CRC(059e1bd8) SHA1(7451c1cfa0d090b0566e353738a1ffba732a8ad2) )
r5534	r5535
989	1110	ROM_LOAD16_BYTE( "tm3k_v502.u51", 0x000000, 0x100000, CRC(6267e2bd) SHA1(c81e5cd059a9ad2f6a36261738e39740a1a3a03f) ) /* TOUCHMASTER 3000 U51 DOMESTIC 5.02 (Standard 11-17-97) (yellow label) */
990	1111	ROM_LOAD16_BYTE( "tm3k_v502.u52", 0x000001, 0x100000, CRC(836fdf1e) SHA1(2ee9c0929950afb72f172b253d6c392e9a698037) ) /* TOUCHMASTER 3000 U52 DOMESTIC 5.02 (Standard 11-17-97) (yellow label) */
991	1112
992		ROM_REGION( 0x600000, "~~gfx1~~", 0 ) // Blitter gfx
	1113	ROM_REGION( 0x600000, "blitter", 0 ) // Blitter gfx
993	1114	ROM_LOAD16_BYTE( "tm3k_graphic.u38", 0x000000, 0x100000, CRC(a6683899) SHA1(d05024390917cdb1871d030996da8e1eb6460918) ) /* Labeled TOUCHMASTER U38 STANDARD 5.0 (pink label) */
994	1115	ROM_LOAD16_BYTE( "tm3k_graphic.u36", 0x000001, 0x100000, CRC(7bde520d) SHA1(77750b689e2f0d47804042456e54bbd9c28deeac) ) /* Labeled TOUCHMASTER U36 STANDARD 5.0 (pink label) */
995	1116	ROM_LOAD16_BYTE( "tm3k_graphic.u39", 0x200000, 0x100000, CRC(206b56a6) SHA1(09e5e05bffd0a09abd24d668e2c59b56f2c79134) ) /* Labeled TOUCHMASTER U39 STANDARD 5.0 (pink label) */
r5534	r5535
1006	1127	ROM_LOAD16_BYTE( "tm3k_v501.u51", 0x000000, 0x100000, CRC(c9522279) SHA1(e613b791f831271722f05b7e96c35519fa9fc174) ) /* TOUCHMASTER 3000 U51 DOMESTIC 5.01 (Standard 11-4-97) (yellow label) */
1007	1128	ROM_LOAD16_BYTE( "tm3k_v501.u52", 0x000001, 0x100000, CRC(8c6a0db7) SHA1(6b0eae60ea471cd8c4001749ac2677d8d4532567) ) /* TOUCHMASTER 3000 U52 DOMESTIC 5.01 (Standard 11-4-97) (yellow label) */
1008	1129
1009		ROM_REGION( 0x600000, "~~gfx1~~", 0 ) // Blitter gfx
	1130	ROM_REGION( 0x600000, "blitter", 0 ) // Blitter gfx
1010	1131	ROM_LOAD16_BYTE( "tm3k_graphic.u38", 0x000000, 0x100000, CRC(a6683899) SHA1(d05024390917cdb1871d030996da8e1eb6460918) ) /* Labeled TOUCHMASTER U38 STANDARD 5.0 (pink label) */
1011	1132	ROM_LOAD16_BYTE( "tm3k_graphic.u36", 0x000001, 0x100000, CRC(7bde520d) SHA1(77750b689e2f0d47804042456e54bbd9c28deeac) ) /* Labeled TOUCHMASTER U36 STANDARD 5.0 (pink label) */
1012	1133	ROM_LOAD16_BYTE( "tm3k_graphic.u39", 0x200000, 0x100000, CRC(206b56a6) SHA1(09e5e05bffd0a09abd24d668e2c59b56f2c79134) ) /* Labeled TOUCHMASTER U39 STANDARD 5.0 (pink label) */
r5534	r5535
1052	1173	ROM_LOAD16_BYTE( "tm4k_v602.u51", 0x000000, 0x100000, CRC(3d8d7848) SHA1(31638f23cdd5e6cfbb2270e953f84fe1bd437950) ) /* TOUCHMASTER 4000 U51 DOMESTIC 6.02 (Standard 4-14-98) */
1053	1174	ROM_LOAD16_BYTE( "tm4k_v602.u52", 0x000001, 0x100000, CRC(6d412871) SHA1(ae27c7723b292daf6682c53bafac22e4a3cd1ece) ) /* TOUCHMASTER 4000 U52 DOMESTIC 6.02 (Standard 4-14-98) */
1054	1175
1055		ROM_REGION( 0x600000, "~~gfx1~~", 0 ) // Blitter gfx
	1176	ROM_REGION( 0x600000, "blitter", 0 ) // Blitter gfx
1056	1177	ROM_LOAD16_BYTE( "tm4k_graphic.u38", 0x000000, 0x100000, CRC(a6683899) SHA1(d05024390917cdb1871d030996da8e1eb6460918) ) /* Mask rom labeled 5341-15746-03 U38 VIDEO IMAGE */
1057	1178	ROM_LOAD16_BYTE( "tm4k_graphic.u36", 0x000001, 0x100000, CRC(7bde520d) SHA1(77750b689e2f0d47804042456e54bbd9c28deeac) ) /* Mask rom labeled 5341-15746-01 U36 VIDEO IMAGE */
1058	1179	ROM_LOAD16_BYTE( "tm4k_graphic.u39", 0x200000, 0x100000, CRC(bac88cfb) SHA1(26ed169296b890c5f5b50c418c15299355a6592f) ) /* Mask rom labeled 5341-15746-04 U39 VIDEO IMAGE */
r5534	r5535
1097	1218	ROM_LOAD16_BYTE( "tm5k_v7_10.u51", 0x000000, 0x100000, CRC(df0bd25e) SHA1(db1a197ed4c868743397f3823f3f1d42b9329f80) ) /* TOUCHMASTER 5000 U51 DOMESTIC 7.10 (Standard 10-9-98) (tan label) */
1098	1219	ROM_LOAD16_BYTE( "tm5k_v7_10.u52", 0x000001, 0x100000, CRC(ddf9e8dc) SHA1(3228f2eba067bdf1bd639116bffc589585ea3e72) ) /* TOUCHMASTER 5000 U52 DOMESTIC 7.10 (Standard 10-9-98) (tan label) */
1099	1220
1100		ROM_REGION( 0x600000, "~~gfx1~~", 0 ) // Blitter gfx
	1221	ROM_REGION( 0x600000, "blitter", 0 ) // Blitter gfx
1101	1222	ROM_LOAD16_BYTE( "tm5k_graphic.u38", 0x000000, 0x100000, CRC(93038e7c) SHA1(448f69bf51ac992f6b35b471cba9675c67984cd7) ) /* Mask rom labeled 5341-15951-07 U38 VIDEO IMAGE */
1102	1223	ROM_LOAD16_BYTE( "tm5k_graphic.u36", 0x000001, 0x100000, CRC(5453a44a) SHA1(094439a56336ca933b0b7ede8c057546d1d490b2) ) /* Mask rom labeled 5341-15951-06 U36 VIDEO IMAGE */
1103	1224	ROM_LOAD16_BYTE( "tm5k_graphic.u39", 0x200000, 0x100000, CRC(1349fdc7) SHA1(5118983be584455320f0d6006133f38e6a8ee0d8) ) /* Mask rom labeled 5341-15951-05 U39 VIDEO IMAGE */
r5534	r5535
1114	1235	ROM_LOAD16_BYTE( "tm5kca_v7_10.u51", 0x000000, 0x100000, CRC(7c03708f) SHA1(e1f8198bc03c1f9d2a00662b589fd66fdcc7a2de) ) /* TOUCHMASTER 5000 U51 CALIFORNIA 7.10 (CA. 10-9-98) (tan label) */
1115	1236	ROM_LOAD16_BYTE( "tm5kca_v7_10.u52", 0x000001, 0x100000, CRC(f1413295) SHA1(ad6b57c590bdae063b0e4a1abcb3b13ee52cd6db) ) /* TOUCHMASTER 5000 U52 CALIFORNIA 7.10 (CA. 10-9-98) (tan label) */
1116	1237
1117		ROM_REGION( 0x600000, "~~gfx1~~", 0 ) // Blitter gfx
	1238	ROM_REGION( 0x600000, "blitter", 0 ) // Blitter gfx
1118	1239	ROM_LOAD16_BYTE( "tm5k_graphic.u38", 0x000000, 0x100000, CRC(93038e7c) SHA1(448f69bf51ac992f6b35b471cba9675c67984cd7) ) /* Mask rom labeled 5341-15951-07 U38 VIDEO IMAGE */
1119	1240	ROM_LOAD16_BYTE( "tm5k_graphic.u36", 0x000001, 0x100000, CRC(5453a44a) SHA1(094439a56336ca933b0b7ede8c057546d1d490b2) ) /* Mask rom labeled 5341-15951-06 U36 VIDEO IMAGE */
1120	1241	ROM_LOAD16_BYTE( "tm5k_graphic.u39", 0x200000, 0x100000, CRC(1349fdc7) SHA1(5118983be584455320f0d6006133f38e6a8ee0d8) ) /* Mask rom labeled 5341-15951-05 U39 VIDEO IMAGE */
r5534	r5535
1131	1252	ROM_LOAD16_BYTE( "tm5k_v7_01.u51", 0x000000, 0x100000, CRC(3ff68213) SHA1(ec4939899a69f56d2437c806fdd0a5b50e58ec6a) ) /* TOUCHMASTER 5000 U51 DOMESTIC 7.01 (Standard 8-21-98) (pink label) */
1132	1253	ROM_LOAD16_BYTE( "tm5k_v7_01.u52", 0x000001, 0x100000, CRC(b3de607c) SHA1(4ede5b8c50177d1934a3b93d311a240ef354c450) ) /* TOUCHMASTER 5000 U52 DOMESTIC 7.01 (Standard 8-21-98) (pink label) */
1133	1254
1134		ROM_REGION( 0x600000, "~~gfx1~~", 0 ) // Blitter gfx
	1255	ROM_REGION( 0x600000, "blitter", 0 ) // Blitter gfx
1135	1256	ROM_LOAD16_BYTE( "tm5k_graphic.u38", 0x000000, 0x100000, CRC(93038e7c) SHA1(448f69bf51ac992f6b35b471cba9675c67984cd7) ) /* Mask rom labeled 5341-15951-07 U38 VIDEO IMAGE */
1136	1257	ROM_LOAD16_BYTE( "tm5k_graphic.u36", 0x000001, 0x100000, CRC(5453a44a) SHA1(094439a56336ca933b0b7ede8c057546d1d490b2) ) /* Mask rom labeled 5341-15951-06 U36 VIDEO IMAGE */
1137	1258	ROM_LOAD16_BYTE( "tm5k_graphic.u39", 0x200000, 0x100000, CRC(1349fdc7) SHA1(5118983be584455320f0d6006133f38e6a8ee0d8) ) /* Mask rom labeled 5341-15951-05 U39 VIDEO IMAGE */
r5534	r5535
1179	1300	ROM_LOAD16_BYTE( "tm7k_v804.u51", 0x000000, 0x100000, CRC(2461af04) SHA1(9cf37c04db0297ff8f9f316fd476d6d5d1c39acf) ) /* TOUCHMASTER 7000 U51 DOMESTIC 8.04 (Standard 06/02/99) (orange label) */
1180	1301	ROM_LOAD16_BYTE( "tm7k_v804.u52", 0x000001, 0x100000, CRC(5d39fad2) SHA1(85e8d110b88e1099117ab7963eaee47dc86ec7c5) ) /* TOUCHMASTER 7000 U52 DOMESTIC 8.04 (Standard 06/02/99) (orange label) */
1181	1302
1182		ROM_REGION( 0x600000, "~~gfx1~~", 0 ) // Blitter gfx
	1303	ROM_REGION( 0x600000, "blitter", 0 ) // Blitter gfx
1183	1304	ROM_LOAD16_BYTE( "tm7k_graphic.u38", 0x000000, 0x100000, CRC(93038e7c) SHA1(448f69bf51ac992f6b35b471cba9675c67984cd7) ) /* Mask rom labeled 5341-16262-07 U38 VIDEO IMAGE */
1184	1305	ROM_LOAD16_BYTE( "tm7k_graphic.u36", 0x000001, 0x100000, CRC(5453a44a) SHA1(094439a56336ca933b0b7ede8c057546d1d490b2) ) /* Mask rom labeled 5341-16262-06 U36 VIDEO IMAGE */
1185	1306	ROM_LOAD16_BYTE( "tm7k_graphic.u39", 0x200000, 0x100000, CRC(26af8da8) SHA1(02555b1597a4962f1fd0c3ffc89e5c8338aa3085) ) /* Mask rom labeled 5341-16262-05 U39 VIDEO IMAGE */
r5534	r5535
1196	1317	ROM_LOAD16_BYTE( "tm7k_v800.u51", 0x000000, 0x100000, CRC(83ec3da7) SHA1(37fa7183e7acc2eab35ac431d99cbbfe4862979e) ) /* TOUCHMASTER 7000 U51 DOMESTIC 8.00 (Standard 03/26/99) (orange label) */
1197	1318	ROM_LOAD16_BYTE( "tm7k_v800.u52", 0x000001, 0x100000, CRC(e2004282) SHA1(aa73029f31e2062cabedfcd778db97b314624ae8) ) /* TOUCHMASTER 7000 U52 DOMESTIC 8.00 (Standard 03/26/99) (orange label) */
1198	1319
1199		ROM_REGION( 0x600000, "~~gfx1~~", 0 ) // Blitter gfx
	1320	ROM_REGION( 0x600000, "blitter", 0 ) // Blitter gfx
1200	1321	ROM_LOAD16_BYTE( "tm7k_graphic.u38", 0x000000, 0x100000, CRC(93038e7c) SHA1(448f69bf51ac992f6b35b471cba9675c67984cd7) ) /* Labeled GRAPHIC U38 8.0 (orange label) */
1201	1322	ROM_LOAD16_BYTE( "tm7k_graphic.u36", 0x000001, 0x100000, CRC(5453a44a) SHA1(094439a56336ca933b0b7ede8c057546d1d490b2) ) /* Labeled GRAPHIC U36 8.0 (orange label) */
1202	1323	ROM_LOAD16_BYTE( "tm7k_graphic.u39", 0x200000, 0x100000, CRC(26af8da8) SHA1(02555b1597a4962f1fd0c3ffc89e5c8338aa3085) ) /* Labeled GRAPHIC U39 8.0 (orange label) */
r5534	r5535
1213	1334	ROM_LOAD16_BYTE( "tm7k_v81x.u51", 0x000000, 0x100000, CRC(57c88287) SHA1(1008bbcd137ede321be4cc2ad22e3982d880471b) ) /* TOUCHMASTER 7000 U51 8.1X (ASI Standard 03/08/99) (white label) */
1214	1335	ROM_LOAD16_BYTE( "tm7k_v81x.u52", 0x000001, 0x100000, CRC(e45d69bb) SHA1(9e8a42924a9cd573cbd2f3164d0fb468eee7ff51) ) /* TOUCHMASTER 7000 U52 8.1X (ASI Standard 03/08/99) (white label) */
1215	1336
1216		ROM_REGION( 0x600000, "~~gfx1~~", 0 ) // Blitter gfx
	1337	ROM_REGION( 0x600000, "blitter", 0 ) // Blitter gfx
1217	1338	ROM_LOAD16_BYTE( "tm7k_graphic.u38", 0x000000, 0x100000, CRC(93038e7c) SHA1(448f69bf51ac992f6b35b471cba9675c67984cd7) ) /* TOUCHMASTER EDCE V8.X U38 (white label) */
1218	1339	ROM_LOAD16_BYTE( "tm7k_graphic.u36", 0x000001, 0x100000, CRC(5453a44a) SHA1(094439a56336ca933b0b7ede8c057546d1d490b2) ) /* TOUCHMASTER DB7F V8.X U36 (white label) */
1219	1340	ROM_LOAD16_BYTE( "tm7k_graphic.u39", 0x200000, 0x100000, CRC(26af8da8) SHA1(02555b1597a4962f1fd0c3ffc89e5c8338aa3085) ) /* TOUCHMASTER 2BB6 V8.X U39 (white label) */
r5534	r5535
1258	1379	ROM_LOAD16_BYTE( "tm8k_v904.u51", 0x000000, 0x100000, CRC(28864ec8) SHA1(e703f9ee350dd915102e784bbd04445a95b7d0a5) ) /* TOUCHMASTER 8000 U51 DOMESTIC 9.04 (Standard 04/25/00) */
1259	1380	ROM_LOAD16_BYTE( "tm8k_v904.u52", 0x000001, 0x100000, CRC(c123eec2) SHA1(3e9c84755b18a4fd900068f385ee47107771391d) ) /* TOUCHMASTER 8000 U52 DOMESTIC 9.04 (Standard 04/25/00) */
1260	1381
1261		ROM_REGION( 0x600000, "~~gfx1~~", 0 ) // Blitter gfx
	1382	ROM_REGION( 0x600000, "blitter", 0 ) // Blitter gfx
1262	1383	ROM_LOAD16_BYTE( "tm8k_graphic.u38", 0x000000, 0x100000, CRC(2a971d46) SHA1(6ca4067e9fa40053df415e670b2e853915319dbb) ) /* Mask rom labeled 5341-16513-07 U38 VIDEO IMAGE */
1263	1384	ROM_LOAD16_BYTE( "tm8k_graphic.u36", 0x000001, 0x100000, CRC(3bde285e) SHA1(87bf60034665542fb0240b7479adfffb7ba9fad7) ) /* Mask rom labeled 5341-16513-06 U36 VIDEO IMAGE */
1264	1385	ROM_LOAD16_BYTE( "tm8k_graphic.u39", 0x200000, 0x100000, CRC(58c6c1d8) SHA1(cc11863c4ea46bde7ea4775075f4328be6d6c6d1) ) /* Mask rom labeled 5341-16513-05 U39 VIDEO IMAGE */
r5534	r5535
1283	1404
1284	1405	----
1285	1406
1286		Board silkscreend 237-0211-00
1287		REV.-D
	1407	Board silkscreened 237-0211-00
	1408	REV.-D
1288	1409
1289	1410	Cartridge based mother board
1290	1411	Holds up to 4 cartridges
r5534	r5535
1292	1413	GALAXY U1 V1.90 12/1/98
1293	1414	GALAXY U2 V1.90 12/1/98
1294	1415
1295		NAMCO 307 Cartridge has surface mount Flash chips in it (not dumped).
1296
1297	1416	Motorola MC68HC000FN12
1298	1417	24 MHz oscillator
1299	1418	Xilinx XC5206
r5534	r5535
1310	1429
1311	1430	***************************************************************************/
1312	1431
	1432	#define GALGAMES_BIOS_ROMS \
	1433	ROM_SYSTEM_BIOS( 0, "0", "v1.90" ) \
	1434	ROMX_LOAD( "galaxy.u2", 0x000000, 0x100000, CRC(e51ff184) SHA1(aaa795f2c15ec29b3ceeb5c917b643db0dbb7083), ROM_SKIP(1) \| ROM_BIOS(1) ) \
	1435	ROMX_LOAD( "galaxy.u1", 0x000001, 0x100000, CRC(c6d7bc6d) SHA1(93c032f9aa38cbbdda59a8a25ff9f38f7ad9c760), ROM_SKIP(1) \| ROM_BIOS(1) )
	1436
	1437	#define GALGAMES_MB_PALS \
	1438	ROM_REGION( 0xa00, "pals", 0) \
	1439	ROM_LOAD( "16v8h-blue.u24", 0x000, 0x117, NO_DUMP ) \
	1440	ROM_LOAD( "16v8h-yellow.u25", 0x200, 0x117, NO_DUMP ) \
	1441	ROM_LOAD( "16v8h-magenta.u26", 0x400, 0x117, NO_DUMP ) \
	1442	ROM_LOAD( "16v8h-green.u27", 0x600, 0x117, NO_DUMP ) \
	1443	ROM_LOAD( "16v8h-red.u45", 0x800, 0x117, NO_DUMP )
	1444
1313	1445	ROM_START( galgbios )
1314		ROM_REGION( 0x200000 + 0x40000, "maincpu", 0 )
1315		ROM_LOAD16_BYTE( "galaxy.u2", 0x1c0000, 0x020000, CRC(e51ff184) SHA1(aaa795f2c15ec29b3ceeb5c917b643db0dbb7083) )
1316		ROM_CONTINUE( 0x000000, 0x0e0000 )
1317		ROM_LOAD16_BYTE( "galaxy.u1", 0x1c0001, 0x020000, CRC(c6d7bc6d) SHA1(93c032f9aa38cbbdda59a8a25ff9f38f7ad9c760) )
1318		ROM_CONTINUE( 0x000001, 0x0e0000 )
1319		ROM_FILL( 0x200000, 0x040000, 0) // RAM
	1446	ROM_REGION( 0x200000, "maincpu", 0 )
	1447	GALGAMES_BIOS_ROMS
1320	1448
1321		ROM_REGION( 0x200000, "gfx1", 0 )
1322		ROM_LOAD16_BYTE( "galaxy.u2", 0x000000, 0x100000, CRC(e51ff184) SHA1(aaa795f2c15ec29b3ceeb5c917b643db0dbb7083) )
1323		ROM_LOAD16_BYTE( "galaxy.u1", 0x000001, 0x100000, CRC(c6d7bc6d) SHA1(93c032f9aa38cbbdda59a8a25ff9f38f7ad9c760) )
	1449	ROM_REGION( 0x200000, "blitter", 0 )
	1450	ROM_COPY( "maincpu", 0, 0, 0x200000 )
1324	1451
1325	1452	ROM_REGION( 0x40000, "oki", ROMREGION_ERASE )
1326	1453	// RAM, filled by the 68000 and fed to the OKI
	1454
	1455	GALGAMES_MB_PALS
1327	1456	ROM_END
1328	1457
	1458	/***************************************************************************
1329	1459
	1460	Galaxy Games StarPak 2
	1461
	1462	NAMCO 307 Cartridge, has surface mount Flash chips in it:
	1463
	1464	.u1 am29f800BB
	1465	.u2 am29f800BB
	1466	.u4 pic 12c508
	1467
	1468	Board silkscreened 237-0209-00
	1469	REV.-C
	1470
	1471	***************************************************************************/
	1472
	1473	ROM_START( galgame2 )
	1474	ROM_REGION( 0x200000 * 2, "maincpu", 0 )
	1475	GALGAMES_BIOS_ROMS
	1476	ROM_LOAD16_BYTE( "namco.u2", 0x200000, 0x100000, CRC(f43c0c54) SHA1(4a13946c3d173b0e4ab25b01849574fa3302b417) )
	1477	ROM_LOAD16_BYTE( "namco.u1", 0x200001, 0x100000, CRC(b8c34a8b) SHA1(40d3b35f573d2bd2ae1c7d876c55fc436864fa3f) )
	1478
	1479	ROM_REGION( 0x9db, "pic", 0 )
	1480	ROM_LOAD( "namco.u4", 0x000, 0x9db, CRC(63ec1224) SHA1(2966b2aa431e6b8d46cbba18a6fc4de7395caa04) )
	1481
	1482	ROM_REGION( 0x200000 * 2, "blitter", 0 )
	1483	ROM_COPY( "maincpu", 0, 0, 0x200000 * 2 )
	1484
	1485	ROM_REGION( 0x40000, "oki", ROMREGION_ERASE )
	1486	// RAM, filled by the 68000 and fed to the OKI
	1487
	1488	GALGAMES_MB_PALS
	1489	ROM_END
	1490
	1491
1330	1492	static DRIVER_INIT( tm4k )
1331	1493	{
1332	1494	UINT16 ROM = (UINT16 )memory_region( machine, "maincpu" );
r5534	r5535
1498	1660
1499	1661	static DRIVER_INIT( galgames )
1500	1662	{
1501		UINT8 *ROM = memory_region(machine, "maincpu");
1502		// configure memory banks
1503		memory_configure_bank(machine, 1, 0, 2, ROM+0x1c0000, 0x40000);
1504		memory_configure_bank(machine, 3, 0, 2, ROM+0x1c0000, 0x40000);
	1663	UINT8 *ROM = memory_region(machine, "maincpu");
	1664	int cart;
1505	1665
1506		memory_configure_bank(machine, 2, 0, 1, ROM+0x200000, 0x40000);
1507		memory_configure_bank(machine, 4, 0, 1, ROM+0x200000, 0x40000);
	1666	// RAM bank at 0x000000-0x03ffff and 0x200000-0x23ffff
	1667	// ROM bank at 0x000000-0x1fffff and 0x200000-0x3fffff (bios)
	1668
	1669	memory_configure_bank(machine, GALGAMES_BANK_000000_R, GALGAMES_RAM, 1, galgames_ram, 0x40000);
	1670	memory_configure_bank(machine, GALGAMES_BANK_000000_R, GALGAMES_ROM0, 1, ROM+0x000000, 0x40000);
	1671
	1672	memory_configure_bank(machine, GALGAMES_BANK_000000_W, GALGAMES_RAM, 1, galgames_ram, 0x40000);
	1673
	1674	memory_configure_bank(machine, GALGAMES_BANK_200000_R, GALGAMES_RAM, 1, galgames_ram, 0x40000);
	1675	memory_configure_bank(machine, GALGAMES_BANK_200000_R, GALGAMES_ROM0, 1, ROM+0x000000, 0x40000);
	1676
	1677	memory_configure_bank(machine, GALGAMES_BANK_200000_W, GALGAMES_RAM, 1, galgames_ram, 0x40000);
	1678
	1679	memory_configure_bank(machine, GALGAMES_BANK_240000_R, GALGAMES_ROM0, 1, ROM+0x040000, 0x1c0000);
	1680
	1681	// More ROM banks at 0x200000-0x3fffff (carts)
	1682
	1683	for (cart = 1; cart <= 4; cart++)
	1684	{
	1685	UINT8 *CART = memory_region(machine, "maincpu");
	1686
	1687	if (0x200000 * (cart+1) <= memory_region_length(machine, "maincpu"))
	1688	CART += 0x200000 * cart;
	1689
	1690	memory_configure_bank(machine, GALGAMES_BANK_200000_R, GALGAMES_ROM0+cart, 1, CART, 0x40000);
	1691	memory_configure_bank(machine, GALGAMES_BANK_240000_R, GALGAMES_ROM0+cart, 1, CART+0x040000, 0x1c0000);
	1692	}
1508	1693	}
1509	1694
1510		GAME( 1996, tm, 0, tm, tm, 0, ROT0, "Midway", "Touchmaster (v3.00 Euro)", 0 )
1511		GAME( 1996, tm2k, 0, tm3k, tmaster, 0, ROT0, "Midway", "Touchmaster 2000 (v4.02 Standard)", 0 )
1512		GAME( 1997, tm3k, 0, tm3k, tmaster, 0, ROT0, "Midway", "Touchmaster 3000 (v5.02 Standard)", 0 )
1513		GAME( 1997, tm3ka, tm3k, tm3k, tmaster, 0, ROT0, "Midway", "Touchmaster 3000 (v5.01 Standard)", 0 )
1514		GAME( 1998, tm4k, 0, tm3k, tmaster, tm4k, ROT0, "Midway", "Touchmaster 4000 (v6.02 Standard)", 0 )
1515		GAME( 1998, tm5k, 0, tm3k, tmaster, tm5k, ROT0, "Midway", "Touchmaster 5000 (v7.10 Standard)", 0 )
1516		GAME( 1998, tm5kca, tm5k, tm3k, tmaster, tm5kca, ROT0, "Midway", "Touchmaster 5000 (v7.10 California)", 0 )
1517		GAME( 1998, tm5ka, tm5k, tm3k, tmaster, tm5ka, ROT0, "Midway", "Touchmaster 5000 (v7.01 Standard)", 0 )
1518		GAME( 1999, tm7k, 0, tm3k, tmaster, tm7k, ROT0, "Midway", "Touchmaster 7000 (v8.04 Standard)", 0 )
1519		GAME( 1999, tm7ka, tm7k, tm3k, tmaster, tm7ka, ROT0, "Midway", "Touchmaster 7000 (v8.00 Standard)", 0 )
1520		GAME( 1999, tm7keval, tm7k, tm3k, tmaster, tm7keval, ROT0, "Midway", "Touchmaster 7000 (v8.1X Evaluation)", 0 )
1521		GAME( 2000, tm8k, 0, tm3k, tmaster, tm8k, ROT0, "Midway", "Touchmaster 8000 (v9.04 Standard)", 0 )
1522		GAME( 1998, galgbios, 0, galgames, galgames, galgames, ROT0, "Creative Electonics & Software", "Galaxy Games (BIOS v1.90)", GAME_IS_BIOS_ROOT )
	1695	static DRIVER_INIT( galgame2 )
	1696	{
	1697	UINT16 ROM = (UINT16 )memory_region( machine, "maincpu" );
	1698
	1699	// Patch BIOS to see the game code as first cartridge (until the PIC therein is emulated)
	1700	ROM[0x118da/2] = 0x4a06;
	1701	ROM[0x118dc/2] = 0x6704;
	1702	ROM[0x118de/2] = 0x7000;
	1703	ROM[0x118e0/2] = 0x6002;
	1704	ROM[0x118e2/2] = 0x7001;
	1705	ROM[0x118e4/2] = 0x4e71;
	1706	ROM[0x118e6/2] = 0x4e71;
	1707	ROM[0x118e8/2] = 0x4e71;
	1708
	1709	// Cartdridge check on game selection screen
	1710	ROM[0x12da0/2] = 0x4e71;
	1711
	1712	DRIVER_INIT_CALL( galgames );
	1713	}
	1714
	1715
	1716	GAME( 1996, tm, 0, tm, tm, 0, ROT0, "Midway", "Touchmaster (v3.00 Euro)", 0 )
	1717	GAME( 1996, tm2k, 0, tm3k, tmaster, 0, ROT0, "Midway", "Touchmaster 2000 (v4.02 Standard)", 0 )
	1718	GAME( 1997, tm3k, 0, tm3k, tmaster, 0, ROT0, "Midway", "Touchmaster 3000 (v5.02 Standard)", 0 )
	1719	GAME( 1997, tm3ka, tm3k, tm3k, tmaster, 0, ROT0, "Midway", "Touchmaster 3000 (v5.01 Standard)", 0 )
	1720	GAME( 1998, tm4k, 0, tm3k, tmaster, tm4k, ROT0, "Midway", "Touchmaster 4000 (v6.02 Standard)", 0 )
	1721	GAME( 1998, tm5k, 0, tm3k, tmaster, tm5k, ROT0, "Midway", "Touchmaster 5000 (v7.10 Standard)", 0 )
	1722	GAME( 1998, tm5kca, tm5k, tm3k, tmaster, tm5kca, ROT0, "Midway", "Touchmaster 5000 (v7.10 California)", 0 )
	1723	GAME( 1998, tm5ka, tm5k, tm3k, tmaster, tm5ka, ROT0, "Midway", "Touchmaster 5000 (v7.01 Standard)", 0 )
	1724	GAME( 1999, tm7k, 0, tm3k, tmaster, tm7k, ROT0, "Midway", "Touchmaster 7000 (v8.04 Standard)", 0 )
	1725	GAME( 1999, tm7ka, tm7k, tm3k, tmaster, tm7ka, ROT0, "Midway", "Touchmaster 7000 (v8.00 Standard)", 0 )
	1726	GAME( 1999, tm7keval, tm7k, tm3k, tmaster, tm7keval, ROT0, "Midway", "Touchmaster 7000 (v8.1X Evaluation)", 0 )
	1727	GAME( 2000, tm8k, 0, tm3k, tmaster, tm8k, ROT0, "Midway", "Touchmaster 8000 (v9.04 Standard)", 0 )
	1728	GAME( 1998, galgbios, 0, galgames, galgames, galgames, ROT0, "Creative Electronics & Software", "Galaxy Games (BIOS v1.90)", GAME_IS_BIOS_ROOT )
	1729	GAME( 1998, galgame2, galgbios, galgame2, galgames, galgame2, ROT0, "Creative Electronics & Software / Namco", "Galaxy Games StarPak 2", 0 )

src/mame/drivers/namcos22.c
r5534	r5535
4684	4684	ROM_LOAD( "dt1ptru2.15f", 0x400000, 0x080000, CRC(1171eaf5) SHA1(168365ea619386f218585c49025cdd7fd1224082) )
4685	4685
4686	4686	ROM_REGION( 0x1000000, "c352", 0 ) /* sound samples */
4687		ROM_LOAD( "dt1wavea.2l", 0x000000, 0x400000, CRC(14352455) SHA1(1965ea6e5ce1b2187ecb64bd40ff044f4b2ba5f6) )
4688		ROM_LOAD( "dt1waveb.1l", 0x400000, 0x400000, CRC(16a4dd8a) SHA1(4883b7ba3ee08a2893d4b2918640ba44e7147164) )
	4687	ROM_LOAD( "dt1wavea.2l", 0x000000, 0x400000, CRC(cbd52e40) SHA1(dc995dd919548c96a90efb0375e5b5f1055e05cb) )
	4688	ROM_LOAD( "dt1waveb.1l", 0x400000, 0x400000, CRC(6b736f94) SHA1(ac3715480aa9a9c2dec099607f89859bb3b73a6a) )
4689	4689	ROM_END
4690	4690
4691	4691	ROM_START( aquajet )

src/mame/drivers/n8080.c
r5534	r5535
81	81	cputag_set_input_line_and_vector(timer->machine, "maincpu", INPUT_LINE_IRQ0, state, 0xd7);
82	82	}
83	83
84		static ~~void~~ n8080_inte_callback~~(const~~ ~~device_config *device, int state~~)
	84	static WRITE_LINE_DEVICE_HANDLER( n8080_inte_callback )
85	85	{
86	86	inte = state;
87	87	}
88	88
89		static ~~void~~ n8080_status_callback~~(const~~ ~~device_config *device, UINT8 status~~)
	89	static WRITE8_DEVICE_HANDLER( n8080_status_callback )
90	90	{
91		if (~~BIT(st~~at~~us,~~ 0))
	91	if (data & I8085_STATUS_INTA)
92	92	{
93	93	/* interrupt acknowledge */
94	94	cpu_set_input_line(device, INPUT_LINE_IRQ0, CLEAR_LINE);
95	95	}
96	96	}
97	97
98		static ~~const i~~8085_~~config~~ n8080_cpu_config =
	98	static I8085_CONFIG( n8080_cpu_config )
99	99	{
100		n8080_inte_callback, /* INTE changed callback */
101		n8080_status_callback, /* STATUS changed callback */
102		NULL, /* SOD changed callback (8085A only) */
103		NULL, /* SID changed callback (8085A only) */
	100	DEVCB_HANDLER(n8080_status_callback), /* STATUS changed callback */
	101	DEVCB_LINE(n8080_inte_callback), /* INTE changed callback */
	102	DEVCB_NULL, /* SID changed callback (8085A only) */
	103	DEVCB_NULL /* SOD changed callback (8085A only) */
104	104	};
105	105
106	106	static MACHINE_DRIVER_START( spacefev )

src/mame/drivers/taitogn.c
r5534	r5535
1173	1173	DISK_IMAGE( "kollon", 0, SHA1(d8ea5b5b0ee99004b16ef89883e23de6c7ddd7ce))
1174	1174	ROM_END
1175	1175
	1176	ROM_START(kollonc)
	1177	TAITOGNET_BIOS
	1178	ROM_DEFAULT_BIOS( "v2" )
	1179
	1180	DISK_REGION( "card" )
	1181	DISK_IMAGE( "kollonc", 0, SHA1(ce62181659701cfb8f7c564870ab902be4d8e060)) /* Original Taito Compact Flash version */
	1182	ROM_END
	1183
1176	1184	ROM_START(shikigam)
1177	1185	TAITOGNET_BIOS
1178	1186
r5534	r5535
1224	1232	ROM_DEFAULT_BIOS( "v2" )
1225	1233
1226	1234	DISK_REGION( "card" )
1227		DISK_IMAGE( "otenamhf", 0, SHA1(5b15c33bf401e5546d78e905f538513d6ffcf562))
	1235	DISK_IMAGE( "otenamhf", 0, SHA1(5b15c33bf401e5546d78e905f538513d6ffcf562)) /* Original Taito Compact Flash version */
1228	1236	ROM_END
1229	1237
1230	1238
r5534	r5535
1296	1304	GAME( 2001, shikigam, taitogn, coh3002t, coh3002t, coh3002t, ROT270, "Taito/Alfa System", "Shikigami no Shiro (V2.03J)", GAME_IMPERFECT_SOUND )
1297	1305	GAME( 2003, sianniv, taitogn, coh3002t, coh3002t, coh3002t, ROT270, "Taito", "Space Invaders Anniversary (V2.02J)", GAME_NOT_WORKING \| GAME_IMPERFECT_SOUND ) // IRQ at the wrong time
1298	1306	GAME( 2003, kollon, taitogn, coh3002t, coh3002t, coh3002t, ROT0, "Taito", "Kollon (V2.04J)", GAME_IMPERFECT_SOUND )
	1307	GAME( 2003, kollonc, kollon, coh3002t, coh3002t, coh3002t, ROT0, "Taito", "Kollon (V2.04JC)", GAME_IMPERFECT_SOUND )
1299	1308
1300	1309	GAME( 1999, otenamih, taitogn, coh3002t, coh3002t, coh3002t, ROT0, "Success", "Otenami Haiken (V2.04J)", GAME_IMPERFECT_SOUND )
1301	1310	GAME( 2005, otenamhf, taitogn, coh3002t, coh3002t, coh3002t, ROT0, "Success/Warashi", "Otenami Haiken Final (V2.07JC)", GAME_IMPERFECT_SOUND )

src/mame/drivers/goindol.c
r5534	r5535
102	102	AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_BASE(&ram)
103	103	AM_RANGE(0xc800, 0xc800) AM_READNOP AM_WRITE(soundlatch_w) // watchdog?
104	104	AM_RANGE(0xc810, 0xc810) AM_WRITE(goindol_bankswitch_w)
105		AM_RANGE(0xc820, 0xd820) AM_READ_PORT("DIAL") AM_WRITE(SMH_RAM) AM_BASE(&goindol_fg_scrolly)
106		AM_RANGE(0xc830, 0xd830) AM_READ_PORT("P1") AM_WRITE(SMH_RAM) AM_BASE(&goindol_fg_scrollx)
	105	AM_RANGE(0xc820, 0xc820) AM_READ_PORT("DIAL")
	106	AM_RANGE(0xc820, 0xd820) AM_WRITE(SMH_RAM) AM_BASE(&goindol_fg_scrolly)
	107	AM_RANGE(0xc830, 0xc830) AM_READ_PORT("P1")
	108	AM_RANGE(0xc830, 0xd830) AM_WRITE(SMH_RAM) AM_BASE(&goindol_fg_scrollx)
107	109	AM_RANGE(0xc834, 0xc834) AM_READ_PORT("P2")
108	110	AM_RANGE(0xd000, 0xd03f) AM_RAM AM_BASE(&spriteram) AM_SIZE(&spriteram_size)
109	111	AM_RANGE(0xd040, 0xd7ff) AM_RAM

src/tools/unidasm.c
r0	r5535
	1	/***************************************************************************
	2
	3	mamedasm.c
	4
	5	Generic MAME disassembler.
	6
	7	Copyright Nicola Salmoria and the MAME Team.
	8	Visit http://mamedev.org for licensing and usage restrictions.
	9
	10	***************************************************************************/
	11
	12	#include "cpuintrf.h"
	13	#include <ctype.h>
	14
	15
	16	enum _display_type
	17	{
	18	_8bit,
	19	_8bitx,
	20	_16be,
	21	_16le,
	22	_24be,
	23	_24le,
	24	_32be,
	25	_32le,
	26	_40be,
	27	_40le,
	28	_48be,
	29	_48le,
	30	_56be,
	31	_56le,
	32	_64be,
	33	_64le
	34	};
	35	typedef enum _display_type display_type;
	36
	37
	38	typedef struct _dasm_table_entry dasm_table_entry;
	39	struct _dasm_table_entry
	40	{
	41	const char * name;
	42	display_type display;
	43	INT8 pcshift;
	44	cpu_disassemble_func func;
	45	};
	46
	47
	48	typedef struct _options options;
	49	struct _options
	50	{
	51	const char * filename;
	52	offs_t basepc;
	53	UINT8 norawbytes;
	54	UINT8 lower;
	55	UINT8 upper;
	56	const dasm_table_entry *dasm;
	57	};
	58
	59
	60	CPU_DISASSEMBLE( adsp21xx );
	61	CPU_DISASSEMBLE( alpha8201 );
	62	CPU_DISASSEMBLE( arm );
	63	CPU_DISASSEMBLE( arm7arm );
	64	CPU_DISASSEMBLE( arm7thumb );
	65	CPU_DISASSEMBLE( asap );
	66	CPU_DISASSEMBLE( avr8 );
	67	CPU_DISASSEMBLE( ccpu );
	68	CPU_DISASSEMBLE( cdp1802 );
	69	CPU_DISASSEMBLE( cop410 );
	70	CPU_DISASSEMBLE( cop420 );
	71	CPU_DISASSEMBLE( cop444 );
	72	CPU_DISASSEMBLE( cp1610 );
	73	CPU_DISASSEMBLE( cquestsnd );
	74	CPU_DISASSEMBLE( cquestrot );
	75	CPU_DISASSEMBLE( cquestlin );
	76	CPU_DISASSEMBLE( dsp32c );
	77	CPU_DISASSEMBLE( dsp56k );
	78	CPU_DISASSEMBLE( hyperstone_generic );
	79	CPU_DISASSEMBLE( esrip );
	80	CPU_DISASSEMBLE( f8 );
	81	CPU_DISASSEMBLE( g65816_generic );
	82	CPU_DISASSEMBLE( h6280 );
	83	CPU_DISASSEMBLE( h8 );
	84	CPU_DISASSEMBLE( hd6309 );
	85	CPU_DISASSEMBLE( i4004 );
	86	CPU_DISASSEMBLE( i8085 );
	87	CPU_DISASSEMBLE( x86_16 );
	88	CPU_DISASSEMBLE( x86_32 );
	89	CPU_DISASSEMBLE( x86_64 );
	90	CPU_DISASSEMBLE( i860 );
	91	CPU_DISASSEMBLE( i960 );
	92	CPU_DISASSEMBLE( jaguargpu );
	93	CPU_DISASSEMBLE( jaguardsp );
	94	CPU_DISASSEMBLE( konami );
	95	CPU_DISASSEMBLE( lh5801 );
	96	CPU_DISASSEMBLE( lr35902 );
	97	CPU_DISASSEMBLE( m37710_generic );
	98	CPU_DISASSEMBLE( m6502 );
	99	CPU_DISASSEMBLE( m65sc02 );
	100	CPU_DISASSEMBLE( m65c02 );
	101	CPU_DISASSEMBLE( m65ce02 );
	102	CPU_DISASSEMBLE( m6510 );
	103	CPU_DISASSEMBLE( deco16 );
	104	CPU_DISASSEMBLE( m4510 );
	105	CPU_DISASSEMBLE( m6800 );
	106	CPU_DISASSEMBLE( m6801 );
	107	CPU_DISASSEMBLE( m6802 );
	108	CPU_DISASSEMBLE( m6803 );
	109	CPU_DISASSEMBLE( hd63701 );
	110	CPU_DISASSEMBLE( nsc8105 );
	111	CPU_DISASSEMBLE( m68000 );
	112	CPU_DISASSEMBLE( m68008 );
	113	CPU_DISASSEMBLE( m68010 );
	114	CPU_DISASSEMBLE( m68020 );
	115	CPU_DISASSEMBLE( m68030 );
	116	CPU_DISASSEMBLE( m68040 );
	117	CPU_DISASSEMBLE( m6805 );
	118	CPU_DISASSEMBLE( m6809 );
	119	CPU_DISASSEMBLE( mb86233 );
	120	CPU_DISASSEMBLE( mb88 );
	121	CPU_DISASSEMBLE( mcs48 );
	122	CPU_DISASSEMBLE( upi41 );
	123	CPU_DISASSEMBLE( i8051 );
	124	CPU_DISASSEMBLE( i8052 );
	125	CPU_DISASSEMBLE( i80c51 );
	126	CPU_DISASSEMBLE( i80c52 );
	127	CPU_DISASSEMBLE( ds5002fp );
	128	CPU_DISASSEMBLE( minx );
	129	CPU_DISASSEMBLE( mips3be );
	130	CPU_DISASSEMBLE( mips3le );
	131	CPU_DISASSEMBLE( psxcpu_generic );
	132	CPU_DISASSEMBLE( r3000be );
	133	CPU_DISASSEMBLE( r3000le );
	134	CPU_DISASSEMBLE( nec_generic );
	135	CPU_DISASSEMBLE( pdp1 );
	136	CPU_DISASSEMBLE( tx0_64kw );
	137	CPU_DISASSEMBLE( tx0_8kw );
	138	CPU_DISASSEMBLE( pic16c5x );
	139	CPU_DISASSEMBLE( powerpc );
	140	CPU_DISASSEMBLE( rsp );
	141	CPU_DISASSEMBLE( s2650 );
	142	CPU_DISASSEMBLE( saturn );
	143	CPU_DISASSEMBLE( sc61860 );
	144	CPU_DISASSEMBLE( se3208 );
	145	CPU_DISASSEMBLE( sh2 );
	146	CPU_DISASSEMBLE( sh4 );
	147	CPU_DISASSEMBLE( sharc );
	148	CPU_DISASSEMBLE( sm8500 );
	149	CPU_DISASSEMBLE( spc700 );
	150	CPU_DISASSEMBLE( ssem );
	151	CPU_DISASSEMBLE( ssp1601 );
	152	CPU_DISASSEMBLE( t11 );
	153	CPU_DISASSEMBLE( t90 );
	154	CPU_DISASSEMBLE( tlcs900 );
	155	CPU_DISASSEMBLE( tms0980 );
	156	CPU_DISASSEMBLE( tms1000 );
	157	CPU_DISASSEMBLE( tms1100 );
	158	CPU_DISASSEMBLE( tms32010 );
	159	CPU_DISASSEMBLE( tms32025 );
	160	CPU_DISASSEMBLE( tms32031 );
	161	CPU_DISASSEMBLE( tms32051 );
	162	CPU_DISASSEMBLE( tms34010 );
	163	CPU_DISASSEMBLE( tms34020 );
	164	CPU_DISASSEMBLE( tms57002 );
	165	CPU_DISASSEMBLE( tms7000 );
	166	CPU_DISASSEMBLE( upd7810 );
	167	CPU_DISASSEMBLE( upd7807 );
	168	CPU_DISASSEMBLE( upd7801 );
	169	CPU_DISASSEMBLE( upd78c05 );
	170	CPU_DISASSEMBLE( v60 );
	171	CPU_DISASSEMBLE( v70 );
	172	CPU_DISASSEMBLE( v810 );
	173	CPU_DISASSEMBLE( z180 );
	174	CPU_DISASSEMBLE( z8000 );
	175	CPU_DISASSEMBLE( z80 );
	176
	177
	178	static const dasm_table_entry dasm_table[] =
	179	{
	180	{ "adsp21xx", _24le, -2, CPU_DISASSEMBLE_NAME(adsp21xx) },
	181	{ "alpha8201", _8bit, 0, CPU_DISASSEMBLE_NAME(alpha8201) },
	182	{ "arm", _32le, 0, CPU_DISASSEMBLE_NAME(arm) },
	183	{ "arm7", _32le, 0, CPU_DISASSEMBLE_NAME(arm7arm) },
	184	{ "arm7thumb", _16le, 0, CPU_DISASSEMBLE_NAME(arm7thumb) },
	185	{ "asap", _32le, 0, CPU_DISASSEMBLE_NAME(asap) },
	186	{ "avr8", _16le, 0, CPU_DISASSEMBLE_NAME(avr8) },
	187	{ "ccpu", _8bit, 0, CPU_DISASSEMBLE_NAME(ccpu) },
	188	{ "cdp1802", _8bit, 0, CPU_DISASSEMBLE_NAME(cdp1802) },
	189	{ "cop410", _8bit, 0, CPU_DISASSEMBLE_NAME(cop410) },
	190	{ "cop420", _8bit, 0, CPU_DISASSEMBLE_NAME(cop420) },
	191	{ "cop444", _8bit, 0, CPU_DISASSEMBLE_NAME(cop444) },
	192	{ "cp1610", _16be, -1, CPU_DISASSEMBLE_NAME(cp1610) },
	193	{ "cquestsnd", _64be, -3, CPU_DISASSEMBLE_NAME(cquestsnd) },
	194	{ "cquestrot", _64be, -3, CPU_DISASSEMBLE_NAME(cquestrot) },
	195	{ "cquestlin", _64be, -3, CPU_DISASSEMBLE_NAME(cquestlin) },
	196	{ "dsp32c", _32le, 0, CPU_DISASSEMBLE_NAME(dsp32c) },
	197	{ "dsp56k", _16le, -1, CPU_DISASSEMBLE_NAME(dsp56k) },
	198	{ "hyperstone", _16be, 0, CPU_DISASSEMBLE_NAME(hyperstone_generic) },
	199	{ "esrip", _64be, 0, CPU_DISASSEMBLE_NAME(esrip) },
	200	{ "f8", _8bit, 0, CPU_DISASSEMBLE_NAME(f8) },
	201	{ "g65816", _8bit, 0, CPU_DISASSEMBLE_NAME(g65816_generic) },
	202	{ "h6280", _8bit, 0, CPU_DISASSEMBLE_NAME(h6280) },
	203	{ "h8", _16be, 0, CPU_DISASSEMBLE_NAME(h8) },
	204	{ "hd6309", _8bit, 0, CPU_DISASSEMBLE_NAME(hd6309) },
	205	{ "i386", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_32) },
	206	{ "i4004", _8bit, 0, CPU_DISASSEMBLE_NAME(i4004) },
	207	{ "i8085", _8bit, 0, CPU_DISASSEMBLE_NAME(i8085) },
	208	{ "i80286", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_16) },
	209	{ "i8086", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_16) },
	210	{ "i960", _32le, 0, CPU_DISASSEMBLE_NAME(i960) },
	211	{ "jaguargpu", _16be, 0, CPU_DISASSEMBLE_NAME(jaguargpu) },
	212	{ "jaguardsp", _16be, 0, CPU_DISASSEMBLE_NAME(jaguardsp) },
	213	{ "x86_16", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_16) },
	214	{ "x86_32", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_32) },
	215	{ "x86_64", _8bit, 0, CPU_DISASSEMBLE_NAME(x86_64) },
	216	{ "konami", _8bit, 0, CPU_DISASSEMBLE_NAME(konami) },
	217	{ "lh5801", _8bit, 0, CPU_DISASSEMBLE_NAME(lh5801) },
	218	{ "lr35902", _8bit, 0, CPU_DISASSEMBLE_NAME(lr35902) },
	219	{ "m37710", _8bit, 0, CPU_DISASSEMBLE_NAME(m37710_generic) },
	220	{ "m6502", _8bit, 0, CPU_DISASSEMBLE_NAME(m6502) },
	221	{ "m65sc02", _8bit, 0, CPU_DISASSEMBLE_NAME(m65sc02) },
	222	{ "m65c02", _8bit, 0, CPU_DISASSEMBLE_NAME(m65c02) },
	223	{ "m65ce02", _8bit, 0, CPU_DISASSEMBLE_NAME(m65ce02) },
	224	{ "m6510", _8bit, 0, CPU_DISASSEMBLE_NAME(m6510) },
	225	{ "deco16", _8bit, 0, CPU_DISASSEMBLE_NAME(deco16) },
	226	{ "m4510", _8bit, 0, CPU_DISASSEMBLE_NAME(m4510) },
	227	{ "m6800", _8bit, 0, CPU_DISASSEMBLE_NAME(m6800) },
	228	{ "m6801", _8bit, 0, CPU_DISASSEMBLE_NAME(m6801) },
	229	{ "m6802", _8bit, 0, CPU_DISASSEMBLE_NAME(m6802) },
	230	{ "m6803", _8bit, 0, CPU_DISASSEMBLE_NAME(m6803) },
	231	{ "hd63701", _8bit, 0, CPU_DISASSEMBLE_NAME(hd63701) },
	232	{ "nsc8105", _8bit, 0, CPU_DISASSEMBLE_NAME(nsc8105) },
	233	{ "m68000", _16be, 0, CPU_DISASSEMBLE_NAME(m68000) },
	234	{ "m68008", _16be, 0, CPU_DISASSEMBLE_NAME(m68008) },
	235	{ "m68010", _16be, 0, CPU_DISASSEMBLE_NAME(m68010) },
	236	{ "m68020", _16be, 0, CPU_DISASSEMBLE_NAME(m68020) },
	237	{ "m68030", _16be, 0, CPU_DISASSEMBLE_NAME(m68030) },
	238	{ "m68040", _16be, 0, CPU_DISASSEMBLE_NAME(m68040) },
	239	{ "m6805", _8bit, 0, CPU_DISASSEMBLE_NAME(m6805) },
	240	{ "m6809", _8bit, 0, CPU_DISASSEMBLE_NAME(m6809) },
	241	{ "mb86233", _32le, -2, CPU_DISASSEMBLE_NAME(mb86233) },
	242	{ "mb88xx", _8bit, 0, CPU_DISASSEMBLE_NAME(mb88) },
	243	{ "mcs48", _8bit, 0, CPU_DISASSEMBLE_NAME(mcs48) },
	244	{ "upi41", _8bit, 0, CPU_DISASSEMBLE_NAME(upi41) },
	245	{ "i8051", _8bit, 0, CPU_DISASSEMBLE_NAME(i8051) },
	246	{ "i8052", _8bit, 0, CPU_DISASSEMBLE_NAME(i8052) },
	247	{ "i80c51", _8bit, 0, CPU_DISASSEMBLE_NAME(i80c51) },
	248	{ "i80c52", _8bit, 0, CPU_DISASSEMBLE_NAME(i80c52) },
	249	{ "ds5002fp", _8bit, 0, CPU_DISASSEMBLE_NAME(ds5002fp) },
	250	{ "minx", _8bit, 0, CPU_DISASSEMBLE_NAME(minx) },
	251	{ "mips3be", _32be, 0, CPU_DISASSEMBLE_NAME(mips3be) },
	252	{ "mips3le", _32le, 0, CPU_DISASSEMBLE_NAME(mips3le) },
	253	{ "psxcpu", _32le, 0, CPU_DISASSEMBLE_NAME(psxcpu_generic) },
	254	{ "r3000be", _32be, 0, CPU_DISASSEMBLE_NAME(r3000be) },
	255	{ "r3000le", _32le, 0, CPU_DISASSEMBLE_NAME(r3000le) },
	256	{ "nec", _8bit, 0, CPU_DISASSEMBLE_NAME(nec_generic) },
	257	{ "pdp1", _32be, 0, CPU_DISASSEMBLE_NAME(pdp1) },
	258	{ "tx0_64kw", _32be, -2, CPU_DISASSEMBLE_NAME(tx0_64kw) },
	259	{ "tx0_8kw", _32be, -2, CPU_DISASSEMBLE_NAME(tx0_8kw) },
	260	{ "pic16c5x", _16le, -1, CPU_DISASSEMBLE_NAME(pic16c5x) },
	261	{ "powerpc", _32be, 0, CPU_DISASSEMBLE_NAME(powerpc) },
	262	{ "rsp", _32le, 0, CPU_DISASSEMBLE_NAME(rsp) },
	263	{ "s2650", _8bit, 0, CPU_DISASSEMBLE_NAME(s2650) },
	264	{ "saturn", _8bit, 0, CPU_DISASSEMBLE_NAME(saturn) },
	265	{ "sc61860", _8bit, 0, CPU_DISASSEMBLE_NAME(sc61860) },
	266	{ "se3208", _16le, 0, CPU_DISASSEMBLE_NAME(se3208) },
	267	{ "sh2", _16be, 0, CPU_DISASSEMBLE_NAME(sh2) },
	268	{ "sh4", _16le, 0, CPU_DISASSEMBLE_NAME(sh4) },
	269	{ "sharc", _64le, -3, CPU_DISASSEMBLE_NAME(sharc) },
	270	{ "sm8500", _8bit, 0, CPU_DISASSEMBLE_NAME(sm8500) },
	271	{ "spc700", _8bit, 0, CPU_DISASSEMBLE_NAME(spc700) },
	272	{ "ssem", _32le, 0, CPU_DISASSEMBLE_NAME(ssem) },
	273	{ "ssp1601", _16be, -1, CPU_DISASSEMBLE_NAME(ssp1601) },
	274	{ "t11", _16le, 0, CPU_DISASSEMBLE_NAME(t11) },
	275	// { "t90", _8bit, 0, CPU_DISASSEMBLE_NAME(t90) },
	276	{ "tlcs900", _8bit, 0, CPU_DISASSEMBLE_NAME(tlcs900) },
	277	{ "tms0980", _16be, 0, CPU_DISASSEMBLE_NAME(tms0980) },
	278	{ "tms1000", _8bit, 0, CPU_DISASSEMBLE_NAME(tms1000) },
	279	{ "tms1100", _8bit, 0, CPU_DISASSEMBLE_NAME(tms1100) },
	280	{ "tms32010", _16be, -1, CPU_DISASSEMBLE_NAME(tms32010) },
	281	{ "tms32025", _16be, -1, CPU_DISASSEMBLE_NAME(tms32025) },
	282	{ "tms32031", _32le, -2, CPU_DISASSEMBLE_NAME(tms32031) },
	283	{ "tms32051", _16le, -1, CPU_DISASSEMBLE_NAME(tms32051) },
	284	{ "tms34010", _8bit, 3, CPU_DISASSEMBLE_NAME(tms34010) },
	285	{ "tms34020", _8bit, 3, CPU_DISASSEMBLE_NAME(tms34020) },
	286	{ "tms57002", _32le, -2, CPU_DISASSEMBLE_NAME(tms57002) },
	287	{ "tms7000", _8bit, 0, CPU_DISASSEMBLE_NAME(tms7000) },
	288	{ "upd7810", _8bit, 0, CPU_DISASSEMBLE_NAME(upd7810) },
	289	{ "upd7807", _8bit, 0, CPU_DISASSEMBLE_NAME(upd7807) },
	290	{ "upd7801", _8bit, 0, CPU_DISASSEMBLE_NAME(upd7801) },
	291	{ "upd78c05", _8bit, 0, CPU_DISASSEMBLE_NAME(upd78c05) },
	292	{ "v60", _8bit, 0, CPU_DISASSEMBLE_NAME(v60) },
	293	{ "v70", _8bit, 0, CPU_DISASSEMBLE_NAME(v70) },
	294	{ "v810", _16le, 0, CPU_DISASSEMBLE_NAME(v810) },
	295	{ "z180", _8bit, 0, CPU_DISASSEMBLE_NAME(z180) },
	296	// { "z8000", _16be, 0, CPU_DISASSEMBLE_NAME(z8000) },
	297	{ "z80", _8bit, 0, CPU_DISASSEMBLE_NAME(z80) },
	298	};
	299
	300
	301	void CLIB_DECL fatalerror(const char *text, ...)
	302	{
	303	va_list arg;
	304
	305	/* dump to the buffer; assume no one writes >2k lines this way */
	306	va_start(arg, text);
	307	vfprintf(stderr, text, arg);
	308	va_end(arg);
	309
	310	exit(1);
	311	}
	312
	313
	314	void CLIB_DECL logerror(const char *format, ...)
	315	{
	316	/* silent logerrors are allowed in disassemblers */
	317	}
	318
	319
	320	void CLIB_DECL mame_printf_debug(const char *format, ...)
	321	{
	322	/* silent mame_printf_debugs are allowed in disassemblers */
	323	}
	324
	325
	326	int parse_options(int argc, char argv[], options opts)
	327	{
	328	int pending_base = FALSE;
	329	int pending_arch = FALSE;
	330	int curarch;
	331	int numrows;
	332	int arg;
	333
	334	memset(opts, 0, sizeof(*opts));
	335
	336	// loop through arguments
	337	for (arg = 1; arg < argc; arg++)
	338	{
	339	char *curarg = argv[arg];
	340
	341	// is it a switch?
	342	if (curarg[0] == '-')
	343	{
	344	if (pending_base \|\| pending_arch)
	345	goto usage;
	346
	347	if (tolower(curarg[1]) == 'a')
	348	pending_arch = TRUE;
	349	else if (tolower(curarg[1]) == 'b')
	350	pending_base = TRUE;
	351	else if (tolower(curarg[1]) == 'l')
	352	opts->lower = TRUE;
	353	else if (tolower(curarg[1]) == 'n')
	354	opts->norawbytes = TRUE;
	355	else if (tolower(curarg[1]) == 'u')
	356	opts->upper = TRUE;
	357	else
	358	goto usage;
	359	}
	360
	361	// base PC
	362	else if (pending_base)
	363	{
	364	if (curarg[0] == '0' && curarg[1] == 'x')
	365	sscanf(&curarg[2], "%x", &opts->basepc);
	366	else if (curarg[0] == '$')
	367	sscanf(&curarg[1], "%x", &opts->basepc);
	368	else
	369	sscanf(&curarg[0], "%x", &opts->basepc);
	370	pending_base = FALSE;
	371	}
	372
	373	// architecture
	374	else if (pending_arch)
	375	{
	376	for (curarch = 0; curarch < ARRAY_LENGTH(dasm_table); curarch++)
	377	if (core_stricmp(curarg, dasm_table[curarch].name) == 0)
	378	break;
	379	if (curarch == ARRAY_LENGTH(dasm_table))
	380	goto usage;
	381	opts->dasm = &dasm_table[curarch];
	382	pending_arch = FALSE;
	383	}
	384
	385	// filename
	386	else if (opts->filename == NULL)
	387	opts->filename = curarg;
	388
	389	// fail
	390	else
	391	goto usage;
	392	}
	393
	394	// if no file or no architecture, fail
	395	if (opts->filename == NULL \|\| opts->dasm == NULL)
	396	goto usage;
	397	return 0;
	398
	399	usage:
	400	printf("Usage: %s <filename> -arch <architecture> [-basepc <pc>] [-norawbytes] [-upper] [-lower]\n", argv[0]);
	401	printf("\n");
	402	printf("Supported architectures:");
	403	numrows = (ARRAY_LENGTH(dasm_table) + 6) / 7;
	404	for (curarch = 0; curarch < numrows * 7; curarch++)
	405	{
	406	int row = curarch / 7;
	407	int col = curarch % 7;
	408	int index = col * numrows + row;
	409	if (col == 0)
	410	printf("\n ");
	411	printf("%-11s", (index < ARRAY_LENGTH(dasm_table)) ? dasm_table[index].name : "");
	412	}
	413	printf("\n");
	414	return 1;
	415	};
	416
	417
	418	int main(int argc, char *argv[])
	419	{
	420	file_error filerr;
	421	int displayendian;
	422	int displaychunk;
	423	UINT32 curbyte;
	424	UINT32 length;
	425	int maxchunks;
	426	UINT32 curpc;
	427	options opts;
	428	int numbytes;
	429	void *data;
	430	char *p;
	431
	432	// parse options first
	433	if (parse_options(argc, argv, &opts))
	434	return 1;
	435
	436	// load the file
	437	filerr = core_fload(opts.filename, &data, &length);
	438	if (filerr != FILERR_NONE)
	439	{
	440	fprintf(stderr, "Error opening file '%s'\n", opts.filename);
	441	return 1;
	442	}
	443
	444	// precompute parameters
	445	displaychunk = (opts.dasm->display / 2) + 1;
	446	displayendian = opts.dasm->display % 2;
	447	switch (displaychunk)
	448	{
	449	case 1: maxchunks = 6; break;
	450	case 2: maxchunks = 3; break;
	451	default: maxchunks = 1; break;
	452	}
	453
	454	// run it
	455	curpc = opts.basepc;
	456	for (curbyte = 0; curbyte < length; curbyte += numbytes)
	457	{
	458	UINT8 oprom = (UINT8 )data + curbyte;
	459	char buffer[1024];
	460	UINT32 pcdelta;
	461	int numchunks;
	462
	463	// disassemble
	464	pcdelta = (*opts.dasm->func)(NULL, buffer, curpc, oprom, oprom) & DASMFLAG_LENGTHMASK;
	465	if (opts.dasm->pcshift < 0)
	466	numbytes = pcdelta << -opts.dasm->pcshift;
	467	else
	468	numbytes = pcdelta >> opts.dasm->pcshift;
	469
	470	// round to the nearest display chunk
	471	numbytes = ((numbytes + displaychunk - 1) / displaychunk) * displaychunk;
	472	if (numbytes == 0)
	473	numbytes = displaychunk;
	474	numchunks = numbytes / displaychunk;
	475
	476	// output the address
	477	printf("%08X: ", curpc);
	478
	479	// output the raw bytes
	480	if (!opts.norawbytes)
	481	{
	482	int firstchunks = (numchunks < maxchunks) ? numchunks : maxchunks;
	483	int chunknum, bytenum;
	484	for (chunknum = 0; chunknum < firstchunks; chunknum++)
	485	{
	486	for (bytenum = 0; bytenum < displaychunk; bytenum++)
	487	printf("%02X", oprom[displayendian ? (displaychunk - 1 - bytenum) : bytenum]);
	488	printf(" ");
	489	oprom += displaychunk;
	490	}
	491	for ( ; chunknum < maxchunks; chunknum++)
	492	printf("%s ", displaychunk 2, "");
	493	printf(" ");
	494	}
	495
	496	// output the disassembly
	497	if (opts.lower)
	498	{
	499	for (p = buffer; *p != 0; p++)
	500	p = tolower(p);
	501	} else if (opts.upper)
	502	{
	503	for (p = buffer; *p != 0; p++)
	504	p = toupper(p);
	505	}
	506	printf("%s\n", buffer);
	507
	508	// output additional raw bytes
	509	if (!opts.norawbytes && numchunks > maxchunks)
	510	{
	511	for (numchunks -= maxchunks; numchunks > 0; numchunks -= maxchunks)
	512	{
	513	int firstchunks = (numchunks < maxchunks) ? numchunks : maxchunks;
	514	int chunknum, bytenum;
	515	printf(" ");
	516	for (chunknum = 0; chunknum < firstchunks; chunknum++)
	517	{
	518	for (bytenum = 0; bytenum < displaychunk; bytenum++)
	519	printf("%02X", oprom[displayendian ? (displaychunk - 1 - bytenum) : bytenum]);
	520	printf(" ");
	521	oprom += displaychunk;
	522	}
	523	printf("\n");
	524	}
	525	}
	526
	527	// advance
	528	curpc += pcdelta;
	529	curbyte += numbytes;
	530	}
	531
	532	return 0;
	533	}

src/tools/tools.mak
r5534	r5535
26	26	romcmp$(EXE) \
27	27	chdman$(EXE) \
28	28	jedutil$(EXE) \
	29	unidasm$(EXE) \
29	30	ldresample$(EXE) \
30	31	ldverify$(EXE) \
31	32	regrep$(EXE) \
r5534	r5535
76	77
77	78
78	79	#-------------------------------------------------
	80	# unidasm
	81	#-------------------------------------------------
	82
	83	UNIDASMOBJS = \
	84	$(TOOLSOBJ)/unidasm.o \
	85
	86	unidasm$(EXE): $(UNIDASMOBJS) $(LIBUTIL) $(LIBOCORE) $(LIBDASM) $(ZLIB) $(EXPAT)
	87	@echo Linking $@...
	88	$(LD) $(LDFLAGS) $^ $(LIBS) -o $@
	89
	90
	91
	92	#-------------------------------------------------
79	93	# ldresample
80	94	#-------------------------------------------------
81	95

src/osd/osdmini/minimisc.c
r5534	r5535
33	33
34	34
35	35	//============================================================
36		// osd_is_bad_read_ptr
37		//============================================================
38
39		int osd_is_bad_read_ptr(const void *ptr, size_t size)
40		{
41		// there is no standard way to do this, so just say no
42		return FALSE;
43		}
44
45
46		//============================================================
47	36	// osd_break_into_debugger
48	37	//============================================================
49	38

src/osd/osdcore.h
r5534	r5535
758	758
759	759
760	760	/*-----------------------------------------------------------------------------
761		osd_is_bad_read_ptr: attempt to determine if the given pointer will
762		generate an access violation if accessed for read
763
764		Parameters:
765
766		ptr - the pointer to examine
767
768		size - the number of bytes to reference
769
770		Return value:
771
772		TRUE if an access to the referenced memory will generate an access
773		violation on a read; FALSE otherwise.
774
775		Notes:
776
777		This function will eventually be deprecated.
778		-----------------------------------------------------------------------------*/
779		int osd_is_bad_read_ptr(const void *ptr, size_t size);
780
781
782		/*-----------------------------------------------------------------------------
783	761	osd_break_into_debugger: break into the hosting system's debugger if one
784	762	is attached
785	763

src/osd/windows/winmisc.c
r5534	r5535
41	41
42	42
43	43	//============================================================
44		// osd_is_bad_read_ptr
45		//============================================================
46
47		int osd_is_bad_read_ptr(const void *ptr, size_t size)
48		{
49		return IsBadReadPtr(ptr, size);
50		}
51
52
53		//============================================================
54	44	// osd_break_into_debugger
55	45	//============================================================
56	46

src/emu/cpu/h83002/h8disasm.c
r5534	r5535
1274	1274	return size;
1275	1275	}
1276	1276
	1277	CPU_DISASSEMBLE(h8)
	1278	{
	1279	return h8_disasm(buffer, pc, oprom, opram, 0xffff);
	1280	}
1277	1281
	1282	// disassembly hook for varients with 24-bit address bus (e.g. H8/3044)
	1283	CPU_DISASSEMBLE(h8_24)
	1284	{
	1285	return h8_disasm(buffer, pc, oprom, opram, 0xffffff);
	1286	}
	1287
	1288	// disassembly hook for full 32-bit address bus
	1289	CPU_DISASSEMBLE(h8_32)
	1290	{
	1291	return h8_disasm(buffer, pc, oprom, opram, 0xffffffff);
	1292	}
	1293

src/emu/cpu/h83002/h8_16.c
r5534	r5535
17	17	#include "h8.h"
18	18	#include "h8priv.h"
19	19
	20	CPU_DISASSEMBLE(h8_24);
	21	CPU_DISASSEMBLE(h8_32);
	22
20	23	#define H8_SP (7)
21	24
22	25	#define h8_mem_read8(x) memory_read_byte(h8->program, x)
r5534	r5535
53	56
54	57	extern offs_t h8_disasm(char output, offs_t address, const UINT8 oprom, const UINT8 *opram, UINT32 addr_mask);
55	58
56		// disassembly hook for varients with 24-bit address bus (e.g. H8/3044)
57		static CPU_DISASSEMBLE(h8_24)
58		{
59		return h8_disasm(buffer, pc, oprom, opram, 0xffffff);
60		}
61
62		// disassembly hook for full 32-bit address bus
63		static CPU_DISASSEMBLE(h8_32)
64		{
65		return h8_disasm(buffer, pc, oprom, opram, 0xffffffff);
66		}
67
68	59	void h8_3002_InterruptRequest(h83xx_state *h8, UINT8 source, UINT8 state)
69	60	{
70	61	// don't allow clear on external interrupts

src/emu/cpu/h83002/h8_8.c
r5534	r5535
13	13	#include "h8.h"
14	14	#include "h8priv.h"
15	15
	16	CPU_DISASSEMBLE(h8);
	17
16	18	#define H8_SP (7)
17	19
18	20	#define h8_mem_read8(x) memory_read_byte(h8->program, x)
r5534	r5535
71	73
72	74	/* implementation */
73	75
74		extern offs_t h8_disasm(char buffer, offs_t pc, const UINT8 oprom, const UINT8 *opram, UINT32 addrmask);
75
76		static CPU_DISASSEMBLE(h8)
77		{
78		return h8_disasm(buffer, pc, oprom, opram, 0xffff);
79		}
80
81	76	static void h8_300_InterruptRequest(h83xx_state *h8, UINT8 source, UINT8 mode)
82	77	{
83	78	if (source>31)

src/emu/cpu/m68000/m68kdasm.c
r5534	r5535
3715	3715	}
3716	3716	#endif
3717	3717
	3718	CPU_DISASSEMBLE( m68000 )
	3719	{
	3720	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68000);
	3721	}
3718	3722
	3723	CPU_DISASSEMBLE( m68008 )
	3724	{
	3725	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68008);
	3726	}
	3727
	3728	CPU_DISASSEMBLE( m68010 )
	3729	{
	3730	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68010);
	3731	}
	3732
	3733	CPU_DISASSEMBLE( m68020 )
	3734	{
	3735	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68020);
	3736	}
	3737
	3738	CPU_DISASSEMBLE( m68030 )
	3739	{
	3740	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68030);
	3741	}
	3742
	3743	CPU_DISASSEMBLE( m68040 )
	3744	{
	3745	return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68040);
	3746	}
	3747
	3748
	3749
3719	3750	/* ======================================================================== */
3720	3751	/* ============================== END OF FILE ============================= */
3721	3752	/* ======================================================================== */

src/emu/cpu/tms32031/dis32031.c
r5534	r5535
731	731
732	732	return 1 \| flags \| DASMFLAG_SUPPORTED;
733	733	}
	734
	735
	736	CPU_DISASSEMBLE( tms32031 )
	737	{
	738	UINT32 op = oprom[0] \| (oprom[1] << 8) \| (oprom[2] << 16) \| (oprom[3] << 24);
	739	return dasm_tms32031(buffer, pc, op);
	740	}

src/emu/cpu/tms32031/tms32031.c
r5534	r5535
10	10	#include "tms32031.h"
11	11	#include "eminline.h"
12	12
	13	CPU_DISASSEMBLE( tms32031 );
13	14
14	15	#define LOG_OPCODE_USAGE (0)
15	16
r5534	r5535
536	537
537	538
538	539	/***************************************************************************
539		DISASSEMBLY HOOK
540		***************************************************************************/
541
542		static CPU_DISASSEMBLE( tms32031 )
543		{
544		UINT32 op = oprom[0] \| (oprom[1] << 8) \| (oprom[2] << 16) \| (oprom[3] << 24);
545		extern unsigned dasm_tms32031(char *, unsigned, UINT32);
546		return dasm_tms32031(buffer, pc, op);
547		}
548
549
550
551		/***************************************************************************
552	540	BOOT LOADER
553	541	***************************************************************************/
554	542

src/emu/cpu/superfx/superfx.h
r0	r5535
	1	#ifndef __SUPERFX_H__
	2	#define __SUPERFX_H__
	3
	4	enum
	5	{
	6	SUPERFX_PC = 1,
	7
	8	SUPERFX_DREG,
	9	SUPERFX_SREG,
	10
	11	SUPERFX_R0,
	12	SUPERFX_R1,
	13	SUPERFX_R2,
	14	SUPERFX_R3,
	15	SUPERFX_R4,
	16	SUPERFX_R5,
	17	SUPERFX_R6,
	18	SUPERFX_R7,
	19	SUPERFX_R8,
	20	SUPERFX_R9,
	21	SUPERFX_R10,
	22	SUPERFX_R11,
	23	SUPERFX_R12,
	24	SUPERFX_R13,
	25	SUPERFX_R14,
	26	SUPERFX_R15,
	27
	28	SUPERFX_PBR,
	29	SUPERFX_SFR,
	30	SUPERFX_ROMBR,
	31	SUPERFX_RAMBR,
	32	SUPERFX_CBR,
	33	SUPERFX_SCBR,
	34	SUPERFX_SCMR,
	35	SUPERFX_COLR,
	36	SUPERFX_POR,
	37	SUPERFX_BRAMR,
	38	SUPERFX_VCR,
	39	SUPERFX_CFGR,
	40	SUPERFX_CLSR,
	41
	42	SUPERFX_ROMCL,
	43	SUPERFX_ROMDR,
	44
	45	SUPERFX_RAMCL,
	46	SUPERFX_RAMAR,
	47	SUPERFX_RAMDR,
	48	SUPERFX_RAMADDR,
	49	};
	50
	51	#define SUPERFX_SFR_IRQ 0x8000 // Interrupt Flag
	52	#define SUPERFX_SFR_B 0x1000 // WITH Flag
	53	#define SUPERFX_SFR_IH 0x0800 // Immediate Higher 8-bit Flag
	54	#define SUPERFX_SFR_IL 0x0400 // Immediate Lower 8-bit Flag
	55	#define SUPERFX_SFR_ALT 0x0300 // ALT Mode, both bits
	56	#define SUPERFX_SFR_ALT0 0x0000 // ALT Mode, no bits
	57	#define SUPERFX_SFR_ALT1 0x0100 // ALT Mode, bit 0
	58	#define SUPERFX_SFR_ALT2 0x0200 // ALT Mode, bit 1
	59	#define SUPERFX_SFR_ALT3 0x0300 // ALT Mode, both bits (convenience dupe)
	60	#define SUPERFX_SFR_R 0x0040 // ROM R14 Read Flag
	61	#define SUPERFX_SFR_G 0x0020 // GO Flag
	62	#define SUPERFX_SFR_OV 0x0010 // Overflow Flag
	63	#define SUPERFX_SFR_S 0x0008 // Sign Flag
	64	#define SUPERFX_SFR_CY 0x0004 // Carry Flag
	65	#define SUPERFX_SFR_Z 0x0002 // Zero Flag
	66
	67	#define SUPERFX_POR_OBJ 0x10
	68	#define SUPERFX_POR_FREEZEHIGH 0x08
	69	#define SUPERFX_POR_HIGHNIBBLE 0x04
	70	#define SUPERFX_POR_DITHER 0x02
	71	#define SUPERFX_POR_TRANSPARENT 0x01
	72
	73	#define SUPERFX_SCMR_HT_MASK 0x24
	74	#define SUPERFX_SCMR_HT0 0x00
	75	#define SUPERFX_SCMR_HT1 0x04
	76	#define SUPERFX_SCMR_HT2 0x20
	77	#define SUPERFX_SCMR_HT3 0x24
	78	#define SUPERFX_SCMR_RON 0x10
	79	#define SUPERFX_SCMR_RAN 0x08
	80	#define SUPERFX_SCMR_MD 0x03
	81
	82	#define SUPERFX_CFGR_IRQ 0x80 // IRQ
	83	#define SUPERFX_CFGR_MS0 0x20 // MS0
	84
	85	CPU_GET_INFO( superfx );
	86	#define CPU_SUPERFX CPU_GET_INFO_NAME( superfx )
	87
	88	CPU_DISASSEMBLE( superfx );
	89	extern offs_t superfx_dasm_one(char *buffer, offs_t pc, UINT8 op, UINT8 param0, UINT8 param1, UINT16 alt);
	90
	91	UINT8 superfx_mmio_read(const device_config *cpu, UINT32 addr);
	92	void superfx_mmio_write(const device_config *cpu, UINT32 addr, UINT8 data);
	93	void superfx_add_clocks(const device_config *cpu, INT32 clocks);
	94
	95	#endif /* __SUPERFX_H__ */

src/emu/cpu/superfx/sfx_dasm.c
r0	r5535
	1	#include "cpuintrf.h"
	2	#include "superfx.h"
	3	#include <stdarg.h>
	4
	5	static char *output;
	6
	7	static void ATTR_PRINTF(1,2) print(const char *fmt, ...)
	8	{
	9	va_list vl;
	10
	11	va_start(vl, fmt);
	12	output += vsprintf(output, fmt, vl);
	13	va_end(vl);
	14	}
	15
	16	offs_t superfx_dasm_one(char *buffer, offs_t pc, UINT8 op, UINT8 param0, UINT8 param1, UINT16 alt)
	17	{
	18	UINT8 bytes_consumed = 1;
	19	output = buffer;
	20
	21	switch(op)
	22	{
	23	case 0x00: // STOP
	24	print("STOP");
	25	break;
	26	case 0x01: // NOP
	27	print("NOP");
	28	break;
	29	case 0x02: // CACHE
	30	print("CACHE");
	31	break;
	32	case 0x03: // LSR
	33	print("LSR");
	34	break;
	35	case 0x04: // ROL
	36	print("ROL");
	37	break;
	38	case 0x05: // BRA
	39	print("BRA %d", (INT8)param0);
	40	bytes_consumed = 2;
	41	break;
	42	case 0x06: // BLT
	43	print("BLT %d", (INT8)param0);
	44	bytes_consumed = 2;
	45	break;
	46	case 0x07: // BGE
	47	print("BGE %d", (INT8)param0);
	48	bytes_consumed = 2;
	49	break;
	50	case 0x08: // BNE
	51	print("BNE %d", (INT8)param0);
	52	bytes_consumed = 2;
	53	break;
	54	case 0x09: // BEQ
	55	print("BEQ %d", (INT8)param0);
	56	bytes_consumed = 2;
	57	break;
	58	case 0x0a: // BPL
	59	print("BPL %d", (INT8)param0);
	60	bytes_consumed = 2;
	61	break;
	62	case 0x0b: // BMI
	63	print("BMI %d", (INT8)param0);
	64	bytes_consumed = 2;
	65	break;
	66	case 0x0c: // BCC
	67	print("BCC %d", (INT8)param0);
	68	bytes_consumed = 2;
	69	break;
	70	case 0x0d: // BCS
	71	print("BCS %d", (INT8)param0);
	72	bytes_consumed = 2;
	73	break;
	74	case 0x0e: // BVC
	75	print("BVC %d", (INT8)param0);
	76	bytes_consumed = 2;
	77	break;
	78	case 0x0f: // BVS
	79	print("BVS %d", (INT8)param0);
	80	bytes_consumed = 2;
	81	break;
	82
	83	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
	84	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: // TO
	85	print("TO R%d", op & 0xf);
	86	break;
	87
	88	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
	89	case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: // WITH
	90	print("WITH R%d", op & 0xf);
	91	break;
	92
	93	case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35:
	94	case 0x36: case 0x37: case 0x38: case 0x39: case 0x3a: case 0x3b: // STW_IR / STB_IR
	95	switch(alt)
	96	{
	97	case SUPERFX_SFR_ALT0:
	98	case SUPERFX_SFR_ALT2:
	99	print("STW (R%d)", op & 0xf);
	100	break;
	101	case SUPERFX_SFR_ALT1:
	102	case SUPERFX_SFR_ALT3:
	103	print("STB (R%d)", op & 0xf);
	104	break;
	105	}
	106	break;
	107
	108	case 0x3c: // LOOP
	109	print("LOOP");
	110	break;
	111	case 0x3d: // ALT1
	112	print("ALT1");
	113	break;
	114	case 0x3e: // ALT2
	115	print("ALT2");
	116	break;
	117	case 0x3f: // ALT3
	118	print("ALT3");
	119	break;
	120
	121	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45:
	122	case 0x46: case 0x47: case 0x48: case 0x49: case 0x4a: case 0x4b: // LDW_IR / LDB_IR
	123	switch(alt)
	124	{
	125	case SUPERFX_SFR_ALT0:
	126	case SUPERFX_SFR_ALT2:
	127	print("LDW (R%d)", op & 0xf);
	128	break;
	129	case SUPERFX_SFR_ALT1:
	130	case SUPERFX_SFR_ALT3:
	131	print("LDB (R%d)", op & 0xf);
	132	break;
	133	}
	134	break;
	135
	136	case 0x4c: // PLOT / RPIX
	137	switch(alt)
	138	{
	139	case SUPERFX_SFR_ALT0:
	140	case SUPERFX_SFR_ALT2:
	141	print("PLOT");
	142	break;
	143	case SUPERFX_SFR_ALT1:
	144	case SUPERFX_SFR_ALT3:
	145	print("RPIX");
	146	break;
	147	}
	148	break;
	149
	150	case 0x4d: // SWAP
	151	print("SWAP");
	152	break;
	153
	154	case 0x4e: // COLOR / CMODE
	155	switch(alt)
	156	{
	157	case SUPERFX_SFR_ALT0:
	158	case SUPERFX_SFR_ALT2:
	159	print("COLOR");
	160	break;
	161	case SUPERFX_SFR_ALT1:
	162	case SUPERFX_SFR_ALT3:
	163	print("CMODE");
	164	break;
	165	}
	166	break;
	167
	168	case 0x4f: // NOT
	169	print("NOT");
	170	break;
	171
	172	case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
	173	case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: // ADD / ADC / ADDI / ADCI
	174	switch(alt)
	175	{
	176	case SUPERFX_SFR_ALT0:
	177	print("ADD R%d", op &0xf);
	178	break;
	179	case SUPERFX_SFR_ALT1:
	180	print("ADC R%d", op &0xf);
	181	break;
	182	case SUPERFX_SFR_ALT2:
	183	print("ADDI R%d", op &0xf);
	184	break;
	185	case SUPERFX_SFR_ALT3:
	186	print("ADCI R%d", op &0xf);
	187	break;
	188	}
	189	break;
	190
	191	case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
	192	case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f: // SUB / SBC / SUBI / CMP
	193	switch(alt)
	194	{
	195	case SUPERFX_SFR_ALT0:
	196	print("SUB R%d", op &0xf);
	197	break;
	198	case SUPERFX_SFR_ALT1:
	199	print("SBC R%d", op &0xf);
	200	break;
	201	case SUPERFX_SFR_ALT2:
	202	print("SUBI R%d", op &0xf);
	203	break;
	204	case SUPERFX_SFR_ALT3:
	205	print("CMP R%d", op &0xf);
	206	break;
	207	}
	208	break;
	209
	210	case 0x70: // MERGE
	211	print("MERGE");
	212	break;
	213
	214	case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
	215	case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: // AND / BIC / ANDI / BICI
	216	switch(alt)
	217	{
	218	case SUPERFX_SFR_ALT0:
	219	print("AND R%d", op &0xf);
	220	break;
	221	case SUPERFX_SFR_ALT1:
	222	print("BIC R%d", op &0xf);
	223	break;
	224	case SUPERFX_SFR_ALT2:
	225	print("ANDI R%d", op &0xf);
	226	break;
	227	case SUPERFX_SFR_ALT3:
	228	print("BICI R%d", op &0xf);
	229	break;
	230	}
	231	break;
	232
	233	case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
	234	case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f: // MULT / UMULT / MULTI / UMULTI
	235	switch(alt)
	236	{
	237	case SUPERFX_SFR_ALT0:
	238	print("MULT R%d", op &0xf);
	239	break;
	240	case SUPERFX_SFR_ALT1:
	241	print("UMULT R%d", op &0xf);
	242	break;
	243	case SUPERFX_SFR_ALT2:
	244	print("MULTI R%d", op &0xf);
	245	break;
	246	case SUPERFX_SFR_ALT3:
	247	print("UMULTI R%d", op &0xf);
	248	break;
	249	}
	250	break;
	251
	252	case 0x90: // SBK
	253	print("SBK");
	254	break;
	255
	256	case 0x91: case 0x92: case 0x93: case 0x94: // LINK
	257	print("LINK %d", op & 0xf);
	258	break;
	259
	260	case 0x95: // SEX
	261	print("SEX");
	262	break;
	263
	264	case 0x96: // ASR / DIV2
	265	switch(alt)
	266	{
	267	case SUPERFX_SFR_ALT0:
	268	case SUPERFX_SFR_ALT2:
	269	print("ASR");
	270	break;
	271	case SUPERFX_SFR_ALT1:
	272	case SUPERFX_SFR_ALT3:
	273	print("DIV2");
	274	break;
	275	}
	276	break;
	277
	278	case 0x97: // ROR
	279	print("ROR");
	280	break;
	281
	282	case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: // JMP / LJMP
	283	switch(alt)
	284	{
	285	case SUPERFX_SFR_ALT0:
	286	case SUPERFX_SFR_ALT2:
	287	print("JMP R%d", op & 0xf);
	288	break;
	289	case SUPERFX_SFR_ALT1:
	290	case SUPERFX_SFR_ALT3:
	291	print("LJMP R%d", op & 0xf);
	292	break;
	293	}
	294	break;
	295
	296	case 0x9e: // LOB
	297	print("LOB");
	298	break;
	299
	300	case 0x9f: // FMULT / LMULT
	301	switch(alt)
	302	{
	303	case SUPERFX_SFR_ALT0:
	304	case SUPERFX_SFR_ALT2:
	305	print("FMULT R%d", op & 0xf);
	306	break;
	307	case SUPERFX_SFR_ALT1:
	308	case SUPERFX_SFR_ALT3:
	309	print("LMULT R%d", op & 0xf);
	310	break;
	311	}
	312	break;
	313
	314	case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
	315	case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf: // IBT / LMS / SMS / LML
	316	switch(alt)
	317	{
	318	case SUPERFX_SFR_ALT0:
	319	print("IBT R%d,0x%02x", op & 0xf, param0);
	320	break;
	321	case SUPERFX_SFR_ALT2:
	322	print("SMS R%d,(0x%04x)", op & 0xf, param0 << 1);
	323	break;
	324	case SUPERFX_SFR_ALT1:
	325	case SUPERFX_SFR_ALT3:
	326	print("LMS R%d,(0x%04x)", op & 0xf, param0 << 1);
	327	break;
	328	}
	329	bytes_consumed = 2;
	330	break;
	331
	332	case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
	333	case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf: // FROM
	334	print("FROM R%d", op & 0xf);
	335	break;
	336
	337	case 0xc0: // HIB
	338	print("HIB");
	339	break;
	340
	341	case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
	342	case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: // OR / XOR / ORI / XORI
	343	switch(alt)
	344	{
	345	case SUPERFX_SFR_ALT0:
	346	print("OR R%d", op &0xf);
	347	break;
	348	case SUPERFX_SFR_ALT1:
	349	print("XOR R%d", op &0xf);
	350	break;
	351	case SUPERFX_SFR_ALT2:
	352	print("ORI R%d", op &0xf);
	353	break;
	354	case SUPERFX_SFR_ALT3:
	355	print("XORI R%d", op &0xf);
	356	break;
	357	}
	358	break;
	359
	360	case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
	361	case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: // INC
	362	print("INC R%d", op & 0xf);
	363	break;
	364
	365	case 0xdf: // GETC / RAMB / ROMB
	366	switch(alt)
	367	{
	368	case SUPERFX_SFR_ALT0:
	369	case SUPERFX_SFR_ALT1:
	370	print("GETC");
	371	break;
	372	case SUPERFX_SFR_ALT2:
	373	print("RAMB");
	374	break;
	375	case SUPERFX_SFR_ALT3:
	376	print("ROMB");
	377	break;
	378	}
	379	break;
	380
	381	case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
	382	case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: // DEC
	383	print("DEC R%d", op & 0xf);
	384	break;
	385
	386	case 0xef: // GETB / GETBH / GETBL / GETBS
	387	switch(alt)
	388	{
	389	case SUPERFX_SFR_ALT0:
	390	print("GETB");
	391	break;
	392	case SUPERFX_SFR_ALT1:
	393	print("GETBH");
	394	break;
	395	case SUPERFX_SFR_ALT2:
	396	print("GETBL");
	397	break;
	398	case SUPERFX_SFR_ALT3:
	399	print("GETBS");
	400	break;
	401	}
	402	break;
	403
	404	case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
	405	case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: // IWT / LM / SM / LM
	406	switch(alt)
	407	{
	408	case SUPERFX_SFR_ALT0:
	409	print("IWT R%d,#%02x%02x", op & 0xf, param1, param0);
	410	bytes_consumed = 3;
	411	break;
	412	case SUPERFX_SFR_ALT2:
	413	print("SM R%d", op & 0xf);
	414	break;
	415	case SUPERFX_SFR_ALT1:
	416	case SUPERFX_SFR_ALT3:
	417	print("LM R%d", op & 0xf);
	418	break;
	419	}
	420	break;
	421	}
	422
	423	return bytes_consumed \| DASMFLAG_SUPPORTED;
	424	}

src/emu/cpu/superfx/superfx.c
r0	r5535
	1	#include "cpuintrf.h"
	2	#include "debugger.h"
	3	#include "superfx.h"
	4
	5	typedef struct
	6	{
	7	UINT16 offset;
	8	UINT8 bitpend;
	9	UINT8 data[8];
	10	} pixelcache_t;
	11
	12	typedef struct
	13	{
	14	UINT8 buffer[0x200];
	15	UINT8 valid[0x20];
	16	} cache_t;
	17
	18	typedef struct _superfx_state superfx_state;
	19	struct _superfx_state
	20	{
	21	UINT8 pipeline;
	22
	23	UINT16 r[16]; // GPRs
	24	UINT16 sfr; // Status Flag Register
	25	UINT8 pbr; // Program Bank Register
	26	UINT8 rombr; // Game Pack ROM Bank Register
	27	UINT8 rambr; // Game Pack RAM Bank Register
	28	UINT16 cbr; // Cache Base Register
	29	UINT8 scbr; // Screen Base Register
	30	UINT8 scmr; // Screen Mode Register
	31	UINT8 colr; // Color Register
	32	UINT8 por; // Plot Option Register
	33	UINT8 bramr; // Back-Up RAM Register
	34	UINT8 vcr; // Version Code Register
	35	UINT8 cfgr; // Config Register
	36	UINT8 clsr; // Clock Select Register
	37
	38	UINT32 romcl; // Clock ticks until ROMDR is valid
	39	UINT8 romdr; // ROM Buffer Data Register
	40
	41	UINT32 ramcl; // Clock ticks until RAMDR is valid;
	42	UINT16 ramar; // RAM Buffer Address Register
	43	UINT8 ramdr; // RAM Buffer Data Register
	44	UINT16 ramaddr; // RAM Address
	45
	46	UINT16 *sreg; // Source Register (From)
	47	UINT8 sreg_idx;// Source Register (To), index
	48	UINT16 *dreg; // Destination Register (To)
	49	UINT8 dreg_idx;// Destination Register (To), index
	50	UINT8 r15_modified;
	51
	52	UINT8 irq; // IRQ Pending
	53
	54	UINT32 cache_access_speed;
	55	UINT32 memory_access_speed;
	56
	57	cache_t cache;
	58	pixelcache_t pixelcache[2];
	59
	60	const device_config *device;
	61	const address_space *program;
	62	int icount;
	63	};
	64
	65	INLINE superfx_state get_safe_token(const device_config device)
	66	{
	67	assert(device != NULL);
	68	assert(device->token != NULL);
	69	assert(device->type == CPU);
	70	assert(cpu_get_type(device) == CPU_SUPERFX);
	71	return (superfx_state *)device->token;
	72	}
	73
	74	/*****************************************************************************/
	75
	76	static void superfx_regs_reset(superfx_state *cpustate);
	77	static void superfx_update_speed(superfx_state *cpustate);
	78	static void superfx_cache_flush(superfx_state *cpustate);
	79	static UINT8 superfx_cache_mmio_read(superfx_state *cpustate, UINT16 addr);
	80	static void superfx_cache_mmio_write(superfx_state *cpustate, UINT32 addr, UINT8 data);
	81	static void superfx_memory_reset(superfx_state *cpustate);
	82	static UINT8 superfx_bus_read(superfx_state *cpustate, UINT32 addr);
	83	static void superfx_bus_write(superfx_state *cpustate, UINT32 addr, UINT8 data);
	84	static void superfx_pixelcache_flush(superfx_state *cpustate, INT32 line);
	85	static void superfx_plot(superfx_state *cpustate, UINT8 x, UINT8 y);
	86	static UINT8 superfx_rpix(superfx_state *cpustate, UINT16 r1, UINT16 r2);
	87	static UINT8 superfx_color(superfx_state *cpustate, UINT8 source);
	88	static UINT8 superfx_rambuffer_sync(superfx_state *cpustate);
	89	static UINT8 superfx_rambuffer_read(superfx_state *cpustate, UINT16 addr);
	90	static void superfx_rambuffer_write(superfx_state *cpustate, UINT16 addr, UINT8 val);
	91	static void superfx_rombuffer_sync(superfx_state *cpustate);
	92	static void superfx_rombuffer_update(superfx_state *cpustate);
	93	static UINT8 superfx_rombuffer_read(superfx_state *cpustate);
	94	static void superfx_gpr_write(superfx_state *cpustate, UINT8 r, UINT16 data);
	95	INLINE UINT8 superfx_op_read(superfx_state *cpustate, UINT16 addr);
	96	INLINE UINT8 superfx_peekpipe(superfx_state *cpustate);
	97	INLINE UINT8 superfx_pipe(superfx_state *cpustate);
	98	static void superfx_add_clocks_internal(superfx_state *cpustate, INT32 clocks);
	99	static void superfx_timing_reset(superfx_state *cpustate);
	100
	101	/*****************************************************************************/
	102
	103	#define SUPERFX_SFR_OV_SET ((cpustate->sfr & SUPERFX_SFR_OV) ? 1 : 0)
	104	#define SUPERFX_SFR_OV_CLEAR ((cpustate->sfr & SUPERFX_SFR_OV) ? 0 : 1)
	105	#define SUPERFX_SFR_S_SET ((cpustate->sfr & SUPERFX_SFR_S) ? 1 : 0)
	106	#define SUPERFX_SFR_S_CLEAR ((cpustate->sfr & SUPERFX_SFR_S) ? 0 : 1)
	107	#define SUPERFX_SFR_CY_SET ((cpustate->sfr & SUPERFX_SFR_CY) ? 1 : 0)
	108	#define SUPERFX_SFR_CY_CLEAR ((cpustate->sfr & SUPERFX_SFR_CY) ? 0 : 1)
	109	#define SUPERFX_SFR_Z_SET ((cpustate->sfr & SUPERFX_SFR_Z) ? 1 : 0)
	110	#define SUPERFX_SFR_Z_CLEAR ((cpustate->sfr & SUPERFX_SFR_Z) ? 0 : 1)
	111
	112	static void superfx_regs_reset(superfx_state *cpustate)
	113	{
	114	cpustate->sfr &= ~(SUPERFX_SFR_B \| SUPERFX_SFR_ALT3);
	115
	116	cpustate->sreg = &cpustate->r[0];
	117	cpustate->dreg = &cpustate->r[0];
	118	cpustate->dreg_idx = 0;
	119	cpustate->sreg_idx = 0;
	120	}
	121
	122	static void superfx_update_speed(superfx_state *cpustate)
	123	{
	124	cpustate->cache_access_speed = (cpustate->clsr ? 1 : 2);
	125	cpustate->memory_access_speed = (cpustate->clsr ? 5 : 6);
	126	if(cpustate->clsr)
	127	{
	128	cpustate->cfgr &= ~SUPERFX_CFGR_MS0; // Cannot use high-speed multiplication in 21MHz mode
	129	}
	130	}
	131
	132	static void superfx_cache_flush(superfx_state *cpustate)
	133	{
	134	UINT32 n = 0;
	135	for(n = 0; n < 32; n++)
	136	{
	137	cpustate->cache.valid[n] = 0;
	138	}
	139	}
	140
	141	static UINT8 superfx_cache_mmio_read(superfx_state *cpustate, UINT16 addr)
	142	{
	143	addr = (addr + cpustate->cbr) & 0x1ff;
	144	return cpustate->cache.buffer[addr];
	145	}
	146
	147	static void superfx_cache_mmio_write(superfx_state *cpustate, UINT32 addr, UINT8 data)
	148	{
	149	addr = (addr + cpustate->cbr) & 0x1ff;
	150	cpustate->cache.buffer[addr] = data;
	151	if((addr & 15) == 15)
	152	{
	153	cpustate->cache.valid[addr >> 4] = 1;
	154	}
	155	}
	156
	157	static void superfx_memory_reset(superfx_state *cpustate)
	158	{
	159	UINT32 n = 0;
	160	for(n = 0; n < 0x200; n++)
	161	{
	162	cpustate->cache.buffer[n] = 0x00;
	163	}
	164	for(n = 0; n < 0x20; n++)
	165	{
	166	cpustate->cache.valid[n] = 0;
	167	}
	168	for(n = 0; n < 2; n++)
	169	{
	170	cpustate->pixelcache[n].offset = ~0;
	171	cpustate->pixelcache[n].bitpend = 0x00;
	172	}
	173	}
	174
	175	static UINT8 superfx_bus_read(superfx_state *cpustate, UINT32 addr)
	176	{
	177	//printf( "superfx_bus_read: %08x\n", addr );
	178	return memory_read_byte(cpustate->program, addr);
	179	}
	180
	181	static void superfx_bus_write(superfx_state *cpustate, UINT32 addr, UINT8 data)
	182	{
	183	memory_write_byte(cpustate->program, addr, data);
	184	//printf( "superfx_bus_write: %08x = %02x\n", addr, data );
	185	// TODO: Hook up to the same memory map as the main 65C816 CPU. See src/chip/superfx/bus/bus.cpp in the bsnes source code.
	186	}
	187
	188	static void superfx_pixelcache_flush(superfx_state *cpustate, INT32 line)
	189	{
	190	UINT8 x = cpustate->pixelcache[line].offset << 3;
	191	UINT8 y = cpustate->pixelcache[line].offset >> 5;
	192	UINT32 cn = 0;
	193	UINT32 bpp = 2 << ((cpustate->scmr & SUPERFX_SCMR_MD) - ((cpustate->scmr & SUPERFX_SCMR_MD) >> 1)); // = [regs.scmr.md]{ 2, 4, 4, 8 };
	194	UINT32 addr = 0;
	195	UINT32 n = 0;
	196
	197	if(cpustate->pixelcache[line].bitpend == 0x00)
	198	{
	199	return;
	200	}
	201
	202	switch((cpustate->por & SUPERFX_POR_OBJ) ? SUPERFX_SCMR_HT3 : (cpustate->scmr & SUPERFX_SCMR_HT_MASK))
	203	{
	204	case SUPERFX_SCMR_HT0:
	205	cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 3);
	206	break;
	207	case SUPERFX_SCMR_HT1:
	208	cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 1) + ((y & 0xf8) >> 3);
	209	break;
	210	case SUPERFX_SCMR_HT2:
	211	cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 0) + ((y & 0xf8) >> 3);
	212	break;
	213	case SUPERFX_SCMR_HT3:
	214	cn = ((y & 0x80) << 2) + ((x & 0x80) << 1) + ((y & 0x78) << 1) + ((x & 0x78) >> 2);
	215	break;
	216	}
	217
	218	addr = 0x700000 + (cn * (bpp << 3)) + (cpustate->scbr << 10) + ((y & 0x07) * 2);
	219
	220	for(n = 0; n < bpp; n++)
	221	{
	222	UINT8 byte = ((n >> 1) << 4) + (n & 1); // = [n]{ 0, 1, 16, 17, 32, 33, 48, 49 };
	223	UINT8 data = 0x00;
	224	UINT32 x = 0;
	225	for(x = 0; x < 8; x++)
	226	{
	227	data \|= ((cpustate->pixelcache[line].data[x] >> n) & 1) << x;
	228	}
	229	if(cpustate->pixelcache[line].bitpend != 0xff)
	230	{
	231	superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
	232	data &= cpustate->pixelcache[line].bitpend;
	233	//printf( "superfx_pixelcache_flush: calling superfx_bus_read\n" );
	234	data \|= superfx_bus_read(cpustate, addr + byte) & ~cpustate->pixelcache[line].bitpend;
	235	}
	236	superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
	237	superfx_bus_write(cpustate, addr + byte, data);
	238	}
	239
	240	cpustate->pixelcache[line].bitpend = 0x00;
	241	}
	242
	243	static void superfx_plot(superfx_state *cpustate, UINT8 x, UINT8 y)
	244	{
	245	UINT8 color = cpustate->colr;
	246	UINT16 offset = (y << 5) + (x >> 3);
	247
	248	printf( "plot: %02x at %d, %d\n", color, x, y );
	249
	250	if((cpustate->por & SUPERFX_POR_DITHER) && ((cpustate->scmr & SUPERFX_SCMR_MD) != 3))
	251	{
	252	if((x ^ y) & 1)
	253	{
	254	color >>= 4;
	255	}
	256	color &= 0x0f;
	257	}
	258
	259	if(!(cpustate->por & SUPERFX_POR_TRANSPARENT))
	260	{
	261	if((cpustate->scmr & SUPERFX_SCMR_MD) == 3)
	262	{
	263	if(cpustate->por & SUPERFX_POR_FREEZEHIGH)
	264	{
	265	if((color & 0x0f) == 0)
	266	{
	267	return;
	268	}
	269	}
	270	else
	271	{
	272	if(color == 0)
	273	{
	274	return;
	275	}
	276	}
	277	}
	278	else
	279	{
	280	if((color & 0x0f) == 0)
	281	{
	282	return;
	283	}
	284	}
	285	}
	286
	287	if(offset != cpustate->pixelcache[0].offset)
	288	{
	289	superfx_pixelcache_flush(cpustate, 1);
	290	cpustate->pixelcache[1] = cpustate->pixelcache[0];
	291	cpustate->pixelcache[0].bitpend = 0x00;
	292	cpustate->pixelcache[0].offset = offset;
	293	}
	294
	295	x = (x & 7) ^ 7;
	296	cpustate->pixelcache[0].data[x] = color;
	297	cpustate->pixelcache[0].bitpend \|= 1 << x;
	298	if(cpustate->pixelcache[0].bitpend == 0xff)
	299	{
	300	superfx_pixelcache_flush(cpustate, 1);
	301	cpustate->pixelcache[1] = cpustate->pixelcache[0];
	302	cpustate->pixelcache[0].bitpend = 0x00;
	303	}
	304	}
	305
	306	static UINT8 superfx_rpix(superfx_state *cpustate, UINT16 x, UINT16 y)
	307	{
	308	UINT32 cn = 0;
	309	UINT32 bpp = 2 << ((cpustate->scmr & SUPERFX_SCMR_MD) - ((cpustate->scmr & SUPERFX_SCMR_MD) >> 1)); // = [regs.scmr.md]{ 2, 4, 4, 8 };
	310	UINT32 addr = 0;
	311	UINT8 data = 0x00;
	312	UINT32 n = 0;
	313
	314	superfx_pixelcache_flush(cpustate, 1);
	315	superfx_pixelcache_flush(cpustate, 0);
	316
	317	switch((cpustate->por & SUPERFX_POR_OBJ) ? SUPERFX_SCMR_HT3 : (cpustate->scmr & SUPERFX_SCMR_HT_MASK))
	318	{
	319	case SUPERFX_SCMR_HT0:
	320	cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 3);
	321	break;
	322	case SUPERFX_SCMR_HT1:
	323	cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 1) + ((y & 0xf8) >> 3);
	324	break;
	325	case SUPERFX_SCMR_HT2:
	326	cn = ((x & 0xf8) << 1) + ((y & 0xf8) >> 0) + ((y & 0xf8) >> 3);
	327	break;
	328	case SUPERFX_SCMR_HT3:
	329	cn = ((y & 0x80) << 2) + ((x & 0x80) << 1) + ((y & 0x78) << 1) + ((x & 0x78) >> 2);
	330	break;
	331	}
	332
	333	addr = 0x700000 + (cn * (bpp << 3)) + (cpustate->scbr << 10) + ((y & 0x07) * 2);
	334	x = (x & 7) ^ 7;
	335
	336	for(n = 0; n < bpp; n++)
	337	{
	338	UINT8 byte = ((n >> 1) << 4) + (n & 1); // = [n]{ 0, 1, 16, 17, 32, 33, 48, 49 };
	339	superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
	340	//printf( "superfx_rpix: calling superfx_bus_read\n" );
	341	data \|= ((superfx_bus_read(cpustate, addr + byte) >> x) & 1) << n;
	342	}
	343
	344	return data;
	345	}
	346
	347	static UINT8 superfx_color(superfx_state *cpustate, UINT8 source)
	348	{
	349	if(cpustate->por & SUPERFX_POR_HIGHNIBBLE)
	350	{
	351	return (cpustate->colr & 0xf0) \| (source >> 4);
	352	}
	353	if(cpustate->por & SUPERFX_POR_FREEZEHIGH)
	354	{
	355	return (cpustate->colr & 0xf0) \| (source & 0x0f);
	356	}
	357	return source;
	358	}
	359
	360	static UINT8 superfx_rambuffer_sync(superfx_state *cpustate)
	361	{
	362	if(cpustate->ramcl)
	363	{
	364	superfx_add_clocks_internal(cpustate, cpustate->ramcl);
	365	}
	366	return 0;
	367	}
	368
	369	static UINT8 superfx_rambuffer_read(superfx_state *cpustate, UINT16 addr)
	370	{
	371	//superfx_rambuffer_sync(cpustate);
	372	//printf( "superfx_rambuffer_read: calling superfx_bus_read\n" );
	373	return superfx_bus_read(cpustate, 0x700000 + (cpustate->rambr << 16) + addr);
	374	}
	375
	376	static void superfx_rambuffer_write(superfx_state *cpustate, UINT16 addr, UINT8 data)
	377	{
	378	superfx_bus_write(cpustate, 0x700000 + (cpustate->rambr << 16) + cpustate->ramar, cpustate->ramdr);
	379	//superfx_rambuffer_sync(cpustate);
	380	//cpustate->ramcl = cpustate->memory_access_speed;
	381	//cpustate->ramar = addr;
	382	//cpustate->ramdr = data;
	383	}
	384
	385	static void superfx_rombuffer_sync(superfx_state *cpustate)
	386	{
	387	//printf( "superfx_rombuffer_sync\n" );
	388	if(cpustate->romcl)
	389	{
	390	printf( "calling add_clocks_internal\n" );
	391	superfx_add_clocks_internal(cpustate, cpustate->romcl);
	392	}
	393	}
	394
	395	static void superfx_rombuffer_update(superfx_state *cpustate)
	396	{
	397	cpustate->sfr \|= SUPERFX_SFR_R;
	398	//printf( "superfx_rombuffer_update: setting romcl\n" );
	399	cpustate->romcl = cpustate->memory_access_speed;
	400	}
	401
	402	static UINT8 superfx_rombuffer_read(superfx_state *cpustate)
	403	{
	404	superfx_rombuffer_sync(cpustate);
	405	printf( "superfx_rombuffer_read: %02x\n", cpustate->romdr);
	406	return cpustate->romdr;
	407	}
	408
	409	static void superfx_gpr_write(superfx_state *cpustate, UINT8 r, UINT16 data)
	410	{
	411	cpustate->r[r] = data;
	412	if(r == 14)
	413	{
	414	superfx_rombuffer_update(cpustate);
	415	}
	416	else if(r == 15)
	417	{
	418	cpustate->r15_modified = 1;
	419	}
	420	}
	421
	422	INLINE UINT8 superfx_op_read(superfx_state *cpustate, UINT16 addr)
	423	{
	424	UINT16 offset = addr - cpustate->cbr;
	425	if(offset < 512)
	426	{
	427	if(!cpustate->cache.valid[offset >> 4])
	428	{
	429	UINT32 dp = offset & 0xfff0;
	430	UINT32 sp = (cpustate->pbr << 16) + ((cpustate->cbr + dp) & 0xfff0);
	431	UINT32 n = 0;
	432	for(n = 0; n < 16; n++)
	433	{
	434	superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
	435	//printf( "superfx_op_read: caching superfx_bus_read value\n" );
	436	cpustate->cache.buffer[dp++] = superfx_bus_read(cpustate, sp++);
	437	}
	438	cpustate->cache.valid[offset >> 4] = 1;
	439	}
	440	else
	441	{
	442	superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
	443	}
	444	return cpustate->cache.buffer[offset];
	445	}
	446
	447	if(cpustate->pbr <= 0x5f)
	448	{
	449	//$[00-5f]:[0000-ffff] ROM
	450	superfx_rombuffer_sync(cpustate);
	451	superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
	452	//printf( "superfx_op_read: reading from rom, calling superfx_bus_read\n" );
	453	return superfx_bus_read(cpustate, (cpustate->pbr << 16) + addr);
	454	}
	455	else
	456	{
	457	//$[60-7f]:[0000-ffff] RAM
	458	superfx_rambuffer_sync(cpustate);
	459	superfx_add_clocks_internal(cpustate, cpustate->memory_access_speed);
	460	//printf( "superfx_op_read: reading from ram, calling superfx_bus_read\n" );
	461	return superfx_bus_read(cpustate, (cpustate->pbr << 16) + addr);
	462	}
	463	}
	464
	465	INLINE UINT8 superfx_peekpipe(superfx_state *cpustate)
	466	{
	467	UINT8 result = cpustate->pipeline;
	468	cpustate->pipeline = superfx_op_read(cpustate, cpustate->r[15]);
	469	cpustate->r15_modified = 0;
	470	return result;
	471	}
	472
	473	INLINE UINT8 superfx_pipe(superfx_state *cpustate)
	474	{
	475	UINT8 result = cpustate->pipeline;
	476	cpustate->pipeline = superfx_op_read(cpustate, ++cpustate->r[15]);
	477	cpustate->r15_modified = 0;
	478	return result;
	479	}
	480
	481	/*****************************************************************************/
	482
	483	UINT8 superfx_mmio_read(const device_config *cpu, UINT32 addr)
	484	{
	485	superfx_state *cpustate = get_safe_token(cpu);
	486
	487	addr &= 0xffff;
	488
	489	if(addr != 0x3030)
	490	{
	491	//printf( "superfx_mmio_read: %08x\n", addr );
	492	}
	493
	494	if(addr >= 0x3100 && addr <= 0x32ff)
	495	{
	496	return superfx_cache_mmio_read(cpustate, addr - 0x3100);
	497	}
	498
	499	if(addr >= 0x3000 && addr <= 0x301f)
	500	{
	501	return cpustate->r[(addr >> 1) & 0xf] >> ((addr & 1) << 3);
	502	}
	503
	504	switch(addr)
	505	{
	506	case 0x3030:
	507	return cpustate->sfr >> 0;
	508
	509	case 0x3031:
	510	{
	511	UINT8 r = cpustate->sfr >> 8;
	512	cpustate->sfr &= ~SUPERFX_SFR_IRQ;
	513	cpustate->irq = 0;
	514	return r;
	515	}
	516
	517	case 0x3034:
	518	return cpustate->pbr;
	519
	520	case 0x3036:
	521	return cpustate->rombr;
	522
	523	case 0x303b:
	524	return cpustate->vcr;
	525
	526	case 0x303c:
	527	return cpustate->rambr;
	528
	529	case 0x303e:
	530	return cpustate->cbr >> 0;
	531
	532	case 0x303f:
	533	return cpustate->cbr >> 8;
	534	}
	535
	536	return 0;
	537	}
	538
	539	void superfx_mmio_write(const device_config *cpu, UINT32 addr, UINT8 data)
	540	{
	541	superfx_state *cpustate = get_safe_token(cpu);
	542
	543	//printf( "superfx_mmio_write: %08x = %02x\n", addr, data );
	544
	545	addr &= 0xffff;
	546
	547	if(addr >= 0x3100 && addr <= 0x32ff)
	548	{
	549	return superfx_cache_mmio_write(cpustate, addr - 0x3100, data);
	550	}
	551
	552	if(addr >= 0x3000 && addr <= 0x301f)
	553	{
	554	UINT32 n = (addr >> 1) & 0xf;
	555	if((addr & 1) == 0)
	556	{
	557	cpustate->r[n] = (cpustate->r[n] & 0xff00) \| data;
	558	}
	559	else
	560	{
	561	cpustate->r[n] = (data << 8) \| (cpustate->r[n] & 0xff);
	562	}
	563
	564	if(addr == 0x301f)
	565	{
	566	cpustate->sfr \|= SUPERFX_SFR_G;
	567	}
	568	return;
	569	}
	570
	571	switch(addr)
	572	{
	573	case 0x3030:
	574	{
	575	UINT8 g = (cpustate->sfr & SUPERFX_SFR_G) ? 1 : 0;
	576	cpustate->sfr = (cpustate->sfr & 0xff00) \| (data << 0);
	577	if(g == 1 && !(cpustate->sfr & SUPERFX_SFR_G))
	578	{
	579	cpustate->cbr = 0x0000;
	580	superfx_cache_flush(cpustate);
	581	}
	582	break;
	583	}
	584
	585	case 0x3031:
	586	cpustate->sfr = (data << 8) \| (cpustate->sfr & 0x00ff);
	587	break;
	588
	589	case 0x3033:
	590	cpustate->bramr = data;
	591	break;
	592
	593	case 0x3034:
	594	cpustate->pbr = data;
	595	superfx_cache_flush(cpustate);
	596	break;
	597
	598	case 0x3037:
	599	cpustate->cfgr = data;
	600	superfx_update_speed(cpustate);
	601	break;
	602
	603	case 0x3038:
	604	cpustate->scbr = data;
	605	break;
	606
	607	case 0x3039:
	608	cpustate->clsr = data;
	609	superfx_update_speed(cpustate);
	610	break;
	611
	612	case 0x303a:
	613	cpustate->scmr = data;
	614	break;
	615	}
	616	}
	617
	618	static void superfx_add_clocks_internal(superfx_state *cpustate, INT32 clocks)
	619	{
	620	//printf( "superfx_add_clocks: %d\n", clocks);
	621	/*
	622	if(cpustate->romcl)
	623	{
	624	printf( "ROM is accessing\n" );
	625	printf( "romcl = %d, -= MIN(%d, %d) (= %d)\n", cpustate->romcl, clocks, cpustate->romcl, MIN(clocks, cpustate->romcl));
	626	cpustate->romcl -= MIN(clocks, cpustate->romcl);
	627	if(cpustate->romcl == 0)
	628	{
	629	cpustate->sfr &= ~SUPERFX_SFR_R;
	630	printf( "superfx_op_read: reading from rom, calling superfx_bus_read: %08x\n", (cpustate->rombr << 16) + cpustate->r[14] );
	631	cpustate->romdr = superfx_bus_read(cpustate, (cpustate->rombr << 16) + cpustate->r[14]);
	632	}
	633	}
	634	*/
	635
	636	if(cpustate->ramcl)
	637	{
	638	cpustate->ramcl -= MIN(clocks, cpustate->ramcl);
	639	if(cpustate->ramcl == 0)
	640	{
	641	printf( "Writing %02x to %08x\n", cpustate->ramdr, 0x700000 + (cpustate->rambr << 16) + cpustate->ramar );
	642	superfx_bus_write(cpustate, 0x700000 + (cpustate->rambr << 16) + cpustate->ramar, cpustate->ramdr);
	643	}
	644	}
	645	}
	646
	647	static void superfx_timing_reset(superfx_state *cpustate)
	648	{
	649	superfx_update_speed(cpustate);
	650	cpustate->r15_modified = 0;
	651
	652	cpustate->romcl = 0;
	653	cpustate->romdr = 0;
	654
	655	cpustate->ramcl = 0;
	656	cpustate->ramar = 0;
	657	cpustate->ramdr = 0;
	658	}
	659
	660	void superfx_add_clocks(const device_config *cpu, INT32 clocks)
	661	{
	662	superfx_state *cpustate = get_safe_token(cpu);
	663
	664	superfx_add_clocks_internal(cpustate, clocks);
	665	}
	666
	667	/*****************************************************************************/
	668
	669	static CPU_INIT( superfx )
	670	{
	671	int i;
	672	superfx_state *cpustate = get_safe_token(device);
	673
	674	for(i = 0; i < 16; i++)
	675	{
	676	cpustate->r[i] = 0;
	677	}
	678
	679	cpustate->sfr = 0;
	680	cpustate->pbr = 0;
	681	cpustate->rombr = 0;
	682	cpustate->rambr = 0;
	683	cpustate->cbr = 0;
	684	cpustate->scbr = 0;
	685	cpustate->scmr = 0;
	686	cpustate->colr = 0;
	687	cpustate->por = 0;
	688	cpustate->bramr = 0;
	689	cpustate->vcr = 0x04;
	690	cpustate->cfgr = 0;
	691	cpustate->clsr = 0;
	692	cpustate->pipeline = 0x01; // nop
	693	cpustate->ramaddr = 0;
	694	cpustate->r15_modified = 0;
	695
	696	superfx_regs_reset(cpustate);
	697	superfx_memory_reset(cpustate);
	698	superfx_update_speed(cpustate);
	699
	700	cpustate->device = device;
	701	cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
	702	}
	703
	704	static CPU_EXIT( superfx )
	705	{
	706	}
	707
	708	static CPU_RESET( superfx )
	709	{
	710	int i;
	711
	712	superfx_state *cpustate = get_safe_token(device);
	713
	714	for(i = 0; i < 16; i++)
	715	{
	716	cpustate->r[i] = 0;
	717	}
	718
	719	cpustate->sfr = 0;
	720	cpustate->pbr = 0;
	721	cpustate->rombr = 0;
	722	cpustate->rambr = 0;
	723	cpustate->cbr = 0;
	724	cpustate->scbr = 0;
	725	cpustate->scmr = 0;
	726	cpustate->colr = 0;
	727	cpustate->por = 0;
	728	cpustate->bramr = 0;
	729	cpustate->vcr = 0x04;
	730	cpustate->cfgr = 0;
	731	cpustate->clsr = 0;
	732	cpustate->pipeline = 0x01; // nop
	733	cpustate->ramaddr = 0;
	734
	735	superfx_regs_reset(cpustate);
	736	superfx_timing_reset(cpustate);
	737	}
	738
	739	INLINE void superfx_dreg_sfr_sz_update(superfx_state *cpustate)
	740	{
	741	cpustate->sfr &= ~(SUPERFX_SFR_S \| SUPERFX_SFR_Z);
	742	cpustate->sfr \|= (*(cpustate->dreg) & 0x8000) ? SUPERFX_SFR_S : 0;
	743	cpustate->sfr \|= (*(cpustate->dreg) == 0) ? SUPERFX_SFR_Z : 0;
	744	}
	745
	746	static CPU_EXECUTE( superfx )
	747	{
	748	superfx_state *cpustate = get_safe_token(device);
	749	UINT8 op;
	750
	751	cpustate->icount = cycles;
	752
	753	if(!(cpustate->sfr & SUPERFX_SFR_G))
	754	{
	755	superfx_add_clocks_internal(cpustate, 6);
	756	cpustate->icount = MIN(cpustate->icount, 0);
	757	}
	758
	759	while (cpustate->icount > 0 && (cpustate->sfr & SUPERFX_SFR_G))
	760	{
	761	if(!(cpustate->sfr & SUPERFX_SFR_G))
	762	{
	763	superfx_add_clocks_internal(cpustate, 6);
	764	cpustate->icount = MIN(cpustate->icount, 0);
	765	break;
	766	}
	767
	768	debugger_instruction_hook(device, (cpustate->pbr << 16) \| cpustate->r[15]);
	769
	770	op = superfx_peekpipe(cpustate);
	771
	772	printf( "Executing op at %06x: %02x\n", (cpustate->pbr << 16) \| cpustate->r[15], op );
	773	switch(op)
	774	{
	775	case 0x00: // STOP
	776	if(!(cpustate->cfgr & SUPERFX_CFGR_IRQ))
	777	{
	778	cpustate->sfr \|= SUPERFX_SFR_IRQ;
	779	cpustate->irq = 1;
	780	}
	781	cpustate->sfr &= ~SUPERFX_SFR_G;
	782	cpustate->pipeline = 0x01;
	783	superfx_regs_reset(cpustate);
	784	break;
	785	case 0x01: // NOP
	786	superfx_regs_reset(cpustate);
	787	break;
	788	case 0x02: // CACHE
	789	if(cpustate->cbr != (cpustate->r[15] & 0xfff0))
	790	{
	791	cpustate->cbr = cpustate->r[15] & 0xfff0;
	792	superfx_cache_flush(cpustate);
	793	}
	794	superfx_regs_reset(cpustate);
	795	break;
	796	case 0x03: // LSR
	797	cpustate->sfr &= ~SUPERFX_SFR_CY;
	798	cpustate->sfr \|= (*(cpustate->sreg) & 1) ? SUPERFX_SFR_CY : 0;
	799	superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) >> 1);
	800	superfx_dreg_sfr_sz_update(cpustate);
	801	superfx_regs_reset(cpustate);
	802	break;
	803	case 0x04: // ROL
	804	{
	805	UINT16 carry = *(cpustate->sreg) & 0x8000;
	806	superfx_gpr_write(cpustate, cpustate->dreg_idx, (*(cpustate->sreg) << 1) \| (SUPERFX_SFR_CY_SET ? 1 : 0));
	807	cpustate->sfr &= ~SUPERFX_SFR_CY;
	808	cpustate->sfr \|= carry ? SUPERFX_SFR_CY : 0;
	809	superfx_dreg_sfr_sz_update(cpustate);
	810	superfx_regs_reset(cpustate);
	811	break;
	812	}
	813	case 0x05: // BRA
	814	{
	815	INT32 e = (INT8)superfx_pipe(cpustate);
	816	superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	817	break;
	818	}
	819	case 0x06: // BLT
	820	{
	821	INT32 e = (INT8)superfx_pipe(cpustate);
	822	if((SUPERFX_SFR_S_SET ^ SUPERFX_SFR_OV_SET) == 0)
	823	{
	824	superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	825	}
	826	break;
	827	}
	828	case 0x07: // BGE
	829	{
	830	INT32 e = (INT8)superfx_pipe(cpustate);
	831	if((SUPERFX_SFR_S_SET ^ SUPERFX_SFR_OV_SET) == 1)
	832	{
	833	superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	834	}
	835	break;
	836	}
	837	case 0x08: // BNE
	838	{
	839	INT32 e = (INT8)superfx_pipe(cpustate);
	840	if(SUPERFX_SFR_Z_SET == 0)
	841	{
	842	superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	843	}
	844	break;
	845	}
	846	case 0x09: // BEQ
	847	{
	848	INT32 e = (INT8)superfx_pipe(cpustate);
	849	if(SUPERFX_SFR_Z_SET == 1)
	850	{
	851	superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	852	}
	853	break;
	854	}
	855	case 0x0a: // BPL
	856	{
	857	INT32 e = (INT8)superfx_pipe(cpustate);
	858	if(SUPERFX_SFR_S_SET == 0)
	859	{
	860	superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	861	}
	862	break;
	863	}
	864	case 0x0b: // BMI
	865	{
	866	INT32 e = (INT8)superfx_pipe(cpustate);
	867	if(SUPERFX_SFR_S_SET == 1)
	868	{
	869	superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	870	}
	871	break;
	872	}
	873	case 0x0c: // BCC
	874	{
	875	INT32 e = (INT8)superfx_pipe(cpustate);
	876	if(SUPERFX_SFR_CY_SET == 0)
	877	{
	878	superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	879	}
	880	break;
	881	}
	882	case 0x0d: // BCS
	883	{
	884	INT32 e = (INT8)superfx_pipe(cpustate);
	885	if(SUPERFX_SFR_CY_SET == 1)
	886	{
	887	superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	888	}
	889	break;
	890	}
	891	case 0x0e: // BVC
	892	{
	893	INT32 e = (INT8)superfx_pipe(cpustate);
	894	if(SUPERFX_SFR_OV_SET == 0)
	895	{
	896	superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	897	}
	898	break;
	899	}
	900	case 0x0f: // BVS
	901	{
	902	INT32 e = (INT8)superfx_pipe(cpustate);
	903	if(SUPERFX_SFR_OV_SET == 1)
	904	{
	905	superfx_gpr_write(cpustate, 15, cpustate->r[15] + e);
	906	}
	907	break;
	908	}
	909
	910	case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
	911	case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: // TO
	912	if(!(cpustate->sfr & SUPERFX_SFR_B))
	913	{
	914	cpustate->dreg = &cpustate->r[op & 0xf];
	915	cpustate->dreg_idx = op & 0xf;
	916	}
	917	else
	918	{
	919	superfx_gpr_write(cpustate, op & 0xf, *(cpustate->sreg));
	920	superfx_regs_reset(cpustate);
	921	}
	922	break;
	923
	924	case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
	925	case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: // WITH
	926	cpustate->sreg = &cpustate->r[op & 0xf];
	927	cpustate->sreg_idx = op & 0xf;
	928	cpustate->dreg = &cpustate->r[op & 0xf];
	929	cpustate->dreg_idx = op & 0xf;
	930	cpustate->sfr \|= SUPERFX_SFR_B;
	931	break;
	932
	933	case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35:
	934	case 0x36: case 0x37: case 0x38: case 0x39: case 0x3a: case 0x3b: // STW_IR / STB_IR
	935	if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	936	{ // STW_IR
	937	cpustate->ramaddr = cpustate->r[op & 0xf];
	938	superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 0, (*(cpustate->sreg)) >> 0);
	939	superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 1, (*(cpustate->sreg)) >> 8);
	940	superfx_regs_reset(cpustate);
	941	}
	942	else
	943	{ // STB_IR
	944	cpustate->ramaddr = cpustate->r[op & 0xf];
	945	superfx_rambuffer_write(cpustate, cpustate->ramaddr, *(cpustate->sreg));
	946	superfx_regs_reset(cpustate);
	947	}
	948	break;
	949
	950	case 0x3c: // LOOP
	951	superfx_gpr_write(cpustate, 12, cpustate->r[12] - 1);
	952	cpustate->sfr &= ~(SUPERFX_SFR_S \| SUPERFX_SFR_Z);
	953	cpustate->sfr \|= (cpustate->r[12] & 0x8000) ? SUPERFX_SFR_S : 0;
	954	cpustate->sfr \|= (cpustate->r[12] == 0) ? SUPERFX_SFR_Z : 0;
	955	if(!(cpustate->sfr & SUPERFX_SFR_Z))
	956	{
	957	superfx_gpr_write(cpustate, 15, cpustate->r[13]);
	958	}
	959	superfx_regs_reset(cpustate);
	960	break;
	961	case 0x3d: // ALT1
	962	cpustate->sfr &= ~SUPERFX_SFR_B;
	963	cpustate->sfr \|= SUPERFX_SFR_ALT1;
	964	break;
	965	case 0x3e: // ALT2
	966	cpustate->sfr &= ~SUPERFX_SFR_B;
	967	cpustate->sfr \|= SUPERFX_SFR_ALT2;
	968	break;
	969	case 0x3f: // ALT3
	970	cpustate->sfr &= ~SUPERFX_SFR_B;
	971	cpustate->sfr \|= SUPERFX_SFR_ALT1;
	972	cpustate->sfr \|= SUPERFX_SFR_ALT2;
	973	break;
	974
	975	case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45:
	976	case 0x46: case 0x47: case 0x48: case 0x49: case 0x4a: case 0x4b: // LDW_IR / LDB_IR
	977	if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	978	{ // LDW_IR
	979	UINT16 data = 0;
	980	cpustate->ramaddr = cpustate->r[op & 0xf];
	981	data = superfx_rambuffer_read(cpustate, (cpustate->ramaddr ^ 0) << 0);
	982	data \|= superfx_rambuffer_read(cpustate, (cpustate->ramaddr ^ 1) << 8);
	983	superfx_gpr_write(cpustate, cpustate->dreg_idx, data);
	984	superfx_regs_reset(cpustate);
	985	}
	986	else
	987	{ // LDB_IR
	988	cpustate->ramaddr = cpustate->r[op & 0xf];
	989	superfx_gpr_write(cpustate, cpustate->dreg_idx, superfx_rambuffer_read(cpustate, cpustate->ramaddr));
	990	superfx_regs_reset(cpustate);
	991	}
	992	break;
	993
	994	case 0x4c: // PLOT / RPIX
	995	if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	996	{ // PLOT
	997	superfx_plot(cpustate, cpustate->r[1], cpustate->r[2]);
	998	superfx_gpr_write(cpustate, 1, cpustate->r[1] + 1);
	999	superfx_regs_reset(cpustate);
	1000	}
	1001	else
	1002	{ // RPIX
	1003	superfx_gpr_write(cpustate, cpustate->dreg_idx, superfx_rpix(cpustate, cpustate->r[1], cpustate->r[2]));
	1004	superfx_dreg_sfr_sz_update(cpustate);
	1005	superfx_regs_reset(cpustate);
	1006	}
	1007	break;
	1008
	1009	case 0x4d: // SWAP
	1010	superfx_gpr_write(cpustate, cpustate->dreg_idx, ((cpustate->sreg) >> 8) \| ((cpustate->sreg) << 8));
	1011	superfx_dreg_sfr_sz_update(cpustate);
	1012	superfx_regs_reset(cpustate);
	1013	break;
	1014
	1015	case 0x4e: // COLOR / CMODE
	1016	if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	1017	{ // COLOR
	1018	cpustate->colr = superfx_color(cpustate, *(cpustate->sreg));
	1019	superfx_regs_reset(cpustate);
	1020	}
	1021	else
	1022	{ // CMODE
	1023	cpustate->por = *(cpustate->sreg);
	1024	superfx_regs_reset(cpustate);
	1025	}
	1026	break;
	1027
	1028	case 0x4f: // NOT
	1029	superfx_gpr_write(cpustate, cpustate->dreg_idx, ~(*(cpustate->sreg)));
	1030	superfx_dreg_sfr_sz_update(cpustate);
	1031	superfx_regs_reset(cpustate);
	1032	break;
	1033
	1034	case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
	1035	case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: // ADD / ADC / ADDI / ADCI
	1036	{
	1037	INT32 r = *(cpustate->sreg);
	1038	cpustate->sfr &= ~(SUPERFX_SFR_OV \| SUPERFX_SFR_S \| SUPERFX_SFR_CY \| SUPERFX_SFR_Z);
	1039	switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1040	{
	1041	case SUPERFX_SFR_ALT0: // ADD
	1042	r += cpustate->r[op & 0xf];
	1043	cpustate->sfr \|= (~(*(cpustate->sreg) ^ cpustate->r[op & 0xf]) & (cpustate->r[op & 0xf] ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1044	break;
	1045	case SUPERFX_SFR_ALT1: // ADC
	1046	r += cpustate->r[op & 0xf] + ((cpustate->sfr & SUPERFX_SFR_CY) ? 1 : 0);
	1047	cpustate->sfr \|= (~(*(cpustate->sreg) ^ cpustate->r[op & 0xf]) & (cpustate->r[op & 0xf] ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1048	break;
	1049	case SUPERFX_SFR_ALT2: // ADDI
	1050	r += op & 0xf;
	1051	cpustate->sfr \|= (~(*(cpustate->sreg) ^ (op & 0xf)) & ((op & 0xf) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1052	break;
	1053	case SUPERFX_SFR_ALT3: // ADCI
	1054	r += (op & 0xf) + ((cpustate->sfr & SUPERFX_SFR_CY) ? 1 : 0);
	1055	cpustate->sfr \|= (~(*(cpustate->sreg) ^ (op & 0xf)) & ((op & 0xf) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1056	break;
	1057	}
	1058	cpustate->sfr \|= (r & 0x8000) ? SUPERFX_SFR_S : 0;
	1059	cpustate->sfr \|= (r >= 0x10000) ? SUPERFX_SFR_CY : 0;
	1060	cpustate->sfr \|= ((UINT16)r == 0) ? SUPERFX_SFR_Z : 0;
	1061	superfx_gpr_write(cpustate, cpustate->dreg_idx, r);
	1062	superfx_regs_reset(cpustate);
	1063	break;
	1064	}
	1065
	1066	case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
	1067	case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f: // SUB / SBC / SUBI / CMP
	1068	{
	1069	INT32 r = *(cpustate->sreg);
	1070	cpustate->sfr &= ~(SUPERFX_SFR_OV \| SUPERFX_SFR_S \| SUPERFX_SFR_CY \| SUPERFX_SFR_Z);
	1071	switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1072	{
	1073	case SUPERFX_SFR_ALT0: // SUB
	1074	r -= cpustate->r[op & 0xf];
	1075	cpustate->sfr \|= (((cpustate->sreg) ^ cpustate->r[op & 0xf]) & ((cpustate->sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1076	superfx_gpr_write(cpustate, cpustate->dreg_idx, r);
	1077	break;
	1078	case SUPERFX_SFR_ALT1: // SBC
	1079	r -= cpustate->r[op & 0xf] - ((cpustate->sfr & SUPERFX_SFR_CY) ? 0 : 1);
	1080	cpustate->sfr \|= (((cpustate->sreg) ^ cpustate->r[op & 0xf]) & ((cpustate->sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1081	superfx_gpr_write(cpustate, cpustate->dreg_idx, r);
	1082	break;
	1083	case SUPERFX_SFR_ALT2: // SUBI
	1084	r -= op & 0xf;
	1085	cpustate->sfr \|= (((cpustate->sreg) ^ (op & 0xf)) & ((cpustate->sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1086	superfx_gpr_write(cpustate, cpustate->dreg_idx, r);
	1087	break;
	1088	case SUPERFX_SFR_ALT3: // CMP
	1089	r -= cpustate->r[op & 0xf];
	1090	cpustate->sfr \|= (((cpustate->sreg) ^ cpustate->r[op & 0xf]) & ((cpustate->sreg) ^ r) & 0x8000) ? SUPERFX_SFR_OV : 0;
	1091	break;
	1092	}
	1093	cpustate->sfr \|= (r & 0x8000) ? SUPERFX_SFR_S : 0;
	1094	cpustate->sfr \|= (r >= 0x10000) ? SUPERFX_SFR_CY : 0;
	1095	cpustate->sfr \|= ((UINT16)r == 0) ? SUPERFX_SFR_Z : 0;
	1096	superfx_regs_reset(cpustate);
	1097	break;
	1098	}
	1099
	1100	case 0x70: // MERGE
	1101	superfx_gpr_write(cpustate, cpustate->dreg_idx, (cpustate->r[7] & 0xff00) \| (cpustate->r[8] >> 8));
	1102	cpustate->sfr &= ~(SUPERFX_SFR_OV \| SUPERFX_SFR_S \| SUPERFX_SFR_CY \| SUPERFX_SFR_Z);
	1103	cpustate->sfr \|= (*(cpustate->dreg) & 0xc0c0) ? SUPERFX_SFR_OV : 0;
	1104	cpustate->sfr \|= (*(cpustate->dreg) & 0x8080) ? SUPERFX_SFR_S : 0;
	1105	cpustate->sfr \|= (*(cpustate->dreg) & 0xe0e0) ? SUPERFX_SFR_CY : 0;
	1106	cpustate->sfr \|= (*(cpustate->dreg) & 0xf0f0) ? SUPERFX_SFR_Z : 0;
	1107	superfx_regs_reset(cpustate);
	1108	break;
	1109
	1110	case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
	1111	case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: // AND / BIC / ANDI / BICI
	1112	switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1113	{
	1114	case SUPERFX_SFR_ALT0: // AND
	1115	superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) & cpustate->r[op & 0xf]);
	1116	break;
	1117	case SUPERFX_SFR_ALT1: // BIC
	1118	superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) & ~cpustate->r[op & 0xf]);
	1119	break;
	1120	case SUPERFX_SFR_ALT2: // ANDI
	1121	superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) & (op & 0xf));
	1122	break;
	1123	case SUPERFX_SFR_ALT3: // BICI
	1124	superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) & ~(op & 0xf));
	1125	break;
	1126	}
	1127	superfx_dreg_sfr_sz_update(cpustate);
	1128	superfx_regs_reset(cpustate);
	1129	break;
	1130
	1131	case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
	1132	case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f: // MULT / UMULT / MULTI / UMULTI
	1133	switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1134	{
	1135	case SUPERFX_SFR_ALT0: // MULT
	1136	superfx_gpr_write(cpustate, cpustate->dreg_idx, (INT8)((cpustate->sreg)) (INT8)(cpustate->r[op & 0xf]));
	1137	break;
	1138	case SUPERFX_SFR_ALT1: // UMULT
	1139	superfx_gpr_write(cpustate, cpustate->dreg_idx, (UINT8)((cpustate->sreg)) (UINT8)(cpustate->r[op & 0xf]));
	1140	break;
	1141	case SUPERFX_SFR_ALT2: // MULTI
	1142	superfx_gpr_write(cpustate, cpustate->dreg_idx, (INT8)((cpustate->sreg)) (INT8)(op & 0xf));
	1143	break;
	1144	case SUPERFX_SFR_ALT3: // UMULTI
	1145	superfx_gpr_write(cpustate, cpustate->dreg_idx, (UINT8)((cpustate->sreg)) (UINT8)(op & 0xf));
	1146	break;
	1147	}
	1148	superfx_dreg_sfr_sz_update(cpustate);
	1149	superfx_regs_reset(cpustate);
	1150	if(!(cpustate->cfgr & SUPERFX_CFGR_MS0))
	1151	{
	1152	superfx_add_clocks_internal(cpustate, 2);
	1153	}
	1154	break;
	1155
	1156	case 0x90: // SBK
	1157	superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 0, *(cpustate->sreg) >> 0);
	1158	superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 1, *(cpustate->sreg) >> 8);
	1159	superfx_regs_reset(cpustate);
	1160	break;
	1161
	1162	case 0x91: case 0x92: case 0x93: case 0x94: // LINK
	1163	superfx_gpr_write(cpustate, 11, cpustate->r[15] + (op & 0xf));
	1164	superfx_regs_reset(cpustate);
	1165	break;
	1166
	1167	case 0x95: // SEX
	1168	superfx_gpr_write(cpustate, cpustate->dreg_idx, (INT8)(*(cpustate->sreg)));
	1169	superfx_dreg_sfr_sz_update(cpustate);
	1170	superfx_regs_reset(cpustate);
	1171	break;
	1172
	1173	case 0x96: // ASR / DIV2
	1174	if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	1175	{ // ASR
	1176	cpustate->sfr &= ~SUPERFX_SFR_CY;
	1177	cpustate->sfr \|= (*(cpustate->sreg) & 1) ? SUPERFX_SFR_CY : 0;
	1178	superfx_gpr_write(cpustate, cpustate->dreg_idx, (INT16)(*(cpustate->sreg) >> 1));
	1179	superfx_dreg_sfr_sz_update(cpustate);
	1180	superfx_regs_reset(cpustate);
	1181	}
	1182	else
	1183	{ // DIV2
	1184	cpustate->sfr &= ~SUPERFX_SFR_CY;
	1185	cpustate->sfr \|= (*(cpustate->sreg) & 1) ? SUPERFX_SFR_CY : 0;
	1186	superfx_gpr_write(cpustate, cpustate->dreg_idx, ((INT16)((cpustate->sreg) >> 1)) + (((cpustate->sreg) + 1) >> 16));
	1187	superfx_dreg_sfr_sz_update(cpustate);
	1188	superfx_regs_reset(cpustate);
	1189	}
	1190	break;
	1191
	1192	case 0x97: // ROR
	1193	{
	1194	UINT16 carry = *(cpustate->sreg) & 1;
	1195	superfx_gpr_write(cpustate, cpustate->dreg_idx, (((cpustate->sfr & SUPERFX_SFR_CY) ? 1 : 0) << 15) \| (*(cpustate->sreg) >> 1));
	1196	cpustate->sfr &= ~SUPERFX_SFR_CY;
	1197	cpustate->sfr \|= carry ? SUPERFX_SFR_CY : 0;
	1198	superfx_dreg_sfr_sz_update(cpustate);
	1199	superfx_regs_reset(cpustate);
	1200	break;
	1201	}
	1202
	1203	case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: // JMP / LJMP
	1204	if((cpustate->sfr & SUPERFX_SFR_ALT1) == 0)
	1205	{ // JMP
	1206	superfx_gpr_write(cpustate, 15, cpustate->r[op & 0xf]);
	1207	superfx_regs_reset(cpustate);
	1208	}
	1209	else
	1210	{ // LJMP
	1211	cpustate->pbr = cpustate->r[op & 0xf];
	1212	superfx_gpr_write(cpustate, 15, *(cpustate->sreg));
	1213	cpustate->cbr = cpustate->r[15] & 0xfff0;
	1214	superfx_cache_flush(cpustate);
	1215	superfx_regs_reset(cpustate);
	1216	}
	1217	break;
	1218
	1219	case 0x9e: // LOB
	1220	superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) & 0xff);
	1221	cpustate->sfr &= ~(SUPERFX_SFR_S \| SUPERFX_SFR_Z);
	1222	cpustate->sfr \|= (*(cpustate->dreg) & 0x80) ? SUPERFX_SFR_S : 0;
	1223	cpustate->sfr \|= (*(cpustate->dreg) == 0) ? SUPERFX_SFR_Z : 0;
	1224	superfx_regs_reset(cpustate);
	1225	break;
	1226
	1227	case 0x9f: // FMULT / LMULT
	1228	{
	1229	UINT32 result = (INT16)((cpustate->sreg)) (INT16)cpustate->r[6];
	1230	if(cpustate->sfr & SUPERFX_SFR_ALT1)
	1231	{ // LMULT
	1232	superfx_gpr_write(cpustate, 4, result);
	1233	}
	1234	superfx_gpr_write(cpustate, cpustate->dreg_idx, result >> 16);
	1235	cpustate->sfr &= ~SUPERFX_SFR_CY;
	1236	cpustate->sfr \|= (result & 0x8000) ? SUPERFX_SFR_CY : 0;
	1237	superfx_dreg_sfr_sz_update(cpustate);
	1238	superfx_regs_reset(cpustate);
	1239	superfx_add_clocks_internal(cpustate, 4 + ((cpustate->cfgr & SUPERFX_CFGR_MS0) ? 4 : 0));
	1240	break;
	1241	}
	1242
	1243	case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
	1244	case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf: // IBT / LMS / SMS / LMS
	1245	switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1246	{
	1247	case SUPERFX_SFR_ALT0: // IBT
	1248	superfx_gpr_write(cpustate, op & 0xf, (INT8)superfx_pipe(cpustate));
	1249	superfx_regs_reset(cpustate);
	1250	break;
	1251	case SUPERFX_SFR_ALT2: // SMS
	1252	cpustate->ramaddr = superfx_pipe(cpustate) << 1;
	1253	superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 0, cpustate->r[op & 0xf] >> 0);
	1254	superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 1, cpustate->r[op & 0xf] >> 8);
	1255	superfx_regs_reset(cpustate);
	1256	break;
	1257	case SUPERFX_SFR_ALT1: // LMS
	1258	case SUPERFX_SFR_ALT3: // LMS
	1259	{
	1260	UINT16 data = 0;
	1261	cpustate->ramaddr = superfx_pipe(cpustate) << 1;
	1262	data = superfx_rambuffer_read(cpustate, cpustate->ramaddr ^ 0) << 0;
	1263	data \|= superfx_rambuffer_read(cpustate, cpustate->ramaddr ^ 1) << 8;
	1264	superfx_gpr_write(cpustate, op & 0xf, data);
	1265	superfx_regs_reset(cpustate);
	1266	break;
	1267	}
	1268	}
	1269	break;
	1270
	1271	case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
	1272	case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf: // FROM
	1273	if(!(cpustate->sfr & SUPERFX_SFR_B))
	1274	{
	1275	cpustate->sreg = &(cpustate->r[op & 0xf]);
	1276	cpustate->sreg_idx = op & 0xf;
	1277	}
	1278	else
	1279	{
	1280	superfx_gpr_write(cpustate, cpustate->dreg_idx, cpustate->r[op & 0xf]);
	1281	cpustate->sfr &= ~SUPERFX_SFR_OV;
	1282	cpustate->sfr \|= (*(cpustate->dreg) & 0x80) ? SUPERFX_SFR_OV : 0;
	1283	superfx_dreg_sfr_sz_update(cpustate);
	1284	superfx_regs_reset(cpustate);
	1285	}
	1286	break;
	1287
	1288	case 0xc0: // HIB
	1289	superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) >> 8);
	1290	superfx_dreg_sfr_sz_update(cpustate);
	1291	superfx_regs_reset(cpustate);
	1292	break;
	1293
	1294	case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc5: case 0xc6: case 0xc7:
	1295	case 0xc8: case 0xc9: case 0xca: case 0xcb: case 0xcc: case 0xcd: case 0xce: case 0xcf: // OR / XOR / ORI / XORI
	1296	switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1297	{
	1298	case SUPERFX_SFR_ALT0: // OR
	1299	superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) \| cpustate->r[op & 0xf]);
	1300	break;
	1301	case SUPERFX_SFR_ALT1: // XOR
	1302	superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) ^ cpustate->r[op & 0xf]);
	1303	break;
	1304	case SUPERFX_SFR_ALT2: // ORI
	1305	superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) \| (op & 0xf));
	1306	break;
	1307	case SUPERFX_SFR_ALT3: // XORI
	1308	superfx_gpr_write(cpustate, cpustate->dreg_idx, *(cpustate->sreg) ^ (op & 0xf));
	1309	break;
	1310	}
	1311	superfx_dreg_sfr_sz_update(cpustate);
	1312	superfx_regs_reset(cpustate);
	1313	break;
	1314
	1315	case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
	1316	case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: case 0xdd: case 0xde: // INC
	1317	superfx_gpr_write(cpustate, op & 0xf, cpustate->r[op & 0xf] + 1);
	1318	cpustate->sfr &= ~(SUPERFX_SFR_S \| SUPERFX_SFR_Z);
	1319	cpustate->sfr \|= (cpustate->r[op & 0xf] & 0x8000) ? SUPERFX_SFR_S : 0;
	1320	cpustate->sfr \|= (cpustate->r[op & 0xf] == 0) ? SUPERFX_SFR_Z : 0;
	1321	superfx_regs_reset(cpustate);
	1322	break;
	1323
	1324	case 0xdf: // GETC / RAMB / ROMB
	1325	switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1326	{
	1327	case SUPERFX_SFR_ALT0: // GETC
	1328	case SUPERFX_SFR_ALT1: // GETC
	1329	cpustate->colr = superfx_color(cpustate, superfx_rombuffer_read(cpustate));
	1330	superfx_regs_reset(cpustate);
	1331	break;
	1332	case SUPERFX_SFR_ALT2: // RAMB
	1333	superfx_rambuffer_sync(cpustate);
	1334	cpustate->rambr = *(cpustate->sreg);
	1335	superfx_regs_reset(cpustate);
	1336	break;
	1337	case SUPERFX_SFR_ALT3: // ROMB
	1338	superfx_rombuffer_sync(cpustate);
	1339	cpustate->rombr = *(cpustate->sreg);
	1340	superfx_regs_reset(cpustate);
	1341	break;
	1342	}
	1343	break;
	1344
	1345	case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe5: case 0xe6: case 0xe7:
	1346	case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xed: case 0xee: // DEC
	1347	superfx_gpr_write(cpustate, op & 0xf, cpustate->r[op & 0xf] - 1);
	1348	cpustate->sfr &= ~(SUPERFX_SFR_S \| SUPERFX_SFR_Z);
	1349	cpustate->sfr \|= (cpustate->r[op & 0xf] & 0x8000) ? SUPERFX_SFR_S : 0;
	1350	cpustate->sfr \|= (cpustate->r[op & 0xf] == 0) ? SUPERFX_SFR_Z : 0;
	1351	superfx_regs_reset(cpustate);
	1352	break;
	1353
	1354	case 0xef: // GETB / GETBH / GETBL / GETBS
	1355	{
	1356	UINT8 byte = superfx_bus_read(cpustate, (cpustate->rombr << 16) + cpustate->r[14]);
	1357	switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1358	{
	1359	case SUPERFX_SFR_ALT0: // GETB
	1360	superfx_gpr_write(cpustate, cpustate->dreg_idx, byte);
	1361	break;
	1362	case SUPERFX_SFR_ALT1: // GETBH
	1363	superfx_gpr_write(cpustate, cpustate->dreg_idx, (byte << 8) \| (*(cpustate->sreg) & 0x00ff));
	1364	break;
	1365	case SUPERFX_SFR_ALT2: // GETBL
	1366	superfx_gpr_write(cpustate, cpustate->dreg_idx, (*(cpustate->sreg) & 0xff00) \| (byte << 0));
	1367	break;
	1368	case SUPERFX_SFR_ALT3: // GETBS
	1369	superfx_gpr_write(cpustate, cpustate->dreg_idx, (INT16)((INT8)byte));
	1370	break;
	1371	}
	1372	superfx_regs_reset(cpustate);
	1373	break;
	1374	}
	1375
	1376	case 0xf0: case 0xf1: case 0xf2: case 0xf3: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
	1377	case 0xf8: case 0xf9: case 0xfa: case 0xfb: case 0xfc: case 0xfd: case 0xfe: case 0xff: // IWT / LM / SM / LM
	1378	{
	1379	UINT16 data;
	1380	switch(cpustate->sfr & SUPERFX_SFR_ALT)
	1381	{
	1382	case SUPERFX_SFR_ALT0: // IWT
	1383	data = superfx_pipe(cpustate) << 0;
	1384	data \|= superfx_pipe(cpustate) << 8;
	1385	superfx_gpr_write(cpustate, op & 0xf, data);
	1386	superfx_regs_reset(cpustate);
	1387	break;
	1388	case SUPERFX_SFR_ALT2: // SM
	1389	cpustate->ramaddr = superfx_pipe(cpustate) << 0;
	1390	cpustate->ramaddr \|= superfx_pipe(cpustate) << 8;
	1391	superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 0, cpustate->r[op & 0xf] >> 0);
	1392	superfx_rambuffer_write(cpustate, cpustate->ramaddr ^ 1, cpustate->r[op & 0xf] >> 8);
	1393	superfx_regs_reset(cpustate);
	1394	break;
	1395	case SUPERFX_SFR_ALT1:
	1396	case SUPERFX_SFR_ALT3: // LM
	1397	cpustate->ramaddr = superfx_pipe(cpustate) << 0;
	1398	cpustate->ramaddr \|= superfx_pipe(cpustate) << 8;
	1399	data = superfx_rambuffer_read(cpustate, cpustate->ramaddr ^ 0) << 0;
	1400	data \|= superfx_rambuffer_read(cpustate, cpustate->ramaddr ^ 1) << 8;
	1401	superfx_gpr_write(cpustate, op & 0xf, data);
	1402	superfx_regs_reset(cpustate);
	1403	break;
	1404	}
	1405	break;
	1406	}
	1407	}
	1408
	1409	if(!cpustate->r15_modified)
	1410	{
	1411	cpustate->r[15]++;
	1412	}
	1413
	1414	--cpustate->icount;
	1415	}
	1416
	1417	return cycles - cpustate->icount;
	1418	}
	1419
	1420	/*****************************************************************************/
	1421
	1422	CPU_DISASSEMBLE( superfx )
	1423	{
	1424	superfx_state *cpustate = get_safe_token(device);
	1425
	1426	UINT8 op = (UINT8 )(opram + 0);
	1427	UINT8 param0 = (UINT8 )(opram + 1);
	1428	UINT8 param1 = (UINT8 )(opram + 2);
	1429	UINT16 alt = cpustate->sfr & SUPERFX_SFR_ALT;
	1430
	1431	return superfx_dasm_one(buffer, pc, op, param0, param1, alt);
	1432	}
	1433
	1434	/*****************************************************************************/
	1435
	1436	static CPU_SET_INFO( superfx )
	1437	{
	1438	superfx_state *cpustate = get_safe_token(device);
	1439
	1440	switch (state)
	1441	{
	1442	/* --- the following bits of info are set as 64-bit signed integers --- */
	1443	case CPUINFO_INT_PC:
	1444	case CPUINFO_INT_REGISTER + SUPERFX_PC: cpustate->r[15] = info->i; break;
	1445	case CPUINFO_INT_REGISTER + SUPERFX_DREG: info->i = cpustate->dreg_idx; break;
	1446	case CPUINFO_INT_REGISTER + SUPERFX_SREG: info->i = cpustate->sreg_idx; break;
	1447	case CPUINFO_INT_REGISTER + SUPERFX_R0: cpustate->r[0] = info->i; break;
	1448	case CPUINFO_INT_REGISTER + SUPERFX_R1: cpustate->r[1] = info->i; break;
	1449	case CPUINFO_INT_REGISTER + SUPERFX_R2: cpustate->r[2] = info->i; break;
	1450	case CPUINFO_INT_REGISTER + SUPERFX_R3: cpustate->r[3] = info->i; break;
	1451	case CPUINFO_INT_REGISTER + SUPERFX_R4: cpustate->r[4] = info->i; break;
	1452	case CPUINFO_INT_REGISTER + SUPERFX_R5: cpustate->r[5] = info->i; break;
	1453	case CPUINFO_INT_REGISTER + SUPERFX_R6: cpustate->r[6] = info->i; break;
	1454	case CPUINFO_INT_REGISTER + SUPERFX_R7: cpustate->r[7] = info->i; break;
	1455	case CPUINFO_INT_REGISTER + SUPERFX_R8: cpustate->r[8] = info->i; break;
	1456	case CPUINFO_INT_REGISTER + SUPERFX_R9: cpustate->r[9] = info->i; break;
	1457	case CPUINFO_INT_REGISTER + SUPERFX_R10: cpustate->r[10] = info->i; break;
	1458	case CPUINFO_INT_REGISTER + SUPERFX_R11: cpustate->r[11] = info->i; break;
	1459	case CPUINFO_INT_REGISTER + SUPERFX_R12: cpustate->r[12] = info->i; break;
	1460	case CPUINFO_INT_REGISTER + SUPERFX_R13: cpustate->r[13] = info->i; break;
	1461	case CPUINFO_INT_REGISTER + SUPERFX_R14: cpustate->r[14] = info->i; break;
	1462	case CPUINFO_INT_REGISTER + SUPERFX_R15: cpustate->r[15] = info->i; break;
	1463	case CPUINFO_INT_REGISTER + SUPERFX_SFR: cpustate->sfr = info->i; break;
	1464	case CPUINFO_INT_REGISTER + SUPERFX_PBR: cpustate->pbr = info->i; break;
	1465	case CPUINFO_INT_REGISTER + SUPERFX_ROMBR: cpustate->rombr = info->i; break;
	1466	case CPUINFO_INT_REGISTER + SUPERFX_RAMBR: cpustate->rambr = info->i; break;
	1467	case CPUINFO_INT_REGISTER + SUPERFX_CBR: cpustate->cbr = info->i; break;
	1468	case CPUINFO_INT_REGISTER + SUPERFX_SCBR: cpustate->scbr = info->i; break;
	1469	case CPUINFO_INT_REGISTER + SUPERFX_SCMR: cpustate->scmr = info->i; break;
	1470	case CPUINFO_INT_REGISTER + SUPERFX_COLR: cpustate->colr = info->i; break;
	1471	case CPUINFO_INT_REGISTER + SUPERFX_POR: cpustate->por = info->i; break;
	1472	case CPUINFO_INT_REGISTER + SUPERFX_BRAMR: cpustate->bramr = info->i; break;
	1473	case CPUINFO_INT_REGISTER + SUPERFX_VCR: cpustate->vcr = info->i; break;
	1474	case CPUINFO_INT_REGISTER + SUPERFX_CFGR: cpustate->cfgr = info->i; break;
	1475	case CPUINFO_INT_REGISTER + SUPERFX_CLSR: cpustate->clsr = info->i; break;
	1476	case CPUINFO_INT_REGISTER + SUPERFX_ROMCL: cpustate->romcl = info->i; break;
	1477	case CPUINFO_INT_REGISTER + SUPERFX_ROMDR: cpustate->romdr = info->i; break;
	1478	case CPUINFO_INT_REGISTER + SUPERFX_RAMCL: cpustate->ramcl = info->i; break;
	1479	case CPUINFO_INT_REGISTER + SUPERFX_RAMAR: cpustate->ramar = info->i; break;
	1480	case CPUINFO_INT_REGISTER + SUPERFX_RAMDR: cpustate->ramdr = info->i; break;
	1481	case CPUINFO_INT_REGISTER + SUPERFX_RAMADDR: cpustate->ramaddr = info->i; break;
	1482	}
	1483	}
	1484
	1485	CPU_GET_INFO( superfx )
	1486	{
	1487	superfx_state *cpustate = (device != NULL && device->token != NULL) ? get_safe_token(device) : NULL;
	1488
	1489	switch(state)
	1490	{
	1491	/* --- the following bits of info are returned as 64-bit signed integers --- */
	1492	case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(superfx_state); break;
	1493	case CPUINFO_INT_INPUT_LINES: info->i = 0; break;
	1494	case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
	1495	case DEVINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
	1496	case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
	1497	case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
	1498	case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break;
	1499	case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 3; break;
	1500	case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
	1501	case CPUINFO_INT_MAX_CYCLES: info->i = 1; break;
	1502
	1503	case CPUINFO_INT_DATABUS_WIDTH_PROGRAM: info->i = 8; break;
	1504	case CPUINFO_INT_ADDRBUS_WIDTH_PROGRAM: info->i = 32; break;
	1505	case CPUINFO_INT_ADDRBUS_SHIFT_PROGRAM: info->i = 0; break;
	1506	case CPUINFO_INT_DATABUS_WIDTH_DATA: info->i = 0; break;
	1507	case CPUINFO_INT_ADDRBUS_WIDTH_DATA: info->i = 0; break;
	1508	case CPUINFO_INT_ADDRBUS_SHIFT_DATA: info->i = 0; break;
	1509	case CPUINFO_INT_DATABUS_WIDTH_IO: info->i = 0; break;
	1510	case CPUINFO_INT_ADDRBUS_WIDTH_IO: info->i = 0; break;
	1511	case CPUINFO_INT_ADDRBUS_SHIFT_IO: info->i = 0; break;
	1512
	1513	case CPUINFO_INT_PC: /* intentional fallthrough */
	1514	case CPUINFO_INT_REGISTER + SUPERFX_PC: info->i = ((cpustate->pbr << 16) \| cpustate->r[15]) - 1; break;
	1515	case CPUINFO_INT_REGISTER + SUPERFX_DREG: info->i = cpustate->dreg_idx; break;
	1516	case CPUINFO_INT_REGISTER + SUPERFX_SREG: info->i = cpustate->sreg_idx; break;
	1517	case CPUINFO_INT_REGISTER + SUPERFX_R0: info->i = cpustate->r[0]; break;
	1518	case CPUINFO_INT_REGISTER + SUPERFX_R1: info->i = cpustate->r[1]; break;
	1519	case CPUINFO_INT_REGISTER + SUPERFX_R2: info->i = cpustate->r[2]; break;
	1520	case CPUINFO_INT_REGISTER + SUPERFX_R3: info->i = cpustate->r[3]; break;
	1521	case CPUINFO_INT_REGISTER + SUPERFX_R4: info->i = cpustate->r[4]; break;
	1522	case CPUINFO_INT_REGISTER + SUPERFX_R5: info->i = cpustate->r[5]; break;
	1523	case CPUINFO_INT_REGISTER + SUPERFX_R6: info->i = cpustate->r[6]; break;
	1524	case CPUINFO_INT_REGISTER + SUPERFX_R7: info->i = cpustate->r[7]; break;
	1525	case CPUINFO_INT_REGISTER + SUPERFX_R8: info->i = cpustate->r[8]; break;
	1526	case CPUINFO_INT_REGISTER + SUPERFX_R9: info->i = cpustate->r[9]; break;
	1527	case CPUINFO_INT_REGISTER + SUPERFX_R10: info->i = cpustate->r[10]; break;
	1528	case CPUINFO_INT_REGISTER + SUPERFX_R11: info->i = cpustate->r[11]; break;
	1529	case CPUINFO_INT_REGISTER + SUPERFX_R12: info->i = cpustate->r[12]; break;
	1530	case CPUINFO_INT_REGISTER + SUPERFX_R13: info->i = cpustate->r[13]; break;
	1531	case CPUINFO_INT_REGISTER + SUPERFX_R14: info->i = cpustate->r[14]; break;
	1532	case CPUINFO_INT_REGISTER + SUPERFX_R15: info->i = cpustate->r[15]; break;
	1533	case CPUINFO_INT_REGISTER + SUPERFX_SFR: info->i = cpustate->sfr; break;
	1534	case CPUINFO_INT_REGISTER + SUPERFX_PBR: info->i = cpustate->sfr; break;
	1535	case CPUINFO_INT_REGISTER + SUPERFX_ROMBR: info->i = cpustate->rombr; break;
	1536	case CPUINFO_INT_REGISTER + SUPERFX_RAMBR: info->i = cpustate->rambr; break;
	1537	case CPUINFO_INT_REGISTER + SUPERFX_CBR: info->i = cpustate->cbr; break;
	1538	case CPUINFO_INT_REGISTER + SUPERFX_SCBR: info->i = cpustate->scbr; break;
	1539	case CPUINFO_INT_REGISTER + SUPERFX_SCMR: info->i = cpustate->scmr; break;
	1540	case CPUINFO_INT_REGISTER + SUPERFX_COLR: info->i = cpustate->colr; break;
	1541	case CPUINFO_INT_REGISTER + SUPERFX_POR: info->i = cpustate->por; break;
	1542	case CPUINFO_INT_REGISTER + SUPERFX_BRAMR: info->i = cpustate->bramr; break;
	1543	case CPUINFO_INT_REGISTER + SUPERFX_VCR: info->i = cpustate->vcr; break;
	1544	case CPUINFO_INT_REGISTER + SUPERFX_CFGR: info->i = cpustate->cfgr; break;
	1545	case CPUINFO_INT_REGISTER + SUPERFX_CLSR: info->i = cpustate->clsr; break;
	1546	case CPUINFO_INT_REGISTER + SUPERFX_ROMCL: info->i = cpustate->romcl; break;
	1547	case CPUINFO_INT_REGISTER + SUPERFX_ROMDR: info->i = cpustate->romdr; break;
	1548	case CPUINFO_INT_REGISTER + SUPERFX_RAMCL: info->i = cpustate->ramcl; break;
	1549	case CPUINFO_INT_REGISTER + SUPERFX_RAMAR: info->i = cpustate->ramar; break;
	1550	case CPUINFO_INT_REGISTER + SUPERFX_RAMDR: info->i = cpustate->ramdr; break;
	1551	case CPUINFO_INT_REGISTER + SUPERFX_RAMADDR: info->i = cpustate->ramaddr; break;
	1552
	1553	/* --- the following bits of info are returned as pointers to data or functions --- */
	1554	case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(superfx); break;
	1555	case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(superfx); break;
	1556	case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(superfx); break;
	1557	case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(superfx); break;
	1558	case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(superfx); break;
	1559	case CPUINFO_FCT_BURN: info->burn = NULL; break;
	1560	case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(superfx); break;
	1561	case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
	1562
	1563	/* --- the following bits of info are returned as NULL-terminated strings --- */
	1564	case DEVINFO_STR_NAME: strcpy(info->s, "SuperFX"); break;
	1565	case DEVINFO_STR_FAMILY: strcpy(info->s, "SuperFX"); break;
	1566	case DEVINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
	1567	case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
	1568	case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright Nicola Salmoria and the MAME Team"); break;
	1569
	1570	case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break;
	1571
	1572	case CPUINFO_STR_REGISTER + SUPERFX_PC: sprintf(info->s, "PC: %06X", (cpustate->pbr << 16) \| cpustate->r[15]); break;
	1573	case CPUINFO_STR_REGISTER + SUPERFX_DREG: sprintf(info->s, "DREG: R%d", cpustate->dreg_idx); break;
	1574	case CPUINFO_STR_REGISTER + SUPERFX_SREG: sprintf(info->s, "SREG: R%d", cpustate->sreg_idx); break;
	1575	case CPUINFO_STR_REGISTER + SUPERFX_R0: sprintf(info->s, "R0: %04X", cpustate->r[0]); break;
	1576	case CPUINFO_STR_REGISTER + SUPERFX_R1: sprintf(info->s, "R1: %04X", cpustate->r[1]); break;
	1577	case CPUINFO_STR_REGISTER + SUPERFX_R2: sprintf(info->s, "R2: %04X", cpustate->r[2]); break;
	1578	case CPUINFO_STR_REGISTER + SUPERFX_R3: sprintf(info->s, "R3: %04X", cpustate->r[3]); break;
	1579	case CPUINFO_STR_REGISTER + SUPERFX_R4: sprintf(info->s, "R4: %04X", cpustate->r[4]); break;
	1580	case CPUINFO_STR_REGISTER + SUPERFX_R5: sprintf(info->s, "R5: %04X", cpustate->r[5]); break;
	1581	case CPUINFO_STR_REGISTER + SUPERFX_R6: sprintf(info->s, "R6: %04X", cpustate->r[6]); break;
	1582	case CPUINFO_STR_REGISTER + SUPERFX_R7: sprintf(info->s, "R7: %04X", cpustate->r[7]); break;
	1583	case CPUINFO_STR_REGISTER + SUPERFX_R8: sprintf(info->s, "R8: %04X", cpustate->r[8]); break;
	1584	case CPUINFO_STR_REGISTER + SUPERFX_R9: sprintf(info->s, "R9: %04X", cpustate->r[9]); break;
	1585	case CPUINFO_STR_REGISTER + SUPERFX_R10: sprintf(info->s, "R10: %04X", cpustate->r[10]); break;
	1586	case CPUINFO_STR_REGISTER + SUPERFX_R11: sprintf(info->s, "R11: %04X", cpustate->r[11]); break;
	1587	case CPUINFO_STR_REGISTER + SUPERFX_R12: sprintf(info->s, "R12: %04X", cpustate->r[12]); break;
	1588	case CPUINFO_STR_REGISTER + SUPERFX_R13: sprintf(info->s, "R13: %04X", cpustate->r[13]); break;
	1589	case CPUINFO_STR_REGISTER + SUPERFX_R14: sprintf(info->s, "R14: %04X", cpustate->r[14]); break;
	1590	case CPUINFO_STR_REGISTER + SUPERFX_R15: sprintf(info->s, "R15: %04X", cpustate->r[15]); break;
	1591	case CPUINFO_STR_REGISTER + SUPERFX_SFR: sprintf(info->s, "SFR: %04X", cpustate->sfr); break;
	1592	case CPUINFO_STR_REGISTER + SUPERFX_PBR: sprintf(info->s, "PBR: %02X", cpustate->sfr); break;
	1593	case CPUINFO_STR_REGISTER + SUPERFX_ROMBR: sprintf(info->s, "ROMBR: %02X", cpustate->rombr); break;
	1594	case CPUINFO_STR_REGISTER + SUPERFX_RAMBR: sprintf(info->s, "RAMBR: %02X", cpustate->rambr); break;
	1595	case CPUINFO_STR_REGISTER + SUPERFX_CBR: sprintf(info->s, "CBR: %04X", cpustate->cbr); break;
	1596	case CPUINFO_STR_REGISTER + SUPERFX_SCBR: sprintf(info->s, "SCBR: %02X", cpustate->scbr); break;
	1597	case CPUINFO_STR_REGISTER + SUPERFX_SCMR: sprintf(info->s, "SCMR: %02X", cpustate->scmr); break;
	1598	case CPUINFO_STR_REGISTER + SUPERFX_COLR: sprintf(info->s, "COLR %02X", cpustate->colr); break;
	1599	case CPUINFO_STR_REGISTER + SUPERFX_POR: sprintf(info->s, "POR: %02X", cpustate->por); break;
	1600	case CPUINFO_STR_REGISTER + SUPERFX_BRAMR: sprintf(info->s, "BRAMR: %02X", cpustate->bramr); break;
	1601	case CPUINFO_STR_REGISTER + SUPERFX_VCR: sprintf(info->s, "VCR: %02X", cpustate->vcr); break;
	1602	case CPUINFO_STR_REGISTER + SUPERFX_CFGR: sprintf(info->s, "CFGR: %02X", cpustate->cfgr); break;
	1603	case CPUINFO_STR_REGISTER + SUPERFX_CLSR: sprintf(info->s, "CLSR: %02X", cpustate->clsr); break;
	1604	case CPUINFO_STR_REGISTER + SUPERFX_ROMCL: sprintf(info->s, "ROMCL: %08X", cpustate->romcl); break;
	1605	case CPUINFO_STR_REGISTER + SUPERFX_ROMDR: sprintf(info->s, "ROMDR: %02X", cpustate->romdr); break;
	1606	case CPUINFO_STR_REGISTER + SUPERFX_RAMCL: sprintf(info->s, "RAMCL: %08X", cpustate->ramcl); break;
	1607	case CPUINFO_STR_REGISTER + SUPERFX_RAMAR: sprintf(info->s, "RAMAR: %04X", cpustate->ramar); break;
	1608	case CPUINFO_STR_REGISTER + SUPERFX_RAMDR: sprintf(info->s, "RAMDR: %02X", cpustate->ramdr); break;
	1609	case CPUINFO_STR_REGISTER + SUPERFX_RAMADDR: sprintf(info->s, "RAMADDR: %04X", cpustate->ramaddr); break;
	1610	}
	1611	}

src/emu/cpu/cpu.mak
r5534	r5535
48	48
49	49	DRCOBJ += \
50	50	$(CPUOBJ)/drcbex64.o \
51		$(CPUOBJ)/x86log.o
	51	$(CPUOBJ)/x86log.o $(CPUOBJ)/i386/i386dasm.o
52	52
53	53	DRCDEPS += \
54	54	$(CPUSRC)/x86emit.h
r5534	r5535
59	59
60	60	DRCOBJ += \
61	61	$(CPUOBJ)/drcbex86.o \
62		$(CPUOBJ)/x86log.o
	62	$(CPUOBJ)/x86log.o $(CPUOBJ)/i386/i386dasm.o
63	63
64	64	DRCDEPS += \
65	65	$(CPUSRC)/x86emit.h
r5534	r5535
81	81	ifneq ($(filter ARM,$(CPUS)),)
82	82	OBJDIRS += $(CPUOBJ)/arm
83	83	CPUOBJS += $(CPUOBJ)/arm/arm.o
84		DBGOBJS += $(CPUOBJ)/arm/armdasm.o
	84	DASMOBJS += $(CPUOBJ)/arm/armdasm.o
85	85	endif
86	86
87	87	ifneq ($(filter ARM7,$(CPUS)),)
88	88	OBJDIRS += $(CPUOBJ)/arm7
89	89	CPUOBJS += $(CPUOBJ)/arm7/arm7.o
90		DBGOBJS += $(CPUOBJ)/arm7/arm7dasm.o
	90	DASMOBJS += $(CPUOBJ)/arm7/arm7dasm.o
91	91	endif
92	92
93	93	$(CPUOBJ)/arm/arm.o: $(CPUSRC)/arm/arm.c \
r5534	r5535
107	107	ifneq ($(filter SE3208,$(CPUS)),)
108	108	OBJDIRS += $(CPUOBJ)/se3208
109	109	CPUOBJS += $(CPUOBJ)/se3208/se3208.o
110		DBGOBJS += $(CPUOBJ)/se3208/se3208dis.o
	110	DASMOBJS += $(CPUOBJ)/se3208/se3208dis.o
111	111	endif
112	112
113	113	$(CPUOBJ)/se3208/se3208.o: $(CPUSRC)/se3208/se3208.c \
r5534	r5535
122	122	ifneq ($(filter ALPHA8201,$(CPUS)),)
123	123	OBJDIRS += $(CPUOBJ)/alph8201
124	124	CPUOBJS += $(CPUOBJ)/alph8201/alph8201.o
125		DBGOBJS += $(CPUOBJ)/alph8201/8201dasm.o
	125	DASMOBJS += $(CPUOBJ)/alph8201/8201dasm.o
126	126	endif
127	127
128	128	$(CPUOBJ)/alph8201/alph8201.o: $(CPUSRC)/alph8201/alph8201.c \
r5534	r5535
137	137	ifneq ($(filter ADSP21XX,$(CPUS)),)
138	138	OBJDIRS += $(CPUOBJ)/adsp2100
139	139	CPUOBJS += $(CPUOBJ)/adsp2100/adsp2100.o
140		DBGOBJS += $(CPUOBJ)/adsp2100/2100dasm.o
	140	DASMOBJS += $(CPUOBJ)/adsp2100/2100dasm.o
141	141	endif
142	142
143	143	$(CPUOBJ)/adsp2100/adsp2100.o: $(CPUSRC)/adsp2100/adsp2100.c \
r5534	r5535
153	153	ifneq ($(filter ADSP21062,$(CPUS)),)
154	154	OBJDIRS += $(CPUOBJ)/sharc
155	155	CPUOBJS += $(CPUOBJ)/sharc/sharc.o
156		DBGOBJS += $(CPUOBJ)/sharc/sharcdsm.o
	156	DASMOBJS += $(CPUOBJ)/sharc/sharcdsm.o
157	157	endif
158	158
159	159	$(CPUOBJ)/sharc/sharc.o: $(CPUSRC)/sharc/sharc.c \
r5534	r5535
175	175	ifneq ($(filter APEXC,$(CPUS)),)
176	176	OBJDIRS += $(CPUOBJ)/apexc
177	177	CPUOBJS += $(CPUOBJ)/apexc/apexc.o
178		DBGOBJS += $(CPUOBJ)/apexc/apexcdsm.o
	178	DASMOBJS += $(CPUOBJ)/apexc/apexcdsm.o
179	179	endif
180	180
181	181	$(CPUOBJ)/apexc/apexc.o: $(CPUSRC)/apexc/apexc.c \
r5534	r5535
190	190	ifneq ($(filter DSP32C,$(CPUS)),)
191	191	OBJDIRS += $(CPUOBJ)/dsp32
192	192	CPUOBJS += $(CPUOBJ)/dsp32/dsp32.o
193		DBGOBJS += $(CPUOBJ)/dsp32/dsp32dis.o
	193	DASMOBJS += $(CPUOBJ)/dsp32/dsp32dis.o
194	194	endif
195	195
196	196	$(CPUOBJ)/dsp32/dsp32.o: $(CPUSRC)/dsp32/dsp32.c \
r5534	r5535
205	205	ifneq ($(filter ASAP,$(CPUS)),)
206	206	OBJDIRS += $(CPUOBJ)/asap
207	207	CPUOBJS += $(CPUOBJ)/asap/asap.o
208		DBGOBJS += $(CPUOBJ)/asap/asapdasm.o
	208	DASMOBJS += $(CPUOBJ)/asap/asapdasm.o
209	209	endif
210	210
211	211	$(CPUOBJ)/asap/asap.o: $(CPUSRC)/asap/asap.c \
r5534	r5535
220	220	ifneq ($(filter JAGUAR,$(CPUS)),)
221	221	OBJDIRS += $(CPUOBJ)/jaguar
222	222	CPUOBJS += $(CPUOBJ)/jaguar/jaguar.o
223		DBGOBJS += $(CPUOBJ)/jaguar/jagdasm.o
	223	DASMOBJS += $(CPUOBJ)/jaguar/jagdasm.o
224	224	endif
225	225
226	226	$(CPUOBJ)/jaguar/jaguar.o: $(CPUSRC)/jaguar/jaguar.c \
r5534	r5535
229	229
230	230
231	231	#-------------------------------------------------
232		# Atmel 8-bit AVR
233		#-------------------------------------------------
234
235		ifneq ($(filter AVR8,$(CPUS)),)
236		OBJDIRS += $(CPUOBJ)/avr8
237		CPUOBJS += $(CPUOBJ)/avr8/avr8.o
238		DBGOBJS += $(CPUOBJ)/avr8/avr8dasm.o
239		endif
240
241		$(CPUOBJ)/avr8/avr8.o: $(CPUSRC)/avr8/avr8.c \
242		$(CPUSRC)/avr8/avr8.h
243
244
245
246		#-------------------------------------------------
247	232	# Simutrek Cube Quest bit-sliced CPUs
248	233	#-------------------------------------------------
249	234
250	235	ifneq ($(filter CUBEQCPU,$(CPUS)),)
251	236	OBJDIRS += $(CPUOBJ)/cubeqcpu
252	237	CPUOBJS += $(CPUOBJ)/cubeqcpu/cubeqcpu.o
253		#DBGOBJS += $(CPUOBJ)/cubeqcpu/cubedasm.o
	238	DASMOBJS += $(CPUOBJ)/cubeqcpu/cubedasm.o
254	239	endif
255	240
256	241	$(CPUOBJ)/cubeqcpu/cubeqcpu.o: $(CPUSRC)/cubeqcpu/cubeqcpu.c \
r5534	r5535
265	250	ifneq ($(filter ESRIP,$(CPUS)),)
266	251	OBJDIRS += $(CPUOBJ)/esrip
267	252	CPUOBJS += $(CPUOBJ)/esrip/esrip.o
268		#DBGOBJS += $(CPUOBJ)/esrip/esrip.o
	253	DASMOBJS += $(CPUOBJ)/esrip/esripdsm.o
269	254	endif
270	255
271	256	$(CPUOBJ)/esrip/esrip.o: $(CPUSRC)/esrip/esrip.c \
r5534	r5535
280	265	ifneq ($(filter CDP1802,$(CPUS)),)
281	266	OBJDIRS += $(CPUOBJ)/cdp1802
282	267	CPUOBJS += $(CPUOBJ)/cdp1802/cdp1802.o
283		DBGOBJS += $(CPUOBJ)/cdp1802/1802dasm.o
	268	DASMOBJS += $(CPUOBJ)/cdp1802/1802dasm.o
284	269	endif
285	270
286	271	$(CPUOBJ)/cdp1802/cdp1802.o: $(CPUSRC)/cdp1802/cdp1802.c \
r5534	r5535
295	280	ifneq ($(filter COP400,$(CPUS)),)
296	281	OBJDIRS += $(CPUOBJ)/cop400
297	282	CPUOBJS += $(CPUOBJ)/cop400/cop400.o
298		DBGOBJS += $(CPUOBJ)/cop400/cop410ds.o
299		DBGOBJS += $(CPUOBJ)/cop400/cop420ds.o
300		DBGOBJS += $(CPUOBJ)/cop400/cop440ds.o
	283	DASMOBJS += $(CPUOBJ)/cop400/cop410ds.o
	284	DASMOBJS += $(CPUOBJ)/cop400/cop420ds.o
	285	DASMOBJS += $(CPUOBJ)/cop400/cop440ds.o
301	286	endif
302	287
303	288	$(CPUOBJ)/cop400/cop400.o: $(CPUSRC)/cop400/cop400.c \
r5534	r5535
313	298	ifneq ($(filter CP1610,$(CPUS)),)
314	299	OBJDIRS += $(CPUOBJ)/cp1610
315	300	CPUOBJS += $(CPUOBJ)/cp1610/cp1610.o
316		DBGOBJS += $(CPUOBJ)/cp1610/1610dasm.o
	301	DASMOBJS += $(CPUOBJ)/cp1610/1610dasm.o
317	302	endif
318	303
319	304	$(CPUOBJ)/cp1610/cp1610.o: $(CPUSRC)/cp1610/cp1610.c \
r5534	r5535
328	313	ifneq ($(filter CCPU,$(CPUS)),)
329	314	OBJDIRS += $(CPUOBJ)/ccpu
330	315	CPUOBJS += $(CPUOBJ)/ccpu/ccpu.o
331		DBGOBJS += $(CPUOBJ)/ccpu/ccpudasm.o
	316	DASMOBJS += $(CPUOBJ)/ccpu/ccpudasm.o
332	317	endif
333	318
334	319	$(CPUOBJ)/ccpu/ccpu.o: $(CPUSRC)/ccpu/ccpu.c \
r5534	r5535
343	328	ifneq ($(filter T11,$(CPUS)),)
344	329	OBJDIRS += $(CPUOBJ)/t11
345	330	CPUOBJS += $(CPUOBJ)/t11/t11.o
346		DBGOBJS += $(CPUOBJ)/t11/t11dasm.o
	331	DASMOBJS += $(CPUOBJ)/t11/t11dasm.o
347	332	endif
348	333
349	334	$(CPUOBJ)/t11/t11.o: $(CPUSRC)/t11/t11.c \
r5534	r5535
360	345	ifneq ($(filter F8,$(CPUS)),)
361	346	OBJDIRS += $(CPUOBJ)/f8
362	347	CPUOBJS += $(CPUOBJ)/f8/f8.o
363		DBGOBJS += $(CPUOBJ)/f8/f8dasm.o
	348	DASMOBJS += $(CPUOBJ)/f8/f8dasm.o
364	349	endif
365	350
366	351	$(CPUOBJ)/f8/f8.o: $(CPUSRC)/f8/f8.c \
r5534	r5535
381	366	$(CPUOBJ)/g65816/g65816o2.o \
382	367	$(CPUOBJ)/g65816/g65816o3.o \
383	368	$(CPUOBJ)/g65816/g65816o4.o
384		DBGOBJS += $(CPUOBJ)/g65816/g65816ds.o
	369	DASMOBJS += $(CPUOBJ)/g65816/g65816ds.o
385	370	endif
386	371
387	372	G65816DEPS = \
r5534	r5535
416	401	ifneq ($(filter HD6309,$(CPUS)),)
417	402	OBJDIRS += $(CPUOBJ)/hd6309
418	403	CPUOBJS += $(CPUOBJ)/hd6309/hd6309.o
419		DBGOBJS += $(CPUOBJ)/hd6309/6309dasm.o
	404	DASMOBJS += $(CPUOBJ)/hd6309/6309dasm.o
420	405	endif
421	406
422	407	$(CPUOBJ)/hd6309/hd6309.o: $(CPUSRC)/hd6309/hd6309.c \
r5534	r5535
432	417	ifneq ($(filter H83002,$(CPUS)),)
433	418	OBJDIRS += $(CPUOBJ)/h83002
434	419	CPUOBJS += $(CPUOBJ)/h83002/h8_16.o $(CPUOBJ)/h83002/h8periph.o
435		DBGOBJS += $(CPUOBJ)/h83002/h8disasm.o
	420	DASMOBJS += $(CPUOBJ)/h83002/h8disasm.o
436	421	endif
437	422
438	423	$(CPUOBJ)/h83002/h8_16.o: $(CPUSRC)/h83002/h8_16.c \
r5534	r5535
453	438	ifneq ($(filter H83334,$(CPUS)),)
454	439	OBJDIRS += $(CPUOBJ)/h83002
455	440	CPUOBJS += $(CPUOBJ)/h83002/h8_8.o $(CPUOBJ)/h83002/h8periph.o
456		DBGOBJS += $(CPUOBJ)/h83002/h8disasm.o
	441	DASMOBJS += $(CPUOBJ)/h83002/h8disasm.o
457	442	endif
458	443
459	444	$(CPUOBJ)/h83002/h8_8.o: $(CPUSRC)/h83002/h8_8.c \
r5534	r5535
473	458	ifneq ($(filter SH2,$(CPUS)),)
474	459	OBJDIRS += $(CPUOBJ)/sh2
475	460	CPUOBJS += $(CPUOBJ)/sh2/sh2.o $(CPUOBJ)/sh2/sh2comn.o $(CPUOBJ)/sh2/sh2drc.o $(CPUOBJ)/sh2/sh2fe.o $(DRCOBJ)
476		DBGOBJS += $(CPUOBJ)/sh2/sh2dasm.o
	461	DASMOBJS += $(CPUOBJ)/sh2/sh2dasm.o
477	462	endif
478	463
479	464	$(CPUOBJ)/sh2/sh2.o: $(CPUSRC)/sh2/sh2.c \
r5534	r5535
499	484	ifneq ($(filter SH4,$(CPUS)),)
500	485	OBJDIRS += $(CPUOBJ)/sh4
501	486	CPUOBJS += $(CPUOBJ)/sh4/sh4.o $(CPUOBJ)/sh4/sh4comn.o
502		DBGOBJS += $(CPUOBJ)/sh4/sh4dasm.o
	487	DASMOBJS += $(CPUOBJ)/sh4/sh4dasm.o
503	488	endif
504	489
505	490	$(CPUOBJ)/sh4/sh4.o: $(CPUSRC)/sh4/sh4.c \
r5534	r5535
519	504	ifneq ($(filter H6280,$(CPUS)),)
520	505	OBJDIRS += $(CPUOBJ)/h6280
521	506	CPUOBJS += $(CPUOBJ)/h6280/h6280.o
522		DBGOBJS += $(CPUOBJ)/h6280/6280dasm.o
	507	DASMOBJS += $(CPUOBJ)/h6280/6280dasm.o
523	508	endif
524	509
525	510	$(CPUOBJ)/h6280/h6280.o: $(CPUSRC)/h6280/h6280.c \
r5534	r5535
536	521	ifneq ($(filter E1,$(CPUS)),)
537	522	OBJDIRS += $(CPUOBJ)/e132xs
538	523	CPUOBJS += $(CPUOBJ)/e132xs/e132xs.o
539		DBGOBJS += $(CPUOBJ)/e132xs/32xsdasm.o
	524	DASMOBJS += $(CPUOBJ)/e132xs/32xsdasm.o
540	525	endif
541	526
542	527	$(CPUOBJ)/e132xs/e132xs.o: $(CPUSRC)/e132xs/e132xs.c \
r5534	r5535
552	537	ifneq ($(filter I4004,$(CPUS)),)
553	538	OBJDIRS += $(CPUOBJ)/i4004
554	539	CPUOBJS += $(CPUOBJ)/i4004/i4004.o
555		DBGOBJS += $(CPUOBJ)/i4004/4004dasm.o
	540	DASMOBJS += $(CPUOBJ)/i4004/4004dasm.o
556	541	endif
557	542
558	543	$(CPUOBJ)/i4004/i4004.o: $(CPUSRC)/i4004/i4004.c \
r5534	r5535
567	552	ifneq ($(filter I8085,$(CPUS)),)
568	553	OBJDIRS += $(CPUOBJ)/i8085
569	554	CPUOBJS += $(CPUOBJ)/i8085/i8085.o
570		DBGOBJS += $(CPUOBJ)/i8085/8085dasm.o
	555	DASMOBJS += $(CPUOBJ)/i8085/8085dasm.o
571	556	endif
572	557
573	558	$(CPUOBJ)/i8085/i8085.o: $(CPUSRC)/i8085/i8085.c \
r5534	r5535
583	568	ifneq ($(filter MCS48,$(CPUS)),)
584	569	OBJDIRS += $(CPUOBJ)/mcs48
585	570	CPUOBJS += $(CPUOBJ)/mcs48/mcs48.o
586		DBGOBJS += $(CPUOBJ)/mcs48/mcs48dsm.o
	571	DASMOBJS += $(CPUOBJ)/mcs48/mcs48dsm.o
587	572	endif
588	573
589	574	$(CPUOBJ)/mcs48/mcs48.o: $(CPUSRC)/mcs48/mcs48.c \
r5534	r5535
598	583	ifneq ($(filter MCS51,$(CPUS)),)
599	584	OBJDIRS += $(CPUOBJ)/mcs51
600	585	CPUOBJS += $(CPUOBJ)/mcs51/mcs51.o
601		DBGOBJS += $(CPUOBJ)/mcs51/mcs51dasm.o
	586	DASMOBJS += $(CPUOBJ)/mcs51/mcs51dasm.o
602	587	endif
603	588
604	589	$(CPUOBJ)/mcs51/mcs51.o: $(CPUSRC)/mcs51/mcs51.c \
r5534	r5535
613	598	OBJDIRS += $(CPUOBJ)/i86 $(CPUOBJ)/i386
614	599	CPUOBJS += $(CPUOBJ)/i86/i86.o
615	600	CPUOBJS += $(CPUOBJ)/i86/i286.o
616		DBGOBJS += $(CPUOBJ)/i386/i386dasm.o
	601	DASMOBJS += $(CPUOBJ)/i386/i386dasm.o
617	602	endif
618	603
619	604	ifneq ($(filter I386,$(CPUS)),)
620	605	OBJDIRS += $(CPUOBJ)/i386
621	606	CPUOBJS += $(CPUOBJ)/i386/i386.o
622		DBGOBJS += $(CPUOBJ)/i386/i386dasm.o
	607	DASMOBJS += $(CPUOBJ)/i386/i386dasm.o
623	608	endif
624	609
625	610	I86DEPS = \
r5534	r5535
662	647	ifneq ($(filter I860,$(CPUS)),)
663	648	OBJDIRS += $(CPUOBJ)/i860
664	649	CPUOBJS += $(CPUOBJ)/i860/i860.o
665		DBGOBJS += $(CPUOBJ)/i860/i860dis.o
	650	DASMOBJS += $(CPUOBJ)/i860/i860dis.o
666	651	endif
667	652
668	653	$(CPUOBJ)/i860/i860.o: $(CPUSRC)/i860/i860.c \
r5534	r5535
676	661	ifneq ($(filter I960,$(CPUS)),)
677	662	OBJDIRS += $(CPUOBJ)/i960
678	663	CPUOBJS += $(CPUOBJ)/i960/i960.o
679		DBGOBJS += $(CPUOBJ)/i960/i960dis.o
	664	DASMOBJS += $(CPUOBJ)/i960/i960dis.o
680	665	endif
681	666
682	667	$(CPUOBJ)/i960/i960.o: $(CPUSRC)/i960/i960.c \
r5534	r5535
691	676	ifneq ($(filter KONAMI,$(CPUS)),)
692	677	OBJDIRS += $(CPUOBJ)/konami
693	678	CPUOBJS += $(CPUOBJ)/konami/konami.o
694		DBGOBJS += $(CPUOBJ)/konami/knmidasm.o
	679	DASMOBJS += $(CPUOBJ)/konami/knmidasm.o
695	680	endif
696	681
697	682	$(CPUOBJ)/konami/konami.o: $(CPUSRC)/konami/konami.c \
r5534	r5535
708	693	ifneq ($(filter LH5801,$(CPUS)),)
709	694	OBJDIRS += $(CPUOBJ)/lh5801
710	695	CPUOBJS += $(CPUOBJ)/lh5801/lh5801.o
711		DBGOBJS += $(CPUOBJ)/lh5801/5801dasm.o
	696	DASMOBJS += $(CPUOBJ)/lh5801/5801dasm.o
712	697	endif
713	698
714	699	$(CPUOBJ)/lh5801/lh5801.o: $(CPUSRC)/lh5801/lh5801.c \
r5534	r5535
724	709	ifneq ($(filter SSEM,$(CPUS)),)
725	710	OBJDIRS += $(CPUOBJ)/ssem
726	711	CPUOBJS += $(CPUOBJ)/ssem/ssem.o
727		DBGOBJS += $(CPUOBJ)/ssem/ssemdasm.o
	712	DASMOBJS += $(CPUOBJ)/ssem/ssemdasm.o
728	713	endif
729	714
730	715	$(CPUOBJ)/ssem/ssem.o: $(CPUSRC)/ssem/ssem.c \
r5534	r5535
739	724	ifneq ($(filter MB88XX,$(CPUS)),)
740	725	OBJDIRS += $(CPUOBJ)/mb88xx
741	726	CPUOBJS += $(CPUOBJ)/mb88xx/mb88xx.o
742		DBGOBJS += $(CPUOBJ)/mb88xx/mb88dasm.o
	727	DASMOBJS += $(CPUOBJ)/mb88xx/mb88dasm.o
743	728	endif
744	729
745	730	$(CPUOBJ)/mb88xx/mb88xx.o: $(CPUSRC)/mb88xx/mb88xx.c \
r5534	r5535
754	739	ifneq ($(filter MB86233,$(CPUS)),)
755	740	OBJDIRS += $(CPUOBJ)/mb86233
756	741	CPUOBJS += $(CPUOBJ)/mb86233/mb86233.o
757		DBGOBJS += $(CPUOBJ)/mb86233/mb86233d.o
	742	DASMOBJS += $(CPUOBJ)/mb86233/mb86233d.o
758	743	endif
759	744
760	745	$(CPUOBJ)/mb86233/mb86233.o: $(CPUSRC)/mb86233/mb86233.c \
r5534	r5535
769	754	ifneq ($(filter PIC16C5X,$(CPUS)),)
770	755	OBJDIRS += $(CPUOBJ)/pic16c5x
771	756	CPUOBJS += $(CPUOBJ)/pic16c5x/pic16c5x.o
772		DBGOBJS += $(CPUOBJ)/pic16c5x/16c5xdsm.o
	757	DASMOBJS += $(CPUOBJ)/pic16c5x/16c5xdsm.o
773	758	endif
774	759
775	760	$(CPUOBJ)/pic16c5x/pic16c5x.o: $(CPUSRC)/pic16c5x/pic16c5x.c \
r5534	r5535
788	773	CPUOBJS += $(CPUOBJ)/mips/r3000.o
789	774	CPUOBJS += $(CPUOBJ)/mips/mips3com.o $(CPUOBJ)/mips/mips3fe.o $(CPUOBJ)/mips/mips3drc.o $(DRCOBJ)
790	775	CPUOBJS += $(CPUOBJ)/mips/psx.o
791		DBGOBJS += $(CPUOBJ)/mips/r3kdasm.o
792		DBGOBJS += $(CPUOBJ)/mips/mips3dsm.o
793		DBGOBJS += $(CPUOBJ)/mips/psxdasm.o
	776	DASMOBJS += $(CPUOBJ)/mips/r3kdasm.o
	777	DASMOBJS += $(CPUOBJ)/mips/mips3dsm.o
	778	DASMOBJS += $(CPUOBJ)/mips/psxdasm.o
794	779	endif
795	780
796	781	$(CPUOBJ)/mips/r3000.o: $(CPUSRC)/mips/r3000.c \
r5534	r5535
826	811	$(CPUOBJ)/m37710/m37710o1.o \
827	812	$(CPUOBJ)/m37710/m37710o2.o \
828	813	$(CPUOBJ)/m37710/m37710o3.o
829		DBGOBJS += $(CPUOBJ)/m37710/m7700ds.o
	814	DASMOBJS += $(CPUOBJ)/m37710/m7700ds.o
830	815	endif
831	816
832	817	M37710DEPS = \
r5534	r5535
864	849	CPUOBJS += $(CPUOBJ)/m6502/m6509.o
865	850	CPUOBJS += $(CPUOBJ)/m6502/m65ce02.o
866	851	CPUOBJS += $(CPUOBJ)/m6502/m4510.o
867		DBGOBJS += $(CPUOBJ)/m6502/6502dasm.o
	852	DASMOBJS += $(CPUOBJ)/m6502/6502dasm.o
868	853	endif
869	854
870	855	$(CPUOBJ)/m6502/m6502.o: $(CPUSRC)/m6502/m6502.c \
r5534	r5535
895	880	ifneq ($(filter M6800,$(CPUS)),)
896	881	OBJDIRS += $(CPUOBJ)/m6800
897	882	CPUOBJS += $(CPUOBJ)/m6800/m6800.o
898		DBGOBJS += $(CPUOBJ)/m6800/6800dasm.o
	883	DASMOBJS += $(CPUOBJ)/m6800/6800dasm.o
899	884	endif
900	885
901	886	$(CPUOBJ)/m6800/m6800.o: $(CPUSRC)/m6800/m6800.c \
r5534	r5535
912	897	ifneq ($(filter M6805,$(CPUS)),)
913	898	OBJDIRS += $(CPUOBJ)/m6805
914	899	CPUOBJS += $(CPUOBJ)/m6805/m6805.o
915		DBGOBJS += $(CPUOBJ)/m6805/6805dasm.o
	900	DASMOBJS += $(CPUOBJ)/m6805/6805dasm.o
916	901	endif
917	902
918	903	$(CPUOBJ)/m6805/m6805.o: $(CPUSRC)/m6805/m6805.c \
r5534	r5535
928	913	ifneq ($(filter M6809,$(CPUS)),)
929	914	OBJDIRS += $(CPUOBJ)/m6809
930	915	CPUOBJS += $(CPUOBJ)/m6809/m6809.o
931		DBGOBJS += $(CPUOBJ)/m6809/6809dasm.o
	916	DASMOBJS += $(CPUOBJ)/m6809/6809dasm.o
932	917	endif
933	918
934	919	$(CPUOBJ)/m6809/m6809.o: $(CPUSRC)/m6809/m6809.c \
r5534	r5535
945	930	ifneq ($(filter MC68HC11,$(CPUS)),)
946	931	OBJDIRS += $(CPUOBJ)/mc68hc11
947	932	CPUOBJS += $(CPUOBJ)/mc68hc11/mc68hc11.o
948		DBGOBJS += $(CPUOBJ)/mc68hc11/hc11dasm.o
	933	DASMOBJS += $(CPUOBJ)/mc68hc11/hc11dasm.o
949	934	endif
950	935
951	936	$(CPUOBJ)/mc68hc11/mc68hc11.o: $(CPUSRC)/mc68hc11/mc68hc11.c \
r5534	r5535
960	945	ifneq ($(filter M680X0,$(CPUS)),)
961	946	OBJDIRS += $(CPUOBJ)/m68000
962	947	CPUOBJS += $(CPUOBJ)/m68000/m68kcpu.o $(CPUOBJ)/m68000/m68kops.o
963		DBGOBJS += $(CPUOBJ)/m68000/m68kdasm.o
	948	DASMOBJS += $(CPUOBJ)/m68000/m68kdasm.o
964	949	M68KMAKE = $(BUILDOUT)/m68kmake$(BUILD_EXE)
965	950	endif
966	951
r5534	r5535
1002	987	ifneq ($(filter DSP56156,$(CPUS)),)
1003	988	OBJDIRS += $(CPUOBJ)/dsp56k
1004	989	CPUOBJS += $(CPUOBJ)/dsp56k/dsp56k.o
1005		DBGOBJS += $(CPUOBJ)/dsp56k/dsp56dsm.o
	990	DASMOBJS += $(CPUOBJ)/dsp56k/dsp56dsm.o
1006	991	endif
1007	992
1008	993	$(CPUOBJ)/dsp56k/dsp56k.o: $(CPUSRC)/dsp56k/dsp56k.c \
r5534	r5535
1020	1005	OBJDIRS += $(CPUOBJ)/pdp1
1021	1006	CPUOBJS += $(CPUOBJ)/pdp1/pdp1.o
1022	1007	CPUOBJS += $(CPUOBJ)/pdp1/tx0.o
1023		DBGOBJS += $(CPUOBJ)/pdp1/pdp1dasm.o
1024		DBGOBJS += $(CPUOBJ)/pdp1/tx0dasm.o
	1008	DASMOBJS += $(CPUOBJ)/pdp1/pdp1dasm.o
	1009	DASMOBJS += $(CPUOBJ)/pdp1/tx0dasm.o
1025	1010	endif
1026	1011
1027	1012	$(CPUOBJ)/pdp1/pdp1.o: $(CPUSRC)/pdp1/pdp1.c \
r5534	r5535
1041	1026	ifneq ($(filter POWERPC,$(CPUS)),)
1042	1027	OBJDIRS += $(CPUOBJ)/powerpc
1043	1028	CPUOBJS += $(CPUOBJ)/powerpc/ppccom.o $(CPUOBJ)/powerpc/ppcfe.o $(CPUOBJ)/powerpc/ppcdrc.o $(DRCOBJ)
1044		DBGOBJS += $(CPUOBJ)/powerpc/ppc_dasm.o
	1029	DASMOBJS += $(CPUOBJ)/powerpc/ppc_dasm.o
1045	1030	endif
1046	1031
1047	1032	$(CPUOBJ)/powerpc/ppccom.o: $(CPUSRC)/powerpc/ppc.h \
r5534	r5535
1066	1051	ifneq ($(filter NEC,$(CPUS)),)
1067	1052	OBJDIRS += $(CPUOBJ)/nec
1068	1053	CPUOBJS += $(CPUOBJ)/nec/nec.o
1069		DBGOBJS += $(CPUOBJ)/nec/necdasm.o
	1054	DASMOBJS += $(CPUOBJ)/nec/necdasm.o
1070	1055	endif
1071	1056
1072	1057	ifneq ($(filter V30MZ,$(CPUS)),)
1073	1058	OBJDIRS += $(CPUOBJ)/v30mz $(CPUOBJ)/nec
1074	1059	CPUOBJS += $(CPUOBJ)/v30mz/v30mz.o
1075		DBGOBJS += $(CPUOBJ)/nec/necdasm.o
	1060	DASMOBJS += $(CPUOBJ)/nec/necdasm.o
1076	1061	endif
1077	1062
1078	1063	$(CPUOBJ)/nec/nec.o: $(CPUSRC)/nec/nec.c \
r5534	r5535
1100	1085	ifneq ($(filter V60,$(CPUS)),)
1101	1086	OBJDIRS += $(CPUOBJ)/v60
1102	1087	CPUOBJS += $(CPUOBJ)/v60/v60.o
1103		DBGOBJS += $(CPUOBJ)/v60/v60d.o
	1088	DASMOBJS += $(CPUOBJ)/v60/v60d.o
1104	1089	endif
1105	1090
1106	1091	$(CPUOBJ)/v60/v60.o: $(CPUSRC)/v60/am.c \
r5534	r5535
1128	1113	ifneq ($(filter V810,$(CPUS)),)
1129	1114	OBJDIRS += $(CPUOBJ)/v810
1130	1115	CPUOBJS += $(CPUOBJ)/v810/v810.o
1131		DBGOBJS += $(CPUOBJ)/v810/v810dasm.o
	1116	DASMOBJS += $(CPUOBJ)/v810/v810dasm.o
1132	1117	endif
1133	1118
1134	1119	$(CPUOBJ)/v810/v810.o: $(CPUSRC)/v810/v810.c \
r5534	r5535
1143	1128	ifneq ($(filter UPD7810,$(CPUS)),)
1144	1129	OBJDIRS += $(CPUOBJ)/upd7810
1145	1130	CPUOBJS += $(CPUOBJ)/upd7810/upd7810.o
1146		DBGOBJS += $(CPUOBJ)/upd7810/7810dasm.o
	1131	DASMOBJS += $(CPUOBJ)/upd7810/7810dasm.o
1147	1132	endif
1148	1133
1149	1134	$(CPUOBJ)/upd7810/upd7810.o: $(CPUSRC)/upd7810/upd7810.c \
r5534	r5535
1160	1145	ifneq ($(filter MINX,$(CPUS)),)
1161	1146	OBJDIRS += $(CPUOBJ)/minx
1162	1147	CPUOBJS += $(CPUOBJ)/minx/minx.o
1163		DBGOBJS += $(CPUOBJ)/minx/minxd.o
	1148	DASMOBJS += $(CPUOBJ)/minx/minxd.o
1164	1149	endif
1165	1150
1166	1151	$(CPUOBJ)/minx/minx.o: $(CPUSRC)/minx/minx.c \
r5534	r5535
1172	1157	$(CPUSRC)/minx/minxfunc.h
1173	1158
1174	1159
1175
1176	1160	#-------------------------------------------------
1177	1161	# Nintendo/SGI RSP (R3000-based + vector processing)
1178	1162	#-------------------------------------------------
r5534	r5535
1180	1164	ifneq ($(filter RSP,$(CPUS)),)
1181	1165	OBJDIRS += $(CPUOBJ)/rsp
1182	1166	CPUOBJS += $(CPUOBJ)/rsp/rsp.o
1183		DBGOBJS += $(CPUOBJ)/rsp/rsp_dasm.o
	1167	DASMOBJS += $(CPUOBJ)/rsp/rsp_dasm.o
1184	1168	endif
1185	1169
1186	1170	$(CPUOBJ)/rsp/rsp.o: $(CPUSRC)/rsp/rsp.c \
r5534	r5535
1195	1179	ifneq ($(filter SATURN,$(CPUS)),)
1196	1180	OBJDIRS += $(CPUOBJ)/saturn
1197	1181	CPUOBJS += $(CPUOBJ)/saturn/saturn.o
1198		DBGOBJS += $(CPUOBJ)/saturn/saturnds.o
	1182	DASMOBJS += $(CPUOBJ)/saturn/saturnds.o
1199	1183	endif
1200	1184
1201	1185	$(CPUOBJ)/saturn/saturn.o: $(CPUSRC)/saturn/saturn.c \
r5534	r5535
1212	1196	ifneq ($(filter S2650,$(CPUS)),)
1213	1197	OBJDIRS += $(CPUOBJ)/s2650
1214	1198	CPUOBJS += $(CPUOBJ)/s2650/s2650.o
1215		DBGOBJS += $(CPUOBJ)/s2650/2650dasm.o
	1199	DASMOBJS += $(CPUOBJ)/s2650/2650dasm.o
1216	1200	endif
1217	1201
1218	1202	$(CPUOBJ)/s2650/s2650.o: $(CPUSRC)/s2650/s2650.c \
r5534	r5535
1228	1212	ifneq ($(filter SC61860,$(CPUS)),)
1229	1213	OBJDIRS += $(CPUOBJ)/sc61860
1230	1214	CPUOBJS += $(CPUOBJ)/sc61860/sc61860.o
1231		DBGOBJS += $(CPUOBJ)/sc61860/scdasm.o
	1215	DASMOBJS += $(CPUOBJ)/sc61860/scdasm.o
1232	1216	endif
1233	1217
1234	1218	$(CPUOBJ)/sc61860/sc61860.o: $(CPUSRC)/sc61860/sc61860.h \
r5534	r5535
1245	1229	ifneq ($(filter SM8500,$(CPUS)),)
1246	1230	OBJDIRS += $(CPUOBJ)/sm8500
1247	1231	CPUOBJS += $(CPUOBJ)/sm8500/sm8500.o
1248		DBGOBJS += $(CPUOBJ)/sm8500/sm8500d.o
	1232	DASMOBJS += $(CPUOBJ)/sm8500/sm8500d.o
1249	1233	endif
1250	1234
1251	1235	$(CPUOBJ)/sm8500/sm8500.o: $(CPUSRC)/sm8500/sm8500.c \
r5534	r5535
1262	1246	SPCD = cpu/spc700
1263	1247	OBJDIRS += $(CPUOBJ)/spc700
1264	1248	CPUOBJS += $(CPUOBJ)/spc700/spc700.o
1265		DBGOBJS += $(CPUOBJ)/spc700/spc700ds.o
	1249	DASMOBJS += $(CPUOBJ)/spc700/spc700ds.o
1266	1250	endif
1267	1251
1268	1252	$(CPUOBJ)/spc700/spc700.o: $(CPUSRC)/spc700/spc700.c \
r5534	r5535
1277	1261	ifneq ($(filter SSP1601,$(CPUS)),)
1278	1262	OBJDIRS += $(CPUOBJ)/ssp1601
1279	1263	CPUOBJS += $(CPUOBJ)/ssp1601/ssp1601.o
1280		DBGOBJS += $(CPUOBJ)/ssp1601/ssp1601d.o
	1264	DASMOBJS += $(CPUOBJ)/ssp1601/ssp1601d.o
1281	1265	endif
1282	1266
1283	1267	$(CPUOBJ)/ssp1610/ssp1601.o: $(CPUSRC)/ssp1601/ssp1601.c \
r5534	r5535
1286	1270
1287	1271
1288	1272	#-------------------------------------------------
	1273	# Atmel 8-bit AVR
	1274	#-------------------------------------------------
	1275
	1276	ifneq ($(filter AVR8,$(CPUS)),)
	1277	OBJDIRS += $(CPUOBJ)/avr8
	1278	CPUOBJS += $(CPUOBJ)/avr8/avr8.o
	1279	DASMOBJS += $(CPUOBJ)/avr8/avr8dasm.o
	1280	endif
	1281
	1282	$(CPUOBJ)/avr8/avr8.o: $(CPUSRC)/avr8/avr8.c \
	1283	$(CPUSRC)/avr8/avr8.h
	1284
	1285
	1286
	1287	#-------------------------------------------------
1289	1288	# Texas Instruments TMS0980
1290	1289	#-------------------------------------------------
1291	1290
1292	1291	ifneq ($(filter TMS0980,$(CPUS)),)
1293	1292	OBJDIRS += $(CPUOBJ)/tms0980
1294	1293	CPUOBJS += $(CPUOBJ)/tms0980/tms0980.o
1295		DBGOBJS += $(CPUOBJ)/tms0980/tms0980d.o
	1294	DASMOBJS += $(CPUOBJ)/tms0980/tms0980d.o
1296	1295	endif
1297	1296
1298	1297	$(CPUOBJ)/tms0980/tms0980.o: $(CPUSRC)/tms0980/tms0980.h \
r5534	r5535
1310	1309	ifneq ($(filter TMS7000,$(CPUS)),)
1311	1310	OBJDIRS += $(CPUOBJ)/tms7000
1312	1311	CPUOBJS += $(CPUOBJ)/tms7000/tms7000.o
1313		DBGOBJS += $(CPUOBJ)/tms7000/7000dasm.o
	1312	DASMOBJS += $(CPUOBJ)/tms7000/7000dasm.o
1314	1313	endif
1315	1314
1316	1315	$(CPUOBJ)/tms7000/tms7000.o: $(CPUSRC)/tms7000/tms7000.h \
r5534	r5535
1331	1330	CPUOBJS += $(CPUOBJ)/tms9900/tms9980a.o
1332	1331	CPUOBJS += $(CPUOBJ)/tms9900/tms9995.o
1333	1332	CPUOBJS += $(CPUOBJ)/tms9900/ti990_10.o
1334		DBGOBJS += $(CPUOBJ)/tms9900/9900dasm.o
	1333	DASMOBJS += $(CPUOBJ)/tms9900/9900dasm.o
1335	1334	endif
1336	1335
1337	1336	$(CPUOBJ)/tms9900/tms9900.o: $(CPUSRC)/tms9900/tms9900.c \
r5534	r5535
1363	1362	ifneq ($(filter TMS340X0,$(CPUS)),)
1364	1363	OBJDIRS += $(CPUOBJ)/tms34010
1365	1364	CPUOBJS += $(CPUOBJ)/tms34010/tms34010.o
1366		DBGOBJS += $(CPUOBJ)/tms34010/34010dsm.o
	1365	DASMOBJS += $(CPUOBJ)/tms34010/34010dsm.o
1367	1366	endif
1368	1367
1369	1368	$(CPUOBJ)/tms34010/tms34010.o: $(CPUSRC)/tms34010/tms34010.c \
r5534	r5535
1382	1381	ifneq ($(filter TMS32010,$(CPUS)),)
1383	1382	OBJDIRS += $(CPUOBJ)/tms32010
1384	1383	CPUOBJS += $(CPUOBJ)/tms32010/tms32010.o
1385		DBGOBJS += $(CPUOBJ)/tms32010/32010dsm.o
	1384	DASMOBJS += $(CPUOBJ)/tms32010/32010dsm.o
1386	1385	endif
1387	1386
1388	1387	$(CPUOBJ)/tms32010/tms32010.o: $(CPUSRC)/tms32010/tms32010.c \
r5534	r5535
1397	1396	ifneq ($(filter TMS32025,$(CPUS)),)
1398	1397	OBJDIRS += $(CPUOBJ)/tms32025
1399	1398	CPUOBJS += $(CPUOBJ)/tms32025/tms32025.o
1400		DBGOBJS += $(CPUOBJ)/tms32025/32025dsm.o
	1399	DASMOBJS += $(CPUOBJ)/tms32025/32025dsm.o
1401	1400	endif
1402	1401
1403	1402	$(CPUOBJ)/tms32025/tms32025.o: $(CPUSRC)/tms32025/tms32025.c \
r5534	r5535
1412	1411	ifneq ($(filter TMS32031,$(CPUS)),)
1413	1412	OBJDIRS += $(CPUOBJ)/tms32031
1414	1413	CPUOBJS += $(CPUOBJ)/tms32031/tms32031.o
1415		DBGOBJS += $(CPUOBJ)/tms32031/dis32031.o
	1414	DASMOBJS += $(CPUOBJ)/tms32031/dis32031.o
1416	1415	endif
1417	1416
1418	1417	$(CPUOBJ)/tms32031/tms32031.o: $(CPUSRC)/tms32031/tms32031.c \
r5534	r5535
1428	1427	ifneq ($(filter TMS32051,$(CPUS)),)
1429	1428	OBJDIRS += $(CPUOBJ)/tms32051
1430	1429	CPUOBJS += $(CPUOBJ)/tms32051/tms32051.o
1431		DBGOBJS += $(CPUOBJ)/tms32051/dis32051.o
	1430	DASMOBJS += $(CPUOBJ)/tms32051/dis32051.o
1432	1431	endif
1433	1432
1434	1433	$(CPUOBJ)/tms32051/tms32051.o: $(CPUSRC)/tms32051/tms32051.c \
r5534	r5535
1443	1442	ifneq ($(filter TMS57002,$(CPUS)),)
1444	1443	OBJDIRS += $(CPUOBJ)/tms57002
1445	1444	CPUOBJS += $(CPUOBJ)/tms57002/tms57002.o
	1445	DASMOBJS += $(CPUOBJ)/tms57002/57002dsm.o
1446	1446	TMSMAKE += $(BUILDOUT)/tmsmake$(BUILD_EXE)
1447	1447	endif
1448	1448
r5534	r5535
1450	1450	$(CPUSRC)/tms57002/tms57002.h \
1451	1451	$(CPUOBJ)/tms57002/tms57002.inc
1452	1452
	1453	$(CPUOBJ)/tms57002/57002dsm.o: $(CPUSRC)/tms57002/57002dsm.c \
	1454	$(CPUOBJ)/tms57002/tms57002.inc
	1455
1453	1456	# rule to generate the C file
1454	1457	$(CPUOBJ)/tms57002/tms57002.inc: $(TMSMAKE) $(CPUSRC)/tms57002/tmsinstr.lst
1455	1458	@echo Generating TMS57002 source file...
r5534	r5535
1474	1477	ifneq ($(filter TLCS90,$(CPUS)),)
1475	1478	OBJDIRS += $(CPUOBJ)/tlcs90
1476	1479	CPUOBJS += $(CPUOBJ)/tlcs90/tlcs90.o
1477		#DBGOBJS += $(CPUOBJ)/tlcs90/tlcs90.o
	1480	#DASMOBJS += $(CPUOBJ)/tlcs90/tlcs90.o
1478	1481	endif
1479	1482
1480	1483	$(CPUOBJ)/tlcs90/tlcs90.o: $(CPUSRC)/tlcs90/tlcs90.c \
r5534	r5535
1489	1492	ifneq ($(filter TLCS900,$(CPUS)),)
1490	1493	OBJDIRS += $(CPUOBJ)/tlcs900
1491	1494	CPUOBJS += $(CPUOBJ)/tlcs900/tlcs900.o
1492		DBGOBJS += $(CPUOBJ)/tlcs900/dasm900.o
	1495	DASMOBJS += $(CPUOBJ)/tlcs900/dasm900.o
1493	1496	endif
1494	1497
1495	1498	$(CPUOBJ)/tlcs900/tlcs900.o: $(CPUSRC)/tlcs900/tlcs900.c \
r5534	r5535
1507	1510	ifneq ($(filter Z80,$(CPUS)),)
1508	1511	OBJDIRS += $(CPUOBJ)/z80
1509	1512	CPUOBJS += $(CPUOBJ)/z80/z80.o $(CPUOBJ)/z80/z80daisy.o
1510		DBGOBJS += $(CPUOBJ)/z80/z80dasm.o
	1513	DASMOBJS += $(CPUOBJ)/z80/z80dasm.o
1511	1514	endif
1512	1515
1513	1516	$(CPUOBJ)/z80/z80.o: $(CPUSRC)/z80/z80.c \
r5534	r5535
1522	1525	ifneq ($(filter LR35902,$(CPUS)),)
1523	1526	OBJDIRS += $(CPUOBJ)/lr35902
1524	1527	CPUOBJS += $(CPUOBJ)/lr35902/lr35902.o
1525		DBGOBJS += $(CPUOBJ)/lr35902/lr35902d.o
	1528	DASMOBJS += $(CPUOBJ)/lr35902/lr35902d.o
1526	1529	endif
1527	1530
1528	1531	$(CPUOBJ)/lr35902/lr35902.o: $(CPUSRC)/lr35902/lr35902.c \
r5534	r5535
1539	1542	ifneq ($(filter Z180,$(CPUS)),)
1540	1543	OBJDIRS += $(CPUOBJ)/z180 $(CPUOBJ)/z80
1541	1544	CPUOBJS += $(CPUOBJ)/z180/z180.o $(CPUOBJ)/z80/z80daisy.o
1542		DBGOBJS += $(CPUOBJ)/z180/z180dasm.o
	1545	DASMOBJS += $(CPUOBJ)/z180/z180dasm.o
1543	1546	endif
1544	1547
1545	1548	$(CPUOBJ)/z180/z180.o: $(CPUSRC)/z180/z180.c \
r5534	r5535
1562	1565	ifneq ($(filter Z8000,$(CPUS)),)
1563	1566	OBJDIRS += $(CPUOBJ)/z8000
1564	1567	CPUOBJS += $(CPUOBJ)/z8000/z8000.o
1565		DBGOBJS += $(CPUOBJ)/z8000/8000dasm.o
	1568	DASMOBJS += $(CPUOBJ)/z8000/8000dasm.o
1566	1569	endif
1567	1570
1568	1571	$(CPUOBJ)/z8000/z8000.o: $(CPUSRC)/z8000/z8000.c \
r5534	r5535
1571	1574	$(CPUSRC)/z8000/z8000dab.h \
1572	1575	$(CPUSRC)/z8000/z8000ops.c \
1573	1576	$(CPUSRC)/z8000/z8000tbl.c
	1577
	1578
	1579
	1580	#-------------------------------------------------
	1581	# Argonaut SuperFX
	1582	#-------------------------------------------------
	1583
	1584	ifneq ($(filter SUPERFX,$(CPUS)),)
	1585	OBJDIRS += $(CPUOBJ)/superfx
	1586	CPUOBJS += $(CPUOBJ)/superfx/superfx.o
	1587	DASMOBJS += $(CPUOBJ)/superfx/sfx_dasm.o
	1588	endif
	1589
	1590	$(CPUOBJ)/superfx/superfx.o:$(CPUSRC)/superfx/superfx.c \
	1591	$(CPUSRC)/superfx/superfx.h

src/emu/cpu/m37710/m7700ds.c
r5534	r5535
608	608
609	609	return length \| flags \| DASMFLAG_SUPPORTED;
610	610	}
	611
	612	CPU_DISASSEMBLE( m37710_generic )
	613	{
	614	return m7700_disassemble(buffer, (pc&0xffff), pc>>16, oprom, 0, 0);
	615	}
	616

src/emu/cpu/sharc/sharc.c
r5534	r5535
6	6	#include "sharc.h"
7	7	#include "debugger.h"
8	8
	9	CPU_DISASSEMBLE( sharc );
	10
9	11	enum
10	12	{
11	13	SHARC_PC=1, SHARC_PCSTK, SHARC_MODE1, SHARC_MODE2,
r5534	r5535
170	172	};
171	173
172	174
173		static CPU_DISASSEMBLE( sharc );
174
175	175	static void sharc_dma_exec(SHARC_REGS *cpustate, int channel);
176	176	static void check_interrupts(SHARC_REGS *cpustate);
177	177
r5534	r5535
416	416	}
417	417	}
418	418
419		static CPU_DISASSEMBLE( sharc )
420		{
421		UINT64 op = 0;
422		UINT32 flags = 0;
423
424		op = ((UINT64)oprom[0] << 0) \| ((UINT64)oprom[1] << 8) \|
425		((UINT64)oprom[2] << 16) \| ((UINT64)oprom[3] << 24) \|
426		((UINT64)oprom[4] << 32) \| ((UINT64)oprom[5] << 40);
427
428		flags = sharc_dasm_one(buffer, pc, op);
429		return 1 \| flags \| DASMFLAG_SUPPORTED;
430		}
431
432
433	419	static CPU_INIT( sharc )
434	420	{
435	421	SHARC_REGS *cpustate = get_safe_token(device);

src/emu/cpu/sharc/sharcdsm.c
r5534	r5535
1181	1181	return flags;
1182	1182	}
1183	1183
	1184
	1185	CPU_DISASSEMBLE( sharc )
	1186	{
	1187	UINT64 op = 0;
	1188	UINT32 flags = 0;
	1189
	1190	op = ((UINT64)oprom[0] << 0) \| ((UINT64)oprom[1] << 8) \|
	1191	((UINT64)oprom[2] << 16) \| ((UINT64)oprom[3] << 24) \|
	1192	((UINT64)oprom[4] << 32) \| ((UINT64)oprom[5] << 40);
	1193
	1194	flags = sharc_dasm_one(buffer, pc, op);
	1195	return 1 \| flags \| DASMFLAG_SUPPORTED;
	1196	}
	1197
	1198

src/emu/cpu/tms57002/57002dsm.c
r0	r5535
	1	#include "tms57002.h"
	2	#include "debugger.h"
	3
	4	#ifdef __GNUC__
	5	#define noinline __attribute__((noinline))
	6	#else
	7	#define noinline /* */
	8	#endif
	9
	10	static const char *tms57002_get_memadr(UINT32 opcode, char type)
	11	{
	12	static char buff[2][10];
	13	static int index = 0;
	14	char *buf;
	15
	16	index = 1-index;
	17	buf = buff[index];
	18
	19	if(((opcode & 0x400) && (type == 'c')) \|\| (!(opcode & 0x400) && (type == 'd'))) {
	20	if(opcode & 0x100)
	21	sprintf(buf, "%c(%02x)", type, opcode & 0xff);
	22	else if(opcode & 0x80)
	23	sprintf(buf, "%c*+", type);
	24	else
	25	sprintf(buf, "%c*", type);
	26	} else if(opcode & 0x200)
	27	sprintf(buf, "%c*+", type);
	28	else
	29	sprintf(buf, "%c*", type);
	30	return buf;
	31	}
	32
	33
	34	CPU_DISASSEMBLE(tms57002)
	35	{
	36	UINT32 opcode = opram[0] \| (opram[1] << 8) \| (opram[2] << 16);
	37	UINT8 fa = opcode >> 18;
	38	char *buf = buffer;
	39	if(fa == 0x3f) {
	40	switch((opcode >> 11) & 0x7f) { // category 3
	41
	42	#define DASM3
	43	#include "cpu/tms57002/tms57002.inc"
	44	#undef DASM3
	45
	46	default:
	47	sprintf(buf, "unk c3 %02x", (opcode >> 11) & 0x7f);
	48	break;
	49	}
	50	} else {
	51	switch(fa) { // category 1
	52	case 0x00:
	53	buf[0] = 0;
	54	break;
	55
	56	#define DASM1
	57	#include "cpu/tms57002/tms57002.inc"
	58	#undef DASM1
	59
	60	default:
	61	sprintf(buf, "unk c1 %02x", fa);
	62	break;
	63	}
	64
	65	buf += strlen(buf);
	66	if(buf != buffer) {
	67	strcpy(buf, " ; ");
	68	buf += 3;
	69	}
	70
	71	switch((opcode >> 11) & 0x7f) { // category 2
	72	case 0x00:
	73	if(buf != buffer)
	74	buf[-3] = 0;
	75	else
	76	sprintf(buf, "nop");
	77	break;
	78
	79	#define DASM2
	80	#include "cpu/tms57002/tms57002.inc"
	81	#undef DASM2
	82
	83	default:
	84	sprintf(buf, "unk c2 %02x", (opcode >> 11) & 0x7f);
	85	break;
	86	}
	87	}
	88
	89	return 1;
	90	}

src/emu/cpu/tms57002/tms57002.c
r5534	r5535
1	1	#include "tms57002.h"
2	2	#include "debugger.h"
3	3
	4	CPU_DISASSEMBLE(tms57002);
	5
4	6	#ifdef __GNUC__
5	7	#define noinline __attribute__((noinline))
6	8	#else
r5534	r5535
117	119
118	120	static void tms57002_cache_flush(tms57002_t *s);
119	121
120		static const char *tms57002_get_memadr(UINT32 opcode, char type)
121		{
122		static char buff[2][10];
123		static int index = 0;
124		char *buf;
125
126		index = 1-index;
127		buf = buff[index];
128
129		if(((opcode & 0x400) && (type == 'c')) \|\| (!(opcode & 0x400) && (type == 'd'))) {
130		if(opcode & 0x100)
131		sprintf(buf, "%c(%02x)", type, opcode & 0xff);
132		else if(opcode & 0x80)
133		sprintf(buf, "%c*+", type);
134		else
135		sprintf(buf, "%c*", type);
136		} else if(opcode & 0x200)
137		sprintf(buf, "%c*+", type);
138		else
139		sprintf(buf, "%c*", type);
140		return buf;
141		}
142
143		static CPU_DISASSEMBLE(tms57002)
144		{
145		UINT32 opcode = opram[0] \| (opram[1] << 8) \| (opram[2] << 16);
146		UINT8 fa = opcode >> 18;
147		char *buf = buffer;
148		if(fa == 0x3f) {
149		switch((opcode >> 11) & 0x7f) { // category 3
150
151		#define DASM3
152		#include "cpu/tms57002/tms57002.inc"
153		#undef DASM3
154
155		default:
156		sprintf(buf, "unk c3 %02x", (opcode >> 11) & 0x7f);
157		break;
158		}
159		} else {
160		switch(fa) { // category 1
161		case 0x00:
162		buf[0] = 0;
163		break;
164
165		#define DASM1
166		#include "cpu/tms57002/tms57002.inc"
167		#undef DASM1
168
169		default:
170		sprintf(buf, "unk c1 %02x", fa);
171		break;
172		}
173
174		buf += strlen(buf);
175		if(buf != buffer) {
176		strcpy(buf, " ; ");
177		buf += 3;
178		}
179
180		switch((opcode >> 11) & 0x7f) { // category 2
181		case 0x00:
182		if(buf != buffer)
183		buf[-3] = 0;
184		else
185		sprintf(buf, "nop");
186		break;
187
188		#define DASM2
189		#include "cpu/tms57002/tms57002.inc"
190		#undef DASM2
191
192		default:
193		sprintf(buf, "unk c2 %02x", (opcode >> 11) & 0x7f);
194		break;
195		}
196		}
197
198		return 1;
199		}
200
201	122	WRITE8_DEVICE_HANDLER(tms57002_pload_w)
202	123	{
203	124	tms57002_t *s = get_safe_token(device);

src/emu/cpu/cubeqcpu/cubedasm.c
r0	r5535
	1	/***************************************************************************
	2
	3	cubedasm.c
	4
	5	Implementation of the Cube Quest AM2901-based CPUs
	6
	7	***************************************************************************/
	8
	9	#include "debugger.h"
	10	#include "cubeqcpu.h"
	11	#include "driver.h"
	12
	13
	14	/***************************************************************************
	15	CONSTANTS
	16	***************************************************************************/
	17
	18	/* Am2901 Instruction Fields */
	19	static const char *const ins[] =
	20	{
	21	"ADD ",
	22	"SUBR ",
	23	"SUBS ",
	24	"OR ",
	25	"AND ",
	26	"NOTRS",
	27	"EXOR ",
	28	"EXNOR",
	29	};
	30
	31	static const char *const src[] =
	32	{
	33	"A,Q",
	34	"A,B",
	35	"0,Q",
	36	"0,B",
	37	"0,A",
	38	"D,A",
	39	"D,Q",
	40	"D,0",
	41	};
	42
	43	static const char *const dst[] =
	44	{
	45	"QREG ",
	46	"NOP ",
	47	"RAMA ",
	48	"RAMF ",
	49	"RAMQD",
	50	"RAMD ",
	51	"RAMQU",
	52	"RAMU ",
	53	};
	54
	55
	56	/***************************************************************************
	57	SOUND DISASSEMBLY HOOK
	58	***************************************************************************/
	59
	60	CPU_DISASSEMBLE( cquestsnd )
	61	{
	62	static const char *const jmps[] =
	63	{
	64	"JUMP ",
	65	" ",
	66	"JMSB ",
	67	"JNMSB",
	68	" ",
	69	"JZERO",
	70	"JOVR ",
	71	"JLOOP",
	72	};
	73
	74
	75	static const char *const latches[] =
	76	{
	77	"PLTCH ",
	78	"DAC ",
	79	"ADLATCH",
	80	" ",
	81	};
	82
	83	UINT64 inst = BIG_ENDIANIZE_INT64((UINT64 )oprom);
	84	UINT32 inslow = inst & 0xffffffff;
	85	UINT32 inshig = inst >> 32;
	86
	87	int t = (inshig >> 24) & 0xff;
	88	int b = (inshig >> 20) & 0xf;
	89	int a = (inshig >> 16) & 0xf;
	90	int ci = (inshig >> 15) & 1;
	91	int i5_3 = (inshig >> 12) & 7;
	92	int _ramen = (inshig >> 11) & 1;
	93	int i2_0 = (inshig >> 8) & 7;
	94	int rtnltch = (inshig >> 7) & 1;
	95	int jmp = (inshig >> 4) & 7;
	96	int inca = (inshig >> 3) & 1;
	97	int i8_6 = (inshig >> 0) & 7;
	98	int _ipram = (inslow >> 31) & 1;
	99	int _ipwrt = (inslow >> 30) & 1;
	100	int latch = (inslow >> 28) & 3;
	101	int rtn = (inslow >> 27) & 1;
	102	int _rin = (inslow >> 26) & 1;
	103
	104
	105	sprintf(buffer, "%s %s %s %x,%x,%c %.2x %s %s %.2x %s %s %s %c %c %c",
	106	ins[i5_3],
	107	src[i2_0],
	108	dst[i8_6],
	109	a,
	110	b,
	111	ci ? 'C' : ' ',
	112	_rin,
	113	jmps[jmp],
	114	rtn ? "RET" : " ",
	115	t,
	116	latches[latch],
	117	rtnltch ? "RTLATCH" : " ",
	118	_ramen ? "PROM" : "RAM ",
	119	_ipram ? ' ' : 'R',
	120	_ipwrt ? ' ' : 'W',
	121	inca ? 'I' : ' ');
	122
	123	return 1 \| DASMFLAG_SUPPORTED;
	124	}
	125
	126
	127	/***************************************************************************
	128	ROTATE DISASSEMBLY HOOK
	129	***************************************************************************/
	130
	131	CPU_DISASSEMBLE( cquestrot )
	132	{
	133	static const char *const jmps[] =
	134	{
	135	" ",
	136	"JSEQ ",
	137	"JC ",
	138	"JSYNC ",
	139	"JLDWAIT",
	140	"JMSB ",
	141	"JGEONE ",
	142	"JZERO ",
	143
	144	"JUMP ",
	145	"JNSEQ ",
	146	"JNC ",
	147	"JNSYNC ",
	148	"JNLDWAI",
	149	"JNMSB ",
	150	"JLTONE ",
	151	"JNZERO ",
	152	};
	153
	154	static const char *const youts[] =
	155	{
	156	" ",
	157	" ",
	158	"Y2LDA",
	159	"Y2LDD",
	160	"Y2DAD",
	161	"Y2DIN",
	162	"Y2R ",
	163	"Y2D ",
	164	};
	165
	166	static const char *const spfs[] =
	167	{
	168	" ",
	169	" ",
	170	"OP ",
	171	"RET ",
	172	"SQLTCH",
	173	"SWRT ",
	174	"DIV ",
	175	"MULT ",
	176
	177	"DRED ",
	178	"DWRT ",
	179	"??? ",
	180	"??? ",
	181	"??? ",
	182	"??? ",
	183	"??? ",
	184	"??? "
	185	};
	186
	187	UINT64 inst = BIG_ENDIANIZE_INT64((UINT64 )oprom);
	188	UINT32 inslow = inst & 0xffffffff;
	189	UINT32 inshig = inst >> 32;
	190
	191	int t = (inshig >> 20) & 0xfff;
	192	int jmp = (inshig >> 16) & 0xf;
	193	int spf = (inshig >> 12) & 0xf;
	194	// int rsrc = (inshig >> 11) & 0x1;
	195	int yout = (inshig >> 8) & 0x7;
	196	int sel = (inshig >> 6) & 0x3;
	197	// int dsrc = (inshig >> 4) & 0x3;
	198	int b = (inshig >> 0) & 0xf;
	199	int a = (inslow >> 28) & 0xf;
	200	int i8_6 = (inslow >> 24) & 0x7;
	201	int ci = (inslow >> 23) & 0x1;
	202	int i5_3 = (inslow >> 20) & 0x7;
	203	// int _sex = (inslow >> 19) & 0x1;
	204	int i2_0 = (inslow >> 16) & 0x7;
	205
	206	sprintf(buffer, "%s %s,%s %x,%x,%c %d %s %s %s %.2x",
	207	ins[i5_3],
	208	src[i2_0],
	209	dst[i8_6],
	210	a,
	211	b,
	212	ci ? 'C' : ' ',
	213	sel,
	214	jmps[jmp],
	215	youts[yout],
	216	spfs[spf],
	217	t);
	218
	219	return 1 \| DASMFLAG_SUPPORTED;
	220	}
	221
	222	/***************************************************************************
	223	LINE DRAWER DISASSEMBLY HOOK
	224	***************************************************************************/
	225
	226	CPU_DISASSEMBLE( cquestlin )
	227	{
	228	static const char *const jmps[] =
	229	{
	230	" ",
	231	"JMSB ",
	232	"JSEQ ",
	233	"JGTZ ",
	234	"JC ",
	235	"JZ ",
	236	"?????",
	237	"?????",
	238
	239	"JUMP ",
	240	"JNMSB",
	241	"JNSEQ",
	242	"JLEZ ",
	243	"JNC ",
	244	"JNZ ",
	245	"?????",
	246	"?????",
	247	};
	248
	249	static const char *const latches[] =
	250	{
	251	" ",
	252	"SEQLTCH",
	253	"XLTCH ",
	254	"YLTCH ",
	255	"BGLTCH ",
	256	"FGLTCH ",
	257	"CLTCH ",
	258	"ZLTCH ",
	259	};
	260
	261	static const char *const spfs[] =
	262	{
	263	" ",
	264	"FSTOP ",
	265	"FREG ",
	266	"FSTART",
	267	"PWRT ",
	268	"MULT ",
	269	"LSTOP ",
	270	"BRES ",
	271	};
	272
	273	UINT64 inst = BIG_ENDIANIZE_INT64((UINT64 )oprom);
	274	UINT32 inslow = inst & 0xffffffff;
	275	UINT32 inshig = inst >> 32;
	276
	277	int t = (inshig >> 24) & 0xff;
	278	int jmp = (inshig >> 20) & 0xf;
	279	int latch = (inshig >> 16) & 0x7;
	280	int op = (inshig >> 15) & 0x1;
	281	int spf = (inshig >> 12) & 0x7;
	282	int b = (inshig >> 8) & 0xf;
	283	int a = (inshig >> 4) & 0xf;
	284	int i8_6 = (inshig >> 0) & 0x7;
	285	int ci = (inslow >> 31) & 0x1;
	286	int i5_3 = (inslow >> 28) & 0x7;
	287	int _pbcs = (inslow >> 27) & 0x1;
	288	int i2_0 = (inslow >> 24) & 0x7;
	289
	290	sprintf(buffer, "%s %s,%s %x,%x %c %s %.2x %s %s %s %s",
	291	ins[i5_3],
	292	src[i2_0],
	293	dst[i8_6],
	294	a,
	295	b,
	296	ci ? 'C' : ' ',
	297	jmps[jmp],
	298	t,
	299	latches[latch],
	300	op ? "OP" : " ",
	301	_pbcs ? " " : "PB",
	302	spfs[spf]);
	303
	304	return 1 \| DASMFLAG_SUPPORTED;
	305	}

src/emu/cpu/cubeqcpu/cubeqcpu.c
r5534	r5535
15	15	#include "driver.h"
16	16
17	17
	18	CPU_DISASSEMBLE( cquestsnd );
	19	CPU_DISASSEMBLE( cquestrot );
	20	CPU_DISASSEMBLE( cquestlin );
	21
	22
18	23	/***************************************************************************
19	24	CONSTANTS
20	25	***************************************************************************/
21	26
22	27	/* Am2901 Instruction Fields */
23		static const char *const ins[] =
24		{
25		"ADD ",
26		"SUBR ",
27		"SUBS ",
28		"OR ",
29		"AND ",
30		"NOTRS",
31		"EXOR ",
32		"EXNOR",
33		};
34
35		static const char *const src[] =
36		{
37		"A,Q",
38		"A,B",
39		"0,Q",
40		"0,B",
41		"0,A",
42		"D,A",
43		"D,Q",
44		"D,0",
45		};
46
47		static const char *const dst[] =
48		{
49		"QREG ",
50		"NOP ",
51		"RAMA ",
52		"RAMF ",
53		"RAMQD",
54		"RAMD ",
55		"RAMQU",
56		"RAMU ",
57		};
58
59	28	enum alu_src
60	29	{
61	30	AQ = 0,
r5534	r5535
737	706
738	707
739	708	/***************************************************************************
740		SOUND DISASSEMBLY HOOK
741		***************************************************************************/
742
743		static CPU_DISASSEMBLE( cquestsnd )
744		{
745		static const char *const jmps[] =
746		{
747		"JUMP ",
748		" ",
749		"JMSB ",
750		"JNMSB",
751		" ",
752		"JZERO",
753		"JOVR ",
754		"JLOOP",
755		};
756
757
758		static const char *const latches[] =
759		{
760		"PLTCH ",
761		"DAC ",
762		"ADLATCH",
763		" ",
764		};
765
766		UINT64 inst = BIG_ENDIANIZE_INT64((UINT64 )oprom);
767		UINT32 inslow = inst & 0xffffffff;
768		UINT32 inshig = inst >> 32;
769
770		int t = (inshig >> 24) & 0xff;
771		int b = (inshig >> 20) & 0xf;
772		int a = (inshig >> 16) & 0xf;
773		int ci = (inshig >> 15) & 1;
774		int i5_3 = (inshig >> 12) & 7;
775		int _ramen = (inshig >> 11) & 1;
776		int i2_0 = (inshig >> 8) & 7;
777		int rtnltch = (inshig >> 7) & 1;
778		int jmp = (inshig >> 4) & 7;
779		int inca = (inshig >> 3) & 1;
780		int i8_6 = (inshig >> 0) & 7;
781		int _ipram = (inslow >> 31) & 1;
782		int _ipwrt = (inslow >> 30) & 1;
783		int latch = (inslow >> 28) & 3;
784		int rtn = (inslow >> 27) & 1;
785		int _rin = (inslow >> 26) & 1;
786
787
788		sprintf(buffer, "%s %s %s %x,%x,%c %.2x %s %s %.2x %s %s %s %c %c %c\n",
789		ins[i5_3],
790		src[i2_0],
791		dst[i8_6],
792		a,
793		b,
794		ci ? 'C' : ' ',
795		_rin,
796		jmps[jmp],
797		rtn ? "RET" : " ",
798		t,
799		latches[latch],
800		rtnltch ? "RTLATCH" : " ",
801		_ramen ? "PROM" : "RAM ",
802		_ipram ? ' ' : 'R',
803		_ipwrt ? ' ' : 'W',
804		inca ? 'I' : ' ');
805
806		return 1 \| DASMFLAG_SUPPORTED;
807		}
808
809
810		/***************************************************************************
811	709	ROTATE CORE EXECUTION LOOP
812	710	***************************************************************************/
813	711
r5534	r5535
1192	1090
1193	1091
1194	1092	/***************************************************************************
1195		ROTATE DISASSEMBLY HOOK
1196		***************************************************************************/
1197
1198		static CPU_DISASSEMBLE( cquestrot )
1199		{
1200		static const char *const jmps[] =
1201		{
1202		" ",
1203		"JSEQ ",
1204		"JC ",
1205		"JSYNC ",
1206		"JLDWAIT",
1207		"JMSB ",
1208		"JGEONE ",
1209		"JZERO ",
1210
1211		"JUMP ",
1212		"JNSEQ ",
1213		"JNC ",
1214		"JNSYNC ",
1215		"JNLDWAI",
1216		"JNMSB ",
1217		"JLTONE ",
1218		"JNZERO ",
1219		};
1220
1221		static const char *const youts[] =
1222		{
1223		" ",
1224		" ",
1225		"Y2LDA",
1226		"Y2LDD",
1227		"Y2DAD",
1228		"Y2DIN",
1229		"Y2R ",
1230		"Y2D ",
1231		};
1232
1233		static const char *const spfs[] =
1234		{
1235		" ",
1236		" ",
1237		"OP ",
1238		"RET ",
1239		"SQLTCH",
1240		"SWRT ",
1241		"DIV ",
1242		"MULT ",
1243
1244		"DRED ",
1245		"DWRT ",
1246		"??? ",
1247		"??? ",
1248		"??? ",
1249		"??? ",
1250		"??? ",
1251		"??? "
1252		};
1253
1254		UINT64 inst = BIG_ENDIANIZE_INT64((UINT64 )oprom);
1255		UINT32 inslow = inst & 0xffffffff;
1256		UINT32 inshig = inst >> 32;
1257
1258		int t = (inshig >> 20) & 0xfff;
1259		int jmp = (inshig >> 16) & 0xf;
1260		int spf = (inshig >> 12) & 0xf;
1261		// int rsrc = (inshig >> 11) & 0x1;
1262		int yout = (inshig >> 8) & 0x7;
1263		int sel = (inshig >> 6) & 0x3;
1264		// int dsrc = (inshig >> 4) & 0x3;
1265		int b = (inshig >> 0) & 0xf;
1266		int a = (inslow >> 28) & 0xf;
1267		int i8_6 = (inslow >> 24) & 0x7;
1268		int ci = (inslow >> 23) & 0x1;
1269		int i5_3 = (inslow >> 20) & 0x7;
1270		// int _sex = (inslow >> 19) & 0x1;
1271		int i2_0 = (inslow >> 16) & 0x7;
1272
1273		sprintf(buffer, "%s %s,%s %x,%x,%c %d %s %s %s %.2x\n",
1274		ins[i5_3],
1275		src[i2_0],
1276		dst[i8_6],
1277		a,
1278		b,
1279		ci ? 'C' : ' ',
1280		sel,
1281		jmps[jmp],
1282		youts[yout],
1283		spfs[spf],
1284		t);
1285
1286		return 1 \| DASMFLAG_SUPPORTED;
1287		}
1288
1289		/***************************************************************************
1290	1093	LINE DRAWER CORE EXECUTION LOOP
1291	1094	***************************************************************************/
1292	1095
r5534	r5535
1755	1558	}
1756	1559
1757	1560
1758		/***************************************************************************
1759		LINE DRAWER DISASSEMBLY HOOK
1760		***************************************************************************/
1761
1762		static CPU_DISASSEMBLE( cquestlin )
1763		{
1764		static const char *const jmps[] =
1765		{
1766		" ",
1767		"JMSB ",
1768		"JSEQ ",
1769		"JGTZ ",
1770		"JC ",
1771		"JZ ",
1772		"?????",
1773		"?????",
1774
1775		"JUMP ",
1776		"JNMSB",
1777		"JNSEQ",
1778		"JLEZ ",
1779		"JNC ",
1780		"JNZ ",
1781		"?????",
1782		"?????",
1783		};
1784
1785		static const char *const latches[] =
1786		{
1787		" ",
1788		"SEQLTCH",
1789		"XLTCH ",
1790		"YLTCH ",
1791		"BGLTCH ",
1792		"FGLTCH ",
1793		"CLTCH ",
1794		"ZLTCH ",
1795		};
1796
1797		static const char *const spfs[] =
1798		{
1799		" ",
1800		"FSTOP ",
1801		"FREG ",
1802		"FSTART",
1803		"PWRT ",
1804		"MULT ",
1805		"LSTOP ",
1806		"BRES ",
1807		};
1808
1809		UINT64 inst = BIG_ENDIANIZE_INT64((UINT64 )oprom);
1810		UINT32 inslow = inst & 0xffffffff;
1811		UINT32 inshig = inst >> 32;
1812
1813		int t = (inshig >> 24) & 0xff;
1814		int jmp = (inshig >> 20) & 0xf;
1815		int latch = (inshig >> 16) & 0x7;
1816		int op = (inshig >> 15) & 0x1;
1817		int spf = (inshig >> 12) & 0x7;
1818		int b = (inshig >> 8) & 0xf;
1819		int a = (inshig >> 4) & 0xf;
1820		int i8_6 = (inshig >> 0) & 0x7;
1821		int ci = (inslow >> 31) & 0x1;
1822		int i5_3 = (inslow >> 28) & 0x7;
1823		int _pbcs = (inslow >> 27) & 0x1;
1824		int i2_0 = (inslow >> 24) & 0x7;
1825
1826		sprintf(buffer, "%s %s,%s %x,%x %c %s %.2x %s %s %s %s\n",
1827		ins[i5_3],
1828		src[i2_0],
1829		dst[i8_6],
1830		a,
1831		b,
1832		ci ? 'C' : ' ',
1833		jmps[jmp],
1834		t,
1835		latches[latch],
1836		op ? "OP" : " ",
1837		_pbcs ? " " : "PB",
1838		spfs[spf]);
1839
1840		return 1 \| DASMFLAG_SUPPORTED;
1841		}
1842
1843	1561	/**************************************************************************
1844	1562	* Sound set_info
1845	1563	**************************************************************************/

src/emu/cpu/x86log.c
r5534	r5535
74	74	***************************************************************************/
75	75
76	76	static void reset_log(x86log_context *log);
77		st~~atic~~ int ~~x86log_~~i386_dasm_one~~_ex~~(char buffer, UINT64 eip, const UINT8 oprom, int mode);
	77	extern int i386_dasm_one(char buffer, UINT64 eip, const UINT8 oprom, int mode);
78	78
79	79
80	80
r5534	r5535
237	237	else
238	238	{
239	239	#ifdef PTR64
240		bytes = ~~x86log_~~i386_dasm_one~~_ex~~(buffer, (FPTR)cur, cur, 64) & DASMFLAG_LENGTHMASK;
	240	bytes = i386_dasm_one(buffer, (FPTR)cur, cur, 64) & DASMFLAG_LENGTHMASK;
241	241	#else
242		bytes = ~~x86log_~~i386_dasm_one~~_ex~~(buffer, (FPTR)cur, cur, 32) & DASMFLAG_LENGTHMASK;
	242	bytes = i386_dasm_one(buffer, (FPTR)cur, cur, 32) & DASMFLAG_LENGTHMASK;
243	243	#endif
244	244	}
245	245
r5534	r5535
305	305	log->comment_count = 0;
306	306	log->comment_pool_next = log->comment_pool;
307	307	}
308
309
310
311		/***************************************************************************
312		DISASSEMBLERS
313		***************************************************************************/
314
315		#define i386_dasm_one x86log_i386_dasm_one
316		#define i386_dasm_one_ex x86log_i386_dasm_one_ex
317		#include "cpu/i386/i386dasm.c"

src/emu/cpu/v60/v60.c
r5534	r5535
199	199	#define ADTMR1 reg[64]
200	200	//29-31 reserved
201	201
202		// Register names
203		const char *const v60_reg_names[69] = {
204		"R0", "R1", "R2", "R3",
205		"R4", "R5", "R6", "R7",
206		"R8", "R9", "R10", "R11",
207		"R12", "R13", "R14", "R15",
208		"R16", "R17", "R18", "R19",
209		"R20", "R21", "R22", "R23",
210		"R24", "R25", "R26", "R27",
211		"R28", "AP", "FP", "SP",
212		"PC", "PSW","Unk","Unk",
213		"ISP", "L0SP", "L1SP", "L2SP",
214		"L3SP", "SBR","TR","SYCW",
215		"TKCW", "PIR", "Reserved","Reserved",
216		"Reserved","Reserved","Reserved","PSW2",
217		"ATBR0", "ATLR0", "ATBR1", "ATLR1",
218		"ATBR2", "ATLR2", "ATBR3", "ATLR3",
219		"TRMODE", "ADTR0", "ADTR1","ADTMR0",
220		"ADTMR1","Reserved","Reserved","Reserved"
221		};
222
223	202	// Defines...
224	203	#define NORMALIZEFLAGS(cs) \
225	204	{ \

src/emu/cpu/v60/v60d.c
r5534	r5535
2	2	#include "debugger.h"
3	3	#include "v60.h"
4	4
	5	// Register names
	6	const char *const v60_reg_names[69] = {
	7	"R0", "R1", "R2", "R3",
	8	"R4", "R5", "R6", "R7",
	9	"R8", "R9", "R10", "R11",
	10	"R12", "R13", "R14", "R15",
	11	"R16", "R17", "R18", "R19",
	12	"R20", "R21", "R22", "R23",
	13	"R24", "R25", "R26", "R27",
	14	"R28", "AP", "FP", "SP",
	15	"PC", "PSW","Unk","Unk",
	16	"ISP", "L0SP", "L1SP", "L2SP",
	17	"L3SP", "SBR","TR","SYCW",
	18	"TKCW", "PIR", "Reserved","Reserved",
	19	"Reserved","Reserved","Reserved","PSW2",
	20	"ATBR0", "ATLR0", "ATBR1", "ATLR1",
	21	"ATBR2", "ATLR2", "ATBR3", "ATLR3",
	22	"TRMODE", "ADTR0", "ADTR1","ADTMR0",
	23	"ADTMR1","Reserved","Reserved","Reserved"
	24	};
	25
5	26	static const UINT8 *rombase;
6	27	static offs_t pcbase;
7	28

src/emu/cpu/ssp1601/ssp1601d.c
r5534	r5535
288	288	}
289	289
290	290	// vim:ts=4
	291
	292	CPU_DISASSEMBLE( ssp1601 )
	293	{
	294	//ssp1601_state_t *ssp1601_state = get_safe_token(device);
	295
	296	return dasm_ssp1601(buffer, pc, oprom);
	297	}
	298
	299

src/emu/cpu/ssp1601/ssp1601.c
r5534	r5535
20	20	#include "debugger.h"
21	21	#include "ssp1601.h"
22	22
	23	CPU_DISASSEMBLE( ssp1601 );
23	24
24	25	/* detect ops with unimplemented/invalid fields.
25	26	* Useful for homebrew or if a new VR revision pops up. */
r5534	r5535
764	765	* MAME interface
765	766	**************************************************************************/
766	767
767		static CPU_DISASSEMBLE( ssp1601 )
768		{
769		//ssp1601_state_t *ssp1601_state = get_safe_token(device);
770
771		return dasm_ssp1601(buffer, pc, oprom);
772		}
773
774
775	768	static CPU_SET_INFO( ssp1601 )
776	769	{
777	770	ssp1601_state_t *ssp1601_state = get_safe_token(device);

src/emu/cpu/e132xs/32xsdasm.c
r5534	r5535
2133	2133
2134	2134	return size \| flags \| DASMFLAG_SUPPORTED;
2135	2135	}
	2136
	2137	CPU_DISASSEMBLE( hyperstone_generic )
	2138	{
	2139	return dasm_hyperstone( buffer, pc, oprom, 0, 0 );
	2140	}

src/emu/cpu/i386/i386dasm.c
r5534	r5535
2055	2055	case GROUP:
2056	2056	handle_modrm( modrm_string );
2057	2057	for( i=0; i < ARRAY_LENGTH(group_op_table); i++ ) {
2058		if( ~~mame_~~stricmp(op->mnemonic, group_op_table[i].mnemonic) == 0 ) {
	2058	if( strcmp(op->mnemonic, group_op_table[i].mnemonic) == 0 ) {
2059	2059	decode_opcode( s, &group_op_table[i].opcode[MODRM_REG1], op1 );
2060	2060	return;
2061	2061	}
r5534	r5535
2137	2137	{
2138	2138	return i386_dasm_one_ex(buffer, eip, oprom, mode);
2139	2139	}
	2140
	2141	CPU_DISASSEMBLE( x86_16 )
	2142	{
	2143	return i386_dasm_one_ex(buffer, pc, oprom, 16);
	2144	}
	2145
	2146	CPU_DISASSEMBLE( x86_32 )
	2147	{
	2148	return i386_dasm_one_ex(buffer, pc, oprom, 32);
	2149	}
	2150
	2151	CPU_DISASSEMBLE( x86_64 )
	2152	{
	2153	return i386_dasm_one_ex(buffer, pc, oprom, 64);
	2154	}

src/emu/cpu/dsp32/dsp32.c
r5534	r5535
30	30	#include "debugger.h"
31	31	#include "dsp32.h"
32	32
	33	CPU_DISASSEMBLE( dsp32c );
33	34
34	35
35	36	/***************************************************************************
r5534	r5535
402	403
403	404
404	405	/***************************************************************************
405		DISASSEMBLY HOOK
406		***************************************************************************/
407
408		static CPU_DISASSEMBLE( dsp32c )
409		{
410		extern unsigned dasm_dsp32(char *, unsigned, UINT32);
411		return dasm_dsp32(buffer, pc, oprom[0] \| (oprom[1] << 8) \| (oprom[2] << 16) \| (oprom[3] << 24));
412		}
413
414
415
416		/***************************************************************************
417	406	PARALLEL INTERFACE WRITES
418	407	***************************************************************************/
419	408

src/emu/cpu/dsp32/dsp32dis.c
r5534	r5535
689	689
690	690	return 4 \| flags \| DASMFLAG_SUPPORTED;
691	691	}
	692
	693
	694	/***************************************************************************
	695	DISASSEMBLY HOOK
	696	***************************************************************************/
	697
	698	CPU_DISASSEMBLE( dsp32c )
	699	{
	700	return dasm_dsp32(buffer, pc, oprom[0] \| (oprom[1] << 8) \| (oprom[2] << 16) \| (oprom[3] << 24));
	701	}

src/emu/cpu/rsp/rsp.c
r5534	r5535
8	8	#include "debugger.h"
9	9	#include "rsp.h"
10	10
	11	CPU_DISASSEMBLE( rsp );
	12
11	13	#define LOG_INSTRUCTION_EXECUTION 0
12	14	#define SAVE_DISASM 0
13	15	#define SAVE_DMEM 0
r5534	r5535
2867	2869
2868	2870	/*****************************************************************************/
2869	2871
2870		static CPU_DISASSEMBLE( rsp )
2871		{
2872		UINT32 op = LITTLE_ENDIANIZE_INT32((UINT32 )opram);
2873		return rsp_dasm_one(buffer, pc, op);
2874		}
2875
2876		/*****************************************************************************/
2877
2878	2872	static CPU_SET_INFO( rsp )
2879	2873	{
2880	2874	rsp_state *cpustate = get_safe_token(device);

src/emu/cpu/rsp/rsp_dasm.c
r5534	r5535
343	343
344	344	return 4 \| flags \| DASMFLAG_SUPPORTED;
345	345	}
	346
	347	/*****************************************************************************/
	348
	349	CPU_DISASSEMBLE( rsp )
	350	{
	351	UINT32 op = LITTLE_ENDIANIZE_INT32((UINT32 )opram);
	352	return rsp_dasm_one(buffer, pc, op);
	353	}

src/emu/cpu/ssem/ssem.c
r5534	r5535
8	8	#include "debugger.h"
9	9	#include "ssem.h"
10	10
	11	CPU_DISASSEMBLE( ssem );
	12
	13
11	14	#define SSEM_DISASM_ON_UNIMPL 0
12	15	#define SSEM_DUMP_MEM_ON_UNIMPL 0
13	16
r5534	r5535
234	237	return cycles - cpustate->icount;
235	238	}
236	239
237		/*****************************************************************************/
238	240
239		static CPU_DISASSEMBLE( ssem )
240		{
241		UINT32 op = ((UINT8 )(opram + 0) << 24) \|
242		((UINT8 )(opram + 1) << 16) \|
243		((UINT8 )(opram + 2) << 8) \|
244		((UINT8 )(opram + 3) << 0);
245		return ssem_dasm_one(buffer, pc, op);
246		}
247
248	241	/*****************************************************************************/
249	242
250	243	static CPU_SET_INFO( ssem )

src/emu/cpu/ssem/ssemdasm.c
r5534	r5535
73	73
74	74	return 4 \| DASMFLAG_SUPPORTED;
75	75	}
	76
	77	/*****************************************************************************/
	78
	79	CPU_DISASSEMBLE( ssem )
	80	{
	81	UINT32 op = ((UINT8 )(opram + 0) << 24) \|
	82	((UINT8 )(opram + 1) << 16) \|
	83	((UINT8 )(opram + 2) << 8) \|
	84	((UINT8 )(opram + 3) << 0);
	85	return ssem_dasm_one(buffer, pc, op);
	86	}

src/emu/cpu/jaguar/jagdasm.c
r5534	r5535
180	180	}
181	181	return size \| flags \| DASMFLAG_SUPPORTED;
182	182	}
	183
	184
	185	CPU_DISASSEMBLE( jaguargpu )
	186	{
	187	return dasmjag(JAGUAR_VARIANT_GPU, buffer, pc, oprom);
	188	}
	189
	190	CPU_DISASSEMBLE( jaguardsp )
	191	{
	192	return dasmjag(JAGUAR_VARIANT_DSP, buffer, pc, oprom);
	193	}
	194
	195
	196

src/emu/cpu/jaguar/jaguar.c
r5534	r5535
10	10	#include "cpuexec.h"
11	11	#include "jaguar.h"
12	12
	13	CPU_DISASSEMBLE( jaguargpu );
	14	CPU_DISASSEMBLE( jaguardsp );
	15
13	16	#define LOG_GPU_IO 0
14	17	#define LOG_DSP_IO 0
15	18
r5534	r5535
557	560
558	561
559	562	/***************************************************************************
560		DISASSEMBLY HOOK
561		***************************************************************************/
562
563		static CPU_DISASSEMBLE( jaguargpu )
564		{
565		extern unsigned dasmjag(int, char , unsigned, const UINT8 );
566		return dasmjag(JAGUAR_VARIANT_GPU, buffer, pc, oprom);
567		}
568
569		static CPU_DISASSEMBLE( jaguardsp )
570		{
571		extern unsigned dasmjag(int, char , unsigned, const UINT8 );
572		return dasmjag(JAGUAR_VARIANT_DSP, buffer, pc, oprom);
573		}
574
575
576
577		/***************************************************************************
578	563	OPCODES
579	564	***************************************************************************/
580	565

src/emu/cpu/i8085/i8085.c
r5534	r5535
1136	1136	case I8085_SID:
1137	1137	{
1138	1138	int sid = devcb_call_read_line(&cpustate->in_sid_func);
1139
	1139
1140	1140	cpustate->ietemp = ((cpustate->IM & IM_SID) != 0);
1141	1141	cpustate->ietemp = (sid != 0);
1142	1142	}

src/emu/cpu/arm/arm.c
r5534	r5535
18	18	#include "arm.h"
19	19	#include "debugger.h"
20	20
	21	CPU_DISASSEMBLE( arm );
	22
21	23	#define READ8(addr) cpu_read8(cpustate,addr)
22	24	#define WRITE8(addr,data) cpu_write8(cpustate,addr,data)
23	25	#define READ32(addr) cpu_read32(cpustate,addr)
r5534	r5535
492	494	arm_check_irq_state(cpustate);
493	495	}
494	496
495		static CPU_DISASSEMBLE( arm )
496		{
497		UINT32 opcode = oprom[0] \| (oprom[1] << 8) \| (oprom[2] << 16) \| (oprom[3] << 24);
498		return 4 \| arm_disasm(buffer, pc, opcode);
499		}
500
501	497	static CPU_INIT( arm )
502	498	{
503	499	ARM_REGS *cpustate = get_safe_token(device);

src/emu/cpu/arm/armdasm.c
r5534	r5535
391	391
392	392	return dasmflags \| DASMFLAG_SUPPORTED;
393	393	}
	394
	395	CPU_DISASSEMBLE( arm )
	396	{
	397	UINT32 opcode = oprom[0] \| (oprom[1] << 8) \| (oprom[2] << 16) \| (oprom[3] << 24);
	398	return 4 \| arm_disasm(buffer, pc, opcode);
	399	}

src/emu/cpu/powerpc/ppc_dasm.c
r5534	r5535
1166	1166	sprintf(buffer, "?");
1167	1167	return 4 \| flags;
1168	1168	}
	1169
	1170	CPU_DISASSEMBLE( powerpc )
	1171	{
	1172	UINT32 op = (UINT32 )oprom;
	1173	op = BIG_ENDIANIZE_INT32(op);
	1174	return ppc_dasm_one(buffer, pc, op);
	1175	}

src/emu/cpu/z8000/8000dasm.c
r5534	r5535
86	86	Z8000_exec *o;
87	87	UINT32 flags = 0;
88	88
	89	/* already initialized? */
	90	if(z8000_exec == NULL)
	91	z8000_init_tables();
	92
89	93	GET_OP(oprom, 0, new_pc - pc);
90	94	new_pc += 2;
91	95	switch (pc)

src/emu/cpu/sh2/sh2dasm.c
r5534	r5535
600	600	}
601	601	return 2 \| flags \| DASMFLAG_SUPPORTED;
602	602	}
	603
	604	CPU_DISASSEMBLE( sh2 )
	605	{
	606	return DasmSH2( buffer, pc, (oprom[0] << 8) \| oprom[1] );
	607	}
	608

src/emu/cpu/sh2/sh2drc.c
r5534	r5535
20	20	#include "sh2comn.h"
21	21	#include "eminline.h"
22	22
	23	CPU_DISASSEMBLE( sh2 );
	24
23	25	#ifdef USE_SH2DRC
24	26
25	27	/***************************************************************************
r5534	r5535
3172	3174
3173	3175
3174	3176	/*-------------------------------------------------
3175		sh2_dasm - disassemble an instruction
3176		-------------------------------------------------*/
3177
3178		static CPU_DISASSEMBLE( sh2 )
3179		{
3180		return DasmSH2( buffer, pc, (oprom[0] << 8) \| oprom[1] );
3181		}
3182
3183		/*-------------------------------------------------
3184	3177	sh2_internal_a5 - read handler for
3185	3178	SH2 internal map
3186	3179	-------------------------------------------------*/

src/emu/cpu/sh2/sh2.c
r5534	r5535
103	103	#include "sh2.h"
104	104	#include "sh2comn.h"
105	105
	106	CPU_DISASSEMBLE( sh2 );
	107
106	108	#ifndef USE_SH2DRC
107	109
108	110	/* speed up delay loops, bail out of tight loops */
r5534	r5535
2239	2241	return cycles - sh2_icount;
2240	2242	}
2241	2243
2242		static CPU_DISASSEMBLE( sh2 )
2243		{
2244		return DasmSH2( buffer, pc, (oprom[0] << 8) \| oprom[1] );
2245		}
2246
2247	2244	static CPU_INIT( sh2 )
2248	2245	{
2249	2246	/* allocate the core memory */

src/emu/cpu/sh4/sh4.c
r5534	r5535
27	27	#include "sh4regs.h"
28	28	#include "sh4comn.h"
29	29
	30	CPU_DISASSEMBLE( sh4 );
	31
30	32	INLINE SH4 get_safe_token(const device_config device)
31	33	{
32	34	assert(device != NULL);
r5534	r5535
3419	3421	return cycles - sh4->sh4_icount;
3420	3422	}
3421	3423
3422		static CPU_DISASSEMBLE( sh4 )
3423		{
3424		return DasmSH4( buffer, pc, (oprom[1] << 8) \| oprom[0] );
3425		}
3426
3427	3424	static CPU_INIT( sh4 )
3428	3425	{
3429	3426	const struct sh4_config conf = (const struct sh4_config )device->static_config;

src/emu/cpu/sh4/sh4dasm.c
r5534	r5535
809	809	}
810	810	return 2 \| flags \| DASMFLAG_SUPPORTED;
811	811	}
	812
	813	CPU_DISASSEMBLE( sh4 )
	814	{
	815	return DasmSH4( buffer, pc, (oprom[1] << 8) \| oprom[0] );
	816	}
	817

src/emu/cpu/g65816/g65816ds.c
r5534	r5535
345	345
346	346	return length \| DASMFLAG_SUPPORTED \| dasm_flags;
347	347	}
	348
	349	CPU_DISASSEMBLE( g65816_generic )
	350	{
	351	return g65816_disassemble(buffer, (pc & 0x00ffff), (pc & 0xff0000) >> 16, oprom, 0, 0);
	352	}

src/emu/cpu/nec/necdasm.c
r5534	r5535
1485	1485	case GROUP:
1486	1486	handle_modrm( modrm_string );
1487	1487	for( i=0; i < ARRAY_LENGTH(group_op_table); i++ ) {
1488		if( ~~mame_~~stricmp(op->mnemonic, group_op_table[i].mnemonic) == 0 )
	1488	if( strcmp(op->mnemonic, group_op_table[i].mnemonic) == 0 )
1489	1489	{
1490	1490	decode_opcode( s, &group_op_table[i].opcode[MODRM_REG1], op1 );
1491	1491	return;
r5534	r5535
1543	1543	decode_opcode( buffer, &necv_opcode_table1[op], op );
1544	1544	return (pc-eip) \| dasm_flags \| DASMFLAG_SUPPORTED;
1545	1545	}
	1546
	1547	CPU_DISASSEMBLE( nec_generic )
	1548	{
	1549	return necv_dasm_one(buffer, pc, oprom, NULL);
	1550	}
	1551

src/emu/cpu/mips/mips3dsm.c
r5534	r5535
509	509	}
510	510	return 4 \| flags \| DASMFLAG_SUPPORTED;
511	511	}
	512
	513
	514	CPU_DISASSEMBLE( mips3be )
	515	{
	516	UINT32 op = (UINT32 )oprom;
	517	op = BIG_ENDIANIZE_INT32(op);
	518	return dasmmips3(buffer, pc, op);
	519	}
	520
	521
	522	CPU_DISASSEMBLE( mips3le )
	523	{
	524	UINT32 op = (UINT32 )oprom;
	525	op = LITTLE_ENDIANIZE_INT32(op);
	526	return dasmmips3(buffer, pc, op);
	527	}
	528
	529

src/emu/cpu/mips/r3000.c
r5534	r5535
9	9	#include "debugger.h"
10	10	#include "r3000.h"
11	11
	12	CPU_DISASSEMBLE( r3000be );
	13	CPU_DISASSEMBLE( r3000le );
12	14
13	15	#define ENABLE_OVERFLOWS 0
14	16
r5534	r5535
888	890	DISASSEMBLY HOOK
889	891	***************************************************************************/
890	892
891		static CPU_DISASSEMBLE( r3000be )
892		{
893		extern unsigned dasmr3k(char *, unsigned, UINT32);
894		UINT32 op = (UINT32 )oprom;
895		op = BIG_ENDIANIZE_INT32(op);
896		return dasmr3k(buffer, pc, op);
897		}
898	893
899
900		static CPU_DISASSEMBLE( r3000le )
901		{
902		extern unsigned dasmr3k(char *, unsigned, UINT32);
903		UINT32 op = (UINT32 )oprom;
904		op = LITTLE_ENDIANIZE_INT32(op);
905		return dasmr3k(buffer, pc, op);
906		}
907
908
909
910	894	/***************************************************************************
911	895	CACHE I/O
912	896	***************************************************************************/

src/emu/cpu/mips/r3kdasm.c
r5534	r5535
369	369	}
370	370	return 4 \| flags \| DASMFLAG_SUPPORTED;
371	371	}
	372
	373
	374	CPU_DISASSEMBLE( r3000be )
	375	{
	376	UINT32 op = (UINT32 )oprom;
	377	op = BIG_ENDIANIZE_INT32(op);
	378	return dasmr3k(buffer, pc, op);
	379	}
	380
	381
	382	CPU_DISASSEMBLE( r3000le )
	383	{
	384	UINT32 op = (UINT32 )oprom;
	385	op = LITTLE_ENDIANIZE_INT32(op);
	386	return dasmr3k(buffer, pc, op);
	387	}

src/emu/cpu/mips/psxdasm.c
r5534	r5535
739	739	}
740	740	return ( opram - oldopram ) \| flags \| DASMFLAG_SUPPORTED;
741	741	}
	742
	743	CPU_DISASSEMBLE( psxcpu_generic )
	744	{
	745	DasmPSXCPU_state state = {0};
	746	state.pc = pc;
	747	return DasmPSXCPU( &state, buffer, pc, opram );
	748	}

src/emu/cpu/z80/z80.c
r5534	r5535
34	34	* - Fixed cycle counts for LD IYL/IXL/IYH/IXH,n [Marshmellow]
35	35	* - Fixed X/Y flags in CCF/SCF/BIT, ZEXALL is happy now [hap]
36	36	* - Simplified DAA, renamed MEMPTR (3.8) to WZ, added TODO [hap]
	37	* - Fixed IM2 interrupt cycles [eke]
37	38	* Changes in 3.8 [Miodrag Milanovic]:
38	39	* - Added MEMPTR register (according to informations provided
39	40	* by Vladimir Kladov
r5534	r5535
3296	3297	PUSH(z80, pc);
3297	3298	RM16(z80, irq_vector, &z80->pc);
3298	3299	LOG(("Z80 '%s' IM2 [$%04x] = $%04x\n", z80->device->tag, irq_vector, z80->PCD));
3299		/* CALL opcode timing */
3300		z80->icount -= z80->cc_op[0xcd];
	3300	/* CALL opcode timing + 'interrupt latency' cycles */
	3301	z80->icount -= z80->cc_op[0xcd] + z80->cc_ex[0xff];
3301	3302	}
3302	3303	else
3303	3304	/* Interrupt mode 1. RST 38h */

src/emu/cpu/esrip/esrip.c
r5534	r5535
11	11	#include "deprecat.h"
12	12	#include "esrip.h"
13	13
	14	CPU_DISASSEMBLE( esrip );
14	15
	16
15	17	/***************************************************************************
16	18	CONSTANTS
17	19	***************************************************************************/
r5534	r5535
1864	1866	}
1865	1867
1866	1868
1867		/***************************************************************************
1868		DISASSEMBLY HOOK (TODO: FINISH)
1869		***************************************************************************/
1870
1871		static CPU_DISASSEMBLE( esrip )
1872		{
1873		#if 0
1874		static const char* const jmp_types[] =
1875		{
1876		"JCT",
1877		"JT1",
1878		"JT2",
1879		"JT3",
1880		"JT4",
1881		"JLBRM",
1882		"J#HBLANK",
1883		"JMP",
1884		};
1885
1886		static const char* const njmp_types[] =
1887		{
1888		"JNCT",
1889		"JNT1",
1890		"JNT2",
1891		"JNT3",
1892		"JNT4",
1893		"JNLBRM",
1894		"J#HBLANK",
1895		" ",
1896		};
1897		#endif
1898
1899		UINT64 inst = BIG_ENDIANIZE_INT64((UINT64 )oprom);
1900
1901		UINT32 inst_hi = inst >> 32;
1902		UINT32 inst_lo = inst & 0xffffffff;
1903
1904		UINT16 ins = (inst_hi >> 16) & 0xffff;
1905		UINT8 ctrl = (inst_hi >> 8) & 0xff;
1906		UINT8 jmp_dest = (inst_lo >> 8) & 0xff;
1907
1908		UINT8 jmp_ctrl = (ctrl >> 3) & 0x1f;
1909
1910		UINT8 ctrl1 = (inst_lo >> 16) & 0xff;
1911		UINT8 ctrl2 = (inst_lo >> 24) & 0xff;
1912		UINT8 ctrl3 = (inst_hi) & 0xff;
1913
1914		sprintf(buffer, "%.4x %c%c%c%c %.2x %s%s%s%s%s%s%s%s %c%s%s%s %c%c%c%c%c%c%c%c\n",
1915		ins,
1916		ctrl & 1 ? 'D' : ' ',
1917		ctrl & 2 ? ' ' : 'Y',
1918		ctrl & 4 ? 'S' : ' ',
1919		(~jmp_ctrl & 0x18) ? 'J' : ' ',
1920		jmp_dest,
1921		ctrl1 & 0x01 ? " " : "I ",
1922		ctrl1 & 0x02 ? " " : "FL",
1923		ctrl1 & 0x04 ? "FE" : " ",
1924		ctrl1 & 0x08 ? " " : "FR",
1925		ctrl1 & 0x10 ? " " : "IL",
1926		ctrl1 & 0x20 ? "IE" : " ",
1927		ctrl1 & 0x40 ? " " : "IR",
1928		ctrl1 & 0x80 ? " " : "IW",
1929
1930		ctrl2 & 0x80 ? ' ' : 'O',
1931		ctrl2 & 0x40 ? " " : "IXLLD",
1932		ctrl2 & 0x20 ? " " : "IADLD",
1933		ctrl2 & 0x10 ? " " : "SCALD",
1934
1935		ctrl3 & 0x01 ? ' ' : '0',
1936		ctrl3 & 0x02 ? ' ' : '1',
1937		ctrl3 & 0x04 ? ' ' : '2',
1938		ctrl3 & 0x08 ? ' ' : '3',
1939		ctrl3 & 0x10 ? ' ' : '4',
1940		ctrl3 & 0x20 ? ' ' : '5',
1941		ctrl3 & 0x40 ? ' ' : '6',
1942		ctrl3 & 0x80 ? ' ' : '7'
1943		);
1944
1945		return 1 \| DASMFLAG_SUPPORTED;
1946		}
1947
1948	1869	/**************************************************************************
1949	1870	* set_info
1950	1871	**************************************************************************/

src/emu/cpu/esrip/esripdsm.c
r0	r5535
	1	/***************************************************************************
	2
	3	esripdsm.c
	4
	5	Implementation of the Entertainment Sciences
	6	AM29116-based Real Time Image Processor
	7
	8	***************************************************************************/
	9
	10	#include "debugger.h"
	11
	12
	13	/***************************************************************************
	14	DISASSEMBLY HOOK (TODO: FINISH)
	15	***************************************************************************/
	16
	17	CPU_DISASSEMBLE( esrip )
	18	{
	19	#if 0
	20	static const char* const jmp_types[] =
	21	{
	22	"JCT",
	23	"JT1",
	24	"JT2",
	25	"JT3",
	26	"JT4",
	27	"JLBRM",
	28	"J#HBLANK",
	29	"JMP",
	30	};
	31
	32	static const char* const njmp_types[] =
	33	{
	34	"JNCT",
	35	"JNT1",
	36	"JNT2",
	37	"JNT3",
	38	"JNT4",
	39	"JNLBRM",
	40	"J#HBLANK",
	41	" ",
	42	};
	43	#endif
	44
	45	UINT64 inst = BIG_ENDIANIZE_INT64((UINT64 )oprom);
	46
	47	UINT32 inst_hi = inst >> 32;
	48	UINT32 inst_lo = inst & 0xffffffff;
	49
	50	UINT16 ins = (inst_hi >> 16) & 0xffff;
	51	UINT8 ctrl = (inst_hi >> 8) & 0xff;
	52	UINT8 jmp_dest = (inst_lo >> 8) & 0xff;
	53
	54	UINT8 jmp_ctrl = (ctrl >> 3) & 0x1f;
	55
	56	UINT8 ctrl1 = (inst_lo >> 16) & 0xff;
	57	UINT8 ctrl2 = (inst_lo >> 24) & 0xff;
	58	UINT8 ctrl3 = (inst_hi) & 0xff;
	59
	60	sprintf(buffer, "%.4x %c%c%c%c %.2x %s%s%s%s%s%s%s%s %c%s%s%s %c%c%c%c%c%c%c%c",
	61	ins,
	62	ctrl & 1 ? 'D' : ' ',
	63	ctrl & 2 ? ' ' : 'Y',
	64	ctrl & 4 ? 'S' : ' ',
	65	(~jmp_ctrl & 0x18) ? 'J' : ' ',
	66	jmp_dest,
	67	ctrl1 & 0x01 ? " " : "I ",
	68	ctrl1 & 0x02 ? " " : "FL",
	69	ctrl1 & 0x04 ? "FE" : " ",
	70	ctrl1 & 0x08 ? " " : "FR",
	71	ctrl1 & 0x10 ? " " : "IL",
	72	ctrl1 & 0x20 ? "IE" : " ",
	73	ctrl1 & 0x40 ? " " : "IR",
	74	ctrl1 & 0x80 ? " " : "IW",
	75
	76	ctrl2 & 0x80 ? ' ' : 'O',
	77	ctrl2 & 0x40 ? " " : "IXLLD",
	78	ctrl2 & 0x20 ? " " : "IADLD",
	79	ctrl2 & 0x10 ? " " : "SCALD",
	80
	81	ctrl3 & 0x01 ? ' ' : '0',
	82	ctrl3 & 0x02 ? ' ' : '1',
	83	ctrl3 & 0x04 ? ' ' : '2',
	84	ctrl3 & 0x08 ? ' ' : '3',
	85	ctrl3 & 0x10 ? ' ' : '4',
	86	ctrl3 & 0x20 ? ' ' : '5',
	87	ctrl3 & 0x40 ? ' ' : '6',
	88	ctrl3 & 0x80 ? ' ' : '7'
	89	);
	90
	91	return 1 \| DASMFLAG_SUPPORTED;
	92	}

src/emu/cpu/i960/i960.c
r5534	r5535
3	3	#include "i960dis.h"
4	4	#include <math.h>
5	5
	6	CPU_DISASSEMBLE( i960 );
	7
6	8	#ifdef _MSC_VER
7	9	/* logb prototype is different for MS Visual C */
8	10	#include <float.h>
r5534	r5535
2084	2086	state_save_register_device_item_array(device, 0, i960->rcache_frame_addr);
2085	2087	}
2086	2088
2087		static CPU_DISASSEMBLE( i960 )
2088		{
2089		disassemble_t dis;
2090
2091		dis.IP = pc;
2092		dis.buffer = buffer;
2093		dis.oprom = oprom;
2094
2095		i960_disassemble(&dis);
2096
2097		return dis.IPinc \| dis.disflags \| DASMFLAG_SUPPORTED;
2098		}
2099
2100	2089	static CPU_RESET( i960 )
2101	2090	{
2102	2091	i960_state_t *i960 = get_safe_token(device);

src/emu/cpu/i960/i960dis.c
r5534	r5535
289	289
290	290
291	291
	292	CPU_DISASSEMBLE( i960 )
	293	{
	294	disassemble_t dis;
	295
	296	dis.IP = pc;
	297	dis.buffer = buffer;
	298	dis.oprom = oprom;
	299
	300	i960_disassemble(&dis);
	301
	302	return dis.IPinc \| dis.disflags \| DASMFLAG_SUPPORTED;
	303	}
	304

src/emu/cpu/mb86233/mb86233.c
r5534	r5535
16	16	#include "mb86233.h"
17	17	#include "debugger.h"
18	18
	19	CPU_DISASSEMBLE( mb86233 );
	20
19	21	/***************************************************************************
20	22	STRUCTURES & TYPEDEFS
21	23	***************************************************************************/
r5534	r5535
1558	1560	}
1559	1561
1560	1562	/***************************************************************************
1561		DISASSEMBLY HOOK
1562		***************************************************************************/
1563
1564		static CPU_DISASSEMBLE( mb86233 )
1565		{
1566		extern UINT32 dasm_mb86233(char *, UINT32);
1567
1568		UINT32 op = (UINT32 )oprom;
1569		op = LITTLE_ENDIANIZE_INT32(op);
1570		return dasm_mb86233(buffer, op);
1571		}
1572
1573
1574		/***************************************************************************
1575	1563	Information Setters
1576	1564	***************************************************************************/
1577	1565

src/emu/cpu/mb86233/mb86233d.c
r5534	r5535
772	772
773	773	return (1 \| DASMFLAG_SUPPORTED);
774	774	}
	775
	776	CPU_DISASSEMBLE( mb86233 )
	777	{
	778	UINT32 op = (UINT32 )oprom;
	779	op = LITTLE_ENDIANIZE_INT32(op);
	780	return dasm_mb86233(buffer, op);
	781	}

src/emu/cpu/arm7/arm7.c
r5534	r5535
279	279
280	280	static CPU_DISASSEMBLE( arm7 )
281	281	{
	282	CPU_DISASSEMBLE( arm7arm );
	283	CPU_DISASSEMBLE( arm7thumb );
	284
282	285	arm_state *cpustate = get_safe_token(device);
283	286
284	287	if (T_IS_SET(GET_CPSR))
285		{
286		return thumb_disasm(buffer, pc, oprom[0] \| (oprom[1] << 8)) \| 2;
287		}
	288	return CPU_DISASSEMBLE_CALL(arm7thumb);
288	289	else
289		{
290		return arm7_disasm(buffer, pc, oprom[0] \| (oprom[1] << 8) \| (oprom[2] << 16) \| (oprom[3] << 24)) \| 4;
291		}
	290	return CPU_DISASSEMBLE_CALL(arm7arm);
292	291	}
293	292
294	293

src/emu/cpu/arm7/arm7dasm.c
r5534	r5535
1305	1305
1306	1306	return dasmflags \| DASMFLAG_SUPPORTED;
1307	1307	}
	1308
	1309	CPU_DISASSEMBLE( arm7arm )
	1310	{
	1311	return arm7_disasm(buffer, pc, oprom[0] \| (oprom[1] << 8) \| (oprom[2] << 16) \| (oprom[3] << 24)) \| 4;
	1312	}
	1313
	1314	CPU_DISASSEMBLE( arm7thumb )
	1315	{
	1316	return thumb_disasm(buffer, pc, oprom[0] \| (oprom[1] << 8)) \| 2;
	1317	}

src/emu/video/mc6845.c
r5534	r5535
436	436
437	437	static void update_upd_adr_timer(mc6845_t *mc6845)
438	438	{
439		if (!is_display_enabled(mc6845))
	439	if (!is_display_enabled(mc6845) && supports_transparent[mc6845->device_type])
440	440	timer_adjust_oneshot(mc6845->upd_adr_timer, mc6845->upd_time, 0);
441	441	}
442	442
r5534	r5535
466	466	if (next_y == mc6845->vert_pix_total)
467	467	next_y = -1;
468	468	}
469		timer_adjust_oneshot(mc6845->upd_adr_timer, attotime_never, 0);
	469	if (supports_transparent[mc6845->device_type]) timer_adjust_oneshot(mc6845->upd_adr_timer, attotime_never, 0);
470	470	}
471	471
472	472	/* we are in a blanking region, get the location of the next display start */

src/emu/emu.mak
r5534	r5535
202	202
203	203	include $(EMUSRC)/cpu/cpu.mak
204	204
205		$(LIBCPU): $(CPUOBJS) ~~$(DBGOBJS)~~
	205	$(LIBCPU): $(CPUOBJS)
206	206
	207	$(LIBDASM): $(DASMOBJS)
207	208
208	209
	210
209	211	#-------------------------------------------------
210	212	# sound core objects
211	213	#-------------------------------------------------

src/emu/inpttype.h
r5534	r5535
113	113	INPUT_PORT_DIGITAL_TYPE( 1, PLAYER1, POKER_HOLD4, "Hold 4", SEQ_DEF_1(KEYCODE_V) )
114	114	INPUT_PORT_DIGITAL_TYPE( 1, PLAYER1, POKER_HOLD5, "Hold 5", SEQ_DEF_1(KEYCODE_B) )
115	115	INPUT_PORT_DIGITAL_TYPE( 1, PLAYER1, POKER_CANCEL, "Cancel", SEQ_DEF_1(KEYCODE_N) )
	116	INPUT_PORT_DIGITAL_TYPE( 1, PLAYER1, POKER_BET, "Bet", SEQ_DEF_1(KEYCODE_1) )
116	117	INPUT_PORT_DIGITAL_TYPE( 1, PLAYER1, SLOT_STOP1, "Stop Reel 1", SEQ_DEF_1(KEYCODE_X) )
117	118	INPUT_PORT_DIGITAL_TYPE( 1, PLAYER1, SLOT_STOP2, "Stop Reel 2", SEQ_DEF_1(KEYCODE_C) )
118	119	INPUT_PORT_DIGITAL_TYPE( 1, PLAYER1, SLOT_STOP3, "Stop Reel 3", SEQ_DEF_1(KEYCODE_V) )

src/emu/inptport.h
r5534	r5535
255	255	IPT_POKER_HOLD4,
256	256	IPT_POKER_HOLD5,
257	257	IPT_POKER_CANCEL,
	258	IPT_POKER_BET,
258	259
259	260	/* slot-specific inputs */
260	261	IPT_SLOT_STOP1,

src/emu/sound/disc_inp.c
r5534	r5535
15	15	*
16	16	************************************************************************/
17	17
18		#define DSS_INPUT__GAIN (*(node->input[0]))
19		#define DSS_INPUT__OFFSET (*(node->input[1]))
20		#define DSS_INPUT__INIT (*(node->input[2]))
21	18
	19	#define DSS_INPUT__GAIN DISCRETE_INPUT(0)
	20	#define DSS_INPUT__OFFSET DISCRETE_INPUT(1)
	21	#define DSS_INPUT__INIT DISCRETE_INPUT(2)
22	22
	23
23	24	struct dss_adjustment_context
24	25	{
25	26	const input_port_config *port;
r5534	r5535
30	31	double scale;
31	32	};
32	33
	34	struct dss_input_context
	35	{
	36	stream_sample_t ptr; / current in ptr for stream */
	37	UINT8 data; /* data written */
	38	double gain; /* node gain */
	39	double offset; /* node offset */
	40	UINT8 is_stream;
	41	UINT8 is_buffered;
	42	UINT32 stream_in_number;
	43	UINT32 stream_out_number;
	44	};
	45
33	46	INLINE discrete_info get_safe_token(const device_config device)
34	47	{
35	48	assert(device != NULL);
r5534	r5535
49	62	/* Read the node input value if allowed */
50	63	if (node)
51	64	{
52		~~UINT8~~ node~~_da~~ta = (~~UINT8~~ )node->context;
	65	struct dss_input_context context = (struct dss_input_context )node->context;
53	66
54	67	/* Bring the system up to now */
55	68	stream_update(info->discrete_stream);
56	69
57		if ((node->module.type >= DSS_INPUT_DATA) && (node->module.type <= DSS_INPUT_PULSE))
	70	if ((node->module->type >= DSS_INPUT_DATA) && (node->module->type <= DSS_INPUT_PULSE))
58	71	{
59		data = *node_data;
	72	data = context->data;
60	73	}
61	74	}
62	75	else
r5534	r5535
65	78	return data;
66	79	}
67	80
68		#if 0
69		static STREAM_BACKGROUND_CALLBACK( disc_cb )
70		{
71		node_description node = (node_description ) ptr;
72	81
73		node->output[0] = param * DSS_INPUT__GAIN + DSS_INPUT__OFFSET;
74		}
75		#endif
76
77	82	WRITE8_DEVICE_HANDLER(discrete_sound_w)
78	83	{
79	84	discrete_info *info = get_safe_token(device);
r5534	r5535
82	87	/* Update the node input value if it's a proper input node */
83	88	if (node)
84	89	{
85		UINT8 node_data = (UINT8 )node->context;
86		UINT8 last_data = *node_data;
	90	struct dss_input_context context = (struct dss_input_context )node->context;
87	91	UINT8 new_data = 0;
88	92
89		switch (node->module.type)
	93	switch (node->module->type)
90	94	{
91	95	case DSS_INPUT_DATA:
92	96	new_data = data;
r5534	r5535
100	104	break;
101	105	}
102	106
103		if (~~las~~t_data != new_data)
	107	if (context->data != new_data)
104	108	{
105		#if 1
106	109	/* Bring the system up to now */
107	110	stream_update(info->discrete_stream);
108	111
109		*node_data = new_data;
	112	context->data = new_data;
110	113
111	114	/* Update the node output here so we don't have to do it each step */
112		node->output[0] = node_data DSS_INPUT__GAIN + DSS_INPUT__OFFSET;
113		#else
114		*node_data = new_data;
115		/* Bring the system up to now */
116		stream_update_background(info->discrete_stream, disc_cb, (void ) node, node_data);
117
118		#endif
	115	node->output[0] = new_data * context->gain + context->offset;
119	116	}
120	117	}
121	118	else
r5534	r5535
137	134	* input[6] -
138	135	*
139	136	************************************************************************/
140		#define DSS_ADJUSTMENT__MIN (*(node->input[0]))
141		#define DSS_ADJUSTMENT__MAX (*(node->input[1]))
142		#define DSS_ADJUSTMENT__LOG (*(node->input[2]))
143		#define DSS_ADJUSTMENT__PORT (*(node->input[3]))
144		#define DSS_ADJUSTMENT__PMIN (*(node->input[4]))
145		#define DSS_ADJUSTMENT__PMAX (*(node->input[5]))
	137	#define DSS_ADJUSTMENT__MIN DISCRETE_INPUT(0)
	138	#define DSS_ADJUSTMENT__MAX DISCRETE_INPUT(1)
	139	#define DSS_ADJUSTMENT__LOG DISCRETE_INPUT(2)
	140	#define DSS_ADJUSTMENT__PORT DISCRETE_INPUT(3)
	141	#define DSS_ADJUSTMENT__PMIN DISCRETE_INPUT(4)
	142	#define DSS_ADJUSTMENT__PMAX DISCRETE_INPUT(5)
146	143
147	144	static DISCRETE_STEP(dss_adjustment)
148	145	{
r5534	r5535
172	169
173	170	if (node->custom)
174	171	{
175		context->port = input_port_by_tag(d~~isc_~~info->device->machine->portconfig, (const char *)node->custom);
	172	context->port = input_port_by_tag(node->info->device->machine->portconfig, (const char *)node->custom);
176	173	if (context->port == NULL)
177	174	fatalerror("DISCRETE_ADJUSTMENT_TAG - NODE_%d has invalid tag", node->node-NODE_00);
178	175	}
179	176	else
180		context->port = input_port_by_index(d~~isc_~~info->device->machine->portconfig, DSS_ADJUSTMENT__PORT);
	177	context->port = input_port_by_index(node->info->device->machine->portconfig, DSS_ADJUSTMENT__PORT);
181	178
182	179	context->lastpval = 0x7fffffff;
183	180	context->pmin = DSS_ADJUSTMENT__PMIN;
r5534	r5535
211	208	* input[0] - Constant value
212	209	*
213	210	************************************************************************/
214		#define DSS_CONSTANT__INIT (*(node->input[0]))
	211	#define DSS_CONSTANT__INIT DISCRETE_INPUT(0)
215	212
216	213	static DISCRETE_RESET(dss_constant)
217	214	{
r5534	r5535
231	228	************************************************************************/
232	229	static DISCRETE_RESET(dss_input)
233	230	{
234		~~UINT8~~ node~~_da~~ta = (~~UINT8~~ )node->context;
	231	struct dss_input_context context = (struct dss_input_context )node->context;
235	232
236		switch (node->module.type)
	233	context->is_buffered = FALSE;
	234	context->is_stream = FALSE;
	235	context->gain = DSS_INPUT__GAIN;
	236	context->offset = DSS_INPUT__OFFSET;
	237
	238	switch (node->module->type)
237	239	{
238	240	case DSS_INPUT_DATA:
239		*node_data = DSS_INPUT__INIT;
	241	context->data = DSS_INPUT__INIT;
240	242	break;
241	243	case DSS_INPUT_LOGIC:
242	244	case DSS_INPUT_PULSE:
243		*node_data = (DSS_INPUT__INIT == 0) ? 0 : 1;
	245	context->data = (DSS_INPUT__INIT == 0) ? 0 : 1;
244	246	break;
245	247	case DSS_INPUT_NOT:
246		*node_data = (DSS_INPUT__INIT == 0) ? 1 : 0;
	248	context->data = (DSS_INPUT__INIT == 0) ? 1 : 0;
247	249	break;
248	250	}
249		node->output[0] = node_data ~~DSS_INPUT__GAIN~~ + ~~DSS_INPUT__OFFSET~~;
	251	node->output[0] = context->data * context->gain + context->offset;
250	252	}
251	253
252	254	static DISCRETE_STEP(dss_input_pulse)
253	255	{
254		~~UINT8~~ node~~_da~~ta = (~~UINT8~~ )node->context;
	256	struct dss_input_context context = (struct dss_input_context )node->context;
255	257
256	258	/* Set a valid output */
257		node->output[0] = *node_data;
	259	node->output[0] = context->data;
258	260	/* Reset the input to default for the next cycle */
259	261	/* node order is now important */
260		*node_data = DSS_INPUT__INIT;
	262	context->data = DSS_INPUT__INIT;
261	263	}
262	264
263	265
r5534	r5535
270	272	* input[2] - Offset value
271	273	*
272	274	************************************************************************/
273		#define DSS_INPUT_STREAM__STREAM (*(node->input[0]))
274		#define DSS_INPUT_STREAM__GAIN (*(node->input[1]))
275		#define DSS_INPUT_STREAM__OFFSET (*(node->input[2]))
	275	#define DSS_INPUT_STREAM__STREAM DISCRETE_INPUT(0)
	276	#define DSS_INPUT_STREAM__GAIN DISCRETE_INPUT(1)
	277	#define DSS_INPUT_STREAM__OFFSET DISCRETE_INPUT(2)
276	278
277	279	static DISCRETE_STEP(dss_input_stream)
278	280	{
279	281	/* the context pointer is set to point to the current input stream data in discrete_stream_update */
280		stream_sample_t ptr = (stream_sample_t )node->context;
281		stream_sample_t data = ptr;
	282	struct dss_input_context context = (struct dss_input_context )node->context;
282	283
283		node->output[0] = data ? (data) DSS_INPUT_STREAM__GAIN + DSS_INPUT_STREAM__OFFSET : 0;
	284	if (context->ptr)
	285	{
	286	node->output[0] = (context->ptr) context->gain + context->offset;
	287	context->ptr++;
	288	}
	289	else
	290	node->output[0] = 0;
284	291	}
285	292
286	293	static DISCRETE_RESET(dss_input_stream)
287	294	{
288		int istream = DSS_INPUT_STREAM__STREAM;
289		/* we will use the node's context pointer to point to the input stream data */
290		assert(istream < disc_info->discrete_input_streams);
291		node->context = (discrete_info *) &disc_info->input_stream_data[istream];
	295	struct dss_input_context context = (struct dss_input_context )node->context;
	296
	297	assert(DSS_INPUT_STREAM__STREAM < linked_list_count(node->info->input_list));
	298	context->is_buffered = FALSE;
	299	context->is_stream = TRUE;
	300	context->stream_in_number = DSS_INPUT_STREAM__STREAM;
	301	context->gain = DSS_INPUT_STREAM__GAIN;
	302	context->offset = DSS_INPUT_STREAM__OFFSET;
	303	context->ptr = NULL;
292	304	}

src/emu/sound/disc_mth.c
r5534	r5535
180	180	* input[4] - Channel3 input value
181	181	*
182	182	************************************************************************/
183		#define DST_ADDER__ENABLE (*(node->input[0]))
184		#define DST_ADDER__IN0 (*(node->input[1]))
185		#define DST_ADDER__IN1 (*(node->input[2]))
186		#define DST_ADDER__IN2 (*(node->input[3]))
187		#define DST_ADDER__IN3 (*(node->input[4]))
	183	#define DST_ADDER__ENABLE DISCRETE_INPUT(0)
	184	#define DST_ADDER__IN0 DISCRETE_INPUT(1)
	185	#define DST_ADDER__IN1 DISCRETE_INPUT(2)
	186	#define DST_ADDER__IN2 DISCRETE_INPUT(3)
	187	#define DST_ADDER__IN3 DISCRETE_INPUT(4)
188	188
189	189	static DISCRETE_STEP(dst_adder)
190	190	{
r5534	r5535
209	209	*
210	210	* Mar 2004, D Renaud.
211	211	************************************************************************/
212		#define DST_COMP_ADDER__SELECT (*(node->input[0]))
	212	#define DST_COMP_ADDER__SELECT DISCRETE_INPUT(0)
213	213
214	214	static DISCRETE_STEP(dst_comp_adder)
215	215	{
r5534	r5535
267	267	* input[4] - Clamp output when disabled
268	268	*
269	269	************************************************************************/
270		#define DST_CLAMP__ENABLE (*(node->input[0]))
271		#define DST_CLAMP__IN (*(node->input[1]))
272		#define DST_CLAMP__MIN (*(node->input[2]))
273		#define DST_CLAMP__MAX (*(node->input[3]))
274		#define DST_CLAMP__CLAMP (*(node->input[4]))
	270	#define DST_CLAMP__ENABLE DISCRETE_INPUT(0)
	271	#define DST_CLAMP__IN DISCRETE_INPUT(1)
	272	#define DST_CLAMP__MIN DISCRETE_INPUT(2)
	273	#define DST_CLAMP__MAX DISCRETE_INPUT(3)
	274	#define DST_CLAMP__CLAMP DISCRETE_INPUT(4)
275	275
276	276	static DISCRETE_STEP(dst_clamp)
277	277	{
r5534	r5535
300	300	*
301	301	* Mar 2004, D Renaud.
302	302	************************************************************************/
303		#define DST_DAC_R1__ENABLE (*(node->input[0]))
304		#define DST_DAC_R1__DATA (*(node->input[1]))
305		#define DST_DAC_R1__VON (*(node->input[2]))
	303	#define DST_DAC_R1__ENABLE DISCRETE_INPUT(0)
	304	#define DST_DAC_R1__DATA DISCRETE_INPUT(1)
	305	#define DST_DAC_R1__VON DISCRETE_INPUT(2)
306	306
307	307	static DISCRETE_STEP(dst_dac_r1)
308	308	{
r5534	r5535
384	384	if (info->ladderLength < 2)
385	385	{
386	386	/* You need at least 2 resistors for a ladder */
387		discrete_log(d~~isc_~~info, "dst_dac_r1_reset - Ladder length too small");
	387	discrete_log(node->info, "dst_dac_r1_reset - Ladder length too small");
388	388	}
389	389	if (info->ladderLength > DISC_LADDER_MAXRES )
390	390	{
391		discrete_log(d~~isc_~~info, "dst_dac_r1_reset - Ladder length exceeds DISC_LADDER_MAXRES");
	391	discrete_log(node->info, "dst_dac_r1_reset - Ladder length exceeds DISC_LADDER_MAXRES");
392	392	}
393	393
394	394	/*
r5534	r5535
426	426	* Dec 2004, D Renaud.
427	427	************************************************************************/
428	428	#define DST_DIODE_MIX_INP_OFFSET 0
429		#define DST_DIODE_MIX__INP(addr) (*(node->input[DST_DIODE_MIX_INP_OFFSET + addr]))
	429	#define DST_DIODE_MIX__INP(addr) DISCRETE_INPUT(DST_DIODE_MIX_INP_OFFSET + addr)
430	430
431	431	static DISCRETE_STEP(dst_diode_mix)
432	432	{
r5534	r5535
480	480	* input[2] - Divisor
481	481	*
482	482	************************************************************************/
483		#define DST_DIVIDE__ENABLE (*(node->input[0]))
484		#define DST_DIVIDE__IN (*(node->input[1]))
485		#define DST_DIVIDE__DIV (*(node->input[2]))
	483	#define DST_DIVIDE__ENABLE DISCRETE_INPUT(0)
	484	#define DST_DIVIDE__IN DISCRETE_INPUT(1)
	485	#define DST_DIVIDE__DIV DISCRETE_INPUT(2)
486	486
487	487	static DISCRETE_STEP(dst_divide)
488	488	{
r5534	r5535
491	491	if(DST_DIVIDE__DIV == 0)
492	492	{
493	493	node->output[0 ]= DBL_MAX; /* Max out but don't break */
494		discrete_log(d~~isc_~~info, "dst_divider_step() - Divide by Zero attempted in NODE_%02d.\n",NODE_INDEX(node->node));
	494	discrete_log(node->info, "dst_divider_step() - Divide by Zero attempted in NODE_%02d.\n",NODE_INDEX(node->node));
495	495	}
496	496	else
497	497	{
r5534	r5535
515	515	* input[3] - Final addition offset
516	516	*
517	517	************************************************************************/
518		#define DST_GAIN__ENABLE (*(node->input[0]))
519		#define DST_GAIN__IN (*(node->input[1]))
520		#define DST_GAIN__GAIN (*(node->input[2]))
521		#define DST_GAIN__OFFSET (*(node->input[3]))
	518	#define DST_GAIN__ENABLE DISCRETE_INPUT(0)
	519	#define DST_GAIN__IN DISCRETE_INPUT(1)
	520	#define DST_GAIN__GAIN DISCRETE_INPUT(2)
	521	#define DST_GAIN__OFFSET DISCRETE_INPUT(3)
522	522
523	523	static DISCRETE_STEP(dst_gain)
524	524	{
r5534	r5535
545	545	*
546	546	* Mar 2004, D Renaud.
547	547	************************************************************************/
548		#define DST_INTEGRATE__TRG0 (*(node->input[0]))
549		#define DST_INTEGRATE__TRG1 (*(node->input[1]))
	548	#define DST_INTEGRATE__TRG0 DISCRETE_INPUT(0)
	549	#define DST_INTEGRATE__TRG1 DISCRETE_INPUT(1)
550	550
551	551	static int dst_trigger_function(int trig0, int trig1, int trig2, int function)
552	552	{
r5534	r5535
609	609	i_neg = context->v_max_in / info->r1;
610	610	i_pos = (DST_INTEGRATE__TRG0 - OP_AMP_NORTON_VBE) / info->r2;
611	611	if (i_pos < 0) i_pos = 0;
612		node->output[0] += (i_pos - i_neg) / d~~isc_~~info->sample_rate / info->c;
	612	node->output[0] += (i_pos - i_neg) / node->info->sample_rate / info->c;
613	613	break;
614	614
615	615	case DISC_INTEGRATE_OP_AMP_2 \| DISC_OP_AMP_IS_NORTON:
r5534	r5535
618	618	i_neg = dst_trigger_function(trig0, trig1, 0, info->f0) ? context->v_max_in_d / info->r1 : 0;
619	619	i_pos = dst_trigger_function(trig0, trig1, 0, info->f1) ? context->v_max_in / info->r2 : 0;
620	620	i_pos += dst_trigger_function(trig0, trig1, 0, info->f2) ? context->v_max_in_d / info->r3 : 0;
621		node->output[0] += (i_pos - i_neg) / d~~isc_~~info->sample_rate / info->c;
	621	node->output[0] += (i_pos - i_neg) / node->info->sample_rate / info->c;
622	622	break;
623	623	}
624	624
r5534	r5535
646	646	v = info->v1 * info->r3 / (info->r2 + info->r3); /* vRef */
647	647	v = info->v1 - v; /* actual charging voltage */
648	648	i = v / info->r1;
649		context->change = i / d~~isc_~~info->sample_rate / info->c;
	649	context->change = i / node->info->sample_rate / info->c;
650	650	}
651	651	node->output[0] = 0;
652	652	}
r5534	r5535
660	660	* input[1] - input[0] value
661	661	*
662	662	************************************************************************/
663		#define DST_LOGIC_INV__ENABLE (*(node->input[0]))
664		#define DST_LOGIC_INV__IN (*(node->input[1]))
	663	#define DST_LOGIC_INV__ENABLE DISCRETE_INPUT(0)
	664	#define DST_LOGIC_INV__IN DISCRETE_INPUT(1)
665	665
666	666	static DISCRETE_STEP(dst_logic_inv)
667	667	{
r5534	r5535
684	684	* input[2] - To bit
685	685	*
686	686	************************************************************************/
687		#define DST_BITS_DECODE__IN (*(node->input[0]))
688		#define DST_BITS_DECODE__FROM (*(node->input[1]))
689		#define DST_BITS_DECODE__TO (*(node->input[2]))
690		#define DST_BITS_DECODE__VOUT (*(node->input[3]))
	687	#define DST_BITS_DECODE__IN DISCRETE_INPUT(0)
	688	#define DST_BITS_DECODE__FROM DISCRETE_INPUT(1)
	689	#define DST_BITS_DECODE__TO DISCRETE_INPUT(2)
	690	#define DST_BITS_DECODE__VOUT DISCRETE_INPUT(3)
691	691
692	692	static DISCRETE_STEP(dst_bits_decode)
693	693	{
r5534	r5535
724	724	* input[4] - input[3] value
725	725	*
726	726	************************************************************************/
727		#define DST_LOGIC_AND__ENABLE (*(node->input[0]))
728		#define DST_LOGIC_AND__IN0 (*(node->input[1]))
729		#define DST_LOGIC_AND__IN1 (*(node->input[2]))
730		#define DST_LOGIC_AND__IN2 (*(node->input[3]))
731		#define DST_LOGIC_AND__IN3 (*(node->input[4]))
	727	#define DST_LOGIC_AND__ENABLE DISCRETE_INPUT(0)
	728	#define DST_LOGIC_AND__IN0 DISCRETE_INPUT(1)
	729	#define DST_LOGIC_AND__IN1 DISCRETE_INPUT(2)
	730	#define DST_LOGIC_AND__IN2 DISCRETE_INPUT(3)
	731	#define DST_LOGIC_AND__IN3 DISCRETE_INPUT(4)
732	732
733	733	static DISCRETE_STEP(dst_logic_and)
734	734	{
r5534	r5535
753	753	* input[4] - input[3] value
754	754	*
755	755	************************************************************************/
756		#define DST_LOGIC_NAND__ENABLE (*(node->input[0]))
757		#define DST_LOGIC_NAND__IN0 (*(node->input[1]))
758		#define DST_LOGIC_NAND__IN1 (*(node->input[2]))
759		#define DST_LOGIC_NAND__IN2 (*(node->input[3]))
760		#define DST_LOGIC_NAND__IN3 (*(node->input[4]))
	756	#define DST_LOGIC_NAND__ENABLE DISCRETE_INPUT(0)
	757	#define DST_LOGIC_NAND__IN0 DISCRETE_INPUT(1)
	758	#define DST_LOGIC_NAND__IN1 DISCRETE_INPUT(2)
	759	#define DST_LOGIC_NAND__IN2 DISCRETE_INPUT(3)
	760	#define DST_LOGIC_NAND__IN3 DISCRETE_INPUT(4)
761	761
762	762	static DISCRETE_STEP(dst_logic_nand)
763	763	{
r5534	r5535
782	782	* input[4] - input[3] value
783	783	*
784	784	************************************************************************/
785		#define DST_LOGIC_OR__ENABLE (*(node->input[0]))
786		#define DST_LOGIC_OR__IN0 (*(node->input[1]))
787		#define DST_LOGIC_OR__IN1 (*(node->input[2]))
788		#define DST_LOGIC_OR__IN2 (*(node->input[3]))
789		#define DST_LOGIC_OR__IN3 (*(node->input[4]))
	785	#define DST_LOGIC_OR__ENABLE DISCRETE_INPUT(0)
	786	#define DST_LOGIC_OR__IN0 DISCRETE_INPUT(1)
	787	#define DST_LOGIC_OR__IN1 DISCRETE_INPUT(2)
	788	#define DST_LOGIC_OR__IN2 DISCRETE_INPUT(3)
	789	#define DST_LOGIC_OR__IN3 DISCRETE_INPUT(4)
790	790
791	791	static DISCRETE_STEP(dst_logic_or)
792	792	{
r5534	r5535
811	811	* input[4] - input[3] value
812	812	*
813	813	************************************************************************/
814		#define DST_LOGIC_NOR__ENABLE (*(node->input[0]))
815		#define DST_LOGIC_NOR__IN0 (*(node->input[1]))
816		#define DST_LOGIC_NOR__IN1 (*(node->input[2]))
817		#define DST_LOGIC_NOR__IN2 (*(node->input[3]))
818		#define DST_LOGIC_NOR__IN3 (*(node->input[4]))
	814	#define DST_LOGIC_NOR__ENABLE DISCRETE_INPUT(0)
	815	#define DST_LOGIC_NOR__IN0 DISCRETE_INPUT(1)
	816	#define DST_LOGIC_NOR__IN1 DISCRETE_INPUT(2)
	817	#define DST_LOGIC_NOR__IN2 DISCRETE_INPUT(3)
	818	#define DST_LOGIC_NOR__IN3 DISCRETE_INPUT(4)
819	819
820	820	static DISCRETE_STEP(dst_logic_nor)
821	821	{
r5534	r5535
838	838	* input[2] - input[1] value
839	839	*
840	840	************************************************************************/
841		#define DST_LOGIC_XOR__ENABLE (*(node->input[0]))
842		#define DST_LOGIC_XOR__IN0 (*(node->input[1]))
843		#define DST_LOGIC_XOR__IN1 (*(node->input[2]))
	841	#define DST_LOGIC_XOR__ENABLE DISCRETE_INPUT(0)
	842	#define DST_LOGIC_XOR__IN0 DISCRETE_INPUT(1)
	843	#define DST_LOGIC_XOR__IN1 DISCRETE_INPUT(2)
844	844
845	845	static DISCRETE_STEP(dst_logic_xor)
846	846	{
r5534	r5535
863	863	* input[2] - input[1] value
864	864	*
865	865	************************************************************************/
866		#define DST_LOGIC_XNOR__ENABLE (*(node->input[0]))
867		#define DST_LOGIC_XNOR__IN0 (*(node->input[1]))
868		#define DST_LOGIC_XNOR__IN1 (*(node->input[2]))
	866	#define DST_LOGIC_XNOR__ENABLE DISCRETE_INPUT(0)
	867	#define DST_LOGIC_XNOR__IN0 DISCRETE_INPUT(1)
	868	#define DST_LOGIC_XNOR__IN1 DISCRETE_INPUT(2)
869	869
870	870	static DISCRETE_STEP(dst_logic_nxor)
871	871	{
r5534	r5535
891	891	* input[4] - data
892	892	*
893	893	************************************************************************/
894		#define DST_LOGIC_DFF__ENABLE (*(node->input[0]))
895		#define DST_LOGIC_DFF__RESET !(*(node->input[1]))
896		#define DST_LOGIC_DFF__SET !(*(node->input[2]))
897		#define DST_LOGIC_DFF__CLOCK (*(node->input[3]))
898		#define DST_LOGIC_DFF__DATA (*(node->input[4]))
	894	#define DST_LOGIC_DFF__ENABLE DISCRETE_INPUT(0)
	895	#define DST_LOGIC_DFF__RESET !DISCRETE_INPUT(1)
	896	#define DST_LOGIC_DFF__SET !DISCRETE_INPUT(2)
	897	#define DST_LOGIC_DFF__CLOCK DISCRETE_INPUT(3)
	898	#define DST_LOGIC_DFF__DATA DISCRETE_INPUT(4)
899	899
900	900	static DISCRETE_STEP(dst_logic_dff)
901	901	{
r5534	r5535
940	940	* input[5] - K
941	941	*
942	942	************************************************************************/
943		#define DST_LOGIC_JKFF__ENABLE (*(node->input[0]))
944		#define DST_LOGIC_JKFF__RESET !(*(node->input[1]))
945		#define DST_LOGIC_JKFF__SET !(*(node->input[2]))
946		#define DST_LOGIC_JKFF__CLOCK (*(node->input[3]))
947		#define DST_LOGIC_JKFF__J (*(node->input[4]))
948		#define DST_LOGIC_JKFF__K (*(node->input[5]))
	943	#define DST_LOGIC_JKFF__ENABLE DISCRETE_INPUT(0)
	944	#define DST_LOGIC_JKFF__RESET !DISCRETE_INPUT(1)
	945	#define DST_LOGIC_JKFF__SET !DISCRETE_INPUT(2)
	946	#define DST_LOGIC_JKFF__CLOCK DISCRETE_INPUT(3)
	947	#define DST_LOGIC_JKFF__J DISCRETE_INPUT(4)
	948	#define DST_LOGIC_JKFF__K DISCRETE_INPUT(5)
949	949
950	950	static DISCRETE_STEP(dst_logic_jkff)
951	951	{
r5534	r5535
1001	1001	*
1002	1002	* Feb 2007, D Renaud.
1003	1003	************************************************************************/
1004		#define DST_LOOKUP_TABLE__ENABLE (*(node->input[0]))
1005		#define DST_LOOKUP_TABLE__IN (*(node->input[1]))
1006		#define DST_LOOKUP_TABLE__SIZE (*(node->input[2]))
	1004	#define DST_LOOKUP_TABLE__ENABLE DISCRETE_INPUT(0)
	1005	#define DST_LOOKUP_TABLE__IN DISCRETE_INPUT(1)
	1006	#define DST_LOOKUP_TABLE__SIZE DISCRETE_INPUT(2)
1007	1007
1008	1008	static DISCRETE_STEP(dst_lookup_table)
1009	1009	{
r5534	r5535
1068	1068	* The voltage is then modified by an inverting amp formula.
1069	1069	* v = vRef + (rF/rI) * (vRef - (i * r))
1070	1070	*/
1071		#define DST_MIXER__ENABLE (*(node->input[0]))
1072		#define DST_MIXER__IN(bit) (*(node->input[bit + 1]))
	1071	#define DST_MIXER__ENABLE DISCRETE_INPUT(0)
	1072	#define DST_MIXER__IN(bit) DISCRETE_INPUT(bit + 1)
1073	1073
1074	1074	static DISCRETE_STEP(dst_mixer)
1075	1075	{
r5534	r5535
1227	1227	context->r_node_bit_flag = 0;
1228	1228	for (bit = 0; bit < 8; bit++)
1229	1229	{
1230		r_node = discrete_find_node(d~~isc_~~info, info->r_node[bit]);
	1230	r_node = discrete_find_node(node->info, info->r_node[bit]);
1231	1231	if (r_node != NULL)
1232	1232	{
1233	1233	context->r_node[bit] = &(r_node->output[NODE_CHILD_NODE_NUM(info->r_node[bit])]);
r5534	r5535
1334	1334	*
1335	1335	* Dec 2004, D Renaud.
1336	1336	************************************************************************/
1337		#define DST_MULTIPLEX__ENABLE (*(node->input[0]))
1338		#define DST_MULTIPLEX__ADDR (*(node->input[1]))
1339		#define DST_MULTIPLEX__INP(addr) (*(node->input[2 + addr]))
	1337	#define DST_MULTIPLEX__ENABLE DISCRETE_INPUT(0)
	1338	#define DST_MULTIPLEX__ADDR DISCRETE_INPUT(1)
	1339	#define DST_MULTIPLEX__INP(addr) DISCRETE_INPUT(2 + addr)
1340	1340
1341	1341	static DISCRETE_STEP(dst_multiplex)
1342	1342	{
r5534	r5535
1354	1354	else
1355	1355	{
1356	1356	/* Bad address. We will leave the output alone. */
1357		discrete_log(d~~isc_~~info, "NODE_%02d - Address = %d. Out of bounds\n", node->node-NODE_00, addr);
	1357	discrete_log(node->info, "NODE_%02d - Address = %d. Out of bounds\n", node->node-NODE_00, addr);
1358	1358	}
1359	1359	}
1360	1360	else
r5534	r5535
1385	1385	*
1386	1386	* Complete re-write Jan 2004, D Renaud.
1387	1387	************************************************************************/
1388		#define DST_ONESHOT__RESET (*(node->input[0]))
1389		#define DST_ONESHOT__TRIG (*(node->input[1]))
1390		#define DST_ONESHOT__AMP (*(node->input[2]))
1391		#define DST_ONESHOT__WIDTH (*(node->input[3]))
1392		#define DST_ONESHOT__TYPE (int)(*(node->input[4]))
	1388	#define DST_ONESHOT__RESET DISCRETE_INPUT(0)
	1389	#define DST_ONESHOT__TRIG DISCRETE_INPUT(1)
	1390	#define DST_ONESHOT__AMP DISCRETE_INPUT(2)
	1391	#define DST_ONESHOT__WIDTH DISCRETE_INPUT(3)
	1392	#define DST_ONESHOT__TYPE (int)DISCRETE_INPUT(4)
1393	1393
1394	1394	static DISCRETE_STEP(dst_oneshot)
1395	1395	{
r5534	r5535
1439	1439
1440	1440	if (do_count)
1441	1441	{
1442		context->countdown -= d~~isc_~~info->sample_time;
	1442	context->countdown -= node->info->sample_time;
1443	1443	if(context->countdown <= 0.0)
1444	1444	{
1445	1445	node->output[0] = (DST_ONESHOT__TYPE & DISC_OUT_ACTIVE_LOW) ? DST_ONESHOT__AMP : 0;
r5534	r5535
1475	1475	* input[5] - Clamp value when disabled
1476	1476	*
1477	1477	************************************************************************/
1478		#define DST_RAMP__ENABLE (*(node->input[0]))
1479		#define DST_RAMP__DIR (*(node->input[1]))
1480		#define DST_RAMP__GRAD (*(node->input[2]))
1481		#define DST_RAMP__START (*(node->input[3]))
1482		#define DST_RAMP__END (*(node->input[4]))
1483		#define DST_RAMP__CLAMP (*(node->input[5]))
	1478	#define DST_RAMP__ENABLE DISCRETE_INPUT(0)
	1479	#define DST_RAMP__DIR DISCRETE_INPUT(1)
	1480	#define DST_RAMP__GRAD DISCRETE_INPUT(2)
	1481	#define DST_RAMP__START DISCRETE_INPUT(3)
	1482	#define DST_RAMP__END DISCRETE_INPUT(4)
	1483	#define DST_RAMP__CLAMP DISCRETE_INPUT(5)
1484	1484
1485	1485	static DISCRETE_STEP(dst_ramp)
1486	1486	{
r5534	r5535
1514	1514	struct dss_ramp_context context = (struct dss_ramp_context )node->context;
1515	1515
1516	1516	node->output[0] = DST_RAMP__CLAMP;
1517		context->step = DST_RAMP__GRAD / d~~isc_~~info->sample_rate;
	1517	context->step = DST_RAMP__GRAD / node->info->sample_rate;
1518	1518	context->dir = ((DST_RAMP__END - DST_RAMP__START) == abs(DST_RAMP__END - DST_RAMP__START));
1519	1519	context->last_en = 0;
1520	1520	}
r5534	r5535
1530	1530	* input[3] - clock type
1531	1531	*
1532	1532	************************************************************************/
1533		#define DST_SAMPHOLD__ENABLE (*(node->input[0]))
1534		#define DST_SAMPHOLD__IN0 (*(node->input[1]))
1535		#define DST_SAMPHOLD__CLOCK (*(node->input[2]))
1536		#define DST_SAMPHOLD__TYPE (*(node->input[3]))
	1533	#define DST_SAMPHOLD__ENABLE DISCRETE_INPUT(0)
	1534	#define DST_SAMPHOLD__IN0 DISCRETE_INPUT(1)
	1535	#define DST_SAMPHOLD__CLOCK DISCRETE_INPUT(2)
	1536	#define DST_SAMPHOLD__TYPE DISCRETE_INPUT(3)
1537	1537
1538	1538	static DISCRETE_STEP(dst_samphold)
1539	1539	{
r5534	r5535
1560	1560	if (DST_SAMPHOLD__CLOCK == 0) node->output[0] = DST_SAMPHOLD__IN0;
1561	1561	break;
1562	1562	default:
1563		discrete_log(d~~isc_~~info, "dst_samphold_step - Invalid clocktype passed");
	1563	discrete_log(node->info, "dst_samphold_step - Invalid clocktype passed");
1564	1564	break;
1565	1565	}
1566	1566	}
r5534	r5535
1594	1594	* input[3] - input[1]
1595	1595	*
1596	1596	************************************************************************/
1597		#define DSS_SWITCH__ENABLE (*(node->input[0]))
1598		#define DSS_SWITCH__SWITCH (*(node->input[1]))
1599		#define DSS_SWITCH__IN0 (*(node->input[2]))
1600		#define DSS_SWITCH__IN1 (*(node->input[3]))
	1597	#define DSS_SWITCH__ENABLE DISCRETE_INPUT(0)
	1598	#define DSS_SWITCH__SWITCH DISCRETE_INPUT(1)
	1599	#define DSS_SWITCH__IN0 DISCRETE_INPUT(2)
	1600	#define DSS_SWITCH__IN1 DISCRETE_INPUT(3)
1601	1601
1602	1602	static DISCRETE_STEP(dst_switch)
1603	1603	{
r5534	r5535
1621	1621	* input[3] - Threshold for enable
1622	1622	*
1623	1623	************************************************************************/
1624		#define DSS_ASWITCH__ENABLE (*(node->input[0]))
1625		#define DSS_ASWITCH__CTRL (*(node->input[1]))
1626		#define DSS_ASWITCH__IN (*(node->input[2]))
1627		#define DSS_ASWITCH__THRESHOLD (*(node->input[3]))
	1624	#define DSS_ASWITCH__ENABLE DISCRETE_INPUT(0)
	1625	#define DSS_ASWITCH__CTRL DISCRETE_INPUT(1)
	1626	#define DSS_ASWITCH__IN DISCRETE_INPUT(2)
	1627	#define DSS_ASWITCH__THRESHOLD DISCRETE_INPUT(3)
1628	1628
1629	1629
1630	1630	static DISCRETE_STEP(dst_aswitch)
r5534	r5535
1651	1651	* input[5] - Channel4 input value
1652	1652	*
1653	1653	************************************************************************/
1654		#define DST_TRANSFORM__IN0 (*(node->input[0]))
1655		#define DST_TRANSFORM__IN1 (*(node->input[1]))
1656		#define DST_TRANSFORM__IN2 (*(node->input[2]))
1657		#define DST_TRANSFORM__IN3 (*(node->input[3]))
1658		#define DST_TRANSFORM__IN4 (*(node->input[4]))
	1654	#define DST_TRANSFORM__IN0 DISCRETE_INPUT(0)
	1655	#define DST_TRANSFORM__IN1 DISCRETE_INPUT(1)
	1656	#define DST_TRANSFORM__IN2 DISCRETE_INPUT(2)
	1657	#define DST_TRANSFORM__IN3 DISCRETE_INPUT(3)
	1658	#define DST_TRANSFORM__IN4 DISCRETE_INPUT(4)
1659	1659
1660	1660	#define MAX_TRANS_STACK 16
1661	1661
r5534	r5535
1762	1762	top = (int)number1 ^ (int)top;
1763	1763	break;
1764	1764	default:
1765		discrete_log(d~~isc_~~info, "dst_transform_step - Invalid function type/variable passed");
	1765	discrete_log(node->info, "dst_transform_step - Invalid function type/variable passed");
1766	1766	node->output[0] = 0;
1767	1767	break;
1768	1768	}
r5534	r5535
1783	1783	*
1784	1784	* Mar 2007, D Renaud.
1785	1785	************************************************************************/
1786		#define DST_OP_AMP__ENABLE (*(node->input[0]))
1787		#define DST_OP_AMP__INP0 (*(node->input[1]))
1788		#define DST_OP_AMP__INP1 (*(node->input[2]))
	1786	#define DST_OP_AMP__ENABLE DISCRETE_INPUT(0)
	1787	#define DST_OP_AMP__INP0 DISCRETE_INPUT(1)
	1788	#define DST_OP_AMP__INP1 DISCRETE_INPUT(2)
1789	1789
1790	1790	static DISCRETE_STEP(dst_op_amp)
1791	1791	{
r5534	r5535
1869	1869	}
1870	1870	else
1871	1871	/* linear charge */
1872		context->exponent = d~~isc_~~info->sample_rate * info->c;
	1872	context->exponent = node->info->sample_rate * info->c;
1873	1873	}
1874	1874
1875		if (info->r3 >= 0)
	1875	if (info->r3 > 0)
1876	1876	context->i_fixed = (info->vP - OP_AMP_NORTON_VBE) / info->r3;
	1877	else
	1878	context->i_fixed = 0;
1877	1879	}
1878	1880
1879	1881
r5534	r5535
1887	1889	*
1888	1890	* Mar 2007, D Renaud.
1889	1891	************************************************************************/
1890		#define DST_OP_AMP_1SHT__TRIGGER (*(node->input[0]))
	1892	#define DST_OP_AMP_1SHT__TRIGGER DISCRETE_INPUT(0)
1891	1893
1892	1894	static DISCRETE_STEP(dst_op_amp_1sht)
1893	1895	{
r5534	r5535
1958	1960	*
1959	1961	* Mar 2004, D Renaud.
1960	1962	************************************************************************/
1961		#define DST_TVCA_OP_AMP__TRG0 (*(node->input[0]))
1962		#define DST_TVCA_OP_AMP__TRG1 (*(node->input[1]))
1963		#define DST_TVCA_OP_AMP__TRG2 (*(node->input[2]))
1964		#define DST_TVCA_OP_AMP__INP0 (*(node->input[3]))
1965		#define DST_TVCA_OP_AMP__INP1 (*(node->input[4]))
	1963	#define DST_TVCA_OP_AMP__TRG0 DISCRETE_INPUT(0)
	1964	#define DST_TVCA_OP_AMP__TRG1 DISCRETE_INPUT(1)
	1965	#define DST_TVCA_OP_AMP__TRG2 DISCRETE_INPUT(2)
	1966	#define DST_TVCA_OP_AMP__INP0 DISCRETE_INPUT(3)
	1967	#define DST_TVCA_OP_AMP__INP1 DISCRETE_INPUT(4)
1966	1968
1967	1969	static DISCRETE_STEP(dst_tvca_op_amp)
1968	1970	{

src/emu/sound/discrete.c
r5534	r5535
38	38	#include "inptport.h"
39	39	#include "wavwrite.h"
40	40	#include "discrete.h"
	41	#include "eminline.h"
41	42
42	43
43	44	/*************************************
r5534	r5535
57	58
58	59	#define DISCRETE_PROFILING (0)
59	60
60
61
62	61	/*************************************
63	62	*
64	63	* Prototypes
65	64	*
66	65	*************************************/
67	66
68		static void init_nodes(discrete_info info, discrete_sound_block block_list, const device_config *device);
69		static void find_input_nodes(discrete_info info, discrete_sound_block block_list);
70		static void setup_output_nodes(const device_config device, discrete_info info);
	67	static void init_nodes(discrete_info info, linked_list_entry block_list, const device_config *device);
	68	static void find_input_nodes(discrete_info *info);
71	69	static void setup_disc_logs(discrete_info *info);
72	70	static node_description discrete_find_node(const discrete_info info, int node);
73	71	static DEVICE_RESET( discrete );
	72	static STREAM_UPDATE( discrete_stream_update );
74	73
75	74
76
77	75	/*************************************
78	76	*
79	77	* Debug logging
r5534	r5535
97	95	}
98	96	}
99	97
	98	typedef struct _task_info task_info;
100	99
	100	struct _task_info
	101	{
	102	discrete_task_context *context;
	103	int samples;
	104	};
101	105
	106	INLINE void step_nodes_in_list(linked_list_entry **list)
	107	{
	108	linked_list_entry *entry;
	109	for (entry = *list; entry != NULL; entry = entry->next)
	110	{
	111	node_description node = (node_description ) entry->ptr;
	112
	113	/* Now step the node */
	114	if (DISCRETE_PROFILING)
	115	node->run_time -= osd_profiling_ticks();
	116
	117	(*node->module->step)(node);
	118	//bigselect(info->device, node);
	119
	120	if (DISCRETE_PROFILING)
	121	node->run_time += osd_profiling_ticks();
	122	}
	123	}
	124
	125	static void task_callback(void param, int threadid)
	126	{
	127	task_info ti = (task_info ) param;
	128	int samples, i;
	129
	130	/* set up task buffers */
	131	for (i = 0; i < ti->context->numbuffered; i++)
	132	ti->context->ptr[i] = &ti->context->node_buf[i][0];
	133
	134	samples = ti->samples;
	135	while (samples-- > 0)
	136	{
	137	step_nodes_in_list(&ti->context->list);
	138	}
	139	/* reset ptr */
	140	for (i = 0; i < ti->context->numbuffered; i++)
	141	ti->context->ptr[i] = &ti->context->node_buf[i][0];
	142
	143	free(param);
	144	return NULL;
	145	}
	146
	147	static DISCRETE_STEP( dso_task )
	148	{
	149	discrete_task_context ctx = (discrete_task_context ) node->context;
	150	int i;
	151
	152	for (i = 0; i < ctx->numbuffered; i++)
	153	*(ctx->ptr[i]++) = (double) DISCRETE_INPUT(i);
	154	}
	155
	156	static DISCRETE_RESET( dso_task )
	157	{
	158	/* nothing to do - just avoid being stepped */
	159	}
	160
	161	static DISCRETE_STEP( dso_output )
	162	{
	163	stream_sample_t output = (stream_sample_t ) &node->context;
	164	double val;
	165
	166	/* Add gain to the output and put into the buffers */
	167	/* Clipping will be handled by the main sound system */
	168	val = DISCRETE_INPUT(0) * DISCRETE_INPUT(1);
	169	**output = val;
	170	(*output)++;
	171	}
	172
	173	static DISCRETE_RESET( dso_output )
	174	{
	175	/* nothing to do - just avoid being stepped */
	176	}
	177
	178
102	179	/*************************************
103	180	*
	181	* Add an entry to a list
	182	*
	183	*************************************/
	184
	185	static void linked_list_add(discrete_info info, linked_list_entry *list_tail_ptr, void ptr)
	186	{
	187	**list_tail_ptr = auto_alloc(info->device->machine, linked_list_entry);
	188	(**list_tail_ptr)->ptr = ptr;
	189	(**list_tail_ptr)->next = NULL;
	190	list_tail_ptr = &((*list_tail_ptr)->next);
	191	}
	192
	193	/*************************************
	194	*
	195	* Count entries in a list
	196	*
	197	*************************************/
	198
	199	static int linked_list_count(linked_list_entry *list)
	200	{
	201	int cnt = 0;
	202	linked_list_entry *entry;
	203
	204	for (entry = list; entry != NULL; entry = entry->next)
	205	cnt++;
	206
	207	return cnt;
	208	}
	209
	210
	211	/*************************************
	212	*
104	213	* Included simulation objects
105	214	*
106	215	*************************************/
r5534	r5535
121	230
122	231	static const discrete_module module_list[] =
123	232	{
124		{ DSO_OUTPUT ,"DSO_OUTPUT" , 0 ,0 ,~~NULL~~ ,~~NULL~~ },
	233	{ DSO_OUTPUT ,"DSO_OUTPUT" , 0 ,0 ,dso_output_reset ,dso_output_step },
125	234	{ DSO_CSVLOG ,"DSO_CSVLOG" , 0 ,0 ,NULL ,NULL },
126	235	{ DSO_WAVELOG ,"DSO_WAVELOG" , 0 ,0 ,NULL ,NULL },
127	236	{ DSO_IMPORT ,"DSO_IMPORT" , 0 ,0 ,NULL ,NULL },
128	237
	238	/* parallel modules */
	239	{ DSO_TASK_START ,"DSO_TASK_START" , 0 ,0 ,NULL ,NULL },
	240	{ DSO_TASK_END ,"DSO_TASK_END" , 0 ,0 ,dso_task_reset ,dso_task_step },
	241	{ DSO_TASK_SYNC ,"DSO_TASK_SYNC" , 0 ,0 ,NULL ,NULL },
	242
129	243	/* nop */
130		{ DSS_NOP ,"DSS_NOP" , 0 ,0 ,NULL ,NULL },
	244	{ DSS_NOP ,"DSS_NOP" , 0 ,0 ,NULL ,NULL },
131	245
132	246	/* from disc_inp.c */
133	247	{ DSS_ADJUSTMENT ,"DSS_ADJUSTMENT" , 1 ,sizeof(struct dss_adjustment_context) ,dss_adjustment_reset ,dss_adjustment_step },
134	248	{ DSS_CONSTANT ,"DSS_CONSTANT" , 1 ,0 ,dss_constant_reset ,NULL },
135		{ DSS_INPUT_DATA ,"DSS_INPUT_DATA" , 1 ,sizeof(UINT8) ,dss_input_reset ,NULL },
136		{ DSS_INPUT_LOGIC ,"DSS_INPUT_LOGIC" , 1 ,sizeof(UINT8) ,dss_input_reset ,NULL },
137		{ DSS_INPUT_NOT ,"DSS_INPUT_NOT" , 1 ,sizeof(UINT8) ,dss_input_reset ,NULL },
138		{ DSS_INPUT_PULSE ,"DSS_INPUT_PULSE" , 1 ,sizeof(UINT8) ,dss_input_reset ,dss_input_pulse_step },
139		{ DSS_INPUT_STREAM,"DSS_INPUT_STREAM", 1 ,0 ,dss_input_stream_reset,dss_input_stream_step},
	249	{ DSS_INPUT_DATA ,"DSS_INPUT_DATA" , 1 ,sizeof(struct dss_input_context) ,dss_input_reset ,NULL },
	250	{ DSS_INPUT_LOGIC ,"DSS_INPUT_LOGIC" , 1 ,sizeof(struct dss_input_context) ,dss_input_reset ,NULL },
	251	{ DSS_INPUT_NOT ,"DSS_INPUT_NOT" , 1 ,sizeof(struct dss_input_context) ,dss_input_reset ,NULL },
	252	{ DSS_INPUT_PULSE ,"DSS_INPUT_PULSE" , 1 ,sizeof(struct dss_input_context) ,dss_input_reset ,dss_input_pulse_step },
	253	{ DSS_INPUT_STREAM,"DSS_INPUT_STREAM", 1 ,sizeof(struct dss_input_context) ,dss_input_stream_reset,dss_input_stream_step},
140	254
141	255	/* from disc_wav.c */
142	256	/* Generic modules */
143	257	{ DSS_COUNTER ,"DSS_COUNTER" , 1 ,sizeof(struct dss_counter_context) ,dss_counter_reset ,dss_counter_step },
144		{ DSS_LFSR_NOISE ,"DSS_LFSR_NOISE" , 1 ,sizeof(struct dss_lfsr_context) ,dss_lfsr_reset ,dss_lfsr_step },
	258	{ DSS_LFSR_NOISE ,"DSS_LFSR_NOISE" , 2 ,sizeof(struct dss_lfsr_context) ,dss_lfsr_reset ,dss_lfsr_step },
145	259	{ DSS_NOISE ,"DSS_NOISE" , 1 ,sizeof(struct dss_noise_context) ,dss_noise_reset ,dss_noise_step },
146	260	{ DSS_NOTE ,"DSS_NOTE" , 1 ,sizeof(struct dss_note_context) ,dss_note_reset ,dss_note_step },
147	261	{ DSS_SAWTOOTHWAVE,"DSS_SAWTOOTHWAVE", 1 ,sizeof(struct dss_sawtoothwave_context),dss_sawtoothwave_reset,dss_sawtoothwave_step},
r5534	r5535
229	343	{ DSS_NULL ,"DSS_NULL" , 0 ,0 ,NULL ,NULL }
230	344	};
231	345
232
233
234	346	/*************************************
235	347	*
236	348	* Find a given node
r5534	r5535
249	361	*
250	362	*************************************/
251	363
252		static int discrete_build_list(discrete_info info, discrete_sound_block intf, di~~screte_sou~~nd_bl~~ock *out,~~ int ~~offs~~et)
	364	static void discrete_build_list(discrete_info info, discrete_sound_block intf, linked_list_entry ***current)
253	365	{
254	366	int node_count = 0;
255	367
r5534	r5535
258	370	/* scan imported */
259	371	if (intf[node_count].type == DSO_IMPORT)
260	372	{
261		offset = discrete_build_list(info, (discrete_sound_block *) intf[node_count].custom, out, offset);
	373	discrete_log(info, "discrete_build_list() - DISCRETE_IMPORT @ NODE_%02d", NODE_INDEX(intf[node_count].node) );
	374	discrete_build_list(info, (discrete_sound_block *) intf[node_count].custom, current);
262	375	}
263	376	else if (intf[node_count].type == DSO_REPLACE)
264	377	{
265		int i;
	378	linked_list_entry *entry;
266	379
267	380	node_count++;
268	381	if (intf[node_count].type == DSS_NULL)
269	382	fatalerror("discrete_build_list: DISCRETE_REPLACE at end of node_list");
270	383
271		for (i = 0; i < offset; i++)
272		if (out[i].type != NODE_SPECIAL )
273		if (out[i].node == intf[node_count].node)
	384	for (entry = info->block_list; entry != NULL; entry = entry->next)
	385	{
	386	discrete_sound_block block = (discrete_sound_block ) entry->ptr;
	387
	388	if (block->type != NODE_SPECIAL )
	389	if (block->node == intf[node_count].node)
274	390	{
275		out[i] = intf[node_count];
	391	entry->ptr = (void *) &intf[node_count];
	392	discrete_log(info, "discrete_build_list() - DISCRETE_REPLACE @ NODE_%02d", NODE_INDEX(intf[node_count].node) );
276	393	break;
277	394	}
	395	}
278	396
279		if (i >= ~~offset~~)
	397	if (entry == NULL)
280	398	fatalerror("discrete_build_list: DISCRETE_REPLACE did not found node %d", NODE_INDEX(intf[node_count].node));
281	399
282	400	}
283	401	else if (intf[node_count].type == DSO_DELETE)
284	402	{
285		in~~t i,p,d~~eleted;
	403	linked_list_entry entry, last;
286	404
287		p = 0;
288		deleted = 0;
289		for (i = 0; i < offset; i++)
	405	last = NULL;
	406	for (entry = info->block_list; entry != NULL; last = entry, entry = entry->next)
290	407	{
291		if ((out[i].node >= intf[node_count].input_node[0]) &&
292		(out[i].node <= intf[node_count].input_node[1]))
	408	discrete_sound_block block = (discrete_sound_block ) entry->ptr;
	409
	410	if ((block->node >= intf[node_count].input_node[0]) &&
	411	(block->node <= intf[node_count].input_node[1]))
293	412	{
294		discrete_log(info, "discrete_build_list() - DISCRETE_DELETE deleted NODE_%02d", NODE_INDEX(out[i].node) );
295		deleted++;
	413	discrete_log(info, "discrete_build_list() - DISCRETE_DELETE deleted NODE_%02d", NODE_INDEX(block->node) );
	414	if (last != NULL)
	415	last->next = entry->next;
	416	else
	417	info->block_list = entry->next;
296	418	}
297		else
298		{
299		out[p++] = out[i];
300		}
301	419	}
302		offset -= deleted;
303	420	}
304	421	else
305		out[offset++] = intf[node_count];
	422	{
	423	discrete_log(info, "discrete_build_list() - adding node %d (current %p)\n", node_count, current);
	424	linked_list_add(info, current, &intf[node_count]);
	425	}
306	426
307	427	node_count++;
308	428	}
309		out[offset] = intf[node_count];
310		return offset;
311	429	}
312	430
313	431	/*************************************
314	432	*
	433	* Sanity check list
	434	*
	435	*************************************/
	436
	437	static void discrete_sanity_check(discrete_info *info)
	438	{
	439	linked_list_entry *entry;
	440	int node_count = 0;
	441
	442	discrete_log(info, "discrete_start() - Doing node list sanity check");
	443	for (entry = info->block_list; entry != NULL; entry = entry->next)
	444	{
	445	discrete_sound_block block = (discrete_sound_block ) entry->ptr;
	446
	447	/* make sure we don't have too many nodes overall */
	448	if (node_count > DISCRETE_MAX_NODES)
	449	fatalerror("discrete_start() - Upper limit of %d nodes exceeded, have you terminated the interface block?", DISCRETE_MAX_NODES);
	450
	451	/* make sure the node number is in range */
	452	if (block->node < NODE_START \|\| block->node > NODE_END)
	453	fatalerror("discrete_start() - Invalid node number on node %02d descriptor", block->node);
	454
	455	/* make sure the node type is valid */
	456	if (block->type > DSO_OUTPUT)
	457	fatalerror("discrete_start() - Invalid function type on NODE_%02d", NODE_INDEX(block->node) );
	458
	459	/* make sure this is a main node */
	460	if (NODE_CHILD_NODE_NUM(block->node) > 0)
	461	fatalerror("discrete_start() - Child node number on NODE_%02d", NODE_INDEX(block->node) );
	462
	463	node_count++;
	464	}
	465	discrete_log(info, "discrete_start() - Sanity check counted %d nodes", node_count);
	466
	467	}
	468
	469	/*************************************
	470	*
315	471	* Master discrete system start
316	472	*
317	473	*************************************/
318	474
319	475	static DEVICE_START( discrete )
320	476	{
321		dis~~cre~~te_~~sou~~n~~d_block~~ *intf;
	477	linked_list_entry **intf;
322	478	discrete_sound_block intf_start = (discrete_sound_block )device->static_config;
323	479	discrete_info *info = get_safe_token(device);
324	480	char name[32];
r5534	r5535
337	493
338	494	/* create the logfile */
339	495	sprintf(name, "discrete%s.log", device->tag);
340		if (DISCRETE_DEBUGLOG ~~&& !info->disclogfile~~)
	496	if (DISCRETE_DEBUGLOG)
341	497	info->disclogfile = fopen(name, "w");
342	498
343	499	/* Build the final block list */
344		intf = auto_alloc_array_clear(device->machine, discrete_sound_block, DISCRETE_MAX_NODES);
345		discrete_build_list(info, intf_start, intf, 0);
	500	info->block_list = NULL;
	501	intf = &info->block_list;
	502	discrete_build_list(info, intf_start, &intf);
346	503
347	504	/* first pass through the nodes: sanity check, fill in the indexed_nodes, and make a total count */
348		discrete_log(info, "discrete_start() - Doing node list sanity check");
349		for (info->node_count = 0; intf[info->node_count].type != DSS_NULL; info->node_count++)
350		{
351		/* make sure we don't have too many nodes overall */
352		if (info->node_count > DISCRETE_MAX_NODES)
353		fatalerror("discrete_start() - Upper limit of %d nodes exceeded, have you terminated the interface block?", DISCRETE_MAX_NODES);
	505	discrete_sanity_check(info);
354	506
355		/* make sure the node number is in range */
356		if (intf[info->node_count].node < NODE_START \|\| intf[info->node_count].node > NODE_END)
357		fatalerror("discrete_start() - Invalid node number on node %02d descriptor", info->node_count);
	507	/* Start with empty lists */
	508	info->node_list = NULL;
	509	info->step_list = NULL;
	510	info->output_list = NULL;
	511	info->input_list = NULL;
358	512
359		/* make sure the node type is valid */
360		if (intf[info->node_count].type > DSO_OUTPUT)
361		fatalerror("discrete_start() - Invalid function type on NODE_%02d", NODE_INDEX(intf[info->node_count].node) );
362
363		/* make sure this is a main node */
364		if (NODE_CHILD_NODE_NUM(intf[info->node_count].node) > 0)
365		fatalerror("discrete_start() - Child node number on NODE_%02d", NODE_INDEX(intf[info->node_count].node) );
366		}
367		info->node_count++;
368		discrete_log(info, "discrete_start() - Sanity check counted %d nodes", info->node_count);
369
370		/* allocate memory for the array of actual nodes */
371		info->node_list = auto_alloc_array_clear(device->machine, node_description, info->node_count);
372
373		/* allocate memory for the node execution order array */
374		info->running_order = auto_alloc_array_clear(device->machine, node_description *, info->node_count);
375
376	513	/* allocate memory to hold pointers to nodes by index */
377	514	info->indexed_node = auto_alloc_array_clear(device->machine, node_description *, DISCRETE_MAX_NODES);
378	515
379	516	/* initialize the node data */
380		init_nodes(info, intf, device);
	517	init_nodes(info, info->block_list, device);
381	518
382	519	/* now go back and find pointers to all input nodes */
383		find_input_nodes(info~~, intf~~);
	520	find_input_nodes(info);
384	521
385	522	/* then set up the output nodes */
386		setup_output_nodes(device, info);
	523	/* initialize the stream(s) */
	524	info->discrete_stream = stream_create(device,linked_list_count(info->input_list), linked_list_count(info->output_list), info->sample_rate, info, discrete_stream_update);
387	525
	526	/* allocate a queue */
	527
	528	info->queue = osd_work_queue_alloc(WORK_QUEUE_FLAG_MULTI \| WORK_QUEUE_FLAG_HIGH_FREQ);
	529
388	530	setup_disc_logs(info);
389	531	}
390	532
r5534	r5535
401	543	discrete_info *info = get_safe_token(device);
402	544	int log_num;
403	545
	546	osd_work_queue_free(info->queue);
	547
404	548	if (DISCRETE_PROFILING)
405	549	{
406		int nodenum;
	550	int count = 0;
	551	linked_list_entry *entry;
407	552	osd_ticks_t total = 0;
408	553	osd_ticks_t tresh;
409	554
410		printf("Total Samples: %d\n", info->total_samples);
411	555	/* calculate total time */
412		for (~~nod~~enum = ~~0; nodenum <~~ info->~~nod~~e_~~cou~~nt; noden~~um++~~)
	556	for (entry = info->step_list; entry != NULL; entry = entry->next)
413	557	{
414		node_description *node = info~~->running~~_order[noden~~um]~~;
	558	node_description node = (node_description ) entry->ptr;
415	559
416	560	/* Now step the node */
417	561	total += node->run_time;
	562	count++;
418	563	}
419	564	/* print statistics */
420		tresh = total / info->node_count;
421		for (nodenum = 0; nodenum < info->node_count; nodenum++)
	565	printf("Total Samples: %d\n", info->total_samples);
	566	tresh = total / count;
	567	for (entry = info->step_list; entry != NULL; entry = entry->next)
422	568	{
423		node_description *node = info~~->running~~_order[noden~~um]~~;
	569	node_description node = (node_description ) entry->ptr;
424	570
425	571	if (node->run_time > tresh)
426		printf("%3d: %20s %8.2f %10d\n", NODE_INDEX(node->node), node->module.name, (float) node->run_time / (float) total * 100.0, ((int) node->run_time) / info->total_samples);
	572	printf("%3d: %20s %8.2f %10d\n", NODE_INDEX(node->node), node->module->name, (float) node->run_time / (float) total * 100.0, ((int) node->run_time) / info->total_samples);
427	573	}
428	574	}
429	575
r5534	r5535
457	603	static DEVICE_RESET( discrete )
458	604	{
459	605	discrete_info *info = get_safe_token(device);
460		int nodenum;
	606	linked_list_entry *entry;
461	607
462	608	/* loop over all nodes */
463		for (~~nod~~enum = ~~0; nodenum <~~ info->node_~~cou~~nt; noden~~um++~~)
	609	for (entry = info->node_list; entry != 0; entry = entry->next)
464	610	{
465		node_description *node = info~~->running~~_order[noden~~um]~~;
	611	node_description node = (node_description ) entry->ptr;
466	612
467	613	node->output[0] = 0;
468	614
469	615	/* if the node has a reset function, call it */
470		if (node->module.reset)
471		(*node->module.reset)(info, node);
	616	if (node->module->reset)
	617	(*node->module->reset)(node);
472	618
473	619	/* otherwise, just step it */
474		else if (node->module.step)
475		(*node->module.step)(info, node);
	620	else if (node->module->step)
	621	(*node->module->step)(node);
476	622	}
477	623	}
478	624
r5534	r5535
562	708	*
563	709	*************************************/
564	710
565		~~static STR~~E~~AM_UPDATE(~~ discrete_stream_update )
	711	INLINE void discrete_stream_update_csv(discrete_info *info)
566	712	{
567		discrete_info info = (discrete_info )param;
568		int samplenum, nodenum, outputnum;
	713	int nodenum, outputnum;
	714
	715	/* Dump any csv logs */
	716	for (outputnum = 0; outputnum < info->num_csvlogs; outputnum++)
	717	{
	718	fprintf(info->disc_csv_file[outputnum], "%" I64FMT "d", ++info->sample_num);
	719	for (nodenum = 0; nodenum < info->csvlog_node[outputnum]->active_inputs; nodenum++)
	720	{
	721	fprintf(info->disc_csv_file[outputnum], ", %f", *info->csvlog_node[outputnum]->input[nodenum]);
	722	}
	723	fprintf(info->disc_csv_file[outputnum], "\n");
	724	}
	725	}
	726
	727	INLINE void discrete_stream_update_wave(discrete_info *info)
	728	{
	729	int outputnum;
569	730	double val;
570	731	INT16 wave_data_l, wave_data_r;
571	732
572		/* Setup any input streams */
573		for (nodenum = 0; nodenum < info->discrete_input_streams; nodenum++)
	733	/* Dump any wave logs */
	734	for (outputnum = 0; outputnum < info->num_wavelogs; outputnum++)
574	735	{
575		info->input_stream_data[nodenum] = inputs[nodenum];
	736	/* get nodes to be logged and apply gain, then clip to 16 bit */
	737	val = (info->wavelog_node[outputnum]->input[0]) (*info->wavelog_node[outputnum]->input[1]);
	738	val = (val < -32768) ? -32768 : (val > 32767) ? 32767 : val;
	739	wave_data_l = (INT16)val;
	740	if (info->wavelog_node[outputnum]->active_inputs == 2)
	741	{
	742	/* DISCRETE_WAVELOG1 */
	743	wav_add_data_16(info->disc_wav_file[outputnum], &wave_data_l, 1);
	744	}
	745	else
	746	{
	747	/* DISCRETE_WAVELOG2 */
	748	val = (info->wavelog_node[outputnum]->input[2]) (*info->wavelog_node[outputnum]->input[3]);
	749	val = (val < -32768) ? -32768 : (val > 32767) ? 32767 : val;
	750	wave_data_r = (INT16)val;
	751
	752	wav_add_data_16lr(info->disc_wav_file[outputnum], &wave_data_l, &wave_data_r, 1);
	753	}
576	754	}
	755	}
577	756
578		/* Now we must do samples iterations of the node list, one output for each step */
579		for (samplenum = 0; samplenum < samples; samplenum++)
580		{
	757	INLINE void discrete_stream_update_nodes(discrete_info *info)
	758	{
	759	linked_list_entry *entry;
	760
	761	if (DISCRETE_PROFILING)
581	762	info->total_samples++;
582		/* loop over all nodes */
583		for (nodenum = 0; nodenum < info->node_count; nodenum++)
584		{
585		node_description *node = info->running_order[nodenum];
586	763
587		/* Now step the node */
588		if (DISCRETE_PROFILING)
589		node->run_time -= osd_profiling_ticks();
	764	/* update task nodes */
	765	for (entry = info->task_list; entry != 0; entry = entry->next)
	766	{
	767	discrete_task_context task = (discrete_task_context ) entry->ptr;
	768	int i;
	769
	770	for (i = 0; i < task->numbuffered; i++)
	771	*task->dest[i] = task->ptr[i]++;
	772	}
590	773
591		if (node->module.step)
592		(*node->module.step)(info, node);
593		//bigselect(info->device, node);
	774	/* loop over all nodes */
	775	step_nodes_in_list(&info->step_list);
	776	}
594	777
595		if (DISCRETE_PROFILING)
596		node->run_time += osd_profiling_ticks();
	778	static STREAM_UPDATE( discrete_stream_update )
	779	{
	780	discrete_info info = (discrete_info )param;
	781	linked_list_entry *entry;
	782	int samplenum, outputnum;
597	783
598		}
	784	if (samples == 0)
	785	return;
599	786
600		/* Add gain to the output and put into the buffers */
601		/* Clipping will be handled by the main sound system */
602		for (outputnum = 0; outputnum < info->discrete_outputs; outputnum++)
603		{
604		val = (info->output_node[outputnum]->input[0]) (*info->output_node[outputnum]->input[1]);
605		outputs[outputnum][samplenum] = val;
606		}
	787	/* Setup any output streams */
	788	for (entry = info->output_list, outputnum = 0; entry != NULL; entry = entry->next, outputnum++)
	789	{
	790	((node_description ) entry->ptr)->context = (void ) outputs[outputnum];
	791	}
607	792
608		/* Dump any csv logs */
609		for (outputnum = 0; outputnum < info->num_csvlogs; outputnum++)
610		{
611		fprintf(info->disc_csv_file[outputnum], "%" I64FMT "d", ++info->sample_num);
612		for (nodenum = 0; nodenum < info->csvlog_node[outputnum]->active_inputs; nodenum++)
613		{
614		fprintf(info->disc_csv_file[outputnum], ", %f", *info->csvlog_node[outputnum]->input[nodenum]);
615		}
616		fprintf(info->disc_csv_file[outputnum], "\n");
617		}
	793	/* Setup any input streams */
	794	for (entry = info->input_list; entry != NULL; entry = entry->next)
	795	{
	796	struct dss_input_context context = (struct dss_input_context ) ((node_description *) entry->ptr)->context;
	797	context->ptr = (void *) inputs[context->stream_in_number];
	798	}
618	799
619		/* Dump any wave logs */
620		for (outputnum = 0; outputnum < info->num_wavelogs; outputnum++)
621		{
622		/* get nodes to be logged and apply gain, then clip to 16 bit */
623		val = (info->wavelog_node[outputnum]->input[0]) (*info->wavelog_node[outputnum]->input[1]);
624		val = (val < -32768) ? -32768 : (val > 32767) ? 32767 : val;
625		wave_data_l = (INT16)val;
626		if (info->wavelog_node[outputnum]->active_inputs == 2)
627		{
628		/* DISCRETE_WAVELOG1 */
629		wav_add_data_16(info->disc_wav_file[outputnum], &wave_data_l, 1);
630		}
631		else
632		{
633		/* DISCRETE_WAVELOG2 */
634		val = (info->wavelog_node[outputnum]->input[2]) (*info->wavelog_node[outputnum]->input[3]);
635		val = (val < -32768) ? -32768 : (val > 32767) ? 32767 : val;
636		wave_data_r = (INT16)val;
	800	for (entry = info->task_list; entry != 0; entry = entry->next)
	801	{
	802	task_info *ti = malloc(sizeof(task_info));
	803	discrete_task_context task = (discrete_task_context ) entry->ptr;
637	804
638		wav_add_data_16lr(info->disc_wav_file[outputnum], &wave_data_l, &wave_data_r, 1);
639		}
640		}
	805	/* Fire task */
	806	ti->context = task;
	807	ti->samples = samples;
	808	osd_work_item_queue(info->queue, task_callback, (void *) ti, WORK_ITEM_FLAG_AUTO_RELEASE);
	809	}
641	810
642		/* advance input streams */
643		for (nodenum = 0; nodenum < info->discrete_input_streams; nodenum++)
	811	/* and wait for them */
	812	osd_work_queue_wait(info->queue, osd_ticks_per_second()*10);
	813
	814	if ((info->num_csvlogs == 0) && (info->num_wavelogs == 0))
	815	{
	816	/* Now we must do samples iterations of the node list, one output for each step */
	817	for (samplenum = 0; samplenum < samples; samplenum++)
	818	discrete_stream_update_nodes(info);
	819	}
	820	else
	821	{
	822	/* Now we must do samples iterations of the node list, one output for each step */
	823	for (samplenum = 0; samplenum < samples; samplenum++)
644	824	{
645		info->input_stream_data[nodenum]++;
	825	discrete_stream_update_nodes(info);
	826	discrete_stream_update_csv(info);
	827	discrete_stream_update_wave(info);
	828
646	829	}
647	830	}
648	831
r5534	r5535
656	839	*
657	840	*************************************/
658	841
659		static void init_nodes(discrete_info info, discrete_sound_block block_list, const device_config *device)
	842
	843	static void init_nodes(discrete_info info, linked_list_entry block_list, const device_config *device)
660	844	{
661		int nodenum;
	845	linked_list_entry **cur_task_node = NULL;
	846	linked_list_entry *entry;
	847	discrete_task_context *task = NULL;
	848	/* list tail pointers */
	849	linked_list_entry **step_list = &info->step_list;
	850	linked_list_entry **node_list = &info->node_list;
	851	linked_list_entry **task_list = &info->task_list;
	852	linked_list_entry **output_list = &info->output_list;
	853	linked_list_entry **input_list = &info->input_list;
662	854
663		/* start with no outputs or input streams */
664		info->discrete_outputs = 0;
665		info->discrete_input_streams = 0;
666
667	855	/* loop over all nodes */
668		for (nodenum = 0; ~~nod~~enum < info->node~~_coun~~t~~; nodenum++~~)
	856	for (entry = block_list; entry != NULL; entry = entry->next)
669	857	{
670		discrete_sound_block *block = &block_list[nodenum];
671		node_description *node = &info->node_list[nodenum];
	858	discrete_sound_block block = (discrete_sound_block ) entry->ptr;
	859	node_description *node = auto_alloc_clear(info->device->machine, node_description);
672	860	int inputnum, modulenum;
673	861
674		/* our running order just follows the order specified */
675		info->running_order[nodenum] = node;
	862	/* find the requested module */
	863	for (modulenum = 0; module_list[modulenum].type != DSS_NULL; modulenum++)
	864	if (module_list[modulenum].type == block->type)
	865	break;
	866	if (module_list[modulenum].type != block->type)
	867	fatalerror("init_nodes() - Unable to find discrete module type %d for NODE_%02d", block->type, NODE_INDEX(block->node));
676	868
	869	/* static inits */
	870	node->context = NULL;
	871	node->info = info;
	872	node->node = block->node;
	873	node->module = &module_list[modulenum];
	874	node->output[0] = 0.0;
	875	node->block = block;
	876	node->custom = block->custom;
	877	node->active_inputs = block->active_inputs;
	878
677	879	/* keep track of special nodes */
678	880	if (block->node == NODE_SPECIAL)
679	881	{
r5534	r5535
681	883	{
682	884	/* Output Node */
683	885	case DSO_OUTPUT:
684		if (info->discrete_outputs == DISCRETE_MAX_OUTPUTS)
685		fatalerror("init_nodes() - There can not be more then %d output nodes", DISCRETE_MAX_OUTPUTS);
686		info->output_node[info->discrete_outputs++] = node;
	886	linked_list_add(info, &output_list, node);
687	887	break;
688	888
689	889	/* CSVlog Node for debugging */
r5534	r5535
700	900	info->wavelog_node[info->num_wavelogs++] = node;
701	901	break;
702	902
	903	/* Task processing */
	904	case DSO_TASK_START:
	905	if (cur_task_node != NULL)
	906	fatalerror("init_nodes() - Nested DISCRETE_START_TASK.");
	907	task = auto_alloc_clear(info->device->machine, discrete_task_context);
	908	linked_list_add(info, &task_list, task);
	909	cur_task_node = &task->list;
	910	break;
	911
	912	case DSO_TASK_END:
	913	if (cur_task_node == NULL)
	914	fatalerror("init_nodes() - NO DISCRETE_START_TASK.");
	915	task->numbuffered = node->active_inputs;
	916	{
	917	int i;
	918	for (i = 0; i < task->numbuffered; i++)
	919	task->dest[i] = (double **) &node->input[i];
	920	}
	921	node->context = task;
	922	task = NULL;
	923	break;
	924
703	925	default:
704	926	fatalerror("init_nodes() - Failed, trying to create unknown special discrete node.");
705	927	}
r5534	r5535
713	935	info->indexed_node[NODE_INDEX(block->node)] = node;
714	936	}
715	937
716		/* find the requested module */
717		for (modulenum = 0; module_list[modulenum].type != DSS_NULL; modulenum++)
718		if (module_list[modulenum].type == block->type)
719		break;
720		if (module_list[modulenum].type != block->type)
721		fatalerror("init_nodes() - Unable to find discrete module type %d for NODE_%02d", block->type, NODE_INDEX(block->node));
722
723		/* static inits */
724		node->node = block->node;
725		node->module = module_list[modulenum];
726		node->output[0] = 0.0;
727		node->block = block;
728
729		node->active_inputs = block->active_inputs;
730	938	for (inputnum = 0; inputnum < DISCRETE_MAX_INPUTS; inputnum++)
731	939	{
732	940	node->input[inputnum] = &(block->initial[inputnum]);
733	941	}
734	942
735		node->context = NULL;
736		node->name = block->name;
737		node->custom = block->custom;
738
739	943	/* setup module if custom */
740	944	if (block->type == DST_CUSTOM)
741	945	{
742	946	const discrete_custom_info custom = (const discrete_custom_info )node->custom;
743		node->module.reset = custom->reset;
744		node->module.step = custom->step;
745		node->module.contextsize = custom->contextsize;
	947	node->module = &custom->module;
746	948	node->custom = custom->custom;
747	949	}
748	950
749	951	/* allocate memory if necessary */
750		if (node->module.contextsize)
751		node->context = auto_alloc_array_clear(device->machine, UINT8, node->module.contextsize);
	952	if (node->module->contextsize)
	953	node->context = auto_alloc_array_clear(device->machine, UINT8, node->module->contextsize);
752	954
753	955	/* if we are an stream input node, track that */
754	956	if (block->type == DSS_INPUT_STREAM)
755	957	{
756		if (info->discrete_input_streams == DISCRETE_MAX_OUTPUTS)
757		fatalerror("init_nodes() - There can not be more then %d input stream nodes", DISCRETE_MAX_OUTPUTS);
758		/* we will use the node's context pointer to point to the input stream data */
759		//node->context = &info->input_stream_data[info->discrete_input_streams++];
760		node->context = NULL;
761		info->discrete_input_streams++;
	958	linked_list_add(info, &input_list, node);
762	959	}
763	960
	961	/* add to node list */
	962	linked_list_add(info, &node_list, node);
	963
	964	/* our running order just follows the order specified */
	965	/* does the node step ? */
	966	if (node->module->step != NULL)
	967	{
	968	/* do we belong to a task? */
	969	if (cur_task_node == NULL)
	970	linked_list_add(info, &step_list, node);
	971	else
	972	linked_list_add(info, &cur_task_node, node);
	973	}
	974
	975	if (block->type == DSO_TASK_END)
	976	{
	977	cur_task_node = NULL;
	978	}
	979
764	980	/* and register save state */
765		state_save_register_device_item_array(device, nodenum, node->output);
	981	if (node->node != NODE_SPECIAL)
	982	state_save_register_device_item_array(device, node->node, node->output);
766	983	}
767	984
768	985	/* if no outputs, give an error */
769		if (in~~fo->~~dis~~cre~~te_outputs == 0)
	986	if (linked_list_count(info->output_list) == 0)
770	987	fatalerror("init_nodes() - Couldn't find an output node");
771	988	}
772	989
r5534	r5535
778	995	*
779	996	*************************************/
780	997
781		static void find_input_nodes(discrete_info info~~, discrete_sound_block block_list~~)
	998	static void find_input_nodes(discrete_info *info)
782	999	{
783		int nodenum, inputnum;
	1000	int inputnum;
	1001	linked_list_entry *entry;
784	1002
785	1003	/* loop over all nodes */
786		for (~~nod~~enum = ~~0; nodenum <~~ info->node_~~cou~~nt; noden~~um++~~)
	1004	for (entry = info->node_list; entry != NULL; entry = entry->next)
787	1005	{
788		node_description *node = &info->node_list[nodenum];
789		discrete_sound_block *block = &block_list[nodenum];
	1006	node_description node = (node_description ) entry->ptr;
	1007	const discrete_sound_block *block = node->block;
790	1008
791	1009	/* loop over all active inputs */
792	1010	for (inputnum = 0; inputnum < node->active_inputs; inputnum++)
r5534	r5535
800	1018	if (!node_ref)
801	1019	fatalerror("discrete_start - NODE_%02d referenced a non existent node NODE_%02d", NODE_INDEX(node->node), NODE_INDEX(inputnode));
802	1020
803		if (NODE_CHILD_NODE_NUM(inputnode) >= node_ref->module.num_output)
	1021	if (NODE_CHILD_NODE_NUM(inputnode) >= node_ref->module->num_output)
804	1022	fatalerror("discrete_start - NODE_%02d referenced non existent output %d on node NODE_%02d", NODE_INDEX(node->node), NODE_CHILD_NODE_NUM(inputnode), NODE_INDEX(inputnode));
805	1023
806	1024	node->input[inputnum] = &(node_ref->output[NODE_CHILD_NODE_NUM(inputnode)]); /* Link referenced node out to input */
r5534	r5535
821	1039	}
822	1040
823	1041
824
825	1042	/*************************************
826	1043	*
827		* Set up the output nodes
828		*
829		*************************************/
830
831		static void setup_output_nodes(const device_config device, discrete_info info)
832		{
833		/* initialize the stream(s) */
834		info->discrete_stream = stream_create(device, info->discrete_input_streams, info->discrete_outputs, info->sample_rate, info, discrete_stream_update);
835		}
836
837
838
839		/*************************************
840		*
841	1044	* Set up the logs
842	1045	*
843	1046	*************************************/

src/emu/sound/discrete.h
r5534	r5535
287	287	* DISCRETE_OP_AMP_FILTER(NODE,ENAB,INP0,INP1,TYPE,INFO)
288	288	* DISCRETE_RCDISC(NODE,ENAB,IN0,RVAL,CVAL)
289	289	* DISCRETE_RCDISC2(NODE,SWITCH,INP0,RVAL0,INP1,RVAL1,CVAL)
290		* DISCRETE_RCDISC3(NODE,ENAB,INP0,RVAL0,RVAL1,CVAL)
	290	* DISCRETE_RCDISC3(NODE,ENAB,INP0,RVAL0,RVAL1,CVAL, DJV)
291	291	* DISCRETE_RCDISC4(NODE,ENAB,INP0,RVAL0,RVAL1,RVAL2,CVAL,VP,TYPE)
292	292	* DISCRETE_RCDISC5(NODE,ENAB,IN0,RVAL,CVAL)
293	293	* DISCRETE_RCINTEGRATE(NODE,INP0,RVAL0,RVAL1,RVAL2,CVAL,vP,TYPE)
r5534	r5535
438	438	* Note: The discrete system is floating point based. So when routing a stream
439	439	* set it's gain to 100% and then use DISCRETE_INPUTX_STREAM to adjust
440	440	* it if needed.
	441	* If you need to access a stream from a discrete task, the stream node
	442	* must be part of that task. If a given stream is used in two tasks or
	443	* a task and the main task, you must declare two stream nodes acccessing the
	444	* same stream input NUM.
441	445	*
442		* EXAMPLES: see
	446	* EXAMPLES: see scramble, frogger
443	447	*
444	448	***********************************************************************
445	449	=======================================================================
r5534	r5535
2249	2253	* vRef >-----------------------' \|/
2250	2254	*
2251	2255	* --------------------------------------------------
	2256	*
	2257	* DISC_OP_AMP_FILTER_IS_LOW_PASS_1M
	2258	* First Order Low Pass Filter
2252	2259	*
	2260	* c1
	2261	* .-------\|\|---------.
	2262	* \| \|
	2263	* r1 \| rF \|
	2264	* IN0 >--ZZZZ--. +------ZZZZ--------+
	2265	* \| \| \|
	2266	* r2 \| \| \|\ \|
	2267	* VP >--ZZZZ--+------+--------+ \| \ \|
	2268	* \| '--\|- \ \|
	2269	* r3 \| \| >--+----------> Netlist Node
	2270	* VN >--ZZZZ--' .--\|+ /
	2271	* \| \| /
	2272	* IN1 >------------------------' \|/
	2273	*
	2274	* --------------------------------------------------
	2275	*
2253	2276	* DISC_OP_AMP_FILTER_IS_HIGH_PASS_1
2254	2277	* First Order High Pass Filter
2255	2278	*
r5534	r5535
2482	2505	* \| \|
2483	2506	* ENAB -0------>\| \|
2484	2507	* \| diode R2 \|
2485		* INPUT1 -1------>\| -+-\|<\|--ZZZZ-+- \|----> Netlist node
	2508	* JV -5------>\| -+-\|>\|--ZZZZ-+- \|----> Netlist node (JV < 0)
	2509	* \| \|
	2510	* \| diode R2 \|
	2511	* INPUT1 -1------>\| -+-\|<\|--ZZZZ-+- \|----> Netlist node (JV > 0)
2486	2512	* \| \| \| \|
2487	2513	* RVAL1 -2------>\| '-ZZZZ-+----' \|
2488	2514	* \| R1 \| \|
r5534	r5535
2499	2525	* input node (or value),
2500	2526	* R1 resistor value in OHMS,
2501	2527	* R2 resistor value in OHMS,
2502		* capacitor value in FARADS)
	2528	* capacitor value in FARADS,
	2529	* diode junction voltage)
2503	2530	*
	2531	* The polarity of the diode junction voltage determines the polarity of the diode.
	2532	*
2504	2533	* Example config line
2505	2534	*
2506		* DISCRETE_RCDISC3(NODE_11,NODE_10,10,100,220,CAP_U(1))
	2535	* DISCRETE_RCDISC3(NODE_11,NODE_10,10,100,220,CAP_U(1), 0.5)
2507	2536	*
2508	2537	* When enabled by NODE_10, C charges from 10v as indicated by RC
2509	2538	* of 100R & 1uF.
2510	2539	*
2511		* EXAMPLES: see Tank8
	2540	* EXAMPLES: see Tank8, bzone
2512	2541	*
2513	2542	***********************************************************************
2514	2543	*
r5534	r5535
3203	3232	* DISCRETE_CUSTOMx(name of node,
3204	3233	* input 0 node or static value, ...)
3205	3234	*
3206		* discrete_custom_info = {reset, step, contextsize, custom}
3207		* reset = address called to reset a node after creation or system reset
3208		* step = address called to execute one time delta of output update
3209		* contextsize = size of context to create
	3235	* discrete_custom_info = {discrete_module, custom}
	3236	* discrete_module = discrete module definition
3210	3237	* custom = address of specific initialization data
3211	3238	*
3212		* ~~EXAMPLES:~~ see Donkey Kong
	3239	* In most case, you should be able to use
3213	3240	*
	3241	* discrete_custom_info = {DISCRETE_CUSTOM_MODULE(basename, context type), custom}
	3242	*
	3243	* if you have used DISCRETE_STEP(basename) and DISCRETE_RESET(basename) to define
	3244	* the step/reset procedures.
	3245	*
	3246	* EXAMPLES: see Donkey Kong, Mario Bros.
	3247	*
3214	3248	***********************************************************************
3215	3249	=======================================================================
3216	3250	* Debugging modules.
r5534	r5535
3304	3338	*************************************/
3305	3339
3306	3340	/* calculate charge exponent using discrete sample time */
3307		#define RC_CHARGE_EXP(rc) (1.0 - exp(d~~isc_~~info->neg_sample_time / (rc)))
	3341	#define RC_CHARGE_EXP(rc) (1.0 - exp(node->info->neg_sample_time / (rc)))
3308	3342	/* calculate charge exponent using given sample time */
3309	3343	#define RC_CHARGE_EXP_DT(rc, dt) (1.0 - exp(-(dt) / (rc)))
3310	3344	#define RC_CHARGE_NEG_EXP_DT(rc, dt) (1.0 - exp((dt) / (rc)))
3311	3345
3312	3346	/* calculate discharge exponent using discrete sample time */
3313		#define RC_DISCHARGE_EXP(rc) (exp(d~~isc_~~info->neg_sample_time / (rc)))
	3347	#define RC_DISCHARGE_EXP(rc) (exp(node->info->neg_sample_time / (rc)))
3314	3348	/* calculate discharge exponent using given sample time */
3315	3349	#define RC_DISCHARGE_EXP_DT(rc, dt) (exp(-(dt) / (rc)))
3316	3350	#define RC_DISCHARGE_NEG_EXP_DT(rc, dt) (exp((dt) / (rc)))
r5534	r5535
3324	3358	#define DISCRETE_STEP_NAME( _func ) _func ## _step
3325	3359	#define DISCRETE_RESET_NAME( _func ) _func ## _reset
3326	3360
3327		#define DISCRETE_STEP(_func) void DISCRETE_STEP_NAME(_func) (const discrete_info disc_info, node_description node)
3328		#define DISCRETE_RESET(_func) void DISCRETE_RESET_NAME(_func) (const discrete_info disc_info, node_description node)
	3361	#define DISCRETE_STEP(_func) void DISCRETE_STEP_NAME(_func) (node_description *node)
	3362	#define DISCRETE_RESET(_func) void DISCRETE_RESET_NAME(_func) (node_description *node)
3329	3363
3330		#define DISCRETE_STEP_CALL(_func) DISCRETE_STEP_NAME(_func) (disc_info, node)
3331		#define DISCRETE_RESET_CALL(_func) DISCRETE_RESET_NAME(_func) (disc_info, node)
	3364	#define DISCRETE_STEP_CALL(_func) DISCRETE_STEP_NAME(_func) (node)
	3365	#define DISCRETE_RESET_CALL(_func) DISCRETE_RESET_NAME(_func) (node)
3332	3366
3333		#if 0
3334		#define DISCRETE_STEP(_func) void DISCRETE_STEP_NAME(_func) (const device_config device, node_description node)
3335		#define DISCRETE_RESET(_func) void DISCRETE_RESET_NAME(_func) (const device_config device, node_description node)
	3367	#define DISCRETE_CUSTOM_MODULE(_basename, _context_type) \
	3368	{ DST_CUSTOM, "CUSTOM", 1, sizeof(_context_type), DISCRETE_RESET_NAME(_basename), DISCRETE_STEP_NAME(_basename) }
3336	3369
3337		#define DISCRETE_STEP_CALL(_func) DISCRETE_STEP_NAME(_func) (device, node)
3338		#define DISCRETE_RESET_CALL(_func) DISCRETE_RESET_NAME(_func) (device, node)
3339		#endif
	3370	#define DISCRETE_INPUT(_num) (*(node->input[_num]))
3340	3371
3341	3372	/*************************************
3342	3373	*
r5534	r5535
3346	3377
3347	3378	#define DISCRETE_MAX_NODES 300
3348	3379	#define DISCRETE_MAX_INPUTS 10
3349		#define DISCRETE_MAX_OUTPUTS 16
3350	3380	#define DISCRETE_MAX_WAVELOGS 10
3351	3381	#define DISCRETE_MAX_CSVLOGS 10
3352		#define DISCRETE_MAX_NO~~DE_O~~UTPUTS 8
	3382	#define DISCRETE_MAX_OUTPUTS 8
3353	3383
3354	3384
3355	3385	/*************************************
r5534	r5535
3460	3490	#define DISC_OP_AMP_FILTER_IS_BAND_PASS_1M 0x30
3461	3491	#define DISC_OP_AMP_FILTER_IS_HIGH_PASS_0 0x40
3462	3492	#define DISC_OP_AMP_FILTER_IS_BAND_PASS_0 0x50
	3493	#define DISC_OP_AMP_FILTER_IS_LOW_PASS_1M 0x60
3463	3494
3464	3495	#define DISC_OP_AMP_FILTER_TYPE_MASK (0xf0 \| DISC_OP_AMP_IS_NORTON) // Used only internally.
3465	3496
r5534	r5535
3585	3616	const char * name;
3586	3617	int num_output; /* Total number of output nodes, i.e. Master node + 1 */
3587	3618	size_t contextsize;
3588		void (reset)(const discrete_info disc_info, node_description node); / Called to reset a node after creation or system reset */
3589		void (step)(const discrete_info disc_info, node_description node); / Called to execute one time delta of output update */
	3619	void (reset)(node_description node); /* Called to reset a node after creation or system reset */
	3620	void (step)(node_description node); /* Called to execute one time delta of output update */
3590	3621	};
3591	3622
3592	3623
r5534	r5535
3599	3630	struct _node_description
3600	3631	{
3601	3632	int node; /* The node's index number in the node list */
3602		double output[DISCRETE_MAX_NO~~DE_O~~UTPUTS]; /* The node's last output value */
	3633	double output[DISCRETE_MAX_OUTPUTS]; /* The node's last output value */
3603	3634
3604	3635	int active_inputs; /* Number of active inputs on this node type */
3605	3636	int input_is_node; /* Bit Flags. 1 in bit location means input_is_node */
3606	3637	const double * input[DISCRETE_MAX_INPUTS]; /* Addresses of Input values */
3607	3638
3608		discrete_module module; /* Copy of the node's module info */
3609		const discrete_sound_block block; / Points to the node's setup block. */
3610	3639	void * context; /* Contextual information specific to this node type */
3611		const char * name; /* Text name string for identification/debug */
3612	3640	const void * custom; /* Custom function specific initialisation data */
	3641
	3642	const discrete_module module; / Node's module info */
	3643	const discrete_sound_block block; / Points to the node's setup block. */
	3644	const discrete_info info; / Points to the parent */
	3645
3613	3646	osd_ticks_t run_time;
3614	3647	};
3615	3648
r5534	r5535
3624	3657	*
3625	3658	*************************************/
3626	3659
	3660	typedef struct _linked_list_entry linked_list_entry;
	3661	struct _linked_list_entry
	3662	{
	3663	void *ptr;
	3664	linked_list_entry *next;
	3665	};
	3666
	3667	typedef struct _discrete_task_context discrete_task_context;
	3668	struct _discrete_task_context
	3669	{
	3670	linked_list_entry *list;
	3671
	3672	int numbuffered;
	3673	double *ptr[5];
	3674	double node_buf[5][2048];
	3675	double **dest[5];
	3676	};
	3677
3627	3678	struct _discrete_info
3628	3679	{
3629	3680	const device_config *device;
r5534	r5535
3634	3685	double neg_sample_time;
3635	3686
3636	3687	/* internal node tracking */
3637		int node_count;
3638		node_description **running_order;
3639	3688	node_description **indexed_node;
3640		node_description *node_list;
3641	3689
	3690	/* list of all nodes */
	3691	linked_list_entry node_list; / node_description * */
	3692
	3693	/* list of nodes which step */
	3694	linked_list_entry step_list; / node_description * */
	3695
	3696	/* list of discrete blocks after prescan (IMPORT, DELETE, REPLACE) */
	3697	linked_list_entry block_list; / discrete_sound_block * */
	3698
	3699	/* tasks */
	3700	linked_list_entry task_list; / discrete_task_context * */
	3701
3642	3702	/* the input streams */
3643		int discrete_input_streams;
3644		stream_sample_t *input_stream_data[DISCRETE_MAX_OUTPUTS];
	3703	linked_list_entry *input_list;
3645	3704
3646	3705	/* output node tracking */
3647		int discrete_outputs;
3648		node_description *output_node[DISCRETE_MAX_OUTPUTS];
	3706	linked_list_entry *output_list;
3649	3707
3650	3708	/* the output stream */
3651	3709	sound_stream *discrete_stream;
r5534	r5535
3664	3722	wav_file *disc_wav_file[DISCRETE_MAX_WAVELOGS];
3665	3723	node_description *wavelog_node[DISCRETE_MAX_WAVELOGS];
3666	3724
	3725	/* parallel tasks */
	3726
	3727	osd_work_queue *queue;
	3728
3667	3729	/* profiling */
3668	3730	int total_samples;
3669	3731	};
r5534	r5535
3927	3989	typedef struct _discrete_custom_info discrete_custom_info;
3928	3990	struct _discrete_custom_info
3929	3991	{
3930		void (reset)(const discrete_info disc_info, node_description node); / Called to reset a node after creation or system reset */
3931		void (step)(const discrete_info disc_info, node_description node); / Called to execute one time delta of output update */
3932		size_t contextsize;
	3992	const discrete_module module;
3933	3993	const void custom; / Custom function specific initialisation data */
3934	3994	};
3935	3995
r5534	r5535
3967	4027	*
3968	4028	*************************************/
3969	4029
3970		#define NODE0_DEF(_x) NODE_ ## 0 ## _x = (0x40000000 + (_x) * DISCRETE_MAX_~~NODE_~~OUTPUTS), \
	4030	#define NODE0_DEF(_x) NODE_ ## 0 ## _x = (0x40000000 + (_x) * DISCRETE_MAX_OUTPUTS), \
3971	4031	NODE_ ## 0 ## _x ## _01, NODE_ ## 0 ## _x ## _02, NODE_ ## 0 ## _x ## _03, NODE_ ## 0 ## _x ## _04, \
3972	4032	NODE_ ## 0 ## _x ## _05, NODE_ ## 0 ## _x ## _06, NODE_ ## 0 ## _x ## _07
3973		#define NODE_DEF(_x) NODE_ ## _x = (0x40000000 + (_x) * DISCRETE_MAX_~~NODE_~~OUTPUTS), \
	4033	#define NODE_DEF(_x) NODE_ ## _x = (0x40000000 + (_x) * DISCRETE_MAX_OUTPUTS), \
3974	4034	NODE_ ## _x ## _01, NODE_ ## _x ## _02, NODE_ ## _x ## _03, NODE_ ## _x ## _04, \
3975	4035	NODE_ ## _x ## _05, NODE_ ## _x ## _06, NODE_ ## _x ## _07
3976	4036
r5534	r5535
4009	4069
4010	4070	/* Some Pre-defined nodes for convenience */
4011	4071
4012		#define NODE(_x) (NODE_00 + (_x) * DISCRETE_MAX_~~NODE_~~OUTPUTS)
	4072	#define NODE(_x) (NODE_00 + (_x) * DISCRETE_MAX_OUTPUTS)
4013	4073	#define NODE_SUB(_x, _y) (NODE(_x) + (_y))
4014	4074
4015		#if DISCRETE_MAX_~~NODE_~~OUTPUTS == 8
	4075	#if DISCRETE_MAX_OUTPUTS == 8
4016	4076	#define NODE_CHILD_NODE_NUM(_x) ((int)(_x) & 7)
4017	4077	#define NODE_DEFAULT_NODE(_x) ((int)(_x) & ~7)
4018	4078	#define NODE_INDEX(_x) (((int)(_x) - NODE_START)>>3)
4019	4079	#else
4020		#error "DISCRETE_MAX_~~NODE_~~OUTPUTS != 8"
	4080	#error "DISCRETE_MAX_OUTPUTS != 8"
4021	4081	#endif
4022	4082
4023	4083	#define NODE_RELATIVE(_x, _y) (NODE(NODE_INDEX(_x) + (_y)))
r5534	r5535
4028	4088	#define NODE_START NODE_00
4029	4089	#define NODE_END NODE_SPECIAL
4030	4090
	4091	#define IS_VALUE_A_NODE(val) (((val) > NODE_START) && ((val) <= NODE_END))
4031	4092
4032	4093
4033	4094	/*************************************
r5534	r5535
4151	4212	DSO_CSVLOG, /* Dump nodes as csv file */
4152	4213	DSO_WAVELOG, /* Dump nodes as wav file */
4153	4214
	4215	/* Parallel execution */
	4216	DSO_TASK_START, /* start of parallel task */
	4217	DSO_TASK_END, /* end of parallel task */
	4218	DSO_TASK_SYNC, /* wait for all parallel tasks to finish */
	4219
4154	4220	/* Output Node -- this must be the last entry in this enum! */
4155	4221	DSO_OUTPUT, /* The final output node */
4156	4222
r5534	r5535
4292	4358	#define DISCRETE_OP_AMP_FILTER(NODE,ENAB,INP0,INP1,TYPE,INFO) { NODE, DST_OP_AMP_FILT , 4, { ENAB,INP0,INP1,NODE_NC }, { ENAB,INP0,INP1,TYPE }, INFO, "DISCRETE_OP_AMP_FILTER" },
4293	4359	#define DISCRETE_RCDISC(NODE,ENAB,INP0,RVAL,CVAL) { NODE, DST_RCDISC , 4, { ENAB,INP0,NODE_NC,NODE_NC }, { ENAB,INP0,RVAL,CVAL }, NULL, "DISCRETE_RCDISC" },
4294	4360	#define DISCRETE_RCDISC2(NODE,SWITCH,INP0,RVAL0,INP1,RVAL1,CVAL) { NODE, DST_RCDISC2 , 6, { SWITCH,INP0,NODE_NC,INP1,NODE_NC,NODE_NC }, { SWITCH,INP0,RVAL0,INP1,RVAL1,CVAL }, NULL, "DISCRETE_RCDISC2" },
4295		#define DISCRETE_RCDISC3(NODE,ENAB,INP0,RVAL0,RVAL1,CVAL) { NODE, DST_RCDISC3 , 5, { ENAB,INP0,NODE_NC,NODE_NC,NODE_NC }, { ENAB,INP0,RVAL0,RVAL1,CVAL }, NULL, "DISCRETE_RCDISC3" },
	4361	#define DISCRETE_RCDISC3(NODE,ENAB,INP0,RVAL0,RVAL1,CVAL,DJV) { NODE, DST_RCDISC3 , 6, { ENAB,INP0,NODE_NC,NODE_NC,NODE_NC,NODE_NC }, { ENAB,INP0,RVAL0,RVAL1,CVAL,DJV }, NULL, "DISCRETE_RCDISC3" },
4296	4362	#define DISCRETE_RCDISC4(NODE,ENAB,INP0,RVAL0,RVAL1,RVAL2,CVAL,VP,TYPE) { NODE, DST_RCDISC4 , 8, { ENAB,INP0,NODE_NC,NODE_NC,NODE_NC,NODE_NC,NODE_NC,NODE_NC }, { ENAB,INP0,RVAL0,RVAL1,RVAL2,CVAL,VP,TYPE }, NULL, "DISCRETE_RCDISC4" },
4297	4363	#define DISCRETE_RCDISC5(NODE,ENAB,INP0,RVAL,CVAL) { NODE, DST_RCDISC5 , 4, { ENAB,INP0,NODE_NC,NODE_NC }, { ENAB,INP0,RVAL,CVAL }, NULL, "DISCRETE_RCDISC5" },
4298	4364	#define DISCRETE_RCDISC_MODULATED(NODE,INP0,INP1,RVAL0,RVAL1,RVAL2,RVAL3,CVAL,VP) { NODE, DST_RCDISC_MOD, 8, { INP0,INP1,NODE_NC,NODE_NC,NODE_NC,NODE_NC,NODE_NC,NODE_NC }, { INP0,INP1,RVAL0,RVAL1,RVAL2,RVAL3,CVAL,VP }, NULL, "DISCRETE_RCDISC_MODULATED" },
r5534	r5535
4330	4396	#define DISCRETE_NOP(NODE) { NODE, DSS_NOP , 0, { 0 }, { 0 }, NULL, "DISCRETE_NOP" },
4331	4397
4332	4398	/* logging */
4333		#define DISCRETE_CSVLOG1(NODE1) { NODE_SPECIAL, DSO_CSVLOG , 1, { NODE1 }, { NODE1 }, NULL, "DISCRETE_CSVLOG1" },
4334		#define DISCRETE_CSVLOG2(NODE1,NODE2) { NODE_SPECIAL, DSO_CSVLOG , 2, { NODE1,NODE2 }, { NODE1,NODE2 }, NULL, "DISCRETE_CSVLOG2" },
4335		#define DISCRETE_CSVLOG3(NODE1,NODE2,NODE3) { NODE_SPECIAL, DSO_CSVLOG , 3, { NODE1,NODE2,NODE3 }, { NODE1,NODE2,NODE3 }, NULL, "DISCRETE_CSVLOG3" },
4336		#define DISCRETE_CSVLOG4(NODE1,NODE2,NODE3,NODE4) { NODE_SPECIAL, DSO_CSVLOG , 4, { NODE1,NODE2,NODE3,NODE4 }, { NODE1,NODE2,NODE3,NODE4 }, NULL, "DISCRETE_CSVLOG4" },
4337		#define DISCRETE_CSVLOG5(NODE1,NODE2,NODE3,NODE4,NODE5) { NODE_SPECIAL, DSO_CSVLOG , 5, { NODE1,NODE2,NODE3,NODE4,NODE5 }, { NODE1,NODE2,NODE3,NODE4,NODE5 }, NULL, "DISCRETE_CSVLOG5" },
4338		#define DISCRETE_WAVELOG1(NODE1,GAIN1) { NODE_SPECIAL, DSO_WAVELOG , 2, { NODE1,NODE_NC }, { NODE1,GAIN1 }, NULL, "DISCRETE_WAVELOG1" },
4339		#define DISCRETE_WAVELOG2(NODE1,GAIN1,NODE2,GAIN2) { NODE_SPECIAL, DSO_WAVELOG , 4, { NODE1,NODE_NC,NODE2,NODE_NC }, { NODE1,GAIN1,NODE2,GAIN2 }, NULL, "DISCRETE_WAVELOG2" },
	4399	#define DISCRETE_CSVLOG1(NODE1) { NODE_SPECIAL, DSO_CSVLOG , 1, { NODE1 }, { NODE1 }, NULL, "DISCRETE_CSVLOG1" },
	4400	#define DISCRETE_CSVLOG2(NODE1,NODE2) { NODE_SPECIAL, DSO_CSVLOG , 2, { NODE1,NODE2 }, { NODE1,NODE2 }, NULL, "DISCRETE_CSVLOG2" },
	4401	#define DISCRETE_CSVLOG3(NODE1,NODE2,NODE3) { NODE_SPECIAL, DSO_CSVLOG , 3, { NODE1,NODE2,NODE3 }, { NODE1,NODE2,NODE3 }, NULL, "DISCRETE_CSVLOG3" },
	4402	#define DISCRETE_CSVLOG4(NODE1,NODE2,NODE3,NODE4) { NODE_SPECIAL, DSO_CSVLOG , 4, { NODE1,NODE2,NODE3,NODE4 }, { NODE1,NODE2,NODE3,NODE4 }, NULL, "DISCRETE_CSVLOG4" },
	4403	#define DISCRETE_CSVLOG5(NODE1,NODE2,NODE3,NODE4,NODE5) { NODE_SPECIAL, DSO_CSVLOG , 5, { NODE1,NODE2,NODE3,NODE4,NODE5 }, { NODE1,NODE2,NODE3,NODE4,NODE5 }, NULL, "DISCRETE_CSVLOG5" },
	4404	#define DISCRETE_WAVELOG1(NODE1,GAIN1) { NODE_SPECIAL, DSO_WAVELOG , 2, { NODE1,NODE_NC }, { NODE1,GAIN1 }, NULL, "DISCRETE_WAVELOG1" },
	4405	#define DISCRETE_WAVELOG2(NODE1,GAIN1,NODE2,GAIN2) { NODE_SPECIAL, DSO_WAVELOG , 4, { NODE1,NODE_NC,NODE2,NODE_NC }, { NODE1,GAIN1,NODE2,GAIN2 }, NULL, "DISCRETE_WAVELOG2" },
4340	4406
4341	4407	/* import */
4342		#define DISCRETE_IMPORT(INFO) { NODE_SPECIAL, DSO_IMPORT , 0, { 0 }, { 0 }, &(INFO##_discrete_interface), "DISCRETE_IMPORT" },
4343		#define DISCRETE_DELETE(NODE_FROM, NODE_TO) { NODE_SPECIAL, DSO_DELETE , 2, { NODE_FROM, NODE_TO }, { NODE_FROM, NODE_TO }, NULL, "DISCRETE_DELETE" },
4344		#define DISCRETE_REPLACE { NODE_SPECIAL, DSO_REPLACE , 0, { 0 }, { 0 }, NULL, "DISCRETE_REPLACE" },
	4408	#define DISCRETE_IMPORT(INFO) { NODE_SPECIAL, DSO_IMPORT , 0, { 0 }, { 0 }, &(INFO##_discrete_interface), "DISCRETE_IMPORT" },
	4409	#define DISCRETE_DELETE(NODE_FROM, NODE_TO) { NODE_SPECIAL, DSO_DELETE , 2, { NODE_FROM, NODE_TO }, { NODE_FROM, NODE_TO }, NULL, "DISCRETE_DELETE" },
	4410	#define DISCRETE_REPLACE { NODE_SPECIAL, DSO_REPLACE , 0, { 0 }, { 0 }, NULL, "DISCRETE_REPLACE" },
4345	4411
	4412	/* parallel tasks */
4346	4413
	4414	#define DISCRETE_TASK_START() { NODE_SPECIAL, DSO_TASK_START, 0, { 0 }, { 0 }, NULL, "DISCRETE_TASK_START" },
	4415	#define DISCRETE_TASK_END(BNODE1) { NODE_SPECIAL, DSO_TASK_END , 1, { BNODE1 }, { BNODE1 }, NULL, "DISCRETE_TASK_END" },
	4416	#define DISCRETE_TASK_END2(BNODE1,BNODE2) { NODE_SPECIAL, DSO_TASK_END , 2, { BNODE1,BNODE2 }, { BNODE1,BNODE2 }, NULL, "DISCRETE_TASK_END2" },
	4417	#define DISCRETE_TASK_END3(BNODE1,BNODE2,BNODE3) { NODE_SPECIAL, DSO_TASK_END , 3, { BNODE1,BNODE2,BNODE3 }, { BNODE1,BNODE2,BNODE3 }, NULL, "DISCRETE_TASK_END3" },
	4418	#define DISCRETE_TASK_END4(BNODE1,BNODE2,BNODE3,BNODE4) { NODE_SPECIAL, DSO_TASK_END , 4, { BNODE1,BNODE2,BNODE3,BNODE4 }, { BNODE1,BNODE2,BNODE3,BNODE4 }, NULL, "DISCRETE_TASK_END4" },
	4419	#define DISCRETE_TASK_END5(BNODE1,BNODE2,BNODE3,BNODE4,BNODE5) { NODE_SPECIAL, DSO_TASK_END , 5, { BNODE1,BNODE2,BNODE3,BNODE4,BNODE5 }, { BNODE1,BNODE2,BNODE3,BNODE4,BNODE5 }, NULL, "DISCRETE_TASK_END5" },
	4420	//#define DISCRETE_TASK_SYNC() { NODE_SPECIAL, DSO_TASK_SYNC, 0, { 0 }, { 0 }, NULL, "DISCRETE_TASK_SYNC" },
	4421
4347	4422	/* output */
4348	4423	#define DISCRETE_OUTPUT(OPNODE,GAIN) { NODE_SPECIAL, DSO_OUTPUT , 2, { OPNODE,NODE_NC }, { 0,GAIN }, NULL, "DISCRETE_OUTPUT" },
4349	4424
4350	4425
4351
4352		#define IS_VALUE_A_NODE(val) (((val) > NODE_START) && ((val) <= NODE_END))
4353
4354	4426	/*************************************
4355	4427	*
4356	4428	* Interface to the external world

src/emu/sound/disc_dev.c
r5534	r5535
141	141	*
142	142	* Jan 2004, D Renaud.
143	143	************************************************************************/
144		#define DSD_555_ASTBL__RESET (! *(node->input[0]))
145		#define DSD_555_ASTBL__R1 (*(node->input[1]))
146		#define DSD_555_ASTBL__R2 (*(node->input[2]))
147		#define DSD_555_ASTBL__C (*(node->input[3]))
148		#define DSD_555_ASTBL__CTRLV (*(node->input[4]))
	144	#define DSD_555_ASTBL__RESET (! DISCRETE_INPUT(0))
	145	#define DSD_555_ASTBL__R1 DISCRETE_INPUT(1)
	146	#define DSD_555_ASTBL__R2 DISCRETE_INPUT(2)
	147	#define DSD_555_ASTBL__C DISCRETE_INPUT(3)
	148	#define DSD_555_ASTBL__CTRLV DISCRETE_INPUT(4)
149	149
150	150	/* bit mask of the above RC inputs */
151	151	#define DSD_555_ASTBL_RC_MASK 0x0e
r5534	r5535
234	234	* dt = R*C(log(1/(1-(Vc/Vr))))
235	235	*/
236	236
237		dt = d~~isc_~~info->sample_time;
	237	dt = node->info->sample_time;
238	238
239	239	/* Sometimes a switching network is used to setup the capacitance.
240	240	* These may select no capacitor, causing oscillation to stop.
r5534	r5535
338	338	}
339	339
340	340	/* Convert last switch time to a ratio */
341		x_time = x_time / d~~isc_~~info->sample_time;
	341	x_time = x_time / node->info->sample_time;
342	342
343	343	switch (context->output_type)
344	344	{
r5534	r5535
387	387	context->v_out_high = (info->v_out_high == DEFAULT_555_HIGH) ? info->v_pos - 1.2 : info->v_out_high;
388	388
389	389	/* setup v_charge or node */
390		v_charge_node = discrete_find_node(d~~isc_~~info, info->v_charge);
	390	v_charge_node = discrete_find_node(node->info, info->v_charge);
391	391	if (v_charge_node)
392	392	context->v_charge_node = &(v_charge_node->output[NODE_CHILD_NODE_NUM(info->v_charge)]);
393	393	else
r5534	r5535
450	450	*
451	451	* Oct 2004, D Renaud.
452	452	************************************************************************/
453		#define DSD_555_MSTBL__RESET (! *(node->input[0]))
454		#define DSD_555_MSTBL__TRIGGER (*(node->input[1]))
455		#define DSD_555_MSTBL__R (*(node->input[2]))
456		#define DSD_555_MSTBL__C (*(node->input[3]))
	453	#define DSD_555_MSTBL__RESET (! DISCRETE_INPUT(0))
	454	#define DSD_555_MSTBL__TRIGGER DISCRETE_INPUT(1)
	455	#define DSD_555_MSTBL__R DISCRETE_INPUT(2)
	456	#define DSD_555_MSTBL__C DISCRETE_INPUT(3)
457	457
458	458	static DISCRETE_STEP(dsd_555_mstbl)
459	459	{
r5534	r5535
548	548	context->output_type = info->options & DISC_555_OUT_MASK;
549	549	if ((context->output_type == DISC_555_OUT_COUNT_F) \|\| (context->output_type == DISC_555_OUT_COUNT_R))
550	550	{
551		discrete_log(d~~isc_~~info, "Invalid Output type in NODE_%d.\n", node->node - NODE_00);
	551	discrete_log(node->info, "Invalid Output type in NODE_%d.\n", node->node - NODE_00);
552	552	context->output_type = DISC_555_OUT_SQW;
553	553	}
554	554
r5534	r5535
590	590	*
591	591	* Mar 2004, D Renaud.
592	592	************************************************************************/
593		#define DSD_555_CC__RESET (! *(node->input[0]))
594		#define DSD_555_CC__VIN (*(node->input[1]))
595		#define DSD_555_CC__R (*(node->input[2]))
596		#define DSD_555_CC__C (*(node->input[3]))
597		#define DSD_555_CC__RBIAS (*(node->input[4]))
598		#define DSD_555_CC__RGND (*(node->input[5]))
599		#define DSD_555_CC__RDIS (*(node->input[6]))
	593	#define DSD_555_CC__RESET (! DISCRETE_INPUT(0))
	594	#define DSD_555_CC__VIN DISCRETE_INPUT(1)
	595	#define DSD_555_CC__R DISCRETE_INPUT(2)
	596	#define DSD_555_CC__C DISCRETE_INPUT(3)
	597	#define DSD_555_CC__RBIAS DISCRETE_INPUT(4)
	598	#define DSD_555_CC__RGND DISCRETE_INPUT(5)
	599	#define DSD_555_CC__RDIS DISCRETE_INPUT(6)
600	600
601	601	/* bit mask of the above RC inputs not including DSD_555_CC__R */
602	602	#define DSD_555_CC_RC_MASK 0x78
r5534	r5535
642	642	return;
643	643	}
644	644
645		dt = d~~isc_~~info->sample_time; /* Change in time */
	645	dt = node->info->sample_time; /* Change in time */
646	646	v_cap = context->cap_voltage; /* Set to voltage before change */
647	647	v_vcharge_limit = DSD_555_CC__VIN + info->v_cc_junction; /* the max v_cap can be and still be charged by i */
648	648	/* Calculate charging current */
r5534	r5535
888	888	context->cap_voltage = v_cap_next;
889	889
890	890	/* Convert last switch time to a ratio */
891		x_time = x_time / d~~isc_~~info->sample_time;
	891	x_time = x_time / node->info->sample_time;
892	892
893	893	switch (context->output_type)
894	894	{
r5534	r5535
1155	1155	*
1156	1156	* Apr 2006, D Renaud.
1157	1157	************************************************************************/
1158		#define DSD_555_VCO1__RESET ((node->input[0])) / reset active low */
1159		#define DSD_555_VCO1__VIN1 (*(node->input[1]))
1160		#define DSD_555_VCO1__VIN2 (*(node->input[2]))
	1158	#define DSD_555_VCO1__RESET DISCRETE_INPUT(0) /* reset active low */
	1159	#define DSD_555_VCO1__VIN1 DISCRETE_INPUT(1)
	1160	#define DSD_555_VCO1__VIN2 DISCRETE_INPUT(2)
1161	1161
1162	1162	static DISCRETE_STEP(dsd_555_vco1)
1163	1163	{
r5534	r5535
1171	1171	double v_cap; /* Current voltage on capacitor, before dt */
1172	1172	double v_cap_next = 0; /* Voltage on capacitor, after dt */
1173	1173
1174		dt = d~~isc_~~info->sample_time; /* Change in time */
	1174	dt = node->info->sample_time; /* Change in time */
1175	1175	v_cap = context->cap_voltage;
1176	1176
1177	1177	/* Check: if the Control Voltage node is connected. */
r5534	r5535
1275	1275	context->cap_voltage = v_cap_next;
1276	1276
1277	1277	/* Convert last switch time to a ratio. No x_time in reset. */
1278		x_time = x_time / d~~isc_~~info->sample_time;
	1278	x_time = x_time / node->info->sample_time;
1279	1279	if (!DSD_555_VCO1__RESET) x_time = 0;
1280	1280
1281	1281	switch (context->output_type)
r5534	r5535
1385	1385	*
1386	1386	* Mar 2004, D Renaud.
1387	1387	************************************************************************/
1388		#define DSD_566__ENABLE (*(node->input[0]))
1389		#define DSD_566__VMOD (*(node->input[1]))
1390		#define DSD_566__R (*(node->input[2]))
1391		#define DSD_566__C (*(node->input[3]))
	1388	#define DSD_566__ENABLE DISCRETE_INPUT(0)
	1389	#define DSD_566__VMOD DISCRETE_INPUT(1)
	1390	#define DSD_566__R DISCRETE_INPUT(2)
	1391	#define DSD_566__C DISCRETE_INPUT(3)
1392	1392
1393	1393	static DISCRETE_STEP(dsd_566)
1394	1394	{
r5534	r5535
1403	1403
1404	1404	if (DSD_566__ENABLE && !context->error)
1405	1405	{
1406		dt = d~~isc_~~info->sample_time; /* Change in time */
	1406	dt = node->info->sample_time; /* Change in time */
1407	1407	v_cap = context->cap_voltage; /* Set to voltage before change */
1408	1408
1409	1409	/* get the v_charge and update each step if it is a node */
r5534	r5535
1528	1528	}
1529	1529
1530	1530	/* setup v_charge or node */
1531		v_charge_node = discrete_find_node(d~~isc_~~info, info->v_charge);
	1531	v_charge_node = discrete_find_node(node->info, info->v_charge);
1532	1532	if (v_charge_node)
1533	1533	context->v_charge_node = &(v_charge_node->output[NODE_CHILD_NODE_NUM(info->v_charge)]);
1534	1534	else
r5534	r5535
1575	1575	*
1576	1576	* Dec 2007, Couriersud
1577	1577	************************************************************************/
1578		#define DSD_LS624__ENABLE (*(node->input[0]))
1579		#define DSD_LS624__VMOD (*(node->input[1]))
1580		#define DSD_LS624__VRNG (*(node->input[2]))
1581		#define DSD_LS624__C (*(node->input[3]))
1582		#define DSD_LS624__OUTTYPE (*(node->input[4]))
	1578	#define DSD_LS624__ENABLE DISCRETE_INPUT(0)
	1579	#define DSD_LS624__VMOD DISCRETE_INPUT(1)
	1580	#define DSD_LS624__VRNG DISCRETE_INPUT(2)
	1581	#define DSD_LS624__C DISCRETE_INPUT(3)
	1582	#define DSD_LS624__OUTTYPE DISCRETE_INPUT(4)
1583	1583
1584	1584	/*
1585	1585	* The datasheet mentions a 600 ohm discharge. It also gives
r5534	r5535
1608	1608	double en = 0.0f;
1609	1609	int cntf = 0, cntr = 0;
1610	1610
1611		sample_t = d~~isc_~~info->sample_time; /* Change in time */
	1611	sample_t = node->info->sample_time; /* Change in time */
1612	1612	//dt = LS624_T(DSD_LS624__C, DSD_LS624__VRNG, DSD_LS624__VMOD) / 2.0;
1613	1613	dt = 1.0f / (2.0f * LS624_F(DSD_LS624__C, DSD_LS624__VMOD, DSD_LS624__VRNG));
1614	1614	t = context->remain;

src/emu/sound/disc_wav.c
r5534	r5535
170	170	*
171	171	* Jan 2004, D Renaud.
172	172	************************************************************************/
173		#define DSS_COUNTER__ENABLE (*(node->input[0]))
174		#define DSS_COUNTER__RESET (*(node->input[1]))
175		#define DSS_COUNTER__CLOCK (*(node->input[2]))
176		#define DSS_COUNTER__MAX (*(node->input[3]))
177		#define DSS_COUNTER__DIR (*(node->input[4]))
178		#define DSS_COUNTER__INIT (*(node->input[5]))
179		#define DSS_COUNTER__CLOCK_TYPE (*(node->input[6]))
	173	#define DSS_COUNTER__ENABLE DISCRETE_INPUT(0)
	174	#define DSS_COUNTER__RESET DISCRETE_INPUT(1)
	175	#define DSS_COUNTER__CLOCK DISCRETE_INPUT(2)
	176	#define DSS_COUNTER__MAX DISCRETE_INPUT(3)
	177	#define DSS_COUNTER__DIR DISCRETE_INPUT(4)
	178	#define DSS_COUNTER__INIT DISCRETE_INPUT(5)
	179	#define DSS_COUNTER__CLOCK_TYPE DISCRETE_INPUT(6)
180	180	#define DSS_7492__CLOCK_TYPE DSS_COUNTER__MAX
181	181
182	182	static const int disc_7492_count[6] = {0x00, 0x01, 0x02, 0x04, 0x05, 0x06};
r5534	r5535
199	199	if (context->clock_type == DISC_CLK_IS_FREQ)
200	200	{
201	201	/* We need to keep clocking the internal clock even if disabled. */
202		cycles = (context->t_left + d~~isc_~~info->sample_time) * ds_clock;
	202	cycles = (context->t_left + node->info->sample_time) * ds_clock;
203	203	inc = (int)cycles;
204	204	context->t_left = (cycles - inc) / ds_clock;
205		if (inc) x_time = context->t_left / d~~isc_~~info->sample_time;
	205	if (inc) x_time = context->t_left / node->info->sample_time;
206	206	}
207	207	else
208	208	{
r5534	r5535
318	318	* also passed dss_lfsr_context structure
319	319	*
320	320	************************************************************************/
321		#define DSS_LFSR_NOISE__ENABLE (*(node->input[0]))
322		#define DSS_LFSR_NOISE__RESET (*(node->input[1]))
323		#define DSS_LFSR_NOISE__CLOCK (*(node->input[2]))
324		#define DSS_LFSR_NOISE__AMP (*(node->input[3]))
325		#define DSS_LFSR_NOISE__FEED (*(node->input[4]))
326		#define DSS_LFSR_NOISE__BIAS (*(node->input[5]))
	321	#define DSS_LFSR_NOISE__ENABLE DISCRETE_INPUT(0)
	322	#define DSS_LFSR_NOISE__RESET DISCRETE_INPUT(1)
	323	#define DSS_LFSR_NOISE__CLOCK DISCRETE_INPUT(2)
	324	#define DSS_LFSR_NOISE__AMP DISCRETE_INPUT(3)
	325	#define DSS_LFSR_NOISE__FEED DISCRETE_INPUT(4)
	326	#define DSS_LFSR_NOISE__BIAS DISCRETE_INPUT(5)
327	327
328	328	INLINE int dss_lfsr_function(const discrete_info *disc_info, int myfunc, int in0, int in1, int bitmask)
329	329	{
r5534	r5535
401	401	if (lfsr_desc->clock_type == DISC_CLK_IS_FREQ)
402	402	{
403	403	/* We need to keep clocking the internal clock even if disabled. */
404		cycles = (context->t_left + d~~isc_~~info->sample_time) / context->t_clock;
	404	cycles = (context->t_left + node->info->sample_time) / context->t_clock;
405	405	inc = (int)cycles;
406	406	context->t_left = (cycles - inc) * context->t_clock;
407	407	}
r5534	r5535
445	445	fbresult = (context->lfsr_reg >> lfsr_desc->bitlength) & 0x01;
446	446
447	447	/* Stage 2 feedback combine fbresultNew with infeed bit */
448		fbresult = dss_lfsr_function(d~~isc_~~info, lfsr_desc->feedback_function1, fbresult, noise_feed, 0x01);
	448	fbresult = dss_lfsr_function(node->info, lfsr_desc->feedback_function1, fbresult, noise_feed, 0x01);
449	449
450	450	/* Stage 3 first we setup where the bit is going to be shifted into */
451	451	fbresult = fbresult * lfsr_desc->feedback_function2_mask;
452	452	/* Then we left shift the register, */
453	453	context->lfsr_reg = context->lfsr_reg << 1;
454	454	/* Now move the fbresult into the shift register and mask it to the bitlength */
455		context->lfsr_reg = dss_lfsr_function(d~~isc_~~info, lfsr_desc->feedback_function2, fbresult, context->lfsr_reg, (1 << lfsr_desc->bitlength) - 1 );
	455	context->lfsr_reg = dss_lfsr_function(node->info, lfsr_desc->feedback_function2, fbresult, context->lfsr_reg, (1 << lfsr_desc->bitlength) - 1 );
456	456
457	457	/* Now get and store the new feedback result */
458	458	/* Fetch the feedback bits */
459	459	fb0 = (context->lfsr_reg >> lfsr_desc->feedback_bitsel0) & 0x01;
460	460	fb1 = (context->lfsr_reg >> lfsr_desc->feedback_bitsel1) & 0x01;
461	461	/* Now do the combo on them */
462		fbresult = dss_lfsr_function(disc_info, lfsr_desc->feedback_function0, fb0, fb1, 0x01);
463		context->lfsr_reg = dss_lfsr_function(disc_info, DISC_LFSR_REPLACE, context->lfsr_reg, fbresult << lfsr_desc->bitlength, (2 << lfsr_desc->bitlength) - 1);
	462	fbresult = dss_lfsr_function(node->info, lfsr_desc->feedback_function0, fb0, fb1, 0x01);
	463	context->lfsr_reg = dss_lfsr_function(node->info, DISC_LFSR_REPLACE, context->lfsr_reg, fbresult << lfsr_desc->bitlength, (2 << lfsr_desc->bitlength) - 1);
464	464
465	465	}
466	466	/* Now select the output bit */
r5534	r5535
479	479
480	480	/* output the lfsr reg ?*/
481	481	if (context->out_lfsr_reg)
482		node->output[1] = context->lfsr_reg;
	482	node->output[1] = (double) context->lfsr_reg;
483	483
484	484	}
485	485	if(!DSS_LFSR_NOISE__ENABLE)
r5534	r5535
500	500	context->out_lfsr_reg = (lfsr_desc->flags & DISC_LFSR_FLAG_OUTPUT_SR_SN1) ? 1 : 0;
501	501
502	502	if ((lfsr_desc->clock_type < DISC_CLK_ON_F_EDGE) \|\| (lfsr_desc->clock_type > DISC_CLK_IS_FREQ))
503		discrete_log(d~~isc_~~info, "Invalid clock type passed in NODE_%d\n", NODE_INDEX(node->node));
	503	discrete_log(node->info, "Invalid clock type passed in NODE_%d\n", NODE_INDEX(node->node));
504	504
505	505	context->last = (DSS_COUNTER__CLOCK != 0);
506	506	if (lfsr_desc->clock_type == DISC_CLK_IS_FREQ) context->t_clock = 1.0 / DSS_LFSR_NOISE__CLOCK;
r5534	r5535
513	513	fb0 = (context->lfsr_reg >> lfsr_desc->feedback_bitsel0) & 0x01;
514	514	fb1=(context->lfsr_reg >> lfsr_desc->feedback_bitsel1) & 0x01;
515	515	/* Now do the combo on them */
516		fbresult = dss_lfsr_function(disc_info, lfsr_desc->feedback_function0, fb0, fb1, 0x01);
517		context->lfsr_reg=dss_lfsr_function(disc_info, DISC_LFSR_REPLACE, context->lfsr_reg, fbresult << lfsr_desc->bitlength, (2<< lfsr_desc->bitlength ) - 1);
	516	fbresult = dss_lfsr_function(node->info, lfsr_desc->feedback_function0, fb0, fb1, 0x01);
	517	context->lfsr_reg=dss_lfsr_function(node->info, DISC_LFSR_REPLACE, context->lfsr_reg, fbresult << lfsr_desc->bitlength, (2<< lfsr_desc->bitlength ) - 1);
518	518
519	519	/* Now select and setup the output bit */
520	520	node->output[0] = (context->lfsr_reg >> lfsr_desc->output_bit) & 0x01;
r5534	r5535
539	539	* input3 - DC Bias value
540	540	*
541	541	************************************************************************/
542		#define DSS_NOISE__ENABLE (*(node->input[0]))
543		#define DSS_NOISE__FREQ (*(node->input[1]))
544		#define DSS_NOISE__AMP (*(node->input[2]))
545		#define DSS_NOISE__BIAS (*(node->input[3]))
	542	#define DSS_NOISE__ENABLE DISCRETE_INPUT(0)
	543	#define DSS_NOISE__FREQ DISCRETE_INPUT(1)
	544	#define DSS_NOISE__AMP DISCRETE_INPUT(2)
	545	#define DSS_NOISE__BIAS DISCRETE_INPUT(3)
546	546
547	547	static DISCRETE_STEP(dss_noise)
548	548	{
r5534	r5535
554	554	if(context->phase > (2.0 * M_PI))
555	555	{
556	556	/* GCC's rand returns a RAND_MAX value of 0x7fff */
557		int newval = (mame_rand(d~~isc_~~info->device->machine) & 0x7fff) - 16384;
	557	int newval = (mame_rand(node->info->device->machine) & 0x7fff) - 16384;
558	558
559	559	/* make sure the peak to peak values are the amplitude */
560	560	node->output[0] = DSS_NOISE__AMP / 2;
r5534	r5535
577	577
578	578	/* The enable input only curtails output, phase rotation still occurs. */
579	579	/* We allow the phase to exceed 2Pi here, so we can tell when to sample the noise. */
580		context->phase += ((2.0 * M_PI * DSS_NOISE__FREQ) / d~~isc_~~info->sample_rate);
	580	context->phase += ((2.0 * M_PI * DSS_NOISE__FREQ) / node->info->sample_rate);
581	581	}
582	582
583	583
r5534	r5535
603	603	*
604	604	* Mar 2004, D Renaud.
605	605	************************************************************************/
606		#define DSS_NOTE__ENABLE (*(node->input[0]))
607		#define DSS_NOTE__CLOCK (*(node->input[1]))
608		#define DSS_NOTE__DATA (*(node->input[2]))
609		#define DSS_NOTE__MAX1 (*(node->input[3]))
610		#define DSS_NOTE__MAX2 (*(node->input[4]))
611		#define DSS_NOTE__CLOCK_TYPE (*(node->input[5]))
	606	#define DSS_NOTE__ENABLE DISCRETE_INPUT(0)
	607	#define DSS_NOTE__CLOCK DISCRETE_INPUT(1)
	608	#define DSS_NOTE__DATA DISCRETE_INPUT(2)
	609	#define DSS_NOTE__MAX1 DISCRETE_INPUT(3)
	610	#define DSS_NOTE__MAX2 DISCRETE_INPUT(4)
	611	#define DSS_NOTE__CLOCK_TYPE DISCRETE_INPUT(5)
612	612
613	613	static DISCRETE_STEP(dss_note)
614	614	{
r5534	r5535
621	621	if (context->clock_type == DISC_CLK_IS_FREQ)
622	622	{
623	623	/* We need to keep clocking the internal clock even if disabled. */
624		cycles = (context->t_left + d~~isc_~~info->sample_time) / context->t_clock;
	624	cycles = (context->t_left + node->info->sample_time) / context->t_clock;
625	625	inc = (int)cycles;
626	626	context->t_left = (cycles - inc) * context->t_clock;
627		if (inc) x_time = context->t_left / d~~isc_~~info->sample_time;
	627	if (inc) x_time = context->t_left / node->info->sample_time;
628	628	}
629	629	else
630	630	{
r5534	r5535
730	730	*
731	731	* Mar 2004, D Renaud.
732	732	************************************************************************/
733		#define DSS_OP_AMP_OSC__ENABLE (*(node->input[0]))
734		#define DSS_OP_AMP_OSC__VMOD1 (*(node->input[1]))
735		#define DSS_OP_AMP_OSC__VMOD2 (*(node->input[2]))
	733	#define DSS_OP_AMP_OSC__ENABLE DISCRETE_INPUT(0)
	734	#define DSS_OP_AMP_OSC__VMOD1 DISCRETE_INPUT(1)
	735	#define DSS_OP_AMP_OSC__VMOD2 DISCRETE_INPUT(2)
736	736
737	737	/* The inputs on a norton op-amp are (info->vP - OP_AMP_NORTON_VBE) */
738	738	/* which is the same as the output high voltage. We will define them */
r5534	r5535
754	754	UINT8 force_charge = 0;
755	755	UINT8 enable = DSS_OP_AMP_OSC__ENABLE;
756	756
757		dt = d~~isc_~~info->sample_time; /* Change in time */
	757	dt = node->info->sample_time; /* Change in time */
758	758	vC = context->v_cap; /* Set to voltage before change */
759	759
760	760	/* work out the charge currents for the VCOs. */
r5534	r5535
931	931	{
932	932	if IS_VALUE_A_NODE(*r_info_ptr)
933	933	{
934		r_node = discrete_find_node(d~~isc_~~info, *r_info_ptr);
	934	r_node = discrete_find_node(node->info, *r_info_ptr);
935	935	r_context_ptr = &(r_node->output[NODE_CHILD_NODE_NUM((int)r_info_ptr)]);
936	936	}
937	937	else
r5534	r5535
1048	1048	* input5 - Initial Phase
1049	1049	*
1050	1050	************************************************************************/
1051		#define DSS_SAWTOOTHWAVE__ENABLE (*(node->input[0]))
1052		#define DSS_SAWTOOTHWAVE__FREQ (*(node->input[1]))
1053		#define DSS_SAWTOOTHWAVE__AMP (*(node->input[2]))
1054		#define DSS_SAWTOOTHWAVE__BIAS (*(node->input[3]))
1055		#define DSS_SAWTOOTHWAVE__GRAD (*(node->input[4]))
1056		#define DSS_SAWTOOTHWAVE__PHASE (*(node->input[5]))
	1051	#define DSS_SAWTOOTHWAVE__ENABLE DISCRETE_INPUT(0)
	1052	#define DSS_SAWTOOTHWAVE__FREQ DISCRETE_INPUT(1)
	1053	#define DSS_SAWTOOTHWAVE__AMP DISCRETE_INPUT(2)
	1054	#define DSS_SAWTOOTHWAVE__BIAS DISCRETE_INPUT(3)
	1055	#define DSS_SAWTOOTHWAVE__GRAD DISCRETE_INPUT(4)
	1056	#define DSS_SAWTOOTHWAVE__PHASE DISCRETE_INPUT(5)
1057	1057
1058	1058	static DISCRETE_STEP(dss_sawtoothwave)
1059	1059	{
r5534	r5535
1078	1078	/* boils out to */
1079	1079	/* phase step = (2Pioutput freq)/sample freq) /
1080	1080	/* Also keep the new phasor in the 2Pi range. */
1081		context->phase = fmod((context->phase + ((2.0 * M_PI * DSS_SAWTOOTHWAVE__FREQ) / d~~isc_~~info->sample_rate)), 2.0 * M_PI);
	1081	context->phase = fmod((context->phase + ((2.0 * M_PI * DSS_SAWTOOTHWAVE__FREQ) / node->info->sample_rate)), 2.0 * M_PI);
1082	1082	}
1083	1083
1084	1084	static DISCRETE_RESET(dss_sawtoothwave)
r5534	r5535
1111	1111	*
1112	1112	* Mar 2004, D Renaud.
1113	1113	************************************************************************/
1114		#define DSS_SCHMITT_OSC__ENABLE (int)(*(node->input[0]))
1115		#define DSS_SCHMITT_OSC__VIN (*(node->input[1]))
1116		#define DSS_SCHMITT_OSC__AMP (*(node->input[2]))
	1114	#define DSS_SCHMITT_OSC__ENABLE (int)DISCRETE_INPUT(0)
	1115	#define DSS_SCHMITT_OSC__VIN DISCRETE_INPUT(1)
	1116	#define DSS_SCHMITT_OSC__AMP DISCRETE_INPUT(2)
1117	1117
1118	1118	static DISCRETE_STEP(dss_schmitt_osc)
1119	1119	{
r5534	r5535
1228	1228	* input4 - Starting phase
1229	1229	*
1230	1230	************************************************************************/
1231		#define DSS_SINEWAVE__ENABLE (*(node->input[0]))
1232		#define DSS_SINEWAVE__FREQ (*(node->input[1]))
1233		#define DSS_SINEWAVE__AMPL (*(node->input[2]))
1234		#define DSS_SINEWAVE__BIAS (*(node->input[3]))
1235		#define DSS_SINEWAVE__PHASE (*(node->input[4]))
	1231	#define DSS_SINEWAVE__ENABLE DISCRETE_INPUT(0)
	1232	#define DSS_SINEWAVE__FREQ DISCRETE_INPUT(1)
	1233	#define DSS_SINEWAVE__AMPL DISCRETE_INPUT(2)
	1234	#define DSS_SINEWAVE__BIAS DISCRETE_INPUT(3)
	1235	#define DSS_SINEWAVE__PHASE DISCRETE_INPUT(4)
1236	1236
1237	1237	static DISCRETE_STEP(dss_sinewave)
1238	1238	{
r5534	r5535
1257	1257	/* boils out to */
1258	1258	/* phase step = (2Pioutput freq)/sample freq) /
1259	1259	/* Also keep the new phasor in the 2Pi range. */
1260		context->phase=fmod((context->phase + ((2.0 * M_PI * DSS_SINEWAVE__FREQ) / d~~isc_~~info->sample_rate)), 2.0 * M_PI);
	1260	context->phase=fmod((context->phase + ((2.0 * M_PI * DSS_SINEWAVE__FREQ) / node->info->sample_rate)), 2.0 * M_PI);
1261	1261	}
1262	1262
1263	1263	static DISCRETE_RESET(dss_sinewave)
r5534	r5535
1286	1286	* input5 - Start Phase
1287	1287	*
1288	1288	************************************************************************/
1289		#define DSS_SQUAREWAVE__ENABLE (*(node->input[0]))
1290		#define DSS_SQUAREWAVE__FREQ (*(node->input[1]))
1291		#define DSS_SQUAREWAVE__AMP (*(node->input[2]))
1292		#define DSS_SQUAREWAVE__DUTY (*(node->input[3]))
1293		#define DSS_SQUAREWAVE__BIAS (*(node->input[4]))
1294		#define DSS_SQUAREWAVE__PHASE (*(node->input[5]))
	1289	#define DSS_SQUAREWAVE__ENABLE DISCRETE_INPUT(0)
	1290	#define DSS_SQUAREWAVE__FREQ DISCRETE_INPUT(1)
	1291	#define DSS_SQUAREWAVE__AMP DISCRETE_INPUT(2)
	1292	#define DSS_SQUAREWAVE__DUTY DISCRETE_INPUT(3)
	1293	#define DSS_SQUAREWAVE__BIAS DISCRETE_INPUT(4)
	1294	#define DSS_SQUAREWAVE__PHASE DISCRETE_INPUT(5)
1295	1295
1296	1296	static DISCRETE_STEP(dss_squarewave)
1297	1297	{
r5534	r5535
1323	1323	/* boils out to */
1324	1324	/* phase step = (2Pioutput freq)/sample freq) /
1325	1325	/* Also keep the new phasor in the 2Pi range. */
1326		context->phase=fmod(context->phase + ((2.0 * M_PI * DSS_SQUAREWAVE__FREQ) / d~~isc_~~info->sample_rate), 2.0 * M_PI);
	1326	context->phase=fmod(context->phase + ((2.0 * M_PI * DSS_SQUAREWAVE__FREQ) / node->info->sample_rate), 2.0 * M_PI);
1327	1327	}
1328	1328
1329	1329	static DISCRETE_RESET(dss_squarewave)
r5534	r5535
1352	1352	* input5 - Start Phase
1353	1353	*
1354	1354	************************************************************************/
1355		#define DSS_SQUAREWFIX__ENABLE (*(node->input[0]))
1356		#define DSS_SQUAREWFIX__FREQ (*(node->input[1]))
1357		#define DSS_SQUAREWFIX__AMP (*(node->input[2]))
1358		#define DSS_SQUAREWFIX__DUTY (*(node->input[3]))
1359		#define DSS_SQUAREWFIX__BIAS (*(node->input[4]))
1360		#define DSS_SQUAREWFIX__PHASE (*(node->input[5]))
	1355	#define DSS_SQUAREWFIX__ENABLE DISCRETE_INPUT(0)
	1356	#define DSS_SQUAREWFIX__FREQ DISCRETE_INPUT(1)
	1357	#define DSS_SQUAREWFIX__AMP DISCRETE_INPUT(2)
	1358	#define DSS_SQUAREWFIX__DUTY DISCRETE_INPUT(3)
	1359	#define DSS_SQUAREWFIX__BIAS DISCRETE_INPUT(4)
	1360	#define DSS_SQUAREWFIX__PHASE DISCRETE_INPUT(5)
1361	1361
1362	1362	static DISCRETE_STEP(dss_squarewfix)
1363	1363	{
r5534	r5535
1392	1392	{
1393	1393	struct dss_squarewfix_context context = (struct dss_squarewfix_context )node->context;
1394	1394
1395		context->sample_step = 1.0 / d~~isc_~~info->sample_rate;
	1395	context->sample_step = 1.0 / node->info->sample_rate;
1396	1396	context->flip_flop = 1;
1397	1397
1398	1398	/* Do the intial time shift and convert freq to off/on times */
r5534	r5535
1430	1430	* input5 - Initial Time Shift
1431	1431	*
1432	1432	************************************************************************/
1433		#define DSS_SQUAREWAVE2__ENABLE (*(node->input[0]))
1434		#define DSS_SQUAREWAVE2__AMP (*(node->input[1]))
1435		#define DSS_SQUAREWAVE2__T_OFF (*(node->input[2]))
1436		#define DSS_SQUAREWAVE2__T_ON (*(node->input[3]))
1437		#define DSS_SQUAREWAVE2__BIAS (*(node->input[4]))
1438		#define DSS_SQUAREWAVE2__SHIFT (*(node->input[5]))
	1433	#define DSS_SQUAREWAVE2__ENABLE DISCRETE_INPUT(0)
	1434	#define DSS_SQUAREWAVE2__AMP DISCRETE_INPUT(1)
	1435	#define DSS_SQUAREWAVE2__T_OFF DISCRETE_INPUT(2)
	1436	#define DSS_SQUAREWAVE2__T_ON DISCRETE_INPUT(3)
	1437	#define DSS_SQUAREWAVE2__BIAS DISCRETE_INPUT(4)
	1438	#define DSS_SQUAREWAVE2__SHIFT DISCRETE_INPUT(5)
1439	1439
1440	1440	static DISCRETE_STEP(dss_squarewave2)
1441	1441	{
r5534	r5535
1454	1454	/* phase step = 2Pi/(output period/sample period) */
1455	1455	/* boils out to */
1456	1456	/* phase step = 2Pi/(output periodsample freq) /
1457		newphase = context->phase + ((2.0 * M_PI) / ((DSS_SQUAREWAVE2__T_OFF + DSS_SQUAREWAVE2__T_ON) * d~~isc_~~info->sample_rate));
	1457	newphase = context->phase + ((2.0 * M_PI) / ((DSS_SQUAREWAVE2__T_OFF + DSS_SQUAREWAVE2__T_ON) * node->info->sample_rate));
1458	1458	/* Keep the new phasor in the 2Pi range.*/
1459	1459	context->phase = fmod(newphase, 2.0 * M_PI);
1460	1460
r5534	r5535
1501	1501	* input4 - Desc
1502	1502	*
1503	1503	************************************************************************/
1504		#define DSS_INVERTER_OSC__ENABLE (*(node->input[0]))
1505		#define DSS_INVERTER_OSC__MOD (*(node->input[1]))
1506		#define DSS_INVERTER_OSC__RC (*(node->input[2]))
1507		#define DSS_INVERTER_OSC__RP (*(node->input[3]))
1508		#define DSS_INVERTER_OSC__C (*(node->input[4]))
1509		#define DSS_INVERTER_OSC__R2 (*(node->input[5]))
	1504	#define DSS_INVERTER_OSC__ENABLE DISCRETE_INPUT(0)
	1505	#define DSS_INVERTER_OSC__MOD DISCRETE_INPUT(1)
	1506	#define DSS_INVERTER_OSC__RC DISCRETE_INPUT(2)
	1507	#define DSS_INVERTER_OSC__RP DISCRETE_INPUT(3)
	1508	#define DSS_INVERTER_OSC__C DISCRETE_INPUT(4)
	1509	#define DSS_INVERTER_OSC__R2 DISCRETE_INPUT(5)
1510	1510
1511	1511	INLINE double dss_inverter_tftab(node_description *node, double x)
1512	1512	{
r5534	r5535
1607	1607	vMix = rMix* ( (vG3-vG2) / context->r1 + (DSS_INVERTER_OSC__MOD-vG2) / context->r2 + (vI-0.7-vG2)/context->rp);
1608	1608	}
1609	1609	diff = vMix - context->v_cap;
1610		diff = diff - diff * exp(-d~~isc_~~info->sample_time / (context->c * rMix));
	1610	diff = diff - diff * exp(-node->info->sample_time / (context->c * rMix));
1611	1611	break;
1612	1612	case DISC_OSC_INVERTER_IS_TYPE5:
1613	1613	if ((info->clamp >= 0.0) && ((vI< - info->clamp) \|\| (vI> info->vB+info->clamp)))
r5534	r5535
1625	1625	vMix = rMix* ( (vG3 - vG2) / context->r1 + (DSS_INVERTER_OSC__MOD-vG2) / context->r2 + (vI+0.7-vG2)/context->rp);
1626	1626	}
1627	1627	diff = vMix - context->v_cap;
1628		diff = diff - diff * exp(-d~~isc_~~info->sample_time/(context->c * rMix));
	1628	diff = diff - diff * exp(-node->info->sample_time/(context->c * rMix));
1629	1629	break;
1630	1630	default:
1631	1631	fatalerror("DISCRETE_INVERTER_OSC - Wrong type on NODE_%02d", node->node - NODE_00);
r5534	r5535
1648	1648	int i;
1649	1649
1650	1650	/* exponent */
1651		context->w = exp(-disc_info->sample_time / (DSS_INVERTER_OSC__RC * DSS_INVERTER_OSC__C));
1652		context->wc = exp(-disc_info->sample_time / ((DSS_INVERTER_OSC__RC * DSS_INVERTER_OSC__RP) / (DSS_INVERTER_OSC__RP + DSS_INVERTER_OSC__RC) * DSS_INVERTER_OSC__C));
	1651	context->w = exp(-node->info->sample_time / (DSS_INVERTER_OSC__RC * DSS_INVERTER_OSC__C));
	1652	context->wc = exp(-node->info->sample_time / ((DSS_INVERTER_OSC__RC * DSS_INVERTER_OSC__RP) / (DSS_INVERTER_OSC__RP + DSS_INVERTER_OSC__RC) * DSS_INVERTER_OSC__C));
1653	1653	node->output[0] = 0;
1654	1654	context->v_cap = 0;
1655	1655	context->v_g2_old = 0;
r5534	r5535
1678	1678	* input4 - Initial Phase
1679	1679	*
1680	1680	************************************************************************/
1681		#define DSS_TRIANGLEWAVE__ENABLE (*(node->input[0]))
1682		#define DSS_TRIANGLEWAVE__FREQ (*(node->input[1]))
1683		#define DSS_TRIANGLEWAVE__AMP (*(node->input[2]))
1684		#define DSS_TRIANGLEWAVE__BIAS (*(node->input[3]))
1685		#define DSS_TRIANGLEWAVE__PHASE (*(node->input[4]))
	1681	#define DSS_TRIANGLEWAVE__ENABLE DISCRETE_INPUT(0)
	1682	#define DSS_TRIANGLEWAVE__FREQ DISCRETE_INPUT(1)
	1683	#define DSS_TRIANGLEWAVE__AMP DISCRETE_INPUT(2)
	1684	#define DSS_TRIANGLEWAVE__BIAS DISCRETE_INPUT(3)
	1685	#define DSS_TRIANGLEWAVE__PHASE DISCRETE_INPUT(4)
1686	1686
1687	1687	static DISCRETE_STEP(dss_trianglewave)
1688	1688	{
r5534	r5535
1708	1708	/* boils out to */
1709	1709	/* phase step = (2Pioutput freq)/sample freq) /
1710	1710	/* Also keep the new phasor in the 2Pi range. */
1711		context->phase=fmod((context->phase + ((2.0 * M_PI * DSS_TRIANGLEWAVE__FREQ) / d~~isc_~~info->sample_rate)), 2.0 * M_PI);
	1711	context->phase=fmod((context->phase + ((2.0 * M_PI * DSS_TRIANGLEWAVE__FREQ) / node->info->sample_rate)), 2.0 * M_PI);
1712	1712	}
1713	1713
1714	1714	static DISCRETE_RESET(dss_trianglewave)
r5534	r5535
1735	1735	* input2 - gain scaling factor
1736	1736	*
1737	1737	************************************************************************/
1738		#define DSS_ADSR__ENABLE (*(node->input[0]))
	1738	#define DSS_ADSR__ENABLE DISCRETE_INPUT(0)
1739	1739
1740	1740	static DISCRETE_STEP(dss_adsrenv)
1741	1741	{

src/emu/sound/disc_flt.c
r5534	r5535
73	73	double exponent0;
74	74	double exponent1;
75	75	double v_cap; /* rcdisc5 */
	76	double v_diode; /* rcdisc3 */
76	77	};
77	78
78	79	struct dst_rcdisc_mod_context
r5534	r5535
134	135	* input[4] - Voltage reference. Usually 0V.
135	136	*
136	137	************************************************************************/
137		#define DST_CRFILTER__ENABLE (*(node->input[0]))
138		#define DST_CRFILTER__IN (*(node->input[1]))
139		#define DST_CRFILTER__R (*(node->input[2]))
140		#define DST_CRFILTER__C (*(node->input[3]))
141		#define DST_CRFILTER__VREF (*(node->input[4]))
	138	#define DST_CRFILTER__ENABLE DISCRETE_INPUT(0)
	139	#define DST_CRFILTER__IN DISCRETE_INPUT(1)
	140	#define DST_CRFILTER__R DISCRETE_INPUT(2)
	141	#define DST_CRFILTER__C DISCRETE_INPUT(3)
	142	#define DST_CRFILTER__VREF DISCRETE_INPUT(4)
142	143
143	144	static DISCRETE_STEP(dst_crfilter)
144	145	{
r5534	r5535
175	176	* input[3] - Filter type (initialization only)
176	177	*
177	178	************************************************************************/
178		#define DST_FILTER1__ENABLE (*(node->input[0]))
179		#define DST_FILTER1__IN (*(node->input[1]))
180		#define DST_FILTER1__FREQ (*(node->input[2]))
181		#define DST_FILTER1__TYPE (*(node->input[3]))
	179	#define DST_FILTER1__ENABLE DISCRETE_INPUT(0)
	180	#define DST_FILTER1__IN DISCRETE_INPUT(1)
	181	#define DST_FILTER1__FREQ DISCRETE_INPUT(2)
	182	#define DST_FILTER1__TYPE DISCRETE_INPUT(3)
182	183
183	184	static void calculate_filter1_coefficients(const discrete_info *disc_info, double fc, double type,
184	185	double a1, double b0, double *b1)
r5534	r5535
228	229	{
229	230	struct dss_filter1_context context = (struct dss_filter1_context )node->context;
230	231
231		calculate_filter1_coefficients(d~~isc_~~info, DST_FILTER1__FREQ, DST_FILTER1__TYPE, &context->a1, &context->b0, &context->b1);
	232	calculate_filter1_coefficients(node->info, DST_FILTER1__FREQ, DST_FILTER1__TYPE, &context->a1, &context->b0, &context->b1);
232	233	node->output[0] = 0;
233	234	}
234	235
r5534	r5535
244	245	* input[4] - Filter type (initialization only)
245	246	*
246	247	************************************************************************/
247		#define DST_FILTER2__ENABLE (*(node->input[0]))
248		#define DST_FILTER2__IN (*(node->input[1]))
249		#define DST_FILTER2__FREQ (*(node->input[2]))
250		#define DST_FILTER2__DAMP (*(node->input[3]))
251		#define DST_FILTER2__TYPE (*(node->input[4]))
	248	#define DST_FILTER2__ENABLE DISCRETE_INPUT(0)
	249	#define DST_FILTER2__IN DISCRETE_INPUT(1)
	250	#define DST_FILTER2__FREQ DISCRETE_INPUT(2)
	251	#define DST_FILTER2__DAMP DISCRETE_INPUT(3)
	252	#define DST_FILTER2__TYPE DISCRETE_INPUT(4)
252	253
253	254	static void calculate_filter2_coefficients(const discrete_info *disc_info,
254	255	double fc, double d, double type,
r5534	r5535
258	259	double w; /* cutoff freq, in radians/sec */
259	260	double w_squared;
260	261	double den; /* temp variable */
261		double two_over_T = 2*disc_info->sample_rate;
	262	double two_over_T = 2 * disc_info->sample_rate;
262	263	double two_over_T_squared = two_over_T * two_over_T;
263	264
264	265	/* calculate digital filter coefficents */
r5534	r5535
317	318	{
318	319	struct dss_filter2_context context = (struct dss_filter2_context )node->context;
319	320
320		calculate_filter2_coefficients(d~~isc_~~info, DST_FILTER2__FREQ, DST_FILTER2__DAMP, DST_FILTER2__TYPE,
	321	calculate_filter2_coefficients(node->info, DST_FILTER2__FREQ, DST_FILTER2__DAMP, DST_FILTER2__TYPE,
321	322	&context->a1, &context->a2,
322	323	&context->b0, &context->b1, &context->b2);
323	324	node->output[0] = 0;
r5534	r5535
337	338	*
338	339	* Mar 2004, D Renaud.
339	340	************************************************************************/
340		#define DST_OP_AMP_FILT__ENABLE (*(node->input[0]))
341		#define DST_OP_AMP_FILT__INP1 (*(node->input[1]))
342		#define DST_OP_AMP_FILT__INP2 (*(node->input[2]))
343		#define DST_OP_AMP_FILT__TYPE (*(node->input[3]))
	341	#define DST_OP_AMP_FILT__ENABLE DISCRETE_INPUT(0)
	342	#define DST_OP_AMP_FILT__INP1 DISCRETE_INPUT(1)
	343	#define DST_OP_AMP_FILT__INP2 DISCRETE_INPUT(2)
	344	#define DST_OP_AMP_FILT__TYPE DISCRETE_INPUT(3)
344	345
345	346	static DISCRETE_STEP(dst_op_amp_filt)
346	347	{
r5534	r5535
360	361	{
361	362	/* Millman the input voltages. */
362	363	i = context->iFixed;
363		i += (DST_OP_AMP_FILT__INP1 - context->vRef) / info->r1;
364		if (info->r2 != 0)
365		i += (DST_OP_AMP_FILT__INP2 - context->vRef) / info->r2;
	364	switch (context->type)
	365	{
	366	case DISC_OP_AMP_FILTER_IS_LOW_PASS_1M:
	367	i += (DST_OP_AMP_FILT__INP1 - DST_OP_AMP_FILT__INP2) / info->r1;
	368	if (info->r2 != 0)
	369	i += (context->vP - DST_OP_AMP_FILT__INP2) / info->r2;
	370	if (info->r3 != 0)
	371	i += (context->vN - DST_OP_AMP_FILT__INP2) / info->r3;
	372	break;
	373	default:
	374	i += (DST_OP_AMP_FILT__INP1 - context->vRef) / info->r1;
	375	if (info->r2 != 0)
	376	i += (DST_OP_AMP_FILT__INP2 - context->vRef) / info->r2;
	377	break;
	378	}
366	379	v = i * context->rTotal;
367	380	}
368	381
r5534	r5535
373	386	node->output[0] = context->vC1 * context->gain + info->vRef;
374	387	break;
375	388
	389	case DISC_OP_AMP_FILTER_IS_LOW_PASS_1M:
	390	context->vC1 += (v - context->vC1) * context->exponentC1;
	391	node->output[0] = context->vC1 * context->gain + DST_OP_AMP_FILT__INP2;
	392	break;
	393
376	394	case DISC_OP_AMP_FILTER_IS_HIGH_PASS_1:
377	395	node->output[0] = (v - context->vC1) * context->gain + info->vRef;
378	396	context->vC1 += (v - context->vC1) * context->exponentC1;
r5534	r5535
470	488	switch (context->type)
471	489	{
472	490	case DISC_OP_AMP_FILTER_IS_LOW_PASS_1:
	491	case DISC_OP_AMP_FILTER_IS_LOW_PASS_1M:
473	492	context->exponentC1 = RC_CHARGE_EXP(info->rF * info->c1);
474	493	context->exponentC2 = 0;
475	494	break;
r5534	r5535
489	508	double d = (info->c1 + info->c2) / sqrt(info->rF / context->rTotal * info->c1 * info->c2);
490	509	double gain = -info->rF / context->rTotal * info->c2 / (info->c1 + info->c2);
491	510
492		calculate_filter2_coefficients(d~~isc_~~info, fc, d, DISC_FILTER_BANDPASS,
	511	calculate_filter2_coefficients(node->info, fc, d, DISC_FILTER_BANDPASS,
493	512	&context->a1, &context->a2,
494	513	&context->b0, &context->b1, &context->b2);
495	514	context->b0 *= gain;
r5534	r5535
534	553	* input[3] - Capacitor Value (initialization only)
535	554	*
536	555	************************************************************************/
537		#define DST_RCDISC__ENABLE (*(node->input[0]))
538		#define DST_RCDISC__IN (*(node->input[1]))
539		#define DST_RCDISC__R (*(node->input[2]))
540		#define DST_RCDISC__C (*(node->input[3]))
	556	#define DST_RCDISC__ENABLE DISCRETE_INPUT(0)
	557	#define DST_RCDISC__IN DISCRETE_INPUT(1)
	558	#define DST_RCDISC__R DISCRETE_INPUT(2)
	559	#define DST_RCDISC__C DISCRETE_INPUT(3)
541	560
542	561	static DISCRETE_STEP(dst_rcdisc)
543	562	{
r5534	r5535
558	577	if (DST_RCDISC__ENABLE)
559	578	{
560	579	node->output[0] = DST_RCDISC__IN * exp(context->t / context->exponent0);
561		context->t += d~~isc_~~info->sample_time;
	580	context->t += node->info->sample_time;
562	581	} else
563	582	{
564	583	context->state = 0;
r5534	r5535
591	610	* input[5] - Capacitor Value (initialization only)
592	611	*
593	612	************************************************************************/
594		#define DST_RCDISC2__ENABLE (*(node->input[0]))
595		#define DST_RCDISC2__IN0 (*(node->input[1]))
596		#define DST_RCDISC2__R0 (*(node->input[2]))
597		#define DST_RCDISC2__IN1 (*(node->input[3]))
598		#define DST_RCDISC2__R1 (*(node->input[4]))
599		#define DST_RCDISC2__C (*(node->input[5]))
	613	#define DST_RCDISC2__ENABLE DISCRETE_INPUT(0)
	614	#define DST_RCDISC2__IN0 DISCRETE_INPUT(1)
	615	#define DST_RCDISC2__R0 DISCRETE_INPUT(2)
	616	#define DST_RCDISC2__IN1 DISCRETE_INPUT(3)
	617	#define DST_RCDISC2__R1 DISCRETE_INPUT(4)
	618	#define DST_RCDISC2__C DISCRETE_INPUT(5)
600	619
601	620	static DISCRETE_STEP(dst_rcdisc2)
602	621	{
r5534	r5535
634	653	* input[2] - Resistor0 value (initialization only)
635	654	* input[4] - Resistor1 value (initialization only)
636	655	* input[5] - Capacitor Value (initialization only)
	656	* input[6] - Diode Junction voltage (initialization only)
637	657	*
638	658	************************************************************************/
639		#define DST_RCDISC3__ENABLE (*(node->input[0]))
640		#define DST_RCDISC3__IN (*(node->input[1]))
641		#define DST_RCDISC3__R1 (*(node->input[2]))
642		#define DST_RCDISC3__R2 (*(node->input[3]))
643		#define DST_RCDISC3__C (*(node->input[4]))
	659	#define DST_RCDISC3__ENABLE DISCRETE_INPUT(0)
	660	#define DST_RCDISC3__IN DISCRETE_INPUT(1)
	661	#define DST_RCDISC3__R1 DISCRETE_INPUT(2)
	662	#define DST_RCDISC3__R2 DISCRETE_INPUT(3)
	663	#define DST_RCDISC3__C DISCRETE_INPUT(4)
	664	#define DST_RCDISC3__DJV DISCRETE_INPUT(6)
644	665
645	666	static DISCRETE_STEP(dst_rcdisc3)
646	667	{
r5534	r5535
653	674	if(DST_RCDISC3__ENABLE)
654	675	{
655	676	diff = DST_RCDISC3__IN - node->output[0];
656		if( diff > 0 )
	677	if (context->v_diode > 0)
657	678	{
658		diff = diff - (diff * context->exponent0);
659		} else if( diff < 0)
	679	if( diff > 0 )
	680	{
	681	diff = diff - (diff * context->exponent0);
	682	} else if( diff < 0)
	683	{
	684	if(diff < -context->v_diode)
	685	diff = diff - (diff * context->exponent1);
	686	else
	687	diff = diff - (diff * context->exponent0);
	688	}
	689	}
	690	else
660	691	{
661		if(diff < -0.5)
662		diff = diff - (diff * context->exponent1);
663		else
	692	if( diff < 0 )
	693	{
664	694	diff = diff - (diff * context->exponent0);
	695	} else if( diff > 0)
	696	{
	697	if(diff > -context->v_diode)
	698	diff = diff - (diff * context->exponent1);
	699	else
	700	diff = diff - (diff * context->exponent0);
	701	}
665	702	}
666	703	node->output[0] += diff;
667	704	}
r5534	r5535
679	716
680	717	context->state = 0;
681	718	context->t = 0;
	719	context->v_diode = DST_RCDISC3__DJV;
682	720	context->exponent0 = RC_CHARGE_EXP(DST_RCDISC3__R1 * DST_RCDISC3__C);
683	721	context->exponent1 = RC_CHARGE_EXP(RES_2_PARALLEL(DST_RCDISC3__R1, DST_RCDISC3__R2) * DST_RCDISC3__C);
684	722	}
r5534	r5535
697	735	* input[4] - circuit type (initialization only)
698	736	*
699	737	************************************************************************/
700		#define DST_RCDISC4__ENABLE (*(node->input[0]))
701		#define DST_RCDISC4__IN (*(node->input[1]))
702		#define DST_RCDISC4__R1 (*(node->input[2]))
703		#define DST_RCDISC4__R2 (*(node->input[3]))
704		#define DST_RCDISC4__R3 (*(node->input[4]))
705		#define DST_RCDISC4__C1 (*(node->input[5]))
706		#define DST_RCDISC4__VP (*(node->input[6]))
707		#define DST_RCDISC4__TYPE (*(node->input[7]))
	738	#define DST_RCDISC4__ENABLE DISCRETE_INPUT(0)
	739	#define DST_RCDISC4__IN DISCRETE_INPUT(1)
	740	#define DST_RCDISC4__R1 DISCRETE_INPUT(2)
	741	#define DST_RCDISC4__R2 DISCRETE_INPUT(3)
	742	#define DST_RCDISC4__R3 DISCRETE_INPUT(4)
	743	#define DST_RCDISC4__C1 DISCRETE_INPUT(5)
	744	#define DST_RCDISC4__VP DISCRETE_INPUT(6)
	745	#define DST_RCDISC4__TYPE DISCRETE_INPUT(7)
708	746
709	747	static DISCRETE_STEP(dst_rcdisc4)
710	748	{
r5534	r5535
742	780	/* some error checking. */
743	781	if (DST_RCDISC4__R1 <= 0 \|\| DST_RCDISC4__R2 <= 0 \|\| DST_RCDISC4__C1 <= 0 \|\| (DST_RCDISC4__R3 <= 0 && context->type == 1))
744	782	{
745		discrete_log(d~~isc_~~info, "Invalid component values in NODE_%d.\n", node->node - NODE_00);
	783	discrete_log(node->info, "Invalid component values in NODE_%d.\n", node->node - NODE_00);
746	784	return;
747	785	}
748	786	if (DST_RCDISC4__VP < 3)
749	787	{
750		discrete_log(d~~isc_~~info, "vP must be >= 3V in NODE_%d.\n", node->node - NODE_00);
	788	discrete_log(node->info, "vP must be >= 3V in NODE_%d.\n", node->node - NODE_00);
751	789	return;
752	790	}
753	791	if (DST_RCDISC4__TYPE < 1 \|\| DST_RCDISC4__TYPE > 3)
754	792	{
755		discrete_log(d~~isc_~~info, "Invalid circuit type in NODE_%d.\n", node->node - NODE_00);
	793	discrete_log(node->info, "Invalid circuit type in NODE_%d.\n", node->node - NODE_00);
756	794	return;
757	795	}
758	796
r5534	r5535
813	851	* input[3] - Capacitor Value (initialization only)
814	852	*
815	853	************************************************************************/
816		#define DST_RCDISC5__ENABLE (*(node->input[0]))
817		#define DST_RCDISC5__IN (*(node->input[1]))
818		#define DST_RCDISC5__R (*(node->input[2]))
819		#define DST_RCDISC5__C (*(node->input[3]))
	854	#define DST_RCDISC5__ENABLE DISCRETE_INPUT(0)
	855	#define DST_RCDISC5__IN DISCRETE_INPUT(1)
	856	#define DST_RCDISC5__R DISCRETE_INPUT(2)
	857	#define DST_RCDISC5__C DISCRETE_INPUT(3)
820	858
821	859	static DISCRETE_STEP( dst_rcdisc5)
822	860	{
r5534	r5535
877	915	* input[8] - Voltage Value (initialization only)
878	916	*
879	917	************************************************************************/
880		#define DST_RCDISC_MOD__IN1 (*(node->input[0]))
881		#define DST_RCDISC_MOD__IN2 (*(node->input[1]))
882		#define DST_RCDISC_MOD__R1 (*(node->input[2]))
883		#define DST_RCDISC_MOD__R2 (*(node->input[3]))
884		#define DST_RCDISC_MOD__R3 (*(node->input[4]))
885		#define DST_RCDISC_MOD__R4 (*(node->input[5]))
886		#define DST_RCDISC_MOD__C (*(node->input[6]))
887		#define DST_RCDISC_MOD__VP (*(node->input[7]))
	918	#define DST_RCDISC_MOD__IN1 DISCRETE_INPUT(0)
	919	#define DST_RCDISC_MOD__IN2 DISCRETE_INPUT(1)
	920	#define DST_RCDISC_MOD__R1 DISCRETE_INPUT(2)
	921	#define DST_RCDISC_MOD__R2 DISCRETE_INPUT(3)
	922	#define DST_RCDISC_MOD__R3 DISCRETE_INPUT(4)
	923	#define DST_RCDISC_MOD__R4 DISCRETE_INPUT(5)
	924	#define DST_RCDISC_MOD__C DISCRETE_INPUT(6)
	925	#define DST_RCDISC_MOD__VP DISCRETE_INPUT(7)
888	926
889	927	static DISCRETE_STEP(dst_rcdisc_mod)
890	928	{
r5534	r5535
970	1008	* input[4] - Voltage reference. Usually 0V.
971	1009	*
972	1010	************************************************************************/
973		#define DST_RCFILTER__ENABLE (*(node->input[0]))
974		#define DST_RCFILTER__VIN (*(node->input[1]))
975		#define DST_RCFILTER__R (*(node->input[2]))
976		#define DST_RCFILTER__C (*(node->input[3]))
977		#define DST_RCFILTER__VREF (*(node->input[4]))
	1011	#define DST_RCFILTER__ENABLE DISCRETE_INPUT(0)
	1012	#define DST_RCFILTER__VIN DISCRETE_INPUT(1)
	1013	#define DST_RCFILTER__R DISCRETE_INPUT(2)
	1014	#define DST_RCFILTER__C DISCRETE_INPUT(3)
	1015	#define DST_RCFILTER__VREF DISCRETE_INPUT(4)
978	1016
979	1017	static DISCRETE_STEP(dst_rcfilter)
980	1018	{
r5534	r5535
1015	1053	* input[4] - Voltage reference. Usually 0V.
1016	1054	*
1017	1055	************************************************************************/
1018		#define DST_RCFILTER_SW__ENABLE (*(node->input[0]))
1019		#define DST_RCFILTER_SW__VIN (*(node->input[1]))
1020		#define DST_RCFILTER_SW__SWITCH (*(node->input[2]))
1021		#define DST_RCFILTER_SW__R (*(node->input[3]))
1022		#define DST_RCFILTER_SW__C(x) (*(node->input[4+x]))
	1056	#define DST_RCFILTER_SW__ENABLE DISCRETE_INPUT(0)
	1057	#define DST_RCFILTER_SW__VIN DISCRETE_INPUT(1)
	1058	#define DST_RCFILTER_SW__SWITCH DISCRETE_INPUT(2)
	1059	#define DST_RCFILTER_SW__R DISCRETE_INPUT(3)
	1060	#define DST_RCFILTER_SW__C(x) DISCRETE_INPUT(4+x)
1023	1061
1024	1062	#define CD4066_ON_RES 270
1025	1063	#define DST_RCFILTER_SW_ITERATIONS (10)
r5534	r5535
1032	1070	int i,j ;
1033	1071	int bits = (int)DST_RCFILTER_SW__SWITCH;
1034	1072	double us = 0, rs = 0;
	1073	double vd;
	1074	double rt;
1035	1075
1036	1076	if (DST_RCFILTER_SW__ENABLE)
1037	1077	{
r5534	r5535
1048	1088	context->vCap[1] += (DST_RCFILTER_SW__VIN - context->vCap[1]) * context->exp1;
1049	1089	node->output[0] = context->vCap[1] + (DST_RCFILTER_SW__VIN - context->vCap[1]) * context->factor;
1050	1090	break;
	1091	case 3:
	1092	rs = 2 * DST_RCFILTER_SW__R;
	1093	vd = RES_VOLTAGE_DIVIDER(rs, CD4066_ON_RES) * DST_RCFILTER_SW__VIN;
	1094	rt = DST_RCFILTER_SW__R / (CD4066_ON_RES + rs);
	1095
	1096	for (j = 0; j < DST_RCFILTER_SW_ITERATIONS; j++)
	1097	{
	1098	node->output[0] = vd + rt * (context->vCap[0] + context->vCap[1]);
	1099	context->vCap[0] += (node->output[0] - context->vCap[0]) * context->exp[0];
	1100	context->vCap[1] += (node->output[0] - context->vCap[1]) * context->exp[1];
	1101	}
	1102	break;
1051	1103	default:
	1104	rs = 0;
	1105
	1106	for (i = 0; i < 4; i++)
	1107	{
	1108	if (( bits & (1 << i)) != 0)
	1109	{
	1110	rs += DST_RCFILTER_SW__R;
	1111	}
	1112	}
	1113
	1114	vd = RES_VOLTAGE_DIVIDER(rs, CD4066_ON_RES) * DST_RCFILTER_SW__VIN;
	1115	rt = DST_RCFILTER_SW__R / (CD4066_ON_RES + rs);
	1116
1052	1117	for (j = 0; j < DST_RCFILTER_SW_ITERATIONS; j++)
1053	1118	{
	1119	us = 0;
1054	1120	for (i = 0; i < 4; i++)
1055	1121	{
1056	1122	if (( bits & (1 << i)) != 0)
1057	1123	{
1058	1124	us += context->vCap[i];
1059		rs += DST_RCFILTER_SW__R;
1060	1125	}
1061	1126	}
1062		node->output[0] = ~~RES_VOLTAGE_DIVIDER(rs,~~ ~~CD4066_ON_RES) * DST_RCFILTER_SW__VIN~~ + ~~DST_RCFILTER_SW__R / (CD4066_ON_RES +~~ rs) * us;
	1127	node->output[0] = vd + rt * us;
1063	1128	for (i = 0; i < 4; i++)
1064	1129	{
1065	1130	if (( bits & (1 << i)) != 0)
r5534	r5535
1108	1173	* input[5] - Capacitor Value (initialization only)
1109	1174	*
1110	1175	************************************************************************/
1111		#define DST_RCINTEGRATE__IN1 (*(node->input[0]))
1112		#define DST_RCINTEGRATE__R1 (*(node->input[1]))
1113		#define DST_RCINTEGRATE__R2 (*(node->input[2]))
1114		#define DST_RCINTEGRATE__R3 (*(node->input[3]))
1115		#define DST_RCINTEGRATE__C (*(node->input[4]))
1116		#define DST_RCINTEGRATE__VP (*(node->input[5]))
1117		#define DST_RCINTEGRATE__TYPE (*(node->input[6]))
	1176	#define DST_RCINTEGRATE__IN1 DISCRETE_INPUT(0)
	1177	#define DST_RCINTEGRATE__R1 DISCRETE_INPUT(1)
	1178	#define DST_RCINTEGRATE__R2 DISCRETE_INPUT(2)
	1179	#define DST_RCINTEGRATE__R3 DISCRETE_INPUT(3)
	1180	#define DST_RCINTEGRATE__C DISCRETE_INPUT(4)
	1181	#define DST_RCINTEGRATE__VP DISCRETE_INPUT(5)
	1182	#define DST_RCINTEGRATE__TYPE DISCRETE_INPUT(6)
1118	1183
1119	1184	/* Ebers-Moll large signal model
1120	1185	* Couriersud:
r5534	r5535
1198	1263	struct dst_rcintegrate_context context = (struct dst_rcintegrate_context )node->context;
1199	1264
1200	1265	double r;
1201		double dt = d~~isc_~~info->sample_time;
	1266	double dt = node->info->sample_time;
1202	1267
1203	1268	context->type = DST_RCINTEGRATE__TYPE;
1204	1269
r5534	r5535
1233	1298	*
1234	1299	* 2008, couriersud
1235	1300	************************************************************************/
1236		#define DST_SALLEN_KEY__ENABLE (*(node->input[0]))
1237		#define DST_SALLEN_KEY__INP0 (*(node->input[1]))
1238		#define DST_SALLEN_KEY__TYPE (*(node->input[2]))
	1301	#define DST_SALLEN_KEY__ENABLE DISCRETE_INPUT(0)
	1302	#define DST_SALLEN_KEY__INP0 DISCRETE_INPUT(1)
	1303	#define DST_SALLEN_KEY__TYPE DISCRETE_INPUT(2)
1239	1304
1240	1305	static DISCRETE_STEP(dst_sallen_key)
1241	1306	{
r5534	r5535
1274	1339	fatalerror("Unknown sallen key filter type");
1275	1340	}
1276	1341
1277		calculate_filter2_coefficients(d~~isc_~~info, freq, 1.0 / q, DISC_FILTER_LOWPASS,
	1342	calculate_filter2_coefficients(node->info, freq, 1.0 / q, DISC_FILTER_LOWPASS,
1278	1343	&context->a1, &context->a2,
1279	1344	&context->b0, &context->b1, &context->b2);
1280	1345	node->output[0] = 0;
r5534	r5535
1294	1359	* input[3] - Capacitor Value (initialization only)
1295	1360	*
1296	1361	************************************************************************/
1297		#define DST_RCFILTERN__ENABLE (*(node->input[0]))
1298		#define DST_RCFILTERN__IN (*(node->input[1]))
1299		#define DST_RCFILTERN__R (*(node->input[2]))
1300		#define DST_RCFILTERN__C (*(node->input[3]))
	1362	#define DST_RCFILTERN__ENABLE DISCRETE_INPUT(0)
	1363	#define DST_RCFILTERN__IN DISCRETE_INPUT(1)
	1364	#define DST_RCFILTERN__R DISCRETE_INPUT(2)
	1365	#define DST_RCFILTERN__C DISCRETE_INPUT(3)
1301	1366
1302	1367	static DISCRETE_RESET(dst_rcfilterN)
1303	1368	{
r5534	r5535
1327	1392	* input[3] - Capacitor Value (initialization only)
1328	1393	*
1329	1394	************************************************************************/
1330		#define DST_RCDISCN__ENABLE (*(node->input[0]))
1331		#define DST_RCDISCN__IN (*(node->input[1]))
1332		#define DST_RCDISCN__R (*(node->input[2]))
1333		#define DST_RCDISCN__C (*(node->input[3]))
	1395	#define DST_RCDISCN__ENABLE DISCRETE_INPUT(0)
	1396	#define DST_RCDISCN__IN DISCRETE_INPUT(1)
	1397	#define DST_RCDISCN__R DISCRETE_INPUT(2)
	1398	#define DST_RCDISCN__C DISCRETE_INPUT(3)
1334	1399
1335	1400	static DISCRETE_RESET(dst_rcdiscN)
1336	1401	{
r5534	r5535
1384	1449	* input[5] - Capacitor Value (initialization only)
1385	1450	*
1386	1451	************************************************************************/
1387		#define DST_RCDISC2N__ENABLE (*(node->input[0]))
1388		#define DST_RCDISC2N__IN0 (*(node->input[1]))
1389		#define DST_RCDISC2N__R0 (*(node->input[2]))
1390		#define DST_RCDISC2N__IN1 (*(node->input[3]))
1391		#define DST_RCDISC2N__R1 (*(node->input[4]))
1392		#define DST_RCDISC2N__C (*(node->input[5]))
	1452	#define DST_RCDISC2N__ENABLE DISCRETE_INPUT(0)
	1453	#define DST_RCDISC2N__IN0 DISCRETE_INPUT(1)
	1454	#define DST_RCDISC2N__R0 DISCRETE_INPUT(2)
	1455	#define DST_RCDISC2N__IN1 DISCRETE_INPUT(3)
	1456	#define DST_RCDISC2N__R1 DISCRETE_INPUT(4)
	1457	#define DST_RCDISC2N__C DISCRETE_INPUT(5)
1393	1458
1394	1459	struct dss_rcdisc2_context
1395	1460	{
r5534	r5535
1422	1487	f1 = 1.0 / (2 * M_PI * DST_RCDISC2N__R0 * DST_RCDISC2N__C);
1423	1488	f2 = 1.0 / (2 * M_PI * DST_RCDISC2N__R1 * DST_RCDISC2N__C);
1424	1489
1425		calculate_filter1_coefficients(disc_info, f1, DISC_FILTER_LOWPASS, &context->a1_0, &context->b0_0, &context->b1_0);
1426		calculate_filter1_coefficients(disc_info, f2, DISC_FILTER_LOWPASS, &context->a1_1, &context->b0_1, &context->b1_1);
	1490	calculate_filter1_coefficients(node->info, f1, DISC_FILTER_LOWPASS, &context->a1_0, &context->b0_0, &context->b1_0);
	1491	calculate_filter1_coefficients(node->info, f2, DISC_FILTER_LOWPASS, &context->a1_1, &context->b0_1, &context->b1_1);
1427	1492
1428	1493	/* Initialize the object */
1429	1494	node->output[0] = 0;

src/mess/tools/messtest/messtest.mak
r5534	r5535
37	37
38	38	#$(MESSTEST_OBJS): maketree
39	39
40		$(MESSTEST): $(VERSIONOBJ) $(MESSTEST_OBJS) $(LIBIMGTOOL) $(DRVLIBS) $(LIBEMU) $(LIBCPU) $(LIBSOUND) $(LIBUTIL) $(EXPAT) $(ZLIB) $(LIBOCORE)
	40	$(MESSTEST): $(VERSIONOBJ) $(MESSTEST_OBJS) $(LIBIMGTOOL) $(DRVLIBS) $(LIBEMU) $(LIBCPU) $(LIBDASM) $(LIBSOUND) $(LIBUTIL) $(EXPAT) $(ZLIB) $(LIBOCORE)
41	41	@echo Linking $@...
42	42	$(LD) $(LDFLAGS) $^ $(LIBS) $(EXPAT) -o $@

src/mess/mess.mak
r5534	r5535
44	44	#-------------------------------------------------
45	45
46	46	CPUS += Z80
47		#CPUS += Z180
	47	CPUS += Z180
48	48	CPUS += I8085
49	49	CPUS += M6502
50	50	CPUS += H6280
r5534	r5535
52	52	CPUS += I386
53	53	CPUS += NEC
54	54	CPUS += V30MZ
55		#CPUS += V60
	55	CPUS += V60
56	56	CPUS += MCS48
57	57	CPUS += MCS51
58	58	CPUS += M6800
59	59	CPUS += M6805
60	60	CPUS += HD6309
61	61	CPUS += M6809
62		#CPUS += KONAMI
	62	CPUS += KONAMI
63	63	CPUS += M680X0
64	64	CPUS += T11
65	65	CPUS += S2650
66		#CPUS += TMS340X0
	66	CPUS += TMS340X0
67	67	CPUS += TMS9900
68	68	CPUS += Z8000
69	69	CPUS += TMS32010
70		#CPUS += TMS32025
71		#CPUS += TMS32031
72		#CPUS += TMS32051
73		#CPUS += TMS57002
74		#CPUS += CCPU
75		#CPUS += ADSP21XX
76		#CPUS += ASAP
	70	CPUS += TMS32025
	71	CPUS += TMS32031
	72	CPUS += TMS32051
	73	CPUS += TMS57002
	74	CPUS += CCPU
	75	CPUS += ADSP21XX
	76	CPUS += ASAP
77	77	CPUS += UPD7810
78	78	CPUS += ARM
79	79	CPUS += ARM7
80	80	CPUS += JAGUAR
81		#CPUS += CUBEQCPU
82		#CPUS += ESRIP
	81	CPUS += CUBEQCPU
	82	CPUS += ESRIP
83	83	CPUS += MIPS
84	84	CPUS += SH2
85	85	CPUS += SH4
86		#CPUS += DSP32C
87		#CPUS += PIC16C5X
	86	CPUS += DSP32C
	87	CPUS += PIC16C5X
88	88	CPUS += G65816
89	89	CPUS += SPC700
90		#CPUS += E1
91		#CPUS += I860
92		#CPUS += I960
	90	CPUS += E1
	91	CPUS += I860
	92	CPUS += I960
93	93	CPUS += H83002
94	94	CPUS += H83334
95	95	CPUS += V810
96		#CPUS += M37710
	96	CPUS += M37710
97	97	CPUS += POWERPC
98		#CPUS += SE3208
99		#CPUS += MC68HC11
100		#CPUS += ADSP21062
101		#CPUS += DSP56156
	98	CPUS += SE3208
	99	CPUS += MC68HC11
	100	CPUS += ADSP21062
	101	CPUS += DSP56156
102	102	CPUS += RSP
103		#CPUS += ALPHA8201
	103	CPUS += ALPHA8201
104	104	CPUS += CDP1802
105	105	CPUS += COP400
106		#CPUS += TLCS90
	106	CPUS += TLCS90
107	107	CPUS += TLCS900
108		#CPUS += MB88XX
109		#CPUS += MB86233
	108	CPUS += MB88XX
	109	CPUS += MB86233
110	110	CPUS += SSP1601
111	111	CPUS += APEXC
112	112	CPUS += CP1610
113	113	CPUS += F8
114		#CPUS += LH5801
	114	CPUS += LH5801
115	115	CPUS += PDP1
116	116	CPUS += SATURN
117	117	CPUS += SC61860
r5534	r5535
123	123	CPUS += AVR8
124	124	CPUS += TMS0980
125	125	CPUS += I4004
	126	CPUS += SUPERFX
126	127
127	128
128	129

src/mess/osd/windows/windows.mak
r5534	r5535
78	78
79	79	EXECUTABLE_DEFINED = 1
80	80
81		$(EMULATORDLL): $(VERSIONOBJ) $(OBJ)/mess/osd/windows/messlib.o $(DRVLIBS) $(LIBOSD) $(LIBEMU) $(LIBCPU) $(LIBSOUND) $(LIBUTIL) $(EXPAT) $(ZLIB) $(LIBOCORE) $(MESS_WINOBJ)/mess.res
	81	$(EMULATORDLL): $(VERSIONOBJ) $(OBJ)/mess/osd/windows/messlib.o $(DRVLIBS) $(LIBOSD) $(LIBEMU) $(LIBCPU) $(LIBDASM) $(LIBSOUND) $(LIBUTIL) $(EXPAT) $(ZLIB) $(LIBOCORE) $(MESS_WINOBJ)/mess.res
82	82	# always recompile the version string
83	83	$(CC) $(CDEFS) $(CFLAGS) -c $(SRC)/version.c -o $(VERSIONOBJ)
84	84	@echo Linking $@...

docs/messnew.txt
r5534	r5535
59	59
60	60	Source Changes:
61	61	----------------
62		- The core is based on MAME 0.133u3. This incorporates all features of the
	62	- The core is based on MAME 0.133u4. This incorporates all features of the
63	63	update to this core. [MAME team]
64	64
65	65

makefile
r5534	r5535
420	420
421	421	LIBEMU = $(OBJ)/libemu.a
422	422	LIBCPU = $(OBJ)/libcpu.a
	423	LIBDASM = $(OBJ)/libdasm.a
423	424	LIBSOUND = $(OBJ)/libsound.a
424	425	LIBUTIL = $(OBJ)/libutil.a
425	426	LIBOCORE = $(OBJ)/libocore.a
r5534	r5535
537	538
538	539	ifndef EXECUTABLE_DEFINED
539	540
540		$(EMULATOR): $(VERSIONOBJ) $(DRVLIBS) $(LIBOSD) $(LIBEMU) $(LIBCPU) $(LIBSOUND) $(LIBUTIL) $(EXPAT) $(ZLIB) $(LIBOCORE) $(RESFILE)
	541	$(EMULATOR): $(VERSIONOBJ) $(DRVLIBS) $(LIBOSD) $(LIBEMU) $(LIBCPU) $(LIBDASM) $(LIBSOUND) $(LIBUTIL) $(EXPAT) $(ZLIB) $(LIBOCORE) $(RESFILE)
541	542	# always recompile the version string
542	543	$(CC) $(CDEFS) $(CFLAGS) -c $(SRC)/version.c -o $(VERSIONOBJ)
543	544	@echo Linking $@...

15994 Revisions