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r5083 Friday 26th June, 2009 at 02:39:07 UTC by Barry Rodewald
[FM77AV] Various MMR improvements, hooked up YM2203 IRQ, added basic 320x200 video mode support.

[src/mess/drivers]	fm7.c
[src/mess/includes]	fm7.h
[src/mess/video]	fm7.c

src/mess/video/fm7.c

r5082	r5083
12	12
13	13	extern UINT8* fm7_video_ram;
14	14	extern emu_timer* fm7_subtimer;
	15	extern UINT8 fm7_type;
15	16
16	17	/*
17	18	* Main CPU: Sub-CPU interface (port 0xfd05)
r5082	r5083
125	126	return;
126	127
127	128	offs = (offset & 0xc000) | ((offset + fm7_video.vram_offset) & 0x3fff);
128		if(fm7_video.vram_access != 0)
	129	//   if(fm7_video.vram_access != 0)
129	130	fm7_video_ram[offs] = data;
130	131	}
131	132
	133	// not pretty, but it should work.
	134	READ8_HANDLER( fm7_vram0_r )
	135	{
	136	return fm7_vram_r(space,offset);
	137	}
	138
	139	READ8_HANDLER( fm7_vram1_r )
	140	{
	141	return fm7_vram_r(space,offset+0x1000);
	142	}
	143
	144	READ8_HANDLER( fm7_vram2_r )
	145	{
	146	return fm7_vram_r(space,offset+0x2000);
	147	}
	148
	149	READ8_HANDLER( fm7_vram3_r )
	150	{
	151	return fm7_vram_r(space,offset+0x3000);
	152	}
	153
	154	READ8_HANDLER( fm7_vram4_r )
	155	{
	156	return fm7_vram_r(space,offset+0x4000);
	157	}
	158
	159	READ8_HANDLER( fm7_vram5_r )
	160	{
	161	return fm7_vram_r(space,offset+0x5000);
	162	}
	163
	164	READ8_HANDLER( fm7_vram6_r )
	165	{
	166	return fm7_vram_r(space,offset+0x6000);
	167	}
	168
	169	READ8_HANDLER( fm7_vram7_r )
	170	{
	171	return fm7_vram_r(space,offset+0x7000);
	172	}
	173
	174	READ8_HANDLER( fm7_vram8_r )
	175	{
	176	return fm7_vram_r(space,offset+0x8000);
	177	}
	178
	179	READ8_HANDLER( fm7_vram9_r )
	180	{
	181	return fm7_vram_r(space,offset+0x9000);
	182	}
	183
	184	READ8_HANDLER( fm7_vramA_r )
	185	{
	186	return fm7_vram_r(space,offset+0xa000);
	187	}
	188
	189	READ8_HANDLER( fm7_vramB_r )
	190	{
	191	return fm7_vram_r(space,offset+0xb000);
	192	}
	193
	194	WRITE8_HANDLER( fm7_vram0_w )
	195	{
	196	fm7_vram_w(space,offset,data);
	197	}
	198
	199	WRITE8_HANDLER( fm7_vram1_w )
	200	{
	201	fm7_vram_w(space,offset+0x1000,data);
	202	}
	203
	204	WRITE8_HANDLER( fm7_vram2_w )
	205	{
	206	fm7_vram_w(space,offset+0x2000,data);
	207	}
	208
	209	WRITE8_HANDLER( fm7_vram3_w )
	210	{
	211	fm7_vram_w(space,offset+0x3000,data);
	212	}
	213
	214	WRITE8_HANDLER( fm7_vram4_w )
	215	{
	216	fm7_vram_w(space,offset+0x4000,data);
	217	}
	218
	219	WRITE8_HANDLER( fm7_vram5_w )
	220	{
	221	fm7_vram_w(space,offset+0x5000,data);
	222	}
	223
	224	WRITE8_HANDLER( fm7_vram6_w )
	225	{
	226	fm7_vram_w(space,offset+0x6000,data);
	227	}
	228
	229	WRITE8_HANDLER( fm7_vram7_w )
	230	{
	231	fm7_vram_w(space,offset+0x7000,data);
	232	}
	233
	234	WRITE8_HANDLER( fm7_vram8_w )
	235	{
	236	fm7_vram_w(space,offset+0x8000,data);
	237	}
	238
	239	WRITE8_HANDLER( fm7_vram9_w )
	240	{
	241	fm7_vram_w(space,offset+0x9000,data);
	242	}
	243
	244	WRITE8_HANDLER( fm7_vramA_w )
	245	{
	246	fm7_vram_w(space,offset+0xa000,data);
	247	}
	248
	249	WRITE8_HANDLER( fm7_vramB_w )
	250	{
	251	fm7_vram_w(space,offset+0xb000,data);
	252	}
	253
132	254	/*
133	255	*  Sub CPU: I/O port 0xd408
134	256	*
r5082	r5083
155	277	WRITE8_HANDLER( fm7_vram_offset_w )
156	278	{
157	279	UINT16 new_offset = 0;
158
	280
159	281	switch(offset)
160	282	{
161	283	case 0:
162	284	new_offset = (data << 8) | (fm7_video.vram_offset & 0x00ff);
163	285	break;
164	286	case 1:  // low 5 bits are used on FM-77AV and later only
165		new_offset = (fm7_video.vram_offset & 0xff00) | (data & 0xe0);
	287	if(fm7_type == SYS_FM7)
	288	new_offset = (fm7_video.vram_offset & 0xff00) | (data & 0xe0);
	289	else
	290	{
	291	if(fm7_video.fine_offset != 0)
	292	new_offset = (fm7_video.vram_offset & 0xff00) | (data & 0xff);
	293	else
	294	new_offset = (fm7_video.vram_offset & 0xff00) | (data & 0xe0);
	295	}
166	296	break;
167		}
168
	297	}
169	298	fm7_video.vram_offset = new_offset;
170	299	}
171	300
r5082	r5083
267	396	*             bit 4 - busy(0)/ready(1)
268	397	*             bit 2 - VSync status (1 if active?)
269	398	*             bit 0 - RESET
	399	*
	400	*     On write: bits 1-0 - CGROM select (maps to 0xd800)
	401	*               bit 2 - fine offset enable (enables OA4-OA0 bits in VRAM offset)
	402	*             bit 5 - active VRAM page
	403	*             bit 6 - display VRAM page
	404	*             bit 7 - NMI mask register (1=mask)
270	405	*/
271	406	READ8_HANDLER( fm77av_video_flags_r )
272	407	{
r5082	r5083
281	416	return ret;
282	417	}
283	418
	419	WRITE8_HANDLER( fm77av_video_flags_w )
	420	{
	421	fm7_video.cgrom = data & 0x03;
	422	fm7_video.fine_offset = data & 0x04;
	423	}
	424
284	425	/*
285	426	*  Main CPU: port 0xfd12
286	427	*  Sub mode status register  (FM-77AV or later)
r5082	r5083
302	443
303	444	WRITE8_HANDLER( fm77av_sub_modestatus_w )
304	445	{
	446	rectangle rect;
305	447	fm7_video.modestatus = data & 0x40;
	448	if(data & 0x40)
	449	{
	450	rect.min_x = rect.min_y = 0;
	451	rect.max_x = 320-1;
	452	rect.max_y = 200-1;
	453	video_screen_configure(space->machine->primary_screen,320,200,&rect,HZ_TO_ATTOSECONDS(60));
	454	}
	455	else
	456	{
	457	rect.min_x = rect.min_y = 0;
	458	rect.max_x = 640-1;
	459	rect.max_y = 200-1;
	460	video_screen_configure(space->machine->primary_screen,640,200,&rect,HZ_TO_ATTOSECONDS(60));
	461	}
306	462	}
307	463
308	464	/*
r5082	r5083
314	470	*/
315	471	WRITE8_HANDLER( fm77av_sub_bank_w )
316	472	{
317		UINT8* RAM = memory_region(space->machine,"sub");
	473	//   UINT8* RAM = memory_region(space->machine,"sub");
318	474	UINT8* ROM;
319	475
320	476	fm7_video.subrom = data & 0x03;
r5082	r5083
322	478	{
323	479	case 0x00:  // Type C, 640x200 (as used on the FM-7)
324	480	ROM = memory_region(space->machine,"subsys_c");
325		memory_set_bankptr(space->machine,20,ROM);
	481	//   memory_set_bankptr(space->machine,20,ROM);
326	482	memory_set_bankptr(space->machine,21,ROM+0x800);
327	483	logerror("VID: Sub ROM Type C selected\n");
328	484	break;
329	485	case 0x01:  // Type A, 640x200
330	486	ROM = memory_region(space->machine,"subsys_a");
331		memory_set_bankptr(space->machine,20,RAM+0xd800);
	487	//   memory_set_bankptr(space->machine,20,RAM+0xd800);
332	488	memory_set_bankptr(space->machine,21,ROM);
333	489	logerror("VID: Sub ROM Type A selected\n");
334	490	break;
335	491	case 0x02:  // Type B, 320x200
336	492	ROM = memory_region(space->machine,"subsys_b");
337		memory_set_bankptr(space->machine,20,RAM+0xd800);
	493	//   memory_set_bankptr(space->machine,20,RAM+0xd800);
338	494	memory_set_bankptr(space->machine,21,ROM);
339	495	logerror("VID: Sub ROM Type B selected\n");
340	496	break;
341	497	case 0x03:  // CG Font?
342	498	ROM = memory_region(space->machine,"subsyscg");
343		memory_set_bankptr(space->machine,20,RAM+0xd800);
	499	//   memory_set_bankptr(space->machine,20,RAM+0xd800);
344	500	memory_set_bankptr(space->machine,21,ROM);
345	501	logerror("VID: Sub ROM CG selected\n");
346	502	break;
r5082	r5083
358	514	fm7_video.vram_offset = 0x0000;
359	515	fm7_video.sub_reset = 0;
360	516	fm7_video.multi_page = 0;
	517	fm7_video.subrom = 0;
	518	fm7_video.cgrom = 0;
	519	fm7_video.fine_offset = 0;
361	520	}
362	521
363	522	VIDEO_UPDATE( fm7 )
r5082	r5083
369	528	if(fm7_video.crt_enable == 0)
370	529	return 0;
371	530
372		for (y = 0; y < 200; y++)
373		{
374		for (x = 0; x < 80; x++)
	531	if(fm7_video.modestatus & 0x40)  // 320x200 mode
	532	{
	533	for (y = 0; y < 200; y++)
375	534	{
376		if(!(fm7_video.multi_page & 0x40))
377		code_r = fm7_video_ram[0x8000 + ((y*80 + x + fm7_video.vram_offset) & 0x3fff)];
378		if(!(fm7_video.multi_page & 0x20))
379		code_g = fm7_video_ram[0x4000 + ((y*80 + x + fm7_video.vram_offset) & 0x3fff)];
380		if(!(fm7_video.multi_page & 0x10))
381		code_b = fm7_video_ram[0x0000 + ((y*80 + x + fm7_video.vram_offset) & 0x3fff)];
382		for (b = 0; b < 8; b++)
383		{
384		col = (((code_r >> b) & 0x01) ? 4 : 0) + (((code_g >> b) & 0x01) ? 2 : 0) + (((code_b >> b) & 0x01) ? 1 : 0);
385		*BITMAP_ADDR16(bitmap, y,  x*8+(7-b)) =  col;
386		}
387		}
388		}
	535	for (x = 0; x < 40; x++)
	536	{
	537	if(!(fm7_video.multi_page & 0x40))
	538	code_r = fm7_video_ram[0x4000 + ((y*40 + x + fm7_video.vram_offset) & 0x1fff)];
	539	if(!(fm7_video.multi_page & 0x20))
	540	code_g = fm7_video_ram[0x2000 + ((y*40 + x + fm7_video.vram_offset) & 0x1fff)];
	541	if(!(fm7_video.multi_page & 0x10))
	542	code_b = fm7_video_ram[0x0000 + ((y*40 + x + fm7_video.vram_offset) & 0x1fff)];
	543	for (b = 0; b < 8; b++)
	544	{
	545	col = (((code_r >> b) & 0x01) ? 4 : 0) + (((code_g >> b) & 0x01) ? 2 : 0) + (((code_b >> b) & 0x01) ? 1 : 0);
	546	*BITMAP_ADDR16(bitmap, y,  x*8+(7-b)) =  col;
	547	}
	548	}
	549	}
	550	}
	551	else
	552	{
	553	for (y = 0; y < 200; y++)
	554	{
	555	for (x = 0; x < 80; x++)
	556	{
	557	if(!(fm7_video.multi_page & 0x40))
	558	code_r = fm7_video_ram[0x8000 + ((y*80 + x + fm7_video.vram_offset) & 0x3fff)];
	559	if(!(fm7_video.multi_page & 0x20))
	560	code_g = fm7_video_ram[0x4000 + ((y*80 + x + fm7_video.vram_offset) & 0x3fff)];
	561	if(!(fm7_video.multi_page & 0x10))
	562	code_b = fm7_video_ram[0x0000 + ((y*80 + x + fm7_video.vram_offset) & 0x3fff)];
	563	for (b = 0; b < 8; b++)
	564	{
	565	col = (((code_r >> b) & 0x01) ? 4 : 0) + (((code_g >> b) & 0x01) ? 2 : 0) + (((code_b >> b) & 0x01) ? 1 : 0);
	566	*BITMAP_ADDR16(bitmap, y,  x*8+(7-b)) =  col;
	567	}
	568	}
	569	}
	570	}
389	571	return 0;
390	572	}
391	573

src/mess/includes/fm7.h

r5082	r5083
11	11	#define IRQ_FLAG_KEY      0x01
12	12	#define IRQ_FLAG_PRINTER  0x02
13	13	#define IRQ_FLAG_TIMER    0x04
14		#define IRQ_FLAG_UNKNOWN  0x08
	14	#define IRQ_FLAG_OTHER    0x08
15	15	// the following are not read in port 0xfd03
16	16	#define IRQ_FLAG_MFD      0x10
17	17	#define IRQ_FLAG_TXRDY    0x20
r5082	r5083
38	38	UINT8 fm77av_pal_g[4096];
39	39	UINT8 fm77av_pal_b[4096];
40	40	UINT8 subrom;  // currently active sub CPU ROM (AV only)
	41	UINT8 cgrom;  // currently active CGROM (AV only)
41	42	UINT8 modestatus;
42	43	UINT8 multi_page;
	44	UINT8 fine_offset;
43	45	};
44	46
45		void fm7_mmr_refresh(running_machine*);
	47	void fm7_mmr_refresh(const address_space*);
46	48
47	49	READ8_HANDLER( fm7_subintf_r );
48	50	WRITE8_HANDLER( fm7_subintf_w );
r5082	r5083
63	65	WRITE8_HANDLER( fm7_crt_w );
64	66	WRITE8_HANDLER( fm7_vram_offset_w );
65	67	READ8_HANDLER( fm77av_video_flags_r );
	68	WRITE8_HANDLER( fm77av_video_flags_w );
66	69
67	70	WRITE8_HANDLER( fm77av_analog_palette_w );
68	71	WRITE8_HANDLER( fm7_multipage_w );
69	72	READ8_HANDLER( fm7_palette_r );
70	73	WRITE8_HANDLER( fm7_palette_w );
71	74
	75	READ8_HANDLER( fm7_vram0_r );
	76	READ8_HANDLER( fm7_vram1_r );
	77	READ8_HANDLER( fm7_vram2_r );
	78	READ8_HANDLER( fm7_vram3_r );
	79	READ8_HANDLER( fm7_vram4_r );
	80	READ8_HANDLER( fm7_vram5_r );
	81	READ8_HANDLER( fm7_vram6_r );
	82	READ8_HANDLER( fm7_vram7_r );
	83	READ8_HANDLER( fm7_vram8_r );
	84	READ8_HANDLER( fm7_vram9_r );
	85	READ8_HANDLER( fm7_vramA_r );
	86	READ8_HANDLER( fm7_vramB_r );
	87	WRITE8_HANDLER( fm7_vram0_w );
	88	WRITE8_HANDLER( fm7_vram1_w );
	89	WRITE8_HANDLER( fm7_vram2_w );
	90	WRITE8_HANDLER( fm7_vram3_w );
	91	WRITE8_HANDLER( fm7_vram4_w );
	92	WRITE8_HANDLER( fm7_vram5_w );
	93	WRITE8_HANDLER( fm7_vram6_w );
	94	WRITE8_HANDLER( fm7_vram7_w );
	95	WRITE8_HANDLER( fm7_vram8_w );
	96	WRITE8_HANDLER( fm7_vram9_w );
	97	WRITE8_HANDLER( fm7_vramA_w );
	98	WRITE8_HANDLER( fm7_vramB_w );
	99
	100
72	101	VIDEO_START( fm7 );
73	102	VIDEO_UPDATE( fm7 );
74	103	PALETTE_INIT( fm7 );

src/mess/drivers/fm7.c

r5082	r5083
52	52
53	53	UINT8* fm7_video_ram;
54	54	UINT8* shared_ram;
	55	UINT8* fm7_boot_ram;  // Boot RAM (AV only)
	56	UINT8 fm7_type;
55	57	static UINT8 irq_flags;  // active IRQ flags
56	58	static UINT8 irq_mask;  // IRQ mask
57	59	emu_timer* fm7_timer;  // main timer, triggered every 2.0345ms
r5082	r5083
70	72	static UINT8 fdc_drive;
71	73	static UINT8 fdc_irq_flag;
72	74	static UINT8 fdc_drq_flag;
73		static UINT8 fm7_type;
	75	static UINT8 fm77av_ym_irq;
74	76
75	77	struct mmr
76	78	{
r5082	r5083
283	285	if(fm7_type == SYS_FM7)
284	286	memory_set_bankptr(space->machine,1,RAM+0x38000);
285	287	else
286		fm7_mmr_refresh(space->machine);
	288	fm7_mmr_refresh(space);
287	289	logerror("BASIC ROM enabled\n");
288	290	return 0x00;
289	291	}
r5082	r5083
296	298	if(fm7_type == SYS_FM7)
297	299	memory_set_bankptr(space->machine,1,RAM+0x8000);
298	300	else
299		fm7_mmr_refresh(space->machine);
	301	fm7_mmr_refresh(space);
300	302	logerror("BASIC ROM disabled\n");
301	303	}
302	304
r5082	r5083
311	313	if(data & 0x02)
312	314	{
313	315	init_rom_en = 0;
314		fm7_mmr_refresh(space->machine);
	316	fm7_mmr_refresh(space);
315	317	}
316	318	else
317	319	{
318	320	init_rom_en = 1;
319		fm7_mmr_refresh(space->machine);
	321	fm7_mmr_refresh(space);
320	322	}
321	323	}
322	324
r5082	r5083
626	628	return psg_data;
627	629	}
628	630
	631	static WRITE8_HANDLER( fm77av_bootram_w )
	632	{
	633	if(!(fm7_mmr.mode & 0x01))
	634	return;
	635	fm7_boot_ram[offset] = data;
	636	}
	637
629	638	static WRITE8_HANDLER( fm7_psg_data_w )
630	639	{
631	640	psg_data = data;
r5082	r5083
647	656	shared_ram[offset] = data;
648	657	}
649	658
	659	static READ8_HANDLER( fm7_fmirq_r )
	660	{
	661	UINT8 ret = 0xff;
	662
	663	if(fm77av_ym_irq == 0)
	664	ret &= ~0x08;
	665
	666	return ret;
	667	}
	668
650	669	static READ8_HANDLER( fm7_unknown_r )
651	670	{
652	671	// Port 0xFDFC is read by Dig Dug.  Controller port, perhaps?
r5082	r5083
681	700	return 0xff;
682	701	}
683	702
684		static void fm7_update_bank(running_machine* machine, int bank, UINT8 physical)
	703	static void fm7_update_bank(const address_space* space, int bank, UINT8 physical)
685	704	{
686		UINT8* RAM = memory_region(machine,"maincpu");
	705	UINT8* RAM = memory_region(space->machine,"maincpu");
	706	UINT16 size = 0xfff;
687	707
688		if(physical > 0x10 && physical <= 0x1f)
	708	if(bank == 15)
	709	size = 0xbff;
	710
	711	if(physical >= 0x10 && physical <= 0x1b)
689	712	{
690		RAM = memory_region(machine,"sub");
691		memory_set_bankptr(machine,bank+1,RAM+(physical<<12)-0x10000);
	713	switch(physical)
	714	{
	715	case 0x10:
	716	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vram0_r,fm7_vram0_w);
	717	break;
	718	case 0x11:
	719	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vram1_r,fm7_vram1_w);
	720	break;
	721	case 0x12:
	722	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vram2_r,fm7_vram2_w);
	723	break;
	724	case 0x13:
	725	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vram3_r,fm7_vram3_w);
	726	break;
	727	case 0x14:
	728	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vram4_r,fm7_vram4_w);
	729	break;
	730	case 0x15:
	731	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vram5_r,fm7_vram5_w);
	732	break;
	733	case 0x16:
	734	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vram6_r,fm7_vram6_w);
	735	break;
	736	case 0x17:
	737	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vram7_r,fm7_vram7_w);
	738	break;
	739	case 0x18:
	740	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vram8_r,fm7_vram8_w);
	741	break;
	742	case 0x19:
	743	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vram9_r,fm7_vram9_w);
	744	break;
	745	case 0x1a:
	746	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vramA_r,fm7_vramA_w);
	747	break;
	748	case 0x1b:
	749	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,fm7_vramB_r,fm7_vramB_w);
	750	break;
	751	}
	752	//      memory_set_bankptr(space->machine,bank+1,RAM+(physical<<12)-0x10000);
	753	return;
692	754	}
	755	if(physical == 0x1d)
	756	{
	757	// special case - the sub CPU's I/O ports are available on this RAM page
	758	// work RAM
	759	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+0x800,0,0,SMH_BANK(bank+1),SMH_BANK(bank+1));
	760	memory_set_bankptr(space->machine,bank+1,RAM+(physical<<12));
	761	//memory_install_readwrite8_handler(space,(bank*0x1000)+0x380,(bank*0x1000)+0x3ff,0,0,SMH_BANK(bank+1),SMH_BANK(bank+1));
	762	// various sub CPU I/O ports
	763	memory_install_readwrite8_handler(space,(bank*0x1000)+0x409,(bank*0x1000)+0x409,0,0,fm7_vram_access_r,fm7_vram_access_w);
	764	memory_install_readwrite8_handler(space,(bank*0x1000)+0x40a,(bank*0x1000)+0x40a,0,0,fm7_sub_busyflag_r,fm7_sub_busyflag_w);
	765	memory_install_write8_handler(space,(bank*0x1000)+0x40e,(bank*0x1000)+0x40f,0,0,fm7_vram_offset_w);
	766	memory_install_readwrite8_handler(space,(bank*0x1000)+0x430,(bank*0x1000)+0x430,0,0,fm77av_video_flags_r,fm77av_video_flags_w);
	767
	768	// sub monitor CGROM
	769	memory_install_readwrite8_handler(space,(bank*0x1000)+0x800,(bank*0x1000)+size,0,0,SMH_BANK(20),SMH_UNMAP);
	770	RAM = memory_region(space->machine,"subsyscg");
	771	memory_set_bankptr(space->machine,20,RAM+(fm7_video.cgrom*0x800));
	772	return;
	773	}
693	774	if(physical == 0x36 || physical == 0x37)
694	775	{
695	776	if(init_rom_en)
696	777	{
697		RAM = memory_region(machine,"init");
698		memory_set_bankptr(machine,bank+1,RAM+(physical<<12)-0x36000);
	778	RAM = memory_region(space->machine,"init");
	779	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,SMH_BANK(bank+1),SMH_BANK(bank+1));
	780	memory_set_bankptr(space->machine,bank+1,RAM+(physical<<12)-0x36000);
699	781	return;
700	782	}
701	783	}
r5082	r5083
703	785	{
704	786	if(basic_rom_en)
705	787	{
706		RAM = memory_region(machine,"fbasic");
707		memory_set_bankptr(machine,bank+1,RAM+(physical<<12)-0x38000);
	788	RAM = memory_region(space->machine,"fbasic");
	789	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,SMH_BANK(bank+1),SMH_BANK(bank+1));
	790	memory_set_bankptr(space->machine,bank+1,RAM+(physical<<12)-0x38000);
708	791	return;
709	792	}
710	793	}
711
712		memory_set_bankptr(machine,bank+1,RAM+(physical<<12));
	794	memory_install_readwrite8_handler(space,bank*0x1000,(bank*0x1000)+size,0,0,SMH_BANK(bank+1),SMH_BANK(bank+1));
	795	memory_set_bankptr(space->machine,bank+1,RAM+(physical<<12));
713	796	}
714	797
715		void fm7_mmr_refresh(running_machine* machine)
	798	void fm7_mmr_refresh(const address_space* space)
716	799	{
717	800	int x;
718	801
719	802	if(fm7_mmr.enabled)
720	803	{
721	804	for(x=0;x<16;x++)
722		fm7_update_bank(machine,x,fm7_mmr.bank_addr[fm7_mmr.segment][x]);
	805	fm7_update_bank(space,x,fm7_mmr.bank_addr[fm7_mmr.segment][x]);
723	806	}
724	807	else
725	808	{
726	809	// when MMR is disabled, 0x30000-0x3ffff is banked in
727	810	for(x=0;x<16;x++)
728		fm7_update_bank(machine,x,0x30+x);
	811	fm7_update_bank(space,x,0x30+x);
729	812	}
730	813	}
731	814
r5082	r5083
735	818	{
736	819	fm7_mmr.bank_addr[fm7_mmr.segment][offset] = data;
737	820	if(fm7_mmr.enabled)
738		fm7_update_bank(space->machine,offset,data);
	821	fm7_update_bank(space,offset,data);
739	822	logerror("MMR: Segment %i, bank %i, set to  0x%02x\n",fm7_mmr.segment,offset,data);
740	823	return;
741	824	}
r5082	r5083
743	826	{
744	827	case 0x10:
745	828	fm7_mmr.segment = data & 0x07;
746		fm7_mmr_refresh(space->machine);
	829	fm7_mmr_refresh(space);
747	830	logerror("MMR: Active segment set to %i\n",fm7_mmr.segment);
748	831	break;
749	832	case 0x12:
r5082	r5083
753	836	case 0x13:
754	837	fm7_mmr.mode = data;
755	838	fm7_mmr.enabled = data & 0x80;
756		fm7_mmr_refresh(space->machine);
	839	fm7_mmr_refresh(space);
757	840	logerror("MMR: Mode register set to %02x\n",data);
758	841	break;
759	842	}
r5082	r5083
851	934	return -1;
852	935	}
853	936
	937	void fm77av_fmirq(const device_config* device,int irq)
	938	{
	939	if(irq == 1)
	940	{
	941	if(irq_mask & IRQ_FLAG_OTHER)
	942	{
	943	irq_flags |= IRQ_FLAG_OTHER;
	944	cputag_set_input_line(device->machine,"maincpu",M6809_IRQ_LINE,ASSERT_LINE);
	945	}
	946	fm77av_ym_irq = 1;
	947	}
	948	else
	949	{
	950	//      cputag_set_input_line(device->machine,"maincpu",M6809_IRQ_LINE,CLEAR_LINE);
	951	fm77av_ym_irq = 0;
	952	}
	953	}
	954
854	955	/*
855	956	0000 - 7FFF: (RAM) BASIC working area, user's area
856	957	8000 - FBFF: (ROM) F-BASIC ROM, extra user RAM
r5082	r5083
953	1054	AM_RANGE(0xfd14,0xfd14) AM_READ(fm7_unknown_r)
954	1055	AM_RANGE(0xfd15,0xfd15) AM_DEVREADWRITE("ym",ym2203_status_port_r,ym2203_control_port_w)
955	1056	AM_RANGE(0xfd16,0xfd16) AM_DEVREADWRITE("ym",ym2203_read_port_r,ym2203_write_port_w)
956		AM_RANGE(0xfd17,0xfd17) AM_READ(fm7_unknown_r)
	1057	AM_RANGE(0xfd17,0xfd17) AM_READ(fm7_fmirq_r)
957	1058	AM_RANGE(0xfd18,0xfd1f) AM_READWRITE(fm7_fdc_r,fm7_fdc_w)
958	1059	AM_RANGE(0xfd24,0xfd2f) AM_READ(fm7_unknown_r)
959	1060	AM_RANGE(0xfd30,0xfd34) AM_WRITE(fm77av_analog_palette_w)
r5082	r5083
964	1065	AM_RANGE(0xfd80,0xfd93) AM_READWRITE(fm7_mmr_r,fm7_mmr_w)
965	1066	AM_RANGE(0xfd94,0xfdff) AM_READ(fm7_unknown_r)
966	1067	// Boot ROM (RAM on FM77AV and later)
967		AM_RANGE(0xfe00,0xffef) AM_RAM
	1068	AM_RANGE(0xfe00,0xffef) AM_RAM_WRITE(fm77av_bootram_w) AM_BASE(&fm7_boot_ram)
968	1069	AM_RANGE(0xfff0,0xffff) AM_READWRITE(vector_r,vector_w)
969	1070	ADDRESS_MAP_END
970	1071
971	1072	static ADDRESS_MAP_START( fm77av_sub_mem, ADDRESS_SPACE_PROGRAM, 8 )
972	1073	AM_RANGE(0x0000,0xbfff) AM_READWRITE(fm7_vram_r,fm7_vram_w) // VRAM
973		AM_RANGE(0xc000,0xcfff) AM_RAM // Console RAM
974		AM_RANGE(0xd000,0xd37f) AM_RAM // Work RAM
	1074	AM_RANGE(0xc000,0xcfff) AM_RAM AM_REGION("maincpu",0x1c000) // Console RAM
	1075	AM_RANGE(0xd000,0xd37f) AM_RAM AM_REGION("maincpu",0x1d000) // Work RAM
975	1076	AM_RANGE(0xd380,0xd3ff) AM_RAM AM_BASE(&shared_ram)
976	1077	// I/O space (D400-D7FF)
977	1078	AM_RANGE(0xd400,0xd401) AM_READ(fm7_sub_keyboard_r)
r5082	r5083
981	1082	AM_RANGE(0xd409,0xd409) AM_READWRITE(fm7_vram_access_r,fm7_vram_access_w)
982	1083	AM_RANGE(0xd40a,0xd40a) AM_READWRITE(fm7_sub_busyflag_r,fm7_sub_busyflag_w)
983	1084	AM_RANGE(0xd40e,0xd40f) AM_WRITE(fm7_vram_offset_w)
984		AM_RANGE(0xd430,0xd430) AM_READ(fm77av_video_flags_r)
	1085	AM_RANGE(0xd430,0xd430) AM_READWRITE(fm77av_video_flags_r,fm77av_video_flags_w)
	1086	AM_RANGE(0xd500,0xd7ff) AM_RAM AM_REGION("maincpu",0x1d500) // Work RAM
985	1087	AM_RANGE(0xd800,0xdfff) AM_ROMBANK(20)
986	1088	AM_RANGE(0xe000,0xffff) AM_ROMBANK(21)
987	1089	ADDRESS_MAP_END
r5082	r5083
1157	1259	// last part of Initiate ROM is visible at the end of RAM too (interrupt vectors)
1158	1260	memcpy(RAM+0xfff0,ROM+0x1ff0,16);
1159	1261
1160		RAM = memory_region(machine,"subsys_c");
1161	1262	fm7_video.subrom = 0;  // default sub CPU ROM is type C.
	1263	RAM = memory_region(machine,"subsyscg");
1162	1264	memory_set_bankptr(machine,20,RAM);
	1265	RAM = memory_region(machine,"subsys_c");
1163	1266	memory_set_bankptr(machine,21,RAM+0x800);
1164	1267
1165	1268	fm7_type = SYS_FM77AV;
r5082	r5083
1192	1295	fm7_mmr.mode = 0;
1193	1296	fm7_mmr.segment = 0;
1194	1297	fm7_mmr.enabled = 0;
1195
	1298	fm77av_ym_irq = 0;
1196	1299	// set boot mode (FM-7 only, AV and later has boot RAM instead)
1197	1300	if(fm7_type == SYS_FM7)
1198	1301	{
r5082	r5083
1207	1310	}
1208	1311	if(fm7_type != SYS_FM7)  // set default RAM banks
1209	1312	{
1210		fm7_mmr_refresh(machine);
	1313	fm7_mmr_refresh(cpu_get_address_space(cputag_get_cpu(machine,"maincpu"),ADDRESS_SPACE_PROGRAM));
1211	1314	}
1212	1315	}
1213	1316
r5082	r5083
1237	1340	DEVCB_NULL,               /* portA write */
1238	1341	DEVCB_NULL               /* portB write */
1239	1342	},
1240		NULL  // TODO
	1343	fm77av_fmirq
1241	1344	};
1242	1345
1243	1346	static const cassette_config fm7_cassette_config =

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